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Commit | Line | Data |
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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
a5544970 | 2 | ;; Copyright (C) 1999-2019 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
da0dcab1 DV |
73 | ; The right hand side of an setmem |
74 | UNSPEC_REPLICATE_BYTE | |
75 | ||
10bbf137 | 76 | ; GOT/PLT and lt-relative accesses |
30a49b23 | 77 | UNSPEC_LTREL_OFFSET |
30a49b23 AK |
78 | UNSPEC_POOL_OFFSET |
79 | UNSPEC_GOTENT | |
80 | UNSPEC_GOT | |
81 | UNSPEC_GOTOFF | |
82 | UNSPEC_PLT | |
83 | UNSPEC_PLTOFF | |
fd7643fb UW |
84 | |
85 | ; Literal pool | |
30a49b23 AK |
86 | UNSPEC_RELOAD_BASE |
87 | UNSPEC_MAIN_BASE | |
88 | UNSPEC_LTREF | |
89 | UNSPEC_INSN | |
90 | UNSPEC_EXECUTE | |
84b4c7b5 | 91 | UNSPEC_EXECUTE_JUMP |
fd7643fb | 92 | |
1a8c13b3 | 93 | ; Atomic Support |
30a49b23 | 94 | UNSPEC_MB |
78ce265b | 95 | UNSPEC_MOVA |
1a8c13b3 | 96 | |
fd7643fb | 97 | ; TLS relocation specifiers |
30a49b23 AK |
98 | UNSPEC_TLSGD |
99 | UNSPEC_TLSLDM | |
100 | UNSPEC_NTPOFF | |
101 | UNSPEC_DTPOFF | |
102 | UNSPEC_GOTNTPOFF | |
103 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
104 | |
105 | ; TLS support | |
30a49b23 AK |
106 | UNSPEC_TLSLDM_NTPOFF |
107 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
108 | |
109 | ; String Functions | |
30a49b23 AK |
110 | UNSPEC_SRST |
111 | UNSPEC_MVST | |
638e37c2 | 112 | |
7b8acc34 | 113 | ; Stack Smashing Protector |
30a49b23 AK |
114 | UNSPEC_SP_SET |
115 | UNSPEC_SP_TEST | |
85dae55a | 116 | |
4cb4721f MK |
117 | ; Split stack support |
118 | UNSPEC_STACK_CHECK | |
119 | ||
638e37c2 | 120 | ; Test Data Class (TDC) |
30a49b23 | 121 | UNSPEC_TDC_INSN |
65b1d8ea AK |
122 | |
123 | ; Population Count | |
30a49b23 AK |
124 | UNSPEC_POPCNT |
125 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
126 | |
127 | ; Load FP Integer | |
128 | UNSPEC_FPINT_FLOOR | |
129 | UNSPEC_FPINT_BTRUNC | |
130 | UNSPEC_FPINT_ROUND | |
131 | UNSPEC_FPINT_CEIL | |
132 | UNSPEC_FPINT_NEARBYINT | |
133 | UNSPEC_FPINT_RINT | |
085261c8 | 134 | |
3af82a61 AK |
135 | UNSPEC_LCBB |
136 | ||
085261c8 | 137 | ; Vector |
3af82a61 AK |
138 | UNSPEC_VEC_SMULT_HI |
139 | UNSPEC_VEC_UMULT_HI | |
140 | UNSPEC_VEC_SMULT_LO | |
085261c8 AK |
141 | UNSPEC_VEC_SMULT_EVEN |
142 | UNSPEC_VEC_UMULT_EVEN | |
143 | UNSPEC_VEC_SMULT_ODD | |
144 | UNSPEC_VEC_UMULT_ODD | |
3af82a61 AK |
145 | |
146 | UNSPEC_VEC_VMAL | |
147 | UNSPEC_VEC_VMAH | |
148 | UNSPEC_VEC_VMALH | |
149 | UNSPEC_VEC_VMAE | |
150 | UNSPEC_VEC_VMALE | |
151 | UNSPEC_VEC_VMAO | |
152 | UNSPEC_VEC_VMALO | |
153 | ||
154 | UNSPEC_VEC_GATHER | |
155 | UNSPEC_VEC_EXTRACT | |
156 | UNSPEC_VEC_INSERT_AND_ZERO | |
157 | UNSPEC_VEC_LOAD_BNDRY | |
085261c8 | 158 | UNSPEC_VEC_LOAD_LEN |
76794c52 | 159 | UNSPEC_VEC_LOAD_LEN_R |
3af82a61 AK |
160 | UNSPEC_VEC_MERGEH |
161 | UNSPEC_VEC_MERGEL | |
162 | UNSPEC_VEC_PACK | |
163 | UNSPEC_VEC_PACK_SATURATE | |
164 | UNSPEC_VEC_PACK_SATURATE_CC | |
165 | UNSPEC_VEC_PACK_SATURATE_GENCC | |
166 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE | |
167 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC | |
168 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC | |
169 | UNSPEC_VEC_PERM | |
170 | UNSPEC_VEC_PERMI | |
171 | UNSPEC_VEC_EXTEND | |
172 | UNSPEC_VEC_STORE_LEN | |
76794c52 AK |
173 | UNSPEC_VEC_STORE_LEN_R |
174 | UNSPEC_VEC_VBPERM | |
3af82a61 AK |
175 | UNSPEC_VEC_UNPACKH |
176 | UNSPEC_VEC_UNPACKH_L | |
177 | UNSPEC_VEC_UNPACKL | |
178 | UNSPEC_VEC_UNPACKL_L | |
179 | UNSPEC_VEC_ADDC | |
3af82a61 AK |
180 | UNSPEC_VEC_ADDE_U128 |
181 | UNSPEC_VEC_ADDEC_U128 | |
182 | UNSPEC_VEC_AVG | |
183 | UNSPEC_VEC_AVGU | |
184 | UNSPEC_VEC_CHECKSUM | |
185 | UNSPEC_VEC_GFMSUM | |
186 | UNSPEC_VEC_GFMSUM_128 | |
187 | UNSPEC_VEC_GFMSUM_ACCUM | |
188 | UNSPEC_VEC_GFMSUM_ACCUM_128 | |
189 | UNSPEC_VEC_SET | |
190 | ||
191 | UNSPEC_VEC_VSUMG | |
192 | UNSPEC_VEC_VSUMQ | |
193 | UNSPEC_VEC_VSUM | |
194 | UNSPEC_VEC_RL_MASK | |
195 | UNSPEC_VEC_SLL | |
196 | UNSPEC_VEC_SLB | |
197 | UNSPEC_VEC_SLDB | |
198 | UNSPEC_VEC_SRAL | |
199 | UNSPEC_VEC_SRAB | |
200 | UNSPEC_VEC_SRL | |
201 | UNSPEC_VEC_SRLB | |
202 | ||
3af82a61 | 203 | UNSPEC_VEC_SUBC |
3af82a61 AK |
204 | UNSPEC_VEC_SUBE_U128 |
205 | UNSPEC_VEC_SUBEC_U128 | |
206 | ||
207 | UNSPEC_VEC_TEST_MASK | |
208 | ||
209 | UNSPEC_VEC_VFAE | |
210 | UNSPEC_VEC_VFAECC | |
211 | ||
212 | UNSPEC_VEC_VFEE | |
213 | UNSPEC_VEC_VFEECC | |
085261c8 AK |
214 | UNSPEC_VEC_VFENE |
215 | UNSPEC_VEC_VFENECC | |
3af82a61 AK |
216 | |
217 | UNSPEC_VEC_VISTR | |
218 | UNSPEC_VEC_VISTRCC | |
219 | ||
220 | UNSPEC_VEC_VSTRC | |
221 | UNSPEC_VEC_VSTRCCC | |
222 | ||
223 | UNSPEC_VEC_VCDGB | |
224 | UNSPEC_VEC_VCDLGB | |
225 | ||
226 | UNSPEC_VEC_VCGDB | |
227 | UNSPEC_VEC_VCLGDB | |
228 | ||
76794c52 | 229 | UNSPEC_VEC_VFI |
3af82a61 | 230 | |
76794c52 AK |
231 | UNSPEC_VEC_VFLL ; vector fp load lengthened |
232 | UNSPEC_VEC_VFLR ; vector fp load rounded | |
3af82a61 | 233 | |
76794c52 AK |
234 | UNSPEC_VEC_VFTCI |
235 | UNSPEC_VEC_VFTCICC | |
236 | ||
237 | UNSPEC_VEC_MSUM | |
238 | ||
239 | UNSPEC_VEC_VFMIN | |
240 | UNSPEC_VEC_VFMAX | |
085261c8 | 241 | ]) |
fd3cd001 UW |
242 | |
243 | ;; | |
244 | ;; UNSPEC_VOLATILE usage | |
245 | ;; | |
246 | ||
30a49b23 AK |
247 | (define_c_enum "unspecv" [ |
248 | ; Blockage | |
249 | UNSPECV_BLOCKAGE | |
10bbf137 | 250 | |
2f7e5a0d | 251 | ; TPF Support |
30a49b23 AK |
252 | UNSPECV_TPF_PROLOGUE |
253 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 254 | |
10bbf137 | 255 | ; Literal pool |
30a49b23 AK |
256 | UNSPECV_POOL |
257 | UNSPECV_POOL_SECTION | |
258 | UNSPECV_POOL_ALIGN | |
259 | UNSPECV_POOL_ENTRY | |
260 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
261 | |
262 | ; TLS support | |
30a49b23 | 263 | UNSPECV_SET_TP |
e0374221 AS |
264 | |
265 | ; Atomic Support | |
30a49b23 AK |
266 | UNSPECV_CAS |
267 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 | 268 | |
aad98a61 AK |
269 | ; Non-branch nops used for compare-and-branch adjustments on z10 |
270 | UNSPECV_NOP_LR_0 | |
271 | UNSPECV_NOP_LR_1 | |
272 | ||
f8af0e30 DV |
273 | ; Hotpatching (unremovable NOPs) |
274 | UNSPECV_NOP_2_BYTE | |
275 | UNSPECV_NOP_4_BYTE | |
276 | UNSPECV_NOP_6_BYTE | |
277 | ||
5a3fe9b6 AK |
278 | ; Transactional Execution support |
279 | UNSPECV_TBEGIN | |
2561451d | 280 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
281 | UNSPECV_TBEGINC |
282 | UNSPECV_TEND | |
283 | UNSPECV_TABORT | |
284 | UNSPECV_ETND | |
285 | UNSPECV_NTSTG | |
286 | UNSPECV_PPA | |
004f64e1 AK |
287 | |
288 | ; Set and get floating point control register | |
289 | UNSPECV_SFPC | |
290 | UNSPECV_EFPC | |
4cb4721f MK |
291 | |
292 | ; Split stack support | |
293 | UNSPECV_SPLIT_STACK_CALL | |
294 | UNSPECV_SPLIT_STACK_DATA | |
539405d5 AK |
295 | |
296 | UNSPECV_OSC_BREAK | |
fd3cd001 UW |
297 | ]) |
298 | ||
ae156f85 AS |
299 | ;; |
300 | ;; Registers | |
301 | ;; | |
302 | ||
35dd9a0e AK |
303 | ; Registers with special meaning |
304 | ||
ae156f85 AS |
305 | (define_constants |
306 | [ | |
307 | ; Sibling call register. | |
308 | (SIBCALL_REGNUM 1) | |
84b4c7b5 AK |
309 | ; A call-clobbered reg which can be used in indirect branch thunks |
310 | (INDIRECT_BRANCH_THUNK_REGNUM 1) | |
ae156f85 AS |
311 | ; Literal pool base register. |
312 | (BASE_REGNUM 13) | |
313 | ; Return address register. | |
314 | (RETURN_REGNUM 14) | |
82c6f58a AK |
315 | ; Stack pointer register. |
316 | (STACK_REGNUM 15) | |
ae156f85 AS |
317 | ; Condition code register. |
318 | (CC_REGNUM 33) | |
f4aa3848 | 319 | ; Thread local storage pointer register. |
ae156f85 AS |
320 | (TP_REGNUM 36) |
321 | ]) | |
322 | ||
35dd9a0e AK |
323 | ; Hardware register names |
324 | ||
325 | (define_constants | |
326 | [ | |
327 | ; General purpose registers | |
328 | (GPR0_REGNUM 0) | |
af344a30 | 329 | (GPR1_REGNUM 1) |
82379bdf AK |
330 | (GPR2_REGNUM 2) |
331 | (GPR6_REGNUM 6) | |
35dd9a0e AK |
332 | ; Floating point registers. |
333 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
334 | (FPR1_REGNUM 20) |
335 | (FPR2_REGNUM 17) | |
336 | (FPR3_REGNUM 21) | |
337 | (FPR4_REGNUM 18) | |
338 | (FPR5_REGNUM 22) | |
339 | (FPR6_REGNUM 19) | |
340 | (FPR7_REGNUM 23) | |
341 | (FPR8_REGNUM 24) | |
342 | (FPR9_REGNUM 28) | |
343 | (FPR10_REGNUM 25) | |
344 | (FPR11_REGNUM 29) | |
345 | (FPR12_REGNUM 26) | |
346 | (FPR13_REGNUM 30) | |
347 | (FPR14_REGNUM 27) | |
348 | (FPR15_REGNUM 31) | |
085261c8 AK |
349 | (VR0_REGNUM 16) |
350 | (VR16_REGNUM 38) | |
351 | (VR23_REGNUM 45) | |
352 | (VR24_REGNUM 46) | |
353 | (VR31_REGNUM 53) | |
35dd9a0e AK |
354 | ]) |
355 | ||
ae8e301e AK |
356 | ; Rounding modes for binary floating point numbers |
357 | (define_constants | |
358 | [(BFP_RND_CURRENT 0) | |
359 | (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1) | |
360 | (BFP_RND_PREP_FOR_SHORT_PREC 3) | |
361 | (BFP_RND_NEAREST_TIE_TO_EVEN 4) | |
362 | (BFP_RND_TOWARD_0 5) | |
363 | (BFP_RND_TOWARD_INF 6) | |
364 | (BFP_RND_TOWARD_MINF 7)]) | |
365 | ||
366 | ; Rounding modes for decimal floating point numbers | |
367 | ; 1-7 were introduced with the floating point extension facility | |
368 | ; available with z196 | |
369 | ; With these rounding modes (1-7) a quantum exception might occur | |
370 | ; which is suppressed for the other modes. | |
371 | (define_constants | |
372 | [(DFP_RND_CURRENT 0) | |
373 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1) | |
374 | (DFP_RND_CURRENT_QUANTEXC 2) | |
375 | (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3) | |
376 | (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4) | |
377 | (DFP_RND_TOWARD_0_QUANTEXC 5) | |
378 | (DFP_RND_TOWARD_INF_QUANTEXC 6) | |
379 | (DFP_RND_TOWARD_MINF_QUANTEXC 7) | |
380 | (DFP_RND_NEAREST_TIE_TO_EVEN 8) | |
381 | (DFP_RND_TOWARD_0 9) | |
382 | (DFP_RND_TOWARD_INF 10) | |
383 | (DFP_RND_TOWARD_MINF 11) | |
384 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12) | |
385 | (DFP_RND_NEAREST_TIE_TO_0 13) | |
386 | (DFP_RND_AWAY_FROM_0 14) | |
387 | (DFP_RND_PREP_FOR_SHORT_PREC 15)]) | |
388 | ||
35dd9a0e AK |
389 | ;; |
390 | ;; PFPO GPR0 argument format | |
391 | ;; | |
392 | ||
393 | (define_constants | |
394 | [ | |
395 | ; PFPO operation type | |
396 | (PFPO_CONVERT 0x1000000) | |
397 | ; PFPO operand types | |
398 | (PFPO_OP_TYPE_SF 0x5) | |
399 | (PFPO_OP_TYPE_DF 0x6) | |
400 | (PFPO_OP_TYPE_TF 0x7) | |
401 | (PFPO_OP_TYPE_SD 0x8) | |
402 | (PFPO_OP_TYPE_DD 0x9) | |
403 | (PFPO_OP_TYPE_TD 0xa) | |
404 | ; Bitposition of operand types | |
405 | (PFPO_OP0_TYPE_SHIFT 16) | |
406 | (PFPO_OP1_TYPE_SHIFT 8) | |
ced8d882 AK |
407 | ; Decide whether current DFP or BFD rounding mode should be used |
408 | ; for the conversion. | |
409 | (PFPO_RND_MODE_DFP 0) | |
410 | (PFPO_RND_MODE_BFP 1) | |
35dd9a0e AK |
411 | ]) |
412 | ||
291a9e98 AK |
413 | ;; PPA constants |
414 | ||
415 | ; Immediate values which can be used as the third operand to the | |
416 | ; perform processor assist instruction | |
417 | ||
418 | (define_constants | |
419 | [(PPA_TX_ABORT 1) | |
420 | (PPA_OOO_BARRIER 15)]) | |
421 | ||
5a3fe9b6 AK |
422 | ; Immediate operands for tbegin and tbeginc |
423 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
424 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 425 | |
29a74354 UW |
426 | ;; Instruction operand type as used in the Principles of Operation. |
427 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 428 | |
29a74354 | 429 | (define_attr "op_type" |
76794c52 | 430 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX,VSI" |
b628bd8e | 431 | (const_string "NN")) |
9db1d521 | 432 | |
29a74354 | 433 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 434 | |
077dab3b | 435 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 436 | cs,vs,store,sem,idiv, |
ed0e512a | 437 | imulhi,imulsi,imuldi, |
2cdece44 | 438 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
439 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
440 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 441 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 442 | fmadddf,fmaddsf, |
9381e3f1 WG |
443 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
444 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
445 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
446 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
447 | ftoidfp, other" | |
29a74354 UW |
448 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
449 | (eq_attr "op_type" "SS") (const_string "cs")] | |
450 | (const_string "integer"))) | |
9db1d521 | 451 | |
29a74354 UW |
452 | ;; Another attribute used for scheduling purposes: |
453 | ;; agen: Instruction uses the address generation unit | |
454 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
455 | |
456 | (define_attr "atype" "agen,reg" | |
62d3f261 | 457 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") |
0101708c AS |
458 | (const_string "reg") |
459 | (const_string "agen"))) | |
9db1d521 | 460 | |
9381e3f1 WG |
461 | ;; Properties concerning Z10 execution grouping and value forwarding. |
462 | ;; z10_super: instruction is superscalar. | |
463 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
464 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
465 | ;; target register. It can forward this value to a second instruction that reads | |
466 | ;; the same register if that second instruction is issued in the same group. | |
467 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
468 | ;; instruction in the S pipe writes to the register, then the T instruction | |
469 | ;; can immediately read the new value. | |
470 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
471 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
472 | ;; |
473 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
474 | ||
475 | ||
476 | (define_attr "z10prop" "none, | |
477 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
478 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
479 | z10_rec, | |
480 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 481 | z10_c" |
9381e3f1 WG |
482 | (const_string "none")) |
483 | ||
65b1d8ea AK |
484 | ;; Properties concerning Z196 decoding |
485 | ;; z196_alone: must group alone | |
486 | ;; z196_end: ends a group | |
487 | ;; z196_cracked: instruction is cracked or expanded | |
488 | (define_attr "z196prop" "none, | |
489 | z196_alone, z196_ends, | |
490 | z196_cracked" | |
491 | (const_string "none")) | |
9381e3f1 | 492 | |
84b4c7b5 AK |
493 | ; mnemonics which only get defined through if_then_else currently |
494 | ; don't get added to the list values automatically and hence need to | |
495 | ; be listed here. | |
8cc6307c | 496 | (define_attr "mnemonic" "b,bas,basr,bc,bcr_flush,unknown" (const_string "unknown")) |
22ac2c2f | 497 | |
9db1d521 HP |
498 | ;; Length in bytes. |
499 | ||
500 | (define_attr "length" "" | |
62d3f261 AK |
501 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
502 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] | |
b628bd8e | 503 | (const_int 6))) |
9db1d521 | 504 | |
29a74354 UW |
505 | |
506 | ;; Processor type. This attribute must exactly match the processor_type | |
52d4aa4f | 507 | ;; enumeration in s390.h. |
29a74354 | 508 | |
e9e8efc9 | 509 | (define_attr "cpu" "z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,z14" |
90c6fd8a | 510 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 511 | |
b5e0425c | 512 | (define_attr "cpu_facility" |
e9e8efc9 | 513 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,z14,vxe" |
3af8e996 AK |
514 | (const_string "standard")) |
515 | ||
516 | (define_attr "enabled" "" | |
517 | (cond [(eq_attr "cpu_facility" "standard") | |
518 | (const_int 1) | |
519 | ||
520 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 521 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
522 | (const_int 1) |
523 | ||
524 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 525 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
526 | (const_int 1) |
527 | ||
528 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 529 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
530 | (const_int 1) |
531 | ||
532 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 533 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
534 | (const_int 1) |
535 | ||
536 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 537 | (match_test "TARGET_DFP")) |
93538e8e AK |
538 | (const_int 1) |
539 | ||
8cc6307c | 540 | (eq_attr "cpu_facility" "cpu_zarch") |
b5e0425c AK |
541 | (const_int 1) |
542 | ||
93538e8e | 543 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 544 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
545 | (const_int 1) |
546 | ||
547 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 548 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
549 | (const_int 1) |
550 | ||
551 | (and (eq_attr "cpu_facility" "zEC12") | |
552 | (match_test "TARGET_ZEC12")) | |
55ac540c AK |
553 | (const_int 1) |
554 | ||
285363a1 | 555 | (and (eq_attr "cpu_facility" "vx") |
55ac540c | 556 | (match_test "TARGET_VX")) |
bf749919 DV |
557 | (const_int 1) |
558 | ||
559 | (and (eq_attr "cpu_facility" "z13") | |
560 | (match_test "TARGET_Z13")) | |
561 | (const_int 1) | |
6654e96f | 562 | |
e9e8efc9 AK |
563 | (and (eq_attr "cpu_facility" "z14") |
564 | (match_test "TARGET_Z14")) | |
6654e96f AK |
565 | (const_int 1) |
566 | ||
567 | (and (eq_attr "cpu_facility" "vxe") | |
568 | (match_test "TARGET_VXE")) | |
569 | (const_int 1) | |
bf749919 | 570 | ] |
3af8e996 AK |
571 | (const_int 0))) |
572 | ||
14cfceb7 IL |
573 | ;; Whether an instruction supports relative long addressing. |
574 | ;; Currently this corresponds to RIL-b and RIL-c instruction formats, | |
575 | ;; but having a separate attribute, as opposed to reusing op_type, | |
576 | ;; provides additional flexibility. | |
577 | ||
578 | (define_attr "relative_long" "no,yes" (const_string "no")) | |
579 | ||
52d4aa4f | 580 | ;; Pipeline description for z900. |
29a74354 UW |
581 | (include "2064.md") |
582 | ||
3443392a | 583 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
584 | (include "2084.md") |
585 | ||
9381e3f1 WG |
586 | ;; Pipeline description for z10 |
587 | (include "2097.md") | |
588 | ||
65b1d8ea AK |
589 | ;; Pipeline description for z196 |
590 | (include "2817.md") | |
591 | ||
22ac2c2f AK |
592 | ;; Pipeline description for zEC12 |
593 | (include "2827.md") | |
594 | ||
23902021 AK |
595 | ;; Pipeline description for z13 |
596 | (include "2964.md") | |
597 | ||
0bfc3f69 AS |
598 | ;; Predicates |
599 | (include "predicates.md") | |
600 | ||
cd8dc1f9 WG |
601 | ;; Constraint definitions |
602 | (include "constraints.md") | |
603 | ||
a8ba31f2 EC |
604 | ;; Other includes |
605 | (include "tpf.md") | |
f52c81dd | 606 | |
3abcb3a7 | 607 | ;; Iterators |
f52c81dd | 608 | |
085261c8 AK |
609 | (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) |
610 | ||
3abcb3a7 | 611 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 612 | ;; same template. |
f4aa3848 | 613 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 614 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 HPN |
615 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
616 | (define_mode_iterator BFP [TF DF SF]) | |
617 | (define_mode_iterator DFP [TD DD]) | |
618 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
619 | (define_mode_iterator DSF [DF SF]) | |
620 | (define_mode_iterator SD_SF [SF SD]) | |
621 | (define_mode_iterator DD_DF [DF DD]) | |
622 | (define_mode_iterator TD_TF [TF TD]) | |
623 | ||
3abcb3a7 | 624 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 625 | ;; from the same template. |
9602b6a1 | 626 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 627 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 628 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 629 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 630 | |
3abcb3a7 | 631 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 632 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 633 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 634 | |
78ce265b RH |
635 | ;; These macros refer to the actual word_mode of the configuration. |
636 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
637 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
638 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
639 | ||
6e0d70c9 AK |
640 | ;; Used by the umul pattern to express modes having half the size. |
641 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
642 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
643 | ||
3abcb3a7 | 644 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 645 | ;; the same template. |
3abcb3a7 | 646 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 647 | |
3abcb3a7 | 648 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 649 | ;; same template. |
9602b6a1 | 650 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
78ce265b | 651 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
64c744b9 | 652 | (define_mode_iterator SINT [SI HI QI]) |
342cf42b | 653 | |
3abcb3a7 | 654 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 655 | ;; the same template. |
3abcb3a7 | 656 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 657 | |
d12a76f3 | 658 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
659 | (define_code_iterator IXOR [ior xor]) |
660 | ||
d12a76f3 AK |
661 | ;; This iterator is used to expand the patterns for the nearest |
662 | ;; integer functions. | |
663 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
664 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
665 | UNSPEC_FPINT_NEARBYINT]) | |
666 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
667 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
668 | (UNSPEC_FPINT_ROUND "round") | |
669 | (UNSPEC_FPINT_CEIL "ceil") | |
670 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
671 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
672 | (UNSPEC_FPINT_BTRUNC "5") | |
673 | (UNSPEC_FPINT_ROUND "1") | |
674 | (UNSPEC_FPINT_CEIL "6") | |
675 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
676 | ||
3abcb3a7 HPN |
677 | ;; This iterator and attribute allow to combine most atomic operations. |
678 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 679 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
cf5b43b0 | 680 | (define_code_attr atomic [(and "and") (ior "or") (xor "xor") |
45d18331 | 681 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 682 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 683 | |
f4aa3848 | 684 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
685 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
686 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 687 | |
f4aa3848 AK |
688 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
689 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
690 | ;; SDmode. |
691 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 692 | |
609e7e80 | 693 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
694 | ;; Likewise for "<RXe>". |
695 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
696 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
697 | ||
609e7e80 | 698 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 699 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
700 | ;; dfp variants in a single insn definition. |
701 | ||
62d3f261 AK |
702 | ;; These mode attributes are supposed to be used in the `enabled' insn |
703 | ;; attribute to disable certain alternatives for certain modes. | |
704 | (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")]) | |
705 | (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")]) | |
706 | (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")]) | |
707 | (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") | |
708 | (TD "0") (DD "0") (DD "0") | |
709 | (TI "0") (DI "*") (SI "0")]) | |
2de2b3f9 AK |
710 | (define_mode_attr DF [(TF "0") (DF "*") (SF "0") |
711 | (TD "0") (DD "0") (DD "0") | |
712 | (TI "0") (DI "0") (SI "0")]) | |
713 | (define_mode_attr SF [(TF "0") (DF "0") (SF "*") | |
714 | (TD "0") (DD "0") (DD "0") | |
715 | (TI "0") (DI "0") (SI "0")]) | |
f5905b37 | 716 | |
85dae55a AK |
717 | ;; This attribute is used in the operand constraint list |
718 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
719 | ;; TFmode values are represented by a fp register pair. Since the | |
720 | ;; sign bit instructions only handle single source and target fp registers | |
721 | ;; these instructions can only be used for TFmode values if the source and | |
722 | ;; target operand uses the same fp register. | |
723 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
724 | ||
3abcb3a7 | 725 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
726 | ;; within instruction mnemonics. |
727 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
728 | ||
0387c142 WG |
729 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
730 | ;; modes and to an empty string for bfp modes. | |
731 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
732 | ||
1b48c8cc AS |
733 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
734 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
735 | ;; version only operates on one register. | |
736 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
737 | ||
738 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
739 | ;; version only operates on one register. The DImode version needs an additional | |
740 | ;; register for the assembler output. | |
741 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
742 | |
743 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
744 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
745 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
746 | ||
747 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 748 | ;; pattern itself and the corresponding function calls. |
f337b930 | 749 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
750 | |
751 | ;; This attribute handles differences in the instruction 'type' and will result | |
752 | ;; in "RRE" for DImode and "RR" for SImode. | |
753 | (define_mode_attr E [(DI "E") (SI "")]) | |
754 | ||
3298c037 AK |
755 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
756 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
757 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
758 | ||
8006eaa6 AS |
759 | ;; This attribute handles differences in the instruction 'type' and will result |
760 | ;; in "RSE" for TImode and "RS" for DImode. | |
761 | (define_mode_attr TE [(TI "E") (DI "")]) | |
762 | ||
9a91a21f AS |
763 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
764 | ;; and "lcr" in SImode. | |
765 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 766 | |
3298c037 AK |
767 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
768 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
769 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
770 | ;; variant for long displacements. | |
771 | (define_mode_attr y [(DI "g") (SI "y")]) | |
772 | ||
9602b6a1 | 773 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
774 | ;; and "cds" in DImode. |
775 | (define_mode_attr tg [(TI "g") (DI "")]) | |
776 | ||
78ce265b RH |
777 | ;; In TDI templates, a string like "c<d>sg". |
778 | (define_mode_attr td [(TI "d") (DI "")]) | |
779 | ||
2f8f8434 AS |
780 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
781 | ;; and "cfdbr" in SImode. | |
782 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
783 | ||
65b1d8ea AK |
784 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
785 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
786 | ;; 3 operands shift instructions into the existing patterns. | |
787 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
788 | ||
f52c81dd AS |
789 | ;; ICM mask required to load MODE value into the lowest subreg |
790 | ;; of a SImode register. | |
791 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
792 | ||
f6ee577c AS |
793 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
794 | ;; HImode and "llgc" in QImode. | |
795 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
796 | ||
a1aed706 AS |
797 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
798 | ;; in SImode. | |
799 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
800 | ||
609e7e80 AK |
801 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
802 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
803 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
804 | ||
f52c81dd AS |
805 | ;; Maximum unsigned integer that fits in MODE. |
806 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
807 | ||
75ca1b39 RH |
808 | ;; Start and end field computations for RISBG et al. |
809 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
810 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
811 | ||
2542ef05 RH |
812 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
813 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
576987fc DV |
814 | ;; 64 - bitsize |
815 | (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")]) | |
816 | (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")]) | |
2542ef05 | 817 | |
da0dcab1 DV |
818 | ;; In place of GET_MODE_SIZE (<MODE>mode) |
819 | (define_mode_attr modesize [(DI "8") (SI "4")]) | |
820 | ||
177bc204 RS |
821 | ;; Allow return and simple_return to be defined from a single template. |
822 | (define_code_iterator ANY_RETURN [return simple_return]) | |
823 | ||
6e5b5de8 AK |
824 | |
825 | ||
826 | ; Condition code modes generated by vector fp comparisons. These will | |
827 | ; be used also in single element mode. | |
828 | (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) | |
829 | ; Used with VFCMP to expand part of the mnemonic | |
830 | ; For fp we have a mismatch: eq in the insn name - e in asm | |
831 | (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) | |
a6a2b532 | 832 | (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")]) |
6e5b5de8 | 833 | |
191eb16d AK |
834 | ;; Subst pattern definitions |
835 | (include "subst.md") | |
6e5b5de8 | 836 | |
085261c8 AK |
837 | (include "vector.md") |
838 | ||
9db1d521 HP |
839 | ;; |
840 | ;;- Compare instructions. | |
841 | ;; | |
842 | ||
07893d4f | 843 | ; Test-under-Mask instructions |
9db1d521 | 844 | |
07893d4f | 845 | (define_insn "*tmqi_mem" |
ae156f85 | 846 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
847 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
848 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
849 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 850 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 851 | "@ |
fc0ea003 UW |
852 | tm\t%S0,%b1 |
853 | tmy\t%S0,%b1" | |
9381e3f1 | 854 | [(set_attr "op_type" "SI,SIY") |
3e4be43f | 855 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 856 | (set_attr "z10prop" "z10_super,z10_super")]) |
9db1d521 | 857 | |
05b9aaaa | 858 | (define_insn "*tmdi_reg" |
ae156f85 | 859 | [(set (reg CC_REGNUM) |
f19a9af7 | 860 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 861 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
862 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
863 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 864 | "TARGET_ZARCH |
3ed99cc9 | 865 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
866 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
867 | "@ | |
868 | tmhh\t%0,%i1 | |
869 | tmhl\t%0,%i1 | |
870 | tmlh\t%0,%i1 | |
871 | tmll\t%0,%i1" | |
9381e3f1 WG |
872 | [(set_attr "op_type" "RI") |
873 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
874 | |
875 | (define_insn "*tmsi_reg" | |
ae156f85 | 876 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
877 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
878 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
879 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 880 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
881 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
882 | "@ | |
883 | tmh\t%0,%i1 | |
884 | tml\t%0,%i1" | |
729e750f WG |
885 | [(set_attr "op_type" "RI") |
886 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 887 | |
f52c81dd | 888 | (define_insn "*tm<mode>_full" |
ae156f85 | 889 | [(set (reg CC_REGNUM) |
f52c81dd AS |
890 | (compare (match_operand:HQI 0 "register_operand" "d") |
891 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 892 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 893 | "tml\t%0,<max_uint>" |
729e750f WG |
894 | [(set_attr "op_type" "RI") |
895 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 896 | |
07893d4f | 897 | |
08a5aaa2 | 898 | ; |
07893d4f | 899 | ; Load-and-Test instructions |
08a5aaa2 AS |
900 | ; |
901 | ||
c0220ea4 | 902 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
903 | |
904 | (define_insn "*tstdi_sign" | |
ae156f85 | 905 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
906 | (compare |
907 | (ashiftrt:DI | |
908 | (ashift:DI | |
3e4be43f | 909 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0) |
963fc8d0 AK |
910 | (const_int 32)) (const_int 32)) |
911 | (match_operand:DI 1 "const0_operand" ""))) | |
912 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 913 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 914 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
915 | "ltgfr\t%2,%0 |
916 | ltgf\t%2,%0" | |
917 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
918 | (set_attr "cpu_facility" "*,z10") |
919 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 920 | |
43a09b63 | 921 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 922 | (define_insn "*tst<mode>_extimm" |
ec24698e | 923 | [(set (reg CC_REGNUM) |
3e4be43f | 924 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
925 | (match_operand:GPR 1 "const0_operand" ""))) |
926 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 927 | (match_dup 0))] |
08a5aaa2 | 928 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 929 | "@ |
08a5aaa2 AS |
930 | lt<g>r\t%2,%0 |
931 | lt<g>\t%2,%0" | |
9381e3f1 | 932 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 933 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 934 | |
97160c9b DV |
935 | ; Peephole to combine a load-and-test from volatile memory which combine does |
936 | ; not do. | |
937 | (define_peephole2 | |
938 | [(set (match_operand:GPR 0 "register_operand") | |
939 | (match_operand:GPR 2 "memory_operand")) | |
940 | (set (reg CC_REGNUM) | |
941 | (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))] | |
942 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM | |
943 | && GENERAL_REG_P (operands[0]) | |
34a249bc IL |
944 | && satisfies_constraint_T (operands[2]) |
945 | && !contains_constant_pool_address_p (operands[2])" | |
97160c9b DV |
946 | [(parallel |
947 | [(set (reg:CCS CC_REGNUM) | |
948 | (compare:CCS (match_dup 2) (match_dup 1))) | |
949 | (set (match_dup 0) (match_dup 2))])]) | |
950 | ||
43a09b63 | 951 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 952 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 953 | [(set (reg CC_REGNUM) |
3e4be43f | 954 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
955 | (match_operand:GPR 1 "const0_operand" ""))) |
956 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
957 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 958 | "@ |
08a5aaa2 AS |
959 | lt<g>r\t%0,%0 |
960 | lt<g>\t%2,%0" | |
9381e3f1 | 961 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 962 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 963 | |
07893d4f | 964 | (define_insn "*tstdi" |
ae156f85 | 965 | [(set (reg CC_REGNUM) |
07893d4f UW |
966 | (compare (match_operand:DI 0 "register_operand" "d") |
967 | (match_operand:DI 1 "const0_operand" ""))) | |
968 | (set (match_operand:DI 2 "register_operand" "=d") | |
969 | (match_dup 0))] | |
9602b6a1 | 970 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 971 | "ltgr\t%2,%0" |
9381e3f1 WG |
972 | [(set_attr "op_type" "RRE") |
973 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 974 | |
07893d4f | 975 | (define_insn "*tstsi" |
ae156f85 | 976 | [(set (reg CC_REGNUM) |
d3632d41 | 977 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 978 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 979 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 980 | (match_dup 0))] |
ec24698e | 981 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 982 | "@ |
d40c829f | 983 | ltr\t%2,%0 |
fc0ea003 UW |
984 | icm\t%2,15,%S0 |
985 | icmy\t%2,15,%S0" | |
9381e3f1 | 986 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 987 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 988 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 989 | |
07893d4f | 990 | (define_insn "*tstsi_cconly" |
ae156f85 | 991 | [(set (reg CC_REGNUM) |
d3632d41 | 992 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 993 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 994 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
995 | "s390_match_ccmode(insn, CCSmode)" |
996 | "@ | |
d40c829f | 997 | ltr\t%0,%0 |
fc0ea003 UW |
998 | icm\t%2,15,%S0 |
999 | icmy\t%2,15,%S0" | |
9381e3f1 | 1000 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 1001 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 1002 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
4023fb28 | 1003 | |
08a5aaa2 AS |
1004 | (define_insn "*tstdi_cconly_31" |
1005 | [(set (reg CC_REGNUM) | |
1006 | (compare (match_operand:DI 0 "register_operand" "d") | |
1007 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 1008 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
1009 | "srda\t%0,0" |
1010 | [(set_attr "op_type" "RS") | |
1011 | (set_attr "atype" "reg")]) | |
1012 | ||
43a09b63 | 1013 | ; ltr, ltgr |
08a5aaa2 | 1014 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 1015 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
1016 | (compare (match_operand:GPR 0 "register_operand" "d") |
1017 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 1018 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 1019 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
1020 | [(set_attr "op_type" "RR<E>") |
1021 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 1022 | |
c0220ea4 | 1023 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 1024 | |
f52c81dd | 1025 | (define_insn "*tst<mode>CCT" |
ae156f85 | 1026 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1027 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
1028 | (match_operand:HQI 1 "const0_operand" ""))) | |
1029 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
1030 | (match_dup 0))] |
1031 | "s390_match_ccmode(insn, CCTmode)" | |
1032 | "@ | |
f52c81dd AS |
1033 | icm\t%2,<icm_lo>,%S0 |
1034 | icmy\t%2,<icm_lo>,%S0 | |
1035 | tml\t%0,<max_uint>" | |
9381e3f1 | 1036 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1037 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1038 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 UW |
1039 | |
1040 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 1041 | [(set (reg CC_REGNUM) |
d3632d41 | 1042 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 1043 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 1044 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
1045 | "s390_match_ccmode(insn, CCTmode)" |
1046 | "@ | |
fc0ea003 UW |
1047 | icm\t%2,3,%S0 |
1048 | icmy\t%2,3,%S0 | |
d40c829f | 1049 | tml\t%0,65535" |
9381e3f1 | 1050 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1051 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1052 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 | 1053 | |
3af97654 | 1054 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 1055 | [(set (reg CC_REGNUM) |
d3632d41 | 1056 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
1057 | (match_operand:QI 1 "const0_operand" "")))] |
1058 | "s390_match_ccmode(insn, CCTmode)" | |
1059 | "@ | |
fc0ea003 UW |
1060 | cli\t%S0,0 |
1061 | cliy\t%S0,0 | |
d40c829f | 1062 | tml\t%0,255" |
9381e3f1 | 1063 | [(set_attr "op_type" "SI,SIY,RI") |
3e4be43f | 1064 | (set_attr "cpu_facility" "*,longdisp,*") |
729e750f | 1065 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 1066 | |
f52c81dd | 1067 | (define_insn "*tst<mode>" |
ae156f85 | 1068 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1069 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1070 | (match_operand:HQI 1 "const0_operand" ""))) | |
1071 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
1072 | (match_dup 0))] |
1073 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 1074 | "@ |
f52c81dd AS |
1075 | icm\t%2,<icm_lo>,%S0 |
1076 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1077 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1078 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1079 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 1080 | |
f52c81dd | 1081 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 1082 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1083 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1084 | (match_operand:HQI 1 "const0_operand" ""))) | |
1085 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 1086 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 1087 | "@ |
f52c81dd AS |
1088 | icm\t%2,<icm_lo>,%S0 |
1089 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1090 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1091 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1092 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
d3632d41 | 1093 | |
9db1d521 | 1094 | |
575f7c2b UW |
1095 | ; Compare (equality) instructions |
1096 | ||
1097 | (define_insn "*cmpdi_cct" | |
ae156f85 | 1098 | [(set (reg CC_REGNUM) |
ec24698e | 1099 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
3e4be43f | 1100 | (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))] |
9602b6a1 | 1101 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
1102 | "@ |
1103 | cgr\t%0,%1 | |
f4f41b4e | 1104 | cghi\t%0,%h1 |
ec24698e | 1105 | cgfi\t%0,%1 |
575f7c2b | 1106 | cg\t%0,%1 |
19b63d8e | 1107 | #" |
9381e3f1 WG |
1108 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
1109 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
1110 | |
1111 | (define_insn "*cmpsi_cct" | |
ae156f85 | 1112 | [(set (reg CC_REGNUM) |
ec24698e UW |
1113 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
1114 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 1115 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
1116 | "@ |
1117 | cr\t%0,%1 | |
f4f41b4e | 1118 | chi\t%0,%h1 |
ec24698e | 1119 | cfi\t%0,%1 |
575f7c2b UW |
1120 | c\t%0,%1 |
1121 | cy\t%0,%1 | |
19b63d8e | 1122 | #" |
9381e3f1 | 1123 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
3e4be43f | 1124 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*") |
e3cba5e5 | 1125 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 1126 | |
07893d4f | 1127 | ; Compare (signed) instructions |
4023fb28 | 1128 | |
07893d4f | 1129 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 1130 | [(set (reg CC_REGNUM) |
963fc8d0 | 1131 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f | 1132 | "d,T,b")) |
963fc8d0 | 1133 | (match_operand:DI 0 "register_operand" "d, d,d")))] |
9602b6a1 | 1134 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 1135 | "@ |
d40c829f | 1136 | cgfr\t%0,%1 |
963fc8d0 AK |
1137 | cgf\t%0,%1 |
1138 | cgfrl\t%0,%1" | |
1139 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 1140 | (set_attr "z10prop" "z10_c,*,*") |
14cfceb7 IL |
1141 | (set_attr "type" "*,*,larl") |
1142 | (set_attr "relative_long" "*,*,yes")]) | |
4023fb28 | 1143 | |
9381e3f1 WG |
1144 | |
1145 | ||
07893d4f | 1146 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 1147 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1148 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
1149 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 1150 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 1151 | "@ |
d40c829f | 1152 | ch\t%0,%1 |
963fc8d0 AK |
1153 | chy\t%0,%1 |
1154 | chrl\t%0,%1" | |
1155 | [(set_attr "op_type" "RX,RXY,RIL") | |
3e4be43f | 1156 | (set_attr "cpu_facility" "*,longdisp,z10") |
65b1d8ea | 1157 | (set_attr "type" "*,*,larl") |
14cfceb7 IL |
1158 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked") |
1159 | (set_attr "relative_long" "*,*,yes")]) | |
963fc8d0 AK |
1160 | |
1161 | (define_insn "*cmphi_ccs_z10" | |
1162 | [(set (reg CC_REGNUM) | |
1163 | (compare (match_operand:HI 0 "s_operand" "Q") | |
1164 | (match_operand:HI 1 "immediate_operand" "K")))] | |
1165 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
1166 | "chhsi\t%0,%1" | |
65b1d8ea AK |
1167 | [(set_attr "op_type" "SIL") |
1168 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
1169 | |
1170 | (define_insn "*cmpdi_ccs_signhi_rl" | |
1171 | [(set (reg CC_REGNUM) | |
3e4be43f | 1172 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b")) |
963fc8d0 AK |
1173 | (match_operand:GPR 0 "register_operand" "d,d")))] |
1174 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
1175 | "@ | |
1176 | cgh\t%0,%1 | |
1177 | cghrl\t%0,%1" | |
1178 | [(set_attr "op_type" "RXY,RIL") | |
14cfceb7 IL |
1179 | (set_attr "type" "*,larl") |
1180 | (set_attr "relative_long" "*,yes")]) | |
4023fb28 | 1181 | |
963fc8d0 | 1182 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 1183 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1184 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1185 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
1186 | "d,d,Q, d,d,d,d") | |
1187 | (match_operand:GPR 1 "general_operand" | |
1188 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 1189 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 1190 | "@ |
3298c037 AK |
1191 | c<g>r\t%0,%1 |
1192 | c<g>hi\t%0,%h1 | |
963fc8d0 | 1193 | c<g>hsi\t%0,%h1 |
3298c037 AK |
1194 | c<g>fi\t%0,%1 |
1195 | c<g>\t%0,%1 | |
963fc8d0 AK |
1196 | c<y>\t%0,%1 |
1197 | c<g>rl\t%0,%1" | |
1198 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
3e4be43f | 1199 | (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10") |
9381e3f1 | 1200 | (set_attr "type" "*,*,*,*,*,*,larl") |
14cfceb7 IL |
1201 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super") |
1202 | (set_attr "relative_long" "*,*,*,*,*,*,yes")]) | |
c7453384 | 1203 | |
07893d4f UW |
1204 | |
1205 | ; Compare (unsigned) instructions | |
9db1d521 | 1206 | |
963fc8d0 AK |
1207 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
1208 | [(set (reg CC_REGNUM) | |
1209 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
1210 | "larl_operand" "X"))) | |
1211 | (match_operand:SI 0 "register_operand" "d")))] | |
1212 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1213 | "clhrl\t%0,%1" | |
1214 | [(set_attr "op_type" "RIL") | |
729e750f | 1215 | (set_attr "type" "larl") |
14cfceb7 IL |
1216 | (set_attr "z10prop" "z10_super") |
1217 | (set_attr "relative_long" "yes")]) | |
963fc8d0 AK |
1218 | |
1219 | ; clhrl, clghrl | |
1220 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
1221 | [(set (reg CC_REGNUM) | |
1222 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
1223 | "larl_operand" "X"))) | |
1224 | (match_operand:GPR 0 "register_operand" "d")))] | |
1225 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1226 | "cl<g>hrl\t%0,%1" | |
1227 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1228 | (set_attr "type" "larl") |
14cfceb7 IL |
1229 | (set_attr "z10prop" "z10_super") |
1230 | (set_attr "relative_long" "yes")]) | |
963fc8d0 | 1231 | |
07893d4f | 1232 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 1233 | [(set (reg CC_REGNUM) |
963fc8d0 | 1234 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f UW |
1235 | "d,T,b")) |
1236 | (match_operand:DI 0 "register_operand" "d,d,d")))] | |
9602b6a1 | 1237 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 1238 | "@ |
d40c829f | 1239 | clgfr\t%0,%1 |
963fc8d0 AK |
1240 | clgf\t%0,%1 |
1241 | clgfrl\t%0,%1" | |
1242 | [(set_attr "op_type" "RRE,RXY,RIL") | |
1243 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 | 1244 | (set_attr "type" "*,*,larl") |
14cfceb7 IL |
1245 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super") |
1246 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 1247 | |
07893d4f | 1248 | (define_insn "*cmpdi_ccu" |
ae156f85 | 1249 | [(set (reg CC_REGNUM) |
963fc8d0 | 1250 | (compare (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1251 | "d, d,d,Q,d, Q,BQ") |
963fc8d0 | 1252 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1253 | "d,Op,b,D,T,BQ,Q")))] |
9602b6a1 | 1254 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 1255 | "@ |
d40c829f | 1256 | clgr\t%0,%1 |
ec24698e | 1257 | clgfi\t%0,%1 |
963fc8d0 AK |
1258 | clgrl\t%0,%1 |
1259 | clghsi\t%0,%x1 | |
575f7c2b | 1260 | clg\t%0,%1 |
e221ef54 | 1261 | # |
19b63d8e | 1262 | #" |
963fc8d0 AK |
1263 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
1264 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 | 1265 | (set_attr "type" "*,*,larl,*,*,*,*") |
14cfceb7 IL |
1266 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*") |
1267 | (set_attr "relative_long" "*,*,yes,*,*,*,*")]) | |
9db1d521 | 1268 | |
07893d4f | 1269 | (define_insn "*cmpsi_ccu" |
ae156f85 | 1270 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1271 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1272 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1273 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1274 | "@ |
d40c829f | 1275 | clr\t%0,%1 |
ec24698e | 1276 | clfi\t%0,%o1 |
963fc8d0 AK |
1277 | clrl\t%0,%1 |
1278 | clfhsi\t%0,%x1 | |
d40c829f | 1279 | cl\t%0,%1 |
575f7c2b | 1280 | cly\t%0,%1 |
e221ef54 | 1281 | # |
19b63d8e | 1282 | #" |
963fc8d0 | 1283 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
3e4be43f | 1284 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*") |
9381e3f1 | 1285 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
14cfceb7 IL |
1286 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*") |
1287 | (set_attr "relative_long" "*,*,yes,*,*,*,*,*")]) | |
9db1d521 | 1288 | |
07893d4f | 1289 | (define_insn "*cmphi_ccu" |
ae156f85 | 1290 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1291 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1292 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1293 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1294 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1295 | "@ |
fc0ea003 UW |
1296 | clm\t%0,3,%S1 |
1297 | clmy\t%0,3,%S1 | |
963fc8d0 | 1298 | clhhsi\t%0,%1 |
e221ef54 | 1299 | # |
19b63d8e | 1300 | #" |
963fc8d0 | 1301 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
3e4be43f | 1302 | (set_attr "cpu_facility" "*,longdisp,z10,*,*") |
9381e3f1 | 1303 | (set_attr "z10prop" "*,*,z10_super,*,*")]) |
9db1d521 HP |
1304 | |
1305 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1306 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1307 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1308 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1309 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1310 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1311 | "@ |
fc0ea003 UW |
1312 | clm\t%0,1,%S1 |
1313 | clmy\t%0,1,%S1 | |
1314 | cli\t%S0,%b1 | |
1315 | cliy\t%S0,%b1 | |
e221ef54 | 1316 | # |
19b63d8e | 1317 | #" |
9381e3f1 | 1318 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
3e4be43f | 1319 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*") |
9381e3f1 | 1320 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) |
9db1d521 HP |
1321 | |
1322 | ||
19b63d8e UW |
1323 | ; Block compare (CLC) instruction patterns. |
1324 | ||
1325 | (define_insn "*clc" | |
ae156f85 | 1326 | [(set (reg CC_REGNUM) |
d4f52f0e | 1327 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1328 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1329 | (use (match_operand 2 "const_int_operand" "n"))] | |
1330 | "s390_match_ccmode (insn, CCUmode) | |
1331 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1332 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1333 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1334 | |
1335 | (define_split | |
ae156f85 | 1336 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1337 | (compare (match_operand 0 "memory_operand" "") |
1338 | (match_operand 1 "memory_operand" "")))] | |
1339 | "reload_completed | |
1340 | && s390_match_ccmode (insn, CCUmode) | |
1341 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1342 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1343 | [(parallel | |
1344 | [(set (match_dup 0) (match_dup 1)) | |
1345 | (use (match_dup 2))])] | |
1346 | { | |
1347 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1348 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1349 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1350 | ||
1351 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1352 | operands[0], operands[1]); | |
1353 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1354 | }) | |
1355 | ||
1356 | ||
609e7e80 | 1357 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1358 | |
e325aba2 AK |
1359 | |
1360 | ; load and test instructions turn SNaN into QNaN what is not | |
1361 | ; acceptable if the target will be used afterwards. On the other hand | |
1362 | ; they are quite convenient for implementing comparisons with 0.0. So | |
1363 | ; try to enable them via splitter if the value isn't needed anymore. | |
1364 | ||
609e7e80 | 1365 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1366 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1367 | [(set (reg CC_REGNUM) |
e325aba2 AK |
1368 | (compare (match_operand:FP 0 "register_operand" "f") |
1369 | (match_operand:FP 1 "const0_operand" ""))) | |
1370 | (clobber (match_operand:FP 2 "register_operand" "=0"))] | |
142cd70f | 1371 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1372 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1373 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1374 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1375 | |
e325aba2 AK |
1376 | (define_split |
1377 | [(set (match_operand 0 "cc_reg_operand") | |
1378 | (compare (match_operand:FP 1 "register_operand") | |
1379 | (match_operand:FP 2 "const0_operand")))] | |
1380 | "TARGET_HARD_FLOAT && REG_P (operands[1]) && dead_or_set_p (insn, operands[1])" | |
1381 | [(parallel | |
1382 | [(set (match_dup 0) (match_dup 3)) | |
1383 | (clobber (match_dup 1))])] | |
1384 | { | |
1385 | /* s390_match_ccmode requires the compare to have the same CC mode | |
1386 | as the CC destination register. */ | |
1387 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[0]), | |
1388 | operands[1], operands[2]); | |
1389 | }) | |
1390 | ||
1391 | ||
2de2b3f9 AK |
1392 | ; VX: TFmode in FPR pairs: use cxbr instead of wfcxb |
1393 | ; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcsb, wfcdb | |
f5905b37 | 1394 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1395 | [(set (reg CC_REGNUM) |
2de2b3f9 AK |
1396 | (compare (match_operand:FP 0 "register_operand" "f,f,v,v") |
1397 | (match_operand:FP 1 "general_operand" "f,R,v,v")))] | |
142cd70f | 1398 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1399 | "@ |
609e7e80 | 1400 | c<xde><bt>r\t%0,%1 |
77c585ca | 1401 | c<xde>b\t%0,%1 |
2de2b3f9 AK |
1402 | wfcdb\t%0,%1 |
1403 | wfcsb\t%0,%1" | |
1404 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
1405 | (set_attr "cpu_facility" "*,*,vx,vxe") | |
1406 | (set_attr "enabled" "*,<DSF>,<DF>,<SF>")]) | |
963fc8d0 AK |
1407 | |
1408 | ; Compare and Branch instructions | |
1409 | ||
1410 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1411 | ; The following instructions do a complementary access of their second |
1412 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1413 | (define_insn "*cmp_and_br_signed_<mode>" |
1414 | [(set (pc) | |
1415 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1416 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1417 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1418 | (label_ref (match_operand 3 "" "")) | |
1419 | (pc))) | |
1420 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1421 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1422 | { |
1423 | if (get_attr_length (insn) == 6) | |
1424 | return which_alternative ? | |
1425 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1426 | else | |
1427 | return which_alternative ? | |
1428 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1429 | } | |
1430 | [(set_attr "op_type" "RIE") | |
1431 | (set_attr "type" "branch") | |
e3cba5e5 | 1432 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1433 | (set (attr "length") |
1434 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1435 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1436 | ; 10 byte for cgr/jg | |
1437 | ||
1438 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1439 | ; The following instructions do a complementary access of their second |
1440 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1441 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1442 | [(set (pc) | |
1443 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1444 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1445 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1446 | (label_ref (match_operand 3 "" "")) | |
1447 | (pc))) | |
1448 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1449 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1450 | { |
1451 | if (get_attr_length (insn) == 6) | |
1452 | return which_alternative ? | |
1453 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1454 | else | |
1455 | return which_alternative ? | |
1456 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1457 | } | |
1458 | [(set_attr "op_type" "RIE") | |
1459 | (set_attr "type" "branch") | |
e3cba5e5 | 1460 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1461 | (set (attr "length") |
1462 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1463 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1464 | ; 10 byte for clgr/jg | |
1465 | ||
b0f86a7e AK |
1466 | ; And now the same two patterns as above but with a negated CC mask. |
1467 | ||
1468 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1469 | ; The following instructions do a complementary access of their second | |
1470 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1471 | (define_insn "*icmp_and_br_signed_<mode>" | |
1472 | [(set (pc) | |
1473 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1474 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1475 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1476 | (pc) | |
1477 | (label_ref (match_operand 3 "" "")))) | |
1478 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1479 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1480 | { |
1481 | if (get_attr_length (insn) == 6) | |
1482 | return which_alternative ? | |
1483 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1484 | else | |
1485 | return which_alternative ? | |
1486 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1487 | } | |
1488 | [(set_attr "op_type" "RIE") | |
1489 | (set_attr "type" "branch") | |
1490 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1491 | (set (attr "length") | |
1492 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1493 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1494 | ; 10 byte for cgr/jg | |
1495 | ||
1496 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1497 | ; The following instructions do a complementary access of their second | |
1498 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1499 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1500 | [(set (pc) | |
1501 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1502 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1503 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1504 | (pc) | |
1505 | (label_ref (match_operand 3 "" "")))) | |
1506 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1507 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1508 | { |
1509 | if (get_attr_length (insn) == 6) | |
1510 | return which_alternative ? | |
1511 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1512 | else | |
1513 | return which_alternative ? | |
1514 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1515 | } | |
1516 | [(set_attr "op_type" "RIE") | |
1517 | (set_attr "type" "branch") | |
1518 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1519 | (set (attr "length") | |
1520 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1521 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1522 | ; 10 byte for clgr/jg | |
1523 | ||
9db1d521 HP |
1524 | ;; |
1525 | ;;- Move instructions. | |
1526 | ;; | |
1527 | ||
1528 | ; | |
1529 | ; movti instruction pattern(s). | |
1530 | ; | |
1531 | ||
3cb9ee2f AK |
1532 | |
1533 | ; Separate out the register pair alternative since constraints (P) are | |
1534 | ; not able to deal with const_wide_int's. But predicates do. | |
1535 | (define_insn "*movti_bigconst" | |
1536 | [(set (match_operand:TI 0 "register_operand" "=d") | |
1537 | (match_operand:TI 1 "reload_const_wide_int_operand" ""))] | |
1538 | "TARGET_ZARCH" | |
1539 | "#") | |
1540 | ||
085261c8 AK |
1541 | ; FIXME: More constants are possible by enabling jxx, jyy constraints |
1542 | ; for TImode (use double-int for the calculations) | |
9db1d521 | 1543 | (define_insn "movti" |
9f3c21d6 AK |
1544 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R,d, d, d, d, d,o") |
1545 | (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,K,NxHD0,Os,NxSD0,dT,d"))] | |
9602b6a1 | 1546 | "TARGET_ZARCH" |
4023fb28 | 1547 | "@ |
fc0ea003 UW |
1548 | lmg\t%0,%N0,%S1 |
1549 | stmg\t%1,%N1,%S0 | |
085261c8 AK |
1550 | vlr\t%v0,%v1 |
1551 | vzero\t%v0 | |
1552 | vone\t%v0 | |
1553 | vlvgp\t%v0,%1,%N1 | |
1554 | # | |
b8923037 AK |
1555 | vl\t%v0,%1%A1 |
1556 | vst\t%v1,%0%A0 | |
4023fb28 | 1557 | # |
9f3c21d6 AK |
1558 | # |
1559 | # | |
1560 | # | |
1561 | # | |
19b63d8e | 1562 | #" |
9f3c21d6 AK |
1563 | [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*,*,*,*,*") |
1564 | (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*,*,*,*,*") | |
1565 | (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*,*,extimm,*,*")]) | |
4023fb28 UW |
1566 | |
1567 | (define_split | |
1568 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1569 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1570 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1571 | && !s_operand (operands[0], TImode) |
1572 | && !s_operand (operands[1], TImode) | |
dc65c307 | 1573 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1574 | [(set (match_dup 2) (match_dup 4)) |
1575 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1576 | { |
dc65c307 UW |
1577 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1578 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1579 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1580 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1581 | }) | |
1582 | ||
1583 | (define_split | |
1584 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1585 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1586 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1587 | && !s_operand (operands[0], TImode) |
1588 | && !s_operand (operands[1], TImode) | |
dc65c307 UW |
1589 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1590 | [(set (match_dup 2) (match_dup 4)) | |
1591 | (set (match_dup 3) (match_dup 5))] | |
1592 | { | |
1593 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1594 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1595 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1596 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1597 | }) | |
4023fb28 | 1598 | |
085261c8 AK |
1599 | ; Use part of the TImode target reg to perform the address |
1600 | ; calculation. If the TImode value is supposed to be copied into a VR | |
1601 | ; this splitter is not necessary. | |
4023fb28 UW |
1602 | (define_split |
1603 | [(set (match_operand:TI 0 "register_operand" "") | |
1604 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1605 | "TARGET_ZARCH && reload_completed |
085261c8 | 1606 | && !VECTOR_REG_P (operands[0]) |
4023fb28 | 1607 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1608 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1609 | { |
1610 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1611 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1612 | s390_load_address (addr, XEXP (operands[1], 0)); |
1613 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1614 | }) |
1615 | ||
833cd70a | 1616 | |
085261c8 AK |
1617 | ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. |
1618 | ; For the higher order bits we do simply a DImode move while the | |
1619 | ; second part is done via vec extract. Both will end up as vlgvg. | |
1620 | (define_split | |
1621 | [(set (match_operand:TI 0 "register_operand" "") | |
1622 | (match_operand:TI 1 "register_operand" ""))] | |
1623 | "TARGET_VX && reload_completed | |
1624 | && GENERAL_REG_P (operands[0]) | |
1625 | && VECTOR_REG_P (operands[1])" | |
1626 | [(set (match_dup 2) (match_dup 4)) | |
1627 | (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] | |
1628 | UNSPEC_VEC_EXTRACT))] | |
1629 | { | |
1630 | operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1631 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1632 | operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1633 | operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); | |
1634 | }) | |
1635 | ||
833cd70a AK |
1636 | ; |
1637 | ; Patterns used for secondary reloads | |
1638 | ; | |
1639 | ||
963fc8d0 AK |
1640 | ; z10 provides move instructions accepting larl memory operands. |
1641 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1642 | ; These patterns are also used for unaligned SI and DI accesses. | |
1643 | ||
085261c8 AK |
1644 | (define_expand "reload<ALL:mode><P:mode>_tomem_z10" |
1645 | [(parallel [(match_operand:ALL 0 "memory_operand" "") | |
1646 | (match_operand:ALL 1 "register_operand" "=d") | |
1647 | (match_operand:P 2 "register_operand" "=&a")])] | |
963fc8d0 AK |
1648 | "TARGET_Z10" |
1649 | { | |
1650 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1651 | DONE; | |
1652 | }) | |
1653 | ||
085261c8 AK |
1654 | (define_expand "reload<ALL:mode><P:mode>_toreg_z10" |
1655 | [(parallel [(match_operand:ALL 0 "register_operand" "=d") | |
1656 | (match_operand:ALL 1 "memory_operand" "") | |
1657 | (match_operand:P 2 "register_operand" "=a")])] | |
963fc8d0 AK |
1658 | "TARGET_Z10" |
1659 | { | |
1660 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1661 | DONE; | |
1662 | }) | |
1663 | ||
1664 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1665 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1666 | (match_operand:P 1 "larl_operand" "") | |
1667 | (match_operand:P 2 "register_operand" "=a")])] | |
1668 | "TARGET_Z10" | |
1669 | { | |
1670 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1671 | DONE; | |
1672 | }) | |
1673 | ||
833cd70a AK |
1674 | ; Handles loading a PLUS (load address) expression |
1675 | ||
1676 | (define_expand "reload<mode>_plus" | |
1677 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1678 | (match_operand:P 1 "s390_plus_operand" "") | |
1679 | (match_operand:P 2 "register_operand" "=&a")])] | |
1680 | "" | |
1681 | { | |
1682 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1683 | DONE; | |
1684 | }) | |
1685 | ||
085261c8 AK |
1686 | ; Not all the indirect memory access instructions support the full |
1687 | ; format (long disp + index + base). So whenever a move from/to such | |
1688 | ; an address is required and the instruction cannot deal with it we do | |
1689 | ; a load address into a scratch register first and use this as the new | |
1690 | ; base register. | |
1691 | ; This in particular is used for: | |
1692 | ; - non-offsetable memory accesses for multiword moves | |
1693 | ; - full vector reg moves with long displacements | |
833cd70a | 1694 | |
085261c8 | 1695 | (define_expand "reload<mode>_la_in" |
833cd70a AK |
1696 | [(parallel [(match_operand 0 "register_operand" "") |
1697 | (match_operand 1 "" "") | |
1698 | (match_operand:P 2 "register_operand" "=&a")])] | |
1699 | "" | |
1700 | { | |
1701 | gcc_assert (MEM_P (operands[1])); | |
1702 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1703 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1704 | emit_move_insn (operands[0], operands[1]); | |
1705 | DONE; | |
1706 | }) | |
1707 | ||
085261c8 | 1708 | (define_expand "reload<mode>_la_out" |
833cd70a AK |
1709 | [(parallel [(match_operand 0 "" "") |
1710 | (match_operand 1 "register_operand" "") | |
1711 | (match_operand:P 2 "register_operand" "=&a")])] | |
1712 | "" | |
dc65c307 | 1713 | { |
9c3c3dcc | 1714 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1715 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1716 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1717 | emit_move_insn (operands[0], operands[1]); | |
1718 | DONE; | |
1719 | }) | |
9db1d521 | 1720 | |
1f9e1fc6 AK |
1721 | (define_expand "reload<mode>_PIC_addr" |
1722 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1723 | (match_operand 1 "larl_operand" "") | |
1724 | (match_operand:P 2 "register_operand" "=a")])] | |
1725 | "" | |
1726 | { | |
0a2aaacc KG |
1727 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1728 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1729 | }) |
1730 | ||
9db1d521 HP |
1731 | ; |
1732 | ; movdi instruction pattern(s). | |
1733 | ; | |
1734 | ||
9db1d521 HP |
1735 | (define_expand "movdi" |
1736 | [(set (match_operand:DI 0 "general_operand" "") | |
1737 | (match_operand:DI 1 "general_operand" ""))] | |
1738 | "" | |
9db1d521 | 1739 | { |
fd3cd001 | 1740 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1741 | if (TARGET_64BIT |
1742 | && (SYMBOLIC_CONST (operands[1]) | |
1743 | || (GET_CODE (operands[1]) == PLUS | |
1744 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1745 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1746 | emit_symbolic_move (operands); |
10bbf137 | 1747 | }) |
9db1d521 | 1748 | |
3af8e996 | 1749 | (define_insn "*movdi_64" |
85dae55a | 1750 | [(set (match_operand:DI 0 "nonimmediate_operand" |
b6f51755 | 1751 | "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R,d") |
85dae55a | 1752 | (match_operand:DI 1 "general_operand" |
b6f51755 | 1753 | " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v,ZL"))] |
9602b6a1 | 1754 | "TARGET_ZARCH" |
85dae55a AK |
1755 | "@ |
1756 | lghi\t%0,%h1 | |
1757 | llihh\t%0,%i1 | |
1758 | llihl\t%0,%i1 | |
1759 | llilh\t%0,%i1 | |
1760 | llill\t%0,%i1 | |
1761 | lgfi\t%0,%1 | |
1762 | llihf\t%0,%k1 | |
1763 | llilf\t%0,%k1 | |
1764 | ldgr\t%0,%1 | |
1765 | lgdr\t%0,%1 | |
1766 | lay\t%0,%a1 | |
963fc8d0 | 1767 | lgrl\t%0,%1 |
85dae55a AK |
1768 | lgr\t%0,%1 |
1769 | lg\t%0,%1 | |
1770 | stg\t%1,%0 | |
1771 | ldr\t%0,%1 | |
1772 | ld\t%0,%1 | |
1773 | ldy\t%0,%1 | |
1774 | std\t%1,%0 | |
1775 | stdy\t%1,%0 | |
963fc8d0 AK |
1776 | stgrl\t%1,%0 |
1777 | mvghi\t%0,%1 | |
85dae55a AK |
1778 | # |
1779 | # | |
1780 | stam\t%1,%N1,%S0 | |
085261c8 AK |
1781 | lam\t%0,%N0,%S1 |
1782 | vleig\t%v0,%h1,0 | |
1783 | vlr\t%v0,%v1 | |
1784 | vlvgg\t%v0,%1,0 | |
1785 | vlgvg\t%0,%v1,0 | |
1786 | vleg\t%v0,%1,0 | |
b6f51755 IL |
1787 | vsteg\t%v1,%0,0 |
1788 | larl\t%0,%1" | |
963fc8d0 | 1789 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
b6f51755 IL |
1790 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS, |
1791 | VRX,VRX,RIL") | |
963fc8d0 | 1792 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
085261c8 | 1793 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, |
b6f51755 | 1794 | *,*,*,*,*,*,*,larl") |
3af8e996 | 1795 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1796 | z10,*,*,*,*,*,longdisp,*,longdisp, |
b6f51755 | 1797 | z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx,*") |
9381e3f1 WG |
1798 | (set_attr "z10prop" "z10_fwd_A1, |
1799 | z10_fwd_E1, | |
1800 | z10_fwd_E1, | |
1801 | z10_fwd_E1, | |
1802 | z10_fwd_E1, | |
1803 | z10_fwd_A1, | |
1804 | z10_fwd_E1, | |
1805 | z10_fwd_E1, | |
1806 | *, | |
1807 | *, | |
1808 | z10_fwd_A1, | |
1809 | z10_fwd_A3, | |
1810 | z10_fr_E1, | |
1811 | z10_fwd_A3, | |
1812 | z10_rec, | |
1813 | *, | |
1814 | *, | |
1815 | *, | |
1816 | *, | |
1817 | *, | |
1818 | z10_rec, | |
1819 | z10_super, | |
1820 | *, | |
1821 | *, | |
1822 | *, | |
b6f51755 IL |
1823 | *,*,*,*,*,*,*, |
1824 | z10_super_A1") | |
14cfceb7 IL |
1825 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*, |
1826 | *,yes,*,*,*,*,*,*,*,*, | |
1827 | yes,*,*,*,*,*,*,*,*,*, | |
1828 | *,*,yes") | |
9381e3f1 | 1829 | ]) |
c5aa1d12 UW |
1830 | |
1831 | (define_split | |
1832 | [(set (match_operand:DI 0 "register_operand" "") | |
1833 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1834 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1835 | [(set (match_dup 2) (match_dup 3)) |
1836 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1837 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1838 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1839 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1840 | ||
1841 | (define_split | |
1842 | [(set (match_operand:DI 0 "register_operand" "") | |
1843 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1844 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1845 | && dead_or_set_p (insn, operands[1])" |
1846 | [(set (match_dup 3) (match_dup 2)) | |
1847 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1848 | (set (match_dup 4) (match_dup 2))] | |
1849 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1850 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1851 | ||
1852 | (define_split | |
1853 | [(set (match_operand:DI 0 "register_operand" "") | |
1854 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1855 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1856 | && !dead_or_set_p (insn, operands[1])" |
1857 | [(set (match_dup 3) (match_dup 2)) | |
1858 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1859 | (set (match_dup 4) (match_dup 2)) | |
1860 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1861 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1862 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1863 | |
1864 | (define_insn "*movdi_31" | |
963fc8d0 | 1865 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1866 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1867 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1868 | " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1869 | "!TARGET_ZARCH" |
4023fb28 | 1870 | "@ |
fc0ea003 | 1871 | lm\t%0,%N0,%S1 |
c4d50129 | 1872 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1873 | stm\t%1,%N1,%S0 |
c4d50129 | 1874 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1875 | # |
1876 | # | |
d40c829f UW |
1877 | ldr\t%0,%1 |
1878 | ld\t%0,%1 | |
1879 | ldy\t%0,%1 | |
1880 | std\t%1,%0 | |
1881 | stdy\t%1,%0 | |
19b63d8e | 1882 | #" |
f2dc2f86 AK |
1883 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1884 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
3e4be43f | 1885 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")]) |
963fc8d0 AK |
1886 | |
1887 | ; For a load from a symbol ref we can use one of the target registers | |
1888 | ; together with larl to load the address. | |
1889 | (define_split | |
1890 | [(set (match_operand:DI 0 "register_operand" "") | |
1891 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1892 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1893 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1894 | [(set (match_dup 2) (match_dup 3)) | |
1895 | (set (match_dup 0) (match_dup 1))] | |
1896 | { | |
1897 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1898 | operands[3] = XEXP (operands[1], 0); | |
1899 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1900 | }) | |
4023fb28 UW |
1901 | |
1902 | (define_split | |
1903 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1904 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1905 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1906 | && !s_operand (operands[0], DImode) |
1907 | && !s_operand (operands[1], DImode) | |
dc65c307 | 1908 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1909 | [(set (match_dup 2) (match_dup 4)) |
1910 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1911 | { |
dc65c307 UW |
1912 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1913 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1914 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1915 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1916 | }) | |
1917 | ||
1918 | (define_split | |
1919 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1920 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1921 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1922 | && !s_operand (operands[0], DImode) |
1923 | && !s_operand (operands[1], DImode) | |
dc65c307 UW |
1924 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1925 | [(set (match_dup 2) (match_dup 4)) | |
1926 | (set (match_dup 3) (match_dup 5))] | |
1927 | { | |
1928 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1929 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1930 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1931 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1932 | }) | |
9db1d521 | 1933 | |
4023fb28 UW |
1934 | (define_split |
1935 | [(set (match_operand:DI 0 "register_operand" "") | |
1936 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1937 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1938 | && !FP_REG_P (operands[0]) |
4023fb28 | 1939 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1940 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1941 | { |
1942 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1943 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1944 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1945 | }) |
1946 | ||
84817c5d UW |
1947 | (define_peephole2 |
1948 | [(set (match_operand:DI 0 "register_operand" "") | |
1949 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1950 | "TARGET_ZARCH |
84817c5d UW |
1951 | && !FP_REG_P (operands[0]) |
1952 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1953 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1954 | && get_pool_mode (operands[1]) == DImode | |
1955 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1956 | [(set (match_dup 0) (match_dup 2))] | |
1957 | "operands[2] = get_pool_constant (operands[1]);") | |
1958 | ||
7bdff56f UW |
1959 | (define_insn "*la_64" |
1960 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 1961 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
1962 | "TARGET_64BIT" |
1963 | "@ | |
1964 | la\t%0,%a1 | |
1965 | lay\t%0,%a1" | |
1966 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 1967 | (set_attr "type" "la") |
3e4be43f | 1968 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1969 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
1970 | |
1971 | (define_peephole2 | |
1972 | [(parallel | |
1973 | [(set (match_operand:DI 0 "register_operand" "") | |
1974 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1975 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1976 | "TARGET_64BIT |
e1d5ee28 | 1977 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1978 | [(set (match_dup 0) (match_dup 1))] |
1979 | "") | |
1980 | ||
1981 | (define_peephole2 | |
1982 | [(set (match_operand:DI 0 "register_operand" "") | |
1983 | (match_operand:DI 1 "register_operand" "")) | |
1984 | (parallel | |
1985 | [(set (match_dup 0) | |
1986 | (plus:DI (match_dup 0) | |
1987 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1988 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1989 | "TARGET_64BIT |
1990 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1991 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1992 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1993 | "") | |
1994 | ||
9db1d521 HP |
1995 | ; |
1996 | ; movsi instruction pattern(s). | |
1997 | ; | |
1998 | ||
9db1d521 HP |
1999 | (define_expand "movsi" |
2000 | [(set (match_operand:SI 0 "general_operand" "") | |
2001 | (match_operand:SI 1 "general_operand" ""))] | |
2002 | "" | |
9db1d521 | 2003 | { |
fd3cd001 | 2004 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
2005 | if (!TARGET_64BIT |
2006 | && (SYMBOLIC_CONST (operands[1]) | |
2007 | || (GET_CODE (operands[1]) == PLUS | |
2008 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
2009 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 2010 | emit_symbolic_move (operands); |
10bbf137 | 2011 | }) |
9db1d521 | 2012 | |
9e8327e3 UW |
2013 | (define_insn "*movsi_larl" |
2014 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2015 | (match_operand:SI 1 "larl_operand" "X"))] | |
8cc6307c | 2016 | "!TARGET_64BIT |
9e8327e3 UW |
2017 | && !FP_REG_P (operands[0])" |
2018 | "larl\t%0,%1" | |
2019 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 2020 | (set_attr "type" "larl") |
14cfceb7 IL |
2021 | (set_attr "z10prop" "z10_fwd_A1") |
2022 | (set_attr "relative_long" "yes")]) | |
9e8327e3 | 2023 | |
f19a9af7 | 2024 | (define_insn "*movsi_zarch" |
2f7e5a0d | 2025 | [(set (match_operand:SI 0 "nonimmediate_operand" |
3e4be43f | 2026 | "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R") |
2f7e5a0d | 2027 | (match_operand:SI 1 "general_operand" |
3e4be43f | 2028 | " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))] |
f19a9af7 | 2029 | "TARGET_ZARCH" |
9db1d521 | 2030 | "@ |
f19a9af7 AK |
2031 | lhi\t%0,%h1 |
2032 | llilh\t%0,%i1 | |
2033 | llill\t%0,%i1 | |
ec24698e | 2034 | iilf\t%0,%o1 |
f19a9af7 | 2035 | lay\t%0,%a1 |
963fc8d0 | 2036 | lrl\t%0,%1 |
d40c829f UW |
2037 | lr\t%0,%1 |
2038 | l\t%0,%1 | |
2039 | ly\t%0,%1 | |
2040 | st\t%1,%0 | |
2041 | sty\t%1,%0 | |
ae1c6198 | 2042 | ldr\t%0,%1 |
d40c829f | 2043 | ler\t%0,%1 |
085261c8 | 2044 | lde\t%0,%1 |
d40c829f UW |
2045 | le\t%0,%1 |
2046 | ley\t%0,%1 | |
2047 | ste\t%1,%0 | |
2048 | stey\t%1,%0 | |
c5aa1d12 UW |
2049 | ear\t%0,%1 |
2050 | sar\t%0,%1 | |
2051 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
2052 | strl\t%1,%0 |
2053 | mvhi\t%0,%1 | |
085261c8 AK |
2054 | lam\t%0,%0,%S1 |
2055 | vleif\t%v0,%h1,0 | |
2056 | vlr\t%v0,%v1 | |
2057 | vlvgf\t%v0,%1,0 | |
2058 | vlgvf\t%0,%v1,0 | |
2059 | vlef\t%v0,%1,0 | |
2060 | vstef\t%v1,%0,0" | |
963fc8d0 | 2061 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
ae1c6198 | 2062 | RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
9381e3f1 WG |
2063 | (set_attr "type" "*, |
2064 | *, | |
2065 | *, | |
2066 | *, | |
2067 | la, | |
2068 | larl, | |
2069 | lr, | |
2070 | load, | |
2071 | load, | |
2072 | store, | |
2073 | store, | |
2074 | floadsf, | |
2075 | floadsf, | |
2076 | floadsf, | |
085261c8 AK |
2077 | floadsf, |
2078 | floadsf, | |
9381e3f1 WG |
2079 | fstoresf, |
2080 | fstoresf, | |
2081 | *, | |
2082 | *, | |
2083 | *, | |
2084 | larl, | |
2085 | *, | |
085261c8 | 2086 | *,*,*,*,*,*,*") |
963fc8d0 | 2087 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
285363a1 | 2088 | vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2089 | (set_attr "z10prop" "z10_fwd_A1, |
2090 | z10_fwd_E1, | |
2091 | z10_fwd_E1, | |
2092 | z10_fwd_A1, | |
2093 | z10_fwd_A1, | |
2094 | z10_fwd_A3, | |
2095 | z10_fr_E1, | |
2096 | z10_fwd_A3, | |
2097 | z10_fwd_A3, | |
729e750f | 2098 | z10_rec, |
9381e3f1 WG |
2099 | z10_rec, |
2100 | *, | |
2101 | *, | |
2102 | *, | |
2103 | *, | |
2104 | *, | |
085261c8 AK |
2105 | *, |
2106 | *, | |
9381e3f1 WG |
2107 | z10_super_E1, |
2108 | z10_super, | |
2109 | *, | |
2110 | z10_rec, | |
2111 | z10_super, | |
14cfceb7 IL |
2112 | *,*,*,*,*,*,*") |
2113 | (set_attr "relative_long" "*,*,*,*,*,yes,*,*,*,*, | |
2114 | *,*,*,*,*,*,*,*,*,*, | |
2115 | *,yes,*,*,*,*,*,*,*,*")]) | |
f19a9af7 AK |
2116 | |
2117 | (define_insn "*movsi_esa" | |
085261c8 AK |
2118 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") |
2119 | (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
2120 | "!TARGET_ZARCH" |
2121 | "@ | |
2122 | lhi\t%0,%h1 | |
2123 | lr\t%0,%1 | |
2124 | l\t%0,%1 | |
2125 | st\t%1,%0 | |
ae1c6198 | 2126 | ldr\t%0,%1 |
f19a9af7 | 2127 | ler\t%0,%1 |
085261c8 | 2128 | lde\t%0,%1 |
f19a9af7 AK |
2129 | le\t%0,%1 |
2130 | ste\t%1,%0 | |
c5aa1d12 UW |
2131 | ear\t%0,%1 |
2132 | sar\t%0,%1 | |
2133 | stam\t%1,%1,%S0 | |
f2dc2f86 | 2134 | lam\t%0,%0,%S1" |
ae1c6198 | 2135 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS") |
085261c8 AK |
2136 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") |
2137 | (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, | |
2138 | z10_super,*,*") | |
285363a1 | 2139 | (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*") |
9381e3f1 | 2140 | ]) |
9db1d521 | 2141 | |
84817c5d UW |
2142 | (define_peephole2 |
2143 | [(set (match_operand:SI 0 "register_operand" "") | |
2144 | (mem:SI (match_operand 1 "address_operand" "")))] | |
2145 | "!FP_REG_P (operands[0]) | |
2146 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2147 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2148 | && get_pool_mode (operands[1]) == SImode | |
2149 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
2150 | [(set (match_dup 0) (match_dup 2))] | |
2151 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 2152 | |
7bdff56f UW |
2153 | (define_insn "*la_31" |
2154 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2155 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
2156 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
2157 | "@ | |
2158 | la\t%0,%a1 | |
2159 | lay\t%0,%a1" | |
2160 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2161 | (set_attr "type" "la") |
3e4be43f | 2162 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2163 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2164 | |
2165 | (define_peephole2 | |
2166 | [(parallel | |
2167 | [(set (match_operand:SI 0 "register_operand" "") | |
2168 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2169 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2170 | "!TARGET_64BIT |
e1d5ee28 | 2171 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2172 | [(set (match_dup 0) (match_dup 1))] |
2173 | "") | |
2174 | ||
2175 | (define_peephole2 | |
2176 | [(set (match_operand:SI 0 "register_operand" "") | |
2177 | (match_operand:SI 1 "register_operand" "")) | |
2178 | (parallel | |
2179 | [(set (match_dup 0) | |
2180 | (plus:SI (match_dup 0) | |
2181 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2182 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2183 | "!TARGET_64BIT |
2184 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2185 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2186 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
2187 | "") | |
2188 | ||
2189 | (define_insn "*la_31_and" | |
2190 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2191 | (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT") |
7bdff56f UW |
2192 | (const_int 2147483647)))] |
2193 | "!TARGET_64BIT" | |
2194 | "@ | |
2195 | la\t%0,%a1 | |
2196 | lay\t%0,%a1" | |
2197 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2198 | (set_attr "type" "la") |
3e4be43f | 2199 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2200 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2201 | |
2202 | (define_insn_and_split "*la_31_and_cc" | |
2203 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2204 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
2205 | (const_int 2147483647))) | |
ae156f85 | 2206 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
2207 | "!TARGET_64BIT" |
2208 | "#" | |
2209 | "&& reload_completed" | |
2210 | [(set (match_dup 0) | |
2211 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
2212 | "" | |
2213 | [(set_attr "op_type" "RX") | |
2214 | (set_attr "type" "la")]) | |
2215 | ||
2216 | (define_insn "force_la_31" | |
2217 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2218 | (match_operand:QI 1 "address_operand" "ZR,ZT")) |
7bdff56f UW |
2219 | (use (const_int 0))] |
2220 | "!TARGET_64BIT" | |
2221 | "@ | |
2222 | la\t%0,%a1 | |
2223 | lay\t%0,%a1" | |
2224 | [(set_attr "op_type" "RX") | |
9381e3f1 | 2225 | (set_attr "type" "la") |
3e4be43f | 2226 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2227 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f | 2228 | |
9db1d521 HP |
2229 | ; |
2230 | ; movhi instruction pattern(s). | |
2231 | ; | |
2232 | ||
02ed3c5e UW |
2233 | (define_expand "movhi" |
2234 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2235 | (match_operand:HI 1 "general_operand" ""))] | |
2236 | "" | |
2237 | { | |
2f7e5a0d | 2238 | /* Make it explicit that loading a register from memory |
02ed3c5e | 2239 | always sign-extends (at least) to SImode. */ |
b3a13419 | 2240 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 2241 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2242 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
2243 | { |
2244 | rtx tmp = gen_reg_rtx (SImode); | |
2245 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
f7df4a84 | 2246 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2247 | operands[1] = gen_lowpart (HImode, tmp); |
2248 | } | |
2249 | }) | |
2250 | ||
2251 | (define_insn "*movhi" | |
3e4be43f UW |
2252 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R") |
2253 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))] | |
9db1d521 HP |
2254 | "" |
2255 | "@ | |
d40c829f UW |
2256 | lr\t%0,%1 |
2257 | lhi\t%0,%h1 | |
2258 | lh\t%0,%1 | |
2259 | lhy\t%0,%1 | |
963fc8d0 | 2260 | lhrl\t%0,%1 |
d40c829f UW |
2261 | sth\t%1,%0 |
2262 | sthy\t%1,%0 | |
963fc8d0 | 2263 | sthrl\t%1,%0 |
085261c8 AK |
2264 | mvhhi\t%0,%1 |
2265 | vleih\t%v0,%h1,0 | |
2266 | vlr\t%v0,%v1 | |
2267 | vlvgh\t%v0,%1,0 | |
2268 | vlgvh\t%0,%v1,0 | |
2269 | vleh\t%v0,%1,0 | |
2270 | vsteh\t%v1,%0,0" | |
2271 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") | |
2272 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2273 | (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2274 | (set_attr "z10prop" "z10_fr_E1, |
2275 | z10_fwd_A1, | |
2276 | z10_super_E1, | |
2277 | z10_super_E1, | |
2278 | z10_super_E1, | |
729e750f | 2279 | z10_rec, |
9381e3f1 WG |
2280 | z10_rec, |
2281 | z10_rec, | |
14cfceb7 IL |
2282 | z10_super,*,*,*,*,*,*") |
2283 | (set_attr "relative_long" "*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*")]) | |
9db1d521 | 2284 | |
84817c5d UW |
2285 | (define_peephole2 |
2286 | [(set (match_operand:HI 0 "register_operand" "") | |
2287 | (mem:HI (match_operand 1 "address_operand" "")))] | |
2288 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2289 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2290 | && get_pool_mode (operands[1]) == HImode | |
2291 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2292 | [(set (match_dup 0) (match_dup 2))] | |
2293 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2294 | |
9db1d521 HP |
2295 | ; |
2296 | ; movqi instruction pattern(s). | |
2297 | ; | |
2298 | ||
02ed3c5e UW |
2299 | (define_expand "movqi" |
2300 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2301 | (match_operand:QI 1 "general_operand" ""))] | |
2302 | "" | |
2303 | { | |
c19ec8f9 | 2304 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 2305 | is just as fast as a QImode load. */ |
b3a13419 | 2306 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 2307 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2308 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 2309 | { |
9602b6a1 AK |
2310 | rtx tmp = gen_reg_rtx (DImode); |
2311 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
f7df4a84 | 2312 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2313 | operands[1] = gen_lowpart (QImode, tmp); |
2314 | } | |
2315 | }) | |
4023fb28 | 2316 | |
02ed3c5e | 2317 | (define_insn "*movqi" |
3e4be43f UW |
2318 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R") |
2319 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))] | |
9db1d521 HP |
2320 | "" |
2321 | "@ | |
d40c829f UW |
2322 | lr\t%0,%1 |
2323 | lhi\t%0,%b1 | |
2324 | ic\t%0,%1 | |
2325 | icy\t%0,%1 | |
2326 | stc\t%1,%0 | |
2327 | stcy\t%1,%0 | |
fc0ea003 | 2328 | mvi\t%S0,%b1 |
0a88561f | 2329 | mviy\t%S0,%b1 |
085261c8 AK |
2330 | # |
2331 | vleib\t%v0,%b1,0 | |
2332 | vlr\t%v0,%v1 | |
2333 | vlvgb\t%v0,%1,0 | |
2334 | vlgvb\t%0,%v1,0 | |
2335 | vleb\t%v0,%1,0 | |
2336 | vsteb\t%v1,%0,0" | |
2337 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") | |
2338 | (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2339 | (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2340 | (set_attr "z10prop" "z10_fr_E1, |
2341 | z10_fwd_A1, | |
2342 | z10_super_E1, | |
2343 | z10_super_E1, | |
729e750f | 2344 | z10_rec, |
9381e3f1 WG |
2345 | z10_rec, |
2346 | z10_super, | |
0a88561f | 2347 | z10_super, |
085261c8 | 2348 | *,*,*,*,*,*,*")]) |
9db1d521 | 2349 | |
84817c5d UW |
2350 | (define_peephole2 |
2351 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2352 | (mem:QI (match_operand 1 "address_operand" "")))] | |
2353 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2354 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2355 | && get_pool_mode (operands[1]) == QImode | |
2356 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2357 | [(set (match_dup 0) (match_dup 2))] | |
2358 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2359 | |
9db1d521 | 2360 | ; |
05b9aaaa | 2361 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
2362 | ; |
2363 | ||
2364 | (define_insn "*movstrictqi" | |
d3632d41 UW |
2365 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
2366 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 2367 | "" |
d3632d41 | 2368 | "@ |
d40c829f UW |
2369 | ic\t%0,%1 |
2370 | icy\t%0,%1" | |
9381e3f1 | 2371 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 2372 | (set_attr "cpu_facility" "*,longdisp") |
729e750f | 2373 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2374 | |
2375 | ; | |
2376 | ; movstricthi instruction pattern(s). | |
2377 | ; | |
2378 | ||
2379 | (define_insn "*movstricthi" | |
d3632d41 | 2380 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2381 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2382 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2383 | "" |
d3632d41 | 2384 | "@ |
fc0ea003 UW |
2385 | icm\t%0,3,%S1 |
2386 | icmy\t%0,3,%S1" | |
9381e3f1 | 2387 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2388 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2389 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2390 | |
2391 | ; | |
2392 | ; movstrictsi instruction pattern(s). | |
2393 | ; | |
2394 | ||
05b9aaaa | 2395 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2396 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2397 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2398 | "TARGET_ZARCH" |
9db1d521 | 2399 | "@ |
d40c829f UW |
2400 | lr\t%0,%1 |
2401 | l\t%0,%1 | |
c5aa1d12 UW |
2402 | ly\t%0,%1 |
2403 | ear\t%0,%1" | |
2404 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 | 2405 | (set_attr "type" "lr,load,load,*") |
3e4be43f | 2406 | (set_attr "cpu_facility" "*,*,longdisp,*") |
9381e3f1 | 2407 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) |
9db1d521 | 2408 | |
f61a2c7d | 2409 | ; |
609e7e80 | 2410 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2411 | ; |
2412 | ||
609e7e80 AK |
2413 | (define_expand "mov<mode>" |
2414 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2415 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2416 | "" |
2417 | "") | |
2418 | ||
609e7e80 | 2419 | (define_insn "*mov<mode>_64" |
3e4be43f UW |
2420 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o") |
2421 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))] | |
9602b6a1 | 2422 | "TARGET_ZARCH" |
f61a2c7d | 2423 | "@ |
65b1d8ea | 2424 | lzxr\t%0 |
f61a2c7d AK |
2425 | lxr\t%0,%1 |
2426 | # | |
2427 | # | |
2428 | lmg\t%0,%N0,%S1 | |
2429 | stmg\t%1,%N1,%S0 | |
2430 | # | |
f61a2c7d | 2431 | #" |
65b1d8ea AK |
2432 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2433 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2434 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2435 | |
609e7e80 | 2436 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2437 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2438 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2439 | "!TARGET_ZARCH" |
f61a2c7d | 2440 | "@ |
65b1d8ea | 2441 | lzxr\t%0 |
f61a2c7d AK |
2442 | lxr\t%0,%1 |
2443 | # | |
f61a2c7d | 2444 | #" |
65b1d8ea AK |
2445 | [(set_attr "op_type" "RRE,RRE,*,*") |
2446 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2447 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2448 | |
2449 | ; TFmode in GPRs splitters | |
2450 | ||
2451 | (define_split | |
609e7e80 AK |
2452 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2453 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2454 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2455 | && !s_operand (operands[0], <MODE>mode) |
2456 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2457 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2458 | [(set (match_dup 2) (match_dup 4)) |
2459 | (set (match_dup 3) (match_dup 5))] | |
2460 | { | |
609e7e80 AK |
2461 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2462 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2463 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2464 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2465 | }) |
2466 | ||
2467 | (define_split | |
609e7e80 AK |
2468 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2469 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2470 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2471 | && !s_operand (operands[0], <MODE>mode) |
2472 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2473 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2474 | [(set (match_dup 2) (match_dup 4)) |
2475 | (set (match_dup 3) (match_dup 5))] | |
2476 | { | |
609e7e80 AK |
2477 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2478 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2479 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2480 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2481 | }) |
2482 | ||
2483 | (define_split | |
609e7e80 AK |
2484 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2485 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2486 | "TARGET_ZARCH && reload_completed |
085261c8 | 2487 | && GENERAL_REG_P (operands[0]) |
f61a2c7d AK |
2488 | && !s_operand (operands[1], VOIDmode)" |
2489 | [(set (match_dup 0) (match_dup 1))] | |
2490 | { | |
609e7e80 | 2491 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2492 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2493 | s390_load_address (addr, XEXP (operands[1], 0)); |
2494 | operands[1] = replace_equiv_address (operands[1], addr); | |
2495 | }) | |
2496 | ||
7b6baae1 | 2497 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2498 | |
2499 | (define_split | |
609e7e80 AK |
2500 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2501 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2502 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2503 | && FP_REG_P (operands[0])" |
2504 | [(set (match_dup 2) (match_dup 4)) | |
2505 | (set (match_dup 3) (match_dup 5))] | |
2506 | { | |
609e7e80 AK |
2507 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2508 | <MODE>mode, 0); | |
2509 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2510 | <MODE>mode, 8); | |
2511 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2512 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2513 | }) |
2514 | ||
2515 | (define_split | |
609e7e80 AK |
2516 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2517 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2518 | "reload_completed && offsettable_memref_p (operands[0]) |
2519 | && FP_REG_P (operands[1])" | |
2520 | [(set (match_dup 2) (match_dup 4)) | |
2521 | (set (match_dup 3) (match_dup 5))] | |
2522 | { | |
609e7e80 AK |
2523 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2524 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2525 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2526 | <MODE>mode, 0); | |
2527 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2528 | <MODE>mode, 8); | |
f61a2c7d AK |
2529 | }) |
2530 | ||
9db1d521 | 2531 | ; |
609e7e80 | 2532 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2533 | ; |
2534 | ||
609e7e80 AK |
2535 | (define_expand "mov<mode>" |
2536 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2537 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2538 | "" |
13c025c1 | 2539 | "") |
9db1d521 | 2540 | |
609e7e80 AK |
2541 | (define_insn "*mov<mode>_64dfp" |
2542 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
590961cf | 2543 | "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R") |
609e7e80 | 2544 | (match_operand:DD_DF 1 "general_operand" |
590961cf | 2545 | " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))] |
9602b6a1 | 2546 | "TARGET_DFP" |
85dae55a | 2547 | "@ |
65b1d8ea | 2548 | lzdr\t%0 |
85dae55a AK |
2549 | ldr\t%0,%1 |
2550 | ldgr\t%0,%1 | |
2551 | lgdr\t%0,%1 | |
2552 | ld\t%0,%1 | |
2553 | ldy\t%0,%1 | |
2554 | std\t%1,%0 | |
2555 | stdy\t%1,%0 | |
45e5214c | 2556 | lghi\t%0,0 |
85dae55a | 2557 | lgr\t%0,%1 |
085261c8 | 2558 | lgrl\t%0,%1 |
85dae55a | 2559 | lg\t%0,%1 |
085261c8 AK |
2560 | stgrl\t%1,%0 |
2561 | stg\t%1,%0 | |
2562 | vlr\t%v0,%v1 | |
590961cf | 2563 | vleig\t%v0,0,0 |
085261c8 AK |
2564 | vlvgg\t%v0,%1,0 |
2565 | vlgvg\t%0,%v1,0 | |
2566 | vleg\t%0,%1,0 | |
2567 | vsteg\t%1,%0,0" | |
590961cf | 2568 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
65b1d8ea | 2569 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
590961cf AK |
2570 | fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store") |
2571 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*") | |
14cfceb7 IL |
2572 | (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx") |
2573 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,yes,*,*,*,*,*,*,*")]) | |
85dae55a | 2574 | |
609e7e80 | 2575 | (define_insn "*mov<mode>_64" |
590961cf AK |
2576 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T") |
2577 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))] | |
9602b6a1 | 2578 | "TARGET_ZARCH" |
9db1d521 | 2579 | "@ |
65b1d8ea | 2580 | lzdr\t%0 |
d40c829f UW |
2581 | ldr\t%0,%1 |
2582 | ld\t%0,%1 | |
2583 | ldy\t%0,%1 | |
2584 | std\t%1,%0 | |
2585 | stdy\t%1,%0 | |
45e5214c | 2586 | lghi\t%0,0 |
d40c829f | 2587 | lgr\t%0,%1 |
085261c8 | 2588 | lgrl\t%0,%1 |
d40c829f | 2589 | lg\t%0,%1 |
085261c8 | 2590 | stgrl\t%1,%0 |
590961cf AK |
2591 | stg\t%1,%0" |
2592 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY") | |
65b1d8ea | 2593 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, |
590961cf AK |
2594 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") |
2595 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
14cfceb7 IL |
2596 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*") |
2597 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,yes,*,*,*")]) | |
609e7e80 AK |
2598 | |
2599 | (define_insn "*mov<mode>_31" | |
2600 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
3e4be43f | 2601 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2602 | (match_operand:DD_DF 1 "general_operand" |
3e4be43f | 2603 | " G,f,R,T,f,f,Q,S,d,d,dPT,d"))] |
9602b6a1 | 2604 | "!TARGET_ZARCH" |
9db1d521 | 2605 | "@ |
65b1d8ea | 2606 | lzdr\t%0 |
d40c829f UW |
2607 | ldr\t%0,%1 |
2608 | ld\t%0,%1 | |
2609 | ldy\t%0,%1 | |
2610 | std\t%1,%0 | |
2611 | stdy\t%1,%0 | |
fc0ea003 | 2612 | lm\t%0,%N0,%S1 |
c4d50129 | 2613 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2614 | stm\t%1,%N1,%S0 |
c4d50129 | 2615 | stmy\t%1,%N1,%S0 |
4023fb28 | 2616 | # |
19b63d8e | 2617 | #" |
65b1d8ea AK |
2618 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2619 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2620 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
3e4be43f | 2621 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")]) |
4023fb28 UW |
2622 | |
2623 | (define_split | |
609e7e80 AK |
2624 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2625 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2626 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2627 | && !s_operand (operands[0], <MODE>mode) |
2628 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2629 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2630 | [(set (match_dup 2) (match_dup 4)) |
2631 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2632 | { |
609e7e80 AK |
2633 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2634 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2635 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2636 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2637 | }) |
2638 | ||
2639 | (define_split | |
609e7e80 AK |
2640 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2641 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2642 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2643 | && !s_operand (operands[0], <MODE>mode) |
2644 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2645 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2646 | [(set (match_dup 2) (match_dup 4)) |
2647 | (set (match_dup 3) (match_dup 5))] | |
2648 | { | |
609e7e80 AK |
2649 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2650 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2651 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2652 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2653 | }) |
9db1d521 | 2654 | |
4023fb28 | 2655 | (define_split |
609e7e80 AK |
2656 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2657 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2658 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2659 | && !FP_REG_P (operands[0]) |
4023fb28 | 2660 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2661 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2662 | { |
609e7e80 | 2663 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2664 | s390_load_address (addr, XEXP (operands[1], 0)); |
2665 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2666 | }) |
2667 | ||
9db1d521 | 2668 | ; |
609e7e80 | 2669 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2670 | ; |
2671 | ||
609e7e80 AK |
2672 | (define_insn "mov<mode>" |
2673 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
3e4be43f | 2674 | "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R") |
609e7e80 | 2675 | (match_operand:SD_SF 1 "general_operand" |
3e4be43f | 2676 | " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))] |
4023fb28 | 2677 | "" |
9db1d521 | 2678 | "@ |
65b1d8ea | 2679 | lzer\t%0 |
ae1c6198 | 2680 | ldr\t%0,%1 |
d40c829f | 2681 | ler\t%0,%1 |
085261c8 | 2682 | lde\t%0,%1 |
d40c829f UW |
2683 | le\t%0,%1 |
2684 | ley\t%0,%1 | |
2685 | ste\t%1,%0 | |
2686 | stey\t%1,%0 | |
45e5214c | 2687 | lhi\t%0,0 |
d40c829f | 2688 | lr\t%0,%1 |
085261c8 | 2689 | lrl\t%0,%1 |
d40c829f UW |
2690 | l\t%0,%1 |
2691 | ly\t%0,%1 | |
085261c8 | 2692 | strl\t%1,%0 |
d40c829f | 2693 | st\t%1,%0 |
085261c8 AK |
2694 | sty\t%1,%0 |
2695 | vlr\t%v0,%v1 | |
298f4647 | 2696 | vleif\t%v0,0,0 |
085261c8 AK |
2697 | vlvgf\t%v0,%1,0 |
2698 | vlgvf\t%0,%v1,0 | |
298f4647 AK |
2699 | vlef\t%0,%1,0 |
2700 | vstef\t%1,%0,0" | |
ae1c6198 | 2701 | [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
085261c8 AK |
2702 | (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, |
2703 | fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") | |
2704 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") | |
14cfceb7 IL |
2705 | (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx") |
2706 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*,*")]) | |
4023fb28 | 2707 | |
9dc62c00 AK |
2708 | ; |
2709 | ; movcc instruction pattern | |
2710 | ; | |
2711 | ||
2712 | (define_insn "movcc" | |
2713 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2714 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2715 | "" |
2716 | "@ | |
2717 | lr\t%0,%1 | |
2718 | tmh\t%1,12288 | |
2719 | ipm\t%0 | |
a71f0749 DV |
2720 | l\t%0,%1 |
2721 | ly\t%0,%1 | |
2722 | st\t%1,%0 | |
2723 | sty\t%1,%0" | |
8dd3b235 | 2724 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 | 2725 | (set_attr "type" "lr,*,*,load,load,store,store") |
3e4be43f | 2726 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp") |
a71f0749 | 2727 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") |
65b1d8ea | 2728 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2729 | |
19b63d8e UW |
2730 | ; |
2731 | ; Block move (MVC) patterns. | |
2732 | ; | |
2733 | ||
2734 | (define_insn "*mvc" | |
2735 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2736 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2737 | (use (match_operand 2 "const_int_operand" "n"))] | |
2738 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2739 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2740 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2741 | |
0a88561f AK |
2742 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2743 | ; order to have it implemented with mvc. | |
2744 | ||
2745 | (define_split | |
2746 | [(set (match_operand:QI 0 "memory_operand" "") | |
2747 | (match_operand:QI 1 "memory_operand" ""))] | |
2748 | "reload_completed" | |
2749 | [(parallel | |
2750 | [(set (match_dup 0) (match_dup 1)) | |
2751 | (use (const_int 1))])] | |
2752 | { | |
2753 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2754 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2755 | }) | |
2756 | ||
2757 | ||
19b63d8e UW |
2758 | (define_peephole2 |
2759 | [(parallel | |
2760 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2761 | (match_operand:BLK 1 "memory_operand" "")) | |
2762 | (use (match_operand 2 "const_int_operand" ""))]) | |
2763 | (parallel | |
2764 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2765 | (match_operand:BLK 4 "memory_operand" "")) | |
2766 | (use (match_operand 5 "const_int_operand" ""))])] | |
f9dcf14a AK |
2767 | "((INTVAL (operands[2]) > 16 && INTVAL (operands[5]) > 16) |
2768 | || (INTVAL (operands[2]) + INTVAL (operands[5]) <= 16)) | |
2769 | && s390_offset_p (operands[0], operands[3], operands[2]) | |
19b63d8e | 2770 | && s390_offset_p (operands[1], operands[4], operands[2]) |
9381e3f1 | 2771 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2772 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2773 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2774 | [(parallel | |
2775 | [(set (match_dup 6) (match_dup 7)) | |
2776 | (use (match_dup 8))])] | |
2777 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2778 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2779 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2780 | ||
f9dcf14a AK |
2781 | (define_peephole2 |
2782 | [(parallel | |
2783 | [(set (match_operand:BLK 0 "plus16_Q_operand" "") | |
2784 | (match_operand:BLK 1 "plus16_Q_operand" "")) | |
2785 | (use (match_operand 2 "const_int_operand" ""))])] | |
2786 | "INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32" | |
2787 | [(parallel | |
2788 | [(set (match_dup 0) (match_dup 1)) | |
2789 | (use (const_int 16))]) | |
2790 | (parallel | |
2791 | [(set (match_dup 3) (match_dup 4)) | |
2792 | (use (match_dup 5))])] | |
2793 | "operands[3] = change_address (operands[0], VOIDmode, | |
2794 | plus_constant (Pmode, XEXP (operands[0], 0), 16)); | |
2795 | operands[4] = change_address (operands[1], VOIDmode, | |
2796 | plus_constant (Pmode, XEXP (operands[1], 0), 16)); | |
2797 | operands[5] = GEN_INT (INTVAL (operands[2]) - 16);") | |
2798 | ||
19b63d8e | 2799 | |
9db1d521 HP |
2800 | ; |
2801 | ; load_multiple pattern(s). | |
2802 | ; | |
22ea6b4f UW |
2803 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2804 | ; we currently support load_multiple/store_multiple only after reload. | |
2805 | ; | |
9db1d521 HP |
2806 | |
2807 | (define_expand "load_multiple" | |
2808 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2809 | (match_operand 1 "" "")) | |
2810 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2811 | "reload_completed" |
9db1d521 | 2812 | { |
ef4bddc2 | 2813 | machine_mode mode; |
9db1d521 HP |
2814 | int regno; |
2815 | int count; | |
2816 | rtx from; | |
4023fb28 | 2817 | int i, off; |
9db1d521 HP |
2818 | |
2819 | /* Support only loading a constant number of fixed-point registers from | |
2820 | memory and only bother with this if more than two */ | |
2821 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2822 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2823 | || INTVAL (operands[2]) > 16 |
2824 | || GET_CODE (operands[1]) != MEM | |
2825 | || GET_CODE (operands[0]) != REG | |
2826 | || REGNO (operands[0]) >= 16) | |
2827 | FAIL; | |
2828 | ||
2829 | count = INTVAL (operands[2]); | |
2830 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2831 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2832 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2833 | FAIL; |
9db1d521 HP |
2834 | |
2835 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2836 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2837 | { |
2838 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2839 | { | |
2840 | from = XEXP (operands[1], 0); | |
2841 | off = 0; | |
2842 | } | |
2843 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2844 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2845 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2846 | { | |
2847 | from = XEXP (XEXP (operands[1], 0), 0); | |
2848 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2849 | } | |
2850 | else | |
2851 | FAIL; | |
4023fb28 UW |
2852 | } |
2853 | else | |
2854 | { | |
2855 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2856 | off = 0; | |
2857 | } | |
9db1d521 HP |
2858 | |
2859 | for (i = 0; i < count; i++) | |
2860 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2861 | = gen_rtx_SET (gen_rtx_REG (mode, regno + i), |
c19ec8f9 | 2862 | change_address (operands[1], mode, |
0a81f074 RS |
2863 | plus_constant (Pmode, from, |
2864 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2865 | }) |
9db1d521 HP |
2866 | |
2867 | (define_insn "*load_multiple_di" | |
2868 | [(match_parallel 0 "load_multiple_operation" | |
2869 | [(set (match_operand:DI 1 "register_operand" "=r") | |
3e4be43f | 2870 | (match_operand:DI 2 "s_operand" "S"))])] |
9602b6a1 | 2871 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2872 | { |
2873 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2874 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2875 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2876 | } |
d3632d41 | 2877 | [(set_attr "op_type" "RSY") |
4023fb28 | 2878 | (set_attr "type" "lm")]) |
9db1d521 HP |
2879 | |
2880 | (define_insn "*load_multiple_si" | |
2881 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2882 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2883 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2884 | "reload_completed" |
9db1d521 HP |
2885 | { |
2886 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2887 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2888 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2889 | } |
d3632d41 | 2890 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2891 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2892 | (set_attr "type" "lm")]) |
9db1d521 HP |
2893 | |
2894 | ; | |
c7453384 | 2895 | ; store multiple pattern(s). |
9db1d521 HP |
2896 | ; |
2897 | ||
2898 | (define_expand "store_multiple" | |
2899 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2900 | (match_operand 1 "" "")) | |
2901 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2902 | "reload_completed" |
9db1d521 | 2903 | { |
ef4bddc2 | 2904 | machine_mode mode; |
9db1d521 HP |
2905 | int regno; |
2906 | int count; | |
2907 | rtx to; | |
4023fb28 | 2908 | int i, off; |
9db1d521 HP |
2909 | |
2910 | /* Support only storing a constant number of fixed-point registers to | |
2911 | memory and only bother with this if more than two. */ | |
2912 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2913 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2914 | || INTVAL (operands[2]) > 16 |
2915 | || GET_CODE (operands[0]) != MEM | |
2916 | || GET_CODE (operands[1]) != REG | |
2917 | || REGNO (operands[1]) >= 16) | |
2918 | FAIL; | |
2919 | ||
2920 | count = INTVAL (operands[2]); | |
2921 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2922 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2923 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2924 | FAIL; |
9db1d521 HP |
2925 | |
2926 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2927 | |
b3a13419 | 2928 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2929 | { |
2930 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2931 | { | |
2932 | to = XEXP (operands[0], 0); | |
2933 | off = 0; | |
2934 | } | |
2935 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2936 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2937 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2938 | { | |
2939 | to = XEXP (XEXP (operands[0], 0), 0); | |
2940 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2941 | } | |
2942 | else | |
2943 | FAIL; | |
4023fb28 | 2944 | } |
c7453384 | 2945 | else |
4023fb28 UW |
2946 | { |
2947 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2948 | off = 0; | |
2949 | } | |
9db1d521 HP |
2950 | |
2951 | for (i = 0; i < count; i++) | |
2952 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2953 | = gen_rtx_SET (change_address (operands[0], mode, |
0a81f074 RS |
2954 | plus_constant (Pmode, to, |
2955 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2956 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2957 | }) |
9db1d521 HP |
2958 | |
2959 | (define_insn "*store_multiple_di" | |
2960 | [(match_parallel 0 "store_multiple_operation" | |
3e4be43f | 2961 | [(set (match_operand:DI 1 "s_operand" "=S") |
9db1d521 | 2962 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2963 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2964 | { |
2965 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2966 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2967 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2968 | } |
d3632d41 | 2969 | [(set_attr "op_type" "RSY") |
4023fb28 | 2970 | (set_attr "type" "stm")]) |
9db1d521 HP |
2971 | |
2972 | ||
2973 | (define_insn "*store_multiple_si" | |
2974 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2975 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2976 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2977 | "reload_completed" |
9db1d521 HP |
2978 | { |
2979 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2980 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2981 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2982 | } |
d3632d41 | 2983 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2984 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2985 | (set_attr "type" "stm")]) |
9db1d521 HP |
2986 | |
2987 | ;; | |
2988 | ;; String instructions. | |
2989 | ;; | |
2990 | ||
963fc8d0 | 2991 | (define_insn "*execute_rl" |
2771c2f9 | 2992 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2993 | [(unspec [(match_operand 1 "register_operand" "a") |
2994 | (match_operand 2 "" "") | |
2995 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2996 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2997 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2998 | "exrl\t%1,%3" | |
2999 | [(set_attr "op_type" "RIL") | |
14cfceb7 IL |
3000 | (set_attr "type" "cs") |
3001 | (set_attr "relative_long" "yes")]) | |
963fc8d0 | 3002 | |
9bb86f41 | 3003 | (define_insn "*execute" |
2771c2f9 | 3004 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
3005 | [(unspec [(match_operand 1 "register_operand" "a") |
3006 | (match_operand:BLK 2 "memory_operand" "R") | |
3007 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
3008 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
3009 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
3010 | "ex\t%1,%2" | |
29a74354 UW |
3011 | [(set_attr "op_type" "RX") |
3012 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
3013 | |
3014 | ||
91d39d71 UW |
3015 | ; |
3016 | ; strlenM instruction pattern(s). | |
3017 | ; | |
3018 | ||
9db2f16d | 3019 | (define_expand "strlen<mode>" |
085261c8 AK |
3020 | [(match_operand:P 0 "register_operand" "") ; result |
3021 | (match_operand:BLK 1 "memory_operand" "") ; input string | |
3022 | (match_operand:SI 2 "immediate_operand" "") ; search character | |
3023 | (match_operand:SI 3 "immediate_operand" "")] ; known alignment | |
3024 | "" | |
3025 | { | |
3026 | if (!TARGET_VX || operands[2] != const0_rtx) | |
3027 | emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], | |
3028 | operands[2], operands[3])); | |
3029 | else | |
3030 | s390_expand_vec_strlen (operands[0], operands[1], operands[3]); | |
3031 | ||
3032 | DONE; | |
3033 | }) | |
3034 | ||
3035 | (define_expand "strlen_srst<mode>" | |
ccbdc0d4 | 3036 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 3037 | (parallel |
91d39d71 | 3038 | [(set (match_dup 4) |
9db2f16d | 3039 | (unspec:P [(const_int 0) |
91d39d71 | 3040 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 3041 | (reg:SI 0) |
91d39d71 | 3042 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3043 | (clobber (scratch:P)) |
ae156f85 | 3044 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 3045 | (parallel |
9db2f16d AS |
3046 | [(set (match_operand:P 0 "register_operand" "") |
3047 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 3048 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 3049 | "" |
91d39d71 | 3050 | { |
9db2f16d AS |
3051 | operands[4] = gen_reg_rtx (Pmode); |
3052 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
3053 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3054 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
3055 | }) | |
3056 | ||
9db2f16d AS |
3057 | (define_insn "*strlen<mode>" |
3058 | [(set (match_operand:P 0 "register_operand" "=a") | |
3059 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
3060 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 3061 | (reg:SI 0) |
91d39d71 | 3062 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3063 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 3064 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 3065 | "" |
91d39d71 | 3066 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
3067 | [(set_attr "length" "8") |
3068 | (set_attr "type" "vs")]) | |
91d39d71 | 3069 | |
ccbdc0d4 AS |
3070 | ; |
3071 | ; cmpstrM instruction pattern(s). | |
3072 | ; | |
3073 | ||
3074 | (define_expand "cmpstrsi" | |
3075 | [(set (reg:SI 0) (const_int 0)) | |
3076 | (parallel | |
3077 | [(clobber (match_operand 3 "" "")) | |
3078 | (clobber (match_dup 4)) | |
3079 | (set (reg:CCU CC_REGNUM) | |
3080 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
3081 | (match_operand:BLK 2 "memory_operand" ""))) | |
3082 | (use (reg:SI 0))]) | |
3083 | (parallel | |
3084 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3085 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
3086 | (clobber (reg:CC CC_REGNUM))])] |
3087 | "" | |
3088 | { | |
3089 | /* As the result of CMPINT is inverted compared to what we need, | |
3090 | we have to swap the operands. */ | |
3091 | rtx op1 = operands[2]; | |
3092 | rtx op2 = operands[1]; | |
3093 | rtx addr1 = gen_reg_rtx (Pmode); | |
3094 | rtx addr2 = gen_reg_rtx (Pmode); | |
3095 | ||
3096 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
3097 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
3098 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
3099 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
3100 | operands[3] = addr1; | |
3101 | operands[4] = addr2; | |
3102 | }) | |
3103 | ||
3104 | (define_insn "*cmpstr<mode>" | |
3105 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
3106 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
3107 | (set (reg:CCU CC_REGNUM) | |
3108 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
3109 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
3110 | (use (reg:SI 0))] | |
3111 | "" | |
3112 | "clst\t%0,%1\;jo\t.-4" | |
3113 | [(set_attr "length" "8") | |
3114 | (set_attr "type" "vs")]) | |
9381e3f1 | 3115 | |
742090fc AS |
3116 | ; |
3117 | ; movstr instruction pattern. | |
3118 | ; | |
3119 | ||
3120 | (define_expand "movstr" | |
4a7dec25 DV |
3121 | [(match_operand 0 "register_operand" "") |
3122 | (match_operand 1 "memory_operand" "") | |
3123 | (match_operand 2 "memory_operand" "")] | |
3124 | "" | |
3125 | { | |
3126 | if (TARGET_64BIT) | |
3127 | emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); | |
3128 | else | |
3129 | emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); | |
3130 | DONE; | |
3131 | }) | |
3132 | ||
3133 | (define_expand "movstr<P:mode>" | |
742090fc | 3134 | [(set (reg:SI 0) (const_int 0)) |
9381e3f1 | 3135 | (parallel |
742090fc AS |
3136 | [(clobber (match_dup 3)) |
3137 | (set (match_operand:BLK 1 "memory_operand" "") | |
3138 | (match_operand:BLK 2 "memory_operand" "")) | |
4a7dec25 DV |
3139 | (set (match_operand:P 0 "register_operand" "") |
3140 | (unspec:P [(match_dup 1) | |
742090fc AS |
3141 | (match_dup 2) |
3142 | (reg:SI 0)] UNSPEC_MVST)) | |
3143 | (clobber (reg:CC CC_REGNUM))])] | |
3144 | "" | |
3145 | { | |
859a4c0e AK |
3146 | rtx addr1, addr2; |
3147 | ||
3148 | if (TARGET_VX && optimize_function_for_speed_p (cfun)) | |
3149 | { | |
3150 | s390_expand_vec_movstr (operands[0], operands[1], operands[2]); | |
3151 | DONE; | |
3152 | } | |
3153 | ||
3154 | addr1 = gen_reg_rtx (Pmode); | |
3155 | addr2 = gen_reg_rtx (Pmode); | |
742090fc AS |
3156 | |
3157 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
3158 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
3159 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3160 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
3161 | operands[3] = addr2; | |
3162 | }) | |
3163 | ||
3164 | (define_insn "*movstr" | |
3165 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
3166 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
3167 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
3168 | (set (match_operand:P 0 "register_operand" "=d") | |
4a7dec25 | 3169 | (unspec:P [(mem:BLK (match_dup 1)) |
742090fc AS |
3170 | (mem:BLK (match_dup 3)) |
3171 | (reg:SI 0)] UNSPEC_MVST)) | |
3172 | (clobber (reg:CC CC_REGNUM))] | |
3173 | "" | |
3174 | "mvst\t%1,%2\;jo\t.-4" | |
3175 | [(set_attr "length" "8") | |
3176 | (set_attr "type" "vs")]) | |
9381e3f1 | 3177 | |
742090fc | 3178 | |
9db1d521 | 3179 | ; |
70128ad9 | 3180 | ; movmemM instruction pattern(s). |
9db1d521 HP |
3181 | ; |
3182 | ||
9db2f16d | 3183 | (define_expand "movmem<mode>" |
963fc8d0 AK |
3184 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
3185 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
3186 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
3187 | (match_operand 3 "" "")] |
3188 | "" | |
367d32f3 AK |
3189 | { |
3190 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
3191 | DONE; | |
3192 | else | |
3193 | FAIL; | |
3194 | }) | |
9db1d521 | 3195 | |
ecbe845e UW |
3196 | ; Move a block that is up to 256 bytes in length. |
3197 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3198 | |
70128ad9 | 3199 | (define_expand "movmem_short" |
b9404c99 UW |
3200 | [(parallel |
3201 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3202 | (match_operand:BLK 1 "memory_operand" "")) | |
3203 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3204 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3205 | (clobber (match_dup 3))])] |
3206 | "" | |
3207 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 3208 | |
70128ad9 | 3209 | (define_insn "*movmem_short" |
963fc8d0 AK |
3210 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
3211 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
3212 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3213 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3214 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3215 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3216 | "#" |
963fc8d0 | 3217 | [(set_attr "type" "cs") |
b5e0425c | 3218 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 3219 | |
9bb86f41 UW |
3220 | (define_split |
3221 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3222 | (match_operand:BLK 1 "memory_operand" "")) | |
3223 | (use (match_operand 2 "const_int_operand" "")) | |
3224 | (use (match_operand 3 "immediate_operand" "")) | |
3225 | (clobber (scratch))] | |
3226 | "reload_completed" | |
3227 | [(parallel | |
3228 | [(set (match_dup 0) (match_dup 1)) | |
3229 | (use (match_dup 2))])] | |
3230 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3231 | |
9bb86f41 UW |
3232 | (define_split |
3233 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3234 | (match_operand:BLK 1 "memory_operand" "")) | |
3235 | (use (match_operand 2 "register_operand" "")) | |
3236 | (use (match_operand 3 "memory_operand" "")) | |
3237 | (clobber (scratch))] | |
3238 | "reload_completed" | |
3239 | [(parallel | |
3240 | [(unspec [(match_dup 2) (match_dup 3) | |
3241 | (const_int 0)] UNSPEC_EXECUTE) | |
3242 | (set (match_dup 0) (match_dup 1)) | |
3243 | (use (const_int 1))])] | |
3244 | "") | |
3245 | ||
963fc8d0 AK |
3246 | (define_split |
3247 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3248 | (match_operand:BLK 1 "memory_operand" "")) | |
3249 | (use (match_operand 2 "register_operand" "")) | |
3250 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3251 | (clobber (scratch))] | |
3252 | "TARGET_Z10 && reload_completed" | |
3253 | [(parallel | |
3254 | [(unspec [(match_dup 2) (const_int 0) | |
3255 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3256 | (set (match_dup 0) (match_dup 1)) | |
3257 | (use (const_int 1))])] | |
3258 | "operands[3] = gen_label_rtx ();") | |
3259 | ||
9bb86f41 UW |
3260 | (define_split |
3261 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3262 | (match_operand:BLK 1 "memory_operand" "")) | |
3263 | (use (match_operand 2 "register_operand" "")) | |
3264 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3265 | (clobber (match_operand 3 "register_operand" ""))] | |
8cc6307c | 3266 | "reload_completed" |
9bb86f41 UW |
3267 | [(set (match_dup 3) (label_ref (match_dup 4))) |
3268 | (parallel | |
9381e3f1 | 3269 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
3270 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
3271 | (set (match_dup 0) (match_dup 1)) | |
3272 | (use (const_int 1))])] | |
3273 | "operands[4] = gen_label_rtx ();") | |
3274 | ||
a41c6c53 | 3275 | ; Move a block of arbitrary length. |
9db1d521 | 3276 | |
70128ad9 | 3277 | (define_expand "movmem_long" |
b9404c99 UW |
3278 | [(parallel |
3279 | [(clobber (match_dup 2)) | |
3280 | (clobber (match_dup 3)) | |
3281 | (set (match_operand:BLK 0 "memory_operand" "") | |
3282 | (match_operand:BLK 1 "memory_operand" "")) | |
3283 | (use (match_operand 2 "general_operand" "")) | |
3284 | (use (match_dup 3)) | |
ae156f85 | 3285 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3286 | "" |
3287 | { | |
ef4bddc2 RS |
3288 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3289 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3290 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3291 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3292 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3293 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3294 | rtx len0 = gen_lowpart (Pmode, reg0); |
3295 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3296 | ||
c41c1387 | 3297 | emit_clobber (reg0); |
b9404c99 UW |
3298 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3299 | emit_move_insn (len0, operands[2]); | |
3300 | ||
c41c1387 | 3301 | emit_clobber (reg1); |
b9404c99 UW |
3302 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3303 | emit_move_insn (len1, operands[2]); | |
3304 | ||
3305 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3306 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3307 | operands[2] = reg0; | |
3308 | operands[3] = reg1; | |
3309 | }) | |
3310 | ||
a1aed706 AS |
3311 | (define_insn "*movmem_long" |
3312 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3313 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3314 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3315 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
3316 | (use (match_dup 2)) |
3317 | (use (match_dup 3)) | |
ae156f85 | 3318 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
3319 | "TARGET_64BIT || !TARGET_ZARCH" |
3320 | "mvcle\t%0,%1,0\;jo\t.-4" | |
3321 | [(set_attr "length" "8") | |
3322 | (set_attr "type" "vs")]) | |
3323 | ||
3324 | (define_insn "*movmem_long_31z" | |
3325 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3326 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3327 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3328 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
3329 | (use (match_dup 2)) | |
3330 | (use (match_dup 3)) | |
3331 | (clobber (reg:CC CC_REGNUM))] | |
3332 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 3333 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3334 | [(set_attr "length" "8") |
3335 | (set_attr "type" "vs")]) | |
9db1d521 | 3336 | |
638e37c2 WG |
3337 | |
3338 | ; | |
3339 | ; Test data class. | |
3340 | ; | |
3341 | ||
0f67fa83 WG |
3342 | (define_expand "signbit<mode>2" |
3343 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3344 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3345 | (match_dup 2)] | |
0f67fa83 WG |
3346 | UNSPEC_TDC_INSN)) |
3347 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3348 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
3349 | "TARGET_HARD_FLOAT" |
3350 | { | |
3351 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
3352 | }) | |
3353 | ||
638e37c2 WG |
3354 | (define_expand "isinf<mode>2" |
3355 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3356 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3357 | (match_dup 2)] | |
638e37c2 WG |
3358 | UNSPEC_TDC_INSN)) |
3359 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3360 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 3361 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
3362 | { |
3363 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
3364 | }) | |
3365 | ||
085261c8 AK |
3366 | ; This extracts CC into a GPR properly shifted. The actual IPM |
3367 | ; instruction will be issued by reload. The constraint of operand 1 | |
3368 | ; forces reload to use a GPR. So reload will issue a movcc insn for | |
3369 | ; copying CC into a GPR first. | |
5a3fe9b6 | 3370 | (define_insn_and_split "*cc_to_int" |
085261c8 | 3371 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
5a3fe9b6 AK |
3372 | (unspec:SI [(match_operand 1 "register_operand" "0")] |
3373 | UNSPEC_CC_TO_INT))] | |
3374 | "operands != NULL" | |
3375 | "#" | |
3376 | "reload_completed" | |
3377 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
3378 | ||
638e37c2 WG |
3379 | ; This insn is used to generate all variants of the Test Data Class |
3380 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
3381 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 3382 | ; specifying the required test(s). |
638e37c2 | 3383 | ; |
be5de7a1 | 3384 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
3385 | (define_insn "*TDC_insn_<mode>" |
3386 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 3387 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 3388 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 3389 | "TARGET_HARD_FLOAT" |
0387c142 | 3390 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 3391 | [(set_attr "op_type" "RXE") |
9381e3f1 | 3392 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 3393 | |
638e37c2 WG |
3394 | |
3395 | ||
9db1d521 | 3396 | ; |
57e84f18 | 3397 | ; setmemM instruction pattern(s). |
9db1d521 HP |
3398 | ; |
3399 | ||
57e84f18 | 3400 | (define_expand "setmem<mode>" |
a41c6c53 | 3401 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 3402 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 3403 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 3404 | (match_operand 3 "" "")] |
a41c6c53 | 3405 | "" |
6d057022 | 3406 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 3407 | |
a41c6c53 | 3408 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
3409 | ; The block length is taken as (operands[1] % 256) + 1. |
3410 | ||
70128ad9 | 3411 | (define_expand "clrmem_short" |
b9404c99 UW |
3412 | [(parallel |
3413 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3414 | (const_int 0)) | |
3415 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 3416 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 3417 | (clobber (match_dup 2)) |
ae156f85 | 3418 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3419 | "" |
3420 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3421 | |
70128ad9 | 3422 | (define_insn "*clrmem_short" |
963fc8d0 | 3423 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 3424 | (const_int 0)) |
963fc8d0 AK |
3425 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
3426 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 3427 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 3428 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 3429 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 3430 | "#" |
963fc8d0 | 3431 | [(set_attr "type" "cs") |
b5e0425c | 3432 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
3433 | |
3434 | (define_split | |
3435 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3436 | (const_int 0)) | |
3437 | (use (match_operand 1 "const_int_operand" "")) | |
3438 | (use (match_operand 2 "immediate_operand" "")) | |
3439 | (clobber (scratch)) | |
ae156f85 | 3440 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3441 | "reload_completed" |
3442 | [(parallel | |
3443 | [(set (match_dup 0) (const_int 0)) | |
3444 | (use (match_dup 1)) | |
ae156f85 | 3445 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3446 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 3447 | |
9bb86f41 UW |
3448 | (define_split |
3449 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3450 | (const_int 0)) | |
3451 | (use (match_operand 1 "register_operand" "")) | |
3452 | (use (match_operand 2 "memory_operand" "")) | |
3453 | (clobber (scratch)) | |
ae156f85 | 3454 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3455 | "reload_completed" |
3456 | [(parallel | |
3457 | [(unspec [(match_dup 1) (match_dup 2) | |
3458 | (const_int 0)] UNSPEC_EXECUTE) | |
3459 | (set (match_dup 0) (const_int 0)) | |
3460 | (use (const_int 1)) | |
ae156f85 | 3461 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3462 | "") |
9db1d521 | 3463 | |
963fc8d0 AK |
3464 | (define_split |
3465 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3466 | (const_int 0)) | |
3467 | (use (match_operand 1 "register_operand" "")) | |
3468 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3469 | (clobber (scratch)) | |
3470 | (clobber (reg:CC CC_REGNUM))] | |
3471 | "TARGET_Z10 && reload_completed" | |
3472 | [(parallel | |
3473 | [(unspec [(match_dup 1) (const_int 0) | |
3474 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3475 | (set (match_dup 0) (const_int 0)) | |
3476 | (use (const_int 1)) | |
3477 | (clobber (reg:CC CC_REGNUM))])] | |
3478 | "operands[3] = gen_label_rtx ();") | |
3479 | ||
9bb86f41 UW |
3480 | (define_split |
3481 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3482 | (const_int 0)) | |
3483 | (use (match_operand 1 "register_operand" "")) | |
3484 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3485 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3486 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 3487 | "reload_completed" |
9bb86f41 UW |
3488 | [(set (match_dup 2) (label_ref (match_dup 3))) |
3489 | (parallel | |
9381e3f1 | 3490 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3491 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3492 | (set (match_dup 0) (const_int 0)) | |
3493 | (use (const_int 1)) | |
ae156f85 | 3494 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3495 | "operands[3] = gen_label_rtx ();") |
3496 | ||
9381e3f1 | 3497 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3498 | |
da0dcab1 | 3499 | (define_expand "setmem_long_<P:mode>" |
b9404c99 UW |
3500 | [(parallel |
3501 | [(clobber (match_dup 1)) | |
3502 | (set (match_operand:BLK 0 "memory_operand" "") | |
dd95128b | 3503 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "") |
da0dcab1 | 3504 | (match_dup 4)] UNSPEC_REPLICATE_BYTE)) |
6d057022 | 3505 | (use (match_dup 3)) |
ae156f85 | 3506 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3507 | "" |
a41c6c53 | 3508 | { |
ef4bddc2 RS |
3509 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3510 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3511 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3512 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3513 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3514 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3515 | |
c41c1387 | 3516 | emit_clobber (reg0); |
b9404c99 UW |
3517 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3518 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3519 | |
b9404c99 | 3520 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3521 | |
b9404c99 UW |
3522 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3523 | operands[1] = reg0; | |
6d057022 | 3524 | operands[3] = reg1; |
da0dcab1 | 3525 | operands[4] = gen_lowpart (Pmode, operands[1]); |
b9404c99 | 3526 | }) |
a41c6c53 | 3527 | |
da0dcab1 DV |
3528 | ; Patterns for 31 bit + Esa and 64 bit + Zarch. |
3529 | ||
db340c73 | 3530 | (define_insn "*setmem_long" |
a1aed706 | 3531 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3532 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
dd95128b | 3533 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y") |
da0dcab1 DV |
3534 | (subreg:P (match_dup 3) <modesize>)] |
3535 | UNSPEC_REPLICATE_BYTE)) | |
a1aed706 | 3536 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3537 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3538 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3539 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3540 | [(set_attr "length" "8") |
3541 | (set_attr "type" "vs")]) | |
9db1d521 | 3542 | |
db340c73 AK |
3543 | (define_insn "*setmem_long_and" |
3544 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3545 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
d876f5cd | 3546 | (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3547 | (subreg:P (match_dup 3) <modesize>)] |
3548 | UNSPEC_REPLICATE_BYTE)) | |
3549 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3550 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3551 | "(TARGET_64BIT || !TARGET_ZARCH)" |
db340c73 AK |
3552 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3553 | [(set_attr "length" "8") | |
3554 | (set_attr "type" "vs")]) | |
3555 | ||
da0dcab1 DV |
3556 | ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets |
3557 | ; of the SImode subregs. | |
3558 | ||
db340c73 | 3559 | (define_insn "*setmem_long_31z" |
9602b6a1 AK |
3560 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
3561 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
dd95128b | 3562 | (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y") |
da0dcab1 | 3563 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
9602b6a1 AK |
3564 | (use (match_operand:TI 1 "register_operand" "d")) |
3565 | (clobber (reg:CC CC_REGNUM))] | |
3566 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3567 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3568 | [(set_attr "length" "8") | |
3569 | (set_attr "type" "vs")]) | |
9602b6a1 | 3570 | |
db340c73 AK |
3571 | (define_insn "*setmem_long_and_31z" |
3572 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3573 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
d876f5cd | 3574 | (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3575 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
3576 | (use (match_operand:TI 1 "register_operand" "d")) | |
3577 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3578 | "(!TARGET_64BIT && TARGET_ZARCH)" |
db340c73 AK |
3579 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3580 | [(set_attr "length" "8") | |
3581 | (set_attr "type" "vs")]) | |
3582 | ||
9db1d521 | 3583 | ; |
358b8f01 | 3584 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3585 | ; |
3586 | ||
358b8f01 | 3587 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3588 | [(set (match_operand:SI 0 "register_operand" "") |
3589 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3590 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3591 | (use (match_operand:SI 3 "general_operand" "")) | |
3592 | (use (match_operand:SI 4 "" ""))] | |
3593 | "" | |
367d32f3 AK |
3594 | { |
3595 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3596 | operands[2], operands[3])) | |
3597 | DONE; | |
3598 | else | |
3599 | FAIL; | |
3600 | }) | |
9db1d521 | 3601 | |
a41c6c53 UW |
3602 | ; Compare a block that is up to 256 bytes in length. |
3603 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3604 | |
b9404c99 UW |
3605 | (define_expand "cmpmem_short" |
3606 | [(parallel | |
ae156f85 | 3607 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3608 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3609 | (match_operand:BLK 1 "memory_operand" ""))) |
3610 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3611 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3612 | (clobber (match_dup 3))])] |
3613 | "" | |
3614 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3615 | |
b9404c99 | 3616 | (define_insn "*cmpmem_short" |
ae156f85 | 3617 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3618 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3619 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3620 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3621 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3622 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3623 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3624 | "#" |
963fc8d0 | 3625 | [(set_attr "type" "cs") |
b5e0425c | 3626 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3627 | |
9bb86f41 | 3628 | (define_split |
ae156f85 | 3629 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3630 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3631 | (match_operand:BLK 1 "memory_operand" ""))) | |
3632 | (use (match_operand 2 "const_int_operand" "")) | |
3633 | (use (match_operand 3 "immediate_operand" "")) | |
3634 | (clobber (scratch))] | |
3635 | "reload_completed" | |
3636 | [(parallel | |
ae156f85 | 3637 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3638 | (use (match_dup 2))])] |
3639 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3640 | |
9bb86f41 | 3641 | (define_split |
ae156f85 | 3642 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3643 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3644 | (match_operand:BLK 1 "memory_operand" ""))) | |
3645 | (use (match_operand 2 "register_operand" "")) | |
3646 | (use (match_operand 3 "memory_operand" "")) | |
3647 | (clobber (scratch))] | |
3648 | "reload_completed" | |
3649 | [(parallel | |
3650 | [(unspec [(match_dup 2) (match_dup 3) | |
3651 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3652 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3653 | (use (const_int 1))])] |
3654 | "") | |
3655 | ||
963fc8d0 AK |
3656 | (define_split |
3657 | [(set (reg:CCU CC_REGNUM) | |
3658 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3659 | (match_operand:BLK 1 "memory_operand" ""))) | |
3660 | (use (match_operand 2 "register_operand" "")) | |
3661 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3662 | (clobber (scratch))] | |
3663 | "TARGET_Z10 && reload_completed" | |
3664 | [(parallel | |
3665 | [(unspec [(match_dup 2) (const_int 0) | |
3666 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3667 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3668 | (use (const_int 1))])] | |
3669 | "operands[4] = gen_label_rtx ();") | |
3670 | ||
9bb86f41 | 3671 | (define_split |
ae156f85 | 3672 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3673 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3674 | (match_operand:BLK 1 "memory_operand" ""))) | |
3675 | (use (match_operand 2 "register_operand" "")) | |
3676 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3677 | (clobber (match_operand 3 "register_operand" ""))] | |
8cc6307c | 3678 | "reload_completed" |
9bb86f41 UW |
3679 | [(set (match_dup 3) (label_ref (match_dup 4))) |
3680 | (parallel | |
9381e3f1 | 3681 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3682 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3683 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3684 | (use (const_int 1))])] |
3685 | "operands[4] = gen_label_rtx ();") | |
3686 | ||
a41c6c53 | 3687 | ; Compare a block of arbitrary length. |
9db1d521 | 3688 | |
b9404c99 UW |
3689 | (define_expand "cmpmem_long" |
3690 | [(parallel | |
3691 | [(clobber (match_dup 2)) | |
3692 | (clobber (match_dup 3)) | |
ae156f85 | 3693 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3694 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3695 | (match_operand:BLK 1 "memory_operand" ""))) |
3696 | (use (match_operand 2 "general_operand" "")) | |
3697 | (use (match_dup 3))])] | |
3698 | "" | |
3699 | { | |
ef4bddc2 RS |
3700 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3701 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3702 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3703 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3704 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3705 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3706 | rtx len0 = gen_lowpart (Pmode, reg0); |
3707 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3708 | ||
c41c1387 | 3709 | emit_clobber (reg0); |
b9404c99 UW |
3710 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3711 | emit_move_insn (len0, operands[2]); | |
3712 | ||
c41c1387 | 3713 | emit_clobber (reg1); |
b9404c99 UW |
3714 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3715 | emit_move_insn (len1, operands[2]); | |
3716 | ||
3717 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3718 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3719 | operands[2] = reg0; | |
3720 | operands[3] = reg1; | |
3721 | }) | |
3722 | ||
a1aed706 AS |
3723 | (define_insn "*cmpmem_long" |
3724 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3725 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3726 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3727 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3728 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3729 | (use (match_dup 2)) |
3730 | (use (match_dup 3))] | |
9602b6a1 | 3731 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3732 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3733 | [(set_attr "length" "8") |
3734 | (set_attr "type" "vs")]) | |
9db1d521 | 3735 | |
9602b6a1 AK |
3736 | (define_insn "*cmpmem_long_31z" |
3737 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3738 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3739 | (set (reg:CCU CC_REGNUM) | |
3740 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3741 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3742 | (use (match_dup 2)) | |
3743 | (use (match_dup 3))] | |
3744 | "!TARGET_64BIT && TARGET_ZARCH" | |
3745 | "clcle\t%0,%1,0\;jo\t.-4" | |
3746 | [(set_attr "op_type" "NN") | |
3747 | (set_attr "type" "vs") | |
3748 | (set_attr "length" "8")]) | |
3749 | ||
02887425 UW |
3750 | ; Convert CCUmode condition code to integer. |
3751 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3752 | |
02887425 | 3753 | (define_insn_and_split "cmpint" |
9db1d521 | 3754 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3755 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3756 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3757 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3758 | "" |
02887425 UW |
3759 | "#" |
3760 | "reload_completed" | |
3761 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3762 | (parallel | |
3763 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3764 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3765 | |
3766 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3767 | [(set (reg CC_REGNUM) |
02887425 | 3768 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3769 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3770 | (const_int 0))) |
3771 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3772 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3773 | "s390_match_ccmode (insn, CCSmode)" |
3774 | "#" | |
3775 | "&& reload_completed" | |
3776 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3777 | (parallel | |
3778 | [(set (match_dup 2) (match_dup 3)) | |
3779 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3780 | { |
02887425 UW |
3781 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3782 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3783 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3784 | }) | |
9db1d521 | 3785 | |
02887425 | 3786 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3787 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3788 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3789 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3790 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3791 | "TARGET_ZARCH" |
02887425 UW |
3792 | "#" |
3793 | "&& reload_completed" | |
3794 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3795 | (parallel | |
3796 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3797 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3798 | |
3799 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3800 | [(set (reg CC_REGNUM) |
9381e3f1 | 3801 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3802 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3803 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3804 | (const_int 32)) (const_int 32)) |
3805 | (const_int 0))) | |
3806 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3807 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3808 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3809 | "#" |
3810 | "&& reload_completed" | |
3811 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3812 | (parallel | |
3813 | [(set (match_dup 2) (match_dup 3)) | |
3814 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3815 | { |
02887425 UW |
3816 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3817 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3818 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3819 | }) | |
9db1d521 | 3820 | |
4023fb28 | 3821 | |
9db1d521 HP |
3822 | ;; |
3823 | ;;- Conversion instructions. | |
3824 | ;; | |
3825 | ||
6fa05db6 | 3826 | (define_insn "*sethighpartsi" |
d3632d41 | 3827 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3828 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3829 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3830 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3831 | "" |
d3632d41 | 3832 | "@ |
6fa05db6 AS |
3833 | icm\t%0,%2,%S1 |
3834 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3835 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3836 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 3837 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
4023fb28 | 3838 | |
6fa05db6 | 3839 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3840 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 3841 | (unspec:DI [(match_operand:BLK 1 "s_operand" "S") |
6fa05db6 | 3842 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) |
ae156f85 | 3843 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3844 | "TARGET_ZARCH" |
6fa05db6 | 3845 | "icmh\t%0,%2,%S1" |
729e750f WG |
3846 | [(set_attr "op_type" "RSY") |
3847 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3848 | |
6fa05db6 | 3849 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3850 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3851 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3852 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3853 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3854 | "!TARGET_ZARCH" |
d3632d41 | 3855 | "@ |
6fa05db6 AS |
3856 | icm\t%0,%2,%S1 |
3857 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3858 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3859 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 WG |
3860 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
3861 | ||
1a2e356e RH |
3862 | ; |
3863 | ; extv instruction patterns | |
3864 | ; | |
3865 | ||
3866 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3867 | ; after resolving some issues with it. | |
3868 | ||
3869 | (define_expand "extzv" | |
3870 | [(parallel | |
3871 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3872 | (zero_extract:DI | |
3873 | (match_operand:DI 1 "register_operand" "d") | |
3874 | (match_operand 2 "const_int_operand" "") ; size | |
3875 | (match_operand 3 "const_int_operand" ""))) ; start | |
3876 | (clobber (reg:CC CC_REGNUM))])] | |
3877 | "TARGET_Z10" | |
3878 | { | |
0f6f72e8 DV |
3879 | if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64)) |
3880 | FAIL; | |
1a2e356e RH |
3881 | /* Starting with zEC12 there is risbgn not clobbering CC. */ |
3882 | if (TARGET_ZEC12) | |
3883 | { | |
3884 | emit_move_insn (operands[0], | |
3885 | gen_rtx_ZERO_EXTRACT (DImode, | |
3886 | operands[1], | |
3887 | operands[2], | |
3888 | operands[3])); | |
3889 | DONE; | |
3890 | } | |
3891 | }) | |
3892 | ||
64c744b9 | 3893 | (define_insn "*extzv<mode><clobbercc_or_nocc>" |
1a2e356e RH |
3894 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3895 | (zero_extract:GPR | |
3896 | (match_operand:GPR 1 "register_operand" "d") | |
3897 | (match_operand 2 "const_int_operand" "") ; size | |
64c744b9 DV |
3898 | (match_operand 3 "const_int_operand" ""))) ; start |
3899 | ] | |
0f6f72e8 DV |
3900 | "<z10_or_zEC12_cond> |
3901 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), | |
3902 | GET_MODE_BITSIZE (<MODE>mode))" | |
64c744b9 DV |
3903 | "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift |
3904 | [(set_attr "op_type" "RIE") | |
3905 | (set_attr "z10prop" "z10_super_E1")]) | |
1a2e356e | 3906 | |
64c744b9 DV |
3907 | ; 64 bit: (a & -16) | ((b >> 8) & 15) |
3908 | (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt" | |
3909 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3910 | (match_operand 1 "const_int_operand" "") ; size | |
3911 | (match_operand 2 "const_int_operand" "")) ; start | |
3912 | (lshiftrt:DI (match_operand:DI 3 "register_operand" "d") | |
3913 | (match_operand:DI 4 "nonzero_shift_count_operand" "")))] | |
3914 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3915 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
64c744b9 DV |
3916 | && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])" |
3917 | "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4" | |
3918 | [(set_attr "op_type" "RIE") | |
3919 | (set_attr "z10prop" "z10_super_E1")]) | |
3920 | ||
3921 | ; 32 bit: (a & -16) | ((b >> 8) & 15) | |
3922 | (define_insn "*<risbg_n>_ior_and_sr_ze" | |
3923 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3924 | (ior:SI (and:SI | |
3925 | (match_operand:SI 1 "register_operand" "0") | |
3926 | (match_operand:SI 2 "const_int_operand" "")) | |
3927 | (subreg:SI | |
3928 | (zero_extract:DI | |
3929 | (match_operand:DI 3 "register_operand" "d") | |
3930 | (match_operand 4 "const_int_operand" "") ; size | |
3931 | (match_operand 5 "const_int_operand" "")) ; start | |
3932 | 4)))] | |
3933 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3934 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64) |
64c744b9 DV |
3935 | && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))" |
3936 | "<risbg_n>\t%0,%3,64-%4,63,%4+%5" | |
3937 | [(set_attr "op_type" "RIE") | |
3938 | (set_attr "z10prop" "z10_super_E1")]) | |
3939 | ||
3940 | ; ((int)foo >> 10) & 1; | |
3941 | (define_insn "*extract1bitdi<clobbercc_or_nocc>" | |
3942 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3943 | (ne:DI (zero_extract:DI | |
3944 | (match_operand:DI 1 "register_operand" "d") | |
3945 | (const_int 1) ; size | |
3946 | (match_operand 2 "const_int_operand" "")) ; start | |
3947 | (const_int 0)))] | |
0f6f72e8 DV |
3948 | "<z10_or_zEC12_cond> |
3949 | && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)" | |
64c744b9 DV |
3950 | "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift |
3951 | [(set_attr "op_type" "RIE") | |
3952 | (set_attr "z10prop" "z10_super_E1")]) | |
3953 | ||
3954 | (define_insn "*<risbg_n>_and_subregdi_rotr" | |
3955 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3956 | (and:DI (subreg:DI | |
3957 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3958 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3959 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3960 | "<z10_or_zEC12_cond> | |
3961 | && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))" | |
3962 | "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift | |
3963 | [(set_attr "op_type" "RIE") | |
3964 | (set_attr "z10prop" "z10_super_E1")]) | |
3965 | ||
3966 | (define_insn "*<risbg_n>_and_subregdi_rotl" | |
3967 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3968 | (and:DI (subreg:DI | |
3969 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3970 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3971 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3972 | "<z10_or_zEC12_cond> | |
3973 | && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))" | |
3974 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
3975 | [(set_attr "op_type" "RIE") | |
3976 | (set_attr "z10prop" "z10_super_E1")]) | |
3977 | ||
3978 | (define_insn "*<risbg_n>_di_and_rot" | |
3979 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3980 | (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
3981 | (match_operand:DI 2 "const_int_operand" "")) | |
3982 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3983 | "<z10_or_zEC12_cond>" | |
3984 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
1a2e356e RH |
3985 | [(set_attr "op_type" "RIE") |
3986 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 3987 | |
1a2e356e | 3988 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 | 3989 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 3990 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 3991 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3992 | (const_int 0))) |
ae156f85 | 3993 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3994 | "!TARGET_Z10" |
cc7ab9b7 UW |
3995 | "#" |
3996 | "&& reload_completed" | |
4023fb28 | 3997 | [(parallel |
6fa05db6 | 3998 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3999 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 4000 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 4001 | { |
6fa05db6 AS |
4002 | int bitsize = INTVAL (operands[2]); |
4003 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
4004 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
4005 | ||
4006 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4007 | set_mem_size (operands[1], size); |
2542ef05 | 4008 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 4009 | operands[3] = GEN_INT (mask); |
b628bd8e | 4010 | }) |
4023fb28 | 4011 | |
1a2e356e | 4012 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 | 4013 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 4014 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 4015 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 4016 | (const_int 0))) |
ae156f85 | 4017 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 4018 | "" |
cc7ab9b7 UW |
4019 | "#" |
4020 | "&& reload_completed" | |
4023fb28 | 4021 | [(parallel |
6fa05db6 | 4022 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 4023 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
4024 | (parallel |
4025 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
4026 | (clobber (reg:CC CC_REGNUM))])] | |
4027 | { | |
4028 | int bitsize = INTVAL (operands[2]); | |
4029 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
4030 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
4031 | ||
4032 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4033 | set_mem_size (operands[1], size); |
2542ef05 | 4034 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
4035 | operands[3] = GEN_INT (mask); |
4036 | }) | |
4037 | ||
4038 | ; | |
4039 | ; insv instruction patterns | |
4040 | ; | |
4041 | ||
4042 | (define_expand "insv" | |
4043 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
4044 | (match_operand 1 "const_int_operand" "") | |
4045 | (match_operand 2 "const_int_operand" "")) | |
4046 | (match_operand 3 "general_operand" ""))] | |
4047 | "" | |
4023fb28 | 4048 | { |
6fa05db6 AS |
4049 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
4050 | DONE; | |
4051 | FAIL; | |
b628bd8e | 4052 | }) |
4023fb28 | 4053 | |
2542ef05 RH |
4054 | |
4055 | ; The normal RTL expansion will never generate a zero_extract where | |
4056 | ; the location operand isn't word mode. However, we do this in the | |
4057 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
64c744b9 | 4058 | (define_insn "*insv<mode><clobbercc_or_nocc>" |
22ac2c2f | 4059 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") |
2542ef05 RH |
4060 | (match_operand 1 "const_int_operand" "I") ; size |
4061 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f | 4062 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
64c744b9 | 4063 | "<z10_or_zEC12_cond> |
0f6f72e8 DV |
4064 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), |
4065 | GET_MODE_BITSIZE (<MODE>mode)) | |
2542ef05 | 4066 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
64c744b9 | 4067 | "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1" |
9381e3f1 WG |
4068 | [(set_attr "op_type" "RIE") |
4069 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4070 | |
22ac2c2f AK |
4071 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
4072 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
64c744b9 DV |
4073 | (define_insn "*insv<mode><clobbercc_or_nocc>_noshift" |
4074 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d") | |
4075 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0") | |
75ca1b39 | 4076 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
64c744b9 | 4077 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d") |
75ca1b39 | 4078 | (match_operand:GPR 4 "const_int_operand" ""))))] |
64c744b9 DV |
4079 | "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
4080 | "@ | |
4081 | <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0 | |
4082 | <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0" | |
4083 | [(set_attr "op_type" "RIE") | |
4084 | (set_attr "z10prop" "z10_super_E1")]) | |
22ac2c2f | 4085 | |
64c744b9 DV |
4086 | (define_insn "*insv_z10_noshift_cc" |
4087 | [(set (reg CC_REGNUM) | |
4088 | (compare | |
4089 | (ior:DI | |
4090 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4091 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4092 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4093 | (match_operand:DI 4 "const_int_operand" ""))) | |
4094 | (const_int 0))) | |
4095 | (set (match_operand:DI 0 "nonimmediate_operand" "=d,d") | |
4096 | (ior:DI (and:DI (match_dup 1) (match_dup 2)) | |
4097 | (and:DI (match_dup 3) (match_dup 4))))] | |
4098 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4099 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4100 | "@ | |
4101 | risbg\t%0,%1,%s2,%e2,0 | |
4102 | risbg\t%0,%3,%s4,%e4,0" | |
4103 | [(set_attr "op_type" "RIE") | |
4104 | (set_attr "z10prop" "z10_super_E1")]) | |
4105 | ||
4106 | (define_insn "*insv_z10_noshift_cconly" | |
4107 | [(set | |
4108 | (reg CC_REGNUM) | |
4109 | (compare | |
4110 | (ior:DI | |
4111 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4112 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4113 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4114 | (match_operand:DI 4 "const_int_operand" ""))) | |
4115 | (const_int 0))) | |
4116 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4117 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4118 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4119 | "@ | |
4120 | risbg\t%0,%1,%s2,%e2,0 | |
4121 | risbg\t%0,%3,%s4,%e4,0" | |
9381e3f1 WG |
4122 | [(set_attr "op_type" "RIE") |
4123 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4124 | |
3d44ff99 AK |
4125 | ; Implement appending Y on the left of S bits of X |
4126 | ; x = (y << s) | (x & ((1 << s) - 1)) | |
64c744b9 | 4127 | (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft" |
3d44ff99 AK |
4128 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4129 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
4130 | (match_operand:GPR 2 "immediate_operand" "")) | |
4131 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
4132 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
64c744b9 DV |
4133 | "<z10_or_zEC12_cond> |
4134 | && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
4135 | "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4" | |
3d44ff99 AK |
4136 | [(set_attr "op_type" "RIE") |
4137 | (set_attr "z10prop" "z10_super_E1")]) | |
4138 | ||
64c744b9 DV |
4139 | ; a = ((i32)a & -16777216) | (((ui32)b) >> 8) |
4140 | (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt" | |
4141 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4142 | (ior:GPR (and:GPR | |
4143 | (match_operand:GPR 1 "register_operand" "0") | |
4144 | (match_operand:GPR 2 "const_int_operand" "")) | |
4145 | (lshiftrt:GPR | |
4146 | (match_operand:GPR 3 "register_operand" "d") | |
4147 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4148 | "<z10_or_zEC12_cond> && UINTVAL (operands[2]) | |
4149 | == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))" | |
4150 | "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4" | |
4151 | [(set_attr "op_type" "RIE") | |
4152 | (set_attr "z10prop" "z10_super_E1")]) | |
4153 | ||
4154 | ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536); | |
4155 | (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt" | |
4156 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4157 | (ior:SI (and:SI | |
4158 | (match_operand:SI 1 "register_operand" "0") | |
4159 | (match_operand:SI 2 "const_int_operand" "")) | |
4160 | (subreg:SI | |
4161 | (lshiftrt:DI | |
4162 | (match_operand:DI 3 "register_operand" "d") | |
4163 | (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))] | |
4164 | "<z10_or_zEC12_cond> | |
4165 | && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))" | |
4166 | "<risbg_n>\t%0,%3,%4,63,64-%4" | |
4167 | [(set_attr "op_type" "RIE") | |
4168 | (set_attr "z10prop" "z10_super_E1")]) | |
4169 | ||
4170 | ; (ui32)(((ui64)x) >> 12) & -4 | |
4171 | (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>" | |
4172 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4173 | (and:SI | |
4174 | (subreg:SI (lshiftrt:DI | |
4175 | (match_operand:DI 1 "register_operand" "d") | |
4176 | (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4) | |
4177 | (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))] | |
4178 | "<z10_or_zEC12_cond>" | |
4179 | "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2" | |
3d44ff99 AK |
4180 | [(set_attr "op_type" "RIE") |
4181 | (set_attr "z10prop" "z10_super_E1")]) | |
4182 | ||
4183 | ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting | |
4184 | ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) | |
4185 | ; -> z = y >> d; z = risbg; | |
4186 | ||
4187 | (define_split | |
4188 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4189 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4190 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4191 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4192 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4193 | "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4194 | [(set (match_dup 6) |
3d44ff99 AK |
4195 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4196 | (set (match_dup 0) | |
1d11f7ce | 4197 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4198 | (ashift:GPR (match_dup 3) (match_dup 4))))] |
4199 | { | |
4200 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3168e073 | 4201 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4202 | { |
4203 | if (!can_create_pseudo_p ()) | |
4204 | FAIL; | |
4205 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4206 | } | |
4207 | else | |
4208 | operands[6] = operands[0]; | |
3d44ff99 AK |
4209 | }) |
4210 | ||
4211 | (define_split | |
4212 | [(parallel | |
4213 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4214 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4215 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4216 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4217 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
4218 | (clobber (reg:CC CC_REGNUM))])] | |
4219 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4220 | [(set (match_dup 6) |
3d44ff99 AK |
4221 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4222 | (parallel | |
4223 | [(set (match_dup 0) | |
1d11f7ce | 4224 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4225 | (ashift:GPR (match_dup 3) (match_dup 4)))) |
4226 | (clobber (reg:CC CC_REGNUM))])] | |
4227 | { | |
4228 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3168e073 | 4229 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4230 | { |
4231 | if (!can_create_pseudo_p ()) | |
4232 | FAIL; | |
4233 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4234 | } | |
4235 | else | |
4236 | operands[6] = operands[0]; | |
3d44ff99 AK |
4237 | }) |
4238 | ||
50dc4eed | 4239 | ; rosbg, rxsbg |
571e408a | 4240 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 4241 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
4242 | (IXOR:GPR |
4243 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4244 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
4245 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 4246 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 4247 | "TARGET_Z10" |
571e408a RH |
4248 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
4249 | [(set_attr "op_type" "RIE")]) | |
4250 | ||
50dc4eed | 4251 | ; rosbg, rxsbg |
571e408a RH |
4252 | (define_insn "*r<noxa>sbg_di_rotl" |
4253 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
4254 | (IXOR:DI | |
4255 | (and:DI | |
4256 | (rotate:DI | |
4257 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4258 | (match_operand:DI 3 "const_int_operand" "")) | |
4259 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4260 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
4261 | (clobber (reg:CC CC_REGNUM))] | |
4262 | "TARGET_Z10" | |
8c21b0d1 | 4263 | "r<noxa>sbg\t%0,%1,%s2,%e2,%b3" |
571e408a RH |
4264 | [(set_attr "op_type" "RIE")]) |
4265 | ||
50dc4eed | 4266 | ; rosbg, rxsbg |
f3d90045 | 4267 | (define_insn "*r<noxa>sbg_<mode>_srl_bitmask" |
571e408a RH |
4268 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4269 | (IXOR:GPR | |
4270 | (and:GPR | |
4271 | (lshiftrt:GPR | |
4272 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4273 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4274 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4275 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4276 | (clobber (reg:CC CC_REGNUM))] | |
4277 | "TARGET_Z10 | |
4278 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
4279 | INTVAL (operands[2]))" | |
b9789752 IL |
4280 | { |
4281 | static char buffer[256]; | |
4282 | sprintf (buffer, "r<noxa>sbg\t%%0,%%1,%%<bfstart>2,%%<bfend>2,%ld", | |
4283 | 64 - INTVAL (operands[3])); | |
4284 | return buffer; | |
4285 | } | |
571e408a RH |
4286 | [(set_attr "op_type" "RIE")]) |
4287 | ||
50dc4eed | 4288 | ; rosbg, rxsbg |
f3d90045 | 4289 | (define_insn "*r<noxa>sbg_<mode>_sll_bitmask" |
571e408a RH |
4290 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4291 | (IXOR:GPR | |
4292 | (and:GPR | |
4293 | (ashift:GPR | |
4294 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4295 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4296 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4297 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4298 | (clobber (reg:CC CC_REGNUM))] | |
4299 | "TARGET_Z10 | |
4300 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
4301 | INTVAL (operands[2]))" | |
4302 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
4303 | [(set_attr "op_type" "RIE")]) |
4304 | ||
f3d90045 DV |
4305 | ;; unsigned {int,long} a, b |
4306 | ;; a = a | (b << const_int) | |
4307 | ;; a = a ^ (b << const_int) | |
50dc4eed | 4308 | ; rosbg, rxsbg |
f3d90045 DV |
4309 | (define_insn "*r<noxa>sbg_<mode>_sll" |
4310 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4311 | (IXOR:GPR | |
4312 | (ashift:GPR | |
4313 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4314 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4315 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4316 | (clobber (reg:CC CC_REGNUM))] | |
4317 | "TARGET_Z10" | |
b9789752 IL |
4318 | { |
4319 | static char buffer[256]; | |
4320 | sprintf (buffer, "r<noxa>sbg\t%%0,%%1,<bitoff>,%ld,%%2", | |
4321 | 63 - INTVAL (operands[2])); | |
4322 | return buffer; | |
4323 | } | |
f3d90045 DV |
4324 | [(set_attr "op_type" "RIE")]) |
4325 | ||
4326 | ;; unsigned {int,long} a, b | |
4327 | ;; a = a | (b >> const_int) | |
4328 | ;; a = a ^ (b >> const_int) | |
50dc4eed | 4329 | ; rosbg, rxsbg |
f3d90045 DV |
4330 | (define_insn "*r<noxa>sbg_<mode>_srl" |
4331 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4332 | (IXOR:GPR | |
4333 | (lshiftrt:GPR | |
4334 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4335 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4336 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4337 | (clobber (reg:CC CC_REGNUM))] | |
4338 | "TARGET_Z10" | |
b9789752 IL |
4339 | { |
4340 | static char buffer[256]; | |
4341 | sprintf (buffer, "r<noxa>sbg\t%%0,%%1,%ld,63,%ld", | |
4342 | <bitoff_plus> INTVAL (operands[2]), 64 - INTVAL (operands[2])); | |
4343 | return buffer; | |
4344 | } | |
4345 | [(set_attr "op_type" "RIE")]) | |
4346 | ||
4347 | ; rosbg, rxsbg | |
4348 | (define_insn "*r<noxa>sbg_sidi_srl" | |
4349 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") | |
4350 | (IXOR:SI | |
4351 | (subreg:SI | |
4352 | (zero_extract:DI | |
4353 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4354 | (const_int 32) | |
4355 | (match_operand:DI 2 "immediate_operand" "")) | |
4356 | 4) | |
4357 | (match_operand:SI 3 "nonimmediate_operand" "0"))) | |
4358 | (clobber (reg:CC CC_REGNUM))] | |
4359 | "TARGET_Z10" | |
4360 | { | |
4361 | static char buffer[256]; | |
4362 | sprintf (buffer, "r<noxa>sbg\t%%0,%%1,%ld,63,%ld", | |
4363 | 64 - INTVAL (operands[2]), 32 + INTVAL (operands[2])); | |
4364 | return buffer; | |
4365 | } | |
f3d90045 DV |
4366 | [(set_attr "op_type" "RIE")]) |
4367 | ||
5bb33936 RH |
4368 | ;; These two are generated by combine for s.bf &= val. |
4369 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
4370 | ;; shifts and ands, which results in some truly awful patterns | |
4371 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
4372 | ;; Instead of | |
4373 | ;; | |
4374 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4375 | ;; (const_int 24 [0x18]) | |
4376 | ;; (const_int 0 [0])) | |
4377 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4378 | ;; (const_int 40 [0x28])) 4) | |
4379 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
4380 | ;; | |
4381 | ;; we should instead generate | |
4382 | ;; | |
4383 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4384 | ;; (const_int 24 [0x18]) | |
4385 | ;; (const_int 0 [0])) | |
4386 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4387 | ;; (const_int 40 [0x28])) | |
4388 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
4389 | ;; | |
4390 | ;; by noticing that we can push down the outer paradoxical subreg | |
4391 | ;; into the operation. | |
4392 | ||
4393 | (define_insn "*insv_rnsbg_noshift" | |
4394 | [(set (zero_extract:DI | |
4395 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4396 | (match_operand 1 "const_int_operand" "") | |
4397 | (match_operand 2 "const_int_operand" "")) | |
4398 | (and:DI | |
4399 | (match_dup 0) | |
4400 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
4401 | (clobber (reg:CC CC_REGNUM))] | |
4402 | "TARGET_Z10 | |
0f6f72e8 | 4403 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4404 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" |
4405 | "rnsbg\t%0,%3,%2,63,0" | |
4406 | [(set_attr "op_type" "RIE")]) | |
4407 | ||
4408 | (define_insn "*insv_rnsbg_srl" | |
4409 | [(set (zero_extract:DI | |
4410 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4411 | (match_operand 1 "const_int_operand" "") | |
4412 | (match_operand 2 "const_int_operand" "")) | |
4413 | (and:DI | |
4414 | (lshiftrt:DI | |
4415 | (match_dup 0) | |
4416 | (match_operand 3 "const_int_operand" "")) | |
4417 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
4418 | (clobber (reg:CC CC_REGNUM))] | |
4419 | "TARGET_Z10 | |
0f6f72e8 | 4420 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4421 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" |
4422 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
4423 | [(set_attr "op_type" "RIE")]) | |
4424 | ||
6fa05db6 | 4425 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 4426 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
4427 | (match_operand 1 "const_int_operand" "n,n") |
4428 | (const_int 0)) | |
9602b6a1 | 4429 | (match_operand:W 2 "register_operand" "d,d"))] |
0f6f72e8 DV |
4430 | "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
4431 | && INTVAL (operands[1]) > 0 | |
6fa05db6 AS |
4432 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) |
4433 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4434 | { | |
4435 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4436 | ||
4437 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 4438 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
4439 | : "stcmy\t%2,%1,%S0"; |
4440 | } | |
9381e3f1 | 4441 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 4442 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4443 | (set_attr "z10prop" "z10_super,z10_super")]) |
6fa05db6 AS |
4444 | |
4445 | (define_insn "*insvdi_mem_reghigh" | |
3e4be43f | 4446 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S") |
6fa05db6 AS |
4447 | (match_operand 1 "const_int_operand" "n") |
4448 | (const_int 0)) | |
4449 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
4450 | (const_int 32)))] | |
9602b6a1 | 4451 | "TARGET_ZARCH |
0f6f72e8 | 4452 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
6fa05db6 AS |
4453 | && INTVAL (operands[1]) > 0 |
4454 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4455 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4456 | { | |
4457 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4458 | ||
4459 | operands[1] = GEN_INT ((1ul << size) - 1); | |
4460 | return "stcmh\t%2,%1,%S0"; | |
4461 | } | |
9381e3f1 WG |
4462 | [(set_attr "op_type" "RSY") |
4463 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 4464 | |
9602b6a1 AK |
4465 | (define_insn "*insvdi_reg_imm" |
4466 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4467 | (const_int 16) | |
4468 | (match_operand 1 "const_int_operand" "n")) | |
4469 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 | 4470 | "TARGET_ZARCH |
0f6f72e8 | 4471 | && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64) |
6fa05db6 AS |
4472 | && INTVAL (operands[1]) >= 0 |
4473 | && INTVAL (operands[1]) < BITS_PER_WORD | |
4474 | && INTVAL (operands[1]) % 16 == 0" | |
4475 | { | |
4476 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
4477 | { | |
4478 | case 64: return "iihh\t%0,%x2"; break; | |
4479 | case 48: return "iihl\t%0,%x2"; break; | |
4480 | case 32: return "iilh\t%0,%x2"; break; | |
4481 | case 16: return "iill\t%0,%x2"; break; | |
4482 | default: gcc_unreachable(); | |
4483 | } | |
4484 | } | |
9381e3f1 WG |
4485 | [(set_attr "op_type" "RI") |
4486 | (set_attr "z10prop" "z10_super_E1")]) | |
4487 | ||
9fec758d WG |
4488 | ; Update the left-most 32 bit of a DI. |
4489 | (define_insn "*insv_h_di_reg_extimm" | |
4490 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4491 | (const_int 32) | |
4492 | (const_int 0)) | |
4493 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4494 | "TARGET_EXTIMM" | |
4495 | "iihf\t%0,%o1" | |
4496 | [(set_attr "op_type" "RIL") | |
4497 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 4498 | |
d378b983 RH |
4499 | ; Update the right-most 32 bit of a DI. |
4500 | (define_insn "*insv_l_di_reg_extimm" | |
4501 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4502 | (const_int 32) | |
4503 | (const_int 32)) | |
4504 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4505 | "TARGET_EXTIMM" | |
4506 | "iilf\t%0,%o1" | |
9381e3f1 | 4507 | [(set_attr "op_type" "RIL") |
9fec758d | 4508 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 4509 | |
9db1d521 HP |
4510 | ; |
4511 | ; extendsidi2 instruction pattern(s). | |
4512 | ; | |
4513 | ||
4023fb28 UW |
4514 | (define_expand "extendsidi2" |
4515 | [(set (match_operand:DI 0 "register_operand" "") | |
4516 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4517 | "" | |
4023fb28 | 4518 | { |
9602b6a1 | 4519 | if (!TARGET_ZARCH) |
4023fb28 | 4520 | { |
c41c1387 | 4521 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4522 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
4523 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
4524 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
4525 | DONE; |
4526 | } | |
ec24698e | 4527 | }) |
4023fb28 UW |
4528 | |
4529 | (define_insn "*extendsidi2" | |
963fc8d0 | 4530 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4531 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4532 | "TARGET_ZARCH" |
9db1d521 | 4533 | "@ |
d40c829f | 4534 | lgfr\t%0,%1 |
963fc8d0 AK |
4535 | lgf\t%0,%1 |
4536 | lgfrl\t%0,%1" | |
4537 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4538 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4539 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4540 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1") |
4541 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 4542 | |
9db1d521 | 4543 | ; |
56477c21 | 4544 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4545 | ; |
4546 | ||
56477c21 AS |
4547 | (define_expand "extend<HQI:mode><DSI:mode>2" |
4548 | [(set (match_operand:DSI 0 "register_operand" "") | |
4549 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 4550 | "" |
4023fb28 | 4551 | { |
9602b6a1 | 4552 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
4553 | { |
4554 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 4555 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
4556 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
4557 | DONE; | |
4558 | } | |
ec24698e | 4559 | else if (!TARGET_EXTIMM) |
4023fb28 | 4560 | { |
2542ef05 | 4561 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
4562 | |
4563 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
4564 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
4565 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
4566 | DONE; |
4567 | } | |
ec24698e UW |
4568 | }) |
4569 | ||
56477c21 AS |
4570 | ; |
4571 | ; extendhidi2 instruction pattern(s). | |
4572 | ; | |
4573 | ||
ec24698e | 4574 | (define_insn "*extendhidi2_extimm" |
963fc8d0 | 4575 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4576 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))] |
9602b6a1 | 4577 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
4578 | "@ |
4579 | lghr\t%0,%1 | |
963fc8d0 AK |
4580 | lgh\t%0,%1 |
4581 | lghrl\t%0,%1" | |
4582 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4583 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4584 | (set_attr "cpu_facility" "extimm,extimm,z10") |
14cfceb7 IL |
4585 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1") |
4586 | (set_attr "relative_long" "*,*,yes")]) | |
4023fb28 UW |
4587 | |
4588 | (define_insn "*extendhidi2" | |
9db1d521 | 4589 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 4590 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))] |
9602b6a1 | 4591 | "TARGET_ZARCH" |
d40c829f | 4592 | "lgh\t%0,%1" |
9381e3f1 WG |
4593 | [(set_attr "op_type" "RXY") |
4594 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 4595 | |
9db1d521 | 4596 | ; |
56477c21 | 4597 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
4598 | ; |
4599 | ||
ec24698e | 4600 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
4601 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4602 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
4603 | "TARGET_EXTIMM" |
4604 | "@ | |
4605 | lhr\t%0,%1 | |
4606 | lh\t%0,%1 | |
963fc8d0 AK |
4607 | lhy\t%0,%1 |
4608 | lhrl\t%0,%1" | |
4609 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
4610 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 | 4611 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
14cfceb7 IL |
4612 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1") |
4613 | (set_attr "relative_long" "*,*,*,yes")]) | |
9db1d521 | 4614 | |
4023fb28 | 4615 | (define_insn "*extendhisi2" |
d3632d41 UW |
4616 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4617 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 4618 | "!TARGET_EXTIMM" |
d3632d41 | 4619 | "@ |
d40c829f UW |
4620 | lh\t%0,%1 |
4621 | lhy\t%0,%1" | |
9381e3f1 | 4622 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 4623 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4624 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 4625 | |
56477c21 AS |
4626 | ; |
4627 | ; extendqi(si|di)2 instruction pattern(s). | |
4628 | ; | |
4629 | ||
43a09b63 | 4630 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
4631 | (define_insn "*extendqi<mode>2_extimm" |
4632 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4633 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4634 | "TARGET_EXTIMM" |
4635 | "@ | |
56477c21 AS |
4636 | l<g>br\t%0,%1 |
4637 | l<g>b\t%0,%1" | |
9381e3f1 WG |
4638 | [(set_attr "op_type" "RRE,RXY") |
4639 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 4640 | |
43a09b63 | 4641 | ; lb, lgb |
56477c21 AS |
4642 | (define_insn "*extendqi<mode>2" |
4643 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4644 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))] |
56477c21 AS |
4645 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
4646 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
4647 | [(set_attr "op_type" "RXY") |
4648 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 4649 | |
56477c21 AS |
4650 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
4651 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4652 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 4653 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 4654 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
4655 | "#" |
4656 | "&& reload_completed" | |
4023fb28 | 4657 | [(parallel |
56477c21 | 4658 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 4659 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 4660 | (parallel |
56477c21 | 4661 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 4662 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
4663 | { |
4664 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4665 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 4666 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 4667 | }) |
9db1d521 | 4668 | |
9db1d521 HP |
4669 | ; |
4670 | ; zero_extendsidi2 instruction pattern(s). | |
4671 | ; | |
4672 | ||
4023fb28 UW |
4673 | (define_expand "zero_extendsidi2" |
4674 | [(set (match_operand:DI 0 "register_operand" "") | |
4675 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4676 | "" | |
4023fb28 | 4677 | { |
9602b6a1 | 4678 | if (!TARGET_ZARCH) |
4023fb28 | 4679 | { |
c41c1387 | 4680 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4681 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
4682 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
4683 | DONE; |
4684 | } | |
ec24698e | 4685 | }) |
4023fb28 UW |
4686 | |
4687 | (define_insn "*zero_extendsidi2" | |
963fc8d0 | 4688 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4689 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4690 | "TARGET_ZARCH" |
9db1d521 | 4691 | "@ |
d40c829f | 4692 | llgfr\t%0,%1 |
963fc8d0 AK |
4693 | llgf\t%0,%1 |
4694 | llgfrl\t%0,%1" | |
4695 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4696 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4697 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4698 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3") |
4699 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 4700 | |
288e517f AK |
4701 | ; |
4702 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
4703 | ; | |
4704 | ||
d6083c7d UW |
4705 | (define_insn "*llgt_sidi" |
4706 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4707 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4708 | (const_int 2147483647)))] |
9602b6a1 | 4709 | "TARGET_ZARCH" |
d6083c7d | 4710 | "llgt\t%0,%1" |
9381e3f1 WG |
4711 | [(set_attr "op_type" "RXE") |
4712 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
4713 | |
4714 | (define_insn_and_split "*llgt_sidi_split" | |
4715 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4716 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4717 | (const_int 2147483647))) |
ae156f85 | 4718 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4719 | "TARGET_ZARCH" |
d6083c7d UW |
4720 | "#" |
4721 | "&& reload_completed" | |
4722 | [(set (match_dup 0) | |
4723 | (and:DI (subreg:DI (match_dup 1) 0) | |
4724 | (const_int 2147483647)))] | |
4725 | "") | |
4726 | ||
288e517f AK |
4727 | (define_insn "*llgt_sisi" |
4728 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 4729 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T") |
288e517f | 4730 | (const_int 2147483647)))] |
c4d50129 | 4731 | "TARGET_ZARCH" |
288e517f AK |
4732 | "@ |
4733 | llgtr\t%0,%1 | |
4734 | llgt\t%0,%1" | |
9381e3f1 WG |
4735 | [(set_attr "op_type" "RRE,RXE") |
4736 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4737 | |
288e517f AK |
4738 | (define_insn "*llgt_didi" |
4739 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4740 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
4741 | (const_int 2147483647)))] | |
9602b6a1 | 4742 | "TARGET_ZARCH" |
288e517f AK |
4743 | "@ |
4744 | llgtr\t%0,%1 | |
4745 | llgt\t%0,%N1" | |
9381e3f1 WG |
4746 | [(set_attr "op_type" "RRE,RXE") |
4747 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4748 | |
f19a9af7 | 4749 | (define_split |
9602b6a1 AK |
4750 | [(set (match_operand:DSI 0 "register_operand" "") |
4751 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 4752 | (const_int 2147483647))) |
ae156f85 | 4753 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 4754 | "TARGET_ZARCH && reload_completed" |
288e517f | 4755 | [(set (match_dup 0) |
9602b6a1 | 4756 | (and:DSI (match_dup 1) |
f6ee577c | 4757 | (const_int 2147483647)))] |
288e517f AK |
4758 | "") |
4759 | ||
9db1d521 | 4760 | ; |
56477c21 | 4761 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4762 | ; |
4763 | ||
56477c21 AS |
4764 | (define_expand "zero_extend<mode>di2" |
4765 | [(set (match_operand:DI 0 "register_operand" "") | |
4766 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4767 | "" | |
4768 | { | |
9602b6a1 | 4769 | if (!TARGET_ZARCH) |
56477c21 AS |
4770 | { |
4771 | rtx tmp = gen_reg_rtx (SImode); | |
4772 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
4773 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4774 | DONE; | |
4775 | } | |
4776 | else if (!TARGET_EXTIMM) | |
4777 | { | |
2542ef05 | 4778 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
4779 | operands[1] = gen_lowpart (DImode, operands[1]); |
4780 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4781 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4782 | DONE; | |
4783 | } | |
4784 | }) | |
4785 | ||
f6ee577c | 4786 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4787 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4788 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4789 | "" |
4023fb28 | 4790 | { |
ec24698e UW |
4791 | if (!TARGET_EXTIMM) |
4792 | { | |
4793 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4794 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4795 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4796 | DONE; |
56477c21 | 4797 | } |
ec24698e UW |
4798 | }) |
4799 | ||
963fc8d0 AK |
4800 | ; llhrl, llghrl |
4801 | (define_insn "*zero_extendhi<mode>2_z10" | |
4802 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3e4be43f | 4803 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))] |
963fc8d0 AK |
4804 | "TARGET_Z10" |
4805 | "@ | |
4806 | ll<g>hr\t%0,%1 | |
4807 | ll<g>h\t%0,%1 | |
4808 | ll<g>hrl\t%0,%1" | |
4809 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4810 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4811 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4812 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3") |
4813 | (set_attr "relative_long" "*,*,yes")]) | |
963fc8d0 | 4814 | |
43a09b63 | 4815 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4816 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4817 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4818 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4819 | "TARGET_EXTIMM" |
4820 | "@ | |
56477c21 AS |
4821 | ll<g><hc>r\t%0,%1 |
4822 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4823 | [(set_attr "op_type" "RRE,RXY") |
4824 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4825 | |
43a09b63 | 4826 | ; llgh, llgc |
56477c21 AS |
4827 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4828 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4829 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))] |
ec24698e | 4830 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4831 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4832 | [(set_attr "op_type" "RXY") |
4833 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4834 | |
4835 | (define_insn_and_split "*zero_extendhisi2_31" | |
4836 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4837 | (zero_extend:SI (match_operand:HI 1 "s_operand" "S"))) |
ae156f85 | 4838 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4839 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4840 | "#" |
4841 | "&& reload_completed" | |
4842 | [(set (match_dup 0) (const_int 0)) | |
4843 | (parallel | |
4844 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4845 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4846 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4847 | |
cc7ab9b7 UW |
4848 | (define_insn_and_split "*zero_extendqisi2_31" |
4849 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4850 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4851 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4852 | "#" |
4853 | "&& reload_completed" | |
4854 | [(set (match_dup 0) (const_int 0)) | |
4855 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4856 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4857 | |
9db1d521 HP |
4858 | ; |
4859 | ; zero_extendqihi2 instruction pattern(s). | |
4860 | ; | |
4861 | ||
9db1d521 HP |
4862 | (define_expand "zero_extendqihi2" |
4863 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4864 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4865 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4866 | { |
4023fb28 UW |
4867 | operands[1] = gen_lowpart (HImode, operands[1]); |
4868 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4869 | DONE; | |
ec24698e | 4870 | }) |
9db1d521 | 4871 | |
4023fb28 | 4872 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4873 | [(set (match_operand:HI 0 "register_operand" "=d") |
3e4be43f | 4874 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
ec24698e | 4875 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4876 | "llgc\t%0,%1" |
9381e3f1 WG |
4877 | [(set_attr "op_type" "RXY") |
4878 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4879 | |
cc7ab9b7 UW |
4880 | (define_insn_and_split "*zero_extendqihi2_31" |
4881 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
3e4be43f | 4882 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4883 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4884 | "#" |
4885 | "&& reload_completed" | |
4886 | [(set (match_dup 0) (const_int 0)) | |
4887 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4888 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4889 | |
609e7e80 | 4890 | ; |
9751ad6e | 4891 | ; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander |
609e7e80 AK |
4892 | ; |
4893 | ||
9751ad6e AK |
4894 | ; This is the only entry point for fixuns_trunc. It multiplexes the |
4895 | ; expansion to either the *_emu expanders below for pre z196 machines | |
4896 | ; or emits the default pattern otherwise. | |
4897 | (define_expand "fixuns_trunc<FP:mode><GPR:mode>2" | |
609e7e80 | 4898 | [(parallel |
9751ad6e AK |
4899 | [(set (match_operand:GPR 0 "register_operand" "") |
4900 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" ""))) | |
4901 | (unspec:GPR [(match_dup 2)] UNSPEC_ROUND) | |
65b1d8ea | 4902 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e | 4903 | "TARGET_HARD_FLOAT" |
609e7e80 | 4904 | { |
65b1d8ea AK |
4905 | if (!TARGET_Z196) |
4906 | { | |
9751ad6e AK |
4907 | /* We don't provide emulation for TD|DD->SI. */ |
4908 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT | |
4909 | && <GPR:MODE>mode == SImode) | |
4910 | FAIL; | |
4911 | emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0], | |
4912 | operands[1])); | |
65b1d8ea AK |
4913 | DONE; |
4914 | } | |
9751ad6e AK |
4915 | |
4916 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT) | |
4917 | operands[2] = GEN_INT (DFP_RND_TOWARD_0); | |
4918 | else | |
4919 | operands[2] = GEN_INT (BFP_RND_TOWARD_0); | |
609e7e80 AK |
4920 | }) |
4921 | ||
9751ad6e AK |
4922 | ; (sf|df|tf)->unsigned (si|di) |
4923 | ||
4924 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4925 | ; machines. | |
4926 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu" | |
4927 | [(parallel | |
4928 | [(set (match_operand:GPR 0 "register_operand" "") | |
4929 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4930 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
4931 | (clobber (reg:CC CC_REGNUM))])] | |
4932 | "!TARGET_Z196 && TARGET_HARD_FLOAT" | |
4933 | { | |
4934 | rtx_code_label *label1 = gen_label_rtx (); | |
4935 | rtx_code_label *label2 = gen_label_rtx (); | |
4936 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
4937 | REAL_VALUE_TYPE cmp, sub; | |
4938 | ||
4939 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
4940 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); | |
4941 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
4942 | ||
4943 | emit_cmp_and_jump_insns (operands[1], | |
4944 | const_double_from_real_value (cmp, <BFP:MODE>mode), | |
4945 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4946 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
4947 | const_double_from_real_value (sub, <BFP:MODE>mode))); | |
4948 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
4949 | GEN_INT (BFP_RND_TOWARD_MINF))); | |
4950 | emit_jump (label2); | |
4951 | ||
4952 | emit_label (label1); | |
4953 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4954 | operands[1], | |
4955 | GEN_INT (BFP_RND_TOWARD_0))); | |
4956 | emit_label (label2); | |
4957 | DONE; | |
4958 | }) | |
4959 | ||
4960 | ; dd->unsigned di | |
4961 | ||
4962 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4963 | ; machines. | |
4964 | (define_expand "fixuns_truncdddi2_emu" | |
65b1d8ea AK |
4965 | [(parallel |
4966 | [(set (match_operand:DI 0 "register_operand" "") | |
9751ad6e | 4967 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) |
ae8e301e | 4968 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea AK |
4969 | (clobber (reg:CC CC_REGNUM))])] |
4970 | ||
9751ad6e | 4971 | "!TARGET_Z196 && TARGET_HARD_DFP" |
609e7e80 | 4972 | { |
9751ad6e AK |
4973 | rtx_code_label *label1 = gen_label_rtx (); |
4974 | rtx_code_label *label2 = gen_label_rtx (); | |
4975 | rtx temp = gen_reg_rtx (TDmode); | |
4976 | REAL_VALUE_TYPE cmp, sub; | |
4977 | ||
4978 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4979 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4980 | ||
4981 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4982 | solution is doing the check and the subtraction in TD mode and using a | |
4983 | TD -> DI convert afterwards. */ | |
4984 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
4985 | temp = force_reg (TDmode, temp); | |
4986 | emit_cmp_and_jump_insns (temp, | |
4987 | const_double_from_real_value (cmp, TDmode), | |
4988 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4989 | emit_insn (gen_subtd3 (temp, temp, | |
4990 | const_double_from_real_value (sub, TDmode))); | |
4991 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
4992 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
4993 | emit_jump (label2); | |
4994 | ||
4995 | emit_label (label1); | |
4996 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], | |
4997 | GEN_INT (DFP_RND_TOWARD_0))); | |
4998 | emit_label (label2); | |
4999 | DONE; | |
609e7e80 | 5000 | }) |
cc7ab9b7 | 5001 | |
9751ad6e | 5002 | ; td->unsigned di |
9db1d521 | 5003 | |
9751ad6e AK |
5004 | ; Emulate the unsigned conversion with the signed version for pre z196 |
5005 | ; machines. | |
5006 | (define_expand "fixuns_trunctddi2_emu" | |
65b1d8ea | 5007 | [(parallel |
9751ad6e AK |
5008 | [(set (match_operand:DI 0 "register_operand" "") |
5009 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
5010 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
65b1d8ea | 5011 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
5012 | |
5013 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
9db1d521 | 5014 | { |
9751ad6e AK |
5015 | rtx_code_label *label1 = gen_label_rtx (); |
5016 | rtx_code_label *label2 = gen_label_rtx (); | |
5017 | rtx temp = gen_reg_rtx (TDmode); | |
5018 | REAL_VALUE_TYPE cmp, sub; | |
5019 | ||
5020 | operands[1] = force_reg (TDmode, operands[1]); | |
5021 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
5022 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
5023 | ||
5024 | emit_cmp_and_jump_insns (operands[1], | |
5025 | const_double_from_real_value (cmp, TDmode), | |
5026 | LT, NULL_RTX, VOIDmode, 0, label1); | |
5027 | emit_insn (gen_subtd3 (temp, operands[1], | |
5028 | const_double_from_real_value (sub, TDmode))); | |
5029 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
5030 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
5031 | emit_jump (label2); | |
5032 | ||
5033 | emit_label (label1); | |
5034 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], | |
5035 | GEN_INT (DFP_RND_TOWARD_0))); | |
5036 | emit_label (label2); | |
5037 | DONE; | |
10bbf137 | 5038 | }) |
9db1d521 | 5039 | |
9751ad6e AK |
5040 | ; Just a dummy to make the code in the first expander a bit easier. |
5041 | (define_expand "fixuns_trunc<mode>si2_emu" | |
65b1d8ea AK |
5042 | [(parallel |
5043 | [(set (match_operand:SI 0 "register_operand" "") | |
5044 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
9751ad6e | 5045 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 5046 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
5047 | |
5048 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
5049 | { | |
5050 | FAIL; | |
5051 | }) | |
5052 | ||
65b1d8ea AK |
5053 | |
5054 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
5055 | ||
9751ad6e AK |
5056 | ; df -> unsigned di |
5057 | (define_insn "*fixuns_truncdfdi2_vx" | |
6e5b5de8 AK |
5058 | [(set (match_operand:DI 0 "register_operand" "=d,v") |
5059 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
5060 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
5061 | (clobber (reg:CC CC_REGNUM))] | |
9751ad6e AK |
5062 | "TARGET_VX && TARGET_HARD_FLOAT" |
5063 | "@ | |
5064 | clgdbr\t%0,%h2,%1,0 | |
5065 | wclgdb\t%v0,%v1,0,%h2" | |
5066 | [(set_attr "op_type" "RRF,VRR") | |
5067 | (set_attr "type" "ftoi")]) | |
6e5b5de8 | 5068 | |
9751ad6e | 5069 | ; (dd|td|sf|df|tf)->unsigned (di|si) |
65b1d8ea AK |
5070 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr |
5071 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
5072 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
6e5b5de8 AK |
5073 | [(set (match_operand:GPR 0 "register_operand" "=d") |
5074 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
5075 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
65b1d8ea | 5076 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 | 5077 | "TARGET_Z196 && TARGET_HARD_FLOAT |
a579871b | 5078 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" |
65b1d8ea AK |
5079 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" |
5080 | [(set_attr "op_type" "RRF") | |
5081 | (set_attr "type" "ftoi")]) | |
5082 | ||
b60cb710 AK |
5083 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
5084 | [(set (match_operand:GPR 0 "register_operand" "") | |
5085 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
5086 | "TARGET_HARD_FLOAT" | |
9db1d521 | 5087 | { |
b60cb710 | 5088 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
ae8e301e | 5089 | GEN_INT (BFP_RND_TOWARD_0))); |
9db1d521 | 5090 | DONE; |
10bbf137 | 5091 | }) |
9db1d521 | 5092 | |
6e5b5de8 AK |
5093 | (define_insn "*fix_truncdfdi2_bfp_z13" |
5094 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
5095 | (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
5096 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
5097 | (clobber (reg:CC CC_REGNUM))] | |
a579871b | 5098 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5099 | "@ |
5100 | cgdbr\t%0,%h2,%1 | |
5101 | wcgdb\t%v0,%v1,0,%h2" | |
5102 | [(set_attr "op_type" "RRE,VRR") | |
5103 | (set_attr "type" "ftoi")]) | |
5104 | ||
43a09b63 | 5105 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
6e5b5de8 AK |
5106 | (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5107 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5108 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5109 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 5110 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
5111 | "TARGET_HARD_FLOAT |
5112 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" | |
7b6baae1 | 5113 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 5114 | [(set_attr "op_type" "RRE") |
077dab3b | 5115 | (set_attr "type" "ftoi")]) |
9db1d521 | 5116 | |
6e5b5de8 AK |
5117 | (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5118 | [(parallel | |
5119 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5120 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5121 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5122 | (clobber (reg:CC CC_REGNUM))])] | |
5123 | "TARGET_HARD_FLOAT") | |
609e7e80 AK |
5124 | ; |
5125 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
5126 | ; | |
5127 | ||
99cd7dd0 AK |
5128 | (define_expand "fix_trunc<mode>di2" |
5129 | [(set (match_operand:DI 0 "register_operand" "") | |
5130 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 5131 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
5132 | { |
5133 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
5134 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
ae8e301e | 5135 | GEN_INT (DFP_RND_TOWARD_0))); |
99cd7dd0 AK |
5136 | DONE; |
5137 | }) | |
5138 | ||
609e7e80 | 5139 | ; cgxtr, cgdtr |
99cd7dd0 | 5140 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
5141 | [(set (match_operand:DI 0 "register_operand" "=d") |
5142 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
5143 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5144 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 5145 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
5146 | "cg<DFP:xde>tr\t%0,%h2,%1" |
5147 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5148 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
5149 | |
5150 | ||
f61a2c7d AK |
5151 | ; |
5152 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
5153 | ; | |
5154 | ||
5155 | (define_expand "fix_trunctf<mode>2" | |
5156 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
5157 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
ae8e301e | 5158 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) |
f61a2c7d | 5159 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5160 | "TARGET_HARD_FLOAT" |
142cd70f | 5161 | "") |
9db1d521 | 5162 | |
9db1d521 | 5163 | |
9db1d521 | 5164 | ; |
142cd70f | 5165 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
5166 | ; |
5167 | ||
609e7e80 | 5168 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 5169 | (define_insn "floatdi<mode>2" |
62d3f261 AK |
5170 | [(set (match_operand:FP 0 "register_operand" "=f,v") |
5171 | (float:FP (match_operand:DI 1 "register_operand" "d,v")))] | |
9602b6a1 | 5172 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5173 | "@ |
5174 | c<xde>g<bt>r\t%0,%1 | |
5175 | wcdgb\t%v0,%v1,0,0" | |
5176 | [(set_attr "op_type" "RRE,VRR") | |
5177 | (set_attr "type" "itof<mode>" ) | |
285363a1 | 5178 | (set_attr "cpu_facility" "*,vx") |
62d3f261 | 5179 | (set_attr "enabled" "*,<DFDI>")]) |
9db1d521 | 5180 | |
43a09b63 | 5181 | ; cxfbr, cdfbr, cefbr |
142cd70f | 5182 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
5183 | [(set (match_operand:BFP 0 "register_operand" "=f") |
5184 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 5185 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
5186 | "c<xde>fbr\t%0,%1" |
5187 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 5188 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 5189 | |
65b1d8ea AK |
5190 | ; cxftr, cdftr |
5191 | (define_insn "floatsi<mode>2" | |
5192 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5193 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
5194 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
5195 | "c<xde>ftr\t%0,0,%1,0" | |
5196 | [(set_attr "op_type" "RRE") | |
5197 | (set_attr "type" "itof<mode>" )]) | |
5198 | ||
5199 | ; | |
5200 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
5201 | ; | |
5202 | ||
6e5b5de8 AK |
5203 | (define_insn "*floatunsdidf2_z13" |
5204 | [(set (match_operand:DF 0 "register_operand" "=f,v") | |
5205 | (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] | |
a579871b | 5206 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5207 | "@ |
5208 | cdlgbr\t%0,0,%1,0 | |
5209 | wcdlgb\t%v0,%v1,0,0" | |
5210 | [(set_attr "op_type" "RRE,VRR") | |
5211 | (set_attr "type" "itofdf")]) | |
5212 | ||
65b1d8ea AK |
5213 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr |
5214 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
6e5b5de8 AK |
5215 | (define_insn "*floatuns<GPR:mode><FP:mode>2" |
5216 | [(set (match_operand:FP 0 "register_operand" "=f") | |
5217 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
5218 | "TARGET_Z196 && TARGET_HARD_FLOAT | |
5219 | && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" | |
65b1d8ea AK |
5220 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" |
5221 | [(set_attr "op_type" "RRE") | |
6e5b5de8 AK |
5222 | (set_attr "type" "itof<FP:mode>")]) |
5223 | ||
5224 | (define_expand "floatuns<GPR:mode><FP:mode>2" | |
5225 | [(set (match_operand:FP 0 "register_operand" "") | |
5226 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] | |
5227 | "TARGET_Z196 && TARGET_HARD_FLOAT") | |
f61a2c7d | 5228 | |
9db1d521 HP |
5229 | ; |
5230 | ; truncdfsf2 instruction pattern(s). | |
5231 | ; | |
5232 | ||
142cd70f | 5233 | (define_insn "truncdfsf2" |
6e5b5de8 AK |
5234 | [(set (match_operand:SF 0 "register_operand" "=f,v") |
5235 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] | |
142cd70f | 5236 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5237 | "@ |
5238 | ledbr\t%0,%1 | |
5239 | wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed | |
5240 | ; According to BFP rounding mode | |
5241 | [(set_attr "op_type" "RRE,VRR") | |
5242 | (set_attr "type" "ftruncdf") | |
285363a1 | 5243 | (set_attr "cpu_facility" "*,vx")]) |
9db1d521 | 5244 | |
f61a2c7d | 5245 | ; |
142cd70f | 5246 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
5247 | ; |
5248 | ||
142cd70f AK |
5249 | ; ldxbr, lexbr |
5250 | (define_insn "trunctf<mode>2" | |
5251 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
5252 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 5253 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
5254 | "TARGET_HARD_FLOAT" |
5255 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 5256 | [(set_attr "length" "6") |
9381e3f1 | 5257 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 5258 | |
609e7e80 AK |
5259 | ; |
5260 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
5261 | ; | |
5262 | ||
432d4670 AK |
5263 | |
5264 | (define_expand "trunctddd2" | |
5265 | [(parallel | |
5266 | [(set (match_operand:DD 0 "register_operand" "") | |
5267 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
5268 | (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND) | |
5269 | (clobber (scratch:TD))])] | |
5270 | "TARGET_HARD_DFP") | |
5271 | ||
5272 | (define_insn "*trunctddd2" | |
609e7e80 | 5273 | [(set (match_operand:DD 0 "register_operand" "=f") |
bf259a77 | 5274 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
432d4670 AK |
5275 | (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND) |
5276 | (clobber (match_scratch:TD 3 "=f"))] | |
fb068247 | 5277 | "TARGET_HARD_DFP" |
432d4670 | 5278 | "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3" |
bf259a77 | 5279 | [(set_attr "length" "6") |
9381e3f1 | 5280 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
5281 | |
5282 | (define_insn "truncddsd2" | |
5283 | [(set (match_operand:SD 0 "register_operand" "=f") | |
5284 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5285 | "TARGET_HARD_DFP" |
609e7e80 AK |
5286 | "ledtr\t%0,0,%1,0" |
5287 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5288 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 5289 | |
feade5a8 AK |
5290 | (define_expand "trunctdsd2" |
5291 | [(parallel | |
d5a216fa | 5292 | [(set (match_dup 2) |
feade5a8 | 5293 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) |
432d4670 | 5294 | (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND) |
d5a216fa | 5295 | (clobber (match_scratch:TD 3 ""))]) |
feade5a8 | 5296 | (set (match_operand:SD 0 "register_operand" "") |
d5a216fa | 5297 | (float_truncate:SD (match_dup 2)))] |
feade5a8 AK |
5298 | "TARGET_HARD_DFP" |
5299 | { | |
d5a216fa | 5300 | operands[2] = gen_reg_rtx (DDmode); |
feade5a8 AK |
5301 | }) |
5302 | ||
9db1d521 | 5303 | ; |
142cd70f | 5304 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
5305 | ; |
5306 | ||
2de2b3f9 | 5307 | ; wflls |
6e5b5de8 AK |
5308 | (define_insn "*extendsfdf2_z13" |
5309 | [(set (match_operand:DF 0 "register_operand" "=f,f,v") | |
5310 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] | |
a579871b | 5311 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5312 | "@ |
5313 | ldebr\t%0,%1 | |
5314 | ldeb\t%0,%1 | |
5315 | wldeb\t%v0,%v1" | |
5316 | [(set_attr "op_type" "RRE,RXE,VRR") | |
5317 | (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) | |
5318 | ||
142cd70f | 5319 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
6e5b5de8 AK |
5320 | (define_insn "*extend<DSF:mode><BFP:mode>2" |
5321 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
142cd70f AK |
5322 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] |
5323 | "TARGET_HARD_FLOAT | |
6e5b5de8 AK |
5324 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) |
5325 | && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" | |
f61a2c7d | 5326 | "@ |
142cd70f AK |
5327 | l<BFP:xde><DSF:xde>br\t%0,%1 |
5328 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
6e5b5de8 AK |
5329 | [(set_attr "op_type" "RRE,RXE") |
5330 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
5331 | ||
5332 | (define_expand "extend<DSF:mode><BFP:mode>2" | |
5333 | [(set (match_operand:BFP 0 "register_operand" "") | |
5334 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] | |
5335 | "TARGET_HARD_FLOAT | |
5336 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") | |
f61a2c7d | 5337 | |
609e7e80 AK |
5338 | ; |
5339 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
5340 | ; | |
5341 | ||
5342 | (define_insn "extendddtd2" | |
5343 | [(set (match_operand:TD 0 "register_operand" "=f") | |
5344 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5345 | "TARGET_HARD_DFP" |
609e7e80 AK |
5346 | "lxdtr\t%0,%1,0" |
5347 | [(set_attr "op_type" "RRF") | |
5348 | (set_attr "type" "fsimptf")]) | |
5349 | ||
5350 | (define_insn "extendsddd2" | |
5351 | [(set (match_operand:DD 0 "register_operand" "=f") | |
5352 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 5353 | "TARGET_HARD_DFP" |
609e7e80 AK |
5354 | "ldetr\t%0,%1,0" |
5355 | [(set_attr "op_type" "RRF") | |
5356 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 5357 | |
feade5a8 AK |
5358 | (define_expand "extendsdtd2" |
5359 | [(set (match_dup 2) | |
5360 | (float_extend:DD (match_operand:SD 1 "register_operand" ""))) | |
5361 | (set (match_operand:TD 0 "register_operand" "") | |
5362 | (float_extend:TD (match_dup 2)))] | |
5363 | "TARGET_HARD_DFP" | |
5364 | { | |
5365 | operands[2] = gen_reg_rtx (DDmode); | |
5366 | }) | |
5367 | ||
d12a76f3 AK |
5368 | ; Binary Floating Point - load fp integer |
5369 | ||
5370 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
5371 | ; For all of them the inexact exceptions are suppressed. | |
5372 | ||
5373 | ; fiebra, fidbra, fixbra | |
5374 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
5375 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5376 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5377 | FPINT))] | |
5378 | "TARGET_Z196" | |
5379 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5380 | [(set_attr "op_type" "RRF") | |
5381 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5382 | ||
5383 | ; rint is supposed to raise an inexact exception so we can use the | |
5384 | ; older instructions. | |
5385 | ||
5386 | ; fiebr, fidbr, fixbr | |
5387 | (define_insn "rint<BFP:mode>2" | |
5388 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5389 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5390 | UNSPEC_FPINT_RINT))] | |
5391 | "" | |
5392 | "fi<BFP:xde>br\t%0,0,%1" | |
5393 | [(set_attr "op_type" "RRF") | |
5394 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5395 | ||
5396 | ||
5397 | ; Decimal Floating Point - load fp integer | |
5398 | ||
5399 | ; fidtr, fixtr | |
5400 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
5401 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5402 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5403 | FPINT))] | |
5404 | "TARGET_HARD_DFP" | |
5405 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5406 | [(set_attr "op_type" "RRF") | |
5407 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5408 | ||
5409 | ; fidtr, fixtr | |
5410 | (define_insn "rint<DFP:mode>2" | |
5411 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5412 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5413 | UNSPEC_FPINT_RINT))] | |
5414 | "TARGET_HARD_DFP" | |
5415 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
5416 | [(set_attr "op_type" "RRF") | |
5417 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5418 | ||
5419 | ; | |
35dd9a0e AK |
5420 | ; Binary <-> Decimal floating point trunc patterns |
5421 | ; | |
5422 | ||
5423 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
5424 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5425 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5426 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5427 | (clobber (reg:CC CC_REGNUM)) |
5428 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5429 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5430 | "pfpo") |
5431 | ||
5432 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
5433 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 5434 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5435 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5436 | (clobber (reg:CC CC_REGNUM)) |
5437 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5438 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5439 | "pfpo") |
5440 | ||
5441 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5442 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5443 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5444 | (parallel | |
5445 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5446 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5447 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5448 | (clobber (reg:CC CC_REGNUM)) |
5449 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5450 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5451 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5452 | "TARGET_HARD_DFP |
35dd9a0e AK |
5453 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5454 | { | |
5455 | HOST_WIDE_INT flags; | |
5456 | ||
ced8d882 AK |
5457 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5458 | rounding mode of the target format needs to be used. */ | |
5459 | ||
35dd9a0e AK |
5460 | flags = (PFPO_CONVERT | |
5461 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5462 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT | |
5463 | PFPO_RND_MODE_DFP); | |
35dd9a0e AK |
5464 | |
5465 | operands[2] = GEN_INT (flags); | |
5466 | }) | |
5467 | ||
5468 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5469 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5470 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5471 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5472 | (parallel | |
2cf4c39e | 5473 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5474 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5475 | (clobber (reg:CC CC_REGNUM)) |
5476 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5477 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5478 | "TARGET_HARD_DFP |
35dd9a0e AK |
5479 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
5480 | { | |
5481 | HOST_WIDE_INT flags; | |
5482 | ||
ced8d882 AK |
5483 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5484 | rounding mode of the target format needs to be used. */ | |
5485 | ||
35dd9a0e AK |
5486 | flags = (PFPO_CONVERT | |
5487 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5488 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT | |
5489 | PFPO_RND_MODE_BFP); | |
35dd9a0e AK |
5490 | |
5491 | operands[2] = GEN_INT (flags); | |
5492 | }) | |
5493 | ||
5494 | ; | |
5495 | ; Binary <-> Decimal floating point extend patterns | |
5496 | ; | |
5497 | ||
5498 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5499 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5500 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5501 | (clobber (reg:CC CC_REGNUM)) |
5502 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5503 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5504 | "pfpo") |
5505 | ||
5506 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5507 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5508 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5509 | (clobber (reg:CC CC_REGNUM)) |
5510 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5511 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5512 | "pfpo") |
5513 | ||
5514 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5515 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5516 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5517 | (parallel | |
5518 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5519 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5520 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5521 | (clobber (reg:CC CC_REGNUM)) |
5522 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5523 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5524 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5525 | "TARGET_HARD_DFP |
35dd9a0e AK |
5526 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5527 | { | |
5528 | HOST_WIDE_INT flags; | |
5529 | ||
ced8d882 AK |
5530 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5531 | rounding mode of the target format needs to be used. */ | |
5532 | ||
35dd9a0e AK |
5533 | flags = (PFPO_CONVERT | |
5534 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5535 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT | |
5536 | PFPO_RND_MODE_DFP); | |
35dd9a0e AK |
5537 | |
5538 | operands[2] = GEN_INT (flags); | |
5539 | }) | |
5540 | ||
5541 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5542 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5543 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5544 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5545 | (parallel | |
2cf4c39e | 5546 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5547 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5548 | (clobber (reg:CC CC_REGNUM)) |
5549 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5550 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5551 | "TARGET_HARD_DFP |
35dd9a0e AK |
5552 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
5553 | { | |
5554 | HOST_WIDE_INT flags; | |
5555 | ||
ced8d882 AK |
5556 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5557 | rounding mode of the target format needs to be used. */ | |
5558 | ||
35dd9a0e AK |
5559 | flags = (PFPO_CONVERT | |
5560 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5561 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT | |
5562 | PFPO_RND_MODE_BFP); | |
35dd9a0e AK |
5563 | |
5564 | operands[2] = GEN_INT (flags); | |
5565 | }) | |
5566 | ||
5567 | ||
9db1d521 | 5568 | ;; |
fae778eb | 5569 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 5570 | ;; |
fae778eb | 5571 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
5572 | ; because of unpredictable Bits in Register for Halfword and Byte |
5573 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
5574 | ||
07893d4f UW |
5575 | ;; |
5576 | ;;- Add instructions. | |
5577 | ;; | |
5578 | ||
1c7b1b7e UW |
5579 | ; |
5580 | ; addti3 instruction pattern(s). | |
5581 | ; | |
5582 | ||
085261c8 AK |
5583 | (define_expand "addti3" |
5584 | [(parallel | |
5585 | [(set (match_operand:TI 0 "register_operand" "") | |
5586 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") | |
5587 | (match_operand:TI 2 "general_operand" "") ) ) | |
5588 | (clobber (reg:CC CC_REGNUM))])] | |
5589 | "TARGET_ZARCH" | |
5590 | { | |
5591 | /* For z13 we have vaq which doesn't set CC. */ | |
5592 | if (TARGET_VX) | |
5593 | { | |
5594 | emit_insn (gen_rtx_SET (operands[0], | |
5595 | gen_rtx_PLUS (TImode, | |
5596 | copy_to_mode_reg (TImode, operands[1]), | |
5597 | copy_to_mode_reg (TImode, operands[2])))); | |
5598 | DONE; | |
5599 | } | |
5600 | }) | |
5601 | ||
5602 | (define_insn_and_split "*addti3" | |
5603 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
1c7b1b7e | 5604 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
085261c8 | 5605 | (match_operand:TI 2 "general_operand" "do") ) ) |
ae156f85 | 5606 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5607 | "TARGET_ZARCH" |
1c7b1b7e UW |
5608 | "#" |
5609 | "&& reload_completed" | |
5610 | [(parallel | |
ae156f85 | 5611 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
5612 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
5613 | (match_dup 7))) | |
5614 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
5615 | (parallel | |
a94a76a7 UW |
5616 | [(set (match_dup 3) (plus:DI |
5617 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5618 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5619 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
5620 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5621 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5622 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5623 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5624 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5625 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5626 | [(set_attr "op_type" "*") | |
5627 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5628 | |
07893d4f UW |
5629 | ; |
5630 | ; adddi3 instruction pattern(s). | |
5631 | ; | |
5632 | ||
3298c037 AK |
5633 | (define_expand "adddi3" |
5634 | [(parallel | |
963fc8d0 | 5635 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
5636 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
5637 | (match_operand:DI 2 "general_operand" ""))) | |
5638 | (clobber (reg:CC CC_REGNUM))])] | |
5639 | "" | |
5640 | "") | |
5641 | ||
07893d4f UW |
5642 | (define_insn "*adddi3_sign" |
5643 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5644 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5645 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5646 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5647 | "TARGET_ZARCH" |
07893d4f | 5648 | "@ |
d40c829f UW |
5649 | agfr\t%0,%2 |
5650 | agf\t%0,%2" | |
65b1d8ea AK |
5651 | [(set_attr "op_type" "RRE,RXY") |
5652 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
5653 | |
5654 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 5655 | [(set (reg CC_REGNUM) |
3e4be43f | 5656 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5657 | (match_operand:DI 1 "register_operand" "0,0")) |
5658 | (const_int 0))) | |
5659 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5660 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 5661 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5662 | "@ |
d40c829f UW |
5663 | algfr\t%0,%2 |
5664 | algf\t%0,%2" | |
9381e3f1 WG |
5665 | [(set_attr "op_type" "RRE,RXY") |
5666 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5667 | |
5668 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 5669 | [(set (reg CC_REGNUM) |
3e4be43f | 5670 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5671 | (match_operand:DI 1 "register_operand" "0,0")) |
5672 | (const_int 0))) | |
5673 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5674 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5675 | "@ |
d40c829f UW |
5676 | algfr\t%0,%2 |
5677 | algf\t%0,%2" | |
9381e3f1 WG |
5678 | [(set_attr "op_type" "RRE,RXY") |
5679 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5680 | |
5681 | (define_insn "*adddi3_zero" | |
5682 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5683 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5684 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5685 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5686 | "TARGET_ZARCH" |
07893d4f | 5687 | "@ |
d40c829f UW |
5688 | algfr\t%0,%2 |
5689 | algf\t%0,%2" | |
9381e3f1 WG |
5690 | [(set_attr "op_type" "RRE,RXY") |
5691 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 5692 | |
e69166de | 5693 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 5694 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
5695 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5696 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5697 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 5698 | "!TARGET_ZARCH" |
e69166de UW |
5699 | "#" |
5700 | "&& reload_completed" | |
5701 | [(parallel | |
ae156f85 | 5702 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
5703 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5704 | (match_dup 7))) | |
5705 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5706 | (parallel | |
a94a76a7 UW |
5707 | [(set (match_dup 3) (plus:SI |
5708 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5709 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5710 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
5711 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5712 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5713 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5714 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5715 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5716 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5717 | |
3298c037 AK |
5718 | ; |
5719 | ; addsi3 instruction pattern(s). | |
5720 | ; | |
5721 | ||
5722 | (define_expand "addsi3" | |
07893d4f | 5723 | [(parallel |
963fc8d0 | 5724 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
5725 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
5726 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5727 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5728 | "" |
07893d4f | 5729 | "") |
9db1d521 | 5730 | |
3298c037 AK |
5731 | (define_insn "*addsi3_sign" |
5732 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5733 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5734 | (match_operand:SI 1 "register_operand" "0,0"))) | |
5735 | (clobber (reg:CC CC_REGNUM))] | |
5736 | "" | |
5737 | "@ | |
5738 | ah\t%0,%2 | |
5739 | ahy\t%0,%2" | |
65b1d8ea | 5740 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 5741 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 5742 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 5743 | |
9db1d521 | 5744 | ; |
3298c037 | 5745 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 5746 | ; |
9db1d521 | 5747 | |
65b1d8ea | 5748 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 5749 | (define_insn "*add<mode>3" |
3e4be43f UW |
5750 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") |
5751 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") | |
5752 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) | |
3298c037 AK |
5753 | (clobber (reg:CC CC_REGNUM))] |
5754 | "" | |
ec24698e | 5755 | "@ |
3298c037 | 5756 | a<g>r\t%0,%2 |
65b1d8ea | 5757 | a<g>rk\t%0,%1,%2 |
3298c037 | 5758 | a<g>hi\t%0,%h2 |
65b1d8ea | 5759 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
5760 | al<g>fi\t%0,%2 |
5761 | sl<g>fi\t%0,%n2 | |
5762 | a<g>\t%0,%2 | |
963fc8d0 AK |
5763 | a<y>\t%0,%2 |
5764 | a<g>si\t%0,%c2" | |
65b1d8ea | 5765 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
3e4be43f | 5766 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10") |
65b1d8ea AK |
5767 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, |
5768 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 5769 | |
65b1d8ea | 5770 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 5771 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 5772 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5773 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5774 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5775 | (match_dup 1))) |
65b1d8ea | 5776 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 5777 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5778 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5779 | "@ |
3298c037 | 5780 | al<g>r\t%0,%2 |
65b1d8ea | 5781 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5782 | al<g>fi\t%0,%2 |
5783 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5784 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5785 | al<g>\t%0,%2 |
963fc8d0 AK |
5786 | al<y>\t%0,%2 |
5787 | al<g>si\t%0,%c2" | |
65b1d8ea | 5788 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5789 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5790 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5791 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5792 | |
65b1d8ea | 5793 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5794 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 5795 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5796 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5797 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5798 | (match_dup 1))) |
65b1d8ea | 5799 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5800 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5801 | "@ |
3298c037 | 5802 | al<g>r\t%0,%2 |
65b1d8ea | 5803 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5804 | al<g>\t%0,%2 |
5805 | al<y>\t%0,%2" | |
65b1d8ea | 5806 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5807 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5808 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5809 | |
65b1d8ea | 5810 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5811 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 5812 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5813 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5814 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5815 | (match_dup 2))) |
3e4be43f | 5816 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5817 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5818 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5819 | "@ |
3298c037 | 5820 | al<g>r\t%0,%2 |
65b1d8ea | 5821 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5822 | al<g>fi\t%0,%2 |
5823 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5824 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5825 | al<g>\t%0,%2 |
963fc8d0 AK |
5826 | al<y>\t%0,%2 |
5827 | al<g>si\t%0,%c2" | |
65b1d8ea | 5828 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5829 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5830 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5831 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5832 | |
65b1d8ea | 5833 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5834 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 5835 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5836 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5837 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5838 | (match_dup 2))) |
65b1d8ea | 5839 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5840 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5841 | "@ |
3298c037 | 5842 | al<g>r\t%0,%2 |
65b1d8ea | 5843 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5844 | al<g>\t%0,%2 |
5845 | al<y>\t%0,%2" | |
65b1d8ea | 5846 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5847 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5848 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5849 | |
65b1d8ea | 5850 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5851 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5852 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5853 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5854 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
9db1d521 | 5855 | (const_int 0))) |
3e4be43f | 5856 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5857 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5858 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5859 | "@ |
3298c037 | 5860 | al<g>r\t%0,%2 |
65b1d8ea | 5861 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5862 | al<g>fi\t%0,%2 |
5863 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5864 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5865 | al<g>\t%0,%2 |
963fc8d0 AK |
5866 | al<y>\t%0,%2 |
5867 | al<g>si\t%0,%c2" | |
65b1d8ea | 5868 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5869 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5870 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, |
5871 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5872 | |
65b1d8ea | 5873 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5874 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5875 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5876 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5877 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5878 | (const_int 0))) |
65b1d8ea | 5879 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5880 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5881 | "@ |
3298c037 | 5882 | al<g>r\t%0,%2 |
65b1d8ea | 5883 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5884 | al<g>\t%0,%2 |
5885 | al<y>\t%0,%2" | |
65b1d8ea | 5886 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5887 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5888 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 5889 | |
65b1d8ea | 5890 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5891 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 5892 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5893 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5894 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
5895 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 5896 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 5897 | "@ |
3298c037 | 5898 | al<g>r\t%0,%2 |
65b1d8ea | 5899 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5900 | al<g>\t%0,%2 |
5901 | al<y>\t%0,%2" | |
65b1d8ea | 5902 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5903 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5904 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5905 | |
963fc8d0 | 5906 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
5907 | (define_insn "*add<mode>3_imm_cc" |
5908 | [(set (reg CC_REGNUM) | |
65b1d8ea | 5909 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
3e4be43f | 5910 | (match_operand:GPR 2 "const_int_operand" " K, K,Os,C")) |
3298c037 | 5911 | (const_int 0))) |
3e4be43f | 5912 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S") |
3298c037 AK |
5913 | (plus:GPR (match_dup 1) (match_dup 2)))] |
5914 | "s390_match_ccmode (insn, CCAmode) | |
5915 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
5916 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
5917 | /* Avoid INT32_MIN on 32 bit. */ | |
5918 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 5919 | "@ |
3298c037 | 5920 | a<g>hi\t%0,%h2 |
65b1d8ea | 5921 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
5922 | a<g>fi\t%0,%2 |
5923 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5924 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
5925 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
5926 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5927 | |
7d2fd075 AK |
5928 | (define_insn "*adddi3_sign" |
5929 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5930 | (plus:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
5931 | (match_operand:DI 1 "register_operand" "0"))) | |
5932 | (clobber (reg:CC CC_REGNUM))] | |
e9e8efc9 | 5933 | "TARGET_Z14" |
7d2fd075 AK |
5934 | "agh\t%0,%2" |
5935 | [(set_attr "op_type" "RXY")]) | |
5936 | ||
9db1d521 | 5937 | ; |
609e7e80 | 5938 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5939 | ; |
5940 | ||
609e7e80 | 5941 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
6e5b5de8 | 5942 | ; FIXME: wfadb does not clobber cc |
142cd70f | 5943 | (define_insn "add<mode>3" |
2de2b3f9 AK |
5944 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
5945 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
5946 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 5947 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5948 | "TARGET_HARD_FLOAT" |
9db1d521 | 5949 | "@ |
62d3f261 AK |
5950 | a<xde>tr\t%0,%1,%2 |
5951 | a<xde>br\t%0,%2 | |
6e5b5de8 | 5952 | a<xde>b\t%0,%2 |
2de2b3f9 AK |
5953 | wfadb\t%v0,%v1,%v2 |
5954 | wfasb\t%v0,%v1,%v2" | |
5955 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 5956 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
5957 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
5958 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 5959 | |
609e7e80 | 5960 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5961 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5962 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5963 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5964 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5965 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5966 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 5967 | (plus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 5968 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5969 | "@ |
62d3f261 AK |
5970 | a<xde>tr\t%0,%1,%2 |
5971 | a<xde>br\t%0,%2 | |
f61a2c7d | 5972 | a<xde>b\t%0,%2" |
62d3f261 AK |
5973 | [(set_attr "op_type" "RRF,RRE,RXE") |
5974 | (set_attr "type" "fsimp<mode>") | |
5975 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5976 | |
609e7e80 | 5977 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5978 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5979 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5980 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5981 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5982 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5983 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 5984 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5985 | "@ |
62d3f261 AK |
5986 | a<xde>tr\t%0,%1,%2 |
5987 | a<xde>br\t%0,%2 | |
f61a2c7d | 5988 | a<xde>b\t%0,%2" |
62d3f261 AK |
5989 | [(set_attr "op_type" "RRF,RRE,RXE") |
5990 | (set_attr "type" "fsimp<mode>") | |
5991 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5992 | |
72a4ddf2 AK |
5993 | ; |
5994 | ; Pointer add instruction patterns | |
5995 | ; | |
5996 | ||
5997 | ; This will match "*la_64" | |
5998 | (define_expand "addptrdi3" | |
5999 | [(set (match_operand:DI 0 "register_operand" "") | |
6000 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
6001 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
6002 | "TARGET_64BIT" | |
6003 | { | |
72a4ddf2 AK |
6004 | if (GET_CODE (operands[2]) == CONST_INT) |
6005 | { | |
357ddc7d TV |
6006 | HOST_WIDE_INT c = INTVAL (operands[2]); |
6007 | ||
72a4ddf2 AK |
6008 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
6009 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
6010 | { | |
6011 | operands[2] = force_const_mem (DImode, operands[2]); | |
6012 | operands[2] = force_reg (DImode, operands[2]); | |
6013 | } | |
6014 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
6015 | operands[2] = force_reg (DImode, operands[2]); | |
6016 | } | |
6017 | }) | |
6018 | ||
6019 | ; For 31 bit we have to prevent the generated pattern from matching | |
6020 | ; normal ADDs since la only does a 31 bit add. This is supposed to | |
6021 | ; match "force_la_31". | |
6022 | (define_expand "addptrsi3" | |
6023 | [(parallel | |
6024 | [(set (match_operand:SI 0 "register_operand" "") | |
6025 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
6026 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
6027 | (use (const_int 0))])] | |
6028 | "!TARGET_64BIT" | |
6029 | { | |
72a4ddf2 AK |
6030 | if (GET_CODE (operands[2]) == CONST_INT) |
6031 | { | |
357ddc7d TV |
6032 | HOST_WIDE_INT c = INTVAL (operands[2]); |
6033 | ||
72a4ddf2 AK |
6034 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
6035 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
6036 | { | |
6037 | operands[2] = force_const_mem (SImode, operands[2]); | |
6038 | operands[2] = force_reg (SImode, operands[2]); | |
6039 | } | |
6040 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
6041 | operands[2] = force_reg (SImode, operands[2]); | |
6042 | } | |
6043 | }) | |
9db1d521 HP |
6044 | |
6045 | ;; | |
6046 | ;;- Subtract instructions. | |
6047 | ;; | |
6048 | ||
1c7b1b7e UW |
6049 | ; |
6050 | ; subti3 instruction pattern(s). | |
6051 | ; | |
6052 | ||
085261c8 AK |
6053 | (define_expand "subti3" |
6054 | [(parallel | |
6055 | [(set (match_operand:TI 0 "register_operand" "") | |
6056 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
6057 | (match_operand:TI 2 "general_operand" "") ) ) | |
6058 | (clobber (reg:CC CC_REGNUM))])] | |
6059 | "TARGET_ZARCH" | |
6060 | { | |
2d71f118 | 6061 | /* For z13 we have vsq which doesn't set CC. */ |
085261c8 AK |
6062 | if (TARGET_VX) |
6063 | { | |
6064 | emit_insn (gen_rtx_SET (operands[0], | |
6065 | gen_rtx_MINUS (TImode, | |
6066 | operands[1], | |
6067 | copy_to_mode_reg (TImode, operands[2])))); | |
6068 | DONE; | |
6069 | } | |
6070 | }) | |
6071 | ||
6072 | (define_insn_and_split "*subti3" | |
6073 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
6074 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
6075 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 6076 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6077 | "TARGET_ZARCH" |
1c7b1b7e UW |
6078 | "#" |
6079 | "&& reload_completed" | |
6080 | [(parallel | |
ae156f85 | 6081 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
6082 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
6083 | (match_dup 7))) | |
6084 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
6085 | (parallel | |
6086 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6087 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6088 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
6089 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
6090 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
6091 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
6092 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
6093 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
6094 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
6095 | [(set_attr "op_type" "*") | |
6096 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 6097 | |
9db1d521 HP |
6098 | ; |
6099 | ; subdi3 instruction pattern(s). | |
6100 | ; | |
6101 | ||
3298c037 AK |
6102 | (define_expand "subdi3" |
6103 | [(parallel | |
6104 | [(set (match_operand:DI 0 "register_operand" "") | |
6105 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
6106 | (match_operand:DI 2 "general_operand" ""))) | |
6107 | (clobber (reg:CC CC_REGNUM))])] | |
6108 | "" | |
6109 | "") | |
6110 | ||
07893d4f UW |
6111 | (define_insn "*subdi3_sign" |
6112 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6113 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6114 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6115 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6116 | "TARGET_ZARCH" |
07893d4f | 6117 | "@ |
d40c829f UW |
6118 | sgfr\t%0,%2 |
6119 | sgf\t%0,%2" | |
9381e3f1 | 6120 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
6121 | (set_attr "z10prop" "z10_c,*") |
6122 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
6123 | |
6124 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 6125 | [(set (reg CC_REGNUM) |
07893d4f | 6126 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6127 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6128 | (const_int 0))) |
6129 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
6130 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 6131 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6132 | "@ |
d40c829f UW |
6133 | slgfr\t%0,%2 |
6134 | slgf\t%0,%2" | |
9381e3f1 WG |
6135 | [(set_attr "op_type" "RRE,RXY") |
6136 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6137 | |
6138 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 6139 | [(set (reg CC_REGNUM) |
07893d4f | 6140 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6141 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6142 | (const_int 0))) |
6143 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 6144 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6145 | "@ |
d40c829f UW |
6146 | slgfr\t%0,%2 |
6147 | slgf\t%0,%2" | |
9381e3f1 WG |
6148 | [(set_attr "op_type" "RRE,RXY") |
6149 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6150 | |
6151 | (define_insn "*subdi3_zero" | |
6152 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6153 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6154 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6155 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6156 | "TARGET_ZARCH" |
07893d4f | 6157 | "@ |
d40c829f UW |
6158 | slgfr\t%0,%2 |
6159 | slgf\t%0,%2" | |
9381e3f1 WG |
6160 | [(set_attr "op_type" "RRE,RXY") |
6161 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 6162 | |
e69166de UW |
6163 | (define_insn_and_split "*subdi3_31z" |
6164 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
6165 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6166 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 6167 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6168 | "!TARGET_ZARCH" |
e69166de UW |
6169 | "#" |
6170 | "&& reload_completed" | |
6171 | [(parallel | |
ae156f85 | 6172 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
6173 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
6174 | (match_dup 7))) | |
6175 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
6176 | (parallel | |
6177 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6178 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6179 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
6180 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
6181 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
6182 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
6183 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
6184 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 6185 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 6186 | |
3298c037 AK |
6187 | ; |
6188 | ; subsi3 instruction pattern(s). | |
6189 | ; | |
6190 | ||
6191 | (define_expand "subsi3" | |
07893d4f | 6192 | [(parallel |
3298c037 AK |
6193 | [(set (match_operand:SI 0 "register_operand" "") |
6194 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
6195 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 6196 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 6197 | "" |
07893d4f | 6198 | "") |
9db1d521 | 6199 | |
3298c037 AK |
6200 | (define_insn "*subsi3_sign" |
6201 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
6202 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
6203 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
6204 | (clobber (reg:CC CC_REGNUM))] | |
6205 | "" | |
6206 | "@ | |
6207 | sh\t%0,%2 | |
6208 | shy\t%0,%2" | |
65b1d8ea | 6209 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 6210 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 6211 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 6212 | |
9db1d521 | 6213 | ; |
3298c037 | 6214 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
6215 | ; |
6216 | ||
65b1d8ea | 6217 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 6218 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
6219 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
6220 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
6221 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
6222 | (clobber (reg:CC CC_REGNUM))] |
6223 | "" | |
6224 | "@ | |
6225 | s<g>r\t%0,%2 | |
65b1d8ea | 6226 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
6227 | s<g>\t%0,%2 |
6228 | s<y>\t%0,%2" | |
65b1d8ea | 6229 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6230 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6231 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
3298c037 | 6232 | |
65b1d8ea | 6233 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6234 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 6235 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6236 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6237 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6238 | (match_dup 1))) |
65b1d8ea | 6239 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6240 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6241 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6242 | "@ |
3298c037 | 6243 | sl<g>r\t%0,%2 |
65b1d8ea | 6244 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6245 | sl<g>\t%0,%2 |
6246 | sl<y>\t%0,%2" | |
65b1d8ea | 6247 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6248 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6249 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6250 | |
65b1d8ea | 6251 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6252 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 6253 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6254 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6255 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6256 | (match_dup 1))) |
65b1d8ea | 6257 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6258 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6259 | "@ |
3298c037 | 6260 | sl<g>r\t%0,%2 |
65b1d8ea | 6261 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6262 | sl<g>\t%0,%2 |
6263 | sl<y>\t%0,%2" | |
65b1d8ea | 6264 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6265 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6266 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6267 | |
65b1d8ea | 6268 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6269 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6270 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6271 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6272 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6273 | (const_int 0))) |
65b1d8ea | 6274 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6275 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6276 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6277 | "@ |
3298c037 | 6278 | sl<g>r\t%0,%2 |
65b1d8ea | 6279 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6280 | sl<g>\t%0,%2 |
6281 | sl<y>\t%0,%2" | |
65b1d8ea | 6282 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6283 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6284 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 6285 | |
65b1d8ea | 6286 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6287 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 6288 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6289 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6290 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6291 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 6292 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
6293 | "s390_match_ccmode (insn, CCL3mode)" |
6294 | "@ | |
3298c037 | 6295 | sl<g>r\t%0,%2 |
65b1d8ea | 6296 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6297 | sl<g>\t%0,%2 |
6298 | sl<y>\t%0,%2" | |
65b1d8ea | 6299 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6300 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6301 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
5d880bd2 | 6302 | |
65b1d8ea | 6303 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6304 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6305 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6306 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6307 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6308 | (const_int 0))) |
65b1d8ea | 6309 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6310 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6311 | "@ |
3298c037 | 6312 | sl<g>r\t%0,%2 |
65b1d8ea | 6313 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6314 | sl<g>\t%0,%2 |
6315 | sl<y>\t%0,%2" | |
65b1d8ea | 6316 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6317 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6318 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6319 | |
9db1d521 | 6320 | |
65b1d8ea | 6321 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6322 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 6323 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6324 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6325 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6326 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
6327 | "s390_match_ccmode (insn, CCL3mode)" |
6328 | "@ | |
3298c037 | 6329 | sl<g>r\t%0,%2 |
65b1d8ea | 6330 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6331 | sl<g>\t%0,%2 |
6332 | sl<y>\t%0,%2" | |
65b1d8ea | 6333 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6334 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6335 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6336 | |
7d2fd075 AK |
6337 | (define_insn "*subdi3_sign" |
6338 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6339 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6340 | (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")))) | |
6341 | (clobber (reg:CC CC_REGNUM))] | |
e9e8efc9 | 6342 | "TARGET_Z14" |
7d2fd075 AK |
6343 | "sgh\t%0,%2" |
6344 | [(set_attr "op_type" "RXY")]) | |
6345 | ||
9db1d521 HP |
6346 | |
6347 | ; | |
609e7e80 | 6348 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6349 | ; |
6350 | ||
2de2b3f9 | 6351 | ; FIXME: (clobber (match_scratch:CC 3 "=c,c,c,X,X")) does not work - why? |
d46f24b6 | 6352 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 6353 | (define_insn "sub<mode>3" |
2de2b3f9 AK |
6354 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6355 | (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
6356 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 6357 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6358 | "TARGET_HARD_FLOAT" |
9db1d521 | 6359 | "@ |
62d3f261 AK |
6360 | s<xde>tr\t%0,%1,%2 |
6361 | s<xde>br\t%0,%2 | |
6e5b5de8 | 6362 | s<xde>b\t%0,%2 |
2de2b3f9 AK |
6363 | wfsdb\t%v0,%v1,%v2 |
6364 | wfssb\t%v0,%v1,%v2" | |
6365 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6366 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
6367 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6368 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6369 | |
d46f24b6 | 6370 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6371 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6372 | [(set (reg CC_REGNUM) |
62d3f261 | 6373 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
2de2b3f9 | 6374 | (match_operand:FP 2 "general_operand" "f,f,R")) |
609e7e80 | 6375 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6376 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 6377 | (minus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 6378 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6379 | "@ |
62d3f261 AK |
6380 | s<xde>tr\t%0,%1,%2 |
6381 | s<xde>br\t%0,%2 | |
f61a2c7d | 6382 | s<xde>b\t%0,%2" |
62d3f261 AK |
6383 | [(set_attr "op_type" "RRF,RRE,RXE") |
6384 | (set_attr "type" "fsimp<mode>") | |
6385 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6386 | |
d46f24b6 | 6387 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6388 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6389 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6390 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
6391 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6392 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6393 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 6394 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6395 | "@ |
62d3f261 AK |
6396 | s<xde>tr\t%0,%1,%2 |
6397 | s<xde>br\t%0,%2 | |
f61a2c7d | 6398 | s<xde>b\t%0,%2" |
62d3f261 AK |
6399 | [(set_attr "op_type" "RRF,RRE,RXE") |
6400 | (set_attr "type" "fsimp<mode>") | |
6401 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6402 | |
9db1d521 | 6403 | |
e69166de UW |
6404 | ;; |
6405 | ;;- Conditional add/subtract instructions. | |
6406 | ;; | |
6407 | ||
6408 | ; | |
9a91a21f | 6409 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
6410 | ; |
6411 | ||
a996720c UW |
6412 | ; the following 4 patterns are used when the result of an add with |
6413 | ; carry is checked for an overflow condition | |
6414 | ||
6415 | ; op1 + op2 + c < op1 | |
6416 | ||
6417 | ; alcr, alc, alcgr, alcg | |
6418 | (define_insn "*add<mode>3_alc_carry1_cc" | |
6419 | [(set (reg CC_REGNUM) | |
6420 | (compare | |
6421 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6422 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6423 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6424 | (match_dup 1))) |
6425 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6426 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
8cc6307c | 6427 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6428 | "@ |
6429 | alc<g>r\t%0,%2 | |
6430 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6431 | [(set_attr "op_type" "RRE,RXY") |
6432 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6433 | |
6434 | ; alcr, alc, alcgr, alcg | |
6435 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
6436 | [(set (reg CC_REGNUM) | |
6437 | (compare | |
6438 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6439 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6440 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6441 | (match_dup 1))) |
6442 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
8cc6307c | 6443 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6444 | "@ |
6445 | alc<g>r\t%0,%2 | |
6446 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6447 | [(set_attr "op_type" "RRE,RXY") |
6448 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6449 | |
6450 | ; op1 + op2 + c < op2 | |
6451 | ||
6452 | ; alcr, alc, alcgr, alcg | |
6453 | (define_insn "*add<mode>3_alc_carry2_cc" | |
6454 | [(set (reg CC_REGNUM) | |
6455 | (compare | |
6456 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6457 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6458 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6459 | (match_dup 2))) |
6460 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6461 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
8cc6307c | 6462 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6463 | "@ |
6464 | alc<g>r\t%0,%2 | |
6465 | alc<g>\t%0,%2" | |
6466 | [(set_attr "op_type" "RRE,RXY")]) | |
6467 | ||
6468 | ; alcr, alc, alcgr, alcg | |
6469 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
6470 | [(set (reg CC_REGNUM) | |
6471 | (compare | |
6472 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6473 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6474 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6475 | (match_dup 2))) |
6476 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
8cc6307c | 6477 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6478 | "@ |
6479 | alc<g>r\t%0,%2 | |
6480 | alc<g>\t%0,%2" | |
6481 | [(set_attr "op_type" "RRE,RXY")]) | |
6482 | ||
43a09b63 | 6483 | ; alcr, alc, alcgr, alcg |
9a91a21f | 6484 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 6485 | [(set (reg CC_REGNUM) |
e69166de | 6486 | (compare |
a94a76a7 UW |
6487 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6488 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6489 | (match_operand:GPR 2 "general_operand" "d,T")) |
e69166de | 6490 | (const_int 0))) |
9a91a21f | 6491 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 6492 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
8cc6307c | 6493 | "s390_match_ccmode (insn, CCLmode)" |
e69166de | 6494 | "@ |
9a91a21f AS |
6495 | alc<g>r\t%0,%2 |
6496 | alc<g>\t%0,%2" | |
e69166de UW |
6497 | [(set_attr "op_type" "RRE,RXY")]) |
6498 | ||
43a09b63 | 6499 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
6500 | (define_insn "*add<mode>3_alc" |
6501 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
6502 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6503 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6504 | (match_operand:GPR 2 "general_operand" "d,T"))) |
ae156f85 | 6505 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6506 | "" |
e69166de | 6507 | "@ |
9a91a21f AS |
6508 | alc<g>r\t%0,%2 |
6509 | alc<g>\t%0,%2" | |
e69166de UW |
6510 | [(set_attr "op_type" "RRE,RXY")]) |
6511 | ||
43a09b63 | 6512 | ; slbr, slb, slbgr, slbg |
9a91a21f | 6513 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 6514 | [(set (reg CC_REGNUM) |
e69166de | 6515 | (compare |
9a91a21f | 6516 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
3e4be43f | 6517 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6518 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 6519 | (const_int 0))) |
9a91a21f AS |
6520 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
6521 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
8cc6307c | 6522 | "s390_match_ccmode (insn, CCLmode)" |
e69166de | 6523 | "@ |
9a91a21f AS |
6524 | slb<g>r\t%0,%2 |
6525 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6526 | [(set_attr "op_type" "RRE,RXY") |
6527 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6528 | |
43a09b63 | 6529 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
6530 | (define_insn "*sub<mode>3_slb" |
6531 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
6532 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
3e4be43f | 6533 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6534 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 6535 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6536 | "" |
e69166de | 6537 | "@ |
9a91a21f AS |
6538 | slb<g>r\t%0,%2 |
6539 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6540 | [(set_attr "op_type" "RRE,RXY") |
6541 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6542 | |
9a91a21f AS |
6543 | (define_expand "add<mode>cc" |
6544 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 6545 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
6546 | (match_operand:GPR 2 "register_operand" "") |
6547 | (match_operand:GPR 3 "const_int_operand" "")] | |
8cc6307c | 6548 | "" |
9381e3f1 | 6549 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 6550 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 6551 | operands[0], operands[2], |
5d880bd2 UW |
6552 | operands[3])) FAIL; DONE;") |
6553 | ||
6554 | ; | |
6555 | ; scond instruction pattern(s). | |
6556 | ; | |
6557 | ||
9a91a21f AS |
6558 | (define_insn_and_split "*scond<mode>" |
6559 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6560 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 6561 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6562 | "" |
5d880bd2 UW |
6563 | "#" |
6564 | "&& reload_completed" | |
6565 | [(set (match_dup 0) (const_int 0)) | |
6566 | (parallel | |
a94a76a7 UW |
6567 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
6568 | (match_dup 0))) | |
ae156f85 | 6569 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6570 | "") |
5d880bd2 | 6571 | |
9a91a21f AS |
6572 | (define_insn_and_split "*scond<mode>_neg" |
6573 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6574 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 6575 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6576 | "" |
5d880bd2 UW |
6577 | "#" |
6578 | "&& reload_completed" | |
6579 | [(set (match_dup 0) (const_int 0)) | |
6580 | (parallel | |
9a91a21f AS |
6581 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
6582 | (match_dup 1))) | |
ae156f85 | 6583 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 6584 | (parallel |
9a91a21f | 6585 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 6586 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6587 | "") |
5d880bd2 | 6588 | |
5d880bd2 | 6589 | |
f90b7a5a | 6590 | (define_expand "cstore<mode>4" |
9a91a21f | 6591 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
6592 | (match_operator:SI 1 "s390_scond_operator" |
6593 | [(match_operand:GPR 2 "register_operand" "") | |
6594 | (match_operand:GPR 3 "general_operand" "")]))] | |
8cc6307c | 6595 | "" |
f90b7a5a | 6596 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
6597 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
6598 | ||
f90b7a5a | 6599 | (define_expand "cstorecc4" |
69950452 | 6600 | [(parallel |
f90b7a5a PB |
6601 | [(set (match_operand:SI 0 "register_operand" "") |
6602 | (match_operator:SI 1 "s390_eqne_operator" | |
3ea685e7 | 6603 | [(match_operand 2 "cc_reg_operand") |
f90b7a5a | 6604 | (match_operand 3 "const0_operand")])) |
69950452 AS |
6605 | (clobber (reg:CC CC_REGNUM))])] |
6606 | "" | |
3ea685e7 DV |
6607 | "machine_mode mode = GET_MODE (operands[2]); |
6608 | if (TARGET_Z196) | |
6609 | { | |
6610 | rtx cond, ite; | |
6611 | ||
6612 | if (GET_CODE (operands[1]) == NE) | |
6613 | cond = gen_rtx_NE (VOIDmode, operands[2], const0_rtx); | |
6614 | else | |
6615 | cond = gen_rtx_EQ (VOIDmode, operands[2], const0_rtx); | |
6616 | ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, const0_rtx); | |
6617 | emit_insn (gen_rtx_SET (operands[0], ite)); | |
6618 | } | |
6619 | else | |
6620 | { | |
6621 | if (mode != CCZ1mode) | |
6622 | FAIL; | |
6623 | emit_insn (gen_sne (operands[0], operands[2])); | |
6624 | if (GET_CODE (operands[1]) == EQ) | |
6625 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
6626 | } | |
f90b7a5a | 6627 | DONE;") |
69950452 | 6628 | |
f90b7a5a | 6629 | (define_insn_and_split "sne" |
69950452 | 6630 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 6631 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
6632 | (const_int 0))) |
6633 | (clobber (reg:CC CC_REGNUM))] | |
6634 | "" | |
6635 | "#" | |
6636 | "reload_completed" | |
6637 | [(parallel | |
6638 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
6639 | (clobber (reg:CC CC_REGNUM))])]) | |
6640 | ||
e69166de | 6641 | |
65b1d8ea AK |
6642 | ;; |
6643 | ;; - Conditional move instructions (introduced with z196) | |
6644 | ;; | |
6645 | ||
6646 | (define_expand "mov<mode>cc" | |
6647 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
6648 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
88e845c0 RD |
6649 | (match_operand:GPR 2 "loc_operand" "") |
6650 | (match_operand:GPR 3 "loc_operand" "")))] | |
65b1d8ea | 6651 | "TARGET_Z196" |
7477de01 | 6652 | { |
88e845c0 RD |
6653 | if (!TARGET_Z13 && CONSTANT_P (operands[2])) |
6654 | operands[2] = force_reg (<MODE>mode, operands[2]); | |
6655 | ||
6656 | if (!TARGET_Z13 && CONSTANT_P (operands[3])) | |
6657 | operands[3] = force_reg (<MODE>mode, operands[3]); | |
6658 | ||
7477de01 AK |
6659 | /* Emit the comparison insn in case we do not already have a comparison result. */ |
6660 | if (!s390_comparison (operands[1], VOIDmode)) | |
6661 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6662 | XEXP (operands[1], 0), | |
6663 | XEXP (operands[1], 1)); | |
6664 | }) | |
65b1d8ea | 6665 | |
d8928886 RD |
6666 | ;; |
6667 | ;; - We do not have instructions for QImode or HImode but still | |
6668 | ;; enable load on condition/if conversion for them. | |
6669 | (define_expand "mov<mode>cc" | |
6670 | [(set (match_operand:HQI 0 "nonimmediate_operand" "") | |
6671 | (if_then_else:HQI (match_operand 1 "comparison_operator" "") | |
6672 | (match_operand:HQI 2 "loc_operand" "") | |
6673 | (match_operand:HQI 3 "loc_operand" "")))] | |
6674 | "TARGET_Z196" | |
6675 | { | |
6676 | /* Emit the comparison insn in case we do not already have a comparison | |
6677 | result. */ | |
6678 | if (!s390_comparison (operands[1], VOIDmode)) | |
6679 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6680 | XEXP (operands[1], 0), | |
6681 | XEXP (operands[1], 1)); | |
6682 | ||
6683 | rtx then = operands[2]; | |
6684 | rtx els = operands[3]; | |
6685 | ||
6686 | if ((!TARGET_Z13 && CONSTANT_P (then)) || MEM_P (then)) | |
6687 | then = force_reg (<MODE>mode, then); | |
6688 | if ((!TARGET_Z13 && CONSTANT_P (els)) || MEM_P (els)) | |
6689 | els = force_reg (<MODE>mode, els); | |
6690 | ||
6691 | if (!CONSTANT_P (then)) | |
6692 | then = simplify_gen_subreg (E_SImode, then, <MODE>mode, 0); | |
6693 | if (!CONSTANT_P (els)) | |
6694 | els = simplify_gen_subreg (E_SImode, els, <MODE>mode, 0); | |
6695 | ||
6696 | rtx tmp_target = gen_reg_rtx (E_SImode); | |
6697 | emit_insn (gen_movsicc (tmp_target, operands[1], then, els)); | |
6698 | emit_move_insn (operands[0], gen_lowpart (<MODE>mode, tmp_target)); | |
6699 | DONE; | |
6700 | }) | |
6701 | ||
6702 | ||
6703 | ||
bf749919 | 6704 | ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi |
561f6312 AK |
6705 | (define_insn "*mov<mode>cc" |
6706 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S") | |
65b1d8ea AK |
6707 | (if_then_else:GPR |
6708 | (match_operator 1 "s390_comparison" | |
561f6312 | 6709 | [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c") |
5a3fe9b6 | 6710 | (match_operand 5 "const_int_operand" "")]) |
561f6312 AK |
6711 | (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0") |
6712 | (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d")))] | |
65b1d8ea AK |
6713 | "TARGET_Z196" |
6714 | "@ | |
6715 | loc<g>r%C1\t%0,%3 | |
6716 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
6717 | loc<g>%C1\t%0,%3 |
6718 | loc<g>%D1\t%0,%4 | |
bf749919 DV |
6719 | loc<g>hi%C1\t%0,%h3 |
6720 | loc<g>hi%D1\t%0,%h4 | |
a6510374 | 6721 | stoc<g>%C1\t%3,%0 |
561f6312 AK |
6722 | stoc<g>%D1\t%4,%0" |
6723 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY") | |
6724 | (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*")]) | |
65b1d8ea | 6725 | |
9db1d521 HP |
6726 | ;; |
6727 | ;;- Multiply instructions. | |
6728 | ;; | |
6729 | ||
4023fb28 UW |
6730 | ; |
6731 | ; muldi3 instruction pattern(s). | |
6732 | ; | |
9db1d521 | 6733 | |
7d2fd075 AK |
6734 | (define_expand "muldi3" |
6735 | [(parallel | |
6736 | [(set (match_operand:DI 0 "register_operand") | |
6737 | (mult:DI (match_operand:DI 1 "nonimmediate_operand") | |
6738 | (match_operand:DI 2 "general_operand"))) | |
6739 | (clobber (reg:CC CC_REGNUM))])] | |
6740 | "TARGET_ZARCH") | |
6741 | ||
07893d4f UW |
6742 | (define_insn "*muldi3_sign" |
6743 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 6744 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 6745 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 6746 | "TARGET_ZARCH" |
07893d4f | 6747 | "@ |
d40c829f UW |
6748 | msgfr\t%0,%2 |
6749 | msgf\t%0,%2" | |
963fc8d0 AK |
6750 | [(set_attr "op_type" "RRE,RXY") |
6751 | (set_attr "type" "imuldi")]) | |
07893d4f | 6752 | |
7d2fd075 AK |
6753 | (define_insn "*muldi3" |
6754 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d") | |
6755 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0") | |
6756 | (match_operand:DI 2 "general_operand" "d,d,K,T,Os"))) | |
6757 | (clobber (match_scratch:CC 3 "=X,c,X,X,X"))] | |
9602b6a1 | 6758 | "TARGET_ZARCH" |
9db1d521 | 6759 | "@ |
d40c829f | 6760 | msgr\t%0,%2 |
7d2fd075 | 6761 | msgrkc\t%0,%1,%2 |
d40c829f | 6762 | mghi\t%0,%h2 |
963fc8d0 AK |
6763 | msg\t%0,%2 |
6764 | msgfi\t%0,%2" | |
7d2fd075 | 6765 | [(set_attr "op_type" "RRE,RRF,RI,RXY,RIL") |
963fc8d0 | 6766 | (set_attr "type" "imuldi") |
e9e8efc9 | 6767 | (set_attr "cpu_facility" "*,z14,*,*,z10")]) |
7d2fd075 AK |
6768 | |
6769 | (define_insn "mulditi3" | |
6770 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6771 | (mult:TI (sign_extend:TI | |
6772 | (match_operand:DI 1 "register_operand" "%d,0")) | |
6773 | (sign_extend:TI | |
6774 | (match_operand:DI 2 "nonimmediate_operand" " d,T"))))] | |
e9e8efc9 | 6775 | "TARGET_Z14" |
7d2fd075 AK |
6776 | "@ |
6777 | mgrk\t%0,%1,%2 | |
6778 | mg\t%0,%2" | |
6779 | [(set_attr "op_type" "RRF,RXY")]) | |
6780 | ||
6781 | ; Combine likes op1 and op2 to be swapped sometimes. | |
6782 | (define_insn "mulditi3_2" | |
6783 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6784 | (mult:TI (sign_extend:TI | |
6785 | (match_operand:DI 1 "nonimmediate_operand" "%d,T")) | |
6786 | (sign_extend:TI | |
6787 | (match_operand:DI 2 "register_operand" " d,0"))))] | |
e9e8efc9 | 6788 | "TARGET_Z14" |
7d2fd075 AK |
6789 | "@ |
6790 | mgrk\t%0,%1,%2 | |
6791 | mg\t%0,%1" | |
6792 | [(set_attr "op_type" "RRF,RXY")]) | |
6793 | ||
6794 | (define_insn "*muldi3_sign" | |
6795 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6796 | (mult:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
6797 | (match_operand:DI 1 "register_operand" "0")))] | |
e9e8efc9 | 6798 | "TARGET_Z14" |
7d2fd075 AK |
6799 | "mgh\t%0,%2" |
6800 | [(set_attr "op_type" "RXY")]) | |
6801 | ||
f2d3c02a | 6802 | |
9db1d521 HP |
6803 | ; |
6804 | ; mulsi3 instruction pattern(s). | |
6805 | ; | |
6806 | ||
7d2fd075 AK |
6807 | (define_expand "mulsi3" |
6808 | [(parallel | |
6809 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6810 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6811 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
6812 | (clobber (reg:CC CC_REGNUM))])] | |
6813 | "") | |
6814 | ||
f1e77d83 | 6815 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
6816 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6817 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
6818 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 6819 | "" |
963fc8d0 AK |
6820 | "@ |
6821 | mh\t%0,%2 | |
6822 | mhy\t%0,%2" | |
6823 | [(set_attr "op_type" "RX,RXY") | |
6824 | (set_attr "type" "imulhi") | |
6825 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 6826 | |
7d2fd075 AK |
6827 | (define_insn "*mulsi3" |
6828 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6829 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6830 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
6831 | (clobber (match_scratch:CC 3 "=X,c,X,X,X,X"))] | |
9db1d521 HP |
6832 | "" |
6833 | "@ | |
d40c829f | 6834 | msr\t%0,%2 |
7d2fd075 | 6835 | msrkc\t%0,%1,%2 |
d40c829f UW |
6836 | mhi\t%0,%h2 |
6837 | ms\t%0,%2 | |
963fc8d0 AK |
6838 | msy\t%0,%2 |
6839 | msfi\t%0,%2" | |
7d2fd075 AK |
6840 | [(set_attr "op_type" "RRE,RRF,RI,RX,RXY,RIL") |
6841 | (set_attr "type" "imulsi,*,imulhi,imulsi,imulsi,imulsi") | |
e9e8efc9 | 6842 | (set_attr "cpu_facility" "*,z14,*,*,longdisp,z10")]) |
9db1d521 | 6843 | |
4023fb28 UW |
6844 | ; |
6845 | ; mulsidi3 instruction pattern(s). | |
6846 | ; | |
6847 | ||
f1e77d83 | 6848 | (define_insn "mulsidi3" |
963fc8d0 | 6849 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 6850 | (mult:DI (sign_extend:DI |
963fc8d0 | 6851 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 6852 | (sign_extend:DI |
963fc8d0 | 6853 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 6854 | "!TARGET_ZARCH" |
f1e77d83 UW |
6855 | "@ |
6856 | mr\t%0,%2 | |
963fc8d0 AK |
6857 | m\t%0,%2 |
6858 | mfy\t%0,%2" | |
6859 | [(set_attr "op_type" "RR,RX,RXY") | |
6860 | (set_attr "type" "imulsi") | |
6861 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 6862 | |
f1e77d83 | 6863 | ; |
6e0d70c9 | 6864 | ; umul instruction pattern(s). |
f1e77d83 | 6865 | ; |
c7453384 | 6866 | |
6e0d70c9 AK |
6867 | ; mlr, ml, mlgr, mlg |
6868 | (define_insn "umul<dwh><mode>3" | |
3e4be43f | 6869 | [(set (match_operand:DW 0 "register_operand" "=d,d") |
6e0d70c9 | 6870 | (mult:DW (zero_extend:DW |
3e4be43f | 6871 | (match_operand:<DWH> 1 "register_operand" "%0,0")) |
6e0d70c9 | 6872 | (zero_extend:DW |
3e4be43f | 6873 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))] |
8cc6307c | 6874 | "" |
f1e77d83 | 6875 | "@ |
6e0d70c9 AK |
6876 | ml<tg>r\t%0,%2 |
6877 | ml<tg>\t%0,%2" | |
f1e77d83 | 6878 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 6879 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 6880 | |
9db1d521 | 6881 | ; |
609e7e80 | 6882 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6883 | ; |
6884 | ||
9381e3f1 | 6885 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 6886 | (define_insn "mul<mode>3" |
2de2b3f9 AK |
6887 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6888 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
6889 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 6890 | "TARGET_HARD_FLOAT" |
9db1d521 | 6891 | "@ |
62d3f261 AK |
6892 | m<xdee>tr\t%0,%1,%2 |
6893 | m<xdee>br\t%0,%2 | |
6e5b5de8 | 6894 | m<xdee>b\t%0,%2 |
2de2b3f9 AK |
6895 | wfmdb\t%v0,%v1,%v2 |
6896 | wfmsb\t%v0,%v1,%v2" | |
6897 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6898 | (set_attr "type" "fmul<mode>") |
2de2b3f9 AK |
6899 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6900 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6901 | |
9381e3f1 | 6902 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 6903 | (define_insn "fma<mode>4" |
2de2b3f9 AK |
6904 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
6905 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
6906 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
6907 | (match_operand:DSF 3 "register_operand" "0,0,v,v")))] | |
d7ecb504 | 6908 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6909 | "@ |
f61a2c7d | 6910 | ma<xde>br\t%0,%1,%2 |
6e5b5de8 | 6911 | ma<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
6912 | wfmadb\t%v0,%v1,%v2,%v3 |
6913 | wfmasb\t%v0,%v1,%v2,%v3" | |
6914 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6915 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
6916 | (set_attr "cpu_facility" "*,*,vx,vxe") |
6917 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
a1b892b5 | 6918 | |
43a09b63 | 6919 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 6920 | (define_insn "fms<mode>4" |
2de2b3f9 AK |
6921 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
6922 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
6923 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
6924 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v,v"))))] | |
d7ecb504 | 6925 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6926 | "@ |
f61a2c7d | 6927 | ms<xde>br\t%0,%1,%2 |
6e5b5de8 | 6928 | ms<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
6929 | wfmsdb\t%v0,%v1,%v2,%v3 |
6930 | wfmssb\t%v0,%v1,%v2,%v3" | |
6931 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6932 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
6933 | (set_attr "cpu_facility" "*,*,vx,vxe") |
6934 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
9db1d521 HP |
6935 | |
6936 | ;; | |
6937 | ;;- Divide and modulo instructions. | |
6938 | ;; | |
6939 | ||
6940 | ; | |
4023fb28 | 6941 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
6942 | ; |
6943 | ||
4023fb28 UW |
6944 | (define_expand "divmoddi4" |
6945 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 6946 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
6947 | (match_operand:DI 2 "general_operand" ""))) |
6948 | (set (match_operand:DI 3 "general_operand" "") | |
6949 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
6950 | (clobber (match_dup 4))] | |
9602b6a1 | 6951 | "TARGET_ZARCH" |
9db1d521 | 6952 | { |
d8485bdb TS |
6953 | rtx div_equal, mod_equal; |
6954 | rtx_insn *insn; | |
4023fb28 UW |
6955 | |
6956 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
6957 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
6958 | |
6959 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 6960 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
6961 | |
6962 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6963 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6964 | |
6965 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6966 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6967 | |
9db1d521 | 6968 | DONE; |
10bbf137 | 6969 | }) |
9db1d521 HP |
6970 | |
6971 | (define_insn "divmodtidi3" | |
4023fb28 UW |
6972 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
6973 | (ior:TI | |
4023fb28 UW |
6974 | (ashift:TI |
6975 | (zero_extend:TI | |
5665e398 | 6976 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6977 | (match_operand:DI 2 "general_operand" "d,T"))) |
5665e398 UW |
6978 | (const_int 64)) |
6979 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 6980 | "TARGET_ZARCH" |
9db1d521 | 6981 | "@ |
d40c829f UW |
6982 | dsgr\t%0,%2 |
6983 | dsg\t%0,%2" | |
d3632d41 | 6984 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6985 | (set_attr "type" "idiv")]) |
9db1d521 | 6986 | |
4023fb28 UW |
6987 | (define_insn "divmodtisi3" |
6988 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6989 | (ior:TI | |
4023fb28 UW |
6990 | (ashift:TI |
6991 | (zero_extend:TI | |
5665e398 | 6992 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 6993 | (sign_extend:DI |
3e4be43f | 6994 | (match_operand:SI 2 "nonimmediate_operand" "d,T")))) |
5665e398 UW |
6995 | (const_int 64)) |
6996 | (zero_extend:TI | |
6997 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 6998 | "TARGET_ZARCH" |
4023fb28 | 6999 | "@ |
d40c829f UW |
7000 | dsgfr\t%0,%2 |
7001 | dsgf\t%0,%2" | |
d3632d41 | 7002 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 7003 | (set_attr "type" "idiv")]) |
9db1d521 | 7004 | |
4023fb28 UW |
7005 | ; |
7006 | ; udivmoddi4 instruction pattern(s). | |
7007 | ; | |
9db1d521 | 7008 | |
4023fb28 UW |
7009 | (define_expand "udivmoddi4" |
7010 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
7011 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
7012 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
7013 | (set (match_operand:DI 3 "general_operand" "") | |
7014 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
7015 | (clobber (match_dup 4))] | |
9602b6a1 | 7016 | "TARGET_ZARCH" |
9db1d521 | 7017 | { |
d8485bdb TS |
7018 | rtx div_equal, mod_equal, equal; |
7019 | rtx_insn *insn; | |
4023fb28 UW |
7020 | |
7021 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
7022 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
7023 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
7024 | gen_rtx_ASHIFT (TImode, |
7025 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
7026 | GEN_INT (64)), |
7027 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
7028 | |
7029 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 7030 | emit_clobber (operands[4]); |
4023fb28 UW |
7031 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
7032 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 7033 | |
4023fb28 | 7034 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7035 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
7036 | |
7037 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 7038 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
7039 | |
7040 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 7041 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 7042 | |
9db1d521 | 7043 | DONE; |
10bbf137 | 7044 | }) |
9db1d521 HP |
7045 | |
7046 | (define_insn "udivmodtidi3" | |
4023fb28 | 7047 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 7048 | (ior:TI |
5665e398 UW |
7049 | (ashift:TI |
7050 | (zero_extend:TI | |
7051 | (truncate:DI | |
2f7e5a0d EC |
7052 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
7053 | (zero_extend:TI | |
3e4be43f | 7054 | (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
7055 | (const_int 64)) |
7056 | (zero_extend:TI | |
7057 | (truncate:DI | |
7058 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 7059 | "TARGET_ZARCH" |
9db1d521 | 7060 | "@ |
d40c829f UW |
7061 | dlgr\t%0,%2 |
7062 | dlg\t%0,%2" | |
d3632d41 | 7063 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 7064 | (set_attr "type" "idiv")]) |
9db1d521 HP |
7065 | |
7066 | ; | |
4023fb28 | 7067 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
7068 | ; |
7069 | ||
4023fb28 UW |
7070 | (define_expand "divmodsi4" |
7071 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
7072 | (div:SI (match_operand:SI 1 "general_operand" "") | |
7073 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7074 | (set (match_operand:SI 3 "general_operand" "") | |
7075 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
7076 | (clobber (match_dup 4))] | |
9602b6a1 | 7077 | "!TARGET_ZARCH" |
9db1d521 | 7078 | { |
d8485bdb TS |
7079 | rtx div_equal, mod_equal, equal; |
7080 | rtx_insn *insn; | |
4023fb28 UW |
7081 | |
7082 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
7083 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
7084 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
7085 | gen_rtx_ASHIFT (DImode, |
7086 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7087 | GEN_INT (32)), |
7088 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
7089 | |
7090 | operands[4] = gen_reg_rtx(DImode); | |
7091 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 7092 | |
4023fb28 | 7093 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7094 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
7095 | |
7096 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7097 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
7098 | |
7099 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7100 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 7101 | |
9db1d521 | 7102 | DONE; |
10bbf137 | 7103 | }) |
9db1d521 HP |
7104 | |
7105 | (define_insn "divmoddisi3" | |
4023fb28 | 7106 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 7107 | (ior:DI |
5665e398 UW |
7108 | (ashift:DI |
7109 | (zero_extend:DI | |
7110 | (truncate:SI | |
2f7e5a0d EC |
7111 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
7112 | (sign_extend:DI | |
5665e398 UW |
7113 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
7114 | (const_int 32)) | |
7115 | (zero_extend:DI | |
7116 | (truncate:SI | |
7117 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 7118 | "!TARGET_ZARCH" |
9db1d521 | 7119 | "@ |
d40c829f UW |
7120 | dr\t%0,%2 |
7121 | d\t%0,%2" | |
9db1d521 | 7122 | [(set_attr "op_type" "RR,RX") |
077dab3b | 7123 | (set_attr "type" "idiv")]) |
9db1d521 HP |
7124 | |
7125 | ; | |
7126 | ; udivsi3 and umodsi3 instruction pattern(s). | |
7127 | ; | |
7128 | ||
f1e77d83 UW |
7129 | (define_expand "udivmodsi4" |
7130 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
7131 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
7132 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7133 | (set (match_operand:SI 3 "general_operand" "") | |
7134 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
7135 | (clobber (match_dup 4))] | |
8cc6307c | 7136 | "!TARGET_ZARCH" |
f1e77d83 | 7137 | { |
d8485bdb TS |
7138 | rtx div_equal, mod_equal, equal; |
7139 | rtx_insn *insn; | |
f1e77d83 UW |
7140 | |
7141 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
7142 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
7143 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
7144 | gen_rtx_ASHIFT (DImode, |
7145 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7146 | GEN_INT (32)), |
7147 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
7148 | |
7149 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 7150 | emit_clobber (operands[4]); |
f1e77d83 UW |
7151 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
7152 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 7153 | |
f1e77d83 | 7154 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7155 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
7156 | |
7157 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7158 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
7159 | |
7160 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7161 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
7162 | |
7163 | DONE; | |
7164 | }) | |
7165 | ||
7166 | (define_insn "udivmoddisi3" | |
7167 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 7168 | (ior:DI |
5665e398 UW |
7169 | (ashift:DI |
7170 | (zero_extend:DI | |
7171 | (truncate:SI | |
2f7e5a0d EC |
7172 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
7173 | (zero_extend:DI | |
3e4be43f | 7174 | (match_operand:SI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
7175 | (const_int 32)) |
7176 | (zero_extend:DI | |
7177 | (truncate:SI | |
7178 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
8cc6307c | 7179 | "!TARGET_ZARCH" |
f1e77d83 UW |
7180 | "@ |
7181 | dlr\t%0,%2 | |
7182 | dl\t%0,%2" | |
7183 | [(set_attr "op_type" "RRE,RXY") | |
7184 | (set_attr "type" "idiv")]) | |
4023fb28 | 7185 | |
9db1d521 | 7186 | ; |
f5905b37 | 7187 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
7188 | ; |
7189 | ||
609e7e80 | 7190 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 7191 | (define_insn "div<mode>3" |
2de2b3f9 AK |
7192 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
7193 | (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
7194 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 7195 | "TARGET_HARD_FLOAT" |
9db1d521 | 7196 | "@ |
62d3f261 AK |
7197 | d<xde>tr\t%0,%1,%2 |
7198 | d<xde>br\t%0,%2 | |
6e5b5de8 | 7199 | d<xde>b\t%0,%2 |
2de2b3f9 AK |
7200 | wfddb\t%v0,%v1,%v2 |
7201 | wfdsb\t%v0,%v1,%v2" | |
7202 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 7203 | (set_attr "type" "fdiv<mode>") |
2de2b3f9 AK |
7204 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
7205 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 7206 | |
9db1d521 HP |
7207 | |
7208 | ;; | |
7209 | ;;- And instructions. | |
7210 | ;; | |
7211 | ||
047d35ed AS |
7212 | (define_expand "and<mode>3" |
7213 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7214 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7215 | (match_operand:INT 2 "general_operand" ""))) | |
7216 | (clobber (reg:CC CC_REGNUM))] | |
7217 | "" | |
7218 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
7219 | ||
9db1d521 HP |
7220 | ; |
7221 | ; anddi3 instruction pattern(s). | |
7222 | ; | |
7223 | ||
7224 | (define_insn "*anddi3_cc" | |
ae156f85 | 7225 | [(set (reg CC_REGNUM) |
e3140518 | 7226 | (compare |
3e4be43f | 7227 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7228 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
e3140518 | 7229 | (const_int 0))) |
3e4be43f | 7230 | (set (match_operand:DI 0 "register_operand" "=d,d,d, d") |
9db1d521 | 7231 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 7232 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 7233 | "@ |
d40c829f | 7234 | ngr\t%0,%2 |
65b1d8ea | 7235 | ngrk\t%0,%1,%2 |
e3140518 RH |
7236 | ng\t%0,%2 |
7237 | risbg\t%0,%1,%s2,128+%e2,0" | |
7238 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7239 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7240 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7241 | |
7242 | (define_insn "*anddi3_cconly" | |
ae156f85 | 7243 | [(set (reg CC_REGNUM) |
e3140518 | 7244 | (compare |
3e4be43f | 7245 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7246 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
9db1d521 | 7247 | (const_int 0))) |
3e4be43f | 7248 | (clobber (match_scratch:DI 0 "=d,d,d, d"))] |
e3140518 RH |
7249 | "TARGET_ZARCH |
7250 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
7251 | /* Do not steal TM patterns. */ |
7252 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 7253 | "@ |
d40c829f | 7254 | ngr\t%0,%2 |
65b1d8ea | 7255 | ngrk\t%0,%1,%2 |
e3140518 RH |
7256 | ng\t%0,%2 |
7257 | risbg\t%0,%1,%s2,128+%e2,0" | |
7258 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7259 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7260 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7261 | |
3af8e996 | 7262 | (define_insn "*anddi3" |
65b1d8ea | 7263 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7264 | "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q") |
e3140518 RH |
7265 | (and:DI |
7266 | (match_operand:DI 1 "nonimmediate_operand" | |
3e4be43f | 7267 | "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0") |
e3140518 | 7268 | (match_operand:DI 2 "general_operand" |
c2586c82 | 7269 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q"))) |
ec24698e | 7270 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7271 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7272 | "@ |
7273 | # | |
7274 | # | |
7275 | nihh\t%0,%j2 | |
7276 | nihl\t%0,%j2 | |
7277 | nilh\t%0,%j2 | |
7278 | nill\t%0,%j2 | |
7279 | nihf\t%0,%m2 | |
7280 | nilf\t%0,%m2 | |
7281 | ngr\t%0,%2 | |
65b1d8ea | 7282 | ngrk\t%0,%1,%2 |
ec24698e | 7283 | ng\t%0,%2 |
e3140518 | 7284 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
7285 | # |
7286 | #" | |
e3140518 RH |
7287 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
7288 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
7289 | (set_attr "z10prop" "*, |
7290 | *, | |
7291 | z10_super_E1, | |
7292 | z10_super_E1, | |
7293 | z10_super_E1, | |
7294 | z10_super_E1, | |
7295 | z10_super_E1, | |
7296 | z10_super_E1, | |
7297 | z10_super_E1, | |
65b1d8ea | 7298 | *, |
9381e3f1 | 7299 | z10_super_E1, |
e3140518 | 7300 | z10_super_E1, |
9381e3f1 WG |
7301 | *, |
7302 | *")]) | |
0dfa6c5e UW |
7303 | |
7304 | (define_split | |
7305 | [(set (match_operand:DI 0 "s_operand" "") | |
7306 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7307 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7308 | "reload_completed" |
7309 | [(parallel | |
7310 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7311 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7312 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7313 | |
1a2e356e | 7314 | ;; These two are what combine generates for (ashift (zero_extract)). |
64c744b9 | 7315 | (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>" |
1a2e356e RH |
7316 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7317 | (and:GPR (lshiftrt:GPR | |
7318 | (match_operand:GPR 1 "register_operand" "d") | |
7319 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7320 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7321 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7322 | /* Note that even for the SImode pattern, the rotate is always DImode. */ |
7323 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
7324 | INTVAL (operands[3]))" | |
64c744b9 | 7325 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" |
1a2e356e RH |
7326 | [(set_attr "op_type" "RIE") |
7327 | (set_attr "z10prop" "z10_super_E1")]) | |
7328 | ||
64c744b9 | 7329 | (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>" |
1a2e356e RH |
7330 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7331 | (and:GPR (ashift:GPR | |
7332 | (match_operand:GPR 1 "register_operand" "d") | |
7333 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7334 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7335 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7336 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), |
7337 | INTVAL (operands[3]))" | |
64c744b9 | 7338 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" |
1a2e356e RH |
7339 | [(set_attr "op_type" "RIE") |
7340 | (set_attr "z10prop" "z10_super_E1")]) | |
7341 | ||
9db1d521 HP |
7342 | |
7343 | ; | |
7344 | ; andsi3 instruction pattern(s). | |
7345 | ; | |
7346 | ||
7347 | (define_insn "*andsi3_cc" | |
ae156f85 | 7348 | [(set (reg CC_REGNUM) |
e3140518 RH |
7349 | (compare |
7350 | (and:SI | |
7351 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7352 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7353 | (const_int 0))) | |
7354 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
7355 | (and:SI (match_dup 1) (match_dup 2)))] |
7356 | "s390_match_ccmode(insn, CCTmode)" | |
7357 | "@ | |
ec24698e | 7358 | nilf\t%0,%o2 |
d40c829f | 7359 | nr\t%0,%2 |
65b1d8ea | 7360 | nrk\t%0,%1,%2 |
d40c829f | 7361 | n\t%0,%2 |
e3140518 RH |
7362 | ny\t%0,%2 |
7363 | risbg\t%0,%1,%t2,128+%f2,0" | |
7364 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7365 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
e3140518 RH |
7366 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7367 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7368 | |
7369 | (define_insn "*andsi3_cconly" | |
ae156f85 | 7370 | [(set (reg CC_REGNUM) |
e3140518 RH |
7371 | (compare |
7372 | (and:SI | |
7373 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7374 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7375 | (const_int 0))) | |
7376 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
7377 | "s390_match_ccmode(insn, CCTmode) |
7378 | /* Do not steal TM patterns. */ | |
7379 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 7380 | "@ |
ec24698e | 7381 | nilf\t%0,%o2 |
d40c829f | 7382 | nr\t%0,%2 |
65b1d8ea | 7383 | nrk\t%0,%1,%2 |
d40c829f | 7384 | n\t%0,%2 |
e3140518 RH |
7385 | ny\t%0,%2 |
7386 | risbg\t%0,%1,%t2,128+%f2,0" | |
7387 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7388 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
65b1d8ea | 7389 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 7390 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 7391 | |
f19a9af7 | 7392 | (define_insn "*andsi3_zarch" |
65b1d8ea | 7393 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 7394 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 7395 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 7396 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 7397 | (match_operand:SI 2 "general_operand" |
c2586c82 | 7398 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q"))) |
ae156f85 | 7399 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7400 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7401 | "@ |
f19a9af7 AK |
7402 | # |
7403 | # | |
7404 | nilh\t%0,%j2 | |
2f7e5a0d | 7405 | nill\t%0,%j2 |
ec24698e | 7406 | nilf\t%0,%o2 |
d40c829f | 7407 | nr\t%0,%2 |
65b1d8ea | 7408 | nrk\t%0,%1,%2 |
d40c829f | 7409 | n\t%0,%2 |
8cb66696 | 7410 | ny\t%0,%2 |
e3140518 | 7411 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 7412 | # |
19b63d8e | 7413 | #" |
e3140518 | 7414 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
3e4be43f | 7415 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*") |
9381e3f1 WG |
7416 | (set_attr "z10prop" "*, |
7417 | *, | |
7418 | z10_super_E1, | |
7419 | z10_super_E1, | |
7420 | z10_super_E1, | |
7421 | z10_super_E1, | |
65b1d8ea | 7422 | *, |
9381e3f1 WG |
7423 | z10_super_E1, |
7424 | z10_super_E1, | |
e3140518 | 7425 | z10_super_E1, |
9381e3f1 WG |
7426 | *, |
7427 | *")]) | |
f19a9af7 AK |
7428 | |
7429 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
7430 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
7431 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
7432 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 7433 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7434 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7435 | "@ |
7436 | nr\t%0,%2 | |
8cb66696 | 7437 | n\t%0,%2 |
0dfa6c5e | 7438 | # |
19b63d8e | 7439 | #" |
9381e3f1 WG |
7440 | [(set_attr "op_type" "RR,RX,SI,SS") |
7441 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
7442 | ||
0dfa6c5e UW |
7443 | |
7444 | (define_split | |
7445 | [(set (match_operand:SI 0 "s_operand" "") | |
7446 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7447 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7448 | "reload_completed" |
7449 | [(parallel | |
7450 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7451 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7452 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7453 | |
9db1d521 HP |
7454 | ; |
7455 | ; andhi3 instruction pattern(s). | |
7456 | ; | |
7457 | ||
8cb66696 | 7458 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
7459 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7460 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7461 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 7462 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7463 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7464 | "@ |
d40c829f | 7465 | nr\t%0,%2 |
65b1d8ea | 7466 | nrk\t%0,%1,%2 |
8cb66696 | 7467 | nill\t%0,%x2 |
0dfa6c5e | 7468 | # |
19b63d8e | 7469 | #" |
65b1d8ea AK |
7470 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7471 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7472 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 7473 | ]) |
8cb66696 UW |
7474 | |
7475 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
7476 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7477 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7478 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 7479 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7480 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7481 | "@ | |
7482 | nr\t%0,%2 | |
0dfa6c5e | 7483 | # |
19b63d8e | 7484 | #" |
9381e3f1 WG |
7485 | [(set_attr "op_type" "RR,SI,SS") |
7486 | (set_attr "z10prop" "z10_super_E1,*,*") | |
7487 | ]) | |
0dfa6c5e UW |
7488 | |
7489 | (define_split | |
7490 | [(set (match_operand:HI 0 "s_operand" "") | |
7491 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7492 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7493 | "reload_completed" |
7494 | [(parallel | |
7495 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7496 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7497 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 7498 | |
9db1d521 HP |
7499 | ; |
7500 | ; andqi3 instruction pattern(s). | |
7501 | ; | |
7502 | ||
8cb66696 | 7503 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
7504 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7505 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7506 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7507 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7508 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7509 | "@ |
d40c829f | 7510 | nr\t%0,%2 |
65b1d8ea | 7511 | nrk\t%0,%1,%2 |
8cb66696 | 7512 | nill\t%0,%b2 |
fc0ea003 UW |
7513 | ni\t%S0,%b2 |
7514 | niy\t%S0,%b2 | |
19b63d8e | 7515 | #" |
65b1d8ea | 7516 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7517 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea | 7518 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) |
8cb66696 UW |
7519 | |
7520 | (define_insn "*andqi3_esa" | |
7521 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7522 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7523 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7524 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7525 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7526 | "@ |
8cb66696 | 7527 | nr\t%0,%2 |
fc0ea003 | 7528 | ni\t%S0,%b2 |
19b63d8e | 7529 | #" |
9381e3f1 WG |
7530 | [(set_attr "op_type" "RR,SI,SS") |
7531 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 7532 | |
deb9351f DV |
7533 | ; |
7534 | ; And with complement | |
7535 | ; | |
7536 | ; c = ~b & a = (b & a) ^ a | |
7537 | ||
7538 | (define_insn_and_split "*andc_split_<mode>" | |
7539 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
7540 | (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" "")) | |
7541 | (match_operand:GPR 2 "general_operand" ""))) | |
7542 | (clobber (reg:CC CC_REGNUM))] | |
ad7ab32e DV |
7543 | "! reload_completed |
7544 | && (GET_CODE (operands[0]) != MEM | |
7545 | /* Ensure that s390_logical_operator_ok_p will succeed even | |
7546 | on the split xor if (b & a) is stored into a pseudo. */ | |
7547 | || rtx_equal_p (operands[0], operands[2]))" | |
deb9351f DV |
7548 | "#" |
7549 | "&& 1" | |
7550 | [ | |
7551 | (parallel | |
7552 | [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2))) | |
7553 | (clobber (reg:CC CC_REGNUM))]) | |
7554 | (parallel | |
7555 | [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2))) | |
7556 | (clobber (reg:CC CC_REGNUM))])] | |
7557 | { | |
7558 | if (reg_overlap_mentioned_p (operands[0], operands[2])) | |
7559 | operands[3] = gen_reg_rtx (<MODE>mode); | |
7560 | else | |
7561 | operands[3] = operands[0]; | |
7562 | }) | |
7563 | ||
19b63d8e UW |
7564 | ; |
7565 | ; Block and (NC) patterns. | |
7566 | ; | |
7567 | ||
7568 | (define_insn "*nc" | |
7569 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7570 | (and:BLK (match_dup 0) | |
7571 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7572 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7573 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7574 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7575 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7576 | [(set_attr "op_type" "SS") |
7577 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7578 | |
7579 | (define_split | |
7580 | [(set (match_operand 0 "memory_operand" "") | |
7581 | (and (match_dup 0) | |
7582 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7583 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7584 | "reload_completed |
7585 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7586 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7587 | [(parallel | |
7588 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
7589 | (use (match_dup 2)) | |
ae156f85 | 7590 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7591 | { |
7592 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7593 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7594 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7595 | }) | |
7596 | ||
7597 | (define_peephole2 | |
7598 | [(parallel | |
7599 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7600 | (and:BLK (match_dup 0) | |
7601 | (match_operand:BLK 1 "memory_operand" ""))) | |
7602 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7603 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7604 | (parallel |
7605 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7606 | (and:BLK (match_dup 3) | |
7607 | (match_operand:BLK 4 "memory_operand" ""))) | |
7608 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7609 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7610 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7611 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7612 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7613 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7614 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7615 | [(parallel | |
7616 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
7617 | (use (match_dup 8)) | |
ae156f85 | 7618 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7619 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7620 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7621 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7622 | ||
9db1d521 HP |
7623 | |
7624 | ;; | |
7625 | ;;- Bit set (inclusive or) instructions. | |
7626 | ;; | |
7627 | ||
047d35ed AS |
7628 | (define_expand "ior<mode>3" |
7629 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7630 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7631 | (match_operand:INT 2 "general_operand" ""))) | |
7632 | (clobber (reg:CC CC_REGNUM))] | |
7633 | "" | |
7634 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
7635 | ||
9db1d521 HP |
7636 | ; |
7637 | ; iordi3 instruction pattern(s). | |
7638 | ; | |
7639 | ||
4023fb28 | 7640 | (define_insn "*iordi3_cc" |
ae156f85 | 7641 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7642 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7643 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7644 | (const_int 0))) |
3e4be43f | 7645 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7646 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7647 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7648 | "@ |
d40c829f | 7649 | ogr\t%0,%2 |
65b1d8ea | 7650 | ogrk\t%0,%1,%2 |
d40c829f | 7651 | og\t%0,%2" |
65b1d8ea AK |
7652 | [(set_attr "op_type" "RRE,RRF,RXY") |
7653 | (set_attr "cpu_facility" "*,z196,*") | |
7654 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
7655 | |
7656 | (define_insn "*iordi3_cconly" | |
ae156f85 | 7657 | [(set (reg CC_REGNUM) |
65b1d8ea | 7658 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
3e4be43f | 7659 | (match_operand:DI 2 "general_operand" " d,d,T")) |
4023fb28 | 7660 | (const_int 0))) |
65b1d8ea | 7661 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7662 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7663 | "@ |
d40c829f | 7664 | ogr\t%0,%2 |
65b1d8ea | 7665 | ogrk\t%0,%1,%2 |
d40c829f | 7666 | og\t%0,%2" |
65b1d8ea AK |
7667 | [(set_attr "op_type" "RRE,RRF,RXY") |
7668 | (set_attr "cpu_facility" "*,z196,*") | |
7669 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7670 | |
3af8e996 | 7671 | (define_insn "*iordi3" |
65b1d8ea | 7672 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7673 | "=d, d, d, d, d, d,d,d,d, AQ,Q") |
65b1d8ea | 7674 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" |
3e4be43f | 7675 | " %0, 0, 0, 0, 0, 0,0,d,0, 0,0") |
ec24698e | 7676 | (match_operand:DI 2 "general_operand" |
3e4be43f | 7677 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q"))) |
ec24698e | 7678 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7679 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7680 | "@ |
7681 | oihh\t%0,%i2 | |
7682 | oihl\t%0,%i2 | |
7683 | oilh\t%0,%i2 | |
7684 | oill\t%0,%i2 | |
7685 | oihf\t%0,%k2 | |
7686 | oilf\t%0,%k2 | |
7687 | ogr\t%0,%2 | |
65b1d8ea | 7688 | ogrk\t%0,%1,%2 |
ec24698e UW |
7689 | og\t%0,%2 |
7690 | # | |
7691 | #" | |
65b1d8ea AK |
7692 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
7693 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
7694 | (set_attr "z10prop" "z10_super_E1, |
7695 | z10_super_E1, | |
7696 | z10_super_E1, | |
7697 | z10_super_E1, | |
7698 | z10_super_E1, | |
7699 | z10_super_E1, | |
7700 | z10_super_E1, | |
65b1d8ea | 7701 | *, |
9381e3f1 WG |
7702 | z10_super_E1, |
7703 | *, | |
7704 | *")]) | |
0dfa6c5e UW |
7705 | |
7706 | (define_split | |
7707 | [(set (match_operand:DI 0 "s_operand" "") | |
7708 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7709 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7710 | "reload_completed" |
7711 | [(parallel | |
7712 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7713 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7714 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7715 | |
9db1d521 HP |
7716 | ; |
7717 | ; iorsi3 instruction pattern(s). | |
7718 | ; | |
7719 | ||
4023fb28 | 7720 | (define_insn "*iorsi3_cc" |
ae156f85 | 7721 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7722 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7723 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7724 | (const_int 0))) |
65b1d8ea | 7725 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7726 | (ior:SI (match_dup 1) (match_dup 2)))] |
7727 | "s390_match_ccmode(insn, CCTmode)" | |
7728 | "@ | |
ec24698e | 7729 | oilf\t%0,%o2 |
d40c829f | 7730 | or\t%0,%2 |
65b1d8ea | 7731 | ork\t%0,%1,%2 |
d40c829f UW |
7732 | o\t%0,%2 |
7733 | oy\t%0,%2" | |
65b1d8ea | 7734 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7735 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7736 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 UW |
7737 | |
7738 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 7739 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7740 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7741 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7742 | (const_int 0))) |
65b1d8ea | 7743 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7744 | "s390_match_ccmode(insn, CCTmode)" |
7745 | "@ | |
ec24698e | 7746 | oilf\t%0,%o2 |
d40c829f | 7747 | or\t%0,%2 |
65b1d8ea | 7748 | ork\t%0,%1,%2 |
d40c829f UW |
7749 | o\t%0,%2 |
7750 | oy\t%0,%2" | |
65b1d8ea | 7751 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7752 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7753 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 | 7754 | |
8cb66696 | 7755 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
7756 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
7757 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
7758 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7759 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7760 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7761 | "@ |
f19a9af7 AK |
7762 | oilh\t%0,%i2 |
7763 | oill\t%0,%i2 | |
ec24698e | 7764 | oilf\t%0,%o2 |
d40c829f | 7765 | or\t%0,%2 |
65b1d8ea | 7766 | ork\t%0,%1,%2 |
d40c829f | 7767 | o\t%0,%2 |
8cb66696 | 7768 | oy\t%0,%2 |
0dfa6c5e | 7769 | # |
19b63d8e | 7770 | #" |
65b1d8ea | 7771 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 7772 | (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*") |
9381e3f1 WG |
7773 | (set_attr "z10prop" "z10_super_E1, |
7774 | z10_super_E1, | |
7775 | z10_super_E1, | |
7776 | z10_super_E1, | |
65b1d8ea | 7777 | *, |
9381e3f1 WG |
7778 | z10_super_E1, |
7779 | z10_super_E1, | |
7780 | *, | |
7781 | *")]) | |
8cb66696 UW |
7782 | |
7783 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 7784 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 7785 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 7786 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 7787 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7788 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7789 | "@ |
7790 | or\t%0,%2 | |
8cb66696 | 7791 | o\t%0,%2 |
0dfa6c5e | 7792 | # |
19b63d8e | 7793 | #" |
9381e3f1 WG |
7794 | [(set_attr "op_type" "RR,RX,SI,SS") |
7795 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7796 | |
7797 | (define_split | |
7798 | [(set (match_operand:SI 0 "s_operand" "") | |
7799 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7800 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7801 | "reload_completed" |
7802 | [(parallel | |
7803 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7804 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7805 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7806 | |
4023fb28 UW |
7807 | ; |
7808 | ; iorhi3 instruction pattern(s). | |
7809 | ; | |
7810 | ||
8cb66696 | 7811 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
7812 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7813 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7814 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 7815 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7816 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7817 | "@ |
d40c829f | 7818 | or\t%0,%2 |
65b1d8ea | 7819 | ork\t%0,%1,%2 |
8cb66696 | 7820 | oill\t%0,%x2 |
0dfa6c5e | 7821 | # |
19b63d8e | 7822 | #" |
65b1d8ea AK |
7823 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7824 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7825 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
7826 | |
7827 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
7828 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7829 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7830 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 7831 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7832 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7833 | "@ | |
7834 | or\t%0,%2 | |
0dfa6c5e | 7835 | # |
19b63d8e | 7836 | #" |
9381e3f1 WG |
7837 | [(set_attr "op_type" "RR,SI,SS") |
7838 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7839 | |
7840 | (define_split | |
7841 | [(set (match_operand:HI 0 "s_operand" "") | |
7842 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7843 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7844 | "reload_completed" |
7845 | [(parallel | |
7846 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7847 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7848 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 7849 | |
9db1d521 | 7850 | ; |
4023fb28 | 7851 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
7852 | ; |
7853 | ||
8cb66696 | 7854 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
7855 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7856 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7857 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7858 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7859 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7860 | "@ |
d40c829f | 7861 | or\t%0,%2 |
65b1d8ea | 7862 | ork\t%0,%1,%2 |
8cb66696 | 7863 | oill\t%0,%b2 |
fc0ea003 UW |
7864 | oi\t%S0,%b2 |
7865 | oiy\t%S0,%b2 | |
19b63d8e | 7866 | #" |
65b1d8ea | 7867 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7868 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea AK |
7869 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, |
7870 | z10_super,z10_super,*")]) | |
8cb66696 UW |
7871 | |
7872 | (define_insn "*iorqi3_esa" | |
7873 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7874 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7875 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7876 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7877 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7878 | "@ |
8cb66696 | 7879 | or\t%0,%2 |
fc0ea003 | 7880 | oi\t%S0,%b2 |
19b63d8e | 7881 | #" |
9381e3f1 WG |
7882 | [(set_attr "op_type" "RR,SI,SS") |
7883 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 7884 | |
19b63d8e UW |
7885 | ; |
7886 | ; Block inclusive or (OC) patterns. | |
7887 | ; | |
7888 | ||
7889 | (define_insn "*oc" | |
7890 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7891 | (ior:BLK (match_dup 0) | |
7892 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7893 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7894 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7895 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7896 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7897 | [(set_attr "op_type" "SS") |
7898 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7899 | |
7900 | (define_split | |
7901 | [(set (match_operand 0 "memory_operand" "") | |
7902 | (ior (match_dup 0) | |
7903 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7904 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7905 | "reload_completed |
7906 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7907 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7908 | [(parallel | |
7909 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
7910 | (use (match_dup 2)) | |
ae156f85 | 7911 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7912 | { |
7913 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7914 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7915 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7916 | }) | |
7917 | ||
7918 | (define_peephole2 | |
7919 | [(parallel | |
7920 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7921 | (ior:BLK (match_dup 0) | |
7922 | (match_operand:BLK 1 "memory_operand" ""))) | |
7923 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7924 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7925 | (parallel |
7926 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7927 | (ior:BLK (match_dup 3) | |
7928 | (match_operand:BLK 4 "memory_operand" ""))) | |
7929 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7930 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7931 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7932 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7933 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7934 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7935 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7936 | [(parallel | |
7937 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
7938 | (use (match_dup 8)) | |
ae156f85 | 7939 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7940 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7941 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7942 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7943 | ||
9db1d521 HP |
7944 | |
7945 | ;; | |
7946 | ;;- Xor instructions. | |
7947 | ;; | |
7948 | ||
047d35ed AS |
7949 | (define_expand "xor<mode>3" |
7950 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7951 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7952 | (match_operand:INT 2 "general_operand" ""))) | |
7953 | (clobber (reg:CC CC_REGNUM))] | |
7954 | "" | |
7955 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
7956 | ||
3c91f126 AK |
7957 | ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing |
7958 | ; simplifications. So its better to have something matching. | |
7959 | (define_split | |
7960 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7961 | (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] | |
7962 | "" | |
7963 | [(parallel | |
7964 | [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) | |
7965 | (clobber (reg:CC CC_REGNUM))])] | |
7966 | { | |
7967 | operands[2] = constm1_rtx; | |
7968 | if (!s390_logical_operator_ok_p (operands)) | |
7969 | FAIL; | |
7970 | }) | |
7971 | ||
9db1d521 HP |
7972 | ; |
7973 | ; xordi3 instruction pattern(s). | |
7974 | ; | |
7975 | ||
4023fb28 | 7976 | (define_insn "*xordi3_cc" |
ae156f85 | 7977 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7978 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7979 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7980 | (const_int 0))) |
3e4be43f | 7981 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7982 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7983 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7984 | "@ |
d40c829f | 7985 | xgr\t%0,%2 |
65b1d8ea | 7986 | xgrk\t%0,%1,%2 |
d40c829f | 7987 | xg\t%0,%2" |
65b1d8ea | 7988 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 7989 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 7990 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
7991 | |
7992 | (define_insn "*xordi3_cconly" | |
ae156f85 | 7993 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7994 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7995 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7996 | (const_int 0))) |
3e4be43f | 7997 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7998 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7999 | "@ |
d40c829f | 8000 | xgr\t%0,%2 |
65b1d8ea | 8001 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 8002 | xg\t%0,%2" |
65b1d8ea AK |
8003 | [(set_attr "op_type" "RRE,RRF,RXY") |
8004 | (set_attr "cpu_facility" "*,z196,*") | |
8005 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 8006 | |
3af8e996 | 8007 | (define_insn "*xordi3" |
3e4be43f UW |
8008 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q") |
8009 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0") | |
8010 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q"))) | |
ec24698e | 8011 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8012 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
8013 | "@ |
8014 | xihf\t%0,%k2 | |
8015 | xilf\t%0,%k2 | |
8016 | xgr\t%0,%2 | |
65b1d8ea | 8017 | xgrk\t%0,%1,%2 |
ec24698e UW |
8018 | xg\t%0,%2 |
8019 | # | |
8020 | #" | |
65b1d8ea AK |
8021 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
8022 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
8023 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
8024 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8025 | |
8026 | (define_split | |
8027 | [(set (match_operand:DI 0 "s_operand" "") | |
8028 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 8029 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8030 | "reload_completed" |
8031 | [(parallel | |
8032 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8033 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8034 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 8035 | |
9db1d521 HP |
8036 | ; |
8037 | ; xorsi3 instruction pattern(s). | |
8038 | ; | |
8039 | ||
4023fb28 | 8040 | (define_insn "*xorsi3_cc" |
ae156f85 | 8041 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8042 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8043 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8044 | (const_int 0))) |
65b1d8ea | 8045 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
8046 | (xor:SI (match_dup 1) (match_dup 2)))] |
8047 | "s390_match_ccmode(insn, CCTmode)" | |
8048 | "@ | |
ec24698e | 8049 | xilf\t%0,%o2 |
d40c829f | 8050 | xr\t%0,%2 |
65b1d8ea | 8051 | xrk\t%0,%1,%2 |
d40c829f UW |
8052 | x\t%0,%2 |
8053 | xy\t%0,%2" | |
65b1d8ea | 8054 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8055 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8056 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8057 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
8058 | |
8059 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 8060 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8061 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8062 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8063 | (const_int 0))) |
65b1d8ea | 8064 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
8065 | "s390_match_ccmode(insn, CCTmode)" |
8066 | "@ | |
ec24698e | 8067 | xilf\t%0,%o2 |
d40c829f | 8068 | xr\t%0,%2 |
65b1d8ea | 8069 | xrk\t%0,%1,%2 |
d40c829f UW |
8070 | x\t%0,%2 |
8071 | xy\t%0,%2" | |
65b1d8ea | 8072 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8073 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8074 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8075 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 8076 | |
8cb66696 | 8077 | (define_insn "*xorsi3" |
65b1d8ea AK |
8078 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
8079 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
8080 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 8081 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8082 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8083 | "@ |
ec24698e | 8084 | xilf\t%0,%o2 |
d40c829f | 8085 | xr\t%0,%2 |
65b1d8ea | 8086 | xrk\t%0,%1,%2 |
d40c829f | 8087 | x\t%0,%2 |
8cb66696 | 8088 | xy\t%0,%2 |
0dfa6c5e | 8089 | # |
19b63d8e | 8090 | #" |
65b1d8ea | 8091 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 8092 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*") |
65b1d8ea AK |
8093 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8094 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8095 | |
8096 | (define_split | |
8097 | [(set (match_operand:SI 0 "s_operand" "") | |
8098 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 8099 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8100 | "reload_completed" |
8101 | [(parallel | |
8102 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8103 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8104 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 8105 | |
9db1d521 HP |
8106 | ; |
8107 | ; xorhi3 instruction pattern(s). | |
8108 | ; | |
8109 | ||
8cb66696 | 8110 | (define_insn "*xorhi3" |
65b1d8ea AK |
8111 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
8112 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
8113 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 8114 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
8115 | "s390_logical_operator_ok_p (operands)" |
8116 | "@ | |
ec24698e | 8117 | xilf\t%0,%x2 |
8cb66696 | 8118 | xr\t%0,%2 |
65b1d8ea | 8119 | xrk\t%0,%1,%2 |
0dfa6c5e | 8120 | # |
19b63d8e | 8121 | #" |
65b1d8ea AK |
8122 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
8123 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
8124 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
8125 | |
8126 | (define_split | |
8127 | [(set (match_operand:HI 0 "s_operand" "") | |
8128 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 8129 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8130 | "reload_completed" |
8131 | [(parallel | |
8132 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8133 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8134 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 8135 | |
9db1d521 HP |
8136 | ; |
8137 | ; xorqi3 instruction pattern(s). | |
8138 | ; | |
8139 | ||
8cb66696 | 8140 | (define_insn "*xorqi3" |
65b1d8ea AK |
8141 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
8142 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
8143 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 8144 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8145 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8146 | "@ |
ec24698e | 8147 | xilf\t%0,%b2 |
8cb66696 | 8148 | xr\t%0,%2 |
65b1d8ea | 8149 | xrk\t%0,%1,%2 |
fc0ea003 UW |
8150 | xi\t%S0,%b2 |
8151 | xiy\t%S0,%b2 | |
19b63d8e | 8152 | #" |
65b1d8ea | 8153 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
3e4be43f | 8154 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*") |
65b1d8ea | 8155 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) |
9381e3f1 | 8156 | |
4023fb28 | 8157 | |
19b63d8e UW |
8158 | ; |
8159 | ; Block exclusive or (XC) patterns. | |
8160 | ; | |
8161 | ||
8162 | (define_insn "*xc" | |
8163 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8164 | (xor:BLK (match_dup 0) | |
8165 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
8166 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 8167 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8168 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 8169 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 8170 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
8171 | |
8172 | (define_split | |
8173 | [(set (match_operand 0 "memory_operand" "") | |
8174 | (xor (match_dup 0) | |
8175 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 8176 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
8177 | "reload_completed |
8178 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
8179 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
8180 | [(parallel | |
8181 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
8182 | (use (match_dup 2)) | |
ae156f85 | 8183 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8184 | { |
8185 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
8186 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
8187 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
8188 | }) | |
8189 | ||
8190 | (define_peephole2 | |
8191 | [(parallel | |
8192 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8193 | (xor:BLK (match_dup 0) | |
8194 | (match_operand:BLK 1 "memory_operand" ""))) | |
8195 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 8196 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8197 | (parallel |
8198 | [(set (match_operand:BLK 3 "memory_operand" "") | |
8199 | (xor:BLK (match_dup 3) | |
8200 | (match_operand:BLK 4 "memory_operand" ""))) | |
8201 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 8202 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8203 | "s390_offset_p (operands[0], operands[3], operands[2]) |
8204 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 8205 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 8206 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
8207 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
8208 | [(parallel | |
8209 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
8210 | (use (match_dup 8)) | |
ae156f85 | 8211 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8212 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8213 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
8214 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
8215 | ||
8216 | ; | |
8217 | ; Block xor (XC) patterns with src == dest. | |
8218 | ; | |
8219 | ||
8220 | (define_insn "*xc_zero" | |
8221 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8222 | (const_int 0)) | |
8223 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 8224 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8225 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 8226 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
8227 | [(set_attr "op_type" "SS") |
8228 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
8229 | |
8230 | (define_peephole2 | |
8231 | [(parallel | |
8232 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8233 | (const_int 0)) | |
8234 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 8235 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8236 | (parallel |
8237 | [(set (match_operand:BLK 2 "memory_operand" "") | |
8238 | (const_int 0)) | |
8239 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 8240 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8241 | "s390_offset_p (operands[0], operands[2], operands[1]) |
8242 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
8243 | [(parallel | |
8244 | [(set (match_dup 4) (const_int 0)) | |
8245 | (use (match_dup 5)) | |
ae156f85 | 8246 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8247 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8248 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
8249 | ||
9db1d521 HP |
8250 | |
8251 | ;; | |
8252 | ;;- Negate instructions. | |
8253 | ;; | |
8254 | ||
8255 | ; | |
9a91a21f | 8256 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
8257 | ; |
8258 | ||
9a91a21f | 8259 | (define_expand "neg<mode>2" |
9db1d521 | 8260 | [(parallel |
9a91a21f AS |
8261 | [(set (match_operand:DSI 0 "register_operand" "=d") |
8262 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 8263 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8264 | "" |
8265 | "") | |
8266 | ||
26a89301 | 8267 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 8268 | [(set (reg CC_REGNUM) |
26a89301 UW |
8269 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8270 | (match_operand:SI 1 "register_operand" "d") 0) | |
8271 | (const_int 32)) (const_int 32))) | |
8272 | (const_int 0))) | |
8273 | (set (match_operand:DI 0 "register_operand" "=d") | |
8274 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8275 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8276 | "lcgfr\t%0,%1" |
729e750f WG |
8277 | [(set_attr "op_type" "RRE") |
8278 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8279 | |
26a89301 UW |
8280 | (define_insn "*negdi2_sign" |
8281 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8282 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8283 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8284 | "TARGET_ZARCH" |
26a89301 | 8285 | "lcgfr\t%0,%1" |
729e750f WG |
8286 | [(set_attr "op_type" "RRE") |
8287 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8288 | |
43a09b63 | 8289 | ; lcr, lcgr |
9a91a21f | 8290 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8291 | [(set (reg CC_REGNUM) |
9a91a21f | 8292 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8293 | (const_int 0))) |
9a91a21f AS |
8294 | (set (match_operand:GPR 0 "register_operand" "=d") |
8295 | (neg:GPR (match_dup 1)))] | |
8296 | "s390_match_ccmode (insn, CCAmode)" | |
8297 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8298 | [(set_attr "op_type" "RR<E>") |
8299 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8300 | |
8301 | ; lcr, lcgr | |
9a91a21f | 8302 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8303 | [(set (reg CC_REGNUM) |
9a91a21f | 8304 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8305 | (const_int 0))) |
9a91a21f AS |
8306 | (clobber (match_scratch:GPR 0 "=d"))] |
8307 | "s390_match_ccmode (insn, CCAmode)" | |
8308 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8309 | [(set_attr "op_type" "RR<E>") |
8310 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8311 | |
8312 | ; lcr, lcgr | |
9a91a21f AS |
8313 | (define_insn "*neg<mode>2" |
8314 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8315 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8316 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
8317 | "" |
8318 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8319 | [(set_attr "op_type" "RR<E>") |
8320 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 8321 | |
b7d19263 | 8322 | (define_insn "*negdi2_31" |
9db1d521 HP |
8323 | [(set (match_operand:DI 0 "register_operand" "=d") |
8324 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 8325 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8326 | "!TARGET_ZARCH" |
b7d19263 AK |
8327 | "#") |
8328 | ||
8329 | ; Split a DImode NEG on 31bit into 2 SImode NEGs | |
8330 | ||
8331 | ; Doing the twos complement separately on the SImode parts does an | |
8332 | ; unwanted +1 on the high part which needs to be subtracted afterwards | |
8333 | ; ... unless the +1 on the low part created an overflow. | |
8334 | ||
8335 | (define_split | |
8336 | [(set (match_operand:DI 0 "register_operand" "") | |
8337 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8338 | (clobber (reg:CC CC_REGNUM))] | |
8339 | "!TARGET_ZARCH | |
8340 | && (REGNO (operands[0]) == REGNO (operands[1]) | |
8341 | || s390_split_ok_p (operands[0], operands[1], DImode, 0)) | |
8342 | && reload_completed" | |
26a89301 UW |
8343 | [(parallel |
8344 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 8345 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 8346 | (parallel |
ae156f85 | 8347 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
8348 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
8349 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
8350 | (set (pc) | |
ae156f85 | 8351 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
8352 | (pc) |
8353 | (label_ref (match_dup 6)))) | |
8354 | (parallel | |
8355 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 8356 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
8357 | (match_dup 6)] |
8358 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8359 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8360 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8361 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8362 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 8363 | |
b7d19263 AK |
8364 | ; Like above but first make a copy of the low part of the src operand |
8365 | ; since it might overlap with the high part of the destination. | |
8366 | ||
8367 | (define_split | |
8368 | [(set (match_operand:DI 0 "register_operand" "") | |
8369 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8370 | (clobber (reg:CC CC_REGNUM))] | |
8371 | "!TARGET_ZARCH | |
8372 | && s390_split_ok_p (operands[0], operands[1], DImode, 1) | |
8373 | && reload_completed" | |
8374 | [; Make a backup of op5 first | |
8375 | (set (match_dup 4) (match_dup 5)) | |
8376 | ; Setting op2 here might clobber op5 | |
8377 | (parallel | |
8378 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
8379 | (clobber (reg:CC CC_REGNUM))]) | |
8380 | (parallel | |
8381 | [(set (reg:CCAP CC_REGNUM) | |
8382 | (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) | |
8383 | (set (match_dup 4) (neg:SI (match_dup 4)))]) | |
8384 | (set (pc) | |
8385 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
8386 | (pc) | |
8387 | (label_ref (match_dup 6)))) | |
8388 | (parallel | |
8389 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
8390 | (clobber (reg:CC CC_REGNUM))]) | |
8391 | (match_dup 6)] | |
8392 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8393 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8394 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8395 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8396 | operands[6] = gen_label_rtx ();") | |
8397 | ||
9db1d521 | 8398 | ; |
f5905b37 | 8399 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8400 | ; |
8401 | ||
f5905b37 | 8402 | (define_expand "neg<mode>2" |
9db1d521 | 8403 | [(parallel |
2de2b3f9 AK |
8404 | [(set (match_operand:BFP 0 "register_operand") |
8405 | (neg:BFP (match_operand:BFP 1 "register_operand"))) | |
ae156f85 | 8406 | (clobber (reg:CC CC_REGNUM))])] |
2de2b3f9 | 8407 | "TARGET_HARD_FLOAT") |
9db1d521 | 8408 | |
43a09b63 | 8409 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 8410 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8411 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8412 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8413 | (match_operand:BFP 2 "const0_operand" ""))) | |
8414 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8415 | (neg:BFP (match_dup 1)))] | |
142cd70f | 8416 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8417 | "lc<xde>br\t%0,%1" |
26a89301 | 8418 | [(set_attr "op_type" "RRE") |
f5905b37 | 8419 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8420 | |
8421 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 8422 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8423 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8424 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8425 | (match_operand:BFP 2 "const0_operand" ""))) | |
8426 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8427 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8428 | "lc<xde>br\t%0,%1" |
26a89301 | 8429 | [(set_attr "op_type" "RRE") |
f5905b37 | 8430 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8431 | |
85dae55a AK |
8432 | ; lcdfr |
8433 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
8434 | [(set (match_operand:FP 0 "register_operand" "=f") |
8435 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8436 | "TARGET_DFP" |
85dae55a AK |
8437 | "lcdfr\t%0,%1" |
8438 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8439 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8440 | |
43a09b63 | 8441 | ; lcxbr, lcdbr, lcebr |
6e5b5de8 | 8442 | ; FIXME: wflcdb does not clobber cc |
2de2b3f9 | 8443 | ; FIXME: Does wflcdb ever match here? |
f5905b37 | 8444 | (define_insn "*neg<mode>2" |
2de2b3f9 AK |
8445 | [(set (match_operand:BFP 0 "register_operand" "=f,v,v") |
8446 | (neg:BFP (match_operand:BFP 1 "register_operand" "f,v,v"))) | |
ae156f85 | 8447 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8448 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8449 | "@ |
8450 | lc<xde>br\t%0,%1 | |
2de2b3f9 AK |
8451 | wflcdb\t%0,%1 |
8452 | wflcsb\t%0,%1" | |
8453 | [(set_attr "op_type" "RRE,VRR,VRR") | |
8454 | (set_attr "cpu_facility" "*,vx,vxe") | |
8455 | (set_attr "type" "fsimp<mode>,*,*") | |
8456 | (set_attr "enabled" "*,<DF>,<SF>")]) | |
9db1d521 | 8457 | |
9db1d521 HP |
8458 | |
8459 | ;; | |
8460 | ;;- Absolute value instructions. | |
8461 | ;; | |
8462 | ||
8463 | ; | |
9a91a21f | 8464 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
8465 | ; |
8466 | ||
26a89301 | 8467 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 8468 | [(set (reg CC_REGNUM) |
26a89301 UW |
8469 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8470 | (match_operand:SI 1 "register_operand" "d") 0) | |
8471 | (const_int 32)) (const_int 32))) | |
8472 | (const_int 0))) | |
8473 | (set (match_operand:DI 0 "register_operand" "=d") | |
8474 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8475 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8476 | "lpgfr\t%0,%1" |
729e750f WG |
8477 | [(set_attr "op_type" "RRE") |
8478 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
8479 | |
8480 | (define_insn "*absdi2_sign" | |
8481 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8482 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8483 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8484 | "TARGET_ZARCH" |
26a89301 | 8485 | "lpgfr\t%0,%1" |
729e750f WG |
8486 | [(set_attr "op_type" "RRE") |
8487 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8488 | |
43a09b63 | 8489 | ; lpr, lpgr |
9a91a21f | 8490 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8491 | [(set (reg CC_REGNUM) |
9a91a21f | 8492 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 8493 | (const_int 0))) |
9a91a21f AS |
8494 | (set (match_operand:GPR 0 "register_operand" "=d") |
8495 | (abs:GPR (match_dup 1)))] | |
26a89301 | 8496 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8497 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8498 | [(set_attr "op_type" "RR<E>") |
8499 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 8500 | |
9381e3f1 | 8501 | ; lpr, lpgr |
9a91a21f | 8502 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8503 | [(set (reg CC_REGNUM) |
9a91a21f | 8504 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8505 | (const_int 0))) |
9a91a21f | 8506 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8507 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8508 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8509 | [(set_attr "op_type" "RR<E>") |
8510 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8511 | |
8512 | ; lpr, lpgr | |
9a91a21f AS |
8513 | (define_insn "abs<mode>2" |
8514 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8515 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8516 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 8517 | "" |
9a91a21f | 8518 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8519 | [(set_attr "op_type" "RR<E>") |
8520 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 8521 | |
9db1d521 | 8522 | ; |
f5905b37 | 8523 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8524 | ; |
8525 | ||
f5905b37 | 8526 | (define_expand "abs<mode>2" |
9db1d521 | 8527 | [(parallel |
7b6baae1 AK |
8528 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8529 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8530 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8531 | "TARGET_HARD_FLOAT" |
8532 | "") | |
8533 | ||
43a09b63 | 8534 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 8535 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8536 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8537 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8538 | (match_operand:BFP 2 "const0_operand" ""))) | |
8539 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8540 | (abs:BFP (match_dup 1)))] | |
142cd70f | 8541 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8542 | "lp<xde>br\t%0,%1" |
26a89301 | 8543 | [(set_attr "op_type" "RRE") |
f5905b37 | 8544 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8545 | |
8546 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 8547 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8548 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8549 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8550 | (match_operand:BFP 2 "const0_operand" ""))) | |
8551 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8552 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8553 | "lp<xde>br\t%0,%1" |
26a89301 | 8554 | [(set_attr "op_type" "RRE") |
f5905b37 | 8555 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8556 | |
85dae55a AK |
8557 | ; lpdfr |
8558 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
8559 | [(set (match_operand:FP 0 "register_operand" "=f") |
8560 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8561 | "TARGET_DFP" |
85dae55a AK |
8562 | "lpdfr\t%0,%1" |
8563 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8564 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8565 | |
43a09b63 | 8566 | ; lpxbr, lpdbr, lpebr |
6e5b5de8 | 8567 | ; FIXME: wflpdb does not clobber cc |
f5905b37 | 8568 | (define_insn "*abs<mode>2" |
62d3f261 AK |
8569 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8570 | (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8571 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8572 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8573 | "@ |
8574 | lp<xde>br\t%0,%1 | |
8575 | wflpdb\t%0,%1" | |
8576 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8577 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8578 | (set_attr "type" "fsimp<mode>,*") |
8579 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8580 | |
9db1d521 | 8581 | |
3ef093a8 AK |
8582 | ;; |
8583 | ;;- Negated absolute value instructions | |
8584 | ;; | |
8585 | ||
8586 | ; | |
8587 | ; Integer | |
8588 | ; | |
8589 | ||
26a89301 | 8590 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 8591 | [(set (reg CC_REGNUM) |
26a89301 UW |
8592 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8593 | (match_operand:SI 1 "register_operand" "d") 0) | |
8594 | (const_int 32)) (const_int 32)))) | |
8595 | (const_int 0))) | |
8596 | (set (match_operand:DI 0 "register_operand" "=d") | |
8597 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 8598 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8599 | "lngfr\t%0,%1" |
729e750f WG |
8600 | [(set_attr "op_type" "RRE") |
8601 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8602 | |
26a89301 UW |
8603 | (define_insn "*negabsdi2_sign" |
8604 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8605 | (neg:DI (abs:DI (sign_extend:DI | |
8606 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 8607 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8608 | "TARGET_ZARCH" |
26a89301 | 8609 | "lngfr\t%0,%1" |
729e750f WG |
8610 | [(set_attr "op_type" "RRE") |
8611 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 8612 | |
43a09b63 | 8613 | ; lnr, lngr |
9a91a21f | 8614 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8615 | [(set (reg CC_REGNUM) |
9a91a21f | 8616 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8617 | (const_int 0))) |
9a91a21f AS |
8618 | (set (match_operand:GPR 0 "register_operand" "=d") |
8619 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 8620 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8621 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8622 | [(set_attr "op_type" "RR<E>") |
8623 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8624 | |
8625 | ; lnr, lngr | |
9a91a21f | 8626 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8627 | [(set (reg CC_REGNUM) |
9a91a21f | 8628 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8629 | (const_int 0))) |
9a91a21f | 8630 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8631 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8632 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8633 | [(set_attr "op_type" "RR<E>") |
8634 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8635 | |
8636 | ; lnr, lngr | |
9a91a21f AS |
8637 | (define_insn "*negabs<mode>2" |
8638 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8639 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 8640 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 8641 | "" |
9a91a21f | 8642 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8643 | [(set_attr "op_type" "RR<E>") |
8644 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8645 | |
3ef093a8 AK |
8646 | ; |
8647 | ; Floating point | |
8648 | ; | |
8649 | ||
43a09b63 | 8650 | ; lnxbr, lndbr, lnebr |
f5905b37 | 8651 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8652 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8653 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8654 | (match_operand:BFP 2 "const0_operand" ""))) | |
8655 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8656 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 8657 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8658 | "ln<xde>br\t%0,%1" |
26a89301 | 8659 | [(set_attr "op_type" "RRE") |
f5905b37 | 8660 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8661 | |
8662 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 8663 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8664 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8665 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8666 | (match_operand:BFP 2 "const0_operand" ""))) | |
8667 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8668 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8669 | "ln<xde>br\t%0,%1" |
26a89301 | 8670 | [(set_attr "op_type" "RRE") |
f5905b37 | 8671 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8672 | |
85dae55a AK |
8673 | ; lndfr |
8674 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
8675 | [(set (match_operand:FP 0 "register_operand" "=f") |
8676 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 8677 | "TARGET_DFP" |
85dae55a AK |
8678 | "lndfr\t%0,%1" |
8679 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8680 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8681 | |
43a09b63 | 8682 | ; lnxbr, lndbr, lnebr |
6e5b5de8 | 8683 | ; FIXME: wflndb does not clobber cc |
f5905b37 | 8684 | (define_insn "*negabs<mode>2" |
62d3f261 AK |
8685 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8686 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) | |
ae156f85 | 8687 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8688 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8689 | "@ |
8690 | ln<xde>br\t%0,%1 | |
8691 | wflndb\t%0,%1" | |
8692 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8693 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8694 | (set_attr "type" "fsimp<mode>,*") |
8695 | (set_attr "enabled" "*,<DFDI>")]) | |
26a89301 | 8696 | |
4023fb28 UW |
8697 | ;; |
8698 | ;;- Square root instructions. | |
8699 | ;; | |
8700 | ||
8701 | ; | |
f5905b37 | 8702 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
8703 | ; |
8704 | ||
9381e3f1 | 8705 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 8706 | (define_insn "sqrt<mode>2" |
62d3f261 AK |
8707 | [(set (match_operand:BFP 0 "register_operand" "=f,f,v") |
8708 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] | |
142cd70f | 8709 | "TARGET_HARD_FLOAT" |
4023fb28 | 8710 | "@ |
f61a2c7d | 8711 | sq<xde>br\t%0,%1 |
6e5b5de8 AK |
8712 | sq<xde>b\t%0,%1 |
8713 | wfsqdb\t%v0,%v1" | |
8714 | [(set_attr "op_type" "RRE,RXE,VRR") | |
8715 | (set_attr "type" "fsqrt<mode>") | |
285363a1 | 8716 | (set_attr "cpu_facility" "*,*,vx") |
62d3f261 | 8717 | (set_attr "enabled" "*,<DSF>,<DFDI>")]) |
4023fb28 | 8718 | |
9db1d521 HP |
8719 | |
8720 | ;; | |
8721 | ;;- One complement instructions. | |
8722 | ;; | |
8723 | ||
8724 | ; | |
342cf42b | 8725 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 8726 | ; |
c7453384 | 8727 | |
342cf42b | 8728 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 8729 | [(parallel |
342cf42b AS |
8730 | [(set (match_operand:INT 0 "register_operand" "") |
8731 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
8732 | (const_int -1))) | |
ae156f85 | 8733 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 8734 | "" |
4023fb28 | 8735 | "") |
9db1d521 HP |
8736 | |
8737 | ||
ec24698e UW |
8738 | ;; |
8739 | ;; Find leftmost bit instructions. | |
8740 | ;; | |
8741 | ||
8742 | (define_expand "clzdi2" | |
8743 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8744 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 8745 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e | 8746 | { |
d8485bdb TS |
8747 | rtx_insn *insn; |
8748 | rtx clz_equal; | |
ec24698e | 8749 | rtx wide_reg = gen_reg_rtx (TImode); |
406fde6e | 8750 | rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63); |
ec24698e UW |
8751 | |
8752 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
8753 | ||
8754 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
8755 | ||
9381e3f1 | 8756 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 8757 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
8758 | |
8759 | DONE; | |
8760 | }) | |
8761 | ||
33f3393a AK |
8762 | ; CLZ result is in hard reg op0 - this is the high part of the target operand |
8763 | ; The source with the left-most one bit cleared is in hard reg op0 + 1 - the low part | |
ec24698e UW |
8764 | (define_insn "clztidi2" |
8765 | [(set (match_operand:TI 0 "register_operand" "=d") | |
8766 | (ior:TI | |
33f3393a AK |
8767 | (ashift:TI (zero_extend:TI (clz:DI (match_operand:DI 1 "register_operand" "d"))) |
8768 | (const_int 64)) | |
8769 | (zero_extend:TI | |
8770 | (xor:DI (match_dup 1) | |
8771 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
8772 | (subreg:SI (clz:DI (match_dup 1)) 4)))))) | |
ec24698e | 8773 | (clobber (reg:CC CC_REGNUM))] |
406fde6e | 8774 | "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63 |
9602b6a1 | 8775 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8776 | "flogr\t%0,%1" |
8777 | [(set_attr "op_type" "RRE")]) | |
8778 | ||
8779 | ||
9db1d521 HP |
8780 | ;; |
8781 | ;;- Rotate instructions. | |
8782 | ;; | |
8783 | ||
8784 | ; | |
9a91a21f | 8785 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
8786 | ; |
8787 | ||
191eb16d AK |
8788 | (define_expand "rotl<mode>3" |
8789 | [(set (match_operand:GPR 0 "register_operand" "") | |
8790 | (rotate:GPR (match_operand:GPR 1 "register_operand" "") | |
8791 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
8cc6307c | 8792 | "" |
191eb16d | 8793 | "") |
9db1d521 | 8794 | |
43a09b63 | 8795 | ; rll, rllg |
191eb16d AK |
8796 | (define_insn "*rotl<mode>3<addr_style_op><masked_op>" |
8797 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8798 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
8799 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
8cc6307c | 8800 | "" |
191eb16d | 8801 | "rll<g>\t%0,%1,<addr_style_op_ops>" |
4989e88a | 8802 | [(set_attr "op_type" "RSE") |
9381e3f1 | 8803 | (set_attr "atype" "reg") |
191eb16d | 8804 | (set_attr "z10prop" "z10_super_E1")]) |
4989e88a | 8805 | |
9db1d521 HP |
8806 | |
8807 | ;; | |
f337b930 | 8808 | ;;- Shift instructions. |
9db1d521 | 8809 | ;; |
9db1d521 HP |
8810 | |
8811 | ; | |
1b48c8cc | 8812 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 8813 | ; Left shifts and logical right shifts |
9db1d521 | 8814 | |
1b48c8cc AS |
8815 | (define_expand "<shift><mode>3" |
8816 | [(set (match_operand:DSI 0 "register_operand" "") | |
8817 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
adf22b3f | 8818 | (match_operand:SI 2 "nonmemory_operand" "")))] |
9db1d521 HP |
8819 | "" |
8820 | "") | |
8821 | ||
adf22b3f | 8822 | ; ESA 64 bit register pair shift with reg or imm shift count |
43a09b63 | 8823 | ; sldl, srdl |
adf22b3f AK |
8824 | (define_insn "*<shift>di3_31<addr_style_op><masked_op>" |
8825 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8826 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
8827 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
9602b6a1 | 8828 | "!TARGET_ZARCH" |
adf22b3f | 8829 | "s<lr>dl\t%0,<addr_style_op_ops>" |
077dab3b | 8830 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
8831 | (set_attr "atype" "reg") |
8832 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8833 | |
adf22b3f AK |
8834 | |
8835 | ; 64 bit register shift with reg or imm shift count | |
65b1d8ea | 8836 | ; sll, srl, sllg, srlg, sllk, srlk |
adf22b3f AK |
8837 | (define_insn "*<shift><mode>3<addr_style_op><masked_op>" |
8838 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8839 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8840 | (match_operand:SI 2 "nonmemory_operand" "an,an")))] | |
1b48c8cc | 8841 | "" |
65b1d8ea | 8842 | "@ |
adf22b3f AK |
8843 | s<lr>l<g>\t%0,<1><addr_style_op_ops> |
8844 | s<lr>l<gk>\t%0,%1,<addr_style_op_ops>" | |
65b1d8ea AK |
8845 | [(set_attr "op_type" "RS<E>,RSY") |
8846 | (set_attr "atype" "reg,reg") | |
8847 | (set_attr "cpu_facility" "*,z196") | |
adf22b3f | 8848 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8849 | |
9db1d521 | 8850 | ; |
1b48c8cc | 8851 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 8852 | ; Arithmetic right shifts |
9db1d521 | 8853 | |
1b48c8cc | 8854 | (define_expand "ashr<mode>3" |
9db1d521 | 8855 | [(parallel |
1b48c8cc AS |
8856 | [(set (match_operand:DSI 0 "register_operand" "") |
8857 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
a9fcf821 | 8858 | (match_operand:SI 2 "nonmemory_operand" ""))) |
ae156f85 | 8859 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8860 | "" |
8861 | "") | |
8862 | ||
a9fcf821 AK |
8863 | ; FIXME: The number of alternatives is doubled here to match the fix |
8864 | ; number of 2 in the subst pattern for the (clobber (match_scratch... | |
8865 | ; The right fix should be to support match_scratch in the output | |
8866 | ; pattern of a define_subst. | |
8867 | (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>" | |
8868 | [(set (match_operand:DI 0 "register_operand" "=d, d") | |
8869 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0") | |
8870 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8871 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8872 | "!TARGET_ZARCH" |
65b1d8ea | 8873 | "@ |
a9fcf821 AK |
8874 | srda\t%0,<addr_style_op_cc_ops> |
8875 | srda\t%0,<addr_style_op_cc_ops>" | |
8876 | [(set_attr "op_type" "RS") | |
8877 | (set_attr "atype" "reg")]) | |
ecbe845e | 8878 | |
ecbe845e | 8879 | |
43a09b63 | 8880 | ; sra, srag |
a9fcf821 AK |
8881 | (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>" |
8882 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8883 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8884 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8885 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 8886 | "" |
65b1d8ea | 8887 | "@ |
a9fcf821 AK |
8888 | sra<g>\t%0,<1><addr_style_op_cc_ops> |
8889 | sra<gk>\t%0,%1,<addr_style_op_cc_ops>" | |
65b1d8ea | 8890 | [(set_attr "op_type" "RS<E>,RSY") |
a9fcf821 | 8891 | (set_attr "atype" "reg") |
01496eca | 8892 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 8893 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8894 | |
9db1d521 | 8895 | |
9db1d521 HP |
8896 | ;; |
8897 | ;; Branch instruction patterns. | |
8898 | ;; | |
8899 | ||
f90b7a5a | 8900 | (define_expand "cbranch<mode>4" |
fa77b251 | 8901 | [(set (pc) |
f90b7a5a PB |
8902 | (if_then_else (match_operator 0 "comparison_operator" |
8903 | [(match_operand:GPR 1 "register_operand" "") | |
8904 | (match_operand:GPR 2 "general_operand" "")]) | |
8905 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 8906 | (pc)))] |
ba956982 | 8907 | "" |
f90b7a5a PB |
8908 | "s390_emit_jump (operands[3], |
8909 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8910 | DONE;") | |
8911 | ||
8912 | (define_expand "cbranch<mode>4" | |
8913 | [(set (pc) | |
8914 | (if_then_else (match_operator 0 "comparison_operator" | |
8915 | [(match_operand:FP 1 "register_operand" "") | |
8916 | (match_operand:FP 2 "general_operand" "")]) | |
8917 | (label_ref (match_operand 3 "" "")) | |
8918 | (pc)))] | |
8919 | "TARGET_HARD_FLOAT" | |
8920 | "s390_emit_jump (operands[3], | |
8921 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8922 | DONE;") | |
8923 | ||
8924 | (define_expand "cbranchcc4" | |
8925 | [(set (pc) | |
de6fba39 | 8926 | (if_then_else (match_operator 0 "s390_comparison" |
f90b7a5a | 8927 | [(match_operand 1 "cc_reg_operand" "") |
de6fba39 | 8928 | (match_operand 2 "const_int_operand" "")]) |
f90b7a5a PB |
8929 | (label_ref (match_operand 3 "" "")) |
8930 | (pc)))] | |
de6fba39 UW |
8931 | "" |
8932 | "") | |
ba956982 | 8933 | |
9db1d521 HP |
8934 | |
8935 | ;; | |
8936 | ;;- Conditional jump instructions. | |
8937 | ;; | |
8938 | ||
6590e19a UW |
8939 | (define_insn "*cjump_64" |
8940 | [(set (pc) | |
8941 | (if_then_else | |
5a3fe9b6 AK |
8942 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8943 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8944 | (label_ref (match_operand 0 "" "")) |
8945 | (pc)))] | |
8cc6307c | 8946 | "" |
9db1d521 | 8947 | { |
13e58269 | 8948 | if (get_attr_length (insn) == 4) |
d40c829f | 8949 | return "j%C1\t%l0"; |
6590e19a | 8950 | else |
d40c829f | 8951 | return "jg%C1\t%l0"; |
6590e19a UW |
8952 | } |
8953 | [(set_attr "op_type" "RI") | |
8954 | (set_attr "type" "branch") | |
8955 | (set (attr "length") | |
8956 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8957 | (const_int 4) (const_int 6)))]) | |
8958 | ||
f314b9b1 | 8959 | (define_insn "*cjump_long" |
6590e19a UW |
8960 | [(set (pc) |
8961 | (if_then_else | |
ae156f85 | 8962 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 8963 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 8964 | (pc)))] |
84b4c7b5 | 8965 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
f314b9b1 UW |
8966 | { |
8967 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8968 | return "b%C1r\t%0"; |
f314b9b1 | 8969 | else |
d40c829f | 8970 | return "b%C1\t%a0"; |
10bbf137 | 8971 | } |
c7453384 | 8972 | [(set (attr "op_type") |
f314b9b1 UW |
8973 | (if_then_else (match_operand 0 "register_operand" "") |
8974 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
8975 | (set (attr "mnemonic") |
8976 | (if_then_else (match_operand 0 "register_operand" "") | |
8977 | (const_string "bcr") (const_string "bc"))) | |
6590e19a | 8978 | (set_attr "type" "branch") |
077dab3b | 8979 | (set_attr "atype" "agen")]) |
9db1d521 | 8980 | |
177bc204 RS |
8981 | ;; A conditional return instruction. |
8982 | (define_insn "*c<code>" | |
8983 | [(set (pc) | |
8984 | (if_then_else | |
8985 | (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
8986 | (ANY_RETURN) | |
8987 | (pc)))] | |
8988 | "s390_can_use_<code>_insn ()" | |
84b4c7b5 AK |
8989 | { |
8990 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
8991 | { | |
8992 | s390_indirect_branch_via_thunk (RETURN_REGNUM, | |
8993 | INVALID_REGNUM, | |
8994 | operands[0], | |
8995 | s390_indirect_branch_type_return); | |
8996 | return ""; | |
8997 | } | |
8998 | else | |
8999 | return "b%C0r\t%%r14"; | |
9000 | } | |
9001 | [(set (attr "op_type") | |
9002 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
9003 | (const_string "RIL") | |
9004 | (const_string "RR"))) | |
9005 | (set (attr "mnemonic") | |
9006 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
9007 | (const_string "brcl") | |
9008 | (const_string "bcr"))) | |
177bc204 RS |
9009 | (set_attr "type" "jsr") |
9010 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
9011 | |
9012 | ;; | |
9013 | ;;- Negated conditional jump instructions. | |
9014 | ;; | |
9015 | ||
6590e19a UW |
9016 | (define_insn "*icjump_64" |
9017 | [(set (pc) | |
9018 | (if_then_else | |
ae156f85 | 9019 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
9020 | (pc) |
9021 | (label_ref (match_operand 0 "" ""))))] | |
8cc6307c | 9022 | "" |
c7453384 | 9023 | { |
13e58269 | 9024 | if (get_attr_length (insn) == 4) |
d40c829f | 9025 | return "j%D1\t%l0"; |
6590e19a | 9026 | else |
d40c829f | 9027 | return "jg%D1\t%l0"; |
6590e19a UW |
9028 | } |
9029 | [(set_attr "op_type" "RI") | |
9030 | (set_attr "type" "branch") | |
9031 | (set (attr "length") | |
9032 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9033 | (const_int 4) (const_int 6)))]) | |
9034 | ||
f314b9b1 | 9035 | (define_insn "*icjump_long" |
6590e19a UW |
9036 | [(set (pc) |
9037 | (if_then_else | |
ae156f85 | 9038 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 9039 | (pc) |
4fe6dea8 | 9040 | (match_operand 0 "address_operand" "ZQZR")))] |
84b4c7b5 | 9041 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
f314b9b1 UW |
9042 | { |
9043 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9044 | return "b%D1r\t%0"; |
f314b9b1 | 9045 | else |
d40c829f | 9046 | return "b%D1\t%a0"; |
10bbf137 | 9047 | } |
c7453384 | 9048 | [(set (attr "op_type") |
f314b9b1 UW |
9049 | (if_then_else (match_operand 0 "register_operand" "") |
9050 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9051 | (set (attr "mnemonic") |
9052 | (if_then_else (match_operand 0 "register_operand" "") | |
9053 | (const_string "bcr") (const_string "bc"))) | |
077dab3b HP |
9054 | (set_attr "type" "branch") |
9055 | (set_attr "atype" "agen")]) | |
9db1d521 | 9056 | |
4456530d HP |
9057 | ;; |
9058 | ;;- Trap instructions. | |
9059 | ;; | |
9060 | ||
9061 | (define_insn "trap" | |
9062 | [(trap_if (const_int 1) (const_int 0))] | |
9063 | "" | |
d40c829f | 9064 | "j\t.+2" |
6590e19a | 9065 | [(set_attr "op_type" "RI") |
077dab3b | 9066 | (set_attr "type" "branch")]) |
4456530d | 9067 | |
f90b7a5a PB |
9068 | (define_expand "ctrap<mode>4" |
9069 | [(trap_if (match_operator 0 "comparison_operator" | |
9070 | [(match_operand:GPR 1 "register_operand" "") | |
9071 | (match_operand:GPR 2 "general_operand" "")]) | |
9072 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 9073 | "" |
f90b7a5a PB |
9074 | { |
9075 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9076 | operands[1], operands[2]); | |
9077 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9078 | DONE; | |
9079 | }) | |
9080 | ||
9081 | (define_expand "ctrap<mode>4" | |
9082 | [(trap_if (match_operator 0 "comparison_operator" | |
9083 | [(match_operand:FP 1 "register_operand" "") | |
9084 | (match_operand:FP 2 "general_operand" "")]) | |
9085 | (match_operand 3 "const0_operand" ""))] | |
9086 | "" | |
9087 | { | |
9088 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9089 | operands[1], operands[2]); | |
9090 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9091 | DONE; | |
9092 | }) | |
4456530d | 9093 | |
f90b7a5a PB |
9094 | (define_insn "condtrap" |
9095 | [(trap_if (match_operator 0 "s390_comparison" | |
9096 | [(match_operand 1 "cc_reg_operand" "c") | |
9097 | (const_int 0)]) | |
4456530d HP |
9098 | (const_int 0))] |
9099 | "" | |
d40c829f | 9100 | "j%C0\t.+2"; |
077dab3b HP |
9101 | [(set_attr "op_type" "RI") |
9102 | (set_attr "type" "branch")]) | |
9db1d521 | 9103 | |
963fc8d0 AK |
9104 | ; crt, cgrt, cit, cgit |
9105 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
9106 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
9107 | [(match_operand:GPR 1 "register_operand" "d,d") | |
9108 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
9109 | (const_int 0))] | |
9110 | "TARGET_Z10" | |
9111 | "@ | |
9112 | c<g>rt%C0\t%1,%2 | |
9113 | c<g>it%C0\t%1,%h2" | |
9114 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 9115 | (set_attr "type" "branch") |
729e750f | 9116 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 9117 | |
22ac2c2f | 9118 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
9119 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
9120 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
3e4be43f UW |
9121 | [(match_operand:GPR 1 "register_operand" "d,d,d") |
9122 | (match_operand:GPR 2 "general_operand" "d,D,T")]) | |
963fc8d0 AK |
9123 | (const_int 0))] |
9124 | "TARGET_Z10" | |
9125 | "@ | |
9126 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
9127 | cl<gf>it%C0\t%1,%x2 |
9128 | cl<g>t%C0\t%1,%2" | |
9129 | [(set_attr "op_type" "RRF,RIE,RSY") | |
9130 | (set_attr "type" "branch") | |
9131 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
9132 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
9133 | ||
9134 | ; lat, lgat | |
9135 | (define_insn "*load_and_trap<mode>" | |
3e4be43f | 9136 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T") |
22ac2c2f AK |
9137 | (const_int 0)) |
9138 | (const_int 0)) | |
9139 | (set (match_operand:GPR 1 "register_operand" "=d") | |
9140 | (match_dup 0))] | |
9141 | "TARGET_ZEC12" | |
9142 | "l<g>at\t%1,%0" | |
9143 | [(set_attr "op_type" "RXY")]) | |
9144 | ||
963fc8d0 | 9145 | |
9db1d521 | 9146 | ;; |
0a3bdf9d | 9147 | ;;- Loop instructions. |
9db1d521 | 9148 | ;; |
0a3bdf9d UW |
9149 | ;; This is all complicated by the fact that since this is a jump insn |
9150 | ;; we must handle our own output reloads. | |
c7453384 | 9151 | |
f1149235 AK |
9152 | ;; branch on index |
9153 | ||
9154 | ; This splitter will be matched by combine and has to add the 2 moves | |
9155 | ; necessary to load the compare and the increment values into a | |
9156 | ; register pair as needed by brxle. | |
9157 | ||
9158 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
9159 | [(set (pc) | |
9160 | (if_then_else | |
9161 | (match_operator 6 "s390_brx_operator" | |
9162 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
9163 | (match_operand:GPR 2 "general_operand" "")) | |
9164 | (match_operand:GPR 3 "register_operand" "")]) | |
9165 | (label_ref (match_operand 0 "" "")) | |
9166 | (pc))) | |
9167 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
9168 | (plus:GPR (match_dup 1) (match_dup 2))) | |
9169 | (clobber (match_scratch:GPR 5 ""))] | |
8cc6307c | 9170 | "" |
f1149235 AK |
9171 | "#" |
9172 | "!reload_completed && !reload_in_progress" | |
9173 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
9174 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
9175 | (parallel [(set (pc) | |
9176 | (if_then_else | |
9177 | (match_op_dup 6 | |
9178 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
9179 | (match_dup 8)]) | |
9180 | (label_ref (match_dup 0)) | |
9181 | (pc))) | |
9182 | (set (match_dup 4) | |
9183 | (plus:GPR (match_dup 1) (match_dup 7))) | |
9184 | (clobber (match_dup 5)) | |
9185 | (clobber (reg:CC CC_REGNUM))])] | |
9186 | { | |
9187 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
9188 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
9189 | gen_highpart (word_mode, dreg)); | |
9190 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
9191 | gen_lowpart (word_mode, dreg)); | |
9192 | }) | |
9193 | ||
9194 | ; brxlg, brxhg | |
9195 | ||
9196 | (define_insn_and_split "*brxg_64bit" | |
9197 | [(set (pc) | |
9198 | (if_then_else | |
9199 | (match_operator 5 "s390_brx_operator" | |
9200 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
9201 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
9202 | (subreg:DI (match_dup 2) 8)]) | |
9203 | (label_ref (match_operand 0 "" "")) | |
9204 | (pc))) | |
9205 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
9206 | (plus:DI (match_dup 1) | |
9207 | (subreg:DI (match_dup 2) 0))) | |
9208 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
9209 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9210 | "TARGET_ZARCH" |
f1149235 AK |
9211 | { |
9212 | if (which_alternative != 0) | |
9213 | return "#"; | |
9214 | else if (get_attr_length (insn) == 6) | |
9215 | return "brx%E5g\t%1,%2,%l0"; | |
9216 | else | |
9217 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
9218 | } | |
9219 | "&& reload_completed | |
9220 | && (!REG_P (operands[3]) | |
9221 | || !rtx_equal_p (operands[1], operands[3]))" | |
9222 | [(set (match_dup 4) (match_dup 1)) | |
9223 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
9224 | (clobber (reg:CC CC_REGNUM))]) | |
9225 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
9226 | (set (match_dup 3) (match_dup 4)) | |
9227 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9228 | (label_ref (match_dup 0)) | |
9229 | (pc)))] | |
9230 | "" | |
9231 | [(set_attr "op_type" "RIE") | |
9232 | (set_attr "type" "branch") | |
9233 | (set (attr "length") | |
9234 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9235 | (const_int 6) (const_int 16)))]) | |
9236 | ||
9237 | ; brxle, brxh | |
9238 | ||
9239 | (define_insn_and_split "*brx_64bit" | |
9240 | [(set (pc) | |
9241 | (if_then_else | |
9242 | (match_operator 5 "s390_brx_operator" | |
9243 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9244 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
9245 | (subreg:SI (match_dup 2) 12)]) | |
9246 | (label_ref (match_operand 0 "" "")) | |
9247 | (pc))) | |
9248 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9249 | (plus:SI (match_dup 1) | |
9250 | (subreg:SI (match_dup 2) 4))) | |
9251 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9252 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9253 | "TARGET_ZARCH" |
f1149235 AK |
9254 | { |
9255 | if (which_alternative != 0) | |
9256 | return "#"; | |
9257 | else if (get_attr_length (insn) == 6) | |
9258 | return "brx%C5\t%1,%2,%l0"; | |
9259 | else | |
9260 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9261 | } | |
9262 | "&& reload_completed | |
9263 | && (!REG_P (operands[3]) | |
9264 | || !rtx_equal_p (operands[1], operands[3]))" | |
9265 | [(set (match_dup 4) (match_dup 1)) | |
9266 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9267 | (clobber (reg:CC CC_REGNUM))]) | |
9268 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
9269 | (set (match_dup 3) (match_dup 4)) | |
9270 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9271 | (label_ref (match_dup 0)) | |
9272 | (pc)))] | |
9273 | "" | |
9274 | [(set_attr "op_type" "RSI") | |
9275 | (set_attr "type" "branch") | |
9276 | (set (attr "length") | |
9277 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9278 | (const_int 6) (const_int 14)))]) | |
9279 | ||
9280 | ; brxle, brxh | |
9281 | ||
9282 | (define_insn_and_split "*brx_31bit" | |
9283 | [(set (pc) | |
9284 | (if_then_else | |
9285 | (match_operator 5 "s390_brx_operator" | |
9286 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9287 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
9288 | (subreg:SI (match_dup 2) 4)]) | |
9289 | (label_ref (match_operand 0 "" "")) | |
9290 | (pc))) | |
9291 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9292 | (plus:SI (match_dup 1) | |
9293 | (subreg:SI (match_dup 2) 0))) | |
9294 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9295 | (clobber (reg:CC CC_REGNUM))] | |
8cc6307c | 9296 | "!TARGET_ZARCH" |
f1149235 AK |
9297 | { |
9298 | if (which_alternative != 0) | |
9299 | return "#"; | |
9300 | else if (get_attr_length (insn) == 6) | |
9301 | return "brx%C5\t%1,%2,%l0"; | |
9302 | else | |
9303 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9304 | } | |
9305 | "&& reload_completed | |
9306 | && (!REG_P (operands[3]) | |
9307 | || !rtx_equal_p (operands[1], operands[3]))" | |
9308 | [(set (match_dup 4) (match_dup 1)) | |
9309 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
9310 | (clobber (reg:CC CC_REGNUM))]) | |
9311 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9312 | (set (match_dup 3) (match_dup 4)) | |
9313 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9314 | (label_ref (match_dup 0)) | |
9315 | (pc)))] | |
9316 | "" | |
9317 | [(set_attr "op_type" "RSI") | |
9318 | (set_attr "type" "branch") | |
9319 | (set (attr "length") | |
9320 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9321 | (const_int 6) (const_int 14)))]) | |
9322 | ||
9323 | ||
9324 | ;; branch on count | |
9325 | ||
0a3bdf9d UW |
9326 | (define_expand "doloop_end" |
9327 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 9328 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 9329 | "" |
0a3bdf9d | 9330 | { |
8cc6307c | 9331 | if (GET_MODE (operands[0]) == SImode) |
1d0216c8 | 9332 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 9333 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 9334 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
9335 | else |
9336 | FAIL; | |
9337 | ||
9338 | DONE; | |
10bbf137 | 9339 | }) |
0a3bdf9d | 9340 | |
6590e19a | 9341 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
9342 | [(set (pc) |
9343 | (if_then_else | |
7e665d18 | 9344 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9345 | (const_int 1)) |
9346 | (label_ref (match_operand 0 "" "")) | |
9347 | (pc))) | |
7e665d18 | 9348 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9349 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9350 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9351 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 9352 | "" |
0a3bdf9d UW |
9353 | { |
9354 | if (which_alternative != 0) | |
10bbf137 | 9355 | return "#"; |
0a3bdf9d | 9356 | else if (get_attr_length (insn) == 4) |
d40c829f | 9357 | return "brct\t%1,%l0"; |
6590e19a | 9358 | else |
545d16ff | 9359 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
9360 | } |
9361 | "&& reload_completed | |
9362 | && (! REG_P (operands[2]) | |
9363 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9364 | [(set (match_dup 3) (match_dup 1)) |
9365 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9366 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9367 | (const_int 0))) | |
9368 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9369 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9370 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9371 | (label_ref (match_dup 0)) |
9372 | (pc)))] | |
9373 | "" | |
9374 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9375 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9376 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9377 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9378 | (set_attr "type" "branch") |
9379 | (set (attr "length") | |
9380 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9381 | (const_int 4) (const_int 10)))]) | |
9382 | ||
6590e19a | 9383 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
9384 | [(set (pc) |
9385 | (if_then_else | |
7e665d18 | 9386 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9387 | (const_int 1)) |
9388 | (label_ref (match_operand 0 "" "")) | |
9389 | (pc))) | |
7e665d18 | 9390 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9391 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 9392 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 9393 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9394 | "TARGET_ZARCH" |
0a3bdf9d UW |
9395 | { |
9396 | if (which_alternative != 0) | |
10bbf137 | 9397 | return "#"; |
0a3bdf9d | 9398 | else if (get_attr_length (insn) == 4) |
d40c829f | 9399 | return "brctg\t%1,%l0"; |
0a3bdf9d | 9400 | else |
545d16ff | 9401 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 9402 | } |
6590e19a | 9403 | "&& reload_completed |
0a3bdf9d UW |
9404 | && (! REG_P (operands[2]) |
9405 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9406 | [(set (match_dup 3) (match_dup 1)) |
9407 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
9408 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
9409 | (const_int 0))) | |
9410 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
9411 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9412 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 9413 | (label_ref (match_dup 0)) |
0a3bdf9d | 9414 | (pc)))] |
6590e19a UW |
9415 | "" |
9416 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9417 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9418 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9419 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9420 | (set_attr "type" "branch") |
9421 | (set (attr "length") | |
9422 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9423 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
9424 | |
9425 | ;; | |
9426 | ;;- Unconditional jump instructions. | |
9427 | ;; | |
9428 | ||
9429 | ; | |
9430 | ; jump instruction pattern(s). | |
9431 | ; | |
9432 | ||
6590e19a UW |
9433 | (define_expand "jump" |
9434 | [(match_operand 0 "" "")] | |
9db1d521 | 9435 | "" |
6590e19a UW |
9436 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
9437 | ||
9438 | (define_insn "*jump64" | |
9439 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8cc6307c | 9440 | "" |
9db1d521 | 9441 | { |
13e58269 | 9442 | if (get_attr_length (insn) == 4) |
d40c829f | 9443 | return "j\t%l0"; |
6590e19a | 9444 | else |
d40c829f | 9445 | return "jg\t%l0"; |
6590e19a UW |
9446 | } |
9447 | [(set_attr "op_type" "RI") | |
9448 | (set_attr "type" "branch") | |
9449 | (set (attr "length") | |
9450 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9451 | (const_int 4) (const_int 6)))]) | |
9452 | ||
9db1d521 HP |
9453 | ; |
9454 | ; indirect-jump instruction pattern(s). | |
9455 | ; | |
9456 | ||
2841f550 AK |
9457 | (define_expand "indirect_jump" |
9458 | [(set (pc) (match_operand 0 "nonimmediate_operand" ""))] | |
9db1d521 | 9459 | "" |
f314b9b1 | 9460 | { |
2841f550 AK |
9461 | if (address_operand (operands[0], GET_MODE (operands[0]))) |
9462 | ; | |
e9e8efc9 | 9463 | else if (TARGET_Z14 |
2841f550 AK |
9464 | && GET_MODE (operands[0]) == Pmode |
9465 | && memory_operand (operands[0], Pmode)) | |
9466 | ; | |
f314b9b1 | 9467 | else |
2841f550 | 9468 | operands[0] = force_reg (Pmode, operands[0]); |
84b4c7b5 AK |
9469 | |
9470 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) | |
9471 | { | |
9472 | operands[0] = force_reg (Pmode, operands[0]); | |
9473 | if (TARGET_CPU_Z10) | |
9474 | { | |
9475 | if (TARGET_64BIT) | |
9476 | emit_jump_insn (gen_indirect_jump_via_thunkdi_z10 (operands[0])); | |
9477 | else | |
9478 | emit_jump_insn (gen_indirect_jump_via_thunksi_z10 (operands[0])); | |
9479 | } | |
9480 | else | |
9481 | { | |
9482 | if (TARGET_64BIT) | |
9483 | emit_jump_insn (gen_indirect_jump_via_thunkdi (operands[0])); | |
9484 | else | |
9485 | emit_jump_insn (gen_indirect_jump_via_thunksi (operands[0])); | |
9486 | } | |
9487 | DONE; | |
9488 | } | |
9489 | ||
9490 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) | |
9491 | { | |
9492 | operands[0] = force_reg (Pmode, operands[0]); | |
9493 | rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
9494 | if (TARGET_CPU_Z10) | |
9495 | { | |
9496 | if (TARGET_64BIT) | |
9497 | emit_jump_insn (gen_indirect_jump_via_inlinethunkdi_z10 (operands[0], | |
9498 | label_ref)); | |
9499 | else | |
9500 | emit_jump_insn (gen_indirect_jump_via_inlinethunksi_z10 (operands[0], | |
9501 | label_ref)); | |
9502 | } | |
9503 | else | |
9504 | { | |
9505 | if (TARGET_64BIT) | |
9506 | emit_jump_insn (gen_indirect_jump_via_inlinethunkdi (operands[0], | |
9507 | label_ref, | |
9508 | force_reg (Pmode, label_ref))); | |
9509 | else | |
9510 | emit_jump_insn (gen_indirect_jump_via_inlinethunksi (operands[0], | |
9511 | label_ref, | |
9512 | force_reg (Pmode, label_ref))); | |
9513 | } | |
9514 | DONE; | |
9515 | } | |
2841f550 AK |
9516 | }) |
9517 | ||
9518 | (define_insn "*indirect_jump" | |
9519 | [(set (pc) | |
84b4c7b5 AK |
9520 | (match_operand 0 "address_operand" "ZR"))] |
9521 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" | |
9522 | { | |
9523 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9524 | return "br\t%0"; | |
9525 | else | |
9526 | return "b\t%a0"; | |
9527 | } | |
9528 | [(set (attr "op_type") | |
9529 | (if_then_else (match_operand 0 "register_operand" "") | |
9530 | (const_string "RR") (const_string "RX"))) | |
9531 | (set (attr "mnemonic") | |
9532 | (if_then_else (match_operand 0 "register_operand" "") | |
9533 | (const_string "br") (const_string "b"))) | |
2841f550 | 9534 | (set_attr "type" "branch") |
84b4c7b5 AK |
9535 | (set_attr "atype" "agen")]) |
9536 | ||
9537 | (define_insn "indirect_jump_via_thunk<mode>_z10" | |
9538 | [(set (pc) | |
9539 | (match_operand:P 0 "register_operand" "a"))] | |
9540 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9541 | && TARGET_CPU_Z10" | |
9542 | { | |
9543 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9544 | INVALID_REGNUM, | |
9545 | NULL_RTX, | |
9546 | s390_indirect_branch_type_jump); | |
9547 | return ""; | |
9548 | } | |
9549 | [(set_attr "op_type" "RIL") | |
9550 | (set_attr "mnemonic" "jg") | |
9551 | (set_attr "type" "branch") | |
9552 | (set_attr "atype" "agen")]) | |
9553 | ||
9554 | (define_insn "indirect_jump_via_thunk<mode>" | |
9555 | [(set (pc) | |
9556 | (match_operand:P 0 "register_operand" " a")) | |
9557 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
9558 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9559 | && !TARGET_CPU_Z10" | |
9560 | { | |
9561 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9562 | INVALID_REGNUM, | |
9563 | NULL_RTX, | |
9564 | s390_indirect_branch_type_jump); | |
9565 | return ""; | |
9566 | } | |
9567 | [(set_attr "op_type" "RIL") | |
9568 | (set_attr "mnemonic" "jg") | |
9569 | (set_attr "type" "branch") | |
9570 | (set_attr "atype" "agen")]) | |
9571 | ||
9572 | ||
9573 | ; The label_ref is wrapped into an if_then_else in order to hide it | |
9574 | ; from mark_jump_label. Without this the label_ref would become the | |
9575 | ; ONLY jump target of that jump breaking the control flow graph. | |
9576 | (define_insn "indirect_jump_via_inlinethunk<mode>_z10" | |
9577 | [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") | |
9578 | (const_int 0) | |
9579 | (const_int 0)) | |
9580 | (const_int 0)] UNSPEC_EXECUTE_JUMP) | |
9581 | (set (pc) (match_operand:P 0 "register_operand" "a"))] | |
9582 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9583 | && TARGET_CPU_Z10" | |
9584 | { | |
9585 | s390_indirect_branch_via_inline_thunk (operands[1]); | |
9586 | return ""; | |
9587 | } | |
9588 | [(set_attr "op_type" "RIL") | |
9589 | (set_attr "type" "branch") | |
9590 | (set_attr "length" "10")]) | |
9591 | ||
9592 | (define_insn "indirect_jump_via_inlinethunk<mode>" | |
9593 | [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") | |
9594 | (const_int 0) | |
9595 | (const_int 0)) | |
9596 | (match_operand:P 2 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) | |
9597 | (set (pc) (match_operand:P 0 "register_operand" "a"))] | |
9598 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9599 | && !TARGET_CPU_Z10" | |
9600 | { | |
9601 | s390_indirect_branch_via_inline_thunk (operands[2]); | |
9602 | return ""; | |
9603 | } | |
9604 | [(set_attr "op_type" "RX") | |
9605 | (set_attr "type" "branch") | |
9606 | (set_attr "length" "8")]) | |
2841f550 AK |
9607 | |
9608 | ; FIXME: LRA does not appear to be able to deal with MEMs being | |
9609 | ; checked against address constraints like ZR above. So make this a | |
9610 | ; separate pattern for now. | |
9611 | (define_insn "*indirect2_jump" | |
9612 | [(set (pc) | |
9613 | (match_operand 0 "nonimmediate_operand" "a,T"))] | |
84b4c7b5 | 9614 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
2841f550 AK |
9615 | "@ |
9616 | br\t%0 | |
9617 | bi\t%0" | |
9618 | [(set_attr "op_type" "RR,RXY") | |
9619 | (set_attr "type" "branch") | |
9620 | (set_attr "atype" "agen") | |
e9e8efc9 | 9621 | (set_attr "cpu_facility" "*,z14")]) |
9db1d521 HP |
9622 | |
9623 | ; | |
f314b9b1 | 9624 | ; casesi instruction pattern(s). |
9db1d521 HP |
9625 | ; |
9626 | ||
84b4c7b5 AK |
9627 | (define_expand "casesi_jump" |
9628 | [(parallel | |
9629 | [(set (pc) (match_operand 0 "address_operand")) | |
9630 | (use (label_ref (match_operand 1 "")))])] | |
9db1d521 | 9631 | "" |
84b4c7b5 AK |
9632 | { |
9633 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) | |
9634 | { | |
9635 | operands[0] = force_reg (GET_MODE (operands[0]), operands[0]); | |
9636 | ||
9637 | if (TARGET_CPU_Z10) | |
9638 | { | |
9639 | if (TARGET_64BIT) | |
9640 | emit_jump_insn (gen_casesi_jump_via_thunkdi_z10 (operands[0], | |
9641 | operands[1])); | |
9642 | else | |
9643 | emit_jump_insn (gen_casesi_jump_via_thunksi_z10 (operands[0], | |
9644 | operands[1])); | |
9645 | } | |
9646 | else | |
9647 | { | |
9648 | if (TARGET_64BIT) | |
9649 | emit_jump_insn (gen_casesi_jump_via_thunkdi (operands[0], | |
9650 | operands[1])); | |
9651 | else | |
9652 | emit_jump_insn (gen_casesi_jump_via_thunksi (operands[0], | |
9653 | operands[1])); | |
9654 | } | |
9655 | DONE; | |
9656 | } | |
9657 | ||
9658 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) | |
9659 | { | |
9660 | operands[0] = force_reg (Pmode, operands[0]); | |
9661 | rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
9662 | if (TARGET_CPU_Z10) | |
9663 | { | |
9664 | if (TARGET_64BIT) | |
9665 | emit_jump_insn (gen_casesi_jump_via_inlinethunkdi_z10 (operands[0], | |
9666 | operands[1], | |
9667 | label_ref)); | |
9668 | else | |
9669 | emit_jump_insn (gen_casesi_jump_via_inlinethunksi_z10 (operands[0], | |
9670 | operands[1], | |
9671 | label_ref)); | |
9672 | } | |
9673 | else | |
9674 | { | |
9675 | if (TARGET_64BIT) | |
9676 | emit_jump_insn (gen_casesi_jump_via_inlinethunkdi (operands[0], | |
9677 | operands[1], | |
9678 | label_ref, | |
9679 | force_reg (Pmode, label_ref))); | |
9680 | else | |
9681 | emit_jump_insn (gen_casesi_jump_via_inlinethunksi (operands[0], | |
9682 | operands[1], | |
9683 | label_ref, | |
9684 | force_reg (Pmode, label_ref))); | |
9685 | } | |
9686 | DONE; | |
9687 | } | |
9688 | }) | |
9689 | ||
9690 | (define_insn "*casesi_jump" | |
9691 | [(set (pc) (match_operand 0 "address_operand" "ZR")) | |
9692 | (use (label_ref (match_operand 1 "" "")))] | |
9693 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" | |
9db1d521 | 9694 | { |
f314b9b1 | 9695 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 9696 | return "br\t%0"; |
f314b9b1 | 9697 | else |
d40c829f | 9698 | return "b\t%a0"; |
10bbf137 | 9699 | } |
c7453384 | 9700 | [(set (attr "op_type") |
f314b9b1 UW |
9701 | (if_then_else (match_operand 0 "register_operand" "") |
9702 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9703 | (set (attr "mnemonic") |
9704 | (if_then_else (match_operand 0 "register_operand" "") | |
9705 | (const_string "br") (const_string "b"))) | |
9706 | (set_attr "type" "branch") | |
9707 | (set_attr "atype" "agen")]) | |
9708 | ||
9709 | (define_insn "casesi_jump_via_thunk<mode>_z10" | |
9710 | [(set (pc) (match_operand:P 0 "register_operand" "a")) | |
9711 | (use (label_ref (match_operand 1 "" "")))] | |
9712 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9713 | && TARGET_CPU_Z10" | |
9714 | { | |
9715 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9716 | INVALID_REGNUM, | |
9717 | NULL_RTX, | |
9718 | s390_indirect_branch_type_jump); | |
9719 | return ""; | |
9720 | } | |
9721 | [(set_attr "op_type" "RIL") | |
9722 | (set_attr "mnemonic" "jg") | |
9723 | (set_attr "type" "branch") | |
9724 | (set_attr "atype" "agen")]) | |
9725 | ||
9726 | (define_insn "casesi_jump_via_thunk<mode>" | |
9727 | [(set (pc) (match_operand:P 0 "register_operand" "a")) | |
9728 | (use (label_ref (match_operand 1 "" ""))) | |
9729 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
9730 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9731 | && !TARGET_CPU_Z10" | |
9732 | { | |
9733 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9734 | INVALID_REGNUM, | |
9735 | NULL_RTX, | |
9736 | s390_indirect_branch_type_jump); | |
9737 | return ""; | |
9738 | } | |
9739 | [(set_attr "op_type" "RIL") | |
9740 | (set_attr "mnemonic" "jg") | |
077dab3b HP |
9741 | (set_attr "type" "branch") |
9742 | (set_attr "atype" "agen")]) | |
9db1d521 | 9743 | |
84b4c7b5 AK |
9744 | |
9745 | ; The label_ref is wrapped into an if_then_else in order to hide it | |
9746 | ; from mark_jump_label. Without this the label_ref would become the | |
9747 | ; ONLY jump target of that jump breaking the control flow graph. | |
9748 | (define_insn "casesi_jump_via_inlinethunk<mode>_z10" | |
9749 | [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") | |
9750 | (const_int 0) | |
9751 | (const_int 0)) | |
9752 | (const_int 0)] UNSPEC_EXECUTE_JUMP) | |
9753 | (set (pc) (match_operand:P 0 "register_operand" "a")) | |
9754 | (use (label_ref (match_operand 1 "" "")))] | |
9755 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9756 | && TARGET_CPU_Z10" | |
9757 | { | |
9758 | s390_indirect_branch_via_inline_thunk (operands[2]); | |
9759 | return ""; | |
9760 | } | |
9761 | [(set_attr "op_type" "RIL") | |
9762 | (set_attr "type" "cs") | |
9763 | (set_attr "length" "10")]) | |
9764 | ||
9765 | (define_insn "casesi_jump_via_inlinethunk<mode>" | |
9766 | [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") | |
9767 | (const_int 0) | |
9768 | (const_int 0)) | |
9769 | (match_operand:P 3 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) | |
9770 | (set (pc) (match_operand:P 0 "register_operand" "a")) | |
9771 | (use (label_ref (match_operand 1 "" "")))] | |
9772 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9773 | && !TARGET_CPU_Z10" | |
9774 | { | |
9775 | s390_indirect_branch_via_inline_thunk (operands[3]); | |
9776 | return ""; | |
9777 | } | |
9778 | [(set_attr "op_type" "RX") | |
9779 | (set_attr "type" "cs") | |
9780 | (set_attr "length" "8")]) | |
9781 | ||
f314b9b1 UW |
9782 | (define_expand "casesi" |
9783 | [(match_operand:SI 0 "general_operand" "") | |
9784 | (match_operand:SI 1 "general_operand" "") | |
9785 | (match_operand:SI 2 "general_operand" "") | |
9786 | (label_ref (match_operand 3 "" "")) | |
9787 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 9788 | "" |
f314b9b1 UW |
9789 | { |
9790 | rtx index = gen_reg_rtx (SImode); | |
9791 | rtx base = gen_reg_rtx (Pmode); | |
9792 | rtx target = gen_reg_rtx (Pmode); | |
9793 | ||
9794 | emit_move_insn (index, operands[0]); | |
9795 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
9796 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 9797 | operands[4]); |
f314b9b1 UW |
9798 | |
9799 | if (Pmode != SImode) | |
9800 | index = convert_to_mode (Pmode, index, 1); | |
9801 | if (GET_CODE (index) != REG) | |
9802 | index = copy_to_mode_reg (Pmode, index); | |
9803 | ||
9804 | if (TARGET_64BIT) | |
9805 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
9806 | else | |
a556fd39 | 9807 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 9808 | |
f314b9b1 UW |
9809 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
9810 | ||
542a8afa | 9811 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
9812 | emit_move_insn (target, index); |
9813 | ||
9814 | if (flag_pic) | |
9815 | target = gen_rtx_PLUS (Pmode, base, target); | |
9816 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
9817 | ||
9818 | DONE; | |
10bbf137 | 9819 | }) |
9db1d521 HP |
9820 | |
9821 | ||
9822 | ;; | |
9823 | ;;- Jump to subroutine. | |
9824 | ;; | |
9825 | ;; | |
9826 | ||
9827 | ; | |
9828 | ; untyped call instruction pattern(s). | |
9829 | ; | |
9830 | ||
9831 | ;; Call subroutine returning any type. | |
9832 | (define_expand "untyped_call" | |
9833 | [(parallel [(call (match_operand 0 "" "") | |
9834 | (const_int 0)) | |
9835 | (match_operand 1 "" "") | |
9836 | (match_operand 2 "" "")])] | |
9837 | "" | |
9db1d521 HP |
9838 | { |
9839 | int i; | |
9840 | ||
9841 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
9842 | ||
9843 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9844 | { | |
9845 | rtx set = XVECEXP (operands[2], 0, i); | |
9846 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9847 | } | |
9848 | ||
9849 | /* The optimizer does not know that the call sets the function value | |
9850 | registers we stored in the result block. We avoid problems by | |
9851 | claiming that all hard registers are used and clobbered at this | |
9852 | point. */ | |
9853 | emit_insn (gen_blockage ()); | |
9854 | ||
9855 | DONE; | |
10bbf137 | 9856 | }) |
9db1d521 HP |
9857 | |
9858 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9859 | ;; all of memory. This blocks insns from being moved across this point. | |
9860 | ||
9861 | (define_insn "blockage" | |
10bbf137 | 9862 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 9863 | "" |
4023fb28 | 9864 | "" |
d5869ca0 UW |
9865 | [(set_attr "type" "none") |
9866 | (set_attr "length" "0")]) | |
4023fb28 | 9867 | |
9db1d521 | 9868 | ; |
ed9676cf | 9869 | ; sibcall patterns |
9db1d521 HP |
9870 | ; |
9871 | ||
ed9676cf | 9872 | (define_expand "sibcall" |
44b8152b | 9873 | [(call (match_operand 0 "" "") |
ed9676cf | 9874 | (match_operand 1 "" ""))] |
9db1d521 | 9875 | "" |
9db1d521 | 9876 | { |
ed9676cf AK |
9877 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
9878 | DONE; | |
9879 | }) | |
9db1d521 | 9880 | |
ed9676cf | 9881 | (define_insn "*sibcall_br" |
ae156f85 | 9882 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9883 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 9884 | "SIBLING_CALL_P (insn) |
ed9676cf | 9885 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
84b4c7b5 AK |
9886 | { |
9887 | if (TARGET_INDIRECT_BRANCH_NOBP_CALL) | |
9888 | { | |
9889 | gcc_assert (TARGET_CPU_Z10); | |
9890 | s390_indirect_branch_via_thunk (SIBCALL_REGNUM, | |
9891 | INVALID_REGNUM, | |
9892 | NULL_RTX, | |
9893 | s390_indirect_branch_type_call); | |
9894 | return ""; | |
9895 | } | |
9896 | else | |
9897 | return "br\t%%r1"; | |
9898 | } | |
9899 | [(set (attr "op_type") | |
9900 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9901 | (const_string "RIL") | |
9902 | (const_string "RR"))) | |
9903 | (set (attr "mnemonic") | |
9904 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9905 | (const_string "jg") | |
9906 | (const_string "br"))) | |
ed9676cf AK |
9907 | (set_attr "type" "branch") |
9908 | (set_attr "atype" "agen")]) | |
9db1d521 | 9909 | |
ed9676cf AK |
9910 | (define_insn "*sibcall_brc" |
9911 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9912 | (match_operand 1 "const_int_operand" "n"))] | |
9913 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9914 | "j\t%0" | |
9915 | [(set_attr "op_type" "RI") | |
9916 | (set_attr "type" "branch")]) | |
9db1d521 | 9917 | |
ed9676cf AK |
9918 | (define_insn "*sibcall_brcl" |
9919 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9920 | (match_operand 1 "const_int_operand" "n"))] | |
8cc6307c | 9921 | "SIBLING_CALL_P (insn)" |
ed9676cf AK |
9922 | "jg\t%0" |
9923 | [(set_attr "op_type" "RIL") | |
9924 | (set_attr "type" "branch")]) | |
44b8152b | 9925 | |
ed9676cf AK |
9926 | ; |
9927 | ; sibcall_value patterns | |
9928 | ; | |
9e8327e3 | 9929 | |
ed9676cf AK |
9930 | (define_expand "sibcall_value" |
9931 | [(set (match_operand 0 "" "") | |
9932 | (call (match_operand 1 "" "") | |
9933 | (match_operand 2 "" "")))] | |
9934 | "" | |
9935 | { | |
9936 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 9937 | DONE; |
10bbf137 | 9938 | }) |
9db1d521 | 9939 | |
ed9676cf AK |
9940 | (define_insn "*sibcall_value_br" |
9941 | [(set (match_operand 0 "" "") | |
ae156f85 | 9942 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9943 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 9944 | "SIBLING_CALL_P (insn) |
ed9676cf | 9945 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
84b4c7b5 AK |
9946 | { |
9947 | if (TARGET_INDIRECT_BRANCH_NOBP_CALL) | |
9948 | { | |
9949 | gcc_assert (TARGET_CPU_Z10); | |
9950 | s390_indirect_branch_via_thunk (SIBCALL_REGNUM, | |
9951 | INVALID_REGNUM, | |
9952 | NULL_RTX, | |
9953 | s390_indirect_branch_type_call); | |
9954 | return ""; | |
9955 | } | |
9956 | else | |
9957 | return "br\t%%r1"; | |
9958 | } | |
9959 | [(set (attr "op_type") | |
9960 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9961 | (const_string "RIL") | |
9962 | (const_string "RR"))) | |
9963 | (set (attr "mnemonic") | |
9964 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9965 | (const_string "jg") | |
9966 | (const_string "br"))) | |
ed9676cf AK |
9967 | (set_attr "type" "branch") |
9968 | (set_attr "atype" "agen")]) | |
9969 | ||
9970 | (define_insn "*sibcall_value_brc" | |
9971 | [(set (match_operand 0 "" "") | |
9972 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9973 | (match_operand 2 "const_int_operand" "n")))] | |
9974 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9975 | "j\t%1" | |
9976 | [(set_attr "op_type" "RI") | |
9977 | (set_attr "type" "branch")]) | |
9978 | ||
9979 | (define_insn "*sibcall_value_brcl" | |
9980 | [(set (match_operand 0 "" "") | |
9981 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9982 | (match_operand 2 "const_int_operand" "n")))] | |
8cc6307c | 9983 | "SIBLING_CALL_P (insn)" |
ed9676cf AK |
9984 | "jg\t%1" |
9985 | [(set_attr "op_type" "RIL") | |
9986 | (set_attr "type" "branch")]) | |
9987 | ||
9988 | ||
9989 | ; | |
9990 | ; call instruction pattern(s). | |
9991 | ; | |
9992 | ||
9993 | (define_expand "call" | |
9994 | [(call (match_operand 0 "" "") | |
9995 | (match_operand 1 "" "")) | |
9996 | (use (match_operand 2 "" ""))] | |
44b8152b | 9997 | "" |
ed9676cf | 9998 | { |
2f7e5a0d | 9999 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
10000 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
10001 | DONE; | |
10002 | }) | |
44b8152b | 10003 | |
9e8327e3 UW |
10004 | (define_insn "*bras" |
10005 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10006 | (match_operand 1 "const_int_operand" "n")) | |
10007 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
10008 | "!SIBLING_CALL_P (insn) |
10009 | && TARGET_SMALL_EXEC | |
ed9676cf | 10010 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 10011 | "bras\t%2,%0" |
9db1d521 | 10012 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10013 | (set_attr "type" "jsr") |
10014 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10015 | |
9e8327e3 UW |
10016 | (define_insn "*brasl" |
10017 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10018 | (match_operand 1 "const_int_operand" "n")) | |
10019 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d | 10020 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10021 | |
ed9676cf | 10022 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
10023 | "brasl\t%2,%0" |
10024 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10025 | (set_attr "type" "jsr") |
14cfceb7 IL |
10026 | (set_attr "z196prop" "z196_cracked") |
10027 | (set_attr "relative_long" "yes")]) | |
9db1d521 | 10028 | |
9e8327e3 | 10029 | (define_insn "*basr" |
3e4be43f | 10030 | [(call (mem:QI (match_operand 0 "address_operand" "ZR")) |
9e8327e3 UW |
10031 | (match_operand 1 "const_int_operand" "n")) |
10032 | (clobber (match_operand 2 "register_operand" "=r"))] | |
84b4c7b5 AK |
10033 | "!TARGET_INDIRECT_BRANCH_NOBP_CALL |
10034 | && !SIBLING_CALL_P (insn) | |
10035 | && GET_MODE (operands[2]) == Pmode" | |
9e8327e3 UW |
10036 | { |
10037 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10038 | return "basr\t%2,%0"; | |
10039 | else | |
10040 | return "bas\t%2,%a0"; | |
10041 | } | |
10042 | [(set (attr "op_type") | |
10043 | (if_then_else (match_operand 0 "register_operand" "") | |
10044 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
10045 | (set (attr "mnemonic") |
10046 | (if_then_else (match_operand 0 "register_operand" "") | |
10047 | (const_string "basr") (const_string "bas"))) | |
10048 | (set_attr "type" "jsr") | |
10049 | (set_attr "atype" "agen") | |
10050 | (set_attr "z196prop" "z196_cracked")]) | |
10051 | ||
10052 | (define_insn "*basr_via_thunk<mode>_z10" | |
10053 | [(call (mem:QI (match_operand:P 0 "register_operand" "a")) | |
10054 | (match_operand 1 "const_int_operand" "n")) | |
10055 | (clobber (match_operand:P 2 "register_operand" "=&r"))] | |
10056 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10057 | && TARGET_CPU_Z10 | |
10058 | && !SIBLING_CALL_P (insn)" | |
10059 | { | |
10060 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10061 | REGNO (operands[2]), | |
10062 | NULL_RTX, | |
10063 | s390_indirect_branch_type_call); | |
10064 | return ""; | |
10065 | } | |
10066 | [(set_attr "op_type" "RIL") | |
10067 | (set_attr "mnemonic" "brasl") | |
10068 | (set_attr "type" "jsr") | |
10069 | (set_attr "atype" "agen") | |
10070 | (set_attr "z196prop" "z196_cracked")]) | |
10071 | ||
10072 | (define_insn "*basr_via_thunk<mode>" | |
10073 | [(call (mem:QI (match_operand:P 0 "register_operand" "a")) | |
10074 | (match_operand 1 "const_int_operand" "n")) | |
10075 | (clobber (match_operand:P 2 "register_operand" "=&r")) | |
10076 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10077 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10078 | && !TARGET_CPU_Z10 | |
10079 | && !SIBLING_CALL_P (insn)" | |
10080 | { | |
10081 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10082 | REGNO (operands[2]), | |
10083 | NULL_RTX, | |
10084 | s390_indirect_branch_type_call); | |
10085 | return ""; | |
10086 | } | |
10087 | [(set_attr "op_type" "RIL") | |
10088 | (set_attr "mnemonic" "brasl") | |
9e8327e3 | 10089 | (set_attr "type" "jsr") |
65b1d8ea AK |
10090 | (set_attr "atype" "agen") |
10091 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
10092 | |
10093 | ; | |
10094 | ; call_value instruction pattern(s). | |
10095 | ; | |
10096 | ||
10097 | (define_expand "call_value" | |
44b8152b UW |
10098 | [(set (match_operand 0 "" "") |
10099 | (call (match_operand 1 "" "") | |
10100 | (match_operand 2 "" ""))) | |
10101 | (use (match_operand 3 "" ""))] | |
9db1d521 | 10102 | "" |
9db1d521 | 10103 | { |
2f7e5a0d | 10104 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 10105 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 10106 | DONE; |
10bbf137 | 10107 | }) |
9db1d521 | 10108 | |
9e8327e3 | 10109 | (define_insn "*bras_r" |
c19ec8f9 | 10110 | [(set (match_operand 0 "" "") |
9e8327e3 | 10111 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 10112 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 10113 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
10114 | "!SIBLING_CALL_P (insn) |
10115 | && TARGET_SMALL_EXEC | |
ed9676cf | 10116 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 10117 | "bras\t%3,%1" |
9db1d521 | 10118 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10119 | (set_attr "type" "jsr") |
10120 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10121 | |
9e8327e3 | 10122 | (define_insn "*brasl_r" |
c19ec8f9 | 10123 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10124 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10125 | (match_operand 2 "const_int_operand" "n"))) | |
10126 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d | 10127 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10128 | |
ed9676cf | 10129 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10130 | "brasl\t%3,%1" |
10131 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10132 | (set_attr "type" "jsr") |
14cfceb7 IL |
10133 | (set_attr "z196prop" "z196_cracked") |
10134 | (set_attr "relative_long" "yes")]) | |
9db1d521 | 10135 | |
9e8327e3 | 10136 | (define_insn "*basr_r" |
c19ec8f9 | 10137 | [(set (match_operand 0 "" "") |
3e4be43f | 10138 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
10139 | (match_operand 2 "const_int_operand" "n"))) |
10140 | (clobber (match_operand 3 "register_operand" "=r"))] | |
84b4c7b5 AK |
10141 | "!TARGET_INDIRECT_BRANCH_NOBP_CALL |
10142 | && !SIBLING_CALL_P (insn) | |
10143 | && GET_MODE (operands[3]) == Pmode" | |
9e8327e3 UW |
10144 | { |
10145 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10146 | return "basr\t%3,%1"; | |
10147 | else | |
10148 | return "bas\t%3,%a1"; | |
10149 | } | |
10150 | [(set (attr "op_type") | |
10151 | (if_then_else (match_operand 1 "register_operand" "") | |
10152 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
10153 | (set (attr "mnemonic") |
10154 | (if_then_else (match_operand 1 "register_operand" "") | |
10155 | (const_string "basr") (const_string "bas"))) | |
10156 | (set_attr "type" "jsr") | |
10157 | (set_attr "atype" "agen") | |
10158 | (set_attr "z196prop" "z196_cracked")]) | |
10159 | ||
10160 | (define_insn "*basr_r_via_thunk_z10" | |
10161 | [(set (match_operand 0 "" "") | |
10162 | (call (mem:QI (match_operand 1 "register_operand" "a")) | |
10163 | (match_operand 2 "const_int_operand" "n"))) | |
10164 | (clobber (match_operand 3 "register_operand" "=&r"))] | |
10165 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10166 | && TARGET_CPU_Z10 | |
10167 | && !SIBLING_CALL_P (insn) | |
10168 | && GET_MODE (operands[3]) == Pmode" | |
10169 | { | |
10170 | s390_indirect_branch_via_thunk (REGNO (operands[1]), | |
10171 | REGNO (operands[3]), | |
10172 | NULL_RTX, | |
10173 | s390_indirect_branch_type_call); | |
10174 | return ""; | |
10175 | } | |
10176 | [(set_attr "op_type" "RIL") | |
10177 | (set_attr "mnemonic" "brasl") | |
10178 | (set_attr "type" "jsr") | |
10179 | (set_attr "atype" "agen") | |
10180 | (set_attr "z196prop" "z196_cracked")]) | |
10181 | ||
10182 | (define_insn "*basr_r_via_thunk" | |
10183 | [(set (match_operand 0 "" "") | |
10184 | (call (mem:QI (match_operand 1 "register_operand" "a")) | |
10185 | (match_operand 2 "const_int_operand" "n"))) | |
10186 | (clobber (match_operand 3 "register_operand" "=&r")) | |
10187 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10188 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10189 | && !TARGET_CPU_Z10 | |
10190 | && !SIBLING_CALL_P (insn) | |
10191 | && GET_MODE (operands[3]) == Pmode" | |
10192 | { | |
10193 | s390_indirect_branch_via_thunk (REGNO (operands[1]), | |
10194 | REGNO (operands[3]), | |
10195 | NULL_RTX, | |
10196 | s390_indirect_branch_type_call); | |
10197 | return ""; | |
10198 | } | |
10199 | [(set_attr "op_type" "RIL") | |
10200 | (set_attr "mnemonic" "brasl") | |
9e8327e3 | 10201 | (set_attr "type" "jsr") |
65b1d8ea AK |
10202 | (set_attr "atype" "agen") |
10203 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10204 | |
fd3cd001 UW |
10205 | ;; |
10206 | ;;- Thread-local storage support. | |
10207 | ;; | |
10208 | ||
f959607b CLT |
10209 | (define_expand "get_thread_pointer<mode>" |
10210 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
10211 | "" | |
c5aa1d12 | 10212 | "") |
fd3cd001 | 10213 | |
f959607b CLT |
10214 | (define_expand "set_thread_pointer<mode>" |
10215 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
10216 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
10217 | "" | |
c5aa1d12 UW |
10218 | "") |
10219 | ||
10220 | (define_insn "*set_tp" | |
ae156f85 | 10221 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
10222 | "" |
10223 | "" | |
10224 | [(set_attr "type" "none") | |
10225 | (set_attr "length" "0")]) | |
c7453384 | 10226 | |
fd3cd001 UW |
10227 | (define_insn "*tls_load_64" |
10228 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 10229 | (unspec:DI [(match_operand:DI 1 "memory_operand" "T") |
fd3cd001 UW |
10230 | (match_operand:DI 2 "" "")] |
10231 | UNSPEC_TLS_LOAD))] | |
10232 | "TARGET_64BIT" | |
d40c829f | 10233 | "lg\t%0,%1%J2" |
9381e3f1 WG |
10234 | [(set_attr "op_type" "RXE") |
10235 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
10236 | |
10237 | (define_insn "*tls_load_31" | |
d3632d41 UW |
10238 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10239 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
10240 | (match_operand:SI 2 "" "")] |
10241 | UNSPEC_TLS_LOAD))] | |
10242 | "!TARGET_64BIT" | |
d3632d41 | 10243 | "@ |
d40c829f UW |
10244 | l\t%0,%1%J2 |
10245 | ly\t%0,%1%J2" | |
9381e3f1 | 10246 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 10247 | (set_attr "type" "load") |
3e4be43f | 10248 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 10249 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 10250 | |
9e8327e3 | 10251 | (define_insn "*bras_tls" |
c19ec8f9 | 10252 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10253 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10254 | (match_operand 2 "const_int_operand" "n"))) | |
10255 | (clobber (match_operand 3 "register_operand" "=r")) | |
10256 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
10257 | "!SIBLING_CALL_P (insn) |
10258 | && TARGET_SMALL_EXEC | |
ed9676cf | 10259 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 10260 | "bras\t%3,%1%J4" |
fd3cd001 | 10261 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10262 | (set_attr "type" "jsr") |
10263 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10264 | |
9e8327e3 | 10265 | (define_insn "*brasl_tls" |
c19ec8f9 | 10266 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10267 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10268 | (match_operand 2 "const_int_operand" "n"))) | |
10269 | (clobber (match_operand 3 "register_operand" "=r")) | |
10270 | (use (match_operand 4 "" ""))] | |
2f7e5a0d | 10271 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10272 | |
ed9676cf | 10273 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10274 | "brasl\t%3,%1%J4" |
10275 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10276 | (set_attr "type" "jsr") |
14cfceb7 IL |
10277 | (set_attr "z196prop" "z196_cracked") |
10278 | (set_attr "relative_long" "yes")]) | |
fd3cd001 | 10279 | |
9e8327e3 | 10280 | (define_insn "*basr_tls" |
c19ec8f9 | 10281 | [(set (match_operand 0 "" "") |
3e4be43f | 10282 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
10283 | (match_operand 2 "const_int_operand" "n"))) |
10284 | (clobber (match_operand 3 "register_operand" "=r")) | |
10285 | (use (match_operand 4 "" ""))] | |
ed9676cf | 10286 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10287 | { |
10288 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10289 | return "basr\t%3,%1%J4"; | |
10290 | else | |
10291 | return "bas\t%3,%a1%J4"; | |
10292 | } | |
10293 | [(set (attr "op_type") | |
10294 | (if_then_else (match_operand 1 "register_operand" "") | |
10295 | (const_string "RR") (const_string "RX"))) | |
10296 | (set_attr "type" "jsr") | |
65b1d8ea AK |
10297 | (set_attr "atype" "agen") |
10298 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10299 | |
e0374221 AS |
10300 | ;; |
10301 | ;;- Atomic operations | |
10302 | ;; | |
10303 | ||
10304 | ; | |
78ce265b | 10305 | ; memory barrier patterns. |
e0374221 AS |
10306 | ; |
10307 | ||
78ce265b RH |
10308 | (define_expand "mem_thread_fence" |
10309 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
10310 | "" | |
10311 | { | |
10312 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
10313 | enough not to require barriers of any kind. */ | |
46b35980 | 10314 | if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) |
78ce265b RH |
10315 | { |
10316 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
10317 | MEM_VOLATILE_P (mem) = 1; | |
10318 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
10319 | } | |
10320 | DONE; | |
e0374221 AS |
10321 | }) |
10322 | ||
78ce265b RH |
10323 | ; Although bcr is superscalar on Z10, this variant will never |
10324 | ; become part of an execution group. | |
a9cc3f58 AK |
10325 | ; With z196 we can make use of the fast-BCR-serialization facility. |
10326 | ; This allows for a slightly faster sync which is sufficient for our | |
10327 | ; purposes. | |
78ce265b | 10328 | (define_insn "mem_thread_fence_1" |
e0374221 | 10329 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 10330 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 10331 | "" |
a9cc3f58 AK |
10332 | { |
10333 | if (TARGET_Z196) | |
10334 | return "bcr\t14,0"; | |
10335 | else | |
10336 | return "bcr\t15,0"; | |
10337 | } | |
10338 | [(set_attr "op_type" "RR") | |
10339 | (set_attr "mnemonic" "bcr_flush") | |
10340 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 10341 | |
78ce265b RH |
10342 | ; |
10343 | ; atomic load/store operations | |
10344 | ; | |
10345 | ||
10346 | ; Atomic loads need not examine the memory model at all. | |
10347 | (define_expand "atomic_load<mode>" | |
10348 | [(match_operand:DINT 0 "register_operand") ;; output | |
10349 | (match_operand:DINT 1 "memory_operand") ;; memory | |
10350 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10351 | "" | |
10352 | { | |
75cc21e2 AK |
10353 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10354 | FAIL; | |
10355 | ||
78ce265b RH |
10356 | if (<MODE>mode == TImode) |
10357 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
10358 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10359 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
10360 | else | |
10361 | emit_move_insn (operands[0], operands[1]); | |
10362 | DONE; | |
10363 | }) | |
10364 | ||
10365 | ; Different from movdi_31 in that we want no splitters. | |
10366 | (define_insn "atomic_loaddi_1" | |
10367 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
10368 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
10369 | UNSPEC_MOVA))] | |
10370 | "!TARGET_ZARCH" | |
10371 | "@ | |
10372 | lm\t%0,%M0,%S1 | |
10373 | lmy\t%0,%M0,%S1 | |
10374 | ld\t%0,%1 | |
10375 | ldy\t%0,%1" | |
10376 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10377 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10378 | (set_attr "type" "lm,lm,floaddf,floaddf")]) |
10379 | ||
10380 | (define_insn "atomic_loadti_1" | |
10381 | [(set (match_operand:TI 0 "register_operand" "=r") | |
3e4be43f | 10382 | (unspec:TI [(match_operand:TI 1 "memory_operand" "T")] |
78ce265b RH |
10383 | UNSPEC_MOVA))] |
10384 | "TARGET_ZARCH" | |
10385 | "lpq\t%0,%1" | |
10386 | [(set_attr "op_type" "RXY") | |
10387 | (set_attr "type" "other")]) | |
10388 | ||
10389 | ; Atomic stores must(?) enforce sequential consistency. | |
10390 | (define_expand "atomic_store<mode>" | |
10391 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
10392 | (match_operand:DINT 1 "register_operand") ;; input | |
10393 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10394 | "" | |
10395 | { | |
46b35980 | 10396 | enum memmodel model = memmodel_from_int (INTVAL (operands[2])); |
78ce265b | 10397 | |
75cc21e2 AK |
10398 | if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) |
10399 | FAIL; | |
10400 | ||
78ce265b RH |
10401 | if (<MODE>mode == TImode) |
10402 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
10403 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10404 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
10405 | else | |
10406 | emit_move_insn (operands[0], operands[1]); | |
46b35980 | 10407 | if (is_mm_seq_cst (model)) |
78ce265b RH |
10408 | emit_insn (gen_mem_thread_fence (operands[2])); |
10409 | DONE; | |
10410 | }) | |
10411 | ||
10412 | ; Different from movdi_31 in that we want no splitters. | |
10413 | (define_insn "atomic_storedi_1" | |
10414 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
10415 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
10416 | UNSPEC_MOVA))] | |
10417 | "!TARGET_ZARCH" | |
10418 | "@ | |
10419 | stm\t%1,%N1,%S0 | |
10420 | stmy\t%1,%N1,%S0 | |
10421 | std %1,%0 | |
10422 | stdy %1,%0" | |
10423 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10424 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10425 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) |
10426 | ||
10427 | (define_insn "atomic_storeti_1" | |
3e4be43f | 10428 | [(set (match_operand:TI 0 "memory_operand" "=T") |
78ce265b RH |
10429 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] |
10430 | UNSPEC_MOVA))] | |
10431 | "TARGET_ZARCH" | |
10432 | "stpq\t%1,%0" | |
10433 | [(set_attr "op_type" "RXY") | |
10434 | (set_attr "type" "other")]) | |
e0374221 AS |
10435 | |
10436 | ; | |
10437 | ; compare and swap patterns. | |
10438 | ; | |
10439 | ||
78ce265b RH |
10440 | (define_expand "atomic_compare_and_swap<mode>" |
10441 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
03db9ab5 DV |
10442 | (match_operand:DINT 1 "nonimmediate_operand");; oldval output |
10443 | (match_operand:DINT 2 "s_operand") ;; memory | |
10444 | (match_operand:DINT 3 "general_operand") ;; expected intput | |
10445 | (match_operand:DINT 4 "general_operand") ;; newval intput | |
78ce265b RH |
10446 | (match_operand:SI 5 "const_int_operand") ;; is_weak |
10447 | (match_operand:SI 6 "const_int_operand") ;; success model | |
10448 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
10449 | "" | |
10450 | { | |
03db9ab5 DV |
10451 | if (GET_MODE_BITSIZE (<MODE>mode) >= 16 |
10452 | && GET_MODE_BITSIZE (<MODE>mode) > MEM_ALIGN (operands[2])) | |
75cc21e2 AK |
10453 | FAIL; |
10454 | ||
03db9ab5 DV |
10455 | s390_expand_cs (<MODE>mode, operands[0], operands[1], operands[2], |
10456 | operands[3], operands[4], INTVAL (operands[5])); | |
10457 | DONE;}) | |
3093f076 | 10458 | |
78ce265b RH |
10459 | (define_expand "atomic_compare_and_swap<mode>_internal" |
10460 | [(parallel | |
10461 | [(set (match_operand:DGPR 0 "register_operand") | |
03db9ab5 | 10462 | (match_operand:DGPR 1 "s_operand")) |
78ce265b RH |
10463 | (set (match_dup 1) |
10464 | (unspec_volatile:DGPR | |
10465 | [(match_dup 1) | |
10466 | (match_operand:DGPR 2 "register_operand") | |
10467 | (match_operand:DGPR 3 "register_operand")] | |
10468 | UNSPECV_CAS)) | |
03db9ab5 DV |
10469 | (set (match_operand 4 "cc_reg_operand") |
10470 | (match_dup 5))])] | |
10471 | "GET_MODE (operands[4]) == CCZmode | |
10472 | || GET_MODE (operands[4]) == CCZ1mode" | |
10473 | { | |
10474 | operands[5] | |
10475 | = gen_rtx_COMPARE (GET_MODE (operands[4]), operands[1], operands[2]); | |
10476 | }) | |
78ce265b RH |
10477 | |
10478 | ; cdsg, csg | |
10479 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
10480 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
bdb57bcb | 10481 | (match_operand:TDI 1 "nonsym_memory_operand" "+S")) |
8006eaa6 | 10482 | (set (match_dup 1) |
78ce265b | 10483 | (unspec_volatile:TDI |
8006eaa6 | 10484 | [(match_dup 1) |
78ce265b RH |
10485 | (match_operand:TDI 2 "register_operand" "0") |
10486 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 | 10487 | UNSPECV_CAS)) |
03db9ab5 DV |
10488 | (set (reg CC_REGNUM) |
10489 | (compare (match_dup 1) (match_dup 2)))] | |
10490 | "TARGET_ZARCH | |
10491 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10492 | "c<td>sg\t%0,%3,%S1" |
10493 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
10494 | (set_attr "type" "sem")]) |
10495 | ||
78ce265b RH |
10496 | ; cds, cdsy |
10497 | (define_insn "*atomic_compare_and_swapdi_2" | |
10498 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
bdb57bcb | 10499 | (match_operand:DI 1 "nonsym_memory_operand" "+Q,S")) |
e0374221 | 10500 | (set (match_dup 1) |
78ce265b RH |
10501 | (unspec_volatile:DI |
10502 | [(match_dup 1) | |
10503 | (match_operand:DI 2 "register_operand" "0,0") | |
10504 | (match_operand:DI 3 "register_operand" "r,r")] | |
10505 | UNSPECV_CAS)) | |
03db9ab5 DV |
10506 | (set (reg CC_REGNUM) |
10507 | (compare (match_dup 1) (match_dup 2)))] | |
10508 | "!TARGET_ZARCH | |
10509 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10510 | "@ |
10511 | cds\t%0,%3,%S1 | |
10512 | cdsy\t%0,%3,%S1" | |
10513 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10514 | (set_attr "cpu_facility" "*,longdisp") |
78ce265b RH |
10515 | (set_attr "type" "sem")]) |
10516 | ||
10517 | ; cs, csy | |
10518 | (define_insn "*atomic_compare_and_swapsi_3" | |
10519 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
bdb57bcb | 10520 | (match_operand:SI 1 "nonsym_memory_operand" "+Q,S")) |
78ce265b RH |
10521 | (set (match_dup 1) |
10522 | (unspec_volatile:SI | |
e0374221 | 10523 | [(match_dup 1) |
78ce265b RH |
10524 | (match_operand:SI 2 "register_operand" "0,0") |
10525 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 10526 | UNSPECV_CAS)) |
03db9ab5 DV |
10527 | (set (reg CC_REGNUM) |
10528 | (compare (match_dup 1) (match_dup 2)))] | |
10529 | "s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10530 | "@ |
10531 | cs\t%0,%3,%S1 | |
10532 | csy\t%0,%3,%S1" | |
10533 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10534 | (set_attr "cpu_facility" "*,longdisp") |
e0374221 AS |
10535 | (set_attr "type" "sem")]) |
10536 | ||
45d18331 AS |
10537 | ; |
10538 | ; Other atomic instruction patterns. | |
10539 | ; | |
10540 | ||
65b1d8ea AK |
10541 | ; z196 load and add, xor, or and and instructions |
10542 | ||
78ce265b RH |
10543 | (define_expand "atomic_fetch_<atomic><mode>" |
10544 | [(match_operand:GPR 0 "register_operand") ;; val out | |
10545 | (ATOMIC_Z196:GPR | |
10546 | (match_operand:GPR 1 "memory_operand") ;; memory | |
10547 | (match_operand:GPR 2 "register_operand")) ;; val in | |
10548 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 10549 | "TARGET_Z196" |
78ce265b | 10550 | { |
75cc21e2 AK |
10551 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10552 | FAIL; | |
10553 | ||
78ce265b RH |
10554 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf |
10555 | (operands[0], operands[1], operands[2])); | |
10556 | DONE; | |
10557 | }) | |
65b1d8ea AK |
10558 | |
10559 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
10560 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
10561 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 10562 | (match_operand:GPR 1 "memory_operand" "+S")) |
78ce265b RH |
10563 | (set (match_dup 1) |
10564 | (unspec_volatile:GPR | |
10565 | [(ATOMIC_Z196:GPR (match_dup 1) | |
10566 | (match_operand:GPR 2 "general_operand" "d"))] | |
10567 | UNSPECV_ATOMIC_OP)) | |
10568 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 10569 | "TARGET_Z196" |
78ce265b RH |
10570 | "la<noxa><g>\t%0,%2,%1" |
10571 | [(set_attr "op_type" "RSY") | |
10572 | (set_attr "type" "sem")]) | |
65b1d8ea | 10573 | |
78ce265b RH |
10574 | ;; For SImode and larger, the optabs.c code will do just fine in |
10575 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
10576 | ;; better by expanding our own loop. | |
65b1d8ea | 10577 | |
78ce265b RH |
10578 | (define_expand "atomic_<atomic><mode>" |
10579 | [(ATOMIC:HQI | |
10580 | (match_operand:HQI 0 "memory_operand") ;; memory | |
10581 | (match_operand:HQI 1 "general_operand")) ;; val in | |
10582 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 10583 | "" |
78ce265b RH |
10584 | { |
10585 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
10586 | operands[1], false); | |
10587 | DONE; | |
10588 | }) | |
45d18331 | 10589 | |
78ce265b RH |
10590 | (define_expand "atomic_fetch_<atomic><mode>" |
10591 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10592 | (ATOMIC:HQI | |
10593 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10594 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10595 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10596 | "" |
78ce265b RH |
10597 | { |
10598 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10599 | operands[2], false); | |
10600 | DONE; | |
10601 | }) | |
10602 | ||
10603 | (define_expand "atomic_<atomic>_fetch<mode>" | |
10604 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10605 | (ATOMIC:HQI | |
10606 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10607 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10608 | (match_operand:SI 3 "const_int_operand")] ;; model | |
10609 | "" | |
10610 | { | |
10611 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10612 | operands[2], true); | |
10613 | DONE; | |
10614 | }) | |
10615 | ||
03db9ab5 DV |
10616 | ;; Pattern to implement atomic_exchange with a compare-and-swap loop. The code |
10617 | ;; generated by the middleend is not good. | |
78ce265b | 10618 | (define_expand "atomic_exchange<mode>" |
03db9ab5 DV |
10619 | [(match_operand:DINT 0 "register_operand") ;; val out |
10620 | (match_operand:DINT 1 "s_operand") ;; memory | |
10621 | (match_operand:DINT 2 "general_operand") ;; val in | |
78ce265b | 10622 | (match_operand:SI 3 "const_int_operand")] ;; model |
45d18331 | 10623 | "" |
78ce265b | 10624 | { |
03db9ab5 DV |
10625 | if (<MODE>mode != QImode |
10626 | && MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)) | |
10627 | FAIL; | |
10628 | if (<MODE>mode == HImode || <MODE>mode == QImode) | |
10629 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], | |
10630 | false); | |
10631 | else if (<MODE>mode == SImode || TARGET_ZARCH) | |
10632 | s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]); | |
10633 | else | |
10634 | FAIL; | |
78ce265b RH |
10635 | DONE; |
10636 | }) | |
45d18331 | 10637 | |
9db1d521 HP |
10638 | ;; |
10639 | ;;- Miscellaneous instructions. | |
10640 | ;; | |
10641 | ||
10642 | ; | |
10643 | ; allocate stack instruction pattern(s). | |
10644 | ; | |
10645 | ||
10646 | (define_expand "allocate_stack" | |
ef44a6ff UW |
10647 | [(match_operand 0 "general_operand" "") |
10648 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 10649 | "TARGET_BACKCHAIN" |
9db1d521 | 10650 | { |
ef44a6ff | 10651 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 10652 | |
ef44a6ff UW |
10653 | emit_move_insn (temp, s390_back_chain_rtx ()); |
10654 | anti_adjust_stack (operands[1]); | |
10655 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 10656 | |
ef44a6ff UW |
10657 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
10658 | DONE; | |
10bbf137 | 10659 | }) |
9db1d521 HP |
10660 | |
10661 | ||
10662 | ; | |
43ab026f | 10663 | ; setjmp instruction pattern. |
9db1d521 HP |
10664 | ; |
10665 | ||
9db1d521 | 10666 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 10667 | [(match_operand 0 "" "")] |
f314b9b1 | 10668 | "flag_pic" |
9db1d521 | 10669 | { |
585539a1 | 10670 | emit_insn (s390_load_got ()); |
c41c1387 | 10671 | emit_use (pic_offset_table_rtx); |
9db1d521 | 10672 | DONE; |
fd7643fb | 10673 | }) |
9db1d521 | 10674 | |
9db1d521 HP |
10675 | ;; These patterns say how to save and restore the stack pointer. We need not |
10676 | ;; save the stack pointer at function level since we are careful to | |
10677 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10678 | ;; when we restore the stack pointer. | |
10679 | ;; | |
10680 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10681 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10682 | ;; save area is a memory location. | |
10683 | ||
10684 | (define_expand "save_stack_function" | |
10685 | [(match_operand 0 "general_operand" "") | |
10686 | (match_operand 1 "general_operand" "")] | |
10687 | "" | |
10688 | "DONE;") | |
10689 | ||
10690 | (define_expand "restore_stack_function" | |
10691 | [(match_operand 0 "general_operand" "") | |
10692 | (match_operand 1 "general_operand" "")] | |
10693 | "" | |
10694 | "DONE;") | |
10695 | ||
10696 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
10697 | [(match_operand 0 "register_operand" "") |
10698 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 10699 | "TARGET_BACKCHAIN" |
9db1d521 | 10700 | { |
ef44a6ff UW |
10701 | rtx temp = gen_reg_rtx (Pmode); |
10702 | ||
10703 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
10704 | emit_move_insn (operands[0], operands[1]); | |
10705 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10706 | ||
10707 | DONE; | |
10bbf137 | 10708 | }) |
9db1d521 HP |
10709 | |
10710 | (define_expand "save_stack_nonlocal" | |
10711 | [(match_operand 0 "memory_operand" "") | |
10712 | (match_operand 1 "register_operand" "")] | |
10713 | "" | |
9db1d521 | 10714 | { |
ef44a6ff UW |
10715 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
10716 | ||
10717 | /* Copy the backchain to the first word, sp to the second and the | |
10718 | literal pool base to the third. */ | |
10719 | ||
9602b6a1 AK |
10720 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
10721 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
10722 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10723 | ||
b3d31392 | 10724 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10725 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 10726 | |
9602b6a1 AK |
10727 | emit_move_insn (save_sp, operands[1]); |
10728 | emit_move_insn (save_bp, base); | |
9db1d521 | 10729 | |
9db1d521 | 10730 | DONE; |
10bbf137 | 10731 | }) |
9db1d521 HP |
10732 | |
10733 | (define_expand "restore_stack_nonlocal" | |
10734 | [(match_operand 0 "register_operand" "") | |
10735 | (match_operand 1 "memory_operand" "")] | |
10736 | "" | |
9db1d521 | 10737 | { |
490ceeb4 | 10738 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 10739 | rtx temp = NULL_RTX; |
9db1d521 | 10740 | |
43ab026f | 10741 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 10742 | literal pool base from the third. */ |
43ab026f | 10743 | |
9602b6a1 AK |
10744 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
10745 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
10746 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10747 | ||
b3d31392 | 10748 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10749 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 10750 | |
9602b6a1 AK |
10751 | emit_move_insn (base, save_bp); |
10752 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
10753 | |
10754 | if (temp) | |
10755 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10756 | ||
c41c1387 | 10757 | emit_use (base); |
9db1d521 | 10758 | DONE; |
10bbf137 | 10759 | }) |
9db1d521 | 10760 | |
7bcebb25 AK |
10761 | (define_expand "exception_receiver" |
10762 | [(const_int 0)] | |
10763 | "" | |
10764 | { | |
10765 | s390_set_has_landing_pad_p (true); | |
10766 | DONE; | |
10767 | }) | |
9db1d521 HP |
10768 | |
10769 | ; | |
10770 | ; nop instruction pattern(s). | |
10771 | ; | |
10772 | ||
10773 | (define_insn "nop" | |
10774 | [(const_int 0)] | |
10775 | "" | |
aad98a61 AK |
10776 | "nopr\t%%r0" |
10777 | [(set_attr "op_type" "RR")]) | |
10778 | ||
10779 | ; non-branch NOPs required for optimizing compare-and-branch patterns | |
10780 | ; on z10 | |
10781 | ||
10782 | (define_insn "nop_lr0" | |
10783 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_0)] | |
10784 | "" | |
d40c829f | 10785 | "lr\t0,0" |
729e750f WG |
10786 | [(set_attr "op_type" "RR") |
10787 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 10788 | |
aad98a61 AK |
10789 | (define_insn "nop_lr1" |
10790 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_1)] | |
d277db6b WG |
10791 | "" |
10792 | "lr\t1,1" | |
10793 | [(set_attr "op_type" "RR")]) | |
10794 | ||
f8af0e30 DV |
10795 | ;;- Undeletable nops (used for hotpatching) |
10796 | ||
10797 | (define_insn "nop_2_byte" | |
10798 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] | |
10799 | "" | |
4bbc8970 | 10800 | "nopr\t%%r0" |
f8af0e30 DV |
10801 | [(set_attr "op_type" "RR")]) |
10802 | ||
10803 | (define_insn "nop_4_byte" | |
10804 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] | |
10805 | "" | |
10806 | "nop\t0" | |
10807 | [(set_attr "op_type" "RX")]) | |
10808 | ||
10809 | (define_insn "nop_6_byte" | |
10810 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] | |
8cc6307c | 10811 | "" |
f8af0e30 | 10812 | "brcl\t0, 0" |
14cfceb7 IL |
10813 | [(set_attr "op_type" "RIL") |
10814 | (set_attr "relative_long" "yes")]) | |
f8af0e30 | 10815 | |
9db1d521 HP |
10816 | |
10817 | ; | |
10818 | ; Special literal pool access instruction pattern(s). | |
10819 | ; | |
10820 | ||
416cf582 UW |
10821 | (define_insn "*pool_entry" |
10822 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
10823 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 10824 | "" |
9db1d521 | 10825 | { |
ef4bddc2 | 10826 | machine_mode mode = GET_MODE (PATTERN (insn)); |
416cf582 | 10827 | unsigned int align = GET_MODE_BITSIZE (mode); |
faeb9bb6 | 10828 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
10829 | return ""; |
10830 | } | |
b628bd8e | 10831 | [(set (attr "length") |
416cf582 | 10832 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 10833 | |
9bb86f41 UW |
10834 | (define_insn "pool_align" |
10835 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
10836 | UNSPECV_POOL_ALIGN)] | |
10837 | "" | |
10838 | ".align\t%0" | |
b628bd8e | 10839 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 10840 | |
9bb86f41 UW |
10841 | (define_insn "pool_section_start" |
10842 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
10843 | "" | |
b929b470 MK |
10844 | { |
10845 | switch_to_section (targetm.asm_out.function_rodata_section | |
10846 | (current_function_decl)); | |
10847 | return ""; | |
10848 | } | |
b628bd8e | 10849 | [(set_attr "length" "0")]) |
b2ccb744 | 10850 | |
9bb86f41 UW |
10851 | (define_insn "pool_section_end" |
10852 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
10853 | "" | |
b929b470 MK |
10854 | { |
10855 | switch_to_section (current_function_section ()); | |
10856 | return ""; | |
10857 | } | |
b628bd8e | 10858 | [(set_attr "length" "0")]) |
b2ccb744 | 10859 | |
5af2f3d3 | 10860 | (define_insn "main_base_64" |
9e8327e3 UW |
10861 | [(set (match_operand 0 "register_operand" "=a") |
10862 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
8cc6307c | 10863 | "GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
10864 | "larl\t%0,%1" |
10865 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 10866 | (set_attr "type" "larl") |
14cfceb7 IL |
10867 | (set_attr "z10prop" "z10_fwd_A1") |
10868 | (set_attr "relative_long" "yes")]) | |
5af2f3d3 UW |
10869 | |
10870 | (define_insn "main_pool" | |
585539a1 UW |
10871 | [(set (match_operand 0 "register_operand" "=a") |
10872 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
10873 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
10874 | { |
10875 | gcc_unreachable (); | |
10876 | } | |
9381e3f1 | 10877 | [(set (attr "type") |
8cc6307c | 10878 | (const_string "larl"))]) |
b2ccb744 | 10879 | |
aee4e0db | 10880 | (define_insn "reload_base_64" |
9e8327e3 UW |
10881 | [(set (match_operand 0 "register_operand" "=a") |
10882 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
8cc6307c | 10883 | "GET_MODE (operands[0]) == Pmode" |
d40c829f | 10884 | "larl\t%0,%1" |
aee4e0db | 10885 | [(set_attr "op_type" "RIL") |
9381e3f1 | 10886 | (set_attr "type" "larl") |
729e750f | 10887 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 10888 | |
aee4e0db | 10889 | (define_insn "pool" |
fd7643fb | 10890 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 10891 | "" |
8d933e31 AS |
10892 | { |
10893 | gcc_unreachable (); | |
10894 | } | |
b628bd8e | 10895 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 10896 | |
4023fb28 UW |
10897 | ;; |
10898 | ;; Insns related to generating the function prologue and epilogue. | |
10899 | ;; | |
10900 | ||
10901 | ||
10902 | (define_expand "prologue" | |
10903 | [(use (const_int 0))] | |
10904 | "" | |
10bbf137 | 10905 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
10906 | |
10907 | (define_expand "epilogue" | |
10908 | [(use (const_int 1))] | |
10909 | "" | |
ed9676cf AK |
10910 | "s390_emit_epilogue (false); DONE;") |
10911 | ||
10912 | (define_expand "sibcall_epilogue" | |
10913 | [(use (const_int 0))] | |
10914 | "" | |
10915 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 10916 | |
177bc204 RS |
10917 | ;; A direct return instruction, without using an epilogue. |
10918 | (define_insn "<code>" | |
10919 | [(ANY_RETURN)] | |
10920 | "s390_can_use_<code>_insn ()" | |
84b4c7b5 AK |
10921 | { |
10922 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
10923 | { | |
10924 | /* The target is always r14 so there is no clobber | |
10925 | of r1 needed for pre z10 targets. */ | |
10926 | s390_indirect_branch_via_thunk (RETURN_REGNUM, | |
10927 | INVALID_REGNUM, | |
10928 | NULL_RTX, | |
10929 | s390_indirect_branch_type_return); | |
10930 | return ""; | |
10931 | } | |
10932 | else | |
10933 | return "br\t%%r14"; | |
10934 | } | |
10935 | [(set (attr "op_type") | |
10936 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10937 | (const_string "RIL") | |
10938 | (const_string "RR"))) | |
10939 | (set (attr "mnemonic") | |
10940 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10941 | (const_string "jg") | |
10942 | (const_string "br"))) | |
177bc204 RS |
10943 | (set_attr "type" "jsr") |
10944 | (set_attr "atype" "agen")]) | |
10945 | ||
84b4c7b5 AK |
10946 | |
10947 | (define_expand "return_use" | |
10948 | [(parallel | |
10949 | [(return) | |
10950 | (use (match_operand 0 "register_operand" "a"))])] | |
10951 | "" | |
10952 | { | |
10953 | if (!TARGET_CPU_Z10 | |
10954 | && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION) | |
10955 | { | |
10956 | if (TARGET_64BIT) | |
10957 | emit_jump_insn (gen_returndi_prez10 (operands[0])); | |
10958 | else | |
10959 | emit_jump_insn (gen_returnsi_prez10 (operands[0])); | |
10960 | DONE; | |
10961 | } | |
10962 | }) | |
10963 | ||
10964 | (define_insn "*return<mode>" | |
4023fb28 | 10965 | [(return) |
84b4c7b5 AK |
10966 | (use (match_operand:P 0 "register_operand" "a"))] |
10967 | "TARGET_CPU_Z10 || !TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" | |
10968 | { | |
10969 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
10970 | { | |
10971 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10972 | INVALID_REGNUM, | |
10973 | NULL_RTX, | |
10974 | s390_indirect_branch_type_return); | |
10975 | return ""; | |
10976 | } | |
10977 | else | |
10978 | return "br\t%0"; | |
10979 | } | |
10980 | [(set (attr "op_type") | |
10981 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10982 | (const_string "RIL") | |
10983 | (const_string "RR"))) | |
10984 | (set (attr "mnemonic") | |
10985 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10986 | (const_string "jg") | |
10987 | (const_string "br"))) | |
10988 | (set_attr "type" "jsr") | |
10989 | (set_attr "atype" "agen")]) | |
10990 | ||
10991 | (define_insn "return<mode>_prez10" | |
10992 | [(return) | |
10993 | (use (match_operand:P 0 "register_operand" "a")) | |
10994 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10995 | "!TARGET_CPU_Z10 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" | |
10996 | { | |
10997 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
10998 | { | |
10999 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
11000 | INVALID_REGNUM, | |
11001 | NULL_RTX, | |
11002 | s390_indirect_branch_type_return); | |
11003 | return ""; | |
11004 | } | |
11005 | else | |
11006 | return "br\t%0"; | |
11007 | } | |
11008 | [(set (attr "op_type") | |
11009 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11010 | (const_string "RIL") | |
11011 | (const_string "RR"))) | |
11012 | (set (attr "mnemonic") | |
11013 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11014 | (const_string "jg") | |
11015 | (const_string "br"))) | |
c7453384 | 11016 | (set_attr "type" "jsr") |
077dab3b | 11017 | (set_attr "atype" "agen")]) |
4023fb28 | 11018 | |
4023fb28 | 11019 | |
c7453384 | 11020 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 11021 | ;; pointer. This is used for compatibility. |
c7453384 EC |
11022 | |
11023 | (define_expand "ptr_extend" | |
11024 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11025 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 11026 | "TARGET_64BIT" |
c7453384 | 11027 | { |
c7453384 EC |
11028 | emit_insn (gen_anddi3 (operands[0], |
11029 | gen_lowpart (DImode, operands[1]), | |
11030 | GEN_INT (0x7fffffff))); | |
c7453384 | 11031 | DONE; |
10bbf137 | 11032 | }) |
4798630c D |
11033 | |
11034 | ;; Instruction definition to expand eh_return macro to support | |
11035 | ;; swapping in special linkage return addresses. | |
11036 | ||
11037 | (define_expand "eh_return" | |
11038 | [(use (match_operand 0 "register_operand" ""))] | |
11039 | "TARGET_TPF" | |
11040 | { | |
11041 | s390_emit_tpf_eh_return (operands[0]); | |
11042 | DONE; | |
11043 | }) | |
11044 | ||
7b8acc34 AK |
11045 | ; |
11046 | ; Stack Protector Patterns | |
11047 | ; | |
11048 | ||
11049 | (define_expand "stack_protect_set" | |
11050 | [(set (match_operand 0 "memory_operand" "") | |
11051 | (match_operand 1 "memory_operand" ""))] | |
11052 | "" | |
11053 | { | |
11054 | #ifdef TARGET_THREAD_SSP_OFFSET | |
11055 | operands[1] | |
11056 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
11057 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
11058 | #endif | |
11059 | if (TARGET_64BIT) | |
11060 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
11061 | else | |
11062 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
11063 | ||
11064 | DONE; | |
11065 | }) | |
11066 | ||
11067 | (define_insn "stack_protect_set<mode>" | |
11068 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
11069 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
11070 | "" | |
11071 | "mvc\t%O0(%G0,%R0),%S1" | |
11072 | [(set_attr "op_type" "SS")]) | |
11073 | ||
11074 | (define_expand "stack_protect_test" | |
11075 | [(set (reg:CC CC_REGNUM) | |
11076 | (compare (match_operand 0 "memory_operand" "") | |
11077 | (match_operand 1 "memory_operand" ""))) | |
11078 | (match_operand 2 "" "")] | |
11079 | "" | |
11080 | { | |
f90b7a5a | 11081 | rtx cc_reg, test; |
7b8acc34 AK |
11082 | #ifdef TARGET_THREAD_SSP_OFFSET |
11083 | operands[1] | |
11084 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
11085 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
11086 | #endif | |
7b8acc34 AK |
11087 | if (TARGET_64BIT) |
11088 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
11089 | else | |
11090 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
11091 | ||
f90b7a5a PB |
11092 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
11093 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
11094 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
11095 | DONE; |
11096 | }) | |
11097 | ||
11098 | (define_insn "stack_protect_test<mode>" | |
11099 | [(set (reg:CCZ CC_REGNUM) | |
11100 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
11101 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
11102 | "" | |
11103 | "clc\t%O0(%G0,%R0),%S1" | |
11104 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
11105 | |
11106 | ; This is used in s390_emit_prologue in order to prevent insns | |
11107 | ; adjusting the stack pointer to be moved over insns writing stack | |
11108 | ; slots using a copy of the stack pointer in a different register. | |
11109 | (define_insn "stack_tie" | |
11110 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
11111 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
11112 | "" | |
11113 | "" | |
11114 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
11115 | |
11116 | ||
82c6f58a AK |
11117 | (define_insn "stack_restore_from_fpr" |
11118 | [(set (reg:DI STACK_REGNUM) | |
11119 | (match_operand:DI 0 "register_operand" "f")) | |
11120 | (clobber (mem:BLK (scratch)))] | |
11121 | "TARGET_Z10" | |
11122 | "lgdr\t%%r15,%0" | |
11123 | [(set_attr "op_type" "RRE")]) | |
11124 | ||
963fc8d0 AK |
11125 | ; |
11126 | ; Data prefetch patterns | |
11127 | ; | |
11128 | ||
11129 | (define_insn "prefetch" | |
3e4be43f UW |
11130 | [(prefetch (match_operand 0 "address_operand" "ZT,X") |
11131 | (match_operand:SI 1 "const_int_operand" " n,n") | |
11132 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
22d72dbc | 11133 | "TARGET_Z10" |
963fc8d0 | 11134 | { |
4fe6dea8 AK |
11135 | switch (which_alternative) |
11136 | { | |
11137 | case 0: | |
4fe6dea8 | 11138 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 11139 | case 1: |
4fe6dea8 AK |
11140 | if (larl_operand (operands[0], Pmode)) |
11141 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
a65593a4 | 11142 | /* fallthrough */ |
4fe6dea8 AK |
11143 | default: |
11144 | ||
11145 | /* This might be reached for symbolic operands with an odd | |
11146 | addend. We simply omit the prefetch for such rare cases. */ | |
11147 | ||
11148 | return ""; | |
11149 | } | |
9381e3f1 | 11150 | } |
22d72dbc AK |
11151 | [(set_attr "type" "load,larl") |
11152 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea | 11153 | (set_attr "z10prop" "z10_super") |
14cfceb7 IL |
11154 | (set_attr "z196prop" "z196_alone") |
11155 | (set_attr "relative_long" "yes")]) | |
07da44ab AK |
11156 | |
11157 | ||
11158 | ; | |
11159 | ; Byte swap instructions | |
11160 | ; | |
11161 | ||
511f5bb1 AK |
11162 | ; FIXME: There is also mvcin but we cannot use it since src and target |
11163 | ; may overlap. | |
50dc4eed | 11164 | ; lrvr, lrv, strv, lrvgr, lrvg, strvg |
07da44ab | 11165 | (define_insn "bswap<mode>2" |
3e4be43f UW |
11166 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") |
11167 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] | |
8cc6307c | 11168 | "" |
07da44ab AK |
11169 | "@ |
11170 | lrv<g>r\t%0,%1 | |
6f5a59d1 AK |
11171 | lrv<g>\t%0,%1 |
11172 | strv<g>\t%1,%0" | |
11173 | [(set_attr "type" "*,load,store") | |
11174 | (set_attr "op_type" "RRE,RXY,RXY") | |
07da44ab | 11175 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 11176 | |
511f5bb1 | 11177 | (define_insn "bswaphi2" |
3e4be43f UW |
11178 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T") |
11179 | (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))] | |
8cc6307c | 11180 | "" |
6f5a59d1 AK |
11181 | "@ |
11182 | # | |
11183 | lrvh\t%0,%1 | |
11184 | strvh\t%1,%0" | |
11185 | [(set_attr "type" "*,load,store") | |
11186 | (set_attr "op_type" "RRE,RXY,RXY") | |
511f5bb1 | 11187 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 11188 | |
6f5a59d1 AK |
11189 | (define_split |
11190 | [(set (match_operand:HI 0 "register_operand" "") | |
11191 | (bswap:HI (match_operand:HI 1 "register_operand" "")))] | |
8cc6307c | 11192 | "" |
6f5a59d1 | 11193 | [(set (match_dup 2) (bswap:SI (match_dup 3))) |
9060e335 | 11194 | (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] |
6f5a59d1 | 11195 | { |
9060e335 | 11196 | operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); |
6f5a59d1 AK |
11197 | operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); |
11198 | }) | |
11199 | ||
11200 | ||
65b1d8ea AK |
11201 | ; |
11202 | ; Population count instruction | |
11203 | ; | |
11204 | ||
11205 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
11206 | ; portions and stores the result in the corresponding bytes in op0. | |
11207 | (define_insn "*popcount<mode>" | |
11208 | [(set (match_operand:INT 0 "register_operand" "=d") | |
11209 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
11210 | (clobber (reg:CC CC_REGNUM))] | |
11211 | "TARGET_Z196" | |
11212 | "popcnt\t%0,%1" | |
11213 | [(set_attr "op_type" "RRE")]) | |
11214 | ||
11215 | (define_expand "popcountdi2" | |
11216 | [; popcnt op0, op1 | |
11217 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
11218 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
11219 | UNSPEC_POPCNT)) | |
11220 | (clobber (reg:CC CC_REGNUM))]) | |
11221 | ; sllg op2, op0, 32 | |
11222 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
11223 | ; agr op0, op2 | |
11224 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11225 | (clobber (reg:CC CC_REGNUM))]) | |
11226 | ; sllg op2, op0, 16 | |
17465c6e | 11227 | (set (match_dup 2) |
65b1d8ea AK |
11228 | (ashift:DI (match_dup 0) (const_int 16))) |
11229 | ; agr op0, op2 | |
11230 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11231 | (clobber (reg:CC CC_REGNUM))]) | |
11232 | ; sllg op2, op0, 8 | |
11233 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
11234 | ; agr op0, op2 | |
11235 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11236 | (clobber (reg:CC CC_REGNUM))]) | |
11237 | ; srlg op0, op0, 56 | |
11238 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
11239 | "TARGET_Z196 && TARGET_64BIT" | |
11240 | "operands[2] = gen_reg_rtx (DImode);") | |
11241 | ||
11242 | (define_expand "popcountsi2" | |
11243 | [; popcnt op0, op1 | |
11244 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
11245 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
11246 | UNSPEC_POPCNT)) | |
11247 | (clobber (reg:CC CC_REGNUM))]) | |
11248 | ; sllk op2, op0, 16 | |
17465c6e | 11249 | (set (match_dup 2) |
65b1d8ea AK |
11250 | (ashift:SI (match_dup 0) (const_int 16))) |
11251 | ; ar op0, op2 | |
11252 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11253 | (clobber (reg:CC CC_REGNUM))]) | |
11254 | ; sllk op2, op0, 8 | |
11255 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
11256 | ; ar op0, op2 | |
11257 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11258 | (clobber (reg:CC CC_REGNUM))]) | |
11259 | ; srl op0, op0, 24 | |
11260 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
11261 | "TARGET_Z196" | |
11262 | "operands[2] = gen_reg_rtx (SImode);") | |
11263 | ||
11264 | (define_expand "popcounthi2" | |
11265 | [; popcnt op0, op1 | |
11266 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
11267 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
11268 | UNSPEC_POPCNT)) | |
11269 | (clobber (reg:CC CC_REGNUM))]) | |
11270 | ; sllk op2, op0, 8 | |
17465c6e | 11271 | (set (match_dup 2) |
65b1d8ea AK |
11272 | (ashift:SI (match_dup 0) (const_int 8))) |
11273 | ; ar op0, op2 | |
11274 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11275 | (clobber (reg:CC CC_REGNUM))]) | |
11276 | ; srl op0, op0, 8 | |
11277 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
11278 | "TARGET_Z196" | |
11279 | "operands[2] = gen_reg_rtx (SImode);") | |
11280 | ||
11281 | (define_expand "popcountqi2" | |
11282 | [; popcnt op0, op1 | |
11283 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
11284 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
11285 | UNSPEC_POPCNT)) | |
11286 | (clobber (reg:CC CC_REGNUM))])] | |
11287 | "TARGET_Z196" | |
11288 | "") | |
11289 | ||
11290 | ;; | |
11291 | ;;- Copy sign instructions | |
11292 | ;; | |
11293 | ||
11294 | (define_insn "copysign<mode>3" | |
11295 | [(set (match_operand:FP 0 "register_operand" "=f") | |
11296 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
11297 | (match_operand:FP 2 "register_operand" "f")] | |
11298 | UNSPEC_COPYSIGN))] | |
11299 | "TARGET_Z196" | |
11300 | "cpsdr\t%0,%2,%1" | |
11301 | [(set_attr "op_type" "RRF") | |
11302 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
11303 | |
11304 | ||
11305 | ;; | |
11306 | ;;- Transactional execution instructions | |
11307 | ;; | |
11308 | ||
11309 | ; This splitter helps combine to make use of CC directly when | |
11310 | ; comparing the integer result of a tbegin builtin with a constant. | |
11311 | ; The unspec is already removed by canonicalize_comparison. So this | |
11312 | ; splitters only job is to turn the PARALLEL into separate insns | |
11313 | ; again. Unfortunately this only works with the very first cc/int | |
11314 | ; compare since combine is not able to deal with data flow across | |
11315 | ; basic block boundaries. | |
11316 | ||
11317 | ; It needs to be an insn pattern as well since combine does not apply | |
11318 | ; the splitter directly. Combine would only use it if it actually | |
11319 | ; would reduce the number of instructions. | |
11320 | (define_insn_and_split "*ccraw_to_int" | |
11321 | [(set (pc) | |
11322 | (if_then_else | |
11323 | (match_operator 0 "s390_eqne_operator" | |
11324 | [(reg:CCRAW CC_REGNUM) | |
11325 | (match_operand 1 "const_int_operand" "")]) | |
11326 | (label_ref (match_operand 2 "" "")) | |
11327 | (pc))) | |
11328 | (set (match_operand:SI 3 "register_operand" "=d") | |
11329 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
11330 | "" | |
11331 | "#" | |
11332 | "" | |
11333 | [(set (match_dup 3) | |
11334 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
11335 | (set (pc) | |
11336 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
11337 | (label_ref (match_dup 2)) | |
11338 | (pc)))] | |
11339 | "") | |
11340 | ||
11341 | ; Non-constrained transaction begin | |
11342 | ||
11343 | (define_expand "tbegin" | |
ee163e72 AK |
11344 | [(match_operand:SI 0 "register_operand" "") |
11345 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11346 | "TARGET_HTM" |
11347 | { | |
11348 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
11349 | DONE; | |
11350 | }) | |
11351 | ||
11352 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
11353 | [(match_operand:SI 0 "register_operand" "") |
11354 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11355 | "TARGET_HTM" |
11356 | { | |
11357 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
11358 | DONE; | |
11359 | }) | |
11360 | ||
11361 | (define_expand "tbegin_retry" | |
ee163e72 AK |
11362 | [(match_operand:SI 0 "register_operand" "") |
11363 | (match_operand:BLK 1 "memory_operand" "") | |
11364 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11365 | "TARGET_HTM" |
11366 | { | |
11367 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
11368 | DONE; | |
11369 | }) | |
11370 | ||
11371 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
11372 | [(match_operand:SI 0 "register_operand" "") |
11373 | (match_operand:BLK 1 "memory_operand" "") | |
11374 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11375 | "TARGET_HTM" |
11376 | { | |
11377 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
11378 | DONE; | |
11379 | }) | |
11380 | ||
c914ac45 AK |
11381 | ; Clobber VRs since they don't get restored |
11382 | (define_insn "tbegin_1_z13" | |
11383 | [(set (reg:CCRAW CC_REGNUM) | |
11384 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] | |
11385 | UNSPECV_TBEGIN)) | |
11386 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11387 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
11388 | (clobber (reg:TI 16)) (clobber (reg:TI 38)) | |
11389 | (clobber (reg:TI 17)) (clobber (reg:TI 39)) | |
11390 | (clobber (reg:TI 18)) (clobber (reg:TI 40)) | |
11391 | (clobber (reg:TI 19)) (clobber (reg:TI 41)) | |
11392 | (clobber (reg:TI 20)) (clobber (reg:TI 42)) | |
11393 | (clobber (reg:TI 21)) (clobber (reg:TI 43)) | |
11394 | (clobber (reg:TI 22)) (clobber (reg:TI 44)) | |
11395 | (clobber (reg:TI 23)) (clobber (reg:TI 45)) | |
11396 | (clobber (reg:TI 24)) (clobber (reg:TI 46)) | |
11397 | (clobber (reg:TI 25)) (clobber (reg:TI 47)) | |
11398 | (clobber (reg:TI 26)) (clobber (reg:TI 48)) | |
11399 | (clobber (reg:TI 27)) (clobber (reg:TI 49)) | |
11400 | (clobber (reg:TI 28)) (clobber (reg:TI 50)) | |
11401 | (clobber (reg:TI 29)) (clobber (reg:TI 51)) | |
11402 | (clobber (reg:TI 30)) (clobber (reg:TI 52)) | |
11403 | (clobber (reg:TI 31)) (clobber (reg:TI 53))] | |
11404 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11405 | ; not supposed to be used for immediates (see genpreds.c). | |
11406 | "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11407 | "tbegin\t%1,%x0" | |
11408 | [(set_attr "op_type" "SIL")]) | |
11409 | ||
5a3fe9b6 AK |
11410 | (define_insn "tbegin_1" |
11411 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 11412 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 11413 | UNSPECV_TBEGIN)) |
2561451d AK |
11414 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
11415 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
11416 | (clobber (reg:DF 16)) |
11417 | (clobber (reg:DF 17)) | |
11418 | (clobber (reg:DF 18)) | |
11419 | (clobber (reg:DF 19)) | |
11420 | (clobber (reg:DF 20)) | |
11421 | (clobber (reg:DF 21)) | |
11422 | (clobber (reg:DF 22)) | |
11423 | (clobber (reg:DF 23)) | |
11424 | (clobber (reg:DF 24)) | |
11425 | (clobber (reg:DF 25)) | |
11426 | (clobber (reg:DF 26)) | |
11427 | (clobber (reg:DF 27)) | |
11428 | (clobber (reg:DF 28)) | |
11429 | (clobber (reg:DF 29)) | |
11430 | (clobber (reg:DF 30)) | |
11431 | (clobber (reg:DF 31))] | |
11432 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11433 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
11434 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
11435 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11436 | [(set_attr "op_type" "SIL")]) |
11437 | ||
11438 | ; Same as above but without the FPR clobbers | |
11439 | (define_insn "tbegin_nofloat_1" | |
11440 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
11441 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
11442 | UNSPECV_TBEGIN)) | |
11443 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11444 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
11445 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11446 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11447 | [(set_attr "op_type" "SIL")]) |
11448 | ||
11449 | ||
11450 | ; Constrained transaction begin | |
11451 | ||
11452 | (define_expand "tbeginc" | |
11453 | [(set (reg:CCRAW CC_REGNUM) | |
11454 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
11455 | UNSPECV_TBEGINC))] | |
11456 | "TARGET_HTM" | |
11457 | "") | |
11458 | ||
11459 | (define_insn "*tbeginc_1" | |
11460 | [(set (reg:CCRAW CC_REGNUM) | |
11461 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
11462 | UNSPECV_TBEGINC))] | |
11463 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11464 | "tbeginc\t0,%x0" | |
11465 | [(set_attr "op_type" "SIL")]) | |
11466 | ||
11467 | ; Transaction end | |
11468 | ||
11469 | (define_expand "tend" | |
11470 | [(set (reg:CCRAW CC_REGNUM) | |
11471 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 11472 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
11473 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
11474 | "TARGET_HTM" | |
11475 | "") | |
11476 | ||
11477 | (define_insn "*tend_1" | |
11478 | [(set (reg:CCRAW CC_REGNUM) | |
11479 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
11480 | "TARGET_HTM" | |
11481 | "tend" | |
11482 | [(set_attr "op_type" "S")]) | |
11483 | ||
11484 | ; Transaction abort | |
11485 | ||
11486 | (define_expand "tabort" | |
eae48192 | 11487 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")] |
5a3fe9b6 AK |
11488 | UNSPECV_TABORT)] |
11489 | "TARGET_HTM && operands != NULL" | |
11490 | { | |
11491 | if (CONST_INT_P (operands[0]) | |
11492 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
11493 | { | |
f3981e7e | 11494 | error ("invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC |
5a3fe9b6 AK |
11495 | ". Values in range 0 through 255 are reserved.", |
11496 | INTVAL (operands[0])); | |
11497 | FAIL; | |
11498 | } | |
11499 | }) | |
11500 | ||
11501 | (define_insn "*tabort_1" | |
eae48192 | 11502 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")] |
5a3fe9b6 AK |
11503 | UNSPECV_TABORT)] |
11504 | "TARGET_HTM && operands != NULL" | |
11505 | "tabort\t%Y0" | |
11506 | [(set_attr "op_type" "S")]) | |
11507 | ||
eae48192 AK |
11508 | (define_insn "*tabort_1_plus" |
11509 | [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a") | |
11510 | (match_operand:SI 1 "const_int_operand" "J"))] | |
11511 | UNSPECV_TABORT)] | |
11512 | "TARGET_HTM && operands != NULL | |
11513 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")" | |
11514 | "tabort\t%1(%0)" | |
11515 | [(set_attr "op_type" "S")]) | |
11516 | ||
5a3fe9b6 AK |
11517 | ; Transaction extract nesting depth |
11518 | ||
11519 | (define_insn "etnd" | |
11520 | [(set (match_operand:SI 0 "register_operand" "=d") | |
11521 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
11522 | "TARGET_HTM" | |
11523 | "etnd\t%0" | |
11524 | [(set_attr "op_type" "RRE")]) | |
11525 | ||
11526 | ; Non-transactional store | |
11527 | ||
11528 | (define_insn "ntstg" | |
3e4be43f | 11529 | [(set (match_operand:DI 0 "memory_operand" "=T") |
5a3fe9b6 AK |
11530 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] |
11531 | UNSPECV_NTSTG))] | |
11532 | "TARGET_HTM" | |
11533 | "ntstg\t%1,%0" | |
11534 | [(set_attr "op_type" "RXY")]) | |
11535 | ||
11536 | ; Transaction perform processor assist | |
11537 | ||
11538 | (define_expand "tx_assist" | |
2561451d AK |
11539 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
11540 | (reg:SI GPR0_REGNUM) | |
291a9e98 | 11541 | (const_int PPA_TX_ABORT)] |
5a3fe9b6 AK |
11542 | UNSPECV_PPA)] |
11543 | "TARGET_HTM" | |
2561451d | 11544 | "") |
5a3fe9b6 AK |
11545 | |
11546 | (define_insn "*ppa" | |
11547 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
11548 | (match_operand:SI 1 "register_operand" "d") | |
11549 | (match_operand 2 "const_int_operand" "I")] | |
11550 | UNSPECV_PPA)] | |
291a9e98 | 11551 | "(TARGET_ZEC12 || TARGET_HTM) && INTVAL (operands[2]) < 16" |
2561451d | 11552 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 11553 | [(set_attr "op_type" "RRF")]) |
004f64e1 AK |
11554 | |
11555 | ||
11556 | ; Set and get floating point control register | |
11557 | ||
3af82a61 | 11558 | (define_insn "sfpc" |
004f64e1 AK |
11559 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] |
11560 | UNSPECV_SFPC)] | |
11561 | "TARGET_HARD_FLOAT" | |
11562 | "sfpc\t%0") | |
11563 | ||
3af82a61 | 11564 | (define_insn "efpc" |
004f64e1 AK |
11565 | [(set (match_operand:SI 0 "register_operand" "=d") |
11566 | (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] | |
11567 | "TARGET_HARD_FLOAT" | |
11568 | "efpc\t%0") | |
3af82a61 AK |
11569 | |
11570 | ||
11571 | ; Load count to block boundary | |
11572 | ||
11573 | (define_insn "lcbb" | |
11574 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3e4be43f | 11575 | (unspec:SI [(match_operand 1 "address_operand" "ZR") |
3af82a61 AK |
11576 | (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) |
11577 | (clobber (reg:CC CC_REGNUM))] | |
11578 | "TARGET_Z13" | |
9a36359e | 11579 | "lcbb\t%0,%a1,%b2" |
3af82a61 | 11580 | [(set_attr "op_type" "VRX")]) |
4cb4721f MK |
11581 | |
11582 | ; Handle -fsplit-stack. | |
11583 | ||
11584 | (define_expand "split_stack_prologue" | |
11585 | [(const_int 0)] | |
11586 | "" | |
11587 | { | |
11588 | s390_expand_split_stack_prologue (); | |
11589 | DONE; | |
11590 | }) | |
11591 | ||
11592 | ;; If there are operand 0 bytes available on the stack, jump to | |
11593 | ;; operand 1. | |
11594 | ||
11595 | (define_expand "split_stack_space_check" | |
11596 | [(set (pc) (if_then_else | |
11597 | (ltu (minus (reg 15) | |
11598 | (match_operand 0 "register_operand")) | |
11599 | (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) | |
11600 | (label_ref (match_operand 1)) | |
11601 | (pc)))] | |
11602 | "" | |
11603 | { | |
11604 | /* Offset from thread pointer to __private_ss. */ | |
11605 | int psso = TARGET_64BIT ? 0x38 : 0x20; | |
11606 | rtx tp = s390_get_thread_pointer (); | |
11607 | rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); | |
11608 | rtx reg = gen_reg_rtx (Pmode); | |
11609 | rtx cc; | |
11610 | if (TARGET_64BIT) | |
11611 | emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); | |
11612 | else | |
11613 | emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); | |
11614 | cc = s390_emit_compare (GT, reg, guard); | |
11615 | s390_emit_jump (operands[1], cc); | |
11616 | ||
11617 | DONE; | |
11618 | }) | |
11619 | ||
11620 | ;; __morestack parameter block for split stack prologue. Parameters are: | |
11621 | ;; parameter block label, label to be called by __morestack, frame size, | |
11622 | ;; stack parameter size. | |
11623 | ||
11624 | (define_insn "split_stack_data" | |
11625 | [(unspec_volatile [(match_operand 0 "" "X") | |
11626 | (match_operand 1 "" "X") | |
11627 | (match_operand 2 "const_int_operand" "X") | |
11628 | (match_operand 3 "const_int_operand" "X")] | |
11629 | UNSPECV_SPLIT_STACK_DATA)] | |
8cc6307c | 11630 | "" |
4cb4721f MK |
11631 | { |
11632 | switch_to_section (targetm.asm_out.function_rodata_section | |
11633 | (current_function_decl)); | |
11634 | ||
11635 | if (TARGET_64BIT) | |
11636 | output_asm_insn (".align\t8", operands); | |
11637 | else | |
11638 | output_asm_insn (".align\t4", operands); | |
11639 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
11640 | CODE_LABEL_NUMBER (operands[0])); | |
11641 | if (TARGET_64BIT) | |
11642 | { | |
11643 | output_asm_insn (".quad\t%2", operands); | |
11644 | output_asm_insn (".quad\t%3", operands); | |
11645 | output_asm_insn (".quad\t%1-%0", operands); | |
11646 | } | |
11647 | else | |
11648 | { | |
11649 | output_asm_insn (".long\t%2", operands); | |
11650 | output_asm_insn (".long\t%3", operands); | |
11651 | output_asm_insn (".long\t%1-%0", operands); | |
11652 | } | |
11653 | ||
11654 | switch_to_section (current_function_section ()); | |
11655 | return ""; | |
11656 | } | |
11657 | [(set_attr "length" "0")]) | |
11658 | ||
11659 | ||
11660 | ;; A jg with minimal fuss for use in split stack prologue. | |
11661 | ||
11662 | (define_expand "split_stack_call" | |
11663 | [(match_operand 0 "bras_sym_operand" "X") | |
11664 | (match_operand 1 "" "")] | |
8cc6307c | 11665 | "" |
4cb4721f MK |
11666 | { |
11667 | if (TARGET_64BIT) | |
11668 | emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1])); | |
11669 | else | |
11670 | emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1])); | |
11671 | DONE; | |
11672 | }) | |
11673 | ||
11674 | (define_insn "split_stack_call_<mode>" | |
11675 | [(set (pc) (label_ref (match_operand 1 "" ""))) | |
11676 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11677 | (reg:P 1)] | |
11678 | UNSPECV_SPLIT_STACK_CALL))] | |
8cc6307c | 11679 | "" |
4cb4721f MK |
11680 | "jg\t%0" |
11681 | [(set_attr "op_type" "RIL") | |
11682 | (set_attr "type" "branch")]) | |
11683 | ||
11684 | ;; Also a conditional one. | |
11685 | ||
11686 | (define_expand "split_stack_cond_call" | |
11687 | [(match_operand 0 "bras_sym_operand" "X") | |
11688 | (match_operand 1 "" "") | |
11689 | (match_operand 2 "" "")] | |
8cc6307c | 11690 | "" |
4cb4721f MK |
11691 | { |
11692 | if (TARGET_64BIT) | |
11693 | emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2])); | |
11694 | else | |
11695 | emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2])); | |
11696 | DONE; | |
11697 | }) | |
11698 | ||
11699 | (define_insn "split_stack_cond_call_<mode>" | |
11700 | [(set (pc) | |
11701 | (if_then_else | |
11702 | (match_operand 1 "" "") | |
11703 | (label_ref (match_operand 2 "" "")) | |
11704 | (pc))) | |
11705 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11706 | (reg:P 1)] | |
11707 | UNSPECV_SPLIT_STACK_CALL))] | |
8cc6307c | 11708 | "" |
4cb4721f MK |
11709 | "jg%C1\t%0" |
11710 | [(set_attr "op_type" "RIL") | |
11711 | (set_attr "type" "branch")]) | |
539405d5 AK |
11712 | |
11713 | (define_insn "osc_break" | |
11714 | [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)] | |
11715 | "" | |
11716 | "bcr\t7,%%r0" | |
11717 | [(set_attr "op_type" "RR")]) | |
291a9e98 AK |
11718 | |
11719 | (define_expand "speculation_barrier" | |
11720 | [(unspec_volatile [(reg:SI GPR0_REGNUM) | |
11721 | (reg:SI GPR0_REGNUM) | |
11722 | (const_int PPA_OOO_BARRIER)] | |
11723 | UNSPECV_PPA)] | |
11724 | "TARGET_ZEC12" | |
11725 | "") |