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PR c++/79797 - ICE with self-reference in array DMI.
[thirdparty/gcc.git] / gcc / config / s390 / vx-builtins.md
CommitLineData
3af82a61 1;;- Instruction patterns for the System z vector facility builtins.
cbe34bb5 2;; Copyright (C) 2015-2017 Free Software Foundation, Inc.
3af82a61
AK		 3;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
4
5;; This file is part of GCC.
6
7;; GCC is free software; you can redistribute it and/or modify it under
8;; the terms of the GNU General Public License as published by the Free
9;; Software Foundation; either version 3, or (at your option) any later
10;; version.
11
12;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15;; for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21; The patterns in this file are enabled with -mzvector
22
23(define_mode_iterator V_HW_64 [V2DI V2DF])
24(define_mode_iterator V_HW_32_64 [V4SI V2DI V2DF])
25(define_mode_iterator VI_HW_SD [V4SI V2DI])
26(define_mode_iterator V_HW_HSD [V8HI V4SI V2DI V2DF])
3af82a61
AK		 27
28; The element type of the vector with floating point modes translated
29; to int modes of the same size.
90573e88
AK		 30(define_mode_attr non_vec_int[(V1QI "QI") (V2QI "QI") (V4QI "QI") (V8QI "QI") (V16QI "QI")
31 (V1HI "HI") (V2HI "HI") (V4HI "HI") (V8HI "HI")
32 (V1SI "SI") (V2SI "SI") (V4SI "SI")
33 (V1DI "DI") (V2DI "DI")
34 (V1SF "SI") (V2SF "SI") (V4SF "SI")
35 (V1DF "DI") (V2DF "DI")])
3af82a61
AK		 36
37; Condition code modes generated by int comparisons
a6a2b532 38(define_mode_iterator VICMP [CCVEQ CCVIH CCVIHU])
3af82a61
AK		 39
40; Comparisons supported by the vec_cmp* builtins
41(define_code_iterator intcmp [eq gt gtu ge geu lt ltu le leu])
42(define_code_iterator fpcmp [eq gt ge lt le])
43
44; Comparisons supported by the vec_all/any* builtins
45(define_code_iterator intcmpcc [eq ne gt ge lt le gtu geu ltu leu])
46(define_code_iterator fpcmpcc [eq ne gt ge unle unlt lt le])
47
48; Flags for vector string instructions (vfae all 4, vfee only ZS and CS, vstrc all 4)
49(define_constants
50 [(VSTRING_FLAG_IN 8) ; invert result
51 (VSTRING_FLAG_RT 4) ; result type
52 (VSTRING_FLAG_ZS 2) ; zero search
53 (VSTRING_FLAG_CS 1)]) ; condition code set
54
55; Rounding modes as being used for e.g. VFI
56(define_constants
57 [(VEC_RND_CURRENT 0)
58 (VEC_RND_NEAREST_AWAY_FROM_ZERO 1)
59 (VEC_RND_SHORT_PREC 3)
60 (VEC_RND_NEAREST_TO_EVEN 4)
61 (VEC_RND_TO_ZERO 5)
62 (VEC_RND_TO_INF 6)
63 (VEC_RND_TO_MINF 7)])
64
65
66; Vector gather element
67
50dc4eed 68; vgef, vgeg
3af82a61 69(define_insn "vec_gather_element<mode>"
e970b4b0
AK		 70 [(set (match_operand:V_HW_32_64 0 "register_operand" "=v")
71 (unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand" "0")
72 (match_operand:<tointvec> 2 "register_operand" "v")
3e4be43f 73 (match_operand:BLK 3 "memory_operand" "R")
e970b4b0 74 (match_operand:QI 4 "const_mask_operand" "C")]
3af82a61 75 UNSPEC_VEC_GATHER))]
e970b4b0 76 "TARGET_VX && UINTVAL (operands[4]) < GET_MODE_NUNITS (<V_HW_32_64:MODE>mode)"
3af82a61
AK		 77 "vge<bhfgq>\t%0,%O3(%v2,%R3),%b4"
78 [(set_attr "op_type" "VRV")])
79
80(define_expand "vec_genmask<mode>"
81 [(match_operand:VI_HW 0 "register_operand" "=v")
e970b4b0
AK		 82 (match_operand:QI 1 "const_int_operand" "C")
83 (match_operand:QI 2 "const_int_operand" "C")]
3af82a61
AK		 84 "TARGET_VX"
85{
86 int nunits = GET_MODE_NUNITS (<VI_HW:MODE>mode);
87 int bitlen = GET_MODE_UNIT_BITSIZE (<VI_HW:MODE>mode);
88 /* To bit little endian style. */
89 int end = bitlen - 1 - INTVAL (operands[1]);
90 int start = bitlen - 1 - INTVAL (operands[2]);
91 rtx const_vec[16];
92 int i;
93 unsigned HOST_WIDE_INT mask;
94 bool swapped_p = false;
95
96 if (start > end)
97 {
98 i = start - 1; start = end + 1; end = i;
99 swapped_p = true;
100 }
101 if (end == 63)
102 mask = HOST_WIDE_INT_M1U;
103 else
104 mask = (HOST_WIDE_INT_1U << (end + 1)) - 1;
105
106 mask &= ~((HOST_WIDE_INT_1U << start) - 1);
107
108 if (swapped_p)
109 mask = ~mask;
110
111 for (i = 0; i < nunits; i++)
112 const_vec[i] = GEN_INT (trunc_int_for_mode (mask,
113 GET_MODE_INNER (<VI_HW:MODE>mode)));
114
115 emit_insn (gen_rtx_SET (operands[0],
116 gen_rtx_CONST_VECTOR (<VI_HW:MODE>mode,
117 gen_rtvec_v (nunits, const_vec))));
118 DONE;
119})
120
121(define_expand "vec_genbytemaskv16qi"
122 [(match_operand:V16QI 0 "register_operand" "")
e970b4b0
AK		 123 (match_operand:HI 1 "const_int_operand" "")]
124 "TARGET_VX"
3af82a61
AK		 125{
126 int i;
127 unsigned mask = 0x8000;
128 rtx const_vec[16];
406fde6e 129 unsigned HOST_WIDE_INT byte_mask = UINTVAL (operands[1]);
3af82a61
AK		 130
131 for (i = 0; i < 16; i++)
132 {
133 if (mask & byte_mask)
134 const_vec[i] = constm1_rtx;
135 else
136 const_vec[i] = const0_rtx;
137 mask = mask >> 1;
138 }
139 emit_insn (gen_rtx_SET (operands[0],
140 gen_rtx_CONST_VECTOR (V16QImode,
141 gen_rtvec_v (16, const_vec))));
142 DONE;
143})
144
145(define_expand "vec_splats<mode>"
146 [(set (match_operand:V_HW 0 "register_operand" "")
147 (vec_duplicate:V_HW (match_operand:<non_vec> 1 "general_operand" "")))]
148 "TARGET_VX")
149
150(define_expand "vec_insert<mode>"
151 [(set (match_operand:V_HW 0 "register_operand" "")
152 (unspec:V_HW [(match_operand:<non_vec> 2 "register_operand" "")
dd95128b 153 (match_operand:SI 3 "nonmemory_operand" "")
3af82a61
AK		 154 (match_operand:V_HW 1 "register_operand" "")]
155 UNSPEC_VEC_SET))]
156 "TARGET_VX"
157 "")
158
159; This is vec_set + modulo arithmetic on the element selector (op 2)
160(define_expand "vec_promote<mode>"
161 [(set (match_operand:V_HW 0 "register_operand" "")
162 (unspec:V_HW [(match_operand:<non_vec> 1 "register_operand" "")
dd95128b 163 (match_operand:SI 2 "nonmemory_operand" "")
3af82a61
AK		 164 (match_dup 0)]
165 UNSPEC_VEC_SET))]
166 "TARGET_VX"
167 "")
168
169; vec_extract is also an RTL standard name -> vector.md
170
50dc4eed 171; vllezb, vllezh, vllezf, vllezg
3af82a61
AK		 172(define_insn "vec_insert_and_zero<mode>"
173 [(set (match_operand:V_HW 0 "register_operand" "=v")
3e4be43f 174 (unspec:V_HW [(match_operand:<non_vec> 1 "memory_operand" "R")]
3af82a61
AK		 175 UNSPEC_VEC_INSERT_AND_ZERO))]
176 "TARGET_VX"
177 "vllez<bhfgq>\t%v0,%1"
178 [(set_attr "op_type" "VRX")])
179
180(define_insn "vlbb"
e970b4b0 181 [(set (match_operand:V16QI 0 "register_operand" "=v")
3e4be43f 182 (unspec:V16QI [(match_operand:BLK 1 "memory_operand" "R")
e970b4b0 183 (match_operand:QI 2 "const_mask_operand" "C")]
3af82a61 184 UNSPEC_VEC_LOAD_BNDRY))]
e970b4b0 185 "TARGET_VX && UINTVAL (operands[2]) < 7"
3af82a61
AK		 186 "vlbb\t%v0,%1,%2"
187 [(set_attr "op_type" "VRX")])
188
189; FIXME: The following two patterns might using vec_merge. But what is
190; the canonical form: (vec_select (vec_merge op0 op1)) or (vec_merge
191; (vec_select op0) (vec_select op1)
50dc4eed 192; vmrhb, vmrhh, vmrhf, vmrhg
3af82a61
AK		 193(define_insn "vec_mergeh<mode>"
194 [(set (match_operand:V_HW 0 "register_operand" "=v")
195 (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
196 (match_operand:V_HW 2 "register_operand" "v")]
197 UNSPEC_VEC_MERGEH))]
198 "TARGET_VX"
199 "vmrh<bhfgq>\t%v0,%1,%2"
200 [(set_attr "op_type" "VRR")])
201
50dc4eed 202; vmrlb, vmrlh, vmrlf, vmrlg
3af82a61
AK		 203(define_insn "vec_mergel<mode>"
204 [(set (match_operand:V_HW 0 "register_operand" "=v")
205 (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
206 (match_operand:V_HW 2 "register_operand" "v")]
207 UNSPEC_VEC_MERGEL))]
208 "TARGET_VX"
209 "vmrl<bhfgq>\t%v0,%1,%2"
210 [(set_attr "op_type" "VRR")])
211
212
213; Vector pack
214
50dc4eed 215; vpkh, vpkf, vpkg
3af82a61
AK		 216(define_insn "vec_pack<mode>"
217 [(set (match_operand:<vec_half> 0 "register_operand" "=v")
218 (unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand" "v")
219 (match_operand:VI_HW_HSD 2 "register_operand" "v")]
220 UNSPEC_VEC_PACK))]
221 "TARGET_VX"
222 "vpk<bhfgq>\t%v0,%v1,%v2"
223 [(set_attr "op_type" "VRR")])
224
225
226; Vector pack saturate
227
50dc4eed 228; vpksh, vpksf, vpksg
3af82a61
AK		 229(define_insn "vec_packs<mode>"
230 [(set (match_operand:<vec_half> 0 "register_operand" "=v")
231 (unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand" "v")
232 (match_operand:VI_HW_HSD 2 "register_operand" "v")]
233 UNSPEC_VEC_PACK_SATURATE))]
234 "TARGET_VX"
235 "vpks<bhfgq>\t%v0,%v1,%v2"
236 [(set_attr "op_type" "VRR")])
237
238
239; This is vec_packs_cc + loading cc into a caller specified memory location.
240(define_expand "vec_packs_cc<mode>"
241 [(parallel
242 [(set (reg:CCRAW CC_REGNUM)
243 (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "")
244 (match_operand:VI_HW_HSD 2 "register_operand" "")]
245 UNSPEC_VEC_PACK_SATURATE_GENCC))
246 (set (match_operand:<vec_half> 0 "register_operand" "")
247 (unspec:<vec_half> [(match_dup 1) (match_dup 2)]
248 UNSPEC_VEC_PACK_SATURATE_CC))])
249 (set (match_dup 4)
250 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
251 (set (match_operand:SI 3 "memory_operand" "")
252 (match_dup 4))]
253 "TARGET_VX"
254{
255 operands[4] = gen_reg_rtx (SImode);
256})
257
50dc4eed 258; vpksh, vpksf, vpksg
3af82a61
AK		 259(define_insn "*vec_packs_cc<mode>"
260 [(set (reg:CCRAW CC_REGNUM)
261 (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "v")
262 (match_operand:VI_HW_HSD 2 "register_operand" "v")]
263 UNSPEC_VEC_PACK_SATURATE_GENCC))
264 (set (match_operand:<vec_half> 0 "register_operand" "=v")
265 (unspec:<vec_half> [(match_dup 1) (match_dup 2)]
266 UNSPEC_VEC_PACK_SATURATE_CC))]
267 "TARGET_VX"
268 "vpks<bhfgq>s\t%v0,%v1,%v2"
269 [(set_attr "op_type" "VRR")])
270
271
272; Vector pack logical saturate
273
50dc4eed 274; vpklsh, vpklsf, vpklsg
3af82a61
AK		 275(define_insn "vec_packsu<mode>"
276 [(set (match_operand:<vec_half> 0 "register_operand" "=v")
277 (unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand" "v")
278 (match_operand:VI_HW_HSD 2 "register_operand" "v")]
279 UNSPEC_VEC_PACK_UNSIGNED_SATURATE))]
280 "TARGET_VX"
281 "vpkls<bhfgq>\t%v0,%v1,%v2"
282 [(set_attr "op_type" "VRR")])
283
284; Emulate saturate unsigned pack on signed operands.
285; Zero out negative elements and continue with the unsigned saturating pack.
286(define_expand "vec_packsu_u<mode>"
287 [(set (match_operand:<vec_half> 0 "register_operand" "=v")
288 (unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand" "v")
289 (match_operand:VI_HW_HSD 2 "register_operand" "v")]
290 UNSPEC_VEC_PACK_UNSIGNED_SATURATE))]
291 "TARGET_VX"
292{
293 rtx null_vec = CONST0_RTX(<MODE>mode);
294 machine_mode half_mode;
295 switch (<MODE>mode)
296 {
297 case V8HImode: half_mode = V16QImode; break;
298 case V4SImode: half_mode = V8HImode; break;
299 case V2DImode: half_mode = V4SImode; break;
300 default: gcc_unreachable ();
301 }
302 s390_expand_vcond (operands[1], operands[1], null_vec,
303 GE, operands[1], null_vec);
304 s390_expand_vcond (operands[2], operands[2], null_vec,
305 GE, operands[2], null_vec);
306 emit_insn (gen_rtx_SET (operands[0],
307 gen_rtx_UNSPEC (half_mode,
308 gen_rtvec (2, operands[1], operands[2]),
309 UNSPEC_VEC_PACK_UNSIGNED_SATURATE)));
310 DONE;
311})
312
313; This is vec_packsu_cc + loading cc into a caller specified memory location.
314; FIXME: The reg to target mem copy should be issued by reload?!
315(define_expand "vec_packsu_cc<mode>"
316 [(parallel
317 [(set (reg:CCRAW CC_REGNUM)
318 (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "")
319 (match_operand:VI_HW_HSD 2 "register_operand" "")]
320 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC))
321 (set (match_operand:<vec_half> 0 "register_operand" "")
322 (unspec:<vec_half> [(match_dup 1) (match_dup 2)]
323 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC))])
324 (set (match_dup 4)
325 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
326 (set (match_operand:SI 3 "memory_operand" "")
327 (match_dup 4))]
328 "TARGET_VX"
329{
330 operands[4] = gen_reg_rtx (SImode);
331})
332
50dc4eed 333; vpklsh, vpklsf, vpklsg
3af82a61
AK		 334(define_insn "*vec_packsu_cc<mode>"
335 [(set (reg:CCRAW CC_REGNUM)
336 (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "v")
337 (match_operand:VI_HW_HSD 2 "register_operand" "v")]
338 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC))
339 (set (match_operand:<vec_half> 0 "register_operand" "=v")
340 (unspec:<vec_half> [(match_dup 1) (match_dup 2)]
341 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC))]
342 "TARGET_VX"
343 "vpkls<bhfgq>s\t%v0,%v1,%v2"
344 [(set_attr "op_type" "VRR")])
345
346
347; Vector permute
348
349; vec_perm is also RTL standard name, but we can only use it for V16QI
350
351(define_insn "vec_zperm<mode>"
352 [(set (match_operand:V_HW_HSD 0 "register_operand" "=v")
353 (unspec:V_HW_HSD [(match_operand:V_HW_HSD 1 "register_operand" "v")
354 (match_operand:V_HW_HSD 2 "register_operand" "v")
355 (match_operand:V16QI 3 "register_operand" "v")]
356 UNSPEC_VEC_PERM))]
357 "TARGET_VX"
358 "vperm\t%v0,%v1,%v2,%v3"
359 [(set_attr "op_type" "VRR")])
360
361(define_expand "vec_permi<mode>"
e970b4b0
AK		 362 [(set (match_operand:V_HW_64 0 "register_operand" "")
363 (unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand" "")
364 (match_operand:V_HW_64 2 "register_operand" "")
365 (match_operand:QI 3 "const_mask_operand" "")]
3af82a61
AK		 366 UNSPEC_VEC_PERMI))]
367 "TARGET_VX"
368{
369 HOST_WIDE_INT val = INTVAL (operands[3]);
370 operands[3] = GEN_INT ((val & 1) | (val & 2) << 1);
371})
372
373(define_insn "*vec_permi<mode>"
e970b4b0
AK		 374 [(set (match_operand:V_HW_64 0 "register_operand" "=v")
375 (unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand" "v")
376 (match_operand:V_HW_64 2 "register_operand" "v")
377 (match_operand:QI 3 "const_mask_operand" "C")]
3af82a61 378 UNSPEC_VEC_PERMI))]
e970b4b0 379 "TARGET_VX && (UINTVAL (operands[3]) & 10) == 0"
3af82a61
AK		 380 "vpdi\t%v0,%v1,%v2,%b3"
381 [(set_attr "op_type" "VRR")])
382
383
384; Vector replicate
385
386
387; Replicate from vector element
388(define_expand "vec_splat<mode>"
389 [(set (match_operand:V_HW 0 "register_operand" "")
390 (vec_duplicate:V_HW (vec_select:<non_vec>
391 (match_operand:V_HW 1 "register_operand" "")
392 (parallel
e970b4b0 393 [(match_operand:QI 2 "const_mask_operand" "")]))))]
3af82a61
AK		 394 "TARGET_VX")
395
396; Vector scatter element
397
398; vscef, vsceg
399
99924e7a 400; A 64 bit target address generated from 32 bit elements
3af82a61
AK		 401(define_insn "vec_scatter_elementv4si_DI"
402 [(set (mem:SI
403 (plus:DI (zero_extend:DI
e970b4b0
AK		 404 (unspec:SI [(match_operand:V4SI 1 "register_operand" "v")
405 (match_operand:QI 3 "const_mask_operand" "C")]
3af82a61 406 UNSPEC_VEC_EXTRACT))
e970b4b0
AK		 407 (match_operand:SI 2 "address_operand" "ZQ")))
408 (unspec:SI [(match_operand:V4SI 0 "register_operand" "v")
3af82a61 409 (match_dup 3)] UNSPEC_VEC_EXTRACT))]
e970b4b0 410 "TARGET_VX && TARGET_64BIT && UINTVAL (operands[3]) < 4"
3af82a61
AK		 411 "vscef\t%v0,%O2(%v1,%R2),%3"
412 [(set_attr "op_type" "VRV")])
413
414; A 31 bit target address is generated from 64 bit elements
50dc4eed 415; vsceg
3af82a61
AK		 416(define_insn "vec_scatter_element<V_HW_64:mode>_SI"
417 [(set (mem:<non_vec>
418 (plus:SI (subreg:SI
e970b4b0
AK		 419 (unspec:<non_vec_int> [(match_operand:V_HW_64 1 "register_operand" "v")
420 (match_operand:QI 3 "const_mask_operand" "C")]
3af82a61 421 UNSPEC_VEC_EXTRACT) 4)
e970b4b0
AK		 422 (match_operand:SI 2 "address_operand" "ZQ")))
423 (unspec:<non_vec> [(match_operand:V_HW_64 0 "register_operand" "v")
3af82a61 424 (match_dup 3)] UNSPEC_VEC_EXTRACT))]
e970b4b0 425 "TARGET_VX && !TARGET_64BIT && UINTVAL (operands[3]) < GET_MODE_NUNITS (<V_HW_64:MODE>mode)"
af77d1df 426 "vsce<V_HW_64:bhfgq>\t%v0,%O2(%v1,%R2),%3"
3af82a61
AK		 427 [(set_attr "op_type" "VRV")])
428
99924e7a 429; Element size and target address size is the same
50dc4eed 430; vscef, vsceg
3af82a61
AK		 431(define_insn "vec_scatter_element<mode>_<non_vec_int>"
432 [(set (mem:<non_vec>
433 (plus:<non_vec_int> (unspec:<non_vec_int>
e970b4b0
AK		 434 [(match_operand:<tointvec> 1 "register_operand" "v")
435 (match_operand:QI 3 "const_mask_operand" "C")]
3af82a61 436 UNSPEC_VEC_EXTRACT)
e970b4b0
AK		 437 (match_operand:DI 2 "address_operand" "ZQ")))
438 (unspec:<non_vec> [(match_operand:V_HW_32_64 0 "register_operand" "v")
3af82a61 439 (match_dup 3)] UNSPEC_VEC_EXTRACT))]
e970b4b0 440 "TARGET_VX && UINTVAL (operands[3]) < GET_MODE_NUNITS (<V_HW_32_64:MODE>mode)"
af77d1df 441 "vsce<bhfgq>\t%v0,%O2(%v1,%R2),%3"
3af82a61
AK		 442 [(set_attr "op_type" "VRV")])
443
444; Depending on the address size we have to expand a different pattern.
445; This however cannot be represented in s390-builtins.def so we do the
446; multiplexing here in the expander.
447(define_expand "vec_scatter_element<V_HW_32_64:mode>"
448 [(match_operand:V_HW_32_64 0 "register_operand" "")
449 (match_operand:<tointvec> 1 "register_operand" "")
450 (match_operand 2 "address_operand" "")
e970b4b0 451 (match_operand:QI 3 "const_mask_operand" "")]
3af82a61
AK		 452 "TARGET_VX"
453{
454 if (TARGET_64BIT)
455 {
456 PUT_MODE (operands[2], DImode);
457 emit_insn (
458 gen_vec_scatter_element<V_HW_32_64:mode>_DI (operands[0], operands[1],
459 operands[2], operands[3]));
460 }
461 else
462 {
463 PUT_MODE (operands[2], SImode);
464 emit_insn (
465 gen_vec_scatter_element<V_HW_32_64:mode>_SI (operands[0], operands[1],
466 operands[2], operands[3]));
467 }
468 DONE;
469})
470
471
472; Vector select
473
474; Operand 3 selects bits from either OP1 (0) or OP2 (1)
475
476; Comparison operator should not matter as long as we always use the same ?!
477
478; Operands 1 and 2 are swapped in order to match the altivec builtin.
479; If operand 3 is a const_int bitmask this would be vec_merge
480(define_expand "vec_sel<mode>"
481 [(set (match_operand:V_HW 0 "register_operand" "")
482 (if_then_else:V_HW
483 (eq (match_operand:<tointvec> 3 "register_operand" "")
484 (match_dup 4))
485 (match_operand:V_HW 2 "register_operand" "")
486 (match_operand:V_HW 1 "register_operand" "")))]
487 "TARGET_VX"
488{
489 operands[4] = CONST0_RTX (<tointvec>mode);
490})
491
492
493; Vector sign extend to doubleword
494
495; Sign extend of right most vector element to respective double-word
50dc4eed 496; vsegb, vsegh, vsegf
3af82a61
AK		 497(define_insn "vec_extend<mode>"
498 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
499 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
500 UNSPEC_VEC_EXTEND))]
501 "TARGET_VX"
502 "vseg<bhfgq>\t%v0,%1"
503 [(set_attr "op_type" "VRR")])
504
505
506; Vector store with length
507
508; Store bytes in OP1 from OP0 with the highest indexed byte to be
509; stored from OP0 given by OP2
510(define_insn "vstl<mode>"
511 [(set (match_operand:BLK 2 "memory_operand" "=Q")
512 (unspec:BLK [(match_operand:V 0 "register_operand" "v")
513 (match_operand:SI 1 "register_operand" "d")]
514 UNSPEC_VEC_STORE_LEN))]
515 "TARGET_VX"
516 "vstl\t%v0,%1,%2"
517 [(set_attr "op_type" "VRS")])
518
519
520; Vector unpack high
521
522; vuphb, vuphh, vuphf
523(define_insn "vec_unpackh<mode>"
524 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
525 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
526 UNSPEC_VEC_UNPACKH))]
527 "TARGET_VX"
528 "vuph<bhfgq>\t%v0,%v1"
529 [(set_attr "op_type" "VRR")])
530
531; vuplhb, vuplhh, vuplhf
532(define_insn "vec_unpackh_l<mode>"
533 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
534 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
535 UNSPEC_VEC_UNPACKH_L))]
536 "TARGET_VX"
537 "vuplh<bhfgq>\t%v0,%v1"
538 [(set_attr "op_type" "VRR")])
539
540
541; Vector unpack low
542
543; vuplb, vuplhw, vuplf
544(define_insn "vec_unpackl<mode>"
545 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
546 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
547 UNSPEC_VEC_UNPACKL))]
548 "TARGET_VX"
549 "vupl<bhfgq><w>\t%v0,%v1"
550 [(set_attr "op_type" "VRR")])
551
552; vupllb, vupllh, vupllf
553(define_insn "vec_unpackl_l<mode>"
554 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
555 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
556 UNSPEC_VEC_UNPACKL_L))]
557 "TARGET_VX"
558 "vupll<bhfgq>\t%v0,%v1"
559 [(set_attr "op_type" "VRR")])
560
561
562; Vector add
563
3af82a61
AK		 564; Vector add compute carry
565
50dc4eed 566; vaccb, vacch, vaccf, vaccg, vaccq
2d71f118
AK		 567(define_insn "vacc<bhfgq>_<mode>"
568 [(set (match_operand:VIT_HW 0 "register_operand" "=v")
569 (unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "%v")
570 (match_operand:VIT_HW 2 "register_operand" "v")]
571 UNSPEC_VEC_ADDC))]
3af82a61
AK		 572 "TARGET_VX"
573 "vacc<bhfgq>\t%v0,%v1,%v2"
574 [(set_attr "op_type" "VRR")])
575
3af82a61
AK		 576; Vector add with carry
577
2d71f118
AK		 578(define_insn "vacq"
579 [(set (match_operand:TI 0 "register_operand" "=v")
580 (unspec:TI [(match_operand:TI 1 "register_operand" "%v")
581 (match_operand:TI 2 "register_operand" "v")
582 (match_operand:TI 3 "register_operand" "v")]
583 UNSPEC_VEC_ADDE_U128))]
3af82a61
AK		 584 "TARGET_VX"
585 "vacq\t%v0,%v1,%v2,%v3"
586 [(set_attr "op_type" "VRR")])
587
588
589; Vector add with carry compute carry
590
2d71f118
AK		 591(define_insn "vacccq"
592 [(set (match_operand:TI 0 "register_operand" "=v")
593 (unspec:TI [(match_operand:TI 1 "register_operand" "%v")
594 (match_operand:TI 2 "register_operand" "v")
595 (match_operand:TI 3 "register_operand" "v")]
596 UNSPEC_VEC_ADDEC_U128))]
3af82a61
AK		 597 "TARGET_VX"
598 "vacccq\t%v0,%v1,%v2,%v3"
599 [(set_attr "op_type" "VRR")])
600
601
602; Vector and
603
604; The following two patterns allow mixed mode and's as required for the intrinsics.
605(define_insn "and_av2df3"
606 [(set (match_operand:V2DF 0 "register_operand" "=v")
607 (and:V2DF (subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0)
608 (match_operand:V2DF 2 "register_operand" "v")))]
609 "TARGET_VX"
610 "vn\t%v0,%v1,%v2"
611 [(set_attr "op_type" "VRR")])
612
613(define_insn "and_cv2df3"
614 [(set (match_operand:V2DF 0 "register_operand" "=v")
615 (and:V2DF (match_operand:V2DF 1 "register_operand" "v")
616 (subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0)))]
617 "TARGET_VX"
618 "vn\t%v0,%v1,%v2"
619 [(set_attr "op_type" "VRR")])
620
621
622; Vector and with complement
623
624; vnc
625(define_insn "vec_andc<mode>3"
626 [(set (match_operand:VT_HW 0 "register_operand" "=v")
627 (and:VT_HW (not:VT_HW (match_operand:VT_HW 2 "register_operand" "v"))
628 (match_operand:VT_HW 1 "register_operand" "v")))]
629 "TARGET_VX"
630 "vnc\t%v0,%v1,%v2"
631 [(set_attr "op_type" "VRR")])
632
633; The following two patterns allow mixed mode and's as required for the intrinsics.
634(define_insn "vec_andc_av2df3"
635 [(set (match_operand:V2DF 0 "register_operand" "=v")
636 (and:V2DF (not:V2DF (match_operand:V2DF 2 "register_operand" "v"))
637 (subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0)))]
638
639 "TARGET_VX"
640 "vnc\t%v0,%v1,%v2"
641 [(set_attr "op_type" "VRR")])
642
643(define_insn "vec_andc_cv2df3"
644 [(set (match_operand:V2DF 0 "register_operand" "=v")
645 (and:V2DF (not:V2DF (subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0))
646 (match_operand:V2DF 1 "register_operand" "v")))]
647 "TARGET_VX"
648 "vnc\t%v0,%v1,%v2"
649 [(set_attr "op_type" "VRR")])
650
651
652; Vector average
653
50dc4eed 654; vavgb, vavgh, vavgf, vavgg
3af82a61
AK		 655(define_insn "vec_avg<mode>"
656 [(set (match_operand:VI_HW 0 "register_operand" "=v")
d9128d88 657 (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v")
3af82a61
AK		 658 (match_operand:VI_HW 2 "register_operand" "v")]
659 UNSPEC_VEC_AVG))]
660 "TARGET_VX"
661 "vavg<bhfgq>\t%v0,%v1,%v2"
662 [(set_attr "op_type" "VRR")])
663
664; Vector average logical
665
50dc4eed 666; vavglb, vavglh, vavglf, vavglg
3af82a61
AK		 667(define_insn "vec_avgu<mode>"
668 [(set (match_operand:VI_HW 0 "register_operand" "=v")
d9128d88 669 (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v")
3af82a61
AK		 670 (match_operand:VI_HW 2 "register_operand" "v")]
671 UNSPEC_VEC_AVGU))]
672 "TARGET_VX"
673 "vavgl<bhfgq>\t%v0,%v1,%v2"
674 [(set_attr "op_type" "VRR")])
675
676
677; Vector checksum
678
679(define_insn "vec_checksum"
680 [(set (match_operand:V4SI 0 "register_operand" "=v")
681 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
682 (match_operand:V4SI 2 "register_operand" "v")]
683 UNSPEC_VEC_CHECKSUM))]
684 "TARGET_VX"
685 "vcksm\t%v0,%v1,%v2"
686 [(set_attr "op_type" "VRR")])
687
688;;
689;; Vector compare
690;;
691
692; vec_all/any int compares
693
694(define_expand "vec_all_<intcmpcc:code><VI_HW:mode>"
695 [(match_operand:SI 0 "register_operand" "")
696 (intcmpcc (match_operand:VI_HW 1 "register_operand" "")
697 (match_operand:VI_HW 2 "register_operand" ""))]
698 "TARGET_VX"
699{
700 s390_expand_vec_compare_cc (operands[0],
701 <intcmpcc:CODE>,
702 operands[1],
703 operands[2],
704 true);
705 DONE;
706})
707
708(define_expand "vec_any_<intcmpcc:code><VI_HW:mode>"
709 [(match_operand:SI 0 "register_operand" "")
710 (intcmpcc (match_operand:VI_HW 1 "register_operand" "")
711 (match_operand:VI_HW 2 "register_operand" ""))]
712 "TARGET_VX"
713{
714 s390_expand_vec_compare_cc (operands[0],
715 <intcmpcc:CODE>,
716 operands[1],
717 operands[2],
718 false);
719 DONE;
720})
721
722; vec_all/any fp compares
723
724(define_expand "vec_all_<fpcmpcc:code>v2df"
725 [(match_operand:SI 0 "register_operand" "")
726 (fpcmpcc (match_operand:V2DF 1 "register_operand" "")
727 (match_operand:V2DF 2 "register_operand" ""))]
728 "TARGET_VX"
729{
730 s390_expand_vec_compare_cc (operands[0],
731 <fpcmpcc:CODE>,
732 operands[1],
733 operands[2],
734 true);
735 DONE;
736})
737
738(define_expand "vec_any_<fpcmpcc:code>v2df"
739 [(match_operand:SI 0 "register_operand" "")
740 (fpcmpcc (match_operand:V2DF 1 "register_operand" "")
741 (match_operand:V2DF 2 "register_operand" ""))]
742 "TARGET_VX"
743{
744 s390_expand_vec_compare_cc (operands[0],
745 <fpcmpcc:CODE>,
746 operands[1],
747 operands[2],
748 false);
749 DONE;
750})
751
752
753; Compare without generating CC
754
755(define_expand "vec_cmp<intcmp:code><VI_HW:mode>"
756 [(set (match_operand:VI_HW 0 "register_operand" "=v")
757 (intcmp:VI_HW (match_operand:VI_HW 1 "register_operand" "v")
758 (match_operand:VI_HW 2 "register_operand" "v")))]
759 "TARGET_VX"
760{
761 s390_expand_vec_compare (operands[0], <intcmp:CODE>, operands[1], operands[2]);
762 DONE;
763})
764
765(define_expand "vec_cmp<fpcmp:code>v2df"
766 [(set (match_operand:V2DI 0 "register_operand" "=v")
767 (fpcmp:V2DI (match_operand:V2DF 1 "register_operand" "v")
768 (match_operand:V2DF 2 "register_operand" "v")))]
769 "TARGET_VX"
770{
771 s390_expand_vec_compare (operands[0], <fpcmp:CODE>, operands[1], operands[2]);
772 DONE;
773})
774
775
776; Vector count leading zeros
777
778; vec_cntlz -> clz
779; vec_cnttz -> ctz
780
781; Vector xor
782
783; vec_xor -> xor
784
785; The following two patterns allow mixed mode xor's as required for the intrinsics.
786(define_insn "xor_av2df3"
787 [(set (match_operand:V2DF 0 "register_operand" "=v")
788 (xor:V2DF (subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0)
789 (match_operand:V2DF 2 "register_operand" "v")))]
790 "TARGET_VX"
791 "vx\t%v0,%v1,%v2"
792 [(set_attr "op_type" "VRR")])
793
794(define_insn "xor_cv2df3"
795 [(set (match_operand:V2DF 0 "register_operand" "=v")
796 (xor:V2DF (match_operand:V2DF 1 "register_operand" "v")
797 (subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0)))]
798 "TARGET_VX"
799 "vx\t%v0,%v1,%v2"
800 [(set_attr "op_type" "VRR")])
801
802
803; Vector Galois field multiply sum
804
50dc4eed 805; vgfmb, vgfmh, vgfmf
3af82a61
AK		 806(define_insn "vec_gfmsum<mode>"
807 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
808 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
809 (match_operand:VI_HW_QHS 2 "register_operand" "v")]
810 UNSPEC_VEC_GFMSUM))]
811 "TARGET_VX"
812 "vgfm<bhfgq>\t%v0,%v1,%v2"
813 [(set_attr "op_type" "VRR")])
814
815(define_insn "vec_gfmsum_128"
816 [(set (match_operand:V16QI 0 "register_operand" "=v")
817 (unspec:V16QI [(match_operand:V2DI 1 "register_operand" "v")
818 (match_operand:V2DI 2 "register_operand" "v")]
819 UNSPEC_VEC_GFMSUM_128))]
820 "TARGET_VX"
821 "vgfmg\t%v0,%v1,%v2"
822 [(set_attr "op_type" "VRR")])
823
50dc4eed 824; vgfmab, vgfmah, vgfmaf
3af82a61
AK		 825(define_insn "vec_gfmsum_accum<mode>"
826 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
827 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")
828 (match_operand:VI_HW_QHS 2 "register_operand" "v")
829 (match_operand:<vec_double> 3 "register_operand" "v")]
830 UNSPEC_VEC_GFMSUM_ACCUM))]
831 "TARGET_VX"
832 "vgfma<bhfgq>\t%v0,%v1,%v2,%v3"
833 [(set_attr "op_type" "VRR")])
834
835(define_insn "vec_gfmsum_accum_128"
836 [(set (match_operand:V16QI 0 "register_operand" "=v")
837 (unspec:V16QI [(match_operand:V2DI 1 "register_operand" "v")
838 (match_operand:V2DI 2 "register_operand" "v")
839 (match_operand:V16QI 3 "register_operand" "v")]
840 UNSPEC_VEC_GFMSUM_ACCUM_128))]
841 "TARGET_VX"
842 "vgfmag\t%v0,%v1,%v2,%v3"
843 [(set_attr "op_type" "VRR")])
844
845
846; FIXME: vec_neg ?
847
848; Vector load positive: vec_abs -> abs
849; Vector maximum vec_max -> smax, logical vec_max -> umax
850; Vector maximum vec_min -> smin, logical vec_min -> umin
851
852
853; Vector multiply and add high
854
855; vec_mladd -> vec_vmal
856; vmalb, vmalh, vmalf, vmalg
857(define_insn "vec_vmal<mode>"
47b653bd 858 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
d9128d88
AK		 859 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
860 (match_operand:VI_HW_QHS 2 "register_operand" "v")
861 (match_operand:VI_HW_QHS 3 "register_operand" "v")]
47b653bd 862 UNSPEC_VEC_VMAL))]
3af82a61
AK		 863 "TARGET_VX"
864 "vmal<bhfgq><w>\t%v0,%v1,%v2,%v3"
865 [(set_attr "op_type" "VRR")])
866
867; vec_mhadd -> vec_vmah/vec_vmalh
868
869; vmahb; vmahh, vmahf, vmahg
870(define_insn "vec_vmah<mode>"
47b653bd 871 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
d9128d88
AK		 872 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
873 (match_operand:VI_HW_QHS 2 "register_operand" "v")
874 (match_operand:VI_HW_QHS 3 "register_operand" "v")]
47b653bd 875 UNSPEC_VEC_VMAH))]
3af82a61
AK		 876 "TARGET_VX"
877 "vmah<bhfgq>\t%v0,%v1,%v2,%v3"
878 [(set_attr "op_type" "VRR")])
879
880; vmalhb; vmalhh, vmalhf, vmalhg
881(define_insn "vec_vmalh<mode>"
47b653bd 882 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
d9128d88
AK		 883 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
884 (match_operand:VI_HW_QHS 2 "register_operand" "v")
885 (match_operand:VI_HW_QHS 3 "register_operand" "v")]
47b653bd 886 UNSPEC_VEC_VMALH))]
3af82a61
AK		 887 "TARGET_VX"
888 "vmalh<bhfgq>\t%v0,%v1,%v2,%v3"
889 [(set_attr "op_type" "VRR")])
890
891; vec_meadd -> vec_vmae/vec_vmale
892
893; vmaeb; vmaeh, vmaef, vmaeg
894(define_insn "vec_vmae<mode>"
895 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
d9128d88
AK		 896 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
897 (match_operand:VI_HW_QHS 2 "register_operand" "v")
3af82a61
AK		 898 (match_operand:<vec_double> 3 "register_operand" "v")]
899 UNSPEC_VEC_VMAE))]
900 "TARGET_VX"
901 "vmae<bhfgq>\t%v0,%v1,%v2,%v3"
902 [(set_attr "op_type" "VRR")])
903
904; vmaleb; vmaleh, vmalef, vmaleg
905(define_insn "vec_vmale<mode>"
906 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
d9128d88 907 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
3af82a61
AK		 908 (match_operand:VI_HW_QHS 2 "register_operand" "v")
909 (match_operand:<vec_double> 3 "register_operand" "v")]
910 UNSPEC_VEC_VMALE))]
911 "TARGET_VX"
912 "vmale<bhfgq>\t%v0,%v1,%v2,%v3"
913 [(set_attr "op_type" "VRR")])
914
915; vec_moadd -> vec_vmao/vec_vmalo
916
917; vmaob; vmaoh, vmaof, vmaog
918(define_insn "vec_vmao<mode>"
919 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
d9128d88 920 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
3af82a61
AK		 921 (match_operand:VI_HW_QHS 2 "register_operand" "v")
922 (match_operand:<vec_double> 3 "register_operand" "v")]
923 UNSPEC_VEC_VMAO))]
924 "TARGET_VX"
925 "vmao<bhfgq>\t%v0,%v1,%v2,%v3"
926 [(set_attr "op_type" "VRR")])
927
928; vmalob; vmaloh, vmalof, vmalog
929(define_insn "vec_vmalo<mode>"
930 [(set (match_operand:<vec_double> 0 "register_operand" "=v")
931 (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")
932 (match_operand:VI_HW_QHS 2 "register_operand" "v")
933 (match_operand:<vec_double> 3 "register_operand" "v")]
934 UNSPEC_VEC_VMALO))]
935 "TARGET_VX"
936 "vmalo<bhfgq>\t%v0,%v1,%v2,%v3"
937 [(set_attr "op_type" "VRR")])
938
939
940; Vector multiply high
941
942; vec_mulh -> vec_smulh/vec_umulh
943
944; vmhb, vmhh, vmhf
945(define_insn "vec_smulh<mode>"
946 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
d9128d88 947 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
3af82a61
AK		 948 (match_operand:VI_HW_QHS 2 "register_operand" "v")]
949 UNSPEC_VEC_SMULT_HI))]
950 "TARGET_VX"
951 "vmh<bhfgq>\t%v0,%v1,%v2"
952 [(set_attr "op_type" "VRR")])
953
954; vmlhb, vmlhh, vmlhf
955(define_insn "vec_umulh<mode>"
956 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
d9128d88 957 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
3af82a61
AK		 958 (match_operand:VI_HW_QHS 2 "register_operand" "v")]
959 UNSPEC_VEC_UMULT_HI))]
960 "TARGET_VX"
961 "vmlh<bhfgq>\t%v0,%v1,%v2"
962 [(set_attr "op_type" "VRR")])
963
964
965; Vector multiply low
966
967; vec_mule -> vec_widen_umult_even/vec_widen_smult_even
968; vec_mulo -> vec_widen_umult_odd/vec_widen_smult_odd
969
970
971; Vector nor
972
973(define_insn "vec_nor<mode>3"
974 [(set (match_operand:VT_HW 0 "register_operand" "=v")
d9128d88 975 (not:VT_HW (ior:VT_HW (match_operand:VT_HW 1 "register_operand" "%v")
3af82a61
AK		 976 (match_operand:VT_HW 2 "register_operand" "v"))))]
977 "TARGET_VX"
978 "vno\t%v0,%v1,%v2"
979 [(set_attr "op_type" "VRR")])
980
981; The following two patterns allow mixed mode and's as required for the intrinsics.
982(define_insn "vec_nor_av2df3"
983 [(set (match_operand:V2DF 0 "register_operand" "=v")
984 (not:V2DF (ior:V2DF (subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0)
985 (match_operand:V2DF 2 "register_operand" "v"))))]
986 "TARGET_VX"
987 "vno\t%v0,%v1,%v2"
988 [(set_attr "op_type" "VRR")])
989
990(define_insn "vec_nor_cv2df3"
991 [(set (match_operand:V2DF 0 "register_operand" "=v")
992 (not:V2DF (ior:V2DF (match_operand:V2DF 1 "register_operand" "v")
993 (subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0))))]
994 "TARGET_VX"
995 "vno\t%v0,%v1,%v2"
996 [(set_attr "op_type" "VRR")])
997
998
999; Vector or
1000
1001; The following two patterns allow mixed mode or's as required for the intrinsics.
1002(define_insn "ior_av2df3"
1003 [(set (match_operand:V2DF 0 "register_operand" "=v")
1004 (ior:V2DF (subreg:V2DF (match_operand:V2DI 1 "register_operand" "v") 0)
1005 (match_operand:V2DF 2 "register_operand" "v")))]
1006 "TARGET_VX"
1007 "vo\t%v0,%v1,%v2"
1008 [(set_attr "op_type" "VRR")])
1009
1010(define_insn "ior_cv2df3"
1011 [(set (match_operand:V2DF 0 "register_operand" "=v")
1012 (ior:V2DF (match_operand:V2DF 1 "register_operand" "v")
1013 (subreg:V2DF (match_operand:V2DI 2 "register_operand" "v") 0)))]
1014 "TARGET_VX"
1015 "vo\t%v0,%v1,%v2"
1016 [(set_attr "op_type" "VRR")])
1017
1018
1019; Vector population count vec_popcnt -> popcount
1020; Vector element rotate left logical vec_rl -> vrotl, vec_rli -> rot
1021
1022; Vector element rotate and insert under mask
1023
1024; verimb, verimh, verimf, verimg
1025(define_insn "verim<mode>"
1026 [(set (match_operand:VI_HW 0 "register_operand" "=v")
1027 (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "0")
1028 (match_operand:VI_HW 2 "register_operand" "v")
1029 (match_operand:VI_HW 3 "register_operand" "v")
e970b4b0 1030 (match_operand:QI 4 "const_int_operand" "C")]
3af82a61
AK		 1031 UNSPEC_VEC_RL_MASK))]
1032 "TARGET_VX"
1033 "verim<bhfgq>\t%v0,%v2,%v3,%b4"
1034 [(set_attr "op_type" "VRI")])
1035
1036
1037; Vector shift left
1038
1039(define_insn "vec_sll<VI_HW:mode><VI_HW_QHS:mode>"
1040 [(set (match_operand:VI_HW 0 "register_operand" "=v")
1041 (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v")
1042 (match_operand:VI_HW_QHS 2 "register_operand" "v")]
1043 UNSPEC_VEC_SLL))]
1044 "TARGET_VX"
1045 "vsl\t%v0,%v1,%v2"
1046 [(set_attr "op_type" "VRR")])
1047
1048
1049; Vector shift left by byte
1050
1051(define_insn "vec_slb<mode>"
1052 [(set (match_operand:V_HW 0 "register_operand" "=v")
1053 (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
1054 (match_operand:<tointvec> 2 "register_operand" "v")]
1055 UNSPEC_VEC_SLB))]
1056 "TARGET_VX"
1057 "vslb\t%v0,%v1,%v2"
1058 [(set_attr "op_type" "VRR")])
1059
1060
1061; Vector shift left double by byte
1062
1063(define_insn "vec_sld<mode>"
1064 [(set (match_operand:V_HW 0 "register_operand" "=v")
1065 (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
1066 (match_operand:V_HW 2 "register_operand" "v")
e970b4b0 1067 (match_operand:QI 3 "const_int_operand" "C")]
3af82a61
AK		 1068 UNSPEC_VEC_SLDB))]
1069 "TARGET_VX"
1070 "vsldb\t%v0,%v1,%v2,%b3"
1071 [(set_attr "op_type" "VRI")])
1072
1073(define_expand "vec_sldw<mode>"
1074 [(set (match_operand:V_HW 0 "register_operand" "")
1075 (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "")
1076 (match_operand:V_HW 2 "register_operand" "")
e970b4b0 1077 (match_operand:QI 3 "const_int_operand" "")]
3af82a61
AK		 1078 UNSPEC_VEC_SLDB))]
1079 "TARGET_VX"
1080{
1081 operands[3] = GEN_INT (INTVAL (operands[3]) << 2);
1082})
1083
1084; Vector shift right arithmetic
1085
1086(define_insn "vec_sral<VI_HW:mode><VI_HW_QHS:mode>"
1087 [(set (match_operand:VI_HW 0 "register_operand" "=v")
1088 (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v")
1089 (match_operand:VI_HW_QHS 2 "register_operand" "v")]
1090 UNSPEC_VEC_SRAL))]
1091 "TARGET_VX"
1092 "vsra\t%v0,%v1,%v2"
1093 [(set_attr "op_type" "VRR")])
1094
1095
1096; Vector shift right arithmetic by byte
1097
1098(define_insn "vec_srab<mode>"
1099 [(set (match_operand:V_HW 0 "register_operand" "=v")
1100 (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
1101 (match_operand:<tointvec> 2 "register_operand" "v")]
1102 UNSPEC_VEC_SRAB))]
1103 "TARGET_VX"
1104 "vsrab\t%v0,%v1,%v2"
1105 [(set_attr "op_type" "VRR")])
1106
1107
1108; Vector shift right logical
1109
1110(define_insn "vec_srl<VI_HW:mode><VI_HW_QHS:mode>"
1111 [(set (match_operand:VI_HW 0 "register_operand" "=v")
1112 (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v")
1113 (match_operand:VI_HW_QHS 2 "register_operand" "v")]
1114 UNSPEC_VEC_SRL))]
1115 "TARGET_VX"
1116 "vsrl\t%v0,%v1,%v2"
1117 [(set_attr "op_type" "VRR")])
1118
1119
1120; Vector shift right logical by byte
1121
1122; Pattern definition in vector.md
1123(define_expand "vec_srb<mode>"
1124 [(set (match_operand:V_HW 0 "register_operand" "")
1125 (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "")
1126 (match_operand:<tointvec> 2 "register_operand" "")]
1127 UNSPEC_VEC_SRLB))]
1128 "TARGET_VX")
1129
1130
1131; Vector subtract
1132
3af82a61
AK		 1133; Vector subtract compute borrow indication
1134
50dc4eed 1135; vscbib, vscbih, vscbif, vscbig, vscbiq
2d71f118
AK		 1136(define_insn "vscbi<bhfgq>_<mode>"
1137 [(set (match_operand:VIT_HW 0 "register_operand" "=v")
1138 (unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "v")
1139 (match_operand:VIT_HW 2 "register_operand" "v")]
3af82a61
AK		 1140 UNSPEC_VEC_SUBC))]
1141 "TARGET_VX"
1142 "vscbi<bhfgq>\t%v0,%v1,%v2"
1143 [(set_attr "op_type" "VRR")])
1144
3af82a61
AK		 1145; Vector subtract with borrow indication
1146
2d71f118
AK		 1147(define_insn "vsbiq"
1148 [(set (match_operand:TI 0 "register_operand" "=v")
1149 (unspec:TI [(match_operand:TI 1 "register_operand" "v")
1150 (match_operand:TI 2 "register_operand" "v")
1151 (match_operand:TI 3 "register_operand" "v")]
3af82a61
AK		 1152 UNSPEC_VEC_SUBE_U128))]
1153 "TARGET_VX"
1154 "vsbiq\t%v0,%v1,%v2,%v3"
1155 [(set_attr "op_type" "VRR")])
1156
1157
1158; Vector subtract with borrow compute and borrow indication
1159
2d71f118
AK		 1160(define_insn "vsbcbiq"
1161 [(set (match_operand:TI 0 "register_operand" "=v")
1162 (unspec:TI [(match_operand:TI 1 "register_operand" "v")
1163 (match_operand:TI 2 "register_operand" "v")
1164 (match_operand:TI 3 "register_operand" "v")]
3af82a61
AK		 1165 UNSPEC_VEC_SUBEC_U128))]
1166 "TARGET_VX"
1167 "vsbcbiq\t%v0,%v1,%v2,%v3"
1168 [(set_attr "op_type" "VRR")])
1169
1170
1171; Vector sum across
1172
1173; Sum across DImode parts of the 1st operand and add the rightmost
1174; element of 2nd operand
1175; vsumgh, vsumgf
1176(define_expand "vec_sum2<mode>"
1177 [(set (match_operand:V2DI 0 "register_operand" "")
1178 (unspec:V2DI [(match_operand:VI_HW_HS 1 "register_operand" "")
1179 (match_operand:VI_HW_HS 2 "register_operand" "")]
1180 UNSPEC_VEC_VSUMG))]
1181 "TARGET_VX")
1182
1183; vsumqh, vsumqf
1184(define_insn "vec_sum_u128<mode>"
1185 [(set (match_operand:V2DI 0 "register_operand" "=v")
1186 (unspec:V2DI [(match_operand:VI_HW_SD 1 "register_operand" "v")
1187 (match_operand:VI_HW_SD 2 "register_operand" "v")]
1188 UNSPEC_VEC_VSUMQ))]
1189 "TARGET_VX"
1190 "vsumq<bhfgq>\t%v0,%v1,%v2"
1191 [(set_attr "op_type" "VRR")])
1192
1193; vsumb, vsumh
1194(define_expand "vec_sum4<mode>"
1195 [(set (match_operand:V4SI 0 "register_operand" "")
1196 (unspec:V4SI [(match_operand:VI_HW_QH 1 "register_operand" "")
1197 (match_operand:VI_HW_QH 2 "register_operand" "")]
1198 UNSPEC_VEC_VSUM))]
1199 "TARGET_VX")
1200
1201
1202; Vector test under mask
1203
1204(define_expand "vec_test_mask_int<mode>"
1205 [(set (reg:CCRAW CC_REGNUM)
1206 (unspec:CCRAW [(match_operand:V_HW 1 "register_operand" "")
1207 (match_operand:<tointvec> 2 "register_operand" "")]
1208 UNSPEC_VEC_TEST_MASK))
1209 (set (match_operand:SI 0 "register_operand" "")
1210 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1211 "TARGET_VX")
1212
1213(define_insn "*vec_test_mask<mode>"
1214 [(set (reg:CCRAW CC_REGNUM)
1215 (unspec:CCRAW [(match_operand:V_HW 0 "register_operand" "v")
1216 (match_operand:<tointvec> 1 "register_operand" "v")]
1217 UNSPEC_VEC_TEST_MASK))]
1218 "TARGET_VX"
1219 "vtm\t%v0,%v1"
1220 [(set_attr "op_type" "VRR")])
1221
1222
1223; Vector find any element equal
1224
1225; vfaeb, vfaeh, vfaef
1226; vfaezb, vfaezh, vfaezf
1227(define_insn "vfae<mode>"
1228 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1229 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1230 (match_operand:VI_HW_QHS 2 "register_operand" "v")
e970b4b0 1231 (match_operand:QI 3 "const_mask_operand" "C")]
3af82a61
AK		 1232 UNSPEC_VEC_VFAE))]
1233 "TARGET_VX"
1234{
406fde6e 1235 unsigned HOST_WIDE_INT flags = UINTVAL (operands[3]);
3af82a61
AK		 1236
1237 if (flags & VSTRING_FLAG_ZS)
1238 {
1239 flags &= ~VSTRING_FLAG_ZS;
1240 operands[3] = GEN_INT (flags);
1241 return "vfaez<bhfgq>\t%v0,%v1,%v2,%b3";
1242 }
1243 return "vfae<bhfgq>\t%v0,%v1,%v2,%b3";
1244}
1245[(set_attr "op_type" "VRR")])
1246
1247; vfaebs, vfaehs, vfaefs
1248; vfaezbs, vfaezhs, vfaezfs
1249(define_insn "*vfaes<mode>"
1250 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
e970b4b0
AK		 1251 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1252 (match_operand:VI_HW_QHS 2 "register_operand" "v")
1253 (match_operand:QI 3 "const_mask_operand" "C")]
3af82a61
AK		 1254 UNSPEC_VEC_VFAE))
1255 (set (reg:CCRAW CC_REGNUM)
1256 (unspec:CCRAW [(match_dup 1)
1257 (match_dup 2)
1258 (match_dup 3)]
1259 UNSPEC_VEC_VFAECC))]
1260 "TARGET_VX"
1261{
406fde6e 1262 unsigned HOST_WIDE_INT flags = UINTVAL (operands[3]);
3af82a61
AK		 1263
1264 if (flags & VSTRING_FLAG_ZS)
1265 {
1266 flags &= ~VSTRING_FLAG_ZS;
1267 operands[3] = GEN_INT (flags);
1268 return "vfaez<bhfgq>s\t%v0,%v1,%v2,%b3";
1269 }
1270 return "vfae<bhfgq>s\t%v0,%v1,%v2,%b3";
1271}
1272 [(set_attr "op_type" "VRR")])
1273
1274(define_expand "vfaez<mode>"
1275 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
e970b4b0
AK		 1276 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1277 (match_operand:VI_HW_QHS 2 "register_operand" "")
1278 (match_operand:QI 3 "const_mask_operand" "")]
3af82a61
AK		 1279 UNSPEC_VEC_VFAE))]
1280 "TARGET_VX"
1281{
1282 operands[3] = GEN_INT (INTVAL (operands[3]) | VSTRING_FLAG_ZS);
1283})
1284
1285(define_expand "vfaes<mode>"
1286 [(parallel
1287 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
e970b4b0
AK		 1288 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1289 (match_operand:VI_HW_QHS 2 "register_operand" "")
1290 (match_operand:QI 3 "const_mask_operand" "")]
3af82a61
AK		 1291 UNSPEC_VEC_VFAE))
1292 (set (reg:CCRAW CC_REGNUM)
1293 (unspec:CCRAW [(match_dup 1)
1294 (match_dup 2)
1295 (match_dup 3)]
1296 UNSPEC_VEC_VFAECC))])
1297 (set (match_operand:SI 4 "memory_operand" "")
1298 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1299 "TARGET_VX"
1300{
1301 operands[3] = GEN_INT (INTVAL (operands[3]) | VSTRING_FLAG_CS);
1302})
1303
1304(define_expand "vfaezs<mode>"
1305 [(parallel
1306 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
e970b4b0
AK		 1307 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1308 (match_operand:VI_HW_QHS 2 "register_operand" "")
1309 (match_operand:SI 3 "const_mask_operand" "")]
3af82a61
AK		 1310 UNSPEC_VEC_VFAE))
1311 (set (reg:CCRAW CC_REGNUM)
1312 (unspec:CCRAW [(match_dup 1)
1313 (match_dup 2)
1314 (match_dup 3)]
1315 UNSPEC_VEC_VFAECC))])
1316 (set (match_operand:SI 4 "memory_operand" "")
1317 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1318 "TARGET_VX"
1319{
1320 operands[3] = GEN_INT (INTVAL (operands[3]) | VSTRING_FLAG_CS | VSTRING_FLAG_ZS);
1321})
1322
1323
1324; Vector find element equal
1325
1326; vfeebs, vfeehs, vfeefs
1327; vfeezbs, vfeezhs, vfeezfs
1328(define_insn "*vfees<mode>"
1329 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1330 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1331 (match_operand:VI_HW_QHS 2 "register_operand" "v")
e970b4b0 1332 (match_operand:QI 3 "const_mask_operand" "C")]
3af82a61
AK		 1333 UNSPEC_VEC_VFEE))
1334 (set (reg:CCRAW CC_REGNUM)
1335 (unspec:CCRAW [(match_dup 1)
1336 (match_dup 2)
1337 (match_dup 3)]
1338 UNSPEC_VEC_VFEECC))]
1339 "TARGET_VX"
1340{
406fde6e 1341 unsigned HOST_WIDE_INT flags = UINTVAL (operands[3]);
3af82a61
AK		 1342
1343 gcc_assert (!(flags & ~(VSTRING_FLAG_ZS | VSTRING_FLAG_CS)));
1344 flags &= ~VSTRING_FLAG_CS;
1345
1346 if (flags == VSTRING_FLAG_ZS)
1347 return "vfeez<bhfgq>s\t%v0,%v1,%v2";
1348 return "vfee<bhfgq>s\t%v0,%v1,%v2,%b3";
1349}
1350 [(set_attr "op_type" "VRR")])
1351
1352; vfeeb, vfeeh, vfeef
1353(define_insn "vfee<mode>"
1354 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1355 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1356 (match_operand:VI_HW_QHS 2 "register_operand" "")
1357 (const_int 0)]
1358 UNSPEC_VEC_VFEE))]
1359 "TARGET_VX"
1360 "vfee<bhfgq>\t%v0,%v1,%v2,0"
1361 [(set_attr "op_type" "VRR")])
1362
1363; vfeezb, vfeezh, vfeezf
1364(define_insn "vfeez<mode>"
1365 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1366 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1367 (match_operand:VI_HW_QHS 2 "register_operand" "")
1368 (const_int VSTRING_FLAG_ZS)]
1369 UNSPEC_VEC_VFEE))]
1370 "TARGET_VX"
1371 "vfeez<bhfgq>s\t%v0,%v1,%v2,2"
1372 [(set_attr "op_type" "VRR")])
1373
1374(define_expand "vfees<mode>"
1375 [(parallel
1376 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1377 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1378 (match_operand:VI_HW_QHS 2 "register_operand" "")
1379 (const_int VSTRING_FLAG_CS)]
1380 UNSPEC_VEC_VFEE))
1381 (set (reg:CCRAW CC_REGNUM)
1382 (unspec:CCRAW [(match_dup 1)
1383 (match_dup 2)
1384 (const_int VSTRING_FLAG_CS)]
1385 UNSPEC_VEC_VFEECC))])
1386 (set (match_operand:SI 3 "memory_operand" "")
1387 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1388 "TARGET_VX")
1389
1390(define_expand "vfeezs<mode>"
1391 [(parallel
1392 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1393 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1394 (match_operand:VI_HW_QHS 2 "register_operand" "")
1395 (match_dup 4)]
1396 UNSPEC_VEC_VFEE))
1397 (set (reg:CCRAW CC_REGNUM)
1398 (unspec:CCRAW [(match_dup 1)
1399 (match_dup 2)
1400 (match_dup 4)]
1401 UNSPEC_VEC_VFEECC))])
1402 (set (match_operand:SI 3 "memory_operand" "")
1403 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1404 "TARGET_VX"
1405{
1406 operands[4] = GEN_INT (VSTRING_FLAG_ZS | VSTRING_FLAG_CS);
1407})
1408
1409; Vector find element not equal
1410
1411; vfeneb, vfeneh, vfenef
1412(define_insn "vfene<mode>"
1413 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1414 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1415 (match_operand:VI_HW_QHS 2 "register_operand" "v")
1416 (const_int 0)]
1417 UNSPEC_VEC_VFENE))]
1418 "TARGET_VX"
1419 "vfene<bhfgq>\t%v0,%v1,%v2,0"
1420 [(set_attr "op_type" "VRR")])
1421
1422; vec_vfenes can be found in vector.md since it is used for strlen
1423
1424; vfenezb, vfenezh, vfenezf
1425(define_insn "vfenez<mode>"
1426 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1427 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1428 (match_operand:VI_HW_QHS 2 "register_operand" "")
1429 (const_int VSTRING_FLAG_ZS)]
1430 UNSPEC_VEC_VFENE))]
1431 "TARGET_VX"
1432 "vfenez<bhfgq>\t%v0,%v1,%v2"
1433 [(set_attr "op_type" "VRR")])
1434
1435(define_expand "vfenes<mode>"
1436 [(parallel
1437 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1438 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1439 (match_operand:VI_HW_QHS 2 "register_operand" "")
1440 (const_int VSTRING_FLAG_CS)]
1441 UNSPEC_VEC_VFENE))
1442 (set (reg:CCRAW CC_REGNUM)
1443 (unspec:CCRAW [(match_dup 1)
1444 (match_dup 2)
1445 (const_int VSTRING_FLAG_CS)]
1446 UNSPEC_VEC_VFENECC))])
1447 (set (match_operand:SI 3 "memory_operand" "")
1448 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1449 "TARGET_VX")
1450
1451(define_expand "vfenezs<mode>"
1452 [(parallel
1453 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1454 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1455 (match_operand:VI_HW_QHS 2 "register_operand" "")
1456 (match_dup 4)]
1457 UNSPEC_VEC_VFENE))
1458 (set (reg:CCRAW CC_REGNUM)
1459 (unspec:CCRAW [(match_dup 1)
1460 (match_dup 2)
1461 (match_dup 4)]
1462 UNSPEC_VEC_VFENECC))])
1463 (set (match_operand:SI 3 "memory_operand" "")
1464 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1465 "TARGET_VX"
1466{
1467 operands[4] = GEN_INT (VSTRING_FLAG_ZS | VSTRING_FLAG_CS);
1468})
1469
1470; Vector isolate string
1471
1472; vistrb, vistrh, vistrf
1473(define_insn "vistr<mode>"
1474 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1475 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
1476 UNSPEC_VEC_VISTR))]
1477 "TARGET_VX"
1478 "vistr<bhfgq>\t%v0,%v1"
1479 [(set_attr "op_type" "VRR")])
1480
1481; vistrbs, vistrhs, vistrfs
1482(define_insn "*vistrs<mode>"
1483 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1484 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
1485 UNSPEC_VEC_VISTR))
1486 (set (reg:CCRAW CC_REGNUM)
1487 (unspec:CCRAW [(match_dup 1)] UNSPEC_VEC_VISTRCC))]
1488 "TARGET_VX"
1489 "vistr<bhfgq>s\t%v0,%v1"
1490 [(set_attr "op_type" "VRR")])
1491
1492(define_expand "vistrs<mode>"
1493 [(parallel
1494 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1495 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")]
1496 UNSPEC_VEC_VISTR))
1497 (set (reg:CCRAW CC_REGNUM)
1498 (unspec:CCRAW [(match_dup 1)]
1499 UNSPEC_VEC_VISTRCC))])
1500 (set (match_operand:SI 2 "memory_operand" "")
1501 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1502 "TARGET_VX")
1503
1504
1505; Vector compare range
1506
1507; vstrcb, vstrch, vstrcf
1508; vstrczb, vstrczh, vstrczf
1509(define_insn "vstrc<mode>"
e970b4b0
AK		 1510 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1511 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1512 (match_operand:VI_HW_QHS 2 "register_operand" "v")
1513 (match_operand:VI_HW_QHS 3 "register_operand" "v")
1514 (match_operand:QI 4 "const_mask_operand" "C")]
3af82a61
AK		 1515 UNSPEC_VEC_VSTRC))]
1516 "TARGET_VX"
1517{
406fde6e 1518 unsigned HOST_WIDE_INT flags = UINTVAL (operands[4]);
3af82a61
AK		 1519
1520 if (flags & VSTRING_FLAG_ZS)
1521 {
1522 flags &= ~VSTRING_FLAG_ZS;
1523 operands[4] = GEN_INT (flags);
1524 return "vstrcz<bhfgq>\t%v0,%v1,%v2,%v3,%b4";
1525 }
1526 return "vstrc<bhfgq>\t%v0,%v1,%v2,%v3,%b4";
1527}
1528[(set_attr "op_type" "VRR")])
1529
1530; vstrcbs, vstrchs, vstrcfs
1531; vstrczbs, vstrczhs, vstrczfs
1532(define_insn "*vstrcs<mode>"
e970b4b0
AK		 1533 [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1534 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1535 (match_operand:VI_HW_QHS 2 "register_operand" "v")
1536 (match_operand:VI_HW_QHS 3 "register_operand" "v")
1537 (match_operand:QI 4 "const_mask_operand" "C")]
3af82a61
AK		 1538 UNSPEC_VEC_VSTRC))
1539 (set (reg:CCRAW CC_REGNUM)
1540 (unspec:CCRAW [(match_dup 1)
1541 (match_dup 2)
1542 (match_dup 3)
1543 (match_dup 4)]
1544 UNSPEC_VEC_VSTRCCC))]
1545 "TARGET_VX"
1546{
406fde6e 1547 unsigned HOST_WIDE_INT flags = UINTVAL (operands[4]);
3af82a61
AK		 1548
1549 if (flags & VSTRING_FLAG_ZS)
1550 {
1551 flags &= ~VSTRING_FLAG_ZS;
1552 operands[4] = GEN_INT (flags);
1553 return "vstrcz<bhfgq>s\t%v0,%v1,%v2,%v3,%b4";
1554 }
1555 return "vstrc<bhfgq>s\t%v0,%v1,%v2,%v3,%b4";
1556}
1557 [(set_attr "op_type" "VRR")])
1558
1559(define_expand "vstrcz<mode>"
e970b4b0
AK		 1560 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1561 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1562 (match_operand:VI_HW_QHS 2 "register_operand" "")
1563 (match_operand:VI_HW_QHS 3 "register_operand" "")
1564 (match_operand:QI 4 "const_mask_operand" "")]
3af82a61
AK		 1565 UNSPEC_VEC_VSTRC))]
1566 "TARGET_VX"
1567{
1568 operands[4] = GEN_INT (INTVAL (operands[4]) | VSTRING_FLAG_ZS);
1569})
1570
1571(define_expand "vstrcs<mode>"
1572 [(parallel
1573 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1574 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1575 (match_operand:VI_HW_QHS 2 "register_operand" "")
1576 (match_operand:VI_HW_QHS 3 "register_operand" "")
e970b4b0 1577 (match_operand:QI 4 "const_mask_operand" "")]
3af82a61
AK		 1578 UNSPEC_VEC_VSTRC))
1579 (set (reg:CCRAW CC_REGNUM)
1580 (unspec:CCRAW [(match_dup 1)
1581 (match_dup 2)
1582 (match_dup 3)
1583 (match_dup 4)]
1584 UNSPEC_VEC_VSTRCCC))])
1585 (set (match_operand:SI 5 "memory_operand" "")
1586 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1587 "TARGET_VX"
1588{
1589 operands[4] = GEN_INT (INTVAL (operands[4]) | VSTRING_FLAG_CS);
1590})
1591
1592(define_expand "vstrczs<mode>"
1593 [(parallel
1594 [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1595 (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1596 (match_operand:VI_HW_QHS 2 "register_operand" "")
1597 (match_operand:VI_HW_QHS 3 "register_operand" "")
e970b4b0 1598 (match_operand:QI 4 "const_mask_operand" "")]
3af82a61
AK		 1599 UNSPEC_VEC_VSTRC))
1600 (set (reg:CCRAW CC_REGNUM)
1601 (unspec:CCRAW [(match_dup 1)
1602 (match_dup 2)
1603 (match_dup 3)
1604 (match_dup 4)]
1605 UNSPEC_VEC_VSTRCCC))])
1606 (set (match_operand:SI 5 "memory_operand" "")
1607 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1608 "TARGET_VX"
1609{
1610 operands[4] = GEN_INT (INTVAL (operands[4]) | VSTRING_FLAG_CS | VSTRING_FLAG_ZS);
1611})
1612
1613
1614; Signed V2DI -> V2DF conversion - inexact exception disabled
1615(define_insn "vec_di_to_df_s64"
e970b4b0
AK		 1616 [(set (match_operand:V2DF 0 "register_operand" "=v")
1617 (unspec:V2DF [(match_operand:V2DI 1 "register_operand" "v")
1618 (match_operand:QI 2 "const_mask_operand" "C")]
3af82a61 1619 UNSPEC_VEC_VCDGB))]
e970b4b0 1620 "TARGET_VX && UINTVAL (operands[2]) != 2 && UINTVAL (operands[2]) <= 7"
3af82a61
AK		 1621 "vcdgb\t%v0,%v1,4,%b2"
1622 [(set_attr "op_type" "VRR")])
1623
1624; The result needs to be multiplied with 2**-op2
1625(define_expand "vec_ctd_s64"
1626 [(set (match_operand:V2DF 0 "register_operand" "")
1627 (unspec:V2DF [(match_operand:V2DI 1 "register_operand" "")
1628 (const_int 0)] ; According to current BFP rounding mode
1629 UNSPEC_VEC_VCDGB))
e970b4b0 1630 (use (match_operand:QI 2 "const_int_operand" ""))
3af82a61
AK		 1631 (set (match_dup 0) (mult:V2DF (match_dup 0) (match_dup 3)))]
1632 "TARGET_VX"
1633{
1634 REAL_VALUE_TYPE f;
1635 rtx c;
1636
1637 real_2expN (&f, -INTVAL (operands[2]), DFmode);
555affd7 1638 c = const_double_from_real_value (f, DFmode);
3af82a61
AK		 1639
1640 operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c));
1641 operands[3] = force_reg (V2DFmode, operands[3]);
1642})
1643
1644; Unsigned V2DI -> V2DF conversion - inexact exception disabled
1645(define_insn "vec_di_to_df_u64"
1646 [(set (match_operand:V2DF 0 "register_operand" "=v")
1647 (unspec:V2DF [(match_operand:V2DI 1 "register_operand" "v")
e970b4b0 1648 (match_operand:QI 2 "const_int_operand" "C")]
3af82a61
AK		 1649 UNSPEC_VEC_VCDLGB))]
1650 "TARGET_VX"
1651 "vcdlgb\t%v0,%v1,4,%b2"
1652 [(set_attr "op_type" "VRR")])
1653
1654; The result needs to be multiplied with 2**-op2
1655(define_expand "vec_ctd_u64"
1656 [(set (match_operand:V2DF 0 "register_operand" "")
1657 (unspec:V2DF [(match_operand:V2DI 1 "register_operand" "")
1658 (const_int 0)] ; According to current BFP rounding mode
1659 UNSPEC_VEC_VCDLGB))
e970b4b0 1660 (use (match_operand:QI 2 "const_int_operand" ""))
3af82a61
AK		 1661 (set (match_dup 0) (mult:V2DF (match_dup 0) (match_dup 3)))]
1662 "TARGET_VX"
1663{
1664 REAL_VALUE_TYPE f;
1665 rtx c;
1666
1667 real_2expN (&f, -INTVAL (operands[2]), DFmode);
555affd7 1668 c = const_double_from_real_value (f, DFmode);
3af82a61
AK		 1669
1670 operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c));
1671 operands[3] = force_reg (V2DFmode, operands[3]);
1672})
1673
1674
1675; Signed V2DF -> V2DI conversion - inexact exception disabled
1676(define_insn "vec_df_to_di_s64"
1677 [(set (match_operand:V2DI 0 "register_operand" "=v")
1678 (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v")
e970b4b0 1679 (match_operand:QI 2 "const_int_operand" "C")]
3af82a61
AK		 1680 UNSPEC_VEC_VCGDB))]
1681 "TARGET_VX"
1682 "vcgdb\t%v0,%v1,4,%b2"
1683 [(set_attr "op_type" "VRR")])
1684
1685; The input needs to be multiplied with 2**op2
1686(define_expand "vec_ctsl"
e970b4b0 1687 [(use (match_operand:QI 2 "const_int_operand" ""))
3af82a61
AK		 1688 (set (match_dup 4) (mult:V2DF (match_operand:V2DF 1 "register_operand" "")
1689 (match_dup 3)))
1690 (set (match_operand:V2DI 0 "register_operand" "")
1691 (unspec:V2DI [(match_dup 4) (const_int 0)] ; According to current BFP rounding mode
1692 UNSPEC_VEC_VCGDB))]
1693 "TARGET_VX"
1694{
1695 REAL_VALUE_TYPE f;
1696 rtx c;
1697
1698 real_2expN (&f, INTVAL (operands[2]), DFmode);
555affd7 1699 c = const_double_from_real_value (f, DFmode);
3af82a61
AK		 1700
1701 operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c));
1702 operands[3] = force_reg (V2DFmode, operands[3]);
1703 operands[4] = gen_reg_rtx (V2DFmode);
1704})
1705
1706; Unsigned V2DF -> V2DI conversion - inexact exception disabled
1707(define_insn "vec_df_to_di_u64"
1708 [(set (match_operand:V2DI 0 "register_operand" "=v")
1709 (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v")
e970b4b0 1710 (match_operand:QI 2 "const_mask_operand" "C")]
3af82a61 1711 UNSPEC_VEC_VCLGDB))]
e970b4b0 1712 "TARGET_VX && UINTVAL (operands[2]) <= 7"
3af82a61
AK		 1713 "vclgdb\t%v0,%v1,4,%b2"
1714 [(set_attr "op_type" "VRR")])
1715
1716; The input needs to be multiplied with 2**op2
1717(define_expand "vec_ctul"
e970b4b0 1718 [(use (match_operand:QI 2 "const_int_operand" ""))
3af82a61
AK		 1719 (set (match_dup 4) (mult:V2DF (match_operand:V2DF 1 "register_operand" "")
1720 (match_dup 3)))
1721 (set (match_operand:V2DI 0 "register_operand" "")
1722 (unspec:V2DI [(match_dup 4) (const_int 0)] ; According to current BFP rounding mode
1723 UNSPEC_VEC_VCLGDB))]
1724 "TARGET_VX"
1725{
1726 REAL_VALUE_TYPE f;
1727 rtx c;
1728
1729 real_2expN (&f, INTVAL (operands[2]), DFmode);
555affd7 1730 c = const_double_from_real_value (f, DFmode);
3af82a61
AK		 1731
1732 operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c));
1733 operands[3] = force_reg (V2DFmode, operands[3]);
1734 operands[4] = gen_reg_rtx (V2DFmode);
1735})
1736
1737; Vector load fp integer - IEEE inexact exception is suppressed
1738(define_insn "vfidb"
e970b4b0
AK		 1739 [(set (match_operand:V2DI 0 "register_operand" "=v")
1740 (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v")
1741 (match_operand:QI 2 "const_mask_operand" "C")
1742 (match_operand:QI 3 "const_mask_operand" "C")]
3af82a61 1743 UNSPEC_VEC_VFIDB))]
e970b4b0 1744 "TARGET_VX && !(UINTVAL (operands[2]) & 3) && UINTVAL (operands[3]) <= 7"
3af82a61
AK		 1745 "vfidb\t%v0,%v1,%b2,%b3"
1746 [(set_attr "op_type" "VRR")])
1747
3af82a61
AK		 1748
1749; Vector load lengthened - V4SF -> V2DF
1750
1751(define_insn "*vldeb"
1752 [(set (match_operand:V2DF 0 "register_operand" "=v")
1753 (unspec:V2DF [(match_operand:V4SF 1 "register_operand" "v")]
1754 UNSPEC_VEC_VLDEB))]
1755 "TARGET_VX"
1756 "vldeb\t%v0,%v1"
1757 [(set_attr "op_type" "VRR")])
1758
1759(define_expand "vec_ld2f"
1760 [; Initialize a vector to all zeroes. FIXME: This should not be
1761 ; necessary since all elements of the vector will be set anyway.
1762 ; This is just to make it explicit to the data flow framework.
1763 (set (match_dup 2) (match_dup 3))
1764 (set (match_dup 2) (unspec:V4SF [(match_operand:SF 1 "memory_operand" "")
1765 (const_int 0)
1766 (match_dup 2)]
1767 UNSPEC_VEC_SET))
1768 (set (match_dup 2) (unspec:V4SF [(match_dup 4)
1769 (const_int 2)
1770 (match_dup 2)]
1771 UNSPEC_VEC_SET))
1772 (set (match_operand:V2DF 0 "register_operand" "")
1773 (unspec:V2DF [(match_dup 2)] UNSPEC_VEC_VLDEB))]
1774 "TARGET_VX"
1775{
1776 operands[2] = gen_reg_rtx (V4SFmode);
1777 operands[3] = CONST0_RTX (V4SFmode);
1778 operands[4] = adjust_address (operands[1], SFmode, 4);
1779})
1780
1781
1782; Vector load rounded - V2DF -> V4SF
1783
1784(define_insn "*vledb"
1785 [(set (match_operand:V4SF 0 "register_operand" "=v")
1786 (unspec:V4SF [(match_operand:V2DF 1 "register_operand" "v")]
1787 UNSPEC_VEC_VLEDB))]
1788 "TARGET_VX"
1789 "vledb\t%v0,%v1,0,0"
1790 [(set_attr "op_type" "VRR")])
1791
1792(define_expand "vec_st2f"
1793 [(set (match_dup 2)
1794 (unspec:V4SF [(match_operand:V2DF 0 "register_operand" "")]
1795 UNSPEC_VEC_VLEDB))
1796 (set (match_operand:SF 1 "memory_operand" "")
1797 (unspec:SF [(match_dup 2) (const_int 0)] UNSPEC_VEC_EXTRACT))
1798 (set (match_dup 3)
1799 (unspec:SF [(match_dup 2) (const_int 2)] UNSPEC_VEC_EXTRACT))]
1800 "TARGET_VX"
1801{
1802 operands[2] = gen_reg_rtx (V4SFmode);
1803 operands[3] = adjust_address (operands[1], SFmode, 4);
1804})
1805
1806
1807; Vector load negated fp
1808
1809(define_expand "vec_nabs"
1810 [(set (match_operand:V2DF 0 "register_operand" "")
1811 (neg:V2DF (abs:V2DF (match_operand:V2DF 1 "register_operand" ""))))]
1812 "TARGET_VX")
1813
1814; Vector square root fp vec_sqrt -> sqrt rtx standard name
1815
1816; Vector FP test data class immediate
1817
1818(define_insn "*vftcidb"
1819 [(set (match_operand:V2DF 0 "register_operand" "=v")
1820 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "v")
e970b4b0 1821 (match_operand:HI 2 "const_int_operand" "J")]
3af82a61
AK		 1822 UNSPEC_VEC_VFTCIDB))
1823 (set (reg:CCRAW CC_REGNUM)
1824 (unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCIDBCC))]
e970b4b0 1825 "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")"
3af82a61
AK		 1826 "vftcidb\t%v0,%v1,%x2"
1827 [(set_attr "op_type" "VRR")])
1828
1829(define_insn "*vftcidb_cconly"
1830 [(set (reg:CCRAW CC_REGNUM)
1831 (unspec:CCRAW [(match_operand:V2DF 1 "register_operand" "v")
e970b4b0 1832 (match_operand:HI 2 "const_int_operand" "J")]
3af82a61
AK		 1833 UNSPEC_VEC_VFTCIDBCC))
1834 (clobber (match_scratch:V2DI 0 "=v"))]
e970b4b0 1835 "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")"
3af82a61
AK		 1836 "vftcidb\t%v0,%v1,%x2"
1837 [(set_attr "op_type" "VRR")])
1838
1839(define_expand "vftcidb"
1840 [(parallel
1841 [(set (match_operand:V2DF 0 "register_operand" "")
1842 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "")
e970b4b0 1843 (match_operand:HI 2 "const_int_operand" "")]
3af82a61
AK		 1844 UNSPEC_VEC_VFTCIDB))
1845 (set (reg:CCRAW CC_REGNUM)
1846 (unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCIDBCC))])
1847 (set (match_operand:SI 3 "memory_operand" "")
1848 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
e970b4b0 1849 "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")")
3af82a61
AK		 1850
1851;;
1852;; Integer compares
1853;;
1854
1855; All comparisons which produce a CC need fully populated (VI_HW)
1856; vector arguments. Otherwise the any/all CCs would be just bogus.
1857
1858(define_insn "*vec_cmp<VICMP:insn_cmp><VI_HW:mode>_cconly"
1859 [(set (reg:VICMP CC_REGNUM)
1860 (compare:VICMP (match_operand:VI_HW 0 "register_operand" "v")
1861 (match_operand:VI_HW 1 "register_operand" "v")))
1862 (clobber (match_scratch:VI_HW 2 "=v"))]
1863 "TARGET_VX"
1864 "vc<VICMP:insn_cmp><VI_HW:bhfgq>s\t%v2,%v0,%v1"
1865 [(set_attr "op_type" "VRR")])
1866
1867; FIXME: The following 2x3 definitions should be merged into 2 with
1868; VICMP like above but I could not find a way to set the comparison
1869; operator (eq) depending on the mode CCVEQ (mode_iterator). Or the
1870; other way around - setting the mode depending on the code
1871; (code_iterator).
1872(define_expand "vec_cmpeq<VI_HW:mode>_cc"
1873 [(parallel
1874 [(set (reg:CCVEQ CC_REGNUM)
1875 (compare:CCVEQ (match_operand:VI_HW 1 "register_operand" "v")
1876 (match_operand:VI_HW 2 "register_operand" "v")))
1877 (set (match_operand:VI_HW 0 "register_operand" "=v")
1878 (eq:VI_HW (match_dup 1) (match_dup 2)))])
1879 (set (match_operand:SI 3 "memory_operand" "")
1880 (unspec:SI [(reg:CCVEQ CC_REGNUM)] UNSPEC_CC_TO_INT))]
1881 "TARGET_VX")
1882
1883(define_expand "vec_cmph<VI_HW:mode>_cc"
1884 [(parallel
a6a2b532
AK		 1885 [(set (reg:CCVIH CC_REGNUM)
1886 (compare:CCVIH (match_operand:VI_HW 1 "register_operand" "v")
1887 (match_operand:VI_HW 2 "register_operand" "v")))
3af82a61
AK		 1888 (set (match_operand:VI_HW 0 "register_operand" "=v")
1889 (gt:VI_HW (match_dup 1) (match_dup 2)))])
1890 (set (match_operand:SI 3 "memory_operand" "")
a6a2b532 1891 (unspec:SI [(reg:CCVIH CC_REGNUM)] UNSPEC_CC_TO_INT))]
3af82a61
AK		 1892 "TARGET_VX")
1893
1894(define_expand "vec_cmphl<VI_HW:mode>_cc"
1895 [(parallel
a6a2b532
AK		 1896 [(set (reg:CCVIHU CC_REGNUM)
1897 (compare:CCVIHU (match_operand:VI_HW 1 "register_operand" "v")
1898 (match_operand:VI_HW 2 "register_operand" "v")))
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AK		 1899 (set (match_operand:VI_HW 0 "register_operand" "=v")
1900 (gtu:VI_HW (match_dup 1) (match_dup 2)))])
1901 (set (match_operand:SI 3 "memory_operand" "")
a6a2b532 1902 (unspec:SI [(reg:CCVIHU CC_REGNUM)] UNSPEC_CC_TO_INT))]
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AK		 1903 "TARGET_VX")
1904
1905
1906(define_insn "*vec_cmpeq<VI_HW:mode>_cc"
1907 [(set (reg:CCVEQ CC_REGNUM)
1908 (compare:CCVEQ (match_operand:VI_HW 0 "register_operand" "v")
1909 (match_operand:VI_HW 1 "register_operand" "v")))
1910 (set (match_operand:VI_HW 2 "register_operand" "=v")
1911 (eq:VI_HW (match_dup 0) (match_dup 1)))]
1912 "TARGET_VX"
1913 "vceq<VI_HW:bhfgq>s\t%v2,%v0,%v1"
1914 [(set_attr "op_type" "VRR")])
1915
1916(define_insn "*vec_cmph<VI_HW:mode>_cc"
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AK		 1917 [(set (reg:CCVIH CC_REGNUM)
1918 (compare:CCVIH (match_operand:VI_HW 0 "register_operand" "v")
1919 (match_operand:VI_HW 1 "register_operand" "v")))
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AK		 1920 (set (match_operand:VI_HW 2 "register_operand" "=v")
1921 (gt:VI_HW (match_dup 0) (match_dup 1)))]
1922 "TARGET_VX"
1923 "vch<VI_HW:bhfgq>s\t%v2,%v0,%v1"
1924 [(set_attr "op_type" "VRR")])
1925
1926(define_insn "*vec_cmphl<VI_HW:mode>_cc"
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AK		 1927 [(set (reg:CCVIHU CC_REGNUM)
1928 (compare:CCVIHU (match_operand:VI_HW 0 "register_operand" "v")
1929 (match_operand:VI_HW 1 "register_operand" "v")))
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AK		 1930 (set (match_operand:VI_HW 2 "register_operand" "=v")
1931 (gtu:VI_HW (match_dup 0) (match_dup 1)))]
1932 "TARGET_VX"
1933 "vchl<VI_HW:bhfgq>s\t%v2,%v0,%v1"
1934 [(set_attr "op_type" "VRR")])
1935
1936;;
1937;; Floating point comparesg
1938;;
1939
1940(define_insn "*vec_cmp<insn_cmp>v2df_cconly"
1941 [(set (reg:VFCMP CC_REGNUM)
1942 (compare:VFCMP (match_operand:V2DF 0 "register_operand" "v")
1943 (match_operand:V2DF 1 "register_operand" "v")))
1944 (clobber (match_scratch:V2DI 2 "=v"))]
1945 "TARGET_VX"
1946 "vfc<asm_fcmp>dbs\t%v2,%v0,%v1"
1947 [(set_attr "op_type" "VRR")])
1948
1949; FIXME: Merge the following 2x3 patterns with VFCMP
1950(define_expand "vec_cmpeqv2df_cc"
1951 [(parallel
1952 [(set (reg:CCVEQ CC_REGNUM)
1953 (compare:CCVEQ (match_operand:V2DF 1 "register_operand" "v")
1954 (match_operand:V2DF 2 "register_operand" "v")))
1955 (set (match_operand:V2DI 0 "register_operand" "=v")
1956 (eq:V2DI (match_dup 1) (match_dup 2)))])
1957 (set (match_operand:SI 3 "memory_operand" "")
1958 (unspec:SI [(reg:CCVEQ CC_REGNUM)] UNSPEC_CC_TO_INT))]
1959 "TARGET_VX")
1960
1961(define_expand "vec_cmphv2df_cc"
1962 [(parallel
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AK		 1963 [(set (reg:CCVIH CC_REGNUM)
1964 (compare:CCVIH (match_operand:V2DF 1 "register_operand" "v")
1965 (match_operand:V2DF 2 "register_operand" "v")))
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AK		 1966 (set (match_operand:V2DI 0 "register_operand" "=v")
1967 (gt:V2DI (match_dup 1) (match_dup 2)))])
1968 (set (match_operand:SI 3 "memory_operand" "")
a6a2b532 1969 (unspec:SI [(reg:CCVIH CC_REGNUM)] UNSPEC_CC_TO_INT))]
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AK		 1970 "TARGET_VX")
1971
1972(define_expand "vec_cmphev2df_cc"
1973 [(parallel
1974 [(set (reg:CCVFHE CC_REGNUM)
1975 (compare:CCVFHE (match_operand:V2DF 1 "register_operand" "v")
1976 (match_operand:V2DF 2 "register_operand" "v")))
1977 (set (match_operand:V2DI 0 "register_operand" "=v")
1978 (ge:V2DI (match_dup 1) (match_dup 2)))])
1979 (set (match_operand:SI 3 "memory_operand" "")
1980 (unspec:SI [(reg:CCVFHE CC_REGNUM)] UNSPEC_CC_TO_INT))]
1981 "TARGET_VX")
1982
1983
1984(define_insn "*vec_cmpeqv2df_cc"
1985 [(set (reg:CCVEQ CC_REGNUM)
1986 (compare:CCVEQ (match_operand:V2DF 0 "register_operand" "v")
1987 (match_operand:V2DF 1 "register_operand" "v")))
1988 (set (match_operand:V2DI 2 "register_operand" "=v")
1989 (eq:V2DI (match_dup 0) (match_dup 1)))]
1990 "TARGET_VX"
1991 "vfcedbs\t%v2,%v0,%v1"
1992 [(set_attr "op_type" "VRR")])
1993
1994(define_insn "*vec_cmphv2df_cc"
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AK		 1995 [(set (reg:CCVIH CC_REGNUM)
1996 (compare:CCVIH (match_operand:V2DF 0 "register_operand" "v")
1997 (match_operand:V2DF 1 "register_operand" "v")))
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AK		 1998 (set (match_operand:V2DI 2 "register_operand" "=v")
1999 (gt:V2DI (match_dup 0) (match_dup 1)))]
2000 "TARGET_VX"
2001 "vfchdbs\t%v2,%v0,%v1"
2002 [(set_attr "op_type" "VRR")])
2003
2004(define_insn "*vec_cmphev2df_cc"
2005 [(set (reg:CCVFHE CC_REGNUM)
2006 (compare:CCVFHE (match_operand:V2DF 0 "register_operand" "v")
2007 (match_operand:V2DF 1 "register_operand" "v")))
2008 (set (match_operand:V2DI 2 "register_operand" "=v")
2009 (ge:V2DI (match_dup 0) (match_dup 1)))]
2010 "TARGET_VX"
2011 "vfchedbs\t%v2,%v0,%v1"
2012 [(set_attr "op_type" "VRR")])
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