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5546ac90 | 1 | ;; Predicate definitions for Renesas / SuperH SH. |
1ce35c11 | 2 | ;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2012 |
c11c09f9 | 3 | ;; Free Software Foundation, Inc. |
5546ac90 KH |
4 | ;; |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify | |
8 | ;; it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 9 | ;; the Free Software Foundation; either version 3, or (at your option) |
5546ac90 KH |
10 | ;; any later version. |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, | |
13 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ;; GNU General Public License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ;; along with GCC; see the file COPYING3. If not see |
19 | ;; <http://www.gnu.org/licenses/>. | |
5546ac90 KH |
20 | |
21 | ;; TODO: Add a comment here. | |
22 | ||
73a4d10b R |
23 | (define_predicate "trapping_target_operand" |
24 | (match_code "if_then_else") | |
25 | { | |
5a82ecd9 | 26 | rtx cond, mem, res, tar, and_expr; |
73a4d10b R |
27 | |
28 | if (GET_MODE (op) != PDImode) | |
29 | return 0; | |
30 | cond = XEXP (op, 0); | |
31 | mem = XEXP (op, 1); | |
32 | res = XEXP (op, 2); | |
f3536097 | 33 | if (!MEM_P (mem) |
73a4d10b R |
34 | || (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE)) |
35 | return 0; | |
36 | tar = XEXP (res, 0); | |
37 | if (!rtx_equal_p (XEXP (mem, 0), tar) | |
38 | || GET_MODE (tar) != Pmode) | |
39 | return 0; | |
40 | if (GET_CODE (cond) == CONST) | |
41 | { | |
42 | cond = XEXP (cond, 0); | |
32a7ab3d | 43 | if (!satisfies_constraint_Csy (tar)) |
73a4d10b R |
44 | return 0; |
45 | if (GET_CODE (tar) == CONST) | |
46 | tar = XEXP (tar, 0); | |
47 | } | |
48 | else if (!arith_reg_operand (tar, VOIDmode) | |
32a7ab3d | 49 | && ! satisfies_constraint_Csy (tar)) |
73a4d10b R |
50 | return 0; |
51 | if (GET_CODE (cond) != EQ) | |
52 | return 0; | |
5a82ecd9 ILT |
53 | and_expr = XEXP (cond, 0); |
54 | return (GET_CODE (and_expr) == AND | |
55 | && rtx_equal_p (XEXP (and_expr, 0), tar) | |
56 | && CONST_INT_P (XEXP (and_expr, 1)) | |
f3536097 | 57 | && CONST_INT_P (XEXP (cond, 1)) |
5a82ecd9 | 58 | && INTVAL (XEXP (and_expr, 1)) == 3 |
73a4d10b R |
59 | && INTVAL (XEXP (cond, 1)) == 3); |
60 | }) | |
5546ac90 KH |
61 | |
62 | ;; TODO: Add a comment here. | |
63 | ||
64 | (define_predicate "and_operand" | |
65 | (match_code "subreg,reg,const_int") | |
66 | { | |
67 | if (logical_operand (op, mode)) | |
68 | return 1; | |
69 | ||
70 | /* Check mshflo.l / mshflhi.l opportunities. */ | |
71 | if (TARGET_SHMEDIA | |
72 | && mode == DImode | |
32a7ab3d | 73 | && satisfies_constraint_J16 (op)) |
5546ac90 KH |
74 | return 1; |
75 | ||
76 | return 0; | |
77 | }) | |
78 | ||
c2acaf06 KH |
79 | ;; Like arith_reg_dest, but this predicate is defined with |
80 | ;; define_special_predicate, not define_predicate. | |
5546ac90 KH |
81 | |
82 | (define_special_predicate "any_arith_reg_dest" | |
83 | (match_code "subreg,reg") | |
84 | { | |
85 | return arith_reg_dest (op, mode); | |
86 | }) | |
87 | ||
c2acaf06 KH |
88 | ;; Like register_operand, but this predicate is defined with |
89 | ;; define_special_predicate, not define_predicate. | |
5546ac90 KH |
90 | |
91 | (define_special_predicate "any_register_operand" | |
92 | (match_code "subreg,reg") | |
93 | { | |
94 | return register_operand (op, mode); | |
95 | }) | |
96 | ||
97 | ;; Returns 1 if OP is a valid source operand for an arithmetic insn. | |
98 | ||
99 | (define_predicate "arith_operand" | |
100 | (match_code "subreg,reg,const_int,truncate") | |
101 | { | |
102 | if (arith_reg_operand (op, mode)) | |
103 | return 1; | |
104 | ||
105 | if (TARGET_SHMEDIA) | |
106 | { | |
107 | /* FIXME: We should be checking whether the CONST_INT fits in a | |
32a7ab3d | 108 | signed 16-bit here, but this causes reload_cse to crash when |
5546ac90 KH |
109 | attempting to transform a sequence of two 64-bit sets of the |
110 | same register from literal constants into a set and an add, | |
111 | when the difference is too wide for an add. */ | |
f3536097 | 112 | if (CONST_INT_P (op) |
32a7ab3d | 113 | || satisfies_constraint_Css (op)) |
5546ac90 KH |
114 | return 1; |
115 | else if (GET_CODE (op) == TRUNCATE | |
f3536097 | 116 | && REG_P (XEXP (op, 0)) |
5546ac90 KH |
117 | && ! system_reg_operand (XEXP (op, 0), VOIDmode) |
118 | && (mode == VOIDmode || mode == GET_MODE (op)) | |
119 | && (GET_MODE_SIZE (GET_MODE (op)) | |
120 | < GET_MODE_SIZE (GET_MODE (XEXP (op, 0)))) | |
121 | && (! FP_REGISTER_P (REGNO (XEXP (op, 0))) | |
122 | || GET_MODE_SIZE (GET_MODE (op)) == 4)) | |
123 | return register_operand (XEXP (op, 0), VOIDmode); | |
124 | else | |
125 | return 0; | |
126 | } | |
32a7ab3d | 127 | else if (satisfies_constraint_I08 (op)) |
5546ac90 KH |
128 | return 1; |
129 | ||
130 | return 0; | |
131 | }) | |
132 | ||
133 | ;; Like above, but for DImode destinations: forbid paradoxical DImode | |
134 | ;; subregs, because this would lead to missing sign extensions when | |
135 | ;; truncating from DImode to SImode. | |
136 | ||
137 | (define_predicate "arith_reg_dest" | |
138 | (match_code "subreg,reg") | |
139 | { | |
140 | if (mode == DImode && GET_CODE (op) == SUBREG | |
141 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8 | |
142 | && TARGET_SHMEDIA) | |
143 | return 0; | |
144 | return arith_reg_operand (op, mode); | |
145 | }) | |
146 | ||
147 | ;; Returns 1 if OP is a normal arithmetic register. | |
148 | ||
149 | (define_predicate "arith_reg_operand" | |
150 | (match_code "subreg,reg,sign_extend") | |
151 | { | |
152 | if (register_operand (op, mode)) | |
153 | { | |
154 | int regno; | |
155 | ||
f3536097 | 156 | if (REG_P (op)) |
5546ac90 | 157 | regno = REGNO (op); |
f3536097 | 158 | else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) |
5546ac90 KH |
159 | regno = REGNO (SUBREG_REG (op)); |
160 | else | |
161 | return 1; | |
162 | ||
163 | return (regno != T_REG && regno != PR_REG | |
164 | && ! TARGET_REGISTER_P (regno) | |
165 | && (regno != FPUL_REG || TARGET_SH4) | |
166 | && regno != MACH_REG && regno != MACL_REG); | |
167 | } | |
168 | /* Allow a no-op sign extension - compare LOAD_EXTEND_OP. | |
169 | We allow SImode here, as not using an FP register is just a matter of | |
170 | proper register allocation. */ | |
171 | if (TARGET_SHMEDIA | |
172 | && GET_MODE (op) == DImode && GET_CODE (op) == SIGN_EXTEND | |
173 | && GET_MODE (XEXP (op, 0)) == SImode | |
174 | && GET_CODE (XEXP (op, 0)) != SUBREG) | |
175 | return register_operand (XEXP (op, 0), VOIDmode); | |
176 | #if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */ | |
177 | if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND | |
178 | && GET_MODE (XEXP (op, 0)) == HImode | |
f3536097 | 179 | && REG_P (XEXP (op, 0)) |
5546ac90 KH |
180 | && REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG) |
181 | return register_operand (XEXP (op, 0), VOIDmode); | |
182 | #endif | |
183 | if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT | |
184 | && GET_CODE (op) == SUBREG | |
185 | && GET_MODE (SUBREG_REG (op)) == DImode | |
186 | && GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND | |
187 | && GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode | |
188 | && GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG) | |
189 | return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode); | |
190 | return 0; | |
191 | }) | |
192 | ||
193 | ;; Returns 1 if OP is a valid source operand for a compare insn. | |
194 | ||
195 | (define_predicate "arith_reg_or_0_operand" | |
196 | (match_code "subreg,reg,const_int,const_vector") | |
197 | { | |
198 | if (arith_reg_operand (op, mode)) | |
199 | return 1; | |
200 | ||
32a7ab3d | 201 | if (satisfies_constraint_Z (op)) |
5546ac90 KH |
202 | return 1; |
203 | ||
204 | return 0; | |
205 | }) | |
206 | ||
207 | ;; TODO: Add a comment here. | |
208 | ||
209 | (define_predicate "binary_float_operator" | |
f289c6a1 KH |
210 | (and (match_code "plus,minus,mult,div") |
211 | (match_test "GET_MODE (op) == mode"))) | |
5546ac90 KH |
212 | |
213 | ;; TODO: Add a comment here. | |
214 | ||
215 | (define_predicate "binary_logical_operator" | |
f289c6a1 KH |
216 | (and (match_code "and,ior,xor") |
217 | (match_test "GET_MODE (op) == mode"))) | |
5546ac90 | 218 | |
f705a9a0 R |
219 | ;; Return 1 of OP is an address suitable for a cache manipulation operation. |
220 | ;; MODE has the meaning as in address_operand. | |
5546ac90 | 221 | |
f705a9a0 | 222 | (define_special_predicate "cache_address_operand" |
5546ac90 KH |
223 | (match_code "plus,reg") |
224 | { | |
225 | if (GET_CODE (op) == PLUS) | |
226 | { | |
f3536097 | 227 | if (!REG_P (XEXP (op, 0))) |
5546ac90 | 228 | return 0; |
f3536097 | 229 | if (!CONST_INT_P (XEXP (op, 1)) |
5546ac90 KH |
230 | || (INTVAL (XEXP (op, 1)) & 31)) |
231 | return 0; | |
232 | } | |
f3536097 | 233 | else if (!REG_P (op)) |
5546ac90 KH |
234 | return 0; |
235 | return address_operand (op, mode); | |
236 | }) | |
237 | ||
238 | ;; Return 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu. | |
239 | ||
240 | (define_predicate "cmp_operand" | |
241 | (match_code "subreg,reg,const_int") | |
242 | { | |
32a7ab3d | 243 | if (satisfies_constraint_N (op)) |
5546ac90 KH |
244 | return 1; |
245 | if (TARGET_SHMEDIA | |
246 | && mode != DImode && GET_CODE (op) == SUBREG | |
247 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4) | |
248 | return 0; | |
249 | return arith_reg_operand (op, mode); | |
250 | }) | |
251 | ||
252 | ;; TODO: Add a comment here. | |
253 | ||
254 | (define_predicate "cmpsi_operand" | |
255 | (match_code "subreg,reg,const_int") | |
256 | { | |
f3536097 | 257 | if (REG_P (op) && REGNO (op) == T_REG |
5546ac90 KH |
258 | && GET_MODE (op) == SImode |
259 | && TARGET_SH1) | |
260 | return 1; | |
261 | return arith_operand (op, mode); | |
262 | }) | |
263 | ||
264 | ;; TODO: Add a comment here. | |
265 | ||
266 | (define_predicate "commutative_float_operator" | |
f289c6a1 KH |
267 | (and (match_code "plus,mult") |
268 | (match_test "GET_MODE (op) == mode"))) | |
5546ac90 KH |
269 | |
270 | ;; TODO: Add a comment here. | |
271 | ||
272 | (define_predicate "equality_comparison_operator" | |
f289c6a1 | 273 | (match_code "eq,ne")) |
5546ac90 KH |
274 | |
275 | ;; TODO: Add a comment here. | |
276 | ||
277 | (define_predicate "extend_reg_operand" | |
278 | (match_code "subreg,reg,truncate") | |
279 | { | |
280 | return (GET_CODE (op) == TRUNCATE | |
281 | ? arith_operand | |
282 | : arith_reg_operand) (op, mode); | |
283 | }) | |
284 | ||
285 | ;; TODO: Add a comment here. | |
286 | ||
287 | (define_predicate "extend_reg_or_0_operand" | |
288 | (match_code "subreg,reg,truncate,const_int") | |
289 | { | |
290 | return (GET_CODE (op) == TRUNCATE | |
291 | ? arith_operand | |
292 | : arith_reg_or_0_operand) (op, mode); | |
293 | }) | |
294 | ||
295 | ;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND. | |
296 | ||
297 | (define_predicate "ext_dest_operand" | |
298 | (match_code "subreg,reg") | |
299 | { | |
300 | return arith_reg_operand (op, mode); | |
301 | }) | |
302 | ||
303 | ;; TODO: Add a comment here. | |
304 | ||
305 | (define_predicate "fp_arith_reg_dest" | |
306 | (match_code "subreg,reg") | |
307 | { | |
308 | if (mode == DImode && GET_CODE (op) == SUBREG | |
309 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8) | |
310 | return 0; | |
311 | return fp_arith_reg_operand (op, mode); | |
312 | }) | |
313 | ||
314 | ;; TODO: Add a comment here. | |
315 | ||
316 | (define_predicate "fp_arith_reg_operand" | |
317 | (match_code "subreg,reg") | |
318 | { | |
319 | if (register_operand (op, mode)) | |
320 | { | |
321 | int regno; | |
322 | ||
f3536097 | 323 | if (REG_P (op)) |
5546ac90 | 324 | regno = REGNO (op); |
f3536097 | 325 | else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) |
5546ac90 KH |
326 | regno = REGNO (SUBREG_REG (op)); |
327 | else | |
328 | return 1; | |
329 | ||
330 | return (regno >= FIRST_PSEUDO_REGISTER | |
331 | || FP_REGISTER_P (regno)); | |
332 | } | |
333 | return 0; | |
334 | }) | |
335 | ||
336 | ;; TODO: Add a comment here. | |
337 | ||
338 | (define_predicate "fpscr_operand" | |
339 | (match_code "reg") | |
340 | { | |
f3536097 | 341 | return (REG_P (op) |
5546ac90 KH |
342 | && (REGNO (op) == FPSCR_REG |
343 | || (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
344 | && !(reload_in_progress || reload_completed))) | |
345 | && GET_MODE (op) == PSImode); | |
346 | }) | |
347 | ||
348 | ;; TODO: Add a comment here. | |
349 | ||
350 | (define_predicate "fpul_operand" | |
351 | (match_code "reg") | |
352 | { | |
353 | if (TARGET_SHMEDIA) | |
354 | return fp_arith_reg_operand (op, mode); | |
355 | ||
f3536097 | 356 | return (REG_P (op) |
5546ac90 KH |
357 | && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER) |
358 | && GET_MODE (op) == mode); | |
359 | }) | |
360 | ||
361 | ;; TODO: Add a comment here. | |
362 | ||
363 | (define_predicate "general_extend_operand" | |
364 | (match_code "subreg,reg,mem,truncate") | |
365 | { | |
366 | return (GET_CODE (op) == TRUNCATE | |
367 | ? arith_operand | |
368 | : nonimmediate_operand) (op, mode); | |
369 | }) | |
370 | ||
24c18ad8 OE |
371 | ;; Returns 1 if OP is a simple register address. |
372 | (define_predicate "simple_mem_operand" | |
373 | (and (match_code "mem") | |
374 | (match_test "arith_reg_operand (XEXP (op, 0), SImode)"))) | |
375 | ||
376 | ;; Returns 1 if OP is a valid displacement address. | |
377 | (define_predicate "displacement_mem_operand" | |
378 | (and (match_code "mem") | |
379 | (match_test "GET_CODE (XEXP (op, 0)) == PLUS") | |
380 | (match_test "arith_reg_operand (XEXP (XEXP (op, 0), 0), SImode)") | |
381 | (match_test "sh_legitimate_index_p (GET_MODE (op), | |
382 | XEXP (XEXP (op, 0), 1), | |
383 | TARGET_SH2A, true)"))) | |
384 | ||
385 | ;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn. | |
386 | (define_predicate "zero_extend_movu_operand" | |
387 | (and (match_operand 0 "displacement_mem_operand") | |
388 | (match_test "GET_MODE (op) == QImode || GET_MODE (op) == HImode"))) | |
389 | ||
33344a62 OE |
390 | ;; Returns 1 if the operand can be used in a zero_extend. |
391 | (define_predicate "zero_extend_operand" | |
392 | (ior (and (match_test "TARGET_SHMEDIA") | |
393 | (match_operand 0 "general_extend_operand")) | |
394 | (and (match_test "! TARGET_SHMEDIA") | |
24c18ad8 OE |
395 | (match_operand 0 "arith_reg_operand")) |
396 | (and (match_test "TARGET_SH2A") | |
397 | (match_operand 0 "zero_extend_movu_operand")))) | |
33344a62 | 398 | |
5546ac90 KH |
399 | ;; Returns 1 if OP can be source of a simple move operation. Same as |
400 | ;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as | |
401 | ;; are subregs of system registers. | |
402 | ||
403 | (define_predicate "general_movsrc_operand" | |
404 | (match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,const,const_vector") | |
405 | { | |
ef812306 OE |
406 | if (t_reg_operand (op, mode)) |
407 | return 0; | |
408 | ||
f3536097 | 409 | if (MEM_P (op)) |
5546ac90 KH |
410 | { |
411 | rtx inside = XEXP (op, 0); | |
412 | if (GET_CODE (inside) == CONST) | |
413 | inside = XEXP (inside, 0); | |
414 | ||
415 | if (GET_CODE (inside) == LABEL_REF) | |
416 | return 1; | |
417 | ||
418 | if (GET_CODE (inside) == PLUS | |
419 | && GET_CODE (XEXP (inside, 0)) == LABEL_REF | |
f3536097 | 420 | && CONST_INT_P (XEXP (inside, 1))) |
5546ac90 KH |
421 | return 1; |
422 | ||
423 | /* Only post inc allowed. */ | |
424 | if (GET_CODE (inside) == PRE_DEC) | |
425 | return 0; | |
426 | } | |
427 | ||
a700b5f0 | 428 | if ((mode == QImode || mode == HImode) |
409fed48 | 429 | && mode == GET_MODE (op) |
a700b5f0 KK |
430 | && (MEM_P (op) |
431 | || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))))) | |
432 | { | |
433 | rtx x = XEXP ((MEM_P (op) ? op : SUBREG_REG (op)), 0); | |
434 | ||
435 | if (GET_CODE (x) == PLUS | |
436 | && REG_P (XEXP (x, 0)) | |
437 | && CONST_INT_P (XEXP (x, 1))) | |
8c2a3f3b | 438 | return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false); |
a700b5f0 KK |
439 | } |
440 | ||
5546ac90 KH |
441 | if (TARGET_SHMEDIA |
442 | && (GET_CODE (op) == PARALLEL || GET_CODE (op) == CONST_VECTOR) | |
443 | && sh_rep_vec (op, mode)) | |
444 | return 1; | |
445 | if (TARGET_SHMEDIA && 1 | |
446 | && GET_CODE (op) == SUBREG && GET_MODE (op) == mode | |
447 | && SUBREG_REG (op) == const0_rtx && subreg_lowpart_p (op)) | |
448 | /* FIXME */ abort (); /* return 1; */ | |
449 | return general_operand (op, mode); | |
450 | }) | |
451 | ||
284c32cf | 452 | ;; Returns 1 if OP is a MEM that does not use displacement addressing. |
344332e8 OE |
453 | |
454 | (define_predicate "movsrc_no_disp_mem_operand" | |
284c32cf | 455 | (match_code "mem") |
344332e8 | 456 | { |
284c32cf | 457 | return general_movsrc_operand (op, mode) && satisfies_constraint_Snd (op); |
344332e8 OE |
458 | }) |
459 | ||
5546ac90 KH |
460 | ;; Returns 1 if OP can be a destination of a move. Same as |
461 | ;; general_operand, but no preinc allowed. | |
462 | ||
463 | (define_predicate "general_movdst_operand" | |
464 | (match_code "subreg,reg,mem") | |
465 | { | |
ef812306 OE |
466 | if (t_reg_operand (op, mode)) |
467 | return 0; | |
468 | ||
5546ac90 | 469 | /* Only pre dec allowed. */ |
f3536097 | 470 | if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC) |
5546ac90 KH |
471 | return 0; |
472 | if (mode == DImode && TARGET_SHMEDIA && GET_CODE (op) == SUBREG | |
473 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8 | |
fae61228 | 474 | && ! (reload_in_progress || reload_completed)) |
5546ac90 KH |
475 | return 0; |
476 | ||
a700b5f0 | 477 | if ((mode == QImode || mode == HImode) |
409fed48 | 478 | && mode == GET_MODE (op) |
a700b5f0 KK |
479 | && (MEM_P (op) |
480 | || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))))) | |
481 | { | |
482 | rtx x = XEXP ((MEM_P (op) ? op : SUBREG_REG (op)), 0); | |
483 | ||
484 | if (GET_CODE (x) == PLUS | |
485 | && REG_P (XEXP (x, 0)) | |
486 | && CONST_INT_P (XEXP (x, 1))) | |
8c2a3f3b | 487 | return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false); |
a700b5f0 KK |
488 | } |
489 | ||
5546ac90 KH |
490 | return general_operand (op, mode); |
491 | }) | |
492 | ||
c11c09f9 KP |
493 | ;; Returns 1 if OP is a POST_INC on stack pointer register. |
494 | ||
495 | (define_predicate "sh_no_delay_pop_operand" | |
496 | (match_code "mem") | |
497 | { | |
498 | rtx inside; | |
499 | inside = XEXP (op, 0); | |
500 | ||
501 | if (GET_CODE (op) == MEM && GET_MODE (op) == SImode | |
502 | && GET_CODE (inside) == POST_INC | |
503 | && GET_CODE (XEXP (inside, 0)) == REG | |
504 | && REGNO (XEXP (inside, 0)) == SP_REG) | |
505 | return 1; | |
506 | ||
507 | return 0; | |
508 | }) | |
509 | ||
5546ac90 KH |
510 | ;; Returns 1 if OP is a MEM that can be source of a simple move operation. |
511 | ||
512 | (define_predicate "unaligned_load_operand" | |
513 | (match_code "mem") | |
514 | { | |
515 | rtx inside; | |
516 | ||
f3536097 | 517 | if (!MEM_P (op) || GET_MODE (op) != mode) |
5546ac90 KH |
518 | return 0; |
519 | ||
520 | inside = XEXP (op, 0); | |
521 | ||
522 | if (GET_CODE (inside) == POST_INC) | |
523 | inside = XEXP (inside, 0); | |
524 | ||
f3536097 | 525 | if (REG_P (inside)) |
5546ac90 KH |
526 | return 1; |
527 | ||
528 | return 0; | |
529 | }) | |
530 | ||
b67b3838 OE |
531 | ;; Returns 1 if OP is a MEM that can be used in "index_disp" combiner |
532 | ;; patterns. | |
533 | (define_predicate "mem_index_disp_operand" | |
534 | (match_code "mem") | |
535 | { | |
536 | rtx plus0_rtx, plus1_rtx, mult_rtx; | |
537 | ||
538 | plus0_rtx = XEXP (op, 0); | |
539 | if (GET_CODE (plus0_rtx) != PLUS) | |
540 | return 0; | |
541 | ||
542 | plus1_rtx = XEXP (plus0_rtx, 0); | |
543 | if (GET_CODE (plus1_rtx) != PLUS) | |
544 | return 0; | |
05852a5f OE |
545 | if (! arith_reg_operand (XEXP (plus1_rtx, 1), GET_MODE (XEXP (plus1_rtx, 1)))) |
546 | return 0; | |
b67b3838 OE |
547 | |
548 | mult_rtx = XEXP (plus1_rtx, 0); | |
549 | if (GET_CODE (mult_rtx) != MULT) | |
550 | return 0; | |
05852a5f OE |
551 | if (! arith_reg_operand (XEXP (mult_rtx, 0), GET_MODE (XEXP (mult_rtx, 0))) |
552 | || ! CONST_INT_P (XEXP (mult_rtx, 1))) | |
553 | return 0; | |
554 | ||
555 | return exact_log2 (INTVAL (XEXP (mult_rtx, 1))) > 0 | |
b67b3838 OE |
556 | && sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true); |
557 | }) | |
558 | ||
5546ac90 KH |
559 | ;; TODO: Add a comment here. |
560 | ||
561 | (define_predicate "greater_comparison_operator" | |
f289c6a1 | 562 | (match_code "gt,ge,gtu,geu")) |
5546ac90 KH |
563 | |
564 | ;; TODO: Add a comment here. | |
565 | ||
566 | (define_predicate "inqhi_operand" | |
567 | (match_code "truncate") | |
568 | { | |
569 | if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op)) | |
570 | return 0; | |
571 | op = XEXP (op, 0); | |
572 | /* Can't use true_regnum here because copy_cost wants to know about | |
573 | SECONDARY_INPUT_RELOAD_CLASS. */ | |
f3536097 | 574 | return REG_P (op) && FP_REGISTER_P (REGNO (op)); |
5546ac90 KH |
575 | }) |
576 | ||
577 | ;; TODO: Add a comment here. | |
578 | ||
579 | (define_special_predicate "int_gpr_dest" | |
580 | (match_code "subreg,reg") | |
581 | { | |
582 | enum machine_mode op_mode = GET_MODE (op); | |
583 | ||
584 | if (GET_MODE_CLASS (op_mode) != MODE_INT | |
585 | || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD) | |
586 | return 0; | |
587 | if (! reload_completed) | |
588 | return 0; | |
589 | return true_regnum (op) <= LAST_GENERAL_REG; | |
590 | }) | |
591 | ||
592 | ;; TODO: Add a comment here. | |
593 | ||
594 | (define_predicate "less_comparison_operator" | |
f289c6a1 | 595 | (match_code "lt,le,ltu,leu")) |
5546ac90 KH |
596 | |
597 | ;; Returns 1 if OP is a valid source operand for a logical operation. | |
598 | ||
599 | (define_predicate "logical_operand" | |
600 | (match_code "subreg,reg,const_int") | |
601 | { | |
602 | if (TARGET_SHMEDIA | |
603 | && mode != DImode && GET_CODE (op) == SUBREG | |
604 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4) | |
605 | return 0; | |
606 | ||
607 | if (arith_reg_operand (op, mode)) | |
608 | return 1; | |
609 | ||
610 | if (TARGET_SHMEDIA) | |
611 | { | |
32a7ab3d | 612 | if (satisfies_constraint_I10 (op)) |
5546ac90 KH |
613 | return 1; |
614 | else | |
615 | return 0; | |
616 | } | |
32a7ab3d | 617 | else if (satisfies_constraint_K08 (op)) |
5546ac90 KH |
618 | return 1; |
619 | ||
620 | return 0; | |
621 | }) | |
622 | ||
5e204a6e OE |
623 | ;; Like logical_operand but allows additional constant values which can be |
624 | ;; done with zero extensions. Used for the second operand of and insns. | |
625 | (define_predicate "logical_and_operand" | |
626 | (match_code "subreg,reg,const_int") | |
627 | { | |
628 | if (logical_operand (op, mode)) | |
629 | return 1; | |
630 | ||
631 | if (! TARGET_SHMEDIA | |
632 | && (satisfies_constraint_Jmb (op) || satisfies_constraint_Jmw (op))) | |
633 | return 1; | |
634 | ||
635 | return 0; | |
636 | }) | |
637 | ||
5546ac90 KH |
638 | ;; TODO: Add a comment here. |
639 | ||
640 | (define_predicate "logical_operator" | |
f289c6a1 | 641 | (match_code "and,ior,xor")) |
5546ac90 KH |
642 | |
643 | ;; Like arith_reg_operand, but for register source operands of narrow | |
644 | ;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs. | |
645 | ||
646 | (define_predicate "logical_reg_operand" | |
647 | (match_code "subreg,reg") | |
648 | { | |
649 | if (TARGET_SHMEDIA | |
650 | && GET_CODE (op) == SUBREG | |
651 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4 | |
652 | && mode != DImode) | |
653 | return 0; | |
654 | return arith_reg_operand (op, mode); | |
655 | }) | |
656 | ||
657 | ;; TODO: Add a comment here. | |
658 | ||
659 | (define_predicate "mextr_bit_offset" | |
660 | (match_code "const_int") | |
661 | { | |
662 | HOST_WIDE_INT i; | |
663 | ||
f3536097 | 664 | if (!CONST_INT_P (op)) |
5546ac90 KH |
665 | return 0; |
666 | i = INTVAL (op); | |
667 | return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0; | |
668 | }) | |
669 | ||
670 | ;; TODO: Add a comment here. | |
671 | ||
672 | (define_predicate "minuend_operand" | |
673 | (match_code "subreg,reg,truncate,const_int") | |
674 | { | |
675 | return op == constm1_rtx || extend_reg_or_0_operand (op, mode); | |
676 | }) | |
677 | ||
678 | ;; TODO: Add a comment here. | |
679 | ||
680 | (define_predicate "noncommutative_float_operator" | |
f289c6a1 KH |
681 | (and (match_code "minus,div") |
682 | (match_test "GET_MODE (op) == mode"))) | |
5546ac90 | 683 | |
f90b7a5a PB |
684 | ;; UNORDERED is only supported on SHMEDIA. |
685 | ||
686 | (define_predicate "sh_float_comparison_operator" | |
687 | (ior (match_operand 0 "ordered_comparison_operator") | |
688 | (and (match_test "TARGET_SHMEDIA") | |
689 | (match_code "unordered")))) | |
690 | ||
691 | (define_predicate "shmedia_cbranch_comparison_operator" | |
692 | (ior (match_operand 0 "equality_comparison_operator") | |
693 | (match_operand 0 "greater_comparison_operator"))) | |
694 | ||
5546ac90 KH |
695 | ;; TODO: Add a comment here. |
696 | ||
697 | (define_predicate "sh_const_vec" | |
698 | (match_code "const_vector") | |
699 | { | |
700 | int i; | |
701 | ||
702 | if (GET_CODE (op) != CONST_VECTOR | |
703 | || (GET_MODE (op) != mode && mode != VOIDmode)) | |
704 | return 0; | |
705 | i = XVECLEN (op, 0) - 1; | |
706 | for (; i >= 0; i--) | |
f3536097 | 707 | if (!CONST_INT_P (XVECEXP (op, 0, i))) |
5546ac90 KH |
708 | return 0; |
709 | return 1; | |
710 | }) | |
711 | ||
712 | ;; Determine if OP is a constant vector matching MODE with only one | |
713 | ;; element that is not a sign extension. Two byte-sized elements | |
714 | ;; count as one. | |
715 | ||
716 | (define_predicate "sh_1el_vec" | |
717 | (match_code "const_vector") | |
718 | { | |
719 | int unit_size; | |
720 | int i, last, least, sign_ix; | |
721 | rtx sign; | |
722 | ||
723 | if (GET_CODE (op) != CONST_VECTOR | |
724 | || (GET_MODE (op) != mode && mode != VOIDmode)) | |
725 | return 0; | |
726 | /* Determine numbers of last and of least significant elements. */ | |
727 | last = XVECLEN (op, 0) - 1; | |
728 | least = TARGET_LITTLE_ENDIAN ? 0 : last; | |
f3536097 | 729 | if (!CONST_INT_P (XVECEXP (op, 0, least))) |
5546ac90 KH |
730 | return 0; |
731 | sign_ix = least; | |
732 | if (GET_MODE_UNIT_SIZE (mode) == 1) | |
733 | sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1; | |
f3536097 | 734 | if (!CONST_INT_P (XVECEXP (op, 0, sign_ix))) |
5546ac90 KH |
735 | return 0; |
736 | unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op)); | |
737 | sign = (INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1) | |
738 | ? constm1_rtx : const0_rtx); | |
739 | i = XVECLEN (op, 0) - 1; | |
740 | do | |
741 | if (i != least && i != sign_ix && XVECEXP (op, 0, i) != sign) | |
742 | return 0; | |
743 | while (--i); | |
744 | return 1; | |
745 | }) | |
746 | ||
747 | ;; Like register_operand, but take into account that SHMEDIA can use | |
748 | ;; the constant zero like a general register. | |
749 | ||
750 | (define_predicate "sh_register_operand" | |
ac42ec79 | 751 | (match_code "reg,subreg,const_int,const_double") |
5546ac90 KH |
752 | { |
753 | if (op == CONST0_RTX (mode) && TARGET_SHMEDIA) | |
754 | return 1; | |
755 | return register_operand (op, mode); | |
756 | }) | |
757 | ||
758 | ;; TODO: Add a comment here. | |
759 | ||
760 | (define_predicate "sh_rep_vec" | |
b4060d3f | 761 | (match_code "const_vector,parallel") |
5546ac90 KH |
762 | { |
763 | int i; | |
764 | rtx x, y; | |
765 | ||
766 | if ((GET_CODE (op) != CONST_VECTOR && GET_CODE (op) != PARALLEL) | |
767 | || (GET_MODE (op) != mode && mode != VOIDmode)) | |
768 | return 0; | |
769 | i = XVECLEN (op, 0) - 2; | |
770 | x = XVECEXP (op, 0, i + 1); | |
771 | if (GET_MODE_UNIT_SIZE (mode) == 1) | |
772 | { | |
773 | y = XVECEXP (op, 0, i); | |
774 | for (i -= 2; i >= 0; i -= 2) | |
775 | if (! rtx_equal_p (XVECEXP (op, 0, i + 1), x) | |
776 | || ! rtx_equal_p (XVECEXP (op, 0, i), y)) | |
777 | return 0; | |
778 | } | |
779 | else | |
780 | for (; i >= 0; i--) | |
781 | if (XVECEXP (op, 0, i) != x) | |
782 | return 0; | |
783 | return 1; | |
784 | }) | |
785 | ||
786 | ;; TODO: Add a comment here. | |
787 | ||
788 | (define_predicate "shift_count_operand" | |
789 | (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,zero_extend,sign_extend") | |
790 | { | |
d8a48c21 OE |
791 | /* Allow T_REG as shift count for dynamic shifts, although it is not |
792 | really possible. It will then be copied to a general purpose reg. */ | |
793 | if (! TARGET_SHMEDIA) | |
aadb5b43 OE |
794 | return const_int_operand (op, mode) || arith_reg_operand (op, mode) |
795 | || (TARGET_DYNSHIFT && t_reg_operand (op, mode)); | |
d8a48c21 | 796 | |
5546ac90 | 797 | return (CONSTANT_P (op) |
f3536097 | 798 | ? (CONST_INT_P (op) |
5546ac90 KH |
799 | ? (unsigned) INTVAL (op) < GET_MODE_BITSIZE (mode) |
800 | : nonmemory_operand (op, mode)) | |
801 | : shift_count_reg_operand (op, mode)); | |
802 | }) | |
803 | ||
804 | ;; TODO: Add a comment here. | |
805 | ||
806 | (define_predicate "shift_count_reg_operand" | |
807 | (match_code "subreg,reg,zero_extend,sign_extend") | |
808 | { | |
809 | if ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND | |
810 | || (GET_CODE (op) == SUBREG && SUBREG_BYTE (op) == 0)) | |
811 | && (mode == VOIDmode || mode == GET_MODE (op)) | |
812 | && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6 | |
813 | && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT) | |
814 | { | |
815 | mode = VOIDmode; | |
816 | do | |
817 | op = XEXP (op, 0); | |
818 | while ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND | |
819 | || GET_CODE (op) == TRUNCATE) | |
820 | && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6 | |
821 | && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT); | |
822 | ||
823 | } | |
824 | return arith_reg_operand (op, mode); | |
825 | }) | |
826 | ||
6e01d526 OE |
827 | ;; Predicates for matching operands that are constant shift |
828 | ;; amounts 1, 2, 8, 16. | |
d8a48c21 OE |
829 | (define_predicate "p27_shift_count_operand" |
830 | (and (match_code "const_int") | |
831 | (match_test "satisfies_constraint_P27 (op)"))) | |
832 | ||
833 | (define_predicate "not_p27_shift_count_operand" | |
834 | (and (match_code "const_int") | |
835 | (match_test "! satisfies_constraint_P27 (op)"))) | |
836 | ||
6e01d526 OE |
837 | ;; For right shifts the constant 1 is a special case because the shlr insn |
838 | ;; clobbers the T_REG and is handled by the T_REG clobbering version of the | |
839 | ;; insn, which is also used for non-P27 shift sequences. | |
840 | (define_predicate "p27_rshift_count_operand" | |
841 | (and (match_code "const_int") | |
842 | (match_test "satisfies_constraint_P27 (op)") | |
843 | (match_test "! satisfies_constraint_M (op)"))) | |
844 | ||
845 | (define_predicate "not_p27_rshift_count_operand" | |
846 | (and (match_code "const_int") | |
847 | (ior (match_test "! satisfies_constraint_P27 (op)") | |
848 | (match_test "satisfies_constraint_M (op)")))) | |
849 | ||
5546ac90 KH |
850 | ;; TODO: Add a comment here. |
851 | ||
852 | (define_predicate "shift_operator" | |
f289c6a1 | 853 | (match_code "ashift,ashiftrt,lshiftrt")) |
5546ac90 KH |
854 | |
855 | ;; TODO: Add a comment here. | |
856 | ||
857 | (define_predicate "symbol_ref_operand" | |
f289c6a1 | 858 | (match_code "symbol_ref")) |
5546ac90 KH |
859 | |
860 | ;; Same as target_reg_operand, except that label_refs and symbol_refs | |
861 | ;; are accepted before reload. | |
862 | ||
863 | (define_special_predicate "target_operand" | |
864 | (match_code "subreg,reg,label_ref,symbol_ref,const,unspec") | |
865 | { | |
866 | if (mode != VOIDmode && mode != Pmode) | |
867 | return 0; | |
868 | ||
869 | if ((GET_MODE (op) == Pmode || GET_MODE (op) == VOIDmode) | |
32a7ab3d | 870 | && satisfies_constraint_Csy (op)) |
5546ac90 KH |
871 | return ! reload_completed; |
872 | ||
873 | return target_reg_operand (op, mode); | |
874 | }) | |
875 | ||
876 | ;; Accept pseudos and branch target registers. | |
877 | ||
878 | (define_special_predicate "target_reg_operand" | |
879 | (match_code "subreg,reg") | |
880 | { | |
881 | if (mode == VOIDmode | |
882 | ? GET_MODE (op) != Pmode && GET_MODE (op) != PDImode | |
883 | : mode != GET_MODE (op)) | |
884 | return 0; | |
885 | ||
886 | if (GET_CODE (op) == SUBREG) | |
887 | op = XEXP (op, 0); | |
888 | ||
f3536097 | 889 | if (!REG_P (op)) |
5546ac90 KH |
890 | return 0; |
891 | ||
892 | /* We must protect ourselves from matching pseudos that are virtual | |
893 | register, because they will eventually be replaced with hardware | |
894 | registers that aren't branch-target registers. */ | |
895 | if (REGNO (op) > LAST_VIRTUAL_REGISTER | |
896 | || TARGET_REGISTER_P (REGNO (op))) | |
897 | return 1; | |
898 | ||
899 | return 0; | |
900 | }) | |
901 | ||
902 | ;; TODO: Add a comment here. | |
903 | ||
904 | (define_special_predicate "trunc_hi_operand" | |
905 | (match_code "subreg,reg,truncate") | |
906 | { | |
907 | enum machine_mode op_mode = GET_MODE (op); | |
908 | ||
909 | if (op_mode != SImode && op_mode != DImode | |
910 | && op_mode != V4HImode && op_mode != V2SImode) | |
911 | return 0; | |
912 | return extend_reg_operand (op, mode); | |
913 | }) | |
914 | ||
f705a9a0 | 915 | ;; Return 1 of OP is an address suitable for an unaligned access instruction. |
5546ac90 | 916 | |
f705a9a0 | 917 | (define_special_predicate "ua_address_operand" |
5546ac90 KH |
918 | (match_code "subreg,reg,plus") |
919 | { | |
920 | if (GET_CODE (op) == PLUS | |
32a7ab3d | 921 | && (! satisfies_constraint_I06 (XEXP (op, 1)))) |
5546ac90 KH |
922 | return 0; |
923 | return address_operand (op, QImode); | |
924 | }) | |
925 | ||
926 | ;; TODO: Add a comment here. | |
927 | ||
928 | (define_predicate "ua_offset" | |
929 | (match_code "const_int") | |
930 | { | |
32a7ab3d | 931 | return satisfies_constraint_I06 (op); |
5546ac90 KH |
932 | }) |
933 | ||
934 | ;; TODO: Add a comment here. | |
935 | ||
936 | (define_predicate "unary_float_operator" | |
f289c6a1 KH |
937 | (and (match_code "abs,neg,sqrt") |
938 | (match_test "GET_MODE (op) == mode"))) | |
5546ac90 KH |
939 | |
940 | ;; Return 1 if OP is a valid source operand for xor. | |
941 | ||
942 | (define_predicate "xor_operand" | |
943 | (match_code "subreg,reg,const_int") | |
944 | { | |
f3536097 | 945 | if (CONST_INT_P (op)) |
5546ac90 | 946 | return (TARGET_SHMEDIA |
32a7ab3d | 947 | ? (satisfies_constraint_I06 (op) |
b3a13419 | 948 | || (!can_create_pseudo_p () && INTVAL (op) == 0xff)) |
32a7ab3d | 949 | : satisfies_constraint_K08 (op)); |
5546ac90 KH |
950 | if (TARGET_SHMEDIA |
951 | && mode != DImode && GET_CODE (op) == SUBREG | |
952 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4) | |
953 | return 0; | |
954 | return arith_reg_operand (op, mode); | |
955 | }) | |
9eb3a0dd N |
956 | |
957 | (define_predicate "bitwise_memory_operand" | |
958 | (match_code "mem") | |
959 | { | |
f3536097 | 960 | if (MEM_P (op)) |
9eb3a0dd N |
961 | { |
962 | if (REG_P (XEXP (op, 0))) | |
963 | return 1; | |
964 | ||
965 | if (GET_CODE (XEXP (op, 0)) == PLUS | |
f3536097 | 966 | && REG_P (XEXP (XEXP (op, 0), 0)) |
9eb3a0dd N |
967 | && satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1))) |
968 | return 1; | |
969 | } | |
970 | return 0; | |
971 | }) | |
c11394f8 OE |
972 | |
973 | ;; The atomic_* operand predicates are used for the atomic patterns. | |
974 | ;; Depending on the particular pattern some operands can be immediate | |
975 | ;; values. Using these predicates avoids the usage of 'force_reg' in the | |
976 | ;; expanders. | |
977 | (define_predicate "atomic_arith_operand" | |
978 | (ior (match_code "subreg,reg") | |
979 | (and (match_test "satisfies_constraint_I08 (op)") | |
980 | (match_test "mode != QImode") | |
981 | (match_test "mode != HImode") | |
982 | (match_test "TARGET_SH4A_ARCH")))) | |
983 | ||
984 | (define_predicate "atomic_logical_operand" | |
985 | (ior (match_code "subreg,reg") | |
986 | (and (match_test "satisfies_constraint_K08 (op)") | |
987 | (match_test "mode != QImode") | |
988 | (match_test "mode != HImode") | |
989 | (match_test "TARGET_SH4A_ARCH")))) | |
990 | ||
f031c344 OE |
991 | ;; A predicate describing the T bit register in any form. |
992 | (define_predicate "t_reg_operand" | |
993 | (match_code "reg,subreg,sign_extend,zero_extend") | |
994 | { | |
995 | switch (GET_CODE (op)) | |
996 | { | |
997 | case REG: | |
998 | return REGNO (op) == T_REG; | |
999 | ||
1000 | case SUBREG: | |
312f9b9d | 1001 | return REG_P (SUBREG_REG (op)) && REGNO (SUBREG_REG (op)) == T_REG; |
f031c344 OE |
1002 | |
1003 | case ZERO_EXTEND: | |
1004 | case SIGN_EXTEND: | |
1005 | return GET_CODE (XEXP (op, 0)) == SUBREG | |
312f9b9d | 1006 | && REG_P (SUBREG_REG (XEXP (op, 0))) |
f031c344 OE |
1007 | && REGNO (SUBREG_REG (XEXP (op, 0))) == T_REG; |
1008 | ||
1009 | default: | |
1010 | return 0; | |
1011 | } | |
1012 | }) | |
1013 | ||
1014 | ;; A predicate describing a negated T bit register. | |
1015 | (define_predicate "negt_reg_operand" | |
1016 | (match_code "subreg,xor") | |
1017 | { | |
1018 | switch (GET_CODE (op)) | |
1019 | { | |
1020 | case XOR: | |
1021 | return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))) | |
1022 | && satisfies_constraint_M (XEXP (op, 1)); | |
1023 | ||
1024 | case SUBREG: | |
1025 | return negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))); | |
1026 | ||
1027 | default: | |
1028 | return 0; | |
1029 | } | |
1030 | }) |