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5546ac90 | 1 | ;; Predicate definitions for Renesas / SuperH SH. |
23a5b65a | 2 | ;; Copyright (C) 2005-2014 Free Software Foundation, Inc. |
5546ac90 KH |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
5546ac90 KH |
9 | ;; any later version. |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
5546ac90 KH |
19 | |
20 | ;; TODO: Add a comment here. | |
73a4d10b R |
21 | (define_predicate "trapping_target_operand" |
22 | (match_code "if_then_else") | |
23 | { | |
5a82ecd9 | 24 | rtx cond, mem, res, tar, and_expr; |
73a4d10b R |
25 | |
26 | if (GET_MODE (op) != PDImode) | |
27 | return 0; | |
28 | cond = XEXP (op, 0); | |
29 | mem = XEXP (op, 1); | |
30 | res = XEXP (op, 2); | |
f3536097 | 31 | if (!MEM_P (mem) |
73a4d10b R |
32 | || (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE)) |
33 | return 0; | |
34 | tar = XEXP (res, 0); | |
35 | if (!rtx_equal_p (XEXP (mem, 0), tar) | |
36 | || GET_MODE (tar) != Pmode) | |
37 | return 0; | |
38 | if (GET_CODE (cond) == CONST) | |
39 | { | |
40 | cond = XEXP (cond, 0); | |
32a7ab3d | 41 | if (!satisfies_constraint_Csy (tar)) |
73a4d10b R |
42 | return 0; |
43 | if (GET_CODE (tar) == CONST) | |
44 | tar = XEXP (tar, 0); | |
45 | } | |
46 | else if (!arith_reg_operand (tar, VOIDmode) | |
32a7ab3d | 47 | && ! satisfies_constraint_Csy (tar)) |
73a4d10b R |
48 | return 0; |
49 | if (GET_CODE (cond) != EQ) | |
50 | return 0; | |
5a82ecd9 ILT |
51 | and_expr = XEXP (cond, 0); |
52 | return (GET_CODE (and_expr) == AND | |
53 | && rtx_equal_p (XEXP (and_expr, 0), tar) | |
54 | && CONST_INT_P (XEXP (and_expr, 1)) | |
f3536097 | 55 | && CONST_INT_P (XEXP (cond, 1)) |
5a82ecd9 | 56 | && INTVAL (XEXP (and_expr, 1)) == 3 |
73a4d10b R |
57 | && INTVAL (XEXP (cond, 1)) == 3); |
58 | }) | |
5546ac90 | 59 | |
50fe8924 | 60 | ;; A logical operand that can be used in an shmedia and insn. |
5546ac90 KH |
61 | (define_predicate "and_operand" |
62 | (match_code "subreg,reg,const_int") | |
63 | { | |
64 | if (logical_operand (op, mode)) | |
65 | return 1; | |
66 | ||
67 | /* Check mshflo.l / mshflhi.l opportunities. */ | |
68 | if (TARGET_SHMEDIA | |
69 | && mode == DImode | |
32a7ab3d | 70 | && satisfies_constraint_J16 (op)) |
5546ac90 KH |
71 | return 1; |
72 | ||
73 | return 0; | |
74 | }) | |
75 | ||
c2acaf06 KH |
76 | ;; Like arith_reg_dest, but this predicate is defined with |
77 | ;; define_special_predicate, not define_predicate. | |
5546ac90 KH |
78 | (define_special_predicate "any_arith_reg_dest" |
79 | (match_code "subreg,reg") | |
80 | { | |
81 | return arith_reg_dest (op, mode); | |
82 | }) | |
83 | ||
c2acaf06 KH |
84 | ;; Like register_operand, but this predicate is defined with |
85 | ;; define_special_predicate, not define_predicate. | |
5546ac90 KH |
86 | (define_special_predicate "any_register_operand" |
87 | (match_code "subreg,reg") | |
88 | { | |
89 | return register_operand (op, mode); | |
90 | }) | |
91 | ||
92 | ;; Returns 1 if OP is a valid source operand for an arithmetic insn. | |
5546ac90 KH |
93 | (define_predicate "arith_operand" |
94 | (match_code "subreg,reg,const_int,truncate") | |
95 | { | |
96 | if (arith_reg_operand (op, mode)) | |
97 | return 1; | |
98 | ||
99 | if (TARGET_SHMEDIA) | |
100 | { | |
101 | /* FIXME: We should be checking whether the CONST_INT fits in a | |
32a7ab3d | 102 | signed 16-bit here, but this causes reload_cse to crash when |
5546ac90 KH |
103 | attempting to transform a sequence of two 64-bit sets of the |
104 | same register from literal constants into a set and an add, | |
105 | when the difference is too wide for an add. */ | |
f3536097 | 106 | if (CONST_INT_P (op) |
32a7ab3d | 107 | || satisfies_constraint_Css (op)) |
5546ac90 KH |
108 | return 1; |
109 | else if (GET_CODE (op) == TRUNCATE | |
f3536097 | 110 | && REG_P (XEXP (op, 0)) |
5546ac90 KH |
111 | && ! system_reg_operand (XEXP (op, 0), VOIDmode) |
112 | && (mode == VOIDmode || mode == GET_MODE (op)) | |
113 | && (GET_MODE_SIZE (GET_MODE (op)) | |
114 | < GET_MODE_SIZE (GET_MODE (XEXP (op, 0)))) | |
115 | && (! FP_REGISTER_P (REGNO (XEXP (op, 0))) | |
116 | || GET_MODE_SIZE (GET_MODE (op)) == 4)) | |
117 | return register_operand (XEXP (op, 0), VOIDmode); | |
118 | else | |
119 | return 0; | |
120 | } | |
32a7ab3d | 121 | else if (satisfies_constraint_I08 (op)) |
5546ac90 KH |
122 | return 1; |
123 | ||
124 | return 0; | |
125 | }) | |
126 | ||
127 | ;; Like above, but for DImode destinations: forbid paradoxical DImode | |
128 | ;; subregs, because this would lead to missing sign extensions when | |
129 | ;; truncating from DImode to SImode. | |
5546ac90 KH |
130 | (define_predicate "arith_reg_dest" |
131 | (match_code "subreg,reg") | |
132 | { | |
133 | if (mode == DImode && GET_CODE (op) == SUBREG | |
134 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8 | |
135 | && TARGET_SHMEDIA) | |
136 | return 0; | |
137 | return arith_reg_operand (op, mode); | |
138 | }) | |
139 | ||
140 | ;; Returns 1 if OP is a normal arithmetic register. | |
5546ac90 KH |
141 | (define_predicate "arith_reg_operand" |
142 | (match_code "subreg,reg,sign_extend") | |
143 | { | |
144 | if (register_operand (op, mode)) | |
145 | { | |
146 | int regno; | |
147 | ||
f3536097 | 148 | if (REG_P (op)) |
5546ac90 | 149 | regno = REGNO (op); |
f3536097 | 150 | else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) |
5546ac90 KH |
151 | regno = REGNO (SUBREG_REG (op)); |
152 | else | |
153 | return 1; | |
154 | ||
155 | return (regno != T_REG && regno != PR_REG | |
156 | && ! TARGET_REGISTER_P (regno) | |
0e26cf79 | 157 | && regno != FPUL_REG |
5546ac90 KH |
158 | && regno != MACH_REG && regno != MACL_REG); |
159 | } | |
160 | /* Allow a no-op sign extension - compare LOAD_EXTEND_OP. | |
161 | We allow SImode here, as not using an FP register is just a matter of | |
162 | proper register allocation. */ | |
163 | if (TARGET_SHMEDIA | |
164 | && GET_MODE (op) == DImode && GET_CODE (op) == SIGN_EXTEND | |
165 | && GET_MODE (XEXP (op, 0)) == SImode | |
166 | && GET_CODE (XEXP (op, 0)) != SUBREG) | |
167 | return register_operand (XEXP (op, 0), VOIDmode); | |
168 | #if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */ | |
169 | if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND | |
170 | && GET_MODE (XEXP (op, 0)) == HImode | |
f3536097 | 171 | && REG_P (XEXP (op, 0)) |
5546ac90 KH |
172 | && REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG) |
173 | return register_operand (XEXP (op, 0), VOIDmode); | |
174 | #endif | |
175 | if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT | |
176 | && GET_CODE (op) == SUBREG | |
177 | && GET_MODE (SUBREG_REG (op)) == DImode | |
178 | && GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND | |
179 | && GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode | |
180 | && GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG) | |
181 | return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode); | |
182 | return 0; | |
183 | }) | |
184 | ||
185 | ;; Returns 1 if OP is a valid source operand for a compare insn. | |
5546ac90 KH |
186 | (define_predicate "arith_reg_or_0_operand" |
187 | (match_code "subreg,reg,const_int,const_vector") | |
188 | { | |
189 | if (arith_reg_operand (op, mode)) | |
190 | return 1; | |
191 | ||
32a7ab3d | 192 | if (satisfies_constraint_Z (op)) |
5546ac90 KH |
193 | return 1; |
194 | ||
195 | return 0; | |
196 | }) | |
197 | ||
2353515d OE |
198 | ;; Returns true if OP is either a register or constant 0 or constant 1. |
199 | (define_predicate "arith_reg_or_0_or_1_operand" | |
200 | (match_code "subreg,reg,const_int,const_vector") | |
201 | { | |
202 | return arith_reg_or_0_operand (op, mode) || satisfies_constraint_M (op); | |
203 | }) | |
204 | ||
205 | ;; Returns true if OP is a suitable constant for the minimum value of a | |
206 | ;; clips.b or clips.w insn. | |
207 | (define_predicate "clips_min_const_int" | |
208 | (and (match_code "const_int") | |
209 | (ior (match_test "INTVAL (op) == -128") | |
210 | (match_test "INTVAL (op) == -32768")))) | |
211 | ||
212 | ;; Returns true if OP is a suitable constant for the maximum value of a | |
213 | ;; clips.b or clips.w insn. | |
214 | (define_predicate "clips_max_const_int" | |
215 | (and (match_code "const_int") | |
216 | (ior (match_test "INTVAL (op) == 127") | |
217 | (match_test "INTVAL (op) == 32767")))) | |
218 | ||
219 | ;; Returns true if OP is a suitable constant for the maximum value of a | |
220 | ;; clipu.b or clipu.w insn. | |
221 | (define_predicate "clipu_max_const_int" | |
222 | (and (match_code "const_int") | |
223 | (ior (match_test "INTVAL (op) == 255") | |
224 | (match_test "INTVAL (op) == 65535")))) | |
225 | ||
50fe8924 | 226 | ;; Returns 1 if OP is a floating point operator with two operands. |
5546ac90 | 227 | (define_predicate "binary_float_operator" |
f289c6a1 KH |
228 | (and (match_code "plus,minus,mult,div") |
229 | (match_test "GET_MODE (op) == mode"))) | |
5546ac90 | 230 | |
50fe8924 | 231 | ;; Returns 1 if OP is a logical operator with two operands. |
5546ac90 | 232 | (define_predicate "binary_logical_operator" |
f289c6a1 KH |
233 | (and (match_code "and,ior,xor") |
234 | (match_test "GET_MODE (op) == mode"))) | |
5546ac90 | 235 | |
50fe8924 | 236 | ;; Return 1 if OP is an address suitable for a cache manipulation operation. |
f705a9a0 | 237 | ;; MODE has the meaning as in address_operand. |
f705a9a0 | 238 | (define_special_predicate "cache_address_operand" |
5546ac90 KH |
239 | (match_code "plus,reg") |
240 | { | |
241 | if (GET_CODE (op) == PLUS) | |
242 | { | |
f3536097 | 243 | if (!REG_P (XEXP (op, 0))) |
5546ac90 | 244 | return 0; |
f3536097 | 245 | if (!CONST_INT_P (XEXP (op, 1)) |
5546ac90 KH |
246 | || (INTVAL (XEXP (op, 1)) & 31)) |
247 | return 0; | |
248 | } | |
f3536097 | 249 | else if (!REG_P (op)) |
5546ac90 KH |
250 | return 0; |
251 | return address_operand (op, mode); | |
252 | }) | |
253 | ||
50fe8924 | 254 | ;; Returns 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu. |
5546ac90 KH |
255 | (define_predicate "cmp_operand" |
256 | (match_code "subreg,reg,const_int") | |
257 | { | |
32a7ab3d | 258 | if (satisfies_constraint_N (op)) |
5546ac90 KH |
259 | return 1; |
260 | if (TARGET_SHMEDIA | |
261 | && mode != DImode && GET_CODE (op) == SUBREG | |
262 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4) | |
263 | return 0; | |
264 | return arith_reg_operand (op, mode); | |
265 | }) | |
266 | ||
50fe8924 OE |
267 | ;; Returns true if OP is an operand that can be used as the first operand in |
268 | ;; the cstoresi4 expander pattern. | |
5546ac90 KH |
269 | (define_predicate "cmpsi_operand" |
270 | (match_code "subreg,reg,const_int") | |
271 | { | |
f3536097 | 272 | if (REG_P (op) && REGNO (op) == T_REG |
5546ac90 KH |
273 | && GET_MODE (op) == SImode |
274 | && TARGET_SH1) | |
275 | return 1; | |
276 | return arith_operand (op, mode); | |
277 | }) | |
278 | ||
50fe8924 OE |
279 | ;; Returns true if OP is a comutative float operator. |
280 | ;; This predicate is currently unused. | |
281 | ;;(define_predicate "commutative_float_operator" | |
282 | ;; (and (match_code "plus,mult") | |
283 | ;; (match_test "GET_MODE (op) == mode"))) | |
5546ac90 | 284 | |
50fe8924 | 285 | ;; Returns true if OP is a equal or not equal operator. |
5546ac90 | 286 | (define_predicate "equality_comparison_operator" |
f289c6a1 | 287 | (match_code "eq,ne")) |
5546ac90 | 288 | |
50fe8924 OE |
289 | ;; Returns true if OP is an arithmetic operand that is zero extended during |
290 | ;; an operation. | |
5546ac90 KH |
291 | (define_predicate "extend_reg_operand" |
292 | (match_code "subreg,reg,truncate") | |
293 | { | |
294 | return (GET_CODE (op) == TRUNCATE | |
295 | ? arith_operand | |
296 | : arith_reg_operand) (op, mode); | |
297 | }) | |
298 | ||
50fe8924 | 299 | ;; Like extend_reg_operand, but also allow a constant 0. |
5546ac90 KH |
300 | (define_predicate "extend_reg_or_0_operand" |
301 | (match_code "subreg,reg,truncate,const_int") | |
302 | { | |
303 | return (GET_CODE (op) == TRUNCATE | |
304 | ? arith_operand | |
305 | : arith_reg_or_0_operand) (op, mode); | |
306 | }) | |
307 | ||
308 | ;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND. | |
5546ac90 KH |
309 | (define_predicate "ext_dest_operand" |
310 | (match_code "subreg,reg") | |
311 | { | |
312 | return arith_reg_operand (op, mode); | |
313 | }) | |
314 | ||
50fe8924 OE |
315 | ;; Returns true if OP can be used as a destination register for shmedia floating |
316 | ;; point to integer conversions. | |
5546ac90 KH |
317 | (define_predicate "fp_arith_reg_dest" |
318 | (match_code "subreg,reg") | |
319 | { | |
320 | if (mode == DImode && GET_CODE (op) == SUBREG | |
321 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8) | |
322 | return 0; | |
323 | return fp_arith_reg_operand (op, mode); | |
324 | }) | |
325 | ||
50fe8924 OE |
326 | ;; Returns true if OP is a floating point register that can be used in floating |
327 | ;; point arithmetic operations. | |
5546ac90 KH |
328 | (define_predicate "fp_arith_reg_operand" |
329 | (match_code "subreg,reg") | |
330 | { | |
331 | if (register_operand (op, mode)) | |
332 | { | |
333 | int regno; | |
334 | ||
f3536097 | 335 | if (REG_P (op)) |
5546ac90 | 336 | regno = REGNO (op); |
f3536097 | 337 | else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) |
5546ac90 KH |
338 | regno = REGNO (SUBREG_REG (op)); |
339 | else | |
340 | return 1; | |
341 | ||
342 | return (regno >= FIRST_PSEUDO_REGISTER | |
343 | || FP_REGISTER_P (regno)); | |
344 | } | |
345 | return 0; | |
346 | }) | |
347 | ||
50fe8924 | 348 | ;; Returns true if OP is the FPSCR. |
5546ac90 KH |
349 | (define_predicate "fpscr_operand" |
350 | (match_code "reg") | |
351 | { | |
f3536097 | 352 | return (REG_P (op) |
5546ac90 KH |
353 | && (REGNO (op) == FPSCR_REG |
354 | || (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
355 | && !(reload_in_progress || reload_completed))) | |
356 | && GET_MODE (op) == PSImode); | |
357 | }) | |
358 | ||
db292b0e OE |
359 | ;; Returns true if OP is an operand that is either the fpul hard reg or |
360 | ;; a pseudo. This prevents combine from propagating function arguments | |
361 | ;; in hard regs into insns that need the operand in fpul. If it's a pseudo | |
362 | ;; reload can fix it up. | |
5546ac90 KH |
363 | (define_predicate "fpul_operand" |
364 | (match_code "reg") | |
365 | { | |
366 | if (TARGET_SHMEDIA) | |
367 | return fp_arith_reg_operand (op, mode); | |
368 | ||
f3536097 | 369 | return (REG_P (op) |
5546ac90 KH |
370 | && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER) |
371 | && GET_MODE (op) == mode); | |
372 | }) | |
373 | ||
db292b0e OE |
374 | ;; Returns true if OP is a valid fpul input operand for the fsca insn. |
375 | ;; The value in fpul is a fixed-point value and its scaling is described | |
376 | ;; in the fsca insn by a mult:SF. To allow pre-scaled fixed-point inputs | |
377 | ;; in fpul we have to permit things like | |
378 | ;; (reg:SI) | |
379 | ;; (fix:SF (float:SF (reg:SI))) | |
380 | (define_predicate "fpul_fsca_operand" | |
381 | (match_code "fix,reg") | |
382 | { | |
383 | if (fpul_operand (op, SImode)) | |
384 | return true; | |
385 | if (GET_CODE (op) == FIX && GET_MODE (op) == SImode | |
386 | && GET_CODE (XEXP (op, 0)) == FLOAT && GET_MODE (XEXP (op, 0)) == SFmode) | |
387 | return fpul_fsca_operand (XEXP (XEXP (op, 0), 0), | |
388 | GET_MODE (XEXP (XEXP (op, 0), 0))); | |
389 | return false; | |
390 | }) | |
391 | ||
392 | ;; Returns true if OP is a valid constant scale factor for the fsca insn. | |
393 | (define_predicate "fsca_scale_factor" | |
394 | (and (match_code "const_double") | |
395 | (match_test "op == sh_fsca_int2sf ()"))) | |
396 | ||
50fe8924 | 397 | ;; Returns true if OP is an operand that is zero extended during an operation. |
5546ac90 KH |
398 | (define_predicate "general_extend_operand" |
399 | (match_code "subreg,reg,mem,truncate") | |
400 | { | |
0bcf9a09 OE |
401 | if (GET_CODE (op) == TRUNCATE) |
402 | return arith_operand (op, mode); | |
403 | ||
404 | if (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))) | |
405 | return general_movsrc_operand (op, mode); | |
406 | ||
407 | return nonimmediate_operand (op, mode); | |
5546ac90 KH |
408 | }) |
409 | ||
24c18ad8 OE |
410 | ;; Returns 1 if OP is a simple register address. |
411 | (define_predicate "simple_mem_operand" | |
412 | (and (match_code "mem") | |
413 | (match_test "arith_reg_operand (XEXP (op, 0), SImode)"))) | |
414 | ||
415 | ;; Returns 1 if OP is a valid displacement address. | |
416 | (define_predicate "displacement_mem_operand" | |
417 | (and (match_code "mem") | |
418 | (match_test "GET_CODE (XEXP (op, 0)) == PLUS") | |
419 | (match_test "arith_reg_operand (XEXP (XEXP (op, 0), 0), SImode)") | |
420 | (match_test "sh_legitimate_index_p (GET_MODE (op), | |
421 | XEXP (XEXP (op, 0), 1), | |
422 | TARGET_SH2A, true)"))) | |
423 | ||
91f65b12 OE |
424 | ;; Returns true if OP is a displacement address that can fit into a |
425 | ;; 16 bit (non-SH2A) memory load / store insn. | |
426 | (define_predicate "short_displacement_mem_operand" | |
427 | (match_test "sh_disp_addr_displacement (op) | |
428 | <= sh_max_mov_insn_displacement (GET_MODE (op), false)")) | |
429 | ||
24c18ad8 OE |
430 | ;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn. |
431 | (define_predicate "zero_extend_movu_operand" | |
432 | (and (match_operand 0 "displacement_mem_operand") | |
433 | (match_test "GET_MODE (op) == QImode || GET_MODE (op) == HImode"))) | |
434 | ||
33344a62 OE |
435 | ;; Returns 1 if the operand can be used in a zero_extend. |
436 | (define_predicate "zero_extend_operand" | |
437 | (ior (and (match_test "TARGET_SHMEDIA") | |
438 | (match_operand 0 "general_extend_operand")) | |
439 | (and (match_test "! TARGET_SHMEDIA") | |
24c18ad8 OE |
440 | (match_operand 0 "arith_reg_operand")) |
441 | (and (match_test "TARGET_SH2A") | |
442 | (match_operand 0 "zero_extend_movu_operand")))) | |
33344a62 | 443 | |
5546ac90 KH |
444 | ;; Returns 1 if OP can be source of a simple move operation. Same as |
445 | ;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as | |
446 | ;; are subregs of system registers. | |
5546ac90 | 447 | (define_predicate "general_movsrc_operand" |
50fe8924 OE |
448 | (match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref, |
449 | const,const_vector") | |
5546ac90 | 450 | { |
ef812306 OE |
451 | if (t_reg_operand (op, mode)) |
452 | return 0; | |
453 | ||
91f65b12 OE |
454 | /* Disallow PC relative QImode loads, since these is no insn to do that |
455 | and an imm8 load should be used instead. */ | |
456 | if (IS_PC_RELATIVE_LOAD_ADDR_P (op) && GET_MODE (op) == QImode) | |
457 | return false; | |
458 | ||
f3536097 | 459 | if (MEM_P (op)) |
5546ac90 KH |
460 | { |
461 | rtx inside = XEXP (op, 0); | |
fce1e5fb OE |
462 | |
463 | /* Disallow mems with GBR address here. They have to go through | |
464 | separate special patterns. */ | |
465 | if ((REG_P (inside) && REGNO (inside) == GBR_REG) | |
466 | || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0)) | |
467 | && REGNO (XEXP (inside, 0)) == GBR_REG)) | |
468 | return 0; | |
469 | ||
5546ac90 KH |
470 | if (GET_CODE (inside) == CONST) |
471 | inside = XEXP (inside, 0); | |
472 | ||
473 | if (GET_CODE (inside) == LABEL_REF) | |
474 | return 1; | |
475 | ||
476 | if (GET_CODE (inside) == PLUS | |
477 | && GET_CODE (XEXP (inside, 0)) == LABEL_REF | |
f3536097 | 478 | && CONST_INT_P (XEXP (inside, 1))) |
5546ac90 KH |
479 | return 1; |
480 | ||
481 | /* Only post inc allowed. */ | |
482 | if (GET_CODE (inside) == PRE_DEC) | |
483 | return 0; | |
484 | } | |
485 | ||
0bcf9a09 OE |
486 | if (mode == GET_MODE (op) |
487 | && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))))) | |
a700b5f0 | 488 | { |
0bcf9a09 OE |
489 | rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op); |
490 | rtx x = XEXP (mem_rtx, 0); | |
a700b5f0 | 491 | |
0bcf9a09 OE |
492 | if ((mode == QImode || mode == HImode) |
493 | && GET_CODE (x) == PLUS | |
a700b5f0 KK |
494 | && REG_P (XEXP (x, 0)) |
495 | && CONST_INT_P (XEXP (x, 1))) | |
8c2a3f3b | 496 | return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false); |
0bcf9a09 OE |
497 | |
498 | /* Allow reg+reg addressing here without validating the register | |
499 | numbers. Usually one of the regs must be R0 or a pseudo reg. | |
500 | In some cases it can happen that arguments from hard regs are | |
501 | propagated directly into address expressions. In this cases reload | |
502 | will have to fix it up later. However, allow this only for native | |
503 | 1, 2 or 4 byte addresses. */ | |
504 | if (can_create_pseudo_p () && GET_CODE (x) == PLUS | |
505 | && GET_MODE_SIZE (mode) <= 4 | |
506 | && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1))) | |
507 | return true; | |
508 | ||
509 | /* 'general_operand' does not allow volatile mems during RTL expansion to | |
510 | avoid matching arithmetic that operates on mems, it seems. | |
511 | On SH this leads to redundant sign extensions for QImode or HImode | |
512 | loads. Thus we mimic the behavior but allow volatile mems. */ | |
513 | if (memory_address_addr_space_p (GET_MODE (mem_rtx), x, | |
514 | MEM_ADDR_SPACE (mem_rtx))) | |
515 | return true; | |
a700b5f0 KK |
516 | } |
517 | ||
5546ac90 KH |
518 | if (TARGET_SHMEDIA |
519 | && (GET_CODE (op) == PARALLEL || GET_CODE (op) == CONST_VECTOR) | |
520 | && sh_rep_vec (op, mode)) | |
521 | return 1; | |
522 | if (TARGET_SHMEDIA && 1 | |
523 | && GET_CODE (op) == SUBREG && GET_MODE (op) == mode | |
524 | && SUBREG_REG (op) == const0_rtx && subreg_lowpart_p (op)) | |
525 | /* FIXME */ abort (); /* return 1; */ | |
0bcf9a09 | 526 | |
5546ac90 KH |
527 | return general_operand (op, mode); |
528 | }) | |
529 | ||
284c32cf | 530 | ;; Returns 1 if OP is a MEM that does not use displacement addressing. |
344332e8 | 531 | (define_predicate "movsrc_no_disp_mem_operand" |
284c32cf | 532 | (match_code "mem") |
344332e8 | 533 | { |
284c32cf | 534 | return general_movsrc_operand (op, mode) && satisfies_constraint_Snd (op); |
344332e8 OE |
535 | }) |
536 | ||
5546ac90 KH |
537 | ;; Returns 1 if OP can be a destination of a move. Same as |
538 | ;; general_operand, but no preinc allowed. | |
5546ac90 KH |
539 | (define_predicate "general_movdst_operand" |
540 | (match_code "subreg,reg,mem") | |
541 | { | |
ef812306 OE |
542 | if (t_reg_operand (op, mode)) |
543 | return 0; | |
544 | ||
fce1e5fb OE |
545 | if (MEM_P (op)) |
546 | { | |
547 | rtx inside = XEXP (op, 0); | |
548 | /* Disallow mems with GBR address here. They have to go through | |
549 | separate special patterns. */ | |
550 | if ((REG_P (inside) && REGNO (inside) == GBR_REG) | |
551 | || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0)) | |
552 | && REGNO (XEXP (inside, 0)) == GBR_REG)) | |
553 | return 0; | |
554 | } | |
555 | ||
5546ac90 | 556 | /* Only pre dec allowed. */ |
f3536097 | 557 | if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC) |
5546ac90 KH |
558 | return 0; |
559 | if (mode == DImode && TARGET_SHMEDIA && GET_CODE (op) == SUBREG | |
560 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8 | |
fae61228 | 561 | && ! (reload_in_progress || reload_completed)) |
5546ac90 KH |
562 | return 0; |
563 | ||
35d1b083 OE |
564 | if (mode == GET_MODE (op) |
565 | && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))))) | |
a700b5f0 | 566 | { |
35d1b083 OE |
567 | rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op); |
568 | rtx x = XEXP (mem_rtx, 0); | |
a700b5f0 | 569 | |
35d1b083 OE |
570 | if ((mode == QImode || mode == HImode) |
571 | && GET_CODE (x) == PLUS | |
a700b5f0 KK |
572 | && REG_P (XEXP (x, 0)) |
573 | && CONST_INT_P (XEXP (x, 1))) | |
8c2a3f3b | 574 | return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false); |
35d1b083 OE |
575 | |
576 | /* Allow reg+reg addressing here without validating the register | |
577 | numbers. Usually one of the regs must be R0 or a pseudo reg. | |
578 | In some cases it can happen that arguments from hard regs are | |
579 | propagated directly into address expressions. In this cases reload | |
580 | will have to fix it up later. However, allow this only for native | |
581 | 1, 2 or 4 byte addresses. */ | |
582 | if (can_create_pseudo_p () && GET_CODE (x) == PLUS | |
583 | && GET_MODE_SIZE (mode) <= 4 | |
584 | && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1))) | |
585 | return true; | |
586 | ||
587 | /* 'general_operand' does not allow volatile mems during RTL expansion to | |
588 | avoid matching arithmetic that operates on mems, it seems. | |
589 | On SH this leads to redundant sign extensions for QImode or HImode | |
590 | stores. Thus we mimic the behavior but allow volatile mems. */ | |
591 | if (memory_address_addr_space_p (GET_MODE (mem_rtx), x, | |
592 | MEM_ADDR_SPACE (mem_rtx))) | |
593 | return true; | |
a700b5f0 KK |
594 | } |
595 | ||
5546ac90 KH |
596 | return general_operand (op, mode); |
597 | }) | |
598 | ||
c11c09f9 | 599 | ;; Returns 1 if OP is a POST_INC on stack pointer register. |
c11c09f9 KP |
600 | (define_predicate "sh_no_delay_pop_operand" |
601 | (match_code "mem") | |
602 | { | |
603 | rtx inside; | |
604 | inside = XEXP (op, 0); | |
605 | ||
606 | if (GET_CODE (op) == MEM && GET_MODE (op) == SImode | |
607 | && GET_CODE (inside) == POST_INC | |
608 | && GET_CODE (XEXP (inside, 0)) == REG | |
609 | && REGNO (XEXP (inside, 0)) == SP_REG) | |
610 | return 1; | |
611 | ||
612 | return 0; | |
613 | }) | |
614 | ||
5546ac90 | 615 | ;; Returns 1 if OP is a MEM that can be source of a simple move operation. |
5546ac90 KH |
616 | (define_predicate "unaligned_load_operand" |
617 | (match_code "mem") | |
618 | { | |
619 | rtx inside; | |
620 | ||
f3536097 | 621 | if (!MEM_P (op) || GET_MODE (op) != mode) |
5546ac90 KH |
622 | return 0; |
623 | ||
624 | inside = XEXP (op, 0); | |
625 | ||
626 | if (GET_CODE (inside) == POST_INC) | |
627 | inside = XEXP (inside, 0); | |
628 | ||
f3536097 | 629 | if (REG_P (inside)) |
5546ac90 KH |
630 | return 1; |
631 | ||
632 | return 0; | |
633 | }) | |
634 | ||
b67b3838 OE |
635 | ;; Returns 1 if OP is a MEM that can be used in "index_disp" combiner |
636 | ;; patterns. | |
637 | (define_predicate "mem_index_disp_operand" | |
638 | (match_code "mem") | |
639 | { | |
640 | rtx plus0_rtx, plus1_rtx, mult_rtx; | |
641 | ||
642 | plus0_rtx = XEXP (op, 0); | |
643 | if (GET_CODE (plus0_rtx) != PLUS) | |
644 | return 0; | |
645 | ||
646 | plus1_rtx = XEXP (plus0_rtx, 0); | |
647 | if (GET_CODE (plus1_rtx) != PLUS) | |
648 | return 0; | |
05852a5f OE |
649 | if (! arith_reg_operand (XEXP (plus1_rtx, 1), GET_MODE (XEXP (plus1_rtx, 1)))) |
650 | return 0; | |
b67b3838 OE |
651 | |
652 | mult_rtx = XEXP (plus1_rtx, 0); | |
653 | if (GET_CODE (mult_rtx) != MULT) | |
654 | return 0; | |
05852a5f OE |
655 | if (! arith_reg_operand (XEXP (mult_rtx, 0), GET_MODE (XEXP (mult_rtx, 0))) |
656 | || ! CONST_INT_P (XEXP (mult_rtx, 1))) | |
657 | return 0; | |
658 | ||
659 | return exact_log2 (INTVAL (XEXP (mult_rtx, 1))) > 0 | |
b67b3838 OE |
660 | && sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true); |
661 | }) | |
662 | ||
50fe8924 | 663 | ;; Returns true if OP is some kind of greater comparision. |
5546ac90 | 664 | (define_predicate "greater_comparison_operator" |
f289c6a1 | 665 | (match_code "gt,ge,gtu,geu")) |
5546ac90 | 666 | |
50fe8924 OE |
667 | ;; Returns true if OP is an operand suitable for shmedia reload_inqi and |
668 | ;; reload_inhi insns. | |
5546ac90 KH |
669 | (define_predicate "inqhi_operand" |
670 | (match_code "truncate") | |
671 | { | |
672 | if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op)) | |
673 | return 0; | |
674 | op = XEXP (op, 0); | |
675 | /* Can't use true_regnum here because copy_cost wants to know about | |
676 | SECONDARY_INPUT_RELOAD_CLASS. */ | |
f3536097 | 677 | return REG_P (op) && FP_REGISTER_P (REGNO (op)); |
5546ac90 KH |
678 | }) |
679 | ||
50fe8924 OE |
680 | ;; Returns true if OP is a general purpose integer register. |
681 | ;; This predicate is currently unused. | |
682 | ;;(define_special_predicate "int_gpr_dest" | |
683 | ;; (match_code "subreg,reg") | |
684 | ;;{ | |
685 | ;; enum machine_mode op_mode = GET_MODE (op); | |
686 | ;; | |
687 | ;; if (GET_MODE_CLASS (op_mode) != MODE_INT | |
688 | ;; || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD) | |
689 | ;; return 0; | |
690 | ;; if (! reload_completed) | |
691 | ;; return 0; | |
692 | ;; return true_regnum (op) <= LAST_GENERAL_REG; | |
693 | ;;}) | |
694 | ||
695 | ;; Returns true if OP is some kind of less comparison. | |
5546ac90 | 696 | (define_predicate "less_comparison_operator" |
f289c6a1 | 697 | (match_code "lt,le,ltu,leu")) |
5546ac90 KH |
698 | |
699 | ;; Returns 1 if OP is a valid source operand for a logical operation. | |
5546ac90 KH |
700 | (define_predicate "logical_operand" |
701 | (match_code "subreg,reg,const_int") | |
702 | { | |
703 | if (TARGET_SHMEDIA | |
704 | && mode != DImode && GET_CODE (op) == SUBREG | |
705 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4) | |
706 | return 0; | |
707 | ||
708 | if (arith_reg_operand (op, mode)) | |
709 | return 1; | |
710 | ||
711 | if (TARGET_SHMEDIA) | |
712 | { | |
32a7ab3d | 713 | if (satisfies_constraint_I10 (op)) |
5546ac90 KH |
714 | return 1; |
715 | else | |
716 | return 0; | |
717 | } | |
32a7ab3d | 718 | else if (satisfies_constraint_K08 (op)) |
5546ac90 KH |
719 | return 1; |
720 | ||
721 | return 0; | |
722 | }) | |
723 | ||
5e204a6e OE |
724 | ;; Like logical_operand but allows additional constant values which can be |
725 | ;; done with zero extensions. Used for the second operand of and insns. | |
726 | (define_predicate "logical_and_operand" | |
727 | (match_code "subreg,reg,const_int") | |
728 | { | |
729 | if (logical_operand (op, mode)) | |
730 | return 1; | |
731 | ||
732 | if (! TARGET_SHMEDIA | |
733 | && (satisfies_constraint_Jmb (op) || satisfies_constraint_Jmw (op))) | |
734 | return 1; | |
735 | ||
736 | return 0; | |
737 | }) | |
738 | ||
50fe8924 | 739 | ;; Returns true if OP is a logical operator. |
5546ac90 | 740 | (define_predicate "logical_operator" |
f289c6a1 | 741 | (match_code "and,ior,xor")) |
5546ac90 KH |
742 | |
743 | ;; Like arith_reg_operand, but for register source operands of narrow | |
744 | ;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs. | |
5546ac90 KH |
745 | (define_predicate "logical_reg_operand" |
746 | (match_code "subreg,reg") | |
747 | { | |
748 | if (TARGET_SHMEDIA | |
749 | && GET_CODE (op) == SUBREG | |
750 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4 | |
751 | && mode != DImode) | |
752 | return 0; | |
753 | return arith_reg_operand (op, mode); | |
754 | }) | |
755 | ||
50fe8924 | 756 | ;; Returns true if OP is a valid bit offset value for the shmedia mextr insns. |
5546ac90 KH |
757 | (define_predicate "mextr_bit_offset" |
758 | (match_code "const_int") | |
759 | { | |
760 | HOST_WIDE_INT i; | |
761 | ||
f3536097 | 762 | if (!CONST_INT_P (op)) |
5546ac90 KH |
763 | return 0; |
764 | i = INTVAL (op); | |
765 | return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0; | |
766 | }) | |
767 | ||
50fe8924 OE |
768 | ;; Returns true if OP is a constant -1, 0 or an zero extended register that |
769 | ;; can be used as an operator in the *subsi3_media insn. | |
5546ac90 KH |
770 | (define_predicate "minuend_operand" |
771 | (match_code "subreg,reg,truncate,const_int") | |
772 | { | |
773 | return op == constm1_rtx || extend_reg_or_0_operand (op, mode); | |
774 | }) | |
775 | ||
50fe8924 OE |
776 | ;; Returns true if OP is a noncommutative floating point operator. |
777 | ;; This predicate is currently unused. | |
778 | ;;(define_predicate "noncommutative_float_operator" | |
779 | ;; (and (match_code "minus,div") | |
780 | ;; (match_test "GET_MODE (op) == mode"))) | |
5546ac90 | 781 | |
f90b7a5a PB |
782 | ;; UNORDERED is only supported on SHMEDIA. |
783 | ||
784 | (define_predicate "sh_float_comparison_operator" | |
785 | (ior (match_operand 0 "ordered_comparison_operator") | |
786 | (and (match_test "TARGET_SHMEDIA") | |
787 | (match_code "unordered")))) | |
788 | ||
789 | (define_predicate "shmedia_cbranch_comparison_operator" | |
790 | (ior (match_operand 0 "equality_comparison_operator") | |
791 | (match_operand 0 "greater_comparison_operator"))) | |
792 | ||
50fe8924 | 793 | ;; Returns true if OP is a constant vector. |
5546ac90 KH |
794 | (define_predicate "sh_const_vec" |
795 | (match_code "const_vector") | |
796 | { | |
797 | int i; | |
798 | ||
799 | if (GET_CODE (op) != CONST_VECTOR | |
800 | || (GET_MODE (op) != mode && mode != VOIDmode)) | |
801 | return 0; | |
802 | i = XVECLEN (op, 0) - 1; | |
803 | for (; i >= 0; i--) | |
f3536097 | 804 | if (!CONST_INT_P (XVECEXP (op, 0, i))) |
5546ac90 KH |
805 | return 0; |
806 | return 1; | |
807 | }) | |
808 | ||
809 | ;; Determine if OP is a constant vector matching MODE with only one | |
810 | ;; element that is not a sign extension. Two byte-sized elements | |
811 | ;; count as one. | |
5546ac90 KH |
812 | (define_predicate "sh_1el_vec" |
813 | (match_code "const_vector") | |
814 | { | |
815 | int unit_size; | |
816 | int i, last, least, sign_ix; | |
817 | rtx sign; | |
818 | ||
819 | if (GET_CODE (op) != CONST_VECTOR | |
820 | || (GET_MODE (op) != mode && mode != VOIDmode)) | |
821 | return 0; | |
822 | /* Determine numbers of last and of least significant elements. */ | |
823 | last = XVECLEN (op, 0) - 1; | |
824 | least = TARGET_LITTLE_ENDIAN ? 0 : last; | |
f3536097 | 825 | if (!CONST_INT_P (XVECEXP (op, 0, least))) |
5546ac90 KH |
826 | return 0; |
827 | sign_ix = least; | |
828 | if (GET_MODE_UNIT_SIZE (mode) == 1) | |
829 | sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1; | |
f3536097 | 830 | if (!CONST_INT_P (XVECEXP (op, 0, sign_ix))) |
5546ac90 KH |
831 | return 0; |
832 | unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op)); | |
833 | sign = (INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1) | |
834 | ? constm1_rtx : const0_rtx); | |
835 | i = XVECLEN (op, 0) - 1; | |
836 | do | |
837 | if (i != least && i != sign_ix && XVECEXP (op, 0, i) != sign) | |
838 | return 0; | |
839 | while (--i); | |
840 | return 1; | |
841 | }) | |
842 | ||
843 | ;; Like register_operand, but take into account that SHMEDIA can use | |
844 | ;; the constant zero like a general register. | |
5546ac90 | 845 | (define_predicate "sh_register_operand" |
ac42ec79 | 846 | (match_code "reg,subreg,const_int,const_double") |
5546ac90 KH |
847 | { |
848 | if (op == CONST0_RTX (mode) && TARGET_SHMEDIA) | |
849 | return 1; | |
850 | return register_operand (op, mode); | |
851 | }) | |
852 | ||
50fe8924 OE |
853 | ;; Returns true if OP is a vector which is composed of one element that is |
854 | ;; repeated. | |
5546ac90 | 855 | (define_predicate "sh_rep_vec" |
b4060d3f | 856 | (match_code "const_vector,parallel") |
5546ac90 KH |
857 | { |
858 | int i; | |
859 | rtx x, y; | |
860 | ||
861 | if ((GET_CODE (op) != CONST_VECTOR && GET_CODE (op) != PARALLEL) | |
862 | || (GET_MODE (op) != mode && mode != VOIDmode)) | |
863 | return 0; | |
864 | i = XVECLEN (op, 0) - 2; | |
865 | x = XVECEXP (op, 0, i + 1); | |
866 | if (GET_MODE_UNIT_SIZE (mode) == 1) | |
867 | { | |
868 | y = XVECEXP (op, 0, i); | |
869 | for (i -= 2; i >= 0; i -= 2) | |
870 | if (! rtx_equal_p (XVECEXP (op, 0, i + 1), x) | |
871 | || ! rtx_equal_p (XVECEXP (op, 0, i), y)) | |
872 | return 0; | |
873 | } | |
874 | else | |
875 | for (; i >= 0; i--) | |
876 | if (XVECEXP (op, 0, i) != x) | |
877 | return 0; | |
878 | return 1; | |
879 | }) | |
880 | ||
50fe8924 | 881 | ;; Returns true if OP is a valid shift count operand for shift operations. |
5546ac90 | 882 | (define_predicate "shift_count_operand" |
50fe8924 OE |
883 | (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg, |
884 | zero_extend,sign_extend") | |
5546ac90 | 885 | { |
d8a48c21 OE |
886 | /* Allow T_REG as shift count for dynamic shifts, although it is not |
887 | really possible. It will then be copied to a general purpose reg. */ | |
888 | if (! TARGET_SHMEDIA) | |
aadb5b43 OE |
889 | return const_int_operand (op, mode) || arith_reg_operand (op, mode) |
890 | || (TARGET_DYNSHIFT && t_reg_operand (op, mode)); | |
d8a48c21 | 891 | |
5546ac90 | 892 | return (CONSTANT_P (op) |
f3536097 | 893 | ? (CONST_INT_P (op) |
5546ac90 KH |
894 | ? (unsigned) INTVAL (op) < GET_MODE_BITSIZE (mode) |
895 | : nonmemory_operand (op, mode)) | |
896 | : shift_count_reg_operand (op, mode)); | |
897 | }) | |
898 | ||
50fe8924 OE |
899 | ;; Returns true if OP is a valid shift count operand in a register which can |
900 | ;; be used by shmedia shift insns. | |
5546ac90 KH |
901 | (define_predicate "shift_count_reg_operand" |
902 | (match_code "subreg,reg,zero_extend,sign_extend") | |
903 | { | |
904 | if ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND | |
905 | || (GET_CODE (op) == SUBREG && SUBREG_BYTE (op) == 0)) | |
906 | && (mode == VOIDmode || mode == GET_MODE (op)) | |
907 | && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6 | |
908 | && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT) | |
909 | { | |
910 | mode = VOIDmode; | |
911 | do | |
912 | op = XEXP (op, 0); | |
913 | while ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND | |
914 | || GET_CODE (op) == TRUNCATE) | |
915 | && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6 | |
916 | && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT); | |
917 | ||
918 | } | |
919 | return arith_reg_operand (op, mode); | |
920 | }) | |
921 | ||
6e01d526 OE |
922 | ;; Predicates for matching operands that are constant shift |
923 | ;; amounts 1, 2, 8, 16. | |
d8a48c21 OE |
924 | (define_predicate "p27_shift_count_operand" |
925 | (and (match_code "const_int") | |
926 | (match_test "satisfies_constraint_P27 (op)"))) | |
927 | ||
928 | (define_predicate "not_p27_shift_count_operand" | |
929 | (and (match_code "const_int") | |
930 | (match_test "! satisfies_constraint_P27 (op)"))) | |
931 | ||
6e01d526 OE |
932 | ;; For right shifts the constant 1 is a special case because the shlr insn |
933 | ;; clobbers the T_REG and is handled by the T_REG clobbering version of the | |
934 | ;; insn, which is also used for non-P27 shift sequences. | |
935 | (define_predicate "p27_rshift_count_operand" | |
936 | (and (match_code "const_int") | |
937 | (match_test "satisfies_constraint_P27 (op)") | |
938 | (match_test "! satisfies_constraint_M (op)"))) | |
939 | ||
940 | (define_predicate "not_p27_rshift_count_operand" | |
941 | (and (match_code "const_int") | |
942 | (ior (match_test "! satisfies_constraint_P27 (op)") | |
943 | (match_test "satisfies_constraint_M (op)")))) | |
944 | ||
50fe8924 | 945 | ;; Returns true if OP is some kind of a shift operator. |
5546ac90 | 946 | (define_predicate "shift_operator" |
f289c6a1 | 947 | (match_code "ashift,ashiftrt,lshiftrt")) |
5546ac90 | 948 | |
50fe8924 | 949 | ;; Returns true if OP is a symbol reference. |
5546ac90 | 950 | (define_predicate "symbol_ref_operand" |
f289c6a1 | 951 | (match_code "symbol_ref")) |
5546ac90 KH |
952 | |
953 | ;; Same as target_reg_operand, except that label_refs and symbol_refs | |
954 | ;; are accepted before reload. | |
5546ac90 KH |
955 | (define_special_predicate "target_operand" |
956 | (match_code "subreg,reg,label_ref,symbol_ref,const,unspec") | |
957 | { | |
958 | if (mode != VOIDmode && mode != Pmode) | |
959 | return 0; | |
960 | ||
961 | if ((GET_MODE (op) == Pmode || GET_MODE (op) == VOIDmode) | |
32a7ab3d | 962 | && satisfies_constraint_Csy (op)) |
5546ac90 KH |
963 | return ! reload_completed; |
964 | ||
965 | return target_reg_operand (op, mode); | |
966 | }) | |
967 | ||
50fe8924 | 968 | ;; A predicate that accepts pseudos and branch target registers. |
5546ac90 KH |
969 | (define_special_predicate "target_reg_operand" |
970 | (match_code "subreg,reg") | |
971 | { | |
972 | if (mode == VOIDmode | |
973 | ? GET_MODE (op) != Pmode && GET_MODE (op) != PDImode | |
974 | : mode != GET_MODE (op)) | |
975 | return 0; | |
976 | ||
977 | if (GET_CODE (op) == SUBREG) | |
978 | op = XEXP (op, 0); | |
979 | ||
f3536097 | 980 | if (!REG_P (op)) |
5546ac90 KH |
981 | return 0; |
982 | ||
983 | /* We must protect ourselves from matching pseudos that are virtual | |
984 | register, because they will eventually be replaced with hardware | |
985 | registers that aren't branch-target registers. */ | |
986 | if (REGNO (op) > LAST_VIRTUAL_REGISTER | |
987 | || TARGET_REGISTER_P (REGNO (op))) | |
988 | return 1; | |
989 | ||
990 | return 0; | |
991 | }) | |
992 | ||
50fe8924 | 993 | ;; Returns true if OP is a valid operand for the shmedia mperm.w insn. |
5546ac90 KH |
994 | (define_special_predicate "trunc_hi_operand" |
995 | (match_code "subreg,reg,truncate") | |
996 | { | |
997 | enum machine_mode op_mode = GET_MODE (op); | |
998 | ||
999 | if (op_mode != SImode && op_mode != DImode | |
1000 | && op_mode != V4HImode && op_mode != V2SImode) | |
1001 | return 0; | |
1002 | return extend_reg_operand (op, mode); | |
1003 | }) | |
1004 | ||
50fe8924 OE |
1005 | ;; Returns true if OP is an address suitable for an unaligned access |
1006 | ;; instruction. | |
f705a9a0 | 1007 | (define_special_predicate "ua_address_operand" |
5546ac90 KH |
1008 | (match_code "subreg,reg,plus") |
1009 | { | |
1010 | if (GET_CODE (op) == PLUS | |
32a7ab3d | 1011 | && (! satisfies_constraint_I06 (XEXP (op, 1)))) |
5546ac90 KH |
1012 | return 0; |
1013 | return address_operand (op, QImode); | |
1014 | }) | |
1015 | ||
50fe8924 | 1016 | ;; Returns true if OP is a valid offset for an unaligned memory address. |
5546ac90 KH |
1017 | (define_predicate "ua_offset" |
1018 | (match_code "const_int") | |
1019 | { | |
32a7ab3d | 1020 | return satisfies_constraint_I06 (op); |
5546ac90 KH |
1021 | }) |
1022 | ||
50fe8924 | 1023 | ;; Returns true if OP is a floating point operator with one operand. |
5546ac90 | 1024 | (define_predicate "unary_float_operator" |
f289c6a1 KH |
1025 | (and (match_code "abs,neg,sqrt") |
1026 | (match_test "GET_MODE (op) == mode"))) | |
5546ac90 KH |
1027 | |
1028 | ;; Return 1 if OP is a valid source operand for xor. | |
5546ac90 KH |
1029 | (define_predicate "xor_operand" |
1030 | (match_code "subreg,reg,const_int") | |
1031 | { | |
f3536097 | 1032 | if (CONST_INT_P (op)) |
5546ac90 | 1033 | return (TARGET_SHMEDIA |
32a7ab3d | 1034 | ? (satisfies_constraint_I06 (op) |
b3a13419 | 1035 | || (!can_create_pseudo_p () && INTVAL (op) == 0xff)) |
32a7ab3d | 1036 | : satisfies_constraint_K08 (op)); |
5546ac90 KH |
1037 | if (TARGET_SHMEDIA |
1038 | && mode != DImode && GET_CODE (op) == SUBREG | |
1039 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4) | |
1040 | return 0; | |
1041 | return arith_reg_operand (op, mode); | |
1042 | }) | |
9eb3a0dd N |
1043 | |
1044 | (define_predicate "bitwise_memory_operand" | |
1045 | (match_code "mem") | |
1046 | { | |
f3536097 | 1047 | if (MEM_P (op)) |
9eb3a0dd N |
1048 | { |
1049 | if (REG_P (XEXP (op, 0))) | |
1050 | return 1; | |
1051 | ||
1052 | if (GET_CODE (XEXP (op, 0)) == PLUS | |
f3536097 | 1053 | && REG_P (XEXP (XEXP (op, 0), 0)) |
9eb3a0dd N |
1054 | && satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1))) |
1055 | return 1; | |
1056 | } | |
1057 | return 0; | |
1058 | }) | |
c11394f8 OE |
1059 | |
1060 | ;; The atomic_* operand predicates are used for the atomic patterns. | |
1061 | ;; Depending on the particular pattern some operands can be immediate | |
1062 | ;; values. Using these predicates avoids the usage of 'force_reg' in the | |
1063 | ;; expanders. | |
1064 | (define_predicate "atomic_arith_operand" | |
1065 | (ior (match_code "subreg,reg") | |
1066 | (and (match_test "satisfies_constraint_I08 (op)") | |
1067 | (match_test "mode != QImode") | |
1068 | (match_test "mode != HImode") | |
1069 | (match_test "TARGET_SH4A_ARCH")))) | |
1070 | ||
1071 | (define_predicate "atomic_logical_operand" | |
1072 | (ior (match_code "subreg,reg") | |
1073 | (and (match_test "satisfies_constraint_K08 (op)") | |
1074 | (match_test "mode != QImode") | |
1075 | (match_test "mode != HImode") | |
1076 | (match_test "TARGET_SH4A_ARCH")))) | |
1077 | ||
f031c344 OE |
1078 | ;; A predicate describing the T bit register in any form. |
1079 | (define_predicate "t_reg_operand" | |
1080 | (match_code "reg,subreg,sign_extend,zero_extend") | |
1081 | { | |
1082 | switch (GET_CODE (op)) | |
1083 | { | |
1084 | case REG: | |
1085 | return REGNO (op) == T_REG; | |
1086 | ||
1087 | case SUBREG: | |
312f9b9d | 1088 | return REG_P (SUBREG_REG (op)) && REGNO (SUBREG_REG (op)) == T_REG; |
f031c344 OE |
1089 | |
1090 | case ZERO_EXTEND: | |
1091 | case SIGN_EXTEND: | |
1092 | return GET_CODE (XEXP (op, 0)) == SUBREG | |
312f9b9d | 1093 | && REG_P (SUBREG_REG (XEXP (op, 0))) |
f031c344 OE |
1094 | && REGNO (SUBREG_REG (XEXP (op, 0))) == T_REG; |
1095 | ||
1096 | default: | |
1097 | return 0; | |
1098 | } | |
1099 | }) | |
1100 | ||
1101 | ;; A predicate describing a negated T bit register. | |
1102 | (define_predicate "negt_reg_operand" | |
1103 | (match_code "subreg,xor") | |
1104 | { | |
1105 | switch (GET_CODE (op)) | |
1106 | { | |
1107 | case XOR: | |
1108 | return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))) | |
1109 | && satisfies_constraint_M (XEXP (op, 1)); | |
1110 | ||
1111 | case SUBREG: | |
1112 | return negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))); | |
1113 | ||
1114 | default: | |
1115 | return 0; | |
1116 | } | |
1117 | }) | |
4eddc42b | 1118 | |
b4eca9c8 OE |
1119 | ;; A predicate that returns true if OP is a valid construct around the T bit |
1120 | ;; that can be used as an operand for conditional branches. | |
1121 | (define_predicate "cbranch_treg_value" | |
48d8568e OE |
1122 | (and (match_code "eq,ne,reg,subreg,xor,sign_extend,zero_extend") |
1123 | (match_test "sh_eval_treg_value (op) >= 0"))) | |
b4eca9c8 | 1124 | |
50fe8924 | 1125 | ;; Returns true if OP is arith_reg_operand or t_reg_operand. |
4eddc42b OE |
1126 | (define_predicate "arith_reg_or_t_reg_operand" |
1127 | (ior (match_operand 0 "arith_reg_operand") | |
1128 | (match_operand 0 "t_reg_operand"))) | |
78040535 OE |
1129 | |
1130 | ;; A predicate describing the negated value of the T bit register shifted | |
1131 | ;; left by 31. | |
1132 | (define_predicate "negt_reg_shl31_operand" | |
1133 | (match_code "plus,minus,if_then_else") | |
1134 | { | |
1135 | /* (plus:SI (mult:SI (match_operand:SI 1 "t_reg_operand") | |
1136 | (const_int -2147483648)) ;; 0xffffffff80000000 | |
1137 | (const_int -2147483648)) | |
1138 | */ | |
1139 | if (GET_CODE (op) == PLUS && satisfies_constraint_Jhb (XEXP (op, 1)) | |
1140 | && GET_CODE (XEXP (op, 0)) == MULT | |
1141 | && t_reg_operand (XEXP (XEXP (op, 0), 0), SImode) | |
1142 | && satisfies_constraint_Jhb (XEXP (XEXP (op, 0), 1))) | |
1143 | return true; | |
1144 | ||
1145 | /* (minus:SI (const_int -2147483648) ;; 0xffffffff80000000 | |
1146 | (mult:SI (match_operand:SI 1 "t_reg_operand") | |
1147 | (const_int -2147483648))) | |
1148 | */ | |
1149 | if (GET_CODE (op) == MINUS | |
1150 | && satisfies_constraint_Jhb (XEXP (op, 0)) | |
1151 | && GET_CODE (XEXP (op, 1)) == MULT | |
1152 | && t_reg_operand (XEXP (XEXP (op, 1), 0), SImode) | |
1153 | && satisfies_constraint_Jhb (XEXP (XEXP (op, 1), 1))) | |
1154 | return true; | |
1155 | ||
1156 | /* (if_then_else:SI (match_operand:SI 1 "t_reg_operand") | |
1157 | (const_int 0) | |
1158 | (const_int -2147483648)) ;; 0xffffffff80000000 | |
1159 | */ | |
1160 | if (GET_CODE (op) == IF_THEN_ELSE && t_reg_operand (XEXP (op, 0), SImode) | |
1161 | && satisfies_constraint_Z (XEXP (op, 1)) | |
1162 | && satisfies_constraint_Jhb (XEXP (op, 2))) | |
1163 | return true; | |
1164 | ||
1165 | return false; | |
1166 | }) | |
7bd76b9c OE |
1167 | |
1168 | ;; A predicate that determines whether a given constant is a valid | |
50fe8924 | 1169 | ;; displacement for a GBR load/store of the specified mode. |
7bd76b9c OE |
1170 | (define_predicate "gbr_displacement" |
1171 | (match_code "const_int") | |
1172 | { | |
1173 | const int mode_sz = GET_MODE_SIZE (mode); | |
1174 | const int move_sz = mode_sz > GET_MODE_SIZE (SImode) | |
1175 | ? GET_MODE_SIZE (SImode) | |
1176 | : mode_sz; | |
1177 | int max_disp = 255 * move_sz; | |
1178 | if (mode_sz > move_sz) | |
1179 | max_disp -= mode_sz - move_sz; | |
1180 | ||
1181 | return INTVAL (op) >= 0 && INTVAL (op) <= max_disp; | |
1182 | }) | |
14df3f36 OE |
1183 | |
1184 | ;; A predicate that determines whether OP is a valid GBR addressing mode | |
1185 | ;; memory reference. | |
1186 | (define_predicate "gbr_address_mem" | |
1187 | (match_code "mem") | |
1188 | { | |
1189 | rtx addr = XEXP (op, 0); | |
1190 | ||
1191 | if (REG_P (addr) && REGNO (addr) == GBR_REG) | |
1192 | return true; | |
1193 | if (GET_CODE (addr) == PLUS | |
1194 | && REG_P (XEXP (addr, 0)) && REGNO (XEXP (addr, 0)) == GBR_REG | |
1195 | && gbr_displacement (XEXP (addr, 1), mode)) | |
1196 | return true; | |
1197 | ||
1198 | return false; | |
1199 | }) |