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5546ac90 | 1 | ;; Predicate definitions for Renesas / SuperH SH. |
818ab71a | 2 | ;; Copyright (C) 2005-2016 Free Software Foundation, Inc. |
5546ac90 KH |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
5546ac90 KH |
9 | ;; any later version. |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
5546ac90 | 19 | |
5546ac90 KH |
20 | |
21 | ;; Returns 1 if OP is a normal arithmetic register. | |
5546ac90 KH |
22 | (define_predicate "arith_reg_operand" |
23 | (match_code "subreg,reg,sign_extend") | |
24 | { | |
25 | if (register_operand (op, mode)) | |
26 | { | |
27 | int regno; | |
28 | ||
f3536097 | 29 | if (REG_P (op)) |
5546ac90 | 30 | regno = REGNO (op); |
f3536097 | 31 | else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) |
5546ac90 KH |
32 | regno = REGNO (SUBREG_REG (op)); |
33 | else | |
34 | return 1; | |
35 | ||
36 | return (regno != T_REG && regno != PR_REG | |
37 | && ! TARGET_REGISTER_P (regno) | |
fe3e478f | 38 | && regno != FPUL_REG && regno != FPSCR_REG |
5546ac90 KH |
39 | && regno != MACH_REG && regno != MACL_REG); |
40 | } | |
41 | /* Allow a no-op sign extension - compare LOAD_EXTEND_OP. | |
42 | We allow SImode here, as not using an FP register is just a matter of | |
43 | proper register allocation. */ | |
e1fab8ba | 44 | |
5546ac90 KH |
45 | #if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */ |
46 | if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND | |
47 | && GET_MODE (XEXP (op, 0)) == HImode | |
f3536097 | 48 | && REG_P (XEXP (op, 0)) |
5546ac90 KH |
49 | && REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG) |
50 | return register_operand (XEXP (op, 0), VOIDmode); | |
51 | #endif | |
52 | if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT | |
53 | && GET_CODE (op) == SUBREG | |
54 | && GET_MODE (SUBREG_REG (op)) == DImode | |
55 | && GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND | |
56 | && GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode | |
57 | && GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG) | |
58 | return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode); | |
59 | return 0; | |
60 | }) | |
61 | ||
5a2fc4d7 OE |
62 | ;; Like above, but for DImode destinations: forbid paradoxical DImode |
63 | ;; subregs, because this would lead to missing sign extensions when | |
64 | ;; truncating from DImode to SImode. | |
65 | (define_predicate "arith_reg_dest" | |
66 | (and (match_code "subreg,reg") | |
67 | (match_operand 0 "arith_reg_operand"))) | |
74bd0da1 | 68 | |
5a2fc4d7 OE |
69 | ;; Returns true if OP is a valid source operand for an arithmetic insn. |
70 | (define_predicate "arith_operand" | |
71 | (and (match_code "subreg,reg,const_int,truncate") | |
72 | (ior (match_operand 0 "arith_reg_operand") | |
73 | (match_test "satisfies_constraint_I08 (op)")))) | |
5546ac90 | 74 | |
5a2fc4d7 OE |
75 | ;; Likewise arith_operand but always permits const_int. |
76 | (define_predicate "arith_or_int_operand" | |
77 | (and (match_code "subreg,reg,const_int,const_vector") | |
78 | (ior (match_operand 0 "arith_operand") | |
79 | (match_operand 0 "const_int_operand")))) | |
5546ac90 | 80 | |
5a2fc4d7 OE |
81 | ;; Returns true if OP is a valid source operand for a compare insn. |
82 | (define_predicate "arith_reg_or_0_operand" | |
83 | (and (match_code "subreg,reg,const_int,const_vector") | |
84 | (ior (match_operand 0 "arith_reg_operand") | |
85 | (match_test "satisfies_constraint_Z (op)")))) | |
5546ac90 | 86 | |
2353515d OE |
87 | ;; Returns true if OP is either a register or constant 0 or constant 1. |
88 | (define_predicate "arith_reg_or_0_or_1_operand" | |
5a2fc4d7 OE |
89 | (and (match_code "subreg,reg,const_int,const_vector") |
90 | (ior (match_operand 0 "arith_reg_or_0_operand") | |
91 | (match_test "satisfies_constraint_M (op)")))) | |
2353515d OE |
92 | |
93 | ;; Returns true if OP is a suitable constant for the minimum value of a | |
94 | ;; clips.b or clips.w insn. | |
95 | (define_predicate "clips_min_const_int" | |
96 | (and (match_code "const_int") | |
97 | (ior (match_test "INTVAL (op) == -128") | |
98 | (match_test "INTVAL (op) == -32768")))) | |
99 | ||
100 | ;; Returns true if OP is a suitable constant for the maximum value of a | |
101 | ;; clips.b or clips.w insn. | |
102 | (define_predicate "clips_max_const_int" | |
103 | (and (match_code "const_int") | |
104 | (ior (match_test "INTVAL (op) == 127") | |
105 | (match_test "INTVAL (op) == 32767")))) | |
106 | ||
107 | ;; Returns true if OP is a suitable constant for the maximum value of a | |
108 | ;; clipu.b or clipu.w insn. | |
109 | (define_predicate "clipu_max_const_int" | |
110 | (and (match_code "const_int") | |
111 | (ior (match_test "INTVAL (op) == 255") | |
112 | (match_test "INTVAL (op) == 65535")))) | |
113 | ||
50fe8924 OE |
114 | ;; Returns true if OP is a floating point register that can be used in floating |
115 | ;; point arithmetic operations. | |
5546ac90 KH |
116 | (define_predicate "fp_arith_reg_operand" |
117 | (match_code "subreg,reg") | |
118 | { | |
119 | if (register_operand (op, mode)) | |
120 | { | |
121 | int regno; | |
122 | ||
f3536097 | 123 | if (REG_P (op)) |
5546ac90 | 124 | regno = REGNO (op); |
f3536097 | 125 | else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) |
5546ac90 KH |
126 | regno = REGNO (SUBREG_REG (op)); |
127 | else | |
128 | return 1; | |
129 | ||
130 | return (regno >= FIRST_PSEUDO_REGISTER | |
131 | || FP_REGISTER_P (regno)); | |
132 | } | |
133 | return 0; | |
134 | }) | |
135 | ||
50fe8924 | 136 | ;; Returns true if OP is the FPSCR. |
5546ac90 | 137 | (define_predicate "fpscr_operand" |
fe3e478f OE |
138 | (and (match_code "reg") |
139 | (match_test "REGNO (op) == FPSCR_REG"))) | |
140 | ||
141 | ;; Returns true if OP is a valid source operand for a FPSCR move insn. | |
142 | (define_predicate "fpscr_movsrc_operand" | |
143 | (match_code "reg,subreg,mem") | |
5546ac90 | 144 | { |
fe3e478f OE |
145 | if (arith_reg_operand (op, mode)) |
146 | return true; | |
147 | ||
148 | return MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC; | |
149 | }) | |
150 | ||
151 | ;; Returns true if OP is a valid destination operand for a FPSCR move insn. | |
152 | (define_predicate "fpscr_movdst_operand" | |
153 | (match_code "reg,subreg,mem") | |
154 | { | |
155 | if (arith_reg_dest (op, mode)) | |
156 | return true; | |
157 | ||
158 | return MEM_P (op) && GET_CODE (XEXP (op, 0)) == PRE_DEC; | |
5546ac90 KH |
159 | }) |
160 | ||
db292b0e OE |
161 | ;; Returns true if OP is an operand that is either the fpul hard reg or |
162 | ;; a pseudo. This prevents combine from propagating function arguments | |
163 | ;; in hard regs into insns that need the operand in fpul. If it's a pseudo | |
164 | ;; reload can fix it up. | |
5546ac90 KH |
165 | (define_predicate "fpul_operand" |
166 | (match_code "reg") | |
167 | { | |
e1fab8ba OE |
168 | return REG_P (op) |
169 | && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
170 | && GET_MODE (op) == mode; | |
5546ac90 KH |
171 | }) |
172 | ||
db292b0e OE |
173 | ;; Returns true if OP is a valid fpul input operand for the fsca insn. |
174 | ;; The value in fpul is a fixed-point value and its scaling is described | |
175 | ;; in the fsca insn by a mult:SF. To allow pre-scaled fixed-point inputs | |
176 | ;; in fpul we have to permit things like | |
177 | ;; (reg:SI) | |
178 | ;; (fix:SF (float:SF (reg:SI))) | |
179 | (define_predicate "fpul_fsca_operand" | |
180 | (match_code "fix,reg") | |
181 | { | |
182 | if (fpul_operand (op, SImode)) | |
183 | return true; | |
184 | if (GET_CODE (op) == FIX && GET_MODE (op) == SImode | |
185 | && GET_CODE (XEXP (op, 0)) == FLOAT && GET_MODE (XEXP (op, 0)) == SFmode) | |
186 | return fpul_fsca_operand (XEXP (XEXP (op, 0), 0), | |
187 | GET_MODE (XEXP (XEXP (op, 0), 0))); | |
188 | return false; | |
189 | }) | |
190 | ||
191 | ;; Returns true if OP is a valid constant scale factor for the fsca insn. | |
192 | (define_predicate "fsca_scale_factor" | |
193 | (and (match_code "const_double") | |
194 | (match_test "op == sh_fsca_int2sf ()"))) | |
195 | ||
50fe8924 | 196 | ;; Returns true if OP is an operand that is zero extended during an operation. |
5546ac90 KH |
197 | (define_predicate "general_extend_operand" |
198 | (match_code "subreg,reg,mem,truncate") | |
199 | { | |
3f0d5131 | 200 | if (reload_completed && GET_CODE (op) == TRUNCATE) |
0bcf9a09 OE |
201 | return arith_operand (op, mode); |
202 | ||
203 | if (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))) | |
204 | return general_movsrc_operand (op, mode); | |
205 | ||
206 | return nonimmediate_operand (op, mode); | |
5546ac90 KH |
207 | }) |
208 | ||
24c18ad8 OE |
209 | ;; Returns 1 if OP is a simple register address. |
210 | (define_predicate "simple_mem_operand" | |
211 | (and (match_code "mem") | |
21f65dc8 | 212 | (match_code "reg" "0") |
24c18ad8 OE |
213 | (match_test "arith_reg_operand (XEXP (op, 0), SImode)"))) |
214 | ||
215 | ;; Returns 1 if OP is a valid displacement address. | |
216 | (define_predicate "displacement_mem_operand" | |
217 | (and (match_code "mem") | |
21f65dc8 OE |
218 | (match_code "plus" "0") |
219 | (match_code "reg" "00") | |
24c18ad8 OE |
220 | (match_test "arith_reg_operand (XEXP (XEXP (op, 0), 0), SImode)") |
221 | (match_test "sh_legitimate_index_p (GET_MODE (op), | |
222 | XEXP (XEXP (op, 0), 1), | |
223 | TARGET_SH2A, true)"))) | |
224 | ||
91f65b12 OE |
225 | ;; Returns true if OP is a displacement address that can fit into a |
226 | ;; 16 bit (non-SH2A) memory load / store insn. | |
227 | (define_predicate "short_displacement_mem_operand" | |
21f65dc8 OE |
228 | (and (match_code "mem") |
229 | (match_operand 0 "displacement_mem_operand") | |
230 | (match_test "sh_disp_addr_displacement (op) | |
231 | <= sh_max_mov_insn_displacement (GET_MODE (op), false)"))) | |
91f65b12 | 232 | |
24c18ad8 OE |
233 | ;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn. |
234 | (define_predicate "zero_extend_movu_operand" | |
841dbf80 OE |
235 | (and (ior (match_operand 0 "displacement_mem_operand") |
236 | (match_operand 0 "simple_mem_operand")) | |
237 | (ior (match_test "GET_MODE (op) == QImode") | |
238 | (match_test "GET_MODE (op) == HImode")))) | |
24c18ad8 | 239 | |
5546ac90 KH |
240 | ;; Returns 1 if OP can be source of a simple move operation. Same as |
241 | ;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as | |
242 | ;; are subregs of system registers. | |
5546ac90 | 243 | (define_predicate "general_movsrc_operand" |
50fe8924 OE |
244 | (match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref, |
245 | const,const_vector") | |
5546ac90 | 246 | { |
ef812306 OE |
247 | if (t_reg_operand (op, mode)) |
248 | return 0; | |
249 | ||
fe3e478f OE |
250 | if (fpscr_operand (op, mode)) |
251 | return false; | |
252 | ||
91f65b12 OE |
253 | /* Disallow PC relative QImode loads, since these is no insn to do that |
254 | and an imm8 load should be used instead. */ | |
255 | if (IS_PC_RELATIVE_LOAD_ADDR_P (op) && GET_MODE (op) == QImode) | |
256 | return false; | |
257 | ||
f3536097 | 258 | if (MEM_P (op)) |
5546ac90 KH |
259 | { |
260 | rtx inside = XEXP (op, 0); | |
fce1e5fb OE |
261 | |
262 | /* Disallow mems with GBR address here. They have to go through | |
263 | separate special patterns. */ | |
264 | if ((REG_P (inside) && REGNO (inside) == GBR_REG) | |
265 | || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0)) | |
266 | && REGNO (XEXP (inside, 0)) == GBR_REG)) | |
267 | return 0; | |
268 | ||
5546ac90 KH |
269 | if (GET_CODE (inside) == CONST) |
270 | inside = XEXP (inside, 0); | |
271 | ||
272 | if (GET_CODE (inside) == LABEL_REF) | |
273 | return 1; | |
274 | ||
275 | if (GET_CODE (inside) == PLUS | |
276 | && GET_CODE (XEXP (inside, 0)) == LABEL_REF | |
f3536097 | 277 | && CONST_INT_P (XEXP (inside, 1))) |
5546ac90 KH |
278 | return 1; |
279 | ||
280 | /* Only post inc allowed. */ | |
281 | if (GET_CODE (inside) == PRE_DEC) | |
282 | return 0; | |
283 | } | |
284 | ||
0bcf9a09 OE |
285 | if (mode == GET_MODE (op) |
286 | && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))))) | |
a700b5f0 | 287 | { |
0bcf9a09 OE |
288 | rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op); |
289 | rtx x = XEXP (mem_rtx, 0); | |
a700b5f0 | 290 | |
fc1fcfa0 KK |
291 | if (GET_CODE (x) == PLUS) |
292 | { | |
293 | rtx y = XEXP (x, 0); | |
294 | ||
295 | if (! REG_P (y) | |
296 | && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))) | |
297 | return false; | |
298 | y = XEXP (x, 1); | |
299 | if (! REG_P (y) | |
300 | && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))) | |
301 | && ! CONST_INT_P (y)) | |
302 | return false; | |
303 | } | |
304 | ||
305 | /* LRA will try to satisfy the constraints for the memory displacements | |
306 | and thus we must not reject invalid displacements in the predicate, | |
307 | or else LRA will bail out. | |
308 | FIXME: maybe remove this check completely? */ | |
309 | if (!lra_in_progress && (mode == QImode || mode == HImode) | |
0bcf9a09 | 310 | && GET_CODE (x) == PLUS |
a700b5f0 KK |
311 | && REG_P (XEXP (x, 0)) |
312 | && CONST_INT_P (XEXP (x, 1))) | |
8c2a3f3b | 313 | return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false); |
0bcf9a09 OE |
314 | |
315 | /* Allow reg+reg addressing here without validating the register | |
316 | numbers. Usually one of the regs must be R0 or a pseudo reg. | |
317 | In some cases it can happen that arguments from hard regs are | |
318 | propagated directly into address expressions. In this cases reload | |
319 | will have to fix it up later. However, allow this only for native | |
320 | 1, 2 or 4 byte addresses. */ | |
321 | if (can_create_pseudo_p () && GET_CODE (x) == PLUS | |
322 | && GET_MODE_SIZE (mode) <= 4 | |
323 | && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1))) | |
324 | return true; | |
325 | ||
326 | /* 'general_operand' does not allow volatile mems during RTL expansion to | |
327 | avoid matching arithmetic that operates on mems, it seems. | |
328 | On SH this leads to redundant sign extensions for QImode or HImode | |
329 | loads. Thus we mimic the behavior but allow volatile mems. */ | |
330 | if (memory_address_addr_space_p (GET_MODE (mem_rtx), x, | |
331 | MEM_ADDR_SPACE (mem_rtx))) | |
332 | return true; | |
a700b5f0 KK |
333 | } |
334 | ||
5546ac90 KH |
335 | return general_operand (op, mode); |
336 | }) | |
337 | ||
5a2fc4d7 | 338 | ;; Returns true if OP is a MEM that does not use displacement addressing. |
344332e8 | 339 | (define_predicate "movsrc_no_disp_mem_operand" |
5a2fc4d7 OE |
340 | (and (match_code "mem") |
341 | (match_operand 0 "general_movsrc_operand") | |
342 | (match_test "satisfies_constraint_Snd (op)"))) | |
344332e8 | 343 | |
5546ac90 KH |
344 | ;; Returns 1 if OP can be a destination of a move. Same as |
345 | ;; general_operand, but no preinc allowed. | |
5546ac90 KH |
346 | (define_predicate "general_movdst_operand" |
347 | (match_code "subreg,reg,mem") | |
348 | { | |
ef812306 OE |
349 | if (t_reg_operand (op, mode)) |
350 | return 0; | |
351 | ||
fe3e478f OE |
352 | if (fpscr_operand (op, mode)) |
353 | return false; | |
354 | ||
fce1e5fb OE |
355 | if (MEM_P (op)) |
356 | { | |
357 | rtx inside = XEXP (op, 0); | |
358 | /* Disallow mems with GBR address here. They have to go through | |
359 | separate special patterns. */ | |
360 | if ((REG_P (inside) && REGNO (inside) == GBR_REG) | |
361 | || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0)) | |
362 | && REGNO (XEXP (inside, 0)) == GBR_REG)) | |
363 | return 0; | |
364 | } | |
365 | ||
5546ac90 | 366 | /* Only pre dec allowed. */ |
f3536097 | 367 | if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC) |
5546ac90 | 368 | return 0; |
5546ac90 | 369 | |
35d1b083 OE |
370 | if (mode == GET_MODE (op) |
371 | && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))))) | |
a700b5f0 | 372 | { |
35d1b083 OE |
373 | rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op); |
374 | rtx x = XEXP (mem_rtx, 0); | |
a700b5f0 | 375 | |
fc1fcfa0 KK |
376 | if (GET_CODE (x) == PLUS) |
377 | { | |
378 | rtx y = XEXP (x, 0); | |
379 | ||
380 | if (! REG_P (y) | |
381 | && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))) | |
382 | return false; | |
383 | y = XEXP (x, 1); | |
384 | if (! REG_P (y) | |
385 | && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))) | |
386 | && ! CONST_INT_P (y)) | |
387 | return false; | |
388 | } | |
389 | ||
390 | /* LRA will try to satisfy the constraints for the memory displacements | |
391 | and thus we must not reject invalid displacements in the predicate, | |
392 | or else LRA will bail out. | |
393 | FIXME: maybe remove this check completely? */ | |
394 | if (!lra_in_progress && (mode == QImode || mode == HImode) | |
35d1b083 | 395 | && GET_CODE (x) == PLUS |
a700b5f0 KK |
396 | && REG_P (XEXP (x, 0)) |
397 | && CONST_INT_P (XEXP (x, 1))) | |
8c2a3f3b | 398 | return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false); |
35d1b083 OE |
399 | |
400 | /* Allow reg+reg addressing here without validating the register | |
401 | numbers. Usually one of the regs must be R0 or a pseudo reg. | |
402 | In some cases it can happen that arguments from hard regs are | |
403 | propagated directly into address expressions. In this cases reload | |
404 | will have to fix it up later. However, allow this only for native | |
405 | 1, 2 or 4 byte addresses. */ | |
406 | if (can_create_pseudo_p () && GET_CODE (x) == PLUS | |
407 | && GET_MODE_SIZE (mode) <= 4 | |
408 | && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1))) | |
409 | return true; | |
410 | ||
411 | /* 'general_operand' does not allow volatile mems during RTL expansion to | |
412 | avoid matching arithmetic that operates on mems, it seems. | |
413 | On SH this leads to redundant sign extensions for QImode or HImode | |
414 | stores. Thus we mimic the behavior but allow volatile mems. */ | |
415 | if (memory_address_addr_space_p (GET_MODE (mem_rtx), x, | |
416 | MEM_ADDR_SPACE (mem_rtx))) | |
417 | return true; | |
a700b5f0 KK |
418 | } |
419 | ||
5546ac90 KH |
420 | return general_operand (op, mode); |
421 | }) | |
422 | ||
423 | ;; Returns 1 if OP is a MEM that can be source of a simple move operation. | |
5546ac90 KH |
424 | (define_predicate "unaligned_load_operand" |
425 | (match_code "mem") | |
426 | { | |
427 | rtx inside; | |
428 | ||
f3536097 | 429 | if (!MEM_P (op) || GET_MODE (op) != mode) |
5546ac90 KH |
430 | return 0; |
431 | ||
432 | inside = XEXP (op, 0); | |
433 | ||
434 | if (GET_CODE (inside) == POST_INC) | |
435 | inside = XEXP (inside, 0); | |
436 | ||
f3536097 | 437 | if (REG_P (inside)) |
5546ac90 KH |
438 | return 1; |
439 | ||
440 | return 0; | |
441 | }) | |
442 | ||
b67b3838 OE |
443 | ;; Returns 1 if OP is a MEM that can be used in "index_disp" combiner |
444 | ;; patterns. | |
445 | (define_predicate "mem_index_disp_operand" | |
446 | (match_code "mem") | |
447 | { | |
448 | rtx plus0_rtx, plus1_rtx, mult_rtx; | |
449 | ||
450 | plus0_rtx = XEXP (op, 0); | |
451 | if (GET_CODE (plus0_rtx) != PLUS) | |
452 | return 0; | |
453 | ||
454 | plus1_rtx = XEXP (plus0_rtx, 0); | |
455 | if (GET_CODE (plus1_rtx) != PLUS) | |
456 | return 0; | |
05852a5f OE |
457 | if (! arith_reg_operand (XEXP (plus1_rtx, 1), GET_MODE (XEXP (plus1_rtx, 1)))) |
458 | return 0; | |
b67b3838 OE |
459 | |
460 | mult_rtx = XEXP (plus1_rtx, 0); | |
461 | if (GET_CODE (mult_rtx) != MULT) | |
462 | return 0; | |
05852a5f OE |
463 | if (! arith_reg_operand (XEXP (mult_rtx, 0), GET_MODE (XEXP (mult_rtx, 0))) |
464 | || ! CONST_INT_P (XEXP (mult_rtx, 1))) | |
465 | return 0; | |
466 | ||
467 | return exact_log2 (INTVAL (XEXP (mult_rtx, 1))) > 0 | |
b67b3838 OE |
468 | && sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true); |
469 | }) | |
470 | ||
5a2fc4d7 | 471 | ;; Returns true if OP is a valid source operand for a logical operation. |
5546ac90 | 472 | (define_predicate "logical_operand" |
5a2fc4d7 OE |
473 | (and (match_code "subreg,reg,const_int") |
474 | (ior (match_operand 0 "arith_reg_operand") | |
475 | (match_test "satisfies_constraint_K08 (op)")))) | |
5546ac90 | 476 | |
dac2637b OE |
477 | ;; Returns true if OP is a valid constant source operand for a logical |
478 | ;; operations tst/and/or/xor #imm,r0. | |
479 | (define_predicate "const_logical_operand" | |
480 | (and (match_code "const_int") | |
481 | (match_test "satisfies_constraint_K08 (op)"))) | |
482 | ||
5e204a6e OE |
483 | ;; Like logical_operand but allows additional constant values which can be |
484 | ;; done with zero extensions. Used for the second operand of and insns. | |
485 | (define_predicate "logical_and_operand" | |
5a2fc4d7 OE |
486 | (and (match_code "subreg,reg,const_int") |
487 | (ior (match_operand 0 "logical_operand") | |
488 | (match_test "satisfies_constraint_Jmb (op)") | |
489 | (match_test "satisfies_constraint_Jmw (op)")))) | |
5e204a6e | 490 | |
50fe8924 | 491 | ;; Returns true if OP is a logical operator. |
5546ac90 | 492 | (define_predicate "logical_operator" |
f289c6a1 | 493 | (match_code "and,ior,xor")) |
5546ac90 | 494 | |
50fe8924 | 495 | ;; Returns true if OP is a constant vector. |
5546ac90 KH |
496 | (define_predicate "sh_const_vec" |
497 | (match_code "const_vector") | |
498 | { | |
5a2fc4d7 | 499 | for (int i = XVECLEN (op, 0) - 1; i >= 0; i--) |
f3536097 | 500 | if (!CONST_INT_P (XVECEXP (op, 0, i))) |
5a2fc4d7 OE |
501 | return false; |
502 | return true; | |
5546ac90 KH |
503 | }) |
504 | ||
505 | ;; Determine if OP is a constant vector matching MODE with only one | |
506 | ;; element that is not a sign extension. Two byte-sized elements | |
507 | ;; count as one. | |
5546ac90 KH |
508 | (define_predicate "sh_1el_vec" |
509 | (match_code "const_vector") | |
510 | { | |
5546ac90 | 511 | /* Determine numbers of last and of least significant elements. */ |
5a2fc4d7 OE |
512 | int last = XVECLEN (op, 0) - 1; |
513 | int least = TARGET_LITTLE_ENDIAN ? 0 : last; | |
f3536097 | 514 | if (!CONST_INT_P (XVECEXP (op, 0, least))) |
5a2fc4d7 OE |
515 | return false; |
516 | int sign_ix = least; | |
5546ac90 KH |
517 | if (GET_MODE_UNIT_SIZE (mode) == 1) |
518 | sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1; | |
f3536097 | 519 | if (!CONST_INT_P (XVECEXP (op, 0, sign_ix))) |
5a2fc4d7 OE |
520 | return false; |
521 | int unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op)); | |
522 | rtx sign = INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1) | |
523 | ? constm1_rtx : const0_rtx; | |
524 | int i = XVECLEN (op, 0) - 1; | |
5546ac90 KH |
525 | do |
526 | if (i != least && i != sign_ix && XVECEXP (op, 0, i) != sign) | |
527 | return 0; | |
528 | while (--i); | |
5a2fc4d7 | 529 | return true; |
5546ac90 KH |
530 | }) |
531 | ||
50fe8924 OE |
532 | ;; Returns true if OP is a vector which is composed of one element that is |
533 | ;; repeated. | |
5546ac90 | 534 | (define_predicate "sh_rep_vec" |
b4060d3f | 535 | (match_code "const_vector,parallel") |
5546ac90 | 536 | { |
5a2fc4d7 OE |
537 | int i = XVECLEN (op, 0) - 2; |
538 | rtx x = XVECEXP (op, 0, i + 1); | |
5546ac90 KH |
539 | if (GET_MODE_UNIT_SIZE (mode) == 1) |
540 | { | |
5a2fc4d7 | 541 | rtx y = XVECEXP (op, 0, i); |
5546ac90 KH |
542 | for (i -= 2; i >= 0; i -= 2) |
543 | if (! rtx_equal_p (XVECEXP (op, 0, i + 1), x) | |
544 | || ! rtx_equal_p (XVECEXP (op, 0, i), y)) | |
5a2fc4d7 | 545 | return false; |
5546ac90 KH |
546 | } |
547 | else | |
548 | for (; i >= 0; i--) | |
549 | if (XVECEXP (op, 0, i) != x) | |
5a2fc4d7 OE |
550 | return false; |
551 | return true; | |
5546ac90 KH |
552 | }) |
553 | ||
50fe8924 | 554 | ;; Returns true if OP is a valid shift count operand for shift operations. |
5546ac90 | 555 | (define_predicate "shift_count_operand" |
50fe8924 OE |
556 | (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg, |
557 | zero_extend,sign_extend") | |
5546ac90 | 558 | { |
d8a48c21 OE |
559 | /* Allow T_REG as shift count for dynamic shifts, although it is not |
560 | really possible. It will then be copied to a general purpose reg. */ | |
e1fab8ba OE |
561 | return const_int_operand (op, mode) || arith_reg_operand (op, mode) |
562 | || (TARGET_DYNSHIFT && t_reg_operand (op, mode)); | |
5546ac90 KH |
563 | }) |
564 | ||
6e01d526 OE |
565 | ;; Predicates for matching operands that are constant shift |
566 | ;; amounts 1, 2, 8, 16. | |
d8a48c21 OE |
567 | (define_predicate "p27_shift_count_operand" |
568 | (and (match_code "const_int") | |
569 | (match_test "satisfies_constraint_P27 (op)"))) | |
570 | ||
571 | (define_predicate "not_p27_shift_count_operand" | |
572 | (and (match_code "const_int") | |
573 | (match_test "! satisfies_constraint_P27 (op)"))) | |
574 | ||
6e01d526 OE |
575 | ;; For right shifts the constant 1 is a special case because the shlr insn |
576 | ;; clobbers the T_REG and is handled by the T_REG clobbering version of the | |
577 | ;; insn, which is also used for non-P27 shift sequences. | |
578 | (define_predicate "p27_rshift_count_operand" | |
579 | (and (match_code "const_int") | |
580 | (match_test "satisfies_constraint_P27 (op)") | |
581 | (match_test "! satisfies_constraint_M (op)"))) | |
582 | ||
583 | (define_predicate "not_p27_rshift_count_operand" | |
584 | (and (match_code "const_int") | |
585 | (ior (match_test "! satisfies_constraint_P27 (op)") | |
586 | (match_test "satisfies_constraint_M (op)")))) | |
587 | ||
50fe8924 | 588 | ;; Returns true if OP is a symbol reference. |
5546ac90 | 589 | (define_predicate "symbol_ref_operand" |
f289c6a1 | 590 | (match_code "symbol_ref")) |
5546ac90 | 591 | |
9eb3a0dd N |
592 | (define_predicate "bitwise_memory_operand" |
593 | (match_code "mem") | |
594 | { | |
f3536097 | 595 | if (MEM_P (op)) |
9eb3a0dd N |
596 | { |
597 | if (REG_P (XEXP (op, 0))) | |
598 | return 1; | |
599 | ||
600 | if (GET_CODE (XEXP (op, 0)) == PLUS | |
f3536097 | 601 | && REG_P (XEXP (XEXP (op, 0), 0)) |
9eb3a0dd N |
602 | && satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1))) |
603 | return 1; | |
604 | } | |
605 | return 0; | |
606 | }) | |
c11394f8 | 607 | |
841dbf80 OE |
608 | ;; A predicate that matches any expression for which there is an |
609 | ;; insn pattern that sets the T bit. | |
610 | (define_predicate "treg_set_expr" | |
611 | (match_test "sh_recog_treg_set_expr (op, mode)")) | |
612 | ||
613 | ;; Same as treg_set_expr but disallow constants 0 and 1 which can be loaded | |
614 | ;; into the T bit. | |
615 | (define_predicate "treg_set_expr_not_const01" | |
616 | (and (match_test "op != const0_rtx") | |
617 | (match_test "op != const1_rtx") | |
618 | (match_operand 0 "treg_set_expr"))) | |
619 | ||
f031c344 OE |
620 | ;; A predicate describing the T bit register in any form. |
621 | (define_predicate "t_reg_operand" | |
6fb917d9 | 622 | (match_code "reg,subreg,sign_extend,zero_extend,ne,eq") |
f031c344 OE |
623 | { |
624 | switch (GET_CODE (op)) | |
625 | { | |
6fb917d9 OE |
626 | case EQ: |
627 | return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))) | |
628 | && XEXP (op, 1) == const1_rtx; | |
629 | ||
630 | case NE: | |
631 | return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))) | |
632 | && XEXP (op, 1) == const0_rtx; | |
633 | ||
f031c344 OE |
634 | case REG: |
635 | return REGNO (op) == T_REG; | |
636 | ||
637 | case SUBREG: | |
312f9b9d | 638 | return REG_P (SUBREG_REG (op)) && REGNO (SUBREG_REG (op)) == T_REG; |
f031c344 OE |
639 | |
640 | case ZERO_EXTEND: | |
641 | case SIGN_EXTEND: | |
fc1fcfa0 KK |
642 | if (REG_P (XEXP (op, 0)) && REGNO (XEXP (op, 0)) == T_REG) |
643 | return true; | |
f031c344 | 644 | return GET_CODE (XEXP (op, 0)) == SUBREG |
312f9b9d | 645 | && REG_P (SUBREG_REG (XEXP (op, 0))) |
f031c344 OE |
646 | && REGNO (SUBREG_REG (XEXP (op, 0))) == T_REG; |
647 | ||
648 | default: | |
649 | return 0; | |
650 | } | |
651 | }) | |
652 | ||
653 | ;; A predicate describing a negated T bit register. | |
654 | (define_predicate "negt_reg_operand" | |
6fb917d9 | 655 | (match_code "subreg,xor,ne,eq") |
f031c344 OE |
656 | { |
657 | switch (GET_CODE (op)) | |
658 | { | |
6fb917d9 OE |
659 | case EQ: |
660 | return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))) | |
661 | && XEXP (op, 1) == const0_rtx; | |
662 | ||
663 | case NE: | |
664 | return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))) | |
665 | && XEXP (op, 1) == const1_rtx; | |
666 | ||
f031c344 OE |
667 | case XOR: |
668 | return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))) | |
6fb917d9 | 669 | && XEXP (op, 1) == const1_rtx; |
f031c344 OE |
670 | |
671 | case SUBREG: | |
672 | return negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))); | |
673 | ||
674 | default: | |
675 | return 0; | |
676 | } | |
677 | }) | |
4eddc42b | 678 | |
5a2fc4d7 OE |
679 | ;; Returns true if OP is an operand that can be used as the first operand in |
680 | ;; the cstoresi4 expander pattern. | |
681 | (define_predicate "cmpsi_operand" | |
682 | (and (match_code "subreg,reg,const_int") | |
683 | (ior (match_operand:SI 0 "t_reg_operand") | |
684 | (match_operand 0 "arith_operand")))) | |
685 | ||
b4eca9c8 OE |
686 | ;; A predicate that returns true if OP is a valid construct around the T bit |
687 | ;; that can be used as an operand for conditional branches. | |
688 | (define_predicate "cbranch_treg_value" | |
48d8568e OE |
689 | (and (match_code "eq,ne,reg,subreg,xor,sign_extend,zero_extend") |
690 | (match_test "sh_eval_treg_value (op) >= 0"))) | |
b4eca9c8 | 691 | |
50fe8924 | 692 | ;; Returns true if OP is arith_reg_operand or t_reg_operand. |
4eddc42b OE |
693 | (define_predicate "arith_reg_or_t_reg_operand" |
694 | (ior (match_operand 0 "arith_reg_operand") | |
695 | (match_operand 0 "t_reg_operand"))) | |
78040535 | 696 | |
841dbf80 OE |
697 | (define_predicate "arith_reg_or_treg_set_expr" |
698 | (ior (match_operand 0 "arith_reg_operand") | |
699 | (match_operand 0 "treg_set_expr"))) | |
700 | ||
78040535 OE |
701 | ;; A predicate describing the negated value of the T bit register shifted |
702 | ;; left by 31. | |
703 | (define_predicate "negt_reg_shl31_operand" | |
704 | (match_code "plus,minus,if_then_else") | |
705 | { | |
b200de02 OE |
706 | /* (minus:SI (const_int -2147483648) ;; 0xffffffff80000000 |
707 | (ashift:SI (match_operand:SI 1 "t_reg_operand") | |
708 | (const_int 31))) | |
709 | */ | |
710 | if (GET_CODE (op) == MINUS && satisfies_constraint_Jhb (XEXP (op, 0)) | |
711 | && GET_CODE (XEXP (op, 1)) == ASHIFT | |
712 | && t_reg_operand (XEXP (XEXP (op, 1), 0), SImode) | |
713 | && CONST_INT_P (XEXP (XEXP (op, 1), 1)) | |
714 | && INTVAL (XEXP (XEXP (op, 1), 1)) == 31) | |
715 | return true; | |
716 | ||
717 | /* (plus:SI (ashift:SI (match_operand:SI 1 "t_reg_operand") | |
718 | (const_int 31)) | |
719 | (const_int -2147483648)) ;; 0xffffffff80000000 | |
720 | */ | |
721 | if (GET_CODE (op) == PLUS && satisfies_constraint_Jhb (XEXP (op, 1)) | |
722 | && GET_CODE (XEXP (op, 0)) == ASHIFT | |
723 | && t_reg_operand (XEXP (XEXP (op, 0), 0), SImode) | |
724 | && CONST_INT_P (XEXP (XEXP (op, 0), 1)) | |
725 | && INTVAL (XEXP (XEXP (op, 0), 1)) == 31) | |
726 | return true; | |
727 | ||
78040535 OE |
728 | /* (plus:SI (mult:SI (match_operand:SI 1 "t_reg_operand") |
729 | (const_int -2147483648)) ;; 0xffffffff80000000 | |
730 | (const_int -2147483648)) | |
731 | */ | |
732 | if (GET_CODE (op) == PLUS && satisfies_constraint_Jhb (XEXP (op, 1)) | |
733 | && GET_CODE (XEXP (op, 0)) == MULT | |
734 | && t_reg_operand (XEXP (XEXP (op, 0), 0), SImode) | |
735 | && satisfies_constraint_Jhb (XEXP (XEXP (op, 0), 1))) | |
736 | return true; | |
737 | ||
738 | /* (minus:SI (const_int -2147483648) ;; 0xffffffff80000000 | |
739 | (mult:SI (match_operand:SI 1 "t_reg_operand") | |
740 | (const_int -2147483648))) | |
741 | */ | |
742 | if (GET_CODE (op) == MINUS | |
743 | && satisfies_constraint_Jhb (XEXP (op, 0)) | |
744 | && GET_CODE (XEXP (op, 1)) == MULT | |
745 | && t_reg_operand (XEXP (XEXP (op, 1), 0), SImode) | |
746 | && satisfies_constraint_Jhb (XEXP (XEXP (op, 1), 1))) | |
747 | return true; | |
748 | ||
749 | /* (if_then_else:SI (match_operand:SI 1 "t_reg_operand") | |
750 | (const_int 0) | |
751 | (const_int -2147483648)) ;; 0xffffffff80000000 | |
752 | */ | |
753 | if (GET_CODE (op) == IF_THEN_ELSE && t_reg_operand (XEXP (op, 0), SImode) | |
754 | && satisfies_constraint_Z (XEXP (op, 1)) | |
755 | && satisfies_constraint_Jhb (XEXP (op, 2))) | |
756 | return true; | |
757 | ||
758 | return false; | |
759 | }) | |
7bd76b9c OE |
760 | |
761 | ;; A predicate that determines whether a given constant is a valid | |
50fe8924 | 762 | ;; displacement for a GBR load/store of the specified mode. |
7bd76b9c OE |
763 | (define_predicate "gbr_displacement" |
764 | (match_code "const_int") | |
765 | { | |
766 | const int mode_sz = GET_MODE_SIZE (mode); | |
767 | const int move_sz = mode_sz > GET_MODE_SIZE (SImode) | |
768 | ? GET_MODE_SIZE (SImode) | |
769 | : mode_sz; | |
770 | int max_disp = 255 * move_sz; | |
771 | if (mode_sz > move_sz) | |
772 | max_disp -= mode_sz - move_sz; | |
773 | ||
774 | return INTVAL (op) >= 0 && INTVAL (op) <= max_disp; | |
775 | }) | |
14df3f36 OE |
776 | |
777 | ;; A predicate that determines whether OP is a valid GBR addressing mode | |
778 | ;; memory reference. | |
779 | (define_predicate "gbr_address_mem" | |
780 | (match_code "mem") | |
781 | { | |
782 | rtx addr = XEXP (op, 0); | |
783 | ||
784 | if (REG_P (addr) && REGNO (addr) == GBR_REG) | |
785 | return true; | |
786 | if (GET_CODE (addr) == PLUS | |
787 | && REG_P (XEXP (addr, 0)) && REGNO (XEXP (addr, 0)) == GBR_REG | |
788 | && gbr_displacement (XEXP (addr, 1), mode)) | |
789 | return true; | |
790 | ||
791 | return false; | |
792 | }) |