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c8f0269d | 1 | /* Output routines for GCC for Renesas / SuperH SH. |
5624e564 | 2 | Copyright (C) 1993-2015 Free Software Foundation, Inc. |
c5c76735 | 3 | Contributed by Steve Chamberlain (sac@cygnus.com). |
f676971a | 4 | Improved by Jim Wilson (wilson@cygnus.com). |
bc45ade3 | 5 | |
7ec022b2 | 6 | This file is part of GCC. |
c15c9075 | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
c15c9075 | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
c15c9075 RK |
11 | any later version. |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
c15c9075 RK |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
bc45ade3 | 21 | |
0bcf70f8 OE |
22 | #include <sstream> |
23 | #include <vector> | |
0bcf70f8 | 24 | |
bc45ade3 | 25 | #include "config.h" |
c5c76735 | 26 | #include "system.h" |
4977bab6 | 27 | #include "coretypes.h" |
c7131fb2 | 28 | #include "backend.h" |
9fdcd34e | 29 | #include "cfghooks.h" |
c7131fb2 AM |
30 | #include "tree.h" |
31 | #include "gimple.h" | |
bc45ade3 | 32 | #include "rtl.h" |
c7131fb2 AM |
33 | #include "df.h" |
34 | #include "insn-config.h" | |
40e23961 | 35 | #include "alias.h" |
40e23961 | 36 | #include "fold-const.h" |
d8a2d370 DN |
37 | #include "stringpool.h" |
38 | #include "stor-layout.h" | |
39 | #include "calls.h" | |
40 | #include "varasm.h" | |
bc45ade3 | 41 | #include "flags.h" |
36566b39 PK |
42 | #include "expmed.h" |
43 | #include "dojump.h" | |
44 | #include "explow.h" | |
45 | #include "emit-rtl.h" | |
46 | #include "stmt.h" | |
bc45ade3 | 47 | #include "expr.h" |
b0710fe1 | 48 | #include "insn-codes.h" |
e78d8e51 | 49 | #include "optabs.h" |
6f50eb9c | 50 | #include "reload.h" |
8aa2a305 | 51 | #include "regs.h" |
8aa2a305 | 52 | #include "output.h" |
956a5206 | 53 | #include "insn-attr.h" |
718f9c0f | 54 | #include "diagnostic-core.h" |
318881c0 | 55 | #include "recog.h" |
a80b0574 | 56 | #include "dwarf2.h" |
318881c0 | 57 | #include "tm_p.h" |
672a6f42 | 58 | #include "target.h" |
c1b92d09 | 59 | #include "langhooks.h" |
60393bbc AM |
60 | #include "cfgrtl.h" |
61 | #include "cfganal.h" | |
62 | #include "lcm.h" | |
63 | #include "cfgbuild.h" | |
64 | #include "cfgcleanup.h" | |
bcc8cc82 | 65 | #include "intl.h" |
58565a33 | 66 | #include "sched-int.h" |
bd9a3465 | 67 | #include "params.h" |
2fb9a547 AM |
68 | #include "internal-fn.h" |
69 | #include "gimple-fold.h" | |
70 | #include "tree-eh.h" | |
45b0be94 | 71 | #include "gimplify.h" |
73a4d10b | 72 | #include "cfgloop.h" |
6dd3c0a5 | 73 | #include "alloc-pool.h" |
32a7ab3d | 74 | #include "tm-constrs.h" |
96e45421 | 75 | #include "opts.h" |
5d30dc5b OE |
76 | #include "tree-pass.h" |
77 | #include "pass_manager.h" | |
78 | #include "context.h" | |
9b2b7279 | 79 | #include "builtins.h" |
5dabe5a9 | 80 | #include "rtl-iter.h" |
5fac2ed2 | 81 | |
994c5d85 | 82 | /* This file should be included last. */ |
d58627a0 RS |
83 | #include "target-def.h" |
84 | ||
1245df60 R |
85 | int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch; |
86 | ||
fa5322fa | 87 | /* These are some macros to abstract register modes. */ |
4111c296 OE |
88 | #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \ |
89 | && ((HOST_WIDE_INT)(VALUE)) <= 511) | |
90 | ||
fa5322fa | 91 | #define CONST_OK_FOR_ADD(size) \ |
735cb76e | 92 | (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size)) |
fa5322fa AO |
93 | #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi)) |
94 | #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3)) | |
95 | #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3)) | |
96 | ||
561642fa AP |
97 | /* Used to simplify the logic below. Find the attributes wherever |
98 | they may be. */ | |
99 | #define SH_ATTRIBUTES(decl) \ | |
100 | (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \ | |
101 | : DECL_ATTRIBUTES (decl) \ | |
102 | ? (DECL_ATTRIBUTES (decl)) \ | |
103 | : TYPE_ATTRIBUTES (TREE_TYPE (decl)) | |
104 | ||
552ecbd9 AH |
105 | /* Set to 1 by expand_prologue() when the function is an interrupt handler. */ |
106 | int current_function_interrupt; | |
107 | ||
a6ab9fc0 R |
108 | tree sh_deferred_function_attributes; |
109 | tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes; | |
16bea517 | 110 | |
6f317ef3 | 111 | /* Global variables for machine-dependent things. */ |
bc45ade3 | 112 | |
16bea517 JW |
113 | /* Which cpu are we scheduling for. */ |
114 | enum processor_type sh_cpu; | |
115 | ||
58565a33 SKG |
116 | /* Definitions used in ready queue reordering for first scheduling pass. */ |
117 | ||
118 | /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */ | |
119 | static short *regmode_weight[2]; | |
120 | ||
121 | /* Total SFmode and SImode weights of scheduled insns. */ | |
122 | static int curr_regmode_pressure[2]; | |
123 | ||
6fb5fa3c DB |
124 | /* Number of r0 life regions. */ |
125 | static int r0_life_regions; | |
126 | ||
58565a33 SKG |
127 | /* If true, skip cycles for Q -> R movement. */ |
128 | static int skip_cycles = 0; | |
129 | ||
50fe8924 | 130 | /* Cached value of can_issue_more. This is cached in sh_variable_issue hook |
58565a33 SKG |
131 | and returned from sh_reorder2. */ |
132 | static short cached_can_issue_more; | |
133 | ||
826159e5 KK |
134 | /* Unique number for UNSPEC_BBR pattern. */ |
135 | static unsigned int unspec_bbr_uid = 1; | |
136 | ||
bc45ade3 | 137 | /* Provides the class number of the smallest class containing |
16bea517 | 138 | reg number. */ |
fada1961 | 139 | enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] = |
bc45ade3 | 140 | { |
8e87e161 | 141 | R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, |
bc45ade3 SC |
142 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, |
143 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
144 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
fa5322fa AO |
145 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, |
146 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
147 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
148 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
149 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
150 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
151 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
152 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
153 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
154 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
155 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
156 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
1a95a963 JW |
157 | FP0_REGS,FP_REGS, FP_REGS, FP_REGS, |
158 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
159 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
160 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
fa5322fa AO |
161 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, |
162 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
163 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
164 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
165 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
166 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
167 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
168 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
169 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
170 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
171 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
172 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
173 | TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS, | |
174 | TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS, | |
225e4f43 R |
175 | DF_REGS, DF_REGS, DF_REGS, DF_REGS, |
176 | DF_REGS, DF_REGS, DF_REGS, DF_REGS, | |
fa5322fa AO |
177 | NO_REGS, GENERAL_REGS, PR_REGS, T_REGS, |
178 | MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS, | |
96a2347e | 179 | GENERAL_REGS, GENERAL_REGS, |
225e4f43 R |
180 | }; |
181 | ||
fa5322fa AO |
182 | char sh_register_names[FIRST_PSEUDO_REGISTER] \ |
183 | [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER; | |
184 | ||
185 | char sh_additional_register_names[ADDREGNAMES_SIZE] \ | |
186 | [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1] | |
187 | = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER; | |
bc45ade3 | 188 | |
225e4f43 R |
189 | int assembler_dialect; |
190 | ||
fe3ad572 SC |
191 | static bool shmedia_space_reserved_for_target_registers; |
192 | ||
6cb7eb41 | 193 | static void split_branches (rtx_insn *); |
cf277499 | 194 | static int branch_dest (rtx); |
7fa55ff6 | 195 | static void print_slot (rtx_sequence *); |
ef4bddc2 | 196 | static rtx_code_label *add_constant (rtx, machine_mode, rtx); |
6cb7eb41 DM |
197 | static void dump_table (rtx_insn *, rtx_insn *); |
198 | static bool broken_move (rtx_insn *); | |
199 | static bool mova_p (rtx_insn *); | |
200 | static rtx_insn *find_barrier (int, rtx_insn *, rtx_insn *); | |
e8a54173 | 201 | static bool noncall_uses_reg (rtx, rtx_insn *, rtx *); |
b32d5189 | 202 | static rtx_insn *gen_block_redirect (rtx_insn *, int, int); |
cf277499 | 203 | static void sh_reorg (void); |
e7a8f681 | 204 | static void sh_option_override (void); |
21d05694 | 205 | static void output_stack_adjust (int, rtx, int, HARD_REG_SET *, bool); |
cd459bf8 | 206 | static rtx_insn *frame_insn (rtx); |
cf277499 SB |
207 | static rtx push (int); |
208 | static void pop (int); | |
209 | static void push_regs (HARD_REG_SET *, int); | |
210 | static int calc_live_regs (HARD_REG_SET *); | |
cf277499 | 211 | static HOST_WIDE_INT rounded_frame_size (int); |
7a296495 | 212 | static bool sh_frame_pointer_required (void); |
cbb1e3d9 | 213 | static void sh_emit_mode_set (int, int, int, HARD_REG_SET); |
ac44248e DM |
214 | static int sh_mode_needed (int, rtx_insn *); |
215 | static int sh_mode_after (int, int, rtx_insn *); | |
06b90602 CB |
216 | static int sh_mode_entry (int); |
217 | static int sh_mode_exit (int); | |
218 | static int sh_mode_priority (int entity, int n); | |
106a52b7 | 219 | static bool sh_lra_p (void); |
06b90602 | 220 | |
cf277499 | 221 | static rtx mark_constant_pool_use (rtx); |
50fe8924 OE |
222 | static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, |
223 | int, bool *); | |
561642fa AP |
224 | static tree sh_handle_resbank_handler_attribute (tree *, tree, |
225 | tree, int, bool *); | |
226 | static tree sh2a_handle_function_vector_handler_attribute (tree *, tree, | |
227 | tree, int, bool *); | |
cf277499 SB |
228 | static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *); |
229 | static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *); | |
230 | static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *); | |
9e94b957 NF |
231 | static void sh_print_operand (FILE *, rtx, int); |
232 | static void sh_print_operand_address (FILE *, rtx); | |
233 | static bool sh_print_operand_punct_valid_p (unsigned char code); | |
ef875e12 | 234 | static bool sh_asm_output_addr_const_extra (FILE *file, rtx x); |
cf277499 SB |
235 | static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT); |
236 | static void sh_insert_attributes (tree, tree *); | |
8d932be3 | 237 | static const char *sh_check_pch_target_flags (int); |
ef4bddc2 | 238 | static int sh_register_move_cost (machine_mode, reg_class_t, reg_class_t); |
ac44248e | 239 | static int sh_adjust_cost (rtx_insn *, rtx, rtx_insn *, int); |
cf277499 | 240 | static int sh_issue_rate (void); |
ac44248e | 241 | static int sh_dfa_new_cycle (FILE *, int, rtx_insn *, int, int, int *sort_p); |
ef4bddc2 RS |
242 | static short find_set_regmode_weight (rtx, machine_mode); |
243 | static short find_insn_regmode_weight (rtx, machine_mode); | |
244 | static void find_regmode_weight (basic_block, machine_mode); | |
6fb5fa3c | 245 | static int find_r0_life_regions (basic_block); |
58565a33 SKG |
246 | static void sh_md_init_global (FILE *, int, int); |
247 | static void sh_md_finish_global (FILE *, int); | |
248 | static int rank_for_reorder (const void *, const void *); | |
ce1ce33a DM |
249 | static void swap_reorder (rtx_insn **, int); |
250 | static void ready_reorder (rtx_insn **, int); | |
ef4bddc2 | 251 | static bool high_pressure (machine_mode); |
ce1ce33a DM |
252 | static int sh_reorder (FILE *, int, rtx_insn **, int *, int); |
253 | static int sh_reorder2 (FILE *, int, rtx_insn **, int *, int); | |
58565a33 | 254 | static void sh_md_init (FILE *, int, int); |
ac44248e | 255 | static int sh_variable_issue (FILE *, int, rtx_insn *, int); |
f676971a | 256 | |
cf277499 SB |
257 | static bool sh_function_ok_for_sibcall (tree, tree); |
258 | ||
259 | static bool sh_cannot_modify_jumps_p (void); | |
cf6186e9 | 260 | static bool sh_can_follow_jump (const rtx_insn *, const rtx_insn *); |
a87cf97e | 261 | static reg_class_t sh_target_reg_class (void); |
fe3ad572 | 262 | static bool sh_optimize_target_register_callee_saved (bool); |
3101faab | 263 | static bool sh_ms_bitfield_layout_p (const_tree); |
cf277499 SB |
264 | |
265 | static void sh_init_builtins (void); | |
1cc24576 | 266 | static tree sh_builtin_decl (unsigned, bool); |
ef4bddc2 | 267 | static rtx sh_expand_builtin (tree, rtx, rtx, machine_mode, int); |
50fe8924 OE |
268 | static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
269 | HOST_WIDE_INT, tree); | |
cf277499 | 270 | static void sh_file_start (void); |
aaf701c5 | 271 | static bool flow_dependent_p (rtx, rtx); |
7bc980e1 | 272 | static void flow_dependent_p_1 (rtx, const_rtx, void *); |
cf277499 | 273 | static int shiftcosts (rtx); |
6ff9d294 | 274 | static int and_xor_ior_costs (rtx, int); |
cf277499 SB |
275 | static int addsubcosts (rtx); |
276 | static int multcosts (rtx); | |
277 | static bool unspec_caller_rtx_p (rtx); | |
ac44248e | 278 | static bool sh_cannot_copy_insn_p (rtx_insn *); |
e548c9df | 279 | static bool sh_rtx_costs (rtx, machine_mode, int, int, int *, bool); |
ef4bddc2 | 280 | static int sh_address_cost (rtx, machine_mode, addr_space_t, bool); |
b48f503c KK |
281 | static int sh_pr_n_sets (void); |
282 | static rtx sh_allocate_initial_value (rtx); | |
486b10aa AS |
283 | static reg_class_t sh_preferred_reload_class (rtx, reg_class_t); |
284 | static reg_class_t sh_secondary_reload (bool, rtx, reg_class_t, | |
ef4bddc2 | 285 | machine_mode, |
486b10aa | 286 | struct secondary_reload_info *); |
ef4bddc2 RS |
287 | static bool sh_legitimate_address_p (machine_mode, rtx, bool); |
288 | static rtx sh_legitimize_address (rtx, rtx, machine_mode); | |
90833f7f | 289 | static rtx sh_delegitimize_address (rtx); |
d6220b11 | 290 | static bool sh_cannot_substitute_mem_equiv_p (rtx); |
14133a4d | 291 | static bool sh_legitimize_address_displacement (rtx *, rtx *, machine_mode); |
fe3ad572 SC |
292 | static int shmedia_target_regs_stack_space (HARD_REG_SET *); |
293 | static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *); | |
294 | static int shmedia_target_regs_stack_adjust (HARD_REG_SET *); | |
fada1961 R |
295 | static int scavenge_reg (HARD_REG_SET *s); |
296 | struct save_schedule_s; | |
297 | static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *, | |
298 | struct save_schedule_s *, int); | |
61f71b34 | 299 | |
cf277499 | 300 | static rtx sh_struct_value_rtx (tree, int); |
d64728cf | 301 | static rtx sh_function_value (const_tree, const_tree, bool); |
e7a8f681 | 302 | static bool sh_function_value_regno_p (const unsigned int); |
ef4bddc2 | 303 | static rtx sh_libcall_value (machine_mode, const_rtx); |
586de218 | 304 | static bool sh_return_in_memory (const_tree, const_tree); |
cf277499 | 305 | static rtx sh_builtin_saveregs (void); |
ef4bddc2 | 306 | static void sh_setup_incoming_varargs (cumulative_args_t, machine_mode, |
50fe8924 | 307 | tree, int *, int); |
d5cc9181 JR |
308 | static bool sh_strict_argument_naming (cumulative_args_t); |
309 | static bool sh_pretend_outgoing_varargs_named (cumulative_args_t); | |
801881b0 | 310 | static void sh_atomic_assign_expand_fenv (tree *, tree *, tree *); |
c35d187f | 311 | static tree sh_build_builtin_va_list (void); |
d7bd8aeb | 312 | static void sh_va_start (tree, rtx); |
726a989a | 313 | static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *); |
d64728cf | 314 | static bool sh_promote_prototypes (const_tree); |
ef4bddc2 RS |
315 | static machine_mode sh_promote_function_mode (const_tree type, |
316 | machine_mode, | |
d055ce45 KK |
317 | int *punsignedp, |
318 | const_tree funtype, | |
6e957ac8 | 319 | int for_return); |
ef4bddc2 | 320 | static bool sh_pass_by_reference (cumulative_args_t, machine_mode, |
586de218 | 321 | const_tree, bool); |
ef4bddc2 | 322 | static bool sh_callee_copies (cumulative_args_t, machine_mode, |
586de218 | 323 | const_tree, bool); |
ef4bddc2 | 324 | static int sh_arg_partial_bytes (cumulative_args_t, machine_mode, |
78a52f11 | 325 | tree, bool); |
ef4bddc2 | 326 | static void sh_function_arg_advance (cumulative_args_t, machine_mode, |
b64336b8 | 327 | const_tree, bool); |
ef4bddc2 | 328 | static rtx sh_function_arg (cumulative_args_t, machine_mode, |
b64336b8 | 329 | const_tree, bool); |
ef4bddc2 | 330 | static bool sh_scalar_mode_supported_p (machine_mode); |
3101faab | 331 | static int sh_dwarf_calling_convention (const_tree); |
561642fa | 332 | static void sh_encode_section_info (tree, rtx, int); |
aaf701c5 | 333 | static bool sh2a_function_vector_p (tree); |
994322ef RH |
334 | static void sh_trampoline_init (rtx, tree, rtx); |
335 | static rtx sh_trampoline_adjust_address (rtx); | |
5efd84c5 | 336 | static void sh_conditional_register_usage (void); |
ef4bddc2 RS |
337 | static bool sh_legitimate_constant_p (machine_mode, rtx); |
338 | static int mov_insn_size (machine_mode, bool); | |
339 | static int mov_insn_alignment_mask (machine_mode, bool); | |
445d7826 | 340 | static bool sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT, |
ae59bd31 JG |
341 | unsigned int, |
342 | enum by_pieces_operation, | |
343 | bool); | |
b32d5189 | 344 | static bool sequence_insn_p (rtx_insn *); |
c354951b AK |
345 | static void sh_canonicalize_comparison (int *, rtx *, rtx *, bool); |
346 | static void sh_canonicalize_comparison (enum rtx_code&, rtx&, rtx&, | |
ef4bddc2 | 347 | machine_mode, bool); |
841dbf80 OE |
348 | static bool sh_legitimate_combined_insn (rtx_insn* insn); |
349 | ||
5d30dc5b | 350 | static bool sh_fixed_condition_code_regs (unsigned int* p1, unsigned int* p2); |
dab37c68 RH |
351 | |
352 | static void sh_init_sync_libfuncs (void) ATTRIBUTE_UNUSED; | |
5a82ecd9 ILT |
353 | \f |
354 | static const struct attribute_spec sh_attribute_table[] = | |
355 | { | |
62d784f7 KT |
356 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
357 | affects_type_identity } */ | |
358 | { "interrupt_handler", 0, 0, true, false, false, | |
359 | sh_handle_interrupt_handler_attribute, false }, | |
360 | { "sp_switch", 1, 1, true, false, false, | |
361 | sh_handle_sp_switch_attribute, false }, | |
362 | { "trap_exit", 1, 1, true, false, false, | |
363 | sh_handle_trap_exit_attribute, false }, | |
364 | { "renesas", 0, 0, false, true, false, | |
365 | sh_handle_renesas_attribute, false }, | |
366 | { "trapa_handler", 0, 0, true, false, false, | |
367 | sh_handle_interrupt_handler_attribute, false }, | |
368 | { "nosave_low_regs", 0, 0, true, false, false, | |
369 | sh_handle_interrupt_handler_attribute, false }, | |
370 | { "resbank", 0, 0, true, false, false, | |
371 | sh_handle_resbank_handler_attribute, false }, | |
372 | { "function_vector", 1, 1, true, false, false, | |
373 | sh2a_handle_function_vector_handler_attribute, false }, | |
62d784f7 | 374 | { NULL, 0, 0, false, false, false, NULL, false } |
5a82ecd9 | 375 | }; |
672a6f42 NB |
376 | \f |
377 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
378 | #undef TARGET_ATTRIBUTE_TABLE |
379 | #define TARGET_ATTRIBUTE_TABLE sh_attribute_table | |
672a6f42 | 380 | |
301d03af RS |
381 | /* The next two are used for debug info when compiling with -gdwarf. */ |
382 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
383 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t" | |
384 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
385 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t" | |
386 | ||
c5387660 | 387 | /* These are NULLed out on non-SH5 in TARGET_OPTION_OVERRIDE. */ |
fa5322fa AO |
388 | #undef TARGET_ASM_UNALIGNED_DI_OP |
389 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t" | |
390 | #undef TARGET_ASM_ALIGNED_DI_OP | |
391 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
392 | ||
e7a8f681 N |
393 | #undef TARGET_OPTION_OVERRIDE |
394 | #define TARGET_OPTION_OVERRIDE sh_option_override | |
395 | ||
9e94b957 NF |
396 | #undef TARGET_PRINT_OPERAND |
397 | #define TARGET_PRINT_OPERAND sh_print_operand | |
398 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
399 | #define TARGET_PRINT_OPERAND_ADDRESS sh_print_operand_address | |
400 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
401 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p | |
ef875e12 AS |
402 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
403 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra | |
404 | ||
08c148a8 NB |
405 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
406 | #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue | |
407 | ||
1aa03f38 R |
408 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
409 | #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk | |
410 | ||
411 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
50fe8924 OE |
412 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \ |
413 | hook_bool_const_tree_hwi_hwi_const_tree_true | |
1aa03f38 | 414 | |
1bc7c5b6 ZW |
415 | #undef TARGET_ASM_FILE_START |
416 | #define TARGET_ASM_FILE_START sh_file_start | |
417 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
418 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
419 | ||
e7a8f681 N |
420 | #undef TARGET_REGISTER_MOVE_COST |
421 | #define TARGET_REGISTER_MOVE_COST sh_register_move_cost | |
422 | ||
12a68f1f JM |
423 | #undef TARGET_INSERT_ATTRIBUTES |
424 | #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes | |
425 | ||
c237e94a ZW |
426 | #undef TARGET_SCHED_ADJUST_COST |
427 | #define TARGET_SCHED_ADJUST_COST sh_adjust_cost | |
428 | ||
fae15c93 VM |
429 | #undef TARGET_SCHED_ISSUE_RATE |
430 | #define TARGET_SCHED_ISSUE_RATE sh_issue_rate | |
431 | ||
58565a33 SKG |
432 | /* The next 5 hooks have been implemented for reenabling sched1. With the |
433 | help of these macros we are limiting the movement of insns in sched1 to | |
f676971a | 434 | reduce the register pressure. The overall idea is to keep count of SImode |
58565a33 SKG |
435 | and SFmode regs required by already scheduled insns. When these counts |
436 | cross some threshold values; give priority to insns that free registers. | |
437 | The insn that frees registers is most likely to be the insn with lowest | |
f676971a | 438 | LUID (original insn order); but such an insn might be there in the stalled |
58565a33 | 439 | queue (Q) instead of the ready queue (R). To solve this, we skip cycles |
073a8998 | 440 | up to a max of 8 cycles so that such insns may move from Q -> R. |
58565a33 SKG |
441 | |
442 | The description of the hooks are as below: | |
443 | ||
444 | TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic | |
445 | scheduler; it is called inside the sched_init function just after | |
446 | find_insn_reg_weights function call. It is used to calculate the SImode | |
1ae58c30 | 447 | and SFmode weights of insns of basic blocks; much similar to what |
f676971a | 448 | find_insn_reg_weights does. |
58565a33 SKG |
449 | TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook. |
450 | ||
451 | TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is | |
452 | indicated by TARGET_SCHED_REORDER2; doing this may move insns from | |
453 | (Q)->(R). | |
454 | ||
455 | TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is | |
456 | high; reorder the ready queue so that the insn with lowest LUID will be | |
457 | issued next. | |
458 | ||
459 | TARGET_SCHED_REORDER2: If the register pressure is high, indicate to | |
460 | TARGET_SCHED_DFA_NEW_CYCLE to skip cycles. | |
461 | ||
462 | TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it | |
463 | can be returned from TARGET_SCHED_REORDER2. | |
464 | ||
465 | TARGET_SCHED_INIT: Reset the register pressure counting variables. */ | |
466 | ||
467 | #undef TARGET_SCHED_DFA_NEW_CYCLE | |
468 | #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle | |
469 | ||
470 | #undef TARGET_SCHED_INIT_GLOBAL | |
471 | #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global | |
472 | ||
473 | #undef TARGET_SCHED_FINISH_GLOBAL | |
474 | #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global | |
475 | ||
476 | #undef TARGET_SCHED_VARIABLE_ISSUE | |
477 | #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue | |
478 | ||
479 | #undef TARGET_SCHED_REORDER | |
480 | #define TARGET_SCHED_REORDER sh_reorder | |
481 | ||
482 | #undef TARGET_SCHED_REORDER2 | |
483 | #define TARGET_SCHED_REORDER2 sh_reorder2 | |
484 | ||
485 | #undef TARGET_SCHED_INIT | |
486 | #define TARGET_SCHED_INIT sh_md_init | |
487 | ||
90833f7f KK |
488 | #undef TARGET_DELEGITIMIZE_ADDRESS |
489 | #define TARGET_DELEGITIMIZE_ADDRESS sh_delegitimize_address | |
490 | ||
506d7b68 PB |
491 | #undef TARGET_LEGITIMIZE_ADDRESS |
492 | #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address | |
493 | ||
fa5322fa AO |
494 | #undef TARGET_CANNOT_MODIFY_JUMPS_P |
495 | #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p | |
cf6186e9 JR |
496 | #undef TARGET_CAN_FOLLOW_JUMP |
497 | #define TARGET_CAN_FOLLOW_JUMP sh_can_follow_jump | |
fe3ad572 SC |
498 | #undef TARGET_BRANCH_TARGET_REGISTER_CLASS |
499 | #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class | |
500 | #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED | |
501 | #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \ | |
50fe8924 | 502 | sh_optimize_target_register_callee_saved |
fa5322fa AO |
503 | |
504 | #undef TARGET_MS_BITFIELD_LAYOUT_P | |
505 | #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p | |
506 | ||
c1b92d09 R |
507 | #undef TARGET_INIT_BUILTINS |
508 | #define TARGET_INIT_BUILTINS sh_init_builtins | |
1cc24576 KK |
509 | #undef TARGET_BUILTIN_DECL |
510 | #define TARGET_BUILTIN_DECL sh_builtin_decl | |
c1b92d09 R |
511 | #undef TARGET_EXPAND_BUILTIN |
512 | #define TARGET_EXPAND_BUILTIN sh_expand_builtin | |
513 | ||
4977bab6 ZW |
514 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
515 | #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall | |
516 | ||
9f3a9a08 KK |
517 | #undef TARGET_CANNOT_COPY_INSN_P |
518 | #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p | |
3c50106f RH |
519 | #undef TARGET_RTX_COSTS |
520 | #define TARGET_RTX_COSTS sh_rtx_costs | |
dcefdf67 RH |
521 | #undef TARGET_ADDRESS_COST |
522 | #define TARGET_ADDRESS_COST sh_address_cost | |
b48f503c KK |
523 | #undef TARGET_ALLOCATE_INITIAL_VALUE |
524 | #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value | |
3c50106f | 525 | |
18dbd950 RS |
526 | #undef TARGET_MACHINE_DEPENDENT_REORG |
527 | #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg | |
528 | ||
63a9de54 CB |
529 | #undef TARGET_DWARF_REGISTER_SPAN |
530 | #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span | |
531 | ||
463f02cd KK |
532 | #ifdef HAVE_AS_TLS |
533 | #undef TARGET_HAVE_TLS | |
534 | #define TARGET_HAVE_TLS true | |
535 | #endif | |
536 | ||
61f71b34 DD |
537 | #undef TARGET_PROMOTE_PROTOTYPES |
538 | #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes | |
d055ce45 KK |
539 | #undef TARGET_PROMOTE_FUNCTION_MODE |
540 | #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode | |
61f71b34 | 541 | |
d64728cf AS |
542 | #undef TARGET_FUNCTION_VALUE |
543 | #define TARGET_FUNCTION_VALUE sh_function_value | |
e7a8f681 N |
544 | #undef TARGET_FUNCTION_VALUE_REGNO_P |
545 | #define TARGET_FUNCTION_VALUE_REGNO_P sh_function_value_regno_p | |
d64728cf AS |
546 | #undef TARGET_LIBCALL_VALUE |
547 | #define TARGET_LIBCALL_VALUE sh_libcall_value | |
61f71b34 DD |
548 | #undef TARGET_STRUCT_VALUE_RTX |
549 | #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx | |
550 | #undef TARGET_RETURN_IN_MEMORY | |
551 | #define TARGET_RETURN_IN_MEMORY sh_return_in_memory | |
552 | ||
553 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
554 | #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs | |
555 | #undef TARGET_SETUP_INCOMING_VARARGS | |
556 | #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs | |
557 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
558 | #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming | |
559 | #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED | |
560 | #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named | |
fe984136 RH |
561 | #undef TARGET_MUST_PASS_IN_STACK |
562 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
8cd5a4e0 RH |
563 | #undef TARGET_PASS_BY_REFERENCE |
564 | #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference | |
6cdd5672 RH |
565 | #undef TARGET_CALLEE_COPIES |
566 | #define TARGET_CALLEE_COPIES sh_callee_copies | |
78a52f11 RH |
567 | #undef TARGET_ARG_PARTIAL_BYTES |
568 | #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes | |
b64336b8 NF |
569 | #undef TARGET_FUNCTION_ARG |
570 | #define TARGET_FUNCTION_ARG sh_function_arg | |
571 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
572 | #define TARGET_FUNCTION_ARG_ADVANCE sh_function_arg_advance | |
61f71b34 | 573 | |
801881b0 KK |
574 | #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV |
575 | #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sh_atomic_assign_expand_fenv | |
576 | ||
c35d187f RH |
577 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
578 | #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list | |
d7bd8aeb JJ |
579 | #undef TARGET_EXPAND_BUILTIN_VA_START |
580 | #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start | |
5fac2ed2 RH |
581 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
582 | #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr | |
c35d187f | 583 | |
b0fbea13 KK |
584 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
585 | #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p | |
f676971a EC |
586 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
587 | #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p | |
588 | ||
8d932be3 RS |
589 | #undef TARGET_CHECK_PCH_TARGET_FLAGS |
590 | #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags | |
bcc8cc82 | 591 | |
a1c496cb EC |
592 | #undef TARGET_DWARF_CALLING_CONVENTION |
593 | #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention | |
594 | ||
7a296495 CB |
595 | #undef TARGET_FRAME_POINTER_REQUIRED |
596 | #define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required | |
597 | ||
06b90602 CB |
598 | #undef TARGET_MODE_EMIT |
599 | #define TARGET_MODE_EMIT sh_emit_mode_set | |
600 | ||
601 | #undef TARGET_MODE_NEEDED | |
602 | #define TARGET_MODE_NEEDED sh_mode_needed | |
603 | ||
604 | #undef TARGET_MODE_AFTER | |
605 | #define TARGET_MODE_AFTER sh_mode_after | |
606 | ||
607 | #undef TARGET_MODE_ENTRY | |
608 | #define TARGET_MODE_ENTRY sh_mode_entry | |
609 | ||
610 | #undef TARGET_MODE_EXIT | |
611 | #define TARGET_MODE_EXIT sh_mode_exit | |
612 | ||
613 | #undef TARGET_MODE_PRIORITY | |
614 | #define TARGET_MODE_PRIORITY sh_mode_priority | |
615 | ||
58565a33 | 616 | /* Return regmode weight for insn. */ |
23d0939b OE |
617 | #define INSN_REGMODE_WEIGHT(INSN, MODE)\ |
618 | regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)] | |
58565a33 SKG |
619 | |
620 | /* Return current register pressure for regmode. */ | |
23d0939b OE |
621 | #define CURR_REGMODE_PRESSURE(MODE)\ |
622 | curr_regmode_pressure[((MODE) == SImode) ? 0 : 1] | |
58565a33 | 623 | |
561642fa AP |
624 | #undef TARGET_ENCODE_SECTION_INFO |
625 | #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info | |
626 | ||
106a52b7 KK |
627 | #undef TARGET_LRA_P |
628 | #define TARGET_LRA_P sh_lra_p | |
629 | ||
8a99f6f9 R |
630 | #undef TARGET_SECONDARY_RELOAD |
631 | #define TARGET_SECONDARY_RELOAD sh_secondary_reload | |
632 | ||
486b10aa AS |
633 | #undef TARGET_PREFERRED_RELOAD_CLASS |
634 | #define TARGET_PREFERRED_RELOAD_CLASS sh_preferred_reload_class | |
635 | ||
5efd84c5 NF |
636 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
637 | #define TARGET_CONDITIONAL_REGISTER_USAGE sh_conditional_register_usage | |
638 | ||
1bb99877 KK |
639 | #undef TARGET_LEGITIMATE_ADDRESS_P |
640 | #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p | |
641 | ||
d6220b11 KK |
642 | #undef TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P |
643 | #define TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P sh_cannot_substitute_mem_equiv_p | |
644 | ||
14133a4d KK |
645 | #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT |
646 | #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \ | |
647 | sh_legitimize_address_displacement | |
648 | ||
994322ef RH |
649 | #undef TARGET_TRAMPOLINE_INIT |
650 | #define TARGET_TRAMPOLINE_INIT sh_trampoline_init | |
651 | #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS | |
652 | #define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address | |
653 | ||
1a627b35 RS |
654 | #undef TARGET_LEGITIMATE_CONSTANT_P |
655 | #define TARGET_LEGITIMATE_CONSTANT_P sh_legitimate_constant_p | |
656 | ||
c354951b AK |
657 | #undef TARGET_CANONICALIZE_COMPARISON |
658 | #define TARGET_CANONICALIZE_COMPARISON sh_canonicalize_comparison | |
659 | ||
841dbf80 OE |
660 | #undef TARGET_LEGITIMATE_COMBINED_INSN |
661 | #define TARGET_LEGITIMATE_COMBINED_INSN sh_legitimate_combined_insn | |
662 | ||
5d30dc5b OE |
663 | #undef TARGET_FIXED_CONDITION_CODE_REGS |
664 | #define TARGET_FIXED_CONDITION_CODE_REGS sh_fixed_condition_code_regs | |
665 | ||
ae59bd31 JG |
666 | #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P |
667 | #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \ | |
668 | sh_use_by_pieces_infrastructure_p | |
669 | ||
561642fa | 670 | /* Machine-specific symbol_ref flags. */ |
50fe8924 | 671 | #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0) |
561642fa | 672 | |
95a6dda5 RH |
673 | /* The tas.b instruction sets the 7th bit in the byte, i.e. 0x80. This value |
674 | is used by optabs.c atomic op expansion code as well as in sync.md. */ | |
675 | #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL | |
676 | #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80 | |
677 | ||
f6897b10 | 678 | struct gcc_target targetm = TARGET_INITIALIZER; |
b9654711 | 679 | \f |
7bd76b9c OE |
680 | |
681 | /* Information on the currently selected atomic model. | |
682 | This is initialized in sh_option_override. */ | |
683 | static sh_atomic_model selected_atomic_model_; | |
684 | ||
685 | const sh_atomic_model& | |
686 | selected_atomic_model (void) | |
687 | { | |
688 | return selected_atomic_model_; | |
689 | } | |
690 | ||
691 | static sh_atomic_model | |
692 | parse_validate_atomic_model_option (const char* str) | |
693 | { | |
694 | const char* model_names[sh_atomic_model::num_models]; | |
695 | model_names[sh_atomic_model::none] = "none"; | |
696 | model_names[sh_atomic_model::soft_gusa] = "soft-gusa"; | |
697 | model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; | |
698 | model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; | |
699 | model_names[sh_atomic_model::soft_imask] = "soft-imask"; | |
700 | ||
9597375a OE |
701 | const char* model_cdef_names[sh_atomic_model::num_models]; |
702 | model_cdef_names[sh_atomic_model::none] = "NONE"; | |
703 | model_cdef_names[sh_atomic_model::soft_gusa] = "SOFT_GUSA"; | |
704 | model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; | |
705 | model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; | |
706 | model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; | |
707 | ||
7bd76b9c OE |
708 | sh_atomic_model ret; |
709 | ret.type = sh_atomic_model::none; | |
9597375a OE |
710 | ret.name = model_names[sh_atomic_model::none]; |
711 | ret.cdef_name = model_cdef_names[sh_atomic_model::none]; | |
7bd76b9c OE |
712 | ret.strict = false; |
713 | ret.tcb_gbr_offset = -1; | |
714 | ||
715 | /* Handle empty string as 'none'. */ | |
716 | if (str == NULL || *str == '\0') | |
717 | return ret; | |
718 | ||
719 | #define err_ret(...) do { error (__VA_ARGS__); return ret; } while (0) | |
720 | ||
721 | std::vector<std::string> tokens; | |
722 | for (std::stringstream ss (str); ss.good (); ) | |
723 | { | |
724 | tokens.push_back (std::string ()); | |
725 | std::getline (ss, tokens.back (), ','); | |
726 | } | |
727 | ||
728 | if (tokens.empty ()) | |
729 | err_ret ("invalid atomic model option"); | |
730 | ||
731 | /* The first token must be the atomic model name. */ | |
732 | { | |
733 | for (size_t i = 0; i < sh_atomic_model::num_models; ++i) | |
734 | if (tokens.front () == model_names[i]) | |
735 | { | |
736 | ret.type = (sh_atomic_model::enum_type)i; | |
9597375a OE |
737 | ret.name = model_names[i]; |
738 | ret.cdef_name = model_cdef_names[i]; | |
7bd76b9c OE |
739 | goto got_mode_name; |
740 | } | |
741 | ||
742 | err_ret ("invalid atomic model name \"%s\"", tokens.front ().c_str ()); | |
743 | got_mode_name:; | |
744 | } | |
745 | ||
746 | /* Go through the remaining tokens. */ | |
747 | for (size_t i = 1; i < tokens.size (); ++i) | |
748 | { | |
749 | if (tokens[i] == "strict") | |
750 | ret.strict = true; | |
751 | else if (tokens[i].find ("gbr-offset=") == 0) | |
752 | { | |
753 | std::string offset_str = tokens[i].substr (strlen ("gbr-offset=")); | |
754 | ret.tcb_gbr_offset = integral_argument (offset_str.c_str ()); | |
755 | if (offset_str.empty () || ret.tcb_gbr_offset == -1) | |
756 | err_ret ("could not parse gbr-offset value \"%s\" in atomic model " | |
757 | "option", offset_str.c_str ()); | |
758 | } | |
759 | else | |
760 | err_ret ("unknown parameter \"%s\" in atomic model option", | |
50fe8924 | 761 | tokens[i].c_str ()); |
7bd76b9c OE |
762 | } |
763 | ||
764 | /* Check that the selection makes sense. */ | |
765 | if (TARGET_SHMEDIA && ret.type != sh_atomic_model::none) | |
766 | err_ret ("atomic operations are not supported on SHmedia"); | |
767 | ||
768 | if (ret.type == sh_atomic_model::soft_gusa && !TARGET_SH3) | |
769 | err_ret ("atomic model %s is only available on SH3 and SH4 targets", | |
9597375a | 770 | ret.name); |
7bd76b9c OE |
771 | |
772 | if (ret.type == sh_atomic_model::hard_llcs && !TARGET_SH4A) | |
9597375a | 773 | err_ret ("atomic model %s is only available on SH4A targets", ret.name); |
7bd76b9c OE |
774 | |
775 | if (ret.type == sh_atomic_model::soft_tcb && ret.tcb_gbr_offset == -1) | |
9597375a | 776 | err_ret ("atomic model %s requires gbr-offset parameter", ret.name); |
7bd76b9c OE |
777 | |
778 | if (ret.type == sh_atomic_model::soft_tcb | |
779 | && (ret.tcb_gbr_offset < 0 || ret.tcb_gbr_offset > 1020 | |
780 | || (ret.tcb_gbr_offset & 3) != 0)) | |
781 | err_ret ("invalid gbr-offset value \"%d\" for atomic model %s; it must be " | |
782 | "a multiple of 4 in the range 0-1020", ret.tcb_gbr_offset, | |
9597375a | 783 | ret.name); |
7bd76b9c OE |
784 | |
785 | if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) | |
9597375a | 786 | err_ret ("cannot use atomic model %s in user mode", ret.name); |
7bd76b9c OE |
787 | |
788 | return ret; | |
789 | ||
790 | #undef err_ret | |
791 | } | |
792 | ||
5d30dc5b OE |
793 | /* Register SH specific RTL passes. */ |
794 | extern opt_pass* make_pass_sh_treg_combine (gcc::context* ctx, bool split_insns, | |
ac973375 OE |
795 | const char* name); |
796 | extern opt_pass* make_pass_sh_optimize_sett_clrt (gcc::context* ctx, | |
797 | const char* name); | |
5d30dc5b OE |
798 | static void |
799 | register_sh_passes (void) | |
800 | { | |
801 | if (!TARGET_SH1) | |
802 | return; | |
803 | ||
804 | /* Running the sh_treg_combine pass after ce1 generates better code when | |
805 | comparisons are combined and reg-reg moves are introduced, because | |
806 | reg-reg moves will be eliminated afterwards. However, there are quite | |
807 | some cases where combine will be unable to fold comparison related insns, | |
808 | thus for now don't do it. | |
809 | register_pass (make_pass_sh_treg_combine (g, false, "sh_treg_combine1"), | |
810 | PASS_POS_INSERT_AFTER, "ce1", 1); | |
811 | */ | |
812 | ||
813 | /* Run sh_treg_combine pass after combine but before register allocation. */ | |
814 | register_pass (make_pass_sh_treg_combine (g, true, "sh_treg_combine2"), | |
815 | PASS_POS_INSERT_AFTER, "split1", 1); | |
816 | ||
817 | /* Run sh_treg_combine pass after register allocation and basic block | |
818 | reordering as this sometimes creates new opportunities. */ | |
819 | register_pass (make_pass_sh_treg_combine (g, true, "sh_treg_combine3"), | |
820 | PASS_POS_INSERT_AFTER, "split4", 1); | |
ac973375 OE |
821 | |
822 | /* Optimize sett and clrt insns, by e.g. removing them if the T bit value | |
823 | is known after a conditional branch. | |
824 | This must be done after basic blocks and branch conditions have | |
825 | stabilized and won't be changed by further passes. */ | |
826 | register_pass (make_pass_sh_optimize_sett_clrt (g, "sh_optimize_sett_clrt"), | |
827 | PASS_POS_INSERT_BEFORE, "sched2", 1); | |
5d30dc5b OE |
828 | } |
829 | ||
e7a8f681 N |
830 | /* Implement TARGET_OPTION_OVERRIDE macro. Validate and override |
831 | various options, and do some machine dependent initialization. */ | |
832 | static void | |
833 | sh_option_override (void) | |
bd9a3465 KK |
834 | { |
835 | int regno; | |
836 | ||
837 | SUBTARGET_OVERRIDE_OPTIONS; | |
3020190e JM |
838 | if (optimize > 1 && !optimize_size) |
839 | target_flags |= MASK_SAVE_ALL_TARGET_REGS; | |
7337ddf4 OE |
840 | |
841 | /* Set default values of TARGET_CBRANCHDI4 and TARGET_CMPEQDI_T. */ | |
842 | TARGET_CBRANCHDI4 = 1; | |
843 | TARGET_CMPEQDI_T = 0; | |
844 | ||
bd9a3465 KK |
845 | sh_cpu = PROCESSOR_SH1; |
846 | assembler_dialect = 0; | |
847 | if (TARGET_SH2) | |
848 | sh_cpu = PROCESSOR_SH2; | |
849 | if (TARGET_SH2E) | |
850 | sh_cpu = PROCESSOR_SH2E; | |
851 | if (TARGET_SH2A) | |
7a61cf6f | 852 | sh_cpu = PROCESSOR_SH2A; |
bd9a3465 KK |
853 | if (TARGET_SH3) |
854 | sh_cpu = PROCESSOR_SH3; | |
855 | if (TARGET_SH3E) | |
856 | sh_cpu = PROCESSOR_SH3E; | |
857 | if (TARGET_SH4) | |
858 | { | |
859 | assembler_dialect = 1; | |
860 | sh_cpu = PROCESSOR_SH4; | |
861 | } | |
f3ca7111 | 862 | if (TARGET_SH4A) |
bd9a3465 KK |
863 | { |
864 | assembler_dialect = 1; | |
865 | sh_cpu = PROCESSOR_SH4A; | |
866 | } | |
867 | if (TARGET_SH5) | |
868 | { | |
869 | sh_cpu = PROCESSOR_SH5; | |
870 | target_flags |= MASK_ALIGN_DOUBLE; | |
871 | if (TARGET_SHMEDIA_FPU) | |
872 | target_flags |= MASK_FMOVD; | |
873 | if (TARGET_SHMEDIA) | |
874 | { | |
875 | /* There are no delay slots on SHmedia. */ | |
876 | flag_delayed_branch = 0; | |
877 | /* Relaxation isn't yet supported for SHmedia */ | |
878 | target_flags &= ~MASK_RELAX; | |
879 | /* After reload, if conversion does little good but can cause | |
880 | ICEs: | |
881 | - find_if_block doesn't do anything for SH because we don't | |
882 | have conditional execution patterns. (We use conditional | |
883 | move patterns, which are handled differently, and only | |
884 | before reload). | |
885 | - find_cond_trap doesn't do anything for the SH because we | |
886 | don't have conditional traps. | |
887 | - find_if_case_1 uses redirect_edge_and_branch_force in | |
888 | the only path that does an optimization, and this causes | |
889 | an ICE when branch targets are in registers. | |
890 | - find_if_case_2 doesn't do anything for the SHmedia after | |
891 | reload except when it can redirect a tablejump - and | |
892 | that's rather rare. */ | |
893 | flag_if_conversion2 = 0; | |
894 | if (! strcmp (sh_div_str, "call")) | |
895 | sh_div_strategy = SH_DIV_CALL; | |
896 | else if (! strcmp (sh_div_str, "call2")) | |
897 | sh_div_strategy = SH_DIV_CALL2; | |
898 | if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) | |
899 | sh_div_strategy = SH_DIV_FP; | |
900 | else if (! strcmp (sh_div_str, "inv")) | |
901 | sh_div_strategy = SH_DIV_INV; | |
902 | else if (! strcmp (sh_div_str, "inv:minlat")) | |
903 | sh_div_strategy = SH_DIV_INV_MINLAT; | |
904 | else if (! strcmp (sh_div_str, "inv20u")) | |
905 | sh_div_strategy = SH_DIV_INV20U; | |
906 | else if (! strcmp (sh_div_str, "inv20l")) | |
907 | sh_div_strategy = SH_DIV_INV20L; | |
908 | else if (! strcmp (sh_div_str, "inv:call2")) | |
909 | sh_div_strategy = SH_DIV_INV_CALL2; | |
910 | else if (! strcmp (sh_div_str, "inv:call")) | |
911 | sh_div_strategy = SH_DIV_INV_CALL; | |
912 | else if (! strcmp (sh_div_str, "inv:fp")) | |
913 | { | |
914 | if (TARGET_FPU_ANY) | |
915 | sh_div_strategy = SH_DIV_INV_FP; | |
916 | else | |
917 | sh_div_strategy = SH_DIV_INV; | |
918 | } | |
919 | TARGET_CBRANCHDI4 = 0; | |
920 | /* Assembler CFI isn't yet fully supported for SHmedia. */ | |
921 | flag_dwarf2_cfi_asm = 0; | |
922 | } | |
923 | } | |
924 | else | |
925 | { | |
926 | /* Only the sh64-elf assembler fully supports .quad properly. */ | |
927 | targetm.asm_out.aligned_op.di = NULL; | |
928 | targetm.asm_out.unaligned_op.di = NULL; | |
929 | } | |
37c5f877 OE |
930 | |
931 | /* User/priviledged mode is supported only on SH3*, SH4* and SH5*. | |
932 | Disable it for everything else. */ | |
933 | if (! (TARGET_SH3 || TARGET_SH5) && TARGET_USERMODE) | |
934 | TARGET_USERMODE = false; | |
935 | ||
bd9a3465 KK |
936 | if (TARGET_SH1) |
937 | { | |
938 | if (! strcmp (sh_div_str, "call-div1")) | |
939 | sh_div_strategy = SH_DIV_CALL_DIV1; | |
940 | else if (! strcmp (sh_div_str, "call-fp") | |
decc676e | 941 | && (TARGET_FPU_DOUBLE || TARGET_FPU_SINGLE_ONLY |
bd9a3465 KK |
942 | || (TARGET_SHCOMPACT && TARGET_FPU_ANY))) |
943 | sh_div_strategy = SH_DIV_CALL_FP; | |
8f6d1c86 | 944 | else if (! strcmp (sh_div_str, "call-table") && TARGET_DYNSHIFT) |
bd9a3465 KK |
945 | sh_div_strategy = SH_DIV_CALL_TABLE; |
946 | else | |
947 | /* Pick one that makes most sense for the target in general. | |
948 | It is not much good to use different functions depending | |
949 | on -Os, since then we'll end up with two different functions | |
950 | when some of the code is compiled for size, and some for | |
951 | speed. */ | |
952 | ||
953 | /* SH4 tends to emphasize speed. */ | |
954 | if (TARGET_HARD_SH4) | |
955 | sh_div_strategy = SH_DIV_CALL_TABLE; | |
956 | /* These have their own way of doing things. */ | |
957 | else if (TARGET_SH2A) | |
958 | sh_div_strategy = SH_DIV_INTRINSIC; | |
959 | /* ??? Should we use the integer SHmedia function instead? */ | |
960 | else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) | |
961 | sh_div_strategy = SH_DIV_CALL_FP; | |
50fe8924 | 962 | /* SH1 .. SH3 cores often go into small-footprint systems, so |
bd9a3465 | 963 | default to the smallest implementation available. */ |
bd9a3465 KK |
964 | else |
965 | sh_div_strategy = SH_DIV_CALL_DIV1; | |
966 | } | |
967 | if (!TARGET_SH1) | |
968 | TARGET_PRETEND_CMOVE = 0; | |
969 | if (sh_divsi3_libfunc[0]) | |
970 | ; /* User supplied - leave it alone. */ | |
971 | else if (TARGET_DIVIDE_CALL_FP) | |
972 | sh_divsi3_libfunc = "__sdivsi3_i4"; | |
973 | else if (TARGET_DIVIDE_CALL_TABLE) | |
974 | sh_divsi3_libfunc = "__sdivsi3_i4i"; | |
975 | else if (TARGET_SH5) | |
976 | sh_divsi3_libfunc = "__sdivsi3_1"; | |
977 | else | |
978 | sh_divsi3_libfunc = "__sdivsi3"; | |
d580af0f | 979 | |
bd9a3465 | 980 | if (sh_branch_cost == -1) |
91afd29b | 981 | { |
91afd29b OE |
982 | /* The SH1 does not have delay slots, hence we get a pipeline stall |
983 | at every branch. The SH4 is superscalar, so the single delay slot | |
d580af0f OE |
984 | is not sufficient to keep both pipelines filled. |
985 | In any case, set the default branch cost to '2', as it results in | |
986 | slightly overall smaller code and also enables some if conversions | |
987 | that are required for matching special T bit related insns. */ | |
988 | sh_branch_cost = 2; | |
91afd29b | 989 | } |
bd9a3465 | 990 | |
f34ee0b2 OE |
991 | /* Set -mzdcbranch for SH4 / SH4A if not otherwise specified by the user. */ |
992 | if (! global_options_set.x_TARGET_ZDCBRANCH && TARGET_HARD_SH4) | |
993 | TARGET_ZDCBRANCH = 1; | |
994 | ||
bd9a3465 KK |
995 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
996 | if (! VALID_REGISTER_P (regno)) | |
997 | sh_register_names[regno][0] = '\0'; | |
998 | ||
999 | for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) | |
1000 | if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) | |
1001 | sh_additional_register_names[regno][0] = '\0'; | |
1002 | ||
bd9a3465 KK |
1003 | if ((flag_pic && ! TARGET_PREFERGOT) |
1004 | || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) | |
1005 | flag_no_function_cse = 1; | |
1006 | ||
50fe8924 | 1007 | if (targetm.small_register_classes_for_mode_p (VOIDmode)) |
bd9a3465 KK |
1008 | { |
1009 | /* Never run scheduling before reload, since that can | |
1010 | break global alloc, and generates slower code anyway due | |
1011 | to the pressure on R0. */ | |
1012 | /* Enable sched1 for SH4 if the user explicitly requests. | |
1013 | When sched1 is enabled, the ready queue will be reordered by | |
1014 | the target hooks if pressure is high. We can not do this for | |
1015 | PIC, SH3 and lower as they give spill failures for R0. */ | |
1016 | if (!TARGET_HARD_SH4 || flag_pic) | |
50fe8924 | 1017 | flag_schedule_insns = 0; |
bd9a3465 KK |
1018 | /* ??? Current exception handling places basic block boundaries |
1019 | after call_insns. It causes the high pressure on R0 and gives | |
1020 | spill failures for R0 in reload. See PR 22553 and the thread | |
1021 | on gcc-patches | |
50fe8924 | 1022 | <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ |
bd9a3465 KK |
1023 | else if (flag_exceptions) |
1024 | { | |
0a587f65 | 1025 | if (flag_schedule_insns && global_options_set.x_flag_schedule_insns) |
50fe8924 OE |
1026 | warning (0, "ignoring -fschedule-insns because of exception " |
1027 | "handling bug"); | |
bd9a3465 KK |
1028 | flag_schedule_insns = 0; |
1029 | } | |
0a587f65 JM |
1030 | else if (flag_schedule_insns |
1031 | && !global_options_set.x_flag_schedule_insns) | |
bd9a3465 KK |
1032 | flag_schedule_insns = 0; |
1033 | } | |
1034 | ||
5921cd19 CB |
1035 | /* Unwind info is not correct around the CFG unless either a frame |
1036 | pointer is present or M_A_O_A is set. Fixing this requires rewriting | |
1037 | unwind info generation to be aware of the CFG and propagating states | |
7a296495 CB |
1038 | around edges. */ |
1039 | if ((flag_unwind_tables || flag_asynchronous_unwind_tables | |
5921cd19 CB |
1040 | || flag_exceptions || flag_non_call_exceptions) |
1041 | && flag_omit_frame_pointer && !TARGET_ACCUMULATE_OUTGOING_ARGS) | |
7a296495 | 1042 | { |
5921cd19 CB |
1043 | warning (0, "unwind tables currently require either a frame pointer " |
1044 | "or -maccumulate-outgoing-args for correctness"); | |
1045 | TARGET_ACCUMULATE_OUTGOING_ARGS = 1; | |
7a296495 CB |
1046 | } |
1047 | ||
b6a0df6c OE |
1048 | /* Adjust loop, jump and function alignment values (in bytes), if those |
1049 | were not specified by the user using -falign-loops, -falign-jumps | |
1050 | and -falign-functions options. | |
1051 | 32 bit alignment is better for speed, because instructions can be | |
1052 | fetched as a pair from a longword boundary. For size use 16 bit | |
1053 | alignment to get more compact code. | |
1054 | Aligning all jumps increases the code size, even if it might | |
1055 | result in slightly faster code. Thus, it is set to the smallest | |
1056 | alignment possible if not specified by the user. */ | |
bd9a3465 | 1057 | if (align_loops == 0) |
b6a0df6c OE |
1058 | { |
1059 | if (TARGET_SH5) | |
1060 | align_loops = 8; | |
1061 | else | |
1062 | align_loops = optimize_size ? 2 : 4; | |
1063 | } | |
1064 | ||
bd9a3465 | 1065 | if (align_jumps == 0) |
b6a0df6c OE |
1066 | { |
1067 | if (TARGET_SHMEDIA) | |
1068 | align_jumps = 1 << CACHE_LOG; | |
1069 | else | |
1070 | align_jumps = 2; | |
1071 | } | |
bd9a3465 KK |
1072 | else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) |
1073 | align_jumps = TARGET_SHMEDIA ? 4 : 2; | |
1074 | ||
bd9a3465 | 1075 | if (align_functions == 0) |
b6a0df6c OE |
1076 | { |
1077 | if (TARGET_SHMEDIA) | |
1078 | align_functions = optimize_size | |
1079 | ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); | |
1080 | else | |
1081 | align_functions = optimize_size ? 2 : 4; | |
1082 | } | |
1083 | ||
bd9a3465 KK |
1084 | /* The linker relaxation code breaks when a function contains |
1085 | alignments that are larger than that at the start of a | |
1086 | compilation unit. */ | |
1087 | if (TARGET_RELAX) | |
1088 | { | |
50fe8924 | 1089 | int min_align = align_loops > align_jumps ? align_loops : align_jumps; |
bd9a3465 | 1090 | |
50fe8924 | 1091 | /* Also take possible .long constants / mova tables into account. */ |
bd9a3465 KK |
1092 | if (min_align < 4) |
1093 | min_align = 4; | |
1094 | if (align_functions < min_align) | |
1095 | align_functions = min_align; | |
1096 | } | |
1097 | ||
aba92f5f OE |
1098 | if (flag_unsafe_math_optimizations) |
1099 | { | |
aba92f5f OE |
1100 | /* Enable fsca insn for SH4A if not otherwise specified by the user. */ |
1101 | if (global_options_set.x_TARGET_FSCA == 0 && TARGET_SH4A_FP) | |
1102 | TARGET_FSCA = 1; | |
1103 | ||
1104 | /* Enable fsrra insn for SH4A if not otherwise specified by the user. */ | |
1105 | if (global_options_set.x_TARGET_FSRRA == 0 && TARGET_SH4A_FP) | |
1106 | TARGET_FSRRA = 1; | |
1107 | } | |
1108 | ||
1109 | /* Allow fsrra insn only if -funsafe-math-optimizations and | |
1110 | -ffinite-math-only is enabled. */ | |
1111 | TARGET_FSRRA = TARGET_FSRRA | |
1112 | && flag_unsafe_math_optimizations | |
1113 | && flag_finite_math_only; | |
2df2ce3f | 1114 | |
13f1f508 OE |
1115 | /* If the -mieee option was not explicitly set by the user, turn it on |
1116 | unless -ffinite-math-only was specified. See also PR 33135. */ | |
1117 | if (! global_options_set.x_TARGET_IEEE) | |
1118 | TARGET_IEEE = ! flag_finite_math_only; | |
1119 | ||
bd9a3465 KK |
1120 | if (sh_fixed_range_str) |
1121 | sh_fix_range (sh_fixed_range_str); | |
0685e770 DD |
1122 | |
1123 | /* This target defaults to strict volatile bitfields. */ | |
36acc1a2 | 1124 | if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) |
0685e770 | 1125 | flag_strict_volatile_bitfields = 1; |
c11394f8 | 1126 | |
7bd76b9c OE |
1127 | /* Parse atomic model option and make sure it is valid for the current |
1128 | target CPU. */ | |
1129 | selected_atomic_model_ | |
1130 | = parse_validate_atomic_model_option (sh_atomic_model_str); | |
5d30dc5b OE |
1131 | |
1132 | register_sh_passes (); | |
bd9a3465 KK |
1133 | } |
1134 | \f | |
16bea517 | 1135 | /* Print the operand address in x to the stream. */ |
9e94b957 NF |
1136 | static void |
1137 | sh_print_operand_address (FILE *stream, rtx x) | |
bc45ade3 SC |
1138 | { |
1139 | switch (GET_CODE (x)) | |
1140 | { | |
1141 | case REG: | |
225e4f43 R |
1142 | case SUBREG: |
1143 | fprintf (stream, "@%s", reg_names[true_regnum (x)]); | |
bc45ade3 | 1144 | break; |
8aa2a305 | 1145 | |
bc45ade3 SC |
1146 | case PLUS: |
1147 | { | |
1148 | rtx base = XEXP (x, 0); | |
1149 | rtx index = XEXP (x, 1); | |
1150 | ||
bc45ade3 SC |
1151 | switch (GET_CODE (index)) |
1152 | { | |
1153 | case CONST_INT: | |
c5b9ef02 | 1154 | fprintf (stream, "@(%d,%s)", (int) INTVAL (index), |
225e4f43 | 1155 | reg_names[true_regnum (base)]); |
bc45ade3 SC |
1156 | break; |
1157 | ||
1158 | case REG: | |
225e4f43 R |
1159 | case SUBREG: |
1160 | { | |
1161 | int base_num = true_regnum (base); | |
1162 | int index_num = true_regnum (index); | |
1163 | ||
1164 | fprintf (stream, "@(r0,%s)", | |
1165 | reg_names[MAX (base_num, index_num)]); | |
1166 | break; | |
1167 | } | |
bc45ade3 SC |
1168 | |
1169 | default: | |
f5b9e7c9 | 1170 | gcc_unreachable (); |
bc45ade3 SC |
1171 | } |
1172 | } | |
bc45ade3 | 1173 | break; |
8aa2a305 | 1174 | |
bc45ade3 | 1175 | case PRE_DEC: |
225e4f43 | 1176 | fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]); |
bc45ade3 SC |
1177 | break; |
1178 | ||
1179 | case POST_INC: | |
225e4f43 | 1180 | fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]); |
bc45ade3 SC |
1181 | break; |
1182 | ||
1183 | default: | |
b91455de | 1184 | x = mark_constant_pool_use (x); |
422be3c3 | 1185 | output_addr_const (stream, x); |
bc45ade3 SC |
1186 | break; |
1187 | } | |
1188 | } | |
1189 | ||
1190 | /* Print operand x (an rtx) in assembler syntax to file stream | |
1191 | according to modifier code. | |
1192 | ||
b9654711 | 1193 | '.' print a .s if insn needs delay slot |
1245df60 | 1194 | ',' print LOCAL_LABEL_PREFIX |
4408efce | 1195 | '@' print trap, rte or rts depending upon pragma interruptness |
8aa2a305 | 1196 | '#' output a nop if there is nothing to put in the delay slot |
fae778eb | 1197 | ''' print likelihood suffix (/u for unlikely). |
73a4d10b | 1198 | '>' print branch target if -fverbose-asm |
8aa2a305 | 1199 | 'O' print a constant without the # |
00f8ff66 | 1200 | 'R' print the LSW of a dp value - changes if in little endian |
00f8ff66 | 1201 | 'S' print the MSW of a dp value - changes if in little endian |
225e4f43 | 1202 | 'T' print the next word of a dp value - same as 'R' in big endian mode. |
31b6f0ae R |
1203 | 'M' SHMEDIA: print an `x' if `m' will print `base,index'. |
1204 | otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM. | |
c1b92d09 | 1205 | 'N' print 'r63' if the operand is (const_int 0). |
312209c6 | 1206 | 'd' print a V2SF reg as dN instead of fpN. |
fa5322fa | 1207 | 'm' print a pair `base,offset' or `base,index', for LD and ST. |
73a4d10b | 1208 | 'U' Likewise for {LD,ST}{HI,LO}. |
de6adfa2 N |
1209 | 'V' print the position of a single bit set. |
1210 | 'W' print the position of a single bit cleared. | |
9eb3a0dd | 1211 | 't' print a memory address which is a register. |
fa5322fa | 1212 | 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value. |
225e4f43 | 1213 | 'o' output an operator. */ |
9e94b957 NF |
1214 | static void |
1215 | sh_print_operand (FILE *stream, rtx x, int code) | |
bc45ade3 | 1216 | { |
73a4d10b | 1217 | int regno; |
ef4bddc2 | 1218 | machine_mode mode; |
73a4d10b | 1219 | |
bc45ade3 SC |
1220 | switch (code) |
1221 | { | |
a6ab9fc0 R |
1222 | tree trapa_attr; |
1223 | ||
b9654711 | 1224 | case '.': |
79b2746a | 1225 | if (final_sequence |
84034c69 DM |
1226 | && ! INSN_ANNULLED_BRANCH_P (final_sequence->insn (0)) |
1227 | && get_attr_length (final_sequence->insn (1))) | |
1245df60 R |
1228 | fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s"); |
1229 | break; | |
1230 | case ',': | |
1231 | fprintf (stream, "%s", LOCAL_LABEL_PREFIX); | |
b9654711 | 1232 | break; |
d3ae8277 | 1233 | case '@': |
a6ab9fc0 R |
1234 | trapa_attr = lookup_attribute ("trap_exit", |
1235 | DECL_ATTRIBUTES (current_function_decl)); | |
1236 | if (trapa_attr) | |
50fe8924 | 1237 | fprintf (stream, "trapa #%ld", |
a6ab9fc0 | 1238 | (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr)))); |
e3ba8d11 | 1239 | else if (sh_cfun_interrupt_handler_p ()) |
561642fa AP |
1240 | { |
1241 | if (sh_cfun_resbank_handler_p ()) | |
1242 | fprintf (stream, "resbank\n"); | |
1243 | fprintf (stream, "rte"); | |
1244 | } | |
d3ae8277 | 1245 | else |
8e87e161 | 1246 | fprintf (stream, "rts"); |
d3ae8277 | 1247 | break; |
bc45ade3 | 1248 | case '#': |
16bea517 | 1249 | /* Output a nop if there's nothing in the delay slot. */ |
bc45ade3 | 1250 | if (dbr_sequence_length () == 0) |
8aa2a305 | 1251 | fprintf (stream, "\n\tnop"); |
bc45ade3 | 1252 | break; |
c8cc4417 R |
1253 | case '\'': |
1254 | { | |
1255 | rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0); | |
1256 | ||
e5af9ddd | 1257 | if (note && XINT (note, 0) * 2 < REG_BR_PROB_BASE) |
c8cc4417 R |
1258 | fputs ("/u", stream); |
1259 | break; | |
1260 | } | |
73a4d10b R |
1261 | case '>': |
1262 | if (flag_verbose_asm && JUMP_LABEL (current_output_insn)) | |
1263 | { | |
1264 | fputs ("\t! target: ", stream); | |
1265 | output_addr_const (stream, JUMP_LABEL (current_output_insn)); | |
1266 | } | |
1267 | break; | |
b9654711 | 1268 | case 'O': |
b91455de | 1269 | x = mark_constant_pool_use (x); |
0d7e008e | 1270 | output_addr_const (stream, x); |
bc45ade3 | 1271 | break; |
4802062c R |
1272 | /* N.B.: %R / %S / %T adjust memory addresses by four. |
1273 | For SHMEDIA, that means they can be used to access the first and | |
1274 | second 32 bit part of a 64 bit (or larger) value that | |
1275 | might be held in floating point registers or memory. | |
1276 | While they can be used to access 64 bit parts of a larger value | |
1277 | held in general purpose registers, that won't work with memory - | |
1278 | neither for fp registers, since the frxx names are used. */ | |
bc45ade3 | 1279 | case 'R': |
4802062c R |
1280 | if (REG_P (x) || GET_CODE (x) == SUBREG) |
1281 | { | |
1282 | regno = true_regnum (x); | |
277772f6 | 1283 | regno += FP_REGISTER_P (regno) ? 1 : SH_REG_LSW_OFFSET; |
4802062c R |
1284 | fputs (reg_names[regno], (stream)); |
1285 | } | |
1286 | else if (MEM_P (x)) | |
1287 | { | |
277772f6 | 1288 | x = adjust_address (x, SImode, 4 * SH_REG_LSW_OFFSET); |
9e94b957 | 1289 | sh_print_operand_address (stream, XEXP (x, 0)); |
4802062c R |
1290 | } |
1291 | else | |
1292 | { | |
1293 | rtx sub = NULL_RTX; | |
1294 | ||
1295 | mode = GET_MODE (x); | |
1296 | if (mode == VOIDmode) | |
1297 | mode = DImode; | |
1298 | if (GET_MODE_SIZE (mode) >= 8) | |
277772f6 | 1299 | sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_LSW_OFFSET); |
4802062c | 1300 | if (sub) |
9e94b957 | 1301 | sh_print_operand (stream, sub, 0); |
4802062c R |
1302 | else |
1303 | output_operand_lossage ("invalid operand to %%R"); | |
1304 | } | |
8aa2a305 JW |
1305 | break; |
1306 | case 'S': | |
4802062c R |
1307 | if (REG_P (x) || GET_CODE (x) == SUBREG) |
1308 | { | |
1309 | regno = true_regnum (x); | |
277772f6 | 1310 | regno += FP_REGISTER_P (regno) ? 0 : SH_REG_MSW_OFFSET; |
4802062c R |
1311 | fputs (reg_names[regno], (stream)); |
1312 | } | |
1313 | else if (MEM_P (x)) | |
1314 | { | |
277772f6 | 1315 | x = adjust_address (x, SImode, 4 * SH_REG_MSW_OFFSET); |
9e94b957 | 1316 | sh_print_operand_address (stream, XEXP (x, 0)); |
4802062c R |
1317 | } |
1318 | else | |
1319 | { | |
1320 | rtx sub = NULL_RTX; | |
1321 | ||
1322 | mode = GET_MODE (x); | |
1323 | if (mode == VOIDmode) | |
1324 | mode = DImode; | |
1325 | if (GET_MODE_SIZE (mode) >= 8) | |
277772f6 | 1326 | sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_MSW_OFFSET); |
4802062c | 1327 | if (sub) |
9e94b957 | 1328 | sh_print_operand (stream, sub, 0); |
4802062c R |
1329 | else |
1330 | output_operand_lossage ("invalid operand to %%S"); | |
1331 | } | |
00f8ff66 SC |
1332 | break; |
1333 | case 'T': | |
16bea517 | 1334 | /* Next word of a double. */ |
bc45ade3 SC |
1335 | switch (GET_CODE (x)) |
1336 | { | |
1337 | case REG: | |
1338 | fputs (reg_names[REGNO (x) + 1], (stream)); | |
1339 | break; | |
1340 | case MEM: | |
225e4f43 R |
1341 | if (GET_CODE (XEXP (x, 0)) != PRE_DEC |
1342 | && GET_CODE (XEXP (x, 0)) != POST_INC) | |
b72f00af | 1343 | x = adjust_address (x, SImode, 4); |
9e94b957 | 1344 | sh_print_operand_address (stream, XEXP (x, 0)); |
bc45ade3 | 1345 | break; |
318881c0 KG |
1346 | default: |
1347 | break; | |
bc45ade3 SC |
1348 | } |
1349 | break; | |
9eb3a0dd N |
1350 | |
1351 | case 't': | |
f3536097 | 1352 | gcc_assert (MEM_P (x)); |
9eb3a0dd N |
1353 | x = XEXP (x, 0); |
1354 | switch (GET_CODE (x)) | |
1355 | { | |
1356 | case REG: | |
1357 | case SUBREG: | |
9e94b957 | 1358 | sh_print_operand (stream, x, 0); |
9eb3a0dd N |
1359 | break; |
1360 | default: | |
1361 | break; | |
1362 | } | |
1363 | break; | |
1364 | ||
225e4f43 R |
1365 | case 'o': |
1366 | switch (GET_CODE (x)) | |
1367 | { | |
1368 | case PLUS: fputs ("add", stream); break; | |
1369 | case MINUS: fputs ("sub", stream); break; | |
1370 | case MULT: fputs ("mul", stream); break; | |
1371 | case DIV: fputs ("div", stream); break; | |
c8cc4417 R |
1372 | case EQ: fputs ("eq", stream); break; |
1373 | case NE: fputs ("ne", stream); break; | |
1374 | case GT: case LT: fputs ("gt", stream); break; | |
1375 | case GE: case LE: fputs ("ge", stream); break; | |
1376 | case GTU: case LTU: fputs ("gtu", stream); break; | |
1377 | case GEU: case LEU: fputs ("geu", stream); break; | |
318881c0 KG |
1378 | default: |
1379 | break; | |
225e4f43 R |
1380 | } |
1381 | break; | |
fa5322fa | 1382 | case 'M': |
31b6f0ae R |
1383 | if (TARGET_SHMEDIA) |
1384 | { | |
f3536097 | 1385 | if (MEM_P (x) |
31b6f0ae | 1386 | && GET_CODE (XEXP (x, 0)) == PLUS |
f3536097 | 1387 | && (REG_P (XEXP (XEXP (x, 0), 1)) |
31b6f0ae R |
1388 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG)) |
1389 | fputc ('x', stream); | |
1390 | } | |
1391 | else | |
1392 | { | |
f3536097 | 1393 | if (MEM_P (x)) |
31b6f0ae R |
1394 | { |
1395 | switch (GET_MODE (x)) | |
1396 | { | |
1397 | case QImode: fputs (".b", stream); break; | |
1398 | case HImode: fputs (".w", stream); break; | |
1399 | case SImode: fputs (".l", stream); break; | |
1400 | case SFmode: fputs (".s", stream); break; | |
1401 | case DFmode: fputs (".d", stream); break; | |
1402 | default: gcc_unreachable (); | |
1403 | } | |
1404 | } | |
1405 | } | |
fa5322fa AO |
1406 | break; |
1407 | ||
1408 | case 'm': | |
f3536097 | 1409 | gcc_assert (MEM_P (x)); |
fa5322fa | 1410 | x = XEXP (x, 0); |
73a4d10b R |
1411 | /* Fall through. */ |
1412 | case 'U': | |
fa5322fa AO |
1413 | switch (GET_CODE (x)) |
1414 | { | |
1415 | case REG: | |
1416 | case SUBREG: | |
9e94b957 | 1417 | sh_print_operand (stream, x, 0); |
fa5322fa AO |
1418 | fputs (", 0", stream); |
1419 | break; | |
1420 | ||
1421 | case PLUS: | |
9e94b957 | 1422 | sh_print_operand (stream, XEXP (x, 0), 0); |
fa5322fa | 1423 | fputs (", ", stream); |
9e94b957 | 1424 | sh_print_operand (stream, XEXP (x, 1), 0); |
fa5322fa AO |
1425 | break; |
1426 | ||
1427 | default: | |
f5b9e7c9 | 1428 | gcc_unreachable (); |
fa5322fa AO |
1429 | } |
1430 | break; | |
1431 | ||
de6adfa2 N |
1432 | case 'V': |
1433 | { | |
1434 | int num = exact_log2 (INTVAL (x)); | |
1435 | gcc_assert (num >= 0); | |
1436 | fprintf (stream, "#%d", num); | |
1437 | } | |
1438 | break; | |
1439 | ||
1440 | case 'W': | |
1441 | { | |
1442 | int num = exact_log2 (~INTVAL (x)); | |
1443 | gcc_assert (num >= 0); | |
1444 | fprintf (stream, "#%d", num); | |
1445 | } | |
1446 | break; | |
1447 | ||
312209c6 | 1448 | case 'd': |
f3536097 | 1449 | gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode); |
312209c6 AO |
1450 | |
1451 | fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1); | |
1452 | break; | |
f676971a | 1453 | |
c1b92d09 | 1454 | case 'N': |
0ac78517 | 1455 | if (x == CONST0_RTX (GET_MODE (x))) |
c1b92d09 R |
1456 | { |
1457 | fprintf ((stream), "r63"); | |
1458 | break; | |
1459 | } | |
1460 | goto default_output; | |
fa5322fa | 1461 | case 'u': |
f3536097 | 1462 | if (CONST_INT_P (x)) |
c8cc4417 | 1463 | { |
fa5322fa AO |
1464 | fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1)); |
1465 | break; | |
1466 | } | |
1467 | /* Fall through. */ | |
1468 | ||
c1b92d09 | 1469 | default_output: |
bc45ade3 | 1470 | default: |
73a4d10b R |
1471 | regno = 0; |
1472 | mode = GET_MODE (x); | |
1473 | ||
bc45ade3 SC |
1474 | switch (GET_CODE (x)) |
1475 | { | |
73a4d10b R |
1476 | case TRUNCATE: |
1477 | { | |
1478 | rtx inner = XEXP (x, 0); | |
1479 | int offset = 0; | |
ef4bddc2 | 1480 | machine_mode inner_mode; |
73a4d10b R |
1481 | |
1482 | /* We might see SUBREGs with vector mode registers inside. */ | |
1483 | if (GET_CODE (inner) == SUBREG | |
1484 | && (GET_MODE_SIZE (GET_MODE (inner)) | |
1485 | == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner)))) | |
1486 | && subreg_lowpart_p (inner)) | |
1487 | inner = SUBREG_REG (inner); | |
f3536097 | 1488 | if (CONST_INT_P (inner)) |
73a4d10b R |
1489 | { |
1490 | x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x))); | |
1491 | goto default_output; | |
1492 | } | |
1493 | inner_mode = GET_MODE (inner); | |
1494 | if (GET_CODE (inner) == SUBREG | |
1495 | && (GET_MODE_SIZE (GET_MODE (inner)) | |
1496 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner)))) | |
f3536097 | 1497 | && REG_P (SUBREG_REG (inner))) |
73a4d10b R |
1498 | { |
1499 | offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)), | |
1500 | GET_MODE (SUBREG_REG (inner)), | |
1501 | SUBREG_BYTE (inner), | |
1502 | GET_MODE (inner)); | |
1503 | inner = SUBREG_REG (inner); | |
1504 | } | |
f3536097 | 1505 | if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8) |
73a4d10b R |
1506 | abort (); |
1507 | /* Floating point register pairs are always big endian; | |
30dc60c7 | 1508 | general purpose registers are 64 bit wide. */ |
73a4d10b R |
1509 | regno = REGNO (inner); |
1510 | regno = (HARD_REGNO_NREGS (regno, inner_mode) | |
1511 | - HARD_REGNO_NREGS (regno, mode)) | |
1512 | + offset; | |
1513 | x = inner; | |
1514 | goto reg; | |
1515 | } | |
1516 | case SIGN_EXTEND: | |
1517 | x = XEXP (x, 0); | |
1518 | goto reg; | |
fa5322fa AO |
1519 | /* FIXME: We need this on SHmedia32 because reload generates |
1520 | some sign-extended HI or QI loads into DImode registers | |
1521 | but, because Pmode is SImode, the address ends up with a | |
1522 | subreg:SI of the DImode register. Maybe reload should be | |
1523 | fixed so as to apply alter_subreg to such loads? */ | |
73a4d10b R |
1524 | case IF_THEN_ELSE: |
1525 | gcc_assert (trapping_target_operand (x, VOIDmode)); | |
1526 | x = XEXP (XEXP (x, 2), 0); | |
1527 | goto default_output; | |
fa5322fa | 1528 | case SUBREG: |
f5b9e7c9 | 1529 | gcc_assert (SUBREG_BYTE (x) == 0 |
f3536097 | 1530 | && REG_P (SUBREG_REG (x))); |
fa5322fa AO |
1531 | |
1532 | x = SUBREG_REG (x); | |
1533 | /* Fall through. */ | |
1534 | ||
73a4d10b | 1535 | reg: |
bc45ade3 | 1536 | case REG: |
73a4d10b R |
1537 | regno += REGNO (x); |
1538 | if (FP_REGISTER_P (regno) | |
1539 | && mode == V16SFmode) | |
1540 | fprintf ((stream), "mtrx%s", reg_names[regno] + 2); | |
fa5322fa | 1541 | else if (FP_REGISTER_P (REGNO (x)) |
73a4d10b R |
1542 | && mode == V4SFmode) |
1543 | fprintf ((stream), "fv%s", reg_names[regno] + 2); | |
f3536097 | 1544 | else if (REG_P (x) |
73a4d10b R |
1545 | && mode == V2SFmode) |
1546 | fprintf ((stream), "fp%s", reg_names[regno] + 2); | |
fa5322fa | 1547 | else if (FP_REGISTER_P (REGNO (x)) |
73a4d10b R |
1548 | && GET_MODE_SIZE (mode) > 4) |
1549 | fprintf ((stream), "d%s", reg_names[regno] + 1); | |
225e4f43 | 1550 | else |
73a4d10b | 1551 | fputs (reg_names[regno], (stream)); |
bc45ade3 | 1552 | break; |
fa5322fa | 1553 | |
bc45ade3 SC |
1554 | case MEM: |
1555 | output_address (XEXP (x, 0)); | |
1556 | break; | |
f676971a | 1557 | |
bc45ade3 | 1558 | default: |
fa5322fa AO |
1559 | if (TARGET_SH1) |
1560 | fputc ('#', stream); | |
bc45ade3 SC |
1561 | output_addr_const (stream, x); |
1562 | break; | |
bc45ade3 SC |
1563 | } |
1564 | break; | |
1565 | } | |
1566 | } | |
9e94b957 NF |
1567 | |
1568 | static bool | |
1569 | sh_print_operand_punct_valid_p (unsigned char code) | |
1570 | { | |
1571 | return (code == '.' || code == '#' || code == '@' || code == ',' | |
50fe8924 | 1572 | || code == '$' || code == '\'' || code == '>'); |
9e94b957 | 1573 | } |
ef875e12 AS |
1574 | |
1575 | /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */ | |
ef875e12 AS |
1576 | static bool |
1577 | sh_asm_output_addr_const_extra (FILE *file, rtx x) | |
1578 | { | |
1579 | if (GET_CODE (x) == UNSPEC) | |
1580 | { | |
1581 | switch (XINT (x, 1)) | |
1582 | { | |
1583 | case UNSPEC_DATALABEL: | |
1584 | fputs ("datalabel ", file); | |
1585 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1586 | break; | |
1587 | case UNSPEC_PIC: | |
1588 | /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ | |
1589 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1590 | break; | |
1591 | case UNSPEC_GOT: | |
1592 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1593 | fputs ("@GOT", file); | |
1594 | break; | |
1595 | case UNSPEC_GOTOFF: | |
1596 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1597 | fputs ("@GOTOFF", file); | |
1598 | break; | |
1599 | case UNSPEC_PLT: | |
1600 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1601 | fputs ("@PLT", file); | |
1602 | break; | |
1603 | case UNSPEC_GOTPLT: | |
1604 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1605 | fputs ("@GOTPLT", file); | |
1606 | break; | |
1607 | case UNSPEC_DTPOFF: | |
1608 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1609 | fputs ("@DTPOFF", file); | |
1610 | break; | |
1611 | case UNSPEC_GOTTPOFF: | |
1612 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1613 | fputs ("@GOTTPOFF", file); | |
1614 | break; | |
1615 | case UNSPEC_TPOFF: | |
1616 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1617 | fputs ("@TPOFF", file); | |
1618 | break; | |
1619 | case UNSPEC_CALLER: | |
1620 | { | |
1621 | char name[32]; | |
1622 | /* LPCS stands for Label for PIC Call Site. */ | |
1623 | targetm.asm_out.generate_internal_label (name, "LPCS", | |
1624 | INTVAL (XVECEXP (x, 0, 0))); | |
1625 | assemble_name (file, name); | |
1626 | } | |
1627 | break; | |
1628 | case UNSPEC_EXTRACT_S16: | |
1629 | case UNSPEC_EXTRACT_U16: | |
1630 | { | |
1631 | rtx val, shift; | |
1632 | ||
1633 | val = XVECEXP (x, 0, 0); | |
1634 | shift = XVECEXP (x, 0, 1); | |
1635 | fputc ('(', file); | |
1636 | if (shift != const0_rtx) | |
50fe8924 | 1637 | fputc ('(', file); |
ef875e12 | 1638 | if (GET_CODE (val) == CONST |
50fe8924 | 1639 | || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ) |
ef875e12 AS |
1640 | { |
1641 | fputc ('(', file); | |
1642 | output_addr_const (file, val); | |
1643 | fputc (')', file); | |
1644 | } | |
1645 | else | |
1646 | output_addr_const (file, val); | |
1647 | if (shift != const0_rtx) | |
1648 | { | |
1649 | fputs (" >> ", file); | |
1650 | output_addr_const (file, shift); | |
1651 | fputc (')', file); | |
1652 | } | |
1653 | fputs (" & 65535)", file); | |
1654 | } | |
1655 | break; | |
1656 | case UNSPEC_SYMOFF: | |
1657 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1658 | fputc ('-', file); | |
1659 | if (GET_CODE (XVECEXP (x, 0, 1)) == CONST) | |
1660 | { | |
1661 | fputc ('(', file); | |
1662 | output_addr_const (file, XVECEXP (x, 0, 1)); | |
1663 | fputc (')', file); | |
1664 | } | |
1665 | else | |
1666 | output_addr_const (file, XVECEXP (x, 0, 1)); | |
1667 | break; | |
1668 | case UNSPEC_PCREL_SYMOFF: | |
1669 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1670 | fputs ("-(", file); | |
1671 | output_addr_const (file, XVECEXP (x, 0, 1)); | |
1672 | fputs ("-.)", file); | |
1673 | break; | |
1674 | default: | |
1675 | return false; | |
1676 | } | |
1677 | return true; | |
1678 | } | |
1679 | else | |
1680 | return false; | |
1681 | } | |
bc45ade3 | 1682 | \f |
561642fa AP |
1683 | /* Encode symbol attributes of a SYMBOL_REF into its |
1684 | SYMBOL_REF_FLAGS. */ | |
1685 | static void | |
1686 | sh_encode_section_info (tree decl, rtx rtl, int first) | |
1687 | { | |
1688 | default_encode_section_info (decl, rtl, first); | |
1689 | ||
1690 | if (TREE_CODE (decl) == FUNCTION_DECL | |
1691 | && sh2a_function_vector_p (decl) && TARGET_SH2A) | |
1692 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION; | |
1693 | } | |
1694 | ||
bc45ade3 | 1695 | /* Prepare operands for a move define_expand; specifically, one of the |
8aa2a305 | 1696 | operands must be in a register. */ |
2ef6611e | 1697 | void |
ef4bddc2 | 1698 | prepare_move_operands (rtx operands[], machine_mode mode) |
bc45ade3 | 1699 | { |
463f02cd KK |
1700 | if ((mode == SImode || mode == DImode) |
1701 | && flag_pic | |
1702 | && ! ((mode == Pmode || mode == ptr_mode) | |
81f40b79 | 1703 | && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE)) |
1a66cd67 AO |
1704 | { |
1705 | rtx temp; | |
1706 | if (SYMBOLIC_CONST_P (operands[1])) | |
1707 | { | |
f3536097 | 1708 | if (MEM_P (operands[0])) |
1a66cd67 | 1709 | operands[1] = force_reg (Pmode, operands[1]); |
5615d8fd SC |
1710 | else if (TARGET_SHMEDIA |
1711 | && GET_CODE (operands[1]) == LABEL_REF | |
fa5322fa AO |
1712 | && target_reg_operand (operands[0], mode)) |
1713 | /* It's ok. */; | |
1a66cd67 AO |
1714 | else |
1715 | { | |
b3a13419 ILT |
1716 | temp = (!can_create_pseudo_p () |
1717 | ? operands[0] | |
1718 | : gen_reg_rtx (Pmode)); | |
fa5322fa | 1719 | operands[1] = legitimize_pic_address (operands[1], mode, temp); |
1a66cd67 AO |
1720 | } |
1721 | } | |
1722 | else if (GET_CODE (operands[1]) == CONST | |
1723 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1724 | && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0))) | |
1725 | { | |
b3a13419 | 1726 | temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); |
1a66cd67 | 1727 | temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0), |
fa5322fa AO |
1728 | mode, temp); |
1729 | operands[1] = expand_binop (mode, add_optab, temp, | |
1a66cd67 | 1730 | XEXP (XEXP (operands[1], 0), 1), |
b3a13419 ILT |
1731 | (!can_create_pseudo_p () |
1732 | ? temp | |
1733 | : gen_reg_rtx (Pmode)), | |
68c37dc9 | 1734 | 0, OPTAB_LIB_WIDEN); |
1a66cd67 AO |
1735 | } |
1736 | } | |
1737 | ||
e22856e8 JW |
1738 | if (! reload_in_progress && ! reload_completed) |
1739 | { | |
1740 | /* Copy the source to a register if both operands aren't registers. */ | |
1741 | if (! register_operand (operands[0], mode) | |
d9da94a1 | 1742 | && ! sh_register_operand (operands[1], mode)) |
e22856e8 JW |
1743 | operands[1] = copy_to_mode_reg (mode, operands[1]); |
1744 | ||
f3536097 | 1745 | if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode)) |
266a2732 R |
1746 | { |
1747 | /* This is like change_address_1 (operands[0], mode, 0, 1) , | |
1748 | except that we can't use that function because it is static. */ | |
0a2aaacc KG |
1749 | rtx new_rtx = change_address (operands[0], mode, 0); |
1750 | MEM_COPY_ATTRIBUTES (new_rtx, operands[0]); | |
1751 | operands[0] = new_rtx; | |
266a2732 R |
1752 | } |
1753 | ||
e22856e8 JW |
1754 | /* This case can happen while generating code to move the result |
1755 | of a library call to the target. Reject `st r0,@(rX,rY)' because | |
1756 | reload will fail to find a spill register for rX, since r0 is already | |
1757 | being used for the source. */ | |
73a4d10b | 1758 | else if (TARGET_SH1 |
c9bd6bcd | 1759 | && refers_to_regno_p (R0_REG, operands[1]) |
f3536097 | 1760 | && MEM_P (operands[0]) |
e22856e8 | 1761 | && GET_CODE (XEXP (operands[0], 0)) == PLUS |
f3536097 | 1762 | && REG_P (XEXP (XEXP (operands[0], 0), 1))) |
e22856e8 | 1763 | operands[1] = copy_to_mode_reg (mode, operands[1]); |
1e3e92b5 KK |
1764 | |
1765 | /* When the displacement addressing is used, RA will assign r0 to | |
1766 | the pseudo register operand for the QI/HImode load/store. | |
1767 | This tends to make a long live range for R0 and might cause | |
1768 | anomalous register spills in some case with LRA. See PR | |
1769 | target/55212. | |
1770 | We split possible load/store to two move insns via r0 so as to | |
1771 | shorten R0 live range. It will make some codes worse but will | |
3cad5f64 KK |
1772 | win on average for LRA. |
1773 | Also when base+index addressing is used and the index term is | |
1774 | a subreg, LRA assumes that more hard registers can be available | |
1775 | in some situation. It isn't the case for SH in the problematic | |
1776 | case. We can pre-allocate R0 for that index term to avoid | |
1777 | the issue. See PR target/66591. */ | |
1e3e92b5 KK |
1778 | else if (sh_lra_p () |
1779 | && TARGET_SH1 && ! TARGET_SH2A | |
1e3e92b5 KK |
1780 | && ((REG_P (operands[0]) && MEM_P (operands[1])) |
1781 | || (REG_P (operands[1]) && MEM_P (operands[0])))) | |
1782 | { | |
1783 | bool load_p = REG_P (operands[0]); | |
1784 | rtx reg = operands[load_p ? 0 : 1]; | |
1785 | rtx adr = XEXP (operands[load_p ? 1 : 0], 0); | |
1786 | ||
3cad5f64 KK |
1787 | if ((mode == QImode || mode == HImode) |
1788 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1e3e92b5 KK |
1789 | && GET_CODE (adr) == PLUS |
1790 | && REG_P (XEXP (adr, 0)) | |
1791 | && (REGNO (XEXP (adr, 0)) >= FIRST_PSEUDO_REGISTER) | |
1792 | && CONST_INT_P (XEXP (adr, 1)) | |
1793 | && INTVAL (XEXP (adr, 1)) != 0 | |
1794 | && sh_legitimate_index_p (mode, XEXP (adr, 1), false, true)) | |
1795 | { | |
1796 | rtx r0_rtx = gen_rtx_REG (mode, R0_REG); | |
1797 | emit_move_insn (r0_rtx, operands[1]); | |
1798 | operands[1] = r0_rtx; | |
1799 | } | |
3cad5f64 KK |
1800 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER |
1801 | && GET_CODE (adr) == PLUS | |
1802 | && REG_P (XEXP (adr, 0)) | |
1803 | && (REGNO (XEXP (adr, 0)) >= FIRST_PSEUDO_REGISTER) | |
1804 | && SUBREG_P (XEXP (adr, 1)) | |
1805 | && REG_P (SUBREG_REG (XEXP (adr, 1)))) | |
1806 | { | |
1807 | rtx r0_rtx = gen_rtx_REG (GET_MODE (XEXP (adr, 1)), R0_REG); | |
1808 | emit_move_insn (r0_rtx, XEXP (adr, 1)); | |
1809 | XEXP (adr, 1) = r0_rtx; | |
1810 | } | |
1e3e92b5 | 1811 | } |
e22856e8 | 1812 | } |
8aa2a305 | 1813 | |
463f02cd KK |
1814 | if (mode == Pmode || mode == ptr_mode) |
1815 | { | |
6058b2fa | 1816 | rtx op0, op1, opc; |
463f02cd KK |
1817 | enum tls_model tls_kind; |
1818 | ||
1819 | op0 = operands[0]; | |
1820 | op1 = operands[1]; | |
6058b2fa KK |
1821 | if (GET_CODE (op1) == CONST |
1822 | && GET_CODE (XEXP (op1, 0)) == PLUS | |
81f40b79 ILT |
1823 | && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode) |
1824 | != TLS_MODEL_NONE)) | |
6058b2fa KK |
1825 | { |
1826 | opc = XEXP (XEXP (op1, 0), 1); | |
1827 | op1 = XEXP (XEXP (op1, 0), 0); | |
1828 | } | |
1829 | else | |
1830 | opc = NULL_RTX; | |
1831 | ||
be6b0bec KK |
1832 | if (! reload_in_progress && ! reload_completed |
1833 | && (tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE) | |
463f02cd KK |
1834 | { |
1835 | rtx tga_op1, tga_ret, tmp, tmp2; | |
1836 | ||
c2bbcb0d KK |
1837 | if (! flag_pic |
1838 | && (tls_kind == TLS_MODEL_GLOBAL_DYNAMIC | |
1839 | || tls_kind == TLS_MODEL_LOCAL_DYNAMIC | |
1840 | || tls_kind == TLS_MODEL_INITIAL_EXEC)) | |
1841 | { | |
b6d10e0b | 1842 | static int got_labelno; |
c2bbcb0d KK |
1843 | /* Don't schedule insns for getting GOT address when |
1844 | the first scheduling is enabled, to avoid spill | |
1845 | failures for R0. */ | |
1846 | if (flag_schedule_insns) | |
1847 | emit_insn (gen_blockage ()); | |
b6d10e0b | 1848 | emit_insn (gen_GOTaddr2picreg (GEN_INT (++got_labelno))); |
c2bbcb0d KK |
1849 | emit_use (gen_rtx_REG (SImode, PIC_REG)); |
1850 | if (flag_schedule_insns) | |
1851 | emit_insn (gen_blockage ()); | |
1852 | } | |
1853 | ||
463f02cd KK |
1854 | switch (tls_kind) |
1855 | { | |
1856 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
1857 | tga_ret = gen_rtx_REG (Pmode, R0_REG); | |
13ecc9e0 | 1858 | emit_call_insn (gen_tls_global_dynamic (tga_ret, op1)); |
c2bbcb0d KK |
1859 | tmp = gen_reg_rtx (Pmode); |
1860 | emit_move_insn (tmp, tga_ret); | |
1861 | op1 = tmp; | |
463f02cd KK |
1862 | break; |
1863 | ||
1864 | case TLS_MODEL_LOCAL_DYNAMIC: | |
1865 | tga_ret = gen_rtx_REG (Pmode, R0_REG); | |
13ecc9e0 | 1866 | emit_call_insn (gen_tls_local_dynamic (tga_ret, op1)); |
463f02cd KK |
1867 | |
1868 | tmp = gen_reg_rtx (Pmode); | |
1869 | emit_move_insn (tmp, tga_ret); | |
1870 | ||
1871 | if (register_operand (op0, Pmode)) | |
1872 | tmp2 = op0; | |
1873 | else | |
1874 | tmp2 = gen_reg_rtx (Pmode); | |
1875 | ||
1876 | emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp)); | |
1877 | op1 = tmp2; | |
1878 | break; | |
1879 | ||
1880 | case TLS_MODEL_INITIAL_EXEC: | |
b3a13419 | 1881 | tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode); |
463f02cd KK |
1882 | tmp = gen_sym2GOTTPOFF (op1); |
1883 | emit_insn (gen_tls_initial_exec (tga_op1, tmp)); | |
1884 | op1 = tga_op1; | |
1885 | break; | |
1886 | ||
1887 | case TLS_MODEL_LOCAL_EXEC: | |
1888 | tmp2 = gen_reg_rtx (Pmode); | |
7d11d296 | 1889 | emit_insn (gen_store_gbr (tmp2)); |
463f02cd KK |
1890 | tmp = gen_reg_rtx (Pmode); |
1891 | emit_insn (gen_symTPOFF2reg (tmp, op1)); | |
463f02cd KK |
1892 | |
1893 | if (register_operand (op0, Pmode)) | |
1894 | op1 = op0; | |
1895 | else | |
1896 | op1 = gen_reg_rtx (Pmode); | |
1897 | ||
1898 | emit_insn (gen_addsi3 (op1, tmp, tmp2)); | |
1899 | break; | |
1900 | ||
1901 | default: | |
f5b9e7c9 | 1902 | gcc_unreachable (); |
463f02cd | 1903 | } |
6058b2fa KK |
1904 | if (opc) |
1905 | emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc))); | |
463f02cd KK |
1906 | operands[1] = op1; |
1907 | } | |
1908 | } | |
8aa2a305 JW |
1909 | } |
1910 | ||
c354951b AK |
1911 | /* Implement the canonicalize_comparison target hook for the combine |
1912 | pass. For the target hook this function is invoked via | |
1913 | sh_canonicalize_comparison. This function is also re-used to | |
1914 | canonicalize comparisons in cbranch pattern expanders. */ | |
1915 | static void | |
ff596ca1 | 1916 | sh_canonicalize_comparison (enum rtx_code& cmp, rtx& op0, rtx& op1, |
ef4bddc2 | 1917 | machine_mode mode, |
5d30dc5b | 1918 | bool op0_preserve_value) |
78d310c2 | 1919 | { |
ff596ca1 OE |
1920 | /* When invoked from within the combine pass the mode is not specified, |
1921 | so try to get it from one of the operands. */ | |
1922 | if (mode == VOIDmode) | |
1923 | mode = GET_MODE (op0); | |
1924 | if (mode == VOIDmode) | |
1925 | mode = GET_MODE (op1); | |
1926 | ||
1927 | // We need to have a mode to do something useful here. | |
1928 | if (mode == VOIDmode) | |
1929 | return; | |
1930 | ||
1931 | // Currently, we don't deal with floats here. | |
1932 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
1933 | return; | |
1934 | ||
1935 | // Make sure that the constant operand is the second operand. | |
1936 | if (CONST_INT_P (op0) && !CONST_INT_P (op1)) | |
78d310c2 | 1937 | { |
5d30dc5b OE |
1938 | if (op0_preserve_value) |
1939 | return; | |
1940 | ||
ff596ca1 OE |
1941 | std::swap (op0, op1); |
1942 | cmp = swap_condition (cmp); | |
78d310c2 | 1943 | } |
ff596ca1 OE |
1944 | |
1945 | if (CONST_INT_P (op1)) | |
78d310c2 | 1946 | { |
ff596ca1 | 1947 | /* Try to adjust the constant operand in such a way that available |
50fe8924 OE |
1948 | comparison insns can be utilized better and the constant can be |
1949 | loaded with a 'mov #imm,Rm' insn. This avoids a load from the | |
1950 | constant pool. */ | |
ff596ca1 OE |
1951 | const HOST_WIDE_INT val = INTVAL (op1); |
1952 | ||
1953 | /* x > -1 --> x >= 0 | |
1954 | x > 0xFFFFFF7F --> x >= 0xFFFFFF80 | |
1955 | x <= -1 --> x < 0 | |
1956 | x <= 0xFFFFFF7F --> x < 0xFFFFFF80 */ | |
1957 | if ((val == -1 || val == -0x81) && (cmp == GT || cmp == LE)) | |
1958 | { | |
1959 | cmp = cmp == GT ? GE : LT; | |
1960 | op1 = gen_int_mode (val + 1, mode); | |
1961 | } | |
1962 | ||
1963 | /* x >= 1 --> x > 0 | |
1964 | x >= 0x80 --> x > 0x7F | |
1965 | x < 1 --> x <= 0 | |
1966 | x < 0x80 --> x <= 0x7F */ | |
1967 | else if ((val == 1 || val == 0x80) && (cmp == GE || cmp == LT)) | |
78d310c2 | 1968 | { |
ff596ca1 OE |
1969 | cmp = cmp == GE ? GT : LE; |
1970 | op1 = gen_int_mode (val - 1, mode); | |
78d310c2 | 1971 | } |
ff596ca1 OE |
1972 | |
1973 | /* unsigned x >= 1 --> x != 0 | |
1974 | unsigned x < 1 --> x == 0 */ | |
1975 | else if (val == 1 && (cmp == GEU || cmp == LTU)) | |
78d310c2 | 1976 | { |
ff596ca1 OE |
1977 | cmp = cmp == GEU ? NE : EQ; |
1978 | op1 = CONST0_RTX (mode); | |
78d310c2 | 1979 | } |
ff596ca1 OE |
1980 | |
1981 | /* unsigned x >= 0x80 --> unsigned x > 0x7F | |
1982 | unsigned x < 0x80 --> unsigned x < 0x7F */ | |
1983 | else if (val == 0x80 && (cmp == GEU || cmp == LTU)) | |
78d310c2 | 1984 | { |
ff596ca1 OE |
1985 | cmp = cmp == GEU ? GTU : LEU; |
1986 | op1 = gen_int_mode (val - 1, mode); | |
78d310c2 | 1987 | } |
ff596ca1 OE |
1988 | |
1989 | /* unsigned x > 0 --> x != 0 | |
1990 | unsigned x <= 0 --> x == 0 */ | |
1991 | else if (val == 0 && (cmp == GTU || cmp == LEU)) | |
1992 | cmp = cmp == GTU ? NE : EQ; | |
1993 | ||
1994 | /* unsigned x > 0x7FFFFFFF --> signed x < 0 | |
1995 | unsigned x <= 0x7FFFFFFF --> signed x >= 0 */ | |
1996 | else if (mode == SImode && (cmp == GTU || cmp == LEU) | |
1997 | && val == 0x7FFFFFFF) | |
78d310c2 | 1998 | { |
ff596ca1 OE |
1999 | cmp = cmp == GTU ? LT : GE; |
2000 | op1 = const0_rtx; | |
78d310c2 | 2001 | } |
ff596ca1 OE |
2002 | |
2003 | /* unsigned x >= 0x80000000 --> signed x < 0 | |
2004 | unsigned x < 0x80000000 --> signed x >= 0 */ | |
2005 | else if (mode == SImode && (cmp == GEU || cmp == LTU) | |
2006 | && (unsigned HOST_WIDE_INT)val | |
2007 | == ((unsigned HOST_WIDE_INT)0x7FFFFFFF + 1)) | |
78d310c2 | 2008 | { |
ff596ca1 OE |
2009 | cmp = cmp == GEU ? LT : GE; |
2010 | op1 = const0_rtx; | |
78d310c2 R |
2011 | } |
2012 | } | |
ff596ca1 OE |
2013 | } |
2014 | ||
c354951b AK |
2015 | /* This function implements the canonicalize_comparison target hook. |
2016 | This wrapper around the internally used sh_canonicalize_comparison | |
2017 | function is needed to do the enum rtx_code <-> int conversion. | |
2018 | Target hooks cannot use enum rtx_code in its definition. */ | |
2019 | static void | |
2020 | sh_canonicalize_comparison (int *code, rtx *op0, rtx *op1, | |
2021 | bool op0_preserve_value) | |
2022 | { | |
2023 | enum rtx_code tmp_code = (enum rtx_code)*code; | |
2024 | sh_canonicalize_comparison (tmp_code, *op0, *op1, | |
2025 | VOIDmode, op0_preserve_value); | |
2026 | *code = (int)tmp_code; | |
2027 | } | |
50fe8924 | 2028 | |
841dbf80 OE |
2029 | /* This function implements the legitimate_combined_insn target hook, |
2030 | which the combine pass uses to early reject combined insns, before | |
2031 | it tries to recog the insn and determine its cost. */ | |
2032 | static bool | |
2033 | sh_legitimate_combined_insn (rtx_insn* insn) | |
2034 | { | |
2035 | /* Reject combinations of memory loads and zero extensions, as these | |
2036 | interfere with other combine patterns such as zero extracts and bit | |
2037 | tests. The SH2A movu.{b|w} insns are formed later in the | |
2038 | 'sh_optimize_extu_exts' pass after combine/split1. */ | |
2039 | rtx p = PATTERN (insn); | |
2040 | if (GET_CODE (p) == SET | |
2041 | && REG_P (XEXP (p, 0)) && GET_MODE (XEXP (p, 0)) == SImode | |
2042 | && GET_CODE (XEXP (p, 1)) == ZERO_EXTEND | |
2043 | && MEM_P (XEXP (XEXP (p, 1), 0))) | |
2044 | return false; | |
2045 | ||
2046 | return true; | |
2047 | } | |
2048 | ||
5d30dc5b OE |
2049 | bool |
2050 | sh_fixed_condition_code_regs (unsigned int* p1, unsigned int* p2) | |
2051 | { | |
2052 | *p1 = T_REG; | |
2053 | *p2 = INVALID_REGNUM; | |
2054 | return true; | |
2055 | } | |
2056 | ||
ff596ca1 | 2057 | enum rtx_code |
ef4bddc2 | 2058 | prepare_cbranch_operands (rtx *operands, machine_mode mode, |
ff596ca1 OE |
2059 | enum rtx_code comparison) |
2060 | { | |
2061 | /* The scratch reg is only available when this is invoked from within | |
2062 | the cbranchdi4_i splitter, through expand_cbranchdi4. */ | |
2063 | rtx scratch = NULL_RTX; | |
2064 | ||
2065 | if (comparison == LAST_AND_UNUSED_RTX_CODE) | |
2066 | comparison = GET_CODE (operands[0]); | |
2067 | else | |
2068 | scratch = operands[4]; | |
2069 | ||
c354951b AK |
2070 | sh_canonicalize_comparison (comparison, operands[1], operands[2], |
2071 | mode, false); | |
ff596ca1 OE |
2072 | |
2073 | /* Notice that this function is also invoked after reload by | |
2074 | the cbranchdi4_i pattern, through expand_cbranchdi4. */ | |
2075 | rtx op1 = operands[1]; | |
2076 | ||
b3a13419 | 2077 | if (can_create_pseudo_p ()) |
78d310c2 R |
2078 | operands[1] = force_reg (mode, op1); |
2079 | /* When we are handling DImode comparisons, we want to keep constants so | |
2080 | that we can optimize the component comparisons; however, memory loads | |
2081 | are better issued as a whole so that they can be scheduled well. | |
2082 | SImode equality comparisons allow I08 constants, but only when they | |
2083 | compare r0. Hence, if operands[1] has to be loaded from somewhere else | |
2084 | into a register, that register might as well be r0, and we allow the | |
2085 | constant. If it is already in a register, this is likely to be | |
2f8e468b | 2086 | allocated to a different hard register, thus we load the constant into |
78d310c2 R |
2087 | a register unless it is zero. */ |
2088 | if (!REG_P (operands[2]) | |
f3536097 | 2089 | && (!CONST_INT_P (operands[2]) |
78d310c2 R |
2090 | || (mode == SImode && operands[2] != CONST0_RTX (SImode) |
2091 | && ((comparison != EQ && comparison != NE) | |
2092 | || (REG_P (op1) && REGNO (op1) != R0_REG) | |
32a7ab3d | 2093 | || !satisfies_constraint_I08 (operands[2]))))) |
78d310c2 R |
2094 | { |
2095 | if (scratch && GET_MODE (scratch) == mode) | |
2096 | { | |
2097 | emit_move_insn (scratch, operands[2]); | |
2098 | operands[2] = scratch; | |
2099 | } | |
b3a13419 | 2100 | else if (can_create_pseudo_p ()) |
78d310c2 R |
2101 | operands[2] = force_reg (mode, operands[2]); |
2102 | } | |
2103 | return comparison; | |
2104 | } | |
2105 | ||
2106 | void | |
2107 | expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability) | |
2108 | { | |
b4eca9c8 | 2109 | rtx (*branch_expander) (rtx) = gen_branch_true; |
78d310c2 R |
2110 | comparison = prepare_cbranch_operands (operands, SImode, comparison); |
2111 | switch (comparison) | |
2112 | { | |
2113 | case NE: case LT: case LE: case LTU: case LEU: | |
2114 | comparison = reverse_condition (comparison); | |
2115 | branch_expander = gen_branch_false; | |
2116 | default: ; | |
2117 | } | |
f7df4a84 | 2118 | emit_insn (gen_rtx_SET (get_t_reg_rtx (), |
50fe8924 OE |
2119 | gen_rtx_fmt_ee (comparison, SImode, |
2120 | operands[1], operands[2]))); | |
6cb7eb41 | 2121 | rtx_insn *jump = emit_jump_insn (branch_expander (operands[3])); |
78d310c2 | 2122 | if (probability >= 0) |
e5af9ddd | 2123 | add_int_reg_note (jump, REG_BR_PROB, probability); |
78d310c2 R |
2124 | } |
2125 | ||
2126 | /* ??? How should we distribute probabilities when more than one branch | |
2eff0b9d | 2127 | is generated. So far we only have some ad-hoc observations: |
78d310c2 R |
2128 | - If the operands are random, they are likely to differ in both parts. |
2129 | - If comparing items in a hash chain, the operands are random or equal; | |
2130 | operation should be EQ or NE. | |
2131 | - If items are searched in an ordered tree from the root, we can expect | |
2132 | the highpart to be unequal about half of the time; operation should be | |
2f8e468b | 2133 | an inequality comparison, operands non-constant, and overall probability |
78d310c2 R |
2134 | about 50%. Likewise for quicksort. |
2135 | - Range checks will be often made against constants. Even if we assume for | |
2136 | simplicity an even distribution of the non-constant operand over a | |
2137 | sub-range here, the same probability could be generated with differently | |
2138 | wide sub-ranges - as long as the ratio of the part of the subrange that | |
2139 | is before the threshold to the part that comes after the threshold stays | |
2140 | the same. Thus, we can't really tell anything here; | |
2141 | assuming random distribution is at least simple. | |
2142 | */ | |
78d310c2 R |
2143 | bool |
2144 | expand_cbranchdi4 (rtx *operands, enum rtx_code comparison) | |
2145 | { | |
2146 | enum rtx_code msw_taken, msw_skip, lsw_taken; | |
6cb7eb41 | 2147 | rtx_code_label *skip_label = NULL; |
78d310c2 R |
2148 | rtx op1h, op1l, op2h, op2l; |
2149 | int num_branches; | |
2150 | int prob, rev_prob; | |
2151 | int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1; | |
6f8eec29 | 2152 | rtx scratch = operands[4]; |
78d310c2 R |
2153 | |
2154 | comparison = prepare_cbranch_operands (operands, DImode, comparison); | |
2155 | op1h = gen_highpart_mode (SImode, DImode, operands[1]); | |
2156 | op2h = gen_highpart_mode (SImode, DImode, operands[2]); | |
2157 | op1l = gen_lowpart (SImode, operands[1]); | |
2158 | op2l = gen_lowpart (SImode, operands[2]); | |
b757d36f | 2159 | msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE; |
78d310c2 R |
2160 | prob = split_branch_probability; |
2161 | rev_prob = REG_BR_PROB_BASE - prob; | |
2162 | switch (comparison) | |
2163 | { | |
2164 | /* ??? Should we use the cmpeqdi_t pattern for equality comparisons? | |
2165 | That costs 1 cycle more when the first branch can be predicted taken, | |
2166 | but saves us mispredicts because only one branch needs prediction. | |
2167 | It also enables generating the cmpeqdi_t-1 pattern. */ | |
2168 | case EQ: | |
2169 | if (TARGET_CMPEQDI_T) | |
2170 | { | |
2171 | emit_insn (gen_cmpeqdi_t (operands[1], operands[2])); | |
b4eca9c8 | 2172 | emit_jump_insn (gen_branch_true (operands[3])); |
78d310c2 R |
2173 | return true; |
2174 | } | |
2175 | msw_skip = NE; | |
2176 | lsw_taken = EQ; | |
2177 | if (prob >= 0) | |
2178 | { | |
ff596ca1 | 2179 | // If we had more precision, we'd use rev_prob - (rev_prob >> 32) . |
78d310c2 R |
2180 | msw_skip_prob = rev_prob; |
2181 | if (REG_BR_PROB_BASE <= 65535) | |
2182 | lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0; | |
2183 | else | |
2184 | { | |
78d310c2 R |
2185 | lsw_taken_prob |
2186 | = (prob | |
2187 | ? (REG_BR_PROB_BASE | |
a9243bfc RB |
2188 | - ((gcov_type) REG_BR_PROB_BASE * rev_prob |
2189 | / ((gcov_type) prob << 32))) | |
78d310c2 R |
2190 | : 0); |
2191 | } | |
2192 | } | |
2193 | break; | |
2194 | case NE: | |
2195 | if (TARGET_CMPEQDI_T) | |
2196 | { | |
2197 | emit_insn (gen_cmpeqdi_t (operands[1], operands[2])); | |
b4eca9c8 | 2198 | emit_jump_insn (gen_branch_false (operands[3])); |
78d310c2 R |
2199 | return true; |
2200 | } | |
2201 | msw_taken = NE; | |
6f8eec29 | 2202 | msw_taken_prob = prob; |
78d310c2 R |
2203 | lsw_taken = NE; |
2204 | lsw_taken_prob = 0; | |
2205 | break; | |
2206 | case GTU: case GT: | |
2207 | msw_taken = comparison; | |
f3536097 | 2208 | if (CONST_INT_P (op2l) && INTVAL (op2l) == -1) |
78d310c2 R |
2209 | break; |
2210 | if (comparison != GTU || op2h != CONST0_RTX (SImode)) | |
2211 | msw_skip = swap_condition (msw_taken); | |
2212 | lsw_taken = GTU; | |
2213 | break; | |
2214 | case GEU: case GE: | |
2215 | if (op2l == CONST0_RTX (SImode)) | |
2216 | msw_taken = comparison; | |
2217 | else | |
2218 | { | |
2219 | msw_taken = comparison == GE ? GT : GTU; | |
2220 | msw_skip = swap_condition (msw_taken); | |
2221 | lsw_taken = GEU; | |
2222 | } | |
2223 | break; | |
2224 | case LTU: case LT: | |
2225 | msw_taken = comparison; | |
2226 | if (op2l == CONST0_RTX (SImode)) | |
2227 | break; | |
2228 | msw_skip = swap_condition (msw_taken); | |
2229 | lsw_taken = LTU; | |
2230 | break; | |
2231 | case LEU: case LE: | |
f3536097 | 2232 | if (CONST_INT_P (op2l) && INTVAL (op2l) == -1) |
78d310c2 R |
2233 | msw_taken = comparison; |
2234 | else | |
2235 | { | |
2236 | lsw_taken = LEU; | |
2237 | if (comparison == LE) | |
2238 | msw_taken = LT; | |
2239 | else if (op2h != CONST0_RTX (SImode)) | |
2240 | msw_taken = LTU; | |
2241 | else | |
5f133038 KK |
2242 | { |
2243 | msw_skip = swap_condition (LTU); | |
2244 | break; | |
2245 | } | |
78d310c2 R |
2246 | msw_skip = swap_condition (msw_taken); |
2247 | } | |
2248 | break; | |
2249 | default: return false; | |
2250 | } | |
b757d36f KK |
2251 | num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE) |
2252 | + (msw_skip != LAST_AND_UNUSED_RTX_CODE) | |
2253 | + (lsw_taken != LAST_AND_UNUSED_RTX_CODE)); | |
78d310c2 R |
2254 | if (comparison != EQ && comparison != NE && num_branches > 1) |
2255 | { | |
2256 | if (!CONSTANT_P (operands[2]) | |
2257 | && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U) | |
2258 | && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U)) | |
2259 | { | |
2260 | msw_taken_prob = prob / 2U; | |
2261 | msw_skip_prob | |
2262 | = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob); | |
2263 | lsw_taken_prob = prob; | |
2264 | } | |
2265 | else | |
2266 | { | |
2267 | msw_taken_prob = prob; | |
2268 | msw_skip_prob = REG_BR_PROB_BASE; | |
2269 | /* ??? If we have a constant op2h, should we use that when | |
2270 | calculating lsw_taken_prob? */ | |
2271 | lsw_taken_prob = prob; | |
2272 | } | |
2273 | } | |
2274 | operands[1] = op1h; | |
2275 | operands[2] = op2h; | |
2276 | operands[4] = NULL_RTX; | |
6f8eec29 | 2277 | if (reload_completed |
99052692 KK |
2278 | && ! arith_reg_or_0_operand (op2h, SImode) |
2279 | && (true_regnum (op1h) || (comparison != EQ && comparison != NE)) | |
b757d36f KK |
2280 | && (msw_taken != LAST_AND_UNUSED_RTX_CODE |
2281 | || msw_skip != LAST_AND_UNUSED_RTX_CODE)) | |
6f8eec29 R |
2282 | { |
2283 | emit_move_insn (scratch, operands[2]); | |
2284 | operands[2] = scratch; | |
2285 | } | |
b757d36f | 2286 | if (msw_taken != LAST_AND_UNUSED_RTX_CODE) |
78d310c2 | 2287 | expand_cbranchsi4 (operands, msw_taken, msw_taken_prob); |
b757d36f | 2288 | if (msw_skip != LAST_AND_UNUSED_RTX_CODE) |
78d310c2 R |
2289 | { |
2290 | rtx taken_label = operands[3]; | |
2291 | ||
d60819f8 CB |
2292 | /* Operands were possibly modified, but msw_skip doesn't expect this. |
2293 | Always use the original ones. */ | |
b757d36f | 2294 | if (msw_taken != LAST_AND_UNUSED_RTX_CODE) |
d60819f8 CB |
2295 | { |
2296 | operands[1] = op1h; | |
2297 | operands[2] = op2h; | |
e95873dd KK |
2298 | if (reload_completed |
2299 | && ! arith_reg_or_0_operand (op2h, SImode) | |
2300 | && (true_regnum (op1h) || (comparison != EQ && comparison != NE))) | |
2301 | { | |
2302 | emit_move_insn (scratch, operands[2]); | |
2303 | operands[2] = scratch; | |
2304 | } | |
d60819f8 CB |
2305 | } |
2306 | ||
78d310c2 R |
2307 | operands[3] = skip_label = gen_label_rtx (); |
2308 | expand_cbranchsi4 (operands, msw_skip, msw_skip_prob); | |
2309 | operands[3] = taken_label; | |
2310 | } | |
2311 | operands[1] = op1l; | |
2312 | operands[2] = op2l; | |
b757d36f | 2313 | if (lsw_taken != LAST_AND_UNUSED_RTX_CODE) |
6f8eec29 R |
2314 | { |
2315 | if (reload_completed | |
99052692 KK |
2316 | && ! arith_reg_or_0_operand (op2l, SImode) |
2317 | && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE))) | |
2318 | { | |
2319 | emit_move_insn (scratch, operands[2]); | |
2320 | operands[2] = scratch; | |
2321 | } | |
6f8eec29 R |
2322 | expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob); |
2323 | } | |
b757d36f | 2324 | if (msw_skip != LAST_AND_UNUSED_RTX_CODE) |
78d310c2 R |
2325 | emit_label (skip_label); |
2326 | return true; | |
2327 | } | |
2328 | ||
b4eca9c8 OE |
2329 | /* Given an operand, return 1 if the evaluated operand plugged into an |
2330 | if_then_else will result in a branch_true, 0 if branch_false, or | |
2331 | -1 if neither nor applies. The truth table goes like this: | |
2332 | ||
2333 | op | cmpval | code | result | |
2334 | ---------+--------+---------+-------------------- | |
2335 | T (0) | 0 | EQ (1) | 0 = 0 ^ (0 == 1) | |
2336 | T (0) | 1 | EQ (1) | 1 = 0 ^ (1 == 1) | |
2337 | T (0) | 0 | NE (0) | 1 = 0 ^ (0 == 0) | |
2338 | T (0) | 1 | NE (0) | 0 = 0 ^ (1 == 0) | |
2339 | !T (1) | 0 | EQ (1) | 1 = 1 ^ (0 == 1) | |
2340 | !T (1) | 1 | EQ (1) | 0 = 1 ^ (1 == 1) | |
2341 | !T (1) | 0 | NE (0) | 0 = 1 ^ (0 == 0) | |
2342 | !T (1) | 1 | NE (0) | 1 = 1 ^ (1 == 0) */ | |
2343 | int | |
2344 | sh_eval_treg_value (rtx op) | |
2345 | { | |
48d8568e OE |
2346 | if (t_reg_operand (op, GET_MODE (op))) |
2347 | return 1; | |
2348 | if (negt_reg_operand (op, GET_MODE (op))) | |
2349 | return 0; | |
2350 | ||
2351 | rtx_code code = GET_CODE (op); | |
b4eca9c8 OE |
2352 | if ((code != EQ && code != NE) || !CONST_INT_P (XEXP (op, 1))) |
2353 | return -1; | |
2354 | ||
2355 | int cmpop = code == EQ ? 1 : 0; | |
2356 | int cmpval = INTVAL (XEXP (op, 1)); | |
2357 | if (cmpval != 0 && cmpval != 1) | |
2358 | return -1; | |
2359 | ||
2360 | int t; | |
2361 | if (t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))) | |
2362 | t = 0; | |
2363 | else if (negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))) | |
2364 | t = 1; | |
2365 | else | |
2366 | return -1; | |
2367 | ||
2368 | return t ^ (cmpval == cmpop); | |
2369 | } | |
2370 | ||
3a2317d1 OE |
2371 | /* Emit INSN, possibly in a PARALLEL with an USE/CLOBBER of FPSCR bits in case |
2372 | of floating-point comparisons. */ | |
f90b7a5a | 2373 | static void |
ef4bddc2 | 2374 | sh_emit_set_t_insn (rtx insn, machine_mode mode) |
f90b7a5a | 2375 | { |
3a2317d1 OE |
2376 | if (TARGET_FPU_ANY && GET_MODE_CLASS (mode) == MODE_FLOAT |
2377 | && GET_CODE (insn) != PARALLEL) | |
f90b7a5a PB |
2378 | { |
2379 | insn = gen_rtx_PARALLEL (VOIDmode, | |
3a2317d1 OE |
2380 | gen_rtvec (3, insn, |
2381 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, FPSCR_STAT_REG)), | |
2382 | gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, FPSCR_MODES_REG)))); | |
f90b7a5a | 2383 | } |
3a2317d1 | 2384 | emit_insn (insn); |
f90b7a5a PB |
2385 | } |
2386 | ||
8aa2a305 | 2387 | /* Prepare the operands for an scc instruction; make sure that the |
f90b7a5a PB |
2388 | compare has been done and the result is in T_REG. */ |
2389 | void | |
2390 | sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1) | |
8aa2a305 | 2391 | { |
78ff60c1 | 2392 | rtx t_reg = get_t_reg_rtx (); |
8aa2a305 | 2393 | enum rtx_code oldcode = code; |
ef4bddc2 | 2394 | machine_mode mode; |
8aa2a305 JW |
2395 | |
2396 | /* First need a compare insn. */ | |
2397 | switch (code) | |
bc45ade3 | 2398 | { |
8aa2a305 JW |
2399 | case NE: |
2400 | /* It isn't possible to handle this case. */ | |
f5b9e7c9 | 2401 | gcc_unreachable (); |
8aa2a305 JW |
2402 | case LT: |
2403 | code = GT; | |
2404 | break; | |
2405 | case LE: | |
2406 | code = GE; | |
2407 | break; | |
2408 | case LTU: | |
2409 | code = GTU; | |
2410 | break; | |
2411 | case LEU: | |
2412 | code = GEU; | |
2413 | break; | |
10db12e0 R |
2414 | default: |
2415 | break; | |
bc45ade3 | 2416 | } |
8aa2a305 | 2417 | if (code != oldcode) |
6f23a2d0 | 2418 | std::swap (op0, op1); |
b9654711 | 2419 | |
f90b7a5a | 2420 | mode = GET_MODE (op0); |
9374bd85 | 2421 | if (mode == VOIDmode) |
f90b7a5a | 2422 | mode = GET_MODE (op1); |
9374bd85 | 2423 | |
f90b7a5a | 2424 | op0 = force_reg (mode, op0); |
1245df60 | 2425 | if ((code != EQ && code != NE |
f90b7a5a | 2426 | && (op1 != const0_rtx |
1245df60 | 2427 | || code == GTU || code == GEU || code == LTU || code == LEU)) |
f90b7a5a | 2428 | || (mode == DImode && op1 != const0_rtx) |
3a8699c7 | 2429 | || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)) |
f90b7a5a | 2430 | op1 = force_reg (mode, op1); |
0d7e008e | 2431 | |
f7df4a84 | 2432 | sh_emit_set_t_insn (gen_rtx_SET (t_reg, |
f90b7a5a PB |
2433 | gen_rtx_fmt_ee (code, SImode, op0, op1)), |
2434 | mode); | |
2435 | } | |
0d7e008e | 2436 | |
f90b7a5a | 2437 | rtx |
ef4bddc2 | 2438 | sh_emit_cheap_store_flag (machine_mode mode, enum rtx_code code, |
f90b7a5a PB |
2439 | rtx op0, rtx op1) |
2440 | { | |
2441 | rtx target = gen_reg_rtx (SImode); | |
2442 | rtx tmp; | |
2443 | ||
2444 | gcc_assert (TARGET_SHMEDIA); | |
2445 | switch (code) | |
2446 | { | |
2447 | case EQ: | |
2448 | case GT: | |
2449 | case LT: | |
2450 | case UNORDERED: | |
2451 | case GTU: | |
2452 | case LTU: | |
2453 | tmp = gen_rtx_fmt_ee (code, SImode, op0, op1); | |
2454 | emit_insn (gen_cstore4_media (target, tmp, op0, op1)); | |
2455 | code = NE; | |
2456 | break; | |
2457 | ||
2458 | case NE: | |
2459 | case GE: | |
2460 | case LE: | |
2461 | case ORDERED: | |
2462 | case GEU: | |
2463 | case LEU: | |
2464 | tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1); | |
2465 | emit_insn (gen_cstore4_media (target, tmp, op0, op1)); | |
2466 | code = EQ; | |
2467 | break; | |
2468 | ||
2469 | case UNEQ: | |
2470 | case UNGE: | |
2471 | case UNGT: | |
2472 | case UNLE: | |
2473 | case UNLT: | |
2474 | case LTGT: | |
2475 | return NULL_RTX; | |
2476 | ||
2477 | default: | |
2478 | gcc_unreachable (); | |
2479 | } | |
2480 | ||
2481 | if (mode == DImode) | |
2482 | { | |
2483 | rtx t2 = gen_reg_rtx (DImode); | |
2484 | emit_insn (gen_extendsidi2 (t2, target)); | |
2485 | target = t2; | |
2486 | } | |
2487 | ||
2488 | return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx); | |
bc45ade3 SC |
2489 | } |
2490 | ||
8aa2a305 | 2491 | /* Called from the md file, set up the operands of a compare instruction. */ |
8aa2a305 | 2492 | void |
ef4bddc2 | 2493 | sh_emit_compare_and_branch (rtx *operands, machine_mode mode) |
bc45ade3 | 2494 | { |
f90b7a5a PB |
2495 | enum rtx_code code = GET_CODE (operands[0]); |
2496 | enum rtx_code branch_code; | |
2497 | rtx op0 = operands[1]; | |
2498 | rtx op1 = operands[2]; | |
6f23a2d0 | 2499 | rtx insn; |
f90b7a5a PB |
2500 | bool need_ccmpeq = false; |
2501 | ||
2502 | if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
bc45ade3 | 2503 | { |
f90b7a5a PB |
2504 | op0 = force_reg (mode, op0); |
2505 | op1 = force_reg (mode, op1); | |
bc45ade3 | 2506 | } |
f90b7a5a | 2507 | else |
1245df60 | 2508 | { |
f90b7a5a | 2509 | if (code != EQ || mode == DImode) |
50fe8924 OE |
2510 | { |
2511 | /* Force args into regs, since we can't use constants here. */ | |
2512 | op0 = force_reg (mode, op0); | |
2513 | if (op1 != const0_rtx || code == GTU || code == GEU) | |
f90b7a5a PB |
2514 | op1 = force_reg (mode, op1); |
2515 | } | |
1245df60 | 2516 | } |
f90b7a5a PB |
2517 | |
2518 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
2519 | { | |
2520 | if (code == LT | |
2521 | || (code == LE && TARGET_IEEE && TARGET_SH2E) | |
2522 | || (code == GE && !(TARGET_IEEE && TARGET_SH2E))) | |
2523 | { | |
6f23a2d0 | 2524 | std::swap (op0, op1); |
f90b7a5a PB |
2525 | code = swap_condition (code); |
2526 | } | |
2527 | ||
2528 | /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */ | |
2529 | if (code == GE) | |
2530 | { | |
2531 | gcc_assert (TARGET_IEEE && TARGET_SH2E); | |
50fe8924 | 2532 | need_ccmpeq = true; |
f90b7a5a PB |
2533 | code = GT; |
2534 | } | |
2535 | ||
2536 | /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed | |
2537 | to EQ/GT respectively. */ | |
2538 | gcc_assert (code == EQ || code == GT || code == NE || code == LE); | |
2539 | } | |
2540 | ||
2541 | switch (code) | |
2542 | { | |
2543 | case EQ: | |
2544 | case GT: | |
2545 | case GE: | |
2546 | case GTU: | |
2547 | case GEU: | |
2548 | branch_code = code; | |
2549 | break; | |
2550 | case NE: | |
2551 | case LT: | |
2552 | case LE: | |
2553 | case LTU: | |
2554 | case LEU: | |
2555 | branch_code = reverse_condition (code); | |
2556 | break; | |
2557 | default: | |
2558 | gcc_unreachable (); | |
2559 | } | |
2560 | ||
f7df4a84 | 2561 | insn = gen_rtx_SET (get_t_reg_rtx (), |
f90b7a5a PB |
2562 | gen_rtx_fmt_ee (branch_code, SImode, op0, op1)); |
2563 | ||
2564 | sh_emit_set_t_insn (insn, mode); | |
2565 | if (need_ccmpeq) | |
2566 | sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode); | |
2567 | ||
2568 | if (branch_code == code) | |
b4eca9c8 | 2569 | emit_jump_insn (gen_branch_true (operands[3])); |
1245df60 | 2570 | else |
b4eca9c8 | 2571 | emit_jump_insn (gen_branch_false (operands[3])); |
f90b7a5a PB |
2572 | } |
2573 | ||
2574 | void | |
ef4bddc2 | 2575 | sh_emit_compare_and_set (rtx *operands, machine_mode mode) |
f90b7a5a PB |
2576 | { |
2577 | enum rtx_code code = GET_CODE (operands[1]); | |
2578 | rtx op0 = operands[2]; | |
2579 | rtx op1 = operands[3]; | |
6cb7eb41 | 2580 | rtx_code_label *lab = NULL; |
f90b7a5a | 2581 | bool invert = false; |
f90b7a5a PB |
2582 | |
2583 | op0 = force_reg (mode, op0); | |
2584 | if ((code != EQ && code != NE | |
2585 | && (op1 != const0_rtx | |
2586 | || code == GTU || code == GEU || code == LTU || code == LEU)) | |
2587 | || (mode == DImode && op1 != const0_rtx) | |
2588 | || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)) | |
2589 | op1 = force_reg (mode, op1); | |
2590 | ||
2591 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
225e4f43 | 2592 | { |
f90b7a5a PB |
2593 | if (code == LT || code == LE) |
2594 | { | |
6f23a2d0 | 2595 | std::swap (op0, op1); |
f90b7a5a | 2596 | code = swap_condition (code); |
f90b7a5a PB |
2597 | } |
2598 | if (code == GE) | |
50fe8924 OE |
2599 | { |
2600 | if (TARGET_IEEE) | |
2601 | { | |
2602 | lab = gen_label_rtx (); | |
2603 | sh_emit_scc_to_t (EQ, op0, op1); | |
2604 | emit_jump_insn (gen_branch_true (lab)); | |
2605 | code = GT; | |
2606 | } | |
2607 | else | |
2608 | { | |
2609 | code = LT; | |
2610 | invert = true; | |
f90b7a5a | 2611 | } |
50fe8924 | 2612 | } |
225e4f43 | 2613 | } |
f90b7a5a PB |
2614 | |
2615 | if (code == NE) | |
2616 | { | |
2617 | code = EQ; | |
2618 | invert = true; | |
2619 | } | |
2620 | ||
2621 | sh_emit_scc_to_t (code, op0, op1); | |
2622 | if (lab) | |
2623 | emit_label (lab); | |
2624 | if (invert) | |
78ff60c1 | 2625 | emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ())); |
225e4f43 | 2626 | else |
78ff60c1 | 2627 | emit_move_insn (operands[0], get_t_reg_rtx ()); |
bc45ade3 SC |
2628 | } |
2629 | \f | |
16bea517 | 2630 | /* Functions to output assembly code. */ |
bc45ade3 | 2631 | |
b9654711 | 2632 | /* Return a sequence of instructions to perform DI or DF move. |
bc45ade3 | 2633 | |
b9654711 | 2634 | Since the SH cannot move a DI or DF in one instruction, we have |
16bea517 | 2635 | to take care when we see overlapping source and dest registers. */ |
318881c0 | 2636 | const char * |
cf277499 | 2637 | output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[], |
ef4bddc2 | 2638 | machine_mode mode) |
bc45ade3 | 2639 | { |
b9654711 SC |
2640 | rtx dst = operands[0]; |
2641 | rtx src = operands[1]; | |
b9654711 | 2642 | |
f3536097 | 2643 | if (MEM_P (dst) |
16bea517 | 2644 | && GET_CODE (XEXP (dst, 0)) == PRE_DEC) |
6387ab2c OE |
2645 | return "mov.l %T1,%0" "\n" |
2646 | " mov.l %1,%0"; | |
8aa2a305 | 2647 | |
b9654711 SC |
2648 | if (register_operand (dst, mode) |
2649 | && register_operand (src, mode)) | |
bc45ade3 | 2650 | { |
b9654711 | 2651 | if (REGNO (src) == MACH_REG) |
6387ab2c OE |
2652 | return "sts mach,%S0" "\n" |
2653 | " sts macl,%R0"; | |
bc45ade3 | 2654 | |
8aa2a305 JW |
2655 | /* When mov.d r1,r2 do r2->r3 then r1->r2; |
2656 | when mov.d r1,r0 do r1->r0 then r2->r1. */ | |
b9654711 | 2657 | if (REGNO (src) + 1 == REGNO (dst)) |
6387ab2c OE |
2658 | return "mov %T1,%T0" "\n" |
2659 | " mov %1,%0"; | |
b9654711 | 2660 | else |
6387ab2c OE |
2661 | return "mov %1,%0" "\n" |
2662 | " mov %T1,%T0"; | |
b9654711 | 2663 | } |
f3536097 | 2664 | else if (CONST_INT_P (src)) |
bc45ade3 | 2665 | { |
8aa2a305 JW |
2666 | if (INTVAL (src) < 0) |
2667 | output_asm_insn ("mov #-1,%S0", operands); | |
bc45ade3 | 2668 | else |
8aa2a305 | 2669 | output_asm_insn ("mov #0,%S0", operands); |
bc45ade3 | 2670 | |
8aa2a305 | 2671 | return "mov %1,%R0"; |
0d7e008e | 2672 | } |
f3536097 | 2673 | else if (MEM_P (src)) |
bc45ade3 | 2674 | { |
8aa2a305 | 2675 | int ptrreg = -1; |
b9654711 SC |
2676 | int dreg = REGNO (dst); |
2677 | rtx inside = XEXP (src, 0); | |
bc45ade3 | 2678 | |
f5b9e7c9 | 2679 | switch (GET_CODE (inside)) |
bc45ade3 | 2680 | { |
f5b9e7c9 NS |
2681 | case REG: |
2682 | ptrreg = REGNO (inside); | |
2683 | break; | |
2684 | ||
2685 | case SUBREG: | |
2686 | ptrreg = subreg_regno (inside); | |
2687 | break; | |
2688 | ||
2689 | case PLUS: | |
8aa2a305 JW |
2690 | ptrreg = REGNO (XEXP (inside, 0)); |
2691 | /* ??? A r0+REG address shouldn't be possible here, because it isn't | |
2692 | an offsettable address. Unfortunately, offsettable addresses use | |
2693 | QImode to check the offset, and a QImode offsettable address | |
2694 | requires r0 for the other operand, which is not currently | |
2695 | supported, so we can't use the 'o' constraint. | |
2696 | Thus we must check for and handle r0+REG addresses here. | |
2697 | We punt for now, since this is likely very rare. */ | |
f3536097 | 2698 | gcc_assert (!REG_P (XEXP (inside, 1))); |
f5b9e7c9 NS |
2699 | break; |
2700 | ||
2701 | case LABEL_REF: | |
6387ab2c OE |
2702 | return "mov.l %1,%0" "\n" |
2703 | " mov.l %1+4,%T0"; | |
f5b9e7c9 | 2704 | case POST_INC: |
6387ab2c OE |
2705 | return "mov.l %1,%0" "\n" |
2706 | " mov.l %1,%T0"; | |
f5b9e7c9 NS |
2707 | default: |
2708 | gcc_unreachable (); | |
bc45ade3 | 2709 | } |
bc45ade3 | 2710 | |
8aa2a305 JW |
2711 | /* Work out the safe way to copy. Copy into the second half first. */ |
2712 | if (dreg == ptrreg) | |
6387ab2c OE |
2713 | return "mov.l %T1,%T0" "\n" |
2714 | " mov.l %1,%0"; | |
bc45ade3 SC |
2715 | } |
2716 | ||
6387ab2c OE |
2717 | return "mov.l %1,%0" "\n" |
2718 | " mov.l %T1,%T0"; | |
bc45ade3 SC |
2719 | } |
2720 | ||
8aa2a305 JW |
2721 | /* Print an instruction which would have gone into a delay slot after |
2722 | another instruction, but couldn't because the other instruction expanded | |
2723 | into a sequence where putting the slot insn at the end wouldn't work. */ | |
8aa2a305 | 2724 | static void |
7fa55ff6 | 2725 | print_slot (rtx_sequence *seq) |
8aa2a305 | 2726 | { |
7fa55ff6 | 2727 | final_scan_insn (seq->insn (1), asm_out_file, optimize, 1, NULL); |
b9654711 | 2728 | |
4654c0cf | 2729 | seq->insn (1)->set_deleted (); |
8aa2a305 | 2730 | } |
0d7e008e | 2731 | |
318881c0 | 2732 | const char * |
6cb7eb41 | 2733 | output_far_jump (rtx_insn *insn, rtx op) |
0d7e008e | 2734 | { |
0a2aaacc | 2735 | struct { rtx lab, reg, op; } this_jmp; |
19f8b229 | 2736 | rtx_code_label *braf_base_lab = NULL; |
318881c0 | 2737 | const char *jump; |
1245df60 | 2738 | int far; |
9d98a694 | 2739 | int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn)); |
6cb7eb41 | 2740 | rtx_insn *prev; |
0d7e008e | 2741 | |
0a2aaacc | 2742 | this_jmp.lab = gen_label_rtx (); |
b9654711 | 2743 | |
1a953d0f R |
2744 | if (TARGET_SH2 |
2745 | && offset >= -32764 | |
4e417af3 KK |
2746 | && offset - get_attr_length (insn) <= 32766 |
2747 | && ! CROSSING_JUMP_P (insn)) | |
1245df60 R |
2748 | { |
2749 | far = 0; | |
6387ab2c OE |
2750 | jump = "mov.w %O0,%1" "\n" |
2751 | " braf %1"; | |
1245df60 R |
2752 | } |
2753 | else | |
2754 | { | |
2755 | far = 1; | |
1a66cd67 | 2756 | if (flag_pic) |
e6dfd05f AO |
2757 | { |
2758 | if (TARGET_SH2) | |
6387ab2c OE |
2759 | jump = "mov.l %O0,%1" "\n" |
2760 | " braf %1"; | |
e6dfd05f | 2761 | else |
6387ab2c OE |
2762 | jump = "mov.l r0,@-r15" "\n" |
2763 | " mova %O0,r0" "\n" | |
2764 | " mov.l @r0,%1" "\n" | |
2765 | " add r0,%1" "\n" | |
2766 | " mov.l @r15+,r0" "\n" | |
2767 | " jmp @%1"; | |
e6dfd05f | 2768 | } |
1a66cd67 | 2769 | else |
6387ab2c OE |
2770 | jump = "mov.l %O0,%1" "\n" |
2771 | " jmp @%1"; | |
1245df60 R |
2772 | } |
2773 | /* If we have a scratch register available, use it. */ | |
f3536097 | 2774 | if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn))) |
10f4f635 | 2775 | && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch) |
1245df60 | 2776 | { |
0a2aaacc KG |
2777 | this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0)); |
2778 | if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2) | |
6387ab2c OE |
2779 | jump = "mov.l r1,@-r15" "\n" |
2780 | " mova %O0,r0" "\n" | |
2781 | " mov.l @r0,r1" "\n" | |
2782 | " add r1,r0" "\n" | |
2783 | " mov.l @r15+,r1" "\n" | |
2784 | " jmp @%1"; | |
0a2aaacc | 2785 | output_asm_insn (jump, &this_jmp.lab); |
1245df60 R |
2786 | if (dbr_sequence_length ()) |
2787 | print_slot (final_sequence); | |
2788 | else | |
2789 | output_asm_insn ("nop", 0); | |
2790 | } | |
2791 | else | |
2792 | { | |
2793 | /* Output the delay slot insn first if any. */ | |
2794 | if (dbr_sequence_length ()) | |
2795 | print_slot (final_sequence); | |
2796 | ||
0a2aaacc | 2797 | this_jmp.reg = gen_rtx_REG (SImode, 13); |
fa5322fa AO |
2798 | /* We must keep the stack aligned to 8-byte boundaries on SH5. |
2799 | Fortunately, MACL is fixed and call-clobbered, and we never | |
2800 | need its value across jumps, so save r13 in it instead of in | |
2801 | the stack. */ | |
2802 | if (TARGET_SH5) | |
6387ab2c | 2803 | output_asm_insn ("lds r13,macl", 0); |
fa5322fa AO |
2804 | else |
2805 | output_asm_insn ("mov.l r13,@-r15", 0); | |
0a2aaacc | 2806 | output_asm_insn (jump, &this_jmp.lab); |
fa5322fa | 2807 | if (TARGET_SH5) |
6387ab2c | 2808 | output_asm_insn ("sts macl,r13", 0); |
fa5322fa AO |
2809 | else |
2810 | output_asm_insn ("mov.l @r15+,r13", 0); | |
1245df60 | 2811 | } |
e6dfd05f AO |
2812 | if (far && flag_pic && TARGET_SH2) |
2813 | { | |
2814 | braf_base_lab = gen_label_rtx (); | |
4977bab6 | 2815 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
e6dfd05f AO |
2816 | CODE_LABEL_NUMBER (braf_base_lab)); |
2817 | } | |
1245df60 R |
2818 | if (far) |
2819 | output_asm_insn (".align 2", 0); | |
0a2aaacc KG |
2820 | (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab)); |
2821 | this_jmp.op = op; | |
1a66cd67 | 2822 | if (far && flag_pic) |
e6dfd05f AO |
2823 | { |
2824 | if (TARGET_SH2) | |
0a2aaacc KG |
2825 | this_jmp.lab = braf_base_lab; |
2826 | output_asm_insn (".long %O2-%O0", &this_jmp.lab); | |
e6dfd05f | 2827 | } |
1a66cd67 | 2828 | else |
0a2aaacc | 2829 | output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab); |
0d7e008e SC |
2830 | return ""; |
2831 | } | |
bc45ade3 | 2832 | |
8aa2a305 JW |
2833 | /* Local label counter, used for constants in the pool and inside |
2834 | pattern branches. */ | |
8aa2a305 JW |
2835 | static int lf = 100; |
2836 | ||
2837 | /* Output code for ordinary branches. */ | |
318881c0 | 2838 | const char * |
84034c69 | 2839 | output_branch (int logic, rtx_insn *insn, rtx *operands) |
bc45ade3 | 2840 | { |
afbc5d86 | 2841 | switch (get_attr_length (insn)) |
bc45ade3 | 2842 | { |
33f7f353 JR |
2843 | case 6: |
2844 | /* This can happen if filling the delay slot has caused a forward | |
2845 | branch to exceed its range (we could reverse it, but only | |
2846 | when we know we won't overextend other branches; this should | |
2847 | best be handled by relaxation). | |
2848 | It can also happen when other condbranches hoist delay slot insn | |
1245df60 R |
2849 | from their destination, thus leading to code size increase. |
2850 | But the branch will still be in the range -4092..+4098 bytes. */ | |
33f7f353 | 2851 | if (! TARGET_RELAX) |
1245df60 | 2852 | { |
33f7f353 JR |
2853 | int label = lf++; |
2854 | /* The call to print_slot will clobber the operands. */ | |
2855 | rtx op0 = operands[0]; | |
f676971a | 2856 | |
33f7f353 JR |
2857 | /* If the instruction in the delay slot is annulled (true), then |
2858 | there is no delay slot where we can put it now. The only safe | |
2859 | place for it is after the label. final will do that by default. */ | |
f676971a | 2860 | |
33f7f353 | 2861 | if (final_sequence |
84034c69 DM |
2862 | && ! INSN_ANNULLED_BRANCH_P (final_sequence->insn (0)) |
2863 | && get_attr_length (final_sequence->insn (1))) | |
33f7f353 | 2864 | { |
afbc5d86 | 2865 | asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t", |
33f7f353 JR |
2866 | ASSEMBLER_DIALECT ? "/" : ".", label); |
2867 | print_slot (final_sequence); | |
2868 | } | |
2869 | else | |
afbc5d86 | 2870 | asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label); |
f676971a | 2871 | |
afbc5d86 R |
2872 | output_asm_insn ("bra\t%l0", &op0); |
2873 | fprintf (asm_out_file, "\tnop\n"); | |
832a3292 | 2874 | (*targetm.asm_out.internal_label) (asm_out_file, "LF", label); |
f676971a | 2875 | |
33f7f353 | 2876 | return ""; |
1245df60 | 2877 | } |
33f7f353 JR |
2878 | /* When relaxing, handle this like a short branch. The linker |
2879 | will fix it up if it still doesn't fit after relaxation. */ | |
2880 | case 2: | |
2881 | return logic ? "bt%.\t%l0" : "bf%.\t%l0"; | |
3a8699c7 AO |
2882 | |
2883 | /* These are for SH2e, in which we have to account for the | |
2884 | extra nop because of the hardware bug in annulled branches. */ | |
2885 | case 8: | |
2886 | if (! TARGET_RELAX) | |
2887 | { | |
2888 | int label = lf++; | |
2889 | ||
f5b9e7c9 NS |
2890 | gcc_assert (!final_sequence |
2891 | || !(INSN_ANNULLED_BRANCH_P | |
2892 | (XVECEXP (final_sequence, 0, 0)))); | |
3a8699c7 AO |
2893 | asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n", |
2894 | logic ? "f" : "t", | |
2895 | ASSEMBLER_DIALECT ? "/" : ".", label); | |
2896 | fprintf (asm_out_file, "\tnop\n"); | |
2897 | output_asm_insn ("bra\t%l0", operands); | |
2898 | fprintf (asm_out_file, "\tnop\n"); | |
2899 | (*targetm.asm_out.internal_label) (asm_out_file, "LF", label); | |
2900 | ||
2901 | return ""; | |
2902 | } | |
2903 | /* When relaxing, fall through. */ | |
2904 | case 4: | |
2905 | { | |
2906 | char buffer[10]; | |
f676971a | 2907 | |
3a8699c7 AO |
2908 | sprintf (buffer, "b%s%ss\t%%l0", |
2909 | logic ? "t" : "f", | |
2910 | ASSEMBLER_DIALECT ? "/" : "."); | |
2911 | output_asm_insn (buffer, &operands[0]); | |
2912 | return "nop"; | |
2913 | } | |
2914 | ||
33f7f353 | 2915 | default: |
afbc5d86 R |
2916 | /* There should be no longer branches now - that would |
2917 | indicate that something has destroyed the branches set | |
2918 | up in machine_dependent_reorg. */ | |
f5b9e7c9 | 2919 | gcc_unreachable (); |
1245df60 | 2920 | } |
1245df60 | 2921 | } |
bc45ade3 | 2922 | |
0a2aaacc | 2923 | /* Output a code sequence for INSN using TEMPL with OPERANDS; but before, |
78d310c2 R |
2924 | fill in operands 9 as a label to the successor insn. |
2925 | We try to use jump threading where possible. | |
2926 | IF CODE matches the comparison in the IF_THEN_ELSE of a following jump, | |
2927 | we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means | |
2928 | follow jmp and bt, if the address is in range. */ | |
318881c0 | 2929 | const char * |
0a2aaacc | 2930 | output_branchy_insn (enum rtx_code code, const char *templ, |
6cb7eb41 | 2931 | rtx_insn *insn, rtx *operands) |
1245df60 | 2932 | { |
6cb7eb41 | 2933 | rtx_insn *next_insn = NEXT_INSN (insn); |
79b2746a | 2934 | |
f3536097 | 2935 | if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn)) |
1245df60 R |
2936 | { |
2937 | rtx src = SET_SRC (PATTERN (next_insn)); | |
2938 | if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code) | |
2939 | { | |
2940 | /* Following branch not taken */ | |
17f385d8 DM |
2941 | rtx_code_label *lab = gen_label_rtx (); |
2942 | emit_label_after (lab, next_insn); | |
2943 | INSN_ADDRESSES_NEW (lab, | |
9d98a694 AO |
2944 | INSN_ADDRESSES (INSN_UID (next_insn)) |
2945 | + get_attr_length (next_insn)); | |
17f385d8 | 2946 | operands[9] = lab; |
0a2aaacc | 2947 | return templ; |
1245df60 R |
2948 | } |
2949 | else | |
2950 | { | |
33f7f353 | 2951 | int offset = (branch_dest (next_insn) |
9d98a694 | 2952 | - INSN_ADDRESSES (INSN_UID (next_insn)) + 4); |
33f7f353 | 2953 | if (offset >= -252 && offset <= 258) |
1245df60 R |
2954 | { |
2955 | if (GET_CODE (src) == IF_THEN_ELSE) | |
2956 | /* branch_true */ | |
2957 | src = XEXP (src, 1); | |
2958 | operands[9] = src; | |
0a2aaacc | 2959 | return templ; |
1245df60 R |
2960 | } |
2961 | } | |
bc45ade3 | 2962 | } |
17f385d8 DM |
2963 | rtx_code_label *lab = gen_label_rtx (); |
2964 | emit_label_after (lab, insn); | |
2965 | INSN_ADDRESSES_NEW (lab, | |
9d98a694 AO |
2966 | INSN_ADDRESSES (INSN_UID (insn)) |
2967 | + get_attr_length (insn)); | |
17f385d8 | 2968 | operands[9] = lab; |
0a2aaacc | 2969 | return templ; |
1245df60 | 2970 | } |
e4fa6b06 | 2971 | |
318881c0 | 2972 | const char * |
6cb7eb41 | 2973 | output_ieee_ccmpeq (rtx_insn *insn, rtx *operands) |
1245df60 | 2974 | { |
6387ab2c OE |
2975 | return output_branchy_insn (NE, "bt %l9" "\n" |
2976 | " fcmp/eq %1,%0", | |
9fd0c419 | 2977 | insn, operands); |
bc45ade3 | 2978 | } |
8e87e161 | 2979 | \f |
1bc7c5b6 | 2980 | /* Output the start of the assembler file. */ |
1bc7c5b6 | 2981 | static void |
cf277499 | 2982 | sh_file_start (void) |
bc45ade3 | 2983 | { |
1bc7c5b6 ZW |
2984 | default_file_start (); |
2985 | ||
2986 | if (TARGET_ELF) | |
2987 | /* We need to show the text section with the proper | |
2988 | attributes as in TEXT_SECTION_ASM_OP, before dwarf2out | |
0fe7abcc | 2989 | emits it without attributes in TEXT_SECTION_ASM_OP, else GAS |
1bc7c5b6 ZW |
2990 | will complain. We can teach GAS specifically about the |
2991 | default attributes for our choice of text section, but | |
2992 | then we would have to change GAS again if/when we change | |
2993 | the text section name. */ | |
2994 | fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP); | |
2995 | else | |
2996 | /* Switch to the data section so that the coffsem symbol | |
2997 | isn't in the text section. */ | |
d6b5193b | 2998 | switch_to_section (data_section); |
b9654711 | 2999 | |
8aa2a305 | 3000 | if (TARGET_LITTLE_ENDIAN) |
1bc7c5b6 | 3001 | fputs ("\t.little\n", asm_out_file); |
fa5322fa | 3002 | |
1bc7c5b6 ZW |
3003 | if (!TARGET_ELF) |
3004 | { | |
3005 | if (TARGET_SHCOMPACT) | |
3006 | fputs ("\t.mode\tSHcompact\n", asm_out_file); | |
3007 | else if (TARGET_SHMEDIA) | |
3008 | fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n", | |
3009 | TARGET_SHMEDIA64 ? 64 : 32); | |
3010 | } | |
bc45ade3 | 3011 | } |
0d7e008e | 3012 | \f |
9f3a9a08 | 3013 | /* Check if PAT includes UNSPEC_CALLER unspec pattern. */ |
9f3a9a08 | 3014 | static bool |
cf277499 | 3015 | unspec_caller_rtx_p (rtx pat) |
9f3a9a08 | 3016 | { |
dc3ba671 RS |
3017 | rtx base, offset; |
3018 | int i; | |
3019 | ||
3020 | split_const (pat, &base, &offset); | |
3021 | if (GET_CODE (base) == UNSPEC) | |
9f3a9a08 | 3022 | { |
dc3ba671 | 3023 | if (XINT (base, 1) == UNSPEC_CALLER) |
9f3a9a08 | 3024 | return true; |
dc3ba671 RS |
3025 | for (i = 0; i < XVECLEN (base, 0); i++) |
3026 | if (unspec_caller_rtx_p (XVECEXP (base, 0, i))) | |
3027 | return true; | |
9f3a9a08 | 3028 | } |
9f3a9a08 KK |
3029 | return false; |
3030 | } | |
3031 | ||
3032 | /* Indicate that INSN cannot be duplicated. This is true for insn | |
569b7f6a | 3033 | that generates a unique label. */ |
9f3a9a08 | 3034 | static bool |
ac44248e | 3035 | sh_cannot_copy_insn_p (rtx_insn *insn) |
9f3a9a08 KK |
3036 | { |
3037 | rtx pat; | |
3038 | ||
3039 | if (!reload_completed || !flag_pic) | |
3040 | return false; | |
3041 | ||
f3536097 | 3042 | if (!NONJUMP_INSN_P (insn)) |
9f3a9a08 KK |
3043 | return false; |
3044 | if (asm_noperands (insn) >= 0) | |
3045 | return false; | |
3046 | ||
3047 | pat = PATTERN (insn); | |
3048 | if (GET_CODE (pat) != SET) | |
3049 | return false; | |
3050 | pat = SET_SRC (pat); | |
3051 | ||
3052 | if (unspec_caller_rtx_p (pat)) | |
3053 | return true; | |
3054 | ||
3055 | return false; | |
3056 | } | |
3057 | \f | |
70d4736c | 3058 | /* Number of instructions used to make an arithmetic right shift by N. */ |
0b5826ac | 3059 | static const char ashiftrt_insns[] = |
16bea517 JW |
3060 | { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2}; |
3061 | ||
70d4736c OE |
3062 | /* Description of a logical left or right shift, when expanded to a sequence |
3063 | of 1/2/8/16 shifts. | |
3064 | Notice that one bit right shifts clobber the T bit. One bit left shifts | |
3065 | are done with an 'add Rn,Rm' insn and thus do not clobber the T bit. */ | |
3066 | enum | |
3067 | { | |
3068 | ASHL_CLOBBERS_T = 1 << 0, | |
3069 | LSHR_CLOBBERS_T = 1 << 1 | |
3070 | }; | |
3071 | ||
3072 | struct ashl_lshr_sequence | |
3073 | { | |
3074 | char insn_count; | |
f3101b31 | 3075 | signed char amount[6]; |
70d4736c OE |
3076 | char clobbers_t; |
3077 | }; | |
f676971a | 3078 | |
70d4736c OE |
3079 | static const struct ashl_lshr_sequence ashl_lshr_seq[32] = |
3080 | { | |
aadb5b43 | 3081 | { 0, { 0 }, 0 }, // 0 |
70d4736c OE |
3082 | { 1, { 1 }, LSHR_CLOBBERS_T }, |
3083 | { 1, { 2 }, 0 }, | |
3084 | { 2, { 2, 1 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 3085 | { 2, { 2, 2 }, 0 }, // 4 |
70d4736c OE |
3086 | { 3, { 2, 1, 2 }, LSHR_CLOBBERS_T }, |
3087 | { 3, { 2, 2, 2 }, 0 }, | |
3088 | { 4, { 2, 2, 1, 2 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 3089 | { 1, { 8 }, 0 }, // 8 |
70d4736c OE |
3090 | { 2, { 8, 1 }, LSHR_CLOBBERS_T }, |
3091 | { 2, { 8, 2 }, 0 }, | |
3092 | { 3, { 8, 1, 2 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 3093 | { 3, { 8, 2, 2 }, 0 }, // 12 |
70d4736c OE |
3094 | { 4, { 8, 2, 1, 2 }, LSHR_CLOBBERS_T }, |
3095 | { 3, { 8, -2, 8 }, 0 }, | |
3096 | { 3, { 8, -1, 8 }, ASHL_CLOBBERS_T }, | |
aadb5b43 | 3097 | { 1, { 16 }, 0 }, // 16 |
70d4736c OE |
3098 | { 2, { 16, 1 }, LSHR_CLOBBERS_T }, |
3099 | { 2, { 16, 2 }, 0 }, | |
3100 | { 3, { 16, 1, 2 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 3101 | { 3, { 16, 2, 2 }, 0 }, // 20 |
70d4736c OE |
3102 | { 4, { 16, 2, 1, 2 }, LSHR_CLOBBERS_T }, |
3103 | { 3, { 16, -2, 8 }, 0 }, | |
3104 | { 3, { 16, -1, 8 }, ASHL_CLOBBERS_T }, | |
aadb5b43 | 3105 | { 2, { 16, 8 }, 0 }, // 24 |
70d4736c OE |
3106 | { 3, { 16, 1, 8 }, LSHR_CLOBBERS_T }, |
3107 | { 3, { 16, 8, 2 }, 0 }, | |
3108 | { 4, { 16, 8, 1, 2 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 3109 | { 4, { 16, 8, 2, 2 }, 0 }, // 28 |
70d4736c OE |
3110 | { 4, { 16, -1, -2, 16 }, ASHL_CLOBBERS_T }, |
3111 | { 3, { 16, -2, 16 }, 0 }, | |
6e01d526 OE |
3112 | |
3113 | /* For a right shift by 31 a 2 insn shll-movt sequence can be used. | |
3114 | For a left shift by 31 a 2 insn and-rotl sequences can be used. | |
3115 | However, the shift-and combiner code needs this entry here to be in | |
3116 | terms of real shift insns. */ | |
70d4736c OE |
3117 | { 3, { 16, -1, 16 }, ASHL_CLOBBERS_T } |
3118 | }; | |
8d481241 | 3119 | |
70d4736c OE |
3120 | /* Individual shift amounts for shift amounts < 16, up to three highmost |
3121 | bits might be clobbered. This is typically used when combined with some | |
3122 | kind of sign or zero extension. */ | |
3123 | static const struct ashl_lshr_sequence ext_ashl_lshr_seq[32] = | |
3124 | { | |
aadb5b43 | 3125 | { 0, { 0 }, 0 }, // 0 |
70d4736c OE |
3126 | { 1, { 1 }, LSHR_CLOBBERS_T }, |
3127 | { 1, { 2 }, 0 }, | |
3128 | { 2, { 2, 1 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 3129 | { 2, { 2, 2 }, 0 }, // 4 |
70d4736c OE |
3130 | { 3, { 2, 1, 2 }, LSHR_CLOBBERS_T }, |
3131 | { 2, { 8, -2 }, 0 }, | |
3132 | { 2, { 8, -1 }, ASHL_CLOBBERS_T }, | |
aadb5b43 | 3133 | { 1, { 8 }, 0 }, // 8 |
70d4736c OE |
3134 | { 2, { 8, 1 }, LSHR_CLOBBERS_T }, |
3135 | { 2, { 8, 2 }, 0 }, | |
3136 | { 3, { 8, 1, 2 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 3137 | { 3, { 8, 2, 2 }, 0 }, // 12 |
70d4736c OE |
3138 | { 3, { 16, -2, -1 }, ASHL_CLOBBERS_T }, |
3139 | { 2, { 16, -2 }, 0 }, | |
3140 | { 2, { 16, -1 }, ASHL_CLOBBERS_T }, | |
aadb5b43 | 3141 | { 1, { 16 }, 0 }, // 16 |
70d4736c OE |
3142 | { 2, { 16, 1 }, LSHR_CLOBBERS_T }, |
3143 | { 2, { 16, 2 }, 0 }, | |
3144 | { 3, { 16, 1, 2 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 3145 | { 3, { 16, 2, 2 }, 0 }, // 20 |
70d4736c OE |
3146 | { 4, { 16, 2, 1, 2 }, LSHR_CLOBBERS_T }, |
3147 | { 3, { 16, -2, 8 }, 0 }, | |
3148 | { 3, { 16, -1, 8 }, ASHL_CLOBBERS_T }, | |
aadb5b43 | 3149 | { 2, { 16, 8 }, 0 }, // 24 |
70d4736c OE |
3150 | { 3, { 16, 1, 8 }, LSHR_CLOBBERS_T }, |
3151 | { 3, { 16, 8, 2 }, 0 }, | |
3152 | { 4, { 16, 8, 1, 2 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 3153 | { 4, { 16, 8, 2, 2 }, 0 }, // 28 |
70d4736c OE |
3154 | { 4, { 16, -1, -2, 16 }, ASHL_CLOBBERS_T }, |
3155 | { 3, { 16, -2, 16 }, 0 }, | |
3156 | { 3, { 16, -1, 16 }, ASHL_CLOBBERS_T } | |
3157 | }; | |
3158 | ||
3159 | /* Return true if a shift left consisting of 1/2/8/16 shift instructions | |
3160 | will clobber the T bit. */ | |
3161 | bool | |
3162 | sh_ashlsi_clobbers_t_reg_p (rtx shift_amount) | |
3163 | { | |
3164 | gcc_assert (CONST_INT_P (shift_amount)); | |
6e01d526 OE |
3165 | |
3166 | const int shift_amount_i = INTVAL (shift_amount) & 31; | |
3167 | ||
3168 | /* Special case for shift count of 31: use and-rotl sequence. */ | |
3169 | if (shift_amount_i == 31) | |
3170 | return true; | |
3171 | ||
3172 | return (ashl_lshr_seq[shift_amount_i].clobbers_t | |
70d4736c OE |
3173 | & ASHL_CLOBBERS_T) != 0; |
3174 | } | |
8d481241 | 3175 | |
50fe8924 OE |
3176 | /* Return true if a logical right shift consisting of 1/2/8/16 shift |
3177 | instructions will clobber the T bit. */ | |
5592815a OE |
3178 | bool |
3179 | sh_lshrsi_clobbers_t_reg_p (rtx shift_amount) | |
3180 | { | |
3181 | gcc_assert (CONST_INT_P (shift_amount)); | |
6e01d526 OE |
3182 | |
3183 | const int shift_amount_i = INTVAL (shift_amount) & 31; | |
3184 | ||
3185 | /* Special case for shift count of 31: use shll-movt sequence. */ | |
3186 | if (shift_amount_i == 31) | |
3187 | return true; | |
3188 | ||
3189 | return (ashl_lshr_seq[shift_amount_i].clobbers_t | |
5592815a OE |
3190 | & LSHR_CLOBBERS_T) != 0; |
3191 | } | |
3192 | ||
6e01d526 OE |
3193 | /* Return true if it is potentially beneficial to use a dynamic shift |
3194 | instruction (shad / shar) instead of a combination of 1/2/8/16 | |
3195 | shift instructions for the specified shift count. | |
3196 | If dynamic shifts are not available, always return false. */ | |
3197 | bool | |
3198 | sh_dynamicalize_shift_p (rtx count) | |
3199 | { | |
3200 | gcc_assert (CONST_INT_P (count)); | |
3201 | ||
3202 | const int shift_amount_i = INTVAL (count) & 31; | |
3203 | int insn_count; | |
3204 | ||
3205 | /* For left and right shifts, there are shorter 2 insn sequences for | |
3206 | shift amounts of 31. */ | |
3207 | if (shift_amount_i == 31) | |
3208 | insn_count = 2; | |
3209 | else | |
3210 | insn_count = ashl_lshr_seq[shift_amount_i].insn_count; | |
3211 | ||
3212 | return TARGET_DYNSHIFT && (insn_count > 1 + SH_DYNAMIC_SHIFT_COST); | |
3213 | } | |
3214 | ||
ae9d19c0 | 3215 | /* Assuming we have a value that has been sign-extended by at least one bit, |
50fe8924 OE |
3216 | can we use the ext_shift_amounts with the last shift turned to an |
3217 | arithmetic shift to shift it by N without data loss, and quicker than by | |
3218 | other means? */ | |
ae9d19c0 JR |
3219 | #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15) |
3220 | ||
16bea517 | 3221 | /* Return the cost of a shift. */ |
3c50106f | 3222 | static inline int |
cf277499 | 3223 | shiftcosts (rtx x) |
bc45ade3 | 3224 | { |
3d422cb1 | 3225 | int value; |
8aa2a305 | 3226 | |
fa5322fa | 3227 | if (TARGET_SHMEDIA) |
ebe0dd38 | 3228 | return 1; |
fa5322fa | 3229 | |
c762ab6e R |
3230 | if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) |
3231 | { | |
3232 | if (GET_MODE (x) == DImode | |
f3536097 | 3233 | && CONST_INT_P (XEXP (x, 1)) |
c762ab6e | 3234 | && INTVAL (XEXP (x, 1)) == 1) |
ebe0dd38 | 3235 | return 2; |
c762ab6e R |
3236 | |
3237 | /* Everything else is invalid, because there is no pattern for it. */ | |
ebe0dd38 | 3238 | return -1; |
c762ab6e | 3239 | } |
16bea517 | 3240 | /* If shift by a non constant, then this will be expensive. */ |
f3536097 | 3241 | if (!CONST_INT_P (XEXP (x, 1))) |
ebe0dd38 | 3242 | return SH_DYNAMIC_SHIFT_COST; |
bc45ade3 | 3243 | |
6c34a092 PB |
3244 | /* Otherwise, return the true cost in instructions. Cope with out of range |
3245 | shift counts more or less arbitrarily. */ | |
3246 | value = INTVAL (XEXP (x, 1)) & 31; | |
3d422cb1 | 3247 | |
8aa2a305 | 3248 | if (GET_CODE (x) == ASHIFTRT) |
49b6d06b JW |
3249 | { |
3250 | int cost = ashiftrt_insns[value]; | |
ebe0dd38 OE |
3251 | /* If dynamic shifts are available and profitable in this case, then we |
3252 | put the constant in a reg and use shad. */ | |
1245df60 R |
3253 | if (cost > 1 + SH_DYNAMIC_SHIFT_COST) |
3254 | cost = 1 + SH_DYNAMIC_SHIFT_COST; | |
ebe0dd38 | 3255 | return cost; |
49b6d06b | 3256 | } |
8aa2a305 | 3257 | else |
70d4736c | 3258 | return ashl_lshr_seq[value].insn_count; |
0d7e008e | 3259 | } |
b9654711 | 3260 | |
b7cf894f | 3261 | /* Return the cost of an AND/XOR/IOR operation. */ |
3c50106f | 3262 | static inline int |
b7cf894f | 3263 | and_xor_ior_costs (rtx x, int code) |
0d7e008e | 3264 | { |
0f9a3fd3 OE |
3265 | /* On SH1-4 we have only max. SImode operations. |
3266 | Double the cost for modes > SImode. */ | |
3267 | const int cost_scale = !TARGET_SHMEDIA | |
3268 | && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD | |
3269 | ? 2 : 1; | |
8aa2a305 | 3270 | |
b7cf894f OE |
3271 | /* A logical operation with two registers is a single cycle |
3272 | instruction. */ | |
f3536097 | 3273 | if (!CONST_INT_P (XEXP (x, 1))) |
0f9a3fd3 | 3274 | return 1 * cost_scale; |
8aa2a305 | 3275 | |
0f9a3fd3 | 3276 | int i = INTVAL (XEXP (x, 1)); |
fa5322fa AO |
3277 | |
3278 | if (TARGET_SHMEDIA) | |
3279 | { | |
32a7ab3d KK |
3280 | if (satisfies_constraint_I10 (XEXP (x, 1)) |
3281 | || satisfies_constraint_J16 (XEXP (x, 1))) | |
fa5322fa AO |
3282 | return 1; |
3283 | else | |
e548c9df | 3284 | return 1 + rtx_cost (XEXP (x, 1), GET_MODE (x), AND, 1, !optimize_size); |
fa5322fa AO |
3285 | } |
3286 | ||
a6f71af5 | 3287 | /* These constants are single cycle extu.[bw] instructions. */ |
b7cf894f | 3288 | if ((i == 0xff || i == 0xffff) && code == AND) |
0f9a3fd3 | 3289 | return 1 * cost_scale; |
b7cf894f OE |
3290 | /* Constants that can be used in an instruction as an immediate are |
3291 | a single cycle, but this requires r0, so make it a little more | |
3292 | expensive. */ | |
735cb76e | 3293 | if (CONST_OK_FOR_K08 (i)) |
0f9a3fd3 | 3294 | return 2 * cost_scale; |
b7cf894f | 3295 | /* Constants that can be loaded with a mov immediate need one more cycle. |
a6f71af5 | 3296 | This case is probably unnecessary. */ |
735cb76e | 3297 | if (CONST_OK_FOR_I08 (i)) |
0f9a3fd3 | 3298 | return 2 * cost_scale; |
b7cf894f | 3299 | /* Any other constant requires an additional 2 cycle pc-relative load. |
a6f71af5 | 3300 | This case is probably unnecessary. */ |
0f9a3fd3 | 3301 | return 3 * cost_scale; |
0d7e008e | 3302 | } |
d3ae8277 | 3303 | |
630c79be | 3304 | /* Return the cost of an addition or a subtraction. */ |
3c50106f | 3305 | static inline int |
cf277499 | 3306 | addsubcosts (rtx x) |
630c79be | 3307 | { |
dd331dd0 OE |
3308 | if (GET_MODE (x) == SImode) |
3309 | { | |
3310 | /* The addc or subc patterns will eventually become one or two | |
3311 | instructions. Below are some costs for some of the patterns | |
3312 | which combine would reject because the costs of the individual | |
3313 | insns in the patterns are lower. | |
3314 | ||
3315 | FIXME: It would be much easier if we had something like insn cost | |
3316 | attributes and the cost calculation machinery used those attributes | |
3317 | in the first place. This would eliminate redundant recog-like C | |
3318 | code to calculate costs of complex patterns. */ | |
3319 | rtx op0 = XEXP (x, 0); | |
3320 | rtx op1 = XEXP (x, 1); | |
3321 | ||
3322 | if (GET_CODE (x) == PLUS) | |
3323 | { | |
3324 | if (GET_CODE (op0) == AND | |
3325 | && XEXP (op0, 1) == const1_rtx | |
3326 | && (GET_CODE (op1) == PLUS | |
3327 | || (GET_CODE (op1) == MULT && XEXP (op1, 1) == const2_rtx))) | |
3328 | return 1; | |
3329 | ||
3330 | if (GET_CODE (op0) == MULT && XEXP (op0, 1) == const2_rtx | |
3331 | && GET_CODE (op1) == LSHIFTRT | |
3332 | && CONST_INT_P (XEXP (op1, 1)) && INTVAL (XEXP (op1, 1)) == 31) | |
3333 | return 1; | |
3334 | } | |
841dbf80 OE |
3335 | /* Let's assume that adding the result of an insns that stores into |
3336 | the T bit is cheap. */ | |
3337 | if (treg_set_expr (op1, SImode)) | |
3338 | return 1; | |
3339 | if (treg_set_expr (op0, SImode)) | |
3340 | return 1; | |
dd331dd0 OE |
3341 | } |
3342 | ||
0f9a3fd3 OE |
3343 | /* On SH1-4 we have only max. SImode operations. |
3344 | Double the cost for modes > SImode. */ | |
3345 | const int cost_scale = !TARGET_SHMEDIA | |
3346 | && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD | |
3347 | ? 2 : 1; | |
3348 | ||
630c79be | 3349 | /* Adding a register is a single cycle insn. */ |
f3536097 | 3350 | if (REG_P (XEXP (x, 1)) |
50ceefc2 | 3351 | || GET_CODE (XEXP (x, 1)) == SUBREG) |
0f9a3fd3 | 3352 | return 1 * cost_scale; |
630c79be BS |
3353 | |
3354 | /* Likewise for small constants. */ | |
f3536097 | 3355 | if (CONST_INT_P (XEXP (x, 1)) |
fa5322fa | 3356 | && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1)))) |
0f9a3fd3 | 3357 | return 1 * cost_scale; |
630c79be | 3358 | |
fa5322fa AO |
3359 | if (TARGET_SHMEDIA) |
3360 | switch (GET_CODE (XEXP (x, 1))) | |
3361 | { | |
3362 | case CONST: | |
3363 | case LABEL_REF: | |
3364 | case SYMBOL_REF: | |
3365 | return TARGET_SHMEDIA64 ? 5 : 3; | |
3366 | ||
3367 | case CONST_INT: | |
735cb76e | 3368 | if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)))) |
50fe8924 | 3369 | return 2; |
735cb76e | 3370 | else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16)) |
fa5322fa | 3371 | return 3; |
735cb76e | 3372 | else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16)) |
fa5322fa AO |
3373 | return 4; |
3374 | ||
3375 | /* Fall through. */ | |
3376 | default: | |
832a3292 | 3377 | return 5; |
fa5322fa AO |
3378 | } |
3379 | ||
630c79be BS |
3380 | /* Any other constant requires a 2 cycle pc-relative load plus an |
3381 | addition. */ | |
0f9a3fd3 | 3382 | return 3 * cost_scale; |
630c79be BS |
3383 | } |
3384 | ||
16bea517 | 3385 | /* Return the cost of a multiply. */ |
3c50106f | 3386 | static inline int |
cf277499 | 3387 | multcosts (rtx x ATTRIBUTE_UNUSED) |
0d7e008e | 3388 | { |
7dd2f19b RS |
3389 | if (sh_multcost >= 0) |
3390 | return sh_multcost; | |
fa5322fa | 3391 | if (TARGET_SHMEDIA) |
73a4d10b R |
3392 | /* ??? We have a mul insn, but it has a latency of three, and doesn't |
3393 | accept constants. Ideally, we would use a cost of one or two and | |
3394 | add the cost of the operand, but disregard the latter when inside loops | |
3395 | and loop invariant code motion is still to follow. | |
3396 | Using a multiply first and splitting it later if it's a loss | |
3397 | doesn't work because of different sign / zero extension semantics | |
3398 | of multiplies vs. shifts. */ | |
3020190e | 3399 | return optimize_size ? 2 : 3; |
fa5322fa | 3400 | |
0d7e008e | 3401 | if (TARGET_SH2) |
d3ae8277 SC |
3402 | { |
3403 | /* We have a mul insn, so we can never take more than the mul and the | |
a7771f78 | 3404 | read of the mac reg, but count more because of the latency and extra |
16bea517 | 3405 | reg usage. */ |
3020190e | 3406 | if (optimize_size) |
8e87e161 | 3407 | return 2; |
a7771f78 | 3408 | return 3; |
d3ae8277 SC |
3409 | } |
3410 | ||
a7771f78 | 3411 | /* If we're aiming at small code, then just count the number of |
16bea517 | 3412 | insns in a multiply call sequence. */ |
3020190e | 3413 | if (optimize_size) |
8aa2a305 | 3414 | return 5; |
d3ae8277 | 3415 | |
16bea517 | 3416 | /* Otherwise count all the insns in the routine we'd be calling too. */ |
d3ae8277 | 3417 | return 20; |
0d7e008e | 3418 | } |
b9654711 | 3419 | |
3c50106f RH |
3420 | /* Compute a (partial) cost for rtx X. Return true if the complete |
3421 | cost has been computed, and false if subexpressions should be | |
3422 | scanned. In either case, *TOTAL contains the cost result. */ | |
3c50106f | 3423 | static bool |
e548c9df AM |
3424 | sh_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code, |
3425 | int opno ATTRIBUTE_UNUSED, | |
68f932c4 | 3426 | int *total, bool speed ATTRIBUTE_UNUSED) |
3c50106f | 3427 | { |
e548c9df AM |
3428 | int code = GET_CODE (x); |
3429 | ||
3c50106f RH |
3430 | switch (code) |
3431 | { | |
0345d1dd OE |
3432 | /* The lower-subreg pass decides whether to split multi-word regs |
3433 | into individual regs by looking at the cost for a SET of certain | |
3434 | modes with the following patterns: | |
3435 | (set (reg) (reg)) | |
3436 | (set (reg) (const_int 0)) | |
3437 | On machines that support vector-move operations a multi-word move | |
3438 | is the same cost as individual reg move. On SH there is no | |
3439 | vector-move, so we have to provide the correct cost in the number | |
3440 | of move insns to load/store the reg of the mode in question. */ | |
3441 | case SET: | |
3442 | if (register_operand (SET_DEST (x), VOIDmode) | |
3443 | && (register_operand (SET_SRC (x), VOIDmode) | |
3444 | || satisfies_constraint_Z (SET_SRC (x)))) | |
3445 | { | |
ef4bddc2 | 3446 | const machine_mode mode = GET_MODE (SET_DEST (x)); |
0345d1dd OE |
3447 | *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) |
3448 | / mov_insn_size (mode, TARGET_SH2A)); | |
3449 | return true; | |
3450 | } | |
3451 | return false; | |
3452 | ||
8385420c OE |
3453 | /* The cost of a mem access is mainly the cost of the address mode. */ |
3454 | case MEM: | |
3455 | *total = sh_address_cost (XEXP (x, 0), GET_MODE (x), MEM_ADDR_SPACE (x), | |
3456 | true); | |
3457 | return true; | |
3458 | ||
841dbf80 OE |
3459 | case IF_THEN_ELSE: |
3460 | /* This case is required for the if_then_else negc pattern. */ | |
3461 | if (treg_set_expr (XEXP (x, 0), SImode)) | |
3462 | { | |
3463 | *total = COSTS_N_INSNS (1); | |
3464 | return true; | |
3465 | } | |
3466 | else | |
3467 | return false; | |
3468 | ||
3469 | /* Zero extracts of single bits are usually combine patterns for the | |
3470 | tst insns. */ | |
3471 | case ZERO_EXTRACT: | |
3472 | if (GET_CODE (XEXP (x, 0)) == XOR | |
3473 | && arith_reg_operand (XEXP (XEXP (x, 0), 0), VOIDmode) | |
3474 | && XEXP (x, 1) == const1_rtx | |
3475 | && CONST_INT_P (XEXP (x, 2)) | |
3476 | && CONST_INT_P (XEXP (XEXP (x, 0), 1)) | |
3477 | /* Check that the xor constaint overlaps with the extracted bit. */ | |
3478 | && (INTVAL (XEXP (XEXP (x, 0), 1)) & (1LL << INTVAL (XEXP (x, 2))))) | |
3479 | { | |
3480 | *total = 1; //COSTS_N_INSNS (1); | |
3481 | return true; | |
3482 | } | |
3483 | return false; | |
3484 | ||
8385420c OE |
3485 | /* The cost of a sign or zero extend depends on whether the source is a |
3486 | reg or a mem. In case of a mem take the address into acount. */ | |
3487 | case SIGN_EXTEND: | |
841dbf80 | 3488 | if (arith_reg_operand (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) |
8385420c OE |
3489 | { |
3490 | *total = COSTS_N_INSNS (1); | |
3491 | return true; | |
3492 | } | |
3493 | if (MEM_P (XEXP (x, 0))) | |
3494 | { | |
3495 | *total = sh_address_cost (XEXP (XEXP (x, 0), 0), | |
3496 | GET_MODE (XEXP (x, 0)), | |
3497 | MEM_ADDR_SPACE (XEXP (x, 0)), true); | |
3498 | return true; | |
3499 | } | |
3500 | return false; | |
3501 | ||
3502 | case ZERO_EXTEND: | |
841dbf80 | 3503 | if (arith_reg_operand (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) |
8385420c OE |
3504 | { |
3505 | *total = COSTS_N_INSNS (1); | |
3506 | return true; | |
3507 | } | |
3508 | else if (TARGET_SH2A && MEM_P (XEXP (x, 0)) | |
3509 | && (GET_MODE (XEXP (x, 0)) == QImode | |
3510 | || GET_MODE (XEXP (x, 0)) == HImode)) | |
3511 | { | |
3512 | /* Handle SH2A's movu.b and movu.w insn. */ | |
3513 | *total = sh_address_cost (XEXP (XEXP (x, 0), 0), | |
3514 | GET_MODE (XEXP (x, 0)), | |
3515 | MEM_ADDR_SPACE (XEXP (x, 0)), true); | |
3516 | return true; | |
3517 | } | |
3518 | return false; | |
3519 | ||
3520 | /* mems for SFmode and DFmode can be inside a parallel due to | |
3521 | the way the fpscr is handled. */ | |
3522 | case PARALLEL: | |
3523 | for (int i = 0; i < XVECLEN (x, 0); i++) | |
3524 | { | |
3525 | rtx xx = XVECEXP (x, 0, i); | |
3526 | if (GET_CODE (xx) == SET && MEM_P (XEXP (xx, 0))) | |
3527 | { | |
3528 | *total = sh_address_cost (XEXP (XEXP (xx, 0), 0), | |
3529 | GET_MODE (XEXP (xx, 0)), | |
3530 | MEM_ADDR_SPACE (XEXP (xx, 0)), true); | |
3531 | return true; | |
3532 | } | |
3533 | if (GET_CODE (xx) == SET && MEM_P (XEXP (xx, 1))) | |
3534 | { | |
3535 | *total = sh_address_cost (XEXP (XEXP (xx, 1), 0), | |
3536 | GET_MODE (XEXP (xx, 1)), | |
3537 | MEM_ADDR_SPACE (XEXP (xx, 1)), true); | |
3538 | return true; | |
3539 | } | |
3540 | } | |
3541 | ||
3542 | if (sh_1el_vec (x, VOIDmode)) | |
3543 | *total = outer_code != SET; | |
3544 | else if (sh_rep_vec (x, VOIDmode)) | |
3545 | *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4 | |
3546 | + (outer_code != SET)); | |
3547 | else | |
3548 | *total = COSTS_N_INSNS (3) + (outer_code != SET); | |
3549 | return true; | |
3550 | ||
3c50106f RH |
3551 | case CONST_INT: |
3552 | if (TARGET_SHMEDIA) | |
50fe8924 | 3553 | { |
3c50106f RH |
3554 | if (INTVAL (x) == 0) |
3555 | *total = 0; | |
3556 | else if (outer_code == AND && and_operand ((x), DImode)) | |
3557 | *total = 0; | |
3558 | else if ((outer_code == IOR || outer_code == XOR | |
3559 | || outer_code == PLUS) | |
735cb76e | 3560 | && CONST_OK_FOR_I10 (INTVAL (x))) |
3c50106f | 3561 | *total = 0; |
735cb76e | 3562 | else if (CONST_OK_FOR_I16 (INTVAL (x))) |
50fe8924 | 3563 | *total = COSTS_N_INSNS (outer_code != SET); |
735cb76e | 3564 | else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16)) |
73a4d10b | 3565 | *total = COSTS_N_INSNS ((outer_code != SET) + 1); |
735cb76e | 3566 | else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16)) |
42201282 | 3567 | *total = COSTS_N_INSNS ((outer_code != SET) + 2); |
50fe8924 | 3568 | else |
42201282 | 3569 | *total = COSTS_N_INSNS ((outer_code != SET) + 3); |
3c50106f | 3570 | return true; |
50fe8924 | 3571 | } |
735cb76e | 3572 | if (CONST_OK_FOR_I08 (INTVAL (x))) |
3c50106f RH |
3573 | *total = 0; |
3574 | else if ((outer_code == AND || outer_code == IOR || outer_code == XOR) | |
735cb76e | 3575 | && CONST_OK_FOR_K08 (INTVAL (x))) |
3c50106f | 3576 | *total = 1; |
78d310c2 | 3577 | /* prepare_cmp_insn will force costly constants int registers before |
35912544 | 3578 | the cbranch[sd]i4 patterns can see them, so preserve potentially |
78d310c2 R |
3579 | interesting ones not covered by I08 above. */ |
3580 | else if (outer_code == COMPARE | |
3581 | && ((unsigned HOST_WIDE_INT) INTVAL (x) | |
3582 | == (unsigned HOST_WIDE_INT) 0x7fffffff + 1 | |
3583 | || INTVAL (x) == 0x7fffffff | |
3584 | || INTVAL (x) == 0x80 || INTVAL (x) == -0x81)) | |
3585 | *total = 1; | |
3c50106f RH |
3586 | else |
3587 | *total = 8; | |
3588 | return true; | |
3589 | ||
6ff9d294 OE |
3590 | case EQ: |
3591 | /* An and with a constant compared against zero is | |
3592 | most likely going to be a TST #imm, R0 instruction. | |
3593 | Notice that this does not catch the zero_extract variants from | |
3594 | the md file. */ | |
841dbf80 OE |
3595 | if (XEXP (x, 1) == const0_rtx |
3596 | && (GET_CODE (XEXP (x, 0)) == AND | |
3597 | || (SUBREG_P (XEXP (x, 0)) | |
3598 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == AND))) | |
3599 | { | |
3600 | *total = 1; | |
3601 | return true; | |
3602 | } | |
3603 | ||
3604 | else if (XEXP (x, 1) == const0_rtx | |
3605 | && GET_CODE (XEXP (x, 0)) == AND | |
3606 | && CONST_INT_P (XEXP (XEXP (x, 0), 1)) | |
3607 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT | |
3608 | && arith_reg_operand (XEXP (XEXP (XEXP (x, 0), 0), 0), SImode) | |
3609 | && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))) | |
6ff9d294 OE |
3610 | { |
3611 | *total = 1; | |
3612 | return true; | |
2353515d OE |
3613 | } |
3614 | else | |
3615 | return false; | |
3616 | ||
3617 | case SMIN: | |
3618 | case SMAX: | |
3619 | /* This is most likely a clips.b or clips.w insn that is being made up | |
3620 | by combine. */ | |
3621 | if (TARGET_SH2A | |
3622 | && (GET_CODE (XEXP (x, 0)) == SMAX || GET_CODE (XEXP (x, 0)) == SMIN) | |
3623 | && CONST_INT_P (XEXP (XEXP (x, 0), 1)) | |
3624 | && REG_P (XEXP (XEXP (x, 0), 0)) | |
3625 | && CONST_INT_P (XEXP (x, 1))) | |
3626 | { | |
3627 | *total = COSTS_N_INSNS (1); | |
3628 | return true; | |
6ff9d294 OE |
3629 | } |
3630 | else | |
3631 | return false; | |
3632 | ||
3c50106f RH |
3633 | case CONST: |
3634 | case LABEL_REF: | |
3635 | case SYMBOL_REF: | |
3636 | if (TARGET_SHMEDIA64) | |
50fe8924 | 3637 | *total = COSTS_N_INSNS (4); |
3c50106f | 3638 | else if (TARGET_SHMEDIA32) |
50fe8924 | 3639 | *total = COSTS_N_INSNS (2); |
3c50106f RH |
3640 | else |
3641 | *total = 5; | |
3642 | return true; | |
3643 | ||
3644 | case CONST_DOUBLE: | |
3645 | if (TARGET_SHMEDIA) | |
50fe8924 | 3646 | *total = COSTS_N_INSNS (4); |
78d310c2 | 3647 | /* prepare_cmp_insn will force costly constants int registers before |
35912544 | 3648 | the cbranchdi4 pattern can see them, so preserve potentially |
78d310c2 R |
3649 | interesting ones. */ |
3650 | else if (outer_code == COMPARE && GET_MODE (x) == DImode) | |
50fe8924 | 3651 | *total = 1; |
3c50106f | 3652 | else |
50fe8924 | 3653 | *total = 10; |
3c50106f | 3654 | return true; |
8385420c | 3655 | |
73a4d10b | 3656 | case CONST_VECTOR: |
8385420c OE |
3657 | /* FIXME: This looks broken. Only the last statement has any effect. |
3658 | Probably this could be folded with the PARALLEL case? */ | |
73a4d10b R |
3659 | if (x == CONST0_RTX (GET_MODE (x))) |
3660 | *total = 0; | |
3661 | else if (sh_1el_vec (x, VOIDmode)) | |
3662 | *total = outer_code != SET; | |
3663 | if (sh_rep_vec (x, VOIDmode)) | |
3664 | *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4 | |
3665 | + (outer_code != SET)); | |
3666 | *total = COSTS_N_INSNS (3) + (outer_code != SET); | |
3667 | return true; | |
3c50106f RH |
3668 | |
3669 | case PLUS: | |
73a4d10b | 3670 | case MINUS: |
3c50106f RH |
3671 | *total = COSTS_N_INSNS (addsubcosts (x)); |
3672 | return true; | |
3673 | ||
3674 | case AND: | |
841dbf80 OE |
3675 | /* Check for (and (not (reg)) (const_int 1)) which is a tst insn. */ |
3676 | if (GET_CODE (XEXP (x, 0)) == NOT && XEXP (x, 1) == const1_rtx) | |
3677 | { | |
3678 | *total = COSTS_N_INSNS (1); | |
3679 | return true; | |
3680 | } | |
3681 | /* Fall through. */ | |
3682 | ||
b7cf894f OE |
3683 | case XOR: |
3684 | case IOR: | |
3685 | *total = COSTS_N_INSNS (and_xor_ior_costs (x, code)); | |
3c50106f RH |
3686 | return true; |
3687 | ||
3688 | case MULT: | |
3689 | *total = COSTS_N_INSNS (multcosts (x)); | |
3690 | return true; | |
3691 | ||
669d4d70 OE |
3692 | case LT: |
3693 | case GE: | |
3694 | /* div0s sign comparison. */ | |
3695 | if (GET_CODE (XEXP (x, 0)) == XOR | |
3696 | && REG_P ((XEXP (XEXP (x, 0), 0))) | |
3697 | && REG_P ((XEXP (XEXP (x, 0), 1))) | |
3698 | && satisfies_constraint_Z (XEXP (x, 1))) | |
3699 | { | |
3700 | *total = COSTS_N_INSNS (1); | |
3701 | return true; | |
3702 | } | |
3703 | else | |
3704 | return false; | |
3705 | ||
3706 | case LSHIFTRT: | |
3707 | /* div0s sign comparison. */ | |
3708 | if (GET_CODE (XEXP (x, 0)) == XOR | |
3709 | && REG_P ((XEXP (XEXP (x, 0), 0))) | |
3710 | && REG_P ((XEXP (XEXP (x, 0), 1))) | |
3711 | && CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 31) | |
3712 | { | |
3713 | *total = COSTS_N_INSNS (1); | |
3714 | return true; | |
3715 | } | |
3716 | /* Fall through to shiftcosts. */ | |
3c50106f RH |
3717 | case ASHIFT: |
3718 | case ASHIFTRT: | |
ebe0dd38 OE |
3719 | { |
3720 | int cost = shiftcosts (x); | |
3721 | if (cost < 0) | |
3722 | return false; | |
3723 | *total = COSTS_N_INSNS (cost); | |
3724 | return true; | |
3725 | } | |
3c50106f RH |
3726 | |
3727 | case DIV: | |
3728 | case UDIV: | |
3729 | case MOD: | |
3730 | case UMOD: | |
3731 | *total = COSTS_N_INSNS (20); | |
3732 | return true; | |
3733 | ||
3734 | case FLOAT: | |
3735 | case FIX: | |
3736 | *total = 100; | |
3737 | return true; | |
3738 | ||
3739 | default: | |
3740 | return false; | |
3741 | } | |
3742 | } | |
3743 | ||
9b9ad23f OE |
3744 | /* Determine the size of the fundamental move insn that will be used |
3745 | for the specified mode. */ | |
9b9ad23f | 3746 | static inline int |
ef4bddc2 | 3747 | mov_insn_size (machine_mode mode, bool consider_sh2a) |
9b9ad23f OE |
3748 | { |
3749 | const int mode_sz = GET_MODE_SIZE (mode); | |
3750 | ||
3751 | if ((consider_sh2a && TARGET_SH2A_DOUBLE && mode == DFmode) | |
3752 | || (TARGET_FMOVD && mode == DFmode)) | |
3753 | return mode_sz; | |
3754 | else | |
3755 | { | |
3756 | /* The max. available mode for actual move insns is SImode. | |
3757 | Larger accesses will be split into multiple loads/stores. */ | |
3758 | const int max_mov_sz = GET_MODE_SIZE (SImode); | |
3759 | return mode_sz >= max_mov_sz ? max_mov_sz : mode_sz; | |
3760 | } | |
3761 | } | |
3762 | ||
3763 | /* Determine the maximum possible displacement for a move insn for the | |
3764 | specified mode. */ | |
91f65b12 OE |
3765 | int |
3766 | sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a) | |
dcefdf67 | 3767 | { |
9b9ad23f OE |
3768 | /* The 4 byte displacement move insns are the same as the 2 byte |
3769 | versions but take a 12 bit displacement. All we need to do is to | |
3770 | scale the max. displacement value accordingly. */ | |
3771 | const int disp_scale = consider_sh2a ? (4095 / 15) : 1; | |
3772 | ||
9b9ad23f OE |
3773 | /* SH2A supports FPU move insns with 12 bit displacements. |
3774 | Other variants to do not support any kind of displacements for | |
3775 | FPU move insns. */ | |
3776 | if (! consider_sh2a && TARGET_FPU_ANY && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3777 | return 0; | |
3778 | else | |
3779 | { | |
3780 | const int mov_insn_sz = mov_insn_size (mode, consider_sh2a); | |
3781 | const int mode_sz = GET_MODE_SIZE (mode); | |
3782 | int r = 15 * mov_insn_sz * disp_scale; | |
3783 | ||
3784 | /* If the mov insn will be split into multiple loads/stores, the | |
3785 | maximum possible displacement is a bit smaller. */ | |
3786 | if (mode_sz > mov_insn_sz) | |
3787 | r -= mode_sz - mov_insn_sz; | |
3788 | return r; | |
3789 | } | |
3790 | } | |
344332e8 | 3791 | |
9b9ad23f OE |
3792 | /* Determine the alignment mask for a move insn of the |
3793 | specified mode. */ | |
9b9ad23f | 3794 | static inline int |
ef4bddc2 | 3795 | mov_insn_alignment_mask (machine_mode mode, bool consider_sh2a) |
9b9ad23f OE |
3796 | { |
3797 | const int mov_insn_sz = mov_insn_size (mode, consider_sh2a); | |
3798 | return mov_insn_sz > 0 ? (mov_insn_sz - 1) : 0; | |
3799 | } | |
3800 | ||
8c2a3f3b | 3801 | /* Return the displacement value of a displacement address. */ |
91f65b12 OE |
3802 | HOST_WIDE_INT |
3803 | sh_disp_addr_displacement (rtx x) | |
8c2a3f3b OE |
3804 | { |
3805 | gcc_assert (satisfies_constraint_Sdd (x)); | |
3806 | return INTVAL (XEXP (XEXP (x, 0), 1)); | |
3807 | } | |
3808 | ||
9b9ad23f | 3809 | /* Compute the cost of an address. */ |
9b9ad23f | 3810 | static int |
ef4bddc2 | 3811 | sh_address_cost (rtx x, machine_mode mode, |
b413068c | 3812 | addr_space_t as ATTRIBUTE_UNUSED, bool speed ATTRIBUTE_UNUSED) |
9b9ad23f | 3813 | { |
fce1e5fb OE |
3814 | /* 'GBR + 0'. Account one more because of R0 restriction. */ |
3815 | if (REG_P (x) && REGNO (x) == GBR_REG) | |
3816 | return 2; | |
3817 | ||
8385420c OE |
3818 | /* Simple reg, post-inc, pre-dec addressing. */ |
3819 | if (REG_P (x) || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC) | |
3820 | return 1; | |
3821 | ||
9b9ad23f | 3822 | /* 'reg + disp' addressing. */ |
8385420c OE |
3823 | if (GET_CODE (x) == PLUS |
3824 | && REG_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1))) | |
9b9ad23f | 3825 | { |
fce1e5fb OE |
3826 | /* 'GBR + disp'. Account one more because of R0 restriction. */ |
3827 | if (REGNO (XEXP (x, 0)) == GBR_REG | |
3828 | && gbr_displacement (XEXP (x, 1), mode)) | |
3829 | return 2; | |
3830 | ||
8385420c | 3831 | const HOST_WIDE_INT offset = INTVAL (XEXP (x, 1)); |
9b9ad23f | 3832 | |
8385420c OE |
3833 | if (offset == 0) |
3834 | return 1; | |
3835 | ||
3836 | /* The displacement would fit into a 2 byte move insn. | |
3837 | HImode and QImode loads/stores with displacement put pressure on | |
3838 | R0 which will most likely require another reg copy. Thus account | |
3839 | a higher cost for that. */ | |
91f65b12 | 3840 | if (offset > 0 && offset <= sh_max_mov_insn_displacement (mode, false)) |
8385420c | 3841 | return (mode == HImode || mode == QImode) ? 2 : 1; |
9b9ad23f OE |
3842 | |
3843 | /* The displacement would fit into a 4 byte move insn (SH2A). */ | |
3844 | if (TARGET_SH2A | |
91f65b12 | 3845 | && offset > 0 && offset <= sh_max_mov_insn_displacement (mode, true)) |
8385420c | 3846 | return 2; |
9b9ad23f OE |
3847 | |
3848 | /* The displacement is probably out of range and will require extra | |
3849 | calculations. */ | |
8385420c | 3850 | return 3; |
9b9ad23f OE |
3851 | } |
3852 | ||
3853 | /* 'reg + reg' addressing. Account a slightly higher cost because of | |
3854 | increased pressure on R0. */ | |
3855 | if (GET_CODE (x) == PLUS && ! CONSTANT_P (XEXP (x, 1)) | |
3856 | && ! TARGET_SHMEDIA) | |
8385420c | 3857 | return 3; |
9b9ad23f | 3858 | |
8385420c OE |
3859 | /* Not sure what it is - probably expensive. */ |
3860 | return 10; | |
dcefdf67 | 3861 | } |
3c50106f | 3862 | |
16bea517 | 3863 | /* Code to expand a shift. */ |
d8a48c21 | 3864 | static void |
cf277499 | 3865 | gen_ashift (int type, int n, rtx reg) |
0d7e008e | 3866 | { |
d8a48c21 OE |
3867 | rtx n_rtx; |
3868 | ||
16bea517 JW |
3869 | /* Negative values here come from the shift_amounts array. */ |
3870 | if (n < 0) | |
3871 | { | |
3872 | if (type == ASHIFT) | |
3873 | type = LSHIFTRT; | |
3874 | else | |
3875 | type = ASHIFT; | |
3876 | n = -n; | |
3877 | } | |
3878 | ||
d8a48c21 OE |
3879 | n_rtx = GEN_INT (n); |
3880 | gcc_assert (satisfies_constraint_P27 (n_rtx)); | |
3881 | ||
0d7e008e | 3882 | switch (type) |
bc45ade3 | 3883 | { |
0d7e008e | 3884 | case ASHIFTRT: |
d8a48c21 | 3885 | emit_insn (gen_ashrsi3_k (reg, reg, n_rtx)); |
0d7e008e SC |
3886 | break; |
3887 | case LSHIFTRT: | |
16bea517 | 3888 | if (n == 1) |
50fe8924 | 3889 | emit_insn (gen_shlr (reg, reg)); |
16bea517 | 3890 | else |
d8a48c21 | 3891 | emit_insn (gen_lshrsi3_k (reg, reg, n_rtx)); |
0d7e008e SC |
3892 | break; |
3893 | case ASHIFT: | |
d8a48c21 | 3894 | emit_insn (gen_ashlsi3_k (reg, reg, n_rtx)); |
0d7e008e | 3895 | break; |
d8a48c21 OE |
3896 | default: |
3897 | gcc_unreachable (); | |
bc45ade3 | 3898 | } |
bc45ade3 | 3899 | } |
bc45ade3 | 3900 | |
50fe8924 | 3901 | /* Code to expand a HImode shift. */ |
d8a48c21 | 3902 | static void |
cf277499 | 3903 | gen_ashift_hi (int type, int n, rtx reg) |
8d481241 JW |
3904 | { |
3905 | /* Negative values here come from the shift_amounts array. */ | |
3906 | if (n < 0) | |
3907 | { | |
3908 | if (type == ASHIFT) | |
3909 | type = LSHIFTRT; | |
3910 | else | |
3911 | type = ASHIFT; | |
3912 | n = -n; | |
3913 | } | |
3914 | ||
3915 | switch (type) | |
3916 | { | |
3917 | case ASHIFTRT: | |
8d481241 | 3918 | case LSHIFTRT: |
d0c42859 R |
3919 | /* We don't have HImode right shift operations because using the |
3920 | ordinary 32 bit shift instructions for that doesn't generate proper | |
3921 | zero/sign extension. | |
3922 | gen_ashift_hi is only called in contexts where we know that the | |
3923 | sign extension works out correctly. */ | |
97d6fd65 | 3924 | { |
ddef6bc7 | 3925 | int offset = 0; |
97d6fd65 R |
3926 | if (GET_CODE (reg) == SUBREG) |
3927 | { | |
ddef6bc7 | 3928 | offset = SUBREG_BYTE (reg); |
97d6fd65 R |
3929 | reg = SUBREG_REG (reg); |
3930 | } | |
ddef6bc7 | 3931 | gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset)); |
97d6fd65 R |
3932 | break; |
3933 | } | |
8d481241 JW |
3934 | case ASHIFT: |
3935 | emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n))); | |
3936 | break; | |
3937 | } | |
3938 | } | |
3939 | ||
8aa2a305 JW |
3940 | /* Output RTL to split a constant shift into its component SH constant |
3941 | shift instructions. */ | |
318881c0 | 3942 | void |
cf277499 | 3943 | gen_shifty_op (int code, rtx *operands) |
bc45ade3 | 3944 | { |
16bea517 | 3945 | int value = INTVAL (operands[2]); |
8aa2a305 | 3946 | int max, i; |
00f8ff66 | 3947 | |
cff3d762 | 3948 | /* Truncate the shift count in case it is out of bounds. */ |
6c34a092 | 3949 | value = value & 31; |
f676971a | 3950 | |
8aa2a305 | 3951 | if (value == 31) |
16bea517 | 3952 | { |
8aa2a305 | 3953 | if (code == LSHIFTRT) |
0d7e008e | 3954 | { |
8aa2a305 | 3955 | emit_insn (gen_rotlsi3_1 (operands[0], operands[0])); |
f031c344 | 3956 | emit_insn (gen_movt (operands[0], get_t_reg_rtx ())); |
8aa2a305 | 3957 | return; |
16bea517 | 3958 | } |
8aa2a305 | 3959 | else if (code == ASHIFT) |
16bea517 | 3960 | { |
8aa2a305 JW |
3961 | /* There is a two instruction sequence for 31 bit left shifts, |
3962 | but it requires r0. */ | |
f3536097 | 3963 | if (REG_P (operands[0]) && REGNO (operands[0]) == 0) |
0d7e008e | 3964 | { |
8aa2a305 JW |
3965 | emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx)); |
3966 | emit_insn (gen_rotlsi3_31 (operands[0], operands[0])); | |
3967 | return; | |
0d7e008e | 3968 | } |
16bea517 | 3969 | } |
8aa2a305 | 3970 | } |
c17f53a8 JW |
3971 | else if (value == 0) |
3972 | { | |
73a4d10b R |
3973 | /* This can happen even when optimizing, if there were subregs before |
3974 | reload. Don't output a nop here, as this is never optimized away; | |
3975 | use a no-op move instead. */ | |
f7df4a84 | 3976 | emit_insn (gen_rtx_SET (operands[0], operands[0])); |
c17f53a8 JW |
3977 | return; |
3978 | } | |
a9f71ad8 | 3979 | |
70d4736c | 3980 | max = ashl_lshr_seq[value].insn_count; |
8aa2a305 | 3981 | for (i = 0; i < max; i++) |
70d4736c | 3982 | gen_ashift (code, ashl_lshr_seq[value].amount[i], operands[0]); |
8aa2a305 | 3983 | } |
f676971a | 3984 | |
50fe8924 OE |
3985 | /* Same as gen_shifty_op, but optimized for values where the topmost bits |
3986 | don't matter. */ | |
318881c0 | 3987 | void |
cf277499 | 3988 | gen_shifty_hi_op (int code, rtx *operands) |
8d481241 JW |
3989 | { |
3990 | int value = INTVAL (operands[2]); | |
3991 | int max, i; | |
cf277499 | 3992 | void (*gen_fun) (int, int, rtx); |
8d481241 JW |
3993 | |
3994 | /* This operation is used by and_shl for SImode values with a few | |
3995 | high bits known to be cleared. */ | |
3996 | value &= 31; | |
3997 | if (value == 0) | |
3998 | { | |
3999 | emit_insn (gen_nop ()); | |
4000 | return; | |
4001 | } | |
4002 | ||
4003 | gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift; | |
4004 | if (code == ASHIFT) | |
4005 | { | |
70d4736c | 4006 | max = ext_ashl_lshr_seq[value].insn_count; |
8d481241 | 4007 | for (i = 0; i < max; i++) |
70d4736c | 4008 | gen_fun (code, ext_ashl_lshr_seq[value].amount[i], operands[0]); |
8d481241 JW |
4009 | } |
4010 | else | |
4011 | /* When shifting right, emit the shifts in reverse order, so that | |
4012 | solitary negative values come first. */ | |
70d4736c OE |
4013 | for (i = ext_ashl_lshr_seq[value].insn_count - 1; i >= 0; i--) |
4014 | gen_fun (code, ext_ashl_lshr_seq[value].amount[i], operands[0]); | |
8d481241 | 4015 | } |
8aa2a305 | 4016 | |
50fe8924 OE |
4017 | /* Output RTL for an arithmetic right shift. |
4018 | ??? Rewrite to use super-optimizer sequences. */ | |
aaf701c5 | 4019 | bool |
cf277499 | 4020 | expand_ashiftrt (rtx *operands) |
8aa2a305 JW |
4021 | { |
4022 | rtx wrk; | |
4023 | char func[18]; | |
8aa2a305 JW |
4024 | int value; |
4025 | ||
a594120b | 4026 | if (TARGET_DYNSHIFT) |
20b04867 | 4027 | { |
f3536097 | 4028 | if (!CONST_INT_P (operands[2])) |
49b6d06b JW |
4029 | { |
4030 | rtx count = copy_to_mode_reg (SImode, operands[2]); | |
4031 | emit_insn (gen_negsi2 (count, count)); | |
4032 | emit_insn (gen_ashrsi3_d (operands[0], operands[1], count)); | |
aaf701c5 | 4033 | return true; |
49b6d06b | 4034 | } |
1245df60 R |
4035 | else if (ashiftrt_insns[INTVAL (operands[2]) & 31] |
4036 | > 1 + SH_DYNAMIC_SHIFT_COST) | |
49b6d06b | 4037 | { |
1245df60 R |
4038 | rtx count |
4039 | = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31))); | |
49b6d06b | 4040 | emit_insn (gen_ashrsi3_d (operands[0], operands[1], count)); |
aaf701c5 | 4041 | return true; |
49b6d06b | 4042 | } |
20b04867 | 4043 | } |
f3536097 | 4044 | if (!CONST_INT_P (operands[2])) |
aaf701c5 | 4045 | return false; |
8aa2a305 | 4046 | |
1245df60 | 4047 | value = INTVAL (operands[2]) & 31; |
8aa2a305 JW |
4048 | |
4049 | if (value == 31) | |
4050 | { | |
73a4d10b R |
4051 | /* If we are called from abs expansion, arrange things so that we |
4052 | we can use a single MT instruction that doesn't clobber the source, | |
4053 | if LICM can hoist out the load of the constant zero. */ | |
4054 | if (currently_expanding_to_rtl) | |
4055 | { | |
4056 | emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)), | |
4057 | operands[1])); | |
be8cbce1 | 4058 | emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ())); |
aaf701c5 | 4059 | return true; |
73a4d10b | 4060 | } |
8aa2a305 | 4061 | emit_insn (gen_ashrsi2_31 (operands[0], operands[1])); |
aaf701c5 | 4062 | return true; |
8aa2a305 JW |
4063 | } |
4064 | else if (value >= 16 && value <= 19) | |
4065 | { | |
4066 | wrk = gen_reg_rtx (SImode); | |
4067 | emit_insn (gen_ashrsi2_16 (wrk, operands[1])); | |
4068 | value -= 16; | |
4069 | while (value--) | |
4070 | gen_ashift (ASHIFTRT, 1, wrk); | |
4071 | emit_move_insn (operands[0], wrk); | |
aaf701c5 | 4072 | return true; |
a9f71ad8 | 4073 | } |
8aa2a305 JW |
4074 | /* Expand a short sequence inline, longer call a magic routine. */ |
4075 | else if (value <= 5) | |
4076 | { | |
4077 | wrk = gen_reg_rtx (SImode); | |
4078 | emit_move_insn (wrk, operands[1]); | |
4079 | while (value--) | |
4080 | gen_ashift (ASHIFTRT, 1, wrk); | |
4081 | emit_move_insn (operands[0], wrk); | |
aaf701c5 | 4082 | return true; |
8aa2a305 JW |
4083 | } |
4084 | ||
4085 | wrk = gen_reg_rtx (Pmode); | |
4086 | ||
4087 | /* Load the value into an arg reg and call a helper. */ | |
c5c76735 | 4088 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]); |
8aa2a305 | 4089 | sprintf (func, "__ashiftrt_r4_%d", value); |
73a4d10b | 4090 | function_symbol (wrk, func, SFUNC_STATIC); |
8aa2a305 | 4091 | emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk)); |
c5c76735 | 4092 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 4)); |
aaf701c5 | 4093 | return true; |
bc45ade3 | 4094 | } |
8d481241 JW |
4095 | |
4096 | /* Try to find a good way to implement the combiner pattern | |
4097 | [(set (match_operand:SI 0 "register_operand" "r") | |
4098 | (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") | |
4099 | (match_operand:SI 2 "const_int_operand" "n")) | |
4100 | (match_operand:SI 3 "const_int_operand" "n"))) . | |
4101 | LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3. | |
4102 | return 0 for simple right / left or left/right shift combination. | |
4103 | return 1 for a combination of shifts with zero_extend. | |
4104 | return 2 for a combination of shifts with an AND that needs r0. | |
4105 | return 3 for a combination of shifts with an AND that needs an extra | |
4106 | scratch register, when the three highmost bits of the AND mask are clear. | |
4107 | return 4 for a combination of shifts with an AND that needs an extra | |
4108 | scratch register, when any of the three highmost bits of the AND mask | |
4109 | is set. | |
4110 | If ATTRP is set, store an initial right shift width in ATTRP[0], | |
4111 | and the instruction length in ATTRP[1] . These values are not valid | |
4112 | when returning 0. | |
4113 | When ATTRP is set and returning 1, ATTRP[2] gets set to the index into | |
4114 | shift_amounts for the last shift value that is to be used before the | |
4115 | sign extend. */ | |
4116 | int | |
cf277499 | 4117 | shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp) |
8d481241 JW |
4118 | { |
4119 | unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2; | |
4120 | int left = INTVAL (left_rtx), right; | |
4121 | int best = 0; | |
4122 | int cost, best_cost = 10000; | |
4123 | int best_right = 0, best_len = 0; | |
4124 | int i; | |
4125 | int can_ext; | |
4126 | ||
4127 | if (left < 0 || left > 31) | |
4128 | return 0; | |
f3536097 | 4129 | if (CONST_INT_P (mask_rtx)) |
8d481241 JW |
4130 | mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left; |
4131 | else | |
4132 | mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left; | |
832a3292 | 4133 | /* Can this be expressed as a right shift / left shift pair? */ |
8d481241 JW |
4134 | lsb = ((mask ^ (mask - 1)) >> 1) + 1; |
4135 | right = exact_log2 (lsb); | |
4136 | mask2 = ~(mask + lsb - 1); | |
4137 | lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1; | |
4138 | /* mask has no zeroes but trailing zeroes <==> ! mask2 */ | |
4139 | if (! mask2) | |
70d4736c OE |
4140 | best_cost = ashl_lshr_seq[right].insn_count |
4141 | + ashl_lshr_seq[right + left].insn_count; | |
8d481241 JW |
4142 | /* mask has no trailing zeroes <==> ! right */ |
4143 | else if (! right && mask2 == ~(lsb2 - 1)) | |
4144 | { | |
4145 | int late_right = exact_log2 (lsb2); | |
70d4736c OE |
4146 | best_cost = ashl_lshr_seq[left + late_right].insn_count |
4147 | + ashl_lshr_seq[late_right].insn_count; | |
8d481241 | 4148 | } |
832a3292 | 4149 | /* Try to use zero extend. */ |
8d481241 JW |
4150 | if (mask2 == ~(lsb2 - 1)) |
4151 | { | |
4152 | int width, first; | |
4153 | ||
4154 | for (width = 8; width <= 16; width += 8) | |
4155 | { | |
832a3292 KH |
4156 | /* Can we zero-extend right away? */ |
4157 | if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width) | |
8d481241 | 4158 | { |
70d4736c OE |
4159 | cost = 1 + ext_ashl_lshr_seq[right].insn_count |
4160 | + ext_ashl_lshr_seq[left + right].insn_count; | |
8d481241 JW |
4161 | if (cost < best_cost) |
4162 | { | |
4163 | best = 1; | |
4164 | best_cost = cost; | |
4165 | best_right = right; | |
4166 | best_len = cost; | |
4167 | if (attrp) | |
4168 | attrp[2] = -1; | |
4169 | } | |
4170 | continue; | |
4171 | } | |
4172 | /* ??? Could try to put zero extend into initial right shift, | |
6f317ef3 | 4173 | or even shift a bit left before the right shift. */ |
8d481241 JW |
4174 | /* Determine value of first part of left shift, to get to the |
4175 | zero extend cut-off point. */ | |
4176 | first = width - exact_log2 (lsb2) + right; | |
4177 | if (first >= 0 && right + left - first >= 0) | |
4178 | { | |
70d4736c OE |
4179 | cost = ext_ashl_lshr_seq[right].insn_count |
4180 | + ext_ashl_lshr_seq[first].insn_count + 1 | |
4181 | + ext_ashl_lshr_seq[right + left - first].insn_count; | |
4182 | ||
8d481241 JW |
4183 | if (cost < best_cost) |
4184 | { | |
4185 | best = 1; | |
4186 | best_cost = cost; | |
4187 | best_right = right; | |
4188 | best_len = cost; | |
4189 | if (attrp) | |
4190 | attrp[2] = first; | |
832a3292 | 4191 | } |
8d481241 JW |
4192 | } |
4193 | } | |
4194 | } | |
4195 | /* Try to use r0 AND pattern */ | |
4196 | for (i = 0; i <= 2; i++) | |
4197 | { | |
4198 | if (i > right) | |
4199 | break; | |
735cb76e | 4200 | if (! CONST_OK_FOR_K08 (mask >> i)) |
8d481241 | 4201 | continue; |
70d4736c | 4202 | cost = (i != 0) + 2 + ext_ashl_lshr_seq[left + i].insn_count; |
8d481241 JW |
4203 | if (cost < best_cost) |
4204 | { | |
4205 | best = 2; | |
4206 | best_cost = cost; | |
4207 | best_right = i; | |
4208 | best_len = cost - 1; | |
4209 | } | |
4210 | } | |
4211 | /* Try to use a scratch register to hold the AND operand. */ | |
832a3292 | 4212 | can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0; |
8d481241 JW |
4213 | for (i = 0; i <= 2; i++) |
4214 | { | |
4215 | if (i > right) | |
4216 | break; | |
735cb76e | 4217 | cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3) |
70d4736c OE |
4218 | + (can_ext |
4219 | ? ext_ashl_lshr_seq | |
4220 | : ashl_lshr_seq)[left + i].insn_count; | |
8d481241 JW |
4221 | if (cost < best_cost) |
4222 | { | |
4223 | best = 4 - can_ext; | |
4224 | best_cost = cost; | |
4225 | best_right = i; | |
735cb76e | 4226 | best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i); |
8d481241 JW |
4227 | } |
4228 | } | |
4229 | ||
4230 | if (attrp) | |
4231 | { | |
4232 | attrp[0] = best_right; | |
4233 | attrp[1] = best_len; | |
4234 | } | |
4235 | return best; | |
4236 | } | |
4237 | ||
4238 | /* This is used in length attributes of the unnamed instructions | |
4239 | corresponding to shl_and_kind return values of 1 and 2. */ | |
4240 | int | |
cf277499 | 4241 | shl_and_length (rtx insn) |
8d481241 JW |
4242 | { |
4243 | rtx set_src, left_rtx, mask_rtx; | |
4244 | int attributes[3]; | |
4245 | ||
4246 | set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
4247 | left_rtx = XEXP (XEXP (set_src, 0), 1); | |
4248 | mask_rtx = XEXP (set_src, 1); | |
4249 | shl_and_kind (left_rtx, mask_rtx, attributes); | |
4250 | return attributes[1]; | |
4251 | } | |
4252 | ||
4253 | /* This is used in length attribute of the and_shl_scratch instruction. */ | |
8d481241 | 4254 | int |
cf277499 | 4255 | shl_and_scr_length (rtx insn) |
8d481241 JW |
4256 | { |
4257 | rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
70d4736c | 4258 | int len = ashl_lshr_seq[INTVAL (XEXP (set_src, 1)) & 31].insn_count; |
8d481241 | 4259 | rtx op = XEXP (set_src, 0); |
70d4736c | 4260 | len += ashl_lshr_seq[INTVAL (XEXP (op, 1)) & 31].insn_count + 1; |
8d481241 | 4261 | op = XEXP (XEXP (op, 0), 0); |
70d4736c | 4262 | return len + ashl_lshr_seq[INTVAL (XEXP (op, 1)) & 31].insn_count; |
8d481241 JW |
4263 | } |
4264 | ||
8d481241 JW |
4265 | /* Generate rtl for instructions for which shl_and_kind advised a particular |
4266 | method of generating them, i.e. returned zero. */ | |
aaf701c5 | 4267 | bool |
cf277499 | 4268 | gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source) |
8d481241 JW |
4269 | { |
4270 | int attributes[3]; | |
4271 | unsigned HOST_WIDE_INT mask; | |
4272 | int kind = shl_and_kind (left_rtx, mask_rtx, attributes); | |
4273 | int right, total_shift; | |
832a3292 | 4274 | void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op; |
8d481241 JW |
4275 | |
4276 | right = attributes[0]; | |
4277 | total_shift = INTVAL (left_rtx) + right; | |
4278 | mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift; | |
4279 | switch (kind) | |
4280 | { | |
4281 | default: | |
aaf701c5 | 4282 | return true; |
8d481241 JW |
4283 | case 1: |
4284 | { | |
4285 | int first = attributes[2]; | |
4286 | rtx operands[3]; | |
4287 | ||
4288 | if (first < 0) | |
4289 | { | |
7174c937 | 4290 | emit_insn ((mask << right) <= 0xff |
832a3292 KH |
4291 | ? gen_zero_extendqisi2 (dest, |
4292 | gen_lowpart (QImode, source)) | |
4293 | : gen_zero_extendhisi2 (dest, | |
4294 | gen_lowpart (HImode, source))); | |
8d481241 JW |
4295 | source = dest; |
4296 | } | |
4297 | if (source != dest) | |
4298 | emit_insn (gen_movsi (dest, source)); | |
4299 | operands[0] = dest; | |
4300 | if (right) | |
4301 | { | |
4302 | operands[2] = GEN_INT (right); | |
4303 | gen_shifty_hi_op (LSHIFTRT, operands); | |
4304 | } | |
4305 | if (first > 0) | |
4306 | { | |
4307 | operands[2] = GEN_INT (first); | |
4308 | gen_shifty_hi_op (ASHIFT, operands); | |
4309 | total_shift -= first; | |
4310 | mask <<= first; | |
4311 | } | |
4312 | if (first >= 0) | |
85af47b9 | 4313 | emit_insn (mask <= 0xff |
832a3292 KH |
4314 | ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest)) |
4315 | : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest))); | |
8d481241 JW |
4316 | if (total_shift > 0) |
4317 | { | |
4318 | operands[2] = GEN_INT (total_shift); | |
4319 | gen_shifty_hi_op (ASHIFT, operands); | |
4320 | } | |
4321 | break; | |
4322 | } | |
4323 | case 4: | |
4324 | shift_gen_fun = gen_shifty_op; | |
8d481241 | 4325 | case 3: |
24c50999 JR |
4326 | /* If the topmost bit that matters is set, set the topmost bits |
4327 | that don't matter. This way, we might be able to get a shorter | |
4328 | signed constant. */ | |
832a3292 KH |
4329 | if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift))) |
4330 | mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift); | |
61fb6bac | 4331 | case 2: |
8d481241 JW |
4332 | /* Don't expand fine-grained when combining, because that will |
4333 | make the pattern fail. */ | |
4586b4ca | 4334 | if (currently_expanding_to_rtl |
8d481241 JW |
4335 | || reload_in_progress || reload_completed) |
4336 | { | |
4337 | rtx operands[3]; | |
f676971a | 4338 | |
61fb6bac R |
4339 | /* Cases 3 and 4 should be handled by this split |
4340 | only while combining */ | |
f5b9e7c9 | 4341 | gcc_assert (kind <= 2); |
8d481241 JW |
4342 | if (right) |
4343 | { | |
4344 | emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right))); | |
4345 | source = dest; | |
4346 | } | |
4347 | emit_insn (gen_andsi3 (dest, source, GEN_INT (mask))); | |
afad3d2c JW |
4348 | if (total_shift) |
4349 | { | |
4350 | operands[0] = dest; | |
4351 | operands[1] = dest; | |
4352 | operands[2] = GEN_INT (total_shift); | |
4353 | shift_gen_fun (ASHIFT, operands); | |
4354 | } | |
8d481241 JW |
4355 | break; |
4356 | } | |
4357 | else | |
4358 | { | |
4359 | int neg = 0; | |
4360 | if (kind != 4 && total_shift < 16) | |
4361 | { | |
70d4736c | 4362 | neg = -ext_ashl_lshr_seq[total_shift].amount[1]; |
8d481241 | 4363 | if (neg > 0) |
70d4736c | 4364 | neg -= ext_ashl_lshr_seq[total_shift].amount[2]; |
8d481241 JW |
4365 | else |
4366 | neg = 0; | |
4367 | } | |
4368 | emit_insn (gen_and_shl_scratch (dest, source, | |
4369 | GEN_INT (right), | |
4370 | GEN_INT (mask), | |
4371 | GEN_INT (total_shift + neg), | |
4372 | GEN_INT (neg))); | |
4373 | emit_insn (gen_movsi (dest, dest)); | |
4374 | break; | |
4375 | } | |
4376 | } | |
aaf701c5 | 4377 | return false; |
8d481241 JW |
4378 | } |
4379 | ||
4380 | /* Try to find a good way to implement the combiner pattern | |
4381 | [(set (match_operand:SI 0 "register_operand" "=r") | |
4382 | (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") | |
4383 | (match_operand:SI 2 "const_int_operand" "n") | |
4384 | (match_operand:SI 3 "const_int_operand" "n") | |
4385 | (const_int 0))) | |
4773afa4 | 4386 | (clobber (reg:SI T_REG))] |
8d481241 JW |
4387 | LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3. |
4388 | return 0 for simple left / right shift combination. | |
4389 | return 1 for left shift / 8 bit sign extend / left shift. | |
4390 | return 2 for left shift / 16 bit sign extend / left shift. | |
4391 | return 3 for left shift / 8 bit sign extend / shift / sign extend. | |
4392 | return 4 for left shift / 16 bit sign extend / shift / sign extend. | |
4393 | return 5 for left shift / 16 bit sign extend / right shift | |
4394 | return 6 for < 8 bit sign extend / left shift. | |
4395 | return 7 for < 8 bit sign extend / left shift / single right shift. | |
4396 | If COSTP is nonzero, assign the calculated cost to *COSTP. */ | |
8d481241 | 4397 | int |
cf277499 | 4398 | shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp) |
8d481241 JW |
4399 | { |
4400 | int left, size, insize, ext; | |
3a8699c7 | 4401 | int cost = 0, best_cost; |
8d481241 JW |
4402 | int kind; |
4403 | ||
4404 | left = INTVAL (left_rtx); | |
4405 | size = INTVAL (size_rtx); | |
4406 | insize = size - left; | |
f5b9e7c9 | 4407 | gcc_assert (insize > 0); |
8d481241 JW |
4408 | /* Default to left / right shift. */ |
4409 | kind = 0; | |
70d4736c OE |
4410 | best_cost = ashl_lshr_seq[32 - insize].insn_count |
4411 | + ashl_lshr_seq[32 - size].insn_count; | |
8d481241 JW |
4412 | if (size <= 16) |
4413 | { | |
4414 | /* 16 bit shift / sign extend / 16 bit shift */ | |
70d4736c OE |
4415 | cost = ashl_lshr_seq[16 - insize].insn_count + 1 |
4416 | + ashl_lshr_seq[16 - size].insn_count; | |
afad3d2c JW |
4417 | /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden |
4418 | below, by alternative 3 or something even better. */ | |
8d481241 JW |
4419 | if (cost < best_cost) |
4420 | { | |
4421 | kind = 5; | |
4422 | best_cost = cost; | |
4423 | } | |
4424 | } | |
4425 | /* Try a plain sign extend between two shifts. */ | |
4426 | for (ext = 16; ext >= insize; ext -= 8) | |
4427 | { | |
4428 | if (ext <= size) | |
4429 | { | |
70d4736c OE |
4430 | cost = ext_ashl_lshr_seq[ext - insize].insn_count + 1 |
4431 | + ashl_lshr_seq[size - ext].insn_count; | |
8d481241 JW |
4432 | if (cost < best_cost) |
4433 | { | |
11f9ed1a | 4434 | kind = ext / (unsigned) 8; |
8d481241 JW |
4435 | best_cost = cost; |
4436 | } | |
4437 | } | |
ae9d19c0 JR |
4438 | /* Check if we can do a sloppy shift with a final signed shift |
4439 | restoring the sign. */ | |
4440 | if (EXT_SHIFT_SIGNED (size - ext)) | |
70d4736c OE |
4441 | cost = ext_ashl_lshr_seq[ext - insize].insn_count |
4442 | + ext_ashl_lshr_seq[size - ext].insn_count + 1; | |
ae9d19c0 JR |
4443 | /* If not, maybe it's still cheaper to do the second shift sloppy, |
4444 | and do a final sign extend? */ | |
4445 | else if (size <= 16) | |
70d4736c OE |
4446 | cost = ext_ashl_lshr_seq[ext - insize].insn_count + 1 |
4447 | + ext_ashl_lshr_seq[size > ext ? size - ext : ext - size].insn_count | |
4448 | + 1; | |
ae9d19c0 JR |
4449 | else |
4450 | continue; | |
4451 | if (cost < best_cost) | |
8d481241 | 4452 | { |
11f9ed1a | 4453 | kind = ext / (unsigned) 8 + 2; |
ae9d19c0 | 4454 | best_cost = cost; |
8d481241 JW |
4455 | } |
4456 | } | |
4457 | /* Check if we can sign extend in r0 */ | |
4458 | if (insize < 8) | |
4459 | { | |
70d4736c | 4460 | cost = 3 + ashl_lshr_seq[left].insn_count; |
8d481241 JW |
4461 | if (cost < best_cost) |
4462 | { | |
4463 | kind = 6; | |
4464 | best_cost = cost; | |
4465 | } | |
4466 | /* Try the same with a final signed shift. */ | |
4467 | if (left < 31) | |
4468 | { | |
70d4736c | 4469 | cost = 3 + ext_ashl_lshr_seq[left + 1].insn_count + 1; |
8d481241 JW |
4470 | if (cost < best_cost) |
4471 | { | |
4472 | kind = 7; | |
4473 | best_cost = cost; | |
4474 | } | |
4475 | } | |
4476 | } | |
a594120b | 4477 | if (TARGET_DYNSHIFT) |
8d481241 JW |
4478 | { |
4479 | /* Try to use a dynamic shift. */ | |
70d4736c | 4480 | cost = ashl_lshr_seq[32 - insize].insn_count + 1 + SH_DYNAMIC_SHIFT_COST; |
8d481241 JW |
4481 | if (cost < best_cost) |
4482 | { | |
4483 | kind = 0; | |
4484 | best_cost = cost; | |
4485 | } | |
4486 | } | |
4487 | if (costp) | |
4488 | *costp = cost; | |
4489 | return kind; | |
4490 | } | |
4491 | ||
4492 | /* Function to be used in the length attribute of the instructions | |
4493 | implementing this pattern. */ | |
8d481241 | 4494 | int |
cf277499 | 4495 | shl_sext_length (rtx insn) |
8d481241 JW |
4496 | { |
4497 | rtx set_src, left_rtx, size_rtx; | |
4498 | int cost; | |
4499 | ||
4500 | set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
4501 | left_rtx = XEXP (XEXP (set_src, 0), 1); | |
4502 | size_rtx = XEXP (set_src, 1); | |
4503 | shl_sext_kind (left_rtx, size_rtx, &cost); | |
4504 | return cost; | |
4505 | } | |
4506 | ||
4507 | /* Generate rtl for this pattern */ | |
aaf701c5 | 4508 | bool |
cf277499 | 4509 | gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source) |
8d481241 JW |
4510 | { |
4511 | int kind; | |
d00d338c | 4512 | int left, size, insize, cost; |
8d481241 JW |
4513 | rtx operands[3]; |
4514 | ||
d00d338c | 4515 | kind = shl_sext_kind (left_rtx, size_rtx, &cost); |
8d481241 JW |
4516 | left = INTVAL (left_rtx); |
4517 | size = INTVAL (size_rtx); | |
4518 | insize = size - left; | |
4519 | switch (kind) | |
4520 | { | |
4521 | case 1: | |
4522 | case 2: | |
4523 | case 3: | |
4524 | case 4: | |
4525 | { | |
4526 | int ext = kind & 1 ? 8 : 16; | |
4527 | int shift2 = size - ext; | |
4528 | ||
4529 | /* Don't expand fine-grained when combining, because that will | |
4530 | make the pattern fail. */ | |
4586b4ca | 4531 | if (! currently_expanding_to_rtl |
8d481241 JW |
4532 | && ! reload_in_progress && ! reload_completed) |
4533 | { | |
4534 | emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx)); | |
4535 | emit_insn (gen_movsi (dest, source)); | |
4536 | break; | |
4537 | } | |
4538 | if (dest != source) | |
4539 | emit_insn (gen_movsi (dest, source)); | |
4540 | operands[0] = dest; | |
afad3d2c JW |
4541 | if (ext - insize) |
4542 | { | |
4543 | operands[2] = GEN_INT (ext - insize); | |
4544 | gen_shifty_hi_op (ASHIFT, operands); | |
4545 | } | |
8d481241 | 4546 | emit_insn (kind & 1 |
832a3292 KH |
4547 | ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest)) |
4548 | : gen_extendhisi2 (dest, gen_lowpart (HImode, dest))); | |
8d481241 JW |
4549 | if (kind <= 2) |
4550 | { | |
afad3d2c JW |
4551 | if (shift2) |
4552 | { | |
4553 | operands[2] = GEN_INT (shift2); | |
4554 | gen_shifty_op (ASHIFT, operands); | |
4555 | } | |
8d481241 JW |
4556 | } |
4557 | else | |
4558 | { | |
afad3d2c | 4559 | if (shift2 > 0) |
8d481241 | 4560 | { |
ae9d19c0 JR |
4561 | if (EXT_SHIFT_SIGNED (shift2)) |
4562 | { | |
4563 | operands[2] = GEN_INT (shift2 + 1); | |
4564 | gen_shifty_op (ASHIFT, operands); | |
a556fd39 | 4565 | operands[2] = const1_rtx; |
ae9d19c0 JR |
4566 | gen_shifty_op (ASHIFTRT, operands); |
4567 | break; | |
4568 | } | |
8d481241 JW |
4569 | operands[2] = GEN_INT (shift2); |
4570 | gen_shifty_hi_op (ASHIFT, operands); | |
4571 | } | |
afad3d2c | 4572 | else if (shift2) |
8d481241 JW |
4573 | { |
4574 | operands[2] = GEN_INT (-shift2); | |
4575 | gen_shifty_hi_op (LSHIFTRT, operands); | |
4576 | } | |
4577 | emit_insn (size <= 8 | |
afad3d2c JW |
4578 | ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest)) |
4579 | : gen_extendhisi2 (dest, gen_lowpart (HImode, dest))); | |
8d481241 JW |
4580 | } |
4581 | break; | |
4582 | } | |
4583 | case 5: | |
afad3d2c JW |
4584 | { |
4585 | int i = 16 - size; | |
4586b4ca | 4586 | if (! currently_expanding_to_rtl |
913d8e13 R |
4587 | && ! reload_in_progress && ! reload_completed) |
4588 | emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx)); | |
4589 | else | |
4590 | { | |
4591 | operands[0] = dest; | |
4592 | operands[2] = GEN_INT (16 - insize); | |
4593 | gen_shifty_hi_op (ASHIFT, operands); | |
4594 | emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest))); | |
4595 | } | |
afad3d2c JW |
4596 | /* Don't use gen_ashrsi3 because it generates new pseudos. */ |
4597 | while (--i >= 0) | |
4598 | gen_ashift (ASHIFTRT, 1, dest); | |
4599 | break; | |
4600 | } | |
8d481241 JW |
4601 | case 6: |
4602 | case 7: | |
4603 | /* Don't expand fine-grained when combining, because that will | |
4604 | make the pattern fail. */ | |
4586b4ca | 4605 | if (! currently_expanding_to_rtl |
8d481241 JW |
4606 | && ! reload_in_progress && ! reload_completed) |
4607 | { | |
4608 | emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx)); | |
4609 | emit_insn (gen_movsi (dest, source)); | |
4610 | break; | |
4611 | } | |
4612 | emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1))); | |
4613 | emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1)))); | |
4614 | emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1)))); | |
4615 | operands[0] = dest; | |
4616 | operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx; | |
4617 | gen_shifty_op (ASHIFT, operands); | |
4618 | if (kind == 7) | |
a556fd39 | 4619 | emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx)); |
8d481241 JW |
4620 | break; |
4621 | default: | |
aaf701c5 | 4622 | return true; |
8d481241 | 4623 | } |
aaf701c5 | 4624 | return false; |
8d481241 | 4625 | } |
fa5322fa AO |
4626 | |
4627 | /* Prefix a symbol_ref name with "datalabel". */ | |
fa5322fa | 4628 | rtx |
cf277499 | 4629 | gen_datalabel_ref (rtx sym) |
fa5322fa | 4630 | { |
73a4d10b R |
4631 | const char *str; |
4632 | ||
fa5322fa AO |
4633 | if (GET_CODE (sym) == LABEL_REF) |
4634 | return gen_rtx_CONST (GET_MODE (sym), | |
4635 | gen_rtx_UNSPEC (GET_MODE (sym), | |
4636 | gen_rtvec (1, sym), | |
4637 | UNSPEC_DATALABEL)); | |
f676971a | 4638 | |
f5b9e7c9 | 4639 | gcc_assert (GET_CODE (sym) == SYMBOL_REF); |
fa5322fa | 4640 | |
73a4d10b R |
4641 | str = XSTR (sym, 0); |
4642 | /* Share all SYMBOL_REF strings with the same value - that is important | |
4643 | for cse. */ | |
4644 | str = IDENTIFIER_POINTER (get_identifier (str)); | |
4645 | XSTR (sym, 0) = str; | |
4646 | ||
fa5322fa AO |
4647 | return sym; |
4648 | } | |
4649 | ||
8aa2a305 | 4650 | \f |
6dd3c0a5 SB |
4651 | typedef struct label_ref_list_d |
4652 | { | |
6cb7eb41 | 4653 | rtx_code_label *label; |
6dd3c0a5 | 4654 | struct label_ref_list_d *next; |
533ab6c4 ML |
4655 | |
4656 | /* Pool allocation new operator. */ | |
4657 | inline void *operator new (size_t) | |
4658 | { | |
4659 | return pool.allocate (); | |
4660 | } | |
4661 | ||
4662 | /* Delete operator utilizing pool allocation. */ | |
4663 | inline void operator delete (void *ptr) | |
4664 | { | |
4665 | pool.remove ((label_ref_list_d *) ptr); | |
4666 | } | |
4667 | ||
4668 | /* Memory allocation pool. */ | |
4669 | static pool_allocator<label_ref_list_d> pool; | |
4670 | ||
6dd3c0a5 SB |
4671 | } *label_ref_list_t; |
4672 | ||
533ab6c4 ML |
4673 | pool_allocator<label_ref_list_d> label_ref_list_d::pool |
4674 | ("label references list", 30); | |
4675 | ||
8aa2a305 JW |
4676 | /* The SH cannot load a large constant into a register, constants have to |
4677 | come from a pc relative load. The reference of a pc relative load | |
0fa2e4df | 4678 | instruction must be less than 1k in front of the instruction. This |
8aa2a305 JW |
4679 | means that we often have to dump a constant inside a function, and |
4680 | generate code to branch around it. | |
bc45ade3 | 4681 | |
8aa2a305 JW |
4682 | It is important to minimize this, since the branches will slow things |
4683 | down and make things bigger. | |
4684 | ||
4685 | Worst case code looks like: | |
4686 | ||
4687 | mov.l L1,rn | |
4688 | bra L2 | |
4689 | nop | |
4690 | align | |
4691 | L1: .long value | |
4692 | L2: | |
4693 | .. | |
4694 | ||
4695 | mov.l L3,rn | |
4696 | bra L4 | |
4697 | nop | |
4698 | align | |
4699 | L3: .long value | |
4700 | L4: | |
4701 | .. | |
4702 | ||
4703 | We fix this by performing a scan before scheduling, which notices which | |
4704 | instructions need to have their operands fetched from the constant table | |
4705 | and builds the table. | |
4706 | ||
4707 | The algorithm is: | |
4708 | ||
4709 | scan, find an instruction which needs a pcrel move. Look forward, find the | |
4710 | last barrier which is within MAX_COUNT bytes of the requirement. | |
4711 | If there isn't one, make one. Process all the instructions between | |
4712 | the find and the barrier. | |
4713 | ||
4714 | In the above example, we can tell that L3 is within 1k of L1, so | |
4715 | the first move can be shrunk from the 3 insn+constant sequence into | |
4716 | just 1 insn, and the constant moved to L3 to make: | |
4717 | ||
4718 | mov.l L1,rn | |
4719 | .. | |
4720 | mov.l L3,rn | |
4721 | bra L4 | |
4722 | nop | |
4723 | align | |
4724 | L3:.long value | |
4725 | L4:.long value | |
4726 | ||
4727 | Then the second move becomes the target for the shortening process. */ | |
4728 | ||
4729 | typedef struct | |
4730 | { | |
4731 | rtx value; /* Value in table. */ | |
6cb7eb41 | 4732 | rtx_code_label *label; /* Label of value. */ |
6dd3c0a5 | 4733 | label_ref_list_t wend; /* End of window. */ |
ef4bddc2 | 4734 | machine_mode mode; /* Mode of value. */ |
3503150c RS |
4735 | |
4736 | /* True if this constant is accessed as part of a post-increment | |
4737 | sequence. Note that HImode constants are never accessed in this way. */ | |
4738 | bool part_of_sequence_p; | |
8aa2a305 JW |
4739 | } pool_node; |
4740 | ||
4741 | /* The maximum number of constants that can fit into one pool, since | |
73a4d10b R |
4742 | constants in the range 0..510 are at least 2 bytes long, and in the |
4743 | range from there to 1018 at least 4 bytes. */ | |
8aa2a305 | 4744 | |
73a4d10b | 4745 | #define MAX_POOL_SIZE 372 |
8aa2a305 JW |
4746 | static pool_node pool_vector[MAX_POOL_SIZE]; |
4747 | static int pool_size; | |
6cb7eb41 | 4748 | static rtx_code_label *pool_window_label; |
b91455de | 4749 | static int pool_window_last; |
8aa2a305 | 4750 | |
4241ecb0 R |
4751 | static int max_labelno_before_reorg; |
4752 | ||
8aa2a305 JW |
4753 | /* ??? If we need a constant in HImode which is the truncated value of a |
4754 | constant we need in SImode, we could combine the two entries thus saving | |
4755 | two bytes. Is this common enough to be worth the effort of implementing | |
4756 | it? */ | |
4757 | ||
4758 | /* ??? This stuff should be done at the same time that we shorten branches. | |
4759 | As it is now, we must assume that all branches are the maximum size, and | |
4760 | this causes us to almost always output constant pools sooner than | |
4761 | necessary. */ | |
4762 | ||
4763 | /* Add a constant to the pool and return its label. */ | |
6cb7eb41 | 4764 | static rtx_code_label * |
ef4bddc2 | 4765 | add_constant (rtx x, machine_mode mode, rtx last_value) |
0d7e008e SC |
4766 | { |
4767 | int i; | |
6cb7eb41 | 4768 | rtx_code_label *lab, *new_rtx; |
6dd3c0a5 | 4769 | label_ref_list_t ref, newref; |
8aa2a305 JW |
4770 | |
4771 | /* First see if we've already got it. */ | |
4772 | for (i = 0; i < pool_size; i++) | |
0d7e008e | 4773 | { |
8aa2a305 JW |
4774 | if (x->code == pool_vector[i].value->code |
4775 | && mode == pool_vector[i].mode) | |
0d7e008e | 4776 | { |
8aa2a305 JW |
4777 | if (x->code == CODE_LABEL) |
4778 | { | |
4779 | if (XINT (x, 3) != XINT (pool_vector[i].value, 3)) | |
4780 | continue; | |
4781 | } | |
4782 | if (rtx_equal_p (x, pool_vector[i].value)) | |
225e4f43 | 4783 | { |
0a2aaacc | 4784 | lab = new_rtx = 0; |
225e4f43 R |
4785 | if (! last_value |
4786 | || ! i | |
4787 | || ! rtx_equal_p (last_value, pool_vector[i-1].value)) | |
4788 | { | |
0a2aaacc KG |
4789 | new_rtx = gen_label_rtx (); |
4790 | LABEL_REFS (new_rtx) = pool_vector[i].label; | |
4791 | pool_vector[i].label = lab = new_rtx; | |
225e4f43 | 4792 | } |
b91455de KK |
4793 | if (lab && pool_window_label) |
4794 | { | |
533ab6c4 | 4795 | newref = new label_ref_list_d; |
6dd3c0a5 | 4796 | newref->label = pool_window_label; |
b91455de | 4797 | ref = pool_vector[pool_window_last].wend; |
6dd3c0a5 | 4798 | newref->next = ref; |
b91455de KK |
4799 | pool_vector[pool_window_last].wend = newref; |
4800 | } | |
0a2aaacc KG |
4801 | if (new_rtx) |
4802 | pool_window_label = new_rtx; | |
b91455de | 4803 | pool_window_last = i; |
225e4f43 R |
4804 | return lab; |
4805 | } | |
0d7e008e | 4806 | } |
0d7e008e | 4807 | } |
b9654711 | 4808 | |
8aa2a305 JW |
4809 | /* Need a new one. */ |
4810 | pool_vector[pool_size].value = x; | |
225e4f43 | 4811 | if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value)) |
3503150c RS |
4812 | { |
4813 | lab = 0; | |
4814 | pool_vector[pool_size - 1].part_of_sequence_p = true; | |
4815 | } | |
225e4f43 R |
4816 | else |
4817 | lab = gen_label_rtx (); | |
8aa2a305 JW |
4818 | pool_vector[pool_size].mode = mode; |
4819 | pool_vector[pool_size].label = lab; | |
6dd3c0a5 | 4820 | pool_vector[pool_size].wend = NULL; |
3503150c | 4821 | pool_vector[pool_size].part_of_sequence_p = (lab == 0); |
b91455de KK |
4822 | if (lab && pool_window_label) |
4823 | { | |
533ab6c4 | 4824 | newref = new label_ref_list_d; |
6dd3c0a5 | 4825 | newref->label = pool_window_label; |
b91455de | 4826 | ref = pool_vector[pool_window_last].wend; |
6dd3c0a5 | 4827 | newref->next = ref; |
b91455de KK |
4828 | pool_vector[pool_window_last].wend = newref; |
4829 | } | |
4830 | if (lab) | |
4831 | pool_window_label = lab; | |
4832 | pool_window_last = pool_size; | |
8aa2a305 JW |
4833 | pool_size++; |
4834 | return lab; | |
0d7e008e | 4835 | } |
16bea517 | 4836 | |
078c8b08 R |
4837 | /* Output the literal table. START, if nonzero, is the first instruction |
4838 | this table is needed for, and also indicates that there is at least one | |
4839 | casesi_worker_2 instruction; We have to emit the operand3 labels from | |
4840 | these insns at a 4-byte aligned position. BARRIER is the barrier | |
4841 | after which we are to place the table. */ | |
b9654711 | 4842 | static void |
6cb7eb41 | 4843 | dump_table (rtx_insn *start, rtx_insn *barrier) |
b9654711 | 4844 | { |
6cb7eb41 | 4845 | rtx_insn *scan = barrier; |
0d7e008e | 4846 | int i; |
23d0939b | 4847 | bool need_align = true; |
6dd3c0a5 SB |
4848 | rtx lab; |
4849 | label_ref_list_t ref; | |
23d0939b | 4850 | bool have_df = false; |
b9654711 | 4851 | |
16bea517 | 4852 | /* Do two passes, first time dump out the HI sized constants. */ |
b9654711 | 4853 | |
0d7e008e | 4854 | for (i = 0; i < pool_size; i++) |
b9654711 | 4855 | { |
8aa2a305 JW |
4856 | pool_node *p = &pool_vector[i]; |
4857 | ||
0d7e008e SC |
4858 | if (p->mode == HImode) |
4859 | { | |
4860 | if (need_align) | |
4861 | { | |
4862 | scan = emit_insn_after (gen_align_2 (), scan); | |
23d0939b | 4863 | need_align = false; |
0d7e008e | 4864 | } |
b91455de KK |
4865 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) |
4866 | scan = emit_label_after (lab, scan); | |
4867 | scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx), | |
4868 | scan); | |
6dd3c0a5 | 4869 | for (ref = p->wend; ref; ref = ref->next) |
b91455de | 4870 | { |
6dd3c0a5 | 4871 | lab = ref->label; |
b91455de KK |
4872 | scan = emit_insn_after (gen_consttable_window_end (lab), scan); |
4873 | } | |
0d7e008e | 4874 | } |
aa06e8f5 | 4875 | else if (p->mode == DFmode) |
23d0939b | 4876 | have_df = true; |
b9654711 | 4877 | } |
8aa2a305 | 4878 | |
23d0939b | 4879 | need_align = true; |
b9654711 | 4880 | |
078c8b08 R |
4881 | if (start) |
4882 | { | |
4883 | scan = emit_insn_after (gen_align_4 (), scan); | |
23d0939b | 4884 | need_align = false; |
078c8b08 | 4885 | for (; start != barrier; start = NEXT_INSN (start)) |
f3536097 | 4886 | if (NONJUMP_INSN_P (start) |
078c8b08 R |
4887 | && recog_memoized (start) == CODE_FOR_casesi_worker_2) |
4888 | { | |
4889 | rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0)); | |
4890 | rtx lab = XEXP (XVECEXP (src, 0, 3), 0); | |
4891 | ||
4892 | scan = emit_label_after (lab, scan); | |
4893 | } | |
4894 | } | |
aa06e8f5 | 4895 | if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df) |
fa5322fa | 4896 | { |
e60365d3 | 4897 | rtx_insn *align_insn = NULL; |
fa5322fa AO |
4898 | |
4899 | scan = emit_label_after (gen_label_rtx (), scan); | |
4900 | scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan); | |
23d0939b | 4901 | need_align = false; |
fa5322fa AO |
4902 | |
4903 | for (i = 0; i < pool_size; i++) | |
4904 | { | |
4905 | pool_node *p = &pool_vector[i]; | |
4906 | ||
4907 | switch (p->mode) | |
4908 | { | |
4909 | case HImode: | |
4910 | break; | |
4911 | case SImode: | |
4912 | case SFmode: | |
3503150c | 4913 | if (align_insn && !p->part_of_sequence_p) |
fa5322fa AO |
4914 | { |
4915 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) | |
4916 | emit_label_before (lab, align_insn); | |
4917 | emit_insn_before (gen_consttable_4 (p->value, const0_rtx), | |
4918 | align_insn); | |
6dd3c0a5 | 4919 | for (ref = p->wend; ref; ref = ref->next) |
fa5322fa | 4920 | { |
6dd3c0a5 | 4921 | lab = ref->label; |
fa5322fa | 4922 | emit_insn_before (gen_consttable_window_end (lab), |
832a3292 | 4923 | align_insn); |
fa5322fa AO |
4924 | } |
4925 | delete_insn (align_insn); | |
e60365d3 | 4926 | align_insn = NULL; |
fa5322fa AO |
4927 | continue; |
4928 | } | |
4929 | else | |
4930 | { | |
4931 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) | |
4932 | scan = emit_label_after (lab, scan); | |
4933 | scan = emit_insn_after (gen_consttable_4 (p->value, | |
4934 | const0_rtx), scan); | |
4935 | need_align = ! need_align; | |
4936 | } | |
4937 | break; | |
4938 | case DFmode: | |
fa5322fa AO |
4939 | if (need_align) |
4940 | { | |
4941 | scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan); | |
4942 | align_insn = scan; | |
23d0939b | 4943 | need_align = false; |
fa5322fa | 4944 | } |
aa06e8f5 | 4945 | case DImode: |
fa5322fa AO |
4946 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) |
4947 | scan = emit_label_after (lab, scan); | |
4948 | scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx), | |
4949 | scan); | |
4950 | break; | |
4951 | default: | |
f5b9e7c9 | 4952 | gcc_unreachable (); |
fa5322fa AO |
4953 | } |
4954 | ||
4955 | if (p->mode != HImode) | |
4956 | { | |
6dd3c0a5 | 4957 | for (ref = p->wend; ref; ref = ref->next) |
fa5322fa | 4958 | { |
6dd3c0a5 | 4959 | lab = ref->label; |
fa5322fa AO |
4960 | scan = emit_insn_after (gen_consttable_window_end (lab), |
4961 | scan); | |
4962 | } | |
4963 | } | |
4964 | } | |
4965 | ||
4966 | pool_size = 0; | |
4967 | } | |
f676971a | 4968 | |
0d7e008e | 4969 | for (i = 0; i < pool_size; i++) |
b9654711 | 4970 | { |
8aa2a305 | 4971 | pool_node *p = &pool_vector[i]; |
b9654711 | 4972 | |
0d7e008e | 4973 | switch (p->mode) |
b9654711 | 4974 | { |
0d7e008e SC |
4975 | case HImode: |
4976 | break; | |
4977 | case SImode: | |
e577c183 | 4978 | case SFmode: |
0d7e008e | 4979 | if (need_align) |
b9654711 | 4980 | { |
23d0939b | 4981 | need_align = false; |
d3ae8277 | 4982 | scan = emit_label_after (gen_label_rtx (), scan); |
0d7e008e | 4983 | scan = emit_insn_after (gen_align_4 (), scan); |
b9654711 | 4984 | } |
b91455de KK |
4985 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) |
4986 | scan = emit_label_after (lab, scan); | |
4987 | scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx), | |
4988 | scan); | |
0d7e008e | 4989 | break; |
e577c183 | 4990 | case DFmode: |
0d7e008e SC |
4991 | case DImode: |
4992 | if (need_align) | |
4993 | { | |
23d0939b | 4994 | need_align = false; |
d3ae8277 | 4995 | scan = emit_label_after (gen_label_rtx (), scan); |
0d7e008e SC |
4996 | scan = emit_insn_after (gen_align_4 (), scan); |
4997 | } | |
b91455de KK |
4998 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) |
4999 | scan = emit_label_after (lab, scan); | |
5000 | scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx), | |
5001 | scan); | |
0d7e008e SC |
5002 | break; |
5003 | default: | |
f5b9e7c9 | 5004 | gcc_unreachable (); |
b9654711 | 5005 | } |
b91455de KK |
5006 | |
5007 | if (p->mode != HImode) | |
5008 | { | |
6dd3c0a5 | 5009 | for (ref = p->wend; ref; ref = ref->next) |
b91455de | 5010 | { |
6dd3c0a5 | 5011 | lab = ref->label; |
b91455de KK |
5012 | scan = emit_insn_after (gen_consttable_window_end (lab), scan); |
5013 | } | |
5014 | } | |
b9654711 | 5015 | } |
b9654711 | 5016 | |
0d7e008e SC |
5017 | scan = emit_insn_after (gen_consttable_end (), scan); |
5018 | scan = emit_barrier_after (scan); | |
5019 | pool_size = 0; | |
6cb7eb41 | 5020 | pool_window_label = NULL; |
b91455de | 5021 | pool_window_last = 0; |
0d7e008e | 5022 | } |
b9654711 | 5023 | |
4241ecb0 R |
5024 | #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0) |
5025 | ||
5e7a8ee0 | 5026 | /* Nonzero if the insn is a move instruction which needs to be fixed. */ |
8aa2a305 JW |
5027 | |
5028 | /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the | |
735cb76e R |
5029 | CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't |
5030 | need to fix it if the input value is CONST_OK_FOR_I08. */ | |
aaf701c5 | 5031 | static bool |
6cb7eb41 | 5032 | broken_move (rtx_insn *insn) |
b9654711 | 5033 | { |
f3536097 | 5034 | if (NONJUMP_INSN_P (insn)) |
e577c183 JR |
5035 | { |
5036 | rtx pat = PATTERN (insn); | |
5037 | if (GET_CODE (pat) == PARALLEL) | |
5038 | pat = XVECEXP (pat, 0, 0); | |
5039 | if (GET_CODE (pat) == SET | |
3b962ea0 | 5040 | /* We can load any 8-bit value if we don't care what the high |
e577c183 JR |
5041 | order bits end up as. */ |
5042 | && GET_MODE (SET_DEST (pat)) != QImode | |
43c05634 | 5043 | && (CONSTANT_P (SET_SRC (pat)) |
8b0a1e0b CB |
5044 | || (GET_CODE (SET_SRC (pat)) == UNSPEC_VOLATILE |
5045 | && XINT (SET_SRC (pat), 1) == UNSPECV_SP_SWITCH_B) | |
43c05634 AO |
5046 | /* Match mova_const. */ |
5047 | || (GET_CODE (SET_SRC (pat)) == UNSPEC | |
5048 | && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA | |
5049 | && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST)) | |
3a8699c7 | 5050 | && ! (TARGET_SH2E |
1245df60 | 5051 | && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE |
e577c183 JR |
5052 | && (fp_zero_operand (SET_SRC (pat)) |
5053 | || fp_one_operand (SET_SRC (pat))) | |
50fe8924 OE |
5054 | /* In general we don't know the current setting of fpscr, so |
5055 | disable fldi. | |
18778292 R |
5056 | There is an exception if this was a register-register move |
5057 | before reload - and hence it was ascertained that we have | |
5058 | single precision setting - and in a post-reload optimization | |
5059 | we changed this to do a constant load. In that case | |
5060 | we don't have an r0 clobber, hence we must use fldi. */ | |
7a61cf6f | 5061 | && (TARGET_FMOVD |
18778292 R |
5062 | || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0)) |
5063 | == SCRATCH)) | |
f3536097 | 5064 | && REG_P (SET_DEST (pat)) |
104ee20b | 5065 | && FP_REGISTER_P (REGNO (SET_DEST (pat)))) |
157371cf AO |
5066 | && ! (TARGET_SH2A |
5067 | && GET_MODE (SET_DEST (pat)) == SImode | |
e990551a JS |
5068 | && (satisfies_constraint_I20 (SET_SRC (pat)) |
5069 | || satisfies_constraint_I28 (SET_SRC (pat)))) | |
32a7ab3d | 5070 | && ! satisfies_constraint_I08 (SET_SRC (pat))) |
aaf701c5 | 5071 | return true; |
e577c183 | 5072 | } |
d3ae8277 | 5073 | |
aaf701c5 | 5074 | return false; |
b9654711 | 5075 | } |
b9654711 | 5076 | |
50fe8924 | 5077 | /* Return true if the specified insn is a mova insn. */ |
aaf701c5 | 5078 | static bool |
6cb7eb41 | 5079 | mova_p (rtx_insn *insn) |
1245df60 | 5080 | { |
f3536097 | 5081 | return (NONJUMP_INSN_P (insn) |
1245df60 R |
5082 | && GET_CODE (PATTERN (insn)) == SET |
5083 | && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC | |
43c05634 AO |
5084 | && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA |
5085 | /* Don't match mova_const. */ | |
4241ecb0 | 5086 | && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF); |
1245df60 R |
5087 | } |
5088 | ||
078c8b08 R |
5089 | /* Fix up a mova from a switch that went out of range. */ |
5090 | static void | |
6cb7eb41 | 5091 | fixup_mova (rtx_insn *mova) |
078c8b08 | 5092 | { |
4241ecb0 | 5093 | PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode); |
078c8b08 R |
5094 | if (! flag_pic) |
5095 | { | |
4241ecb0 | 5096 | SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova); |
078c8b08 R |
5097 | INSN_CODE (mova) = -1; |
5098 | } | |
5099 | else | |
5100 | { | |
b32d5189 | 5101 | rtx_insn *worker = mova; |
19f8b229 | 5102 | rtx_code_label *lab = gen_label_rtx (); |
dc3ba671 | 5103 | rtx wpat, wpat0, wpat1, wsrc, target, base, diff; |
078c8b08 R |
5104 | |
5105 | do | |
5106 | { | |
5107 | worker = NEXT_INSN (worker); | |
f5b9e7c9 | 5108 | gcc_assert (worker |
f3536097 SZ |
5109 | && !LABEL_P (worker) |
5110 | && !JUMP_P (worker)); | |
5111 | } while (NOTE_P (worker) | |
0bf72672 | 5112 | || recog_memoized (worker) != CODE_FOR_casesi_worker_1); |
078c8b08 R |
5113 | wpat = PATTERN (worker); |
5114 | wpat0 = XVECEXP (wpat, 0, 0); | |
5115 | wpat1 = XVECEXP (wpat, 0, 1); | |
5116 | wsrc = SET_SRC (wpat0); | |
5117 | PATTERN (worker) = (gen_casesi_worker_2 | |
5118 | (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1), | |
5119 | XEXP (XVECEXP (wsrc, 0, 2), 0), lab, | |
5120 | XEXP (wpat1, 0))); | |
5121 | INSN_CODE (worker) = -1; | |
dc3ba671 RS |
5122 | target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0); |
5123 | base = gen_rtx_LABEL_REF (Pmode, lab); | |
5124 | diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF); | |
078c8b08 R |
5125 | SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff); |
5126 | INSN_CODE (mova) = -1; | |
5127 | } | |
5128 | } | |
5129 | ||
4241ecb0 R |
5130 | /* NEW_MOVA is a mova we've just encountered while scanning forward. Update |
5131 | *num_mova, and check if the new mova is not nested within the first one. | |
5132 | return 0 if *first_mova was replaced, 1 if new_mova was replaced, | |
5133 | 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */ | |
5134 | static int | |
6cb7eb41 | 5135 | untangle_mova (int *num_mova, rtx_insn **first_mova, rtx_insn *new_mova) |
4241ecb0 | 5136 | { |
c6d56443 KK |
5137 | int n_addr = 0; /* Initialization to shut up spurious warning. */ |
5138 | int f_target, n_target = 0; /* Likewise. */ | |
4241ecb0 R |
5139 | |
5140 | if (optimize) | |
5141 | { | |
77253e56 KK |
5142 | /* If NEW_MOVA has no address yet, it will be handled later. */ |
5143 | if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova)) | |
5144 | return -1; | |
5145 | ||
4241ecb0 R |
5146 | n_addr = INSN_ADDRESSES (INSN_UID (new_mova)); |
5147 | n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0))); | |
5148 | if (n_addr > n_target || n_addr + 1022 < n_target) | |
5149 | { | |
5150 | /* Change the mova into a load. | |
5151 | broken_move will then return true for it. */ | |
5152 | fixup_mova (new_mova); | |
5153 | return 1; | |
5154 | } | |
5155 | } | |
5156 | if (!(*num_mova)++) | |
5157 | { | |
5158 | *first_mova = new_mova; | |
5159 | return 2; | |
5160 | } | |
5161 | if (!optimize | |
5162 | || ((f_target | |
5163 | = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0)))) | |
5164 | >= n_target)) | |
5165 | return -1; | |
5166 | ||
5167 | (*num_mova)--; | |
5168 | if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova)) | |
5169 | > n_target - n_addr) | |
5170 | { | |
5171 | fixup_mova (*first_mova); | |
5172 | return 0; | |
5173 | } | |
5174 | else | |
5175 | { | |
5176 | fixup_mova (new_mova); | |
5177 | return 1; | |
5178 | } | |
5179 | } | |
5180 | ||
8aa2a305 JW |
5181 | /* Find the last barrier from insn FROM which is close enough to hold the |
5182 | constant pool. If we can't find one, then create one near the end of | |
5183 | the range. */ | |
6cb7eb41 DM |
5184 | static rtx_insn * |
5185 | find_barrier (int num_mova, rtx_insn *mova, rtx_insn *from) | |
b9654711 | 5186 | { |
0d7e008e SC |
5187 | int count_si = 0; |
5188 | int count_hi = 0; | |
5189 | int found_hi = 0; | |
5190 | int found_si = 0; | |
fa5322fa | 5191 | int found_di = 0; |
33f7f353 JR |
5192 | int hi_align = 2; |
5193 | int si_align = 2; | |
1245df60 | 5194 | int leading_mova = num_mova; |
6cb7eb41 DM |
5195 | rtx_insn *barrier_before_mova = NULL; |
5196 | rtx_insn *found_barrier = NULL; | |
5197 | rtx_insn *good_barrier = NULL; | |
c17f53a8 JW |
5198 | int si_limit; |
5199 | int hi_limit; | |
6cb7eb41 | 5200 | rtx_insn *orig = from; |
b32d5189 | 5201 | rtx_insn *last_got = NULL; |
6cb7eb41 | 5202 | rtx_insn *last_symoff = NULL; |
8aa2a305 JW |
5203 | |
5204 | /* For HImode: range is 510, add 4 because pc counts from address of | |
5205 | second instruction after this one, subtract 2 for the jump instruction | |
3adbde60 JW |
5206 | that we may need to emit before the table, subtract 2 for the instruction |
5207 | that fills the jump delay slot (in very rare cases, reorg will take an | |
5208 | instruction from after the constant pool or will leave the delay slot | |
5209 | empty). This gives 510. | |
8aa2a305 JW |
5210 | For SImode: range is 1020, add 4 because pc counts from address of |
5211 | second instruction after this one, subtract 2 in case pc is 2 byte | |
5212 | aligned, subtract 2 for the jump instruction that we may need to emit | |
3adbde60 JW |
5213 | before the table, subtract 2 for the instruction that fills the jump |
5214 | delay slot. This gives 1018. */ | |
c17f53a8 | 5215 | |
1245df60 | 5216 | /* The branch will always be shortened now that the reference address for |
956d6950 | 5217 | forward branches is the successor address, thus we need no longer make |
1245df60 | 5218 | adjustments to the [sh]i_limit for -O0. */ |
c17f53a8 | 5219 | |
1245df60 R |
5220 | si_limit = 1018; |
5221 | hi_limit = 510; | |
e4fa6b06 | 5222 | |
c17f53a8 | 5223 | while (from && count_si < si_limit && count_hi < hi_limit) |
0d7e008e | 5224 | { |
33f7f353 JR |
5225 | int inc = get_attr_length (from); |
5226 | int new_align = 1; | |
1245df60 | 5227 | |
4241ecb0 R |
5228 | /* If this is a label that existed at the time of the compute_alignments |
5229 | call, determine the alignment. N.B. When find_barrier recurses for | |
5230 | an out-of-reach mova, we might see labels at the start of previously | |
5231 | inserted constant tables. */ | |
f3536097 | 5232 | if (LABEL_P (from) |
4241ecb0 | 5233 | && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg) |
77008a44 R |
5234 | { |
5235 | if (optimize) | |
5236 | new_align = 1 << label_to_alignment (from); | |
f3536097 | 5237 | else if (BARRIER_P (prev_nonnote_insn (from))) |
77008a44 R |
5238 | new_align = 1 << barrier_align (from); |
5239 | else | |
5240 | new_align = 1; | |
5241 | inc = 0; | |
5242 | } | |
4241ecb0 R |
5243 | /* In case we are scanning a constant table because of recursion, check |
5244 | for explicit alignments. If the table is long, we might be forced | |
5245 | to emit the new table in front of it; the length of the alignment | |
5246 | might be the last straw. */ | |
f3536097 | 5247 | else if (NONJUMP_INSN_P (from) |
4241ecb0 R |
5248 | && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE |
5249 | && XINT (PATTERN (from), 1) == UNSPECV_ALIGN) | |
5250 | new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0)); | |
5251 | /* When we find the end of a constant table, paste the new constant | |
5252 | at the end. That is better than putting it in front because | |
5253 | this way, we don't need extra alignment for adding a 4-byte-aligned | |
5254 | mov(a) label to a 2/4 or 8/4 byte aligned table. */ | |
f3536097 | 5255 | else if (NONJUMP_INSN_P (from) |
4241ecb0 R |
5256 | && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE |
5257 | && XINT (PATTERN (from), 1) == UNSPECV_CONST_END) | |
5258 | return from; | |
8aa2a305 | 5259 | |
f3536097 | 5260 | if (BARRIER_P (from)) |
1245df60 | 5261 | { |
6cb7eb41 | 5262 | rtx_insn *next; |
33f7f353 | 5263 | |
1245df60 | 5264 | found_barrier = from; |
33f7f353 | 5265 | |
956d6950 | 5266 | /* If we are at the end of the function, or in front of an alignment |
1245df60 R |
5267 | instruction, we need not insert an extra alignment. We prefer |
5268 | this kind of barrier. */ | |
33f7f353 | 5269 | if (barrier_align (from) > 2) |
1245df60 | 5270 | good_barrier = from; |
6d4d15b8 KK |
5271 | |
5272 | /* If we are at the end of a hot/cold block, dump the constants | |
5273 | here. */ | |
5274 | next = NEXT_INSN (from); | |
5275 | if (next | |
5276 | && NOTE_P (next) | |
5277 | && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS) | |
5278 | break; | |
1245df60 | 5279 | } |
8aa2a305 | 5280 | |
8aa2a305 | 5281 | if (broken_move (from)) |
0d7e008e | 5282 | { |
1245df60 | 5283 | rtx pat, src, dst; |
ef4bddc2 | 5284 | machine_mode mode; |
1245df60 R |
5285 | |
5286 | pat = PATTERN (from); | |
5287 | if (GET_CODE (pat) == PARALLEL) | |
5288 | pat = XVECEXP (pat, 0, 0); | |
5289 | src = SET_SRC (pat); | |
5290 | dst = SET_DEST (pat); | |
5291 | mode = GET_MODE (dst); | |
c17f53a8 | 5292 | |
e938feb4 CB |
5293 | /* GOT pcrelat setting comes in pair of |
5294 | mova .L8,r0 | |
5295 | mov.l .L8,r12 | |
5296 | instructions. (plus add r0,r12). | |
5297 | Remember if we see one without the other. */ | |
50fe8924 | 5298 | if (GET_CODE (src) == UNSPEC && PIC_ADDR_P (XVECEXP (src, 0, 0))) |
b32d5189 | 5299 | last_got = last_got ? NULL : from; |
50fe8924 | 5300 | else if (PIC_ADDR_P (src)) |
b32d5189 | 5301 | last_got = last_got ? NULL : from; |
e938feb4 | 5302 | |
c17f53a8 JW |
5303 | /* We must explicitly check the mode, because sometimes the |
5304 | front end will generate code to load unsigned constants into | |
5305 | HImode targets without properly sign extending them. */ | |
225e4f43 | 5306 | if (mode == HImode |
bdb7ddcc OE |
5307 | || (mode == SImode && satisfies_constraint_I16 (src) |
5308 | && REGNO (dst) != FPUL_REG)) | |
00e94d65 | 5309 | { |
1245df60 | 5310 | found_hi += 2; |
00e94d65 RK |
5311 | /* We put the short constants before the long constants, so |
5312 | we must count the length of short constants in the range | |
5313 | for the long constants. */ | |
5314 | /* ??? This isn't optimal, but is easy to do. */ | |
1245df60 | 5315 | si_limit -= 2; |
00e94d65 | 5316 | } |
0d7e008e | 5317 | else |
1245df60 | 5318 | { |
fa5322fa AO |
5319 | /* We dump DF/DI constants before SF/SI ones, because |
5320 | the limit is the same, but the alignment requirements | |
5321 | are higher. We may waste up to 4 additional bytes | |
5322 | for alignment, and the DF/DI constant may have | |
24746a42 | 5323 | another SF/SI constant placed before it. */ |
fa5322fa AO |
5324 | if (TARGET_SHCOMPACT |
5325 | && ! found_di | |
5326 | && (mode == DFmode || mode == DImode)) | |
5327 | { | |
5328 | found_di = 1; | |
5329 | si_limit -= 8; | |
5330 | } | |
33f7f353 JR |
5331 | while (si_align > 2 && found_si + si_align - 2 > count_si) |
5332 | si_align >>= 1; | |
1245df60 R |
5333 | if (found_si > count_si) |
5334 | count_si = found_si; | |
5335 | found_si += GET_MODE_SIZE (mode); | |
5336 | if (num_mova) | |
5337 | si_limit -= GET_MODE_SIZE (mode); | |
5338 | } | |
0d7e008e | 5339 | } |
5325c0fa | 5340 | |
33f7f353 | 5341 | if (mova_p (from)) |
1245df60 | 5342 | { |
4241ecb0 | 5343 | switch (untangle_mova (&num_mova, &mova, from)) |
1245df60 | 5344 | { |
fc9c984d KK |
5345 | case 1: |
5346 | if (flag_pic) | |
5347 | { | |
5348 | rtx src = SET_SRC (PATTERN (from)); | |
5349 | if (GET_CODE (src) == CONST | |
5350 | && GET_CODE (XEXP (src, 0)) == UNSPEC | |
5351 | && XINT (XEXP (src, 0), 1) == UNSPEC_SYMOFF) | |
5352 | last_symoff = from; | |
5353 | } | |
5354 | break; | |
4241ecb0 R |
5355 | case 0: return find_barrier (0, 0, mova); |
5356 | case 2: | |
5357 | { | |
5358 | leading_mova = 0; | |
5359 | barrier_before_mova | |
5360 | = good_barrier ? good_barrier : found_barrier; | |
5361 | } | |
5362 | default: break; | |
1245df60 R |
5363 | } |
5364 | if (found_si > count_si) | |
5365 | count_si = found_si; | |
5366 | } | |
39718607 SB |
5367 | else if (JUMP_TABLE_DATA_P (from) |
5368 | && GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC) | |
1245df60 | 5369 | { |
4241ecb0 R |
5370 | if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode) |
5371 | || (num_mova | |
5372 | && (prev_nonnote_insn (from) | |
5373 | == XEXP (MOVA_LABELREF (mova), 0)))) | |
1245df60 | 5374 | num_mova--; |
10f4f635 | 5375 | if (barrier_align (next_real_insn (from)) == align_jumps_log) |
1245df60 | 5376 | { |
38e01259 | 5377 | /* We have just passed the barrier in front of the |
a0798779 R |
5378 | ADDR_DIFF_VEC, which is stored in found_barrier. Since |
5379 | the ADDR_DIFF_VEC is accessed as data, just like our pool | |
5380 | constants, this is a good opportunity to accommodate what | |
5381 | we have gathered so far. | |
1245df60 R |
5382 | If we waited any longer, we could end up at a barrier in |
5383 | front of code, which gives worse cache usage for separated | |
5384 | instruction / data caches. */ | |
a0798779 | 5385 | good_barrier = found_barrier; |
1245df60 R |
5386 | break; |
5387 | } | |
a0798779 R |
5388 | else |
5389 | { | |
5390 | rtx body = PATTERN (from); | |
5391 | inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body)); | |
5392 | } | |
1245df60 | 5393 | } |
50ceefc2 | 5394 | /* For the SH1, we generate alignments even after jumps-around-jumps. */ |
f3536097 | 5395 | else if (JUMP_P (from) |
50ceefc2 | 5396 | && ! TARGET_SH2 |
3020190e | 5397 | && ! optimize_size) |
50ceefc2 | 5398 | new_align = 4; |
5325c0fa | 5399 | |
9e3c399e CB |
5400 | /* There is a possibility that a bf is transformed into a bf/s by the |
5401 | delay slot scheduler. */ | |
39718607 | 5402 | if (JUMP_P (from) |
9e3c399e | 5403 | && get_attr_type (from) == TYPE_CBRANCH |
83d88a6d | 5404 | && ! sequence_insn_p (from)) |
9e3c399e CB |
5405 | inc += 2; |
5406 | ||
0d7e008e | 5407 | if (found_si) |
33f7f353 | 5408 | { |
50ceefc2 | 5409 | count_si += inc; |
33f7f353 JR |
5410 | if (new_align > si_align) |
5411 | { | |
318881c0 | 5412 | si_limit -= (count_si - 1) & (new_align - si_align); |
33f7f353 JR |
5413 | si_align = new_align; |
5414 | } | |
318881c0 | 5415 | count_si = (count_si + new_align - 1) & -new_align; |
33f7f353 | 5416 | } |
0d7e008e | 5417 | if (found_hi) |
33f7f353 | 5418 | { |
50ceefc2 | 5419 | count_hi += inc; |
33f7f353 JR |
5420 | if (new_align > hi_align) |
5421 | { | |
318881c0 | 5422 | hi_limit -= (count_hi - 1) & (new_align - hi_align); |
33f7f353 JR |
5423 | hi_align = new_align; |
5424 | } | |
318881c0 | 5425 | count_hi = (count_hi + new_align - 1) & -new_align; |
33f7f353 | 5426 | } |
0d7e008e SC |
5427 | from = NEXT_INSN (from); |
5428 | } | |
5429 | ||
1245df60 | 5430 | if (num_mova) |
eda44c78 R |
5431 | { |
5432 | if (leading_mova) | |
5433 | { | |
5434 | /* Try as we might, the leading mova is out of range. Change | |
5435 | it into a load (which will become a pcload) and retry. */ | |
078c8b08 | 5436 | fixup_mova (mova); |
eda44c78 R |
5437 | return find_barrier (0, 0, mova); |
5438 | } | |
5439 | else | |
5440 | { | |
5441 | /* Insert the constant pool table before the mova instruction, | |
5442 | to prevent the mova label reference from going out of range. */ | |
5443 | from = mova; | |
5444 | good_barrier = found_barrier = barrier_before_mova; | |
5445 | } | |
5446 | } | |
5325c0fa | 5447 | |
1245df60 R |
5448 | if (found_barrier) |
5449 | { | |
33f7f353 | 5450 | if (good_barrier && next_real_insn (found_barrier)) |
1245df60 | 5451 | found_barrier = good_barrier; |
1245df60 R |
5452 | } |
5453 | else | |
b9654711 | 5454 | { |
8aa2a305 JW |
5455 | /* We didn't find a barrier in time to dump our stuff, |
5456 | so we'll make one. */ | |
6cb7eb41 | 5457 | rtx_code_label *label = gen_label_rtx (); |
8aa2a305 | 5458 | |
fc9c984d KK |
5459 | /* Don't emit a constant table in the middle of insns for |
5460 | casesi_worker_2. This is a bit overkill but is enough | |
5461 | because casesi_worker_2 wouldn't appear so frequently. */ | |
5462 | if (last_symoff) | |
5463 | from = last_symoff; | |
5464 | ||
5dbcc9c0 RK |
5465 | /* If we exceeded the range, then we must back up over the last |
5466 | instruction we looked at. Otherwise, we just need to undo the | |
5467 | NEXT_INSN at the end of the loop. */ | |
7a3cb3ab KK |
5468 | if (PREV_INSN (from) != orig |
5469 | && (count_hi > hi_limit || count_si > si_limit)) | |
5dbcc9c0 RK |
5470 | from = PREV_INSN (PREV_INSN (from)); |
5471 | else | |
5472 | from = PREV_INSN (from); | |
5473 | ||
e938feb4 CB |
5474 | /* Don't emit a constant table int the middle of global pointer setting, |
5475 | since that that would move the addressing base GOT into another table. | |
5476 | We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_ | |
066922e6 CLT |
5477 | in the pool anyway, so just move up the whole constant pool. |
5478 | ||
5479 | However, avoid doing so when the last single GOT mov is the starting | |
5480 | insn itself. Going past above the start insn would create a negative | |
5481 | offset, causing errors. */ | |
5482 | if (last_got && last_got != orig) | |
e938feb4 CB |
5483 | from = PREV_INSN (last_got); |
5484 | ||
bd55b817 KK |
5485 | /* Don't insert the constant pool table at the position which |
5486 | may be the landing pad. */ | |
5487 | if (flag_exceptions | |
5488 | && CALL_P (from) | |
5489 | && find_reg_note (from, REG_EH_REGION, NULL_RTX)) | |
5490 | from = PREV_INSN (from); | |
5491 | ||
8aa2a305 JW |
5492 | /* Walk back to be just before any jump or label. |
5493 | Putting it before a label reduces the number of times the branch | |
5494 | around the constant pool table will be hit. Putting it before | |
5495 | a jump makes it more likely that the bra delay slot will be | |
5496 | filled. */ | |
f3536097 SZ |
5497 | while (NOTE_P (from) || JUMP_P (from) |
5498 | || LABEL_P (from)) | |
8aa2a305 JW |
5499 | from = PREV_INSN (from); |
5500 | ||
5969b52d KK |
5501 | /* Make sure we do not split between a call and its corresponding |
5502 | CALL_ARG_LOCATION note. */ | |
5503 | if (CALL_P (from)) | |
5504 | { | |
6cb7eb41 | 5505 | rtx_insn *next = NEXT_INSN (from); |
5969b52d KK |
5506 | if (next && NOTE_P (next) |
5507 | && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION) | |
5508 | from = next; | |
5509 | } | |
5510 | ||
0d7e008e SC |
5511 | from = emit_jump_insn_after (gen_jump (label), from); |
5512 | JUMP_LABEL (from) = label; | |
e081ed26 | 5513 | LABEL_NUSES (label) = 1; |
0d7e008e SC |
5514 | found_barrier = emit_barrier_after (from); |
5515 | emit_label_after (label, found_barrier); | |
b9654711 | 5516 | } |
b9654711 | 5517 | |
8aa2a305 | 5518 | return found_barrier; |
0d7e008e | 5519 | } |
b9654711 | 5520 | |
4787bce0 JW |
5521 | /* If the instruction INSN is implemented by a special function, and we can |
5522 | positively find the register that is used to call the sfunc, and this | |
5523 | register is not used anywhere else in this instruction - except as the | |
5524 | destination of a set, return this register; else, return 0. */ | |
1245df60 | 5525 | rtx |
84034c69 | 5526 | sfunc_uses_reg (rtx_insn *insn) |
4787bce0 JW |
5527 | { |
5528 | int i; | |
5529 | rtx pattern, part, reg_part, reg; | |
5530 | ||
f3536097 | 5531 | if (!NONJUMP_INSN_P (insn)) |
23d0939b | 5532 | return NULL_RTX; |
4787bce0 JW |
5533 | pattern = PATTERN (insn); |
5534 | if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC) | |
23d0939b | 5535 | return NULL_RTX; |
4787bce0 | 5536 | |
23d0939b | 5537 | for (reg_part = NULL_RTX, i = XVECLEN (pattern, 0) - 1; i >= 1; i--) |
4787bce0 JW |
5538 | { |
5539 | part = XVECEXP (pattern, 0, i); | |
1245df60 | 5540 | if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode) |
4787bce0 JW |
5541 | reg_part = part; |
5542 | } | |
5543 | if (! reg_part) | |
23d0939b | 5544 | return NULL_RTX; |
4787bce0 JW |
5545 | reg = XEXP (reg_part, 0); |
5546 | for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--) | |
5547 | { | |
5548 | part = XVECEXP (pattern, 0, i); | |
225e4f43 | 5549 | if (part == reg_part || GET_CODE (part) == CLOBBER) |
4787bce0 JW |
5550 | continue; |
5551 | if (reg_mentioned_p (reg, ((GET_CODE (part) == SET | |
f3536097 | 5552 | && REG_P (SET_DEST (part))) |
4787bce0 | 5553 | ? SET_SRC (part) : part))) |
23d0939b | 5554 | return NULL_RTX; |
4787bce0 JW |
5555 | } |
5556 | return reg; | |
5557 | } | |
5558 | ||
933c3ba3 JW |
5559 | /* See if the only way in which INSN uses REG is by calling it, or by |
5560 | setting it while calling it. Set *SET to a SET rtx if the register | |
5561 | is set by INSN. */ | |
aaf701c5 | 5562 | static bool |
e8a54173 | 5563 | noncall_uses_reg (rtx reg, rtx_insn *insn, rtx *set) |
933c3ba3 | 5564 | { |
4787bce0 | 5565 | rtx pattern, reg2; |
933c3ba3 JW |
5566 | |
5567 | *set = NULL_RTX; | |
5568 | ||
4787bce0 JW |
5569 | reg2 = sfunc_uses_reg (insn); |
5570 | if (reg2 && REGNO (reg2) == REGNO (reg)) | |
5571 | { | |
5572 | pattern = single_set (insn); | |
5573 | if (pattern | |
f3536097 | 5574 | && REG_P (SET_DEST (pattern)) |
4787bce0 JW |
5575 | && REGNO (reg) == REGNO (SET_DEST (pattern))) |
5576 | *set = pattern; | |
aaf701c5 | 5577 | return false; |
4787bce0 | 5578 | } |
f3536097 | 5579 | if (!CALL_P (insn)) |
933c3ba3 JW |
5580 | { |
5581 | /* We don't use rtx_equal_p because we don't care if the mode is | |
5582 | different. */ | |
5583 | pattern = single_set (insn); | |
5584 | if (pattern | |
f3536097 | 5585 | && REG_P (SET_DEST (pattern)) |
933c3ba3 JW |
5586 | && REGNO (reg) == REGNO (SET_DEST (pattern))) |
5587 | { | |
4787bce0 JW |
5588 | rtx par, part; |
5589 | int i; | |
5590 | ||
933c3ba3 | 5591 | *set = pattern; |
4787bce0 JW |
5592 | par = PATTERN (insn); |
5593 | if (GET_CODE (par) == PARALLEL) | |
5594 | for (i = XVECLEN (par, 0) - 1; i >= 0; i--) | |
5595 | { | |
5596 | part = XVECEXP (par, 0, i); | |
5597 | if (GET_CODE (part) != SET && reg_mentioned_p (reg, part)) | |
aaf701c5 | 5598 | return true; |
4787bce0 JW |
5599 | } |
5600 | return reg_mentioned_p (reg, SET_SRC (pattern)); | |
933c3ba3 JW |
5601 | } |
5602 | ||
aaf701c5 | 5603 | return true; |
933c3ba3 JW |
5604 | } |
5605 | ||
5606 | pattern = PATTERN (insn); | |
5607 | ||
5608 | if (GET_CODE (pattern) == PARALLEL) | |
5609 | { | |
5610 | int i; | |
5611 | ||
5612 | for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--) | |
5613 | if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i))) | |
aaf701c5 | 5614 | return true; |
933c3ba3 JW |
5615 | pattern = XVECEXP (pattern, 0, 0); |
5616 | } | |
5617 | ||
5618 | if (GET_CODE (pattern) == SET) | |
5619 | { | |
5620 | if (reg_mentioned_p (reg, SET_DEST (pattern))) | |
5621 | { | |
5622 | /* We don't use rtx_equal_p, because we don't care if the | |
50fe8924 | 5623 | mode is different. */ |
f3536097 | 5624 | if (!REG_P (SET_DEST (pattern)) |
933c3ba3 | 5625 | || REGNO (reg) != REGNO (SET_DEST (pattern))) |
aaf701c5 | 5626 | return true; |
933c3ba3 JW |
5627 | |
5628 | *set = pattern; | |
5629 | } | |
5630 | ||
5631 | pattern = SET_SRC (pattern); | |
5632 | } | |
5633 | ||
5634 | if (GET_CODE (pattern) != CALL | |
f3536097 | 5635 | || !MEM_P (XEXP (pattern, 0)) |
933c3ba3 | 5636 | || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0))) |
aaf701c5 | 5637 | return true; |
933c3ba3 | 5638 | |
aaf701c5 | 5639 | return false; |
933c3ba3 JW |
5640 | } |
5641 | ||
1245df60 R |
5642 | /* Given a X, a pattern of an insn or a part of it, return a mask of used |
5643 | general registers. Bits 0..15 mean that the respective registers | |
5644 | are used as inputs in the instruction. Bits 16..31 mean that the | |
5645 | registers 0..15, respectively, are used as outputs, or are clobbered. | |
5646 | IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */ | |
5647 | int | |
cf277499 | 5648 | regs_used (rtx x, int is_dest) |
1245df60 R |
5649 | { |
5650 | enum rtx_code code; | |
6f7d635c | 5651 | const char *fmt; |
1245df60 R |
5652 | int i, used = 0; |
5653 | ||
5654 | if (! x) | |
5655 | return used; | |
5656 | code = GET_CODE (x); | |
5657 | switch (code) | |
5658 | { | |
5659 | case REG: | |
5660 | if (REGNO (x) < 16) | |
5661 | return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1) | |
5662 | << (REGNO (x) + is_dest)); | |
5663 | return 0; | |
5664 | case SUBREG: | |
5665 | { | |
5666 | rtx y = SUBREG_REG (x); | |
f676971a | 5667 | |
f3536097 | 5668 | if (!REG_P (y)) |
1245df60 R |
5669 | break; |
5670 | if (REGNO (y) < 16) | |
5671 | return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1) | |
ddef6bc7 JJ |
5672 | << (REGNO (y) + |
5673 | subreg_regno_offset (REGNO (y), | |
5674 | GET_MODE (y), | |
5675 | SUBREG_BYTE (x), | |
5676 | GET_MODE (x)) + is_dest)); | |
1245df60 R |
5677 | return 0; |
5678 | } | |
5679 | case SET: | |
5680 | return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16); | |
5681 | case RETURN: | |
5682 | /* If there was a return value, it must have been indicated with USE. */ | |
5683 | return 0x00ffff00; | |
5684 | case CLOBBER: | |
5685 | is_dest = 1; | |
5686 | break; | |
5687 | case MEM: | |
5688 | is_dest = 0; | |
5689 | break; | |
5690 | case CALL: | |
5691 | used |= 0x00ff00f0; | |
5692 | break; | |
318881c0 KG |
5693 | default: |
5694 | break; | |
1245df60 R |
5695 | } |
5696 | ||
5697 | fmt = GET_RTX_FORMAT (code); | |
5698 | ||
5699 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5700 | { | |
5701 | if (fmt[i] == 'E') | |
5702 | { | |
23d0939b | 5703 | int j; |
1245df60 R |
5704 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
5705 | used |= regs_used (XVECEXP (x, i, j), is_dest); | |
5706 | } | |
5707 | else if (fmt[i] == 'e') | |
5708 | used |= regs_used (XEXP (x, i), is_dest); | |
5709 | } | |
5710 | return used; | |
5711 | } | |
5712 | ||
5713 | /* Create an instruction that prevents redirection of a conditional branch | |
956d6950 | 5714 | to the destination of the JUMP with address ADDR. |
1245df60 R |
5715 | If the branch needs to be implemented as an indirect jump, try to find |
5716 | a scratch register for it. | |
5717 | If NEED_BLOCK is 0, don't do anything unless we need a scratch register. | |
5718 | If any preceding insn that doesn't fit into a delay slot is good enough, | |
5719 | pass 1. Pass 2 if a definite blocking insn is needed. | |
5720 | -1 is used internally to avoid deep recursion. | |
5721 | If a blocking instruction is made or recognized, return it. */ | |
b32d5189 DM |
5722 | static rtx_insn * |
5723 | gen_block_redirect (rtx_insn *jump, int addr, int need_block) | |
1245df60 R |
5724 | { |
5725 | int dead = 0; | |
b32d5189 | 5726 | rtx_insn *prev = prev_nonnote_insn (jump); |
1245df60 R |
5727 | rtx dest; |
5728 | ||
5729 | /* First, check if we already have an instruction that satisfies our need. */ | |
4654c0cf | 5730 | if (prev && NONJUMP_INSN_P (prev) && ! prev->deleted ()) |
1245df60 R |
5731 | { |
5732 | if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch) | |
5733 | return prev; | |
5734 | if (GET_CODE (PATTERN (prev)) == USE | |
5735 | || GET_CODE (PATTERN (prev)) == CLOBBER | |
5736 | || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES) | |
5737 | prev = jump; | |
5738 | else if ((need_block &= ~1) < 0) | |
5739 | return prev; | |
5740 | else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect) | |
5741 | need_block = 0; | |
5742 | } | |
f9654065 R |
5743 | if (GET_CODE (PATTERN (jump)) == RETURN) |
5744 | { | |
5745 | if (! need_block) | |
5746 | return prev; | |
5747 | /* Reorg even does nasty things with return insns that cause branches | |
5748 | to go out of range - see find_end_label and callers. */ | |
a556fd39 | 5749 | return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump); |
f9654065 | 5750 | } |
1245df60 R |
5751 | /* We can't use JUMP_LABEL here because it might be undefined |
5752 | when not optimizing. */ | |
5753 | dest = XEXP (SET_SRC (PATTERN (jump)), 0); | |
5754 | /* If the branch is out of range, try to find a scratch register for it. */ | |
5755 | if (optimize | |
11f9ed1a KG |
5756 | && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092 |
5757 | > 4092 + 4098)) | |
1245df60 | 5758 | { |
b32d5189 | 5759 | rtx_insn *scan; |
1245df60 | 5760 | /* Don't look for the stack pointer as a scratch register, |
956d6950 | 5761 | it would cause trouble if an interrupt occurred. */ |
0a2aaacc | 5762 | unsigned attempt = 0x7fff, used; |
1245df60 | 5763 | int jump_left = flag_expensive_optimizations + 1; |
f676971a | 5764 | |
1245df60 R |
5765 | /* It is likely that the most recent eligible instruction is wanted for |
5766 | the delay slot. Therefore, find out which registers it uses, and | |
5767 | try to avoid using them. */ | |
f676971a | 5768 | |
318881c0 | 5769 | for (scan = jump; (scan = PREV_INSN (scan)); ) |
1245df60 R |
5770 | { |
5771 | enum rtx_code code; | |
5772 | ||
4654c0cf | 5773 | if (scan->deleted ()) |
1245df60 R |
5774 | continue; |
5775 | code = GET_CODE (scan); | |
5776 | if (code == CODE_LABEL || code == JUMP_INSN) | |
5777 | break; | |
5778 | if (code == INSN | |
5779 | && GET_CODE (PATTERN (scan)) != USE | |
5780 | && GET_CODE (PATTERN (scan)) != CLOBBER | |
5781 | && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES) | |
5782 | { | |
0a2aaacc | 5783 | attempt &= ~regs_used (PATTERN (scan), 0); |
1245df60 R |
5784 | break; |
5785 | } | |
5786 | } | |
b32d5189 | 5787 | for (used = dead = 0, scan = JUMP_LABEL_AS_INSN (jump); |
eda44c78 | 5788 | (scan = NEXT_INSN (scan)); ) |
1245df60 R |
5789 | { |
5790 | enum rtx_code code; | |
5791 | ||
4654c0cf | 5792 | if (scan->deleted ()) |
1245df60 R |
5793 | continue; |
5794 | code = GET_CODE (scan); | |
ec8e098d | 5795 | if (INSN_P (scan)) |
1245df60 R |
5796 | { |
5797 | used |= regs_used (PATTERN (scan), 0); | |
5798 | if (code == CALL_INSN) | |
5799 | used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0); | |
5800 | dead |= (used >> 16) & ~used; | |
0a2aaacc | 5801 | if (dead & attempt) |
1245df60 | 5802 | { |
0a2aaacc | 5803 | dead &= attempt; |
1245df60 R |
5804 | break; |
5805 | } | |
5806 | if (code == JUMP_INSN) | |
eda44c78 R |
5807 | { |
5808 | if (jump_left-- && simplejump_p (scan)) | |
b32d5189 | 5809 | scan = JUMP_LABEL_AS_INSN (scan); |
eda44c78 R |
5810 | else |
5811 | break; | |
5812 | } | |
1245df60 R |
5813 | } |
5814 | } | |
5815 | /* Mask out the stack pointer again, in case it was | |
5816 | the only 'free' register we have found. */ | |
5817 | dead &= 0x7fff; | |
5818 | } | |
5819 | /* If the immediate destination is still in range, check for possible | |
5820 | threading with a jump beyond the delay slot insn. | |
5821 | Don't check if we are called recursively; the jump has been or will be | |
956d6950 | 5822 | checked in a different invocation then. */ |
f676971a | 5823 | |
1245df60 R |
5824 | else if (optimize && need_block >= 0) |
5825 | { | |
b32d5189 | 5826 | rtx_insn *next = next_active_insn (next_active_insn (dest)); |
f3536097 | 5827 | if (next && JUMP_P (next) |
1245df60 | 5828 | && GET_CODE (PATTERN (next)) == SET |
ddf8ec7e | 5829 | && recog_memoized (next) == CODE_FOR_jump_compact) |
1245df60 R |
5830 | { |
5831 | dest = JUMP_LABEL (next); | |
5832 | if (dest | |
11f9ed1a | 5833 | && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092 |
9d98a694 AO |
5834 | > 4092 + 4098)) |
5835 | gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1); | |
1245df60 R |
5836 | } |
5837 | } | |
5838 | ||
5839 | if (dead) | |
5840 | { | |
c5c76735 | 5841 | rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead)); |
1245df60 R |
5842 | |
5843 | /* It would be nice if we could convert the jump into an indirect | |
956d6950 | 5844 | jump / far branch right now, and thus exposing all constituent |
1245df60 R |
5845 | instructions to further optimization. However, reorg uses |
5846 | simplejump_p to determine if there is an unconditional jump where | |
5847 | it should try to schedule instructions from the target of the | |
5848 | branch; simplejump_p fails for indirect jumps even if they have | |
5849 | a JUMP_LABEL. */ | |
b32d5189 DM |
5850 | rtx_insn *insn = emit_insn_before (gen_indirect_jump_scratch |
5851 | (reg, GEN_INT (unspec_bbr_uid++)), | |
5852 | jump); | |
10f4f635 R |
5853 | /* ??? We would like this to have the scope of the jump, but that |
5854 | scope will change when a delay slot insn of an inner scope is added. | |
5855 | Hence, after delay slot scheduling, we'll have to expect | |
5856 | NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and | |
5857 | the jump. */ | |
f676971a | 5858 | |
9d12bc68 | 5859 | INSN_LOCATION (insn) = INSN_LOCATION (jump); |
1245df60 R |
5860 | INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch; |
5861 | return insn; | |
5862 | } | |
5863 | else if (need_block) | |
5864 | /* We can't use JUMP_LABEL here because it might be undefined | |
5865 | when not optimizing. */ | |
5866 | return emit_insn_before (gen_block_branch_redirect | |
826159e5 KK |
5867 | (GEN_INT (unspec_bbr_uid++)), |
5868 | jump); | |
1245df60 R |
5869 | return prev; |
5870 | } | |
5871 | ||
5872 | #define CONDJUMP_MIN -252 | |
5873 | #define CONDJUMP_MAX 262 | |
5874 | struct far_branch | |
5875 | { | |
5876 | /* A label (to be placed) in front of the jump | |
5877 | that jumps to our ultimate destination. */ | |
b32d5189 | 5878 | rtx_insn *near_label; |
1245df60 R |
5879 | /* Where we are going to insert it if we cannot move the jump any farther, |
5880 | or the jump itself if we have picked up an existing jump. */ | |
b32d5189 | 5881 | rtx_insn *insert_place; |
1245df60 | 5882 | /* The ultimate destination. */ |
b32d5189 | 5883 | rtx_insn *far_label; |
1245df60 R |
5884 | struct far_branch *prev; |
5885 | /* If the branch has already been created, its address; | |
5886 | else the address of its first prospective user. */ | |
5887 | int address; | |
5888 | }; | |
5889 | ||
cf277499 | 5890 | static void gen_far_branch (struct far_branch *); |
1245df60 | 5891 | enum mdep_reorg_phase_e mdep_reorg_phase; |
c5b9ef02 | 5892 | static void |
cf277499 | 5893 | gen_far_branch (struct far_branch *bp) |
1245df60 | 5894 | { |
e60365d3 | 5895 | rtx_insn *insn = bp->insert_place; |
1476d1bd | 5896 | rtx_jump_insn *jump; |
19f8b229 | 5897 | rtx_code_label *label = gen_label_rtx (); |
f5b9e7c9 | 5898 | int ok; |
1245df60 R |
5899 | |
5900 | emit_label_after (label, insn); | |
5901 | if (bp->far_label) | |
5902 | { | |
5903 | jump = emit_jump_insn_after (gen_jump (bp->far_label), insn); | |
5904 | LABEL_NUSES (bp->far_label)++; | |
5905 | } | |
5906 | else | |
5907 | jump = emit_jump_insn_after (gen_return (), insn); | |
867ff7ed | 5908 | |
225e4f43 R |
5909 | /* Emit a barrier so that reorg knows that any following instructions |
5910 | are not reachable via a fall-through path. | |
fae778eb | 5911 | But don't do this when not optimizing, since we wouldn't suppress the |
225e4f43 R |
5912 | alignment for the barrier then, and could end up with out-of-range |
5913 | pc-relative loads. */ | |
5914 | if (optimize) | |
5915 | emit_barrier_after (jump); | |
1245df60 | 5916 | emit_label_after (bp->near_label, insn); |
867ff7ed CB |
5917 | |
5918 | if (bp->far_label) | |
5919 | JUMP_LABEL (jump) = bp->far_label; | |
5920 | else | |
5921 | { | |
5922 | rtx pat = PATTERN (jump); | |
5923 | gcc_assert (ANY_RETURN_P (pat)); | |
5924 | JUMP_LABEL (jump) = pat; | |
5925 | } | |
5926 | ||
1476d1bd | 5927 | ok = invert_jump (as_a <rtx_jump_insn *> (insn), label, 1); |
f5b9e7c9 | 5928 | gcc_assert (ok); |
867ff7ed | 5929 | |
f9654065 R |
5930 | /* If we are branching around a jump (rather than a return), prevent |
5931 | reorg from using an insn from the jump target as the delay slot insn - | |
5932 | when reorg did this, it pessimized code (we rather hide the delay slot) | |
5933 | and it could cause branches to go out of range. */ | |
5934 | if (bp->far_label) | |
5935 | (emit_insn_after | |
5936 | (gen_stuff_delay_slot | |
826159e5 | 5937 | (GEN_INT (unspec_bbr_uid++), |
f9654065 R |
5938 | GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)), |
5939 | insn)); | |
1245df60 R |
5940 | /* Prevent reorg from undoing our splits. */ |
5941 | gen_block_redirect (jump, bp->address += 2, 2); | |
5942 | } | |
5943 | ||
1245df60 R |
5944 | /* Fix up ADDR_DIFF_VECs. */ |
5945 | void | |
b32d5189 | 5946 | fixup_addr_diff_vecs (rtx_insn *first) |
1245df60 | 5947 | { |
b32d5189 | 5948 | rtx_insn *insn; |
33f7f353 | 5949 | |
1245df60 R |
5950 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
5951 | { | |
b32d5189 DM |
5952 | rtx vec_lab, pat, prevpat, x, braf_label; |
5953 | rtx_insn *prev; | |
1245df60 | 5954 | |
34f0d87a | 5955 | if (! JUMP_TABLE_DATA_P (insn) |
1245df60 R |
5956 | || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) |
5957 | continue; | |
5958 | pat = PATTERN (insn); | |
33f7f353 | 5959 | vec_lab = XEXP (XEXP (pat, 0), 0); |
1245df60 | 5960 | |
33f7f353 | 5961 | /* Search the matching casesi_jump_2. */ |
b32d5189 | 5962 | for (prev = as_a <rtx_insn *> (vec_lab); ; prev = PREV_INSN (prev)) |
1245df60 | 5963 | { |
f3536097 | 5964 | if (!JUMP_P (prev)) |
33f7f353 JR |
5965 | continue; |
5966 | prevpat = PATTERN (prev); | |
5967 | if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2) | |
5968 | continue; | |
5969 | x = XVECEXP (prevpat, 0, 1); | |
5970 | if (GET_CODE (x) != USE) | |
5971 | continue; | |
5972 | x = XEXP (x, 0); | |
5973 | if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab) | |
5974 | break; | |
1245df60 | 5975 | } |
157371cf AO |
5976 | /* FIXME: This is a bug in the optimizer, but it seems harmless |
5977 | to just avoid panicing. */ | |
5978 | if (!prev) | |
5979 | continue; | |
eb3881bf R |
5980 | |
5981 | /* Emit the reference label of the braf where it belongs, right after | |
5982 | the casesi_jump_2 (i.e. braf). */ | |
5983 | braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0); | |
5984 | emit_label_after (braf_label, prev); | |
5985 | ||
33f7f353 JR |
5986 | /* Fix up the ADDR_DIF_VEC to be relative |
5987 | to the reference address of the braf. */ | |
eb3881bf | 5988 | XEXP (XEXP (pat, 0), 0) = braf_label; |
1245df60 | 5989 | } |
1245df60 R |
5990 | } |
5991 | ||
33f7f353 JR |
5992 | /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following |
5993 | a barrier. Return the base 2 logarithm of the desired alignment. */ | |
1245df60 | 5994 | int |
b32d5189 | 5995 | barrier_align (rtx_insn *barrier_or_label) |
1245df60 | 5996 | { |
d7b6661b | 5997 | rtx next, pat; |
f676971a | 5998 | |
d7be3fcd KK |
5999 | if (! barrier_or_label) |
6000 | return 0; | |
6001 | ||
d7b6661b SB |
6002 | if (LABEL_P (barrier_or_label) |
6003 | && NEXT_INSN (barrier_or_label) | |
6004 | && JUMP_TABLE_DATA_P (NEXT_INSN (barrier_or_label))) | |
33f7f353 | 6005 | return 2; |
1245df60 | 6006 | |
d7b6661b SB |
6007 | if (BARRIER_P (barrier_or_label) |
6008 | && PREV_INSN (barrier_or_label) | |
6009 | && JUMP_TABLE_DATA_P (PREV_INSN (barrier_or_label))) | |
1245df60 | 6010 | { |
d7b6661b | 6011 | pat = PATTERN (PREV_INSN (barrier_or_label)); |
33f7f353 JR |
6012 | /* If this is a very small table, we want to keep the alignment after |
6013 | the table to the minimum for proper code alignment. */ | |
3020190e | 6014 | return ((optimize_size |
d042370e | 6015 | || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat)) |
832a3292 | 6016 | <= (unsigned) 1 << (CACHE_LOG - 2))) |
10f4f635 | 6017 | ? 1 << TARGET_SHMEDIA : align_jumps_log); |
1245df60 | 6018 | } |
33f7f353 | 6019 | |
d7b6661b SB |
6020 | next = next_active_insn (barrier_or_label); |
6021 | ||
6022 | if (! next) | |
6023 | return 0; | |
6024 | ||
6025 | pat = PATTERN (next); | |
6026 | ||
6027 | if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN) | |
6028 | /* This is a barrier in front of a constant table. */ | |
6029 | return 0; | |
6030 | ||
3020190e | 6031 | if (optimize_size) |
33f7f353 JR |
6032 | return 0; |
6033 | ||
4d070fd3 | 6034 | if (! TARGET_SH2 || ! optimize) |
10f4f635 | 6035 | return align_jumps_log; |
33f7f353 | 6036 | |
225e4f43 R |
6037 | /* When fixing up pcloads, a constant table might be inserted just before |
6038 | the basic block that ends with the barrier. Thus, we can't trust the | |
6039 | instruction lengths before that. */ | |
6040 | if (mdep_reorg_phase > SH_FIXUP_PCLOAD) | |
1245df60 | 6041 | { |
225e4f43 R |
6042 | /* Check if there is an immediately preceding branch to the insn beyond |
6043 | the barrier. We must weight the cost of discarding useful information | |
6044 | from the current cache line when executing this branch and there is | |
6045 | an alignment, against that of fetching unneeded insn in front of the | |
6046 | branch target when there is no alignment. */ | |
6047 | ||
f676971a EC |
6048 | /* There are two delay_slot cases to consider. One is the simple case |
6049 | where the preceding branch is to the insn beyond the barrier (simple | |
6050 | delay slot filling), and the other is where the preceding branch has | |
6051 | a delay slot that is a duplicate of the insn after the barrier | |
6052 | (fill_eager_delay_slots) and the branch is to the insn after the insn | |
b1b41fe4 CP |
6053 | after the barrier. */ |
6054 | ||
23d0939b OE |
6055 | int slot, credit; |
6056 | bool jump_to_next = false; | |
6057 | ||
d7b6661b SB |
6058 | /* Skip to the insn before the JUMP_INSN before the barrier under |
6059 | investigation. */ | |
b32d5189 | 6060 | rtx_insn *prev = prev_real_insn (prev_active_insn (barrier_or_label)); |
225e4f43 | 6061 | |
c5b9ef02 | 6062 | for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2; |
f3536097 | 6063 | credit >= 0 && prev && NONJUMP_INSN_P (prev); |
225e4f43 R |
6064 | prev = prev_real_insn (prev)) |
6065 | { | |
23d0939b | 6066 | jump_to_next = false; |
225e4f43 R |
6067 | if (GET_CODE (PATTERN (prev)) == USE |
6068 | || GET_CODE (PATTERN (prev)) == CLOBBER) | |
6069 | continue; | |
b32d5189 | 6070 | if (rtx_sequence *prev_seq = dyn_cast <rtx_sequence *> (PATTERN (prev))) |
b1b41fe4 | 6071 | { |
b32d5189 | 6072 | prev = prev_seq->insn (1); |
f676971a | 6073 | if (INSN_UID (prev) == INSN_UID (next)) |
b1b41fe4 CP |
6074 | { |
6075 | /* Delay slot was filled with insn at jump target. */ | |
23d0939b | 6076 | jump_to_next = true; |
b1b41fe4 CP |
6077 | continue; |
6078 | } | |
6079 | } | |
6080 | ||
225e4f43 R |
6081 | if (slot && |
6082 | get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES) | |
6083 | slot = 0; | |
6084 | credit -= get_attr_length (prev); | |
6085 | } | |
dc0ff1c8 | 6086 | if (prev && jump_to_label_p (prev)) |
2b9d17c7 | 6087 | { |
b32d5189 | 6088 | rtx_insn *x; |
300c5453 | 6089 | if (jump_to_next |
2b9d17c7 | 6090 | || next_real_insn (JUMP_LABEL (prev)) == next |
1594c6bc AO |
6091 | /* If relax_delay_slots() decides NEXT was redundant |
6092 | with some previous instruction, it will have | |
6093 | redirected PREV's jump to the following insn. */ | |
5d291213 | 6094 | || JUMP_LABEL (prev) == next_nonnote_insn (next) |
300c5453 AO |
6095 | /* There is no upper bound on redundant instructions |
6096 | that might have been skipped, but we must not put an | |
2b9d17c7 | 6097 | alignment where none had been before. */ |
f676971a EC |
6098 | || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))), |
6099 | (INSN_P (x) | |
2b9d17c7 | 6100 | && (INSN_CODE (x) == CODE_FOR_block_branch_redirect |
9959c8c7 R |
6101 | || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch |
6102 | || INSN_CODE (x) == CODE_FOR_stuff_delay_slot)))) | |
2b9d17c7 AH |
6103 | { |
6104 | rtx pat = PATTERN (prev); | |
6105 | if (GET_CODE (pat) == PARALLEL) | |
300c5453 | 6106 | pat = XVECEXP (pat, 0, 0); |
2b9d17c7 AH |
6107 | if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0)) |
6108 | return 0; | |
6109 | } | |
300c5453 | 6110 | } |
33f7f353 | 6111 | } |
f676971a | 6112 | |
10f4f635 | 6113 | return align_jumps_log; |
1245df60 R |
6114 | } |
6115 | ||
2148624a R |
6116 | /* If we are inside a phony loop, almost any kind of label can turn up as the |
6117 | first one in the loop. Aligning a braf label causes incorrect switch | |
6118 | destination addresses; we can detect braf labels because they are | |
6119 | followed by a BARRIER. | |
6120 | Applying loop alignment to small constant or switch tables is a waste | |
6121 | of space, so we suppress this too. */ | |
6122 | int | |
647d790d | 6123 | sh_loop_align (rtx_insn *label) |
2148624a | 6124 | { |
647d790d | 6125 | rtx_insn *next = label; |
2148624a | 6126 | |
b6a0df6c OE |
6127 | if (! optimize || optimize_size) |
6128 | return 0; | |
6129 | ||
2148624a R |
6130 | do |
6131 | next = next_nonnote_insn (next); | |
f3536097 | 6132 | while (next && LABEL_P (next)); |
2148624a R |
6133 | |
6134 | if (! next | |
2c3c49de | 6135 | || ! INSN_P (next) |
2148624a R |
6136 | || recog_memoized (next) == CODE_FOR_consttable_2) |
6137 | return 0; | |
fa5322fa | 6138 | |
10f4f635 | 6139 | return align_loops_log; |
2148624a R |
6140 | } |
6141 | ||
18dbd950 | 6142 | /* Do a final pass over the function, just before delayed branch |
933c3ba3 | 6143 | scheduling. */ |
18dbd950 | 6144 | static void |
cf277499 | 6145 | sh_reorg (void) |
0d7e008e | 6146 | { |
6cb7eb41 | 6147 | rtx_insn *first, *insn, *mova = NULL; |
1245df60 | 6148 | int num_mova; |
c5c76735 JL |
6149 | rtx r0_rtx = gen_rtx_REG (Pmode, 0); |
6150 | rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx); | |
8aa2a305 | 6151 | |
18dbd950 | 6152 | first = get_insns (); |
4241ecb0 | 6153 | max_labelno_before_reorg = max_label_num (); |
18dbd950 | 6154 | |
cb51ecd2 AO |
6155 | /* We must split call insns before introducing `mova's. If we're |
6156 | optimizing, they'll have already been split. Otherwise, make | |
6157 | sure we don't split them too late. */ | |
6158 | if (! optimize) | |
6f862f2f | 6159 | split_all_insns_noflow (); |
cb51ecd2 | 6160 | |
fa5322fa AO |
6161 | if (TARGET_SHMEDIA) |
6162 | return; | |
6163 | ||
933c3ba3 JW |
6164 | /* If relaxing, generate pseudo-ops to associate function calls with |
6165 | the symbols they call. It does no harm to not generate these | |
2eff0b9d | 6166 | pseudo-ops. However, when we can generate them, it enables the |
933c3ba3 JW |
6167 | linker to potentially relax the jsr to a bsr, and eliminate the |
6168 | register load and, possibly, the constant pool entry. */ | |
6169 | ||
1245df60 | 6170 | mdep_reorg_phase = SH_INSERT_USES_LABELS; |
933c3ba3 JW |
6171 | if (TARGET_RELAX) |
6172 | { | |
cf7c4aa6 HPN |
6173 | /* Remove all REG_LABEL_OPERAND notes. We want to use them for our |
6174 | own purposes. This works because none of the remaining passes | |
933c3ba3 JW |
6175 | need to look at them. |
6176 | ||
6177 | ??? But it may break in the future. We should use a machine | |
6178 | dependent REG_NOTE, or some other approach entirely. */ | |
6179 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
6180 | { | |
2c3c49de | 6181 | if (INSN_P (insn)) |
933c3ba3 JW |
6182 | { |
6183 | rtx note; | |
6184 | ||
cf7c4aa6 HPN |
6185 | while ((note = find_reg_note (insn, REG_LABEL_OPERAND, |
6186 | NULL_RTX)) != 0) | |
933c3ba3 JW |
6187 | remove_note (insn, note); |
6188 | } | |
6189 | } | |
6190 | ||
6191 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
6192 | { | |
19f8b229 TS |
6193 | rtx pattern, reg, set, dies; |
6194 | rtx_code_label *label; | |
6cb7eb41 | 6195 | rtx_insn *link, *scan; |
933c3ba3 JW |
6196 | int rescan = 0, foundinsn = 0; |
6197 | ||
f3536097 | 6198 | if (CALL_P (insn)) |
4787bce0 JW |
6199 | { |
6200 | pattern = PATTERN (insn); | |
933c3ba3 | 6201 | |
4787bce0 JW |
6202 | if (GET_CODE (pattern) == PARALLEL) |
6203 | pattern = XVECEXP (pattern, 0, 0); | |
6204 | if (GET_CODE (pattern) == SET) | |
6205 | pattern = SET_SRC (pattern); | |
933c3ba3 | 6206 | |
4787bce0 | 6207 | if (GET_CODE (pattern) != CALL |
f3536097 | 6208 | || !MEM_P (XEXP (pattern, 0))) |
4787bce0 | 6209 | continue; |
933c3ba3 | 6210 | |
4787bce0 JW |
6211 | reg = XEXP (XEXP (pattern, 0), 0); |
6212 | } | |
6213 | else | |
6214 | { | |
6215 | reg = sfunc_uses_reg (insn); | |
6216 | if (! reg) | |
6217 | continue; | |
6218 | } | |
933c3ba3 | 6219 | |
f3536097 | 6220 | if (!REG_P (reg)) |
933c3ba3 JW |
6221 | continue; |
6222 | ||
6fb5fa3c DB |
6223 | /* Try scanning backward to find where the register is set. */ |
6224 | link = NULL; | |
6225 | for (scan = PREV_INSN (insn); | |
f3536097 | 6226 | scan && !LABEL_P (scan); |
6fb5fa3c | 6227 | scan = PREV_INSN (scan)) |
933c3ba3 | 6228 | { |
6fb5fa3c | 6229 | if (! INSN_P (scan)) |
50fe8924 | 6230 | continue; |
933c3ba3 | 6231 | |
6fb5fa3c | 6232 | if (! reg_mentioned_p (reg, scan)) |
50fe8924 | 6233 | continue; |
933c3ba3 | 6234 | |
6fb5fa3c | 6235 | if (noncall_uses_reg (reg, scan, &set)) |
50fe8924 | 6236 | break; |
933c3ba3 | 6237 | |
6fb5fa3c DB |
6238 | if (set) |
6239 | { | |
6240 | link = scan; | |
6241 | break; | |
933c3ba3 JW |
6242 | } |
6243 | } | |
6244 | ||
6245 | if (! link) | |
6246 | continue; | |
6247 | ||
6248 | /* The register is set at LINK. */ | |
6249 | ||
6250 | /* We can only optimize the function call if the register is | |
50fe8924 OE |
6251 | being set to a symbol. In theory, we could sometimes |
6252 | optimize calls to a constant location, but the assembler | |
6253 | and linker do not support that at present. */ | |
933c3ba3 JW |
6254 | if (GET_CODE (SET_SRC (set)) != SYMBOL_REF |
6255 | && GET_CODE (SET_SRC (set)) != LABEL_REF) | |
6256 | continue; | |
6257 | ||
6258 | /* Scan forward from LINK to the place where REG dies, and | |
50fe8924 OE |
6259 | make sure that the only insns which use REG are |
6260 | themselves function calls. */ | |
933c3ba3 | 6261 | |
c1e8e6bd JW |
6262 | /* ??? This doesn't work for call targets that were allocated |
6263 | by reload, since there may not be a REG_DEAD note for the | |
6264 | register. */ | |
6265 | ||
933c3ba3 JW |
6266 | dies = NULL_RTX; |
6267 | for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan)) | |
6268 | { | |
6269 | rtx scanset; | |
6270 | ||
c1e8e6bd JW |
6271 | /* Don't try to trace forward past a CODE_LABEL if we haven't |
6272 | seen INSN yet. Ordinarily, we will only find the setting insn | |
6fb5fa3c | 6273 | if it is in the same basic block. However, |
c1e8e6bd JW |
6274 | cross-jumping can insert code labels in between the load and |
6275 | the call, and can result in situations where a single call | |
6276 | insn may have two targets depending on where we came from. */ | |
6277 | ||
f3536097 | 6278 | if (LABEL_P (scan) && ! foundinsn) |
c1e8e6bd JW |
6279 | break; |
6280 | ||
2c3c49de | 6281 | if (! INSN_P (scan)) |
933c3ba3 JW |
6282 | continue; |
6283 | ||
6284 | /* Don't try to trace forward past a JUMP. To optimize | |
50fe8924 OE |
6285 | safely, we would have to check that all the |
6286 | instructions at the jump destination did not use REG. */ | |
933c3ba3 | 6287 | |
f3536097 | 6288 | if (JUMP_P (scan)) |
933c3ba3 JW |
6289 | break; |
6290 | ||
6291 | if (! reg_mentioned_p (reg, scan)) | |
6292 | continue; | |
6293 | ||
6294 | if (noncall_uses_reg (reg, scan, &scanset)) | |
6295 | break; | |
6296 | ||
6297 | if (scan == insn) | |
6298 | foundinsn = 1; | |
6299 | ||
4787bce0 | 6300 | if (scan != insn |
f3536097 | 6301 | && (CALL_P (scan) || sfunc_uses_reg (scan))) |
933c3ba3 JW |
6302 | { |
6303 | /* There is a function call to this register other | |
50fe8924 OE |
6304 | than the one we are checking. If we optimize |
6305 | this call, we need to rescan again below. */ | |
933c3ba3 JW |
6306 | rescan = 1; |
6307 | } | |
6308 | ||
6309 | /* ??? We shouldn't have to worry about SCANSET here. | |
6310 | We should just be able to check for a REG_DEAD note | |
6311 | on a function call. However, the REG_DEAD notes are | |
6312 | apparently not dependable around libcalls; c-torture | |
6313 | execute/920501-2 is a test case. If SCANSET is set, | |
6314 | then this insn sets the register, so it must have | |
6315 | died earlier. Unfortunately, this will only handle | |
6316 | the cases in which the register is, in fact, set in a | |
6317 | later insn. */ | |
6318 | ||
6319 | /* ??? We shouldn't have to use FOUNDINSN here. | |
6fb5fa3c DB |
6320 | This dates back to when we used LOG_LINKS to find |
6321 | the most recent insn which sets the register. */ | |
933c3ba3 JW |
6322 | |
6323 | if (foundinsn | |
6324 | && (scanset | |
6325 | || find_reg_note (scan, REG_DEAD, reg))) | |
6326 | { | |
6327 | dies = scan; | |
6328 | break; | |
6329 | } | |
6330 | } | |
6331 | ||
6332 | if (! dies) | |
6333 | { | |
6334 | /* Either there was a branch, or some insn used REG | |
50fe8924 | 6335 | other than as a function call address. */ |
933c3ba3 JW |
6336 | continue; |
6337 | } | |
6338 | ||
cf7c4aa6 | 6339 | /* Create a code label, and put it in a REG_LABEL_OPERAND note |
50fe8924 OE |
6340 | on the insn which sets the register, and on each call insn |
6341 | which uses the register. In final_prescan_insn we look for | |
6342 | the REG_LABEL_OPERAND notes, and output the appropriate label | |
6343 | or pseudo-op. */ | |
933c3ba3 JW |
6344 | |
6345 | label = gen_label_rtx (); | |
65c5f2a6 ILT |
6346 | add_reg_note (link, REG_LABEL_OPERAND, label); |
6347 | add_reg_note (insn, REG_LABEL_OPERAND, label); | |
933c3ba3 JW |
6348 | if (rescan) |
6349 | { | |
6350 | scan = link; | |
6351 | do | |
6352 | { | |
4787bce0 JW |
6353 | rtx reg2; |
6354 | ||
933c3ba3 JW |
6355 | scan = NEXT_INSN (scan); |
6356 | if (scan != insn | |
f3536097 | 6357 | && ((CALL_P (scan) |
4787bce0 JW |
6358 | && reg_mentioned_p (reg, scan)) |
6359 | || ((reg2 = sfunc_uses_reg (scan)) | |
6360 | && REGNO (reg2) == REGNO (reg)))) | |
65c5f2a6 | 6361 | add_reg_note (scan, REG_LABEL_OPERAND, label); |
933c3ba3 JW |
6362 | } |
6363 | while (scan != dies); | |
6364 | } | |
6365 | } | |
6366 | } | |
6367 | ||
33f7f353 JR |
6368 | if (TARGET_SH2) |
6369 | fixup_addr_diff_vecs (first); | |
1245df60 R |
6370 | |
6371 | if (optimize) | |
6372 | { | |
1245df60 R |
6373 | mdep_reorg_phase = SH_SHORTEN_BRANCHES0; |
6374 | shorten_branches (first); | |
6375 | } | |
6dd3c0a5 | 6376 | |
933c3ba3 JW |
6377 | /* Scan the function looking for move instructions which have to be |
6378 | changed to pc-relative loads and insert the literal tables. */ | |
1245df60 R |
6379 | mdep_reorg_phase = SH_FIXUP_PCLOAD; |
6380 | for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn)) | |
0d7e008e | 6381 | { |
1245df60 R |
6382 | if (mova_p (insn)) |
6383 | { | |
078c8b08 R |
6384 | /* ??? basic block reordering can move a switch table dispatch |
6385 | below the switch table. Check if that has happened. | |
6386 | We only have the addresses available when optimizing; but then, | |
6387 | this check shouldn't be needed when not optimizing. */ | |
4241ecb0 | 6388 | if (!untangle_mova (&num_mova, &mova, insn)) |
078c8b08 | 6389 | { |
4241ecb0 R |
6390 | insn = mova; |
6391 | num_mova = 0; | |
078c8b08 | 6392 | } |
1245df60 | 6393 | } |
34f0d87a | 6394 | else if (JUMP_TABLE_DATA_P (insn) |
1245df60 | 6395 | && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC |
4241ecb0 R |
6396 | && num_mova |
6397 | /* ??? loop invariant motion can also move a mova out of a | |
6398 | loop. Since loop does this code motion anyway, maybe we | |
6399 | should wrap UNSPEC_MOVA into a CONST, so that reload can | |
6400 | move it back. */ | |
6401 | && ((num_mova > 1 | |
6402 | && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode) | |
6403 | || (prev_nonnote_insn (insn) | |
6404 | == XEXP (MOVA_LABELREF (mova), 0)))) | |
1245df60 | 6405 | { |
b32d5189 | 6406 | rtx_insn *scan; |
1245df60 R |
6407 | int total; |
6408 | ||
6409 | num_mova--; | |
6410 | ||
6411 | /* Some code might have been inserted between the mova and | |
6412 | its ADDR_DIFF_VEC. Check if the mova is still in range. */ | |
6413 | for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan)) | |
33f7f353 | 6414 | total += get_attr_length (scan); |
1245df60 R |
6415 | |
6416 | /* range of mova is 1020, add 4 because pc counts from address of | |
6417 | second instruction after this one, subtract 2 in case pc is 2 | |
6418 | byte aligned. Possible alignment needed for the ADDR_DIFF_VEC | |
956d6950 | 6419 | cancels out with alignment effects of the mova itself. */ |
1245df60 R |
6420 | if (total > 1022) |
6421 | { | |
6422 | /* Change the mova into a load, and restart scanning | |
6423 | there. broken_move will then return true for mova. */ | |
078c8b08 | 6424 | fixup_mova (mova); |
1245df60 R |
6425 | insn = mova; |
6426 | } | |
6427 | } | |
078c8b08 | 6428 | if (broken_move (insn) |
f3536097 | 6429 | || (NONJUMP_INSN_P (insn) |
078c8b08 | 6430 | && recog_memoized (insn) == CODE_FOR_casesi_worker_2)) |
0d7e008e | 6431 | { |
6cb7eb41 | 6432 | rtx_insn *scan; |
8aa2a305 JW |
6433 | /* Scan ahead looking for a barrier to stick the constant table |
6434 | behind. */ | |
6cb7eb41 | 6435 | rtx_insn *barrier = find_barrier (num_mova, mova, insn); |
a5d567ec DM |
6436 | rtx_insn *last_float_move = NULL; |
6437 | rtx last_float = 0, *last_float_addr = NULL; | |
078c8b08 | 6438 | int need_aligned_label = 0; |
b9654711 | 6439 | |
1245df60 R |
6440 | if (num_mova && ! mova_p (mova)) |
6441 | { | |
6442 | /* find_barrier had to change the first mova into a | |
6443 | pcload; thus, we have to start with this new pcload. */ | |
6444 | insn = mova; | |
6445 | num_mova = 0; | |
6446 | } | |
16bea517 | 6447 | /* Now find all the moves between the points and modify them. */ |
0d7e008e SC |
6448 | for (scan = insn; scan != barrier; scan = NEXT_INSN (scan)) |
6449 | { | |
f3536097 | 6450 | if (LABEL_P (scan)) |
1245df60 | 6451 | last_float = 0; |
f3536097 | 6452 | if (NONJUMP_INSN_P (scan) |
078c8b08 R |
6453 | && recog_memoized (scan) == CODE_FOR_casesi_worker_2) |
6454 | need_aligned_label = 1; | |
0d7e008e SC |
6455 | if (broken_move (scan)) |
6456 | { | |
e577c183 JR |
6457 | rtx *patp = &PATTERN (scan), pat = *patp; |
6458 | rtx src, dst; | |
0d7e008e | 6459 | rtx lab; |
0d7e008e | 6460 | rtx newsrc; |
ef4bddc2 | 6461 | machine_mode mode; |
e577c183 JR |
6462 | |
6463 | if (GET_CODE (pat) == PARALLEL) | |
6464 | patp = &XVECEXP (pat, 0, 0), pat = *patp; | |
6465 | src = SET_SRC (pat); | |
6466 | dst = SET_DEST (pat); | |
6467 | mode = GET_MODE (dst); | |
0d7e008e | 6468 | |
bdb7ddcc | 6469 | if (mode == SImode && satisfies_constraint_I16 (src) |
225e4f43 | 6470 | && REGNO (dst) != FPUL_REG) |
0d7e008e | 6471 | { |
23ed92ca | 6472 | int offset = 0; |
8aa2a305 | 6473 | |
0d7e008e | 6474 | mode = HImode; |
d3ae8277 | 6475 | while (GET_CODE (dst) == SUBREG) |
23ed92ca | 6476 | { |
ddef6bc7 JJ |
6477 | offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)), |
6478 | GET_MODE (SUBREG_REG (dst)), | |
6479 | SUBREG_BYTE (dst), | |
6480 | GET_MODE (dst)); | |
23ed92ca JW |
6481 | dst = SUBREG_REG (dst); |
6482 | } | |
c5c76735 | 6483 | dst = gen_rtx_REG (HImode, REGNO (dst) + offset); |
0d7e008e | 6484 | } |
f3536097 | 6485 | if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst))) |
1245df60 | 6486 | { |
b8794099 | 6487 | /* This must be an insn that clobbers r0. */ |
0f2b41b2 AO |
6488 | rtx *clobberp = &XVECEXP (PATTERN (scan), 0, |
6489 | XVECLEN (PATTERN (scan), 0) | |
6490 | - 1); | |
6491 | rtx clobber = *clobberp; | |
b8794099 | 6492 | |
f5b9e7c9 NS |
6493 | gcc_assert (GET_CODE (clobber) == CLOBBER |
6494 | && rtx_equal_p (XEXP (clobber, 0), r0_rtx)); | |
b8794099 | 6495 | |
1245df60 R |
6496 | if (last_float |
6497 | && reg_set_between_p (r0_rtx, last_float_move, scan)) | |
6498 | last_float = 0; | |
3503150c RS |
6499 | if (last_float |
6500 | && TARGET_SHCOMPACT | |
6501 | && GET_MODE_SIZE (mode) != 4 | |
6502 | && GET_MODE_SIZE (GET_MODE (last_float)) == 4) | |
6503 | last_float = 0; | |
1245df60 R |
6504 | lab = add_constant (src, mode, last_float); |
6505 | if (lab) | |
6506 | emit_insn_before (gen_mova (lab), scan); | |
6507 | else | |
b8794099 R |
6508 | { |
6509 | /* There will be a REG_UNUSED note for r0 on | |
6510 | LAST_FLOAT_MOVE; we have to change it to REG_INC, | |
6511 | lest reorg:mark_target_live_regs will not | |
6512 | consider r0 to be used, and we end up with delay | |
475f26dd | 6513 | slot insn in front of SCAN that clobbers r0. */ |
b8794099 R |
6514 | rtx note |
6515 | = find_regno_note (last_float_move, REG_UNUSED, 0); | |
6516 | ||
ab1672a3 JW |
6517 | /* If we are not optimizing, then there may not be |
6518 | a note. */ | |
6519 | if (note) | |
81f40b79 | 6520 | PUT_REG_NOTE_KIND (note, REG_INC); |
b8794099 R |
6521 | |
6522 | *last_float_addr = r0_inc_rtx; | |
6523 | } | |
1245df60 R |
6524 | last_float_move = scan; |
6525 | last_float = src; | |
57d38024 | 6526 | newsrc = gen_const_mem (mode, |
318881c0 | 6527 | (((TARGET_SH4 && ! TARGET_FMOVD) |
225e4f43 | 6528 | || REGNO (dst) == FPUL_REG) |
1245df60 R |
6529 | ? r0_inc_rtx |
6530 | : r0_rtx)); | |
6531 | last_float_addr = &XEXP (newsrc, 0); | |
b8794099 R |
6532 | |
6533 | /* Remove the clobber of r0. */ | |
0f2b41b2 AO |
6534 | *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber), |
6535 | gen_rtx_SCRATCH (Pmode)); | |
1245df60 | 6536 | } |
1a66cd67 | 6537 | /* This is a mova needing a label. Create it. */ |
43c05634 AO |
6538 | else if (GET_CODE (src) == UNSPEC |
6539 | && XINT (src, 1) == UNSPEC_MOVA | |
6540 | && GET_CODE (XVECEXP (src, 0, 0)) == CONST) | |
1a66cd67 | 6541 | { |
43c05634 | 6542 | lab = add_constant (XVECEXP (src, 0, 0), mode, 0); |
1a66cd67 | 6543 | newsrc = gen_rtx_LABEL_REF (VOIDmode, lab); |
e69d1422 | 6544 | newsrc = gen_rtx_UNSPEC (SImode, |
4773afa4 AO |
6545 | gen_rtvec (1, newsrc), |
6546 | UNSPEC_MOVA); | |
1a66cd67 | 6547 | } |
8b0a1e0b CB |
6548 | else if (GET_CODE (src) == UNSPEC_VOLATILE |
6549 | && XINT (src, 1) == UNSPECV_SP_SWITCH_B) | |
6550 | { | |
6551 | newsrc = XVECEXP (src, 0, 0); | |
6552 | XVECEXP (src, 0, 0) = gen_const_mem (mode, newsrc); | |
6553 | INSN_CODE (scan) = -1; | |
6554 | continue; | |
6555 | } | |
1245df60 R |
6556 | else |
6557 | { | |
6558 | lab = add_constant (src, mode, 0); | |
542a8afa RH |
6559 | newsrc = gen_rtx_LABEL_REF (VOIDmode, lab); |
6560 | newsrc = gen_const_mem (mode, newsrc); | |
1245df60 | 6561 | } |
f7df4a84 | 6562 | *patp = gen_rtx_SET (dst, newsrc); |
e577c183 | 6563 | INSN_CODE (scan) = -1; |
0d7e008e SC |
6564 | } |
6565 | } | |
078c8b08 | 6566 | dump_table (need_aligned_label ? insn : 0, barrier); |
1245df60 | 6567 | insn = barrier; |
0d7e008e SC |
6568 | } |
6569 | } | |
533ab6c4 | 6570 | label_ref_list_d::pool.release (); |
4241ecb0 R |
6571 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
6572 | PUT_MODE (insn, VOIDmode); | |
6573 | ||
1245df60 | 6574 | mdep_reorg_phase = SH_SHORTEN_BRANCHES1; |
9d98a694 | 6575 | INSN_ADDRESSES_FREE (); |
1245df60 R |
6576 | split_branches (first); |
6577 | ||
6578 | /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it | |
a920aefe | 6579 | also has an effect on the register that holds the address of the sfunc. |
1245df60 R |
6580 | Insert an extra dummy insn in front of each sfunc that pretends to |
6581 | use this register. */ | |
6582 | if (flag_delayed_branch) | |
6583 | { | |
6584 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
6585 | { | |
6586 | rtx reg = sfunc_uses_reg (insn); | |
6587 | ||
6588 | if (! reg) | |
6589 | continue; | |
6590 | emit_insn_before (gen_use_sfunc_addr (reg), insn); | |
6591 | } | |
6592 | } | |
6593 | mdep_reorg_phase = SH_AFTER_MDEP_REORG; | |
6594 | } | |
6595 | ||
50fe8924 | 6596 | /* Return the UID of the insn that follows the specified label. */ |
1245df60 | 6597 | int |
cf277499 | 6598 | get_dest_uid (rtx label, int max_uid) |
1245df60 | 6599 | { |
b32d5189 | 6600 | rtx_insn *dest = next_real_insn (label); |
1245df60 R |
6601 | int dest_uid; |
6602 | if (! dest) | |
6603 | /* This can happen for an undefined label. */ | |
6604 | return 0; | |
6605 | dest_uid = INSN_UID (dest); | |
6606 | /* If this is a newly created branch redirection blocking instruction, | |
6607 | we cannot index the branch_uid or insn_addresses arrays with its | |
6608 | uid. But then, we won't need to, because the actual destination is | |
6609 | the following branch. */ | |
6610 | while (dest_uid >= max_uid) | |
6611 | { | |
6612 | dest = NEXT_INSN (dest); | |
6613 | dest_uid = INSN_UID (dest); | |
6614 | } | |
f3536097 | 6615 | if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN) |
1245df60 R |
6616 | return 0; |
6617 | return dest_uid; | |
6618 | } | |
6619 | ||
6620 | /* Split condbranches that are out of range. Also add clobbers for | |
6621 | scratch registers that are needed in far jumps. | |
6622 | We do this before delay slot scheduling, so that it can take our | |
6623 | newly created instructions into account. It also allows us to | |
6624 | find branches with common targets more easily. */ | |
1245df60 | 6625 | static void |
6cb7eb41 | 6626 | split_branches (rtx_insn *first) |
1245df60 | 6627 | { |
6cb7eb41 | 6628 | rtx_insn *insn; |
1245df60 R |
6629 | struct far_branch **uid_branch, *far_branch_list = 0; |
6630 | int max_uid = get_max_uid (); | |
f5b9e7c9 | 6631 | int ok; |
1245df60 R |
6632 | |
6633 | /* Find out which branches are out of range. */ | |
1245df60 R |
6634 | shorten_branches (first); |
6635 | ||
6636 | uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch); | |
2e09e75a | 6637 | memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch); |
1245df60 R |
6638 | |
6639 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 6640 | if (! INSN_P (insn)) |
1245df60 | 6641 | continue; |
4654c0cf | 6642 | else if (insn->deleted ()) |
1245df60 R |
6643 | { |
6644 | /* Shorten_branches would split this instruction again, | |
6645 | so transform it into a note. */ | |
a38e7aa5 | 6646 | SET_INSN_DELETED (insn); |
1245df60 | 6647 | } |
39718607 | 6648 | else if (JUMP_P (insn)) |
1245df60 R |
6649 | { |
6650 | enum attr_type type = get_attr_type (insn); | |
6651 | if (type == TYPE_CBRANCH) | |
6652 | { | |
b32d5189 | 6653 | rtx_insn *next, *beyond; |
f676971a | 6654 | |
1245df60 R |
6655 | if (get_attr_length (insn) > 4) |
6656 | { | |
6657 | rtx src = SET_SRC (PATTERN (insn)); | |
1245df60 | 6658 | rtx olabel = XEXP (XEXP (src, 1), 0); |
9d98a694 | 6659 | int addr = INSN_ADDRESSES (INSN_UID (insn)); |
b32d5189 | 6660 | rtx_insn *label = 0; |
1245df60 R |
6661 | int dest_uid = get_dest_uid (olabel, max_uid); |
6662 | struct far_branch *bp = uid_branch[dest_uid]; | |
f676971a | 6663 | |
1245df60 | 6664 | /* redirect_jump needs a valid JUMP_LABEL, and it might delete |
25938114 | 6665 | the label if the LABEL_NUSES count drops to zero. There is |
1245df60 R |
6666 | always a jump_optimize pass that sets these values, but it |
6667 | proceeds to delete unreferenced code, and then if not | |
956d6950 | 6668 | optimizing, to un-delete the deleted instructions, thus |
1245df60 R |
6669 | leaving labels with too low uses counts. */ |
6670 | if (! optimize) | |
6671 | { | |
6672 | JUMP_LABEL (insn) = olabel; | |
6673 | LABEL_NUSES (olabel)++; | |
6674 | } | |
6675 | if (! bp) | |
6676 | { | |
6677 | bp = (struct far_branch *) alloca (sizeof *bp); | |
6678 | uid_branch[dest_uid] = bp; | |
6679 | bp->prev = far_branch_list; | |
6680 | far_branch_list = bp; | |
b32d5189 DM |
6681 | bp->far_label = as_a <rtx_insn *> ( |
6682 | XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), | |
6683 | 0)); | |
1245df60 R |
6684 | LABEL_NUSES (bp->far_label)++; |
6685 | } | |
6686 | else | |
6687 | { | |
6688 | label = bp->near_label; | |
6689 | if (! label && bp->address - addr >= CONDJUMP_MIN) | |
6690 | { | |
b32d5189 | 6691 | rtx_insn *block = bp->insert_place; |
1245df60 R |
6692 | |
6693 | if (GET_CODE (PATTERN (block)) == RETURN) | |
6694 | block = PREV_INSN (block); | |
6695 | else | |
6696 | block = gen_block_redirect (block, | |
6697 | bp->address, 2); | |
6698 | label = emit_label_after (gen_label_rtx (), | |
6699 | PREV_INSN (block)); | |
6700 | bp->near_label = label; | |
6701 | } | |
6702 | else if (label && ! NEXT_INSN (label)) | |
eda44c78 R |
6703 | { |
6704 | if (addr + 2 - bp->address <= CONDJUMP_MAX) | |
6705 | bp->insert_place = insn; | |
6706 | else | |
6707 | gen_far_branch (bp); | |
6708 | } | |
1245df60 R |
6709 | } |
6710 | if (! label | |
318881c0 | 6711 | || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN)) |
1245df60 R |
6712 | { |
6713 | bp->near_label = label = gen_label_rtx (); | |
6714 | bp->insert_place = insn; | |
6715 | bp->address = addr; | |
6716 | } | |
1476d1bd | 6717 | ok = redirect_jump (as_a <rtx_jump_insn *> (insn), label, 0); |
f5b9e7c9 | 6718 | gcc_assert (ok); |
1245df60 R |
6719 | } |
6720 | else | |
6721 | { | |
6722 | /* get_attr_length (insn) == 2 */ | |
6723 | /* Check if we have a pattern where reorg wants to redirect | |
6724 | the branch to a label from an unconditional branch that | |
6725 | is too far away. */ | |
6726 | /* We can't use JUMP_LABEL here because it might be undefined | |
6727 | when not optimizing. */ | |
33f7f353 | 6728 | /* A syntax error might cause beyond to be NULL_RTX. */ |
1245df60 R |
6729 | beyond |
6730 | = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), | |
6731 | 0)); | |
f676971a | 6732 | |
33f7f353 | 6733 | if (beyond |
f3536097 | 6734 | && (JUMP_P (beyond) |
b94544e4 | 6735 | || ((beyond = next_active_insn (beyond)) |
f3536097 | 6736 | && JUMP_P (beyond))) |
1245df60 | 6737 | && GET_CODE (PATTERN (beyond)) == SET |
ddf8ec7e | 6738 | && recog_memoized (beyond) == CODE_FOR_jump_compact |
9d98a694 AO |
6739 | && ((INSN_ADDRESSES |
6740 | (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0))) | |
11f9ed1a | 6741 | - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252) |
1245df60 R |
6742 | > 252 + 258 + 2)) |
6743 | gen_block_redirect (beyond, | |
9d98a694 | 6744 | INSN_ADDRESSES (INSN_UID (beyond)), 1); |
1245df60 | 6745 | } |
f676971a | 6746 | |
1245df60 R |
6747 | next = next_active_insn (insn); |
6748 | ||
a7d6f306 KK |
6749 | if (next |
6750 | && (JUMP_P (next) | |
6751 | || ((next = next_active_insn (next)) | |
6752 | && JUMP_P (next))) | |
1245df60 | 6753 | && GET_CODE (PATTERN (next)) == SET |
ddf8ec7e | 6754 | && recog_memoized (next) == CODE_FOR_jump_compact |
9d98a694 AO |
6755 | && ((INSN_ADDRESSES |
6756 | (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0))) | |
11f9ed1a | 6757 | - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252) |
1245df60 | 6758 | > 252 + 258 + 2)) |
9d98a694 | 6759 | gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1); |
1245df60 R |
6760 | } |
6761 | else if (type == TYPE_JUMP || type == TYPE_RETURN) | |
6762 | { | |
9d98a694 | 6763 | int addr = INSN_ADDRESSES (INSN_UID (insn)); |
b32d5189 | 6764 | rtx_insn *far_label = 0; |
1245df60 R |
6765 | int dest_uid = 0; |
6766 | struct far_branch *bp; | |
6767 | ||
6768 | if (type == TYPE_JUMP) | |
6769 | { | |
4e417af3 KK |
6770 | if (CROSSING_JUMP_P (insn)) |
6771 | { | |
6772 | emit_insn_before (gen_block_branch_redirect (const0_rtx), | |
6773 | insn); | |
6774 | continue; | |
6775 | } | |
6776 | ||
b32d5189 DM |
6777 | far_label = as_a <rtx_insn *> ( |
6778 | XEXP (SET_SRC (PATTERN (insn)), 0)); | |
1245df60 R |
6779 | dest_uid = get_dest_uid (far_label, max_uid); |
6780 | if (! dest_uid) | |
6781 | { | |
6782 | /* Parse errors can lead to labels outside | |
6783 | the insn stream. */ | |
6784 | if (! NEXT_INSN (far_label)) | |
6785 | continue; | |
6786 | ||
6787 | if (! optimize) | |
6788 | { | |
6789 | JUMP_LABEL (insn) = far_label; | |
6790 | LABEL_NUSES (far_label)++; | |
6791 | } | |
1476d1bd | 6792 | redirect_jump (as_a <rtx_jump_insn *> (insn), ret_rtx, 1); |
1245df60 R |
6793 | far_label = 0; |
6794 | } | |
6795 | } | |
6796 | bp = uid_branch[dest_uid]; | |
6797 | if (! bp) | |
6798 | { | |
6799 | bp = (struct far_branch *) alloca (sizeof *bp); | |
6800 | uid_branch[dest_uid] = bp; | |
6801 | bp->prev = far_branch_list; | |
6802 | far_branch_list = bp; | |
6803 | bp->near_label = 0; | |
6804 | bp->far_label = far_label; | |
6805 | if (far_label) | |
6806 | LABEL_NUSES (far_label)++; | |
6807 | } | |
6808 | else if (bp->near_label && ! NEXT_INSN (bp->near_label)) | |
6809 | if (addr - bp->address <= CONDJUMP_MAX) | |
6810 | emit_label_after (bp->near_label, PREV_INSN (insn)); | |
6811 | else | |
6812 | { | |
6813 | gen_far_branch (bp); | |
6814 | bp->near_label = 0; | |
6815 | } | |
6816 | else | |
6817 | bp->near_label = 0; | |
6818 | bp->address = addr; | |
6819 | bp->insert_place = insn; | |
6820 | if (! far_label) | |
6821 | emit_insn_before (gen_block_branch_redirect (const0_rtx), insn); | |
6822 | else | |
6823 | gen_block_redirect (insn, addr, bp->near_label ? 2 : 0); | |
6824 | } | |
6825 | } | |
6826 | /* Generate all pending far branches, | |
6827 | and free our references to the far labels. */ | |
6828 | while (far_branch_list) | |
6829 | { | |
6830 | if (far_branch_list->near_label | |
6831 | && ! NEXT_INSN (far_branch_list->near_label)) | |
6832 | gen_far_branch (far_branch_list); | |
6833 | if (optimize | |
6834 | && far_branch_list->far_label | |
6835 | && ! --LABEL_NUSES (far_branch_list->far_label)) | |
6836 | delete_insn (far_branch_list->far_label); | |
6837 | far_branch_list = far_branch_list->prev; | |
6838 | } | |
a0798779 R |
6839 | |
6840 | /* Instruction length information is no longer valid due to the new | |
6841 | instructions that have been generated. */ | |
6842 | init_insn_lengths (); | |
b9654711 SC |
6843 | } |
6844 | ||
8aa2a305 | 6845 | /* Dump out instruction addresses, which is useful for debugging the |
933c3ba3 JW |
6846 | constant pool table stuff. |
6847 | ||
6848 | If relaxing, output the label and pseudo-ops used to link together | |
50fe8924 | 6849 | calls and the instruction which set the registers. |
8aa2a305 | 6850 | |
50fe8924 | 6851 | ??? The addresses printed by this routine for insns are nonsense for |
8aa2a305 JW |
6852 | insns which are inside of a sequence where none of the inner insns have |
6853 | variable length. This is because the second pass of shorten_branches | |
6854 | does not bother to update them. */ | |
8e87e161 | 6855 | void |
6cb7eb41 | 6856 | final_prescan_insn (rtx_insn *insn, rtx *opvec ATTRIBUTE_UNUSED, |
cf277499 | 6857 | int noperands ATTRIBUTE_UNUSED) |
b9654711 | 6858 | { |
8aa2a305 | 6859 | if (TARGET_DUMPISIZE) |
9d98a694 | 6860 | fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn))); |
933c3ba3 JW |
6861 | |
6862 | if (TARGET_RELAX) | |
6863 | { | |
6864 | rtx note; | |
6865 | ||
cf7c4aa6 | 6866 | note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX); |
933c3ba3 JW |
6867 | if (note) |
6868 | { | |
6869 | rtx pattern; | |
6870 | ||
6871 | pattern = PATTERN (insn); | |
4b7d2f07 R |
6872 | if (GET_CODE (pattern) == PARALLEL) |
6873 | pattern = XVECEXP (pattern, 0, 0); | |
f5b9e7c9 NS |
6874 | switch (GET_CODE (pattern)) |
6875 | { | |
f5b9e7c9 NS |
6876 | case SET: |
6877 | if (GET_CODE (SET_SRC (pattern)) != CALL | |
6878 | && get_attr_type (insn) != TYPE_SFUNC) | |
6879 | { | |
6880 | targetm.asm_out.internal_label | |
6881 | (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0))); | |
6882 | break; | |
6883 | } | |
6884 | /* else FALLTHROUGH */ | |
6885 | case CALL: | |
6886 | asm_fprintf (asm_out_file, "\t.uses %LL%d\n", | |
6887 | CODE_LABEL_NUMBER (XEXP (note, 0))); | |
6888 | break; | |
6889 | ||
6890 | default: | |
6891 | gcc_unreachable (); | |
6892 | } | |
933c3ba3 JW |
6893 | } |
6894 | } | |
0d7e008e | 6895 | } |
b9654711 | 6896 | |
8aa2a305 | 6897 | /* Dump out any constants accumulated in the final pass. These will |
38e01259 | 6898 | only be labels. */ |
318881c0 | 6899 | const char * |
cf277499 | 6900 | output_jump_label_table (void) |
0d7e008e | 6901 | { |
8aa2a305 JW |
6902 | int i; |
6903 | ||
6904 | if (pool_size) | |
6905 | { | |
6906 | fprintf (asm_out_file, "\t.align 2\n"); | |
6907 | for (i = 0; i < pool_size; i++) | |
6908 | { | |
6909 | pool_node *p = &pool_vector[i]; | |
6910 | ||
4977bab6 | 6911 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
8aa2a305 JW |
6912 | CODE_LABEL_NUMBER (p->label)); |
6913 | output_asm_insn (".long %O0", &p->value); | |
6914 | } | |
6915 | pool_size = 0; | |
6916 | } | |
b9654711 | 6917 | |
8aa2a305 JW |
6918 | return ""; |
6919 | } | |
6920 | \f | |
6921 | /* A full frame looks like: | |
16bea517 JW |
6922 | |
6923 | arg-5 | |
6924 | arg-4 | |
6925 | [ if current_function_anonymous_args | |
6926 | arg-3 | |
6927 | arg-2 | |
6928 | arg-1 | |
6929 | arg-0 ] | |
6930 | saved-fp | |
6931 | saved-r10 | |
6932 | saved-r11 | |
6933 | saved-r12 | |
6934 | saved-pr | |
6935 | local-n | |
6936 | .. | |
6937 | local-1 | |
50fe8924 | 6938 | local-0 <- fp points here. |
8e87e161 | 6939 | |
50fe8924 OE |
6940 | Number of bytes pushed for anonymous args, used to pass information |
6941 | between expand_prologue and expand_epilogue. | |
8aa2a305 | 6942 | |
50fe8924 | 6943 | Adjust the stack by SIZE bytes. REG holds the rtl of the register to be |
fada1961 | 6944 | adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's |
726d4cb7 KK |
6945 | for an epilogue and a negative value means that it's for a sibcall |
6946 | epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of | |
6947 | all the registers that are about to be restored, and hence dead. */ | |
8aa2a305 | 6948 | static void |
fada1961 | 6949 | output_stack_adjust (int size, rtx reg, int epilogue_p, |
21d05694 | 6950 | HARD_REG_SET *live_regs_mask, bool frame_p) |
8aa2a305 | 6951 | { |
cd459bf8 | 6952 | rtx_insn *(*emit_fn) (rtx) = frame_p ? &frame_insn : &emit_insn; |
8aa2a305 JW |
6953 | if (size) |
6954 | { | |
fa5322fa AO |
6955 | HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT; |
6956 | ||
157371cf AO |
6957 | /* This test is bogus, as output_stack_adjust is used to re-align the |
6958 | stack. */ | |
6959 | #if 0 | |
f5b9e7c9 | 6960 | gcc_assert (!(size % align)); |
157371cf | 6961 | #endif |
fa5322fa AO |
6962 | |
6963 | if (CONST_OK_FOR_ADD (size)) | |
2754d3c5 | 6964 | emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size))); |
f3cd5375 JW |
6965 | /* Try to do it with two partial adjustments; however, we must make |
6966 | sure that the stack is properly aligned at all times, in case | |
6f317ef3 | 6967 | an interrupt occurs between the two partial adjustments. */ |
fa5322fa AO |
6968 | else if (CONST_OK_FOR_ADD (size / 2 & -align) |
6969 | && CONST_OK_FOR_ADD (size - (size / 2 & -align))) | |
f3cd5375 | 6970 | { |
2754d3c5 R |
6971 | emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align))); |
6972 | emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align)))); | |
f3cd5375 JW |
6973 | } |
6974 | else | |
8aa2a305 | 6975 | { |
f3cd5375 | 6976 | rtx const_reg; |
2754d3c5 | 6977 | rtx insn; |
fada1961 R |
6978 | int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1); |
6979 | int i; | |
f3cd5375 JW |
6980 | |
6981 | /* If TEMP is invalid, we could temporarily save a general | |
6982 | register to MACL. However, there is currently no need | |
f5b9e7c9 | 6983 | to handle this case, so just die when we see it. */ |
726d4cb7 KK |
6984 | if (epilogue_p < 0 |
6985 | || current_function_interrupt | |
62164eb4 | 6986 | || ! call_really_used_regs[temp] || fixed_regs[temp]) |
fada1961 | 6987 | temp = -1; |
726d4cb7 KK |
6988 | if (temp < 0 && ! current_function_interrupt |
6989 | && (TARGET_SHMEDIA || epilogue_p >= 0)) | |
fada1961 R |
6990 | { |
6991 | HARD_REG_SET temps; | |
6992 | COPY_HARD_REG_SET (temps, call_used_reg_set); | |
6993 | AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set); | |
726d4cb7 | 6994 | if (epilogue_p > 0) |
fada1961 | 6995 | { |
726d4cb7 | 6996 | int nreg = 0; |
38173d38 | 6997 | if (crtl->return_rtx) |
726d4cb7 | 6998 | { |
ef4bddc2 | 6999 | machine_mode mode; |
38173d38 | 7000 | mode = GET_MODE (crtl->return_rtx); |
726d4cb7 KK |
7001 | if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG) |
7002 | nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode); | |
7003 | } | |
7004 | for (i = 0; i < nreg; i++) | |
fada1961 | 7005 | CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i); |
e3b5732b | 7006 | if (crtl->calls_eh_return) |
fada1961 R |
7007 | { |
7008 | CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO); | |
7009 | for (i = 0; i <= 3; i++) | |
7010 | CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i)); | |
7011 | } | |
7012 | } | |
726d4cb7 KK |
7013 | if (TARGET_SHMEDIA && epilogue_p < 0) |
7014 | for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++) | |
7015 | CLEAR_HARD_REG_BIT (temps, i); | |
7016 | if (epilogue_p <= 0) | |
fada1961 R |
7017 | { |
7018 | for (i = FIRST_PARM_REG; | |
7019 | i < FIRST_PARM_REG + NPARM_REGS (SImode); i++) | |
7020 | CLEAR_HARD_REG_BIT (temps, i); | |
6de9cd9a | 7021 | if (cfun->static_chain_decl != NULL) |
fada1961 R |
7022 | CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM); |
7023 | } | |
7024 | temp = scavenge_reg (&temps); | |
7025 | } | |
7026 | if (temp < 0 && live_regs_mask) | |
eb996a4a KK |
7027 | { |
7028 | HARD_REG_SET temps; | |
7029 | ||
7030 | COPY_HARD_REG_SET (temps, *live_regs_mask); | |
7031 | CLEAR_HARD_REG_BIT (temps, REGNO (reg)); | |
7032 | temp = scavenge_reg (&temps); | |
7033 | } | |
f3cd5375 | 7034 | if (temp < 0) |
726d4cb7 | 7035 | { |
f5b9e7c9 NS |
7036 | rtx adj_reg, tmp_reg, mem; |
7037 | ||
726d4cb7 KK |
7038 | /* If we reached here, the most likely case is the (sibcall) |
7039 | epilogue for non SHmedia. Put a special push/pop sequence | |
7040 | for such case as the last resort. This looks lengthy but | |
f5b9e7c9 NS |
7041 | would not be problem because it seems to be very |
7042 | rare. */ | |
7043 | ||
7044 | gcc_assert (!TARGET_SHMEDIA && epilogue_p); | |
7045 | ||
7046 | ||
7047 | /* ??? There is still the slight possibility that r4 or | |
7048 | r5 have been reserved as fixed registers or assigned | |
7049 | as global registers, and they change during an | |
7050 | interrupt. There are possible ways to handle this: | |
7051 | ||
7052 | - If we are adjusting the frame pointer (r14), we can do | |
7053 | with a single temp register and an ordinary push / pop | |
7054 | on the stack. | |
7055 | - Grab any call-used or call-saved registers (i.e. not | |
7056 | fixed or globals) for the temps we need. We might | |
7057 | also grab r14 if we are adjusting the stack pointer. | |
7058 | If we can't find enough available registers, issue | |
7059 | a diagnostic and die - the user must have reserved | |
7060 | way too many registers. | |
7061 | But since all this is rather unlikely to happen and | |
7062 | would require extra testing, we just die if r4 / r5 | |
7063 | are not available. */ | |
7064 | gcc_assert (!fixed_regs[4] && !fixed_regs[5] | |
7065 | && !global_regs[4] && !global_regs[5]); | |
7066 | ||
7067 | adj_reg = gen_rtx_REG (GET_MODE (reg), 4); | |
7068 | tmp_reg = gen_rtx_REG (GET_MODE (reg), 5); | |
57d38024 | 7069 | emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg); |
f5b9e7c9 NS |
7070 | emit_insn (GEN_MOV (adj_reg, GEN_INT (size))); |
7071 | emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg)); | |
57d38024 | 7072 | mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg)); |
f5b9e7c9 | 7073 | emit_move_insn (mem, tmp_reg); |
57d38024 R |
7074 | emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg)); |
7075 | mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg)); | |
7076 | emit_move_insn (mem, tmp_reg); | |
7077 | emit_move_insn (reg, adj_reg); | |
7078 | mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg)); | |
7079 | emit_move_insn (adj_reg, mem); | |
7080 | mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg)); | |
7081 | emit_move_insn (tmp_reg, mem); | |
eb996a4a | 7082 | /* Tell flow the insns that pop r4/r5 aren't dead. */ |
c41c1387 RS |
7083 | emit_use (tmp_reg); |
7084 | emit_use (adj_reg); | |
57d38024 | 7085 | return; |
726d4cb7 | 7086 | } |
fa5322fa | 7087 | const_reg = gen_rtx_REG (GET_MODE (reg), temp); |
f3cd5375 JW |
7088 | |
7089 | /* If SIZE is negative, subtract the positive value. | |
7090 | This sometimes allows a constant pool entry to be shared | |
7091 | between prologue and epilogue code. */ | |
7092 | if (size < 0) | |
885c9a39 | 7093 | { |
fa5322fa | 7094 | emit_insn (GEN_MOV (const_reg, GEN_INT (-size))); |
2754d3c5 | 7095 | insn = emit_fn (GEN_SUB3 (reg, reg, const_reg)); |
885c9a39 JR |
7096 | } |
7097 | else | |
7098 | { | |
fa5322fa | 7099 | emit_insn (GEN_MOV (const_reg, GEN_INT (size))); |
2754d3c5 | 7100 | insn = emit_fn (GEN_ADD3 (reg, reg, const_reg)); |
885c9a39 | 7101 | } |
2b8088e7 | 7102 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
f7df4a84 RS |
7103 | gen_rtx_SET (reg, gen_rtx_PLUS (SImode, reg, |
7104 | GEN_INT (size)))); | |
8aa2a305 | 7105 | } |
8aa2a305 JW |
7106 | } |
7107 | } | |
7108 | ||
50fe8924 OE |
7109 | /* Emit the specified insn and mark it as frame related. |
7110 | FIXME: Rename this to emit_frame_insn. */ | |
cd459bf8 | 7111 | static rtx_insn * |
cf277499 | 7112 | frame_insn (rtx x) |
2754d3c5 | 7113 | { |
cd459bf8 DM |
7114 | rtx_insn *insn = emit_insn (x); |
7115 | RTX_FRAME_RELATED_P (insn) = 1; | |
7116 | return insn; | |
2754d3c5 R |
7117 | } |
7118 | ||
8aa2a305 | 7119 | /* Output RTL to push register RN onto the stack. */ |
2754d3c5 | 7120 | static rtx |
cf277499 | 7121 | push (int rn) |
8aa2a305 JW |
7122 | { |
7123 | rtx x; | |
225e4f43 R |
7124 | if (rn == FPUL_REG) |
7125 | x = gen_push_fpul (); | |
7144b2d8 DD |
7126 | else if (rn == FPSCR_REG) |
7127 | x = gen_push_fpscr (); | |
50fe8924 OE |
7128 | else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD |
7129 | && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P (rn)) | |
225e4f43 | 7130 | { |
104ee20b | 7131 | if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1) |
d042370e | 7132 | return NULL_RTX; |
c5c76735 | 7133 | x = gen_push_4 (gen_rtx_REG (DFmode, rn)); |
225e4f43 | 7134 | } |
3a8699c7 | 7135 | else if (TARGET_SH2E && FP_REGISTER_P (rn)) |
c5c76735 | 7136 | x = gen_push_e (gen_rtx_REG (SFmode, rn)); |
1a95a963 | 7137 | else |
c5c76735 | 7138 | x = gen_push (gen_rtx_REG (SImode, rn)); |
1a95a963 | 7139 | |
2754d3c5 | 7140 | x = frame_insn (x); |
b757d36f | 7141 | add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM)); |
2754d3c5 | 7142 | return x; |
8aa2a305 JW |
7143 | } |
7144 | ||
7145 | /* Output RTL to pop register RN from the stack. */ | |
8aa2a305 | 7146 | static void |
cf277499 | 7147 | pop (int rn) |
8aa2a305 | 7148 | { |
2b8088e7 | 7149 | rtx x, sp_reg, reg; |
225e4f43 R |
7150 | if (rn == FPUL_REG) |
7151 | x = gen_pop_fpul (); | |
7144b2d8 DD |
7152 | else if (rn == FPSCR_REG) |
7153 | x = gen_pop_fpscr (); | |
50fe8924 OE |
7154 | else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD |
7155 | && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P (rn)) | |
225e4f43 | 7156 | { |
104ee20b | 7157 | if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1) |
225e4f43 | 7158 | return; |
c5c76735 | 7159 | x = gen_pop_4 (gen_rtx_REG (DFmode, rn)); |
225e4f43 | 7160 | } |
3a8699c7 | 7161 | else if (TARGET_SH2E && FP_REGISTER_P (rn)) |
c5c76735 | 7162 | x = gen_pop_e (gen_rtx_REG (SFmode, rn)); |
1a95a963 | 7163 | else |
c5c76735 | 7164 | x = gen_pop (gen_rtx_REG (SImode, rn)); |
f676971a | 7165 | |
1245df60 | 7166 | x = emit_insn (x); |
2b8088e7 CLT |
7167 | |
7168 | sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM); | |
7169 | reg = copy_rtx (GET_CODE (PATTERN (x)) == PARALLEL | |
7170 | ? SET_DEST (XVECEXP (PATTERN (x), 0, 0)) | |
7171 | : SET_DEST (PATTERN (x))); | |
7172 | add_reg_note (x, REG_CFA_RESTORE, reg); | |
7173 | add_reg_note (x, REG_CFA_ADJUST_CFA, | |
f7df4a84 | 7174 | gen_rtx_SET (sp_reg, |
2b8088e7 CLT |
7175 | plus_constant (SImode, sp_reg, |
7176 | GET_MODE_SIZE (GET_MODE (reg))))); | |
b757d36f | 7177 | add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM)); |
2b8088e7 | 7178 | RTX_FRAME_RELATED_P (x) = 1; |
8aa2a305 JW |
7179 | } |
7180 | ||
1245df60 | 7181 | /* Generate code to push the regs specified in the mask. */ |
8aa2a305 | 7182 | static void |
cf277499 | 7183 | push_regs (HARD_REG_SET *mask, int interrupt_handler) |
8aa2a305 | 7184 | { |
5c7cafa8 | 7185 | int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0; |
ac55736a | 7186 | int skip_fpscr = 0; |
8aa2a305 | 7187 | |
1245df60 R |
7188 | /* Push PR last; this gives better latencies after the prologue, and |
7189 | candidates for the return delay slot when there are no general | |
7190 | registers pushed. */ | |
5c7cafa8 | 7191 | for (; i < FIRST_PSEUDO_REGISTER; i++) |
ac55736a R |
7192 | { |
7193 | /* If this is an interrupt handler, and the SZ bit varies, | |
7194 | and we have to push any floating point register, we need | |
7195 | to switch to the correct precision first. */ | |
7196 | if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD | |
56b138ae | 7197 | && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS])) |
ac55736a R |
7198 | { |
7199 | HARD_REG_SET unsaved; | |
7200 | ||
7201 | push (FPSCR_REG); | |
832a3292 | 7202 | COMPL_HARD_REG_SET (unsaved, *mask); |
ac55736a R |
7203 | fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved); |
7204 | skip_fpscr = 1; | |
7205 | } | |
7206 | if (i != PR_REG | |
7207 | && (i != FPSCR_REG || ! skip_fpscr) | |
7208 | && TEST_HARD_REG_BIT (*mask, i)) | |
50fe8924 OE |
7209 | { |
7210 | /* If the ISR has RESBANK attribute assigned, don't push any of | |
7211 | the following registers - R0-R14, MACH, MACL and GBR. */ | |
561642fa AP |
7212 | if (! (sh_cfun_resbank_handler_p () |
7213 | && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG) | |
7214 | || i == MACH_REG | |
7215 | || i == MACL_REG | |
7216 | || i == GBR_REG))) | |
7217 | push (i); | |
50fe8924 | 7218 | } |
ac55736a | 7219 | } |
5c7cafa8 CB |
7220 | |
7221 | /* Push banked registers last to improve delay slot opportunities. */ | |
7222 | if (interrupt_handler) | |
91a19652 N |
7223 | { |
7224 | bool use_movml = false; | |
7225 | ||
7226 | if (TARGET_SH2A) | |
7227 | { | |
7228 | unsigned int count = 0; | |
7229 | ||
7230 | for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++) | |
7231 | if (TEST_HARD_REG_BIT (*mask, i)) | |
7232 | count++; | |
7233 | else | |
7234 | break; | |
7235 | ||
7236 | /* Use movml when all banked registers are pushed. */ | |
7237 | if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1) | |
7238 | use_movml = true; | |
7239 | } | |
7240 | ||
57c7433f N |
7241 | if (sh_cfun_resbank_handler_p ()) |
7242 | ; /* Do nothing. */ | |
7243 | else if (use_movml) | |
91a19652 N |
7244 | { |
7245 | rtx x, mem, reg, set; | |
7246 | rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM); | |
7247 | ||
7248 | /* We must avoid scheduling multiple store insn with another | |
7249 | insns. */ | |
7250 | emit_insn (gen_blockage ()); | |
7251 | x = gen_movml_push_banked (sp_reg); | |
7252 | x = frame_insn (x); | |
7253 | for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++) | |
7254 | { | |
0a81f074 | 7255 | mem = gen_rtx_MEM (SImode, plus_constant (Pmode, sp_reg, i * 4)); |
91a19652 | 7256 | reg = gen_rtx_REG (SImode, i); |
f7df4a84 | 7257 | add_reg_note (x, REG_CFA_OFFSET, gen_rtx_SET (mem, reg)); |
91a19652 N |
7258 | } |
7259 | ||
f7df4a84 | 7260 | set = gen_rtx_SET (sp_reg, plus_constant (Pmode, sp_reg, - 32)); |
91a19652 N |
7261 | add_reg_note (x, REG_CFA_ADJUST_CFA, set); |
7262 | emit_insn (gen_blockage ()); | |
7263 | } | |
7264 | else | |
7265 | for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++) | |
7266 | if (TEST_HARD_REG_BIT (*mask, i)) | |
7267 | push (i); | |
7268 | } | |
5c7cafa8 | 7269 | |
561642fa AP |
7270 | /* Don't push PR register for an ISR with RESBANK attribute assigned. */ |
7271 | if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ()) | |
1245df60 | 7272 | push (PR_REG); |
8aa2a305 JW |
7273 | } |
7274 | ||
fe3ad572 SC |
7275 | /* Calculate how much extra space is needed to save all callee-saved |
7276 | target registers. | |
7277 | LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */ | |
fe3ad572 SC |
7278 | static int |
7279 | shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask) | |
7280 | { | |
7281 | int reg; | |
7282 | int stack_space = 0; | |
7283 | int interrupt_handler = sh_cfun_interrupt_handler_p (); | |
7284 | ||
7285 | for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--) | |
62164eb4 | 7286 | if ((! call_really_used_regs[reg] || interrupt_handler) |
50fe8924 | 7287 | && ! TEST_HARD_REG_BIT (*live_regs_mask, reg)) |
fe3ad572 | 7288 | /* Leave space to save this target register on the stack, |
24746a42 | 7289 | in case target register allocation wants to use it. */ |
fe3ad572 SC |
7290 | stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg)); |
7291 | return stack_space; | |
7292 | } | |
f676971a | 7293 | |
fe3ad572 SC |
7294 | /* Decide whether we should reserve space for callee-save target registers, |
7295 | in case target register allocation wants to use them. REGS_SAVED is | |
7296 | the space, in bytes, that is already required for register saves. | |
7297 | LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */ | |
fe3ad572 SC |
7298 | static int |
7299 | shmedia_reserve_space_for_target_registers_p (int regs_saved, | |
7300 | HARD_REG_SET *live_regs_mask) | |
7301 | { | |
7302 | if (optimize_size) | |
7303 | return 0; | |
7304 | return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved; | |
7305 | } | |
7306 | ||
7307 | /* Decide how much space to reserve for callee-save target registers | |
7308 | in case target register allocation wants to use them. | |
7309 | LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */ | |
fe3ad572 SC |
7310 | static int |
7311 | shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask) | |
7312 | { | |
7313 | if (shmedia_space_reserved_for_target_registers) | |
7314 | return shmedia_target_regs_stack_space (live_regs_mask); | |
7315 | else | |
7316 | return 0; | |
7317 | } | |
7318 | ||
8aa2a305 | 7319 | /* Work out the registers which need to be saved, both as a mask and a |
490dbac7 | 7320 | count of saved words. Return the count. |
8aa2a305 JW |
7321 | |
7322 | If doing a pragma interrupt function, then push all regs used by the | |
7323 | function, and if we call another function (we can tell by looking at PR), | |
7324 | make sure that all the regs it clobbers are safe too. */ | |
490dbac7 | 7325 | static int |
cf277499 | 7326 | calc_live_regs (HARD_REG_SET *live_regs_mask) |
8aa2a305 | 7327 | { |
0ef2c525 | 7328 | unsigned int reg; |
1245df60 | 7329 | int count; |
a6ab9fc0 R |
7330 | tree attrs; |
7331 | bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler; | |
7332 | bool nosave_low_regs; | |
fada1961 | 7333 | int pr_live, has_call; |
157131d7 | 7334 | |
a6ab9fc0 R |
7335 | attrs = DECL_ATTRIBUTES (current_function_decl); |
7336 | interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p (); | |
7337 | trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE; | |
7338 | interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler; | |
7339 | nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE; | |
8aa2a305 | 7340 | |
fada1961 | 7341 | CLEAR_HARD_REG_SET (*live_regs_mask); |
157371cf | 7342 | if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler |
6fb5fa3c | 7343 | && df_regs_ever_live_p (FPSCR_REG)) |
c0fb94d7 | 7344 | target_flags &= ~MASK_FPU_SINGLE; |
225e4f43 | 7345 | /* If we can save a lot of saves by switching to double mode, do that. */ |
50fe8924 OE |
7346 | else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD |
7347 | && TARGET_FPU_SINGLE) | |
225e4f43 | 7348 | for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2) |
6fb5fa3c | 7349 | if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1) |
62164eb4 | 7350 | && (! call_really_used_regs[reg] |
a6ab9fc0 | 7351 | || interrupt_handler) |
225e4f43 R |
7352 | && ++count > 2) |
7353 | { | |
c0fb94d7 | 7354 | target_flags &= ~MASK_FPU_SINGLE; |
225e4f43 R |
7355 | break; |
7356 | } | |
9d7ed806 R |
7357 | /* PR_MEDIA_REG is a general purpose register, thus global_alloc already |
7358 | knows how to use it. That means the pseudo originally allocated for | |
7359 | the initial value can become the PR_MEDIA_REG hard register, as seen for | |
7360 | execute/20010122-1.c:test9. */ | |
7361 | if (TARGET_SHMEDIA) | |
7d73a2ba R |
7362 | /* ??? this function is called from initial_elimination_offset, hence we |
7363 | can't use the result of sh_media_register_for_return here. */ | |
97b3d0f0 | 7364 | pr_live = sh_pr_n_sets (); |
9d7ed806 R |
7365 | else |
7366 | { | |
7367 | rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG); | |
7368 | pr_live = (pr_initial | |
f3536097 | 7369 | ? (!REG_P (pr_initial) |
29db2a1e | 7370 | || REGNO (pr_initial) != (PR_REG)) |
6fb5fa3c | 7371 | : df_regs_ever_live_p (PR_REG)); |
7d73a2ba R |
7372 | /* For Shcompact, if not optimizing, we end up with a memory reference |
7373 | using the return address pointer for __builtin_return_address even | |
7374 | though there is no actual need to put the PR register on the stack. */ | |
6fb5fa3c | 7375 | pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM); |
9d7ed806 | 7376 | } |
fa5322fa AO |
7377 | /* Force PR to be live if the prologue has to call the SHmedia |
7378 | argument decoder or register saver. */ | |
7379 | if (TARGET_SHCOMPACT | |
38173d38 | 7380 | && ((crtl->args.info.call_cookie |
fa5322fa | 7381 | & ~ CALL_COOKIE_RET_TRAMP (1)) |
e3b5732b | 7382 | || crtl->saves_all_registers)) |
fa5322fa | 7383 | pr_live = 1; |
fada1961 | 7384 | has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live; |
0ef2c525 | 7385 | for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; ) |
8aa2a305 | 7386 | { |
97b3d0f0 | 7387 | if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) |
3007d592 | 7388 | ? pr_live |
a6ab9fc0 | 7389 | : interrupt_handler |
1245df60 | 7390 | ? (/* Need to save all the regs ever live. */ |
6fb5fa3c | 7391 | (df_regs_ever_live_p (reg) |
62164eb4 R |
7392 | || (call_really_used_regs[reg] |
7393 | && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG | |
7394 | || reg == PIC_OFFSET_TABLE_REGNUM) | |
fada1961 | 7395 | && has_call) |
a6ab9fc0 R |
7396 | || (TARGET_SHMEDIA && has_call |
7397 | && REGISTER_NATURAL_MODE (reg) == SImode | |
fada1961 | 7398 | && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg)))) |
1245df60 R |
7399 | && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM |
7400 | && reg != RETURN_ADDRESS_POINTER_REGNUM | |
7144b2d8 | 7401 | && reg != T_REG && reg != GBR_REG |
3a2317d1 | 7402 | && reg != FPSCR_MODES_REG && reg != FPSCR_STAT_REG |
7144b2d8 DD |
7403 | /* Push fpscr only on targets which have FPU */ |
7404 | && (reg != FPSCR_REG || TARGET_FPU_ANY)) | |
1245df60 | 7405 | : (/* Only push those regs which are used and need to be saved. */ |
180bde4f RS |
7406 | (TARGET_SHCOMPACT |
7407 | && flag_pic | |
38173d38 | 7408 | && crtl->args.info.call_cookie |
0ef2c525 | 7409 | && reg == PIC_OFFSET_TABLE_REGNUM) |
6fb5fa3c | 7410 | || (df_regs_ever_live_p (reg) |
9fdcdc74 KK |
7411 | && ((!call_really_used_regs[reg] |
7412 | && !(reg != PIC_OFFSET_TABLE_REGNUM | |
7413 | && fixed_regs[reg] && call_used_regs[reg])) | |
a6ab9fc0 | 7414 | || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY))) |
e3b5732b | 7415 | || (crtl->calls_eh_return |
0ef2c525 KK |
7416 | && (reg == EH_RETURN_DATA_REGNO (0) |
7417 | || reg == EH_RETURN_DATA_REGNO (1) | |
7418 | || reg == EH_RETURN_DATA_REGNO (2) | |
7419 | || reg == EH_RETURN_DATA_REGNO (3))) | |
61f71b34 | 7420 | || ((reg == MACL_REG || reg == MACH_REG) |
6fb5fa3c | 7421 | && df_regs_ever_live_p (reg) |
61f71b34 DD |
7422 | && sh_cfun_attr_renesas_p ()) |
7423 | )) | |
8aa2a305 | 7424 | { |
490dbac7 | 7425 | SET_HARD_REG_BIT (*live_regs_mask, reg); |
fa5322fa AO |
7426 | count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg)); |
7427 | ||
157371cf | 7428 | if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD |
fa5322fa | 7429 | && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT) |
eda44c78 | 7430 | { |
104ee20b | 7431 | if (FP_REGISTER_P (reg)) |
eda44c78 | 7432 | { |
6fb5fa3c | 7433 | if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1)) |
eda44c78 | 7434 | { |
490dbac7 | 7435 | SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1)); |
fa5322fa | 7436 | count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1)); |
eda44c78 R |
7437 | } |
7438 | } | |
fa5322fa | 7439 | else if (XD_REGISTER_P (reg)) |
eda44c78 R |
7440 | { |
7441 | /* Must switch to double mode to access these registers. */ | |
c0fb94d7 | 7442 | target_flags &= ~MASK_FPU_SINGLE; |
eda44c78 R |
7443 | } |
7444 | } | |
8aa2a305 | 7445 | } |
a6ab9fc0 R |
7446 | if (nosave_low_regs && reg == R8_REG) |
7447 | break; | |
8aa2a305 | 7448 | } |
fe3ad572 SC |
7449 | /* If we have a target register optimization pass after prologue / epilogue |
7450 | threading, we need to assume all target registers will be live even if | |
7451 | they aren't now. */ | |
7452 | if (flag_branch_target_load_optimize2 | |
7453 | && TARGET_SAVE_ALL_TARGET_REGS | |
7454 | && shmedia_space_reserved_for_target_registers) | |
7455 | for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--) | |
62164eb4 | 7456 | if ((! call_really_used_regs[reg] || interrupt_handler) |
fe3ad572 SC |
7457 | && ! TEST_HARD_REG_BIT (*live_regs_mask, reg)) |
7458 | { | |
7459 | SET_HARD_REG_BIT (*live_regs_mask, reg); | |
7460 | count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg)); | |
7461 | } | |
fada1961 R |
7462 | /* If this is an interrupt handler, we don't have any call-clobbered |
7463 | registers we can conveniently use for target register save/restore. | |
7464 | Make sure we save at least one general purpose register when we need | |
7465 | to save target registers. */ | |
7466 | if (interrupt_handler | |
56b138ae RS |
7467 | && hard_reg_set_intersect_p (*live_regs_mask, |
7468 | reg_class_contents[TARGET_REGS]) | |
7469 | && ! hard_reg_set_intersect_p (*live_regs_mask, | |
7470 | reg_class_contents[GENERAL_REGS])) | |
fada1961 R |
7471 | { |
7472 | SET_HARD_REG_BIT (*live_regs_mask, R0_REG); | |
7473 | count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG)); | |
7474 | } | |
8aa2a305 | 7475 | |
490dbac7 | 7476 | return count; |
8aa2a305 JW |
7477 | } |
7478 | ||
7479 | /* Code to generate prologue and epilogue sequences */ | |
b9654711 | 7480 | |
a93d1ba2 | 7481 | /* PUSHED is the number of bytes that are being pushed on the |
0ad913af R |
7482 | stack for register saves. Return the frame size, padded |
7483 | appropriately so that the stack stays properly aligned. */ | |
e5f8d4c0 | 7484 | static HOST_WIDE_INT |
cf277499 | 7485 | rounded_frame_size (int pushed) |
e5f8d4c0 R |
7486 | { |
7487 | HOST_WIDE_INT size = get_frame_size (); | |
7488 | HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT; | |
7489 | ||
7a296495 CB |
7490 | if (ACCUMULATE_OUTGOING_ARGS) |
7491 | size += crtl->outgoing_args_size; | |
7492 | ||
c5b9ef02 | 7493 | return ((size + pushed + align - 1) & -align) - pushed; |
e5f8d4c0 R |
7494 | } |
7495 | ||
fa5322fa AO |
7496 | /* Choose a call-clobbered target-branch register that remains |
7497 | unchanged along the whole function. We set it up as the return | |
7498 | value in the prologue. */ | |
7499 | int | |
cf277499 | 7500 | sh_media_register_for_return (void) |
fa5322fa AO |
7501 | { |
7502 | int regno; | |
7503 | int tr0_used; | |
7504 | ||
416ff32e | 7505 | if (! crtl->is_leaf) |
fa5322fa | 7506 | return -1; |
fada1961 R |
7507 | if (lookup_attribute ("interrupt_handler", |
7508 | DECL_ATTRIBUTES (current_function_decl))) | |
7509 | return -1; | |
73a4d10b R |
7510 | if (sh_cfun_interrupt_handler_p ()) |
7511 | return -1; | |
fa5322fa | 7512 | |
6fb5fa3c | 7513 | tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM); |
fa5322fa AO |
7514 | |
7515 | for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++) | |
6fb5fa3c | 7516 | if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno)) |
fa5322fa AO |
7517 | return regno; |
7518 | ||
7519 | return -1; | |
7520 | } | |
7521 | ||
fada1961 R |
7522 | /* The maximum registers we need to save are: |
7523 | - 62 general purpose registers (r15 is stack pointer, r63 is zero) | |
7524 | - 32 floating point registers (for each pair, we save none, | |
7525 | one single precision value, or a double precision value). | |
7526 | - 8 target registers | |
7527 | - add 1 entry for a delimiter. */ | |
7528 | #define MAX_SAVED_REGS (62+32+8) | |
7529 | ||
7530 | typedef struct save_entry_s | |
7531 | { | |
7532 | unsigned char reg; | |
7533 | unsigned char mode; | |
7534 | short offset; | |
7535 | } save_entry; | |
7536 | ||
7537 | #define MAX_TEMPS 4 | |
7538 | ||
7539 | /* There will be a delimiter entry with VOIDmode both at the start and the | |
7540 | end of a filled in schedule. The end delimiter has the offset of the | |
7541 | save with the smallest (i.e. most negative) offset. */ | |
7542 | typedef struct save_schedule_s | |
7543 | { | |
7544 | save_entry entries[MAX_SAVED_REGS + 2]; | |
7545 | int temps[MAX_TEMPS+1]; | |
7546 | } save_schedule; | |
7547 | ||
7548 | /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero, | |
7549 | use reverse order. Returns the last entry written to (not counting | |
7550 | the delimiter). OFFSET_BASE is a number to be added to all offset | |
7551 | entries. */ | |
fada1961 R |
7552 | static save_entry * |
7553 | sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule, | |
7554 | int offset_base) | |
7555 | { | |
7556 | int align, i; | |
7557 | save_entry *entry = schedule->entries; | |
7558 | int tmpx = 0; | |
7559 | int offset; | |
7560 | ||
7561 | if (! current_function_interrupt) | |
7562 | for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++) | |
62164eb4 | 7563 | if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG |
fada1961 R |
7564 | && ! FUNCTION_ARG_REGNO_P (i) |
7565 | && i != FIRST_RET_REG | |
6de9cd9a | 7566 | && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM) |
e3b5732b | 7567 | && ! (crtl->calls_eh_return |
fada1961 | 7568 | && (i == EH_RETURN_STACKADJ_REGNO |
f94cef0a KK |
7569 | || ((unsigned) i >= EH_RETURN_DATA_REGNO (0) |
7570 | && (unsigned) i <= EH_RETURN_DATA_REGNO (3))))) | |
fada1961 R |
7571 | schedule->temps[tmpx++] = i; |
7572 | entry->reg = -1; | |
7573 | entry->mode = VOIDmode; | |
7574 | entry->offset = offset_base; | |
7575 | entry++; | |
7576 | /* We loop twice: first, we save 8-byte aligned registers in the | |
7577 | higher addresses, that are known to be aligned. Then, we | |
7578 | proceed to saving 32-bit registers that don't need 8-byte | |
7579 | alignment. | |
7580 | If this is an interrupt function, all registers that need saving | |
7581 | need to be saved in full. moreover, we need to postpone saving | |
7582 | target registers till we have saved some general purpose registers | |
7583 | we can then use as scratch registers. */ | |
7584 | offset = offset_base; | |
7585 | for (align = 1; align >= 0; align--) | |
7586 | { | |
7587 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
7588 | if (TEST_HARD_REG_BIT (*live_regs_mask, i)) | |
7589 | { | |
ef4bddc2 | 7590 | machine_mode mode = REGISTER_NATURAL_MODE (i); |
fada1961 R |
7591 | int reg = i; |
7592 | ||
7593 | if (current_function_interrupt) | |
7594 | { | |
7595 | if (TARGET_REGISTER_P (i)) | |
7596 | continue; | |
7597 | if (GENERAL_REGISTER_P (i)) | |
7598 | mode = DImode; | |
7599 | } | |
7600 | if (mode == SFmode && (i % 2) == 1 | |
7601 | && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i) | |
7602 | && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1)))) | |
7603 | { | |
7604 | mode = DFmode; | |
7605 | i--; | |
7606 | reg--; | |
7607 | } | |
7608 | ||
7609 | /* If we're doing the aligned pass and this is not aligned, | |
7610 | or we're doing the unaligned pass and this is aligned, | |
7611 | skip it. */ | |
7612 | if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0) | |
7613 | != align) | |
7614 | continue; | |
7615 | ||
7616 | if (current_function_interrupt | |
7617 | && GENERAL_REGISTER_P (i) | |
7618 | && tmpx < MAX_TEMPS) | |
7619 | schedule->temps[tmpx++] = i; | |
7620 | ||
7621 | offset -= GET_MODE_SIZE (mode); | |
7622 | entry->reg = i; | |
7623 | entry->mode = mode; | |
7624 | entry->offset = offset; | |
7625 | entry++; | |
7626 | } | |
7627 | if (align && current_function_interrupt) | |
7628 | for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--) | |
7629 | if (TEST_HARD_REG_BIT (*live_regs_mask, i)) | |
7630 | { | |
7631 | offset -= GET_MODE_SIZE (DImode); | |
7632 | entry->reg = i; | |
7633 | entry->mode = DImode; | |
7634 | entry->offset = offset; | |
7635 | entry++; | |
7636 | } | |
7637 | } | |
7638 | entry->reg = -1; | |
7639 | entry->mode = VOIDmode; | |
7640 | entry->offset = offset; | |
7641 | schedule->temps[tmpx] = -1; | |
7642 | return entry - 1; | |
7643 | } | |
7644 | ||
50fe8924 | 7645 | /* Expand code for the function prologue. */ |
b9654711 | 7646 | void |
cf277499 | 7647 | sh_expand_prologue (void) |
b9654711 | 7648 | { |
490dbac7 | 7649 | HARD_REG_SET live_regs_mask; |
40d2032b | 7650 | int d, i; |
fa5322fa | 7651 | int d_rounding = 0; |
225e4f43 | 7652 | int save_flags = target_flags; |
49616835 | 7653 | int pretend_args; |
e631262b | 7654 | int stack_usage; |
a6ab9fc0 R |
7655 | tree sp_switch_attr |
7656 | = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)); | |
b9654711 | 7657 | |
e3ba8d11 | 7658 | current_function_interrupt = sh_cfun_interrupt_handler_p (); |
552ecbd9 | 7659 | |
0d7e008e | 7660 | /* We have pretend args if we had an object sent partially in registers |
8aa2a305 | 7661 | and partially on the stack, e.g. a large structure. */ |
38173d38 | 7662 | pretend_args = crtl->args.pretend_args_size; |
49616835 JR |
7663 | if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl) |
7664 | && (NPARM_REGS(SImode) | |
38173d38 | 7665 | > crtl->args.info.arg_count[(int) SH_ARG_INT])) |
49616835 | 7666 | pretend_args = 0; |
803b9370 | 7667 | |
49616835 | 7668 | output_stack_adjust (-pretend_args |
38173d38 | 7669 | - crtl->args.info.stack_regs * 8, |
803b9370 | 7670 | stack_pointer_rtx, 0, NULL, true); |
e631262b | 7671 | stack_usage = pretend_args + crtl->args.info.stack_regs * 8; |
b9654711 | 7672 | |
38173d38 | 7673 | if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie) |
2b1fd83f AO |
7674 | /* We're going to use the PIC register to load the address of the |
7675 | incoming-argument decoder and/or of the return trampoline from | |
7676 | the GOT, so make sure the PIC register is preserved and | |
7677 | initialized. */ | |
6fb5fa3c | 7678 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
2b1fd83f | 7679 | |
fa5322fa | 7680 | if (TARGET_SHCOMPACT |
38173d38 | 7681 | && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1))) |
fa5322fa AO |
7682 | { |
7683 | int reg; | |
7684 | ||
7685 | /* First, make all registers with incoming arguments that will | |
7686 | be pushed onto the stack live, so that register renaming | |
7687 | doesn't overwrite them. */ | |
7688 | for (reg = 0; reg < NPARM_REGS (SImode); reg++) | |
38173d38 | 7689 | if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie) |
fa5322fa AO |
7690 | >= NPARM_REGS (SImode) - reg) |
7691 | for (; reg < NPARM_REGS (SImode); reg++) | |
7692 | emit_insn (gen_shcompact_preserve_incoming_args | |
7693 | (gen_rtx_REG (SImode, FIRST_PARM_REG + reg))); | |
7694 | else if (CALL_COOKIE_INT_REG_GET | |
38173d38 | 7695 | (crtl->args.info.call_cookie, reg) == 1) |
fa5322fa AO |
7696 | emit_insn (gen_shcompact_preserve_incoming_args |
7697 | (gen_rtx_REG (SImode, FIRST_PARM_REG + reg))); | |
7698 | ||
7699 | emit_move_insn (gen_rtx_REG (Pmode, MACL_REG), | |
7700 | stack_pointer_rtx); | |
7701 | emit_move_insn (gen_rtx_REG (SImode, R0_REG), | |
38173d38 | 7702 | GEN_INT (crtl->args.info.call_cookie)); |
fa5322fa AO |
7703 | emit_move_insn (gen_rtx_REG (SImode, MACH_REG), |
7704 | gen_rtx_REG (SImode, R0_REG)); | |
7705 | } | |
7706 | else if (TARGET_SHMEDIA) | |
7707 | { | |
7708 | int tr = sh_media_register_for_return (); | |
7709 | ||
7710 | if (tr >= 0) | |
6fb5fa3c DB |
7711 | emit_move_insn (gen_rtx_REG (DImode, tr), |
7712 | gen_rtx_REG (DImode, PR_MEDIA_REG)); | |
fa5322fa AO |
7713 | } |
7714 | ||
7ab56274 | 7715 | /* Emit the code for SETUP_VARARGS. */ |
e3b5732b | 7716 | if (cfun->stdarg) |
b9654711 | 7717 | { |
49616835 | 7718 | if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)) |
1245df60 | 7719 | { |
1a95a963 JW |
7720 | /* Push arg regs as if they'd been provided by caller in stack. */ |
7721 | for (i = 0; i < NPARM_REGS(SImode); i++) | |
7722 | { | |
7723 | int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1; | |
2754d3c5 | 7724 | |
f676971a | 7725 | if (i >= (NPARM_REGS(SImode) |
38173d38 | 7726 | - crtl->args.info.arg_count[(int) SH_ARG_INT] |
aec373f1 | 7727 | )) |
1a95a963 | 7728 | break; |
535b951f | 7729 | push (rn); |
e631262b | 7730 | stack_usage += GET_MODE_SIZE (SImode); |
1a95a963 | 7731 | } |
1245df60 | 7732 | } |
b9654711 | 7733 | } |
1a95a963 | 7734 | |
4408efce | 7735 | /* If we're supposed to switch stacks at function entry, do so now. */ |
a6ab9fc0 R |
7736 | if (sp_switch_attr) |
7737 | { | |
20e19db4 | 7738 | rtx lab, newsrc; |
a6ab9fc0 R |
7739 | /* The argument specifies a variable holding the address of the |
7740 | stack the interrupt function should switch to/from at entry/exit. */ | |
20e19db4 | 7741 | tree arg = TREE_VALUE ( TREE_VALUE (sp_switch_attr)); |
a6ab9fc0 | 7742 | const char *s |
20e19db4 | 7743 | = ggc_strdup (TREE_STRING_POINTER (arg)); |
a6ab9fc0 R |
7744 | rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s); |
7745 | ||
20e19db4 DD |
7746 | lab = add_constant (sp_switch, SImode, 0); |
7747 | newsrc = gen_rtx_LABEL_REF (VOIDmode, lab); | |
20e19db4 DD |
7748 | |
7749 | emit_insn (gen_sp_switch_1 (newsrc)); | |
a6ab9fc0 | 7750 | } |
4408efce | 7751 | |
490dbac7 | 7752 | d = calc_live_regs (&live_regs_mask); |
225e4f43 R |
7753 | /* ??? Maybe we could save some switching if we can move a mode switch |
7754 | that already happens to be at the function start into the prologue. */ | |
ac55736a | 7755 | if (target_flags != save_flags && ! current_function_interrupt) |
225e4f43 | 7756 | emit_insn (gen_toggle_sz ()); |
f676971a | 7757 | |
fa5322fa AO |
7758 | if (TARGET_SH5) |
7759 | { | |
fada1961 R |
7760 | int offset_base, offset; |
7761 | rtx r0 = NULL_RTX; | |
fa5322fa AO |
7762 | int offset_in_r0 = -1; |
7763 | int sp_in_r0 = 0; | |
fe3ad572 SC |
7764 | int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask); |
7765 | int total_size, save_size; | |
fada1961 R |
7766 | save_schedule schedule; |
7767 | save_entry *entry; | |
7768 | int *tmp_pnt; | |
7769 | ||
62164eb4 | 7770 | if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG] |
fada1961 R |
7771 | && ! current_function_interrupt) |
7772 | r0 = gen_rtx_REG (Pmode, R0_REG); | |
fe3ad572 SC |
7773 | |
7774 | /* D is the actual number of bytes that we need for saving registers, | |
7775 | however, in initial_elimination_offset we have committed to using | |
7776 | an additional TREGS_SPACE amount of bytes - in order to keep both | |
7777 | addresses to arguments supplied by the caller and local variables | |
7778 | valid, we must keep this gap. Place it between the incoming | |
7779 | arguments and the actually saved registers in a bid to optimize | |
7780 | locality of reference. */ | |
7781 | total_size = d + tregs_space; | |
7782 | total_size += rounded_frame_size (total_size); | |
7783 | save_size = total_size - rounded_frame_size (d); | |
7784 | if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT)) | |
fa5322fa | 7785 | d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT) |
fe3ad572 SC |
7786 | - save_size % (STACK_BOUNDARY / BITS_PER_UNIT)); |
7787 | ||
7788 | /* If adjusting the stack in a single step costs nothing extra, do so. | |
7789 | I.e. either if a single addi is enough, or we need a movi anyway, | |
7790 | and we don't exceed the maximum offset range (the test for the | |
7791 | latter is conservative for simplicity). */ | |
7792 | if (TARGET_SHMEDIA | |
7793 | && (CONST_OK_FOR_I10 (-total_size) | |
7794 | || (! CONST_OK_FOR_I10 (-(save_size + d_rounding)) | |
7795 | && total_size <= 2044))) | |
7796 | d_rounding = total_size - save_size; | |
fa5322fa | 7797 | |
fada1961 | 7798 | offset_base = d + d_rounding; |
fe3ad572 SC |
7799 | |
7800 | output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx, | |
21d05694 | 7801 | 0, NULL, true); |
e631262b | 7802 | stack_usage += save_size + d_rounding; |
fa5322fa | 7803 | |
fada1961 R |
7804 | sh5_schedule_saves (&live_regs_mask, &schedule, offset_base); |
7805 | tmp_pnt = schedule.temps; | |
7806 | for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++) | |
7807 | { | |
ef4bddc2 | 7808 | machine_mode mode = (machine_mode) entry->mode; |
0ef2c525 | 7809 | unsigned int reg = entry->reg; |
fada1961 | 7810 | rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX; |
455786b6 | 7811 | rtx orig_reg_rtx; |
fa5322fa | 7812 | |
fada1961 | 7813 | offset = entry->offset; |
fa5322fa | 7814 | |
fada1961 | 7815 | reg_rtx = gen_rtx_REG (mode, reg); |
fa5322fa | 7816 | |
57d38024 R |
7817 | mem_rtx = gen_frame_mem (mode, |
7818 | gen_rtx_PLUS (Pmode, | |
7819 | stack_pointer_rtx, | |
7820 | GEN_INT (offset))); | |
fa5322fa | 7821 | |
6de7a512 PB |
7822 | if (!memory_address_p (mode, XEXP (mem_rtx, 0))) |
7823 | { | |
7824 | gcc_assert (r0); | |
7825 | mem_rtx = NULL_RTX; | |
7826 | } | |
fa5322fa | 7827 | |
6de7a512 PB |
7828 | if (HAVE_PRE_DECREMENT |
7829 | && (offset_in_r0 - offset == GET_MODE_SIZE (mode) | |
7830 | || mem_rtx == NULL_RTX | |
7831 | || reg == PR_REG || SPECIAL_REGISTER_P (reg))) | |
7832 | { | |
7833 | pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0)); | |
fa5322fa | 7834 | |
6de7a512 | 7835 | if (!memory_address_p (mode, XEXP (pre_dec, 0))) |
fada1961 | 7836 | pre_dec = NULL_RTX; |
6de7a512 PB |
7837 | else |
7838 | { | |
7839 | mem_rtx = NULL_RTX; | |
7840 | offset += GET_MODE_SIZE (mode); | |
7841 | } | |
7842 | } | |
fa5322fa | 7843 | |
fada1961 R |
7844 | if (mem_rtx != NULL_RTX) |
7845 | goto addr_ok; | |
fa5322fa | 7846 | |
fada1961 R |
7847 | if (offset_in_r0 == -1) |
7848 | { | |
7849 | emit_move_insn (r0, GEN_INT (offset)); | |
7850 | offset_in_r0 = offset; | |
7851 | } | |
7852 | else if (offset != offset_in_r0) | |
7853 | { | |
7854 | emit_move_insn (r0, | |
7855 | gen_rtx_PLUS | |
7856 | (Pmode, r0, | |
7857 | GEN_INT (offset - offset_in_r0))); | |
7858 | offset_in_r0 += offset - offset_in_r0; | |
7859 | } | |
f676971a | 7860 | |
fada1961 R |
7861 | if (pre_dec != NULL_RTX) |
7862 | { | |
7863 | if (! sp_in_r0) | |
fa5322fa AO |
7864 | { |
7865 | emit_move_insn (r0, | |
7866 | gen_rtx_PLUS | |
fada1961 R |
7867 | (Pmode, r0, stack_pointer_rtx)); |
7868 | sp_in_r0 = 1; | |
fa5322fa | 7869 | } |
fa5322fa | 7870 | |
fada1961 R |
7871 | offset -= GET_MODE_SIZE (mode); |
7872 | offset_in_r0 -= GET_MODE_SIZE (mode); | |
fa5322fa | 7873 | |
fada1961 R |
7874 | mem_rtx = pre_dec; |
7875 | } | |
7876 | else if (sp_in_r0) | |
57d38024 | 7877 | mem_rtx = gen_frame_mem (mode, r0); |
fada1961 | 7878 | else |
57d38024 R |
7879 | mem_rtx = gen_frame_mem (mode, |
7880 | gen_rtx_PLUS (Pmode, | |
7881 | stack_pointer_rtx, | |
7882 | r0)); | |
fada1961 R |
7883 | |
7884 | /* We must not use an r0-based address for target-branch | |
7885 | registers or for special registers without pre-dec | |
7886 | memory addresses, since we store their values in r0 | |
7887 | first. */ | |
f5b9e7c9 NS |
7888 | gcc_assert (!TARGET_REGISTER_P (reg) |
7889 | && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg)) | |
7890 | || mem_rtx == pre_dec)); | |
7891 | ||
fada1961 | 7892 | addr_ok: |
455786b6 | 7893 | orig_reg_rtx = reg_rtx; |
fada1961 R |
7894 | if (TARGET_REGISTER_P (reg) |
7895 | || ((reg == PR_REG || SPECIAL_REGISTER_P (reg)) | |
7896 | && mem_rtx != pre_dec)) | |
7897 | { | |
7898 | rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt); | |
fa5322fa | 7899 | |
fada1961 | 7900 | emit_move_insn (tmp_reg, reg_rtx); |
fa5322fa | 7901 | |
fada1961 R |
7902 | if (REGNO (tmp_reg) == R0_REG) |
7903 | { | |
fa5322fa AO |
7904 | offset_in_r0 = -1; |
7905 | sp_in_r0 = 0; | |
c9bd6bcd | 7906 | gcc_assert (!refers_to_regno_p (R0_REG, mem_rtx)); |
fa5322fa AO |
7907 | } |
7908 | ||
fada1961 R |
7909 | if (*++tmp_pnt <= 0) |
7910 | tmp_pnt = schedule.temps; | |
7911 | ||
7912 | reg_rtx = tmp_reg; | |
fa5322fa | 7913 | } |
fada1961 R |
7914 | { |
7915 | rtx insn; | |
7916 | ||
7917 | /* Mark as interesting for dwarf cfi generator */ | |
7918 | insn = emit_move_insn (mem_rtx, reg_rtx); | |
7919 | RTX_FRAME_RELATED_P (insn) = 1; | |
455786b6 KK |
7920 | /* If we use an intermediate register for the save, we can't |
7921 | describe this exactly in cfi as a copy of the to-be-saved | |
7922 | register into the temporary register and then the temporary | |
7923 | register on the stack, because the temporary register can | |
7924 | have a different natural size than the to-be-saved register. | |
7925 | Thus, we gloss over the intermediate copy and pretend we do | |
7926 | a direct save from the to-be-saved register. */ | |
7927 | if (REGNO (reg_rtx) != reg) | |
7928 | { | |
b757d36f | 7929 | rtx set; |
455786b6 | 7930 | |
f7df4a84 | 7931 | set = gen_rtx_SET (mem_rtx, orig_reg_rtx); |
b757d36f | 7932 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, set); |
455786b6 | 7933 | } |
fada1961 | 7934 | |
f676971a | 7935 | if (TARGET_SHCOMPACT && (offset_in_r0 != -1)) |
fada1961 R |
7936 | { |
7937 | rtx reg_rtx = gen_rtx_REG (mode, reg); | |
b757d36f | 7938 | rtx set; |
57d38024 R |
7939 | rtx mem_rtx = gen_frame_mem (mode, |
7940 | gen_rtx_PLUS (Pmode, | |
7941 | stack_pointer_rtx, | |
7942 | GEN_INT (offset))); | |
fada1961 | 7943 | |
f7df4a84 | 7944 | set = gen_rtx_SET (mem_rtx, reg_rtx); |
b757d36f | 7945 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, set); |
fada1961 R |
7946 | } |
7947 | } | |
7948 | } | |
fa5322fa | 7949 | |
f5b9e7c9 | 7950 | gcc_assert (entry->offset == d_rounding); |
fa5322fa AO |
7951 | } |
7952 | else | |
e631262b KK |
7953 | { |
7954 | push_regs (&live_regs_mask, current_function_interrupt); | |
7955 | stack_usage += d; | |
7956 | } | |
1a66cd67 | 7957 | |
6fb5fa3c | 7958 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
b6d10e0b | 7959 | emit_insn (gen_GOTaddr2picreg (const0_rtx)); |
1a66cd67 | 7960 | |
fa5322fa AO |
7961 | if (SHMEDIA_REGS_STACK_ADJUST ()) |
7962 | { | |
fa5322fa AO |
7963 | /* This must NOT go through the PLT, otherwise mach and macl |
7964 | may be clobbered. */ | |
73a4d10b R |
7965 | function_symbol (gen_rtx_REG (Pmode, R0_REG), |
7966 | (TARGET_FPU_ANY | |
7967 | ? "__GCC_push_shmedia_regs" | |
7968 | : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT); | |
fa5322fa AO |
7969 | emit_insn (gen_shmedia_save_restore_regs_compact |
7970 | (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ()))); | |
7971 | } | |
7972 | ||
ac55736a | 7973 | if (target_flags != save_flags && ! current_function_interrupt) |
6fb5fa3c | 7974 | emit_insn (gen_toggle_sz ()); |
1a95a963 | 7975 | |
225e4f43 R |
7976 | target_flags = save_flags; |
7977 | ||
fa5322fa | 7978 | output_stack_adjust (-rounded_frame_size (d) + d_rounding, |
21d05694 | 7979 | stack_pointer_rtx, 0, NULL, true); |
e631262b | 7980 | stack_usage += rounded_frame_size (d) - d_rounding; |
b9654711 SC |
7981 | |
7982 | if (frame_pointer_needed) | |
96a2347e | 7983 | frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx)); |
fa5322fa | 7984 | |
fa5322fa | 7985 | if (TARGET_SHCOMPACT |
38173d38 | 7986 | && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1))) |
fa5322fa AO |
7987 | { |
7988 | /* This must NOT go through the PLT, otherwise mach and macl | |
7989 | may be clobbered. */ | |
73a4d10b R |
7990 | function_symbol (gen_rtx_REG (Pmode, R0_REG), |
7991 | "__GCC_shcompact_incoming_args", SFUNC_GOT); | |
fa5322fa AO |
7992 | emit_insn (gen_shcompact_incoming_args ()); |
7993 | } | |
e631262b | 7994 | |
6c5bfec0 KK |
7995 | /* If we are profiling, make sure no instructions are scheduled before |
7996 | the call to mcount. Similarly if some call instructions are swapped | |
7997 | before frame related insns, it'll confuse the unwinder because | |
7998 | currently SH has no unwind info for function epilogues. */ | |
7999 | if (crtl->profile || flag_exceptions || flag_unwind_tables) | |
8000 | emit_insn (gen_blockage ()); | |
8001 | ||
a11e0df4 | 8002 | if (flag_stack_usage_info) |
e631262b | 8003 | current_function_static_stack_size = stack_usage; |
b9654711 SC |
8004 | } |
8005 | ||
50fe8924 | 8006 | /* Expand code for the function epilogue. */ |
b9654711 | 8007 | void |
726d4cb7 | 8008 | sh_expand_epilogue (bool sibcall_p) |
b9654711 | 8009 | { |
490dbac7 | 8010 | HARD_REG_SET live_regs_mask; |
40d2032b | 8011 | int d, i; |
fa5322fa | 8012 | int d_rounding = 0; |
b9654711 | 8013 | |
225e4f43 | 8014 | int save_flags = target_flags; |
fe3ad572 | 8015 | int frame_size, save_size; |
ac55736a | 8016 | int fpscr_deferred = 0; |
726d4cb7 | 8017 | int e = sibcall_p ? -1 : 1; |
3d5a0820 | 8018 | |
490dbac7 | 8019 | d = calc_live_regs (&live_regs_mask); |
3d5a0820 | 8020 | |
fe3ad572 SC |
8021 | save_size = d; |
8022 | frame_size = rounded_frame_size (d); | |
8023 | ||
8024 | if (TARGET_SH5) | |
8025 | { | |
8026 | int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask); | |
8027 | int total_size; | |
8028 | if (d % (STACK_BOUNDARY / BITS_PER_UNIT)) | |
50fe8924 OE |
8029 | d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT) |
8030 | - d % (STACK_BOUNDARY / BITS_PER_UNIT)); | |
fe3ad572 SC |
8031 | |
8032 | total_size = d + tregs_space; | |
8033 | total_size += rounded_frame_size (total_size); | |
8034 | save_size = total_size - frame_size; | |
8035 | ||
8036 | /* If adjusting the stack in a single step costs nothing extra, do so. | |
8037 | I.e. either if a single addi is enough, or we need a movi anyway, | |
8038 | and we don't exceed the maximum offset range (the test for the | |
8039 | latter is conservative for simplicity). */ | |
8040 | if (TARGET_SHMEDIA | |
8041 | && ! frame_pointer_needed | |
8042 | && (CONST_OK_FOR_I10 (total_size) | |
8043 | || (! CONST_OK_FOR_I10 (save_size + d_rounding) | |
8044 | && total_size <= 2044))) | |
8045 | d_rounding = frame_size; | |
fa5322fa | 8046 | |
fe3ad572 SC |
8047 | frame_size -= d_rounding; |
8048 | } | |
16bea517 | 8049 | |
b9654711 | 8050 | if (frame_pointer_needed) |
46d81ffa | 8051 | { |
1964788a | 8052 | /* We must avoid scheduling the epilogue with previous basic blocks. |
47ea8d4e | 8053 | See PR/18032 and PR/40313. */ |
1964788a | 8054 | emit_insn (gen_blockage ()); |
96a2347e | 8055 | output_stack_adjust (frame_size, hard_frame_pointer_rtx, e, |
2b8088e7 | 8056 | &live_regs_mask, true); |
07f5b9aa JL |
8057 | |
8058 | /* We must avoid moving the stack pointer adjustment past code | |
8059 | which reads from the local frame, else an interrupt could | |
8060 | occur after the SP adjustment and clobber data in the local | |
8061 | frame. */ | |
8062 | emit_insn (gen_blockage ()); | |
2b8088e7 | 8063 | frame_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx)); |
46d81ffa | 8064 | } |
3d5a0820 | 8065 | else if (frame_size) |
07f5b9aa JL |
8066 | { |
8067 | /* We must avoid moving the stack pointer adjustment past code | |
8068 | which reads from the local frame, else an interrupt could | |
8069 | occur after the SP adjustment and clobber data in the local | |
8070 | frame. */ | |
8071 | emit_insn (gen_blockage ()); | |
21d05694 | 8072 | output_stack_adjust (frame_size, stack_pointer_rtx, e, |
2b8088e7 | 8073 | &live_regs_mask, true); |
07f5b9aa | 8074 | } |
b9654711 | 8075 | |
fa5322fa AO |
8076 | if (SHMEDIA_REGS_STACK_ADJUST ()) |
8077 | { | |
73a4d10b R |
8078 | function_symbol (gen_rtx_REG (Pmode, R0_REG), |
8079 | (TARGET_FPU_ANY | |
8080 | ? "__GCC_pop_shmedia_regs" | |
8081 | : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT); | |
fa5322fa AO |
8082 | /* This must NOT go through the PLT, otherwise mach and macl |
8083 | may be clobbered. */ | |
8084 | emit_insn (gen_shmedia_save_restore_regs_compact | |
8085 | (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ()))); | |
8086 | } | |
8087 | ||
16bea517 | 8088 | /* Pop all the registers. */ |
0d7e008e | 8089 | |
ac55736a | 8090 | if (target_flags != save_flags && ! current_function_interrupt) |
225e4f43 | 8091 | emit_insn (gen_toggle_sz ()); |
fa5322fa AO |
8092 | if (TARGET_SH5) |
8093 | { | |
fada1961 | 8094 | int offset_base, offset; |
fa5322fa AO |
8095 | int offset_in_r0 = -1; |
8096 | int sp_in_r0 = 0; | |
fa5322fa | 8097 | rtx r0 = gen_rtx_REG (Pmode, R0_REG); |
fada1961 R |
8098 | save_schedule schedule; |
8099 | save_entry *entry; | |
8100 | int *tmp_pnt; | |
7d73a2ba | 8101 | |
fada1961 R |
8102 | entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding); |
8103 | offset_base = -entry[1].offset + d_rounding; | |
8104 | tmp_pnt = schedule.temps; | |
8105 | for (; entry->mode != VOIDmode; entry--) | |
8106 | { | |
ef4bddc2 | 8107 | machine_mode mode = (machine_mode) entry->mode; |
fada1961 | 8108 | int reg = entry->reg; |
535b951f | 8109 | rtx reg_rtx, mem_rtx, post_inc = NULL_RTX; |
fa5322fa | 8110 | |
fada1961 R |
8111 | offset = offset_base + entry->offset; |
8112 | reg_rtx = gen_rtx_REG (mode, reg); | |
fa5322fa | 8113 | |
57d38024 R |
8114 | mem_rtx = gen_frame_mem (mode, |
8115 | gen_rtx_PLUS (Pmode, | |
8116 | stack_pointer_rtx, | |
8117 | GEN_INT (offset))); | |
fa5322fa | 8118 | |
6de7a512 PB |
8119 | if (!memory_address_p (mode, XEXP (mem_rtx, 0))) |
8120 | mem_rtx = NULL_RTX; | |
fa5322fa | 8121 | |
6de7a512 PB |
8122 | if (HAVE_POST_INCREMENT |
8123 | && (offset == offset_in_r0 | |
8124 | || (offset + GET_MODE_SIZE (mode) != d + d_rounding | |
8125 | && mem_rtx == NULL_RTX) | |
8126 | || reg == PR_REG || SPECIAL_REGISTER_P (reg))) | |
8127 | { | |
8128 | post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0)); | |
fa5322fa | 8129 | |
6de7a512 | 8130 | if (!memory_address_p (mode, XEXP (post_inc, 0))) |
fada1961 | 8131 | post_inc = NULL_RTX; |
6de7a512 | 8132 | else |
fada1961 | 8133 | mem_rtx = NULL_RTX; |
6de7a512 | 8134 | } |
f676971a | 8135 | |
fada1961 R |
8136 | if (mem_rtx != NULL_RTX) |
8137 | goto addr_ok; | |
fa5322fa | 8138 | |
fada1961 R |
8139 | if (offset_in_r0 == -1) |
8140 | { | |
8141 | emit_move_insn (r0, GEN_INT (offset)); | |
8142 | offset_in_r0 = offset; | |
8143 | } | |
8144 | else if (offset != offset_in_r0) | |
8145 | { | |
8146 | emit_move_insn (r0, | |
8147 | gen_rtx_PLUS | |
8148 | (Pmode, r0, | |
8149 | GEN_INT (offset - offset_in_r0))); | |
8150 | offset_in_r0 += offset - offset_in_r0; | |
8151 | } | |
f676971a | 8152 | |
fada1961 R |
8153 | if (post_inc != NULL_RTX) |
8154 | { | |
8155 | if (! sp_in_r0) | |
fa5322fa AO |
8156 | { |
8157 | emit_move_insn (r0, | |
8158 | gen_rtx_PLUS | |
fada1961 R |
8159 | (Pmode, r0, stack_pointer_rtx)); |
8160 | sp_in_r0 = 1; | |
fa5322fa | 8161 | } |
f676971a | 8162 | |
fada1961 | 8163 | mem_rtx = post_inc; |
fa5322fa | 8164 | |
fada1961 R |
8165 | offset_in_r0 += GET_MODE_SIZE (mode); |
8166 | } | |
8167 | else if (sp_in_r0) | |
57d38024 | 8168 | mem_rtx = gen_frame_mem (mode, r0); |
fada1961 | 8169 | else |
57d38024 R |
8170 | mem_rtx = gen_frame_mem (mode, |
8171 | gen_rtx_PLUS (Pmode, | |
8172 | stack_pointer_rtx, | |
8173 | r0)); | |
fa5322fa | 8174 | |
f5b9e7c9 NS |
8175 | gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg)) |
8176 | || mem_rtx == post_inc); | |
fa5322fa | 8177 | |
fada1961 R |
8178 | addr_ok: |
8179 | if ((reg == PR_REG || SPECIAL_REGISTER_P (reg)) | |
8180 | && mem_rtx != post_inc) | |
8181 | { | |
535b951f | 8182 | emit_move_insn (r0, mem_rtx); |
fada1961 R |
8183 | mem_rtx = r0; |
8184 | } | |
8185 | else if (TARGET_REGISTER_P (reg)) | |
8186 | { | |
8187 | rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt); | |
8188 | ||
8189 | /* Give the scheduler a bit of freedom by using up to | |
8190 | MAX_TEMPS registers in a round-robin fashion. */ | |
535b951f | 8191 | emit_move_insn (tmp_reg, mem_rtx); |
fada1961 R |
8192 | mem_rtx = tmp_reg; |
8193 | if (*++tmp_pnt < 0) | |
8194 | tmp_pnt = schedule.temps; | |
fa5322fa AO |
8195 | } |
8196 | ||
535b951f | 8197 | emit_move_insn (reg_rtx, mem_rtx); |
fada1961 R |
8198 | } |
8199 | ||
f5b9e7c9 | 8200 | gcc_assert (entry->offset + offset_base == d + d_rounding); |
fa5322fa | 8201 | } |
fe3ad572 | 8202 | else /* ! TARGET_SH5 */ |
b9654711 | 8203 | { |
5c7cafa8 CB |
8204 | int last_reg; |
8205 | ||
fe3ad572 | 8206 | save_size = 0; |
561642fa AP |
8207 | /* For an ISR with RESBANK attribute assigned, don't pop PR |
8208 | register. */ | |
8209 | if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG) | |
8210 | && !sh_cfun_resbank_handler_p ()) | |
6fb5fa3c DB |
8211 | { |
8212 | if (!frame_pointer_needed) | |
8213 | emit_insn (gen_blockage ()); | |
8214 | pop (PR_REG); | |
8215 | } | |
5c7cafa8 | 8216 | |
6a62ca52 | 8217 | /* Banked registers are popped first to avoid being scheduled in the |
5c7cafa8 CB |
8218 | delay slot. RTE switches banks before the ds instruction. */ |
8219 | if (current_function_interrupt) | |
8220 | { | |
91a19652 N |
8221 | bool use_movml = false; |
8222 | ||
8223 | if (TARGET_SH2A) | |
8224 | { | |
8225 | unsigned int count = 0; | |
8226 | ||
8227 | for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++) | |
8228 | if (TEST_HARD_REG_BIT (live_regs_mask, i)) | |
8229 | count++; | |
8230 | else | |
8231 | break; | |
8232 | ||
8233 | /* Use movml when all banked register are poped. */ | |
8234 | if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1) | |
8235 | use_movml = true; | |
8236 | } | |
8237 | ||
57c7433f N |
8238 | if (sh_cfun_resbank_handler_p ()) |
8239 | ; /* Do nothing. */ | |
8240 | else if (use_movml) | |
91a19652 N |
8241 | { |
8242 | rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM); | |
8243 | ||
8244 | /* We must avoid scheduling multiple load insn with another | |
8245 | insns. */ | |
8246 | emit_insn (gen_blockage ()); | |
8247 | emit_insn (gen_movml_pop_banked (sp_reg)); | |
8248 | emit_insn (gen_blockage ()); | |
8249 | } | |
8250 | else | |
8251 | for (i = LAST_BANKED_REG; i >= FIRST_BANKED_REG; i--) | |
8252 | if (TEST_HARD_REG_BIT (live_regs_mask, i)) | |
8253 | pop (i); | |
5c7cafa8 CB |
8254 | |
8255 | last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1; | |
8256 | } | |
8257 | else | |
8258 | last_reg = FIRST_PSEUDO_REGISTER; | |
8259 | ||
8260 | for (i = 0; i < last_reg; i++) | |
fe3ad572 SC |
8261 | { |
8262 | int j = (FIRST_PSEUDO_REGISTER - 1) - i; | |
f676971a | 8263 | |
fe3ad572 | 8264 | if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD |
56b138ae RS |
8265 | && hard_reg_set_intersect_p (live_regs_mask, |
8266 | reg_class_contents[DF_REGS])) | |
fe3ad572 | 8267 | fpscr_deferred = 1; |
561642fa AP |
8268 | /* For an ISR with RESBANK attribute assigned, don't pop |
8269 | following registers, R0-R14, MACH, MACL and GBR. */ | |
8270 | else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j) | |
8271 | && ! (sh_cfun_resbank_handler_p () | |
8272 | && ((j >= FIRST_GENERAL_REG | |
8273 | && j < LAST_GENERAL_REG) | |
8274 | || j == MACH_REG | |
8275 | || j == MACL_REG | |
8276 | || j == GBR_REG))) | |
fe3ad572 | 8277 | pop (j); |
5c7cafa8 | 8278 | |
fe3ad572 SC |
8279 | if (j == FIRST_FP_REG && fpscr_deferred) |
8280 | pop (FPSCR_REG); | |
fe3ad572 | 8281 | } |
b9654711 | 8282 | } |
ac55736a | 8283 | if (target_flags != save_flags && ! current_function_interrupt) |
225e4f43 R |
8284 | emit_insn (gen_toggle_sz ()); |
8285 | target_flags = save_flags; | |
b9654711 | 8286 | |
38173d38 | 8287 | output_stack_adjust (crtl->args.pretend_args_size |
fe3ad572 | 8288 | + save_size + d_rounding |
38173d38 | 8289 | + crtl->args.info.stack_regs * 8, |
2b8088e7 | 8290 | stack_pointer_rtx, e, NULL, true); |
4408efce | 8291 | |
e3b5732b | 8292 | if (crtl->calls_eh_return) |
4977bab6 ZW |
8293 | emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx, |
8294 | EH_RETURN_STACKADJ_RTX)); | |
8295 | ||
4408efce | 8296 | /* Switch back to the normal stack if necessary. */ |
a6ab9fc0 | 8297 | if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl))) |
4408efce | 8298 | emit_insn (gen_sp_switch_2 ()); |
89d4bc35 AO |
8299 | |
8300 | /* Tell flow the insn that pops PR isn't dead. */ | |
fa5322fa AO |
8301 | /* PR_REG will never be live in SHmedia mode, and we don't need to |
8302 | USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG | |
8303 | by the return pattern. */ | |
490dbac7 | 8304 | if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)) |
c41c1387 | 8305 | emit_use (gen_rtx_REG (SImode, PR_REG)); |
b9654711 SC |
8306 | } |
8307 | ||
4977bab6 ZW |
8308 | /* Emit code to change the current function's return address to RA. |
8309 | TEMP is available as a scratch register, if needed. */ | |
4977bab6 | 8310 | void |
cf277499 | 8311 | sh_set_return_address (rtx ra, rtx tmp) |
4977bab6 | 8312 | { |
490dbac7 | 8313 | HARD_REG_SET live_regs_mask; |
4977bab6 | 8314 | int d; |
4977bab6 ZW |
8315 | int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG; |
8316 | int pr_offset; | |
8317 | ||
490dbac7 | 8318 | d = calc_live_regs (&live_regs_mask); |
4977bab6 ZW |
8319 | |
8320 | /* If pr_reg isn't life, we can set it (or the register given in | |
8321 | sh_media_register_for_return) directly. */ | |
490dbac7 | 8322 | if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg)) |
4977bab6 ZW |
8323 | { |
8324 | rtx rr; | |
8325 | ||
8326 | if (TARGET_SHMEDIA) | |
8327 | { | |
8328 | int rr_regno = sh_media_register_for_return (); | |
8329 | ||
8330 | if (rr_regno < 0) | |
8331 | rr_regno = pr_reg; | |
8332 | ||
8333 | rr = gen_rtx_REG (DImode, rr_regno); | |
8334 | } | |
8335 | else | |
8336 | rr = gen_rtx_REG (SImode, pr_reg); | |
8337 | ||
8338 | emit_insn (GEN_MOV (rr, ra)); | |
8339 | /* Tell flow the register for return isn't dead. */ | |
c41c1387 | 8340 | emit_use (rr); |
4977bab6 ZW |
8341 | return; |
8342 | } | |
8343 | ||
8344 | if (TARGET_SH5) | |
8345 | { | |
4977bab6 | 8346 | int offset; |
fada1961 R |
8347 | save_schedule schedule; |
8348 | save_entry *entry; | |
f676971a | 8349 | |
fada1961 R |
8350 | entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0); |
8351 | offset = entry[1].offset; | |
8352 | for (; entry->mode != VOIDmode; entry--) | |
8353 | if (entry->reg == pr_reg) | |
8354 | goto found; | |
4977bab6 ZW |
8355 | |
8356 | /* We can't find pr register. */ | |
f5b9e7c9 | 8357 | gcc_unreachable (); |
4977bab6 ZW |
8358 | |
8359 | found: | |
fada1961 R |
8360 | offset = entry->offset - offset; |
8361 | pr_offset = (rounded_frame_size (d) + offset | |
4977bab6 ZW |
8362 | + SHMEDIA_REGS_STACK_ADJUST ()); |
8363 | } | |
8364 | else | |
fada1961 | 8365 | pr_offset = rounded_frame_size (d); |
4977bab6 ZW |
8366 | |
8367 | emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset))); | |
7a296495 CB |
8368 | |
8369 | if (frame_pointer_needed) | |
8370 | emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx)); | |
8371 | else | |
8372 | emit_insn (GEN_ADD3 (tmp, tmp, stack_pointer_rtx)); | |
4977bab6 | 8373 | |
57d38024 | 8374 | tmp = gen_frame_mem (Pmode, tmp); |
4977bab6 | 8375 | emit_insn (GEN_MOV (tmp, ra)); |
7f9a14e3 KK |
8376 | /* Tell this store isn't dead. */ |
8377 | emit_use (tmp); | |
4977bab6 ZW |
8378 | } |
8379 | ||
8aa2a305 | 8380 | /* Clear variables at function end. */ |
08c148a8 | 8381 | static void |
cf277499 SB |
8382 | sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
8383 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
8aa2a305 | 8384 | { |
8aa2a305 JW |
8385 | } |
8386 | ||
61f71b34 | 8387 | static rtx |
cf277499 | 8388 | sh_builtin_saveregs (void) |
1a95a963 | 8389 | { |
1a95a963 | 8390 | /* First unnamed integer register. */ |
38173d38 | 8391 | int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT]; |
1a95a963 JW |
8392 | /* Number of integer registers we need to save. */ |
8393 | int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg); | |
8394 | /* First unnamed SFmode float reg */ | |
38173d38 | 8395 | int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT]; |
1a95a963 JW |
8396 | /* Number of SFmode float regs to save. */ |
8397 | int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg); | |
318881c0 | 8398 | rtx regbuf, fpregs; |
ba4828e0 | 8399 | int bufsize, regno; |
4862826d | 8400 | alias_set_type alias_set; |
1a95a963 | 8401 | |
fa5322fa AO |
8402 | if (TARGET_SH5) |
8403 | { | |
8404 | if (n_intregs) | |
8405 | { | |
8406 | int pushregs = n_intregs; | |
8407 | ||
8408 | while (pushregs < NPARM_REGS (SImode) - 1 | |
8409 | && (CALL_COOKIE_INT_REG_GET | |
38173d38 | 8410 | (crtl->args.info.call_cookie, |
fa5322fa AO |
8411 | NPARM_REGS (SImode) - pushregs) |
8412 | == 1)) | |
8413 | { | |
38173d38 | 8414 | crtl->args.info.call_cookie |
fa5322fa AO |
8415 | &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) |
8416 | - pushregs, 1); | |
8417 | pushregs++; | |
8418 | } | |
8419 | ||
8420 | if (pushregs == NPARM_REGS (SImode)) | |
38173d38 | 8421 | crtl->args.info.call_cookie |
fa5322fa AO |
8422 | |= (CALL_COOKIE_INT_REG (0, 1) |
8423 | | CALL_COOKIE_STACKSEQ (pushregs - 1)); | |
8424 | else | |
38173d38 | 8425 | crtl->args.info.call_cookie |
fa5322fa AO |
8426 | |= CALL_COOKIE_STACKSEQ (pushregs); |
8427 | ||
38173d38 | 8428 | crtl->args.pretend_args_size += 8 * n_intregs; |
fa5322fa AO |
8429 | } |
8430 | if (TARGET_SHCOMPACT) | |
8431 | return const0_rtx; | |
8432 | } | |
f676971a | 8433 | |
3a8699c7 | 8434 | if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5) |
fa5322fa AO |
8435 | { |
8436 | error ("__builtin_saveregs not supported by this subtarget"); | |
8437 | return const0_rtx; | |
8438 | } | |
8439 | ||
8440 | if (TARGET_SHMEDIA) | |
8441 | n_floatregs = 0; | |
8442 | ||
6f317ef3 | 8443 | /* Allocate block of memory for the regs. */ |
1a95a963 JW |
8444 | /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte? |
8445 | Or can assign_stack_local accept a 0 SIZE argument? */ | |
8446 | bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD); | |
8447 | ||
fa5322fa | 8448 | if (TARGET_SHMEDIA) |
57d38024 | 8449 | regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM)); |
f78ec36a R |
8450 | else if (n_floatregs & 1) |
8451 | { | |
8452 | rtx addr; | |
8453 | ||
8454 | regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0); | |
8455 | addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0)); | |
8456 | emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD))); | |
8457 | regbuf = change_address (regbuf, BLKmode, addr); | |
8458 | } | |
a11c004b R |
8459 | else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs) |
8460 | { | |
8461 | rtx addr, mask; | |
8462 | ||
8463 | regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0); | |
0a81f074 RS |
8464 | addr = copy_to_mode_reg (Pmode, plus_constant (Pmode, |
8465 | XEXP (regbuf, 0), 4)); | |
a11c004b R |
8466 | mask = copy_to_mode_reg (Pmode, GEN_INT (-8)); |
8467 | emit_insn (gen_andsi3 (addr, addr, mask)); | |
8468 | regbuf = change_address (regbuf, BLKmode, addr); | |
8469 | } | |
fa5322fa | 8470 | else |
a11c004b | 8471 | regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0); |
514066a1 | 8472 | alias_set = get_varargs_alias_set (); |
ba4828e0 | 8473 | set_mem_alias_set (regbuf, alias_set); |
1a95a963 JW |
8474 | |
8475 | /* Save int args. | |
8476 | This is optimized to only save the regs that are necessary. Explicitly | |
8477 | named args need not be saved. */ | |
8478 | if (n_intregs > 0) | |
8479 | move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg, | |
f4ef873c RK |
8480 | adjust_address (regbuf, BLKmode, |
8481 | n_floatregs * UNITS_PER_WORD), | |
c6b97fac | 8482 | n_intregs); |
1a95a963 | 8483 | |
fa5322fa AO |
8484 | if (TARGET_SHMEDIA) |
8485 | /* Return the address of the regbuf. */ | |
8486 | return XEXP (regbuf, 0); | |
8487 | ||
1a95a963 JW |
8488 | /* Save float args. |
8489 | This is optimized to only save the regs that are necessary. Explicitly | |
8490 | named args need not be saved. | |
8491 | We explicitly build a pointer to the buffer because it halves the insn | |
8492 | count when not optimizing (otherwise the pointer is built for each reg | |
1245df60 R |
8493 | saved). |
8494 | We emit the moves in reverse order so that we can use predecrement. */ | |
1a95a963 | 8495 | |
7d9c5aa1 | 8496 | fpregs = copy_to_mode_reg (Pmode, |
0a81f074 RS |
8497 | plus_constant (Pmode, XEXP (regbuf, 0), |
8498 | n_floatregs * UNITS_PER_WORD)); | |
157371cf | 8499 | if (TARGET_SH4 || TARGET_SH2A_DOUBLE) |
225e4f43 | 8500 | { |
514066a1 | 8501 | rtx mem; |
225e4f43 R |
8502 | for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2) |
8503 | { | |
8504 | emit_insn (gen_addsi3 (fpregs, fpregs, | |
8505 | GEN_INT (-2 * UNITS_PER_WORD))); | |
57d38024 | 8506 | mem = change_address (regbuf, DFmode, fpregs); |
f676971a | 8507 | emit_move_insn (mem, |
c0d4e710 | 8508 | gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno)); |
225e4f43 R |
8509 | } |
8510 | regno = first_floatreg; | |
8511 | if (regno & 1) | |
8512 | { | |
832a3292 | 8513 | emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD))); |
57d38024 | 8514 | mem = change_address (regbuf, SFmode, fpregs); |
514066a1 | 8515 | emit_move_insn (mem, |
277772f6 OE |
8516 | gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) |
8517 | + regno - SH_REG_MSW_OFFSET)); | |
225e4f43 R |
8518 | } |
8519 | } | |
8520 | else | |
1245df60 R |
8521 | for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--) |
8522 | { | |
514066a1 | 8523 | rtx mem; |
ba4828e0 | 8524 | |
832a3292 | 8525 | emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD))); |
57d38024 | 8526 | mem = change_address (regbuf, SFmode, fpregs); |
514066a1 | 8527 | emit_move_insn (mem, |
c5c76735 | 8528 | gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno)); |
1245df60 | 8529 | } |
1a95a963 JW |
8530 | |
8531 | /* Return the address of the regbuf. */ | |
8532 | return XEXP (regbuf, 0); | |
8533 | } | |
8534 | ||
514066a1 | 8535 | /* Define the `__builtin_va_list' type for the ABI. */ |
c35d187f RH |
8536 | static tree |
8537 | sh_build_builtin_va_list (void) | |
514066a1 RH |
8538 | { |
8539 | tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack; | |
10575b5d | 8540 | tree record, type_decl; |
514066a1 | 8541 | |
61f71b34 DD |
8542 | if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4) |
8543 | || TARGET_HITACHI || sh_cfun_attr_renesas_p ()) | |
514066a1 RH |
8544 | return ptr_type_node; |
8545 | ||
5d27ef94 | 8546 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
10575b5d KK |
8547 | type_decl = build_decl (BUILTINS_LOCATION, |
8548 | TYPE_DECL, get_identifier ("__va_list_tag"), record); | |
514066a1 | 8549 | |
4c4bde29 AH |
8550 | f_next_o = build_decl (BUILTINS_LOCATION, |
8551 | FIELD_DECL, get_identifier ("__va_next_o"), | |
514066a1 | 8552 | ptr_type_node); |
4c4bde29 AH |
8553 | f_next_o_limit = build_decl (BUILTINS_LOCATION, |
8554 | FIELD_DECL, | |
514066a1 RH |
8555 | get_identifier ("__va_next_o_limit"), |
8556 | ptr_type_node); | |
4c4bde29 AH |
8557 | f_next_fp = build_decl (BUILTINS_LOCATION, |
8558 | FIELD_DECL, get_identifier ("__va_next_fp"), | |
514066a1 | 8559 | ptr_type_node); |
4c4bde29 AH |
8560 | f_next_fp_limit = build_decl (BUILTINS_LOCATION, |
8561 | FIELD_DECL, | |
514066a1 RH |
8562 | get_identifier ("__va_next_fp_limit"), |
8563 | ptr_type_node); | |
4c4bde29 AH |
8564 | f_next_stack = build_decl (BUILTINS_LOCATION, |
8565 | FIELD_DECL, get_identifier ("__va_next_stack"), | |
514066a1 RH |
8566 | ptr_type_node); |
8567 | ||
8568 | DECL_FIELD_CONTEXT (f_next_o) = record; | |
8569 | DECL_FIELD_CONTEXT (f_next_o_limit) = record; | |
8570 | DECL_FIELD_CONTEXT (f_next_fp) = record; | |
8571 | DECL_FIELD_CONTEXT (f_next_fp_limit) = record; | |
8572 | DECL_FIELD_CONTEXT (f_next_stack) = record; | |
8573 | ||
0fd2eac2 | 8574 | TYPE_STUB_DECL (record) = type_decl; |
10575b5d | 8575 | TYPE_NAME (record) = type_decl; |
514066a1 | 8576 | TYPE_FIELDS (record) = f_next_o; |
910ad8de NF |
8577 | DECL_CHAIN (f_next_o) = f_next_o_limit; |
8578 | DECL_CHAIN (f_next_o_limit) = f_next_fp; | |
8579 | DECL_CHAIN (f_next_fp) = f_next_fp_limit; | |
8580 | DECL_CHAIN (f_next_fp_limit) = f_next_stack; | |
514066a1 RH |
8581 | |
8582 | layout_type (record); | |
8583 | ||
8584 | return record; | |
8585 | } | |
8586 | ||
8587 | /* Implement `va_start' for varargs and stdarg. */ | |
d7bd8aeb | 8588 | static void |
cf277499 | 8589 | sh_va_start (tree valist, rtx nextarg) |
514066a1 RH |
8590 | { |
8591 | tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack; | |
8592 | tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack; | |
8593 | tree t, u; | |
8594 | int nfp, nint; | |
8595 | ||
fa5322fa AO |
8596 | if (TARGET_SH5) |
8597 | { | |
8598 | expand_builtin_saveregs (); | |
e5faf155 | 8599 | std_expand_builtin_va_start (valist, nextarg); |
fa5322fa AO |
8600 | return; |
8601 | } | |
8602 | ||
61f71b34 DD |
8603 | if ((! TARGET_SH2E && ! TARGET_SH4) |
8604 | || TARGET_HITACHI || sh_cfun_attr_renesas_p ()) | |
514066a1 | 8605 | { |
e5faf155 | 8606 | std_expand_builtin_va_start (valist, nextarg); |
514066a1 RH |
8607 | return; |
8608 | } | |
8609 | ||
8610 | f_next_o = TYPE_FIELDS (va_list_type_node); | |
910ad8de NF |
8611 | f_next_o_limit = DECL_CHAIN (f_next_o); |
8612 | f_next_fp = DECL_CHAIN (f_next_o_limit); | |
8613 | f_next_fp_limit = DECL_CHAIN (f_next_fp); | |
8614 | f_next_stack = DECL_CHAIN (f_next_fp_limit); | |
514066a1 | 8615 | |
47a25a46 | 8616 | next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o, |
44de5aeb | 8617 | NULL_TREE); |
47a25a46 RG |
8618 | next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit), |
8619 | valist, f_next_o_limit, NULL_TREE); | |
8620 | next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp, | |
8621 | NULL_TREE); | |
8622 | next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit), | |
8623 | valist, f_next_fp_limit, NULL_TREE); | |
8624 | next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack), | |
8625 | valist, f_next_stack, NULL_TREE); | |
514066a1 RH |
8626 | |
8627 | /* Call __builtin_saveregs. */ | |
5be014d5 AP |
8628 | u = make_tree (sizetype, expand_builtin_saveregs ()); |
8629 | u = fold_convert (ptr_type_node, u); | |
726a989a | 8630 | t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u); |
514066a1 RH |
8631 | TREE_SIDE_EFFECTS (t) = 1; |
8632 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
8633 | ||
38173d38 | 8634 | nfp = crtl->args.info.arg_count[SH_ARG_FLOAT]; |
514066a1 RH |
8635 | if (nfp < 8) |
8636 | nfp = 8 - nfp; | |
8637 | else | |
8638 | nfp = 0; | |
5d49b6a7 | 8639 | u = fold_build_pointer_plus_hwi (u, UNITS_PER_WORD * nfp); |
726a989a | 8640 | t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u); |
514066a1 RH |
8641 | TREE_SIDE_EFFECTS (t) = 1; |
8642 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
8643 | ||
726a989a | 8644 | t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u); |
514066a1 RH |
8645 | TREE_SIDE_EFFECTS (t) = 1; |
8646 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
8647 | ||
38173d38 | 8648 | nint = crtl->args.info.arg_count[SH_ARG_INT]; |
514066a1 RH |
8649 | if (nint < 4) |
8650 | nint = 4 - nint; | |
8651 | else | |
8652 | nint = 0; | |
5d49b6a7 | 8653 | u = fold_build_pointer_plus_hwi (u, UNITS_PER_WORD * nint); |
726a989a | 8654 | t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u); |
514066a1 RH |
8655 | TREE_SIDE_EFFECTS (t) = 1; |
8656 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
8657 | ||
8658 | u = make_tree (ptr_type_node, nextarg); | |
726a989a | 8659 | t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u); |
514066a1 RH |
8660 | TREE_SIDE_EFFECTS (t) = 1; |
8661 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
8662 | } | |
8663 | ||
917f1b7e | 8664 | /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized |
21bdb106 JR |
8665 | member, return it. */ |
8666 | static tree | |
8667 | find_sole_member (tree type) | |
8668 | { | |
8669 | tree field, member = NULL_TREE; | |
8670 | ||
910ad8de | 8671 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) |
21bdb106 JR |
8672 | { |
8673 | if (TREE_CODE (field) != FIELD_DECL) | |
8674 | continue; | |
8675 | if (!DECL_SIZE (field)) | |
8676 | return NULL_TREE; | |
8677 | if (integer_zerop (DECL_SIZE (field))) | |
8678 | continue; | |
8679 | if (member) | |
8680 | return NULL_TREE; | |
8681 | member = field; | |
8682 | } | |
8683 | return member; | |
8684 | } | |
514066a1 | 8685 | |
50fe8924 | 8686 | /* Implement `va_arg'. */ |
5fac2ed2 | 8687 | static tree |
726a989a RB |
8688 | sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
8689 | gimple_seq *post_p ATTRIBUTE_UNUSED) | |
514066a1 RH |
8690 | { |
8691 | HOST_WIDE_INT size, rsize; | |
318881c0 | 8692 | tree tmp, pptr_type_node; |
0ef2c525 | 8693 | tree addr, lab_over = NULL, result = NULL; |
57a944d7 | 8694 | bool pass_by_ref; |
11160b58 | 8695 | tree eff_type; |
5fac2ed2 | 8696 | |
57a944d7 KK |
8697 | if (!VOID_TYPE_P (type)) |
8698 | pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type); | |
8699 | else | |
8700 | pass_by_ref = false; | |
8701 | ||
5fac2ed2 RH |
8702 | if (pass_by_ref) |
8703 | type = build_pointer_type (type); | |
514066a1 RH |
8704 | |
8705 | size = int_size_in_bytes (type); | |
8706 | rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; | |
8707 | pptr_type_node = build_pointer_type (ptr_type_node); | |
8708 | ||
61f71b34 DD |
8709 | if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4) |
8710 | && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ())) | |
514066a1 RH |
8711 | { |
8712 | tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack; | |
8713 | tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack; | |
8714 | int pass_as_float; | |
5fac2ed2 | 8715 | tree lab_false; |
21bdb106 | 8716 | tree member; |
514066a1 RH |
8717 | |
8718 | f_next_o = TYPE_FIELDS (va_list_type_node); | |
910ad8de NF |
8719 | f_next_o_limit = DECL_CHAIN (f_next_o); |
8720 | f_next_fp = DECL_CHAIN (f_next_o_limit); | |
8721 | f_next_fp_limit = DECL_CHAIN (f_next_fp); | |
8722 | f_next_stack = DECL_CHAIN (f_next_fp_limit); | |
514066a1 | 8723 | |
47a25a46 RG |
8724 | next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o, |
8725 | NULL_TREE); | |
8726 | next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit), | |
8727 | valist, f_next_o_limit, NULL_TREE); | |
8728 | next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), | |
50fe8924 | 8729 | valist, f_next_fp, NULL_TREE); |
47a25a46 RG |
8730 | next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit), |
8731 | valist, f_next_fp_limit, NULL_TREE); | |
8732 | next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack), | |
8733 | valist, f_next_stack, NULL_TREE); | |
514066a1 | 8734 | |
6d1cb95f R |
8735 | /* Structures with a single member with a distinct mode are passed |
8736 | like their member. This is relevant if the latter has a REAL_TYPE | |
8737 | or COMPLEX_TYPE type. */ | |
11160b58 R |
8738 | eff_type = type; |
8739 | while (TREE_CODE (eff_type) == RECORD_TYPE | |
8740 | && (member = find_sole_member (eff_type)) | |
21bdb106 JR |
8741 | && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE |
8742 | || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE | |
8743 | || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE)) | |
c26104e4 | 8744 | { |
21bdb106 | 8745 | tree field_type = TREE_TYPE (member); |
c26104e4 | 8746 | |
11160b58 R |
8747 | if (TYPE_MODE (eff_type) == TYPE_MODE (field_type)) |
8748 | eff_type = field_type; | |
c26104e4 | 8749 | else |
8a2209bf | 8750 | { |
11160b58 | 8751 | gcc_assert ((TYPE_ALIGN (eff_type) |
21bdb106 | 8752 | < GET_MODE_ALIGNMENT (TYPE_MODE (field_type))) |
11160b58 | 8753 | || (TYPE_ALIGN (eff_type) |
21bdb106 JR |
8754 | > GET_MODE_BITSIZE (TYPE_MODE (field_type)))); |
8755 | break; | |
8a2209bf | 8756 | } |
c26104e4 | 8757 | } |
5fac2ed2 | 8758 | |
bdf57c40 | 8759 | if (TARGET_SH4 || TARGET_SH2A_DOUBLE) |
514066a1 | 8760 | { |
11160b58 R |
8761 | pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8) |
8762 | || (TREE_CODE (eff_type) == COMPLEX_TYPE | |
8763 | && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE | |
514066a1 RH |
8764 | && size <= 16)); |
8765 | } | |
8766 | else | |
8767 | { | |
11160b58 | 8768 | pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4); |
514066a1 RH |
8769 | } |
8770 | ||
9b489f31 | 8771 | addr = create_tmp_var (pptr_type_node); |
4c4bde29 AH |
8772 | lab_false = create_artificial_label (UNKNOWN_LOCATION); |
8773 | lab_over = create_artificial_label (UNKNOWN_LOCATION); | |
514066a1 | 8774 | |
70f34814 | 8775 | valist = build_simple_mem_ref (addr); |
6d1cb95f | 8776 | |
514066a1 RH |
8777 | if (pass_as_float) |
8778 | { | |
9b489f31 | 8779 | tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp)); |
a11c004b | 8780 | tree cmp; |
11160b58 | 8781 | bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE; |
f78ec36a | 8782 | |
8c54989a KK |
8783 | tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp)); |
8784 | gimplify_assign (unshare_expr (addr), tmp, pre_p); | |
a11c004b | 8785 | |
8c54989a | 8786 | gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p); |
a11c004b R |
8787 | tmp = next_fp_limit; |
8788 | if (size > 4 && !is_double) | |
5d49b6a7 | 8789 | tmp = fold_build_pointer_plus_hwi (unshare_expr (tmp), 4 - size); |
8c54989a KK |
8790 | tmp = build2 (GE_EXPR, boolean_type_node, |
8791 | unshare_expr (next_fp_tmp), unshare_expr (tmp)); | |
47a25a46 | 8792 | cmp = build3 (COND_EXPR, void_type_node, tmp, |
8c54989a KK |
8793 | build1 (GOTO_EXPR, void_type_node, |
8794 | unshare_expr (lab_false)), NULL_TREE); | |
a11c004b R |
8795 | if (!is_double) |
8796 | gimplify_and_add (cmp, pre_p); | |
514066a1 | 8797 | |
11160b58 R |
8798 | if (TYPE_ALIGN (eff_type) > BITS_PER_WORD |
8799 | || (is_double || size == 16)) | |
514066a1 | 8800 | { |
5be014d5 AP |
8801 | tmp = fold_convert (sizetype, next_fp_tmp); |
8802 | tmp = build2 (BIT_AND_EXPR, sizetype, tmp, | |
8803 | size_int (UNITS_PER_WORD)); | |
5d49b6a7 | 8804 | tmp = fold_build_pointer_plus (unshare_expr (next_fp_tmp), tmp); |
8c54989a | 8805 | gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p); |
514066a1 | 8806 | } |
a11c004b R |
8807 | if (is_double) |
8808 | gimplify_and_add (cmp, pre_p); | |
514066a1 | 8809 | |
6d1cb95f | 8810 | #ifdef FUNCTION_ARG_SCmode_WART |
11160b58 R |
8811 | if (TYPE_MODE (eff_type) == SCmode |
8812 | && TARGET_SH4 && TARGET_LITTLE_ENDIAN) | |
6d1cb95f | 8813 | { |
11160b58 | 8814 | tree subtype = TREE_TYPE (eff_type); |
5fac2ed2 | 8815 | tree real, imag; |
6d1cb95f | 8816 | |
a11c004b R |
8817 | imag |
8818 | = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL); | |
5fac2ed2 | 8819 | imag = get_initialized_tmp_var (imag, pre_p, NULL); |
6d1cb95f | 8820 | |
a11c004b R |
8821 | real |
8822 | = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL); | |
5fac2ed2 RH |
8823 | real = get_initialized_tmp_var (real, pre_p, NULL); |
8824 | ||
f2a945b1 KK |
8825 | result = build2 (COMPLEX_EXPR, eff_type, real, imag); |
8826 | if (type != eff_type) | |
8827 | result = build1 (VIEW_CONVERT_EXPR, type, result); | |
5fac2ed2 | 8828 | result = get_initialized_tmp_var (result, pre_p, NULL); |
6d1cb95f R |
8829 | } |
8830 | #endif /* FUNCTION_ARG_SCmode_WART */ | |
8831 | ||
8c54989a | 8832 | tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over)); |
5fac2ed2 RH |
8833 | gimplify_and_add (tmp, pre_p); |
8834 | ||
8c54989a | 8835 | tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false)); |
5fac2ed2 | 8836 | gimplify_and_add (tmp, pre_p); |
514066a1 | 8837 | |
8c54989a KK |
8838 | tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack)); |
8839 | gimplify_assign (unshare_expr (addr), tmp, pre_p); | |
8840 | gimplify_assign (unshare_expr (next_fp_tmp), | |
8841 | unshare_expr (valist), pre_p); | |
a11c004b | 8842 | |
8c54989a KK |
8843 | gimplify_assign (unshare_expr (valist), |
8844 | unshare_expr (next_fp_tmp), post_p); | |
a11c004b | 8845 | valist = next_fp_tmp; |
514066a1 RH |
8846 | } |
8847 | else | |
8848 | { | |
5d49b6a7 | 8849 | tmp = fold_build_pointer_plus_hwi (unshare_expr (next_o), rsize); |
8c54989a KK |
8850 | tmp = build2 (GT_EXPR, boolean_type_node, tmp, |
8851 | unshare_expr (next_o_limit)); | |
47a25a46 | 8852 | tmp = build3 (COND_EXPR, void_type_node, tmp, |
8c54989a KK |
8853 | build1 (GOTO_EXPR, void_type_node, |
8854 | unshare_expr (lab_false)), | |
8855 | NULL_TREE); | |
5fac2ed2 | 8856 | gimplify_and_add (tmp, pre_p); |
514066a1 | 8857 | |
8c54989a KK |
8858 | tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o)); |
8859 | gimplify_assign (unshare_expr (addr), tmp, pre_p); | |
514066a1 | 8860 | |
8c54989a | 8861 | tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over)); |
5fac2ed2 RH |
8862 | gimplify_and_add (tmp, pre_p); |
8863 | ||
8c54989a | 8864 | tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false)); |
5fac2ed2 | 8865 | gimplify_and_add (tmp, pre_p); |
514066a1 | 8866 | |
bdf57c40 | 8867 | if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A)) |
8c54989a KK |
8868 | gimplify_assign (unshare_expr (next_o), |
8869 | unshare_expr (next_o_limit), pre_p); | |
514066a1 | 8870 | |
8c54989a KK |
8871 | tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack)); |
8872 | gimplify_assign (unshare_expr (addr), tmp, pre_p); | |
514066a1 RH |
8873 | } |
8874 | ||
5fac2ed2 RH |
8875 | if (!result) |
8876 | { | |
8c54989a | 8877 | tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over)); |
5fac2ed2 RH |
8878 | gimplify_and_add (tmp, pre_p); |
8879 | } | |
514066a1 RH |
8880 | } |
8881 | ||
8882 | /* ??? In va-sh.h, there had been code to make values larger than | |
8883 | size 8 indirect. This does not match the FUNCTION_ARG macros. */ | |
8884 | ||
5fac2ed2 | 8885 | tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL); |
6d1cb95f R |
8886 | if (result) |
8887 | { | |
726a989a | 8888 | gimplify_assign (result, tmp, pre_p); |
a1516d08 | 8889 | result = build1 (NOP_EXPR, TREE_TYPE (result), result); |
8c54989a | 8890 | tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over)); |
5fac2ed2 | 8891 | gimplify_and_add (tmp, pre_p); |
6d1cb95f R |
8892 | } |
8893 | else | |
5fac2ed2 | 8894 | result = tmp; |
6d1cb95f | 8895 | |
5e039e6b | 8896 | if (pass_by_ref) |
d6e9821f | 8897 | result = build_va_arg_indirect_ref (result); |
5fac2ed2 | 8898 | |
5e039e6b | 8899 | return result; |
514066a1 RH |
8900 | } |
8901 | ||
63a9de54 | 8902 | /* 64 bit floating points memory transfers are paired single precision loads |
50fe8924 | 8903 | or store. So DWARF information needs fixing in little endian (unless |
63a9de54 CB |
8904 | PR=SZ=1 in FPSCR). */ |
8905 | rtx | |
8906 | sh_dwarf_register_span (rtx reg) | |
8907 | { | |
8908 | unsigned regno = REGNO (reg); | |
8909 | ||
8910 | if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode) | |
8911 | return NULL_RTX; | |
8912 | ||
8913 | return | |
8914 | gen_rtx_PARALLEL (VOIDmode, | |
8915 | gen_rtvec (2, | |
59248459 KK |
8916 | gen_rtx_REG (SFmode, regno + 1), |
8917 | gen_rtx_REG (SFmode, regno))); | |
63a9de54 CB |
8918 | } |
8919 | ||
ef4bddc2 RS |
8920 | static machine_mode |
8921 | sh_promote_function_mode (const_tree type, machine_mode mode, | |
d8158ff1 | 8922 | int *punsignedp, const_tree funtype, |
8a575d5a | 8923 | int for_return) |
cde0f3fd PB |
8924 | { |
8925 | if (sh_promote_prototypes (funtype)) | |
d055ce45 | 8926 | return promote_mode (type, mode, punsignedp); |
cde0f3fd | 8927 | else |
8a575d5a PB |
8928 | return default_promote_function_mode (type, mode, punsignedp, funtype, |
8929 | for_return); | |
cde0f3fd PB |
8930 | } |
8931 | ||
d64728cf | 8932 | static bool |
586de218 | 8933 | sh_promote_prototypes (const_tree type) |
61f71b34 DD |
8934 | { |
8935 | if (TARGET_HITACHI) | |
aaf701c5 | 8936 | return false; |
61f71b34 | 8937 | if (! type) |
aaf701c5 | 8938 | return true; |
61f71b34 DD |
8939 | return ! sh_attr_renesas_p (type); |
8940 | } | |
8941 | ||
8cd5a4e0 RH |
8942 | /* Whether an argument must be passed by reference. On SHcompact, we |
8943 | pretend arguments wider than 32-bits that would have been passed in | |
8944 | registers are passed by reference, so that an SHmedia trampoline | |
8945 | loads them into the full 64-bits registers. */ | |
8cd5a4e0 | 8946 | static int |
ef4bddc2 | 8947 | shcompact_byref (const CUMULATIVE_ARGS *cum, machine_mode mode, |
586de218 | 8948 | const_tree type, bool named) |
8cd5a4e0 RH |
8949 | { |
8950 | unsigned HOST_WIDE_INT size; | |
8951 | ||
8952 | if (type) | |
8953 | size = int_size_in_bytes (type); | |
8954 | else | |
8955 | size = GET_MODE_SIZE (mode); | |
8956 | ||
8957 | if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode) | |
8958 | && (!named | |
8959 | || GET_SH_ARG_CLASS (mode) == SH_ARG_INT | |
8960 | || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT | |
8961 | && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode))) | |
8962 | && size > 4 | |
8963 | && !SHCOMPACT_FORCE_ON_STACK (mode, type) | |
8964 | && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named)) | |
8965 | return size; | |
8966 | else | |
8967 | return 0; | |
8968 | } | |
8969 | ||
8970 | static bool | |
ef4bddc2 | 8971 | sh_pass_by_reference (cumulative_args_t cum_v, machine_mode mode, |
586de218 | 8972 | const_tree type, bool named) |
8cd5a4e0 | 8973 | { |
d5cc9181 JR |
8974 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
8975 | ||
8cd5a4e0 RH |
8976 | if (targetm.calls.must_pass_in_stack (mode, type)) |
8977 | return true; | |
8978 | ||
03603192 JR |
8979 | /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function |
8980 | wants to know about pass-by-reference semantics for incoming | |
8981 | arguments. */ | |
8982 | if (! cum) | |
8983 | return false; | |
8984 | ||
8cd5a4e0 RH |
8985 | if (TARGET_SHCOMPACT) |
8986 | { | |
8987 | cum->byref = shcompact_byref (cum, mode, type, named); | |
8988 | return cum->byref != 0; | |
8989 | } | |
8990 | ||
8991 | return false; | |
8992 | } | |
8993 | ||
6cdd5672 | 8994 | static bool |
ef4bddc2 | 8995 | sh_callee_copies (cumulative_args_t cum, machine_mode mode, |
586de218 | 8996 | const_tree type, bool named ATTRIBUTE_UNUSED) |
6cdd5672 RH |
8997 | { |
8998 | /* ??? How can it possibly be correct to return true only on the | |
8999 | caller side of the equation? Is there someplace else in the | |
9000 | sh backend that's magically producing the copies? */ | |
d5cc9181 | 9001 | return (get_cumulative_args (cum)->outgoing |
6cdd5672 RH |
9002 | && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) |
9003 | % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0)); | |
9004 | } | |
9005 | ||
f6982a08 OE |
9006 | /* Round a register number up to a proper boundary for an arg of mode |
9007 | MODE. | |
9008 | The SH doesn't care about double alignment, so we only | |
9009 | round doubles to even regs when asked to explicitly. */ | |
9010 | static int | |
9011 | sh_round_reg (const CUMULATIVE_ARGS& cum, machine_mode mode) | |
9012 | { | |
9013 | /* FIXME: This used to be a macro and has been copy pasted into this | |
9014 | function as is. Make this more readable. */ | |
9015 | return | |
9016 | (((TARGET_ALIGN_DOUBLE | |
9017 | || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) | |
9018 | && (mode == DFmode || mode == DCmode) | |
9019 | && cum.arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (mode))) | |
9020 | && GET_MODE_UNIT_SIZE (mode) > UNITS_PER_WORD) | |
9021 | ? (cum.arg_count[(int) GET_SH_ARG_CLASS (mode)] | |
9022 | + (cum.arg_count[(int) GET_SH_ARG_CLASS (mode)] & 1)) | |
9023 | : cum.arg_count[(int) GET_SH_ARG_CLASS (mode)]); | |
9024 | } | |
9025 | ||
026c3cfd | 9026 | /* Return true if arg of the specified mode should be passed in a register |
f6982a08 OE |
9027 | or false otherwise. */ |
9028 | static bool | |
9029 | sh_pass_in_reg_p (const CUMULATIVE_ARGS& cum, machine_mode mode, | |
9030 | const_tree type) | |
9031 | { | |
9032 | /* FIXME: This used to be a macro and has been copy pasted into this | |
9033 | function as is. Make this more readable. */ | |
9034 | return | |
9035 | ((type == 0 | |
9036 | || (! TREE_ADDRESSABLE (type) | |
9037 | && (! (TARGET_HITACHI || cum.renesas_abi) | |
9038 | || ! (AGGREGATE_TYPE_P (type) | |
9039 | || (!TARGET_FPU_ANY | |
9040 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
9041 | && GET_MODE_SIZE (mode) > GET_MODE_SIZE (SFmode))))))) | |
9042 | && ! cum.force_mem | |
9043 | && (TARGET_SH2E | |
9044 | ? ((mode) == BLKmode | |
9045 | ? ((cum.arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD | |
9046 | + int_size_in_bytes (type)) | |
9047 | <= NPARM_REGS (SImode) * UNITS_PER_WORD) | |
9048 | : ((sh_round_reg (cum, mode) | |
9049 | + HARD_REGNO_NREGS (BASE_ARG_REG (mode), mode)) | |
9050 | <= NPARM_REGS (mode))) | |
9051 | : sh_round_reg (cum, mode) < NPARM_REGS (mode))); | |
9052 | } | |
9053 | ||
78a52f11 | 9054 | static int |
ef4bddc2 | 9055 | sh_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode, |
78a52f11 RH |
9056 | tree type, bool named ATTRIBUTE_UNUSED) |
9057 | { | |
d5cc9181 | 9058 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
78a52f11 RH |
9059 | int words = 0; |
9060 | ||
9061 | if (!TARGET_SH5 | |
f6982a08 | 9062 | && sh_pass_in_reg_p (*cum, mode, type) |
78a52f11 | 9063 | && !(TARGET_SH4 || TARGET_SH2A_DOUBLE) |
f6982a08 | 9064 | && (sh_round_reg (*cum, mode) |
78a52f11 | 9065 | + (mode != BLKmode |
f6982a08 OE |
9066 | ? CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD) |
9067 | : CEIL (int_size_in_bytes (type), UNITS_PER_WORD)) | |
78a52f11 | 9068 | > NPARM_REGS (mode))) |
f6982a08 | 9069 | words = NPARM_REGS (mode) - sh_round_reg (*cum, mode); |
78a52f11 RH |
9070 | |
9071 | else if (!TARGET_SHCOMPACT | |
9072 | && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named)) | |
9073 | words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT]; | |
9074 | ||
9075 | return words * UNITS_PER_WORD; | |
9076 | } | |
9077 | ||
9078 | ||
61f71b34 DD |
9079 | /* Define where to put the arguments to a function. |
9080 | Value is zero to push the argument on the stack, | |
9081 | or a hard register in which to store the argument. | |
9082 | ||
9083 | MODE is the argument's machine mode. | |
9084 | TYPE is the data type of the argument (as a tree). | |
9085 | This is null for libcalls where that information may | |
9086 | not be available. | |
9087 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
9088 | the preceding args and about the function being called. | |
9089 | NAMED is nonzero if this argument is a named parameter | |
9090 | (otherwise it is an extra parameter matching an ellipsis). | |
9091 | ||
9092 | On SH the first args are normally in registers | |
9093 | and the rest are pushed. Any arg that starts within the first | |
9094 | NPARM_REGS words is at least partially passed in a register unless | |
9095 | its data type forbids. */ | |
b64336b8 | 9096 | static rtx |
ef4bddc2 | 9097 | sh_function_arg (cumulative_args_t ca_v, machine_mode mode, |
b64336b8 | 9098 | const_tree type, bool named) |
61f71b34 | 9099 | { |
d5cc9181 JR |
9100 | CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); |
9101 | ||
61f71b34 DD |
9102 | if (! TARGET_SH5 && mode == VOIDmode) |
9103 | return GEN_INT (ca->renesas_abi ? 1 : 0); | |
9104 | ||
9105 | if (! TARGET_SH5 | |
f6982a08 | 9106 | && sh_pass_in_reg_p (*ca, mode, type) |
61f71b34 DD |
9107 | && (named || ! (TARGET_HITACHI || ca->renesas_abi))) |
9108 | { | |
9109 | int regno; | |
9110 | ||
9111 | if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN | |
f6982a08 | 9112 | && (! FUNCTION_ARG_SCmode_WART || (sh_round_reg (*ca, mode) & 1))) |
61f71b34 DD |
9113 | { |
9114 | rtx r1 = gen_rtx_EXPR_LIST (VOIDmode, | |
9115 | gen_rtx_REG (SFmode, | |
9116 | BASE_ARG_REG (mode) | |
f6982a08 | 9117 | + (sh_round_reg (*ca, mode) ^ 1)), |
61f71b34 | 9118 | const0_rtx); |
832a3292 KH |
9119 | rtx r2 = gen_rtx_EXPR_LIST (VOIDmode, |
9120 | gen_rtx_REG (SFmode, | |
9121 | BASE_ARG_REG (mode) | |
f6982a08 | 9122 | + ((sh_round_reg (*ca, mode) + 1) ^ 1)), |
832a3292 | 9123 | GEN_INT (4)); |
61f71b34 DD |
9124 | return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2)); |
9125 | } | |
9126 | ||
9127 | /* If the alignment of a DF value causes an SF register to be | |
9128 | skipped, we will use that skipped register for the next SF | |
9129 | value. */ | |
9130 | if ((TARGET_HITACHI || ca->renesas_abi) | |
9131 | && ca->free_single_fp_reg | |
9132 | && mode == SFmode) | |
9133 | return gen_rtx_REG (mode, ca->free_single_fp_reg); | |
9134 | ||
f6982a08 | 9135 | regno = (BASE_ARG_REG (mode) + sh_round_reg (*ca, mode)) |
61f71b34 | 9136 | ^ (mode == SFmode && TARGET_SH4 |
23d0939b | 9137 | && TARGET_LITTLE_ENDIAN |
61f71b34 DD |
9138 | && ! TARGET_HITACHI && ! ca->renesas_abi); |
9139 | return gen_rtx_REG (mode, regno); | |
9140 | ||
9141 | } | |
f676971a | 9142 | |
61f71b34 DD |
9143 | if (TARGET_SH5) |
9144 | { | |
9145 | if (mode == VOIDmode && TARGET_SHCOMPACT) | |
9146 | return GEN_INT (ca->call_cookie); | |
9147 | ||
9148 | /* The following test assumes unnamed arguments are promoted to | |
9149 | DFmode. */ | |
9150 | if (mode == SFmode && ca->free_single_fp_reg) | |
9151 | return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg); | |
9152 | ||
9153 | if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT) | |
9154 | && (named || ! ca->prototype_p) | |
9155 | && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode)) | |
9156 | { | |
9157 | if (! ca->prototype_p && TARGET_SHMEDIA) | |
9158 | return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode); | |
9159 | ||
9160 | return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, | |
9161 | FIRST_FP_PARM_REG | |
9162 | + ca->arg_count[(int) SH_ARG_FLOAT]); | |
9163 | } | |
9164 | ||
9165 | if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) | |
9166 | && (! TARGET_SHCOMPACT | |
9167 | || (! SHCOMPACT_FORCE_ON_STACK (mode, type) | |
9168 | && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode, | |
9169 | type, named)))) | |
9170 | { | |
9171 | return gen_rtx_REG (mode, (FIRST_PARM_REG | |
9172 | + ca->arg_count[(int) SH_ARG_INT])); | |
9173 | } | |
9174 | ||
23d0939b | 9175 | return NULL_RTX; |
61f71b34 DD |
9176 | } |
9177 | ||
23d0939b | 9178 | return NULL_RTX; |
61f71b34 | 9179 | } |
f676971a | 9180 | |
61f71b34 DD |
9181 | /* Update the data in CUM to advance over an argument |
9182 | of mode MODE and data type TYPE. | |
9183 | (TYPE is null for libcalls where that information may not be | |
9184 | available.) */ | |
b64336b8 | 9185 | static void |
ef4bddc2 | 9186 | sh_function_arg_advance (cumulative_args_t ca_v, machine_mode mode, |
b64336b8 | 9187 | const_tree type, bool named) |
61f71b34 | 9188 | { |
d5cc9181 JR |
9189 | CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); |
9190 | ||
832a3292 KH |
9191 | if (ca->force_mem) |
9192 | ca->force_mem = 0; | |
9193 | else if (TARGET_SH5) | |
9194 | { | |
b64336b8 NF |
9195 | const_tree type2 = (ca->byref && type |
9196 | ? TREE_TYPE (type) | |
9197 | : type); | |
ef4bddc2 | 9198 | machine_mode mode2 = (ca->byref && type |
832a3292 KH |
9199 | ? TYPE_MODE (type2) |
9200 | : mode); | |
9201 | int dwords = ((ca->byref | |
9202 | ? ca->byref | |
9203 | : mode2 == BLKmode | |
9204 | ? int_size_in_bytes (type2) | |
9205 | : GET_MODE_SIZE (mode2)) + 7) / 8; | |
9206 | int numregs = MIN (dwords, NPARM_REGS (SImode) | |
9207 | - ca->arg_count[(int) SH_ARG_INT]); | |
9208 | ||
9209 | if (numregs) | |
9210 | { | |
9211 | ca->arg_count[(int) SH_ARG_INT] += numregs; | |
9212 | if (TARGET_SHCOMPACT | |
9213 | && SHCOMPACT_FORCE_ON_STACK (mode2, type2)) | |
9214 | { | |
9215 | ca->call_cookie | |
9216 | |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT] | |
9217 | - numregs, 1); | |
9218 | /* N.B. We want this also for outgoing. */ | |
9219 | ca->stack_regs += numregs; | |
9220 | } | |
9221 | else if (ca->byref) | |
9222 | { | |
9223 | if (! ca->outgoing) | |
9224 | ca->stack_regs += numregs; | |
9225 | ca->byref_regs += numregs; | |
9226 | ca->byref = 0; | |
9227 | do | |
9228 | ca->call_cookie | |
9229 | |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT] | |
9230 | - numregs, 2); | |
9231 | while (--numregs); | |
9232 | ca->call_cookie | |
9233 | |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT] | |
9234 | - 1, 1); | |
9235 | } | |
9236 | else if (dwords > numregs) | |
9237 | { | |
9238 | int pushregs = numregs; | |
9239 | ||
9240 | if (TARGET_SHCOMPACT) | |
9241 | ca->stack_regs += numregs; | |
9242 | while (pushregs < NPARM_REGS (SImode) - 1 | |
9243 | && (CALL_COOKIE_INT_REG_GET | |
9244 | (ca->call_cookie, | |
9245 | NPARM_REGS (SImode) - pushregs) | |
9246 | == 1)) | |
9247 | { | |
9248 | ca->call_cookie | |
9249 | &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) | |
9250 | - pushregs, 1); | |
9251 | pushregs++; | |
9252 | } | |
9253 | if (numregs == NPARM_REGS (SImode)) | |
9254 | ca->call_cookie | |
9255 | |= CALL_COOKIE_INT_REG (0, 1) | |
9256 | | CALL_COOKIE_STACKSEQ (numregs - 1); | |
9257 | else | |
9258 | ca->call_cookie | |
9259 | |= CALL_COOKIE_STACKSEQ (numregs); | |
9260 | } | |
9261 | } | |
9262 | if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT | |
9263 | && (named || ! ca->prototype_p)) | |
9264 | { | |
9265 | if (mode2 == SFmode && ca->free_single_fp_reg) | |
9266 | ca->free_single_fp_reg = 0; | |
9267 | else if (ca->arg_count[(int) SH_ARG_FLOAT] | |
9268 | < NPARM_REGS (SFmode)) | |
9269 | { | |
9270 | int numfpregs | |
9271 | = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2, | |
9272 | NPARM_REGS (SFmode) | |
9273 | - ca->arg_count[(int) SH_ARG_FLOAT]); | |
9274 | ||
9275 | ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs; | |
9276 | ||
9277 | if (TARGET_SHCOMPACT && ! ca->prototype_p) | |
9278 | { | |
9279 | if (ca->outgoing && numregs > 0) | |
9280 | do | |
9281 | { | |
9282 | ca->call_cookie | |
9283 | |= (CALL_COOKIE_INT_REG | |
9284 | (ca->arg_count[(int) SH_ARG_INT] | |
9285 | - numregs + ((numfpregs - 2) / 2), | |
9286 | 4 + (ca->arg_count[(int) SH_ARG_FLOAT] | |
9287 | - numfpregs) / 2)); | |
9288 | } | |
9289 | while (numfpregs -= 2); | |
9290 | } | |
9291 | else if (mode2 == SFmode && (named) | |
9292 | && (ca->arg_count[(int) SH_ARG_FLOAT] | |
9293 | < NPARM_REGS (SFmode))) | |
9294 | ca->free_single_fp_reg | |
9295 | = FIRST_FP_PARM_REG - numfpregs | |
9296 | + ca->arg_count[(int) SH_ARG_FLOAT] + 1; | |
9297 | } | |
9298 | } | |
9299 | return; | |
9300 | } | |
9301 | ||
9302 | if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE) | |
9303 | { | |
9304 | /* Note that we've used the skipped register. */ | |
9305 | if (mode == SFmode && ca->free_single_fp_reg) | |
9306 | { | |
9307 | ca->free_single_fp_reg = 0; | |
9308 | return; | |
9309 | } | |
9310 | /* When we have a DF after an SF, there's an SF register that get | |
9311 | skipped in order to align the DF value. We note this skipped | |
9312 | register, because the next SF value will use it, and not the | |
9313 | SF that follows the DF. */ | |
9314 | if (mode == DFmode | |
f6982a08 | 9315 | && sh_round_reg (*ca, DFmode) != sh_round_reg (*ca, SFmode)) |
832a3292 | 9316 | { |
f6982a08 | 9317 | ca->free_single_fp_reg = (sh_round_reg (*ca, SFmode) |
832a3292 KH |
9318 | + BASE_ARG_REG (mode)); |
9319 | } | |
9320 | } | |
9321 | ||
157371cf | 9322 | if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi) |
f6982a08 | 9323 | || sh_pass_in_reg_p (*ca, mode, type)) |
832a3292 | 9324 | (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)] |
f6982a08 | 9325 | = (sh_round_reg (*ca, mode) |
832a3292 | 9326 | + (mode == BLKmode |
f6982a08 OE |
9327 | ? CEIL (int_size_in_bytes (type), UNITS_PER_WORD) |
9328 | : CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD)))); | |
61f71b34 DD |
9329 | } |
9330 | ||
61f71b34 DD |
9331 | /* The Renesas calling convention doesn't quite fit into this scheme since |
9332 | the address is passed like an invisible argument, but one that is always | |
9333 | passed in memory. */ | |
9334 | static rtx | |
cf277499 | 9335 | sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED) |
61f71b34 DD |
9336 | { |
9337 | if (TARGET_HITACHI || sh_attr_renesas_p (fndecl)) | |
23d0939b | 9338 | return NULL_RTX; |
61f71b34 DD |
9339 | return gen_rtx_REG (Pmode, 2); |
9340 | } | |
9341 | ||
d64728cf AS |
9342 | /* Worker function for TARGET_FUNCTION_VALUE. |
9343 | ||
9344 | For the SH, this is like LIBCALL_VALUE, except that we must change the | |
9345 | mode like PROMOTE_MODE does. | |
9346 | ??? PROMOTE_MODE is ignored for non-scalar types. The set of types | |
50fe8924 OE |
9347 | tested here has to be kept in sync with the one in |
9348 | explow.c:promote_mode. */ | |
d64728cf AS |
9349 | static rtx |
9350 | sh_function_value (const_tree valtype, | |
9351 | const_tree fn_decl_or_type, | |
9352 | bool outgoing ATTRIBUTE_UNUSED) | |
9353 | { | |
9354 | if (fn_decl_or_type | |
9355 | && !DECL_P (fn_decl_or_type)) | |
9356 | fn_decl_or_type = NULL; | |
9357 | ||
9358 | return gen_rtx_REG ( | |
9359 | ((GET_MODE_CLASS (TYPE_MODE (valtype)) == MODE_INT | |
9360 | && GET_MODE_SIZE (TYPE_MODE (valtype)) < 4 | |
9361 | && (TREE_CODE (valtype) == INTEGER_TYPE | |
9362 | || TREE_CODE (valtype) == ENUMERAL_TYPE | |
9363 | || TREE_CODE (valtype) == BOOLEAN_TYPE | |
9364 | || TREE_CODE (valtype) == REAL_TYPE | |
9365 | || TREE_CODE (valtype) == OFFSET_TYPE)) | |
9366 | && sh_promote_prototypes (fn_decl_or_type) | |
9367 | ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (valtype)), | |
9368 | BASE_RETURN_VALUE_REG (TYPE_MODE (valtype))); | |
9369 | } | |
9370 | ||
9371 | /* Worker function for TARGET_LIBCALL_VALUE. */ | |
d64728cf | 9372 | static rtx |
ef4bddc2 | 9373 | sh_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) |
d64728cf AS |
9374 | { |
9375 | return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG (mode)); | |
9376 | } | |
9377 | ||
e7a8f681 | 9378 | /* Return true if N is a possible register number of function value. */ |
e7a8f681 | 9379 | static bool |
d64728cf AS |
9380 | sh_function_value_regno_p (const unsigned int regno) |
9381 | { | |
9382 | return ((regno) == FIRST_RET_REG | |
9383 | || (TARGET_SH2E && (regno) == FIRST_FP_RET_REG) | |
9384 | || (TARGET_SHMEDIA_FPU && (regno) == FIRST_FP_RET_REG)); | |
9385 | } | |
9386 | ||
bd5bd7ac | 9387 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
61f71b34 | 9388 | static bool |
586de218 | 9389 | sh_return_in_memory (const_tree type, const_tree fndecl) |
61f71b34 DD |
9390 | { |
9391 | if (TARGET_SH5) | |
9392 | { | |
9393 | if (TYPE_MODE (type) == BLKmode) | |
9394 | return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8; | |
9395 | else | |
9396 | return GET_MODE_SIZE (TYPE_MODE (type)) > 8; | |
9397 | } | |
9398 | else | |
9399 | { | |
9400 | return (TYPE_MODE (type) == BLKmode | |
9401 | || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl)) | |
9402 | && TREE_CODE (type) == RECORD_TYPE)); | |
9403 | } | |
9404 | } | |
9405 | ||
9406 | /* We actually emit the code in sh_expand_prologue. We used to use | |
9407 | a static variable to flag that we need to emit this code, but that | |
9408 | doesn't when inlining, when functions are deferred and then emitted | |
9409 | later. Fortunately, we already have two flags that are part of struct | |
9410 | function that tell if a function uses varargs or stdarg. */ | |
9411 | static void | |
d5cc9181 | 9412 | sh_setup_incoming_varargs (cumulative_args_t ca, |
ef4bddc2 | 9413 | machine_mode mode, |
49616835 JR |
9414 | tree type, |
9415 | int *pretend_arg_size, | |
cf277499 | 9416 | int second_time ATTRIBUTE_UNUSED) |
61f71b34 | 9417 | { |
e3b5732b | 9418 | gcc_assert (cfun->stdarg); |
49616835 JR |
9419 | if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)) |
9420 | { | |
9421 | int named_parm_regs, anon_parm_regs; | |
9422 | ||
f6982a08 | 9423 | named_parm_regs = (sh_round_reg (*get_cumulative_args (ca), mode) |
49616835 | 9424 | + (mode == BLKmode |
f6982a08 OE |
9425 | ? CEIL (int_size_in_bytes (type), UNITS_PER_WORD) |
9426 | : CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD))); | |
49616835 JR |
9427 | anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs; |
9428 | if (anon_parm_regs > 0) | |
9429 | *pretend_arg_size = anon_parm_regs * 4; | |
9430 | } | |
61f71b34 DD |
9431 | } |
9432 | ||
9433 | static bool | |
d5cc9181 | 9434 | sh_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) |
61f71b34 DD |
9435 | { |
9436 | return TARGET_SH5; | |
9437 | } | |
9438 | ||
9439 | static bool | |
d5cc9181 | 9440 | sh_pretend_outgoing_varargs_named (cumulative_args_t ca_v) |
61f71b34 | 9441 | { |
d5cc9181 JR |
9442 | CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); |
9443 | ||
61f71b34 DD |
9444 | return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5; |
9445 | } | |
9446 | ||
9447 | ||
0d7e008e SC |
9448 | /* Define the offset between two registers, one to be eliminated, and |
9449 | the other its replacement, at the start of a routine. */ | |
0d7e008e | 9450 | int |
cf277499 | 9451 | initial_elimination_offset (int from, int to) |
0d7e008e SC |
9452 | { |
9453 | int regs_saved; | |
fa5322fa | 9454 | int regs_saved_rounding = 0; |
0d7e008e | 9455 | int total_saved_regs_space; |
e5f8d4c0 | 9456 | int total_auto_space; |
1245df60 | 9457 | int save_flags = target_flags; |
fa5322fa | 9458 | int copy_flags; |
490dbac7 | 9459 | HARD_REG_SET live_regs_mask; |
fe3ad572 SC |
9460 | |
9461 | shmedia_space_reserved_for_target_registers = false; | |
490dbac7 | 9462 | regs_saved = calc_live_regs (&live_regs_mask); |
fa5322fa | 9463 | regs_saved += SHMEDIA_REGS_STACK_ADJUST (); |
fe3ad572 SC |
9464 | |
9465 | if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask)) | |
9466 | { | |
9467 | shmedia_space_reserved_for_target_registers = true; | |
9468 | regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask); | |
9469 | } | |
9470 | ||
fa5322fa AO |
9471 | if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT)) |
9472 | regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT) | |
9473 | - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT)); | |
8e87e161 | 9474 | |
fa5322fa AO |
9475 | total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding; |
9476 | copy_flags = target_flags; | |
1245df60 | 9477 | target_flags = save_flags; |
1a95a963 | 9478 | |
fa5322fa | 9479 | total_saved_regs_space = regs_saved + regs_saved_rounding; |
b9654711 | 9480 | |
96a2347e | 9481 | if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) |
fa5322fa | 9482 | return total_saved_regs_space + total_auto_space |
50fe8924 | 9483 | + crtl->args.info.byref_regs * 8; |
8aa2a305 | 9484 | |
0d7e008e | 9485 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
fa5322fa | 9486 | return total_saved_regs_space + total_auto_space |
50fe8924 | 9487 | + crtl->args.info.byref_regs * 8; |
8aa2a305 JW |
9488 | |
9489 | /* Initial gap between fp and sp is 0. */ | |
96a2347e | 9490 | if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
8aa2a305 JW |
9491 | return 0; |
9492 | ||
96a2347e KK |
9493 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
9494 | return rounded_frame_size (0); | |
9495 | ||
9496 | if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) | |
9497 | return rounded_frame_size (0); | |
9498 | ||
f5b9e7c9 | 9499 | gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM |
96a2347e KK |
9500 | && (to == HARD_FRAME_POINTER_REGNUM |
9501 | || to == STACK_POINTER_REGNUM)); | |
f5b9e7c9 | 9502 | if (TARGET_SH5) |
d042370e | 9503 | { |
f5b9e7c9 NS |
9504 | int n = total_saved_regs_space; |
9505 | int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG; | |
9506 | save_schedule schedule; | |
9507 | save_entry *entry; | |
50fe8924 | 9508 | |
f5b9e7c9 | 9509 | n += total_auto_space; |
50fe8924 | 9510 | |
f5b9e7c9 NS |
9511 | /* If it wasn't saved, there's not much we can do. */ |
9512 | if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg)) | |
9513 | return n; | |
50fe8924 | 9514 | |
f5b9e7c9 | 9515 | target_flags = copy_flags; |
50fe8924 | 9516 | |
f5b9e7c9 NS |
9517 | sh5_schedule_saves (&live_regs_mask, &schedule, n); |
9518 | for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++) | |
9519 | if (entry->reg == pr_reg) | |
9520 | { | |
9521 | target_flags = save_flags; | |
9522 | return entry->offset; | |
9523 | } | |
9524 | gcc_unreachable (); | |
d042370e | 9525 | } |
f5b9e7c9 NS |
9526 | else |
9527 | return total_auto_space; | |
0d7e008e | 9528 | } |
3217af3e KK |
9529 | |
9530 | /* Parse the -mfixed-range= option string. */ | |
9531 | void | |
9532 | sh_fix_range (const char *const_str) | |
9533 | { | |
9534 | int i, first, last; | |
9535 | char *str, *dash, *comma; | |
50fe8924 | 9536 | |
3217af3e KK |
9537 | /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and |
9538 | REG2 are either register names or register numbers. The effect | |
9539 | of this option is to mark the registers in the range from REG1 to | |
9540 | REG2 as ``fixed'' so they won't be used by the compiler. */ | |
50fe8924 | 9541 | |
3217af3e KK |
9542 | i = strlen (const_str); |
9543 | str = (char *) alloca (i + 1); | |
9544 | memcpy (str, const_str, i + 1); | |
50fe8924 | 9545 | |
3217af3e KK |
9546 | while (1) |
9547 | { | |
9548 | dash = strchr (str, '-'); | |
9549 | if (!dash) | |
9550 | { | |
9551 | warning (0, "value of -mfixed-range must have form REG1-REG2"); | |
9552 | return; | |
9553 | } | |
9554 | *dash = '\0'; | |
9555 | comma = strchr (dash + 1, ','); | |
9556 | if (comma) | |
9557 | *comma = '\0'; | |
50fe8924 | 9558 | |
3217af3e KK |
9559 | first = decode_reg_name (str); |
9560 | if (first < 0) | |
9561 | { | |
9562 | warning (0, "unknown register name: %s", str); | |
9563 | return; | |
9564 | } | |
50fe8924 | 9565 | |
3217af3e KK |
9566 | last = decode_reg_name (dash + 1); |
9567 | if (last < 0) | |
9568 | { | |
9569 | warning (0, "unknown register name: %s", dash + 1); | |
9570 | return; | |
9571 | } | |
50fe8924 | 9572 | |
3217af3e | 9573 | *dash = '-'; |
50fe8924 | 9574 | |
3217af3e KK |
9575 | if (first > last) |
9576 | { | |
9577 | warning (0, "%s-%s is an empty range", str, dash + 1); | |
9578 | return; | |
9579 | } | |
50fe8924 | 9580 | |
3217af3e KK |
9581 | for (i = first; i <= last; ++i) |
9582 | fixed_regs[i] = call_used_regs[i] = 1; | |
9583 | ||
9584 | if (!comma) | |
9585 | break; | |
9586 | ||
9587 | *comma = ','; | |
9588 | str = comma + 1; | |
9589 | } | |
9590 | } | |
8aa2a305 | 9591 | \f |
a6ab9fc0 | 9592 | /* Insert any deferred function attributes from earlier pragmas. */ |
12a68f1f | 9593 | static void |
cf277499 | 9594 | sh_insert_attributes (tree node, tree *attributes) |
157131d7 | 9595 | { |
a6ab9fc0 R |
9596 | tree attrs; |
9597 | ||
9598 | if (TREE_CODE (node) != FUNCTION_DECL) | |
157131d7 SC |
9599 | return; |
9600 | ||
9601 | /* We are only interested in fields. */ | |
6615c446 | 9602 | if (!DECL_P (node)) |
157131d7 SC |
9603 | return; |
9604 | ||
a6ab9fc0 R |
9605 | /* Append the attributes to the deferred attributes. */ |
9606 | *sh_deferred_function_attributes_tail = *attributes; | |
9607 | attrs = sh_deferred_function_attributes; | |
9608 | if (!attrs) | |
9609 | return; | |
9610 | ||
9611 | /* Some attributes imply or require the interrupt attribute. */ | |
9612 | if (!lookup_attribute ("interrupt_handler", attrs) | |
9613 | && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node))) | |
9614 | { | |
9615 | /* If we have a trapa_handler, but no interrupt_handler attribute, | |
9616 | insert an interrupt_handler attribute. */ | |
9617 | if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE) | |
9618 | /* We can't use sh_pr_interrupt here because that's not in the | |
9619 | java frontend. */ | |
9620 | attrs | |
9621 | = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs); | |
561642fa AP |
9622 | /* However, for sp_switch, trap_exit, nosave_low_regs and resbank, |
9623 | if the interrupt attribute is missing, we ignore the attribute | |
9624 | and warn. */ | |
a6ab9fc0 R |
9625 | else if (lookup_attribute ("sp_switch", attrs) |
9626 | || lookup_attribute ("trap_exit", attrs) | |
561642fa AP |
9627 | || lookup_attribute ("nosave_low_regs", attrs) |
9628 | || lookup_attribute ("resbank", attrs)) | |
a6ab9fc0 R |
9629 | { |
9630 | tree *tail; | |
9631 | ||
9632 | for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs)) | |
9633 | { | |
9634 | if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs)) | |
9635 | || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs)) | |
561642fa AP |
9636 | || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs)) |
9637 | || is_attribute_p ("resbank", TREE_PURPOSE (attrs))) | |
a6ab9fc0 | 9638 | warning (OPT_Wattributes, |
29d08eba JM |
9639 | "%qE attribute only applies to interrupt functions", |
9640 | TREE_PURPOSE (attrs)); | |
a6ab9fc0 R |
9641 | else |
9642 | { | |
9643 | *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE, | |
9644 | NULL_TREE); | |
9645 | tail = &TREE_CHAIN (*tail); | |
9646 | } | |
9647 | } | |
9648 | attrs = *attributes; | |
9649 | } | |
9650 | } | |
9651 | ||
9652 | /* Install the processed list. */ | |
9653 | *attributes = attrs; | |
9654 | ||
9655 | /* Clear deferred attributes. */ | |
9656 | sh_deferred_function_attributes = NULL_TREE; | |
9657 | sh_deferred_function_attributes_tail = &sh_deferred_function_attributes; | |
157131d7 SC |
9658 | |
9659 | return; | |
9660 | } | |
9661 | ||
845f4111 | 9662 | /*------------------------------------------------------------------------------ |
86cf62b8 | 9663 | Target specific attributes |
845f4111 OE |
9664 | Supported attributes are: |
9665 | ||
9666 | * interrupt_handler | |
9667 | Specifies this function is an interrupt handler. | |
9668 | ||
9669 | * trapa_handler | |
9670 | Like interrupt_handler, but don't save all registers. | |
9671 | ||
9672 | * sp_switch | |
9673 | Specifies an alternate stack for an interrupt handler to run on. | |
9674 | ||
9675 | * trap_exit | |
9676 | Use a trapa to exit an interrupt function instead of rte. | |
9677 | ||
9678 | * nosave_low_regs | |
9679 | Don't save r0..r7 in an interrupt handler function. | |
9680 | This is useful on SH3* and SH4*, which have a separate set of low | |
9681 | regs for user and privileged modes. | |
9682 | This is mainly to be used for non-reentrant interrupt handlers (i.e. | |
9683 | those that run with interrupts disabled and thus can't be | |
9684 | interrupted thenselves). | |
9685 | ||
9686 | * renesas | |
9687 | Use Renesas calling/layout conventions (functions and structures). | |
9688 | ||
9689 | * resbank | |
9690 | In case of an interrupt handler function, use a register bank to | |
9691 | save registers R0-R14, MACH, MACL, GBR and PR. | |
9692 | This is available only on SH2A targets. | |
9693 | ||
9694 | * function_vector | |
9695 | Declares a function to be called using the TBR relative addressing | |
9696 | mode. Takes an argument that specifies the slot number in the table | |
9697 | where this function can be looked up by the JSR/N @@(disp8,TBR) insn. | |
61f71b34 | 9698 | */ |
4408efce | 9699 | |
561642fa AP |
9700 | /* Handle a 'resbank' attribute. */ |
9701 | static tree | |
9702 | sh_handle_resbank_handler_attribute (tree * node, tree name, | |
50fe8924 OE |
9703 | tree args ATTRIBUTE_UNUSED, |
9704 | int flags ATTRIBUTE_UNUSED, | |
9705 | bool * no_add_attrs) | |
561642fa AP |
9706 | { |
9707 | if (!TARGET_SH2A) | |
9708 | { | |
29d08eba | 9709 | warning (OPT_Wattributes, "%qE attribute is supported only for SH2A", |
50fe8924 | 9710 | name); |
561642fa AP |
9711 | *no_add_attrs = true; |
9712 | } | |
9713 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
9714 | { | |
29d08eba | 9715 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
50fe8924 | 9716 | name); |
561642fa AP |
9717 | *no_add_attrs = true; |
9718 | } | |
9719 | ||
9720 | return NULL_TREE; | |
9721 | } | |
9722 | ||
91d231cb JM |
9723 | /* Handle an "interrupt_handler" attribute; arguments as in |
9724 | struct attribute_spec.handler. */ | |
9725 | static tree | |
cf277499 | 9726 | sh_handle_interrupt_handler_attribute (tree *node, tree name, |
50fe8924 OE |
9727 | tree args ATTRIBUTE_UNUSED, |
9728 | int flags ATTRIBUTE_UNUSED, | |
9729 | bool *no_add_attrs) | |
91d231cb JM |
9730 | { |
9731 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
4408efce | 9732 | { |
29d08eba | 9733 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
50fe8924 | 9734 | name); |
91d231cb | 9735 | *no_add_attrs = true; |
4408efce | 9736 | } |
58ab7171 R |
9737 | else if (TARGET_SHCOMPACT) |
9738 | { | |
9739 | error ("attribute interrupt_handler is not compatible with -m5-compact"); | |
9740 | *no_add_attrs = true; | |
9741 | } | |
4408efce | 9742 | |
91d231cb JM |
9743 | return NULL_TREE; |
9744 | } | |
9745 | ||
561642fa AP |
9746 | /* Handle an 'function_vector' attribute; arguments as in |
9747 | struct attribute_spec.handler. */ | |
9748 | static tree | |
9749 | sh2a_handle_function_vector_handler_attribute (tree * node, tree name, | |
50fe8924 OE |
9750 | tree args ATTRIBUTE_UNUSED, |
9751 | int flags ATTRIBUTE_UNUSED, | |
9752 | bool * no_add_attrs) | |
561642fa AP |
9753 | { |
9754 | if (!TARGET_SH2A) | |
9755 | { | |
29d08eba | 9756 | warning (OPT_Wattributes, "%qE attribute only applies to SH2A", |
50fe8924 | 9757 | name); |
561642fa AP |
9758 | *no_add_attrs = true; |
9759 | } | |
9760 | else if (TREE_CODE (*node) != FUNCTION_DECL) | |
9761 | { | |
29d08eba | 9762 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
50fe8924 | 9763 | name); |
561642fa AP |
9764 | *no_add_attrs = true; |
9765 | } | |
9766 | else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST) | |
9767 | { | |
9768 | /* The argument must be a constant integer. */ | |
9769 | warning (OPT_Wattributes, | |
50fe8924 OE |
9770 | "%qE attribute argument not an integer constant", |
9771 | name); | |
561642fa AP |
9772 | *no_add_attrs = true; |
9773 | } | |
9774 | else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255) | |
9775 | { | |
9776 | /* The argument value must be between 0 to 255. */ | |
9777 | warning (OPT_Wattributes, | |
50fe8924 OE |
9778 | "%qE attribute argument should be between 0 to 255", |
9779 | name); | |
561642fa AP |
9780 | *no_add_attrs = true; |
9781 | } | |
9782 | return NULL_TREE; | |
9783 | } | |
9784 | ||
aaf701c5 | 9785 | /* Returns true if current function has been assigned the attribute |
561642fa | 9786 | 'function_vector'. */ |
aaf701c5 | 9787 | bool |
561642fa AP |
9788 | sh2a_is_function_vector_call (rtx x) |
9789 | { | |
9790 | if (GET_CODE (x) == SYMBOL_REF | |
9791 | && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION)) | |
9792 | { | |
9793 | tree tr = SYMBOL_REF_DECL (x); | |
9794 | ||
9795 | if (sh2a_function_vector_p (tr)) | |
aaf701c5 | 9796 | return true; |
561642fa AP |
9797 | } |
9798 | ||
aaf701c5 | 9799 | return false; |
561642fa AP |
9800 | } |
9801 | ||
dd5a833e | 9802 | /* Returns the function vector number, if the attribute |
561642fa AP |
9803 | 'function_vector' is assigned, otherwise returns zero. */ |
9804 | int | |
9805 | sh2a_get_function_vector_number (rtx x) | |
9806 | { | |
9807 | int num; | |
9808 | tree list, t; | |
9809 | ||
9810 | if ((GET_CODE (x) == SYMBOL_REF) | |
9811 | && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION)) | |
9812 | { | |
9813 | t = SYMBOL_REF_DECL (x); | |
9814 | ||
9815 | if (TREE_CODE (t) != FUNCTION_DECL) | |
50fe8924 | 9816 | return 0; |
561642fa AP |
9817 | |
9818 | list = SH_ATTRIBUTES (t); | |
9819 | while (list) | |
50fe8924 OE |
9820 | { |
9821 | if (is_attribute_p ("function_vector", TREE_PURPOSE (list))) | |
9822 | { | |
9823 | num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list))); | |
9824 | return num; | |
9825 | } | |
561642fa | 9826 | |
50fe8924 OE |
9827 | list = TREE_CHAIN (list); |
9828 | } | |
561642fa AP |
9829 | |
9830 | return 0; | |
9831 | } | |
9832 | else | |
9833 | return 0; | |
9834 | } | |
9835 | ||
91d231cb JM |
9836 | /* Handle an "sp_switch" attribute; arguments as in |
9837 | struct attribute_spec.handler. */ | |
9838 | static tree | |
cf277499 SB |
9839 | sh_handle_sp_switch_attribute (tree *node, tree name, tree args, |
9840 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
91d231cb JM |
9841 | { |
9842 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
9843 | { | |
29d08eba JM |
9844 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
9845 | name); | |
91d231cb JM |
9846 | *no_add_attrs = true; |
9847 | } | |
91d231cb JM |
9848 | else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST) |
9849 | { | |
4408efce | 9850 | /* The argument must be a constant string. */ |
29d08eba JM |
9851 | warning (OPT_Wattributes, "%qE attribute argument not a string constant", |
9852 | name); | |
91d231cb JM |
9853 | *no_add_attrs = true; |
9854 | } | |
4408efce | 9855 | |
91d231cb JM |
9856 | return NULL_TREE; |
9857 | } | |
9858 | ||
9859 | /* Handle an "trap_exit" attribute; arguments as in | |
9860 | struct attribute_spec.handler. */ | |
9861 | static tree | |
cf277499 SB |
9862 | sh_handle_trap_exit_attribute (tree *node, tree name, tree args, |
9863 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
91d231cb JM |
9864 | { |
9865 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
9866 | { | |
29d08eba JM |
9867 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
9868 | name); | |
91d231cb JM |
9869 | *no_add_attrs = true; |
9870 | } | |
a6ab9fc0 R |
9871 | /* The argument specifies a trap number to be used in a trapa instruction |
9872 | at function exit (instead of an rte instruction). */ | |
91d231cb JM |
9873 | else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST) |
9874 | { | |
4408efce | 9875 | /* The argument must be a constant integer. */ |
29d08eba JM |
9876 | warning (OPT_Wattributes, "%qE attribute argument not an " |
9877 | "integer constant", name); | |
91d231cb JM |
9878 | *no_add_attrs = true; |
9879 | } | |
318881c0 | 9880 | |
91d231cb | 9881 | return NULL_TREE; |
4408efce JL |
9882 | } |
9883 | ||
61f71b34 | 9884 | static tree |
cf277499 SB |
9885 | sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED, |
9886 | tree name ATTRIBUTE_UNUSED, | |
9887 | tree args ATTRIBUTE_UNUSED, | |
9888 | int flags ATTRIBUTE_UNUSED, | |
9889 | bool *no_add_attrs ATTRIBUTE_UNUSED) | |
61f71b34 DD |
9890 | { |
9891 | return NULL_TREE; | |
9892 | } | |
9893 | ||
9894 | /* True if __attribute__((renesas)) or -mrenesas. */ | |
aaf701c5 | 9895 | bool |
586de218 | 9896 | sh_attr_renesas_p (const_tree td) |
61f71b34 DD |
9897 | { |
9898 | if (TARGET_HITACHI) | |
aaf701c5 | 9899 | return true; |
23d0939b | 9900 | if (td == NULL_TREE) |
aaf701c5 | 9901 | return false; |
61f71b34 DD |
9902 | if (DECL_P (td)) |
9903 | td = TREE_TYPE (td); | |
a11c004b | 9904 | if (td == error_mark_node) |
aaf701c5 | 9905 | return false; |
61f71b34 DD |
9906 | return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td)) |
9907 | != NULL_TREE); | |
9908 | } | |
9909 | ||
9910 | /* True if __attribute__((renesas)) or -mrenesas, for the current | |
9911 | function. */ | |
aaf701c5 | 9912 | bool |
cf277499 | 9913 | sh_cfun_attr_renesas_p (void) |
61f71b34 DD |
9914 | { |
9915 | return sh_attr_renesas_p (current_function_decl); | |
9916 | } | |
9917 | ||
50fe8924 OE |
9918 | /* Returns true if the current function has the "interrupt_handler" |
9919 | attribute set. */ | |
aaf701c5 | 9920 | bool |
cf277499 | 9921 | sh_cfun_interrupt_handler_p (void) |
e3ba8d11 R |
9922 | { |
9923 | return (lookup_attribute ("interrupt_handler", | |
9924 | DECL_ATTRIBUTES (current_function_decl)) | |
9925 | != NULL_TREE); | |
9926 | } | |
bcc8cc82 | 9927 | |
aaf701c5 | 9928 | /* Returns true if FUNC has been assigned the attribute |
561642fa | 9929 | "function_vector". */ |
aaf701c5 | 9930 | bool |
561642fa AP |
9931 | sh2a_function_vector_p (tree func) |
9932 | { | |
9933 | tree list; | |
9934 | if (TREE_CODE (func) != FUNCTION_DECL) | |
aaf701c5 | 9935 | return false; |
561642fa AP |
9936 | |
9937 | list = SH_ATTRIBUTES (func); | |
9938 | while (list) | |
9939 | { | |
9940 | if (is_attribute_p ("function_vector", TREE_PURPOSE (list))) | |
50fe8924 | 9941 | return true; |
561642fa AP |
9942 | |
9943 | list = TREE_CHAIN (list); | |
9944 | } | |
aaf701c5 | 9945 | return false; |
561642fa AP |
9946 | } |
9947 | ||
50fe8924 | 9948 | /* Returns true if given tree has the "resbank" attribute set. */ |
aaf701c5 | 9949 | bool |
561642fa AP |
9950 | sh_cfun_resbank_handler_p (void) |
9951 | { | |
9952 | return ((lookup_attribute ("resbank", | |
50fe8924 OE |
9953 | DECL_ATTRIBUTES (current_function_decl)) |
9954 | != NULL_TREE) | |
9955 | && (lookup_attribute ("interrupt_handler", | |
9956 | DECL_ATTRIBUTES (current_function_decl)) | |
9957 | != NULL_TREE) && TARGET_SH2A); | |
561642fa AP |
9958 | } |
9959 | ||
d16202ba | 9960 | /* Returns true if the current function has a "trap_exit" attribute set. */ |
d16202ba OE |
9961 | bool |
9962 | sh_cfun_trap_exit_p (void) | |
9963 | { | |
9964 | return lookup_attribute ("trap_exit", DECL_ATTRIBUTES (current_function_decl)) | |
9965 | != NULL_TREE; | |
9966 | } | |
9967 | ||
8d932be3 | 9968 | /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */ |
8d932be3 RS |
9969 | static const char * |
9970 | sh_check_pch_target_flags (int old_flags) | |
9971 | { | |
c0fb94d7 RS |
9972 | if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3 |
9973 | | MASK_SH_E | MASK_HARD_SH4 | |
9974 | | MASK_FPU_SINGLE | MASK_SH4)) | |
9975 | return _("created and used with different architectures / ABIs"); | |
9976 | if ((old_flags ^ target_flags) & MASK_HITACHI) | |
9977 | return _("created and used with different ABIs"); | |
9978 | if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN) | |
9979 | return _("created and used with different endianness"); | |
bcc8cc82 | 9980 | return NULL; |
bcc8cc82 | 9981 | } |
0d7e008e | 9982 | \f |
8aa2a305 | 9983 | /* Predicates used by the templates. */ |
0d7e008e | 9984 | |
aaf701c5 | 9985 | /* Returns true if OP is MACL, MACH or PR. The input must be a REG rtx. |
8aa2a305 | 9986 | Used only in general_movsrc_operand. */ |
aaf701c5 | 9987 | bool |
ef4bddc2 | 9988 | system_reg_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) |
0d7e008e | 9989 | { |
8aa2a305 | 9990 | switch (REGNO (op)) |
0d7e008e | 9991 | { |
8aa2a305 JW |
9992 | case PR_REG: |
9993 | case MACL_REG: | |
9994 | case MACH_REG: | |
aaf701c5 | 9995 | return true; |
0d7e008e | 9996 | } |
aaf701c5 | 9997 | return false; |
0d7e008e | 9998 | } |
0d7e008e | 9999 | |
aaf701c5 | 10000 | /* Returns true if OP is a floating point value with value 0.0. */ |
aaf701c5 | 10001 | bool |
cf277499 | 10002 | fp_zero_operand (rtx op) |
d3ae8277 | 10003 | { |
1a95a963 | 10004 | REAL_VALUE_TYPE r; |
d3ae8277 | 10005 | |
1a95a963 | 10006 | if (GET_MODE (op) != SFmode) |
aaf701c5 | 10007 | return false; |
1a95a963 JW |
10008 | |
10009 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
e4fa6b06 | 10010 | return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r); |
d3ae8277 SC |
10011 | } |
10012 | ||
aaf701c5 | 10013 | /* Returns true if OP is a floating point value with value 1.0. */ |
aaf701c5 | 10014 | bool |
cf277499 | 10015 | fp_one_operand (rtx op) |
d3ae8277 | 10016 | { |
1a95a963 JW |
10017 | REAL_VALUE_TYPE r; |
10018 | ||
10019 | if (GET_MODE (op) != SFmode) | |
aaf701c5 | 10020 | return false; |
1a95a963 JW |
10021 | |
10022 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
10023 | return REAL_VALUES_EQUAL (r, dconst1); | |
d3ae8277 | 10024 | } |
1245df60 | 10025 | |
50fe8924 | 10026 | /* Return the TLS type for TLS symbols. */ |
81f40b79 | 10027 | enum tls_model |
ef4bddc2 | 10028 | tls_symbolic_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) |
463f02cd | 10029 | { |
463f02cd | 10030 | if (GET_CODE (op) != SYMBOL_REF) |
81f40b79 | 10031 | return TLS_MODEL_NONE; |
675ff4c7 | 10032 | return SYMBOL_REF_TLS_MODEL (op); |
463f02cd | 10033 | } |
1245df60 | 10034 | \f |
33f7f353 | 10035 | /* Return the destination address of a branch. */ |
318881c0 | 10036 | static int |
cf277499 | 10037 | branch_dest (rtx branch) |
1245df60 | 10038 | { |
33f7f353 JR |
10039 | rtx dest = SET_SRC (PATTERN (branch)); |
10040 | int dest_uid; | |
1245df60 R |
10041 | |
10042 | if (GET_CODE (dest) == IF_THEN_ELSE) | |
10043 | dest = XEXP (dest, 1); | |
10044 | dest = XEXP (dest, 0); | |
10045 | dest_uid = INSN_UID (dest); | |
9d98a694 | 10046 | return INSN_ADDRESSES (dest_uid); |
1245df60 | 10047 | } |
a55e9d2b | 10048 | \f |
5e7a8ee0 | 10049 | /* Return nonzero if REG is not used after INSN. |
a55e9d2b | 10050 | We assume REG is a reload reg, and therefore does |
8b760293 | 10051 | not live past labels. It may live past calls or jumps though. */ |
aaf701c5 | 10052 | bool |
b32d5189 | 10053 | reg_unused_after (rtx reg, rtx_insn *insn) |
a55e9d2b | 10054 | { |
8783b15e | 10055 | enum rtx_code code; |
a55e9d2b RK |
10056 | rtx set; |
10057 | ||
10058 | /* If the reg is set by this instruction, then it is safe for our | |
10059 | case. Disregard the case where this is a store to memory, since | |
10060 | we are checking a register used in the store address. */ | |
10061 | set = single_set (insn); | |
f3536097 | 10062 | if (set && !MEM_P (SET_DEST (set)) |
a55e9d2b | 10063 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) |
aaf701c5 | 10064 | return true; |
a55e9d2b | 10065 | |
318881c0 | 10066 | while ((insn = NEXT_INSN (insn))) |
a55e9d2b | 10067 | { |
ec8e098d PB |
10068 | rtx set; |
10069 | if (!INSN_P (insn)) | |
10070 | continue; | |
10071 | ||
a55e9d2b | 10072 | code = GET_CODE (insn); |
8783b15e | 10073 | |
c8f6f18d RK |
10074 | #if 0 |
10075 | /* If this is a label that existed before reload, then the register | |
2eff0b9d | 10076 | is dead here. However, if this is a label added by reorg, then |
c8f6f18d RK |
10077 | the register may still be live here. We can't tell the difference, |
10078 | so we just ignore labels completely. */ | |
8783b15e | 10079 | if (code == CODE_LABEL) |
a55e9d2b | 10080 | return 1; |
c8f6f18d RK |
10081 | /* else */ |
10082 | #endif | |
a55e9d2b | 10083 | |
8b760293 | 10084 | if (code == JUMP_INSN) |
aaf701c5 | 10085 | return false; |
8b760293 | 10086 | |
8783b15e RK |
10087 | /* If this is a sequence, we must handle them all at once. |
10088 | We could have for instance a call that sets the target register, | |
e03f5d43 | 10089 | and an insn in a delay slot that uses the register. In this case, |
8783b15e | 10090 | we must return 0. */ |
8b760293 | 10091 | else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) |
a55e9d2b | 10092 | { |
e8a54173 | 10093 | rtx_sequence *seq = as_a <rtx_sequence *> (PATTERN (insn)); |
8783b15e RK |
10094 | int i; |
10095 | int retval = 0; | |
10096 | ||
e8a54173 | 10097 | for (i = 0; i < seq->len (); i++) |
8783b15e | 10098 | { |
e8a54173 | 10099 | rtx_insn *this_insn = seq->insn (i); |
8783b15e RK |
10100 | rtx set = single_set (this_insn); |
10101 | ||
f3536097 | 10102 | if (CALL_P (this_insn)) |
8783b15e | 10103 | code = CALL_INSN; |
f3536097 | 10104 | else if (JUMP_P (this_insn)) |
38f35781 JW |
10105 | { |
10106 | if (INSN_ANNULLED_BRANCH_P (this_insn)) | |
aaf701c5 | 10107 | return false; |
38f35781 JW |
10108 | code = JUMP_INSN; |
10109 | } | |
a55e9d2b | 10110 | |
8783b15e | 10111 | if (set && reg_overlap_mentioned_p (reg, SET_SRC (set))) |
aaf701c5 | 10112 | return false; |
8783b15e RK |
10113 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) |
10114 | { | |
f3536097 | 10115 | if (!MEM_P (SET_DEST (set))) |
aaf701c5 | 10116 | retval = true; |
8783b15e | 10117 | else |
aaf701c5 | 10118 | return false; |
8783b15e | 10119 | } |
23d0939b | 10120 | if (set == NULL_RTX |
8783b15e | 10121 | && reg_overlap_mentioned_p (reg, PATTERN (this_insn))) |
aaf701c5 | 10122 | return false; |
8783b15e RK |
10123 | } |
10124 | if (retval == 1) | |
aaf701c5 | 10125 | return true; |
38f35781 | 10126 | else if (code == JUMP_INSN) |
aaf701c5 | 10127 | return false; |
8783b15e | 10128 | } |
a55e9d2b | 10129 | |
ec8e098d PB |
10130 | set = single_set (insn); |
10131 | if (set && reg_overlap_mentioned_p (reg, SET_SRC (set))) | |
aaf701c5 | 10132 | return false; |
ec8e098d | 10133 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) |
f3536097 | 10134 | return !MEM_P (SET_DEST (set)); |
ec8e098d | 10135 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) |
aaf701c5 | 10136 | return false; |
8783b15e | 10137 | |
62164eb4 | 10138 | if (code == CALL_INSN && call_really_used_regs[REGNO (reg)]) |
aaf701c5 | 10139 | return true; |
a55e9d2b | 10140 | } |
aaf701c5 | 10141 | return true; |
a55e9d2b | 10142 | } |
225e4f43 | 10143 | \f |
225e4f43 | 10144 | |
f031c344 OE |
10145 | static GTY(()) rtx t_reg_rtx; |
10146 | rtx | |
10147 | get_t_reg_rtx (void) | |
10148 | { | |
10149 | if (! t_reg_rtx) | |
10150 | t_reg_rtx = gen_rtx_REG (SImode, T_REG); | |
10151 | return t_reg_rtx; | |
10152 | } | |
10153 | ||
24c2fde2 RH |
10154 | static GTY(()) tree fpscr_values; |
10155 | ||
10156 | static void | |
10157 | emit_fpu_switch (rtx scratch, int index) | |
10158 | { | |
0caee3ca | 10159 | rtx src; |
24c2fde2 RH |
10160 | |
10161 | if (fpscr_values == NULL) | |
10162 | { | |
10163 | tree t; | |
10164 | ||
10165 | t = build_index_type (integer_one_node); | |
10166 | t = build_array_type (integer_type_node, t); | |
4c4bde29 AH |
10167 | t = build_decl (BUILTINS_LOCATION, |
10168 | VAR_DECL, get_identifier ("__fpscr_values"), t); | |
24c2fde2 RH |
10169 | DECL_ARTIFICIAL (t) = 1; |
10170 | DECL_IGNORED_P (t) = 1; | |
10171 | DECL_EXTERNAL (t) = 1; | |
10172 | TREE_STATIC (t) = 1; | |
a5f5c6be | 10173 | TREE_PUBLIC (t) = 1; |
24c2fde2 RH |
10174 | TREE_USED (t) = 1; |
10175 | ||
10176 | fpscr_values = t; | |
10177 | } | |
10178 | ||
10179 | src = DECL_RTL (fpscr_values); | |
b3a13419 | 10180 | if (!can_create_pseudo_p ()) |
24c2fde2 RH |
10181 | { |
10182 | emit_move_insn (scratch, XEXP (src, 0)); | |
10183 | if (index != 0) | |
10184 | emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4))); | |
fe3e478f | 10185 | src = adjust_automodify_address (src, SImode, scratch, index * 4); |
24c2fde2 RH |
10186 | } |
10187 | else | |
fe3e478f | 10188 | src = adjust_address (src, SImode, index * 4); |
24c2fde2 | 10189 | |
fe3e478f | 10190 | emit_insn (gen_lds_fpscr (src)); |
24c2fde2 | 10191 | } |
225e4f43 | 10192 | \f |
cf277499 | 10193 | static rtx get_free_reg (HARD_REG_SET); |
9f09b1f2 R |
10194 | |
10195 | /* This function returns a register to use to load the address to load | |
10196 | the fpscr from. Currently it always returns r1 or r7, but when we are | |
10197 | able to use pseudo registers after combine, or have a better mechanism | |
10198 | for choosing a register, it should be done here. */ | |
10199 | /* REGS_LIVE is the liveness information for the point for which we | |
10200 | need this allocation. In some bare-bones exit blocks, r1 is live at the | |
10201 | start. We can even have all of r0..r3 being live: | |
10202 | __complex__ long long f (double d) { if (d == 0) return 2; else return 3; } | |
10203 | INSN before which new insns are placed with will clobber the register | |
10204 | we return. If a basic block consists only of setting the return value | |
10205 | register to a pseudo and using that register, the return value is not | |
10206 | live before or after this block, yet we we'll insert our insns right in | |
10207 | the middle. */ | |
9f09b1f2 | 10208 | static rtx |
cf277499 | 10209 | get_free_reg (HARD_REG_SET regs_live) |
225e4f43 | 10210 | { |
9f09b1f2 R |
10211 | if (! TEST_HARD_REG_BIT (regs_live, 1)) |
10212 | return gen_rtx_REG (Pmode, 1); | |
225e4f43 | 10213 | |
42db504c | 10214 | /* Hard reg 1 is live; since this is a small register classes target, |
9f09b1f2 | 10215 | there shouldn't be anything but a jump before the function end. */ |
f5b9e7c9 NS |
10216 | gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7)); |
10217 | return gen_rtx_REG (Pmode, 7); | |
9f09b1f2 | 10218 | } |
225e4f43 | 10219 | |
f676971a | 10220 | /* This function will set the fpscr from memory. |
9f09b1f2 R |
10221 | MODE is the mode we are setting it to. */ |
10222 | void | |
cf277499 | 10223 | fpscr_set_from_mem (int mode, HARD_REG_SET regs_live) |
9f09b1f2 | 10224 | { |
81f40b79 | 10225 | enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode; |
24c2fde2 | 10226 | enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE); |
5e77c6f9 | 10227 | rtx addr_reg; |
9f09b1f2 | 10228 | |
b3a13419 | 10229 | addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX; |
24c2fde2 | 10230 | emit_fpu_switch (addr_reg, fp_mode == norm_mode); |
225e4f43 | 10231 | } |
9342c0c4 R |
10232 | |
10233 | /* Is the given character a logical line separator for the assembler? */ | |
10234 | #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR | |
980d8882 | 10235 | #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';') |
9342c0c4 R |
10236 | #endif |
10237 | ||
83d88a6d | 10238 | static bool |
b32d5189 | 10239 | sequence_insn_p (rtx_insn *insn) |
83d88a6d | 10240 | { |
6cb7eb41 | 10241 | rtx_insn *prev, *next; |
83d88a6d OE |
10242 | |
10243 | prev = PREV_INSN (insn); | |
10244 | if (prev == NULL) | |
10245 | return false; | |
10246 | ||
10247 | next = NEXT_INSN (prev); | |
10248 | if (next == NULL) | |
10249 | return false; | |
10250 | ||
312f9b9d | 10251 | return INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE; |
83d88a6d OE |
10252 | } |
10253 | ||
9342c0c4 | 10254 | int |
6cb7eb41 | 10255 | sh_insn_length_adjustment (rtx_insn *insn) |
9342c0c4 R |
10256 | { |
10257 | /* Instructions with unfilled delay slots take up an extra two bytes for | |
10258 | the nop in the delay slot. */ | |
f3536097 | 10259 | if (((NONJUMP_INSN_P (insn) |
c1b92d09 R |
10260 | && GET_CODE (PATTERN (insn)) != USE |
10261 | && GET_CODE (PATTERN (insn)) != CLOBBER) | |
39718607 | 10262 | || CALL_P (insn) || JUMP_P (insn)) |
83d88a6d | 10263 | && ! sequence_insn_p (insn) |
9342c0c4 R |
10264 | && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES) |
10265 | return 2; | |
10266 | ||
f05911fb OE |
10267 | /* Increase the insn length of a cbranch without a delay slot insn to |
10268 | force a delay slot which will be stuffed with a nop. */ | |
10269 | if (TARGET_CBRANCH_FORCE_DELAY_SLOT && TARGET_SH2 | |
10270 | && JUMP_P (insn) && get_attr_type (insn) == TYPE_CBRANCH | |
83d88a6d | 10271 | && ! sequence_insn_p (insn)) |
3a8699c7 AO |
10272 | return 2; |
10273 | ||
9342c0c4 | 10274 | /* sh-dsp parallel processing insn take four bytes instead of two. */ |
f676971a | 10275 | |
f3536097 | 10276 | if (NONJUMP_INSN_P (insn)) |
9342c0c4 R |
10277 | { |
10278 | int sum = 0; | |
10279 | rtx body = PATTERN (insn); | |
0a2aaacc | 10280 | const char *templ; |
8ceaac3c | 10281 | char c; |
23d0939b | 10282 | bool maybe_label = true; |
9342c0c4 R |
10283 | |
10284 | if (GET_CODE (body) == ASM_INPUT) | |
0a2aaacc | 10285 | templ = XSTR (body, 0); |
9342c0c4 | 10286 | else if (asm_noperands (body) >= 0) |
0a2aaacc | 10287 | templ |
343d66ad | 10288 | = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL); |
9342c0c4 R |
10289 | else |
10290 | return 0; | |
10291 | do | |
10292 | { | |
10293 | int ppi_adjust = 0; | |
10294 | ||
10295 | do | |
0a2aaacc | 10296 | c = *templ++; |
9342c0c4 R |
10297 | while (c == ' ' || c == '\t'); |
10298 | /* all sh-dsp parallel-processing insns start with p. | |
10299 | The only non-ppi sh insn starting with p is pref. | |
10300 | The only ppi starting with pr is prnd. */ | |
0a2aaacc | 10301 | if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2)) |
9342c0c4 R |
10302 | ppi_adjust = 2; |
10303 | /* The repeat pseudo-insn expands two three insns, a total of | |
10304 | six bytes in size. */ | |
10305 | else if ((c == 'r' || c == 'R') | |
0a2aaacc | 10306 | && ! strncasecmp ("epeat", templ, 5)) |
9342c0c4 | 10307 | ppi_adjust = 4; |
980d8882 | 10308 | while (c && c != '\n' |
0a2aaacc | 10309 | && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ)) |
9342c0c4 R |
10310 | { |
10311 | /* If this is a label, it is obviously not a ppi insn. */ | |
10312 | if (c == ':' && maybe_label) | |
10313 | { | |
10314 | ppi_adjust = 0; | |
10315 | break; | |
10316 | } | |
10317 | else if (c == '\'' || c == '"') | |
23d0939b | 10318 | maybe_label = false; |
0a2aaacc | 10319 | c = *templ++; |
9342c0c4 R |
10320 | } |
10321 | sum += ppi_adjust; | |
10322 | maybe_label = c != ':'; | |
10323 | } | |
10324 | while (c); | |
10325 | return sum; | |
10326 | } | |
10327 | return 0; | |
10328 | } | |
1a66cd67 | 10329 | \f |
cdeed45a KK |
10330 | /* Return TRUE for a valid displacement for the REG+disp addressing |
10331 | with MODE. */ | |
cdeed45a | 10332 | bool |
ef4bddc2 | 10333 | sh_legitimate_index_p (machine_mode mode, rtx op, bool consider_sh2a, |
8c2a3f3b | 10334 | bool allow_zero) |
cdeed45a | 10335 | { |
9b9ad23f OE |
10336 | if (! CONST_INT_P (op)) |
10337 | return false; | |
cdeed45a | 10338 | |
9b9ad23f OE |
10339 | if (TARGET_SHMEDIA) |
10340 | { | |
10341 | int size; | |
cdeed45a | 10342 | |
9b9ad23f OE |
10343 | /* Check if this is the address of an unaligned load / store. */ |
10344 | if (mode == VOIDmode) | |
4111c296 | 10345 | return satisfies_constraint_I06 (op); |
cdeed45a | 10346 | |
9b9ad23f OE |
10347 | size = GET_MODE_SIZE (mode); |
10348 | return (!(INTVAL (op) & (size - 1)) | |
10349 | && INTVAL (op) >= -512 * size | |
10350 | && INTVAL (op) < 512 * size); | |
10351 | } | |
10352 | else | |
10353 | { | |
10354 | const HOST_WIDE_INT offset = INTVAL (op); | |
91f65b12 | 10355 | const int max_disp = sh_max_mov_insn_displacement (mode, consider_sh2a); |
8c2a3f3b | 10356 | const int align_mask = mov_insn_alignment_mask (mode, consider_sh2a); |
344332e8 | 10357 | |
9b9ad23f OE |
10358 | /* If the mode does not support any displacement always return false. |
10359 | Even though an index of '0' is actually always valid, it will cause | |
10360 | troubles when e.g. a DFmode move is split into two SFmode moves, | |
10361 | where one SFmode move will have index '0' and the other move will | |
10362 | have index '4'. */ | |
8c2a3f3b | 10363 | if (!allow_zero && max_disp < 1) |
9b9ad23f | 10364 | return false; |
cdeed45a | 10365 | |
9b9ad23f | 10366 | return offset >= 0 && offset <= max_disp && (offset & align_mask) == 0; |
cdeed45a | 10367 | } |
cdeed45a KK |
10368 | } |
10369 | ||
10370 | /* Recognize an RTL expression that is a valid memory address for | |
10371 | an instruction. | |
10372 | The MODE argument is the machine mode for the MEM expression | |
10373 | that wants to use this address. | |
10374 | Allow REG | |
10375 | REG+disp | |
10376 | REG+r0 | |
10377 | REG++ | |
fce1e5fb OE |
10378 | --REG |
10379 | GBR | |
10380 | GBR+disp */ | |
1bb99877 | 10381 | static bool |
ef4bddc2 | 10382 | sh_legitimate_address_p (machine_mode mode, rtx x, bool strict) |
cdeed45a | 10383 | { |
79a1fe43 OE |
10384 | if (! ALLOW_INDEXED_ADDRESS |
10385 | && GET_CODE (x) == PLUS && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1))) | |
10386 | return false; | |
10387 | ||
fce1e5fb OE |
10388 | if (REG_P (x) && REGNO (x) == GBR_REG) |
10389 | return true; | |
10390 | ||
cdeed45a KK |
10391 | if (MAYBE_BASE_REGISTER_RTX_P (x, strict)) |
10392 | return true; | |
10393 | else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC) | |
10394 | && ! TARGET_SHMEDIA | |
10395 | && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict)) | |
10396 | return true; | |
fe3e478f | 10397 | else if (GET_CODE (x) == PLUS) |
cdeed45a KK |
10398 | { |
10399 | rtx xop0 = XEXP (x, 0); | |
10400 | rtx xop1 = XEXP (x, 1); | |
10401 | ||
fce1e5fb OE |
10402 | if (REG_P (xop0) && REGNO (xop0) == GBR_REG) |
10403 | return gbr_displacement (xop1, mode); | |
10404 | ||
cdeed45a KK |
10405 | if (GET_MODE_SIZE (mode) <= 8 |
10406 | && MAYBE_BASE_REGISTER_RTX_P (xop0, strict) | |
8c2a3f3b | 10407 | && sh_legitimate_index_p (mode, xop1, TARGET_SH2A, false)) |
cdeed45a KK |
10408 | return true; |
10409 | ||
10410 | if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode | |
10411 | || ((xop0 == stack_pointer_rtx | |
10412 | || xop0 == hard_frame_pointer_rtx) | |
10413 | && REG_P (xop1) && REGNO (xop1) == R0_REG) | |
10414 | || ((xop1 == stack_pointer_rtx | |
10415 | || xop1 == hard_frame_pointer_rtx) | |
10416 | && REG_P (xop0) && REGNO (xop0) == R0_REG)) | |
10417 | && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4) | |
10418 | || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8) | |
10419 | || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) | |
10420 | && TARGET_FMOVD && mode == DFmode))) | |
10421 | { | |
10422 | if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict) | |
10423 | && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict)) | |
10424 | return true; | |
10425 | if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict) | |
10426 | && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)) | |
10427 | return true; | |
10428 | } | |
10429 | } | |
10430 | ||
10431 | return false; | |
10432 | } | |
10433 | \f | |
55eec660 AO |
10434 | /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol |
10435 | isn't protected by a PIC unspec. */ | |
aaf701c5 | 10436 | bool |
cf277499 | 10437 | nonpic_symbol_mentioned_p (rtx x) |
1a66cd67 | 10438 | { |
aaf701c5 OE |
10439 | const char *fmt; |
10440 | int i; | |
1a66cd67 | 10441 | |
fa5322fa AO |
10442 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF |
10443 | || GET_CODE (x) == PC) | |
aaf701c5 | 10444 | return true; |
1a66cd67 | 10445 | |
fa5322fa AO |
10446 | /* We don't want to look into the possible MEM location of a |
10447 | CONST_DOUBLE, since we're not going to use it, in general. */ | |
10448 | if (GET_CODE (x) == CONST_DOUBLE) | |
aaf701c5 | 10449 | return false; |
fa5322fa | 10450 | |
1a66cd67 | 10451 | if (GET_CODE (x) == UNSPEC |
4773afa4 AO |
10452 | && (XINT (x, 1) == UNSPEC_PIC |
10453 | || XINT (x, 1) == UNSPEC_GOT | |
10454 | || XINT (x, 1) == UNSPEC_GOTOFF | |
fa5322fa | 10455 | || XINT (x, 1) == UNSPEC_GOTPLT |
463f02cd KK |
10456 | || XINT (x, 1) == UNSPEC_GOTTPOFF |
10457 | || XINT (x, 1) == UNSPEC_DTPOFF | |
58f451f0 | 10458 | || XINT (x, 1) == UNSPEC_TPOFF |
dc3ba671 RS |
10459 | || XINT (x, 1) == UNSPEC_PLT |
10460 | || XINT (x, 1) == UNSPEC_SYMOFF | |
10461 | || XINT (x, 1) == UNSPEC_PCREL_SYMOFF)) | |
aaf701c5 | 10462 | return false; |
1a66cd67 AO |
10463 | |
10464 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
10465 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
10466 | { | |
10467 | if (fmt[i] == 'E') | |
10468 | { | |
aaf701c5 | 10469 | int j; |
1a66cd67 AO |
10470 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
10471 | if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j))) | |
aaf701c5 | 10472 | return true; |
1a66cd67 AO |
10473 | } |
10474 | else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i))) | |
aaf701c5 | 10475 | return true; |
1a66cd67 AO |
10476 | } |
10477 | ||
aaf701c5 | 10478 | return false; |
1a66cd67 AO |
10479 | } |
10480 | ||
10481 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or | |
6f317ef3 | 10482 | @GOTOFF in `reg'. */ |
1a66cd67 | 10483 | rtx |
ef4bddc2 | 10484 | legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, |
cf277499 | 10485 | rtx reg) |
1a66cd67 | 10486 | { |
81f40b79 | 10487 | if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE) |
463f02cd KK |
10488 | return orig; |
10489 | ||
1a66cd67 | 10490 | if (GET_CODE (orig) == LABEL_REF |
675ff4c7 | 10491 | || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig))) |
1a66cd67 | 10492 | { |
23d0939b | 10493 | if (reg == NULL_RTX) |
1a66cd67 AO |
10494 | reg = gen_reg_rtx (Pmode); |
10495 | ||
10496 | emit_insn (gen_symGOTOFF2reg (reg, orig)); | |
10497 | return reg; | |
10498 | } | |
10499 | else if (GET_CODE (orig) == SYMBOL_REF) | |
10500 | { | |
23d0939b | 10501 | if (reg == NULL_RTX) |
1a66cd67 AO |
10502 | reg = gen_reg_rtx (Pmode); |
10503 | ||
10504 | emit_insn (gen_symGOT2reg (reg, orig)); | |
10505 | return reg; | |
10506 | } | |
10507 | return orig; | |
10508 | } | |
b91455de | 10509 | |
8c6d71c0 OE |
10510 | /* Given a (logical) mode size and an offset in bytes, try to find a the |
10511 | appropriate displacement value for a mov insn. On SH the displacements | |
10512 | are limited to max. 60 bytes for SImode, max. 30 bytes in HImode and max. | |
10513 | 15 bytes in QImode. To compensate this we create a new base address by | |
10514 | adding an adjustment value to it. | |
10515 | ||
10516 | If the originally requested offset is greater than 127 we prefer using | |
10517 | values 124..127 over 128..131 to increase opportunities to use the | |
10518 | add #imm, Rn insn. | |
10519 | ||
10520 | In some cases it is possible that a requested offset might seem unaligned | |
10521 | or inappropriate for the mode size, like offset = 2 and mode size = 4. | |
10522 | This is compensated by adjusting the base address so that the effective | |
10523 | address of the displacement move insn will be aligned. | |
10524 | ||
10525 | This is not the best possible way of rebasing the base address, as it | |
10526 | does not look at other present displacement addressings around it. | |
10527 | In some cases this can create more base address adjustments than would | |
10528 | actually be necessary. */ | |
8c6d71c0 OE |
10529 | struct disp_adjust |
10530 | { | |
10531 | rtx offset_adjust; | |
10532 | rtx mov_disp; | |
8c6d71c0 OE |
10533 | }; |
10534 | ||
10535 | static struct disp_adjust | |
ef4bddc2 | 10536 | sh_find_mov_disp_adjust (machine_mode mode, HOST_WIDE_INT offset) |
8c6d71c0 | 10537 | { |
9b9ad23f | 10538 | struct disp_adjust res = { NULL_RTX, NULL_RTX }; |
8c6d71c0 | 10539 | |
9b9ad23f OE |
10540 | /* Do not try to use SH2A's large displacements here, because this would |
10541 | effectively disable the small displacement insns. */ | |
10542 | const int mode_sz = GET_MODE_SIZE (mode); | |
10543 | const int mov_insn_sz = mov_insn_size (mode, false); | |
91f65b12 | 10544 | const int max_disp = sh_max_mov_insn_displacement (mode, false); |
9b9ad23f OE |
10545 | const int max_disp_next = max_disp + mov_insn_sz; |
10546 | HOST_WIDE_INT align_modifier = offset > 127 ? mov_insn_sz : 0; | |
8c6d71c0 | 10547 | HOST_WIDE_INT offset_adjust; |
506d7b68 | 10548 | |
8c6d71c0 | 10549 | /* In some cases this actually does happen and we must check for it. */ |
9b9ad23f | 10550 | if (mode_sz < 1 || mode_sz > 8 || max_disp < 1) |
8c6d71c0 OE |
10551 | return res; |
10552 | ||
8c6d71c0 OE |
10553 | /* Keeps the previous behavior for QImode displacement addressing. |
10554 | This just decides how the offset is re-based. Removing this special | |
10555 | case will result in slightly bigger code on average, but it's not that | |
10556 | bad actually. */ | |
9b9ad23f | 10557 | if (mov_insn_sz == 1) |
8c6d71c0 OE |
10558 | align_modifier = 0; |
10559 | ||
8c6d71c0 OE |
10560 | offset_adjust = ((offset + align_modifier) & ~max_disp) - align_modifier; |
10561 | ||
9b9ad23f | 10562 | if (mode_sz + offset - offset_adjust <= max_disp_next) |
8c6d71c0 OE |
10563 | { |
10564 | res.offset_adjust = GEN_INT (offset_adjust); | |
10565 | res.mov_disp = GEN_INT (offset - offset_adjust); | |
10566 | } | |
10567 | ||
10568 | return res; | |
10569 | } | |
10570 | ||
10571 | /* Try to modify an illegitimate address and make it legitimate. | |
10572 | If we find one, return the new, valid address. | |
10573 | Otherwise, return the original address. */ | |
506d7b68 | 10574 | static rtx |
ef4bddc2 | 10575 | sh_legitimize_address (rtx x, rtx oldx, machine_mode mode) |
506d7b68 PB |
10576 | { |
10577 | if (flag_pic) | |
10578 | x = legitimize_pic_address (oldx, mode, NULL_RTX); | |
10579 | ||
8c6d71c0 OE |
10580 | if (TARGET_SHMEDIA) |
10581 | return x; | |
506d7b68 | 10582 | |
8c6d71c0 OE |
10583 | if (((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode) |
10584 | || (TARGET_SH2E && mode == SFmode)) | |
10585 | return x; | |
506d7b68 | 10586 | |
8c6d71c0 OE |
10587 | if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)) |
10588 | && BASE_REGISTER_RTX_P (XEXP (x, 0))) | |
344332e8 | 10589 | { |
9b9ad23f | 10590 | struct disp_adjust adj = sh_find_mov_disp_adjust (mode, |
8c6d71c0 OE |
10591 | INTVAL (XEXP (x, 1))); |
10592 | ||
10593 | if (adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX) | |
344332e8 OE |
10594 | { |
10595 | rtx sum = expand_binop (Pmode, add_optab, XEXP (x, 0), | |
8c6d71c0 OE |
10596 | adj.offset_adjust, NULL_RTX, 0, |
10597 | OPTAB_LIB_WIDEN); | |
10598 | return gen_rtx_PLUS (Pmode, sum, adj.mov_disp); | |
344332e8 OE |
10599 | } |
10600 | } | |
506d7b68 PB |
10601 | return x; |
10602 | } | |
10603 | ||
8c6d71c0 | 10604 | /* Attempt to replace *p, which is an address that needs reloading, with |
6f50eb9c KK |
10605 | a valid memory address for an operand of mode MODE. |
10606 | Like for sh_legitimize_address, for the SH we try to get a normal form | |
10607 | of the address. That will allow inheritance of the address reloads. */ | |
6f50eb9c | 10608 | bool |
ef4bddc2 | 10609 | sh_legitimize_reload_address (rtx *p, machine_mode mode, int opnum, |
6f50eb9c KK |
10610 | int itype) |
10611 | { | |
10612 | enum reload_type type = (enum reload_type) itype; | |
8c6d71c0 | 10613 | const int mode_sz = GET_MODE_SIZE (mode); |
6f50eb9c | 10614 | |
106a52b7 KK |
10615 | if (sh_lra_p ()) |
10616 | return false; | |
10617 | ||
79a1fe43 OE |
10618 | if (! ALLOW_INDEXED_ADDRESS |
10619 | && GET_CODE (*p) == PLUS | |
10620 | && REG_P (XEXP (*p, 0)) && REG_P (XEXP (*p, 1))) | |
10621 | { | |
10622 | *p = copy_rtx (*p); | |
10623 | push_reload (*p, NULL_RTX, p, NULL, | |
10624 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); | |
10625 | return true; | |
10626 | } | |
10627 | ||
10628 | if (! ALLOW_INDEXED_ADDRESS | |
10629 | && GET_CODE (*p) == PLUS | |
10630 | && GET_CODE (XEXP (*p, 0)) == PLUS) | |
10631 | { | |
10632 | rtx sum = gen_rtx_PLUS (Pmode, XEXP (XEXP (*p, 0), 0), | |
10633 | XEXP (XEXP (*p, 0), 1)); | |
10634 | *p = gen_rtx_PLUS (Pmode, sum, XEXP (*p, 1)); | |
10635 | push_reload (sum, NULL_RTX, &XEXP (*p, 0), NULL, | |
10636 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); | |
10637 | return true; | |
10638 | } | |
10639 | ||
8c6d71c0 OE |
10640 | if (TARGET_SHMEDIA) |
10641 | return false; | |
10642 | ||
10643 | if (GET_CODE (*p) == PLUS && CONST_INT_P (XEXP (*p, 1)) | |
7140f0f9 | 10644 | && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p, 0), true) |
6f50eb9c KK |
10645 | && (ALLOW_INDEXED_ADDRESS |
10646 | || XEXP (*p, 0) == stack_pointer_rtx | |
10647 | || XEXP (*p, 0) == hard_frame_pointer_rtx)) | |
10648 | { | |
8c6d71c0 | 10649 | const HOST_WIDE_INT offset = INTVAL (XEXP (*p, 1)); |
9b9ad23f | 10650 | struct disp_adjust adj = sh_find_mov_disp_adjust (mode, offset); |
6f50eb9c KK |
10651 | |
10652 | if (TARGET_SH2A && mode == DFmode && (offset & 0x7)) | |
10653 | { | |
10654 | push_reload (*p, NULL_RTX, p, NULL, | |
10655 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); | |
8c6d71c0 | 10656 | return true; |
6f50eb9c | 10657 | } |
8c6d71c0 | 10658 | |
6f50eb9c KK |
10659 | if (TARGET_SH2E && mode == SFmode) |
10660 | { | |
10661 | *p = copy_rtx (*p); | |
10662 | push_reload (*p, NULL_RTX, p, NULL, | |
10663 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); | |
8c6d71c0 | 10664 | return true; |
6f50eb9c | 10665 | } |
8c6d71c0 OE |
10666 | |
10667 | /* FIXME: Do not allow to legitimize QImode and HImode displacement | |
10668 | moves because then reload has a problem figuring the constraint | |
10669 | that the move insn target/source reg must be R0. | |
10670 | Or maybe some handling is wrong in sh_secondary_reload for this | |
10671 | to work properly? */ | |
10672 | if ((mode_sz == 4 || mode_sz == 8) | |
10673 | && ! (TARGET_SH4 && mode == DFmode) | |
10674 | && adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX) | |
10675 | { | |
10676 | rtx sum = gen_rtx_PLUS (Pmode, XEXP (*p, 0), adj.offset_adjust); | |
10677 | *p = gen_rtx_PLUS (Pmode, sum, adj.mov_disp); | |
6f50eb9c KK |
10678 | push_reload (sum, NULL_RTX, &XEXP (*p, 0), NULL, |
10679 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); | |
8c6d71c0 | 10680 | return true; |
6f50eb9c KK |
10681 | } |
10682 | } | |
8c6d71c0 | 10683 | |
6f50eb9c | 10684 | /* We must re-recognize what we created before. */ |
8c6d71c0 OE |
10685 | if (GET_CODE (*p) == PLUS |
10686 | && (mode_sz == 4 || mode_sz == 8) | |
10687 | && GET_CODE (XEXP (*p, 0)) == PLUS | |
10688 | && CONST_INT_P (XEXP (XEXP (*p, 0), 1)) | |
10689 | && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p, 0), 0), true) | |
10690 | && CONST_INT_P (XEXP (*p, 1)) | |
10691 | && ! (TARGET_SH2E && mode == SFmode)) | |
6f50eb9c KK |
10692 | { |
10693 | /* Because this address is so complex, we know it must have | |
10694 | been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, | |
10695 | it is already unshared, and needs no further unsharing. */ | |
10696 | push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL, | |
10697 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); | |
8c6d71c0 | 10698 | return true; |
6f50eb9c KK |
10699 | } |
10700 | ||
10701 | return false; | |
6f50eb9c KK |
10702 | } |
10703 | ||
90833f7f KK |
10704 | /* In the name of slightly smaller debug output, and to cater to |
10705 | general assembler lossage, recognize various UNSPEC sequences | |
10706 | and turn them back into a direct symbol reference. */ | |
90833f7f KK |
10707 | static rtx |
10708 | sh_delegitimize_address (rtx orig_x) | |
10709 | { | |
10710 | rtx x, y; | |
10711 | ||
10712 | orig_x = delegitimize_mem_from_attrs (orig_x); | |
10713 | ||
10714 | x = orig_x; | |
10715 | if (MEM_P (x)) | |
10716 | x = XEXP (x, 0); | |
10717 | if (GET_CODE (x) == CONST) | |
10718 | { | |
10719 | y = XEXP (x, 0); | |
10720 | if (GET_CODE (y) == UNSPEC) | |
10721 | { | |
10722 | if (XINT (y, 1) == UNSPEC_GOT | |
2efd0aa6 KK |
10723 | || XINT (y, 1) == UNSPEC_GOTOFF |
10724 | || XINT (y, 1) == UNSPEC_SYMOFF) | |
90833f7f | 10725 | return XVECEXP (y, 0, 0); |
2efd0aa6 KK |
10726 | else if (XINT (y, 1) == UNSPEC_PCREL_SYMOFF) |
10727 | { | |
10728 | if (GET_CODE (XVECEXP (y, 0, 0)) == CONST) | |
10729 | { | |
10730 | rtx symplt = XEXP (XVECEXP (y, 0, 0), 0); | |
10731 | ||
10732 | if (GET_CODE (symplt) == UNSPEC | |
10733 | && XINT (symplt, 1) == UNSPEC_PLT) | |
10734 | return XVECEXP (symplt, 0, 0); | |
10735 | } | |
10736 | } | |
90833f7f KK |
10737 | else if (TARGET_SHMEDIA |
10738 | && (XINT (y, 1) == UNSPEC_EXTRACT_S16 | |
10739 | || XINT (y, 1) == UNSPEC_EXTRACT_U16)) | |
10740 | { | |
10741 | rtx offset = XVECEXP (y, 0, 1); | |
10742 | ||
10743 | x = gen_rtx_PLUS (Pmode, XVECEXP (y, 0, 0), offset); | |
10744 | if (MEM_P (orig_x)) | |
10745 | x = replace_equiv_address_nv (orig_x, x); | |
10746 | return x; | |
10747 | } | |
10748 | } | |
10749 | } | |
10750 | ||
10751 | return orig_x; | |
10752 | } | |
10753 | ||
b91455de KK |
10754 | /* Mark the use of a constant in the literal table. If the constant |
10755 | has multiple labels, make it unique. */ | |
c1b92d09 | 10756 | static rtx |
cf277499 | 10757 | mark_constant_pool_use (rtx x) |
b91455de | 10758 | { |
b32d5189 DM |
10759 | rtx_insn *insn, *lab; |
10760 | rtx pattern; | |
b91455de | 10761 | |
23d0939b | 10762 | if (x == NULL_RTX) |
b91455de KK |
10763 | return x; |
10764 | ||
10765 | switch (GET_CODE (x)) | |
10766 | { | |
10767 | case LABEL_REF: | |
10768 | x = XEXP (x, 0); | |
10769 | case CODE_LABEL: | |
10770 | break; | |
10771 | default: | |
10772 | return x; | |
10773 | } | |
10774 | ||
10775 | /* Get the first label in the list of labels for the same constant | |
10776 | and delete another labels in the list. */ | |
b32d5189 DM |
10777 | lab = as_a <rtx_insn *> (x); |
10778 | for (insn = PREV_INSN (lab); insn; insn = PREV_INSN (insn)) | |
b91455de | 10779 | { |
f3536097 | 10780 | if (!LABEL_P (insn) |
b91455de KK |
10781 | || LABEL_REFS (insn) != NEXT_INSN (insn)) |
10782 | break; | |
10783 | lab = insn; | |
10784 | } | |
10785 | ||
b32d5189 | 10786 | for (rtx insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn)) |
4654c0cf | 10787 | as_a<rtx_insn *> (insn)->set_deleted (); |
b91455de KK |
10788 | |
10789 | /* Mark constants in a window. */ | |
b32d5189 | 10790 | for (insn = NEXT_INSN (as_a <rtx_insn *> (x)); insn; insn = NEXT_INSN (insn)) |
b91455de | 10791 | { |
f3536097 | 10792 | if (!NONJUMP_INSN_P (insn)) |
b91455de KK |
10793 | continue; |
10794 | ||
10795 | pattern = PATTERN (insn); | |
10796 | if (GET_CODE (pattern) != UNSPEC_VOLATILE) | |
10797 | continue; | |
10798 | ||
10799 | switch (XINT (pattern, 1)) | |
10800 | { | |
10801 | case UNSPECV_CONST2: | |
10802 | case UNSPECV_CONST4: | |
10803 | case UNSPECV_CONST8: | |
10804 | XVECEXP (pattern, 0, 1) = const1_rtx; | |
10805 | break; | |
10806 | case UNSPECV_WINDOW_END: | |
10807 | if (XVECEXP (pattern, 0, 0) == x) | |
10808 | return lab; | |
10809 | break; | |
10810 | case UNSPECV_CONST_END: | |
10811 | return lab; | |
10812 | default: | |
10813 | break; | |
10814 | } | |
10815 | } | |
10816 | ||
10817 | return lab; | |
10818 | } | |
6e7b03e1 AH |
10819 | \f |
10820 | /* Return true if it's possible to redirect BRANCH1 to the destination | |
10821 | of an unconditional jump BRANCH2. We only want to do this if the | |
10822 | resulting branch will have a short displacement. */ | |
cf6186e9 JR |
10823 | static bool |
10824 | sh_can_follow_jump (const rtx_insn *branch1, const rtx_insn *branch2) | |
6e7b03e1 | 10825 | { |
d808ecdd KK |
10826 | /* Don't follow if BRANCH2 is possible to be a jump crossing between |
10827 | hot and cold partitions. */ | |
10828 | if (TARGET_SH1 | |
10829 | && flag_reorder_blocks_and_partition | |
10830 | && simplejump_p (branch2) | |
10831 | && CROSSING_JUMP_P (branch2)) | |
10832 | return false; | |
10833 | ||
6e7b03e1 AH |
10834 | if (flag_expensive_optimizations && simplejump_p (branch2)) |
10835 | { | |
10836 | rtx dest = XEXP (SET_SRC (single_set (branch2)), 0); | |
6cb7eb41 | 10837 | rtx_insn *insn; |
6e7b03e1 | 10838 | int distance; |
f676971a EC |
10839 | |
10840 | for (distance = 0, insn = NEXT_INSN (branch1); | |
10841 | insn && distance < 256; | |
6e7b03e1 AH |
10842 | insn = PREV_INSN (insn)) |
10843 | { | |
f676971a | 10844 | if (insn == dest) |
aaf701c5 | 10845 | return true; |
6e7b03e1 AH |
10846 | else |
10847 | distance += get_attr_length (insn); | |
10848 | } | |
f676971a EC |
10849 | for (distance = 0, insn = NEXT_INSN (branch1); |
10850 | insn && distance < 256; | |
6e7b03e1 AH |
10851 | insn = NEXT_INSN (insn)) |
10852 | { | |
f676971a | 10853 | if (insn == dest) |
aaf701c5 | 10854 | return true; |
6e7b03e1 AH |
10855 | else |
10856 | distance += get_attr_length (insn); | |
10857 | } | |
10858 | } | |
aaf701c5 | 10859 | return false; |
6e7b03e1 AH |
10860 | } |
10861 | ||
5e7a8ee0 | 10862 | /* Return nonzero if register old_reg can be renamed to register new_reg. */ |
aaf701c5 | 10863 | bool |
cf277499 SB |
10864 | sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, |
10865 | unsigned int new_reg) | |
03b8ec29 | 10866 | { |
832a3292 KH |
10867 | /* Interrupt functions can only use registers that have already been |
10868 | saved by the prologue, even if they would normally be | |
10869 | call-clobbered. */ | |
6fb5fa3c | 10870 | if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg)) |
aaf701c5 | 10871 | return false; |
03b8ec29 | 10872 | |
aaf701c5 | 10873 | return true; |
03b8ec29 DD |
10874 | } |
10875 | ||
95c0af87 | 10876 | /* Function to update the integer COST |
c237e94a ZW |
10877 | based on the relationship between INSN that is dependent on |
10878 | DEP_INSN through the dependence LINK. The default is to make no | |
10879 | adjustment to COST. This can be used for example to specify to | |
10880 | the scheduler that an output- or anti-dependence does not incur | |
95c0af87 JR |
10881 | the same cost as a data-dependence. The return value should be |
10882 | the new value for COST. */ | |
c237e94a | 10883 | static int |
ac44248e DM |
10884 | sh_adjust_cost (rtx_insn *insn, rtx link ATTRIBUTE_UNUSED, |
10885 | rtx_insn *dep_insn, int cost) | |
c237e94a | 10886 | { |
c49439f1 | 10887 | rtx reg, use_pat; |
c237e94a | 10888 | |
2ad65b0e SC |
10889 | if (TARGET_SHMEDIA) |
10890 | { | |
10891 | /* On SHmedia, if the dependence is an anti-dependence or | |
24746a42 | 10892 | output-dependence, there is no cost. */ |
2ad65b0e | 10893 | if (REG_NOTE_KIND (link) != 0) |
73a4d10b R |
10894 | { |
10895 | /* However, dependencies between target register loads and | |
10896 | uses of the register in a subsequent block that are separated | |
10897 | by a conditional branch are not modelled - we have to do with | |
10898 | the anti-dependency between the target register load and the | |
10899 | conditional branch that ends the current block. */ | |
10900 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI | |
10901 | && GET_CODE (PATTERN (dep_insn)) == SET | |
10902 | && (get_attr_type (dep_insn) == TYPE_PT_MEDIA | |
10903 | || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA) | |
10904 | && get_attr_type (insn) == TYPE_CBRANCH_MEDIA) | |
10905 | { | |
10906 | int orig_cost = cost; | |
10907 | rtx note = find_reg_note (insn, REG_BR_PROB, 0); | |
e5af9ddd | 10908 | rtx target = ((!note || XINT (note, 0) * 2 < REG_BR_PROB_BASE) |
73a4d10b R |
10909 | ? insn : JUMP_LABEL (insn)); |
10910 | /* On the likely path, the branch costs 1, on the unlikely path, | |
10911 | it costs 3. */ | |
10912 | cost--; | |
10913 | do | |
10914 | target = next_active_insn (target); | |
10915 | while (target && ! flow_dependent_p (target, dep_insn) | |
10916 | && --cost > 0); | |
10917 | /* If two branches are executed in immediate succession, with the | |
10918 | first branch properly predicted, this causes a stall at the | |
10919 | second branch, hence we won't need the target for the | |
10920 | second branch for two cycles after the launch of the first | |
10921 | branch. */ | |
10922 | if (cost > orig_cost - 2) | |
10923 | cost = orig_cost - 2; | |
10924 | } | |
10925 | else | |
10926 | cost = 0; | |
10927 | } | |
2ad65b0e | 10928 | |
73a4d10b R |
10929 | else if (get_attr_is_mac_media (insn) |
10930 | && get_attr_is_mac_media (dep_insn)) | |
10931 | cost = 1; | |
10932 | ||
10933 | else if (! reload_completed | |
10934 | && GET_CODE (PATTERN (insn)) == SET | |
10935 | && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT | |
10936 | && GET_CODE (PATTERN (dep_insn)) == SET | |
10937 | && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode) | |
10938 | && cost < 4) | |
10939 | cost = 4; | |
10940 | /* Schedule the ptabs for a casesi_jump_media in preference to stuff | |
10941 | that is needed at the target. */ | |
10942 | else if (get_attr_type (insn) == TYPE_JUMP_MEDIA | |
10943 | && ! flow_dependent_p (insn, dep_insn)) | |
10944 | cost--; | |
2ad65b0e | 10945 | } |
c49439f1 | 10946 | else if (REG_NOTE_KIND (link) == 0) |
c237e94a | 10947 | { |
78d310c2 R |
10948 | enum attr_type type; |
10949 | rtx dep_set; | |
c49439f1 R |
10950 | |
10951 | if (recog_memoized (insn) < 0 | |
10952 | || recog_memoized (dep_insn) < 0) | |
95c0af87 | 10953 | return cost; |
c49439f1 | 10954 | |
78d310c2 | 10955 | dep_set = single_set (dep_insn); |
c49439f1 | 10956 | |
78d310c2 R |
10957 | /* The latency that we specify in the scheduling description refers |
10958 | to the actual output, not to an auto-increment register; for that, | |
10959 | the latency is one. */ | |
10960 | if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1) | |
10961 | { | |
10962 | rtx set = single_set (insn); | |
10963 | ||
10964 | if (set | |
10965 | && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set)) | |
10966 | && (!MEM_P (SET_DEST (set)) | |
10967 | || !reg_mentioned_p (SET_DEST (dep_set), | |
10968 | XEXP (SET_DEST (set), 0)))) | |
10969 | cost = 1; | |
10970 | } | |
c237e94a ZW |
10971 | /* The only input for a call that is timing-critical is the |
10972 | function's address. */ | |
f3536097 | 10973 | if (CALL_P (insn)) |
c49439f1 | 10974 | { |
da4fdf2d SB |
10975 | rtx call = get_call_rtx_from (insn); |
10976 | if (call | |
73a4d10b R |
10977 | /* sibcalli_thunk uses a symbol_ref in an unspec. */ |
10978 | && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC | |
10979 | || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))) | |
78d310c2 | 10980 | cost -= TARGET_SH4_300 ? 3 : 6; |
c49439f1 | 10981 | } |
c237e94a ZW |
10982 | /* Likewise, the most timing critical input for an sfuncs call |
10983 | is the function address. However, sfuncs typically start | |
10984 | using their arguments pretty quickly. | |
78d310c2 R |
10985 | Assume a four cycle delay for SH4 before they are needed. |
10986 | Cached ST40-300 calls are quicker, so assume only a one | |
10987 | cycle delay there. | |
10988 | ??? Maybe we should encode the delays till input registers | |
10989 | are needed by sfuncs into the sfunc call insn. */ | |
c49439f1 R |
10990 | /* All sfunc calls are parallels with at least four components. |
10991 | Exploit this to avoid unnecessary calls to sfunc_uses_reg. */ | |
10992 | else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
10993 | && XVECLEN (PATTERN (insn), 0) >= 4 | |
10994 | && (reg = sfunc_uses_reg (insn))) | |
10995 | { | |
10996 | if (! reg_set_p (reg, dep_insn)) | |
78d310c2 R |
10997 | cost -= TARGET_SH4_300 ? 1 : 4; |
10998 | } | |
10999 | if (TARGET_HARD_SH4 && !TARGET_SH4_300) | |
11000 | { | |
11001 | enum attr_type dep_type = get_attr_type (dep_insn); | |
11002 | ||
11003 | if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD) | |
11004 | cost--; | |
11005 | else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI) | |
11006 | && (type = get_attr_type (insn)) != TYPE_CALL | |
11007 | && type != TYPE_SFUNC) | |
11008 | cost--; | |
11009 | /* When the preceding instruction loads the shift amount of | |
11010 | the following SHAD/SHLD, the latency of the load is increased | |
11011 | by 1 cycle. */ | |
11012 | if (get_attr_type (insn) == TYPE_DYN_SHIFT | |
11013 | && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES | |
c6ac6e82 | 11014 | && reg_overlap_mentioned_p (SET_DEST (dep_set), |
78d310c2 R |
11015 | XEXP (SET_SRC (single_set (insn)), |
11016 | 1))) | |
11017 | cost++; | |
11018 | /* When an LS group instruction with a latency of less than | |
11019 | 3 cycles is followed by a double-precision floating-point | |
11020 | instruction, FIPR, or FTRV, the latency of the first | |
11021 | instruction is increased to 3 cycles. */ | |
11022 | else if (cost < 3 | |
11023 | && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP | |
11024 | && get_attr_dfp_comp (insn) == DFP_COMP_YES) | |
11025 | cost = 3; | |
11026 | /* The lsw register of a double-precision computation is ready one | |
11027 | cycle earlier. */ | |
11028 | else if (reload_completed | |
11029 | && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES | |
11030 | && (use_pat = single_set (insn)) | |
11031 | && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))), | |
11032 | SET_SRC (use_pat))) | |
11033 | cost -= 1; | |
11034 | ||
11035 | if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES | |
11036 | && get_attr_late_fp_use (insn) == LATE_FP_USE_YES) | |
11037 | cost -= 1; | |
11038 | } | |
11039 | else if (TARGET_SH4_300) | |
11040 | { | |
11041 | /* Stores need their input register two cycles later. */ | |
11042 | if (dep_set && cost >= 1 | |
11043 | && ((type = get_attr_type (insn)) == TYPE_STORE | |
11044 | || type == TYPE_PSTORE | |
11045 | || type == TYPE_FSTORE || type == TYPE_MAC_MEM)) | |
11046 | { | |
11047 | rtx set = single_set (insn); | |
11048 | ||
11049 | if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0)) | |
11050 | && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set))) | |
11051 | { | |
11052 | cost -= 2; | |
11053 | /* But don't reduce the cost below 1 if the address depends | |
11054 | on a side effect of dep_insn. */ | |
11055 | if (cost < 1 | |
11056 | && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn)) | |
11057 | cost = 1; | |
11058 | } | |
11059 | } | |
11060 | } | |
c49439f1 R |
11061 | } |
11062 | /* An anti-dependence penalty of two applies if the first insn is a double | |
11063 | precision fadd / fsub / fmul. */ | |
78d310c2 R |
11064 | else if (!TARGET_SH4_300 |
11065 | && REG_NOTE_KIND (link) == REG_DEP_ANTI | |
c49439f1 | 11066 | && recog_memoized (dep_insn) >= 0 |
78d310c2 R |
11067 | && (get_attr_type (dep_insn) == TYPE_DFP_ARITH |
11068 | || get_attr_type (dep_insn) == TYPE_DFP_MUL) | |
c49439f1 R |
11069 | /* A lot of alleged anti-flow dependences are fake, |
11070 | so check this one is real. */ | |
11071 | && flow_dependent_p (dep_insn, insn)) | |
c237e94a | 11072 | cost = 2; |
c49439f1 | 11073 | |
c237e94a ZW |
11074 | return cost; |
11075 | } | |
3007d592 | 11076 | |
c49439f1 R |
11077 | /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check |
11078 | if DEP_INSN is anti-flow dependent on INSN. */ | |
aaf701c5 | 11079 | static bool |
cf277499 | 11080 | flow_dependent_p (rtx insn, rtx dep_insn) |
c49439f1 R |
11081 | { |
11082 | rtx tmp = PATTERN (insn); | |
11083 | ||
11084 | note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp); | |
11085 | return tmp == NULL_RTX; | |
11086 | } | |
11087 | ||
11088 | /* A helper function for flow_dependent_p called through note_stores. */ | |
11089 | static void | |
7bc980e1 | 11090 | flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) |
c49439f1 R |
11091 | { |
11092 | rtx * pinsn = (rtx *) data; | |
11093 | ||
11094 | if (*pinsn && reg_referenced_p (x, *pinsn)) | |
11095 | *pinsn = NULL_RTX; | |
11096 | } | |
11097 | ||
b48f503c | 11098 | /* For use by sh_allocate_initial_value. Note that sh.md contains some |
3007d592 R |
11099 | 'special function' patterns (type sfunc) that clobber pr, but that |
11100 | do not look like function calls to leaf_function_p. Hence we must | |
11101 | do this extra check. */ | |
b48f503c | 11102 | static int |
cf277499 | 11103 | sh_pr_n_sets (void) |
3007d592 | 11104 | { |
6fb5fa3c | 11105 | return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG); |
3007d592 | 11106 | } |
fa5322fa | 11107 | |
b48f503c KK |
11108 | /* Return where to allocate pseudo for a given hard register initial |
11109 | value. */ | |
11110 | static rtx | |
11111 | sh_allocate_initial_value (rtx hard_reg) | |
11112 | { | |
11113 | rtx x; | |
11114 | ||
11115 | if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)) | |
11116 | { | |
416ff32e | 11117 | if (crtl->is_leaf |
b48f503c KK |
11118 | && ! sh_pr_n_sets () |
11119 | && ! (TARGET_SHCOMPACT | |
38173d38 | 11120 | && ((crtl->args.info.call_cookie |
b48f503c | 11121 | & ~ CALL_COOKIE_RET_TRAMP (1)) |
e3b5732b | 11122 | || crtl->saves_all_registers))) |
b48f503c KK |
11123 | x = hard_reg; |
11124 | else | |
57d38024 | 11125 | x = gen_frame_mem (Pmode, return_address_pointer_rtx); |
b48f503c KK |
11126 | } |
11127 | else | |
11128 | x = NULL_RTX; | |
11129 | ||
11130 | return x; | |
11131 | } | |
11132 | ||
c49439f1 R |
11133 | /* This function returns "2" to indicate dual issue for the SH4 |
11134 | processor. To be used by the DFA pipeline description. */ | |
fae15c93 | 11135 | static int |
832a3292 | 11136 | sh_issue_rate (void) |
fae15c93 | 11137 | { |
c49439f1 R |
11138 | if (TARGET_SUPERSCALAR) |
11139 | return 2; | |
11140 | else | |
11141 | return 1; | |
fae15c93 VM |
11142 | } |
11143 | ||
58565a33 SKG |
11144 | /* Functions for ready queue reordering for sched1. */ |
11145 | ||
11146 | /* Get weight for mode for a set x. */ | |
11147 | static short | |
ef4bddc2 | 11148 | find_set_regmode_weight (rtx x, machine_mode mode) |
58565a33 SKG |
11149 | { |
11150 | if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode)) | |
11151 | return 1; | |
11152 | if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode)) | |
11153 | { | |
f3536097 | 11154 | if (REG_P (SET_DEST (x))) |
58565a33 SKG |
11155 | { |
11156 | if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x))) | |
11157 | return 1; | |
11158 | else | |
11159 | return 0; | |
11160 | } | |
11161 | return 1; | |
11162 | } | |
11163 | return 0; | |
11164 | } | |
11165 | ||
11166 | /* Get regmode weight for insn. */ | |
11167 | static short | |
ef4bddc2 | 11168 | find_insn_regmode_weight (rtx insn, machine_mode mode) |
58565a33 SKG |
11169 | { |
11170 | short reg_weight = 0; | |
11171 | rtx x; | |
11172 | ||
11173 | /* Increment weight for each register born here. */ | |
11174 | x = PATTERN (insn); | |
11175 | reg_weight += find_set_regmode_weight (x, mode); | |
11176 | if (GET_CODE (x) == PARALLEL) | |
11177 | { | |
11178 | int j; | |
11179 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) | |
11180 | { | |
11181 | x = XVECEXP (PATTERN (insn), 0, j); | |
11182 | reg_weight += find_set_regmode_weight (x, mode); | |
11183 | } | |
11184 | } | |
11185 | /* Decrement weight for each register that dies here. */ | |
11186 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) | |
11187 | { | |
11188 | if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED) | |
11189 | { | |
11190 | rtx note = XEXP (x, 0); | |
f3536097 | 11191 | if (REG_P (note) && GET_MODE (note) == mode) |
58565a33 SKG |
11192 | reg_weight--; |
11193 | } | |
11194 | } | |
11195 | return reg_weight; | |
11196 | } | |
11197 | ||
11198 | /* Calculate regmode weights for all insns of a basic block. */ | |
11199 | static void | |
ef4bddc2 | 11200 | find_regmode_weight (basic_block b, machine_mode mode) |
58565a33 | 11201 | { |
52d251b5 | 11202 | rtx_insn *insn, *next_tail, *head, *tail; |
58565a33 | 11203 | |
c6d56443 | 11204 | get_ebb_head_tail (b, b, &head, &tail); |
58565a33 SKG |
11205 | next_tail = NEXT_INSN (tail); |
11206 | ||
11207 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
11208 | { | |
11209 | /* Handle register life information. */ | |
11210 | if (!INSN_P (insn)) | |
11211 | continue; | |
11212 | ||
11213 | if (mode == SFmode) | |
11214 | INSN_REGMODE_WEIGHT (insn, mode) = | |
6387ab2c OE |
11215 | find_insn_regmode_weight (insn, mode) |
11216 | + 2 * find_insn_regmode_weight (insn, DFmode); | |
58565a33 SKG |
11217 | else if (mode == SImode) |
11218 | INSN_REGMODE_WEIGHT (insn, mode) = | |
6387ab2c OE |
11219 | find_insn_regmode_weight (insn, mode) |
11220 | + 2 * find_insn_regmode_weight (insn, DImode); | |
58565a33 SKG |
11221 | } |
11222 | } | |
11223 | ||
11224 | /* Comparison function for ready queue sorting. */ | |
11225 | static int | |
508ea1c5 | 11226 | rank_for_reorder (const void *x, const void *y) |
58565a33 | 11227 | { |
ce1ce33a DM |
11228 | rtx_insn *tmp = *(rtx_insn * const *) y; |
11229 | rtx_insn *tmp2 = *(rtx_insn * const *) x; | |
58565a33 SKG |
11230 | |
11231 | /* The insn in a schedule group should be issued the first. */ | |
11232 | if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2)) | |
11233 | return SCHED_GROUP_P (tmp2) ? 1 : -1; | |
11234 | ||
f676971a | 11235 | /* If insns are equally good, sort by INSN_LUID (original insn order), This |
58565a33 SKG |
11236 | minimizes instruction movement, thus minimizing sched's effect on |
11237 | register pressure. */ | |
11238 | return INSN_LUID (tmp) - INSN_LUID (tmp2); | |
11239 | } | |
11240 | ||
11241 | /* Resort the array A in which only element at index N may be out of order. */ | |
11242 | static void | |
ce1ce33a | 11243 | swap_reorder (rtx_insn **a, int n) |
58565a33 | 11244 | { |
ce1ce33a | 11245 | rtx_insn *insn = a[n - 1]; |
58565a33 SKG |
11246 | int i = n - 2; |
11247 | ||
11248 | while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0) | |
11249 | { | |
11250 | a[i + 1] = a[i]; | |
11251 | i -= 1; | |
11252 | } | |
11253 | a[i + 1] = insn; | |
11254 | } | |
11255 | ||
e6b8b8c7 | 11256 | /* Sort the ready list by ascending priority. */ |
58565a33 | 11257 | static void |
ce1ce33a | 11258 | ready_reorder (rtx_insn **ready, int nready) |
58565a33 | 11259 | { |
e6b8b8c7 OE |
11260 | if (nready == 2) |
11261 | swap_reorder (ready, nready); | |
11262 | else if (nready > 2) | |
ce1ce33a | 11263 | qsort (ready, nready, sizeof (rtx_insn *), rank_for_reorder); |
58565a33 SKG |
11264 | } |
11265 | ||
6fb5fa3c DB |
11266 | /* Count life regions of r0 for a block. */ |
11267 | static int | |
11268 | find_r0_life_regions (basic_block b) | |
11269 | { | |
6cb7eb41 | 11270 | rtx_insn *end, *insn; |
6fb5fa3c DB |
11271 | rtx pset; |
11272 | rtx r0_reg; | |
11273 | int live; | |
11274 | int set; | |
11275 | int death = 0; | |
11276 | ||
89a95777 | 11277 | if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG)) |
6fb5fa3c DB |
11278 | { |
11279 | set = 1; | |
11280 | live = 1; | |
11281 | } | |
11282 | else | |
11283 | { | |
11284 | set = 0; | |
11285 | live = 0; | |
11286 | } | |
11287 | ||
11288 | insn = BB_HEAD (b); | |
11289 | end = BB_END (b); | |
11290 | r0_reg = gen_rtx_REG (SImode, R0_REG); | |
11291 | while (1) | |
11292 | { | |
11293 | if (INSN_P (insn)) | |
11294 | { | |
11295 | if (find_regno_note (insn, REG_DEAD, R0_REG)) | |
11296 | { | |
11297 | death++; | |
11298 | live = 0; | |
11299 | } | |
11300 | if (!live | |
11301 | && (pset = single_set (insn)) | |
11302 | && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset)) | |
11303 | && !find_regno_note (insn, REG_UNUSED, R0_REG)) | |
11304 | { | |
11305 | set++; | |
11306 | live = 1; | |
11307 | } | |
11308 | } | |
11309 | if (insn == end) | |
11310 | break; | |
11311 | insn = NEXT_INSN (insn); | |
11312 | } | |
11313 | return set - death; | |
11314 | } | |
11315 | ||
58565a33 SKG |
11316 | /* Calculate regmode weights for all insns of all basic block. */ |
11317 | static void | |
508ea1c5 KH |
11318 | sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED, |
11319 | int verbose ATTRIBUTE_UNUSED, | |
11320 | int old_max_uid) | |
58565a33 SKG |
11321 | { |
11322 | basic_block b; | |
11323 | ||
11324 | regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short)); | |
11325 | regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short)); | |
6fb5fa3c | 11326 | r0_life_regions = 0; |
58565a33 | 11327 | |
4f42035e | 11328 | FOR_EACH_BB_REVERSE_FN (b, cfun) |
58565a33 | 11329 | { |
c6d56443 KK |
11330 | find_regmode_weight (b, SImode); |
11331 | find_regmode_weight (b, SFmode); | |
6fb5fa3c DB |
11332 | if (!reload_completed) |
11333 | r0_life_regions += find_r0_life_regions (b); | |
58565a33 SKG |
11334 | } |
11335 | ||
11336 | CURR_REGMODE_PRESSURE (SImode) = 0; | |
11337 | CURR_REGMODE_PRESSURE (SFmode) = 0; | |
58565a33 SKG |
11338 | } |
11339 | ||
11340 | /* Cleanup. */ | |
11341 | static void | |
508ea1c5 KH |
11342 | sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED, |
11343 | int verbose ATTRIBUTE_UNUSED) | |
58565a33 SKG |
11344 | { |
11345 | if (regmode_weight[0]) | |
11346 | { | |
11347 | free (regmode_weight[0]); | |
11348 | regmode_weight[0] = NULL; | |
11349 | } | |
11350 | if (regmode_weight[1]) | |
11351 | { | |
11352 | free (regmode_weight[1]); | |
11353 | regmode_weight[1] = NULL; | |
11354 | } | |
11355 | } | |
11356 | ||
b0fbea13 KK |
11357 | /* The scalar modes supported differs from the default version in TImode |
11358 | for 32-bit SHMEDIA. */ | |
11359 | static bool | |
ef4bddc2 | 11360 | sh_scalar_mode_supported_p (machine_mode mode) |
b0fbea13 KK |
11361 | { |
11362 | if (TARGET_SHMEDIA32 && mode == TImode) | |
11363 | return false; | |
11364 | ||
11365 | return default_scalar_mode_supported_p (mode); | |
11366 | } | |
11367 | ||
58565a33 SKG |
11368 | /* Cache the can_issue_more so that we can return it from reorder2. Also, |
11369 | keep count of register pressures on SImode and SFmode. */ | |
11370 | static int | |
508ea1c5 KH |
11371 | sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED, |
11372 | int sched_verbose ATTRIBUTE_UNUSED, | |
ac44248e | 11373 | rtx_insn *insn, |
508ea1c5 | 11374 | int can_issue_more) |
58565a33 SKG |
11375 | { |
11376 | if (GET_CODE (PATTERN (insn)) != USE | |
11377 | && GET_CODE (PATTERN (insn)) != CLOBBER) | |
11378 | cached_can_issue_more = can_issue_more - 1; | |
11379 | else | |
11380 | cached_can_issue_more = can_issue_more; | |
11381 | ||
11382 | if (reload_completed) | |
11383 | return cached_can_issue_more; | |
11384 | ||
11385 | CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode); | |
11386 | CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode); | |
11387 | ||
11388 | return cached_can_issue_more; | |
11389 | } | |
11390 | ||
11391 | static void | |
508ea1c5 KH |
11392 | sh_md_init (FILE *dump ATTRIBUTE_UNUSED, |
11393 | int verbose ATTRIBUTE_UNUSED, | |
11394 | int veclen ATTRIBUTE_UNUSED) | |
58565a33 SKG |
11395 | { |
11396 | CURR_REGMODE_PRESSURE (SImode) = 0; | |
11397 | CURR_REGMODE_PRESSURE (SFmode) = 0; | |
11398 | } | |
11399 | ||
11400 | /* Some magic numbers. */ | |
11401 | /* Pressure on register r0 can lead to spill failures. so avoid sched1 for | |
11402 | functions that already have high pressure on r0. */ | |
11403 | #define R0_MAX_LIFE_REGIONS 2 | |
4ee31f1e | 11404 | /* Register Pressure thresholds for SImode and SFmode registers. */ |
58565a33 SKG |
11405 | #define SIMODE_MAX_WEIGHT 5 |
11406 | #define SFMODE_MAX_WEIGHT 10 | |
11407 | ||
11408 | /* Return true if the pressure is high for MODE. */ | |
aaf701c5 | 11409 | static bool |
ef4bddc2 | 11410 | high_pressure (machine_mode mode) |
58565a33 SKG |
11411 | { |
11412 | /* Pressure on register r0 can lead to spill failures. so avoid sched1 for | |
11413 | functions that already have high pressure on r0. */ | |
6fb5fa3c | 11414 | if (r0_life_regions >= R0_MAX_LIFE_REGIONS) |
aaf701c5 | 11415 | return true; |
58565a33 SKG |
11416 | |
11417 | if (mode == SFmode) | |
11418 | return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT); | |
11419 | else | |
11420 | return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT); | |
11421 | } | |
11422 | ||
11423 | /* Reorder ready queue if register pressure is high. */ | |
11424 | static int | |
508ea1c5 KH |
11425 | sh_reorder (FILE *dump ATTRIBUTE_UNUSED, |
11426 | int sched_verbose ATTRIBUTE_UNUSED, | |
ce1ce33a | 11427 | rtx_insn **ready, |
508ea1c5 KH |
11428 | int *n_readyp, |
11429 | int clock_var ATTRIBUTE_UNUSED) | |
58565a33 SKG |
11430 | { |
11431 | if (reload_completed) | |
11432 | return sh_issue_rate (); | |
11433 | ||
11434 | if (high_pressure (SFmode) || high_pressure (SImode)) | |
11435 | { | |
11436 | ready_reorder (ready, *n_readyp); | |
11437 | } | |
11438 | ||
11439 | return sh_issue_rate (); | |
11440 | } | |
11441 | ||
11442 | /* Skip cycles if the current register pressure is high. */ | |
f676971a | 11443 | static int |
508ea1c5 KH |
11444 | sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED, |
11445 | int sched_verbose ATTRIBUTE_UNUSED, | |
ce1ce33a | 11446 | rtx_insn **ready ATTRIBUTE_UNUSED, |
508ea1c5 KH |
11447 | int *n_readyp ATTRIBUTE_UNUSED, |
11448 | int clock_var ATTRIBUTE_UNUSED) | |
58565a33 SKG |
11449 | { |
11450 | if (reload_completed) | |
11451 | return cached_can_issue_more; | |
11452 | ||
f676971a | 11453 | if (high_pressure(SFmode) || high_pressure (SImode)) |
58565a33 SKG |
11454 | skip_cycles = 1; |
11455 | ||
11456 | return cached_can_issue_more; | |
11457 | } | |
11458 | ||
11459 | /* Skip cycles without sorting the ready queue. This will move insn from | |
11460 | Q->R. If this is the last cycle we are skipping; allow sorting of ready | |
f676971a | 11461 | queue by sh_reorder. */ |
58565a33 | 11462 | |
f676971a EC |
11463 | /* Generally, skipping these many cycles are sufficient for all insns to move |
11464 | from Q -> R. */ | |
11465 | #define MAX_SKIPS 8 | |
58565a33 SKG |
11466 | |
11467 | static int | |
508ea1c5 KH |
11468 | sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED, |
11469 | int sched_verbose ATTRIBUTE_UNUSED, | |
ac44248e | 11470 | rtx_insn *insn ATTRIBUTE_UNUSED, |
508ea1c5 KH |
11471 | int last_clock_var, |
11472 | int clock_var, | |
11473 | int *sort_p) | |
58565a33 SKG |
11474 | { |
11475 | if (reload_completed) | |
832a3292 | 11476 | return 0; |
58565a33 | 11477 | |
f676971a | 11478 | if (skip_cycles) |
58565a33 | 11479 | { |
832a3292 KH |
11480 | if ((clock_var - last_clock_var) < MAX_SKIPS) |
11481 | { | |
11482 | *sort_p = 0; | |
11483 | return 1; | |
11484 | } | |
11485 | /* If this is the last cycle we are skipping, allow reordering of R. */ | |
11486 | if ((clock_var - last_clock_var) == MAX_SKIPS) | |
11487 | { | |
11488 | *sort_p = 1; | |
11489 | return 1; | |
11490 | } | |
58565a33 | 11491 | } |
58565a33 SKG |
11492 | |
11493 | skip_cycles = 0; | |
11494 | ||
11495 | return 0; | |
11496 | } | |
11497 | ||
fa5322fa AO |
11498 | /* SHmedia requires registers for branches, so we can't generate new |
11499 | branches past reload. */ | |
11500 | static bool | |
cf277499 | 11501 | sh_cannot_modify_jumps_p (void) |
fa5322fa AO |
11502 | { |
11503 | return (TARGET_SHMEDIA && (reload_in_progress || reload_completed)); | |
11504 | } | |
11505 | ||
a87cf97e | 11506 | static reg_class_t |
fe3ad572 SC |
11507 | sh_target_reg_class (void) |
11508 | { | |
11509 | return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS; | |
11510 | } | |
11511 | ||
11512 | static bool | |
11513 | sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen) | |
11514 | { | |
73a4d10b R |
11515 | if (! shmedia_space_reserved_for_target_registers) |
11516 | return 0; | |
11517 | if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS) | |
11518 | return 0; | |
6387ab2c OE |
11519 | |
11520 | HARD_REG_SET dummy; | |
73a4d10b R |
11521 | if (calc_live_regs (&dummy) >= 6 * 8) |
11522 | return 1; | |
73a4d10b | 11523 | return 0; |
fe3ad572 SC |
11524 | } |
11525 | ||
fa5322fa | 11526 | static bool |
3101faab | 11527 | sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED) |
fa5322fa | 11528 | { |
61f71b34 | 11529 | return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type)); |
fa5322fa | 11530 | } |
ca903bba | 11531 | \f |
f676971a | 11532 | /* |
ca903bba R |
11533 | On the SH1..SH4, the trampoline looks like |
11534 | 2 0002 D202 mov.l l2,r2 | |
11535 | 1 0000 D301 mov.l l1,r3 | |
11536 | 3 0004 422B jmp @r2 | |
11537 | 4 0006 0009 nop | |
11538 | 5 0008 00000000 l1: .long area | |
11539 | 6 000c 00000000 l2: .long function | |
11540 | ||
11541 | SH5 (compact) uses r1 instead of r3 for the static chain. */ | |
11542 | ||
11543 | ||
11544 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
11545 | FNADDR is an RTX for the address of the function's pure code. | |
11546 | CXT is an RTX for the static chain value for the function. */ | |
994322ef RH |
11547 | static void |
11548 | sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt) | |
ca903bba | 11549 | { |
994322ef RH |
11550 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); |
11551 | rtx tramp = force_reg (Pmode, XEXP (tramp_mem, 0)); | |
57d38024 | 11552 | |
ca903bba R |
11553 | if (TARGET_SHMEDIA64) |
11554 | { | |
11555 | rtx tramp_templ; | |
11556 | int fixed_len; | |
11557 | ||
11558 | rtx movi1 = GEN_INT (0xcc000010); | |
11559 | rtx shori1 = GEN_INT (0xc8000010); | |
11560 | rtx src, dst; | |
11561 | ||
11562 | /* The following trampoline works within a +- 128 KB range for cxt: | |
11563 | ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0; | |
50fe8924 OE |
11564 | shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0 |
11565 | gettr tr1,r1; blink tr0,r63 */ | |
ca903bba R |
11566 | /* Address rounding makes it hard to compute the exact bounds of the |
11567 | offset for this trampoline, but we have a rather generous offset | |
11568 | range, so frame_offset should do fine as an upper bound. */ | |
11569 | if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000) | |
11570 | { | |
11571 | /* ??? could optimize this trampoline initialization | |
11572 | by writing DImode words with two insns each. */ | |
11573 | rtx mask = force_reg (DImode, GEN_INT (0x3fffc00)); | |
11574 | rtx insn = gen_rtx_MINUS (DImode, cxt, tramp); | |
11575 | insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2)); | |
11576 | insn = gen_rtx_AND (DImode, insn, mask); | |
11577 | /* Or in ptb/u .,tr1 pattern */ | |
11578 | insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode)); | |
11579 | insn = force_operand (insn, NULL_RTX); | |
11580 | insn = gen_lowpart (SImode, insn); | |
57d38024 | 11581 | emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn); |
ca903bba R |
11582 | insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38)); |
11583 | insn = gen_rtx_AND (DImode, insn, mask); | |
11584 | insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX); | |
11585 | insn = gen_lowpart (SImode, insn); | |
57d38024 | 11586 | emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn); |
ca903bba R |
11587 | insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22)); |
11588 | insn = gen_rtx_AND (DImode, insn, mask); | |
11589 | insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX); | |
11590 | insn = gen_lowpart (SImode, insn); | |
57d38024 | 11591 | emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn); |
ca903bba R |
11592 | insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6)); |
11593 | insn = gen_rtx_AND (DImode, insn, mask); | |
11594 | insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX); | |
11595 | insn = gen_lowpart (SImode, insn); | |
57d38024 | 11596 | emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn); |
ca903bba R |
11597 | insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10)); |
11598 | insn = gen_rtx_AND (DImode, insn, mask); | |
11599 | insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX); | |
11600 | insn = gen_lowpart (SImode, insn); | |
57d38024 R |
11601 | emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn); |
11602 | emit_move_insn (adjust_address (tramp_mem, SImode, 20), | |
ca903bba | 11603 | GEN_INT (0x6bf10600)); |
57d38024 | 11604 | emit_move_insn (adjust_address (tramp_mem, SImode, 24), |
ca903bba | 11605 | GEN_INT (0x4415fc10)); |
57d38024 | 11606 | emit_move_insn (adjust_address (tramp_mem, SImode, 28), |
ca903bba R |
11607 | GEN_INT (0x4401fff0)); |
11608 | emit_insn (gen_ic_invalidate_line (tramp)); | |
11609 | return; | |
11610 | } | |
11611 | tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline"); | |
11612 | fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode); | |
11613 | ||
11614 | tramp_templ = gen_datalabel_ref (tramp_templ); | |
57d38024 R |
11615 | dst = tramp_mem; |
11616 | src = gen_const_mem (BLKmode, tramp_templ); | |
ca903bba R |
11617 | set_mem_align (dst, 256); |
11618 | set_mem_align (src, 64); | |
44bb111a | 11619 | emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL); |
ca903bba | 11620 | |
57d38024 R |
11621 | emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr); |
11622 | emit_move_insn (adjust_address (tramp_mem, Pmode, | |
11623 | fixed_len + GET_MODE_SIZE (Pmode)), | |
ca903bba R |
11624 | cxt); |
11625 | emit_insn (gen_ic_invalidate_line (tramp)); | |
11626 | return; | |
11627 | } | |
11628 | else if (TARGET_SHMEDIA) | |
11629 | { | |
11630 | /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0 | |
11631 | movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */ | |
11632 | rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode); | |
11633 | rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode); | |
11634 | /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated, | |
825db093 | 11635 | rotated 10 right, and higher 16 bit of every 32 selected. */ |
ca903bba R |
11636 | rtx movishori |
11637 | = force_reg (V2HImode, (simplify_gen_subreg | |
11638 | (V2HImode, GEN_INT (0x4330432), SImode, 0))); | |
11639 | rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600)); | |
11640 | rtx blink = force_reg (DImode, GEN_INT (0x4401fff0)); | |
11641 | ||
ca903bba R |
11642 | fnaddr = force_reg (SImode, fnaddr); |
11643 | cxt = force_reg (SImode, cxt); | |
11644 | emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0), | |
11645 | gen_rtx_SUBREG (V2HImode, fnaddr, 0), | |
11646 | movishori)); | |
f1e2239f | 11647 | emit_insn (gen_rotrdi3_mextr (quad0, quad0, |
ca903bba | 11648 | GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56))); |
a556fd39 | 11649 | emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx)); |
57d38024 | 11650 | emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0); |
ca903bba R |
11651 | emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0), |
11652 | gen_rtx_SUBREG (V2HImode, cxt, 0), | |
11653 | movishori)); | |
f1e2239f | 11654 | emit_insn (gen_rotrdi3_mextr (cxtload, cxtload, |
ca903bba | 11655 | GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56))); |
a556fd39 | 11656 | emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx)); |
ca903bba R |
11657 | if (TARGET_LITTLE_ENDIAN) |
11658 | { | |
11659 | emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload)); | |
11660 | emit_insn (gen_mextr4 (quad2, cxtload, blink)); | |
11661 | } | |
11662 | else | |
11663 | { | |
11664 | emit_insn (gen_mextr4 (quad1, cxtload, ptabs)); | |
11665 | emit_insn (gen_mshflo_l_di (quad2, blink, cxtload)); | |
11666 | } | |
57d38024 R |
11667 | emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1); |
11668 | emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2); | |
ca903bba R |
11669 | emit_insn (gen_ic_invalidate_line (tramp)); |
11670 | return; | |
11671 | } | |
11672 | else if (TARGET_SHCOMPACT) | |
11673 | { | |
11674 | emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr)); | |
11675 | return; | |
11676 | } | |
57d38024 | 11677 | emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), |
ca903bba R |
11678 | gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301, |
11679 | SImode)); | |
57d38024 | 11680 | emit_move_insn (adjust_address (tramp_mem, SImode, 4), |
ca903bba R |
11681 | gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009, |
11682 | SImode)); | |
57d38024 R |
11683 | emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt); |
11684 | emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr); | |
ead4af4f | 11685 | if (TARGET_HARD_SH4 || TARGET_SH5) |
ca903bba | 11686 | { |
dc557046 | 11687 | if (!TARGET_INLINE_IC_INVALIDATE |
f3ca7111 | 11688 | || (!(TARGET_SH4A || TARGET_SH4_300) && TARGET_USERMODE)) |
73a4d10b R |
11689 | emit_library_call (function_symbol (NULL, "__ic_invalidate", |
11690 | FUNCTION_ORDINARY), | |
b757d36f | 11691 | LCT_NORMAL, VOIDmode, 1, tramp, SImode); |
ca903bba R |
11692 | else |
11693 | emit_insn (gen_ic_invalidate_line (tramp)); | |
11694 | } | |
11695 | } | |
11696 | ||
994322ef | 11697 | /* On SH5, trampolines are SHmedia code, so add 1 to the address. */ |
994322ef RH |
11698 | static rtx |
11699 | sh_trampoline_adjust_address (rtx tramp) | |
11700 | { | |
11701 | if (TARGET_SHMEDIA) | |
11702 | tramp = expand_simple_binop (Pmode, PLUS, tramp, const1_rtx, | |
11703 | gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); | |
11704 | return tramp; | |
11705 | } | |
11706 | ||
4977bab6 ZW |
11707 | /* FIXME: This is overly conservative. A SHcompact function that |
11708 | receives arguments ``by reference'' will have them stored in its | |
11709 | own stack frame, so it must not pass pointers or references to | |
11710 | these arguments to other functions by means of sibling calls. */ | |
73a4d10b R |
11711 | /* If PIC, we cannot make sibling calls to global functions |
11712 | because the PLT requires r12 to be live. */ | |
4977bab6 | 11713 | static bool |
cf277499 | 11714 | sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
4977bab6 | 11715 | { |
73a4d10b | 11716 | return (1 |
4977bab6 | 11717 | && (! TARGET_SHCOMPACT |
38173d38 | 11718 | || crtl->args.info.stack_regs == 0) |
73a4d10b R |
11719 | && ! sh_cfun_interrupt_handler_p () |
11720 | && (! flag_pic | |
11721 | || (decl && ! TREE_PUBLIC (decl)) | |
11722 | || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT))); | |
4977bab6 | 11723 | } |
c1b92d09 R |
11724 | \f |
11725 | /* Machine specific built-in functions. */ | |
11726 | ||
11727 | struct builtin_description | |
11728 | { | |
6d9e1220 | 11729 | bool (* const is_enabled) (void); |
c1b92d09 R |
11730 | const enum insn_code icode; |
11731 | const char *const name; | |
11732 | int signature; | |
1cc24576 | 11733 | tree fndecl; |
c1b92d09 R |
11734 | }; |
11735 | ||
6d9e1220 OE |
11736 | static bool |
11737 | shmedia_builtin_p (void) | |
11738 | { | |
11739 | return TARGET_SHMEDIA; | |
11740 | } | |
11741 | ||
6af1a779 | 11742 | /* This function can be used if there are any built-ins that are not for |
fe3e478f | 11743 | SHmedia. It's commented out to avoid the defined-but-unused warning. */ |
7d11d296 OE |
11744 | static bool |
11745 | sh1_builtin_p (void) | |
11746 | { | |
11747 | return TARGET_SH1; | |
11748 | } | |
11749 | ||
c1b92d09 R |
11750 | /* describe number and signedness of arguments; arg[0] == result |
11751 | (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */ | |
3b962ea0 | 11752 | /* 9: 64-bit pointer, 10: 32-bit pointer */ |
c1b92d09 R |
11753 | static const char signature_args[][4] = |
11754 | { | |
11755 | #define SH_BLTIN_V2SI2 0 | |
11756 | { 4, 4 }, | |
11757 | #define SH_BLTIN_V4HI2 1 | |
11758 | { 4, 4 }, | |
11759 | #define SH_BLTIN_V2SI3 2 | |
11760 | { 4, 4, 4 }, | |
11761 | #define SH_BLTIN_V4HI3 3 | |
11762 | { 4, 4, 4 }, | |
11763 | #define SH_BLTIN_V8QI3 4 | |
11764 | { 4, 4, 4 }, | |
11765 | #define SH_BLTIN_MAC_HISI 5 | |
11766 | { 1, 4, 4, 1 }, | |
11767 | #define SH_BLTIN_SH_HI 6 | |
11768 | { 4, 4, 1 }, | |
11769 | #define SH_BLTIN_SH_SI 7 | |
11770 | { 4, 4, 1 }, | |
11771 | #define SH_BLTIN_V4HI2V2SI 8 | |
11772 | { 4, 4, 4 }, | |
11773 | #define SH_BLTIN_V4HI2V8QI 9 | |
11774 | { 4, 4, 4 }, | |
11775 | #define SH_BLTIN_SISF 10 | |
11776 | { 4, 2 }, | |
11777 | #define SH_BLTIN_LDUA_L 11 | |
73a4d10b | 11778 | { 2, 10 }, |
c1b92d09 | 11779 | #define SH_BLTIN_LDUA_Q 12 |
73a4d10b | 11780 | { 1, 10 }, |
c1b92d09 | 11781 | #define SH_BLTIN_STUA_L 13 |
73a4d10b | 11782 | { 0, 10, 2 }, |
c1b92d09 | 11783 | #define SH_BLTIN_STUA_Q 14 |
73a4d10b R |
11784 | { 0, 10, 1 }, |
11785 | #define SH_BLTIN_LDUA_L64 15 | |
11786 | { 2, 9 }, | |
11787 | #define SH_BLTIN_LDUA_Q64 16 | |
11788 | { 1, 9 }, | |
11789 | #define SH_BLTIN_STUA_L64 17 | |
11790 | { 0, 9, 2 }, | |
11791 | #define SH_BLTIN_STUA_Q64 18 | |
11792 | { 0, 9, 1 }, | |
11793 | #define SH_BLTIN_NUM_SHARED_SIGNATURES 19 | |
11794 | #define SH_BLTIN_2 19 | |
11795 | #define SH_BLTIN_SU 19 | |
c1b92d09 | 11796 | { 1, 2 }, |
73a4d10b R |
11797 | #define SH_BLTIN_3 20 |
11798 | #define SH_BLTIN_SUS 20 | |
c1b92d09 | 11799 | { 2, 2, 1 }, |
73a4d10b | 11800 | #define SH_BLTIN_PSSV 21 |
c1b92d09 | 11801 | { 0, 8, 2, 2 }, |
73a4d10b R |
11802 | #define SH_BLTIN_XXUU 22 |
11803 | #define SH_BLTIN_UUUU 22 | |
c1b92d09 | 11804 | { 1, 1, 1, 1 }, |
73a4d10b | 11805 | #define SH_BLTIN_PV 23 |
c1b92d09 | 11806 | { 0, 8 }, |
7d11d296 OE |
11807 | #define SH_BLTIN_VP 24 |
11808 | { 8, 0 }, | |
fe3e478f OE |
11809 | #define SH_BLTIN_UV 25 |
11810 | { 1, 0 }, | |
11811 | #define SH_BLTIN_VU 26 | |
11812 | { 0, 1 }, | |
c1b92d09 | 11813 | }; |
24746a42 | 11814 | /* mcmv: operands considered unsigned. */ |
c1b92d09 | 11815 | /* mmulsum_wq, msad_ubq: result considered unsigned long long. */ |
24746a42 KH |
11816 | /* mperm: control value considered unsigned int. */ |
11817 | /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */ | |
c1b92d09 R |
11818 | /* mshards_q: returns signed short. */ |
11819 | /* nsb: takes long long arg, returns unsigned char. */ | |
1cc24576 KK |
11820 | static struct builtin_description bdesc[] = |
11821 | { | |
6d9e1220 OE |
11822 | { shmedia_builtin_p, |
11823 | CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2, 0 }, | |
11824 | { shmedia_builtin_p, | |
11825 | CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2, 0 }, | |
11826 | { shmedia_builtin_p, | |
11827 | CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3, 0 }, | |
11828 | { shmedia_builtin_p, | |
11829 | CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3, 0 }, | |
11830 | { shmedia_builtin_p, | |
11831 | CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3, 0 }, | |
11832 | { shmedia_builtin_p, | |
11833 | CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3, 0 }, | |
11834 | { shmedia_builtin_p, | |
11835 | CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3, 0 }, | |
11836 | { shmedia_builtin_p, | |
11837 | CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV, 0 }, | |
11838 | { shmedia_builtin_p, | |
11839 | CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3, 0 }, | |
11840 | { shmedia_builtin_p, | |
11841 | CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3, 0 }, | |
11842 | { shmedia_builtin_p, | |
11843 | CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3, 0 }, | |
11844 | { shmedia_builtin_p, | |
11845 | CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3, 0 }, | |
11846 | { shmedia_builtin_p, | |
11847 | CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3, 0 }, | |
11848 | { shmedia_builtin_p, | |
11849 | CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3, 0 }, | |
11850 | { shmedia_builtin_p, | |
11851 | CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU, 0 }, | |
11852 | { shmedia_builtin_p, | |
11853 | CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3, 0 }, | |
11854 | { shmedia_builtin_p, | |
11855 | CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI, 0 }, | |
11856 | { shmedia_builtin_p, | |
11857 | CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI, 0 }, | |
11858 | { shmedia_builtin_p, | |
11859 | CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3, 0 }, | |
11860 | { shmedia_builtin_p, | |
11861 | CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3, 0 }, | |
11862 | { shmedia_builtin_p, | |
11863 | CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3, 0 }, | |
11864 | { shmedia_builtin_p, | |
11865 | CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3, 0 }, | |
11866 | { shmedia_builtin_p, | |
11867 | CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3, 0 }, | |
11868 | { shmedia_builtin_p, | |
11869 | CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3, 0 }, | |
11870 | { shmedia_builtin_p, | |
11871 | CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3, 0 }, | |
11872 | { shmedia_builtin_p, | |
11873 | CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI, 0 }, | |
11874 | { shmedia_builtin_p, | |
11875 | CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI, 0 }, | |
11876 | { shmedia_builtin_p, | |
11877 | CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, 0 }, | |
11878 | { shmedia_builtin_p, | |
11879 | CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3, 0 }, | |
11880 | { shmedia_builtin_p, | |
11881 | CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3, 0 }, | |
11882 | { shmedia_builtin_p, | |
11883 | CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3, 0 }, | |
11884 | { shmedia_builtin_p, | |
11885 | CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3, 0 }, | |
11886 | { shmedia_builtin_p, | |
11887 | CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI, 0 }, | |
11888 | { shmedia_builtin_p, | |
11889 | CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI, 0 }, | |
11890 | { shmedia_builtin_p, | |
11891 | CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU, 0 }, | |
11892 | { shmedia_builtin_p, | |
11893 | CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI, 0 }, | |
11894 | { shmedia_builtin_p, | |
11895 | CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU, 0 }, | |
11896 | { shmedia_builtin_p, | |
11897 | CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI, 0 }, | |
11898 | { shmedia_builtin_p, | |
11899 | CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI, 0 }, | |
11900 | { shmedia_builtin_p, | |
11901 | CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI, 0 }, | |
11902 | { shmedia_builtin_p, | |
11903 | CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI, 0 }, | |
11904 | { shmedia_builtin_p, | |
11905 | CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS, 0 }, | |
11906 | { shmedia_builtin_p, | |
11907 | CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3, 0 }, | |
11908 | { shmedia_builtin_p, | |
11909 | CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3, 0 }, | |
11910 | { shmedia_builtin_p, | |
11911 | CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3, 0 }, | |
11912 | { shmedia_builtin_p, | |
11913 | CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3, 0 }, | |
11914 | { shmedia_builtin_p, | |
11915 | CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3, 0 }, | |
11916 | { shmedia_builtin_p, | |
11917 | CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3, 0 }, | |
11918 | { shmedia_builtin_p, | |
11919 | CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI, 0 }, | |
11920 | { shmedia_builtin_p, | |
11921 | CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI, 0 }, | |
11922 | { shmedia_builtin_p, | |
11923 | CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI, 0 }, | |
11924 | { shmedia_builtin_p, | |
11925 | CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI, 0 }, | |
11926 | { shmedia_builtin_p, | |
11927 | CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3, 0 }, | |
11928 | { shmedia_builtin_p, | |
11929 | CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3, 0 }, | |
11930 | { shmedia_builtin_p, | |
11931 | CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3, 0 }, | |
11932 | { shmedia_builtin_p, | |
11933 | CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3, 0 }, | |
11934 | { shmedia_builtin_p, | |
11935 | CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3, 0 }, | |
11936 | { shmedia_builtin_p, | |
11937 | CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF, 0 }, | |
11938 | { shmedia_builtin_p, | |
11939 | CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF, 0 }, | |
11940 | { shmedia_builtin_p, | |
11941 | CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3, 0 }, | |
11942 | { shmedia_builtin_p, | |
11943 | CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3, 0 }, | |
11944 | { shmedia_builtin_p, | |
11945 | CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2, 0 }, | |
11946 | { shmedia_builtin_p, | |
11947 | CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2, 0 }, | |
11948 | { shmedia_builtin_p, | |
11949 | CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2, 0 }, | |
11950 | { shmedia_builtin_p, | |
11951 | CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L, 0 }, | |
11952 | { shmedia_builtin_p, | |
11953 | CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q, 0 }, | |
11954 | { shmedia_builtin_p, | |
11955 | CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L, 0 }, | |
11956 | { shmedia_builtin_p, | |
11957 | CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q, 0 }, | |
11958 | { shmedia_builtin_p, | |
11959 | CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L, 0 }, | |
11960 | { shmedia_builtin_p, | |
11961 | CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q, 0 }, | |
11962 | { shmedia_builtin_p, | |
11963 | CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L, 0 }, | |
11964 | { shmedia_builtin_p, | |
11965 | CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q, 0 }, | |
11966 | { shmedia_builtin_p, | |
11967 | CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64, 0 }, | |
11968 | { shmedia_builtin_p, | |
11969 | CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64, 0 }, | |
11970 | { shmedia_builtin_p, | |
11971 | CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64, 0 }, | |
11972 | { shmedia_builtin_p, | |
11973 | CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64, 0 }, | |
11974 | { shmedia_builtin_p, | |
11975 | CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64, 0 }, | |
11976 | { shmedia_builtin_p, | |
11977 | CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64, 0 }, | |
11978 | { shmedia_builtin_p, | |
11979 | CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64, 0 }, | |
11980 | { shmedia_builtin_p, | |
11981 | CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64, 0 }, | |
11982 | { shmedia_builtin_p, | |
11983 | CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU, 0 }, | |
11984 | { shmedia_builtin_p, | |
11985 | CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2, 0 }, | |
11986 | { shmedia_builtin_p, | |
11987 | CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV, 0 }, | |
fe3e478f OE |
11988 | |
11989 | { sh1_builtin_p, | |
11990 | CODE_FOR_sts_fpscr, "__builtin_sh_get_fpscr", SH_BLTIN_UV, 0 }, | |
11991 | { sh1_builtin_p, | |
11992 | CODE_FOR_set_fpscr, "__builtin_sh_set_fpscr", SH_BLTIN_VU, 0 }, | |
c1b92d09 R |
11993 | }; |
11994 | ||
801881b0 KK |
11995 | static tree sh_builtin_get_fpscr; |
11996 | static tree sh_builtin_set_fpscr; | |
11997 | ||
c1b92d09 | 11998 | static void |
6d9e1220 | 11999 | sh_init_builtins (void) |
c1b92d09 R |
12000 | { |
12001 | tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES]; | |
a3acdc0c | 12002 | memset (shared, 0, sizeof shared); |
6d9e1220 OE |
12003 | |
12004 | for (unsigned int di = 0; di < ARRAY_SIZE (bdesc); ++di) | |
c1b92d09 | 12005 | { |
6d9e1220 OE |
12006 | builtin_description* d = &bdesc[di]; |
12007 | ||
12008 | if (!d->is_enabled ()) | |
12009 | continue; | |
12010 | ||
12011 | tree type, arg_type = NULL_TREE; | |
c1b92d09 | 12012 | int signature = d->signature; |
c1b92d09 R |
12013 | |
12014 | if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature]) | |
12015 | type = shared[signature]; | |
12016 | else | |
12017 | { | |
12018 | int has_result = signature_args[signature][0] != 0; | |
4cb44528 | 12019 | tree args[3]; |
c1b92d09 | 12020 | |
73a4d10b R |
12021 | if ((signature_args[signature][1] & 8) |
12022 | && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32) | |
12023 | || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64))) | |
c1b92d09 R |
12024 | continue; |
12025 | if (! TARGET_FPU_ANY | |
12026 | && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode)) | |
12027 | continue; | |
6d9e1220 | 12028 | for (unsigned int i = 0; i < ARRAY_SIZE (args); i++) |
4cb44528 | 12029 | args[i] = NULL_TREE; |
6d9e1220 | 12030 | for (int i = 3; ; i--) |
c1b92d09 R |
12031 | { |
12032 | int arg = signature_args[signature][i]; | |
12033 | int opno = i - 1 + has_result; | |
12034 | ||
73a4d10b | 12035 | if (arg & 8) |
c1b92d09 R |
12036 | arg_type = ptr_type_node; |
12037 | else if (arg) | |
73a4d10b | 12038 | arg_type = (*lang_hooks.types.type_for_mode) |
6d9e1220 | 12039 | (insn_data[d->icode].operand[opno].mode, (arg & 1)); |
c1b92d09 R |
12040 | else if (i) |
12041 | continue; | |
12042 | else | |
12043 | arg_type = void_type_node; | |
12044 | if (i == 0) | |
12045 | break; | |
4cb44528 | 12046 | args[i-1] = arg_type; |
c1b92d09 | 12047 | } |
4cb44528 NF |
12048 | type = build_function_type_list (arg_type, args[0], args[1], |
12049 | args[2], NULL_TREE); | |
c1b92d09 R |
12050 | if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES) |
12051 | shared[signature] = type; | |
12052 | } | |
1cc24576 KK |
12053 | d->fndecl = |
12054 | add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD, | |
12055 | NULL, NULL_TREE); | |
801881b0 KK |
12056 | /* Recode {sts,set}_fpscr decls for sh_atomic_assign_expand_fenv. */ |
12057 | if (d->icode == CODE_FOR_sts_fpscr) | |
12058 | sh_builtin_get_fpscr = d->fndecl; | |
12059 | else if (d->icode == CODE_FOR_set_fpscr) | |
12060 | sh_builtin_set_fpscr = d->fndecl; | |
c1b92d09 R |
12061 | } |
12062 | } | |
12063 | ||
801881b0 KK |
12064 | /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */ |
12065 | ||
12066 | static void | |
12067 | sh_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) | |
12068 | { | |
12069 | const unsigned SH_FE_INVALID = 64; | |
12070 | const unsigned SH_FE_DIVBYZERO = 32; | |
12071 | const unsigned SH_FE_OVERFLOW = 16; | |
12072 | const unsigned SH_FE_UNDERFLOW = 8; | |
12073 | const unsigned SH_FE_INEXACT = 4; | |
12074 | const unsigned HOST_WIDE_INT SH_FE_ALL_EXCEPT = (SH_FE_INVALID | |
12075 | | SH_FE_DIVBYZERO | |
12076 | | SH_FE_OVERFLOW | |
12077 | | SH_FE_UNDERFLOW | |
12078 | | SH_FE_INEXACT); | |
12079 | const unsigned HOST_WIDE_INT SH_FE_EXCEPT_SHIFT = 5; | |
12080 | tree fenv_var, mask, ld_fenv, masked_fenv; | |
12081 | tree new_fenv_var, reload_fenv, restore_fnenv; | |
12082 | tree update_call, atomic_feraiseexcept, hold_fnclex; | |
12083 | ||
12084 | if (! TARGET_FPU_ANY) | |
12085 | return; | |
12086 | ||
12087 | /* Generate the equivalent of : | |
12088 | unsigned int fenv_var; | |
12089 | fenv_var = __builtin_sh_get_fpscr (); | |
12090 | ||
12091 | unsigned int masked_fenv; | |
12092 | masked_fenv = fenv_var & mask; | |
12093 | ||
12094 | __builtin_sh_set_fpscr (masked_fenv); */ | |
12095 | ||
12096 | fenv_var = create_tmp_var (unsigned_type_node); | |
12097 | mask = build_int_cst (unsigned_type_node, | |
12098 | ~((SH_FE_ALL_EXCEPT << SH_FE_EXCEPT_SHIFT) | |
12099 | | SH_FE_ALL_EXCEPT)); | |
12100 | ld_fenv = build2 (MODIFY_EXPR, unsigned_type_node, | |
12101 | fenv_var, build_call_expr (sh_builtin_get_fpscr, 0)); | |
12102 | masked_fenv = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, mask); | |
12103 | hold_fnclex = build_call_expr (sh_builtin_set_fpscr, 1, masked_fenv); | |
12104 | *hold = build2 (COMPOUND_EXPR, void_type_node, | |
12105 | build2 (COMPOUND_EXPR, void_type_node, masked_fenv, ld_fenv), | |
12106 | hold_fnclex); | |
12107 | ||
12108 | /* Store the value of masked_fenv to clear the exceptions: | |
12109 | __builtin_sh_set_fpscr (masked_fenv); */ | |
12110 | ||
12111 | *clear = build_call_expr (sh_builtin_set_fpscr, 1, masked_fenv); | |
12112 | ||
12113 | /* Generate the equivalent of : | |
12114 | unsigned int new_fenv_var; | |
12115 | new_fenv_var = __builtin_sh_get_fpscr (); | |
12116 | ||
12117 | __builtin_sh_set_fpscr (fenv_var); | |
12118 | ||
12119 | __atomic_feraiseexcept (new_fenv_var); */ | |
12120 | ||
12121 | new_fenv_var = create_tmp_var (unsigned_type_node); | |
12122 | reload_fenv = build2 (MODIFY_EXPR, unsigned_type_node, new_fenv_var, | |
12123 | build_call_expr (sh_builtin_get_fpscr, 0)); | |
12124 | restore_fnenv = build_call_expr (sh_builtin_set_fpscr, 1, fenv_var); | |
12125 | atomic_feraiseexcept = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT); | |
12126 | update_call = build_call_expr (atomic_feraiseexcept, 1, | |
12127 | fold_convert (integer_type_node, | |
12128 | new_fenv_var)); | |
12129 | *update = build2 (COMPOUND_EXPR, void_type_node, | |
12130 | build2 (COMPOUND_EXPR, void_type_node, | |
12131 | reload_fenv, restore_fnenv), update_call); | |
12132 | } | |
12133 | ||
f676971a EC |
12134 | /* Implements target hook vector_mode_supported_p. */ |
12135 | bool | |
ef4bddc2 | 12136 | sh_vector_mode_supported_p (machine_mode mode) |
f676971a EC |
12137 | { |
12138 | if (TARGET_FPU_ANY | |
12139 | && ((mode == V2SFmode) | |
12140 | || (mode == V4SFmode) | |
12141 | || (mode == V16SFmode))) | |
12142 | return true; | |
12143 | ||
12144 | else if (TARGET_SHMEDIA | |
12145 | && ((mode == V8QImode) | |
12146 | || (mode == V2HImode) | |
12147 | || (mode == V4HImode) | |
12148 | || (mode == V2SImode))) | |
12149 | return true; | |
12150 | ||
12151 | return false; | |
12152 | } | |
12153 | ||
7a296495 CB |
12154 | bool |
12155 | sh_frame_pointer_required (void) | |
12156 | { | |
12157 | /* If needed override this in other tm.h files to cope with various OS | |
12158 | lossage requiring a frame pointer. */ | |
12159 | if (SUBTARGET_FRAME_POINTER_REQUIRED) | |
12160 | return true; | |
12161 | ||
12162 | if (crtl->profile) | |
12163 | return true; | |
12164 | ||
12165 | return false; | |
12166 | } | |
12167 | ||
a1c496cb EC |
12168 | /* Implements target hook dwarf_calling_convention. Return an enum |
12169 | of dwarf_calling_convention. */ | |
12170 | int | |
3101faab | 12171 | sh_dwarf_calling_convention (const_tree func) |
a1c496cb EC |
12172 | { |
12173 | if (sh_attr_renesas_p (func)) | |
29832164 | 12174 | return DW_CC_GNU_renesas_sh; |
a1c496cb EC |
12175 | |
12176 | return DW_CC_normal; | |
12177 | } | |
12178 | ||
1cc24576 | 12179 | /* Returns the sh builtin decl for CODE. */ |
1cc24576 KK |
12180 | static tree |
12181 | sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) | |
6d9e1220 OE |
12182 | { |
12183 | if (code >= ARRAY_SIZE (bdesc)) | |
12184 | return error_mark_node; | |
12185 | ||
12186 | if (!bdesc[code].is_enabled ()) | |
12187 | return error_mark_node; | |
12188 | ||
12189 | return bdesc[code].fndecl; | |
1cc24576 KK |
12190 | } |
12191 | ||
c1b92d09 R |
12192 | /* Expand an expression EXP that calls a built-in function, |
12193 | with result going to TARGET if that's convenient | |
12194 | (and in mode MODE if that's convenient). | |
12195 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
12196 | IGNORE is nonzero if the value is to be ignored. */ | |
c1b92d09 | 12197 | static rtx |
cf277499 | 12198 | sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
ef4bddc2 | 12199 | machine_mode mode ATTRIBUTE_UNUSED, int ignore) |
c1b92d09 | 12200 | { |
5039610b | 12201 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
c1b92d09 R |
12202 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
12203 | const struct builtin_description *d = &bdesc[fcode]; | |
12204 | enum insn_code icode = d->icode; | |
12205 | int signature = d->signature; | |
6d9e1220 | 12206 | int nop = 0; |
c1b92d09 | 12207 | rtx op[4]; |
c1b92d09 R |
12208 | |
12209 | if (signature_args[signature][0]) | |
12210 | { | |
12211 | if (ignore) | |
23d0939b | 12212 | return NULL_RTX; |
c1b92d09 | 12213 | |
ef4bddc2 | 12214 | machine_mode tmode = insn_data[icode].operand[0].mode; |
6d9e1220 | 12215 | if (! target || GET_MODE (target) != tmode |
c1b92d09 R |
12216 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) |
12217 | target = gen_reg_rtx (tmode); | |
12218 | op[nop++] = target; | |
12219 | } | |
12220 | else | |
6d9e1220 | 12221 | target = NULL_RTX; |
c1b92d09 | 12222 | |
6d9e1220 | 12223 | for (int i = 1; i <= 3; i++, nop++) |
c1b92d09 R |
12224 | { |
12225 | tree arg; | |
ef4bddc2 | 12226 | machine_mode opmode, argmode; |
73a4d10b | 12227 | tree optype; |
c1b92d09 R |
12228 | |
12229 | if (! signature_args[signature][i]) | |
12230 | break; | |
5039610b | 12231 | arg = CALL_EXPR_ARG (exp, i - 1); |
3578cf63 R |
12232 | if (arg == error_mark_node) |
12233 | return const0_rtx; | |
73a4d10b R |
12234 | if (signature_args[signature][i] & 8) |
12235 | { | |
12236 | opmode = ptr_mode; | |
12237 | optype = ptr_type_node; | |
12238 | } | |
12239 | else | |
12240 | { | |
12241 | opmode = insn_data[icode].operand[nop].mode; | |
12242 | optype = (*lang_hooks.types.type_for_mode) (opmode, 0); | |
12243 | } | |
c1b92d09 R |
12244 | argmode = TYPE_MODE (TREE_TYPE (arg)); |
12245 | if (argmode != opmode) | |
73a4d10b | 12246 | arg = build1 (NOP_EXPR, optype, arg); |
b757d36f | 12247 | op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL); |
c1b92d09 R |
12248 | if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode)) |
12249 | op[nop] = copy_to_mode_reg (opmode, op[nop]); | |
12250 | } | |
12251 | ||
6d9e1220 OE |
12252 | rtx pat = NULL_RTX; |
12253 | ||
c1b92d09 R |
12254 | switch (nop) |
12255 | { | |
12256 | case 1: | |
12257 | pat = (*insn_data[d->icode].genfun) (op[0]); | |
12258 | break; | |
12259 | case 2: | |
12260 | pat = (*insn_data[d->icode].genfun) (op[0], op[1]); | |
12261 | break; | |
12262 | case 3: | |
12263 | pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]); | |
12264 | break; | |
12265 | case 4: | |
12266 | pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]); | |
12267 | break; | |
95c0af87 | 12268 | default: |
f5b9e7c9 | 12269 | gcc_unreachable (); |
c1b92d09 R |
12270 | } |
12271 | if (! pat) | |
23d0939b | 12272 | return NULL_RTX; |
c1b92d09 R |
12273 | emit_insn (pat); |
12274 | return target; | |
12275 | } | |
0ac78517 R |
12276 | |
12277 | void | |
cf277499 | 12278 | sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1) |
0ac78517 R |
12279 | { |
12280 | rtx sel0 = const0_rtx; | |
12281 | rtx sel1 = const1_rtx; | |
cf277499 | 12282 | rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op; |
0ac78517 R |
12283 | rtx op = gen_rtx_fmt_e (code, SFmode, op1); |
12284 | ||
12285 | emit_insn ((*fn) (op0, op1, op, sel0, sel0)); | |
12286 | emit_insn ((*fn) (op0, op1, op, sel1, sel1)); | |
12287 | } | |
12288 | ||
12289 | void | |
cf277499 | 12290 | sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2) |
0ac78517 | 12291 | { |
0ac78517 R |
12292 | rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2); |
12293 | ||
f8be3f56 KK |
12294 | emit_insn (gen_binary_sf_op0 (op0, op1, op2, op)); |
12295 | emit_insn (gen_binary_sf_op1 (op0, op1, op2, op)); | |
0ac78517 R |
12296 | } |
12297 | ||
347146a4 KK |
12298 | /* Return true if hard register REGNO can hold a value of machine-mode MODE. |
12299 | We can allow any mode in any general register. The special registers | |
12300 | only allow SImode. Don't allow any mode in the PR. | |
12301 | ||
12302 | We cannot hold DCmode values in the XD registers because alter_reg | |
12303 | handles subregs of them incorrectly. We could work around this by | |
12304 | spacing the XD registers like the DR registers, but this would require | |
12305 | additional memory in every compilation to hold larger register vectors. | |
12306 | We could hold SFmode / SCmode values in XD registers, but that | |
12307 | would require a tertiary reload when reloading from / to memory, | |
12308 | and a secondary reload to reload from / to general regs; that | |
073a8998 | 12309 | seems to be a losing proposition. |
347146a4 KK |
12310 | |
12311 | We want to allow TImode FP regs so that when V4SFmode is loaded as TImode, | |
12312 | it won't be ferried through GP registers first. */ | |
347146a4 | 12313 | bool |
ef4bddc2 | 12314 | sh_hard_regno_mode_ok (unsigned int regno, machine_mode mode) |
347146a4 KK |
12315 | { |
12316 | if (SPECIAL_REGISTER_P (regno)) | |
12317 | return mode == SImode; | |
12318 | ||
12319 | if (regno == FPUL_REG) | |
12320 | return (mode == SImode || mode == SFmode); | |
12321 | ||
12322 | if (FP_REGISTER_P (regno) && mode == SFmode) | |
12323 | return true; | |
12324 | ||
12325 | if (mode == V2SFmode) | |
12326 | { | |
12327 | if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0) | |
12328 | || GENERAL_REGISTER_P (regno))) | |
12329 | return true; | |
12330 | else | |
12331 | return false; | |
12332 | } | |
12333 | ||
12334 | if (mode == V4SFmode) | |
12335 | { | |
12336 | if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0) | |
12337 | || GENERAL_REGISTER_P (regno)) | |
12338 | return true; | |
12339 | else | |
12340 | return false; | |
12341 | } | |
12342 | ||
12343 | if (mode == V16SFmode) | |
12344 | { | |
12345 | if (TARGET_SHMEDIA) | |
12346 | { | |
12347 | if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0) | |
12348 | return true; | |
12349 | else | |
12350 | return false; | |
12351 | } | |
12352 | else | |
12353 | return regno == FIRST_XD_REG; | |
12354 | } | |
12355 | ||
12356 | if (FP_REGISTER_P (regno)) | |
12357 | { | |
12358 | if (mode == SFmode | |
12359 | || mode == SImode | |
12360 | || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode) | |
12361 | || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode) | |
12362 | || mode == DCmode | |
12363 | || (TARGET_SHMEDIA | |
12364 | && (mode == DFmode || mode == DImode | |
12365 | || mode == V2SFmode || mode == TImode))) | |
12366 | && ((regno - FIRST_FP_REG) & 1) == 0) | |
12367 | || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode | |
12368 | && ((regno - FIRST_FP_REG) & 3) == 0)) | |
12369 | return true; | |
12370 | else | |
12371 | return false; | |
12372 | } | |
12373 | ||
12374 | if (XD_REGISTER_P (regno)) | |
12375 | return mode == DFmode; | |
12376 | ||
12377 | if (TARGET_REGISTER_P (regno)) | |
12378 | return (mode == DImode || mode == SImode || mode == PDImode); | |
12379 | ||
12380 | if (regno == PR_REG) | |
12381 | return mode == SImode; | |
12382 | ||
12383 | if (regno == FPSCR_REG) | |
fe3e478f | 12384 | return mode == SImode; |
347146a4 KK |
12385 | |
12386 | /* FIXME. This works around PR target/37633 for -O0. */ | |
12387 | if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4) | |
12388 | { | |
12389 | unsigned int n = GET_MODE_SIZE (mode) / 8; | |
12390 | ||
12391 | if (regno >= FIRST_GENERAL_REG + 10 - n + 1 | |
12392 | && regno <= FIRST_GENERAL_REG + 14) | |
12393 | return false; | |
12394 | } | |
12395 | ||
12396 | return true; | |
12397 | } | |
12398 | ||
fc1fcfa0 KK |
12399 | /* Specify the modes required to caller save a given hard regno. |
12400 | choose_hard_reg_mode chooses mode based on HARD_REGNO_MODE_OK | |
12401 | and returns ?Imode for float regs when sh_hard_regno_mode_ok | |
12402 | permits integer modes on them. That makes LRA's split process | |
12403 | unhappy. See PR55212. | |
12404 | */ | |
12405 | machine_mode | |
12406 | sh_hard_regno_caller_save_mode (unsigned int regno, unsigned int nregs, | |
12407 | machine_mode mode) | |
12408 | { | |
12409 | if (FP_REGISTER_P (regno) | |
12410 | && (mode == SFmode | |
12411 | || mode == SCmode | |
12412 | || ((mode == DFmode || mode == DCmode) | |
12413 | && ((regno - FIRST_FP_REG) & 1) == 0))) | |
12414 | return mode; | |
12415 | ||
12416 | return choose_hard_reg_mode (regno, nregs, false); | |
12417 | } | |
12418 | ||
cff9f8d5 AH |
12419 | /* Return the class of registers for which a mode change from FROM to TO |
12420 | is invalid. */ | |
b0c42aed | 12421 | bool |
ef4bddc2 | 12422 | sh_cannot_change_mode_class (machine_mode from, machine_mode to, |
0a2aaacc | 12423 | enum reg_class rclass) |
cff9f8d5 | 12424 | { |
312209c6 AO |
12425 | /* We want to enable the use of SUBREGs as a means to |
12426 | VEC_SELECT a single element of a vector. */ | |
344332e8 OE |
12427 | |
12428 | /* This effectively disallows using GENERAL_REGS for SFmode vector subregs. | |
12429 | This can be problematic when SFmode vector subregs need to be accessed | |
12430 | on the stack with displacement addressing, as it happens with -O0. | |
12431 | Thus we disallow the mode change for -O0. */ | |
312209c6 | 12432 | if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode) |
344332e8 | 12433 | return optimize ? (reg_classes_intersect_p (GENERAL_REGS, rclass)) : false; |
312209c6 | 12434 | |
cff9f8d5 AH |
12435 | if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to)) |
12436 | { | |
832a3292 KH |
12437 | if (TARGET_LITTLE_ENDIAN) |
12438 | { | |
12439 | if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8) | |
0a2aaacc | 12440 | return reg_classes_intersect_p (DF_REGS, rclass); |
832a3292 KH |
12441 | } |
12442 | else | |
12443 | { | |
12444 | if (GET_MODE_SIZE (from) < 8) | |
1818d01c | 12445 | return reg_classes_intersect_p (DF_REGS, rclass); |
832a3292 | 12446 | } |
cff9f8d5 | 12447 | } |
344332e8 | 12448 | return false; |
cff9f8d5 AH |
12449 | } |
12450 | ||
42db504c SB |
12451 | /* Return true if registers in machine mode MODE will likely be |
12452 | allocated to registers in small register classes. */ | |
9c265c4d | 12453 | bool |
ef4bddc2 | 12454 | sh_small_register_classes_for_mode_p (machine_mode mode ATTRIBUTE_UNUSED) |
42db504c SB |
12455 | { |
12456 | return (! TARGET_SHMEDIA); | |
12457 | } | |
ea4210ef RS |
12458 | |
12459 | /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times | |
12460 | that label is used. */ | |
ea4210ef | 12461 | void |
cf277499 | 12462 | sh_mark_label (rtx address, int nuses) |
ea4210ef RS |
12463 | { |
12464 | if (GOTOFF_P (address)) | |
12465 | { | |
12466 | /* Extract the label or symbol. */ | |
12467 | address = XEXP (address, 0); | |
12468 | if (GET_CODE (address) == PLUS) | |
12469 | address = XEXP (address, 0); | |
12470 | address = XVECEXP (address, 0, 0); | |
12471 | } | |
12472 | if (GET_CODE (address) == LABEL_REF | |
f3536097 | 12473 | && LABEL_P (XEXP (address, 0))) |
ea4210ef RS |
12474 | LABEL_NUSES (XEXP (address, 0)) += nuses; |
12475 | } | |
12476 | ||
95c0af87 | 12477 | /* Compute extra cost of moving data between one register class |
50fe8924 | 12478 | and another. |
95c0af87 | 12479 | |
50fe8924 | 12480 | If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass |
ec555f32 | 12481 | uses this information. Hence, the general register <-> floating point |
95c0af87 | 12482 | register information here is not used for SFmode. */ |
e7a8f681 | 12483 | static int |
ef4bddc2 | 12484 | sh_register_move_cost (machine_mode mode, |
e7a8f681 | 12485 | reg_class_t srcclass, reg_class_t dstclass) |
95c0af87 JR |
12486 | { |
12487 | if (dstclass == T_REGS || dstclass == PR_REGS) | |
12488 | return 10; | |
12489 | ||
b1dcf523 DD |
12490 | if (dstclass == MAC_REGS && srcclass == MAC_REGS) |
12491 | return 4; | |
12492 | ||
ec555f32 R |
12493 | if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD |
12494 | && REGCLASS_HAS_FP_REG (srcclass) | |
12495 | && REGCLASS_HAS_FP_REG (dstclass)) | |
12496 | return 4; | |
12497 | ||
9c24200c KK |
12498 | if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS) |
12499 | return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7); | |
12500 | ||
a60a9553 | 12501 | if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS) |
832a3292 | 12502 | || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass))) |
a60a9553 R |
12503 | return 9; |
12504 | ||
95c0af87 JR |
12505 | if ((REGCLASS_HAS_FP_REG (dstclass) |
12506 | && REGCLASS_HAS_GENERAL_REG (srcclass)) | |
12507 | || (REGCLASS_HAS_GENERAL_REG (dstclass) | |
12508 | && REGCLASS_HAS_FP_REG (srcclass))) | |
4978c736 KK |
12509 | { |
12510 | /* Discourage trying to use fp regs for a pointer. This also | |
12511 | discourages fp regs with SImode because Pmode is an alias | |
12512 | of SImode on this target. See PR target/48596. */ | |
12513 | int addend = (mode == Pmode) ? 40 : 0; | |
12514 | ||
12515 | return (((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12) + addend) | |
12516 | * ((GET_MODE_SIZE (mode) + 7) / 8U)); | |
12517 | } | |
95c0af87 JR |
12518 | |
12519 | if ((dstclass == FPUL_REGS | |
12520 | && REGCLASS_HAS_GENERAL_REG (srcclass)) | |
12521 | || (srcclass == FPUL_REGS | |
12522 | && REGCLASS_HAS_GENERAL_REG (dstclass))) | |
12523 | return 5; | |
12524 | ||
12525 | if ((dstclass == FPUL_REGS | |
12526 | && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS)) | |
f676971a | 12527 | || (srcclass == FPUL_REGS |
95c0af87 JR |
12528 | && (dstclass == PR_REGS || dstclass == MAC_REGS))) |
12529 | return 7; | |
12530 | ||
12531 | if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass)) | |
12532 | || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass))) | |
12533 | return 20; | |
12534 | ||
73a4d10b R |
12535 | /* ??? ptabs faults on (value & 0x3) == 0x3 */ |
12536 | if (TARGET_SHMEDIA | |
12537 | && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS)) | |
12538 | { | |
7dd2f19b RS |
12539 | if (sh_gettrcost >= 0) |
12540 | return sh_gettrcost; | |
73a4d10b R |
12541 | else if (!TARGET_PT_FIXED) |
12542 | return 100; | |
12543 | } | |
12544 | ||
95c0af87 JR |
12545 | if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass)) |
12546 | || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass))) | |
12547 | return 4; | |
12548 | ||
ec555f32 R |
12549 | if (TARGET_SHMEDIA |
12550 | || (TARGET_FMOVD | |
12551 | && ! REGCLASS_HAS_GENERAL_REG (srcclass) | |
12552 | && ! REGCLASS_HAS_GENERAL_REG (dstclass))) | |
12553 | return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U); | |
12554 | ||
12555 | return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U); | |
95c0af87 JR |
12556 | } |
12557 | ||
1aa03f38 | 12558 | static rtx |
cf277499 | 12559 | emit_load_ptr (rtx reg, rtx addr) |
1aa03f38 | 12560 | { |
57d38024 | 12561 | rtx mem = gen_const_mem (ptr_mode, addr); |
1aa03f38 R |
12562 | |
12563 | if (Pmode != ptr_mode) | |
12564 | mem = gen_rtx_SIGN_EXTEND (Pmode, mem); | |
12565 | return emit_move_insn (reg, mem); | |
12566 | } | |
12567 | ||
73a4d10b | 12568 | static void |
cf277499 SB |
12569 | sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
12570 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
12571 | tree function) | |
1aa03f38 R |
12572 | { |
12573 | CUMULATIVE_ARGS cum; | |
12574 | int structure_value_byref = 0; | |
6cb7eb41 DM |
12575 | rtx this_rtx, this_value, sibcall, funexp; |
12576 | rtx_insn *insns; | |
1aa03f38 | 12577 | tree funtype = TREE_TYPE (function); |
735cb76e | 12578 | int simple_add = CONST_OK_FOR_ADD (delta); |
1aa03f38 R |
12579 | int did_load = 0; |
12580 | rtx scratch0, scratch1, scratch2; | |
73a4d10b | 12581 | unsigned i; |
1aa03f38 R |
12582 | |
12583 | reload_completed = 1; | |
fe3ad572 | 12584 | epilogue_completed = 1; |
416ff32e | 12585 | crtl->uses_only_leaf_regs = 1; |
1aa03f38 | 12586 | |
2e040219 | 12587 | emit_note (NOTE_INSN_PROLOGUE_END); |
1aa03f38 R |
12588 | |
12589 | /* Find the "this" pointer. We have such a wide range of ABIs for the | |
12590 | SH that it's best to do this completely machine independently. | |
f676971a | 12591 | "this" is passed as first argument, unless a structure return pointer |
1aa03f38 | 12592 | comes first, in which case "this" comes second. */ |
0f6937fe | 12593 | INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1); |
1aa03f38 | 12594 | #ifndef PCC_STATIC_STRUCT_RETURN |
61f71b34 | 12595 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
1aa03f38 R |
12596 | structure_value_byref = 1; |
12597 | #endif /* not PCC_STATIC_STRUCT_RETURN */ | |
61f71b34 | 12598 | if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0) |
f676971a | 12599 | { |
1aa03f38 R |
12600 | tree ptype = build_pointer_type (TREE_TYPE (funtype)); |
12601 | ||
d5cc9181 | 12602 | sh_function_arg_advance (pack_cumulative_args (&cum), Pmode, ptype, true); |
1aa03f38 | 12603 | } |
d5cc9181 JR |
12604 | this_rtx |
12605 | = sh_function_arg (pack_cumulative_args (&cum), Pmode, ptr_type_node, true); | |
1aa03f38 R |
12606 | |
12607 | /* For SHcompact, we only have r0 for a scratch register: r1 is the | |
12608 | static chain pointer (even if you can't have nested virtual functions | |
12609 | right now, someone might implement them sometime), and the rest of the | |
12610 | registers are used for argument passing, are callee-saved, or reserved. */ | |
73a4d10b R |
12611 | /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg / |
12612 | -ffixed-reg has been used. */ | |
12613 | if (! call_used_regs[0] || fixed_regs[0]) | |
12614 | error ("r0 needs to be available as a call-clobbered register"); | |
1aa03f38 R |
12615 | scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0); |
12616 | if (! TARGET_SH5) | |
12617 | { | |
73a4d10b R |
12618 | if (call_used_regs[1] && ! fixed_regs[1]) |
12619 | scratch1 = gen_rtx_REG (ptr_mode, 1); | |
1aa03f38 R |
12620 | /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer |
12621 | pointing where to return struct values. */ | |
73a4d10b R |
12622 | if (call_used_regs[3] && ! fixed_regs[3]) |
12623 | scratch2 = gen_rtx_REG (Pmode, 3); | |
1aa03f38 R |
12624 | } |
12625 | else if (TARGET_SHMEDIA) | |
12626 | { | |
73a4d10b R |
12627 | for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++) |
12628 | if (i != REGNO (scratch0) && | |
12629 | call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i)) | |
12630 | { | |
12631 | scratch1 = gen_rtx_REG (ptr_mode, i); | |
12632 | break; | |
12633 | } | |
12634 | if (scratch1 == scratch0) | |
d8a07487 | 12635 | error ("need a second call-clobbered general purpose register"); |
73a4d10b R |
12636 | for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++) |
12637 | if (call_used_regs[i] && ! fixed_regs[i]) | |
12638 | { | |
12639 | scratch2 = gen_rtx_REG (Pmode, i); | |
12640 | break; | |
12641 | } | |
12642 | if (scratch2 == scratch0) | |
d8a07487 | 12643 | error ("need a call-clobbered target register"); |
1aa03f38 R |
12644 | } |
12645 | ||
0a81f074 | 12646 | this_value = plus_constant (Pmode, this_rtx, delta); |
1aa03f38 R |
12647 | if (vcall_offset |
12648 | && (simple_add || scratch0 != scratch1) | |
12649 | && strict_memory_address_p (ptr_mode, this_value)) | |
12650 | { | |
12651 | emit_load_ptr (scratch0, this_value); | |
12652 | did_load = 1; | |
12653 | } | |
12654 | ||
12655 | if (!delta) | |
12656 | ; /* Do nothing. */ | |
12657 | else if (simple_add) | |
0a2aaacc | 12658 | emit_move_insn (this_rtx, this_value); |
1aa03f38 R |
12659 | else |
12660 | { | |
12661 | emit_move_insn (scratch1, GEN_INT (delta)); | |
0a2aaacc | 12662 | emit_insn (gen_add2_insn (this_rtx, scratch1)); |
1aa03f38 R |
12663 | } |
12664 | ||
12665 | if (vcall_offset) | |
12666 | { | |
12667 | rtx offset_addr; | |
12668 | ||
12669 | if (!did_load) | |
0a2aaacc | 12670 | emit_load_ptr (scratch0, this_rtx); |
1aa03f38 | 12671 | |
0a81f074 | 12672 | offset_addr = plus_constant (Pmode, scratch0, vcall_offset); |
1aa03f38 R |
12673 | if (strict_memory_address_p (ptr_mode, offset_addr)) |
12674 | ; /* Do nothing. */ | |
73a4d10b | 12675 | else if (! TARGET_SH5 && scratch0 != scratch1) |
1aa03f38 R |
12676 | { |
12677 | /* scratch0 != scratch1, and we have indexed loads. Get better | |
12678 | schedule by loading the offset into r1 and using an indexed | |
12679 | load - then the load of r1 can issue before the load from | |
50fe8924 | 12680 | (this_rtx + delta) finishes. */ |
1aa03f38 R |
12681 | emit_move_insn (scratch1, GEN_INT (vcall_offset)); |
12682 | offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1); | |
12683 | } | |
735cb76e | 12684 | else if (CONST_OK_FOR_ADD (vcall_offset)) |
1aa03f38 R |
12685 | { |
12686 | emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset))); | |
12687 | offset_addr = scratch0; | |
12688 | } | |
12689 | else if (scratch0 != scratch1) | |
12690 | { | |
12691 | emit_move_insn (scratch1, GEN_INT (vcall_offset)); | |
12692 | emit_insn (gen_add2_insn (scratch0, scratch1)); | |
12693 | offset_addr = scratch0; | |
12694 | } | |
12695 | else | |
f5b9e7c9 | 12696 | gcc_unreachable (); /* FIXME */ |
1aa03f38 R |
12697 | emit_load_ptr (scratch0, offset_addr); |
12698 | ||
832a3292 | 12699 | if (Pmode != ptr_mode) |
1aa03f38 | 12700 | scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0); |
0a2aaacc | 12701 | emit_insn (gen_add2_insn (this_rtx, scratch0)); |
1aa03f38 R |
12702 | } |
12703 | ||
12704 | /* Generate a tail call to the target function. */ | |
12705 | if (! TREE_USED (function)) | |
12706 | { | |
12707 | assemble_external (function); | |
12708 | TREE_USED (function) = 1; | |
12709 | } | |
12710 | funexp = XEXP (DECL_RTL (function), 0); | |
73a4d10b R |
12711 | /* If the function is overridden, so is the thunk, hence we don't |
12712 | need GOT addressing even if this is a public symbol. */ | |
12713 | #if 0 | |
12714 | if (TARGET_SH1 && ! flag_weak) | |
12715 | sibcall = gen_sibcalli_thunk (funexp, const0_rtx); | |
12716 | else | |
12717 | #endif | |
12718 | if (TARGET_SH2 && flag_pic) | |
12719 | { | |
12720 | sibcall = gen_sibcall_pcrel (funexp, const0_rtx); | |
12721 | XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2; | |
12722 | } | |
12723 | else | |
12724 | { | |
12725 | if (TARGET_SHMEDIA && flag_pic) | |
12726 | { | |
12727 | funexp = gen_sym2PIC (funexp); | |
12728 | PUT_MODE (funexp, Pmode); | |
12729 | } | |
12730 | emit_move_insn (scratch2, funexp); | |
12731 | funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2); | |
12732 | sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX); | |
12733 | } | |
12734 | sibcall = emit_call_insn (sibcall); | |
1aa03f38 | 12735 | SIBLING_CALL_P (sibcall) = 1; |
0a2aaacc | 12736 | use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx); |
1aa03f38 R |
12737 | emit_barrier (); |
12738 | ||
a2855205 | 12739 | /* Run just enough of rest_of_compilation to do scheduling and get |
1aa03f38 R |
12740 | the insns emitted. Note that use_thunk calls |
12741 | assemble_start_function and assemble_end_function. */ | |
a2855205 | 12742 | |
1aa03f38 R |
12743 | insns = get_insns (); |
12744 | ||
6fb5fa3c DB |
12745 | if (optimize > 0) |
12746 | { | |
12747 | if (! cfun->cfg) | |
eb6cbf91 | 12748 | init_flow (cfun); |
6fb5fa3c DB |
12749 | split_all_insns_noflow (); |
12750 | } | |
1aa03f38 | 12751 | |
18dbd950 | 12752 | sh_reorg (); |
1aa03f38 R |
12753 | shorten_branches (insns); |
12754 | final_start_function (insns, file, 1); | |
c9d691e9 | 12755 | final (insns, file, 1); |
1aa03f38 R |
12756 | final_end_function (); |
12757 | ||
1aa03f38 | 12758 | reload_completed = 0; |
fe3ad572 | 12759 | epilogue_completed = 0; |
1aa03f38 R |
12760 | } |
12761 | ||
90534361 | 12762 | rtx |
73a4d10b | 12763 | function_symbol (rtx target, const char *name, enum sh_function_kind kind) |
90534361 | 12764 | { |
73a4d10b R |
12765 | rtx sym; |
12766 | ||
12767 | /* If this is not an ordinary function, the name usually comes from a | |
12768 | string literal or an sprintf buffer. Make sure we use the same | |
12769 | string consistently, so that cse will be able to unify address loads. */ | |
12770 | if (kind != FUNCTION_ORDINARY) | |
12771 | name = IDENTIFIER_POINTER (get_identifier (name)); | |
12772 | sym = gen_rtx_SYMBOL_REF (Pmode, name); | |
90534361 | 12773 | SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION; |
73a4d10b R |
12774 | if (flag_pic) |
12775 | switch (kind) | |
12776 | { | |
12777 | case FUNCTION_ORDINARY: | |
12778 | break; | |
12779 | case SFUNC_GOT: | |
12780 | { | |
12781 | rtx reg = target ? target : gen_reg_rtx (Pmode); | |
12782 | ||
12783 | emit_insn (gen_symGOT2reg (reg, sym)); | |
12784 | sym = reg; | |
12785 | break; | |
12786 | } | |
12787 | case SFUNC_STATIC: | |
12788 | { | |
12789 | /* ??? To allow cse to work, we use GOTOFF relocations. | |
50fe8924 | 12790 | We could add combiner patterns to transform this into |
73a4d10b R |
12791 | straight pc-relative calls with sym2PIC / bsrf when |
12792 | label load and function call are still 1:1 and in the | |
12793 | same basic block during combine. */ | |
12794 | rtx reg = target ? target : gen_reg_rtx (Pmode); | |
12795 | ||
12796 | emit_insn (gen_symGOTOFF2reg (reg, sym)); | |
12797 | sym = reg; | |
12798 | break; | |
12799 | } | |
12800 | } | |
12801 | if (target && sym != target) | |
12802 | { | |
12803 | emit_move_insn (target, sym); | |
12804 | return target; | |
12805 | } | |
90534361 R |
12806 | return sym; |
12807 | } | |
12808 | ||
fada1961 R |
12809 | /* Find the number of a general purpose register in S. */ |
12810 | static int | |
12811 | scavenge_reg (HARD_REG_SET *s) | |
12812 | { | |
12813 | int r; | |
12814 | for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++) | |
12815 | if (TEST_HARD_REG_BIT (*s, r)) | |
12816 | return r; | |
12817 | return -1; | |
12818 | } | |
12819 | ||
12820 | rtx | |
12821 | sh_get_pr_initial_val (void) | |
12822 | { | |
7d73a2ba R |
12823 | rtx val; |
12824 | ||
b869f904 R |
12825 | /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the |
12826 | PR register on SHcompact, because it might be clobbered by the prologue. | |
7d73a2ba | 12827 | We check first if that is known to be the case. */ |
b869f904 | 12828 | if (TARGET_SHCOMPACT |
38173d38 | 12829 | && ((crtl->args.info.call_cookie |
7d73a2ba | 12830 | & ~ CALL_COOKIE_RET_TRAMP (1)) |
e3b5732b | 12831 | || crtl->saves_all_registers)) |
57d38024 | 12832 | return gen_frame_mem (SImode, return_address_pointer_rtx); |
7d73a2ba R |
12833 | |
12834 | /* If we haven't finished rtl generation, there might be a nonlocal label | |
12835 | that we haven't seen yet. | |
b3a13419 ILT |
12836 | ??? get_hard_reg_initial_val fails if it is called after register |
12837 | allocation has started, unless it has been called before for the | |
12838 | same register. And even then, we end in trouble if we didn't use | |
12839 | the register in the same basic block before. So call | |
12840 | get_hard_reg_initial_val now and wrap it in an unspec if we might | |
12841 | need to replace it. */ | |
dce20bbc R |
12842 | /* ??? We also must do this for TARGET_SH1 in general, because otherwise |
12843 | combine can put the pseudo returned by get_hard_reg_initial_val into | |
12844 | instructions that need a general purpose registers, which will fail to | |
12845 | be recognized when the pseudo becomes allocated to PR. */ | |
7d73a2ba R |
12846 | val |
12847 | = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG); | |
dce20bbc | 12848 | if (TARGET_SH1) |
7d73a2ba R |
12849 | return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA); |
12850 | return val; | |
fada1961 R |
12851 | } |
12852 | ||
10c17a58 | 12853 | bool |
f90b7a5a | 12854 | sh_expand_t_scc (rtx operands[]) |
3db1b434 | 12855 | { |
f90b7a5a PB |
12856 | enum rtx_code code = GET_CODE (operands[1]); |
12857 | rtx target = operands[0]; | |
12858 | rtx op0 = operands[2]; | |
12859 | rtx op1 = operands[3]; | |
3db1b434 R |
12860 | rtx result = target; |
12861 | HOST_WIDE_INT val; | |
12862 | ||
f3536097 SZ |
12863 | if (!REG_P (op0) || REGNO (op0) != T_REG |
12864 | || !CONST_INT_P (op1)) | |
10c17a58 | 12865 | return false; |
f3536097 | 12866 | if (!REG_P (result)) |
3db1b434 | 12867 | result = gen_reg_rtx (SImode); |
f90b7a5a | 12868 | val = INTVAL (op1); |
3db1b434 | 12869 | if ((code == EQ && val == 1) || (code == NE && val == 0)) |
f031c344 | 12870 | emit_insn (gen_movt (result, get_t_reg_rtx ())); |
3db1b434 | 12871 | else if ((code == EQ && val == 0) || (code == NE && val == 1)) |
78ff60c1 | 12872 | emit_insn (gen_movnegt (result, get_t_reg_rtx ())); |
3db1b434 R |
12873 | else if (code == EQ || code == NE) |
12874 | emit_insn (gen_move_insn (result, GEN_INT (code == NE))); | |
12875 | else | |
10c17a58 | 12876 | return false; |
3db1b434 R |
12877 | if (result != target) |
12878 | emit_move_insn (target, result); | |
10c17a58 | 12879 | return true; |
3db1b434 R |
12880 | } |
12881 | ||
07d7d2f4 R |
12882 | /* INSN is an sfunc; return the rtx that describes the address used. */ |
12883 | static rtx | |
12884 | extract_sfunc_addr (rtx insn) | |
12885 | { | |
12886 | rtx pattern, part = NULL_RTX; | |
12887 | int len, i; | |
12888 | ||
12889 | pattern = PATTERN (insn); | |
12890 | len = XVECLEN (pattern, 0); | |
12891 | for (i = 0; i < len; i++) | |
12892 | { | |
12893 | part = XVECEXP (pattern, 0, i); | |
12894 | if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode | |
12895 | && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0)))) | |
12896 | return XEXP (part, 0); | |
12897 | } | |
f5b9e7c9 NS |
12898 | gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE); |
12899 | return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1); | |
07d7d2f4 R |
12900 | } |
12901 | ||
12902 | /* Verify that the register in use_sfunc_addr still agrees with the address | |
12903 | used in the sfunc. This prevents fill_slots_from_thread from changing | |
12904 | use_sfunc_addr. | |
12905 | INSN is the use_sfunc_addr instruction, and REG is the register it | |
12906 | guards. */ | |
aaf701c5 | 12907 | bool |
b32d5189 | 12908 | check_use_sfunc_addr (rtx_insn *insn, rtx reg) |
07d7d2f4 R |
12909 | { |
12910 | /* Search for the sfunc. It should really come right after INSN. */ | |
12911 | while ((insn = NEXT_INSN (insn))) | |
12912 | { | |
f3536097 | 12913 | if (LABEL_P (insn) || JUMP_P (insn)) |
07d7d2f4 R |
12914 | break; |
12915 | if (! INSN_P (insn)) | |
12916 | continue; | |
f676971a | 12917 | |
b32d5189 DM |
12918 | if (rtx_sequence *seq = dyn_cast<rtx_sequence *> (PATTERN (insn))) |
12919 | insn = seq->insn (0); | |
07d7d2f4 R |
12920 | if (GET_CODE (PATTERN (insn)) != PARALLEL |
12921 | || get_attr_type (insn) != TYPE_SFUNC) | |
12922 | continue; | |
12923 | return rtx_equal_p (extract_sfunc_addr (insn), reg); | |
12924 | } | |
f5b9e7c9 | 12925 | gcc_unreachable (); |
07d7d2f4 R |
12926 | } |
12927 | ||
db292b0e OE |
12928 | /* This function returns a constant rtx that represents 2**15 / pi in |
12929 | SFmode. It's used to scale a fixed-point signed 16.16-bit fraction | |
12930 | of a full circle back to an SFmode value, i.e. 0x10000 maps to 2*pi. */ | |
312209c6 AO |
12931 | static GTY(()) rtx sh_fsca_sf2int_rtx; |
12932 | ||
12933 | rtx | |
12934 | sh_fsca_sf2int (void) | |
12935 | { | |
12936 | if (! sh_fsca_sf2int_rtx) | |
12937 | { | |
12938 | REAL_VALUE_TYPE rv; | |
12939 | ||
12940 | real_from_string (&rv, "10430.378350470453"); | |
12941 | sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode); | |
12942 | } | |
12943 | ||
12944 | return sh_fsca_sf2int_rtx; | |
12945 | } | |
f676971a | 12946 | |
db292b0e OE |
12947 | /* This function returns a constant rtx that represents pi / 2**15 in |
12948 | SFmode. It's used to scale SFmode angles, in radians, to a | |
12949 | fixed-point signed 16.16-bit fraction of a full circle, i.e. 2*pi | |
12950 | maps to 0x10000. */ | |
312209c6 AO |
12951 | static GTY(()) rtx sh_fsca_int2sf_rtx; |
12952 | ||
12953 | rtx | |
12954 | sh_fsca_int2sf (void) | |
12955 | { | |
12956 | if (! sh_fsca_int2sf_rtx) | |
12957 | { | |
12958 | REAL_VALUE_TYPE rv; | |
12959 | ||
12960 | real_from_string (&rv, "9.587379924285257e-5"); | |
12961 | sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode); | |
12962 | } | |
12963 | ||
12964 | return sh_fsca_int2sf_rtx; | |
12965 | } | |
cc15e98f | 12966 | |
8b0add27 | 12967 | /* Initialize the CUMULATIVE_ARGS structure. */ |
cc15e98f NC |
12968 | void |
12969 | sh_init_cumulative_args (CUMULATIVE_ARGS * pcum, | |
50fe8924 | 12970 | tree fntype, |
cc15e98f | 12971 | rtx libname ATTRIBUTE_UNUSED, |
50fe8924 OE |
12972 | tree fndecl, |
12973 | signed int n_named_args, | |
ef4bddc2 | 12974 | machine_mode mode) |
cc15e98f NC |
12975 | { |
12976 | pcum->arg_count [(int) SH_ARG_FLOAT] = 0; | |
12977 | pcum->free_single_fp_reg = 0; | |
12978 | pcum->stack_regs = 0; | |
12979 | pcum->byref_regs = 0; | |
12980 | pcum->byref = 0; | |
12981 | pcum->outgoing = (n_named_args == -1) ? 0 : 1; | |
12982 | ||
12983 | /* XXX - Should we check TARGET_HITACHI here ??? */ | |
12984 | pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0; | |
12985 | ||
12986 | if (fntype) | |
12987 | { | |
12988 | pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi) | |
12989 | && aggregate_value_p (TREE_TYPE (fntype), fndecl)); | |
f4da8dce | 12990 | pcum->prototype_p = prototype_p (fntype); |
cc15e98f NC |
12991 | pcum->arg_count [(int) SH_ARG_INT] |
12992 | = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl); | |
12993 | ||
12994 | pcum->call_cookie | |
12995 | = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT | |
12996 | && pcum->arg_count [(int) SH_ARG_INT] == 0 | |
12997 | && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
12998 | ? int_size_in_bytes (TREE_TYPE (fntype)) | |
12999 | : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4 | |
13000 | && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype))) | |
13001 | == FIRST_RET_REG)); | |
13002 | } | |
13003 | else | |
13004 | { | |
13005 | pcum->arg_count [(int) SH_ARG_INT] = 0; | |
13006 | pcum->prototype_p = FALSE; | |
13007 | if (mode != VOIDmode) | |
13008 | { | |
29832164 | 13009 | pcum->call_cookie = |
cc15e98f NC |
13010 | CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT |
13011 | && GET_MODE_SIZE (mode) > 4 | |
13012 | && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG); | |
13013 | ||
13014 | /* If the default ABI is the Renesas ABI then all library | |
13015 | calls must assume that the library will be using the | |
13016 | Renesas ABI. So if the function would return its result | |
13017 | in memory then we must force the address of this memory | |
13018 | block onto the stack. Ideally we would like to call | |
13019 | targetm.calls.return_in_memory() here but we do not have | |
8b0add27 | 13020 | the TYPE or the FNDECL available so we synthesize the |
cc15e98f NC |
13021 | contents of that function as best we can. */ |
13022 | pcum->force_mem = | |
c0fb94d7 | 13023 | (TARGET_DEFAULT & MASK_HITACHI) |
cc15e98f NC |
13024 | && (mode == BLKmode |
13025 | || (GET_MODE_SIZE (mode) > 4 | |
13026 | && !(mode == DFmode | |
13027 | && TARGET_FPU_DOUBLE))); | |
13028 | } | |
13029 | else | |
13030 | { | |
13031 | pcum->call_cookie = 0; | |
13032 | pcum->force_mem = FALSE; | |
13033 | } | |
13034 | } | |
13035 | } | |
13036 | ||
73a4d10b | 13037 | rtx |
ef4bddc2 | 13038 | sh_gen_truncate (machine_mode mode, rtx x, int need_sign_ext) |
73a4d10b R |
13039 | { |
13040 | enum rtx_code code = TRUNCATE; | |
13041 | ||
13042 | if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
13043 | { | |
13044 | rtx inner = XEXP (x, 0); | |
ef4bddc2 | 13045 | machine_mode inner_mode = GET_MODE (inner); |
73a4d10b R |
13046 | |
13047 | if (inner_mode == mode) | |
13048 | return inner; | |
13049 | else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode)) | |
13050 | x = inner; | |
13051 | else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode) | |
13052 | && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND)) | |
13053 | { | |
13054 | code = GET_CODE (x); | |
13055 | x = inner; | |
13056 | } | |
13057 | } | |
13058 | return gen_rtx_fmt_e (code, mode, x); | |
13059 | } | |
13060 | ||
5dabe5a9 RS |
13061 | /* Look through X cleaning up truncates of registers that span multiple |
13062 | actual hard registers. Return the number of changes made. */ | |
73a4d10b | 13063 | int |
5dabe5a9 | 13064 | shmedia_cleanup_truncate (rtx x) |
73a4d10b | 13065 | { |
5dabe5a9 RS |
13066 | int n_changes = 0; |
13067 | subrtx_var_iterator::array_type array; | |
13068 | FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST) | |
73a4d10b | 13069 | { |
5dabe5a9 RS |
13070 | rtx x = *iter; |
13071 | if (GET_CODE (x) == TRUNCATE) | |
13072 | { | |
13073 | rtx reg = XEXP (x, 0); | |
ef4bddc2 | 13074 | machine_mode reg_mode = GET_MODE (reg); |
5dabe5a9 RS |
13075 | if (REG_P (reg) && GET_MODE_SIZE (reg_mode) > 8) |
13076 | { | |
13077 | int offset = subreg_lowpart_offset (DImode, reg_mode); | |
13078 | XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode, offset); | |
13079 | n_changes += 1; | |
13080 | iter.skip_subrtxes (); | |
13081 | } | |
13082 | } | |
73a4d10b | 13083 | } |
5dabe5a9 | 13084 | return n_changes; |
73a4d10b R |
13085 | } |
13086 | ||
13087 | /* Load and store depend on the highpart of the address. However, | |
13088 | set_attr_alternative does not give well-defined results before reload, | |
13089 | so we must look at the rtl ourselves to see if any of the feeding | |
50fe8924 | 13090 | registers is used in a memref. |
73a4d10b | 13091 | |
2caafc44 | 13092 | Return true iff INSN contains a MEM. */ |
aaf701c5 | 13093 | bool |
73a4d10b R |
13094 | sh_contains_memref_p (rtx insn) |
13095 | { | |
2caafc44 RS |
13096 | subrtx_iterator::array_type array; |
13097 | FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST) | |
13098 | if (MEM_P (*iter)) | |
13099 | return true; | |
13100 | return false; | |
73a4d10b R |
13101 | } |
13102 | ||
aaf701c5 OE |
13103 | /* Return true iff INSN loads a banked register. */ |
13104 | bool | |
5c7cafa8 CB |
13105 | sh_loads_bankedreg_p (rtx insn) |
13106 | { | |
13107 | if (GET_CODE (PATTERN (insn)) == SET) | |
13108 | { | |
13109 | rtx op = SET_DEST (PATTERN(insn)); | |
13110 | if (REG_P (op) && BANKED_REGISTER_P (REGNO (op))) | |
aaf701c5 | 13111 | return true; |
5c7cafa8 CB |
13112 | } |
13113 | ||
aaf701c5 | 13114 | return false; |
5c7cafa8 CB |
13115 | } |
13116 | ||
73a4d10b R |
13117 | /* FNADDR is the MEM expression from a call expander. Return an address |
13118 | to use in an SHmedia insn pattern. */ | |
13119 | rtx | |
13120 | shmedia_prepare_call_address (rtx fnaddr, int is_sibcall) | |
13121 | { | |
13122 | int is_sym; | |
13123 | ||
13124 | fnaddr = XEXP (fnaddr, 0); | |
13125 | is_sym = GET_CODE (fnaddr) == SYMBOL_REF; | |
13126 | if (flag_pic && is_sym) | |
13127 | { | |
13128 | if (! SYMBOL_REF_LOCAL_P (fnaddr)) | |
13129 | { | |
13130 | rtx reg = gen_reg_rtx (Pmode); | |
13131 | ||
13132 | /* We must not use GOTPLT for sibcalls, because PIC_REG | |
13133 | must be restored before the PLT code gets to run. */ | |
13134 | if (is_sibcall) | |
13135 | emit_insn (gen_symGOT2reg (reg, fnaddr)); | |
13136 | else | |
13137 | emit_insn (gen_symGOTPLT2reg (reg, fnaddr)); | |
13138 | fnaddr = reg; | |
13139 | } | |
13140 | else | |
13141 | { | |
13142 | fnaddr = gen_sym2PIC (fnaddr); | |
13143 | PUT_MODE (fnaddr, Pmode); | |
13144 | } | |
13145 | } | |
13146 | /* If ptabs might trap, make this visible to the rest of the compiler. | |
13147 | We generally assume that symbols pertain to valid locations, but | |
13148 | it is possible to generate invalid symbols with asm or linker tricks. | |
30dc60c7 | 13149 | In a list of functions where each returns its successor, an invalid |
73a4d10b R |
13150 | symbol might denote an empty list. */ |
13151 | if (!TARGET_PT_FIXED | |
13152 | && (!is_sym || TARGET_INVALID_SYMBOLS) | |
13153 | && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr)))) | |
13154 | { | |
13155 | rtx tr = gen_reg_rtx (PDImode); | |
13156 | ||
13157 | emit_insn (gen_ptabs (tr, fnaddr)); | |
13158 | fnaddr = tr; | |
13159 | } | |
13160 | else if (! target_reg_operand (fnaddr, Pmode)) | |
13161 | fnaddr = copy_to_mode_reg (Pmode, fnaddr); | |
13162 | return fnaddr; | |
13163 | } | |
13164 | ||
486b10aa | 13165 | /* Implement TARGET_PREFERRED_RELOAD_CLASS. */ |
486b10aa AS |
13166 | static reg_class_t |
13167 | sh_preferred_reload_class (rtx x, reg_class_t rclass) | |
13168 | { | |
13169 | if (rclass == NO_REGS | |
13170 | && TARGET_SHMEDIA | |
13171 | && (CONST_DOUBLE_P (x) | |
13172 | || GET_CODE (x) == SYMBOL_REF | |
13173 | || PIC_ADDR_P (x))) | |
13174 | return GENERAL_REGS; | |
13175 | ||
13176 | return rclass; | |
13177 | } | |
13178 | ||
13179 | /* Implement TARGET_SECONDARY_RELOAD. */ | |
486b10aa | 13180 | static reg_class_t |
a87cf97e | 13181 | sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, |
ef4bddc2 | 13182 | machine_mode mode, secondary_reload_info *sri) |
8a99f6f9 | 13183 | { |
a87cf97e JR |
13184 | enum reg_class rclass = (enum reg_class) rclass_i; |
13185 | ||
fce1e5fb OE |
13186 | if (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS |
13187 | && REG_P (XEXP (XEXP (x, 0), 0)) | |
13188 | && REGNO (XEXP (XEXP (x, 0), 0)) == GBR_REG) | |
13189 | return rclass == R0_REGS ? NO_REGS : R0_REGS; | |
13190 | ||
13191 | if (MEM_P (x) && REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == GBR_REG) | |
13192 | return rclass == R0_REGS ? NO_REGS : R0_REGS; | |
13193 | ||
13194 | if (REG_P (x) && REGNO (x) == GBR_REG) | |
13195 | return NO_REGS; | |
13196 | ||
8a99f6f9 R |
13197 | if (in_p) |
13198 | { | |
0a2aaacc | 13199 | if (REGCLASS_HAS_FP_REG (rclass) |
8a99f6f9 R |
13200 | && ! TARGET_SHMEDIA |
13201 | && immediate_operand ((x), mode) | |
ddfe2bdb | 13202 | && ! ((fp_zero_operand (x) || fp_one_operand (x)) && mode == SFmode)) |
8a99f6f9 R |
13203 | switch (mode) |
13204 | { | |
13205 | case SFmode: | |
13206 | sri->icode = CODE_FOR_reload_insf__frn; | |
13207 | return NO_REGS; | |
13208 | case DFmode: | |
13209 | sri->icode = CODE_FOR_reload_indf__frn; | |
13210 | return NO_REGS; | |
13211 | case SImode: | |
13212 | /* ??? If we knew that we are in the appropriate mode - | |
13213 | single precision - we could use a reload pattern directly. */ | |
13214 | return FPUL_REGS; | |
13215 | default: | |
13216 | abort (); | |
13217 | } | |
0a2aaacc | 13218 | if (rclass == FPUL_REGS |
50fe8924 OE |
13219 | && ((REG_P (x) && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG |
13220 | || REGNO (x) == T_REG)) | |
13221 | || GET_CODE (x) == PLUS)) | |
13222 | return GENERAL_REGS; | |
0a2aaacc | 13223 | if (rclass == FPUL_REGS && immediate_operand (x, mode)) |
8a99f6f9 | 13224 | { |
d973ac5a | 13225 | if (satisfies_constraint_I08 (x) || fp_zero_operand (x)) |
8a99f6f9 | 13226 | return GENERAL_REGS; |
d973ac5a KK |
13227 | else if (mode == SFmode) |
13228 | return FP_REGS; | |
8a99f6f9 R |
13229 | sri->icode = CODE_FOR_reload_insi__i_fpul; |
13230 | return NO_REGS; | |
13231 | } | |
0a2aaacc | 13232 | if (rclass == FPSCR_REGS |
50fe8924 OE |
13233 | && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER) |
13234 | || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS))) | |
8a99f6f9 | 13235 | return GENERAL_REGS; |
0a2aaacc | 13236 | if (REGCLASS_HAS_FP_REG (rclass) |
50fe8924 OE |
13237 | && TARGET_SHMEDIA |
13238 | && immediate_operand (x, mode) | |
13239 | && x != CONST0_RTX (GET_MODE (x)) | |
13240 | && GET_MODE (x) != V4SFmode) | |
13241 | return GENERAL_REGS; | |
8a99f6f9 | 13242 | if ((mode == QImode || mode == HImode) |
50fe8924 | 13243 | && TARGET_SHMEDIA && inqhi_operand (x, mode)) |
8a99f6f9 R |
13244 | { |
13245 | sri->icode = ((mode == QImode) | |
13246 | ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi); | |
13247 | return NO_REGS; | |
13248 | } | |
0a2aaacc | 13249 | if (TARGET_SHMEDIA && rclass == GENERAL_REGS |
50fe8924 OE |
13250 | && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x))) |
13251 | return TARGET_REGS; | |
8a99f6f9 R |
13252 | } /* end of input-only processing. */ |
13253 | ||
0a2aaacc | 13254 | if (((REGCLASS_HAS_FP_REG (rclass) |
f3536097 | 13255 | && (REG_P (x) |
8a99f6f9 R |
13256 | && (GENERAL_OR_AP_REGISTER_P (REGNO (x)) |
13257 | || (FP_REGISTER_P (REGNO (x)) && mode == SImode | |
13258 | && TARGET_FMOVD)))) | |
0a2aaacc | 13259 | || (REGCLASS_HAS_GENERAL_REG (rclass) |
f3536097 | 13260 | && REG_P (x) |
8a99f6f9 R |
13261 | && FP_REGISTER_P (REGNO (x)))) |
13262 | && ! TARGET_SHMEDIA | |
13263 | && (mode == SFmode || mode == SImode)) | |
13264 | return FPUL_REGS; | |
0a2aaacc KG |
13265 | if ((rclass == FPUL_REGS |
13266 | || (REGCLASS_HAS_FP_REG (rclass) | |
50fe8924 | 13267 | && ! TARGET_SHMEDIA && mode == SImode)) |
f3536097 | 13268 | && (MEM_P (x) |
50fe8924 OE |
13269 | || (REG_P (x) |
13270 | && (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
13271 | || REGNO (x) == T_REG | |
13272 | || system_reg_operand (x, VOIDmode))))) | |
8a99f6f9 | 13273 | { |
0a2aaacc | 13274 | if (rclass == FPUL_REGS) |
8a99f6f9 | 13275 | return GENERAL_REGS; |
fc1fcfa0 | 13276 | return NO_REGS; // LRA wants NO_REGS here, it used to be FPUL_REGS; |
8a99f6f9 | 13277 | } |
0a2aaacc KG |
13278 | if ((rclass == TARGET_REGS |
13279 | || (TARGET_SHMEDIA && rclass == SIBCALL_REGS)) | |
32a7ab3d | 13280 | && !satisfies_constraint_Csy (x) |
f3536097 | 13281 | && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x)))) |
8a99f6f9 | 13282 | return GENERAL_REGS; |
0a2aaacc | 13283 | if ((rclass == MAC_REGS || rclass == PR_REGS) |
f3536097 | 13284 | && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x)) |
0a2aaacc | 13285 | && rclass != REGNO_REG_CLASS (REGNO (x))) |
8a99f6f9 | 13286 | return GENERAL_REGS; |
f3536097 | 13287 | if (rclass != GENERAL_REGS && REG_P (x) |
8a99f6f9 R |
13288 | && TARGET_REGISTER_P (REGNO (x))) |
13289 | return GENERAL_REGS; | |
cebc182b OE |
13290 | |
13291 | /* If here fall back to loading FPUL register through general registers. | |
13292 | This case can happen when movsi_ie insn is picked initially to | |
13293 | load/store the FPUL register from/to another register, and then the | |
13294 | other register is allocated on the stack. */ | |
13295 | if (rclass == FPUL_REGS && true_regnum (x) == -1) | |
13296 | return GENERAL_REGS; | |
13297 | ||
8c2a3f3b OE |
13298 | /* Force mov.b / mov.w displacement addressing insn to use R0 as |
13299 | the other operand. | |
344332e8 OE |
13300 | On SH2A could also just leave it alone here, which would result in a |
13301 | 4 byte move insn being generated instead. However, for this to work | |
13302 | the insns must have the appropriate alternatives. */ | |
8c2a3f3b OE |
13303 | if ((mode == QImode || mode == HImode) && rclass != R0_REGS |
13304 | && satisfies_constraint_Sdd (x) | |
91f65b12 OE |
13305 | && sh_disp_addr_displacement (x) |
13306 | <= sh_max_mov_insn_displacement (mode, false)) | |
344332e8 OE |
13307 | return R0_REGS; |
13308 | ||
13309 | /* When reload is trying to address a QImode or HImode subreg on the stack, | |
13310 | force any subreg byte into R0_REGS, as this is going to become a | |
13311 | displacement address. | |
13312 | We could restrict this to SUBREG_BYTE (x) > 0, but if the actual reg | |
13313 | is on the stack, the memref to it might already require a displacement | |
13314 | and that has to be added to the final address. At this point we don't | |
13315 | know the cumulative displacement so we assume the worst case. */ | |
13316 | if ((mode == QImode || mode == HImode) && rclass != R0_REGS | |
13317 | && GET_CODE (x) == SUBREG && true_regnum (x) == -1) | |
13318 | return R0_REGS; | |
13319 | ||
8a99f6f9 R |
13320 | return NO_REGS; |
13321 | } | |
13322 | ||
d6220b11 KK |
13323 | /* Return true if SUBST can't safely replace its equivalent during RA. */ |
13324 | static bool | |
13325 | sh_cannot_substitute_mem_equiv_p (rtx) | |
13326 | { | |
13327 | if (TARGET_SHMEDIA) | |
13328 | return false; | |
13329 | ||
13330 | /* If SUBST is mem[base+index] or QI/HImode mem[base+disp], the insn | |
13331 | uses R0 and may cause spill failure when R0 is already used. | |
13332 | We have to return true for that case at least. | |
13333 | Moreover SH has strong R0 parity and also have not enough numbers of | |
13334 | the hard registers to make the equiv substitution win in the size | |
13335 | and the speed on average working sets. The pseudos produced to | |
13336 | hold the equiv values can't get good hard registers for bad cases | |
13337 | and end up memory save/restore insns which make the code worse. */ | |
13338 | return true; | |
13339 | } | |
13340 | ||
14133a4d KK |
13341 | /* Return true if DISP can be legitimized. */ |
13342 | static bool | |
13343 | sh_legitimize_address_displacement (rtx *disp, rtx *offs, | |
13344 | machine_mode mode) | |
13345 | { | |
13346 | if (TARGET_SHMEDIA) | |
13347 | return false; | |
13348 | ||
13349 | if (((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode) | |
13350 | || (TARGET_SH2E && mode == SFmode)) | |
13351 | return false; | |
13352 | ||
13353 | struct disp_adjust adj = sh_find_mov_disp_adjust (mode, INTVAL (*disp)); | |
13354 | if (adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX) | |
13355 | { | |
13356 | *disp = adj.mov_disp; | |
13357 | *offs = adj.offset_adjust; | |
13358 | return true; | |
13359 | } | |
13360 | ||
13361 | return false; | |
13362 | } | |
13363 | ||
6efc6b7f KK |
13364 | /* Return true if movsf insn should be splited with an additional |
13365 | register. */ | |
13366 | bool | |
13367 | sh_movsf_ie_ra_split_p (rtx op0, rtx op1, rtx op2) | |
13368 | { | |
13369 | /* op0 == op1 */ | |
13370 | if (rtx_equal_p (op0, op1)) | |
13371 | return true; | |
13372 | /* fy, FQ, reg */ | |
13373 | if (GET_CODE (op1) == CONST_DOUBLE | |
13374 | && ! satisfies_constraint_G (op1) | |
13375 | && ! satisfies_constraint_H (op1) | |
13376 | && REG_P (op0) | |
13377 | && REG_P (op2)) | |
13378 | return true; | |
13379 | /* f, r, y */ | |
13380 | if (REG_P (op0) && FP_REGISTER_P (REGNO (op0)) | |
13381 | && REG_P (op1) && GENERAL_REGISTER_P (REGNO (op1)) | |
13382 | && REG_P (op2) && (REGNO (op2) == FPUL_REG)) | |
13383 | return true; | |
13384 | /* r, f, y */ | |
13385 | if (REG_P (op1) && FP_REGISTER_P (REGNO (op1)) | |
13386 | && REG_P (op0) && GENERAL_REGISTER_P (REGNO (op0)) | |
13387 | && REG_P (op2) && (REGNO (op2) == FPUL_REG)) | |
13388 | return true; | |
13389 | ||
13390 | return false; | |
13391 | } | |
13392 | ||
5efd84c5 NF |
13393 | static void |
13394 | sh_conditional_register_usage (void) | |
13395 | { | |
13396 | int regno; | |
13397 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) | |
13398 | if (! VALID_REGISTER_P (regno)) | |
13399 | fixed_regs[regno] = call_used_regs[regno] = 1; | |
13400 | /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ | |
13401 | if (TARGET_SH5) | |
13402 | { | |
13403 | call_used_regs[FIRST_GENERAL_REG + 8] | |
13404 | = call_used_regs[FIRST_GENERAL_REG + 9] = 1; | |
13405 | call_really_used_regs[FIRST_GENERAL_REG + 8] | |
13406 | = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; | |
13407 | } | |
13408 | if (TARGET_SHMEDIA) | |
13409 | { | |
13410 | regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; | |
13411 | CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); | |
13412 | regno_reg_class[FIRST_FP_REG] = FP_REGS; | |
13413 | } | |
13414 | if (flag_pic) | |
13415 | { | |
13416 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
13417 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
13418 | } | |
13419 | /* Renesas saves and restores mac registers on call. */ | |
13420 | if (TARGET_HITACHI && ! TARGET_NOMACSAVE) | |
13421 | { | |
13422 | call_really_used_regs[MACH_REG] = 0; | |
13423 | call_really_used_regs[MACL_REG] = 0; | |
13424 | } | |
1818d01c | 13425 | |
5efd84c5 NF |
13426 | if (TARGET_SHMEDIA) |
13427 | { | |
13428 | for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++) | |
13429 | if (! fixed_regs[regno] && call_really_used_regs[regno]) | |
13430 | SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); | |
13431 | } | |
13432 | else | |
13433 | for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) | |
13434 | if (! fixed_regs[regno] && call_really_used_regs[regno]) | |
13435 | SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); | |
3a2317d1 OE |
13436 | |
13437 | call_really_used_regs[FPSCR_MODES_REG] = 0; | |
13438 | call_really_used_regs[FPSCR_STAT_REG] = 0; | |
5efd84c5 NF |
13439 | } |
13440 | ||
1a627b35 RS |
13441 | /* Implement TARGET_LEGITIMATE_CONSTANT_P |
13442 | ||
13443 | can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */ | |
1a627b35 | 13444 | static bool |
ef4bddc2 | 13445 | sh_legitimate_constant_p (machine_mode mode, rtx x) |
1a627b35 RS |
13446 | { |
13447 | return (TARGET_SHMEDIA | |
13448 | ? ((mode != DFmode && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT) | |
13449 | || x == CONST0_RTX (mode) | |
13450 | || !TARGET_SHMEDIA_FPU | |
13451 | || TARGET_SHMEDIA64) | |
13452 | : (GET_CODE (x) != CONST_DOUBLE | |
13453 | || mode == DFmode || mode == SFmode | |
13454 | || mode == DImode || GET_MODE (x) == VOIDmode)); | |
13455 | } | |
5efd84c5 | 13456 | |
73a4d10b R |
13457 | enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT; |
13458 | ||
dab37c68 RH |
13459 | static void |
13460 | sh_init_sync_libfuncs (void) | |
13461 | { | |
13462 | init_sync_libfuncs (UNITS_PER_WORD); | |
13463 | } | |
13464 | ||
fcf8632e CB |
13465 | /* Return true if it is appropriate to emit `ret' instructions in the |
13466 | body of a function. */ | |
fcf8632e CB |
13467 | bool |
13468 | sh_can_use_simple_return_p (void) | |
13469 | { | |
13470 | HARD_REG_SET live_regs_mask; | |
13471 | int d; | |
13472 | ||
7d9f9bd1 KK |
13473 | /* Some targets require special return insns. */ |
13474 | if (TARGET_SHMEDIA | |
13475 | || (TARGET_SHCOMPACT | |
13476 | && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1)))) | |
13477 | return false; | |
13478 | ||
fcf8632e CB |
13479 | if (! reload_completed || frame_pointer_needed) |
13480 | return false; | |
13481 | ||
13482 | /* Moving prologue around does't reduce the size. */ | |
13483 | if (optimize_function_for_size_p (cfun)) | |
13484 | return false; | |
13485 | ||
fcf8632e CB |
13486 | /* Finally, allow for pr save. */ |
13487 | d = calc_live_regs (&live_regs_mask); | |
13488 | ||
13489 | if (rounded_frame_size (d) > 4) | |
13490 | return false; | |
13491 | ||
13492 | return true; | |
fcf8632e CB |
13493 | } |
13494 | ||
fce1e5fb OE |
13495 | /*------------------------------------------------------------------------------ |
13496 | Address mode optimization support code | |
13497 | */ | |
13498 | ||
13499 | typedef HOST_WIDE_INT disp_t; | |
13500 | static const disp_t MIN_DISP = HOST_WIDE_INT_MIN; | |
13501 | static const disp_t MAX_DISP = HOST_WIDE_INT_MAX; | |
13502 | static const disp_t INVALID_DISP = MAX_DISP; | |
13503 | ||
13504 | /* A memory reference which is described by a base register and a | |
13505 | displacement. */ | |
13506 | class base_reg_disp | |
13507 | { | |
13508 | public: | |
13509 | base_reg_disp (rtx br, disp_t d); | |
13510 | ||
13511 | bool is_reg (void) const; | |
13512 | bool is_disp (void) const; | |
13513 | rtx reg (void) const; | |
13514 | disp_t disp (void) const; | |
13515 | ||
13516 | private: | |
13517 | rtx reg_; | |
13518 | disp_t disp_; | |
13519 | }; | |
13520 | ||
13521 | inline | |
13522 | base_reg_disp::base_reg_disp (rtx br, disp_t d) | |
13523 | : reg_ (br), disp_ (d) | |
13524 | { | |
13525 | } | |
13526 | ||
13527 | inline bool | |
13528 | base_reg_disp::is_reg (void) const | |
13529 | { | |
13530 | return reg_ != NULL_RTX && disp_ != INVALID_DISP; | |
13531 | } | |
13532 | ||
13533 | inline bool | |
13534 | base_reg_disp::is_disp (void) const | |
13535 | { | |
13536 | return reg_ == NULL_RTX && disp_ != INVALID_DISP; | |
13537 | } | |
13538 | ||
13539 | inline rtx | |
13540 | base_reg_disp::reg (void) const | |
13541 | { | |
13542 | return reg_; | |
13543 | } | |
13544 | ||
13545 | inline disp_t | |
13546 | base_reg_disp::disp (void) const | |
13547 | { | |
13548 | return disp_; | |
13549 | } | |
13550 | ||
13551 | /* Find the base register and calculate the displacement for a given | |
4eac9c2b | 13552 | address rtx 'x'. */ |
fce1e5fb | 13553 | static base_reg_disp |
4eac9c2b OE |
13554 | sh_find_base_reg_disp (rtx_insn* insn, rtx x, disp_t disp = 0, |
13555 | rtx base_reg = NULL) | |
fce1e5fb OE |
13556 | { |
13557 | if (REG_P (x)) | |
13558 | { | |
13559 | if (REGNO (x) == GBR_REG) | |
13560 | return base_reg_disp (x, disp); | |
13561 | ||
13562 | /* We've reached a hard-reg. This is probably the point where | |
13563 | function args are copied to pseudos. Do not go any further and | |
13564 | stick to the pseudo. If the original mem addr was in a hard reg | |
13565 | from the beginning, it will become the base reg. */ | |
13566 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
13567 | return base_reg_disp (base_reg != NULL ? base_reg : x, disp); | |
13568 | ||
4eac9c2b OE |
13569 | /* Find the def of the reg and trace it. If there are more than one |
13570 | defs and they are not the same, assume it's not safe to proceed. */ | |
13571 | rtx_insn* last_i = NULL; | |
13572 | rtx last_set = NULL; | |
13573 | for (df_ref d = DF_REG_DEF_CHAIN (REGNO (x)); d != NULL; | |
13574 | d = DF_REF_NEXT_REG (d)) | |
fce1e5fb | 13575 | { |
4eac9c2b | 13576 | rtx set = const_cast<rtx> (set_of (x, DF_REF_INSN (d))); |
fce1e5fb | 13577 | |
4eac9c2b OE |
13578 | /* Accept multiple defs, as long as they are equal. */ |
13579 | if (last_set == NULL || rtx_equal_p (last_set, set)) | |
13580 | { | |
13581 | last_i = DF_REF_INSN (d); | |
13582 | last_set = set; | |
13583 | } | |
13584 | else | |
fce1e5fb | 13585 | { |
4eac9c2b OE |
13586 | last_i = NULL; |
13587 | last_set = NULL; | |
13588 | break; | |
fce1e5fb OE |
13589 | } |
13590 | } | |
13591 | ||
4eac9c2b OE |
13592 | if (last_set != NULL && last_i != NULL) |
13593 | return sh_find_base_reg_disp (last_i, XEXP (last_set, 1), disp, | |
13594 | XEXP (last_set, 0)); | |
13595 | ||
13596 | /* When here, no previous insn was found that sets the reg. | |
13597 | The input reg is already the base reg. */ | |
13598 | return base_reg_disp (x, disp); | |
13599 | } | |
fce1e5fb OE |
13600 | |
13601 | else if (GET_CODE (x) == PLUS) | |
13602 | { | |
13603 | base_reg_disp left_val = sh_find_base_reg_disp (insn, XEXP (x, 0)); | |
13604 | base_reg_disp right_val = sh_find_base_reg_disp (insn, XEXP (x, 1)); | |
13605 | ||
13606 | /* Either left or right val must be a reg. | |
13607 | We don't handle the case of 'reg + reg' here. */ | |
13608 | if (left_val.is_reg () && right_val.is_disp ()) | |
13609 | return base_reg_disp (left_val.reg (), left_val.disp () | |
13610 | + right_val.disp () + disp); | |
13611 | else if (right_val.is_reg () && left_val.is_disp ()) | |
13612 | return base_reg_disp (right_val.reg (), right_val.disp () | |
13613 | + left_val.disp () + disp); | |
13614 | else | |
13615 | return base_reg_disp (base_reg, disp); | |
13616 | } | |
13617 | ||
13618 | else if (CONST_INT_P (x)) | |
13619 | return base_reg_disp (NULL, disp + INTVAL (x)); | |
13620 | ||
13621 | /* Didn't find anything useful. */ | |
13622 | return base_reg_disp (base_reg, disp); | |
13623 | } | |
13624 | ||
13625 | /* Given an insn and a memory operand, try to find an equivalent GBR | |
13626 | based memory address and return the corresponding new memory address. | |
13627 | Return NULL_RTX if not found. */ | |
13628 | rtx | |
4eac9c2b | 13629 | sh_find_equiv_gbr_addr (rtx_insn* insn, rtx mem) |
fce1e5fb | 13630 | { |
4eac9c2b | 13631 | if (!MEM_P (mem) || gbr_address_mem (mem, GET_MODE (mem))) |
fce1e5fb OE |
13632 | return NULL_RTX; |
13633 | ||
13634 | /* Leave post/pre inc/dec or any other side effect addresses alone. */ | |
13635 | if (side_effects_p (XEXP (mem, 0))) | |
13636 | return NULL_RTX; | |
13637 | ||
4eac9c2b OE |
13638 | /* When not optimizing there might be no dataflow available. */ |
13639 | if (df == NULL) | |
13640 | return NULL_RTX; | |
13641 | ||
fce1e5fb OE |
13642 | base_reg_disp gbr_disp = sh_find_base_reg_disp (insn, XEXP (mem, 0)); |
13643 | ||
13644 | if (gbr_disp.is_reg () && REGNO (gbr_disp.reg ()) == GBR_REG) | |
13645 | { | |
4eac9c2b OE |
13646 | /* If GBR is marked as call clobbered we bail out if we see a call. |
13647 | FIXME: Actually should check if this mem refers to the gbr value | |
13648 | before or after the call. If there is a store_gbr preceeding this | |
13649 | mem, it's safe to use GBR for this mem. | |
13650 | ||
13651 | If GBR is not marked as call clobbered, but there is some other | |
13652 | def than a call, it's probably a load_gbr upon which we also | |
13653 | bail out to be on the safe side. | |
13654 | FIXME: Should check if we have a use-after-def case, such as | |
13655 | the call case above. */ | |
13656 | for (df_ref d = DF_REG_DEF_CHAIN (GBR_REG); d != NULL; | |
13657 | d = DF_REF_NEXT_REG (d)) | |
13658 | { | |
13659 | if (CALL_P (DF_REF_INSN (d))) | |
13660 | { | |
13661 | if (REGNO_REG_SET_P (regs_invalidated_by_call_regset, GBR_REG)) | |
13662 | return NULL_RTX; | |
13663 | else | |
13664 | continue; | |
13665 | } | |
13666 | else | |
13667 | return NULL_RTX; | |
13668 | } | |
13669 | ||
fce1e5fb OE |
13670 | rtx disp = GEN_INT (gbr_disp.disp ()); |
13671 | if (gbr_displacement (disp, GET_MODE (mem))) | |
13672 | return gen_rtx_PLUS (SImode, gen_rtx_REG (SImode, GBR_REG), disp); | |
13673 | } | |
13674 | ||
13675 | return NULL_RTX; | |
13676 | } | |
13677 | ||
26943929 OE |
13678 | /*------------------------------------------------------------------------------ |
13679 | Manual insn combine support code. | |
13680 | */ | |
13681 | ||
9270a54f OE |
13682 | /* Return true if the specified insn contains any UNSPECs or |
13683 | UNSPEC_VOLATILEs. */ | |
13684 | static bool | |
b151091d | 13685 | sh_unspec_insn_p (rtx x) |
9270a54f | 13686 | { |
b151091d OE |
13687 | subrtx_iterator::array_type array; |
13688 | FOR_EACH_SUBRTX (i, array, x, ALL) | |
13689 | if (*i != NULL | |
13690 | && (GET_CODE (*i) == UNSPEC || GET_CODE (*i) == UNSPEC_VOLATILE)) | |
13691 | return true; | |
9270a54f | 13692 | |
b151091d | 13693 | return false; |
9270a54f OE |
13694 | } |
13695 | ||
13696 | /* Return true if the register operands of the specified insn are modified | |
13697 | between the specified from and to insns (exclusive of those two). */ | |
841dbf80 | 13698 | bool |
9270a54f OE |
13699 | sh_insn_operands_modified_between_p (rtx_insn* operands_insn, |
13700 | const rtx_insn* from, | |
13701 | const rtx_insn* to) | |
13702 | { | |
13703 | /* FIXME: Return true for multiple sets for now. */ | |
13704 | rtx s = single_set (operands_insn); | |
13705 | if (s == NULL_RTX) | |
13706 | return true; | |
13707 | ||
13708 | subrtx_iterator::array_type array; | |
13709 | FOR_EACH_SUBRTX (i, array, SET_SRC (s), ALL) | |
b151091d OE |
13710 | if (*i != NULL && |
13711 | ((REG_P (*i) || SUBREG_P (*i)) && reg_set_between_p (*i, from, to))) | |
9270a54f OE |
13712 | return true; |
13713 | ||
13714 | return false; | |
13715 | } | |
13716 | ||
841dbf80 OE |
13717 | /* Given an insn, determine whether it's a 'nott' insn, i.e. an insn that |
13718 | negates the T bit and stores the result in the T bit. */ | |
13719 | bool | |
13720 | sh_is_nott_insn (const rtx_insn* i) | |
13721 | { | |
13722 | return i != NULL && GET_CODE (PATTERN (i)) == SET | |
13723 | && t_reg_operand (XEXP (PATTERN (i), 0), VOIDmode) | |
13724 | && negt_reg_operand (XEXP (PATTERN (i), 1), VOIDmode); | |
13725 | } | |
13726 | ||
13727 | rtx | |
13728 | sh_movt_set_dest (const rtx_insn* i) | |
13729 | { | |
13730 | if (i == NULL) | |
13731 | return NULL; | |
13732 | ||
13733 | const_rtx p = PATTERN (i); | |
13734 | return GET_CODE (p) == SET | |
13735 | && arith_reg_dest (XEXP (p, 0), SImode) | |
13736 | && t_reg_operand (XEXP (p, 1), VOIDmode) ? XEXP (p, 0) : NULL; | |
13737 | } | |
13738 | ||
13739 | /* Given an insn, check whether it's a 'movrt' kind of insn, i.e. an insn | |
13740 | that stores the negated T bit in a register, and return the destination | |
13741 | register rtx, or null. */ | |
13742 | rtx | |
13743 | sh_movrt_set_dest (const rtx_insn* i) | |
13744 | { | |
13745 | if (i == NULL) | |
13746 | return NULL; | |
13747 | ||
13748 | const_rtx p = PATTERN (i); | |
13749 | ||
13750 | /* The negc movrt replacement is inside a parallel. */ | |
13751 | if (GET_CODE (p) == PARALLEL) | |
13752 | p = XVECEXP (p, 0, 0); | |
13753 | ||
13754 | return GET_CODE (p) == SET | |
13755 | && arith_reg_dest (XEXP (p, 0), SImode) | |
13756 | && negt_reg_operand (XEXP (p, 1), VOIDmode) ? XEXP (p, 0) : NULL; | |
13757 | } | |
13758 | ||
13759 | /* Given an insn and a reg number, tell whether the reg dies or is unused | |
13760 | after the insn. */ | |
13761 | bool | |
13762 | sh_reg_dead_or_unused_after_insn (const rtx_insn* i, int regno) | |
13763 | { | |
13764 | return find_regno_note (i, REG_DEAD, regno) != NULL | |
13765 | || find_regno_note (i, REG_UNUSED, regno) != NULL; | |
13766 | } | |
13767 | ||
83e3f98b OE |
13768 | /* Given an insn and a reg number, remove reg dead or reg unused notes to |
13769 | mark it as being used after the insn. */ | |
13770 | void | |
13771 | sh_remove_reg_dead_or_unused_notes (rtx_insn* i, int regno) | |
13772 | { | |
13773 | if (rtx n = find_regno_note (i, REG_DEAD, regno)) | |
13774 | remove_note (i, n); | |
13775 | if (rtx n = find_regno_note (i, REG_UNUSED, regno)) | |
13776 | remove_note (i, n); | |
13777 | } | |
13778 | ||
dac2637b OE |
13779 | /* Given an insn check if it contains any post/pre inc/dec mem operands and |
13780 | add the REG_INC notes accordingly. | |
13781 | FIXME: This function is very similar to lra.c (add_auto_inc_notes). | |
13782 | FIXME: This function is currently used by peephole2 patterns because | |
13783 | the peephole2 pass does not preserve REG_INC notes. If the notes | |
13784 | are dropped the following passes will do wrong things. */ | |
13785 | rtx_insn* | |
13786 | sh_check_add_incdec_notes (rtx_insn* i) | |
13787 | { | |
13788 | struct for_each_inc_dec_clb | |
13789 | { | |
13790 | static int func (rtx mem ATTRIBUTE_UNUSED, rtx op ATTRIBUTE_UNUSED, | |
13791 | rtx dest, rtx src ATTRIBUTE_UNUSED, | |
13792 | rtx srcoff ATTRIBUTE_UNUSED, void* arg) | |
13793 | { | |
13794 | gcc_assert (REG_P (dest)); | |
13795 | ||
13796 | rtx_insn* i = (rtx_insn*)arg; | |
13797 | if (find_regno_note (i, REG_INC, REGNO (dest)) == NULL) | |
13798 | add_reg_note (i, REG_INC, dest); | |
13799 | ||
13800 | return 0; | |
13801 | } | |
13802 | }; | |
13803 | ||
13804 | for_each_inc_dec (PATTERN (i), for_each_inc_dec_clb::func, i); | |
13805 | return i; | |
13806 | } | |
13807 | ||
26943929 OE |
13808 | /* Given an op rtx and an insn, try to find out whether the result of the |
13809 | specified op consists only of logical operations on T bit stores. */ | |
13810 | bool | |
355e9975 | 13811 | sh_is_logical_t_store_expr (rtx op, rtx_insn* insn) |
26943929 OE |
13812 | { |
13813 | if (!logical_operator (op, SImode)) | |
13814 | return false; | |
13815 | ||
13816 | rtx ops[2] = { XEXP (op, 0), XEXP (op, 1) }; | |
13817 | int op_is_t_count = 0; | |
13818 | ||
13819 | for (int i = 0; i < 2; ++i) | |
13820 | { | |
13821 | if (t_reg_operand (ops[i], VOIDmode) | |
13822 | || negt_reg_operand (ops[i], VOIDmode)) | |
13823 | op_is_t_count++; | |
13824 | ||
13825 | else | |
13826 | { | |
13827 | set_of_reg op_set = sh_find_set_of_reg (ops[i], insn, | |
13828 | prev_nonnote_insn_bb); | |
13829 | if (op_set.set_src == NULL_RTX) | |
13830 | continue; | |
13831 | ||
13832 | if (t_reg_operand (op_set.set_src, VOIDmode) | |
13833 | || negt_reg_operand (op_set.set_src, VOIDmode) | |
13834 | || sh_is_logical_t_store_expr (op_set.set_src, op_set.insn)) | |
13835 | op_is_t_count++; | |
13836 | } | |
13837 | } | |
13838 | ||
13839 | return op_is_t_count == 2; | |
13840 | } | |
13841 | ||
13842 | /* Given the operand that is extended in a sign/zero extend insn, and the | |
13843 | insn, try to figure out whether the sign/zero extension can be replaced | |
13844 | by a simple reg-reg copy. If so, the replacement reg rtx is returned, | |
13845 | NULL_RTX otherwise. */ | |
13846 | rtx | |
355e9975 | 13847 | sh_try_omit_signzero_extend (rtx extended_op, rtx_insn* insn) |
26943929 OE |
13848 | { |
13849 | if (REG_P (extended_op)) | |
13850 | extended_op = extended_op; | |
13851 | else if (GET_CODE (extended_op) == SUBREG && REG_P (SUBREG_REG (extended_op))) | |
13852 | extended_op = SUBREG_REG (extended_op); | |
13853 | else | |
13854 | return NULL_RTX; | |
13855 | ||
13856 | /* Reg moves must be of the same mode. */ | |
13857 | if (GET_MODE (extended_op) != SImode) | |
13858 | return NULL_RTX; | |
13859 | ||
13860 | set_of_reg s = sh_find_set_of_reg (extended_op, insn, prev_nonnote_insn_bb); | |
13861 | if (s.set_src == NULL_RTX) | |
13862 | return NULL_RTX; | |
13863 | ||
13864 | if (t_reg_operand (s.set_src, VOIDmode) | |
13865 | || negt_reg_operand (s.set_src, VOIDmode)) | |
13866 | return extended_op; | |
13867 | ||
13868 | /* If the zero extended reg was formed by a logical operation, check the | |
13869 | operands of the logical operation. If both originated from T bit | |
13870 | stores the zero extension can be eliminated. */ | |
13871 | else if (sh_is_logical_t_store_expr (s.set_src, s.insn)) | |
13872 | return extended_op; | |
13873 | ||
13874 | return NULL_RTX; | |
13875 | } | |
13876 | ||
355e9975 OE |
13877 | /* Given the current insn, which is assumed to be a movrt_negc insn, try to |
13878 | figure out whether it should be converted into a movt-xor sequence in | |
13879 | the movrt_negc splitter. | |
13880 | Returns true if insns have been modified and the splitter has succeeded. */ | |
13881 | bool | |
13882 | sh_split_movrt_negc_to_movt_xor (rtx_insn* curr_insn, rtx operands[]) | |
13883 | { | |
13884 | /* In cases such as | |
13885 | tst r4,r4 | |
13886 | mov #-1,r1 | |
13887 | negc r1,r1 | |
13888 | tst r4,r4 | |
13889 | we can replace the T bit clobbering negc with a movt-xor sequence and | |
13890 | eliminate the redundant comparison. | |
13891 | Because the xor insn depends on register allocation results, allow this | |
13892 | only before reload. */ | |
13893 | if (!can_create_pseudo_p ()) | |
13894 | return false; | |
13895 | ||
13896 | set_of_reg t_before_negc = sh_find_set_of_reg (get_t_reg_rtx (), curr_insn, | |
13897 | prev_nonnote_insn_bb); | |
13898 | set_of_reg t_after_negc = sh_find_set_of_reg (get_t_reg_rtx (), curr_insn, | |
13899 | next_nonnote_insn_bb); | |
13900 | ||
13901 | if (t_before_negc.set_rtx != NULL_RTX && t_after_negc.set_rtx != NULL_RTX | |
13902 | && rtx_equal_p (t_before_negc.set_rtx, t_after_negc.set_rtx) | |
9270a54f OE |
13903 | && !reg_used_between_p (get_t_reg_rtx (), curr_insn, t_after_negc.insn) |
13904 | && !sh_insn_operands_modified_between_p (t_before_negc.insn, | |
13905 | t_before_negc.insn, | |
13906 | t_after_negc.insn) | |
13907 | && !sh_unspec_insn_p (t_after_negc.insn) | |
13908 | && !volatile_insn_p (PATTERN (t_after_negc.insn)) | |
13909 | && !side_effects_p (PATTERN (t_after_negc.insn)) | |
13910 | && !may_trap_or_fault_p (PATTERN (t_after_negc.insn))) | |
355e9975 OE |
13911 | { |
13912 | emit_insn (gen_movrt_xor (operands[0], get_t_reg_rtx ())); | |
13913 | set_insn_deleted (t_after_negc.insn); | |
13914 | return true; | |
13915 | } | |
13916 | else | |
13917 | return false; | |
13918 | } | |
13919 | ||
83e3f98b OE |
13920 | /* Given a reg and the current insn, see if the value of the reg originated |
13921 | from a sign or zero extension and return the discovered information. */ | |
13922 | sh_extending_set_of_reg | |
13923 | sh_find_extending_set_of_reg (rtx reg, rtx_insn* curr_insn) | |
13924 | { | |
13925 | if (reg == NULL) | |
13926 | return sh_extending_set_of_reg (curr_insn); | |
13927 | ||
13928 | if (SUBREG_P (reg)) | |
13929 | reg = SUBREG_REG (reg); | |
13930 | ||
13931 | if (!REG_P (reg)) | |
13932 | return sh_extending_set_of_reg (curr_insn); | |
13933 | ||
13934 | /* FIXME: Also search the predecessor basic blocks. It seems that checking | |
13935 | only the adjacent predecessor blocks would cover most of the cases. | |
13936 | Also try to look through the first extension that we hit. There are some | |
13937 | cases, where a zero_extend is followed an (implicit) sign_extend, and it | |
13938 | fails to see the sign_extend. */ | |
13939 | sh_extending_set_of_reg result = | |
13940 | sh_find_set_of_reg (reg, curr_insn, prev_nonnote_insn_bb, true); | |
13941 | ||
13942 | if (result.set_src != NULL) | |
13943 | { | |
13944 | if (GET_CODE (result.set_src) == SIGN_EXTEND | |
13945 | || GET_CODE (result.set_src) == ZERO_EXTEND) | |
13946 | { | |
13947 | if (dump_file) | |
b151091d | 13948 | fprintf (dump_file, "sh_find_extending_set_of_reg: reg %d is " |
83e3f98b OE |
13949 | "explicitly sign/zero extended in insn %d\n", |
13950 | REGNO (reg), INSN_UID (result.insn)); | |
13951 | result.from_mode = GET_MODE (XEXP (result.set_src, 0)); | |
13952 | result.ext_code = GET_CODE (result.set_src); | |
13953 | } | |
13954 | else if (MEM_P (result.set_src) | |
13955 | && (GET_MODE (result.set_src) == QImode | |
b151091d OE |
13956 | || GET_MODE (result.set_src) == HImode) |
13957 | && !sh_unspec_insn_p (result.insn)) | |
83e3f98b OE |
13958 | { |
13959 | /* On SH QIHImode memory loads always sign extend. However, in | |
13960 | some cases where it seems that the higher bits are not | |
13961 | interesting, the loads will not be expanded as sign extending | |
13962 | insns, but as QIHImode loads into QIHImode regs. We report that | |
13963 | the reg has been sign extended by the mem load. When it is used | |
13964 | as such, we must convert the mem load into a sign extending insn, | |
13965 | see also sh_extending_set_of_reg::use_as_extended_reg. */ | |
13966 | if (dump_file) | |
13967 | fprintf (dump_file, "sh_find_extending_set_of_reg: reg %d is " | |
13968 | "implicitly sign extended in insn %d\n", | |
13969 | REGNO (reg), INSN_UID (result.insn)); | |
13970 | result.from_mode = GET_MODE (result.set_src); | |
13971 | result.ext_code = SIGN_EXTEND; | |
13972 | } | |
13973 | } | |
13974 | ||
13975 | return result; | |
13976 | } | |
13977 | ||
13978 | /* Given a reg that is known to be sign or zero extended at some insn, | |
13979 | take the appropriate measures so that the extended value can be used as | |
13980 | a reg at the specified insn and return the resulting reg rtx. */ | |
13981 | rtx | |
13982 | sh_extending_set_of_reg::use_as_extended_reg (rtx_insn* use_at_insn) const | |
13983 | { | |
13984 | gcc_assert (insn != NULL && set_src != NULL && set_rtx != NULL); | |
13985 | gcc_assert (ext_code == SIGN_EXTEND || ext_code == ZERO_EXTEND); | |
13986 | gcc_assert (from_mode == QImode || from_mode == HImode); | |
13987 | ||
13988 | if (MEM_P (set_src) && ext_code == SIGN_EXTEND) | |
13989 | { | |
13990 | if (dump_file) | |
13991 | fprintf (dump_file, | |
13992 | "use_as_extended_reg: converting non-extending mem load in " | |
13993 | "insn %d into sign-extending load\n", INSN_UID (insn)); | |
13994 | ||
13995 | rtx r = gen_reg_rtx (SImode); | |
13996 | rtx_insn* i0; | |
13997 | if (from_mode == QImode) | |
13998 | i0 = emit_insn_after (gen_extendqisi2 (r, set_src), insn); | |
13999 | else if (from_mode == HImode) | |
14000 | i0 = emit_insn_after (gen_extendhisi2 (r, set_src), insn); | |
14001 | else | |
14002 | gcc_unreachable (); | |
14003 | ||
14004 | emit_insn_after ( | |
14005 | gen_move_insn (XEXP (set_rtx, 0), | |
14006 | gen_lowpart (GET_MODE (set_src), r)), i0); | |
14007 | set_insn_deleted (insn); | |
14008 | return r; | |
14009 | } | |
14010 | else | |
14011 | { | |
14012 | rtx extension_dst = XEXP (set_rtx, 0); | |
14013 | if (modified_between_p (extension_dst, insn, use_at_insn)) | |
14014 | { | |
14015 | if (dump_file) | |
14016 | fprintf (dump_file, | |
14017 | "use_as_extended_reg: dest reg %d of extending insn %d is " | |
14018 | "modified, inserting a reg-reg copy\n", | |
14019 | REGNO (extension_dst), INSN_UID (insn)); | |
14020 | ||
14021 | rtx r = gen_reg_rtx (SImode); | |
14022 | emit_insn_after (gen_move_insn (r, extension_dst), insn); | |
14023 | return r; | |
14024 | } | |
14025 | else | |
14026 | { | |
14027 | sh_remove_reg_dead_or_unused_notes (insn, REGNO (extension_dst)); | |
14028 | return extension_dst; | |
14029 | } | |
14030 | } | |
14031 | } | |
14032 | ||
841dbf80 OE |
14033 | bool |
14034 | sh_extending_set_of_reg::can_use_as_unextended_reg (void) const | |
14035 | { | |
14036 | if ((ext_code == SIGN_EXTEND || ext_code == ZERO_EXTEND) | |
14037 | && (from_mode == QImode || from_mode == HImode) | |
14038 | && set_src != NULL) | |
14039 | return arith_reg_operand (XEXP (set_src, 0), from_mode); | |
14040 | else | |
14041 | return false; | |
14042 | } | |
14043 | ||
14044 | rtx | |
14045 | sh_extending_set_of_reg::use_as_unextended_reg (rtx_insn* use_at_insn) const | |
14046 | { | |
14047 | gcc_assert (can_use_as_unextended_reg ()); | |
14048 | ||
14049 | rtx r = XEXP (set_src, 0); | |
14050 | rtx r0 = simplify_gen_subreg (SImode, r, from_mode, 0); | |
14051 | ||
14052 | if (modified_between_p (r, insn, use_at_insn)) | |
14053 | { | |
14054 | rtx r1 = gen_reg_rtx (SImode); | |
14055 | emit_insn_after (gen_move_insn (r1, r0), insn); | |
14056 | return r1; | |
14057 | } | |
14058 | else | |
14059 | { | |
14060 | sh_remove_reg_dead_or_unused_notes (insn, SUBREG_P (r) | |
14061 | ? REGNO (SUBREG_REG (r)) | |
14062 | : REGNO (r)); | |
14063 | return r0; | |
14064 | } | |
14065 | } | |
14066 | ||
83e3f98b OE |
14067 | /* Given the current insn, which is assumed to be the *tst<mode>_t_subregs insn, |
14068 | perform the necessary checks on the operands and split it accordingly. */ | |
14069 | void | |
14070 | sh_split_tst_subregs (rtx_insn* curr_insn, machine_mode subreg_mode, | |
14071 | int subreg_offset, rtx operands[]) | |
14072 | { | |
14073 | gcc_assert (subreg_mode == QImode || subreg_mode == HImode); | |
14074 | ||
14075 | sh_extending_set_of_reg eop0 = sh_find_extending_set_of_reg (operands[0], | |
14076 | curr_insn); | |
14077 | sh_extending_set_of_reg eop1 = sh_find_extending_set_of_reg (operands[1], | |
14078 | curr_insn); | |
14079 | ||
14080 | /* If one of the operands is known to be zero extended, that's already | |
14081 | sufficient to mask out the unwanted high bits. */ | |
14082 | if (eop0.ext_code == ZERO_EXTEND && eop0.from_mode == subreg_mode) | |
14083 | { | |
14084 | emit_insn (gen_tstsi_t (eop0.use_as_extended_reg (curr_insn), | |
14085 | operands[1])); | |
14086 | return; | |
14087 | } | |
14088 | if (eop1.ext_code == ZERO_EXTEND && eop1.from_mode == subreg_mode) | |
14089 | { | |
14090 | emit_insn (gen_tstsi_t (operands[0], | |
14091 | eop1.use_as_extended_reg (curr_insn))); | |
14092 | return; | |
14093 | } | |
14094 | ||
14095 | /* None of the operands seem to be zero extended. | |
14096 | If both are sign extended it's OK, too. */ | |
14097 | if (eop0.ext_code == SIGN_EXTEND && eop1.ext_code == SIGN_EXTEND | |
14098 | && eop0.from_mode == subreg_mode && eop1.from_mode == subreg_mode) | |
14099 | { | |
14100 | emit_insn (gen_tstsi_t (eop0.use_as_extended_reg (curr_insn), | |
14101 | eop1.use_as_extended_reg (curr_insn))); | |
14102 | return; | |
14103 | } | |
14104 | ||
14105 | /* Otherwise we have to insert a zero extension on one of the operands to | |
14106 | mask out the unwanted high bits. | |
14107 | Prefer the operand that has no known extension. */ | |
14108 | if (eop0.ext_code != UNKNOWN && eop1.ext_code == UNKNOWN) | |
14109 | std::swap (operands[0], operands[1]); | |
14110 | ||
14111 | rtx tmp0 = gen_reg_rtx (SImode); | |
14112 | rtx tmp1 = simplify_gen_subreg (subreg_mode, operands[0], | |
14113 | GET_MODE (operands[0]), subreg_offset); | |
14114 | emit_insn (subreg_mode == QImode | |
14115 | ? gen_zero_extendqisi2 (tmp0, tmp1) | |
14116 | : gen_zero_extendhisi2 (tmp0, tmp1)); | |
14117 | emit_insn (gen_tstsi_t (tmp0, operands[1])); | |
14118 | } | |
14119 | ||
841dbf80 OE |
14120 | /* A helper class to increment/decrement a counter variable each time a |
14121 | function is entered/left. */ | |
14122 | class scope_counter | |
14123 | { | |
14124 | public: | |
14125 | scope_counter (int& counter) : m_counter (counter) { ++m_counter; } | |
14126 | ||
14127 | ~scope_counter (void) | |
14128 | { | |
14129 | --m_counter; | |
14130 | gcc_assert (m_counter >= 0); | |
14131 | } | |
14132 | ||
14133 | int count (void) const { return m_counter; } | |
14134 | ||
14135 | private: | |
14136 | int& m_counter; | |
14137 | }; | |
14138 | ||
14139 | /* Given an rtx x, determine whether the expression can be used to create | |
14140 | an insn that calulates x and stores the result in the T bit. | |
14141 | This is used by the 'treg_set_expr' predicate to construct insns sequences | |
14142 | where T bit results are fed into other insns, such as addc, subc, negc | |
14143 | insns. | |
14144 | ||
14145 | FIXME: The patterns that expand 'treg_set_expr' operands tend to | |
14146 | distinguish between 'positive' and 'negative' forms. For now this has to | |
14147 | be done in the preparation code. We could also introduce | |
14148 | 'pos_treg_set_expr' and 'neg_treg_set_expr' predicates for that and write | |
14149 | two different patterns for the 'postive' and 'negative' forms. However, | |
14150 | the total amount of lines of code seems to be about the same and the | |
14151 | '{pos|neg}_treg_set_expr' predicates would be more expensive, because the | |
14152 | recog function would need to look inside the expression by temporarily | |
14153 | splitting it. */ | |
14154 | static int sh_recog_treg_set_expr_reent_count = 0; | |
14155 | ||
14156 | bool | |
14157 | sh_recog_treg_set_expr (rtx op, machine_mode mode) | |
14158 | { | |
14159 | scope_counter recursion (sh_recog_treg_set_expr_reent_count); | |
14160 | ||
14161 | /* Limit the recursion count to avoid nested expressions which we can't | |
14162 | resolve to a single treg set insn. */ | |
14163 | if (recursion.count () > 1) | |
14164 | return false; | |
14165 | ||
14166 | /* Early accept known possible operands before doing recog. */ | |
14167 | if (op == const0_rtx || op == const1_rtx || t_reg_operand (op, mode)) | |
14168 | return true; | |
14169 | ||
14170 | /* Early reject impossible operands before doing recog. | |
14171 | There are some (set ((t) (subreg ...))) patterns, but we must be careful | |
14172 | not to allow any invalid reg-reg or mem-reg moves, or else other passes | |
14173 | such as lower-subreg will bail out. Some insns such as SH4A movua are | |
14174 | done with UNSPEC, so must reject those, too, or else it would result | |
14175 | in an invalid reg -> treg move. */ | |
14176 | if (register_operand (op, mode) || memory_operand (op, mode) | |
14177 | || sh_unspec_insn_p (op)) | |
14178 | return false; | |
14179 | ||
14180 | if (!can_create_pseudo_p ()) | |
14181 | return false; | |
14182 | ||
14183 | /* We are going to invoke recog in a re-entrant way and thus | |
14184 | have to capture its current state and restore it afterwards. */ | |
14185 | recog_data_d prev_recog_data = recog_data; | |
14186 | ||
f7df4a84 | 14187 | rtx_insn* i = make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), op)); |
841dbf80 OE |
14188 | SET_PREV_INSN (i) = NULL; |
14189 | SET_NEXT_INSN (i) = NULL; | |
14190 | ||
14191 | int result = recog (PATTERN (i), i, 0); | |
14192 | ||
14193 | /* It seems there is no insn like that. Create a simple negated | |
14194 | version and try again. If we hit a negated form, we'll allow that | |
14195 | and append a nott sequence when splitting out the insns. Insns that | |
14196 | do the split can then remove the trailing nott if they know how to | |
14197 | deal with it. */ | |
14198 | if (result < 0 && GET_CODE (op) == EQ) | |
14199 | { | |
14200 | PUT_CODE (op, NE); | |
14201 | result = recog (PATTERN (i), i, 0); | |
14202 | PUT_CODE (op, EQ); | |
14203 | } | |
14204 | if (result < 0 && GET_CODE (op) == NE) | |
14205 | { | |
14206 | PUT_CODE (op, EQ); | |
14207 | result = recog (PATTERN (i), i, 0); | |
14208 | PUT_CODE (op, NE); | |
14209 | } | |
14210 | ||
14211 | recog_data = prev_recog_data; | |
14212 | return result >= 0; | |
14213 | } | |
14214 | ||
14215 | /* Returns true when recog of a 'treg_set_expr' is currently in progress. | |
14216 | This can be used as a condition for insn/split patterns to allow certain | |
14217 | T bit setting patters only to be matched as sub expressions of other | |
14218 | patterns. */ | |
14219 | bool | |
14220 | sh_in_recog_treg_set_expr (void) | |
14221 | { | |
14222 | return sh_recog_treg_set_expr_reent_count > 0; | |
14223 | } | |
14224 | ||
14225 | /* Given an rtx x, which is assumed to be some expression that has been | |
14226 | matched by the 'treg_set_expr' predicate before, split and emit the | |
14227 | insns that are necessary to calculate the expression and store the result | |
14228 | in the T bit. | |
14229 | The splitting is done recursively similar to 'try_split' in emit-rt.c. | |
14230 | Unfortunately we can't use 'try_split' here directly, as it tries to invoke | |
14231 | 'delete_insn' which then causes the DF parts to bail out, because we | |
14232 | currently are inside another gen_split* function and would invoke | |
14233 | 'try_split' in a reentrant way. */ | |
14234 | static std::pair<rtx_insn*, rtx_insn*> | |
14235 | sh_try_split_insn_simple (rtx_insn* i, rtx_insn* curr_insn, int n = 0) | |
14236 | { | |
14237 | if (dump_file) | |
14238 | { | |
14239 | fprintf (dump_file, "sh_try_split_insn_simple n = %d i = \n", n); | |
14240 | print_rtl_single (dump_file, i); | |
14241 | fprintf (dump_file, "\n"); | |
14242 | } | |
14243 | ||
bb5c4956 | 14244 | rtx_insn* seq = split_insns (PATTERN (i), curr_insn); |
841dbf80 OE |
14245 | |
14246 | if (seq == NULL) | |
14247 | return std::make_pair (i, i); | |
14248 | ||
14249 | /* Avoid infinite splitter loops if any insn of the result matches | |
14250 | the original pattern. */ | |
14251 | for (rtx_insn* s = seq; s != NULL; s = NEXT_INSN (s)) | |
14252 | if (INSN_P (s) && rtx_equal_p (PATTERN (s), PATTERN (i))) | |
14253 | return std::make_pair (i, i); | |
14254 | ||
14255 | unshare_all_rtl_in_chain (seq); | |
14256 | ||
14257 | /* 'seq' is now a replacement for 'i'. Assuming that 'i' is an insn in | |
14258 | a linked list, replace the single insn with the new insns. */ | |
14259 | rtx_insn* seqlast = seq; | |
14260 | while (NEXT_INSN (seqlast) != NULL) | |
14261 | seqlast = NEXT_INSN (seqlast); | |
14262 | ||
14263 | if (rtx_insn* iprev = PREV_INSN (i)) | |
14264 | SET_NEXT_INSN (iprev) = seq; | |
14265 | if (rtx_insn* inext = NEXT_INSN (i)) | |
14266 | SET_PREV_INSN (inext) = seqlast; | |
14267 | ||
14268 | SET_PREV_INSN (seq) = PREV_INSN (i); | |
14269 | SET_NEXT_INSN (seqlast) = NEXT_INSN (i); | |
14270 | ||
14271 | SET_PREV_INSN (i) = NULL; | |
14272 | SET_NEXT_INSN (i) = NULL; | |
14273 | ||
14274 | /* Recursively split all insns. */ | |
14275 | for (i = seq; ; i = NEXT_INSN (i)) | |
14276 | { | |
14277 | std::pair<rtx_insn*, rtx_insn*> ii = | |
14278 | sh_try_split_insn_simple (i, curr_insn, n + 1); | |
14279 | if (i == seq) | |
14280 | seq = ii.first; | |
14281 | if (i == seqlast) | |
14282 | { | |
14283 | seqlast = ii.second; | |
14284 | break; | |
14285 | } | |
14286 | i = ii.first; | |
14287 | } | |
14288 | ||
14289 | return std::make_pair (seq, seqlast); | |
14290 | } | |
14291 | ||
14292 | sh_treg_insns | |
14293 | sh_split_treg_set_expr (rtx x, rtx_insn* curr_insn) | |
14294 | { | |
14295 | if (t_reg_operand (x, VOIDmode)) | |
14296 | return sh_treg_insns (); | |
14297 | ||
14298 | scope_counter in_treg_set_expr (sh_recog_treg_set_expr_reent_count); | |
14299 | ||
f7df4a84 | 14300 | rtx_insn* i = make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), x)); |
841dbf80 OE |
14301 | SET_PREV_INSN (i) = NULL; |
14302 | SET_NEXT_INSN (i) = NULL; | |
14303 | ||
14304 | if (dump_file) | |
14305 | { | |
14306 | fprintf (dump_file, "split_treg_set_expr insn:\n"); | |
14307 | print_rtl (dump_file, i); | |
14308 | fprintf (dump_file, "\n"); | |
14309 | } | |
14310 | ||
14311 | /* We are going to invoke recog/split_insns in a re-entrant way and thus | |
14312 | have to capture its current state and restore it afterwards. */ | |
14313 | recog_data_d prev_recog_data = recog_data; | |
14314 | ||
14315 | int insn_code = recog (PATTERN (i), i, 0); | |
14316 | ||
14317 | /* If the insn was not found, see if we matched the negated form before | |
14318 | and append a nott. */ | |
14319 | bool append_nott = false; | |
14320 | ||
14321 | if (insn_code < 0 && GET_CODE (x) == EQ) | |
14322 | { | |
14323 | PUT_CODE (x, NE); | |
14324 | insn_code = recog (PATTERN (i), i, 0); | |
14325 | if (insn_code >= 0) | |
14326 | append_nott = true; | |
14327 | else | |
14328 | PUT_CODE (x, EQ); | |
14329 | } | |
14330 | if (insn_code < 0 && GET_CODE (x) == NE) | |
14331 | { | |
14332 | PUT_CODE (x, EQ); | |
14333 | insn_code = recog (PATTERN (i), i, 0); | |
14334 | if (insn_code >= 0) | |
14335 | append_nott = true; | |
14336 | else | |
14337 | PUT_CODE (x, NE); | |
14338 | } | |
14339 | ||
14340 | gcc_assert (insn_code >= 0); | |
14341 | ||
14342 | /* Try to recursively split the insn. Some insns might refuse to split | |
14343 | any further while we are in the treg_set_expr splitting phase. They | |
14344 | will be emitted as part of the outer insn and then split again. */ | |
14345 | std::pair<rtx_insn*, rtx_insn*> insnlist = | |
14346 | sh_try_split_insn_simple (i, curr_insn); | |
14347 | ||
14348 | /* Restore recog state. */ | |
14349 | recog_data = prev_recog_data; | |
14350 | ||
14351 | rtx_insn* nott_insn = sh_is_nott_insn (insnlist.second) | |
14352 | ? insnlist.second | |
14353 | : NULL; | |
14354 | if (dump_file) | |
14355 | { | |
14356 | fprintf (dump_file, "split_treg_set_expr insnlist:\n"); | |
14357 | print_rtl (dump_file, insnlist.first); | |
14358 | fprintf (dump_file, "\n"); | |
14359 | ||
14360 | if (nott_insn != NULL) | |
14361 | fprintf (dump_file, "trailing nott insn %d\n", INSN_UID (nott_insn)); | |
14362 | } | |
14363 | ||
48e4f473 OE |
14364 | emit_insn (insnlist.first); |
14365 | ||
841dbf80 OE |
14366 | if (nott_insn != NULL && append_nott) |
14367 | { | |
14368 | if (dump_file) | |
14369 | fprintf (dump_file, "removing trailing nott\n"); | |
14370 | remove_insn (nott_insn); | |
14371 | nott_insn = NULL; | |
14372 | append_nott = false; | |
14373 | } | |
14374 | ||
841dbf80 OE |
14375 | if (append_nott) |
14376 | nott_insn = emit_insn (gen_nott (get_t_reg_rtx ())); | |
14377 | ||
14378 | rtx_insn* first_insn = get_insns (); | |
14379 | ||
14380 | if (dump_file) | |
14381 | { | |
14382 | fprintf (dump_file, "resulting insns:\n"); | |
14383 | print_rtl (dump_file, first_insn); | |
14384 | fprintf (dump_file, "\n"); | |
14385 | } | |
14386 | ||
14387 | return sh_treg_insns (first_insn, nott_insn); | |
14388 | } | |
14389 | ||
83e3f98b OE |
14390 | /*------------------------------------------------------------------------------ |
14391 | Mode switching support code. | |
14392 | */ | |
14393 | ||
06b90602 CB |
14394 | static void |
14395 | sh_emit_mode_set (int entity ATTRIBUTE_UNUSED, int mode, | |
3a2317d1 | 14396 | int prev_mode, HARD_REG_SET regs_live ATTRIBUTE_UNUSED) |
06b90602 | 14397 | { |
cbb1e3d9 CB |
14398 | if ((TARGET_SH4A_FP || TARGET_SH4_300) |
14399 | && prev_mode != FP_MODE_NONE && prev_mode != mode) | |
14400 | { | |
14401 | emit_insn (gen_toggle_pr ()); | |
14402 | if (TARGET_FMOVD) | |
14403 | emit_insn (gen_toggle_sz ()); | |
14404 | } | |
3a2317d1 OE |
14405 | else if (mode != FP_MODE_NONE) |
14406 | { | |
fe3e478f OE |
14407 | rtx tmp = gen_reg_rtx (SImode); |
14408 | emit_insn (gen_sts_fpscr (tmp)); | |
3a2317d1 OE |
14409 | rtx i = NULL; |
14410 | ||
14411 | const unsigned HOST_WIDE_INT fpbits = | |
14412 | TARGET_FMOVD ? (FPSCR_PR | FPSCR_SZ) : FPSCR_PR; | |
14413 | ||
14414 | if (prev_mode != FP_MODE_NONE && prev_mode != mode) | |
fe3e478f | 14415 | i = gen_xorsi3 (tmp, tmp, force_reg (SImode, GEN_INT (fpbits))); |
3a2317d1 | 14416 | else if (mode == FP_MODE_SINGLE) |
fe3e478f | 14417 | i = gen_andsi3 (tmp, tmp, force_reg (SImode, GEN_INT (~fpbits))); |
3a2317d1 | 14418 | else if (mode == FP_MODE_DOUBLE) |
fe3e478f | 14419 | i = gen_iorsi3 (tmp, tmp, force_reg (SImode, GEN_INT (fpbits))); |
3a2317d1 OE |
14420 | else |
14421 | gcc_unreachable (); | |
14422 | ||
14423 | emit_insn (i); | |
fe3e478f | 14424 | emit_insn (gen_lds_fpscr (tmp)); |
3a2317d1 | 14425 | } |
06b90602 CB |
14426 | } |
14427 | ||
14428 | static int | |
ac44248e | 14429 | sh_mode_needed (int entity ATTRIBUTE_UNUSED, rtx_insn *insn) |
06b90602 CB |
14430 | { |
14431 | return recog_memoized (insn) >= 0 ? get_attr_fp_mode (insn) : FP_MODE_NONE; | |
14432 | } | |
14433 | ||
14434 | static int | |
ac44248e | 14435 | sh_mode_after (int entity ATTRIBUTE_UNUSED, int mode, rtx_insn *insn) |
06b90602 CB |
14436 | { |
14437 | if (TARGET_HITACHI && recog_memoized (insn) >= 0 && | |
14438 | get_attr_fp_set (insn) != FP_SET_NONE) | |
14439 | return (int) get_attr_fp_set (insn); | |
14440 | else | |
14441 | return mode; | |
14442 | } | |
14443 | ||
14444 | static int | |
14445 | sh_mode_entry (int entity ATTRIBUTE_UNUSED) | |
14446 | { | |
14447 | return NORMAL_MODE (entity); | |
14448 | } | |
14449 | ||
14450 | static int | |
14451 | sh_mode_exit (int entity ATTRIBUTE_UNUSED) | |
14452 | { | |
14453 | return sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (entity); | |
14454 | } | |
14455 | ||
14456 | static int | |
14457 | sh_mode_priority (int entity ATTRIBUTE_UNUSED, int n) | |
14458 | { | |
14459 | return ((TARGET_FPU_SINGLE != 0) ^ (n) ? FP_MODE_SINGLE : FP_MODE_DOUBLE); | |
14460 | } | |
14461 | ||
83e3f98b OE |
14462 | /*------------------------------------------------------------------------------ |
14463 | Misc | |
14464 | */ | |
14465 | ||
106a52b7 KK |
14466 | /* Return true if we use LRA instead of reload pass. */ |
14467 | static bool | |
14468 | sh_lra_p (void) | |
14469 | { | |
14470 | return sh_lra_flag; | |
14471 | } | |
14472 | ||
ae59bd31 JG |
14473 | /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */ |
14474 | ||
14475 | static bool | |
445d7826 | 14476 | sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size, |
ae59bd31 JG |
14477 | unsigned int align, |
14478 | enum by_pieces_operation op, | |
14479 | bool speed_p) | |
14480 | { | |
14481 | switch (op) | |
14482 | { | |
14483 | case MOVE_BY_PIECES: | |
14484 | return move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1) | |
14485 | < (!speed_p ? 2 : (align >= 32) ? 16 : 2); | |
14486 | case STORE_BY_PIECES: | |
14487 | case SET_BY_PIECES: | |
14488 | return move_by_pieces_ninsns (size, align, STORE_MAX_PIECES + 1) | |
14489 | < (!speed_p ? 2 : (align >= 32) ? 16 : 2); | |
14490 | default: | |
14491 | return default_use_by_pieces_infrastructure_p (size, align, | |
14492 | op, speed_p); | |
14493 | } | |
14494 | } | |
14495 | ||
e2500fed | 14496 | #include "gt-sh.h" |