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c8f0269d | 1 | /* Output routines for GCC for Renesas / SuperH SH. |
cbe34bb5 | 2 | Copyright (C) 1993-2017 Free Software Foundation, Inc. |
c5c76735 | 3 | Contributed by Steve Chamberlain (sac@cygnus.com). |
f676971a | 4 | Improved by Jim Wilson (wilson@cygnus.com). |
bc45ade3 | 5 | |
7ec022b2 | 6 | This file is part of GCC. |
c15c9075 | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
c15c9075 | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
c15c9075 RK |
11 | any later version. |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
c15c9075 RK |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
bc45ade3 | 21 | |
0bcf70f8 | 22 | #include <sstream> |
0bcf70f8 | 23 | |
bc45ade3 | 24 | #include "config.h" |
2c384ad8 | 25 | #define INCLUDE_VECTOR |
c5c76735 | 26 | #include "system.h" |
4977bab6 | 27 | #include "coretypes.h" |
c7131fb2 | 28 | #include "backend.h" |
e11c4407 AM |
29 | #include "target.h" |
30 | #include "rtl.h" | |
c7131fb2 AM |
31 | #include "tree.h" |
32 | #include "gimple.h" | |
e11c4407 | 33 | #include "cfghooks.h" |
c7131fb2 | 34 | #include "df.h" |
4d0cdd0c | 35 | #include "memmodel.h" |
e11c4407 AM |
36 | #include "tm_p.h" |
37 | #include "stringpool.h" | |
2643d17f | 38 | #include "attribs.h" |
e11c4407 AM |
39 | #include "optabs.h" |
40 | #include "emit-rtl.h" | |
41 | #include "recog.h" | |
42 | #include "diagnostic-core.h" | |
40e23961 | 43 | #include "alias.h" |
40e23961 | 44 | #include "fold-const.h" |
d8a2d370 DN |
45 | #include "stor-layout.h" |
46 | #include "calls.h" | |
47 | #include "varasm.h" | |
bc45ade3 | 48 | #include "flags.h" |
36566b39 | 49 | #include "explow.h" |
bc45ade3 | 50 | #include "expr.h" |
6f50eb9c | 51 | #include "reload.h" |
8aa2a305 | 52 | #include "output.h" |
956a5206 | 53 | #include "insn-attr.h" |
a80b0574 | 54 | #include "dwarf2.h" |
c1b92d09 | 55 | #include "langhooks.h" |
60393bbc | 56 | #include "cfgrtl.h" |
bcc8cc82 | 57 | #include "intl.h" |
58565a33 | 58 | #include "sched-int.h" |
45b0be94 | 59 | #include "gimplify.h" |
32a7ab3d | 60 | #include "tm-constrs.h" |
96e45421 | 61 | #include "opts.h" |
5d30dc5b | 62 | #include "tree-pass.h" |
5d30dc5b | 63 | #include "context.h" |
9b2b7279 | 64 | #include "builtins.h" |
5dabe5a9 | 65 | #include "rtl-iter.h" |
a93072ca | 66 | #include "regs.h" |
5fac2ed2 | 67 | |
994c5d85 | 68 | /* This file should be included last. */ |
d58627a0 RS |
69 | #include "target-def.h" |
70 | ||
1245df60 R |
71 | int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch; |
72 | ||
e1fab8ba OE |
73 | #define CONST_OK_FOR_ADD(size) CONST_OK_FOR_I08 (size) |
74 | #define GEN_MOV (*(gen_movsi)) | |
75 | #define GEN_ADD3 (*(gen_addsi3)) | |
76 | #define GEN_SUB3 (*(gen_subsi3)) | |
fa5322fa | 77 | |
561642fa AP |
78 | /* Used to simplify the logic below. Find the attributes wherever |
79 | they may be. */ | |
80 | #define SH_ATTRIBUTES(decl) \ | |
81 | (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \ | |
82 | : DECL_ATTRIBUTES (decl) \ | |
83 | ? (DECL_ATTRIBUTES (decl)) \ | |
84 | : TYPE_ATTRIBUTES (TREE_TYPE (decl)) | |
85 | ||
df4bacab OE |
86 | /* Set to true by expand_prologue() when the function is an |
87 | interrupt handler. */ | |
88 | bool current_function_interrupt; | |
552ecbd9 | 89 | |
a6ab9fc0 R |
90 | tree sh_deferred_function_attributes; |
91 | tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes; | |
16bea517 | 92 | |
6f317ef3 | 93 | /* Global variables for machine-dependent things. */ |
bc45ade3 | 94 | |
16bea517 JW |
95 | /* Which cpu are we scheduling for. */ |
96 | enum processor_type sh_cpu; | |
97 | ||
58565a33 SKG |
98 | /* Definitions used in ready queue reordering for first scheduling pass. */ |
99 | ||
100 | /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */ | |
101 | static short *regmode_weight[2]; | |
102 | ||
103 | /* Total SFmode and SImode weights of scheduled insns. */ | |
104 | static int curr_regmode_pressure[2]; | |
105 | ||
6fb5fa3c DB |
106 | /* Number of r0 life regions. */ |
107 | static int r0_life_regions; | |
108 | ||
58565a33 SKG |
109 | /* If true, skip cycles for Q -> R movement. */ |
110 | static int skip_cycles = 0; | |
111 | ||
50fe8924 | 112 | /* Cached value of can_issue_more. This is cached in sh_variable_issue hook |
58565a33 SKG |
113 | and returned from sh_reorder2. */ |
114 | static short cached_can_issue_more; | |
115 | ||
826159e5 KK |
116 | /* Unique number for UNSPEC_BBR pattern. */ |
117 | static unsigned int unspec_bbr_uid = 1; | |
118 | ||
bc45ade3 | 119 | /* Provides the class number of the smallest class containing |
16bea517 | 120 | reg number. */ |
fada1961 | 121 | enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] = |
bc45ade3 | 122 | { |
8e87e161 | 123 | R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, |
bc45ade3 SC |
124 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, |
125 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
126 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
fa5322fa AO |
127 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, |
128 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
129 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
130 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
131 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
132 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
133 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
134 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
135 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
136 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
137 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
138 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
1a95a963 JW |
139 | FP0_REGS,FP_REGS, FP_REGS, FP_REGS, |
140 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
141 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
142 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
fa5322fa AO |
143 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, |
144 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
145 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
146 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
147 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
148 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
149 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
150 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
151 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
152 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
153 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
154 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
155 | TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS, | |
156 | TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS, | |
225e4f43 R |
157 | DF_REGS, DF_REGS, DF_REGS, DF_REGS, |
158 | DF_REGS, DF_REGS, DF_REGS, DF_REGS, | |
fa5322fa AO |
159 | NO_REGS, GENERAL_REGS, PR_REGS, T_REGS, |
160 | MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS, | |
96a2347e | 161 | GENERAL_REGS, GENERAL_REGS, |
225e4f43 R |
162 | }; |
163 | ||
fa5322fa AO |
164 | char sh_register_names[FIRST_PSEUDO_REGISTER] \ |
165 | [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER; | |
166 | ||
167 | char sh_additional_register_names[ADDREGNAMES_SIZE] \ | |
168 | [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1] | |
169 | = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER; | |
bc45ade3 | 170 | |
225e4f43 R |
171 | int assembler_dialect; |
172 | ||
6cb7eb41 | 173 | static void split_branches (rtx_insn *); |
cf277499 | 174 | static int branch_dest (rtx); |
7fa55ff6 | 175 | static void print_slot (rtx_sequence *); |
ef4bddc2 | 176 | static rtx_code_label *add_constant (rtx, machine_mode, rtx); |
6cb7eb41 DM |
177 | static void dump_table (rtx_insn *, rtx_insn *); |
178 | static bool broken_move (rtx_insn *); | |
179 | static bool mova_p (rtx_insn *); | |
180 | static rtx_insn *find_barrier (int, rtx_insn *, rtx_insn *); | |
e8a54173 | 181 | static bool noncall_uses_reg (rtx, rtx_insn *, rtx *); |
b32d5189 | 182 | static rtx_insn *gen_block_redirect (rtx_insn *, int, int); |
cf277499 | 183 | static void sh_reorg (void); |
e7a8f681 | 184 | static void sh_option_override (void); |
4c221995 | 185 | static void sh_override_options_after_change (void); |
21d05694 | 186 | static void output_stack_adjust (int, rtx, int, HARD_REG_SET *, bool); |
df4bacab | 187 | static rtx_insn* emit_frame_insn (rtx); |
cf277499 SB |
188 | static rtx push (int); |
189 | static void pop (int); | |
df4bacab | 190 | static void push_regs (HARD_REG_SET* mask, bool interrupt_handler); |
cf277499 | 191 | static int calc_live_regs (HARD_REG_SET *); |
cf277499 | 192 | static HOST_WIDE_INT rounded_frame_size (int); |
7a296495 | 193 | static bool sh_frame_pointer_required (void); |
cbb1e3d9 | 194 | static void sh_emit_mode_set (int, int, int, HARD_REG_SET); |
ac44248e DM |
195 | static int sh_mode_needed (int, rtx_insn *); |
196 | static int sh_mode_after (int, int, rtx_insn *); | |
06b90602 CB |
197 | static int sh_mode_entry (int); |
198 | static int sh_mode_exit (int); | |
199 | static int sh_mode_priority (int entity, int n); | |
200 | ||
cf277499 | 201 | static rtx mark_constant_pool_use (rtx); |
50fe8924 OE |
202 | static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, |
203 | int, bool *); | |
561642fa AP |
204 | static tree sh_handle_resbank_handler_attribute (tree *, tree, |
205 | tree, int, bool *); | |
206 | static tree sh2a_handle_function_vector_handler_attribute (tree *, tree, | |
207 | tree, int, bool *); | |
cf277499 SB |
208 | static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *); |
209 | static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *); | |
210 | static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *); | |
9e94b957 | 211 | static void sh_print_operand (FILE *, rtx, int); |
cc8ca59e | 212 | static void sh_print_operand_address (FILE *, machine_mode, rtx); |
9e94b957 | 213 | static bool sh_print_operand_punct_valid_p (unsigned char code); |
ef875e12 | 214 | static bool sh_asm_output_addr_const_extra (FILE *file, rtx x); |
42776416 | 215 | static void sh_output_function_epilogue (FILE *); |
cf277499 | 216 | static void sh_insert_attributes (tree, tree *); |
8d932be3 | 217 | static const char *sh_check_pch_target_flags (int); |
ef4bddc2 | 218 | static int sh_register_move_cost (machine_mode, reg_class_t, reg_class_t); |
b505225b | 219 | static int sh_adjust_cost (rtx_insn *, int, rtx_insn *, int, unsigned int); |
cf277499 | 220 | static int sh_issue_rate (void); |
ac44248e | 221 | static int sh_dfa_new_cycle (FILE *, int, rtx_insn *, int, int, int *sort_p); |
ef4bddc2 RS |
222 | static short find_set_regmode_weight (rtx, machine_mode); |
223 | static short find_insn_regmode_weight (rtx, machine_mode); | |
224 | static void find_regmode_weight (basic_block, machine_mode); | |
6fb5fa3c | 225 | static int find_r0_life_regions (basic_block); |
58565a33 SKG |
226 | static void sh_md_init_global (FILE *, int, int); |
227 | static void sh_md_finish_global (FILE *, int); | |
228 | static int rank_for_reorder (const void *, const void *); | |
ce1ce33a DM |
229 | static void swap_reorder (rtx_insn **, int); |
230 | static void ready_reorder (rtx_insn **, int); | |
ef4bddc2 | 231 | static bool high_pressure (machine_mode); |
ce1ce33a DM |
232 | static int sh_reorder (FILE *, int, rtx_insn **, int *, int); |
233 | static int sh_reorder2 (FILE *, int, rtx_insn **, int *, int); | |
58565a33 | 234 | static void sh_md_init (FILE *, int, int); |
ac44248e | 235 | static int sh_variable_issue (FILE *, int, rtx_insn *, int); |
f676971a | 236 | |
cf277499 SB |
237 | static bool sh_function_ok_for_sibcall (tree, tree); |
238 | ||
cf6186e9 | 239 | static bool sh_can_follow_jump (const rtx_insn *, const rtx_insn *); |
3101faab | 240 | static bool sh_ms_bitfield_layout_p (const_tree); |
cf277499 SB |
241 | |
242 | static void sh_init_builtins (void); | |
1cc24576 | 243 | static tree sh_builtin_decl (unsigned, bool); |
ef4bddc2 | 244 | static rtx sh_expand_builtin (tree, rtx, rtx, machine_mode, int); |
50fe8924 OE |
245 | static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
246 | HOST_WIDE_INT, tree); | |
cf277499 | 247 | static void sh_file_start (void); |
1e44e857 | 248 | static bool sh_assemble_integer (rtx, unsigned int, int); |
aaf701c5 | 249 | static bool flow_dependent_p (rtx, rtx); |
7bc980e1 | 250 | static void flow_dependent_p_1 (rtx, const_rtx, void *); |
cf277499 | 251 | static int shiftcosts (rtx); |
6ff9d294 | 252 | static int and_xor_ior_costs (rtx, int); |
cf277499 SB |
253 | static int addsubcosts (rtx); |
254 | static int multcosts (rtx); | |
255 | static bool unspec_caller_rtx_p (rtx); | |
ac44248e | 256 | static bool sh_cannot_copy_insn_p (rtx_insn *); |
1e44e857 | 257 | static bool sh_cannot_force_const_mem_p (machine_mode, rtx); |
e548c9df | 258 | static bool sh_rtx_costs (rtx, machine_mode, int, int, int *, bool); |
ef4bddc2 | 259 | static int sh_address_cost (rtx, machine_mode, addr_space_t, bool); |
b48f503c KK |
260 | static int sh_pr_n_sets (void); |
261 | static rtx sh_allocate_initial_value (rtx); | |
486b10aa AS |
262 | static reg_class_t sh_preferred_reload_class (rtx, reg_class_t); |
263 | static reg_class_t sh_secondary_reload (bool, rtx, reg_class_t, | |
ef4bddc2 | 264 | machine_mode, |
486b10aa | 265 | struct secondary_reload_info *); |
ef4bddc2 RS |
266 | static bool sh_legitimate_address_p (machine_mode, rtx, bool); |
267 | static rtx sh_legitimize_address (rtx, rtx, machine_mode); | |
90833f7f | 268 | static rtx sh_delegitimize_address (rtx); |
d6220b11 | 269 | static bool sh_cannot_substitute_mem_equiv_p (rtx); |
14133a4d | 270 | static bool sh_legitimize_address_displacement (rtx *, rtx *, machine_mode); |
fada1961 | 271 | static int scavenge_reg (HARD_REG_SET *s); |
61f71b34 | 272 | |
cf277499 | 273 | static rtx sh_struct_value_rtx (tree, int); |
d64728cf | 274 | static rtx sh_function_value (const_tree, const_tree, bool); |
e7a8f681 | 275 | static bool sh_function_value_regno_p (const unsigned int); |
ef4bddc2 | 276 | static rtx sh_libcall_value (machine_mode, const_rtx); |
586de218 | 277 | static bool sh_return_in_memory (const_tree, const_tree); |
cf277499 | 278 | static rtx sh_builtin_saveregs (void); |
ef4bddc2 | 279 | static void sh_setup_incoming_varargs (cumulative_args_t, machine_mode, |
50fe8924 | 280 | tree, int *, int); |
d5cc9181 JR |
281 | static bool sh_strict_argument_naming (cumulative_args_t); |
282 | static bool sh_pretend_outgoing_varargs_named (cumulative_args_t); | |
801881b0 | 283 | static void sh_atomic_assign_expand_fenv (tree *, tree *, tree *); |
c35d187f | 284 | static tree sh_build_builtin_va_list (void); |
d7bd8aeb | 285 | static void sh_va_start (tree, rtx); |
726a989a | 286 | static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *); |
d64728cf | 287 | static bool sh_promote_prototypes (const_tree); |
ef4bddc2 RS |
288 | static machine_mode sh_promote_function_mode (const_tree type, |
289 | machine_mode, | |
d055ce45 KK |
290 | int *punsignedp, |
291 | const_tree funtype, | |
6e957ac8 | 292 | int for_return); |
ef4bddc2 | 293 | static bool sh_pass_by_reference (cumulative_args_t, machine_mode, |
586de218 | 294 | const_tree, bool); |
ef4bddc2 | 295 | static bool sh_callee_copies (cumulative_args_t, machine_mode, |
586de218 | 296 | const_tree, bool); |
ef4bddc2 | 297 | static int sh_arg_partial_bytes (cumulative_args_t, machine_mode, |
78a52f11 | 298 | tree, bool); |
ef4bddc2 | 299 | static void sh_function_arg_advance (cumulative_args_t, machine_mode, |
b64336b8 | 300 | const_tree, bool); |
ef4bddc2 | 301 | static rtx sh_function_arg (cumulative_args_t, machine_mode, |
b64336b8 | 302 | const_tree, bool); |
3101faab | 303 | static int sh_dwarf_calling_convention (const_tree); |
561642fa | 304 | static void sh_encode_section_info (tree, rtx, int); |
aaf701c5 | 305 | static bool sh2a_function_vector_p (tree); |
994322ef RH |
306 | static void sh_trampoline_init (rtx, tree, rtx); |
307 | static rtx sh_trampoline_adjust_address (rtx); | |
5efd84c5 | 308 | static void sh_conditional_register_usage (void); |
ef4bddc2 RS |
309 | static bool sh_legitimate_constant_p (machine_mode, rtx); |
310 | static int mov_insn_size (machine_mode, bool); | |
311 | static int mov_insn_alignment_mask (machine_mode, bool); | |
445d7826 | 312 | static bool sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT, |
ae59bd31 JG |
313 | unsigned int, |
314 | enum by_pieces_operation, | |
315 | bool); | |
b32d5189 | 316 | static bool sequence_insn_p (rtx_insn *); |
c354951b AK |
317 | static void sh_canonicalize_comparison (int *, rtx *, rtx *, bool); |
318 | static void sh_canonicalize_comparison (enum rtx_code&, rtx&, rtx&, | |
ef4bddc2 | 319 | machine_mode, bool); |
841dbf80 OE |
320 | static bool sh_legitimate_combined_insn (rtx_insn* insn); |
321 | ||
5d30dc5b | 322 | static bool sh_fixed_condition_code_regs (unsigned int* p1, unsigned int* p2); |
dab37c68 RH |
323 | |
324 | static void sh_init_sync_libfuncs (void) ATTRIBUTE_UNUSED; | |
c43f4279 | 325 | static unsigned int sh_hard_regno_nregs (unsigned int, machine_mode); |
f939c3e6 | 326 | static bool sh_hard_regno_mode_ok (unsigned int, machine_mode); |
99e1629f | 327 | static bool sh_modes_tieable_p (machine_mode, machine_mode); |
0d803030 | 328 | static bool sh_can_change_mode_class (machine_mode, machine_mode, reg_class_t); |
5a82ecd9 ILT |
329 | \f |
330 | static const struct attribute_spec sh_attribute_table[] = | |
331 | { | |
62d784f7 KT |
332 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
333 | affects_type_identity } */ | |
334 | { "interrupt_handler", 0, 0, true, false, false, | |
335 | sh_handle_interrupt_handler_attribute, false }, | |
336 | { "sp_switch", 1, 1, true, false, false, | |
337 | sh_handle_sp_switch_attribute, false }, | |
338 | { "trap_exit", 1, 1, true, false, false, | |
339 | sh_handle_trap_exit_attribute, false }, | |
340 | { "renesas", 0, 0, false, true, false, | |
341 | sh_handle_renesas_attribute, false }, | |
342 | { "trapa_handler", 0, 0, true, false, false, | |
343 | sh_handle_interrupt_handler_attribute, false }, | |
344 | { "nosave_low_regs", 0, 0, true, false, false, | |
345 | sh_handle_interrupt_handler_attribute, false }, | |
346 | { "resbank", 0, 0, true, false, false, | |
347 | sh_handle_resbank_handler_attribute, false }, | |
348 | { "function_vector", 1, 1, true, false, false, | |
349 | sh2a_handle_function_vector_handler_attribute, false }, | |
62d784f7 | 350 | { NULL, 0, 0, false, false, false, NULL, false } |
5a82ecd9 | 351 | }; |
672a6f42 NB |
352 | \f |
353 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
354 | #undef TARGET_ATTRIBUTE_TABLE |
355 | #define TARGET_ATTRIBUTE_TABLE sh_attribute_table | |
672a6f42 | 356 | |
301d03af RS |
357 | /* The next two are used for debug info when compiling with -gdwarf. */ |
358 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
359 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t" | |
360 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
361 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t" | |
362 | ||
e7a8f681 N |
363 | #undef TARGET_OPTION_OVERRIDE |
364 | #define TARGET_OPTION_OVERRIDE sh_option_override | |
365 | ||
4c221995 KK |
366 | #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE |
367 | #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \ | |
368 | sh_override_options_after_change | |
369 | ||
9e94b957 NF |
370 | #undef TARGET_PRINT_OPERAND |
371 | #define TARGET_PRINT_OPERAND sh_print_operand | |
372 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
373 | #define TARGET_PRINT_OPERAND_ADDRESS sh_print_operand_address | |
374 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
375 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p | |
ef875e12 AS |
376 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
377 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra | |
378 | ||
08c148a8 NB |
379 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
380 | #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue | |
381 | ||
1aa03f38 R |
382 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
383 | #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk | |
384 | ||
385 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
50fe8924 OE |
386 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \ |
387 | hook_bool_const_tree_hwi_hwi_const_tree_true | |
1aa03f38 | 388 | |
1bc7c5b6 ZW |
389 | #undef TARGET_ASM_FILE_START |
390 | #define TARGET_ASM_FILE_START sh_file_start | |
391 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
392 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
393 | ||
1e44e857 DJ |
394 | #undef TARGET_ASM_INTEGER |
395 | #define TARGET_ASM_INTEGER sh_assemble_integer | |
396 | ||
e7a8f681 N |
397 | #undef TARGET_REGISTER_MOVE_COST |
398 | #define TARGET_REGISTER_MOVE_COST sh_register_move_cost | |
399 | ||
12a68f1f JM |
400 | #undef TARGET_INSERT_ATTRIBUTES |
401 | #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes | |
402 | ||
c237e94a ZW |
403 | #undef TARGET_SCHED_ADJUST_COST |
404 | #define TARGET_SCHED_ADJUST_COST sh_adjust_cost | |
405 | ||
fae15c93 VM |
406 | #undef TARGET_SCHED_ISSUE_RATE |
407 | #define TARGET_SCHED_ISSUE_RATE sh_issue_rate | |
408 | ||
58565a33 SKG |
409 | /* The next 5 hooks have been implemented for reenabling sched1. With the |
410 | help of these macros we are limiting the movement of insns in sched1 to | |
f676971a | 411 | reduce the register pressure. The overall idea is to keep count of SImode |
58565a33 SKG |
412 | and SFmode regs required by already scheduled insns. When these counts |
413 | cross some threshold values; give priority to insns that free registers. | |
414 | The insn that frees registers is most likely to be the insn with lowest | |
f676971a | 415 | LUID (original insn order); but such an insn might be there in the stalled |
58565a33 | 416 | queue (Q) instead of the ready queue (R). To solve this, we skip cycles |
073a8998 | 417 | up to a max of 8 cycles so that such insns may move from Q -> R. |
58565a33 SKG |
418 | |
419 | The description of the hooks are as below: | |
420 | ||
421 | TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic | |
422 | scheduler; it is called inside the sched_init function just after | |
423 | find_insn_reg_weights function call. It is used to calculate the SImode | |
1ae58c30 | 424 | and SFmode weights of insns of basic blocks; much similar to what |
f676971a | 425 | find_insn_reg_weights does. |
58565a33 SKG |
426 | TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook. |
427 | ||
428 | TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is | |
429 | indicated by TARGET_SCHED_REORDER2; doing this may move insns from | |
430 | (Q)->(R). | |
431 | ||
432 | TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is | |
433 | high; reorder the ready queue so that the insn with lowest LUID will be | |
434 | issued next. | |
435 | ||
436 | TARGET_SCHED_REORDER2: If the register pressure is high, indicate to | |
437 | TARGET_SCHED_DFA_NEW_CYCLE to skip cycles. | |
438 | ||
439 | TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it | |
440 | can be returned from TARGET_SCHED_REORDER2. | |
441 | ||
442 | TARGET_SCHED_INIT: Reset the register pressure counting variables. */ | |
443 | ||
444 | #undef TARGET_SCHED_DFA_NEW_CYCLE | |
445 | #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle | |
446 | ||
447 | #undef TARGET_SCHED_INIT_GLOBAL | |
448 | #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global | |
449 | ||
450 | #undef TARGET_SCHED_FINISH_GLOBAL | |
451 | #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global | |
452 | ||
453 | #undef TARGET_SCHED_VARIABLE_ISSUE | |
454 | #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue | |
455 | ||
456 | #undef TARGET_SCHED_REORDER | |
457 | #define TARGET_SCHED_REORDER sh_reorder | |
458 | ||
459 | #undef TARGET_SCHED_REORDER2 | |
460 | #define TARGET_SCHED_REORDER2 sh_reorder2 | |
461 | ||
462 | #undef TARGET_SCHED_INIT | |
463 | #define TARGET_SCHED_INIT sh_md_init | |
464 | ||
90833f7f KK |
465 | #undef TARGET_DELEGITIMIZE_ADDRESS |
466 | #define TARGET_DELEGITIMIZE_ADDRESS sh_delegitimize_address | |
467 | ||
506d7b68 PB |
468 | #undef TARGET_LEGITIMIZE_ADDRESS |
469 | #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address | |
470 | ||
cf6186e9 JR |
471 | #undef TARGET_CAN_FOLLOW_JUMP |
472 | #define TARGET_CAN_FOLLOW_JUMP sh_can_follow_jump | |
fa5322fa AO |
473 | |
474 | #undef TARGET_MS_BITFIELD_LAYOUT_P | |
475 | #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p | |
476 | ||
c1b92d09 R |
477 | #undef TARGET_INIT_BUILTINS |
478 | #define TARGET_INIT_BUILTINS sh_init_builtins | |
1cc24576 KK |
479 | #undef TARGET_BUILTIN_DECL |
480 | #define TARGET_BUILTIN_DECL sh_builtin_decl | |
c1b92d09 R |
481 | #undef TARGET_EXPAND_BUILTIN |
482 | #define TARGET_EXPAND_BUILTIN sh_expand_builtin | |
483 | ||
4977bab6 ZW |
484 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
485 | #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall | |
486 | ||
9f3a9a08 KK |
487 | #undef TARGET_CANNOT_COPY_INSN_P |
488 | #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p | |
3c50106f RH |
489 | #undef TARGET_RTX_COSTS |
490 | #define TARGET_RTX_COSTS sh_rtx_costs | |
dcefdf67 RH |
491 | #undef TARGET_ADDRESS_COST |
492 | #define TARGET_ADDRESS_COST sh_address_cost | |
b48f503c KK |
493 | #undef TARGET_ALLOCATE_INITIAL_VALUE |
494 | #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value | |
3c50106f | 495 | |
18dbd950 RS |
496 | #undef TARGET_MACHINE_DEPENDENT_REORG |
497 | #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg | |
498 | ||
63a9de54 CB |
499 | #undef TARGET_DWARF_REGISTER_SPAN |
500 | #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span | |
501 | ||
463f02cd KK |
502 | #ifdef HAVE_AS_TLS |
503 | #undef TARGET_HAVE_TLS | |
504 | #define TARGET_HAVE_TLS true | |
505 | #endif | |
506 | ||
61f71b34 DD |
507 | #undef TARGET_PROMOTE_PROTOTYPES |
508 | #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes | |
d055ce45 KK |
509 | #undef TARGET_PROMOTE_FUNCTION_MODE |
510 | #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode | |
61f71b34 | 511 | |
d64728cf AS |
512 | #undef TARGET_FUNCTION_VALUE |
513 | #define TARGET_FUNCTION_VALUE sh_function_value | |
e7a8f681 N |
514 | #undef TARGET_FUNCTION_VALUE_REGNO_P |
515 | #define TARGET_FUNCTION_VALUE_REGNO_P sh_function_value_regno_p | |
d64728cf AS |
516 | #undef TARGET_LIBCALL_VALUE |
517 | #define TARGET_LIBCALL_VALUE sh_libcall_value | |
61f71b34 DD |
518 | #undef TARGET_STRUCT_VALUE_RTX |
519 | #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx | |
520 | #undef TARGET_RETURN_IN_MEMORY | |
521 | #define TARGET_RETURN_IN_MEMORY sh_return_in_memory | |
522 | ||
523 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
524 | #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs | |
525 | #undef TARGET_SETUP_INCOMING_VARARGS | |
526 | #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs | |
527 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
528 | #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming | |
529 | #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED | |
530 | #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named | |
fe984136 RH |
531 | #undef TARGET_MUST_PASS_IN_STACK |
532 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
8cd5a4e0 RH |
533 | #undef TARGET_PASS_BY_REFERENCE |
534 | #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference | |
6cdd5672 RH |
535 | #undef TARGET_CALLEE_COPIES |
536 | #define TARGET_CALLEE_COPIES sh_callee_copies | |
78a52f11 RH |
537 | #undef TARGET_ARG_PARTIAL_BYTES |
538 | #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes | |
b64336b8 NF |
539 | #undef TARGET_FUNCTION_ARG |
540 | #define TARGET_FUNCTION_ARG sh_function_arg | |
541 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
542 | #define TARGET_FUNCTION_ARG_ADVANCE sh_function_arg_advance | |
61f71b34 | 543 | |
801881b0 KK |
544 | #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV |
545 | #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sh_atomic_assign_expand_fenv | |
546 | ||
c35d187f RH |
547 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
548 | #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list | |
d7bd8aeb JJ |
549 | #undef TARGET_EXPAND_BUILTIN_VA_START |
550 | #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start | |
5fac2ed2 RH |
551 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
552 | #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr | |
c35d187f | 553 | |
f676971a EC |
554 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
555 | #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p | |
556 | ||
8d932be3 RS |
557 | #undef TARGET_CHECK_PCH_TARGET_FLAGS |
558 | #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags | |
bcc8cc82 | 559 | |
a1c496cb EC |
560 | #undef TARGET_DWARF_CALLING_CONVENTION |
561 | #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention | |
562 | ||
7a296495 CB |
563 | #undef TARGET_FRAME_POINTER_REQUIRED |
564 | #define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required | |
565 | ||
06b90602 CB |
566 | #undef TARGET_MODE_EMIT |
567 | #define TARGET_MODE_EMIT sh_emit_mode_set | |
568 | ||
569 | #undef TARGET_MODE_NEEDED | |
570 | #define TARGET_MODE_NEEDED sh_mode_needed | |
571 | ||
572 | #undef TARGET_MODE_AFTER | |
573 | #define TARGET_MODE_AFTER sh_mode_after | |
574 | ||
575 | #undef TARGET_MODE_ENTRY | |
576 | #define TARGET_MODE_ENTRY sh_mode_entry | |
577 | ||
578 | #undef TARGET_MODE_EXIT | |
579 | #define TARGET_MODE_EXIT sh_mode_exit | |
580 | ||
581 | #undef TARGET_MODE_PRIORITY | |
582 | #define TARGET_MODE_PRIORITY sh_mode_priority | |
583 | ||
58565a33 | 584 | /* Return regmode weight for insn. */ |
23d0939b OE |
585 | #define INSN_REGMODE_WEIGHT(INSN, MODE)\ |
586 | regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)] | |
58565a33 SKG |
587 | |
588 | /* Return current register pressure for regmode. */ | |
23d0939b OE |
589 | #define CURR_REGMODE_PRESSURE(MODE)\ |
590 | curr_regmode_pressure[((MODE) == SImode) ? 0 : 1] | |
58565a33 | 591 | |
561642fa AP |
592 | #undef TARGET_ENCODE_SECTION_INFO |
593 | #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info | |
594 | ||
106a52b7 KK |
595 | #undef TARGET_LRA_P |
596 | #define TARGET_LRA_P sh_lra_p | |
597 | ||
8a99f6f9 R |
598 | #undef TARGET_SECONDARY_RELOAD |
599 | #define TARGET_SECONDARY_RELOAD sh_secondary_reload | |
600 | ||
486b10aa AS |
601 | #undef TARGET_PREFERRED_RELOAD_CLASS |
602 | #define TARGET_PREFERRED_RELOAD_CLASS sh_preferred_reload_class | |
603 | ||
5efd84c5 NF |
604 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
605 | #define TARGET_CONDITIONAL_REGISTER_USAGE sh_conditional_register_usage | |
606 | ||
1bb99877 KK |
607 | #undef TARGET_LEGITIMATE_ADDRESS_P |
608 | #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p | |
609 | ||
d6220b11 KK |
610 | #undef TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P |
611 | #define TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P sh_cannot_substitute_mem_equiv_p | |
612 | ||
14133a4d KK |
613 | #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT |
614 | #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \ | |
615 | sh_legitimize_address_displacement | |
616 | ||
994322ef RH |
617 | #undef TARGET_TRAMPOLINE_INIT |
618 | #define TARGET_TRAMPOLINE_INIT sh_trampoline_init | |
619 | #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS | |
620 | #define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address | |
621 | ||
1a627b35 RS |
622 | #undef TARGET_LEGITIMATE_CONSTANT_P |
623 | #define TARGET_LEGITIMATE_CONSTANT_P sh_legitimate_constant_p | |
624 | ||
c354951b AK |
625 | #undef TARGET_CANONICALIZE_COMPARISON |
626 | #define TARGET_CANONICALIZE_COMPARISON sh_canonicalize_comparison | |
627 | ||
841dbf80 OE |
628 | #undef TARGET_LEGITIMATE_COMBINED_INSN |
629 | #define TARGET_LEGITIMATE_COMBINED_INSN sh_legitimate_combined_insn | |
630 | ||
5d30dc5b OE |
631 | #undef TARGET_FIXED_CONDITION_CODE_REGS |
632 | #define TARGET_FIXED_CONDITION_CODE_REGS sh_fixed_condition_code_regs | |
633 | ||
ae59bd31 JG |
634 | #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P |
635 | #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \ | |
636 | sh_use_by_pieces_infrastructure_p | |
637 | ||
561642fa | 638 | /* Machine-specific symbol_ref flags. */ |
50fe8924 | 639 | #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0) |
561642fa | 640 | |
95a6dda5 RH |
641 | /* The tas.b instruction sets the 7th bit in the byte, i.e. 0x80. This value |
642 | is used by optabs.c atomic op expansion code as well as in sync.md. */ | |
643 | #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL | |
644 | #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80 | |
645 | ||
1e44e857 DJ |
646 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
647 | #define TARGET_CANNOT_FORCE_CONST_MEM sh_cannot_force_const_mem_p | |
648 | ||
c43f4279 RS |
649 | #undef TARGET_HARD_REGNO_NREGS |
650 | #define TARGET_HARD_REGNO_NREGS sh_hard_regno_nregs | |
f939c3e6 RS |
651 | #undef TARGET_HARD_REGNO_MODE_OK |
652 | #define TARGET_HARD_REGNO_MODE_OK sh_hard_regno_mode_ok | |
653 | ||
99e1629f RS |
654 | #undef TARGET_MODES_TIEABLE_P |
655 | #define TARGET_MODES_TIEABLE_P sh_modes_tieable_p | |
656 | ||
0d803030 RS |
657 | #undef TARGET_CAN_CHANGE_MODE_CLASS |
658 | #define TARGET_CAN_CHANGE_MODE_CLASS sh_can_change_mode_class | |
659 | ||
58e17cf8 RS |
660 | #undef TARGET_CONSTANT_ALIGNMENT |
661 | #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings | |
662 | ||
f6897b10 | 663 | struct gcc_target targetm = TARGET_INITIALIZER; |
b9654711 | 664 | \f |
7bd76b9c OE |
665 | |
666 | /* Information on the currently selected atomic model. | |
667 | This is initialized in sh_option_override. */ | |
668 | static sh_atomic_model selected_atomic_model_; | |
669 | ||
670 | const sh_atomic_model& | |
671 | selected_atomic_model (void) | |
672 | { | |
673 | return selected_atomic_model_; | |
674 | } | |
675 | ||
676 | static sh_atomic_model | |
677 | parse_validate_atomic_model_option (const char* str) | |
678 | { | |
679 | const char* model_names[sh_atomic_model::num_models]; | |
680 | model_names[sh_atomic_model::none] = "none"; | |
681 | model_names[sh_atomic_model::soft_gusa] = "soft-gusa"; | |
682 | model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; | |
683 | model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; | |
684 | model_names[sh_atomic_model::soft_imask] = "soft-imask"; | |
685 | ||
9597375a OE |
686 | const char* model_cdef_names[sh_atomic_model::num_models]; |
687 | model_cdef_names[sh_atomic_model::none] = "NONE"; | |
688 | model_cdef_names[sh_atomic_model::soft_gusa] = "SOFT_GUSA"; | |
689 | model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; | |
690 | model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; | |
691 | model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; | |
692 | ||
7bd76b9c OE |
693 | sh_atomic_model ret; |
694 | ret.type = sh_atomic_model::none; | |
9597375a OE |
695 | ret.name = model_names[sh_atomic_model::none]; |
696 | ret.cdef_name = model_cdef_names[sh_atomic_model::none]; | |
7bd76b9c OE |
697 | ret.strict = false; |
698 | ret.tcb_gbr_offset = -1; | |
699 | ||
700 | /* Handle empty string as 'none'. */ | |
701 | if (str == NULL || *str == '\0') | |
702 | return ret; | |
703 | ||
704 | #define err_ret(...) do { error (__VA_ARGS__); return ret; } while (0) | |
705 | ||
706 | std::vector<std::string> tokens; | |
707 | for (std::stringstream ss (str); ss.good (); ) | |
708 | { | |
709 | tokens.push_back (std::string ()); | |
710 | std::getline (ss, tokens.back (), ','); | |
711 | } | |
712 | ||
713 | if (tokens.empty ()) | |
714 | err_ret ("invalid atomic model option"); | |
715 | ||
716 | /* The first token must be the atomic model name. */ | |
717 | { | |
718 | for (size_t i = 0; i < sh_atomic_model::num_models; ++i) | |
719 | if (tokens.front () == model_names[i]) | |
720 | { | |
721 | ret.type = (sh_atomic_model::enum_type)i; | |
9597375a OE |
722 | ret.name = model_names[i]; |
723 | ret.cdef_name = model_cdef_names[i]; | |
7bd76b9c OE |
724 | goto got_mode_name; |
725 | } | |
726 | ||
727 | err_ret ("invalid atomic model name \"%s\"", tokens.front ().c_str ()); | |
728 | got_mode_name:; | |
729 | } | |
730 | ||
731 | /* Go through the remaining tokens. */ | |
732 | for (size_t i = 1; i < tokens.size (); ++i) | |
733 | { | |
734 | if (tokens[i] == "strict") | |
735 | ret.strict = true; | |
736 | else if (tokens[i].find ("gbr-offset=") == 0) | |
737 | { | |
738 | std::string offset_str = tokens[i].substr (strlen ("gbr-offset=")); | |
739 | ret.tcb_gbr_offset = integral_argument (offset_str.c_str ()); | |
740 | if (offset_str.empty () || ret.tcb_gbr_offset == -1) | |
741 | err_ret ("could not parse gbr-offset value \"%s\" in atomic model " | |
742 | "option", offset_str.c_str ()); | |
743 | } | |
744 | else | |
745 | err_ret ("unknown parameter \"%s\" in atomic model option", | |
50fe8924 | 746 | tokens[i].c_str ()); |
7bd76b9c OE |
747 | } |
748 | ||
749 | /* Check that the selection makes sense. */ | |
7bd76b9c OE |
750 | if (ret.type == sh_atomic_model::soft_gusa && !TARGET_SH3) |
751 | err_ret ("atomic model %s is only available on SH3 and SH4 targets", | |
9597375a | 752 | ret.name); |
7bd76b9c OE |
753 | |
754 | if (ret.type == sh_atomic_model::hard_llcs && !TARGET_SH4A) | |
9597375a | 755 | err_ret ("atomic model %s is only available on SH4A targets", ret.name); |
7bd76b9c OE |
756 | |
757 | if (ret.type == sh_atomic_model::soft_tcb && ret.tcb_gbr_offset == -1) | |
9597375a | 758 | err_ret ("atomic model %s requires gbr-offset parameter", ret.name); |
7bd76b9c OE |
759 | |
760 | if (ret.type == sh_atomic_model::soft_tcb | |
761 | && (ret.tcb_gbr_offset < 0 || ret.tcb_gbr_offset > 1020 | |
762 | || (ret.tcb_gbr_offset & 3) != 0)) | |
763 | err_ret ("invalid gbr-offset value \"%d\" for atomic model %s; it must be " | |
764 | "a multiple of 4 in the range 0-1020", ret.tcb_gbr_offset, | |
9597375a | 765 | ret.name); |
7bd76b9c OE |
766 | |
767 | if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) | |
9597375a | 768 | err_ret ("cannot use atomic model %s in user mode", ret.name); |
7bd76b9c OE |
769 | |
770 | return ret; | |
771 | ||
772 | #undef err_ret | |
773 | } | |
774 | ||
5d30dc5b OE |
775 | /* Register SH specific RTL passes. */ |
776 | extern opt_pass* make_pass_sh_treg_combine (gcc::context* ctx, bool split_insns, | |
ac973375 OE |
777 | const char* name); |
778 | extern opt_pass* make_pass_sh_optimize_sett_clrt (gcc::context* ctx, | |
779 | const char* name); | |
5d30dc5b OE |
780 | static void |
781 | register_sh_passes (void) | |
782 | { | |
5d30dc5b OE |
783 | /* Running the sh_treg_combine pass after ce1 generates better code when |
784 | comparisons are combined and reg-reg moves are introduced, because | |
785 | reg-reg moves will be eliminated afterwards. However, there are quite | |
786 | some cases where combine will be unable to fold comparison related insns, | |
787 | thus for now don't do it. | |
788 | register_pass (make_pass_sh_treg_combine (g, false, "sh_treg_combine1"), | |
789 | PASS_POS_INSERT_AFTER, "ce1", 1); | |
790 | */ | |
791 | ||
792 | /* Run sh_treg_combine pass after combine but before register allocation. */ | |
793 | register_pass (make_pass_sh_treg_combine (g, true, "sh_treg_combine2"), | |
794 | PASS_POS_INSERT_AFTER, "split1", 1); | |
795 | ||
796 | /* Run sh_treg_combine pass after register allocation and basic block | |
797 | reordering as this sometimes creates new opportunities. */ | |
798 | register_pass (make_pass_sh_treg_combine (g, true, "sh_treg_combine3"), | |
799 | PASS_POS_INSERT_AFTER, "split4", 1); | |
ac973375 OE |
800 | |
801 | /* Optimize sett and clrt insns, by e.g. removing them if the T bit value | |
802 | is known after a conditional branch. | |
803 | This must be done after basic blocks and branch conditions have | |
804 | stabilized and won't be changed by further passes. */ | |
805 | register_pass (make_pass_sh_optimize_sett_clrt (g, "sh_optimize_sett_clrt"), | |
806 | PASS_POS_INSERT_BEFORE, "sched2", 1); | |
5d30dc5b OE |
807 | } |
808 | ||
e7a8f681 N |
809 | /* Implement TARGET_OPTION_OVERRIDE macro. Validate and override |
810 | various options, and do some machine dependent initialization. */ | |
811 | static void | |
812 | sh_option_override (void) | |
bd9a3465 KK |
813 | { |
814 | int regno; | |
815 | ||
816 | SUBTARGET_OVERRIDE_OPTIONS; | |
7337ddf4 | 817 | |
bd9a3465 KK |
818 | sh_cpu = PROCESSOR_SH1; |
819 | assembler_dialect = 0; | |
820 | if (TARGET_SH2) | |
821 | sh_cpu = PROCESSOR_SH2; | |
822 | if (TARGET_SH2E) | |
823 | sh_cpu = PROCESSOR_SH2E; | |
824 | if (TARGET_SH2A) | |
7a61cf6f | 825 | sh_cpu = PROCESSOR_SH2A; |
bd9a3465 KK |
826 | if (TARGET_SH3) |
827 | sh_cpu = PROCESSOR_SH3; | |
828 | if (TARGET_SH3E) | |
829 | sh_cpu = PROCESSOR_SH3E; | |
830 | if (TARGET_SH4) | |
831 | { | |
832 | assembler_dialect = 1; | |
833 | sh_cpu = PROCESSOR_SH4; | |
834 | } | |
f3ca7111 | 835 | if (TARGET_SH4A) |
bd9a3465 KK |
836 | { |
837 | assembler_dialect = 1; | |
838 | sh_cpu = PROCESSOR_SH4A; | |
839 | } | |
37c5f877 | 840 | |
e1fab8ba | 841 | /* User/priviledged mode is supported only on SH3* and SH4*. |
37c5f877 | 842 | Disable it for everything else. */ |
e1fab8ba | 843 | if (!TARGET_SH3 && TARGET_USERMODE) |
37c5f877 OE |
844 | TARGET_USERMODE = false; |
845 | ||
f1bebab6 OE |
846 | if (! strcmp (sh_div_str, "call-div1")) |
847 | sh_div_strategy = SH_DIV_CALL_DIV1; | |
848 | else if (! strcmp (sh_div_str, "call-fp") && TARGET_FPU_ANY) | |
849 | sh_div_strategy = SH_DIV_CALL_FP; | |
850 | else if (! strcmp (sh_div_str, "call-table") && TARGET_DYNSHIFT) | |
851 | sh_div_strategy = SH_DIV_CALL_TABLE; | |
852 | else | |
bd9a3465 | 853 | { |
f1bebab6 OE |
854 | /* Pick one that makes most sense for the target in general. |
855 | It is not much good to use different functions depending on -Os, | |
856 | since then we'll end up with two different functions when some of | |
857 | the code is compiled for size, and some for speed. */ | |
858 | ||
859 | /* SH4 tends to emphasize speed. */ | |
860 | if (TARGET_HARD_SH4) | |
bd9a3465 | 861 | sh_div_strategy = SH_DIV_CALL_TABLE; |
f1bebab6 OE |
862 | /* These have their own way of doing things. */ |
863 | else if (TARGET_SH2A) | |
864 | sh_div_strategy = SH_DIV_INTRINSIC; | |
865 | /* SH1 .. SH3 cores often go into small-footprint systems, so | |
866 | default to the smallest implementation available. */ | |
bd9a3465 | 867 | else |
f1bebab6 | 868 | sh_div_strategy = SH_DIV_CALL_DIV1; |
bd9a3465 | 869 | } |
f1bebab6 | 870 | |
bd9a3465 KK |
871 | if (sh_divsi3_libfunc[0]) |
872 | ; /* User supplied - leave it alone. */ | |
873 | else if (TARGET_DIVIDE_CALL_FP) | |
874 | sh_divsi3_libfunc = "__sdivsi3_i4"; | |
875 | else if (TARGET_DIVIDE_CALL_TABLE) | |
876 | sh_divsi3_libfunc = "__sdivsi3_i4i"; | |
bd9a3465 KK |
877 | else |
878 | sh_divsi3_libfunc = "__sdivsi3"; | |
d580af0f | 879 | |
bd9a3465 | 880 | if (sh_branch_cost == -1) |
91afd29b | 881 | { |
91afd29b OE |
882 | /* The SH1 does not have delay slots, hence we get a pipeline stall |
883 | at every branch. The SH4 is superscalar, so the single delay slot | |
d580af0f OE |
884 | is not sufficient to keep both pipelines filled. |
885 | In any case, set the default branch cost to '2', as it results in | |
886 | slightly overall smaller code and also enables some if conversions | |
887 | that are required for matching special T bit related insns. */ | |
888 | sh_branch_cost = 2; | |
91afd29b | 889 | } |
bd9a3465 | 890 | |
f34ee0b2 OE |
891 | /* Set -mzdcbranch for SH4 / SH4A if not otherwise specified by the user. */ |
892 | if (! global_options_set.x_TARGET_ZDCBRANCH && TARGET_HARD_SH4) | |
893 | TARGET_ZDCBRANCH = 1; | |
894 | ||
1e44e857 DJ |
895 | /* FDPIC code is a special form of PIC, and the vast majority of code |
896 | generation constraints that apply to PIC also apply to FDPIC, so we | |
897 | set flag_pic to avoid the need to check TARGET_FDPIC everywhere | |
898 | flag_pic is checked. */ | |
899 | if (TARGET_FDPIC && !flag_pic) | |
900 | flag_pic = 2; | |
901 | ||
bd9a3465 KK |
902 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
903 | if (! VALID_REGISTER_P (regno)) | |
904 | sh_register_names[regno][0] = '\0'; | |
905 | ||
906 | for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) | |
907 | if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) | |
908 | sh_additional_register_names[regno][0] = '\0'; | |
909 | ||
e1fab8ba | 910 | if (flag_pic && ! TARGET_PREFERGOT) |
bd9a3465 KK |
911 | flag_no_function_cse = 1; |
912 | ||
50fe8924 | 913 | if (targetm.small_register_classes_for_mode_p (VOIDmode)) |
bd9a3465 KK |
914 | { |
915 | /* Never run scheduling before reload, since that can | |
916 | break global alloc, and generates slower code anyway due | |
917 | to the pressure on R0. */ | |
918 | /* Enable sched1 for SH4 if the user explicitly requests. | |
919 | When sched1 is enabled, the ready queue will be reordered by | |
920 | the target hooks if pressure is high. We can not do this for | |
921 | PIC, SH3 and lower as they give spill failures for R0. */ | |
922 | if (!TARGET_HARD_SH4 || flag_pic) | |
50fe8924 | 923 | flag_schedule_insns = 0; |
bd9a3465 KK |
924 | /* ??? Current exception handling places basic block boundaries |
925 | after call_insns. It causes the high pressure on R0 and gives | |
926 | spill failures for R0 in reload. See PR 22553 and the thread | |
927 | on gcc-patches | |
50fe8924 | 928 | <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ |
bd9a3465 KK |
929 | else if (flag_exceptions) |
930 | { | |
0a587f65 | 931 | if (flag_schedule_insns && global_options_set.x_flag_schedule_insns) |
50fe8924 OE |
932 | warning (0, "ignoring -fschedule-insns because of exception " |
933 | "handling bug"); | |
bd9a3465 KK |
934 | flag_schedule_insns = 0; |
935 | } | |
0a587f65 JM |
936 | else if (flag_schedule_insns |
937 | && !global_options_set.x_flag_schedule_insns) | |
bd9a3465 KK |
938 | flag_schedule_insns = 0; |
939 | } | |
940 | ||
5921cd19 CB |
941 | /* Unwind info is not correct around the CFG unless either a frame |
942 | pointer is present or M_A_O_A is set. Fixing this requires rewriting | |
943 | unwind info generation to be aware of the CFG and propagating states | |
7a296495 CB |
944 | around edges. */ |
945 | if ((flag_unwind_tables || flag_asynchronous_unwind_tables | |
5921cd19 CB |
946 | || flag_exceptions || flag_non_call_exceptions) |
947 | && flag_omit_frame_pointer && !TARGET_ACCUMULATE_OUTGOING_ARGS) | |
7a296495 | 948 | { |
5921cd19 CB |
949 | warning (0, "unwind tables currently require either a frame pointer " |
950 | "or -maccumulate-outgoing-args for correctness"); | |
951 | TARGET_ACCUMULATE_OUTGOING_ARGS = 1; | |
7a296495 CB |
952 | } |
953 | ||
4c221995 KK |
954 | if (flag_unsafe_math_optimizations) |
955 | { | |
956 | /* Enable fsca insn for SH4A if not otherwise specified by the user. */ | |
957 | if (global_options_set.x_TARGET_FSCA == 0 && TARGET_SH4A_FP) | |
958 | TARGET_FSCA = 1; | |
959 | ||
960 | /* Enable fsrra insn for SH4A if not otherwise specified by the user. */ | |
961 | if (global_options_set.x_TARGET_FSRRA == 0 && TARGET_SH4A_FP) | |
962 | TARGET_FSRRA = 1; | |
963 | } | |
964 | ||
965 | /* Allow fsrra insn only if -funsafe-math-optimizations and | |
966 | -ffinite-math-only is enabled. */ | |
967 | TARGET_FSRRA = TARGET_FSRRA | |
968 | && flag_unsafe_math_optimizations | |
969 | && flag_finite_math_only; | |
970 | ||
971 | /* If the -mieee option was not explicitly set by the user, turn it on | |
972 | unless -ffinite-math-only was specified. See also PR 33135. */ | |
973 | if (! global_options_set.x_TARGET_IEEE) | |
974 | TARGET_IEEE = ! flag_finite_math_only; | |
975 | ||
976 | if (sh_fixed_range_str) | |
977 | sh_fix_range (sh_fixed_range_str); | |
978 | ||
979 | /* This target defaults to strict volatile bitfields. */ | |
980 | if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) | |
981 | flag_strict_volatile_bitfields = 1; | |
982 | ||
983 | sh_override_options_after_change (); | |
984 | ||
985 | /* Parse atomic model option and make sure it is valid for the current | |
986 | target CPU. */ | |
987 | selected_atomic_model_ | |
988 | = parse_validate_atomic_model_option (sh_atomic_model_str); | |
989 | ||
990 | register_sh_passes (); | |
991 | } | |
992 | ||
993 | /* Implement targetm.override_options_after_change. */ | |
994 | ||
995 | static void | |
996 | sh_override_options_after_change (void) | |
997 | { | |
b6a0df6c OE |
998 | /* Adjust loop, jump and function alignment values (in bytes), if those |
999 | were not specified by the user using -falign-loops, -falign-jumps | |
1000 | and -falign-functions options. | |
1001 | 32 bit alignment is better for speed, because instructions can be | |
1002 | fetched as a pair from a longword boundary. For size use 16 bit | |
1003 | alignment to get more compact code. | |
1004 | Aligning all jumps increases the code size, even if it might | |
1005 | result in slightly faster code. Thus, it is set to the smallest | |
1006 | alignment possible if not specified by the user. */ | |
bd9a3465 | 1007 | if (align_loops == 0) |
e1fab8ba | 1008 | align_loops = optimize_size ? 2 : 4; |
b6a0df6c | 1009 | |
bd9a3465 | 1010 | if (align_jumps == 0) |
e1fab8ba OE |
1011 | align_jumps = 2; |
1012 | else if (align_jumps < 2) | |
1013 | align_jumps = 2; | |
bd9a3465 | 1014 | |
bd9a3465 | 1015 | if (align_functions == 0) |
e1fab8ba | 1016 | align_functions = optimize_size ? 2 : 4; |
b6a0df6c | 1017 | |
bd9a3465 KK |
1018 | /* The linker relaxation code breaks when a function contains |
1019 | alignments that are larger than that at the start of a | |
1020 | compilation unit. */ | |
1021 | if (TARGET_RELAX) | |
1022 | { | |
50fe8924 | 1023 | int min_align = align_loops > align_jumps ? align_loops : align_jumps; |
bd9a3465 | 1024 | |
50fe8924 | 1025 | /* Also take possible .long constants / mova tables into account. */ |
bd9a3465 KK |
1026 | if (min_align < 4) |
1027 | min_align = 4; | |
1028 | if (align_functions < min_align) | |
1029 | align_functions = min_align; | |
1030 | } | |
bd9a3465 KK |
1031 | } |
1032 | \f | |
16bea517 | 1033 | /* Print the operand address in x to the stream. */ |
9e94b957 | 1034 | static void |
cc8ca59e | 1035 | sh_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x) |
bc45ade3 SC |
1036 | { |
1037 | switch (GET_CODE (x)) | |
1038 | { | |
1039 | case REG: | |
225e4f43 R |
1040 | case SUBREG: |
1041 | fprintf (stream, "@%s", reg_names[true_regnum (x)]); | |
bc45ade3 | 1042 | break; |
8aa2a305 | 1043 | |
bc45ade3 SC |
1044 | case PLUS: |
1045 | { | |
1046 | rtx base = XEXP (x, 0); | |
1047 | rtx index = XEXP (x, 1); | |
1048 | ||
bc45ade3 SC |
1049 | switch (GET_CODE (index)) |
1050 | { | |
1051 | case CONST_INT: | |
c5b9ef02 | 1052 | fprintf (stream, "@(%d,%s)", (int) INTVAL (index), |
225e4f43 | 1053 | reg_names[true_regnum (base)]); |
bc45ade3 SC |
1054 | break; |
1055 | ||
1056 | case REG: | |
225e4f43 R |
1057 | case SUBREG: |
1058 | { | |
1059 | int base_num = true_regnum (base); | |
1060 | int index_num = true_regnum (index); | |
1061 | ||
c389d349 OE |
1062 | /* If base or index is R0, make sure that it comes first. |
1063 | Usually one of them will be R0, but the order might be wrong. | |
1064 | If neither base nor index are R0 it's an error and we just | |
1065 | pass it on to the assembler. This avoids silent wrong code | |
1066 | bugs. */ | |
1067 | if (base_num == 0 && index_num != 0) | |
1068 | std::swap (base_num, index_num); | |
1069 | ||
1070 | fprintf (stream, "@(%s,%s)", reg_names[index_num], | |
1071 | reg_names[base_num]); | |
225e4f43 R |
1072 | break; |
1073 | } | |
bc45ade3 SC |
1074 | |
1075 | default: | |
f5b9e7c9 | 1076 | gcc_unreachable (); |
bc45ade3 SC |
1077 | } |
1078 | } | |
bc45ade3 | 1079 | break; |
8aa2a305 | 1080 | |
bc45ade3 | 1081 | case PRE_DEC: |
225e4f43 | 1082 | fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]); |
bc45ade3 SC |
1083 | break; |
1084 | ||
1085 | case POST_INC: | |
225e4f43 | 1086 | fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]); |
bc45ade3 SC |
1087 | break; |
1088 | ||
1089 | default: | |
b91455de | 1090 | x = mark_constant_pool_use (x); |
422be3c3 | 1091 | output_addr_const (stream, x); |
bc45ade3 SC |
1092 | break; |
1093 | } | |
1094 | } | |
1095 | ||
1096 | /* Print operand x (an rtx) in assembler syntax to file stream | |
1097 | according to modifier code. | |
1098 | ||
b9654711 | 1099 | '.' print a .s if insn needs delay slot |
1245df60 | 1100 | ',' print LOCAL_LABEL_PREFIX |
4408efce | 1101 | '@' print trap, rte or rts depending upon pragma interruptness |
8aa2a305 | 1102 | '#' output a nop if there is nothing to put in the delay slot |
fae778eb | 1103 | ''' print likelihood suffix (/u for unlikely). |
73a4d10b | 1104 | '>' print branch target if -fverbose-asm |
8aa2a305 | 1105 | 'O' print a constant without the # |
00f8ff66 | 1106 | 'R' print the LSW of a dp value - changes if in little endian |
00f8ff66 | 1107 | 'S' print the MSW of a dp value - changes if in little endian |
225e4f43 | 1108 | 'T' print the next word of a dp value - same as 'R' in big endian mode. |
e1fab8ba | 1109 | 'M' print .b / .w / .l / .s / .d suffix if operand is a MEM. |
c1b92d09 | 1110 | 'N' print 'r63' if the operand is (const_int 0). |
312209c6 | 1111 | 'd' print a V2SF reg as dN instead of fpN. |
fa5322fa | 1112 | 'm' print a pair `base,offset' or `base,index', for LD and ST. |
73a4d10b | 1113 | 'U' Likewise for {LD,ST}{HI,LO}. |
de6adfa2 N |
1114 | 'V' print the position of a single bit set. |
1115 | 'W' print the position of a single bit cleared. | |
9eb3a0dd | 1116 | 't' print a memory address which is a register. |
fa5322fa | 1117 | 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value. |
225e4f43 | 1118 | 'o' output an operator. */ |
9e94b957 NF |
1119 | static void |
1120 | sh_print_operand (FILE *stream, rtx x, int code) | |
bc45ade3 | 1121 | { |
73a4d10b | 1122 | int regno; |
ef4bddc2 | 1123 | machine_mode mode; |
73a4d10b | 1124 | |
bc45ade3 SC |
1125 | switch (code) |
1126 | { | |
a6ab9fc0 R |
1127 | tree trapa_attr; |
1128 | ||
b9654711 | 1129 | case '.': |
79b2746a | 1130 | if (final_sequence |
84034c69 DM |
1131 | && ! INSN_ANNULLED_BRANCH_P (final_sequence->insn (0)) |
1132 | && get_attr_length (final_sequence->insn (1))) | |
1245df60 R |
1133 | fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s"); |
1134 | break; | |
1135 | case ',': | |
1136 | fprintf (stream, "%s", LOCAL_LABEL_PREFIX); | |
b9654711 | 1137 | break; |
d3ae8277 | 1138 | case '@': |
a6ab9fc0 R |
1139 | trapa_attr = lookup_attribute ("trap_exit", |
1140 | DECL_ATTRIBUTES (current_function_decl)); | |
1141 | if (trapa_attr) | |
50fe8924 | 1142 | fprintf (stream, "trapa #%ld", |
a6ab9fc0 | 1143 | (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr)))); |
e3ba8d11 | 1144 | else if (sh_cfun_interrupt_handler_p ()) |
561642fa AP |
1145 | { |
1146 | if (sh_cfun_resbank_handler_p ()) | |
1147 | fprintf (stream, "resbank\n"); | |
1148 | fprintf (stream, "rte"); | |
1149 | } | |
d3ae8277 | 1150 | else |
8e87e161 | 1151 | fprintf (stream, "rts"); |
d3ae8277 | 1152 | break; |
bc45ade3 | 1153 | case '#': |
16bea517 | 1154 | /* Output a nop if there's nothing in the delay slot. */ |
bc45ade3 | 1155 | if (dbr_sequence_length () == 0) |
8aa2a305 | 1156 | fprintf (stream, "\n\tnop"); |
bc45ade3 | 1157 | break; |
c8cc4417 R |
1158 | case '\'': |
1159 | { | |
1160 | rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0); | |
1161 | ||
5fa396ad JH |
1162 | if (note |
1163 | && profile_probability::from_reg_br_prob_note (XINT (note, 0)) | |
1164 | < profile_probability::even ()) | |
c8cc4417 R |
1165 | fputs ("/u", stream); |
1166 | break; | |
1167 | } | |
73a4d10b R |
1168 | case '>': |
1169 | if (flag_verbose_asm && JUMP_LABEL (current_output_insn)) | |
1170 | { | |
1171 | fputs ("\t! target: ", stream); | |
1172 | output_addr_const (stream, JUMP_LABEL (current_output_insn)); | |
1173 | } | |
1174 | break; | |
b9654711 | 1175 | case 'O': |
b91455de | 1176 | x = mark_constant_pool_use (x); |
0d7e008e | 1177 | output_addr_const (stream, x); |
bc45ade3 | 1178 | break; |
4802062c | 1179 | /* N.B.: %R / %S / %T adjust memory addresses by four. |
4802062c R |
1180 | While they can be used to access 64 bit parts of a larger value |
1181 | held in general purpose registers, that won't work with memory - | |
1182 | neither for fp registers, since the frxx names are used. */ | |
bc45ade3 | 1183 | case 'R': |
4802062c R |
1184 | if (REG_P (x) || GET_CODE (x) == SUBREG) |
1185 | { | |
1186 | regno = true_regnum (x); | |
277772f6 | 1187 | regno += FP_REGISTER_P (regno) ? 1 : SH_REG_LSW_OFFSET; |
4802062c R |
1188 | fputs (reg_names[regno], (stream)); |
1189 | } | |
1190 | else if (MEM_P (x)) | |
1191 | { | |
277772f6 | 1192 | x = adjust_address (x, SImode, 4 * SH_REG_LSW_OFFSET); |
cc8ca59e | 1193 | sh_print_operand_address (stream, GET_MODE (x), XEXP (x, 0)); |
4802062c R |
1194 | } |
1195 | else | |
1196 | { | |
1197 | rtx sub = NULL_RTX; | |
1198 | ||
1199 | mode = GET_MODE (x); | |
1200 | if (mode == VOIDmode) | |
1201 | mode = DImode; | |
1202 | if (GET_MODE_SIZE (mode) >= 8) | |
277772f6 | 1203 | sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_LSW_OFFSET); |
4802062c | 1204 | if (sub) |
9e94b957 | 1205 | sh_print_operand (stream, sub, 0); |
4802062c R |
1206 | else |
1207 | output_operand_lossage ("invalid operand to %%R"); | |
1208 | } | |
8aa2a305 JW |
1209 | break; |
1210 | case 'S': | |
4802062c R |
1211 | if (REG_P (x) || GET_CODE (x) == SUBREG) |
1212 | { | |
1213 | regno = true_regnum (x); | |
277772f6 | 1214 | regno += FP_REGISTER_P (regno) ? 0 : SH_REG_MSW_OFFSET; |
4802062c R |
1215 | fputs (reg_names[regno], (stream)); |
1216 | } | |
1217 | else if (MEM_P (x)) | |
1218 | { | |
277772f6 | 1219 | x = adjust_address (x, SImode, 4 * SH_REG_MSW_OFFSET); |
cc8ca59e | 1220 | sh_print_operand_address (stream, GET_MODE (x), XEXP (x, 0)); |
4802062c R |
1221 | } |
1222 | else | |
1223 | { | |
1224 | rtx sub = NULL_RTX; | |
1225 | ||
1226 | mode = GET_MODE (x); | |
1227 | if (mode == VOIDmode) | |
1228 | mode = DImode; | |
1229 | if (GET_MODE_SIZE (mode) >= 8) | |
277772f6 | 1230 | sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_MSW_OFFSET); |
4802062c | 1231 | if (sub) |
9e94b957 | 1232 | sh_print_operand (stream, sub, 0); |
4802062c R |
1233 | else |
1234 | output_operand_lossage ("invalid operand to %%S"); | |
1235 | } | |
00f8ff66 SC |
1236 | break; |
1237 | case 'T': | |
16bea517 | 1238 | /* Next word of a double. */ |
bc45ade3 SC |
1239 | switch (GET_CODE (x)) |
1240 | { | |
1241 | case REG: | |
1242 | fputs (reg_names[REGNO (x) + 1], (stream)); | |
1243 | break; | |
1244 | case MEM: | |
cc8ca59e JB |
1245 | { |
1246 | machine_mode mode = GET_MODE (x); | |
1247 | if (GET_CODE (XEXP (x, 0)) != PRE_DEC | |
1248 | && GET_CODE (XEXP (x, 0)) != POST_INC) | |
1249 | x = adjust_address (x, SImode, 4); | |
1250 | sh_print_operand_address (stream, mode, XEXP (x, 0)); | |
1251 | } | |
bc45ade3 | 1252 | break; |
318881c0 KG |
1253 | default: |
1254 | break; | |
bc45ade3 SC |
1255 | } |
1256 | break; | |
9eb3a0dd N |
1257 | |
1258 | case 't': | |
f3536097 | 1259 | gcc_assert (MEM_P (x)); |
9eb3a0dd N |
1260 | x = XEXP (x, 0); |
1261 | switch (GET_CODE (x)) | |
1262 | { | |
1263 | case REG: | |
1264 | case SUBREG: | |
9e94b957 | 1265 | sh_print_operand (stream, x, 0); |
9eb3a0dd N |
1266 | break; |
1267 | default: | |
1268 | break; | |
1269 | } | |
1270 | break; | |
1271 | ||
225e4f43 R |
1272 | case 'o': |
1273 | switch (GET_CODE (x)) | |
1274 | { | |
1275 | case PLUS: fputs ("add", stream); break; | |
1276 | case MINUS: fputs ("sub", stream); break; | |
1277 | case MULT: fputs ("mul", stream); break; | |
1278 | case DIV: fputs ("div", stream); break; | |
c8cc4417 R |
1279 | case EQ: fputs ("eq", stream); break; |
1280 | case NE: fputs ("ne", stream); break; | |
1281 | case GT: case LT: fputs ("gt", stream); break; | |
1282 | case GE: case LE: fputs ("ge", stream); break; | |
1283 | case GTU: case LTU: fputs ("gtu", stream); break; | |
1284 | case GEU: case LEU: fputs ("geu", stream); break; | |
318881c0 KG |
1285 | default: |
1286 | break; | |
225e4f43 R |
1287 | } |
1288 | break; | |
fa5322fa | 1289 | case 'M': |
e1fab8ba | 1290 | if (MEM_P (x)) |
31b6f0ae | 1291 | { |
e1fab8ba | 1292 | switch (GET_MODE (x)) |
31b6f0ae | 1293 | { |
4e10a5a7 RS |
1294 | case E_QImode: fputs (".b", stream); break; |
1295 | case E_HImode: fputs (".w", stream); break; | |
1296 | case E_SImode: fputs (".l", stream); break; | |
1297 | case E_SFmode: fputs (".s", stream); break; | |
1298 | case E_DFmode: fputs (".d", stream); break; | |
e1fab8ba | 1299 | default: gcc_unreachable (); |
31b6f0ae R |
1300 | } |
1301 | } | |
fa5322fa AO |
1302 | break; |
1303 | ||
1304 | case 'm': | |
f3536097 | 1305 | gcc_assert (MEM_P (x)); |
fa5322fa | 1306 | x = XEXP (x, 0); |
73a4d10b R |
1307 | /* Fall through. */ |
1308 | case 'U': | |
fa5322fa AO |
1309 | switch (GET_CODE (x)) |
1310 | { | |
1311 | case REG: | |
1312 | case SUBREG: | |
9e94b957 | 1313 | sh_print_operand (stream, x, 0); |
fa5322fa AO |
1314 | fputs (", 0", stream); |
1315 | break; | |
1316 | ||
1317 | case PLUS: | |
9e94b957 | 1318 | sh_print_operand (stream, XEXP (x, 0), 0); |
fa5322fa | 1319 | fputs (", ", stream); |
9e94b957 | 1320 | sh_print_operand (stream, XEXP (x, 1), 0); |
fa5322fa AO |
1321 | break; |
1322 | ||
1323 | default: | |
f5b9e7c9 | 1324 | gcc_unreachable (); |
fa5322fa AO |
1325 | } |
1326 | break; | |
1327 | ||
de6adfa2 N |
1328 | case 'V': |
1329 | { | |
1330 | int num = exact_log2 (INTVAL (x)); | |
1331 | gcc_assert (num >= 0); | |
1332 | fprintf (stream, "#%d", num); | |
1333 | } | |
1334 | break; | |
1335 | ||
1336 | case 'W': | |
1337 | { | |
1338 | int num = exact_log2 (~INTVAL (x)); | |
1339 | gcc_assert (num >= 0); | |
1340 | fprintf (stream, "#%d", num); | |
1341 | } | |
1342 | break; | |
1343 | ||
312209c6 | 1344 | case 'd': |
f3536097 | 1345 | gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode); |
312209c6 AO |
1346 | |
1347 | fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1); | |
1348 | break; | |
f676971a | 1349 | |
c1b92d09 | 1350 | case 'N': |
0ac78517 | 1351 | if (x == CONST0_RTX (GET_MODE (x))) |
c1b92d09 R |
1352 | { |
1353 | fprintf ((stream), "r63"); | |
1354 | break; | |
1355 | } | |
1356 | goto default_output; | |
fa5322fa | 1357 | case 'u': |
f3536097 | 1358 | if (CONST_INT_P (x)) |
c8cc4417 | 1359 | { |
fa5322fa AO |
1360 | fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1)); |
1361 | break; | |
1362 | } | |
1363 | /* Fall through. */ | |
1364 | ||
c1b92d09 | 1365 | default_output: |
bc45ade3 | 1366 | default: |
73a4d10b R |
1367 | regno = 0; |
1368 | mode = GET_MODE (x); | |
1369 | ||
bc45ade3 SC |
1370 | switch (GET_CODE (x)) |
1371 | { | |
73a4d10b R |
1372 | case TRUNCATE: |
1373 | { | |
1374 | rtx inner = XEXP (x, 0); | |
1375 | int offset = 0; | |
ef4bddc2 | 1376 | machine_mode inner_mode; |
73a4d10b R |
1377 | |
1378 | /* We might see SUBREGs with vector mode registers inside. */ | |
1379 | if (GET_CODE (inner) == SUBREG | |
1380 | && (GET_MODE_SIZE (GET_MODE (inner)) | |
1381 | == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner)))) | |
1382 | && subreg_lowpart_p (inner)) | |
1383 | inner = SUBREG_REG (inner); | |
f3536097 | 1384 | if (CONST_INT_P (inner)) |
73a4d10b R |
1385 | { |
1386 | x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x))); | |
1387 | goto default_output; | |
1388 | } | |
1389 | inner_mode = GET_MODE (inner); | |
1390 | if (GET_CODE (inner) == SUBREG | |
1391 | && (GET_MODE_SIZE (GET_MODE (inner)) | |
1392 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner)))) | |
f3536097 | 1393 | && REG_P (SUBREG_REG (inner))) |
73a4d10b R |
1394 | { |
1395 | offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)), | |
1396 | GET_MODE (SUBREG_REG (inner)), | |
1397 | SUBREG_BYTE (inner), | |
1398 | GET_MODE (inner)); | |
1399 | inner = SUBREG_REG (inner); | |
1400 | } | |
f3536097 | 1401 | if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8) |
73a4d10b R |
1402 | abort (); |
1403 | /* Floating point register pairs are always big endian; | |
30dc60c7 | 1404 | general purpose registers are 64 bit wide. */ |
73a4d10b | 1405 | regno = REGNO (inner); |
a93072ca RS |
1406 | regno = (hard_regno_nregs (regno, inner_mode) |
1407 | - hard_regno_nregs (regno, mode)) | |
73a4d10b R |
1408 | + offset; |
1409 | x = inner; | |
1410 | goto reg; | |
1411 | } | |
1412 | case SIGN_EXTEND: | |
1413 | x = XEXP (x, 0); | |
1414 | goto reg; | |
fa5322fa | 1415 | case SUBREG: |
f5b9e7c9 | 1416 | gcc_assert (SUBREG_BYTE (x) == 0 |
f3536097 | 1417 | && REG_P (SUBREG_REG (x))); |
fa5322fa AO |
1418 | |
1419 | x = SUBREG_REG (x); | |
1420 | /* Fall through. */ | |
1421 | ||
73a4d10b | 1422 | reg: |
bc45ade3 | 1423 | case REG: |
73a4d10b R |
1424 | regno += REGNO (x); |
1425 | if (FP_REGISTER_P (regno) | |
1426 | && mode == V16SFmode) | |
1427 | fprintf ((stream), "mtrx%s", reg_names[regno] + 2); | |
fa5322fa | 1428 | else if (FP_REGISTER_P (REGNO (x)) |
73a4d10b R |
1429 | && mode == V4SFmode) |
1430 | fprintf ((stream), "fv%s", reg_names[regno] + 2); | |
f3536097 | 1431 | else if (REG_P (x) |
73a4d10b R |
1432 | && mode == V2SFmode) |
1433 | fprintf ((stream), "fp%s", reg_names[regno] + 2); | |
fa5322fa | 1434 | else if (FP_REGISTER_P (REGNO (x)) |
73a4d10b R |
1435 | && GET_MODE_SIZE (mode) > 4) |
1436 | fprintf ((stream), "d%s", reg_names[regno] + 1); | |
225e4f43 | 1437 | else |
73a4d10b | 1438 | fputs (reg_names[regno], (stream)); |
bc45ade3 | 1439 | break; |
fa5322fa | 1440 | |
bc45ade3 | 1441 | case MEM: |
cc8ca59e | 1442 | output_address (GET_MODE (x), XEXP (x, 0)); |
bc45ade3 | 1443 | break; |
f676971a | 1444 | |
bc45ade3 | 1445 | default: |
f1bebab6 | 1446 | fputc ('#', stream); |
bc45ade3 SC |
1447 | output_addr_const (stream, x); |
1448 | break; | |
bc45ade3 SC |
1449 | } |
1450 | break; | |
1451 | } | |
1452 | } | |
9e94b957 NF |
1453 | |
1454 | static bool | |
1455 | sh_print_operand_punct_valid_p (unsigned char code) | |
1456 | { | |
1457 | return (code == '.' || code == '#' || code == '@' || code == ',' | |
50fe8924 | 1458 | || code == '$' || code == '\'' || code == '>'); |
9e94b957 | 1459 | } |
ef875e12 AS |
1460 | |
1461 | /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */ | |
ef875e12 AS |
1462 | static bool |
1463 | sh_asm_output_addr_const_extra (FILE *file, rtx x) | |
1464 | { | |
1465 | if (GET_CODE (x) == UNSPEC) | |
1466 | { | |
1467 | switch (XINT (x, 1)) | |
1468 | { | |
ef875e12 AS |
1469 | case UNSPEC_PIC: |
1470 | /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ | |
1471 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1472 | break; | |
1473 | case UNSPEC_GOT: | |
1474 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1475 | fputs ("@GOT", file); | |
1476 | break; | |
1477 | case UNSPEC_GOTOFF: | |
1478 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1479 | fputs ("@GOTOFF", file); | |
1480 | break; | |
1481 | case UNSPEC_PLT: | |
1482 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1483 | fputs ("@PLT", file); | |
1484 | break; | |
1485 | case UNSPEC_GOTPLT: | |
1486 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1487 | fputs ("@GOTPLT", file); | |
1488 | break; | |
fbce972a KK |
1489 | case UNSPEC_PCREL: |
1490 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1491 | fputs ("@PCREL", file); | |
1492 | break; | |
ef875e12 AS |
1493 | case UNSPEC_DTPOFF: |
1494 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1495 | fputs ("@DTPOFF", file); | |
1496 | break; | |
1497 | case UNSPEC_GOTTPOFF: | |
1498 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1499 | fputs ("@GOTTPOFF", file); | |
1500 | break; | |
1501 | case UNSPEC_TPOFF: | |
1502 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1503 | fputs ("@TPOFF", file); | |
1504 | break; | |
1505 | case UNSPEC_CALLER: | |
1506 | { | |
1507 | char name[32]; | |
1508 | /* LPCS stands for Label for PIC Call Site. */ | |
1509 | targetm.asm_out.generate_internal_label (name, "LPCS", | |
1510 | INTVAL (XVECEXP (x, 0, 0))); | |
1511 | assemble_name (file, name); | |
1512 | } | |
1513 | break; | |
ef875e12 AS |
1514 | case UNSPEC_SYMOFF: |
1515 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1516 | fputc ('-', file); | |
1517 | if (GET_CODE (XVECEXP (x, 0, 1)) == CONST) | |
1518 | { | |
1519 | fputc ('(', file); | |
1520 | output_addr_const (file, XVECEXP (x, 0, 1)); | |
1521 | fputc (')', file); | |
1522 | } | |
1523 | else | |
1524 | output_addr_const (file, XVECEXP (x, 0, 1)); | |
1525 | break; | |
1526 | case UNSPEC_PCREL_SYMOFF: | |
1527 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1528 | fputs ("-(", file); | |
1529 | output_addr_const (file, XVECEXP (x, 0, 1)); | |
1530 | fputs ("-.)", file); | |
1531 | break; | |
1e44e857 DJ |
1532 | case UNSPEC_GOTFUNCDESC: |
1533 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1534 | fputs ("@GOTFUNCDESC", file); | |
1535 | break; | |
1536 | case UNSPEC_GOTOFFFUNCDESC: | |
1537 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
1538 | fputs ("@GOTOFFFUNCDESC", file); | |
1539 | break; | |
ef875e12 AS |
1540 | default: |
1541 | return false; | |
1542 | } | |
1543 | return true; | |
1544 | } | |
1545 | else | |
1546 | return false; | |
1547 | } | |
bc45ade3 | 1548 | \f |
561642fa AP |
1549 | /* Encode symbol attributes of a SYMBOL_REF into its |
1550 | SYMBOL_REF_FLAGS. */ | |
1551 | static void | |
1552 | sh_encode_section_info (tree decl, rtx rtl, int first) | |
1553 | { | |
1554 | default_encode_section_info (decl, rtl, first); | |
1555 | ||
1556 | if (TREE_CODE (decl) == FUNCTION_DECL | |
1557 | && sh2a_function_vector_p (decl) && TARGET_SH2A) | |
1558 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION; | |
1559 | } | |
1560 | ||
bc45ade3 | 1561 | /* Prepare operands for a move define_expand; specifically, one of the |
8aa2a305 | 1562 | operands must be in a register. */ |
2ef6611e | 1563 | void |
ef4bddc2 | 1564 | prepare_move_operands (rtx operands[], machine_mode mode) |
bc45ade3 | 1565 | { |
463f02cd KK |
1566 | if ((mode == SImode || mode == DImode) |
1567 | && flag_pic | |
1568 | && ! ((mode == Pmode || mode == ptr_mode) | |
81f40b79 | 1569 | && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE)) |
1a66cd67 AO |
1570 | { |
1571 | rtx temp; | |
1572 | if (SYMBOLIC_CONST_P (operands[1])) | |
1573 | { | |
f3536097 | 1574 | if (MEM_P (operands[0])) |
1a66cd67 AO |
1575 | operands[1] = force_reg (Pmode, operands[1]); |
1576 | else | |
1577 | { | |
b3a13419 ILT |
1578 | temp = (!can_create_pseudo_p () |
1579 | ? operands[0] | |
1580 | : gen_reg_rtx (Pmode)); | |
fa5322fa | 1581 | operands[1] = legitimize_pic_address (operands[1], mode, temp); |
1a66cd67 AO |
1582 | } |
1583 | } | |
1584 | else if (GET_CODE (operands[1]) == CONST | |
1585 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1586 | && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0))) | |
1587 | { | |
b3a13419 | 1588 | temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); |
1a66cd67 | 1589 | temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0), |
fa5322fa AO |
1590 | mode, temp); |
1591 | operands[1] = expand_binop (mode, add_optab, temp, | |
1a66cd67 | 1592 | XEXP (XEXP (operands[1], 0), 1), |
b3a13419 ILT |
1593 | (!can_create_pseudo_p () |
1594 | ? temp | |
1595 | : gen_reg_rtx (Pmode)), | |
68c37dc9 | 1596 | 0, OPTAB_LIB_WIDEN); |
1a66cd67 AO |
1597 | } |
1598 | } | |
1599 | ||
e22856e8 JW |
1600 | if (! reload_in_progress && ! reload_completed) |
1601 | { | |
1602 | /* Copy the source to a register if both operands aren't registers. */ | |
1603 | if (! register_operand (operands[0], mode) | |
e1fab8ba | 1604 | && ! register_operand (operands[1], mode)) |
e22856e8 JW |
1605 | operands[1] = copy_to_mode_reg (mode, operands[1]); |
1606 | ||
f3536097 | 1607 | if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode)) |
266a2732 R |
1608 | { |
1609 | /* This is like change_address_1 (operands[0], mode, 0, 1) , | |
1610 | except that we can't use that function because it is static. */ | |
0a2aaacc KG |
1611 | rtx new_rtx = change_address (operands[0], mode, 0); |
1612 | MEM_COPY_ATTRIBUTES (new_rtx, operands[0]); | |
1613 | operands[0] = new_rtx; | |
266a2732 R |
1614 | } |
1615 | ||
e22856e8 JW |
1616 | /* This case can happen while generating code to move the result |
1617 | of a library call to the target. Reject `st r0,@(rX,rY)' because | |
1618 | reload will fail to find a spill register for rX, since r0 is already | |
1619 | being used for the source. */ | |
f1bebab6 | 1620 | else if (refers_to_regno_p (R0_REG, operands[1]) |
f3536097 | 1621 | && MEM_P (operands[0]) |
e22856e8 | 1622 | && GET_CODE (XEXP (operands[0], 0)) == PLUS |
f3536097 | 1623 | && REG_P (XEXP (XEXP (operands[0], 0), 1))) |
e22856e8 | 1624 | operands[1] = copy_to_mode_reg (mode, operands[1]); |
1e3e92b5 KK |
1625 | |
1626 | /* When the displacement addressing is used, RA will assign r0 to | |
1627 | the pseudo register operand for the QI/HImode load/store. | |
1628 | This tends to make a long live range for R0 and might cause | |
1629 | anomalous register spills in some case with LRA. See PR | |
1630 | target/55212. | |
1631 | We split possible load/store to two move insns via r0 so as to | |
1632 | shorten R0 live range. It will make some codes worse but will | |
3cad5f64 KK |
1633 | win on average for LRA. |
1634 | Also when base+index addressing is used and the index term is | |
1635 | a subreg, LRA assumes that more hard registers can be available | |
1636 | in some situation. It isn't the case for SH in the problematic | |
1637 | case. We can pre-allocate R0 for that index term to avoid | |
1638 | the issue. See PR target/66591. */ | |
1e3e92b5 | 1639 | else if (sh_lra_p () |
f1bebab6 | 1640 | && ! TARGET_SH2A |
1e3e92b5 KK |
1641 | && ((REG_P (operands[0]) && MEM_P (operands[1])) |
1642 | || (REG_P (operands[1]) && MEM_P (operands[0])))) | |
1643 | { | |
1644 | bool load_p = REG_P (operands[0]); | |
1645 | rtx reg = operands[load_p ? 0 : 1]; | |
1646 | rtx adr = XEXP (operands[load_p ? 1 : 0], 0); | |
1647 | ||
3cad5f64 KK |
1648 | if ((mode == QImode || mode == HImode) |
1649 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1e3e92b5 KK |
1650 | && GET_CODE (adr) == PLUS |
1651 | && REG_P (XEXP (adr, 0)) | |
1652 | && (REGNO (XEXP (adr, 0)) >= FIRST_PSEUDO_REGISTER) | |
1653 | && CONST_INT_P (XEXP (adr, 1)) | |
1654 | && INTVAL (XEXP (adr, 1)) != 0 | |
1655 | && sh_legitimate_index_p (mode, XEXP (adr, 1), false, true)) | |
1656 | { | |
1657 | rtx r0_rtx = gen_rtx_REG (mode, R0_REG); | |
1658 | emit_move_insn (r0_rtx, operands[1]); | |
1659 | operands[1] = r0_rtx; | |
1660 | } | |
3cad5f64 KK |
1661 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER |
1662 | && GET_CODE (adr) == PLUS | |
1663 | && REG_P (XEXP (adr, 0)) | |
1664 | && (REGNO (XEXP (adr, 0)) >= FIRST_PSEUDO_REGISTER) | |
1665 | && SUBREG_P (XEXP (adr, 1)) | |
1666 | && REG_P (SUBREG_REG (XEXP (adr, 1)))) | |
1667 | { | |
1668 | rtx r0_rtx = gen_rtx_REG (GET_MODE (XEXP (adr, 1)), R0_REG); | |
1669 | emit_move_insn (r0_rtx, XEXP (adr, 1)); | |
1670 | XEXP (adr, 1) = r0_rtx; | |
1671 | } | |
1e3e92b5 | 1672 | } |
e22856e8 | 1673 | } |
8aa2a305 | 1674 | |
463f02cd KK |
1675 | if (mode == Pmode || mode == ptr_mode) |
1676 | { | |
df4bacab OE |
1677 | rtx op0 = operands[0]; |
1678 | rtx op1 = operands[1]; | |
1679 | rtx opc; | |
6058b2fa KK |
1680 | if (GET_CODE (op1) == CONST |
1681 | && GET_CODE (XEXP (op1, 0)) == PLUS | |
81f40b79 ILT |
1682 | && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode) |
1683 | != TLS_MODEL_NONE)) | |
6058b2fa KK |
1684 | { |
1685 | opc = XEXP (XEXP (op1, 0), 1); | |
1686 | op1 = XEXP (XEXP (op1, 0), 0); | |
1687 | } | |
1688 | else | |
1689 | opc = NULL_RTX; | |
1690 | ||
df4bacab OE |
1691 | enum tls_model tls_kind; |
1692 | ||
be6b0bec KK |
1693 | if (! reload_in_progress && ! reload_completed |
1694 | && (tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE) | |
463f02cd KK |
1695 | { |
1696 | rtx tga_op1, tga_ret, tmp, tmp2; | |
1697 | ||
c2bbcb0d KK |
1698 | if (! flag_pic |
1699 | && (tls_kind == TLS_MODEL_GLOBAL_DYNAMIC | |
1700 | || tls_kind == TLS_MODEL_LOCAL_DYNAMIC | |
1701 | || tls_kind == TLS_MODEL_INITIAL_EXEC)) | |
1702 | { | |
b6d10e0b | 1703 | static int got_labelno; |
c2bbcb0d KK |
1704 | /* Don't schedule insns for getting GOT address when |
1705 | the first scheduling is enabled, to avoid spill | |
1706 | failures for R0. */ | |
1707 | if (flag_schedule_insns) | |
1708 | emit_insn (gen_blockage ()); | |
b6d10e0b | 1709 | emit_insn (gen_GOTaddr2picreg (GEN_INT (++got_labelno))); |
c2bbcb0d KK |
1710 | emit_use (gen_rtx_REG (SImode, PIC_REG)); |
1711 | if (flag_schedule_insns) | |
1712 | emit_insn (gen_blockage ()); | |
df4bacab | 1713 | } |
c2bbcb0d | 1714 | |
463f02cd KK |
1715 | switch (tls_kind) |
1716 | { | |
1717 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
1718 | tga_ret = gen_rtx_REG (Pmode, R0_REG); | |
1e44e857 DJ |
1719 | if (TARGET_FDPIC) |
1720 | emit_move_insn (gen_rtx_REG (Pmode, PIC_REG), | |
1721 | sh_get_fdpic_reg_initial_val ()); | |
13ecc9e0 | 1722 | emit_call_insn (gen_tls_global_dynamic (tga_ret, op1)); |
c2bbcb0d KK |
1723 | tmp = gen_reg_rtx (Pmode); |
1724 | emit_move_insn (tmp, tga_ret); | |
1725 | op1 = tmp; | |
463f02cd KK |
1726 | break; |
1727 | ||
1728 | case TLS_MODEL_LOCAL_DYNAMIC: | |
1729 | tga_ret = gen_rtx_REG (Pmode, R0_REG); | |
1e44e857 DJ |
1730 | if (TARGET_FDPIC) |
1731 | emit_move_insn (gen_rtx_REG (Pmode, PIC_REG), | |
1732 | sh_get_fdpic_reg_initial_val ()); | |
13ecc9e0 | 1733 | emit_call_insn (gen_tls_local_dynamic (tga_ret, op1)); |
463f02cd KK |
1734 | |
1735 | tmp = gen_reg_rtx (Pmode); | |
1736 | emit_move_insn (tmp, tga_ret); | |
1737 | ||
1738 | if (register_operand (op0, Pmode)) | |
1739 | tmp2 = op0; | |
1740 | else | |
1741 | tmp2 = gen_reg_rtx (Pmode); | |
1742 | ||
1743 | emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp)); | |
1744 | op1 = tmp2; | |
1745 | break; | |
1746 | ||
1747 | case TLS_MODEL_INITIAL_EXEC: | |
b3a13419 | 1748 | tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode); |
463f02cd | 1749 | tmp = gen_sym2GOTTPOFF (op1); |
1e44e857 DJ |
1750 | if (TARGET_FDPIC) |
1751 | emit_move_insn (gen_rtx_REG (Pmode, PIC_REG), | |
1752 | sh_get_fdpic_reg_initial_val ()); | |
463f02cd KK |
1753 | emit_insn (gen_tls_initial_exec (tga_op1, tmp)); |
1754 | op1 = tga_op1; | |
1755 | break; | |
1756 | ||
1757 | case TLS_MODEL_LOCAL_EXEC: | |
1758 | tmp2 = gen_reg_rtx (Pmode); | |
7d11d296 | 1759 | emit_insn (gen_store_gbr (tmp2)); |
463f02cd KK |
1760 | tmp = gen_reg_rtx (Pmode); |
1761 | emit_insn (gen_symTPOFF2reg (tmp, op1)); | |
463f02cd KK |
1762 | |
1763 | if (register_operand (op0, Pmode)) | |
1764 | op1 = op0; | |
1765 | else | |
1766 | op1 = gen_reg_rtx (Pmode); | |
1767 | ||
1768 | emit_insn (gen_addsi3 (op1, tmp, tmp2)); | |
1769 | break; | |
1770 | ||
1771 | default: | |
f5b9e7c9 | 1772 | gcc_unreachable (); |
463f02cd | 1773 | } |
6058b2fa KK |
1774 | if (opc) |
1775 | emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc))); | |
463f02cd KK |
1776 | operands[1] = op1; |
1777 | } | |
1778 | } | |
1e44e857 DJ |
1779 | |
1780 | if (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) | |
1781 | { | |
1782 | rtx base, offset; | |
1783 | split_const (operands[1], &base, &offset); | |
1784 | ||
1785 | if (GET_CODE (base) == SYMBOL_REF | |
1786 | && !offset_within_block_p (base, INTVAL (offset))) | |
1787 | { | |
1788 | rtx tmp = can_create_pseudo_p () ? gen_reg_rtx (mode) : operands[0]; | |
1789 | emit_move_insn (tmp, base); | |
1790 | if (!arith_operand (offset, mode)) | |
1791 | offset = force_reg (mode, offset); | |
1792 | emit_insn (gen_add3_insn (operands[0], tmp, offset)); | |
1793 | } | |
1794 | } | |
8aa2a305 JW |
1795 | } |
1796 | ||
c354951b AK |
1797 | /* Implement the canonicalize_comparison target hook for the combine |
1798 | pass. For the target hook this function is invoked via | |
1799 | sh_canonicalize_comparison. This function is also re-used to | |
1800 | canonicalize comparisons in cbranch pattern expanders. */ | |
1801 | static void | |
ff596ca1 | 1802 | sh_canonicalize_comparison (enum rtx_code& cmp, rtx& op0, rtx& op1, |
ef4bddc2 | 1803 | machine_mode mode, |
5d30dc5b | 1804 | bool op0_preserve_value) |
78d310c2 | 1805 | { |
ff596ca1 OE |
1806 | /* When invoked from within the combine pass the mode is not specified, |
1807 | so try to get it from one of the operands. */ | |
1808 | if (mode == VOIDmode) | |
1809 | mode = GET_MODE (op0); | |
1810 | if (mode == VOIDmode) | |
1811 | mode = GET_MODE (op1); | |
1812 | ||
1813 | // We need to have a mode to do something useful here. | |
1814 | if (mode == VOIDmode) | |
1815 | return; | |
1816 | ||
1817 | // Currently, we don't deal with floats here. | |
1818 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
1819 | return; | |
1820 | ||
1821 | // Make sure that the constant operand is the second operand. | |
1822 | if (CONST_INT_P (op0) && !CONST_INT_P (op1)) | |
78d310c2 | 1823 | { |
5d30dc5b OE |
1824 | if (op0_preserve_value) |
1825 | return; | |
1826 | ||
ff596ca1 OE |
1827 | std::swap (op0, op1); |
1828 | cmp = swap_condition (cmp); | |
78d310c2 | 1829 | } |
ff596ca1 OE |
1830 | |
1831 | if (CONST_INT_P (op1)) | |
78d310c2 | 1832 | { |
ff596ca1 | 1833 | /* Try to adjust the constant operand in such a way that available |
50fe8924 OE |
1834 | comparison insns can be utilized better and the constant can be |
1835 | loaded with a 'mov #imm,Rm' insn. This avoids a load from the | |
1836 | constant pool. */ | |
ff596ca1 OE |
1837 | const HOST_WIDE_INT val = INTVAL (op1); |
1838 | ||
1839 | /* x > -1 --> x >= 0 | |
1840 | x > 0xFFFFFF7F --> x >= 0xFFFFFF80 | |
1841 | x <= -1 --> x < 0 | |
1842 | x <= 0xFFFFFF7F --> x < 0xFFFFFF80 */ | |
1843 | if ((val == -1 || val == -0x81) && (cmp == GT || cmp == LE)) | |
1844 | { | |
1845 | cmp = cmp == GT ? GE : LT; | |
1846 | op1 = gen_int_mode (val + 1, mode); | |
1847 | } | |
1848 | ||
1849 | /* x >= 1 --> x > 0 | |
1850 | x >= 0x80 --> x > 0x7F | |
1851 | x < 1 --> x <= 0 | |
1852 | x < 0x80 --> x <= 0x7F */ | |
1853 | else if ((val == 1 || val == 0x80) && (cmp == GE || cmp == LT)) | |
78d310c2 | 1854 | { |
ff596ca1 OE |
1855 | cmp = cmp == GE ? GT : LE; |
1856 | op1 = gen_int_mode (val - 1, mode); | |
78d310c2 | 1857 | } |
ff596ca1 OE |
1858 | |
1859 | /* unsigned x >= 1 --> x != 0 | |
1860 | unsigned x < 1 --> x == 0 */ | |
1861 | else if (val == 1 && (cmp == GEU || cmp == LTU)) | |
78d310c2 | 1862 | { |
ff596ca1 OE |
1863 | cmp = cmp == GEU ? NE : EQ; |
1864 | op1 = CONST0_RTX (mode); | |
78d310c2 | 1865 | } |
ff596ca1 OE |
1866 | |
1867 | /* unsigned x >= 0x80 --> unsigned x > 0x7F | |
1868 | unsigned x < 0x80 --> unsigned x < 0x7F */ | |
1869 | else if (val == 0x80 && (cmp == GEU || cmp == LTU)) | |
78d310c2 | 1870 | { |
ff596ca1 OE |
1871 | cmp = cmp == GEU ? GTU : LEU; |
1872 | op1 = gen_int_mode (val - 1, mode); | |
78d310c2 | 1873 | } |
ff596ca1 OE |
1874 | |
1875 | /* unsigned x > 0 --> x != 0 | |
1876 | unsigned x <= 0 --> x == 0 */ | |
1877 | else if (val == 0 && (cmp == GTU || cmp == LEU)) | |
1878 | cmp = cmp == GTU ? NE : EQ; | |
1879 | ||
1880 | /* unsigned x > 0x7FFFFFFF --> signed x < 0 | |
1881 | unsigned x <= 0x7FFFFFFF --> signed x >= 0 */ | |
1882 | else if (mode == SImode && (cmp == GTU || cmp == LEU) | |
1883 | && val == 0x7FFFFFFF) | |
78d310c2 | 1884 | { |
ff596ca1 OE |
1885 | cmp = cmp == GTU ? LT : GE; |
1886 | op1 = const0_rtx; | |
78d310c2 | 1887 | } |
ff596ca1 OE |
1888 | |
1889 | /* unsigned x >= 0x80000000 --> signed x < 0 | |
1890 | unsigned x < 0x80000000 --> signed x >= 0 */ | |
1891 | else if (mode == SImode && (cmp == GEU || cmp == LTU) | |
1892 | && (unsigned HOST_WIDE_INT)val | |
1893 | == ((unsigned HOST_WIDE_INT)0x7FFFFFFF + 1)) | |
78d310c2 | 1894 | { |
ff596ca1 OE |
1895 | cmp = cmp == GEU ? LT : GE; |
1896 | op1 = const0_rtx; | |
78d310c2 R |
1897 | } |
1898 | } | |
ff596ca1 OE |
1899 | } |
1900 | ||
c354951b AK |
1901 | /* This function implements the canonicalize_comparison target hook. |
1902 | This wrapper around the internally used sh_canonicalize_comparison | |
1903 | function is needed to do the enum rtx_code <-> int conversion. | |
1904 | Target hooks cannot use enum rtx_code in its definition. */ | |
1905 | static void | |
1906 | sh_canonicalize_comparison (int *code, rtx *op0, rtx *op1, | |
1907 | bool op0_preserve_value) | |
1908 | { | |
1909 | enum rtx_code tmp_code = (enum rtx_code)*code; | |
1910 | sh_canonicalize_comparison (tmp_code, *op0, *op1, | |
1911 | VOIDmode, op0_preserve_value); | |
1912 | *code = (int)tmp_code; | |
1913 | } | |
50fe8924 | 1914 | |
841dbf80 OE |
1915 | /* This function implements the legitimate_combined_insn target hook, |
1916 | which the combine pass uses to early reject combined insns, before | |
1917 | it tries to recog the insn and determine its cost. */ | |
1918 | static bool | |
1919 | sh_legitimate_combined_insn (rtx_insn* insn) | |
1920 | { | |
1921 | /* Reject combinations of memory loads and zero extensions, as these | |
1922 | interfere with other combine patterns such as zero extracts and bit | |
1923 | tests. The SH2A movu.{b|w} insns are formed later in the | |
1924 | 'sh_optimize_extu_exts' pass after combine/split1. */ | |
1925 | rtx p = PATTERN (insn); | |
1926 | if (GET_CODE (p) == SET | |
1927 | && REG_P (XEXP (p, 0)) && GET_MODE (XEXP (p, 0)) == SImode | |
1928 | && GET_CODE (XEXP (p, 1)) == ZERO_EXTEND | |
1929 | && MEM_P (XEXP (XEXP (p, 1), 0))) | |
1930 | return false; | |
1931 | ||
1932 | return true; | |
1933 | } | |
1934 | ||
5d30dc5b OE |
1935 | bool |
1936 | sh_fixed_condition_code_regs (unsigned int* p1, unsigned int* p2) | |
1937 | { | |
1938 | *p1 = T_REG; | |
1939 | *p2 = INVALID_REGNUM; | |
1940 | return true; | |
1941 | } | |
1942 | ||
e22daa4b OE |
1943 | /* Try to calculate the branch distance of a conditional branch in bytes. |
1944 | ||
1945 | FIXME: Because of PR 59189 we can't use the CFG here. Instead just | |
1946 | walk from this insn into the next (fall-through) basic block and see if | |
1947 | we hit the label. */ | |
1948 | unsigned int | |
1949 | sh_cbranch_distance (rtx_insn* _cbranch_insn, unsigned int max_dist) | |
1950 | { | |
1951 | rtx_jump_insn* cbranch_insn = safe_as_a<rtx_jump_insn*> (_cbranch_insn); | |
1952 | ||
1953 | if (dump_file) | |
1954 | { | |
1955 | fprintf (dump_file, "sh_cbranch_distance insn = \n"); | |
1956 | print_rtl_single (dump_file, cbranch_insn); | |
1957 | } | |
1958 | ||
1959 | unsigned int dist = 0; | |
1960 | ||
1961 | for (rtx_insn* i = next_nonnote_insn (cbranch_insn); | |
1962 | i != NULL && dist < max_dist; i = next_nonnote_insn (i)) | |
1963 | { | |
1964 | const unsigned int i_len = get_attr_length (i); | |
1965 | dist += i_len; | |
1966 | ||
1967 | if (dump_file) | |
1968 | fprintf (dump_file, " insn %d length = %u dist = %u\n", | |
1969 | INSN_UID (i), i_len, dist); | |
1970 | ||
1971 | if (rtx_code_label* l = dyn_cast<rtx_code_label*> (i)) | |
1972 | { | |
1973 | if (l == cbranch_insn->jump_target ()) | |
1974 | { | |
1975 | if (dump_file) | |
1976 | fprintf (dump_file, " cbranch dist = %u\n", dist); | |
1977 | return dist; | |
1978 | } | |
1979 | break; | |
1980 | } | |
1981 | } | |
1982 | ||
1983 | if (dump_file) | |
1984 | fprintf (dump_file, " cbranch dist = unknown\n"); | |
1985 | ||
1986 | return unknown_cbranch_distance; | |
1987 | } | |
1988 | ||
ff596ca1 | 1989 | enum rtx_code |
ef4bddc2 | 1990 | prepare_cbranch_operands (rtx *operands, machine_mode mode, |
ff596ca1 OE |
1991 | enum rtx_code comparison) |
1992 | { | |
40d848c7 | 1993 | gcc_assert (can_create_pseudo_p ()); |
ff596ca1 OE |
1994 | |
1995 | if (comparison == LAST_AND_UNUSED_RTX_CODE) | |
1996 | comparison = GET_CODE (operands[0]); | |
ff596ca1 | 1997 | |
c354951b AK |
1998 | sh_canonicalize_comparison (comparison, operands[1], operands[2], |
1999 | mode, false); | |
ff596ca1 | 2000 | |
ff596ca1 | 2001 | rtx op1 = operands[1]; |
40d848c7 | 2002 | operands[1] = force_reg (mode, op1); |
ff596ca1 | 2003 | |
78d310c2 R |
2004 | /* When we are handling DImode comparisons, we want to keep constants so |
2005 | that we can optimize the component comparisons; however, memory loads | |
2006 | are better issued as a whole so that they can be scheduled well. | |
2007 | SImode equality comparisons allow I08 constants, but only when they | |
2008 | compare r0. Hence, if operands[1] has to be loaded from somewhere else | |
2009 | into a register, that register might as well be r0, and we allow the | |
2010 | constant. If it is already in a register, this is likely to be | |
2f8e468b | 2011 | allocated to a different hard register, thus we load the constant into |
78d310c2 R |
2012 | a register unless it is zero. */ |
2013 | if (!REG_P (operands[2]) | |
f3536097 | 2014 | && (!CONST_INT_P (operands[2]) |
78d310c2 R |
2015 | || (mode == SImode && operands[2] != CONST0_RTX (SImode) |
2016 | && ((comparison != EQ && comparison != NE) | |
2017 | || (REG_P (op1) && REGNO (op1) != R0_REG) | |
32a7ab3d | 2018 | || !satisfies_constraint_I08 (operands[2]))))) |
40d848c7 OE |
2019 | operands[2] = force_reg (mode, operands[2]); |
2020 | ||
78d310c2 R |
2021 | return comparison; |
2022 | } | |
2023 | ||
5fa396ad JH |
2024 | static void |
2025 | expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, | |
2026 | profile_probability probability) | |
78d310c2 | 2027 | { |
b4eca9c8 | 2028 | rtx (*branch_expander) (rtx) = gen_branch_true; |
78d310c2 R |
2029 | comparison = prepare_cbranch_operands (operands, SImode, comparison); |
2030 | switch (comparison) | |
2031 | { | |
2032 | case NE: case LT: case LE: case LTU: case LEU: | |
2033 | comparison = reverse_condition (comparison); | |
2034 | branch_expander = gen_branch_false; | |
2035 | default: ; | |
2036 | } | |
f7df4a84 | 2037 | emit_insn (gen_rtx_SET (get_t_reg_rtx (), |
50fe8924 OE |
2038 | gen_rtx_fmt_ee (comparison, SImode, |
2039 | operands[1], operands[2]))); | |
6cb7eb41 | 2040 | rtx_insn *jump = emit_jump_insn (branch_expander (operands[3])); |
5fa396ad JH |
2041 | if (probability.initialized_p ()) |
2042 | add_reg_br_prob_note (jump, probability); | |
2043 | } | |
2044 | ||
2045 | void | |
2046 | expand_cbranchsi4 (rtx *operands, enum rtx_code comparison) | |
2047 | { | |
2048 | expand_cbranchsi4 (operands, comparison, | |
2049 | profile_probability::uninitialized ()); | |
78d310c2 R |
2050 | } |
2051 | ||
2052 | /* ??? How should we distribute probabilities when more than one branch | |
2eff0b9d | 2053 | is generated. So far we only have some ad-hoc observations: |
78d310c2 R |
2054 | - If the operands are random, they are likely to differ in both parts. |
2055 | - If comparing items in a hash chain, the operands are random or equal; | |
2056 | operation should be EQ or NE. | |
2057 | - If items are searched in an ordered tree from the root, we can expect | |
2058 | the highpart to be unequal about half of the time; operation should be | |
2f8e468b | 2059 | an inequality comparison, operands non-constant, and overall probability |
78d310c2 R |
2060 | about 50%. Likewise for quicksort. |
2061 | - Range checks will be often made against constants. Even if we assume for | |
2062 | simplicity an even distribution of the non-constant operand over a | |
2063 | sub-range here, the same probability could be generated with differently | |
2064 | wide sub-ranges - as long as the ratio of the part of the subrange that | |
2065 | is before the threshold to the part that comes after the threshold stays | |
2066 | the same. Thus, we can't really tell anything here; | |
2067 | assuming random distribution is at least simple. | |
2068 | */ | |
78d310c2 R |
2069 | bool |
2070 | expand_cbranchdi4 (rtx *operands, enum rtx_code comparison) | |
2071 | { | |
2072 | enum rtx_code msw_taken, msw_skip, lsw_taken; | |
6cb7eb41 | 2073 | rtx_code_label *skip_label = NULL; |
78d310c2 R |
2074 | rtx op1h, op1l, op2h, op2l; |
2075 | int num_branches; | |
5fa396ad JH |
2076 | profile_probability prob, rev_prob; |
2077 | profile_probability msw_taken_prob = profile_probability::uninitialized (), | |
2078 | msw_skip_prob = profile_probability::uninitialized (), | |
2079 | lsw_taken_prob = profile_probability::uninitialized (); | |
78d310c2 R |
2080 | |
2081 | comparison = prepare_cbranch_operands (operands, DImode, comparison); | |
2082 | op1h = gen_highpart_mode (SImode, DImode, operands[1]); | |
2083 | op2h = gen_highpart_mode (SImode, DImode, operands[2]); | |
2084 | op1l = gen_lowpart (SImode, operands[1]); | |
2085 | op2l = gen_lowpart (SImode, operands[2]); | |
b757d36f | 2086 | msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE; |
78d310c2 | 2087 | prob = split_branch_probability; |
5fa396ad | 2088 | rev_prob = prob.invert (); |
78d310c2 R |
2089 | switch (comparison) |
2090 | { | |
78d310c2 | 2091 | case EQ: |
78d310c2 R |
2092 | msw_skip = NE; |
2093 | lsw_taken = EQ; | |
5fa396ad | 2094 | if (prob.initialized_p ()) |
78d310c2 | 2095 | { |
5fa396ad JH |
2096 | /* FIXME: This is not optimal. We do not really know the probablity |
2097 | that values differ by MCW only, but we should probably distribute | |
2098 | probabilities more evenly. */ | |
78d310c2 | 2099 | msw_skip_prob = rev_prob; |
5fa396ad JH |
2100 | lsw_taken_prob = prob > profile_probability::never () |
2101 | ? profile_probability::guessed_always () | |
2102 | : profile_probability::guessed_never (); | |
78d310c2 R |
2103 | } |
2104 | break; | |
2105 | case NE: | |
78d310c2 | 2106 | msw_taken = NE; |
6f8eec29 | 2107 | msw_taken_prob = prob; |
78d310c2 | 2108 | lsw_taken = NE; |
5fa396ad | 2109 | lsw_taken_prob = profile_probability::guessed_never (); |
78d310c2 R |
2110 | break; |
2111 | case GTU: case GT: | |
2112 | msw_taken = comparison; | |
f3536097 | 2113 | if (CONST_INT_P (op2l) && INTVAL (op2l) == -1) |
78d310c2 R |
2114 | break; |
2115 | if (comparison != GTU || op2h != CONST0_RTX (SImode)) | |
2116 | msw_skip = swap_condition (msw_taken); | |
2117 | lsw_taken = GTU; | |
2118 | break; | |
2119 | case GEU: case GE: | |
2120 | if (op2l == CONST0_RTX (SImode)) | |
2121 | msw_taken = comparison; | |
2122 | else | |
2123 | { | |
2124 | msw_taken = comparison == GE ? GT : GTU; | |
2125 | msw_skip = swap_condition (msw_taken); | |
2126 | lsw_taken = GEU; | |
2127 | } | |
2128 | break; | |
2129 | case LTU: case LT: | |
2130 | msw_taken = comparison; | |
2131 | if (op2l == CONST0_RTX (SImode)) | |
2132 | break; | |
2133 | msw_skip = swap_condition (msw_taken); | |
2134 | lsw_taken = LTU; | |
2135 | break; | |
2136 | case LEU: case LE: | |
f3536097 | 2137 | if (CONST_INT_P (op2l) && INTVAL (op2l) == -1) |
78d310c2 R |
2138 | msw_taken = comparison; |
2139 | else | |
2140 | { | |
2141 | lsw_taken = LEU; | |
2142 | if (comparison == LE) | |
2143 | msw_taken = LT; | |
2144 | else if (op2h != CONST0_RTX (SImode)) | |
2145 | msw_taken = LTU; | |
2146 | else | |
5f133038 KK |
2147 | { |
2148 | msw_skip = swap_condition (LTU); | |
2149 | break; | |
2150 | } | |
78d310c2 R |
2151 | msw_skip = swap_condition (msw_taken); |
2152 | } | |
2153 | break; | |
2154 | default: return false; | |
2155 | } | |
b757d36f KK |
2156 | num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE) |
2157 | + (msw_skip != LAST_AND_UNUSED_RTX_CODE) | |
2158 | + (lsw_taken != LAST_AND_UNUSED_RTX_CODE)); | |
78d310c2 R |
2159 | if (comparison != EQ && comparison != NE && num_branches > 1) |
2160 | { | |
2161 | if (!CONSTANT_P (operands[2]) | |
5fa396ad JH |
2162 | && prob.initialized_p () |
2163 | && prob.to_reg_br_prob_base () >= (int) (REG_BR_PROB_BASE * 3 / 8U) | |
2164 | && prob.to_reg_br_prob_base () <= (int) (REG_BR_PROB_BASE * 5 / 8U)) | |
78d310c2 | 2165 | { |
5fa396ad JH |
2166 | msw_taken_prob = prob.apply_scale (1, 2); |
2167 | msw_skip_prob = rev_prob.apply_scale (REG_BR_PROB_BASE, | |
2168 | rev_prob.to_reg_br_prob_base () | |
2169 | + REG_BR_PROB_BASE); | |
78d310c2 R |
2170 | lsw_taken_prob = prob; |
2171 | } | |
2172 | else | |
2173 | { | |
2174 | msw_taken_prob = prob; | |
5fa396ad | 2175 | msw_skip_prob = profile_probability::guessed_always (); |
78d310c2 R |
2176 | /* ??? If we have a constant op2h, should we use that when |
2177 | calculating lsw_taken_prob? */ | |
2178 | lsw_taken_prob = prob; | |
2179 | } | |
2180 | } | |
2181 | operands[1] = op1h; | |
2182 | operands[2] = op2h; | |
40d848c7 | 2183 | |
b757d36f | 2184 | if (msw_taken != LAST_AND_UNUSED_RTX_CODE) |
78d310c2 | 2185 | expand_cbranchsi4 (operands, msw_taken, msw_taken_prob); |
b757d36f | 2186 | if (msw_skip != LAST_AND_UNUSED_RTX_CODE) |
78d310c2 R |
2187 | { |
2188 | rtx taken_label = operands[3]; | |
2189 | ||
d60819f8 CB |
2190 | /* Operands were possibly modified, but msw_skip doesn't expect this. |
2191 | Always use the original ones. */ | |
b757d36f | 2192 | if (msw_taken != LAST_AND_UNUSED_RTX_CODE) |
d60819f8 CB |
2193 | { |
2194 | operands[1] = op1h; | |
2195 | operands[2] = op2h; | |
2196 | } | |
2197 | ||
78d310c2 R |
2198 | operands[3] = skip_label = gen_label_rtx (); |
2199 | expand_cbranchsi4 (operands, msw_skip, msw_skip_prob); | |
2200 | operands[3] = taken_label; | |
2201 | } | |
2202 | operands[1] = op1l; | |
2203 | operands[2] = op2l; | |
b757d36f | 2204 | if (lsw_taken != LAST_AND_UNUSED_RTX_CODE) |
40d848c7 | 2205 | expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob); |
b757d36f | 2206 | if (msw_skip != LAST_AND_UNUSED_RTX_CODE) |
78d310c2 R |
2207 | emit_label (skip_label); |
2208 | return true; | |
2209 | } | |
2210 | ||
b4eca9c8 OE |
2211 | /* Given an operand, return 1 if the evaluated operand plugged into an |
2212 | if_then_else will result in a branch_true, 0 if branch_false, or | |
2213 | -1 if neither nor applies. The truth table goes like this: | |
2214 | ||
2215 | op | cmpval | code | result | |
2216 | ---------+--------+---------+-------------------- | |
2217 | T (0) | 0 | EQ (1) | 0 = 0 ^ (0 == 1) | |
2218 | T (0) | 1 | EQ (1) | 1 = 0 ^ (1 == 1) | |
2219 | T (0) | 0 | NE (0) | 1 = 0 ^ (0 == 0) | |
2220 | T (0) | 1 | NE (0) | 0 = 0 ^ (1 == 0) | |
2221 | !T (1) | 0 | EQ (1) | 1 = 1 ^ (0 == 1) | |
2222 | !T (1) | 1 | EQ (1) | 0 = 1 ^ (1 == 1) | |
2223 | !T (1) | 0 | NE (0) | 0 = 1 ^ (0 == 0) | |
2224 | !T (1) | 1 | NE (0) | 1 = 1 ^ (1 == 0) */ | |
2225 | int | |
2226 | sh_eval_treg_value (rtx op) | |
2227 | { | |
48d8568e OE |
2228 | if (t_reg_operand (op, GET_MODE (op))) |
2229 | return 1; | |
2230 | if (negt_reg_operand (op, GET_MODE (op))) | |
2231 | return 0; | |
2232 | ||
2233 | rtx_code code = GET_CODE (op); | |
b4eca9c8 OE |
2234 | if ((code != EQ && code != NE) || !CONST_INT_P (XEXP (op, 1))) |
2235 | return -1; | |
2236 | ||
2237 | int cmpop = code == EQ ? 1 : 0; | |
2238 | int cmpval = INTVAL (XEXP (op, 1)); | |
2239 | if (cmpval != 0 && cmpval != 1) | |
2240 | return -1; | |
2241 | ||
2242 | int t; | |
2243 | if (t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))) | |
2244 | t = 0; | |
2245 | else if (negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))) | |
2246 | t = 1; | |
2247 | else | |
2248 | return -1; | |
2249 | ||
2250 | return t ^ (cmpval == cmpop); | |
2251 | } | |
2252 | ||
3a2317d1 OE |
2253 | /* Emit INSN, possibly in a PARALLEL with an USE/CLOBBER of FPSCR bits in case |
2254 | of floating-point comparisons. */ | |
f90b7a5a | 2255 | static void |
ef4bddc2 | 2256 | sh_emit_set_t_insn (rtx insn, machine_mode mode) |
f90b7a5a | 2257 | { |
3a2317d1 OE |
2258 | if (TARGET_FPU_ANY && GET_MODE_CLASS (mode) == MODE_FLOAT |
2259 | && GET_CODE (insn) != PARALLEL) | |
f90b7a5a PB |
2260 | { |
2261 | insn = gen_rtx_PARALLEL (VOIDmode, | |
3a2317d1 OE |
2262 | gen_rtvec (3, insn, |
2263 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, FPSCR_STAT_REG)), | |
2264 | gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, FPSCR_MODES_REG)))); | |
f90b7a5a | 2265 | } |
3a2317d1 | 2266 | emit_insn (insn); |
f90b7a5a PB |
2267 | } |
2268 | ||
8aa2a305 | 2269 | /* Prepare the operands for an scc instruction; make sure that the |
f90b7a5a PB |
2270 | compare has been done and the result is in T_REG. */ |
2271 | void | |
2272 | sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1) | |
8aa2a305 | 2273 | { |
78ff60c1 | 2274 | rtx t_reg = get_t_reg_rtx (); |
8aa2a305 JW |
2275 | enum rtx_code oldcode = code; |
2276 | ||
2277 | /* First need a compare insn. */ | |
2278 | switch (code) | |
bc45ade3 | 2279 | { |
8aa2a305 JW |
2280 | case NE: |
2281 | /* It isn't possible to handle this case. */ | |
f5b9e7c9 | 2282 | gcc_unreachable (); |
8aa2a305 JW |
2283 | case LT: |
2284 | code = GT; | |
2285 | break; | |
2286 | case LE: | |
2287 | code = GE; | |
2288 | break; | |
2289 | case LTU: | |
2290 | code = GTU; | |
2291 | break; | |
2292 | case LEU: | |
2293 | code = GEU; | |
2294 | break; | |
10db12e0 R |
2295 | default: |
2296 | break; | |
bc45ade3 | 2297 | } |
8aa2a305 | 2298 | if (code != oldcode) |
6f23a2d0 | 2299 | std::swap (op0, op1); |
b9654711 | 2300 | |
df4bacab | 2301 | machine_mode mode = GET_MODE (op0); |
9374bd85 | 2302 | if (mode == VOIDmode) |
f90b7a5a | 2303 | mode = GET_MODE (op1); |
9374bd85 | 2304 | |
f90b7a5a | 2305 | op0 = force_reg (mode, op0); |
1245df60 | 2306 | if ((code != EQ && code != NE |
f90b7a5a | 2307 | && (op1 != const0_rtx |
1245df60 | 2308 | || code == GTU || code == GEU || code == LTU || code == LEU)) |
f90b7a5a | 2309 | || (mode == DImode && op1 != const0_rtx) |
3a8699c7 | 2310 | || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)) |
f90b7a5a | 2311 | op1 = force_reg (mode, op1); |
0d7e008e | 2312 | |
f7df4a84 | 2313 | sh_emit_set_t_insn (gen_rtx_SET (t_reg, |
f90b7a5a PB |
2314 | gen_rtx_fmt_ee (code, SImode, op0, op1)), |
2315 | mode); | |
2316 | } | |
0d7e008e | 2317 | |
8aa2a305 | 2318 | /* Called from the md file, set up the operands of a compare instruction. */ |
8aa2a305 | 2319 | void |
ef4bddc2 | 2320 | sh_emit_compare_and_branch (rtx *operands, machine_mode mode) |
bc45ade3 | 2321 | { |
f90b7a5a PB |
2322 | enum rtx_code code = GET_CODE (operands[0]); |
2323 | enum rtx_code branch_code; | |
2324 | rtx op0 = operands[1]; | |
2325 | rtx op1 = operands[2]; | |
6f23a2d0 | 2326 | rtx insn; |
f90b7a5a PB |
2327 | bool need_ccmpeq = false; |
2328 | ||
2329 | if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
bc45ade3 | 2330 | { |
f90b7a5a PB |
2331 | op0 = force_reg (mode, op0); |
2332 | op1 = force_reg (mode, op1); | |
bc45ade3 | 2333 | } |
f90b7a5a | 2334 | else |
1245df60 | 2335 | { |
f90b7a5a | 2336 | if (code != EQ || mode == DImode) |
50fe8924 OE |
2337 | { |
2338 | /* Force args into regs, since we can't use constants here. */ | |
2339 | op0 = force_reg (mode, op0); | |
2340 | if (op1 != const0_rtx || code == GTU || code == GEU) | |
f90b7a5a PB |
2341 | op1 = force_reg (mode, op1); |
2342 | } | |
1245df60 | 2343 | } |
f90b7a5a PB |
2344 | |
2345 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
2346 | { | |
2347 | if (code == LT | |
2348 | || (code == LE && TARGET_IEEE && TARGET_SH2E) | |
2349 | || (code == GE && !(TARGET_IEEE && TARGET_SH2E))) | |
2350 | { | |
6f23a2d0 | 2351 | std::swap (op0, op1); |
f90b7a5a PB |
2352 | code = swap_condition (code); |
2353 | } | |
2354 | ||
2355 | /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */ | |
2356 | if (code == GE) | |
2357 | { | |
2358 | gcc_assert (TARGET_IEEE && TARGET_SH2E); | |
50fe8924 | 2359 | need_ccmpeq = true; |
f90b7a5a PB |
2360 | code = GT; |
2361 | } | |
2362 | ||
2363 | /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed | |
2364 | to EQ/GT respectively. */ | |
2365 | gcc_assert (code == EQ || code == GT || code == NE || code == LE); | |
2366 | } | |
2367 | ||
2368 | switch (code) | |
2369 | { | |
2370 | case EQ: | |
2371 | case GT: | |
2372 | case GE: | |
2373 | case GTU: | |
2374 | case GEU: | |
2375 | branch_code = code; | |
2376 | break; | |
2377 | case NE: | |
2378 | case LT: | |
2379 | case LE: | |
2380 | case LTU: | |
2381 | case LEU: | |
2382 | branch_code = reverse_condition (code); | |
2383 | break; | |
2384 | default: | |
2385 | gcc_unreachable (); | |
2386 | } | |
2387 | ||
f7df4a84 | 2388 | insn = gen_rtx_SET (get_t_reg_rtx (), |
f90b7a5a PB |
2389 | gen_rtx_fmt_ee (branch_code, SImode, op0, op1)); |
2390 | ||
2391 | sh_emit_set_t_insn (insn, mode); | |
2392 | if (need_ccmpeq) | |
2393 | sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode); | |
2394 | ||
2395 | if (branch_code == code) | |
b4eca9c8 | 2396 | emit_jump_insn (gen_branch_true (operands[3])); |
1245df60 | 2397 | else |
b4eca9c8 | 2398 | emit_jump_insn (gen_branch_false (operands[3])); |
f90b7a5a PB |
2399 | } |
2400 | ||
2401 | void | |
ef4bddc2 | 2402 | sh_emit_compare_and_set (rtx *operands, machine_mode mode) |
f90b7a5a PB |
2403 | { |
2404 | enum rtx_code code = GET_CODE (operands[1]); | |
2405 | rtx op0 = operands[2]; | |
2406 | rtx op1 = operands[3]; | |
6cb7eb41 | 2407 | rtx_code_label *lab = NULL; |
f90b7a5a | 2408 | bool invert = false; |
f90b7a5a PB |
2409 | |
2410 | op0 = force_reg (mode, op0); | |
2411 | if ((code != EQ && code != NE | |
2412 | && (op1 != const0_rtx | |
2413 | || code == GTU || code == GEU || code == LTU || code == LEU)) | |
2414 | || (mode == DImode && op1 != const0_rtx) | |
2415 | || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)) | |
2416 | op1 = force_reg (mode, op1); | |
2417 | ||
2418 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
225e4f43 | 2419 | { |
f90b7a5a PB |
2420 | if (code == LT || code == LE) |
2421 | { | |
6f23a2d0 | 2422 | std::swap (op0, op1); |
f90b7a5a | 2423 | code = swap_condition (code); |
f90b7a5a PB |
2424 | } |
2425 | if (code == GE) | |
50fe8924 OE |
2426 | { |
2427 | if (TARGET_IEEE) | |
2428 | { | |
2429 | lab = gen_label_rtx (); | |
2430 | sh_emit_scc_to_t (EQ, op0, op1); | |
2431 | emit_jump_insn (gen_branch_true (lab)); | |
2432 | code = GT; | |
2433 | } | |
2434 | else | |
2435 | { | |
2436 | code = LT; | |
2437 | invert = true; | |
f90b7a5a | 2438 | } |
50fe8924 | 2439 | } |
225e4f43 | 2440 | } |
f90b7a5a PB |
2441 | |
2442 | if (code == NE) | |
2443 | { | |
2444 | code = EQ; | |
2445 | invert = true; | |
2446 | } | |
2447 | ||
2448 | sh_emit_scc_to_t (code, op0, op1); | |
2449 | if (lab) | |
2450 | emit_label (lab); | |
2451 | if (invert) | |
78ff60c1 | 2452 | emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ())); |
225e4f43 | 2453 | else |
78ff60c1 | 2454 | emit_move_insn (operands[0], get_t_reg_rtx ()); |
bc45ade3 SC |
2455 | } |
2456 | \f | |
16bea517 | 2457 | /* Functions to output assembly code. */ |
bc45ade3 | 2458 | |
b9654711 | 2459 | /* Return a sequence of instructions to perform DI or DF move. |
bc45ade3 | 2460 | |
b9654711 | 2461 | Since the SH cannot move a DI or DF in one instruction, we have |
16bea517 | 2462 | to take care when we see overlapping source and dest registers. */ |
318881c0 | 2463 | const char * |
cf277499 | 2464 | output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[], |
ef4bddc2 | 2465 | machine_mode mode) |
bc45ade3 | 2466 | { |
b9654711 SC |
2467 | rtx dst = operands[0]; |
2468 | rtx src = operands[1]; | |
b9654711 | 2469 | |
f3536097 | 2470 | if (MEM_P (dst) |
16bea517 | 2471 | && GET_CODE (XEXP (dst, 0)) == PRE_DEC) |
6387ab2c OE |
2472 | return "mov.l %T1,%0" "\n" |
2473 | " mov.l %1,%0"; | |
8aa2a305 | 2474 | |
b9654711 SC |
2475 | if (register_operand (dst, mode) |
2476 | && register_operand (src, mode)) | |
bc45ade3 | 2477 | { |
b9654711 | 2478 | if (REGNO (src) == MACH_REG) |
6387ab2c OE |
2479 | return "sts mach,%S0" "\n" |
2480 | " sts macl,%R0"; | |
bc45ade3 | 2481 | |
8aa2a305 JW |
2482 | /* When mov.d r1,r2 do r2->r3 then r1->r2; |
2483 | when mov.d r1,r0 do r1->r0 then r2->r1. */ | |
b9654711 | 2484 | if (REGNO (src) + 1 == REGNO (dst)) |
6387ab2c OE |
2485 | return "mov %T1,%T0" "\n" |
2486 | " mov %1,%0"; | |
b9654711 | 2487 | else |
6387ab2c OE |
2488 | return "mov %1,%0" "\n" |
2489 | " mov %T1,%T0"; | |
b9654711 | 2490 | } |
f3536097 | 2491 | else if (CONST_INT_P (src)) |
bc45ade3 | 2492 | { |
8aa2a305 JW |
2493 | if (INTVAL (src) < 0) |
2494 | output_asm_insn ("mov #-1,%S0", operands); | |
bc45ade3 | 2495 | else |
8aa2a305 | 2496 | output_asm_insn ("mov #0,%S0", operands); |
bc45ade3 | 2497 | |
8aa2a305 | 2498 | return "mov %1,%R0"; |
0d7e008e | 2499 | } |
f3536097 | 2500 | else if (MEM_P (src)) |
bc45ade3 | 2501 | { |
8aa2a305 | 2502 | int ptrreg = -1; |
b9654711 SC |
2503 | int dreg = REGNO (dst); |
2504 | rtx inside = XEXP (src, 0); | |
bc45ade3 | 2505 | |
f5b9e7c9 | 2506 | switch (GET_CODE (inside)) |
bc45ade3 | 2507 | { |
f5b9e7c9 NS |
2508 | case REG: |
2509 | ptrreg = REGNO (inside); | |
2510 | break; | |
2511 | ||
2512 | case SUBREG: | |
2513 | ptrreg = subreg_regno (inside); | |
2514 | break; | |
2515 | ||
2516 | case PLUS: | |
8aa2a305 JW |
2517 | ptrreg = REGNO (XEXP (inside, 0)); |
2518 | /* ??? A r0+REG address shouldn't be possible here, because it isn't | |
2519 | an offsettable address. Unfortunately, offsettable addresses use | |
2520 | QImode to check the offset, and a QImode offsettable address | |
2521 | requires r0 for the other operand, which is not currently | |
2522 | supported, so we can't use the 'o' constraint. | |
2523 | Thus we must check for and handle r0+REG addresses here. | |
2524 | We punt for now, since this is likely very rare. */ | |
f3536097 | 2525 | gcc_assert (!REG_P (XEXP (inside, 1))); |
f5b9e7c9 NS |
2526 | break; |
2527 | ||
2528 | case LABEL_REF: | |
6387ab2c OE |
2529 | return "mov.l %1,%0" "\n" |
2530 | " mov.l %1+4,%T0"; | |
f5b9e7c9 | 2531 | case POST_INC: |
6387ab2c OE |
2532 | return "mov.l %1,%0" "\n" |
2533 | " mov.l %1,%T0"; | |
f5b9e7c9 NS |
2534 | default: |
2535 | gcc_unreachable (); | |
bc45ade3 | 2536 | } |
bc45ade3 | 2537 | |
8aa2a305 JW |
2538 | /* Work out the safe way to copy. Copy into the second half first. */ |
2539 | if (dreg == ptrreg) | |
6387ab2c OE |
2540 | return "mov.l %T1,%T0" "\n" |
2541 | " mov.l %1,%0"; | |
bc45ade3 SC |
2542 | } |
2543 | ||
6387ab2c OE |
2544 | return "mov.l %1,%0" "\n" |
2545 | " mov.l %T1,%T0"; | |
bc45ade3 SC |
2546 | } |
2547 | ||
8aa2a305 JW |
2548 | /* Print an instruction which would have gone into a delay slot after |
2549 | another instruction, but couldn't because the other instruction expanded | |
2550 | into a sequence where putting the slot insn at the end wouldn't work. */ | |
8aa2a305 | 2551 | static void |
7fa55ff6 | 2552 | print_slot (rtx_sequence *seq) |
8aa2a305 | 2553 | { |
7fa55ff6 | 2554 | final_scan_insn (seq->insn (1), asm_out_file, optimize, 1, NULL); |
b9654711 | 2555 | |
4654c0cf | 2556 | seq->insn (1)->set_deleted (); |
8aa2a305 | 2557 | } |
0d7e008e | 2558 | |
318881c0 | 2559 | const char * |
6cb7eb41 | 2560 | output_far_jump (rtx_insn *insn, rtx op) |
0d7e008e | 2561 | { |
0a2aaacc | 2562 | struct { rtx lab, reg, op; } this_jmp; |
19f8b229 | 2563 | rtx_code_label *braf_base_lab = NULL; |
318881c0 | 2564 | const char *jump; |
1245df60 | 2565 | int far; |
9d98a694 | 2566 | int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn)); |
6cb7eb41 | 2567 | rtx_insn *prev; |
0d7e008e | 2568 | |
0a2aaacc | 2569 | this_jmp.lab = gen_label_rtx (); |
b9654711 | 2570 | |
1a953d0f R |
2571 | if (TARGET_SH2 |
2572 | && offset >= -32764 | |
4e417af3 KK |
2573 | && offset - get_attr_length (insn) <= 32766 |
2574 | && ! CROSSING_JUMP_P (insn)) | |
1245df60 R |
2575 | { |
2576 | far = 0; | |
6387ab2c OE |
2577 | jump = "mov.w %O0,%1" "\n" |
2578 | " braf %1"; | |
1245df60 R |
2579 | } |
2580 | else | |
2581 | { | |
2582 | far = 1; | |
1a66cd67 | 2583 | if (flag_pic) |
e6dfd05f AO |
2584 | { |
2585 | if (TARGET_SH2) | |
6387ab2c OE |
2586 | jump = "mov.l %O0,%1" "\n" |
2587 | " braf %1"; | |
e6dfd05f | 2588 | else |
6387ab2c OE |
2589 | jump = "mov.l r0,@-r15" "\n" |
2590 | " mova %O0,r0" "\n" | |
2591 | " mov.l @r0,%1" "\n" | |
2592 | " add r0,%1" "\n" | |
2593 | " mov.l @r15+,r0" "\n" | |
2594 | " jmp @%1"; | |
e6dfd05f | 2595 | } |
1a66cd67 | 2596 | else |
6387ab2c OE |
2597 | jump = "mov.l %O0,%1" "\n" |
2598 | " jmp @%1"; | |
1245df60 R |
2599 | } |
2600 | /* If we have a scratch register available, use it. */ | |
f3536097 | 2601 | if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn))) |
10f4f635 | 2602 | && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch) |
1245df60 | 2603 | { |
0a2aaacc KG |
2604 | this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0)); |
2605 | if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2) | |
6387ab2c OE |
2606 | jump = "mov.l r1,@-r15" "\n" |
2607 | " mova %O0,r0" "\n" | |
2608 | " mov.l @r0,r1" "\n" | |
2609 | " add r1,r0" "\n" | |
2610 | " mov.l @r15+,r1" "\n" | |
2611 | " jmp @%1"; | |
0a2aaacc | 2612 | output_asm_insn (jump, &this_jmp.lab); |
1245df60 R |
2613 | if (dbr_sequence_length ()) |
2614 | print_slot (final_sequence); | |
2615 | else | |
2616 | output_asm_insn ("nop", 0); | |
2617 | } | |
2618 | else | |
2619 | { | |
2620 | /* Output the delay slot insn first if any. */ | |
2621 | if (dbr_sequence_length ()) | |
2622 | print_slot (final_sequence); | |
2623 | ||
0a2aaacc | 2624 | this_jmp.reg = gen_rtx_REG (SImode, 13); |
e1fab8ba | 2625 | output_asm_insn ("mov.l r13,@-r15", 0); |
0a2aaacc | 2626 | output_asm_insn (jump, &this_jmp.lab); |
e1fab8ba | 2627 | output_asm_insn ("mov.l @r15+,r13", 0); |
1245df60 | 2628 | } |
e6dfd05f AO |
2629 | if (far && flag_pic && TARGET_SH2) |
2630 | { | |
2631 | braf_base_lab = gen_label_rtx (); | |
4977bab6 | 2632 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
e6dfd05f AO |
2633 | CODE_LABEL_NUMBER (braf_base_lab)); |
2634 | } | |
1245df60 R |
2635 | if (far) |
2636 | output_asm_insn (".align 2", 0); | |
0a2aaacc KG |
2637 | (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab)); |
2638 | this_jmp.op = op; | |
1a66cd67 | 2639 | if (far && flag_pic) |
e6dfd05f AO |
2640 | { |
2641 | if (TARGET_SH2) | |
0a2aaacc KG |
2642 | this_jmp.lab = braf_base_lab; |
2643 | output_asm_insn (".long %O2-%O0", &this_jmp.lab); | |
e6dfd05f | 2644 | } |
1a66cd67 | 2645 | else |
0a2aaacc | 2646 | output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab); |
0d7e008e SC |
2647 | return ""; |
2648 | } | |
bc45ade3 | 2649 | |
8aa2a305 JW |
2650 | /* Local label counter, used for constants in the pool and inside |
2651 | pattern branches. */ | |
8aa2a305 JW |
2652 | static int lf = 100; |
2653 | ||
2654 | /* Output code for ordinary branches. */ | |
318881c0 | 2655 | const char * |
84034c69 | 2656 | output_branch (int logic, rtx_insn *insn, rtx *operands) |
bc45ade3 | 2657 | { |
afbc5d86 | 2658 | switch (get_attr_length (insn)) |
bc45ade3 | 2659 | { |
33f7f353 JR |
2660 | case 6: |
2661 | /* This can happen if filling the delay slot has caused a forward | |
2662 | branch to exceed its range (we could reverse it, but only | |
2663 | when we know we won't overextend other branches; this should | |
2664 | best be handled by relaxation). | |
2665 | It can also happen when other condbranches hoist delay slot insn | |
1245df60 R |
2666 | from their destination, thus leading to code size increase. |
2667 | But the branch will still be in the range -4092..+4098 bytes. */ | |
33f7f353 | 2668 | if (! TARGET_RELAX) |
1245df60 | 2669 | { |
33f7f353 JR |
2670 | int label = lf++; |
2671 | /* The call to print_slot will clobber the operands. */ | |
2672 | rtx op0 = operands[0]; | |
f676971a | 2673 | |
33f7f353 JR |
2674 | /* If the instruction in the delay slot is annulled (true), then |
2675 | there is no delay slot where we can put it now. The only safe | |
2676 | place for it is after the label. final will do that by default. */ | |
f676971a | 2677 | |
33f7f353 | 2678 | if (final_sequence |
84034c69 DM |
2679 | && ! INSN_ANNULLED_BRANCH_P (final_sequence->insn (0)) |
2680 | && get_attr_length (final_sequence->insn (1))) | |
33f7f353 | 2681 | { |
afbc5d86 | 2682 | asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t", |
33f7f353 JR |
2683 | ASSEMBLER_DIALECT ? "/" : ".", label); |
2684 | print_slot (final_sequence); | |
2685 | } | |
2686 | else | |
afbc5d86 | 2687 | asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label); |
f676971a | 2688 | |
afbc5d86 R |
2689 | output_asm_insn ("bra\t%l0", &op0); |
2690 | fprintf (asm_out_file, "\tnop\n"); | |
832a3292 | 2691 | (*targetm.asm_out.internal_label) (asm_out_file, "LF", label); |
f676971a | 2692 | |
33f7f353 | 2693 | return ""; |
1245df60 | 2694 | } |
133634de | 2695 | /* FALLTHRU */ |
33f7f353 JR |
2696 | /* When relaxing, handle this like a short branch. The linker |
2697 | will fix it up if it still doesn't fit after relaxation. */ | |
2698 | case 2: | |
2699 | return logic ? "bt%.\t%l0" : "bf%.\t%l0"; | |
3a8699c7 AO |
2700 | |
2701 | /* These are for SH2e, in which we have to account for the | |
2702 | extra nop because of the hardware bug in annulled branches. */ | |
2703 | case 8: | |
2704 | if (! TARGET_RELAX) | |
2705 | { | |
2706 | int label = lf++; | |
2707 | ||
f5b9e7c9 NS |
2708 | gcc_assert (!final_sequence |
2709 | || !(INSN_ANNULLED_BRANCH_P | |
2710 | (XVECEXP (final_sequence, 0, 0)))); | |
3a8699c7 AO |
2711 | asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n", |
2712 | logic ? "f" : "t", | |
2713 | ASSEMBLER_DIALECT ? "/" : ".", label); | |
2714 | fprintf (asm_out_file, "\tnop\n"); | |
2715 | output_asm_insn ("bra\t%l0", operands); | |
2716 | fprintf (asm_out_file, "\tnop\n"); | |
2717 | (*targetm.asm_out.internal_label) (asm_out_file, "LF", label); | |
2718 | ||
2719 | return ""; | |
2720 | } | |
133634de | 2721 | /* FALLTHRU */ |
3a8699c7 AO |
2722 | case 4: |
2723 | { | |
2724 | char buffer[10]; | |
f676971a | 2725 | |
3a8699c7 AO |
2726 | sprintf (buffer, "b%s%ss\t%%l0", |
2727 | logic ? "t" : "f", | |
2728 | ASSEMBLER_DIALECT ? "/" : "."); | |
2729 | output_asm_insn (buffer, &operands[0]); | |
2730 | return "nop"; | |
2731 | } | |
2732 | ||
33f7f353 | 2733 | default: |
afbc5d86 R |
2734 | /* There should be no longer branches now - that would |
2735 | indicate that something has destroyed the branches set | |
2736 | up in machine_dependent_reorg. */ | |
f5b9e7c9 | 2737 | gcc_unreachable (); |
1245df60 | 2738 | } |
1245df60 | 2739 | } |
bc45ade3 | 2740 | |
0a2aaacc | 2741 | /* Output a code sequence for INSN using TEMPL with OPERANDS; but before, |
78d310c2 R |
2742 | fill in operands 9 as a label to the successor insn. |
2743 | We try to use jump threading where possible. | |
2744 | IF CODE matches the comparison in the IF_THEN_ELSE of a following jump, | |
2745 | we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means | |
2746 | follow jmp and bt, if the address is in range. */ | |
318881c0 | 2747 | const char * |
0a2aaacc | 2748 | output_branchy_insn (enum rtx_code code, const char *templ, |
6cb7eb41 | 2749 | rtx_insn *insn, rtx *operands) |
1245df60 | 2750 | { |
6cb7eb41 | 2751 | rtx_insn *next_insn = NEXT_INSN (insn); |
79b2746a | 2752 | |
f3536097 | 2753 | if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn)) |
1245df60 R |
2754 | { |
2755 | rtx src = SET_SRC (PATTERN (next_insn)); | |
2756 | if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code) | |
2757 | { | |
2758 | /* Following branch not taken */ | |
17f385d8 DM |
2759 | rtx_code_label *lab = gen_label_rtx (); |
2760 | emit_label_after (lab, next_insn); | |
2761 | INSN_ADDRESSES_NEW (lab, | |
9d98a694 AO |
2762 | INSN_ADDRESSES (INSN_UID (next_insn)) |
2763 | + get_attr_length (next_insn)); | |
17f385d8 | 2764 | operands[9] = lab; |
0a2aaacc | 2765 | return templ; |
1245df60 R |
2766 | } |
2767 | else | |
2768 | { | |
33f7f353 | 2769 | int offset = (branch_dest (next_insn) |
9d98a694 | 2770 | - INSN_ADDRESSES (INSN_UID (next_insn)) + 4); |
33f7f353 | 2771 | if (offset >= -252 && offset <= 258) |
1245df60 R |
2772 | { |
2773 | if (GET_CODE (src) == IF_THEN_ELSE) | |
2774 | /* branch_true */ | |
2775 | src = XEXP (src, 1); | |
2776 | operands[9] = src; | |
0a2aaacc | 2777 | return templ; |
1245df60 R |
2778 | } |
2779 | } | |
bc45ade3 | 2780 | } |
17f385d8 DM |
2781 | rtx_code_label *lab = gen_label_rtx (); |
2782 | emit_label_after (lab, insn); | |
2783 | INSN_ADDRESSES_NEW (lab, | |
9d98a694 AO |
2784 | INSN_ADDRESSES (INSN_UID (insn)) |
2785 | + get_attr_length (insn)); | |
17f385d8 | 2786 | operands[9] = lab; |
0a2aaacc | 2787 | return templ; |
1245df60 | 2788 | } |
e4fa6b06 | 2789 | |
318881c0 | 2790 | const char * |
6cb7eb41 | 2791 | output_ieee_ccmpeq (rtx_insn *insn, rtx *operands) |
1245df60 | 2792 | { |
6387ab2c OE |
2793 | return output_branchy_insn (NE, "bt %l9" "\n" |
2794 | " fcmp/eq %1,%0", | |
9fd0c419 | 2795 | insn, operands); |
bc45ade3 | 2796 | } |
8e87e161 | 2797 | \f |
1bc7c5b6 | 2798 | /* Output the start of the assembler file. */ |
1bc7c5b6 | 2799 | static void |
cf277499 | 2800 | sh_file_start (void) |
bc45ade3 | 2801 | { |
1bc7c5b6 ZW |
2802 | default_file_start (); |
2803 | ||
2804 | if (TARGET_ELF) | |
2805 | /* We need to show the text section with the proper | |
2806 | attributes as in TEXT_SECTION_ASM_OP, before dwarf2out | |
0fe7abcc | 2807 | emits it without attributes in TEXT_SECTION_ASM_OP, else GAS |
1bc7c5b6 ZW |
2808 | will complain. We can teach GAS specifically about the |
2809 | default attributes for our choice of text section, but | |
2810 | then we would have to change GAS again if/when we change | |
2811 | the text section name. */ | |
2812 | fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP); | |
2813 | else | |
2814 | /* Switch to the data section so that the coffsem symbol | |
2815 | isn't in the text section. */ | |
d6b5193b | 2816 | switch_to_section (data_section); |
b9654711 | 2817 | |
8aa2a305 | 2818 | if (TARGET_LITTLE_ENDIAN) |
1bc7c5b6 | 2819 | fputs ("\t.little\n", asm_out_file); |
bc45ade3 | 2820 | } |
0d7e008e | 2821 | \f |
1e44e857 DJ |
2822 | /* Implementation of TARGET_ASM_INTEGER for SH. Pointers to functions |
2823 | need to be output as pointers to function descriptors for | |
2824 | FDPIC. */ | |
2825 | ||
2826 | static bool | |
2827 | sh_assemble_integer (rtx value, unsigned int size, int aligned_p) | |
2828 | { | |
2829 | if (TARGET_FDPIC && size == UNITS_PER_WORD | |
2830 | && GET_CODE (value) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (value)) | |
2831 | { | |
2832 | fputs ("\t.long\t", asm_out_file); | |
2833 | output_addr_const (asm_out_file, value); | |
2834 | fputs ("@FUNCDESC\n", asm_out_file); | |
2835 | return true; | |
2836 | } | |
2837 | return default_assemble_integer (value, size, aligned_p); | |
2838 | } | |
2839 | \f | |
9f3a9a08 | 2840 | /* Check if PAT includes UNSPEC_CALLER unspec pattern. */ |
9f3a9a08 | 2841 | static bool |
cf277499 | 2842 | unspec_caller_rtx_p (rtx pat) |
9f3a9a08 | 2843 | { |
dc3ba671 | 2844 | rtx base, offset; |
dc3ba671 | 2845 | split_const (pat, &base, &offset); |
df4bacab | 2846 | |
dc3ba671 | 2847 | if (GET_CODE (base) == UNSPEC) |
9f3a9a08 | 2848 | { |
dc3ba671 | 2849 | if (XINT (base, 1) == UNSPEC_CALLER) |
9f3a9a08 | 2850 | return true; |
df4bacab | 2851 | for (int i = 0; i < XVECLEN (base, 0); i++) |
dc3ba671 RS |
2852 | if (unspec_caller_rtx_p (XVECEXP (base, 0, i))) |
2853 | return true; | |
9f3a9a08 | 2854 | } |
9f3a9a08 KK |
2855 | return false; |
2856 | } | |
2857 | ||
2858 | /* Indicate that INSN cannot be duplicated. This is true for insn | |
569b7f6a | 2859 | that generates a unique label. */ |
9f3a9a08 | 2860 | static bool |
ac44248e | 2861 | sh_cannot_copy_insn_p (rtx_insn *insn) |
9f3a9a08 | 2862 | { |
9f3a9a08 KK |
2863 | if (!reload_completed || !flag_pic) |
2864 | return false; | |
2865 | ||
f3536097 | 2866 | if (!NONJUMP_INSN_P (insn)) |
9f3a9a08 KK |
2867 | return false; |
2868 | if (asm_noperands (insn) >= 0) | |
2869 | return false; | |
2870 | ||
df4bacab | 2871 | rtx pat = PATTERN (insn); |
1e44e857 DJ |
2872 | |
2873 | if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == USE) | |
2874 | return false; | |
2875 | ||
2876 | if (TARGET_FDPIC && GET_CODE (pat) == PARALLEL) | |
2877 | { | |
2878 | rtx t = XVECEXP (pat, 0, XVECLEN (pat, 0) - 1); | |
2879 | if (GET_CODE (t) == USE && unspec_caller_rtx_p (XEXP (t, 0))) | |
2880 | return true; | |
2881 | } | |
2882 | ||
9f3a9a08 KK |
2883 | if (GET_CODE (pat) != SET) |
2884 | return false; | |
2885 | pat = SET_SRC (pat); | |
2886 | ||
2887 | if (unspec_caller_rtx_p (pat)) | |
2888 | return true; | |
2889 | ||
2890 | return false; | |
2891 | } | |
2892 | \f | |
70d4736c | 2893 | /* Number of instructions used to make an arithmetic right shift by N. */ |
0b5826ac | 2894 | static const char ashiftrt_insns[] = |
16bea517 JW |
2895 | { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2}; |
2896 | ||
70d4736c OE |
2897 | /* Description of a logical left or right shift, when expanded to a sequence |
2898 | of 1/2/8/16 shifts. | |
2899 | Notice that one bit right shifts clobber the T bit. One bit left shifts | |
2900 | are done with an 'add Rn,Rm' insn and thus do not clobber the T bit. */ | |
2901 | enum | |
2902 | { | |
2903 | ASHL_CLOBBERS_T = 1 << 0, | |
2904 | LSHR_CLOBBERS_T = 1 << 1 | |
2905 | }; | |
2906 | ||
2907 | struct ashl_lshr_sequence | |
2908 | { | |
2909 | char insn_count; | |
f3101b31 | 2910 | signed char amount[6]; |
70d4736c OE |
2911 | char clobbers_t; |
2912 | }; | |
f676971a | 2913 | |
70d4736c OE |
2914 | static const struct ashl_lshr_sequence ashl_lshr_seq[32] = |
2915 | { | |
aadb5b43 | 2916 | { 0, { 0 }, 0 }, // 0 |
70d4736c OE |
2917 | { 1, { 1 }, LSHR_CLOBBERS_T }, |
2918 | { 1, { 2 }, 0 }, | |
2919 | { 2, { 2, 1 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 2920 | { 2, { 2, 2 }, 0 }, // 4 |
70d4736c OE |
2921 | { 3, { 2, 1, 2 }, LSHR_CLOBBERS_T }, |
2922 | { 3, { 2, 2, 2 }, 0 }, | |
2923 | { 4, { 2, 2, 1, 2 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 2924 | { 1, { 8 }, 0 }, // 8 |
70d4736c OE |
2925 | { 2, { 8, 1 }, LSHR_CLOBBERS_T }, |
2926 | { 2, { 8, 2 }, 0 }, | |
2927 | { 3, { 8, 1, 2 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 2928 | { 3, { 8, 2, 2 }, 0 }, // 12 |
70d4736c OE |
2929 | { 4, { 8, 2, 1, 2 }, LSHR_CLOBBERS_T }, |
2930 | { 3, { 8, -2, 8 }, 0 }, | |
2931 | { 3, { 8, -1, 8 }, ASHL_CLOBBERS_T }, | |
aadb5b43 | 2932 | { 1, { 16 }, 0 }, // 16 |
70d4736c OE |
2933 | { 2, { 16, 1 }, LSHR_CLOBBERS_T }, |
2934 | { 2, { 16, 2 }, 0 }, | |
2935 | { 3, { 16, 1, 2 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 2936 | { 3, { 16, 2, 2 }, 0 }, // 20 |
70d4736c OE |
2937 | { 4, { 16, 2, 1, 2 }, LSHR_CLOBBERS_T }, |
2938 | { 3, { 16, -2, 8 }, 0 }, | |
2939 | { 3, { 16, -1, 8 }, ASHL_CLOBBERS_T }, | |
aadb5b43 | 2940 | { 2, { 16, 8 }, 0 }, // 24 |
70d4736c OE |
2941 | { 3, { 16, 1, 8 }, LSHR_CLOBBERS_T }, |
2942 | { 3, { 16, 8, 2 }, 0 }, | |
2943 | { 4, { 16, 8, 1, 2 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 2944 | { 4, { 16, 8, 2, 2 }, 0 }, // 28 |
70d4736c OE |
2945 | { 4, { 16, -1, -2, 16 }, ASHL_CLOBBERS_T }, |
2946 | { 3, { 16, -2, 16 }, 0 }, | |
6e01d526 OE |
2947 | |
2948 | /* For a right shift by 31 a 2 insn shll-movt sequence can be used. | |
2949 | For a left shift by 31 a 2 insn and-rotl sequences can be used. | |
2950 | However, the shift-and combiner code needs this entry here to be in | |
2951 | terms of real shift insns. */ | |
70d4736c OE |
2952 | { 3, { 16, -1, 16 }, ASHL_CLOBBERS_T } |
2953 | }; | |
8d481241 | 2954 | |
70d4736c OE |
2955 | /* Individual shift amounts for shift amounts < 16, up to three highmost |
2956 | bits might be clobbered. This is typically used when combined with some | |
2957 | kind of sign or zero extension. */ | |
2958 | static const struct ashl_lshr_sequence ext_ashl_lshr_seq[32] = | |
2959 | { | |
aadb5b43 | 2960 | { 0, { 0 }, 0 }, // 0 |
70d4736c OE |
2961 | { 1, { 1 }, LSHR_CLOBBERS_T }, |
2962 | { 1, { 2 }, 0 }, | |
2963 | { 2, { 2, 1 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 2964 | { 2, { 2, 2 }, 0 }, // 4 |
70d4736c OE |
2965 | { 3, { 2, 1, 2 }, LSHR_CLOBBERS_T }, |
2966 | { 2, { 8, -2 }, 0 }, | |
2967 | { 2, { 8, -1 }, ASHL_CLOBBERS_T }, | |
aadb5b43 | 2968 | { 1, { 8 }, 0 }, // 8 |
70d4736c OE |
2969 | { 2, { 8, 1 }, LSHR_CLOBBERS_T }, |
2970 | { 2, { 8, 2 }, 0 }, | |
2971 | { 3, { 8, 1, 2 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 2972 | { 3, { 8, 2, 2 }, 0 }, // 12 |
70d4736c OE |
2973 | { 3, { 16, -2, -1 }, ASHL_CLOBBERS_T }, |
2974 | { 2, { 16, -2 }, 0 }, | |
2975 | { 2, { 16, -1 }, ASHL_CLOBBERS_T }, | |
aadb5b43 | 2976 | { 1, { 16 }, 0 }, // 16 |
70d4736c OE |
2977 | { 2, { 16, 1 }, LSHR_CLOBBERS_T }, |
2978 | { 2, { 16, 2 }, 0 }, | |
2979 | { 3, { 16, 1, 2 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 2980 | { 3, { 16, 2, 2 }, 0 }, // 20 |
70d4736c OE |
2981 | { 4, { 16, 2, 1, 2 }, LSHR_CLOBBERS_T }, |
2982 | { 3, { 16, -2, 8 }, 0 }, | |
2983 | { 3, { 16, -1, 8 }, ASHL_CLOBBERS_T }, | |
aadb5b43 | 2984 | { 2, { 16, 8 }, 0 }, // 24 |
70d4736c OE |
2985 | { 3, { 16, 1, 8 }, LSHR_CLOBBERS_T }, |
2986 | { 3, { 16, 8, 2 }, 0 }, | |
2987 | { 4, { 16, 8, 1, 2 }, LSHR_CLOBBERS_T }, | |
aadb5b43 | 2988 | { 4, { 16, 8, 2, 2 }, 0 }, // 28 |
70d4736c OE |
2989 | { 4, { 16, -1, -2, 16 }, ASHL_CLOBBERS_T }, |
2990 | { 3, { 16, -2, 16 }, 0 }, | |
2991 | { 3, { 16, -1, 16 }, ASHL_CLOBBERS_T } | |
2992 | }; | |
2993 | ||
2994 | /* Return true if a shift left consisting of 1/2/8/16 shift instructions | |
2995 | will clobber the T bit. */ | |
2996 | bool | |
2997 | sh_ashlsi_clobbers_t_reg_p (rtx shift_amount) | |
2998 | { | |
2999 | gcc_assert (CONST_INT_P (shift_amount)); | |
6e01d526 OE |
3000 | |
3001 | const int shift_amount_i = INTVAL (shift_amount) & 31; | |
3002 | ||
3003 | /* Special case for shift count of 31: use and-rotl sequence. */ | |
3004 | if (shift_amount_i == 31) | |
3005 | return true; | |
3006 | ||
3007 | return (ashl_lshr_seq[shift_amount_i].clobbers_t | |
70d4736c OE |
3008 | & ASHL_CLOBBERS_T) != 0; |
3009 | } | |
8d481241 | 3010 | |
50fe8924 OE |
3011 | /* Return true if a logical right shift consisting of 1/2/8/16 shift |
3012 | instructions will clobber the T bit. */ | |
5592815a OE |
3013 | bool |
3014 | sh_lshrsi_clobbers_t_reg_p (rtx shift_amount) | |
3015 | { | |
3016 | gcc_assert (CONST_INT_P (shift_amount)); | |
6e01d526 | 3017 | |
f88d45dc OE |
3018 | /* For right shifts the constant might be negative. */ |
3019 | const int shift_amount_i = std::abs (INTVAL (shift_amount)) & 31; | |
6e01d526 OE |
3020 | |
3021 | /* Special case for shift count of 31: use shll-movt sequence. */ | |
3022 | if (shift_amount_i == 31) | |
3023 | return true; | |
3024 | ||
3025 | return (ashl_lshr_seq[shift_amount_i].clobbers_t | |
5592815a OE |
3026 | & LSHR_CLOBBERS_T) != 0; |
3027 | } | |
3028 | ||
6e01d526 OE |
3029 | /* Return true if it is potentially beneficial to use a dynamic shift |
3030 | instruction (shad / shar) instead of a combination of 1/2/8/16 | |
3031 | shift instructions for the specified shift count. | |
3032 | If dynamic shifts are not available, always return false. */ | |
3033 | bool | |
3034 | sh_dynamicalize_shift_p (rtx count) | |
3035 | { | |
3036 | gcc_assert (CONST_INT_P (count)); | |
3037 | ||
f88d45dc OE |
3038 | /* For right shifts the constant might be negative. */ |
3039 | const int shift_amount_i = std::abs (INTVAL (count)) & 31; | |
6e01d526 OE |
3040 | int insn_count; |
3041 | ||
3042 | /* For left and right shifts, there are shorter 2 insn sequences for | |
3043 | shift amounts of 31. */ | |
3044 | if (shift_amount_i == 31) | |
3045 | insn_count = 2; | |
3046 | else | |
3047 | insn_count = ashl_lshr_seq[shift_amount_i].insn_count; | |
3048 | ||
3049 | return TARGET_DYNSHIFT && (insn_count > 1 + SH_DYNAMIC_SHIFT_COST); | |
3050 | } | |
3051 | ||
ae9d19c0 | 3052 | /* Assuming we have a value that has been sign-extended by at least one bit, |
50fe8924 OE |
3053 | can we use the ext_shift_amounts with the last shift turned to an |
3054 | arithmetic shift to shift it by N without data loss, and quicker than by | |
3055 | other means? */ | |
ae9d19c0 JR |
3056 | #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15) |
3057 | ||
16bea517 | 3058 | /* Return the cost of a shift. */ |
3c50106f | 3059 | static inline int |
cf277499 | 3060 | shiftcosts (rtx x) |
bc45ade3 | 3061 | { |
c762ab6e R |
3062 | if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) |
3063 | { | |
3064 | if (GET_MODE (x) == DImode | |
f3536097 | 3065 | && CONST_INT_P (XEXP (x, 1)) |
c762ab6e | 3066 | && INTVAL (XEXP (x, 1)) == 1) |
ebe0dd38 | 3067 | return 2; |
c762ab6e R |
3068 | |
3069 | /* Everything else is invalid, because there is no pattern for it. */ | |
ebe0dd38 | 3070 | return -1; |
c762ab6e | 3071 | } |
16bea517 | 3072 | /* If shift by a non constant, then this will be expensive. */ |
f3536097 | 3073 | if (!CONST_INT_P (XEXP (x, 1))) |
ebe0dd38 | 3074 | return SH_DYNAMIC_SHIFT_COST; |
bc45ade3 | 3075 | |
6c34a092 PB |
3076 | /* Otherwise, return the true cost in instructions. Cope with out of range |
3077 | shift counts more or less arbitrarily. */ | |
e1fab8ba | 3078 | int value = INTVAL (XEXP (x, 1)) & 31; |
3d422cb1 | 3079 | |
8aa2a305 | 3080 | if (GET_CODE (x) == ASHIFTRT) |
49b6d06b JW |
3081 | { |
3082 | int cost = ashiftrt_insns[value]; | |
ebe0dd38 OE |
3083 | /* If dynamic shifts are available and profitable in this case, then we |
3084 | put the constant in a reg and use shad. */ | |
1245df60 R |
3085 | if (cost > 1 + SH_DYNAMIC_SHIFT_COST) |
3086 | cost = 1 + SH_DYNAMIC_SHIFT_COST; | |
ebe0dd38 | 3087 | return cost; |
49b6d06b | 3088 | } |
8aa2a305 | 3089 | else |
70d4736c | 3090 | return ashl_lshr_seq[value].insn_count; |
0d7e008e | 3091 | } |
b9654711 | 3092 | |
b7cf894f | 3093 | /* Return the cost of an AND/XOR/IOR operation. */ |
3c50106f | 3094 | static inline int |
b7cf894f | 3095 | and_xor_ior_costs (rtx x, int code) |
0d7e008e | 3096 | { |
0f9a3fd3 OE |
3097 | /* On SH1-4 we have only max. SImode operations. |
3098 | Double the cost for modes > SImode. */ | |
e1fab8ba | 3099 | const int cost_scale = GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD ? 2 : 1; |
8aa2a305 | 3100 | |
b7cf894f OE |
3101 | /* A logical operation with two registers is a single cycle |
3102 | instruction. */ | |
f3536097 | 3103 | if (!CONST_INT_P (XEXP (x, 1))) |
0f9a3fd3 | 3104 | return 1 * cost_scale; |
8aa2a305 | 3105 | |
0f9a3fd3 | 3106 | int i = INTVAL (XEXP (x, 1)); |
fa5322fa | 3107 | |
a6f71af5 | 3108 | /* These constants are single cycle extu.[bw] instructions. */ |
b7cf894f | 3109 | if ((i == 0xff || i == 0xffff) && code == AND) |
0f9a3fd3 | 3110 | return 1 * cost_scale; |
b7cf894f OE |
3111 | /* Constants that can be used in an instruction as an immediate are |
3112 | a single cycle, but this requires r0, so make it a little more | |
3113 | expensive. */ | |
735cb76e | 3114 | if (CONST_OK_FOR_K08 (i)) |
0f9a3fd3 | 3115 | return 2 * cost_scale; |
b7cf894f | 3116 | /* Constants that can be loaded with a mov immediate need one more cycle. |
a6f71af5 | 3117 | This case is probably unnecessary. */ |
735cb76e | 3118 | if (CONST_OK_FOR_I08 (i)) |
0f9a3fd3 | 3119 | return 2 * cost_scale; |
b7cf894f | 3120 | /* Any other constant requires an additional 2 cycle pc-relative load. |
a6f71af5 | 3121 | This case is probably unnecessary. */ |
0f9a3fd3 | 3122 | return 3 * cost_scale; |
0d7e008e | 3123 | } |
d3ae8277 | 3124 | |
630c79be | 3125 | /* Return the cost of an addition or a subtraction. */ |
3c50106f | 3126 | static inline int |
cf277499 | 3127 | addsubcosts (rtx x) |
630c79be | 3128 | { |
dd331dd0 OE |
3129 | if (GET_MODE (x) == SImode) |
3130 | { | |
3131 | /* The addc or subc patterns will eventually become one or two | |
3132 | instructions. Below are some costs for some of the patterns | |
3133 | which combine would reject because the costs of the individual | |
3134 | insns in the patterns are lower. | |
3135 | ||
3136 | FIXME: It would be much easier if we had something like insn cost | |
3137 | attributes and the cost calculation machinery used those attributes | |
3138 | in the first place. This would eliminate redundant recog-like C | |
3139 | code to calculate costs of complex patterns. */ | |
3140 | rtx op0 = XEXP (x, 0); | |
3141 | rtx op1 = XEXP (x, 1); | |
3142 | ||
3143 | if (GET_CODE (x) == PLUS) | |
3144 | { | |
3145 | if (GET_CODE (op0) == AND | |
3146 | && XEXP (op0, 1) == const1_rtx | |
3147 | && (GET_CODE (op1) == PLUS | |
3148 | || (GET_CODE (op1) == MULT && XEXP (op1, 1) == const2_rtx))) | |
3149 | return 1; | |
3150 | ||
3151 | if (GET_CODE (op0) == MULT && XEXP (op0, 1) == const2_rtx | |
3152 | && GET_CODE (op1) == LSHIFTRT | |
3153 | && CONST_INT_P (XEXP (op1, 1)) && INTVAL (XEXP (op1, 1)) == 31) | |
3154 | return 1; | |
3155 | } | |
841dbf80 OE |
3156 | /* Let's assume that adding the result of an insns that stores into |
3157 | the T bit is cheap. */ | |
3158 | if (treg_set_expr (op1, SImode)) | |
3159 | return 1; | |
3160 | if (treg_set_expr (op0, SImode)) | |
3161 | return 1; | |
dd331dd0 OE |
3162 | } |
3163 | ||
0f9a3fd3 OE |
3164 | /* On SH1-4 we have only max. SImode operations. |
3165 | Double the cost for modes > SImode. */ | |
e1fab8ba | 3166 | const int cost_scale = GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD ? 2 : 1; |
0f9a3fd3 | 3167 | |
630c79be | 3168 | /* Adding a register is a single cycle insn. */ |
f3536097 | 3169 | if (REG_P (XEXP (x, 1)) |
50ceefc2 | 3170 | || GET_CODE (XEXP (x, 1)) == SUBREG) |
0f9a3fd3 | 3171 | return 1 * cost_scale; |
630c79be BS |
3172 | |
3173 | /* Likewise for small constants. */ | |
f3536097 | 3174 | if (CONST_INT_P (XEXP (x, 1)) |
fa5322fa | 3175 | && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1)))) |
0f9a3fd3 | 3176 | return 1 * cost_scale; |
630c79be BS |
3177 | |
3178 | /* Any other constant requires a 2 cycle pc-relative load plus an | |
3179 | addition. */ | |
0f9a3fd3 | 3180 | return 3 * cost_scale; |
630c79be BS |
3181 | } |
3182 | ||
16bea517 | 3183 | /* Return the cost of a multiply. */ |
3c50106f | 3184 | static inline int |
cf277499 | 3185 | multcosts (rtx x ATTRIBUTE_UNUSED) |
0d7e008e | 3186 | { |
7dd2f19b RS |
3187 | if (sh_multcost >= 0) |
3188 | return sh_multcost; | |
fa5322fa | 3189 | |
0d7e008e | 3190 | if (TARGET_SH2) |
d3ae8277 SC |
3191 | { |
3192 | /* We have a mul insn, so we can never take more than the mul and the | |
a7771f78 | 3193 | read of the mac reg, but count more because of the latency and extra |
16bea517 | 3194 | reg usage. */ |
3020190e | 3195 | if (optimize_size) |
8e87e161 | 3196 | return 2; |
a7771f78 | 3197 | return 3; |
d3ae8277 SC |
3198 | } |
3199 | ||
a7771f78 | 3200 | /* If we're aiming at small code, then just count the number of |
16bea517 | 3201 | insns in a multiply call sequence. */ |
3020190e | 3202 | if (optimize_size) |
8aa2a305 | 3203 | return 5; |
d3ae8277 | 3204 | |
16bea517 | 3205 | /* Otherwise count all the insns in the routine we'd be calling too. */ |
d3ae8277 | 3206 | return 20; |
0d7e008e | 3207 | } |
b9654711 | 3208 | |
3c50106f RH |
3209 | /* Compute a (partial) cost for rtx X. Return true if the complete |
3210 | cost has been computed, and false if subexpressions should be | |
3211 | scanned. In either case, *TOTAL contains the cost result. */ | |
3c50106f | 3212 | static bool |
e548c9df AM |
3213 | sh_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code, |
3214 | int opno ATTRIBUTE_UNUSED, | |
68f932c4 | 3215 | int *total, bool speed ATTRIBUTE_UNUSED) |
3c50106f | 3216 | { |
e548c9df AM |
3217 | int code = GET_CODE (x); |
3218 | ||
3c50106f RH |
3219 | switch (code) |
3220 | { | |
0345d1dd OE |
3221 | /* The lower-subreg pass decides whether to split multi-word regs |
3222 | into individual regs by looking at the cost for a SET of certain | |
3223 | modes with the following patterns: | |
3224 | (set (reg) (reg)) | |
3225 | (set (reg) (const_int 0)) | |
3226 | On machines that support vector-move operations a multi-word move | |
3227 | is the same cost as individual reg move. On SH there is no | |
3228 | vector-move, so we have to provide the correct cost in the number | |
3229 | of move insns to load/store the reg of the mode in question. */ | |
3230 | case SET: | |
4e7e89e8 OE |
3231 | if (sh_movt_set_dest (x) != NULL || sh_movrt_set_dest (x) != NULL) |
3232 | { | |
3233 | *total = COSTS_N_INSNS (1); | |
3234 | return true; | |
3235 | } | |
3236 | ||
0345d1dd OE |
3237 | if (register_operand (SET_DEST (x), VOIDmode) |
3238 | && (register_operand (SET_SRC (x), VOIDmode) | |
3239 | || satisfies_constraint_Z (SET_SRC (x)))) | |
3240 | { | |
ef4bddc2 | 3241 | const machine_mode mode = GET_MODE (SET_DEST (x)); |
0345d1dd OE |
3242 | *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) |
3243 | / mov_insn_size (mode, TARGET_SH2A)); | |
3244 | return true; | |
3245 | } | |
3246 | return false; | |
3247 | ||
8385420c OE |
3248 | /* The cost of a mem access is mainly the cost of the address mode. */ |
3249 | case MEM: | |
3250 | *total = sh_address_cost (XEXP (x, 0), GET_MODE (x), MEM_ADDR_SPACE (x), | |
3251 | true); | |
3252 | return true; | |
3253 | ||
841dbf80 OE |
3254 | case IF_THEN_ELSE: |
3255 | /* This case is required for the if_then_else negc pattern. */ | |
3256 | if (treg_set_expr (XEXP (x, 0), SImode)) | |
3257 | { | |
3258 | *total = COSTS_N_INSNS (1); | |
3259 | return true; | |
3260 | } | |
3261 | else | |
3262 | return false; | |
3263 | ||
3264 | /* Zero extracts of single bits are usually combine patterns for the | |
3265 | tst insns. */ | |
3266 | case ZERO_EXTRACT: | |
3267 | if (GET_CODE (XEXP (x, 0)) == XOR | |
3268 | && arith_reg_operand (XEXP (XEXP (x, 0), 0), VOIDmode) | |
3269 | && XEXP (x, 1) == const1_rtx | |
3270 | && CONST_INT_P (XEXP (x, 2)) | |
3271 | && CONST_INT_P (XEXP (XEXP (x, 0), 1)) | |
3272 | /* Check that the xor constaint overlaps with the extracted bit. */ | |
3273 | && (INTVAL (XEXP (XEXP (x, 0), 1)) & (1LL << INTVAL (XEXP (x, 2))))) | |
3274 | { | |
3275 | *total = 1; //COSTS_N_INSNS (1); | |
3276 | return true; | |
3277 | } | |
765d7b54 OE |
3278 | |
3279 | /* div0s variant. */ | |
3280 | if (GET_CODE (XEXP (x, 0)) == XOR | |
3281 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR | |
3282 | && CONST_INT_P (XEXP (XEXP (x, 0), 1))) | |
3283 | { | |
3284 | *total = 1; | |
3285 | return true; | |
3286 | } | |
841dbf80 OE |
3287 | return false; |
3288 | ||
8385420c | 3289 | /* The cost of a sign or zero extend depends on whether the source is a |
5764ee3c | 3290 | reg or a mem. In case of a mem take the address into account. */ |
8385420c | 3291 | case SIGN_EXTEND: |
841dbf80 | 3292 | if (arith_reg_operand (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) |
8385420c OE |
3293 | { |
3294 | *total = COSTS_N_INSNS (1); | |
3295 | return true; | |
3296 | } | |
3297 | if (MEM_P (XEXP (x, 0))) | |
3298 | { | |
3299 | *total = sh_address_cost (XEXP (XEXP (x, 0), 0), | |
3300 | GET_MODE (XEXP (x, 0)), | |
3301 | MEM_ADDR_SPACE (XEXP (x, 0)), true); | |
3302 | return true; | |
3303 | } | |
3304 | return false; | |
3305 | ||
3306 | case ZERO_EXTEND: | |
841dbf80 | 3307 | if (arith_reg_operand (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) |
8385420c OE |
3308 | { |
3309 | *total = COSTS_N_INSNS (1); | |
3310 | return true; | |
3311 | } | |
3312 | else if (TARGET_SH2A && MEM_P (XEXP (x, 0)) | |
3313 | && (GET_MODE (XEXP (x, 0)) == QImode | |
3314 | || GET_MODE (XEXP (x, 0)) == HImode)) | |
3315 | { | |
3316 | /* Handle SH2A's movu.b and movu.w insn. */ | |
3317 | *total = sh_address_cost (XEXP (XEXP (x, 0), 0), | |
3318 | GET_MODE (XEXP (x, 0)), | |
3319 | MEM_ADDR_SPACE (XEXP (x, 0)), true); | |
3320 | return true; | |
3321 | } | |
3322 | return false; | |
3323 | ||
3324 | /* mems for SFmode and DFmode can be inside a parallel due to | |
3325 | the way the fpscr is handled. */ | |
3326 | case PARALLEL: | |
3327 | for (int i = 0; i < XVECLEN (x, 0); i++) | |
3328 | { | |
3329 | rtx xx = XVECEXP (x, 0, i); | |
3330 | if (GET_CODE (xx) == SET && MEM_P (XEXP (xx, 0))) | |
3331 | { | |
3332 | *total = sh_address_cost (XEXP (XEXP (xx, 0), 0), | |
3333 | GET_MODE (XEXP (xx, 0)), | |
3334 | MEM_ADDR_SPACE (XEXP (xx, 0)), true); | |
3335 | return true; | |
3336 | } | |
3337 | if (GET_CODE (xx) == SET && MEM_P (XEXP (xx, 1))) | |
3338 | { | |
3339 | *total = sh_address_cost (XEXP (XEXP (xx, 1), 0), | |
3340 | GET_MODE (XEXP (xx, 1)), | |
3341 | MEM_ADDR_SPACE (XEXP (xx, 1)), true); | |
3342 | return true; | |
3343 | } | |
3344 | } | |
3345 | ||
3346 | if (sh_1el_vec (x, VOIDmode)) | |
3347 | *total = outer_code != SET; | |
3348 | else if (sh_rep_vec (x, VOIDmode)) | |
3349 | *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4 | |
3350 | + (outer_code != SET)); | |
3351 | else | |
3352 | *total = COSTS_N_INSNS (3) + (outer_code != SET); | |
3353 | return true; | |
3354 | ||
3c50106f | 3355 | case CONST_INT: |
735cb76e | 3356 | if (CONST_OK_FOR_I08 (INTVAL (x))) |
3c50106f RH |
3357 | *total = 0; |
3358 | else if ((outer_code == AND || outer_code == IOR || outer_code == XOR) | |
735cb76e | 3359 | && CONST_OK_FOR_K08 (INTVAL (x))) |
3c50106f | 3360 | *total = 1; |
78d310c2 | 3361 | /* prepare_cmp_insn will force costly constants int registers before |
35912544 | 3362 | the cbranch[sd]i4 patterns can see them, so preserve potentially |
78d310c2 R |
3363 | interesting ones not covered by I08 above. */ |
3364 | else if (outer_code == COMPARE | |
3365 | && ((unsigned HOST_WIDE_INT) INTVAL (x) | |
3366 | == (unsigned HOST_WIDE_INT) 0x7fffffff + 1 | |
3367 | || INTVAL (x) == 0x7fffffff | |
3368 | || INTVAL (x) == 0x80 || INTVAL (x) == -0x81)) | |
3369 | *total = 1; | |
3c50106f RH |
3370 | else |
3371 | *total = 8; | |
3372 | return true; | |
3373 | ||
6ff9d294 OE |
3374 | case EQ: |
3375 | /* An and with a constant compared against zero is | |
6fb917d9 | 3376 | most likely going to be a TST #imm, R0 instruction. */ |
841dbf80 | 3377 | if (XEXP (x, 1) == const0_rtx |
6fb917d9 OE |
3378 | && ((GET_CODE (XEXP (x, 0)) == AND |
3379 | || (SUBREG_P (XEXP (x, 0)) | |
3380 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == AND)) | |
3381 | || GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT)) | |
841dbf80 OE |
3382 | { |
3383 | *total = 1; | |
3384 | return true; | |
3385 | } | |
3386 | ||
3387 | else if (XEXP (x, 1) == const0_rtx | |
3388 | && GET_CODE (XEXP (x, 0)) == AND | |
3389 | && CONST_INT_P (XEXP (XEXP (x, 0), 1)) | |
3390 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT | |
3391 | && arith_reg_operand (XEXP (XEXP (XEXP (x, 0), 0), 0), SImode) | |
3392 | && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))) | |
6ff9d294 OE |
3393 | { |
3394 | *total = 1; | |
3395 | return true; | |
2353515d OE |
3396 | } |
3397 | else | |
3398 | return false; | |
3399 | ||
3400 | case SMIN: | |
3401 | case SMAX: | |
3402 | /* This is most likely a clips.b or clips.w insn that is being made up | |
3403 | by combine. */ | |
3404 | if (TARGET_SH2A | |
3405 | && (GET_CODE (XEXP (x, 0)) == SMAX || GET_CODE (XEXP (x, 0)) == SMIN) | |
3406 | && CONST_INT_P (XEXP (XEXP (x, 0), 1)) | |
3407 | && REG_P (XEXP (XEXP (x, 0), 0)) | |
3408 | && CONST_INT_P (XEXP (x, 1))) | |
3409 | { | |
3410 | *total = COSTS_N_INSNS (1); | |
3411 | return true; | |
6ff9d294 OE |
3412 | } |
3413 | else | |
3414 | return false; | |
3415 | ||
3c50106f RH |
3416 | case CONST: |
3417 | case LABEL_REF: | |
3418 | case SYMBOL_REF: | |
e1fab8ba | 3419 | *total = 5; |
3c50106f RH |
3420 | return true; |
3421 | ||
3422 | case CONST_DOUBLE: | |
78d310c2 | 3423 | /* prepare_cmp_insn will force costly constants int registers before |
35912544 | 3424 | the cbranchdi4 pattern can see them, so preserve potentially |
78d310c2 | 3425 | interesting ones. */ |
e1fab8ba | 3426 | if (outer_code == COMPARE && GET_MODE (x) == DImode) |
50fe8924 | 3427 | *total = 1; |
3c50106f | 3428 | else |
50fe8924 | 3429 | *total = 10; |
3c50106f | 3430 | return true; |
8385420c | 3431 | |
73a4d10b | 3432 | case CONST_VECTOR: |
8385420c OE |
3433 | /* FIXME: This looks broken. Only the last statement has any effect. |
3434 | Probably this could be folded with the PARALLEL case? */ | |
73a4d10b R |
3435 | if (x == CONST0_RTX (GET_MODE (x))) |
3436 | *total = 0; | |
3437 | else if (sh_1el_vec (x, VOIDmode)) | |
3438 | *total = outer_code != SET; | |
3439 | if (sh_rep_vec (x, VOIDmode)) | |
3440 | *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4 | |
3441 | + (outer_code != SET)); | |
3442 | *total = COSTS_N_INSNS (3) + (outer_code != SET); | |
3443 | return true; | |
3c50106f RH |
3444 | |
3445 | case PLUS: | |
73a4d10b | 3446 | case MINUS: |
3c50106f RH |
3447 | *total = COSTS_N_INSNS (addsubcosts (x)); |
3448 | return true; | |
3449 | ||
3450 | case AND: | |
841dbf80 OE |
3451 | /* Check for (and (not (reg)) (const_int 1)) which is a tst insn. */ |
3452 | if (GET_CODE (XEXP (x, 0)) == NOT && XEXP (x, 1) == const1_rtx) | |
3453 | { | |
3454 | *total = COSTS_N_INSNS (1); | |
3455 | return true; | |
3456 | } | |
3457 | /* Fall through. */ | |
3458 | ||
b7cf894f OE |
3459 | case XOR: |
3460 | case IOR: | |
3461 | *total = COSTS_N_INSNS (and_xor_ior_costs (x, code)); | |
3c50106f RH |
3462 | return true; |
3463 | ||
3464 | case MULT: | |
3465 | *total = COSTS_N_INSNS (multcosts (x)); | |
3466 | return true; | |
3467 | ||
669d4d70 OE |
3468 | case LT: |
3469 | case GE: | |
3470 | /* div0s sign comparison. */ | |
3471 | if (GET_CODE (XEXP (x, 0)) == XOR | |
3472 | && REG_P ((XEXP (XEXP (x, 0), 0))) | |
3473 | && REG_P ((XEXP (XEXP (x, 0), 1))) | |
3474 | && satisfies_constraint_Z (XEXP (x, 1))) | |
3475 | { | |
3476 | *total = COSTS_N_INSNS (1); | |
3477 | return true; | |
3478 | } | |
3479 | else | |
3480 | return false; | |
3481 | ||
3482 | case LSHIFTRT: | |
3483 | /* div0s sign comparison. */ | |
3484 | if (GET_CODE (XEXP (x, 0)) == XOR | |
3485 | && REG_P ((XEXP (XEXP (x, 0), 0))) | |
3486 | && REG_P ((XEXP (XEXP (x, 0), 1))) | |
3487 | && CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 31) | |
3488 | { | |
3489 | *total = COSTS_N_INSNS (1); | |
3490 | return true; | |
3491 | } | |
133634de | 3492 | /* FALLTHRU */ |
3c50106f RH |
3493 | case ASHIFT: |
3494 | case ASHIFTRT: | |
ebe0dd38 OE |
3495 | { |
3496 | int cost = shiftcosts (x); | |
3497 | if (cost < 0) | |
3498 | return false; | |
3499 | *total = COSTS_N_INSNS (cost); | |
3500 | return true; | |
3501 | } | |
3c50106f RH |
3502 | |
3503 | case DIV: | |
3504 | case UDIV: | |
3505 | case MOD: | |
3506 | case UMOD: | |
3507 | *total = COSTS_N_INSNS (20); | |
3508 | return true; | |
3509 | ||
3510 | case FLOAT: | |
3511 | case FIX: | |
3512 | *total = 100; | |
3513 | return true; | |
3514 | ||
3515 | default: | |
3516 | return false; | |
3517 | } | |
3518 | } | |
3519 | ||
9b9ad23f OE |
3520 | /* Determine the size of the fundamental move insn that will be used |
3521 | for the specified mode. */ | |
9b9ad23f | 3522 | static inline int |
ef4bddc2 | 3523 | mov_insn_size (machine_mode mode, bool consider_sh2a) |
9b9ad23f OE |
3524 | { |
3525 | const int mode_sz = GET_MODE_SIZE (mode); | |
3526 | ||
3527 | if ((consider_sh2a && TARGET_SH2A_DOUBLE && mode == DFmode) | |
3528 | || (TARGET_FMOVD && mode == DFmode)) | |
3529 | return mode_sz; | |
3530 | else | |
3531 | { | |
3532 | /* The max. available mode for actual move insns is SImode. | |
3533 | Larger accesses will be split into multiple loads/stores. */ | |
3534 | const int max_mov_sz = GET_MODE_SIZE (SImode); | |
3535 | return mode_sz >= max_mov_sz ? max_mov_sz : mode_sz; | |
3536 | } | |
3537 | } | |
3538 | ||
3539 | /* Determine the maximum possible displacement for a move insn for the | |
3540 | specified mode. */ | |
91f65b12 OE |
3541 | int |
3542 | sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a) | |
dcefdf67 | 3543 | { |
9b9ad23f OE |
3544 | /* The 4 byte displacement move insns are the same as the 2 byte |
3545 | versions but take a 12 bit displacement. All we need to do is to | |
3546 | scale the max. displacement value accordingly. */ | |
3547 | const int disp_scale = consider_sh2a ? (4095 / 15) : 1; | |
3548 | ||
9b9ad23f OE |
3549 | /* SH2A supports FPU move insns with 12 bit displacements. |
3550 | Other variants to do not support any kind of displacements for | |
3551 | FPU move insns. */ | |
3552 | if (! consider_sh2a && TARGET_FPU_ANY && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3553 | return 0; | |
3554 | else | |
3555 | { | |
3556 | const int mov_insn_sz = mov_insn_size (mode, consider_sh2a); | |
3557 | const int mode_sz = GET_MODE_SIZE (mode); | |
3558 | int r = 15 * mov_insn_sz * disp_scale; | |
3559 | ||
3560 | /* If the mov insn will be split into multiple loads/stores, the | |
3561 | maximum possible displacement is a bit smaller. */ | |
3562 | if (mode_sz > mov_insn_sz) | |
3563 | r -= mode_sz - mov_insn_sz; | |
3564 | return r; | |
3565 | } | |
3566 | } | |
344332e8 | 3567 | |
9b9ad23f OE |
3568 | /* Determine the alignment mask for a move insn of the |
3569 | specified mode. */ | |
9b9ad23f | 3570 | static inline int |
ef4bddc2 | 3571 | mov_insn_alignment_mask (machine_mode mode, bool consider_sh2a) |
9b9ad23f OE |
3572 | { |
3573 | const int mov_insn_sz = mov_insn_size (mode, consider_sh2a); | |
3574 | return mov_insn_sz > 0 ? (mov_insn_sz - 1) : 0; | |
3575 | } | |
3576 | ||
8c2a3f3b | 3577 | /* Return the displacement value of a displacement address. */ |
91f65b12 OE |
3578 | HOST_WIDE_INT |
3579 | sh_disp_addr_displacement (rtx x) | |
8c2a3f3b OE |
3580 | { |
3581 | gcc_assert (satisfies_constraint_Sdd (x)); | |
3582 | return INTVAL (XEXP (XEXP (x, 0), 1)); | |
3583 | } | |
3584 | ||
9b9ad23f | 3585 | /* Compute the cost of an address. */ |
9b9ad23f | 3586 | static int |
ef4bddc2 | 3587 | sh_address_cost (rtx x, machine_mode mode, |
b413068c | 3588 | addr_space_t as ATTRIBUTE_UNUSED, bool speed ATTRIBUTE_UNUSED) |
9b9ad23f | 3589 | { |
fce1e5fb OE |
3590 | /* 'GBR + 0'. Account one more because of R0 restriction. */ |
3591 | if (REG_P (x) && REGNO (x) == GBR_REG) | |
3592 | return 2; | |
3593 | ||
8385420c OE |
3594 | /* Simple reg, post-inc, pre-dec addressing. */ |
3595 | if (REG_P (x) || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC) | |
3596 | return 1; | |
3597 | ||
9b9ad23f | 3598 | /* 'reg + disp' addressing. */ |
8385420c OE |
3599 | if (GET_CODE (x) == PLUS |
3600 | && REG_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1))) | |
9b9ad23f | 3601 | { |
fce1e5fb OE |
3602 | /* 'GBR + disp'. Account one more because of R0 restriction. */ |
3603 | if (REGNO (XEXP (x, 0)) == GBR_REG | |
3604 | && gbr_displacement (XEXP (x, 1), mode)) | |
3605 | return 2; | |
3606 | ||
8385420c | 3607 | const HOST_WIDE_INT offset = INTVAL (XEXP (x, 1)); |
9b9ad23f | 3608 | |
8385420c OE |
3609 | if (offset == 0) |
3610 | return 1; | |
3611 | ||
3612 | /* The displacement would fit into a 2 byte move insn. | |
3613 | HImode and QImode loads/stores with displacement put pressure on | |
3614 | R0 which will most likely require another reg copy. Thus account | |
3615 | a higher cost for that. */ | |
91f65b12 | 3616 | if (offset > 0 && offset <= sh_max_mov_insn_displacement (mode, false)) |
8385420c | 3617 | return (mode == HImode || mode == QImode) ? 2 : 1; |
9b9ad23f OE |
3618 | |
3619 | /* The displacement would fit into a 4 byte move insn (SH2A). */ | |
3620 | if (TARGET_SH2A | |
91f65b12 | 3621 | && offset > 0 && offset <= sh_max_mov_insn_displacement (mode, true)) |
8385420c | 3622 | return 2; |
9b9ad23f OE |
3623 | |
3624 | /* The displacement is probably out of range and will require extra | |
3625 | calculations. */ | |
8385420c | 3626 | return 3; |
9b9ad23f OE |
3627 | } |
3628 | ||
3629 | /* 'reg + reg' addressing. Account a slightly higher cost because of | |
3630 | increased pressure on R0. */ | |
e1fab8ba | 3631 | if (GET_CODE (x) == PLUS && ! CONSTANT_P (XEXP (x, 1))) |
8385420c | 3632 | return 3; |
9b9ad23f | 3633 | |
8385420c OE |
3634 | /* Not sure what it is - probably expensive. */ |
3635 | return 10; | |
dcefdf67 | 3636 | } |
3c50106f | 3637 | |
16bea517 | 3638 | /* Code to expand a shift. */ |
d8a48c21 | 3639 | static void |
cf277499 | 3640 | gen_ashift (int type, int n, rtx reg) |
0d7e008e | 3641 | { |
d8a48c21 OE |
3642 | rtx n_rtx; |
3643 | ||
16bea517 JW |
3644 | /* Negative values here come from the shift_amounts array. */ |
3645 | if (n < 0) | |
3646 | { | |
3647 | if (type == ASHIFT) | |
3648 | type = LSHIFTRT; | |
3649 | else | |
3650 | type = ASHIFT; | |
3651 | n = -n; | |
3652 | } | |
3653 | ||
d8a48c21 OE |
3654 | n_rtx = GEN_INT (n); |
3655 | gcc_assert (satisfies_constraint_P27 (n_rtx)); | |
3656 | ||
0d7e008e | 3657 | switch (type) |
bc45ade3 | 3658 | { |
0d7e008e | 3659 | case ASHIFTRT: |
d8a48c21 | 3660 | emit_insn (gen_ashrsi3_k (reg, reg, n_rtx)); |
0d7e008e SC |
3661 | break; |
3662 | case LSHIFTRT: | |
16bea517 | 3663 | if (n == 1) |
50fe8924 | 3664 | emit_insn (gen_shlr (reg, reg)); |
16bea517 | 3665 | else |
d8a48c21 | 3666 | emit_insn (gen_lshrsi3_k (reg, reg, n_rtx)); |
0d7e008e SC |
3667 | break; |
3668 | case ASHIFT: | |
d8a48c21 | 3669 | emit_insn (gen_ashlsi3_k (reg, reg, n_rtx)); |
0d7e008e | 3670 | break; |
d8a48c21 OE |
3671 | default: |
3672 | gcc_unreachable (); | |
bc45ade3 | 3673 | } |
bc45ade3 | 3674 | } |
bc45ade3 | 3675 | |
50fe8924 | 3676 | /* Code to expand a HImode shift. */ |
d8a48c21 | 3677 | static void |
cf277499 | 3678 | gen_ashift_hi (int type, int n, rtx reg) |
8d481241 JW |
3679 | { |
3680 | /* Negative values here come from the shift_amounts array. */ | |
3681 | if (n < 0) | |
3682 | { | |
3683 | if (type == ASHIFT) | |
3684 | type = LSHIFTRT; | |
3685 | else | |
3686 | type = ASHIFT; | |
3687 | n = -n; | |
3688 | } | |
3689 | ||
3690 | switch (type) | |
3691 | { | |
3692 | case ASHIFTRT: | |
8d481241 | 3693 | case LSHIFTRT: |
d0c42859 R |
3694 | /* We don't have HImode right shift operations because using the |
3695 | ordinary 32 bit shift instructions for that doesn't generate proper | |
3696 | zero/sign extension. | |
3697 | gen_ashift_hi is only called in contexts where we know that the | |
3698 | sign extension works out correctly. */ | |
97d6fd65 | 3699 | { |
ddef6bc7 | 3700 | int offset = 0; |
97d6fd65 R |
3701 | if (GET_CODE (reg) == SUBREG) |
3702 | { | |
ddef6bc7 | 3703 | offset = SUBREG_BYTE (reg); |
97d6fd65 R |
3704 | reg = SUBREG_REG (reg); |
3705 | } | |
ddef6bc7 | 3706 | gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset)); |
97d6fd65 R |
3707 | break; |
3708 | } | |
8d481241 JW |
3709 | case ASHIFT: |
3710 | emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n))); | |
3711 | break; | |
3712 | } | |
3713 | } | |
3714 | ||
8aa2a305 JW |
3715 | /* Output RTL to split a constant shift into its component SH constant |
3716 | shift instructions. */ | |
318881c0 | 3717 | void |
cf277499 | 3718 | gen_shifty_op (int code, rtx *operands) |
bc45ade3 | 3719 | { |
16bea517 | 3720 | int value = INTVAL (operands[2]); |
8aa2a305 | 3721 | int max, i; |
00f8ff66 | 3722 | |
cff3d762 | 3723 | /* Truncate the shift count in case it is out of bounds. */ |
6c34a092 | 3724 | value = value & 31; |
f676971a | 3725 | |
8aa2a305 | 3726 | if (value == 31) |
16bea517 | 3727 | { |
8aa2a305 | 3728 | if (code == LSHIFTRT) |
0d7e008e | 3729 | { |
8aa2a305 | 3730 | emit_insn (gen_rotlsi3_1 (operands[0], operands[0])); |
f031c344 | 3731 | emit_insn (gen_movt (operands[0], get_t_reg_rtx ())); |
8aa2a305 | 3732 | return; |
16bea517 | 3733 | } |
8aa2a305 | 3734 | else if (code == ASHIFT) |
16bea517 | 3735 | { |
8aa2a305 JW |
3736 | /* There is a two instruction sequence for 31 bit left shifts, |
3737 | but it requires r0. */ | |
f3536097 | 3738 | if (REG_P (operands[0]) && REGNO (operands[0]) == 0) |
0d7e008e | 3739 | { |
8aa2a305 JW |
3740 | emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx)); |
3741 | emit_insn (gen_rotlsi3_31 (operands[0], operands[0])); | |
3742 | return; | |
0d7e008e | 3743 | } |
16bea517 | 3744 | } |
8aa2a305 | 3745 | } |
c17f53a8 JW |
3746 | else if (value == 0) |
3747 | { | |
73a4d10b R |
3748 | /* This can happen even when optimizing, if there were subregs before |
3749 | reload. Don't output a nop here, as this is never optimized away; | |
3750 | use a no-op move instead. */ | |
f7df4a84 | 3751 | emit_insn (gen_rtx_SET (operands[0], operands[0])); |
c17f53a8 JW |
3752 | return; |
3753 | } | |
a9f71ad8 | 3754 | |
70d4736c | 3755 | max = ashl_lshr_seq[value].insn_count; |
8aa2a305 | 3756 | for (i = 0; i < max; i++) |
70d4736c | 3757 | gen_ashift (code, ashl_lshr_seq[value].amount[i], operands[0]); |
8aa2a305 | 3758 | } |
f676971a | 3759 | |
50fe8924 OE |
3760 | /* Same as gen_shifty_op, but optimized for values where the topmost bits |
3761 | don't matter. */ | |
318881c0 | 3762 | void |
cf277499 | 3763 | gen_shifty_hi_op (int code, rtx *operands) |
8d481241 JW |
3764 | { |
3765 | int value = INTVAL (operands[2]); | |
3766 | int max, i; | |
cf277499 | 3767 | void (*gen_fun) (int, int, rtx); |
8d481241 JW |
3768 | |
3769 | /* This operation is used by and_shl for SImode values with a few | |
3770 | high bits known to be cleared. */ | |
3771 | value &= 31; | |
3772 | if (value == 0) | |
3773 | { | |
3774 | emit_insn (gen_nop ()); | |
3775 | return; | |
3776 | } | |
3777 | ||
3778 | gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift; | |
3779 | if (code == ASHIFT) | |
3780 | { | |
70d4736c | 3781 | max = ext_ashl_lshr_seq[value].insn_count; |
8d481241 | 3782 | for (i = 0; i < max; i++) |
70d4736c | 3783 | gen_fun (code, ext_ashl_lshr_seq[value].amount[i], operands[0]); |
8d481241 JW |
3784 | } |
3785 | else | |
3786 | /* When shifting right, emit the shifts in reverse order, so that | |
3787 | solitary negative values come first. */ | |
70d4736c OE |
3788 | for (i = ext_ashl_lshr_seq[value].insn_count - 1; i >= 0; i--) |
3789 | gen_fun (code, ext_ashl_lshr_seq[value].amount[i], operands[0]); | |
8d481241 | 3790 | } |
8aa2a305 | 3791 | |
50fe8924 OE |
3792 | /* Output RTL for an arithmetic right shift. |
3793 | ??? Rewrite to use super-optimizer sequences. */ | |
aaf701c5 | 3794 | bool |
cf277499 | 3795 | expand_ashiftrt (rtx *operands) |
8aa2a305 JW |
3796 | { |
3797 | rtx wrk; | |
3798 | char func[18]; | |
8aa2a305 JW |
3799 | int value; |
3800 | ||
a594120b | 3801 | if (TARGET_DYNSHIFT) |
20b04867 | 3802 | { |
f3536097 | 3803 | if (!CONST_INT_P (operands[2])) |
49b6d06b JW |
3804 | { |
3805 | rtx count = copy_to_mode_reg (SImode, operands[2]); | |
3806 | emit_insn (gen_negsi2 (count, count)); | |
3807 | emit_insn (gen_ashrsi3_d (operands[0], operands[1], count)); | |
aaf701c5 | 3808 | return true; |
49b6d06b | 3809 | } |
1245df60 R |
3810 | else if (ashiftrt_insns[INTVAL (operands[2]) & 31] |
3811 | > 1 + SH_DYNAMIC_SHIFT_COST) | |
49b6d06b | 3812 | { |
1245df60 R |
3813 | rtx count |
3814 | = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31))); | |
49b6d06b | 3815 | emit_insn (gen_ashrsi3_d (operands[0], operands[1], count)); |
aaf701c5 | 3816 | return true; |
49b6d06b | 3817 | } |
20b04867 | 3818 | } |
f3536097 | 3819 | if (!CONST_INT_P (operands[2])) |
aaf701c5 | 3820 | return false; |
8aa2a305 | 3821 | |
1245df60 | 3822 | value = INTVAL (operands[2]) & 31; |
8aa2a305 JW |
3823 | |
3824 | if (value == 31) | |
3825 | { | |
73a4d10b R |
3826 | /* If we are called from abs expansion, arrange things so that we |
3827 | we can use a single MT instruction that doesn't clobber the source, | |
3828 | if LICM can hoist out the load of the constant zero. */ | |
3829 | if (currently_expanding_to_rtl) | |
3830 | { | |
3831 | emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)), | |
3832 | operands[1])); | |
be8cbce1 | 3833 | emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ())); |
aaf701c5 | 3834 | return true; |
73a4d10b | 3835 | } |
8aa2a305 | 3836 | emit_insn (gen_ashrsi2_31 (operands[0], operands[1])); |
aaf701c5 | 3837 | return true; |
8aa2a305 JW |
3838 | } |
3839 | else if (value >= 16 && value <= 19) | |
3840 | { | |
3841 | wrk = gen_reg_rtx (SImode); | |
3842 | emit_insn (gen_ashrsi2_16 (wrk, operands[1])); | |
3843 | value -= 16; | |
3844 | while (value--) | |
3845 | gen_ashift (ASHIFTRT, 1, wrk); | |
3846 | emit_move_insn (operands[0], wrk); | |
aaf701c5 | 3847 | return true; |
a9f71ad8 | 3848 | } |
8aa2a305 JW |
3849 | /* Expand a short sequence inline, longer call a magic routine. */ |
3850 | else if (value <= 5) | |
3851 | { | |
3852 | wrk = gen_reg_rtx (SImode); | |
3853 | emit_move_insn (wrk, operands[1]); | |
3854 | while (value--) | |
3855 | gen_ashift (ASHIFTRT, 1, wrk); | |
3856 | emit_move_insn (operands[0], wrk); | |
aaf701c5 | 3857 | return true; |
8aa2a305 JW |
3858 | } |
3859 | ||
3860 | wrk = gen_reg_rtx (Pmode); | |
3861 | ||
3862 | /* Load the value into an arg reg and call a helper. */ | |
c5c76735 | 3863 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]); |
8aa2a305 | 3864 | sprintf (func, "__ashiftrt_r4_%d", value); |
1e44e857 DJ |
3865 | rtx lab = function_symbol (wrk, func, SFUNC_STATIC).lab; |
3866 | emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk, lab)); | |
c5c76735 | 3867 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 4)); |
aaf701c5 | 3868 | return true; |
bc45ade3 | 3869 | } |
8d481241 JW |
3870 | |
3871 | /* Try to find a good way to implement the combiner pattern | |
3872 | [(set (match_operand:SI 0 "register_operand" "r") | |
3873 | (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") | |
3874 | (match_operand:SI 2 "const_int_operand" "n")) | |
3875 | (match_operand:SI 3 "const_int_operand" "n"))) . | |
3876 | LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3. | |
3877 | return 0 for simple right / left or left/right shift combination. | |
3878 | return 1 for a combination of shifts with zero_extend. | |
3879 | return 2 for a combination of shifts with an AND that needs r0. | |
3880 | return 3 for a combination of shifts with an AND that needs an extra | |
3881 | scratch register, when the three highmost bits of the AND mask are clear. | |
3882 | return 4 for a combination of shifts with an AND that needs an extra | |
3883 | scratch register, when any of the three highmost bits of the AND mask | |
3884 | is set. | |
3885 | If ATTRP is set, store an initial right shift width in ATTRP[0], | |
3886 | and the instruction length in ATTRP[1] . These values are not valid | |
3887 | when returning 0. | |
3888 | When ATTRP is set and returning 1, ATTRP[2] gets set to the index into | |
3889 | shift_amounts for the last shift value that is to be used before the | |
3890 | sign extend. */ | |
3891 | int | |
cf277499 | 3892 | shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp) |
8d481241 JW |
3893 | { |
3894 | unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2; | |
3895 | int left = INTVAL (left_rtx), right; | |
3896 | int best = 0; | |
3897 | int cost, best_cost = 10000; | |
3898 | int best_right = 0, best_len = 0; | |
3899 | int i; | |
3900 | int can_ext; | |
3901 | ||
3902 | if (left < 0 || left > 31) | |
3903 | return 0; | |
f3536097 | 3904 | if (CONST_INT_P (mask_rtx)) |
8d481241 JW |
3905 | mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left; |
3906 | else | |
3907 | mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left; | |
832a3292 | 3908 | /* Can this be expressed as a right shift / left shift pair? */ |
8d481241 JW |
3909 | lsb = ((mask ^ (mask - 1)) >> 1) + 1; |
3910 | right = exact_log2 (lsb); | |
3911 | mask2 = ~(mask + lsb - 1); | |
3912 | lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1; | |
3913 | /* mask has no zeroes but trailing zeroes <==> ! mask2 */ | |
3914 | if (! mask2) | |
70d4736c OE |
3915 | best_cost = ashl_lshr_seq[right].insn_count |
3916 | + ashl_lshr_seq[right + left].insn_count; | |
8d481241 JW |
3917 | /* mask has no trailing zeroes <==> ! right */ |
3918 | else if (! right && mask2 == ~(lsb2 - 1)) | |
3919 | { | |
3920 | int late_right = exact_log2 (lsb2); | |
70d4736c OE |
3921 | best_cost = ashl_lshr_seq[left + late_right].insn_count |
3922 | + ashl_lshr_seq[late_right].insn_count; | |
8d481241 | 3923 | } |
832a3292 | 3924 | /* Try to use zero extend. */ |
8d481241 JW |
3925 | if (mask2 == ~(lsb2 - 1)) |
3926 | { | |
3927 | int width, first; | |
3928 | ||
3929 | for (width = 8; width <= 16; width += 8) | |
3930 | { | |
832a3292 KH |
3931 | /* Can we zero-extend right away? */ |
3932 | if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width) | |
8d481241 | 3933 | { |
70d4736c OE |
3934 | cost = 1 + ext_ashl_lshr_seq[right].insn_count |
3935 | + ext_ashl_lshr_seq[left + right].insn_count; | |
8d481241 JW |
3936 | if (cost < best_cost) |
3937 | { | |
3938 | best = 1; | |
3939 | best_cost = cost; | |
3940 | best_right = right; | |
3941 | best_len = cost; | |
3942 | if (attrp) | |
3943 | attrp[2] = -1; | |
3944 | } | |
3945 | continue; | |
3946 | } | |
3947 | /* ??? Could try to put zero extend into initial right shift, | |
6f317ef3 | 3948 | or even shift a bit left before the right shift. */ |
8d481241 JW |
3949 | /* Determine value of first part of left shift, to get to the |
3950 | zero extend cut-off point. */ | |
3951 | first = width - exact_log2 (lsb2) + right; | |
3952 | if (first >= 0 && right + left - first >= 0) | |
3953 | { | |
70d4736c OE |
3954 | cost = ext_ashl_lshr_seq[right].insn_count |
3955 | + ext_ashl_lshr_seq[first].insn_count + 1 | |
3956 | + ext_ashl_lshr_seq[right + left - first].insn_count; | |
3957 | ||
8d481241 JW |
3958 | if (cost < best_cost) |
3959 | { | |
3960 | best = 1; | |
3961 | best_cost = cost; | |
3962 | best_right = right; | |
3963 | best_len = cost; | |
3964 | if (attrp) | |
3965 | attrp[2] = first; | |
832a3292 | 3966 | } |
8d481241 JW |
3967 | } |
3968 | } | |
3969 | } | |
3970 | /* Try to use r0 AND pattern */ | |
3971 | for (i = 0; i <= 2; i++) | |
3972 | { | |
3973 | if (i > right) | |
3974 | break; | |
735cb76e | 3975 | if (! CONST_OK_FOR_K08 (mask >> i)) |
8d481241 | 3976 | continue; |
70d4736c | 3977 | cost = (i != 0) + 2 + ext_ashl_lshr_seq[left + i].insn_count; |
8d481241 JW |
3978 | if (cost < best_cost) |
3979 | { | |
3980 | best = 2; | |
3981 | best_cost = cost; | |
3982 | best_right = i; | |
3983 | best_len = cost - 1; | |
3984 | } | |
3985 | } | |
3986 | /* Try to use a scratch register to hold the AND operand. */ | |
832a3292 | 3987 | can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0; |
8d481241 JW |
3988 | for (i = 0; i <= 2; i++) |
3989 | { | |
3990 | if (i > right) | |
3991 | break; | |
735cb76e | 3992 | cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3) |
70d4736c OE |
3993 | + (can_ext |
3994 | ? ext_ashl_lshr_seq | |
3995 | : ashl_lshr_seq)[left + i].insn_count; | |
8d481241 JW |
3996 | if (cost < best_cost) |
3997 | { | |
3998 | best = 4 - can_ext; | |
3999 | best_cost = cost; | |
4000 | best_right = i; | |
735cb76e | 4001 | best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i); |
8d481241 JW |
4002 | } |
4003 | } | |
4004 | ||
4005 | if (attrp) | |
4006 | { | |
4007 | attrp[0] = best_right; | |
4008 | attrp[1] = best_len; | |
4009 | } | |
4010 | return best; | |
4011 | } | |
4012 | ||
4013 | /* This is used in length attributes of the unnamed instructions | |
4014 | corresponding to shl_and_kind return values of 1 and 2. */ | |
4015 | int | |
cf277499 | 4016 | shl_and_length (rtx insn) |
8d481241 JW |
4017 | { |
4018 | rtx set_src, left_rtx, mask_rtx; | |
4019 | int attributes[3]; | |
4020 | ||
4021 | set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
4022 | left_rtx = XEXP (XEXP (set_src, 0), 1); | |
4023 | mask_rtx = XEXP (set_src, 1); | |
4024 | shl_and_kind (left_rtx, mask_rtx, attributes); | |
4025 | return attributes[1]; | |
4026 | } | |
4027 | ||
4028 | /* This is used in length attribute of the and_shl_scratch instruction. */ | |
8d481241 | 4029 | int |
cf277499 | 4030 | shl_and_scr_length (rtx insn) |
8d481241 JW |
4031 | { |
4032 | rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
70d4736c | 4033 | int len = ashl_lshr_seq[INTVAL (XEXP (set_src, 1)) & 31].insn_count; |
8d481241 | 4034 | rtx op = XEXP (set_src, 0); |
70d4736c | 4035 | len += ashl_lshr_seq[INTVAL (XEXP (op, 1)) & 31].insn_count + 1; |
8d481241 | 4036 | op = XEXP (XEXP (op, 0), 0); |
70d4736c | 4037 | return len + ashl_lshr_seq[INTVAL (XEXP (op, 1)) & 31].insn_count; |
8d481241 JW |
4038 | } |
4039 | ||
8d481241 JW |
4040 | /* Generate rtl for instructions for which shl_and_kind advised a particular |
4041 | method of generating them, i.e. returned zero. */ | |
aaf701c5 | 4042 | bool |
cf277499 | 4043 | gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source) |
8d481241 JW |
4044 | { |
4045 | int attributes[3]; | |
4046 | unsigned HOST_WIDE_INT mask; | |
4047 | int kind = shl_and_kind (left_rtx, mask_rtx, attributes); | |
4048 | int right, total_shift; | |
832a3292 | 4049 | void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op; |
8d481241 JW |
4050 | |
4051 | right = attributes[0]; | |
4052 | total_shift = INTVAL (left_rtx) + right; | |
4053 | mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift; | |
4054 | switch (kind) | |
4055 | { | |
4056 | default: | |
aaf701c5 | 4057 | return true; |
8d481241 JW |
4058 | case 1: |
4059 | { | |
4060 | int first = attributes[2]; | |
4061 | rtx operands[3]; | |
4062 | ||
4063 | if (first < 0) | |
4064 | { | |
7174c937 | 4065 | emit_insn ((mask << right) <= 0xff |
832a3292 KH |
4066 | ? gen_zero_extendqisi2 (dest, |
4067 | gen_lowpart (QImode, source)) | |
4068 | : gen_zero_extendhisi2 (dest, | |
4069 | gen_lowpart (HImode, source))); | |
8d481241 JW |
4070 | source = dest; |
4071 | } | |
4072 | if (source != dest) | |
4073 | emit_insn (gen_movsi (dest, source)); | |
4074 | operands[0] = dest; | |
4075 | if (right) | |
4076 | { | |
4077 | operands[2] = GEN_INT (right); | |
4078 | gen_shifty_hi_op (LSHIFTRT, operands); | |
4079 | } | |
4080 | if (first > 0) | |
4081 | { | |
4082 | operands[2] = GEN_INT (first); | |
4083 | gen_shifty_hi_op (ASHIFT, operands); | |
4084 | total_shift -= first; | |
4085 | mask <<= first; | |
4086 | } | |
4087 | if (first >= 0) | |
85af47b9 | 4088 | emit_insn (mask <= 0xff |
832a3292 KH |
4089 | ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest)) |
4090 | : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest))); | |
8d481241 JW |
4091 | if (total_shift > 0) |
4092 | { | |
4093 | operands[2] = GEN_INT (total_shift); | |
4094 | gen_shifty_hi_op (ASHIFT, operands); | |
4095 | } | |
4096 | break; | |
4097 | } | |
4098 | case 4: | |
4099 | shift_gen_fun = gen_shifty_op; | |
133634de | 4100 | /* FALLTHRU */ |
8d481241 | 4101 | case 3: |
24c50999 JR |
4102 | /* If the topmost bit that matters is set, set the topmost bits |
4103 | that don't matter. This way, we might be able to get a shorter | |
4104 | signed constant. */ | |
832a3292 | 4105 | if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift))) |
e3ed8bb7 | 4106 | mask |= (HOST_WIDE_INT) ((HOST_WIDE_INT_M1U) << (31 - total_shift)); |
133634de | 4107 | /* FALLTHRU */ |
61fb6bac | 4108 | case 2: |
8d481241 JW |
4109 | /* Don't expand fine-grained when combining, because that will |
4110 | make the pattern fail. */ | |
4586b4ca | 4111 | if (currently_expanding_to_rtl |
8d481241 JW |
4112 | || reload_in_progress || reload_completed) |
4113 | { | |
4114 | rtx operands[3]; | |
f676971a | 4115 | |
61fb6bac R |
4116 | /* Cases 3 and 4 should be handled by this split |
4117 | only while combining */ | |
f5b9e7c9 | 4118 | gcc_assert (kind <= 2); |
8d481241 JW |
4119 | if (right) |
4120 | { | |
4121 | emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right))); | |
4122 | source = dest; | |
4123 | } | |
4124 | emit_insn (gen_andsi3 (dest, source, GEN_INT (mask))); | |
afad3d2c JW |
4125 | if (total_shift) |
4126 | { | |
4127 | operands[0] = dest; | |
4128 | operands[1] = dest; | |
4129 | operands[2] = GEN_INT (total_shift); | |
4130 | shift_gen_fun (ASHIFT, operands); | |
4131 | } | |
8d481241 JW |
4132 | break; |
4133 | } | |
4134 | else | |
4135 | { | |
4136 | int neg = 0; | |
4137 | if (kind != 4 && total_shift < 16) | |
4138 | { | |
70d4736c | 4139 | neg = -ext_ashl_lshr_seq[total_shift].amount[1]; |
8d481241 | 4140 | if (neg > 0) |
70d4736c | 4141 | neg -= ext_ashl_lshr_seq[total_shift].amount[2]; |
8d481241 JW |
4142 | else |
4143 | neg = 0; | |
4144 | } | |
4145 | emit_insn (gen_and_shl_scratch (dest, source, | |
4146 | GEN_INT (right), | |
4147 | GEN_INT (mask), | |
4148 | GEN_INT (total_shift + neg), | |
4149 | GEN_INT (neg))); | |
4150 | emit_insn (gen_movsi (dest, dest)); | |
4151 | break; | |
4152 | } | |
4153 | } | |
aaf701c5 | 4154 | return false; |
8d481241 JW |
4155 | } |
4156 | ||
4157 | /* Try to find a good way to implement the combiner pattern | |
4158 | [(set (match_operand:SI 0 "register_operand" "=r") | |
4159 | (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") | |
4160 | (match_operand:SI 2 "const_int_operand" "n") | |
4161 | (match_operand:SI 3 "const_int_operand" "n") | |
4162 | (const_int 0))) | |
4773afa4 | 4163 | (clobber (reg:SI T_REG))] |
8d481241 JW |
4164 | LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3. |
4165 | return 0 for simple left / right shift combination. | |
4166 | return 1 for left shift / 8 bit sign extend / left shift. | |
4167 | return 2 for left shift / 16 bit sign extend / left shift. | |
4168 | return 3 for left shift / 8 bit sign extend / shift / sign extend. | |
4169 | return 4 for left shift / 16 bit sign extend / shift / sign extend. | |
4170 | return 5 for left shift / 16 bit sign extend / right shift | |
4171 | return 6 for < 8 bit sign extend / left shift. | |
4172 | return 7 for < 8 bit sign extend / left shift / single right shift. | |
4173 | If COSTP is nonzero, assign the calculated cost to *COSTP. */ | |
8d481241 | 4174 | int |
cf277499 | 4175 | shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp) |
8d481241 JW |
4176 | { |
4177 | int left, size, insize, ext; | |
3a8699c7 | 4178 | int cost = 0, best_cost; |
8d481241 JW |
4179 | int kind; |
4180 | ||
4181 | left = INTVAL (left_rtx); | |
4182 | size = INTVAL (size_rtx); | |
4183 | insize = size - left; | |
f5b9e7c9 | 4184 | gcc_assert (insize > 0); |
8d481241 JW |
4185 | /* Default to left / right shift. */ |
4186 | kind = 0; | |
70d4736c OE |
4187 | best_cost = ashl_lshr_seq[32 - insize].insn_count |
4188 | + ashl_lshr_seq[32 - size].insn_count; | |
8d481241 JW |
4189 | if (size <= 16) |
4190 | { | |
4191 | /* 16 bit shift / sign extend / 16 bit shift */ | |
70d4736c OE |
4192 | cost = ashl_lshr_seq[16 - insize].insn_count + 1 |
4193 | + ashl_lshr_seq[16 - size].insn_count; | |
afad3d2c JW |
4194 | /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden |
4195 | below, by alternative 3 or something even better. */ | |
8d481241 JW |
4196 | if (cost < best_cost) |
4197 | { | |
4198 | kind = 5; | |
4199 | best_cost = cost; | |
4200 | } | |
4201 | } | |
4202 | /* Try a plain sign extend between two shifts. */ | |
4203 | for (ext = 16; ext >= insize; ext -= 8) | |
4204 | { | |
4205 | if (ext <= size) | |
4206 | { | |
70d4736c OE |
4207 | cost = ext_ashl_lshr_seq[ext - insize].insn_count + 1 |
4208 | + ashl_lshr_seq[size - ext].insn_count; | |
8d481241 JW |
4209 | if (cost < best_cost) |
4210 | { | |
11f9ed1a | 4211 | kind = ext / (unsigned) 8; |
8d481241 JW |
4212 | best_cost = cost; |
4213 | } | |
4214 | } | |
ae9d19c0 JR |
4215 | /* Check if we can do a sloppy shift with a final signed shift |
4216 | restoring the sign. */ | |
4217 | if (EXT_SHIFT_SIGNED (size - ext)) | |
70d4736c OE |
4218 | cost = ext_ashl_lshr_seq[ext - insize].insn_count |
4219 | + ext_ashl_lshr_seq[size - ext].insn_count + 1; | |
ae9d19c0 JR |
4220 | /* If not, maybe it's still cheaper to do the second shift sloppy, |
4221 | and do a final sign extend? */ | |
4222 | else if (size <= 16) | |
70d4736c OE |
4223 | cost = ext_ashl_lshr_seq[ext - insize].insn_count + 1 |
4224 | + ext_ashl_lshr_seq[size > ext ? size - ext : ext - size].insn_count | |
4225 | + 1; | |
ae9d19c0 JR |
4226 | else |
4227 | continue; | |
4228 | if (cost < best_cost) | |
8d481241 | 4229 | { |
11f9ed1a | 4230 | kind = ext / (unsigned) 8 + 2; |
ae9d19c0 | 4231 | best_cost = cost; |
8d481241 JW |
4232 | } |
4233 | } | |
4234 | /* Check if we can sign extend in r0 */ | |
4235 | if (insize < 8) | |
4236 | { | |
70d4736c | 4237 | cost = 3 + ashl_lshr_seq[left].insn_count; |
8d481241 JW |
4238 | if (cost < best_cost) |
4239 | { | |
4240 | kind = 6; | |
4241 | best_cost = cost; | |
4242 | } | |
4243 | /* Try the same with a final signed shift. */ | |
4244 | if (left < 31) | |
4245 | { | |
70d4736c | 4246 | cost = 3 + ext_ashl_lshr_seq[left + 1].insn_count + 1; |
8d481241 JW |
4247 | if (cost < best_cost) |
4248 | { | |
4249 | kind = 7; | |
4250 | best_cost = cost; | |
4251 | } | |
4252 | } | |
4253 | } | |
a594120b | 4254 | if (TARGET_DYNSHIFT) |
8d481241 JW |
4255 | { |
4256 | /* Try to use a dynamic shift. */ | |
70d4736c | 4257 | cost = ashl_lshr_seq[32 - insize].insn_count + 1 + SH_DYNAMIC_SHIFT_COST; |
8d481241 JW |
4258 | if (cost < best_cost) |
4259 | { | |
4260 | kind = 0; | |
4261 | best_cost = cost; | |
4262 | } | |
4263 | } | |
4264 | if (costp) | |
4265 | *costp = cost; | |
4266 | return kind; | |
4267 | } | |
4268 | ||
4269 | /* Function to be used in the length attribute of the instructions | |
4270 | implementing this pattern. */ | |
8d481241 | 4271 | int |
cf277499 | 4272 | shl_sext_length (rtx insn) |
8d481241 JW |
4273 | { |
4274 | rtx set_src, left_rtx, size_rtx; | |
4275 | int cost; | |
4276 | ||
4277 | set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
4278 | left_rtx = XEXP (XEXP (set_src, 0), 1); | |
4279 | size_rtx = XEXP (set_src, 1); | |
4280 | shl_sext_kind (left_rtx, size_rtx, &cost); | |
4281 | return cost; | |
4282 | } | |
4283 | ||
4284 | /* Generate rtl for this pattern */ | |
aaf701c5 | 4285 | bool |
cf277499 | 4286 | gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source) |
8d481241 JW |
4287 | { |
4288 | int kind; | |
d00d338c | 4289 | int left, size, insize, cost; |
8d481241 JW |
4290 | rtx operands[3]; |
4291 | ||
d00d338c | 4292 | kind = shl_sext_kind (left_rtx, size_rtx, &cost); |
8d481241 JW |
4293 | left = INTVAL (left_rtx); |
4294 | size = INTVAL (size_rtx); | |
4295 | insize = size - left; | |
4296 | switch (kind) | |
4297 | { | |
4298 | case 1: | |
4299 | case 2: | |
4300 | case 3: | |
4301 | case 4: | |
4302 | { | |
4303 | int ext = kind & 1 ? 8 : 16; | |
4304 | int shift2 = size - ext; | |
4305 | ||
4306 | /* Don't expand fine-grained when combining, because that will | |
4307 | make the pattern fail. */ | |
4586b4ca | 4308 | if (! currently_expanding_to_rtl |
8d481241 JW |
4309 | && ! reload_in_progress && ! reload_completed) |
4310 | { | |
4311 | emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx)); | |
4312 | emit_insn (gen_movsi (dest, source)); | |
4313 | break; | |
4314 | } | |
4315 | if (dest != source) | |
4316 | emit_insn (gen_movsi (dest, source)); | |
4317 | operands[0] = dest; | |
afad3d2c JW |
4318 | if (ext - insize) |
4319 | { | |
4320 | operands[2] = GEN_INT (ext - insize); | |
4321 | gen_shifty_hi_op (ASHIFT, operands); | |
4322 | } | |
8d481241 | 4323 | emit_insn (kind & 1 |
832a3292 KH |
4324 | ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest)) |
4325 | : gen_extendhisi2 (dest, gen_lowpart (HImode, dest))); | |
8d481241 JW |
4326 | if (kind <= 2) |
4327 | { | |
afad3d2c JW |
4328 | if (shift2) |
4329 | { | |
4330 | operands[2] = GEN_INT (shift2); | |
4331 | gen_shifty_op (ASHIFT, operands); | |
4332 | } | |
8d481241 JW |
4333 | } |
4334 | else | |
4335 | { | |
afad3d2c | 4336 | if (shift2 > 0) |
8d481241 | 4337 | { |
ae9d19c0 JR |
4338 | if (EXT_SHIFT_SIGNED (shift2)) |
4339 | { | |
4340 | operands[2] = GEN_INT (shift2 + 1); | |
4341 | gen_shifty_op (ASHIFT, operands); | |
a556fd39 | 4342 | operands[2] = const1_rtx; |
ae9d19c0 JR |
4343 | gen_shifty_op (ASHIFTRT, operands); |
4344 | break; | |
4345 | } | |
8d481241 JW |
4346 | operands[2] = GEN_INT (shift2); |
4347 | gen_shifty_hi_op (ASHIFT, operands); | |
4348 | } | |
afad3d2c | 4349 | else if (shift2) |
8d481241 JW |
4350 | { |
4351 | operands[2] = GEN_INT (-shift2); | |
4352 | gen_shifty_hi_op (LSHIFTRT, operands); | |
4353 | } | |
4354 | emit_insn (size <= 8 | |
afad3d2c JW |
4355 | ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest)) |
4356 | : gen_extendhisi2 (dest, gen_lowpart (HImode, dest))); | |
8d481241 JW |
4357 | } |
4358 | break; | |
4359 | } | |
4360 | case 5: | |
afad3d2c JW |
4361 | { |
4362 | int i = 16 - size; | |
4586b4ca | 4363 | if (! currently_expanding_to_rtl |
913d8e13 R |
4364 | && ! reload_in_progress && ! reload_completed) |
4365 | emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx)); | |
4366 | else | |
4367 | { | |
4368 | operands[0] = dest; | |
4369 | operands[2] = GEN_INT (16 - insize); | |
4370 | gen_shifty_hi_op (ASHIFT, operands); | |
4371 | emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest))); | |
4372 | } | |
afad3d2c JW |
4373 | /* Don't use gen_ashrsi3 because it generates new pseudos. */ |
4374 | while (--i >= 0) | |
4375 | gen_ashift (ASHIFTRT, 1, dest); | |
4376 | break; | |
4377 | } | |
8d481241 JW |
4378 | case 6: |
4379 | case 7: | |
4380 | /* Don't expand fine-grained when combining, because that will | |
4381 | make the pattern fail. */ | |
4586b4ca | 4382 | if (! currently_expanding_to_rtl |
8d481241 JW |
4383 | && ! reload_in_progress && ! reload_completed) |
4384 | { | |
4385 | emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx)); | |
4386 | emit_insn (gen_movsi (dest, source)); | |
4387 | break; | |
4388 | } | |
4389 | emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1))); | |
4390 | emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1)))); | |
e3ed8bb7 | 4391 | emit_insn (gen_addsi3 (dest, dest, GEN_INT (HOST_WIDE_INT_M1U << (insize - 1)))); |
8d481241 JW |
4392 | operands[0] = dest; |
4393 | operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx; | |
4394 | gen_shifty_op (ASHIFT, operands); | |
4395 | if (kind == 7) | |
a556fd39 | 4396 | emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx)); |
8d481241 JW |
4397 | break; |
4398 | default: | |
aaf701c5 | 4399 | return true; |
8d481241 | 4400 | } |
aaf701c5 | 4401 | return false; |
8d481241 | 4402 | } |
fa5322fa | 4403 | |
6dd3c0a5 SB |
4404 | typedef struct label_ref_list_d |
4405 | { | |
6cb7eb41 | 4406 | rtx_code_label *label; |
6dd3c0a5 SB |
4407 | struct label_ref_list_d *next; |
4408 | } *label_ref_list_t; | |
4409 | ||
fb0b2914 | 4410 | static object_allocator<label_ref_list_d> label_ref_list_d_pool |
8c464611 | 4411 | ("label references list"); |
533ab6c4 | 4412 | |
8aa2a305 JW |
4413 | /* The SH cannot load a large constant into a register, constants have to |
4414 | come from a pc relative load. The reference of a pc relative load | |
0fa2e4df | 4415 | instruction must be less than 1k in front of the instruction. This |
8aa2a305 JW |
4416 | means that we often have to dump a constant inside a function, and |
4417 | generate code to branch around it. | |
bc45ade3 | 4418 | |
8aa2a305 JW |
4419 | It is important to minimize this, since the branches will slow things |
4420 | down and make things bigger. | |
4421 | ||
4422 | Worst case code looks like: | |
4423 | ||
4424 | mov.l L1,rn | |
4425 | bra L2 | |
4426 | nop | |
4427 | align | |
4428 | L1: .long value | |
4429 | L2: | |
4430 | .. | |
4431 | ||
4432 | mov.l L3,rn | |
4433 | bra L4 | |
4434 | nop | |
4435 | align | |
4436 | L3: .long value | |
4437 | L4: | |
4438 | .. | |
4439 | ||
4440 | We fix this by performing a scan before scheduling, which notices which | |
4441 | instructions need to have their operands fetched from the constant table | |
4442 | and builds the table. | |
4443 | ||
4444 | The algorithm is: | |
4445 | ||
4446 | scan, find an instruction which needs a pcrel move. Look forward, find the | |
4447 | last barrier which is within MAX_COUNT bytes of the requirement. | |
4448 | If there isn't one, make one. Process all the instructions between | |
4449 | the find and the barrier. | |
4450 | ||
4451 | In the above example, we can tell that L3 is within 1k of L1, so | |
4452 | the first move can be shrunk from the 3 insn+constant sequence into | |
4453 | just 1 insn, and the constant moved to L3 to make: | |
4454 | ||
4455 | mov.l L1,rn | |
4456 | .. | |
4457 | mov.l L3,rn | |
4458 | bra L4 | |
4459 | nop | |
4460 | align | |
4461 | L3:.long value | |
4462 | L4:.long value | |
4463 | ||
4464 | Then the second move becomes the target for the shortening process. */ | |
4465 | ||
4466 | typedef struct | |
4467 | { | |
4468 | rtx value; /* Value in table. */ | |
6cb7eb41 | 4469 | rtx_code_label *label; /* Label of value. */ |
6dd3c0a5 | 4470 | label_ref_list_t wend; /* End of window. */ |
ef4bddc2 | 4471 | machine_mode mode; /* Mode of value. */ |
3503150c RS |
4472 | |
4473 | /* True if this constant is accessed as part of a post-increment | |
4474 | sequence. Note that HImode constants are never accessed in this way. */ | |
4475 | bool part_of_sequence_p; | |
8aa2a305 JW |
4476 | } pool_node; |
4477 | ||
4478 | /* The maximum number of constants that can fit into one pool, since | |
73a4d10b R |
4479 | constants in the range 0..510 are at least 2 bytes long, and in the |
4480 | range from there to 1018 at least 4 bytes. */ | |
8aa2a305 | 4481 | |
73a4d10b | 4482 | #define MAX_POOL_SIZE 372 |
8aa2a305 JW |
4483 | static pool_node pool_vector[MAX_POOL_SIZE]; |
4484 | static int pool_size; | |
6cb7eb41 | 4485 | static rtx_code_label *pool_window_label; |
b91455de | 4486 | static int pool_window_last; |
8aa2a305 | 4487 | |
4241ecb0 R |
4488 | static int max_labelno_before_reorg; |
4489 | ||
8aa2a305 JW |
4490 | /* ??? If we need a constant in HImode which is the truncated value of a |
4491 | constant we need in SImode, we could combine the two entries thus saving | |
4492 | two bytes. Is this common enough to be worth the effort of implementing | |
4493 | it? */ | |
4494 | ||
4495 | /* ??? This stuff should be done at the same time that we shorten branches. | |
4496 | As it is now, we must assume that all branches are the maximum size, and | |
4497 | this causes us to almost always output constant pools sooner than | |
4498 | necessary. */ | |
4499 | ||
4500 | /* Add a constant to the pool and return its label. */ | |
6cb7eb41 | 4501 | static rtx_code_label * |
ef4bddc2 | 4502 | add_constant (rtx x, machine_mode mode, rtx last_value) |
0d7e008e | 4503 | { |
6cb7eb41 | 4504 | rtx_code_label *lab, *new_rtx; |
6dd3c0a5 | 4505 | label_ref_list_t ref, newref; |
8aa2a305 JW |
4506 | |
4507 | /* First see if we've already got it. */ | |
df4bacab | 4508 | for (int i = 0; i < pool_size; i++) |
0d7e008e | 4509 | { |
8aa2a305 JW |
4510 | if (x->code == pool_vector[i].value->code |
4511 | && mode == pool_vector[i].mode) | |
0d7e008e | 4512 | { |
8aa2a305 JW |
4513 | if (x->code == CODE_LABEL) |
4514 | { | |
4515 | if (XINT (x, 3) != XINT (pool_vector[i].value, 3)) | |
4516 | continue; | |
4517 | } | |
4518 | if (rtx_equal_p (x, pool_vector[i].value)) | |
225e4f43 | 4519 | { |
0a2aaacc | 4520 | lab = new_rtx = 0; |
225e4f43 R |
4521 | if (! last_value |
4522 | || ! i | |
4523 | || ! rtx_equal_p (last_value, pool_vector[i-1].value)) | |
4524 | { | |
0a2aaacc KG |
4525 | new_rtx = gen_label_rtx (); |
4526 | LABEL_REFS (new_rtx) = pool_vector[i].label; | |
4527 | pool_vector[i].label = lab = new_rtx; | |
225e4f43 | 4528 | } |
b91455de KK |
4529 | if (lab && pool_window_label) |
4530 | { | |
fb0b2914 | 4531 | newref = label_ref_list_d_pool.allocate (); |
6dd3c0a5 | 4532 | newref->label = pool_window_label; |
b91455de | 4533 | ref = pool_vector[pool_window_last].wend; |
6dd3c0a5 | 4534 | newref->next = ref; |
b91455de KK |
4535 | pool_vector[pool_window_last].wend = newref; |
4536 | } | |
0a2aaacc KG |
4537 | if (new_rtx) |
4538 | pool_window_label = new_rtx; | |
b91455de | 4539 | pool_window_last = i; |
225e4f43 R |
4540 | return lab; |
4541 | } | |
0d7e008e | 4542 | } |
0d7e008e | 4543 | } |
b9654711 | 4544 | |
8aa2a305 JW |
4545 | /* Need a new one. */ |
4546 | pool_vector[pool_size].value = x; | |
225e4f43 | 4547 | if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value)) |
3503150c RS |
4548 | { |
4549 | lab = 0; | |
4550 | pool_vector[pool_size - 1].part_of_sequence_p = true; | |
4551 | } | |
225e4f43 R |
4552 | else |
4553 | lab = gen_label_rtx (); | |
8aa2a305 JW |
4554 | pool_vector[pool_size].mode = mode; |
4555 | pool_vector[pool_size].label = lab; | |
6dd3c0a5 | 4556 | pool_vector[pool_size].wend = NULL; |
3503150c | 4557 | pool_vector[pool_size].part_of_sequence_p = (lab == 0); |
b91455de KK |
4558 | if (lab && pool_window_label) |
4559 | { | |
fb0b2914 | 4560 | newref = label_ref_list_d_pool.allocate (); |
6dd3c0a5 | 4561 | newref->label = pool_window_label; |
b91455de | 4562 | ref = pool_vector[pool_window_last].wend; |
6dd3c0a5 | 4563 | newref->next = ref; |
b91455de KK |
4564 | pool_vector[pool_window_last].wend = newref; |
4565 | } | |
4566 | if (lab) | |
4567 | pool_window_label = lab; | |
4568 | pool_window_last = pool_size; | |
8aa2a305 JW |
4569 | pool_size++; |
4570 | return lab; | |
0d7e008e | 4571 | } |
16bea517 | 4572 | |
078c8b08 R |
4573 | /* Output the literal table. START, if nonzero, is the first instruction |
4574 | this table is needed for, and also indicates that there is at least one | |
4575 | casesi_worker_2 instruction; We have to emit the operand3 labels from | |
4576 | these insns at a 4-byte aligned position. BARRIER is the barrier | |
4577 | after which we are to place the table. */ | |
b9654711 | 4578 | static void |
6cb7eb41 | 4579 | dump_table (rtx_insn *start, rtx_insn *barrier) |
b9654711 | 4580 | { |
6cb7eb41 | 4581 | rtx_insn *scan = barrier; |
23d0939b | 4582 | bool need_align = true; |
6dd3c0a5 SB |
4583 | rtx lab; |
4584 | label_ref_list_t ref; | |
23d0939b | 4585 | bool have_df = false; |
b9654711 | 4586 | |
16bea517 | 4587 | /* Do two passes, first time dump out the HI sized constants. */ |
b9654711 | 4588 | |
df4bacab | 4589 | for (int i = 0; i < pool_size; i++) |
b9654711 | 4590 | { |
8aa2a305 JW |
4591 | pool_node *p = &pool_vector[i]; |
4592 | ||
0d7e008e SC |
4593 | if (p->mode == HImode) |
4594 | { | |
4595 | if (need_align) | |
4596 | { | |
4597 | scan = emit_insn_after (gen_align_2 (), scan); | |
23d0939b | 4598 | need_align = false; |
0d7e008e | 4599 | } |
b91455de KK |
4600 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) |
4601 | scan = emit_label_after (lab, scan); | |
4602 | scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx), | |
4603 | scan); | |
6dd3c0a5 | 4604 | for (ref = p->wend; ref; ref = ref->next) |
b91455de | 4605 | { |
6dd3c0a5 | 4606 | lab = ref->label; |
b91455de KK |
4607 | scan = emit_insn_after (gen_consttable_window_end (lab), scan); |
4608 | } | |
0d7e008e | 4609 | } |
aa06e8f5 | 4610 | else if (p->mode == DFmode) |
23d0939b | 4611 | have_df = true; |
b9654711 | 4612 | } |
8aa2a305 | 4613 | |
23d0939b | 4614 | need_align = true; |
b9654711 | 4615 | |
078c8b08 R |
4616 | if (start) |
4617 | { | |
4618 | scan = emit_insn_after (gen_align_4 (), scan); | |
23d0939b | 4619 | need_align = false; |
078c8b08 | 4620 | for (; start != barrier; start = NEXT_INSN (start)) |
f3536097 | 4621 | if (NONJUMP_INSN_P (start) |
078c8b08 R |
4622 | && recog_memoized (start) == CODE_FOR_casesi_worker_2) |
4623 | { | |
4624 | rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0)); | |
4625 | rtx lab = XEXP (XVECEXP (src, 0, 3), 0); | |
4626 | ||
4627 | scan = emit_label_after (lab, scan); | |
4628 | } | |
4629 | } | |
aa06e8f5 | 4630 | if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df) |
fa5322fa | 4631 | { |
e60365d3 | 4632 | rtx_insn *align_insn = NULL; |
fa5322fa AO |
4633 | |
4634 | scan = emit_label_after (gen_label_rtx (), scan); | |
4635 | scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan); | |
23d0939b | 4636 | need_align = false; |
fa5322fa | 4637 | |
df4bacab | 4638 | for (int i = 0; i < pool_size; i++) |
fa5322fa AO |
4639 | { |
4640 | pool_node *p = &pool_vector[i]; | |
4641 | ||
4642 | switch (p->mode) | |
4643 | { | |
4e10a5a7 | 4644 | case E_HImode: |
fa5322fa | 4645 | break; |
4e10a5a7 RS |
4646 | case E_SImode: |
4647 | case E_SFmode: | |
3503150c | 4648 | if (align_insn && !p->part_of_sequence_p) |
fa5322fa AO |
4649 | { |
4650 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) | |
4651 | emit_label_before (lab, align_insn); | |
4652 | emit_insn_before (gen_consttable_4 (p->value, const0_rtx), | |
4653 | align_insn); | |
6dd3c0a5 | 4654 | for (ref = p->wend; ref; ref = ref->next) |
fa5322fa | 4655 | { |
6dd3c0a5 | 4656 | lab = ref->label; |
fa5322fa | 4657 | emit_insn_before (gen_consttable_window_end (lab), |
832a3292 | 4658 | align_insn); |
fa5322fa AO |
4659 | } |
4660 | delete_insn (align_insn); | |
e60365d3 | 4661 | align_insn = NULL; |
fa5322fa AO |
4662 | continue; |
4663 | } | |
4664 | else | |
4665 | { | |
4666 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) | |
4667 | scan = emit_label_after (lab, scan); | |
4668 | scan = emit_insn_after (gen_consttable_4 (p->value, | |
4669 | const0_rtx), scan); | |
4670 | need_align = ! need_align; | |
4671 | } | |
4672 | break; | |
4e10a5a7 | 4673 | case E_DFmode: |
fa5322fa AO |
4674 | if (need_align) |
4675 | { | |
4676 | scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan); | |
4677 | align_insn = scan; | |
23d0939b | 4678 | need_align = false; |
fa5322fa | 4679 | } |
133634de | 4680 | /* FALLTHRU */ |
4e10a5a7 | 4681 | case E_DImode: |
fa5322fa AO |
4682 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) |
4683 | scan = emit_label_after (lab, scan); | |
4684 | scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx), | |
4685 | scan); | |
4686 | break; | |
4687 | default: | |
f5b9e7c9 | 4688 | gcc_unreachable (); |
fa5322fa AO |
4689 | } |
4690 | ||
4691 | if (p->mode != HImode) | |
4692 | { | |
6dd3c0a5 | 4693 | for (ref = p->wend; ref; ref = ref->next) |
fa5322fa | 4694 | { |
6dd3c0a5 | 4695 | lab = ref->label; |
fa5322fa AO |
4696 | scan = emit_insn_after (gen_consttable_window_end (lab), |
4697 | scan); | |
4698 | } | |
4699 | } | |
4700 | } | |
4701 | ||
4702 | pool_size = 0; | |
4703 | } | |
f676971a | 4704 | |
df4bacab | 4705 | for (int i = 0; i < pool_size; i++) |
b9654711 | 4706 | { |
8aa2a305 | 4707 | pool_node *p = &pool_vector[i]; |
b9654711 | 4708 | |
0d7e008e | 4709 | switch (p->mode) |
b9654711 | 4710 | { |
4e10a5a7 | 4711 | case E_HImode: |
0d7e008e | 4712 | break; |
4e10a5a7 RS |
4713 | case E_SImode: |
4714 | case E_SFmode: | |
0d7e008e | 4715 | if (need_align) |
b9654711 | 4716 | { |
23d0939b | 4717 | need_align = false; |
d3ae8277 | 4718 | scan = emit_label_after (gen_label_rtx (), scan); |
0d7e008e | 4719 | scan = emit_insn_after (gen_align_4 (), scan); |
b9654711 | 4720 | } |
b91455de KK |
4721 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) |
4722 | scan = emit_label_after (lab, scan); | |
4723 | scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx), | |
4724 | scan); | |
0d7e008e | 4725 | break; |
4e10a5a7 RS |
4726 | case E_DFmode: |
4727 | case E_DImode: | |
0d7e008e SC |
4728 | if (need_align) |
4729 | { | |
23d0939b | 4730 | need_align = false; |
d3ae8277 | 4731 | scan = emit_label_after (gen_label_rtx (), scan); |
0d7e008e SC |
4732 | scan = emit_insn_after (gen_align_4 (), scan); |
4733 | } | |
b91455de KK |
4734 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) |
4735 | scan = emit_label_after (lab, scan); | |
4736 | scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx), | |
4737 | scan); | |
0d7e008e SC |
4738 | break; |
4739 | default: | |
f5b9e7c9 | 4740 | gcc_unreachable (); |
b9654711 | 4741 | } |
b91455de KK |
4742 | |
4743 | if (p->mode != HImode) | |
4744 | { | |
6dd3c0a5 | 4745 | for (ref = p->wend; ref; ref = ref->next) |
b91455de | 4746 | { |
6dd3c0a5 | 4747 | lab = ref->label; |
b91455de KK |
4748 | scan = emit_insn_after (gen_consttable_window_end (lab), scan); |
4749 | } | |
4750 | } | |
b9654711 | 4751 | } |
b9654711 | 4752 | |
0d7e008e SC |
4753 | scan = emit_insn_after (gen_consttable_end (), scan); |
4754 | scan = emit_barrier_after (scan); | |
4755 | pool_size = 0; | |
6cb7eb41 | 4756 | pool_window_label = NULL; |
b91455de | 4757 | pool_window_last = 0; |
0d7e008e | 4758 | } |
b9654711 | 4759 | |
4241ecb0 R |
4760 | #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0) |
4761 | ||
5e7a8ee0 | 4762 | /* Nonzero if the insn is a move instruction which needs to be fixed. */ |
8aa2a305 JW |
4763 | |
4764 | /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the | |
735cb76e R |
4765 | CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't |
4766 | need to fix it if the input value is CONST_OK_FOR_I08. */ | |
aaf701c5 | 4767 | static bool |
6cb7eb41 | 4768 | broken_move (rtx_insn *insn) |
b9654711 | 4769 | { |
f3536097 | 4770 | if (NONJUMP_INSN_P (insn)) |
e577c183 JR |
4771 | { |
4772 | rtx pat = PATTERN (insn); | |
4773 | if (GET_CODE (pat) == PARALLEL) | |
4774 | pat = XVECEXP (pat, 0, 0); | |
4775 | if (GET_CODE (pat) == SET | |
3b962ea0 | 4776 | /* We can load any 8-bit value if we don't care what the high |
e577c183 JR |
4777 | order bits end up as. */ |
4778 | && GET_MODE (SET_DEST (pat)) != QImode | |
43c05634 | 4779 | && (CONSTANT_P (SET_SRC (pat)) |
8b0a1e0b CB |
4780 | || (GET_CODE (SET_SRC (pat)) == UNSPEC_VOLATILE |
4781 | && XINT (SET_SRC (pat), 1) == UNSPECV_SP_SWITCH_B) | |
43c05634 AO |
4782 | /* Match mova_const. */ |
4783 | || (GET_CODE (SET_SRC (pat)) == UNSPEC | |
4784 | && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA | |
4785 | && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST)) | |
3a8699c7 | 4786 | && ! (TARGET_SH2E |
1245df60 | 4787 | && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE |
e577c183 JR |
4788 | && (fp_zero_operand (SET_SRC (pat)) |
4789 | || fp_one_operand (SET_SRC (pat))) | |
50fe8924 OE |
4790 | /* In general we don't know the current setting of fpscr, so |
4791 | disable fldi. | |
18778292 R |
4792 | There is an exception if this was a register-register move |
4793 | before reload - and hence it was ascertained that we have | |
4794 | single precision setting - and in a post-reload optimization | |
4795 | we changed this to do a constant load. In that case | |
4796 | we don't have an r0 clobber, hence we must use fldi. */ | |
7a61cf6f | 4797 | && (TARGET_FMOVD |
18778292 R |
4798 | || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0)) |
4799 | == SCRATCH)) | |
f3536097 | 4800 | && REG_P (SET_DEST (pat)) |
104ee20b | 4801 | && FP_REGISTER_P (REGNO (SET_DEST (pat)))) |
157371cf AO |
4802 | && ! (TARGET_SH2A |
4803 | && GET_MODE (SET_DEST (pat)) == SImode | |
e990551a JS |
4804 | && (satisfies_constraint_I20 (SET_SRC (pat)) |
4805 | || satisfies_constraint_I28 (SET_SRC (pat)))) | |
32a7ab3d | 4806 | && ! satisfies_constraint_I08 (SET_SRC (pat))) |
aaf701c5 | 4807 | return true; |
e577c183 | 4808 | } |
d3ae8277 | 4809 | |
aaf701c5 | 4810 | return false; |
b9654711 | 4811 | } |
b9654711 | 4812 | |
50fe8924 | 4813 | /* Return true if the specified insn is a mova insn. */ |
aaf701c5 | 4814 | static bool |
6cb7eb41 | 4815 | mova_p (rtx_insn *insn) |
1245df60 | 4816 | { |
f3536097 | 4817 | return (NONJUMP_INSN_P (insn) |
1245df60 R |
4818 | && GET_CODE (PATTERN (insn)) == SET |
4819 | && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC | |
43c05634 AO |
4820 | && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA |
4821 | /* Don't match mova_const. */ | |
4241ecb0 | 4822 | && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF); |
1245df60 R |
4823 | } |
4824 | ||
078c8b08 R |
4825 | /* Fix up a mova from a switch that went out of range. */ |
4826 | static void | |
6cb7eb41 | 4827 | fixup_mova (rtx_insn *mova) |
078c8b08 | 4828 | { |
4241ecb0 | 4829 | PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode); |
078c8b08 R |
4830 | if (! flag_pic) |
4831 | { | |
4241ecb0 | 4832 | SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova); |
078c8b08 R |
4833 | INSN_CODE (mova) = -1; |
4834 | } | |
4835 | else | |
4836 | { | |
b32d5189 | 4837 | rtx_insn *worker = mova; |
19f8b229 | 4838 | rtx_code_label *lab = gen_label_rtx (); |
dc3ba671 | 4839 | rtx wpat, wpat0, wpat1, wsrc, target, base, diff; |
078c8b08 R |
4840 | |
4841 | do | |
4842 | { | |
4843 | worker = NEXT_INSN (worker); | |
f5b9e7c9 | 4844 | gcc_assert (worker |
f3536097 SZ |
4845 | && !LABEL_P (worker) |
4846 | && !JUMP_P (worker)); | |
4847 | } while (NOTE_P (worker) | |
0bf72672 | 4848 | || recog_memoized (worker) != CODE_FOR_casesi_worker_1); |
078c8b08 R |
4849 | wpat = PATTERN (worker); |
4850 | wpat0 = XVECEXP (wpat, 0, 0); | |
4851 | wpat1 = XVECEXP (wpat, 0, 1); | |
4852 | wsrc = SET_SRC (wpat0); | |
4853 | PATTERN (worker) = (gen_casesi_worker_2 | |
4854 | (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1), | |
4855 | XEXP (XVECEXP (wsrc, 0, 2), 0), lab, | |
4856 | XEXP (wpat1, 0))); | |
4857 | INSN_CODE (worker) = -1; | |
dc3ba671 RS |
4858 | target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0); |
4859 | base = gen_rtx_LABEL_REF (Pmode, lab); | |
4860 | diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF); | |
078c8b08 R |
4861 | SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff); |
4862 | INSN_CODE (mova) = -1; | |
4863 | } | |
4864 | } | |
4865 | ||
4241ecb0 R |
4866 | /* NEW_MOVA is a mova we've just encountered while scanning forward. Update |
4867 | *num_mova, and check if the new mova is not nested within the first one. | |
4868 | return 0 if *first_mova was replaced, 1 if new_mova was replaced, | |
4869 | 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */ | |
4870 | static int | |
6cb7eb41 | 4871 | untangle_mova (int *num_mova, rtx_insn **first_mova, rtx_insn *new_mova) |
4241ecb0 | 4872 | { |
c6d56443 KK |
4873 | int n_addr = 0; /* Initialization to shut up spurious warning. */ |
4874 | int f_target, n_target = 0; /* Likewise. */ | |
4241ecb0 R |
4875 | |
4876 | if (optimize) | |
4877 | { | |
77253e56 KK |
4878 | /* If NEW_MOVA has no address yet, it will be handled later. */ |
4879 | if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova)) | |
4880 | return -1; | |
4881 | ||
4241ecb0 R |
4882 | n_addr = INSN_ADDRESSES (INSN_UID (new_mova)); |
4883 | n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0))); | |
4884 | if (n_addr > n_target || n_addr + 1022 < n_target) | |
4885 | { | |
4886 | /* Change the mova into a load. | |
4887 | broken_move will then return true for it. */ | |
4888 | fixup_mova (new_mova); | |
4889 | return 1; | |
4890 | } | |
4891 | } | |
4892 | if (!(*num_mova)++) | |
4893 | { | |
4894 | *first_mova = new_mova; | |
4895 | return 2; | |
4896 | } | |
4897 | if (!optimize | |
4898 | || ((f_target | |
4899 | = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0)))) | |
4900 | >= n_target)) | |
4901 | return -1; | |
4902 | ||
4903 | (*num_mova)--; | |
4904 | if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova)) | |
4905 | > n_target - n_addr) | |
4906 | { | |
4907 | fixup_mova (*first_mova); | |
4908 | return 0; | |
4909 | } | |
4910 | else | |
4911 | { | |
4912 | fixup_mova (new_mova); | |
4913 | return 1; | |
4914 | } | |
4915 | } | |
4916 | ||
8aa2a305 JW |
4917 | /* Find the last barrier from insn FROM which is close enough to hold the |
4918 | constant pool. If we can't find one, then create one near the end of | |
4919 | the range. */ | |
6cb7eb41 DM |
4920 | static rtx_insn * |
4921 | find_barrier (int num_mova, rtx_insn *mova, rtx_insn *from) | |
b9654711 | 4922 | { |
0d7e008e SC |
4923 | int count_si = 0; |
4924 | int count_hi = 0; | |
4925 | int found_hi = 0; | |
4926 | int found_si = 0; | |
33f7f353 JR |
4927 | int hi_align = 2; |
4928 | int si_align = 2; | |
1245df60 | 4929 | int leading_mova = num_mova; |
6cb7eb41 DM |
4930 | rtx_insn *barrier_before_mova = NULL; |
4931 | rtx_insn *found_barrier = NULL; | |
4932 | rtx_insn *good_barrier = NULL; | |
c17f53a8 JW |
4933 | int si_limit; |
4934 | int hi_limit; | |
6cb7eb41 | 4935 | rtx_insn *orig = from; |
b32d5189 | 4936 | rtx_insn *last_got = NULL; |
6cb7eb41 | 4937 | rtx_insn *last_symoff = NULL; |
8aa2a305 JW |
4938 | |
4939 | /* For HImode: range is 510, add 4 because pc counts from address of | |
4940 | second instruction after this one, subtract 2 for the jump instruction | |
3adbde60 JW |
4941 | that we may need to emit before the table, subtract 2 for the instruction |
4942 | that fills the jump delay slot (in very rare cases, reorg will take an | |
4943 | instruction from after the constant pool or will leave the delay slot | |
4944 | empty). This gives 510. | |
8aa2a305 JW |
4945 | For SImode: range is 1020, add 4 because pc counts from address of |
4946 | second instruction after this one, subtract 2 in case pc is 2 byte | |
4947 | aligned, subtract 2 for the jump instruction that we may need to emit | |
3adbde60 JW |
4948 | before the table, subtract 2 for the instruction that fills the jump |
4949 | delay slot. This gives 1018. */ | |
c17f53a8 | 4950 | |
1245df60 | 4951 | /* The branch will always be shortened now that the reference address for |
956d6950 | 4952 | forward branches is the successor address, thus we need no longer make |
1245df60 | 4953 | adjustments to the [sh]i_limit for -O0. */ |
c17f53a8 | 4954 | |
1245df60 R |
4955 | si_limit = 1018; |
4956 | hi_limit = 510; | |
e4fa6b06 | 4957 | |
c17f53a8 | 4958 | while (from && count_si < si_limit && count_hi < hi_limit) |
0d7e008e | 4959 | { |
33f7f353 JR |
4960 | int inc = get_attr_length (from); |
4961 | int new_align = 1; | |
1245df60 | 4962 | |
4241ecb0 R |
4963 | /* If this is a label that existed at the time of the compute_alignments |
4964 | call, determine the alignment. N.B. When find_barrier recurses for | |
4965 | an out-of-reach mova, we might see labels at the start of previously | |
4966 | inserted constant tables. */ | |
f3536097 | 4967 | if (LABEL_P (from) |
4241ecb0 | 4968 | && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg) |
77008a44 R |
4969 | { |
4970 | if (optimize) | |
4971 | new_align = 1 << label_to_alignment (from); | |
f3536097 | 4972 | else if (BARRIER_P (prev_nonnote_insn (from))) |
77008a44 R |
4973 | new_align = 1 << barrier_align (from); |
4974 | else | |
4975 | new_align = 1; | |
4976 | inc = 0; | |
4977 | } | |
4241ecb0 R |
4978 | /* In case we are scanning a constant table because of recursion, check |
4979 | for explicit alignments. If the table is long, we might be forced | |
4980 | to emit the new table in front of it; the length of the alignment | |
4981 | might be the last straw. */ | |
f3536097 | 4982 | else if (NONJUMP_INSN_P (from) |
4241ecb0 R |
4983 | && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE |
4984 | && XINT (PATTERN (from), 1) == UNSPECV_ALIGN) | |
4985 | new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0)); | |
4986 | /* When we find the end of a constant table, paste the new constant | |
4987 | at the end. That is better than putting it in front because | |
4988 | this way, we don't need extra alignment for adding a 4-byte-aligned | |
4989 | mov(a) label to a 2/4 or 8/4 byte aligned table. */ | |
f3536097 | 4990 | else if (NONJUMP_INSN_P (from) |
4241ecb0 R |
4991 | && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE |
4992 | && XINT (PATTERN (from), 1) == UNSPECV_CONST_END) | |
4993 | return from; | |
8aa2a305 | 4994 | |
f3536097 | 4995 | if (BARRIER_P (from)) |
1245df60 | 4996 | { |
6cb7eb41 | 4997 | rtx_insn *next; |
33f7f353 | 4998 | |
1245df60 | 4999 | found_barrier = from; |
33f7f353 | 5000 | |
956d6950 | 5001 | /* If we are at the end of the function, or in front of an alignment |
1245df60 R |
5002 | instruction, we need not insert an extra alignment. We prefer |
5003 | this kind of barrier. */ | |
33f7f353 | 5004 | if (barrier_align (from) > 2) |
1245df60 | 5005 | good_barrier = from; |
6d4d15b8 KK |
5006 | |
5007 | /* If we are at the end of a hot/cold block, dump the constants | |
5008 | here. */ | |
5009 | next = NEXT_INSN (from); | |
5010 | if (next | |
5011 | && NOTE_P (next) | |
5012 | && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS) | |
5013 | break; | |
1245df60 | 5014 | } |
8aa2a305 | 5015 | |
8aa2a305 | 5016 | if (broken_move (from)) |
0d7e008e | 5017 | { |
1245df60 | 5018 | rtx pat, src, dst; |
ef4bddc2 | 5019 | machine_mode mode; |
1245df60 R |
5020 | |
5021 | pat = PATTERN (from); | |
5022 | if (GET_CODE (pat) == PARALLEL) | |
5023 | pat = XVECEXP (pat, 0, 0); | |
5024 | src = SET_SRC (pat); | |
5025 | dst = SET_DEST (pat); | |
5026 | mode = GET_MODE (dst); | |
c17f53a8 | 5027 | |
e938feb4 CB |
5028 | /* GOT pcrelat setting comes in pair of |
5029 | mova .L8,r0 | |
5030 | mov.l .L8,r12 | |
5031 | instructions. (plus add r0,r12). | |
5032 | Remember if we see one without the other. */ | |
50fe8924 | 5033 | if (GET_CODE (src) == UNSPEC && PIC_ADDR_P (XVECEXP (src, 0, 0))) |
b32d5189 | 5034 | last_got = last_got ? NULL : from; |
50fe8924 | 5035 | else if (PIC_ADDR_P (src)) |
b32d5189 | 5036 | last_got = last_got ? NULL : from; |
e938feb4 | 5037 | |
c17f53a8 JW |
5038 | /* We must explicitly check the mode, because sometimes the |
5039 | front end will generate code to load unsigned constants into | |
5040 | HImode targets without properly sign extending them. */ | |
225e4f43 | 5041 | if (mode == HImode |
bdb7ddcc OE |
5042 | || (mode == SImode && satisfies_constraint_I16 (src) |
5043 | && REGNO (dst) != FPUL_REG)) | |
00e94d65 | 5044 | { |
1245df60 | 5045 | found_hi += 2; |
00e94d65 RK |
5046 | /* We put the short constants before the long constants, so |
5047 | we must count the length of short constants in the range | |
5048 | for the long constants. */ | |
5049 | /* ??? This isn't optimal, but is easy to do. */ | |
1245df60 | 5050 | si_limit -= 2; |
00e94d65 | 5051 | } |
0d7e008e | 5052 | else |
1245df60 | 5053 | { |
fa5322fa AO |
5054 | /* We dump DF/DI constants before SF/SI ones, because |
5055 | the limit is the same, but the alignment requirements | |
5056 | are higher. We may waste up to 4 additional bytes | |
5057 | for alignment, and the DF/DI constant may have | |
24746a42 | 5058 | another SF/SI constant placed before it. */ |
33f7f353 JR |
5059 | while (si_align > 2 && found_si + si_align - 2 > count_si) |
5060 | si_align >>= 1; | |
1245df60 R |
5061 | if (found_si > count_si) |
5062 | count_si = found_si; | |
5063 | found_si += GET_MODE_SIZE (mode); | |
5064 | if (num_mova) | |
5065 | si_limit -= GET_MODE_SIZE (mode); | |
5066 | } | |
0d7e008e | 5067 | } |
5325c0fa | 5068 | |
33f7f353 | 5069 | if (mova_p (from)) |
1245df60 | 5070 | { |
4241ecb0 | 5071 | switch (untangle_mova (&num_mova, &mova, from)) |
1245df60 | 5072 | { |
fc9c984d KK |
5073 | case 1: |
5074 | if (flag_pic) | |
5075 | { | |
5076 | rtx src = SET_SRC (PATTERN (from)); | |
5077 | if (GET_CODE (src) == CONST | |
5078 | && GET_CODE (XEXP (src, 0)) == UNSPEC | |
5079 | && XINT (XEXP (src, 0), 1) == UNSPEC_SYMOFF) | |
5080 | last_symoff = from; | |
5081 | } | |
5082 | break; | |
4241ecb0 R |
5083 | case 0: return find_barrier (0, 0, mova); |
5084 | case 2: | |
5085 | { | |
5086 | leading_mova = 0; | |
5087 | barrier_before_mova | |
5088 | = good_barrier ? good_barrier : found_barrier; | |
5089 | } | |
5090 | default: break; | |
1245df60 R |
5091 | } |
5092 | if (found_si > count_si) | |
5093 | count_si = found_si; | |
5094 | } | |
39718607 SB |
5095 | else if (JUMP_TABLE_DATA_P (from) |
5096 | && GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC) | |
1245df60 | 5097 | { |
4241ecb0 R |
5098 | if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode) |
5099 | || (num_mova | |
5100 | && (prev_nonnote_insn (from) | |
5101 | == XEXP (MOVA_LABELREF (mova), 0)))) | |
1245df60 | 5102 | num_mova--; |
10f4f635 | 5103 | if (barrier_align (next_real_insn (from)) == align_jumps_log) |
1245df60 | 5104 | { |
38e01259 | 5105 | /* We have just passed the barrier in front of the |
a0798779 R |
5106 | ADDR_DIFF_VEC, which is stored in found_barrier. Since |
5107 | the ADDR_DIFF_VEC is accessed as data, just like our pool | |
5108 | constants, this is a good opportunity to accommodate what | |
5109 | we have gathered so far. | |
1245df60 R |
5110 | If we waited any longer, we could end up at a barrier in |
5111 | front of code, which gives worse cache usage for separated | |
5112 | instruction / data caches. */ | |
a0798779 | 5113 | good_barrier = found_barrier; |
1245df60 R |
5114 | break; |
5115 | } | |
a0798779 R |
5116 | else |
5117 | { | |
5118 | rtx body = PATTERN (from); | |
5119 | inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body)); | |
5120 | } | |
1245df60 | 5121 | } |
50ceefc2 | 5122 | /* For the SH1, we generate alignments even after jumps-around-jumps. */ |
f3536097 | 5123 | else if (JUMP_P (from) |
50ceefc2 | 5124 | && ! TARGET_SH2 |
3020190e | 5125 | && ! optimize_size) |
50ceefc2 | 5126 | new_align = 4; |
5325c0fa | 5127 | |
9e3c399e CB |
5128 | /* There is a possibility that a bf is transformed into a bf/s by the |
5129 | delay slot scheduler. */ | |
39718607 | 5130 | if (JUMP_P (from) |
9e3c399e | 5131 | && get_attr_type (from) == TYPE_CBRANCH |
83d88a6d | 5132 | && ! sequence_insn_p (from)) |
9e3c399e CB |
5133 | inc += 2; |
5134 | ||
0d7e008e | 5135 | if (found_si) |
33f7f353 | 5136 | { |
50ceefc2 | 5137 | count_si += inc; |
33f7f353 JR |
5138 | if (new_align > si_align) |
5139 | { | |
318881c0 | 5140 | si_limit -= (count_si - 1) & (new_align - si_align); |
33f7f353 JR |
5141 | si_align = new_align; |
5142 | } | |
318881c0 | 5143 | count_si = (count_si + new_align - 1) & -new_align; |
33f7f353 | 5144 | } |
0d7e008e | 5145 | if (found_hi) |
33f7f353 | 5146 | { |
50ceefc2 | 5147 | count_hi += inc; |
33f7f353 JR |
5148 | if (new_align > hi_align) |
5149 | { | |
318881c0 | 5150 | hi_limit -= (count_hi - 1) & (new_align - hi_align); |
33f7f353 JR |
5151 | hi_align = new_align; |
5152 | } | |
318881c0 | 5153 | count_hi = (count_hi + new_align - 1) & -new_align; |
33f7f353 | 5154 | } |
0d7e008e SC |
5155 | from = NEXT_INSN (from); |
5156 | } | |
5157 | ||
1245df60 | 5158 | if (num_mova) |
eda44c78 R |
5159 | { |
5160 | if (leading_mova) | |
5161 | { | |
5162 | /* Try as we might, the leading mova is out of range. Change | |
5163 | it into a load (which will become a pcload) and retry. */ | |
078c8b08 | 5164 | fixup_mova (mova); |
eda44c78 R |
5165 | return find_barrier (0, 0, mova); |
5166 | } | |
5167 | else | |
5168 | { | |
5169 | /* Insert the constant pool table before the mova instruction, | |
5170 | to prevent the mova label reference from going out of range. */ | |
5171 | from = mova; | |
5172 | good_barrier = found_barrier = barrier_before_mova; | |
5173 | } | |
5174 | } | |
5325c0fa | 5175 | |
1245df60 R |
5176 | if (found_barrier) |
5177 | { | |
33f7f353 | 5178 | if (good_barrier && next_real_insn (found_barrier)) |
1245df60 | 5179 | found_barrier = good_barrier; |
1245df60 R |
5180 | } |
5181 | else | |
b9654711 | 5182 | { |
8aa2a305 JW |
5183 | /* We didn't find a barrier in time to dump our stuff, |
5184 | so we'll make one. */ | |
6cb7eb41 | 5185 | rtx_code_label *label = gen_label_rtx (); |
8aa2a305 | 5186 | |
fc9c984d KK |
5187 | /* Don't emit a constant table in the middle of insns for |
5188 | casesi_worker_2. This is a bit overkill but is enough | |
5189 | because casesi_worker_2 wouldn't appear so frequently. */ | |
5190 | if (last_symoff) | |
5191 | from = last_symoff; | |
5192 | ||
5dbcc9c0 RK |
5193 | /* If we exceeded the range, then we must back up over the last |
5194 | instruction we looked at. Otherwise, we just need to undo the | |
5195 | NEXT_INSN at the end of the loop. */ | |
7a3cb3ab KK |
5196 | if (PREV_INSN (from) != orig |
5197 | && (count_hi > hi_limit || count_si > si_limit)) | |
5dbcc9c0 RK |
5198 | from = PREV_INSN (PREV_INSN (from)); |
5199 | else | |
5200 | from = PREV_INSN (from); | |
5201 | ||
e938feb4 CB |
5202 | /* Don't emit a constant table int the middle of global pointer setting, |
5203 | since that that would move the addressing base GOT into another table. | |
5204 | We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_ | |
066922e6 CLT |
5205 | in the pool anyway, so just move up the whole constant pool. |
5206 | ||
5207 | However, avoid doing so when the last single GOT mov is the starting | |
5208 | insn itself. Going past above the start insn would create a negative | |
5209 | offset, causing errors. */ | |
5210 | if (last_got && last_got != orig) | |
e938feb4 CB |
5211 | from = PREV_INSN (last_got); |
5212 | ||
bd55b817 KK |
5213 | /* Don't insert the constant pool table at the position which |
5214 | may be the landing pad. */ | |
5215 | if (flag_exceptions | |
5216 | && CALL_P (from) | |
5217 | && find_reg_note (from, REG_EH_REGION, NULL_RTX)) | |
5218 | from = PREV_INSN (from); | |
5219 | ||
8aa2a305 JW |
5220 | /* Walk back to be just before any jump or label. |
5221 | Putting it before a label reduces the number of times the branch | |
5222 | around the constant pool table will be hit. Putting it before | |
5223 | a jump makes it more likely that the bra delay slot will be | |
5224 | filled. */ | |
f3536097 SZ |
5225 | while (NOTE_P (from) || JUMP_P (from) |
5226 | || LABEL_P (from)) | |
8aa2a305 JW |
5227 | from = PREV_INSN (from); |
5228 | ||
5969b52d KK |
5229 | /* Make sure we do not split between a call and its corresponding |
5230 | CALL_ARG_LOCATION note. */ | |
5231 | if (CALL_P (from)) | |
5232 | { | |
6cb7eb41 | 5233 | rtx_insn *next = NEXT_INSN (from); |
5969b52d KK |
5234 | if (next && NOTE_P (next) |
5235 | && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION) | |
5236 | from = next; | |
5237 | } | |
5238 | ||
0d7e008e SC |
5239 | from = emit_jump_insn_after (gen_jump (label), from); |
5240 | JUMP_LABEL (from) = label; | |
e081ed26 | 5241 | LABEL_NUSES (label) = 1; |
0d7e008e SC |
5242 | found_barrier = emit_barrier_after (from); |
5243 | emit_label_after (label, found_barrier); | |
b9654711 | 5244 | } |
b9654711 | 5245 | |
8aa2a305 | 5246 | return found_barrier; |
0d7e008e | 5247 | } |
b9654711 | 5248 | |
4787bce0 JW |
5249 | /* If the instruction INSN is implemented by a special function, and we can |
5250 | positively find the register that is used to call the sfunc, and this | |
5251 | register is not used anywhere else in this instruction - except as the | |
5252 | destination of a set, return this register; else, return 0. */ | |
1245df60 | 5253 | rtx |
84034c69 | 5254 | sfunc_uses_reg (rtx_insn *insn) |
4787bce0 JW |
5255 | { |
5256 | int i; | |
5257 | rtx pattern, part, reg_part, reg; | |
5258 | ||
f3536097 | 5259 | if (!NONJUMP_INSN_P (insn)) |
23d0939b | 5260 | return NULL_RTX; |
4787bce0 JW |
5261 | pattern = PATTERN (insn); |
5262 | if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC) | |
23d0939b | 5263 | return NULL_RTX; |
4787bce0 | 5264 | |
23d0939b | 5265 | for (reg_part = NULL_RTX, i = XVECLEN (pattern, 0) - 1; i >= 1; i--) |
4787bce0 JW |
5266 | { |
5267 | part = XVECEXP (pattern, 0, i); | |
1245df60 | 5268 | if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode) |
4787bce0 JW |
5269 | reg_part = part; |
5270 | } | |
5271 | if (! reg_part) | |
23d0939b | 5272 | return NULL_RTX; |
4787bce0 | 5273 | reg = XEXP (reg_part, 0); |
df4bacab | 5274 | for (int i = XVECLEN (pattern, 0) - 1; i >= 0; i--) |
4787bce0 JW |
5275 | { |
5276 | part = XVECEXP (pattern, 0, i); | |
225e4f43 | 5277 | if (part == reg_part || GET_CODE (part) == CLOBBER) |
4787bce0 JW |
5278 | continue; |
5279 | if (reg_mentioned_p (reg, ((GET_CODE (part) == SET | |
f3536097 | 5280 | && REG_P (SET_DEST (part))) |
4787bce0 | 5281 | ? SET_SRC (part) : part))) |
23d0939b | 5282 | return NULL_RTX; |
4787bce0 JW |
5283 | } |
5284 | return reg; | |
5285 | } | |
5286 | ||
933c3ba3 JW |
5287 | /* See if the only way in which INSN uses REG is by calling it, or by |
5288 | setting it while calling it. Set *SET to a SET rtx if the register | |
5289 | is set by INSN. */ | |
aaf701c5 | 5290 | static bool |
e8a54173 | 5291 | noncall_uses_reg (rtx reg, rtx_insn *insn, rtx *set) |
933c3ba3 | 5292 | { |
933c3ba3 JW |
5293 | *set = NULL_RTX; |
5294 | ||
df4bacab | 5295 | rtx reg2 = sfunc_uses_reg (insn); |
4787bce0 JW |
5296 | if (reg2 && REGNO (reg2) == REGNO (reg)) |
5297 | { | |
df4bacab | 5298 | rtx pattern = single_set (insn); |
4787bce0 | 5299 | if (pattern |
f3536097 | 5300 | && REG_P (SET_DEST (pattern)) |
4787bce0 JW |
5301 | && REGNO (reg) == REGNO (SET_DEST (pattern))) |
5302 | *set = pattern; | |
aaf701c5 | 5303 | return false; |
4787bce0 | 5304 | } |
f3536097 | 5305 | if (!CALL_P (insn)) |
933c3ba3 JW |
5306 | { |
5307 | /* We don't use rtx_equal_p because we don't care if the mode is | |
5308 | different. */ | |
df4bacab | 5309 | rtx pattern = single_set (insn); |
933c3ba3 | 5310 | if (pattern |
f3536097 | 5311 | && REG_P (SET_DEST (pattern)) |
933c3ba3 JW |
5312 | && REGNO (reg) == REGNO (SET_DEST (pattern))) |
5313 | { | |
4787bce0 JW |
5314 | rtx par, part; |
5315 | int i; | |
5316 | ||
933c3ba3 | 5317 | *set = pattern; |
4787bce0 JW |
5318 | par = PATTERN (insn); |
5319 | if (GET_CODE (par) == PARALLEL) | |
5320 | for (i = XVECLEN (par, 0) - 1; i >= 0; i--) | |
5321 | { | |
5322 | part = XVECEXP (par, 0, i); | |
5323 | if (GET_CODE (part) != SET && reg_mentioned_p (reg, part)) | |
aaf701c5 | 5324 | return true; |
4787bce0 JW |
5325 | } |
5326 | return reg_mentioned_p (reg, SET_SRC (pattern)); | |
933c3ba3 JW |
5327 | } |
5328 | ||
aaf701c5 | 5329 | return true; |
933c3ba3 JW |
5330 | } |
5331 | ||
df4bacab | 5332 | rtx pattern = PATTERN (insn); |
933c3ba3 JW |
5333 | |
5334 | if (GET_CODE (pattern) == PARALLEL) | |
5335 | { | |
df4bacab | 5336 | for (int i = XVECLEN (pattern, 0) - 1; i >= 1; i--) |
933c3ba3 | 5337 | if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i))) |
aaf701c5 | 5338 | return true; |
933c3ba3 JW |
5339 | pattern = XVECEXP (pattern, 0, 0); |
5340 | } | |
5341 | ||
5342 | if (GET_CODE (pattern) == SET) | |
5343 | { | |
5344 | if (reg_mentioned_p (reg, SET_DEST (pattern))) | |
5345 | { | |
5346 | /* We don't use rtx_equal_p, because we don't care if the | |
50fe8924 | 5347 | mode is different. */ |
f3536097 | 5348 | if (!REG_P (SET_DEST (pattern)) |
933c3ba3 | 5349 | || REGNO (reg) != REGNO (SET_DEST (pattern))) |
aaf701c5 | 5350 | return true; |
933c3ba3 JW |
5351 | |
5352 | *set = pattern; | |
5353 | } | |
5354 | ||
5355 | pattern = SET_SRC (pattern); | |
5356 | } | |
5357 | ||
5358 | if (GET_CODE (pattern) != CALL | |
f3536097 | 5359 | || !MEM_P (XEXP (pattern, 0)) |
933c3ba3 | 5360 | || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0))) |
aaf701c5 | 5361 | return true; |
933c3ba3 | 5362 | |
aaf701c5 | 5363 | return false; |
933c3ba3 JW |
5364 | } |
5365 | ||
1245df60 R |
5366 | /* Given a X, a pattern of an insn or a part of it, return a mask of used |
5367 | general registers. Bits 0..15 mean that the respective registers | |
5368 | are used as inputs in the instruction. Bits 16..31 mean that the | |
5369 | registers 0..15, respectively, are used as outputs, or are clobbered. | |
5370 | IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */ | |
5371 | int | |
cf277499 | 5372 | regs_used (rtx x, int is_dest) |
1245df60 R |
5373 | { |
5374 | enum rtx_code code; | |
6f7d635c | 5375 | const char *fmt; |
df4bacab | 5376 | int used = 0; |
1245df60 R |
5377 | |
5378 | if (! x) | |
5379 | return used; | |
5380 | code = GET_CODE (x); | |
5381 | switch (code) | |
5382 | { | |
5383 | case REG: | |
5384 | if (REGNO (x) < 16) | |
a93072ca | 5385 | return (((1 << hard_regno_nregs (0, GET_MODE (x))) - 1) |
1245df60 R |
5386 | << (REGNO (x) + is_dest)); |
5387 | return 0; | |
5388 | case SUBREG: | |
5389 | { | |
5390 | rtx y = SUBREG_REG (x); | |
f676971a | 5391 | |
f3536097 | 5392 | if (!REG_P (y)) |
1245df60 R |
5393 | break; |
5394 | if (REGNO (y) < 16) | |
a93072ca | 5395 | return (((1 << hard_regno_nregs (0, GET_MODE (x))) - 1) |
ddef6bc7 JJ |
5396 | << (REGNO (y) + |
5397 | subreg_regno_offset (REGNO (y), | |
5398 | GET_MODE (y), | |
5399 | SUBREG_BYTE (x), | |
5400 | GET_MODE (x)) + is_dest)); | |
1245df60 R |
5401 | return 0; |
5402 | } | |
5403 | case SET: | |
5404 | return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16); | |
5405 | case RETURN: | |
5406 | /* If there was a return value, it must have been indicated with USE. */ | |
5407 | return 0x00ffff00; | |
5408 | case CLOBBER: | |
5409 | is_dest = 1; | |
5410 | break; | |
5411 | case MEM: | |
5412 | is_dest = 0; | |
5413 | break; | |
5414 | case CALL: | |
5415 | used |= 0x00ff00f0; | |
5416 | break; | |
318881c0 KG |
5417 | default: |
5418 | break; | |
1245df60 R |
5419 | } |
5420 | ||
5421 | fmt = GET_RTX_FORMAT (code); | |
5422 | ||
df4bacab | 5423 | for (int i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
1245df60 R |
5424 | { |
5425 | if (fmt[i] == 'E') | |
5426 | { | |
df4bacab | 5427 | for (int j = XVECLEN (x, i) - 1; j >= 0; j--) |
1245df60 R |
5428 | used |= regs_used (XVECEXP (x, i, j), is_dest); |
5429 | } | |
5430 | else if (fmt[i] == 'e') | |
5431 | used |= regs_used (XEXP (x, i), is_dest); | |
5432 | } | |
5433 | return used; | |
5434 | } | |
5435 | ||
5436 | /* Create an instruction that prevents redirection of a conditional branch | |
956d6950 | 5437 | to the destination of the JUMP with address ADDR. |
1245df60 R |
5438 | If the branch needs to be implemented as an indirect jump, try to find |
5439 | a scratch register for it. | |
5440 | If NEED_BLOCK is 0, don't do anything unless we need a scratch register. | |
5441 | If any preceding insn that doesn't fit into a delay slot is good enough, | |
5442 | pass 1. Pass 2 if a definite blocking insn is needed. | |
5443 | -1 is used internally to avoid deep recursion. | |
5444 | If a blocking instruction is made or recognized, return it. */ | |
b32d5189 DM |
5445 | static rtx_insn * |
5446 | gen_block_redirect (rtx_insn *jump, int addr, int need_block) | |
1245df60 R |
5447 | { |
5448 | int dead = 0; | |
b32d5189 | 5449 | rtx_insn *prev = prev_nonnote_insn (jump); |
1245df60 R |
5450 | |
5451 | /* First, check if we already have an instruction that satisfies our need. */ | |
4654c0cf | 5452 | if (prev && NONJUMP_INSN_P (prev) && ! prev->deleted ()) |
1245df60 R |
5453 | { |
5454 | if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch) | |
5455 | return prev; | |
5456 | if (GET_CODE (PATTERN (prev)) == USE | |
5457 | || GET_CODE (PATTERN (prev)) == CLOBBER | |
5458 | || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES) | |
5459 | prev = jump; | |
5460 | else if ((need_block &= ~1) < 0) | |
5461 | return prev; | |
5462 | else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect) | |
5463 | need_block = 0; | |
5464 | } | |
f9654065 R |
5465 | if (GET_CODE (PATTERN (jump)) == RETURN) |
5466 | { | |
5467 | if (! need_block) | |
5468 | return prev; | |
5469 | /* Reorg even does nasty things with return insns that cause branches | |
5470 | to go out of range - see find_end_label and callers. */ | |
a556fd39 | 5471 | return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump); |
f9654065 | 5472 | } |
1245df60 R |
5473 | /* We can't use JUMP_LABEL here because it might be undefined |
5474 | when not optimizing. */ | |
df4bacab | 5475 | rtx dest = XEXP (SET_SRC (PATTERN (jump)), 0); |
1245df60 R |
5476 | /* If the branch is out of range, try to find a scratch register for it. */ |
5477 | if (optimize | |
11f9ed1a KG |
5478 | && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092 |
5479 | > 4092 + 4098)) | |
1245df60 | 5480 | { |
b32d5189 | 5481 | rtx_insn *scan; |
1245df60 | 5482 | /* Don't look for the stack pointer as a scratch register, |
956d6950 | 5483 | it would cause trouble if an interrupt occurred. */ |
0a2aaacc | 5484 | unsigned attempt = 0x7fff, used; |
1245df60 | 5485 | int jump_left = flag_expensive_optimizations + 1; |
f676971a | 5486 | |
1245df60 R |
5487 | /* It is likely that the most recent eligible instruction is wanted for |
5488 | the delay slot. Therefore, find out which registers it uses, and | |
5489 | try to avoid using them. */ | |
f676971a | 5490 | |
318881c0 | 5491 | for (scan = jump; (scan = PREV_INSN (scan)); ) |
1245df60 | 5492 | { |
4654c0cf | 5493 | if (scan->deleted ()) |
1245df60 | 5494 | continue; |
df4bacab | 5495 | rtx_code code = GET_CODE (scan); |
1245df60 R |
5496 | if (code == CODE_LABEL || code == JUMP_INSN) |
5497 | break; | |
5498 | if (code == INSN | |
5499 | && GET_CODE (PATTERN (scan)) != USE | |
5500 | && GET_CODE (PATTERN (scan)) != CLOBBER | |
5501 | && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES) | |
5502 | { | |
0a2aaacc | 5503 | attempt &= ~regs_used (PATTERN (scan), 0); |
1245df60 R |
5504 | break; |
5505 | } | |
5506 | } | |
b32d5189 | 5507 | for (used = dead = 0, scan = JUMP_LABEL_AS_INSN (jump); |
eda44c78 | 5508 | (scan = NEXT_INSN (scan)); ) |
1245df60 | 5509 | { |
4654c0cf | 5510 | if (scan->deleted ()) |
1245df60 | 5511 | continue; |
df4bacab | 5512 | rtx_code code = GET_CODE (scan); |
ec8e098d | 5513 | if (INSN_P (scan)) |
1245df60 R |
5514 | { |
5515 | used |= regs_used (PATTERN (scan), 0); | |
5516 | if (code == CALL_INSN) | |
5517 | used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0); | |
5518 | dead |= (used >> 16) & ~used; | |
0a2aaacc | 5519 | if (dead & attempt) |
1245df60 | 5520 | { |
0a2aaacc | 5521 | dead &= attempt; |
1245df60 R |
5522 | break; |
5523 | } | |
5524 | if (code == JUMP_INSN) | |
eda44c78 R |
5525 | { |
5526 | if (jump_left-- && simplejump_p (scan)) | |
b32d5189 | 5527 | scan = JUMP_LABEL_AS_INSN (scan); |
eda44c78 R |
5528 | else |
5529 | break; | |
5530 | } | |
1245df60 R |
5531 | } |
5532 | } | |
5533 | /* Mask out the stack pointer again, in case it was | |
5534 | the only 'free' register we have found. */ | |
5535 | dead &= 0x7fff; | |
5536 | } | |
5537 | /* If the immediate destination is still in range, check for possible | |
5538 | threading with a jump beyond the delay slot insn. | |
5539 | Don't check if we are called recursively; the jump has been or will be | |
956d6950 | 5540 | checked in a different invocation then. */ |
f676971a | 5541 | |
1245df60 R |
5542 | else if (optimize && need_block >= 0) |
5543 | { | |
7c9796ed TS |
5544 | rtx_insn *next = next_active_insn (as_a<rtx_insn *> (dest)); |
5545 | next = next_active_insn (next); | |
f3536097 | 5546 | if (next && JUMP_P (next) |
1245df60 | 5547 | && GET_CODE (PATTERN (next)) == SET |
ddf8ec7e | 5548 | && recog_memoized (next) == CODE_FOR_jump_compact) |
1245df60 R |
5549 | { |
5550 | dest = JUMP_LABEL (next); | |
5551 | if (dest | |
11f9ed1a | 5552 | && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092 |
9d98a694 AO |
5553 | > 4092 + 4098)) |
5554 | gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1); | |
1245df60 R |
5555 | } |
5556 | } | |
5557 | ||
5558 | if (dead) | |
5559 | { | |
c5c76735 | 5560 | rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead)); |
1245df60 R |
5561 | |
5562 | /* It would be nice if we could convert the jump into an indirect | |
956d6950 | 5563 | jump / far branch right now, and thus exposing all constituent |
1245df60 R |
5564 | instructions to further optimization. However, reorg uses |
5565 | simplejump_p to determine if there is an unconditional jump where | |
5566 | it should try to schedule instructions from the target of the | |
5567 | branch; simplejump_p fails for indirect jumps even if they have | |
5568 | a JUMP_LABEL. */ | |
b32d5189 DM |
5569 | rtx_insn *insn = emit_insn_before (gen_indirect_jump_scratch |
5570 | (reg, GEN_INT (unspec_bbr_uid++)), | |
5571 | jump); | |
10f4f635 R |
5572 | /* ??? We would like this to have the scope of the jump, but that |
5573 | scope will change when a delay slot insn of an inner scope is added. | |
5574 | Hence, after delay slot scheduling, we'll have to expect | |
5575 | NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and | |
5576 | the jump. */ | |
f676971a | 5577 | |
9d12bc68 | 5578 | INSN_LOCATION (insn) = INSN_LOCATION (jump); |
1245df60 R |
5579 | INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch; |
5580 | return insn; | |
5581 | } | |
5582 | else if (need_block) | |
5583 | /* We can't use JUMP_LABEL here because it might be undefined | |
5584 | when not optimizing. */ | |
5585 | return emit_insn_before (gen_block_branch_redirect | |
826159e5 KK |
5586 | (GEN_INT (unspec_bbr_uid++)), |
5587 | jump); | |
1245df60 R |
5588 | return prev; |
5589 | } | |
5590 | ||
5591 | #define CONDJUMP_MIN -252 | |
5592 | #define CONDJUMP_MAX 262 | |
5593 | struct far_branch | |
5594 | { | |
5595 | /* A label (to be placed) in front of the jump | |
5596 | that jumps to our ultimate destination. */ | |
b32d5189 | 5597 | rtx_insn *near_label; |
1245df60 R |
5598 | /* Where we are going to insert it if we cannot move the jump any farther, |
5599 | or the jump itself if we have picked up an existing jump. */ | |
b32d5189 | 5600 | rtx_insn *insert_place; |
1245df60 | 5601 | /* The ultimate destination. */ |
b32d5189 | 5602 | rtx_insn *far_label; |
1245df60 R |
5603 | struct far_branch *prev; |
5604 | /* If the branch has already been created, its address; | |
5605 | else the address of its first prospective user. */ | |
5606 | int address; | |
5607 | }; | |
5608 | ||
5609 | enum mdep_reorg_phase_e mdep_reorg_phase; | |
df4bacab | 5610 | |
c5b9ef02 | 5611 | static void |
cf277499 | 5612 | gen_far_branch (struct far_branch *bp) |
1245df60 | 5613 | { |
e60365d3 | 5614 | rtx_insn *insn = bp->insert_place; |
1476d1bd | 5615 | rtx_jump_insn *jump; |
19f8b229 | 5616 | rtx_code_label *label = gen_label_rtx (); |
1245df60 R |
5617 | |
5618 | emit_label_after (label, insn); | |
5619 | if (bp->far_label) | |
5620 | { | |
5621 | jump = emit_jump_insn_after (gen_jump (bp->far_label), insn); | |
5622 | LABEL_NUSES (bp->far_label)++; | |
5623 | } | |
5624 | else | |
5625 | jump = emit_jump_insn_after (gen_return (), insn); | |
867ff7ed | 5626 | |
225e4f43 R |
5627 | /* Emit a barrier so that reorg knows that any following instructions |
5628 | are not reachable via a fall-through path. | |
fae778eb | 5629 | But don't do this when not optimizing, since we wouldn't suppress the |
225e4f43 R |
5630 | alignment for the barrier then, and could end up with out-of-range |
5631 | pc-relative loads. */ | |
5632 | if (optimize) | |
5633 | emit_barrier_after (jump); | |
1245df60 | 5634 | emit_label_after (bp->near_label, insn); |
867ff7ed CB |
5635 | |
5636 | if (bp->far_label) | |
5637 | JUMP_LABEL (jump) = bp->far_label; | |
5638 | else | |
5639 | { | |
5640 | rtx pat = PATTERN (jump); | |
5641 | gcc_assert (ANY_RETURN_P (pat)); | |
5642 | JUMP_LABEL (jump) = pat; | |
5643 | } | |
5644 | ||
df4bacab | 5645 | bool ok = invert_jump (as_a <rtx_jump_insn *> (insn), label, 1); |
f5b9e7c9 | 5646 | gcc_assert (ok); |
867ff7ed | 5647 | |
f9654065 R |
5648 | /* If we are branching around a jump (rather than a return), prevent |
5649 | reorg from using an insn from the jump target as the delay slot insn - | |
5650 | when reorg did this, it pessimized code (we rather hide the delay slot) | |
5651 | and it could cause branches to go out of range. */ | |
5652 | if (bp->far_label) | |
5653 | (emit_insn_after | |
5654 | (gen_stuff_delay_slot | |
826159e5 | 5655 | (GEN_INT (unspec_bbr_uid++), |
f9654065 R |
5656 | GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)), |
5657 | insn)); | |
1245df60 R |
5658 | /* Prevent reorg from undoing our splits. */ |
5659 | gen_block_redirect (jump, bp->address += 2, 2); | |
5660 | } | |
5661 | ||
1245df60 R |
5662 | /* Fix up ADDR_DIFF_VECs. */ |
5663 | void | |
b32d5189 | 5664 | fixup_addr_diff_vecs (rtx_insn *first) |
1245df60 | 5665 | { |
b32d5189 | 5666 | rtx_insn *insn; |
33f7f353 | 5667 | |
1245df60 R |
5668 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
5669 | { | |
b32d5189 DM |
5670 | rtx vec_lab, pat, prevpat, x, braf_label; |
5671 | rtx_insn *prev; | |
1245df60 | 5672 | |
34f0d87a | 5673 | if (! JUMP_TABLE_DATA_P (insn) |
1245df60 R |
5674 | || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) |
5675 | continue; | |
5676 | pat = PATTERN (insn); | |
33f7f353 | 5677 | vec_lab = XEXP (XEXP (pat, 0), 0); |
1245df60 | 5678 | |
33f7f353 | 5679 | /* Search the matching casesi_jump_2. */ |
b32d5189 | 5680 | for (prev = as_a <rtx_insn *> (vec_lab); ; prev = PREV_INSN (prev)) |
1245df60 | 5681 | { |
f3536097 | 5682 | if (!JUMP_P (prev)) |
33f7f353 JR |
5683 | continue; |
5684 | prevpat = PATTERN (prev); | |
5685 | if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2) | |
5686 | continue; | |
5687 | x = XVECEXP (prevpat, 0, 1); | |
5688 | if (GET_CODE (x) != USE) | |
5689 | continue; | |
5690 | x = XEXP (x, 0); | |
5691 | if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab) | |
5692 | break; | |
1245df60 | 5693 | } |
157371cf AO |
5694 | /* FIXME: This is a bug in the optimizer, but it seems harmless |
5695 | to just avoid panicing. */ | |
5696 | if (!prev) | |
5697 | continue; | |
eb3881bf R |
5698 | |
5699 | /* Emit the reference label of the braf where it belongs, right after | |
5700 | the casesi_jump_2 (i.e. braf). */ | |
5701 | braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0); | |
5702 | emit_label_after (braf_label, prev); | |
5703 | ||
33f7f353 JR |
5704 | /* Fix up the ADDR_DIF_VEC to be relative |
5705 | to the reference address of the braf. */ | |
eb3881bf | 5706 | XEXP (XEXP (pat, 0), 0) = braf_label; |
1245df60 | 5707 | } |
1245df60 R |
5708 | } |
5709 | ||
33f7f353 JR |
5710 | /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following |
5711 | a barrier. Return the base 2 logarithm of the desired alignment. */ | |
1245df60 | 5712 | int |
b32d5189 | 5713 | barrier_align (rtx_insn *barrier_or_label) |
1245df60 | 5714 | { |
d7be3fcd KK |
5715 | if (! barrier_or_label) |
5716 | return 0; | |
5717 | ||
d7b6661b SB |
5718 | if (LABEL_P (barrier_or_label) |
5719 | && NEXT_INSN (barrier_or_label) | |
5720 | && JUMP_TABLE_DATA_P (NEXT_INSN (barrier_or_label))) | |
33f7f353 | 5721 | return 2; |
1245df60 | 5722 | |
d7b6661b SB |
5723 | if (BARRIER_P (barrier_or_label) |
5724 | && PREV_INSN (barrier_or_label) | |
5725 | && JUMP_TABLE_DATA_P (PREV_INSN (barrier_or_label))) | |
1245df60 | 5726 | { |
df4bacab | 5727 | rtx pat = PATTERN (PREV_INSN (barrier_or_label)); |
33f7f353 JR |
5728 | /* If this is a very small table, we want to keep the alignment after |
5729 | the table to the minimum for proper code alignment. */ | |
3020190e | 5730 | return ((optimize_size |
d042370e | 5731 | || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat)) |
832a3292 | 5732 | <= (unsigned) 1 << (CACHE_LOG - 2))) |
e1fab8ba | 5733 | ? 1 : align_jumps_log); |
1245df60 | 5734 | } |
33f7f353 | 5735 | |
82082f65 | 5736 | rtx_insn *next = next_active_insn (barrier_or_label); |
d7b6661b SB |
5737 | |
5738 | if (! next) | |
5739 | return 0; | |
5740 | ||
df4bacab | 5741 | rtx pat = PATTERN (next); |
d7b6661b SB |
5742 | |
5743 | if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN) | |
5744 | /* This is a barrier in front of a constant table. */ | |
5745 | return 0; | |
5746 | ||
3020190e | 5747 | if (optimize_size) |
33f7f353 JR |
5748 | return 0; |
5749 | ||
4d070fd3 | 5750 | if (! TARGET_SH2 || ! optimize) |
10f4f635 | 5751 | return align_jumps_log; |
33f7f353 | 5752 | |
225e4f43 R |
5753 | /* When fixing up pcloads, a constant table might be inserted just before |
5754 | the basic block that ends with the barrier. Thus, we can't trust the | |
5755 | instruction lengths before that. */ | |
5756 | if (mdep_reorg_phase > SH_FIXUP_PCLOAD) | |
1245df60 | 5757 | { |
225e4f43 R |
5758 | /* Check if there is an immediately preceding branch to the insn beyond |
5759 | the barrier. We must weight the cost of discarding useful information | |
5760 | from the current cache line when executing this branch and there is | |
5761 | an alignment, against that of fetching unneeded insn in front of the | |
5762 | branch target when there is no alignment. */ | |
5763 | ||
f676971a EC |
5764 | /* There are two delay_slot cases to consider. One is the simple case |
5765 | where the preceding branch is to the insn beyond the barrier (simple | |
5766 | delay slot filling), and the other is where the preceding branch has | |
5767 | a delay slot that is a duplicate of the insn after the barrier | |
5768 | (fill_eager_delay_slots) and the branch is to the insn after the insn | |
b1b41fe4 CP |
5769 | after the barrier. */ |
5770 | ||
23d0939b OE |
5771 | int slot, credit; |
5772 | bool jump_to_next = false; | |
5773 | ||
d7b6661b SB |
5774 | /* Skip to the insn before the JUMP_INSN before the barrier under |
5775 | investigation. */ | |
b32d5189 | 5776 | rtx_insn *prev = prev_real_insn (prev_active_insn (barrier_or_label)); |
225e4f43 | 5777 | |
c5b9ef02 | 5778 | for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2; |
f3536097 | 5779 | credit >= 0 && prev && NONJUMP_INSN_P (prev); |
225e4f43 R |
5780 | prev = prev_real_insn (prev)) |
5781 | { | |
23d0939b | 5782 | jump_to_next = false; |
225e4f43 R |
5783 | if (GET_CODE (PATTERN (prev)) == USE |
5784 | || GET_CODE (PATTERN (prev)) == CLOBBER) | |
5785 | continue; | |
b32d5189 | 5786 | if (rtx_sequence *prev_seq = dyn_cast <rtx_sequence *> (PATTERN (prev))) |
b1b41fe4 | 5787 | { |
b32d5189 | 5788 | prev = prev_seq->insn (1); |
f676971a | 5789 | if (INSN_UID (prev) == INSN_UID (next)) |
b1b41fe4 CP |
5790 | { |
5791 | /* Delay slot was filled with insn at jump target. */ | |
23d0939b | 5792 | jump_to_next = true; |
b1b41fe4 CP |
5793 | continue; |
5794 | } | |
5795 | } | |
5796 | ||
225e4f43 R |
5797 | if (slot && |
5798 | get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES) | |
5799 | slot = 0; | |
5800 | credit -= get_attr_length (prev); | |
5801 | } | |
dc0ff1c8 | 5802 | if (prev && jump_to_label_p (prev)) |
2b9d17c7 | 5803 | { |
b32d5189 | 5804 | rtx_insn *x; |
300c5453 | 5805 | if (jump_to_next |
2b9d17c7 | 5806 | || next_real_insn (JUMP_LABEL (prev)) == next |
1594c6bc AO |
5807 | /* If relax_delay_slots() decides NEXT was redundant |
5808 | with some previous instruction, it will have | |
5809 | redirected PREV's jump to the following insn. */ | |
5d291213 | 5810 | || JUMP_LABEL (prev) == next_nonnote_insn (next) |
300c5453 AO |
5811 | /* There is no upper bound on redundant instructions |
5812 | that might have been skipped, but we must not put an | |
2b9d17c7 | 5813 | alignment where none had been before. */ |
f676971a EC |
5814 | || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))), |
5815 | (INSN_P (x) | |
2b9d17c7 | 5816 | && (INSN_CODE (x) == CODE_FOR_block_branch_redirect |
9959c8c7 R |
5817 | || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch |
5818 | || INSN_CODE (x) == CODE_FOR_stuff_delay_slot)))) | |
2b9d17c7 AH |
5819 | { |
5820 | rtx pat = PATTERN (prev); | |
5821 | if (GET_CODE (pat) == PARALLEL) | |
300c5453 | 5822 | pat = XVECEXP (pat, 0, 0); |
2b9d17c7 AH |
5823 | if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0)) |
5824 | return 0; | |
5825 | } | |
300c5453 | 5826 | } |
33f7f353 | 5827 | } |
f676971a | 5828 | |
10f4f635 | 5829 | return align_jumps_log; |
1245df60 R |
5830 | } |
5831 | ||
2148624a R |
5832 | /* If we are inside a phony loop, almost any kind of label can turn up as the |
5833 | first one in the loop. Aligning a braf label causes incorrect switch | |
5834 | destination addresses; we can detect braf labels because they are | |
5835 | followed by a BARRIER. | |
5836 | Applying loop alignment to small constant or switch tables is a waste | |
5837 | of space, so we suppress this too. */ | |
5838 | int | |
647d790d | 5839 | sh_loop_align (rtx_insn *label) |
2148624a | 5840 | { |
647d790d | 5841 | rtx_insn *next = label; |
2148624a | 5842 | |
b6a0df6c OE |
5843 | if (! optimize || optimize_size) |
5844 | return 0; | |
5845 | ||
2148624a R |
5846 | do |
5847 | next = next_nonnote_insn (next); | |
f3536097 | 5848 | while (next && LABEL_P (next)); |
2148624a R |
5849 | |
5850 | if (! next | |
2c3c49de | 5851 | || ! INSN_P (next) |
2148624a R |
5852 | || recog_memoized (next) == CODE_FOR_consttable_2) |
5853 | return 0; | |
fa5322fa | 5854 | |
10f4f635 | 5855 | return align_loops_log; |
2148624a R |
5856 | } |
5857 | ||
18dbd950 | 5858 | /* Do a final pass over the function, just before delayed branch |
933c3ba3 | 5859 | scheduling. */ |
18dbd950 | 5860 | static void |
cf277499 | 5861 | sh_reorg (void) |
0d7e008e | 5862 | { |
6cb7eb41 | 5863 | rtx_insn *first, *insn, *mova = NULL; |
1245df60 | 5864 | int num_mova; |
c5c76735 JL |
5865 | rtx r0_rtx = gen_rtx_REG (Pmode, 0); |
5866 | rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx); | |
8aa2a305 | 5867 | |
18dbd950 | 5868 | first = get_insns (); |
4241ecb0 | 5869 | max_labelno_before_reorg = max_label_num (); |
18dbd950 | 5870 | |
cb51ecd2 AO |
5871 | /* We must split call insns before introducing `mova's. If we're |
5872 | optimizing, they'll have already been split. Otherwise, make | |
5873 | sure we don't split them too late. */ | |
5874 | if (! optimize) | |
6f862f2f | 5875 | split_all_insns_noflow (); |
cb51ecd2 | 5876 | |
933c3ba3 JW |
5877 | /* If relaxing, generate pseudo-ops to associate function calls with |
5878 | the symbols they call. It does no harm to not generate these | |
2eff0b9d | 5879 | pseudo-ops. However, when we can generate them, it enables the |
933c3ba3 JW |
5880 | linker to potentially relax the jsr to a bsr, and eliminate the |
5881 | register load and, possibly, the constant pool entry. */ | |
5882 | ||
1245df60 | 5883 | mdep_reorg_phase = SH_INSERT_USES_LABELS; |
933c3ba3 JW |
5884 | if (TARGET_RELAX) |
5885 | { | |
cf7c4aa6 HPN |
5886 | /* Remove all REG_LABEL_OPERAND notes. We want to use them for our |
5887 | own purposes. This works because none of the remaining passes | |
933c3ba3 JW |
5888 | need to look at them. |
5889 | ||
5890 | ??? But it may break in the future. We should use a machine | |
5891 | dependent REG_NOTE, or some other approach entirely. */ | |
5892 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
5893 | { | |
2c3c49de | 5894 | if (INSN_P (insn)) |
933c3ba3 JW |
5895 | { |
5896 | rtx note; | |
5897 | ||
cf7c4aa6 HPN |
5898 | while ((note = find_reg_note (insn, REG_LABEL_OPERAND, |
5899 | NULL_RTX)) != 0) | |
933c3ba3 JW |
5900 | remove_note (insn, note); |
5901 | } | |
5902 | } | |
5903 | ||
5904 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
5905 | { | |
19f8b229 TS |
5906 | rtx pattern, reg, set, dies; |
5907 | rtx_code_label *label; | |
6cb7eb41 | 5908 | rtx_insn *link, *scan; |
933c3ba3 JW |
5909 | int rescan = 0, foundinsn = 0; |
5910 | ||
f3536097 | 5911 | if (CALL_P (insn)) |
4787bce0 JW |
5912 | { |
5913 | pattern = PATTERN (insn); | |
933c3ba3 | 5914 | |
4787bce0 JW |
5915 | if (GET_CODE (pattern) == PARALLEL) |
5916 | pattern = XVECEXP (pattern, 0, 0); | |
5917 | if (GET_CODE (pattern) == SET) | |
5918 | pattern = SET_SRC (pattern); | |
933c3ba3 | 5919 | |
4787bce0 | 5920 | if (GET_CODE (pattern) != CALL |
f3536097 | 5921 | || !MEM_P (XEXP (pattern, 0))) |
4787bce0 | 5922 | continue; |
933c3ba3 | 5923 | |
4787bce0 JW |
5924 | reg = XEXP (XEXP (pattern, 0), 0); |
5925 | } | |
5926 | else | |
5927 | { | |
5928 | reg = sfunc_uses_reg (insn); | |
5929 | if (! reg) | |
5930 | continue; | |
5931 | } | |
933c3ba3 | 5932 | |
f3536097 | 5933 | if (!REG_P (reg)) |
933c3ba3 JW |
5934 | continue; |
5935 | ||
6fb5fa3c DB |
5936 | /* Try scanning backward to find where the register is set. */ |
5937 | link = NULL; | |
5938 | for (scan = PREV_INSN (insn); | |
f3536097 | 5939 | scan && !LABEL_P (scan); |
6fb5fa3c | 5940 | scan = PREV_INSN (scan)) |
933c3ba3 | 5941 | { |
6fb5fa3c | 5942 | if (! INSN_P (scan)) |
50fe8924 | 5943 | continue; |
933c3ba3 | 5944 | |
6fb5fa3c | 5945 | if (! reg_mentioned_p (reg, scan)) |
50fe8924 | 5946 | continue; |
933c3ba3 | 5947 | |
6fb5fa3c | 5948 | if (noncall_uses_reg (reg, scan, &set)) |
50fe8924 | 5949 | break; |
933c3ba3 | 5950 | |
6fb5fa3c DB |
5951 | if (set) |
5952 | { | |
5953 | link = scan; | |
5954 | break; | |
933c3ba3 JW |
5955 | } |
5956 | } | |
5957 | ||
5958 | if (! link) | |
5959 | continue; | |
5960 | ||
5961 | /* The register is set at LINK. */ | |
5962 | ||
5963 | /* We can only optimize the function call if the register is | |
50fe8924 OE |
5964 | being set to a symbol. In theory, we could sometimes |
5965 | optimize calls to a constant location, but the assembler | |
5966 | and linker do not support that at present. */ | |
933c3ba3 JW |
5967 | if (GET_CODE (SET_SRC (set)) != SYMBOL_REF |
5968 | && GET_CODE (SET_SRC (set)) != LABEL_REF) | |
5969 | continue; | |
5970 | ||
5971 | /* Scan forward from LINK to the place where REG dies, and | |
50fe8924 OE |
5972 | make sure that the only insns which use REG are |
5973 | themselves function calls. */ | |
933c3ba3 | 5974 | |
c1e8e6bd JW |
5975 | /* ??? This doesn't work for call targets that were allocated |
5976 | by reload, since there may not be a REG_DEAD note for the | |
5977 | register. */ | |
5978 | ||
933c3ba3 JW |
5979 | dies = NULL_RTX; |
5980 | for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan)) | |
5981 | { | |
5982 | rtx scanset; | |
5983 | ||
c1e8e6bd JW |
5984 | /* Don't try to trace forward past a CODE_LABEL if we haven't |
5985 | seen INSN yet. Ordinarily, we will only find the setting insn | |
6fb5fa3c | 5986 | if it is in the same basic block. However, |
c1e8e6bd JW |
5987 | cross-jumping can insert code labels in between the load and |
5988 | the call, and can result in situations where a single call | |
5989 | insn may have two targets depending on where we came from. */ | |
5990 | ||
f3536097 | 5991 | if (LABEL_P (scan) && ! foundinsn) |
c1e8e6bd JW |
5992 | break; |
5993 | ||
2c3c49de | 5994 | if (! INSN_P (scan)) |
933c3ba3 JW |
5995 | continue; |
5996 | ||
5997 | /* Don't try to trace forward past a JUMP. To optimize | |
50fe8924 OE |
5998 | safely, we would have to check that all the |
5999 | instructions at the jump destination did not use REG. */ | |
933c3ba3 | 6000 | |
f3536097 | 6001 | if (JUMP_P (scan)) |
933c3ba3 JW |
6002 | break; |
6003 | ||
6004 | if (! reg_mentioned_p (reg, scan)) | |
6005 | continue; | |
6006 | ||
6007 | if (noncall_uses_reg (reg, scan, &scanset)) | |
6008 | break; | |
6009 | ||
6010 | if (scan == insn) | |
6011 | foundinsn = 1; | |
6012 | ||
4787bce0 | 6013 | if (scan != insn |
f3536097 | 6014 | && (CALL_P (scan) || sfunc_uses_reg (scan))) |
933c3ba3 JW |
6015 | { |
6016 | /* There is a function call to this register other | |
50fe8924 OE |
6017 | than the one we are checking. If we optimize |
6018 | this call, we need to rescan again below. */ | |
933c3ba3 JW |
6019 | rescan = 1; |
6020 | } | |
6021 | ||
6022 | /* ??? We shouldn't have to worry about SCANSET here. | |
6023 | We should just be able to check for a REG_DEAD note | |
6024 | on a function call. However, the REG_DEAD notes are | |
6025 | apparently not dependable around libcalls; c-torture | |
6026 | execute/920501-2 is a test case. If SCANSET is set, | |
6027 | then this insn sets the register, so it must have | |
6028 | died earlier. Unfortunately, this will only handle | |
6029 | the cases in which the register is, in fact, set in a | |
6030 | later insn. */ | |
6031 | ||
6032 | /* ??? We shouldn't have to use FOUNDINSN here. | |
6fb5fa3c DB |
6033 | This dates back to when we used LOG_LINKS to find |
6034 | the most recent insn which sets the register. */ | |
933c3ba3 JW |
6035 | |
6036 | if (foundinsn | |
6037 | && (scanset | |
6038 | || find_reg_note (scan, REG_DEAD, reg))) | |
6039 | { | |
6040 | dies = scan; | |
6041 | break; | |
6042 | } | |
6043 | } | |
6044 | ||
6045 | if (! dies) | |
6046 | { | |
6047 | /* Either there was a branch, or some insn used REG | |
50fe8924 | 6048 | other than as a function call address. */ |
933c3ba3 JW |
6049 | continue; |
6050 | } | |
6051 | ||
cf7c4aa6 | 6052 | /* Create a code label, and put it in a REG_LABEL_OPERAND note |
50fe8924 OE |
6053 | on the insn which sets the register, and on each call insn |
6054 | which uses the register. In final_prescan_insn we look for | |
6055 | the REG_LABEL_OPERAND notes, and output the appropriate label | |
6056 | or pseudo-op. */ | |
933c3ba3 JW |
6057 | |
6058 | label = gen_label_rtx (); | |
65c5f2a6 ILT |
6059 | add_reg_note (link, REG_LABEL_OPERAND, label); |
6060 | add_reg_note (insn, REG_LABEL_OPERAND, label); | |
933c3ba3 JW |
6061 | if (rescan) |
6062 | { | |
6063 | scan = link; | |
6064 | do | |
6065 | { | |
4787bce0 JW |
6066 | rtx reg2; |
6067 | ||
933c3ba3 JW |
6068 | scan = NEXT_INSN (scan); |
6069 | if (scan != insn | |
f3536097 | 6070 | && ((CALL_P (scan) |
4787bce0 JW |
6071 | && reg_mentioned_p (reg, scan)) |
6072 | || ((reg2 = sfunc_uses_reg (scan)) | |
6073 | && REGNO (reg2) == REGNO (reg)))) | |
65c5f2a6 | 6074 | add_reg_note (scan, REG_LABEL_OPERAND, label); |
933c3ba3 JW |
6075 | } |
6076 | while (scan != dies); | |
6077 | } | |
6078 | } | |
6079 | } | |
6080 | ||
33f7f353 JR |
6081 | if (TARGET_SH2) |
6082 | fixup_addr_diff_vecs (first); | |
1245df60 R |
6083 | |
6084 | if (optimize) | |
6085 | { | |
1245df60 R |
6086 | mdep_reorg_phase = SH_SHORTEN_BRANCHES0; |
6087 | shorten_branches (first); | |
6088 | } | |
6dd3c0a5 | 6089 | |
933c3ba3 JW |
6090 | /* Scan the function looking for move instructions which have to be |
6091 | changed to pc-relative loads and insert the literal tables. */ | |
1245df60 R |
6092 | mdep_reorg_phase = SH_FIXUP_PCLOAD; |
6093 | for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn)) | |
0d7e008e | 6094 | { |
1245df60 R |
6095 | if (mova_p (insn)) |
6096 | { | |
078c8b08 R |
6097 | /* ??? basic block reordering can move a switch table dispatch |
6098 | below the switch table. Check if that has happened. | |
6099 | We only have the addresses available when optimizing; but then, | |
6100 | this check shouldn't be needed when not optimizing. */ | |
4241ecb0 | 6101 | if (!untangle_mova (&num_mova, &mova, insn)) |
078c8b08 | 6102 | { |
4241ecb0 R |
6103 | insn = mova; |
6104 | num_mova = 0; | |
078c8b08 | 6105 | } |
1245df60 | 6106 | } |
34f0d87a | 6107 | else if (JUMP_TABLE_DATA_P (insn) |
1245df60 | 6108 | && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC |
4241ecb0 R |
6109 | && num_mova |
6110 | /* ??? loop invariant motion can also move a mova out of a | |
6111 | loop. Since loop does this code motion anyway, maybe we | |
6112 | should wrap UNSPEC_MOVA into a CONST, so that reload can | |
6113 | move it back. */ | |
6114 | && ((num_mova > 1 | |
6115 | && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode) | |
6116 | || (prev_nonnote_insn (insn) | |
6117 | == XEXP (MOVA_LABELREF (mova), 0)))) | |
1245df60 | 6118 | { |
b32d5189 | 6119 | rtx_insn *scan; |
1245df60 R |
6120 | int total; |
6121 | ||
6122 | num_mova--; | |
6123 | ||
6124 | /* Some code might have been inserted between the mova and | |
6125 | its ADDR_DIFF_VEC. Check if the mova is still in range. */ | |
6126 | for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan)) | |
33f7f353 | 6127 | total += get_attr_length (scan); |
1245df60 R |
6128 | |
6129 | /* range of mova is 1020, add 4 because pc counts from address of | |
6130 | second instruction after this one, subtract 2 in case pc is 2 | |
6131 | byte aligned. Possible alignment needed for the ADDR_DIFF_VEC | |
956d6950 | 6132 | cancels out with alignment effects of the mova itself. */ |
1245df60 R |
6133 | if (total > 1022) |
6134 | { | |
6135 | /* Change the mova into a load, and restart scanning | |
6136 | there. broken_move will then return true for mova. */ | |
078c8b08 | 6137 | fixup_mova (mova); |
1245df60 R |
6138 | insn = mova; |
6139 | } | |
6140 | } | |
078c8b08 | 6141 | if (broken_move (insn) |
f3536097 | 6142 | || (NONJUMP_INSN_P (insn) |
078c8b08 | 6143 | && recog_memoized (insn) == CODE_FOR_casesi_worker_2)) |
0d7e008e | 6144 | { |
6cb7eb41 | 6145 | rtx_insn *scan; |
8aa2a305 JW |
6146 | /* Scan ahead looking for a barrier to stick the constant table |
6147 | behind. */ | |
6cb7eb41 | 6148 | rtx_insn *barrier = find_barrier (num_mova, mova, insn); |
a5d567ec DM |
6149 | rtx_insn *last_float_move = NULL; |
6150 | rtx last_float = 0, *last_float_addr = NULL; | |
078c8b08 | 6151 | int need_aligned_label = 0; |
b9654711 | 6152 | |
1245df60 R |
6153 | if (num_mova && ! mova_p (mova)) |
6154 | { | |
6155 | /* find_barrier had to change the first mova into a | |
6156 | pcload; thus, we have to start with this new pcload. */ | |
6157 | insn = mova; | |
6158 | num_mova = 0; | |
6159 | } | |
16bea517 | 6160 | /* Now find all the moves between the points and modify them. */ |
0d7e008e SC |
6161 | for (scan = insn; scan != barrier; scan = NEXT_INSN (scan)) |
6162 | { | |
f3536097 | 6163 | if (LABEL_P (scan)) |
1245df60 | 6164 | last_float = 0; |
f3536097 | 6165 | if (NONJUMP_INSN_P (scan) |
078c8b08 R |
6166 | && recog_memoized (scan) == CODE_FOR_casesi_worker_2) |
6167 | need_aligned_label = 1; | |
0d7e008e SC |
6168 | if (broken_move (scan)) |
6169 | { | |
e577c183 JR |
6170 | rtx *patp = &PATTERN (scan), pat = *patp; |
6171 | rtx src, dst; | |
0d7e008e | 6172 | rtx lab; |
0d7e008e | 6173 | rtx newsrc; |
ef4bddc2 | 6174 | machine_mode mode; |
e577c183 JR |
6175 | |
6176 | if (GET_CODE (pat) == PARALLEL) | |
6177 | patp = &XVECEXP (pat, 0, 0), pat = *patp; | |
6178 | src = SET_SRC (pat); | |
6179 | dst = SET_DEST (pat); | |
6180 | mode = GET_MODE (dst); | |
0d7e008e | 6181 | |
bdb7ddcc | 6182 | if (mode == SImode && satisfies_constraint_I16 (src) |
225e4f43 | 6183 | && REGNO (dst) != FPUL_REG) |
0d7e008e | 6184 | { |
23ed92ca | 6185 | int offset = 0; |
8aa2a305 | 6186 | |
0d7e008e | 6187 | mode = HImode; |
d3ae8277 | 6188 | while (GET_CODE (dst) == SUBREG) |
23ed92ca | 6189 | { |
ddef6bc7 JJ |
6190 | offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)), |
6191 | GET_MODE (SUBREG_REG (dst)), | |
6192 | SUBREG_BYTE (dst), | |
6193 | GET_MODE (dst)); | |
23ed92ca JW |
6194 | dst = SUBREG_REG (dst); |
6195 | } | |
c5c76735 | 6196 | dst = gen_rtx_REG (HImode, REGNO (dst) + offset); |
0d7e008e | 6197 | } |
f3536097 | 6198 | if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst))) |
1245df60 | 6199 | { |
b8794099 | 6200 | /* This must be an insn that clobbers r0. */ |
0f2b41b2 AO |
6201 | rtx *clobberp = &XVECEXP (PATTERN (scan), 0, |
6202 | XVECLEN (PATTERN (scan), 0) | |
6203 | - 1); | |
6204 | rtx clobber = *clobberp; | |
b8794099 | 6205 | |
f5b9e7c9 NS |
6206 | gcc_assert (GET_CODE (clobber) == CLOBBER |
6207 | && rtx_equal_p (XEXP (clobber, 0), r0_rtx)); | |
b8794099 | 6208 | |
1245df60 R |
6209 | if (last_float |
6210 | && reg_set_between_p (r0_rtx, last_float_move, scan)) | |
6211 | last_float = 0; | |
6212 | lab = add_constant (src, mode, last_float); | |
6213 | if (lab) | |
6214 | emit_insn_before (gen_mova (lab), scan); | |
6215 | else | |
b8794099 R |
6216 | { |
6217 | /* There will be a REG_UNUSED note for r0 on | |
6218 | LAST_FLOAT_MOVE; we have to change it to REG_INC, | |
6219 | lest reorg:mark_target_live_regs will not | |
6220 | consider r0 to be used, and we end up with delay | |
475f26dd | 6221 | slot insn in front of SCAN that clobbers r0. */ |
b8794099 R |
6222 | rtx note |
6223 | = find_regno_note (last_float_move, REG_UNUSED, 0); | |
6224 | ||
ab1672a3 JW |
6225 | /* If we are not optimizing, then there may not be |
6226 | a note. */ | |
6227 | if (note) | |
81f40b79 | 6228 | PUT_REG_NOTE_KIND (note, REG_INC); |
b8794099 R |
6229 | |
6230 | *last_float_addr = r0_inc_rtx; | |
6231 | } | |
1245df60 R |
6232 | last_float_move = scan; |
6233 | last_float = src; | |
57d38024 | 6234 | newsrc = gen_const_mem (mode, |
318881c0 | 6235 | (((TARGET_SH4 && ! TARGET_FMOVD) |
225e4f43 | 6236 | || REGNO (dst) == FPUL_REG) |
1245df60 R |
6237 | ? r0_inc_rtx |
6238 | : r0_rtx)); | |
6239 | last_float_addr = &XEXP (newsrc, 0); | |
b8794099 R |
6240 | |
6241 | /* Remove the clobber of r0. */ | |
0f2b41b2 AO |
6242 | *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber), |
6243 | gen_rtx_SCRATCH (Pmode)); | |
1245df60 | 6244 | } |
1a66cd67 | 6245 | /* This is a mova needing a label. Create it. */ |
43c05634 AO |
6246 | else if (GET_CODE (src) == UNSPEC |
6247 | && XINT (src, 1) == UNSPEC_MOVA | |
6248 | && GET_CODE (XVECEXP (src, 0, 0)) == CONST) | |
1a66cd67 | 6249 | { |
43c05634 | 6250 | lab = add_constant (XVECEXP (src, 0, 0), mode, 0); |
1a66cd67 | 6251 | newsrc = gen_rtx_LABEL_REF (VOIDmode, lab); |
e69d1422 | 6252 | newsrc = gen_rtx_UNSPEC (SImode, |
4773afa4 AO |
6253 | gen_rtvec (1, newsrc), |
6254 | UNSPEC_MOVA); | |
1a66cd67 | 6255 | } |
8b0a1e0b CB |
6256 | else if (GET_CODE (src) == UNSPEC_VOLATILE |
6257 | && XINT (src, 1) == UNSPECV_SP_SWITCH_B) | |
6258 | { | |
6259 | newsrc = XVECEXP (src, 0, 0); | |
6260 | XVECEXP (src, 0, 0) = gen_const_mem (mode, newsrc); | |
6261 | INSN_CODE (scan) = -1; | |
6262 | continue; | |
6263 | } | |
1245df60 R |
6264 | else |
6265 | { | |
6266 | lab = add_constant (src, mode, 0); | |
542a8afa RH |
6267 | newsrc = gen_rtx_LABEL_REF (VOIDmode, lab); |
6268 | newsrc = gen_const_mem (mode, newsrc); | |
1245df60 | 6269 | } |
f7df4a84 | 6270 | *patp = gen_rtx_SET (dst, newsrc); |
e577c183 | 6271 | INSN_CODE (scan) = -1; |
0d7e008e SC |
6272 | } |
6273 | } | |
078c8b08 | 6274 | dump_table (need_aligned_label ? insn : 0, barrier); |
1245df60 | 6275 | insn = barrier; |
0d7e008e SC |
6276 | } |
6277 | } | |
fb0b2914 | 6278 | label_ref_list_d_pool.release (); |
4241ecb0 R |
6279 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
6280 | PUT_MODE (insn, VOIDmode); | |
6281 | ||
1245df60 | 6282 | mdep_reorg_phase = SH_SHORTEN_BRANCHES1; |
9d98a694 | 6283 | INSN_ADDRESSES_FREE (); |
1245df60 R |
6284 | split_branches (first); |
6285 | ||
6286 | /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it | |
a920aefe | 6287 | also has an effect on the register that holds the address of the sfunc. |
1245df60 R |
6288 | Insert an extra dummy insn in front of each sfunc that pretends to |
6289 | use this register. */ | |
6290 | if (flag_delayed_branch) | |
6291 | { | |
6292 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
6293 | { | |
6294 | rtx reg = sfunc_uses_reg (insn); | |
6295 | ||
6296 | if (! reg) | |
6297 | continue; | |
6298 | emit_insn_before (gen_use_sfunc_addr (reg), insn); | |
6299 | } | |
6300 | } | |
6301 | mdep_reorg_phase = SH_AFTER_MDEP_REORG; | |
6302 | } | |
6303 | ||
50fe8924 | 6304 | /* Return the UID of the insn that follows the specified label. */ |
1245df60 | 6305 | int |
cf277499 | 6306 | get_dest_uid (rtx label, int max_uid) |
1245df60 | 6307 | { |
b32d5189 | 6308 | rtx_insn *dest = next_real_insn (label); |
df4bacab | 6309 | |
1245df60 R |
6310 | if (! dest) |
6311 | /* This can happen for an undefined label. */ | |
6312 | return 0; | |
df4bacab | 6313 | int dest_uid = INSN_UID (dest); |
1245df60 R |
6314 | /* If this is a newly created branch redirection blocking instruction, |
6315 | we cannot index the branch_uid or insn_addresses arrays with its | |
6316 | uid. But then, we won't need to, because the actual destination is | |
6317 | the following branch. */ | |
6318 | while (dest_uid >= max_uid) | |
6319 | { | |
6320 | dest = NEXT_INSN (dest); | |
6321 | dest_uid = INSN_UID (dest); | |
6322 | } | |
f3536097 | 6323 | if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN) |
1245df60 R |
6324 | return 0; |
6325 | return dest_uid; | |
6326 | } | |
6327 | ||
6328 | /* Split condbranches that are out of range. Also add clobbers for | |
6329 | scratch registers that are needed in far jumps. | |
6330 | We do this before delay slot scheduling, so that it can take our | |
6331 | newly created instructions into account. It also allows us to | |
6332 | find branches with common targets more easily. */ | |
1245df60 | 6333 | static void |
6cb7eb41 | 6334 | split_branches (rtx_insn *first) |
1245df60 | 6335 | { |
6cb7eb41 | 6336 | rtx_insn *insn; |
1245df60 R |
6337 | struct far_branch **uid_branch, *far_branch_list = 0; |
6338 | int max_uid = get_max_uid (); | |
f5b9e7c9 | 6339 | int ok; |
1245df60 R |
6340 | |
6341 | /* Find out which branches are out of range. */ | |
1245df60 R |
6342 | shorten_branches (first); |
6343 | ||
6344 | uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch); | |
2e09e75a | 6345 | memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch); |
1245df60 R |
6346 | |
6347 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 6348 | if (! INSN_P (insn)) |
1245df60 | 6349 | continue; |
4654c0cf | 6350 | else if (insn->deleted ()) |
1245df60 R |
6351 | { |
6352 | /* Shorten_branches would split this instruction again, | |
6353 | so transform it into a note. */ | |
a38e7aa5 | 6354 | SET_INSN_DELETED (insn); |
1245df60 | 6355 | } |
39718607 | 6356 | else if (JUMP_P (insn)) |
1245df60 R |
6357 | { |
6358 | enum attr_type type = get_attr_type (insn); | |
6359 | if (type == TYPE_CBRANCH) | |
6360 | { | |
b32d5189 | 6361 | rtx_insn *next, *beyond; |
f676971a | 6362 | |
1245df60 R |
6363 | if (get_attr_length (insn) > 4) |
6364 | { | |
6365 | rtx src = SET_SRC (PATTERN (insn)); | |
1245df60 | 6366 | rtx olabel = XEXP (XEXP (src, 1), 0); |
9d98a694 | 6367 | int addr = INSN_ADDRESSES (INSN_UID (insn)); |
b32d5189 | 6368 | rtx_insn *label = 0; |
1245df60 R |
6369 | int dest_uid = get_dest_uid (olabel, max_uid); |
6370 | struct far_branch *bp = uid_branch[dest_uid]; | |
f676971a | 6371 | |
1245df60 | 6372 | /* redirect_jump needs a valid JUMP_LABEL, and it might delete |
25938114 | 6373 | the label if the LABEL_NUSES count drops to zero. There is |
1245df60 R |
6374 | always a jump_optimize pass that sets these values, but it |
6375 | proceeds to delete unreferenced code, and then if not | |
956d6950 | 6376 | optimizing, to un-delete the deleted instructions, thus |
1245df60 R |
6377 | leaving labels with too low uses counts. */ |
6378 | if (! optimize) | |
6379 | { | |
6380 | JUMP_LABEL (insn) = olabel; | |
6381 | LABEL_NUSES (olabel)++; | |
6382 | } | |
6383 | if (! bp) | |
6384 | { | |
6385 | bp = (struct far_branch *) alloca (sizeof *bp); | |
6386 | uid_branch[dest_uid] = bp; | |
6387 | bp->prev = far_branch_list; | |
6388 | far_branch_list = bp; | |
b32d5189 DM |
6389 | bp->far_label = as_a <rtx_insn *> ( |
6390 | XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), | |
6391 | 0)); | |
1245df60 R |
6392 | LABEL_NUSES (bp->far_label)++; |
6393 | } | |
6394 | else | |
6395 | { | |
6396 | label = bp->near_label; | |
6397 | if (! label && bp->address - addr >= CONDJUMP_MIN) | |
6398 | { | |
b32d5189 | 6399 | rtx_insn *block = bp->insert_place; |
1245df60 R |
6400 | |
6401 | if (GET_CODE (PATTERN (block)) == RETURN) | |
6402 | block = PREV_INSN (block); | |
6403 | else | |
6404 | block = gen_block_redirect (block, | |
6405 | bp->address, 2); | |
6406 | label = emit_label_after (gen_label_rtx (), | |
6407 | PREV_INSN (block)); | |
6408 | bp->near_label = label; | |
6409 | } | |
6410 | else if (label && ! NEXT_INSN (label)) | |
eda44c78 R |
6411 | { |
6412 | if (addr + 2 - bp->address <= CONDJUMP_MAX) | |
6413 | bp->insert_place = insn; | |
6414 | else | |
6415 | gen_far_branch (bp); | |
6416 | } | |
1245df60 R |
6417 | } |
6418 | if (! label | |
318881c0 | 6419 | || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN)) |
1245df60 R |
6420 | { |
6421 | bp->near_label = label = gen_label_rtx (); | |
6422 | bp->insert_place = insn; | |
6423 | bp->address = addr; | |
6424 | } | |
1476d1bd | 6425 | ok = redirect_jump (as_a <rtx_jump_insn *> (insn), label, 0); |
f5b9e7c9 | 6426 | gcc_assert (ok); |
1245df60 R |
6427 | } |
6428 | else | |
6429 | { | |
6430 | /* get_attr_length (insn) == 2 */ | |
6431 | /* Check if we have a pattern where reorg wants to redirect | |
6432 | the branch to a label from an unconditional branch that | |
6433 | is too far away. */ | |
6434 | /* We can't use JUMP_LABEL here because it might be undefined | |
6435 | when not optimizing. */ | |
33f7f353 | 6436 | /* A syntax error might cause beyond to be NULL_RTX. */ |
7c9796ed TS |
6437 | rtx temp = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0); |
6438 | beyond = next_active_insn (as_a<rtx_insn *> (temp)); | |
f676971a | 6439 | |
33f7f353 | 6440 | if (beyond |
f3536097 | 6441 | && (JUMP_P (beyond) |
b94544e4 | 6442 | || ((beyond = next_active_insn (beyond)) |
f3536097 | 6443 | && JUMP_P (beyond))) |
1245df60 | 6444 | && GET_CODE (PATTERN (beyond)) == SET |
ddf8ec7e | 6445 | && recog_memoized (beyond) == CODE_FOR_jump_compact |
9d98a694 AO |
6446 | && ((INSN_ADDRESSES |
6447 | (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0))) | |
11f9ed1a | 6448 | - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252) |
1245df60 R |
6449 | > 252 + 258 + 2)) |
6450 | gen_block_redirect (beyond, | |
9d98a694 | 6451 | INSN_ADDRESSES (INSN_UID (beyond)), 1); |
1245df60 | 6452 | } |
f676971a | 6453 | |
1245df60 R |
6454 | next = next_active_insn (insn); |
6455 | ||
a7d6f306 KK |
6456 | if (next |
6457 | && (JUMP_P (next) | |
6458 | || ((next = next_active_insn (next)) | |
6459 | && JUMP_P (next))) | |
1245df60 | 6460 | && GET_CODE (PATTERN (next)) == SET |
ddf8ec7e | 6461 | && recog_memoized (next) == CODE_FOR_jump_compact |
9d98a694 AO |
6462 | && ((INSN_ADDRESSES |
6463 | (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0))) | |
11f9ed1a | 6464 | - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252) |
1245df60 | 6465 | > 252 + 258 + 2)) |
9d98a694 | 6466 | gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1); |
1245df60 R |
6467 | } |
6468 | else if (type == TYPE_JUMP || type == TYPE_RETURN) | |
6469 | { | |
9d98a694 | 6470 | int addr = INSN_ADDRESSES (INSN_UID (insn)); |
b32d5189 | 6471 | rtx_insn *far_label = 0; |
1245df60 R |
6472 | int dest_uid = 0; |
6473 | struct far_branch *bp; | |
6474 | ||
6475 | if (type == TYPE_JUMP) | |
6476 | { | |
4e417af3 KK |
6477 | if (CROSSING_JUMP_P (insn)) |
6478 | { | |
6479 | emit_insn_before (gen_block_branch_redirect (const0_rtx), | |
6480 | insn); | |
6481 | continue; | |
6482 | } | |
6483 | ||
b32d5189 DM |
6484 | far_label = as_a <rtx_insn *> ( |
6485 | XEXP (SET_SRC (PATTERN (insn)), 0)); | |
1245df60 R |
6486 | dest_uid = get_dest_uid (far_label, max_uid); |
6487 | if (! dest_uid) | |
6488 | { | |
6489 | /* Parse errors can lead to labels outside | |
6490 | the insn stream. */ | |
6491 | if (! NEXT_INSN (far_label)) | |
6492 | continue; | |
6493 | ||
6494 | if (! optimize) | |
6495 | { | |
6496 | JUMP_LABEL (insn) = far_label; | |
6497 | LABEL_NUSES (far_label)++; | |
6498 | } | |
1476d1bd | 6499 | redirect_jump (as_a <rtx_jump_insn *> (insn), ret_rtx, 1); |
1245df60 R |
6500 | far_label = 0; |
6501 | } | |
6502 | } | |
6503 | bp = uid_branch[dest_uid]; | |
6504 | if (! bp) | |
6505 | { | |
6506 | bp = (struct far_branch *) alloca (sizeof *bp); | |
6507 | uid_branch[dest_uid] = bp; | |
6508 | bp->prev = far_branch_list; | |
6509 | far_branch_list = bp; | |
6510 | bp->near_label = 0; | |
6511 | bp->far_label = far_label; | |
6512 | if (far_label) | |
6513 | LABEL_NUSES (far_label)++; | |
6514 | } | |
6515 | else if (bp->near_label && ! NEXT_INSN (bp->near_label)) | |
6516 | if (addr - bp->address <= CONDJUMP_MAX) | |
6517 | emit_label_after (bp->near_label, PREV_INSN (insn)); | |
6518 | else | |
6519 | { | |
6520 | gen_far_branch (bp); | |
6521 | bp->near_label = 0; | |
6522 | } | |
6523 | else | |
6524 | bp->near_label = 0; | |
6525 | bp->address = addr; | |
6526 | bp->insert_place = insn; | |
6527 | if (! far_label) | |
6528 | emit_insn_before (gen_block_branch_redirect (const0_rtx), insn); | |
6529 | else | |
6530 | gen_block_redirect (insn, addr, bp->near_label ? 2 : 0); | |
6531 | } | |
6532 | } | |
6533 | /* Generate all pending far branches, | |
6534 | and free our references to the far labels. */ | |
6535 | while (far_branch_list) | |
6536 | { | |
6537 | if (far_branch_list->near_label | |
6538 | && ! NEXT_INSN (far_branch_list->near_label)) | |
6539 | gen_far_branch (far_branch_list); | |
6540 | if (optimize | |
6541 | && far_branch_list->far_label | |
6542 | && ! --LABEL_NUSES (far_branch_list->far_label)) | |
6543 | delete_insn (far_branch_list->far_label); | |
6544 | far_branch_list = far_branch_list->prev; | |
6545 | } | |
a0798779 R |
6546 | |
6547 | /* Instruction length information is no longer valid due to the new | |
6548 | instructions that have been generated. */ | |
6549 | init_insn_lengths (); | |
b9654711 SC |
6550 | } |
6551 | ||
8aa2a305 | 6552 | /* Dump out instruction addresses, which is useful for debugging the |
933c3ba3 JW |
6553 | constant pool table stuff. |
6554 | ||
6555 | If relaxing, output the label and pseudo-ops used to link together | |
50fe8924 | 6556 | calls and the instruction which set the registers. |
8aa2a305 | 6557 | |
50fe8924 | 6558 | ??? The addresses printed by this routine for insns are nonsense for |
8aa2a305 JW |
6559 | insns which are inside of a sequence where none of the inner insns have |
6560 | variable length. This is because the second pass of shorten_branches | |
6561 | does not bother to update them. */ | |
8e87e161 | 6562 | void |
6cb7eb41 | 6563 | final_prescan_insn (rtx_insn *insn, rtx *opvec ATTRIBUTE_UNUSED, |
cf277499 | 6564 | int noperands ATTRIBUTE_UNUSED) |
b9654711 | 6565 | { |
8aa2a305 | 6566 | if (TARGET_DUMPISIZE) |
9d98a694 | 6567 | fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn))); |
933c3ba3 JW |
6568 | |
6569 | if (TARGET_RELAX) | |
6570 | { | |
df4bacab | 6571 | if (rtx note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX)) |
933c3ba3 | 6572 | { |
df4bacab | 6573 | rtx pattern = PATTERN (insn); |
4b7d2f07 R |
6574 | if (GET_CODE (pattern) == PARALLEL) |
6575 | pattern = XVECEXP (pattern, 0, 0); | |
f5b9e7c9 NS |
6576 | switch (GET_CODE (pattern)) |
6577 | { | |
f5b9e7c9 NS |
6578 | case SET: |
6579 | if (GET_CODE (SET_SRC (pattern)) != CALL | |
6580 | && get_attr_type (insn) != TYPE_SFUNC) | |
6581 | { | |
6582 | targetm.asm_out.internal_label | |
6583 | (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0))); | |
6584 | break; | |
6585 | } | |
be594fbc | 6586 | /* FALLTHROUGH */ |
f5b9e7c9 NS |
6587 | case CALL: |
6588 | asm_fprintf (asm_out_file, "\t.uses %LL%d\n", | |
6589 | CODE_LABEL_NUMBER (XEXP (note, 0))); | |
6590 | break; | |
6591 | ||
6592 | default: | |
6593 | gcc_unreachable (); | |
6594 | } | |
933c3ba3 JW |
6595 | } |
6596 | } | |
0d7e008e | 6597 | } |
b9654711 | 6598 | |
8aa2a305 | 6599 | /* Dump out any constants accumulated in the final pass. These will |
38e01259 | 6600 | only be labels. */ |
318881c0 | 6601 | const char * |
cf277499 | 6602 | output_jump_label_table (void) |
0d7e008e | 6603 | { |
8aa2a305 JW |
6604 | if (pool_size) |
6605 | { | |
6606 | fprintf (asm_out_file, "\t.align 2\n"); | |
df4bacab | 6607 | for (int i = 0; i < pool_size; i++) |
8aa2a305 JW |
6608 | { |
6609 | pool_node *p = &pool_vector[i]; | |
6610 | ||
4977bab6 | 6611 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
8aa2a305 JW |
6612 | CODE_LABEL_NUMBER (p->label)); |
6613 | output_asm_insn (".long %O0", &p->value); | |
6614 | } | |
6615 | pool_size = 0; | |
6616 | } | |
b9654711 | 6617 | |
8aa2a305 JW |
6618 | return ""; |
6619 | } | |
6620 | \f | |
6621 | /* A full frame looks like: | |
16bea517 JW |
6622 | |
6623 | arg-5 | |
6624 | arg-4 | |
6625 | [ if current_function_anonymous_args | |
6626 | arg-3 | |
6627 | arg-2 | |
6628 | arg-1 | |
6629 | arg-0 ] | |
6630 | saved-fp | |
6631 | saved-r10 | |
6632 | saved-r11 | |
6633 | saved-r12 | |
6634 | saved-pr | |
6635 | local-n | |
6636 | .. | |
6637 | local-1 | |
50fe8924 | 6638 | local-0 <- fp points here. |
8e87e161 | 6639 | |
50fe8924 OE |
6640 | Number of bytes pushed for anonymous args, used to pass information |
6641 | between expand_prologue and expand_epilogue. | |
8aa2a305 | 6642 | |
50fe8924 | 6643 | Adjust the stack by SIZE bytes. REG holds the rtl of the register to be |
fada1961 | 6644 | adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's |
726d4cb7 KK |
6645 | for an epilogue and a negative value means that it's for a sibcall |
6646 | epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of | |
6647 | all the registers that are about to be restored, and hence dead. */ | |
8aa2a305 | 6648 | static void |
fada1961 | 6649 | output_stack_adjust (int size, rtx reg, int epilogue_p, |
21d05694 | 6650 | HARD_REG_SET *live_regs_mask, bool frame_p) |
8aa2a305 | 6651 | { |
df4bacab | 6652 | rtx_insn *(*emit_fn) (rtx) = frame_p ? &emit_frame_insn : &emit_insn; |
8aa2a305 JW |
6653 | if (size) |
6654 | { | |
fa5322fa AO |
6655 | HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT; |
6656 | ||
157371cf AO |
6657 | /* This test is bogus, as output_stack_adjust is used to re-align the |
6658 | stack. */ | |
6659 | #if 0 | |
f5b9e7c9 | 6660 | gcc_assert (!(size % align)); |
157371cf | 6661 | #endif |
fa5322fa AO |
6662 | |
6663 | if (CONST_OK_FOR_ADD (size)) | |
2754d3c5 | 6664 | emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size))); |
f3cd5375 JW |
6665 | /* Try to do it with two partial adjustments; however, we must make |
6666 | sure that the stack is properly aligned at all times, in case | |
6f317ef3 | 6667 | an interrupt occurs between the two partial adjustments. */ |
fa5322fa AO |
6668 | else if (CONST_OK_FOR_ADD (size / 2 & -align) |
6669 | && CONST_OK_FOR_ADD (size - (size / 2 & -align))) | |
f3cd5375 | 6670 | { |
2754d3c5 R |
6671 | emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align))); |
6672 | emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align)))); | |
f3cd5375 JW |
6673 | } |
6674 | else | |
8aa2a305 | 6675 | { |
f3cd5375 | 6676 | rtx const_reg; |
2754d3c5 | 6677 | rtx insn; |
e1fab8ba | 6678 | int temp = epilogue_p ? 7 : 1; |
fada1961 | 6679 | int i; |
f3cd5375 JW |
6680 | |
6681 | /* If TEMP is invalid, we could temporarily save a general | |
6682 | register to MACL. However, there is currently no need | |
f5b9e7c9 | 6683 | to handle this case, so just die when we see it. */ |
726d4cb7 KK |
6684 | if (epilogue_p < 0 |
6685 | || current_function_interrupt | |
62164eb4 | 6686 | || ! call_really_used_regs[temp] || fixed_regs[temp]) |
fada1961 | 6687 | temp = -1; |
e1fab8ba | 6688 | if (temp < 0 && ! current_function_interrupt && epilogue_p >= 0) |
fada1961 R |
6689 | { |
6690 | HARD_REG_SET temps; | |
6691 | COPY_HARD_REG_SET (temps, call_used_reg_set); | |
6692 | AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set); | |
726d4cb7 | 6693 | if (epilogue_p > 0) |
fada1961 | 6694 | { |
726d4cb7 | 6695 | int nreg = 0; |
38173d38 | 6696 | if (crtl->return_rtx) |
726d4cb7 | 6697 | { |
ef4bddc2 | 6698 | machine_mode mode; |
38173d38 | 6699 | mode = GET_MODE (crtl->return_rtx); |
726d4cb7 | 6700 | if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG) |
a93072ca | 6701 | nreg = hard_regno_nregs (FIRST_RET_REG, mode); |
726d4cb7 KK |
6702 | } |
6703 | for (i = 0; i < nreg; i++) | |
fada1961 | 6704 | CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i); |
e3b5732b | 6705 | if (crtl->calls_eh_return) |
fada1961 R |
6706 | { |
6707 | CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO); | |
6708 | for (i = 0; i <= 3; i++) | |
6709 | CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i)); | |
6710 | } | |
6711 | } | |
726d4cb7 | 6712 | if (epilogue_p <= 0) |
fada1961 R |
6713 | { |
6714 | for (i = FIRST_PARM_REG; | |
6715 | i < FIRST_PARM_REG + NPARM_REGS (SImode); i++) | |
6716 | CLEAR_HARD_REG_BIT (temps, i); | |
6de9cd9a | 6717 | if (cfun->static_chain_decl != NULL) |
fada1961 R |
6718 | CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM); |
6719 | } | |
6720 | temp = scavenge_reg (&temps); | |
6721 | } | |
6722 | if (temp < 0 && live_regs_mask) | |
eb996a4a KK |
6723 | { |
6724 | HARD_REG_SET temps; | |
6725 | ||
6726 | COPY_HARD_REG_SET (temps, *live_regs_mask); | |
6727 | CLEAR_HARD_REG_BIT (temps, REGNO (reg)); | |
6728 | temp = scavenge_reg (&temps); | |
6729 | } | |
f3cd5375 | 6730 | if (temp < 0) |
726d4cb7 | 6731 | { |
f5b9e7c9 NS |
6732 | rtx adj_reg, tmp_reg, mem; |
6733 | ||
726d4cb7 | 6734 | /* If we reached here, the most likely case is the (sibcall) |
af952763 OE |
6735 | epilogue. Put a special push/pop sequence for such case as |
6736 | the last resort. This looks lengthy but would not be problem | |
6737 | because it seems to be very rare. */ | |
e1fab8ba | 6738 | gcc_assert (epilogue_p); |
f5b9e7c9 | 6739 | |
af952763 | 6740 | /* ??? There is still the slight possibility that r4 or |
f5b9e7c9 NS |
6741 | r5 have been reserved as fixed registers or assigned |
6742 | as global registers, and they change during an | |
6743 | interrupt. There are possible ways to handle this: | |
6744 | ||
6745 | - If we are adjusting the frame pointer (r14), we can do | |
6746 | with a single temp register and an ordinary push / pop | |
6747 | on the stack. | |
6748 | - Grab any call-used or call-saved registers (i.e. not | |
6749 | fixed or globals) for the temps we need. We might | |
6750 | also grab r14 if we are adjusting the stack pointer. | |
6751 | If we can't find enough available registers, issue | |
6752 | a diagnostic and die - the user must have reserved | |
6753 | way too many registers. | |
6754 | But since all this is rather unlikely to happen and | |
6755 | would require extra testing, we just die if r4 / r5 | |
6756 | are not available. */ | |
6757 | gcc_assert (!fixed_regs[4] && !fixed_regs[5] | |
6758 | && !global_regs[4] && !global_regs[5]); | |
6759 | ||
6760 | adj_reg = gen_rtx_REG (GET_MODE (reg), 4); | |
6761 | tmp_reg = gen_rtx_REG (GET_MODE (reg), 5); | |
57d38024 | 6762 | emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg); |
f5b9e7c9 NS |
6763 | emit_insn (GEN_MOV (adj_reg, GEN_INT (size))); |
6764 | emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg)); | |
57d38024 | 6765 | mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg)); |
f5b9e7c9 | 6766 | emit_move_insn (mem, tmp_reg); |
57d38024 R |
6767 | emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg)); |
6768 | mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg)); | |
6769 | emit_move_insn (mem, tmp_reg); | |
6770 | emit_move_insn (reg, adj_reg); | |
6771 | mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg)); | |
6772 | emit_move_insn (adj_reg, mem); | |
6773 | mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg)); | |
6774 | emit_move_insn (tmp_reg, mem); | |
eb996a4a | 6775 | /* Tell flow the insns that pop r4/r5 aren't dead. */ |
c41c1387 RS |
6776 | emit_use (tmp_reg); |
6777 | emit_use (adj_reg); | |
57d38024 | 6778 | return; |
726d4cb7 | 6779 | } |
fa5322fa | 6780 | const_reg = gen_rtx_REG (GET_MODE (reg), temp); |
f3cd5375 JW |
6781 | |
6782 | /* If SIZE is negative, subtract the positive value. | |
6783 | This sometimes allows a constant pool entry to be shared | |
6784 | between prologue and epilogue code. */ | |
6785 | if (size < 0) | |
885c9a39 | 6786 | { |
fa5322fa | 6787 | emit_insn (GEN_MOV (const_reg, GEN_INT (-size))); |
2754d3c5 | 6788 | insn = emit_fn (GEN_SUB3 (reg, reg, const_reg)); |
885c9a39 JR |
6789 | } |
6790 | else | |
6791 | { | |
fa5322fa | 6792 | emit_insn (GEN_MOV (const_reg, GEN_INT (size))); |
2754d3c5 | 6793 | insn = emit_fn (GEN_ADD3 (reg, reg, const_reg)); |
885c9a39 | 6794 | } |
2b8088e7 | 6795 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
f7df4a84 RS |
6796 | gen_rtx_SET (reg, gen_rtx_PLUS (SImode, reg, |
6797 | GEN_INT (size)))); | |
8aa2a305 | 6798 | } |
8aa2a305 JW |
6799 | } |
6800 | } | |
6801 | ||
df4bacab | 6802 | /* Emit the specified insn and mark it as frame related. */ |
cd459bf8 | 6803 | static rtx_insn * |
df4bacab | 6804 | emit_frame_insn (rtx x) |
2754d3c5 | 6805 | { |
cd459bf8 DM |
6806 | rtx_insn *insn = emit_insn (x); |
6807 | RTX_FRAME_RELATED_P (insn) = 1; | |
6808 | return insn; | |
2754d3c5 R |
6809 | } |
6810 | ||
8aa2a305 | 6811 | /* Output RTL to push register RN onto the stack. */ |
2754d3c5 | 6812 | static rtx |
cf277499 | 6813 | push (int rn) |
8aa2a305 JW |
6814 | { |
6815 | rtx x; | |
225e4f43 R |
6816 | if (rn == FPUL_REG) |
6817 | x = gen_push_fpul (); | |
7144b2d8 DD |
6818 | else if (rn == FPSCR_REG) |
6819 | x = gen_push_fpscr (); | |
d5dd0a62 | 6820 | else if (TARGET_FPU_DOUBLE && TARGET_FMOVD |
50fe8924 | 6821 | && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P (rn)) |
225e4f43 | 6822 | { |
104ee20b | 6823 | if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1) |
d042370e | 6824 | return NULL_RTX; |
c5c76735 | 6825 | x = gen_push_4 (gen_rtx_REG (DFmode, rn)); |
225e4f43 | 6826 | } |
3a8699c7 | 6827 | else if (TARGET_SH2E && FP_REGISTER_P (rn)) |
c5c76735 | 6828 | x = gen_push_e (gen_rtx_REG (SFmode, rn)); |
1a95a963 | 6829 | else |
c5c76735 | 6830 | x = gen_push (gen_rtx_REG (SImode, rn)); |
1a95a963 | 6831 | |
df4bacab | 6832 | x = emit_frame_insn (x); |
b757d36f | 6833 | add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM)); |
2754d3c5 | 6834 | return x; |
8aa2a305 JW |
6835 | } |
6836 | ||
6837 | /* Output RTL to pop register RN from the stack. */ | |
8aa2a305 | 6838 | static void |
cf277499 | 6839 | pop (int rn) |
8aa2a305 | 6840 | { |
2b8088e7 | 6841 | rtx x, sp_reg, reg; |
225e4f43 R |
6842 | if (rn == FPUL_REG) |
6843 | x = gen_pop_fpul (); | |
7144b2d8 DD |
6844 | else if (rn == FPSCR_REG) |
6845 | x = gen_pop_fpscr (); | |
d5dd0a62 | 6846 | else if (TARGET_FPU_DOUBLE && TARGET_FMOVD |
50fe8924 | 6847 | && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P (rn)) |
225e4f43 | 6848 | { |
104ee20b | 6849 | if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1) |
225e4f43 | 6850 | return; |
c5c76735 | 6851 | x = gen_pop_4 (gen_rtx_REG (DFmode, rn)); |
225e4f43 | 6852 | } |
3a8699c7 | 6853 | else if (TARGET_SH2E && FP_REGISTER_P (rn)) |
c5c76735 | 6854 | x = gen_pop_e (gen_rtx_REG (SFmode, rn)); |
1a95a963 | 6855 | else |
c5c76735 | 6856 | x = gen_pop (gen_rtx_REG (SImode, rn)); |
f676971a | 6857 | |
1245df60 | 6858 | x = emit_insn (x); |
2b8088e7 CLT |
6859 | |
6860 | sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM); | |
6861 | reg = copy_rtx (GET_CODE (PATTERN (x)) == PARALLEL | |
6862 | ? SET_DEST (XVECEXP (PATTERN (x), 0, 0)) | |
6863 | : SET_DEST (PATTERN (x))); | |
6864 | add_reg_note (x, REG_CFA_RESTORE, reg); | |
6865 | add_reg_note (x, REG_CFA_ADJUST_CFA, | |
f7df4a84 | 6866 | gen_rtx_SET (sp_reg, |
2b8088e7 CLT |
6867 | plus_constant (SImode, sp_reg, |
6868 | GET_MODE_SIZE (GET_MODE (reg))))); | |
b757d36f | 6869 | add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM)); |
2b8088e7 | 6870 | RTX_FRAME_RELATED_P (x) = 1; |
8aa2a305 JW |
6871 | } |
6872 | ||
1245df60 | 6873 | /* Generate code to push the regs specified in the mask. */ |
8aa2a305 | 6874 | static void |
df4bacab | 6875 | push_regs (HARD_REG_SET *mask, bool interrupt_handler) |
8aa2a305 | 6876 | { |
df4bacab | 6877 | bool skip_fpscr = false; |
8aa2a305 | 6878 | |
1245df60 R |
6879 | /* Push PR last; this gives better latencies after the prologue, and |
6880 | candidates for the return delay slot when there are no general | |
6881 | registers pushed. */ | |
df4bacab OE |
6882 | for (int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0; |
6883 | i < FIRST_PSEUDO_REGISTER; i++) | |
ac55736a R |
6884 | { |
6885 | /* If this is an interrupt handler, and the SZ bit varies, | |
6886 | and we have to push any floating point register, we need | |
6887 | to switch to the correct precision first. */ | |
6888 | if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD | |
56b138ae | 6889 | && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS])) |
ac55736a R |
6890 | { |
6891 | HARD_REG_SET unsaved; | |
6892 | ||
6893 | push (FPSCR_REG); | |
832a3292 | 6894 | COMPL_HARD_REG_SET (unsaved, *mask); |
ac55736a | 6895 | fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved); |
df4bacab | 6896 | skip_fpscr = true; |
ac55736a R |
6897 | } |
6898 | if (i != PR_REG | |
6899 | && (i != FPSCR_REG || ! skip_fpscr) | |
6900 | && TEST_HARD_REG_BIT (*mask, i)) | |
50fe8924 OE |
6901 | { |
6902 | /* If the ISR has RESBANK attribute assigned, don't push any of | |
6903 | the following registers - R0-R14, MACH, MACL and GBR. */ | |
561642fa AP |
6904 | if (! (sh_cfun_resbank_handler_p () |
6905 | && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG) | |
6906 | || i == MACH_REG | |
6907 | || i == MACL_REG | |
6908 | || i == GBR_REG))) | |
6909 | push (i); | |
50fe8924 | 6910 | } |
ac55736a | 6911 | } |
5c7cafa8 CB |
6912 | |
6913 | /* Push banked registers last to improve delay slot opportunities. */ | |
6914 | if (interrupt_handler) | |
91a19652 N |
6915 | { |
6916 | bool use_movml = false; | |
6917 | ||
6918 | if (TARGET_SH2A) | |
6919 | { | |
6920 | unsigned int count = 0; | |
6921 | ||
df4bacab | 6922 | for (int i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++) |
91a19652 N |
6923 | if (TEST_HARD_REG_BIT (*mask, i)) |
6924 | count++; | |
6925 | else | |
6926 | break; | |
6927 | ||
6928 | /* Use movml when all banked registers are pushed. */ | |
6929 | if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1) | |
6930 | use_movml = true; | |
6931 | } | |
6932 | ||
57c7433f N |
6933 | if (sh_cfun_resbank_handler_p ()) |
6934 | ; /* Do nothing. */ | |
6935 | else if (use_movml) | |
91a19652 N |
6936 | { |
6937 | rtx x, mem, reg, set; | |
6938 | rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM); | |
6939 | ||
6940 | /* We must avoid scheduling multiple store insn with another | |
6941 | insns. */ | |
6942 | emit_insn (gen_blockage ()); | |
6943 | x = gen_movml_push_banked (sp_reg); | |
df4bacab OE |
6944 | x = emit_frame_insn (x); |
6945 | for (int i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++) | |
91a19652 | 6946 | { |
0a81f074 | 6947 | mem = gen_rtx_MEM (SImode, plus_constant (Pmode, sp_reg, i * 4)); |
91a19652 | 6948 | reg = gen_rtx_REG (SImode, i); |
f7df4a84 | 6949 | add_reg_note (x, REG_CFA_OFFSET, gen_rtx_SET (mem, reg)); |
91a19652 N |
6950 | } |
6951 | ||
f7df4a84 | 6952 | set = gen_rtx_SET (sp_reg, plus_constant (Pmode, sp_reg, - 32)); |
91a19652 N |
6953 | add_reg_note (x, REG_CFA_ADJUST_CFA, set); |
6954 | emit_insn (gen_blockage ()); | |
6955 | } | |
6956 | else | |
df4bacab | 6957 | for (int i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++) |
91a19652 N |
6958 | if (TEST_HARD_REG_BIT (*mask, i)) |
6959 | push (i); | |
6960 | } | |
5c7cafa8 | 6961 | |
561642fa AP |
6962 | /* Don't push PR register for an ISR with RESBANK attribute assigned. */ |
6963 | if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ()) | |
1245df60 | 6964 | push (PR_REG); |
8aa2a305 JW |
6965 | } |
6966 | ||
6967 | /* Work out the registers which need to be saved, both as a mask and a | |
490dbac7 | 6968 | count of saved words. Return the count. |
8aa2a305 JW |
6969 | |
6970 | If doing a pragma interrupt function, then push all regs used by the | |
6971 | function, and if we call another function (we can tell by looking at PR), | |
6972 | make sure that all the regs it clobbers are safe too. */ | |
490dbac7 | 6973 | static int |
cf277499 | 6974 | calc_live_regs (HARD_REG_SET *live_regs_mask) |
8aa2a305 | 6975 | { |
0ef2c525 | 6976 | unsigned int reg; |
a6ab9fc0 R |
6977 | tree attrs; |
6978 | bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler; | |
6979 | bool nosave_low_regs; | |
157131d7 | 6980 | |
a6ab9fc0 R |
6981 | attrs = DECL_ATTRIBUTES (current_function_decl); |
6982 | interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p (); | |
6983 | trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE; | |
6984 | interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler; | |
6985 | nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE; | |
8aa2a305 | 6986 | |
fada1961 | 6987 | CLEAR_HARD_REG_SET (*live_regs_mask); |
d5dd0a62 | 6988 | if (TARGET_FPU_DOUBLE && TARGET_FMOVD && interrupt_handler |
6fb5fa3c | 6989 | && df_regs_ever_live_p (FPSCR_REG)) |
c0fb94d7 | 6990 | target_flags &= ~MASK_FPU_SINGLE; |
225e4f43 | 6991 | /* If we can save a lot of saves by switching to double mode, do that. */ |
d5dd0a62 | 6992 | else if (TARGET_FPU_DOUBLE && TARGET_FMOVD && TARGET_FPU_SINGLE) |
df4bacab | 6993 | for (int count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2) |
6fb5fa3c | 6994 | if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1) |
62164eb4 | 6995 | && (! call_really_used_regs[reg] |
a6ab9fc0 | 6996 | || interrupt_handler) |
225e4f43 R |
6997 | && ++count > 2) |
6998 | { | |
c0fb94d7 | 6999 | target_flags &= ~MASK_FPU_SINGLE; |
225e4f43 R |
7000 | break; |
7001 | } | |
e1fab8ba | 7002 | |
df4bacab OE |
7003 | |
7004 | rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG); | |
7005 | bool pr_live = (pr_initial | |
f3536097 | 7006 | ? (!REG_P (pr_initial) |
29db2a1e | 7007 | || REGNO (pr_initial) != (PR_REG)) |
6fb5fa3c | 7008 | : df_regs_ever_live_p (PR_REG)); |
df4bacab OE |
7009 | /* For Shcompact, if not optimizing, we end up with a memory reference |
7010 | using the return address pointer for __builtin_return_address even | |
7011 | though there is no actual need to put the PR register on the stack. */ | |
7012 | pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM); | |
7013 | ||
fa5322fa AO |
7014 | /* Force PR to be live if the prologue has to call the SHmedia |
7015 | argument decoder or register saver. */ | |
df4bacab OE |
7016 | bool has_call = pr_live; |
7017 | ||
7018 | int count; | |
0ef2c525 | 7019 | for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; ) |
8aa2a305 | 7020 | { |
e1fab8ba | 7021 | if (reg == PR_REG |
3007d592 | 7022 | ? pr_live |
a6ab9fc0 | 7023 | : interrupt_handler |
1245df60 | 7024 | ? (/* Need to save all the regs ever live. */ |
6fb5fa3c | 7025 | (df_regs_ever_live_p (reg) |
62164eb4 R |
7026 | || (call_really_used_regs[reg] |
7027 | && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG | |
7028 | || reg == PIC_OFFSET_TABLE_REGNUM) | |
e1fab8ba | 7029 | && has_call)) |
1245df60 R |
7030 | && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM |
7031 | && reg != RETURN_ADDRESS_POINTER_REGNUM | |
7144b2d8 | 7032 | && reg != T_REG && reg != GBR_REG |
3a2317d1 | 7033 | && reg != FPSCR_MODES_REG && reg != FPSCR_STAT_REG |
7144b2d8 DD |
7034 | /* Push fpscr only on targets which have FPU */ |
7035 | && (reg != FPSCR_REG || TARGET_FPU_ANY)) | |
1245df60 | 7036 | : (/* Only push those regs which are used and need to be saved. */ |
e1fab8ba | 7037 | (false) |
6fb5fa3c | 7038 | || (df_regs_ever_live_p (reg) |
9fdcdc74 KK |
7039 | && ((!call_really_used_regs[reg] |
7040 | && !(reg != PIC_OFFSET_TABLE_REGNUM | |
7041 | && fixed_regs[reg] && call_used_regs[reg])) | |
a6ab9fc0 | 7042 | || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY))) |
e3b5732b | 7043 | || (crtl->calls_eh_return |
0ef2c525 KK |
7044 | && (reg == EH_RETURN_DATA_REGNO (0) |
7045 | || reg == EH_RETURN_DATA_REGNO (1) | |
7046 | || reg == EH_RETURN_DATA_REGNO (2) | |
7047 | || reg == EH_RETURN_DATA_REGNO (3))) | |
61f71b34 | 7048 | || ((reg == MACL_REG || reg == MACH_REG) |
6fb5fa3c | 7049 | && df_regs_ever_live_p (reg) |
61f71b34 DD |
7050 | && sh_cfun_attr_renesas_p ()) |
7051 | )) | |
8aa2a305 | 7052 | { |
490dbac7 | 7053 | SET_HARD_REG_BIT (*live_regs_mask, reg); |
fa5322fa AO |
7054 | count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg)); |
7055 | ||
d5dd0a62 | 7056 | if (TARGET_FPU_DOUBLE && TARGET_FMOVD |
fa5322fa | 7057 | && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT) |
eda44c78 | 7058 | { |
104ee20b | 7059 | if (FP_REGISTER_P (reg)) |
eda44c78 | 7060 | { |
6fb5fa3c | 7061 | if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1)) |
eda44c78 | 7062 | { |
490dbac7 | 7063 | SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1)); |
fa5322fa | 7064 | count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1)); |
eda44c78 R |
7065 | } |
7066 | } | |
fa5322fa | 7067 | else if (XD_REGISTER_P (reg)) |
eda44c78 R |
7068 | { |
7069 | /* Must switch to double mode to access these registers. */ | |
c0fb94d7 | 7070 | target_flags &= ~MASK_FPU_SINGLE; |
eda44c78 R |
7071 | } |
7072 | } | |
8aa2a305 | 7073 | } |
a6ab9fc0 R |
7074 | if (nosave_low_regs && reg == R8_REG) |
7075 | break; | |
8aa2a305 JW |
7076 | } |
7077 | ||
490dbac7 | 7078 | return count; |
8aa2a305 JW |
7079 | } |
7080 | ||
7081 | /* Code to generate prologue and epilogue sequences */ | |
b9654711 | 7082 | |
a93d1ba2 | 7083 | /* PUSHED is the number of bytes that are being pushed on the |
0ad913af R |
7084 | stack for register saves. Return the frame size, padded |
7085 | appropriately so that the stack stays properly aligned. */ | |
e5f8d4c0 | 7086 | static HOST_WIDE_INT |
cf277499 | 7087 | rounded_frame_size (int pushed) |
e5f8d4c0 R |
7088 | { |
7089 | HOST_WIDE_INT size = get_frame_size (); | |
7090 | HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT; | |
7091 | ||
7a296495 CB |
7092 | if (ACCUMULATE_OUTGOING_ARGS) |
7093 | size += crtl->outgoing_args_size; | |
7094 | ||
c5b9ef02 | 7095 | return ((size + pushed + align - 1) & -align) - pushed; |
e5f8d4c0 R |
7096 | } |
7097 | ||
50fe8924 | 7098 | /* Expand code for the function prologue. */ |
b9654711 | 7099 | void |
cf277499 | 7100 | sh_expand_prologue (void) |
b9654711 | 7101 | { |
225e4f43 | 7102 | int save_flags = target_flags; |
a6ab9fc0 R |
7103 | tree sp_switch_attr |
7104 | = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)); | |
b9654711 | 7105 | |
e3ba8d11 | 7106 | current_function_interrupt = sh_cfun_interrupt_handler_p (); |
552ecbd9 | 7107 | |
0d7e008e | 7108 | /* We have pretend args if we had an object sent partially in registers |
8aa2a305 | 7109 | and partially on the stack, e.g. a large structure. */ |
df4bacab | 7110 | int pretend_args = crtl->args.pretend_args_size; |
49616835 JR |
7111 | if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl) |
7112 | && (NPARM_REGS(SImode) | |
38173d38 | 7113 | > crtl->args.info.arg_count[(int) SH_ARG_INT])) |
49616835 | 7114 | pretend_args = 0; |
803b9370 | 7115 | |
df4bacab OE |
7116 | output_stack_adjust (-pretend_args, stack_pointer_rtx, 0, NULL, true); |
7117 | int stack_usage = pretend_args; | |
b9654711 | 7118 | |
7ab56274 | 7119 | /* Emit the code for SETUP_VARARGS. */ |
e3b5732b | 7120 | if (cfun->stdarg) |
b9654711 | 7121 | { |
49616835 | 7122 | if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)) |
1245df60 | 7123 | { |
1a95a963 | 7124 | /* Push arg regs as if they'd been provided by caller in stack. */ |
df4bacab | 7125 | for (int i = 0; i < NPARM_REGS(SImode); i++) |
1a95a963 JW |
7126 | { |
7127 | int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1; | |
2754d3c5 | 7128 | |
f676971a | 7129 | if (i >= (NPARM_REGS(SImode) |
38173d38 | 7130 | - crtl->args.info.arg_count[(int) SH_ARG_INT] |
aec373f1 | 7131 | )) |
1a95a963 | 7132 | break; |
535b951f | 7133 | push (rn); |
e631262b | 7134 | stack_usage += GET_MODE_SIZE (SImode); |
1a95a963 | 7135 | } |
1245df60 | 7136 | } |
b9654711 | 7137 | } |
1a95a963 | 7138 | |
4408efce | 7139 | /* If we're supposed to switch stacks at function entry, do so now. */ |
a6ab9fc0 R |
7140 | if (sp_switch_attr) |
7141 | { | |
20e19db4 | 7142 | rtx lab, newsrc; |
a6ab9fc0 R |
7143 | /* The argument specifies a variable holding the address of the |
7144 | stack the interrupt function should switch to/from at entry/exit. */ | |
20e19db4 | 7145 | tree arg = TREE_VALUE ( TREE_VALUE (sp_switch_attr)); |
df4bacab | 7146 | const char* s = ggc_strdup (TREE_STRING_POINTER (arg)); |
a6ab9fc0 R |
7147 | rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s); |
7148 | ||
20e19db4 DD |
7149 | lab = add_constant (sp_switch, SImode, 0); |
7150 | newsrc = gen_rtx_LABEL_REF (VOIDmode, lab); | |
20e19db4 DD |
7151 | |
7152 | emit_insn (gen_sp_switch_1 (newsrc)); | |
a6ab9fc0 | 7153 | } |
4408efce | 7154 | |
df4bacab OE |
7155 | HARD_REG_SET live_regs_mask; |
7156 | int d = calc_live_regs (&live_regs_mask); | |
225e4f43 R |
7157 | /* ??? Maybe we could save some switching if we can move a mode switch |
7158 | that already happens to be at the function start into the prologue. */ | |
ac55736a | 7159 | if (target_flags != save_flags && ! current_function_interrupt) |
225e4f43 | 7160 | emit_insn (gen_toggle_sz ()); |
f676971a | 7161 | |
e1fab8ba OE |
7162 | push_regs (&live_regs_mask, current_function_interrupt); |
7163 | stack_usage += d; | |
1a66cd67 | 7164 | |
1e44e857 DJ |
7165 | if (flag_pic && !TARGET_FDPIC |
7166 | && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) | |
b6d10e0b | 7167 | emit_insn (gen_GOTaddr2picreg (const0_rtx)); |
1a66cd67 | 7168 | |
ac55736a | 7169 | if (target_flags != save_flags && ! current_function_interrupt) |
6fb5fa3c | 7170 | emit_insn (gen_toggle_sz ()); |
1a95a963 | 7171 | |
225e4f43 R |
7172 | target_flags = save_flags; |
7173 | ||
df4bacab | 7174 | output_stack_adjust (-rounded_frame_size (d), |
21d05694 | 7175 | stack_pointer_rtx, 0, NULL, true); |
df4bacab | 7176 | stack_usage += rounded_frame_size (d); |
b9654711 SC |
7177 | |
7178 | if (frame_pointer_needed) | |
df4bacab | 7179 | emit_frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx)); |
fa5322fa | 7180 | |
6c5bfec0 KK |
7181 | /* If we are profiling, make sure no instructions are scheduled before |
7182 | the call to mcount. Similarly if some call instructions are swapped | |
7183 | before frame related insns, it'll confuse the unwinder because | |
7184 | currently SH has no unwind info for function epilogues. */ | |
7185 | if (crtl->profile || flag_exceptions || flag_unwind_tables) | |
7186 | emit_insn (gen_blockage ()); | |
7187 | ||
a11e0df4 | 7188 | if (flag_stack_usage_info) |
e631262b | 7189 | current_function_static_stack_size = stack_usage; |
b9654711 SC |
7190 | } |
7191 | ||
50fe8924 | 7192 | /* Expand code for the function epilogue. */ |
b9654711 | 7193 | void |
726d4cb7 | 7194 | sh_expand_epilogue (bool sibcall_p) |
b9654711 | 7195 | { |
225e4f43 | 7196 | int save_flags = target_flags; |
df4bacab | 7197 | bool fpscr_deferred = false; |
726d4cb7 | 7198 | int e = sibcall_p ? -1 : 1; |
3d5a0820 | 7199 | |
df4bacab OE |
7200 | HARD_REG_SET live_regs_mask; |
7201 | int d = calc_live_regs (&live_regs_mask); | |
3d5a0820 | 7202 | |
df4bacab OE |
7203 | int save_size = d; |
7204 | int frame_size = rounded_frame_size (d); | |
fe3ad572 | 7205 | |
b9654711 | 7206 | if (frame_pointer_needed) |
46d81ffa | 7207 | { |
1964788a | 7208 | /* We must avoid scheduling the epilogue with previous basic blocks. |
47ea8d4e | 7209 | See PR/18032 and PR/40313. */ |
1964788a | 7210 | emit_insn (gen_blockage ()); |
96a2347e | 7211 | output_stack_adjust (frame_size, hard_frame_pointer_rtx, e, |
2b8088e7 | 7212 | &live_regs_mask, true); |
07f5b9aa JL |
7213 | |
7214 | /* We must avoid moving the stack pointer adjustment past code | |
7215 | which reads from the local frame, else an interrupt could | |
7216 | occur after the SP adjustment and clobber data in the local | |
7217 | frame. */ | |
7218 | emit_insn (gen_blockage ()); | |
df4bacab | 7219 | emit_frame_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx)); |
46d81ffa | 7220 | } |
3d5a0820 | 7221 | else if (frame_size) |
07f5b9aa JL |
7222 | { |
7223 | /* We must avoid moving the stack pointer adjustment past code | |
7224 | which reads from the local frame, else an interrupt could | |
7225 | occur after the SP adjustment and clobber data in the local | |
7226 | frame. */ | |
7227 | emit_insn (gen_blockage ()); | |
21d05694 | 7228 | output_stack_adjust (frame_size, stack_pointer_rtx, e, |
2b8088e7 | 7229 | &live_regs_mask, true); |
07f5b9aa | 7230 | } |
b9654711 | 7231 | |
16bea517 | 7232 | /* Pop all the registers. */ |
0d7e008e | 7233 | |
ac55736a | 7234 | if (target_flags != save_flags && ! current_function_interrupt) |
225e4f43 | 7235 | emit_insn (gen_toggle_sz ()); |
fa5322fa | 7236 | |
b9654711 | 7237 | { |
5c7cafa8 CB |
7238 | int last_reg; |
7239 | ||
fe3ad572 | 7240 | save_size = 0; |
561642fa AP |
7241 | /* For an ISR with RESBANK attribute assigned, don't pop PR |
7242 | register. */ | |
7243 | if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG) | |
7244 | && !sh_cfun_resbank_handler_p ()) | |
6fb5fa3c DB |
7245 | { |
7246 | if (!frame_pointer_needed) | |
7247 | emit_insn (gen_blockage ()); | |
7248 | pop (PR_REG); | |
7249 | } | |
5c7cafa8 | 7250 | |
6a62ca52 | 7251 | /* Banked registers are popped first to avoid being scheduled in the |
5c7cafa8 CB |
7252 | delay slot. RTE switches banks before the ds instruction. */ |
7253 | if (current_function_interrupt) | |
7254 | { | |
91a19652 N |
7255 | bool use_movml = false; |
7256 | ||
7257 | if (TARGET_SH2A) | |
7258 | { | |
7259 | unsigned int count = 0; | |
7260 | ||
df4bacab | 7261 | for (int i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++) |
91a19652 N |
7262 | if (TEST_HARD_REG_BIT (live_regs_mask, i)) |
7263 | count++; | |
7264 | else | |
7265 | break; | |
7266 | ||
7267 | /* Use movml when all banked register are poped. */ | |
7268 | if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1) | |
7269 | use_movml = true; | |
7270 | } | |
7271 | ||
57c7433f N |
7272 | if (sh_cfun_resbank_handler_p ()) |
7273 | ; /* Do nothing. */ | |
7274 | else if (use_movml) | |
91a19652 N |
7275 | { |
7276 | rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM); | |
7277 | ||
7278 | /* We must avoid scheduling multiple load insn with another | |
7279 | insns. */ | |
7280 | emit_insn (gen_blockage ()); | |
7281 | emit_insn (gen_movml_pop_banked (sp_reg)); | |
7282 | emit_insn (gen_blockage ()); | |
7283 | } | |
7284 | else | |
df4bacab | 7285 | for (int i = LAST_BANKED_REG; i >= FIRST_BANKED_REG; i--) |
91a19652 N |
7286 | if (TEST_HARD_REG_BIT (live_regs_mask, i)) |
7287 | pop (i); | |
5c7cafa8 CB |
7288 | |
7289 | last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1; | |
7290 | } | |
7291 | else | |
7292 | last_reg = FIRST_PSEUDO_REGISTER; | |
7293 | ||
df4bacab | 7294 | for (int i = 0; i < last_reg; i++) |
fe3ad572 SC |
7295 | { |
7296 | int j = (FIRST_PSEUDO_REGISTER - 1) - i; | |
f676971a | 7297 | |
fe3ad572 | 7298 | if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD |
56b138ae RS |
7299 | && hard_reg_set_intersect_p (live_regs_mask, |
7300 | reg_class_contents[DF_REGS])) | |
df4bacab | 7301 | fpscr_deferred = true; |
561642fa AP |
7302 | /* For an ISR with RESBANK attribute assigned, don't pop |
7303 | following registers, R0-R14, MACH, MACL and GBR. */ | |
7304 | else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j) | |
7305 | && ! (sh_cfun_resbank_handler_p () | |
7306 | && ((j >= FIRST_GENERAL_REG | |
7307 | && j < LAST_GENERAL_REG) | |
7308 | || j == MACH_REG | |
7309 | || j == MACL_REG | |
7310 | || j == GBR_REG))) | |
fe3ad572 | 7311 | pop (j); |
5c7cafa8 | 7312 | |
fe3ad572 SC |
7313 | if (j == FIRST_FP_REG && fpscr_deferred) |
7314 | pop (FPSCR_REG); | |
fe3ad572 | 7315 | } |
b9654711 | 7316 | } |
ac55736a | 7317 | if (target_flags != save_flags && ! current_function_interrupt) |
225e4f43 R |
7318 | emit_insn (gen_toggle_sz ()); |
7319 | target_flags = save_flags; | |
b9654711 | 7320 | |
df4bacab | 7321 | output_stack_adjust (crtl->args.pretend_args_size + save_size, |
2b8088e7 | 7322 | stack_pointer_rtx, e, NULL, true); |
4408efce | 7323 | |
e3b5732b | 7324 | if (crtl->calls_eh_return) |
4977bab6 ZW |
7325 | emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx, |
7326 | EH_RETURN_STACKADJ_RTX)); | |
7327 | ||
4408efce | 7328 | /* Switch back to the normal stack if necessary. */ |
a6ab9fc0 | 7329 | if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl))) |
4408efce | 7330 | emit_insn (gen_sp_switch_2 ()); |
89d4bc35 AO |
7331 | |
7332 | /* Tell flow the insn that pops PR isn't dead. */ | |
490dbac7 | 7333 | if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)) |
c41c1387 | 7334 | emit_use (gen_rtx_REG (SImode, PR_REG)); |
b9654711 SC |
7335 | } |
7336 | ||
4977bab6 ZW |
7337 | /* Emit code to change the current function's return address to RA. |
7338 | TEMP is available as a scratch register, if needed. */ | |
4977bab6 | 7339 | void |
cf277499 | 7340 | sh_set_return_address (rtx ra, rtx tmp) |
4977bab6 | 7341 | { |
490dbac7 | 7342 | HARD_REG_SET live_regs_mask; |
e1fab8ba | 7343 | int d = calc_live_regs (&live_regs_mask); |
4977bab6 | 7344 | |
df4bacab | 7345 | /* If pr_reg isn't life, we can set it directly. */ |
e1fab8ba | 7346 | if (! TEST_HARD_REG_BIT (live_regs_mask, PR_REG)) |
4977bab6 | 7347 | { |
e1fab8ba | 7348 | rtx rr = gen_rtx_REG (SImode, PR_REG); |
4977bab6 ZW |
7349 | emit_insn (GEN_MOV (rr, ra)); |
7350 | /* Tell flow the register for return isn't dead. */ | |
c41c1387 | 7351 | emit_use (rr); |
4977bab6 ZW |
7352 | return; |
7353 | } | |
7354 | ||
e1fab8ba | 7355 | int pr_offset = rounded_frame_size (d); |
4977bab6 ZW |
7356 | |
7357 | emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset))); | |
7a296495 CB |
7358 | |
7359 | if (frame_pointer_needed) | |
7360 | emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx)); | |
7361 | else | |
7362 | emit_insn (GEN_ADD3 (tmp, tmp, stack_pointer_rtx)); | |
4977bab6 | 7363 | |
57d38024 | 7364 | tmp = gen_frame_mem (Pmode, tmp); |
4977bab6 | 7365 | emit_insn (GEN_MOV (tmp, ra)); |
7f9a14e3 KK |
7366 | /* Tell this store isn't dead. */ |
7367 | emit_use (tmp); | |
4977bab6 ZW |
7368 | } |
7369 | ||
8aa2a305 | 7370 | /* Clear variables at function end. */ |
08c148a8 | 7371 | static void |
42776416 | 7372 | sh_output_function_epilogue (FILE *) |
8aa2a305 | 7373 | { |
8aa2a305 JW |
7374 | } |
7375 | ||
61f71b34 | 7376 | static rtx |
cf277499 | 7377 | sh_builtin_saveregs (void) |
1a95a963 | 7378 | { |
1a95a963 | 7379 | /* First unnamed integer register. */ |
38173d38 | 7380 | int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT]; |
1a95a963 JW |
7381 | /* Number of integer registers we need to save. */ |
7382 | int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg); | |
7383 | /* First unnamed SFmode float reg */ | |
38173d38 | 7384 | int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT]; |
1a95a963 JW |
7385 | /* Number of SFmode float regs to save. */ |
7386 | int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg); | |
318881c0 | 7387 | rtx regbuf, fpregs; |
ba4828e0 | 7388 | int bufsize, regno; |
4862826d | 7389 | alias_set_type alias_set; |
1a95a963 | 7390 | |
df4bacab | 7391 | if (!TARGET_FPU_ANY) |
fa5322fa | 7392 | { |
e1fab8ba OE |
7393 | error ("__builtin_saveregs not supported by this subtarget"); |
7394 | return const0_rtx; | |
7395 | } | |
fa5322fa | 7396 | |
6f317ef3 | 7397 | /* Allocate block of memory for the regs. */ |
1a95a963 JW |
7398 | /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte? |
7399 | Or can assign_stack_local accept a 0 SIZE argument? */ | |
7400 | bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD); | |
7401 | ||
e1fab8ba | 7402 | if (n_floatregs & 1) |
f78ec36a R |
7403 | { |
7404 | rtx addr; | |
7405 | ||
7406 | regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0); | |
7407 | addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0)); | |
7408 | emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD))); | |
7409 | regbuf = change_address (regbuf, BLKmode, addr); | |
7410 | } | |
a11c004b R |
7411 | else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs) |
7412 | { | |
7413 | rtx addr, mask; | |
7414 | ||
7415 | regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0); | |
0a81f074 RS |
7416 | addr = copy_to_mode_reg (Pmode, plus_constant (Pmode, |
7417 | XEXP (regbuf, 0), 4)); | |
a11c004b R |
7418 | mask = copy_to_mode_reg (Pmode, GEN_INT (-8)); |
7419 | emit_insn (gen_andsi3 (addr, addr, mask)); | |
7420 | regbuf = change_address (regbuf, BLKmode, addr); | |
7421 | } | |
fa5322fa | 7422 | else |
a11c004b | 7423 | regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0); |
514066a1 | 7424 | alias_set = get_varargs_alias_set (); |
ba4828e0 | 7425 | set_mem_alias_set (regbuf, alias_set); |
1a95a963 JW |
7426 | |
7427 | /* Save int args. | |
7428 | This is optimized to only save the regs that are necessary. Explicitly | |
7429 | named args need not be saved. */ | |
7430 | if (n_intregs > 0) | |
7431 | move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg, | |
f4ef873c RK |
7432 | adjust_address (regbuf, BLKmode, |
7433 | n_floatregs * UNITS_PER_WORD), | |
c6b97fac | 7434 | n_intregs); |
1a95a963 JW |
7435 | |
7436 | /* Save float args. | |
7437 | This is optimized to only save the regs that are necessary. Explicitly | |
7438 | named args need not be saved. | |
7439 | We explicitly build a pointer to the buffer because it halves the insn | |
7440 | count when not optimizing (otherwise the pointer is built for each reg | |
1245df60 R |
7441 | saved). |
7442 | We emit the moves in reverse order so that we can use predecrement. */ | |
1a95a963 | 7443 | |
7d9c5aa1 | 7444 | fpregs = copy_to_mode_reg (Pmode, |
0a81f074 RS |
7445 | plus_constant (Pmode, XEXP (regbuf, 0), |
7446 | n_floatregs * UNITS_PER_WORD)); | |
d5dd0a62 | 7447 | if (TARGET_FPU_DOUBLE) |
225e4f43 | 7448 | { |
514066a1 | 7449 | rtx mem; |
225e4f43 R |
7450 | for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2) |
7451 | { | |
7452 | emit_insn (gen_addsi3 (fpregs, fpregs, | |
7453 | GEN_INT (-2 * UNITS_PER_WORD))); | |
57d38024 | 7454 | mem = change_address (regbuf, DFmode, fpregs); |
f676971a | 7455 | emit_move_insn (mem, |
c0d4e710 | 7456 | gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno)); |
225e4f43 R |
7457 | } |
7458 | regno = first_floatreg; | |
7459 | if (regno & 1) | |
7460 | { | |
832a3292 | 7461 | emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD))); |
57d38024 | 7462 | mem = change_address (regbuf, SFmode, fpregs); |
514066a1 | 7463 | emit_move_insn (mem, |
277772f6 OE |
7464 | gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) |
7465 | + regno - SH_REG_MSW_OFFSET)); | |
225e4f43 R |
7466 | } |
7467 | } | |
7468 | else | |
1245df60 R |
7469 | for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--) |
7470 | { | |
514066a1 | 7471 | rtx mem; |
ba4828e0 | 7472 | |
832a3292 | 7473 | emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD))); |
57d38024 | 7474 | mem = change_address (regbuf, SFmode, fpregs); |
514066a1 | 7475 | emit_move_insn (mem, |
c5c76735 | 7476 | gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno)); |
1245df60 | 7477 | } |
1a95a963 JW |
7478 | |
7479 | /* Return the address of the regbuf. */ | |
7480 | return XEXP (regbuf, 0); | |
7481 | } | |
7482 | ||
514066a1 | 7483 | /* Define the `__builtin_va_list' type for the ABI. */ |
c35d187f RH |
7484 | static tree |
7485 | sh_build_builtin_va_list (void) | |
514066a1 RH |
7486 | { |
7487 | tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack; | |
10575b5d | 7488 | tree record, type_decl; |
514066a1 | 7489 | |
e1fab8ba | 7490 | if ((! TARGET_SH2E && ! TARGET_SH4) |
61f71b34 | 7491 | || TARGET_HITACHI || sh_cfun_attr_renesas_p ()) |
514066a1 RH |
7492 | return ptr_type_node; |
7493 | ||
5d27ef94 | 7494 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
10575b5d KK |
7495 | type_decl = build_decl (BUILTINS_LOCATION, |
7496 | TYPE_DECL, get_identifier ("__va_list_tag"), record); | |
514066a1 | 7497 | |
4c4bde29 AH |
7498 | f_next_o = build_decl (BUILTINS_LOCATION, |
7499 | FIELD_DECL, get_identifier ("__va_next_o"), | |
514066a1 | 7500 | ptr_type_node); |
4c4bde29 AH |
7501 | f_next_o_limit = build_decl (BUILTINS_LOCATION, |
7502 | FIELD_DECL, | |
514066a1 RH |
7503 | get_identifier ("__va_next_o_limit"), |
7504 | ptr_type_node); | |
4c4bde29 AH |
7505 | f_next_fp = build_decl (BUILTINS_LOCATION, |
7506 | FIELD_DECL, get_identifier ("__va_next_fp"), | |
514066a1 | 7507 | ptr_type_node); |
4c4bde29 AH |
7508 | f_next_fp_limit = build_decl (BUILTINS_LOCATION, |
7509 | FIELD_DECL, | |
514066a1 RH |
7510 | get_identifier ("__va_next_fp_limit"), |
7511 | ptr_type_node); | |
4c4bde29 AH |
7512 | f_next_stack = build_decl (BUILTINS_LOCATION, |
7513 | FIELD_DECL, get_identifier ("__va_next_stack"), | |
514066a1 RH |
7514 | ptr_type_node); |
7515 | ||
7516 | DECL_FIELD_CONTEXT (f_next_o) = record; | |
7517 | DECL_FIELD_CONTEXT (f_next_o_limit) = record; | |
7518 | DECL_FIELD_CONTEXT (f_next_fp) = record; | |
7519 | DECL_FIELD_CONTEXT (f_next_fp_limit) = record; | |
7520 | DECL_FIELD_CONTEXT (f_next_stack) = record; | |
7521 | ||
0fd2eac2 | 7522 | TYPE_STUB_DECL (record) = type_decl; |
10575b5d | 7523 | TYPE_NAME (record) = type_decl; |
514066a1 | 7524 | TYPE_FIELDS (record) = f_next_o; |
910ad8de NF |
7525 | DECL_CHAIN (f_next_o) = f_next_o_limit; |
7526 | DECL_CHAIN (f_next_o_limit) = f_next_fp; | |
7527 | DECL_CHAIN (f_next_fp) = f_next_fp_limit; | |
7528 | DECL_CHAIN (f_next_fp_limit) = f_next_stack; | |
514066a1 RH |
7529 | |
7530 | layout_type (record); | |
7531 | ||
7532 | return record; | |
7533 | } | |
7534 | ||
7535 | /* Implement `va_start' for varargs and stdarg. */ | |
d7bd8aeb | 7536 | static void |
cf277499 | 7537 | sh_va_start (tree valist, rtx nextarg) |
514066a1 RH |
7538 | { |
7539 | tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack; | |
7540 | tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack; | |
7541 | tree t, u; | |
7542 | int nfp, nint; | |
7543 | ||
61f71b34 DD |
7544 | if ((! TARGET_SH2E && ! TARGET_SH4) |
7545 | || TARGET_HITACHI || sh_cfun_attr_renesas_p ()) | |
514066a1 | 7546 | { |
e5faf155 | 7547 | std_expand_builtin_va_start (valist, nextarg); |
514066a1 RH |
7548 | return; |
7549 | } | |
7550 | ||
7551 | f_next_o = TYPE_FIELDS (va_list_type_node); | |
910ad8de NF |
7552 | f_next_o_limit = DECL_CHAIN (f_next_o); |
7553 | f_next_fp = DECL_CHAIN (f_next_o_limit); | |
7554 | f_next_fp_limit = DECL_CHAIN (f_next_fp); | |
7555 | f_next_stack = DECL_CHAIN (f_next_fp_limit); | |
514066a1 | 7556 | |
47a25a46 | 7557 | next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o, |
44de5aeb | 7558 | NULL_TREE); |
47a25a46 RG |
7559 | next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit), |
7560 | valist, f_next_o_limit, NULL_TREE); | |
7561 | next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp, | |
7562 | NULL_TREE); | |
7563 | next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit), | |
7564 | valist, f_next_fp_limit, NULL_TREE); | |
7565 | next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack), | |
7566 | valist, f_next_stack, NULL_TREE); | |
514066a1 RH |
7567 | |
7568 | /* Call __builtin_saveregs. */ | |
5be014d5 AP |
7569 | u = make_tree (sizetype, expand_builtin_saveregs ()); |
7570 | u = fold_convert (ptr_type_node, u); | |
726a989a | 7571 | t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u); |
514066a1 RH |
7572 | TREE_SIDE_EFFECTS (t) = 1; |
7573 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
7574 | ||
38173d38 | 7575 | nfp = crtl->args.info.arg_count[SH_ARG_FLOAT]; |
514066a1 RH |
7576 | if (nfp < 8) |
7577 | nfp = 8 - nfp; | |
7578 | else | |
7579 | nfp = 0; | |
5d49b6a7 | 7580 | u = fold_build_pointer_plus_hwi (u, UNITS_PER_WORD * nfp); |
726a989a | 7581 | t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u); |
514066a1 RH |
7582 | TREE_SIDE_EFFECTS (t) = 1; |
7583 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
7584 | ||
726a989a | 7585 | t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u); |
514066a1 RH |
7586 | TREE_SIDE_EFFECTS (t) = 1; |
7587 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
7588 | ||
38173d38 | 7589 | nint = crtl->args.info.arg_count[SH_ARG_INT]; |
514066a1 RH |
7590 | if (nint < 4) |
7591 | nint = 4 - nint; | |
7592 | else | |
7593 | nint = 0; | |
5d49b6a7 | 7594 | u = fold_build_pointer_plus_hwi (u, UNITS_PER_WORD * nint); |
726a989a | 7595 | t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u); |
514066a1 RH |
7596 | TREE_SIDE_EFFECTS (t) = 1; |
7597 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
7598 | ||
7599 | u = make_tree (ptr_type_node, nextarg); | |
726a989a | 7600 | t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u); |
514066a1 RH |
7601 | TREE_SIDE_EFFECTS (t) = 1; |
7602 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
7603 | } | |
7604 | ||
917f1b7e | 7605 | /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized |
21bdb106 JR |
7606 | member, return it. */ |
7607 | static tree | |
7608 | find_sole_member (tree type) | |
7609 | { | |
7610 | tree field, member = NULL_TREE; | |
7611 | ||
910ad8de | 7612 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) |
21bdb106 JR |
7613 | { |
7614 | if (TREE_CODE (field) != FIELD_DECL) | |
7615 | continue; | |
7616 | if (!DECL_SIZE (field)) | |
7617 | return NULL_TREE; | |
7618 | if (integer_zerop (DECL_SIZE (field))) | |
7619 | continue; | |
7620 | if (member) | |
7621 | return NULL_TREE; | |
7622 | member = field; | |
7623 | } | |
7624 | return member; | |
7625 | } | |
514066a1 | 7626 | |
50fe8924 | 7627 | /* Implement `va_arg'. */ |
5fac2ed2 | 7628 | static tree |
726a989a RB |
7629 | sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
7630 | gimple_seq *post_p ATTRIBUTE_UNUSED) | |
514066a1 | 7631 | { |
df4bacab | 7632 | tree tmp; |
0ef2c525 | 7633 | tree addr, lab_over = NULL, result = NULL; |
11160b58 | 7634 | tree eff_type; |
5fac2ed2 | 7635 | |
df4bacab OE |
7636 | const bool pass_by_ref = |
7637 | !VOID_TYPE_P (type) | |
7638 | && targetm.calls.must_pass_in_stack (TYPE_MODE (type), type); | |
57a944d7 | 7639 | |
5fac2ed2 RH |
7640 | if (pass_by_ref) |
7641 | type = build_pointer_type (type); | |
514066a1 | 7642 | |
df4bacab OE |
7643 | HOST_WIDE_INT size = int_size_in_bytes (type); |
7644 | HOST_WIDE_INT rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; | |
7645 | tree pptr_type_node = build_pointer_type (ptr_type_node); | |
514066a1 | 7646 | |
e1fab8ba | 7647 | if ((TARGET_SH2E || TARGET_SH4) |
61f71b34 | 7648 | && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ())) |
514066a1 RH |
7649 | { |
7650 | tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack; | |
7651 | tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack; | |
5fac2ed2 | 7652 | tree lab_false; |
21bdb106 | 7653 | tree member; |
514066a1 RH |
7654 | |
7655 | f_next_o = TYPE_FIELDS (va_list_type_node); | |
910ad8de NF |
7656 | f_next_o_limit = DECL_CHAIN (f_next_o); |
7657 | f_next_fp = DECL_CHAIN (f_next_o_limit); | |
7658 | f_next_fp_limit = DECL_CHAIN (f_next_fp); | |
7659 | f_next_stack = DECL_CHAIN (f_next_fp_limit); | |
514066a1 | 7660 | |
47a25a46 RG |
7661 | next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o, |
7662 | NULL_TREE); | |
7663 | next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit), | |
7664 | valist, f_next_o_limit, NULL_TREE); | |
7665 | next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), | |
50fe8924 | 7666 | valist, f_next_fp, NULL_TREE); |
47a25a46 RG |
7667 | next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit), |
7668 | valist, f_next_fp_limit, NULL_TREE); | |
7669 | next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack), | |
7670 | valist, f_next_stack, NULL_TREE); | |
514066a1 | 7671 | |
6d1cb95f R |
7672 | /* Structures with a single member with a distinct mode are passed |
7673 | like their member. This is relevant if the latter has a REAL_TYPE | |
7674 | or COMPLEX_TYPE type. */ | |
11160b58 R |
7675 | eff_type = type; |
7676 | while (TREE_CODE (eff_type) == RECORD_TYPE | |
7677 | && (member = find_sole_member (eff_type)) | |
21bdb106 JR |
7678 | && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE |
7679 | || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE | |
7680 | || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE)) | |
c26104e4 | 7681 | { |
21bdb106 | 7682 | tree field_type = TREE_TYPE (member); |
c26104e4 | 7683 | |
11160b58 R |
7684 | if (TYPE_MODE (eff_type) == TYPE_MODE (field_type)) |
7685 | eff_type = field_type; | |
c26104e4 | 7686 | else |
8a2209bf | 7687 | { |
11160b58 | 7688 | gcc_assert ((TYPE_ALIGN (eff_type) |
21bdb106 | 7689 | < GET_MODE_ALIGNMENT (TYPE_MODE (field_type))) |
11160b58 | 7690 | || (TYPE_ALIGN (eff_type) |
21bdb106 JR |
7691 | > GET_MODE_BITSIZE (TYPE_MODE (field_type)))); |
7692 | break; | |
8a2209bf | 7693 | } |
c26104e4 | 7694 | } |
5fac2ed2 | 7695 | |
df4bacab | 7696 | bool pass_as_float; |
d5dd0a62 | 7697 | if (TARGET_FPU_DOUBLE) |
514066a1 | 7698 | { |
11160b58 R |
7699 | pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8) |
7700 | || (TREE_CODE (eff_type) == COMPLEX_TYPE | |
7701 | && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE | |
514066a1 RH |
7702 | && size <= 16)); |
7703 | } | |
7704 | else | |
7705 | { | |
11160b58 | 7706 | pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4); |
514066a1 RH |
7707 | } |
7708 | ||
9b489f31 | 7709 | addr = create_tmp_var (pptr_type_node); |
4c4bde29 AH |
7710 | lab_false = create_artificial_label (UNKNOWN_LOCATION); |
7711 | lab_over = create_artificial_label (UNKNOWN_LOCATION); | |
514066a1 | 7712 | |
70f34814 | 7713 | valist = build_simple_mem_ref (addr); |
6d1cb95f | 7714 | |
514066a1 RH |
7715 | if (pass_as_float) |
7716 | { | |
9b489f31 | 7717 | tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp)); |
a11c004b | 7718 | tree cmp; |
11160b58 | 7719 | bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE; |
f78ec36a | 7720 | |
8c54989a KK |
7721 | tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp)); |
7722 | gimplify_assign (unshare_expr (addr), tmp, pre_p); | |
a11c004b | 7723 | |
8c54989a | 7724 | gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p); |
a11c004b R |
7725 | tmp = next_fp_limit; |
7726 | if (size > 4 && !is_double) | |
5d49b6a7 | 7727 | tmp = fold_build_pointer_plus_hwi (unshare_expr (tmp), 4 - size); |
8c54989a KK |
7728 | tmp = build2 (GE_EXPR, boolean_type_node, |
7729 | unshare_expr (next_fp_tmp), unshare_expr (tmp)); | |
47a25a46 | 7730 | cmp = build3 (COND_EXPR, void_type_node, tmp, |
8c54989a KK |
7731 | build1 (GOTO_EXPR, void_type_node, |
7732 | unshare_expr (lab_false)), NULL_TREE); | |
a11c004b R |
7733 | if (!is_double) |
7734 | gimplify_and_add (cmp, pre_p); | |
514066a1 | 7735 | |
11160b58 R |
7736 | if (TYPE_ALIGN (eff_type) > BITS_PER_WORD |
7737 | || (is_double || size == 16)) | |
514066a1 | 7738 | { |
5be014d5 AP |
7739 | tmp = fold_convert (sizetype, next_fp_tmp); |
7740 | tmp = build2 (BIT_AND_EXPR, sizetype, tmp, | |
7741 | size_int (UNITS_PER_WORD)); | |
5d49b6a7 | 7742 | tmp = fold_build_pointer_plus (unshare_expr (next_fp_tmp), tmp); |
8c54989a | 7743 | gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p); |
514066a1 | 7744 | } |
a11c004b R |
7745 | if (is_double) |
7746 | gimplify_and_add (cmp, pre_p); | |
514066a1 | 7747 | |
6d1cb95f | 7748 | #ifdef FUNCTION_ARG_SCmode_WART |
11160b58 R |
7749 | if (TYPE_MODE (eff_type) == SCmode |
7750 | && TARGET_SH4 && TARGET_LITTLE_ENDIAN) | |
6d1cb95f | 7751 | { |
11160b58 | 7752 | tree subtype = TREE_TYPE (eff_type); |
5fac2ed2 | 7753 | tree real, imag; |
6d1cb95f | 7754 | |
a11c004b R |
7755 | imag |
7756 | = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL); | |
5fac2ed2 | 7757 | imag = get_initialized_tmp_var (imag, pre_p, NULL); |
6d1cb95f | 7758 | |
a11c004b R |
7759 | real |
7760 | = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL); | |
5fac2ed2 RH |
7761 | real = get_initialized_tmp_var (real, pre_p, NULL); |
7762 | ||
f2a945b1 KK |
7763 | result = build2 (COMPLEX_EXPR, eff_type, real, imag); |
7764 | if (type != eff_type) | |
7765 | result = build1 (VIEW_CONVERT_EXPR, type, result); | |
5fac2ed2 | 7766 | result = get_initialized_tmp_var (result, pre_p, NULL); |
6d1cb95f R |
7767 | } |
7768 | #endif /* FUNCTION_ARG_SCmode_WART */ | |
7769 | ||
8c54989a | 7770 | tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over)); |
5fac2ed2 RH |
7771 | gimplify_and_add (tmp, pre_p); |
7772 | ||
8c54989a | 7773 | tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false)); |
5fac2ed2 | 7774 | gimplify_and_add (tmp, pre_p); |
514066a1 | 7775 | |
8c54989a KK |
7776 | tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack)); |
7777 | gimplify_assign (unshare_expr (addr), tmp, pre_p); | |
7778 | gimplify_assign (unshare_expr (next_fp_tmp), | |
7779 | unshare_expr (valist), pre_p); | |
a11c004b | 7780 | |
8c54989a KK |
7781 | gimplify_assign (unshare_expr (valist), |
7782 | unshare_expr (next_fp_tmp), post_p); | |
a11c004b | 7783 | valist = next_fp_tmp; |
514066a1 RH |
7784 | } |
7785 | else | |
7786 | { | |
5d49b6a7 | 7787 | tmp = fold_build_pointer_plus_hwi (unshare_expr (next_o), rsize); |
8c54989a KK |
7788 | tmp = build2 (GT_EXPR, boolean_type_node, tmp, |
7789 | unshare_expr (next_o_limit)); | |
47a25a46 | 7790 | tmp = build3 (COND_EXPR, void_type_node, tmp, |
8c54989a KK |
7791 | build1 (GOTO_EXPR, void_type_node, |
7792 | unshare_expr (lab_false)), | |
7793 | NULL_TREE); | |
5fac2ed2 | 7794 | gimplify_and_add (tmp, pre_p); |
514066a1 | 7795 | |
8c54989a KK |
7796 | tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o)); |
7797 | gimplify_assign (unshare_expr (addr), tmp, pre_p); | |
514066a1 | 7798 | |
8c54989a | 7799 | tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over)); |
5fac2ed2 RH |
7800 | gimplify_and_add (tmp, pre_p); |
7801 | ||
8c54989a | 7802 | tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false)); |
5fac2ed2 | 7803 | gimplify_and_add (tmp, pre_p); |
514066a1 | 7804 | |
bdf57c40 | 7805 | if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A)) |
8c54989a KK |
7806 | gimplify_assign (unshare_expr (next_o), |
7807 | unshare_expr (next_o_limit), pre_p); | |
514066a1 | 7808 | |
8c54989a KK |
7809 | tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack)); |
7810 | gimplify_assign (unshare_expr (addr), tmp, pre_p); | |
514066a1 RH |
7811 | } |
7812 | ||
5fac2ed2 RH |
7813 | if (!result) |
7814 | { | |
8c54989a | 7815 | tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over)); |
5fac2ed2 RH |
7816 | gimplify_and_add (tmp, pre_p); |
7817 | } | |
514066a1 RH |
7818 | } |
7819 | ||
7820 | /* ??? In va-sh.h, there had been code to make values larger than | |
7821 | size 8 indirect. This does not match the FUNCTION_ARG macros. */ | |
7822 | ||
5fac2ed2 | 7823 | tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL); |
6d1cb95f R |
7824 | if (result) |
7825 | { | |
726a989a | 7826 | gimplify_assign (result, tmp, pre_p); |
a1516d08 | 7827 | result = build1 (NOP_EXPR, TREE_TYPE (result), result); |
8c54989a | 7828 | tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over)); |
5fac2ed2 | 7829 | gimplify_and_add (tmp, pre_p); |
6d1cb95f R |
7830 | } |
7831 | else | |
5fac2ed2 | 7832 | result = tmp; |
6d1cb95f | 7833 | |
5e039e6b | 7834 | if (pass_by_ref) |
d6e9821f | 7835 | result = build_va_arg_indirect_ref (result); |
5fac2ed2 | 7836 | |
5e039e6b | 7837 | return result; |
514066a1 RH |
7838 | } |
7839 | ||
63a9de54 | 7840 | /* 64 bit floating points memory transfers are paired single precision loads |
50fe8924 | 7841 | or store. So DWARF information needs fixing in little endian (unless |
63a9de54 CB |
7842 | PR=SZ=1 in FPSCR). */ |
7843 | rtx | |
7844 | sh_dwarf_register_span (rtx reg) | |
7845 | { | |
7846 | unsigned regno = REGNO (reg); | |
7847 | ||
7848 | if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode) | |
7849 | return NULL_RTX; | |
7850 | ||
7851 | return | |
7852 | gen_rtx_PARALLEL (VOIDmode, | |
7853 | gen_rtvec (2, | |
59248459 KK |
7854 | gen_rtx_REG (SFmode, regno + 1), |
7855 | gen_rtx_REG (SFmode, regno))); | |
63a9de54 CB |
7856 | } |
7857 | ||
ef4bddc2 RS |
7858 | static machine_mode |
7859 | sh_promote_function_mode (const_tree type, machine_mode mode, | |
d8158ff1 | 7860 | int *punsignedp, const_tree funtype, |
8a575d5a | 7861 | int for_return) |
cde0f3fd PB |
7862 | { |
7863 | if (sh_promote_prototypes (funtype)) | |
d055ce45 | 7864 | return promote_mode (type, mode, punsignedp); |
cde0f3fd | 7865 | else |
8a575d5a PB |
7866 | return default_promote_function_mode (type, mode, punsignedp, funtype, |
7867 | for_return); | |
cde0f3fd PB |
7868 | } |
7869 | ||
d64728cf | 7870 | static bool |
586de218 | 7871 | sh_promote_prototypes (const_tree type) |
61f71b34 DD |
7872 | { |
7873 | if (TARGET_HITACHI) | |
aaf701c5 | 7874 | return false; |
61f71b34 | 7875 | if (! type) |
aaf701c5 | 7876 | return true; |
61f71b34 DD |
7877 | return ! sh_attr_renesas_p (type); |
7878 | } | |
7879 | ||
8cd5a4e0 | 7880 | static bool |
ef4bddc2 | 7881 | sh_pass_by_reference (cumulative_args_t cum_v, machine_mode mode, |
e1fab8ba | 7882 | const_tree type, bool named ATTRIBUTE_UNUSED) |
8cd5a4e0 | 7883 | { |
d5cc9181 JR |
7884 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
7885 | ||
8cd5a4e0 RH |
7886 | if (targetm.calls.must_pass_in_stack (mode, type)) |
7887 | return true; | |
7888 | ||
03603192 JR |
7889 | /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function |
7890 | wants to know about pass-by-reference semantics for incoming | |
7891 | arguments. */ | |
7892 | if (! cum) | |
7893 | return false; | |
7894 | ||
8cd5a4e0 RH |
7895 | return false; |
7896 | } | |
7897 | ||
6cdd5672 | 7898 | static bool |
ef4bddc2 | 7899 | sh_callee_copies (cumulative_args_t cum, machine_mode mode, |
586de218 | 7900 | const_tree type, bool named ATTRIBUTE_UNUSED) |
6cdd5672 RH |
7901 | { |
7902 | /* ??? How can it possibly be correct to return true only on the | |
7903 | caller side of the equation? Is there someplace else in the | |
7904 | sh backend that's magically producing the copies? */ | |
d5cc9181 | 7905 | return (get_cumulative_args (cum)->outgoing |
6cdd5672 RH |
7906 | && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) |
7907 | % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0)); | |
7908 | } | |
7909 | ||
0983497f OE |
7910 | static sh_arg_class |
7911 | get_sh_arg_class (machine_mode mode) | |
7912 | { | |
7913 | if (TARGET_FPU_ANY && mode == SFmode) | |
7914 | return SH_ARG_FLOAT; | |
7915 | ||
7916 | if (TARGET_FPU_DOUBLE | |
7917 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
7918 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)) | |
7919 | return SH_ARG_FLOAT; | |
7920 | ||
7921 | return SH_ARG_INT; | |
7922 | } | |
7923 | ||
f6982a08 OE |
7924 | /* Round a register number up to a proper boundary for an arg of mode |
7925 | MODE. | |
7926 | The SH doesn't care about double alignment, so we only | |
7927 | round doubles to even regs when asked to explicitly. */ | |
7928 | static int | |
7929 | sh_round_reg (const CUMULATIVE_ARGS& cum, machine_mode mode) | |
7930 | { | |
7931 | /* FIXME: This used to be a macro and has been copy pasted into this | |
7932 | function as is. Make this more readable. */ | |
7933 | return | |
7934 | (((TARGET_ALIGN_DOUBLE | |
d5dd0a62 | 7935 | || (TARGET_FPU_DOUBLE |
f6982a08 OE |
7936 | && (mode == DFmode || mode == DCmode) |
7937 | && cum.arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (mode))) | |
7938 | && GET_MODE_UNIT_SIZE (mode) > UNITS_PER_WORD) | |
0983497f OE |
7939 | ? (cum.arg_count[(int) get_sh_arg_class (mode)] |
7940 | + (cum.arg_count[(int) get_sh_arg_class (mode)] & 1)) | |
7941 | : cum.arg_count[(int) get_sh_arg_class (mode)]); | |
f6982a08 OE |
7942 | } |
7943 | ||
026c3cfd | 7944 | /* Return true if arg of the specified mode should be passed in a register |
f6982a08 OE |
7945 | or false otherwise. */ |
7946 | static bool | |
7947 | sh_pass_in_reg_p (const CUMULATIVE_ARGS& cum, machine_mode mode, | |
7948 | const_tree type) | |
7949 | { | |
7950 | /* FIXME: This used to be a macro and has been copy pasted into this | |
7951 | function as is. Make this more readable. */ | |
7952 | return | |
7953 | ((type == 0 | |
7954 | || (! TREE_ADDRESSABLE (type) | |
7955 | && (! (TARGET_HITACHI || cum.renesas_abi) | |
7956 | || ! (AGGREGATE_TYPE_P (type) | |
7957 | || (!TARGET_FPU_ANY | |
7958 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
7959 | && GET_MODE_SIZE (mode) > GET_MODE_SIZE (SFmode))))))) | |
7960 | && ! cum.force_mem | |
7961 | && (TARGET_SH2E | |
7962 | ? ((mode) == BLKmode | |
7963 | ? ((cum.arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD | |
7964 | + int_size_in_bytes (type)) | |
7965 | <= NPARM_REGS (SImode) * UNITS_PER_WORD) | |
7966 | : ((sh_round_reg (cum, mode) | |
c43f4279 | 7967 | + sh_hard_regno_nregs (BASE_ARG_REG (mode), mode)) |
f6982a08 OE |
7968 | <= NPARM_REGS (mode))) |
7969 | : sh_round_reg (cum, mode) < NPARM_REGS (mode))); | |
7970 | } | |
7971 | ||
78a52f11 | 7972 | static int |
ef4bddc2 | 7973 | sh_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode, |
78a52f11 RH |
7974 | tree type, bool named ATTRIBUTE_UNUSED) |
7975 | { | |
d5cc9181 | 7976 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
78a52f11 RH |
7977 | int words = 0; |
7978 | ||
e1fab8ba | 7979 | if (sh_pass_in_reg_p (*cum, mode, type) |
d5dd0a62 | 7980 | && !TARGET_FPU_DOUBLE |
f6982a08 | 7981 | && (sh_round_reg (*cum, mode) |
78a52f11 | 7982 | + (mode != BLKmode |
f6982a08 OE |
7983 | ? CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD) |
7984 | : CEIL (int_size_in_bytes (type), UNITS_PER_WORD)) | |
78a52f11 | 7985 | > NPARM_REGS (mode))) |
f6982a08 | 7986 | words = NPARM_REGS (mode) - sh_round_reg (*cum, mode); |
78a52f11 | 7987 | |
78a52f11 RH |
7988 | return words * UNITS_PER_WORD; |
7989 | } | |
7990 | ||
7991 | ||
61f71b34 DD |
7992 | /* Define where to put the arguments to a function. |
7993 | Value is zero to push the argument on the stack, | |
7994 | or a hard register in which to store the argument. | |
7995 | ||
7996 | MODE is the argument's machine mode. | |
7997 | TYPE is the data type of the argument (as a tree). | |
7998 | This is null for libcalls where that information may | |
7999 | not be available. | |
8000 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
8001 | the preceding args and about the function being called. | |
8002 | NAMED is nonzero if this argument is a named parameter | |
8003 | (otherwise it is an extra parameter matching an ellipsis). | |
8004 | ||
8005 | On SH the first args are normally in registers | |
8006 | and the rest are pushed. Any arg that starts within the first | |
8007 | NPARM_REGS words is at least partially passed in a register unless | |
8008 | its data type forbids. */ | |
b64336b8 | 8009 | static rtx |
ef4bddc2 | 8010 | sh_function_arg (cumulative_args_t ca_v, machine_mode mode, |
b64336b8 | 8011 | const_tree type, bool named) |
61f71b34 | 8012 | { |
d5cc9181 JR |
8013 | CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); |
8014 | ||
e1fab8ba OE |
8015 | if (mode == VOIDmode) |
8016 | return ca->renesas_abi ? const1_rtx : const0_rtx; | |
61f71b34 | 8017 | |
e1fab8ba | 8018 | if (sh_pass_in_reg_p (*ca, mode, type) |
61f71b34 DD |
8019 | && (named || ! (TARGET_HITACHI || ca->renesas_abi))) |
8020 | { | |
8021 | int regno; | |
8022 | ||
8023 | if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN | |
f6982a08 | 8024 | && (! FUNCTION_ARG_SCmode_WART || (sh_round_reg (*ca, mode) & 1))) |
61f71b34 DD |
8025 | { |
8026 | rtx r1 = gen_rtx_EXPR_LIST (VOIDmode, | |
8027 | gen_rtx_REG (SFmode, | |
8028 | BASE_ARG_REG (mode) | |
f6982a08 | 8029 | + (sh_round_reg (*ca, mode) ^ 1)), |
61f71b34 | 8030 | const0_rtx); |
832a3292 KH |
8031 | rtx r2 = gen_rtx_EXPR_LIST (VOIDmode, |
8032 | gen_rtx_REG (SFmode, | |
8033 | BASE_ARG_REG (mode) | |
f6982a08 | 8034 | + ((sh_round_reg (*ca, mode) + 1) ^ 1)), |
832a3292 | 8035 | GEN_INT (4)); |
61f71b34 DD |
8036 | return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2)); |
8037 | } | |
8038 | ||
8039 | /* If the alignment of a DF value causes an SF register to be | |
8040 | skipped, we will use that skipped register for the next SF | |
8041 | value. */ | |
8042 | if ((TARGET_HITACHI || ca->renesas_abi) | |
8043 | && ca->free_single_fp_reg | |
8044 | && mode == SFmode) | |
8045 | return gen_rtx_REG (mode, ca->free_single_fp_reg); | |
8046 | ||
f6982a08 | 8047 | regno = (BASE_ARG_REG (mode) + sh_round_reg (*ca, mode)) |
61f71b34 | 8048 | ^ (mode == SFmode && TARGET_SH4 |
23d0939b | 8049 | && TARGET_LITTLE_ENDIAN |
61f71b34 DD |
8050 | && ! TARGET_HITACHI && ! ca->renesas_abi); |
8051 | return gen_rtx_REG (mode, regno); | |
8052 | ||
8053 | } | |
f676971a | 8054 | |
23d0939b | 8055 | return NULL_RTX; |
61f71b34 | 8056 | } |
f676971a | 8057 | |
61f71b34 DD |
8058 | /* Update the data in CUM to advance over an argument |
8059 | of mode MODE and data type TYPE. | |
8060 | (TYPE is null for libcalls where that information may not be | |
8061 | available.) */ | |
b64336b8 | 8062 | static void |
ef4bddc2 | 8063 | sh_function_arg_advance (cumulative_args_t ca_v, machine_mode mode, |
e1fab8ba | 8064 | const_tree type, bool named ATTRIBUTE_UNUSED) |
61f71b34 | 8065 | { |
d5cc9181 JR |
8066 | CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); |
8067 | ||
832a3292 | 8068 | if (ca->force_mem) |
df4bacab | 8069 | ca->force_mem = false; |
832a3292 KH |
8070 | |
8071 | if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE) | |
8072 | { | |
8073 | /* Note that we've used the skipped register. */ | |
8074 | if (mode == SFmode && ca->free_single_fp_reg) | |
8075 | { | |
8076 | ca->free_single_fp_reg = 0; | |
8077 | return; | |
8078 | } | |
8079 | /* When we have a DF after an SF, there's an SF register that get | |
8080 | skipped in order to align the DF value. We note this skipped | |
8081 | register, because the next SF value will use it, and not the | |
8082 | SF that follows the DF. */ | |
8083 | if (mode == DFmode | |
f6982a08 | 8084 | && sh_round_reg (*ca, DFmode) != sh_round_reg (*ca, SFmode)) |
832a3292 | 8085 | { |
f6982a08 | 8086 | ca->free_single_fp_reg = (sh_round_reg (*ca, SFmode) |
832a3292 KH |
8087 | + BASE_ARG_REG (mode)); |
8088 | } | |
8089 | } | |
8090 | ||
157371cf | 8091 | if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi) |
f6982a08 | 8092 | || sh_pass_in_reg_p (*ca, mode, type)) |
0983497f | 8093 | (ca->arg_count[(int) get_sh_arg_class (mode)] |
f6982a08 | 8094 | = (sh_round_reg (*ca, mode) |
832a3292 | 8095 | + (mode == BLKmode |
f6982a08 OE |
8096 | ? CEIL (int_size_in_bytes (type), UNITS_PER_WORD) |
8097 | : CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD)))); | |
61f71b34 DD |
8098 | } |
8099 | ||
61f71b34 DD |
8100 | /* The Renesas calling convention doesn't quite fit into this scheme since |
8101 | the address is passed like an invisible argument, but one that is always | |
8102 | passed in memory. */ | |
8103 | static rtx | |
cf277499 | 8104 | sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED) |
61f71b34 DD |
8105 | { |
8106 | if (TARGET_HITACHI || sh_attr_renesas_p (fndecl)) | |
23d0939b | 8107 | return NULL_RTX; |
61f71b34 DD |
8108 | return gen_rtx_REG (Pmode, 2); |
8109 | } | |
8110 | ||
d64728cf AS |
8111 | /* Worker function for TARGET_FUNCTION_VALUE. |
8112 | ||
8113 | For the SH, this is like LIBCALL_VALUE, except that we must change the | |
8114 | mode like PROMOTE_MODE does. | |
8115 | ??? PROMOTE_MODE is ignored for non-scalar types. The set of types | |
50fe8924 OE |
8116 | tested here has to be kept in sync with the one in |
8117 | explow.c:promote_mode. */ | |
d64728cf AS |
8118 | static rtx |
8119 | sh_function_value (const_tree valtype, | |
8120 | const_tree fn_decl_or_type, | |
8121 | bool outgoing ATTRIBUTE_UNUSED) | |
8122 | { | |
8123 | if (fn_decl_or_type | |
8124 | && !DECL_P (fn_decl_or_type)) | |
8125 | fn_decl_or_type = NULL; | |
8126 | ||
8127 | return gen_rtx_REG ( | |
8128 | ((GET_MODE_CLASS (TYPE_MODE (valtype)) == MODE_INT | |
8129 | && GET_MODE_SIZE (TYPE_MODE (valtype)) < 4 | |
8130 | && (TREE_CODE (valtype) == INTEGER_TYPE | |
8131 | || TREE_CODE (valtype) == ENUMERAL_TYPE | |
8132 | || TREE_CODE (valtype) == BOOLEAN_TYPE | |
8133 | || TREE_CODE (valtype) == REAL_TYPE | |
8134 | || TREE_CODE (valtype) == OFFSET_TYPE)) | |
8135 | && sh_promote_prototypes (fn_decl_or_type) | |
e1fab8ba | 8136 | ? SImode : TYPE_MODE (valtype)), |
d64728cf AS |
8137 | BASE_RETURN_VALUE_REG (TYPE_MODE (valtype))); |
8138 | } | |
8139 | ||
8140 | /* Worker function for TARGET_LIBCALL_VALUE. */ | |
d64728cf | 8141 | static rtx |
ef4bddc2 | 8142 | sh_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) |
d64728cf AS |
8143 | { |
8144 | return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG (mode)); | |
8145 | } | |
8146 | ||
e7a8f681 | 8147 | /* Return true if N is a possible register number of function value. */ |
e7a8f681 | 8148 | static bool |
d64728cf AS |
8149 | sh_function_value_regno_p (const unsigned int regno) |
8150 | { | |
e1fab8ba | 8151 | return regno == FIRST_RET_REG || (TARGET_SH2E && regno == FIRST_FP_RET_REG); |
d64728cf AS |
8152 | } |
8153 | ||
bd5bd7ac | 8154 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
61f71b34 | 8155 | static bool |
586de218 | 8156 | sh_return_in_memory (const_tree type, const_tree fndecl) |
61f71b34 | 8157 | { |
e1fab8ba OE |
8158 | return TYPE_MODE (type) == BLKmode |
8159 | || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl)) | |
8160 | && TREE_CODE (type) == RECORD_TYPE); | |
61f71b34 DD |
8161 | } |
8162 | ||
8163 | /* We actually emit the code in sh_expand_prologue. We used to use | |
8164 | a static variable to flag that we need to emit this code, but that | |
8165 | doesn't when inlining, when functions are deferred and then emitted | |
8166 | later. Fortunately, we already have two flags that are part of struct | |
8167 | function that tell if a function uses varargs or stdarg. */ | |
8168 | static void | |
d5cc9181 | 8169 | sh_setup_incoming_varargs (cumulative_args_t ca, |
ef4bddc2 | 8170 | machine_mode mode, |
49616835 JR |
8171 | tree type, |
8172 | int *pretend_arg_size, | |
cf277499 | 8173 | int second_time ATTRIBUTE_UNUSED) |
61f71b34 | 8174 | { |
e3b5732b | 8175 | gcc_assert (cfun->stdarg); |
49616835 JR |
8176 | if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)) |
8177 | { | |
8178 | int named_parm_regs, anon_parm_regs; | |
8179 | ||
f6982a08 | 8180 | named_parm_regs = (sh_round_reg (*get_cumulative_args (ca), mode) |
49616835 | 8181 | + (mode == BLKmode |
f6982a08 OE |
8182 | ? CEIL (int_size_in_bytes (type), UNITS_PER_WORD) |
8183 | : CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD))); | |
49616835 JR |
8184 | anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs; |
8185 | if (anon_parm_regs > 0) | |
8186 | *pretend_arg_size = anon_parm_regs * 4; | |
8187 | } | |
61f71b34 DD |
8188 | } |
8189 | ||
8190 | static bool | |
d5cc9181 | 8191 | sh_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) |
61f71b34 | 8192 | { |
e1fab8ba | 8193 | return false; |
61f71b34 DD |
8194 | } |
8195 | ||
8196 | static bool | |
d5cc9181 | 8197 | sh_pretend_outgoing_varargs_named (cumulative_args_t ca_v) |
61f71b34 | 8198 | { |
d5cc9181 JR |
8199 | CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); |
8200 | ||
e1fab8ba | 8201 | return ! (TARGET_HITACHI || ca->renesas_abi); |
61f71b34 DD |
8202 | } |
8203 | ||
8204 | ||
0d7e008e SC |
8205 | /* Define the offset between two registers, one to be eliminated, and |
8206 | the other its replacement, at the start of a routine. */ | |
0d7e008e | 8207 | int |
cf277499 | 8208 | initial_elimination_offset (int from, int to) |
0d7e008e | 8209 | { |
df4bacab | 8210 | const int regs_saved_rounding = 0; |
1245df60 | 8211 | int save_flags = target_flags; |
490dbac7 | 8212 | HARD_REG_SET live_regs_mask; |
fe3ad572 | 8213 | |
df4bacab | 8214 | int regs_saved = calc_live_regs (&live_regs_mask); |
8e87e161 | 8215 | |
df4bacab | 8216 | int total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding; |
1245df60 | 8217 | target_flags = save_flags; |
1a95a963 | 8218 | |
df4bacab | 8219 | int total_saved_regs_space = regs_saved + regs_saved_rounding; |
b9654711 | 8220 | |
96a2347e | 8221 | if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) |
df4bacab | 8222 | return total_saved_regs_space + total_auto_space; |
8aa2a305 | 8223 | |
0d7e008e | 8224 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
df4bacab | 8225 | return total_saved_regs_space + total_auto_space; |
8aa2a305 JW |
8226 | |
8227 | /* Initial gap between fp and sp is 0. */ | |
96a2347e | 8228 | if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
8aa2a305 JW |
8229 | return 0; |
8230 | ||
96a2347e KK |
8231 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
8232 | return rounded_frame_size (0); | |
8233 | ||
8234 | if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) | |
8235 | return rounded_frame_size (0); | |
8236 | ||
f5b9e7c9 | 8237 | gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM |
96a2347e KK |
8238 | && (to == HARD_FRAME_POINTER_REGNUM |
8239 | || to == STACK_POINTER_REGNUM)); | |
e1fab8ba | 8240 | return total_auto_space; |
0d7e008e | 8241 | } |
3217af3e KK |
8242 | |
8243 | /* Parse the -mfixed-range= option string. */ | |
8244 | void | |
8245 | sh_fix_range (const char *const_str) | |
8246 | { | |
3217af3e KK |
8247 | /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and |
8248 | REG2 are either register names or register numbers. The effect | |
8249 | of this option is to mark the registers in the range from REG1 to | |
8250 | REG2 as ``fixed'' so they won't be used by the compiler. */ | |
50fe8924 | 8251 | |
df4bacab | 8252 | char* str = strcpy ((char*)alloca (strlen (const_str) + 1), const_str); |
50fe8924 | 8253 | |
3217af3e KK |
8254 | while (1) |
8255 | { | |
df4bacab | 8256 | char* dash = strchr (str, '-'); |
3217af3e KK |
8257 | if (!dash) |
8258 | { | |
8259 | warning (0, "value of -mfixed-range must have form REG1-REG2"); | |
8260 | return; | |
8261 | } | |
8262 | *dash = '\0'; | |
df4bacab | 8263 | char* comma = strchr (dash + 1, ','); |
3217af3e KK |
8264 | if (comma) |
8265 | *comma = '\0'; | |
50fe8924 | 8266 | |
df4bacab | 8267 | int first = decode_reg_name (str); |
3217af3e KK |
8268 | if (first < 0) |
8269 | { | |
8270 | warning (0, "unknown register name: %s", str); | |
8271 | return; | |
8272 | } | |
50fe8924 | 8273 | |
df4bacab | 8274 | int last = decode_reg_name (dash + 1); |
3217af3e KK |
8275 | if (last < 0) |
8276 | { | |
8277 | warning (0, "unknown register name: %s", dash + 1); | |
8278 | return; | |
8279 | } | |
50fe8924 | 8280 | |
3217af3e | 8281 | *dash = '-'; |
50fe8924 | 8282 | |
3217af3e KK |
8283 | if (first > last) |
8284 | { | |
8285 | warning (0, "%s-%s is an empty range", str, dash + 1); | |
8286 | return; | |
8287 | } | |
50fe8924 | 8288 | |
df4bacab | 8289 | for (int i = first; i <= last; ++i) |
3217af3e KK |
8290 | fixed_regs[i] = call_used_regs[i] = 1; |
8291 | ||
8292 | if (!comma) | |
8293 | break; | |
8294 | ||
8295 | *comma = ','; | |
8296 | str = comma + 1; | |
8297 | } | |
8298 | } | |
8aa2a305 | 8299 | \f |
a6ab9fc0 | 8300 | /* Insert any deferred function attributes from earlier pragmas. */ |
12a68f1f | 8301 | static void |
cf277499 | 8302 | sh_insert_attributes (tree node, tree *attributes) |
157131d7 | 8303 | { |
a6ab9fc0 | 8304 | if (TREE_CODE (node) != FUNCTION_DECL) |
157131d7 SC |
8305 | return; |
8306 | ||
8307 | /* We are only interested in fields. */ | |
6615c446 | 8308 | if (!DECL_P (node)) |
157131d7 SC |
8309 | return; |
8310 | ||
a6ab9fc0 R |
8311 | /* Append the attributes to the deferred attributes. */ |
8312 | *sh_deferred_function_attributes_tail = *attributes; | |
df4bacab | 8313 | tree attrs = sh_deferred_function_attributes; |
a6ab9fc0 R |
8314 | if (!attrs) |
8315 | return; | |
8316 | ||
8317 | /* Some attributes imply or require the interrupt attribute. */ | |
8318 | if (!lookup_attribute ("interrupt_handler", attrs) | |
8319 | && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node))) | |
8320 | { | |
8321 | /* If we have a trapa_handler, but no interrupt_handler attribute, | |
8322 | insert an interrupt_handler attribute. */ | |
8323 | if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE) | |
8324 | /* We can't use sh_pr_interrupt here because that's not in the | |
8325 | java frontend. */ | |
8326 | attrs | |
8327 | = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs); | |
561642fa AP |
8328 | /* However, for sp_switch, trap_exit, nosave_low_regs and resbank, |
8329 | if the interrupt attribute is missing, we ignore the attribute | |
8330 | and warn. */ | |
a6ab9fc0 R |
8331 | else if (lookup_attribute ("sp_switch", attrs) |
8332 | || lookup_attribute ("trap_exit", attrs) | |
561642fa AP |
8333 | || lookup_attribute ("nosave_low_regs", attrs) |
8334 | || lookup_attribute ("resbank", attrs)) | |
a6ab9fc0 R |
8335 | { |
8336 | tree *tail; | |
8337 | ||
8338 | for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs)) | |
8339 | { | |
8340 | if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs)) | |
8341 | || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs)) | |
561642fa AP |
8342 | || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs)) |
8343 | || is_attribute_p ("resbank", TREE_PURPOSE (attrs))) | |
a6ab9fc0 | 8344 | warning (OPT_Wattributes, |
29d08eba JM |
8345 | "%qE attribute only applies to interrupt functions", |
8346 | TREE_PURPOSE (attrs)); | |
a6ab9fc0 R |
8347 | else |
8348 | { | |
8349 | *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE, | |
8350 | NULL_TREE); | |
8351 | tail = &TREE_CHAIN (*tail); | |
8352 | } | |
8353 | } | |
8354 | attrs = *attributes; | |
8355 | } | |
8356 | } | |
8357 | ||
8358 | /* Install the processed list. */ | |
8359 | *attributes = attrs; | |
8360 | ||
8361 | /* Clear deferred attributes. */ | |
8362 | sh_deferred_function_attributes = NULL_TREE; | |
8363 | sh_deferred_function_attributes_tail = &sh_deferred_function_attributes; | |
157131d7 SC |
8364 | |
8365 | return; | |
8366 | } | |
8367 | ||
845f4111 | 8368 | /*------------------------------------------------------------------------------ |
86cf62b8 | 8369 | Target specific attributes |
845f4111 OE |
8370 | Supported attributes are: |
8371 | ||
8372 | * interrupt_handler | |
8373 | Specifies this function is an interrupt handler. | |
8374 | ||
8375 | * trapa_handler | |
8376 | Like interrupt_handler, but don't save all registers. | |
8377 | ||
8378 | * sp_switch | |
8379 | Specifies an alternate stack for an interrupt handler to run on. | |
8380 | ||
8381 | * trap_exit | |
8382 | Use a trapa to exit an interrupt function instead of rte. | |
8383 | ||
8384 | * nosave_low_regs | |
8385 | Don't save r0..r7 in an interrupt handler function. | |
8386 | This is useful on SH3* and SH4*, which have a separate set of low | |
8387 | regs for user and privileged modes. | |
8388 | This is mainly to be used for non-reentrant interrupt handlers (i.e. | |
8389 | those that run with interrupts disabled and thus can't be | |
8390 | interrupted thenselves). | |
8391 | ||
8392 | * renesas | |
8393 | Use Renesas calling/layout conventions (functions and structures). | |
8394 | ||
8395 | * resbank | |
8396 | In case of an interrupt handler function, use a register bank to | |
8397 | save registers R0-R14, MACH, MACL, GBR and PR. | |
8398 | This is available only on SH2A targets. | |
8399 | ||
8400 | * function_vector | |
8401 | Declares a function to be called using the TBR relative addressing | |
8402 | mode. Takes an argument that specifies the slot number in the table | |
8403 | where this function can be looked up by the JSR/N @@(disp8,TBR) insn. | |
61f71b34 | 8404 | */ |
4408efce | 8405 | |
561642fa AP |
8406 | /* Handle a 'resbank' attribute. */ |
8407 | static tree | |
8408 | sh_handle_resbank_handler_attribute (tree * node, tree name, | |
50fe8924 OE |
8409 | tree args ATTRIBUTE_UNUSED, |
8410 | int flags ATTRIBUTE_UNUSED, | |
8411 | bool * no_add_attrs) | |
561642fa AP |
8412 | { |
8413 | if (!TARGET_SH2A) | |
8414 | { | |
29d08eba | 8415 | warning (OPT_Wattributes, "%qE attribute is supported only for SH2A", |
50fe8924 | 8416 | name); |
561642fa AP |
8417 | *no_add_attrs = true; |
8418 | } | |
8419 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
8420 | { | |
29d08eba | 8421 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
50fe8924 | 8422 | name); |
561642fa AP |
8423 | *no_add_attrs = true; |
8424 | } | |
8425 | ||
8426 | return NULL_TREE; | |
8427 | } | |
8428 | ||
91d231cb JM |
8429 | /* Handle an "interrupt_handler" attribute; arguments as in |
8430 | struct attribute_spec.handler. */ | |
8431 | static tree | |
cf277499 | 8432 | sh_handle_interrupt_handler_attribute (tree *node, tree name, |
50fe8924 OE |
8433 | tree args ATTRIBUTE_UNUSED, |
8434 | int flags ATTRIBUTE_UNUSED, | |
8435 | bool *no_add_attrs) | |
91d231cb JM |
8436 | { |
8437 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
4408efce | 8438 | { |
29d08eba | 8439 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
50fe8924 | 8440 | name); |
91d231cb | 8441 | *no_add_attrs = true; |
4408efce JL |
8442 | } |
8443 | ||
91d231cb JM |
8444 | return NULL_TREE; |
8445 | } | |
8446 | ||
561642fa AP |
8447 | /* Handle an 'function_vector' attribute; arguments as in |
8448 | struct attribute_spec.handler. */ | |
8449 | static tree | |
8450 | sh2a_handle_function_vector_handler_attribute (tree * node, tree name, | |
50fe8924 OE |
8451 | tree args ATTRIBUTE_UNUSED, |
8452 | int flags ATTRIBUTE_UNUSED, | |
8453 | bool * no_add_attrs) | |
561642fa AP |
8454 | { |
8455 | if (!TARGET_SH2A) | |
8456 | { | |
29d08eba | 8457 | warning (OPT_Wattributes, "%qE attribute only applies to SH2A", |
50fe8924 | 8458 | name); |
561642fa AP |
8459 | *no_add_attrs = true; |
8460 | } | |
8461 | else if (TREE_CODE (*node) != FUNCTION_DECL) | |
8462 | { | |
29d08eba | 8463 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
50fe8924 | 8464 | name); |
561642fa AP |
8465 | *no_add_attrs = true; |
8466 | } | |
8467 | else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST) | |
8468 | { | |
8469 | /* The argument must be a constant integer. */ | |
8470 | warning (OPT_Wattributes, | |
50fe8924 OE |
8471 | "%qE attribute argument not an integer constant", |
8472 | name); | |
561642fa AP |
8473 | *no_add_attrs = true; |
8474 | } | |
8475 | else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255) | |
8476 | { | |
8477 | /* The argument value must be between 0 to 255. */ | |
8478 | warning (OPT_Wattributes, | |
50fe8924 OE |
8479 | "%qE attribute argument should be between 0 to 255", |
8480 | name); | |
561642fa AP |
8481 | *no_add_attrs = true; |
8482 | } | |
8483 | return NULL_TREE; | |
8484 | } | |
8485 | ||
aaf701c5 | 8486 | /* Returns true if current function has been assigned the attribute |
561642fa | 8487 | 'function_vector'. */ |
aaf701c5 | 8488 | bool |
561642fa AP |
8489 | sh2a_is_function_vector_call (rtx x) |
8490 | { | |
8491 | if (GET_CODE (x) == SYMBOL_REF | |
8492 | && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION)) | |
8493 | { | |
8494 | tree tr = SYMBOL_REF_DECL (x); | |
8495 | ||
8496 | if (sh2a_function_vector_p (tr)) | |
aaf701c5 | 8497 | return true; |
561642fa AP |
8498 | } |
8499 | ||
aaf701c5 | 8500 | return false; |
561642fa AP |
8501 | } |
8502 | ||
dd5a833e | 8503 | /* Returns the function vector number, if the attribute |
561642fa AP |
8504 | 'function_vector' is assigned, otherwise returns zero. */ |
8505 | int | |
8506 | sh2a_get_function_vector_number (rtx x) | |
8507 | { | |
561642fa AP |
8508 | if ((GET_CODE (x) == SYMBOL_REF) |
8509 | && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION)) | |
8510 | { | |
df4bacab | 8511 | tree t = SYMBOL_REF_DECL (x); |
561642fa AP |
8512 | |
8513 | if (TREE_CODE (t) != FUNCTION_DECL) | |
50fe8924 | 8514 | return 0; |
561642fa | 8515 | |
df4bacab OE |
8516 | for (tree list = SH_ATTRIBUTES (t); list; list = TREE_CHAIN (list)) |
8517 | if (is_attribute_p ("function_vector", TREE_PURPOSE (list))) | |
8518 | return TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list))); | |
561642fa AP |
8519 | |
8520 | return 0; | |
8521 | } | |
8522 | else | |
8523 | return 0; | |
8524 | } | |
8525 | ||
91d231cb JM |
8526 | /* Handle an "sp_switch" attribute; arguments as in |
8527 | struct attribute_spec.handler. */ | |
8528 | static tree | |
cf277499 SB |
8529 | sh_handle_sp_switch_attribute (tree *node, tree name, tree args, |
8530 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
91d231cb JM |
8531 | { |
8532 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
8533 | { | |
29d08eba JM |
8534 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
8535 | name); | |
91d231cb JM |
8536 | *no_add_attrs = true; |
8537 | } | |
91d231cb JM |
8538 | else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST) |
8539 | { | |
4408efce | 8540 | /* The argument must be a constant string. */ |
29d08eba JM |
8541 | warning (OPT_Wattributes, "%qE attribute argument not a string constant", |
8542 | name); | |
91d231cb JM |
8543 | *no_add_attrs = true; |
8544 | } | |
4408efce | 8545 | |
91d231cb JM |
8546 | return NULL_TREE; |
8547 | } | |
8548 | ||
8549 | /* Handle an "trap_exit" attribute; arguments as in | |
8550 | struct attribute_spec.handler. */ | |
8551 | static tree | |
cf277499 SB |
8552 | sh_handle_trap_exit_attribute (tree *node, tree name, tree args, |
8553 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
91d231cb JM |
8554 | { |
8555 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
8556 | { | |
29d08eba JM |
8557 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
8558 | name); | |
91d231cb JM |
8559 | *no_add_attrs = true; |
8560 | } | |
a6ab9fc0 R |
8561 | /* The argument specifies a trap number to be used in a trapa instruction |
8562 | at function exit (instead of an rte instruction). */ | |
91d231cb JM |
8563 | else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST) |
8564 | { | |
4408efce | 8565 | /* The argument must be a constant integer. */ |
29d08eba JM |
8566 | warning (OPT_Wattributes, "%qE attribute argument not an " |
8567 | "integer constant", name); | |
91d231cb JM |
8568 | *no_add_attrs = true; |
8569 | } | |
318881c0 | 8570 | |
91d231cb | 8571 | return NULL_TREE; |
4408efce JL |
8572 | } |
8573 | ||
61f71b34 | 8574 | static tree |
cf277499 SB |
8575 | sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED, |
8576 | tree name ATTRIBUTE_UNUSED, | |
8577 | tree args ATTRIBUTE_UNUSED, | |
8578 | int flags ATTRIBUTE_UNUSED, | |
8579 | bool *no_add_attrs ATTRIBUTE_UNUSED) | |
61f71b34 DD |
8580 | { |
8581 | return NULL_TREE; | |
8582 | } | |
8583 | ||
8584 | /* True if __attribute__((renesas)) or -mrenesas. */ | |
aaf701c5 | 8585 | bool |
586de218 | 8586 | sh_attr_renesas_p (const_tree td) |
61f71b34 DD |
8587 | { |
8588 | if (TARGET_HITACHI) | |
aaf701c5 | 8589 | return true; |
23d0939b | 8590 | if (td == NULL_TREE) |
aaf701c5 | 8591 | return false; |
61f71b34 DD |
8592 | if (DECL_P (td)) |
8593 | td = TREE_TYPE (td); | |
a11c004b | 8594 | if (td == error_mark_node) |
aaf701c5 | 8595 | return false; |
df4bacab | 8596 | return lookup_attribute ("renesas", TYPE_ATTRIBUTES (td)) != NULL_TREE; |
61f71b34 DD |
8597 | } |
8598 | ||
8599 | /* True if __attribute__((renesas)) or -mrenesas, for the current | |
8600 | function. */ | |
aaf701c5 | 8601 | bool |
cf277499 | 8602 | sh_cfun_attr_renesas_p (void) |
61f71b34 DD |
8603 | { |
8604 | return sh_attr_renesas_p (current_function_decl); | |
8605 | } | |
8606 | ||
50fe8924 OE |
8607 | /* Returns true if the current function has the "interrupt_handler" |
8608 | attribute set. */ | |
aaf701c5 | 8609 | bool |
cf277499 | 8610 | sh_cfun_interrupt_handler_p (void) |
e3ba8d11 R |
8611 | { |
8612 | return (lookup_attribute ("interrupt_handler", | |
8613 | DECL_ATTRIBUTES (current_function_decl)) | |
8614 | != NULL_TREE); | |
8615 | } | |
bcc8cc82 | 8616 | |
aaf701c5 | 8617 | /* Returns true if FUNC has been assigned the attribute |
561642fa | 8618 | "function_vector". */ |
aaf701c5 | 8619 | bool |
561642fa AP |
8620 | sh2a_function_vector_p (tree func) |
8621 | { | |
561642fa | 8622 | if (TREE_CODE (func) != FUNCTION_DECL) |
aaf701c5 | 8623 | return false; |
561642fa | 8624 | |
df4bacab OE |
8625 | for (tree list = SH_ATTRIBUTES (func); list; list = TREE_CHAIN (list)) |
8626 | if (is_attribute_p ("function_vector", TREE_PURPOSE (list))) | |
8627 | return true; | |
561642fa | 8628 | |
aaf701c5 | 8629 | return false; |
561642fa AP |
8630 | } |
8631 | ||
50fe8924 | 8632 | /* Returns true if given tree has the "resbank" attribute set. */ |
aaf701c5 | 8633 | bool |
561642fa AP |
8634 | sh_cfun_resbank_handler_p (void) |
8635 | { | |
8636 | return ((lookup_attribute ("resbank", | |
50fe8924 OE |
8637 | DECL_ATTRIBUTES (current_function_decl)) |
8638 | != NULL_TREE) | |
8639 | && (lookup_attribute ("interrupt_handler", | |
8640 | DECL_ATTRIBUTES (current_function_decl)) | |
8641 | != NULL_TREE) && TARGET_SH2A); | |
561642fa AP |
8642 | } |
8643 | ||
d16202ba | 8644 | /* Returns true if the current function has a "trap_exit" attribute set. */ |
d16202ba OE |
8645 | bool |
8646 | sh_cfun_trap_exit_p (void) | |
8647 | { | |
8648 | return lookup_attribute ("trap_exit", DECL_ATTRIBUTES (current_function_decl)) | |
8649 | != NULL_TREE; | |
8650 | } | |
8651 | ||
8d932be3 | 8652 | /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */ |
8d932be3 RS |
8653 | static const char * |
8654 | sh_check_pch_target_flags (int old_flags) | |
8655 | { | |
c0fb94d7 RS |
8656 | if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3 |
8657 | | MASK_SH_E | MASK_HARD_SH4 | |
8658 | | MASK_FPU_SINGLE | MASK_SH4)) | |
8659 | return _("created and used with different architectures / ABIs"); | |
8660 | if ((old_flags ^ target_flags) & MASK_HITACHI) | |
8661 | return _("created and used with different ABIs"); | |
8662 | if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN) | |
8663 | return _("created and used with different endianness"); | |
bcc8cc82 | 8664 | return NULL; |
bcc8cc82 | 8665 | } |
0d7e008e | 8666 | \f |
8aa2a305 | 8667 | /* Predicates used by the templates. */ |
0d7e008e | 8668 | |
aaf701c5 | 8669 | /* Returns true if OP is MACL, MACH or PR. The input must be a REG rtx. |
8aa2a305 | 8670 | Used only in general_movsrc_operand. */ |
aaf701c5 | 8671 | bool |
ef4bddc2 | 8672 | system_reg_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) |
0d7e008e | 8673 | { |
8aa2a305 | 8674 | switch (REGNO (op)) |
0d7e008e | 8675 | { |
8aa2a305 JW |
8676 | case PR_REG: |
8677 | case MACL_REG: | |
8678 | case MACH_REG: | |
aaf701c5 | 8679 | return true; |
0d7e008e | 8680 | } |
aaf701c5 | 8681 | return false; |
0d7e008e | 8682 | } |
0d7e008e | 8683 | |
aaf701c5 | 8684 | /* Returns true if OP is a floating point value with value 0.0. */ |
aaf701c5 | 8685 | bool |
cf277499 | 8686 | fp_zero_operand (rtx op) |
d3ae8277 | 8687 | { |
1a95a963 | 8688 | if (GET_MODE (op) != SFmode) |
aaf701c5 | 8689 | return false; |
1a95a963 | 8690 | |
df4bacab | 8691 | const REAL_VALUE_TYPE* r = CONST_DOUBLE_REAL_VALUE (op); |
34a72c33 | 8692 | return real_equal (r, &dconst0) && ! REAL_VALUE_MINUS_ZERO (*r); |
d3ae8277 SC |
8693 | } |
8694 | ||
aaf701c5 | 8695 | /* Returns true if OP is a floating point value with value 1.0. */ |
aaf701c5 | 8696 | bool |
cf277499 | 8697 | fp_one_operand (rtx op) |
d3ae8277 | 8698 | { |
1a95a963 | 8699 | if (GET_MODE (op) != SFmode) |
aaf701c5 | 8700 | return false; |
1a95a963 | 8701 | |
34a72c33 | 8702 | return real_equal (CONST_DOUBLE_REAL_VALUE (op), &dconst1); |
d3ae8277 | 8703 | } |
1245df60 | 8704 | |
50fe8924 | 8705 | /* Return the TLS type for TLS symbols. */ |
81f40b79 | 8706 | enum tls_model |
ef4bddc2 | 8707 | tls_symbolic_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) |
463f02cd | 8708 | { |
463f02cd | 8709 | if (GET_CODE (op) != SYMBOL_REF) |
81f40b79 | 8710 | return TLS_MODEL_NONE; |
675ff4c7 | 8711 | return SYMBOL_REF_TLS_MODEL (op); |
463f02cd | 8712 | } |
1245df60 | 8713 | \f |
33f7f353 | 8714 | /* Return the destination address of a branch. */ |
318881c0 | 8715 | static int |
cf277499 | 8716 | branch_dest (rtx branch) |
1245df60 | 8717 | { |
33f7f353 | 8718 | rtx dest = SET_SRC (PATTERN (branch)); |
1245df60 R |
8719 | |
8720 | if (GET_CODE (dest) == IF_THEN_ELSE) | |
8721 | dest = XEXP (dest, 1); | |
df4bacab OE |
8722 | |
8723 | return INSN_ADDRESSES (INSN_UID (XEXP (dest, 0))); | |
1245df60 | 8724 | } |
a55e9d2b | 8725 | \f |
5e7a8ee0 | 8726 | /* Return nonzero if REG is not used after INSN. |
a55e9d2b | 8727 | We assume REG is a reload reg, and therefore does |
8b760293 | 8728 | not live past labels. It may live past calls or jumps though. */ |
aaf701c5 | 8729 | bool |
b32d5189 | 8730 | reg_unused_after (rtx reg, rtx_insn *insn) |
a55e9d2b | 8731 | { |
a55e9d2b RK |
8732 | /* If the reg is set by this instruction, then it is safe for our |
8733 | case. Disregard the case where this is a store to memory, since | |
8734 | we are checking a register used in the store address. */ | |
df4bacab | 8735 | rtx set = single_set (insn); |
f3536097 | 8736 | if (set && !MEM_P (SET_DEST (set)) |
a55e9d2b | 8737 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) |
aaf701c5 | 8738 | return true; |
a55e9d2b | 8739 | |
318881c0 | 8740 | while ((insn = NEXT_INSN (insn))) |
a55e9d2b | 8741 | { |
ec8e098d PB |
8742 | if (!INSN_P (insn)) |
8743 | continue; | |
8744 | ||
df4bacab | 8745 | rtx_code code = GET_CODE (insn); |
8783b15e | 8746 | |
c8f6f18d RK |
8747 | #if 0 |
8748 | /* If this is a label that existed before reload, then the register | |
2eff0b9d | 8749 | is dead here. However, if this is a label added by reorg, then |
c8f6f18d RK |
8750 | the register may still be live here. We can't tell the difference, |
8751 | so we just ignore labels completely. */ | |
8783b15e | 8752 | if (code == CODE_LABEL) |
a55e9d2b | 8753 | return 1; |
c8f6f18d RK |
8754 | /* else */ |
8755 | #endif | |
a55e9d2b | 8756 | |
8b760293 | 8757 | if (code == JUMP_INSN) |
aaf701c5 | 8758 | return false; |
8b760293 | 8759 | |
8783b15e RK |
8760 | /* If this is a sequence, we must handle them all at once. |
8761 | We could have for instance a call that sets the target register, | |
e03f5d43 | 8762 | and an insn in a delay slot that uses the register. In this case, |
8783b15e | 8763 | we must return 0. */ |
8b760293 | 8764 | else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) |
a55e9d2b | 8765 | { |
e8a54173 | 8766 | rtx_sequence *seq = as_a <rtx_sequence *> (PATTERN (insn)); |
df4bacab | 8767 | bool retval = false; |
8783b15e | 8768 | |
df4bacab | 8769 | for (int i = 0; i < seq->len (); i++) |
8783b15e | 8770 | { |
e8a54173 | 8771 | rtx_insn *this_insn = seq->insn (i); |
8783b15e RK |
8772 | rtx set = single_set (this_insn); |
8773 | ||
f3536097 | 8774 | if (CALL_P (this_insn)) |
8783b15e | 8775 | code = CALL_INSN; |
f3536097 | 8776 | else if (JUMP_P (this_insn)) |
38f35781 JW |
8777 | { |
8778 | if (INSN_ANNULLED_BRANCH_P (this_insn)) | |
aaf701c5 | 8779 | return false; |
38f35781 JW |
8780 | code = JUMP_INSN; |
8781 | } | |
a55e9d2b | 8782 | |
8783b15e | 8783 | if (set && reg_overlap_mentioned_p (reg, SET_SRC (set))) |
aaf701c5 | 8784 | return false; |
8783b15e RK |
8785 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) |
8786 | { | |
f3536097 | 8787 | if (!MEM_P (SET_DEST (set))) |
aaf701c5 | 8788 | retval = true; |
8783b15e | 8789 | else |
aaf701c5 | 8790 | return false; |
8783b15e | 8791 | } |
23d0939b | 8792 | if (set == NULL_RTX |
8783b15e | 8793 | && reg_overlap_mentioned_p (reg, PATTERN (this_insn))) |
aaf701c5 | 8794 | return false; |
8783b15e | 8795 | } |
df4bacab | 8796 | if (retval) |
aaf701c5 | 8797 | return true; |
38f35781 | 8798 | else if (code == JUMP_INSN) |
aaf701c5 | 8799 | return false; |
8783b15e | 8800 | } |
a55e9d2b | 8801 | |
df4bacab | 8802 | rtx set = single_set (insn); |
ec8e098d | 8803 | if (set && reg_overlap_mentioned_p (reg, SET_SRC (set))) |
aaf701c5 | 8804 | return false; |
ec8e098d | 8805 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) |
f3536097 | 8806 | return !MEM_P (SET_DEST (set)); |
df4bacab | 8807 | if (set == NULL && reg_overlap_mentioned_p (reg, PATTERN (insn))) |
aaf701c5 | 8808 | return false; |
8783b15e | 8809 | |
62164eb4 | 8810 | if (code == CALL_INSN && call_really_used_regs[REGNO (reg)]) |
aaf701c5 | 8811 | return true; |
a55e9d2b | 8812 | } |
aaf701c5 | 8813 | return true; |
a55e9d2b | 8814 | } |
225e4f43 | 8815 | \f |
225e4f43 | 8816 | |
f031c344 OE |
8817 | static GTY(()) rtx t_reg_rtx; |
8818 | rtx | |
8819 | get_t_reg_rtx (void) | |
8820 | { | |
8821 | if (! t_reg_rtx) | |
8822 | t_reg_rtx = gen_rtx_REG (SImode, T_REG); | |
8823 | return t_reg_rtx; | |
8824 | } | |
8825 | ||
24c2fde2 RH |
8826 | static GTY(()) tree fpscr_values; |
8827 | ||
8828 | static void | |
8829 | emit_fpu_switch (rtx scratch, int index) | |
8830 | { | |
24c2fde2 RH |
8831 | if (fpscr_values == NULL) |
8832 | { | |
df4bacab | 8833 | tree t = build_index_type (integer_one_node); |
24c2fde2 | 8834 | t = build_array_type (integer_type_node, t); |
4c4bde29 AH |
8835 | t = build_decl (BUILTINS_LOCATION, |
8836 | VAR_DECL, get_identifier ("__fpscr_values"), t); | |
24c2fde2 RH |
8837 | DECL_ARTIFICIAL (t) = 1; |
8838 | DECL_IGNORED_P (t) = 1; | |
8839 | DECL_EXTERNAL (t) = 1; | |
8840 | TREE_STATIC (t) = 1; | |
a5f5c6be | 8841 | TREE_PUBLIC (t) = 1; |
24c2fde2 RH |
8842 | TREE_USED (t) = 1; |
8843 | ||
8844 | fpscr_values = t; | |
8845 | } | |
8846 | ||
df4bacab | 8847 | rtx src = DECL_RTL (fpscr_values); |
b3a13419 | 8848 | if (!can_create_pseudo_p ()) |
24c2fde2 RH |
8849 | { |
8850 | emit_move_insn (scratch, XEXP (src, 0)); | |
8851 | if (index != 0) | |
8852 | emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4))); | |
fe3e478f | 8853 | src = adjust_automodify_address (src, SImode, scratch, index * 4); |
24c2fde2 RH |
8854 | } |
8855 | else | |
fe3e478f | 8856 | src = adjust_address (src, SImode, index * 4); |
24c2fde2 | 8857 | |
fe3e478f | 8858 | emit_insn (gen_lds_fpscr (src)); |
24c2fde2 | 8859 | } |
225e4f43 | 8860 | \f |
cf277499 | 8861 | static rtx get_free_reg (HARD_REG_SET); |
9f09b1f2 R |
8862 | |
8863 | /* This function returns a register to use to load the address to load | |
8864 | the fpscr from. Currently it always returns r1 or r7, but when we are | |
8865 | able to use pseudo registers after combine, or have a better mechanism | |
8866 | for choosing a register, it should be done here. */ | |
8867 | /* REGS_LIVE is the liveness information for the point for which we | |
8868 | need this allocation. In some bare-bones exit blocks, r1 is live at the | |
8869 | start. We can even have all of r0..r3 being live: | |
8870 | __complex__ long long f (double d) { if (d == 0) return 2; else return 3; } | |
8871 | INSN before which new insns are placed with will clobber the register | |
8872 | we return. If a basic block consists only of setting the return value | |
8873 | register to a pseudo and using that register, the return value is not | |
8874 | live before or after this block, yet we we'll insert our insns right in | |
8875 | the middle. */ | |
9f09b1f2 | 8876 | static rtx |
cf277499 | 8877 | get_free_reg (HARD_REG_SET regs_live) |
225e4f43 | 8878 | { |
9f09b1f2 R |
8879 | if (! TEST_HARD_REG_BIT (regs_live, 1)) |
8880 | return gen_rtx_REG (Pmode, 1); | |
225e4f43 | 8881 | |
42db504c | 8882 | /* Hard reg 1 is live; since this is a small register classes target, |
9f09b1f2 | 8883 | there shouldn't be anything but a jump before the function end. */ |
f5b9e7c9 NS |
8884 | gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7)); |
8885 | return gen_rtx_REG (Pmode, 7); | |
9f09b1f2 | 8886 | } |
225e4f43 | 8887 | |
f676971a | 8888 | /* This function will set the fpscr from memory. |
9f09b1f2 R |
8889 | MODE is the mode we are setting it to. */ |
8890 | void | |
cf277499 | 8891 | fpscr_set_from_mem (int mode, HARD_REG_SET regs_live) |
9f09b1f2 | 8892 | { |
81f40b79 | 8893 | enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode; |
24c2fde2 | 8894 | enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE); |
9f09b1f2 | 8895 | |
df4bacab | 8896 | rtx addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX; |
24c2fde2 | 8897 | emit_fpu_switch (addr_reg, fp_mode == norm_mode); |
225e4f43 | 8898 | } |
9342c0c4 R |
8899 | |
8900 | /* Is the given character a logical line separator for the assembler? */ | |
8901 | #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR | |
980d8882 | 8902 | #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';') |
9342c0c4 R |
8903 | #endif |
8904 | ||
83d88a6d | 8905 | static bool |
b32d5189 | 8906 | sequence_insn_p (rtx_insn *insn) |
83d88a6d | 8907 | { |
df4bacab | 8908 | rtx_insn* prev = PREV_INSN (insn); |
83d88a6d OE |
8909 | if (prev == NULL) |
8910 | return false; | |
8911 | ||
df4bacab | 8912 | rtx_insn* next = NEXT_INSN (prev); |
83d88a6d OE |
8913 | if (next == NULL) |
8914 | return false; | |
8915 | ||
312f9b9d | 8916 | return INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE; |
83d88a6d OE |
8917 | } |
8918 | ||
9342c0c4 | 8919 | int |
6cb7eb41 | 8920 | sh_insn_length_adjustment (rtx_insn *insn) |
9342c0c4 R |
8921 | { |
8922 | /* Instructions with unfilled delay slots take up an extra two bytes for | |
8923 | the nop in the delay slot. */ | |
f3536097 | 8924 | if (((NONJUMP_INSN_P (insn) |
c1b92d09 R |
8925 | && GET_CODE (PATTERN (insn)) != USE |
8926 | && GET_CODE (PATTERN (insn)) != CLOBBER) | |
39718607 | 8927 | || CALL_P (insn) || JUMP_P (insn)) |
83d88a6d | 8928 | && ! sequence_insn_p (insn) |
9342c0c4 R |
8929 | && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES) |
8930 | return 2; | |
8931 | ||
f05911fb OE |
8932 | /* Increase the insn length of a cbranch without a delay slot insn to |
8933 | force a delay slot which will be stuffed with a nop. */ | |
8934 | if (TARGET_CBRANCH_FORCE_DELAY_SLOT && TARGET_SH2 | |
8935 | && JUMP_P (insn) && get_attr_type (insn) == TYPE_CBRANCH | |
83d88a6d | 8936 | && ! sequence_insn_p (insn)) |
3a8699c7 AO |
8937 | return 2; |
8938 | ||
9342c0c4 | 8939 | /* sh-dsp parallel processing insn take four bytes instead of two. */ |
f676971a | 8940 | |
f3536097 | 8941 | if (NONJUMP_INSN_P (insn)) |
9342c0c4 R |
8942 | { |
8943 | int sum = 0; | |
8944 | rtx body = PATTERN (insn); | |
0a2aaacc | 8945 | const char *templ; |
8ceaac3c | 8946 | char c; |
23d0939b | 8947 | bool maybe_label = true; |
9342c0c4 R |
8948 | |
8949 | if (GET_CODE (body) == ASM_INPUT) | |
0a2aaacc | 8950 | templ = XSTR (body, 0); |
9342c0c4 | 8951 | else if (asm_noperands (body) >= 0) |
0a2aaacc | 8952 | templ |
343d66ad | 8953 | = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL); |
9342c0c4 R |
8954 | else |
8955 | return 0; | |
8956 | do | |
8957 | { | |
8958 | int ppi_adjust = 0; | |
8959 | ||
8960 | do | |
0a2aaacc | 8961 | c = *templ++; |
9342c0c4 R |
8962 | while (c == ' ' || c == '\t'); |
8963 | /* all sh-dsp parallel-processing insns start with p. | |
8964 | The only non-ppi sh insn starting with p is pref. | |
8965 | The only ppi starting with pr is prnd. */ | |
0a2aaacc | 8966 | if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2)) |
9342c0c4 R |
8967 | ppi_adjust = 2; |
8968 | /* The repeat pseudo-insn expands two three insns, a total of | |
8969 | six bytes in size. */ | |
8970 | else if ((c == 'r' || c == 'R') | |
0a2aaacc | 8971 | && ! strncasecmp ("epeat", templ, 5)) |
9342c0c4 | 8972 | ppi_adjust = 4; |
980d8882 | 8973 | while (c && c != '\n' |
0a2aaacc | 8974 | && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ)) |
9342c0c4 R |
8975 | { |
8976 | /* If this is a label, it is obviously not a ppi insn. */ | |
8977 | if (c == ':' && maybe_label) | |
8978 | { | |
8979 | ppi_adjust = 0; | |
8980 | break; | |
8981 | } | |
8982 | else if (c == '\'' || c == '"') | |
23d0939b | 8983 | maybe_label = false; |
0a2aaacc | 8984 | c = *templ++; |
9342c0c4 R |
8985 | } |
8986 | sum += ppi_adjust; | |
8987 | maybe_label = c != ':'; | |
8988 | } | |
8989 | while (c); | |
8990 | return sum; | |
8991 | } | |
8992 | return 0; | |
8993 | } | |
1a66cd67 | 8994 | \f |
cdeed45a KK |
8995 | /* Return TRUE for a valid displacement for the REG+disp addressing |
8996 | with MODE. */ | |
cdeed45a | 8997 | bool |
ef4bddc2 | 8998 | sh_legitimate_index_p (machine_mode mode, rtx op, bool consider_sh2a, |
8c2a3f3b | 8999 | bool allow_zero) |
cdeed45a | 9000 | { |
9b9ad23f OE |
9001 | if (! CONST_INT_P (op)) |
9002 | return false; | |
cdeed45a | 9003 | |
9b9ad23f OE |
9004 | { |
9005 | const HOST_WIDE_INT offset = INTVAL (op); | |
91f65b12 | 9006 | const int max_disp = sh_max_mov_insn_displacement (mode, consider_sh2a); |
8c2a3f3b | 9007 | const int align_mask = mov_insn_alignment_mask (mode, consider_sh2a); |
344332e8 | 9008 | |
9b9ad23f OE |
9009 | /* If the mode does not support any displacement always return false. |
9010 | Even though an index of '0' is actually always valid, it will cause | |
9011 | troubles when e.g. a DFmode move is split into two SFmode moves, | |
9012 | where one SFmode move will have index '0' and the other move will | |
9013 | have index '4'. */ | |
8c2a3f3b | 9014 | if (!allow_zero && max_disp < 1) |
9b9ad23f | 9015 | return false; |
cdeed45a | 9016 | |
9b9ad23f | 9017 | return offset >= 0 && offset <= max_disp && (offset & align_mask) == 0; |
cdeed45a | 9018 | } |
cdeed45a KK |
9019 | } |
9020 | ||
9021 | /* Recognize an RTL expression that is a valid memory address for | |
9022 | an instruction. | |
9023 | The MODE argument is the machine mode for the MEM expression | |
9024 | that wants to use this address. | |
9025 | Allow REG | |
9026 | REG+disp | |
9027 | REG+r0 | |
9028 | REG++ | |
fce1e5fb OE |
9029 | --REG |
9030 | GBR | |
9031 | GBR+disp */ | |
1bb99877 | 9032 | static bool |
ef4bddc2 | 9033 | sh_legitimate_address_p (machine_mode mode, rtx x, bool strict) |
cdeed45a | 9034 | { |
fce1e5fb OE |
9035 | if (REG_P (x) && REGNO (x) == GBR_REG) |
9036 | return true; | |
9037 | ||
cdeed45a KK |
9038 | if (MAYBE_BASE_REGISTER_RTX_P (x, strict)) |
9039 | return true; | |
9040 | else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC) | |
cdeed45a KK |
9041 | && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict)) |
9042 | return true; | |
fe3e478f | 9043 | else if (GET_CODE (x) == PLUS) |
cdeed45a KK |
9044 | { |
9045 | rtx xop0 = XEXP (x, 0); | |
9046 | rtx xop1 = XEXP (x, 1); | |
9047 | ||
fce1e5fb OE |
9048 | if (REG_P (xop0) && REGNO (xop0) == GBR_REG) |
9049 | return gbr_displacement (xop1, mode); | |
9050 | ||
cdeed45a KK |
9051 | if (GET_MODE_SIZE (mode) <= 8 |
9052 | && MAYBE_BASE_REGISTER_RTX_P (xop0, strict) | |
8c2a3f3b | 9053 | && sh_legitimate_index_p (mode, xop1, TARGET_SH2A, false)) |
cdeed45a KK |
9054 | return true; |
9055 | ||
e1fab8ba | 9056 | if (GET_MODE_SIZE (mode) <= 4 |
d5dd0a62 | 9057 | || (TARGET_FPU_DOUBLE && TARGET_FMOVD && mode == DFmode)) |
cdeed45a KK |
9058 | { |
9059 | if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict) | |
9060 | && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict)) | |
9061 | return true; | |
9062 | if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict) | |
9063 | && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)) | |
9064 | return true; | |
9065 | } | |
9066 | } | |
9067 | ||
9068 | return false; | |
9069 | } | |
9070 | \f | |
55eec660 AO |
9071 | /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol |
9072 | isn't protected by a PIC unspec. */ | |
aaf701c5 | 9073 | bool |
cf277499 | 9074 | nonpic_symbol_mentioned_p (rtx x) |
1a66cd67 | 9075 | { |
fa5322fa AO |
9076 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF |
9077 | || GET_CODE (x) == PC) | |
aaf701c5 | 9078 | return true; |
1a66cd67 | 9079 | |
fa5322fa AO |
9080 | /* We don't want to look into the possible MEM location of a |
9081 | CONST_DOUBLE, since we're not going to use it, in general. */ | |
9082 | if (GET_CODE (x) == CONST_DOUBLE) | |
aaf701c5 | 9083 | return false; |
fa5322fa | 9084 | |
1a66cd67 | 9085 | if (GET_CODE (x) == UNSPEC |
4773afa4 AO |
9086 | && (XINT (x, 1) == UNSPEC_PIC |
9087 | || XINT (x, 1) == UNSPEC_GOT | |
9088 | || XINT (x, 1) == UNSPEC_GOTOFF | |
fa5322fa | 9089 | || XINT (x, 1) == UNSPEC_GOTPLT |
463f02cd KK |
9090 | || XINT (x, 1) == UNSPEC_GOTTPOFF |
9091 | || XINT (x, 1) == UNSPEC_DTPOFF | |
58f451f0 | 9092 | || XINT (x, 1) == UNSPEC_TPOFF |
dc3ba671 | 9093 | || XINT (x, 1) == UNSPEC_PLT |
fbce972a | 9094 | || XINT (x, 1) == UNSPEC_PCREL |
dc3ba671 | 9095 | || XINT (x, 1) == UNSPEC_SYMOFF |
1e44e857 DJ |
9096 | || XINT (x, 1) == UNSPEC_PCREL_SYMOFF |
9097 | || XINT (x, 1) == UNSPEC_GOTFUNCDESC | |
9098 | || XINT (x, 1) == UNSPEC_GOTOFFFUNCDESC)) | |
aaf701c5 | 9099 | return false; |
1a66cd67 | 9100 | |
df4bacab OE |
9101 | const char* fmt = GET_RTX_FORMAT (GET_CODE (x)); |
9102 | for (int i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
1a66cd67 AO |
9103 | { |
9104 | if (fmt[i] == 'E') | |
9105 | { | |
df4bacab | 9106 | for (int j = XVECLEN (x, i) - 1; j >= 0; j--) |
1a66cd67 | 9107 | if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j))) |
aaf701c5 | 9108 | return true; |
1a66cd67 AO |
9109 | } |
9110 | else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i))) | |
aaf701c5 | 9111 | return true; |
1a66cd67 AO |
9112 | } |
9113 | ||
aaf701c5 | 9114 | return false; |
1a66cd67 AO |
9115 | } |
9116 | ||
9117 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or | |
6f317ef3 | 9118 | @GOTOFF in `reg'. */ |
1a66cd67 | 9119 | rtx |
df4bacab | 9120 | legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, rtx reg) |
1a66cd67 | 9121 | { |
81f40b79 | 9122 | if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE) |
463f02cd KK |
9123 | return orig; |
9124 | ||
1a66cd67 | 9125 | if (GET_CODE (orig) == LABEL_REF |
675ff4c7 | 9126 | || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig))) |
1a66cd67 | 9127 | { |
23d0939b | 9128 | if (reg == NULL_RTX) |
1a66cd67 AO |
9129 | reg = gen_reg_rtx (Pmode); |
9130 | ||
1e44e857 DJ |
9131 | if (TARGET_FDPIC |
9132 | && GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (orig)) | |
9133 | { | |
9134 | /* Weak functions may be NULL which doesn't work with | |
9135 | GOTOFFFUNCDESC because the runtime offset is not known. */ | |
9136 | if (SYMBOL_REF_WEAK (orig)) | |
9137 | emit_insn (gen_symGOTFUNCDESC2reg (reg, orig)); | |
9138 | else | |
9139 | emit_insn (gen_symGOTOFFFUNCDESC2reg (reg, orig)); | |
9140 | } | |
9141 | else if (TARGET_FDPIC | |
9142 | && (GET_CODE (orig) == LABEL_REF | |
9143 | || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_DECL (orig) | |
9144 | && (TREE_READONLY (SYMBOL_REF_DECL (orig)) | |
9145 | || SYMBOL_REF_EXTERNAL_P (orig) | |
9146 | || DECL_SECTION_NAME(SYMBOL_REF_DECL (orig)))))) | |
9147 | /* In FDPIC, GOTOFF can only be used for writable data. */ | |
9148 | emit_insn (gen_symGOT2reg (reg, orig)); | |
9149 | else | |
9150 | emit_insn (gen_symGOTOFF2reg (reg, orig)); | |
1a66cd67 AO |
9151 | return reg; |
9152 | } | |
9153 | else if (GET_CODE (orig) == SYMBOL_REF) | |
9154 | { | |
23d0939b | 9155 | if (reg == NULL_RTX) |
1a66cd67 AO |
9156 | reg = gen_reg_rtx (Pmode); |
9157 | ||
1e44e857 DJ |
9158 | if (TARGET_FDPIC && SYMBOL_REF_FUNCTION_P (orig)) |
9159 | emit_insn (gen_symGOTFUNCDESC2reg (reg, orig)); | |
9160 | else | |
9161 | emit_insn (gen_symGOT2reg (reg, orig)); | |
1a66cd67 AO |
9162 | return reg; |
9163 | } | |
9164 | return orig; | |
9165 | } | |
b91455de | 9166 | |
8c6d71c0 OE |
9167 | /* Given a (logical) mode size and an offset in bytes, try to find a the |
9168 | appropriate displacement value for a mov insn. On SH the displacements | |
9169 | are limited to max. 60 bytes for SImode, max. 30 bytes in HImode and max. | |
9170 | 15 bytes in QImode. To compensate this we create a new base address by | |
9171 | adding an adjustment value to it. | |
9172 | ||
9173 | If the originally requested offset is greater than 127 we prefer using | |
9174 | values 124..127 over 128..131 to increase opportunities to use the | |
9175 | add #imm, Rn insn. | |
9176 | ||
9177 | In some cases it is possible that a requested offset might seem unaligned | |
9178 | or inappropriate for the mode size, like offset = 2 and mode size = 4. | |
9179 | This is compensated by adjusting the base address so that the effective | |
9180 | address of the displacement move insn will be aligned. | |
9181 | ||
9182 | This is not the best possible way of rebasing the base address, as it | |
9183 | does not look at other present displacement addressings around it. | |
9184 | In some cases this can create more base address adjustments than would | |
9185 | actually be necessary. */ | |
8c6d71c0 OE |
9186 | struct disp_adjust |
9187 | { | |
9188 | rtx offset_adjust; | |
9189 | rtx mov_disp; | |
8c6d71c0 OE |
9190 | }; |
9191 | ||
9192 | static struct disp_adjust | |
ef4bddc2 | 9193 | sh_find_mov_disp_adjust (machine_mode mode, HOST_WIDE_INT offset) |
8c6d71c0 | 9194 | { |
9b9ad23f | 9195 | struct disp_adjust res = { NULL_RTX, NULL_RTX }; |
8c6d71c0 | 9196 | |
9b9ad23f OE |
9197 | /* Do not try to use SH2A's large displacements here, because this would |
9198 | effectively disable the small displacement insns. */ | |
9199 | const int mode_sz = GET_MODE_SIZE (mode); | |
9200 | const int mov_insn_sz = mov_insn_size (mode, false); | |
91f65b12 | 9201 | const int max_disp = sh_max_mov_insn_displacement (mode, false); |
9b9ad23f OE |
9202 | const int max_disp_next = max_disp + mov_insn_sz; |
9203 | HOST_WIDE_INT align_modifier = offset > 127 ? mov_insn_sz : 0; | |
8c6d71c0 | 9204 | HOST_WIDE_INT offset_adjust; |
506d7b68 | 9205 | |
8c6d71c0 | 9206 | /* In some cases this actually does happen and we must check for it. */ |
9b9ad23f | 9207 | if (mode_sz < 1 || mode_sz > 8 || max_disp < 1) |
8c6d71c0 OE |
9208 | return res; |
9209 | ||
8c6d71c0 OE |
9210 | /* Keeps the previous behavior for QImode displacement addressing. |
9211 | This just decides how the offset is re-based. Removing this special | |
9212 | case will result in slightly bigger code on average, but it's not that | |
9213 | bad actually. */ | |
9b9ad23f | 9214 | if (mov_insn_sz == 1) |
8c6d71c0 OE |
9215 | align_modifier = 0; |
9216 | ||
8c6d71c0 OE |
9217 | offset_adjust = ((offset + align_modifier) & ~max_disp) - align_modifier; |
9218 | ||
9b9ad23f | 9219 | if (mode_sz + offset - offset_adjust <= max_disp_next) |
8c6d71c0 OE |
9220 | { |
9221 | res.offset_adjust = GEN_INT (offset_adjust); | |
9222 | res.mov_disp = GEN_INT (offset - offset_adjust); | |
9223 | } | |
9224 | ||
9225 | return res; | |
9226 | } | |
9227 | ||
9228 | /* Try to modify an illegitimate address and make it legitimate. | |
9229 | If we find one, return the new, valid address. | |
9230 | Otherwise, return the original address. */ | |
506d7b68 | 9231 | static rtx |
ef4bddc2 | 9232 | sh_legitimize_address (rtx x, rtx oldx, machine_mode mode) |
506d7b68 PB |
9233 | { |
9234 | if (flag_pic) | |
9235 | x = legitimize_pic_address (oldx, mode, NULL_RTX); | |
9236 | ||
d5dd0a62 | 9237 | if ((TARGET_FPU_DOUBLE && mode == DFmode) |
8c6d71c0 OE |
9238 | || (TARGET_SH2E && mode == SFmode)) |
9239 | return x; | |
506d7b68 | 9240 | |
8c6d71c0 OE |
9241 | if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)) |
9242 | && BASE_REGISTER_RTX_P (XEXP (x, 0))) | |
344332e8 | 9243 | { |
9b9ad23f | 9244 | struct disp_adjust adj = sh_find_mov_disp_adjust (mode, |
8c6d71c0 OE |
9245 | INTVAL (XEXP (x, 1))); |
9246 | ||
9247 | if (adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX) | |
344332e8 OE |
9248 | { |
9249 | rtx sum = expand_binop (Pmode, add_optab, XEXP (x, 0), | |
8c6d71c0 OE |
9250 | adj.offset_adjust, NULL_RTX, 0, |
9251 | OPTAB_LIB_WIDEN); | |
9252 | return gen_rtx_PLUS (Pmode, sum, adj.mov_disp); | |
344332e8 OE |
9253 | } |
9254 | } | |
506d7b68 PB |
9255 | return x; |
9256 | } | |
9257 | ||
8c6d71c0 | 9258 | /* Attempt to replace *p, which is an address that needs reloading, with |
6f50eb9c KK |
9259 | a valid memory address for an operand of mode MODE. |
9260 | Like for sh_legitimize_address, for the SH we try to get a normal form | |
9261 | of the address. That will allow inheritance of the address reloads. */ | |
6f50eb9c | 9262 | bool |
ef4bddc2 | 9263 | sh_legitimize_reload_address (rtx *p, machine_mode mode, int opnum, |
6f50eb9c KK |
9264 | int itype) |
9265 | { | |
9266 | enum reload_type type = (enum reload_type) itype; | |
8c6d71c0 | 9267 | const int mode_sz = GET_MODE_SIZE (mode); |
6f50eb9c | 9268 | |
106a52b7 KK |
9269 | if (sh_lra_p ()) |
9270 | return false; | |
9271 | ||
8c6d71c0 | 9272 | if (GET_CODE (*p) == PLUS && CONST_INT_P (XEXP (*p, 1)) |
e1fab8ba | 9273 | && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p, 0), true)) |
6f50eb9c | 9274 | { |
8c6d71c0 | 9275 | const HOST_WIDE_INT offset = INTVAL (XEXP (*p, 1)); |
9b9ad23f | 9276 | struct disp_adjust adj = sh_find_mov_disp_adjust (mode, offset); |
6f50eb9c KK |
9277 | |
9278 | if (TARGET_SH2A && mode == DFmode && (offset & 0x7)) | |
9279 | { | |
9280 | push_reload (*p, NULL_RTX, p, NULL, | |
9281 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); | |
8c6d71c0 | 9282 | return true; |
6f50eb9c | 9283 | } |
8c6d71c0 | 9284 | |
6f50eb9c KK |
9285 | if (TARGET_SH2E && mode == SFmode) |
9286 | { | |
9287 | *p = copy_rtx (*p); | |
9288 | push_reload (*p, NULL_RTX, p, NULL, | |
9289 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); | |
8c6d71c0 | 9290 | return true; |
6f50eb9c | 9291 | } |
8c6d71c0 OE |
9292 | |
9293 | /* FIXME: Do not allow to legitimize QImode and HImode displacement | |
9294 | moves because then reload has a problem figuring the constraint | |
9295 | that the move insn target/source reg must be R0. | |
9296 | Or maybe some handling is wrong in sh_secondary_reload for this | |
9297 | to work properly? */ | |
9298 | if ((mode_sz == 4 || mode_sz == 8) | |
9299 | && ! (TARGET_SH4 && mode == DFmode) | |
9300 | && adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX) | |
9301 | { | |
9302 | rtx sum = gen_rtx_PLUS (Pmode, XEXP (*p, 0), adj.offset_adjust); | |
9303 | *p = gen_rtx_PLUS (Pmode, sum, adj.mov_disp); | |
6f50eb9c KK |
9304 | push_reload (sum, NULL_RTX, &XEXP (*p, 0), NULL, |
9305 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); | |
8c6d71c0 | 9306 | return true; |
6f50eb9c KK |
9307 | } |
9308 | } | |
8c6d71c0 | 9309 | |
6f50eb9c | 9310 | /* We must re-recognize what we created before. */ |
8c6d71c0 OE |
9311 | if (GET_CODE (*p) == PLUS |
9312 | && (mode_sz == 4 || mode_sz == 8) | |
9313 | && GET_CODE (XEXP (*p, 0)) == PLUS | |
9314 | && CONST_INT_P (XEXP (XEXP (*p, 0), 1)) | |
9315 | && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p, 0), 0), true) | |
9316 | && CONST_INT_P (XEXP (*p, 1)) | |
9317 | && ! (TARGET_SH2E && mode == SFmode)) | |
6f50eb9c KK |
9318 | { |
9319 | /* Because this address is so complex, we know it must have | |
9320 | been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, | |
9321 | it is already unshared, and needs no further unsharing. */ | |
9322 | push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL, | |
9323 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); | |
8c6d71c0 | 9324 | return true; |
6f50eb9c KK |
9325 | } |
9326 | ||
9327 | return false; | |
6f50eb9c KK |
9328 | } |
9329 | ||
90833f7f KK |
9330 | /* In the name of slightly smaller debug output, and to cater to |
9331 | general assembler lossage, recognize various UNSPEC sequences | |
9332 | and turn them back into a direct symbol reference. */ | |
90833f7f KK |
9333 | static rtx |
9334 | sh_delegitimize_address (rtx orig_x) | |
9335 | { | |
90833f7f KK |
9336 | orig_x = delegitimize_mem_from_attrs (orig_x); |
9337 | ||
df4bacab | 9338 | rtx x = orig_x; |
90833f7f KK |
9339 | if (MEM_P (x)) |
9340 | x = XEXP (x, 0); | |
9341 | if (GET_CODE (x) == CONST) | |
9342 | { | |
df4bacab | 9343 | rtx y = XEXP (x, 0); |
90833f7f KK |
9344 | if (GET_CODE (y) == UNSPEC) |
9345 | { | |
9346 | if (XINT (y, 1) == UNSPEC_GOT | |
2efd0aa6 KK |
9347 | || XINT (y, 1) == UNSPEC_GOTOFF |
9348 | || XINT (y, 1) == UNSPEC_SYMOFF) | |
90833f7f | 9349 | return XVECEXP (y, 0, 0); |
2efd0aa6 KK |
9350 | else if (XINT (y, 1) == UNSPEC_PCREL_SYMOFF) |
9351 | { | |
9352 | if (GET_CODE (XVECEXP (y, 0, 0)) == CONST) | |
9353 | { | |
9354 | rtx symplt = XEXP (XVECEXP (y, 0, 0), 0); | |
9355 | ||
9356 | if (GET_CODE (symplt) == UNSPEC | |
fbce972a KK |
9357 | && (XINT (symplt, 1) == UNSPEC_PLT |
9358 | || XINT (symplt, 1) == UNSPEC_PCREL)) | |
2efd0aa6 KK |
9359 | return XVECEXP (symplt, 0, 0); |
9360 | } | |
9361 | } | |
90833f7f KK |
9362 | } |
9363 | } | |
9364 | ||
9365 | return orig_x; | |
9366 | } | |
9367 | ||
b91455de KK |
9368 | /* Mark the use of a constant in the literal table. If the constant |
9369 | has multiple labels, make it unique. */ | |
c1b92d09 | 9370 | static rtx |
cf277499 | 9371 | mark_constant_pool_use (rtx x) |
b91455de | 9372 | { |
23d0939b | 9373 | if (x == NULL_RTX) |
b91455de KK |
9374 | return x; |
9375 | ||
9376 | switch (GET_CODE (x)) | |
9377 | { | |
9378 | case LABEL_REF: | |
9379 | x = XEXP (x, 0); | |
9380 | case CODE_LABEL: | |
9381 | break; | |
9382 | default: | |
9383 | return x; | |
9384 | } | |
9385 | ||
9386 | /* Get the first label in the list of labels for the same constant | |
9387 | and delete another labels in the list. */ | |
df4bacab OE |
9388 | rtx_insn* lab = as_a <rtx_insn*> (x); |
9389 | for (rtx_insn* insn = PREV_INSN (lab); insn; insn = PREV_INSN (insn)) | |
b91455de | 9390 | { |
f3536097 | 9391 | if (!LABEL_P (insn) |
b91455de KK |
9392 | || LABEL_REFS (insn) != NEXT_INSN (insn)) |
9393 | break; | |
9394 | lab = insn; | |
9395 | } | |
9396 | ||
b32d5189 | 9397 | for (rtx insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn)) |
4654c0cf | 9398 | as_a<rtx_insn *> (insn)->set_deleted (); |
b91455de KK |
9399 | |
9400 | /* Mark constants in a window. */ | |
df4bacab OE |
9401 | for (rtx_insn* insn = NEXT_INSN (as_a <rtx_insn *> (x)); insn; |
9402 | insn = NEXT_INSN (insn)) | |
b91455de | 9403 | { |
f3536097 | 9404 | if (!NONJUMP_INSN_P (insn)) |
b91455de KK |
9405 | continue; |
9406 | ||
df4bacab | 9407 | rtx pattern = PATTERN (insn); |
b91455de KK |
9408 | if (GET_CODE (pattern) != UNSPEC_VOLATILE) |
9409 | continue; | |
9410 | ||
9411 | switch (XINT (pattern, 1)) | |
9412 | { | |
9413 | case UNSPECV_CONST2: | |
9414 | case UNSPECV_CONST4: | |
9415 | case UNSPECV_CONST8: | |
9416 | XVECEXP (pattern, 0, 1) = const1_rtx; | |
9417 | break; | |
9418 | case UNSPECV_WINDOW_END: | |
9419 | if (XVECEXP (pattern, 0, 0) == x) | |
9420 | return lab; | |
9421 | break; | |
9422 | case UNSPECV_CONST_END: | |
9423 | return lab; | |
9424 | default: | |
9425 | break; | |
9426 | } | |
9427 | } | |
9428 | ||
9429 | return lab; | |
9430 | } | |
6e7b03e1 AH |
9431 | \f |
9432 | /* Return true if it's possible to redirect BRANCH1 to the destination | |
9433 | of an unconditional jump BRANCH2. We only want to do this if the | |
9434 | resulting branch will have a short displacement. */ | |
cf6186e9 JR |
9435 | static bool |
9436 | sh_can_follow_jump (const rtx_insn *branch1, const rtx_insn *branch2) | |
6e7b03e1 | 9437 | { |
d808ecdd KK |
9438 | /* Don't follow if BRANCH2 is possible to be a jump crossing between |
9439 | hot and cold partitions. */ | |
f1bebab6 | 9440 | if (flag_reorder_blocks_and_partition |
d808ecdd KK |
9441 | && simplejump_p (branch2) |
9442 | && CROSSING_JUMP_P (branch2)) | |
9443 | return false; | |
9444 | ||
6e7b03e1 AH |
9445 | if (flag_expensive_optimizations && simplejump_p (branch2)) |
9446 | { | |
9447 | rtx dest = XEXP (SET_SRC (single_set (branch2)), 0); | |
6cb7eb41 | 9448 | rtx_insn *insn; |
6e7b03e1 | 9449 | int distance; |
f676971a EC |
9450 | |
9451 | for (distance = 0, insn = NEXT_INSN (branch1); | |
9452 | insn && distance < 256; | |
6e7b03e1 AH |
9453 | insn = PREV_INSN (insn)) |
9454 | { | |
f676971a | 9455 | if (insn == dest) |
aaf701c5 | 9456 | return true; |
6e7b03e1 AH |
9457 | else |
9458 | distance += get_attr_length (insn); | |
9459 | } | |
f676971a EC |
9460 | for (distance = 0, insn = NEXT_INSN (branch1); |
9461 | insn && distance < 256; | |
6e7b03e1 AH |
9462 | insn = NEXT_INSN (insn)) |
9463 | { | |
f676971a | 9464 | if (insn == dest) |
aaf701c5 | 9465 | return true; |
6e7b03e1 AH |
9466 | else |
9467 | distance += get_attr_length (insn); | |
9468 | } | |
9469 | } | |
aaf701c5 | 9470 | return false; |
6e7b03e1 AH |
9471 | } |
9472 | ||
5e7a8ee0 | 9473 | /* Return nonzero if register old_reg can be renamed to register new_reg. */ |
aaf701c5 | 9474 | bool |
cf277499 SB |
9475 | sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, |
9476 | unsigned int new_reg) | |
03b8ec29 | 9477 | { |
832a3292 KH |
9478 | /* Interrupt functions can only use registers that have already been |
9479 | saved by the prologue, even if they would normally be | |
9480 | call-clobbered. */ | |
6fb5fa3c | 9481 | if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg)) |
aaf701c5 | 9482 | return false; |
03b8ec29 | 9483 | |
aaf701c5 | 9484 | return true; |
03b8ec29 DD |
9485 | } |
9486 | ||
95c0af87 | 9487 | /* Function to update the integer COST |
c237e94a ZW |
9488 | based on the relationship between INSN that is dependent on |
9489 | DEP_INSN through the dependence LINK. The default is to make no | |
9490 | adjustment to COST. This can be used for example to specify to | |
9491 | the scheduler that an output- or anti-dependence does not incur | |
95c0af87 JR |
9492 | the same cost as a data-dependence. The return value should be |
9493 | the new value for COST. */ | |
c237e94a | 9494 | static int |
b505225b TS |
9495 | sh_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, |
9496 | unsigned int) | |
c237e94a | 9497 | { |
c49439f1 | 9498 | rtx reg, use_pat; |
c237e94a | 9499 | |
b505225b | 9500 | if (dep_type == 0) |
c237e94a | 9501 | { |
c49439f1 R |
9502 | if (recog_memoized (insn) < 0 |
9503 | || recog_memoized (dep_insn) < 0) | |
95c0af87 | 9504 | return cost; |
c49439f1 | 9505 | |
df4bacab | 9506 | rtx dep_set = single_set (dep_insn); |
c49439f1 | 9507 | |
78d310c2 R |
9508 | /* The latency that we specify in the scheduling description refers |
9509 | to the actual output, not to an auto-increment register; for that, | |
9510 | the latency is one. */ | |
9511 | if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1) | |
9512 | { | |
9513 | rtx set = single_set (insn); | |
9514 | ||
9515 | if (set | |
9516 | && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set)) | |
9517 | && (!MEM_P (SET_DEST (set)) | |
9518 | || !reg_mentioned_p (SET_DEST (dep_set), | |
9519 | XEXP (SET_DEST (set), 0)))) | |
9520 | cost = 1; | |
9521 | } | |
c237e94a ZW |
9522 | /* The only input for a call that is timing-critical is the |
9523 | function's address. */ | |
f3536097 | 9524 | if (CALL_P (insn)) |
c49439f1 | 9525 | { |
da4fdf2d SB |
9526 | rtx call = get_call_rtx_from (insn); |
9527 | if (call | |
73a4d10b R |
9528 | /* sibcalli_thunk uses a symbol_ref in an unspec. */ |
9529 | && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC | |
9530 | || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))) | |
78d310c2 | 9531 | cost -= TARGET_SH4_300 ? 3 : 6; |
c49439f1 | 9532 | } |
c237e94a ZW |
9533 | /* Likewise, the most timing critical input for an sfuncs call |
9534 | is the function address. However, sfuncs typically start | |
9535 | using their arguments pretty quickly. | |
78d310c2 R |
9536 | Assume a four cycle delay for SH4 before they are needed. |
9537 | Cached ST40-300 calls are quicker, so assume only a one | |
9538 | cycle delay there. | |
9539 | ??? Maybe we should encode the delays till input registers | |
9540 | are needed by sfuncs into the sfunc call insn. */ | |
c49439f1 R |
9541 | /* All sfunc calls are parallels with at least four components. |
9542 | Exploit this to avoid unnecessary calls to sfunc_uses_reg. */ | |
9543 | else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
9544 | && XVECLEN (PATTERN (insn), 0) >= 4 | |
9545 | && (reg = sfunc_uses_reg (insn))) | |
9546 | { | |
9547 | if (! reg_set_p (reg, dep_insn)) | |
78d310c2 R |
9548 | cost -= TARGET_SH4_300 ? 1 : 4; |
9549 | } | |
9550 | if (TARGET_HARD_SH4 && !TARGET_SH4_300) | |
9551 | { | |
df4bacab OE |
9552 | attr_type dep_type = get_attr_type (dep_insn); |
9553 | attr_type type; | |
78d310c2 R |
9554 | if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD) |
9555 | cost--; | |
9556 | else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI) | |
9557 | && (type = get_attr_type (insn)) != TYPE_CALL | |
9558 | && type != TYPE_SFUNC) | |
9559 | cost--; | |
9560 | /* When the preceding instruction loads the shift amount of | |
9561 | the following SHAD/SHLD, the latency of the load is increased | |
9562 | by 1 cycle. */ | |
9563 | if (get_attr_type (insn) == TYPE_DYN_SHIFT | |
9564 | && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES | |
c6ac6e82 | 9565 | && reg_overlap_mentioned_p (SET_DEST (dep_set), |
78d310c2 R |
9566 | XEXP (SET_SRC (single_set (insn)), |
9567 | 1))) | |
9568 | cost++; | |
9569 | /* When an LS group instruction with a latency of less than | |
9570 | 3 cycles is followed by a double-precision floating-point | |
9571 | instruction, FIPR, or FTRV, the latency of the first | |
9572 | instruction is increased to 3 cycles. */ | |
9573 | else if (cost < 3 | |
9574 | && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP | |
9575 | && get_attr_dfp_comp (insn) == DFP_COMP_YES) | |
9576 | cost = 3; | |
9577 | /* The lsw register of a double-precision computation is ready one | |
9578 | cycle earlier. */ | |
9579 | else if (reload_completed | |
9580 | && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES | |
9581 | && (use_pat = single_set (insn)) | |
9582 | && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))), | |
9583 | SET_SRC (use_pat))) | |
9584 | cost -= 1; | |
9585 | ||
9586 | if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES | |
9587 | && get_attr_late_fp_use (insn) == LATE_FP_USE_YES) | |
9588 | cost -= 1; | |
9589 | } | |
9590 | else if (TARGET_SH4_300) | |
9591 | { | |
9592 | /* Stores need their input register two cycles later. */ | |
df4bacab | 9593 | attr_type type; |
78d310c2 R |
9594 | if (dep_set && cost >= 1 |
9595 | && ((type = get_attr_type (insn)) == TYPE_STORE | |
9596 | || type == TYPE_PSTORE | |
9597 | || type == TYPE_FSTORE || type == TYPE_MAC_MEM)) | |
9598 | { | |
9599 | rtx set = single_set (insn); | |
9600 | ||
9601 | if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0)) | |
9602 | && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set))) | |
9603 | { | |
9604 | cost -= 2; | |
9605 | /* But don't reduce the cost below 1 if the address depends | |
9606 | on a side effect of dep_insn. */ | |
9607 | if (cost < 1 | |
9608 | && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn)) | |
9609 | cost = 1; | |
9610 | } | |
9611 | } | |
9612 | } | |
c49439f1 R |
9613 | } |
9614 | /* An anti-dependence penalty of two applies if the first insn is a double | |
9615 | precision fadd / fsub / fmul. */ | |
78d310c2 | 9616 | else if (!TARGET_SH4_300 |
b505225b | 9617 | && dep_type == REG_DEP_ANTI |
c49439f1 | 9618 | && recog_memoized (dep_insn) >= 0 |
78d310c2 R |
9619 | && (get_attr_type (dep_insn) == TYPE_DFP_ARITH |
9620 | || get_attr_type (dep_insn) == TYPE_DFP_MUL) | |
c49439f1 R |
9621 | /* A lot of alleged anti-flow dependences are fake, |
9622 | so check this one is real. */ | |
9623 | && flow_dependent_p (dep_insn, insn)) | |
c237e94a | 9624 | cost = 2; |
c49439f1 | 9625 | |
c237e94a ZW |
9626 | return cost; |
9627 | } | |
3007d592 | 9628 | |
c49439f1 R |
9629 | /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check |
9630 | if DEP_INSN is anti-flow dependent on INSN. */ | |
aaf701c5 | 9631 | static bool |
cf277499 | 9632 | flow_dependent_p (rtx insn, rtx dep_insn) |
c49439f1 R |
9633 | { |
9634 | rtx tmp = PATTERN (insn); | |
9635 | ||
9636 | note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp); | |
9637 | return tmp == NULL_RTX; | |
9638 | } | |
9639 | ||
9640 | /* A helper function for flow_dependent_p called through note_stores. */ | |
9641 | static void | |
7bc980e1 | 9642 | flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) |
c49439f1 R |
9643 | { |
9644 | rtx * pinsn = (rtx *) data; | |
9645 | ||
9646 | if (*pinsn && reg_referenced_p (x, *pinsn)) | |
9647 | *pinsn = NULL_RTX; | |
9648 | } | |
9649 | ||
b48f503c | 9650 | /* For use by sh_allocate_initial_value. Note that sh.md contains some |
3007d592 R |
9651 | 'special function' patterns (type sfunc) that clobber pr, but that |
9652 | do not look like function calls to leaf_function_p. Hence we must | |
9653 | do this extra check. */ | |
b48f503c | 9654 | static int |
cf277499 | 9655 | sh_pr_n_sets (void) |
3007d592 | 9656 | { |
e1fab8ba | 9657 | return DF_REG_DEF_COUNT (PR_REG); |
3007d592 | 9658 | } |
fa5322fa | 9659 | |
b48f503c KK |
9660 | /* Return where to allocate pseudo for a given hard register initial |
9661 | value. */ | |
9662 | static rtx | |
9663 | sh_allocate_initial_value (rtx hard_reg) | |
9664 | { | |
e1fab8ba | 9665 | if (REGNO (hard_reg) == PR_REG) |
b48f503c | 9666 | { |
e1fab8ba OE |
9667 | if (crtl->is_leaf && ! sh_pr_n_sets ()) |
9668 | return hard_reg; | |
b48f503c | 9669 | else |
e1fab8ba | 9670 | return gen_frame_mem (Pmode, return_address_pointer_rtx); |
b48f503c | 9671 | } |
b48f503c | 9672 | |
e1fab8ba | 9673 | return NULL_RTX; |
b48f503c KK |
9674 | } |
9675 | ||
c49439f1 R |
9676 | /* This function returns "2" to indicate dual issue for the SH4 |
9677 | processor. To be used by the DFA pipeline description. */ | |
fae15c93 | 9678 | static int |
832a3292 | 9679 | sh_issue_rate (void) |
fae15c93 | 9680 | { |
c49439f1 R |
9681 | if (TARGET_SUPERSCALAR) |
9682 | return 2; | |
9683 | else | |
9684 | return 1; | |
fae15c93 VM |
9685 | } |
9686 | ||
58565a33 SKG |
9687 | /* Functions for ready queue reordering for sched1. */ |
9688 | ||
9689 | /* Get weight for mode for a set x. */ | |
9690 | static short | |
ef4bddc2 | 9691 | find_set_regmode_weight (rtx x, machine_mode mode) |
58565a33 SKG |
9692 | { |
9693 | if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode)) | |
9694 | return 1; | |
9695 | if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode)) | |
9696 | { | |
f3536097 | 9697 | if (REG_P (SET_DEST (x))) |
58565a33 SKG |
9698 | { |
9699 | if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x))) | |
9700 | return 1; | |
9701 | else | |
9702 | return 0; | |
9703 | } | |
9704 | return 1; | |
9705 | } | |
9706 | return 0; | |
9707 | } | |
9708 | ||
9709 | /* Get regmode weight for insn. */ | |
9710 | static short | |
ef4bddc2 | 9711 | find_insn_regmode_weight (rtx insn, machine_mode mode) |
58565a33 | 9712 | { |
58565a33 | 9713 | /* Increment weight for each register born here. */ |
df4bacab OE |
9714 | rtx x = PATTERN (insn); |
9715 | short reg_weight = find_set_regmode_weight (x, mode); | |
58565a33 SKG |
9716 | if (GET_CODE (x) == PARALLEL) |
9717 | { | |
9718 | int j; | |
9719 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) | |
9720 | { | |
9721 | x = XVECEXP (PATTERN (insn), 0, j); | |
9722 | reg_weight += find_set_regmode_weight (x, mode); | |
9723 | } | |
9724 | } | |
9725 | /* Decrement weight for each register that dies here. */ | |
9726 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) | |
9727 | { | |
9728 | if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED) | |
9729 | { | |
9730 | rtx note = XEXP (x, 0); | |
f3536097 | 9731 | if (REG_P (note) && GET_MODE (note) == mode) |
58565a33 SKG |
9732 | reg_weight--; |
9733 | } | |
9734 | } | |
9735 | return reg_weight; | |
9736 | } | |
9737 | ||
9738 | /* Calculate regmode weights for all insns of a basic block. */ | |
9739 | static void | |
ef4bddc2 | 9740 | find_regmode_weight (basic_block b, machine_mode mode) |
58565a33 | 9741 | { |
52d251b5 | 9742 | rtx_insn *insn, *next_tail, *head, *tail; |
58565a33 | 9743 | |
c6d56443 | 9744 | get_ebb_head_tail (b, b, &head, &tail); |
58565a33 SKG |
9745 | next_tail = NEXT_INSN (tail); |
9746 | ||
9747 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
9748 | { | |
9749 | /* Handle register life information. */ | |
9750 | if (!INSN_P (insn)) | |
9751 | continue; | |
9752 | ||
9753 | if (mode == SFmode) | |
9754 | INSN_REGMODE_WEIGHT (insn, mode) = | |
6387ab2c OE |
9755 | find_insn_regmode_weight (insn, mode) |
9756 | + 2 * find_insn_regmode_weight (insn, DFmode); | |
58565a33 SKG |
9757 | else if (mode == SImode) |
9758 | INSN_REGMODE_WEIGHT (insn, mode) = | |
6387ab2c OE |
9759 | find_insn_regmode_weight (insn, mode) |
9760 | + 2 * find_insn_regmode_weight (insn, DImode); | |
58565a33 SKG |
9761 | } |
9762 | } | |
9763 | ||
9764 | /* Comparison function for ready queue sorting. */ | |
9765 | static int | |
508ea1c5 | 9766 | rank_for_reorder (const void *x, const void *y) |
58565a33 | 9767 | { |
ce1ce33a DM |
9768 | rtx_insn *tmp = *(rtx_insn * const *) y; |
9769 | rtx_insn *tmp2 = *(rtx_insn * const *) x; | |
58565a33 SKG |
9770 | |
9771 | /* The insn in a schedule group should be issued the first. */ | |
9772 | if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2)) | |
9773 | return SCHED_GROUP_P (tmp2) ? 1 : -1; | |
9774 | ||
f676971a | 9775 | /* If insns are equally good, sort by INSN_LUID (original insn order), This |
58565a33 SKG |
9776 | minimizes instruction movement, thus minimizing sched's effect on |
9777 | register pressure. */ | |
9778 | return INSN_LUID (tmp) - INSN_LUID (tmp2); | |
9779 | } | |
9780 | ||
9781 | /* Resort the array A in which only element at index N may be out of order. */ | |
9782 | static void | |
ce1ce33a | 9783 | swap_reorder (rtx_insn **a, int n) |
58565a33 | 9784 | { |
ce1ce33a | 9785 | rtx_insn *insn = a[n - 1]; |
58565a33 SKG |
9786 | int i = n - 2; |
9787 | ||
9788 | while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0) | |
9789 | { | |
9790 | a[i + 1] = a[i]; | |
9791 | i -= 1; | |
9792 | } | |
9793 | a[i + 1] = insn; | |
9794 | } | |
9795 | ||
e6b8b8c7 | 9796 | /* Sort the ready list by ascending priority. */ |
58565a33 | 9797 | static void |
ce1ce33a | 9798 | ready_reorder (rtx_insn **ready, int nready) |
58565a33 | 9799 | { |
e6b8b8c7 OE |
9800 | if (nready == 2) |
9801 | swap_reorder (ready, nready); | |
9802 | else if (nready > 2) | |
ce1ce33a | 9803 | qsort (ready, nready, sizeof (rtx_insn *), rank_for_reorder); |
58565a33 SKG |
9804 | } |
9805 | ||
6fb5fa3c DB |
9806 | /* Count life regions of r0 for a block. */ |
9807 | static int | |
9808 | find_r0_life_regions (basic_block b) | |
9809 | { | |
df4bacab | 9810 | bool live; |
6fb5fa3c DB |
9811 | int set; |
9812 | int death = 0; | |
9813 | ||
89a95777 | 9814 | if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG)) |
6fb5fa3c DB |
9815 | { |
9816 | set = 1; | |
df4bacab | 9817 | live = true; |
6fb5fa3c DB |
9818 | } |
9819 | else | |
9820 | { | |
9821 | set = 0; | |
df4bacab | 9822 | live = false; |
6fb5fa3c DB |
9823 | } |
9824 | ||
df4bacab OE |
9825 | rtx_insn* insn = BB_HEAD (b); |
9826 | rtx_insn* end = BB_END (b); | |
9827 | rtx r0_reg = gen_rtx_REG (SImode, R0_REG); | |
6fb5fa3c DB |
9828 | while (1) |
9829 | { | |
9830 | if (INSN_P (insn)) | |
9831 | { | |
9832 | if (find_regno_note (insn, REG_DEAD, R0_REG)) | |
9833 | { | |
9834 | death++; | |
df4bacab | 9835 | live = false; |
6fb5fa3c | 9836 | } |
df4bacab OE |
9837 | |
9838 | rtx pset; | |
6fb5fa3c DB |
9839 | if (!live |
9840 | && (pset = single_set (insn)) | |
9841 | && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset)) | |
9842 | && !find_regno_note (insn, REG_UNUSED, R0_REG)) | |
9843 | { | |
9844 | set++; | |
df4bacab | 9845 | live = true; |
6fb5fa3c DB |
9846 | } |
9847 | } | |
9848 | if (insn == end) | |
9849 | break; | |
9850 | insn = NEXT_INSN (insn); | |
9851 | } | |
9852 | return set - death; | |
9853 | } | |
9854 | ||
58565a33 SKG |
9855 | /* Calculate regmode weights for all insns of all basic block. */ |
9856 | static void | |
508ea1c5 KH |
9857 | sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED, |
9858 | int verbose ATTRIBUTE_UNUSED, | |
9859 | int old_max_uid) | |
58565a33 SKG |
9860 | { |
9861 | basic_block b; | |
9862 | ||
9863 | regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short)); | |
9864 | regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short)); | |
6fb5fa3c | 9865 | r0_life_regions = 0; |
58565a33 | 9866 | |
4f42035e | 9867 | FOR_EACH_BB_REVERSE_FN (b, cfun) |
58565a33 | 9868 | { |
c6d56443 KK |
9869 | find_regmode_weight (b, SImode); |
9870 | find_regmode_weight (b, SFmode); | |
6fb5fa3c DB |
9871 | if (!reload_completed) |
9872 | r0_life_regions += find_r0_life_regions (b); | |
58565a33 SKG |
9873 | } |
9874 | ||
9875 | CURR_REGMODE_PRESSURE (SImode) = 0; | |
9876 | CURR_REGMODE_PRESSURE (SFmode) = 0; | |
58565a33 SKG |
9877 | } |
9878 | ||
9879 | /* Cleanup. */ | |
9880 | static void | |
508ea1c5 KH |
9881 | sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED, |
9882 | int verbose ATTRIBUTE_UNUSED) | |
58565a33 SKG |
9883 | { |
9884 | if (regmode_weight[0]) | |
9885 | { | |
9886 | free (regmode_weight[0]); | |
9887 | regmode_weight[0] = NULL; | |
9888 | } | |
9889 | if (regmode_weight[1]) | |
9890 | { | |
9891 | free (regmode_weight[1]); | |
9892 | regmode_weight[1] = NULL; | |
9893 | } | |
9894 | } | |
9895 | ||
9896 | /* Cache the can_issue_more so that we can return it from reorder2. Also, | |
9897 | keep count of register pressures on SImode and SFmode. */ | |
9898 | static int | |
508ea1c5 KH |
9899 | sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED, |
9900 | int sched_verbose ATTRIBUTE_UNUSED, | |
ac44248e | 9901 | rtx_insn *insn, |
508ea1c5 | 9902 | int can_issue_more) |
58565a33 SKG |
9903 | { |
9904 | if (GET_CODE (PATTERN (insn)) != USE | |
9905 | && GET_CODE (PATTERN (insn)) != CLOBBER) | |
9906 | cached_can_issue_more = can_issue_more - 1; | |
9907 | else | |
9908 | cached_can_issue_more = can_issue_more; | |
9909 | ||
9910 | if (reload_completed) | |
9911 | return cached_can_issue_more; | |
9912 | ||
9913 | CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode); | |
9914 | CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode); | |
9915 | ||
9916 | return cached_can_issue_more; | |
9917 | } | |
9918 | ||
9919 | static void | |
508ea1c5 KH |
9920 | sh_md_init (FILE *dump ATTRIBUTE_UNUSED, |
9921 | int verbose ATTRIBUTE_UNUSED, | |
9922 | int veclen ATTRIBUTE_UNUSED) | |
58565a33 SKG |
9923 | { |
9924 | CURR_REGMODE_PRESSURE (SImode) = 0; | |
9925 | CURR_REGMODE_PRESSURE (SFmode) = 0; | |
9926 | } | |
9927 | ||
9928 | /* Some magic numbers. */ | |
9929 | /* Pressure on register r0 can lead to spill failures. so avoid sched1 for | |
9930 | functions that already have high pressure on r0. */ | |
9931 | #define R0_MAX_LIFE_REGIONS 2 | |
4ee31f1e | 9932 | /* Register Pressure thresholds for SImode and SFmode registers. */ |
58565a33 SKG |
9933 | #define SIMODE_MAX_WEIGHT 5 |
9934 | #define SFMODE_MAX_WEIGHT 10 | |
9935 | ||
9936 | /* Return true if the pressure is high for MODE. */ | |
aaf701c5 | 9937 | static bool |
ef4bddc2 | 9938 | high_pressure (machine_mode mode) |
58565a33 SKG |
9939 | { |
9940 | /* Pressure on register r0 can lead to spill failures. so avoid sched1 for | |
9941 | functions that already have high pressure on r0. */ | |
6fb5fa3c | 9942 | if (r0_life_regions >= R0_MAX_LIFE_REGIONS) |
aaf701c5 | 9943 | return true; |
58565a33 SKG |
9944 | |
9945 | if (mode == SFmode) | |
9946 | return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT); | |
9947 | else | |
9948 | return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT); | |
9949 | } | |
9950 | ||
9951 | /* Reorder ready queue if register pressure is high. */ | |
9952 | static int | |
508ea1c5 KH |
9953 | sh_reorder (FILE *dump ATTRIBUTE_UNUSED, |
9954 | int sched_verbose ATTRIBUTE_UNUSED, | |
ce1ce33a | 9955 | rtx_insn **ready, |
508ea1c5 KH |
9956 | int *n_readyp, |
9957 | int clock_var ATTRIBUTE_UNUSED) | |
58565a33 SKG |
9958 | { |
9959 | if (reload_completed) | |
9960 | return sh_issue_rate (); | |
9961 | ||
9962 | if (high_pressure (SFmode) || high_pressure (SImode)) | |
9963 | { | |
9964 | ready_reorder (ready, *n_readyp); | |
9965 | } | |
9966 | ||
9967 | return sh_issue_rate (); | |
9968 | } | |
9969 | ||
9970 | /* Skip cycles if the current register pressure is high. */ | |
f676971a | 9971 | static int |
508ea1c5 KH |
9972 | sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED, |
9973 | int sched_verbose ATTRIBUTE_UNUSED, | |
ce1ce33a | 9974 | rtx_insn **ready ATTRIBUTE_UNUSED, |
508ea1c5 KH |
9975 | int *n_readyp ATTRIBUTE_UNUSED, |
9976 | int clock_var ATTRIBUTE_UNUSED) | |
58565a33 SKG |
9977 | { |
9978 | if (reload_completed) | |
9979 | return cached_can_issue_more; | |
9980 | ||
f676971a | 9981 | if (high_pressure(SFmode) || high_pressure (SImode)) |
58565a33 SKG |
9982 | skip_cycles = 1; |
9983 | ||
9984 | return cached_can_issue_more; | |
9985 | } | |
9986 | ||
9987 | /* Skip cycles without sorting the ready queue. This will move insn from | |
9988 | Q->R. If this is the last cycle we are skipping; allow sorting of ready | |
f676971a | 9989 | queue by sh_reorder. */ |
58565a33 | 9990 | |
f676971a EC |
9991 | /* Generally, skipping these many cycles are sufficient for all insns to move |
9992 | from Q -> R. */ | |
9993 | #define MAX_SKIPS 8 | |
58565a33 SKG |
9994 | |
9995 | static int | |
508ea1c5 KH |
9996 | sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED, |
9997 | int sched_verbose ATTRIBUTE_UNUSED, | |
ac44248e | 9998 | rtx_insn *insn ATTRIBUTE_UNUSED, |
508ea1c5 KH |
9999 | int last_clock_var, |
10000 | int clock_var, | |
10001 | int *sort_p) | |
58565a33 SKG |
10002 | { |
10003 | if (reload_completed) | |
832a3292 | 10004 | return 0; |
58565a33 | 10005 | |
f676971a | 10006 | if (skip_cycles) |
58565a33 | 10007 | { |
832a3292 KH |
10008 | if ((clock_var - last_clock_var) < MAX_SKIPS) |
10009 | { | |
10010 | *sort_p = 0; | |
10011 | return 1; | |
10012 | } | |
10013 | /* If this is the last cycle we are skipping, allow reordering of R. */ | |
10014 | if ((clock_var - last_clock_var) == MAX_SKIPS) | |
10015 | { | |
10016 | *sort_p = 1; | |
10017 | return 1; | |
10018 | } | |
58565a33 | 10019 | } |
58565a33 SKG |
10020 | |
10021 | skip_cycles = 0; | |
10022 | ||
10023 | return 0; | |
10024 | } | |
10025 | ||
fa5322fa | 10026 | static bool |
3101faab | 10027 | sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED) |
fa5322fa | 10028 | { |
e1fab8ba | 10029 | return TARGET_HITACHI || sh_attr_renesas_p (record_type); |
fa5322fa | 10030 | } |
ca903bba | 10031 | \f |
f676971a | 10032 | /* |
ca903bba R |
10033 | On the SH1..SH4, the trampoline looks like |
10034 | 2 0002 D202 mov.l l2,r2 | |
10035 | 1 0000 D301 mov.l l1,r3 | |
10036 | 3 0004 422B jmp @r2 | |
10037 | 4 0006 0009 nop | |
10038 | 5 0008 00000000 l1: .long area | |
10039 | 6 000c 00000000 l2: .long function | |
10040 | ||
1e44e857 DJ |
10041 | FDPIC needs a form that includes a function descriptor and |
10042 | code to load the GOT register: | |
10043 | 0 0000 00000000 .long l0 | |
10044 | 1 0004 00000000 .long gotval | |
10045 | 2 0008 D302 l0: mov.l l1,r3 | |
10046 | 3 000a D203 mov.l l2,r2 | |
10047 | 4 000c 6122 mov.l @r2,r1 | |
10048 | 5 000e 5C21 mov.l @(4,r2),r12 | |
10049 | 6 0010 412B jmp @r1 | |
10050 | 7 0012 0009 nop | |
10051 | 8 0014 00000000 l1: .long area | |
10052 | 9 0018 00000000 l2: .long function | |
10053 | ||
ca903bba R |
10054 | SH5 (compact) uses r1 instead of r3 for the static chain. */ |
10055 | ||
1e44e857 DJ |
10056 | /* Emit insns to store a value at memory address + offset. */ |
10057 | static void | |
10058 | sh_emit_storesi (rtx addr, HOST_WIDE_INT offset, rtx value) | |
10059 | { | |
10060 | gcc_assert ((offset & 3) == 0); | |
10061 | emit_move_insn (offset == 0 | |
10062 | ? change_address (addr, SImode, NULL_RTX) | |
10063 | : adjust_address (addr, SImode, offset), value); | |
10064 | } | |
10065 | ||
10066 | /* Emit insns to store w0 at addr + offset and w1 at addr + offset + 2. */ | |
10067 | static void | |
10068 | sh_emit_storehi (rtx addr, HOST_WIDE_INT offset, uint16_t w0, uint16_t w1) | |
10069 | { | |
10070 | sh_emit_storesi (addr, offset, gen_int_mode (TARGET_LITTLE_ENDIAN | |
10071 | ? (w0 | (w1 << 16)) | |
10072 | : (w1 | (w0 << 16)), SImode)); | |
10073 | } | |
ca903bba R |
10074 | |
10075 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
10076 | FNADDR is an RTX for the address of the function's pure code. | |
10077 | CXT is an RTX for the static chain value for the function. */ | |
994322ef RH |
10078 | static void |
10079 | sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt) | |
ca903bba | 10080 | { |
994322ef RH |
10081 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); |
10082 | rtx tramp = force_reg (Pmode, XEXP (tramp_mem, 0)); | |
57d38024 | 10083 | |
1e44e857 DJ |
10084 | if (TARGET_FDPIC) |
10085 | { | |
10086 | rtx a = force_reg (Pmode, plus_constant (Pmode, XEXP (tramp_mem, 0), 8)); | |
10087 | ||
10088 | sh_emit_storesi (tramp_mem, 0, a); | |
10089 | sh_emit_storesi (tramp_mem, 4, sh_get_fdpic_reg_initial_val ()); | |
10090 | ||
10091 | sh_emit_storehi (tramp_mem, 8, 0xd302, 0xd203); | |
10092 | sh_emit_storehi (tramp_mem, 12, 0x6122, 0x5c21); | |
10093 | sh_emit_storehi (tramp_mem, 16, 0x412b, 0x0009); | |
10094 | ||
10095 | sh_emit_storesi (tramp_mem, 20, cxt); | |
10096 | sh_emit_storesi (tramp_mem, 24, fnaddr); | |
10097 | } | |
10098 | else | |
10099 | { | |
10100 | sh_emit_storehi (tramp_mem, 0, 0xd202, 0xd301); | |
10101 | sh_emit_storehi (tramp_mem, 4, 0x422b, 0x0009); | |
10102 | ||
10103 | sh_emit_storesi (tramp_mem, 8, cxt); | |
10104 | sh_emit_storesi (tramp_mem, 12, fnaddr); | |
10105 | } | |
e1fab8ba | 10106 | if (TARGET_HARD_SH4) |
ca903bba | 10107 | { |
dc557046 | 10108 | if (!TARGET_INLINE_IC_INVALIDATE |
f3ca7111 | 10109 | || (!(TARGET_SH4A || TARGET_SH4_300) && TARGET_USERMODE)) |
73a4d10b | 10110 | emit_library_call (function_symbol (NULL, "__ic_invalidate", |
1e44e857 | 10111 | FUNCTION_ORDINARY).sym, |
db69559b | 10112 | LCT_NORMAL, VOIDmode, tramp, SImode); |
ca903bba R |
10113 | else |
10114 | emit_insn (gen_ic_invalidate_line (tramp)); | |
10115 | } | |
10116 | } | |
10117 | ||
994322ef | 10118 | /* On SH5, trampolines are SHmedia code, so add 1 to the address. */ |
994322ef RH |
10119 | static rtx |
10120 | sh_trampoline_adjust_address (rtx tramp) | |
10121 | { | |
994322ef RH |
10122 | return tramp; |
10123 | } | |
10124 | ||
73a4d10b R |
10125 | /* If PIC, we cannot make sibling calls to global functions |
10126 | because the PLT requires r12 to be live. */ | |
4977bab6 | 10127 | static bool |
cf277499 | 10128 | sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
4977bab6 | 10129 | { |
73a4d10b | 10130 | return (1 |
73a4d10b | 10131 | && ! sh_cfun_interrupt_handler_p () |
1e44e857 | 10132 | && (! flag_pic || TARGET_FDPIC |
fbce972a | 10133 | || (decl && ! (TREE_PUBLIC (decl) || DECL_WEAK (decl))) |
73a4d10b | 10134 | || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT))); |
4977bab6 | 10135 | } |
fbce972a KK |
10136 | |
10137 | /* Expand to appropriate sym*_label2reg for SYM and SIBCALL_P. */ | |
10138 | void | |
10139 | sh_expand_sym_label2reg (rtx reg, rtx sym, rtx lab, bool sibcall_p) | |
10140 | { | |
10141 | const_tree decl = SYMBOL_REF_DECL (sym); | |
10142 | bool is_weak = (decl && DECL_P (decl) && DECL_WEAK (decl)); | |
10143 | ||
10144 | if (!is_weak && SYMBOL_REF_LOCAL_P (sym)) | |
10145 | emit_insn (gen_sym_label2reg (reg, sym, lab)); | |
1e44e857 | 10146 | else if (sibcall_p && SYMBOL_REF_LOCAL_P (sym)) |
fbce972a KK |
10147 | emit_insn (gen_symPCREL_label2reg (reg, sym, lab)); |
10148 | else | |
10149 | emit_insn (gen_symPLT_label2reg (reg, sym, lab)); | |
10150 | } | |
c1b92d09 R |
10151 | \f |
10152 | /* Machine specific built-in functions. */ | |
10153 | ||
10154 | struct builtin_description | |
10155 | { | |
6d9e1220 | 10156 | bool (* const is_enabled) (void); |
c1b92d09 R |
10157 | const enum insn_code icode; |
10158 | const char *const name; | |
10159 | int signature; | |
1cc24576 | 10160 | tree fndecl; |
c1b92d09 R |
10161 | }; |
10162 | ||
6af1a779 | 10163 | /* This function can be used if there are any built-ins that are not for |
fe3e478f | 10164 | SHmedia. It's commented out to avoid the defined-but-unused warning. */ |
7d11d296 OE |
10165 | static bool |
10166 | sh1_builtin_p (void) | |
10167 | { | |
10168 | return TARGET_SH1; | |
10169 | } | |
10170 | ||
c1b92d09 R |
10171 | /* describe number and signedness of arguments; arg[0] == result |
10172 | (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */ | |
3b962ea0 | 10173 | /* 9: 64-bit pointer, 10: 32-bit pointer */ |
c1b92d09 R |
10174 | static const char signature_args[][4] = |
10175 | { | |
10176 | #define SH_BLTIN_V2SI2 0 | |
10177 | { 4, 4 }, | |
10178 | #define SH_BLTIN_V4HI2 1 | |
10179 | { 4, 4 }, | |
10180 | #define SH_BLTIN_V2SI3 2 | |
10181 | { 4, 4, 4 }, | |
10182 | #define SH_BLTIN_V4HI3 3 | |
10183 | { 4, 4, 4 }, | |
10184 | #define SH_BLTIN_V8QI3 4 | |
10185 | { 4, 4, 4 }, | |
10186 | #define SH_BLTIN_MAC_HISI 5 | |
10187 | { 1, 4, 4, 1 }, | |
10188 | #define SH_BLTIN_SH_HI 6 | |
10189 | { 4, 4, 1 }, | |
10190 | #define SH_BLTIN_SH_SI 7 | |
10191 | { 4, 4, 1 }, | |
10192 | #define SH_BLTIN_V4HI2V2SI 8 | |
10193 | { 4, 4, 4 }, | |
10194 | #define SH_BLTIN_V4HI2V8QI 9 | |
10195 | { 4, 4, 4 }, | |
10196 | #define SH_BLTIN_SISF 10 | |
10197 | { 4, 2 }, | |
10198 | #define SH_BLTIN_LDUA_L 11 | |
73a4d10b | 10199 | { 2, 10 }, |
c1b92d09 | 10200 | #define SH_BLTIN_LDUA_Q 12 |
73a4d10b | 10201 | { 1, 10 }, |
c1b92d09 | 10202 | #define SH_BLTIN_STUA_L 13 |
73a4d10b | 10203 | { 0, 10, 2 }, |
c1b92d09 | 10204 | #define SH_BLTIN_STUA_Q 14 |
73a4d10b R |
10205 | { 0, 10, 1 }, |
10206 | #define SH_BLTIN_LDUA_L64 15 | |
10207 | { 2, 9 }, | |
10208 | #define SH_BLTIN_LDUA_Q64 16 | |
10209 | { 1, 9 }, | |
10210 | #define SH_BLTIN_STUA_L64 17 | |
10211 | { 0, 9, 2 }, | |
10212 | #define SH_BLTIN_STUA_Q64 18 | |
10213 | { 0, 9, 1 }, | |
10214 | #define SH_BLTIN_NUM_SHARED_SIGNATURES 19 | |
10215 | #define SH_BLTIN_2 19 | |
10216 | #define SH_BLTIN_SU 19 | |
c1b92d09 | 10217 | { 1, 2 }, |
73a4d10b R |
10218 | #define SH_BLTIN_3 20 |
10219 | #define SH_BLTIN_SUS 20 | |
c1b92d09 | 10220 | { 2, 2, 1 }, |
73a4d10b | 10221 | #define SH_BLTIN_PSSV 21 |
c1b92d09 | 10222 | { 0, 8, 2, 2 }, |
73a4d10b R |
10223 | #define SH_BLTIN_XXUU 22 |
10224 | #define SH_BLTIN_UUUU 22 | |
c1b92d09 | 10225 | { 1, 1, 1, 1 }, |
73a4d10b | 10226 | #define SH_BLTIN_PV 23 |
c1b92d09 | 10227 | { 0, 8 }, |
7d11d296 OE |
10228 | #define SH_BLTIN_VP 24 |
10229 | { 8, 0 }, | |
fe3e478f OE |
10230 | #define SH_BLTIN_UV 25 |
10231 | { 1, 0 }, | |
10232 | #define SH_BLTIN_VU 26 | |
10233 | { 0, 1 }, | |
c1b92d09 | 10234 | }; |
24746a42 | 10235 | /* mcmv: operands considered unsigned. */ |
c1b92d09 | 10236 | /* mmulsum_wq, msad_ubq: result considered unsigned long long. */ |
24746a42 KH |
10237 | /* mperm: control value considered unsigned int. */ |
10238 | /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */ | |
c1b92d09 R |
10239 | /* mshards_q: returns signed short. */ |
10240 | /* nsb: takes long long arg, returns unsigned char. */ | |
1cc24576 KK |
10241 | static struct builtin_description bdesc[] = |
10242 | { | |
fe3e478f OE |
10243 | { sh1_builtin_p, |
10244 | CODE_FOR_sts_fpscr, "__builtin_sh_get_fpscr", SH_BLTIN_UV, 0 }, | |
10245 | { sh1_builtin_p, | |
10246 | CODE_FOR_set_fpscr, "__builtin_sh_set_fpscr", SH_BLTIN_VU, 0 }, | |
c1b92d09 R |
10247 | }; |
10248 | ||
801881b0 KK |
10249 | static tree sh_builtin_get_fpscr; |
10250 | static tree sh_builtin_set_fpscr; | |
10251 | ||
c1b92d09 | 10252 | static void |
6d9e1220 | 10253 | sh_init_builtins (void) |
c1b92d09 R |
10254 | { |
10255 | tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES]; | |
a3acdc0c | 10256 | memset (shared, 0, sizeof shared); |
6d9e1220 OE |
10257 | |
10258 | for (unsigned int di = 0; di < ARRAY_SIZE (bdesc); ++di) | |
c1b92d09 | 10259 | { |
6d9e1220 OE |
10260 | builtin_description* d = &bdesc[di]; |
10261 | ||
10262 | if (!d->is_enabled ()) | |
10263 | continue; | |
10264 | ||
10265 | tree type, arg_type = NULL_TREE; | |
c1b92d09 | 10266 | int signature = d->signature; |
c1b92d09 R |
10267 | |
10268 | if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature]) | |
10269 | type = shared[signature]; | |
10270 | else | |
10271 | { | |
10272 | int has_result = signature_args[signature][0] != 0; | |
4cb44528 | 10273 | tree args[3]; |
c1b92d09 | 10274 | |
c1b92d09 R |
10275 | if (! TARGET_FPU_ANY |
10276 | && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode)) | |
10277 | continue; | |
6d9e1220 | 10278 | for (unsigned int i = 0; i < ARRAY_SIZE (args); i++) |
4cb44528 | 10279 | args[i] = NULL_TREE; |
6d9e1220 | 10280 | for (int i = 3; ; i--) |
c1b92d09 R |
10281 | { |
10282 | int arg = signature_args[signature][i]; | |
10283 | int opno = i - 1 + has_result; | |
10284 | ||
73a4d10b | 10285 | if (arg & 8) |
c1b92d09 R |
10286 | arg_type = ptr_type_node; |
10287 | else if (arg) | |
73a4d10b | 10288 | arg_type = (*lang_hooks.types.type_for_mode) |
6d9e1220 | 10289 | (insn_data[d->icode].operand[opno].mode, (arg & 1)); |
c1b92d09 R |
10290 | else if (i) |
10291 | continue; | |
10292 | else | |
10293 | arg_type = void_type_node; | |
10294 | if (i == 0) | |
10295 | break; | |
4cb44528 | 10296 | args[i-1] = arg_type; |
c1b92d09 | 10297 | } |
4cb44528 NF |
10298 | type = build_function_type_list (arg_type, args[0], args[1], |
10299 | args[2], NULL_TREE); | |
c1b92d09 R |
10300 | if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES) |
10301 | shared[signature] = type; | |
10302 | } | |
1cc24576 KK |
10303 | d->fndecl = |
10304 | add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD, | |
10305 | NULL, NULL_TREE); | |
801881b0 KK |
10306 | /* Recode {sts,set}_fpscr decls for sh_atomic_assign_expand_fenv. */ |
10307 | if (d->icode == CODE_FOR_sts_fpscr) | |
10308 | sh_builtin_get_fpscr = d->fndecl; | |
10309 | else if (d->icode == CODE_FOR_set_fpscr) | |
10310 | sh_builtin_set_fpscr = d->fndecl; | |
c1b92d09 R |
10311 | } |
10312 | } | |
10313 | ||
801881b0 KK |
10314 | /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */ |
10315 | ||
10316 | static void | |
10317 | sh_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) | |
10318 | { | |
10319 | const unsigned SH_FE_INVALID = 64; | |
10320 | const unsigned SH_FE_DIVBYZERO = 32; | |
10321 | const unsigned SH_FE_OVERFLOW = 16; | |
10322 | const unsigned SH_FE_UNDERFLOW = 8; | |
10323 | const unsigned SH_FE_INEXACT = 4; | |
10324 | const unsigned HOST_WIDE_INT SH_FE_ALL_EXCEPT = (SH_FE_INVALID | |
10325 | | SH_FE_DIVBYZERO | |
10326 | | SH_FE_OVERFLOW | |
10327 | | SH_FE_UNDERFLOW | |
10328 | | SH_FE_INEXACT); | |
10329 | const unsigned HOST_WIDE_INT SH_FE_EXCEPT_SHIFT = 5; | |
10330 | tree fenv_var, mask, ld_fenv, masked_fenv; | |
10331 | tree new_fenv_var, reload_fenv, restore_fnenv; | |
10332 | tree update_call, atomic_feraiseexcept, hold_fnclex; | |
10333 | ||
10334 | if (! TARGET_FPU_ANY) | |
10335 | return; | |
10336 | ||
10337 | /* Generate the equivalent of : | |
10338 | unsigned int fenv_var; | |
10339 | fenv_var = __builtin_sh_get_fpscr (); | |
10340 | ||
10341 | unsigned int masked_fenv; | |
10342 | masked_fenv = fenv_var & mask; | |
10343 | ||
10344 | __builtin_sh_set_fpscr (masked_fenv); */ | |
10345 | ||
7c286398 | 10346 | fenv_var = create_tmp_var_raw (unsigned_type_node); |
801881b0 KK |
10347 | mask = build_int_cst (unsigned_type_node, |
10348 | ~((SH_FE_ALL_EXCEPT << SH_FE_EXCEPT_SHIFT) | |
10349 | | SH_FE_ALL_EXCEPT)); | |
10350 | ld_fenv = build2 (MODIFY_EXPR, unsigned_type_node, | |
10351 | fenv_var, build_call_expr (sh_builtin_get_fpscr, 0)); | |
10352 | masked_fenv = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, mask); | |
10353 | hold_fnclex = build_call_expr (sh_builtin_set_fpscr, 1, masked_fenv); | |
7c286398 KK |
10354 | fenv_var = build4 (TARGET_EXPR, unsigned_type_node, fenv_var, |
10355 | build2 (COMPOUND_EXPR, void_type_node, masked_fenv, | |
10356 | ld_fenv), | |
10357 | NULL_TREE, NULL_TREE); | |
10358 | *hold = build2 (COMPOUND_EXPR, void_type_node, fenv_var, hold_fnclex); | |
801881b0 KK |
10359 | |
10360 | /* Store the value of masked_fenv to clear the exceptions: | |
10361 | __builtin_sh_set_fpscr (masked_fenv); */ | |
10362 | ||
10363 | *clear = build_call_expr (sh_builtin_set_fpscr, 1, masked_fenv); | |
10364 | ||
10365 | /* Generate the equivalent of : | |
10366 | unsigned int new_fenv_var; | |
10367 | new_fenv_var = __builtin_sh_get_fpscr (); | |
10368 | ||
10369 | __builtin_sh_set_fpscr (fenv_var); | |
10370 | ||
10371 | __atomic_feraiseexcept (new_fenv_var); */ | |
10372 | ||
7c286398 | 10373 | new_fenv_var = create_tmp_var_raw (unsigned_type_node); |
801881b0 KK |
10374 | reload_fenv = build2 (MODIFY_EXPR, unsigned_type_node, new_fenv_var, |
10375 | build_call_expr (sh_builtin_get_fpscr, 0)); | |
10376 | restore_fnenv = build_call_expr (sh_builtin_set_fpscr, 1, fenv_var); | |
10377 | atomic_feraiseexcept = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT); | |
10378 | update_call = build_call_expr (atomic_feraiseexcept, 1, | |
10379 | fold_convert (integer_type_node, | |
10380 | new_fenv_var)); | |
10381 | *update = build2 (COMPOUND_EXPR, void_type_node, | |
10382 | build2 (COMPOUND_EXPR, void_type_node, | |
10383 | reload_fenv, restore_fnenv), update_call); | |
10384 | } | |
10385 | ||
f676971a EC |
10386 | /* Implements target hook vector_mode_supported_p. */ |
10387 | bool | |
e1fab8ba | 10388 | sh_vector_mode_supported_p (machine_mode mode ATTRIBUTE_UNUSED) |
f676971a | 10389 | { |
f676971a EC |
10390 | return false; |
10391 | } | |
10392 | ||
7a296495 CB |
10393 | bool |
10394 | sh_frame_pointer_required (void) | |
10395 | { | |
10396 | /* If needed override this in other tm.h files to cope with various OS | |
10397 | lossage requiring a frame pointer. */ | |
10398 | if (SUBTARGET_FRAME_POINTER_REQUIRED) | |
10399 | return true; | |
10400 | ||
10401 | if (crtl->profile) | |
10402 | return true; | |
10403 | ||
10404 | return false; | |
10405 | } | |
10406 | ||
a1c496cb EC |
10407 | /* Implements target hook dwarf_calling_convention. Return an enum |
10408 | of dwarf_calling_convention. */ | |
10409 | int | |
3101faab | 10410 | sh_dwarf_calling_convention (const_tree func) |
a1c496cb EC |
10411 | { |
10412 | if (sh_attr_renesas_p (func)) | |
29832164 | 10413 | return DW_CC_GNU_renesas_sh; |
a1c496cb EC |
10414 | |
10415 | return DW_CC_normal; | |
10416 | } | |
10417 | ||
1cc24576 | 10418 | /* Returns the sh builtin decl for CODE. */ |
1cc24576 KK |
10419 | static tree |
10420 | sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) | |
6d9e1220 OE |
10421 | { |
10422 | if (code >= ARRAY_SIZE (bdesc)) | |
10423 | return error_mark_node; | |
10424 | ||
10425 | if (!bdesc[code].is_enabled ()) | |
10426 | return error_mark_node; | |
10427 | ||
10428 | return bdesc[code].fndecl; | |
1cc24576 KK |
10429 | } |
10430 | ||
c1b92d09 R |
10431 | /* Expand an expression EXP that calls a built-in function, |
10432 | with result going to TARGET if that's convenient | |
10433 | (and in mode MODE if that's convenient). | |
10434 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
10435 | IGNORE is nonzero if the value is to be ignored. */ | |
c1b92d09 | 10436 | static rtx |
cf277499 | 10437 | sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
ef4bddc2 | 10438 | machine_mode mode ATTRIBUTE_UNUSED, int ignore) |
c1b92d09 | 10439 | { |
5039610b | 10440 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
c1b92d09 R |
10441 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
10442 | const struct builtin_description *d = &bdesc[fcode]; | |
10443 | enum insn_code icode = d->icode; | |
10444 | int signature = d->signature; | |
6d9e1220 | 10445 | int nop = 0; |
c1b92d09 | 10446 | rtx op[4]; |
c1b92d09 R |
10447 | |
10448 | if (signature_args[signature][0]) | |
10449 | { | |
10450 | if (ignore) | |
23d0939b | 10451 | return NULL_RTX; |
c1b92d09 | 10452 | |
ef4bddc2 | 10453 | machine_mode tmode = insn_data[icode].operand[0].mode; |
6d9e1220 | 10454 | if (! target || GET_MODE (target) != tmode |
c1b92d09 R |
10455 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) |
10456 | target = gen_reg_rtx (tmode); | |
10457 | op[nop++] = target; | |
10458 | } | |
10459 | else | |
6d9e1220 | 10460 | target = NULL_RTX; |
c1b92d09 | 10461 | |
6d9e1220 | 10462 | for (int i = 1; i <= 3; i++, nop++) |
c1b92d09 | 10463 | { |
c1b92d09 R |
10464 | if (! signature_args[signature][i]) |
10465 | break; | |
df4bacab | 10466 | tree arg = CALL_EXPR_ARG (exp, i - 1); |
3578cf63 R |
10467 | if (arg == error_mark_node) |
10468 | return const0_rtx; | |
df4bacab OE |
10469 | |
10470 | machine_mode opmode; | |
10471 | tree optype; | |
73a4d10b R |
10472 | if (signature_args[signature][i] & 8) |
10473 | { | |
10474 | opmode = ptr_mode; | |
10475 | optype = ptr_type_node; | |
10476 | } | |
10477 | else | |
10478 | { | |
10479 | opmode = insn_data[icode].operand[nop].mode; | |
10480 | optype = (*lang_hooks.types.type_for_mode) (opmode, 0); | |
10481 | } | |
df4bacab OE |
10482 | |
10483 | machine_mode argmode = TYPE_MODE (TREE_TYPE (arg)); | |
c1b92d09 | 10484 | if (argmode != opmode) |
73a4d10b | 10485 | arg = build1 (NOP_EXPR, optype, arg); |
b757d36f | 10486 | op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL); |
c1b92d09 R |
10487 | if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode)) |
10488 | op[nop] = copy_to_mode_reg (opmode, op[nop]); | |
10489 | } | |
10490 | ||
6d9e1220 OE |
10491 | rtx pat = NULL_RTX; |
10492 | ||
c1b92d09 R |
10493 | switch (nop) |
10494 | { | |
10495 | case 1: | |
10496 | pat = (*insn_data[d->icode].genfun) (op[0]); | |
10497 | break; | |
10498 | case 2: | |
10499 | pat = (*insn_data[d->icode].genfun) (op[0], op[1]); | |
10500 | break; | |
10501 | case 3: | |
10502 | pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]); | |
10503 | break; | |
10504 | case 4: | |
10505 | pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]); | |
10506 | break; | |
95c0af87 | 10507 | default: |
f5b9e7c9 | 10508 | gcc_unreachable (); |
c1b92d09 R |
10509 | } |
10510 | if (! pat) | |
23d0939b | 10511 | return NULL_RTX; |
c1b92d09 R |
10512 | emit_insn (pat); |
10513 | return target; | |
10514 | } | |
0ac78517 | 10515 | |
c43f4279 RS |
10516 | /* Implement TARGET_HARD_REGNO_NREGS. On the SH all but the XD regs are |
10517 | UNITS_PER_WORD bits wide. */ | |
10518 | ||
10519 | static unsigned int | |
10520 | sh_hard_regno_nregs (unsigned int regno, machine_mode mode) | |
10521 | { | |
10522 | if (XD_REGISTER_P (regno)) | |
10523 | return CEIL (GET_MODE_SIZE (mode), 2 * UNITS_PER_WORD); | |
10524 | return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD); | |
10525 | } | |
10526 | ||
f939c3e6 RS |
10527 | /* Implement TARGET_HARD_REGNO_MODE_OK. |
10528 | ||
347146a4 KK |
10529 | We can allow any mode in any general register. The special registers |
10530 | only allow SImode. Don't allow any mode in the PR. | |
10531 | ||
10532 | We cannot hold DCmode values in the XD registers because alter_reg | |
10533 | handles subregs of them incorrectly. We could work around this by | |
10534 | spacing the XD registers like the DR registers, but this would require | |
10535 | additional memory in every compilation to hold larger register vectors. | |
10536 | We could hold SFmode / SCmode values in XD registers, but that | |
10537 | would require a tertiary reload when reloading from / to memory, | |
10538 | and a secondary reload to reload from / to general regs; that | |
073a8998 | 10539 | seems to be a losing proposition. |
347146a4 KK |
10540 | |
10541 | We want to allow TImode FP regs so that when V4SFmode is loaded as TImode, | |
10542 | it won't be ferried through GP registers first. */ | |
f939c3e6 | 10543 | static bool |
ef4bddc2 | 10544 | sh_hard_regno_mode_ok (unsigned int regno, machine_mode mode) |
347146a4 KK |
10545 | { |
10546 | if (SPECIAL_REGISTER_P (regno)) | |
10547 | return mode == SImode; | |
10548 | ||
10549 | if (regno == FPUL_REG) | |
10550 | return (mode == SImode || mode == SFmode); | |
10551 | ||
10552 | if (FP_REGISTER_P (regno) && mode == SFmode) | |
10553 | return true; | |
10554 | ||
10555 | if (mode == V2SFmode) | |
10556 | { | |
10557 | if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0) | |
10558 | || GENERAL_REGISTER_P (regno))) | |
10559 | return true; | |
10560 | else | |
10561 | return false; | |
10562 | } | |
10563 | ||
10564 | if (mode == V4SFmode) | |
10565 | { | |
10566 | if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0) | |
10567 | || GENERAL_REGISTER_P (regno)) | |
10568 | return true; | |
10569 | else | |
10570 | return false; | |
10571 | } | |
10572 | ||
10573 | if (mode == V16SFmode) | |
e1fab8ba | 10574 | return regno == FIRST_XD_REG; |
347146a4 KK |
10575 | |
10576 | if (FP_REGISTER_P (regno)) | |
10577 | { | |
10578 | if (mode == SFmode | |
10579 | || mode == SImode | |
e1fab8ba | 10580 | || ((TARGET_SH2E) && mode == SCmode) |
d5dd0a62 | 10581 | || (((TARGET_FPU_DOUBLE && mode == DFmode) || mode == DCmode) |
347146a4 | 10582 | && ((regno - FIRST_FP_REG) & 1) == 0) |
e1fab8ba | 10583 | || (TARGET_SH4 && mode == TImode |
347146a4 KK |
10584 | && ((regno - FIRST_FP_REG) & 3) == 0)) |
10585 | return true; | |
10586 | else | |
10587 | return false; | |
10588 | } | |
10589 | ||
10590 | if (XD_REGISTER_P (regno)) | |
10591 | return mode == DFmode; | |
10592 | ||
347146a4 KK |
10593 | if (regno == PR_REG) |
10594 | return mode == SImode; | |
10595 | ||
10596 | if (regno == FPSCR_REG) | |
fe3e478f | 10597 | return mode == SImode; |
347146a4 | 10598 | |
347146a4 KK |
10599 | return true; |
10600 | } | |
10601 | ||
99e1629f RS |
10602 | /* Implement TARGET_MODES_TIEABLE_P. |
10603 | ||
10604 | If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1 | |
10605 | and MODE2, for any hard reg, then this must be false for correct output. | |
10606 | That's the case for xd registers: we don't hold SFmode values in | |
10607 | them, so we can't tie an SFmode pseudos with one in another | |
10608 | floating-point mode. */ | |
10609 | ||
10610 | static bool | |
10611 | sh_modes_tieable_p (machine_mode mode1, machine_mode mode2) | |
10612 | { | |
10613 | return (mode1 == mode2 | |
10614 | || (GET_MODE_CLASS (mode1) == GET_MODE_CLASS (mode2) | |
10615 | && (mode1 != SFmode && mode2 != SFmode))); | |
10616 | } | |
10617 | ||
fc1fcfa0 | 10618 | /* Specify the modes required to caller save a given hard regno. |
f939c3e6 | 10619 | choose_hard_reg_mode chooses mode based on TARGET_HARD_REGNO_MODE_OK |
fc1fcfa0 KK |
10620 | and returns ?Imode for float regs when sh_hard_regno_mode_ok |
10621 | permits integer modes on them. That makes LRA's split process | |
10622 | unhappy. See PR55212. | |
10623 | */ | |
10624 | machine_mode | |
10625 | sh_hard_regno_caller_save_mode (unsigned int regno, unsigned int nregs, | |
10626 | machine_mode mode) | |
10627 | { | |
10628 | if (FP_REGISTER_P (regno) | |
10629 | && (mode == SFmode | |
10630 | || mode == SCmode | |
10631 | || ((mode == DFmode || mode == DCmode) | |
10632 | && ((regno - FIRST_FP_REG) & 1) == 0))) | |
10633 | return mode; | |
10634 | ||
10635 | return choose_hard_reg_mode (regno, nregs, false); | |
10636 | } | |
10637 | ||
0d803030 RS |
10638 | /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */ |
10639 | static bool | |
10640 | sh_can_change_mode_class (machine_mode from, machine_mode to, | |
10641 | reg_class_t rclass) | |
cff9f8d5 | 10642 | { |
312209c6 AO |
10643 | /* We want to enable the use of SUBREGs as a means to |
10644 | VEC_SELECT a single element of a vector. */ | |
344332e8 OE |
10645 | |
10646 | /* This effectively disallows using GENERAL_REGS for SFmode vector subregs. | |
10647 | This can be problematic when SFmode vector subregs need to be accessed | |
10648 | on the stack with displacement addressing, as it happens with -O0. | |
10649 | Thus we disallow the mode change for -O0. */ | |
312209c6 | 10650 | if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode) |
0d803030 | 10651 | return optimize ? !reg_classes_intersect_p (GENERAL_REGS, rclass) : true; |
312209c6 | 10652 | |
cff9f8d5 AH |
10653 | if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to)) |
10654 | { | |
832a3292 KH |
10655 | if (TARGET_LITTLE_ENDIAN) |
10656 | { | |
10657 | if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8) | |
0d803030 | 10658 | return !reg_classes_intersect_p (DF_REGS, rclass); |
832a3292 KH |
10659 | } |
10660 | else | |
10661 | { | |
10662 | if (GET_MODE_SIZE (from) < 8) | |
0d803030 | 10663 | return !reg_classes_intersect_p (DF_REGS, rclass); |
832a3292 | 10664 | } |
cff9f8d5 | 10665 | } |
0d803030 | 10666 | return true; |
cff9f8d5 AH |
10667 | } |
10668 | ||
42db504c SB |
10669 | /* Return true if registers in machine mode MODE will likely be |
10670 | allocated to registers in small register classes. */ | |
9c265c4d | 10671 | bool |
ef4bddc2 | 10672 | sh_small_register_classes_for_mode_p (machine_mode mode ATTRIBUTE_UNUSED) |
42db504c | 10673 | { |
e1fab8ba | 10674 | return true; |
42db504c | 10675 | } |
ea4210ef RS |
10676 | |
10677 | /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times | |
10678 | that label is used. */ | |
ea4210ef | 10679 | void |
cf277499 | 10680 | sh_mark_label (rtx address, int nuses) |
ea4210ef RS |
10681 | { |
10682 | if (GOTOFF_P (address)) | |
10683 | { | |
10684 | /* Extract the label or symbol. */ | |
10685 | address = XEXP (address, 0); | |
10686 | if (GET_CODE (address) == PLUS) | |
10687 | address = XEXP (address, 0); | |
10688 | address = XVECEXP (address, 0, 0); | |
10689 | } | |
10690 | if (GET_CODE (address) == LABEL_REF | |
f3536097 | 10691 | && LABEL_P (XEXP (address, 0))) |
ea4210ef RS |
10692 | LABEL_NUSES (XEXP (address, 0)) += nuses; |
10693 | } | |
10694 | ||
95c0af87 | 10695 | /* Compute extra cost of moving data between one register class |
50fe8924 | 10696 | and another. |
95c0af87 | 10697 | |
50fe8924 | 10698 | If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass |
ec555f32 | 10699 | uses this information. Hence, the general register <-> floating point |
95c0af87 | 10700 | register information here is not used for SFmode. */ |
e7a8f681 | 10701 | static int |
ef4bddc2 | 10702 | sh_register_move_cost (machine_mode mode, |
e7a8f681 | 10703 | reg_class_t srcclass, reg_class_t dstclass) |
95c0af87 JR |
10704 | { |
10705 | if (dstclass == T_REGS || dstclass == PR_REGS) | |
10706 | return 10; | |
10707 | ||
b1dcf523 DD |
10708 | if (dstclass == MAC_REGS && srcclass == MAC_REGS) |
10709 | return 4; | |
10710 | ||
e1fab8ba | 10711 | if (mode == SImode && TARGET_FMOVD |
ec555f32 R |
10712 | && REGCLASS_HAS_FP_REG (srcclass) |
10713 | && REGCLASS_HAS_FP_REG (dstclass)) | |
10714 | return 4; | |
10715 | ||
9c24200c KK |
10716 | if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS) |
10717 | return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7); | |
10718 | ||
a60a9553 | 10719 | if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS) |
832a3292 | 10720 | || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass))) |
a60a9553 R |
10721 | return 9; |
10722 | ||
95c0af87 JR |
10723 | if ((REGCLASS_HAS_FP_REG (dstclass) |
10724 | && REGCLASS_HAS_GENERAL_REG (srcclass)) | |
10725 | || (REGCLASS_HAS_GENERAL_REG (dstclass) | |
10726 | && REGCLASS_HAS_FP_REG (srcclass))) | |
4978c736 KK |
10727 | { |
10728 | /* Discourage trying to use fp regs for a pointer. This also | |
10729 | discourages fp regs with SImode because Pmode is an alias | |
10730 | of SImode on this target. See PR target/48596. */ | |
10731 | int addend = (mode == Pmode) ? 40 : 0; | |
10732 | ||
e1fab8ba OE |
10733 | return ((TARGET_FMOVD ? 8 : 12) + addend) |
10734 | * ((GET_MODE_SIZE (mode) + 7) / 8U); | |
4978c736 | 10735 | } |
95c0af87 JR |
10736 | |
10737 | if ((dstclass == FPUL_REGS | |
10738 | && REGCLASS_HAS_GENERAL_REG (srcclass)) | |
10739 | || (srcclass == FPUL_REGS | |
10740 | && REGCLASS_HAS_GENERAL_REG (dstclass))) | |
10741 | return 5; | |
10742 | ||
10743 | if ((dstclass == FPUL_REGS | |
10744 | && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS)) | |
f676971a | 10745 | || (srcclass == FPUL_REGS |
95c0af87 JR |
10746 | && (dstclass == PR_REGS || dstclass == MAC_REGS))) |
10747 | return 7; | |
10748 | ||
95c0af87 JR |
10749 | if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass)) |
10750 | || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass))) | |
10751 | return 4; | |
10752 | ||
e1fab8ba OE |
10753 | if (TARGET_FMOVD |
10754 | && ! REGCLASS_HAS_GENERAL_REG (srcclass) | |
10755 | && ! REGCLASS_HAS_GENERAL_REG (dstclass)) | |
ec555f32 R |
10756 | return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U); |
10757 | ||
10758 | return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U); | |
95c0af87 JR |
10759 | } |
10760 | ||
1aa03f38 | 10761 | static rtx |
cf277499 | 10762 | emit_load_ptr (rtx reg, rtx addr) |
1aa03f38 | 10763 | { |
57d38024 | 10764 | rtx mem = gen_const_mem (ptr_mode, addr); |
1aa03f38 R |
10765 | |
10766 | if (Pmode != ptr_mode) | |
10767 | mem = gen_rtx_SIGN_EXTEND (Pmode, mem); | |
10768 | return emit_move_insn (reg, mem); | |
10769 | } | |
10770 | ||
73a4d10b | 10771 | static void |
cf277499 SB |
10772 | sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
10773 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
10774 | tree function) | |
1aa03f38 R |
10775 | { |
10776 | CUMULATIVE_ARGS cum; | |
10777 | int structure_value_byref = 0; | |
6cb7eb41 DM |
10778 | rtx this_rtx, this_value, sibcall, funexp; |
10779 | rtx_insn *insns; | |
1aa03f38 | 10780 | tree funtype = TREE_TYPE (function); |
735cb76e | 10781 | int simple_add = CONST_OK_FOR_ADD (delta); |
1aa03f38 R |
10782 | int did_load = 0; |
10783 | rtx scratch0, scratch1, scratch2; | |
10784 | ||
10785 | reload_completed = 1; | |
fe3ad572 | 10786 | epilogue_completed = 1; |
416ff32e | 10787 | crtl->uses_only_leaf_regs = 1; |
1aa03f38 | 10788 | |
2e040219 | 10789 | emit_note (NOTE_INSN_PROLOGUE_END); |
1aa03f38 R |
10790 | |
10791 | /* Find the "this" pointer. We have such a wide range of ABIs for the | |
10792 | SH that it's best to do this completely machine independently. | |
f676971a | 10793 | "this" is passed as first argument, unless a structure return pointer |
1aa03f38 | 10794 | comes first, in which case "this" comes second. */ |
0f6937fe | 10795 | INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1); |
1aa03f38 | 10796 | #ifndef PCC_STATIC_STRUCT_RETURN |
61f71b34 | 10797 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
1aa03f38 R |
10798 | structure_value_byref = 1; |
10799 | #endif /* not PCC_STATIC_STRUCT_RETURN */ | |
61f71b34 | 10800 | if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0) |
f676971a | 10801 | { |
1aa03f38 R |
10802 | tree ptype = build_pointer_type (TREE_TYPE (funtype)); |
10803 | ||
d5cc9181 | 10804 | sh_function_arg_advance (pack_cumulative_args (&cum), Pmode, ptype, true); |
1aa03f38 | 10805 | } |
d5cc9181 JR |
10806 | this_rtx |
10807 | = sh_function_arg (pack_cumulative_args (&cum), Pmode, ptr_type_node, true); | |
1aa03f38 R |
10808 | |
10809 | /* For SHcompact, we only have r0 for a scratch register: r1 is the | |
10810 | static chain pointer (even if you can't have nested virtual functions | |
10811 | right now, someone might implement them sometime), and the rest of the | |
10812 | registers are used for argument passing, are callee-saved, or reserved. */ | |
73a4d10b R |
10813 | /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg / |
10814 | -ffixed-reg has been used. */ | |
10815 | if (! call_used_regs[0] || fixed_regs[0]) | |
10816 | error ("r0 needs to be available as a call-clobbered register"); | |
1aa03f38 | 10817 | scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0); |
e1fab8ba | 10818 | |
1aa03f38 | 10819 | { |
73a4d10b R |
10820 | if (call_used_regs[1] && ! fixed_regs[1]) |
10821 | scratch1 = gen_rtx_REG (ptr_mode, 1); | |
1aa03f38 R |
10822 | /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer |
10823 | pointing where to return struct values. */ | |
73a4d10b R |
10824 | if (call_used_regs[3] && ! fixed_regs[3]) |
10825 | scratch2 = gen_rtx_REG (Pmode, 3); | |
1aa03f38 | 10826 | } |
1aa03f38 | 10827 | |
0a81f074 | 10828 | this_value = plus_constant (Pmode, this_rtx, delta); |
1aa03f38 R |
10829 | if (vcall_offset |
10830 | && (simple_add || scratch0 != scratch1) | |
10831 | && strict_memory_address_p (ptr_mode, this_value)) | |
10832 | { | |
10833 | emit_load_ptr (scratch0, this_value); | |
10834 | did_load = 1; | |
10835 | } | |
10836 | ||
10837 | if (!delta) | |
10838 | ; /* Do nothing. */ | |
10839 | else if (simple_add) | |
0a2aaacc | 10840 | emit_move_insn (this_rtx, this_value); |
1aa03f38 R |
10841 | else |
10842 | { | |
10843 | emit_move_insn (scratch1, GEN_INT (delta)); | |
0a2aaacc | 10844 | emit_insn (gen_add2_insn (this_rtx, scratch1)); |
1aa03f38 R |
10845 | } |
10846 | ||
10847 | if (vcall_offset) | |
10848 | { | |
10849 | rtx offset_addr; | |
10850 | ||
10851 | if (!did_load) | |
0a2aaacc | 10852 | emit_load_ptr (scratch0, this_rtx); |
1aa03f38 | 10853 | |
0a81f074 | 10854 | offset_addr = plus_constant (Pmode, scratch0, vcall_offset); |
1aa03f38 R |
10855 | if (strict_memory_address_p (ptr_mode, offset_addr)) |
10856 | ; /* Do nothing. */ | |
e1fab8ba | 10857 | else if (scratch0 != scratch1) |
1aa03f38 R |
10858 | { |
10859 | /* scratch0 != scratch1, and we have indexed loads. Get better | |
10860 | schedule by loading the offset into r1 and using an indexed | |
10861 | load - then the load of r1 can issue before the load from | |
50fe8924 | 10862 | (this_rtx + delta) finishes. */ |
1aa03f38 R |
10863 | emit_move_insn (scratch1, GEN_INT (vcall_offset)); |
10864 | offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1); | |
10865 | } | |
735cb76e | 10866 | else if (CONST_OK_FOR_ADD (vcall_offset)) |
1aa03f38 R |
10867 | { |
10868 | emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset))); | |
10869 | offset_addr = scratch0; | |
10870 | } | |
10871 | else if (scratch0 != scratch1) | |
10872 | { | |
10873 | emit_move_insn (scratch1, GEN_INT (vcall_offset)); | |
10874 | emit_insn (gen_add2_insn (scratch0, scratch1)); | |
10875 | offset_addr = scratch0; | |
10876 | } | |
10877 | else | |
f5b9e7c9 | 10878 | gcc_unreachable (); /* FIXME */ |
1aa03f38 R |
10879 | emit_load_ptr (scratch0, offset_addr); |
10880 | ||
832a3292 | 10881 | if (Pmode != ptr_mode) |
1aa03f38 | 10882 | scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0); |
0a2aaacc | 10883 | emit_insn (gen_add2_insn (this_rtx, scratch0)); |
1aa03f38 R |
10884 | } |
10885 | ||
10886 | /* Generate a tail call to the target function. */ | |
10887 | if (! TREE_USED (function)) | |
10888 | { | |
10889 | assemble_external (function); | |
10890 | TREE_USED (function) = 1; | |
10891 | } | |
10892 | funexp = XEXP (DECL_RTL (function), 0); | |
73a4d10b R |
10893 | /* If the function is overridden, so is the thunk, hence we don't |
10894 | need GOT addressing even if this is a public symbol. */ | |
10895 | #if 0 | |
10896 | if (TARGET_SH1 && ! flag_weak) | |
10897 | sibcall = gen_sibcalli_thunk (funexp, const0_rtx); | |
10898 | else | |
10899 | #endif | |
10900 | if (TARGET_SH2 && flag_pic) | |
10901 | { | |
1e44e857 DJ |
10902 | if (TARGET_FDPIC) |
10903 | { | |
10904 | sibcall = gen_sibcall_pcrel_fdpic (funexp, const0_rtx); | |
10905 | XEXP (XVECEXP (sibcall, 0, 3), 0) = scratch2; | |
10906 | } | |
10907 | else | |
10908 | { | |
10909 | sibcall = gen_sibcall_pcrel (funexp, const0_rtx); | |
10910 | XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2; | |
10911 | } | |
73a4d10b R |
10912 | } |
10913 | else | |
10914 | { | |
73a4d10b R |
10915 | emit_move_insn (scratch2, funexp); |
10916 | funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2); | |
10917 | sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX); | |
10918 | } | |
10919 | sibcall = emit_call_insn (sibcall); | |
1aa03f38 | 10920 | SIBLING_CALL_P (sibcall) = 1; |
0a2aaacc | 10921 | use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx); |
1aa03f38 R |
10922 | emit_barrier (); |
10923 | ||
a2855205 | 10924 | /* Run just enough of rest_of_compilation to do scheduling and get |
1aa03f38 R |
10925 | the insns emitted. Note that use_thunk calls |
10926 | assemble_start_function and assemble_end_function. */ | |
a2855205 | 10927 | |
1aa03f38 R |
10928 | insns = get_insns (); |
10929 | ||
6fb5fa3c DB |
10930 | if (optimize > 0) |
10931 | { | |
10932 | if (! cfun->cfg) | |
eb6cbf91 | 10933 | init_flow (cfun); |
6fb5fa3c DB |
10934 | split_all_insns_noflow (); |
10935 | } | |
1aa03f38 | 10936 | |
18dbd950 | 10937 | sh_reorg (); |
1aa03f38 R |
10938 | shorten_branches (insns); |
10939 | final_start_function (insns, file, 1); | |
c9d691e9 | 10940 | final (insns, file, 1); |
1aa03f38 R |
10941 | final_end_function (); |
10942 | ||
1aa03f38 | 10943 | reload_completed = 0; |
fe3ad572 | 10944 | epilogue_completed = 0; |
1aa03f38 R |
10945 | } |
10946 | ||
1e44e857 DJ |
10947 | /* Return an RTX pair for the address and call site label of a function |
10948 | NAME of kind KIND, placing the result in TARGET if not NULL. For | |
10949 | SFUNC_STATIC, if FDPIC, the LAB member of result will be set to | |
10950 | (const_int 0) if jsr should be used, or a label_ref if bsrf should | |
10951 | be used. For FDPIC, both SFUNC_GOT and SFUNC_STATIC will return the | |
10952 | address of the function itself, not a function descriptor, so they | |
10953 | can only be used with functions not using the FDPIC register that | |
10954 | are known to be called directory without a PLT entry. */ | |
73a4d10b | 10955 | |
1e44e857 DJ |
10956 | function_symbol_result |
10957 | function_symbol (rtx target, const char *name, sh_function_kind kind) | |
10958 | { | |
73a4d10b R |
10959 | /* If this is not an ordinary function, the name usually comes from a |
10960 | string literal or an sprintf buffer. Make sure we use the same | |
10961 | string consistently, so that cse will be able to unify address loads. */ | |
10962 | if (kind != FUNCTION_ORDINARY) | |
10963 | name = IDENTIFIER_POINTER (get_identifier (name)); | |
1e44e857 DJ |
10964 | rtx sym = gen_rtx_SYMBOL_REF (Pmode, name); |
10965 | rtx lab = const0_rtx; | |
90534361 | 10966 | SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION; |
73a4d10b R |
10967 | if (flag_pic) |
10968 | switch (kind) | |
10969 | { | |
10970 | case FUNCTION_ORDINARY: | |
10971 | break; | |
10972 | case SFUNC_GOT: | |
10973 | { | |
10974 | rtx reg = target ? target : gen_reg_rtx (Pmode); | |
10975 | ||
10976 | emit_insn (gen_symGOT2reg (reg, sym)); | |
10977 | sym = reg; | |
10978 | break; | |
10979 | } | |
10980 | case SFUNC_STATIC: | |
10981 | { | |
73a4d10b R |
10982 | rtx reg = target ? target : gen_reg_rtx (Pmode); |
10983 | ||
1e44e857 DJ |
10984 | if (TARGET_FDPIC) |
10985 | { | |
10986 | /* We use PC-relative calls, since GOTOFF can only refer | |
10987 | to writable data. This works along with sh_sfunc_call. */ | |
10988 | lab = PATTERN (gen_call_site ()); | |
10989 | emit_insn (gen_sym_label2reg (reg, sym, lab)); | |
10990 | } | |
10991 | else | |
10992 | { | |
10993 | /* ??? To allow cse to work, we use GOTOFF relocations. | |
10994 | we could add combiner patterns to transform this into | |
10995 | straight pc-relative calls with sym2PIC / bsrf when | |
10996 | label load and function call are still 1:1 and in the | |
10997 | same basic block during combine. */ | |
10998 | emit_insn (gen_symGOTOFF2reg (reg, sym)); | |
10999 | } | |
11000 | ||
73a4d10b R |
11001 | sym = reg; |
11002 | break; | |
11003 | } | |
11004 | } | |
11005 | if (target && sym != target) | |
11006 | { | |
11007 | emit_move_insn (target, sym); | |
1e44e857 | 11008 | return function_symbol_result (target, lab); |
73a4d10b | 11009 | } |
1e44e857 | 11010 | return function_symbol_result (sym, lab); |
90534361 R |
11011 | } |
11012 | ||
df4bacab OE |
11013 | /* Find the number of the first general purpose register in S that |
11014 | is not set. */ | |
fada1961 R |
11015 | static int |
11016 | scavenge_reg (HARD_REG_SET *s) | |
11017 | { | |
df4bacab | 11018 | for (int r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++) |
fada1961 R |
11019 | if (TEST_HARD_REG_BIT (*s, r)) |
11020 | return r; | |
11021 | return -1; | |
11022 | } | |
11023 | ||
11024 | rtx | |
11025 | sh_get_pr_initial_val (void) | |
11026 | { | |
7d73a2ba R |
11027 | /* If we haven't finished rtl generation, there might be a nonlocal label |
11028 | that we haven't seen yet. | |
b3a13419 ILT |
11029 | ??? get_hard_reg_initial_val fails if it is called after register |
11030 | allocation has started, unless it has been called before for the | |
11031 | same register. And even then, we end in trouble if we didn't use | |
11032 | the register in the same basic block before. So call | |
11033 | get_hard_reg_initial_val now and wrap it in an unspec if we might | |
11034 | need to replace it. */ | |
dce20bbc R |
11035 | /* ??? We also must do this for TARGET_SH1 in general, because otherwise |
11036 | combine can put the pseudo returned by get_hard_reg_initial_val into | |
11037 | instructions that need a general purpose registers, which will fail to | |
11038 | be recognized when the pseudo becomes allocated to PR. */ | |
e1fab8ba OE |
11039 | rtx val = get_hard_reg_initial_val (Pmode, PR_REG); |
11040 | return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA); | |
fada1961 R |
11041 | } |
11042 | ||
10c17a58 | 11043 | bool |
f90b7a5a | 11044 | sh_expand_t_scc (rtx operands[]) |
3db1b434 | 11045 | { |
f90b7a5a PB |
11046 | enum rtx_code code = GET_CODE (operands[1]); |
11047 | rtx target = operands[0]; | |
11048 | rtx op0 = operands[2]; | |
11049 | rtx op1 = operands[3]; | |
3db1b434 | 11050 | rtx result = target; |
3db1b434 | 11051 | |
f3536097 SZ |
11052 | if (!REG_P (op0) || REGNO (op0) != T_REG |
11053 | || !CONST_INT_P (op1)) | |
10c17a58 | 11054 | return false; |
f3536097 | 11055 | if (!REG_P (result)) |
3db1b434 | 11056 | result = gen_reg_rtx (SImode); |
df4bacab | 11057 | HOST_WIDE_INT val = INTVAL (op1); |
3db1b434 | 11058 | if ((code == EQ && val == 1) || (code == NE && val == 0)) |
f031c344 | 11059 | emit_insn (gen_movt (result, get_t_reg_rtx ())); |
3db1b434 | 11060 | else if ((code == EQ && val == 0) || (code == NE && val == 1)) |
78ff60c1 | 11061 | emit_insn (gen_movnegt (result, get_t_reg_rtx ())); |
3db1b434 R |
11062 | else if (code == EQ || code == NE) |
11063 | emit_insn (gen_move_insn (result, GEN_INT (code == NE))); | |
11064 | else | |
10c17a58 | 11065 | return false; |
3db1b434 R |
11066 | if (result != target) |
11067 | emit_move_insn (target, result); | |
10c17a58 | 11068 | return true; |
3db1b434 R |
11069 | } |
11070 | ||
07d7d2f4 R |
11071 | /* INSN is an sfunc; return the rtx that describes the address used. */ |
11072 | static rtx | |
11073 | extract_sfunc_addr (rtx insn) | |
11074 | { | |
df4bacab OE |
11075 | rtx pattern = PATTERN (insn); |
11076 | const int len = XVECLEN (pattern, 0); | |
11077 | for (int i = 0; i < len; i++) | |
07d7d2f4 | 11078 | { |
df4bacab | 11079 | rtx part = XVECEXP (pattern, 0, i); |
07d7d2f4 R |
11080 | if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode |
11081 | && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0)))) | |
11082 | return XEXP (part, 0); | |
11083 | } | |
f5b9e7c9 NS |
11084 | gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE); |
11085 | return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1); | |
07d7d2f4 R |
11086 | } |
11087 | ||
11088 | /* Verify that the register in use_sfunc_addr still agrees with the address | |
11089 | used in the sfunc. This prevents fill_slots_from_thread from changing | |
11090 | use_sfunc_addr. | |
11091 | INSN is the use_sfunc_addr instruction, and REG is the register it | |
11092 | guards. */ | |
aaf701c5 | 11093 | bool |
b32d5189 | 11094 | check_use_sfunc_addr (rtx_insn *insn, rtx reg) |
07d7d2f4 R |
11095 | { |
11096 | /* Search for the sfunc. It should really come right after INSN. */ | |
11097 | while ((insn = NEXT_INSN (insn))) | |
11098 | { | |
f3536097 | 11099 | if (LABEL_P (insn) || JUMP_P (insn)) |
07d7d2f4 R |
11100 | break; |
11101 | if (! INSN_P (insn)) | |
11102 | continue; | |
f676971a | 11103 | |
b32d5189 DM |
11104 | if (rtx_sequence *seq = dyn_cast<rtx_sequence *> (PATTERN (insn))) |
11105 | insn = seq->insn (0); | |
07d7d2f4 R |
11106 | if (GET_CODE (PATTERN (insn)) != PARALLEL |
11107 | || get_attr_type (insn) != TYPE_SFUNC) | |
11108 | continue; | |
11109 | return rtx_equal_p (extract_sfunc_addr (insn), reg); | |
11110 | } | |
f5b9e7c9 | 11111 | gcc_unreachable (); |
07d7d2f4 R |
11112 | } |
11113 | ||
db292b0e OE |
11114 | /* This function returns a constant rtx that represents 2**15 / pi in |
11115 | SFmode. It's used to scale a fixed-point signed 16.16-bit fraction | |
11116 | of a full circle back to an SFmode value, i.e. 0x10000 maps to 2*pi. */ | |
312209c6 AO |
11117 | static GTY(()) rtx sh_fsca_sf2int_rtx; |
11118 | ||
11119 | rtx | |
11120 | sh_fsca_sf2int (void) | |
11121 | { | |
11122 | if (! sh_fsca_sf2int_rtx) | |
11123 | { | |
11124 | REAL_VALUE_TYPE rv; | |
11125 | ||
11126 | real_from_string (&rv, "10430.378350470453"); | |
11127 | sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode); | |
11128 | } | |
11129 | ||
11130 | return sh_fsca_sf2int_rtx; | |
11131 | } | |
f676971a | 11132 | |
db292b0e OE |
11133 | /* This function returns a constant rtx that represents pi / 2**15 in |
11134 | SFmode. It's used to scale SFmode angles, in radians, to a | |
11135 | fixed-point signed 16.16-bit fraction of a full circle, i.e. 2*pi | |
11136 | maps to 0x10000. */ | |
312209c6 AO |
11137 | static GTY(()) rtx sh_fsca_int2sf_rtx; |
11138 | ||
11139 | rtx | |
11140 | sh_fsca_int2sf (void) | |
11141 | { | |
11142 | if (! sh_fsca_int2sf_rtx) | |
11143 | { | |
11144 | REAL_VALUE_TYPE rv; | |
11145 | ||
11146 | real_from_string (&rv, "9.587379924285257e-5"); | |
11147 | sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode); | |
11148 | } | |
11149 | ||
11150 | return sh_fsca_int2sf_rtx; | |
11151 | } | |
cc15e98f | 11152 | |
8b0add27 | 11153 | /* Initialize the CUMULATIVE_ARGS structure. */ |
cc15e98f NC |
11154 | void |
11155 | sh_init_cumulative_args (CUMULATIVE_ARGS * pcum, | |
50fe8924 | 11156 | tree fntype, |
cc15e98f | 11157 | rtx libname ATTRIBUTE_UNUSED, |
50fe8924 OE |
11158 | tree fndecl, |
11159 | signed int n_named_args, | |
ef4bddc2 | 11160 | machine_mode mode) |
cc15e98f NC |
11161 | { |
11162 | pcum->arg_count [(int) SH_ARG_FLOAT] = 0; | |
11163 | pcum->free_single_fp_reg = 0; | |
df4bacab | 11164 | pcum->outgoing = n_named_args != -1; |
cc15e98f | 11165 | |
df4bacab OE |
11166 | /* FIXME: Should we check TARGET_HITACHI here ??? */ |
11167 | pcum->renesas_abi = sh_attr_renesas_p (fntype); | |
cc15e98f NC |
11168 | |
11169 | if (fntype) | |
11170 | { | |
11171 | pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi) | |
11172 | && aggregate_value_p (TREE_TYPE (fntype), fndecl)); | |
f4da8dce | 11173 | pcum->prototype_p = prototype_p (fntype); |
e1fab8ba | 11174 | pcum->arg_count [(int) SH_ARG_INT] = false; |
cc15e98f NC |
11175 | } |
11176 | else | |
11177 | { | |
11178 | pcum->arg_count [(int) SH_ARG_INT] = 0; | |
df4bacab | 11179 | pcum->prototype_p = false; |
cc15e98f NC |
11180 | if (mode != VOIDmode) |
11181 | { | |
cc15e98f NC |
11182 | /* If the default ABI is the Renesas ABI then all library |
11183 | calls must assume that the library will be using the | |
11184 | Renesas ABI. So if the function would return its result | |
11185 | in memory then we must force the address of this memory | |
11186 | block onto the stack. Ideally we would like to call | |
11187 | targetm.calls.return_in_memory() here but we do not have | |
8b0add27 | 11188 | the TYPE or the FNDECL available so we synthesize the |
cc15e98f NC |
11189 | contents of that function as best we can. */ |
11190 | pcum->force_mem = | |
c0fb94d7 | 11191 | (TARGET_DEFAULT & MASK_HITACHI) |
cc15e98f NC |
11192 | && (mode == BLKmode |
11193 | || (GET_MODE_SIZE (mode) > 4 | |
11194 | && !(mode == DFmode | |
11195 | && TARGET_FPU_DOUBLE))); | |
11196 | } | |
11197 | else | |
df4bacab | 11198 | pcum->force_mem = false; |
cc15e98f NC |
11199 | } |
11200 | } | |
11201 | ||
73a4d10b | 11202 | rtx |
ef4bddc2 | 11203 | sh_gen_truncate (machine_mode mode, rtx x, int need_sign_ext) |
73a4d10b R |
11204 | { |
11205 | enum rtx_code code = TRUNCATE; | |
11206 | ||
11207 | if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
11208 | { | |
11209 | rtx inner = XEXP (x, 0); | |
ef4bddc2 | 11210 | machine_mode inner_mode = GET_MODE (inner); |
73a4d10b R |
11211 | |
11212 | if (inner_mode == mode) | |
11213 | return inner; | |
11214 | else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode)) | |
11215 | x = inner; | |
11216 | else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode) | |
11217 | && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND)) | |
11218 | { | |
11219 | code = GET_CODE (x); | |
11220 | x = inner; | |
11221 | } | |
11222 | } | |
11223 | return gen_rtx_fmt_e (code, mode, x); | |
11224 | } | |
11225 | ||
73a4d10b R |
11226 | /* Load and store depend on the highpart of the address. However, |
11227 | set_attr_alternative does not give well-defined results before reload, | |
11228 | so we must look at the rtl ourselves to see if any of the feeding | |
50fe8924 | 11229 | registers is used in a memref. |
73a4d10b | 11230 | |
2caafc44 | 11231 | Return true iff INSN contains a MEM. */ |
aaf701c5 | 11232 | bool |
73a4d10b R |
11233 | sh_contains_memref_p (rtx insn) |
11234 | { | |
2caafc44 RS |
11235 | subrtx_iterator::array_type array; |
11236 | FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST) | |
11237 | if (MEM_P (*iter)) | |
11238 | return true; | |
11239 | return false; | |
73a4d10b R |
11240 | } |
11241 | ||
aaf701c5 OE |
11242 | /* Return true iff INSN loads a banked register. */ |
11243 | bool | |
5c7cafa8 CB |
11244 | sh_loads_bankedreg_p (rtx insn) |
11245 | { | |
11246 | if (GET_CODE (PATTERN (insn)) == SET) | |
11247 | { | |
11248 | rtx op = SET_DEST (PATTERN(insn)); | |
11249 | if (REG_P (op) && BANKED_REGISTER_P (REGNO (op))) | |
aaf701c5 | 11250 | return true; |
5c7cafa8 CB |
11251 | } |
11252 | ||
aaf701c5 | 11253 | return false; |
5c7cafa8 CB |
11254 | } |
11255 | ||
486b10aa | 11256 | /* Implement TARGET_PREFERRED_RELOAD_CLASS. */ |
486b10aa | 11257 | static reg_class_t |
e1fab8ba | 11258 | sh_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) |
486b10aa | 11259 | { |
486b10aa AS |
11260 | return rclass; |
11261 | } | |
11262 | ||
11263 | /* Implement TARGET_SECONDARY_RELOAD. */ | |
486b10aa | 11264 | static reg_class_t |
a87cf97e | 11265 | sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, |
ef4bddc2 | 11266 | machine_mode mode, secondary_reload_info *sri) |
8a99f6f9 | 11267 | { |
a87cf97e JR |
11268 | enum reg_class rclass = (enum reg_class) rclass_i; |
11269 | ||
fce1e5fb OE |
11270 | if (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS |
11271 | && REG_P (XEXP (XEXP (x, 0), 0)) | |
11272 | && REGNO (XEXP (XEXP (x, 0), 0)) == GBR_REG) | |
11273 | return rclass == R0_REGS ? NO_REGS : R0_REGS; | |
11274 | ||
11275 | if (MEM_P (x) && REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == GBR_REG) | |
11276 | return rclass == R0_REGS ? NO_REGS : R0_REGS; | |
11277 | ||
11278 | if (REG_P (x) && REGNO (x) == GBR_REG) | |
11279 | return NO_REGS; | |
11280 | ||
8a99f6f9 R |
11281 | if (in_p) |
11282 | { | |
0a2aaacc | 11283 | if (REGCLASS_HAS_FP_REG (rclass) |
8a99f6f9 | 11284 | && immediate_operand ((x), mode) |
ddfe2bdb | 11285 | && ! ((fp_zero_operand (x) || fp_one_operand (x)) && mode == SFmode)) |
8a99f6f9 R |
11286 | switch (mode) |
11287 | { | |
4e10a5a7 | 11288 | case E_SFmode: |
8a99f6f9 R |
11289 | sri->icode = CODE_FOR_reload_insf__frn; |
11290 | return NO_REGS; | |
4e10a5a7 | 11291 | case E_DFmode: |
8a99f6f9 R |
11292 | sri->icode = CODE_FOR_reload_indf__frn; |
11293 | return NO_REGS; | |
4e10a5a7 | 11294 | case E_SImode: |
8a99f6f9 R |
11295 | /* ??? If we knew that we are in the appropriate mode - |
11296 | single precision - we could use a reload pattern directly. */ | |
11297 | return FPUL_REGS; | |
11298 | default: | |
11299 | abort (); | |
11300 | } | |
0a2aaacc | 11301 | if (rclass == FPUL_REGS |
50fe8924 OE |
11302 | && ((REG_P (x) && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG |
11303 | || REGNO (x) == T_REG)) | |
11304 | || GET_CODE (x) == PLUS)) | |
11305 | return GENERAL_REGS; | |
0a2aaacc | 11306 | if (rclass == FPUL_REGS && immediate_operand (x, mode)) |
8a99f6f9 | 11307 | { |
d973ac5a | 11308 | if (satisfies_constraint_I08 (x) || fp_zero_operand (x)) |
8a99f6f9 | 11309 | return GENERAL_REGS; |
d973ac5a KK |
11310 | else if (mode == SFmode) |
11311 | return FP_REGS; | |
8a99f6f9 R |
11312 | sri->icode = CODE_FOR_reload_insi__i_fpul; |
11313 | return NO_REGS; | |
11314 | } | |
0a2aaacc | 11315 | if (rclass == FPSCR_REGS |
50fe8924 OE |
11316 | && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER) |
11317 | || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS))) | |
8a99f6f9 | 11318 | return GENERAL_REGS; |
8a99f6f9 R |
11319 | } /* end of input-only processing. */ |
11320 | ||
0a2aaacc | 11321 | if (((REGCLASS_HAS_FP_REG (rclass) |
f3536097 | 11322 | && (REG_P (x) |
8a99f6f9 R |
11323 | && (GENERAL_OR_AP_REGISTER_P (REGNO (x)) |
11324 | || (FP_REGISTER_P (REGNO (x)) && mode == SImode | |
11325 | && TARGET_FMOVD)))) | |
0a2aaacc | 11326 | || (REGCLASS_HAS_GENERAL_REG (rclass) |
f3536097 | 11327 | && REG_P (x) |
8a99f6f9 | 11328 | && FP_REGISTER_P (REGNO (x)))) |
8a99f6f9 R |
11329 | && (mode == SFmode || mode == SImode)) |
11330 | return FPUL_REGS; | |
0a2aaacc | 11331 | if ((rclass == FPUL_REGS |
e1fab8ba | 11332 | || (REGCLASS_HAS_FP_REG (rclass) && mode == SImode)) |
f3536097 | 11333 | && (MEM_P (x) |
50fe8924 OE |
11334 | || (REG_P (x) |
11335 | && (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
11336 | || REGNO (x) == T_REG | |
11337 | || system_reg_operand (x, VOIDmode))))) | |
8a99f6f9 | 11338 | { |
0a2aaacc | 11339 | if (rclass == FPUL_REGS) |
8a99f6f9 | 11340 | return GENERAL_REGS; |
fc1fcfa0 | 11341 | return NO_REGS; // LRA wants NO_REGS here, it used to be FPUL_REGS; |
8a99f6f9 | 11342 | } |
34d5fe77 | 11343 | |
0a2aaacc | 11344 | if ((rclass == MAC_REGS || rclass == PR_REGS) |
f3536097 | 11345 | && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x)) |
0a2aaacc | 11346 | && rclass != REGNO_REG_CLASS (REGNO (x))) |
8a99f6f9 | 11347 | return GENERAL_REGS; |
cebc182b OE |
11348 | |
11349 | /* If here fall back to loading FPUL register through general registers. | |
11350 | This case can happen when movsi_ie insn is picked initially to | |
11351 | load/store the FPUL register from/to another register, and then the | |
11352 | other register is allocated on the stack. */ | |
11353 | if (rclass == FPUL_REGS && true_regnum (x) == -1) | |
11354 | return GENERAL_REGS; | |
11355 | ||
8c2a3f3b OE |
11356 | /* Force mov.b / mov.w displacement addressing insn to use R0 as |
11357 | the other operand. | |
344332e8 OE |
11358 | On SH2A could also just leave it alone here, which would result in a |
11359 | 4 byte move insn being generated instead. However, for this to work | |
11360 | the insns must have the appropriate alternatives. */ | |
8c2a3f3b OE |
11361 | if ((mode == QImode || mode == HImode) && rclass != R0_REGS |
11362 | && satisfies_constraint_Sdd (x) | |
91f65b12 OE |
11363 | && sh_disp_addr_displacement (x) |
11364 | <= sh_max_mov_insn_displacement (mode, false)) | |
344332e8 OE |
11365 | return R0_REGS; |
11366 | ||
11367 | /* When reload is trying to address a QImode or HImode subreg on the stack, | |
11368 | force any subreg byte into R0_REGS, as this is going to become a | |
11369 | displacement address. | |
11370 | We could restrict this to SUBREG_BYTE (x) > 0, but if the actual reg | |
11371 | is on the stack, the memref to it might already require a displacement | |
11372 | and that has to be added to the final address. At this point we don't | |
11373 | know the cumulative displacement so we assume the worst case. */ | |
11374 | if ((mode == QImode || mode == HImode) && rclass != R0_REGS | |
11375 | && GET_CODE (x) == SUBREG && true_regnum (x) == -1) | |
11376 | return R0_REGS; | |
11377 | ||
8a99f6f9 R |
11378 | return NO_REGS; |
11379 | } | |
11380 | ||
d6220b11 KK |
11381 | /* Return true if SUBST can't safely replace its equivalent during RA. */ |
11382 | static bool | |
11383 | sh_cannot_substitute_mem_equiv_p (rtx) | |
11384 | { | |
d6220b11 KK |
11385 | /* If SUBST is mem[base+index] or QI/HImode mem[base+disp], the insn |
11386 | uses R0 and may cause spill failure when R0 is already used. | |
11387 | We have to return true for that case at least. | |
11388 | Moreover SH has strong R0 parity and also have not enough numbers of | |
11389 | the hard registers to make the equiv substitution win in the size | |
11390 | and the speed on average working sets. The pseudos produced to | |
11391 | hold the equiv values can't get good hard registers for bad cases | |
11392 | and end up memory save/restore insns which make the code worse. */ | |
11393 | return true; | |
11394 | } | |
11395 | ||
14133a4d KK |
11396 | /* Return true if DISP can be legitimized. */ |
11397 | static bool | |
11398 | sh_legitimize_address_displacement (rtx *disp, rtx *offs, | |
11399 | machine_mode mode) | |
11400 | { | |
d5dd0a62 | 11401 | if ((TARGET_FPU_DOUBLE && mode == DFmode) |
14133a4d KK |
11402 | || (TARGET_SH2E && mode == SFmode)) |
11403 | return false; | |
11404 | ||
11405 | struct disp_adjust adj = sh_find_mov_disp_adjust (mode, INTVAL (*disp)); | |
11406 | if (adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX) | |
11407 | { | |
11408 | *disp = adj.mov_disp; | |
11409 | *offs = adj.offset_adjust; | |
11410 | return true; | |
11411 | } | |
11412 | ||
11413 | return false; | |
11414 | } | |
11415 | ||
6efc6b7f KK |
11416 | /* Return true if movsf insn should be splited with an additional |
11417 | register. */ | |
11418 | bool | |
11419 | sh_movsf_ie_ra_split_p (rtx op0, rtx op1, rtx op2) | |
11420 | { | |
11421 | /* op0 == op1 */ | |
11422 | if (rtx_equal_p (op0, op1)) | |
11423 | return true; | |
11424 | /* fy, FQ, reg */ | |
11425 | if (GET_CODE (op1) == CONST_DOUBLE | |
11426 | && ! satisfies_constraint_G (op1) | |
11427 | && ! satisfies_constraint_H (op1) | |
11428 | && REG_P (op0) | |
11429 | && REG_P (op2)) | |
11430 | return true; | |
11431 | /* f, r, y */ | |
11432 | if (REG_P (op0) && FP_REGISTER_P (REGNO (op0)) | |
11433 | && REG_P (op1) && GENERAL_REGISTER_P (REGNO (op1)) | |
11434 | && REG_P (op2) && (REGNO (op2) == FPUL_REG)) | |
11435 | return true; | |
11436 | /* r, f, y */ | |
11437 | if (REG_P (op1) && FP_REGISTER_P (REGNO (op1)) | |
11438 | && REG_P (op0) && GENERAL_REGISTER_P (REGNO (op0)) | |
11439 | && REG_P (op2) && (REGNO (op2) == FPUL_REG)) | |
11440 | return true; | |
11441 | ||
11442 | return false; | |
11443 | } | |
11444 | ||
5efd84c5 NF |
11445 | static void |
11446 | sh_conditional_register_usage (void) | |
11447 | { | |
df4bacab | 11448 | for (int regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) |
5efd84c5 NF |
11449 | if (! VALID_REGISTER_P (regno)) |
11450 | fixed_regs[regno] = call_used_regs[regno] = 1; | |
11451 | /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ | |
5efd84c5 NF |
11452 | if (flag_pic) |
11453 | { | |
11454 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
11455 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
11456 | } | |
1e44e857 DJ |
11457 | if (TARGET_FDPIC) |
11458 | { | |
11459 | fixed_regs[PIC_REG] = 1; | |
11460 | call_used_regs[PIC_REG] = 1; | |
11461 | call_really_used_regs[PIC_REG] = 1; | |
11462 | } | |
5efd84c5 NF |
11463 | /* Renesas saves and restores mac registers on call. */ |
11464 | if (TARGET_HITACHI && ! TARGET_NOMACSAVE) | |
11465 | { | |
11466 | call_really_used_regs[MACH_REG] = 0; | |
11467 | call_really_used_regs[MACL_REG] = 0; | |
11468 | } | |
1818d01c | 11469 | |
df4bacab | 11470 | for (int regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) |
e1fab8ba OE |
11471 | if (! fixed_regs[regno] && call_really_used_regs[regno]) |
11472 | SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); | |
3a2317d1 OE |
11473 | |
11474 | call_really_used_regs[FPSCR_MODES_REG] = 0; | |
11475 | call_really_used_regs[FPSCR_STAT_REG] = 0; | |
5efd84c5 NF |
11476 | } |
11477 | ||
1a627b35 RS |
11478 | /* Implement TARGET_LEGITIMATE_CONSTANT_P |
11479 | ||
11480 | can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */ | |
1a627b35 | 11481 | static bool |
ef4bddc2 | 11482 | sh_legitimate_constant_p (machine_mode mode, rtx x) |
1a627b35 | 11483 | { |
1e44e857 DJ |
11484 | if (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) |
11485 | { | |
11486 | rtx base, offset; | |
11487 | split_const (x, &base, &offset); | |
11488 | ||
11489 | if (GET_CODE (base) == SYMBOL_REF | |
11490 | && !offset_within_block_p (base, INTVAL (offset))) | |
11491 | return false; | |
11492 | } | |
11493 | ||
11494 | if (TARGET_FDPIC | |
11495 | && (SYMBOLIC_CONST_P (x) | |
11496 | || (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
11497 | && SYMBOLIC_CONST_P (XEXP (XEXP (x, 0), 0))))) | |
11498 | return false; | |
11499 | ||
1e44e857 DJ |
11500 | return GET_CODE (x) != CONST_DOUBLE |
11501 | || mode == DFmode || mode == SFmode | |
11502 | || mode == DImode || GET_MODE (x) == VOIDmode; | |
1a627b35 | 11503 | } |
5efd84c5 | 11504 | |
73a4d10b R |
11505 | enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT; |
11506 | ||
dab37c68 RH |
11507 | static void |
11508 | sh_init_sync_libfuncs (void) | |
11509 | { | |
11510 | init_sync_libfuncs (UNITS_PER_WORD); | |
11511 | } | |
11512 | ||
fcf8632e CB |
11513 | /* Return true if it is appropriate to emit `ret' instructions in the |
11514 | body of a function. */ | |
fcf8632e CB |
11515 | bool |
11516 | sh_can_use_simple_return_p (void) | |
11517 | { | |
fcf8632e CB |
11518 | if (! reload_completed || frame_pointer_needed) |
11519 | return false; | |
11520 | ||
11521 | /* Moving prologue around does't reduce the size. */ | |
11522 | if (optimize_function_for_size_p (cfun)) | |
11523 | return false; | |
11524 | ||
fcf8632e | 11525 | /* Finally, allow for pr save. */ |
df4bacab OE |
11526 | HARD_REG_SET live_regs_mask; |
11527 | int d = calc_live_regs (&live_regs_mask); | |
fcf8632e CB |
11528 | |
11529 | if (rounded_frame_size (d) > 4) | |
11530 | return false; | |
11531 | ||
11532 | return true; | |
fcf8632e CB |
11533 | } |
11534 | ||
fce1e5fb OE |
11535 | /*------------------------------------------------------------------------------ |
11536 | Address mode optimization support code | |
11537 | */ | |
11538 | ||
11539 | typedef HOST_WIDE_INT disp_t; | |
11540 | static const disp_t MIN_DISP = HOST_WIDE_INT_MIN; | |
11541 | static const disp_t MAX_DISP = HOST_WIDE_INT_MAX; | |
11542 | static const disp_t INVALID_DISP = MAX_DISP; | |
11543 | ||
11544 | /* A memory reference which is described by a base register and a | |
11545 | displacement. */ | |
11546 | class base_reg_disp | |
11547 | { | |
11548 | public: | |
11549 | base_reg_disp (rtx br, disp_t d); | |
11550 | ||
11551 | bool is_reg (void) const; | |
11552 | bool is_disp (void) const; | |
11553 | rtx reg (void) const; | |
11554 | disp_t disp (void) const; | |
11555 | ||
11556 | private: | |
11557 | rtx reg_; | |
11558 | disp_t disp_; | |
11559 | }; | |
11560 | ||
11561 | inline | |
11562 | base_reg_disp::base_reg_disp (rtx br, disp_t d) | |
11563 | : reg_ (br), disp_ (d) | |
11564 | { | |
11565 | } | |
11566 | ||
11567 | inline bool | |
11568 | base_reg_disp::is_reg (void) const | |
11569 | { | |
11570 | return reg_ != NULL_RTX && disp_ != INVALID_DISP; | |
11571 | } | |
11572 | ||
11573 | inline bool | |
11574 | base_reg_disp::is_disp (void) const | |
11575 | { | |
11576 | return reg_ == NULL_RTX && disp_ != INVALID_DISP; | |
11577 | } | |
11578 | ||
11579 | inline rtx | |
11580 | base_reg_disp::reg (void) const | |
11581 | { | |
11582 | return reg_; | |
11583 | } | |
11584 | ||
11585 | inline disp_t | |
11586 | base_reg_disp::disp (void) const | |
11587 | { | |
11588 | return disp_; | |
11589 | } | |
11590 | ||
11591 | /* Find the base register and calculate the displacement for a given | |
4eac9c2b | 11592 | address rtx 'x'. */ |
fce1e5fb | 11593 | static base_reg_disp |
4eac9c2b OE |
11594 | sh_find_base_reg_disp (rtx_insn* insn, rtx x, disp_t disp = 0, |
11595 | rtx base_reg = NULL) | |
fce1e5fb OE |
11596 | { |
11597 | if (REG_P (x)) | |
11598 | { | |
11599 | if (REGNO (x) == GBR_REG) | |
11600 | return base_reg_disp (x, disp); | |
11601 | ||
11602 | /* We've reached a hard-reg. This is probably the point where | |
11603 | function args are copied to pseudos. Do not go any further and | |
11604 | stick to the pseudo. If the original mem addr was in a hard reg | |
11605 | from the beginning, it will become the base reg. */ | |
11606 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
11607 | return base_reg_disp (base_reg != NULL ? base_reg : x, disp); | |
11608 | ||
4eac9c2b OE |
11609 | /* Find the def of the reg and trace it. If there are more than one |
11610 | defs and they are not the same, assume it's not safe to proceed. */ | |
11611 | rtx_insn* last_i = NULL; | |
11612 | rtx last_set = NULL; | |
11613 | for (df_ref d = DF_REG_DEF_CHAIN (REGNO (x)); d != NULL; | |
11614 | d = DF_REF_NEXT_REG (d)) | |
fce1e5fb | 11615 | { |
4eac9c2b | 11616 | rtx set = const_cast<rtx> (set_of (x, DF_REF_INSN (d))); |
fce1e5fb | 11617 | |
4eac9c2b OE |
11618 | /* Accept multiple defs, as long as they are equal. */ |
11619 | if (last_set == NULL || rtx_equal_p (last_set, set)) | |
11620 | { | |
11621 | last_i = DF_REF_INSN (d); | |
11622 | last_set = set; | |
11623 | } | |
11624 | else | |
fce1e5fb | 11625 | { |
4eac9c2b OE |
11626 | last_i = NULL; |
11627 | last_set = NULL; | |
11628 | break; | |
fce1e5fb OE |
11629 | } |
11630 | } | |
11631 | ||
4eac9c2b OE |
11632 | if (last_set != NULL && last_i != NULL) |
11633 | return sh_find_base_reg_disp (last_i, XEXP (last_set, 1), disp, | |
11634 | XEXP (last_set, 0)); | |
11635 | ||
11636 | /* When here, no previous insn was found that sets the reg. | |
11637 | The input reg is already the base reg. */ | |
11638 | return base_reg_disp (x, disp); | |
11639 | } | |
fce1e5fb OE |
11640 | |
11641 | else if (GET_CODE (x) == PLUS) | |
11642 | { | |
11643 | base_reg_disp left_val = sh_find_base_reg_disp (insn, XEXP (x, 0)); | |
11644 | base_reg_disp right_val = sh_find_base_reg_disp (insn, XEXP (x, 1)); | |
11645 | ||
11646 | /* Either left or right val must be a reg. | |
11647 | We don't handle the case of 'reg + reg' here. */ | |
11648 | if (left_val.is_reg () && right_val.is_disp ()) | |
11649 | return base_reg_disp (left_val.reg (), left_val.disp () | |
11650 | + right_val.disp () + disp); | |
11651 | else if (right_val.is_reg () && left_val.is_disp ()) | |
11652 | return base_reg_disp (right_val.reg (), right_val.disp () | |
11653 | + left_val.disp () + disp); | |
11654 | else | |
11655 | return base_reg_disp (base_reg, disp); | |
11656 | } | |
11657 | ||
11658 | else if (CONST_INT_P (x)) | |
11659 | return base_reg_disp (NULL, disp + INTVAL (x)); | |
11660 | ||
11661 | /* Didn't find anything useful. */ | |
11662 | return base_reg_disp (base_reg, disp); | |
11663 | } | |
11664 | ||
11665 | /* Given an insn and a memory operand, try to find an equivalent GBR | |
11666 | based memory address and return the corresponding new memory address. | |
11667 | Return NULL_RTX if not found. */ | |
11668 | rtx | |
4eac9c2b | 11669 | sh_find_equiv_gbr_addr (rtx_insn* insn, rtx mem) |
fce1e5fb | 11670 | { |
4eac9c2b | 11671 | if (!MEM_P (mem) || gbr_address_mem (mem, GET_MODE (mem))) |
fce1e5fb OE |
11672 | return NULL_RTX; |
11673 | ||
11674 | /* Leave post/pre inc/dec or any other side effect addresses alone. */ | |
11675 | if (side_effects_p (XEXP (mem, 0))) | |
11676 | return NULL_RTX; | |
11677 | ||
4eac9c2b OE |
11678 | /* When not optimizing there might be no dataflow available. */ |
11679 | if (df == NULL) | |
11680 | return NULL_RTX; | |
11681 | ||
fce1e5fb OE |
11682 | base_reg_disp gbr_disp = sh_find_base_reg_disp (insn, XEXP (mem, 0)); |
11683 | ||
11684 | if (gbr_disp.is_reg () && REGNO (gbr_disp.reg ()) == GBR_REG) | |
11685 | { | |
4eac9c2b OE |
11686 | /* If GBR is marked as call clobbered we bail out if we see a call. |
11687 | FIXME: Actually should check if this mem refers to the gbr value | |
11688 | before or after the call. If there is a store_gbr preceeding this | |
11689 | mem, it's safe to use GBR for this mem. | |
11690 | ||
11691 | If GBR is not marked as call clobbered, but there is some other | |
11692 | def than a call, it's probably a load_gbr upon which we also | |
11693 | bail out to be on the safe side. | |
11694 | FIXME: Should check if we have a use-after-def case, such as | |
11695 | the call case above. */ | |
11696 | for (df_ref d = DF_REG_DEF_CHAIN (GBR_REG); d != NULL; | |
11697 | d = DF_REF_NEXT_REG (d)) | |
11698 | { | |
11699 | if (CALL_P (DF_REF_INSN (d))) | |
11700 | { | |
11701 | if (REGNO_REG_SET_P (regs_invalidated_by_call_regset, GBR_REG)) | |
11702 | return NULL_RTX; | |
11703 | else | |
11704 | continue; | |
11705 | } | |
11706 | else | |
11707 | return NULL_RTX; | |
11708 | } | |
11709 | ||
fce1e5fb OE |
11710 | rtx disp = GEN_INT (gbr_disp.disp ()); |
11711 | if (gbr_displacement (disp, GET_MODE (mem))) | |
11712 | return gen_rtx_PLUS (SImode, gen_rtx_REG (SImode, GBR_REG), disp); | |
11713 | } | |
11714 | ||
11715 | return NULL_RTX; | |
11716 | } | |
11717 | ||
26943929 OE |
11718 | /*------------------------------------------------------------------------------ |
11719 | Manual insn combine support code. | |
11720 | */ | |
11721 | ||
9270a54f OE |
11722 | /* Return true if the specified insn contains any UNSPECs or |
11723 | UNSPEC_VOLATILEs. */ | |
11724 | static bool | |
b151091d | 11725 | sh_unspec_insn_p (rtx x) |
9270a54f | 11726 | { |
b151091d OE |
11727 | subrtx_iterator::array_type array; |
11728 | FOR_EACH_SUBRTX (i, array, x, ALL) | |
11729 | if (*i != NULL | |
11730 | && (GET_CODE (*i) == UNSPEC || GET_CODE (*i) == UNSPEC_VOLATILE)) | |
11731 | return true; | |
9270a54f | 11732 | |
b151091d | 11733 | return false; |
9270a54f OE |
11734 | } |
11735 | ||
11736 | /* Return true if the register operands of the specified insn are modified | |
11737 | between the specified from and to insns (exclusive of those two). */ | |
841dbf80 | 11738 | bool |
9270a54f OE |
11739 | sh_insn_operands_modified_between_p (rtx_insn* operands_insn, |
11740 | const rtx_insn* from, | |
11741 | const rtx_insn* to) | |
11742 | { | |
11743 | /* FIXME: Return true for multiple sets for now. */ | |
11744 | rtx s = single_set (operands_insn); | |
11745 | if (s == NULL_RTX) | |
11746 | return true; | |
11747 | ||
11748 | subrtx_iterator::array_type array; | |
11749 | FOR_EACH_SUBRTX (i, array, SET_SRC (s), ALL) | |
b151091d OE |
11750 | if (*i != NULL && |
11751 | ((REG_P (*i) || SUBREG_P (*i)) && reg_set_between_p (*i, from, to))) | |
9270a54f OE |
11752 | return true; |
11753 | ||
11754 | return false; | |
11755 | } | |
11756 | ||
841dbf80 OE |
11757 | /* Given an insn, determine whether it's a 'nott' insn, i.e. an insn that |
11758 | negates the T bit and stores the result in the T bit. */ | |
11759 | bool | |
11760 | sh_is_nott_insn (const rtx_insn* i) | |
11761 | { | |
11762 | return i != NULL && GET_CODE (PATTERN (i)) == SET | |
11763 | && t_reg_operand (XEXP (PATTERN (i), 0), VOIDmode) | |
11764 | && negt_reg_operand (XEXP (PATTERN (i), 1), VOIDmode); | |
11765 | } | |
11766 | ||
11767 | rtx | |
11768 | sh_movt_set_dest (const rtx_insn* i) | |
11769 | { | |
50c6dd20 OE |
11770 | return i == NULL ? NULL : sh_movt_set_dest (PATTERN (i)); |
11771 | } | |
841dbf80 | 11772 | |
50c6dd20 OE |
11773 | rtx |
11774 | sh_movt_set_dest (const_rtx pat) | |
11775 | { | |
11776 | return GET_CODE (pat) == SET | |
11777 | && arith_reg_dest (XEXP (pat, 0), SImode) | |
11778 | && t_reg_operand (XEXP (pat, 1), VOIDmode) ? XEXP (pat, 0) : NULL; | |
841dbf80 OE |
11779 | } |
11780 | ||
11781 | /* Given an insn, check whether it's a 'movrt' kind of insn, i.e. an insn | |
11782 | that stores the negated T bit in a register, and return the destination | |
11783 | register rtx, or null. */ | |
11784 | rtx | |
11785 | sh_movrt_set_dest (const rtx_insn* i) | |
11786 | { | |
50c6dd20 OE |
11787 | return i == NULL ? NULL : sh_movrt_set_dest (PATTERN (i)); |
11788 | } | |
841dbf80 | 11789 | |
50c6dd20 OE |
11790 | rtx |
11791 | sh_movrt_set_dest (const_rtx pat) | |
11792 | { | |
841dbf80 | 11793 | /* The negc movrt replacement is inside a parallel. */ |
50c6dd20 OE |
11794 | if (GET_CODE (pat) == PARALLEL) |
11795 | pat = XVECEXP (pat, 0, 0); | |
11796 | ||
11797 | return GET_CODE (pat) == SET | |
11798 | && arith_reg_dest (XEXP (pat, 0), SImode) | |
11799 | && negt_reg_operand (XEXP (pat, 1), VOIDmode) ? XEXP (pat, 0) : NULL; | |
841dbf80 | 11800 | |
841dbf80 OE |
11801 | } |
11802 | ||
11803 | /* Given an insn and a reg number, tell whether the reg dies or is unused | |
11804 | after the insn. */ | |
11805 | bool | |
11806 | sh_reg_dead_or_unused_after_insn (const rtx_insn* i, int regno) | |
11807 | { | |
11808 | return find_regno_note (i, REG_DEAD, regno) != NULL | |
11809 | || find_regno_note (i, REG_UNUSED, regno) != NULL; | |
11810 | } | |
11811 | ||
83e3f98b OE |
11812 | /* Given an insn and a reg number, remove reg dead or reg unused notes to |
11813 | mark it as being used after the insn. */ | |
11814 | void | |
11815 | sh_remove_reg_dead_or_unused_notes (rtx_insn* i, int regno) | |
11816 | { | |
11817 | if (rtx n = find_regno_note (i, REG_DEAD, regno)) | |
11818 | remove_note (i, n); | |
11819 | if (rtx n = find_regno_note (i, REG_UNUSED, regno)) | |
11820 | remove_note (i, n); | |
11821 | } | |
11822 | ||
dac2637b OE |
11823 | /* Given an insn check if it contains any post/pre inc/dec mem operands and |
11824 | add the REG_INC notes accordingly. | |
11825 | FIXME: This function is very similar to lra.c (add_auto_inc_notes). | |
11826 | FIXME: This function is currently used by peephole2 patterns because | |
11827 | the peephole2 pass does not preserve REG_INC notes. If the notes | |
11828 | are dropped the following passes will do wrong things. */ | |
11829 | rtx_insn* | |
11830 | sh_check_add_incdec_notes (rtx_insn* i) | |
11831 | { | |
11832 | struct for_each_inc_dec_clb | |
11833 | { | |
11834 | static int func (rtx mem ATTRIBUTE_UNUSED, rtx op ATTRIBUTE_UNUSED, | |
11835 | rtx dest, rtx src ATTRIBUTE_UNUSED, | |
11836 | rtx srcoff ATTRIBUTE_UNUSED, void* arg) | |
11837 | { | |
11838 | gcc_assert (REG_P (dest)); | |
11839 | ||
11840 | rtx_insn* i = (rtx_insn*)arg; | |
11841 | if (find_regno_note (i, REG_INC, REGNO (dest)) == NULL) | |
11842 | add_reg_note (i, REG_INC, dest); | |
11843 | ||
11844 | return 0; | |
11845 | } | |
11846 | }; | |
11847 | ||
11848 | for_each_inc_dec (PATTERN (i), for_each_inc_dec_clb::func, i); | |
11849 | return i; | |
11850 | } | |
11851 | ||
7dc5a9bb OE |
11852 | /* Given a move insn destiation and a source, make sure that the move source |
11853 | operand is not a post-inc mem load with the same address reg as the | |
11854 | destination. Returns the modified source operand with the post-inc removed | |
11855 | if necessary. */ | |
11856 | rtx | |
11857 | sh_remove_overlapping_post_inc (rtx dst, rtx src) | |
11858 | { | |
11859 | if (!MEM_P (src)) | |
11860 | return src; | |
11861 | ||
11862 | rtx addr = XEXP (src, 0); | |
11863 | ||
11864 | if (GET_CODE (addr) == POST_INC | |
11865 | && reg_overlap_mentioned_p (XEXP (addr, 0), dst)) | |
11866 | return replace_equiv_address (src, XEXP (addr, 0)); | |
11867 | ||
11868 | gcc_assert (GET_CODE (addr) != POST_MODIFY); | |
11869 | return src; | |
11870 | } | |
11871 | ||
11872 | /* Emit a move insn that is safe to be used in peephole patterns. */ | |
11873 | rtx_insn* | |
11874 | sh_peephole_emit_move_insn (rtx dst, rtx src) | |
11875 | { | |
11876 | return sh_check_add_incdec_notes ( | |
11877 | emit_move_insn (dst, sh_remove_overlapping_post_inc (dst, src))); | |
11878 | } | |
11879 | ||
26943929 OE |
11880 | /* Given an op rtx and an insn, try to find out whether the result of the |
11881 | specified op consists only of logical operations on T bit stores. */ | |
11882 | bool | |
355e9975 | 11883 | sh_is_logical_t_store_expr (rtx op, rtx_insn* insn) |
26943929 OE |
11884 | { |
11885 | if (!logical_operator (op, SImode)) | |
11886 | return false; | |
11887 | ||
11888 | rtx ops[2] = { XEXP (op, 0), XEXP (op, 1) }; | |
11889 | int op_is_t_count = 0; | |
11890 | ||
11891 | for (int i = 0; i < 2; ++i) | |
11892 | { | |
11893 | if (t_reg_operand (ops[i], VOIDmode) | |
11894 | || negt_reg_operand (ops[i], VOIDmode)) | |
11895 | op_is_t_count++; | |
11896 | ||
11897 | else | |
11898 | { | |
11899 | set_of_reg op_set = sh_find_set_of_reg (ops[i], insn, | |
11900 | prev_nonnote_insn_bb); | |
11901 | if (op_set.set_src == NULL_RTX) | |
11902 | continue; | |
11903 | ||
11904 | if (t_reg_operand (op_set.set_src, VOIDmode) | |
11905 | || negt_reg_operand (op_set.set_src, VOIDmode) | |
11906 | || sh_is_logical_t_store_expr (op_set.set_src, op_set.insn)) | |
11907 | op_is_t_count++; | |
11908 | } | |
11909 | } | |
11910 | ||
11911 | return op_is_t_count == 2; | |
11912 | } | |
11913 | ||
11914 | /* Given the operand that is extended in a sign/zero extend insn, and the | |
11915 | insn, try to figure out whether the sign/zero extension can be replaced | |
11916 | by a simple reg-reg copy. If so, the replacement reg rtx is returned, | |
11917 | NULL_RTX otherwise. */ | |
11918 | rtx | |
355e9975 | 11919 | sh_try_omit_signzero_extend (rtx extended_op, rtx_insn* insn) |
26943929 OE |
11920 | { |
11921 | if (REG_P (extended_op)) | |
11922 | extended_op = extended_op; | |
11923 | else if (GET_CODE (extended_op) == SUBREG && REG_P (SUBREG_REG (extended_op))) | |
11924 | extended_op = SUBREG_REG (extended_op); | |
11925 | else | |
11926 | return NULL_RTX; | |
11927 | ||
11928 | /* Reg moves must be of the same mode. */ | |
11929 | if (GET_MODE (extended_op) != SImode) | |
11930 | return NULL_RTX; | |
11931 | ||
11932 | set_of_reg s = sh_find_set_of_reg (extended_op, insn, prev_nonnote_insn_bb); | |
11933 | if (s.set_src == NULL_RTX) | |
11934 | return NULL_RTX; | |
11935 | ||
11936 | if (t_reg_operand (s.set_src, VOIDmode) | |
11937 | || negt_reg_operand (s.set_src, VOIDmode)) | |
11938 | return extended_op; | |
11939 | ||
11940 | /* If the zero extended reg was formed by a logical operation, check the | |
11941 | operands of the logical operation. If both originated from T bit | |
11942 | stores the zero extension can be eliminated. */ | |
11943 | else if (sh_is_logical_t_store_expr (s.set_src, s.insn)) | |
11944 | return extended_op; | |
11945 | ||
11946 | return NULL_RTX; | |
11947 | } | |
11948 | ||
355e9975 OE |
11949 | /* Given the current insn, which is assumed to be a movrt_negc insn, try to |
11950 | figure out whether it should be converted into a movt-xor sequence in | |
11951 | the movrt_negc splitter. | |
11952 | Returns true if insns have been modified and the splitter has succeeded. */ | |
11953 | bool | |
11954 | sh_split_movrt_negc_to_movt_xor (rtx_insn* curr_insn, rtx operands[]) | |
11955 | { | |
11956 | /* In cases such as | |
11957 | tst r4,r4 | |
11958 | mov #-1,r1 | |
11959 | negc r1,r1 | |
11960 | tst r4,r4 | |
11961 | we can replace the T bit clobbering negc with a movt-xor sequence and | |
11962 | eliminate the redundant comparison. | |
11963 | Because the xor insn depends on register allocation results, allow this | |
11964 | only before reload. */ | |
11965 | if (!can_create_pseudo_p ()) | |
11966 | return false; | |
11967 | ||
11968 | set_of_reg t_before_negc = sh_find_set_of_reg (get_t_reg_rtx (), curr_insn, | |
11969 | prev_nonnote_insn_bb); | |
11970 | set_of_reg t_after_negc = sh_find_set_of_reg (get_t_reg_rtx (), curr_insn, | |
11971 | next_nonnote_insn_bb); | |
11972 | ||
11973 | if (t_before_negc.set_rtx != NULL_RTX && t_after_negc.set_rtx != NULL_RTX | |
11974 | && rtx_equal_p (t_before_negc.set_rtx, t_after_negc.set_rtx) | |
9270a54f OE |
11975 | && !reg_used_between_p (get_t_reg_rtx (), curr_insn, t_after_negc.insn) |
11976 | && !sh_insn_operands_modified_between_p (t_before_negc.insn, | |
11977 | t_before_negc.insn, | |
11978 | t_after_negc.insn) | |
9354f9e7 | 11979 | && !modified_between_p (get_t_reg_rtx (), curr_insn, t_after_negc.insn) |
9270a54f OE |
11980 | && !sh_unspec_insn_p (t_after_negc.insn) |
11981 | && !volatile_insn_p (PATTERN (t_after_negc.insn)) | |
11982 | && !side_effects_p (PATTERN (t_after_negc.insn)) | |
11983 | && !may_trap_or_fault_p (PATTERN (t_after_negc.insn))) | |
355e9975 OE |
11984 | { |
11985 | emit_insn (gen_movrt_xor (operands[0], get_t_reg_rtx ())); | |
11986 | set_insn_deleted (t_after_negc.insn); | |
11987 | return true; | |
11988 | } | |
11989 | else | |
11990 | return false; | |
11991 | } | |
11992 | ||
83e3f98b OE |
11993 | /* Given a reg and the current insn, see if the value of the reg originated |
11994 | from a sign or zero extension and return the discovered information. */ | |
11995 | sh_extending_set_of_reg | |
11996 | sh_find_extending_set_of_reg (rtx reg, rtx_insn* curr_insn) | |
11997 | { | |
11998 | if (reg == NULL) | |
11999 | return sh_extending_set_of_reg (curr_insn); | |
12000 | ||
12001 | if (SUBREG_P (reg)) | |
12002 | reg = SUBREG_REG (reg); | |
12003 | ||
12004 | if (!REG_P (reg)) | |
12005 | return sh_extending_set_of_reg (curr_insn); | |
12006 | ||
12007 | /* FIXME: Also search the predecessor basic blocks. It seems that checking | |
12008 | only the adjacent predecessor blocks would cover most of the cases. | |
12009 | Also try to look through the first extension that we hit. There are some | |
12010 | cases, where a zero_extend is followed an (implicit) sign_extend, and it | |
12011 | fails to see the sign_extend. */ | |
12012 | sh_extending_set_of_reg result = | |
12013 | sh_find_set_of_reg (reg, curr_insn, prev_nonnote_insn_bb, true); | |
12014 | ||
12015 | if (result.set_src != NULL) | |
12016 | { | |
12017 | if (GET_CODE (result.set_src) == SIGN_EXTEND | |
12018 | || GET_CODE (result.set_src) == ZERO_EXTEND) | |
12019 | { | |
12020 | if (dump_file) | |
b151091d | 12021 | fprintf (dump_file, "sh_find_extending_set_of_reg: reg %d is " |
83e3f98b OE |
12022 | "explicitly sign/zero extended in insn %d\n", |
12023 | REGNO (reg), INSN_UID (result.insn)); | |
12024 | result.from_mode = GET_MODE (XEXP (result.set_src, 0)); | |
12025 | result.ext_code = GET_CODE (result.set_src); | |
12026 | } | |
12027 | else if (MEM_P (result.set_src) | |
12028 | && (GET_MODE (result.set_src) == QImode | |
b151091d OE |
12029 | || GET_MODE (result.set_src) == HImode) |
12030 | && !sh_unspec_insn_p (result.insn)) | |
83e3f98b OE |
12031 | { |
12032 | /* On SH QIHImode memory loads always sign extend. However, in | |
12033 | some cases where it seems that the higher bits are not | |
12034 | interesting, the loads will not be expanded as sign extending | |
12035 | insns, but as QIHImode loads into QIHImode regs. We report that | |
12036 | the reg has been sign extended by the mem load. When it is used | |
12037 | as such, we must convert the mem load into a sign extending insn, | |
12038 | see also sh_extending_set_of_reg::use_as_extended_reg. */ | |
12039 | if (dump_file) | |
12040 | fprintf (dump_file, "sh_find_extending_set_of_reg: reg %d is " | |
12041 | "implicitly sign extended in insn %d\n", | |
12042 | REGNO (reg), INSN_UID (result.insn)); | |
12043 | result.from_mode = GET_MODE (result.set_src); | |
12044 | result.ext_code = SIGN_EXTEND; | |
12045 | } | |
12046 | } | |
12047 | ||
12048 | return result; | |
12049 | } | |
12050 | ||
12051 | /* Given a reg that is known to be sign or zero extended at some insn, | |
12052 | take the appropriate measures so that the extended value can be used as | |
12053 | a reg at the specified insn and return the resulting reg rtx. */ | |
12054 | rtx | |
12055 | sh_extending_set_of_reg::use_as_extended_reg (rtx_insn* use_at_insn) const | |
12056 | { | |
12057 | gcc_assert (insn != NULL && set_src != NULL && set_rtx != NULL); | |
12058 | gcc_assert (ext_code == SIGN_EXTEND || ext_code == ZERO_EXTEND); | |
12059 | gcc_assert (from_mode == QImode || from_mode == HImode); | |
12060 | ||
12061 | if (MEM_P (set_src) && ext_code == SIGN_EXTEND) | |
12062 | { | |
12063 | if (dump_file) | |
12064 | fprintf (dump_file, | |
12065 | "use_as_extended_reg: converting non-extending mem load in " | |
12066 | "insn %d into sign-extending load\n", INSN_UID (insn)); | |
12067 | ||
12068 | rtx r = gen_reg_rtx (SImode); | |
12069 | rtx_insn* i0; | |
12070 | if (from_mode == QImode) | |
12071 | i0 = emit_insn_after (gen_extendqisi2 (r, set_src), insn); | |
12072 | else if (from_mode == HImode) | |
12073 | i0 = emit_insn_after (gen_extendhisi2 (r, set_src), insn); | |
12074 | else | |
12075 | gcc_unreachable (); | |
12076 | ||
12077 | emit_insn_after ( | |
12078 | gen_move_insn (XEXP (set_rtx, 0), | |
12079 | gen_lowpart (GET_MODE (set_src), r)), i0); | |
12080 | set_insn_deleted (insn); | |
12081 | return r; | |
12082 | } | |
12083 | else | |
12084 | { | |
12085 | rtx extension_dst = XEXP (set_rtx, 0); | |
c661ca79 OE |
12086 | if (GET_MODE (extension_dst) != SImode) |
12087 | extension_dst = simplify_gen_subreg (SImode, extension_dst, | |
12088 | GET_MODE (extension_dst), 0); | |
83e3f98b OE |
12089 | if (modified_between_p (extension_dst, insn, use_at_insn)) |
12090 | { | |
12091 | if (dump_file) | |
12092 | fprintf (dump_file, | |
12093 | "use_as_extended_reg: dest reg %d of extending insn %d is " | |
12094 | "modified, inserting a reg-reg copy\n", | |
12095 | REGNO (extension_dst), INSN_UID (insn)); | |
12096 | ||
12097 | rtx r = gen_reg_rtx (SImode); | |
12098 | emit_insn_after (gen_move_insn (r, extension_dst), insn); | |
12099 | return r; | |
12100 | } | |
12101 | else | |
12102 | { | |
12103 | sh_remove_reg_dead_or_unused_notes (insn, REGNO (extension_dst)); | |
12104 | return extension_dst; | |
12105 | } | |
12106 | } | |
12107 | } | |
12108 | ||
841dbf80 OE |
12109 | bool |
12110 | sh_extending_set_of_reg::can_use_as_unextended_reg (void) const | |
12111 | { | |
12112 | if ((ext_code == SIGN_EXTEND || ext_code == ZERO_EXTEND) | |
12113 | && (from_mode == QImode || from_mode == HImode) | |
12114 | && set_src != NULL) | |
12115 | return arith_reg_operand (XEXP (set_src, 0), from_mode); | |
12116 | else | |
12117 | return false; | |
12118 | } | |
12119 | ||
12120 | rtx | |
12121 | sh_extending_set_of_reg::use_as_unextended_reg (rtx_insn* use_at_insn) const | |
12122 | { | |
12123 | gcc_assert (can_use_as_unextended_reg ()); | |
12124 | ||
12125 | rtx r = XEXP (set_src, 0); | |
12126 | rtx r0 = simplify_gen_subreg (SImode, r, from_mode, 0); | |
12127 | ||
12128 | if (modified_between_p (r, insn, use_at_insn)) | |
12129 | { | |
12130 | rtx r1 = gen_reg_rtx (SImode); | |
12131 | emit_insn_after (gen_move_insn (r1, r0), insn); | |
12132 | return r1; | |
12133 | } | |
12134 | else | |
12135 | { | |
12136 | sh_remove_reg_dead_or_unused_notes (insn, SUBREG_P (r) | |
12137 | ? REGNO (SUBREG_REG (r)) | |
12138 | : REGNO (r)); | |
12139 | return r0; | |
12140 | } | |
12141 | } | |
12142 | ||
83e3f98b OE |
12143 | /* Given the current insn, which is assumed to be the *tst<mode>_t_subregs insn, |
12144 | perform the necessary checks on the operands and split it accordingly. */ | |
12145 | void | |
12146 | sh_split_tst_subregs (rtx_insn* curr_insn, machine_mode subreg_mode, | |
12147 | int subreg_offset, rtx operands[]) | |
12148 | { | |
12149 | gcc_assert (subreg_mode == QImode || subreg_mode == HImode); | |
12150 | ||
12151 | sh_extending_set_of_reg eop0 = sh_find_extending_set_of_reg (operands[0], | |
12152 | curr_insn); | |
12153 | sh_extending_set_of_reg eop1 = sh_find_extending_set_of_reg (operands[1], | |
12154 | curr_insn); | |
12155 | ||
12156 | /* If one of the operands is known to be zero extended, that's already | |
12157 | sufficient to mask out the unwanted high bits. */ | |
12158 | if (eop0.ext_code == ZERO_EXTEND && eop0.from_mode == subreg_mode) | |
12159 | { | |
12160 | emit_insn (gen_tstsi_t (eop0.use_as_extended_reg (curr_insn), | |
12161 | operands[1])); | |
12162 | return; | |
12163 | } | |
12164 | if (eop1.ext_code == ZERO_EXTEND && eop1.from_mode == subreg_mode) | |
12165 | { | |
12166 | emit_insn (gen_tstsi_t (operands[0], | |
12167 | eop1.use_as_extended_reg (curr_insn))); | |
12168 | return; | |
12169 | } | |
12170 | ||
12171 | /* None of the operands seem to be zero extended. | |
12172 | If both are sign extended it's OK, too. */ | |
12173 | if (eop0.ext_code == SIGN_EXTEND && eop1.ext_code == SIGN_EXTEND | |
12174 | && eop0.from_mode == subreg_mode && eop1.from_mode == subreg_mode) | |
12175 | { | |
12176 | emit_insn (gen_tstsi_t (eop0.use_as_extended_reg (curr_insn), | |
12177 | eop1.use_as_extended_reg (curr_insn))); | |
12178 | return; | |
12179 | } | |
12180 | ||
12181 | /* Otherwise we have to insert a zero extension on one of the operands to | |
12182 | mask out the unwanted high bits. | |
12183 | Prefer the operand that has no known extension. */ | |
12184 | if (eop0.ext_code != UNKNOWN && eop1.ext_code == UNKNOWN) | |
12185 | std::swap (operands[0], operands[1]); | |
12186 | ||
12187 | rtx tmp0 = gen_reg_rtx (SImode); | |
12188 | rtx tmp1 = simplify_gen_subreg (subreg_mode, operands[0], | |
12189 | GET_MODE (operands[0]), subreg_offset); | |
12190 | emit_insn (subreg_mode == QImode | |
12191 | ? gen_zero_extendqisi2 (tmp0, tmp1) | |
12192 | : gen_zero_extendhisi2 (tmp0, tmp1)); | |
12193 | emit_insn (gen_tstsi_t (tmp0, operands[1])); | |
12194 | } | |
12195 | ||
841dbf80 OE |
12196 | /* A helper class to increment/decrement a counter variable each time a |
12197 | function is entered/left. */ | |
12198 | class scope_counter | |
12199 | { | |
12200 | public: | |
12201 | scope_counter (int& counter) : m_counter (counter) { ++m_counter; } | |
12202 | ||
12203 | ~scope_counter (void) | |
12204 | { | |
12205 | --m_counter; | |
12206 | gcc_assert (m_counter >= 0); | |
12207 | } | |
12208 | ||
12209 | int count (void) const { return m_counter; } | |
12210 | ||
12211 | private: | |
12212 | int& m_counter; | |
12213 | }; | |
12214 | ||
12215 | /* Given an rtx x, determine whether the expression can be used to create | |
12216 | an insn that calulates x and stores the result in the T bit. | |
12217 | This is used by the 'treg_set_expr' predicate to construct insns sequences | |
12218 | where T bit results are fed into other insns, such as addc, subc, negc | |
12219 | insns. | |
12220 | ||
12221 | FIXME: The patterns that expand 'treg_set_expr' operands tend to | |
12222 | distinguish between 'positive' and 'negative' forms. For now this has to | |
12223 | be done in the preparation code. We could also introduce | |
12224 | 'pos_treg_set_expr' and 'neg_treg_set_expr' predicates for that and write | |
12225 | two different patterns for the 'postive' and 'negative' forms. However, | |
12226 | the total amount of lines of code seems to be about the same and the | |
12227 | '{pos|neg}_treg_set_expr' predicates would be more expensive, because the | |
12228 | recog function would need to look inside the expression by temporarily | |
12229 | splitting it. */ | |
12230 | static int sh_recog_treg_set_expr_reent_count = 0; | |
12231 | ||
12232 | bool | |
12233 | sh_recog_treg_set_expr (rtx op, machine_mode mode) | |
12234 | { | |
12235 | scope_counter recursion (sh_recog_treg_set_expr_reent_count); | |
12236 | ||
12237 | /* Limit the recursion count to avoid nested expressions which we can't | |
12238 | resolve to a single treg set insn. */ | |
12239 | if (recursion.count () > 1) | |
12240 | return false; | |
12241 | ||
12242 | /* Early accept known possible operands before doing recog. */ | |
6fb917d9 OE |
12243 | if (op == const0_rtx || op == const1_rtx || t_reg_operand (op, mode) |
12244 | || negt_reg_operand (op, mode)) | |
841dbf80 OE |
12245 | return true; |
12246 | ||
12247 | /* Early reject impossible operands before doing recog. | |
12248 | There are some (set ((t) (subreg ...))) patterns, but we must be careful | |
12249 | not to allow any invalid reg-reg or mem-reg moves, or else other passes | |
12250 | such as lower-subreg will bail out. Some insns such as SH4A movua are | |
12251 | done with UNSPEC, so must reject those, too, or else it would result | |
12252 | in an invalid reg -> treg move. */ | |
6fb917d9 OE |
12253 | if (CONST_INT_P (op) || register_operand (op, mode) |
12254 | || memory_operand (op, mode) || sh_unspec_insn_p (op)) | |
841dbf80 OE |
12255 | return false; |
12256 | ||
12257 | if (!can_create_pseudo_p ()) | |
12258 | return false; | |
12259 | ||
fa0a20e3 KK |
12260 | /* expand_debug_locations may call this to compute rtx costs at |
12261 | very early stage. In that case, don't make new insns here to | |
12262 | avoid codegen differences with -g. */ | |
12263 | if (currently_expanding_to_rtl) | |
12264 | return false; | |
12265 | ||
841dbf80 OE |
12266 | /* We are going to invoke recog in a re-entrant way and thus |
12267 | have to capture its current state and restore it afterwards. */ | |
12268 | recog_data_d prev_recog_data = recog_data; | |
12269 | ||
f7df4a84 | 12270 | rtx_insn* i = make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), op)); |
841dbf80 OE |
12271 | SET_PREV_INSN (i) = NULL; |
12272 | SET_NEXT_INSN (i) = NULL; | |
12273 | ||
6fb917d9 OE |
12274 | /* If the comparison op doesn't have a result mode, set it to SImode. */ |
12275 | machine_mode prev_op_mode = GET_MODE (op); | |
12276 | if (COMPARISON_P (op) && prev_op_mode == VOIDmode) | |
12277 | PUT_MODE (op, SImode); | |
12278 | ||
841dbf80 OE |
12279 | int result = recog (PATTERN (i), i, 0); |
12280 | ||
6fb917d9 OE |
12281 | /* It seems there is no insn like that. Create a negated version and |
12282 | try again. If we hit a negated form, we'll allow that and append a | |
12283 | nott sequence when splitting out the insns. Insns that do the split | |
12284 | can then remove the trailing nott if they know how to deal with it. */ | |
12285 | if (result < 0 && COMPARISON_P (op)) | |
841dbf80 | 12286 | { |
6fb917d9 OE |
12287 | machine_mode cmp_mode = GET_MODE (XEXP (op, 0)); |
12288 | if (cmp_mode == VOIDmode) | |
12289 | cmp_mode = GET_MODE (XEXP (op, 1)); | |
12290 | ||
12291 | rtx_code prev_code = GET_CODE (op); | |
12292 | PUT_CODE (op, reverse_condition (GET_CODE (op))); | |
841dbf80 | 12293 | result = recog (PATTERN (i), i, 0); |
6fb917d9 | 12294 | PUT_CODE (op, prev_code); |
841dbf80 OE |
12295 | } |
12296 | ||
6fb917d9 | 12297 | PUT_MODE (op, prev_op_mode); |
841dbf80 OE |
12298 | recog_data = prev_recog_data; |
12299 | return result >= 0; | |
12300 | } | |
12301 | ||
12302 | /* Returns true when recog of a 'treg_set_expr' is currently in progress. | |
12303 | This can be used as a condition for insn/split patterns to allow certain | |
12304 | T bit setting patters only to be matched as sub expressions of other | |
12305 | patterns. */ | |
12306 | bool | |
12307 | sh_in_recog_treg_set_expr (void) | |
12308 | { | |
12309 | return sh_recog_treg_set_expr_reent_count > 0; | |
12310 | } | |
12311 | ||
12312 | /* Given an rtx x, which is assumed to be some expression that has been | |
12313 | matched by the 'treg_set_expr' predicate before, split and emit the | |
12314 | insns that are necessary to calculate the expression and store the result | |
12315 | in the T bit. | |
12316 | The splitting is done recursively similar to 'try_split' in emit-rt.c. | |
12317 | Unfortunately we can't use 'try_split' here directly, as it tries to invoke | |
12318 | 'delete_insn' which then causes the DF parts to bail out, because we | |
12319 | currently are inside another gen_split* function and would invoke | |
12320 | 'try_split' in a reentrant way. */ | |
12321 | static std::pair<rtx_insn*, rtx_insn*> | |
12322 | sh_try_split_insn_simple (rtx_insn* i, rtx_insn* curr_insn, int n = 0) | |
12323 | { | |
12324 | if (dump_file) | |
12325 | { | |
12326 | fprintf (dump_file, "sh_try_split_insn_simple n = %d i = \n", n); | |
12327 | print_rtl_single (dump_file, i); | |
12328 | fprintf (dump_file, "\n"); | |
12329 | } | |
12330 | ||
bb5c4956 | 12331 | rtx_insn* seq = split_insns (PATTERN (i), curr_insn); |
841dbf80 OE |
12332 | |
12333 | if (seq == NULL) | |
12334 | return std::make_pair (i, i); | |
12335 | ||
12336 | /* Avoid infinite splitter loops if any insn of the result matches | |
12337 | the original pattern. */ | |
12338 | for (rtx_insn* s = seq; s != NULL; s = NEXT_INSN (s)) | |
12339 | if (INSN_P (s) && rtx_equal_p (PATTERN (s), PATTERN (i))) | |
12340 | return std::make_pair (i, i); | |
12341 | ||
12342 | unshare_all_rtl_in_chain (seq); | |
12343 | ||
12344 | /* 'seq' is now a replacement for 'i'. Assuming that 'i' is an insn in | |
12345 | a linked list, replace the single insn with the new insns. */ | |
12346 | rtx_insn* seqlast = seq; | |
12347 | while (NEXT_INSN (seqlast) != NULL) | |
12348 | seqlast = NEXT_INSN (seqlast); | |
12349 | ||
12350 | if (rtx_insn* iprev = PREV_INSN (i)) | |
12351 | SET_NEXT_INSN (iprev) = seq; | |
12352 | if (rtx_insn* inext = NEXT_INSN (i)) | |
12353 | SET_PREV_INSN (inext) = seqlast; | |
12354 | ||
12355 | SET_PREV_INSN (seq) = PREV_INSN (i); | |
12356 | SET_NEXT_INSN (seqlast) = NEXT_INSN (i); | |
12357 | ||
12358 | SET_PREV_INSN (i) = NULL; | |
12359 | SET_NEXT_INSN (i) = NULL; | |
12360 | ||
12361 | /* Recursively split all insns. */ | |
12362 | for (i = seq; ; i = NEXT_INSN (i)) | |
12363 | { | |
12364 | std::pair<rtx_insn*, rtx_insn*> ii = | |
12365 | sh_try_split_insn_simple (i, curr_insn, n + 1); | |
12366 | if (i == seq) | |
12367 | seq = ii.first; | |
12368 | if (i == seqlast) | |
12369 | { | |
12370 | seqlast = ii.second; | |
12371 | break; | |
12372 | } | |
12373 | i = ii.first; | |
12374 | } | |
12375 | ||
12376 | return std::make_pair (seq, seqlast); | |
12377 | } | |
12378 | ||
12379 | sh_treg_insns | |
12380 | sh_split_treg_set_expr (rtx x, rtx_insn* curr_insn) | |
12381 | { | |
12382 | if (t_reg_operand (x, VOIDmode)) | |
12383 | return sh_treg_insns (); | |
12384 | ||
12385 | scope_counter in_treg_set_expr (sh_recog_treg_set_expr_reent_count); | |
12386 | ||
f7df4a84 | 12387 | rtx_insn* i = make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), x)); |
841dbf80 OE |
12388 | SET_PREV_INSN (i) = NULL; |
12389 | SET_NEXT_INSN (i) = NULL; | |
12390 | ||
12391 | if (dump_file) | |
12392 | { | |
12393 | fprintf (dump_file, "split_treg_set_expr insn:\n"); | |
12394 | print_rtl (dump_file, i); | |
12395 | fprintf (dump_file, "\n"); | |
12396 | } | |
12397 | ||
6fb917d9 OE |
12398 | /* If the insn is not found, we will try a negated form and append |
12399 | a nott. */ | |
12400 | bool append_nott = false; | |
12401 | ||
841dbf80 OE |
12402 | /* We are going to invoke recog/split_insns in a re-entrant way and thus |
12403 | have to capture its current state and restore it afterwards. */ | |
12404 | recog_data_d prev_recog_data = recog_data; | |
12405 | ||
6fb917d9 | 12406 | if (negt_reg_operand (x, GET_MODE (x))) |
841dbf80 | 12407 | { |
6fb917d9 OE |
12408 | /* This is a normal movt followed by a nott. It will be converted |
12409 | into a movrt after initial expansion. */ | |
12410 | XEXP (PATTERN (i), 1) = get_t_reg_rtx (); | |
12411 | append_nott = true; | |
841dbf80 | 12412 | } |
6fb917d9 | 12413 | else |
841dbf80 | 12414 | { |
6fb917d9 OE |
12415 | /* If the comparison op doesn't have a mode set, set it to SImode. */ |
12416 | if (COMPARISON_P (x) && GET_MODE (x) == VOIDmode) | |
12417 | PUT_MODE (x, SImode); | |
12418 | ||
12419 | int insn_code = recog (PATTERN (i), i, 0); | |
841dbf80 | 12420 | |
6fb917d9 OE |
12421 | if (insn_code < 0 && COMPARISON_P (x)) |
12422 | { | |
12423 | machine_mode cmp_mode = GET_MODE (XEXP (x, 0)); | |
12424 | if (cmp_mode == VOIDmode) | |
12425 | cmp_mode = GET_MODE (XEXP (x, 1)); | |
12426 | ||
12427 | PUT_CODE (x, reverse_condition (GET_CODE (x))); | |
12428 | insn_code = recog (PATTERN (i), i, 0); | |
12429 | append_nott = true; | |
12430 | } | |
12431 | ||
12432 | gcc_assert (insn_code >= 0); | |
12433 | } | |
841dbf80 OE |
12434 | |
12435 | /* Try to recursively split the insn. Some insns might refuse to split | |
12436 | any further while we are in the treg_set_expr splitting phase. They | |
12437 | will be emitted as part of the outer insn and then split again. */ | |
12438 | std::pair<rtx_insn*, rtx_insn*> insnlist = | |
12439 | sh_try_split_insn_simple (i, curr_insn); | |
12440 | ||
12441 | /* Restore recog state. */ | |
12442 | recog_data = prev_recog_data; | |
12443 | ||
12444 | rtx_insn* nott_insn = sh_is_nott_insn (insnlist.second) | |
12445 | ? insnlist.second | |
12446 | : NULL; | |
12447 | if (dump_file) | |
12448 | { | |
12449 | fprintf (dump_file, "split_treg_set_expr insnlist:\n"); | |
12450 | print_rtl (dump_file, insnlist.first); | |
12451 | fprintf (dump_file, "\n"); | |
12452 | ||
12453 | if (nott_insn != NULL) | |
12454 | fprintf (dump_file, "trailing nott insn %d\n", INSN_UID (nott_insn)); | |
12455 | } | |
12456 | ||
48e4f473 OE |
12457 | emit_insn (insnlist.first); |
12458 | ||
841dbf80 OE |
12459 | if (nott_insn != NULL && append_nott) |
12460 | { | |
12461 | if (dump_file) | |
12462 | fprintf (dump_file, "removing trailing nott\n"); | |
12463 | remove_insn (nott_insn); | |
12464 | nott_insn = NULL; | |
12465 | append_nott = false; | |
12466 | } | |
12467 | ||
841dbf80 OE |
12468 | if (append_nott) |
12469 | nott_insn = emit_insn (gen_nott (get_t_reg_rtx ())); | |
12470 | ||
12471 | rtx_insn* first_insn = get_insns (); | |
12472 | ||
12473 | if (dump_file) | |
12474 | { | |
12475 | fprintf (dump_file, "resulting insns:\n"); | |
12476 | print_rtl (dump_file, first_insn); | |
12477 | fprintf (dump_file, "\n"); | |
12478 | } | |
12479 | ||
12480 | return sh_treg_insns (first_insn, nott_insn); | |
12481 | } | |
12482 | ||
83e3f98b OE |
12483 | /*------------------------------------------------------------------------------ |
12484 | Mode switching support code. | |
12485 | */ | |
12486 | ||
06b90602 CB |
12487 | static void |
12488 | sh_emit_mode_set (int entity ATTRIBUTE_UNUSED, int mode, | |
3a2317d1 | 12489 | int prev_mode, HARD_REG_SET regs_live ATTRIBUTE_UNUSED) |
06b90602 | 12490 | { |
cbb1e3d9 CB |
12491 | if ((TARGET_SH4A_FP || TARGET_SH4_300) |
12492 | && prev_mode != FP_MODE_NONE && prev_mode != mode) | |
12493 | { | |
12494 | emit_insn (gen_toggle_pr ()); | |
12495 | if (TARGET_FMOVD) | |
12496 | emit_insn (gen_toggle_sz ()); | |
12497 | } | |
3a2317d1 OE |
12498 | else if (mode != FP_MODE_NONE) |
12499 | { | |
fe3e478f OE |
12500 | rtx tmp = gen_reg_rtx (SImode); |
12501 | emit_insn (gen_sts_fpscr (tmp)); | |
3a2317d1 OE |
12502 | rtx i = NULL; |
12503 | ||
12504 | const unsigned HOST_WIDE_INT fpbits = | |
12505 | TARGET_FMOVD ? (FPSCR_PR | FPSCR_SZ) : FPSCR_PR; | |
12506 | ||
12507 | if (prev_mode != FP_MODE_NONE && prev_mode != mode) | |
fe3e478f | 12508 | i = gen_xorsi3 (tmp, tmp, force_reg (SImode, GEN_INT (fpbits))); |
3a2317d1 | 12509 | else if (mode == FP_MODE_SINGLE) |
fe3e478f | 12510 | i = gen_andsi3 (tmp, tmp, force_reg (SImode, GEN_INT (~fpbits))); |
3a2317d1 | 12511 | else if (mode == FP_MODE_DOUBLE) |
fe3e478f | 12512 | i = gen_iorsi3 (tmp, tmp, force_reg (SImode, GEN_INT (fpbits))); |
3a2317d1 OE |
12513 | else |
12514 | gcc_unreachable (); | |
12515 | ||
12516 | emit_insn (i); | |
fe3e478f | 12517 | emit_insn (gen_lds_fpscr (tmp)); |
3a2317d1 | 12518 | } |
06b90602 CB |
12519 | } |
12520 | ||
12521 | static int | |
ac44248e | 12522 | sh_mode_needed (int entity ATTRIBUTE_UNUSED, rtx_insn *insn) |
06b90602 CB |
12523 | { |
12524 | return recog_memoized (insn) >= 0 ? get_attr_fp_mode (insn) : FP_MODE_NONE; | |
12525 | } | |
12526 | ||
12527 | static int | |
ac44248e | 12528 | sh_mode_after (int entity ATTRIBUTE_UNUSED, int mode, rtx_insn *insn) |
06b90602 CB |
12529 | { |
12530 | if (TARGET_HITACHI && recog_memoized (insn) >= 0 && | |
12531 | get_attr_fp_set (insn) != FP_SET_NONE) | |
12532 | return (int) get_attr_fp_set (insn); | |
12533 | else | |
12534 | return mode; | |
12535 | } | |
12536 | ||
12537 | static int | |
12538 | sh_mode_entry (int entity ATTRIBUTE_UNUSED) | |
12539 | { | |
12540 | return NORMAL_MODE (entity); | |
12541 | } | |
12542 | ||
12543 | static int | |
12544 | sh_mode_exit (int entity ATTRIBUTE_UNUSED) | |
12545 | { | |
12546 | return sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (entity); | |
12547 | } | |
12548 | ||
12549 | static int | |
12550 | sh_mode_priority (int entity ATTRIBUTE_UNUSED, int n) | |
12551 | { | |
12552 | return ((TARGET_FPU_SINGLE != 0) ^ (n) ? FP_MODE_SINGLE : FP_MODE_DOUBLE); | |
12553 | } | |
12554 | ||
83e3f98b OE |
12555 | /*------------------------------------------------------------------------------ |
12556 | Misc | |
12557 | */ | |
12558 | ||
106a52b7 | 12559 | /* Return true if we use LRA instead of reload pass. */ |
a981b743 | 12560 | bool |
106a52b7 KK |
12561 | sh_lra_p (void) |
12562 | { | |
12563 | return sh_lra_flag; | |
12564 | } | |
12565 | ||
ae59bd31 JG |
12566 | /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */ |
12567 | ||
12568 | static bool | |
445d7826 | 12569 | sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size, |
ae59bd31 JG |
12570 | unsigned int align, |
12571 | enum by_pieces_operation op, | |
12572 | bool speed_p) | |
12573 | { | |
12574 | switch (op) | |
12575 | { | |
12576 | case MOVE_BY_PIECES: | |
56812845 | 12577 | return by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1, op) |
ae59bd31 JG |
12578 | < (!speed_p ? 2 : (align >= 32) ? 16 : 2); |
12579 | case STORE_BY_PIECES: | |
12580 | case SET_BY_PIECES: | |
56812845 | 12581 | return by_pieces_ninsns (size, align, STORE_MAX_PIECES + 1, op) |
ae59bd31 JG |
12582 | < (!speed_p ? 2 : (align >= 32) ? 16 : 2); |
12583 | default: | |
12584 | return default_use_by_pieces_infrastructure_p (size, align, | |
12585 | op, speed_p); | |
12586 | } | |
12587 | } | |
12588 | ||
1e44e857 DJ |
12589 | bool |
12590 | sh_cannot_force_const_mem_p (machine_mode mode ATTRIBUTE_UNUSED, | |
12591 | rtx x ATTRIBUTE_UNUSED) | |
12592 | { | |
12593 | return TARGET_FDPIC; | |
12594 | } | |
12595 | ||
12596 | /* Emit insns to load the function address from FUNCDESC (an FDPIC | |
12597 | function descriptor) into r1 and the GOT address into r12, | |
12598 | returning an rtx for r1. */ | |
12599 | ||
12600 | rtx | |
12601 | sh_load_function_descriptor (rtx funcdesc) | |
12602 | { | |
12603 | rtx r1 = gen_rtx_REG (Pmode, R1_REG); | |
12604 | rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG); | |
12605 | rtx fnaddr = gen_rtx_MEM (Pmode, funcdesc); | |
12606 | rtx gotaddr = gen_rtx_MEM (Pmode, plus_constant (Pmode, funcdesc, 4)); | |
12607 | ||
12608 | emit_move_insn (r1, fnaddr); | |
12609 | /* The ABI requires the entry point address to be loaded first, so | |
12610 | prevent the load from being moved after that of the GOT | |
12611 | address. */ | |
12612 | emit_insn (gen_blockage ()); | |
12613 | emit_move_insn (pic_reg, gotaddr); | |
12614 | return r1; | |
12615 | } | |
12616 | ||
12617 | /* Return an rtx holding the initial value of the FDPIC register (the | |
12618 | FDPIC pointer passed in from the caller). */ | |
12619 | ||
12620 | rtx | |
12621 | sh_get_fdpic_reg_initial_val (void) | |
12622 | { | |
12623 | return get_hard_reg_initial_val (Pmode, PIC_REG); | |
12624 | } | |
12625 | ||
e2500fed | 12626 | #include "gt-sh.h" |