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[thirdparty/gcc.git] / gcc / config / sh / sh.c
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c8f0269d 1/* Output routines for GCC for Renesas / SuperH SH.
5b71da26 2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
2efd0aa6 3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
e938feb4 4 Free Software Foundation, Inc.
c5c76735 5 Contributed by Steve Chamberlain (sac@cygnus.com).
f676971a 6 Improved by Jim Wilson (wilson@cygnus.com).
bc45ade3 7
7ec022b2 8This file is part of GCC.
c15c9075 9
7ec022b2 10GCC is free software; you can redistribute it and/or modify
c15c9075 11it under the terms of the GNU General Public License as published by
2f83c7d6 12the Free Software Foundation; either version 3, or (at your option)
c15c9075
RK		 13any later version.
14
7ec022b2 15GCC is distributed in the hope that it will be useful,
c15c9075
RK		 16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
2f83c7d6
NC		 21along with GCC; see the file COPYING3. If not see
22<http://www.gnu.org/licenses/>. */
bc45ade3 23
bc45ade3 24#include "config.h"
c5c76735 25#include "system.h"
4977bab6
ZW		 26#include "coretypes.h"
27#include "tm.h"
318881c0 28#include "insn-config.h"
bc45ade3 29#include "rtl.h"
bc45ade3 30#include "tree.h"
bc45ade3 31#include "flags.h"
bc45ade3 32#include "expr.h"
e78d8e51 33#include "optabs.h"
6f50eb9c 34#include "reload.h"
49ad7cfa 35#include "function.h"
8aa2a305
JW		 36#include "regs.h"
37#include "hard-reg-set.h"
38#include "output.h"
956a5206 39#include "insn-attr.h"
718f9c0f 40#include "diagnostic-core.h"
318881c0 41#include "recog.h"
950a3816 42#include "integrate.h"
a80b0574 43#include "dwarf2.h"
318881c0 44#include "tm_p.h"
672a6f42
NB		 45#include "target.h"
46#include "target-def.h"
c1b92d09 47#include "langhooks.h"
1aa03f38 48#include "basic-block.h"
6fb5fa3c 49#include "df.h"
117dca74 50#include "cfglayout.h"
bcc8cc82 51#include "intl.h"
58565a33 52#include "sched-int.h"
bd9a3465 53#include "params.h"
8582b18a 54#include "ggc.h"
726a989a 55#include "gimple.h"
73a4d10b 56#include "cfgloop.h"
6dd3c0a5 57#include "alloc-pool.h"
32a7ab3d 58#include "tm-constrs.h"
96e45421 59#include "opts.h"
5fac2ed2 60
bc45ade3 61
1245df60
R		 62int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
63
00f8ff66
SC		 64#define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
65#define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
66
fa5322fa
AO		 67/* These are some macros to abstract register modes. */
68#define CONST_OK_FOR_ADD(size) \
735cb76e 69 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
fa5322fa
AO		 70#define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
71#define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
72#define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
73
561642fa
AP		 74/* Used to simplify the logic below. Find the attributes wherever
75 they may be. */
76#define SH_ATTRIBUTES(decl) \
77 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
78 : DECL_ATTRIBUTES (decl) \
79 ? (DECL_ATTRIBUTES (decl)) \
80 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
81
552ecbd9
AH		 82/* Set to 1 by expand_prologue() when the function is an interrupt handler. */
83int current_function_interrupt;
84
a6ab9fc0
R		 85tree sh_deferred_function_attributes;
86tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
16bea517 87
6f317ef3 88/* Global variables for machine-dependent things. */
bc45ade3 89
16bea517
JW		 90/* Which cpu are we scheduling for. */
91enum processor_type sh_cpu;
92
58565a33
SKG		 93/* Definitions used in ready queue reordering for first scheduling pass. */
94
95/* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
96static short *regmode_weight[2];
97
98/* Total SFmode and SImode weights of scheduled insns. */
99static int curr_regmode_pressure[2];
100
6fb5fa3c
DB		 101/* Number of r0 life regions. */
102static int r0_life_regions;
103
58565a33
SKG		 104/* If true, skip cycles for Q -> R movement. */
105static int skip_cycles = 0;
106
107/* Cached value of can_issue_more. This is cached in sh_variable_issue hook
108 and returned from sh_reorder2. */
109static short cached_can_issue_more;
110
826159e5
KK		 111/* Unique number for UNSPEC_BBR pattern. */
112static unsigned int unspec_bbr_uid = 1;
113
bc45ade3 114/* Provides the class number of the smallest class containing
16bea517 115 reg number. */
bc45ade3 116
fada1961 117enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
bc45ade3 118{
8e87e161 119 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
bc45ade3
SC		 120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
fa5322fa
AO		 123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
131 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
132 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
133 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
1a95a963
JW		 135 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
fa5322fa
AO		 139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
147 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
148 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
149 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
152 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
225e4f43
R		 153 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
154 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
fa5322fa
AO		 155 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
156 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
96a2347e 157 GENERAL_REGS, GENERAL_REGS,
225e4f43
R		 158};
159
fa5322fa
AO		 160char sh_register_names[FIRST_PSEUDO_REGISTER] \
161 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
162
163char sh_additional_register_names[ADDREGNAMES_SIZE] \
164 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
165 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
bc45ade3 166
225e4f43
R		 167int assembler_dialect;
168
fe3ad572
SC		 169static bool shmedia_space_reserved_for_target_registers;
170
96e45421
JM		 171static bool sh_handle_option (struct gcc_options *, struct gcc_options *,
172 const struct cl_decoded_option *, location_t);
cf277499
SB		 173static void split_branches (rtx);
174static int branch_dest (rtx);
175static void force_into (rtx, rtx);
176static void print_slot (rtx);
177static rtx add_constant (rtx, enum machine_mode, rtx);
078c8b08 178static void dump_table (rtx, rtx);
cf277499
SB		 179static int hi_const (rtx);
180static int broken_move (rtx);
181static int mova_p (rtx);
182static rtx find_barrier (int, rtx, rtx);
183static int noncall_uses_reg (rtx, rtx, rtx *);
184static rtx gen_block_redirect (rtx, int, int);
185static void sh_reorg (void);
e7a8f681 186static void sh_option_override (void);
7e4aae92 187static void sh_option_init_struct (struct gcc_options *);
128dc8e2 188static void sh_option_default_params (void);
21d05694 189static void output_stack_adjust (int, rtx, int, HARD_REG_SET *, bool);
cf277499
SB		 190static rtx frame_insn (rtx);
191static rtx push (int);
192static void pop (int);
193static void push_regs (HARD_REG_SET *, int);
194static int calc_live_regs (HARD_REG_SET *);
cf277499 195static HOST_WIDE_INT rounded_frame_size (int);
7a296495 196static bool sh_frame_pointer_required (void);
cf277499 197static rtx mark_constant_pool_use (rtx);
cf277499 198static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
561642fa
AP		 199static tree sh_handle_resbank_handler_attribute (tree *, tree,
200 tree, int, bool *);
201static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
202 tree, int, bool *);
cf277499
SB		 203static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
204static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
205static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
9e94b957
NF		 206static void sh_print_operand (FILE *, rtx, int);
207static void sh_print_operand_address (FILE *, rtx);
208static bool sh_print_operand_punct_valid_p (unsigned char code);
ef875e12 209static bool sh_asm_output_addr_const_extra (FILE *file, rtx x);
cf277499
SB		 210static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
211static void sh_insert_attributes (tree, tree *);
8d932be3 212static const char *sh_check_pch_target_flags (int);
e7a8f681 213static int sh_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
cf277499 214static int sh_adjust_cost (rtx, rtx, rtx, int);
cf277499 215static int sh_issue_rate (void);
58565a33
SKG		 216static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
217static short find_set_regmode_weight (rtx, enum machine_mode);
218static short find_insn_regmode_weight (rtx, enum machine_mode);
c6d56443 219static void find_regmode_weight (basic_block, enum machine_mode);
6fb5fa3c 220static int find_r0_life_regions (basic_block);
58565a33
SKG		 221static void sh_md_init_global (FILE *, int, int);
222static void sh_md_finish_global (FILE *, int);
223static int rank_for_reorder (const void *, const void *);
224static void swap_reorder (rtx *, int);
225static void ready_reorder (rtx *, int);
226static short high_pressure (enum machine_mode);
227static int sh_reorder (FILE *, int, rtx *, int *, int);
228static int sh_reorder2 (FILE *, int, rtx *, int *, int);
229static void sh_md_init (FILE *, int, int);
230static int sh_variable_issue (FILE *, int, rtx, int);
f676971a 231
cf277499
SB		 232static bool sh_function_ok_for_sibcall (tree, tree);
233
234static bool sh_cannot_modify_jumps_p (void);
a87cf97e 235static reg_class_t sh_target_reg_class (void);
fe3ad572 236static bool sh_optimize_target_register_callee_saved (bool);
3101faab 237static bool sh_ms_bitfield_layout_p (const_tree);
cf277499
SB		 238
239static void sh_init_builtins (void);
1cc24576 240static tree sh_builtin_decl (unsigned, bool);
cf277499 241static void sh_media_init_builtins (void);
1cc24576 242static tree sh_media_builtin_decl (unsigned, bool);
cf277499
SB		 243static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
244static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
245static void sh_file_start (void);
246static int flow_dependent_p (rtx, rtx);
7bc980e1 247static void flow_dependent_p_1 (rtx, const_rtx, void *);
cf277499
SB		 248static int shiftcosts (rtx);
249static int andcosts (rtx);
250static int addsubcosts (rtx);
251static int multcosts (rtx);
252static bool unspec_caller_rtx_p (rtx);
253static bool sh_cannot_copy_insn_p (rtx);
f40751dd
JH		 254static bool sh_rtx_costs (rtx, int, int, int *, bool);
255static int sh_address_cost (rtx, bool);
b48f503c
KK		 256static int sh_pr_n_sets (void);
257static rtx sh_allocate_initial_value (rtx);
486b10aa
AS		 258static reg_class_t sh_preferred_reload_class (rtx, reg_class_t);
259static reg_class_t sh_secondary_reload (bool, rtx, reg_class_t,
260 enum machine_mode,
261 struct secondary_reload_info *);
1bb99877 262static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);
506d7b68 263static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
90833f7f 264static rtx sh_delegitimize_address (rtx);
fe3ad572
SC		 265static int shmedia_target_regs_stack_space (HARD_REG_SET *);
266static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
267static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
fada1961
R		 268static int scavenge_reg (HARD_REG_SET *s);
269struct save_schedule_s;
270static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
271 struct save_schedule_s *, int);
61f71b34 272
cf277499 273static rtx sh_struct_value_rtx (tree, int);
d64728cf 274static rtx sh_function_value (const_tree, const_tree, bool);
e7a8f681 275static bool sh_function_value_regno_p (const unsigned int);
d64728cf 276static rtx sh_libcall_value (enum machine_mode, const_rtx);
586de218 277static bool sh_return_in_memory (const_tree, const_tree);
cf277499
SB		 278static rtx sh_builtin_saveregs (void);
279static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
280static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
281static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
c35d187f 282static tree sh_build_builtin_va_list (void);
d7bd8aeb 283static void sh_va_start (tree, rtx);
726a989a 284static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
d64728cf 285static bool sh_promote_prototypes (const_tree);
d055ce45
KK		 286static enum machine_mode sh_promote_function_mode (const_tree type,
287 enum machine_mode,
288 int *punsignedp,
289 const_tree funtype,
6e957ac8 290 int for_return);
8cd5a4e0 291static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
586de218 292 const_tree, bool);
6cdd5672 293static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
586de218 294 const_tree, bool);
78a52f11
RH		 295static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
296 tree, bool);
b64336b8
NF		 297static void sh_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
298 const_tree, bool);
299static rtx sh_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
300 const_tree, bool);
b0fbea13 301static bool sh_scalar_mode_supported_p (enum machine_mode);
3101faab 302static int sh_dwarf_calling_convention (const_tree);
561642fa
AP		 303static void sh_encode_section_info (tree, rtx, int);
304static int sh2a_function_vector_p (tree);
994322ef
RH		 305static void sh_trampoline_init (rtx, tree, rtx);
306static rtx sh_trampoline_adjust_address (rtx);
5efd84c5 307static void sh_conditional_register_usage (void);
5a82ecd9
ILT		 308\f
309static const struct attribute_spec sh_attribute_table[] =
310{
62d784f7
KT		 311 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
312 affects_type_identity } */
313 { "interrupt_handler", 0, 0, true, false, false,
314 sh_handle_interrupt_handler_attribute, false },
315 { "sp_switch", 1, 1, true, false, false,
316 sh_handle_sp_switch_attribute, false },
317 { "trap_exit", 1, 1, true, false, false,
318 sh_handle_trap_exit_attribute, false },
319 { "renesas", 0, 0, false, true, false,
320 sh_handle_renesas_attribute, false },
321 { "trapa_handler", 0, 0, true, false, false,
322 sh_handle_interrupt_handler_attribute, false },
323 { "nosave_low_regs", 0, 0, true, false, false,
324 sh_handle_interrupt_handler_attribute, false },
325 { "resbank", 0, 0, true, false, false,
326 sh_handle_resbank_handler_attribute, false },
327 { "function_vector", 1, 1, true, false, false,
328 sh2a_handle_function_vector_handler_attribute, false },
62d784f7 329 { NULL, 0, 0, false, false, false, NULL, false }
5a82ecd9 330};
3020190e
JM		 331
332/* Set default optimization options. */
333static const struct default_options sh_option_optimization_table[] =
334 {
335 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
336 { OPT_LEVELS_1_PLUS_SPEED_ONLY, OPT_mdiv_, "inv:minlat", 1 },
337 { OPT_LEVELS_SIZE, OPT_mdiv_, SH_DIV_STR_FOR_SIZE, 1 },
338 { OPT_LEVELS_0_ONLY, OPT_mdiv_, "", 1 },
339 { OPT_LEVELS_SIZE, OPT_mcbranchdi, NULL, 0 },
340 /* We can't meaningfully test TARGET_SHMEDIA here, because -m
341 options haven't been parsed yet, hence we'd read only the
342 default. sh_target_reg_class will return NO_REGS if this is
343 not SHMEDIA, so it's OK to always set
344 flag_branch_target_load_optimize. */
345 { OPT_LEVELS_2_PLUS, OPT_fbranch_target_load_optimize, NULL, 1 },
346 { OPT_LEVELS_NONE, 0, NULL, 0 }
347 };
672a6f42
NB		 348\f
349/* Initialize the GCC target structure. */
91d231cb
JM		 350#undef TARGET_ATTRIBUTE_TABLE
351#define TARGET_ATTRIBUTE_TABLE sh_attribute_table
672a6f42 352
301d03af
RS		 353/* The next two are used for debug info when compiling with -gdwarf. */
354#undef TARGET_ASM_UNALIGNED_HI_OP
355#define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
356#undef TARGET_ASM_UNALIGNED_SI_OP
357#define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
358
c5387660 359/* These are NULLed out on non-SH5 in TARGET_OPTION_OVERRIDE. */
fa5322fa
AO		 360#undef TARGET_ASM_UNALIGNED_DI_OP
361#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
362#undef TARGET_ASM_ALIGNED_DI_OP
363#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
364
e7a8f681
N		 365#undef TARGET_OPTION_OVERRIDE
366#define TARGET_OPTION_OVERRIDE sh_option_override
3020190e
JM		 367#undef TARGET_OPTION_OPTIMIZATION_TABLE
368#define TARGET_OPTION_OPTIMIZATION_TABLE sh_option_optimization_table
7e4aae92
JM		 369#undef TARGET_OPTION_INIT_STRUCT
370#define TARGET_OPTION_INIT_STRUCT sh_option_init_struct
128dc8e2
JM		 371#undef TARGET_OPTION_DEFAULT_PARAMS
372#define TARGET_OPTION_DEFAULT_PARAMS sh_option_default_params
e7a8f681 373
9e94b957
NF		 374#undef TARGET_PRINT_OPERAND
375#define TARGET_PRINT_OPERAND sh_print_operand
376#undef TARGET_PRINT_OPERAND_ADDRESS
377#define TARGET_PRINT_OPERAND_ADDRESS sh_print_operand_address
378#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
379#define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p
ef875e12
AS		 380#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
381#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra
382
08c148a8
NB		 383#undef TARGET_ASM_FUNCTION_EPILOGUE
384#define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
385
1aa03f38
R		 386#undef TARGET_ASM_OUTPUT_MI_THUNK
387#define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
388
389#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
3101faab 390#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1aa03f38 391
1bc7c5b6
ZW		 392#undef TARGET_ASM_FILE_START
393#define TARGET_ASM_FILE_START sh_file_start
394#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
395#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
396
c0fb94d7
RS		 397#undef TARGET_DEFAULT_TARGET_FLAGS
398#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
399#undef TARGET_HANDLE_OPTION
400#define TARGET_HANDLE_OPTION sh_handle_option
401
e7a8f681
N		 402#undef TARGET_REGISTER_MOVE_COST
403#define TARGET_REGISTER_MOVE_COST sh_register_move_cost
404
12a68f1f
JM		 405#undef TARGET_INSERT_ATTRIBUTES
406#define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
407
c237e94a
ZW		 408#undef TARGET_SCHED_ADJUST_COST
409#define TARGET_SCHED_ADJUST_COST sh_adjust_cost
410
fae15c93
VM		 411#undef TARGET_SCHED_ISSUE_RATE
412#define TARGET_SCHED_ISSUE_RATE sh_issue_rate
413
58565a33
SKG		 414/* The next 5 hooks have been implemented for reenabling sched1. With the
415 help of these macros we are limiting the movement of insns in sched1 to
f676971a 416 reduce the register pressure. The overall idea is to keep count of SImode
58565a33
SKG		 417 and SFmode regs required by already scheduled insns. When these counts
418 cross some threshold values; give priority to insns that free registers.
419 The insn that frees registers is most likely to be the insn with lowest
f676971a 420 LUID (original insn order); but such an insn might be there in the stalled
58565a33
SKG		 421 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
422 upto a max of 8 cycles so that such insns may move from Q -> R.
423
424 The description of the hooks are as below:
425
426 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
427 scheduler; it is called inside the sched_init function just after
428 find_insn_reg_weights function call. It is used to calculate the SImode
1ae58c30 429 and SFmode weights of insns of basic blocks; much similar to what
f676971a 430 find_insn_reg_weights does.
58565a33
SKG		 431 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
432
433 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
434 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
435 (Q)->(R).
436
437 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
438 high; reorder the ready queue so that the insn with lowest LUID will be
439 issued next.
440
441 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
442 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
443
444 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
445 can be returned from TARGET_SCHED_REORDER2.
446
447 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
448
449#undef TARGET_SCHED_DFA_NEW_CYCLE
450#define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
451
452#undef TARGET_SCHED_INIT_GLOBAL
453#define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
454
455#undef TARGET_SCHED_FINISH_GLOBAL
456#define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
457
458#undef TARGET_SCHED_VARIABLE_ISSUE
459#define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
460
461#undef TARGET_SCHED_REORDER
462#define TARGET_SCHED_REORDER sh_reorder
463
464#undef TARGET_SCHED_REORDER2
465#define TARGET_SCHED_REORDER2 sh_reorder2
466
467#undef TARGET_SCHED_INIT
468#define TARGET_SCHED_INIT sh_md_init
469
90833f7f
KK		 470#undef TARGET_DELEGITIMIZE_ADDRESS
471#define TARGET_DELEGITIMIZE_ADDRESS sh_delegitimize_address
472
506d7b68
PB		 473#undef TARGET_LEGITIMIZE_ADDRESS
474#define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
475
fa5322fa
AO		 476#undef TARGET_CANNOT_MODIFY_JUMPS_P
477#define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
fe3ad572
SC		 478#undef TARGET_BRANCH_TARGET_REGISTER_CLASS
479#define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
480#undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
481#define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
482 sh_optimize_target_register_callee_saved
fa5322fa
AO		 483
484#undef TARGET_MS_BITFIELD_LAYOUT_P
485#define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
486
c1b92d09
R		 487#undef TARGET_INIT_BUILTINS
488#define TARGET_INIT_BUILTINS sh_init_builtins
1cc24576
KK		 489#undef TARGET_BUILTIN_DECL
490#define TARGET_BUILTIN_DECL sh_builtin_decl
c1b92d09
R		 491#undef TARGET_EXPAND_BUILTIN
492#define TARGET_EXPAND_BUILTIN sh_expand_builtin
493
4977bab6
ZW		 494#undef TARGET_FUNCTION_OK_FOR_SIBCALL
495#define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
496
9f3a9a08
KK		 497#undef TARGET_CANNOT_COPY_INSN_P
498#define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
3c50106f
RH		 499#undef TARGET_RTX_COSTS
500#define TARGET_RTX_COSTS sh_rtx_costs
dcefdf67
RH		 501#undef TARGET_ADDRESS_COST
502#define TARGET_ADDRESS_COST sh_address_cost
b48f503c
KK		 503#undef TARGET_ALLOCATE_INITIAL_VALUE
504#define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
3c50106f 505
18dbd950
RS		 506#undef TARGET_MACHINE_DEPENDENT_REORG
507#define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
508
63a9de54
CB		 509#undef TARGET_DWARF_REGISTER_SPAN
510#define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
511
463f02cd
KK		 512#ifdef HAVE_AS_TLS
513#undef TARGET_HAVE_TLS
514#define TARGET_HAVE_TLS true
515#endif
516
61f71b34
DD		 517#undef TARGET_PROMOTE_PROTOTYPES
518#define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
d055ce45
KK		 519#undef TARGET_PROMOTE_FUNCTION_MODE
520#define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode
61f71b34 521
d64728cf
AS		 522#undef TARGET_FUNCTION_VALUE
523#define TARGET_FUNCTION_VALUE sh_function_value
e7a8f681
N		 524#undef TARGET_FUNCTION_VALUE_REGNO_P
525#define TARGET_FUNCTION_VALUE_REGNO_P sh_function_value_regno_p
d64728cf
AS		 526#undef TARGET_LIBCALL_VALUE
527#define TARGET_LIBCALL_VALUE sh_libcall_value
61f71b34
DD		 528#undef TARGET_STRUCT_VALUE_RTX
529#define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
530#undef TARGET_RETURN_IN_MEMORY
531#define TARGET_RETURN_IN_MEMORY sh_return_in_memory
532
533#undef TARGET_EXPAND_BUILTIN_SAVEREGS
534#define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
535#undef TARGET_SETUP_INCOMING_VARARGS
536#define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
537#undef TARGET_STRICT_ARGUMENT_NAMING
538#define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
539#undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
540#define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
fe984136
RH		 541#undef TARGET_MUST_PASS_IN_STACK
542#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
8cd5a4e0
RH		 543#undef TARGET_PASS_BY_REFERENCE
544#define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
6cdd5672
RH		 545#undef TARGET_CALLEE_COPIES
546#define TARGET_CALLEE_COPIES sh_callee_copies
78a52f11
RH		 547#undef TARGET_ARG_PARTIAL_BYTES
548#define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
b64336b8
NF		 549#undef TARGET_FUNCTION_ARG
550#define TARGET_FUNCTION_ARG sh_function_arg
551#undef TARGET_FUNCTION_ARG_ADVANCE
552#define TARGET_FUNCTION_ARG_ADVANCE sh_function_arg_advance
61f71b34 553
c35d187f
RH		 554#undef TARGET_BUILD_BUILTIN_VA_LIST
555#define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
d7bd8aeb
JJ		 556#undef TARGET_EXPAND_BUILTIN_VA_START
557#define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
5fac2ed2
RH		 558#undef TARGET_GIMPLIFY_VA_ARG_EXPR
559#define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
c35d187f 560
b0fbea13
KK		 561#undef TARGET_SCALAR_MODE_SUPPORTED_P
562#define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
f676971a
EC		 563#undef TARGET_VECTOR_MODE_SUPPORTED_P
564#define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
565
8d932be3
RS		 566#undef TARGET_CHECK_PCH_TARGET_FLAGS
567#define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
bcc8cc82 568
a1c496cb
EC		 569#undef TARGET_DWARF_CALLING_CONVENTION
570#define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
571
7a296495
CB		 572#undef TARGET_FRAME_POINTER_REQUIRED
573#define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required
574
58565a33
SKG		 575/* Return regmode weight for insn. */
576#define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
577
578/* Return current register pressure for regmode. */
579#define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
580
561642fa
AP		 581#undef TARGET_ENCODE_SECTION_INFO
582#define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
583
8a99f6f9
R		 584#undef TARGET_SECONDARY_RELOAD
585#define TARGET_SECONDARY_RELOAD sh_secondary_reload
586
486b10aa
AS		 587#undef TARGET_PREFERRED_RELOAD_CLASS
588#define TARGET_PREFERRED_RELOAD_CLASS sh_preferred_reload_class
589
5efd84c5
NF		 590#undef TARGET_CONDITIONAL_REGISTER_USAGE
591#define TARGET_CONDITIONAL_REGISTER_USAGE sh_conditional_register_usage
592
1bb99877
KK		 593#undef TARGET_LEGITIMATE_ADDRESS_P
594#define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
595
994322ef
RH		 596#undef TARGET_TRAMPOLINE_INIT
597#define TARGET_TRAMPOLINE_INIT sh_trampoline_init
598#undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
599#define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address
600
561642fa
AP		 601/* Machine-specific symbol_ref flags. */
602#define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
603
f6897b10 604struct gcc_target targetm = TARGET_INITIALIZER;
b9654711 605\f
c0fb94d7
RS		 606/* Implement TARGET_HANDLE_OPTION. */
607
608static bool
96e45421
JM		 609sh_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
610 const struct cl_decoded_option *decoded,
611 location_t loc ATTRIBUTE_UNUSED)
c0fb94d7 612{
96e45421
JM		 613 size_t code = decoded->opt_index;
614
615 gcc_assert (opts == &global_options);
616 gcc_assert (opts_set == &global_options_set);
617
c0fb94d7
RS		 618 switch (code)
619 {
620 case OPT_m1:
621 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
622 return true;
623
624 case OPT_m2:
625 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
626 return true;
627
628 case OPT_m2a:
629 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
630 return true;
631
632 case OPT_m2a_nofpu:
633 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
634 return true;
635
636 case OPT_m2a_single:
637 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
638 return true;
639
640 case OPT_m2a_single_only:
641 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
642 return true;
643
644 case OPT_m2e:
645 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
646 return true;
647
648 case OPT_m3:
649 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
650 return true;
651
652 case OPT_m3e:
653 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
654 return true;
655
656 case OPT_m4:
25e651ca
AS		 657 case OPT_m4_100:
658 case OPT_m4_200:
78d310c2 659 case OPT_m4_300:
c0fb94d7
RS		 660 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
661 return true;
662
663 case OPT_m4_nofpu:
78d310c2
R		 664 case OPT_m4_100_nofpu:
665 case OPT_m4_200_nofpu:
666 case OPT_m4_300_nofpu:
667 case OPT_m4_340:
25e651ca
AS		 668 case OPT_m4_400:
669 case OPT_m4_500:
c0fb94d7
RS		 670 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
671 return true;
672
673 case OPT_m4_single:
25e651ca
AS		 674 case OPT_m4_100_single:
675 case OPT_m4_200_single:
78d310c2 676 case OPT_m4_300_single:
c0fb94d7
RS		 677 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
678 return true;
679
680 case OPT_m4_single_only:
25e651ca
AS		 681 case OPT_m4_100_single_only:
682 case OPT_m4_200_single_only:
78d310c2 683 case OPT_m4_300_single_only:
c0fb94d7
RS		 684 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
685 return true;
686
687 case OPT_m4a:
688 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
689 return true;
690
691 case OPT_m4a_nofpu:
692 case OPT_m4al:
693 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
694 return true;
695
696 case OPT_m4a_single:
697 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
698 return true;
699
700 case OPT_m4a_single_only:
701 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
702 return true;
703
704 case OPT_m5_32media:
705 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
706 return true;
707
708 case OPT_m5_32media_nofpu:
709 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
710 return true;
711
712 case OPT_m5_64media:
713 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
714 return true;
715
716 case OPT_m5_64media_nofpu:
717 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
718 return true;
719
720 case OPT_m5_compact:
721 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
722 return true;
723
724 case OPT_m5_compact_nofpu:
725 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
726 return true;
727
728 default:
729 return true;
730 }
731}
732\f
7e4aae92
JM		 733/* Implement TARGET_OPTION_INIT_STRUCT. */
734static void
735sh_option_init_struct (struct gcc_options *opts)
736{
737 /* We can't meaningfully test TARGET_SH2E / TARGET_IEEE
738 here, so leave it to TARGET_OPTION_OVERRIDE to set
739 flag_finite_math_only. We set it to 2 here so we know if the user
740 explicitly requested this to be on or off. */
741 opts->x_flag_finite_math_only = 2;
742}
743
128dc8e2
JM		 744/* Implement TARGET_OPTION_DEFAULT_PARAMS. */
745static void
746sh_option_default_params (void)
747{
748 set_default_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 2);
bd9a3465
KK		 749}
750
e7a8f681
N		 751/* Implement TARGET_OPTION_OVERRIDE macro. Validate and override
752 various options, and do some machine dependent initialization. */
753static void
754sh_option_override (void)
bd9a3465
KK		 755{
756 int regno;
757
758 SUBTARGET_OVERRIDE_OPTIONS;
3020190e
JM		 759 if (optimize > 1 && !optimize_size)
760 target_flags |= MASK_SAVE_ALL_TARGET_REGS;
bd9a3465
KK		 761 if (flag_finite_math_only == 2)
762 flag_finite_math_only
763 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;
764 if (TARGET_SH2E && !flag_finite_math_only)
765 target_flags |= MASK_IEEE;
766 sh_cpu = PROCESSOR_SH1;
767 assembler_dialect = 0;
768 if (TARGET_SH2)
769 sh_cpu = PROCESSOR_SH2;
770 if (TARGET_SH2E)
771 sh_cpu = PROCESSOR_SH2E;
772 if (TARGET_SH2A)
7a61cf6f 773 sh_cpu = PROCESSOR_SH2A;
bd9a3465
KK		 774 if (TARGET_SH3)
775 sh_cpu = PROCESSOR_SH3;
776 if (TARGET_SH3E)
777 sh_cpu = PROCESSOR_SH3E;
778 if (TARGET_SH4)
779 {
780 assembler_dialect = 1;
781 sh_cpu = PROCESSOR_SH4;
782 }
783 if (TARGET_SH4A_ARCH)
784 {
785 assembler_dialect = 1;
786 sh_cpu = PROCESSOR_SH4A;
787 }
788 if (TARGET_SH5)
789 {
790 sh_cpu = PROCESSOR_SH5;
791 target_flags |= MASK_ALIGN_DOUBLE;
792 if (TARGET_SHMEDIA_FPU)
793 target_flags |= MASK_FMOVD;
794 if (TARGET_SHMEDIA)
795 {
796 /* There are no delay slots on SHmedia. */
797 flag_delayed_branch = 0;
798 /* Relaxation isn't yet supported for SHmedia */
799 target_flags &= ~MASK_RELAX;
800 /* After reload, if conversion does little good but can cause
801 ICEs:
802 - find_if_block doesn't do anything for SH because we don't
803 have conditional execution patterns. (We use conditional
804 move patterns, which are handled differently, and only
805 before reload).
806 - find_cond_trap doesn't do anything for the SH because we
807 don't have conditional traps.
808 - find_if_case_1 uses redirect_edge_and_branch_force in
809 the only path that does an optimization, and this causes
810 an ICE when branch targets are in registers.
811 - find_if_case_2 doesn't do anything for the SHmedia after
812 reload except when it can redirect a tablejump - and
813 that's rather rare. */
814 flag_if_conversion2 = 0;
815 if (! strcmp (sh_div_str, "call"))
816 sh_div_strategy = SH_DIV_CALL;
817 else if (! strcmp (sh_div_str, "call2"))
818 sh_div_strategy = SH_DIV_CALL2;
819 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)
820 sh_div_strategy = SH_DIV_FP;
821 else if (! strcmp (sh_div_str, "inv"))
822 sh_div_strategy = SH_DIV_INV;
823 else if (! strcmp (sh_div_str, "inv:minlat"))
824 sh_div_strategy = SH_DIV_INV_MINLAT;
825 else if (! strcmp (sh_div_str, "inv20u"))
826 sh_div_strategy = SH_DIV_INV20U;
827 else if (! strcmp (sh_div_str, "inv20l"))
828 sh_div_strategy = SH_DIV_INV20L;
829 else if (! strcmp (sh_div_str, "inv:call2"))
830 sh_div_strategy = SH_DIV_INV_CALL2;
831 else if (! strcmp (sh_div_str, "inv:call"))
832 sh_div_strategy = SH_DIV_INV_CALL;
833 else if (! strcmp (sh_div_str, "inv:fp"))
834 {
835 if (TARGET_FPU_ANY)
836 sh_div_strategy = SH_DIV_INV_FP;
837 else
838 sh_div_strategy = SH_DIV_INV;
839 }
840 TARGET_CBRANCHDI4 = 0;
841 /* Assembler CFI isn't yet fully supported for SHmedia. */
842 flag_dwarf2_cfi_asm = 0;
843 }
844 }
845 else
846 {
847 /* Only the sh64-elf assembler fully supports .quad properly. */
848 targetm.asm_out.aligned_op.di = NULL;
849 targetm.asm_out.unaligned_op.di = NULL;
850 }
851 if (TARGET_SH1)
852 {
853 if (! strcmp (sh_div_str, "call-div1"))
854 sh_div_strategy = SH_DIV_CALL_DIV1;
855 else if (! strcmp (sh_div_str, "call-fp")
856 && (TARGET_FPU_DOUBLE
857 || (TARGET_HARD_SH4 && TARGET_SH2E)
858 || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))
859 sh_div_strategy = SH_DIV_CALL_FP;
860 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2)
861 sh_div_strategy = SH_DIV_CALL_TABLE;
862 else
863 /* Pick one that makes most sense for the target in general.
864 It is not much good to use different functions depending
865 on -Os, since then we'll end up with two different functions
866 when some of the code is compiled for size, and some for
867 speed. */
868
869 /* SH4 tends to emphasize speed. */
870 if (TARGET_HARD_SH4)
871 sh_div_strategy = SH_DIV_CALL_TABLE;
872 /* These have their own way of doing things. */
873 else if (TARGET_SH2A)
874 sh_div_strategy = SH_DIV_INTRINSIC;
875 /* ??? Should we use the integer SHmedia function instead? */
876 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)
877 sh_div_strategy = SH_DIV_CALL_FP;
878 /* SH1 .. SH3 cores often go into small-footprint systems, so
879 default to the smallest implementation available. */
880 else if (TARGET_SH2) /* ??? EXPERIMENTAL */
881 sh_div_strategy = SH_DIV_CALL_TABLE;
882 else
883 sh_div_strategy = SH_DIV_CALL_DIV1;
884 }
885 if (!TARGET_SH1)
886 TARGET_PRETEND_CMOVE = 0;
887 if (sh_divsi3_libfunc[0])
888 ; /* User supplied - leave it alone. */
889 else if (TARGET_DIVIDE_CALL_FP)
890 sh_divsi3_libfunc = "__sdivsi3_i4";
891 else if (TARGET_DIVIDE_CALL_TABLE)
892 sh_divsi3_libfunc = "__sdivsi3_i4i";
893 else if (TARGET_SH5)
894 sh_divsi3_libfunc = "__sdivsi3_1";
895 else
896 sh_divsi3_libfunc = "__sdivsi3";
897 if (sh_branch_cost == -1)
898 sh_branch_cost
899 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1;
900
901 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
902 if (! VALID_REGISTER_P (regno))
903 sh_register_names[regno][0] = '\0';
904
905 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
906 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
907 sh_additional_register_names[regno][0] = '\0';
908
7a296495 909 flag_omit_frame_pointer = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);
bd9a3465
KK		 910
911 if ((flag_pic && ! TARGET_PREFERGOT)
912 || (TARGET_SHMEDIA && !TARGET_PT_FIXED))
913 flag_no_function_cse = 1;
914
42db504c 915 if (targetm.small_register_classes_for_mode_p (VOIDmode)) \
bd9a3465
KK		 916 {
917 /* Never run scheduling before reload, since that can
918 break global alloc, and generates slower code anyway due
919 to the pressure on R0. */
920 /* Enable sched1 for SH4 if the user explicitly requests.
921 When sched1 is enabled, the ready queue will be reordered by
922 the target hooks if pressure is high. We can not do this for
923 PIC, SH3 and lower as they give spill failures for R0. */
924 if (!TARGET_HARD_SH4 || flag_pic)
925 flag_schedule_insns = 0;
926 /* ??? Current exception handling places basic block boundaries
927 after call_insns. It causes the high pressure on R0 and gives
928 spill failures for R0 in reload. See PR 22553 and the thread
929 on gcc-patches
930 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
931 else if (flag_exceptions)
932 {
0a587f65 933 if (flag_schedule_insns && global_options_set.x_flag_schedule_insns)
bd9a3465
KK		 934 warning (0, "ignoring -fschedule-insns because of exception handling bug");
935 flag_schedule_insns = 0;
936 }
0a587f65
JM		 937 else if (flag_schedule_insns
938 && !global_options_set.x_flag_schedule_insns)
bd9a3465
KK		 939 flag_schedule_insns = 0;
940 }
941
7a296495
CB		 942 if ((target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS) == 0)
943 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
944
945 /* Unwind info is not correct around the CFG unless either a frame
946 pointer is present or M_A_O_A is set. Fixing this requires rewriting
947 unwind info generation to be aware of the CFG and propagating states
948 around edges. */
949 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
950 || flag_exceptions || flag_non_call_exceptions)
951 && flag_omit_frame_pointer
952 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
953 {
954 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
955 warning (0, "unwind tables currently require either a frame pointer "
956 "or -maccumulate-outgoing-args for correctness");
957 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
958 }
959
91d1d521
KK		 960 /* Unwinding with -freorder-blocks-and-partition does not work on this
961 architecture, because it requires far jumps to label crossing between
962 hot/cold sections which are rejected on this architecture. */
963 if (flag_reorder_blocks_and_partition)
964 {
965 if (flag_exceptions)
966 {
967 inform (input_location,
968 "-freorder-blocks-and-partition does not work with "
969 "exceptions on this architecture");
970 flag_reorder_blocks_and_partition = 0;
971 flag_reorder_blocks = 1;
972 }
973 else if (flag_unwind_tables)
974 {
975 inform (input_location,
976 "-freorder-blocks-and-partition does not support unwind "
977 "info on this architecture");
978 flag_reorder_blocks_and_partition = 0;
979 flag_reorder_blocks = 1;
980 }
981 }
982
bd9a3465
KK		 983 if (align_loops == 0)
984 align_loops = 1 << (TARGET_SH5 ? 3 : 2);
985 if (align_jumps == 0)
986 align_jumps = 1 << CACHE_LOG;
987 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))
988 align_jumps = TARGET_SHMEDIA ? 4 : 2;
989
990 /* Allocation boundary (in *bytes*) for the code of a function.
991 SH1: 32 bit alignment is faster, because instructions are always
992 fetched as a pair from a longword boundary.
993 SH2 .. SH5 : align to cache line start. */
994 if (align_functions == 0)
995 align_functions
3020190e 996 = optimize_size ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);
bd9a3465
KK		 997 /* The linker relaxation code breaks when a function contains
998 alignments that are larger than that at the start of a
999 compilation unit. */
1000 if (TARGET_RELAX)
1001 {
1002 int min_align
1003 = align_loops > align_jumps ? align_loops : align_jumps;
1004
1005 /* Also take possible .long constants / mova tables int account. */
1006 if (min_align < 4)
1007 min_align = 4;
1008 if (align_functions < min_align)
1009 align_functions = min_align;
1010 }
1011
1012 if (sh_fixed_range_str)
1013 sh_fix_range (sh_fixed_range_str);
0685e770
DD		 1014
1015 /* This target defaults to strict volatile bitfields. */
1016 if (flag_strict_volatile_bitfields < 0)
1017 flag_strict_volatile_bitfields = 1;
bd9a3465
KK		 1018}
1019\f
16bea517 1020/* Print the operand address in x to the stream. */
bc45ade3 1021
9e94b957
NF		 1022static void
1023sh_print_operand_address (FILE *stream, rtx x)
bc45ade3
SC		 1024{
1025 switch (GET_CODE (x))
1026 {
1027 case REG:
225e4f43
R		 1028 case SUBREG:
1029 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
bc45ade3 1030 break;
8aa2a305 1031
bc45ade3
SC		 1032 case PLUS:
1033 {
1034 rtx base = XEXP (x, 0);
1035 rtx index = XEXP (x, 1);
1036
bc45ade3
SC		 1037 switch (GET_CODE (index))
1038 {
1039 case CONST_INT:
c5b9ef02 1040 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
225e4f43 1041 reg_names[true_regnum (base)]);
bc45ade3
SC		 1042 break;
1043
1044 case REG:
225e4f43
R		 1045 case SUBREG:
1046 {
1047 int base_num = true_regnum (base);
1048 int index_num = true_regnum (index);
1049
1050 fprintf (stream, "@(r0,%s)",
1051 reg_names[MAX (base_num, index_num)]);
1052 break;
1053 }
bc45ade3
SC		 1054
1055 default:
f5b9e7c9 1056 gcc_unreachable ();
bc45ade3
SC		 1057 }
1058 }
bc45ade3 1059 break;
8aa2a305 1060
bc45ade3 1061 case PRE_DEC:
225e4f43 1062 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
bc45ade3
SC		 1063 break;
1064
1065 case POST_INC:
225e4f43 1066 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
bc45ade3
SC		 1067 break;
1068
1069 default:
b91455de 1070 x = mark_constant_pool_use (x);
422be3c3 1071 output_addr_const (stream, x);
bc45ade3
SC		 1072 break;
1073 }
1074}
1075
1076/* Print operand x (an rtx) in assembler syntax to file stream
1077 according to modifier code.
1078
b9654711 1079 '.' print a .s if insn needs delay slot
1245df60 1080 ',' print LOCAL_LABEL_PREFIX
4408efce 1081 '@' print trap, rte or rts depending upon pragma interruptness
8aa2a305 1082 '#' output a nop if there is nothing to put in the delay slot
fae778eb 1083 ''' print likelihood suffix (/u for unlikely).
73a4d10b 1084 '>' print branch target if -fverbose-asm
8aa2a305 1085 'O' print a constant without the #
00f8ff66 1086 'R' print the LSW of a dp value - changes if in little endian
00f8ff66 1087 'S' print the MSW of a dp value - changes if in little endian
225e4f43 1088 'T' print the next word of a dp value - same as 'R' in big endian mode.
31b6f0ae
R		 1089 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
1090 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
c1b92d09 1091 'N' print 'r63' if the operand is (const_int 0).
312209c6 1092 'd' print a V2SF reg as dN instead of fpN.
fa5322fa 1093 'm' print a pair `base,offset' or `base,index', for LD and ST.
73a4d10b 1094 'U' Likewise for {LD,ST}{HI,LO}.
de6adfa2
N		 1095 'V' print the position of a single bit set.
1096 'W' print the position of a single bit cleared.
9eb3a0dd 1097 't' print a memory address which is a register.
fa5322fa 1098 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
225e4f43 1099 'o' output an operator. */
bc45ade3 1100
9e94b957
NF		 1101static void
1102sh_print_operand (FILE *stream, rtx x, int code)
bc45ade3 1103{
73a4d10b
R		 1104 int regno;
1105 enum machine_mode mode;
1106
bc45ade3
SC		 1107 switch (code)
1108 {
a6ab9fc0
R		 1109 tree trapa_attr;
1110
b9654711 1111 case '.':
79b2746a 1112 if (final_sequence
c608a684
R		 1113 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
1114 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
1245df60
R		 1115 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
1116 break;
1117 case ',':
1118 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
b9654711 1119 break;
d3ae8277 1120 case '@':
a6ab9fc0
R		 1121 trapa_attr = lookup_attribute ("trap_exit",
1122 DECL_ATTRIBUTES (current_function_decl));
1123 if (trapa_attr)
1124 fprintf (stream, "trapa #%ld",
1125 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
e3ba8d11 1126 else if (sh_cfun_interrupt_handler_p ())
561642fa
AP		 1127 {
1128 if (sh_cfun_resbank_handler_p ())
1129 fprintf (stream, "resbank\n");
1130 fprintf (stream, "rte");
1131 }
d3ae8277 1132 else
8e87e161 1133 fprintf (stream, "rts");
d3ae8277 1134 break;
bc45ade3 1135 case '#':
16bea517 1136 /* Output a nop if there's nothing in the delay slot. */
bc45ade3 1137 if (dbr_sequence_length () == 0)
8aa2a305 1138 fprintf (stream, "\n\tnop");
bc45ade3 1139 break;
c8cc4417
R		 1140 case '\'':
1141 {
1142 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
1143
1144 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
1145 fputs ("/u", stream);
1146 break;
1147 }
73a4d10b
R		 1148 case '>':
1149 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
1150 {
1151 fputs ("\t! target: ", stream);
1152 output_addr_const (stream, JUMP_LABEL (current_output_insn));
1153 }
1154 break;
b9654711 1155 case 'O':
b91455de 1156 x = mark_constant_pool_use (x);
0d7e008e 1157 output_addr_const (stream, x);
bc45ade3 1158 break;
4802062c
R		 1159 /* N.B.: %R / %S / %T adjust memory addresses by four.
1160 For SHMEDIA, that means they can be used to access the first and
1161 second 32 bit part of a 64 bit (or larger) value that
1162 might be held in floating point registers or memory.
1163 While they can be used to access 64 bit parts of a larger value
1164 held in general purpose registers, that won't work with memory -
1165 neither for fp registers, since the frxx names are used. */
bc45ade3 1166 case 'R':
4802062c
R		 1167 if (REG_P (x) || GET_CODE (x) == SUBREG)
1168 {
1169 regno = true_regnum (x);
1170 regno += FP_REGISTER_P (regno) ? 1 : LSW;
1171 fputs (reg_names[regno], (stream));
1172 }
1173 else if (MEM_P (x))
1174 {
1175 x = adjust_address (x, SImode, 4 * LSW);
9e94b957 1176 sh_print_operand_address (stream, XEXP (x, 0));
4802062c
R		 1177 }
1178 else
1179 {
1180 rtx sub = NULL_RTX;
1181
1182 mode = GET_MODE (x);
1183 if (mode == VOIDmode)
1184 mode = DImode;
1185 if (GET_MODE_SIZE (mode) >= 8)
1186 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
1187 if (sub)
9e94b957 1188 sh_print_operand (stream, sub, 0);
4802062c
R		 1189 else
1190 output_operand_lossage ("invalid operand to %%R");
1191 }
8aa2a305
JW		 1192 break;
1193 case 'S':
4802062c
R		 1194 if (REG_P (x) || GET_CODE (x) == SUBREG)
1195 {
1196 regno = true_regnum (x);
1197 regno += FP_REGISTER_P (regno) ? 0 : MSW;
1198 fputs (reg_names[regno], (stream));
1199 }
1200 else if (MEM_P (x))
1201 {
1202 x = adjust_address (x, SImode, 4 * MSW);
9e94b957 1203 sh_print_operand_address (stream, XEXP (x, 0));
4802062c
R		 1204 }
1205 else
1206 {
1207 rtx sub = NULL_RTX;
1208
1209 mode = GET_MODE (x);
1210 if (mode == VOIDmode)
1211 mode = DImode;
1212 if (GET_MODE_SIZE (mode) >= 8)
1213 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
1214 if (sub)
9e94b957 1215 sh_print_operand (stream, sub, 0);
4802062c
R		 1216 else
1217 output_operand_lossage ("invalid operand to %%S");
1218 }
00f8ff66
SC		 1219 break;
1220 case 'T':
16bea517 1221 /* Next word of a double. */
bc45ade3
SC		 1222 switch (GET_CODE (x))
1223 {
1224 case REG:
1225 fputs (reg_names[REGNO (x) + 1], (stream));
1226 break;
1227 case MEM:
225e4f43
R		 1228 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
1229 && GET_CODE (XEXP (x, 0)) != POST_INC)
b72f00af 1230 x = adjust_address (x, SImode, 4);
9e94b957 1231 sh_print_operand_address (stream, XEXP (x, 0));
bc45ade3 1232 break;
318881c0
KG		 1233 default:
1234 break;
bc45ade3
SC		 1235 }
1236 break;
9eb3a0dd
N		 1237
1238 case 't':
f3536097 1239 gcc_assert (MEM_P (x));
9eb3a0dd
N		 1240 x = XEXP (x, 0);
1241 switch (GET_CODE (x))
1242 {
1243 case REG:
1244 case SUBREG:
9e94b957 1245 sh_print_operand (stream, x, 0);
9eb3a0dd
N		 1246 break;
1247 default:
1248 break;
1249 }
1250 break;
1251
225e4f43
R		 1252 case 'o':
1253 switch (GET_CODE (x))
1254 {
1255 case PLUS: fputs ("add", stream); break;
1256 case MINUS: fputs ("sub", stream); break;
1257 case MULT: fputs ("mul", stream); break;
1258 case DIV: fputs ("div", stream); break;
c8cc4417
R		 1259 case EQ: fputs ("eq", stream); break;
1260 case NE: fputs ("ne", stream); break;
1261 case GT: case LT: fputs ("gt", stream); break;
1262 case GE: case LE: fputs ("ge", stream); break;
1263 case GTU: case LTU: fputs ("gtu", stream); break;
1264 case GEU: case LEU: fputs ("geu", stream); break;
318881c0
KG		 1265 default:
1266 break;
225e4f43
R		 1267 }
1268 break;
fa5322fa 1269 case 'M':
31b6f0ae
R		 1270 if (TARGET_SHMEDIA)
1271 {
f3536097 1272 if (MEM_P (x)
31b6f0ae 1273 && GET_CODE (XEXP (x, 0)) == PLUS
f3536097 1274 && (REG_P (XEXP (XEXP (x, 0), 1))
31b6f0ae
R		 1275 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
1276 fputc ('x', stream);
1277 }
1278 else
1279 {
f3536097 1280 if (MEM_P (x))
31b6f0ae
R		 1281 {
1282 switch (GET_MODE (x))
1283 {
1284 case QImode: fputs (".b", stream); break;
1285 case HImode: fputs (".w", stream); break;
1286 case SImode: fputs (".l", stream); break;
1287 case SFmode: fputs (".s", stream); break;
1288 case DFmode: fputs (".d", stream); break;
1289 default: gcc_unreachable ();
1290 }
1291 }
1292 }
fa5322fa
AO		 1293 break;
1294
1295 case 'm':
f3536097 1296 gcc_assert (MEM_P (x));
fa5322fa 1297 x = XEXP (x, 0);
73a4d10b
R		 1298 /* Fall through. */
1299 case 'U':
fa5322fa
AO		 1300 switch (GET_CODE (x))
1301 {
1302 case REG:
1303 case SUBREG:
9e94b957 1304 sh_print_operand (stream, x, 0);
fa5322fa
AO		 1305 fputs (", 0", stream);
1306 break;
1307
1308 case PLUS:
9e94b957 1309 sh_print_operand (stream, XEXP (x, 0), 0);
fa5322fa 1310 fputs (", ", stream);
9e94b957 1311 sh_print_operand (stream, XEXP (x, 1), 0);
fa5322fa
AO		 1312 break;
1313
1314 default:
f5b9e7c9 1315 gcc_unreachable ();
fa5322fa
AO		 1316 }
1317 break;
1318
de6adfa2
N		 1319 case 'V':
1320 {
1321 int num = exact_log2 (INTVAL (x));
1322 gcc_assert (num >= 0);
1323 fprintf (stream, "#%d", num);
1324 }
1325 break;
1326
1327 case 'W':
1328 {
1329 int num = exact_log2 (~INTVAL (x));
1330 gcc_assert (num >= 0);
1331 fprintf (stream, "#%d", num);
1332 }
1333 break;
1334
312209c6 1335 case 'd':
f3536097 1336 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
312209c6
AO		 1337
1338 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1339 break;
f676971a 1340
c1b92d09 1341 case 'N':
0ac78517 1342 if (x == CONST0_RTX (GET_MODE (x)))
c1b92d09
R		 1343 {
1344 fprintf ((stream), "r63");
1345 break;
1346 }
1347 goto default_output;
fa5322fa 1348 case 'u':
f3536097 1349 if (CONST_INT_P (x))
c8cc4417 1350 {
fa5322fa
AO		 1351 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
1352 break;
1353 }
1354 /* Fall through. */
1355
c1b92d09 1356 default_output:
bc45ade3 1357 default:
73a4d10b
R		 1358 regno = 0;
1359 mode = GET_MODE (x);
1360
bc45ade3
SC		 1361 switch (GET_CODE (x))
1362 {
73a4d10b
R		 1363 case TRUNCATE:
1364 {
1365 rtx inner = XEXP (x, 0);
1366 int offset = 0;
1367 enum machine_mode inner_mode;
1368
1369 /* We might see SUBREGs with vector mode registers inside. */
1370 if (GET_CODE (inner) == SUBREG
1371 && (GET_MODE_SIZE (GET_MODE (inner))
1372 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1373 && subreg_lowpart_p (inner))
1374 inner = SUBREG_REG (inner);
f3536097 1375 if (CONST_INT_P (inner))
73a4d10b
R		 1376 {
1377 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
1378 goto default_output;
1379 }
1380 inner_mode = GET_MODE (inner);
1381 if (GET_CODE (inner) == SUBREG
1382 && (GET_MODE_SIZE (GET_MODE (inner))
1383 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
f3536097 1384 && REG_P (SUBREG_REG (inner)))
73a4d10b
R		 1385 {
1386 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
1387 GET_MODE (SUBREG_REG (inner)),
1388 SUBREG_BYTE (inner),
1389 GET_MODE (inner));
1390 inner = SUBREG_REG (inner);
1391 }
f3536097 1392 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
73a4d10b
R		 1393 abort ();
1394 /* Floating point register pairs are always big endian;
30dc60c7 1395 general purpose registers are 64 bit wide. */
73a4d10b
R		 1396 regno = REGNO (inner);
1397 regno = (HARD_REGNO_NREGS (regno, inner_mode)
1398 - HARD_REGNO_NREGS (regno, mode))
1399 + offset;
1400 x = inner;
1401 goto reg;
1402 }
1403 case SIGN_EXTEND:
1404 x = XEXP (x, 0);
1405 goto reg;
fa5322fa
AO		 1406 /* FIXME: We need this on SHmedia32 because reload generates
1407 some sign-extended HI or QI loads into DImode registers
1408 but, because Pmode is SImode, the address ends up with a
1409 subreg:SI of the DImode register. Maybe reload should be
1410 fixed so as to apply alter_subreg to such loads? */
73a4d10b
R		 1411 case IF_THEN_ELSE:
1412 gcc_assert (trapping_target_operand (x, VOIDmode));
1413 x = XEXP (XEXP (x, 2), 0);
1414 goto default_output;
fa5322fa 1415 case SUBREG:
f5b9e7c9 1416 gcc_assert (SUBREG_BYTE (x) == 0
f3536097 1417 && REG_P (SUBREG_REG (x)));
fa5322fa
AO		 1418
1419 x = SUBREG_REG (x);
1420 /* Fall through. */
1421
73a4d10b 1422 reg:
bc45ade3 1423 case REG:
73a4d10b
R		 1424 regno += REGNO (x);
1425 if (FP_REGISTER_P (regno)
1426 && mode == V16SFmode)
1427 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
fa5322fa 1428 else if (FP_REGISTER_P (REGNO (x))
73a4d10b
R		 1429 && mode == V4SFmode)
1430 fprintf ((stream), "fv%s", reg_names[regno] + 2);
f3536097 1431 else if (REG_P (x)
73a4d10b
R		 1432 && mode == V2SFmode)
1433 fprintf ((stream), "fp%s", reg_names[regno] + 2);
fa5322fa 1434 else if (FP_REGISTER_P (REGNO (x))
73a4d10b
R		 1435 && GET_MODE_SIZE (mode) > 4)
1436 fprintf ((stream), "d%s", reg_names[regno] + 1);
225e4f43 1437 else
73a4d10b 1438 fputs (reg_names[regno], (stream));
bc45ade3 1439 break;
fa5322fa 1440
bc45ade3
SC		 1441 case MEM:
1442 output_address (XEXP (x, 0));
1443 break;
f676971a 1444
bc45ade3 1445 default:
fa5322fa
AO		 1446 if (TARGET_SH1)
1447 fputc ('#', stream);
bc45ade3
SC		 1448 output_addr_const (stream, x);
1449 break;
bc45ade3
SC		 1450 }
1451 break;
1452 }
1453}
9e94b957
NF		 1454
1455static bool
1456sh_print_operand_punct_valid_p (unsigned char code)
1457{
1458 return (code == '.' || code == '#' || code == '@' || code == ','
1459 || code == '$' || code == '\'' || code == '>');
1460}
ef875e12
AS		 1461
1462/* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
1463
1464static bool
1465sh_asm_output_addr_const_extra (FILE *file, rtx x)
1466{
1467 if (GET_CODE (x) == UNSPEC)
1468 {
1469 switch (XINT (x, 1))
1470 {
1471 case UNSPEC_DATALABEL:
1472 fputs ("datalabel ", file);
1473 output_addr_const (file, XVECEXP (x, 0, 0));
1474 break;
1475 case UNSPEC_PIC:
1476 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
1477 output_addr_const (file, XVECEXP (x, 0, 0));
1478 break;
1479 case UNSPEC_GOT:
1480 output_addr_const (file, XVECEXP (x, 0, 0));
1481 fputs ("@GOT", file);
1482 break;
1483 case UNSPEC_GOTOFF:
1484 output_addr_const (file, XVECEXP (x, 0, 0));
1485 fputs ("@GOTOFF", file);
1486 break;
1487 case UNSPEC_PLT:
1488 output_addr_const (file, XVECEXP (x, 0, 0));
1489 fputs ("@PLT", file);
1490 break;
1491 case UNSPEC_GOTPLT:
1492 output_addr_const (file, XVECEXP (x, 0, 0));
1493 fputs ("@GOTPLT", file);
1494 break;
1495 case UNSPEC_DTPOFF:
1496 output_addr_const (file, XVECEXP (x, 0, 0));
1497 fputs ("@DTPOFF", file);
1498 break;
1499 case UNSPEC_GOTTPOFF:
1500 output_addr_const (file, XVECEXP (x, 0, 0));
1501 fputs ("@GOTTPOFF", file);
1502 break;
1503 case UNSPEC_TPOFF:
1504 output_addr_const (file, XVECEXP (x, 0, 0));
1505 fputs ("@TPOFF", file);
1506 break;
1507 case UNSPEC_CALLER:
1508 {
1509 char name[32];
1510 /* LPCS stands for Label for PIC Call Site. */
1511 targetm.asm_out.generate_internal_label (name, "LPCS",
1512 INTVAL (XVECEXP (x, 0, 0)));
1513 assemble_name (file, name);
1514 }
1515 break;
1516 case UNSPEC_EXTRACT_S16:
1517 case UNSPEC_EXTRACT_U16:
1518 {
1519 rtx val, shift;
1520
1521 val = XVECEXP (x, 0, 0);
1522 shift = XVECEXP (x, 0, 1);
1523 fputc ('(', file);
1524 if (shift != const0_rtx)
1525 fputc ('(', file);
1526 if (GET_CODE (val) == CONST
1527 || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ)
1528 {
1529 fputc ('(', file);
1530 output_addr_const (file, val);
1531 fputc (')', file);
1532 }
1533 else
1534 output_addr_const (file, val);
1535 if (shift != const0_rtx)
1536 {
1537 fputs (" >> ", file);
1538 output_addr_const (file, shift);
1539 fputc (')', file);
1540 }
1541 fputs (" & 65535)", file);
1542 }
1543 break;
1544 case UNSPEC_SYMOFF:
1545 output_addr_const (file, XVECEXP (x, 0, 0));
1546 fputc ('-', file);
1547 if (GET_CODE (XVECEXP (x, 0, 1)) == CONST)
1548 {
1549 fputc ('(', file);
1550 output_addr_const (file, XVECEXP (x, 0, 1));
1551 fputc (')', file);
1552 }
1553 else
1554 output_addr_const (file, XVECEXP (x, 0, 1));
1555 break;
1556 case UNSPEC_PCREL_SYMOFF:
1557 output_addr_const (file, XVECEXP (x, 0, 0));
1558 fputs ("-(", file);
1559 output_addr_const (file, XVECEXP (x, 0, 1));
1560 fputs ("-.)", file);
1561 break;
1562 default:
1563 return false;
1564 }
1565 return true;
1566 }
1567 else
1568 return false;
1569}
bc45ade3 1570\f
561642fa
AP		 1571
1572/* Encode symbol attributes of a SYMBOL_REF into its
1573 SYMBOL_REF_FLAGS. */
1574static void
1575sh_encode_section_info (tree decl, rtx rtl, int first)
1576{
1577 default_encode_section_info (decl, rtl, first);
1578
1579 if (TREE_CODE (decl) == FUNCTION_DECL
1580 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1581 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1582}
1583
0aa692fc
R		 1584/* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1585static void
cf277499 1586force_into (rtx value, rtx target)
0aa692fc
R		 1587{
1588 value = force_operand (value, target);
1589 if (! rtx_equal_p (value, target))
1590 emit_insn (gen_move_insn (target, value));
1591}
1592
0d7e008e
SC		 1593/* Emit code to perform a block move. Choose the best method.
1594
1595 OPERANDS[0] is the destination.
1596 OPERANDS[1] is the source.
1597 OPERANDS[2] is the size.
1598 OPERANDS[3] is the alignment safe to use. */
1599
0d7e008e 1600int
cf277499 1601expand_block_move (rtx *operands)
0d7e008e
SC		 1602{
1603 int align = INTVAL (operands[3]);
f3536097 1604 int constp = (CONST_INT_P (operands[2]));
0d7e008e 1605 int bytes = (constp ? INTVAL (operands[2]) : 0);
0d7e008e 1606
312209c6
AO		 1607 if (! constp)
1608 return 0;
1609
1610 /* If we could use mov.l to move words and dest is word-aligned, we
1611 can use movua.l for loads and still generate a relatively short
1612 and efficient sequence. */
1613 if (TARGET_SH4A_ARCH && align < 4
1614 && MEM_ALIGN (operands[0]) >= 32
1615 && can_move_by_pieces (bytes, 32))
1616 {
1617 rtx dest = copy_rtx (operands[0]);
1618 rtx src = copy_rtx (operands[1]);
1619 /* We could use different pseudos for each copied word, but
1620 since movua can only load into r0, it's kind of
1621 pointless. */
1622 rtx temp = gen_reg_rtx (SImode);
1623 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1624 int copied = 0;
1625
1626 while (copied + 4 <= bytes)
1627 {
1628 rtx to = adjust_address (dest, SImode, copied);
85144c5c
RS		 1629 rtx from = adjust_automodify_address (src, BLKmode,
1630 src_addr, copied);
312209c6 1631
85144c5c 1632 set_mem_size (from, GEN_INT (4));
312209c6
AO		 1633 emit_insn (gen_movua (temp, from));
1634 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1635 emit_move_insn (to, temp);
1636 copied += 4;
1637 }
1638
1639 if (copied < bytes)
1640 move_by_pieces (adjust_address (dest, BLKmode, copied),
1641 adjust_automodify_address (src, BLKmode,
1642 src_addr, copied),
1643 bytes - copied, align, 0);
1644
1645 return 1;
1646 }
1647
8aa2a305
JW		 1648 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1649 alignment, or if it isn't a multiple of 4 bytes, then fail. */
312209c6 1650 if (align < 4 || (bytes % 4 != 0))
d3ae8277
SC		 1651 return 0;
1652
225e4f43
R		 1653 if (TARGET_HARD_SH4)
1654 {
1655 if (bytes < 12)
1656 return 0;
1657 else if (bytes == 12)
1658 {
73a4d10b 1659 rtx func_addr_rtx = gen_reg_rtx (Pmode);
c0d4e710
KH		 1660 rtx r4 = gen_rtx_REG (SImode, 4);
1661 rtx r5 = gen_rtx_REG (SImode, 5);
225e4f43 1662
73a4d10b 1663 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
0aa692fc
R		 1664 force_into (XEXP (operands[0], 0), r4);
1665 force_into (XEXP (operands[1], 0), r5);
225e4f43
R		 1666 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1667 return 1;
1668 }
3020190e 1669 else if (! optimize_size)
225e4f43 1670 {
73a4d10b
R		 1671 const char *entry_name;
1672 rtx func_addr_rtx = gen_reg_rtx (Pmode);
225e4f43 1673 int dwords;
c0d4e710
KH		 1674 rtx r4 = gen_rtx_REG (SImode, 4);
1675 rtx r5 = gen_rtx_REG (SImode, 5);
1676 rtx r6 = gen_rtx_REG (SImode, 6);
225e4f43 1677
73a4d10b
R		 1678 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1679 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
0aa692fc
R		 1680 force_into (XEXP (operands[0], 0), r4);
1681 force_into (XEXP (operands[1], 0), r5);
225e4f43
R		 1682
1683 dwords = bytes >> 3;
1684 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1685 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1686 return 1;
1687 }
1688 else
1689 return 0;
1690 }
8aa2a305 1691 if (bytes < 64)
0d7e008e
SC		 1692 {
1693 char entry[30];
73a4d10b 1694 rtx func_addr_rtx = gen_reg_rtx (Pmode);
c5c76735
JL		 1695 rtx r4 = gen_rtx_REG (SImode, 4);
1696 rtx r5 = gen_rtx_REG (SImode, 5);
8aa2a305 1697
70128ad9 1698 sprintf (entry, "__movmemSI%d", bytes);
73a4d10b 1699 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
0aa692fc
R		 1700 force_into (XEXP (operands[0], 0), r4);
1701 force_into (XEXP (operands[1], 0), r5);
0d7e008e
SC		 1702 emit_insn (gen_block_move_real (func_addr_rtx));
1703 return 1;
1704 }
8aa2a305
JW		 1705
1706 /* This is the same number of bytes as a memcpy call, but to a different
1707 less common function name, so this will occasionally use more space. */
3020190e 1708 if (! optimize_size)
0d7e008e 1709 {
73a4d10b 1710 rtx func_addr_rtx = gen_reg_rtx (Pmode);
8aa2a305 1711 int final_switch, while_loop;
c5c76735
JL		 1712 rtx r4 = gen_rtx_REG (SImode, 4);
1713 rtx r5 = gen_rtx_REG (SImode, 5);
1714 rtx r6 = gen_rtx_REG (SImode, 6);
0d7e008e 1715
73a4d10b 1716 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
0aa692fc
R		 1717 force_into (XEXP (operands[0], 0), r4);
1718 force_into (XEXP (operands[1], 0), r5);
0d7e008e 1719
8aa2a305
JW		 1720 /* r6 controls the size of the move. 16 is decremented from it
1721 for each 64 bytes moved. Then the negative bit left over is used
1722 as an index into a list of move instructions. e.g., a 72 byte move
1723 would be set up with size(r6) = 14, for one iteration through the
1724 big while loop, and a switch of -2 for the last part. */
0d7e008e 1725
8aa2a305
JW		 1726 final_switch = 16 - ((bytes / 4) % 16);
1727 while_loop = ((bytes / 4) / 16 - 1) * 16;
1728 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1729 emit_insn (gen_block_lump_real (func_addr_rtx));
1730 return 1;
0d7e008e 1731 }
0d7e008e 1732
d3ae8277 1733 return 0;
0d7e008e
SC		 1734}
1735
bc45ade3 1736/* Prepare operands for a move define_expand; specifically, one of the
8aa2a305 1737 operands must be in a register. */
bc45ade3 1738
b9654711 1739int
cf277499 1740prepare_move_operands (rtx operands[], enum machine_mode mode)
bc45ade3 1741{
463f02cd
KK		 1742 if ((mode == SImode || mode == DImode)
1743 && flag_pic
1744 && ! ((mode == Pmode || mode == ptr_mode)
81f40b79 1745 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1a66cd67
AO		 1746 {
1747 rtx temp;
1748 if (SYMBOLIC_CONST_P (operands[1]))
1749 {
f3536097 1750 if (MEM_P (operands[0]))
1a66cd67 1751 operands[1] = force_reg (Pmode, operands[1]);
5615d8fd
SC		 1752 else if (TARGET_SHMEDIA
1753 && GET_CODE (operands[1]) == LABEL_REF
fa5322fa
AO		 1754 && target_reg_operand (operands[0], mode))
1755 /* It's ok. */;
1a66cd67
AO		 1756 else
1757 {
b3a13419
ILT		 1758 temp = (!can_create_pseudo_p ()
1759 ? operands[0]
1760 : gen_reg_rtx (Pmode));
fa5322fa 1761 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1a66cd67
AO		 1762 }
1763 }
1764 else if (GET_CODE (operands[1]) == CONST
1765 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1766 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1767 {
b3a13419 1768 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1a66cd67 1769 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
fa5322fa
AO		 1770 mode, temp);
1771 operands[1] = expand_binop (mode, add_optab, temp,
1a66cd67 1772 XEXP (XEXP (operands[1], 0), 1),
b3a13419
ILT		 1773 (!can_create_pseudo_p ()
1774 ? temp
1775 : gen_reg_rtx (Pmode)),
68c37dc9 1776 0, OPTAB_LIB_WIDEN);
1a66cd67
AO		 1777 }
1778 }
1779
e22856e8
JW		 1780 if (! reload_in_progress && ! reload_completed)
1781 {
1782 /* Copy the source to a register if both operands aren't registers. */
1783 if (! register_operand (operands[0], mode)
d9da94a1 1784 && ! sh_register_operand (operands[1], mode))
e22856e8
JW		 1785 operands[1] = copy_to_mode_reg (mode, operands[1]);
1786
f3536097 1787 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
266a2732
R		 1788 {
1789 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1790 except that we can't use that function because it is static. */
0a2aaacc
KG		 1791 rtx new_rtx = change_address (operands[0], mode, 0);
1792 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1793 operands[0] = new_rtx;
266a2732
R		 1794 }
1795
e22856e8
JW		 1796 /* This case can happen while generating code to move the result
1797 of a library call to the target. Reject `st r0,@(rX,rY)' because
1798 reload will fail to find a spill register for rX, since r0 is already
1799 being used for the source. */
73a4d10b
R		 1800 else if (TARGET_SH1
1801 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
f3536097 1802 && MEM_P (operands[0])
e22856e8 1803 && GET_CODE (XEXP (operands[0], 0)) == PLUS
f3536097 1804 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
e22856e8
JW		 1805 operands[1] = copy_to_mode_reg (mode, operands[1]);
1806 }
8aa2a305 1807
463f02cd
KK		 1808 if (mode == Pmode || mode == ptr_mode)
1809 {
6058b2fa 1810 rtx op0, op1, opc;
463f02cd
KK		 1811 enum tls_model tls_kind;
1812
1813 op0 = operands[0];
1814 op1 = operands[1];
6058b2fa
KK		 1815 if (GET_CODE (op1) == CONST
1816 && GET_CODE (XEXP (op1, 0)) == PLUS
81f40b79
ILT		 1817 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1818 != TLS_MODEL_NONE))
6058b2fa
KK		 1819 {
1820 opc = XEXP (XEXP (op1, 0), 1);
1821 op1 = XEXP (XEXP (op1, 0), 0);
1822 }
1823 else
1824 opc = NULL_RTX;
1825
81f40b79 1826 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
463f02cd
KK		 1827 {
1828 rtx tga_op1, tga_ret, tmp, tmp2;
1829
463f02cd
KK		 1830 switch (tls_kind)
1831 {
1832 case TLS_MODEL_GLOBAL_DYNAMIC:
1833 tga_ret = gen_rtx_REG (Pmode, R0_REG);
13ecc9e0 1834 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
463f02cd
KK		 1835 op1 = tga_ret;
1836 break;
1837
1838 case TLS_MODEL_LOCAL_DYNAMIC:
1839 tga_ret = gen_rtx_REG (Pmode, R0_REG);
13ecc9e0 1840 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
463f02cd
KK		 1841
1842 tmp = gen_reg_rtx (Pmode);
1843 emit_move_insn (tmp, tga_ret);
1844
1845 if (register_operand (op0, Pmode))
1846 tmp2 = op0;
1847 else
1848 tmp2 = gen_reg_rtx (Pmode);
1849
1850 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1851 op1 = tmp2;
1852 break;
1853
1854 case TLS_MODEL_INITIAL_EXEC:
1855 if (! flag_pic)
b741fa00 1856 {
b92c3264
KK		 1857 /* Don't schedule insns for getting GOT address when
1858 the first scheduling is enabled, to avoid spill
1859 failures for R0. */
1860 if (flag_schedule_insns)
1861 emit_insn (gen_blockage ());
b741fa00 1862 emit_insn (gen_GOTaddr2picreg ());
c41c1387 1863 emit_use (gen_rtx_REG (SImode, PIC_REG));
b92c3264
KK		 1864 if (flag_schedule_insns)
1865 emit_insn (gen_blockage ());
b741fa00 1866 }
b3a13419 1867 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
463f02cd
KK		 1868 tmp = gen_sym2GOTTPOFF (op1);
1869 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1870 op1 = tga_op1;
1871 break;
1872
1873 case TLS_MODEL_LOCAL_EXEC:
1874 tmp2 = gen_reg_rtx (Pmode);
1875 emit_insn (gen_load_gbr (tmp2));
1876 tmp = gen_reg_rtx (Pmode);
1877 emit_insn (gen_symTPOFF2reg (tmp, op1));
463f02cd
KK		 1878
1879 if (register_operand (op0, Pmode))
1880 op1 = op0;
1881 else
1882 op1 = gen_reg_rtx (Pmode);
1883
1884 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1885 break;
1886
1887 default:
f5b9e7c9 1888 gcc_unreachable ();
463f02cd 1889 }
6058b2fa
KK		 1890 if (opc)
1891 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
463f02cd
KK		 1892 operands[1] = op1;
1893 }
1894 }
1895
8aa2a305
JW		 1896 return 0;
1897}
1898
78d310c2
R		 1899enum rtx_code
1900prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1901 enum rtx_code comparison)
1902{
1903 rtx op1;
1904 rtx scratch = NULL_RTX;
1905
b757d36f 1906 if (comparison == LAST_AND_UNUSED_RTX_CODE)
78d310c2
R		 1907 comparison = GET_CODE (operands[0]);
1908 else
1909 scratch = operands[4];
f3536097
SZ		 1910 if (CONST_INT_P (operands[1])
1911 && !CONST_INT_P (operands[2]))
78d310c2
R		 1912 {
1913 rtx tmp = operands[1];
1914
1915 operands[1] = operands[2];
1916 operands[2] = tmp;
1917 comparison = swap_condition (comparison);
1918 }
f3536097 1919 if (CONST_INT_P (operands[2]))
78d310c2
R		 1920 {
1921 HOST_WIDE_INT val = INTVAL (operands[2]);
1922 if ((val == -1 || val == -0x81)
1923 && (comparison == GT || comparison == LE))
1924 {
1925 comparison = (comparison == GT) ? GE : LT;
1926 operands[2] = gen_int_mode (val + 1, mode);
1927 }
1928 else if ((val == 1 || val == 0x80)
1929 && (comparison == GE || comparison == LT))
1930 {
1931 comparison = (comparison == GE) ? GT : LE;
1932 operands[2] = gen_int_mode (val - 1, mode);
1933 }
1934 else if (val == 1 && (comparison == GEU || comparison == LTU))
1935 {
1936 comparison = (comparison == GEU) ? NE : EQ;
1937 operands[2] = CONST0_RTX (mode);
1938 }
1939 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1940 {
1941 comparison = (comparison == GEU) ? GTU : LEU;
1942 operands[2] = gen_int_mode (val - 1, mode);
1943 }
1944 else if (val == 0 && (comparison == GTU || comparison == LEU))
1945 comparison = (comparison == GTU) ? NE : EQ;
1946 else if (mode == SImode
1947 && ((val == 0x7fffffff
1948 && (comparison == GTU || comparison == LEU))
1949 || ((unsigned HOST_WIDE_INT) val
1950 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1951 && (comparison == GEU || comparison == LTU))))
1952 {
1953 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1954 operands[2] = CONST0_RTX (mode);
1955 }
1956 }
1957 op1 = operands[1];
b3a13419 1958 if (can_create_pseudo_p ())
78d310c2
R		 1959 operands[1] = force_reg (mode, op1);
1960 /* When we are handling DImode comparisons, we want to keep constants so
1961 that we can optimize the component comparisons; however, memory loads
1962 are better issued as a whole so that they can be scheduled well.
1963 SImode equality comparisons allow I08 constants, but only when they
1964 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1965 into a register, that register might as well be r0, and we allow the
1966 constant. If it is already in a register, this is likely to be
2f8e468b 1967 allocated to a different hard register, thus we load the constant into
78d310c2
R		 1968 a register unless it is zero. */
1969 if (!REG_P (operands[2])
f3536097 1970 && (!CONST_INT_P (operands[2])
78d310c2
R		 1971 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1972 && ((comparison != EQ && comparison != NE)
1973 || (REG_P (op1) && REGNO (op1) != R0_REG)
32a7ab3d 1974 || !satisfies_constraint_I08 (operands[2])))))
78d310c2
R		 1975 {
1976 if (scratch && GET_MODE (scratch) == mode)
1977 {
1978 emit_move_insn (scratch, operands[2]);
1979 operands[2] = scratch;
1980 }
b3a13419 1981 else if (can_create_pseudo_p ())
78d310c2
R		 1982 operands[2] = force_reg (mode, operands[2]);
1983 }
1984 return comparison;
1985}
1986
1987void
1988expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1989{
1990 rtx (*branch_expander) (rtx) = gen_branch_true;
1991 rtx jump;
1992
1993 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1994 switch (comparison)
1995 {
1996 case NE: case LT: case LE: case LTU: case LEU:
1997 comparison = reverse_condition (comparison);
1998 branch_expander = gen_branch_false;
1999 default: ;
2000 }
2001 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
2002 gen_rtx_fmt_ee (comparison, SImode,
2003 operands[1], operands[2])));
2004 jump = emit_jump_insn (branch_expander (operands[3]));
2005 if (probability >= 0)
b757d36f 2006 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
78d310c2
R		 2007
2008}
2009
2010/* ??? How should we distribute probabilities when more than one branch
2011 is generated. So far we only have soem ad-hoc observations:
2012 - If the operands are random, they are likely to differ in both parts.
2013 - If comparing items in a hash chain, the operands are random or equal;
2014 operation should be EQ or NE.
2015 - If items are searched in an ordered tree from the root, we can expect
2016 the highpart to be unequal about half of the time; operation should be
2f8e468b 2017 an inequality comparison, operands non-constant, and overall probability
78d310c2
R		 2018 about 50%. Likewise for quicksort.
2019 - Range checks will be often made against constants. Even if we assume for
2020 simplicity an even distribution of the non-constant operand over a
2021 sub-range here, the same probability could be generated with differently
2022 wide sub-ranges - as long as the ratio of the part of the subrange that
2023 is before the threshold to the part that comes after the threshold stays
2024 the same. Thus, we can't really tell anything here;
2025 assuming random distribution is at least simple.
2026 */
2027
2028bool
2029expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
2030{
2031 enum rtx_code msw_taken, msw_skip, lsw_taken;
cb3d3842 2032 rtx skip_label = NULL_RTX;
78d310c2
R		 2033 rtx op1h, op1l, op2h, op2l;
2034 int num_branches;
2035 int prob, rev_prob;
2036 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
6f8eec29 2037 rtx scratch = operands[4];
78d310c2
R		 2038
2039 comparison = prepare_cbranch_operands (operands, DImode, comparison);
2040 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
2041 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
2042 op1l = gen_lowpart (SImode, operands[1]);
2043 op2l = gen_lowpart (SImode, operands[2]);
b757d36f 2044 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
78d310c2
R		 2045 prob = split_branch_probability;
2046 rev_prob = REG_BR_PROB_BASE - prob;
2047 switch (comparison)
2048 {
2049 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
2050 That costs 1 cycle more when the first branch can be predicted taken,
2051 but saves us mispredicts because only one branch needs prediction.
2052 It also enables generating the cmpeqdi_t-1 pattern. */
2053 case EQ:
2054 if (TARGET_CMPEQDI_T)
2055 {
2056 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
2057 emit_jump_insn (gen_branch_true (operands[3]));
2058 return true;
2059 }
2060 msw_skip = NE;
2061 lsw_taken = EQ;
2062 if (prob >= 0)
2063 {
2064 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
2065 */
2066 msw_skip_prob = rev_prob;
2067 if (REG_BR_PROB_BASE <= 65535)
2068 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
2069 else
2070 {
2071 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
2072 lsw_taken_prob
2073 = (prob
2074 ? (REG_BR_PROB_BASE
2075 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
2076 / ((HOST_WIDEST_INT) prob << 32)))
2077 : 0);
2078 }
2079 }
2080 break;
2081 case NE:
2082 if (TARGET_CMPEQDI_T)
2083 {
2084 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
2085 emit_jump_insn (gen_branch_false (operands[3]));
2086 return true;
2087 }
2088 msw_taken = NE;
6f8eec29 2089 msw_taken_prob = prob;
78d310c2
R		 2090 lsw_taken = NE;
2091 lsw_taken_prob = 0;
2092 break;
2093 case GTU: case GT:
2094 msw_taken = comparison;
f3536097 2095 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
78d310c2
R		 2096 break;
2097 if (comparison != GTU || op2h != CONST0_RTX (SImode))
2098 msw_skip = swap_condition (msw_taken);
2099 lsw_taken = GTU;
2100 break;
2101 case GEU: case GE:
2102 if (op2l == CONST0_RTX (SImode))
2103 msw_taken = comparison;
2104 else
2105 {
2106 msw_taken = comparison == GE ? GT : GTU;
2107 msw_skip = swap_condition (msw_taken);
2108 lsw_taken = GEU;
2109 }
2110 break;
2111 case LTU: case LT:
2112 msw_taken = comparison;
2113 if (op2l == CONST0_RTX (SImode))
2114 break;
2115 msw_skip = swap_condition (msw_taken);
2116 lsw_taken = LTU;
2117 break;
2118 case LEU: case LE:
f3536097 2119 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
78d310c2
R		 2120 msw_taken = comparison;
2121 else
2122 {
2123 lsw_taken = LEU;
2124 if (comparison == LE)
2125 msw_taken = LT;
2126 else if (op2h != CONST0_RTX (SImode))
2127 msw_taken = LTU;
2128 else
2129 break;
2130 msw_skip = swap_condition (msw_taken);
2131 }
2132 break;
2133 default: return false;
2134 }
b757d36f
KK		 2135 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
2136 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2137 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
78d310c2
R		 2138 if (comparison != EQ && comparison != NE && num_branches > 1)
2139 {
2140 if (!CONSTANT_P (operands[2])
2141 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
2142 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
2143 {
2144 msw_taken_prob = prob / 2U;
2145 msw_skip_prob
2146 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
2147 lsw_taken_prob = prob;
2148 }
2149 else
2150 {
2151 msw_taken_prob = prob;
2152 msw_skip_prob = REG_BR_PROB_BASE;
2153 /* ??? If we have a constant op2h, should we use that when
2154 calculating lsw_taken_prob? */
2155 lsw_taken_prob = prob;
2156 }
2157 }
2158 operands[1] = op1h;
2159 operands[2] = op2h;
2160 operands[4] = NULL_RTX;
6f8eec29 2161 if (reload_completed
99052692
KK		 2162 && ! arith_reg_or_0_operand (op2h, SImode)
2163 && (true_regnum (op1h) || (comparison != EQ && comparison != NE))
b757d36f
KK		 2164 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
2165 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
6f8eec29
R		 2166 {
2167 emit_move_insn (scratch, operands[2]);
2168 operands[2] = scratch;
2169 }
b757d36f 2170 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
78d310c2 2171 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
b757d36f 2172 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
78d310c2
R		 2173 {
2174 rtx taken_label = operands[3];
2175
d60819f8
CB		 2176 /* Operands were possibly modified, but msw_skip doesn't expect this.
2177 Always use the original ones. */
b757d36f 2178 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
d60819f8
CB		 2179 {
2180 operands[1] = op1h;
2181 operands[2] = op2h;
2182 }
2183
78d310c2
R		 2184 operands[3] = skip_label = gen_label_rtx ();
2185 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
2186 operands[3] = taken_label;
2187 }
2188 operands[1] = op1l;
2189 operands[2] = op2l;
b757d36f 2190 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
6f8eec29
R		 2191 {
2192 if (reload_completed
99052692
KK		 2193 && ! arith_reg_or_0_operand (op2l, SImode)
2194 && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE)))
2195 {
2196 emit_move_insn (scratch, operands[2]);
2197 operands[2] = scratch;
2198 }
6f8eec29
R		 2199 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
2200 }
b757d36f 2201 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
78d310c2
R		 2202 emit_label (skip_label);
2203 return true;
2204}
2205
f90b7a5a
PB		 2206/* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
2207
2208static void
2209sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
2210{
2211 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
2212 {
2213 insn = gen_rtx_PARALLEL (VOIDmode,
2214 gen_rtvec (2, insn,
2215 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
2216 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
2217 }
2218 else
2219 emit_insn (insn);
2220}
2221
8aa2a305 2222/* Prepare the operands for an scc instruction; make sure that the
f90b7a5a
PB		 2223 compare has been done and the result is in T_REG. */
2224void
2225sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
8aa2a305 2226{
c5c76735 2227 rtx t_reg = gen_rtx_REG (SImode, T_REG);
8aa2a305 2228 enum rtx_code oldcode = code;
9374bd85 2229 enum machine_mode mode;
8aa2a305
JW		 2230
2231 /* First need a compare insn. */
2232 switch (code)
bc45ade3 2233 {
8aa2a305
JW		 2234 case NE:
2235 /* It isn't possible to handle this case. */
f5b9e7c9 2236 gcc_unreachable ();
8aa2a305
JW		 2237 case LT:
2238 code = GT;
2239 break;
2240 case LE:
2241 code = GE;
2242 break;
2243 case LTU:
2244 code = GTU;
2245 break;
2246 case LEU:
2247 code = GEU;
2248 break;
10db12e0
R		 2249 default:
2250 break;
bc45ade3 2251 }
8aa2a305 2252 if (code != oldcode)
b9654711 2253 {
f90b7a5a
PB		 2254 rtx tmp = op0;
2255 op0 = op1;
2256 op1 = tmp;
0d7e008e 2257 }
b9654711 2258
f90b7a5a 2259 mode = GET_MODE (op0);
9374bd85 2260 if (mode == VOIDmode)
f90b7a5a 2261 mode = GET_MODE (op1);
9374bd85 2262
f90b7a5a 2263 op0 = force_reg (mode, op0);
1245df60 2264 if ((code != EQ && code != NE
f90b7a5a 2265 && (op1 != const0_rtx
1245df60 2266 || code == GTU || code == GEU || code == LTU || code == LEU))
f90b7a5a 2267 || (mode == DImode && op1 != const0_rtx)
3a8699c7 2268 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
f90b7a5a 2269 op1 = force_reg (mode, op1);
0d7e008e 2270
f90b7a5a
PB		 2271 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode, t_reg,
2272 gen_rtx_fmt_ee (code, SImode, op0, op1)),
2273 mode);
2274}
0d7e008e 2275
f90b7a5a
PB		 2276rtx
2277sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
2278 rtx op0, rtx op1)
2279{
2280 rtx target = gen_reg_rtx (SImode);
2281 rtx tmp;
2282
2283 gcc_assert (TARGET_SHMEDIA);
2284 switch (code)
2285 {
2286 case EQ:
2287 case GT:
2288 case LT:
2289 case UNORDERED:
2290 case GTU:
2291 case LTU:
2292 tmp = gen_rtx_fmt_ee (code, SImode, op0, op1);
2293 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2294 code = NE;
2295 break;
2296
2297 case NE:
2298 case GE:
2299 case LE:
2300 case ORDERED:
2301 case GEU:
2302 case LEU:
2303 tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1);
2304 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2305 code = EQ;
2306 break;
2307
2308 case UNEQ:
2309 case UNGE:
2310 case UNGT:
2311 case UNLE:
2312 case UNLT:
2313 case LTGT:
2314 return NULL_RTX;
2315
2316 default:
2317 gcc_unreachable ();
2318 }
2319
2320 if (mode == DImode)
2321 {
2322 rtx t2 = gen_reg_rtx (DImode);
2323 emit_insn (gen_extendsidi2 (t2, target));
2324 target = t2;
2325 }
2326
2327 return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx);
bc45ade3
SC		 2328}
2329
8aa2a305
JW		 2330/* Called from the md file, set up the operands of a compare instruction. */
2331
2332void
f90b7a5a 2333sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
bc45ade3 2334{
f90b7a5a
PB		 2335 enum rtx_code code = GET_CODE (operands[0]);
2336 enum rtx_code branch_code;
2337 rtx op0 = operands[1];
2338 rtx op1 = operands[2];
2339 rtx insn, tem;
2340 bool need_ccmpeq = false;
2341
2342 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
bc45ade3 2343 {
f90b7a5a
PB		 2344 op0 = force_reg (mode, op0);
2345 op1 = force_reg (mode, op1);
bc45ade3 2346 }
f90b7a5a 2347 else
1245df60 2348 {
f90b7a5a
PB		 2349 if (code != EQ || mode == DImode)
2350 {
2351 /* Force args into regs, since we can't use constants here. */
2352 op0 = force_reg (mode, op0);
2353 if (op1 != const0_rtx || code == GTU || code == GEU)
2354 op1 = force_reg (mode, op1);
2355 }
1245df60 2356 }
f90b7a5a
PB		 2357
2358 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2359 {
2360 if (code == LT
2361 || (code == LE && TARGET_IEEE && TARGET_SH2E)
2362 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
2363 {
2364 tem = op0, op0 = op1, op1 = tem;
2365 code = swap_condition (code);
2366 }
2367
2368 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2369 if (code == GE)
2370 {
2371 gcc_assert (TARGET_IEEE && TARGET_SH2E);
2372 need_ccmpeq = true;
2373 code = GT;
2374 }
2375
2376 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2377 to EQ/GT respectively. */
2378 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
2379 }
2380
2381 switch (code)
2382 {
2383 case EQ:
2384 case GT:
2385 case GE:
2386 case GTU:
2387 case GEU:
2388 branch_code = code;
2389 break;
2390 case NE:
2391 case LT:
2392 case LE:
2393 case LTU:
2394 case LEU:
2395 branch_code = reverse_condition (code);
2396 break;
2397 default:
2398 gcc_unreachable ();
2399 }
2400
2401 insn = gen_rtx_SET (VOIDmode,
2402 gen_rtx_REG (SImode, T_REG),
2403 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
2404
2405 sh_emit_set_t_insn (insn, mode);
2406 if (need_ccmpeq)
2407 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
2408
2409 if (branch_code == code)
2410 emit_jump_insn (gen_branch_true (operands[3]));
1245df60 2411 else
f90b7a5a
PB		 2412 emit_jump_insn (gen_branch_false (operands[3]));
2413}
2414
2415void
2416sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
2417{
2418 enum rtx_code code = GET_CODE (operands[1]);
2419 rtx op0 = operands[2];
2420 rtx op1 = operands[3];
2421 rtx lab = NULL_RTX;
2422 bool invert = false;
2423 rtx tem;
2424
2425 op0 = force_reg (mode, op0);
2426 if ((code != EQ && code != NE
2427 && (op1 != const0_rtx
2428 || code == GTU || code == GEU || code == LTU || code == LEU))
2429 || (mode == DImode && op1 != const0_rtx)
2430 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2431 op1 = force_reg (mode, op1);
2432
2433 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
225e4f43 2434 {
f90b7a5a
PB		 2435 if (code == LT || code == LE)
2436 {
2437 code = swap_condition (code);
2438 tem = op0, op0 = op1, op1 = tem;
2439 }
2440 if (code == GE)
2441 {
2442 if (TARGET_IEEE)
2443 {
2444 lab = gen_label_rtx ();
2445 sh_emit_scc_to_t (EQ, op0, op1);
2446 emit_jump_insn (gen_branch_true (lab));
2447 code = GT;
2448 }
2449 else
2450 {
2451 code = LT;
2452 invert = true;
2453 }
2454 }
225e4f43 2455 }
f90b7a5a
PB		 2456
2457 if (code == NE)
2458 {
2459 code = EQ;
2460 invert = true;
2461 }
2462
2463 sh_emit_scc_to_t (code, op0, op1);
2464 if (lab)
2465 emit_label (lab);
2466 if (invert)
2467 emit_insn (gen_movnegt (operands[0]));
225e4f43 2468 else
f90b7a5a 2469 emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
bc45ade3
SC		 2470}
2471\f
16bea517 2472/* Functions to output assembly code. */
bc45ade3 2473
b9654711 2474/* Return a sequence of instructions to perform DI or DF move.
bc45ade3 2475
b9654711 2476 Since the SH cannot move a DI or DF in one instruction, we have
16bea517 2477 to take care when we see overlapping source and dest registers. */
0d7e008e 2478
318881c0 2479const char *
cf277499
SB		 2480output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
2481 enum machine_mode mode)
bc45ade3 2482{
b9654711
SC		 2483 rtx dst = operands[0];
2484 rtx src = operands[1];
b9654711 2485
f3536097 2486 if (MEM_P (dst)
16bea517 2487 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
8aa2a305
JW		 2488 return "mov.l %T1,%0\n\tmov.l %1,%0";
2489
b9654711
SC		 2490 if (register_operand (dst, mode)
2491 && register_operand (src, mode))
bc45ade3 2492 {
b9654711 2493 if (REGNO (src) == MACH_REG)
00f8ff66 2494 return "sts mach,%S0\n\tsts macl,%R0";
bc45ade3 2495
8aa2a305
JW		 2496 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2497 when mov.d r1,r0 do r1->r0 then r2->r1. */
b9654711
SC		 2498
2499 if (REGNO (src) + 1 == REGNO (dst))
5325c0fa 2500 return "mov %T1,%T0\n\tmov %1,%0";
b9654711 2501 else
5325c0fa 2502 return "mov %1,%0\n\tmov %T1,%T0";
b9654711 2503 }
f3536097 2504 else if (CONST_INT_P (src))
bc45ade3 2505 {
8aa2a305
JW		 2506 if (INTVAL (src) < 0)
2507 output_asm_insn ("mov #-1,%S0", operands);
bc45ade3 2508 else
8aa2a305 2509 output_asm_insn ("mov #0,%S0", operands);
bc45ade3 2510
8aa2a305 2511 return "mov %1,%R0";
0d7e008e 2512 }
f3536097 2513 else if (MEM_P (src))
bc45ade3 2514 {
8aa2a305 2515 int ptrreg = -1;
b9654711
SC		 2516 int dreg = REGNO (dst);
2517 rtx inside = XEXP (src, 0);
bc45ade3 2518
f5b9e7c9 2519 switch (GET_CODE (inside))
bc45ade3 2520 {
f5b9e7c9
NS		 2521 case REG:
2522 ptrreg = REGNO (inside);
2523 break;
2524
2525 case SUBREG:
2526 ptrreg = subreg_regno (inside);
2527 break;
2528
2529 case PLUS:
8aa2a305
JW		 2530 ptrreg = REGNO (XEXP (inside, 0));
2531 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2532 an offsettable address. Unfortunately, offsettable addresses use
2533 QImode to check the offset, and a QImode offsettable address
2534 requires r0 for the other operand, which is not currently
2535 supported, so we can't use the 'o' constraint.
2536 Thus we must check for and handle r0+REG addresses here.
2537 We punt for now, since this is likely very rare. */
f3536097 2538 gcc_assert (!REG_P (XEXP (inside, 1)));
f5b9e7c9
NS		 2539 break;
2540
2541 case LABEL_REF:
2542 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2543 case POST_INC:
2544 return "mov.l %1,%0\n\tmov.l %1,%T0";
2545 default:
2546 gcc_unreachable ();
bc45ade3 2547 }
bc45ade3 2548
8aa2a305
JW		 2549 /* Work out the safe way to copy. Copy into the second half first. */
2550 if (dreg == ptrreg)
2551 return "mov.l %T1,%T0\n\tmov.l %1,%0";
bc45ade3
SC		 2552 }
2553
00f8ff66 2554 return "mov.l %1,%0\n\tmov.l %T1,%T0";
bc45ade3
SC		 2555}
2556
8aa2a305
JW		 2557/* Print an instruction which would have gone into a delay slot after
2558 another instruction, but couldn't because the other instruction expanded
2559 into a sequence where putting the slot insn at the end wouldn't work. */
0d7e008e 2560
8aa2a305 2561static void
cf277499 2562print_slot (rtx insn)
8aa2a305 2563{
c9d691e9 2564 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
b9654711 2565
8aa2a305
JW		 2566 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
2567}
0d7e008e 2568
318881c0 2569const char *
cf277499 2570output_far_jump (rtx insn, rtx op)
0d7e008e 2571{
0a2aaacc 2572 struct { rtx lab, reg, op; } this_jmp;
950a3816 2573 rtx braf_base_lab = NULL_RTX;
318881c0 2574 const char *jump;
1245df60 2575 int far;
9d98a694 2576 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
10f4f635 2577 rtx prev;
0d7e008e 2578
0a2aaacc 2579 this_jmp.lab = gen_label_rtx ();
b9654711 2580
1a953d0f
R		 2581 if (TARGET_SH2
2582 && offset >= -32764
2583 && offset - get_attr_length (insn) <= 32766)
1245df60
R		 2584 {
2585 far = 0;
e6dfd05f 2586 jump = "mov.w %O0,%1; braf %1";
1245df60
R		 2587 }
2588 else
2589 {
2590 far = 1;
1a66cd67 2591 if (flag_pic)
e6dfd05f
AO		 2592 {
2593 if (TARGET_SH2)
2594 jump = "mov.l %O0,%1; braf %1";
2595 else
2596 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2597 }
1a66cd67 2598 else
e6dfd05f 2599 jump = "mov.l %O0,%1; jmp @%1";
1245df60
R		 2600 }
2601 /* If we have a scratch register available, use it. */
f3536097 2602 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
10f4f635 2603 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
1245df60 2604 {
0a2aaacc
KG		 2605 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2606 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
e6dfd05f 2607 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
0a2aaacc 2608 output_asm_insn (jump, &this_jmp.lab);
1245df60
R		 2609 if (dbr_sequence_length ())
2610 print_slot (final_sequence);
2611 else
2612 output_asm_insn ("nop", 0);
2613 }
2614 else
2615 {
2616 /* Output the delay slot insn first if any. */
2617 if (dbr_sequence_length ())
2618 print_slot (final_sequence);
2619
0a2aaacc 2620 this_jmp.reg = gen_rtx_REG (SImode, 13);
fa5322fa
AO		 2621 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2622 Fortunately, MACL is fixed and call-clobbered, and we never
2623 need its value across jumps, so save r13 in it instead of in
2624 the stack. */
2625 if (TARGET_SH5)
2626 output_asm_insn ("lds r13, macl", 0);
2627 else
2628 output_asm_insn ("mov.l r13,@-r15", 0);
0a2aaacc 2629 output_asm_insn (jump, &this_jmp.lab);
fa5322fa
AO		 2630 if (TARGET_SH5)
2631 output_asm_insn ("sts macl, r13", 0);
2632 else
2633 output_asm_insn ("mov.l @r15+,r13", 0);
1245df60 2634 }
e6dfd05f
AO		 2635 if (far && flag_pic && TARGET_SH2)
2636 {
2637 braf_base_lab = gen_label_rtx ();
4977bab6 2638 (*targetm.asm_out.internal_label) (asm_out_file, "L",
e6dfd05f
AO		 2639 CODE_LABEL_NUMBER (braf_base_lab));
2640 }
1245df60
R		 2641 if (far)
2642 output_asm_insn (".align 2", 0);
0a2aaacc
KG		 2643 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2644 this_jmp.op = op;
1a66cd67 2645 if (far && flag_pic)
e6dfd05f
AO		 2646 {
2647 if (TARGET_SH2)
0a2aaacc
KG		 2648 this_jmp.lab = braf_base_lab;
2649 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
e6dfd05f 2650 }
1a66cd67 2651 else
0a2aaacc 2652 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
0d7e008e
SC		 2653 return "";
2654}
bc45ade3 2655
8aa2a305
JW		 2656/* Local label counter, used for constants in the pool and inside
2657 pattern branches. */
2658
2659static int lf = 100;
2660
2661/* Output code for ordinary branches. */
2662
318881c0 2663const char *
cf277499 2664output_branch (int logic, rtx insn, rtx *operands)
bc45ade3 2665{
afbc5d86 2666 switch (get_attr_length (insn))
bc45ade3 2667 {
33f7f353
JR		 2668 case 6:
2669 /* This can happen if filling the delay slot has caused a forward
2670 branch to exceed its range (we could reverse it, but only
2671 when we know we won't overextend other branches; this should
2672 best be handled by relaxation).
2673 It can also happen when other condbranches hoist delay slot insn
1245df60
R		 2674 from their destination, thus leading to code size increase.
2675 But the branch will still be in the range -4092..+4098 bytes. */
bc45ade3 2676
33f7f353 2677 if (! TARGET_RELAX)
1245df60 2678 {
33f7f353
JR		 2679 int label = lf++;
2680 /* The call to print_slot will clobber the operands. */
2681 rtx op0 = operands[0];
f676971a 2682
33f7f353
JR		 2683 /* If the instruction in the delay slot is annulled (true), then
2684 there is no delay slot where we can put it now. The only safe
2685 place for it is after the label. final will do that by default. */
f676971a 2686
33f7f353 2687 if (final_sequence
bee9efbc
KK		 2688 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2689 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
33f7f353 2690 {
afbc5d86 2691 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
33f7f353
JR		 2692 ASSEMBLER_DIALECT ? "/" : ".", label);
2693 print_slot (final_sequence);
2694 }
2695 else
afbc5d86 2696 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
f676971a 2697
afbc5d86
R		 2698 output_asm_insn ("bra\t%l0", &op0);
2699 fprintf (asm_out_file, "\tnop\n");
832a3292 2700 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
f676971a 2701
33f7f353 2702 return "";
1245df60 2703 }
33f7f353
JR		 2704 /* When relaxing, handle this like a short branch. The linker
2705 will fix it up if it still doesn't fit after relaxation. */
2706 case 2:
2707 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
3a8699c7
AO		 2708
2709 /* These are for SH2e, in which we have to account for the
2710 extra nop because of the hardware bug in annulled branches. */
2711 case 8:
2712 if (! TARGET_RELAX)
2713 {
2714 int label = lf++;
2715
f5b9e7c9
NS		 2716 gcc_assert (!final_sequence
2717 || !(INSN_ANNULLED_BRANCH_P
2718 (XVECEXP (final_sequence, 0, 0))));
3a8699c7
AO		 2719 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2720 logic ? "f" : "t",
2721 ASSEMBLER_DIALECT ? "/" : ".", label);
2722 fprintf (asm_out_file, "\tnop\n");
2723 output_asm_insn ("bra\t%l0", operands);
2724 fprintf (asm_out_file, "\tnop\n");
2725 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2726
2727 return "";
2728 }
2729 /* When relaxing, fall through. */
2730 case 4:
2731 {
2732 char buffer[10];
f676971a 2733
3a8699c7
AO		 2734 sprintf (buffer, "b%s%ss\t%%l0",
2735 logic ? "t" : "f",
2736 ASSEMBLER_DIALECT ? "/" : ".");
2737 output_asm_insn (buffer, &operands[0]);
2738 return "nop";
2739 }
2740
33f7f353 2741 default:
afbc5d86
R		 2742 /* There should be no longer branches now - that would
2743 indicate that something has destroyed the branches set
2744 up in machine_dependent_reorg. */
f5b9e7c9 2745 gcc_unreachable ();
1245df60 2746 }
1245df60 2747}
bc45ade3 2748
0a2aaacc 2749/* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
78d310c2
R		 2750 fill in operands 9 as a label to the successor insn.
2751 We try to use jump threading where possible.
2752 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2753 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2754 follow jmp and bt, if the address is in range. */
318881c0 2755const char *
0a2aaacc 2756output_branchy_insn (enum rtx_code code, const char *templ,
cf277499 2757 rtx insn, rtx *operands)
1245df60
R		 2758{
2759 rtx next_insn = NEXT_INSN (insn);
79b2746a 2760
f3536097 2761 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
1245df60
R		 2762 {
2763 rtx src = SET_SRC (PATTERN (next_insn));
2764 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2765 {
2766 /* Following branch not taken */
2767 operands[9] = gen_label_rtx ();
2768 emit_label_after (operands[9], next_insn);
9d98a694
AO		 2769 INSN_ADDRESSES_NEW (operands[9],
2770 INSN_ADDRESSES (INSN_UID (next_insn))
2771 + get_attr_length (next_insn));
0a2aaacc 2772 return templ;
1245df60
R		 2773 }
2774 else
2775 {
33f7f353 2776 int offset = (branch_dest (next_insn)
9d98a694 2777 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
33f7f353 2778 if (offset >= -252 && offset <= 258)
1245df60
R		 2779 {
2780 if (GET_CODE (src) == IF_THEN_ELSE)
2781 /* branch_true */
2782 src = XEXP (src, 1);
2783 operands[9] = src;
0a2aaacc 2784 return templ;
1245df60
R		 2785 }
2786 }
bc45ade3 2787 }
1245df60
R		 2788 operands[9] = gen_label_rtx ();
2789 emit_label_after (operands[9], insn);
9d98a694
AO		 2790 INSN_ADDRESSES_NEW (operands[9],
2791 INSN_ADDRESSES (INSN_UID (insn))
2792 + get_attr_length (insn));
0a2aaacc 2793 return templ;
1245df60 2794}
e4fa6b06 2795
318881c0 2796const char *
cf277499 2797output_ieee_ccmpeq (rtx insn, rtx *operands)
1245df60 2798{
9fd0c419
R		 2799 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2800 insn, operands);
bc45ade3 2801}
8e87e161 2802\f
1bc7c5b6 2803/* Output the start of the assembler file. */
8aa2a305 2804
1bc7c5b6 2805static void
cf277499 2806sh_file_start (void)
bc45ade3 2807{
1bc7c5b6
ZW		 2808 default_file_start ();
2809
2810 if (TARGET_ELF)
2811 /* We need to show the text section with the proper
2812 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
0fe7abcc 2813 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
1bc7c5b6
ZW		 2814 will complain. We can teach GAS specifically about the
2815 default attributes for our choice of text section, but
2816 then we would have to change GAS again if/when we change
2817 the text section name. */
2818 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2819 else
2820 /* Switch to the data section so that the coffsem symbol
2821 isn't in the text section. */
d6b5193b 2822 switch_to_section (data_section);
b9654711 2823
8aa2a305 2824 if (TARGET_LITTLE_ENDIAN)
1bc7c5b6 2825 fputs ("\t.little\n", asm_out_file);
fa5322fa 2826
1bc7c5b6
ZW		 2827 if (!TARGET_ELF)
2828 {
2829 if (TARGET_SHCOMPACT)
2830 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2831 else if (TARGET_SHMEDIA)
2832 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2833 TARGET_SHMEDIA64 ? 64 : 32);
2834 }
bc45ade3 2835}
0d7e008e 2836\f
9f3a9a08
KK		 2837/* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2838
2839static bool
cf277499 2840unspec_caller_rtx_p (rtx pat)
9f3a9a08 2841{
dc3ba671
RS		 2842 rtx base, offset;
2843 int i;
2844
2845 split_const (pat, &base, &offset);
2846 if (GET_CODE (base) == UNSPEC)
9f3a9a08 2847 {
dc3ba671 2848 if (XINT (base, 1) == UNSPEC_CALLER)
9f3a9a08 2849 return true;
dc3ba671
RS		 2850 for (i = 0; i < XVECLEN (base, 0); i++)
2851 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2852 return true;
9f3a9a08 2853 }
9f3a9a08
KK		 2854 return false;
2855}
2856
2857/* Indicate that INSN cannot be duplicated. This is true for insn
569b7f6a 2858 that generates a unique label. */
9f3a9a08
KK		 2859
2860static bool
cf277499 2861sh_cannot_copy_insn_p (rtx insn)
9f3a9a08
KK		 2862{
2863 rtx pat;
2864
2865 if (!reload_completed || !flag_pic)
2866 return false;
2867
f3536097 2868 if (!NONJUMP_INSN_P (insn))
9f3a9a08
KK		 2869 return false;
2870 if (asm_noperands (insn) >= 0)
2871 return false;
2872
2873 pat = PATTERN (insn);
2874 if (GET_CODE (pat) != SET)
2875 return false;
2876 pat = SET_SRC (pat);
2877
2878 if (unspec_caller_rtx_p (pat))
2879 return true;
2880
2881 return false;
2882}
2883\f
16bea517 2884/* Actual number of instructions used to make a shift by N. */
0b5826ac 2885static const char ashiftrt_insns[] =
16bea517
JW		 2886 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2887
2888/* Left shift and logical right shift are the same. */
0b5826ac 2889static const char shift_insns[] =
16bea517 2890 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
8aa2a305 2891
16bea517
JW		 2892/* Individual shift amounts needed to get the above length sequences.
2893 One bit right shifts clobber the T bit, so when possible, put one bit
2894 shifts in the middle of the sequence, so the ends are eligible for
2895 branch delay slots. */
0139adca 2896static const short shift_amounts[32][5] = {
16bea517
JW		 2897 {0}, {1}, {2}, {2, 1},
2898 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2899 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2900 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2901 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2902 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2903 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1d3534c0 2904 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
16bea517 2905
8d481241
JW		 2906/* Likewise, but for shift amounts < 16, up to three highmost bits
2907 might be clobbered. This is typically used when combined with some
2908 kind of sign or zero extension. */
f676971a 2909
0b5826ac 2910static const char ext_shift_insns[] =
8d481241
JW		 2911 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2912
0b5826ac 2913static const short ext_shift_amounts[32][4] = {
8d481241
JW		 2914 {0}, {1}, {2}, {2, 1},
2915 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2916 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2917 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2918 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2919 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2920 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2921 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2922
ae9d19c0
JR		 2923/* Assuming we have a value that has been sign-extended by at least one bit,
2924 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2925 to shift it by N without data loss, and quicker than by other means? */
2926#define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2927
16bea517
JW		 2928/* This is used in length attributes in sh.md to help compute the length
2929 of arbitrary constant shift instructions. */
bc45ade3 2930
16bea517 2931int
cf277499 2932shift_insns_rtx (rtx insn)
16bea517
JW		 2933{
2934 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
6c34a092 2935 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
16bea517 2936 enum rtx_code shift_code = GET_CODE (set_src);
00f8ff66 2937
16bea517
JW		 2938 switch (shift_code)
2939 {
2940 case ASHIFTRT:
2941 return ashiftrt_insns[shift_count];
2942 case LSHIFTRT:
2943 case ASHIFT:
2944 return shift_insns[shift_count];
2945 default:
f5b9e7c9 2946 gcc_unreachable ();
16bea517
JW		 2947 }
2948}
2949
16bea517 2950/* Return the cost of a shift. */
bc45ade3 2951
3c50106f 2952static inline int
cf277499 2953shiftcosts (rtx x)
bc45ade3 2954{
3d422cb1 2955 int value;
8aa2a305 2956
fa5322fa
AO		 2957 if (TARGET_SHMEDIA)
2958 return 1;
2959
c762ab6e
R		 2960 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2961 {
2962 if (GET_MODE (x) == DImode
f3536097 2963 && CONST_INT_P (XEXP (x, 1))
c762ab6e
R		 2964 && INTVAL (XEXP (x, 1)) == 1)
2965 return 2;
2966
2967 /* Everything else is invalid, because there is no pattern for it. */
cb2eb96f 2968 return MAX_COST;
c762ab6e 2969 }
16bea517 2970 /* If shift by a non constant, then this will be expensive. */
f3536097 2971 if (!CONST_INT_P (XEXP (x, 1)))
1245df60 2972 return SH_DYNAMIC_SHIFT_COST;
bc45ade3 2973
6c34a092
PB		 2974 /* Otherwise, return the true cost in instructions. Cope with out of range
2975 shift counts more or less arbitrarily. */
2976 value = INTVAL (XEXP (x, 1)) & 31;
3d422cb1 2977
8aa2a305 2978 if (GET_CODE (x) == ASHIFTRT)
49b6d06b
JW		 2979 {
2980 int cost = ashiftrt_insns[value];
2981 /* If SH3, then we put the constant in a reg and use shad. */
1245df60
R		 2982 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2983 cost = 1 + SH_DYNAMIC_SHIFT_COST;
49b6d06b
JW		 2984 return cost;
2985 }
8aa2a305
JW		 2986 else
2987 return shift_insns[value];
0d7e008e 2988}
b9654711 2989
8aa2a305
JW		 2990/* Return the cost of an AND operation. */
2991
3c50106f 2992static inline int
cf277499 2993andcosts (rtx x)
0d7e008e
SC		 2994{
2995 int i;
8aa2a305 2996
a6f71af5 2997 /* Anding with a register is a single cycle and instruction. */
f3536097 2998 if (!CONST_INT_P (XEXP (x, 1)))
a6f71af5 2999 return 1;
8aa2a305
JW		 3000
3001 i = INTVAL (XEXP (x, 1));
fa5322fa
AO		 3002
3003 if (TARGET_SHMEDIA)
3004 {
32a7ab3d
KK		 3005 if (satisfies_constraint_I10 (XEXP (x, 1))
3006 || satisfies_constraint_J16 (XEXP (x, 1)))
fa5322fa
AO		 3007 return 1;
3008 else
f40751dd 3009 return 1 + rtx_cost (XEXP (x, 1), AND, !optimize_size);
fa5322fa
AO		 3010 }
3011
a6f71af5 3012 /* These constants are single cycle extu.[bw] instructions. */
0d7e008e 3013 if (i == 0xff || i == 0xffff)
a6f71af5 3014 return 1;
735cb76e 3015 /* Constants that can be used in an and immediate instruction in a single
a6f71af5 3016 cycle, but this requires r0, so make it a little more expensive. */
735cb76e 3017 if (CONST_OK_FOR_K08 (i))
0d7e008e 3018 return 2;
a6f71af5
JW		 3019 /* Constants that can be loaded with a mov immediate and an and.
3020 This case is probably unnecessary. */
735cb76e 3021 if (CONST_OK_FOR_I08 (i))
a6f71af5
JW		 3022 return 2;
3023 /* Any other constants requires a 2 cycle pc-relative load plus an and.
3024 This case is probably unnecessary. */
3025 return 3;
0d7e008e 3026}
d3ae8277 3027
630c79be
BS		 3028/* Return the cost of an addition or a subtraction. */
3029
3c50106f 3030static inline int
cf277499 3031addsubcosts (rtx x)
630c79be
BS		 3032{
3033 /* Adding a register is a single cycle insn. */
f3536097 3034 if (REG_P (XEXP (x, 1))
50ceefc2 3035 || GET_CODE (XEXP (x, 1)) == SUBREG)
630c79be
BS		 3036 return 1;
3037
3038 /* Likewise for small constants. */
f3536097 3039 if (CONST_INT_P (XEXP (x, 1))
fa5322fa 3040 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
630c79be
BS		 3041 return 1;
3042
fa5322fa
AO		 3043 if (TARGET_SHMEDIA)
3044 switch (GET_CODE (XEXP (x, 1)))
3045 {
3046 case CONST:
3047 case LABEL_REF:
3048 case SYMBOL_REF:
3049 return TARGET_SHMEDIA64 ? 5 : 3;
3050
3051 case CONST_INT:
735cb76e 3052 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
fa5322fa 3053 return 2;
735cb76e 3054 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
fa5322fa 3055 return 3;
735cb76e 3056 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
fa5322fa
AO		 3057 return 4;
3058
3059 /* Fall through. */
3060 default:
832a3292 3061 return 5;
fa5322fa
AO		 3062 }
3063
630c79be
BS		 3064 /* Any other constant requires a 2 cycle pc-relative load plus an
3065 addition. */
3066 return 3;
3067}
3068
16bea517 3069/* Return the cost of a multiply. */
3c50106f 3070static inline int
cf277499 3071multcosts (rtx x ATTRIBUTE_UNUSED)
0d7e008e 3072{
7dd2f19b
RS		 3073 if (sh_multcost >= 0)
3074 return sh_multcost;
fa5322fa 3075 if (TARGET_SHMEDIA)
73a4d10b
R		 3076 /* ??? We have a mul insn, but it has a latency of three, and doesn't
3077 accept constants. Ideally, we would use a cost of one or two and
3078 add the cost of the operand, but disregard the latter when inside loops
3079 and loop invariant code motion is still to follow.
3080 Using a multiply first and splitting it later if it's a loss
3081 doesn't work because of different sign / zero extension semantics
3082 of multiplies vs. shifts. */
3020190e 3083 return optimize_size ? 2 : 3;
fa5322fa 3084
0d7e008e 3085 if (TARGET_SH2)
d3ae8277
SC		 3086 {
3087 /* We have a mul insn, so we can never take more than the mul and the
a7771f78 3088 read of the mac reg, but count more because of the latency and extra
16bea517 3089 reg usage. */
3020190e 3090 if (optimize_size)
8e87e161 3091 return 2;
a7771f78 3092 return 3;
d3ae8277
SC		 3093 }
3094
a7771f78 3095 /* If we're aiming at small code, then just count the number of
16bea517 3096 insns in a multiply call sequence. */
3020190e 3097 if (optimize_size)
8aa2a305 3098 return 5;
d3ae8277 3099
16bea517 3100 /* Otherwise count all the insns in the routine we'd be calling too. */
d3ae8277 3101 return 20;
0d7e008e 3102}
b9654711 3103
3c50106f
RH		 3104/* Compute a (partial) cost for rtx X. Return true if the complete
3105 cost has been computed, and false if subexpressions should be
3106 scanned. In either case, *TOTAL contains the cost result. */
3107
3108static bool
f40751dd
JH		 3109sh_rtx_costs (rtx x, int code, int outer_code, int *total,
3110 bool speed ATTRIBUTE_UNUSED)
3c50106f
RH		 3111{
3112 switch (code)
3113 {
3114 case CONST_INT:
3115 if (TARGET_SHMEDIA)
3116 {
3117 if (INTVAL (x) == 0)
3118 *total = 0;
3119 else if (outer_code == AND && and_operand ((x), DImode))
3120 *total = 0;
3121 else if ((outer_code == IOR || outer_code == XOR
3122 || outer_code == PLUS)
735cb76e 3123 && CONST_OK_FOR_I10 (INTVAL (x)))
3c50106f 3124 *total = 0;
735cb76e 3125 else if (CONST_OK_FOR_I16 (INTVAL (x)))
3c50106f 3126 *total = COSTS_N_INSNS (outer_code != SET);
735cb76e 3127 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
73a4d10b 3128 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
735cb76e 3129 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
42201282 3130 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
3c50106f 3131 else
42201282 3132 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
3c50106f
RH		 3133 return true;
3134 }
735cb76e 3135 if (CONST_OK_FOR_I08 (INTVAL (x)))
3c50106f
RH		 3136 *total = 0;
3137 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
735cb76e 3138 && CONST_OK_FOR_K08 (INTVAL (x)))
3c50106f 3139 *total = 1;
78d310c2 3140 /* prepare_cmp_insn will force costly constants int registers before
35912544 3141 the cbranch[sd]i4 patterns can see them, so preserve potentially
78d310c2
R		 3142 interesting ones not covered by I08 above. */
3143 else if (outer_code == COMPARE
3144 && ((unsigned HOST_WIDE_INT) INTVAL (x)
3145 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
3146 || INTVAL (x) == 0x7fffffff
3147 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
3148 *total = 1;
3c50106f
RH		 3149 else
3150 *total = 8;
3151 return true;
3152
3153 case CONST:
3154 case LABEL_REF:
3155 case SYMBOL_REF:
3156 if (TARGET_SHMEDIA64)
3157 *total = COSTS_N_INSNS (4);
3158 else if (TARGET_SHMEDIA32)
3159 *total = COSTS_N_INSNS (2);
3160 else
3161 *total = 5;
3162 return true;
3163
3164 case CONST_DOUBLE:
3165 if (TARGET_SHMEDIA)
3166 *total = COSTS_N_INSNS (4);
78d310c2 3167 /* prepare_cmp_insn will force costly constants int registers before
35912544 3168 the cbranchdi4 pattern can see them, so preserve potentially
78d310c2
R		 3169 interesting ones. */
3170 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
3171 *total = 1;
3c50106f
RH		 3172 else
3173 *total = 10;
3174 return true;
73a4d10b
R		 3175 case CONST_VECTOR:
3176 if (x == CONST0_RTX (GET_MODE (x)))
3177 *total = 0;
3178 else if (sh_1el_vec (x, VOIDmode))
3179 *total = outer_code != SET;
3180 if (sh_rep_vec (x, VOIDmode))
3181 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3182 + (outer_code != SET));
3183 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3184 return true;
3c50106f
RH		 3185
3186 case PLUS:
73a4d10b 3187 case MINUS:
3c50106f
RH		 3188 *total = COSTS_N_INSNS (addsubcosts (x));
3189 return true;
3190
3191 case AND:
3192 *total = COSTS_N_INSNS (andcosts (x));
3193 return true;
3194
3195 case MULT:
3196 *total = COSTS_N_INSNS (multcosts (x));
3197 return true;
3198
3199 case ASHIFT:
3200 case ASHIFTRT:
3201 case LSHIFTRT:
3202 *total = COSTS_N_INSNS (shiftcosts (x));
3203 return true;
3204
3205 case DIV:
3206 case UDIV:
3207 case MOD:
3208 case UMOD:
3209 *total = COSTS_N_INSNS (20);
3210 return true;
3211
73a4d10b
R		 3212 case PARALLEL:
3213 if (sh_1el_vec (x, VOIDmode))
3214 *total = outer_code != SET;
3215 if (sh_rep_vec (x, VOIDmode))
3216 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3217 + (outer_code != SET));
3218 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3219 return true;
3220
3c50106f
RH		 3221 case FLOAT:
3222 case FIX:
3223 *total = 100;
3224 return true;
3225
3226 default:
3227 return false;
3228 }
3229}
3230
dcefdf67
RH		 3231/* Compute the cost of an address. For the SH, all valid addresses are
3232 the same cost. Use a slightly higher cost for reg + reg addressing,
3233 since it increases pressure on r0. */
3234
3235static int
f40751dd
JH		 3236sh_address_cost (rtx X,
3237 bool speed ATTRIBUTE_UNUSED)
dcefdf67
RH		 3238{
3239 return (GET_CODE (X) == PLUS
3240 && ! CONSTANT_P (XEXP (X, 1))
3241 && ! TARGET_SHMEDIA ? 1 : 0);
3242}
3c50106f 3243
16bea517 3244/* Code to expand a shift. */
b9654711 3245
0d7e008e 3246void
cf277499 3247gen_ashift (int type, int n, rtx reg)
0d7e008e 3248{
16bea517
JW		 3249 /* Negative values here come from the shift_amounts array. */
3250 if (n < 0)
3251 {
3252 if (type == ASHIFT)
3253 type = LSHIFTRT;
3254 else
3255 type = ASHIFT;
3256 n = -n;
3257 }
3258
0d7e008e 3259 switch (type)
bc45ade3 3260 {
0d7e008e
SC		 3261 case ASHIFTRT:
3262 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
3263 break;
3264 case LSHIFTRT:
16bea517
JW		 3265 if (n == 1)
3266 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
3267 else
3268 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
0d7e008e
SC		 3269 break;
3270 case ASHIFT:
7e2fda6e 3271 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
0d7e008e 3272 break;
bc45ade3 3273 }
bc45ade3 3274}
bc45ade3 3275
8d481241
JW		 3276/* Same for HImode */
3277
3278void
cf277499 3279gen_ashift_hi (int type, int n, rtx reg)
8d481241
JW		 3280{
3281 /* Negative values here come from the shift_amounts array. */
3282 if (n < 0)
3283 {
3284 if (type == ASHIFT)
3285 type = LSHIFTRT;
3286 else
3287 type = ASHIFT;
3288 n = -n;
3289 }
3290
3291 switch (type)
3292 {
3293 case ASHIFTRT:
8d481241 3294 case LSHIFTRT:
d0c42859
R		 3295 /* We don't have HImode right shift operations because using the
3296 ordinary 32 bit shift instructions for that doesn't generate proper
3297 zero/sign extension.
3298 gen_ashift_hi is only called in contexts where we know that the
3299 sign extension works out correctly. */
97d6fd65 3300 {
ddef6bc7 3301 int offset = 0;
97d6fd65
R		 3302 if (GET_CODE (reg) == SUBREG)
3303 {
ddef6bc7 3304 offset = SUBREG_BYTE (reg);
97d6fd65
R		 3305 reg = SUBREG_REG (reg);
3306 }
ddef6bc7 3307 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
97d6fd65
R		 3308 break;
3309 }
8d481241
JW		 3310 case ASHIFT:
3311 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
3312 break;
3313 }
3314}
3315
8aa2a305
JW		 3316/* Output RTL to split a constant shift into its component SH constant
3317 shift instructions. */
f676971a 3318
318881c0 3319void
cf277499 3320gen_shifty_op (int code, rtx *operands)
bc45ade3 3321{
16bea517 3322 int value = INTVAL (operands[2]);
8aa2a305 3323 int max, i;
00f8ff66 3324
cff3d762 3325 /* Truncate the shift count in case it is out of bounds. */
6c34a092 3326 value = value & 31;
f676971a 3327
8aa2a305 3328 if (value == 31)
16bea517 3329 {
8aa2a305 3330 if (code == LSHIFTRT)
0d7e008e 3331 {
8aa2a305
JW		 3332 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3333 emit_insn (gen_movt (operands[0]));
3334 return;
16bea517 3335 }
8aa2a305 3336 else if (code == ASHIFT)
16bea517 3337 {
8aa2a305
JW		 3338 /* There is a two instruction sequence for 31 bit left shifts,
3339 but it requires r0. */
f3536097 3340 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
0d7e008e 3341 {
8aa2a305
JW		 3342 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
3343 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3344 return;
0d7e008e 3345 }
16bea517 3346 }
8aa2a305 3347 }
c17f53a8
JW		 3348 else if (value == 0)
3349 {
73a4d10b
R		 3350 /* This can happen even when optimizing, if there were subregs before
3351 reload. Don't output a nop here, as this is never optimized away;
3352 use a no-op move instead. */
3353 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
c17f53a8
JW		 3354 return;
3355 }
a9f71ad8 3356
8aa2a305
JW		 3357 max = shift_insns[value];
3358 for (i = 0; i < max; i++)
3359 gen_ashift (code, shift_amounts[value][i], operands[0]);
3360}
f676971a 3361
8d481241
JW		 3362/* Same as above, but optimized for values where the topmost bits don't
3363 matter. */
3364
318881c0 3365void
cf277499 3366gen_shifty_hi_op (int code, rtx *operands)
8d481241
JW		 3367{
3368 int value = INTVAL (operands[2]);
3369 int max, i;
cf277499 3370 void (*gen_fun) (int, int, rtx);
8d481241
JW		 3371
3372 /* This operation is used by and_shl for SImode values with a few
3373 high bits known to be cleared. */
3374 value &= 31;
3375 if (value == 0)
3376 {
3377 emit_insn (gen_nop ());
3378 return;
3379 }
3380
3381 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
3382 if (code == ASHIFT)
3383 {
3384 max = ext_shift_insns[value];
3385 for (i = 0; i < max; i++)
3386 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3387 }
3388 else
3389 /* When shifting right, emit the shifts in reverse order, so that
3390 solitary negative values come first. */
3391 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
3392 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3393}
8aa2a305
JW		 3394
3395/* Output RTL for an arithmetic right shift. */
3396
3397/* ??? Rewrite to use super-optimizer sequences. */
3398
3399int
cf277499 3400expand_ashiftrt (rtx *operands)
8aa2a305
JW		 3401{
3402 rtx wrk;
3403 char func[18];
8aa2a305
JW		 3404 int value;
3405
49b6d06b 3406 if (TARGET_SH3)
20b04867 3407 {
f3536097 3408 if (!CONST_INT_P (operands[2]))
49b6d06b
JW		 3409 {
3410 rtx count = copy_to_mode_reg (SImode, operands[2]);
3411 emit_insn (gen_negsi2 (count, count));
3412 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3413 return 1;
3414 }
1245df60
R		 3415 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
3416 > 1 + SH_DYNAMIC_SHIFT_COST)
49b6d06b 3417 {
1245df60
R		 3418 rtx count
3419 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
49b6d06b
JW		 3420 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3421 return 1;
3422 }
20b04867 3423 }
f3536097 3424 if (!CONST_INT_P (operands[2]))
8aa2a305
JW		 3425 return 0;
3426
1245df60 3427 value = INTVAL (operands[2]) & 31;
8aa2a305
JW		 3428
3429 if (value == 31)
3430 {
73a4d10b
R		 3431 /* If we are called from abs expansion, arrange things so that we
3432 we can use a single MT instruction that doesn't clobber the source,
3433 if LICM can hoist out the load of the constant zero. */
3434 if (currently_expanding_to_rtl)
3435 {
3436 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
3437 operands[1]));
3438 emit_insn (gen_mov_neg_si_t (operands[0]));
3439 return 1;
3440 }
8aa2a305
JW		 3441 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
3442 return 1;
3443 }
3444 else if (value >= 16 && value <= 19)
3445 {
3446 wrk = gen_reg_rtx (SImode);
3447 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
3448 value -= 16;
3449 while (value--)
3450 gen_ashift (ASHIFTRT, 1, wrk);
3451 emit_move_insn (operands[0], wrk);
3452 return 1;
a9f71ad8 3453 }
8aa2a305
JW		 3454 /* Expand a short sequence inline, longer call a magic routine. */
3455 else if (value <= 5)
3456 {
3457 wrk = gen_reg_rtx (SImode);
3458 emit_move_insn (wrk, operands[1]);
3459 while (value--)
3460 gen_ashift (ASHIFTRT, 1, wrk);
3461 emit_move_insn (operands[0], wrk);
3462 return 1;
3463 }
3464
3465 wrk = gen_reg_rtx (Pmode);
3466
3467 /* Load the value into an arg reg and call a helper. */
c5c76735 3468 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
8aa2a305 3469 sprintf (func, "__ashiftrt_r4_%d", value);
73a4d10b 3470 function_symbol (wrk, func, SFUNC_STATIC);
8aa2a305 3471 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
c5c76735 3472 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
8aa2a305 3473 return 1;
bc45ade3 3474}
8d481241 3475
318881c0 3476int
cf277499 3477sh_dynamicalize_shift_p (rtx count)
1245df60 3478{
6c34a092 3479 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
1245df60
R		 3480}
3481
8d481241
JW		 3482/* Try to find a good way to implement the combiner pattern
3483 [(set (match_operand:SI 0 "register_operand" "r")
3484 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3485 (match_operand:SI 2 "const_int_operand" "n"))
3486 (match_operand:SI 3 "const_int_operand" "n"))) .
3487 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3488 return 0 for simple right / left or left/right shift combination.
3489 return 1 for a combination of shifts with zero_extend.
3490 return 2 for a combination of shifts with an AND that needs r0.
3491 return 3 for a combination of shifts with an AND that needs an extra
3492 scratch register, when the three highmost bits of the AND mask are clear.
3493 return 4 for a combination of shifts with an AND that needs an extra
3494 scratch register, when any of the three highmost bits of the AND mask
3495 is set.
3496 If ATTRP is set, store an initial right shift width in ATTRP[0],
3497 and the instruction length in ATTRP[1] . These values are not valid
3498 when returning 0.
3499 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3500 shift_amounts for the last shift value that is to be used before the
3501 sign extend. */
3502int
cf277499 3503shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
8d481241
JW		 3504{
3505 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
3506 int left = INTVAL (left_rtx), right;
3507 int best = 0;
3508 int cost, best_cost = 10000;
3509 int best_right = 0, best_len = 0;
3510 int i;
3511 int can_ext;
3512
3513 if (left < 0 || left > 31)
3514 return 0;
f3536097 3515 if (CONST_INT_P (mask_rtx))
8d481241
JW		 3516 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3517 else
3518 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
832a3292 3519 /* Can this be expressed as a right shift / left shift pair? */
8d481241
JW		 3520 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3521 right = exact_log2 (lsb);
3522 mask2 = ~(mask + lsb - 1);
3523 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3524 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3525 if (! mask2)
3526 best_cost = shift_insns[right] + shift_insns[right + left];
3527 /* mask has no trailing zeroes <==> ! right */
3528 else if (! right && mask2 == ~(lsb2 - 1))
3529 {
3530 int late_right = exact_log2 (lsb2);
3531 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
3532 }
832a3292 3533 /* Try to use zero extend. */
8d481241
JW		 3534 if (mask2 == ~(lsb2 - 1))
3535 {
3536 int width, first;
3537
3538 for (width = 8; width <= 16; width += 8)
3539 {
832a3292
KH		 3540 /* Can we zero-extend right away? */
3541 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
8d481241
JW		 3542 {
3543 cost
3544 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
3545 if (cost < best_cost)
3546 {
3547 best = 1;
3548 best_cost = cost;
3549 best_right = right;
3550 best_len = cost;
3551 if (attrp)
3552 attrp[2] = -1;
3553 }
3554 continue;
3555 }
3556 /* ??? Could try to put zero extend into initial right shift,
6f317ef3 3557 or even shift a bit left before the right shift. */
8d481241
JW		 3558 /* Determine value of first part of left shift, to get to the
3559 zero extend cut-off point. */
3560 first = width - exact_log2 (lsb2) + right;
3561 if (first >= 0 && right + left - first >= 0)
3562 {
3563 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
3564 + ext_shift_insns[right + left - first];
3565 if (cost < best_cost)
3566 {
3567 best = 1;
3568 best_cost = cost;
3569 best_right = right;
3570 best_len = cost;
3571 if (attrp)
3572 attrp[2] = first;
832a3292 3573 }
8d481241
JW		 3574 }
3575 }
3576 }
3577 /* Try to use r0 AND pattern */
3578 for (i = 0; i <= 2; i++)
3579 {
3580 if (i > right)
3581 break;
735cb76e 3582 if (! CONST_OK_FOR_K08 (mask >> i))
8d481241
JW		 3583 continue;
3584 cost = (i != 0) + 2 + ext_shift_insns[left + i];
3585 if (cost < best_cost)
3586 {
3587 best = 2;
3588 best_cost = cost;
3589 best_right = i;
3590 best_len = cost - 1;
3591 }
3592 }
3593 /* Try to use a scratch register to hold the AND operand. */
832a3292 3594 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
8d481241
JW		 3595 for (i = 0; i <= 2; i++)
3596 {
3597 if (i > right)
3598 break;
735cb76e 3599 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
6ab911bb 3600 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
8d481241
JW		 3601 if (cost < best_cost)
3602 {
3603 best = 4 - can_ext;
3604 best_cost = cost;
3605 best_right = i;
735cb76e 3606 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
8d481241
JW		 3607 }
3608 }
3609
3610 if (attrp)
3611 {
3612 attrp[0] = best_right;
3613 attrp[1] = best_len;
3614 }
3615 return best;
3616}
3617
3618/* This is used in length attributes of the unnamed instructions
3619 corresponding to shl_and_kind return values of 1 and 2. */
3620int
cf277499 3621shl_and_length (rtx insn)
8d481241
JW		 3622{
3623 rtx set_src, left_rtx, mask_rtx;
3624 int attributes[3];
3625
3626 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3627 left_rtx = XEXP (XEXP (set_src, 0), 1);
3628 mask_rtx = XEXP (set_src, 1);
3629 shl_and_kind (left_rtx, mask_rtx, attributes);
3630 return attributes[1];
3631}
3632
3633/* This is used in length attribute of the and_shl_scratch instruction. */
3634
3635int
cf277499 3636shl_and_scr_length (rtx insn)
8d481241
JW		 3637{
3638 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
6c34a092 3639 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
8d481241 3640 rtx op = XEXP (set_src, 0);
6c34a092 3641 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
8d481241 3642 op = XEXP (XEXP (op, 0), 0);
6c34a092 3643 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
8d481241
JW		 3644}
3645
8d481241
JW		 3646/* Generate rtl for instructions for which shl_and_kind advised a particular
3647 method of generating them, i.e. returned zero. */
3648
3649int
cf277499 3650gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
8d481241
JW		 3651{
3652 int attributes[3];
3653 unsigned HOST_WIDE_INT mask;
3654 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3655 int right, total_shift;
832a3292 3656 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
8d481241
JW		 3657
3658 right = attributes[0];
3659 total_shift = INTVAL (left_rtx) + right;
3660 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3661 switch (kind)
3662 {
3663 default:
3664 return -1;
3665 case 1:
3666 {
3667 int first = attributes[2];
3668 rtx operands[3];
3669
3670 if (first < 0)
3671 {
7174c937 3672 emit_insn ((mask << right) <= 0xff
832a3292
KH		 3673 ? gen_zero_extendqisi2 (dest,
3674 gen_lowpart (QImode, source))
3675 : gen_zero_extendhisi2 (dest,
3676 gen_lowpart (HImode, source)));
8d481241
JW		 3677 source = dest;
3678 }
3679 if (source != dest)
3680 emit_insn (gen_movsi (dest, source));
3681 operands[0] = dest;
3682 if (right)
3683 {
3684 operands[2] = GEN_INT (right);
3685 gen_shifty_hi_op (LSHIFTRT, operands);
3686 }
3687 if (first > 0)
3688 {
3689 operands[2] = GEN_INT (first);
3690 gen_shifty_hi_op (ASHIFT, operands);
3691 total_shift -= first;
3692 mask <<= first;
3693 }
3694 if (first >= 0)
85af47b9 3695 emit_insn (mask <= 0xff
832a3292
KH		 3696 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3697 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
8d481241
JW		 3698 if (total_shift > 0)
3699 {
3700 operands[2] = GEN_INT (total_shift);
3701 gen_shifty_hi_op (ASHIFT, operands);
3702 }
3703 break;
3704 }
3705 case 4:
3706 shift_gen_fun = gen_shifty_op;
8d481241 3707 case 3:
24c50999
JR		 3708 /* If the topmost bit that matters is set, set the topmost bits
3709 that don't matter. This way, we might be able to get a shorter
3710 signed constant. */
832a3292
KH		 3711 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3712 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
61fb6bac 3713 case 2:
8d481241
JW		 3714 /* Don't expand fine-grained when combining, because that will
3715 make the pattern fail. */
4586b4ca 3716 if (currently_expanding_to_rtl
8d481241
JW		 3717 || reload_in_progress || reload_completed)
3718 {
3719 rtx operands[3];
f676971a 3720
61fb6bac
R		 3721 /* Cases 3 and 4 should be handled by this split
3722 only while combining */
f5b9e7c9 3723 gcc_assert (kind <= 2);
8d481241
JW		 3724 if (right)
3725 {
3726 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3727 source = dest;
3728 }
3729 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
afad3d2c
JW		 3730 if (total_shift)
3731 {
3732 operands[0] = dest;
3733 operands[1] = dest;
3734 operands[2] = GEN_INT (total_shift);
3735 shift_gen_fun (ASHIFT, operands);
3736 }
8d481241
JW		 3737 break;
3738 }
3739 else
3740 {
3741 int neg = 0;
3742 if (kind != 4 && total_shift < 16)
3743 {
3744 neg = -ext_shift_amounts[total_shift][1];
3745 if (neg > 0)
3746 neg -= ext_shift_amounts[total_shift][2];
3747 else
3748 neg = 0;
3749 }
3750 emit_insn (gen_and_shl_scratch (dest, source,
3751 GEN_INT (right),
3752 GEN_INT (mask),
3753 GEN_INT (total_shift + neg),
3754 GEN_INT (neg)));
3755 emit_insn (gen_movsi (dest, dest));
3756 break;
3757 }
3758 }
3759 return 0;
3760}
3761
3762/* Try to find a good way to implement the combiner pattern
3763 [(set (match_operand:SI 0 "register_operand" "=r")
3764 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3765 (match_operand:SI 2 "const_int_operand" "n")
3766 (match_operand:SI 3 "const_int_operand" "n")
3767 (const_int 0)))
4773afa4 3768 (clobber (reg:SI T_REG))]
8d481241
JW		 3769 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3770 return 0 for simple left / right shift combination.
3771 return 1 for left shift / 8 bit sign extend / left shift.
3772 return 2 for left shift / 16 bit sign extend / left shift.
3773 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3774 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3775 return 5 for left shift / 16 bit sign extend / right shift
3776 return 6 for < 8 bit sign extend / left shift.
3777 return 7 for < 8 bit sign extend / left shift / single right shift.
3778 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3779
3780int
cf277499 3781shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
8d481241
JW		 3782{
3783 int left, size, insize, ext;
3a8699c7 3784 int cost = 0, best_cost;
8d481241
JW		 3785 int kind;
3786
3787 left = INTVAL (left_rtx);
3788 size = INTVAL (size_rtx);
3789 insize = size - left;
f5b9e7c9 3790 gcc_assert (insize > 0);
8d481241
JW		 3791 /* Default to left / right shift. */
3792 kind = 0;
3793 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3794 if (size <= 16)
3795 {
3796 /* 16 bit shift / sign extend / 16 bit shift */
3797 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
afad3d2c
JW		 3798 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3799 below, by alternative 3 or something even better. */
8d481241
JW		 3800 if (cost < best_cost)
3801 {
3802 kind = 5;
3803 best_cost = cost;
3804 }
3805 }
3806 /* Try a plain sign extend between two shifts. */
3807 for (ext = 16; ext >= insize; ext -= 8)
3808 {
3809 if (ext <= size)
3810 {
3811 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3812 if (cost < best_cost)
3813 {
11f9ed1a 3814 kind = ext / (unsigned) 8;
8d481241
JW		 3815 best_cost = cost;
3816 }
3817 }
ae9d19c0
JR		 3818 /* Check if we can do a sloppy shift with a final signed shift
3819 restoring the sign. */
3820 if (EXT_SHIFT_SIGNED (size - ext))
3821 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3822 /* If not, maybe it's still cheaper to do the second shift sloppy,
3823 and do a final sign extend? */
3824 else if (size <= 16)
3825 cost = ext_shift_insns[ext - insize] + 1
3826 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3827 else
3828 continue;
3829 if (cost < best_cost)
8d481241 3830 {
11f9ed1a 3831 kind = ext / (unsigned) 8 + 2;
ae9d19c0 3832 best_cost = cost;
8d481241
JW		 3833 }
3834 }
3835 /* Check if we can sign extend in r0 */
3836 if (insize < 8)
3837 {
3838 cost = 3 + shift_insns[left];
3839 if (cost < best_cost)
3840 {
3841 kind = 6;
3842 best_cost = cost;
3843 }
3844 /* Try the same with a final signed shift. */
3845 if (left < 31)
3846 {
3847 cost = 3 + ext_shift_insns[left + 1] + 1;
3848 if (cost < best_cost)
3849 {
3850 kind = 7;
3851 best_cost = cost;
3852 }
3853 }
3854 }
3855 if (TARGET_SH3)
3856 {
3857 /* Try to use a dynamic shift. */
1245df60 3858 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
8d481241
JW		 3859 if (cost < best_cost)
3860 {
3861 kind = 0;
3862 best_cost = cost;
3863 }
3864 }
3865 if (costp)
3866 *costp = cost;
3867 return kind;
3868}
3869
3870/* Function to be used in the length attribute of the instructions
3871 implementing this pattern. */
3872
3873int
cf277499 3874shl_sext_length (rtx insn)
8d481241
JW		 3875{
3876 rtx set_src, left_rtx, size_rtx;
3877 int cost;
3878
3879 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3880 left_rtx = XEXP (XEXP (set_src, 0), 1);
3881 size_rtx = XEXP (set_src, 1);
3882 shl_sext_kind (left_rtx, size_rtx, &cost);
3883 return cost;
3884}
3885
3886/* Generate rtl for this pattern */
3887
3888int
cf277499 3889gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
8d481241
JW		 3890{
3891 int kind;
d00d338c 3892 int left, size, insize, cost;
8d481241
JW		 3893 rtx operands[3];
3894
d00d338c 3895 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
8d481241
JW		 3896 left = INTVAL (left_rtx);
3897 size = INTVAL (size_rtx);
3898 insize = size - left;
3899 switch (kind)
3900 {
3901 case 1:
3902 case 2:
3903 case 3:
3904 case 4:
3905 {
3906 int ext = kind & 1 ? 8 : 16;
3907 int shift2 = size - ext;
3908
3909 /* Don't expand fine-grained when combining, because that will
3910 make the pattern fail. */
4586b4ca 3911 if (! currently_expanding_to_rtl
8d481241
JW		 3912 && ! reload_in_progress && ! reload_completed)
3913 {
3914 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3915 emit_insn (gen_movsi (dest, source));
3916 break;
3917 }
3918 if (dest != source)
3919 emit_insn (gen_movsi (dest, source));
3920 operands[0] = dest;
afad3d2c
JW		 3921 if (ext - insize)
3922 {
3923 operands[2] = GEN_INT (ext - insize);
3924 gen_shifty_hi_op (ASHIFT, operands);
3925 }
8d481241 3926 emit_insn (kind & 1
832a3292
KH		 3927 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3928 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
8d481241
JW		 3929 if (kind <= 2)
3930 {
afad3d2c
JW		 3931 if (shift2)
3932 {
3933 operands[2] = GEN_INT (shift2);
3934 gen_shifty_op (ASHIFT, operands);
3935 }
8d481241
JW		 3936 }
3937 else
3938 {
afad3d2c 3939 if (shift2 > 0)
8d481241 3940 {
ae9d19c0
JR		 3941 if (EXT_SHIFT_SIGNED (shift2))
3942 {
3943 operands[2] = GEN_INT (shift2 + 1);
3944 gen_shifty_op (ASHIFT, operands);
a556fd39 3945 operands[2] = const1_rtx;
ae9d19c0
JR		 3946 gen_shifty_op (ASHIFTRT, operands);
3947 break;
3948 }
8d481241
JW		 3949 operands[2] = GEN_INT (shift2);
3950 gen_shifty_hi_op (ASHIFT, operands);
3951 }
afad3d2c 3952 else if (shift2)
8d481241
JW		 3953 {
3954 operands[2] = GEN_INT (-shift2);
3955 gen_shifty_hi_op (LSHIFTRT, operands);
3956 }
3957 emit_insn (size <= 8
afad3d2c
JW		 3958 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3959 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
8d481241
JW		 3960 }
3961 break;
3962 }
3963 case 5:
afad3d2c
JW		 3964 {
3965 int i = 16 - size;
4586b4ca 3966 if (! currently_expanding_to_rtl
913d8e13
R		 3967 && ! reload_in_progress && ! reload_completed)
3968 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3969 else
3970 {
3971 operands[0] = dest;
3972 operands[2] = GEN_INT (16 - insize);
3973 gen_shifty_hi_op (ASHIFT, operands);
3974 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3975 }
afad3d2c
JW		 3976 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3977 while (--i >= 0)
3978 gen_ashift (ASHIFTRT, 1, dest);
3979 break;
3980 }
8d481241
JW		 3981 case 6:
3982 case 7:
3983 /* Don't expand fine-grained when combining, because that will
3984 make the pattern fail. */
4586b4ca 3985 if (! currently_expanding_to_rtl
8d481241
JW		 3986 && ! reload_in_progress && ! reload_completed)
3987 {
3988 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3989 emit_insn (gen_movsi (dest, source));
3990 break;
3991 }
3992 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3993 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3994 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3995 operands[0] = dest;
3996 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3997 gen_shifty_op (ASHIFT, operands);
3998 if (kind == 7)
a556fd39 3999 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
8d481241
JW		 4000 break;
4001 default:
4002 return -1;
4003 }
4004 return 0;
4005}
fa5322fa
AO		 4006
4007/* Prefix a symbol_ref name with "datalabel". */
4008
4009rtx
cf277499 4010gen_datalabel_ref (rtx sym)
fa5322fa 4011{
73a4d10b
R		 4012 const char *str;
4013
fa5322fa
AO		 4014 if (GET_CODE (sym) == LABEL_REF)
4015 return gen_rtx_CONST (GET_MODE (sym),
4016 gen_rtx_UNSPEC (GET_MODE (sym),
4017 gen_rtvec (1, sym),
4018 UNSPEC_DATALABEL));
f676971a 4019
f5b9e7c9 4020 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
fa5322fa 4021
73a4d10b
R		 4022 str = XSTR (sym, 0);
4023 /* Share all SYMBOL_REF strings with the same value - that is important
4024 for cse. */
4025 str = IDENTIFIER_POINTER (get_identifier (str));
4026 XSTR (sym, 0) = str;
4027
fa5322fa
AO		 4028 return sym;
4029}
4030
8aa2a305 4031\f
6dd3c0a5
SB		 4032static alloc_pool label_ref_list_pool;
4033
4034typedef struct label_ref_list_d
4035{
4036 rtx label;
4037 struct label_ref_list_d *next;
4038} *label_ref_list_t;
4039
8aa2a305
JW		 4040/* The SH cannot load a large constant into a register, constants have to
4041 come from a pc relative load. The reference of a pc relative load
0fa2e4df 4042 instruction must be less than 1k in front of the instruction. This
8aa2a305
JW		 4043 means that we often have to dump a constant inside a function, and
4044 generate code to branch around it.
bc45ade3 4045
8aa2a305
JW		 4046 It is important to minimize this, since the branches will slow things
4047 down and make things bigger.
4048
4049 Worst case code looks like:
4050
4051 mov.l L1,rn
4052 bra L2
4053 nop
4054 align
4055 L1: .long value
4056 L2:
4057 ..
4058
4059 mov.l L3,rn
4060 bra L4
4061 nop
4062 align
4063 L3: .long value
4064 L4:
4065 ..
4066
4067 We fix this by performing a scan before scheduling, which notices which
4068 instructions need to have their operands fetched from the constant table
4069 and builds the table.
4070
4071 The algorithm is:
4072
4073 scan, find an instruction which needs a pcrel move. Look forward, find the
4074 last barrier which is within MAX_COUNT bytes of the requirement.
4075 If there isn't one, make one. Process all the instructions between
4076 the find and the barrier.
4077
4078 In the above example, we can tell that L3 is within 1k of L1, so
4079 the first move can be shrunk from the 3 insn+constant sequence into
4080 just 1 insn, and the constant moved to L3 to make:
4081
4082 mov.l L1,rn
4083 ..
4084 mov.l L3,rn
4085 bra L4
4086 nop
4087 align
4088 L3:.long value
4089 L4:.long value
4090
4091 Then the second move becomes the target for the shortening process. */
4092
4093typedef struct
4094{
4095 rtx value; /* Value in table. */
4096 rtx label; /* Label of value. */
6dd3c0a5 4097 label_ref_list_t wend; /* End of window. */
8aa2a305 4098 enum machine_mode mode; /* Mode of value. */
3503150c
RS		 4099
4100 /* True if this constant is accessed as part of a post-increment
4101 sequence. Note that HImode constants are never accessed in this way. */
4102 bool part_of_sequence_p;
8aa2a305
JW		 4103} pool_node;
4104
4105/* The maximum number of constants that can fit into one pool, since
73a4d10b
R		 4106 constants in the range 0..510 are at least 2 bytes long, and in the
4107 range from there to 1018 at least 4 bytes. */
8aa2a305 4108
73a4d10b 4109#define MAX_POOL_SIZE 372
8aa2a305
JW		 4110static pool_node pool_vector[MAX_POOL_SIZE];
4111static int pool_size;
b91455de
KK		 4112static rtx pool_window_label;
4113static int pool_window_last;
8aa2a305 4114
4241ecb0
R		 4115static int max_labelno_before_reorg;
4116
8aa2a305
JW		 4117/* ??? If we need a constant in HImode which is the truncated value of a
4118 constant we need in SImode, we could combine the two entries thus saving
4119 two bytes. Is this common enough to be worth the effort of implementing
4120 it? */
4121
4122/* ??? This stuff should be done at the same time that we shorten branches.
4123 As it is now, we must assume that all branches are the maximum size, and
4124 this causes us to almost always output constant pools sooner than
4125 necessary. */
4126
4127/* Add a constant to the pool and return its label. */
4128
4129static rtx
cf277499 4130add_constant (rtx x, enum machine_mode mode, rtx last_value)
0d7e008e
SC		 4131{
4132 int i;
0a2aaacc 4133 rtx lab, new_rtx;
6dd3c0a5 4134 label_ref_list_t ref, newref;
8aa2a305
JW		 4135
4136 /* First see if we've already got it. */
4137 for (i = 0; i < pool_size; i++)
0d7e008e 4138 {
8aa2a305
JW		 4139 if (x->code == pool_vector[i].value->code
4140 && mode == pool_vector[i].mode)
0d7e008e 4141 {
8aa2a305
JW		 4142 if (x->code == CODE_LABEL)
4143 {
4144 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
4145 continue;
4146 }
4147 if (rtx_equal_p (x, pool_vector[i].value))
225e4f43 4148 {
0a2aaacc 4149 lab = new_rtx = 0;
225e4f43
R		 4150 if (! last_value
4151 || ! i
4152 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
4153 {
0a2aaacc
KG		 4154 new_rtx = gen_label_rtx ();
4155 LABEL_REFS (new_rtx) = pool_vector[i].label;
4156 pool_vector[i].label = lab = new_rtx;
225e4f43 4157 }
b91455de
KK		 4158 if (lab && pool_window_label)
4159 {
6dd3c0a5
SB		 4160 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
4161 newref->label = pool_window_label;
b91455de 4162 ref = pool_vector[pool_window_last].wend;
6dd3c0a5 4163 newref->next = ref;
b91455de
KK		 4164 pool_vector[pool_window_last].wend = newref;
4165 }
0a2aaacc
KG		 4166 if (new_rtx)
4167 pool_window_label = new_rtx;
b91455de 4168 pool_window_last = i;
225e4f43
R		 4169 return lab;
4170 }
0d7e008e 4171 }
0d7e008e 4172 }
b9654711 4173
8aa2a305
JW		 4174 /* Need a new one. */
4175 pool_vector[pool_size].value = x;
225e4f43 4176 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3503150c
RS		 4177 {
4178 lab = 0;
4179 pool_vector[pool_size - 1].part_of_sequence_p = true;
4180 }
225e4f43
R		 4181 else
4182 lab = gen_label_rtx ();
8aa2a305
JW		 4183 pool_vector[pool_size].mode = mode;
4184 pool_vector[pool_size].label = lab;
6dd3c0a5 4185 pool_vector[pool_size].wend = NULL;
3503150c 4186 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
b91455de
KK		 4187 if (lab && pool_window_label)
4188 {
6dd3c0a5
SB		 4189 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
4190 newref->label = pool_window_label;
b91455de 4191 ref = pool_vector[pool_window_last].wend;
6dd3c0a5 4192 newref->next = ref;
b91455de
KK		 4193 pool_vector[pool_window_last].wend = newref;
4194 }
4195 if (lab)
4196 pool_window_label = lab;
4197 pool_window_last = pool_size;
8aa2a305
JW		 4198 pool_size++;
4199 return lab;
0d7e008e 4200}
16bea517 4201
078c8b08
R		 4202/* Output the literal table. START, if nonzero, is the first instruction
4203 this table is needed for, and also indicates that there is at least one
4204 casesi_worker_2 instruction; We have to emit the operand3 labels from
4205 these insns at a 4-byte aligned position. BARRIER is the barrier
4206 after which we are to place the table. */
b9654711 4207
b9654711 4208static void
078c8b08 4209dump_table (rtx start, rtx barrier)
b9654711 4210{
078c8b08 4211 rtx scan = barrier;
0d7e008e 4212 int i;
0d7e008e 4213 int need_align = 1;
6dd3c0a5
SB		 4214 rtx lab;
4215 label_ref_list_t ref;
aa06e8f5 4216 int have_df = 0;
b9654711 4217
16bea517 4218 /* Do two passes, first time dump out the HI sized constants. */
b9654711 4219
0d7e008e 4220 for (i = 0; i < pool_size; i++)
b9654711 4221 {
8aa2a305
JW		 4222 pool_node *p = &pool_vector[i];
4223
0d7e008e
SC		 4224 if (p->mode == HImode)
4225 {
4226 if (need_align)
4227 {
4228 scan = emit_insn_after (gen_align_2 (), scan);
4229 need_align = 0;
4230 }
b91455de
KK		 4231 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4232 scan = emit_label_after (lab, scan);
4233 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
4234 scan);
6dd3c0a5 4235 for (ref = p->wend; ref; ref = ref->next)
b91455de 4236 {
6dd3c0a5 4237 lab = ref->label;
b91455de
KK		 4238 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4239 }
0d7e008e 4240 }
aa06e8f5
R		 4241 else if (p->mode == DFmode)
4242 have_df = 1;
b9654711 4243 }
8aa2a305 4244
0d7e008e 4245 need_align = 1;
b9654711 4246
078c8b08
R		 4247 if (start)
4248 {
4249 scan = emit_insn_after (gen_align_4 (), scan);
4250 need_align = 0;
4251 for (; start != barrier; start = NEXT_INSN (start))
f3536097 4252 if (NONJUMP_INSN_P (start)
078c8b08
R		 4253 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
4254 {
4255 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
4256 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
4257
4258 scan = emit_label_after (lab, scan);
4259 }
4260 }
aa06e8f5 4261 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
fa5322fa
AO		 4262 {
4263 rtx align_insn = NULL_RTX;
4264
4265 scan = emit_label_after (gen_label_rtx (), scan);
4266 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4267 need_align = 0;
4268
4269 for (i = 0; i < pool_size; i++)
4270 {
4271 pool_node *p = &pool_vector[i];
4272
4273 switch (p->mode)
4274 {
4275 case HImode:
4276 break;
4277 case SImode:
4278 case SFmode:
3503150c 4279 if (align_insn && !p->part_of_sequence_p)
fa5322fa
AO		 4280 {
4281 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4282 emit_label_before (lab, align_insn);
4283 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
4284 align_insn);
6dd3c0a5 4285 for (ref = p->wend; ref; ref = ref->next)
fa5322fa 4286 {
6dd3c0a5 4287 lab = ref->label;
fa5322fa 4288 emit_insn_before (gen_consttable_window_end (lab),
832a3292 4289 align_insn);
fa5322fa
AO		 4290 }
4291 delete_insn (align_insn);
4292 align_insn = NULL_RTX;
4293 continue;
4294 }
4295 else
4296 {
4297 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4298 scan = emit_label_after (lab, scan);
4299 scan = emit_insn_after (gen_consttable_4 (p->value,
4300 const0_rtx), scan);
4301 need_align = ! need_align;
4302 }
4303 break;
4304 case DFmode:
fa5322fa
AO		 4305 if (need_align)
4306 {
4307 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4308 align_insn = scan;
4309 need_align = 0;
4310 }
aa06e8f5 4311 case DImode:
fa5322fa
AO		 4312 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4313 scan = emit_label_after (lab, scan);
4314 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4315 scan);
4316 break;
4317 default:
f5b9e7c9 4318 gcc_unreachable ();
fa5322fa
AO		 4319 }
4320
4321 if (p->mode != HImode)
4322 {
6dd3c0a5 4323 for (ref = p->wend; ref; ref = ref->next)
fa5322fa 4324 {
6dd3c0a5 4325 lab = ref->label;
fa5322fa
AO		 4326 scan = emit_insn_after (gen_consttable_window_end (lab),
4327 scan);
4328 }
4329 }
4330 }
4331
4332 pool_size = 0;
4333 }
f676971a 4334
0d7e008e 4335 for (i = 0; i < pool_size; i++)
b9654711 4336 {
8aa2a305 4337 pool_node *p = &pool_vector[i];
b9654711 4338
0d7e008e 4339 switch (p->mode)
b9654711 4340 {
0d7e008e
SC		 4341 case HImode:
4342 break;
4343 case SImode:
e577c183 4344 case SFmode:
0d7e008e 4345 if (need_align)
b9654711 4346 {
0d7e008e 4347 need_align = 0;
d3ae8277 4348 scan = emit_label_after (gen_label_rtx (), scan);
0d7e008e 4349 scan = emit_insn_after (gen_align_4 (), scan);
b9654711 4350 }
b91455de
KK		 4351 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4352 scan = emit_label_after (lab, scan);
4353 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
4354 scan);
0d7e008e 4355 break;
e577c183 4356 case DFmode:
0d7e008e
SC		 4357 case DImode:
4358 if (need_align)
4359 {
4360 need_align = 0;
d3ae8277 4361 scan = emit_label_after (gen_label_rtx (), scan);
0d7e008e
SC		 4362 scan = emit_insn_after (gen_align_4 (), scan);
4363 }
b91455de
KK		 4364 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4365 scan = emit_label_after (lab, scan);
4366 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4367 scan);
0d7e008e
SC		 4368 break;
4369 default:
f5b9e7c9 4370 gcc_unreachable ();
b9654711 4371 }
b91455de
KK		 4372
4373 if (p->mode != HImode)
4374 {
6dd3c0a5 4375 for (ref = p->wend; ref; ref = ref->next)
b91455de 4376 {
6dd3c0a5 4377 lab = ref->label;
b91455de
KK		 4378 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4379 }
4380 }
b9654711 4381 }
b9654711 4382
0d7e008e
SC		 4383 scan = emit_insn_after (gen_consttable_end (), scan);
4384 scan = emit_barrier_after (scan);
4385 pool_size = 0;
b91455de
KK		 4386 pool_window_label = NULL_RTX;
4387 pool_window_last = 0;
0d7e008e 4388}
b9654711 4389
5e7a8ee0 4390/* Return nonzero if constant would be an ok source for a
8aa2a305 4391 mov.w instead of a mov.l. */
b9654711 4392
16bea517 4393static int
cf277499 4394hi_const (rtx src)
0d7e008e 4395{
f3536097 4396 return (CONST_INT_P (src)
8aa2a305
JW		 4397 && INTVAL (src) >= -32768
4398 && INTVAL (src) <= 32767);
b9654711
SC		 4399}
4400
4241ecb0
R		 4401#define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4402
5e7a8ee0 4403/* Nonzero if the insn is a move instruction which needs to be fixed. */
8aa2a305
JW		 4404
4405/* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
735cb76e
R		 4406 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4407 need to fix it if the input value is CONST_OK_FOR_I08. */
8aa2a305
JW		 4408
4409static int
cf277499 4410broken_move (rtx insn)
b9654711 4411{
f3536097 4412 if (NONJUMP_INSN_P (insn))
e577c183
JR		 4413 {
4414 rtx pat = PATTERN (insn);
4415 if (GET_CODE (pat) == PARALLEL)
4416 pat = XVECEXP (pat, 0, 0);
4417 if (GET_CODE (pat) == SET
3b962ea0 4418 /* We can load any 8-bit value if we don't care what the high
e577c183
JR		 4419 order bits end up as. */
4420 && GET_MODE (SET_DEST (pat)) != QImode
43c05634
AO		 4421 && (CONSTANT_P (SET_SRC (pat))
4422 /* Match mova_const. */
4423 || (GET_CODE (SET_SRC (pat)) == UNSPEC
4424 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
4425 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
3a8699c7 4426 && ! (TARGET_SH2E
1245df60 4427 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
e577c183
JR		 4428 && (fp_zero_operand (SET_SRC (pat))
4429 || fp_one_operand (SET_SRC (pat)))
7a61cf6f 4430 /* In general we don't know the current setting of fpscr, so disable fldi.
18778292
R		 4431 There is an exception if this was a register-register move
4432 before reload - and hence it was ascertained that we have
4433 single precision setting - and in a post-reload optimization
4434 we changed this to do a constant load. In that case
4435 we don't have an r0 clobber, hence we must use fldi. */
7a61cf6f 4436 && (TARGET_FMOVD
18778292
R		 4437 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
4438 == SCRATCH))
f3536097 4439 && REG_P (SET_DEST (pat))
104ee20b 4440 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
157371cf
AO		 4441 && ! (TARGET_SH2A
4442 && GET_MODE (SET_DEST (pat)) == SImode
e990551a
JS		 4443 && (satisfies_constraint_I20 (SET_SRC (pat))
4444 || satisfies_constraint_I28 (SET_SRC (pat))))
32a7ab3d 4445 && ! satisfies_constraint_I08 (SET_SRC (pat)))
e577c183
JR		 4446 return 1;
4447 }
d3ae8277 4448
8aa2a305 4449 return 0;
b9654711 4450}
b9654711 4451
1245df60 4452static int
cf277499 4453mova_p (rtx insn)
1245df60 4454{
f3536097 4455 return (NONJUMP_INSN_P (insn)
1245df60
R		 4456 && GET_CODE (PATTERN (insn)) == SET
4457 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
43c05634
AO		 4458 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
4459 /* Don't match mova_const. */
4241ecb0 4460 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
1245df60
R		 4461}
4462
078c8b08
R		 4463/* Fix up a mova from a switch that went out of range. */
4464static void
4465fixup_mova (rtx mova)
4466{
4241ecb0 4467 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
078c8b08
R		 4468 if (! flag_pic)
4469 {
4241ecb0 4470 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
078c8b08
R		 4471 INSN_CODE (mova) = -1;
4472 }
4473 else
4474 {
4475 rtx worker = mova;
4476 rtx lab = gen_label_rtx ();
dc3ba671 4477 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
078c8b08
R		 4478
4479 do
4480 {
4481 worker = NEXT_INSN (worker);
f5b9e7c9 4482 gcc_assert (worker
f3536097
SZ		 4483 && !LABEL_P (worker)
4484 && !JUMP_P (worker));
4485 } while (NOTE_P (worker)
0bf72672 4486 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
078c8b08
R		 4487 wpat = PATTERN (worker);
4488 wpat0 = XVECEXP (wpat, 0, 0);
4489 wpat1 = XVECEXP (wpat, 0, 1);
4490 wsrc = SET_SRC (wpat0);
4491 PATTERN (worker) = (gen_casesi_worker_2
4492 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
4493 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
4494 XEXP (wpat1, 0)));
4495 INSN_CODE (worker) = -1;
dc3ba671
RS		 4496 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4497 base = gen_rtx_LABEL_REF (Pmode, lab);
4498 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
078c8b08
R		 4499 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
4500 INSN_CODE (mova) = -1;
4501 }
4502}
4503
4241ecb0
R		 4504/* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4505 *num_mova, and check if the new mova is not nested within the first one.
4506 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4507 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4508static int
4509untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
4510{
c6d56443
KK		 4511 int n_addr = 0; /* Initialization to shut up spurious warning. */
4512 int f_target, n_target = 0; /* Likewise. */
4241ecb0
R		 4513
4514 if (optimize)
4515 {
77253e56
KK		 4516 /* If NEW_MOVA has no address yet, it will be handled later. */
4517 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4518 return -1;
4519
4241ecb0
R		 4520 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4521 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4522 if (n_addr > n_target || n_addr + 1022 < n_target)
4523 {
4524 /* Change the mova into a load.
4525 broken_move will then return true for it. */
4526 fixup_mova (new_mova);
4527 return 1;
4528 }
4529 }
4530 if (!(*num_mova)++)
4531 {
4532 *first_mova = new_mova;
4533 return 2;
4534 }
4535 if (!optimize
4536 || ((f_target
4537 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4538 >= n_target))
4539 return -1;
4540
4541 (*num_mova)--;
4542 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4543 > n_target - n_addr)
4544 {
4545 fixup_mova (*first_mova);
4546 return 0;
4547 }
4548 else
4549 {
4550 fixup_mova (new_mova);
4551 return 1;
4552 }
4553}
4554
8aa2a305
JW		 4555/* Find the last barrier from insn FROM which is close enough to hold the
4556 constant pool. If we can't find one, then create one near the end of
4557 the range. */
b9654711 4558
8aa2a305 4559static rtx
cf277499 4560find_barrier (int num_mova, rtx mova, rtx from)
b9654711 4561{
0d7e008e
SC		 4562 int count_si = 0;
4563 int count_hi = 0;
4564 int found_hi = 0;
4565 int found_si = 0;
fa5322fa 4566 int found_di = 0;
33f7f353
JR		 4567 int hi_align = 2;
4568 int si_align = 2;
1245df60 4569 int leading_mova = num_mova;
3a8699c7 4570 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
c17f53a8
JW		 4571 int si_limit;
4572 int hi_limit;
7a3cb3ab 4573 rtx orig = from;
e938feb4 4574 rtx last_got = NULL_RTX;
fc9c984d 4575 rtx last_symoff = NULL_RTX;
8aa2a305
JW		 4576
4577 /* For HImode: range is 510, add 4 because pc counts from address of
4578 second instruction after this one, subtract 2 for the jump instruction
3adbde60
JW		 4579 that we may need to emit before the table, subtract 2 for the instruction
4580 that fills the jump delay slot (in very rare cases, reorg will take an
4581 instruction from after the constant pool or will leave the delay slot
4582 empty). This gives 510.
8aa2a305
JW		 4583 For SImode: range is 1020, add 4 because pc counts from address of
4584 second instruction after this one, subtract 2 in case pc is 2 byte
4585 aligned, subtract 2 for the jump instruction that we may need to emit
3adbde60
JW		 4586 before the table, subtract 2 for the instruction that fills the jump
4587 delay slot. This gives 1018. */
c17f53a8 4588
1245df60 4589 /* The branch will always be shortened now that the reference address for
956d6950 4590 forward branches is the successor address, thus we need no longer make
1245df60 4591 adjustments to the [sh]i_limit for -O0. */
c17f53a8 4592
1245df60
R		 4593 si_limit = 1018;
4594 hi_limit = 510;
e4fa6b06 4595
c17f53a8 4596 while (from && count_si < si_limit && count_hi < hi_limit)
0d7e008e 4597 {
33f7f353
JR		 4598 int inc = get_attr_length (from);
4599 int new_align = 1;
1245df60 4600
4241ecb0
R		 4601 /* If this is a label that existed at the time of the compute_alignments
4602 call, determine the alignment. N.B. When find_barrier recurses for
4603 an out-of-reach mova, we might see labels at the start of previously
4604 inserted constant tables. */
f3536097 4605 if (LABEL_P (from)
4241ecb0 4606 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
77008a44
R		 4607 {
4608 if (optimize)
4609 new_align = 1 << label_to_alignment (from);
f3536097 4610 else if (BARRIER_P (prev_nonnote_insn (from)))
77008a44
R		 4611 new_align = 1 << barrier_align (from);
4612 else
4613 new_align = 1;
4614 inc = 0;
4615 }
4241ecb0
R		 4616 /* In case we are scanning a constant table because of recursion, check
4617 for explicit alignments. If the table is long, we might be forced
4618 to emit the new table in front of it; the length of the alignment
4619 might be the last straw. */
f3536097 4620 else if (NONJUMP_INSN_P (from)
4241ecb0
R		 4621 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4622 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4623 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4624 /* When we find the end of a constant table, paste the new constant
4625 at the end. That is better than putting it in front because
4626 this way, we don't need extra alignment for adding a 4-byte-aligned
4627 mov(a) label to a 2/4 or 8/4 byte aligned table. */
f3536097 4628 else if (NONJUMP_INSN_P (from)
4241ecb0
R		 4629 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4630 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4631 return from;
8aa2a305 4632
f3536097 4633 if (BARRIER_P (from))
1245df60 4634 {
6d4d15b8 4635 rtx next;
33f7f353 4636
1245df60 4637 found_barrier = from;
33f7f353 4638
956d6950 4639 /* If we are at the end of the function, or in front of an alignment
1245df60
R		 4640 instruction, we need not insert an extra alignment. We prefer
4641 this kind of barrier. */
33f7f353 4642 if (barrier_align (from) > 2)
1245df60 4643 good_barrier = from;
6d4d15b8
KK		 4644
4645 /* If we are at the end of a hot/cold block, dump the constants
4646 here. */
4647 next = NEXT_INSN (from);
4648 if (next
4649 && NOTE_P (next)
4650 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4651 break;
1245df60 4652 }
8aa2a305 4653
8aa2a305 4654 if (broken_move (from))
0d7e008e 4655 {
1245df60
R		 4656 rtx pat, src, dst;
4657 enum machine_mode mode;
4658
4659 pat = PATTERN (from);
4660 if (GET_CODE (pat) == PARALLEL)
4661 pat = XVECEXP (pat, 0, 0);
4662 src = SET_SRC (pat);
4663 dst = SET_DEST (pat);
4664 mode = GET_MODE (dst);
c17f53a8 4665
e938feb4
CB		 4666 /* GOT pcrelat setting comes in pair of
4667 mova .L8,r0
4668 mov.l .L8,r12
4669 instructions. (plus add r0,r12).
4670 Remember if we see one without the other. */
4671 if (GET_CODE (src) == UNSPEC && PIC_ADDR_P (XVECEXP (src, 0, 0)))
4672 last_got = last_got ? NULL_RTX : from;
4673 else if (PIC_ADDR_P (src))
4674 last_got = last_got ? NULL_RTX : from;
4675
c17f53a8
JW		 4676 /* We must explicitly check the mode, because sometimes the
4677 front end will generate code to load unsigned constants into
4678 HImode targets without properly sign extending them. */
225e4f43
R		 4679 if (mode == HImode
4680 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
00e94d65 4681 {
1245df60 4682 found_hi += 2;
00e94d65
RK		 4683 /* We put the short constants before the long constants, so
4684 we must count the length of short constants in the range
4685 for the long constants. */
4686 /* ??? This isn't optimal, but is easy to do. */
1245df60 4687 si_limit -= 2;
00e94d65 4688 }
0d7e008e 4689 else
1245df60 4690 {
fa5322fa
AO		 4691 /* We dump DF/DI constants before SF/SI ones, because
4692 the limit is the same, but the alignment requirements
4693 are higher. We may waste up to 4 additional bytes
4694 for alignment, and the DF/DI constant may have
24746a42 4695 another SF/SI constant placed before it. */
fa5322fa
AO		 4696 if (TARGET_SHCOMPACT
4697 && ! found_di
4698 && (mode == DFmode || mode == DImode))
4699 {
4700 found_di = 1;
4701 si_limit -= 8;
4702 }
33f7f353
JR		 4703 while (si_align > 2 && found_si + si_align - 2 > count_si)
4704 si_align >>= 1;
1245df60
R		 4705 if (found_si > count_si)
4706 count_si = found_si;
4707 found_si += GET_MODE_SIZE (mode);
4708 if (num_mova)
4709 si_limit -= GET_MODE_SIZE (mode);
4710 }
0d7e008e 4711 }
5325c0fa 4712
33f7f353 4713 if (mova_p (from))
1245df60 4714 {
4241ecb0 4715 switch (untangle_mova (&num_mova, &mova, from))
1245df60 4716 {
fc9c984d
KK		 4717 case 1:
4718 if (flag_pic)
4719 {
4720 rtx src = SET_SRC (PATTERN (from));
4721 if (GET_CODE (src) == CONST
4722 && GET_CODE (XEXP (src, 0)) == UNSPEC
4723 && XINT (XEXP (src, 0), 1) == UNSPEC_SYMOFF)
4724 last_symoff = from;
4725 }
4726 break;
4241ecb0
R		 4727 case 0: return find_barrier (0, 0, mova);
4728 case 2:
4729 {
4730 leading_mova = 0;
4731 barrier_before_mova
4732 = good_barrier ? good_barrier : found_barrier;
4733 }
4734 default: break;
1245df60
R		 4735 }
4736 if (found_si > count_si)
4737 count_si = found_si;
4738 }
f3536097 4739 else if (JUMP_TABLE_DATA_P (from))
1245df60 4740 {
4241ecb0
R		 4741 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4742 || (num_mova
4743 && (prev_nonnote_insn (from)
4744 == XEXP (MOVA_LABELREF (mova), 0))))
1245df60 4745 num_mova--;
10f4f635 4746 if (barrier_align (next_real_insn (from)) == align_jumps_log)
1245df60 4747 {
38e01259 4748 /* We have just passed the barrier in front of the
a0798779
R		 4749 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4750 the ADDR_DIFF_VEC is accessed as data, just like our pool
4751 constants, this is a good opportunity to accommodate what
4752 we have gathered so far.
1245df60
R		 4753 If we waited any longer, we could end up at a barrier in
4754 front of code, which gives worse cache usage for separated
4755 instruction / data caches. */
a0798779 4756 good_barrier = found_barrier;
1245df60
R		 4757 break;
4758 }
a0798779
R		 4759 else
4760 {
4761 rtx body = PATTERN (from);
4762 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4763 }
1245df60 4764 }
50ceefc2 4765 /* For the SH1, we generate alignments even after jumps-around-jumps. */
f3536097 4766 else if (JUMP_P (from)
50ceefc2 4767 && ! TARGET_SH2
3020190e 4768 && ! optimize_size)
50ceefc2 4769 new_align = 4;
5325c0fa 4770
9e3c399e
CB		 4771 /* There is a possibility that a bf is transformed into a bf/s by the
4772 delay slot scheduler. */
4773 if (JUMP_P (from) && !JUMP_TABLE_DATA_P (from)
4774 && get_attr_type (from) == TYPE_CBRANCH
4775 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (from)))) != SEQUENCE)
4776 inc += 2;
4777
0d7e008e 4778 if (found_si)
33f7f353 4779 {
50ceefc2 4780 count_si += inc;
33f7f353
JR		 4781 if (new_align > si_align)
4782 {
318881c0 4783 si_limit -= (count_si - 1) & (new_align - si_align);
33f7f353
JR		 4784 si_align = new_align;
4785 }
318881c0 4786 count_si = (count_si + new_align - 1) & -new_align;
33f7f353 4787 }
0d7e008e 4788 if (found_hi)
33f7f353 4789 {
50ceefc2 4790 count_hi += inc;
33f7f353
JR		 4791 if (new_align > hi_align)
4792 {
318881c0 4793 hi_limit -= (count_hi - 1) & (new_align - hi_align);
33f7f353
JR		 4794 hi_align = new_align;
4795 }
318881c0 4796 count_hi = (count_hi + new_align - 1) & -new_align;
33f7f353 4797 }
0d7e008e
SC		 4798 from = NEXT_INSN (from);
4799 }
4800
1245df60 4801 if (num_mova)
eda44c78
R		 4802 {
4803 if (leading_mova)
4804 {
4805 /* Try as we might, the leading mova is out of range. Change
4806 it into a load (which will become a pcload) and retry. */
078c8b08 4807 fixup_mova (mova);
eda44c78
R		 4808 return find_barrier (0, 0, mova);
4809 }
4810 else
4811 {
4812 /* Insert the constant pool table before the mova instruction,
4813 to prevent the mova label reference from going out of range. */
4814 from = mova;
4815 good_barrier = found_barrier = barrier_before_mova;
4816 }
4817 }
5325c0fa 4818
1245df60
R		 4819 if (found_barrier)
4820 {
33f7f353 4821 if (good_barrier && next_real_insn (found_barrier))
1245df60 4822 found_barrier = good_barrier;
1245df60
R		 4823 }
4824 else
b9654711 4825 {
8aa2a305
JW		 4826 /* We didn't find a barrier in time to dump our stuff,
4827 so we'll make one. */
0d7e008e 4828 rtx label = gen_label_rtx ();
8aa2a305 4829
fc9c984d
KK		 4830 /* Don't emit a constant table in the middle of insns for
4831 casesi_worker_2. This is a bit overkill but is enough
4832 because casesi_worker_2 wouldn't appear so frequently. */
4833 if (last_symoff)
4834 from = last_symoff;
4835
5dbcc9c0
RK		 4836 /* If we exceeded the range, then we must back up over the last
4837 instruction we looked at. Otherwise, we just need to undo the
4838 NEXT_INSN at the end of the loop. */
7a3cb3ab
KK		 4839 if (PREV_INSN (from) != orig
4840 && (count_hi > hi_limit || count_si > si_limit))
5dbcc9c0
RK		 4841 from = PREV_INSN (PREV_INSN (from));
4842 else
4843 from = PREV_INSN (from);
4844
e938feb4
CB		 4845 /* Don't emit a constant table int the middle of global pointer setting,
4846 since that that would move the addressing base GOT into another table.
4847 We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_
4848 in the pool anyway, so just move up the whole constant pool. */
4849 if (last_got)
4850 from = PREV_INSN (last_got);
4851
bd55b817
KK		 4852 /* Don't insert the constant pool table at the position which
4853 may be the landing pad. */
4854 if (flag_exceptions
4855 && CALL_P (from)
4856 && find_reg_note (from, REG_EH_REGION, NULL_RTX))
4857 from = PREV_INSN (from);
4858
8aa2a305
JW		 4859 /* Walk back to be just before any jump or label.
4860 Putting it before a label reduces the number of times the branch
4861 around the constant pool table will be hit. Putting it before
4862 a jump makes it more likely that the bra delay slot will be
4863 filled. */
f3536097
SZ		 4864 while (NOTE_P (from) || JUMP_P (from)
4865 || LABEL_P (from))
8aa2a305
JW		 4866 from = PREV_INSN (from);
4867
5969b52d
KK		 4868 /* Make sure we do not split between a call and its corresponding
4869 CALL_ARG_LOCATION note. */
4870 if (CALL_P (from))
4871 {
4872 rtx next = NEXT_INSN (from);
4873 if (next && NOTE_P (next)
4874 && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)
4875 from = next;
4876 }
4877
0d7e008e
SC		 4878 from = emit_jump_insn_after (gen_jump (label), from);
4879 JUMP_LABEL (from) = label;
e081ed26 4880 LABEL_NUSES (label) = 1;
0d7e008e
SC		 4881 found_barrier = emit_barrier_after (from);
4882 emit_label_after (label, found_barrier);
b9654711 4883 }
b9654711 4884
8aa2a305 4885 return found_barrier;
0d7e008e 4886}
b9654711 4887
4787bce0
JW		 4888/* If the instruction INSN is implemented by a special function, and we can
4889 positively find the register that is used to call the sfunc, and this
4890 register is not used anywhere else in this instruction - except as the
4891 destination of a set, return this register; else, return 0. */
1245df60 4892rtx
cf277499 4893sfunc_uses_reg (rtx insn)
4787bce0
JW		 4894{
4895 int i;
4896 rtx pattern, part, reg_part, reg;
4897
f3536097 4898 if (!NONJUMP_INSN_P (insn))
4787bce0
JW		 4899 return 0;
4900 pattern = PATTERN (insn);
4901 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4902 return 0;
4903
4904 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4905 {
4906 part = XVECEXP (pattern, 0, i);
1245df60 4907 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4787bce0
JW		 4908 reg_part = part;
4909 }
4910 if (! reg_part)
4911 return 0;
4912 reg = XEXP (reg_part, 0);
4913 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4914 {
4915 part = XVECEXP (pattern, 0, i);
225e4f43 4916 if (part == reg_part || GET_CODE (part) == CLOBBER)
4787bce0
JW		 4917 continue;
4918 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
f3536097 4919 && REG_P (SET_DEST (part)))
4787bce0
JW		 4920 ? SET_SRC (part) : part)))
4921 return 0;
4922 }
4923 return reg;
4924}
4925
933c3ba3
JW		 4926/* See if the only way in which INSN uses REG is by calling it, or by
4927 setting it while calling it. Set *SET to a SET rtx if the register
4928 is set by INSN. */
4929
4930static int
cf277499 4931noncall_uses_reg (rtx reg, rtx insn, rtx *set)
933c3ba3 4932{
4787bce0 4933 rtx pattern, reg2;
933c3ba3
JW		 4934
4935 *set = NULL_RTX;
4936
4787bce0
JW		 4937 reg2 = sfunc_uses_reg (insn);
4938 if (reg2 && REGNO (reg2) == REGNO (reg))
4939 {
4940 pattern = single_set (insn);
4941 if (pattern
f3536097 4942 && REG_P (SET_DEST (pattern))
4787bce0
JW		 4943 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4944 *set = pattern;
4945 return 0;
4946 }
f3536097 4947 if (!CALL_P (insn))
933c3ba3
JW		 4948 {
4949 /* We don't use rtx_equal_p because we don't care if the mode is
4950 different. */
4951 pattern = single_set (insn);
4952 if (pattern
f3536097 4953 && REG_P (SET_DEST (pattern))
933c3ba3
JW		 4954 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4955 {
4787bce0
JW		 4956 rtx par, part;
4957 int i;
4958
933c3ba3 4959 *set = pattern;
4787bce0
JW		 4960 par = PATTERN (insn);
4961 if (GET_CODE (par) == PARALLEL)
4962 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4963 {
4964 part = XVECEXP (par, 0, i);
4965 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4966 return 1;
4967 }
4968 return reg_mentioned_p (reg, SET_SRC (pattern));
933c3ba3
JW		 4969 }
4970
4971 return 1;
4972 }
4973
4974 pattern = PATTERN (insn);
4975
4976 if (GET_CODE (pattern) == PARALLEL)
4977 {
4978 int i;
4979
4980 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4981 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4982 return 1;
4983 pattern = XVECEXP (pattern, 0, 0);
4984 }
4985
4986 if (GET_CODE (pattern) == SET)
4987 {
4988 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4989 {
4990 /* We don't use rtx_equal_p, because we don't care if the
4991 mode is different. */
f3536097 4992 if (!REG_P (SET_DEST (pattern))
933c3ba3
JW		 4993 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4994 return 1;
4995
4996 *set = pattern;
4997 }
4998
4999 pattern = SET_SRC (pattern);
5000 }
5001
5002 if (GET_CODE (pattern) != CALL
f3536097 5003 || !MEM_P (XEXP (pattern, 0))
933c3ba3
JW		 5004 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
5005 return 1;
5006
5007 return 0;
5008}
5009
1245df60
R		 5010/* Given a X, a pattern of an insn or a part of it, return a mask of used
5011 general registers. Bits 0..15 mean that the respective registers
5012 are used as inputs in the instruction. Bits 16..31 mean that the
5013 registers 0..15, respectively, are used as outputs, or are clobbered.
5014 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
5015int
cf277499 5016regs_used (rtx x, int is_dest)
1245df60
R		 5017{
5018 enum rtx_code code;
6f7d635c 5019 const char *fmt;
1245df60
R		 5020 int i, used = 0;
5021
5022 if (! x)
5023 return used;
5024 code = GET_CODE (x);
5025 switch (code)
5026 {
5027 case REG:
5028 if (REGNO (x) < 16)
5029 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
5030 << (REGNO (x) + is_dest));
5031 return 0;
5032 case SUBREG:
5033 {
5034 rtx y = SUBREG_REG (x);
f676971a 5035
f3536097 5036 if (!REG_P (y))
1245df60
R		 5037 break;
5038 if (REGNO (y) < 16)
5039 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
ddef6bc7
JJ		 5040 << (REGNO (y) +
5041 subreg_regno_offset (REGNO (y),
5042 GET_MODE (y),
5043 SUBREG_BYTE (x),
5044 GET_MODE (x)) + is_dest));
1245df60
R		 5045 return 0;
5046 }
5047 case SET:
5048 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
5049 case RETURN:
5050 /* If there was a return value, it must have been indicated with USE. */
5051 return 0x00ffff00;
5052 case CLOBBER:
5053 is_dest = 1;
5054 break;
5055 case MEM:
5056 is_dest = 0;
5057 break;
5058 case CALL:
5059 used |= 0x00ff00f0;
5060 break;
318881c0
KG		 5061 default:
5062 break;
1245df60
R		 5063 }
5064
5065 fmt = GET_RTX_FORMAT (code);
5066
5067 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5068 {
5069 if (fmt[i] == 'E')
5070 {
5071 register int j;
5072 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5073 used |= regs_used (XVECEXP (x, i, j), is_dest);
5074 }
5075 else if (fmt[i] == 'e')
5076 used |= regs_used (XEXP (x, i), is_dest);
5077 }
5078 return used;
5079}
5080
5081/* Create an instruction that prevents redirection of a conditional branch
956d6950 5082 to the destination of the JUMP with address ADDR.
1245df60
R		 5083 If the branch needs to be implemented as an indirect jump, try to find
5084 a scratch register for it.
5085 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
5086 If any preceding insn that doesn't fit into a delay slot is good enough,
5087 pass 1. Pass 2 if a definite blocking insn is needed.
5088 -1 is used internally to avoid deep recursion.
5089 If a blocking instruction is made or recognized, return it. */
f676971a 5090
1245df60 5091static rtx
cf277499 5092gen_block_redirect (rtx jump, int addr, int need_block)
1245df60
R		 5093{
5094 int dead = 0;
5095 rtx prev = prev_nonnote_insn (jump);
5096 rtx dest;
5097
5098 /* First, check if we already have an instruction that satisfies our need. */
f3536097 5099 if (prev && NONJUMP_INSN_P (prev) && ! INSN_DELETED_P (prev))
1245df60
R		 5100 {
5101 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
5102 return prev;
5103 if (GET_CODE (PATTERN (prev)) == USE
5104 || GET_CODE (PATTERN (prev)) == CLOBBER
5105 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5106 prev = jump;
5107 else if ((need_block &= ~1) < 0)
5108 return prev;
5109 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
5110 need_block = 0;
5111 }
f9654065
R		 5112 if (GET_CODE (PATTERN (jump)) == RETURN)
5113 {
5114 if (! need_block)
5115 return prev;
5116 /* Reorg even does nasty things with return insns that cause branches
5117 to go out of range - see find_end_label and callers. */
a556fd39 5118 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
f9654065 5119 }
1245df60
R		 5120 /* We can't use JUMP_LABEL here because it might be undefined
5121 when not optimizing. */
5122 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
5123 /* If the branch is out of range, try to find a scratch register for it. */
5124 if (optimize
11f9ed1a
KG		 5125 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
5126 > 4092 + 4098))
1245df60
R		 5127 {
5128 rtx scan;
5129 /* Don't look for the stack pointer as a scratch register,
956d6950 5130 it would cause trouble if an interrupt occurred. */
0a2aaacc 5131 unsigned attempt = 0x7fff, used;
1245df60 5132 int jump_left = flag_expensive_optimizations + 1;
f676971a 5133
1245df60
R		 5134 /* It is likely that the most recent eligible instruction is wanted for
5135 the delay slot. Therefore, find out which registers it uses, and
5136 try to avoid using them. */
f676971a 5137
318881c0 5138 for (scan = jump; (scan = PREV_INSN (scan)); )
1245df60
R		 5139 {
5140 enum rtx_code code;
5141
5142 if (INSN_DELETED_P (scan))
5143 continue;
5144 code = GET_CODE (scan);
5145 if (code == CODE_LABEL || code == JUMP_INSN)
5146 break;
5147 if (code == INSN
5148 && GET_CODE (PATTERN (scan)) != USE
5149 && GET_CODE (PATTERN (scan)) != CLOBBER
5150 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
5151 {
0a2aaacc 5152 attempt &= ~regs_used (PATTERN (scan), 0);
1245df60
R		 5153 break;
5154 }
5155 }
eda44c78
R		 5156 for (used = dead = 0, scan = JUMP_LABEL (jump);
5157 (scan = NEXT_INSN (scan)); )
1245df60
R		 5158 {
5159 enum rtx_code code;
5160
5161 if (INSN_DELETED_P (scan))
5162 continue;
5163 code = GET_CODE (scan);
ec8e098d 5164 if (INSN_P (scan))
1245df60
R		 5165 {
5166 used |= regs_used (PATTERN (scan), 0);
5167 if (code == CALL_INSN)
5168 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
5169 dead |= (used >> 16) & ~used;
0a2aaacc 5170 if (dead & attempt)
1245df60 5171 {
0a2aaacc 5172 dead &= attempt;
1245df60
R		 5173 break;
5174 }
5175 if (code == JUMP_INSN)
eda44c78
R		 5176 {
5177 if (jump_left-- && simplejump_p (scan))
5178 scan = JUMP_LABEL (scan);
5179 else
5180 break;
5181 }
1245df60
R		 5182 }
5183 }
5184 /* Mask out the stack pointer again, in case it was
5185 the only 'free' register we have found. */
5186 dead &= 0x7fff;
5187 }
5188 /* If the immediate destination is still in range, check for possible
5189 threading with a jump beyond the delay slot insn.
5190 Don't check if we are called recursively; the jump has been or will be
956d6950 5191 checked in a different invocation then. */
f676971a 5192
1245df60
R		 5193 else if (optimize && need_block >= 0)
5194 {
5195 rtx next = next_active_insn (next_active_insn (dest));
f3536097 5196 if (next && JUMP_P (next)
1245df60 5197 && GET_CODE (PATTERN (next)) == SET
ddf8ec7e 5198 && recog_memoized (next) == CODE_FOR_jump_compact)
1245df60
R		 5199 {
5200 dest = JUMP_LABEL (next);
5201 if (dest
11f9ed1a 5202 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
9d98a694
AO		 5203 > 4092 + 4098))
5204 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
1245df60
R		 5205 }
5206 }
5207
5208 if (dead)
5209 {
c5c76735 5210 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
1245df60
R		 5211
5212 /* It would be nice if we could convert the jump into an indirect
956d6950 5213 jump / far branch right now, and thus exposing all constituent
1245df60
R		 5214 instructions to further optimization. However, reorg uses
5215 simplejump_p to determine if there is an unconditional jump where
5216 it should try to schedule instructions from the target of the
5217 branch; simplejump_p fails for indirect jumps even if they have
5218 a JUMP_LABEL. */
5219 rtx insn = emit_insn_before (gen_indirect_jump_scratch
826159e5
KK		 5220 (reg, GEN_INT (unspec_bbr_uid++)),
5221 jump);
10f4f635
R		 5222 /* ??? We would like this to have the scope of the jump, but that
5223 scope will change when a delay slot insn of an inner scope is added.
5224 Hence, after delay slot scheduling, we'll have to expect
5225 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
5226 the jump. */
f676971a 5227
86143cb4 5228 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
1245df60
R		 5229 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
5230 return insn;
5231 }
5232 else if (need_block)
5233 /* We can't use JUMP_LABEL here because it might be undefined
5234 when not optimizing. */
5235 return emit_insn_before (gen_block_branch_redirect
826159e5
KK		 5236 (GEN_INT (unspec_bbr_uid++)),
5237 jump);
1245df60
R		 5238 return prev;
5239}
5240
5241#define CONDJUMP_MIN -252
5242#define CONDJUMP_MAX 262
5243struct far_branch
5244{
5245 /* A label (to be placed) in front of the jump
5246 that jumps to our ultimate destination. */
5247 rtx near_label;
5248 /* Where we are going to insert it if we cannot move the jump any farther,
5249 or the jump itself if we have picked up an existing jump. */
5250 rtx insert_place;
5251 /* The ultimate destination. */
5252 rtx far_label;
5253 struct far_branch *prev;
5254 /* If the branch has already been created, its address;
5255 else the address of its first prospective user. */
5256 int address;
5257};
5258
cf277499 5259static void gen_far_branch (struct far_branch *);
1245df60 5260enum mdep_reorg_phase_e mdep_reorg_phase;
c5b9ef02 5261static void
cf277499 5262gen_far_branch (struct far_branch *bp)
1245df60
R		 5263{
5264 rtx insn = bp->insert_place;
5265 rtx jump;
5266 rtx label = gen_label_rtx ();
f5b9e7c9 5267 int ok;
1245df60
R		 5268
5269 emit_label_after (label, insn);
5270 if (bp->far_label)
5271 {
5272 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
5273 LABEL_NUSES (bp->far_label)++;
5274 }
5275 else
5276 jump = emit_jump_insn_after (gen_return (), insn);
225e4f43
R		 5277 /* Emit a barrier so that reorg knows that any following instructions
5278 are not reachable via a fall-through path.
fae778eb 5279 But don't do this when not optimizing, since we wouldn't suppress the
225e4f43
R		 5280 alignment for the barrier then, and could end up with out-of-range
5281 pc-relative loads. */
5282 if (optimize)
5283 emit_barrier_after (jump);
1245df60
R		 5284 emit_label_after (bp->near_label, insn);
5285 JUMP_LABEL (jump) = bp->far_label;
f5b9e7c9
NS		 5286 ok = invert_jump (insn, label, 1);
5287 gcc_assert (ok);
5288
f9654065
R		 5289 /* If we are branching around a jump (rather than a return), prevent
5290 reorg from using an insn from the jump target as the delay slot insn -
5291 when reorg did this, it pessimized code (we rather hide the delay slot)
5292 and it could cause branches to go out of range. */
5293 if (bp->far_label)
5294 (emit_insn_after
5295 (gen_stuff_delay_slot
826159e5 5296 (GEN_INT (unspec_bbr_uid++),
f9654065
R		 5297 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
5298 insn));
1245df60
R		 5299 /* Prevent reorg from undoing our splits. */
5300 gen_block_redirect (jump, bp->address += 2, 2);
5301}
5302
1245df60
R		 5303/* Fix up ADDR_DIFF_VECs. */
5304void
cf277499 5305fixup_addr_diff_vecs (rtx first)
1245df60
R		 5306{
5307 rtx insn;
33f7f353 5308
1245df60
R		 5309 for (insn = first; insn; insn = NEXT_INSN (insn))
5310 {
eb3881bf 5311 rtx vec_lab, pat, prev, prevpat, x, braf_label;
1245df60 5312
f3536097 5313 if (!JUMP_P (insn)
1245df60
R		 5314 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
5315 continue;
5316 pat = PATTERN (insn);
33f7f353 5317 vec_lab = XEXP (XEXP (pat, 0), 0);
1245df60 5318
33f7f353
JR		 5319 /* Search the matching casesi_jump_2. */
5320 for (prev = vec_lab; ; prev = PREV_INSN (prev))
1245df60 5321 {
f3536097 5322 if (!JUMP_P (prev))
33f7f353
JR		 5323 continue;
5324 prevpat = PATTERN (prev);
5325 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
5326 continue;
5327 x = XVECEXP (prevpat, 0, 1);
5328 if (GET_CODE (x) != USE)
5329 continue;
5330 x = XEXP (x, 0);
5331 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
5332 break;
1245df60 5333 }
157371cf
AO		 5334 /* FIXME: This is a bug in the optimizer, but it seems harmless
5335 to just avoid panicing. */
5336 if (!prev)
5337 continue;
eb3881bf
R		 5338
5339 /* Emit the reference label of the braf where it belongs, right after
5340 the casesi_jump_2 (i.e. braf). */
5341 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
5342 emit_label_after (braf_label, prev);
5343
33f7f353
JR		 5344 /* Fix up the ADDR_DIF_VEC to be relative
5345 to the reference address of the braf. */
eb3881bf 5346 XEXP (XEXP (pat, 0), 0) = braf_label;
1245df60 5347 }
1245df60
R		 5348}
5349
33f7f353
JR		 5350/* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5351 a barrier. Return the base 2 logarithm of the desired alignment. */
1245df60 5352int
cf277499 5353barrier_align (rtx barrier_or_label)
1245df60 5354{
33f7f353 5355 rtx next = next_real_insn (barrier_or_label), pat, prev;
3a8699c7 5356 int slot, credit, jump_to_next = 0;
f676971a 5357
33f7f353 5358 if (! next)
1245df60 5359 return 0;
1245df60 5360
33f7f353 5361 pat = PATTERN (next);
1245df60 5362
33f7f353
JR		 5363 if (GET_CODE (pat) == ADDR_DIFF_VEC)
5364 return 2;
1245df60 5365
4773afa4 5366 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
33f7f353
JR		 5367 /* This is a barrier in front of a constant table. */
5368 return 0;
5369
5370 prev = prev_real_insn (barrier_or_label);
5371 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
1245df60 5372 {
33f7f353
JR		 5373 pat = PATTERN (prev);
5374 /* If this is a very small table, we want to keep the alignment after
5375 the table to the minimum for proper code alignment. */
3020190e 5376 return ((optimize_size
d042370e 5377 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
832a3292 5378 <= (unsigned) 1 << (CACHE_LOG - 2)))
10f4f635 5379 ? 1 << TARGET_SHMEDIA : align_jumps_log);
1245df60 5380 }
33f7f353 5381
3020190e 5382 if (optimize_size)
33f7f353
JR		 5383 return 0;
5384
4d070fd3 5385 if (! TARGET_SH2 || ! optimize)
10f4f635 5386 return align_jumps_log;
33f7f353 5387
225e4f43
R		 5388 /* When fixing up pcloads, a constant table might be inserted just before
5389 the basic block that ends with the barrier. Thus, we can't trust the
5390 instruction lengths before that. */
5391 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
1245df60 5392 {
225e4f43
R		 5393 /* Check if there is an immediately preceding branch to the insn beyond
5394 the barrier. We must weight the cost of discarding useful information
5395 from the current cache line when executing this branch and there is
5396 an alignment, against that of fetching unneeded insn in front of the
5397 branch target when there is no alignment. */
5398
f676971a
EC		 5399 /* There are two delay_slot cases to consider. One is the simple case
5400 where the preceding branch is to the insn beyond the barrier (simple
5401 delay slot filling), and the other is where the preceding branch has
5402 a delay slot that is a duplicate of the insn after the barrier
5403 (fill_eager_delay_slots) and the branch is to the insn after the insn
b1b41fe4
CP		 5404 after the barrier. */
5405
225e4f43
R		 5406 /* PREV is presumed to be the JUMP_INSN for the barrier under
5407 investigation. Skip to the insn before it. */
5408 prev = prev_real_insn (prev);
5409
c5b9ef02 5410 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
f3536097 5411 credit >= 0 && prev && NONJUMP_INSN_P (prev);
225e4f43
R		 5412 prev = prev_real_insn (prev))
5413 {
b1b41fe4 5414 jump_to_next = 0;
225e4f43
R		 5415 if (GET_CODE (PATTERN (prev)) == USE
5416 || GET_CODE (PATTERN (prev)) == CLOBBER)
5417 continue;
5418 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
b1b41fe4
CP		 5419 {
5420 prev = XVECEXP (PATTERN (prev), 0, 1);
f676971a 5421 if (INSN_UID (prev) == INSN_UID (next))
b1b41fe4
CP		 5422 {
5423 /* Delay slot was filled with insn at jump target. */
5424 jump_to_next = 1;
5425 continue;
5426 }
5427 }
5428
225e4f43
R		 5429 if (slot &&
5430 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5431 slot = 0;
5432 credit -= get_attr_length (prev);
5433 }
5434 if (prev
f3536097 5435 && JUMP_P (prev)
2b9d17c7
AH		 5436 && JUMP_LABEL (prev))
5437 {
5438 rtx x;
300c5453 5439 if (jump_to_next
2b9d17c7 5440 || next_real_insn (JUMP_LABEL (prev)) == next
1594c6bc
AO		 5441 /* If relax_delay_slots() decides NEXT was redundant
5442 with some previous instruction, it will have
5443 redirected PREV's jump to the following insn. */
5d291213 5444 || JUMP_LABEL (prev) == next_nonnote_insn (next)
300c5453
AO		 5445 /* There is no upper bound on redundant instructions
5446 that might have been skipped, but we must not put an
2b9d17c7 5447 alignment where none had been before. */
f676971a
EC		 5448 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
5449 (INSN_P (x)
2b9d17c7 5450 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
9959c8c7
R		 5451 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
5452 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
2b9d17c7
AH		 5453 {
5454 rtx pat = PATTERN (prev);
5455 if (GET_CODE (pat) == PARALLEL)
300c5453 5456 pat = XVECEXP (pat, 0, 0);
2b9d17c7
AH		 5457 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
5458 return 0;
5459 }
300c5453 5460 }
33f7f353 5461 }
f676971a 5462
10f4f635 5463 return align_jumps_log;
1245df60
R		 5464}
5465
2148624a
R		 5466/* If we are inside a phony loop, almost any kind of label can turn up as the
5467 first one in the loop. Aligning a braf label causes incorrect switch
5468 destination addresses; we can detect braf labels because they are
5469 followed by a BARRIER.
5470 Applying loop alignment to small constant or switch tables is a waste
5471 of space, so we suppress this too. */
5472int
cf277499 5473sh_loop_align (rtx label)
2148624a
R		 5474{
5475 rtx next = label;
5476
5477 do
5478 next = next_nonnote_insn (next);
f3536097 5479 while (next && LABEL_P (next));
2148624a
R		 5480
5481 if (! next
2c3c49de 5482 || ! INSN_P (next)
2148624a
R		 5483 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
5484 || recog_memoized (next) == CODE_FOR_consttable_2)
5485 return 0;
fa5322fa 5486
10f4f635 5487 return align_loops_log;
2148624a
R		 5488}
5489
18dbd950 5490/* Do a final pass over the function, just before delayed branch
933c3ba3 5491 scheduling. */
b9654711 5492
18dbd950 5493static void
cf277499 5494sh_reorg (void)
0d7e008e 5495{
18dbd950 5496 rtx first, insn, mova = NULL_RTX;
1245df60 5497 int num_mova;
c5c76735
JL		 5498 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
5499 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
8aa2a305 5500
18dbd950 5501 first = get_insns ();
4241ecb0 5502 max_labelno_before_reorg = max_label_num ();
18dbd950 5503
cb51ecd2
AO		 5504 /* We must split call insns before introducing `mova's. If we're
5505 optimizing, they'll have already been split. Otherwise, make
5506 sure we don't split them too late. */
5507 if (! optimize)
6f862f2f 5508 split_all_insns_noflow ();
cb51ecd2 5509
fa5322fa
AO		 5510 if (TARGET_SHMEDIA)
5511 return;
5512
933c3ba3
JW		 5513 /* If relaxing, generate pseudo-ops to associate function calls with
5514 the symbols they call. It does no harm to not generate these
5515 pseudo-ops. However, when we can generate them, it enables to
5516 linker to potentially relax the jsr to a bsr, and eliminate the
5517 register load and, possibly, the constant pool entry. */
5518
1245df60 5519 mdep_reorg_phase = SH_INSERT_USES_LABELS;
933c3ba3
JW		 5520 if (TARGET_RELAX)
5521 {
cf7c4aa6
HPN		 5522 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5523 own purposes. This works because none of the remaining passes
933c3ba3
JW		 5524 need to look at them.
5525
5526 ??? But it may break in the future. We should use a machine
5527 dependent REG_NOTE, or some other approach entirely. */
5528 for (insn = first; insn; insn = NEXT_INSN (insn))
5529 {
2c3c49de 5530 if (INSN_P (insn))
933c3ba3
JW		 5531 {
5532 rtx note;
5533
cf7c4aa6
HPN		 5534 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
5535 NULL_RTX)) != 0)
933c3ba3
JW		 5536 remove_note (insn, note);
5537 }
5538 }
5539
5540 for (insn = first; insn; insn = NEXT_INSN (insn))
5541 {
5542 rtx pattern, reg, link, set, scan, dies, label;
5543 int rescan = 0, foundinsn = 0;
5544
f3536097 5545 if (CALL_P (insn))
4787bce0
JW		 5546 {
5547 pattern = PATTERN (insn);
933c3ba3 5548
4787bce0
JW		 5549 if (GET_CODE (pattern) == PARALLEL)
5550 pattern = XVECEXP (pattern, 0, 0);
5551 if (GET_CODE (pattern) == SET)
5552 pattern = SET_SRC (pattern);
933c3ba3 5553
4787bce0 5554 if (GET_CODE (pattern) != CALL
f3536097 5555 || !MEM_P (XEXP (pattern, 0)))
4787bce0 5556 continue;
933c3ba3 5557
4787bce0
JW		 5558 reg = XEXP (XEXP (pattern, 0), 0);
5559 }
5560 else
5561 {
5562 reg = sfunc_uses_reg (insn);
5563 if (! reg)
5564 continue;
5565 }
933c3ba3 5566
f3536097 5567 if (!REG_P (reg))
933c3ba3
JW		 5568 continue;
5569
6fb5fa3c
DB		 5570 /* Try scanning backward to find where the register is set. */
5571 link = NULL;
5572 for (scan = PREV_INSN (insn);
f3536097 5573 scan && !LABEL_P (scan);
6fb5fa3c 5574 scan = PREV_INSN (scan))
933c3ba3 5575 {
6fb5fa3c
DB		 5576 if (! INSN_P (scan))
5577 continue;
933c3ba3 5578
6fb5fa3c
DB		 5579 if (! reg_mentioned_p (reg, scan))
5580 continue;
933c3ba3 5581
6fb5fa3c
DB		 5582 if (noncall_uses_reg (reg, scan, &set))
5583 break;
933c3ba3 5584
6fb5fa3c
DB		 5585 if (set)
5586 {
5587 link = scan;
5588 break;
933c3ba3
JW		 5589 }
5590 }
5591
5592 if (! link)
5593 continue;
5594
5595 /* The register is set at LINK. */
5596
5597 /* We can only optimize the function call if the register is
5598 being set to a symbol. In theory, we could sometimes
5599 optimize calls to a constant location, but the assembler
5600 and linker do not support that at present. */
5601 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5602 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5603 continue;
5604
5605 /* Scan forward from LINK to the place where REG dies, and
5606 make sure that the only insns which use REG are
5607 themselves function calls. */
5608
c1e8e6bd
JW		 5609 /* ??? This doesn't work for call targets that were allocated
5610 by reload, since there may not be a REG_DEAD note for the
5611 register. */
5612
933c3ba3
JW		 5613 dies = NULL_RTX;
5614 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5615 {
5616 rtx scanset;
5617
c1e8e6bd
JW		 5618 /* Don't try to trace forward past a CODE_LABEL if we haven't
5619 seen INSN yet. Ordinarily, we will only find the setting insn
6fb5fa3c 5620 if it is in the same basic block. However,
c1e8e6bd
JW		 5621 cross-jumping can insert code labels in between the load and
5622 the call, and can result in situations where a single call
5623 insn may have two targets depending on where we came from. */
5624
f3536097 5625 if (LABEL_P (scan) && ! foundinsn)
c1e8e6bd
JW		 5626 break;
5627
2c3c49de 5628 if (! INSN_P (scan))
933c3ba3
JW		 5629 continue;
5630
5631 /* Don't try to trace forward past a JUMP. To optimize
5632 safely, we would have to check that all the
c1e8e6bd 5633 instructions at the jump destination did not use REG. */
933c3ba3 5634
f3536097 5635 if (JUMP_P (scan))
933c3ba3
JW		 5636 break;
5637
5638 if (! reg_mentioned_p (reg, scan))
5639 continue;
5640
5641 if (noncall_uses_reg (reg, scan, &scanset))
5642 break;
5643
5644 if (scan == insn)
5645 foundinsn = 1;
5646
4787bce0 5647 if (scan != insn
f3536097 5648 && (CALL_P (scan) || sfunc_uses_reg (scan)))
933c3ba3
JW		 5649 {
5650 /* There is a function call to this register other
5651 than the one we are checking. If we optimize
5652 this call, we need to rescan again below. */
5653 rescan = 1;
5654 }
5655
5656 /* ??? We shouldn't have to worry about SCANSET here.
5657 We should just be able to check for a REG_DEAD note
5658 on a function call. However, the REG_DEAD notes are
5659 apparently not dependable around libcalls; c-torture
5660 execute/920501-2 is a test case. If SCANSET is set,
5661 then this insn sets the register, so it must have
5662 died earlier. Unfortunately, this will only handle
5663 the cases in which the register is, in fact, set in a
5664 later insn. */
5665
5666 /* ??? We shouldn't have to use FOUNDINSN here.
6fb5fa3c
DB		 5667 This dates back to when we used LOG_LINKS to find
5668 the most recent insn which sets the register. */
933c3ba3
JW		 5669
5670 if (foundinsn
5671 && (scanset
5672 || find_reg_note (scan, REG_DEAD, reg)))
5673 {
5674 dies = scan;
5675 break;
5676 }
5677 }
5678
5679 if (! dies)
5680 {
5681 /* Either there was a branch, or some insn used REG
5682 other than as a function call address. */
5683 continue;
5684 }
5685
cf7c4aa6
HPN		 5686 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5687 on the insn which sets the register, and on each call insn
5688 which uses the register. In final_prescan_insn we look for
5689 the REG_LABEL_OPERAND notes, and output the appropriate label
933c3ba3
JW		 5690 or pseudo-op. */
5691
5692 label = gen_label_rtx ();
65c5f2a6
ILT		 5693 add_reg_note (link, REG_LABEL_OPERAND, label);
5694 add_reg_note (insn, REG_LABEL_OPERAND, label);
933c3ba3
JW		 5695 if (rescan)
5696 {
5697 scan = link;
5698 do
5699 {
4787bce0
JW		 5700 rtx reg2;
5701
933c3ba3
JW		 5702 scan = NEXT_INSN (scan);
5703 if (scan != insn
f3536097 5704 && ((CALL_P (scan)
4787bce0
JW		 5705 && reg_mentioned_p (reg, scan))
5706 || ((reg2 = sfunc_uses_reg (scan))
5707 && REGNO (reg2) == REGNO (reg))))
65c5f2a6 5708 add_reg_note (scan, REG_LABEL_OPERAND, label);
933c3ba3
JW		 5709 }
5710 while (scan != dies);
5711 }
5712 }
5713 }
5714
33f7f353
JR		 5715 if (TARGET_SH2)
5716 fixup_addr_diff_vecs (first);
1245df60
R		 5717
5718 if (optimize)
5719 {
1245df60
R		 5720 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5721 shorten_branches (first);
5722 }
6dd3c0a5 5723
933c3ba3
JW		 5724 /* Scan the function looking for move instructions which have to be
5725 changed to pc-relative loads and insert the literal tables. */
6dd3c0a5
SB		 5726 label_ref_list_pool = create_alloc_pool ("label references list",
5727 sizeof (struct label_ref_list_d),
5728 30);
1245df60
R		 5729 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5730 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
0d7e008e 5731 {
1245df60
R		 5732 if (mova_p (insn))
5733 {
078c8b08
R		 5734 /* ??? basic block reordering can move a switch table dispatch
5735 below the switch table. Check if that has happened.
5736 We only have the addresses available when optimizing; but then,
5737 this check shouldn't be needed when not optimizing. */
4241ecb0 5738 if (!untangle_mova (&num_mova, &mova, insn))
078c8b08 5739 {
4241ecb0
R		 5740 insn = mova;
5741 num_mova = 0;
078c8b08 5742 }
1245df60 5743 }
f3536097 5744 else if (JUMP_P (insn)
1245df60 5745 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
4241ecb0
R		 5746 && num_mova
5747 /* ??? loop invariant motion can also move a mova out of a
5748 loop. Since loop does this code motion anyway, maybe we
5749 should wrap UNSPEC_MOVA into a CONST, so that reload can
5750 move it back. */
5751 && ((num_mova > 1
5752 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5753 || (prev_nonnote_insn (insn)
5754 == XEXP (MOVA_LABELREF (mova), 0))))
1245df60
R		 5755 {
5756 rtx scan;
5757 int total;
5758
5759 num_mova--;
5760
5761 /* Some code might have been inserted between the mova and
5762 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5763 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
33f7f353 5764 total += get_attr_length (scan);
1245df60
R		 5765
5766 /* range of mova is 1020, add 4 because pc counts from address of
5767 second instruction after this one, subtract 2 in case pc is 2
5768 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
956d6950 5769 cancels out with alignment effects of the mova itself. */
1245df60
R		 5770 if (total > 1022)
5771 {
5772 /* Change the mova into a load, and restart scanning
5773 there. broken_move will then return true for mova. */
078c8b08 5774 fixup_mova (mova);
1245df60
R		 5775 insn = mova;
5776 }
5777 }
078c8b08 5778 if (broken_move (insn)
f3536097 5779 || (NONJUMP_INSN_P (insn)
078c8b08 5780 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
0d7e008e 5781 {
0d7e008e 5782 rtx scan;
8aa2a305
JW		 5783 /* Scan ahead looking for a barrier to stick the constant table
5784 behind. */
1245df60 5785 rtx barrier = find_barrier (num_mova, mova, insn);
3a8699c7 5786 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
078c8b08 5787 int need_aligned_label = 0;
b9654711 5788
1245df60
R		 5789 if (num_mova && ! mova_p (mova))
5790 {
5791 /* find_barrier had to change the first mova into a
5792 pcload; thus, we have to start with this new pcload. */
5793 insn = mova;
5794 num_mova = 0;
5795 }
16bea517 5796 /* Now find all the moves between the points and modify them. */
0d7e008e
SC		 5797 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5798 {
f3536097 5799 if (LABEL_P (scan))
1245df60 5800 last_float = 0;
f3536097 5801 if (NONJUMP_INSN_P (scan)
078c8b08
R		 5802 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5803 need_aligned_label = 1;
0d7e008e
SC		 5804 if (broken_move (scan))
5805 {
e577c183
JR		 5806 rtx *patp = &PATTERN (scan), pat = *patp;
5807 rtx src, dst;
0d7e008e 5808 rtx lab;
0d7e008e 5809 rtx newsrc;
e577c183
JR		 5810 enum machine_mode mode;
5811
5812 if (GET_CODE (pat) == PARALLEL)
5813 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5814 src = SET_SRC (pat);
5815 dst = SET_DEST (pat);
5816 mode = GET_MODE (dst);
0d7e008e 5817
225e4f43
R		 5818 if (mode == SImode && hi_const (src)
5819 && REGNO (dst) != FPUL_REG)
0d7e008e 5820 {
23ed92ca 5821 int offset = 0;
8aa2a305 5822
0d7e008e 5823 mode = HImode;
d3ae8277 5824 while (GET_CODE (dst) == SUBREG)
23ed92ca 5825 {
ddef6bc7
JJ		 5826 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5827 GET_MODE (SUBREG_REG (dst)),
5828 SUBREG_BYTE (dst),
5829 GET_MODE (dst));
23ed92ca
JW		 5830 dst = SUBREG_REG (dst);
5831 }
c5c76735 5832 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
0d7e008e 5833 }
f3536097 5834 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
1245df60 5835 {
b8794099 5836 /* This must be an insn that clobbers r0. */
0f2b41b2
AO		 5837 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5838 XVECLEN (PATTERN (scan), 0)
5839 - 1);
5840 rtx clobber = *clobberp;
b8794099 5841
f5b9e7c9
NS		 5842 gcc_assert (GET_CODE (clobber) == CLOBBER
5843 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
b8794099 5844
1245df60
R		 5845 if (last_float
5846 && reg_set_between_p (r0_rtx, last_float_move, scan))
5847 last_float = 0;
3503150c
RS		 5848 if (last_float
5849 && TARGET_SHCOMPACT
5850 && GET_MODE_SIZE (mode) != 4
5851 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5852 last_float = 0;
1245df60
R		 5853 lab = add_constant (src, mode, last_float);
5854 if (lab)
5855 emit_insn_before (gen_mova (lab), scan);
5856 else
b8794099
R		 5857 {
5858 /* There will be a REG_UNUSED note for r0 on
5859 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5860 lest reorg:mark_target_live_regs will not
5861 consider r0 to be used, and we end up with delay
475f26dd 5862 slot insn in front of SCAN that clobbers r0. */
b8794099
R		 5863 rtx note
5864 = find_regno_note (last_float_move, REG_UNUSED, 0);
5865
ab1672a3
JW		 5866 /* If we are not optimizing, then there may not be
5867 a note. */
5868 if (note)
81f40b79 5869 PUT_REG_NOTE_KIND (note, REG_INC);
b8794099
R		 5870
5871 *last_float_addr = r0_inc_rtx;
5872 }
1245df60
R		 5873 last_float_move = scan;
5874 last_float = src;
57d38024 5875 newsrc = gen_const_mem (mode,
318881c0 5876 (((TARGET_SH4 && ! TARGET_FMOVD)
225e4f43 5877 || REGNO (dst) == FPUL_REG)
1245df60
R		 5878 ? r0_inc_rtx
5879 : r0_rtx));
5880 last_float_addr = &XEXP (newsrc, 0);
b8794099
R		 5881
5882 /* Remove the clobber of r0. */
0f2b41b2
AO		 5883 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5884 gen_rtx_SCRATCH (Pmode));
1245df60 5885 }
1a66cd67 5886 /* This is a mova needing a label. Create it. */
43c05634
AO		 5887 else if (GET_CODE (src) == UNSPEC
5888 && XINT (src, 1) == UNSPEC_MOVA
5889 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
1a66cd67 5890 {
43c05634 5891 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
1a66cd67 5892 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
e69d1422 5893 newsrc = gen_rtx_UNSPEC (SImode,
4773afa4
AO		 5894 gen_rtvec (1, newsrc),
5895 UNSPEC_MOVA);
1a66cd67 5896 }
1245df60
R		 5897 else
5898 {
5899 lab = add_constant (src, mode, 0);
542a8afa
RH		 5900 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5901 newsrc = gen_const_mem (mode, newsrc);
1245df60 5902 }
c5c76735 5903 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
e577c183 5904 INSN_CODE (scan) = -1;
0d7e008e
SC		 5905 }
5906 }
078c8b08 5907 dump_table (need_aligned_label ? insn : 0, barrier);
1245df60 5908 insn = barrier;
0d7e008e
SC		 5909 }
5910 }
6dd3c0a5 5911 free_alloc_pool (label_ref_list_pool);
4241ecb0
R		 5912 for (insn = first; insn; insn = NEXT_INSN (insn))
5913 PUT_MODE (insn, VOIDmode);
5914
1245df60 5915 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
9d98a694 5916 INSN_ADDRESSES_FREE ();
1245df60
R		 5917 split_branches (first);
5918
5919 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
a920aefe 5920 also has an effect on the register that holds the address of the sfunc.
1245df60
R		 5921 Insert an extra dummy insn in front of each sfunc that pretends to
5922 use this register. */
5923 if (flag_delayed_branch)
5924 {
5925 for (insn = first; insn; insn = NEXT_INSN (insn))
5926 {
5927 rtx reg = sfunc_uses_reg (insn);
5928
5929 if (! reg)
5930 continue;
5931 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5932 }
5933 }
225e4f43
R		 5934#if 0
5935 /* fpscr is not actually a user variable, but we pretend it is for the
5936 sake of the previous optimization passes, since we want it handled like
9f09b1f2 5937 one. However, we don't have any debugging information for it, so turn
225e4f43
R		 5938 it into a non-user variable now. */
5939 if (TARGET_SH4)
5940 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5941#endif
1245df60
R		 5942 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5943}
5944
5945int
cf277499 5946get_dest_uid (rtx label, int max_uid)
1245df60
R		 5947{
5948 rtx dest = next_real_insn (label);
5949 int dest_uid;
5950 if (! dest)
5951 /* This can happen for an undefined label. */
5952 return 0;
5953 dest_uid = INSN_UID (dest);
5954 /* If this is a newly created branch redirection blocking instruction,
5955 we cannot index the branch_uid or insn_addresses arrays with its
5956 uid. But then, we won't need to, because the actual destination is
5957 the following branch. */
5958 while (dest_uid >= max_uid)
5959 {
5960 dest = NEXT_INSN (dest);
5961 dest_uid = INSN_UID (dest);
5962 }
f3536097 5963 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
1245df60
R		 5964 return 0;
5965 return dest_uid;
5966}
5967
5968/* Split condbranches that are out of range. Also add clobbers for
5969 scratch registers that are needed in far jumps.
5970 We do this before delay slot scheduling, so that it can take our
5971 newly created instructions into account. It also allows us to
5972 find branches with common targets more easily. */
5973
5974static void
cf277499 5975split_branches (rtx first)
1245df60
R		 5976{
5977 rtx insn;
5978 struct far_branch **uid_branch, *far_branch_list = 0;
5979 int max_uid = get_max_uid ();
f5b9e7c9 5980 int ok;
1245df60
R		 5981
5982 /* Find out which branches are out of range. */
1245df60
R		 5983 shorten_branches (first);
5984
5985 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
2e09e75a 5986 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
1245df60
R		 5987
5988 for (insn = first; insn; insn = NEXT_INSN (insn))
2c3c49de 5989 if (! INSN_P (insn))
1245df60
R		 5990 continue;
5991 else if (INSN_DELETED_P (insn))
5992 {
5993 /* Shorten_branches would split this instruction again,
5994 so transform it into a note. */
a38e7aa5 5995 SET_INSN_DELETED (insn);
1245df60 5996 }
f3536097 5997 else if (JUMP_P (insn)
1245df60
R		 5998 /* Don't mess with ADDR_DIFF_VEC */
5999 && (GET_CODE (PATTERN (insn)) == SET
6000 || GET_CODE (PATTERN (insn)) == RETURN))
6001 {
6002 enum attr_type type = get_attr_type (insn);
6003 if (type == TYPE_CBRANCH)
6004 {
6005 rtx next, beyond;
f676971a 6006
1245df60
R		 6007 if (get_attr_length (insn) > 4)
6008 {
6009 rtx src = SET_SRC (PATTERN (insn));
1245df60 6010 rtx olabel = XEXP (XEXP (src, 1), 0);
9d98a694 6011 int addr = INSN_ADDRESSES (INSN_UID (insn));
1245df60
R		 6012 rtx label = 0;
6013 int dest_uid = get_dest_uid (olabel, max_uid);
6014 struct far_branch *bp = uid_branch[dest_uid];
f676971a 6015
1245df60 6016 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
25938114 6017 the label if the LABEL_NUSES count drops to zero. There is
1245df60
R		 6018 always a jump_optimize pass that sets these values, but it
6019 proceeds to delete unreferenced code, and then if not
956d6950 6020 optimizing, to un-delete the deleted instructions, thus
1245df60
R		 6021 leaving labels with too low uses counts. */
6022 if (! optimize)
6023 {
6024 JUMP_LABEL (insn) = olabel;
6025 LABEL_NUSES (olabel)++;
6026 }
6027 if (! bp)
6028 {
6029 bp = (struct far_branch *) alloca (sizeof *bp);
6030 uid_branch[dest_uid] = bp;
6031 bp->prev = far_branch_list;
6032 far_branch_list = bp;
6033 bp->far_label
6034 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
6035 LABEL_NUSES (bp->far_label)++;
6036 }
6037 else
6038 {
6039 label = bp->near_label;
6040 if (! label && bp->address - addr >= CONDJUMP_MIN)
6041 {
6042 rtx block = bp->insert_place;
6043
6044 if (GET_CODE (PATTERN (block)) == RETURN)
6045 block = PREV_INSN (block);
6046 else
6047 block = gen_block_redirect (block,
6048 bp->address, 2);
6049 label = emit_label_after (gen_label_rtx (),
6050 PREV_INSN (block));
6051 bp->near_label = label;
6052 }
6053 else if (label && ! NEXT_INSN (label))
eda44c78
R		 6054 {
6055 if (addr + 2 - bp->address <= CONDJUMP_MAX)
6056 bp->insert_place = insn;
6057 else
6058 gen_far_branch (bp);
6059 }
1245df60
R		 6060 }
6061 if (! label
318881c0 6062 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
1245df60
R		 6063 {
6064 bp->near_label = label = gen_label_rtx ();
6065 bp->insert_place = insn;
6066 bp->address = addr;
6067 }
2acdc1fb 6068 ok = redirect_jump (insn, label, 0);
f5b9e7c9 6069 gcc_assert (ok);
1245df60
R		 6070 }
6071 else
6072 {
6073 /* get_attr_length (insn) == 2 */
6074 /* Check if we have a pattern where reorg wants to redirect
6075 the branch to a label from an unconditional branch that
6076 is too far away. */
6077 /* We can't use JUMP_LABEL here because it might be undefined
6078 when not optimizing. */
33f7f353 6079 /* A syntax error might cause beyond to be NULL_RTX. */
1245df60
R		 6080 beyond
6081 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
6082 0));
f676971a 6083
33f7f353 6084 if (beyond
f3536097 6085 && (JUMP_P (beyond)
b94544e4 6086 || ((beyond = next_active_insn (beyond))
f3536097 6087 && JUMP_P (beyond)))
1245df60 6088 && GET_CODE (PATTERN (beyond)) == SET
ddf8ec7e 6089 && recog_memoized (beyond) == CODE_FOR_jump_compact
9d98a694
AO		 6090 && ((INSN_ADDRESSES
6091 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
11f9ed1a 6092 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
1245df60
R		 6093 > 252 + 258 + 2))
6094 gen_block_redirect (beyond,
9d98a694 6095 INSN_ADDRESSES (INSN_UID (beyond)), 1);
1245df60 6096 }
f676971a 6097
1245df60
R		 6098 next = next_active_insn (insn);
6099
a7d6f306
KK		 6100 if (next
6101 && (JUMP_P (next)
6102 || ((next = next_active_insn (next))
6103 && JUMP_P (next)))
1245df60 6104 && GET_CODE (PATTERN (next)) == SET
ddf8ec7e 6105 && recog_memoized (next) == CODE_FOR_jump_compact
9d98a694
AO		 6106 && ((INSN_ADDRESSES
6107 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
11f9ed1a 6108 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
1245df60 6109 > 252 + 258 + 2))
9d98a694 6110 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
1245df60
R		 6111 }
6112 else if (type == TYPE_JUMP || type == TYPE_RETURN)
6113 {
9d98a694 6114 int addr = INSN_ADDRESSES (INSN_UID (insn));
1245df60
R		 6115 rtx far_label = 0;
6116 int dest_uid = 0;
6117 struct far_branch *bp;
6118
6119 if (type == TYPE_JUMP)
6120 {
6121 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
6122 dest_uid = get_dest_uid (far_label, max_uid);
6123 if (! dest_uid)
6124 {
6125 /* Parse errors can lead to labels outside
6126 the insn stream. */
6127 if (! NEXT_INSN (far_label))
6128 continue;
6129
6130 if (! optimize)
6131 {
6132 JUMP_LABEL (insn) = far_label;
6133 LABEL_NUSES (far_label)++;
6134 }
8ceaac3c 6135 redirect_jump (insn, NULL_RTX, 1);
1245df60
R		 6136 far_label = 0;
6137 }
6138 }
6139 bp = uid_branch[dest_uid];
6140 if (! bp)
6141 {
6142 bp = (struct far_branch *) alloca (sizeof *bp);
6143 uid_branch[dest_uid] = bp;
6144 bp->prev = far_branch_list;
6145 far_branch_list = bp;
6146 bp->near_label = 0;
6147 bp->far_label = far_label;
6148 if (far_label)
6149 LABEL_NUSES (far_label)++;
6150 }
6151 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
6152 if (addr - bp->address <= CONDJUMP_MAX)
6153 emit_label_after (bp->near_label, PREV_INSN (insn));
6154 else
6155 {
6156 gen_far_branch (bp);
6157 bp->near_label = 0;
6158 }
6159 else
6160 bp->near_label = 0;
6161 bp->address = addr;
6162 bp->insert_place = insn;
6163 if (! far_label)
6164 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
6165 else
6166 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
6167 }
6168 }
6169 /* Generate all pending far branches,
6170 and free our references to the far labels. */
6171 while (far_branch_list)
6172 {
6173 if (far_branch_list->near_label
6174 && ! NEXT_INSN (far_branch_list->near_label))
6175 gen_far_branch (far_branch_list);
6176 if (optimize
6177 && far_branch_list->far_label
6178 && ! --LABEL_NUSES (far_branch_list->far_label))
6179 delete_insn (far_branch_list->far_label);
6180 far_branch_list = far_branch_list->prev;
6181 }
a0798779
R		 6182
6183 /* Instruction length information is no longer valid due to the new
6184 instructions that have been generated. */
6185 init_insn_lengths ();
b9654711
SC		 6186}
6187
8aa2a305 6188/* Dump out instruction addresses, which is useful for debugging the
933c3ba3
JW		 6189 constant pool table stuff.
6190
6191 If relaxing, output the label and pseudo-ops used to link together
6192 calls and the instruction which set the registers. */
8aa2a305 6193
8aa2a305
JW		 6194/* ??? The addresses printed by this routine for insns are nonsense for
6195 insns which are inside of a sequence where none of the inner insns have
6196 variable length. This is because the second pass of shorten_branches
6197 does not bother to update them. */
0d7e008e 6198
8e87e161 6199void
cf277499
SB		 6200final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
6201 int noperands ATTRIBUTE_UNUSED)
b9654711 6202{
8aa2a305 6203 if (TARGET_DUMPISIZE)
9d98a694 6204 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
933c3ba3
JW		 6205
6206 if (TARGET_RELAX)
6207 {
6208 rtx note;
6209
cf7c4aa6 6210 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
933c3ba3
JW		 6211 if (note)
6212 {
6213 rtx pattern;
6214
6215 pattern = PATTERN (insn);
4b7d2f07
R		 6216 if (GET_CODE (pattern) == PARALLEL)
6217 pattern = XVECEXP (pattern, 0, 0);
f5b9e7c9
NS		 6218 switch (GET_CODE (pattern))
6219 {
f5b9e7c9
NS		 6220 case SET:
6221 if (GET_CODE (SET_SRC (pattern)) != CALL
6222 && get_attr_type (insn) != TYPE_SFUNC)
6223 {
6224 targetm.asm_out.internal_label
6225 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
6226 break;
6227 }
6228 /* else FALLTHROUGH */
6229 case CALL:
6230 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
6231 CODE_LABEL_NUMBER (XEXP (note, 0)));
6232 break;
6233
6234 default:
6235 gcc_unreachable ();
6236 }
933c3ba3
JW		 6237 }
6238 }
0d7e008e 6239}
b9654711 6240
8aa2a305 6241/* Dump out any constants accumulated in the final pass. These will
38e01259 6242 only be labels. */
b9654711 6243
318881c0 6244const char *
cf277499 6245output_jump_label_table (void)
0d7e008e 6246{
8aa2a305
JW		 6247 int i;
6248
6249 if (pool_size)
6250 {
6251 fprintf (asm_out_file, "\t.align 2\n");
6252 for (i = 0; i < pool_size; i++)
6253 {
6254 pool_node *p = &pool_vector[i];
6255
4977bab6 6256 (*targetm.asm_out.internal_label) (asm_out_file, "L",
8aa2a305
JW		 6257 CODE_LABEL_NUMBER (p->label));
6258 output_asm_insn (".long %O0", &p->value);
6259 }
6260 pool_size = 0;
6261 }
b9654711 6262
8aa2a305
JW		 6263 return "";
6264}
6265\f
6266/* A full frame looks like:
16bea517
JW		 6267
6268 arg-5
6269 arg-4
6270 [ if current_function_anonymous_args
6271 arg-3
6272 arg-2
6273 arg-1
6274 arg-0 ]
6275 saved-fp
6276 saved-r10
6277 saved-r11
6278 saved-r12
6279 saved-pr
6280 local-n
6281 ..
6282 local-1
6283 local-0 <- fp points here. */
8e87e161 6284
8aa2a305
JW		 6285/* Number of bytes pushed for anonymous args, used to pass information
6286 between expand_prologue and expand_epilogue. */
6287
fada1961
R		 6288/* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6289 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
726d4cb7
KK		 6290 for an epilogue and a negative value means that it's for a sibcall
6291 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6292 all the registers that are about to be restored, and hence dead. */
8aa2a305
JW		 6293
6294static void
fada1961 6295output_stack_adjust (int size, rtx reg, int epilogue_p,
21d05694 6296 HARD_REG_SET *live_regs_mask, bool frame_p)
8aa2a305 6297{
21d05694 6298 rtx (*emit_fn) (rtx) = frame_p ? &frame_insn : &emit_insn;
8aa2a305
JW		 6299 if (size)
6300 {
fa5322fa
AO		 6301 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6302
157371cf
AO		 6303/* This test is bogus, as output_stack_adjust is used to re-align the
6304 stack. */
6305#if 0
f5b9e7c9 6306 gcc_assert (!(size % align));
157371cf 6307#endif
fa5322fa
AO		 6308
6309 if (CONST_OK_FOR_ADD (size))
2754d3c5 6310 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
f3cd5375
JW		 6311 /* Try to do it with two partial adjustments; however, we must make
6312 sure that the stack is properly aligned at all times, in case
6f317ef3 6313 an interrupt occurs between the two partial adjustments. */
fa5322fa
AO		 6314 else if (CONST_OK_FOR_ADD (size / 2 & -align)
6315 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
f3cd5375 6316 {
2754d3c5
R		 6317 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
6318 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
f3cd5375
JW		 6319 }
6320 else
8aa2a305 6321 {
f3cd5375 6322 rtx const_reg;
2754d3c5 6323 rtx insn;
fada1961
R		 6324 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
6325 int i;
f3cd5375
JW		 6326
6327 /* If TEMP is invalid, we could temporarily save a general
6328 register to MACL. However, there is currently no need
f5b9e7c9 6329 to handle this case, so just die when we see it. */
726d4cb7
KK		 6330 if (epilogue_p < 0
6331 || current_function_interrupt
62164eb4 6332 || ! call_really_used_regs[temp] || fixed_regs[temp])
fada1961 6333 temp = -1;
726d4cb7
KK		 6334 if (temp < 0 && ! current_function_interrupt
6335 && (TARGET_SHMEDIA || epilogue_p >= 0))
fada1961
R		 6336 {
6337 HARD_REG_SET temps;
6338 COPY_HARD_REG_SET (temps, call_used_reg_set);
6339 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
726d4cb7 6340 if (epilogue_p > 0)
fada1961 6341 {
726d4cb7 6342 int nreg = 0;
38173d38 6343 if (crtl->return_rtx)
726d4cb7
KK		 6344 {
6345 enum machine_mode mode;
38173d38 6346 mode = GET_MODE (crtl->return_rtx);
726d4cb7
KK		 6347 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
6348 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
6349 }
6350 for (i = 0; i < nreg; i++)
fada1961 6351 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
e3b5732b 6352 if (crtl->calls_eh_return)
fada1961
R		 6353 {
6354 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
6355 for (i = 0; i <= 3; i++)
6356 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
6357 }
6358 }
726d4cb7
KK		 6359 if (TARGET_SHMEDIA && epilogue_p < 0)
6360 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
6361 CLEAR_HARD_REG_BIT (temps, i);
6362 if (epilogue_p <= 0)
fada1961
R		 6363 {
6364 for (i = FIRST_PARM_REG;
6365 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
6366 CLEAR_HARD_REG_BIT (temps, i);
6de9cd9a 6367 if (cfun->static_chain_decl != NULL)
fada1961
R		 6368 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
6369 }
6370 temp = scavenge_reg (&temps);
6371 }
6372 if (temp < 0 && live_regs_mask)
eb996a4a
KK		 6373 {
6374 HARD_REG_SET temps;
6375
6376 COPY_HARD_REG_SET (temps, *live_regs_mask);
6377 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
6378 temp = scavenge_reg (&temps);
6379 }
f3cd5375 6380 if (temp < 0)
726d4cb7 6381 {
f5b9e7c9
NS		 6382 rtx adj_reg, tmp_reg, mem;
6383
726d4cb7
KK		 6384 /* If we reached here, the most likely case is the (sibcall)
6385 epilogue for non SHmedia. Put a special push/pop sequence
6386 for such case as the last resort. This looks lengthy but
f5b9e7c9
NS		 6387 would not be problem because it seems to be very
6388 rare. */
6389
6390 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
6391
6392
6393 /* ??? There is still the slight possibility that r4 or
6394 r5 have been reserved as fixed registers or assigned
6395 as global registers, and they change during an
6396 interrupt. There are possible ways to handle this:
6397
6398 - If we are adjusting the frame pointer (r14), we can do
6399 with a single temp register and an ordinary push / pop
6400 on the stack.
6401 - Grab any call-used or call-saved registers (i.e. not
6402 fixed or globals) for the temps we need. We might
6403 also grab r14 if we are adjusting the stack pointer.
6404 If we can't find enough available registers, issue
6405 a diagnostic and die - the user must have reserved
6406 way too many registers.
6407 But since all this is rather unlikely to happen and
6408 would require extra testing, we just die if r4 / r5
6409 are not available. */
6410 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
6411 && !global_regs[4] && !global_regs[5]);
6412
6413 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
6414 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
57d38024 6415 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
f5b9e7c9
NS		 6416 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
6417 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
57d38024 6418 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
f5b9e7c9 6419 emit_move_insn (mem, tmp_reg);
57d38024
R		 6420 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
6421 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6422 emit_move_insn (mem, tmp_reg);
6423 emit_move_insn (reg, adj_reg);
6424 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6425 emit_move_insn (adj_reg, mem);
6426 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6427 emit_move_insn (tmp_reg, mem);
eb996a4a 6428 /* Tell flow the insns that pop r4/r5 aren't dead. */
c41c1387
RS		 6429 emit_use (tmp_reg);
6430 emit_use (adj_reg);
57d38024 6431 return;
726d4cb7 6432 }
fa5322fa 6433 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
f3cd5375
JW		 6434
6435 /* If SIZE is negative, subtract the positive value.
6436 This sometimes allows a constant pool entry to be shared
6437 between prologue and epilogue code. */
6438 if (size < 0)
885c9a39 6439 {
fa5322fa 6440 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
2754d3c5 6441 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
885c9a39
JR		 6442 }
6443 else
6444 {
fa5322fa 6445 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
2754d3c5 6446 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
885c9a39 6447 }
fada1961 6448 if (! epilogue_p)
b757d36f
KK		 6449 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
6450 gen_rtx_SET (VOIDmode, reg,
6451 gen_rtx_PLUS (SImode, reg,
6452 GEN_INT (size))));
8aa2a305 6453 }
8aa2a305
JW		 6454 }
6455}
6456
2754d3c5 6457static rtx
cf277499 6458frame_insn (rtx x)
2754d3c5
R		 6459{
6460 x = emit_insn (x);
6461 RTX_FRAME_RELATED_P (x) = 1;
6462 return x;
6463}
6464
8aa2a305
JW		 6465/* Output RTL to push register RN onto the stack. */
6466
2754d3c5 6467static rtx
cf277499 6468push (int rn)
8aa2a305
JW		 6469{
6470 rtx x;
225e4f43
R		 6471 if (rn == FPUL_REG)
6472 x = gen_push_fpul ();
7144b2d8
DD		 6473 else if (rn == FPSCR_REG)
6474 x = gen_push_fpscr ();
157371cf 6475 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
104ee20b 6476 && FP_OR_XD_REGISTER_P (rn))
225e4f43 6477 {
104ee20b 6478 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
d042370e 6479 return NULL_RTX;
c5c76735 6480 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
225e4f43 6481 }
3a8699c7 6482 else if (TARGET_SH2E && FP_REGISTER_P (rn))
c5c76735 6483 x = gen_push_e (gen_rtx_REG (SFmode, rn));
1a95a963 6484 else
c5c76735 6485 x = gen_push (gen_rtx_REG (SImode, rn));
1a95a963 6486
2754d3c5 6487 x = frame_insn (x);
b757d36f 6488 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
2754d3c5 6489 return x;
8aa2a305
JW		 6490}
6491
6492/* Output RTL to pop register RN from the stack. */
6493
6494static void
cf277499 6495pop (int rn)
8aa2a305
JW		 6496{
6497 rtx x;
225e4f43
R		 6498 if (rn == FPUL_REG)
6499 x = gen_pop_fpul ();
7144b2d8
DD		 6500 else if (rn == FPSCR_REG)
6501 x = gen_pop_fpscr ();
157371cf 6502 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
104ee20b 6503 && FP_OR_XD_REGISTER_P (rn))
225e4f43 6504 {
104ee20b 6505 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
225e4f43 6506 return;
c5c76735 6507 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
225e4f43 6508 }
3a8699c7 6509 else if (TARGET_SH2E && FP_REGISTER_P (rn))
c5c76735 6510 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
1a95a963 6511 else
c5c76735 6512 x = gen_pop (gen_rtx_REG (SImode, rn));
f676971a 6513
1245df60 6514 x = emit_insn (x);
b757d36f 6515 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
8aa2a305
JW		 6516}
6517
1245df60 6518/* Generate code to push the regs specified in the mask. */
8aa2a305
JW		 6519
6520static void
cf277499 6521push_regs (HARD_REG_SET *mask, int interrupt_handler)
8aa2a305 6522{
5c7cafa8 6523 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
ac55736a 6524 int skip_fpscr = 0;
8aa2a305 6525
1245df60
R		 6526 /* Push PR last; this gives better latencies after the prologue, and
6527 candidates for the return delay slot when there are no general
6528 registers pushed. */
5c7cafa8 6529 for (; i < FIRST_PSEUDO_REGISTER; i++)
ac55736a
R		 6530 {
6531 /* If this is an interrupt handler, and the SZ bit varies,
6532 and we have to push any floating point register, we need
6533 to switch to the correct precision first. */
6534 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
56b138ae 6535 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
ac55736a
R		 6536 {
6537 HARD_REG_SET unsaved;
6538
6539 push (FPSCR_REG);
832a3292 6540 COMPL_HARD_REG_SET (unsaved, *mask);
ac55736a
R		 6541 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
6542 skip_fpscr = 1;
6543 }
6544 if (i != PR_REG
6545 && (i != FPSCR_REG || ! skip_fpscr)
6546 && TEST_HARD_REG_BIT (*mask, i))
561642fa
AP		 6547 {
6548 /* If the ISR has RESBANK attribute assigned, don't push any of
6549 the following registers - R0-R14, MACH, MACL and GBR. */
6550 if (! (sh_cfun_resbank_handler_p ()
6551 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
6552 || i == MACH_REG
6553 || i == MACL_REG
6554 || i == GBR_REG)))
6555 push (i);
6556 }
ac55736a 6557 }
5c7cafa8
CB		 6558
6559 /* Push banked registers last to improve delay slot opportunities. */
6560 if (interrupt_handler)
91a19652
N		 6561 {
6562 bool use_movml = false;
6563
6564 if (TARGET_SH2A)
6565 {
6566 unsigned int count = 0;
6567
6568 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6569 if (TEST_HARD_REG_BIT (*mask, i))
6570 count++;
6571 else
6572 break;
6573
6574 /* Use movml when all banked registers are pushed. */
6575 if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
6576 use_movml = true;
6577 }
6578
6579 if (use_movml)
6580 {
6581 rtx x, mem, reg, set;
6582 rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
6583
6584 /* We must avoid scheduling multiple store insn with another
6585 insns. */
6586 emit_insn (gen_blockage ());
6587 x = gen_movml_push_banked (sp_reg);
6588 x = frame_insn (x);
6589 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6590 {
6591 mem = gen_rtx_MEM (SImode, plus_constant (sp_reg, i * 4));
6592 reg = gen_rtx_REG (SImode, i);
6593 add_reg_note (x, REG_CFA_OFFSET, gen_rtx_SET (SImode, mem, reg));
6594 }
6595
6596 set = gen_rtx_SET (SImode, sp_reg, plus_constant (sp_reg, - 32));
6597 add_reg_note (x, REG_CFA_ADJUST_CFA, set);
6598 emit_insn (gen_blockage ());
6599 }
6600 else
6601 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6602 if (TEST_HARD_REG_BIT (*mask, i))
6603 push (i);
6604 }
5c7cafa8 6605
561642fa
AP		 6606 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6607 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
1245df60 6608 push (PR_REG);
8aa2a305
JW		 6609}
6610
fe3ad572
SC		 6611/* Calculate how much extra space is needed to save all callee-saved
6612 target registers.
6613 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6614
6615static int
6616shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
6617{
6618 int reg;
6619 int stack_space = 0;
6620 int interrupt_handler = sh_cfun_interrupt_handler_p ();
6621
6622 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
62164eb4 6623 if ((! call_really_used_regs[reg] || interrupt_handler)
fe3ad572
SC		 6624 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6625 /* Leave space to save this target register on the stack,
24746a42 6626 in case target register allocation wants to use it. */
fe3ad572
SC		 6627 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6628 return stack_space;
6629}
f676971a 6630
fe3ad572
SC		 6631/* Decide whether we should reserve space for callee-save target registers,
6632 in case target register allocation wants to use them. REGS_SAVED is
6633 the space, in bytes, that is already required for register saves.
6634 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6635
6636static int
6637shmedia_reserve_space_for_target_registers_p (int regs_saved,
6638 HARD_REG_SET *live_regs_mask)
6639{
6640 if (optimize_size)
6641 return 0;
6642 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
6643}
6644
6645/* Decide how much space to reserve for callee-save target registers
6646 in case target register allocation wants to use them.
6647 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6648
6649static int
6650shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
6651{
6652 if (shmedia_space_reserved_for_target_registers)
6653 return shmedia_target_regs_stack_space (live_regs_mask);
6654 else
6655 return 0;
6656}
6657
8aa2a305 6658/* Work out the registers which need to be saved, both as a mask and a
490dbac7 6659 count of saved words. Return the count.
8aa2a305
JW		 6660
6661 If doing a pragma interrupt function, then push all regs used by the
6662 function, and if we call another function (we can tell by looking at PR),
6663 make sure that all the regs it clobbers are safe too. */
6664
490dbac7 6665static int
cf277499 6666calc_live_regs (HARD_REG_SET *live_regs_mask)
8aa2a305 6667{
0ef2c525 6668 unsigned int reg;
1245df60 6669 int count;
a6ab9fc0
R		 6670 tree attrs;
6671 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6672 bool nosave_low_regs;
fada1961 6673 int pr_live, has_call;
157131d7 6674
a6ab9fc0
R		 6675 attrs = DECL_ATTRIBUTES (current_function_decl);
6676 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6677 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6678 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6679 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
8aa2a305 6680
fada1961 6681 CLEAR_HARD_REG_SET (*live_regs_mask);
157371cf 6682 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
6fb5fa3c 6683 && df_regs_ever_live_p (FPSCR_REG))
c0fb94d7 6684 target_flags &= ~MASK_FPU_SINGLE;
225e4f43 6685 /* If we can save a lot of saves by switching to double mode, do that. */
157371cf 6686 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
225e4f43 6687 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6fb5fa3c 6688 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
62164eb4 6689 && (! call_really_used_regs[reg]
a6ab9fc0 6690 || interrupt_handler)
225e4f43
R		 6691 && ++count > 2)
6692 {
c0fb94d7 6693 target_flags &= ~MASK_FPU_SINGLE;
225e4f43
R		 6694 break;
6695 }
9d7ed806
R		 6696 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6697 knows how to use it. That means the pseudo originally allocated for
6698 the initial value can become the PR_MEDIA_REG hard register, as seen for
6699 execute/20010122-1.c:test9. */
6700 if (TARGET_SHMEDIA)
7d73a2ba
R		 6701 /* ??? this function is called from initial_elimination_offset, hence we
6702 can't use the result of sh_media_register_for_return here. */
97b3d0f0 6703 pr_live = sh_pr_n_sets ();
9d7ed806
R		 6704 else
6705 {
6706 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
6707 pr_live = (pr_initial
f3536097 6708 ? (!REG_P (pr_initial)
29db2a1e 6709 || REGNO (pr_initial) != (PR_REG))
6fb5fa3c 6710 : df_regs_ever_live_p (PR_REG));
7d73a2ba
R		 6711 /* For Shcompact, if not optimizing, we end up with a memory reference
6712 using the return address pointer for __builtin_return_address even
6713 though there is no actual need to put the PR register on the stack. */
6fb5fa3c 6714 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
9d7ed806 6715 }
fa5322fa
AO		 6716 /* Force PR to be live if the prologue has to call the SHmedia
6717 argument decoder or register saver. */
6718 if (TARGET_SHCOMPACT
38173d38 6719 && ((crtl->args.info.call_cookie
fa5322fa 6720 & ~ CALL_COOKIE_RET_TRAMP (1))
e3b5732b 6721 || crtl->saves_all_registers))
fa5322fa 6722 pr_live = 1;
fada1961 6723 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
0ef2c525 6724 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
8aa2a305 6725 {
97b3d0f0 6726 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
3007d592 6727 ? pr_live
a6ab9fc0 6728 : interrupt_handler
1245df60 6729 ? (/* Need to save all the regs ever live. */
6fb5fa3c 6730 (df_regs_ever_live_p (reg)
62164eb4
R		 6731 || (call_really_used_regs[reg]
6732 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
6733 || reg == PIC_OFFSET_TABLE_REGNUM)
fada1961 6734 && has_call)
a6ab9fc0
R		 6735 || (TARGET_SHMEDIA && has_call
6736 && REGISTER_NATURAL_MODE (reg) == SImode
fada1961 6737 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
1245df60
R		 6738 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
6739 && reg != RETURN_ADDRESS_POINTER_REGNUM
7144b2d8
DD		 6740 && reg != T_REG && reg != GBR_REG
6741 /* Push fpscr only on targets which have FPU */
6742 && (reg != FPSCR_REG || TARGET_FPU_ANY))
1245df60 6743 : (/* Only push those regs which are used and need to be saved. */
180bde4f
RS		 6744 (TARGET_SHCOMPACT
6745 && flag_pic
38173d38 6746 && crtl->args.info.call_cookie
0ef2c525 6747 && reg == PIC_OFFSET_TABLE_REGNUM)
6fb5fa3c 6748 || (df_regs_ever_live_p (reg)
9fdcdc74
KK		 6749 && ((!call_really_used_regs[reg]
6750 && !(reg != PIC_OFFSET_TABLE_REGNUM
6751 && fixed_regs[reg] && call_used_regs[reg]))
a6ab9fc0 6752 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
e3b5732b 6753 || (crtl->calls_eh_return
0ef2c525
KK		 6754 && (reg == EH_RETURN_DATA_REGNO (0)
6755 || reg == EH_RETURN_DATA_REGNO (1)
6756 || reg == EH_RETURN_DATA_REGNO (2)
6757 || reg == EH_RETURN_DATA_REGNO (3)))
61f71b34 6758 || ((reg == MACL_REG || reg == MACH_REG)
6fb5fa3c 6759 && df_regs_ever_live_p (reg)
61f71b34
DD		 6760 && sh_cfun_attr_renesas_p ())
6761 ))
8aa2a305 6762 {
490dbac7 6763 SET_HARD_REG_BIT (*live_regs_mask, reg);
fa5322fa
AO		 6764 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6765
157371cf 6766 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
fa5322fa 6767 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
eda44c78 6768 {
104ee20b 6769 if (FP_REGISTER_P (reg))
eda44c78 6770 {
6fb5fa3c 6771 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
eda44c78 6772 {
490dbac7 6773 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
fa5322fa 6774 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
eda44c78
R		 6775 }
6776 }
fa5322fa 6777 else if (XD_REGISTER_P (reg))
eda44c78
R		 6778 {
6779 /* Must switch to double mode to access these registers. */
c0fb94d7 6780 target_flags &= ~MASK_FPU_SINGLE;
eda44c78
R		 6781 }
6782 }
8aa2a305 6783 }
a6ab9fc0
R		 6784 if (nosave_low_regs && reg == R8_REG)
6785 break;
8aa2a305 6786 }
fe3ad572
SC		 6787 /* If we have a target register optimization pass after prologue / epilogue
6788 threading, we need to assume all target registers will be live even if
6789 they aren't now. */
6790 if (flag_branch_target_load_optimize2
6791 && TARGET_SAVE_ALL_TARGET_REGS
6792 && shmedia_space_reserved_for_target_registers)
6793 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
62164eb4 6794 if ((! call_really_used_regs[reg] || interrupt_handler)
fe3ad572
SC		 6795 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6796 {
6797 SET_HARD_REG_BIT (*live_regs_mask, reg);
6798 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6799 }
fada1961
R		 6800 /* If this is an interrupt handler, we don't have any call-clobbered
6801 registers we can conveniently use for target register save/restore.
6802 Make sure we save at least one general purpose register when we need
6803 to save target registers. */
6804 if (interrupt_handler
56b138ae
RS		 6805 && hard_reg_set_intersect_p (*live_regs_mask,
6806 reg_class_contents[TARGET_REGS])
6807 && ! hard_reg_set_intersect_p (*live_regs_mask,
6808 reg_class_contents[GENERAL_REGS]))
fada1961
R		 6809 {
6810 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6811 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6812 }
8aa2a305 6813
490dbac7 6814 return count;
8aa2a305
JW		 6815}
6816
6817/* Code to generate prologue and epilogue sequences */
b9654711 6818
a93d1ba2 6819/* PUSHED is the number of bytes that are being pushed on the
0ad913af
R		 6820 stack for register saves. Return the frame size, padded
6821 appropriately so that the stack stays properly aligned. */
e5f8d4c0 6822static HOST_WIDE_INT
cf277499 6823rounded_frame_size (int pushed)
e5f8d4c0
R		 6824{
6825 HOST_WIDE_INT size = get_frame_size ();
6826 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6827
7a296495
CB		 6828 if (ACCUMULATE_OUTGOING_ARGS)
6829 size += crtl->outgoing_args_size;
6830
c5b9ef02 6831 return ((size + pushed + align - 1) & -align) - pushed;
e5f8d4c0
R		 6832}
6833
fa5322fa
AO		 6834/* Choose a call-clobbered target-branch register that remains
6835 unchanged along the whole function. We set it up as the return
6836 value in the prologue. */
6837int
cf277499 6838sh_media_register_for_return (void)
fa5322fa
AO		 6839{
6840 int regno;
6841 int tr0_used;
6842
6843 if (! current_function_is_leaf)
6844 return -1;
fada1961
R		 6845 if (lookup_attribute ("interrupt_handler",
6846 DECL_ATTRIBUTES (current_function_decl)))
6847 return -1;
73a4d10b
R		 6848 if (sh_cfun_interrupt_handler_p ())
6849 return -1;
fa5322fa 6850
6fb5fa3c 6851 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
fa5322fa
AO		 6852
6853 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6fb5fa3c 6854 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
fa5322fa
AO		 6855 return regno;
6856
6857 return -1;
6858}
6859
fada1961
R		 6860/* The maximum registers we need to save are:
6861 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6862 - 32 floating point registers (for each pair, we save none,
6863 one single precision value, or a double precision value).
6864 - 8 target registers
6865 - add 1 entry for a delimiter. */
6866#define MAX_SAVED_REGS (62+32+8)
6867
6868typedef struct save_entry_s
6869{
6870 unsigned char reg;
6871 unsigned char mode;
6872 short offset;
6873} save_entry;
6874
6875#define MAX_TEMPS 4
6876
6877/* There will be a delimiter entry with VOIDmode both at the start and the
6878 end of a filled in schedule. The end delimiter has the offset of the
6879 save with the smallest (i.e. most negative) offset. */
6880typedef struct save_schedule_s
6881{
6882 save_entry entries[MAX_SAVED_REGS + 2];
6883 int temps[MAX_TEMPS+1];
6884} save_schedule;
6885
6886/* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6887 use reverse order. Returns the last entry written to (not counting
6888 the delimiter). OFFSET_BASE is a number to be added to all offset
6889 entries. */
f676971a 6890
fada1961
R		 6891static save_entry *
6892sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6893 int offset_base)
6894{
6895 int align, i;
6896 save_entry *entry = schedule->entries;
6897 int tmpx = 0;
6898 int offset;
6899
6900 if (! current_function_interrupt)
6901 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
62164eb4 6902 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
fada1961
R		 6903 && ! FUNCTION_ARG_REGNO_P (i)
6904 && i != FIRST_RET_REG
6de9cd9a 6905 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
e3b5732b 6906 && ! (crtl->calls_eh_return
fada1961 6907 && (i == EH_RETURN_STACKADJ_REGNO
f94cef0a
KK		 6908 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6909 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
fada1961
R		 6910 schedule->temps[tmpx++] = i;
6911 entry->reg = -1;
6912 entry->mode = VOIDmode;
6913 entry->offset = offset_base;
6914 entry++;
6915 /* We loop twice: first, we save 8-byte aligned registers in the
6916 higher addresses, that are known to be aligned. Then, we
6917 proceed to saving 32-bit registers that don't need 8-byte
6918 alignment.
6919 If this is an interrupt function, all registers that need saving
6920 need to be saved in full. moreover, we need to postpone saving
6921 target registers till we have saved some general purpose registers
6922 we can then use as scratch registers. */
6923 offset = offset_base;
6924 for (align = 1; align >= 0; align--)
6925 {
6926 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6927 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6928 {
6929 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6930 int reg = i;
6931
6932 if (current_function_interrupt)
6933 {
6934 if (TARGET_REGISTER_P (i))
6935 continue;
6936 if (GENERAL_REGISTER_P (i))
6937 mode = DImode;
6938 }
6939 if (mode == SFmode && (i % 2) == 1
6940 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6941 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6942 {
6943 mode = DFmode;
6944 i--;
6945 reg--;
6946 }
6947
6948 /* If we're doing the aligned pass and this is not aligned,
6949 or we're doing the unaligned pass and this is aligned,
6950 skip it. */
6951 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6952 != align)
6953 continue;
6954
6955 if (current_function_interrupt
6956 && GENERAL_REGISTER_P (i)
6957 && tmpx < MAX_TEMPS)
6958 schedule->temps[tmpx++] = i;
6959
6960 offset -= GET_MODE_SIZE (mode);
6961 entry->reg = i;
6962 entry->mode = mode;
6963 entry->offset = offset;
6964 entry++;
6965 }
6966 if (align && current_function_interrupt)
6967 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6968 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6969 {
6970 offset -= GET_MODE_SIZE (DImode);
6971 entry->reg = i;
6972 entry->mode = DImode;
6973 entry->offset = offset;
6974 entry++;
6975 }
6976 }
6977 entry->reg = -1;
6978 entry->mode = VOIDmode;
6979 entry->offset = offset;
6980 schedule->temps[tmpx] = -1;
6981 return entry - 1;
6982}
6983
b9654711 6984void
cf277499 6985sh_expand_prologue (void)
b9654711 6986{
490dbac7 6987 HARD_REG_SET live_regs_mask;
40d2032b 6988 int d, i;
fa5322fa 6989 int d_rounding = 0;
225e4f43 6990 int save_flags = target_flags;
49616835 6991 int pretend_args;
e631262b 6992 int stack_usage;
a6ab9fc0
R		 6993 tree sp_switch_attr
6994 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
b9654711 6995
e3ba8d11 6996 current_function_interrupt = sh_cfun_interrupt_handler_p ();
552ecbd9 6997
0d7e008e 6998 /* We have pretend args if we had an object sent partially in registers
8aa2a305 6999 and partially on the stack, e.g. a large structure. */
38173d38 7000 pretend_args = crtl->args.pretend_args_size;
49616835
JR		 7001 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
7002 && (NPARM_REGS(SImode)
38173d38 7003 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
49616835 7004 pretend_args = 0;
803b9370 7005
49616835 7006 output_stack_adjust (-pretend_args
38173d38 7007 - crtl->args.info.stack_regs * 8,
803b9370 7008 stack_pointer_rtx, 0, NULL, true);
e631262b 7009 stack_usage = pretend_args + crtl->args.info.stack_regs * 8;
b9654711 7010
38173d38 7011 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
2b1fd83f
AO		 7012 /* We're going to use the PIC register to load the address of the
7013 incoming-argument decoder and/or of the return trampoline from
7014 the GOT, so make sure the PIC register is preserved and
7015 initialized. */
6fb5fa3c 7016 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
2b1fd83f 7017
fa5322fa 7018 if (TARGET_SHCOMPACT
38173d38 7019 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
fa5322fa
AO		 7020 {
7021 int reg;
7022
7023 /* First, make all registers with incoming arguments that will
7024 be pushed onto the stack live, so that register renaming
7025 doesn't overwrite them. */
7026 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
38173d38 7027 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
fa5322fa
AO		 7028 >= NPARM_REGS (SImode) - reg)
7029 for (; reg < NPARM_REGS (SImode); reg++)
7030 emit_insn (gen_shcompact_preserve_incoming_args
7031 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
7032 else if (CALL_COOKIE_INT_REG_GET
38173d38 7033 (crtl->args.info.call_cookie, reg) == 1)
fa5322fa
AO		 7034 emit_insn (gen_shcompact_preserve_incoming_args
7035 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
7036
7037 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
7038 stack_pointer_rtx);
7039 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
38173d38 7040 GEN_INT (crtl->args.info.call_cookie));
fa5322fa
AO		 7041 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
7042 gen_rtx_REG (SImode, R0_REG));
7043 }
7044 else if (TARGET_SHMEDIA)
7045 {
7046 int tr = sh_media_register_for_return ();
7047
7048 if (tr >= 0)
6fb5fa3c
DB		 7049 emit_move_insn (gen_rtx_REG (DImode, tr),
7050 gen_rtx_REG (DImode, PR_MEDIA_REG));
fa5322fa
AO		 7051 }
7052
7ab56274 7053 /* Emit the code for SETUP_VARARGS. */
e3b5732b 7054 if (cfun->stdarg)
b9654711 7055 {
49616835 7056 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
1245df60 7057 {
1a95a963
JW		 7058 /* Push arg regs as if they'd been provided by caller in stack. */
7059 for (i = 0; i < NPARM_REGS(SImode); i++)
7060 {
7061 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
2754d3c5 7062
f676971a 7063 if (i >= (NPARM_REGS(SImode)
38173d38 7064 - crtl->args.info.arg_count[(int) SH_ARG_INT]
aec373f1 7065 ))
1a95a963 7066 break;
535b951f 7067 push (rn);
e631262b 7068 stack_usage += GET_MODE_SIZE (SImode);
1a95a963 7069 }
1245df60 7070 }
b9654711 7071 }
1a95a963 7072
4408efce 7073 /* If we're supposed to switch stacks at function entry, do so now. */
a6ab9fc0
R		 7074 if (sp_switch_attr)
7075 {
20e19db4 7076 rtx lab, newsrc;
a6ab9fc0
R		 7077 /* The argument specifies a variable holding the address of the
7078 stack the interrupt function should switch to/from at entry/exit. */
20e19db4 7079 tree arg = TREE_VALUE ( TREE_VALUE (sp_switch_attr));
a6ab9fc0 7080 const char *s
20e19db4 7081 = ggc_strdup (TREE_STRING_POINTER (arg));
a6ab9fc0
R		 7082 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
7083
20e19db4
DD		 7084 lab = add_constant (sp_switch, SImode, 0);
7085 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
7086 newsrc = gen_const_mem (SImode, newsrc);
7087
7088 emit_insn (gen_sp_switch_1 (newsrc));
a6ab9fc0 7089 }
4408efce 7090
490dbac7 7091 d = calc_live_regs (&live_regs_mask);
225e4f43
R		 7092 /* ??? Maybe we could save some switching if we can move a mode switch
7093 that already happens to be at the function start into the prologue. */
ac55736a 7094 if (target_flags != save_flags && ! current_function_interrupt)
225e4f43 7095 emit_insn (gen_toggle_sz ());
f676971a 7096
fa5322fa
AO		 7097 if (TARGET_SH5)
7098 {
fada1961
R		 7099 int offset_base, offset;
7100 rtx r0 = NULL_RTX;
fa5322fa
AO		 7101 int offset_in_r0 = -1;
7102 int sp_in_r0 = 0;
fe3ad572
SC		 7103 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
7104 int total_size, save_size;
fada1961
R		 7105 save_schedule schedule;
7106 save_entry *entry;
7107 int *tmp_pnt;
7108
62164eb4 7109 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
fada1961
R		 7110 && ! current_function_interrupt)
7111 r0 = gen_rtx_REG (Pmode, R0_REG);
fe3ad572
SC		 7112
7113 /* D is the actual number of bytes that we need for saving registers,
7114 however, in initial_elimination_offset we have committed to using
7115 an additional TREGS_SPACE amount of bytes - in order to keep both
7116 addresses to arguments supplied by the caller and local variables
7117 valid, we must keep this gap. Place it between the incoming
7118 arguments and the actually saved registers in a bid to optimize
7119 locality of reference. */
7120 total_size = d + tregs_space;
7121 total_size += rounded_frame_size (total_size);
7122 save_size = total_size - rounded_frame_size (d);
7123 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
fa5322fa 7124 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
fe3ad572
SC		 7125 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
7126
7127 /* If adjusting the stack in a single step costs nothing extra, do so.
7128 I.e. either if a single addi is enough, or we need a movi anyway,
7129 and we don't exceed the maximum offset range (the test for the
7130 latter is conservative for simplicity). */
7131 if (TARGET_SHMEDIA
7132 && (CONST_OK_FOR_I10 (-total_size)
7133 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
7134 && total_size <= 2044)))
7135 d_rounding = total_size - save_size;
fa5322fa 7136
fada1961 7137 offset_base = d + d_rounding;
fe3ad572
SC		 7138
7139 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
21d05694 7140 0, NULL, true);
e631262b 7141 stack_usage += save_size + d_rounding;
fa5322fa 7142
fada1961
R		 7143 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
7144 tmp_pnt = schedule.temps;
7145 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
7146 {
81f40b79 7147 enum machine_mode mode = (enum machine_mode) entry->mode;
0ef2c525 7148 unsigned int reg = entry->reg;
fada1961 7149 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
455786b6 7150 rtx orig_reg_rtx;
fa5322fa 7151
fada1961 7152 offset = entry->offset;
fa5322fa 7153
fada1961 7154 reg_rtx = gen_rtx_REG (mode, reg);
fa5322fa 7155
57d38024
R		 7156 mem_rtx = gen_frame_mem (mode,
7157 gen_rtx_PLUS (Pmode,
7158 stack_pointer_rtx,
7159 GEN_INT (offset)));
fa5322fa 7160
6de7a512
PB		 7161 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7162 {
7163 gcc_assert (r0);
7164 mem_rtx = NULL_RTX;
7165 }
fa5322fa 7166
6de7a512
PB		 7167 if (HAVE_PRE_DECREMENT
7168 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
7169 || mem_rtx == NULL_RTX
7170 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7171 {
7172 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
fa5322fa 7173
6de7a512 7174 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
fada1961 7175 pre_dec = NULL_RTX;
6de7a512
PB		 7176 else
7177 {
7178 mem_rtx = NULL_RTX;
7179 offset += GET_MODE_SIZE (mode);
7180 }
7181 }
fa5322fa 7182
fada1961
R		 7183 if (mem_rtx != NULL_RTX)
7184 goto addr_ok;
fa5322fa 7185
fada1961
R		 7186 if (offset_in_r0 == -1)
7187 {
7188 emit_move_insn (r0, GEN_INT (offset));
7189 offset_in_r0 = offset;
7190 }
7191 else if (offset != offset_in_r0)
7192 {
7193 emit_move_insn (r0,
7194 gen_rtx_PLUS
7195 (Pmode, r0,
7196 GEN_INT (offset - offset_in_r0)));
7197 offset_in_r0 += offset - offset_in_r0;
7198 }
f676971a 7199
fada1961
R		 7200 if (pre_dec != NULL_RTX)
7201 {
7202 if (! sp_in_r0)
fa5322fa
AO		 7203 {
7204 emit_move_insn (r0,
7205 gen_rtx_PLUS
fada1961
R		 7206 (Pmode, r0, stack_pointer_rtx));
7207 sp_in_r0 = 1;
fa5322fa 7208 }
fa5322fa 7209
fada1961
R		 7210 offset -= GET_MODE_SIZE (mode);
7211 offset_in_r0 -= GET_MODE_SIZE (mode);
fa5322fa 7212
fada1961
R		 7213 mem_rtx = pre_dec;
7214 }
7215 else if (sp_in_r0)
57d38024 7216 mem_rtx = gen_frame_mem (mode, r0);
fada1961 7217 else
57d38024
R		 7218 mem_rtx = gen_frame_mem (mode,
7219 gen_rtx_PLUS (Pmode,
7220 stack_pointer_rtx,
7221 r0));
fada1961
R		 7222
7223 /* We must not use an r0-based address for target-branch
7224 registers or for special registers without pre-dec
7225 memory addresses, since we store their values in r0
7226 first. */
f5b9e7c9
NS		 7227 gcc_assert (!TARGET_REGISTER_P (reg)
7228 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7229 || mem_rtx == pre_dec));
7230
fada1961 7231 addr_ok:
455786b6 7232 orig_reg_rtx = reg_rtx;
fada1961
R		 7233 if (TARGET_REGISTER_P (reg)
7234 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7235 && mem_rtx != pre_dec))
7236 {
7237 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
fa5322fa 7238
fada1961 7239 emit_move_insn (tmp_reg, reg_rtx);
fa5322fa 7240
fada1961
R		 7241 if (REGNO (tmp_reg) == R0_REG)
7242 {
fa5322fa
AO		 7243 offset_in_r0 = -1;
7244 sp_in_r0 = 0;
f5b9e7c9
NS		 7245 gcc_assert (!refers_to_regno_p
7246 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
fa5322fa
AO		 7247 }
7248
fada1961
R		 7249 if (*++tmp_pnt <= 0)
7250 tmp_pnt = schedule.temps;
7251
7252 reg_rtx = tmp_reg;
fa5322fa 7253 }
fada1961
R		 7254 {
7255 rtx insn;
7256
7257 /* Mark as interesting for dwarf cfi generator */
7258 insn = emit_move_insn (mem_rtx, reg_rtx);
7259 RTX_FRAME_RELATED_P (insn) = 1;
455786b6
KK		 7260 /* If we use an intermediate register for the save, we can't
7261 describe this exactly in cfi as a copy of the to-be-saved
7262 register into the temporary register and then the temporary
7263 register on the stack, because the temporary register can
7264 have a different natural size than the to-be-saved register.
7265 Thus, we gloss over the intermediate copy and pretend we do
7266 a direct save from the to-be-saved register. */
7267 if (REGNO (reg_rtx) != reg)
7268 {
b757d36f 7269 rtx set;
455786b6
KK		 7270
7271 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
b757d36f 7272 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
455786b6 7273 }
fada1961 7274
f676971a 7275 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
fada1961
R		 7276 {
7277 rtx reg_rtx = gen_rtx_REG (mode, reg);
b757d36f 7278 rtx set;
57d38024
R		 7279 rtx mem_rtx = gen_frame_mem (mode,
7280 gen_rtx_PLUS (Pmode,
7281 stack_pointer_rtx,
7282 GEN_INT (offset)));
fada1961
R		 7283
7284 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
b757d36f 7285 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
fada1961
R		 7286 }
7287 }
7288 }
fa5322fa 7289
f5b9e7c9 7290 gcc_assert (entry->offset == d_rounding);
fa5322fa
AO		 7291 }
7292 else
e631262b
KK		 7293 {
7294 push_regs (&live_regs_mask, current_function_interrupt);
7295 stack_usage += d;
7296 }
1a66cd67 7297
6fb5fa3c
DB		 7298 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7299 emit_insn (gen_GOTaddr2picreg ());
1a66cd67 7300
fa5322fa
AO		 7301 if (SHMEDIA_REGS_STACK_ADJUST ())
7302 {
fa5322fa
AO		 7303 /* This must NOT go through the PLT, otherwise mach and macl
7304 may be clobbered. */
73a4d10b
R		 7305 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7306 (TARGET_FPU_ANY
7307 ? "__GCC_push_shmedia_regs"
7308 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
fa5322fa
AO		 7309 emit_insn (gen_shmedia_save_restore_regs_compact
7310 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
7311 }
7312
ac55736a 7313 if (target_flags != save_flags && ! current_function_interrupt)
6fb5fa3c 7314 emit_insn (gen_toggle_sz ());
1a95a963 7315
225e4f43
R		 7316 target_flags = save_flags;
7317
fa5322fa 7318 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
21d05694 7319 stack_pointer_rtx, 0, NULL, true);
e631262b 7320 stack_usage += rounded_frame_size (d) - d_rounding;
b9654711
SC		 7321
7322 if (frame_pointer_needed)
96a2347e 7323 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
fa5322fa 7324
fa5322fa 7325 if (TARGET_SHCOMPACT
38173d38 7326 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
fa5322fa
AO		 7327 {
7328 /* This must NOT go through the PLT, otherwise mach and macl
7329 may be clobbered. */
73a4d10b
R		 7330 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7331 "__GCC_shcompact_incoming_args", SFUNC_GOT);
fa5322fa
AO		 7332 emit_insn (gen_shcompact_incoming_args ());
7333 }
e631262b
KK		 7334
7335 if (flag_stack_usage)
7336 current_function_static_stack_size = stack_usage;
b9654711
SC		 7337}
7338
7339void
726d4cb7 7340sh_expand_epilogue (bool sibcall_p)
b9654711 7341{
490dbac7 7342 HARD_REG_SET live_regs_mask;
40d2032b 7343 int d, i;
fa5322fa 7344 int d_rounding = 0;
b9654711 7345
225e4f43 7346 int save_flags = target_flags;
fe3ad572 7347 int frame_size, save_size;
ac55736a 7348 int fpscr_deferred = 0;
726d4cb7 7349 int e = sibcall_p ? -1 : 1;
3d5a0820 7350
490dbac7 7351 d = calc_live_regs (&live_regs_mask);
3d5a0820 7352
fe3ad572
SC		 7353 save_size = d;
7354 frame_size = rounded_frame_size (d);
7355
7356 if (TARGET_SH5)
7357 {
7358 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
7359 int total_size;
7360 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
7361 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7362 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
7363
7364 total_size = d + tregs_space;
7365 total_size += rounded_frame_size (total_size);
7366 save_size = total_size - frame_size;
7367
7368 /* If adjusting the stack in a single step costs nothing extra, do so.
7369 I.e. either if a single addi is enough, or we need a movi anyway,
7370 and we don't exceed the maximum offset range (the test for the
7371 latter is conservative for simplicity). */
7372 if (TARGET_SHMEDIA
7373 && ! frame_pointer_needed
7374 && (CONST_OK_FOR_I10 (total_size)
7375 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
7376 && total_size <= 2044)))
7377 d_rounding = frame_size;
fa5322fa 7378
fe3ad572
SC		 7379 frame_size -= d_rounding;
7380 }
16bea517 7381
b9654711 7382 if (frame_pointer_needed)
46d81ffa 7383 {
1964788a 7384 /* We must avoid scheduling the epilogue with previous basic blocks.
47ea8d4e 7385 See PR/18032 and PR/40313. */
1964788a 7386 emit_insn (gen_blockage ());
96a2347e 7387 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
21d05694 7388 &live_regs_mask, false);
07f5b9aa
JL		 7389
7390 /* We must avoid moving the stack pointer adjustment past code
7391 which reads from the local frame, else an interrupt could
7392 occur after the SP adjustment and clobber data in the local
7393 frame. */
7394 emit_insn (gen_blockage ());
96a2347e 7395 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
46d81ffa 7396 }
3d5a0820 7397 else if (frame_size)
07f5b9aa
JL		 7398 {
7399 /* We must avoid moving the stack pointer adjustment past code
7400 which reads from the local frame, else an interrupt could
7401 occur after the SP adjustment and clobber data in the local
7402 frame. */
7403 emit_insn (gen_blockage ());
21d05694
DD		 7404 output_stack_adjust (frame_size, stack_pointer_rtx, e,
7405 &live_regs_mask, false);
07f5b9aa 7406 }
b9654711 7407
fa5322fa
AO		 7408 if (SHMEDIA_REGS_STACK_ADJUST ())
7409 {
73a4d10b
R		 7410 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7411 (TARGET_FPU_ANY
7412 ? "__GCC_pop_shmedia_regs"
7413 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
fa5322fa
AO		 7414 /* This must NOT go through the PLT, otherwise mach and macl
7415 may be clobbered. */
7416 emit_insn (gen_shmedia_save_restore_regs_compact
7417 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
7418 }
7419
16bea517 7420 /* Pop all the registers. */
0d7e008e 7421
ac55736a 7422 if (target_flags != save_flags && ! current_function_interrupt)
225e4f43 7423 emit_insn (gen_toggle_sz ());
fa5322fa
AO		 7424 if (TARGET_SH5)
7425 {
fada1961 7426 int offset_base, offset;
fa5322fa
AO		 7427 int offset_in_r0 = -1;
7428 int sp_in_r0 = 0;
fa5322fa 7429 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
fada1961
R		 7430 save_schedule schedule;
7431 save_entry *entry;
7432 int *tmp_pnt;
7d73a2ba 7433
fada1961
R		 7434 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
7435 offset_base = -entry[1].offset + d_rounding;
7436 tmp_pnt = schedule.temps;
7437 for (; entry->mode != VOIDmode; entry--)
7438 {
81f40b79 7439 enum machine_mode mode = (enum machine_mode) entry->mode;
fada1961 7440 int reg = entry->reg;
535b951f 7441 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX;
fa5322fa 7442
fada1961
R		 7443 offset = offset_base + entry->offset;
7444 reg_rtx = gen_rtx_REG (mode, reg);
fa5322fa 7445
57d38024
R		 7446 mem_rtx = gen_frame_mem (mode,
7447 gen_rtx_PLUS (Pmode,
7448 stack_pointer_rtx,
7449 GEN_INT (offset)));
fa5322fa 7450
6de7a512
PB		 7451 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7452 mem_rtx = NULL_RTX;
fa5322fa 7453
6de7a512
PB		 7454 if (HAVE_POST_INCREMENT
7455 && (offset == offset_in_r0
7456 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
7457 && mem_rtx == NULL_RTX)
7458 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7459 {
7460 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
fa5322fa 7461
6de7a512 7462 if (!memory_address_p (mode, XEXP (post_inc, 0)))
fada1961 7463 post_inc = NULL_RTX;
6de7a512 7464 else
fada1961 7465 mem_rtx = NULL_RTX;
6de7a512 7466 }
f676971a 7467
fada1961
R		 7468 if (mem_rtx != NULL_RTX)
7469 goto addr_ok;
fa5322fa 7470
fada1961
R		 7471 if (offset_in_r0 == -1)
7472 {
7473 emit_move_insn (r0, GEN_INT (offset));
7474 offset_in_r0 = offset;
7475 }
7476 else if (offset != offset_in_r0)
7477 {
7478 emit_move_insn (r0,
7479 gen_rtx_PLUS
7480 (Pmode, r0,
7481 GEN_INT (offset - offset_in_r0)));
7482 offset_in_r0 += offset - offset_in_r0;
7483 }
f676971a 7484
fada1961
R		 7485 if (post_inc != NULL_RTX)
7486 {
7487 if (! sp_in_r0)
fa5322fa
AO		 7488 {
7489 emit_move_insn (r0,
7490 gen_rtx_PLUS
fada1961
R		 7491 (Pmode, r0, stack_pointer_rtx));
7492 sp_in_r0 = 1;
fa5322fa 7493 }
f676971a 7494
fada1961 7495 mem_rtx = post_inc;
fa5322fa 7496
fada1961
R		 7497 offset_in_r0 += GET_MODE_SIZE (mode);
7498 }
7499 else if (sp_in_r0)
57d38024 7500 mem_rtx = gen_frame_mem (mode, r0);
fada1961 7501 else
57d38024
R		 7502 mem_rtx = gen_frame_mem (mode,
7503 gen_rtx_PLUS (Pmode,
7504 stack_pointer_rtx,
7505 r0));
fa5322fa 7506
f5b9e7c9
NS		 7507 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7508 || mem_rtx == post_inc);
fa5322fa 7509
fada1961
R		 7510 addr_ok:
7511 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7512 && mem_rtx != post_inc)
7513 {
535b951f 7514 emit_move_insn (r0, mem_rtx);
fada1961
R		 7515 mem_rtx = r0;
7516 }
7517 else if (TARGET_REGISTER_P (reg))
7518 {
7519 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
7520
7521 /* Give the scheduler a bit of freedom by using up to
7522 MAX_TEMPS registers in a round-robin fashion. */
535b951f 7523 emit_move_insn (tmp_reg, mem_rtx);
fada1961
R		 7524 mem_rtx = tmp_reg;
7525 if (*++tmp_pnt < 0)
7526 tmp_pnt = schedule.temps;
fa5322fa
AO		 7527 }
7528
535b951f 7529 emit_move_insn (reg_rtx, mem_rtx);
fada1961
R		 7530 }
7531
f5b9e7c9 7532 gcc_assert (entry->offset + offset_base == d + d_rounding);
fa5322fa 7533 }
fe3ad572 7534 else /* ! TARGET_SH5 */
b9654711 7535 {
5c7cafa8
CB		 7536 int last_reg;
7537
fe3ad572 7538 save_size = 0;
561642fa
AP		 7539 /* For an ISR with RESBANK attribute assigned, don't pop PR
7540 register. */
7541 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
7542 && !sh_cfun_resbank_handler_p ())
6fb5fa3c
DB		 7543 {
7544 if (!frame_pointer_needed)
7545 emit_insn (gen_blockage ());
7546 pop (PR_REG);
7547 }
5c7cafa8 7548
6a62ca52 7549 /* Banked registers are popped first to avoid being scheduled in the
5c7cafa8
CB		 7550 delay slot. RTE switches banks before the ds instruction. */
7551 if (current_function_interrupt)
7552 {
91a19652
N		 7553 bool use_movml = false;
7554
7555 if (TARGET_SH2A)
7556 {
7557 unsigned int count = 0;
7558
7559 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
7560 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7561 count++;
7562 else
7563 break;
7564
7565 /* Use movml when all banked register are poped. */
7566 if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
7567 use_movml = true;
7568 }
7569
7570 if (use_movml)
7571 {
7572 rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
7573
7574 /* We must avoid scheduling multiple load insn with another
7575 insns. */
7576 emit_insn (gen_blockage ());
7577 emit_insn (gen_movml_pop_banked (sp_reg));
7578 emit_insn (gen_blockage ());
7579 }
7580 else
7581 for (i = LAST_BANKED_REG; i >= FIRST_BANKED_REG; i--)
7582 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7583 pop (i);
5c7cafa8
CB		 7584
7585 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
7586 }
7587 else
7588 last_reg = FIRST_PSEUDO_REGISTER;
7589
7590 for (i = 0; i < last_reg; i++)
fe3ad572
SC		 7591 {
7592 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
f676971a 7593
fe3ad572 7594 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
56b138ae
RS		 7595 && hard_reg_set_intersect_p (live_regs_mask,
7596 reg_class_contents[DF_REGS]))
fe3ad572 7597 fpscr_deferred = 1;
561642fa
AP		 7598 /* For an ISR with RESBANK attribute assigned, don't pop
7599 following registers, R0-R14, MACH, MACL and GBR. */
7600 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
7601 && ! (sh_cfun_resbank_handler_p ()
7602 && ((j >= FIRST_GENERAL_REG
7603 && j < LAST_GENERAL_REG)
7604 || j == MACH_REG
7605 || j == MACL_REG
7606 || j == GBR_REG)))
fe3ad572 7607 pop (j);
5c7cafa8 7608
fe3ad572
SC		 7609 if (j == FIRST_FP_REG && fpscr_deferred)
7610 pop (FPSCR_REG);
fe3ad572 7611 }
b9654711 7612 }
ac55736a 7613 if (target_flags != save_flags && ! current_function_interrupt)
225e4f43
R		 7614 emit_insn (gen_toggle_sz ());
7615 target_flags = save_flags;
b9654711 7616
38173d38 7617 output_stack_adjust (crtl->args.pretend_args_size
fe3ad572 7618 + save_size + d_rounding
38173d38 7619 + crtl->args.info.stack_regs * 8,
21d05694 7620 stack_pointer_rtx, e, NULL, false);
4408efce 7621
e3b5732b 7622 if (crtl->calls_eh_return)
4977bab6
ZW		 7623 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
7624 EH_RETURN_STACKADJ_RTX));
7625
4408efce 7626 /* Switch back to the normal stack if necessary. */
a6ab9fc0 7627 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
4408efce 7628 emit_insn (gen_sp_switch_2 ());
89d4bc35
AO		 7629
7630 /* Tell flow the insn that pops PR isn't dead. */
fa5322fa
AO		 7631 /* PR_REG will never be live in SHmedia mode, and we don't need to
7632 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
7633 by the return pattern. */
490dbac7 7634 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
c41c1387 7635 emit_use (gen_rtx_REG (SImode, PR_REG));
b9654711
SC		 7636}
7637
afbc2905
R		 7638static int sh_need_epilogue_known = 0;
7639
7640int
cf277499 7641sh_need_epilogue (void)
afbc2905
R		 7642{
7643 if (! sh_need_epilogue_known)
7644 {
7645 rtx epilogue;
7646
7647 start_sequence ();
726d4cb7 7648 sh_expand_epilogue (0);
2f937369 7649 epilogue = get_insns ();
afbc2905 7650 end_sequence ();
2f937369 7651 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
afbc2905
R		 7652 }
7653 return sh_need_epilogue_known > 0;
7654}
7655
4977bab6
ZW		 7656/* Emit code to change the current function's return address to RA.
7657 TEMP is available as a scratch register, if needed. */
7658
7659void
cf277499 7660sh_set_return_address (rtx ra, rtx tmp)
4977bab6 7661{
490dbac7 7662 HARD_REG_SET live_regs_mask;
4977bab6 7663 int d;
4977bab6
ZW		 7664 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7665 int pr_offset;
7666
490dbac7 7667 d = calc_live_regs (&live_regs_mask);
4977bab6
ZW		 7668
7669 /* If pr_reg isn't life, we can set it (or the register given in
7670 sh_media_register_for_return) directly. */
490dbac7 7671 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
4977bab6
ZW		 7672 {
7673 rtx rr;
7674
7675 if (TARGET_SHMEDIA)
7676 {
7677 int rr_regno = sh_media_register_for_return ();
7678
7679 if (rr_regno < 0)
7680 rr_regno = pr_reg;
7681
7682 rr = gen_rtx_REG (DImode, rr_regno);
7683 }
7684 else
7685 rr = gen_rtx_REG (SImode, pr_reg);
7686
7687 emit_insn (GEN_MOV (rr, ra));
7688 /* Tell flow the register for return isn't dead. */
c41c1387 7689 emit_use (rr);
4977bab6
ZW		 7690 return;
7691 }
7692
7693 if (TARGET_SH5)
7694 {
4977bab6 7695 int offset;
fada1961
R		 7696 save_schedule schedule;
7697 save_entry *entry;
f676971a 7698
fada1961
R		 7699 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
7700 offset = entry[1].offset;
7701 for (; entry->mode != VOIDmode; entry--)
7702 if (entry->reg == pr_reg)
7703 goto found;
4977bab6
ZW		 7704
7705 /* We can't find pr register. */
f5b9e7c9 7706 gcc_unreachable ();
4977bab6
ZW		 7707
7708 found:
fada1961
R		 7709 offset = entry->offset - offset;
7710 pr_offset = (rounded_frame_size (d) + offset
4977bab6
ZW		 7711 + SHMEDIA_REGS_STACK_ADJUST ());
7712 }
7713 else
fada1961 7714 pr_offset = rounded_frame_size (d);
4977bab6
ZW		 7715
7716 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7a296495
CB		 7717
7718 if (frame_pointer_needed)
7719 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7720 else
7721 emit_insn (GEN_ADD3 (tmp, tmp, stack_pointer_rtx));
4977bab6 7722
57d38024 7723 tmp = gen_frame_mem (Pmode, tmp);
4977bab6 7724 emit_insn (GEN_MOV (tmp, ra));
7f9a14e3
KK		 7725 /* Tell this store isn't dead. */
7726 emit_use (tmp);
4977bab6
ZW		 7727}
7728
8aa2a305
JW		 7729/* Clear variables at function end. */
7730
08c148a8 7731static void
cf277499
SB		 7732sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7733 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8aa2a305 7734{
afbc2905 7735 sh_need_epilogue_known = 0;
8aa2a305
JW		 7736}
7737
61f71b34 7738static rtx
cf277499 7739sh_builtin_saveregs (void)
1a95a963 7740{
1a95a963 7741 /* First unnamed integer register. */
38173d38 7742 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
1a95a963
JW		 7743 /* Number of integer registers we need to save. */
7744 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7745 /* First unnamed SFmode float reg */
38173d38 7746 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
1a95a963
JW		 7747 /* Number of SFmode float regs to save. */
7748 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
318881c0 7749 rtx regbuf, fpregs;
ba4828e0 7750 int bufsize, regno;
4862826d 7751 alias_set_type alias_set;
1a95a963 7752
fa5322fa
AO		 7753 if (TARGET_SH5)
7754 {
7755 if (n_intregs)
7756 {
7757 int pushregs = n_intregs;
7758
7759 while (pushregs < NPARM_REGS (SImode) - 1
7760 && (CALL_COOKIE_INT_REG_GET
38173d38 7761 (crtl->args.info.call_cookie,
fa5322fa
AO		 7762 NPARM_REGS (SImode) - pushregs)
7763 == 1))
7764 {
38173d38 7765 crtl->args.info.call_cookie
fa5322fa
AO		 7766 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7767 - pushregs, 1);
7768 pushregs++;
7769 }
7770
7771 if (pushregs == NPARM_REGS (SImode))
38173d38 7772 crtl->args.info.call_cookie
fa5322fa
AO		 7773 |= (CALL_COOKIE_INT_REG (0, 1)
7774 | CALL_COOKIE_STACKSEQ (pushregs - 1));
7775 else
38173d38 7776 crtl->args.info.call_cookie
fa5322fa
AO		 7777 |= CALL_COOKIE_STACKSEQ (pushregs);
7778
38173d38 7779 crtl->args.pretend_args_size += 8 * n_intregs;
fa5322fa
AO		 7780 }
7781 if (TARGET_SHCOMPACT)
7782 return const0_rtx;
7783 }
f676971a 7784
3a8699c7 7785 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
fa5322fa
AO		 7786 {
7787 error ("__builtin_saveregs not supported by this subtarget");
7788 return const0_rtx;
7789 }
7790
7791 if (TARGET_SHMEDIA)
7792 n_floatregs = 0;
7793
6f317ef3 7794 /* Allocate block of memory for the regs. */
1a95a963
JW		 7795 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7796 Or can assign_stack_local accept a 0 SIZE argument? */
7797 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7798
fa5322fa 7799 if (TARGET_SHMEDIA)
57d38024 7800 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
f78ec36a
R		 7801 else if (n_floatregs & 1)
7802 {
7803 rtx addr;
7804
7805 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7806 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7807 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7808 regbuf = change_address (regbuf, BLKmode, addr);
7809 }
a11c004b
R		 7810 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7811 {
7812 rtx addr, mask;
7813
7814 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7815 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7816 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7817 emit_insn (gen_andsi3 (addr, addr, mask));
7818 regbuf = change_address (regbuf, BLKmode, addr);
7819 }
fa5322fa 7820 else
a11c004b 7821 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
514066a1 7822 alias_set = get_varargs_alias_set ();
ba4828e0 7823 set_mem_alias_set (regbuf, alias_set);
1a95a963
JW		 7824
7825 /* Save int args.
7826 This is optimized to only save the regs that are necessary. Explicitly
7827 named args need not be saved. */
7828 if (n_intregs > 0)
7829 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
f4ef873c
RK		 7830 adjust_address (regbuf, BLKmode,
7831 n_floatregs * UNITS_PER_WORD),
c6b97fac 7832 n_intregs);
1a95a963 7833
fa5322fa
AO		 7834 if (TARGET_SHMEDIA)
7835 /* Return the address of the regbuf. */
7836 return XEXP (regbuf, 0);
7837
1a95a963
JW		 7838 /* Save float args.
7839 This is optimized to only save the regs that are necessary. Explicitly
7840 named args need not be saved.
7841 We explicitly build a pointer to the buffer because it halves the insn
7842 count when not optimizing (otherwise the pointer is built for each reg
1245df60
R		 7843 saved).
7844 We emit the moves in reverse order so that we can use predecrement. */
1a95a963 7845
7d9c5aa1
R		 7846 fpregs = copy_to_mode_reg (Pmode,
7847 plus_constant (XEXP (regbuf, 0),
7848 n_floatregs * UNITS_PER_WORD));
157371cf 7849 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
225e4f43 7850 {
514066a1 7851 rtx mem;
225e4f43
R		 7852 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7853 {
7854 emit_insn (gen_addsi3 (fpregs, fpregs,
7855 GEN_INT (-2 * UNITS_PER_WORD)));
57d38024 7856 mem = change_address (regbuf, DFmode, fpregs);
f676971a 7857 emit_move_insn (mem,
c0d4e710 7858 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
225e4f43
R		 7859 }
7860 regno = first_floatreg;
7861 if (regno & 1)
7862 {
832a3292 7863 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
57d38024 7864 mem = change_address (regbuf, SFmode, fpregs);
514066a1 7865 emit_move_insn (mem,
c0d4e710 7866 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
225e4f43
R		 7867 - (TARGET_LITTLE_ENDIAN != 0)));
7868 }
7869 }
7870 else
1245df60
R		 7871 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7872 {
514066a1 7873 rtx mem;
ba4828e0 7874
832a3292 7875 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
57d38024 7876 mem = change_address (regbuf, SFmode, fpregs);
514066a1 7877 emit_move_insn (mem,
c5c76735 7878 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
1245df60 7879 }
1a95a963
JW		 7880
7881 /* Return the address of the regbuf. */
7882 return XEXP (regbuf, 0);
7883}
7884
514066a1
RH		 7885/* Define the `__builtin_va_list' type for the ABI. */
7886
c35d187f
RH		 7887static tree
7888sh_build_builtin_va_list (void)
514066a1
RH		 7889{
7890 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
10575b5d 7891 tree record, type_decl;
514066a1 7892
61f71b34
DD		 7893 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7894 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
514066a1
RH		 7895 return ptr_type_node;
7896
5d27ef94 7897 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
10575b5d
KK		 7898 type_decl = build_decl (BUILTINS_LOCATION,
7899 TYPE_DECL, get_identifier ("__va_list_tag"), record);
514066a1 7900
4c4bde29
AH		 7901 f_next_o = build_decl (BUILTINS_LOCATION,
7902 FIELD_DECL, get_identifier ("__va_next_o"),
514066a1 7903 ptr_type_node);
4c4bde29
AH		 7904 f_next_o_limit = build_decl (BUILTINS_LOCATION,
7905 FIELD_DECL,
514066a1
RH		 7906 get_identifier ("__va_next_o_limit"),
7907 ptr_type_node);
4c4bde29
AH		 7908 f_next_fp = build_decl (BUILTINS_LOCATION,
7909 FIELD_DECL, get_identifier ("__va_next_fp"),
514066a1 7910 ptr_type_node);
4c4bde29
AH		 7911 f_next_fp_limit = build_decl (BUILTINS_LOCATION,
7912 FIELD_DECL,
514066a1
RH		 7913 get_identifier ("__va_next_fp_limit"),
7914 ptr_type_node);
4c4bde29
AH		 7915 f_next_stack = build_decl (BUILTINS_LOCATION,
7916 FIELD_DECL, get_identifier ("__va_next_stack"),
514066a1
RH		 7917 ptr_type_node);
7918
7919 DECL_FIELD_CONTEXT (f_next_o) = record;
7920 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7921 DECL_FIELD_CONTEXT (f_next_fp) = record;
7922 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7923 DECL_FIELD_CONTEXT (f_next_stack) = record;
7924
0fd2eac2 7925 TYPE_STUB_DECL (record) = type_decl;
10575b5d 7926 TYPE_NAME (record) = type_decl;
514066a1 7927 TYPE_FIELDS (record) = f_next_o;
910ad8de
NF		 7928 DECL_CHAIN (f_next_o) = f_next_o_limit;
7929 DECL_CHAIN (f_next_o_limit) = f_next_fp;
7930 DECL_CHAIN (f_next_fp) = f_next_fp_limit;
7931 DECL_CHAIN (f_next_fp_limit) = f_next_stack;
514066a1
RH		 7932
7933 layout_type (record);
7934
7935 return record;
7936}
7937
7938/* Implement `va_start' for varargs and stdarg. */
7939
d7bd8aeb 7940static void
cf277499 7941sh_va_start (tree valist, rtx nextarg)
514066a1
RH		 7942{
7943 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7944 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7945 tree t, u;
7946 int nfp, nint;
7947
fa5322fa
AO		 7948 if (TARGET_SH5)
7949 {
7950 expand_builtin_saveregs ();
e5faf155 7951 std_expand_builtin_va_start (valist, nextarg);
fa5322fa
AO		 7952 return;
7953 }
7954
61f71b34
DD		 7955 if ((! TARGET_SH2E && ! TARGET_SH4)
7956 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
514066a1 7957 {
e5faf155 7958 std_expand_builtin_va_start (valist, nextarg);
514066a1
RH		 7959 return;
7960 }
7961
7962 f_next_o = TYPE_FIELDS (va_list_type_node);
910ad8de
NF		 7963 f_next_o_limit = DECL_CHAIN (f_next_o);
7964 f_next_fp = DECL_CHAIN (f_next_o_limit);
7965 f_next_fp_limit = DECL_CHAIN (f_next_fp);
7966 f_next_stack = DECL_CHAIN (f_next_fp_limit);
514066a1 7967
47a25a46 7968 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
44de5aeb 7969 NULL_TREE);
47a25a46
RG		 7970 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7971 valist, f_next_o_limit, NULL_TREE);
7972 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7973 NULL_TREE);
7974 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7975 valist, f_next_fp_limit, NULL_TREE);
7976 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7977 valist, f_next_stack, NULL_TREE);
514066a1
RH		 7978
7979 /* Call __builtin_saveregs. */
5be014d5
AP		 7980 u = make_tree (sizetype, expand_builtin_saveregs ());
7981 u = fold_convert (ptr_type_node, u);
726a989a 7982 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
514066a1
RH		 7983 TREE_SIDE_EFFECTS (t) = 1;
7984 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7985
38173d38 7986 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
514066a1
RH		 7987 if (nfp < 8)
7988 nfp = 8 - nfp;
7989 else
7990 nfp = 0;
5be014d5
AP		 7991 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7992 size_int (UNITS_PER_WORD * nfp));
726a989a 7993 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
514066a1
RH		 7994 TREE_SIDE_EFFECTS (t) = 1;
7995 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7996
726a989a 7997 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
514066a1
RH		 7998 TREE_SIDE_EFFECTS (t) = 1;
7999 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8000
38173d38 8001 nint = crtl->args.info.arg_count[SH_ARG_INT];
514066a1
RH		 8002 if (nint < 4)
8003 nint = 4 - nint;
8004 else
8005 nint = 0;
5be014d5
AP		 8006 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
8007 size_int (UNITS_PER_WORD * nint));
726a989a 8008 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
514066a1
RH		 8009 TREE_SIDE_EFFECTS (t) = 1;
8010 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8011
8012 u = make_tree (ptr_type_node, nextarg);
726a989a 8013 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
514066a1
RH		 8014 TREE_SIDE_EFFECTS (t) = 1;
8015 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8016}
8017
917f1b7e 8018/* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
21bdb106
JR		 8019 member, return it. */
8020static tree
8021find_sole_member (tree type)
8022{
8023 tree field, member = NULL_TREE;
8024
910ad8de 8025 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
21bdb106
JR		 8026 {
8027 if (TREE_CODE (field) != FIELD_DECL)
8028 continue;
8029 if (!DECL_SIZE (field))
8030 return NULL_TREE;
8031 if (integer_zerop (DECL_SIZE (field)))
8032 continue;
8033 if (member)
8034 return NULL_TREE;
8035 member = field;
8036 }
8037 return member;
8038}
514066a1
RH		 8039/* Implement `va_arg'. */
8040
5fac2ed2 8041static tree
726a989a
RB		 8042sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
8043 gimple_seq *post_p ATTRIBUTE_UNUSED)
514066a1
RH		 8044{
8045 HOST_WIDE_INT size, rsize;
318881c0 8046 tree tmp, pptr_type_node;
0ef2c525 8047 tree addr, lab_over = NULL, result = NULL;
03603192 8048 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
11160b58 8049 tree eff_type;
5fac2ed2
RH		 8050
8051 if (pass_by_ref)
8052 type = build_pointer_type (type);
514066a1
RH		 8053
8054 size = int_size_in_bytes (type);
8055 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
8056 pptr_type_node = build_pointer_type (ptr_type_node);
8057
61f71b34
DD		 8058 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
8059 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
514066a1
RH		 8060 {
8061 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
8062 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
8063 int pass_as_float;
5fac2ed2 8064 tree lab_false;
21bdb106 8065 tree member;
514066a1
RH		 8066
8067 f_next_o = TYPE_FIELDS (va_list_type_node);
910ad8de
NF		 8068 f_next_o_limit = DECL_CHAIN (f_next_o);
8069 f_next_fp = DECL_CHAIN (f_next_o_limit);
8070 f_next_fp_limit = DECL_CHAIN (f_next_fp);
8071 f_next_stack = DECL_CHAIN (f_next_fp_limit);
514066a1 8072
47a25a46
RG		 8073 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
8074 NULL_TREE);
8075 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
8076 valist, f_next_o_limit, NULL_TREE);
8077 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
8078 valist, f_next_fp, NULL_TREE);
8079 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
8080 valist, f_next_fp_limit, NULL_TREE);
8081 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
8082 valist, f_next_stack, NULL_TREE);
514066a1 8083
6d1cb95f
R		 8084 /* Structures with a single member with a distinct mode are passed
8085 like their member. This is relevant if the latter has a REAL_TYPE
8086 or COMPLEX_TYPE type. */
11160b58
R		 8087 eff_type = type;
8088 while (TREE_CODE (eff_type) == RECORD_TYPE
8089 && (member = find_sole_member (eff_type))
21bdb106
JR		 8090 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
8091 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
8092 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
c26104e4 8093 {
21bdb106 8094 tree field_type = TREE_TYPE (member);
c26104e4 8095
11160b58
R		 8096 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
8097 eff_type = field_type;
c26104e4 8098 else
8a2209bf 8099 {
11160b58 8100 gcc_assert ((TYPE_ALIGN (eff_type)
21bdb106 8101 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
11160b58 8102 || (TYPE_ALIGN (eff_type)
21bdb106
JR		 8103 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
8104 break;
8a2209bf 8105 }
c26104e4 8106 }
5fac2ed2 8107
bdf57c40 8108 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
514066a1 8109 {
11160b58
R		 8110 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
8111 || (TREE_CODE (eff_type) == COMPLEX_TYPE
8112 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
514066a1
RH		 8113 && size <= 16));
8114 }
8115 else
8116 {
11160b58 8117 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
514066a1
RH		 8118 }
8119
5fac2ed2 8120 addr = create_tmp_var (pptr_type_node, NULL);
4c4bde29
AH		 8121 lab_false = create_artificial_label (UNKNOWN_LOCATION);
8122 lab_over = create_artificial_label (UNKNOWN_LOCATION);
514066a1 8123
70f34814 8124 valist = build_simple_mem_ref (addr);
6d1cb95f 8125
514066a1
RH		 8126 if (pass_as_float)
8127 {
a11c004b
R		 8128 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
8129 tree cmp;
11160b58 8130 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
f78ec36a 8131
8c54989a
KK		 8132 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
8133 gimplify_assign (unshare_expr (addr), tmp, pre_p);
a11c004b 8134
8c54989a 8135 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
a11c004b
R		 8136 tmp = next_fp_limit;
8137 if (size > 4 && !is_double)
8c54989a
KK		 8138 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp),
8139 unshare_expr (tmp), size_int (4 - size));
8140 tmp = build2 (GE_EXPR, boolean_type_node,
8141 unshare_expr (next_fp_tmp), unshare_expr (tmp));
47a25a46 8142 cmp = build3 (COND_EXPR, void_type_node, tmp,
8c54989a
KK		 8143 build1 (GOTO_EXPR, void_type_node,
8144 unshare_expr (lab_false)), NULL_TREE);
a11c004b
R		 8145 if (!is_double)
8146 gimplify_and_add (cmp, pre_p);
514066a1 8147
11160b58
R		 8148 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
8149 || (is_double || size == 16))
514066a1 8150 {
5be014d5
AP		 8151 tmp = fold_convert (sizetype, next_fp_tmp);
8152 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
8153 size_int (UNITS_PER_WORD));
8154 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
8c54989a
KK		 8155 unshare_expr (next_fp_tmp), tmp);
8156 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
514066a1 8157 }
a11c004b
R		 8158 if (is_double)
8159 gimplify_and_add (cmp, pre_p);
514066a1 8160
6d1cb95f 8161#ifdef FUNCTION_ARG_SCmode_WART
11160b58
R		 8162 if (TYPE_MODE (eff_type) == SCmode
8163 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
6d1cb95f 8164 {
11160b58 8165 tree subtype = TREE_TYPE (eff_type);
5fac2ed2 8166 tree real, imag;
6d1cb95f 8167
a11c004b
R		 8168 imag
8169 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
5fac2ed2 8170 imag = get_initialized_tmp_var (imag, pre_p, NULL);
6d1cb95f 8171
a11c004b
R		 8172 real
8173 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
5fac2ed2
RH		 8174 real = get_initialized_tmp_var (real, pre_p, NULL);
8175
f2a945b1
KK		 8176 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
8177 if (type != eff_type)
8178 result = build1 (VIEW_CONVERT_EXPR, type, result);
5fac2ed2 8179 result = get_initialized_tmp_var (result, pre_p, NULL);
6d1cb95f
R		 8180 }
8181#endif /* FUNCTION_ARG_SCmode_WART */
8182
8c54989a 8183 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
5fac2ed2
RH		 8184 gimplify_and_add (tmp, pre_p);
8185
8c54989a 8186 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
5fac2ed2 8187 gimplify_and_add (tmp, pre_p);
514066a1 8188
8c54989a
KK		 8189 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
8190 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8191 gimplify_assign (unshare_expr (next_fp_tmp),
8192 unshare_expr (valist), pre_p);
a11c004b 8193
8c54989a
KK		 8194 gimplify_assign (unshare_expr (valist),
8195 unshare_expr (next_fp_tmp), post_p);
a11c004b 8196 valist = next_fp_tmp;
514066a1
RH		 8197 }
8198 else
8199 {
8c54989a
KK		 8200 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
8201 unshare_expr (next_o), size_int (rsize));
8202 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
8203 unshare_expr (next_o_limit));
47a25a46 8204 tmp = build3 (COND_EXPR, void_type_node, tmp,
8c54989a
KK		 8205 build1 (GOTO_EXPR, void_type_node,
8206 unshare_expr (lab_false)),
8207 NULL_TREE);
5fac2ed2 8208 gimplify_and_add (tmp, pre_p);
514066a1 8209
8c54989a
KK		 8210 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
8211 gimplify_assign (unshare_expr (addr), tmp, pre_p);
514066a1 8212
8c54989a 8213 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
5fac2ed2
RH		 8214 gimplify_and_add (tmp, pre_p);
8215
8c54989a 8216 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
5fac2ed2 8217 gimplify_and_add (tmp, pre_p);
514066a1 8218
bdf57c40 8219 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
8c54989a
KK		 8220 gimplify_assign (unshare_expr (next_o),
8221 unshare_expr (next_o_limit), pre_p);
514066a1 8222
8c54989a
KK		 8223 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
8224 gimplify_assign (unshare_expr (addr), tmp, pre_p);
514066a1
RH		 8225 }
8226
5fac2ed2
RH		 8227 if (!result)
8228 {
8c54989a 8229 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
5fac2ed2
RH		 8230 gimplify_and_add (tmp, pre_p);
8231 }
514066a1
RH		 8232 }
8233
8234 /* ??? In va-sh.h, there had been code to make values larger than
8235 size 8 indirect. This does not match the FUNCTION_ARG macros. */
8236
5fac2ed2 8237 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
6d1cb95f
R		 8238 if (result)
8239 {
726a989a 8240 gimplify_assign (result, tmp, pre_p);
a1516d08 8241 result = build1 (NOP_EXPR, TREE_TYPE (result), result);
8c54989a 8242 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
5fac2ed2 8243 gimplify_and_add (tmp, pre_p);
6d1cb95f
R		 8244 }
8245 else
5fac2ed2 8246 result = tmp;
6d1cb95f 8247
5e039e6b 8248 if (pass_by_ref)
d6e9821f 8249 result = build_va_arg_indirect_ref (result);
5fac2ed2 8250
5e039e6b 8251 return result;
514066a1
RH		 8252}
8253
63a9de54
CB		 8254/* 64 bit floating points memory transfers are paired single precision loads
8255 or store. So DWARF information needs fixing in little endian (unless
8256 PR=SZ=1 in FPSCR). */
8257rtx
8258sh_dwarf_register_span (rtx reg)
8259{
8260 unsigned regno = REGNO (reg);
8261
8262 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
8263 return NULL_RTX;
8264
8265 return
8266 gen_rtx_PARALLEL (VOIDmode,
8267 gen_rtvec (2,
8268 gen_rtx_REG (SFmode,
8269 DBX_REGISTER_NUMBER (regno+1)),
8270 gen_rtx_REG (SFmode,
8271 DBX_REGISTER_NUMBER (regno))));
8272}
8273
6e957ac8 8274static enum machine_mode
cde0f3fd 8275sh_promote_function_mode (const_tree type, enum machine_mode mode,
d8158ff1 8276 int *punsignedp, const_tree funtype,
8a575d5a 8277 int for_return)
cde0f3fd
PB		 8278{
8279 if (sh_promote_prototypes (funtype))
d055ce45 8280 return promote_mode (type, mode, punsignedp);
cde0f3fd 8281 else
8a575d5a
PB		 8282 return default_promote_function_mode (type, mode, punsignedp, funtype,
8283 for_return);
cde0f3fd
PB		 8284}
8285
d64728cf 8286static bool
586de218 8287sh_promote_prototypes (const_tree type)
61f71b34
DD		 8288{
8289 if (TARGET_HITACHI)
8290 return 0;
8291 if (! type)
8292 return 1;
8293 return ! sh_attr_renesas_p (type);
8294}
8295
8cd5a4e0
RH		 8296/* Whether an argument must be passed by reference. On SHcompact, we
8297 pretend arguments wider than 32-bits that would have been passed in
8298 registers are passed by reference, so that an SHmedia trampoline
8299 loads them into the full 64-bits registers. */
8300
8301static int
586de218
KG		 8302shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
8303 const_tree type, bool named)
8cd5a4e0
RH		 8304{
8305 unsigned HOST_WIDE_INT size;
8306
8307 if (type)
8308 size = int_size_in_bytes (type);
8309 else
8310 size = GET_MODE_SIZE (mode);
8311
8312 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
8313 && (!named
8314 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
8315 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
8316 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
8317 && size > 4
8318 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
8319 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
8320 return size;
8321 else
8322 return 0;
8323}
8324
8325static bool
8326sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
586de218 8327 const_tree type, bool named)
8cd5a4e0
RH		 8328{
8329 if (targetm.calls.must_pass_in_stack (mode, type))
8330 return true;
8331
03603192
JR		 8332 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
8333 wants to know about pass-by-reference semantics for incoming
8334 arguments. */
8335 if (! cum)
8336 return false;
8337
8cd5a4e0
RH		 8338 if (TARGET_SHCOMPACT)
8339 {
8340 cum->byref = shcompact_byref (cum, mode, type, named);
8341 return cum->byref != 0;
8342 }
8343
8344 return false;
8345}
8346
6cdd5672
RH		 8347static bool
8348sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
586de218 8349 const_tree type, bool named ATTRIBUTE_UNUSED)
6cdd5672
RH		 8350{
8351 /* ??? How can it possibly be correct to return true only on the
8352 caller side of the equation? Is there someplace else in the
8353 sh backend that's magically producing the copies? */
8354 return (cum->outgoing
8355 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
8356 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
8357}
8358
78a52f11
RH		 8359static int
8360sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8361 tree type, bool named ATTRIBUTE_UNUSED)
8362{
8363 int words = 0;
8364
8365 if (!TARGET_SH5
8366 && PASS_IN_REG_P (*cum, mode, type)
8367 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
8368 && (ROUND_REG (*cum, mode)
8369 + (mode != BLKmode
8370 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
8371 : ROUND_ADVANCE (int_size_in_bytes (type)))
8372 > NPARM_REGS (mode)))
8373 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
8374
8375 else if (!TARGET_SHCOMPACT
8376 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
8377 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
8378
8379 return words * UNITS_PER_WORD;
8380}
8381
8382
61f71b34
DD		 8383/* Define where to put the arguments to a function.
8384 Value is zero to push the argument on the stack,
8385 or a hard register in which to store the argument.
8386
8387 MODE is the argument's machine mode.
8388 TYPE is the data type of the argument (as a tree).
8389 This is null for libcalls where that information may
8390 not be available.
8391 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8392 the preceding args and about the function being called.
8393 NAMED is nonzero if this argument is a named parameter
8394 (otherwise it is an extra parameter matching an ellipsis).
8395
8396 On SH the first args are normally in registers
8397 and the rest are pushed. Any arg that starts within the first
8398 NPARM_REGS words is at least partially passed in a register unless
8399 its data type forbids. */
8400
b64336b8 8401static rtx
cf277499 8402sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
b64336b8 8403 const_tree type, bool named)
61f71b34
DD		 8404{
8405 if (! TARGET_SH5 && mode == VOIDmode)
8406 return GEN_INT (ca->renesas_abi ? 1 : 0);
8407
8408 if (! TARGET_SH5
8409 && PASS_IN_REG_P (*ca, mode, type)
8410 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
8411 {
8412 int regno;
8413
8414 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
8415 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
8416 {
8417 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
8418 gen_rtx_REG (SFmode,
8419 BASE_ARG_REG (mode)
8420 + (ROUND_REG (*ca, mode) ^ 1)),
8421 const0_rtx);
832a3292
KH		 8422 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
8423 gen_rtx_REG (SFmode,
8424 BASE_ARG_REG (mode)
8425 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
8426 GEN_INT (4));
61f71b34
DD		 8427 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
8428 }
8429
8430 /* If the alignment of a DF value causes an SF register to be
8431 skipped, we will use that skipped register for the next SF
8432 value. */
8433 if ((TARGET_HITACHI || ca->renesas_abi)
8434 && ca->free_single_fp_reg
8435 && mode == SFmode)
8436 return gen_rtx_REG (mode, ca->free_single_fp_reg);
8437
8438 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
8439 ^ (mode == SFmode && TARGET_SH4
8440 && TARGET_LITTLE_ENDIAN != 0
8441 && ! TARGET_HITACHI && ! ca->renesas_abi);
8442 return gen_rtx_REG (mode, regno);
8443
8444 }
f676971a 8445
61f71b34
DD		 8446 if (TARGET_SH5)
8447 {
8448 if (mode == VOIDmode && TARGET_SHCOMPACT)
8449 return GEN_INT (ca->call_cookie);
8450
8451 /* The following test assumes unnamed arguments are promoted to
8452 DFmode. */
8453 if (mode == SFmode && ca->free_single_fp_reg)
8454 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
8455
8456 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
8457 && (named || ! ca->prototype_p)
8458 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
8459 {
8460 if (! ca->prototype_p && TARGET_SHMEDIA)
8461 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
8462
8463 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
8464 FIRST_FP_PARM_REG
8465 + ca->arg_count[(int) SH_ARG_FLOAT]);
8466 }
8467
8468 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
8469 && (! TARGET_SHCOMPACT
8470 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
8471 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
8472 type, named))))
8473 {
8474 return gen_rtx_REG (mode, (FIRST_PARM_REG
8475 + ca->arg_count[(int) SH_ARG_INT]));
8476 }
8477
8478 return 0;
8479 }
8480
8481 return 0;
8482}
f676971a 8483
61f71b34
DD		 8484/* Update the data in CUM to advance over an argument
8485 of mode MODE and data type TYPE.
8486 (TYPE is null for libcalls where that information may not be
8487 available.) */
8488
b64336b8 8489static void
cf277499 8490sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
b64336b8 8491 const_tree type, bool named)
61f71b34 8492{
832a3292
KH		 8493 if (ca->force_mem)
8494 ca->force_mem = 0;
8495 else if (TARGET_SH5)
8496 {
b64336b8
NF		 8497 const_tree type2 = (ca->byref && type
8498 ? TREE_TYPE (type)
8499 : type);
832a3292
KH		 8500 enum machine_mode mode2 = (ca->byref && type
8501 ? TYPE_MODE (type2)
8502 : mode);
8503 int dwords = ((ca->byref
8504 ? ca->byref
8505 : mode2 == BLKmode
8506 ? int_size_in_bytes (type2)
8507 : GET_MODE_SIZE (mode2)) + 7) / 8;
8508 int numregs = MIN (dwords, NPARM_REGS (SImode)
8509 - ca->arg_count[(int) SH_ARG_INT]);
8510
8511 if (numregs)
8512 {
8513 ca->arg_count[(int) SH_ARG_INT] += numregs;
8514 if (TARGET_SHCOMPACT
8515 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
8516 {
8517 ca->call_cookie
8518 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8519 - numregs, 1);
8520 /* N.B. We want this also for outgoing. */
8521 ca->stack_regs += numregs;
8522 }
8523 else if (ca->byref)
8524 {
8525 if (! ca->outgoing)
8526 ca->stack_regs += numregs;
8527 ca->byref_regs += numregs;
8528 ca->byref = 0;
8529 do
8530 ca->call_cookie
8531 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8532 - numregs, 2);
8533 while (--numregs);
8534 ca->call_cookie
8535 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8536 - 1, 1);
8537 }
8538 else if (dwords > numregs)
8539 {
8540 int pushregs = numregs;
8541
8542 if (TARGET_SHCOMPACT)
8543 ca->stack_regs += numregs;
8544 while (pushregs < NPARM_REGS (SImode) - 1
8545 && (CALL_COOKIE_INT_REG_GET
8546 (ca->call_cookie,
8547 NPARM_REGS (SImode) - pushregs)
8548 == 1))
8549 {
8550 ca->call_cookie
8551 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
8552 - pushregs, 1);
8553 pushregs++;
8554 }
8555 if (numregs == NPARM_REGS (SImode))
8556 ca->call_cookie
8557 |= CALL_COOKIE_INT_REG (0, 1)
8558 | CALL_COOKIE_STACKSEQ (numregs - 1);
8559 else
8560 ca->call_cookie
8561 |= CALL_COOKIE_STACKSEQ (numregs);
8562 }
8563 }
8564 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
8565 && (named || ! ca->prototype_p))
8566 {
8567 if (mode2 == SFmode && ca->free_single_fp_reg)
8568 ca->free_single_fp_reg = 0;
8569 else if (ca->arg_count[(int) SH_ARG_FLOAT]
8570 < NPARM_REGS (SFmode))
8571 {
8572 int numfpregs
8573 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
8574 NPARM_REGS (SFmode)
8575 - ca->arg_count[(int) SH_ARG_FLOAT]);
8576
8577 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
8578
8579 if (TARGET_SHCOMPACT && ! ca->prototype_p)
8580 {
8581 if (ca->outgoing && numregs > 0)
8582 do
8583 {
8584 ca->call_cookie
8585 |= (CALL_COOKIE_INT_REG
8586 (ca->arg_count[(int) SH_ARG_INT]
8587 - numregs + ((numfpregs - 2) / 2),
8588 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
8589 - numfpregs) / 2));
8590 }
8591 while (numfpregs -= 2);
8592 }
8593 else if (mode2 == SFmode && (named)
8594 && (ca->arg_count[(int) SH_ARG_FLOAT]
8595 < NPARM_REGS (SFmode)))
8596 ca->free_single_fp_reg
8597 = FIRST_FP_PARM_REG - numfpregs
8598 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
8599 }
8600 }
8601 return;
8602 }
8603
8604 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
8605 {
8606 /* Note that we've used the skipped register. */
8607 if (mode == SFmode && ca->free_single_fp_reg)
8608 {
8609 ca->free_single_fp_reg = 0;
8610 return;
8611 }
8612 /* When we have a DF after an SF, there's an SF register that get
8613 skipped in order to align the DF value. We note this skipped
8614 register, because the next SF value will use it, and not the
8615 SF that follows the DF. */
8616 if (mode == DFmode
8617 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
8618 {
8619 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
8620 + BASE_ARG_REG (mode));
8621 }
8622 }
8623
157371cf 8624 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
832a3292
KH		 8625 || PASS_IN_REG_P (*ca, mode, type))
8626 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
8627 = (ROUND_REG (*ca, mode)
8628 + (mode == BLKmode
8629 ? ROUND_ADVANCE (int_size_in_bytes (type))
8630 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
61f71b34
DD		 8631}
8632
61f71b34
DD		 8633/* The Renesas calling convention doesn't quite fit into this scheme since
8634 the address is passed like an invisible argument, but one that is always
8635 passed in memory. */
8636static rtx
cf277499 8637sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
61f71b34
DD		 8638{
8639 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8640 return 0;
8641 return gen_rtx_REG (Pmode, 2);
8642}
8643
d64728cf
AS		 8644/* Worker function for TARGET_FUNCTION_VALUE.
8645
8646 For the SH, this is like LIBCALL_VALUE, except that we must change the
8647 mode like PROMOTE_MODE does.
8648 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
8649 tested here has to be kept in sync with the one in explow.c:promote_mode.
8650*/
8651
8652static rtx
8653sh_function_value (const_tree valtype,
8654 const_tree fn_decl_or_type,
8655 bool outgoing ATTRIBUTE_UNUSED)
8656{
8657 if (fn_decl_or_type
8658 && !DECL_P (fn_decl_or_type))
8659 fn_decl_or_type = NULL;
8660
8661 return gen_rtx_REG (
8662 ((GET_MODE_CLASS (TYPE_MODE (valtype)) == MODE_INT
8663 && GET_MODE_SIZE (TYPE_MODE (valtype)) < 4
8664 && (TREE_CODE (valtype) == INTEGER_TYPE
8665 || TREE_CODE (valtype) == ENUMERAL_TYPE
8666 || TREE_CODE (valtype) == BOOLEAN_TYPE
8667 || TREE_CODE (valtype) == REAL_TYPE
8668 || TREE_CODE (valtype) == OFFSET_TYPE))
8669 && sh_promote_prototypes (fn_decl_or_type)
8670 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (valtype)),
8671 BASE_RETURN_VALUE_REG (TYPE_MODE (valtype)));
8672}
8673
8674/* Worker function for TARGET_LIBCALL_VALUE. */
8675
8676static rtx
8677sh_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8678{
8679 return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG (mode));
8680}
8681
e7a8f681 8682/* Return true if N is a possible register number of function value. */
d64728cf 8683
e7a8f681 8684static bool
d64728cf
AS		 8685sh_function_value_regno_p (const unsigned int regno)
8686{
8687 return ((regno) == FIRST_RET_REG
8688 || (TARGET_SH2E && (regno) == FIRST_FP_RET_REG)
8689 || (TARGET_SHMEDIA_FPU && (regno) == FIRST_FP_RET_REG));
8690}
8691
bd5bd7ac
KH		 8692/* Worker function for TARGET_RETURN_IN_MEMORY. */
8693
61f71b34 8694static bool
586de218 8695sh_return_in_memory (const_tree type, const_tree fndecl)
61f71b34
DD		 8696{
8697 if (TARGET_SH5)
8698 {
8699 if (TYPE_MODE (type) == BLKmode)
8700 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
8701 else
8702 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
8703 }
8704 else
8705 {
8706 return (TYPE_MODE (type) == BLKmode
8707 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8708 && TREE_CODE (type) == RECORD_TYPE));
8709 }
8710}
8711
8712/* We actually emit the code in sh_expand_prologue. We used to use
8713 a static variable to flag that we need to emit this code, but that
8714 doesn't when inlining, when functions are deferred and then emitted
8715 later. Fortunately, we already have two flags that are part of struct
8716 function that tell if a function uses varargs or stdarg. */
8717static void
49616835
JR		 8718sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
8719 enum machine_mode mode,
8720 tree type,
8721 int *pretend_arg_size,
cf277499 8722 int second_time ATTRIBUTE_UNUSED)
61f71b34 8723{
e3b5732b 8724 gcc_assert (cfun->stdarg);
49616835
JR		 8725 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8726 {
8727 int named_parm_regs, anon_parm_regs;
8728
8729 named_parm_regs = (ROUND_REG (*ca, mode)
8730 + (mode == BLKmode
8731 ? ROUND_ADVANCE (int_size_in_bytes (type))
8732 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
8733 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
8734 if (anon_parm_regs > 0)
8735 *pretend_arg_size = anon_parm_regs * 4;
8736 }
61f71b34
DD		 8737}
8738
8739static bool
cf277499 8740sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
61f71b34
DD		 8741{
8742 return TARGET_SH5;
8743}
8744
8745static bool
cf277499 8746sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
61f71b34
DD		 8747{
8748 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
8749}
8750
8751
0d7e008e
SC		 8752/* Define the offset between two registers, one to be eliminated, and
8753 the other its replacement, at the start of a routine. */
8754
8755int
cf277499 8756initial_elimination_offset (int from, int to)
0d7e008e
SC		 8757{
8758 int regs_saved;
fa5322fa 8759 int regs_saved_rounding = 0;
0d7e008e 8760 int total_saved_regs_space;
e5f8d4c0 8761 int total_auto_space;
1245df60 8762 int save_flags = target_flags;
fa5322fa 8763 int copy_flags;
490dbac7 8764 HARD_REG_SET live_regs_mask;
fe3ad572
SC		 8765
8766 shmedia_space_reserved_for_target_registers = false;
490dbac7 8767 regs_saved = calc_live_regs (&live_regs_mask);
fa5322fa 8768 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
fe3ad572
SC		 8769
8770 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
8771 {
8772 shmedia_space_reserved_for_target_registers = true;
8773 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
8774 }
8775
fa5322fa
AO		 8776 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
8777 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8778 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
8e87e161 8779
fa5322fa
AO		 8780 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8781 copy_flags = target_flags;
1245df60 8782 target_flags = save_flags;
1a95a963 8783
fa5322fa 8784 total_saved_regs_space = regs_saved + regs_saved_rounding;
b9654711 8785
96a2347e 8786 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
fa5322fa 8787 return total_saved_regs_space + total_auto_space
38173d38 8788 + crtl->args.info.byref_regs * 8;
8aa2a305 8789
0d7e008e 8790 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
fa5322fa 8791 return total_saved_regs_space + total_auto_space
38173d38 8792 + crtl->args.info.byref_regs * 8;
8aa2a305
JW		 8793
8794 /* Initial gap between fp and sp is 0. */
96a2347e 8795 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8aa2a305
JW		 8796 return 0;
8797
96a2347e
KK		 8798 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8799 return rounded_frame_size (0);
8800
8801 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8802 return rounded_frame_size (0);
8803
f5b9e7c9 8804 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
96a2347e
KK		 8805 && (to == HARD_FRAME_POINTER_REGNUM
8806 || to == STACK_POINTER_REGNUM));
f5b9e7c9 8807 if (TARGET_SH5)
d042370e 8808 {
f5b9e7c9
NS		 8809 int n = total_saved_regs_space;
8810 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
8811 save_schedule schedule;
8812 save_entry *entry;
8813
8814 n += total_auto_space;
8815
8816 /* If it wasn't saved, there's not much we can do. */
8817 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
8818 return n;
8819
8820 target_flags = copy_flags;
8821
8822 sh5_schedule_saves (&live_regs_mask, &schedule, n);
8823 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
8824 if (entry->reg == pr_reg)
8825 {
8826 target_flags = save_flags;
8827 return entry->offset;
8828 }
8829 gcc_unreachable ();
d042370e 8830 }
f5b9e7c9
NS		 8831 else
8832 return total_auto_space;
0d7e008e 8833}
3217af3e
KK		 8834
8835/* Parse the -mfixed-range= option string. */
8836void
8837sh_fix_range (const char *const_str)
8838{
8839 int i, first, last;
8840 char *str, *dash, *comma;
8841
8842 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8843 REG2 are either register names or register numbers. The effect
8844 of this option is to mark the registers in the range from REG1 to
8845 REG2 as ``fixed'' so they won't be used by the compiler. */
8846
8847 i = strlen (const_str);
8848 str = (char *) alloca (i + 1);
8849 memcpy (str, const_str, i + 1);
8850
8851 while (1)
8852 {
8853 dash = strchr (str, '-');
8854 if (!dash)
8855 {
8856 warning (0, "value of -mfixed-range must have form REG1-REG2");
8857 return;
8858 }
8859 *dash = '\0';
8860 comma = strchr (dash + 1, ',');
8861 if (comma)
8862 *comma = '\0';
8863
8864 first = decode_reg_name (str);
8865 if (first < 0)
8866 {
8867 warning (0, "unknown register name: %s", str);
8868 return;
8869 }
8870
8871 last = decode_reg_name (dash + 1);
8872 if (last < 0)
8873 {
8874 warning (0, "unknown register name: %s", dash + 1);
8875 return;
8876 }
8877
8878 *dash = '-';
8879
8880 if (first > last)
8881 {
8882 warning (0, "%s-%s is an empty range", str, dash + 1);
8883 return;
8884 }
8885
8886 for (i = first; i <= last; ++i)
8887 fixed_regs[i] = call_used_regs[i] = 1;
8888
8889 if (!comma)
8890 break;
8891
8892 *comma = ',';
8893 str = comma + 1;
8894 }
8895}
8aa2a305 8896\f
a6ab9fc0 8897/* Insert any deferred function attributes from earlier pragmas. */
12a68f1f 8898static void
cf277499 8899sh_insert_attributes (tree node, tree *attributes)
157131d7 8900{
a6ab9fc0
R		 8901 tree attrs;
8902
8903 if (TREE_CODE (node) != FUNCTION_DECL)
157131d7
SC		 8904 return;
8905
8906 /* We are only interested in fields. */
6615c446 8907 if (!DECL_P (node))
157131d7
SC		 8908 return;
8909
a6ab9fc0
R		 8910 /* Append the attributes to the deferred attributes. */
8911 *sh_deferred_function_attributes_tail = *attributes;
8912 attrs = sh_deferred_function_attributes;
8913 if (!attrs)
8914 return;
8915
8916 /* Some attributes imply or require the interrupt attribute. */
8917 if (!lookup_attribute ("interrupt_handler", attrs)
8918 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8919 {
8920 /* If we have a trapa_handler, but no interrupt_handler attribute,
8921 insert an interrupt_handler attribute. */
8922 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8923 /* We can't use sh_pr_interrupt here because that's not in the
8924 java frontend. */
8925 attrs
8926 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
561642fa
AP		 8927 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8928 if the interrupt attribute is missing, we ignore the attribute
8929 and warn. */
a6ab9fc0
R		 8930 else if (lookup_attribute ("sp_switch", attrs)
8931 || lookup_attribute ("trap_exit", attrs)
561642fa
AP		 8932 || lookup_attribute ("nosave_low_regs", attrs)
8933 || lookup_attribute ("resbank", attrs))
a6ab9fc0
R		 8934 {
8935 tree *tail;
8936
8937 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8938 {
8939 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8940 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
561642fa
AP		 8941 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8942 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
a6ab9fc0 8943 warning (OPT_Wattributes,
29d08eba
JM		 8944 "%qE attribute only applies to interrupt functions",
8945 TREE_PURPOSE (attrs));
a6ab9fc0
R		 8946 else
8947 {
8948 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8949 NULL_TREE);
8950 tail = &TREE_CHAIN (*tail);
8951 }
8952 }
8953 attrs = *attributes;
8954 }
8955 }
8956
8957 /* Install the processed list. */
8958 *attributes = attrs;
8959
8960 /* Clear deferred attributes. */
8961 sh_deferred_function_attributes = NULL_TREE;
8962 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
157131d7
SC		 8963
8964 return;
8965}
8966
91d231cb 8967/* Supported attributes:
4408efce
JL		 8968
8969 interrupt_handler -- specifies this function is an interrupt handler.
8970
a6ab9fc0
R		 8971 trapa_handler - like above, but don't save all registers.
8972
4408efce
JL		 8973 sp_switch -- specifies an alternate stack for an interrupt handler
8974 to run on.
8975
956d6950 8976 trap_exit -- use a trapa to exit an interrupt function instead of
61f71b34
DD		 8977 an rte instruction.
8978
a6ab9fc0
R		 8979 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8980 This is useful on the SH3 and upwards,
8981 which has a separate set of low regs for User and Supervisor modes.
8982 This should only be used for the lowest level of interrupts. Higher levels
8983 of interrupts must save the registers in case they themselves are
8984 interrupted.
8985
61f71b34
DD		 8986 renesas -- use Renesas calling/layout conventions (functions and
8987 structures).
8988
561642fa
AP		 8989 resbank -- In case of an ISR, use a register bank to save registers
8990 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
61f71b34 8991*/
4408efce 8992
561642fa
AP		 8993/* Handle a 'resbank' attribute. */
8994static tree
8995sh_handle_resbank_handler_attribute (tree * node, tree name,
8996 tree args ATTRIBUTE_UNUSED,
8997 int flags ATTRIBUTE_UNUSED,
8998 bool * no_add_attrs)
8999{
9000 if (!TARGET_SH2A)
9001 {
29d08eba
JM		 9002 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
9003 name);
561642fa
AP		 9004 *no_add_attrs = true;
9005 }
9006 if (TREE_CODE (*node) != FUNCTION_DECL)
9007 {
29d08eba
JM		 9008 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9009 name);
561642fa
AP		 9010 *no_add_attrs = true;
9011 }
9012
9013 return NULL_TREE;
9014}
9015
91d231cb
JM		 9016/* Handle an "interrupt_handler" attribute; arguments as in
9017 struct attribute_spec.handler. */
9018static tree
cf277499 9019sh_handle_interrupt_handler_attribute (tree *node, tree name,
561642fa
AP		 9020 tree args ATTRIBUTE_UNUSED,
9021 int flags ATTRIBUTE_UNUSED,
9022 bool *no_add_attrs)
91d231cb
JM		 9023{
9024 if (TREE_CODE (*node) != FUNCTION_DECL)
4408efce 9025 {
29d08eba
JM		 9026 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9027 name);
91d231cb 9028 *no_add_attrs = true;
4408efce 9029 }
58ab7171
R		 9030 else if (TARGET_SHCOMPACT)
9031 {
9032 error ("attribute interrupt_handler is not compatible with -m5-compact");
9033 *no_add_attrs = true;
9034 }
4408efce 9035
91d231cb
JM		 9036 return NULL_TREE;
9037}
9038
561642fa
AP		 9039/* Handle an 'function_vector' attribute; arguments as in
9040 struct attribute_spec.handler. */
9041static tree
9042sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
9043 tree args ATTRIBUTE_UNUSED,
9044 int flags ATTRIBUTE_UNUSED,
9045 bool * no_add_attrs)
9046{
9047 if (!TARGET_SH2A)
9048 {
29d08eba
JM		 9049 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
9050 name);
561642fa
AP		 9051 *no_add_attrs = true;
9052 }
9053 else if (TREE_CODE (*node) != FUNCTION_DECL)
9054 {
29d08eba
JM		 9055 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9056 name);
561642fa
AP		 9057 *no_add_attrs = true;
9058 }
9059 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
9060 {
9061 /* The argument must be a constant integer. */
9062 warning (OPT_Wattributes,
29d08eba
JM		 9063 "%qE attribute argument not an integer constant",
9064 name);
561642fa
AP		 9065 *no_add_attrs = true;
9066 }
9067 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
9068 {
9069 /* The argument value must be between 0 to 255. */
9070 warning (OPT_Wattributes,
29d08eba
JM		 9071 "%qE attribute argument should be between 0 to 255",
9072 name);
561642fa
AP		 9073 *no_add_attrs = true;
9074 }
9075 return NULL_TREE;
9076}
9077
9078/* Returns 1 if current function has been assigned the attribute
9079 'function_vector'. */
9080int
9081sh2a_is_function_vector_call (rtx x)
9082{
9083 if (GET_CODE (x) == SYMBOL_REF
9084 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
9085 {
9086 tree tr = SYMBOL_REF_DECL (x);
9087
9088 if (sh2a_function_vector_p (tr))
9089 return 1;
9090 }
9091
9092 return 0;
9093}
9094
9095/* Returns the function vector number, if the the attribute
9096 'function_vector' is assigned, otherwise returns zero. */
9097int
9098sh2a_get_function_vector_number (rtx x)
9099{
9100 int num;
9101 tree list, t;
9102
9103 if ((GET_CODE (x) == SYMBOL_REF)
9104 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
9105 {
9106 t = SYMBOL_REF_DECL (x);
9107
9108 if (TREE_CODE (t) != FUNCTION_DECL)
9109 return 0;
9110
9111 list = SH_ATTRIBUTES (t);
9112 while (list)
9113 {
9114 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
9115 {
9116 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
9117 return num;
9118 }
9119
9120 list = TREE_CHAIN (list);
9121 }
9122
9123 return 0;
9124 }
9125 else
9126 return 0;
9127}
9128
91d231cb
JM		 9129/* Handle an "sp_switch" attribute; arguments as in
9130 struct attribute_spec.handler. */
9131static tree
cf277499
SB		 9132sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
9133 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
91d231cb
JM		 9134{
9135 if (TREE_CODE (*node) != FUNCTION_DECL)
9136 {
29d08eba
JM		 9137 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9138 name);
91d231cb
JM		 9139 *no_add_attrs = true;
9140 }
91d231cb
JM		 9141 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
9142 {
4408efce 9143 /* The argument must be a constant string. */
29d08eba
JM		 9144 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
9145 name);
91d231cb
JM		 9146 *no_add_attrs = true;
9147 }
4408efce 9148
91d231cb
JM		 9149 return NULL_TREE;
9150}
9151
9152/* Handle an "trap_exit" attribute; arguments as in
9153 struct attribute_spec.handler. */
9154static tree
cf277499
SB		 9155sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
9156 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
91d231cb
JM		 9157{
9158 if (TREE_CODE (*node) != FUNCTION_DECL)
9159 {
29d08eba
JM		 9160 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9161 name);
91d231cb
JM		 9162 *no_add_attrs = true;
9163 }
a6ab9fc0
R		 9164 /* The argument specifies a trap number to be used in a trapa instruction
9165 at function exit (instead of an rte instruction). */
91d231cb
JM		 9166 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
9167 {
4408efce 9168 /* The argument must be a constant integer. */
29d08eba
JM		 9169 warning (OPT_Wattributes, "%qE attribute argument not an "
9170 "integer constant", name);
91d231cb
JM		 9171 *no_add_attrs = true;
9172 }
318881c0 9173
91d231cb 9174 return NULL_TREE;
4408efce
JL		 9175}
9176
61f71b34 9177static tree
cf277499
SB		 9178sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
9179 tree name ATTRIBUTE_UNUSED,
9180 tree args ATTRIBUTE_UNUSED,
9181 int flags ATTRIBUTE_UNUSED,
9182 bool *no_add_attrs ATTRIBUTE_UNUSED)
61f71b34
DD		 9183{
9184 return NULL_TREE;
9185}
9186
9187/* True if __attribute__((renesas)) or -mrenesas. */
9188int
586de218 9189sh_attr_renesas_p (const_tree td)
61f71b34
DD		 9190{
9191 if (TARGET_HITACHI)
9192 return 1;
9193 if (td == 0)
9194 return 0;
9195 if (DECL_P (td))
9196 td = TREE_TYPE (td);
a11c004b
R		 9197 if (td == error_mark_node)
9198 return 0;
61f71b34
DD		 9199 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
9200 != NULL_TREE);
9201}
9202
9203/* True if __attribute__((renesas)) or -mrenesas, for the current
9204 function. */
9205int
cf277499 9206sh_cfun_attr_renesas_p (void)
61f71b34
DD		 9207{
9208 return sh_attr_renesas_p (current_function_decl);
9209}
9210
e3ba8d11 9211int
cf277499 9212sh_cfun_interrupt_handler_p (void)
e3ba8d11
R		 9213{
9214 return (lookup_attribute ("interrupt_handler",
9215 DECL_ATTRIBUTES (current_function_decl))
9216 != NULL_TREE);
9217}
bcc8cc82 9218
561642fa
AP		 9219/* Returns 1 if FUNC has been assigned the attribute
9220 "function_vector". */
9221int
9222sh2a_function_vector_p (tree func)
9223{
9224 tree list;
9225 if (TREE_CODE (func) != FUNCTION_DECL)
9226 return 0;
9227
9228 list = SH_ATTRIBUTES (func);
9229 while (list)
9230 {
9231 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
9232 return 1;
9233
9234 list = TREE_CHAIN (list);
9235 }
9236 return 0;
9237}
9238
9239/* Returns TRUE if given tree has the "resbank" attribute. */
9240
9241int
9242sh_cfun_resbank_handler_p (void)
9243{
9244 return ((lookup_attribute ("resbank",
9245 DECL_ATTRIBUTES (current_function_decl))
9246 != NULL_TREE)
9247 && (lookup_attribute ("interrupt_handler",
9248 DECL_ATTRIBUTES (current_function_decl))
9249 != NULL_TREE) && TARGET_SH2A);
9250}
9251
8d932be3 9252/* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
73a4d10b 9253
8d932be3
RS		 9254static const char *
9255sh_check_pch_target_flags (int old_flags)
9256{
c0fb94d7
RS		 9257 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
9258 | MASK_SH_E | MASK_HARD_SH4
9259 | MASK_FPU_SINGLE | MASK_SH4))
9260 return _("created and used with different architectures / ABIs");
9261 if ((old_flags ^ target_flags) & MASK_HITACHI)
9262 return _("created and used with different ABIs");
9263 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
9264 return _("created and used with different endianness");
bcc8cc82 9265 return NULL;
bcc8cc82 9266}
0d7e008e 9267\f
8aa2a305 9268/* Predicates used by the templates. */
0d7e008e 9269
8aa2a305
JW		 9270/* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
9271 Used only in general_movsrc_operand. */
0d7e008e 9272
8aa2a305 9273int
cf277499 9274system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
0d7e008e 9275{
8aa2a305 9276 switch (REGNO (op))
0d7e008e 9277 {
8aa2a305
JW		 9278 case PR_REG:
9279 case MACL_REG:
9280 case MACH_REG:
9281 return 1;
0d7e008e 9282 }
8aa2a305 9283 return 0;
0d7e008e 9284}
0d7e008e 9285
1a95a963
JW		 9286/* Nonzero if OP is a floating point value with value 0.0. */
9287
9288int
cf277499 9289fp_zero_operand (rtx op)
d3ae8277 9290{
1a95a963 9291 REAL_VALUE_TYPE r;
d3ae8277 9292
1a95a963
JW		 9293 if (GET_MODE (op) != SFmode)
9294 return 0;
9295
9296 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
e4fa6b06 9297 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
d3ae8277
SC		 9298}
9299
1a95a963 9300/* Nonzero if OP is a floating point value with value 1.0. */
d3ae8277
SC		 9301
9302int
cf277499 9303fp_one_operand (rtx op)
d3ae8277 9304{
1a95a963
JW		 9305 REAL_VALUE_TYPE r;
9306
9307 if (GET_MODE (op) != SFmode)
9308 return 0;
9309
9310 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
9311 return REAL_VALUES_EQUAL (r, dconst1);
d3ae8277 9312}
1245df60 9313
7a61cf6f 9314/* In general mode switching is used. If we are
9f09b1f2
R		 9315 compiling without -mfmovd, movsf_ie isn't taken into account for
9316 mode switching. We could check in machine_dependent_reorg for
9317 cases where we know we are in single precision mode, but there is
9318 interface to find that out during reload, so we must avoid
9319 choosing an fldi alternative during reload and thus failing to
9320 allocate a scratch register for the constant loading. */
9321int
cf277499 9322fldi_ok (void)
9f09b1f2 9323{
7a61cf6f 9324 return 1;
9f09b1f2
R		 9325}
9326
225e4f43 9327int
cf277499 9328tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
225e4f43
R		 9329{
9330 enum rtx_code code = GET_CODE (op);
9331 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
9332}
9333
463f02cd 9334/* Return the TLS type for TLS symbols, 0 for otherwise. */
81f40b79 9335enum tls_model
cf277499 9336tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
463f02cd 9337{
463f02cd 9338 if (GET_CODE (op) != SYMBOL_REF)
81f40b79 9339 return TLS_MODEL_NONE;
675ff4c7 9340 return SYMBOL_REF_TLS_MODEL (op);
463f02cd 9341}
1245df60 9342\f
33f7f353 9343/* Return the destination address of a branch. */
f676971a 9344
318881c0 9345static int
cf277499 9346branch_dest (rtx branch)
1245df60 9347{
33f7f353
JR		 9348 rtx dest = SET_SRC (PATTERN (branch));
9349 int dest_uid;
1245df60
R		 9350
9351 if (GET_CODE (dest) == IF_THEN_ELSE)
9352 dest = XEXP (dest, 1);
9353 dest = XEXP (dest, 0);
9354 dest_uid = INSN_UID (dest);
9d98a694 9355 return INSN_ADDRESSES (dest_uid);
1245df60 9356}
a55e9d2b 9357\f
5e7a8ee0 9358/* Return nonzero if REG is not used after INSN.
a55e9d2b 9359 We assume REG is a reload reg, and therefore does
8b760293 9360 not live past labels. It may live past calls or jumps though. */
a55e9d2b 9361int
cf277499 9362reg_unused_after (rtx reg, rtx insn)
a55e9d2b 9363{
8783b15e 9364 enum rtx_code code;
a55e9d2b
RK		 9365 rtx set;
9366
9367 /* If the reg is set by this instruction, then it is safe for our
9368 case. Disregard the case where this is a store to memory, since
9369 we are checking a register used in the store address. */
9370 set = single_set (insn);
f3536097 9371 if (set && !MEM_P (SET_DEST (set))
a55e9d2b
RK		 9372 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9373 return 1;
9374
318881c0 9375 while ((insn = NEXT_INSN (insn)))
a55e9d2b 9376 {
ec8e098d
PB		 9377 rtx set;
9378 if (!INSN_P (insn))
9379 continue;
9380
a55e9d2b 9381 code = GET_CODE (insn);
8783b15e 9382
c8f6f18d
RK		 9383#if 0
9384 /* If this is a label that existed before reload, then the register
9385 if dead here. However, if this is a label added by reorg, then
9386 the register may still be live here. We can't tell the difference,
9387 so we just ignore labels completely. */
8783b15e 9388 if (code == CODE_LABEL)
a55e9d2b 9389 return 1;
c8f6f18d
RK		 9390 /* else */
9391#endif
a55e9d2b 9392
8b760293
JW		 9393 if (code == JUMP_INSN)
9394 return 0;
9395
8783b15e
RK		 9396 /* If this is a sequence, we must handle them all at once.
9397 We could have for instance a call that sets the target register,
e03f5d43 9398 and an insn in a delay slot that uses the register. In this case,
8783b15e 9399 we must return 0. */
8b760293 9400 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
a55e9d2b 9401 {
8783b15e
RK		 9402 int i;
9403 int retval = 0;
9404
9405 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9406 {
9407 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
9408 rtx set = single_set (this_insn);
9409
f3536097 9410 if (CALL_P (this_insn))
8783b15e 9411 code = CALL_INSN;
f3536097 9412 else if (JUMP_P (this_insn))
38f35781
JW		 9413 {
9414 if (INSN_ANNULLED_BRANCH_P (this_insn))
9415 return 0;
9416 code = JUMP_INSN;
9417 }
a55e9d2b 9418
8783b15e
RK		 9419 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9420 return 0;
9421 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9422 {
f3536097 9423 if (!MEM_P (SET_DEST (set)))
8783b15e
RK		 9424 retval = 1;
9425 else
9426 return 0;
9427 }
9428 if (set == 0
9429 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
9430 return 0;
9431 }
9432 if (retval == 1)
9433 return 1;
38f35781
JW		 9434 else if (code == JUMP_INSN)
9435 return 0;
8783b15e 9436 }
a55e9d2b 9437
ec8e098d
PB		 9438 set = single_set (insn);
9439 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9440 return 0;
9441 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
f3536097 9442 return !MEM_P (SET_DEST (set));
ec8e098d
PB		 9443 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9444 return 0;
8783b15e 9445
62164eb4 9446 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
8783b15e 9447 return 1;
a55e9d2b
RK		 9448 }
9449 return 1;
9450}
225e4f43 9451\f
c5b9ef02 9452#include "ggc.h"
225e4f43 9453
e2500fed 9454static GTY(()) rtx fpscr_rtx;
225e4f43 9455rtx
cf277499 9456get_fpscr_rtx (void)
225e4f43 9457{
225e4f43
R		 9458 if (! fpscr_rtx)
9459 {
c0d4e710 9460 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
225e4f43 9461 REG_USERVAR_P (fpscr_rtx) = 1;
225e4f43
R		 9462 mark_user_reg (fpscr_rtx);
9463 }
9464 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
9465 mark_user_reg (fpscr_rtx);
9466 return fpscr_rtx;
9467}
9468
24c2fde2
RH		 9469static GTY(()) tree fpscr_values;
9470
9471static void
9472emit_fpu_switch (rtx scratch, int index)
9473{
9474 rtx dst, src;
9475
9476 if (fpscr_values == NULL)
9477 {
9478 tree t;
9479
9480 t = build_index_type (integer_one_node);
9481 t = build_array_type (integer_type_node, t);
4c4bde29
AH		 9482 t = build_decl (BUILTINS_LOCATION,
9483 VAR_DECL, get_identifier ("__fpscr_values"), t);
24c2fde2
RH		 9484 DECL_ARTIFICIAL (t) = 1;
9485 DECL_IGNORED_P (t) = 1;
9486 DECL_EXTERNAL (t) = 1;
9487 TREE_STATIC (t) = 1;
a5f5c6be 9488 TREE_PUBLIC (t) = 1;
24c2fde2
RH		 9489 TREE_USED (t) = 1;
9490
9491 fpscr_values = t;
9492 }
9493
9494 src = DECL_RTL (fpscr_values);
b3a13419 9495 if (!can_create_pseudo_p ())
24c2fde2
RH		 9496 {
9497 emit_move_insn (scratch, XEXP (src, 0));
9498 if (index != 0)
9499 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
9500 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
9501 }
9502 else
9503 src = adjust_address (src, PSImode, index * 4);
9504
9505 dst = get_fpscr_rtx ();
9506 emit_move_insn (dst, src);
9507}
9508
225e4f43 9509void
cf277499 9510emit_sf_insn (rtx pat)
225e4f43 9511{
225e4f43 9512 emit_insn (pat);
225e4f43
R		 9513}
9514
9515void
cf277499 9516emit_df_insn (rtx pat)
225e4f43 9517{
225e4f43 9518 emit_insn (pat);
225e4f43
R		 9519}
9520
9521void
cf277499 9522expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
225e4f43
R		 9523{
9524 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9525}
9526
9527void
cf277499 9528expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
225e4f43
R		 9529{
9530 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
9531 get_fpscr_rtx ()));
9532}
9533
9534void
cf277499 9535expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
225e4f43
R		 9536{
9537 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9538}
9539
9540void
cf277499 9541expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
225e4f43
R		 9542{
9543 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
832a3292 9544 get_fpscr_rtx ()));
225e4f43 9545}
225e4f43 9546\f
cf277499 9547static rtx get_free_reg (HARD_REG_SET);
9f09b1f2
R		 9548
9549/* This function returns a register to use to load the address to load
9550 the fpscr from. Currently it always returns r1 or r7, but when we are
9551 able to use pseudo registers after combine, or have a better mechanism
9552 for choosing a register, it should be done here. */
9553/* REGS_LIVE is the liveness information for the point for which we
9554 need this allocation. In some bare-bones exit blocks, r1 is live at the
9555 start. We can even have all of r0..r3 being live:
9556__complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
9557 INSN before which new insns are placed with will clobber the register
9558 we return. If a basic block consists only of setting the return value
9559 register to a pseudo and using that register, the return value is not
9560 live before or after this block, yet we we'll insert our insns right in
9561 the middle. */
225e4f43 9562
9f09b1f2 9563static rtx
cf277499 9564get_free_reg (HARD_REG_SET regs_live)
225e4f43 9565{
9f09b1f2
R		 9566 if (! TEST_HARD_REG_BIT (regs_live, 1))
9567 return gen_rtx_REG (Pmode, 1);
225e4f43 9568
42db504c 9569 /* Hard reg 1 is live; since this is a small register classes target,
9f09b1f2 9570 there shouldn't be anything but a jump before the function end. */
f5b9e7c9
NS		 9571 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
9572 return gen_rtx_REG (Pmode, 7);
9f09b1f2 9573}
225e4f43 9574
f676971a 9575/* This function will set the fpscr from memory.
9f09b1f2
R		 9576 MODE is the mode we are setting it to. */
9577void
cf277499 9578fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
9f09b1f2 9579{
81f40b79 9580 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
24c2fde2 9581 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
5e77c6f9 9582 rtx addr_reg;
9f09b1f2 9583
b3a13419 9584 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
24c2fde2 9585 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
225e4f43 9586}
9342c0c4
R		 9587
9588/* Is the given character a logical line separator for the assembler? */
9589#ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
980d8882 9590#define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
9342c0c4
R		 9591#endif
9592
9593int
cf277499 9594sh_insn_length_adjustment (rtx insn)
9342c0c4
R		 9595{
9596 /* Instructions with unfilled delay slots take up an extra two bytes for
9597 the nop in the delay slot. */
f3536097 9598 if (((NONJUMP_INSN_P (insn)
c1b92d09
R		 9599 && GET_CODE (PATTERN (insn)) != USE
9600 && GET_CODE (PATTERN (insn)) != CLOBBER)
f3536097 9601 || CALL_P (insn)
69b18163 9602 || (JUMP_P (insn) && !JUMP_TABLE_DATA_P (insn)))
9342c0c4
R		 9603 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
9604 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
9605 return 2;
9606
3a8699c7
AO		 9607 /* SH2e has a bug that prevents the use of annulled branches, so if
9608 the delay slot is not filled, we'll have to put a NOP in it. */
b757d36f 9609 if (sh_cpu_attr == CPU_SH2E
69b18163 9610 && JUMP_P (insn) && !JUMP_TABLE_DATA_P (insn)
3a8699c7
AO		 9611 && get_attr_type (insn) == TYPE_CBRANCH
9612 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
9613 return 2;
9614
9342c0c4 9615 /* sh-dsp parallel processing insn take four bytes instead of two. */
f676971a 9616
f3536097 9617 if (NONJUMP_INSN_P (insn))
9342c0c4
R		 9618 {
9619 int sum = 0;
9620 rtx body = PATTERN (insn);
0a2aaacc 9621 const char *templ;
8ceaac3c 9622 char c;
9342c0c4
R		 9623 int maybe_label = 1;
9624
9625 if (GET_CODE (body) == ASM_INPUT)
0a2aaacc 9626 templ = XSTR (body, 0);
9342c0c4 9627 else if (asm_noperands (body) >= 0)
0a2aaacc 9628 templ
343d66ad 9629 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
9342c0c4
R		 9630 else
9631 return 0;
9632 do
9633 {
9634 int ppi_adjust = 0;
9635
9636 do
0a2aaacc 9637 c = *templ++;
9342c0c4
R		 9638 while (c == ' ' || c == '\t');
9639 /* all sh-dsp parallel-processing insns start with p.
9640 The only non-ppi sh insn starting with p is pref.
9641 The only ppi starting with pr is prnd. */
0a2aaacc 9642 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
9342c0c4
R		 9643 ppi_adjust = 2;
9644 /* The repeat pseudo-insn expands two three insns, a total of
9645 six bytes in size. */
9646 else if ((c == 'r' || c == 'R')
0a2aaacc 9647 && ! strncasecmp ("epeat", templ, 5))
9342c0c4 9648 ppi_adjust = 4;
980d8882 9649 while (c && c != '\n'
0a2aaacc 9650 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
9342c0c4
R		 9651 {
9652 /* If this is a label, it is obviously not a ppi insn. */
9653 if (c == ':' && maybe_label)
9654 {
9655 ppi_adjust = 0;
9656 break;
9657 }
9658 else if (c == '\'' || c == '"')
9659 maybe_label = 0;
0a2aaacc 9660 c = *templ++;
9342c0c4
R		 9661 }
9662 sum += ppi_adjust;
9663 maybe_label = c != ':';
9664 }
9665 while (c);
9666 return sum;
9667 }
9668 return 0;
9669}
1a66cd67 9670\f
cdeed45a
KK		 9671/* Return TRUE for a valid displacement for the REG+disp addressing
9672 with MODE. */
9673
9674/* ??? The SH2e does not have the REG+disp addressing mode when loading values
9675 into the FRx registers. We implement this by setting the maximum offset
9676 to zero when the value is SFmode. This also restricts loading of SFmode
9677 values into the integer registers, but that can't be helped. */
9678
9679/* The SH allows a displacement in a QI or HI amode, but only when the
9680 other operand is R0. GCC doesn't handle this very well, so we forgot
9681 all of that.
9682
9683 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
9684 DI can be any number 0..60. */
9685
9686bool
9687sh_legitimate_index_p (enum machine_mode mode, rtx op)
9688{
f3536097 9689 if (CONST_INT_P (op))
cdeed45a
KK		 9690 {
9691 if (TARGET_SHMEDIA)
9692 {
9693 int size;
9694
9695 /* Check if this the address of an unaligned load / store. */
9696 if (mode == VOIDmode)
9697 return CONST_OK_FOR_I06 (INTVAL (op));
9698
9699 size = GET_MODE_SIZE (mode);
9700 return (!(INTVAL (op) & (size - 1))
9701 && INTVAL (op) >= -512 * size
9702 && INTVAL (op) < 512 * size);
9703 }
9704
9705 if (TARGET_SH2A)
9706 {
9707 if (GET_MODE_SIZE (mode) == 1
9708 && (unsigned) INTVAL (op) < 4096)
9709 return true;
9710 }
9711
9712 if ((GET_MODE_SIZE (mode) == 4
9713 && (unsigned) INTVAL (op) < 64
9714 && !(INTVAL (op) & 3)
9715 && !(TARGET_SH2E && mode == SFmode))
9716 || (GET_MODE_SIZE (mode) == 4
9717 && (unsigned) INTVAL (op) < 16383
9718 && !(INTVAL (op) & 3) && TARGET_SH2A))
9719 return true;
9720
9721 if ((GET_MODE_SIZE (mode) == 8
9722 && (unsigned) INTVAL (op) < 60
9723 && !(INTVAL (op) & 3)
9724 && !((TARGET_SH4 || TARGET_SH2A) && mode == DFmode))
9725 || ((GET_MODE_SIZE (mode)==8)
9726 && (unsigned) INTVAL (op) < 8192
9727 && !(INTVAL (op) & (TARGET_SH2A_DOUBLE ? 7 : 3))
9728 && (TARGET_SH2A && mode == DFmode)))
9729 return true;
9730 }
9731
9732 return false;
9733}
9734
9735/* Recognize an RTL expression that is a valid memory address for
9736 an instruction.
9737 The MODE argument is the machine mode for the MEM expression
9738 that wants to use this address.
9739 Allow REG
9740 REG+disp
9741 REG+r0
9742 REG++
9743 --REG */
9744
1bb99877 9745static bool
cdeed45a
KK		 9746sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9747{
9748 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9749 return true;
9750 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9751 && ! TARGET_SHMEDIA
9752 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9753 return true;
9754 else if (GET_CODE (x) == PLUS
9755 && (mode != PSImode || reload_completed))
9756 {
9757 rtx xop0 = XEXP (x, 0);
9758 rtx xop1 = XEXP (x, 1);
9759
9760 if (GET_MODE_SIZE (mode) <= 8
9761 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9762 && sh_legitimate_index_p (mode, xop1))
9763 return true;
9764
9765 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode
9766 || ((xop0 == stack_pointer_rtx
9767 || xop0 == hard_frame_pointer_rtx)
9768 && REG_P (xop1) && REGNO (xop1) == R0_REG)
9769 || ((xop1 == stack_pointer_rtx
9770 || xop1 == hard_frame_pointer_rtx)
9771 && REG_P (xop0) && REGNO (xop0) == R0_REG))
9772 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4)
9773 || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8)
9774 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
9775 && TARGET_FMOVD && mode == DFmode)))
9776 {
9777 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9778 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9779 return true;
9780 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9781 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9782 return true;
9783 }
9784 }
9785
9786 return false;
9787}
9788\f
55eec660
AO		 9789/* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9790 isn't protected by a PIC unspec. */
1a66cd67 9791int
cf277499 9792nonpic_symbol_mentioned_p (rtx x)
1a66cd67
AO		 9793{
9794 register const char *fmt;
9795 register int i;
9796
fa5322fa
AO		 9797 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9798 || GET_CODE (x) == PC)
1a66cd67
AO		 9799 return 1;
9800
fa5322fa
AO		 9801 /* We don't want to look into the possible MEM location of a
9802 CONST_DOUBLE, since we're not going to use it, in general. */
9803 if (GET_CODE (x) == CONST_DOUBLE)
9804 return 0;
9805
1a66cd67 9806 if (GET_CODE (x) == UNSPEC
4773afa4
AO		 9807 && (XINT (x, 1) == UNSPEC_PIC
9808 || XINT (x, 1) == UNSPEC_GOT
9809 || XINT (x, 1) == UNSPEC_GOTOFF
fa5322fa 9810 || XINT (x, 1) == UNSPEC_GOTPLT
463f02cd
KK		 9811 || XINT (x, 1) == UNSPEC_GOTTPOFF
9812 || XINT (x, 1) == UNSPEC_DTPOFF
58f451f0 9813 || XINT (x, 1) == UNSPEC_TPOFF
dc3ba671
RS		 9814 || XINT (x, 1) == UNSPEC_PLT
9815 || XINT (x, 1) == UNSPEC_SYMOFF
9816 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
832a3292 9817 return 0;
1a66cd67
AO		 9818
9819 fmt = GET_RTX_FORMAT (GET_CODE (x));
9820 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9821 {
9822 if (fmt[i] == 'E')
9823 {
9824 register int j;
9825
9826 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9827 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9828 return 1;
9829 }
9830 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9831 return 1;
9832 }
9833
9834 return 0;
9835}
9836
9837/* Convert a non-PIC address in `orig' to a PIC address using @GOT or
6f317ef3 9838 @GOTOFF in `reg'. */
1a66cd67 9839rtx
cf277499
SB		 9840legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
9841 rtx reg)
1a66cd67 9842{
81f40b79 9843 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
463f02cd
KK		 9844 return orig;
9845
1a66cd67 9846 if (GET_CODE (orig) == LABEL_REF
675ff4c7 9847 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
1a66cd67
AO		 9848 {
9849 if (reg == 0)
9850 reg = gen_reg_rtx (Pmode);
9851
9852 emit_insn (gen_symGOTOFF2reg (reg, orig));
9853 return reg;
9854 }
9855 else if (GET_CODE (orig) == SYMBOL_REF)
9856 {
9857 if (reg == 0)
9858 reg = gen_reg_rtx (Pmode);
9859
9860 emit_insn (gen_symGOT2reg (reg, orig));
9861 return reg;
9862 }
9863 return orig;
9864}
b91455de 9865
506d7b68
PB		 9866/* Try machine-dependent ways of modifying an illegitimate address
9867 to be legitimate. If we find one, return the new, valid address.
9868 Otherwise, return X.
9869
9870 For the SH, if X is almost suitable for indexing, but the offset is
9871 out of range, convert it into a normal form so that CSE has a chance
9872 of reducing the number of address registers used. */
9873
9874static rtx
9875sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
9876{
9877 if (flag_pic)
9878 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9879
9880 if (GET_CODE (x) == PLUS
9881 && (GET_MODE_SIZE (mode) == 4
9882 || GET_MODE_SIZE (mode) == 8)
f3536097 9883 && CONST_INT_P (XEXP (x, 1))
506d7b68
PB		 9884 && BASE_REGISTER_RTX_P (XEXP (x, 0))
9885 && ! TARGET_SHMEDIA
9886 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
9887 && ! (TARGET_SH2E && mode == SFmode))
9888 {
9889 rtx index_rtx = XEXP (x, 1);
9890 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9891 rtx sum;
9892
9893 /* On rare occasions, we might get an unaligned pointer
9894 that is indexed in a way to give an aligned address.
9895 Therefore, keep the lower two bits in offset_base. */
9896 /* Instead of offset_base 128..131 use 124..127, so that
9897 simple add suffices. */
9898 if (offset > 127)
9899 offset_base = ((offset + 4) & ~60) - 4;
9900 else
9901 offset_base = offset & ~60;
9902
9903 /* Sometimes the normal form does not suit DImode. We
9904 could avoid that by using smaller ranges, but that
9905 would give less optimized code when SImode is
9906 prevalent. */
9907 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9908 {
9909 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9910 GEN_INT (offset_base), NULL_RTX, 0,
9911 OPTAB_LIB_WIDEN);
9912
9913 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9914 }
9915 }
9916
9917 return x;
9918}
9919
6f50eb9c
KK		 9920/* Attempt to replace *P, which is an address that needs reloading, with
9921 a valid memory address for an operand of mode MODE.
9922 Like for sh_legitimize_address, for the SH we try to get a normal form
9923 of the address. That will allow inheritance of the address reloads. */
9924
9925bool
9926sh_legitimize_reload_address (rtx *p, enum machine_mode mode, int opnum,
9927 int itype)
9928{
9929 enum reload_type type = (enum reload_type) itype;
9930
9931 if (GET_CODE (*p) == PLUS
9932 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
9933 && CONST_INT_P (XEXP (*p, 1))
7140f0f9 9934 && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p, 0), true)
6f50eb9c
KK		 9935 && ! TARGET_SHMEDIA
9936 && ! (TARGET_SH4 && mode == DFmode)
9937 && ! (mode == PSImode && type == RELOAD_FOR_INPUT_ADDRESS)
9938 && (ALLOW_INDEXED_ADDRESS
9939 || XEXP (*p, 0) == stack_pointer_rtx
9940 || XEXP (*p, 0) == hard_frame_pointer_rtx))
9941 {
9942 rtx index_rtx = XEXP (*p, 1);
9943 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9944 rtx sum;
9945
9946 if (TARGET_SH2A && mode == DFmode && (offset & 0x7))
9947 {
9948 push_reload (*p, NULL_RTX, p, NULL,
9949 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9950 goto win;
9951 }
9952 if (TARGET_SH2E && mode == SFmode)
9953 {
9954 *p = copy_rtx (*p);
9955 push_reload (*p, NULL_RTX, p, NULL,
9956 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9957 goto win;
9958 }
9959 /* Instead of offset_base 128..131 use 124..127, so that
9960 simple add suffices. */
9961 if (offset > 127)
9962 offset_base = ((offset + 4) & ~60) - 4;
9963 else
9964 offset_base = offset & ~60;
9965 /* Sometimes the normal form does not suit DImode. We could avoid
9966 that by using smaller ranges, but that would give less optimized
9967 code when SImode is prevalent. */
7140f0f9 9968 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
6f50eb9c
KK		 9969 {
9970 sum = gen_rtx_PLUS (Pmode, XEXP (*p, 0), GEN_INT (offset_base));
9971 *p = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9972 push_reload (sum, NULL_RTX, &XEXP (*p, 0), NULL,
9973 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9974 goto win;
9975 }
9976 }
9977 /* We must re-recognize what we created before. */
9978 else if (GET_CODE (*p) == PLUS
9979 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
9980 && GET_CODE (XEXP (*p, 0)) == PLUS
9981 && CONST_INT_P (XEXP (XEXP (*p, 0), 1))
7140f0f9 9982 && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p, 0), 0), true)
6f50eb9c
KK		 9983 && CONST_INT_P (XEXP (*p, 1))
9984 && ! TARGET_SHMEDIA
9985 && ! (TARGET_SH2E && mode == SFmode))
9986 {
9987 /* Because this address is so complex, we know it must have
9988 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
9989 it is already unshared, and needs no further unsharing. */
9990 push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
9991 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9992 goto win;
9993 }
9994
9995 return false;
9996
9997 win:
9998 return true;
9999}
10000
90833f7f
KK		 10001/* In the name of slightly smaller debug output, and to cater to
10002 general assembler lossage, recognize various UNSPEC sequences
10003 and turn them back into a direct symbol reference. */
10004
10005static rtx
10006sh_delegitimize_address (rtx orig_x)
10007{
10008 rtx x, y;
10009
10010 orig_x = delegitimize_mem_from_attrs (orig_x);
10011
10012 x = orig_x;
10013 if (MEM_P (x))
10014 x = XEXP (x, 0);
10015 if (GET_CODE (x) == CONST)
10016 {
10017 y = XEXP (x, 0);
10018 if (GET_CODE (y) == UNSPEC)
10019 {
10020 if (XINT (y, 1) == UNSPEC_GOT
2efd0aa6
KK		 10021 || XINT (y, 1) == UNSPEC_GOTOFF
10022 || XINT (y, 1) == UNSPEC_SYMOFF)
90833f7f 10023 return XVECEXP (y, 0, 0);
2efd0aa6
KK		 10024 else if (XINT (y, 1) == UNSPEC_PCREL_SYMOFF)
10025 {
10026 if (GET_CODE (XVECEXP (y, 0, 0)) == CONST)
10027 {
10028 rtx symplt = XEXP (XVECEXP (y, 0, 0), 0);
10029
10030 if (GET_CODE (symplt) == UNSPEC
10031 && XINT (symplt, 1) == UNSPEC_PLT)
10032 return XVECEXP (symplt, 0, 0);
10033 }
10034 }
90833f7f
KK		 10035 else if (TARGET_SHMEDIA
10036 && (XINT (y, 1) == UNSPEC_EXTRACT_S16
10037 || XINT (y, 1) == UNSPEC_EXTRACT_U16))
10038 {
10039 rtx offset = XVECEXP (y, 0, 1);
10040
10041 x = gen_rtx_PLUS (Pmode, XVECEXP (y, 0, 0), offset);
10042 if (MEM_P (orig_x))
10043 x = replace_equiv_address_nv (orig_x, x);
10044 return x;
10045 }
10046 }
10047 }
10048
10049 return orig_x;
10050}
10051
b91455de
KK		 10052/* Mark the use of a constant in the literal table. If the constant
10053 has multiple labels, make it unique. */
c1b92d09 10054static rtx
cf277499 10055mark_constant_pool_use (rtx x)
b91455de
KK		 10056{
10057 rtx insn, lab, pattern;
10058
10059 if (x == NULL)
10060 return x;
10061
10062 switch (GET_CODE (x))
10063 {
10064 case LABEL_REF:
10065 x = XEXP (x, 0);
10066 case CODE_LABEL:
10067 break;
10068 default:
10069 return x;
10070 }
10071
10072 /* Get the first label in the list of labels for the same constant
10073 and delete another labels in the list. */
10074 lab = x;
10075 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
10076 {
f3536097 10077 if (!LABEL_P (insn)
b91455de
KK		 10078 || LABEL_REFS (insn) != NEXT_INSN (insn))
10079 break;
10080 lab = insn;
10081 }
10082
10083 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
10084 INSN_DELETED_P (insn) = 1;
10085
10086 /* Mark constants in a window. */
10087 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
10088 {
f3536097 10089 if (!NONJUMP_INSN_P (insn))
b91455de
KK		 10090 continue;
10091
10092 pattern = PATTERN (insn);
10093 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
10094 continue;
10095
10096 switch (XINT (pattern, 1))
10097 {
10098 case UNSPECV_CONST2:
10099 case UNSPECV_CONST4:
10100 case UNSPECV_CONST8:
10101 XVECEXP (pattern, 0, 1) = const1_rtx;
10102 break;
10103 case UNSPECV_WINDOW_END:
10104 if (XVECEXP (pattern, 0, 0) == x)
10105 return lab;
10106 break;
10107 case UNSPECV_CONST_END:
10108 return lab;
10109 default:
10110 break;
10111 }
10112 }
10113
10114 return lab;
10115}
6e7b03e1
AH		 10116\f
10117/* Return true if it's possible to redirect BRANCH1 to the destination
10118 of an unconditional jump BRANCH2. We only want to do this if the
10119 resulting branch will have a short displacement. */
f676971a 10120int
cf277499 10121sh_can_redirect_branch (rtx branch1, rtx branch2)
6e7b03e1
AH		 10122{
10123 if (flag_expensive_optimizations && simplejump_p (branch2))
10124 {
10125 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
10126 rtx insn;
10127 int distance;
f676971a
EC		 10128
10129 for (distance = 0, insn = NEXT_INSN (branch1);
10130 insn && distance < 256;
6e7b03e1
AH		 10131 insn = PREV_INSN (insn))
10132 {
f676971a 10133 if (insn == dest)
6e7b03e1
AH		 10134 return 1;
10135 else
10136 distance += get_attr_length (insn);
10137 }
f676971a
EC		 10138 for (distance = 0, insn = NEXT_INSN (branch1);
10139 insn && distance < 256;
6e7b03e1
AH		 10140 insn = NEXT_INSN (insn))
10141 {
f676971a 10142 if (insn == dest)
6e7b03e1
AH		 10143 return 1;
10144 else
10145 distance += get_attr_length (insn);
10146 }
10147 }
10148 return 0;
10149}
10150
5e7a8ee0 10151/* Return nonzero if register old_reg can be renamed to register new_reg. */
03b8ec29 10152int
cf277499
SB		 10153sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
10154 unsigned int new_reg)
03b8ec29 10155{
832a3292
KH		 10156 /* Interrupt functions can only use registers that have already been
10157 saved by the prologue, even if they would normally be
10158 call-clobbered. */
03b8ec29 10159
6fb5fa3c 10160 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
832a3292 10161 return 0;
03b8ec29 10162
832a3292 10163 return 1;
03b8ec29
DD		 10164}
10165
95c0af87 10166/* Function to update the integer COST
c237e94a
ZW		 10167 based on the relationship between INSN that is dependent on
10168 DEP_INSN through the dependence LINK. The default is to make no
10169 adjustment to COST. This can be used for example to specify to
10170 the scheduler that an output- or anti-dependence does not incur
95c0af87
JR		 10171 the same cost as a data-dependence. The return value should be
10172 the new value for COST. */
c237e94a 10173static int
cf277499 10174sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
c237e94a 10175{
c49439f1 10176 rtx reg, use_pat;
c237e94a 10177
2ad65b0e
SC		 10178 if (TARGET_SHMEDIA)
10179 {
10180 /* On SHmedia, if the dependence is an anti-dependence or
24746a42 10181 output-dependence, there is no cost. */
2ad65b0e 10182 if (REG_NOTE_KIND (link) != 0)
73a4d10b
R		 10183 {
10184 /* However, dependencies between target register loads and
10185 uses of the register in a subsequent block that are separated
10186 by a conditional branch are not modelled - we have to do with
10187 the anti-dependency between the target register load and the
10188 conditional branch that ends the current block. */
10189 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
10190 && GET_CODE (PATTERN (dep_insn)) == SET
10191 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
10192 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
10193 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
10194 {
10195 int orig_cost = cost;
10196 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
10197 rtx target = ((! note
10198 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
10199 ? insn : JUMP_LABEL (insn));
10200 /* On the likely path, the branch costs 1, on the unlikely path,
10201 it costs 3. */
10202 cost--;
10203 do
10204 target = next_active_insn (target);
10205 while (target && ! flow_dependent_p (target, dep_insn)
10206 && --cost > 0);
10207 /* If two branches are executed in immediate succession, with the
10208 first branch properly predicted, this causes a stall at the
10209 second branch, hence we won't need the target for the
10210 second branch for two cycles after the launch of the first
10211 branch. */
10212 if (cost > orig_cost - 2)
10213 cost = orig_cost - 2;
10214 }
10215 else
10216 cost = 0;
10217 }
2ad65b0e 10218
73a4d10b
R		 10219 else if (get_attr_is_mac_media (insn)
10220 && get_attr_is_mac_media (dep_insn))
10221 cost = 1;
10222
10223 else if (! reload_completed
10224 && GET_CODE (PATTERN (insn)) == SET
10225 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
10226 && GET_CODE (PATTERN (dep_insn)) == SET
10227 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
10228 && cost < 4)
10229 cost = 4;
10230 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
10231 that is needed at the target. */
10232 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
10233 && ! flow_dependent_p (insn, dep_insn))
10234 cost--;
2ad65b0e 10235 }
c49439f1 10236 else if (REG_NOTE_KIND (link) == 0)
c237e94a 10237 {
78d310c2
R		 10238 enum attr_type type;
10239 rtx dep_set;
c49439f1
R		 10240
10241 if (recog_memoized (insn) < 0
10242 || recog_memoized (dep_insn) < 0)
95c0af87 10243 return cost;
c49439f1 10244
78d310c2 10245 dep_set = single_set (dep_insn);
c49439f1 10246
78d310c2
R		 10247 /* The latency that we specify in the scheduling description refers
10248 to the actual output, not to an auto-increment register; for that,
10249 the latency is one. */
10250 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
10251 {
10252 rtx set = single_set (insn);
10253
10254 if (set
10255 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
10256 && (!MEM_P (SET_DEST (set))
10257 || !reg_mentioned_p (SET_DEST (dep_set),
10258 XEXP (SET_DEST (set), 0))))
10259 cost = 1;
10260 }
c237e94a
ZW		 10261 /* The only input for a call that is timing-critical is the
10262 function's address. */
f3536097 10263 if (CALL_P (insn))
c49439f1
R		 10264 {
10265 rtx call = PATTERN (insn);
10266
10267 if (GET_CODE (call) == PARALLEL)
10268 call = XVECEXP (call, 0 ,0);
10269 if (GET_CODE (call) == SET)
10270 call = SET_SRC (call);
f3536097 10271 if (GET_CODE (call) == CALL && MEM_P (XEXP (call, 0))
73a4d10b
R		 10272 /* sibcalli_thunk uses a symbol_ref in an unspec. */
10273 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
10274 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
78d310c2 10275 cost -= TARGET_SH4_300 ? 3 : 6;
c49439f1 10276 }
c237e94a
ZW		 10277 /* Likewise, the most timing critical input for an sfuncs call
10278 is the function address. However, sfuncs typically start
10279 using their arguments pretty quickly.
78d310c2
R		 10280 Assume a four cycle delay for SH4 before they are needed.
10281 Cached ST40-300 calls are quicker, so assume only a one
10282 cycle delay there.
10283 ??? Maybe we should encode the delays till input registers
10284 are needed by sfuncs into the sfunc call insn. */
c49439f1
R		 10285 /* All sfunc calls are parallels with at least four components.
10286 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
10287 else if (GET_CODE (PATTERN (insn)) == PARALLEL
10288 && XVECLEN (PATTERN (insn), 0) >= 4
10289 && (reg = sfunc_uses_reg (insn)))
10290 {
10291 if (! reg_set_p (reg, dep_insn))
78d310c2
R		 10292 cost -= TARGET_SH4_300 ? 1 : 4;
10293 }
10294 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
10295 {
10296 enum attr_type dep_type = get_attr_type (dep_insn);
10297
10298 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
10299 cost--;
10300 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
10301 && (type = get_attr_type (insn)) != TYPE_CALL
10302 && type != TYPE_SFUNC)
10303 cost--;
10304 /* When the preceding instruction loads the shift amount of
10305 the following SHAD/SHLD, the latency of the load is increased
10306 by 1 cycle. */
10307 if (get_attr_type (insn) == TYPE_DYN_SHIFT
10308 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
c6ac6e82 10309 && reg_overlap_mentioned_p (SET_DEST (dep_set),
78d310c2
R		 10310 XEXP (SET_SRC (single_set (insn)),
10311 1)))
10312 cost++;
10313 /* When an LS group instruction with a latency of less than
10314 3 cycles is followed by a double-precision floating-point
10315 instruction, FIPR, or FTRV, the latency of the first
10316 instruction is increased to 3 cycles. */
10317 else if (cost < 3
10318 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
10319 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
10320 cost = 3;
10321 /* The lsw register of a double-precision computation is ready one
10322 cycle earlier. */
10323 else if (reload_completed
10324 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
10325 && (use_pat = single_set (insn))
10326 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
10327 SET_SRC (use_pat)))
10328 cost -= 1;
10329
10330 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
10331 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
10332 cost -= 1;
10333 }
10334 else if (TARGET_SH4_300)
10335 {
10336 /* Stores need their input register two cycles later. */
10337 if (dep_set && cost >= 1
10338 && ((type = get_attr_type (insn)) == TYPE_STORE
10339 || type == TYPE_PSTORE
10340 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
10341 {
10342 rtx set = single_set (insn);
10343
10344 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
10345 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
10346 {
10347 cost -= 2;
10348 /* But don't reduce the cost below 1 if the address depends
10349 on a side effect of dep_insn. */
10350 if (cost < 1
10351 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
10352 cost = 1;
10353 }
10354 }
10355 }
c49439f1
R		 10356 }
10357 /* An anti-dependence penalty of two applies if the first insn is a double
10358 precision fadd / fsub / fmul. */
78d310c2
R		 10359 else if (!TARGET_SH4_300
10360 && REG_NOTE_KIND (link) == REG_DEP_ANTI
c49439f1 10361 && recog_memoized (dep_insn) >= 0
78d310c2
R		 10362 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
10363 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
c49439f1
R		 10364 /* A lot of alleged anti-flow dependences are fake,
10365 so check this one is real. */
10366 && flow_dependent_p (dep_insn, insn))
c237e94a 10367 cost = 2;
c49439f1 10368
c237e94a
ZW		 10369 return cost;
10370}
3007d592 10371
c49439f1
R		 10372/* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
10373 if DEP_INSN is anti-flow dependent on INSN. */
10374static int
cf277499 10375flow_dependent_p (rtx insn, rtx dep_insn)
c49439f1
R		 10376{
10377 rtx tmp = PATTERN (insn);
10378
10379 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
10380 return tmp == NULL_RTX;
10381}
10382
10383/* A helper function for flow_dependent_p called through note_stores. */
10384static void
7bc980e1 10385flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
c49439f1
R		 10386{
10387 rtx * pinsn = (rtx *) data;
10388
10389 if (*pinsn && reg_referenced_p (x, *pinsn))
10390 *pinsn = NULL_RTX;
10391}
10392
b48f503c 10393/* For use by sh_allocate_initial_value. Note that sh.md contains some
3007d592
R		 10394 'special function' patterns (type sfunc) that clobber pr, but that
10395 do not look like function calls to leaf_function_p. Hence we must
10396 do this extra check. */
b48f503c 10397static int
cf277499 10398sh_pr_n_sets (void)
3007d592 10399{
6fb5fa3c 10400 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
3007d592 10401}
fa5322fa 10402
b48f503c
KK		 10403/* Return where to allocate pseudo for a given hard register initial
10404 value. */
10405static rtx
10406sh_allocate_initial_value (rtx hard_reg)
10407{
10408 rtx x;
10409
10410 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
10411 {
10412 if (current_function_is_leaf
10413 && ! sh_pr_n_sets ()
10414 && ! (TARGET_SHCOMPACT
38173d38 10415 && ((crtl->args.info.call_cookie
b48f503c 10416 & ~ CALL_COOKIE_RET_TRAMP (1))
e3b5732b 10417 || crtl->saves_all_registers)))
b48f503c
KK		 10418 x = hard_reg;
10419 else
57d38024 10420 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
b48f503c
KK		 10421 }
10422 else
10423 x = NULL_RTX;
10424
10425 return x;
10426}
10427
c49439f1
R		 10428/* This function returns "2" to indicate dual issue for the SH4
10429 processor. To be used by the DFA pipeline description. */
fae15c93 10430static int
832a3292 10431sh_issue_rate (void)
fae15c93 10432{
c49439f1
R		 10433 if (TARGET_SUPERSCALAR)
10434 return 2;
10435 else
10436 return 1;
fae15c93
VM		 10437}
10438
58565a33
SKG		 10439/* Functions for ready queue reordering for sched1. */
10440
10441/* Get weight for mode for a set x. */
10442static short
508ea1c5 10443find_set_regmode_weight (rtx x, enum machine_mode mode)
58565a33
SKG		 10444{
10445 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
10446 return 1;
10447 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
10448 {
f3536097 10449 if (REG_P (SET_DEST (x)))
58565a33
SKG		 10450 {
10451 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
10452 return 1;
10453 else
10454 return 0;
10455 }
10456 return 1;
10457 }
10458 return 0;
10459}
10460
10461/* Get regmode weight for insn. */
10462static short
508ea1c5 10463find_insn_regmode_weight (rtx insn, enum machine_mode mode)
58565a33
SKG		 10464{
10465 short reg_weight = 0;
10466 rtx x;
10467
10468 /* Increment weight for each register born here. */
10469 x = PATTERN (insn);
10470 reg_weight += find_set_regmode_weight (x, mode);
10471 if (GET_CODE (x) == PARALLEL)
10472 {
10473 int j;
10474 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
10475 {
10476 x = XVECEXP (PATTERN (insn), 0, j);
10477 reg_weight += find_set_regmode_weight (x, mode);
10478 }
10479 }
10480 /* Decrement weight for each register that dies here. */
10481 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
10482 {
10483 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
10484 {
10485 rtx note = XEXP (x, 0);
f3536097 10486 if (REG_P (note) && GET_MODE (note) == mode)
58565a33
SKG		 10487 reg_weight--;
10488 }
10489 }
10490 return reg_weight;
10491}
10492
10493/* Calculate regmode weights for all insns of a basic block. */
10494static void
c6d56443 10495find_regmode_weight (basic_block b, enum machine_mode mode)
58565a33
SKG		 10496{
10497 rtx insn, next_tail, head, tail;
10498
c6d56443 10499 get_ebb_head_tail (b, b, &head, &tail);
58565a33
SKG		 10500 next_tail = NEXT_INSN (tail);
10501
10502 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
10503 {
10504 /* Handle register life information. */
10505 if (!INSN_P (insn))
10506 continue;
10507
10508 if (mode == SFmode)
10509 INSN_REGMODE_WEIGHT (insn, mode) =
10510 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
10511 else if (mode == SImode)
10512 INSN_REGMODE_WEIGHT (insn, mode) =
10513 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
10514 }
10515}
10516
10517/* Comparison function for ready queue sorting. */
10518static int
508ea1c5 10519rank_for_reorder (const void *x, const void *y)
58565a33
SKG		 10520{
10521 rtx tmp = *(const rtx *) y;
10522 rtx tmp2 = *(const rtx *) x;
10523
10524 /* The insn in a schedule group should be issued the first. */
10525 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
10526 return SCHED_GROUP_P (tmp2) ? 1 : -1;
10527
f676971a 10528 /* If insns are equally good, sort by INSN_LUID (original insn order), This
58565a33
SKG		 10529 minimizes instruction movement, thus minimizing sched's effect on
10530 register pressure. */
10531 return INSN_LUID (tmp) - INSN_LUID (tmp2);
10532}
10533
10534/* Resort the array A in which only element at index N may be out of order. */
10535static void
508ea1c5 10536swap_reorder (rtx *a, int n)
58565a33
SKG		 10537{
10538 rtx insn = a[n - 1];
10539 int i = n - 2;
10540
10541 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
10542 {
10543 a[i + 1] = a[i];
10544 i -= 1;
10545 }
10546 a[i + 1] = insn;
10547}
10548
832a3292
KH		 10549#define SCHED_REORDER(READY, N_READY) \
10550 do \
10551 { \
10552 if ((N_READY) == 2) \
10553 swap_reorder (READY, N_READY); \
10554 else if ((N_READY) > 2) \
10555 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
10556 } \
10557 while (0)
58565a33
SKG		 10558
10559/* Sort the ready list READY by ascending priority, using the SCHED_REORDER
10560 macro. */
10561static void
508ea1c5 10562ready_reorder (rtx *ready, int nready)
58565a33
SKG		 10563{
10564 SCHED_REORDER (ready, nready);
10565}
10566
6fb5fa3c
DB		 10567/* Count life regions of r0 for a block. */
10568static int
10569find_r0_life_regions (basic_block b)
10570{
10571 rtx end, insn;
10572 rtx pset;
10573 rtx r0_reg;
10574 int live;
10575 int set;
10576 int death = 0;
10577
89a95777 10578 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
6fb5fa3c
DB		 10579 {
10580 set = 1;
10581 live = 1;
10582 }
10583 else
10584 {
10585 set = 0;
10586 live = 0;
10587 }
10588
10589 insn = BB_HEAD (b);
10590 end = BB_END (b);
10591 r0_reg = gen_rtx_REG (SImode, R0_REG);
10592 while (1)
10593 {
10594 if (INSN_P (insn))
10595 {
10596 if (find_regno_note (insn, REG_DEAD, R0_REG))
10597 {
10598 death++;
10599 live = 0;
10600 }
10601 if (!live
10602 && (pset = single_set (insn))
10603 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
10604 && !find_regno_note (insn, REG_UNUSED, R0_REG))
10605 {
10606 set++;
10607 live = 1;
10608 }
10609 }
10610 if (insn == end)
10611 break;
10612 insn = NEXT_INSN (insn);
10613 }
10614 return set - death;
10615}
10616
58565a33
SKG		 10617/* Calculate regmode weights for all insns of all basic block. */
10618static void
508ea1c5
KH		 10619sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
10620 int verbose ATTRIBUTE_UNUSED,
10621 int old_max_uid)
58565a33
SKG		 10622{
10623 basic_block b;
10624
10625 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
10626 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
6fb5fa3c 10627 r0_life_regions = 0;
58565a33
SKG		 10628
10629 FOR_EACH_BB_REVERSE (b)
10630 {
c6d56443
KK		 10631 find_regmode_weight (b, SImode);
10632 find_regmode_weight (b, SFmode);
6fb5fa3c
DB		 10633 if (!reload_completed)
10634 r0_life_regions += find_r0_life_regions (b);
58565a33
SKG		 10635 }
10636
10637 CURR_REGMODE_PRESSURE (SImode) = 0;
10638 CURR_REGMODE_PRESSURE (SFmode) = 0;
10639
10640}
10641
10642/* Cleanup. */
10643static void
508ea1c5
KH		 10644sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
10645 int verbose ATTRIBUTE_UNUSED)
58565a33
SKG		 10646{
10647 if (regmode_weight[0])
10648 {
10649 free (regmode_weight[0]);
10650 regmode_weight[0] = NULL;
10651 }
10652 if (regmode_weight[1])
10653 {
10654 free (regmode_weight[1]);
10655 regmode_weight[1] = NULL;
10656 }
10657}
10658
b0fbea13
KK		 10659/* The scalar modes supported differs from the default version in TImode
10660 for 32-bit SHMEDIA. */
10661static bool
10662sh_scalar_mode_supported_p (enum machine_mode mode)
10663{
10664 if (TARGET_SHMEDIA32 && mode == TImode)
10665 return false;
10666
10667 return default_scalar_mode_supported_p (mode);
10668}
10669
58565a33
SKG		 10670/* Cache the can_issue_more so that we can return it from reorder2. Also,
10671 keep count of register pressures on SImode and SFmode. */
10672static int
508ea1c5
KH		 10673sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
10674 int sched_verbose ATTRIBUTE_UNUSED,
10675 rtx insn,
10676 int can_issue_more)
58565a33
SKG		 10677{
10678 if (GET_CODE (PATTERN (insn)) != USE
10679 && GET_CODE (PATTERN (insn)) != CLOBBER)
10680 cached_can_issue_more = can_issue_more - 1;
10681 else
10682 cached_can_issue_more = can_issue_more;
10683
10684 if (reload_completed)
10685 return cached_can_issue_more;
10686
10687 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
10688 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
10689
10690 return cached_can_issue_more;
10691}
10692
10693static void
508ea1c5
KH		 10694sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
10695 int verbose ATTRIBUTE_UNUSED,
10696 int veclen ATTRIBUTE_UNUSED)
58565a33
SKG		 10697{
10698 CURR_REGMODE_PRESSURE (SImode) = 0;
10699 CURR_REGMODE_PRESSURE (SFmode) = 0;
10700}
10701
10702/* Some magic numbers. */
10703/* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10704 functions that already have high pressure on r0. */
10705#define R0_MAX_LIFE_REGIONS 2
4ee31f1e 10706/* Register Pressure thresholds for SImode and SFmode registers. */
58565a33
SKG		 10707#define SIMODE_MAX_WEIGHT 5
10708#define SFMODE_MAX_WEIGHT 10
10709
10710/* Return true if the pressure is high for MODE. */
10711static short
508ea1c5 10712high_pressure (enum machine_mode mode)
58565a33
SKG		 10713{
10714 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10715 functions that already have high pressure on r0. */
6fb5fa3c
DB		 10716 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
10717 return 1;
58565a33
SKG		 10718
10719 if (mode == SFmode)
10720 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
10721 else
10722 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
10723}
10724
10725/* Reorder ready queue if register pressure is high. */
10726static int
508ea1c5
KH		 10727sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
10728 int sched_verbose ATTRIBUTE_UNUSED,
10729 rtx *ready,
10730 int *n_readyp,
10731 int clock_var ATTRIBUTE_UNUSED)
58565a33
SKG		 10732{
10733 if (reload_completed)
10734 return sh_issue_rate ();
10735
10736 if (high_pressure (SFmode) || high_pressure (SImode))
10737 {
10738 ready_reorder (ready, *n_readyp);
10739 }
10740
10741 return sh_issue_rate ();
10742}
10743
10744/* Skip cycles if the current register pressure is high. */
f676971a 10745static int
508ea1c5
KH		 10746sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
10747 int sched_verbose ATTRIBUTE_UNUSED,
10748 rtx *ready ATTRIBUTE_UNUSED,
10749 int *n_readyp ATTRIBUTE_UNUSED,
10750 int clock_var ATTRIBUTE_UNUSED)
58565a33
SKG		 10751{
10752 if (reload_completed)
10753 return cached_can_issue_more;
10754
f676971a 10755 if (high_pressure(SFmode) || high_pressure (SImode))
58565a33
SKG		 10756 skip_cycles = 1;
10757
10758 return cached_can_issue_more;
10759}
10760
10761/* Skip cycles without sorting the ready queue. This will move insn from
10762 Q->R. If this is the last cycle we are skipping; allow sorting of ready
f676971a 10763 queue by sh_reorder. */
58565a33 10764
f676971a
EC		 10765/* Generally, skipping these many cycles are sufficient for all insns to move
10766 from Q -> R. */
10767#define MAX_SKIPS 8
58565a33
SKG		 10768
10769static int
508ea1c5
KH		 10770sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
10771 int sched_verbose ATTRIBUTE_UNUSED,
10772 rtx insn ATTRIBUTE_UNUSED,
10773 int last_clock_var,
10774 int clock_var,
10775 int *sort_p)
58565a33
SKG		 10776{
10777 if (reload_completed)
832a3292 10778 return 0;
58565a33 10779
f676971a 10780 if (skip_cycles)
58565a33 10781 {
832a3292
KH		 10782 if ((clock_var - last_clock_var) < MAX_SKIPS)
10783 {
10784 *sort_p = 0;
10785 return 1;
10786 }
10787 /* If this is the last cycle we are skipping, allow reordering of R. */
10788 if ((clock_var - last_clock_var) == MAX_SKIPS)
10789 {
10790 *sort_p = 1;
10791 return 1;
10792 }
58565a33 10793 }
58565a33
SKG		 10794
10795 skip_cycles = 0;
10796
10797 return 0;
10798}
10799
fa5322fa
AO		 10800/* SHmedia requires registers for branches, so we can't generate new
10801 branches past reload. */
10802static bool
cf277499 10803sh_cannot_modify_jumps_p (void)
fa5322fa
AO		 10804{
10805 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
10806}
10807
a87cf97e 10808static reg_class_t
fe3ad572
SC		 10809sh_target_reg_class (void)
10810{
10811 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
10812}
10813
10814static bool
10815sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
10816{
73a4d10b 10817 HARD_REG_SET dummy;
cb3d3842 10818#if 0
73a4d10b 10819 rtx insn;
cb3d3842 10820#endif
73a4d10b
R		 10821
10822 if (! shmedia_space_reserved_for_target_registers)
10823 return 0;
10824 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
10825 return 0;
10826 if (calc_live_regs (&dummy) >= 6 * 8)
10827 return 1;
73a4d10b 10828 return 0;
fe3ad572
SC		 10829}
10830
fa5322fa 10831static bool
3101faab 10832sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
fa5322fa 10833{
61f71b34 10834 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
fa5322fa 10835}
ca903bba 10836\f
f676971a 10837/*
ca903bba
R		 10838 On the SH1..SH4, the trampoline looks like
10839 2 0002 D202 mov.l l2,r2
10840 1 0000 D301 mov.l l1,r3
10841 3 0004 422B jmp @r2
10842 4 0006 0009 nop
10843 5 0008 00000000 l1: .long area
10844 6 000c 00000000 l2: .long function
10845
10846 SH5 (compact) uses r1 instead of r3 for the static chain. */
10847
10848
10849/* Emit RTL insns to initialize the variable parts of a trampoline.
10850 FNADDR is an RTX for the address of the function's pure code.
10851 CXT is an RTX for the static chain value for the function. */
10852
994322ef
RH		 10853static void
10854sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
ca903bba 10855{
994322ef
RH		 10856 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10857 rtx tramp = force_reg (Pmode, XEXP (tramp_mem, 0));
57d38024 10858
ca903bba
R		 10859 if (TARGET_SHMEDIA64)
10860 {
10861 rtx tramp_templ;
10862 int fixed_len;
10863
10864 rtx movi1 = GEN_INT (0xcc000010);
10865 rtx shori1 = GEN_INT (0xc8000010);
10866 rtx src, dst;
10867
10868 /* The following trampoline works within a +- 128 KB range for cxt:
10869 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10870 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10871 gettr tr1,r1; blink tr0,r63 */
10872 /* Address rounding makes it hard to compute the exact bounds of the
10873 offset for this trampoline, but we have a rather generous offset
10874 range, so frame_offset should do fine as an upper bound. */
10875 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
10876 {
10877 /* ??? could optimize this trampoline initialization
10878 by writing DImode words with two insns each. */
10879 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
10880 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
10881 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
10882 insn = gen_rtx_AND (DImode, insn, mask);
10883 /* Or in ptb/u .,tr1 pattern */
10884 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
10885 insn = force_operand (insn, NULL_RTX);
10886 insn = gen_lowpart (SImode, insn);
57d38024 10887 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
ca903bba
R		 10888 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
10889 insn = gen_rtx_AND (DImode, insn, mask);
10890 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
10891 insn = gen_lowpart (SImode, insn);
57d38024 10892 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
ca903bba
R		 10893 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
10894 insn = gen_rtx_AND (DImode, insn, mask);
10895 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10896 insn = gen_lowpart (SImode, insn);
57d38024 10897 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
ca903bba
R		 10898 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
10899 insn = gen_rtx_AND (DImode, insn, mask);
10900 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10901 insn = gen_lowpart (SImode, insn);
57d38024 10902 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
ca903bba
R		 10903 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
10904 insn = gen_rtx_AND (DImode, insn, mask);
10905 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10906 insn = gen_lowpart (SImode, insn);
57d38024
R		 10907 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
10908 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
ca903bba 10909 GEN_INT (0x6bf10600));
57d38024 10910 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
ca903bba 10911 GEN_INT (0x4415fc10));
57d38024 10912 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
ca903bba
R		 10913 GEN_INT (0x4401fff0));
10914 emit_insn (gen_ic_invalidate_line (tramp));
10915 return;
10916 }
10917 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
10918 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
10919
10920 tramp_templ = gen_datalabel_ref (tramp_templ);
57d38024
R		 10921 dst = tramp_mem;
10922 src = gen_const_mem (BLKmode, tramp_templ);
ca903bba
R		 10923 set_mem_align (dst, 256);
10924 set_mem_align (src, 64);
44bb111a 10925 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
ca903bba 10926
57d38024
R		 10927 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
10928 emit_move_insn (adjust_address (tramp_mem, Pmode,
10929 fixed_len + GET_MODE_SIZE (Pmode)),
ca903bba
R		 10930 cxt);
10931 emit_insn (gen_ic_invalidate_line (tramp));
10932 return;
10933 }
10934 else if (TARGET_SHMEDIA)
10935 {
10936 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10937 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10938 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
10939 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
10940 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
825db093 10941 rotated 10 right, and higher 16 bit of every 32 selected. */
ca903bba
R		 10942 rtx movishori
10943 = force_reg (V2HImode, (simplify_gen_subreg
10944 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
10945 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
10946 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
10947
ca903bba
R		 10948 fnaddr = force_reg (SImode, fnaddr);
10949 cxt = force_reg (SImode, cxt);
10950 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
10951 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
10952 movishori));
f1e2239f 10953 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
ca903bba 10954 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
a556fd39 10955 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
57d38024 10956 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
ca903bba
R		 10957 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
10958 gen_rtx_SUBREG (V2HImode, cxt, 0),
10959 movishori));
f1e2239f 10960 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
ca903bba 10961 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
a556fd39 10962 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
ca903bba
R		 10963 if (TARGET_LITTLE_ENDIAN)
10964 {
10965 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
10966 emit_insn (gen_mextr4 (quad2, cxtload, blink));
10967 }
10968 else
10969 {
10970 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
10971 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
10972 }
57d38024
R		 10973 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
10974 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
ca903bba
R		 10975 emit_insn (gen_ic_invalidate_line (tramp));
10976 return;
10977 }
10978 else if (TARGET_SHCOMPACT)
10979 {
10980 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
10981 return;
10982 }
57d38024 10983 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
ca903bba
R		 10984 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
10985 SImode));
57d38024 10986 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
ca903bba
R		 10987 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
10988 SImode));
57d38024
R		 10989 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
10990 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
ca903bba
R		 10991 if (TARGET_HARVARD)
10992 {
dc557046 10993 if (!TARGET_INLINE_IC_INVALIDATE
6f8eec29 10994 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
73a4d10b
R		 10995 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10996 FUNCTION_ORDINARY),
b757d36f 10997 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
ca903bba
R		 10998 else
10999 emit_insn (gen_ic_invalidate_line (tramp));
11000 }
11001}
11002
994322ef
RH		 11003/* On SH5, trampolines are SHmedia code, so add 1 to the address. */
11004
11005static rtx
11006sh_trampoline_adjust_address (rtx tramp)
11007{
11008 if (TARGET_SHMEDIA)
11009 tramp = expand_simple_binop (Pmode, PLUS, tramp, const1_rtx,
11010 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN);
11011 return tramp;
11012}
11013
4977bab6
ZW		 11014/* FIXME: This is overly conservative. A SHcompact function that
11015 receives arguments ``by reference'' will have them stored in its
11016 own stack frame, so it must not pass pointers or references to
11017 these arguments to other functions by means of sibling calls. */
73a4d10b
R		 11018/* If PIC, we cannot make sibling calls to global functions
11019 because the PLT requires r12 to be live. */
4977bab6 11020static bool
cf277499 11021sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
4977bab6 11022{
73a4d10b 11023 return (1
4977bab6 11024 && (! TARGET_SHCOMPACT
38173d38 11025 || crtl->args.info.stack_regs == 0)
73a4d10b
R		 11026 && ! sh_cfun_interrupt_handler_p ()
11027 && (! flag_pic
11028 || (decl && ! TREE_PUBLIC (decl))
11029 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
4977bab6 11030}
c1b92d09
R		 11031\f
11032/* Machine specific built-in functions. */
11033
11034struct builtin_description
11035{
11036 const enum insn_code icode;
11037 const char *const name;
11038 int signature;
1cc24576 11039 tree fndecl;
c1b92d09
R		 11040};
11041
11042/* describe number and signedness of arguments; arg[0] == result
11043 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
3b962ea0 11044/* 9: 64-bit pointer, 10: 32-bit pointer */
c1b92d09
R		 11045static const char signature_args[][4] =
11046{
11047#define SH_BLTIN_V2SI2 0
11048 { 4, 4 },
11049#define SH_BLTIN_V4HI2 1
11050 { 4, 4 },
11051#define SH_BLTIN_V2SI3 2
11052 { 4, 4, 4 },
11053#define SH_BLTIN_V4HI3 3
11054 { 4, 4, 4 },
11055#define SH_BLTIN_V8QI3 4
11056 { 4, 4, 4 },
11057#define SH_BLTIN_MAC_HISI 5
11058 { 1, 4, 4, 1 },
11059#define SH_BLTIN_SH_HI 6
11060 { 4, 4, 1 },
11061#define SH_BLTIN_SH_SI 7
11062 { 4, 4, 1 },
11063#define SH_BLTIN_V4HI2V2SI 8
11064 { 4, 4, 4 },
11065#define SH_BLTIN_V4HI2V8QI 9
11066 { 4, 4, 4 },
11067#define SH_BLTIN_SISF 10
11068 { 4, 2 },
11069#define SH_BLTIN_LDUA_L 11
73a4d10b 11070 { 2, 10 },
c1b92d09 11071#define SH_BLTIN_LDUA_Q 12
73a4d10b 11072 { 1, 10 },
c1b92d09 11073#define SH_BLTIN_STUA_L 13
73a4d10b 11074 { 0, 10, 2 },
c1b92d09 11075#define SH_BLTIN_STUA_Q 14
73a4d10b
R		 11076 { 0, 10, 1 },
11077#define SH_BLTIN_LDUA_L64 15
11078 { 2, 9 },
11079#define SH_BLTIN_LDUA_Q64 16
11080 { 1, 9 },
11081#define SH_BLTIN_STUA_L64 17
11082 { 0, 9, 2 },
11083#define SH_BLTIN_STUA_Q64 18
11084 { 0, 9, 1 },
11085#define SH_BLTIN_NUM_SHARED_SIGNATURES 19
11086#define SH_BLTIN_2 19
11087#define SH_BLTIN_SU 19
c1b92d09 11088 { 1, 2 },
73a4d10b
R		 11089#define SH_BLTIN_3 20
11090#define SH_BLTIN_SUS 20
c1b92d09 11091 { 2, 2, 1 },
73a4d10b 11092#define SH_BLTIN_PSSV 21
c1b92d09 11093 { 0, 8, 2, 2 },
73a4d10b
R		 11094#define SH_BLTIN_XXUU 22
11095#define SH_BLTIN_UUUU 22
c1b92d09 11096 { 1, 1, 1, 1 },
73a4d10b 11097#define SH_BLTIN_PV 23
c1b92d09
R		 11098 { 0, 8 },
11099};
24746a42 11100/* mcmv: operands considered unsigned. */
c1b92d09 11101/* mmulsum_wq, msad_ubq: result considered unsigned long long. */
24746a42
KH		 11102/* mperm: control value considered unsigned int. */
11103/* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
c1b92d09
R		 11104/* mshards_q: returns signed short. */
11105/* nsb: takes long long arg, returns unsigned char. */
1cc24576
KK		 11106static struct builtin_description bdesc[] =
11107{
11108 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2, 0 },
11109 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2, 0 },
11110 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3, 0 },
11111 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3, 0 },
11112 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3, 0 },
11113 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3, 0 },
11114 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3, 0 },
11115 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV, 0 },
11116 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3, 0 },
11117 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3, 0 },
11118 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3, 0 },
11119 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3, 0 },
11120 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3, 0 },
11121 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3, 0 },
11122 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU, 0 },
11123 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3, 0 },
11124 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI, 0 },
11125 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI, 0 },
11126 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3, 0 },
11127 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3, 0 },
11128 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3, 0 },
11129 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3, 0 },
11130 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3, 0 },
11131 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3, 0 },
11132 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3, 0 },
11133 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI, 0 },
11134 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI, 0 },
11135 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, 0 },
11136 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3, 0 },
11137 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3, 0 },
11138 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3, 0 },
11139 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3, 0 },
11140 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI, 0 },
11141 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI, 0 },
11142 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU, 0 },
11143 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI, 0 },
11144 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU, 0 },
11145 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI, 0 },
11146 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI, 0 },
11147 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI, 0 },
11148 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI, 0 },
11149 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS, 0 },
11150 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3, 0 },
11151 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3, 0 },
11152 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3, 0 },
11153 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3, 0 },
11154 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3, 0 },
11155 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3, 0 },
11156 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI, 0 },
11157 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI, 0 },
11158 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI, 0 },
11159 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI, 0 },
11160 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3, 0 },
11161 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3, 0 },
11162 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3, 0 },
11163 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3, 0 },
11164 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3, 0 },
11165 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF, 0 },
11166 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF, 0 },
11167 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3, 0 },
11168 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3, 0 },
11169 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3, 0 },
11170 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2, 0 },
11171 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2, 0 },
11172 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2, 0 },
11173 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L, 0 },
11174 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q, 0 },
11175 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L, 0 },
11176 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q, 0 },
11177 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L, 0 },
11178 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q, 0 },
11179 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L, 0 },
11180 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q, 0 },
11181 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64, 0 },
11182 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64, 0 },
11183 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64, 0 },
11184 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64, 0 },
11185 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64, 0 },
11186 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64, 0 },
11187 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64, 0 },
11188 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64, 0 },
11189 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU, 0 },
11190 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2, 0 },
11191 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV, 0 },
c1b92d09
R		 11192};
11193
11194static void
cf277499 11195sh_media_init_builtins (void)
c1b92d09
R		 11196{
11197 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
1cc24576 11198 struct builtin_description *d;
c1b92d09 11199
a3acdc0c 11200 memset (shared, 0, sizeof shared);
e97a46ce 11201 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
c1b92d09 11202 {
73a4d10b 11203 tree type, arg_type = 0;
c1b92d09
R		 11204 int signature = d->signature;
11205 int i;
11206
11207 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
11208 type = shared[signature];
11209 else
11210 {
11211 int has_result = signature_args[signature][0] != 0;
11212
73a4d10b
R		 11213 if ((signature_args[signature][1] & 8)
11214 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
11215 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
c1b92d09
R		 11216 continue;
11217 if (! TARGET_FPU_ANY
11218 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
11219 continue;
11220 type = void_list_node;
11221 for (i = 3; ; i--)
11222 {
11223 int arg = signature_args[signature][i];
11224 int opno = i - 1 + has_result;
11225
73a4d10b 11226 if (arg & 8)
c1b92d09
R		 11227 arg_type = ptr_type_node;
11228 else if (arg)
73a4d10b
R		 11229 arg_type = (*lang_hooks.types.type_for_mode)
11230 (insn_data[d->icode].operand[opno].mode,
11231 (arg & 1));
c1b92d09
R		 11232 else if (i)
11233 continue;
11234 else
11235 arg_type = void_type_node;
11236 if (i == 0)
11237 break;
11238 type = tree_cons (NULL_TREE, arg_type, type);
11239 }
11240 type = build_function_type (arg_type, type);
11241 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
11242 shared[signature] = type;
11243 }
1cc24576
KK		 11244 d->fndecl =
11245 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
11246 NULL, NULL_TREE);
c1b92d09
R		 11247 }
11248}
11249
1cc24576
KK		 11250/* Returns the shmedia builtin decl for CODE. */
11251
11252static tree
11253sh_media_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11254{
11255 if (code >= ARRAY_SIZE (bdesc))
11256 return error_mark_node;
11257
11258 return bdesc[code].fndecl;
11259}
11260
f676971a
EC		 11261/* Implements target hook vector_mode_supported_p. */
11262bool
11263sh_vector_mode_supported_p (enum machine_mode mode)
11264{
11265 if (TARGET_FPU_ANY
11266 && ((mode == V2SFmode)
11267 || (mode == V4SFmode)
11268 || (mode == V16SFmode)))
11269 return true;
11270
11271 else if (TARGET_SHMEDIA
11272 && ((mode == V8QImode)
11273 || (mode == V2HImode)
11274 || (mode == V4HImode)
11275 || (mode == V2SImode)))
11276 return true;
11277
11278 return false;
11279}
11280
7a296495
CB		 11281bool
11282sh_frame_pointer_required (void)
11283{
11284/* If needed override this in other tm.h files to cope with various OS
11285 lossage requiring a frame pointer. */
11286 if (SUBTARGET_FRAME_POINTER_REQUIRED)
11287 return true;
11288
11289 if (crtl->profile)
11290 return true;
11291
11292 return false;
11293}
11294
a1c496cb
EC		 11295/* Implements target hook dwarf_calling_convention. Return an enum
11296 of dwarf_calling_convention. */
11297int
3101faab 11298sh_dwarf_calling_convention (const_tree func)
a1c496cb
EC		 11299{
11300 if (sh_attr_renesas_p (func))
29832164 11301 return DW_CC_GNU_renesas_sh;
a1c496cb
EC		 11302
11303 return DW_CC_normal;
11304}
11305
c1b92d09 11306static void
cf277499 11307sh_init_builtins (void)
c1b92d09
R		 11308{
11309 if (TARGET_SHMEDIA)
11310 sh_media_init_builtins ();
11311}
11312
1cc24576
KK		 11313/* Returns the sh builtin decl for CODE. */
11314
11315static tree
11316sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11317{
11318 if (TARGET_SHMEDIA)
11319 return sh_media_builtin_decl (code, initialize_p);
11320
11321 return error_mark_node;
11322}
11323
c1b92d09
R		 11324/* Expand an expression EXP that calls a built-in function,
11325 with result going to TARGET if that's convenient
11326 (and in mode MODE if that's convenient).
11327 SUBTARGET may be used as the target for computing one of EXP's operands.
11328 IGNORE is nonzero if the value is to be ignored. */
11329
11330static rtx
cf277499
SB		 11331sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11332 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
c1b92d09 11333{
5039610b 11334 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
c1b92d09
R		 11335 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
11336 const struct builtin_description *d = &bdesc[fcode];
11337 enum insn_code icode = d->icode;
11338 int signature = d->signature;
11339 enum machine_mode tmode = VOIDmode;
11340 int nop = 0, i;
11341 rtx op[4];
73a4d10b 11342 rtx pat = 0;
c1b92d09
R		 11343
11344 if (signature_args[signature][0])
11345 {
11346 if (ignore)
11347 return 0;
11348
11349 tmode = insn_data[icode].operand[0].mode;
11350 if (! target
11351 || GET_MODE (target) != tmode
11352 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11353 target = gen_reg_rtx (tmode);
11354 op[nop++] = target;
11355 }
11356 else
11357 target = 0;
11358
11359 for (i = 1; i <= 3; i++, nop++)
11360 {
11361 tree arg;
11362 enum machine_mode opmode, argmode;
73a4d10b 11363 tree optype;
c1b92d09
R		 11364
11365 if (! signature_args[signature][i])
11366 break;
5039610b 11367 arg = CALL_EXPR_ARG (exp, i - 1);
3578cf63
R		 11368 if (arg == error_mark_node)
11369 return const0_rtx;
73a4d10b
R		 11370 if (signature_args[signature][i] & 8)
11371 {
11372 opmode = ptr_mode;
11373 optype = ptr_type_node;
11374 }
11375 else
11376 {
11377 opmode = insn_data[icode].operand[nop].mode;
11378 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
11379 }
c1b92d09
R		 11380 argmode = TYPE_MODE (TREE_TYPE (arg));
11381 if (argmode != opmode)
73a4d10b 11382 arg = build1 (NOP_EXPR, optype, arg);
b757d36f 11383 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
c1b92d09
R		 11384 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
11385 op[nop] = copy_to_mode_reg (opmode, op[nop]);
11386 }
11387
11388 switch (nop)
11389 {
11390 case 1:
11391 pat = (*insn_data[d->icode].genfun) (op[0]);
11392 break;
11393 case 2:
11394 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
11395 break;
11396 case 3:
11397 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
11398 break;
11399 case 4:
11400 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
11401 break;
95c0af87 11402 default:
f5b9e7c9 11403 gcc_unreachable ();
c1b92d09
R		 11404 }
11405 if (! pat)
11406 return 0;
11407 emit_insn (pat);
11408 return target;
11409}
0ac78517
R		 11410
11411void
cf277499 11412sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
0ac78517
R		 11413{
11414 rtx sel0 = const0_rtx;
11415 rtx sel1 = const1_rtx;
cf277499 11416 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
0ac78517
R		 11417 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
11418
11419 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
11420 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
11421}
11422
11423void
cf277499 11424sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
0ac78517 11425{
0ac78517
R		 11426 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
11427
f8be3f56
KK		 11428 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
11429 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
0ac78517
R		 11430}
11431
347146a4
KK		 11432/* Return true if hard register REGNO can hold a value of machine-mode MODE.
11433 We can allow any mode in any general register. The special registers
11434 only allow SImode. Don't allow any mode in the PR.
11435
11436 We cannot hold DCmode values in the XD registers because alter_reg
11437 handles subregs of them incorrectly. We could work around this by
11438 spacing the XD registers like the DR registers, but this would require
11439 additional memory in every compilation to hold larger register vectors.
11440 We could hold SFmode / SCmode values in XD registers, but that
11441 would require a tertiary reload when reloading from / to memory,
11442 and a secondary reload to reload from / to general regs; that
11443 seems to be a loosing proposition.
11444
11445 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
11446 it won't be ferried through GP registers first. */
11447
11448bool
11449sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11450{
11451 if (SPECIAL_REGISTER_P (regno))
11452 return mode == SImode;
11453
11454 if (regno == FPUL_REG)
11455 return (mode == SImode || mode == SFmode);
11456
11457 if (FP_REGISTER_P (regno) && mode == SFmode)
11458 return true;
11459
11460 if (mode == V2SFmode)
11461 {
11462 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
11463 || GENERAL_REGISTER_P (regno)))
11464 return true;
11465 else
11466 return false;
11467 }
11468
11469 if (mode == V4SFmode)
11470 {
11471 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
11472 || GENERAL_REGISTER_P (regno))
11473 return true;
11474 else
11475 return false;
11476 }
11477
11478 if (mode == V16SFmode)
11479 {
11480 if (TARGET_SHMEDIA)
11481 {
11482 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
11483 return true;
11484 else
11485 return false;
11486 }
11487 else
11488 return regno == FIRST_XD_REG;
11489 }
11490
11491 if (FP_REGISTER_P (regno))
11492 {
11493 if (mode == SFmode
11494 || mode == SImode
11495 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
11496 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
11497 || mode == DCmode
11498 || (TARGET_SHMEDIA
11499 && (mode == DFmode || mode == DImode
11500 || mode == V2SFmode || mode == TImode)))
11501 && ((regno - FIRST_FP_REG) & 1) == 0)
11502 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
11503 && ((regno - FIRST_FP_REG) & 3) == 0))
11504 return true;
11505 else
11506 return false;
11507 }
11508
11509 if (XD_REGISTER_P (regno))
11510 return mode == DFmode;
11511
11512 if (TARGET_REGISTER_P (regno))
11513 return (mode == DImode || mode == SImode || mode == PDImode);
11514
11515 if (regno == PR_REG)
11516 return mode == SImode;
11517
11518 if (regno == FPSCR_REG)
11519 return mode == PSImode;
11520
11521 /* FIXME. This works around PR target/37633 for -O0. */
11522 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
11523 {
11524 unsigned int n = GET_MODE_SIZE (mode) / 8;
11525
11526 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
11527 && regno <= FIRST_GENERAL_REG + 14)
11528 return false;
11529 }
11530
11531 return true;
11532}
11533
cff9f8d5
AH		 11534/* Return the class of registers for which a mode change from FROM to TO
11535 is invalid. */
b0c42aed 11536bool
cf277499 11537sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
0a2aaacc 11538 enum reg_class rclass)
cff9f8d5 11539{
312209c6
AO		 11540 /* We want to enable the use of SUBREGs as a means to
11541 VEC_SELECT a single element of a vector. */
11542 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
0a2aaacc 11543 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
312209c6 11544
cff9f8d5
AH		 11545 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
11546 {
832a3292
KH		 11547 if (TARGET_LITTLE_ENDIAN)
11548 {
11549 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
0a2aaacc 11550 return reg_classes_intersect_p (DF_REGS, rclass);
832a3292
KH		 11551 }
11552 else
11553 {
11554 if (GET_MODE_SIZE (from) < 8)
0a2aaacc 11555 return reg_classes_intersect_p (DF_HI_REGS, rclass);
832a3292 11556 }
cff9f8d5 11557 }
b0c42aed 11558 return 0;
cff9f8d5
AH		 11559}
11560
42db504c
SB		 11561/* Return true if registers in machine mode MODE will likely be
11562 allocated to registers in small register classes. */
11563
9c265c4d 11564bool
42db504c
SB		 11565sh_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED)
11566{
11567 return (! TARGET_SHMEDIA);
11568}
ea4210ef
RS		 11569
11570/* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
11571 that label is used. */
11572
11573void
cf277499 11574sh_mark_label (rtx address, int nuses)
ea4210ef
RS		 11575{
11576 if (GOTOFF_P (address))
11577 {
11578 /* Extract the label or symbol. */
11579 address = XEXP (address, 0);
11580 if (GET_CODE (address) == PLUS)
11581 address = XEXP (address, 0);
11582 address = XVECEXP (address, 0, 0);
11583 }
11584 if (GET_CODE (address) == LABEL_REF
f3536097 11585 && LABEL_P (XEXP (address, 0)))
ea4210ef
RS		 11586 LABEL_NUSES (XEXP (address, 0)) += nuses;
11587}
11588
95c0af87
JR		 11589/* Compute extra cost of moving data between one register class
11590 and another. */
11591
ec555f32
R		 11592/* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
11593 uses this information. Hence, the general register <-> floating point
95c0af87
JR		 11594 register information here is not used for SFmode. */
11595
e7a8f681 11596static int
cf277499 11597sh_register_move_cost (enum machine_mode mode,
e7a8f681 11598 reg_class_t srcclass, reg_class_t dstclass)
95c0af87
JR		 11599{
11600 if (dstclass == T_REGS || dstclass == PR_REGS)
11601 return 10;
11602
b1dcf523
DD		 11603 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
11604 return 4;
11605
ec555f32
R		 11606 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
11607 && REGCLASS_HAS_FP_REG (srcclass)
11608 && REGCLASS_HAS_FP_REG (dstclass))
11609 return 4;
11610
9c24200c
KK		 11611 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
11612 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
11613
a60a9553 11614 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
832a3292 11615 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
a60a9553
R		 11616 return 9;
11617
95c0af87
JR		 11618 if ((REGCLASS_HAS_FP_REG (dstclass)
11619 && REGCLASS_HAS_GENERAL_REG (srcclass))
11620 || (REGCLASS_HAS_GENERAL_REG (dstclass)
11621 && REGCLASS_HAS_FP_REG (srcclass)))
832a3292
KH		 11622 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
11623 * ((GET_MODE_SIZE (mode) + 7) / 8U));
95c0af87
JR		 11624
11625 if ((dstclass == FPUL_REGS
11626 && REGCLASS_HAS_GENERAL_REG (srcclass))
11627 || (srcclass == FPUL_REGS
11628 && REGCLASS_HAS_GENERAL_REG (dstclass)))
11629 return 5;
11630
11631 if ((dstclass == FPUL_REGS
11632 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
f676971a 11633 || (srcclass == FPUL_REGS
95c0af87
JR		 11634 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
11635 return 7;
11636
11637 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11638 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11639 return 20;
11640
73a4d10b
R		 11641 /* ??? ptabs faults on (value & 0x3) == 0x3 */
11642 if (TARGET_SHMEDIA
11643 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
11644 {
7dd2f19b
RS		 11645 if (sh_gettrcost >= 0)
11646 return sh_gettrcost;
73a4d10b
R		 11647 else if (!TARGET_PT_FIXED)
11648 return 100;
11649 }
11650
95c0af87
JR		 11651 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11652 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11653 return 4;
11654
ec555f32
R		 11655 if (TARGET_SHMEDIA
11656 || (TARGET_FMOVD
11657 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
11658 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
11659 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
11660
11661 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
95c0af87
JR		 11662}
11663
cf277499 11664static rtx emit_load_ptr (rtx, rtx);
1aa03f38
R		 11665
11666static rtx
cf277499 11667emit_load_ptr (rtx reg, rtx addr)
1aa03f38 11668{
57d38024 11669 rtx mem = gen_const_mem (ptr_mode, addr);
1aa03f38
R		 11670
11671 if (Pmode != ptr_mode)
11672 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
11673 return emit_move_insn (reg, mem);
11674}
11675
73a4d10b 11676static void
cf277499
SB		 11677sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11678 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11679 tree function)
1aa03f38
R		 11680{
11681 CUMULATIVE_ARGS cum;
11682 int structure_value_byref = 0;
0a2aaacc 11683 rtx this_rtx, this_value, sibcall, insns, funexp;
1aa03f38 11684 tree funtype = TREE_TYPE (function);
735cb76e 11685 int simple_add = CONST_OK_FOR_ADD (delta);
1aa03f38
R		 11686 int did_load = 0;
11687 rtx scratch0, scratch1, scratch2;
73a4d10b 11688 unsigned i;
1aa03f38
R		 11689
11690 reload_completed = 1;
fe3ad572 11691 epilogue_completed = 1;
1aa03f38
R		 11692 current_function_uses_only_leaf_regs = 1;
11693
2e040219 11694 emit_note (NOTE_INSN_PROLOGUE_END);
1aa03f38
R		 11695
11696 /* Find the "this" pointer. We have such a wide range of ABIs for the
11697 SH that it's best to do this completely machine independently.
f676971a 11698 "this" is passed as first argument, unless a structure return pointer
1aa03f38 11699 comes first, in which case "this" comes second. */
0f6937fe 11700 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
1aa03f38 11701#ifndef PCC_STATIC_STRUCT_RETURN
61f71b34 11702 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
1aa03f38
R		 11703 structure_value_byref = 1;
11704#endif /* not PCC_STATIC_STRUCT_RETURN */
61f71b34 11705 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
f676971a 11706 {
1aa03f38
R		 11707 tree ptype = build_pointer_type (TREE_TYPE (funtype));
11708
b64336b8 11709 sh_function_arg_advance (&cum, Pmode, ptype, true);
1aa03f38 11710 }
b64336b8 11711 this_rtx = sh_function_arg (&cum, Pmode, ptr_type_node, true);
1aa03f38
R		 11712
11713 /* For SHcompact, we only have r0 for a scratch register: r1 is the
11714 static chain pointer (even if you can't have nested virtual functions
11715 right now, someone might implement them sometime), and the rest of the
11716 registers are used for argument passing, are callee-saved, or reserved. */
73a4d10b
R		 11717 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
11718 -ffixed-reg has been used. */
11719 if (! call_used_regs[0] || fixed_regs[0])
11720 error ("r0 needs to be available as a call-clobbered register");
1aa03f38
R		 11721 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
11722 if (! TARGET_SH5)
11723 {
73a4d10b
R		 11724 if (call_used_regs[1] && ! fixed_regs[1])
11725 scratch1 = gen_rtx_REG (ptr_mode, 1);
1aa03f38
R		 11726 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
11727 pointing where to return struct values. */
73a4d10b
R		 11728 if (call_used_regs[3] && ! fixed_regs[3])
11729 scratch2 = gen_rtx_REG (Pmode, 3);
1aa03f38
R		 11730 }
11731 else if (TARGET_SHMEDIA)
11732 {
73a4d10b
R		 11733 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
11734 if (i != REGNO (scratch0) &&
11735 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
11736 {
11737 scratch1 = gen_rtx_REG (ptr_mode, i);
11738 break;
11739 }
11740 if (scratch1 == scratch0)
d8a07487 11741 error ("need a second call-clobbered general purpose register");
73a4d10b
R		 11742 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
11743 if (call_used_regs[i] && ! fixed_regs[i])
11744 {
11745 scratch2 = gen_rtx_REG (Pmode, i);
11746 break;
11747 }
11748 if (scratch2 == scratch0)
d8a07487 11749 error ("need a call-clobbered target register");
1aa03f38
R		 11750 }
11751
0a2aaacc 11752 this_value = plus_constant (this_rtx, delta);
1aa03f38
R		 11753 if (vcall_offset
11754 && (simple_add || scratch0 != scratch1)
11755 && strict_memory_address_p (ptr_mode, this_value))
11756 {
11757 emit_load_ptr (scratch0, this_value);
11758 did_load = 1;
11759 }
11760
11761 if (!delta)
11762 ; /* Do nothing. */
11763 else if (simple_add)
0a2aaacc 11764 emit_move_insn (this_rtx, this_value);
1aa03f38
R		 11765 else
11766 {
11767 emit_move_insn (scratch1, GEN_INT (delta));
0a2aaacc 11768 emit_insn (gen_add2_insn (this_rtx, scratch1));
1aa03f38
R		 11769 }
11770
11771 if (vcall_offset)
11772 {
11773 rtx offset_addr;
11774
11775 if (!did_load)
0a2aaacc 11776 emit_load_ptr (scratch0, this_rtx);
1aa03f38
R		 11777
11778 offset_addr = plus_constant (scratch0, vcall_offset);
11779 if (strict_memory_address_p (ptr_mode, offset_addr))
11780 ; /* Do nothing. */
73a4d10b 11781 else if (! TARGET_SH5 && scratch0 != scratch1)
1aa03f38
R		 11782 {
11783 /* scratch0 != scratch1, and we have indexed loads. Get better
11784 schedule by loading the offset into r1 and using an indexed
11785 load - then the load of r1 can issue before the load from
0a2aaacc 11786 (this_rtx + delta) finishes. */
1aa03f38
R		 11787 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11788 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
11789 }
735cb76e 11790 else if (CONST_OK_FOR_ADD (vcall_offset))
1aa03f38
R		 11791 {
11792 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
11793 offset_addr = scratch0;
11794 }
11795 else if (scratch0 != scratch1)
11796 {
11797 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11798 emit_insn (gen_add2_insn (scratch0, scratch1));
11799 offset_addr = scratch0;
11800 }
11801 else
f5b9e7c9 11802 gcc_unreachable (); /* FIXME */
1aa03f38
R		 11803 emit_load_ptr (scratch0, offset_addr);
11804
832a3292 11805 if (Pmode != ptr_mode)
1aa03f38 11806 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
0a2aaacc 11807 emit_insn (gen_add2_insn (this_rtx, scratch0));
1aa03f38
R		 11808 }
11809
11810 /* Generate a tail call to the target function. */
11811 if (! TREE_USED (function))
11812 {
11813 assemble_external (function);
11814 TREE_USED (function) = 1;
11815 }
11816 funexp = XEXP (DECL_RTL (function), 0);
73a4d10b
R		 11817 /* If the function is overridden, so is the thunk, hence we don't
11818 need GOT addressing even if this is a public symbol. */
11819#if 0
11820 if (TARGET_SH1 && ! flag_weak)
11821 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
11822 else
11823#endif
11824 if (TARGET_SH2 && flag_pic)
11825 {
11826 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
11827 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
11828 }
11829 else
11830 {
11831 if (TARGET_SHMEDIA && flag_pic)
11832 {
11833 funexp = gen_sym2PIC (funexp);
11834 PUT_MODE (funexp, Pmode);
11835 }
11836 emit_move_insn (scratch2, funexp);
11837 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
11838 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
11839 }
11840 sibcall = emit_call_insn (sibcall);
1aa03f38 11841 SIBLING_CALL_P (sibcall) = 1;
0a2aaacc 11842 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
1aa03f38
R		 11843 emit_barrier ();
11844
a2855205 11845 /* Run just enough of rest_of_compilation to do scheduling and get
1aa03f38
R		 11846 the insns emitted. Note that use_thunk calls
11847 assemble_start_function and assemble_end_function. */
a2855205 11848
55e092c4 11849 insn_locators_alloc ();
1aa03f38
R		 11850 insns = get_insns ();
11851
6fb5fa3c
DB		 11852 if (optimize > 0)
11853 {
11854 if (! cfun->cfg)
eb6cbf91 11855 init_flow (cfun);
6fb5fa3c
DB		 11856 split_all_insns_noflow ();
11857 }
1aa03f38 11858
18dbd950 11859 sh_reorg ();
1aa03f38
R		 11860
11861 if (optimize > 0 && flag_delayed_branch)
10d22567 11862 dbr_schedule (insns);
384a8760 11863
1aa03f38
R		 11864 shorten_branches (insns);
11865 final_start_function (insns, file, 1);
c9d691e9 11866 final (insns, file, 1);
1aa03f38
R		 11867 final_end_function ();
11868
1aa03f38 11869 reload_completed = 0;
fe3ad572 11870 epilogue_completed = 0;
1aa03f38
R		 11871}
11872
90534361 11873rtx
73a4d10b 11874function_symbol (rtx target, const char *name, enum sh_function_kind kind)
90534361 11875{
73a4d10b
R		 11876 rtx sym;
11877
11878 /* If this is not an ordinary function, the name usually comes from a
11879 string literal or an sprintf buffer. Make sure we use the same
11880 string consistently, so that cse will be able to unify address loads. */
11881 if (kind != FUNCTION_ORDINARY)
11882 name = IDENTIFIER_POINTER (get_identifier (name));
11883 sym = gen_rtx_SYMBOL_REF (Pmode, name);
90534361 11884 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
73a4d10b
R		 11885 if (flag_pic)
11886 switch (kind)
11887 {
11888 case FUNCTION_ORDINARY:
11889 break;
11890 case SFUNC_GOT:
11891 {
11892 rtx reg = target ? target : gen_reg_rtx (Pmode);
11893
11894 emit_insn (gen_symGOT2reg (reg, sym));
11895 sym = reg;
11896 break;
11897 }
11898 case SFUNC_STATIC:
11899 {
11900 /* ??? To allow cse to work, we use GOTOFF relocations.
11901 we could add combiner patterns to transform this into
11902 straight pc-relative calls with sym2PIC / bsrf when
11903 label load and function call are still 1:1 and in the
11904 same basic block during combine. */
11905 rtx reg = target ? target : gen_reg_rtx (Pmode);
11906
11907 emit_insn (gen_symGOTOFF2reg (reg, sym));
11908 sym = reg;
11909 break;
11910 }
11911 }
11912 if (target && sym != target)
11913 {
11914 emit_move_insn (target, sym);
11915 return target;
11916 }
90534361
R		 11917 return sym;
11918}
11919
fada1961
R		 11920/* Find the number of a general purpose register in S. */
11921static int
11922scavenge_reg (HARD_REG_SET *s)
11923{
11924 int r;
11925 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11926 if (TEST_HARD_REG_BIT (*s, r))
11927 return r;
11928 return -1;
11929}
11930
11931rtx
11932sh_get_pr_initial_val (void)
11933{
7d73a2ba
R		 11934 rtx val;
11935
b869f904
R		 11936 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11937 PR register on SHcompact, because it might be clobbered by the prologue.
7d73a2ba 11938 We check first if that is known to be the case. */
b869f904 11939 if (TARGET_SHCOMPACT
38173d38 11940 && ((crtl->args.info.call_cookie
7d73a2ba 11941 & ~ CALL_COOKIE_RET_TRAMP (1))
e3b5732b 11942 || crtl->saves_all_registers))
57d38024 11943 return gen_frame_mem (SImode, return_address_pointer_rtx);
7d73a2ba
R		 11944
11945 /* If we haven't finished rtl generation, there might be a nonlocal label
11946 that we haven't seen yet.
b3a13419
ILT		 11947 ??? get_hard_reg_initial_val fails if it is called after register
11948 allocation has started, unless it has been called before for the
11949 same register. And even then, we end in trouble if we didn't use
11950 the register in the same basic block before. So call
11951 get_hard_reg_initial_val now and wrap it in an unspec if we might
11952 need to replace it. */
dce20bbc
R		 11953 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11954 combine can put the pseudo returned by get_hard_reg_initial_val into
11955 instructions that need a general purpose registers, which will fail to
11956 be recognized when the pseudo becomes allocated to PR. */
7d73a2ba
R		 11957 val
11958 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
dce20bbc 11959 if (TARGET_SH1)
7d73a2ba
R		 11960 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11961 return val;
fada1961
R		 11962}
11963
3db1b434 11964int
f90b7a5a 11965sh_expand_t_scc (rtx operands[])
3db1b434 11966{
f90b7a5a
PB		 11967 enum rtx_code code = GET_CODE (operands[1]);
11968 rtx target = operands[0];
11969 rtx op0 = operands[2];
11970 rtx op1 = operands[3];
3db1b434
R		 11971 rtx result = target;
11972 HOST_WIDE_INT val;
11973
f3536097
SZ		 11974 if (!REG_P (op0) || REGNO (op0) != T_REG
11975 || !CONST_INT_P (op1))
3db1b434 11976 return 0;
f3536097 11977 if (!REG_P (result))
3db1b434 11978 result = gen_reg_rtx (SImode);
f90b7a5a 11979 val = INTVAL (op1);
3db1b434
R		 11980 if ((code == EQ && val == 1) || (code == NE && val == 0))
11981 emit_insn (gen_movt (result));
f326a6cb
N		 11982 else if (TARGET_SH2A && ((code == EQ && val == 0)
11983 || (code == NE && val == 1)))
c185de40 11984 emit_insn (gen_xorsi3_movrt (result));
3db1b434
R		 11985 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11986 {
c41c1387 11987 emit_clobber (result);
3db1b434 11988 emit_insn (gen_subc (result, result, result));
a556fd39 11989 emit_insn (gen_addsi3 (result, result, const1_rtx));
3db1b434
R		 11990 }
11991 else if (code == EQ || code == NE)
11992 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11993 else
11994 return 0;
11995 if (result != target)
11996 emit_move_insn (target, result);
11997 return 1;
11998}
11999
07d7d2f4
R		 12000/* INSN is an sfunc; return the rtx that describes the address used. */
12001static rtx
12002extract_sfunc_addr (rtx insn)
12003{
12004 rtx pattern, part = NULL_RTX;
12005 int len, i;
12006
12007 pattern = PATTERN (insn);
12008 len = XVECLEN (pattern, 0);
12009 for (i = 0; i < len; i++)
12010 {
12011 part = XVECEXP (pattern, 0, i);
12012 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
12013 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
12014 return XEXP (part, 0);
12015 }
f5b9e7c9
NS		 12016 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
12017 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
07d7d2f4
R		 12018}
12019
12020/* Verify that the register in use_sfunc_addr still agrees with the address
12021 used in the sfunc. This prevents fill_slots_from_thread from changing
12022 use_sfunc_addr.
12023 INSN is the use_sfunc_addr instruction, and REG is the register it
12024 guards. */
12025int
12026check_use_sfunc_addr (rtx insn, rtx reg)
12027{
12028 /* Search for the sfunc. It should really come right after INSN. */
12029 while ((insn = NEXT_INSN (insn)))
12030 {
f3536097 12031 if (LABEL_P (insn) || JUMP_P (insn))
07d7d2f4
R		 12032 break;
12033 if (! INSN_P (insn))
12034 continue;
f676971a 12035
07d7d2f4
R		 12036 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
12037 insn = XVECEXP (PATTERN (insn), 0, 0);
12038 if (GET_CODE (PATTERN (insn)) != PARALLEL
12039 || get_attr_type (insn) != TYPE_SFUNC)
12040 continue;
12041 return rtx_equal_p (extract_sfunc_addr (insn), reg);
12042 }
f5b9e7c9 12043 gcc_unreachable ();
07d7d2f4
R		 12044}
12045
312209c6
AO		 12046/* This function returns a constant rtx that represents pi / 2**15 in
12047 SFmode. it's used to scale SFmode angles, in radians, to a
12048 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
12049 maps to 0x10000). */
12050
12051static GTY(()) rtx sh_fsca_sf2int_rtx;
12052
12053rtx
12054sh_fsca_sf2int (void)
12055{
12056 if (! sh_fsca_sf2int_rtx)
12057 {
12058 REAL_VALUE_TYPE rv;
12059
12060 real_from_string (&rv, "10430.378350470453");
12061 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
12062 }
12063
12064 return sh_fsca_sf2int_rtx;
12065}
f676971a 12066
312209c6
AO		 12067/* This function returns a constant rtx that represents pi / 2**15 in
12068 DFmode. it's used to scale DFmode angles, in radians, to a
12069 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
12070 maps to 0x10000). */
12071
12072static GTY(()) rtx sh_fsca_df2int_rtx;
12073
12074rtx
12075sh_fsca_df2int (void)
12076{
12077 if (! sh_fsca_df2int_rtx)
12078 {
12079 REAL_VALUE_TYPE rv;
12080
12081 real_from_string (&rv, "10430.378350470453");
12082 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
12083 }
12084
12085 return sh_fsca_df2int_rtx;
12086}
f676971a 12087
312209c6
AO		 12088/* This function returns a constant rtx that represents 2**15 / pi in
12089 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
12090 of a full circle back to a SFmode value, i.e., 0x10000 maps to
12091 2*pi). */
12092
12093static GTY(()) rtx sh_fsca_int2sf_rtx;
12094
12095rtx
12096sh_fsca_int2sf (void)
12097{
12098 if (! sh_fsca_int2sf_rtx)
12099 {
12100 REAL_VALUE_TYPE rv;
12101
12102 real_from_string (&rv, "9.587379924285257e-5");
12103 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
12104 }
12105
12106 return sh_fsca_int2sf_rtx;
12107}
cc15e98f 12108
8b0add27 12109/* Initialize the CUMULATIVE_ARGS structure. */
cc15e98f
NC		 12110
12111void
12112sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
12113 tree fntype,
12114 rtx libname ATTRIBUTE_UNUSED,
12115 tree fndecl,
12116 signed int n_named_args,
12117 enum machine_mode mode)
12118{
12119 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
12120 pcum->free_single_fp_reg = 0;
12121 pcum->stack_regs = 0;
12122 pcum->byref_regs = 0;
12123 pcum->byref = 0;
12124 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
12125
12126 /* XXX - Should we check TARGET_HITACHI here ??? */
12127 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
12128
12129 if (fntype)
12130 {
12131 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
12132 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
f4da8dce 12133 pcum->prototype_p = prototype_p (fntype);
cc15e98f
NC		 12134 pcum->arg_count [(int) SH_ARG_INT]
12135 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
12136
12137 pcum->call_cookie
12138 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
12139 && pcum->arg_count [(int) SH_ARG_INT] == 0
12140 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
12141 ? int_size_in_bytes (TREE_TYPE (fntype))
12142 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
12143 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
12144 == FIRST_RET_REG));
12145 }
12146 else
12147 {
12148 pcum->arg_count [(int) SH_ARG_INT] = 0;
12149 pcum->prototype_p = FALSE;
12150 if (mode != VOIDmode)
12151 {
29832164 12152 pcum->call_cookie =
cc15e98f
NC		 12153 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
12154 && GET_MODE_SIZE (mode) > 4
12155 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
12156
12157 /* If the default ABI is the Renesas ABI then all library
12158 calls must assume that the library will be using the
12159 Renesas ABI. So if the function would return its result
12160 in memory then we must force the address of this memory
12161 block onto the stack. Ideally we would like to call
12162 targetm.calls.return_in_memory() here but we do not have
8b0add27 12163 the TYPE or the FNDECL available so we synthesize the
cc15e98f
NC		 12164 contents of that function as best we can. */
12165 pcum->force_mem =
c0fb94d7 12166 (TARGET_DEFAULT & MASK_HITACHI)
cc15e98f
NC		 12167 && (mode == BLKmode
12168 || (GET_MODE_SIZE (mode) > 4
12169 && !(mode == DFmode
12170 && TARGET_FPU_DOUBLE)));
12171 }
12172 else
12173 {
12174 pcum->call_cookie = 0;
12175 pcum->force_mem = FALSE;
12176 }
12177 }
12178}
12179
73a4d10b
R		 12180/* Replace any occurrence of FROM(n) in X with TO(n). The function does
12181 not enter into CONST_DOUBLE for the replace.
12182
12183 Note that copying is not done so X must not be shared unless all copies
12184 are to be modified.
12185
12186 This is like replace_rtx, except that we operate on N_REPLACEMENTS
30dc60c7 12187 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
73a4d10b
R		 12188 replacements[n*2+1] - and that we take mode changes into account.
12189
30dc60c7 12190 If a replacement is ambiguous, return NULL_RTX.
73a4d10b
R		 12191
12192 If MODIFY is zero, don't modify any rtl in place,
12193 just return zero or nonzero for failure / success. */
12194
12195rtx
12196replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
12197{
12198 int i, j;
12199 const char *fmt;
12200
12201 /* The following prevents loops occurrence when we change MEM in
12202 CONST_DOUBLE onto the same CONST_DOUBLE. */
12203 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
12204 return x;
12205
12206 for (i = n_replacements - 1; i >= 0 ; i--)
12207 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
12208 return replacements[i*2+1];
12209
12210 /* Allow this function to make replacements in EXPR_LISTs. */
12211 if (x == 0)
12212 return 0;
12213
12214 if (GET_CODE (x) == SUBREG)
12215 {
0a2aaacc 12216 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
73a4d10b
R		 12217 n_replacements, modify);
12218
f3536097 12219 if (CONST_INT_P (new_rtx))
73a4d10b 12220 {
0a2aaacc 12221 x = simplify_subreg (GET_MODE (x), new_rtx,
73a4d10b
R		 12222 GET_MODE (SUBREG_REG (x)),
12223 SUBREG_BYTE (x));
12224 if (! x)
12225 abort ();
12226 }
12227 else if (modify)
0a2aaacc 12228 SUBREG_REG (x) = new_rtx;
73a4d10b
R		 12229
12230 return x;
12231 }
f3536097 12232 else if (REG_P (x))
73a4d10b
R		 12233 {
12234 unsigned regno = REGNO (x);
12235 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
12236 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
12237 rtx result = NULL_RTX;
12238
12239 for (i = n_replacements - 1; i >= 0; i--)
12240 {
12241 rtx from = replacements[i*2];
12242 rtx to = replacements[i*2+1];
12243 unsigned from_regno, from_nregs, to_regno, new_regno;
12244
f3536097 12245 if (!REG_P (from))
73a4d10b
R		 12246 continue;
12247 from_regno = REGNO (from);
12248 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
12249 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
12250 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
12251 {
12252 if (regno < from_regno
12253 || regno + nregs > from_regno + nregs
f3536097 12254 || !REG_P (to)
73a4d10b
R		 12255 || result)
12256 return NULL_RTX;
12257 to_regno = REGNO (to);
12258 if (to_regno < FIRST_PSEUDO_REGISTER)
12259 {
12260 new_regno = regno + to_regno - from_regno;
12261 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
12262 != nregs)
12263 return NULL_RTX;
12264 result = gen_rtx_REG (GET_MODE (x), new_regno);
12265 }
12266 else if (GET_MODE (x) <= GET_MODE (to))
12267 result = gen_lowpart_common (GET_MODE (x), to);
12268 else
12269 result = gen_lowpart_SUBREG (GET_MODE (x), to);
12270 }
12271 }
12272 return result ? result : x;
12273 }
12274 else if (GET_CODE (x) == ZERO_EXTEND)
12275 {
0a2aaacc 12276 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
73a4d10b
R		 12277 n_replacements, modify);
12278
f3536097 12279 if (CONST_INT_P (new_rtx))
73a4d10b
R		 12280 {
12281 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
0a2aaacc 12282 new_rtx, GET_MODE (XEXP (x, 0)));
73a4d10b
R		 12283 if (! x)
12284 abort ();
12285 }
12286 else if (modify)
0a2aaacc 12287 XEXP (x, 0) = new_rtx;
73a4d10b
R		 12288
12289 return x;
12290 }
12291
12292 fmt = GET_RTX_FORMAT (GET_CODE (x));
12293 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
12294 {
0a2aaacc 12295 rtx new_rtx;
73a4d10b
R		 12296
12297 if (fmt[i] == 'e')
12298 {
0a2aaacc 12299 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
73a4d10b 12300 n_replacements, modify);
0a2aaacc 12301 if (!new_rtx)
73a4d10b
R		 12302 return NULL_RTX;
12303 if (modify)
0a2aaacc 12304 XEXP (x, i) = new_rtx;
73a4d10b
R		 12305 }
12306 else if (fmt[i] == 'E')
12307 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12308 {
0a2aaacc 12309 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
73a4d10b 12310 n_replacements, modify);
0a2aaacc 12311 if (!new_rtx)
73a4d10b
R		 12312 return NULL_RTX;
12313 if (modify)
0a2aaacc 12314 XVECEXP (x, i, j) = new_rtx;
73a4d10b
R		 12315 }
12316 }
12317
12318 return x;
12319}
12320
12321rtx
12322sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
12323{
12324 enum rtx_code code = TRUNCATE;
12325
12326 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
12327 {
12328 rtx inner = XEXP (x, 0);
12329 enum machine_mode inner_mode = GET_MODE (inner);
12330
12331 if (inner_mode == mode)
12332 return inner;
12333 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
12334 x = inner;
12335 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
12336 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
12337 {
12338 code = GET_CODE (x);
12339 x = inner;
12340 }
12341 }
12342 return gen_rtx_fmt_e (code, mode, x);
12343}
12344
12345/* called via for_each_rtx after reload, to clean up truncates of
12346 registers that span multiple actual hard registers. */
12347int
12348shmedia_cleanup_truncate (rtx *p, void *n_changes)
12349{
12350 rtx x = *p, reg;
12351
12352 if (GET_CODE (x) != TRUNCATE)
12353 return 0;
12354 reg = XEXP (x, 0);
f3536097 12355 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && REG_P (reg))
73a4d10b
R		 12356 {
12357 enum machine_mode reg_mode = GET_MODE (reg);
12358 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
12359 subreg_lowpart_offset (DImode, reg_mode));
12360 *(int*) n_changes += 1;
12361 return -1;
12362 }
12363 return 0;
12364}
12365
12366/* Load and store depend on the highpart of the address. However,
12367 set_attr_alternative does not give well-defined results before reload,
12368 so we must look at the rtl ourselves to see if any of the feeding
12369 registers is used in a memref. */
12370
12371/* Called by sh_contains_memref_p via for_each_rtx. */
12372static int
12373sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
12374{
f3536097 12375 return (MEM_P (*loc));
73a4d10b
R		 12376}
12377
a4d05547 12378/* Return nonzero iff INSN contains a MEM. */
73a4d10b
R		 12379int
12380sh_contains_memref_p (rtx insn)
12381{
12382 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
12383}
12384
5c7cafa8
CB		 12385/* Return nonzero iff INSN loads a banked register. */
12386int
12387sh_loads_bankedreg_p (rtx insn)
12388{
12389 if (GET_CODE (PATTERN (insn)) == SET)
12390 {
12391 rtx op = SET_DEST (PATTERN(insn));
12392 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
12393 return 1;
12394 }
12395
12396 return 0;
12397}
12398
73a4d10b
R		 12399/* FNADDR is the MEM expression from a call expander. Return an address
12400 to use in an SHmedia insn pattern. */
12401rtx
12402shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
12403{
12404 int is_sym;
12405
12406 fnaddr = XEXP (fnaddr, 0);
12407 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
12408 if (flag_pic && is_sym)
12409 {
12410 if (! SYMBOL_REF_LOCAL_P (fnaddr))
12411 {
12412 rtx reg = gen_reg_rtx (Pmode);
12413
12414 /* We must not use GOTPLT for sibcalls, because PIC_REG
12415 must be restored before the PLT code gets to run. */
12416 if (is_sibcall)
12417 emit_insn (gen_symGOT2reg (reg, fnaddr));
12418 else
12419 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
12420 fnaddr = reg;
12421 }
12422 else
12423 {
12424 fnaddr = gen_sym2PIC (fnaddr);
12425 PUT_MODE (fnaddr, Pmode);
12426 }
12427 }
12428 /* If ptabs might trap, make this visible to the rest of the compiler.
12429 We generally assume that symbols pertain to valid locations, but
12430 it is possible to generate invalid symbols with asm or linker tricks.
30dc60c7 12431 In a list of functions where each returns its successor, an invalid
73a4d10b
R		 12432 symbol might denote an empty list. */
12433 if (!TARGET_PT_FIXED
12434 && (!is_sym || TARGET_INVALID_SYMBOLS)
12435 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
12436 {
12437 rtx tr = gen_reg_rtx (PDImode);
12438
12439 emit_insn (gen_ptabs (tr, fnaddr));
12440 fnaddr = tr;
12441 }
12442 else if (! target_reg_operand (fnaddr, Pmode))
12443 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
12444 return fnaddr;
12445}
12446
486b10aa
AS		 12447/* Implement TARGET_PREFERRED_RELOAD_CLASS. */
12448
12449static reg_class_t
12450sh_preferred_reload_class (rtx x, reg_class_t rclass)
12451{
12452 if (rclass == NO_REGS
12453 && TARGET_SHMEDIA
12454 && (CONST_DOUBLE_P (x)
12455 || GET_CODE (x) == SYMBOL_REF
12456 || PIC_ADDR_P (x)))
12457 return GENERAL_REGS;
12458
12459 return rclass;
12460}
12461
12462/* Implement TARGET_SECONDARY_RELOAD. */
12463
12464static reg_class_t
a87cf97e 12465sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
8a99f6f9
R		 12466 enum machine_mode mode, secondary_reload_info *sri)
12467{
a87cf97e
JR		 12468 enum reg_class rclass = (enum reg_class) rclass_i;
12469
8a99f6f9
R		 12470 if (in_p)
12471 {
0a2aaacc 12472 if (REGCLASS_HAS_FP_REG (rclass)
8a99f6f9
R		 12473 && ! TARGET_SHMEDIA
12474 && immediate_operand ((x), mode)
12475 && ! ((fp_zero_operand (x) || fp_one_operand (x))
12476 && mode == SFmode && fldi_ok ()))
12477 switch (mode)
12478 {
12479 case SFmode:
12480 sri->icode = CODE_FOR_reload_insf__frn;
12481 return NO_REGS;
12482 case DFmode:
12483 sri->icode = CODE_FOR_reload_indf__frn;
12484 return NO_REGS;
12485 case SImode:
12486 /* ??? If we knew that we are in the appropriate mode -
12487 single precision - we could use a reload pattern directly. */
12488 return FPUL_REGS;
12489 default:
12490 abort ();
12491 }
0a2aaacc 12492 if (rclass == FPUL_REGS
f3536097 12493 && ((REG_P (x)
8a99f6f9
R		 12494 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
12495 || REGNO (x) == T_REG))
12496 || GET_CODE (x) == PLUS))
12497 return GENERAL_REGS;
0a2aaacc 12498 if (rclass == FPUL_REGS && immediate_operand (x, mode))
8a99f6f9 12499 {
d973ac5a 12500 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
8a99f6f9 12501 return GENERAL_REGS;
d973ac5a
KK		 12502 else if (mode == SFmode)
12503 return FP_REGS;
8a99f6f9
R		 12504 sri->icode = CODE_FOR_reload_insi__i_fpul;
12505 return NO_REGS;
12506 }
0a2aaacc 12507 if (rclass == FPSCR_REGS
f3536097
SZ		 12508 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
12509 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
8a99f6f9 12510 return GENERAL_REGS;
0a2aaacc 12511 if (REGCLASS_HAS_FP_REG (rclass)
8a99f6f9
R		 12512 && TARGET_SHMEDIA
12513 && immediate_operand (x, mode)
12514 && x != CONST0_RTX (GET_MODE (x))
12515 && GET_MODE (x) != V4SFmode)
12516 return GENERAL_REGS;
12517 if ((mode == QImode || mode == HImode)
12518 && TARGET_SHMEDIA && inqhi_operand (x, mode))
12519 {
12520 sri->icode = ((mode == QImode)
12521 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
12522 return NO_REGS;
12523 }
0a2aaacc 12524 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
dc3ba671 12525 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
8a99f6f9
R		 12526 return TARGET_REGS;
12527 } /* end of input-only processing. */
12528
0a2aaacc 12529 if (((REGCLASS_HAS_FP_REG (rclass)
f3536097 12530 && (REG_P (x)
8a99f6f9
R		 12531 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
12532 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
12533 && TARGET_FMOVD))))
0a2aaacc 12534 || (REGCLASS_HAS_GENERAL_REG (rclass)
f3536097 12535 && REG_P (x)
8a99f6f9
R		 12536 && FP_REGISTER_P (REGNO (x))))
12537 && ! TARGET_SHMEDIA
12538 && (mode == SFmode || mode == SImode))
12539 return FPUL_REGS;
0a2aaacc
KG		 12540 if ((rclass == FPUL_REGS
12541 || (REGCLASS_HAS_FP_REG (rclass)
8a99f6f9 12542 && ! TARGET_SHMEDIA && mode == SImode))
f3536097
SZ		 12543 && (MEM_P (x)
12544 || (REG_P (x)
8a99f6f9
R		 12545 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
12546 || REGNO (x) == T_REG
12547 || system_reg_operand (x, VOIDmode)))))
12548 {
0a2aaacc 12549 if (rclass == FPUL_REGS)
8a99f6f9
R		 12550 return GENERAL_REGS;
12551 return FPUL_REGS;
12552 }
0a2aaacc
KG		 12553 if ((rclass == TARGET_REGS
12554 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
32a7ab3d 12555 && !satisfies_constraint_Csy (x)
f3536097 12556 && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
8a99f6f9 12557 return GENERAL_REGS;
0a2aaacc 12558 if ((rclass == MAC_REGS || rclass == PR_REGS)
f3536097 12559 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
0a2aaacc 12560 && rclass != REGNO_REG_CLASS (REGNO (x)))
8a99f6f9 12561 return GENERAL_REGS;
f3536097 12562 if (rclass != GENERAL_REGS && REG_P (x)
8a99f6f9
R		 12563 && TARGET_REGISTER_P (REGNO (x)))
12564 return GENERAL_REGS;
12565 return NO_REGS;
12566}
12567
5efd84c5
NF		 12568static void
12569sh_conditional_register_usage (void)
12570{
12571 int regno;
12572 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++)
12573 if (! VALID_REGISTER_P (regno))
12574 fixed_regs[regno] = call_used_regs[regno] = 1;
12575 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */
12576 if (TARGET_SH5)
12577 {
12578 call_used_regs[FIRST_GENERAL_REG + 8]
12579 = call_used_regs[FIRST_GENERAL_REG + 9] = 1;
12580 call_really_used_regs[FIRST_GENERAL_REG + 8]
12581 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1;
12582 }
12583 if (TARGET_SHMEDIA)
12584 {
12585 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS;
12586 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]);
12587 regno_reg_class[FIRST_FP_REG] = FP_REGS;
12588 }
12589 if (flag_pic)
12590 {
12591 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
12592 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
12593 }
12594 /* Renesas saves and restores mac registers on call. */
12595 if (TARGET_HITACHI && ! TARGET_NOMACSAVE)
12596 {
12597 call_really_used_regs[MACH_REG] = 0;
12598 call_really_used_regs[MACL_REG] = 0;
12599 }
12600 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0);
12601 regno <= LAST_FP_REG; regno += 2)
12602 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno);
12603 if (TARGET_SHMEDIA)
12604 {
12605 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)
12606 if (! fixed_regs[regno] && call_really_used_regs[regno])
12607 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);
12608 }
12609 else
12610 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++)
12611 if (! fixed_regs[regno] && call_really_used_regs[regno])
12612 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);
12613}
12614
12615
73a4d10b
R		 12616enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;
12617
e2500fed 12618#include "gt-sh.h"
Mirror of https://gcc.gnu.org/git/gcc.git