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* target.h (struct gcc_target): Add calls.pass_by_reference.
[thirdparty/gcc.git] / gcc / config / sh / sh.c
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7b23765d 1/* Output routines for GCC for Renesas / SuperH SH.
530178a9 2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002,
5c836ef9 3 2003, 2004 Free Software Foundation, Inc.
7014838c 4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7208c779 6
187b36cf 7This file is part of GCC.
9b754436 8
187b36cf 9GCC is free software; you can redistribute it and/or modify
9b754436 10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
187b36cf 14GCC is distributed in the hope that it will be useful,
9b754436 15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
187b36cf 20along with GCC; see the file COPYING. If not, write to
9b754436 21the Free Software Foundation, 59 Temple Place - Suite 330,
22Boston, MA 02111-1307, USA. */
7208c779 23
7208c779 24#include "config.h"
7014838c 25#include "system.h"
805e22b2 26#include "coretypes.h"
27#include "tm.h"
b7dbbdb2 28#include "insn-config.h"
7208c779 29#include "rtl.h"
7208c779 30#include "tree.h"
7208c779 31#include "flags.h"
7208c779 32#include "expr.h"
d8fc4d0b 33#include "optabs.h"
0a893c29 34#include "function.h"
73401833 35#include "regs.h"
36#include "hard-reg-set.h"
37#include "output.h"
891b35f2 38#include "insn-attr.h"
b7dbbdb2 39#include "toplev.h"
40#include "recog.h"
1fcd08b1 41#include "c-pragma.h"
e51fa923 42#include "integrate.h"
b7dbbdb2 43#include "tm_p.h"
a767736d 44#include "target.h"
45#include "target-def.h"
30ab56ba 46#include "real.h"
e3fac27d 47#include "langhooks.h"
c83ee613 48#include "basic-block.h"
36a2dfdb 49#include "ra.h"
356907d3 50#include "cfglayout.h"
133479bd 51#include "intl.h"
f77a5bb0 52#include "sched-int.h"
5bf8e2fe 53#include "ggc.h"
20cdebf8 54#include "tree-gimple.h"
55
7208c779 56
8ded0752 57int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
58
3dfc1807 59#define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
60#define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
61
87e19636 62/* These are some macros to abstract register modes. */
63#define CONST_OK_FOR_ADD(size) \
af2c1324 64 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
87e19636 65#define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
66#define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
67#define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
68
0d687b6d 69/* Set to 1 by expand_prologue() when the function is an interrupt handler. */
70int current_function_interrupt;
71
0b89dfaf 72/* ??? The pragma interrupt support will not work for SH3. */
73401833 73/* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
74 output code for the next function appropriate for an interrupt handler. */
97595bfd 75int pragma_interrupt;
7208c779 76
15cb1799 77/* This is set by the trap_exit attribute for functions. It specifies
78 a trap number to be used in a trapa instruction at function exit
79 (instead of an rte instruction). */
80int trap_exit;
81
82/* This is used by the sp_switch attribute for functions. It specifies
83 a variable holding the address of the stack the interrupt function
84 should switch to/from at entry/exit. */
85rtx sp_switch;
86
73401833 87/* This is set by #pragma trapa, and is similar to the above, except that
88 the compiler doesn't emit code to preserve all registers. */
89static int pragma_trapa;
90
891b35f2 91/* This is set by #pragma nosave_low_regs. This is useful on the SH3,
92 which has a separate set of low regs for User and Supervisor modes.
93 This should only be used for the lowest level of interrupts. Higher levels
94 of interrupts must save the registers in case they themselves are
95 interrupted. */
96int pragma_nosave_low_regs;
97
6644435d 98/* This is used for communication between TARGET_SETUP_INCOMING_VARARGS and
73401833 99 sh_expand_prologue. */
7208c779 100int current_function_anonymous_args;
1504eb7e 101
9df03d69 102/* Global variables for machine-dependent things. */
7208c779 103
1504eb7e 104/* Which cpu are we scheduling for. */
105enum processor_type sh_cpu;
106
f77a5bb0 107/* Definitions used in ready queue reordering for first scheduling pass. */
108
109/* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
110static short *regmode_weight[2];
111
112/* Total SFmode and SImode weights of scheduled insns. */
113static int curr_regmode_pressure[2];
114
115/* If true, skip cycles for Q -> R movement. */
116static int skip_cycles = 0;
117
118/* Cached value of can_issue_more. This is cached in sh_variable_issue hook
119 and returned from sh_reorder2. */
120static short cached_can_issue_more;
121
7208c779 122/* Saved operands from the last compare to use when we generate an scc
1504eb7e 123 or bcc insn. */
7208c779 124
125rtx sh_compare_op0;
126rtx sh_compare_op1;
127
128/* Provides the class number of the smallest class containing
1504eb7e 129 reg number. */
7208c779 130
41fafa66 131enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
7208c779 132{
2e3d4844 133 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
7208c779 134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
135 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
136 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
87e19636 137 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
138 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
139 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
140 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
141 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
142 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
143 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
144 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
145 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
146 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
147 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
148 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
b00564da 149 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
152 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
87e19636 153 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
154 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
155 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
156 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
157 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
158 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
159 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
160 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
161 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
162 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
163 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
164 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
165 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
166 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
1b61190c 167 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
168 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
87e19636 169 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
170 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
171 GENERAL_REGS,
1b61190c 172};
173
87e19636 174char sh_register_names[FIRST_PSEUDO_REGISTER] \
175 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
176
177char sh_additional_register_names[ADDREGNAMES_SIZE] \
178 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
179 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
7208c779 180
181/* Provide reg_class from a letter such as appears in the machine
e04da7b6 182 description. *: target independently reserved letter.
4aa67c38 183 reg_class_from_letter['e' - 'a'] is set to NO_REGS for TARGET_FMOVD. */
7208c779 184
e04da7b6 185enum reg_class reg_class_from_letter[] =
7208c779 186{
e04da7b6 187 /* a */ ALL_REGS, /* b */ TARGET_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
188 /* e */ FP_REGS, /* f */ FP_REGS, /* g **/ NO_REGS, /* h */ NO_REGS,
189 /* i **/ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
190 /* m **/ NO_REGS, /* n **/ NO_REGS, /* o **/ NO_REGS, /* p **/ NO_REGS,
191 /* q */ NO_REGS, /* r **/ NO_REGS, /* s **/ NO_REGS, /* t */ T_REGS,
192 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
b00564da 193 /* y */ FPUL_REGS, /* z */ R0_REGS
7208c779 194};
8ded0752 195
1b61190c 196int assembler_dialect;
197
8af3db02 198static bool shmedia_space_reserved_for_target_registers;
199
04f04b72 200static void split_branches (rtx);
201static int branch_dest (rtx);
202static void force_into (rtx, rtx);
203static void print_slot (rtx);
204static rtx add_constant (rtx, enum machine_mode, rtx);
51dade95 205static void dump_table (rtx, rtx);
04f04b72 206static int hi_const (rtx);
207static int broken_move (rtx);
208static int mova_p (rtx);
209static rtx find_barrier (int, rtx, rtx);
210static int noncall_uses_reg (rtx, rtx, rtx *);
211static rtx gen_block_redirect (rtx, int, int);
212static void sh_reorg (void);
41fafa66 213static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
04f04b72 214static rtx frame_insn (rtx);
215static rtx push (int);
216static void pop (int);
217static void push_regs (HARD_REG_SET *, int);
218static int calc_live_regs (HARD_REG_SET *);
219static void mark_use (rtx, rtx *);
220static HOST_WIDE_INT rounded_frame_size (int);
221static rtx mark_constant_pool_use (rtx);
e3c541f0 222const struct attribute_spec sh_attribute_table[];
04f04b72 223static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
224static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
225static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
226static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
227static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
228static void sh_insert_attributes (tree, tree *);
229static int sh_adjust_cost (rtx, rtx, rtx, int);
230static int sh_use_dfa_interface (void);
231static int sh_issue_rate (void);
f77a5bb0 232static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
233static short find_set_regmode_weight (rtx, enum machine_mode);
234static short find_insn_regmode_weight (rtx, enum machine_mode);
235static void find_regmode_weight (int, enum machine_mode);
236static void sh_md_init_global (FILE *, int, int);
237static void sh_md_finish_global (FILE *, int);
238static int rank_for_reorder (const void *, const void *);
239static void swap_reorder (rtx *, int);
240static void ready_reorder (rtx *, int);
241static short high_pressure (enum machine_mode);
242static int sh_reorder (FILE *, int, rtx *, int *, int);
243static int sh_reorder2 (FILE *, int, rtx *, int *, int);
244static void sh_md_init (FILE *, int, int);
245static int sh_variable_issue (FILE *, int, rtx, int);
246
04f04b72 247static bool sh_function_ok_for_sibcall (tree, tree);
248
249static bool sh_cannot_modify_jumps_p (void);
e26dbf6d 250static int sh_target_reg_class (void);
8af3db02 251static bool sh_optimize_target_register_callee_saved (bool);
04f04b72 252static bool sh_ms_bitfield_layout_p (tree);
253
254static void sh_init_builtins (void);
255static void sh_media_init_builtins (void);
256static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
257static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
258static void sh_file_start (void);
259static int flow_dependent_p (rtx, rtx);
260static void flow_dependent_p_1 (rtx, rtx, void *);
261static int shiftcosts (rtx);
262static int andcosts (rtx);
263static int addsubcosts (rtx);
264static int multcosts (rtx);
265static bool unspec_caller_rtx_p (rtx);
266static bool sh_cannot_copy_insn_p (rtx);
267static bool sh_rtx_costs (rtx, int, int, int *);
268static int sh_address_cost (rtx);
8af3db02 269static int shmedia_target_regs_stack_space (HARD_REG_SET *);
270static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
271static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
41fafa66 272static int scavenge_reg (HARD_REG_SET *s);
273struct save_schedule_s;
274static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
275 struct save_schedule_s *, int);
45550790 276
04f04b72 277static rtx sh_struct_value_rtx (tree, int);
278static bool sh_return_in_memory (tree, tree);
279static rtx sh_builtin_saveregs (void);
280static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
281static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
282static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
2e15d750 283static tree sh_build_builtin_va_list (void);
20cdebf8 284static tree sh_gimplify_va_arg_expr (tree, tree, tree *, tree *);
b981d932 285static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
286 tree, bool);
45550790 287
a767736d 288\f
289/* Initialize the GCC target structure. */
e3c541f0 290#undef TARGET_ATTRIBUTE_TABLE
291#define TARGET_ATTRIBUTE_TABLE sh_attribute_table
a767736d 292
58356836 293/* The next two are used for debug info when compiling with -gdwarf. */
294#undef TARGET_ASM_UNALIGNED_HI_OP
295#define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
296#undef TARGET_ASM_UNALIGNED_SI_OP
297#define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
298
87e19636 299/* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
300#undef TARGET_ASM_UNALIGNED_DI_OP
301#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
302#undef TARGET_ASM_ALIGNED_DI_OP
303#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
304
17d9b0c3 305#undef TARGET_ASM_FUNCTION_EPILOGUE
306#define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
307
c83ee613 308#undef TARGET_ASM_OUTPUT_MI_THUNK
309#define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
310
311#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
312#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
313
92c473b8 314#undef TARGET_ASM_FILE_START
315#define TARGET_ASM_FILE_START sh_file_start
316#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
317#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
318
8ee295a7 319#undef TARGET_INSERT_ATTRIBUTES
320#define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
321
747af5e7 322#undef TARGET_SCHED_ADJUST_COST
323#define TARGET_SCHED_ADJUST_COST sh_adjust_cost
324
bea4bad2 325#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
326#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
327 sh_use_dfa_interface
328#undef TARGET_SCHED_ISSUE_RATE
329#define TARGET_SCHED_ISSUE_RATE sh_issue_rate
330
f77a5bb0 331/* The next 5 hooks have been implemented for reenabling sched1. With the
332 help of these macros we are limiting the movement of insns in sched1 to
333 reduce the register pressure. The overall idea is to keep count of SImode
334 and SFmode regs required by already scheduled insns. When these counts
335 cross some threshold values; give priority to insns that free registers.
336 The insn that frees registers is most likely to be the insn with lowest
337 LUID (original insn order); but such an insn might be there in the stalled
338 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
339 upto a max of 8 cycles so that such insns may move from Q -> R.
340
341 The description of the hooks are as below:
342
343 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
344 scheduler; it is called inside the sched_init function just after
345 find_insn_reg_weights function call. It is used to calculate the SImode
7bd28bba 346 and SFmode weights of insns of basic blocks; much similar to what
f77a5bb0 347 find_insn_reg_weights does.
348 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
349
350 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
351 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
352 (Q)->(R).
353
354 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
355 high; reorder the ready queue so that the insn with lowest LUID will be
356 issued next.
357
358 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
359 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
360
361 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
362 can be returned from TARGET_SCHED_REORDER2.
363
364 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
365
366#undef TARGET_SCHED_DFA_NEW_CYCLE
367#define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
368
369#undef TARGET_SCHED_INIT_GLOBAL
370#define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
371
372#undef TARGET_SCHED_FINISH_GLOBAL
373#define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
374
375#undef TARGET_SCHED_VARIABLE_ISSUE
376#define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
377
378#undef TARGET_SCHED_REORDER
379#define TARGET_SCHED_REORDER sh_reorder
380
381#undef TARGET_SCHED_REORDER2
382#define TARGET_SCHED_REORDER2 sh_reorder2
383
384#undef TARGET_SCHED_INIT
385#define TARGET_SCHED_INIT sh_md_init
386
87e19636 387#undef TARGET_CANNOT_MODIFY_JUMPS_P
388#define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
8af3db02 389#undef TARGET_BRANCH_TARGET_REGISTER_CLASS
390#define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
391#undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
392#define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
393 sh_optimize_target_register_callee_saved
87e19636 394
395#undef TARGET_MS_BITFIELD_LAYOUT_P
396#define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
397
e3fac27d 398#undef TARGET_INIT_BUILTINS
399#define TARGET_INIT_BUILTINS sh_init_builtins
400#undef TARGET_EXPAND_BUILTIN
401#define TARGET_EXPAND_BUILTIN sh_expand_builtin
402
805e22b2 403#undef TARGET_FUNCTION_OK_FOR_SIBCALL
404#define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
405
02359f85 406#undef TARGET_CANNOT_COPY_INSN_P
407#define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
fab7adbf 408#undef TARGET_RTX_COSTS
409#define TARGET_RTX_COSTS sh_rtx_costs
ec0457a8 410#undef TARGET_ADDRESS_COST
411#define TARGET_ADDRESS_COST sh_address_cost
fab7adbf 412
2efea8c0 413#undef TARGET_MACHINE_DEPENDENT_REORG
414#define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
415
cec78553 416#ifdef HAVE_AS_TLS
417#undef TARGET_HAVE_TLS
418#define TARGET_HAVE_TLS true
419#endif
420
45550790 421#undef TARGET_PROMOTE_PROTOTYPES
422#define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
423#undef TARGET_PROMOTE_FUNCTION_ARGS
424#define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
425#undef TARGET_PROMOTE_FUNCTION_RETURN
426#define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
427
428#undef TARGET_STRUCT_VALUE_RTX
429#define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
430#undef TARGET_RETURN_IN_MEMORY
431#define TARGET_RETURN_IN_MEMORY sh_return_in_memory
432
433#undef TARGET_EXPAND_BUILTIN_SAVEREGS
434#define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
435#undef TARGET_SETUP_INCOMING_VARARGS
436#define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
437#undef TARGET_STRICT_ARGUMENT_NAMING
438#define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
439#undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
440#define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
0336f0f0 441#undef TARGET_MUST_PASS_IN_STACK
442#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
b981d932 443#undef TARGET_PASS_BY_REFERENCE
444#define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
45550790 445
2e15d750 446#undef TARGET_BUILD_BUILTIN_VA_LIST
447#define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
20cdebf8 448#undef TARGET_GIMPLIFY_VA_ARG_EXPR
449#define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
2e15d750 450
133479bd 451#undef TARGET_PCH_VALID_P
452#define TARGET_PCH_VALID_P sh_pch_valid_p
453
f77a5bb0 454/* Return regmode weight for insn. */
455#define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
456
457/* Return current register pressure for regmode. */
458#define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
459
db281f5a 460#ifdef SYMBIAN
461
462#undef TARGET_ENCODE_SECTION_INFO
463#define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
464#undef TARGET_STRIP_NAME_ENCODING
465#define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
466#undef TARGET_CXX_IMPORT_EXPORT_CLASS
467#define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
468
469#endif /* SYMBIAN */
470
57e4bbfb 471struct gcc_target targetm = TARGET_INITIALIZER;
47c009e5 472\f
1504eb7e 473/* Print the operand address in x to the stream. */
7208c779 474
475void
04f04b72 476print_operand_address (FILE *stream, rtx x)
7208c779 477{
478 switch (GET_CODE (x))
479 {
480 case REG:
1b61190c 481 case SUBREG:
482 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
7208c779 483 break;
73401833 484
7208c779 485 case PLUS:
486 {
487 rtx base = XEXP (x, 0);
488 rtx index = XEXP (x, 1);
489
7208c779 490 switch (GET_CODE (index))
491 {
492 case CONST_INT:
26576132 493 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
1b61190c 494 reg_names[true_regnum (base)]);
7208c779 495 break;
496
497 case REG:
1b61190c 498 case SUBREG:
499 {
500 int base_num = true_regnum (base);
501 int index_num = true_regnum (index);
502
503 fprintf (stream, "@(r0,%s)",
504 reg_names[MAX (base_num, index_num)]);
505 break;
506 }
7208c779 507
508 default:
47c009e5 509 debug_rtx (x);
7208c779 510 abort ();
511 }
512 }
7208c779 513 break;
73401833 514
7208c779 515 case PRE_DEC:
1b61190c 516 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
7208c779 517 break;
518
519 case POST_INC:
1b61190c 520 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
7208c779 521 break;
522
523 default:
ecf6ff7c 524 x = mark_constant_pool_use (x);
b60f0749 525 output_addr_const (stream, x);
7208c779 526 break;
527 }
528}
529
530/* Print operand x (an rtx) in assembler syntax to file stream
531 according to modifier code.
532
47c009e5 533 '.' print a .s if insn needs delay slot
8ded0752 534 ',' print LOCAL_LABEL_PREFIX
15cb1799 535 '@' print trap, rte or rts depending upon pragma interruptness
73401833 536 '#' output a nop if there is nothing to put in the delay slot
1fc184ee 537 ''' print likelihood suffix (/u for unlikely).
73401833 538 'O' print a constant without the #
3dfc1807 539 'R' print the LSW of a dp value - changes if in little endian
3dfc1807 540 'S' print the MSW of a dp value - changes if in little endian
1b61190c 541 'T' print the next word of a dp value - same as 'R' in big endian mode.
87e19636 542 'M' print an `x' if `m' will print `base,index'.
e3fac27d 543 'N' print 'r63' if the operand is (const_int 0).
87e19636 544 'm' print a pair `base,offset' or `base,index', for LD and ST.
545 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
1b61190c 546 'o' output an operator. */
7208c779 547
548void
04f04b72 549print_operand (FILE *stream, rtx x, int code)
7208c779 550{
551 switch (code)
552 {
47c009e5 553 case '.':
3f2613e4 554 if (final_sequence
36858eff 555 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
556 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
8ded0752 557 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
558 break;
559 case ',':
560 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
47c009e5 561 break;
f3d93547 562 case '@':
15cb1799 563 if (trap_exit)
564 fprintf (stream, "trapa #%d", trap_exit);
5df3d11f 565 else if (sh_cfun_interrupt_handler_p ())
2e3d4844 566 fprintf (stream, "rte");
f3d93547 567 else
2e3d4844 568 fprintf (stream, "rts");
f3d93547 569 break;
7208c779 570 case '#':
1504eb7e 571 /* Output a nop if there's nothing in the delay slot. */
7208c779 572 if (dbr_sequence_length () == 0)
73401833 573 fprintf (stream, "\n\tnop");
7208c779 574 break;
3c4bc54e 575 case '\'':
576 {
577 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
578
579 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
580 fputs ("/u", stream);
581 break;
582 }
47c009e5 583 case 'O':
ecf6ff7c 584 x = mark_constant_pool_use (x);
97595bfd 585 output_addr_const (stream, x);
7208c779 586 break;
7208c779 587 case 'R':
73401833 588 fputs (reg_names[REGNO (x) + LSW], (stream));
589 break;
590 case 'S':
591 fputs (reg_names[REGNO (x) + MSW], (stream));
3dfc1807 592 break;
593 case 'T':
1504eb7e 594 /* Next word of a double. */
7208c779 595 switch (GET_CODE (x))
596 {
597 case REG:
598 fputs (reg_names[REGNO (x) + 1], (stream));
599 break;
600 case MEM:
1b61190c 601 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
602 && GET_CODE (XEXP (x, 0)) != POST_INC)
eafc6604 603 x = adjust_address (x, SImode, 4);
1b61190c 604 print_operand_address (stream, XEXP (x, 0));
7208c779 605 break;
b7dbbdb2 606 default:
607 break;
7208c779 608 }
609 break;
1b61190c 610 case 'o':
611 switch (GET_CODE (x))
612 {
613 case PLUS: fputs ("add", stream); break;
614 case MINUS: fputs ("sub", stream); break;
615 case MULT: fputs ("mul", stream); break;
616 case DIV: fputs ("div", stream); break;
3c4bc54e 617 case EQ: fputs ("eq", stream); break;
618 case NE: fputs ("ne", stream); break;
619 case GT: case LT: fputs ("gt", stream); break;
620 case GE: case LE: fputs ("ge", stream); break;
621 case GTU: case LTU: fputs ("gtu", stream); break;
622 case GEU: case LEU: fputs ("geu", stream); break;
b7dbbdb2 623 default:
624 break;
1b61190c 625 }
626 break;
87e19636 627 case 'M':
628 if (GET_CODE (x) == MEM
629 && GET_CODE (XEXP (x, 0)) == PLUS
630 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
631 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
632 fputc ('x', stream);
633 break;
634
635 case 'm':
636 if (GET_CODE (x) != MEM)
637 abort ();
638 x = XEXP (x, 0);
639 switch (GET_CODE (x))
640 {
641 case REG:
642 case SUBREG:
643 print_operand (stream, x, 0);
644 fputs (", 0", stream);
645 break;
646
647 case PLUS:
648 print_operand (stream, XEXP (x, 0), 0);
649 fputs (", ", stream);
650 print_operand (stream, XEXP (x, 1), 0);
651 break;
652
653 default:
654 abort ();
655 }
656 break;
657
e3fac27d 658 case 'N':
d3b29bbd 659 if (x == CONST0_RTX (GET_MODE (x)))
e3fac27d 660 {
661 fprintf ((stream), "r63");
662 break;
663 }
664 goto default_output;
87e19636 665 case 'u':
666 if (GET_CODE (x) == CONST_INT)
3c4bc54e 667 {
87e19636 668 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
669 break;
670 }
671 /* Fall through. */
672
e3fac27d 673 default_output:
7208c779 674 default:
675 switch (GET_CODE (x))
676 {
87e19636 677 /* FIXME: We need this on SHmedia32 because reload generates
678 some sign-extended HI or QI loads into DImode registers
679 but, because Pmode is SImode, the address ends up with a
680 subreg:SI of the DImode register. Maybe reload should be
681 fixed so as to apply alter_subreg to such loads? */
682 case SUBREG:
683 if (SUBREG_BYTE (x) != 0
684 || GET_CODE (SUBREG_REG (x)) != REG)
685 abort ();
686
687 x = SUBREG_REG (x);
688 /* Fall through. */
689
7208c779 690 case REG:
e2142b04 691 if (FP_REGISTER_P (REGNO (x))
87e19636 692 && GET_MODE (x) == V16SFmode)
693 fprintf ((stream), "mtrx%s", reg_names[REGNO (x)] + 2);
694 else if (FP_REGISTER_P (REGNO (x))
695 && GET_MODE (x) == V4SFmode)
696 fprintf ((stream), "fv%s", reg_names[REGNO (x)] + 2);
697 else if (GET_CODE (x) == REG
698 && GET_MODE (x) == V2SFmode)
699 fprintf ((stream), "fp%s", reg_names[REGNO (x)] + 2);
700 else if (FP_REGISTER_P (REGNO (x))
701 && GET_MODE_SIZE (GET_MODE (x)) > 4)
702 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1b61190c 703 else
704 fputs (reg_names[REGNO (x)], (stream));
7208c779 705 break;
87e19636 706
7208c779 707 case MEM:
708 output_address (XEXP (x, 0));
709 break;
87e19636 710
711 case CONST:
712 if (TARGET_SHMEDIA
713 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
714 && GET_MODE (XEXP (x, 0)) == DImode
715 && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE
716 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)
717 {
718 rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0);
719
720 fputc ('(', stream);
721 if (GET_CODE (val) == ASHIFTRT)
722 {
723 fputc ('(', stream);
724 if (GET_CODE (XEXP (val, 0)) == CONST)
725 fputc ('(', stream);
726 output_addr_const (stream, XEXP (val, 0));
727 if (GET_CODE (XEXP (val, 0)) == CONST)
728 fputc (')', stream);
729 fputs (" >> ", stream);
730 output_addr_const (stream, XEXP (val, 1));
731 fputc (')', stream);
732 }
733 else
734 {
735 if (GET_CODE (val) == CONST)
736 fputc ('(', stream);
737 output_addr_const (stream, val);
738 if (GET_CODE (val) == CONST)
739 fputc (')', stream);
740 }
741 fputs (" & 65535)", stream);
742 break;
743 }
744
745 /* Fall through. */
7208c779 746 default:
87e19636 747 if (TARGET_SH1)
748 fputc ('#', stream);
7208c779 749 output_addr_const (stream, x);
750 break;
7208c779 751 }
752 break;
753 }
754}
7208c779 755\f
eb400f70 756/* Like force_operand, but guarantees that VALUE ends up in TARGET. */
757static void
04f04b72 758force_into (rtx value, rtx target)
eb400f70 759{
760 value = force_operand (value, target);
761 if (! rtx_equal_p (value, target))
762 emit_insn (gen_move_insn (target, value));
763}
764
97595bfd 765/* Emit code to perform a block move. Choose the best method.
766
767 OPERANDS[0] is the destination.
768 OPERANDS[1] is the source.
769 OPERANDS[2] is the size.
770 OPERANDS[3] is the alignment safe to use. */
771
97595bfd 772int
04f04b72 773expand_block_move (rtx *operands)
97595bfd 774{
775 int align = INTVAL (operands[3]);
776 int constp = (GET_CODE (operands[2]) == CONST_INT);
777 int bytes = (constp ? INTVAL (operands[2]) : 0);
97595bfd 778
73401833 779 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
780 alignment, or if it isn't a multiple of 4 bytes, then fail. */
781 if (! constp || align < 4 || (bytes % 4 != 0))
f3d93547 782 return 0;
783
1b61190c 784 if (TARGET_HARD_SH4)
785 {
786 if (bytes < 12)
787 return 0;
788 else if (bytes == 12)
789 {
790 tree entry_name;
649bfcd0 791 rtx sym;
1b61190c 792 rtx func_addr_rtx;
407d9153 793 rtx r4 = gen_rtx_REG (SImode, 4);
794 rtx r5 = gen_rtx_REG (SImode, 5);
1b61190c 795
008c057d 796 entry_name = get_identifier ("__movmemSI12_i4");
1b61190c 797
45271277 798 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
649bfcd0 799 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
eb400f70 800 force_into (XEXP (operands[0], 0), r4);
801 force_into (XEXP (operands[1], 0), r5);
1b61190c 802 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
803 return 1;
804 }
805 else if (! TARGET_SMALLCODE)
806 {
807 tree entry_name;
649bfcd0 808 rtx sym;
1b61190c 809 rtx func_addr_rtx;
810 int dwords;
407d9153 811 rtx r4 = gen_rtx_REG (SImode, 4);
812 rtx r5 = gen_rtx_REG (SImode, 5);
813 rtx r6 = gen_rtx_REG (SImode, 6);
1b61190c 814
815 entry_name = get_identifier (bytes & 4
008c057d 816 ? "__movmem_i4_odd"
817 : "__movmem_i4_even");
45271277 818 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
649bfcd0 819 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
eb400f70 820 force_into (XEXP (operands[0], 0), r4);
821 force_into (XEXP (operands[1], 0), r5);
1b61190c 822
823 dwords = bytes >> 3;
824 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
825 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
826 return 1;
827 }
828 else
829 return 0;
830 }
73401833 831 if (bytes < 64)
97595bfd 832 {
833 char entry[30];
834 tree entry_name;
649bfcd0 835 rtx sym;
97595bfd 836 rtx func_addr_rtx;
7014838c 837 rtx r4 = gen_rtx_REG (SImode, 4);
838 rtx r5 = gen_rtx_REG (SImode, 5);
73401833 839
008c057d 840 sprintf (entry, "__movmemSI%d", bytes);
97595bfd 841 entry_name = get_identifier (entry);
45271277 842 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
649bfcd0 843 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
eb400f70 844 force_into (XEXP (operands[0], 0), r4);
845 force_into (XEXP (operands[1], 0), r5);
97595bfd 846 emit_insn (gen_block_move_real (func_addr_rtx));
847 return 1;
848 }
73401833 849
850 /* This is the same number of bytes as a memcpy call, but to a different
851 less common function name, so this will occasionally use more space. */
852 if (! TARGET_SMALLCODE)
97595bfd 853 {
97595bfd 854 tree entry_name;
649bfcd0 855 rtx sym;
97595bfd 856 rtx func_addr_rtx;
73401833 857 int final_switch, while_loop;
7014838c 858 rtx r4 = gen_rtx_REG (SImode, 4);
859 rtx r5 = gen_rtx_REG (SImode, 5);
860 rtx r6 = gen_rtx_REG (SImode, 6);
97595bfd 861
008c057d 862 entry_name = get_identifier ("__movmem");
45271277 863 sym = function_symbol (IDENTIFIER_POINTER (entry_name));
649bfcd0 864 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
eb400f70 865 force_into (XEXP (operands[0], 0), r4);
866 force_into (XEXP (operands[1], 0), r5);
97595bfd 867
73401833 868 /* r6 controls the size of the move. 16 is decremented from it
869 for each 64 bytes moved. Then the negative bit left over is used
870 as an index into a list of move instructions. e.g., a 72 byte move
871 would be set up with size(r6) = 14, for one iteration through the
872 big while loop, and a switch of -2 for the last part. */
97595bfd 873
73401833 874 final_switch = 16 - ((bytes / 4) % 16);
875 while_loop = ((bytes / 4) / 16 - 1) * 16;
876 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
877 emit_insn (gen_block_lump_real (func_addr_rtx));
878 return 1;
97595bfd 879 }
97595bfd 880
f3d93547 881 return 0;
97595bfd 882}
883
7208c779 884/* Prepare operands for a move define_expand; specifically, one of the
73401833 885 operands must be in a register. */
7208c779 886
47c009e5 887int
04f04b72 888prepare_move_operands (rtx operands[], enum machine_mode mode)
7208c779 889{
cec78553 890 if ((mode == SImode || mode == DImode)
891 && flag_pic
892 && ! ((mode == Pmode || mode == ptr_mode)
893 && tls_symbolic_operand (operands[1], Pmode) != 0))
0abf894c 894 {
895 rtx temp;
896 if (SYMBOLIC_CONST_P (operands[1]))
897 {
898 if (GET_CODE (operands[0]) == MEM)
899 operands[1] = force_reg (Pmode, operands[1]);
afef6540 900 else if (TARGET_SHMEDIA
901 && GET_CODE (operands[1]) == LABEL_REF
87e19636 902 && target_reg_operand (operands[0], mode))
903 /* It's ok. */;
0abf894c 904 else
905 {
906 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
87e19636 907 operands[1] = legitimize_pic_address (operands[1], mode, temp);
0abf894c 908 }
909 }
910 else if (GET_CODE (operands[1]) == CONST
911 && GET_CODE (XEXP (operands[1], 0)) == PLUS
912 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
913 {
6883f2aa 914 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
0abf894c 915 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
87e19636 916 mode, temp);
917 operands[1] = expand_binop (mode, add_optab, temp,
0abf894c 918 XEXP (XEXP (operands[1], 0), 1),
6883f2aa 919 no_new_pseudos ? temp
920 : gen_reg_rtx (Pmode),
921 0, OPTAB_LIB_WIDEN);
0abf894c 922 }
923 }
924
5beb0a57 925 if (! reload_in_progress && ! reload_completed)
926 {
927 /* Copy the source to a register if both operands aren't registers. */
928 if (! register_operand (operands[0], mode)
0edea8ba 929 && ! sh_register_operand (operands[1], mode))
5beb0a57 930 operands[1] = copy_to_mode_reg (mode, operands[1]);
931
7bc2d3b3 932 if (GET_CODE (operands[0]) == MEM && ! memory_operand (operands[0], mode))
933 {
934 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
935 except that we can't use that function because it is static. */
936 rtx new = change_address (operands[0], mode, 0);
937 MEM_COPY_ATTRIBUTES (new, operands[0]);
938 operands[0] = new;
939 }
940
5beb0a57 941 /* This case can happen while generating code to move the result
942 of a library call to the target. Reject `st r0,@(rX,rY)' because
943 reload will fail to find a spill register for rX, since r0 is already
944 being used for the source. */
7bc2d3b3 945 else if (refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
5beb0a57 946 && GET_CODE (operands[0]) == MEM
947 && GET_CODE (XEXP (operands[0], 0)) == PLUS
948 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
949 operands[1] = copy_to_mode_reg (mode, operands[1]);
950 }
73401833 951
cec78553 952 if (mode == Pmode || mode == ptr_mode)
953 {
954 rtx op0, op1;
955 enum tls_model tls_kind;
956
957 op0 = operands[0];
958 op1 = operands[1];
959 if ((tls_kind = tls_symbolic_operand (op1, Pmode)))
960 {
961 rtx tga_op1, tga_ret, tmp, tmp2;
962
963
964 switch (tls_kind)
965 {
966 case TLS_MODEL_GLOBAL_DYNAMIC:
967 tga_ret = gen_rtx_REG (Pmode, R0_REG);
8cdd3257 968 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
cec78553 969 op1 = tga_ret;
970 break;
971
972 case TLS_MODEL_LOCAL_DYNAMIC:
973 tga_ret = gen_rtx_REG (Pmode, R0_REG);
8cdd3257 974 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
cec78553 975
976 tmp = gen_reg_rtx (Pmode);
977 emit_move_insn (tmp, tga_ret);
978
979 if (register_operand (op0, Pmode))
980 tmp2 = op0;
981 else
982 tmp2 = gen_reg_rtx (Pmode);
983
984 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
985 op1 = tmp2;
986 break;
987
988 case TLS_MODEL_INITIAL_EXEC:
989 if (! flag_pic)
990 emit_insn (gen_GOTaddr2picreg ());
991 tga_op1 = gen_reg_rtx (Pmode);
992 tmp = gen_sym2GOTTPOFF (op1);
993 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
994 op1 = tga_op1;
995 break;
996
997 case TLS_MODEL_LOCAL_EXEC:
998 tmp2 = gen_reg_rtx (Pmode);
999 emit_insn (gen_load_gbr (tmp2));
1000 tmp = gen_reg_rtx (Pmode);
1001 emit_insn (gen_symTPOFF2reg (tmp, op1));
1002 RTX_UNCHANGING_P (tmp) = 1;
1003
1004 if (register_operand (op0, Pmode))
1005 op1 = op0;
1006 else
1007 op1 = gen_reg_rtx (Pmode);
1008
1009 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1010 break;
1011
1012 default:
1013 abort ();
1014 }
1015 operands[1] = op1;
1016 }
1017 }
1018
73401833 1019 return 0;
1020}
1021
1022/* Prepare the operands for an scc instruction; make sure that the
1023 compare has been done. */
1024rtx
04f04b72 1025prepare_scc_operands (enum rtx_code code)
73401833 1026{
7014838c 1027 rtx t_reg = gen_rtx_REG (SImode, T_REG);
73401833 1028 enum rtx_code oldcode = code;
e9646547 1029 enum machine_mode mode;
73401833 1030
1031 /* First need a compare insn. */
1032 switch (code)
7208c779 1033 {
73401833 1034 case NE:
1035 /* It isn't possible to handle this case. */
1036 abort ();
1037 case LT:
1038 code = GT;
1039 break;
1040 case LE:
1041 code = GE;
1042 break;
1043 case LTU:
1044 code = GTU;
1045 break;
1046 case LEU:
1047 code = GEU;
1048 break;
7984f145 1049 default:
1050 break;
7208c779 1051 }
73401833 1052 if (code != oldcode)
47c009e5 1053 {
73401833 1054 rtx tmp = sh_compare_op0;
1055 sh_compare_op0 = sh_compare_op1;
1056 sh_compare_op1 = tmp;
97595bfd 1057 }
47c009e5 1058
e9646547 1059 mode = GET_MODE (sh_compare_op0);
1060 if (mode == VOIDmode)
1061 mode = GET_MODE (sh_compare_op1);
1062
1063 sh_compare_op0 = force_reg (mode, sh_compare_op0);
8ded0752 1064 if ((code != EQ && code != NE
1065 && (sh_compare_op1 != const0_rtx
1066 || code == GTU || code == GEU || code == LTU || code == LEU))
e5d518fa 1067 || (mode == DImode && sh_compare_op1 != const0_rtx)
87ed74ef 1068 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
e9646547 1069 sh_compare_op1 = force_reg (mode, sh_compare_op1);
97595bfd 1070
1b61190c 1071 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
1072 (mode == SFmode ? emit_sf_insn : emit_df_insn)
407d9153 1073 (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
1074 gen_rtx_SET (VOIDmode, t_reg,
dc55b8a9 1075 gen_rtx_fmt_ee (code, SImode,
1076 sh_compare_op0, sh_compare_op1)),
407d9153 1077 gen_rtx_USE (VOIDmode, get_fpscr_rtx ()))));
1b61190c 1078 else
407d9153 1079 emit_insn (gen_rtx_SET (VOIDmode, t_reg,
dc55b8a9 1080 gen_rtx_fmt_ee (code, SImode,
1081 sh_compare_op0, sh_compare_op1)));
97595bfd 1082
73401833 1083 return t_reg;
7208c779 1084}
1085
73401833 1086/* Called from the md file, set up the operands of a compare instruction. */
1087
1088void
04f04b72 1089from_compare (rtx *operands, int code)
7208c779 1090{
8ded0752 1091 enum machine_mode mode = GET_MODE (sh_compare_op0);
1092 rtx insn;
1093 if (mode == VOIDmode)
1094 mode = GET_MODE (sh_compare_op1);
1095 if (code != EQ
1096 || mode == DImode
87ed74ef 1097 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
7208c779 1098 {
73401833 1099 /* Force args into regs, since we can't use constants here. */
65bc3ae6 1100 sh_compare_op0 = force_reg (mode, sh_compare_op0);
73401833 1101 if (sh_compare_op1 != const0_rtx
8ded0752 1102 || code == GTU || code == GEU
87ed74ef 1103 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
65bc3ae6 1104 sh_compare_op1 = force_reg (mode, sh_compare_op1);
7208c779 1105 }
87ed74ef 1106 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
8ded0752 1107 {
1108 from_compare (operands, GT);
1109 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
1110 }
1111 else
7014838c 1112 insn = gen_rtx_SET (VOIDmode,
a5bd34f1 1113 gen_rtx_REG (SImode, T_REG),
dc55b8a9 1114 gen_rtx_fmt_ee (code, SImode,
1115 sh_compare_op0, sh_compare_op1));
1b61190c 1116 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
1117 {
407d9153 1118 insn = gen_rtx_PARALLEL (VOIDmode,
1b61190c 1119 gen_rtvec (2, insn,
407d9153 1120 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
1b61190c 1121 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1122 }
1123 else
1124 emit_insn (insn);
7208c779 1125}
1126\f
1504eb7e 1127/* Functions to output assembly code. */
7208c779 1128
47c009e5 1129/* Return a sequence of instructions to perform DI or DF move.
7208c779 1130
47c009e5 1131 Since the SH cannot move a DI or DF in one instruction, we have
1504eb7e 1132 to take care when we see overlapping source and dest registers. */
97595bfd 1133
b7dbbdb2 1134const char *
04f04b72 1135output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1136 enum machine_mode mode)
7208c779 1137{
47c009e5 1138 rtx dst = operands[0];
1139 rtx src = operands[1];
47c009e5 1140
97595bfd 1141 if (GET_CODE (dst) == MEM
1504eb7e 1142 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
73401833 1143 return "mov.l %T1,%0\n\tmov.l %1,%0";
1144
47c009e5 1145 if (register_operand (dst, mode)
1146 && register_operand (src, mode))
7208c779 1147 {
47c009e5 1148 if (REGNO (src) == MACH_REG)
3dfc1807 1149 return "sts mach,%S0\n\tsts macl,%R0";
7208c779 1150
73401833 1151 /* When mov.d r1,r2 do r2->r3 then r1->r2;
1152 when mov.d r1,r0 do r1->r0 then r2->r1. */
47c009e5 1153
1154 if (REGNO (src) + 1 == REGNO (dst))
335e16a0 1155 return "mov %T1,%T0\n\tmov %1,%0";
47c009e5 1156 else
335e16a0 1157 return "mov %1,%0\n\tmov %T1,%T0";
47c009e5 1158 }
1159 else if (GET_CODE (src) == CONST_INT)
7208c779 1160 {
73401833 1161 if (INTVAL (src) < 0)
1162 output_asm_insn ("mov #-1,%S0", operands);
7208c779 1163 else
73401833 1164 output_asm_insn ("mov #0,%S0", operands);
7208c779 1165
73401833 1166 return "mov %1,%R0";
97595bfd 1167 }
47c009e5 1168 else if (GET_CODE (src) == MEM)
7208c779 1169 {
73401833 1170 int ptrreg = -1;
47c009e5 1171 int dreg = REGNO (dst);
1172 rtx inside = XEXP (src, 0);
7208c779 1173
1174 if (GET_CODE (inside) == REG)
73401833 1175 ptrreg = REGNO (inside);
3f2613e4 1176 else if (GET_CODE (inside) == SUBREG)
701e46d0 1177 ptrreg = subreg_regno (inside);
7208c779 1178 else if (GET_CODE (inside) == PLUS)
1179 {
73401833 1180 ptrreg = REGNO (XEXP (inside, 0));
1181 /* ??? A r0+REG address shouldn't be possible here, because it isn't
1182 an offsettable address. Unfortunately, offsettable addresses use
1183 QImode to check the offset, and a QImode offsettable address
1184 requires r0 for the other operand, which is not currently
1185 supported, so we can't use the 'o' constraint.
1186 Thus we must check for and handle r0+REG addresses here.
1187 We punt for now, since this is likely very rare. */
1188 if (GET_CODE (XEXP (inside, 1)) == REG)
1189 abort ();
7208c779 1190 }
97595bfd 1191 else if (GET_CODE (inside) == LABEL_REF)
73401833 1192 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2e3d4844 1193 else if (GET_CODE (inside) == POST_INC)
73401833 1194 return "mov.l %1,%0\n\tmov.l %1,%T0";
7208c779 1195 else
1196 abort ();
1197
73401833 1198 /* Work out the safe way to copy. Copy into the second half first. */
1199 if (dreg == ptrreg)
1200 return "mov.l %T1,%T0\n\tmov.l %1,%0";
7208c779 1201 }
1202
3dfc1807 1203 return "mov.l %1,%0\n\tmov.l %T1,%T0";
7208c779 1204}
1205
73401833 1206/* Print an instruction which would have gone into a delay slot after
1207 another instruction, but couldn't because the other instruction expanded
1208 into a sequence where putting the slot insn at the end wouldn't work. */
97595bfd 1209
73401833 1210static void
04f04b72 1211print_slot (rtx insn)
73401833 1212{
fbf5169c 1213 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1, NULL);
47c009e5 1214
73401833 1215 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
1216}
97595bfd 1217
b7dbbdb2 1218const char *
04f04b72 1219output_far_jump (rtx insn, rtx op)
97595bfd 1220{
8ded0752 1221 struct { rtx lab, reg, op; } this;
e51fa923 1222 rtx braf_base_lab = NULL_RTX;
b7dbbdb2 1223 const char *jump;
8ded0752 1224 int far;
47fc0706 1225 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2a6493a5 1226 rtx prev;
97595bfd 1227
8ded0752 1228 this.lab = gen_label_rtx ();
47c009e5 1229
15494e01 1230 if (TARGET_SH2
1231 && offset >= -32764
1232 && offset - get_attr_length (insn) <= 32766)
8ded0752 1233 {
1234 far = 0;
d1665c4c 1235 jump = "mov.w %O0,%1; braf %1";
8ded0752 1236 }
1237 else
1238 {
1239 far = 1;
0abf894c 1240 if (flag_pic)
d1665c4c 1241 {
1242 if (TARGET_SH2)
1243 jump = "mov.l %O0,%1; braf %1";
1244 else
1245 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1246 }
0abf894c 1247 else
d1665c4c 1248 jump = "mov.l %O0,%1; jmp @%1";
8ded0752 1249 }
1250 /* If we have a scratch register available, use it. */
2a6493a5 1251 if (GET_CODE ((prev = prev_nonnote_insn (insn))) == INSN
1252 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
8ded0752 1253 {
2a6493a5 1254 this.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
d1665c4c 1255 if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2)
1256 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
8ded0752 1257 output_asm_insn (jump, &this.lab);
1258 if (dbr_sequence_length ())
1259 print_slot (final_sequence);
1260 else
1261 output_asm_insn ("nop", 0);
1262 }
1263 else
1264 {
1265 /* Output the delay slot insn first if any. */
1266 if (dbr_sequence_length ())
1267 print_slot (final_sequence);
1268
7014838c 1269 this.reg = gen_rtx_REG (SImode, 13);
87e19636 1270 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1271 Fortunately, MACL is fixed and call-clobbered, and we never
1272 need its value across jumps, so save r13 in it instead of in
1273 the stack. */
1274 if (TARGET_SH5)
1275 output_asm_insn ("lds r13, macl", 0);
1276 else
1277 output_asm_insn ("mov.l r13,@-r15", 0);
8ded0752 1278 output_asm_insn (jump, &this.lab);
87e19636 1279 if (TARGET_SH5)
1280 output_asm_insn ("sts macl, r13", 0);
1281 else
1282 output_asm_insn ("mov.l @r15+,r13", 0);
8ded0752 1283 }
d1665c4c 1284 if (far && flag_pic && TARGET_SH2)
1285 {
1286 braf_base_lab = gen_label_rtx ();
805e22b2 1287 (*targetm.asm_out.internal_label) (asm_out_file, "L",
d1665c4c 1288 CODE_LABEL_NUMBER (braf_base_lab));
1289 }
8ded0752 1290 if (far)
1291 output_asm_insn (".align 2", 0);
805e22b2 1292 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
8ded0752 1293 this.op = op;
0abf894c 1294 if (far && flag_pic)
d1665c4c 1295 {
1296 if (TARGET_SH2)
1297 this.lab = braf_base_lab;
1298 output_asm_insn (".long %O2-%O0", &this.lab);
1299 }
0abf894c 1300 else
1301 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
97595bfd 1302 return "";
1303}
7208c779 1304
73401833 1305/* Local label counter, used for constants in the pool and inside
1306 pattern branches. */
1307
1308static int lf = 100;
1309
1310/* Output code for ordinary branches. */
1311
b7dbbdb2 1312const char *
04f04b72 1313output_branch (int logic, rtx insn, rtx *operands)
7208c779 1314{
fb2fe7e1 1315 switch (get_attr_length (insn))
7208c779 1316 {
9eaab178 1317 case 6:
1318 /* This can happen if filling the delay slot has caused a forward
1319 branch to exceed its range (we could reverse it, but only
1320 when we know we won't overextend other branches; this should
1321 best be handled by relaxation).
1322 It can also happen when other condbranches hoist delay slot insn
8ded0752 1323 from their destination, thus leading to code size increase.
1324 But the branch will still be in the range -4092..+4098 bytes. */
7208c779 1325
9eaab178 1326 if (! TARGET_RELAX)
8ded0752 1327 {
9eaab178 1328 int label = lf++;
1329 /* The call to print_slot will clobber the operands. */
1330 rtx op0 = operands[0];
1331
1332 /* If the instruction in the delay slot is annulled (true), then
1333 there is no delay slot where we can put it now. The only safe
1334 place for it is after the label. final will do that by default. */
1335
1336 if (final_sequence
1337 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1338 {
fb2fe7e1 1339 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
9eaab178 1340 ASSEMBLER_DIALECT ? "/" : ".", label);
1341 print_slot (final_sequence);
1342 }
1343 else
fb2fe7e1 1344 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
9eaab178 1345
fb2fe7e1 1346 output_asm_insn ("bra\t%l0", &op0);
1347 fprintf (asm_out_file, "\tnop\n");
d767e27e 1348 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
9eaab178 1349
1350 return "";
8ded0752 1351 }
9eaab178 1352 /* When relaxing, handle this like a short branch. The linker
1353 will fix it up if it still doesn't fit after relaxation. */
1354 case 2:
1355 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
87ed74ef 1356
1357 /* These are for SH2e, in which we have to account for the
1358 extra nop because of the hardware bug in annulled branches. */
1359 case 8:
1360 if (! TARGET_RELAX)
1361 {
1362 int label = lf++;
1363
1364 if (final_sequence
1365 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1366 abort ();
1367 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
1368 logic ? "f" : "t",
1369 ASSEMBLER_DIALECT ? "/" : ".", label);
1370 fprintf (asm_out_file, "\tnop\n");
1371 output_asm_insn ("bra\t%l0", operands);
1372 fprintf (asm_out_file, "\tnop\n");
1373 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
1374
1375 return "";
1376 }
1377 /* When relaxing, fall through. */
1378 case 4:
1379 {
1380 char buffer[10];
1381
1382 sprintf (buffer, "b%s%ss\t%%l0",
1383 logic ? "t" : "f",
1384 ASSEMBLER_DIALECT ? "/" : ".");
1385 output_asm_insn (buffer, &operands[0]);
1386 return "nop";
1387 }
1388
9eaab178 1389 default:
fb2fe7e1 1390 /* There should be no longer branches now - that would
1391 indicate that something has destroyed the branches set
1392 up in machine_dependent_reorg. */
9eaab178 1393 abort ();
8ded0752 1394 }
8ded0752 1395}
7208c779 1396
b7dbbdb2 1397const char *
04f04b72 1398output_branchy_insn (enum rtx_code code, const char *template,
1399 rtx insn, rtx *operands)
8ded0752 1400{
1401 rtx next_insn = NEXT_INSN (insn);
3f2613e4 1402
8ded0752 1403 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
1404 {
1405 rtx src = SET_SRC (PATTERN (next_insn));
1406 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
1407 {
1408 /* Following branch not taken */
1409 operands[9] = gen_label_rtx ();
1410 emit_label_after (operands[9], next_insn);
47fc0706 1411 INSN_ADDRESSES_NEW (operands[9],
1412 INSN_ADDRESSES (INSN_UID (next_insn))
1413 + get_attr_length (next_insn));
8ded0752 1414 return template;
1415 }
1416 else
1417 {
9eaab178 1418 int offset = (branch_dest (next_insn)
47fc0706 1419 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
9eaab178 1420 if (offset >= -252 && offset <= 258)
8ded0752 1421 {
1422 if (GET_CODE (src) == IF_THEN_ELSE)
1423 /* branch_true */
1424 src = XEXP (src, 1);
1425 operands[9] = src;
1426 return template;
1427 }
1428 }
7208c779 1429 }
8ded0752 1430 operands[9] = gen_label_rtx ();
1431 emit_label_after (operands[9], insn);
47fc0706 1432 INSN_ADDRESSES_NEW (operands[9],
1433 INSN_ADDRESSES (INSN_UID (insn))
1434 + get_attr_length (insn));
8ded0752 1435 return template;
1436}
e6c94d0d 1437
b7dbbdb2 1438const char *
04f04b72 1439output_ieee_ccmpeq (rtx insn, rtx *operands)
8ded0752 1440{
b7dbbdb2 1441 return output_branchy_insn (NE, "bt\t%l9\\;fcmp/eq\t%1,%0", insn, operands);
7208c779 1442}
2e3d4844 1443\f
92c473b8 1444/* Output the start of the assembler file. */
73401833 1445
92c473b8 1446static void
04f04b72 1447sh_file_start (void)
7208c779 1448{
92c473b8 1449 default_file_start ();
1450
db281f5a 1451#ifdef SYMBIAN
1452 /* Declare the .directive section before it is used. */
1453 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
1454 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
1455#endif
1456
92c473b8 1457 if (TARGET_ELF)
1458 /* We need to show the text section with the proper
1459 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
9fd95d94 1460 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
92c473b8 1461 will complain. We can teach GAS specifically about the
1462 default attributes for our choice of text section, but
1463 then we would have to change GAS again if/when we change
1464 the text section name. */
1465 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
1466 else
1467 /* Switch to the data section so that the coffsem symbol
1468 isn't in the text section. */
1469 data_section ();
47c009e5 1470
73401833 1471 if (TARGET_LITTLE_ENDIAN)
92c473b8 1472 fputs ("\t.little\n", asm_out_file);
87e19636 1473
92c473b8 1474 if (!TARGET_ELF)
1475 {
1476 if (TARGET_SHCOMPACT)
1477 fputs ("\t.mode\tSHcompact\n", asm_out_file);
1478 else if (TARGET_SHMEDIA)
1479 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1480 TARGET_SHMEDIA64 ? 64 : 32);
1481 }
7208c779 1482}
97595bfd 1483\f
02359f85 1484/* Check if PAT includes UNSPEC_CALLER unspec pattern. */
1485
1486static bool
04f04b72 1487unspec_caller_rtx_p (rtx pat)
02359f85 1488{
1489 switch (GET_CODE (pat))
1490 {
1491 case CONST:
1492 return unspec_caller_rtx_p (XEXP (pat, 0));
1493 case PLUS:
1494 case MINUS:
1495 if (unspec_caller_rtx_p (XEXP (pat, 0)))
1496 return true;
1497 return unspec_caller_rtx_p (XEXP (pat, 1));
1498 case UNSPEC:
1499 if (XINT (pat, 1) == UNSPEC_CALLER)
1500 return true;
1501 default:
1502 break;
1503 }
1504
1505 return false;
1506}
1507
1508/* Indicate that INSN cannot be duplicated. This is true for insn
1509 that generates an unique label. */
1510
1511static bool
04f04b72 1512sh_cannot_copy_insn_p (rtx insn)
02359f85 1513{
1514 rtx pat;
1515
1516 if (!reload_completed || !flag_pic)
1517 return false;
1518
1519 if (GET_CODE (insn) != INSN)
1520 return false;
1521 if (asm_noperands (insn) >= 0)
1522 return false;
1523
1524 pat = PATTERN (insn);
1525 if (GET_CODE (pat) != SET)
1526 return false;
1527 pat = SET_SRC (pat);
1528
1529 if (unspec_caller_rtx_p (pat))
1530 return true;
1531
1532 return false;
1533}
1534\f
1504eb7e 1535/* Actual number of instructions used to make a shift by N. */
e7c691ac 1536static const char ashiftrt_insns[] =
1504eb7e 1537 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1538
1539/* Left shift and logical right shift are the same. */
e7c691ac 1540static const char shift_insns[] =
1504eb7e 1541 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
73401833 1542
1504eb7e 1543/* Individual shift amounts needed to get the above length sequences.
1544 One bit right shifts clobber the T bit, so when possible, put one bit
1545 shifts in the middle of the sequence, so the ends are eligible for
1546 branch delay slots. */
c8834c5f 1547static const short shift_amounts[32][5] = {
1504eb7e 1548 {0}, {1}, {2}, {2, 1},
1549 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1550 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1551 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1552 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1553 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1554 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
ad7aadac 1555 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1504eb7e 1556
2ce8df5a 1557/* Likewise, but for shift amounts < 16, up to three highmost bits
1558 might be clobbered. This is typically used when combined with some
1559 kind of sign or zero extension. */
1560
e7c691ac 1561static const char ext_shift_insns[] =
2ce8df5a 1562 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1563
e7c691ac 1564static const short ext_shift_amounts[32][4] = {
2ce8df5a 1565 {0}, {1}, {2}, {2, 1},
1566 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1567 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1568 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1569 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1570 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1571 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1572 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1573
69b02875 1574/* Assuming we have a value that has been sign-extended by at least one bit,
1575 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1576 to shift it by N without data loss, and quicker than by other means? */
1577#define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1578
1504eb7e 1579/* This is used in length attributes in sh.md to help compute the length
1580 of arbitrary constant shift instructions. */
7208c779 1581
1504eb7e 1582int
04f04b72 1583shift_insns_rtx (rtx insn)
1504eb7e 1584{
1585 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1586 int shift_count = INTVAL (XEXP (set_src, 1));
1587 enum rtx_code shift_code = GET_CODE (set_src);
3dfc1807 1588
1504eb7e 1589 switch (shift_code)
1590 {
1591 case ASHIFTRT:
1592 return ashiftrt_insns[shift_count];
1593 case LSHIFTRT:
1594 case ASHIFT:
1595 return shift_insns[shift_count];
1596 default:
d767e27e 1597 abort ();
1504eb7e 1598 }
1599}
1600
1504eb7e 1601/* Return the cost of a shift. */
7208c779 1602
fab7adbf 1603static inline int
04f04b72 1604shiftcosts (rtx x)
7208c779 1605{
d6fe3e0d 1606 int value;
73401833 1607
87e19636 1608 if (TARGET_SHMEDIA)
1609 return 1;
1610
41f4d177 1611 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
1612 {
1613 if (GET_MODE (x) == DImode
1614 && GET_CODE (XEXP (x, 1)) == CONST_INT
1615 && INTVAL (XEXP (x, 1)) == 1)
1616 return 2;
1617
1618 /* Everything else is invalid, because there is no pattern for it. */
1619 return 10000;
1620 }
1504eb7e 1621 /* If shift by a non constant, then this will be expensive. */
73401833 1622 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
8ded0752 1623 return SH_DYNAMIC_SHIFT_COST;
7208c779 1624
d6fe3e0d 1625 value = INTVAL (XEXP (x, 1));
1626
1504eb7e 1627 /* Otherwise, return the true cost in instructions. */
73401833 1628 if (GET_CODE (x) == ASHIFTRT)
79f0f2fe 1629 {
1630 int cost = ashiftrt_insns[value];
1631 /* If SH3, then we put the constant in a reg and use shad. */
8ded0752 1632 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
1633 cost = 1 + SH_DYNAMIC_SHIFT_COST;
79f0f2fe 1634 return cost;
1635 }
73401833 1636 else
1637 return shift_insns[value];
97595bfd 1638}
47c009e5 1639
73401833 1640/* Return the cost of an AND operation. */
1641
fab7adbf 1642static inline int
04f04b72 1643andcosts (rtx x)
97595bfd 1644{
1645 int i;
73401833 1646
f22b6811 1647 /* Anding with a register is a single cycle and instruction. */
73401833 1648 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
f22b6811 1649 return 1;
73401833 1650
1651 i = INTVAL (XEXP (x, 1));
87e19636 1652
1653 if (TARGET_SHMEDIA)
1654 {
1655 if ((GET_CODE (XEXP (x, 1)) == CONST_INT
af2c1324 1656 && CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
1657 || EXTRA_CONSTRAINT_C16 (XEXP (x, 1)))
87e19636 1658 return 1;
1659 else
1660 return 2;
1661 }
1662
f22b6811 1663 /* These constants are single cycle extu.[bw] instructions. */
97595bfd 1664 if (i == 0xff || i == 0xffff)
f22b6811 1665 return 1;
af2c1324 1666 /* Constants that can be used in an and immediate instruction in a single
f22b6811 1667 cycle, but this requires r0, so make it a little more expensive. */
af2c1324 1668 if (CONST_OK_FOR_K08 (i))
97595bfd 1669 return 2;
f22b6811 1670 /* Constants that can be loaded with a mov immediate and an and.
1671 This case is probably unnecessary. */
af2c1324 1672 if (CONST_OK_FOR_I08 (i))
f22b6811 1673 return 2;
1674 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1675 This case is probably unnecessary. */
1676 return 3;
97595bfd 1677}
f3d93547 1678
d27eb4b1 1679/* Return the cost of an addition or a subtraction. */
1680
fab7adbf 1681static inline int
04f04b72 1682addsubcosts (rtx x)
d27eb4b1 1683{
1684 /* Adding a register is a single cycle insn. */
0d93aeb0 1685 if (GET_CODE (XEXP (x, 1)) == REG
1686 || GET_CODE (XEXP (x, 1)) == SUBREG)
d27eb4b1 1687 return 1;
1688
1689 /* Likewise for small constants. */
d6fe3e0d 1690 if (GET_CODE (XEXP (x, 1)) == CONST_INT
87e19636 1691 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
d27eb4b1 1692 return 1;
1693
87e19636 1694 if (TARGET_SHMEDIA)
1695 switch (GET_CODE (XEXP (x, 1)))
1696 {
1697 case CONST:
1698 case LABEL_REF:
1699 case SYMBOL_REF:
1700 return TARGET_SHMEDIA64 ? 5 : 3;
1701
1702 case CONST_INT:
af2c1324 1703 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
87e19636 1704 return 2;
af2c1324 1705 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
87e19636 1706 return 3;
af2c1324 1707 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
87e19636 1708 return 4;
1709
1710 /* Fall through. */
1711 default:
d767e27e 1712 return 5;
87e19636 1713 }
1714
d27eb4b1 1715 /* Any other constant requires a 2 cycle pc-relative load plus an
1716 addition. */
1717 return 3;
1718}
1719
1504eb7e 1720/* Return the cost of a multiply. */
fab7adbf 1721static inline int
04f04b72 1722multcosts (rtx x ATTRIBUTE_UNUSED)
97595bfd 1723{
87e19636 1724 if (TARGET_SHMEDIA)
1725 return 3;
1726
97595bfd 1727 if (TARGET_SH2)
f3d93547 1728 {
1729 /* We have a mul insn, so we can never take more than the mul and the
8cd86814 1730 read of the mac reg, but count more because of the latency and extra
1504eb7e 1731 reg usage. */
f3d93547 1732 if (TARGET_SMALLCODE)
2e3d4844 1733 return 2;
8cd86814 1734 return 3;
f3d93547 1735 }
1736
8cd86814 1737 /* If we're aiming at small code, then just count the number of
1504eb7e 1738 insns in a multiply call sequence. */
2e3d4844 1739 if (TARGET_SMALLCODE)
73401833 1740 return 5;
f3d93547 1741
1504eb7e 1742 /* Otherwise count all the insns in the routine we'd be calling too. */
f3d93547 1743 return 20;
97595bfd 1744}
47c009e5 1745
fab7adbf 1746/* Compute a (partial) cost for rtx X. Return true if the complete
1747 cost has been computed, and false if subexpressions should be
1748 scanned. In either case, *TOTAL contains the cost result. */
1749
1750static bool
04f04b72 1751sh_rtx_costs (rtx x, int code, int outer_code, int *total)
fab7adbf 1752{
1753 switch (code)
1754 {
1755 case CONST_INT:
1756 if (TARGET_SHMEDIA)
1757 {
1758 if (INTVAL (x) == 0)
1759 *total = 0;
1760 else if (outer_code == AND && and_operand ((x), DImode))
1761 *total = 0;
1762 else if ((outer_code == IOR || outer_code == XOR
1763 || outer_code == PLUS)
af2c1324 1764 && CONST_OK_FOR_I10 (INTVAL (x)))
fab7adbf 1765 *total = 0;
af2c1324 1766 else if (CONST_OK_FOR_I16 (INTVAL (x)))
fab7adbf 1767 *total = COSTS_N_INSNS (outer_code != SET);
af2c1324 1768 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
fab7adbf 1769 *total = COSTS_N_INSNS (2);
af2c1324 1770 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
fab7adbf 1771 *total = COSTS_N_INSNS (3);
1772 else
1773 *total = COSTS_N_INSNS (4);
1774 return true;
1775 }
af2c1324 1776 if (CONST_OK_FOR_I08 (INTVAL (x)))
fab7adbf 1777 *total = 0;
1778 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
af2c1324 1779 && CONST_OK_FOR_K08 (INTVAL (x)))
fab7adbf 1780 *total = 1;
1781 else
1782 *total = 8;
1783 return true;
1784
1785 case CONST:
1786 case LABEL_REF:
1787 case SYMBOL_REF:
1788 if (TARGET_SHMEDIA64)
1789 *total = COSTS_N_INSNS (4);
1790 else if (TARGET_SHMEDIA32)
1791 *total = COSTS_N_INSNS (2);
1792 else
1793 *total = 5;
1794 return true;
1795
1796 case CONST_DOUBLE:
1797 if (TARGET_SHMEDIA)
1798 *total = COSTS_N_INSNS (4);
1799 else
1800 *total = 10;
1801 return true;
1802
1803 case PLUS:
1804 *total = COSTS_N_INSNS (addsubcosts (x));
1805 return true;
1806
1807 case AND:
1808 *total = COSTS_N_INSNS (andcosts (x));
1809 return true;
1810
1811 case MULT:
1812 *total = COSTS_N_INSNS (multcosts (x));
1813 return true;
1814
1815 case ASHIFT:
1816 case ASHIFTRT:
1817 case LSHIFTRT:
1818 *total = COSTS_N_INSNS (shiftcosts (x));
1819 return true;
1820
1821 case DIV:
1822 case UDIV:
1823 case MOD:
1824 case UMOD:
1825 *total = COSTS_N_INSNS (20);
1826 return true;
1827
1828 case FLOAT:
1829 case FIX:
1830 *total = 100;
1831 return true;
1832
1833 default:
1834 return false;
1835 }
1836}
1837
ec0457a8 1838/* Compute the cost of an address. For the SH, all valid addresses are
1839 the same cost. Use a slightly higher cost for reg + reg addressing,
1840 since it increases pressure on r0. */
1841
1842static int
04f04b72 1843sh_address_cost (rtx X)
ec0457a8 1844{
1845 return (GET_CODE (X) == PLUS
1846 && ! CONSTANT_P (XEXP (X, 1))
1847 && ! TARGET_SHMEDIA ? 1 : 0);
1848}
fab7adbf 1849
1504eb7e 1850/* Code to expand a shift. */
47c009e5 1851
97595bfd 1852void
04f04b72 1853gen_ashift (int type, int n, rtx reg)
97595bfd 1854{
1504eb7e 1855 /* Negative values here come from the shift_amounts array. */
1856 if (n < 0)
1857 {
1858 if (type == ASHIFT)
1859 type = LSHIFTRT;
1860 else
1861 type = ASHIFT;
1862 n = -n;
1863 }
1864
97595bfd 1865 switch (type)
7208c779 1866 {
97595bfd 1867 case ASHIFTRT:
1868 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
1869 break;
1870 case LSHIFTRT:
1504eb7e 1871 if (n == 1)
1872 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
1873 else
1874 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
97595bfd 1875 break;
1876 case ASHIFT:
184d8105 1877 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
97595bfd 1878 break;
7208c779 1879 }
7208c779 1880}
7208c779 1881
2ce8df5a 1882/* Same for HImode */
1883
1884void
04f04b72 1885gen_ashift_hi (int type, int n, rtx reg)
2ce8df5a 1886{
1887 /* Negative values here come from the shift_amounts array. */
1888 if (n < 0)
1889 {
1890 if (type == ASHIFT)
1891 type = LSHIFTRT;
1892 else
1893 type = ASHIFT;
1894 n = -n;
1895 }
1896
1897 switch (type)
1898 {
1899 case ASHIFTRT:
2ce8df5a 1900 case LSHIFTRT:
4b9cbc29 1901 /* We don't have HImode right shift operations because using the
1902 ordinary 32 bit shift instructions for that doesn't generate proper
1903 zero/sign extension.
1904 gen_ashift_hi is only called in contexts where we know that the
1905 sign extension works out correctly. */
7d175685 1906 {
701e46d0 1907 int offset = 0;
7d175685 1908 if (GET_CODE (reg) == SUBREG)
1909 {
701e46d0 1910 offset = SUBREG_BYTE (reg);
7d175685 1911 reg = SUBREG_REG (reg);
1912 }
701e46d0 1913 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
7d175685 1914 break;
1915 }
2ce8df5a 1916 case ASHIFT:
1917 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
1918 break;
1919 }
1920}
1921
73401833 1922/* Output RTL to split a constant shift into its component SH constant
1923 shift instructions. */
1924
b7dbbdb2 1925void
04f04b72 1926gen_shifty_op (int code, rtx *operands)
7208c779 1927{
1504eb7e 1928 int value = INTVAL (operands[2]);
73401833 1929 int max, i;
3dfc1807 1930
01515da1 1931 /* Truncate the shift count in case it is out of bounds. */
1932 value = value & 0x1f;
1933
73401833 1934 if (value == 31)
1504eb7e 1935 {
73401833 1936 if (code == LSHIFTRT)
97595bfd 1937 {
73401833 1938 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1939 emit_insn (gen_movt (operands[0]));
1940 return;
1504eb7e 1941 }
73401833 1942 else if (code == ASHIFT)
1504eb7e 1943 {
73401833 1944 /* There is a two instruction sequence for 31 bit left shifts,
1945 but it requires r0. */
1946 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
97595bfd 1947 {
73401833 1948 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
1949 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1950 return;
97595bfd 1951 }
1504eb7e 1952 }
73401833 1953 }
37ad966e 1954 else if (value == 0)
1955 {
1956 /* This can happen when not optimizing. We must output something here
1957 to prevent the compiler from aborting in final.c after the try_split
1958 call. */
1959 emit_insn (gen_nop ());
1960 return;
1961 }
4248bee7 1962
73401833 1963 max = shift_insns[value];
1964 for (i = 0; i < max; i++)
1965 gen_ashift (code, shift_amounts[value][i], operands[0]);
1966}
2ce8df5a 1967
1968/* Same as above, but optimized for values where the topmost bits don't
1969 matter. */
1970
b7dbbdb2 1971void
04f04b72 1972gen_shifty_hi_op (int code, rtx *operands)
2ce8df5a 1973{
1974 int value = INTVAL (operands[2]);
1975 int max, i;
04f04b72 1976 void (*gen_fun) (int, int, rtx);
2ce8df5a 1977
1978 /* This operation is used by and_shl for SImode values with a few
1979 high bits known to be cleared. */
1980 value &= 31;
1981 if (value == 0)
1982 {
1983 emit_insn (gen_nop ());
1984 return;
1985 }
1986
1987 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
1988 if (code == ASHIFT)
1989 {
1990 max = ext_shift_insns[value];
1991 for (i = 0; i < max; i++)
1992 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1993 }
1994 else
1995 /* When shifting right, emit the shifts in reverse order, so that
1996 solitary negative values come first. */
1997 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
1998 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1999}
73401833 2000
2001/* Output RTL for an arithmetic right shift. */
2002
2003/* ??? Rewrite to use super-optimizer sequences. */
2004
2005int
04f04b72 2006expand_ashiftrt (rtx *operands)
73401833 2007{
649bfcd0 2008 rtx sym;
73401833 2009 rtx wrk;
2010 char func[18];
2011 tree func_name;
2012 int value;
2013
79f0f2fe 2014 if (TARGET_SH3)
0b89dfaf 2015 {
79f0f2fe 2016 if (GET_CODE (operands[2]) != CONST_INT)
2017 {
2018 rtx count = copy_to_mode_reg (SImode, operands[2]);
2019 emit_insn (gen_negsi2 (count, count));
2020 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2021 return 1;
2022 }
8ded0752 2023 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
2024 > 1 + SH_DYNAMIC_SHIFT_COST)
79f0f2fe 2025 {
8ded0752 2026 rtx count
2027 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
79f0f2fe 2028 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2029 return 1;
2030 }
0b89dfaf 2031 }
73401833 2032 if (GET_CODE (operands[2]) != CONST_INT)
2033 return 0;
2034
8ded0752 2035 value = INTVAL (operands[2]) & 31;
73401833 2036
2037 if (value == 31)
2038 {
2039 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
2040 return 1;
2041 }
2042 else if (value >= 16 && value <= 19)
2043 {
2044 wrk = gen_reg_rtx (SImode);
2045 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
2046 value -= 16;
2047 while (value--)
2048 gen_ashift (ASHIFTRT, 1, wrk);
2049 emit_move_insn (operands[0], wrk);
2050 return 1;
4248bee7 2051 }
73401833 2052 /* Expand a short sequence inline, longer call a magic routine. */
2053 else if (value <= 5)
2054 {
2055 wrk = gen_reg_rtx (SImode);
2056 emit_move_insn (wrk, operands[1]);
2057 while (value--)
2058 gen_ashift (ASHIFTRT, 1, wrk);
2059 emit_move_insn (operands[0], wrk);
2060 return 1;
2061 }
2062
2063 wrk = gen_reg_rtx (Pmode);
2064
2065 /* Load the value into an arg reg and call a helper. */
7014838c 2066 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
73401833 2067 sprintf (func, "__ashiftrt_r4_%d", value);
2068 func_name = get_identifier (func);
45271277 2069 sym = function_symbol (IDENTIFIER_POINTER (func_name));
649bfcd0 2070 emit_move_insn (wrk, sym);
73401833 2071 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
7014838c 2072 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
73401833 2073 return 1;
7208c779 2074}
2ce8df5a 2075
b7dbbdb2 2076int
04f04b72 2077sh_dynamicalize_shift_p (rtx count)
8ded0752 2078{
2079 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
2080}
2081
2ce8df5a 2082/* Try to find a good way to implement the combiner pattern
2083 [(set (match_operand:SI 0 "register_operand" "r")
2084 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2085 (match_operand:SI 2 "const_int_operand" "n"))
2086 (match_operand:SI 3 "const_int_operand" "n"))) .
2087 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
2088 return 0 for simple right / left or left/right shift combination.
2089 return 1 for a combination of shifts with zero_extend.
2090 return 2 for a combination of shifts with an AND that needs r0.
2091 return 3 for a combination of shifts with an AND that needs an extra
2092 scratch register, when the three highmost bits of the AND mask are clear.
2093 return 4 for a combination of shifts with an AND that needs an extra
2094 scratch register, when any of the three highmost bits of the AND mask
2095 is set.
2096 If ATTRP is set, store an initial right shift width in ATTRP[0],
2097 and the instruction length in ATTRP[1] . These values are not valid
2098 when returning 0.
2099 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
2100 shift_amounts for the last shift value that is to be used before the
2101 sign extend. */
2102int
04f04b72 2103shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
2ce8df5a 2104{
2105 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
2106 int left = INTVAL (left_rtx), right;
2107 int best = 0;
2108 int cost, best_cost = 10000;
2109 int best_right = 0, best_len = 0;
2110 int i;
2111 int can_ext;
2112
2113 if (left < 0 || left > 31)
2114 return 0;
2115 if (GET_CODE (mask_rtx) == CONST_INT)
2116 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
2117 else
2118 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
d767e27e 2119 /* Can this be expressed as a right shift / left shift pair? */
2ce8df5a 2120 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
2121 right = exact_log2 (lsb);
2122 mask2 = ~(mask + lsb - 1);
2123 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
2124 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
2125 if (! mask2)
2126 best_cost = shift_insns[right] + shift_insns[right + left];
2127 /* mask has no trailing zeroes <==> ! right */
2128 else if (! right && mask2 == ~(lsb2 - 1))
2129 {
2130 int late_right = exact_log2 (lsb2);
2131 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
2132 }
d767e27e 2133 /* Try to use zero extend. */
2ce8df5a 2134 if (mask2 == ~(lsb2 - 1))
2135 {
2136 int width, first;
2137
2138 for (width = 8; width <= 16; width += 8)
2139 {
d767e27e 2140 /* Can we zero-extend right away? */
2141 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
2ce8df5a 2142 {
2143 cost
2144 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
2145 if (cost < best_cost)
2146 {
2147 best = 1;
2148 best_cost = cost;
2149 best_right = right;
2150 best_len = cost;
2151 if (attrp)
2152 attrp[2] = -1;
2153 }
2154 continue;
2155 }
2156 /* ??? Could try to put zero extend into initial right shift,
9df03d69 2157 or even shift a bit left before the right shift. */
2ce8df5a 2158 /* Determine value of first part of left shift, to get to the
2159 zero extend cut-off point. */
2160 first = width - exact_log2 (lsb2) + right;
2161 if (first >= 0 && right + left - first >= 0)
2162 {
2163 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
2164 + ext_shift_insns[right + left - first];
2165 if (cost < best_cost)
2166 {
2167 best = 1;
2168 best_cost = cost;
2169 best_right = right;
2170 best_len = cost;
2171 if (attrp)
2172 attrp[2] = first;
d767e27e 2173 }
2ce8df5a 2174 }
2175 }
2176 }
2177 /* Try to use r0 AND pattern */
2178 for (i = 0; i <= 2; i++)
2179 {
2180 if (i > right)
2181 break;
af2c1324 2182 if (! CONST_OK_FOR_K08 (mask >> i))
2ce8df5a 2183 continue;
2184 cost = (i != 0) + 2 + ext_shift_insns[left + i];
2185 if (cost < best_cost)
2186 {
2187 best = 2;
2188 best_cost = cost;
2189 best_right = i;
2190 best_len = cost - 1;
2191 }
2192 }
2193 /* Try to use a scratch register to hold the AND operand. */
d767e27e 2194 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
2ce8df5a 2195 for (i = 0; i <= 2; i++)
2196 {
2197 if (i > right)
2198 break;
af2c1324 2199 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
57ea6605 2200 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
2ce8df5a 2201 if (cost < best_cost)
2202 {
2203 best = 4 - can_ext;
2204 best_cost = cost;
2205 best_right = i;
af2c1324 2206 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
2ce8df5a 2207 }
2208 }
2209
2210 if (attrp)
2211 {
2212 attrp[0] = best_right;
2213 attrp[1] = best_len;
2214 }
2215 return best;
2216}
2217
2218/* This is used in length attributes of the unnamed instructions
2219 corresponding to shl_and_kind return values of 1 and 2. */
2220int
04f04b72 2221shl_and_length (rtx insn)
2ce8df5a 2222{
2223 rtx set_src, left_rtx, mask_rtx;
2224 int attributes[3];
2225
2226 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2227 left_rtx = XEXP (XEXP (set_src, 0), 1);
2228 mask_rtx = XEXP (set_src, 1);
2229 shl_and_kind (left_rtx, mask_rtx, attributes);
2230 return attributes[1];
2231}
2232
2233/* This is used in length attribute of the and_shl_scratch instruction. */
2234
2235int
04f04b72 2236shl_and_scr_length (rtx insn)
2ce8df5a 2237{
2238 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2239 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
2240 rtx op = XEXP (set_src, 0);
2241 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
2242 op = XEXP (XEXP (op, 0), 0);
2243 return len + shift_insns[INTVAL (XEXP (op, 1))];
2244}
2245
2246/* Generating rtl? */
2247extern int rtx_equal_function_value_matters;
2248
2249/* Generate rtl for instructions for which shl_and_kind advised a particular
2250 method of generating them, i.e. returned zero. */
2251
2252int
04f04b72 2253gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
2ce8df5a 2254{
2255 int attributes[3];
2256 unsigned HOST_WIDE_INT mask;
2257 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
2258 int right, total_shift;
d767e27e 2259 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
2ce8df5a 2260
2261 right = attributes[0];
2262 total_shift = INTVAL (left_rtx) + right;
2263 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
2264 switch (kind)
2265 {
2266 default:
2267 return -1;
2268 case 1:
2269 {
2270 int first = attributes[2];
2271 rtx operands[3];
2272
2273 if (first < 0)
2274 {
250fc29e 2275 emit_insn ((mask << right) <= 0xff
d767e27e 2276 ? gen_zero_extendqisi2 (dest,
2277 gen_lowpart (QImode, source))
2278 : gen_zero_extendhisi2 (dest,
2279 gen_lowpart (HImode, source)));
2ce8df5a 2280 source = dest;
2281 }
2282 if (source != dest)
2283 emit_insn (gen_movsi (dest, source));
2284 operands[0] = dest;
2285 if (right)
2286 {
2287 operands[2] = GEN_INT (right);
2288 gen_shifty_hi_op (LSHIFTRT, operands);
2289 }
2290 if (first > 0)
2291 {
2292 operands[2] = GEN_INT (first);
2293 gen_shifty_hi_op (ASHIFT, operands);
2294 total_shift -= first;
2295 mask <<= first;
2296 }
2297 if (first >= 0)
c721f167 2298 emit_insn (mask <= 0xff
d767e27e 2299 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
2300 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2ce8df5a 2301 if (total_shift > 0)
2302 {
2303 operands[2] = GEN_INT (total_shift);
2304 gen_shifty_hi_op (ASHIFT, operands);
2305 }
2306 break;
2307 }
2308 case 4:
2309 shift_gen_fun = gen_shifty_op;
2ce8df5a 2310 case 3:
74605264 2311 /* If the topmost bit that matters is set, set the topmost bits
2312 that don't matter. This way, we might be able to get a shorter
2313 signed constant. */
d767e27e 2314 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
2315 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
f8641a34 2316 case 2:
2ce8df5a 2317 /* Don't expand fine-grained when combining, because that will
2318 make the pattern fail. */
2319 if (rtx_equal_function_value_matters
2320 || reload_in_progress || reload_completed)
2321 {
2322 rtx operands[3];
2323
f8641a34 2324 /* Cases 3 and 4 should be handled by this split
2325 only while combining */
2326 if (kind > 2)
2327 abort ();
2ce8df5a 2328 if (right)
2329 {
2330 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
2331 source = dest;
2332 }
2333 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
2d7f129b 2334 if (total_shift)
2335 {
2336 operands[0] = dest;
2337 operands[1] = dest;
2338 operands[2] = GEN_INT (total_shift);
2339 shift_gen_fun (ASHIFT, operands);
2340 }
2ce8df5a 2341 break;
2342 }
2343 else
2344 {
2345 int neg = 0;
2346 if (kind != 4 && total_shift < 16)
2347 {
2348 neg = -ext_shift_amounts[total_shift][1];
2349 if (neg > 0)
2350 neg -= ext_shift_amounts[total_shift][2];
2351 else
2352 neg = 0;
2353 }
2354 emit_insn (gen_and_shl_scratch (dest, source,
2355 GEN_INT (right),
2356 GEN_INT (mask),
2357 GEN_INT (total_shift + neg),
2358 GEN_INT (neg)));
2359 emit_insn (gen_movsi (dest, dest));
2360 break;
2361 }
2362 }
2363 return 0;
2364}
2365
2366/* Try to find a good way to implement the combiner pattern
2367 [(set (match_operand:SI 0 "register_operand" "=r")
2368 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2369 (match_operand:SI 2 "const_int_operand" "n")
2370 (match_operand:SI 3 "const_int_operand" "n")
2371 (const_int 0)))
a5bd34f1 2372 (clobber (reg:SI T_REG))]
2ce8df5a 2373 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
2374 return 0 for simple left / right shift combination.
2375 return 1 for left shift / 8 bit sign extend / left shift.
2376 return 2 for left shift / 16 bit sign extend / left shift.
2377 return 3 for left shift / 8 bit sign extend / shift / sign extend.
2378 return 4 for left shift / 16 bit sign extend / shift / sign extend.
2379 return 5 for left shift / 16 bit sign extend / right shift
2380 return 6 for < 8 bit sign extend / left shift.
2381 return 7 for < 8 bit sign extend / left shift / single right shift.
2382 If COSTP is nonzero, assign the calculated cost to *COSTP. */
2383
2384int
04f04b72 2385shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
2ce8df5a 2386{
2387 int left, size, insize, ext;
87ed74ef 2388 int cost = 0, best_cost;
2ce8df5a 2389 int kind;
2390
2391 left = INTVAL (left_rtx);
2392 size = INTVAL (size_rtx);
2393 insize = size - left;
2394 if (insize <= 0)
2395 abort ();
2396 /* Default to left / right shift. */
2397 kind = 0;
2398 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
2399 if (size <= 16)
2400 {
2401 /* 16 bit shift / sign extend / 16 bit shift */
2402 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
2d7f129b 2403 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
2404 below, by alternative 3 or something even better. */
2ce8df5a 2405 if (cost < best_cost)
2406 {
2407 kind = 5;
2408 best_cost = cost;
2409 }
2410 }
2411 /* Try a plain sign extend between two shifts. */
2412 for (ext = 16; ext >= insize; ext -= 8)
2413 {
2414 if (ext <= size)
2415 {
2416 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
2417 if (cost < best_cost)
2418 {
30435bf8 2419 kind = ext / (unsigned) 8;
2ce8df5a 2420 best_cost = cost;
2421 }
2422 }
69b02875 2423 /* Check if we can do a sloppy shift with a final signed shift
2424 restoring the sign. */
2425 if (EXT_SHIFT_SIGNED (size - ext))
2426 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
2427 /* If not, maybe it's still cheaper to do the second shift sloppy,
2428 and do a final sign extend? */
2429 else if (size <= 16)
2430 cost = ext_shift_insns[ext - insize] + 1
2431 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
2432 else
2433 continue;
2434 if (cost < best_cost)
2ce8df5a 2435 {
30435bf8 2436 kind = ext / (unsigned) 8 + 2;
69b02875 2437 best_cost = cost;
2ce8df5a 2438 }
2439 }
2440 /* Check if we can sign extend in r0 */
2441 if (insize < 8)
2442 {
2443 cost = 3 + shift_insns[left];
2444 if (cost < best_cost)
2445 {
2446 kind = 6;
2447 best_cost = cost;
2448 }
2449 /* Try the same with a final signed shift. */
2450 if (left < 31)
2451 {
2452 cost = 3 + ext_shift_insns[left + 1] + 1;
2453 if (cost < best_cost)
2454 {
2455 kind = 7;
2456 best_cost = cost;
2457 }
2458 }
2459 }
2460 if (TARGET_SH3)
2461 {
2462 /* Try to use a dynamic shift. */
8ded0752 2463 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
2ce8df5a 2464 if (cost < best_cost)
2465 {
2466 kind = 0;
2467 best_cost = cost;
2468 }
2469 }
2470 if (costp)
2471 *costp = cost;
2472 return kind;
2473}
2474
2475/* Function to be used in the length attribute of the instructions
2476 implementing this pattern. */
2477
2478int
04f04b72 2479shl_sext_length (rtx insn)
2ce8df5a 2480{
2481 rtx set_src, left_rtx, size_rtx;
2482 int cost;
2483
2484 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2485 left_rtx = XEXP (XEXP (set_src, 0), 1);
2486 size_rtx = XEXP (set_src, 1);
2487 shl_sext_kind (left_rtx, size_rtx, &cost);
2488 return cost;
2489}
2490
2491/* Generate rtl for this pattern */
2492
2493int
04f04b72 2494gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
2ce8df5a 2495{
2496 int kind;
1a47e85b 2497 int left, size, insize, cost;
2ce8df5a 2498 rtx operands[3];
2499
1a47e85b 2500 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
2ce8df5a 2501 left = INTVAL (left_rtx);
2502 size = INTVAL (size_rtx);
2503 insize = size - left;
2504 switch (kind)
2505 {
2506 case 1:
2507 case 2:
2508 case 3:
2509 case 4:
2510 {
2511 int ext = kind & 1 ? 8 : 16;
2512 int shift2 = size - ext;
2513
2514 /* Don't expand fine-grained when combining, because that will
2515 make the pattern fail. */
2516 if (! rtx_equal_function_value_matters
2517 && ! reload_in_progress && ! reload_completed)
2518 {
2519 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2520 emit_insn (gen_movsi (dest, source));
2521 break;
2522 }
2523 if (dest != source)
2524 emit_insn (gen_movsi (dest, source));
2525 operands[0] = dest;
2d7f129b 2526 if (ext - insize)
2527 {
2528 operands[2] = GEN_INT (ext - insize);
2529 gen_shifty_hi_op (ASHIFT, operands);
2530 }
2ce8df5a 2531 emit_insn (kind & 1
d767e27e 2532 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
2533 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2ce8df5a 2534 if (kind <= 2)
2535 {
2d7f129b 2536 if (shift2)
2537 {
2538 operands[2] = GEN_INT (shift2);
2539 gen_shifty_op (ASHIFT, operands);
2540 }
2ce8df5a 2541 }
2542 else
2543 {
2d7f129b 2544 if (shift2 > 0)
2ce8df5a 2545 {
69b02875 2546 if (EXT_SHIFT_SIGNED (shift2))
2547 {
2548 operands[2] = GEN_INT (shift2 + 1);
2549 gen_shifty_op (ASHIFT, operands);
bcd9bd66 2550 operands[2] = const1_rtx;
69b02875 2551 gen_shifty_op (ASHIFTRT, operands);
2552 break;
2553 }
2ce8df5a 2554 operands[2] = GEN_INT (shift2);
2555 gen_shifty_hi_op (ASHIFT, operands);
2556 }
2d7f129b 2557 else if (shift2)
2ce8df5a 2558 {
2559 operands[2] = GEN_INT (-shift2);
2560 gen_shifty_hi_op (LSHIFTRT, operands);
2561 }
2562 emit_insn (size <= 8
2d7f129b 2563 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
2564 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2ce8df5a 2565 }
2566 break;
2567 }
2568 case 5:
2d7f129b 2569 {
2570 int i = 16 - size;
f2bfaeea 2571 if (! rtx_equal_function_value_matters
2572 && ! reload_in_progress && ! reload_completed)
2573 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2574 else
2575 {
2576 operands[0] = dest;
2577 operands[2] = GEN_INT (16 - insize);
2578 gen_shifty_hi_op (ASHIFT, operands);
2579 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2580 }
2d7f129b 2581 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2582 while (--i >= 0)
2583 gen_ashift (ASHIFTRT, 1, dest);
2584 break;
2585 }
2ce8df5a 2586 case 6:
2587 case 7:
2588 /* Don't expand fine-grained when combining, because that will
2589 make the pattern fail. */
2590 if (! rtx_equal_function_value_matters
2591 && ! reload_in_progress && ! reload_completed)
2592 {
2593 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2594 emit_insn (gen_movsi (dest, source));
2595 break;
2596 }
2597 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
2598 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
2599 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
2600 operands[0] = dest;
2601 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
2602 gen_shifty_op (ASHIFT, operands);
2603 if (kind == 7)
bcd9bd66 2604 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
2ce8df5a 2605 break;
2606 default:
2607 return -1;
2608 }
2609 return 0;
2610}
87e19636 2611
2612/* Prefix a symbol_ref name with "datalabel". */
2613
2614rtx
04f04b72 2615gen_datalabel_ref (rtx sym)
87e19636 2616{
2617 if (GET_CODE (sym) == LABEL_REF)
2618 return gen_rtx_CONST (GET_MODE (sym),
2619 gen_rtx_UNSPEC (GET_MODE (sym),
2620 gen_rtvec (1, sym),
2621 UNSPEC_DATALABEL));
2622
2623 if (GET_CODE (sym) != SYMBOL_REF)
2624 abort ();
2625
87e19636 2626 return sym;
2627}
2628
73401833 2629\f
2630/* The SH cannot load a large constant into a register, constants have to
2631 come from a pc relative load. The reference of a pc relative load
2632 instruction must be less than 1k infront of the instruction. This
2633 means that we often have to dump a constant inside a function, and
2634 generate code to branch around it.
7208c779 2635
73401833 2636 It is important to minimize this, since the branches will slow things
2637 down and make things bigger.
2638
2639 Worst case code looks like:
2640
2641 mov.l L1,rn
2642 bra L2
2643 nop
2644 align
2645 L1: .long value
2646 L2:
2647 ..
2648
2649 mov.l L3,rn
2650 bra L4
2651 nop
2652 align
2653 L3: .long value
2654 L4:
2655 ..
2656
2657 We fix this by performing a scan before scheduling, which notices which
2658 instructions need to have their operands fetched from the constant table
2659 and builds the table.
2660
2661 The algorithm is:
2662
2663 scan, find an instruction which needs a pcrel move. Look forward, find the
2664 last barrier which is within MAX_COUNT bytes of the requirement.
2665 If there isn't one, make one. Process all the instructions between
2666 the find and the barrier.
2667
2668 In the above example, we can tell that L3 is within 1k of L1, so
2669 the first move can be shrunk from the 3 insn+constant sequence into
2670 just 1 insn, and the constant moved to L3 to make:
2671
2672 mov.l L1,rn
2673 ..
2674 mov.l L3,rn
2675 bra L4
2676 nop
2677 align
2678 L3:.long value
2679 L4:.long value
2680
2681 Then the second move becomes the target for the shortening process. */
2682
2683typedef struct
2684{
2685 rtx value; /* Value in table. */
2686 rtx label; /* Label of value. */
ecf6ff7c 2687 rtx wend; /* End of window. */
73401833 2688 enum machine_mode mode; /* Mode of value. */
c5ea35c4 2689
2690 /* True if this constant is accessed as part of a post-increment
2691 sequence. Note that HImode constants are never accessed in this way. */
2692 bool part_of_sequence_p;
73401833 2693} pool_node;
2694
2695/* The maximum number of constants that can fit into one pool, since
2696 the pc relative range is 0...1020 bytes and constants are at least 4
2697 bytes long. */
2698
2699#define MAX_POOL_SIZE (1020/4)
2700static pool_node pool_vector[MAX_POOL_SIZE];
2701static int pool_size;
ecf6ff7c 2702static rtx pool_window_label;
2703static int pool_window_last;
73401833 2704
2705/* ??? If we need a constant in HImode which is the truncated value of a
2706 constant we need in SImode, we could combine the two entries thus saving
2707 two bytes. Is this common enough to be worth the effort of implementing
2708 it? */
2709
2710/* ??? This stuff should be done at the same time that we shorten branches.
2711 As it is now, we must assume that all branches are the maximum size, and
2712 this causes us to almost always output constant pools sooner than
2713 necessary. */
2714
2715/* Add a constant to the pool and return its label. */
2716
2717static rtx
04f04b72 2718add_constant (rtx x, enum machine_mode mode, rtx last_value)
97595bfd 2719{
2720 int i;
ecf6ff7c 2721 rtx lab, new, ref, newref;
73401833 2722
2723 /* First see if we've already got it. */
2724 for (i = 0; i < pool_size; i++)
97595bfd 2725 {
73401833 2726 if (x->code == pool_vector[i].value->code
2727 && mode == pool_vector[i].mode)
97595bfd 2728 {
73401833 2729 if (x->code == CODE_LABEL)
2730 {
2731 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
2732 continue;
2733 }
2734 if (rtx_equal_p (x, pool_vector[i].value))
1b61190c 2735 {
ecf6ff7c 2736 lab = new = 0;
1b61190c 2737 if (! last_value
2738 || ! i
2739 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
2740 {
ecf6ff7c 2741 new = gen_label_rtx ();
2742 LABEL_REFS (new) = pool_vector[i].label;
2743 pool_vector[i].label = lab = new;
1b61190c 2744 }
ecf6ff7c 2745 if (lab && pool_window_label)
2746 {
2747 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2748 ref = pool_vector[pool_window_last].wend;
2749 LABEL_NEXTREF (newref) = ref;
2750 pool_vector[pool_window_last].wend = newref;
2751 }
2752 if (new)
2753 pool_window_label = new;
2754 pool_window_last = i;
1b61190c 2755 return lab;
2756 }
97595bfd 2757 }
97595bfd 2758 }
47c009e5 2759
73401833 2760 /* Need a new one. */
2761 pool_vector[pool_size].value = x;
1b61190c 2762 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
c5ea35c4 2763 {
2764 lab = 0;
2765 pool_vector[pool_size - 1].part_of_sequence_p = true;
2766 }
1b61190c 2767 else
2768 lab = gen_label_rtx ();
73401833 2769 pool_vector[pool_size].mode = mode;
2770 pool_vector[pool_size].label = lab;
ecf6ff7c 2771 pool_vector[pool_size].wend = NULL_RTX;
c5ea35c4 2772 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
ecf6ff7c 2773 if (lab && pool_window_label)
2774 {
2775 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2776 ref = pool_vector[pool_window_last].wend;
2777 LABEL_NEXTREF (newref) = ref;
2778 pool_vector[pool_window_last].wend = newref;
2779 }
2780 if (lab)
2781 pool_window_label = lab;
2782 pool_window_last = pool_size;
73401833 2783 pool_size++;
2784 return lab;
97595bfd 2785}
1504eb7e 2786
51dade95 2787/* Output the literal table. START, if nonzero, is the first instruction
2788 this table is needed for, and also indicates that there is at least one
2789 casesi_worker_2 instruction; We have to emit the operand3 labels from
2790 these insns at a 4-byte aligned position. BARRIER is the barrier
2791 after which we are to place the table. */
47c009e5 2792
47c009e5 2793static void
51dade95 2794dump_table (rtx start, rtx barrier)
47c009e5 2795{
51dade95 2796 rtx scan = barrier;
97595bfd 2797 int i;
97595bfd 2798 int need_align = 1;
ecf6ff7c 2799 rtx lab, ref;
d1b048f6 2800 int have_df = 0;
47c009e5 2801
1504eb7e 2802 /* Do two passes, first time dump out the HI sized constants. */
47c009e5 2803
97595bfd 2804 for (i = 0; i < pool_size; i++)
47c009e5 2805 {
73401833 2806 pool_node *p = &pool_vector[i];
2807
97595bfd 2808 if (p->mode == HImode)
2809 {
2810 if (need_align)
2811 {
2812 scan = emit_insn_after (gen_align_2 (), scan);
2813 need_align = 0;
2814 }
ecf6ff7c 2815 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2816 scan = emit_label_after (lab, scan);
2817 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
2818 scan);
2819 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2820 {
2821 lab = XEXP (ref, 0);
2822 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2823 }
97595bfd 2824 }
d1b048f6 2825 else if (p->mode == DFmode)
2826 have_df = 1;
47c009e5 2827 }
73401833 2828
97595bfd 2829 need_align = 1;
47c009e5 2830
51dade95 2831 if (start)
2832 {
2833 scan = emit_insn_after (gen_align_4 (), scan);
2834 need_align = 0;
2835 for (; start != barrier; start = NEXT_INSN (start))
2836 if (GET_CODE (start) == INSN
2837 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
2838 {
2839 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
2840 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
2841
2842 scan = emit_label_after (lab, scan);
2843 }
2844 }
d1b048f6 2845 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
87e19636 2846 {
2847 rtx align_insn = NULL_RTX;
2848
2849 scan = emit_label_after (gen_label_rtx (), scan);
2850 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2851 need_align = 0;
2852
2853 for (i = 0; i < pool_size; i++)
2854 {
2855 pool_node *p = &pool_vector[i];
2856
2857 switch (p->mode)
2858 {
2859 case HImode:
2860 break;
2861 case SImode:
2862 case SFmode:
c5ea35c4 2863 if (align_insn && !p->part_of_sequence_p)
87e19636 2864 {
2865 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2866 emit_label_before (lab, align_insn);
2867 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
2868 align_insn);
2869 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2870 {
2871 lab = XEXP (ref, 0);
2872 emit_insn_before (gen_consttable_window_end (lab),
d767e27e 2873 align_insn);
87e19636 2874 }
2875 delete_insn (align_insn);
2876 align_insn = NULL_RTX;
2877 continue;
2878 }
2879 else
2880 {
2881 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2882 scan = emit_label_after (lab, scan);
2883 scan = emit_insn_after (gen_consttable_4 (p->value,
2884 const0_rtx), scan);
2885 need_align = ! need_align;
2886 }
2887 break;
2888 case DFmode:
87e19636 2889 if (need_align)
2890 {
2891 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2892 align_insn = scan;
2893 need_align = 0;
2894 }
d1b048f6 2895 case DImode:
87e19636 2896 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2897 scan = emit_label_after (lab, scan);
2898 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2899 scan);
2900 break;
2901 default:
2902 abort ();
2903 break;
2904 }
2905
2906 if (p->mode != HImode)
2907 {
2908 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2909 {
2910 lab = XEXP (ref, 0);
2911 scan = emit_insn_after (gen_consttable_window_end (lab),
2912 scan);
2913 }
2914 }
2915 }
2916
2917 pool_size = 0;
2918 }
2919
97595bfd 2920 for (i = 0; i < pool_size; i++)
47c009e5 2921 {
73401833 2922 pool_node *p = &pool_vector[i];
47c009e5 2923
97595bfd 2924 switch (p->mode)
47c009e5 2925 {
97595bfd 2926 case HImode:
2927 break;
2928 case SImode:
00f87557 2929 case SFmode:
97595bfd 2930 if (need_align)
47c009e5 2931 {
97595bfd 2932 need_align = 0;
f3d93547 2933 scan = emit_label_after (gen_label_rtx (), scan);
97595bfd 2934 scan = emit_insn_after (gen_align_4 (), scan);
47c009e5 2935 }
ecf6ff7c 2936 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2937 scan = emit_label_after (lab, scan);
2938 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
2939 scan);
97595bfd 2940 break;
00f87557 2941 case DFmode:
97595bfd 2942 case DImode:
2943 if (need_align)
2944 {
2945 need_align = 0;
f3d93547 2946 scan = emit_label_after (gen_label_rtx (), scan);
97595bfd 2947 scan = emit_insn_after (gen_align_4 (), scan);
2948 }
ecf6ff7c 2949 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2950 scan = emit_label_after (lab, scan);
2951 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2952 scan);
97595bfd 2953 break;
2954 default:
2955 abort ();
2956 break;
47c009e5 2957 }
ecf6ff7c 2958
2959 if (p->mode != HImode)
2960 {
2961 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2962 {
2963 lab = XEXP (ref, 0);
2964 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2965 }
2966 }
47c009e5 2967 }
47c009e5 2968
97595bfd 2969 scan = emit_insn_after (gen_consttable_end (), scan);
2970 scan = emit_barrier_after (scan);
2971 pool_size = 0;
ecf6ff7c 2972 pool_window_label = NULL_RTX;
2973 pool_window_last = 0;
97595bfd 2974}
47c009e5 2975
808a491c 2976/* Return nonzero if constant would be an ok source for a
73401833 2977 mov.w instead of a mov.l. */
47c009e5 2978
1504eb7e 2979static int
04f04b72 2980hi_const (rtx src)
97595bfd 2981{
73401833 2982 return (GET_CODE (src) == CONST_INT
2983 && INTVAL (src) >= -32768
2984 && INTVAL (src) <= 32767);
47c009e5 2985}
2986
808a491c 2987/* Nonzero if the insn is a move instruction which needs to be fixed. */
73401833 2988
2989/* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
af2c1324 2990 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
2991 need to fix it if the input value is CONST_OK_FOR_I08. */
73401833 2992
2993static int
04f04b72 2994broken_move (rtx insn)
47c009e5 2995{
00f87557 2996 if (GET_CODE (insn) == INSN)
2997 {
2998 rtx pat = PATTERN (insn);
2999 if (GET_CODE (pat) == PARALLEL)
3000 pat = XVECEXP (pat, 0, 0);
3001 if (GET_CODE (pat) == SET
3002 /* We can load any 8 bit value if we don't care what the high
3003 order bits end up as. */
3004 && GET_MODE (SET_DEST (pat)) != QImode
393fac7b 3005 && (CONSTANT_P (SET_SRC (pat))
3006 /* Match mova_const. */
3007 || (GET_CODE (SET_SRC (pat)) == UNSPEC
3008 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
3009 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
87ed74ef 3010 && ! (TARGET_SH2E
8ded0752 3011 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
00f87557 3012 && (fp_zero_operand (SET_SRC (pat))
3013 || fp_one_operand (SET_SRC (pat)))
4ea39690 3014 /* ??? If this is a -m4 or -m4-single compilation, in general
3015 we don't know the current setting of fpscr, so disable fldi.
3016 There is an exception if this was a register-register move
3017 before reload - and hence it was ascertained that we have
3018 single precision setting - and in a post-reload optimization
3019 we changed this to do a constant load. In that case
3020 we don't have an r0 clobber, hence we must use fldi. */
3021 && (! TARGET_SH4 || TARGET_FMOVD
3022 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
3023 == SCRATCH))
00f87557 3024 && GET_CODE (SET_DEST (pat)) == REG
e2142b04 3025 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
00f87557 3026 && (GET_CODE (SET_SRC (pat)) != CONST_INT
af2c1324 3027 || ! CONST_OK_FOR_I08 (INTVAL (SET_SRC (pat)))))
00f87557 3028 return 1;
3029 }
f3d93547 3030
73401833 3031 return 0;
47c009e5 3032}
47c009e5 3033
8ded0752 3034static int
04f04b72 3035mova_p (rtx insn)
8ded0752 3036{
3037 return (GET_CODE (insn) == INSN
3038 && GET_CODE (PATTERN (insn)) == SET
3039 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
393fac7b 3040 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
3041 /* Don't match mova_const. */
dc115ee8 3042 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn)), 0, 0)) == LABEL_REF);
8ded0752 3043}
3044
51dade95 3045/* Fix up a mova from a switch that went out of range. */
3046static void
3047fixup_mova (rtx mova)
3048{
3049 if (! flag_pic)
3050 {
3051 SET_SRC (PATTERN (mova)) = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3052 INSN_CODE (mova) = -1;
3053 }
3054 else
3055 {
3056 rtx worker = mova;
3057 rtx lab = gen_label_rtx ();
3058 rtx wpat, wpat0, wpat1, wsrc, diff;
3059
3060 do
3061 {
3062 worker = NEXT_INSN (worker);
3063 if (! worker
3064 || GET_CODE (worker) == CODE_LABEL
3065 || GET_CODE (worker) == JUMP_INSN)
3066 abort ();
3067 } while (recog_memoized (worker) != CODE_FOR_casesi_worker_1);
3068 wpat = PATTERN (worker);
3069 wpat0 = XVECEXP (wpat, 0, 0);
3070 wpat1 = XVECEXP (wpat, 0, 1);
3071 wsrc = SET_SRC (wpat0);
3072 PATTERN (worker) = (gen_casesi_worker_2
3073 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
3074 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
3075 XEXP (wpat1, 0)));
3076 INSN_CODE (worker) = -1;
3077 diff = gen_rtx_MINUS (Pmode, XVECEXP (SET_SRC (PATTERN (mova)), 0, 0),
3078 gen_rtx_LABEL_REF (Pmode, lab));
3079 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, diff), UNSPEC_PIC);
3080 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
3081 INSN_CODE (mova) = -1;
3082 }
3083}
3084
73401833 3085/* Find the last barrier from insn FROM which is close enough to hold the
3086 constant pool. If we can't find one, then create one near the end of
3087 the range. */
47c009e5 3088
73401833 3089static rtx
04f04b72 3090find_barrier (int num_mova, rtx mova, rtx from)
47c009e5 3091{
97595bfd 3092 int count_si = 0;
3093 int count_hi = 0;
3094 int found_hi = 0;
3095 int found_si = 0;
87e19636 3096 int found_di = 0;
9eaab178 3097 int hi_align = 2;
3098 int si_align = 2;
8ded0752 3099 int leading_mova = num_mova;
87ed74ef 3100 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
37ad966e 3101 int si_limit;
3102 int hi_limit;
73401833 3103
3104 /* For HImode: range is 510, add 4 because pc counts from address of
3105 second instruction after this one, subtract 2 for the jump instruction
9629ee1b 3106 that we may need to emit before the table, subtract 2 for the instruction
3107 that fills the jump delay slot (in very rare cases, reorg will take an
3108 instruction from after the constant pool or will leave the delay slot
3109 empty). This gives 510.
73401833 3110 For SImode: range is 1020, add 4 because pc counts from address of
3111 second instruction after this one, subtract 2 in case pc is 2 byte
3112 aligned, subtract 2 for the jump instruction that we may need to emit
9629ee1b 3113 before the table, subtract 2 for the instruction that fills the jump
3114 delay slot. This gives 1018. */
37ad966e 3115
8ded0752 3116 /* The branch will always be shortened now that the reference address for
ad87de1e 3117 forward branches is the successor address, thus we need no longer make
8ded0752 3118 adjustments to the [sh]i_limit for -O0. */
37ad966e 3119
8ded0752 3120 si_limit = 1018;
3121 hi_limit = 510;
e6c94d0d 3122
37ad966e 3123 while (from && count_si < si_limit && count_hi < hi_limit)
97595bfd 3124 {
9eaab178 3125 int inc = get_attr_length (from);
3126 int new_align = 1;
8ded0752 3127
9eaab178 3128 if (GET_CODE (from) == CODE_LABEL)
887884c5 3129 {
3130 if (optimize)
3131 new_align = 1 << label_to_alignment (from);
3132 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
3133 new_align = 1 << barrier_align (from);
3134 else
3135 new_align = 1;
3136 inc = 0;
3137 }
73401833 3138
97595bfd 3139 if (GET_CODE (from) == BARRIER)
8ded0752 3140 {
9eaab178 3141
8ded0752 3142 found_barrier = from;
9eaab178 3143
ad87de1e 3144 /* If we are at the end of the function, or in front of an alignment
8ded0752 3145 instruction, we need not insert an extra alignment. We prefer
3146 this kind of barrier. */
9eaab178 3147 if (barrier_align (from) > 2)
8ded0752 3148 good_barrier = from;
3149 }
73401833 3150
73401833 3151 if (broken_move (from))
97595bfd 3152 {
8ded0752 3153 rtx pat, src, dst;
3154 enum machine_mode mode;
3155
3156 pat = PATTERN (from);
3157 if (GET_CODE (pat) == PARALLEL)
3158 pat = XVECEXP (pat, 0, 0);
3159 src = SET_SRC (pat);
3160 dst = SET_DEST (pat);
3161 mode = GET_MODE (dst);
37ad966e 3162
3163 /* We must explicitly check the mode, because sometimes the
3164 front end will generate code to load unsigned constants into
3165 HImode targets without properly sign extending them. */
1b61190c 3166 if (mode == HImode
3167 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
22f26681 3168 {
8ded0752 3169 found_hi += 2;
22f26681 3170 /* We put the short constants before the long constants, so
3171 we must count the length of short constants in the range
3172 for the long constants. */
3173 /* ??? This isn't optimal, but is easy to do. */
8ded0752 3174 si_limit -= 2;
22f26681 3175 }
97595bfd 3176 else
8ded0752 3177 {
87e19636 3178 /* We dump DF/DI constants before SF/SI ones, because
3179 the limit is the same, but the alignment requirements
3180 are higher. We may waste up to 4 additional bytes
3181 for alignment, and the DF/DI constant may have
ada8cf8b 3182 another SF/SI constant placed before it. */
87e19636 3183 if (TARGET_SHCOMPACT
3184 && ! found_di
3185 && (mode == DFmode || mode == DImode))
3186 {
3187 found_di = 1;
3188 si_limit -= 8;
3189 }
9eaab178 3190 while (si_align > 2 && found_si + si_align - 2 > count_si)
3191 si_align >>= 1;
8ded0752 3192 if (found_si > count_si)
3193 count_si = found_si;
3194 found_si += GET_MODE_SIZE (mode);
3195 if (num_mova)
3196 si_limit -= GET_MODE_SIZE (mode);
3197 }
cc83a5de 3198
3199 /* See the code in machine_dependent_reorg, which has a similar if
c0359809 3200 statement that generates a new mova insn in many cases. */
e2142b04 3201 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
cc83a5de 3202 inc += 2;
97595bfd 3203 }
335e16a0 3204
9eaab178 3205 if (mova_p (from))
8ded0752 3206 {
3207 if (! num_mova++)
3208 {
3209 leading_mova = 0;
3210 mova = from;
3211 barrier_before_mova = good_barrier ? good_barrier : found_barrier;
3212 }
3213 if (found_si > count_si)
3214 count_si = found_si;
3215 }
335e16a0 3216 else if (GET_CODE (from) == JUMP_INSN
3217 && (GET_CODE (PATTERN (from)) == ADDR_VEC
3218 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
8ded0752 3219 {
3220 if (num_mova)
3221 num_mova--;
2a6493a5 3222 if (barrier_align (next_real_insn (from)) == align_jumps_log)
8ded0752 3223 {
3398e91d 3224 /* We have just passed the barrier in front of the
bd967f88 3225 ADDR_DIFF_VEC, which is stored in found_barrier. Since
3226 the ADDR_DIFF_VEC is accessed as data, just like our pool
3227 constants, this is a good opportunity to accommodate what
3228 we have gathered so far.
8ded0752 3229 If we waited any longer, we could end up at a barrier in
3230 front of code, which gives worse cache usage for separated
3231 instruction / data caches. */
bd967f88 3232 good_barrier = found_barrier;
8ded0752 3233 break;
3234 }
bd967f88 3235 else
3236 {
3237 rtx body = PATTERN (from);
3238 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
3239 }
8ded0752 3240 }
0d93aeb0 3241 /* For the SH1, we generate alignments even after jumps-around-jumps. */
3242 else if (GET_CODE (from) == JUMP_INSN
3243 && ! TARGET_SH2
3244 && ! TARGET_SMALLCODE)
3245 new_align = 4;
335e16a0 3246
97595bfd 3247 if (found_si)
9eaab178 3248 {
0d93aeb0 3249 count_si += inc;
9eaab178 3250 if (new_align > si_align)
3251 {
b7dbbdb2 3252 si_limit -= (count_si - 1) & (new_align - si_align);
9eaab178 3253 si_align = new_align;
3254 }
b7dbbdb2 3255 count_si = (count_si + new_align - 1) & -new_align;
9eaab178 3256 }
97595bfd 3257 if (found_hi)
9eaab178 3258 {
0d93aeb0 3259 count_hi += inc;
9eaab178 3260 if (new_align > hi_align)
3261 {
b7dbbdb2 3262 hi_limit -= (count_hi - 1) & (new_align - hi_align);
9eaab178 3263 hi_align = new_align;
3264 }
b7dbbdb2 3265 count_hi = (count_hi + new_align - 1) & -new_align;
9eaab178 3266 }
97595bfd 3267 from = NEXT_INSN (from);
3268 }
3269
8ded0752 3270 if (num_mova)
17bec211 3271 {
3272 if (leading_mova)
3273 {
3274 /* Try as we might, the leading mova is out of range. Change
3275 it into a load (which will become a pcload) and retry. */
51dade95 3276 fixup_mova (mova);
17bec211 3277 return find_barrier (0, 0, mova);
3278 }
3279 else
3280 {
3281 /* Insert the constant pool table before the mova instruction,
3282 to prevent the mova label reference from going out of range. */
3283 from = mova;
3284 good_barrier = found_barrier = barrier_before_mova;
3285 }
3286 }
335e16a0 3287
8ded0752 3288 if (found_barrier)
3289 {
9eaab178 3290 if (good_barrier && next_real_insn (found_barrier))
8ded0752 3291 found_barrier = good_barrier;
8ded0752 3292 }
3293 else
47c009e5 3294 {
73401833 3295 /* We didn't find a barrier in time to dump our stuff,
3296 so we'll make one. */
97595bfd 3297 rtx label = gen_label_rtx ();
73401833 3298
92e80318 3299 /* If we exceeded the range, then we must back up over the last
3300 instruction we looked at. Otherwise, we just need to undo the
3301 NEXT_INSN at the end of the loop. */
37ad966e 3302 if (count_hi > hi_limit || count_si > si_limit)
92e80318 3303 from = PREV_INSN (PREV_INSN (from));
3304 else
3305 from = PREV_INSN (from);
3306
73401833 3307 /* Walk back to be just before any jump or label.
3308 Putting it before a label reduces the number of times the branch
3309 around the constant pool table will be hit. Putting it before
3310 a jump makes it more likely that the bra delay slot will be
3311 filled. */
3312 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
2e3d4844 3313 || GET_CODE (from) == CODE_LABEL)
73401833 3314 from = PREV_INSN (from);
3315
97595bfd 3316 from = emit_jump_insn_after (gen_jump (label), from);
3317 JUMP_LABEL (from) = label;
bdb9edaa 3318 LABEL_NUSES (label) = 1;
97595bfd 3319 found_barrier = emit_barrier_after (from);
3320 emit_label_after (label, found_barrier);
47c009e5 3321 }
47c009e5 3322
73401833 3323 return found_barrier;
97595bfd 3324}
47c009e5 3325
881ffd32 3326/* If the instruction INSN is implemented by a special function, and we can
3327 positively find the register that is used to call the sfunc, and this
3328 register is not used anywhere else in this instruction - except as the
3329 destination of a set, return this register; else, return 0. */
8ded0752 3330rtx
04f04b72 3331sfunc_uses_reg (rtx insn)
881ffd32 3332{
3333 int i;
3334 rtx pattern, part, reg_part, reg;
3335
3336 if (GET_CODE (insn) != INSN)
3337 return 0;
3338 pattern = PATTERN (insn);
3339 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
3340 return 0;
3341
3342 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
3343 {
3344 part = XVECEXP (pattern, 0, i);
8ded0752 3345 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
881ffd32 3346 reg_part = part;
3347 }
3348 if (! reg_part)
3349 return 0;
3350 reg = XEXP (reg_part, 0);
3351 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
3352 {
3353 part = XVECEXP (pattern, 0, i);
1b61190c 3354 if (part == reg_part || GET_CODE (part) == CLOBBER)
881ffd32 3355 continue;
3356 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
3357 && GET_CODE (SET_DEST (part)) == REG)
3358 ? SET_SRC (part) : part)))
3359 return 0;
3360 }
3361 return reg;
3362}
3363
90e84010 3364/* See if the only way in which INSN uses REG is by calling it, or by
3365 setting it while calling it. Set *SET to a SET rtx if the register
3366 is set by INSN. */
3367
3368static int
04f04b72 3369noncall_uses_reg (rtx reg, rtx insn, rtx *set)
90e84010 3370{
881ffd32 3371 rtx pattern, reg2;
90e84010 3372
3373 *set = NULL_RTX;
3374
881ffd32 3375 reg2 = sfunc_uses_reg (insn);
3376 if (reg2 && REGNO (reg2) == REGNO (reg))
3377 {
3378 pattern = single_set (insn);
3379 if (pattern
3380 && GET_CODE (SET_DEST (pattern)) == REG
3381 && REGNO (reg) == REGNO (SET_DEST (pattern)))
3382 *set = pattern;
3383 return 0;
3384 }
90e84010 3385 if (GET_CODE (insn) != CALL_INSN)
3386 {
3387 /* We don't use rtx_equal_p because we don't care if the mode is
3388 different. */
3389 pattern = single_set (insn);
3390 if (pattern
3391 && GET_CODE (SET_DEST (pattern)) == REG
3392 && REGNO (reg) == REGNO (SET_DEST (pattern)))
3393 {
881ffd32 3394 rtx par, part;
3395 int i;
3396
90e84010 3397 *set = pattern;
881ffd32 3398 par = PATTERN (insn);
3399 if (GET_CODE (par) == PARALLEL)
3400 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
3401 {
3402 part = XVECEXP (par, 0, i);
3403 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
3404 return 1;
3405 }
3406 return reg_mentioned_p (reg, SET_SRC (pattern));
90e84010 3407 }
3408
3409 return 1;
3410 }
3411
3412 pattern = PATTERN (insn);
3413
3414 if (GET_CODE (pattern) == PARALLEL)
3415 {
3416 int i;
3417
3418 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
3419 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
3420 return 1;
3421 pattern = XVECEXP (pattern, 0, 0);
3422 }
3423
3424 if (GET_CODE (pattern) == SET)
3425 {
3426 if (reg_mentioned_p (reg, SET_DEST (pattern)))
3427 {
3428 /* We don't use rtx_equal_p, because we don't care if the
3429 mode is different. */
3430 if (GET_CODE (SET_DEST (pattern)) != REG
3431 || REGNO (reg) != REGNO (SET_DEST (pattern)))
3432 return 1;
3433
3434 *set = pattern;
3435 }
3436
3437 pattern = SET_SRC (pattern);
3438 }
3439
3440 if (GET_CODE (pattern) != CALL
3441 || GET_CODE (XEXP (pattern, 0)) != MEM
3442 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
3443 return 1;
3444
3445 return 0;
3446}
3447
8ded0752 3448/* Given a X, a pattern of an insn or a part of it, return a mask of used
3449 general registers. Bits 0..15 mean that the respective registers
3450 are used as inputs in the instruction. Bits 16..31 mean that the
3451 registers 0..15, respectively, are used as outputs, or are clobbered.
3452 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
3453int
04f04b72 3454regs_used (rtx x, int is_dest)
8ded0752 3455{
3456 enum rtx_code code;
d2ca078f 3457 const char *fmt;
8ded0752 3458 int i, used = 0;
3459
3460 if (! x)
3461 return used;
3462 code = GET_CODE (x);
3463 switch (code)
3464 {
3465 case REG:
3466 if (REGNO (x) < 16)
3467 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3468 << (REGNO (x) + is_dest));
3469 return 0;
3470 case SUBREG:
3471 {
3472 rtx y = SUBREG_REG (x);
3473
3474 if (GET_CODE (y) != REG)
3475 break;
3476 if (REGNO (y) < 16)
3477 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
701e46d0 3478 << (REGNO (y) +
3479 subreg_regno_offset (REGNO (y),
3480 GET_MODE (y),
3481 SUBREG_BYTE (x),
3482 GET_MODE (x)) + is_dest));
8ded0752 3483 return 0;
3484 }
3485 case SET:
3486 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
3487 case RETURN:
3488 /* If there was a return value, it must have been indicated with USE. */
3489 return 0x00ffff00;
3490 case CLOBBER:
3491 is_dest = 1;
3492 break;
3493 case MEM:
3494 is_dest = 0;
3495 break;
3496 case CALL:
3497 used |= 0x00ff00f0;
3498 break;
b7dbbdb2 3499 default:
3500 break;
8ded0752 3501 }
3502
3503 fmt = GET_RTX_FORMAT (code);
3504
3505 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3506 {
3507 if (fmt[i] == 'E')
3508 {
3509 register int j;
3510 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3511 used |= regs_used (XVECEXP (x, i, j), is_dest);
3512 }
3513 else if (fmt[i] == 'e')
3514 used |= regs_used (XEXP (x, i), is_dest);
3515 }
3516 return used;
3517}
3518
3519/* Create an instruction that prevents redirection of a conditional branch
ad87de1e 3520 to the destination of the JUMP with address ADDR.
8ded0752 3521 If the branch needs to be implemented as an indirect jump, try to find
3522 a scratch register for it.
3523 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
3524 If any preceding insn that doesn't fit into a delay slot is good enough,
3525 pass 1. Pass 2 if a definite blocking insn is needed.
3526 -1 is used internally to avoid deep recursion.
3527 If a blocking instruction is made or recognized, return it. */
3528
3529static rtx
04f04b72 3530gen_block_redirect (rtx jump, int addr, int need_block)
8ded0752 3531{
3532 int dead = 0;
3533 rtx prev = prev_nonnote_insn (jump);
3534 rtx dest;
3535
3536 /* First, check if we already have an instruction that satisfies our need. */
3537 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
3538 {
3539 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
3540 return prev;
3541 if (GET_CODE (PATTERN (prev)) == USE
3542 || GET_CODE (PATTERN (prev)) == CLOBBER
3543 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3544 prev = jump;
3545 else if ((need_block &= ~1) < 0)
3546 return prev;
3547 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
3548 need_block = 0;
3549 }
b78739b6 3550 if (GET_CODE (PATTERN (jump)) == RETURN)
3551 {
3552 if (! need_block)
3553 return prev;
3554 /* Reorg even does nasty things with return insns that cause branches
3555 to go out of range - see find_end_label and callers. */
bcd9bd66 3556 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
b78739b6 3557 }
8ded0752 3558 /* We can't use JUMP_LABEL here because it might be undefined
3559 when not optimizing. */
3560 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
3561 /* If the branch is out of range, try to find a scratch register for it. */
3562 if (optimize
30435bf8 3563 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3564 > 4092 + 4098))
8ded0752 3565 {
3566 rtx scan;
3567 /* Don't look for the stack pointer as a scratch register,
ad87de1e 3568 it would cause trouble if an interrupt occurred. */
8ded0752 3569 unsigned try = 0x7fff, used;
3570 int jump_left = flag_expensive_optimizations + 1;
3571
3572 /* It is likely that the most recent eligible instruction is wanted for
3573 the delay slot. Therefore, find out which registers it uses, and
3574 try to avoid using them. */
3575
b7dbbdb2 3576 for (scan = jump; (scan = PREV_INSN (scan)); )
8ded0752 3577 {
3578 enum rtx_code code;
3579
3580 if (INSN_DELETED_P (scan))
3581 continue;
3582 code = GET_CODE (scan);
3583 if (code == CODE_LABEL || code == JUMP_INSN)
3584 break;
3585 if (code == INSN
3586 && GET_CODE (PATTERN (scan)) != USE
3587 && GET_CODE (PATTERN (scan)) != CLOBBER
3588 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
3589 {
3590 try &= ~regs_used (PATTERN (scan), 0);
3591 break;
3592 }
3593 }
17bec211 3594 for (used = dead = 0, scan = JUMP_LABEL (jump);
3595 (scan = NEXT_INSN (scan)); )
8ded0752 3596 {
3597 enum rtx_code code;
3598
3599 if (INSN_DELETED_P (scan))
3600 continue;
3601 code = GET_CODE (scan);
6720e96c 3602 if (INSN_P (scan))
8ded0752 3603 {
3604 used |= regs_used (PATTERN (scan), 0);
3605 if (code == CALL_INSN)
3606 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
3607 dead |= (used >> 16) & ~used;
3608 if (dead & try)
3609 {
3610 dead &= try;
3611 break;
3612 }
3613 if (code == JUMP_INSN)
17bec211 3614 {
3615 if (jump_left-- && simplejump_p (scan))
3616 scan = JUMP_LABEL (scan);
3617 else
3618 break;
3619 }
8ded0752 3620 }
3621 }
3622 /* Mask out the stack pointer again, in case it was
3623 the only 'free' register we have found. */
3624 dead &= 0x7fff;
3625 }
3626 /* If the immediate destination is still in range, check for possible
3627 threading with a jump beyond the delay slot insn.
3628 Don't check if we are called recursively; the jump has been or will be
ad87de1e 3629 checked in a different invocation then. */
8ded0752 3630
3631 else if (optimize && need_block >= 0)
3632 {
3633 rtx next = next_active_insn (next_active_insn (dest));
3634 if (next && GET_CODE (next) == JUMP_INSN
3635 && GET_CODE (PATTERN (next)) == SET
adbcc7c4 3636 && recog_memoized (next) == CODE_FOR_jump_compact)
8ded0752 3637 {
3638 dest = JUMP_LABEL (next);
3639 if (dest
30435bf8 3640 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
47fc0706 3641 > 4092 + 4098))
3642 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
8ded0752 3643 }
3644 }
3645
3646 if (dead)
3647 {
7014838c 3648 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
8ded0752 3649
3650 /* It would be nice if we could convert the jump into an indirect
ad87de1e 3651 jump / far branch right now, and thus exposing all constituent
8ded0752 3652 instructions to further optimization. However, reorg uses
3653 simplejump_p to determine if there is an unconditional jump where
3654 it should try to schedule instructions from the target of the
3655 branch; simplejump_p fails for indirect jumps even if they have
3656 a JUMP_LABEL. */
3657 rtx insn = emit_insn_before (gen_indirect_jump_scratch
3658 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
3659 , jump);
2a6493a5 3660 /* ??? We would like this to have the scope of the jump, but that
3661 scope will change when a delay slot insn of an inner scope is added.
3662 Hence, after delay slot scheduling, we'll have to expect
3663 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
3664 the jump. */
3665
2f49e3cb 3666 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
8ded0752 3667 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
3668 return insn;
3669 }
3670 else if (need_block)
3671 /* We can't use JUMP_LABEL here because it might be undefined
3672 when not optimizing. */
3673 return emit_insn_before (gen_block_branch_redirect
3674 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
3675 , jump);
3676 return prev;
3677}
3678
3679#define CONDJUMP_MIN -252
3680#define CONDJUMP_MAX 262
3681struct far_branch
3682{
3683 /* A label (to be placed) in front of the jump
3684 that jumps to our ultimate destination. */
3685 rtx near_label;
3686 /* Where we are going to insert it if we cannot move the jump any farther,
3687 or the jump itself if we have picked up an existing jump. */
3688 rtx insert_place;
3689 /* The ultimate destination. */
3690 rtx far_label;
3691 struct far_branch *prev;
3692 /* If the branch has already been created, its address;
3693 else the address of its first prospective user. */
3694 int address;
3695};
3696
04f04b72 3697static void gen_far_branch (struct far_branch *);
8ded0752 3698enum mdep_reorg_phase_e mdep_reorg_phase;
26576132 3699static void
04f04b72 3700gen_far_branch (struct far_branch *bp)
8ded0752 3701{
3702 rtx insn = bp->insert_place;
3703 rtx jump;
3704 rtx label = gen_label_rtx ();
3705
3706 emit_label_after (label, insn);
3707 if (bp->far_label)
3708 {
3709 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
3710 LABEL_NUSES (bp->far_label)++;
3711 }
3712 else
3713 jump = emit_jump_insn_after (gen_return (), insn);
1b61190c 3714 /* Emit a barrier so that reorg knows that any following instructions
3715 are not reachable via a fall-through path.
1fc184ee 3716 But don't do this when not optimizing, since we wouldn't suppress the
1b61190c 3717 alignment for the barrier then, and could end up with out-of-range
3718 pc-relative loads. */
3719 if (optimize)
3720 emit_barrier_after (jump);
8ded0752 3721 emit_label_after (bp->near_label, insn);
3722 JUMP_LABEL (jump) = bp->far_label;
5e20801c 3723 if (! invert_jump (insn, label, 1))
8ded0752 3724 abort ();
b78739b6 3725 /* If we are branching around a jump (rather than a return), prevent
3726 reorg from using an insn from the jump target as the delay slot insn -
3727 when reorg did this, it pessimized code (we rather hide the delay slot)
3728 and it could cause branches to go out of range. */
3729 if (bp->far_label)
3730 (emit_insn_after
3731 (gen_stuff_delay_slot
3732 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
3733 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
3734 insn));
8ded0752 3735 /* Prevent reorg from undoing our splits. */
3736 gen_block_redirect (jump, bp->address += 2, 2);
3737}
3738
8ded0752 3739/* Fix up ADDR_DIFF_VECs. */
3740void
04f04b72 3741fixup_addr_diff_vecs (rtx first)
8ded0752 3742{
3743 rtx insn;
9eaab178 3744
8ded0752 3745 for (insn = first; insn; insn = NEXT_INSN (insn))
3746 {
21022457 3747 rtx vec_lab, pat, prev, prevpat, x, braf_label;
8ded0752 3748
3749 if (GET_CODE (insn) != JUMP_INSN
3750 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
3751 continue;
3752 pat = PATTERN (insn);
9eaab178 3753 vec_lab = XEXP (XEXP (pat, 0), 0);
8ded0752 3754
9eaab178 3755 /* Search the matching casesi_jump_2. */
3756 for (prev = vec_lab; ; prev = PREV_INSN (prev))
8ded0752 3757 {
9eaab178 3758 if (GET_CODE (prev) != JUMP_INSN)
3759 continue;
3760 prevpat = PATTERN (prev);
3761 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
3762 continue;
3763 x = XVECEXP (prevpat, 0, 1);
3764 if (GET_CODE (x) != USE)
3765 continue;
3766 x = XEXP (x, 0);
3767 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
3768 break;
8ded0752 3769 }
21022457 3770
3771 /* Emit the reference label of the braf where it belongs, right after
3772 the casesi_jump_2 (i.e. braf). */
3773 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
3774 emit_label_after (braf_label, prev);
3775
9eaab178 3776 /* Fix up the ADDR_DIF_VEC to be relative
3777 to the reference address of the braf. */
21022457 3778 XEXP (XEXP (pat, 0), 0) = braf_label;
8ded0752 3779 }
8ded0752 3780}
3781
9eaab178 3782/* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3783 a barrier. Return the base 2 logarithm of the desired alignment. */
8ded0752 3784int
04f04b72 3785barrier_align (rtx barrier_or_label)
8ded0752 3786{
9eaab178 3787 rtx next = next_real_insn (barrier_or_label), pat, prev;
87ed74ef 3788 int slot, credit, jump_to_next = 0;
9eaab178 3789
3790 if (! next)
8ded0752 3791 return 0;
8ded0752 3792
9eaab178 3793 pat = PATTERN (next);
8ded0752 3794
9eaab178 3795 if (GET_CODE (pat) == ADDR_DIFF_VEC)
3796 return 2;
8ded0752 3797
a5bd34f1 3798 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
9eaab178 3799 /* This is a barrier in front of a constant table. */
3800 return 0;
3801
3802 prev = prev_real_insn (barrier_or_label);
3803 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
8ded0752 3804 {
9eaab178 3805 pat = PATTERN (prev);
3806 /* If this is a very small table, we want to keep the alignment after
3807 the table to the minimum for proper code alignment. */
3808 return ((TARGET_SMALLCODE
acda5809 3809 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
d767e27e 3810 <= (unsigned) 1 << (CACHE_LOG - 2)))
2a6493a5 3811 ? 1 << TARGET_SHMEDIA : align_jumps_log);
8ded0752 3812 }
9eaab178 3813
3814 if (TARGET_SMALLCODE)
3815 return 0;
3816
ecc15191 3817 if (! TARGET_SH2 || ! optimize)
2a6493a5 3818 return align_jumps_log;
9eaab178 3819
1b61190c 3820 /* When fixing up pcloads, a constant table might be inserted just before
3821 the basic block that ends with the barrier. Thus, we can't trust the
3822 instruction lengths before that. */
3823 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
8ded0752 3824 {
1b61190c 3825 /* Check if there is an immediately preceding branch to the insn beyond
3826 the barrier. We must weight the cost of discarding useful information
3827 from the current cache line when executing this branch and there is
3828 an alignment, against that of fetching unneeded insn in front of the
3829 branch target when there is no alignment. */
3830
fd787fea 3831 /* There are two delay_slot cases to consider. One is the simple case
3832 where the preceding branch is to the insn beyond the barrier (simple
3833 delay slot filling), and the other is where the preceding branch has
3834 a delay slot that is a duplicate of the insn after the barrier
3835 (fill_eager_delay_slots) and the branch is to the insn after the insn
3836 after the barrier. */
3837
1b61190c 3838 /* PREV is presumed to be the JUMP_INSN for the barrier under
3839 investigation. Skip to the insn before it. */
3840 prev = prev_real_insn (prev);
3841
26576132 3842 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
1b61190c 3843 credit >= 0 && prev && GET_CODE (prev) == INSN;
3844 prev = prev_real_insn (prev))
3845 {
fd787fea 3846 jump_to_next = 0;
1b61190c 3847 if (GET_CODE (PATTERN (prev)) == USE
3848 || GET_CODE (PATTERN (prev)) == CLOBBER)
3849 continue;
3850 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
fd787fea 3851 {
3852 prev = XVECEXP (PATTERN (prev), 0, 1);
3853 if (INSN_UID (prev) == INSN_UID (next))
3854 {
3855 /* Delay slot was filled with insn at jump target. */
3856 jump_to_next = 1;
3857 continue;
3858 }
3859 }
3860
1b61190c 3861 if (slot &&
3862 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3863 slot = 0;
3864 credit -= get_attr_length (prev);
3865 }
3866 if (prev
3867 && GET_CODE (prev) == JUMP_INSN
24f975d6 3868 && JUMP_LABEL (prev))
3869 {
3870 rtx x;
7628b8bf 3871 if (jump_to_next
24f975d6 3872 || next_real_insn (JUMP_LABEL (prev)) == next
07eac433 3873 /* If relax_delay_slots() decides NEXT was redundant
3874 with some previous instruction, it will have
3875 redirected PREV's jump to the following insn. */
67169380 3876 || JUMP_LABEL (prev) == next_nonnote_insn (next)
7628b8bf 3877 /* There is no upper bound on redundant instructions
3878 that might have been skipped, but we must not put an
24f975d6 3879 alignment where none had been before. */
3880 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
3881 (INSN_P (x)
3882 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
72cc4fb4 3883 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
3884 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
24f975d6 3885 {
3886 rtx pat = PATTERN (prev);
3887 if (GET_CODE (pat) == PARALLEL)
7628b8bf 3888 pat = XVECEXP (pat, 0, 0);
24f975d6 3889 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
3890 return 0;
3891 }
7628b8bf 3892 }
9eaab178 3893 }
24f975d6 3894
2a6493a5 3895 return align_jumps_log;
8ded0752 3896}
3897
afd5d59a 3898/* If we are inside a phony loop, almost any kind of label can turn up as the
3899 first one in the loop. Aligning a braf label causes incorrect switch
3900 destination addresses; we can detect braf labels because they are
3901 followed by a BARRIER.
3902 Applying loop alignment to small constant or switch tables is a waste
3903 of space, so we suppress this too. */
3904int
04f04b72 3905sh_loop_align (rtx label)
afd5d59a 3906{
3907 rtx next = label;
3908
3909 do
3910 next = next_nonnote_insn (next);
3911 while (next && GET_CODE (next) == CODE_LABEL);
3912
3913 if (! next
9204e736 3914 || ! INSN_P (next)
afd5d59a 3915 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
3916 || recog_memoized (next) == CODE_FOR_consttable_2)
3917 return 0;
87e19636 3918
2a6493a5 3919 return align_loops_log;
afd5d59a 3920}
3921
2efea8c0 3922/* Do a final pass over the function, just before delayed branch
90e84010 3923 scheduling. */
47c009e5 3924
2efea8c0 3925static void
04f04b72 3926sh_reorg (void)
97595bfd 3927{
2efea8c0 3928 rtx first, insn, mova = NULL_RTX;
8ded0752 3929 int num_mova;
7014838c 3930 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
3931 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
73401833 3932
2efea8c0 3933 first = get_insns ();
3934
5acd0683 3935 /* We must split call insns before introducing `mova's. If we're
3936 optimizing, they'll have already been split. Otherwise, make
3937 sure we don't split them too late. */
3938 if (! optimize)
161b1647 3939 split_all_insns_noflow ();
5acd0683 3940
87e19636 3941 if (TARGET_SHMEDIA)
3942 return;
3943
90e84010 3944 /* If relaxing, generate pseudo-ops to associate function calls with
3945 the symbols they call. It does no harm to not generate these
3946 pseudo-ops. However, when we can generate them, it enables to
3947 linker to potentially relax the jsr to a bsr, and eliminate the
3948 register load and, possibly, the constant pool entry. */
3949
8ded0752 3950 mdep_reorg_phase = SH_INSERT_USES_LABELS;
90e84010 3951 if (TARGET_RELAX)
3952 {
3953 /* Remove all REG_LABEL notes. We want to use them for our own
3954 purposes. This works because none of the remaining passes
3955 need to look at them.
3956
3957 ??? But it may break in the future. We should use a machine
3958 dependent REG_NOTE, or some other approach entirely. */
3959 for (insn = first; insn; insn = NEXT_INSN (insn))
3960 {
9204e736 3961 if (INSN_P (insn))
90e84010 3962 {
3963 rtx note;
3964
3965 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
3966 remove_note (insn, note);
3967 }
3968 }
3969
3970 for (insn = first; insn; insn = NEXT_INSN (insn))
3971 {
3972 rtx pattern, reg, link, set, scan, dies, label;
3973 int rescan = 0, foundinsn = 0;
3974
881ffd32 3975 if (GET_CODE (insn) == CALL_INSN)
3976 {
3977 pattern = PATTERN (insn);
90e84010 3978
881ffd32 3979 if (GET_CODE (pattern) == PARALLEL)
3980 pattern = XVECEXP (pattern, 0, 0);
3981 if (GET_CODE (pattern) == SET)
3982 pattern = SET_SRC (pattern);
90e84010 3983
881ffd32 3984 if (GET_CODE (pattern) != CALL
3985 || GET_CODE (XEXP (pattern, 0)) != MEM)
3986 continue;
90e84010 3987
881ffd32 3988 reg = XEXP (XEXP (pattern, 0), 0);
3989 }
3990 else
3991 {
3992 reg = sfunc_uses_reg (insn);
3993 if (! reg)
3994 continue;
3995 }
90e84010 3996
90e84010 3997 if (GET_CODE (reg) != REG)
3998 continue;
3999
4000 /* This is a function call via REG. If the only uses of REG
4001 between the time that it is set and the time that it dies
4002 are in function calls, then we can associate all the
4003 function calls with the setting of REG. */
4004
4005 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
4006 {
3730a264 4007 if (REG_NOTE_KIND (link) != 0)
4008 continue;
90e84010 4009 set = single_set (XEXP (link, 0));
4010 if (set && rtx_equal_p (reg, SET_DEST (set)))
4011 {
4012 link = XEXP (link, 0);
4013 break;
4014 }
4015 }
4016
4017 if (! link)
4018 {
4019 /* ??? Sometimes global register allocation will have
4020 deleted the insn pointed to by LOG_LINKS. Try
4021 scanning backward to find where the register is set. */
4022 for (scan = PREV_INSN (insn);
4023 scan && GET_CODE (scan) != CODE_LABEL;
4024 scan = PREV_INSN (scan))
4025 {
9204e736 4026 if (! INSN_P (scan))
90e84010 4027 continue;
4028
4029 if (! reg_mentioned_p (reg, scan))
4030 continue;
4031
4032 if (noncall_uses_reg (reg, scan, &set))
4033 break;
4034
4035 if (set)
4036 {
4037 link = scan;
4038 break;
4039 }
4040 }
4041 }
4042
4043 if (! link)
4044 continue;
4045
4046 /* The register is set at LINK. */
4047
4048 /* We can only optimize the function call if the register is
4049 being set to a symbol. In theory, we could sometimes
4050 optimize calls to a constant location, but the assembler
4051 and linker do not support that at present. */
4052 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
4053 && GET_CODE (SET_SRC (set)) != LABEL_REF)
4054 continue;
4055
4056 /* Scan forward from LINK to the place where REG dies, and
4057 make sure that the only insns which use REG are
4058 themselves function calls. */
4059
4fa2e8b8 4060 /* ??? This doesn't work for call targets that were allocated
4061 by reload, since there may not be a REG_DEAD note for the
4062 register. */
4063
90e84010 4064 dies = NULL_RTX;
4065 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
4066 {
4067 rtx scanset;
4068
4fa2e8b8 4069 /* Don't try to trace forward past a CODE_LABEL if we haven't
4070 seen INSN yet. Ordinarily, we will only find the setting insn
4071 in LOG_LINKS if it is in the same basic block. However,
4072 cross-jumping can insert code labels in between the load and
4073 the call, and can result in situations where a single call
4074 insn may have two targets depending on where we came from. */
4075
4076 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
4077 break;
4078
9204e736 4079 if (! INSN_P (scan))
90e84010 4080 continue;
4081
4082 /* Don't try to trace forward past a JUMP. To optimize
4083 safely, we would have to check that all the
4fa2e8b8 4084 instructions at the jump destination did not use REG. */
90e84010 4085
4fa2e8b8 4086 if (GET_CODE (scan) == JUMP_INSN)
90e84010 4087 break;
4088
4089 if (! reg_mentioned_p (reg, scan))
4090 continue;
4091
4092 if (noncall_uses_reg (reg, scan, &scanset))
4093 break;
4094
4095 if (scan == insn)
4096 foundinsn = 1;
4097
881ffd32 4098 if (scan != insn
4099 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
90e84010 4100 {
4101 /* There is a function call to this register other
4102 than the one we are checking. If we optimize
4103 this call, we need to rescan again below. */
4104 rescan = 1;
4105 }
4106
4107 /* ??? We shouldn't have to worry about SCANSET here.
4108 We should just be able to check for a REG_DEAD note
4109 on a function call. However, the REG_DEAD notes are
4110 apparently not dependable around libcalls; c-torture
4111 execute/920501-2 is a test case. If SCANSET is set,
4112 then this insn sets the register, so it must have
4113 died earlier. Unfortunately, this will only handle
4114 the cases in which the register is, in fact, set in a
4115 later insn. */
4116
4117 /* ??? We shouldn't have to use FOUNDINSN here.
4118 However, the LOG_LINKS fields are apparently not
4119 entirely reliable around libcalls;
4120 newlib/libm/math/e_pow.c is a test case. Sometimes
4121 an insn will appear in LOG_LINKS even though it is
9df03d69 4122 not the most recent insn which sets the register. */
90e84010 4123
4124 if (foundinsn
4125 && (scanset
4126 || find_reg_note (scan, REG_DEAD, reg)))
4127 {
4128 dies = scan;
4129 break;
4130 }
4131 }
4132
4133 if (! dies)
4134 {
4135 /* Either there was a branch, or some insn used REG
4136 other than as a function call address. */
4137 continue;
4138 }
4139
4140 /* Create a code label, and put it in a REG_LABEL note on
4141 the insn which sets the register, and on each call insn
4142 which uses the register. In final_prescan_insn we look
4143 for the REG_LABEL notes, and output the appropriate label
4144 or pseudo-op. */
4145
4146 label = gen_label_rtx ();
4bb30577 4147 REG_NOTES (link) = gen_rtx_INSN_LIST (REG_LABEL, label,
7014838c 4148 REG_NOTES (link));
4bb30577 4149 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, label,
7014838c 4150 REG_NOTES (insn));
90e84010 4151 if (rescan)
4152 {
4153 scan = link;
4154 do
4155 {
881ffd32 4156 rtx reg2;
4157
90e84010 4158 scan = NEXT_INSN (scan);
4159 if (scan != insn
881ffd32 4160 && ((GET_CODE (scan) == CALL_INSN
4161 && reg_mentioned_p (reg, scan))
4162 || ((reg2 = sfunc_uses_reg (scan))
4163 && REGNO (reg2) == REGNO (reg))))
7014838c 4164 REG_NOTES (scan)
4bb30577 4165 = gen_rtx_INSN_LIST (REG_LABEL, label, REG_NOTES (scan));
90e84010 4166 }
4167 while (scan != dies);
4168 }
4169 }
4170 }
4171
9eaab178 4172 if (TARGET_SH2)
4173 fixup_addr_diff_vecs (first);
8ded0752 4174
4175 if (optimize)
4176 {
8ded0752 4177 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
4178 shorten_branches (first);
4179 }
90e84010 4180 /* Scan the function looking for move instructions which have to be
4181 changed to pc-relative loads and insert the literal tables. */
4182
8ded0752 4183 mdep_reorg_phase = SH_FIXUP_PCLOAD;
4184 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
97595bfd 4185 {
8ded0752 4186 if (mova_p (insn))
4187 {
51dade95 4188 /* ??? basic block reordering can move a switch table dispatch
4189 below the switch table. Check if that has happened.
4190 We only have the addresses available when optimizing; but then,
4191 this check shouldn't be needed when not optimizing. */
4192 rtx label_ref = XVECEXP (SET_SRC (PATTERN (insn)), 0, 0);
4193 if (optimize
4194 && (INSN_ADDRESSES (INSN_UID (insn))
4195 > INSN_ADDRESSES (INSN_UID (XEXP (label_ref, 0)))))
4196 {
4197 /* Change the mova into a load.
4198 broken_move will then return true for it. */
4199 fixup_mova (insn);
4200 }
4201 else if (! num_mova++)
8ded0752 4202 mova = insn;
4203 }
4204 else if (GET_CODE (insn) == JUMP_INSN
4205 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
4206 && num_mova)
4207 {
4208 rtx scan;
4209 int total;
4210
4211 num_mova--;
4212
4213 /* Some code might have been inserted between the mova and
4214 its ADDR_DIFF_VEC. Check if the mova is still in range. */
4215 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
9eaab178 4216 total += get_attr_length (scan);
8ded0752 4217
4218 /* range of mova is 1020, add 4 because pc counts from address of
4219 second instruction after this one, subtract 2 in case pc is 2
4220 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
ad87de1e 4221 cancels out with alignment effects of the mova itself. */
8ded0752 4222 if (total > 1022)
4223 {
4224 /* Change the mova into a load, and restart scanning
4225 there. broken_move will then return true for mova. */
51dade95 4226 fixup_mova (mova);
8ded0752 4227 insn = mova;
4228 }
4229 }
51dade95 4230 if (broken_move (insn)
4231 || (GET_CODE (insn) == INSN
4232 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
97595bfd 4233 {
97595bfd 4234 rtx scan;
73401833 4235 /* Scan ahead looking for a barrier to stick the constant table
4236 behind. */
8ded0752 4237 rtx barrier = find_barrier (num_mova, mova, insn);
87ed74ef 4238 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
51dade95 4239 int need_aligned_label = 0;
47c009e5 4240
8ded0752 4241 if (num_mova && ! mova_p (mova))
4242 {
4243 /* find_barrier had to change the first mova into a
4244 pcload; thus, we have to start with this new pcload. */
4245 insn = mova;
4246 num_mova = 0;
4247 }
1504eb7e 4248 /* Now find all the moves between the points and modify them. */
97595bfd 4249 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
4250 {
8ded0752 4251 if (GET_CODE (scan) == CODE_LABEL)
4252 last_float = 0;
51dade95 4253 if (GET_CODE (scan) == INSN
4254 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
4255 need_aligned_label = 1;
97595bfd 4256 if (broken_move (scan))
4257 {
00f87557 4258 rtx *patp = &PATTERN (scan), pat = *patp;
4259 rtx src, dst;
97595bfd 4260 rtx lab;
97595bfd 4261 rtx newsrc;
00f87557 4262 enum machine_mode mode;
4263
4264 if (GET_CODE (pat) == PARALLEL)
4265 patp = &XVECEXP (pat, 0, 0), pat = *patp;
4266 src = SET_SRC (pat);
4267 dst = SET_DEST (pat);
4268 mode = GET_MODE (dst);
97595bfd 4269
1b61190c 4270 if (mode == SImode && hi_const (src)
4271 && REGNO (dst) != FPUL_REG)
97595bfd 4272 {
59a5a83f 4273 int offset = 0;
73401833 4274
97595bfd 4275 mode = HImode;
f3d93547 4276 while (GET_CODE (dst) == SUBREG)
59a5a83f 4277 {
701e46d0 4278 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
4279 GET_MODE (SUBREG_REG (dst)),
4280 SUBREG_BYTE (dst),
4281 GET_MODE (dst));
59a5a83f 4282 dst = SUBREG_REG (dst);
4283 }
7014838c 4284 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
97595bfd 4285 }
e2142b04 4286 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
8ded0752 4287 {
c961a48b 4288 /* This must be an insn that clobbers r0. */
adbf1ac5 4289 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
4290 XVECLEN (PATTERN (scan), 0)
4291 - 1);
4292 rtx clobber = *clobberp;
c961a48b 4293
4294 if (GET_CODE (clobber) != CLOBBER
4295 || ! rtx_equal_p (XEXP (clobber, 0), r0_rtx))
4296 abort ();
4297
8ded0752 4298 if (last_float
4299 && reg_set_between_p (r0_rtx, last_float_move, scan))
4300 last_float = 0;
c5ea35c4 4301 if (last_float
4302 && TARGET_SHCOMPACT
4303 && GET_MODE_SIZE (mode) != 4
4304 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
4305 last_float = 0;
8ded0752 4306 lab = add_constant (src, mode, last_float);
4307 if (lab)
4308 emit_insn_before (gen_mova (lab), scan);
4309 else
c961a48b 4310 {
4311 /* There will be a REG_UNUSED note for r0 on
4312 LAST_FLOAT_MOVE; we have to change it to REG_INC,
4313 lest reorg:mark_target_live_regs will not
4314 consider r0 to be used, and we end up with delay
d06d4df0 4315 slot insn in front of SCAN that clobbers r0. */
c961a48b 4316 rtx note
4317 = find_regno_note (last_float_move, REG_UNUSED, 0);
4318
46bc3e81 4319 /* If we are not optimizing, then there may not be
4320 a note. */
4321 if (note)
4322 PUT_MODE (note, REG_INC);
c961a48b 4323
4324 *last_float_addr = r0_inc_rtx;
4325 }
8ded0752 4326 last_float_move = scan;
4327 last_float = src;
407d9153 4328 newsrc = gen_rtx_MEM (mode,
b7dbbdb2 4329 (((TARGET_SH4 && ! TARGET_FMOVD)
1b61190c 4330 || REGNO (dst) == FPUL_REG)
8ded0752 4331 ? r0_inc_rtx
4332 : r0_rtx));
4333 last_float_addr = &XEXP (newsrc, 0);
c961a48b 4334
4335 /* Remove the clobber of r0. */
adbf1ac5 4336 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
4337 gen_rtx_SCRATCH (Pmode));
944d7a23 4338 RTX_UNCHANGING_P (newsrc) = 1;
8ded0752 4339 }
0abf894c 4340 /* This is a mova needing a label. Create it. */
393fac7b 4341 else if (GET_CODE (src) == UNSPEC
4342 && XINT (src, 1) == UNSPEC_MOVA
4343 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
0abf894c 4344 {
393fac7b 4345 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
0abf894c 4346 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
f4dba476 4347 newsrc = gen_rtx_UNSPEC (SImode,
a5bd34f1 4348 gen_rtvec (1, newsrc),
4349 UNSPEC_MOVA);
0abf894c 4350 }
8ded0752 4351 else
4352 {
4353 lab = add_constant (src, mode, 0);
7014838c 4354 newsrc = gen_rtx_MEM (mode,
4355 gen_rtx_LABEL_REF (VOIDmode, lab));
944d7a23 4356 RTX_UNCHANGING_P (newsrc) = 1;
8ded0752 4357 }
7014838c 4358 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
00f87557 4359 INSN_CODE (scan) = -1;
97595bfd 4360 }
4361 }
51dade95 4362 dump_table (need_aligned_label ? insn : 0, barrier);
8ded0752 4363 insn = barrier;
97595bfd 4364 }
4365 }
8ded0752 4366
4367 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
47fc0706 4368 INSN_ADDRESSES_FREE ();
8ded0752 4369 split_branches (first);
4370
4371 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
f747aa2d 4372 also has an effect on the register that holds the address of the sfunc.
8ded0752 4373 Insert an extra dummy insn in front of each sfunc that pretends to
4374 use this register. */
4375 if (flag_delayed_branch)
4376 {
4377 for (insn = first; insn; insn = NEXT_INSN (insn))
4378 {
4379 rtx reg = sfunc_uses_reg (insn);
4380
4381 if (! reg)
4382 continue;
4383 emit_insn_before (gen_use_sfunc_addr (reg), insn);
4384 }
4385 }
1b61190c 4386#if 0
4387 /* fpscr is not actually a user variable, but we pretend it is for the
4388 sake of the previous optimization passes, since we want it handled like
18862b5a 4389 one. However, we don't have any debugging information for it, so turn
1b61190c 4390 it into a non-user variable now. */
4391 if (TARGET_SH4)
4392 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
4393#endif
8ded0752 4394 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
4395}
4396
4397int
04f04b72 4398get_dest_uid (rtx label, int max_uid)
8ded0752 4399{
4400 rtx dest = next_real_insn (label);
4401 int dest_uid;
4402 if (! dest)
4403 /* This can happen for an undefined label. */
4404 return 0;
4405 dest_uid = INSN_UID (dest);
4406 /* If this is a newly created branch redirection blocking instruction,
4407 we cannot index the branch_uid or insn_addresses arrays with its
4408 uid. But then, we won't need to, because the actual destination is
4409 the following branch. */
4410 while (dest_uid >= max_uid)
4411 {
4412 dest = NEXT_INSN (dest);
4413 dest_uid = INSN_UID (dest);
4414 }
4415 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
4416 return 0;
4417 return dest_uid;
4418}
4419
4420/* Split condbranches that are out of range. Also add clobbers for
4421 scratch registers that are needed in far jumps.
4422 We do this before delay slot scheduling, so that it can take our
4423 newly created instructions into account. It also allows us to
4424 find branches with common targets more easily. */
4425
4426static void
04f04b72 4427split_branches (rtx first)
8ded0752 4428{
4429 rtx insn;
4430 struct far_branch **uid_branch, *far_branch_list = 0;
4431 int max_uid = get_max_uid ();
4432
4433 /* Find out which branches are out of range. */
8ded0752 4434 shorten_branches (first);
4435
4436 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
8e547276 4437 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
8ded0752 4438
4439 for (insn = first; insn; insn = NEXT_INSN (insn))
9204e736 4440 if (! INSN_P (insn))
8ded0752 4441 continue;
4442 else if (INSN_DELETED_P (insn))
4443 {
4444 /* Shorten_branches would split this instruction again,
4445 so transform it into a note. */
4446 PUT_CODE (insn, NOTE);
4447 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4448 NOTE_SOURCE_FILE (insn) = 0;
4449 }
4450 else if (GET_CODE (insn) == JUMP_INSN
4451 /* Don't mess with ADDR_DIFF_VEC */
4452 && (GET_CODE (PATTERN (insn)) == SET
4453 || GET_CODE (PATTERN (insn)) == RETURN))
4454 {
4455 enum attr_type type = get_attr_type (insn);
4456 if (type == TYPE_CBRANCH)
4457 {
4458 rtx next, beyond;
4459
4460 if (get_attr_length (insn) > 4)
4461 {
4462 rtx src = SET_SRC (PATTERN (insn));
8ded0752 4463 rtx olabel = XEXP (XEXP (src, 1), 0);
47fc0706 4464 int addr = INSN_ADDRESSES (INSN_UID (insn));
8ded0752 4465 rtx label = 0;
4466 int dest_uid = get_dest_uid (olabel, max_uid);
4467 struct far_branch *bp = uid_branch[dest_uid];
4468
4469 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
40df6fd4 4470 the label if the LABEL_NUSES count drops to zero. There is
8ded0752 4471 always a jump_optimize pass that sets these values, but it
4472 proceeds to delete unreferenced code, and then if not
ad87de1e 4473 optimizing, to un-delete the deleted instructions, thus
8ded0752 4474 leaving labels with too low uses counts. */
4475 if (! optimize)
4476 {
4477 JUMP_LABEL (insn) = olabel;
4478 LABEL_NUSES (olabel)++;
4479 }
4480 if (! bp)
4481 {
4482 bp = (struct far_branch *) alloca (sizeof *bp);
4483 uid_branch[dest_uid] = bp;
4484 bp->prev = far_branch_list;
4485 far_branch_list = bp;
4486 bp->far_label
4487 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
4488 LABEL_NUSES (bp->far_label)++;
4489 }
4490 else
4491 {
4492 label = bp->near_label;
4493 if (! label && bp->address - addr >= CONDJUMP_MIN)
4494 {
4495 rtx block = bp->insert_place;
4496
4497 if (GET_CODE (PATTERN (block)) == RETURN)
4498 block = PREV_INSN (block);
4499 else
4500 block = gen_block_redirect (block,
4501 bp->address, 2);
4502 label = emit_label_after (gen_label_rtx (),
4503 PREV_INSN (block));
4504 bp->near_label = label;
4505 }
4506 else if (label && ! NEXT_INSN (label))
17bec211 4507 {
4508 if (addr + 2 - bp->address <= CONDJUMP_MAX)
4509 bp->insert_place = insn;
4510 else
4511 gen_far_branch (bp);
4512 }
8ded0752 4513 }
4514 if (! label
b7dbbdb2 4515 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
8ded0752 4516 {
4517 bp->near_label = label = gen_label_rtx ();
4518 bp->insert_place = insn;
4519 bp->address = addr;
4520 }
5e20801c 4521 if (! redirect_jump (insn, label, 1))
8ded0752 4522 abort ();
4523 }
4524 else
4525 {
4526 /* get_attr_length (insn) == 2 */
4527 /* Check if we have a pattern where reorg wants to redirect
4528 the branch to a label from an unconditional branch that
4529 is too far away. */
4530 /* We can't use JUMP_LABEL here because it might be undefined
4531 when not optimizing. */
9eaab178 4532 /* A syntax error might cause beyond to be NULL_RTX. */
8ded0752 4533 beyond
4534 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
4535 0));
4536
9eaab178 4537 if (beyond
4538 && (GET_CODE (beyond) == JUMP_INSN
b1060622 4539 || ((beyond = next_active_insn (beyond))
4540 && GET_CODE (beyond) == JUMP_INSN))
8ded0752 4541 && GET_CODE (PATTERN (beyond)) == SET
adbcc7c4 4542 && recog_memoized (beyond) == CODE_FOR_jump_compact
47fc0706 4543 && ((INSN_ADDRESSES
4544 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
30435bf8 4545 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
8ded0752 4546 > 252 + 258 + 2))
4547 gen_block_redirect (beyond,
47fc0706 4548 INSN_ADDRESSES (INSN_UID (beyond)), 1);
8ded0752 4549 }
4550
4551 next = next_active_insn (insn);
4552
4553 if ((GET_CODE (next) == JUMP_INSN
4554 || GET_CODE (next = next_active_insn (next)) == JUMP_INSN)
4555 && GET_CODE (PATTERN (next)) == SET
adbcc7c4 4556 && recog_memoized (next) == CODE_FOR_jump_compact
47fc0706 4557 && ((INSN_ADDRESSES
4558 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
30435bf8 4559 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
8ded0752 4560 > 252 + 258 + 2))
47fc0706 4561 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
8ded0752 4562 }
4563 else if (type == TYPE_JUMP || type == TYPE_RETURN)
4564 {
47fc0706 4565 int addr = INSN_ADDRESSES (INSN_UID (insn));
8ded0752 4566 rtx far_label = 0;
4567 int dest_uid = 0;
4568 struct far_branch *bp;
4569
4570 if (type == TYPE_JUMP)
4571 {
4572 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
4573 dest_uid = get_dest_uid (far_label, max_uid);
4574 if (! dest_uid)
4575 {
4576 /* Parse errors can lead to labels outside
4577 the insn stream. */
4578 if (! NEXT_INSN (far_label))
4579 continue;
4580
4581 if (! optimize)
4582 {
4583 JUMP_LABEL (insn) = far_label;
4584 LABEL_NUSES (far_label)++;
4585 }
5e20801c 4586 redirect_jump (insn, NULL_RTX, 1);
8ded0752 4587 far_label = 0;
4588 }
4589 }
4590 bp = uid_branch[dest_uid];
4591 if (! bp)
4592 {
4593 bp = (struct far_branch *) alloca (sizeof *bp);
4594 uid_branch[dest_uid] = bp;
4595 bp->prev = far_branch_list;
4596 far_branch_list = bp;
4597 bp->near_label = 0;
4598 bp->far_label = far_label;
4599 if (far_label)
4600 LABEL_NUSES (far_label)++;
4601 }
4602 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
4603 if (addr - bp->address <= CONDJUMP_MAX)
4604 emit_label_after (bp->near_label, PREV_INSN (insn));
4605 else
4606 {
4607 gen_far_branch (bp);
4608 bp->near_label = 0;
4609 }
4610 else
4611 bp->near_label = 0;
4612 bp->address = addr;
4613 bp->insert_place = insn;
4614 if (! far_label)
4615 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
4616 else
4617 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
4618 }
4619 }
4620 /* Generate all pending far branches,
4621 and free our references to the far labels. */
4622 while (far_branch_list)
4623 {
4624 if (far_branch_list->near_label
4625 && ! NEXT_INSN (far_branch_list->near_label))
4626 gen_far_branch (far_branch_list);
4627 if (optimize
4628 && far_branch_list->far_label
4629 && ! --LABEL_NUSES (far_branch_list->far_label))
4630 delete_insn (far_branch_list->far_label);
4631 far_branch_list = far_branch_list->prev;
4632 }
bd967f88 4633
4634 /* Instruction length information is no longer valid due to the new
4635 instructions that have been generated. */
4636 init_insn_lengths ();
47c009e5 4637}
4638
73401833 4639/* Dump out instruction addresses, which is useful for debugging the
90e84010 4640 constant pool table stuff.
4641
4642 If relaxing, output the label and pseudo-ops used to link together
4643 calls and the instruction which set the registers. */
73401833 4644
73401833 4645/* ??? The addresses printed by this routine for insns are nonsense for
4646 insns which are inside of a sequence where none of the inner insns have
4647 variable length. This is because the second pass of shorten_branches
4648 does not bother to update them. */
97595bfd 4649
2e3d4844 4650void
04f04b72 4651final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
4652 int noperands ATTRIBUTE_UNUSED)
47c009e5 4653{
73401833 4654 if (TARGET_DUMPISIZE)
47fc0706 4655 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
90e84010 4656
4657 if (TARGET_RELAX)
4658 {
4659 rtx note;
4660
4661 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
4662 if (note)
4663 {
4664 rtx pattern;
4665
4666 pattern = PATTERN (insn);
4667 if (GET_CODE (pattern) == PARALLEL)
4668 pattern = XVECEXP (pattern, 0, 0);
4669 if (GET_CODE (pattern) == CALL
4670 || (GET_CODE (pattern) == SET
881ffd32 4671 && (GET_CODE (SET_SRC (pattern)) == CALL
4672 || get_attr_type (insn) == TYPE_SFUNC)))
64916c76 4673 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
4674 CODE_LABEL_NUMBER (XEXP (note, 0)));
90e84010 4675 else if (GET_CODE (pattern) == SET)
805e22b2 4676 (*targetm.asm_out.internal_label) (asm_out_file, "L",
90e84010 4677 CODE_LABEL_NUMBER (XEXP (note, 0)));
4678 else
4679 abort ();
4680 }
4681 }
97595bfd 4682}
47c009e5 4683
73401833 4684/* Dump out any constants accumulated in the final pass. These will
3398e91d 4685 only be labels. */
47c009e5 4686
b7dbbdb2 4687const char *
04f04b72 4688output_jump_label_table (void)
97595bfd 4689{
73401833 4690 int i;
4691
4692 if (pool_size)
4693 {
4694 fprintf (asm_out_file, "\t.align 2\n");
4695 for (i = 0; i < pool_size; i++)
4696 {
4697 pool_node *p = &pool_vector[i];
4698
805e22b2 4699 (*targetm.asm_out.internal_label) (asm_out_file, "L",
73401833 4700 CODE_LABEL_NUMBER (p->label));
4701 output_asm_insn (".long %O0", &p->value);
4702 }
4703 pool_size = 0;
4704 }
47c009e5 4705
73401833 4706 return "";
4707}
4708\f
4709/* A full frame looks like:
1504eb7e 4710
4711 arg-5
4712 arg-4
4713 [ if current_function_anonymous_args
4714 arg-3
4715 arg-2
4716 arg-1
4717 arg-0 ]
4718 saved-fp
4719 saved-r10
4720 saved-r11
4721 saved-r12
4722 saved-pr
4723 local-n
4724 ..
4725 local-1
4726 local-0 <- fp points here. */
2e3d4844 4727
73401833 4728/* Number of bytes pushed for anonymous args, used to pass information
4729 between expand_prologue and expand_epilogue. */
4730
41fafa66 4731/* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
4732 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
66209063 4733 for an epilogue and a negative value means that it's for a sibcall
4734 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
4735 all the registers that are about to be restored, and hence dead. */
73401833 4736
4737static void
41fafa66 4738output_stack_adjust (int size, rtx reg, int epilogue_p,
4739 HARD_REG_SET *live_regs_mask)
73401833 4740{
41fafa66 4741 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
73401833 4742 if (size)
4743 {
87e19636 4744 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4745
4746 if (size % align)
4747 abort ();
4748
4749 if (CONST_OK_FOR_ADD (size))
363600c8 4750 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
b9d4bd5a 4751 /* Try to do it with two partial adjustments; however, we must make
4752 sure that the stack is properly aligned at all times, in case
9df03d69 4753 an interrupt occurs between the two partial adjustments. */
87e19636 4754 else if (CONST_OK_FOR_ADD (size / 2 & -align)
4755 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
b9d4bd5a 4756 {
363600c8 4757 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
4758 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
b9d4bd5a 4759 }
4760 else
73401833 4761 {
b9d4bd5a 4762 rtx const_reg;
363600c8 4763 rtx insn;
41fafa66 4764 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
4765 int i;
b9d4bd5a 4766
4767 /* If TEMP is invalid, we could temporarily save a general
4768 register to MACL. However, there is currently no need
4769 to handle this case, so just abort when we see it. */
66209063 4770 if (epilogue_p < 0
4771 || current_function_interrupt
41fafa66 4772 || ! call_used_regs[temp] || fixed_regs[temp])
4773 temp = -1;
66209063 4774 if (temp < 0 && ! current_function_interrupt
4775 && (TARGET_SHMEDIA || epilogue_p >= 0))
41fafa66 4776 {
4777 HARD_REG_SET temps;
4778 COPY_HARD_REG_SET (temps, call_used_reg_set);
4779 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
66209063 4780 if (epilogue_p > 0)
41fafa66 4781 {
66209063 4782 int nreg = 0;
4783 if (current_function_return_rtx)
4784 {
4785 enum machine_mode mode;
4786 mode = GET_MODE (current_function_return_rtx);
4787 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
4788 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
4789 }
4790 for (i = 0; i < nreg; i++)
41fafa66 4791 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
4792 if (current_function_calls_eh_return)
4793 {
4794 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
4795 for (i = 0; i <= 3; i++)
4796 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
4797 }
4798 }
66209063 4799 if (TARGET_SHMEDIA && epilogue_p < 0)
4800 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
4801 CLEAR_HARD_REG_BIT (temps, i);
4802 if (epilogue_p <= 0)
41fafa66 4803 {
4804 for (i = FIRST_PARM_REG;
4805 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
4806 CLEAR_HARD_REG_BIT (temps, i);
4ee9c684 4807 if (cfun->static_chain_decl != NULL)
41fafa66 4808 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
4809 }
4810 temp = scavenge_reg (&temps);
4811 }
4812 if (temp < 0 && live_regs_mask)
4813 temp = scavenge_reg (live_regs_mask);
b9d4bd5a 4814 if (temp < 0)
66209063 4815 {
4816 /* If we reached here, the most likely case is the (sibcall)
4817 epilogue for non SHmedia. Put a special push/pop sequence
4818 for such case as the last resort. This looks lengthy but
4819 would not be problem because it seems to be very rare. */
4820 if (! TARGET_SHMEDIA && epilogue_p)
4821 {
4822 rtx adj_reg, tmp_reg, mem;
4823
4824 /* ??? There is still the slight possibility that r4 or r5
4825 have been reserved as fixed registers or assigned as
4826 global registers, and they change during an interrupt.
4827 There are possible ways to handle this:
4828 - If we are adjusting the frame pointer (r14), we can do
4829 with a single temp register and an ordinary push / pop
4830 on the stack.
4831 - Grab any call-used or call-saved registers (i.e. not
4832 fixed or globals) for the temps we need. We might
4833 also grab r14 if we are adjusting the stack pointer.
4834 If we can't find enough available registers, issue
4835 a diagnostic and abort - the user must have reserved
4836 way too many registers.
4837 But since all this is rather unlikely to happen and
4838 would require extra testing, we just abort if r4 / r5
4839 are not available. */
4840 if (fixed_regs[4] || fixed_regs[5]
4841 || global_regs[4] || global_regs[5])
4842 abort ();
4843
4844 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
4845 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
4846 emit_move_insn (gen_rtx_MEM (Pmode, reg), adj_reg);
4847 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
4848 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
4849 mem = gen_rtx_MEM (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
4850 emit_move_insn (mem, tmp_reg);
4851 emit_move_insn (tmp_reg, gen_rtx_MEM (Pmode, reg));
4852 mem = gen_rtx_MEM (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
4853 emit_move_insn (mem, tmp_reg);
4854 emit_move_insn (reg, adj_reg);
4855 mem = gen_rtx_MEM (Pmode, gen_rtx_POST_INC (Pmode, reg));
4856 emit_move_insn (adj_reg, mem);
4857 mem = gen_rtx_MEM (Pmode, gen_rtx_POST_INC (Pmode, reg));
4858 emit_move_insn (tmp_reg, mem);
4859 return;
4860 }
4861 else
4862 abort ();
4863 }
87e19636 4864 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
b9d4bd5a 4865
4866 /* If SIZE is negative, subtract the positive value.
4867 This sometimes allows a constant pool entry to be shared
4868 between prologue and epilogue code. */
4869 if (size < 0)
51143b47 4870 {
87e19636 4871 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
363600c8 4872 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
51143b47 4873 }
4874 else
4875 {
87e19636 4876 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
363600c8 4877 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
51143b47 4878 }
41fafa66 4879 if (! epilogue_p)
363600c8 4880 REG_NOTES (insn)
4881 = (gen_rtx_EXPR_LIST
4882 (REG_FRAME_RELATED_EXPR,
4883 gen_rtx_SET (VOIDmode, reg,
4884 gen_rtx_PLUS (SImode, reg, GEN_INT (size))),
4885 REG_NOTES (insn)));
73401833 4886 }
73401833 4887 }
4888}
4889
363600c8 4890static rtx
04f04b72 4891frame_insn (rtx x)
363600c8 4892{
4893 x = emit_insn (x);
4894 RTX_FRAME_RELATED_P (x) = 1;
4895 return x;
4896}
4897
73401833 4898/* Output RTL to push register RN onto the stack. */
4899
363600c8 4900static rtx
04f04b72 4901push (int rn)
73401833 4902{
4903 rtx x;
1b61190c 4904 if (rn == FPUL_REG)
4905 x = gen_push_fpul ();
88b7f6c6 4906 else if (rn == FPSCR_REG)
4907 x = gen_push_fpscr ();
1b61190c 4908 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
e2142b04 4909 && FP_OR_XD_REGISTER_P (rn))
1b61190c 4910 {
e2142b04 4911 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
acda5809 4912 return NULL_RTX;
7014838c 4913 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
1b61190c 4914 }
87ed74ef 4915 else if (TARGET_SH2E && FP_REGISTER_P (rn))
7014838c 4916 x = gen_push_e (gen_rtx_REG (SFmode, rn));
b00564da 4917 else
7014838c 4918 x = gen_push (gen_rtx_REG (SImode, rn));
b00564da 4919
363600c8 4920 x = frame_insn (x);
7014838c 4921 REG_NOTES (x)
4922 = gen_rtx_EXPR_LIST (REG_INC,
4923 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
363600c8 4924 return x;
73401833 4925}
4926
4927/* Output RTL to pop register RN from the stack. */
4928
4929static void
04f04b72 4930pop (int rn)
73401833 4931{
4932 rtx x;
1b61190c 4933 if (rn == FPUL_REG)
4934 x = gen_pop_fpul ();
88b7f6c6 4935 else if (rn == FPSCR_REG)
4936 x = gen_pop_fpscr ();
1b61190c 4937 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
e2142b04 4938 && FP_OR_XD_REGISTER_P (rn))
1b61190c 4939 {
e2142b04 4940 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
1b61190c 4941 return;
7014838c 4942 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
1b61190c 4943 }
87ed74ef 4944 else if (TARGET_SH2E && FP_REGISTER_P (rn))
7014838c 4945 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
b00564da 4946 else
7014838c 4947 x = gen_pop (gen_rtx_REG (SImode, rn));
b00564da 4948
8ded0752 4949 x = emit_insn (x);
7014838c 4950 REG_NOTES (x)
4951 = gen_rtx_EXPR_LIST (REG_INC,
4952 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
73401833 4953}
4954
8ded0752 4955/* Generate code to push the regs specified in the mask. */
73401833 4956
4957static void
04f04b72 4958push_regs (HARD_REG_SET *mask, int interrupt_handler)
73401833 4959{
4960 int i;
36a2dfdb 4961 int skip_fpscr = 0;
73401833 4962
8ded0752 4963 /* Push PR last; this gives better latencies after the prologue, and
4964 candidates for the return delay slot when there are no general
4965 registers pushed. */
87e19636 4966 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
36a2dfdb 4967 {
4968 /* If this is an interrupt handler, and the SZ bit varies,
4969 and we have to push any floating point register, we need
4970 to switch to the correct precision first. */
4971 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
4972 && hard_regs_intersect_p (mask, &reg_class_contents[DF_REGS]))
4973 {
4974 HARD_REG_SET unsaved;
4975
4976 push (FPSCR_REG);
d767e27e 4977 COMPL_HARD_REG_SET (unsaved, *mask);
36a2dfdb 4978 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
4979 skip_fpscr = 1;
4980 }
4981 if (i != PR_REG
4982 && (i != FPSCR_REG || ! skip_fpscr)
4983 && TEST_HARD_REG_BIT (*mask, i))
4984 push (i);
4985 }
ed8483c0 4986 if (TEST_HARD_REG_BIT (*mask, PR_REG))
8ded0752 4987 push (PR_REG);
73401833 4988}
4989
8af3db02 4990/* Calculate how much extra space is needed to save all callee-saved
4991 target registers.
4992 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4993
4994static int
4995shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
4996{
4997 int reg;
4998 int stack_space = 0;
4999 int interrupt_handler = sh_cfun_interrupt_handler_p ();
5000
5001 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
5002 if ((! call_used_regs[reg] || interrupt_handler)
5003 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
5004 /* Leave space to save this target register on the stack,
ada8cf8b 5005 in case target register allocation wants to use it. */
8af3db02 5006 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5007 return stack_space;
5008}
5009
5010/* Decide whether we should reserve space for callee-save target registers,
5011 in case target register allocation wants to use them. REGS_SAVED is
5012 the space, in bytes, that is already required for register saves.
5013 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5014
5015static int
5016shmedia_reserve_space_for_target_registers_p (int regs_saved,
5017 HARD_REG_SET *live_regs_mask)
5018{
5019 if (optimize_size)
5020 return 0;
5021 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
5022}
5023
5024/* Decide how much space to reserve for callee-save target registers
5025 in case target register allocation wants to use them.
5026 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5027
5028static int
5029shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
5030{
5031 if (shmedia_space_reserved_for_target_registers)
5032 return shmedia_target_regs_stack_space (live_regs_mask);
5033 else
5034 return 0;
5035}
5036
73401833 5037/* Work out the registers which need to be saved, both as a mask and a
ed8483c0 5038 count of saved words. Return the count.
73401833 5039
5040 If doing a pragma interrupt function, then push all regs used by the
5041 function, and if we call another function (we can tell by looking at PR),
5042 make sure that all the regs it clobbers are safe too. */
5043
ed8483c0 5044static int
04f04b72 5045calc_live_regs (HARD_REG_SET *live_regs_mask)
73401833 5046{
5047 int reg;
8ded0752 5048 int count;
49f630e1 5049 int interrupt_handler;
41fafa66 5050 int pr_live, has_call;
49f630e1 5051
5df3d11f 5052 interrupt_handler = sh_cfun_interrupt_handler_p ();
73401833 5053
41fafa66 5054 CLEAR_HARD_REG_SET (*live_regs_mask);
36a2dfdb 5055 if (TARGET_SH4 && TARGET_FMOVD && interrupt_handler
5056 && regs_ever_live[FPSCR_REG])
5057 target_flags &= ~FPU_SINGLE_BIT;
1b61190c 5058 /* If we can save a lot of saves by switching to double mode, do that. */
36a2dfdb 5059 else if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE)
1b61190c 5060 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
5061 if (regs_ever_live[reg] && regs_ever_live[reg+1]
49f630e1 5062 && (! call_used_regs[reg] || (interrupt_handler && ! pragma_trapa))
1b61190c 5063 && ++count > 2)
5064 {
5065 target_flags &= ~FPU_SINGLE_BIT;
5066 break;
5067 }
0b1c30e1 5068 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
5069 knows how to use it. That means the pseudo originally allocated for
5070 the initial value can become the PR_MEDIA_REG hard register, as seen for
5071 execute/20010122-1.c:test9. */
5072 if (TARGET_SHMEDIA)
ca474d26 5073 /* ??? this function is called from initial_elimination_offset, hence we
5074 can't use the result of sh_media_register_for_return here. */
93ea47c4 5075 pr_live = sh_pr_n_sets ();
0b1c30e1 5076 else
5077 {
5078 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
5079 pr_live = (pr_initial
0a41c525 5080 ? (GET_CODE (pr_initial) != REG
5081 || REGNO (pr_initial) != (PR_REG))
5082 : regs_ever_live[PR_REG]);
ca474d26 5083 /* For Shcompact, if not optimizing, we end up with a memory reference
5084 using the return address pointer for __builtin_return_address even
5085 though there is no actual need to put the PR register on the stack. */
5086 pr_live |= regs_ever_live[RETURN_ADDRESS_POINTER_REGNUM];
0b1c30e1 5087 }
87e19636 5088 /* Force PR to be live if the prologue has to call the SHmedia
5089 argument decoder or register saver. */
5090 if (TARGET_SHCOMPACT
5091 && ((current_function_args_info.call_cookie
5092 & ~ CALL_COOKIE_RET_TRAMP (1))
5093 || current_function_has_nonlocal_label))
5094 pr_live = 1;
41fafa66 5095 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
8ded0752 5096 for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--)
73401833 5097 {
93ea47c4 5098 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
476444cc 5099 ? pr_live
5100 : (interrupt_handler && ! pragma_trapa)
8ded0752 5101 ? (/* Need to save all the regs ever live. */
5102 (regs_ever_live[reg]
5103 || (call_used_regs[reg]
5104 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
41fafa66 5105 && has_call)
5106 || (has_call && REGISTER_NATURAL_MODE (reg) == SImode
5107 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
8ded0752 5108 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
5109 && reg != RETURN_ADDRESS_POINTER_REGNUM
88b7f6c6 5110 && reg != T_REG && reg != GBR_REG
5111 /* Push fpscr only on targets which have FPU */
5112 && (reg != FPSCR_REG || TARGET_FPU_ANY))
8ded0752 5113 : (/* Only push those regs which are used and need to be saved. */
6977cd64 5114 (TARGET_SHCOMPACT
5115 && flag_pic
5116 && current_function_args_info.call_cookie
41fafa66 5117 && reg == (int) PIC_OFFSET_TABLE_REGNUM)
805e22b2 5118 || (regs_ever_live[reg] && ! call_used_regs[reg])
5119 || (current_function_calls_eh_return
41fafa66 5120 && (reg == (int) EH_RETURN_DATA_REGNO (0)
5121 || reg == (int) EH_RETURN_DATA_REGNO (1)
5122 || reg == (int) EH_RETURN_DATA_REGNO (2)
45550790 5123 || reg == (int) EH_RETURN_DATA_REGNO (3)))
5124 || ((reg == MACL_REG || reg == MACH_REG)
5125 && regs_ever_live[reg]
5126 && sh_cfun_attr_renesas_p ())
5127 ))
73401833 5128 {
ed8483c0 5129 SET_HARD_REG_BIT (*live_regs_mask, reg);
87e19636 5130 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5131
5132 if ((TARGET_SH4 || TARGET_SH5) && TARGET_FMOVD
5133 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
17bec211 5134 {
e2142b04 5135 if (FP_REGISTER_P (reg))
17bec211 5136 {
5137 if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
5138 {
ed8483c0 5139 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
87e19636 5140 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
17bec211 5141 }
5142 }
87e19636 5143 else if (XD_REGISTER_P (reg))
17bec211 5144 {
5145 /* Must switch to double mode to access these registers. */
5146 target_flags &= ~FPU_SINGLE_BIT;
17bec211 5147 }
5148 }
73401833 5149 }
5150 }
8af3db02 5151 /* If we have a target register optimization pass after prologue / epilogue
5152 threading, we need to assume all target registers will be live even if
5153 they aren't now. */
5154 if (flag_branch_target_load_optimize2
5155 && TARGET_SAVE_ALL_TARGET_REGS
5156 && shmedia_space_reserved_for_target_registers)
5157 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
5158 if ((! call_used_regs[reg] || interrupt_handler)
5159 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
5160 {
5161 SET_HARD_REG_BIT (*live_regs_mask, reg);
5162 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5163 }
41fafa66 5164 /* If this is an interrupt handler, we don't have any call-clobbered
5165 registers we can conveniently use for target register save/restore.
5166 Make sure we save at least one general purpose register when we need
5167 to save target registers. */
5168 if (interrupt_handler
5169 && hard_regs_intersect_p (live_regs_mask,
5170 &reg_class_contents[TARGET_REGS])
5171 && ! hard_regs_intersect_p (live_regs_mask,
5172 &reg_class_contents[GENERAL_REGS]))
5173 {
5174 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
5175 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
5176 }
73401833 5177
ed8483c0 5178 return count;
73401833 5179}
5180
5181/* Code to generate prologue and epilogue sequences */
47c009e5 5182
4aa67c38 5183/* PUSHED is the number of bytes that are being pushed on the
f10edf5a 5184 stack for register saves. Return the frame size, padded
5185 appropriately so that the stack stays properly aligned. */
9200a51c 5186static HOST_WIDE_INT
04f04b72 5187rounded_frame_size (int pushed)
9200a51c 5188{
5189 HOST_WIDE_INT size = get_frame_size ();
5190 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
5191
26576132 5192 return ((size + pushed + align - 1) & -align) - pushed;
9200a51c 5193}
5194
87e19636 5195/* Choose a call-clobbered target-branch register that remains
5196 unchanged along the whole function. We set it up as the return
5197 value in the prologue. */
5198int
04f04b72 5199sh_media_register_for_return (void)
87e19636 5200{
5201 int regno;
5202 int tr0_used;
5203
5204 if (! current_function_is_leaf)
5205 return -1;
41fafa66 5206 if (lookup_attribute ("interrupt_handler",
5207 DECL_ATTRIBUTES (current_function_decl)))
5208 return -1;
87e19636 5209
5210 tr0_used = flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
5211
5212 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
5213 if (call_used_regs[regno] && ! regs_ever_live[regno])
5214 return regno;
5215
5216 return -1;
5217}
5218
41fafa66 5219/* The maximum registers we need to save are:
5220 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
5221 - 32 floating point registers (for each pair, we save none,
5222 one single precision value, or a double precision value).
5223 - 8 target registers
5224 - add 1 entry for a delimiter. */
5225#define MAX_SAVED_REGS (62+32+8)
5226
5227typedef struct save_entry_s
5228{
5229 unsigned char reg;
5230 unsigned char mode;
5231 short offset;
5232} save_entry;
5233
5234#define MAX_TEMPS 4
5235
5236/* There will be a delimiter entry with VOIDmode both at the start and the
5237 end of a filled in schedule. The end delimiter has the offset of the
5238 save with the smallest (i.e. most negative) offset. */
5239typedef struct save_schedule_s
5240{
5241 save_entry entries[MAX_SAVED_REGS + 2];
5242 int temps[MAX_TEMPS+1];
5243} save_schedule;
5244
5245/* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
5246 use reverse order. Returns the last entry written to (not counting
5247 the delimiter). OFFSET_BASE is a number to be added to all offset
5248 entries. */
5249
5250static save_entry *
5251sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
5252 int offset_base)
5253{
5254 int align, i;
5255 save_entry *entry = schedule->entries;
5256 int tmpx = 0;
5257 int offset;
5258
5259 if (! current_function_interrupt)
5260 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
ca474d26 5261 if (call_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
41fafa66 5262 && ! FUNCTION_ARG_REGNO_P (i)
5263 && i != FIRST_RET_REG
4ee9c684 5264 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
41fafa66 5265 && ! (current_function_calls_eh_return
5266 && (i == EH_RETURN_STACKADJ_REGNO
d767e27e 5267 || ((unsigned) i <= EH_RETURN_DATA_REGNO (0)
5268 && (unsigned) i >= EH_RETURN_DATA_REGNO (3)))))
41fafa66 5269 schedule->temps[tmpx++] = i;
5270 entry->reg = -1;
5271 entry->mode = VOIDmode;
5272 entry->offset = offset_base;
5273 entry++;
5274 /* We loop twice: first, we save 8-byte aligned registers in the
5275 higher addresses, that are known to be aligned. Then, we
5276 proceed to saving 32-bit registers that don't need 8-byte
5277 alignment.
5278 If this is an interrupt function, all registers that need saving
5279 need to be saved in full. moreover, we need to postpone saving
5280 target registers till we have saved some general purpose registers
5281 we can then use as scratch registers. */
5282 offset = offset_base;
5283 for (align = 1; align >= 0; align--)
5284 {
5285 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
5286 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
5287 {
5288 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5289 int reg = i;
5290
5291 if (current_function_interrupt)
5292 {
5293 if (TARGET_REGISTER_P (i))
5294 continue;
5295 if (GENERAL_REGISTER_P (i))
5296 mode = DImode;
5297 }
5298 if (mode == SFmode && (i % 2) == 1
5299 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5300 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
5301 {
5302 mode = DFmode;
5303 i--;
5304 reg--;
5305 }
5306
5307 /* If we're doing the aligned pass and this is not aligned,
5308 or we're doing the unaligned pass and this is aligned,
5309 skip it. */
5310 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
5311 != align)
5312 continue;
5313
5314 if (current_function_interrupt
5315 && GENERAL_REGISTER_P (i)
5316 && tmpx < MAX_TEMPS)
5317 schedule->temps[tmpx++] = i;
5318
5319 offset -= GET_MODE_SIZE (mode);
5320 entry->reg = i;
5321 entry->mode = mode;
5322 entry->offset = offset;
5323 entry++;
5324 }
5325 if (align && current_function_interrupt)
5326 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
5327 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
5328 {
5329 offset -= GET_MODE_SIZE (DImode);
5330 entry->reg = i;
5331 entry->mode = DImode;
5332 entry->offset = offset;
5333 entry++;
5334 }
5335 }
5336 entry->reg = -1;
5337 entry->mode = VOIDmode;
5338 entry->offset = offset;
5339 schedule->temps[tmpx] = -1;
5340 return entry - 1;
5341}
5342
47c009e5 5343void
04f04b72 5344sh_expand_prologue (void)
47c009e5 5345{
ed8483c0 5346 HARD_REG_SET live_regs_mask;
0f021c78 5347 int d, i;
87e19636 5348 int d_rounding = 0;
1b61190c 5349 int save_flags = target_flags;
09a512b9 5350 int pretend_args;
47c009e5 5351
5df3d11f 5352 current_function_interrupt = sh_cfun_interrupt_handler_p ();
0d687b6d 5353
97595bfd 5354 /* We have pretend args if we had an object sent partially in registers
73401833 5355 and partially on the stack, e.g. a large structure. */
09a512b9 5356 pretend_args = current_function_pretend_args_size;
5357 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
5358 && (NPARM_REGS(SImode)
5359 > current_function_args_info.arg_count[(int) SH_ARG_INT]))
5360 pretend_args = 0;
5361 output_stack_adjust (-pretend_args
87e19636 5362 - current_function_args_info.stack_regs * 8,
41fafa66 5363 stack_pointer_rtx, 0, NULL);
47c009e5 5364
87708ea5 5365 if (TARGET_SHCOMPACT && flag_pic && current_function_args_info.call_cookie)
5366 /* We're going to use the PIC register to load the address of the
5367 incoming-argument decoder and/or of the return trampoline from
5368 the GOT, so make sure the PIC register is preserved and
5369 initialized. */
5370 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
5371
87e19636 5372 if (TARGET_SHCOMPACT
5373 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
5374 {
5375 int reg;
5376
5377 /* First, make all registers with incoming arguments that will
5378 be pushed onto the stack live, so that register renaming
5379 doesn't overwrite them. */
5380 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
5381 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info.call_cookie)
5382 >= NPARM_REGS (SImode) - reg)
5383 for (; reg < NPARM_REGS (SImode); reg++)
5384 emit_insn (gen_shcompact_preserve_incoming_args
5385 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
5386 else if (CALL_COOKIE_INT_REG_GET
5387 (current_function_args_info.call_cookie, reg) == 1)
5388 emit_insn (gen_shcompact_preserve_incoming_args
5389 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
5390
5391 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
5392 stack_pointer_rtx);
5393 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
5394 GEN_INT (current_function_args_info.call_cookie));
5395 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
5396 gen_rtx_REG (SImode, R0_REG));
5397 }
5398 else if (TARGET_SHMEDIA)
5399 {
5400 int tr = sh_media_register_for_return ();
5401
5402 if (tr >= 0)
5403 {
5404 rtx insn = emit_move_insn (gen_rtx_REG (DImode, tr),
5405 gen_rtx_REG (DImode, PR_MEDIA_REG));
5406
ca474d26 5407 /* ??? We should suppress saving pr when we don't need it, but this
5408 is tricky because of builtin_return_address. */
5409
87e19636 5410 /* If this function only exits with sibcalls, this copy
5411 will be flagged as dead. */
5412 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5413 const0_rtx,
5414 REG_NOTES (insn));
5415 }
5416 }
5417
bf622d7d 5418 /* Emit the code for SETUP_VARARGS. */
7ccc713a 5419 if (current_function_stdarg)
47c009e5 5420 {
09a512b9 5421 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8ded0752 5422 {
b00564da 5423 /* Push arg regs as if they'd been provided by caller in stack. */
5424 for (i = 0; i < NPARM_REGS(SImode); i++)
5425 {
5426 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
363600c8 5427 rtx insn;
5428
75c2fa85 5429 if (i >= (NPARM_REGS(SImode)
5430 - current_function_args_info.arg_count[(int) SH_ARG_INT]
5431 ))
b00564da 5432 break;
363600c8 5433 insn = push (rn);
5434 RTX_FRAME_RELATED_P (insn) = 0;
b00564da 5435 }
8ded0752 5436 }
47c009e5 5437 }
b00564da 5438
15cb1799 5439 /* If we're supposed to switch stacks at function entry, do so now. */
5440 if (sp_switch)
5441 emit_insn (gen_sp_switch_1 ());
5442
ed8483c0 5443 d = calc_live_regs (&live_regs_mask);
1b61190c 5444 /* ??? Maybe we could save some switching if we can move a mode switch
5445 that already happens to be at the function start into the prologue. */
36a2dfdb 5446 if (target_flags != save_flags && ! current_function_interrupt)
1b61190c 5447 emit_insn (gen_toggle_sz ());
420261ef 5448
87e19636 5449 if (TARGET_SH5)
5450 {
41fafa66 5451 int offset_base, offset;
5452 rtx r0 = NULL_RTX;
87e19636 5453 int offset_in_r0 = -1;
5454 int sp_in_r0 = 0;
8af3db02 5455 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
5456 int total_size, save_size;
41fafa66 5457 save_schedule schedule;
5458 save_entry *entry;
5459 int *tmp_pnt;
5460
5461 if (call_used_regs[R0_REG] && ! fixed_regs[R0_REG]
5462 && ! current_function_interrupt)
5463 r0 = gen_rtx_REG (Pmode, R0_REG);
8af3db02 5464
5465 /* D is the actual number of bytes that we need for saving registers,
5466 however, in initial_elimination_offset we have committed to using
5467 an additional TREGS_SPACE amount of bytes - in order to keep both
5468 addresses to arguments supplied by the caller and local variables
5469 valid, we must keep this gap. Place it between the incoming
5470 arguments and the actually saved registers in a bid to optimize
5471 locality of reference. */
5472 total_size = d + tregs_space;
5473 total_size += rounded_frame_size (total_size);
5474 save_size = total_size - rounded_frame_size (d);
5475 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
87e19636 5476 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8af3db02 5477 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
5478
5479 /* If adjusting the stack in a single step costs nothing extra, do so.
5480 I.e. either if a single addi is enough, or we need a movi anyway,
5481 and we don't exceed the maximum offset range (the test for the
5482 latter is conservative for simplicity). */
5483 if (TARGET_SHMEDIA
5484 && (CONST_OK_FOR_I10 (-total_size)
5485 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
5486 && total_size <= 2044)))
5487 d_rounding = total_size - save_size;
87e19636 5488
41fafa66 5489 offset_base = d + d_rounding;
8af3db02 5490
5491 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
41fafa66 5492 0, NULL);
87e19636 5493
41fafa66 5494 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
5495 tmp_pnt = schedule.temps;
5496 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
5497 {
5498 enum machine_mode mode = entry->mode;
5499 int reg = entry->reg;
5500 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
87e19636 5501
41fafa66 5502 offset = entry->offset;
87e19636 5503
41fafa66 5504 reg_rtx = gen_rtx_REG (mode, reg);
87e19636 5505
41fafa66 5506 mem_rtx = gen_rtx_MEM (mode,
5507 gen_rtx_PLUS (Pmode,
5508 stack_pointer_rtx,
5509 GEN_INT (offset)));
87e19636 5510
41fafa66 5511 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
87e19636 5512
41fafa66 5513 if (! r0)
5514 abort ();
5515 mem_rtx = NULL_RTX;
87e19636 5516
41fafa66 5517 try_pre_dec:
5518 do
5519 if (HAVE_PRE_DECREMENT
5520 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
5521 || mem_rtx == NULL_RTX
5522 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
5523 {
5524 pre_dec = gen_rtx_MEM (mode,
5525 gen_rtx_PRE_DEC (Pmode, r0));
87e19636 5526
41fafa66 5527 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
5528 pre_dec_ok);
87e19636 5529
41fafa66 5530 pre_dec = NULL_RTX;
87e19636 5531
41fafa66 5532 break;
87e19636 5533
41fafa66 5534 pre_dec_ok:
5535 mem_rtx = NULL_RTX;
5536 offset += GET_MODE_SIZE (mode);
5537 }
5538 while (0);
87e19636 5539
41fafa66 5540 if (mem_rtx != NULL_RTX)
5541 goto addr_ok;
87e19636 5542
41fafa66 5543 if (offset_in_r0 == -1)
5544 {
5545 emit_move_insn (r0, GEN_INT (offset));
5546 offset_in_r0 = offset;
5547 }
5548 else if (offset != offset_in_r0)
5549 {
5550 emit_move_insn (r0,
5551 gen_rtx_PLUS
5552 (Pmode, r0,
5553 GEN_INT (offset - offset_in_r0)));
5554 offset_in_r0 += offset - offset_in_r0;
5555 }
5556
5557 if (pre_dec != NULL_RTX)
5558 {
5559 if (! sp_in_r0)
87e19636 5560 {
5561 emit_move_insn (r0,
5562 gen_rtx_PLUS
41fafa66 5563 (Pmode, r0, stack_pointer_rtx));
5564 sp_in_r0 = 1;
87e19636 5565 }
87e19636 5566
41fafa66 5567 offset -= GET_MODE_SIZE (mode);
5568 offset_in_r0 -= GET_MODE_SIZE (mode);
87e19636 5569
41fafa66 5570 mem_rtx = pre_dec;
5571 }
5572 else if (sp_in_r0)
5573 mem_rtx = gen_rtx_MEM (mode, r0);
5574 else
5575 mem_rtx = gen_rtx_MEM (mode,
5576 gen_rtx_PLUS (Pmode,
5577 stack_pointer_rtx,
5578 r0));
5579
5580 /* We must not use an r0-based address for target-branch
5581 registers or for special registers without pre-dec
5582 memory addresses, since we store their values in r0
5583 first. */
5584 if (TARGET_REGISTER_P (reg)
5585 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5586 && mem_rtx != pre_dec))
5587 abort ();
5588
5589 addr_ok:
5590 if (TARGET_REGISTER_P (reg)
5591 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5592 && mem_rtx != pre_dec))
5593 {
5594 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
87e19636 5595
41fafa66 5596 emit_move_insn (tmp_reg, reg_rtx);
87e19636 5597
41fafa66 5598 if (REGNO (tmp_reg) == R0_REG)
5599 {
87e19636 5600 offset_in_r0 = -1;
5601 sp_in_r0 = 0;
41fafa66 5602 if (refers_to_regno_p (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0))
5603 abort ();
87e19636 5604 }
5605
41fafa66 5606 if (*++tmp_pnt <= 0)
5607 tmp_pnt = schedule.temps;
5608
5609 reg_rtx = tmp_reg;
87e19636 5610 }
41fafa66 5611 {
5612 rtx insn;
5613
5614 /* Mark as interesting for dwarf cfi generator */
5615 insn = emit_move_insn (mem_rtx, reg_rtx);
5616 RTX_FRAME_RELATED_P (insn) = 1;
5617
5618 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
5619 {
5620 rtx reg_rtx = gen_rtx_REG (mode, reg);
5621 rtx set, note_rtx;
5622 rtx mem_rtx = gen_rtx_MEM (mode,
5623 gen_rtx_PLUS (Pmode,
5624 stack_pointer_rtx,
5625 GEN_INT (offset)));
5626
5627 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
5628 note_rtx = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set,
5629 REG_NOTES (insn));
5630 REG_NOTES (insn) = note_rtx;
5631 }
5632 }
5633 }
87e19636 5634
41fafa66 5635 if (entry->offset != d_rounding)
87e19636 5636 abort ();
5637 }
5638 else
36a2dfdb 5639 push_regs (&live_regs_mask, current_function_interrupt);
0abf894c 5640
420261ef 5641 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
47890aff 5642 {
5643 rtx insn = get_last_insn ();
5644 rtx last = emit_insn (gen_GOTaddr2picreg ());
5645
5646 /* Mark these insns as possibly dead. Sometimes, flow2 may
5647 delete all uses of the PIC register. In this case, let it
5648 delete the initialization too. */
5649 do
5650 {
5651 insn = NEXT_INSN (insn);
5652
5653 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5654 const0_rtx,
5655 REG_NOTES (insn));
5656 }
5657 while (insn != last);
5658 }
0abf894c 5659
87e19636 5660 if (SHMEDIA_REGS_STACK_ADJUST ())
5661 {
5662 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
45271277 5663 function_symbol (TARGET_FPU_ANY
5664 ? "__GCC_push_shmedia_regs"
5665 : "__GCC_push_shmedia_regs_nofpu"));
87e19636 5666 /* This must NOT go through the PLT, otherwise mach and macl
5667 may be clobbered. */
5668 emit_insn (gen_shmedia_save_restore_regs_compact
5669 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
5670 }
5671
36a2dfdb 5672 if (target_flags != save_flags && ! current_function_interrupt)
55a97ca8 5673 {
5674 rtx insn = emit_insn (gen_toggle_sz ());
5675
5676 /* If we're lucky, a mode switch in the function body will
5677 overwrite fpscr, turning this insn dead. Tell flow this
5678 insn is ok to delete. */
5679 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5680 const0_rtx,
5681 REG_NOTES (insn));
5682 }
b00564da 5683
1b61190c 5684 target_flags = save_flags;
5685
87e19636 5686 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
41fafa66 5687 stack_pointer_rtx, 0, NULL);
47c009e5 5688
5689 if (frame_pointer_needed)
363600c8 5690 frame_insn (GEN_MOV (frame_pointer_rtx, stack_pointer_rtx));
87e19636 5691
87e19636 5692 if (TARGET_SHCOMPACT
5693 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
5694 {
5695 /* This must NOT go through the PLT, otherwise mach and macl
5696 may be clobbered. */
5697 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
45271277 5698 function_symbol ("__GCC_shcompact_incoming_args"));
87e19636 5699 emit_insn (gen_shcompact_incoming_args ());
5700 }
47c009e5 5701}
5702
5703void
66209063 5704sh_expand_epilogue (bool sibcall_p)
47c009e5 5705{
ed8483c0 5706 HARD_REG_SET live_regs_mask;
0f021c78 5707 int d, i;
87e19636 5708 int d_rounding = 0;
47c009e5 5709
1b61190c 5710 int save_flags = target_flags;
8af3db02 5711 int frame_size, save_size;
36a2dfdb 5712 int fpscr_deferred = 0;
66209063 5713 int e = sibcall_p ? -1 : 1;
ba46e0eb 5714
ed8483c0 5715 d = calc_live_regs (&live_regs_mask);
ba46e0eb 5716
8af3db02 5717 save_size = d;
5718 frame_size = rounded_frame_size (d);
5719
5720 if (TARGET_SH5)
5721 {
5722 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
5723 int total_size;
5724 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
5725 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5726 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
5727
5728 total_size = d + tregs_space;
5729 total_size += rounded_frame_size (total_size);
5730 save_size = total_size - frame_size;
5731
5732 /* If adjusting the stack in a single step costs nothing extra, do so.
5733 I.e. either if a single addi is enough, or we need a movi anyway,
5734 and we don't exceed the maximum offset range (the test for the
5735 latter is conservative for simplicity). */
5736 if (TARGET_SHMEDIA
5737 && ! frame_pointer_needed
5738 && (CONST_OK_FOR_I10 (total_size)
5739 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
5740 && total_size <= 2044)))
5741 d_rounding = frame_size;
87e19636 5742
8af3db02 5743 frame_size -= d_rounding;
5744 }
1504eb7e 5745
47c009e5 5746 if (frame_pointer_needed)
64623096 5747 {
66209063 5748 output_stack_adjust (frame_size, frame_pointer_rtx, e, &live_regs_mask);
b5a24772 5749
5750 /* We must avoid moving the stack pointer adjustment past code
5751 which reads from the local frame, else an interrupt could
5752 occur after the SP adjustment and clobber data in the local
5753 frame. */
5754 emit_insn (gen_blockage ());
87e19636 5755 emit_insn (GEN_MOV (stack_pointer_rtx, frame_pointer_rtx));
64623096 5756 }
ba46e0eb 5757 else if (frame_size)
b5a24772 5758 {
5759 /* We must avoid moving the stack pointer adjustment past code
5760 which reads from the local frame, else an interrupt could
5761 occur after the SP adjustment and clobber data in the local
5762 frame. */
5763 emit_insn (gen_blockage ());
66209063 5764 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
b5a24772 5765 }
47c009e5 5766
87e19636 5767 if (SHMEDIA_REGS_STACK_ADJUST ())
5768 {
5769 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
45271277 5770 function_symbol (TARGET_FPU_ANY
5771 ? "__GCC_pop_shmedia_regs"
5772 : "__GCC_pop_shmedia_regs_nofpu"));
87e19636 5773 /* This must NOT go through the PLT, otherwise mach and macl
5774 may be clobbered. */
5775 emit_insn (gen_shmedia_save_restore_regs_compact
5776 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
5777 }
5778
1504eb7e 5779 /* Pop all the registers. */
97595bfd 5780
36a2dfdb 5781 if (target_flags != save_flags && ! current_function_interrupt)
1b61190c 5782 emit_insn (gen_toggle_sz ());
87e19636 5783 if (TARGET_SH5)
5784 {
41fafa66 5785 int offset_base, offset;
87e19636 5786 int offset_in_r0 = -1;
5787 int sp_in_r0 = 0;
87e19636 5788 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
41fafa66 5789 save_schedule schedule;
5790 save_entry *entry;
5791 int *tmp_pnt;
ca474d26 5792
41fafa66 5793 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
5794 offset_base = -entry[1].offset + d_rounding;
5795 tmp_pnt = schedule.temps;
5796 for (; entry->mode != VOIDmode; entry--)
5797 {
5798 enum machine_mode mode = entry->mode;
5799 int reg = entry->reg;
5800 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
87e19636 5801
41fafa66 5802 offset = offset_base + entry->offset;
5803 reg_rtx = gen_rtx_REG (mode, reg);
87e19636 5804
41fafa66 5805 mem_rtx = gen_rtx_MEM (mode,
5806 gen_rtx_PLUS (Pmode,
5807 stack_pointer_rtx,
5808 GEN_INT (offset)));
87e19636 5809
41fafa66 5810 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
87e19636 5811
41fafa66 5812 mem_rtx = NULL_RTX;
87e19636 5813
41fafa66 5814 try_post_inc:
5815 do
5816 if (HAVE_POST_INCREMENT
5817 && (offset == offset_in_r0
5818 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
5819 && mem_rtx == NULL_RTX)
5820 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
5821 {
5822 post_inc = gen_rtx_MEM (mode,
5823 gen_rtx_POST_INC (Pmode, r0));
87e19636 5824
41fafa66 5825 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
5826 post_inc_ok);
87e19636 5827
41fafa66 5828 post_inc = NULL_RTX;
87e19636 5829
41fafa66 5830 break;
5831
5832 post_inc_ok:
5833 mem_rtx = NULL_RTX;
5834 }
5835 while (0);
5836
5837 if (mem_rtx != NULL_RTX)
5838 goto addr_ok;
87e19636 5839
41fafa66 5840 if (offset_in_r0 == -1)
5841 {
5842 emit_move_insn (r0, GEN_INT (offset));
5843 offset_in_r0 = offset;
5844 }
5845 else if (offset != offset_in_r0)
5846 {
5847 emit_move_insn (r0,
5848 gen_rtx_PLUS
5849 (Pmode, r0,
5850 GEN_INT (offset - offset_in_r0)));
5851 offset_in_r0 += offset - offset_in_r0;
5852 }
87e19636 5853
41fafa66 5854 if (post_inc != NULL_RTX)
5855 {
5856 if (! sp_in_r0)
87e19636 5857 {
5858 emit_move_insn (r0,
5859 gen_rtx_PLUS
41fafa66 5860 (Pmode, r0, stack_pointer_rtx));
5861 sp_in_r0 = 1;
87e19636 5862 }
41fafa66 5863
5864 mem_rtx = post_inc;
87e19636 5865
41fafa66 5866 offset_in_r0 += GET_MODE_SIZE (mode);
5867 }
5868 else if (sp_in_r0)
5869 mem_rtx = gen_rtx_MEM (mode, r0);
5870 else
5871 mem_rtx = gen_rtx_MEM (mode,
5872 gen_rtx_PLUS (Pmode,
5873 stack_pointer_rtx,
5874 r0));
87e19636 5875
41fafa66 5876 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5877 && mem_rtx != post_inc)
5878 abort ();
87e19636 5879
41fafa66 5880 addr_ok:
5881 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
5882 && mem_rtx != post_inc)
5883 {
5884 insn = emit_move_insn (r0, mem_rtx);
5885 mem_rtx = r0;
5886 }
5887 else if (TARGET_REGISTER_P (reg))
5888 {
5889 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
5890
5891 /* Give the scheduler a bit of freedom by using up to
5892 MAX_TEMPS registers in a round-robin fashion. */
5893 insn = emit_move_insn (tmp_reg, mem_rtx);
5894 mem_rtx = tmp_reg;
5895 if (*++tmp_pnt < 0)
5896 tmp_pnt = schedule.temps;
87e19636 5897 }
5898
41fafa66 5899 insn = emit_move_insn (reg_rtx, mem_rtx);
ca474d26 5900 if (reg == PR_MEDIA_REG && sh_media_register_for_return () >= 0)
5901 /* This is dead, unless we return with a sibcall. */
5902 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
5903 const0_rtx,
5904 REG_NOTES (insn));
41fafa66 5905 }
5906
5907 if (entry->offset + offset_base != d + d_rounding)
87e19636 5908 abort ();
87e19636 5909 }
8af3db02 5910 else /* ! TARGET_SH5 */
47c009e5 5911 {
8af3db02 5912 save_size = 0;
5913 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
5914 pop (PR_REG);
5915 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5916 {
5917 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
5918
5919 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
5920 && hard_regs_intersect_p (&live_regs_mask,
5921 &reg_class_contents[DF_REGS]))
5922 fpscr_deferred = 1;
5923 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j))
5924 pop (j);
5925 if (j == FIRST_FP_REG && fpscr_deferred)
5926 pop (FPSCR_REG);
87e19636 5927
8af3db02 5928 }
47c009e5 5929 }
36a2dfdb 5930 if (target_flags != save_flags && ! current_function_interrupt)
1b61190c 5931 emit_insn (gen_toggle_sz ());
5932 target_flags = save_flags;
47c009e5 5933
09a512b9 5934 output_stack_adjust (current_function_pretend_args_size
8af3db02 5935 + save_size + d_rounding
87e19636 5936 + current_function_args_info.stack_regs * 8,
66209063 5937 stack_pointer_rtx, e, NULL);
15cb1799 5938
805e22b2 5939 if (current_function_calls_eh_return)
5940 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
5941 EH_RETURN_STACKADJ_RTX));
5942
15cb1799 5943 /* Switch back to the normal stack if necessary. */
5944 if (sp_switch)
5945 emit_insn (gen_sp_switch_2 ());
6dc67d01 5946
5947 /* Tell flow the insn that pops PR isn't dead. */
87e19636 5948 /* PR_REG will never be live in SHmedia mode, and we don't need to
5949 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
5950 by the return pattern. */
ed8483c0 5951 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
6dc67d01 5952 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
47c009e5 5953}
5954
303d40e1 5955static int sh_need_epilogue_known = 0;
5956
5957int
04f04b72 5958sh_need_epilogue (void)
303d40e1 5959{
5960 if (! sh_need_epilogue_known)
5961 {
5962 rtx epilogue;
5963
5964 start_sequence ();
66209063 5965 sh_expand_epilogue (0);
31d3e01c 5966 epilogue = get_insns ();
303d40e1 5967 end_sequence ();
31d3e01c 5968 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
303d40e1 5969 }
5970 return sh_need_epilogue_known > 0;
5971}
5972
805e22b2 5973/* Emit code to change the current function's return address to RA.
5974 TEMP is available as a scratch register, if needed. */
5975
5976void
04f04b72 5977sh_set_return_address (rtx ra, rtx tmp)
805e22b2 5978{
ed8483c0 5979 HARD_REG_SET live_regs_mask;
805e22b2 5980 int d;
805e22b2 5981 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
5982 int pr_offset;
5983
ed8483c0 5984 d = calc_live_regs (&live_regs_mask);
805e22b2 5985
5986 /* If pr_reg isn't life, we can set it (or the register given in
5987 sh_media_register_for_return) directly. */
ed8483c0 5988 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
805e22b2 5989 {
5990 rtx rr;
5991
5992 if (TARGET_SHMEDIA)
5993 {
5994 int rr_regno = sh_media_register_for_return ();
5995
5996 if (rr_regno < 0)
5997 rr_regno = pr_reg;
5998
5999 rr = gen_rtx_REG (DImode, rr_regno);
6000 }
6001 else
6002 rr = gen_rtx_REG (SImode, pr_reg);
6003
6004 emit_insn (GEN_MOV (rr, ra));
6005 /* Tell flow the register for return isn't dead. */
6006 emit_insn (gen_rtx_USE (VOIDmode, rr));
6007 return;
6008 }
6009
6010 if (TARGET_SH5)
6011 {
805e22b2 6012 int offset;
41fafa66 6013 save_schedule schedule;
6014 save_entry *entry;
805e22b2 6015
41fafa66 6016 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
6017 offset = entry[1].offset;
6018 for (; entry->mode != VOIDmode; entry--)
6019 if (entry->reg == pr_reg)
6020 goto found;
805e22b2 6021
6022 /* We can't find pr register. */
6023 abort ();
6024
6025 found:
41fafa66 6026 offset = entry->offset - offset;
6027 pr_offset = (rounded_frame_size (d) + offset
805e22b2 6028 + SHMEDIA_REGS_STACK_ADJUST ());
6029 }
6030 else
41fafa66 6031 pr_offset = rounded_frame_size (d);
805e22b2 6032
6033 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
6034 emit_insn (GEN_ADD3 (tmp, tmp, frame_pointer_rtx));
6035
6036 tmp = gen_rtx_MEM (Pmode, tmp);
6037 emit_insn (GEN_MOV (tmp, ra));
6038}
6039
73401833 6040/* Clear variables at function end. */
6041
17d9b0c3 6042static void
04f04b72 6043sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6044 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
73401833 6045{
15cb1799 6046 trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
303d40e1 6047 sh_need_epilogue_known = 0;
15cb1799 6048 sp_switch = NULL_RTX;
73401833 6049}
6050
45550790 6051static rtx
04f04b72 6052sh_builtin_saveregs (void)
b00564da 6053{
b00564da 6054 /* First unnamed integer register. */
6055 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
6056 /* Number of integer registers we need to save. */
6057 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
6058 /* First unnamed SFmode float reg */
6059 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
6060 /* Number of SFmode float regs to save. */
6061 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
b7dbbdb2 6062 rtx regbuf, fpregs;
ab6ab77e 6063 int bufsize, regno;
6064 HOST_WIDE_INT alias_set;
b00564da 6065
87e19636 6066 if (TARGET_SH5)
6067 {
6068 if (n_intregs)
6069 {
6070 int pushregs = n_intregs;
6071
6072 while (pushregs < NPARM_REGS (SImode) - 1
6073 && (CALL_COOKIE_INT_REG_GET
6074 (current_function_args_info.call_cookie,
6075 NPARM_REGS (SImode) - pushregs)
6076 == 1))
6077 {
6078 current_function_args_info.call_cookie
6079 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
6080 - pushregs, 1);
6081 pushregs++;
6082 }
6083
6084 if (pushregs == NPARM_REGS (SImode))
6085 current_function_args_info.call_cookie
6086 |= (CALL_COOKIE_INT_REG (0, 1)
6087 | CALL_COOKIE_STACKSEQ (pushregs - 1));
6088 else
6089 current_function_args_info.call_cookie
6090 |= CALL_COOKIE_STACKSEQ (pushregs);
6091
6092 current_function_pretend_args_size += 8 * n_intregs;
6093 }
6094 if (TARGET_SHCOMPACT)
6095 return const0_rtx;
6096 }
6097
87ed74ef 6098 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
87e19636 6099 {
6100 error ("__builtin_saveregs not supported by this subtarget");
6101 return const0_rtx;
6102 }
6103
6104 if (TARGET_SHMEDIA)
6105 n_floatregs = 0;
6106
9df03d69 6107 /* Allocate block of memory for the regs. */
b00564da 6108 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
6109 Or can assign_stack_local accept a 0 SIZE argument? */
6110 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
6111
87e19636 6112 if (TARGET_SHMEDIA)
6113 regbuf = gen_rtx_MEM (BLKmode,
6114 gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
65f753eb 6115 else if (n_floatregs & 1)
6116 {
6117 rtx addr;
6118
6119 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
6120 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
6121 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
6122 regbuf = change_address (regbuf, BLKmode, addr);
6123 }
87e19636 6124 else
6125 regbuf = assign_stack_local (BLKmode, bufsize, 0);
d1de1e66 6126 alias_set = get_varargs_alias_set ();
ab6ab77e 6127 set_mem_alias_set (regbuf, alias_set);
b00564da 6128
6129 /* Save int args.
6130 This is optimized to only save the regs that are necessary. Explicitly
6131 named args need not be saved. */
6132 if (n_intregs > 0)
6133 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
e513d163 6134 adjust_address (regbuf, BLKmode,
6135 n_floatregs * UNITS_PER_WORD),
530178a9 6136 n_intregs);
b00564da 6137
87e19636 6138 if (TARGET_SHMEDIA)
6139 /* Return the address of the regbuf. */
6140 return XEXP (regbuf, 0);
6141
b00564da 6142 /* Save float args.
6143 This is optimized to only save the regs that are necessary. Explicitly
6144 named args need not be saved.
6145 We explicitly build a pointer to the buffer because it halves the insn
6146 count when not optimizing (otherwise the pointer is built for each reg
8ded0752 6147 saved).
6148 We emit the moves in reverse order so that we can use predecrement. */
b00564da 6149
6150 fpregs = gen_reg_rtx (Pmode);
6151 emit_move_insn (fpregs, XEXP (regbuf, 0));
8ded0752 6152 emit_insn (gen_addsi3 (fpregs, fpregs,
6153 GEN_INT (n_floatregs * UNITS_PER_WORD)));
1b61190c 6154 if (TARGET_SH4)
6155 {
d1de1e66 6156 rtx mem;
1b61190c 6157 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
6158 {
6159 emit_insn (gen_addsi3 (fpregs, fpregs,
6160 GEN_INT (-2 * UNITS_PER_WORD)));
d1de1e66 6161 mem = gen_rtx_MEM (DFmode, fpregs);
ab6ab77e 6162 set_mem_alias_set (mem, alias_set);
d1de1e66 6163 emit_move_insn (mem,
407d9153 6164 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
1b61190c 6165 }
6166 regno = first_floatreg;
6167 if (regno & 1)
6168 {
d767e27e 6169 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
d1de1e66 6170 mem = gen_rtx_MEM (SFmode, fpregs);
ab6ab77e 6171 set_mem_alias_set (mem, alias_set);
d1de1e66 6172 emit_move_insn (mem,
407d9153 6173 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
1b61190c 6174 - (TARGET_LITTLE_ENDIAN != 0)));
6175 }
6176 }
6177 else
8ded0752 6178 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
6179 {
d1de1e66 6180 rtx mem;
ab6ab77e 6181
d767e27e 6182 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
d1de1e66 6183 mem = gen_rtx_MEM (SFmode, fpregs);
ab6ab77e 6184 set_mem_alias_set (mem, alias_set);
d1de1e66 6185 emit_move_insn (mem,
7014838c 6186 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
8ded0752 6187 }
b00564da 6188
6189 /* Return the address of the regbuf. */
6190 return XEXP (regbuf, 0);
6191}
6192
d1de1e66 6193/* Define the `__builtin_va_list' type for the ABI. */
6194
2e15d750 6195static tree
6196sh_build_builtin_va_list (void)
d1de1e66 6197{
6198 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
6199 tree record;
6200
45550790 6201 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
6202 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
d1de1e66 6203 return ptr_type_node;
6204
89fdb407 6205 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
d1de1e66 6206
6207 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
6208 ptr_type_node);
6209 f_next_o_limit = build_decl (FIELD_DECL,
6210 get_identifier ("__va_next_o_limit"),
6211 ptr_type_node);
6212 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
6213 ptr_type_node);
6214 f_next_fp_limit = build_decl (FIELD_DECL,
6215 get_identifier ("__va_next_fp_limit"),
6216 ptr_type_node);
6217 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
6218 ptr_type_node);
6219
6220 DECL_FIELD_CONTEXT (f_next_o) = record;
6221 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
6222 DECL_FIELD_CONTEXT (f_next_fp) = record;
6223 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
6224 DECL_FIELD_CONTEXT (f_next_stack) = record;
6225
6226 TYPE_FIELDS (record) = f_next_o;
6227 TREE_CHAIN (f_next_o) = f_next_o_limit;
6228 TREE_CHAIN (f_next_o_limit) = f_next_fp;
6229 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
6230 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
6231
6232 layout_type (record);
6233
6234 return record;
6235}
6236
6237/* Implement `va_start' for varargs and stdarg. */
6238
6239void
04f04b72 6240sh_va_start (tree valist, rtx nextarg)
d1de1e66 6241{
6242 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
6243 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
6244 tree t, u;
6245 int nfp, nint;
6246
87e19636 6247 if (TARGET_SH5)
6248 {
6249 expand_builtin_saveregs ();
7df226a2 6250 std_expand_builtin_va_start (valist, nextarg);
87e19636 6251 return;
6252 }
6253
45550790 6254 if ((! TARGET_SH2E && ! TARGET_SH4)
6255 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
d1de1e66 6256 {
7df226a2 6257 std_expand_builtin_va_start (valist, nextarg);
d1de1e66 6258 return;
6259 }
6260
6261 f_next_o = TYPE_FIELDS (va_list_type_node);
6262 f_next_o_limit = TREE_CHAIN (f_next_o);
6263 f_next_fp = TREE_CHAIN (f_next_o_limit);
6264 f_next_fp_limit = TREE_CHAIN (f_next_fp);
6265 f_next_stack = TREE_CHAIN (f_next_fp_limit);
6266
6374121b 6267 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
6268 NULL_TREE);
d1de1e66 6269 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
6374121b 6270 valist, f_next_o_limit, NULL_TREE);
6271 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
6272 NULL_TREE);
d1de1e66 6273 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
6374121b 6274 valist, f_next_fp_limit, NULL_TREE);
d1de1e66 6275 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
6374121b 6276 valist, f_next_stack, NULL_TREE);
d1de1e66 6277
6278 /* Call __builtin_saveregs. */
6279 u = make_tree (ptr_type_node, expand_builtin_saveregs ());
6280 t = build (MODIFY_EXPR, ptr_type_node, next_fp, u);
6281 TREE_SIDE_EFFECTS (t) = 1;
6282 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6283
6284 nfp = current_function_args_info.arg_count[SH_ARG_FLOAT];
6285 if (nfp < 8)
6286 nfp = 8 - nfp;
6287 else
6288 nfp = 0;
6289 u = fold (build (PLUS_EXPR, ptr_type_node, u,
6290 build_int_2 (UNITS_PER_WORD * nfp, 0)));
6291 t = build (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
6292 TREE_SIDE_EFFECTS (t) = 1;
6293 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6294
6295 t = build (MODIFY_EXPR, ptr_type_node, next_o, u);
6296 TREE_SIDE_EFFECTS (t) = 1;
6297 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6298
6299 nint = current_function_args_info.arg_count[SH_ARG_INT];
6300 if (nint < 4)
6301 nint = 4 - nint;
6302 else
6303 nint = 0;
6304 u = fold (build (PLUS_EXPR, ptr_type_node, u,
6305 build_int_2 (UNITS_PER_WORD * nint, 0)));
6306 t = build (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
6307 TREE_SIDE_EFFECTS (t) = 1;
6308 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6309
6310 u = make_tree (ptr_type_node, nextarg);
d1de1e66 6311 t = build (MODIFY_EXPR, ptr_type_node, next_stack, u);
6312 TREE_SIDE_EFFECTS (t) = 1;
6313 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6314}
6315
6316/* Implement `va_arg'. */
6317
20cdebf8 6318static tree
6319sh_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p,
6320 tree *post_p ATTRIBUTE_UNUSED)
d1de1e66 6321{
6322 HOST_WIDE_INT size, rsize;
b7dbbdb2 6323 tree tmp, pptr_type_node;
20cdebf8 6324 tree addr, lab_over, result = NULL;
0336f0f0 6325 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
20cdebf8 6326
6327 if (pass_by_ref)
6328 type = build_pointer_type (type);
d1de1e66 6329
6330 size = int_size_in_bytes (type);
6331 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6332 pptr_type_node = build_pointer_type (ptr_type_node);
6333
45550790 6334 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
6335 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
d1de1e66 6336 {
6337 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
6338 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
6339 int pass_as_float;
20cdebf8 6340 tree lab_false;
d1de1e66 6341
6342 f_next_o = TYPE_FIELDS (va_list_type_node);
6343 f_next_o_limit = TREE_CHAIN (f_next_o);
6344 f_next_fp = TREE_CHAIN (f_next_o_limit);
6345 f_next_fp_limit = TREE_CHAIN (f_next_fp);
6346 f_next_stack = TREE_CHAIN (f_next_fp_limit);
6347
6374121b 6348 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
6349 NULL_TREE);
d1de1e66 6350 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
6374121b 6351 valist, f_next_o_limit, NULL_TREE);
d1de1e66 6352 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp),
6374121b 6353 valist, f_next_fp, NULL_TREE);
d1de1e66 6354 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
6374121b 6355 valist, f_next_fp_limit, NULL_TREE);
d1de1e66 6356 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
6374121b 6357 valist, f_next_stack, NULL_TREE);
d1de1e66 6358
d8e6ba8f 6359 /* Structures with a single member with a distinct mode are passed
6360 like their member. This is relevant if the latter has a REAL_TYPE
6361 or COMPLEX_TYPE type. */
6362 if (TREE_CODE (type) == RECORD_TYPE
6363 && TYPE_FIELDS (type)
6364 && TREE_CODE (TYPE_FIELDS (type)) == FIELD_DECL
6365 && (TREE_CODE (TREE_TYPE (TYPE_FIELDS (type))) == REAL_TYPE
6366 || TREE_CODE (TREE_TYPE (TYPE_FIELDS (type))) == COMPLEX_TYPE)
6367 && TREE_CHAIN (TYPE_FIELDS (type)) == NULL_TREE)
6368 type = TREE_TYPE (TYPE_FIELDS (type));
20cdebf8 6369
d1de1e66 6370 if (TARGET_SH4)
6371 {
6372 pass_as_float = ((TREE_CODE (type) == REAL_TYPE && size <= 8)
6373 || (TREE_CODE (type) == COMPLEX_TYPE
6374 && TREE_CODE (TREE_TYPE (type)) == REAL_TYPE
6375 && size <= 16));
6376 }
6377 else
6378 {
6379 pass_as_float = (TREE_CODE (type) == REAL_TYPE && size == 4);
6380 }
6381
20cdebf8 6382 addr = create_tmp_var (pptr_type_node, NULL);
6383 lab_false = create_artificial_label ();
6384 lab_over = create_artificial_label ();
d1de1e66 6385
20cdebf8 6386 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
d8e6ba8f 6387
d1de1e66 6388 if (pass_as_float)
6389 {
65f753eb 6390 int first_floatreg
6391 = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
6392 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
6393
20cdebf8 6394 tmp = build (GE_EXPR, boolean_type_node, next_fp, next_fp_limit);
6395 tmp = build (COND_EXPR, void_type_node, tmp,
6396 build (GOTO_EXPR, void_type_node, lab_false),
6397 NULL);
6398 gimplify_and_add (tmp, pre_p);
d1de1e66 6399
65f753eb 6400 if (TYPE_ALIGN (type) > BITS_PER_WORD
6401 || (((TREE_CODE (type) == REAL_TYPE && size == 8) || size == 16)
6402 && (n_floatregs & 1)))
d1de1e66 6403 {
20cdebf8 6404 tmp = fold_convert (ptr_type_node, size_int (UNITS_PER_WORD));
6405 tmp = build (BIT_AND_EXPR, ptr_type_node, next_fp, tmp);
d1de1e66 6406 tmp = build (PLUS_EXPR, ptr_type_node, next_fp, tmp);
6407 tmp = build (MODIFY_EXPR, ptr_type_node, next_fp, tmp);
20cdebf8 6408 gimplify_and_add (tmp, pre_p);
d1de1e66 6409 }
6410
6411 tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp);
20cdebf8 6412 tmp = build (MODIFY_EXPR, void_type_node, addr, tmp);
6413 gimplify_and_add (tmp, pre_p);
d1de1e66 6414
d8e6ba8f 6415#ifdef FUNCTION_ARG_SCmode_WART
6416 if (TYPE_MODE (type) == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
6417 {
d8e6ba8f 6418 tree subtype = TREE_TYPE (type);
20cdebf8 6419 tree real, imag;
d8e6ba8f 6420
20cdebf8 6421 imag = std_gimplify_va_arg_expr (valist, subtype, pre_p, NULL);
6422 imag = get_initialized_tmp_var (imag, pre_p, NULL);
d8e6ba8f 6423
20cdebf8 6424 real = std_gimplify_va_arg_expr (valist, subtype, pre_p, NULL);
6425 real = get_initialized_tmp_var (real, pre_p, NULL);
6426
6427 result = build (COMPLEX_EXPR, type, real, imag);
6428 result = get_initialized_tmp_var (result, pre_p, NULL);
d8e6ba8f 6429 }
6430#endif /* FUNCTION_ARG_SCmode_WART */
6431
20cdebf8 6432 tmp = build (GOTO_EXPR, void_type_node, lab_over);
6433 gimplify_and_add (tmp, pre_p);
6434
6435 tmp = build (LABEL_EXPR, void_type_node, lab_false);
6436 gimplify_and_add (tmp, pre_p);
d1de1e66 6437
6438 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
20cdebf8 6439 tmp = build (MODIFY_EXPR, void_type_node, addr, tmp);
6440 gimplify_and_add (tmp, pre_p);
d1de1e66 6441 }
6442 else
6443 {
20cdebf8 6444 tmp = fold_convert (ptr_type_node, size_int (rsize));
6445 tmp = build (PLUS_EXPR, ptr_type_node, next_o, tmp);
6446 tmp = build (GT_EXPR, boolean_type_node, tmp, next_o_limit);
6447 tmp = build (COND_EXPR, void_type_node, tmp,
6448 build (GOTO_EXPR, void_type_node, lab_false),
6449 NULL);
6450 gimplify_and_add (tmp, pre_p);
d1de1e66 6451
6452 tmp = build1 (ADDR_EXPR, pptr_type_node, next_o);
20cdebf8 6453 tmp = build (MODIFY_EXPR, void_type_node, addr, tmp);
6454 gimplify_and_add (tmp, pre_p);
d1de1e66 6455
20cdebf8 6456 tmp = build (GOTO_EXPR, void_type_node, lab_over);
6457 gimplify_and_add (tmp, pre_p);
6458
6459 tmp = build (LABEL_EXPR, void_type_node, lab_false);
6460 gimplify_and_add (tmp, pre_p);
d1de1e66 6461
6462 if (size > 4 && ! TARGET_SH4)
6463 {
6464 tmp = build (MODIFY_EXPR, ptr_type_node, next_o, next_o_limit);
20cdebf8 6465 gimplify_and_add (tmp, pre_p);
d1de1e66 6466 }
6467
6468 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
20cdebf8 6469 tmp = build (MODIFY_EXPR, void_type_node, addr, tmp);
6470 gimplify_and_add (tmp, pre_p);
d1de1e66 6471 }
6472
20cdebf8 6473 if (!result)
6474 {
6475 tmp = build (LABEL_EXPR, void_type_node, lab_over);
6476 gimplify_and_add (tmp, pre_p);
6477 }
d1de1e66 6478 }
6479
6480 /* ??? In va-sh.h, there had been code to make values larger than
6481 size 8 indirect. This does not match the FUNCTION_ARG macros. */
6482
20cdebf8 6483 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
d8e6ba8f 6484 if (result)
6485 {
20cdebf8 6486 tmp = build (MODIFY_EXPR, void_type_node, result, tmp);
6487 gimplify_and_add (tmp, pre_p);
6488
6489 tmp = build (LABEL_EXPR, void_type_node, lab_over);
6490 gimplify_and_add (tmp, pre_p);
d8e6ba8f 6491 }
6492 else
20cdebf8 6493 result = tmp;
d8e6ba8f 6494
a3e17e8c 6495 if (pass_by_ref)
20cdebf8 6496 result = build_fold_indirect_ref (result);
6497
a3e17e8c 6498 return result;
d1de1e66 6499}
6500
f5f12868 6501bool
04f04b72 6502sh_promote_prototypes (tree type)
45550790 6503{
6504 if (TARGET_HITACHI)
6505 return 0;
6506 if (! type)
6507 return 1;
6508 return ! sh_attr_renesas_p (type);
6509}
6510
b981d932 6511/* Whether an argument must be passed by reference. On SHcompact, we
6512 pretend arguments wider than 32-bits that would have been passed in
6513 registers are passed by reference, so that an SHmedia trampoline
6514 loads them into the full 64-bits registers. */
6515
6516static int
6517shcompact_byref (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6518 tree type, bool named)
6519{
6520 unsigned HOST_WIDE_INT size;
6521
6522 if (type)
6523 size = int_size_in_bytes (type);
6524 else
6525 size = GET_MODE_SIZE (mode);
6526
6527 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
6528 && (!named
6529 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
6530 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
6531 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
6532 && size > 4
6533 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
6534 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
6535 return size;
6536 else
6537 return 0;
6538}
6539
6540static bool
6541sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6542 tree type, bool named)
6543{
6544 if (targetm.calls.must_pass_in_stack (mode, type))
6545 return true;
6546
6547 if (TARGET_SHCOMPACT)
6548 {
6549 cum->byref = shcompact_byref (cum, mode, type, named);
6550 return cum->byref != 0;
6551 }
6552
6553 return false;
6554}
6555
45550790 6556/* Define where to put the arguments to a function.
6557 Value is zero to push the argument on the stack,
6558 or a hard register in which to store the argument.
6559
6560 MODE is the argument's machine mode.
6561 TYPE is the data type of the argument (as a tree).
6562 This is null for libcalls where that information may
6563 not be available.
6564 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6565 the preceding args and about the function being called.
6566 NAMED is nonzero if this argument is a named parameter
6567 (otherwise it is an extra parameter matching an ellipsis).
6568
6569 On SH the first args are normally in registers
6570 and the rest are pushed. Any arg that starts within the first
6571 NPARM_REGS words is at least partially passed in a register unless
6572 its data type forbids. */
6573
6574
6575rtx
04f04b72 6576sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
6577 tree type, int named)
45550790 6578{
6579 if (! TARGET_SH5 && mode == VOIDmode)
6580 return GEN_INT (ca->renesas_abi ? 1 : 0);
6581
6582 if (! TARGET_SH5
6583 && PASS_IN_REG_P (*ca, mode, type)
6584 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
6585 {
6586 int regno;
6587
6588 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
6589 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
6590 {
6591 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
6592 gen_rtx_REG (SFmode,
6593 BASE_ARG_REG (mode)
6594 + (ROUND_REG (*ca, mode) ^ 1)),
6595 const0_rtx);
d767e27e 6596 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
6597 gen_rtx_REG (SFmode,
6598 BASE_ARG_REG (mode)
6599 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
6600 GEN_INT (4));
45550790 6601 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
6602 }
6603
6604 /* If the alignment of a DF value causes an SF register to be
6605 skipped, we will use that skipped register for the next SF
6606 value. */
6607 if ((TARGET_HITACHI || ca->renesas_abi)
6608 && ca->free_single_fp_reg
6609 && mode == SFmode)
6610 return gen_rtx_REG (mode, ca->free_single_fp_reg);
6611
6612 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
6613 ^ (mode == SFmode && TARGET_SH4
6614 && TARGET_LITTLE_ENDIAN != 0
6615 && ! TARGET_HITACHI && ! ca->renesas_abi);
6616 return gen_rtx_REG (mode, regno);
6617
6618 }
6619
6620 if (TARGET_SH5)
6621 {
6622 if (mode == VOIDmode && TARGET_SHCOMPACT)
6623 return GEN_INT (ca->call_cookie);
6624
6625 /* The following test assumes unnamed arguments are promoted to
6626 DFmode. */
6627 if (mode == SFmode && ca->free_single_fp_reg)
6628 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
6629
6630 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
6631 && (named || ! ca->prototype_p)
6632 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
6633 {
6634 if (! ca->prototype_p && TARGET_SHMEDIA)
6635 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
6636
6637 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
6638 FIRST_FP_PARM_REG
6639 + ca->arg_count[(int) SH_ARG_FLOAT]);
6640 }
6641
6642 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
6643 && (! TARGET_SHCOMPACT
6644 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
6645 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
6646 type, named))))
6647 {
6648 return gen_rtx_REG (mode, (FIRST_PARM_REG
6649 + ca->arg_count[(int) SH_ARG_INT]));
6650 }
6651
6652 return 0;
6653 }
6654
6655 return 0;
6656}
6657
6658/* Update the data in CUM to advance over an argument
6659 of mode MODE and data type TYPE.
6660 (TYPE is null for libcalls where that information may not be
6661 available.) */
6662
6663void
04f04b72 6664sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
6665 tree type, int named)
45550790 6666{
d767e27e 6667 if (ca->force_mem)
6668 ca->force_mem = 0;
6669 else if (TARGET_SH5)
6670 {
6671 tree type2 = (ca->byref && type
6672 ? TREE_TYPE (type)
6673 : type);
6674 enum machine_mode mode2 = (ca->byref && type
6675 ? TYPE_MODE (type2)
6676 : mode);
6677 int dwords = ((ca->byref
6678 ? ca->byref
6679 : mode2 == BLKmode
6680 ? int_size_in_bytes (type2)
6681 : GET_MODE_SIZE (mode2)) + 7) / 8;
6682 int numregs = MIN (dwords, NPARM_REGS (SImode)
6683 - ca->arg_count[(int) SH_ARG_INT]);
6684
6685 if (numregs)
6686 {
6687 ca->arg_count[(int) SH_ARG_INT] += numregs;
6688 if (TARGET_SHCOMPACT
6689 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
6690 {
6691 ca->call_cookie
6692 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
6693 - numregs, 1);
6694 /* N.B. We want this also for outgoing. */
6695 ca->stack_regs += numregs;
6696 }
6697 else if (ca->byref)
6698 {
6699 if (! ca->outgoing)
6700 ca->stack_regs += numregs;
6701 ca->byref_regs += numregs;
6702 ca->byref = 0;
6703 do
6704 ca->call_cookie
6705 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
6706 - numregs, 2);
6707 while (--numregs);
6708 ca->call_cookie
6709 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
6710 - 1, 1);
6711 }
6712 else if (dwords > numregs)
6713 {
6714 int pushregs = numregs;
6715
6716 if (TARGET_SHCOMPACT)
6717 ca->stack_regs += numregs;
6718 while (pushregs < NPARM_REGS (SImode) - 1
6719 && (CALL_COOKIE_INT_REG_GET
6720 (ca->call_cookie,
6721 NPARM_REGS (SImode) - pushregs)
6722 == 1))
6723 {
6724 ca->call_cookie
6725 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
6726 - pushregs, 1);
6727 pushregs++;
6728 }
6729 if (numregs == NPARM_REGS (SImode))
6730 ca->call_cookie
6731 |= CALL_COOKIE_INT_REG (0, 1)
6732 | CALL_COOKIE_STACKSEQ (numregs - 1);
6733 else
6734 ca->call_cookie
6735 |= CALL_COOKIE_STACKSEQ (numregs);
6736 }
6737 }
6738 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
6739 && (named || ! ca->prototype_p))
6740 {
6741 if (mode2 == SFmode && ca->free_single_fp_reg)
6742 ca->free_single_fp_reg = 0;
6743 else if (ca->arg_count[(int) SH_ARG_FLOAT]
6744 < NPARM_REGS (SFmode))
6745 {
6746 int numfpregs
6747 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
6748 NPARM_REGS (SFmode)
6749 - ca->arg_count[(int) SH_ARG_FLOAT]);
6750
6751 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
6752
6753 if (TARGET_SHCOMPACT && ! ca->prototype_p)
6754 {
6755 if (ca->outgoing && numregs > 0)
6756 do
6757 {
6758 ca->call_cookie
6759 |= (CALL_COOKIE_INT_REG
6760 (ca->arg_count[(int) SH_ARG_INT]
6761 - numregs + ((numfpregs - 2) / 2),
6762 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
6763 - numfpregs) / 2));
6764 }
6765 while (numfpregs -= 2);
6766 }
6767 else if (mode2 == SFmode && (named)
6768 && (ca->arg_count[(int) SH_ARG_FLOAT]
6769 < NPARM_REGS (SFmode)))
6770 ca->free_single_fp_reg
6771 = FIRST_FP_PARM_REG - numfpregs
6772 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
6773 }
6774 }
6775 return;
6776 }
6777
6778 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
6779 {
6780 /* Note that we've used the skipped register. */
6781 if (mode == SFmode && ca->free_single_fp_reg)
6782 {
6783 ca->free_single_fp_reg = 0;
6784 return;
6785 }
6786 /* When we have a DF after an SF, there's an SF register that get
6787 skipped in order to align the DF value. We note this skipped
6788 register, because the next SF value will use it, and not the
6789 SF that follows the DF. */
6790 if (mode == DFmode
6791 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
6792 {
6793 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
6794 + BASE_ARG_REG (mode));
6795 }
6796 }
6797
6798 if (! (TARGET_SH4 || ca->renesas_abi)
6799 || PASS_IN_REG_P (*ca, mode, type))
6800 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
6801 = (ROUND_REG (*ca, mode)
6802 + (mode == BLKmode
6803 ? ROUND_ADVANCE (int_size_in_bytes (type))
6804 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
45550790 6805}
6806
45550790 6807/* The Renesas calling convention doesn't quite fit into this scheme since
6808 the address is passed like an invisible argument, but one that is always
6809 passed in memory. */
6810static rtx
04f04b72 6811sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
45550790 6812{
6813 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
6814 return 0;
6815 return gen_rtx_REG (Pmode, 2);
6816}
6817
6644435d 6818/* Worker function for TARGET_RETURN_IN_MEMORY. */
6819
45550790 6820static bool
04f04b72 6821sh_return_in_memory (tree type, tree fndecl)
45550790 6822{
6823 if (TARGET_SH5)
6824 {
6825 if (TYPE_MODE (type) == BLKmode)
6826 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
6827 else
6828 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
6829 }
6830 else
6831 {
6832 return (TYPE_MODE (type) == BLKmode
6833 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
6834 && TREE_CODE (type) == RECORD_TYPE));
6835 }
6836}
6837
6838/* We actually emit the code in sh_expand_prologue. We used to use
6839 a static variable to flag that we need to emit this code, but that
6840 doesn't when inlining, when functions are deferred and then emitted
6841 later. Fortunately, we already have two flags that are part of struct
6842 function that tell if a function uses varargs or stdarg. */
6843static void
09a512b9 6844sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
6845 enum machine_mode mode,
6846 tree type,
6847 int *pretend_arg_size,
04f04b72 6848 int second_time ATTRIBUTE_UNUSED)
45550790 6849{
6850 if (! current_function_stdarg)
6851 abort ();
09a512b9 6852 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6853 {
6854 int named_parm_regs, anon_parm_regs;
6855
6856 named_parm_regs = (ROUND_REG (*ca, mode)
6857 + (mode == BLKmode
6858 ? ROUND_ADVANCE (int_size_in_bytes (type))
6859 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
6860 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
6861 if (anon_parm_regs > 0)
6862 *pretend_arg_size = anon_parm_regs * 4;
6863 }
45550790 6864}
6865
6866static bool
04f04b72 6867sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
45550790 6868{
6869 return TARGET_SH5;
6870}
6871
6872static bool
04f04b72 6873sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
45550790 6874{
6875 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
6876}
6877
6878
97595bfd 6879/* Define the offset between two registers, one to be eliminated, and
6880 the other its replacement, at the start of a routine. */
6881
6882int
04f04b72 6883initial_elimination_offset (int from, int to)
97595bfd 6884{
6885 int regs_saved;
87e19636 6886 int regs_saved_rounding = 0;
97595bfd 6887 int total_saved_regs_space;
9200a51c 6888 int total_auto_space;
8ded0752 6889 int save_flags = target_flags;
87e19636 6890 int copy_flags;
ed8483c0 6891 HARD_REG_SET live_regs_mask;
8af3db02 6892
6893 shmedia_space_reserved_for_target_registers = false;
ed8483c0 6894 regs_saved = calc_live_regs (&live_regs_mask);
87e19636 6895 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
8af3db02 6896
6897 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
6898 {
6899 shmedia_space_reserved_for_target_registers = true;
6900 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
6901 }
6902
87e19636 6903 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
6904 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6905 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
2e3d4844 6906
87e19636 6907 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
6908 copy_flags = target_flags;
8ded0752 6909 target_flags = save_flags;
b00564da 6910
87e19636 6911 total_saved_regs_space = regs_saved + regs_saved_rounding;
47c009e5 6912
97595bfd 6913 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
87e19636 6914 return total_saved_regs_space + total_auto_space
6915 + current_function_args_info.byref_regs * 8;
73401833 6916
97595bfd 6917 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
87e19636 6918 return total_saved_regs_space + total_auto_space
6919 + current_function_args_info.byref_regs * 8;
73401833 6920
6921 /* Initial gap between fp and sp is 0. */
97595bfd 6922 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
73401833 6923 return 0;
6924
ffa209e0 6925 if (from == RETURN_ADDRESS_POINTER_REGNUM
6926 && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
acda5809 6927 {
87e19636 6928 if (TARGET_SH5)
6929 {
41fafa66 6930 int n = total_saved_regs_space;
87e19636 6931 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
41fafa66 6932 save_schedule schedule;
6933 save_entry *entry;
87e19636 6934
6935 n += total_auto_space;
6936
6937 /* If it wasn't saved, there's not much we can do. */
ed8483c0 6938 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
87e19636 6939 return n;
6940
6941 target_flags = copy_flags;
6942
41fafa66 6943 sh5_schedule_saves (&live_regs_mask, &schedule, n);
6944 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6945 if (entry->reg == pr_reg)
6946 {
6947 target_flags = save_flags;
6948 return entry->offset;
6949 }
87e19636 6950 abort ();
6951 }
6952 else
acda5809 6953 return total_auto_space;
6954 }
ffa209e0 6955
97595bfd 6956 abort ();
6957}
73401833 6958\f
7b23765d 6959/* Handle machine specific pragmas to be semi-compatible with Renesas
1504eb7e 6960 compiler. */
47c009e5 6961
1fcd08b1 6962void
04f04b72 6963sh_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
47c009e5 6964{
1fcd08b1 6965 pragma_interrupt = 1;
6966}
b97b38c0 6967
1fcd08b1 6968void
04f04b72 6969sh_pr_trapa (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1fcd08b1 6970{
6971 pragma_interrupt = pragma_trapa = 1;
6972}
b97b38c0 6973
1fcd08b1 6974void
04f04b72 6975sh_pr_nosave_low_regs (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1fcd08b1 6976{
6977 pragma_nosave_low_regs = 1;
97595bfd 6978}
49f630e1 6979
6980/* Generate 'handle_interrupt' attribute for decls */
6981
8ee295a7 6982static void
04f04b72 6983sh_insert_attributes (tree node, tree *attributes)
49f630e1 6984{
49f630e1 6985 if (! pragma_interrupt
6986 || TREE_CODE (node) != FUNCTION_DECL)
6987 return;
6988
6989 /* We are only interested in fields. */
6990 if (TREE_CODE_CLASS (TREE_CODE (node)) != 'd')
6991 return;
6992
6993 /* Add a 'handle_interrupt' attribute. */
6994 * attributes = tree_cons (get_identifier ("interrupt_handler"), NULL, * attributes);
6995
6996 return;
6997}
6998
e3c541f0 6999/* Supported attributes:
15cb1799 7000
7001 interrupt_handler -- specifies this function is an interrupt handler.
7002
7003 sp_switch -- specifies an alternate stack for an interrupt handler
7004 to run on.
7005
ad87de1e 7006 trap_exit -- use a trapa to exit an interrupt function instead of
45550790 7007 an rte instruction.
7008
7009 renesas -- use Renesas calling/layout conventions (functions and
7010 structures).
7011
7012*/
15cb1799 7013
e3c541f0 7014const struct attribute_spec sh_attribute_table[] =
15cb1799 7015{
e3c541f0 7016 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
7017 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
7018 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
7019 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
45550790 7020 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
db281f5a 7021#ifdef SYMBIAN
7022 /* Symbian support adds three new attributes:
7023 dllexport - for exporting a function/variable that will live in a dll
7024 dllimport - for importing a function/variable from a dll
7025
7026 Microsoft allows multiple declspecs in one __declspec, separating
7027 them with spaces. We do NOT support this. Instead, use __declspec
7028 multiple times. */
7029 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
7030 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
7031#endif
e3c541f0 7032 { NULL, 0, 0, false, false, false, NULL }
7033};
15cb1799 7034
e3c541f0 7035/* Handle an "interrupt_handler" attribute; arguments as in
7036 struct attribute_spec.handler. */
7037static tree
04f04b72 7038sh_handle_interrupt_handler_attribute (tree *node, tree name,
7039 tree args ATTRIBUTE_UNUSED,
7040 int flags ATTRIBUTE_UNUSED,
7041 bool *no_add_attrs)
e3c541f0 7042{
7043 if (TREE_CODE (*node) != FUNCTION_DECL)
15cb1799 7044 {
e3c541f0 7045 warning ("`%s' attribute only applies to functions",
7046 IDENTIFIER_POINTER (name));
7047 *no_add_attrs = true;
15cb1799 7048 }
154b29aa 7049 else if (TARGET_SHCOMPACT)
7050 {
7051 error ("attribute interrupt_handler is not compatible with -m5-compact");
7052 *no_add_attrs = true;
7053 }
15cb1799 7054
e3c541f0 7055 return NULL_TREE;
7056}
7057
7058/* Handle an "sp_switch" attribute; arguments as in
7059 struct attribute_spec.handler. */
7060static tree
04f04b72 7061sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
7062 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
e3c541f0 7063{
7064 if (TREE_CODE (*node) != FUNCTION_DECL)
7065 {
7066 warning ("`%s' attribute only applies to functions",
7067 IDENTIFIER_POINTER (name));
7068 *no_add_attrs = true;
7069 }
7070 else if (!pragma_interrupt)
15cb1799 7071 {
7072 /* The sp_switch attribute only has meaning for interrupt functions. */
e3c541f0 7073 warning ("`%s' attribute only applies to interrupt functions",
7074 IDENTIFIER_POINTER (name));
7075 *no_add_attrs = true;
7076 }
7077 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
7078 {
15cb1799 7079 /* The argument must be a constant string. */
e3c541f0 7080 warning ("`%s' attribute argument not a string constant",
7081 IDENTIFIER_POINTER (name));
7082 *no_add_attrs = true;
7083 }
7084 else
7085 {
cbe4c3a5 7086 sp_switch = gen_rtx_SYMBOL_REF (VOIDmode,
7087 TREE_STRING_POINTER (TREE_VALUE (args)));
15cb1799 7088 }
7089
e3c541f0 7090 return NULL_TREE;
7091}
7092
7093/* Handle an "trap_exit" attribute; arguments as in
7094 struct attribute_spec.handler. */
7095static tree
04f04b72 7096sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
7097 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
e3c541f0 7098{
7099 if (TREE_CODE (*node) != FUNCTION_DECL)
7100 {
7101 warning ("`%s' attribute only applies to functions",
7102 IDENTIFIER_POINTER (name));
7103 *no_add_attrs = true;
7104 }
7105 else if (!pragma_interrupt)
15cb1799 7106 {
7107 /* The trap_exit attribute only has meaning for interrupt functions. */
e3c541f0 7108 warning ("`%s' attribute only applies to interrupt functions",
7109 IDENTIFIER_POINTER (name));
7110 *no_add_attrs = true;
7111 }
7112 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
7113 {
15cb1799 7114 /* The argument must be a constant integer. */
e3c541f0 7115 warning ("`%s' attribute argument not an integer constant",
7116 IDENTIFIER_POINTER (name));
7117 *no_add_attrs = true;
7118 }
7119 else
7120 {
15cb1799 7121 trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args));
15cb1799 7122 }
b7dbbdb2 7123
e3c541f0 7124 return NULL_TREE;
15cb1799 7125}
7126
45550790 7127static tree
04f04b72 7128sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
7129 tree name ATTRIBUTE_UNUSED,
7130 tree args ATTRIBUTE_UNUSED,
7131 int flags ATTRIBUTE_UNUSED,
7132 bool *no_add_attrs ATTRIBUTE_UNUSED)
45550790 7133{
7134 return NULL_TREE;
7135}
7136
7137/* True if __attribute__((renesas)) or -mrenesas. */
7138int
04f04b72 7139sh_attr_renesas_p (tree td)
45550790 7140{
7141 if (TARGET_HITACHI)
7142 return 1;
7143 if (td == 0)
7144 return 0;
7145 if (DECL_P (td))
7146 td = TREE_TYPE (td);
7147 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
7148 != NULL_TREE);
7149}
7150
7151/* True if __attribute__((renesas)) or -mrenesas, for the current
7152 function. */
7153int
04f04b72 7154sh_cfun_attr_renesas_p (void)
45550790 7155{
7156 return sh_attr_renesas_p (current_function_decl);
7157}
7158
5df3d11f 7159int
04f04b72 7160sh_cfun_interrupt_handler_p (void)
5df3d11f 7161{
7162 return (lookup_attribute ("interrupt_handler",
7163 DECL_ATTRIBUTES (current_function_decl))
7164 != NULL_TREE);
7165}
133479bd 7166
7167/* ??? target_switches in toplev.c is static, hence we have to duplicate it. */
7168static const struct
7169{
7170 const char *const name;
7171 const int value;
7172 const char *const description;
7173}
7174sh_target_switches[] = TARGET_SWITCHES;
7175#define target_switches sh_target_switches
7176
7177/* Like default_pch_valid_p, but take flag_mask into account. */
7178const char *
7179sh_pch_valid_p (const void *data_p, size_t len)
7180{
7181 const char *data = (const char *)data_p;
7182 const char *flag_that_differs = NULL;
7183 size_t i;
7184 int old_flags;
7185 int flag_mask
7186 = (SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | HARD_SH4_BIT | FPU_SINGLE_BIT
7187 | SH4_BIT | HITACHI_BIT | LITTLE_ENDIAN_BIT);
7188
7189 /* -fpic and -fpie also usually make a PCH invalid. */
7190 if (data[0] != flag_pic)
7191 return _("created and used with different settings of -fpic");
7192 if (data[1] != flag_pie)
7193 return _("created and used with different settings of -fpie");
7194 data += 2;
7195
7196 /* Check target_flags. */
7197 memcpy (&old_flags, data, sizeof (target_flags));
7198 if (((old_flags ^ target_flags) & flag_mask) != 0)
7199 {
7200 for (i = 0; i < ARRAY_SIZE (target_switches); i++)
7201 {
7202 int bits;
7203
7204 bits = target_switches[i].value;
7205 if (bits < 0)
7206 bits = -bits;
7207 bits &= flag_mask;
7208 if ((target_flags & bits) != (old_flags & bits))
7209 {
7210 flag_that_differs = target_switches[i].name;
7211 goto make_message;
7212 }
7213 }
7214 abort ();
7215 }
7216 data += sizeof (target_flags);
7217 len -= sizeof (target_flags);
7218
7219 /* Check string options. */
7220#ifdef TARGET_OPTIONS
7221 for (i = 0; i < ARRAY_SIZE (target_options); i++)
7222 {
7223 const char *str = *target_options[i].variable;
7224 size_t l;
7225 if (! str)
7226 str = "";
7227 l = strlen (str) + 1;
7228 if (len < l || memcmp (data, str, l) != 0)
7229 {
7230 flag_that_differs = target_options[i].prefix;
7231 goto make_message;
7232 }
7233 data += l;
7234 len -= l;
7235 }
7236#endif
7237
7238 return NULL;
7239
7240 make_message:
7241 {
7242 char *r;
7243 asprintf (&r, _("created and used with differing settings of `-m%s'"),
7244 flag_that_differs);
7245 if (r == NULL)
7246 return _("out of memory");
7247 return r;
7248 }
7249}
97595bfd 7250\f
73401833 7251/* Predicates used by the templates. */
97595bfd 7252
73401833 7253/* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
7254 Used only in general_movsrc_operand. */
97595bfd 7255
73401833 7256int
04f04b72 7257system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
97595bfd 7258{
73401833 7259 switch (REGNO (op))
97595bfd 7260 {
73401833 7261 case PR_REG:
7262 case MACL_REG:
7263 case MACH_REG:
7264 return 1;
97595bfd 7265 }
73401833 7266 return 0;
97595bfd 7267}
97595bfd 7268
7269/* Returns 1 if OP can be source of a simple move operation.
7270 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
1504eb7e 7271 invalid as are subregs of system registers. */
97595bfd 7272
7273int
04f04b72 7274general_movsrc_operand (rtx op, enum machine_mode mode)
97595bfd 7275{
42e2009a 7276 if (GET_CODE (op) == MEM)
7277 {
7278 rtx inside = XEXP (op, 0);
7279 if (GET_CODE (inside) == CONST)
7280 inside = XEXP (inside, 0);
97595bfd 7281
42e2009a 7282 if (GET_CODE (inside) == LABEL_REF)
7283 return 1;
2e3d4844 7284
42e2009a 7285 if (GET_CODE (inside) == PLUS
73401833 7286 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
7287 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
42e2009a 7288 return 1;
1504eb7e 7289
7290 /* Only post inc allowed. */
5b94bdcd 7291 if (GET_CODE (inside) == PRE_DEC)
42e2009a 7292 return 0;
42e2009a 7293 }
97595bfd 7294
7295 if ((mode == QImode || mode == HImode)
7296 && (GET_CODE (op) == SUBREG
7297 && GET_CODE (XEXP (op, 0)) == REG
7298 && system_reg_operand (XEXP (op, 0), mode)))
7299 return 0;
7300
97595bfd 7301 return general_operand (op, mode);
47c009e5 7302}
7303
97595bfd 7304/* Returns 1 if OP can be a destination of a move.
7305 Same as general_operand, but no preinc allowed. */
7306
47c009e5 7307int
04f04b72 7308general_movdst_operand (rtx op, enum machine_mode mode)
47c009e5 7309{
1504eb7e 7310 /* Only pre dec allowed. */
5b94bdcd 7311 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
97595bfd 7312 return 0;
f3d93547 7313
97595bfd 7314 return general_operand (op, mode);
7315}
7316
97595bfd 7317/* Returns 1 if OP is a normal arithmetic register. */
7318
7319int
04f04b72 7320arith_reg_operand (rtx op, enum machine_mode mode)
97595bfd 7321{
7322 if (register_operand (op, mode))
7323 {
1b6897f5 7324 int regno;
7325
97595bfd 7326 if (GET_CODE (op) == REG)
1b6897f5 7327 regno = REGNO (op);
7328 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
7329 regno = REGNO (SUBREG_REG (op));
7330 else
7331 return 1;
7332
1b61190c 7333 return (regno != T_REG && regno != PR_REG
87e19636 7334 && ! TARGET_REGISTER_P (regno)
1b61190c 7335 && (regno != FPUL_REG || TARGET_SH4)
7336 && regno != MACH_REG && regno != MACL_REG);
7337 }
7338 return 0;
7339}
7340
e3fac27d 7341/* Like above, but for DImode destinations: forbid paradoxical DImode subregs,
7342 because this would lead to missing sign extensions when truncating from
7343 DImode to SImode. */
7344int
04f04b72 7345arith_reg_dest (rtx op, enum machine_mode mode)
e3fac27d 7346{
7347 if (mode == DImode && GET_CODE (op) == SUBREG
7348 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
7349 return 0;
7350 return arith_reg_operand (op, mode);
7351}
7352
f4dba476 7353int
04f04b72 7354int_gpr_dest (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
f4dba476 7355{
7356 enum machine_mode op_mode = GET_MODE (op);
7357
7358 if (GET_MODE_CLASS (op_mode) != MODE_INT
7359 || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
7360 return 0;
7361 if (! reload_completed)
7362 return 0;
7363 return true_regnum (op) <= LAST_GENERAL_REG;
7364}
7365
1b61190c 7366int
04f04b72 7367fp_arith_reg_operand (rtx op, enum machine_mode mode)
1b61190c 7368{
7369 if (register_operand (op, mode))
7370 {
7371 int regno;
7372
7373 if (GET_CODE (op) == REG)
7374 regno = REGNO (op);
7375 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
7376 regno = REGNO (SUBREG_REG (op));
7377 else
7378 return 1;
7379
0137dce2 7380 return (regno >= FIRST_PSEUDO_REGISTER
e2142b04 7381 || FP_REGISTER_P (regno));
97595bfd 7382 }
7383 return 0;
7384}
7385
97595bfd 7386/* Returns 1 if OP is a valid source operand for an arithmetic insn. */
7387
7388int
04f04b72 7389arith_operand (rtx op, enum machine_mode mode)
97595bfd 7390{
7391 if (arith_reg_operand (op, mode))
7392 return 1;
7393
87e19636 7394 if (TARGET_SHMEDIA)
7395 {
7396 /* FIXME: We should be checking whether the CONST_INT fits in a
af2c1324 7397 CONST_OK_FOR_I16 here, but this causes reload_cse to crash when
87e19636 7398 attempting to transform a sequence of two 64-bit sets of the
7399 same register from literal constants into a set and an add,
7400 when the difference is too wide for an add. */
7401 if (GET_CODE (op) == CONST_INT
af2c1324 7402 || EXTRA_CONSTRAINT_C16 (op))
87e19636 7403 return 1;
7404 else
7405 return 0;
7406 }
af2c1324 7407 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (op)))
73401833 7408 return 1;
7409
97595bfd 7410 return 0;
7411}
7412
37e141e6 7413/* Returns 1 if OP is a valid source operand for a compare insn. */
7414
7415int
04f04b72 7416arith_reg_or_0_operand (rtx op, enum machine_mode mode)
37e141e6 7417{
7418 if (arith_reg_operand (op, mode))
7419 return 1;
7420
af2c1324 7421 if (EXTRA_CONSTRAINT_Z (op))
73401833 7422 return 1;
7423
37e141e6 7424 return 0;
7425}
7426
87e19636 7427/* Return 1 if OP is a valid source operand for an SHmedia operation
7428 that takes either a register or a 6-bit immediate. */
7429
7430int
04f04b72 7431shmedia_6bit_operand (rtx op, enum machine_mode mode)
87e19636 7432{
7433 return (arith_reg_operand (op, mode)
af2c1324 7434 || (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I06 (INTVAL (op))));
87e19636 7435}
7436
1504eb7e 7437/* Returns 1 if OP is a valid source operand for a logical operation. */
97595bfd 7438
7439int
04f04b72 7440logical_operand (rtx op, enum machine_mode mode)
97595bfd 7441{
7442 if (arith_reg_operand (op, mode))
7443 return 1;
7444
87e19636 7445 if (TARGET_SHMEDIA)
7446 {
af2c1324 7447 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I10 (INTVAL (op)))
87e19636 7448 return 1;
7449 else
7450 return 0;
7451 }
af2c1324 7452 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K08 (INTVAL (op)))
73401833 7453 return 1;
7454
97595bfd 7455 return 0;
47c009e5 7456}
f3d93547 7457
e3fac27d 7458int
04f04b72 7459and_operand (rtx op, enum machine_mode mode)
e3fac27d 7460{
7461 if (logical_operand (op, mode))
7462 return 1;
7463
7464 /* Check mshflo.l / mshflhi.l opportunities. */
7465 if (TARGET_SHMEDIA
7466 && mode == DImode
7467 && GET_CODE (op) == CONST_INT
af2c1324 7468 && CONST_OK_FOR_J16 (INTVAL (op)))
d767e27e 7469 return 1;
e3fac27d 7470
7471 return 0;
7472}
7473
b00564da 7474/* Nonzero if OP is a floating point value with value 0.0. */
7475
7476int
04f04b72 7477fp_zero_operand (rtx op)
f3d93547 7478{
b00564da 7479 REAL_VALUE_TYPE r;
f3d93547 7480
b00564da 7481 if (GET_MODE (op) != SFmode)
7482 return 0;
7483
7484 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
e6c94d0d 7485 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
f3d93547 7486}
7487
b00564da 7488/* Nonzero if OP is a floating point value with value 1.0. */
f3d93547 7489
7490int
04f04b72 7491fp_one_operand (rtx op)
f3d93547 7492{
b00564da 7493 REAL_VALUE_TYPE r;
7494
7495 if (GET_MODE (op) != SFmode)
7496 return 0;
7497
7498 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
7499 return REAL_VALUES_EQUAL (r, dconst1);
f3d93547 7500}
8ded0752 7501
18862b5a 7502/* For -m4 and -m4-single-only, mode switching is used. If we are
7503 compiling without -mfmovd, movsf_ie isn't taken into account for
7504 mode switching. We could check in machine_dependent_reorg for
7505 cases where we know we are in single precision mode, but there is
7506 interface to find that out during reload, so we must avoid
7507 choosing an fldi alternative during reload and thus failing to
7508 allocate a scratch register for the constant loading. */
7509int
04f04b72 7510fldi_ok (void)
18862b5a 7511{
7512 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
7513}
7514
1b61190c 7515int
04f04b72 7516tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1b61190c 7517{
7518 enum rtx_code code = GET_CODE (op);
7519 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
7520}
7521
7522int
04f04b72 7523fpscr_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1b61190c 7524{
7525 return (GET_CODE (op) == REG && REGNO (op) == FPSCR_REG
7526 && GET_MODE (op) == PSImode);
7527}
7528
087cf8ba 7529int
04f04b72 7530fpul_operand (rtx op, enum machine_mode mode)
087cf8ba 7531{
87e19636 7532 if (TARGET_SHMEDIA)
7533 return fp_arith_reg_operand (op, mode);
7534
087cf8ba 7535 return (GET_CODE (op) == REG
7536 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
7537 && GET_MODE (op) == mode);
7538}
7539
1b3a64a8 7540int
04f04b72 7541symbol_ref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1b3a64a8 7542{
7543 return (GET_CODE (op) == SYMBOL_REF);
7544}
7545
cec78553 7546/* Return the TLS type for TLS symbols, 0 for otherwise. */
7547int
04f04b72 7548tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
cec78553 7549{
cec78553 7550 if (GET_CODE (op) != SYMBOL_REF)
7551 return 0;
2fb8cf90 7552 return SYMBOL_REF_TLS_MODEL (op);
cec78553 7553}
7554
1b61190c 7555int
04f04b72 7556commutative_float_operator (rtx op, enum machine_mode mode)
1b61190c 7557{
7558 if (GET_MODE (op) != mode)
7559 return 0;
7560 switch (GET_CODE (op))
7561 {
7562 case PLUS:
7563 case MULT:
7564 return 1;
b7dbbdb2 7565 default:
7566 break;
1b61190c 7567 }
7568 return 0;
7569}
7570
7571int
04f04b72 7572noncommutative_float_operator (rtx op, enum machine_mode mode)
1b61190c 7573{
7574 if (GET_MODE (op) != mode)
7575 return 0;
7576 switch (GET_CODE (op))
7577 {
7578 case MINUS:
7579 case DIV:
7580 return 1;
b7dbbdb2 7581 default:
7582 break;
1b61190c 7583 }
7584 return 0;
7585}
7586
d3b29bbd 7587int
04f04b72 7588unary_float_operator (rtx op, enum machine_mode mode)
d3b29bbd 7589{
7590 if (GET_MODE (op) != mode)
7591 return 0;
7592 switch (GET_CODE (op))
7593 {
7594 case ABS:
7595 case NEG:
7596 case SQRT:
7597 return 1;
7598 default:
7599 break;
7600 }
7601 return 0;
7602}
7603
1b61190c 7604int
04f04b72 7605binary_float_operator (rtx op, enum machine_mode mode)
1b61190c 7606{
7607 if (GET_MODE (op) != mode)
7608 return 0;
7609 switch (GET_CODE (op))
7610 {
7611 case PLUS:
7612 case MINUS:
7613 case MULT:
7614 case DIV:
7615 return 1;
b7dbbdb2 7616 default:
7617 break;
1b61190c 7618 }
7619 return 0;
7620}
87e19636 7621
b7265200 7622int
04f04b72 7623binary_logical_operator (rtx op, enum machine_mode mode)
b7265200 7624{
7625 if (GET_MODE (op) != mode)
7626 return 0;
7627 switch (GET_CODE (op))
7628 {
7629 case IOR:
7630 case AND:
7631 case XOR:
7632 return 1;
7633 default:
7634 break;
7635 }
7636 return 0;
7637}
7638
3c4bc54e 7639int
04f04b72 7640equality_comparison_operator (rtx op, enum machine_mode mode)
3c4bc54e 7641{
7642 return ((mode == VOIDmode || GET_MODE (op) == mode)
7643 && (GET_CODE (op) == EQ || GET_CODE (op) == NE));
7644}
7645
d767e27e 7646int
7647greater_comparison_operator (rtx op, enum machine_mode mode)
3c4bc54e 7648{
7649 if (mode != VOIDmode && GET_MODE (op) == mode)
7650 return 0;
7651 switch (GET_CODE (op))
7652 {
7653 case GT:
7654 case GE:
7655 case GTU:
7656 case GEU:
7657 return 1;
7658 default:
7659 return 0;
7660 }
7661}
7662
d767e27e 7663int
7664less_comparison_operator (rtx op, enum machine_mode mode)
3c4bc54e 7665{
7666 if (mode != VOIDmode && GET_MODE (op) == mode)
7667 return 0;
7668 switch (GET_CODE (op))
7669 {
7670 case LT:
7671 case LE:
7672 case LTU:
7673 case LEU:
7674 return 1;
7675 default:
7676 return 0;
7677 }
7678}
7679
87e19636 7680/* Accept pseudos and branch target registers. */
7681int
04f04b72 7682target_reg_operand (rtx op, enum machine_mode mode)
87e19636 7683{
7684 if (mode != DImode
7685 || GET_MODE (op) != DImode)
7686 return 0;
7687
7688 if (GET_CODE (op) == SUBREG)
7689 op = XEXP (op, 0);
7690
7691 if (GET_CODE (op) != REG)
7692 return 0;
7693
7694 /* We must protect ourselves from matching pseudos that are virtual
7695 register, because they will eventually be replaced with hardware
7696 registers that aren't branch-target registers. */
7697 if (REGNO (op) > LAST_VIRTUAL_REGISTER
7698 || TARGET_REGISTER_P (REGNO (op)))
7699 return 1;
7700
7701 return 0;
7702}
7703
7704/* Same as target_reg_operand, except that label_refs and symbol_refs
7705 are accepted before reload. */
7706int
04f04b72 7707target_operand (rtx op, enum machine_mode mode)
87e19636 7708{
7709 if (mode != DImode)
7710 return 0;
7711
7712 if ((GET_MODE (op) == DImode || GET_MODE (op) == VOIDmode)
af2c1324 7713 && EXTRA_CONSTRAINT_Csy (op))
87e19636 7714 return ! reload_completed;
7715
7716 return target_reg_operand (op, mode);
7717}
7718
e3fac27d 7719int
04f04b72 7720mextr_bit_offset (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
e3fac27d 7721{
7722 HOST_WIDE_INT i;
7723
7724 if (GET_CODE (op) != CONST_INT)
7725 return 0;
7726 i = INTVAL (op);
d767e27e 7727 return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
e3fac27d 7728}
7729
7730int
04f04b72 7731extend_reg_operand (rtx op, enum machine_mode mode)
e3fac27d 7732{
7733 return (GET_CODE (op) == TRUNCATE
7734 ? arith_operand
7735 : arith_reg_operand) (op, mode);
7736}
7737
f4dba476 7738int
04f04b72 7739trunc_hi_operand (rtx op, enum machine_mode mode)
f4dba476 7740{
7741 enum machine_mode op_mode = GET_MODE (op);
7742
7743 if (op_mode != SImode && op_mode != DImode
7744 && op_mode != V4HImode && op_mode != V2SImode)
7745 return 0;
7746 return extend_reg_operand (op, mode);
7747}
7748
e3fac27d 7749int
04f04b72 7750extend_reg_or_0_operand (rtx op, enum machine_mode mode)
e3fac27d 7751{
7752 return (GET_CODE (op) == TRUNCATE
7753 ? arith_operand
7754 : arith_reg_or_0_operand) (op, mode);
7755}
7756
645de543 7757int
04f04b72 7758general_extend_operand (rtx op, enum machine_mode mode)
645de543 7759{
7760 return (GET_CODE (op) == TRUNCATE
7761 ? arith_operand
7762 : nonimmediate_operand) (op, mode);
7763}
7764
7765int
04f04b72 7766inqhi_operand (rtx op, enum machine_mode mode)
645de543 7767{
7768 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
7769 return 0;
7770 op = XEXP (op, 0);
7771 /* Can't use true_regnum here because copy_cost wants to know about
7772 SECONDARY_INPUT_RELOAD_CLASS. */
7773 return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op));
7774}
7775
e3fac27d 7776int
04f04b72 7777sh_rep_vec (rtx v, enum machine_mode mode)
e3fac27d 7778{
7779 int i;
7780 rtx x, y;
7781
7782 if ((GET_CODE (v) != CONST_VECTOR && GET_CODE (v) != PARALLEL)
7783 || (GET_MODE (v) != mode && mode != VOIDmode))
7784 return 0;
7785 i = XVECLEN (v, 0) - 2;
7786 x = XVECEXP (v, 0, i + 1);
7787 if (GET_MODE_UNIT_SIZE (mode) == 1)
7788 {
7789 y = XVECEXP (v, 0, i);
d767e27e 7790 for (i -= 2; i >= 0; i -= 2)
e3fac27d 7791 if (! rtx_equal_p (XVECEXP (v, 0, i + 1), x)
7792 || ! rtx_equal_p (XVECEXP (v, 0, i), y))
3c4bc54e 7793 return 0;
e3fac27d 7794 }
7795 else
7796 for (; i >= 0; i--)
7797 if (XVECEXP (v, 0, i) != x)
3c4bc54e 7798 return 0;
e3fac27d 7799 return 1;
7800}
7801
7802/* Determine if V is a constant vector matching MODE with only one element
7803 that is not a sign extension. Two byte-sized elements count as one. */
7804int
04f04b72 7805sh_1el_vec (rtx v, enum machine_mode mode)
e3fac27d 7806{
7807 int unit_size;
7808 int i, last, least, sign_ix;
7809 rtx sign;
7810
7811 if (GET_CODE (v) != CONST_VECTOR
7812 || (GET_MODE (v) != mode && mode != VOIDmode))
7813 return 0;
0924aa1d 7814 /* Determine numbers of last and of least significant elements. */
e3fac27d 7815 last = XVECLEN (v, 0) - 1;
7816 least = TARGET_LITTLE_ENDIAN ? 0 : last;
7817 if (GET_CODE (XVECEXP (v, 0, least)) != CONST_INT)
7818 return 0;
7819 sign_ix = least;
7820 if (GET_MODE_UNIT_SIZE (mode) == 1)
7821 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
7822 if (GET_CODE (XVECEXP (v, 0, sign_ix)) != CONST_INT)
7823 return 0;
7824 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (v));
7825 sign = (INTVAL (XVECEXP (v, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
7826 ? constm1_rtx : const0_rtx);
7827 i = XVECLEN (v, 0) - 1;
7828 do
7829 if (i != least && i != sign_ix && XVECEXP (v, 0, i) != sign)
7830 return 0;
7831 while (--i);
7832 return 1;
7833}
7834
7835int
04f04b72 7836sh_const_vec (rtx v, enum machine_mode mode)
e3fac27d 7837{
7838 int i;
7839
7840 if (GET_CODE (v) != CONST_VECTOR
7841 || (GET_MODE (v) != mode && mode != VOIDmode))
7842 return 0;
7843 i = XVECLEN (v, 0) - 1;
7844 for (; i >= 0; i--)
7845 if (GET_CODE (XVECEXP (v, 0, i)) != CONST_INT)
7846 return 0;
7847 return 1;
7848}
8ded0752 7849\f
9eaab178 7850/* Return the destination address of a branch. */
8ded0752 7851
b7dbbdb2 7852static int
04f04b72 7853branch_dest (rtx branch)
8ded0752 7854{
9eaab178 7855 rtx dest = SET_SRC (PATTERN (branch));
7856 int dest_uid;
8ded0752 7857
7858 if (GET_CODE (dest) == IF_THEN_ELSE)
7859 dest = XEXP (dest, 1);
7860 dest = XEXP (dest, 0);
7861 dest_uid = INSN_UID (dest);
47fc0706 7862 return INSN_ADDRESSES (dest_uid);
8ded0752 7863}
72bccaaa 7864\f
808a491c 7865/* Return nonzero if REG is not used after INSN.
72bccaaa 7866 We assume REG is a reload reg, and therefore does
e020b473 7867 not live past labels. It may live past calls or jumps though. */
72bccaaa 7868int
04f04b72 7869reg_unused_after (rtx reg, rtx insn)
72bccaaa 7870{
0f7bb88e 7871 enum rtx_code code;
72bccaaa 7872 rtx set;
7873
7874 /* If the reg is set by this instruction, then it is safe for our
7875 case. Disregard the case where this is a store to memory, since
7876 we are checking a register used in the store address. */
7877 set = single_set (insn);
7878 if (set && GET_CODE (SET_DEST (set)) != MEM
7879 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7880 return 1;
7881
b7dbbdb2 7882 while ((insn = NEXT_INSN (insn)))
72bccaaa 7883 {
6720e96c 7884 rtx set;
7885 if (!INSN_P (insn))
7886 continue;
7887
72bccaaa 7888 code = GET_CODE (insn);
0f7bb88e 7889
87faf2d3 7890#if 0
7891 /* If this is a label that existed before reload, then the register
7892 if dead here. However, if this is a label added by reorg, then
7893 the register may still be live here. We can't tell the difference,
7894 so we just ignore labels completely. */
0f7bb88e 7895 if (code == CODE_LABEL)
72bccaaa 7896 return 1;
87faf2d3 7897 /* else */
7898#endif
72bccaaa 7899
e020b473 7900 if (code == JUMP_INSN)
7901 return 0;
7902
0f7bb88e 7903 /* If this is a sequence, we must handle them all at once.
7904 We could have for instance a call that sets the target register,
ebb11c7b 7905 and an insn in a delay slot that uses the register. In this case,
0f7bb88e 7906 we must return 0. */
e020b473 7907 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
72bccaaa 7908 {
0f7bb88e 7909 int i;
7910 int retval = 0;
7911
7912 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7913 {
7914 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
7915 rtx set = single_set (this_insn);
7916
7917 if (GET_CODE (this_insn) == CALL_INSN)
7918 code = CALL_INSN;
fafe466d 7919 else if (GET_CODE (this_insn) == JUMP_INSN)
7920 {
7921 if (INSN_ANNULLED_BRANCH_P (this_insn))
7922 return 0;
7923 code = JUMP_INSN;
7924 }
72bccaaa 7925
0f7bb88e 7926 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
7927 return 0;
7928 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7929 {
7930 if (GET_CODE (SET_DEST (set)) != MEM)
7931 retval = 1;
7932 else
7933 return 0;
7934 }
7935 if (set == 0
7936 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
7937 return 0;
7938 }
7939 if (retval == 1)
7940 return 1;
fafe466d 7941 else if (code == JUMP_INSN)
7942 return 0;
0f7bb88e 7943 }
72bccaaa 7944
6720e96c 7945 set = single_set (insn);
7946 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
7947 return 0;
7948 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
7949 return GET_CODE (SET_DEST (set)) != MEM;
7950 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
7951 return 0;
0f7bb88e 7952
7953 if (code == CALL_INSN && call_used_regs[REGNO (reg)])
7954 return 1;
72bccaaa 7955 }
7956 return 1;
7957}
1b61190c 7958\f
26576132 7959#include "ggc.h"
1b61190c 7960
1f3233d1 7961static GTY(()) rtx fpscr_rtx;
1b61190c 7962rtx
04f04b72 7963get_fpscr_rtx (void)
1b61190c 7964{
1b61190c 7965 if (! fpscr_rtx)
7966 {
407d9153 7967 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
1b61190c 7968 REG_USERVAR_P (fpscr_rtx) = 1;
1b61190c 7969 mark_user_reg (fpscr_rtx);
7970 }
7971 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
7972 mark_user_reg (fpscr_rtx);
7973 return fpscr_rtx;
7974}
7975
7976void
04f04b72 7977emit_sf_insn (rtx pat)
1b61190c 7978{
1b61190c 7979 emit_insn (pat);
1b61190c 7980}
7981
7982void
04f04b72 7983emit_df_insn (rtx pat)
1b61190c 7984{
1b61190c 7985 emit_insn (pat);
1b61190c 7986}
7987
7988void
04f04b72 7989expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
1b61190c 7990{
7991 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
7992}
7993
7994void
04f04b72 7995expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
1b61190c 7996{
7997 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
7998 get_fpscr_rtx ()));
7999}
8000
8001void
04f04b72 8002expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
1b61190c 8003{
8004 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8005}
8006
8007void
04f04b72 8008expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
1b61190c 8009{
8010 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
d767e27e 8011 get_fpscr_rtx ()));
1b61190c 8012}
1b61190c 8013\f
8014/* ??? gcc does flow analysis strictly after common subexpression
0924aa1d 8015 elimination. As a result, common subexpression elimination fails
1b61190c 8016 when there are some intervening statements setting the same register.
8017 If we did nothing about this, this would hurt the precision switching
8018 for SH4 badly. There is some cse after reload, but it is unable to
8019 undo the extra register pressure from the unused instructions, and
8020 it cannot remove auto-increment loads.
8021
8022 A C code example that shows this flow/cse weakness for (at least) SH
8023 and sparc (as of gcc ss-970706) is this:
8024
8025double
8026f(double a)
8027{
8028 double d;
8029 d = 0.1;
8030 a += d;
8031 d = 1.1;
8032 d = 0.1;
8033 a *= d;
8034 return a;
8035}
8036
8037 So we add another pass before common subexpression elimination, to
8038 remove assignments that are dead due to a following assignment in the
8039 same basic block. */
8040
1b61190c 8041static void
04f04b72 8042mark_use (rtx x, rtx *reg_set_block)
1b61190c 8043{
8044 enum rtx_code code;
8045
8046 if (! x)
8047 return;
8048 code = GET_CODE (x);
8049 switch (code)
8050 {
8051 case REG:
8052 {
8053 int regno = REGNO (x);
8054 int nregs = (regno < FIRST_PSEUDO_REGISTER
8055 ? HARD_REGNO_NREGS (regno, GET_MODE (x))
8056 : 1);
8057 do
8058 {
8059 reg_set_block[regno + nregs - 1] = 0;
8060 }
8061 while (--nregs);
8062 break;
8063 }
8064 case SET:
8065 {
8066 rtx dest = SET_DEST (x);
8067
8068 if (GET_CODE (dest) == SUBREG)
8069 dest = SUBREG_REG (dest);
8070 if (GET_CODE (dest) != REG)
8071 mark_use (dest, reg_set_block);
8072 mark_use (SET_SRC (x), reg_set_block);
8073 break;
8074 }
8075 case CLOBBER:
8076 break;
8077 default:
8078 {
d2ca078f 8079 const char *fmt = GET_RTX_FORMAT (code);
1b61190c 8080 int i, j;
8081 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8082 {
8083 if (fmt[i] == 'e')
8084 mark_use (XEXP (x, i), reg_set_block);
8085 else if (fmt[i] == 'E')
8086 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8087 mark_use (XVECEXP (x, i, j), reg_set_block);
8088 }
8089 break;
8090 }
8091 }
8092}
18862b5a 8093\f
04f04b72 8094static rtx get_free_reg (HARD_REG_SET);
18862b5a 8095
8096/* This function returns a register to use to load the address to load
8097 the fpscr from. Currently it always returns r1 or r7, but when we are
8098 able to use pseudo registers after combine, or have a better mechanism
8099 for choosing a register, it should be done here. */
8100/* REGS_LIVE is the liveness information for the point for which we
8101 need this allocation. In some bare-bones exit blocks, r1 is live at the
8102 start. We can even have all of r0..r3 being live:
8103__complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
8104 INSN before which new insns are placed with will clobber the register
8105 we return. If a basic block consists only of setting the return value
8106 register to a pseudo and using that register, the return value is not
8107 live before or after this block, yet we we'll insert our insns right in
8108 the middle. */
1b61190c 8109
18862b5a 8110static rtx
04f04b72 8111get_free_reg (HARD_REG_SET regs_live)
1b61190c 8112{
18862b5a 8113 if (! TEST_HARD_REG_BIT (regs_live, 1))
8114 return gen_rtx_REG (Pmode, 1);
1b61190c 8115
18862b5a 8116 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
8117 there shouldn't be anything but a jump before the function end. */
8118 if (! TEST_HARD_REG_BIT (regs_live, 7))
8119 return gen_rtx_REG (Pmode, 7);
1b61190c 8120
18862b5a 8121 abort ();
8122}
1b61190c 8123
18862b5a 8124/* This function will set the fpscr from memory.
8125 MODE is the mode we are setting it to. */
8126void
04f04b72 8127fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
18862b5a 8128{
8129 enum attr_fp_mode fp_mode = mode;
18862b5a 8130 rtx addr_reg = get_free_reg (regs_live);
8131
ab5ad604 8132 if (fp_mode == (enum attr_fp_mode) ACTUAL_NORMAL_MODE (FP_MODE))
26576132 8133 emit_insn (gen_fpu_switch1 (addr_reg));
8134 else
8135 emit_insn (gen_fpu_switch0 (addr_reg));
1b61190c 8136}
2522e445 8137
8138/* Is the given character a logical line separator for the assembler? */
8139#ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
8140#define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
8141#endif
8142
8143int
04f04b72 8144sh_insn_length_adjustment (rtx insn)
2522e445 8145{
8146 /* Instructions with unfilled delay slots take up an extra two bytes for
8147 the nop in the delay slot. */
8148 if (((GET_CODE (insn) == INSN
e3fac27d 8149 && GET_CODE (PATTERN (insn)) != USE
8150 && GET_CODE (PATTERN (insn)) != CLOBBER)
2522e445 8151 || GET_CODE (insn) == CALL_INSN
8152 || (GET_CODE (insn) == JUMP_INSN
8153 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8154 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
8155 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
8156 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
8157 return 2;
8158
87ed74ef 8159 /* SH2e has a bug that prevents the use of annulled branches, so if
8160 the delay slot is not filled, we'll have to put a NOP in it. */
8161 if (sh_cpu == CPU_SH2E
8162 && GET_CODE (insn) == JUMP_INSN
8163 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8164 && GET_CODE (PATTERN (insn)) != ADDR_VEC
8165 && get_attr_type (insn) == TYPE_CBRANCH
8166 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
8167 return 2;
8168
2522e445 8169 /* sh-dsp parallel processing insn take four bytes instead of two. */
8170
8171 if (GET_CODE (insn) == INSN)
8172 {
8173 int sum = 0;
8174 rtx body = PATTERN (insn);
5e20801c 8175 const char *template;
8176 char c;
2522e445 8177 int maybe_label = 1;
8178
8179 if (GET_CODE (body) == ASM_INPUT)
8180 template = XSTR (body, 0);
8181 else if (asm_noperands (body) >= 0)
8182 template
2571646d 8183 = decode_asm_operands (body, NULL, NULL, NULL, NULL);
2522e445 8184 else
8185 return 0;
8186 do
8187 {
8188 int ppi_adjust = 0;
8189
8190 do
8191 c = *template++;
8192 while (c == ' ' || c == '\t');
8193 /* all sh-dsp parallel-processing insns start with p.
8194 The only non-ppi sh insn starting with p is pref.
8195 The only ppi starting with pr is prnd. */
8196 if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2))
8197 ppi_adjust = 2;
8198 /* The repeat pseudo-insn expands two three insns, a total of
8199 six bytes in size. */
8200 else if ((c == 'r' || c == 'R')
8201 && ! strncasecmp ("epeat", template, 5))
8202 ppi_adjust = 4;
8203 while (c && c != '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c))
8204 {
8205 /* If this is a label, it is obviously not a ppi insn. */
8206 if (c == ':' && maybe_label)
8207 {
8208 ppi_adjust = 0;
8209 break;
8210 }
8211 else if (c == '\'' || c == '"')
8212 maybe_label = 0;
8213 c = *template++;
8214 }
8215 sum += ppi_adjust;
8216 maybe_label = c != ':';
8217 }
8218 while (c);
8219 return sum;
8220 }
8221 return 0;
8222}
0abf894c 8223\f
55e0f12f 8224/* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
8225 isn't protected by a PIC unspec. */
0abf894c 8226int
04f04b72 8227nonpic_symbol_mentioned_p (rtx x)
0abf894c 8228{
8229 register const char *fmt;
8230 register int i;
8231
87e19636 8232 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
8233 || GET_CODE (x) == PC)
0abf894c 8234 return 1;
8235
87e19636 8236 /* We don't want to look into the possible MEM location of a
8237 CONST_DOUBLE, since we're not going to use it, in general. */
8238 if (GET_CODE (x) == CONST_DOUBLE)
8239 return 0;
8240
0abf894c 8241 if (GET_CODE (x) == UNSPEC
a5bd34f1 8242 && (XINT (x, 1) == UNSPEC_PIC
8243 || XINT (x, 1) == UNSPEC_GOT
8244 || XINT (x, 1) == UNSPEC_GOTOFF
87e19636 8245 || XINT (x, 1) == UNSPEC_GOTPLT
cec78553 8246 || XINT (x, 1) == UNSPEC_GOTTPOFF
8247 || XINT (x, 1) == UNSPEC_DTPOFF
a5bd34f1 8248 || XINT (x, 1) == UNSPEC_PLT))
d767e27e 8249 return 0;
0abf894c 8250
8251 fmt = GET_RTX_FORMAT (GET_CODE (x));
8252 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8253 {
8254 if (fmt[i] == 'E')
8255 {
8256 register int j;
8257
8258 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8259 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
8260 return 1;
8261 }
8262 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
8263 return 1;
8264 }
8265
8266 return 0;
8267}
8268
8269/* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9df03d69 8270 @GOTOFF in `reg'. */
0abf894c 8271rtx
04f04b72 8272legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
8273 rtx reg)
0abf894c 8274{
cec78553 8275 if (tls_symbolic_operand (orig, Pmode))
8276 return orig;
8277
0abf894c 8278 if (GET_CODE (orig) == LABEL_REF
2fb8cf90 8279 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
0abf894c 8280 {
8281 if (reg == 0)
8282 reg = gen_reg_rtx (Pmode);
8283
8284 emit_insn (gen_symGOTOFF2reg (reg, orig));
8285 return reg;
8286 }
8287 else if (GET_CODE (orig) == SYMBOL_REF)
8288 {
8289 if (reg == 0)
8290 reg = gen_reg_rtx (Pmode);
8291
8292 emit_insn (gen_symGOT2reg (reg, orig));
8293 return reg;
8294 }
8295 return orig;
8296}
ecf6ff7c 8297
8298/* Mark the use of a constant in the literal table. If the constant
8299 has multiple labels, make it unique. */
e3fac27d 8300static rtx
04f04b72 8301mark_constant_pool_use (rtx x)
ecf6ff7c 8302{
8303 rtx insn, lab, pattern;
8304
8305 if (x == NULL)
8306 return x;
8307
8308 switch (GET_CODE (x))
8309 {
8310 case LABEL_REF:
8311 x = XEXP (x, 0);
8312 case CODE_LABEL:
8313 break;
8314 default:
8315 return x;
8316 }
8317
8318 /* Get the first label in the list of labels for the same constant
8319 and delete another labels in the list. */
8320 lab = x;
8321 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
8322 {
8323 if (GET_CODE (insn) != CODE_LABEL
8324 || LABEL_REFS (insn) != NEXT_INSN (insn))
8325 break;
8326 lab = insn;
8327 }
8328
8329 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
8330 INSN_DELETED_P (insn) = 1;
8331
8332 /* Mark constants in a window. */
8333 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
8334 {
8335 if (GET_CODE (insn) != INSN)
8336 continue;
8337
8338 pattern = PATTERN (insn);
8339 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
8340 continue;
8341
8342 switch (XINT (pattern, 1))
8343 {
8344 case UNSPECV_CONST2:
8345 case UNSPECV_CONST4:
8346 case UNSPECV_CONST8:
8347 XVECEXP (pattern, 0, 1) = const1_rtx;
8348 break;
8349 case UNSPECV_WINDOW_END:
8350 if (XVECEXP (pattern, 0, 0) == x)
8351 return lab;
8352 break;
8353 case UNSPECV_CONST_END:
8354 return lab;
8355 default:
8356 break;
8357 }
8358 }
8359
8360 return lab;
8361}
e95ebfe0 8362\f
8363/* Return true if it's possible to redirect BRANCH1 to the destination
8364 of an unconditional jump BRANCH2. We only want to do this if the
8365 resulting branch will have a short displacement. */
8366int
04f04b72 8367sh_can_redirect_branch (rtx branch1, rtx branch2)
e95ebfe0 8368{
8369 if (flag_expensive_optimizations && simplejump_p (branch2))
8370 {
8371 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
8372 rtx insn;
8373 int distance;
8374
8375 for (distance = 0, insn = NEXT_INSN (branch1);
8376 insn && distance < 256;
8377 insn = PREV_INSN (insn))
8378 {
8379 if (insn == dest)
8380 return 1;
8381 else
8382 distance += get_attr_length (insn);
8383 }
8384 for (distance = 0, insn = NEXT_INSN (branch1);
8385 insn && distance < 256;
8386 insn = NEXT_INSN (insn))
8387 {
8388 if (insn == dest)
8389 return 1;
8390 else
8391 distance += get_attr_length (insn);
8392 }
8393 }
8394 return 0;
8395}
8396
808a491c 8397/* Return nonzero if register old_reg can be renamed to register new_reg. */
c67138a9 8398int
04f04b72 8399sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
8400 unsigned int new_reg)
c67138a9 8401{
d767e27e 8402 /* Interrupt functions can only use registers that have already been
8403 saved by the prologue, even if they would normally be
8404 call-clobbered. */
c67138a9 8405
5df3d11f 8406 if (sh_cfun_interrupt_handler_p () && !regs_ever_live[new_reg])
d767e27e 8407 return 0;
c67138a9 8408
d767e27e 8409 return 1;
c67138a9 8410}
8411
83b35a61 8412/* Function to update the integer COST
747af5e7 8413 based on the relationship between INSN that is dependent on
8414 DEP_INSN through the dependence LINK. The default is to make no
8415 adjustment to COST. This can be used for example to specify to
8416 the scheduler that an output- or anti-dependence does not incur
83b35a61 8417 the same cost as a data-dependence. The return value should be
8418 the new value for COST. */
747af5e7 8419static int
04f04b72 8420sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
747af5e7 8421{
ab55c58f 8422 rtx reg, use_pat;
747af5e7 8423
dca8af3e 8424 if (TARGET_SHMEDIA)
8425 {
8426 /* On SHmedia, if the dependence is an anti-dependence or
ada8cf8b 8427 output-dependence, there is no cost. */
dca8af3e 8428 if (REG_NOTE_KIND (link) != 0)
8429 cost = 0;
8430
8431 if (get_attr_is_mac_media (insn)
8432 && get_attr_is_mac_media (dep_insn))
8433 cost = 1;
8434 }
ab55c58f 8435 else if (REG_NOTE_KIND (link) == 0)
747af5e7 8436 {
ab55c58f 8437 enum attr_type dep_type, type;
8438
8439 if (recog_memoized (insn) < 0
8440 || recog_memoized (dep_insn) < 0)
83b35a61 8441 return cost;
ab55c58f 8442
8443 dep_type = get_attr_type (dep_insn);
8444 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
8445 cost--;
8446 if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
8447 && (type = get_attr_type (insn)) != TYPE_CALL
8448 && type != TYPE_SFUNC)
8449 cost--;
8450
747af5e7 8451 /* The only input for a call that is timing-critical is the
8452 function's address. */
ab55c58f 8453 if (GET_CODE(insn) == CALL_INSN)
8454 {
8455 rtx call = PATTERN (insn);
8456
8457 if (GET_CODE (call) == PARALLEL)
8458 call = XVECEXP (call, 0 ,0);
8459 if (GET_CODE (call) == SET)
8460 call = SET_SRC (call);
8461 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
8462 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))
8463 cost = 0;
8464 }
747af5e7 8465 /* Likewise, the most timing critical input for an sfuncs call
8466 is the function address. However, sfuncs typically start
8467 using their arguments pretty quickly.
8468 Assume a four cycle delay before they are needed. */
ab55c58f 8469 /* All sfunc calls are parallels with at least four components.
8470 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
8471 else if (GET_CODE (PATTERN (insn)) == PARALLEL
8472 && XVECLEN (PATTERN (insn), 0) >= 4
8473 && (reg = sfunc_uses_reg (insn)))
8474 {
8475 if (! reg_set_p (reg, dep_insn))
8476 cost -= 4;
8477 }
8478 /* When the preceding instruction loads the shift amount of
8479 the following SHAD/SHLD, the latency of the load is increased
8480 by 1 cycle. */
8481 else if (TARGET_SH4
8482 && get_attr_type (insn) == TYPE_DYN_SHIFT
8483 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
8484 && reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
d767e27e 8485 XEXP (SET_SRC (single_set (insn)),
ab55c58f 8486 1)))
8487 cost++;
8488 /* When an LS group instruction with a latency of less than
8489 3 cycles is followed by a double-precision floating-point
8490 instruction, FIPR, or FTRV, the latency of the first
8491 instruction is increased to 3 cycles. */
8492 else if (cost < 3
8493 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
8494 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
8495 cost = 3;
8496 /* The lsw register of a double-precision computation is ready one
8497 cycle earlier. */
8498 else if (reload_completed
8499 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
8500 && (use_pat = single_set (insn))
8501 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
8502 SET_SRC (use_pat)))
8503 cost -= 1;
8504
8505 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
8506 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
8507 cost -= 1;
8508 }
8509 /* An anti-dependence penalty of two applies if the first insn is a double
8510 precision fadd / fsub / fmul. */
8511 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI
8512 && recog_memoized (dep_insn) >= 0
8513 && get_attr_type (dep_insn) == TYPE_DFP_ARITH
8514 /* A lot of alleged anti-flow dependences are fake,
8515 so check this one is real. */
8516 && flow_dependent_p (dep_insn, insn))
747af5e7 8517 cost = 2;
ab55c58f 8518
747af5e7 8519
8520 return cost;
8521}
476444cc 8522
ab55c58f 8523/* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
8524 if DEP_INSN is anti-flow dependent on INSN. */
8525static int
04f04b72 8526flow_dependent_p (rtx insn, rtx dep_insn)
ab55c58f 8527{
8528 rtx tmp = PATTERN (insn);
8529
8530 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
8531 return tmp == NULL_RTX;
8532}
8533
8534/* A helper function for flow_dependent_p called through note_stores. */
8535static void
04f04b72 8536flow_dependent_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
ab55c58f 8537{
8538 rtx * pinsn = (rtx *) data;
8539
8540 if (*pinsn && reg_referenced_p (x, *pinsn))
8541 *pinsn = NULL_RTX;
8542}
8543
476444cc 8544/* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
8545 'special function' patterns (type sfunc) that clobber pr, but that
8546 do not look like function calls to leaf_function_p. Hence we must
8547 do this extra check. */
8548int
04f04b72 8549sh_pr_n_sets (void)
476444cc 8550{
4a1a3f67 8551 return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
476444cc 8552}
87e19636 8553
c8515df4 8554/* This Function returns nonzero if the DFA based scheduler interface
c56a693a 8555 is to be used. At present this is only supported properly for the SH4.
8556 For the SH1 the current DFA model is just the converted form of the old
8557 pipeline model description. */
bea4bad2 8558static int
d767e27e 8559sh_use_dfa_interface (void)
bea4bad2 8560{
c56a693a 8561 if (TARGET_SH1)
ab55c58f 8562 return 1;
8563 else
8564 return 0;
bea4bad2 8565}
8566
ab55c58f 8567/* This function returns "2" to indicate dual issue for the SH4
8568 processor. To be used by the DFA pipeline description. */
bea4bad2 8569static int
d767e27e 8570sh_issue_rate (void)
bea4bad2 8571{
ab55c58f 8572 if (TARGET_SUPERSCALAR)
8573 return 2;
8574 else
8575 return 1;
bea4bad2 8576}
8577
f77a5bb0 8578/* Functions for ready queue reordering for sched1. */
8579
8580/* Get weight for mode for a set x. */
8581static short
b60226ef 8582find_set_regmode_weight (rtx x, enum machine_mode mode)
f77a5bb0 8583{
8584 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
8585 return 1;
8586 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
8587 {
8588 if (GET_CODE (SET_DEST (x)) == REG)
8589 {
8590 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
8591 return 1;
8592 else
8593 return 0;
8594 }
8595 return 1;
8596 }
8597 return 0;
8598}
8599
8600/* Get regmode weight for insn. */
8601static short
b60226ef 8602find_insn_regmode_weight (rtx insn, enum machine_mode mode)
f77a5bb0 8603{
8604 short reg_weight = 0;
8605 rtx x;
8606
8607 /* Increment weight for each register born here. */
8608 x = PATTERN (insn);
8609 reg_weight += find_set_regmode_weight (x, mode);
8610 if (GET_CODE (x) == PARALLEL)
8611 {
8612 int j;
8613 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
8614 {
8615 x = XVECEXP (PATTERN (insn), 0, j);
8616 reg_weight += find_set_regmode_weight (x, mode);
8617 }
8618 }
8619 /* Decrement weight for each register that dies here. */
8620 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8621 {
8622 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
8623 {
8624 rtx note = XEXP (x, 0);
8625 if (GET_CODE (note) == REG && GET_MODE (note) == mode)
8626 reg_weight--;
8627 }
8628 }
8629 return reg_weight;
8630}
8631
8632/* Calculate regmode weights for all insns of a basic block. */
8633static void
b60226ef 8634find_regmode_weight (int b, enum machine_mode mode)
f77a5bb0 8635{
8636 rtx insn, next_tail, head, tail;
8637
8638 get_block_head_tail (b, &head, &tail);
8639 next_tail = NEXT_INSN (tail);
8640
8641 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
8642 {
8643 /* Handle register life information. */
8644 if (!INSN_P (insn))
8645 continue;
8646
8647 if (mode == SFmode)
8648 INSN_REGMODE_WEIGHT (insn, mode) =
8649 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
8650 else if (mode == SImode)
8651 INSN_REGMODE_WEIGHT (insn, mode) =
8652 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
8653 }
8654}
8655
8656/* Comparison function for ready queue sorting. */
8657static int
b60226ef 8658rank_for_reorder (const void *x, const void *y)
f77a5bb0 8659{
8660 rtx tmp = *(const rtx *) y;
8661 rtx tmp2 = *(const rtx *) x;
8662
8663 /* The insn in a schedule group should be issued the first. */
8664 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
8665 return SCHED_GROUP_P (tmp2) ? 1 : -1;
8666
8667 /* If insns are equally good, sort by INSN_LUID (original insn order), This
8668 minimizes instruction movement, thus minimizing sched's effect on
8669 register pressure. */
8670 return INSN_LUID (tmp) - INSN_LUID (tmp2);
8671}
8672
8673/* Resort the array A in which only element at index N may be out of order. */
8674static void
b60226ef 8675swap_reorder (rtx *a, int n)
f77a5bb0 8676{
8677 rtx insn = a[n - 1];
8678 int i = n - 2;
8679
8680 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
8681 {
8682 a[i + 1] = a[i];
8683 i -= 1;
8684 }
8685 a[i + 1] = insn;
8686}
8687
d767e27e 8688#define SCHED_REORDER(READY, N_READY) \
8689 do \
8690 { \
8691 if ((N_READY) == 2) \
8692 swap_reorder (READY, N_READY); \
8693 else if ((N_READY) > 2) \
8694 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
8695 } \
8696 while (0)
f77a5bb0 8697
8698/* Sort the ready list READY by ascending priority, using the SCHED_REORDER
8699 macro. */
8700static void
b60226ef 8701ready_reorder (rtx *ready, int nready)
f77a5bb0 8702{
8703 SCHED_REORDER (ready, nready);
8704}
8705
8706/* Calculate regmode weights for all insns of all basic block. */
8707static void
b60226ef 8708sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
8709 int verbose ATTRIBUTE_UNUSED,
8710 int old_max_uid)
f77a5bb0 8711{
8712 basic_block b;
8713
8714 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
8715 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
8716
8717 FOR_EACH_BB_REVERSE (b)
8718 {
8719 find_regmode_weight (b->index, SImode);
8720 find_regmode_weight (b->index, SFmode);
8721 }
8722
8723 CURR_REGMODE_PRESSURE (SImode) = 0;
8724 CURR_REGMODE_PRESSURE (SFmode) = 0;
8725
8726}
8727
8728/* Cleanup. */
8729static void
b60226ef 8730sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
8731 int verbose ATTRIBUTE_UNUSED)
f77a5bb0 8732{
8733 if (regmode_weight[0])
8734 {
8735 free (regmode_weight[0]);
8736 regmode_weight[0] = NULL;
8737 }
8738 if (regmode_weight[1])
8739 {
8740 free (regmode_weight[1]);
8741 regmode_weight[1] = NULL;
8742 }
8743}
8744
8745/* Cache the can_issue_more so that we can return it from reorder2. Also,
8746 keep count of register pressures on SImode and SFmode. */
8747static int
b60226ef 8748sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
8749 int sched_verbose ATTRIBUTE_UNUSED,
8750 rtx insn,
8751 int can_issue_more)
f77a5bb0 8752{
8753 if (GET_CODE (PATTERN (insn)) != USE
8754 && GET_CODE (PATTERN (insn)) != CLOBBER)
8755 cached_can_issue_more = can_issue_more - 1;
8756 else
8757 cached_can_issue_more = can_issue_more;
8758
8759 if (reload_completed)
8760 return cached_can_issue_more;
8761
8762 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
8763 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
8764
8765 return cached_can_issue_more;
8766}
8767
8768static void
b60226ef 8769sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
8770 int verbose ATTRIBUTE_UNUSED,
8771 int veclen ATTRIBUTE_UNUSED)
f77a5bb0 8772{
8773 CURR_REGMODE_PRESSURE (SImode) = 0;
8774 CURR_REGMODE_PRESSURE (SFmode) = 0;
8775}
8776
8777/* Some magic numbers. */
8778/* Pressure on register r0 can lead to spill failures. so avoid sched1 for
8779 functions that already have high pressure on r0. */
8780#define R0_MAX_LIFE_REGIONS 2
8781#define R0_MAX_LIVE_LENGTH 12
0aee14a5 8782/* Register Pressure thresholds for SImode and SFmode registers. */
f77a5bb0 8783#define SIMODE_MAX_WEIGHT 5
8784#define SFMODE_MAX_WEIGHT 10
8785
8786/* Return true if the pressure is high for MODE. */
8787static short
b60226ef 8788high_pressure (enum machine_mode mode)
f77a5bb0 8789{
8790 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
8791 functions that already have high pressure on r0. */
8792 if ((REG_N_SETS (0) - REG_N_DEATHS (0)) >= R0_MAX_LIFE_REGIONS
8793 && REG_LIVE_LENGTH (0) >= R0_MAX_LIVE_LENGTH)
8794 return 1;
8795
8796 if (mode == SFmode)
8797 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
8798 else
8799 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
8800}
8801
8802/* Reorder ready queue if register pressure is high. */
8803static int
b60226ef 8804sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
8805 int sched_verbose ATTRIBUTE_UNUSED,
8806 rtx *ready,
8807 int *n_readyp,
8808 int clock_var ATTRIBUTE_UNUSED)
f77a5bb0 8809{
8810 if (reload_completed)
8811 return sh_issue_rate ();
8812
8813 if (high_pressure (SFmode) || high_pressure (SImode))
8814 {
8815 ready_reorder (ready, *n_readyp);
8816 }
8817
8818 return sh_issue_rate ();
8819}
8820
8821/* Skip cycles if the current register pressure is high. */
8822static int
b60226ef 8823sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
8824 int sched_verbose ATTRIBUTE_UNUSED,
8825 rtx *ready ATTRIBUTE_UNUSED,
8826 int *n_readyp ATTRIBUTE_UNUSED,
8827 int clock_var ATTRIBUTE_UNUSED)
f77a5bb0 8828{
8829 if (reload_completed)
8830 return cached_can_issue_more;
8831
8832 if (high_pressure(SFmode) || high_pressure (SImode))
8833 skip_cycles = 1;
8834
8835 return cached_can_issue_more;
8836}
8837
8838/* Skip cycles without sorting the ready queue. This will move insn from
8839 Q->R. If this is the last cycle we are skipping; allow sorting of ready
8840 queue by sh_reorder. */
8841
8842/* Generally, skipping these many cycles are sufficient for all insns to move
8843 from Q -> R. */
8844#define MAX_SKIPS 8
8845
8846static int
b60226ef 8847sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
8848 int sched_verbose ATTRIBUTE_UNUSED,
8849 rtx insn ATTRIBUTE_UNUSED,
8850 int last_clock_var,
8851 int clock_var,
8852 int *sort_p)
f77a5bb0 8853{
8854 if (reload_completed)
d767e27e 8855 return 0;
f77a5bb0 8856
8857 if (skip_cycles)
f77a5bb0 8858 {
d767e27e 8859 if ((clock_var - last_clock_var) < MAX_SKIPS)
8860 {
8861 *sort_p = 0;
8862 return 1;
8863 }
8864 /* If this is the last cycle we are skipping, allow reordering of R. */
8865 if ((clock_var - last_clock_var) == MAX_SKIPS)
8866 {
8867 *sort_p = 1;
8868 return 1;
8869 }
f77a5bb0 8870 }
f77a5bb0 8871
8872 skip_cycles = 0;
8873
8874 return 0;
8875}
8876
87e19636 8877/* SHmedia requires registers for branches, so we can't generate new
8878 branches past reload. */
8879static bool
04f04b72 8880sh_cannot_modify_jumps_p (void)
87e19636 8881{
8882 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
8883}
8884
e26dbf6d 8885static int
8af3db02 8886sh_target_reg_class (void)
8887{
8888 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
8889}
8890
8891static bool
8892sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
8893{
8894 return (shmedia_space_reserved_for_target_registers
8895 && (! after_prologue_epilogue_gen || TARGET_SAVE_ALL_TARGET_REGS));
8896}
8897
87e19636 8898static bool
b60226ef 8899sh_ms_bitfield_layout_p (tree record_type ATTRIBUTE_UNUSED)
87e19636 8900{
45550790 8901 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
87e19636 8902}
e40c2d35 8903\f
8904/*
8905 On the SH1..SH4, the trampoline looks like
8906 2 0002 D202 mov.l l2,r2
8907 1 0000 D301 mov.l l1,r3
8908 3 0004 422B jmp @r2
8909 4 0006 0009 nop
8910 5 0008 00000000 l1: .long area
8911 6 000c 00000000 l2: .long function
8912
8913 SH5 (compact) uses r1 instead of r3 for the static chain. */
8914
8915
8916/* Emit RTL insns to initialize the variable parts of a trampoline.
8917 FNADDR is an RTX for the address of the function's pure code.
8918 CXT is an RTX for the static chain value for the function. */
8919
8920void
04f04b72 8921sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
e40c2d35 8922{
8923 if (TARGET_SHMEDIA64)
8924 {
8925 rtx tramp_templ;
8926 int fixed_len;
8927
8928 rtx movi1 = GEN_INT (0xcc000010);
8929 rtx shori1 = GEN_INT (0xc8000010);
8930 rtx src, dst;
8931
8932 /* The following trampoline works within a +- 128 KB range for cxt:
8933 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
8934 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
8935 gettr tr1,r1; blink tr0,r63 */
8936 /* Address rounding makes it hard to compute the exact bounds of the
8937 offset for this trampoline, but we have a rather generous offset
8938 range, so frame_offset should do fine as an upper bound. */
8939 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
8940 {
8941 /* ??? could optimize this trampoline initialization
8942 by writing DImode words with two insns each. */
8943 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
8944 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
8945 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
8946 insn = gen_rtx_AND (DImode, insn, mask);
8947 /* Or in ptb/u .,tr1 pattern */
8948 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
8949 insn = force_operand (insn, NULL_RTX);
8950 insn = gen_lowpart (SImode, insn);
8951 emit_move_insn (gen_rtx_MEM (SImode, tramp), insn);
8952 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
8953 insn = gen_rtx_AND (DImode, insn, mask);
8954 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
8955 insn = gen_lowpart (SImode, insn);
8956 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), insn);
8957 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
8958 insn = gen_rtx_AND (DImode, insn, mask);
8959 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8960 insn = gen_lowpart (SImode, insn);
8961 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), insn);
8962 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
8963 insn = gen_rtx_AND (DImode, insn, mask);
8964 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8965 insn = gen_lowpart (SImode, insn);
8966 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
8967 insn);
8968 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
8969 insn = gen_rtx_AND (DImode, insn, mask);
8970 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
8971 insn = gen_lowpart (SImode, insn);
8972 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 16)),
8973 insn);
8974 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 20)),
8975 GEN_INT (0x6bf10600));
8976 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 24)),
8977 GEN_INT (0x4415fc10));
8978 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 28)),
8979 GEN_INT (0x4401fff0));
8980 emit_insn (gen_ic_invalidate_line (tramp));
8981 return;
8982 }
8983 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
8984 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
8985
8986 tramp_templ = gen_datalabel_ref (tramp_templ);
8987 dst = gen_rtx_MEM (BLKmode, tramp);
8988 src = gen_rtx_MEM (BLKmode, tramp_templ);
8989 set_mem_align (dst, 256);
8990 set_mem_align (src, 64);
0378dbdc 8991 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
e40c2d35 8992
8993 emit_move_insn (gen_rtx_MEM (Pmode, plus_constant (tramp, fixed_len)),
8994 fnaddr);
8995 emit_move_insn (gen_rtx_MEM (Pmode,
8996 plus_constant (tramp,
8997 fixed_len
8998 + GET_MODE_SIZE (Pmode))),
8999 cxt);
9000 emit_insn (gen_ic_invalidate_line (tramp));
9001 return;
9002 }
9003 else if (TARGET_SHMEDIA)
9004 {
9005 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
9006 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
9007 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
9008 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
9009 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
0924aa1d 9010 rotated 10 right, and higher 16 bit of every 32 selected. */
e40c2d35 9011 rtx movishori
9012 = force_reg (V2HImode, (simplify_gen_subreg
9013 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
9014 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
9015 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
9016
9017 tramp = force_reg (Pmode, tramp);
9018 fnaddr = force_reg (SImode, fnaddr);
9019 cxt = force_reg (SImode, cxt);
9020 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
9021 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
9022 movishori));
e586c16d 9023 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
e40c2d35 9024 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
bcd9bd66 9025 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
e40c2d35 9026 emit_move_insn (gen_rtx_MEM (DImode, tramp), quad0);
9027 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
9028 gen_rtx_SUBREG (V2HImode, cxt, 0),
9029 movishori));
e586c16d 9030 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
e40c2d35 9031 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
bcd9bd66 9032 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
e40c2d35 9033 if (TARGET_LITTLE_ENDIAN)
9034 {
9035 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
9036 emit_insn (gen_mextr4 (quad2, cxtload, blink));
9037 }
9038 else
9039 {
9040 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
9041 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
9042 }
9043 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 8)), quad1);
9044 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), quad2);
9045 emit_insn (gen_ic_invalidate_line (tramp));
9046 return;
9047 }
9048 else if (TARGET_SHCOMPACT)
9049 {
9050 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
9051 return;
9052 }
9053 emit_move_insn (gen_rtx_MEM (SImode, tramp),
9054 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
9055 SImode));
9056 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
9057 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
9058 SImode));
9059 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
9060 cxt);
9061 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
9062 fnaddr);
9063 if (TARGET_HARVARD)
9064 {
9065 if (TARGET_USERMODE)
45271277 9066 emit_library_call (function_symbol ("__ic_invalidate"),
e40c2d35 9067 0, VOIDmode, 1, tramp, SImode);
9068 else
9069 emit_insn (gen_ic_invalidate_line (tramp));
9070 }
9071}
9072
805e22b2 9073/* FIXME: This is overly conservative. A SHcompact function that
9074 receives arguments ``by reference'' will have them stored in its
9075 own stack frame, so it must not pass pointers or references to
9076 these arguments to other functions by means of sibling calls. */
9077static bool
04f04b72 9078sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
805e22b2 9079{
9080 return (decl
9081 && (! TARGET_SHCOMPACT
372faa42 9082 || current_function_args_info.stack_regs == 0)
9083 && ! sh_cfun_interrupt_handler_p ());
805e22b2 9084}
e3fac27d 9085\f
9086/* Machine specific built-in functions. */
9087
9088struct builtin_description
9089{
9090 const enum insn_code icode;
9091 const char *const name;
9092 int signature;
9093};
9094
9095/* describe number and signedness of arguments; arg[0] == result
9096 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
9097static const char signature_args[][4] =
9098{
9099#define SH_BLTIN_V2SI2 0
9100 { 4, 4 },
9101#define SH_BLTIN_V4HI2 1
9102 { 4, 4 },
9103#define SH_BLTIN_V2SI3 2
9104 { 4, 4, 4 },
9105#define SH_BLTIN_V4HI3 3
9106 { 4, 4, 4 },
9107#define SH_BLTIN_V8QI3 4
9108 { 4, 4, 4 },
9109#define SH_BLTIN_MAC_HISI 5
9110 { 1, 4, 4, 1 },
9111#define SH_BLTIN_SH_HI 6
9112 { 4, 4, 1 },
9113#define SH_BLTIN_SH_SI 7
9114 { 4, 4, 1 },
9115#define SH_BLTIN_V4HI2V2SI 8
9116 { 4, 4, 4 },
9117#define SH_BLTIN_V4HI2V8QI 9
9118 { 4, 4, 4 },
9119#define SH_BLTIN_SISF 10
9120 { 4, 2 },
9121#define SH_BLTIN_LDUA_L 11
9122 { 2, 8 },
9123#define SH_BLTIN_LDUA_Q 12
9124 { 1, 8 },
9125#define SH_BLTIN_STUA_L 13
9126 { 0, 8, 2 },
9127#define SH_BLTIN_STUA_Q 14
9128 { 0, 8, 1 },
d3b29bbd 9129#define SH_BLTIN_UDI 15
9130 { 0, 8, 1 },
9131#define SH_BLTIN_NUM_SHARED_SIGNATURES 16
9132#define SH_BLTIN_2 16
9133#define SH_BLTIN_SU 16
e3fac27d 9134 { 1, 2 },
d3b29bbd 9135#define SH_BLTIN_3 17
9136#define SH_BLTIN_SUS 17
e3fac27d 9137 { 2, 2, 1 },
d3b29bbd 9138#define SH_BLTIN_PSSV 18
e3fac27d 9139 { 0, 8, 2, 2 },
d3b29bbd 9140#define SH_BLTIN_XXUU 19
9141#define SH_BLTIN_UUUU 19
e3fac27d 9142 { 1, 1, 1, 1 },
d3b29bbd 9143#define SH_BLTIN_PV 20
e3fac27d 9144 { 0, 8 },
9145};
ada8cf8b 9146/* mcmv: operands considered unsigned. */
e3fac27d 9147/* mmulsum_wq, msad_ubq: result considered unsigned long long. */
ada8cf8b 9148/* mperm: control value considered unsigned int. */
9149/* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
e3fac27d 9150/* mshards_q: returns signed short. */
9151/* nsb: takes long long arg, returns unsigned char. */
9152static const struct builtin_description bdesc[] =
9153{
9154 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
9155 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
9156 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
9157 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
9158 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
9159 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
9160 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
9161#if 0
9162 { CODE_FOR_alloco32, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
9163 { CODE_FOR_alloco64, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
9164#endif
9165 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
9166 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
9167 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
9168 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
9169 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
9170 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
9171 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
9172 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
9173 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
9174 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
d3b29bbd 9175 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_UDI },
9176 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_UDI },
9177 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_UDI },
9178 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_UDI },
9179 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_UDI },
9180 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_UDI },
9181 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_UDI },
e3fac27d 9182 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
9183 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
9184 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
9185 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
9186 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
9187 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
9188 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
9189 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
9190 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
9191 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
9192 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
9193 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
9194 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
9195 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
9196 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
9197 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
9198 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
9199 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
9200 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
9201 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
9202 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
9203 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
9204 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
9205 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
9206 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
9207 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
9208 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
9209 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
9210 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
9211 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
9212 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
9213 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
9214 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
9215 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
9216 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
9217 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
9218 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
9219#if 0
9220 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
9221 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
9222 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
9223 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
9224 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
9225 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
9226 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
9227 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
9228 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
9229 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
9230 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
9231 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
9232 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
9233 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
9234 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
9235 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
d3b29bbd 9236#endif
e3fac27d 9237 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
9238 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
d3b29bbd 9239#if 0
e3fac27d 9240 { CODE_FOR_prefetch32,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
9241 { CODE_FOR_prefetch64,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV }
9242#endif
9243};
9244
9245static void
04f04b72 9246sh_media_init_builtins (void)
e3fac27d 9247{
9248 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
9249 const struct builtin_description *d;
9250
c5006c15 9251 memset (shared, 0, sizeof shared);
3b9d9482 9252 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
e3fac27d 9253 {
9254 tree type, arg_type;
9255 int signature = d->signature;
9256 int i;
9257
9258 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
9259 type = shared[signature];
9260 else
9261 {
9262 int has_result = signature_args[signature][0] != 0;
9263
9264 if (signature_args[signature][1] == 8
9265 && (insn_data[d->icode].operand[has_result].mode != Pmode))
9266 continue;
9267 if (! TARGET_FPU_ANY
9268 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
9269 continue;
9270 type = void_list_node;
9271 for (i = 3; ; i--)
9272 {
9273 int arg = signature_args[signature][i];
9274 int opno = i - 1 + has_result;
9275
9276 if (arg == 8)
9277 arg_type = ptr_type_node;
9278 else if (arg)
9279 arg_type = ((*lang_hooks.types.type_for_mode)
9280 (insn_data[d->icode].operand[opno].mode,
9281 (arg & 1)));
9282 else if (i)
9283 continue;
9284 else
9285 arg_type = void_type_node;
9286 if (i == 0)
9287 break;
9288 type = tree_cons (NULL_TREE, arg_type, type);
9289 }
9290 type = build_function_type (arg_type, type);
9291 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
9292 shared[signature] = type;
9293 }
c5006c15 9294 builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
9295 NULL, NULL_TREE);
e3fac27d 9296 }
9297}
9298
9299static void
04f04b72 9300sh_init_builtins (void)
e3fac27d 9301{
9302 if (TARGET_SHMEDIA)
9303 sh_media_init_builtins ();
9304}
9305
9306/* Expand an expression EXP that calls a built-in function,
9307 with result going to TARGET if that's convenient
9308 (and in mode MODE if that's convenient).
9309 SUBTARGET may be used as the target for computing one of EXP's operands.
9310 IGNORE is nonzero if the value is to be ignored. */
9311
9312static rtx
04f04b72 9313sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9314 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
e3fac27d 9315{
9316 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9317 tree arglist = TREE_OPERAND (exp, 1);
9318 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9319 const struct builtin_description *d = &bdesc[fcode];
9320 enum insn_code icode = d->icode;
9321 int signature = d->signature;
9322 enum machine_mode tmode = VOIDmode;
9323 int nop = 0, i;
9324 rtx op[4];
9325 rtx pat;
9326
9327 if (signature_args[signature][0])
9328 {
9329 if (ignore)
9330 return 0;
9331
9332 tmode = insn_data[icode].operand[0].mode;
9333 if (! target
9334 || GET_MODE (target) != tmode
9335 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9336 target = gen_reg_rtx (tmode);
9337 op[nop++] = target;
9338 }
9339 else
9340 target = 0;
9341
9342 for (i = 1; i <= 3; i++, nop++)
9343 {
9344 tree arg;
9345 enum machine_mode opmode, argmode;
9346
9347 if (! signature_args[signature][i])
9348 break;
9349 arg = TREE_VALUE (arglist);
dec9884d 9350 if (arg == error_mark_node)
9351 return const0_rtx;
e3fac27d 9352 arglist = TREE_CHAIN (arglist);
9353 opmode = insn_data[icode].operand[nop].mode;
9354 argmode = TYPE_MODE (TREE_TYPE (arg));
9355 if (argmode != opmode)
9356 arg = build1 (NOP_EXPR,
9357 (*lang_hooks.types.type_for_mode) (opmode, 0), arg);
9358 op[nop] = expand_expr (arg, NULL_RTX, opmode, 0);
9359 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
9360 op[nop] = copy_to_mode_reg (opmode, op[nop]);
9361 }
9362
9363 switch (nop)
9364 {
9365 case 1:
9366 pat = (*insn_data[d->icode].genfun) (op[0]);
9367 break;
9368 case 2:
9369 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
9370 break;
9371 case 3:
9372 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
9373 break;
9374 case 4:
9375 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
9376 break;
83b35a61 9377 default:
9378 abort ();
e3fac27d 9379 }
9380 if (! pat)
9381 return 0;
9382 emit_insn (pat);
9383 return target;
9384}
d3b29bbd 9385
9386void
04f04b72 9387sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
d3b29bbd 9388{
9389 rtx sel0 = const0_rtx;
9390 rtx sel1 = const1_rtx;
04f04b72 9391 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
d3b29bbd 9392 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
9393
9394 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
9395 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
9396}
9397
9398void
04f04b72 9399sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
d3b29bbd 9400{
9401 rtx sel0 = const0_rtx;
9402 rtx sel1 = const1_rtx;
04f04b72 9403 rtx (*fn) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx)
4aa67c38 9404 = gen_binary_sf_op;
d3b29bbd 9405 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
9406
4aa67c38 9407 emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0, sel1));
9408 emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1, sel0));
d3b29bbd 9409}
9410
897118e8 9411/* Return the class of registers for which a mode change from FROM to TO
9412 is invalid. */
22aae821 9413bool
04f04b72 9414sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
9415 enum reg_class class)
897118e8 9416{
9417 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
9418 {
d767e27e 9419 if (TARGET_LITTLE_ENDIAN)
9420 {
9421 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
9422 return reg_classes_intersect_p (DF_REGS, class);
9423 }
9424 else
9425 {
9426 if (GET_MODE_SIZE (from) < 8)
9427 return reg_classes_intersect_p (DF_HI_REGS, class);
9428 }
897118e8 9429 }
22aae821 9430 return 0;
897118e8 9431}
9432
33946087 9433
9434/* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
9435 that label is used. */
9436
9437void
04f04b72 9438sh_mark_label (rtx address, int nuses)
33946087 9439{
9440 if (GOTOFF_P (address))
9441 {
9442 /* Extract the label or symbol. */
9443 address = XEXP (address, 0);
9444 if (GET_CODE (address) == PLUS)
9445 address = XEXP (address, 0);
9446 address = XVECEXP (address, 0, 0);
9447 }
9448 if (GET_CODE (address) == LABEL_REF
9449 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
9450 LABEL_NUSES (XEXP (address, 0)) += nuses;
9451}
9452
83b35a61 9453/* Compute extra cost of moving data between one register class
9454 and another. */
9455
e04da7b6 9456/* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
9457 uses this information. Hence, the general register <-> floating point
83b35a61 9458 register information here is not used for SFmode. */
9459
9460int
04f04b72 9461sh_register_move_cost (enum machine_mode mode,
9462 enum reg_class srcclass, enum reg_class dstclass)
83b35a61 9463{
9464 if (dstclass == T_REGS || dstclass == PR_REGS)
9465 return 10;
9466
f9afdd51 9467 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
9468 return 4;
9469
e04da7b6 9470 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
9471 && REGCLASS_HAS_FP_REG (srcclass)
9472 && REGCLASS_HAS_FP_REG (dstclass))
9473 return 4;
9474
0ec45dc1 9475 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
d767e27e 9476 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
0ec45dc1 9477 return 9;
9478
83b35a61 9479 if ((REGCLASS_HAS_FP_REG (dstclass)
9480 && REGCLASS_HAS_GENERAL_REG (srcclass))
9481 || (REGCLASS_HAS_GENERAL_REG (dstclass)
9482 && REGCLASS_HAS_FP_REG (srcclass)))
d767e27e 9483 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
9484 * ((GET_MODE_SIZE (mode) + 7) / 8U));
83b35a61 9485
9486 if ((dstclass == FPUL_REGS
9487 && REGCLASS_HAS_GENERAL_REG (srcclass))
9488 || (srcclass == FPUL_REGS
9489 && REGCLASS_HAS_GENERAL_REG (dstclass)))
9490 return 5;
9491
9492 if ((dstclass == FPUL_REGS
9493 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
9494 || (srcclass == FPUL_REGS
9495 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
9496 return 7;
9497
9498 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
9499 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
9500 return 20;
9501
9502 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
9503 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
9504 return 4;
9505
e04da7b6 9506 if (TARGET_SHMEDIA
9507 || (TARGET_FMOVD
9508 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
9509 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
9510 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
9511
9512 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
83b35a61 9513}
9514
0edea8ba 9515/* Like register_operand, but take into account that SHMEDIA can use
9516 the constant zero like a general register. */
9517int
04f04b72 9518sh_register_operand (rtx op, enum machine_mode mode)
0edea8ba 9519{
9520 if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
9521 return 1;
9522 return register_operand (op, mode);
9523}
9524
0c3578e6 9525int
9526cmpsi_operand (rtx op, enum machine_mode mode)
9527{
9528 if (GET_CODE (op) == REG && REGNO (op) == T_REG
9529 && GET_MODE (op) == SImode)
9530 return 1;
9531 return arith_operand (op, mode);
9532}
9533
04f04b72 9534static rtx emit_load_ptr (rtx, rtx);
c83ee613 9535
9536static rtx
04f04b72 9537emit_load_ptr (rtx reg, rtx addr)
c83ee613 9538{
9539 rtx mem = gen_rtx_MEM (ptr_mode, addr);
9540
9541 if (Pmode != ptr_mode)
9542 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
9543 return emit_move_insn (reg, mem);
9544}
9545
9546void
04f04b72 9547sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
9548 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9549 tree function)
c83ee613 9550{
9551 CUMULATIVE_ARGS cum;
9552 int structure_value_byref = 0;
9553 rtx this, this_value, sibcall, insns, funexp;
9554 tree funtype = TREE_TYPE (function);
af2c1324 9555 int simple_add = CONST_OK_FOR_ADD (delta);
c83ee613 9556 int did_load = 0;
9557 rtx scratch0, scratch1, scratch2;
9558
9559 reload_completed = 1;
8af3db02 9560 epilogue_completed = 1;
c83ee613 9561 no_new_pseudos = 1;
9562 current_function_uses_only_leaf_regs = 1;
656047bf 9563 reset_block_changes ();
c83ee613 9564
31b97e8f 9565 emit_note (NOTE_INSN_PROLOGUE_END);
c83ee613 9566
9567 /* Find the "this" pointer. We have such a wide range of ABIs for the
9568 SH that it's best to do this completely machine independently.
9569 "this" is passed as first argument, unless a structure return pointer
9570 comes first, in which case "this" comes second. */
30c70355 9571 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
c83ee613 9572#ifndef PCC_STATIC_STRUCT_RETURN
45550790 9573 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
c83ee613 9574 structure_value_byref = 1;
9575#endif /* not PCC_STATIC_STRUCT_RETURN */
45550790 9576 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
c83ee613 9577 {
9578 tree ptype = build_pointer_type (TREE_TYPE (funtype));
9579
9580 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
9581 }
9582 this = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
9583
9584 /* For SHcompact, we only have r0 for a scratch register: r1 is the
9585 static chain pointer (even if you can't have nested virtual functions
9586 right now, someone might implement them sometime), and the rest of the
9587 registers are used for argument passing, are callee-saved, or reserved. */
9588 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
9589 if (! TARGET_SH5)
9590 {
9591 scratch1 = gen_rtx_REG (ptr_mode, 1);
9592 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
9593 pointing where to return struct values. */
9594 scratch2 = gen_rtx_REG (Pmode, 3);
9595 }
9596 else if (TARGET_SHMEDIA)
9597 {
9598 scratch1 = gen_rtx_REG (ptr_mode, 21);
9599 scratch2 = gen_rtx_REG (Pmode, TR0_REG);
9600 }
9601
9602 this_value = plus_constant (this, delta);
9603 if (vcall_offset
9604 && (simple_add || scratch0 != scratch1)
9605 && strict_memory_address_p (ptr_mode, this_value))
9606 {
9607 emit_load_ptr (scratch0, this_value);
9608 did_load = 1;
9609 }
9610
9611 if (!delta)
9612 ; /* Do nothing. */
9613 else if (simple_add)
9614 emit_move_insn (this, this_value);
9615 else
9616 {
9617 emit_move_insn (scratch1, GEN_INT (delta));
9618 emit_insn (gen_add2_insn (this, scratch1));
9619 }
9620
9621 if (vcall_offset)
9622 {
9623 rtx offset_addr;
9624
9625 if (!did_load)
9626 emit_load_ptr (scratch0, this);
9627
9628 offset_addr = plus_constant (scratch0, vcall_offset);
9629 if (strict_memory_address_p (ptr_mode, offset_addr))
9630 ; /* Do nothing. */
9631 else if (! TARGET_SH5)
9632 {
9633 /* scratch0 != scratch1, and we have indexed loads. Get better
9634 schedule by loading the offset into r1 and using an indexed
9635 load - then the load of r1 can issue before the load from
9636 (this + delta) finishes. */
9637 emit_move_insn (scratch1, GEN_INT (vcall_offset));
9638 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
9639 }
af2c1324 9640 else if (CONST_OK_FOR_ADD (vcall_offset))
c83ee613 9641 {
9642 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
9643 offset_addr = scratch0;
9644 }
9645 else if (scratch0 != scratch1)
9646 {
9647 emit_move_insn (scratch1, GEN_INT (vcall_offset));
9648 emit_insn (gen_add2_insn (scratch0, scratch1));
9649 offset_addr = scratch0;
9650 }
9651 else
9652 abort (); /* FIXME */
9653 emit_load_ptr (scratch0, offset_addr);
9654
d767e27e 9655 if (Pmode != ptr_mode)
c83ee613 9656 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
9657 emit_insn (gen_add2_insn (this, scratch0));
9658 }
9659
9660 /* Generate a tail call to the target function. */
9661 if (! TREE_USED (function))
9662 {
9663 assemble_external (function);
9664 TREE_USED (function) = 1;
9665 }
9666 funexp = XEXP (DECL_RTL (function), 0);
9667 emit_move_insn (scratch2, funexp);
9668 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
9669 sibcall = emit_call_insn (gen_sibcall (funexp, const0_rtx, NULL_RTX));
9670 SIBLING_CALL_P (sibcall) = 1;
9671 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this);
9672 emit_barrier ();
9673
50494502 9674 /* Run just enough of rest_of_compilation to do scheduling and get
c83ee613 9675 the insns emitted. Note that use_thunk calls
9676 assemble_start_function and assemble_end_function. */
50494502 9677
9678 insn_locators_initialize ();
c83ee613 9679 insns = get_insns ();
9680
9681 if (optimize > 0 && flag_schedule_insns_after_reload)
9682 {
450d042a 9683 find_basic_blocks (insns, max_reg_num (), dump_file);
61317220 9684 life_analysis (dump_file, PROP_FINAL);
c83ee613 9685
9686 split_all_insns (1);
9687
450d042a 9688 schedule_insns (dump_file);
c83ee613 9689 }
9690
2efea8c0 9691 sh_reorg ();
c83ee613 9692
9693 if (optimize > 0 && flag_delayed_branch)
d767e27e 9694 dbr_schedule (insns, dump_file);
c83ee613 9695 shorten_branches (insns);
9696 final_start_function (insns, file, 1);
9697 final (insns, file, 1, 0);
9698 final_end_function ();
9699
9700 if (optimize > 0 && flag_schedule_insns_after_reload)
9701 {
9702 /* Release all memory allocated by flow. */
e086b176 9703 free_basic_block_vars ();
c83ee613 9704
9705 /* Release all memory held by regsets now. */
9706 regset_release_memory ();
9707 }
9708
9709 reload_completed = 0;
8af3db02 9710 epilogue_completed = 0;
c83ee613 9711 no_new_pseudos = 0;
9712}
9713
45271277 9714rtx
9715function_symbol (const char *name)
9716{
9717 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
9718 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
9719 return sym;
9720}
9721
41fafa66 9722/* Find the number of a general purpose register in S. */
9723static int
9724scavenge_reg (HARD_REG_SET *s)
9725{
9726 int r;
9727 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
9728 if (TEST_HARD_REG_BIT (*s, r))
9729 return r;
9730 return -1;
9731}
9732
9733rtx
9734sh_get_pr_initial_val (void)
9735{
ca474d26 9736 rtx val;
9737
7a1492b5 9738 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
9739 PR register on SHcompact, because it might be clobbered by the prologue.
ca474d26 9740 We check first if that is known to be the case. */
7a1492b5 9741 if (TARGET_SHCOMPACT
ca474d26 9742 && ((current_function_args_info.call_cookie
9743 & ~ CALL_COOKIE_RET_TRAMP (1))
7a1492b5 9744 || current_function_has_nonlocal_label))
9745 return gen_rtx_MEM (SImode, return_address_pointer_rtx);
ca474d26 9746
9747 /* If we haven't finished rtl generation, there might be a nonlocal label
9748 that we haven't seen yet.
9749 ??? get_hard_reg_initial_val fails if it is called while no_new_pseudos
9750 is set, unless it has been called before for the same register. And even
9751 then, we end in trouble if we didn't use the register in the same
9752 basic block before. So call get_hard_reg_initial_val now and wrap it
9753 in an unspec if we might need to replace it. */
ce022e7a 9754 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
9755 combine can put the pseudo returned by get_hard_reg_initial_val into
9756 instructions that need a general purpose registers, which will fail to
9757 be recognized when the pseudo becomes allocated to PR. */
ca474d26 9758 val
9759 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
ce022e7a 9760 if (TARGET_SH1)
ca474d26 9761 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
9762 return val;
41fafa66 9763}
9764
0c3578e6 9765int
9766sh_expand_t_scc (enum rtx_code code, rtx target)
9767{
9768 rtx result = target;
9769 HOST_WIDE_INT val;
9770
9771 if (GET_CODE (sh_compare_op0) != REG || REGNO (sh_compare_op0) != T_REG
9772 || GET_CODE (sh_compare_op1) != CONST_INT)
9773 return 0;
9774 if (GET_CODE (result) != REG)
9775 result = gen_reg_rtx (SImode);
9776 val = INTVAL (sh_compare_op1);
9777 if ((code == EQ && val == 1) || (code == NE && val == 0))
9778 emit_insn (gen_movt (result));
9779 else if ((code == EQ && val == 0) || (code == NE && val == 1))
9780 {
9781 emit_insn (gen_rtx_CLOBBER (VOIDmode, result));
9782 emit_insn (gen_subc (result, result, result));
bcd9bd66 9783 emit_insn (gen_addsi3 (result, result, const1_rtx));
0c3578e6 9784 }
9785 else if (code == EQ || code == NE)
9786 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
9787 else
9788 return 0;
9789 if (result != target)
9790 emit_move_insn (target, result);
9791 return 1;
9792}
9793
05e09565 9794/* INSN is an sfunc; return the rtx that describes the address used. */
9795static rtx
9796extract_sfunc_addr (rtx insn)
9797{
9798 rtx pattern, part = NULL_RTX;
9799 int len, i;
9800
9801 pattern = PATTERN (insn);
9802 len = XVECLEN (pattern, 0);
9803 for (i = 0; i < len; i++)
9804 {
9805 part = XVECEXP (pattern, 0, i);
9806 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
9807 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
9808 return XEXP (part, 0);
9809 }
9810 if (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE)
9811 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
9812 abort ();
9813}
9814
9815/* Verify that the register in use_sfunc_addr still agrees with the address
9816 used in the sfunc. This prevents fill_slots_from_thread from changing
9817 use_sfunc_addr.
9818 INSN is the use_sfunc_addr instruction, and REG is the register it
9819 guards. */
9820int
9821check_use_sfunc_addr (rtx insn, rtx reg)
9822{
9823 /* Search for the sfunc. It should really come right after INSN. */
9824 while ((insn = NEXT_INSN (insn)))
9825 {
9826 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN)
9827 break;
9828 if (! INSN_P (insn))
9829 continue;
9830
9831 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
9832 insn = XVECEXP (PATTERN (insn), 0, 0);
9833 if (GET_CODE (PATTERN (insn)) != PARALLEL
9834 || get_attr_type (insn) != TYPE_SFUNC)
9835 continue;
9836 return rtx_equal_p (extract_sfunc_addr (insn), reg);
9837 }
9838 abort ();
9839}
9840
1f3233d1 9841#include "gt-sh.h"
Mirror of https://gcc.gnu.org/git/gcc.git