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c8f0269d 1/* Output routines for GCC for Renesas / SuperH SH.
5b71da26 2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
01e935c1 3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
c5c76735 4 Contributed by Steve Chamberlain (sac@cygnus.com).
f676971a 5 Improved by Jim Wilson (wilson@cygnus.com).
bc45ade3 6
7ec022b2 7This file is part of GCC.
c15c9075 8
7ec022b2 9GCC is free software; you can redistribute it and/or modify
c15c9075 10it under the terms of the GNU General Public License as published by
2f83c7d6 11the Free Software Foundation; either version 3, or (at your option)
c15c9075
RK		 12any later version.
13
7ec022b2 14GCC is distributed in the hope that it will be useful,
c15c9075
RK		 15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
2f83c7d6
NC		 20along with GCC; see the file COPYING3. If not see
21<http://www.gnu.org/licenses/>. */
bc45ade3 22
bc45ade3 23#include "config.h"
c5c76735 24#include "system.h"
4977bab6
ZW		 25#include "coretypes.h"
26#include "tm.h"
318881c0 27#include "insn-config.h"
bc45ade3 28#include "rtl.h"
bc45ade3 29#include "tree.h"
bc45ade3 30#include "flags.h"
bc45ade3 31#include "expr.h"
e78d8e51 32#include "optabs.h"
49ad7cfa 33#include "function.h"
8aa2a305
JW		 34#include "regs.h"
35#include "hard-reg-set.h"
36#include "output.h"
956a5206 37#include "insn-attr.h"
318881c0
KG		 38#include "toplev.h"
39#include "recog.h"
950a3816 40#include "integrate.h"
bbf531f0 41#include "elf/dwarf2.h"
318881c0 42#include "tm_p.h"
672a6f42
NB		 43#include "target.h"
44#include "target-def.h"
62526ec3 45#include "real.h"
c1b92d09 46#include "langhooks.h"
1aa03f38 47#include "basic-block.h"
6fb5fa3c 48#include "df.h"
117dca74 49#include "cfglayout.h"
bcc8cc82 50#include "intl.h"
58565a33 51#include "sched-int.h"
bd9a3465 52#include "params.h"
8582b18a 53#include "ggc.h"
726a989a 54#include "gimple.h"
73a4d10b 55#include "cfgloop.h"
6dd3c0a5 56#include "alloc-pool.h"
32a7ab3d 57#include "tm-constrs.h"
5fac2ed2 58
bc45ade3 59
1245df60
R		 60int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
61
00f8ff66
SC		 62#define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
63#define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
64
fa5322fa
AO		 65/* These are some macros to abstract register modes. */
66#define CONST_OK_FOR_ADD(size) \
735cb76e 67 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
fa5322fa
AO		 68#define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
69#define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
70#define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
71
561642fa
AP		 72/* Used to simplify the logic below. Find the attributes wherever
73 they may be. */
74#define SH_ATTRIBUTES(decl) \
75 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
76 : DECL_ATTRIBUTES (decl) \
77 ? (DECL_ATTRIBUTES (decl)) \
78 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
79
552ecbd9
AH		 80/* Set to 1 by expand_prologue() when the function is an interrupt handler. */
81int current_function_interrupt;
82
a6ab9fc0
R		 83tree sh_deferred_function_attributes;
84tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
16bea517 85
6f317ef3 86/* Global variables for machine-dependent things. */
bc45ade3 87
16bea517
JW		 88/* Which cpu are we scheduling for. */
89enum processor_type sh_cpu;
90
58565a33
SKG		 91/* Definitions used in ready queue reordering for first scheduling pass. */
92
93/* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
94static short *regmode_weight[2];
95
96/* Total SFmode and SImode weights of scheduled insns. */
97static int curr_regmode_pressure[2];
98
6fb5fa3c
DB		 99/* Number of r0 life regions. */
100static int r0_life_regions;
101
58565a33
SKG		 102/* If true, skip cycles for Q -> R movement. */
103static int skip_cycles = 0;
104
105/* Cached value of can_issue_more. This is cached in sh_variable_issue hook
106 and returned from sh_reorder2. */
107static short cached_can_issue_more;
108
bc45ade3 109/* Provides the class number of the smallest class containing
16bea517 110 reg number. */
bc45ade3 111
fada1961 112enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
bc45ade3 113{
8e87e161 114 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
bc45ade3
SC		 115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
fa5322fa
AO		 118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
1a95a963
JW		 130 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
fa5322fa
AO		 134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
147 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
225e4f43
R		 148 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
149 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
fa5322fa
AO		 150 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
151 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
96a2347e 152 GENERAL_REGS, GENERAL_REGS,
225e4f43
R		 153};
154
fa5322fa
AO		 155char sh_register_names[FIRST_PSEUDO_REGISTER] \
156 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
157
158char sh_additional_register_names[ADDREGNAMES_SIZE] \
159 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
160 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
bc45ade3 161
225e4f43
R		 162int assembler_dialect;
163
fe3ad572
SC		 164static bool shmedia_space_reserved_for_target_registers;
165
c0fb94d7 166static bool sh_handle_option (size_t, const char *, int);
cf277499
SB		 167static void split_branches (rtx);
168static int branch_dest (rtx);
169static void force_into (rtx, rtx);
170static void print_slot (rtx);
171static rtx add_constant (rtx, enum machine_mode, rtx);
078c8b08 172static void dump_table (rtx, rtx);
cf277499
SB		 173static int hi_const (rtx);
174static int broken_move (rtx);
175static int mova_p (rtx);
176static rtx find_barrier (int, rtx, rtx);
177static int noncall_uses_reg (rtx, rtx, rtx *);
178static rtx gen_block_redirect (rtx, int, int);
179static void sh_reorg (void);
fada1961 180static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
cf277499
SB		 181static rtx frame_insn (rtx);
182static rtx push (int);
183static void pop (int);
184static void push_regs (HARD_REG_SET *, int);
185static int calc_live_regs (HARD_REG_SET *);
cf277499
SB		 186static HOST_WIDE_INT rounded_frame_size (int);
187static rtx mark_constant_pool_use (rtx);
cf277499 188static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
561642fa
AP		 189static tree sh_handle_resbank_handler_attribute (tree *, tree,
190 tree, int, bool *);
191static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
192 tree, int, bool *);
cf277499
SB		 193static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
194static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
195static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
196static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
197static void sh_insert_attributes (tree, tree *);
8d932be3 198static const char *sh_check_pch_target_flags (int);
cf277499 199static int sh_adjust_cost (rtx, rtx, rtx, int);
cf277499 200static int sh_issue_rate (void);
58565a33
SKG		 201static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
202static short find_set_regmode_weight (rtx, enum machine_mode);
203static short find_insn_regmode_weight (rtx, enum machine_mode);
c6d56443 204static void find_regmode_weight (basic_block, enum machine_mode);
6fb5fa3c 205static int find_r0_life_regions (basic_block);
58565a33
SKG		 206static void sh_md_init_global (FILE *, int, int);
207static void sh_md_finish_global (FILE *, int);
208static int rank_for_reorder (const void *, const void *);
209static void swap_reorder (rtx *, int);
210static void ready_reorder (rtx *, int);
211static short high_pressure (enum machine_mode);
212static int sh_reorder (FILE *, int, rtx *, int *, int);
213static int sh_reorder2 (FILE *, int, rtx *, int *, int);
214static void sh_md_init (FILE *, int, int);
215static int sh_variable_issue (FILE *, int, rtx, int);
f676971a 216
cf277499
SB		 217static bool sh_function_ok_for_sibcall (tree, tree);
218
219static bool sh_cannot_modify_jumps_p (void);
81f40b79 220static enum reg_class sh_target_reg_class (void);
fe3ad572 221static bool sh_optimize_target_register_callee_saved (bool);
3101faab 222static bool sh_ms_bitfield_layout_p (const_tree);
cf277499
SB		 223
224static void sh_init_builtins (void);
225static void sh_media_init_builtins (void);
226static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
227static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
228static void sh_file_start (void);
229static int flow_dependent_p (rtx, rtx);
7bc980e1 230static void flow_dependent_p_1 (rtx, const_rtx, void *);
cf277499
SB		 231static int shiftcosts (rtx);
232static int andcosts (rtx);
233static int addsubcosts (rtx);
234static int multcosts (rtx);
235static bool unspec_caller_rtx_p (rtx);
236static bool sh_cannot_copy_insn_p (rtx);
f40751dd
JH		 237static bool sh_rtx_costs (rtx, int, int, int *, bool);
238static int sh_address_cost (rtx, bool);
b48f503c
KK		 239static int sh_pr_n_sets (void);
240static rtx sh_allocate_initial_value (rtx);
1bb99877 241static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);
506d7b68 242static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
fe3ad572
SC		 243static int shmedia_target_regs_stack_space (HARD_REG_SET *);
244static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
245static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
fada1961
R		 246static int scavenge_reg (HARD_REG_SET *s);
247struct save_schedule_s;
248static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
249 struct save_schedule_s *, int);
61f71b34 250
cf277499 251static rtx sh_struct_value_rtx (tree, int);
586de218 252static bool sh_return_in_memory (const_tree, const_tree);
cf277499
SB		 253static rtx sh_builtin_saveregs (void);
254static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
255static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
256static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
c35d187f 257static tree sh_build_builtin_va_list (void);
d7bd8aeb 258static void sh_va_start (tree, rtx);
726a989a 259static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
8cd5a4e0 260static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
586de218 261 const_tree, bool);
6cdd5672 262static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
586de218 263 const_tree, bool);
78a52f11
RH		 264static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
265 tree, bool);
b0fbea13 266static bool sh_scalar_mode_supported_p (enum machine_mode);
3101faab 267static int sh_dwarf_calling_convention (const_tree);
561642fa
AP		 268static void sh_encode_section_info (tree, rtx, int);
269static int sh2a_function_vector_p (tree);
5a82ecd9
ILT		 270\f
271static const struct attribute_spec sh_attribute_table[] =
272{
273 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
274 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
275 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
276 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
277 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
278 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
279 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
280 { "resbank", 0, 0, true, false, false, sh_handle_resbank_handler_attribute },
281 { "function_vector", 1, 1, true, false, false, sh2a_handle_function_vector_handler_attribute },
282#ifdef SYMBIAN
283 /* Symbian support adds three new attributes:
284 dllexport - for exporting a function/variable that will live in a dll
285 dllimport - for importing a function/variable from a dll
61f71b34 286
5a82ecd9
ILT		 287 Microsoft allows multiple declspecs in one __declspec, separating
288 them with spaces. We do NOT support this. Instead, use __declspec
289 multiple times. */
290 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
291 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
292#endif
293 { NULL, 0, 0, false, false, false, NULL }
294};
672a6f42
NB		 295\f
296/* Initialize the GCC target structure. */
91d231cb
JM		 297#undef TARGET_ATTRIBUTE_TABLE
298#define TARGET_ATTRIBUTE_TABLE sh_attribute_table
672a6f42 299
301d03af
RS		 300/* The next two are used for debug info when compiling with -gdwarf. */
301#undef TARGET_ASM_UNALIGNED_HI_OP
302#define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
303#undef TARGET_ASM_UNALIGNED_SI_OP
304#define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
305
fa5322fa
AO		 306/* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
307#undef TARGET_ASM_UNALIGNED_DI_OP
308#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
309#undef TARGET_ASM_ALIGNED_DI_OP
310#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
311
08c148a8
NB		 312#undef TARGET_ASM_FUNCTION_EPILOGUE
313#define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
314
1aa03f38
R		 315#undef TARGET_ASM_OUTPUT_MI_THUNK
316#define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
317
318#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
3101faab 319#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1aa03f38 320
1bc7c5b6
ZW		 321#undef TARGET_ASM_FILE_START
322#define TARGET_ASM_FILE_START sh_file_start
323#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
324#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
325
c0fb94d7
RS		 326#undef TARGET_DEFAULT_TARGET_FLAGS
327#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
328#undef TARGET_HANDLE_OPTION
329#define TARGET_HANDLE_OPTION sh_handle_option
330
12a68f1f
JM		 331#undef TARGET_INSERT_ATTRIBUTES
332#define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
333
c237e94a
ZW		 334#undef TARGET_SCHED_ADJUST_COST
335#define TARGET_SCHED_ADJUST_COST sh_adjust_cost
336
fae15c93
VM		 337#undef TARGET_SCHED_ISSUE_RATE
338#define TARGET_SCHED_ISSUE_RATE sh_issue_rate
339
58565a33
SKG		 340/* The next 5 hooks have been implemented for reenabling sched1. With the
341 help of these macros we are limiting the movement of insns in sched1 to
f676971a 342 reduce the register pressure. The overall idea is to keep count of SImode
58565a33
SKG		 343 and SFmode regs required by already scheduled insns. When these counts
344 cross some threshold values; give priority to insns that free registers.
345 The insn that frees registers is most likely to be the insn with lowest
f676971a 346 LUID (original insn order); but such an insn might be there in the stalled
58565a33
SKG		 347 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
348 upto a max of 8 cycles so that such insns may move from Q -> R.
349
350 The description of the hooks are as below:
351
352 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
353 scheduler; it is called inside the sched_init function just after
354 find_insn_reg_weights function call. It is used to calculate the SImode
1ae58c30 355 and SFmode weights of insns of basic blocks; much similar to what
f676971a 356 find_insn_reg_weights does.
58565a33
SKG		 357 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
358
359 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
360 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
361 (Q)->(R).
362
363 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
364 high; reorder the ready queue so that the insn with lowest LUID will be
365 issued next.
366
367 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
368 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
369
370 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
371 can be returned from TARGET_SCHED_REORDER2.
372
373 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
374
375#undef TARGET_SCHED_DFA_NEW_CYCLE
376#define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
377
378#undef TARGET_SCHED_INIT_GLOBAL
379#define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
380
381#undef TARGET_SCHED_FINISH_GLOBAL
382#define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
383
384#undef TARGET_SCHED_VARIABLE_ISSUE
385#define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
386
387#undef TARGET_SCHED_REORDER
388#define TARGET_SCHED_REORDER sh_reorder
389
390#undef TARGET_SCHED_REORDER2
391#define TARGET_SCHED_REORDER2 sh_reorder2
392
393#undef TARGET_SCHED_INIT
394#define TARGET_SCHED_INIT sh_md_init
395
506d7b68
PB		 396#undef TARGET_LEGITIMIZE_ADDRESS
397#define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
398
fa5322fa
AO		 399#undef TARGET_CANNOT_MODIFY_JUMPS_P
400#define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
fe3ad572
SC		 401#undef TARGET_BRANCH_TARGET_REGISTER_CLASS
402#define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
403#undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
404#define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
405 sh_optimize_target_register_callee_saved
fa5322fa
AO		 406
407#undef TARGET_MS_BITFIELD_LAYOUT_P
408#define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
409
c1b92d09
R		 410#undef TARGET_INIT_BUILTINS
411#define TARGET_INIT_BUILTINS sh_init_builtins
412#undef TARGET_EXPAND_BUILTIN
413#define TARGET_EXPAND_BUILTIN sh_expand_builtin
414
4977bab6
ZW		 415#undef TARGET_FUNCTION_OK_FOR_SIBCALL
416#define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
417
9f3a9a08
KK		 418#undef TARGET_CANNOT_COPY_INSN_P
419#define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
3c50106f
RH		 420#undef TARGET_RTX_COSTS
421#define TARGET_RTX_COSTS sh_rtx_costs
dcefdf67
RH		 422#undef TARGET_ADDRESS_COST
423#define TARGET_ADDRESS_COST sh_address_cost
b48f503c
KK		 424#undef TARGET_ALLOCATE_INITIAL_VALUE
425#define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
3c50106f 426
18dbd950
RS		 427#undef TARGET_MACHINE_DEPENDENT_REORG
428#define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
429
63a9de54
CB		 430#undef TARGET_DWARF_REGISTER_SPAN
431#define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
432
463f02cd
KK		 433#ifdef HAVE_AS_TLS
434#undef TARGET_HAVE_TLS
435#define TARGET_HAVE_TLS true
436#endif
437
61f71b34
DD		 438#undef TARGET_PROMOTE_PROTOTYPES
439#define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
440#undef TARGET_PROMOTE_FUNCTION_ARGS
441#define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
442#undef TARGET_PROMOTE_FUNCTION_RETURN
443#define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
444
445#undef TARGET_STRUCT_VALUE_RTX
446#define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
447#undef TARGET_RETURN_IN_MEMORY
448#define TARGET_RETURN_IN_MEMORY sh_return_in_memory
449
450#undef TARGET_EXPAND_BUILTIN_SAVEREGS
451#define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
452#undef TARGET_SETUP_INCOMING_VARARGS
453#define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
454#undef TARGET_STRICT_ARGUMENT_NAMING
455#define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
456#undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
457#define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
fe984136
RH		 458#undef TARGET_MUST_PASS_IN_STACK
459#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
8cd5a4e0
RH		 460#undef TARGET_PASS_BY_REFERENCE
461#define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
6cdd5672
RH		 462#undef TARGET_CALLEE_COPIES
463#define TARGET_CALLEE_COPIES sh_callee_copies
78a52f11
RH		 464#undef TARGET_ARG_PARTIAL_BYTES
465#define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
61f71b34 466
c35d187f
RH		 467#undef TARGET_BUILD_BUILTIN_VA_LIST
468#define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
d7bd8aeb
JJ		 469#undef TARGET_EXPAND_BUILTIN_VA_START
470#define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
5fac2ed2
RH		 471#undef TARGET_GIMPLIFY_VA_ARG_EXPR
472#define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
c35d187f 473
b0fbea13
KK		 474#undef TARGET_SCALAR_MODE_SUPPORTED_P
475#define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
f676971a
EC		 476#undef TARGET_VECTOR_MODE_SUPPORTED_P
477#define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
478
8d932be3
RS		 479#undef TARGET_CHECK_PCH_TARGET_FLAGS
480#define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
bcc8cc82 481
a1c496cb
EC		 482#undef TARGET_DWARF_CALLING_CONVENTION
483#define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
484
58565a33
SKG		 485/* Return regmode weight for insn. */
486#define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
487
488/* Return current register pressure for regmode. */
489#define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
490
561642fa
AP		 491#undef TARGET_ENCODE_SECTION_INFO
492#define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
493
b55e3aad
NC		 494#ifdef SYMBIAN
495
496#undef TARGET_ENCODE_SECTION_INFO
497#define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
498#undef TARGET_STRIP_NAME_ENCODING
499#define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
500#undef TARGET_CXX_IMPORT_EXPORT_CLASS
501#define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
502
503#endif /* SYMBIAN */
504
8a99f6f9
R		 505#undef TARGET_SECONDARY_RELOAD
506#define TARGET_SECONDARY_RELOAD sh_secondary_reload
507
1bb99877
KK		 508#undef TARGET_LEGITIMATE_ADDRESS_P
509#define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
510
561642fa
AP		 511/* Machine-specific symbol_ref flags. */
512#define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
513
f6897b10 514struct gcc_target targetm = TARGET_INITIALIZER;
b9654711 515\f
c0fb94d7
RS		 516/* Implement TARGET_HANDLE_OPTION. */
517
518static bool
519sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
520 int value ATTRIBUTE_UNUSED)
521{
522 switch (code)
523 {
524 case OPT_m1:
525 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
526 return true;
527
528 case OPT_m2:
529 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
530 return true;
531
532 case OPT_m2a:
533 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
534 return true;
535
536 case OPT_m2a_nofpu:
537 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
538 return true;
539
540 case OPT_m2a_single:
541 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
542 return true;
543
544 case OPT_m2a_single_only:
545 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
546 return true;
547
548 case OPT_m2e:
549 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
550 return true;
551
552 case OPT_m3:
553 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
554 return true;
555
556 case OPT_m3e:
557 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
558 return true;
559
560 case OPT_m4:
25e651ca
AS		 561 case OPT_m4_100:
562 case OPT_m4_200:
78d310c2 563 case OPT_m4_300:
c0fb94d7
RS		 564 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
565 return true;
566
567 case OPT_m4_nofpu:
78d310c2
R		 568 case OPT_m4_100_nofpu:
569 case OPT_m4_200_nofpu:
570 case OPT_m4_300_nofpu:
571 case OPT_m4_340:
25e651ca
AS		 572 case OPT_m4_400:
573 case OPT_m4_500:
c0fb94d7
RS		 574 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
575 return true;
576
577 case OPT_m4_single:
25e651ca
AS		 578 case OPT_m4_100_single:
579 case OPT_m4_200_single:
78d310c2 580 case OPT_m4_300_single:
c0fb94d7
RS		 581 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
582 return true;
583
584 case OPT_m4_single_only:
25e651ca
AS		 585 case OPT_m4_100_single_only:
586 case OPT_m4_200_single_only:
78d310c2 587 case OPT_m4_300_single_only:
c0fb94d7
RS		 588 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
589 return true;
590
591 case OPT_m4a:
592 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
593 return true;
594
595 case OPT_m4a_nofpu:
596 case OPT_m4al:
597 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
598 return true;
599
600 case OPT_m4a_single:
601 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
602 return true;
603
604 case OPT_m4a_single_only:
605 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
606 return true;
607
608 case OPT_m5_32media:
609 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
610 return true;
611
612 case OPT_m5_32media_nofpu:
613 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
614 return true;
615
616 case OPT_m5_64media:
617 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
618 return true;
619
620 case OPT_m5_64media_nofpu:
621 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
622 return true;
623
624 case OPT_m5_compact:
625 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
626 return true;
627
628 case OPT_m5_compact_nofpu:
629 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
630 return true;
631
632 default:
633 return true;
634 }
635}
636\f
bd9a3465
KK		 637/* Set default optimization options. */
638void
639sh_optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
640{
641 if (level)
642 {
643 flag_omit_frame_pointer = 2;
644 if (!size)
645 sh_div_str = "inv:minlat";
646 }
647 if (size)
648 {
649 target_flags |= MASK_SMALLCODE;
650 sh_div_str = SH_DIV_STR_FOR_SIZE ;
651 }
652 else
653 TARGET_CBRANCHDI4 = 1;
654 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options
655 haven't been parsed yet, hence we'd read only the default.
656 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so
657 it's OK to always set flag_branch_target_load_optimize. */
658 if (level > 1)
659 {
660 flag_branch_target_load_optimize = 1;
661 if (!size)
662 target_flags |= MASK_SAVE_ALL_TARGET_REGS;
663 }
664 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE
665 here, so leave it to OVERRIDE_OPTIONS to set
666 flag_finite_math_only. We set it to 2 here so we know if the user
667 explicitly requested this to be on or off. */
668 flag_finite_math_only = 2;
669 /* If flag_schedule_insns is 1, we set it to 2 here so we know if
670 the user explicitly requested this to be on or off. */
671 if (flag_schedule_insns > 0)
672 flag_schedule_insns = 2;
673
674 set_param_value ("simultaneous-prefetches", 2);
675}
676
677/* Implement OVERRIDE_OPTIONS macro. Validate and override various
678 options, and do some machine dependent initialization. */
679void
680sh_override_options (void)
681{
682 int regno;
683
684 SUBTARGET_OVERRIDE_OPTIONS;
685 if (flag_finite_math_only == 2)
686 flag_finite_math_only
687 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;
688 if (TARGET_SH2E && !flag_finite_math_only)
689 target_flags |= MASK_IEEE;
690 sh_cpu = PROCESSOR_SH1;
691 assembler_dialect = 0;
692 if (TARGET_SH2)
693 sh_cpu = PROCESSOR_SH2;
694 if (TARGET_SH2E)
695 sh_cpu = PROCESSOR_SH2E;
696 if (TARGET_SH2A)
697 {
698 sh_cpu = PROCESSOR_SH2A;
699 if (TARGET_SH2A_DOUBLE)
700 target_flags |= MASK_FMOVD;
701 }
702 if (TARGET_SH3)
703 sh_cpu = PROCESSOR_SH3;
704 if (TARGET_SH3E)
705 sh_cpu = PROCESSOR_SH3E;
706 if (TARGET_SH4)
707 {
708 assembler_dialect = 1;
709 sh_cpu = PROCESSOR_SH4;
710 }
711 if (TARGET_SH4A_ARCH)
712 {
713 assembler_dialect = 1;
714 sh_cpu = PROCESSOR_SH4A;
715 }
716 if (TARGET_SH5)
717 {
718 sh_cpu = PROCESSOR_SH5;
719 target_flags |= MASK_ALIGN_DOUBLE;
720 if (TARGET_SHMEDIA_FPU)
721 target_flags |= MASK_FMOVD;
722 if (TARGET_SHMEDIA)
723 {
724 /* There are no delay slots on SHmedia. */
725 flag_delayed_branch = 0;
726 /* Relaxation isn't yet supported for SHmedia */
727 target_flags &= ~MASK_RELAX;
728 /* After reload, if conversion does little good but can cause
729 ICEs:
730 - find_if_block doesn't do anything for SH because we don't
731 have conditional execution patterns. (We use conditional
732 move patterns, which are handled differently, and only
733 before reload).
734 - find_cond_trap doesn't do anything for the SH because we
735 don't have conditional traps.
736 - find_if_case_1 uses redirect_edge_and_branch_force in
737 the only path that does an optimization, and this causes
738 an ICE when branch targets are in registers.
739 - find_if_case_2 doesn't do anything for the SHmedia after
740 reload except when it can redirect a tablejump - and
741 that's rather rare. */
742 flag_if_conversion2 = 0;
743 if (! strcmp (sh_div_str, "call"))
744 sh_div_strategy = SH_DIV_CALL;
745 else if (! strcmp (sh_div_str, "call2"))
746 sh_div_strategy = SH_DIV_CALL2;
747 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)
748 sh_div_strategy = SH_DIV_FP;
749 else if (! strcmp (sh_div_str, "inv"))
750 sh_div_strategy = SH_DIV_INV;
751 else if (! strcmp (sh_div_str, "inv:minlat"))
752 sh_div_strategy = SH_DIV_INV_MINLAT;
753 else if (! strcmp (sh_div_str, "inv20u"))
754 sh_div_strategy = SH_DIV_INV20U;
755 else if (! strcmp (sh_div_str, "inv20l"))
756 sh_div_strategy = SH_DIV_INV20L;
757 else if (! strcmp (sh_div_str, "inv:call2"))
758 sh_div_strategy = SH_DIV_INV_CALL2;
759 else if (! strcmp (sh_div_str, "inv:call"))
760 sh_div_strategy = SH_DIV_INV_CALL;
761 else if (! strcmp (sh_div_str, "inv:fp"))
762 {
763 if (TARGET_FPU_ANY)
764 sh_div_strategy = SH_DIV_INV_FP;
765 else
766 sh_div_strategy = SH_DIV_INV;
767 }
768 TARGET_CBRANCHDI4 = 0;
769 /* Assembler CFI isn't yet fully supported for SHmedia. */
770 flag_dwarf2_cfi_asm = 0;
771 }
772 }
773 else
774 {
775 /* Only the sh64-elf assembler fully supports .quad properly. */
776 targetm.asm_out.aligned_op.di = NULL;
777 targetm.asm_out.unaligned_op.di = NULL;
778 }
779 if (TARGET_SH1)
780 {
781 if (! strcmp (sh_div_str, "call-div1"))
782 sh_div_strategy = SH_DIV_CALL_DIV1;
783 else if (! strcmp (sh_div_str, "call-fp")
784 && (TARGET_FPU_DOUBLE
785 || (TARGET_HARD_SH4 && TARGET_SH2E)
786 || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))
787 sh_div_strategy = SH_DIV_CALL_FP;
788 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2)
789 sh_div_strategy = SH_DIV_CALL_TABLE;
790 else
791 /* Pick one that makes most sense for the target in general.
792 It is not much good to use different functions depending
793 on -Os, since then we'll end up with two different functions
794 when some of the code is compiled for size, and some for
795 speed. */
796
797 /* SH4 tends to emphasize speed. */
798 if (TARGET_HARD_SH4)
799 sh_div_strategy = SH_DIV_CALL_TABLE;
800 /* These have their own way of doing things. */
801 else if (TARGET_SH2A)
802 sh_div_strategy = SH_DIV_INTRINSIC;
803 /* ??? Should we use the integer SHmedia function instead? */
804 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)
805 sh_div_strategy = SH_DIV_CALL_FP;
806 /* SH1 .. SH3 cores often go into small-footprint systems, so
807 default to the smallest implementation available. */
808 else if (TARGET_SH2) /* ??? EXPERIMENTAL */
809 sh_div_strategy = SH_DIV_CALL_TABLE;
810 else
811 sh_div_strategy = SH_DIV_CALL_DIV1;
812 }
813 if (!TARGET_SH1)
814 TARGET_PRETEND_CMOVE = 0;
815 if (sh_divsi3_libfunc[0])
816 ; /* User supplied - leave it alone. */
817 else if (TARGET_DIVIDE_CALL_FP)
818 sh_divsi3_libfunc = "__sdivsi3_i4";
819 else if (TARGET_DIVIDE_CALL_TABLE)
820 sh_divsi3_libfunc = "__sdivsi3_i4i";
821 else if (TARGET_SH5)
822 sh_divsi3_libfunc = "__sdivsi3_1";
823 else
824 sh_divsi3_libfunc = "__sdivsi3";
825 if (sh_branch_cost == -1)
826 sh_branch_cost
827 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1;
828
829 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
830 if (! VALID_REGISTER_P (regno))
831 sh_register_names[regno][0] = '\0';
832
833 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
834 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
835 sh_additional_register_names[regno][0] = '\0';
836
837 if (flag_omit_frame_pointer == 2)
838 {
839 /* The debugging information is sufficient,
840 but gdb doesn't implement this yet */
841 if (0)
842 flag_omit_frame_pointer
843 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);
844 else
845 flag_omit_frame_pointer = 0;
846 }
847
848 if ((flag_pic && ! TARGET_PREFERGOT)
849 || (TARGET_SHMEDIA && !TARGET_PT_FIXED))
850 flag_no_function_cse = 1;
851
852 if (SMALL_REGISTER_CLASSES)
853 {
854 /* Never run scheduling before reload, since that can
855 break global alloc, and generates slower code anyway due
856 to the pressure on R0. */
857 /* Enable sched1 for SH4 if the user explicitly requests.
858 When sched1 is enabled, the ready queue will be reordered by
859 the target hooks if pressure is high. We can not do this for
860 PIC, SH3 and lower as they give spill failures for R0. */
861 if (!TARGET_HARD_SH4 || flag_pic)
862 flag_schedule_insns = 0;
863 /* ??? Current exception handling places basic block boundaries
864 after call_insns. It causes the high pressure on R0 and gives
865 spill failures for R0 in reload. See PR 22553 and the thread
866 on gcc-patches
867 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
868 else if (flag_exceptions)
869 {
870 if (flag_schedule_insns == 1)
871 warning (0, "ignoring -fschedule-insns because of exception handling bug");
872 flag_schedule_insns = 0;
873 }
874 else if (flag_schedule_insns == 2)
875 flag_schedule_insns = 0;
876 }
877
878 if (align_loops == 0)
879 align_loops = 1 << (TARGET_SH5 ? 3 : 2);
880 if (align_jumps == 0)
881 align_jumps = 1 << CACHE_LOG;
882 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))
883 align_jumps = TARGET_SHMEDIA ? 4 : 2;
884
885 /* Allocation boundary (in *bytes*) for the code of a function.
886 SH1: 32 bit alignment is faster, because instructions are always
887 fetched as a pair from a longword boundary.
888 SH2 .. SH5 : align to cache line start. */
889 if (align_functions == 0)
890 align_functions
891 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);
892 /* The linker relaxation code breaks when a function contains
893 alignments that are larger than that at the start of a
894 compilation unit. */
895 if (TARGET_RELAX)
896 {
897 int min_align
898 = align_loops > align_jumps ? align_loops : align_jumps;
899
900 /* Also take possible .long constants / mova tables int account. */
901 if (min_align < 4)
902 min_align = 4;
903 if (align_functions < min_align)
904 align_functions = min_align;
905 }
906
907 if (sh_fixed_range_str)
908 sh_fix_range (sh_fixed_range_str);
909}
910\f
16bea517 911/* Print the operand address in x to the stream. */
bc45ade3
SC		 912
913void
cf277499 914print_operand_address (FILE *stream, rtx x)
bc45ade3
SC		 915{
916 switch (GET_CODE (x))
917 {
918 case REG:
225e4f43
R		 919 case SUBREG:
920 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
bc45ade3 921 break;
8aa2a305 922
bc45ade3
SC		 923 case PLUS:
924 {
925 rtx base = XEXP (x, 0);
926 rtx index = XEXP (x, 1);
927
bc45ade3
SC		 928 switch (GET_CODE (index))
929 {
930 case CONST_INT:
c5b9ef02 931 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
225e4f43 932 reg_names[true_regnum (base)]);
bc45ade3
SC		 933 break;
934
935 case REG:
225e4f43
R		 936 case SUBREG:
937 {
938 int base_num = true_regnum (base);
939 int index_num = true_regnum (index);
940
941 fprintf (stream, "@(r0,%s)",
942 reg_names[MAX (base_num, index_num)]);
943 break;
944 }
bc45ade3
SC		 945
946 default:
f5b9e7c9 947 gcc_unreachable ();
bc45ade3
SC		 948 }
949 }
bc45ade3 950 break;
8aa2a305 951
bc45ade3 952 case PRE_DEC:
225e4f43 953 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
bc45ade3
SC		 954 break;
955
956 case POST_INC:
225e4f43 957 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
bc45ade3
SC		 958 break;
959
960 default:
b91455de 961 x = mark_constant_pool_use (x);
422be3c3 962 output_addr_const (stream, x);
bc45ade3
SC		 963 break;
964 }
965}
966
967/* Print operand x (an rtx) in assembler syntax to file stream
968 according to modifier code.
969
b9654711 970 '.' print a .s if insn needs delay slot
1245df60 971 ',' print LOCAL_LABEL_PREFIX
4408efce 972 '@' print trap, rte or rts depending upon pragma interruptness
8aa2a305 973 '#' output a nop if there is nothing to put in the delay slot
fae778eb 974 ''' print likelihood suffix (/u for unlikely).
73a4d10b 975 '>' print branch target if -fverbose-asm
8aa2a305 976 'O' print a constant without the #
00f8ff66 977 'R' print the LSW of a dp value - changes if in little endian
00f8ff66 978 'S' print the MSW of a dp value - changes if in little endian
225e4f43 979 'T' print the next word of a dp value - same as 'R' in big endian mode.
31b6f0ae
R		 980 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
981 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
c1b92d09 982 'N' print 'r63' if the operand is (const_int 0).
312209c6 983 'd' print a V2SF reg as dN instead of fpN.
fa5322fa 984 'm' print a pair `base,offset' or `base,index', for LD and ST.
73a4d10b 985 'U' Likewise for {LD,ST}{HI,LO}.
de6adfa2
N		 986 'V' print the position of a single bit set.
987 'W' print the position of a single bit cleared.
9eb3a0dd 988 't' print a memory address which is a register.
fa5322fa 989 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
225e4f43 990 'o' output an operator. */
bc45ade3
SC		 991
992void
cf277499 993print_operand (FILE *stream, rtx x, int code)
bc45ade3 994{
73a4d10b
R		 995 int regno;
996 enum machine_mode mode;
997
bc45ade3
SC		 998 switch (code)
999 {
a6ab9fc0
R		 1000 tree trapa_attr;
1001
b9654711 1002 case '.':
79b2746a 1003 if (final_sequence
c608a684
R		 1004 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
1005 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
1245df60
R		 1006 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
1007 break;
1008 case ',':
1009 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
b9654711 1010 break;
d3ae8277 1011 case '@':
a6ab9fc0
R		 1012 trapa_attr = lookup_attribute ("trap_exit",
1013 DECL_ATTRIBUTES (current_function_decl));
1014 if (trapa_attr)
1015 fprintf (stream, "trapa #%ld",
1016 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
e3ba8d11 1017 else if (sh_cfun_interrupt_handler_p ())
561642fa
AP		 1018 {
1019 if (sh_cfun_resbank_handler_p ())
1020 fprintf (stream, "resbank\n");
1021 fprintf (stream, "rte");
1022 }
d3ae8277 1023 else
8e87e161 1024 fprintf (stream, "rts");
d3ae8277 1025 break;
bc45ade3 1026 case '#':
16bea517 1027 /* Output a nop if there's nothing in the delay slot. */
bc45ade3 1028 if (dbr_sequence_length () == 0)
8aa2a305 1029 fprintf (stream, "\n\tnop");
bc45ade3 1030 break;
c8cc4417
R		 1031 case '\'':
1032 {
1033 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
1034
1035 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
1036 fputs ("/u", stream);
1037 break;
1038 }
73a4d10b
R		 1039 case '>':
1040 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
1041 {
1042 fputs ("\t! target: ", stream);
1043 output_addr_const (stream, JUMP_LABEL (current_output_insn));
1044 }
1045 break;
b9654711 1046 case 'O':
b91455de 1047 x = mark_constant_pool_use (x);
0d7e008e 1048 output_addr_const (stream, x);
bc45ade3 1049 break;
4802062c
R		 1050 /* N.B.: %R / %S / %T adjust memory addresses by four.
1051 For SHMEDIA, that means they can be used to access the first and
1052 second 32 bit part of a 64 bit (or larger) value that
1053 might be held in floating point registers or memory.
1054 While they can be used to access 64 bit parts of a larger value
1055 held in general purpose registers, that won't work with memory -
1056 neither for fp registers, since the frxx names are used. */
bc45ade3 1057 case 'R':
4802062c
R		 1058 if (REG_P (x) || GET_CODE (x) == SUBREG)
1059 {
1060 regno = true_regnum (x);
1061 regno += FP_REGISTER_P (regno) ? 1 : LSW;
1062 fputs (reg_names[regno], (stream));
1063 }
1064 else if (MEM_P (x))
1065 {
1066 x = adjust_address (x, SImode, 4 * LSW);
1067 print_operand_address (stream, XEXP (x, 0));
1068 }
1069 else
1070 {
1071 rtx sub = NULL_RTX;
1072
1073 mode = GET_MODE (x);
1074 if (mode == VOIDmode)
1075 mode = DImode;
1076 if (GET_MODE_SIZE (mode) >= 8)
1077 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
1078 if (sub)
1079 print_operand (stream, sub, 0);
1080 else
1081 output_operand_lossage ("invalid operand to %%R");
1082 }
8aa2a305
JW		 1083 break;
1084 case 'S':
4802062c
R		 1085 if (REG_P (x) || GET_CODE (x) == SUBREG)
1086 {
1087 regno = true_regnum (x);
1088 regno += FP_REGISTER_P (regno) ? 0 : MSW;
1089 fputs (reg_names[regno], (stream));
1090 }
1091 else if (MEM_P (x))
1092 {
1093 x = adjust_address (x, SImode, 4 * MSW);
1094 print_operand_address (stream, XEXP (x, 0));
1095 }
1096 else
1097 {
1098 rtx sub = NULL_RTX;
1099
1100 mode = GET_MODE (x);
1101 if (mode == VOIDmode)
1102 mode = DImode;
1103 if (GET_MODE_SIZE (mode) >= 8)
1104 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
1105 if (sub)
1106 print_operand (stream, sub, 0);
1107 else
1108 output_operand_lossage ("invalid operand to %%S");
1109 }
00f8ff66
SC		 1110 break;
1111 case 'T':
16bea517 1112 /* Next word of a double. */
bc45ade3
SC		 1113 switch (GET_CODE (x))
1114 {
1115 case REG:
1116 fputs (reg_names[REGNO (x) + 1], (stream));
1117 break;
1118 case MEM:
225e4f43
R		 1119 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
1120 && GET_CODE (XEXP (x, 0)) != POST_INC)
b72f00af 1121 x = adjust_address (x, SImode, 4);
225e4f43 1122 print_operand_address (stream, XEXP (x, 0));
bc45ade3 1123 break;
318881c0
KG		 1124 default:
1125 break;
bc45ade3
SC		 1126 }
1127 break;
9eb3a0dd
N		 1128
1129 case 't':
f3536097 1130 gcc_assert (MEM_P (x));
9eb3a0dd
N		 1131 x = XEXP (x, 0);
1132 switch (GET_CODE (x))
1133 {
1134 case REG:
1135 case SUBREG:
1136 print_operand (stream, x, 0);
1137 break;
1138 default:
1139 break;
1140 }
1141 break;
1142
225e4f43
R		 1143 case 'o':
1144 switch (GET_CODE (x))
1145 {
1146 case PLUS: fputs ("add", stream); break;
1147 case MINUS: fputs ("sub", stream); break;
1148 case MULT: fputs ("mul", stream); break;
1149 case DIV: fputs ("div", stream); break;
c8cc4417
R		 1150 case EQ: fputs ("eq", stream); break;
1151 case NE: fputs ("ne", stream); break;
1152 case GT: case LT: fputs ("gt", stream); break;
1153 case GE: case LE: fputs ("ge", stream); break;
1154 case GTU: case LTU: fputs ("gtu", stream); break;
1155 case GEU: case LEU: fputs ("geu", stream); break;
318881c0
KG		 1156 default:
1157 break;
225e4f43
R		 1158 }
1159 break;
fa5322fa 1160 case 'M':
31b6f0ae
R		 1161 if (TARGET_SHMEDIA)
1162 {
f3536097 1163 if (MEM_P (x)
31b6f0ae 1164 && GET_CODE (XEXP (x, 0)) == PLUS
f3536097 1165 && (REG_P (XEXP (XEXP (x, 0), 1))
31b6f0ae
R		 1166 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
1167 fputc ('x', stream);
1168 }
1169 else
1170 {
f3536097 1171 if (MEM_P (x))
31b6f0ae
R		 1172 {
1173 switch (GET_MODE (x))
1174 {
1175 case QImode: fputs (".b", stream); break;
1176 case HImode: fputs (".w", stream); break;
1177 case SImode: fputs (".l", stream); break;
1178 case SFmode: fputs (".s", stream); break;
1179 case DFmode: fputs (".d", stream); break;
1180 default: gcc_unreachable ();
1181 }
1182 }
1183 }
fa5322fa
AO		 1184 break;
1185
1186 case 'm':
f3536097 1187 gcc_assert (MEM_P (x));
fa5322fa 1188 x = XEXP (x, 0);
73a4d10b
R		 1189 /* Fall through. */
1190 case 'U':
fa5322fa
AO		 1191 switch (GET_CODE (x))
1192 {
1193 case REG:
1194 case SUBREG:
1195 print_operand (stream, x, 0);
1196 fputs (", 0", stream);
1197 break;
1198
1199 case PLUS:
1200 print_operand (stream, XEXP (x, 0), 0);
1201 fputs (", ", stream);
1202 print_operand (stream, XEXP (x, 1), 0);
1203 break;
1204
1205 default:
f5b9e7c9 1206 gcc_unreachable ();
fa5322fa
AO		 1207 }
1208 break;
1209
de6adfa2
N		 1210 case 'V':
1211 {
1212 int num = exact_log2 (INTVAL (x));
1213 gcc_assert (num >= 0);
1214 fprintf (stream, "#%d", num);
1215 }
1216 break;
1217
1218 case 'W':
1219 {
1220 int num = exact_log2 (~INTVAL (x));
1221 gcc_assert (num >= 0);
1222 fprintf (stream, "#%d", num);
1223 }
1224 break;
1225
312209c6 1226 case 'd':
f3536097 1227 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
312209c6
AO		 1228
1229 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1230 break;
f676971a 1231
c1b92d09 1232 case 'N':
0ac78517 1233 if (x == CONST0_RTX (GET_MODE (x)))
c1b92d09
R		 1234 {
1235 fprintf ((stream), "r63");
1236 break;
1237 }
1238 goto default_output;
fa5322fa 1239 case 'u':
f3536097 1240 if (CONST_INT_P (x))
c8cc4417 1241 {
fa5322fa
AO		 1242 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
1243 break;
1244 }
1245 /* Fall through. */
1246
c1b92d09 1247 default_output:
bc45ade3 1248 default:
73a4d10b
R		 1249 regno = 0;
1250 mode = GET_MODE (x);
1251
bc45ade3
SC		 1252 switch (GET_CODE (x))
1253 {
73a4d10b
R		 1254 case TRUNCATE:
1255 {
1256 rtx inner = XEXP (x, 0);
1257 int offset = 0;
1258 enum machine_mode inner_mode;
1259
1260 /* We might see SUBREGs with vector mode registers inside. */
1261 if (GET_CODE (inner) == SUBREG
1262 && (GET_MODE_SIZE (GET_MODE (inner))
1263 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1264 && subreg_lowpart_p (inner))
1265 inner = SUBREG_REG (inner);
f3536097 1266 if (CONST_INT_P (inner))
73a4d10b
R		 1267 {
1268 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
1269 goto default_output;
1270 }
1271 inner_mode = GET_MODE (inner);
1272 if (GET_CODE (inner) == SUBREG
1273 && (GET_MODE_SIZE (GET_MODE (inner))
1274 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
f3536097 1275 && REG_P (SUBREG_REG (inner)))
73a4d10b
R		 1276 {
1277 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
1278 GET_MODE (SUBREG_REG (inner)),
1279 SUBREG_BYTE (inner),
1280 GET_MODE (inner));
1281 inner = SUBREG_REG (inner);
1282 }
f3536097 1283 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
73a4d10b
R		 1284 abort ();
1285 /* Floating point register pairs are always big endian;
30dc60c7 1286 general purpose registers are 64 bit wide. */
73a4d10b
R		 1287 regno = REGNO (inner);
1288 regno = (HARD_REGNO_NREGS (regno, inner_mode)
1289 - HARD_REGNO_NREGS (regno, mode))
1290 + offset;
1291 x = inner;
1292 goto reg;
1293 }
1294 case SIGN_EXTEND:
1295 x = XEXP (x, 0);
1296 goto reg;
fa5322fa
AO		 1297 /* FIXME: We need this on SHmedia32 because reload generates
1298 some sign-extended HI or QI loads into DImode registers
1299 but, because Pmode is SImode, the address ends up with a
1300 subreg:SI of the DImode register. Maybe reload should be
1301 fixed so as to apply alter_subreg to such loads? */
73a4d10b
R		 1302 case IF_THEN_ELSE:
1303 gcc_assert (trapping_target_operand (x, VOIDmode));
1304 x = XEXP (XEXP (x, 2), 0);
1305 goto default_output;
fa5322fa 1306 case SUBREG:
f5b9e7c9 1307 gcc_assert (SUBREG_BYTE (x) == 0
f3536097 1308 && REG_P (SUBREG_REG (x)));
fa5322fa
AO		 1309
1310 x = SUBREG_REG (x);
1311 /* Fall through. */
1312
73a4d10b 1313 reg:
bc45ade3 1314 case REG:
73a4d10b
R		 1315 regno += REGNO (x);
1316 if (FP_REGISTER_P (regno)
1317 && mode == V16SFmode)
1318 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
fa5322fa 1319 else if (FP_REGISTER_P (REGNO (x))
73a4d10b
R		 1320 && mode == V4SFmode)
1321 fprintf ((stream), "fv%s", reg_names[regno] + 2);
f3536097 1322 else if (REG_P (x)
73a4d10b
R		 1323 && mode == V2SFmode)
1324 fprintf ((stream), "fp%s", reg_names[regno] + 2);
fa5322fa 1325 else if (FP_REGISTER_P (REGNO (x))
73a4d10b
R		 1326 && GET_MODE_SIZE (mode) > 4)
1327 fprintf ((stream), "d%s", reg_names[regno] + 1);
225e4f43 1328 else
73a4d10b 1329 fputs (reg_names[regno], (stream));
bc45ade3 1330 break;
fa5322fa 1331
bc45ade3
SC		 1332 case MEM:
1333 output_address (XEXP (x, 0));
1334 break;
f676971a 1335
bc45ade3 1336 default:
fa5322fa
AO		 1337 if (TARGET_SH1)
1338 fputc ('#', stream);
bc45ade3
SC		 1339 output_addr_const (stream, x);
1340 break;
bc45ade3
SC		 1341 }
1342 break;
1343 }
1344}
bc45ade3 1345\f
561642fa
AP		 1346
1347/* Encode symbol attributes of a SYMBOL_REF into its
1348 SYMBOL_REF_FLAGS. */
1349static void
1350sh_encode_section_info (tree decl, rtx rtl, int first)
1351{
1352 default_encode_section_info (decl, rtl, first);
1353
1354 if (TREE_CODE (decl) == FUNCTION_DECL
1355 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1356 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1357}
1358
0aa692fc
R		 1359/* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1360static void
cf277499 1361force_into (rtx value, rtx target)
0aa692fc
R		 1362{
1363 value = force_operand (value, target);
1364 if (! rtx_equal_p (value, target))
1365 emit_insn (gen_move_insn (target, value));
1366}
1367
0d7e008e
SC		 1368/* Emit code to perform a block move. Choose the best method.
1369
1370 OPERANDS[0] is the destination.
1371 OPERANDS[1] is the source.
1372 OPERANDS[2] is the size.
1373 OPERANDS[3] is the alignment safe to use. */
1374
0d7e008e 1375int
cf277499 1376expand_block_move (rtx *operands)
0d7e008e
SC		 1377{
1378 int align = INTVAL (operands[3]);
f3536097 1379 int constp = (CONST_INT_P (operands[2]));
0d7e008e 1380 int bytes = (constp ? INTVAL (operands[2]) : 0);
0d7e008e 1381
312209c6
AO		 1382 if (! constp)
1383 return 0;
1384
1385 /* If we could use mov.l to move words and dest is word-aligned, we
1386 can use movua.l for loads and still generate a relatively short
1387 and efficient sequence. */
1388 if (TARGET_SH4A_ARCH && align < 4
1389 && MEM_ALIGN (operands[0]) >= 32
1390 && can_move_by_pieces (bytes, 32))
1391 {
1392 rtx dest = copy_rtx (operands[0]);
1393 rtx src = copy_rtx (operands[1]);
1394 /* We could use different pseudos for each copied word, but
1395 since movua can only load into r0, it's kind of
1396 pointless. */
1397 rtx temp = gen_reg_rtx (SImode);
1398 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1399 int copied = 0;
1400
1401 while (copied + 4 <= bytes)
1402 {
1403 rtx to = adjust_address (dest, SImode, copied);
85144c5c
RS		 1404 rtx from = adjust_automodify_address (src, BLKmode,
1405 src_addr, copied);
312209c6 1406
85144c5c 1407 set_mem_size (from, GEN_INT (4));
312209c6
AO		 1408 emit_insn (gen_movua (temp, from));
1409 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1410 emit_move_insn (to, temp);
1411 copied += 4;
1412 }
1413
1414 if (copied < bytes)
1415 move_by_pieces (adjust_address (dest, BLKmode, copied),
1416 adjust_automodify_address (src, BLKmode,
1417 src_addr, copied),
1418 bytes - copied, align, 0);
1419
1420 return 1;
1421 }
1422
8aa2a305
JW		 1423 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1424 alignment, or if it isn't a multiple of 4 bytes, then fail. */
312209c6 1425 if (align < 4 || (bytes % 4 != 0))
d3ae8277
SC		 1426 return 0;
1427
225e4f43
R		 1428 if (TARGET_HARD_SH4)
1429 {
1430 if (bytes < 12)
1431 return 0;
1432 else if (bytes == 12)
1433 {
73a4d10b 1434 rtx func_addr_rtx = gen_reg_rtx (Pmode);
c0d4e710
KH		 1435 rtx r4 = gen_rtx_REG (SImode, 4);
1436 rtx r5 = gen_rtx_REG (SImode, 5);
225e4f43 1437
73a4d10b 1438 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
0aa692fc
R		 1439 force_into (XEXP (operands[0], 0), r4);
1440 force_into (XEXP (operands[1], 0), r5);
225e4f43
R		 1441 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1442 return 1;
1443 }
1444 else if (! TARGET_SMALLCODE)
1445 {
73a4d10b
R		 1446 const char *entry_name;
1447 rtx func_addr_rtx = gen_reg_rtx (Pmode);
225e4f43 1448 int dwords;
c0d4e710
KH		 1449 rtx r4 = gen_rtx_REG (SImode, 4);
1450 rtx r5 = gen_rtx_REG (SImode, 5);
1451 rtx r6 = gen_rtx_REG (SImode, 6);
225e4f43 1452
73a4d10b
R		 1453 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1454 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
0aa692fc
R		 1455 force_into (XEXP (operands[0], 0), r4);
1456 force_into (XEXP (operands[1], 0), r5);
225e4f43
R		 1457
1458 dwords = bytes >> 3;
1459 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1460 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1461 return 1;
1462 }
1463 else
1464 return 0;
1465 }
8aa2a305 1466 if (bytes < 64)
0d7e008e
SC		 1467 {
1468 char entry[30];
73a4d10b 1469 rtx func_addr_rtx = gen_reg_rtx (Pmode);
c5c76735
JL		 1470 rtx r4 = gen_rtx_REG (SImode, 4);
1471 rtx r5 = gen_rtx_REG (SImode, 5);
8aa2a305 1472
70128ad9 1473 sprintf (entry, "__movmemSI%d", bytes);
73a4d10b 1474 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
0aa692fc
R		 1475 force_into (XEXP (operands[0], 0), r4);
1476 force_into (XEXP (operands[1], 0), r5);
0d7e008e
SC		 1477 emit_insn (gen_block_move_real (func_addr_rtx));
1478 return 1;
1479 }
8aa2a305
JW		 1480
1481 /* This is the same number of bytes as a memcpy call, but to a different
1482 less common function name, so this will occasionally use more space. */
1483 if (! TARGET_SMALLCODE)
0d7e008e 1484 {
73a4d10b 1485 rtx func_addr_rtx = gen_reg_rtx (Pmode);
8aa2a305 1486 int final_switch, while_loop;
c5c76735
JL		 1487 rtx r4 = gen_rtx_REG (SImode, 4);
1488 rtx r5 = gen_rtx_REG (SImode, 5);
1489 rtx r6 = gen_rtx_REG (SImode, 6);
0d7e008e 1490
73a4d10b 1491 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
0aa692fc
R		 1492 force_into (XEXP (operands[0], 0), r4);
1493 force_into (XEXP (operands[1], 0), r5);
0d7e008e 1494
8aa2a305
JW		 1495 /* r6 controls the size of the move. 16 is decremented from it
1496 for each 64 bytes moved. Then the negative bit left over is used
1497 as an index into a list of move instructions. e.g., a 72 byte move
1498 would be set up with size(r6) = 14, for one iteration through the
1499 big while loop, and a switch of -2 for the last part. */
0d7e008e 1500
8aa2a305
JW		 1501 final_switch = 16 - ((bytes / 4) % 16);
1502 while_loop = ((bytes / 4) / 16 - 1) * 16;
1503 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1504 emit_insn (gen_block_lump_real (func_addr_rtx));
1505 return 1;
0d7e008e 1506 }
0d7e008e 1507
d3ae8277 1508 return 0;
0d7e008e
SC		 1509}
1510
bc45ade3 1511/* Prepare operands for a move define_expand; specifically, one of the
8aa2a305 1512 operands must be in a register. */
bc45ade3 1513
b9654711 1514int
cf277499 1515prepare_move_operands (rtx operands[], enum machine_mode mode)
bc45ade3 1516{
463f02cd
KK		 1517 if ((mode == SImode || mode == DImode)
1518 && flag_pic
1519 && ! ((mode == Pmode || mode == ptr_mode)
81f40b79 1520 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1a66cd67
AO		 1521 {
1522 rtx temp;
1523 if (SYMBOLIC_CONST_P (operands[1]))
1524 {
f3536097 1525 if (MEM_P (operands[0]))
1a66cd67 1526 operands[1] = force_reg (Pmode, operands[1]);
5615d8fd
SC		 1527 else if (TARGET_SHMEDIA
1528 && GET_CODE (operands[1]) == LABEL_REF
fa5322fa
AO		 1529 && target_reg_operand (operands[0], mode))
1530 /* It's ok. */;
1a66cd67
AO		 1531 else
1532 {
b3a13419
ILT		 1533 temp = (!can_create_pseudo_p ()
1534 ? operands[0]
1535 : gen_reg_rtx (Pmode));
fa5322fa 1536 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1a66cd67
AO		 1537 }
1538 }
1539 else if (GET_CODE (operands[1]) == CONST
1540 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1541 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1542 {
b3a13419 1543 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1a66cd67 1544 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
fa5322fa
AO		 1545 mode, temp);
1546 operands[1] = expand_binop (mode, add_optab, temp,
1a66cd67 1547 XEXP (XEXP (operands[1], 0), 1),
b3a13419
ILT		 1548 (!can_create_pseudo_p ()
1549 ? temp
1550 : gen_reg_rtx (Pmode)),
68c37dc9 1551 0, OPTAB_LIB_WIDEN);
1a66cd67
AO		 1552 }
1553 }
1554
e22856e8
JW		 1555 if (! reload_in_progress && ! reload_completed)
1556 {
1557 /* Copy the source to a register if both operands aren't registers. */
1558 if (! register_operand (operands[0], mode)
d9da94a1 1559 && ! sh_register_operand (operands[1], mode))
e22856e8
JW		 1560 operands[1] = copy_to_mode_reg (mode, operands[1]);
1561
f3536097 1562 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
266a2732
R		 1563 {
1564 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1565 except that we can't use that function because it is static. */
0a2aaacc
KG		 1566 rtx new_rtx = change_address (operands[0], mode, 0);
1567 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1568 operands[0] = new_rtx;
266a2732
R		 1569 }
1570
e22856e8
JW		 1571 /* This case can happen while generating code to move the result
1572 of a library call to the target. Reject `st r0,@(rX,rY)' because
1573 reload will fail to find a spill register for rX, since r0 is already
1574 being used for the source. */
73a4d10b
R		 1575 else if (TARGET_SH1
1576 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
f3536097 1577 && MEM_P (operands[0])
e22856e8 1578 && GET_CODE (XEXP (operands[0], 0)) == PLUS
f3536097 1579 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
e22856e8
JW		 1580 operands[1] = copy_to_mode_reg (mode, operands[1]);
1581 }
8aa2a305 1582
463f02cd
KK		 1583 if (mode == Pmode || mode == ptr_mode)
1584 {
6058b2fa 1585 rtx op0, op1, opc;
463f02cd
KK		 1586 enum tls_model tls_kind;
1587
1588 op0 = operands[0];
1589 op1 = operands[1];
6058b2fa
KK		 1590 if (GET_CODE (op1) == CONST
1591 && GET_CODE (XEXP (op1, 0)) == PLUS
81f40b79
ILT		 1592 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1593 != TLS_MODEL_NONE))
6058b2fa
KK		 1594 {
1595 opc = XEXP (XEXP (op1, 0), 1);
1596 op1 = XEXP (XEXP (op1, 0), 0);
1597 }
1598 else
1599 opc = NULL_RTX;
1600
81f40b79 1601 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
463f02cd
KK		 1602 {
1603 rtx tga_op1, tga_ret, tmp, tmp2;
1604
463f02cd
KK		 1605 switch (tls_kind)
1606 {
1607 case TLS_MODEL_GLOBAL_DYNAMIC:
1608 tga_ret = gen_rtx_REG (Pmode, R0_REG);
13ecc9e0 1609 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
463f02cd
KK		 1610 op1 = tga_ret;
1611 break;
1612
1613 case TLS_MODEL_LOCAL_DYNAMIC:
1614 tga_ret = gen_rtx_REG (Pmode, R0_REG);
13ecc9e0 1615 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
463f02cd
KK		 1616
1617 tmp = gen_reg_rtx (Pmode);
1618 emit_move_insn (tmp, tga_ret);
1619
1620 if (register_operand (op0, Pmode))
1621 tmp2 = op0;
1622 else
1623 tmp2 = gen_reg_rtx (Pmode);
1624
1625 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1626 op1 = tmp2;
1627 break;
1628
1629 case TLS_MODEL_INITIAL_EXEC:
1630 if (! flag_pic)
b741fa00 1631 {
b92c3264
KK		 1632 /* Don't schedule insns for getting GOT address when
1633 the first scheduling is enabled, to avoid spill
1634 failures for R0. */
1635 if (flag_schedule_insns)
1636 emit_insn (gen_blockage ());
b741fa00 1637 emit_insn (gen_GOTaddr2picreg ());
c41c1387 1638 emit_use (gen_rtx_REG (SImode, PIC_REG));
b92c3264
KK		 1639 if (flag_schedule_insns)
1640 emit_insn (gen_blockage ());
b741fa00 1641 }
b3a13419 1642 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
463f02cd
KK		 1643 tmp = gen_sym2GOTTPOFF (op1);
1644 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1645 op1 = tga_op1;
1646 break;
1647
1648 case TLS_MODEL_LOCAL_EXEC:
1649 tmp2 = gen_reg_rtx (Pmode);
1650 emit_insn (gen_load_gbr (tmp2));
1651 tmp = gen_reg_rtx (Pmode);
1652 emit_insn (gen_symTPOFF2reg (tmp, op1));
463f02cd
KK		 1653
1654 if (register_operand (op0, Pmode))
1655 op1 = op0;
1656 else
1657 op1 = gen_reg_rtx (Pmode);
1658
1659 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1660 break;
1661
1662 default:
f5b9e7c9 1663 gcc_unreachable ();
463f02cd 1664 }
6058b2fa
KK		 1665 if (opc)
1666 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
463f02cd
KK		 1667 operands[1] = op1;
1668 }
1669 }
1670
8aa2a305
JW		 1671 return 0;
1672}
1673
78d310c2
R		 1674enum rtx_code
1675prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1676 enum rtx_code comparison)
1677{
1678 rtx op1;
1679 rtx scratch = NULL_RTX;
1680
b757d36f 1681 if (comparison == LAST_AND_UNUSED_RTX_CODE)
78d310c2
R		 1682 comparison = GET_CODE (operands[0]);
1683 else
1684 scratch = operands[4];
f3536097
SZ		 1685 if (CONST_INT_P (operands[1])
1686 && !CONST_INT_P (operands[2]))
78d310c2
R		 1687 {
1688 rtx tmp = operands[1];
1689
1690 operands[1] = operands[2];
1691 operands[2] = tmp;
1692 comparison = swap_condition (comparison);
1693 }
f3536097 1694 if (CONST_INT_P (operands[2]))
78d310c2
R		 1695 {
1696 HOST_WIDE_INT val = INTVAL (operands[2]);
1697 if ((val == -1 || val == -0x81)
1698 && (comparison == GT || comparison == LE))
1699 {
1700 comparison = (comparison == GT) ? GE : LT;
1701 operands[2] = gen_int_mode (val + 1, mode);
1702 }
1703 else if ((val == 1 || val == 0x80)
1704 && (comparison == GE || comparison == LT))
1705 {
1706 comparison = (comparison == GE) ? GT : LE;
1707 operands[2] = gen_int_mode (val - 1, mode);
1708 }
1709 else if (val == 1 && (comparison == GEU || comparison == LTU))
1710 {
1711 comparison = (comparison == GEU) ? NE : EQ;
1712 operands[2] = CONST0_RTX (mode);
1713 }
1714 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1715 {
1716 comparison = (comparison == GEU) ? GTU : LEU;
1717 operands[2] = gen_int_mode (val - 1, mode);
1718 }
1719 else if (val == 0 && (comparison == GTU || comparison == LEU))
1720 comparison = (comparison == GTU) ? NE : EQ;
1721 else if (mode == SImode
1722 && ((val == 0x7fffffff
1723 && (comparison == GTU || comparison == LEU))
1724 || ((unsigned HOST_WIDE_INT) val
1725 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1726 && (comparison == GEU || comparison == LTU))))
1727 {
1728 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1729 operands[2] = CONST0_RTX (mode);
1730 }
1731 }
1732 op1 = operands[1];
b3a13419 1733 if (can_create_pseudo_p ())
78d310c2
R		 1734 operands[1] = force_reg (mode, op1);
1735 /* When we are handling DImode comparisons, we want to keep constants so
1736 that we can optimize the component comparisons; however, memory loads
1737 are better issued as a whole so that they can be scheduled well.
1738 SImode equality comparisons allow I08 constants, but only when they
1739 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1740 into a register, that register might as well be r0, and we allow the
1741 constant. If it is already in a register, this is likely to be
2f8e468b 1742 allocated to a different hard register, thus we load the constant into
78d310c2
R		 1743 a register unless it is zero. */
1744 if (!REG_P (operands[2])
f3536097 1745 && (!CONST_INT_P (operands[2])
78d310c2
R		 1746 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1747 && ((comparison != EQ && comparison != NE)
1748 || (REG_P (op1) && REGNO (op1) != R0_REG)
32a7ab3d 1749 || !satisfies_constraint_I08 (operands[2])))))
78d310c2
R		 1750 {
1751 if (scratch && GET_MODE (scratch) == mode)
1752 {
1753 emit_move_insn (scratch, operands[2]);
1754 operands[2] = scratch;
1755 }
b3a13419 1756 else if (can_create_pseudo_p ())
78d310c2
R		 1757 operands[2] = force_reg (mode, operands[2]);
1758 }
1759 return comparison;
1760}
1761
1762void
1763expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1764{
1765 rtx (*branch_expander) (rtx) = gen_branch_true;
1766 rtx jump;
1767
1768 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1769 switch (comparison)
1770 {
1771 case NE: case LT: case LE: case LTU: case LEU:
1772 comparison = reverse_condition (comparison);
1773 branch_expander = gen_branch_false;
1774 default: ;
1775 }
1776 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1777 gen_rtx_fmt_ee (comparison, SImode,
1778 operands[1], operands[2])));
1779 jump = emit_jump_insn (branch_expander (operands[3]));
1780 if (probability >= 0)
b757d36f 1781 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
78d310c2
R		 1782
1783}
1784
1785/* ??? How should we distribute probabilities when more than one branch
1786 is generated. So far we only have soem ad-hoc observations:
1787 - If the operands are random, they are likely to differ in both parts.
1788 - If comparing items in a hash chain, the operands are random or equal;
1789 operation should be EQ or NE.
1790 - If items are searched in an ordered tree from the root, we can expect
1791 the highpart to be unequal about half of the time; operation should be
2f8e468b 1792 an inequality comparison, operands non-constant, and overall probability
78d310c2
R		 1793 about 50%. Likewise for quicksort.
1794 - Range checks will be often made against constants. Even if we assume for
1795 simplicity an even distribution of the non-constant operand over a
1796 sub-range here, the same probability could be generated with differently
1797 wide sub-ranges - as long as the ratio of the part of the subrange that
1798 is before the threshold to the part that comes after the threshold stays
1799 the same. Thus, we can't really tell anything here;
1800 assuming random distribution is at least simple.
1801 */
1802
1803bool
1804expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1805{
1806 enum rtx_code msw_taken, msw_skip, lsw_taken;
cb3d3842 1807 rtx skip_label = NULL_RTX;
78d310c2
R		 1808 rtx op1h, op1l, op2h, op2l;
1809 int num_branches;
1810 int prob, rev_prob;
1811 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
6f8eec29 1812 rtx scratch = operands[4];
78d310c2
R		 1813
1814 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1815 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1816 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1817 op1l = gen_lowpart (SImode, operands[1]);
1818 op2l = gen_lowpart (SImode, operands[2]);
b757d36f 1819 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
78d310c2
R		 1820 prob = split_branch_probability;
1821 rev_prob = REG_BR_PROB_BASE - prob;
1822 switch (comparison)
1823 {
1824 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1825 That costs 1 cycle more when the first branch can be predicted taken,
1826 but saves us mispredicts because only one branch needs prediction.
1827 It also enables generating the cmpeqdi_t-1 pattern. */
1828 case EQ:
1829 if (TARGET_CMPEQDI_T)
1830 {
1831 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1832 emit_jump_insn (gen_branch_true (operands[3]));
1833 return true;
1834 }
1835 msw_skip = NE;
1836 lsw_taken = EQ;
1837 if (prob >= 0)
1838 {
1839 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1840 */
1841 msw_skip_prob = rev_prob;
1842 if (REG_BR_PROB_BASE <= 65535)
1843 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1844 else
1845 {
1846 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1847 lsw_taken_prob
1848 = (prob
1849 ? (REG_BR_PROB_BASE
1850 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1851 / ((HOST_WIDEST_INT) prob << 32)))
1852 : 0);
1853 }
1854 }
1855 break;
1856 case NE:
1857 if (TARGET_CMPEQDI_T)
1858 {
1859 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1860 emit_jump_insn (gen_branch_false (operands[3]));
1861 return true;
1862 }
1863 msw_taken = NE;
6f8eec29 1864 msw_taken_prob = prob;
78d310c2
R		 1865 lsw_taken = NE;
1866 lsw_taken_prob = 0;
1867 break;
1868 case GTU: case GT:
1869 msw_taken = comparison;
f3536097 1870 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
78d310c2
R		 1871 break;
1872 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1873 msw_skip = swap_condition (msw_taken);
1874 lsw_taken = GTU;
1875 break;
1876 case GEU: case GE:
1877 if (op2l == CONST0_RTX (SImode))
1878 msw_taken = comparison;
1879 else
1880 {
1881 msw_taken = comparison == GE ? GT : GTU;
1882 msw_skip = swap_condition (msw_taken);
1883 lsw_taken = GEU;
1884 }
1885 break;
1886 case LTU: case LT:
1887 msw_taken = comparison;
1888 if (op2l == CONST0_RTX (SImode))
1889 break;
1890 msw_skip = swap_condition (msw_taken);
1891 lsw_taken = LTU;
1892 break;
1893 case LEU: case LE:
f3536097 1894 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
78d310c2
R		 1895 msw_taken = comparison;
1896 else
1897 {
1898 lsw_taken = LEU;
1899 if (comparison == LE)
1900 msw_taken = LT;
1901 else if (op2h != CONST0_RTX (SImode))
1902 msw_taken = LTU;
1903 else
1904 break;
1905 msw_skip = swap_condition (msw_taken);
1906 }
1907 break;
1908 default: return false;
1909 }
b757d36f
KK		 1910 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
1911 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1912 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
78d310c2
R		 1913 if (comparison != EQ && comparison != NE && num_branches > 1)
1914 {
1915 if (!CONSTANT_P (operands[2])
1916 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1917 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1918 {
1919 msw_taken_prob = prob / 2U;
1920 msw_skip_prob
1921 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1922 lsw_taken_prob = prob;
1923 }
1924 else
1925 {
1926 msw_taken_prob = prob;
1927 msw_skip_prob = REG_BR_PROB_BASE;
1928 /* ??? If we have a constant op2h, should we use that when
1929 calculating lsw_taken_prob? */
1930 lsw_taken_prob = prob;
1931 }
1932 }
1933 operands[1] = op1h;
1934 operands[2] = op2h;
1935 operands[4] = NULL_RTX;
6f8eec29 1936 if (reload_completed
99052692
KK		 1937 && ! arith_reg_or_0_operand (op2h, SImode)
1938 && (true_regnum (op1h) || (comparison != EQ && comparison != NE))
b757d36f
KK		 1939 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
1940 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
6f8eec29
R		 1941 {
1942 emit_move_insn (scratch, operands[2]);
1943 operands[2] = scratch;
1944 }
b757d36f 1945 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
78d310c2 1946 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
b757d36f 1947 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
78d310c2
R		 1948 {
1949 rtx taken_label = operands[3];
1950
d60819f8
CB		 1951 /* Operands were possibly modified, but msw_skip doesn't expect this.
1952 Always use the original ones. */
b757d36f 1953 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
d60819f8
CB		 1954 {
1955 operands[1] = op1h;
1956 operands[2] = op2h;
1957 }
1958
78d310c2
R		 1959 operands[3] = skip_label = gen_label_rtx ();
1960 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
1961 operands[3] = taken_label;
1962 }
1963 operands[1] = op1l;
1964 operands[2] = op2l;
b757d36f 1965 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
6f8eec29
R		 1966 {
1967 if (reload_completed
99052692
KK		 1968 && ! arith_reg_or_0_operand (op2l, SImode)
1969 && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE)))
1970 {
1971 emit_move_insn (scratch, operands[2]);
1972 operands[2] = scratch;
1973 }
6f8eec29
R		 1974 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
1975 }
b757d36f 1976 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
78d310c2
R		 1977 emit_label (skip_label);
1978 return true;
1979}
1980
f90b7a5a
PB		 1981/* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
1982
1983static void
1984sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
1985{
1986 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1987 {
1988 insn = gen_rtx_PARALLEL (VOIDmode,
1989 gen_rtvec (2, insn,
1990 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
1991 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1992 }
1993 else
1994 emit_insn (insn);
1995}
1996
8aa2a305 1997/* Prepare the operands for an scc instruction; make sure that the
f90b7a5a
PB		 1998 compare has been done and the result is in T_REG. */
1999void
2000sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
8aa2a305 2001{
c5c76735 2002 rtx t_reg = gen_rtx_REG (SImode, T_REG);
8aa2a305 2003 enum rtx_code oldcode = code;
9374bd85 2004 enum machine_mode mode;
8aa2a305
JW		 2005
2006 /* First need a compare insn. */
2007 switch (code)
bc45ade3 2008 {
8aa2a305
JW		 2009 case NE:
2010 /* It isn't possible to handle this case. */
f5b9e7c9 2011 gcc_unreachable ();
8aa2a305
JW		 2012 case LT:
2013 code = GT;
2014 break;
2015 case LE:
2016 code = GE;
2017 break;
2018 case LTU:
2019 code = GTU;
2020 break;
2021 case LEU:
2022 code = GEU;
2023 break;
10db12e0
R		 2024 default:
2025 break;
bc45ade3 2026 }
8aa2a305 2027 if (code != oldcode)
b9654711 2028 {
f90b7a5a
PB		 2029 rtx tmp = op0;
2030 op0 = op1;
2031 op1 = tmp;
0d7e008e 2032 }
b9654711 2033
f90b7a5a 2034 mode = GET_MODE (op0);
9374bd85 2035 if (mode == VOIDmode)
f90b7a5a 2036 mode = GET_MODE (op1);
9374bd85 2037
f90b7a5a 2038 op0 = force_reg (mode, op0);
1245df60 2039 if ((code != EQ && code != NE
f90b7a5a 2040 && (op1 != const0_rtx
1245df60 2041 || code == GTU || code == GEU || code == LTU || code == LEU))
f90b7a5a 2042 || (mode == DImode && op1 != const0_rtx)
3a8699c7 2043 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
f90b7a5a 2044 op1 = force_reg (mode, op1);
0d7e008e 2045
f90b7a5a
PB		 2046 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode, t_reg,
2047 gen_rtx_fmt_ee (code, SImode, op0, op1)),
2048 mode);
2049}
0d7e008e 2050
f90b7a5a
PB		 2051rtx
2052sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
2053 rtx op0, rtx op1)
2054{
2055 rtx target = gen_reg_rtx (SImode);
2056 rtx tmp;
2057
2058 gcc_assert (TARGET_SHMEDIA);
2059 switch (code)
2060 {
2061 case EQ:
2062 case GT:
2063 case LT:
2064 case UNORDERED:
2065 case GTU:
2066 case LTU:
2067 tmp = gen_rtx_fmt_ee (code, SImode, op0, op1);
2068 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2069 code = NE;
2070 break;
2071
2072 case NE:
2073 case GE:
2074 case LE:
2075 case ORDERED:
2076 case GEU:
2077 case LEU:
2078 tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1);
2079 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2080 code = EQ;
2081 break;
2082
2083 case UNEQ:
2084 case UNGE:
2085 case UNGT:
2086 case UNLE:
2087 case UNLT:
2088 case LTGT:
2089 return NULL_RTX;
2090
2091 default:
2092 gcc_unreachable ();
2093 }
2094
2095 if (mode == DImode)
2096 {
2097 rtx t2 = gen_reg_rtx (DImode);
2098 emit_insn (gen_extendsidi2 (t2, target));
2099 target = t2;
2100 }
2101
2102 return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx);
bc45ade3
SC		 2103}
2104
8aa2a305
JW		 2105/* Called from the md file, set up the operands of a compare instruction. */
2106
2107void
f90b7a5a 2108sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
bc45ade3 2109{
f90b7a5a
PB		 2110 enum rtx_code code = GET_CODE (operands[0]);
2111 enum rtx_code branch_code;
2112 rtx op0 = operands[1];
2113 rtx op1 = operands[2];
2114 rtx insn, tem;
2115 bool need_ccmpeq = false;
2116
2117 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
bc45ade3 2118 {
f90b7a5a
PB		 2119 op0 = force_reg (mode, op0);
2120 op1 = force_reg (mode, op1);
bc45ade3 2121 }
f90b7a5a 2122 else
1245df60 2123 {
f90b7a5a
PB		 2124 if (code != EQ || mode == DImode)
2125 {
2126 /* Force args into regs, since we can't use constants here. */
2127 op0 = force_reg (mode, op0);
2128 if (op1 != const0_rtx || code == GTU || code == GEU)
2129 op1 = force_reg (mode, op1);
2130 }
1245df60 2131 }
f90b7a5a
PB		 2132
2133 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2134 {
2135 if (code == LT
2136 || (code == LE && TARGET_IEEE && TARGET_SH2E)
2137 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
2138 {
2139 tem = op0, op0 = op1, op1 = tem;
2140 code = swap_condition (code);
2141 }
2142
2143 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2144 if (code == GE)
2145 {
2146 gcc_assert (TARGET_IEEE && TARGET_SH2E);
2147 need_ccmpeq = true;
2148 code = GT;
2149 }
2150
2151 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2152 to EQ/GT respectively. */
2153 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
2154 }
2155
2156 switch (code)
2157 {
2158 case EQ:
2159 case GT:
2160 case GE:
2161 case GTU:
2162 case GEU:
2163 branch_code = code;
2164 break;
2165 case NE:
2166 case LT:
2167 case LE:
2168 case LTU:
2169 case LEU:
2170 branch_code = reverse_condition (code);
2171 break;
2172 default:
2173 gcc_unreachable ();
2174 }
2175
2176 insn = gen_rtx_SET (VOIDmode,
2177 gen_rtx_REG (SImode, T_REG),
2178 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
2179
2180 sh_emit_set_t_insn (insn, mode);
2181 if (need_ccmpeq)
2182 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
2183
2184 if (branch_code == code)
2185 emit_jump_insn (gen_branch_true (operands[3]));
1245df60 2186 else
f90b7a5a
PB		 2187 emit_jump_insn (gen_branch_false (operands[3]));
2188}
2189
2190void
2191sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
2192{
2193 enum rtx_code code = GET_CODE (operands[1]);
2194 rtx op0 = operands[2];
2195 rtx op1 = operands[3];
2196 rtx lab = NULL_RTX;
2197 bool invert = false;
2198 rtx tem;
2199
2200 op0 = force_reg (mode, op0);
2201 if ((code != EQ && code != NE
2202 && (op1 != const0_rtx
2203 || code == GTU || code == GEU || code == LTU || code == LEU))
2204 || (mode == DImode && op1 != const0_rtx)
2205 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2206 op1 = force_reg (mode, op1);
2207
2208 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
225e4f43 2209 {
f90b7a5a
PB		 2210 if (code == LT || code == LE)
2211 {
2212 code = swap_condition (code);
2213 tem = op0, op0 = op1, op1 = tem;
2214 }
2215 if (code == GE)
2216 {
2217 if (TARGET_IEEE)
2218 {
2219 lab = gen_label_rtx ();
2220 sh_emit_scc_to_t (EQ, op0, op1);
2221 emit_jump_insn (gen_branch_true (lab));
2222 code = GT;
2223 }
2224 else
2225 {
2226 code = LT;
2227 invert = true;
2228 }
2229 }
225e4f43 2230 }
f90b7a5a
PB		 2231
2232 if (code == NE)
2233 {
2234 code = EQ;
2235 invert = true;
2236 }
2237
2238 sh_emit_scc_to_t (code, op0, op1);
2239 if (lab)
2240 emit_label (lab);
2241 if (invert)
2242 emit_insn (gen_movnegt (operands[0]));
225e4f43 2243 else
f90b7a5a 2244 emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
bc45ade3
SC		 2245}
2246\f
16bea517 2247/* Functions to output assembly code. */
bc45ade3 2248
b9654711 2249/* Return a sequence of instructions to perform DI or DF move.
bc45ade3 2250
b9654711 2251 Since the SH cannot move a DI or DF in one instruction, we have
16bea517 2252 to take care when we see overlapping source and dest registers. */
0d7e008e 2253
318881c0 2254const char *
cf277499
SB		 2255output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
2256 enum machine_mode mode)
bc45ade3 2257{
b9654711
SC		 2258 rtx dst = operands[0];
2259 rtx src = operands[1];
b9654711 2260
f3536097 2261 if (MEM_P (dst)
16bea517 2262 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
8aa2a305
JW		 2263 return "mov.l %T1,%0\n\tmov.l %1,%0";
2264
b9654711
SC		 2265 if (register_operand (dst, mode)
2266 && register_operand (src, mode))
bc45ade3 2267 {
b9654711 2268 if (REGNO (src) == MACH_REG)
00f8ff66 2269 return "sts mach,%S0\n\tsts macl,%R0";
bc45ade3 2270
8aa2a305
JW		 2271 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2272 when mov.d r1,r0 do r1->r0 then r2->r1. */
b9654711
SC		 2273
2274 if (REGNO (src) + 1 == REGNO (dst))
5325c0fa 2275 return "mov %T1,%T0\n\tmov %1,%0";
b9654711 2276 else
5325c0fa 2277 return "mov %1,%0\n\tmov %T1,%T0";
b9654711 2278 }
f3536097 2279 else if (CONST_INT_P (src))
bc45ade3 2280 {
8aa2a305
JW		 2281 if (INTVAL (src) < 0)
2282 output_asm_insn ("mov #-1,%S0", operands);
bc45ade3 2283 else
8aa2a305 2284 output_asm_insn ("mov #0,%S0", operands);
bc45ade3 2285
8aa2a305 2286 return "mov %1,%R0";
0d7e008e 2287 }
f3536097 2288 else if (MEM_P (src))
bc45ade3 2289 {
8aa2a305 2290 int ptrreg = -1;
b9654711
SC		 2291 int dreg = REGNO (dst);
2292 rtx inside = XEXP (src, 0);
bc45ade3 2293
f5b9e7c9 2294 switch (GET_CODE (inside))
bc45ade3 2295 {
f5b9e7c9
NS		 2296 case REG:
2297 ptrreg = REGNO (inside);
2298 break;
2299
2300 case SUBREG:
2301 ptrreg = subreg_regno (inside);
2302 break;
2303
2304 case PLUS:
8aa2a305
JW		 2305 ptrreg = REGNO (XEXP (inside, 0));
2306 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2307 an offsettable address. Unfortunately, offsettable addresses use
2308 QImode to check the offset, and a QImode offsettable address
2309 requires r0 for the other operand, which is not currently
2310 supported, so we can't use the 'o' constraint.
2311 Thus we must check for and handle r0+REG addresses here.
2312 We punt for now, since this is likely very rare. */
f3536097 2313 gcc_assert (!REG_P (XEXP (inside, 1)));
f5b9e7c9
NS		 2314 break;
2315
2316 case LABEL_REF:
2317 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2318 case POST_INC:
2319 return "mov.l %1,%0\n\tmov.l %1,%T0";
2320 default:
2321 gcc_unreachable ();
bc45ade3 2322 }
bc45ade3 2323
8aa2a305
JW		 2324 /* Work out the safe way to copy. Copy into the second half first. */
2325 if (dreg == ptrreg)
2326 return "mov.l %T1,%T0\n\tmov.l %1,%0";
bc45ade3
SC		 2327 }
2328
00f8ff66 2329 return "mov.l %1,%0\n\tmov.l %T1,%T0";
bc45ade3
SC		 2330}
2331
8aa2a305
JW		 2332/* Print an instruction which would have gone into a delay slot after
2333 another instruction, but couldn't because the other instruction expanded
2334 into a sequence where putting the slot insn at the end wouldn't work. */
0d7e008e 2335
8aa2a305 2336static void
cf277499 2337print_slot (rtx insn)
8aa2a305 2338{
c9d691e9 2339 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
b9654711 2340
8aa2a305
JW		 2341 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
2342}
0d7e008e 2343
318881c0 2344const char *
cf277499 2345output_far_jump (rtx insn, rtx op)
0d7e008e 2346{
0a2aaacc 2347 struct { rtx lab, reg, op; } this_jmp;
950a3816 2348 rtx braf_base_lab = NULL_RTX;
318881c0 2349 const char *jump;
1245df60 2350 int far;
9d98a694 2351 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
10f4f635 2352 rtx prev;
0d7e008e 2353
0a2aaacc 2354 this_jmp.lab = gen_label_rtx ();
b9654711 2355
1a953d0f
R		 2356 if (TARGET_SH2
2357 && offset >= -32764
2358 && offset - get_attr_length (insn) <= 32766)
1245df60
R		 2359 {
2360 far = 0;
e6dfd05f 2361 jump = "mov.w %O0,%1; braf %1";
1245df60
R		 2362 }
2363 else
2364 {
2365 far = 1;
1a66cd67 2366 if (flag_pic)
e6dfd05f
AO		 2367 {
2368 if (TARGET_SH2)
2369 jump = "mov.l %O0,%1; braf %1";
2370 else
2371 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2372 }
1a66cd67 2373 else
e6dfd05f 2374 jump = "mov.l %O0,%1; jmp @%1";
1245df60
R		 2375 }
2376 /* If we have a scratch register available, use it. */
f3536097 2377 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
10f4f635 2378 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
1245df60 2379 {
0a2aaacc
KG		 2380 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2381 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
e6dfd05f 2382 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
0a2aaacc 2383 output_asm_insn (jump, &this_jmp.lab);
1245df60
R		 2384 if (dbr_sequence_length ())
2385 print_slot (final_sequence);
2386 else
2387 output_asm_insn ("nop", 0);
2388 }
2389 else
2390 {
2391 /* Output the delay slot insn first if any. */
2392 if (dbr_sequence_length ())
2393 print_slot (final_sequence);
2394
0a2aaacc 2395 this_jmp.reg = gen_rtx_REG (SImode, 13);
fa5322fa
AO		 2396 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2397 Fortunately, MACL is fixed and call-clobbered, and we never
2398 need its value across jumps, so save r13 in it instead of in
2399 the stack. */
2400 if (TARGET_SH5)
2401 output_asm_insn ("lds r13, macl", 0);
2402 else
2403 output_asm_insn ("mov.l r13,@-r15", 0);
0a2aaacc 2404 output_asm_insn (jump, &this_jmp.lab);
fa5322fa
AO		 2405 if (TARGET_SH5)
2406 output_asm_insn ("sts macl, r13", 0);
2407 else
2408 output_asm_insn ("mov.l @r15+,r13", 0);
1245df60 2409 }
e6dfd05f
AO		 2410 if (far && flag_pic && TARGET_SH2)
2411 {
2412 braf_base_lab = gen_label_rtx ();
4977bab6 2413 (*targetm.asm_out.internal_label) (asm_out_file, "L",
e6dfd05f
AO		 2414 CODE_LABEL_NUMBER (braf_base_lab));
2415 }
1245df60
R		 2416 if (far)
2417 output_asm_insn (".align 2", 0);
0a2aaacc
KG		 2418 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2419 this_jmp.op = op;
1a66cd67 2420 if (far && flag_pic)
e6dfd05f
AO		 2421 {
2422 if (TARGET_SH2)
0a2aaacc
KG		 2423 this_jmp.lab = braf_base_lab;
2424 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
e6dfd05f 2425 }
1a66cd67 2426 else
0a2aaacc 2427 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
0d7e008e
SC		 2428 return "";
2429}
bc45ade3 2430
8aa2a305
JW		 2431/* Local label counter, used for constants in the pool and inside
2432 pattern branches. */
2433
2434static int lf = 100;
2435
2436/* Output code for ordinary branches. */
2437
318881c0 2438const char *
cf277499 2439output_branch (int logic, rtx insn, rtx *operands)
bc45ade3 2440{
afbc5d86 2441 switch (get_attr_length (insn))
bc45ade3 2442 {
33f7f353
JR		 2443 case 6:
2444 /* This can happen if filling the delay slot has caused a forward
2445 branch to exceed its range (we could reverse it, but only
2446 when we know we won't overextend other branches; this should
2447 best be handled by relaxation).
2448 It can also happen when other condbranches hoist delay slot insn
1245df60
R		 2449 from their destination, thus leading to code size increase.
2450 But the branch will still be in the range -4092..+4098 bytes. */
bc45ade3 2451
33f7f353 2452 if (! TARGET_RELAX)
1245df60 2453 {
33f7f353
JR		 2454 int label = lf++;
2455 /* The call to print_slot will clobber the operands. */
2456 rtx op0 = operands[0];
f676971a 2457
33f7f353
JR		 2458 /* If the instruction in the delay slot is annulled (true), then
2459 there is no delay slot where we can put it now. The only safe
2460 place for it is after the label. final will do that by default. */
f676971a 2461
33f7f353 2462 if (final_sequence
bee9efbc
KK		 2463 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2464 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
33f7f353 2465 {
afbc5d86 2466 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
33f7f353
JR		 2467 ASSEMBLER_DIALECT ? "/" : ".", label);
2468 print_slot (final_sequence);
2469 }
2470 else
afbc5d86 2471 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
f676971a 2472
afbc5d86
R		 2473 output_asm_insn ("bra\t%l0", &op0);
2474 fprintf (asm_out_file, "\tnop\n");
832a3292 2475 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
f676971a 2476
33f7f353 2477 return "";
1245df60 2478 }
33f7f353
JR		 2479 /* When relaxing, handle this like a short branch. The linker
2480 will fix it up if it still doesn't fit after relaxation. */
2481 case 2:
2482 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
3a8699c7
AO		 2483
2484 /* These are for SH2e, in which we have to account for the
2485 extra nop because of the hardware bug in annulled branches. */
2486 case 8:
2487 if (! TARGET_RELAX)
2488 {
2489 int label = lf++;
2490
f5b9e7c9
NS		 2491 gcc_assert (!final_sequence
2492 || !(INSN_ANNULLED_BRANCH_P
2493 (XVECEXP (final_sequence, 0, 0))));
3a8699c7
AO		 2494 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2495 logic ? "f" : "t",
2496 ASSEMBLER_DIALECT ? "/" : ".", label);
2497 fprintf (asm_out_file, "\tnop\n");
2498 output_asm_insn ("bra\t%l0", operands);
2499 fprintf (asm_out_file, "\tnop\n");
2500 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2501
2502 return "";
2503 }
2504 /* When relaxing, fall through. */
2505 case 4:
2506 {
2507 char buffer[10];
f676971a 2508
3a8699c7
AO		 2509 sprintf (buffer, "b%s%ss\t%%l0",
2510 logic ? "t" : "f",
2511 ASSEMBLER_DIALECT ? "/" : ".");
2512 output_asm_insn (buffer, &operands[0]);
2513 return "nop";
2514 }
2515
33f7f353 2516 default:
afbc5d86
R		 2517 /* There should be no longer branches now - that would
2518 indicate that something has destroyed the branches set
2519 up in machine_dependent_reorg. */
f5b9e7c9 2520 gcc_unreachable ();
1245df60 2521 }
1245df60 2522}
bc45ade3 2523
0a2aaacc 2524/* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
78d310c2
R		 2525 fill in operands 9 as a label to the successor insn.
2526 We try to use jump threading where possible.
2527 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2528 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2529 follow jmp and bt, if the address is in range. */
318881c0 2530const char *
0a2aaacc 2531output_branchy_insn (enum rtx_code code, const char *templ,
cf277499 2532 rtx insn, rtx *operands)
1245df60
R		 2533{
2534 rtx next_insn = NEXT_INSN (insn);
79b2746a 2535
f3536097 2536 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
1245df60
R		 2537 {
2538 rtx src = SET_SRC (PATTERN (next_insn));
2539 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2540 {
2541 /* Following branch not taken */
2542 operands[9] = gen_label_rtx ();
2543 emit_label_after (operands[9], next_insn);
9d98a694
AO		 2544 INSN_ADDRESSES_NEW (operands[9],
2545 INSN_ADDRESSES (INSN_UID (next_insn))
2546 + get_attr_length (next_insn));
0a2aaacc 2547 return templ;
1245df60
R		 2548 }
2549 else
2550 {
33f7f353 2551 int offset = (branch_dest (next_insn)
9d98a694 2552 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
33f7f353 2553 if (offset >= -252 && offset <= 258)
1245df60
R		 2554 {
2555 if (GET_CODE (src) == IF_THEN_ELSE)
2556 /* branch_true */
2557 src = XEXP (src, 1);
2558 operands[9] = src;
0a2aaacc 2559 return templ;
1245df60
R		 2560 }
2561 }
bc45ade3 2562 }
1245df60
R		 2563 operands[9] = gen_label_rtx ();
2564 emit_label_after (operands[9], insn);
9d98a694
AO		 2565 INSN_ADDRESSES_NEW (operands[9],
2566 INSN_ADDRESSES (INSN_UID (insn))
2567 + get_attr_length (insn));
0a2aaacc 2568 return templ;
1245df60 2569}
e4fa6b06 2570
318881c0 2571const char *
cf277499 2572output_ieee_ccmpeq (rtx insn, rtx *operands)
1245df60 2573{
9fd0c419
R		 2574 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2575 insn, operands);
bc45ade3 2576}
8e87e161 2577\f
1bc7c5b6 2578/* Output the start of the assembler file. */
8aa2a305 2579
1bc7c5b6 2580static void
cf277499 2581sh_file_start (void)
bc45ade3 2582{
1bc7c5b6
ZW		 2583 default_file_start ();
2584
b55e3aad
NC		 2585#ifdef SYMBIAN
2586 /* Declare the .directive section before it is used. */
2587 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2588 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2589#endif
f676971a 2590
1bc7c5b6
ZW		 2591 if (TARGET_ELF)
2592 /* We need to show the text section with the proper
2593 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
0fe7abcc 2594 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
1bc7c5b6
ZW		 2595 will complain. We can teach GAS specifically about the
2596 default attributes for our choice of text section, but
2597 then we would have to change GAS again if/when we change
2598 the text section name. */
2599 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2600 else
2601 /* Switch to the data section so that the coffsem symbol
2602 isn't in the text section. */
d6b5193b 2603 switch_to_section (data_section);
b9654711 2604
8aa2a305 2605 if (TARGET_LITTLE_ENDIAN)
1bc7c5b6 2606 fputs ("\t.little\n", asm_out_file);
fa5322fa 2607
1bc7c5b6
ZW		 2608 if (!TARGET_ELF)
2609 {
2610 if (TARGET_SHCOMPACT)
2611 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2612 else if (TARGET_SHMEDIA)
2613 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2614 TARGET_SHMEDIA64 ? 64 : 32);
2615 }
bc45ade3 2616}
0d7e008e 2617\f
9f3a9a08
KK		 2618/* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2619
2620static bool
cf277499 2621unspec_caller_rtx_p (rtx pat)
9f3a9a08 2622{
dc3ba671
RS		 2623 rtx base, offset;
2624 int i;
2625
2626 split_const (pat, &base, &offset);
2627 if (GET_CODE (base) == UNSPEC)
9f3a9a08 2628 {
dc3ba671 2629 if (XINT (base, 1) == UNSPEC_CALLER)
9f3a9a08 2630 return true;
dc3ba671
RS		 2631 for (i = 0; i < XVECLEN (base, 0); i++)
2632 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2633 return true;
9f3a9a08 2634 }
9f3a9a08
KK		 2635 return false;
2636}
2637
2638/* Indicate that INSN cannot be duplicated. This is true for insn
569b7f6a 2639 that generates a unique label. */
9f3a9a08
KK		 2640
2641static bool
cf277499 2642sh_cannot_copy_insn_p (rtx insn)
9f3a9a08
KK		 2643{
2644 rtx pat;
2645
2646 if (!reload_completed || !flag_pic)
2647 return false;
2648
f3536097 2649 if (!NONJUMP_INSN_P (insn))
9f3a9a08
KK		 2650 return false;
2651 if (asm_noperands (insn) >= 0)
2652 return false;
2653
2654 pat = PATTERN (insn);
2655 if (GET_CODE (pat) != SET)
2656 return false;
2657 pat = SET_SRC (pat);
2658
2659 if (unspec_caller_rtx_p (pat))
2660 return true;
2661
2662 return false;
2663}
2664\f
16bea517 2665/* Actual number of instructions used to make a shift by N. */
0b5826ac 2666static const char ashiftrt_insns[] =
16bea517
JW		 2667 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2668
2669/* Left shift and logical right shift are the same. */
0b5826ac 2670static const char shift_insns[] =
16bea517 2671 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
8aa2a305 2672
16bea517
JW		 2673/* Individual shift amounts needed to get the above length sequences.
2674 One bit right shifts clobber the T bit, so when possible, put one bit
2675 shifts in the middle of the sequence, so the ends are eligible for
2676 branch delay slots. */
0139adca 2677static const short shift_amounts[32][5] = {
16bea517
JW		 2678 {0}, {1}, {2}, {2, 1},
2679 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2680 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2681 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2682 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2683 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2684 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1d3534c0 2685 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
16bea517 2686
8d481241
JW		 2687/* Likewise, but for shift amounts < 16, up to three highmost bits
2688 might be clobbered. This is typically used when combined with some
2689 kind of sign or zero extension. */
f676971a 2690
0b5826ac 2691static const char ext_shift_insns[] =
8d481241
JW		 2692 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2693
0b5826ac 2694static const short ext_shift_amounts[32][4] = {
8d481241
JW		 2695 {0}, {1}, {2}, {2, 1},
2696 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2697 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2698 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2699 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2700 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2701 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2702 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2703
ae9d19c0
JR		 2704/* Assuming we have a value that has been sign-extended by at least one bit,
2705 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2706 to shift it by N without data loss, and quicker than by other means? */
2707#define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2708
16bea517
JW		 2709/* This is used in length attributes in sh.md to help compute the length
2710 of arbitrary constant shift instructions. */
bc45ade3 2711
16bea517 2712int
cf277499 2713shift_insns_rtx (rtx insn)
16bea517
JW		 2714{
2715 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
6c34a092 2716 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
16bea517 2717 enum rtx_code shift_code = GET_CODE (set_src);
00f8ff66 2718
16bea517
JW		 2719 switch (shift_code)
2720 {
2721 case ASHIFTRT:
2722 return ashiftrt_insns[shift_count];
2723 case LSHIFTRT:
2724 case ASHIFT:
2725 return shift_insns[shift_count];
2726 default:
f5b9e7c9 2727 gcc_unreachable ();
16bea517
JW		 2728 }
2729}
2730
16bea517 2731/* Return the cost of a shift. */
bc45ade3 2732
3c50106f 2733static inline int
cf277499 2734shiftcosts (rtx x)
bc45ade3 2735{
3d422cb1 2736 int value;
8aa2a305 2737
fa5322fa
AO		 2738 if (TARGET_SHMEDIA)
2739 return 1;
2740
c762ab6e
R		 2741 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2742 {
2743 if (GET_MODE (x) == DImode
f3536097 2744 && CONST_INT_P (XEXP (x, 1))
c762ab6e
R		 2745 && INTVAL (XEXP (x, 1)) == 1)
2746 return 2;
2747
2748 /* Everything else is invalid, because there is no pattern for it. */
cb2eb96f 2749 return MAX_COST;
c762ab6e 2750 }
16bea517 2751 /* If shift by a non constant, then this will be expensive. */
f3536097 2752 if (!CONST_INT_P (XEXP (x, 1)))
1245df60 2753 return SH_DYNAMIC_SHIFT_COST;
bc45ade3 2754
6c34a092
PB		 2755 /* Otherwise, return the true cost in instructions. Cope with out of range
2756 shift counts more or less arbitrarily. */
2757 value = INTVAL (XEXP (x, 1)) & 31;
3d422cb1 2758
8aa2a305 2759 if (GET_CODE (x) == ASHIFTRT)
49b6d06b
JW		 2760 {
2761 int cost = ashiftrt_insns[value];
2762 /* If SH3, then we put the constant in a reg and use shad. */
1245df60
R		 2763 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2764 cost = 1 + SH_DYNAMIC_SHIFT_COST;
49b6d06b
JW		 2765 return cost;
2766 }
8aa2a305
JW		 2767 else
2768 return shift_insns[value];
0d7e008e 2769}
b9654711 2770
8aa2a305
JW		 2771/* Return the cost of an AND operation. */
2772
3c50106f 2773static inline int
cf277499 2774andcosts (rtx x)
0d7e008e
SC		 2775{
2776 int i;
8aa2a305 2777
a6f71af5 2778 /* Anding with a register is a single cycle and instruction. */
f3536097 2779 if (!CONST_INT_P (XEXP (x, 1)))
a6f71af5 2780 return 1;
8aa2a305
JW		 2781
2782 i = INTVAL (XEXP (x, 1));
fa5322fa
AO		 2783
2784 if (TARGET_SHMEDIA)
2785 {
32a7ab3d
KK		 2786 if (satisfies_constraint_I10 (XEXP (x, 1))
2787 || satisfies_constraint_J16 (XEXP (x, 1)))
fa5322fa
AO		 2788 return 1;
2789 else
f40751dd 2790 return 1 + rtx_cost (XEXP (x, 1), AND, !optimize_size);
fa5322fa
AO		 2791 }
2792
a6f71af5 2793 /* These constants are single cycle extu.[bw] instructions. */
0d7e008e 2794 if (i == 0xff || i == 0xffff)
a6f71af5 2795 return 1;
735cb76e 2796 /* Constants that can be used in an and immediate instruction in a single
a6f71af5 2797 cycle, but this requires r0, so make it a little more expensive. */
735cb76e 2798 if (CONST_OK_FOR_K08 (i))
0d7e008e 2799 return 2;
a6f71af5
JW		 2800 /* Constants that can be loaded with a mov immediate and an and.
2801 This case is probably unnecessary. */
735cb76e 2802 if (CONST_OK_FOR_I08 (i))
a6f71af5
JW		 2803 return 2;
2804 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2805 This case is probably unnecessary. */
2806 return 3;
0d7e008e 2807}
d3ae8277 2808
630c79be
BS		 2809/* Return the cost of an addition or a subtraction. */
2810
3c50106f 2811static inline int
cf277499 2812addsubcosts (rtx x)
630c79be
BS		 2813{
2814 /* Adding a register is a single cycle insn. */
f3536097 2815 if (REG_P (XEXP (x, 1))
50ceefc2 2816 || GET_CODE (XEXP (x, 1)) == SUBREG)
630c79be
BS		 2817 return 1;
2818
2819 /* Likewise for small constants. */
f3536097 2820 if (CONST_INT_P (XEXP (x, 1))
fa5322fa 2821 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
630c79be
BS		 2822 return 1;
2823
fa5322fa
AO		 2824 if (TARGET_SHMEDIA)
2825 switch (GET_CODE (XEXP (x, 1)))
2826 {
2827 case CONST:
2828 case LABEL_REF:
2829 case SYMBOL_REF:
2830 return TARGET_SHMEDIA64 ? 5 : 3;
2831
2832 case CONST_INT:
735cb76e 2833 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
fa5322fa 2834 return 2;
735cb76e 2835 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
fa5322fa 2836 return 3;
735cb76e 2837 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
fa5322fa
AO		 2838 return 4;
2839
2840 /* Fall through. */
2841 default:
832a3292 2842 return 5;
fa5322fa
AO		 2843 }
2844
630c79be
BS		 2845 /* Any other constant requires a 2 cycle pc-relative load plus an
2846 addition. */
2847 return 3;
2848}
2849
16bea517 2850/* Return the cost of a multiply. */
3c50106f 2851static inline int
cf277499 2852multcosts (rtx x ATTRIBUTE_UNUSED)
0d7e008e 2853{
7dd2f19b
RS		 2854 if (sh_multcost >= 0)
2855 return sh_multcost;
fa5322fa 2856 if (TARGET_SHMEDIA)
73a4d10b
R		 2857 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2858 accept constants. Ideally, we would use a cost of one or two and
2859 add the cost of the operand, but disregard the latter when inside loops
2860 and loop invariant code motion is still to follow.
2861 Using a multiply first and splitting it later if it's a loss
2862 doesn't work because of different sign / zero extension semantics
2863 of multiplies vs. shifts. */
2864 return TARGET_SMALLCODE ? 2 : 3;
fa5322fa 2865
0d7e008e 2866 if (TARGET_SH2)
d3ae8277
SC		 2867 {
2868 /* We have a mul insn, so we can never take more than the mul and the
a7771f78 2869 read of the mac reg, but count more because of the latency and extra
16bea517 2870 reg usage. */
d3ae8277 2871 if (TARGET_SMALLCODE)
8e87e161 2872 return 2;
a7771f78 2873 return 3;
d3ae8277
SC		 2874 }
2875
a7771f78 2876 /* If we're aiming at small code, then just count the number of
16bea517 2877 insns in a multiply call sequence. */
8e87e161 2878 if (TARGET_SMALLCODE)
8aa2a305 2879 return 5;
d3ae8277 2880
16bea517 2881 /* Otherwise count all the insns in the routine we'd be calling too. */
d3ae8277 2882 return 20;
0d7e008e 2883}
b9654711 2884
3c50106f
RH		 2885/* Compute a (partial) cost for rtx X. Return true if the complete
2886 cost has been computed, and false if subexpressions should be
2887 scanned. In either case, *TOTAL contains the cost result. */
2888
2889static bool
f40751dd
JH		 2890sh_rtx_costs (rtx x, int code, int outer_code, int *total,
2891 bool speed ATTRIBUTE_UNUSED)
3c50106f
RH		 2892{
2893 switch (code)
2894 {
2895 case CONST_INT:
2896 if (TARGET_SHMEDIA)
2897 {
2898 if (INTVAL (x) == 0)
2899 *total = 0;
2900 else if (outer_code == AND && and_operand ((x), DImode))
2901 *total = 0;
2902 else if ((outer_code == IOR || outer_code == XOR
2903 || outer_code == PLUS)
735cb76e 2904 && CONST_OK_FOR_I10 (INTVAL (x)))
3c50106f 2905 *total = 0;
735cb76e 2906 else if (CONST_OK_FOR_I16 (INTVAL (x)))
3c50106f 2907 *total = COSTS_N_INSNS (outer_code != SET);
735cb76e 2908 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
73a4d10b 2909 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
735cb76e 2910 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
42201282 2911 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
3c50106f 2912 else
42201282 2913 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
3c50106f
RH		 2914 return true;
2915 }
735cb76e 2916 if (CONST_OK_FOR_I08 (INTVAL (x)))
3c50106f
RH		 2917 *total = 0;
2918 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
735cb76e 2919 && CONST_OK_FOR_K08 (INTVAL (x)))
3c50106f 2920 *total = 1;
78d310c2 2921 /* prepare_cmp_insn will force costly constants int registers before
35912544 2922 the cbranch[sd]i4 patterns can see them, so preserve potentially
78d310c2
R		 2923 interesting ones not covered by I08 above. */
2924 else if (outer_code == COMPARE
2925 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2926 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2927 || INTVAL (x) == 0x7fffffff
2928 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2929 *total = 1;
3c50106f
RH		 2930 else
2931 *total = 8;
2932 return true;
2933
2934 case CONST:
2935 case LABEL_REF:
2936 case SYMBOL_REF:
2937 if (TARGET_SHMEDIA64)
2938 *total = COSTS_N_INSNS (4);
2939 else if (TARGET_SHMEDIA32)
2940 *total = COSTS_N_INSNS (2);
2941 else
2942 *total = 5;
2943 return true;
2944
2945 case CONST_DOUBLE:
2946 if (TARGET_SHMEDIA)
2947 *total = COSTS_N_INSNS (4);
78d310c2 2948 /* prepare_cmp_insn will force costly constants int registers before
35912544 2949 the cbranchdi4 pattern can see them, so preserve potentially
78d310c2
R		 2950 interesting ones. */
2951 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
2952 *total = 1;
3c50106f
RH		 2953 else
2954 *total = 10;
2955 return true;
73a4d10b
R		 2956 case CONST_VECTOR:
2957 if (x == CONST0_RTX (GET_MODE (x)))
2958 *total = 0;
2959 else if (sh_1el_vec (x, VOIDmode))
2960 *total = outer_code != SET;
2961 if (sh_rep_vec (x, VOIDmode))
2962 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2963 + (outer_code != SET));
2964 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2965 return true;
3c50106f
RH		 2966
2967 case PLUS:
73a4d10b 2968 case MINUS:
3c50106f
RH		 2969 *total = COSTS_N_INSNS (addsubcosts (x));
2970 return true;
2971
2972 case AND:
2973 *total = COSTS_N_INSNS (andcosts (x));
2974 return true;
2975
2976 case MULT:
2977 *total = COSTS_N_INSNS (multcosts (x));
2978 return true;
2979
2980 case ASHIFT:
2981 case ASHIFTRT:
2982 case LSHIFTRT:
2983 *total = COSTS_N_INSNS (shiftcosts (x));
2984 return true;
2985
2986 case DIV:
2987 case UDIV:
2988 case MOD:
2989 case UMOD:
2990 *total = COSTS_N_INSNS (20);
2991 return true;
2992
73a4d10b
R		 2993 case PARALLEL:
2994 if (sh_1el_vec (x, VOIDmode))
2995 *total = outer_code != SET;
2996 if (sh_rep_vec (x, VOIDmode))
2997 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2998 + (outer_code != SET));
2999 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3000 return true;
3001
3c50106f
RH		 3002 case FLOAT:
3003 case FIX:
3004 *total = 100;
3005 return true;
3006
3007 default:
3008 return false;
3009 }
3010}
3011
dcefdf67
RH		 3012/* Compute the cost of an address. For the SH, all valid addresses are
3013 the same cost. Use a slightly higher cost for reg + reg addressing,
3014 since it increases pressure on r0. */
3015
3016static int
f40751dd
JH		 3017sh_address_cost (rtx X,
3018 bool speed ATTRIBUTE_UNUSED)
dcefdf67
RH		 3019{
3020 return (GET_CODE (X) == PLUS
3021 && ! CONSTANT_P (XEXP (X, 1))
3022 && ! TARGET_SHMEDIA ? 1 : 0);
3023}
3c50106f 3024
16bea517 3025/* Code to expand a shift. */
b9654711 3026
0d7e008e 3027void
cf277499 3028gen_ashift (int type, int n, rtx reg)
0d7e008e 3029{
16bea517
JW		 3030 /* Negative values here come from the shift_amounts array. */
3031 if (n < 0)
3032 {
3033 if (type == ASHIFT)
3034 type = LSHIFTRT;
3035 else
3036 type = ASHIFT;
3037 n = -n;
3038 }
3039
0d7e008e 3040 switch (type)
bc45ade3 3041 {
0d7e008e
SC		 3042 case ASHIFTRT:
3043 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
3044 break;
3045 case LSHIFTRT:
16bea517
JW		 3046 if (n == 1)
3047 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
3048 else
3049 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
0d7e008e
SC		 3050 break;
3051 case ASHIFT:
7e2fda6e 3052 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
0d7e008e 3053 break;
bc45ade3 3054 }
bc45ade3 3055}
bc45ade3 3056
8d481241
JW		 3057/* Same for HImode */
3058
3059void
cf277499 3060gen_ashift_hi (int type, int n, rtx reg)
8d481241
JW		 3061{
3062 /* Negative values here come from the shift_amounts array. */
3063 if (n < 0)
3064 {
3065 if (type == ASHIFT)
3066 type = LSHIFTRT;
3067 else
3068 type = ASHIFT;
3069 n = -n;
3070 }
3071
3072 switch (type)
3073 {
3074 case ASHIFTRT:
8d481241 3075 case LSHIFTRT:
d0c42859
R		 3076 /* We don't have HImode right shift operations because using the
3077 ordinary 32 bit shift instructions for that doesn't generate proper
3078 zero/sign extension.
3079 gen_ashift_hi is only called in contexts where we know that the
3080 sign extension works out correctly. */
97d6fd65 3081 {
ddef6bc7 3082 int offset = 0;
97d6fd65
R		 3083 if (GET_CODE (reg) == SUBREG)
3084 {
ddef6bc7 3085 offset = SUBREG_BYTE (reg);
97d6fd65
R		 3086 reg = SUBREG_REG (reg);
3087 }
ddef6bc7 3088 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
97d6fd65
R		 3089 break;
3090 }
8d481241
JW		 3091 case ASHIFT:
3092 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
3093 break;
3094 }
3095}
3096
8aa2a305
JW		 3097/* Output RTL to split a constant shift into its component SH constant
3098 shift instructions. */
f676971a 3099
318881c0 3100void
cf277499 3101gen_shifty_op (int code, rtx *operands)
bc45ade3 3102{
16bea517 3103 int value = INTVAL (operands[2]);
8aa2a305 3104 int max, i;
00f8ff66 3105
cff3d762 3106 /* Truncate the shift count in case it is out of bounds. */
6c34a092 3107 value = value & 31;
f676971a 3108
8aa2a305 3109 if (value == 31)
16bea517 3110 {
8aa2a305 3111 if (code == LSHIFTRT)
0d7e008e 3112 {
8aa2a305
JW		 3113 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3114 emit_insn (gen_movt (operands[0]));
3115 return;
16bea517 3116 }
8aa2a305 3117 else if (code == ASHIFT)
16bea517 3118 {
8aa2a305
JW		 3119 /* There is a two instruction sequence for 31 bit left shifts,
3120 but it requires r0. */
f3536097 3121 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
0d7e008e 3122 {
8aa2a305
JW		 3123 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
3124 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3125 return;
0d7e008e 3126 }
16bea517 3127 }
8aa2a305 3128 }
c17f53a8
JW		 3129 else if (value == 0)
3130 {
73a4d10b
R		 3131 /* This can happen even when optimizing, if there were subregs before
3132 reload. Don't output a nop here, as this is never optimized away;
3133 use a no-op move instead. */
3134 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
c17f53a8
JW		 3135 return;
3136 }
a9f71ad8 3137
8aa2a305
JW		 3138 max = shift_insns[value];
3139 for (i = 0; i < max; i++)
3140 gen_ashift (code, shift_amounts[value][i], operands[0]);
3141}
f676971a 3142
8d481241
JW		 3143/* Same as above, but optimized for values where the topmost bits don't
3144 matter. */
3145
318881c0 3146void
cf277499 3147gen_shifty_hi_op (int code, rtx *operands)
8d481241
JW		 3148{
3149 int value = INTVAL (operands[2]);
3150 int max, i;
cf277499 3151 void (*gen_fun) (int, int, rtx);
8d481241
JW		 3152
3153 /* This operation is used by and_shl for SImode values with a few
3154 high bits known to be cleared. */
3155 value &= 31;
3156 if (value == 0)
3157 {
3158 emit_insn (gen_nop ());
3159 return;
3160 }
3161
3162 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
3163 if (code == ASHIFT)
3164 {
3165 max = ext_shift_insns[value];
3166 for (i = 0; i < max; i++)
3167 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3168 }
3169 else
3170 /* When shifting right, emit the shifts in reverse order, so that
3171 solitary negative values come first. */
3172 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
3173 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3174}
8aa2a305
JW		 3175
3176/* Output RTL for an arithmetic right shift. */
3177
3178/* ??? Rewrite to use super-optimizer sequences. */
3179
3180int
cf277499 3181expand_ashiftrt (rtx *operands)
8aa2a305
JW		 3182{
3183 rtx wrk;
3184 char func[18];
8aa2a305
JW		 3185 int value;
3186
49b6d06b 3187 if (TARGET_SH3)
20b04867 3188 {
f3536097 3189 if (!CONST_INT_P (operands[2]))
49b6d06b
JW		 3190 {
3191 rtx count = copy_to_mode_reg (SImode, operands[2]);
3192 emit_insn (gen_negsi2 (count, count));
3193 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3194 return 1;
3195 }
1245df60
R		 3196 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
3197 > 1 + SH_DYNAMIC_SHIFT_COST)
49b6d06b 3198 {
1245df60
R		 3199 rtx count
3200 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
49b6d06b
JW		 3201 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3202 return 1;
3203 }
20b04867 3204 }
f3536097 3205 if (!CONST_INT_P (operands[2]))
8aa2a305
JW		 3206 return 0;
3207
1245df60 3208 value = INTVAL (operands[2]) & 31;
8aa2a305
JW		 3209
3210 if (value == 31)
3211 {
73a4d10b
R		 3212 /* If we are called from abs expansion, arrange things so that we
3213 we can use a single MT instruction that doesn't clobber the source,
3214 if LICM can hoist out the load of the constant zero. */
3215 if (currently_expanding_to_rtl)
3216 {
3217 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
3218 operands[1]));
3219 emit_insn (gen_mov_neg_si_t (operands[0]));
3220 return 1;
3221 }
8aa2a305
JW		 3222 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
3223 return 1;
3224 }
3225 else if (value >= 16 && value <= 19)
3226 {
3227 wrk = gen_reg_rtx (SImode);
3228 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
3229 value -= 16;
3230 while (value--)
3231 gen_ashift (ASHIFTRT, 1, wrk);
3232 emit_move_insn (operands[0], wrk);
3233 return 1;
a9f71ad8 3234 }
8aa2a305
JW		 3235 /* Expand a short sequence inline, longer call a magic routine. */
3236 else if (value <= 5)
3237 {
3238 wrk = gen_reg_rtx (SImode);
3239 emit_move_insn (wrk, operands[1]);
3240 while (value--)
3241 gen_ashift (ASHIFTRT, 1, wrk);
3242 emit_move_insn (operands[0], wrk);
3243 return 1;
3244 }
3245
3246 wrk = gen_reg_rtx (Pmode);
3247
3248 /* Load the value into an arg reg and call a helper. */
c5c76735 3249 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
8aa2a305 3250 sprintf (func, "__ashiftrt_r4_%d", value);
73a4d10b 3251 function_symbol (wrk, func, SFUNC_STATIC);
8aa2a305 3252 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
c5c76735 3253 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
8aa2a305 3254 return 1;
bc45ade3 3255}
8d481241 3256
318881c0 3257int
cf277499 3258sh_dynamicalize_shift_p (rtx count)
1245df60 3259{
6c34a092 3260 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
1245df60
R		 3261}
3262
8d481241
JW		 3263/* Try to find a good way to implement the combiner pattern
3264 [(set (match_operand:SI 0 "register_operand" "r")
3265 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3266 (match_operand:SI 2 "const_int_operand" "n"))
3267 (match_operand:SI 3 "const_int_operand" "n"))) .
3268 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3269 return 0 for simple right / left or left/right shift combination.
3270 return 1 for a combination of shifts with zero_extend.
3271 return 2 for a combination of shifts with an AND that needs r0.
3272 return 3 for a combination of shifts with an AND that needs an extra
3273 scratch register, when the three highmost bits of the AND mask are clear.
3274 return 4 for a combination of shifts with an AND that needs an extra
3275 scratch register, when any of the three highmost bits of the AND mask
3276 is set.
3277 If ATTRP is set, store an initial right shift width in ATTRP[0],
3278 and the instruction length in ATTRP[1] . These values are not valid
3279 when returning 0.
3280 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3281 shift_amounts for the last shift value that is to be used before the
3282 sign extend. */
3283int
cf277499 3284shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
8d481241
JW		 3285{
3286 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
3287 int left = INTVAL (left_rtx), right;
3288 int best = 0;
3289 int cost, best_cost = 10000;
3290 int best_right = 0, best_len = 0;
3291 int i;
3292 int can_ext;
3293
3294 if (left < 0 || left > 31)
3295 return 0;
f3536097 3296 if (CONST_INT_P (mask_rtx))
8d481241
JW		 3297 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3298 else
3299 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
832a3292 3300 /* Can this be expressed as a right shift / left shift pair? */
8d481241
JW		 3301 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3302 right = exact_log2 (lsb);
3303 mask2 = ~(mask + lsb - 1);
3304 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3305 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3306 if (! mask2)
3307 best_cost = shift_insns[right] + shift_insns[right + left];
3308 /* mask has no trailing zeroes <==> ! right */
3309 else if (! right && mask2 == ~(lsb2 - 1))
3310 {
3311 int late_right = exact_log2 (lsb2);
3312 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
3313 }
832a3292 3314 /* Try to use zero extend. */
8d481241
JW		 3315 if (mask2 == ~(lsb2 - 1))
3316 {
3317 int width, first;
3318
3319 for (width = 8; width <= 16; width += 8)
3320 {
832a3292
KH		 3321 /* Can we zero-extend right away? */
3322 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
8d481241
JW		 3323 {
3324 cost
3325 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
3326 if (cost < best_cost)
3327 {
3328 best = 1;
3329 best_cost = cost;
3330 best_right = right;
3331 best_len = cost;
3332 if (attrp)
3333 attrp[2] = -1;
3334 }
3335 continue;
3336 }
3337 /* ??? Could try to put zero extend into initial right shift,
6f317ef3 3338 or even shift a bit left before the right shift. */
8d481241
JW		 3339 /* Determine value of first part of left shift, to get to the
3340 zero extend cut-off point. */
3341 first = width - exact_log2 (lsb2) + right;
3342 if (first >= 0 && right + left - first >= 0)
3343 {
3344 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
3345 + ext_shift_insns[right + left - first];
3346 if (cost < best_cost)
3347 {
3348 best = 1;
3349 best_cost = cost;
3350 best_right = right;
3351 best_len = cost;
3352 if (attrp)
3353 attrp[2] = first;
832a3292 3354 }
8d481241
JW		 3355 }
3356 }
3357 }
3358 /* Try to use r0 AND pattern */
3359 for (i = 0; i <= 2; i++)
3360 {
3361 if (i > right)
3362 break;
735cb76e 3363 if (! CONST_OK_FOR_K08 (mask >> i))
8d481241
JW		 3364 continue;
3365 cost = (i != 0) + 2 + ext_shift_insns[left + i];
3366 if (cost < best_cost)
3367 {
3368 best = 2;
3369 best_cost = cost;
3370 best_right = i;
3371 best_len = cost - 1;
3372 }
3373 }
3374 /* Try to use a scratch register to hold the AND operand. */
832a3292 3375 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
8d481241
JW		 3376 for (i = 0; i <= 2; i++)
3377 {
3378 if (i > right)
3379 break;
735cb76e 3380 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
6ab911bb 3381 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
8d481241
JW		 3382 if (cost < best_cost)
3383 {
3384 best = 4 - can_ext;
3385 best_cost = cost;
3386 best_right = i;
735cb76e 3387 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
8d481241
JW		 3388 }
3389 }
3390
3391 if (attrp)
3392 {
3393 attrp[0] = best_right;
3394 attrp[1] = best_len;
3395 }
3396 return best;
3397}
3398
3399/* This is used in length attributes of the unnamed instructions
3400 corresponding to shl_and_kind return values of 1 and 2. */
3401int
cf277499 3402shl_and_length (rtx insn)
8d481241
JW		 3403{
3404 rtx set_src, left_rtx, mask_rtx;
3405 int attributes[3];
3406
3407 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3408 left_rtx = XEXP (XEXP (set_src, 0), 1);
3409 mask_rtx = XEXP (set_src, 1);
3410 shl_and_kind (left_rtx, mask_rtx, attributes);
3411 return attributes[1];
3412}
3413
3414/* This is used in length attribute of the and_shl_scratch instruction. */
3415
3416int
cf277499 3417shl_and_scr_length (rtx insn)
8d481241
JW		 3418{
3419 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
6c34a092 3420 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
8d481241 3421 rtx op = XEXP (set_src, 0);
6c34a092 3422 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
8d481241 3423 op = XEXP (XEXP (op, 0), 0);
6c34a092 3424 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
8d481241
JW		 3425}
3426
8d481241
JW		 3427/* Generate rtl for instructions for which shl_and_kind advised a particular
3428 method of generating them, i.e. returned zero. */
3429
3430int
cf277499 3431gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
8d481241
JW		 3432{
3433 int attributes[3];
3434 unsigned HOST_WIDE_INT mask;
3435 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3436 int right, total_shift;
832a3292 3437 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
8d481241
JW		 3438
3439 right = attributes[0];
3440 total_shift = INTVAL (left_rtx) + right;
3441 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3442 switch (kind)
3443 {
3444 default:
3445 return -1;
3446 case 1:
3447 {
3448 int first = attributes[2];
3449 rtx operands[3];
3450
3451 if (first < 0)
3452 {
7174c937 3453 emit_insn ((mask << right) <= 0xff
832a3292
KH		 3454 ? gen_zero_extendqisi2 (dest,
3455 gen_lowpart (QImode, source))
3456 : gen_zero_extendhisi2 (dest,
3457 gen_lowpart (HImode, source)));
8d481241
JW		 3458 source = dest;
3459 }
3460 if (source != dest)
3461 emit_insn (gen_movsi (dest, source));
3462 operands[0] = dest;
3463 if (right)
3464 {
3465 operands[2] = GEN_INT (right);
3466 gen_shifty_hi_op (LSHIFTRT, operands);
3467 }
3468 if (first > 0)
3469 {
3470 operands[2] = GEN_INT (first);
3471 gen_shifty_hi_op (ASHIFT, operands);
3472 total_shift -= first;
3473 mask <<= first;
3474 }
3475 if (first >= 0)
85af47b9 3476 emit_insn (mask <= 0xff
832a3292
KH		 3477 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3478 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
8d481241
JW		 3479 if (total_shift > 0)
3480 {
3481 operands[2] = GEN_INT (total_shift);
3482 gen_shifty_hi_op (ASHIFT, operands);
3483 }
3484 break;
3485 }
3486 case 4:
3487 shift_gen_fun = gen_shifty_op;
8d481241 3488 case 3:
24c50999
JR		 3489 /* If the topmost bit that matters is set, set the topmost bits
3490 that don't matter. This way, we might be able to get a shorter
3491 signed constant. */
832a3292
KH		 3492 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3493 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
61fb6bac 3494 case 2:
8d481241
JW		 3495 /* Don't expand fine-grained when combining, because that will
3496 make the pattern fail. */
4586b4ca 3497 if (currently_expanding_to_rtl
8d481241
JW		 3498 || reload_in_progress || reload_completed)
3499 {
3500 rtx operands[3];
f676971a 3501
61fb6bac
R		 3502 /* Cases 3 and 4 should be handled by this split
3503 only while combining */
f5b9e7c9 3504 gcc_assert (kind <= 2);
8d481241
JW		 3505 if (right)
3506 {
3507 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3508 source = dest;
3509 }
3510 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
afad3d2c
JW		 3511 if (total_shift)
3512 {
3513 operands[0] = dest;
3514 operands[1] = dest;
3515 operands[2] = GEN_INT (total_shift);
3516 shift_gen_fun (ASHIFT, operands);
3517 }
8d481241
JW		 3518 break;
3519 }
3520 else
3521 {
3522 int neg = 0;
3523 if (kind != 4 && total_shift < 16)
3524 {
3525 neg = -ext_shift_amounts[total_shift][1];
3526 if (neg > 0)
3527 neg -= ext_shift_amounts[total_shift][2];
3528 else
3529 neg = 0;
3530 }
3531 emit_insn (gen_and_shl_scratch (dest, source,
3532 GEN_INT (right),
3533 GEN_INT (mask),
3534 GEN_INT (total_shift + neg),
3535 GEN_INT (neg)));
3536 emit_insn (gen_movsi (dest, dest));
3537 break;
3538 }
3539 }
3540 return 0;
3541}
3542
3543/* Try to find a good way to implement the combiner pattern
3544 [(set (match_operand:SI 0 "register_operand" "=r")
3545 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3546 (match_operand:SI 2 "const_int_operand" "n")
3547 (match_operand:SI 3 "const_int_operand" "n")
3548 (const_int 0)))
4773afa4 3549 (clobber (reg:SI T_REG))]
8d481241
JW		 3550 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3551 return 0 for simple left / right shift combination.
3552 return 1 for left shift / 8 bit sign extend / left shift.
3553 return 2 for left shift / 16 bit sign extend / left shift.
3554 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3555 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3556 return 5 for left shift / 16 bit sign extend / right shift
3557 return 6 for < 8 bit sign extend / left shift.
3558 return 7 for < 8 bit sign extend / left shift / single right shift.
3559 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3560
3561int
cf277499 3562shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
8d481241
JW		 3563{
3564 int left, size, insize, ext;
3a8699c7 3565 int cost = 0, best_cost;
8d481241
JW		 3566 int kind;
3567
3568 left = INTVAL (left_rtx);
3569 size = INTVAL (size_rtx);
3570 insize = size - left;
f5b9e7c9 3571 gcc_assert (insize > 0);
8d481241
JW		 3572 /* Default to left / right shift. */
3573 kind = 0;
3574 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3575 if (size <= 16)
3576 {
3577 /* 16 bit shift / sign extend / 16 bit shift */
3578 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
afad3d2c
JW		 3579 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3580 below, by alternative 3 or something even better. */
8d481241
JW		 3581 if (cost < best_cost)
3582 {
3583 kind = 5;
3584 best_cost = cost;
3585 }
3586 }
3587 /* Try a plain sign extend between two shifts. */
3588 for (ext = 16; ext >= insize; ext -= 8)
3589 {
3590 if (ext <= size)
3591 {
3592 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3593 if (cost < best_cost)
3594 {
11f9ed1a 3595 kind = ext / (unsigned) 8;
8d481241
JW		 3596 best_cost = cost;
3597 }
3598 }
ae9d19c0
JR		 3599 /* Check if we can do a sloppy shift with a final signed shift
3600 restoring the sign. */
3601 if (EXT_SHIFT_SIGNED (size - ext))
3602 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3603 /* If not, maybe it's still cheaper to do the second shift sloppy,
3604 and do a final sign extend? */
3605 else if (size <= 16)
3606 cost = ext_shift_insns[ext - insize] + 1
3607 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3608 else
3609 continue;
3610 if (cost < best_cost)
8d481241 3611 {
11f9ed1a 3612 kind = ext / (unsigned) 8 + 2;
ae9d19c0 3613 best_cost = cost;
8d481241
JW		 3614 }
3615 }
3616 /* Check if we can sign extend in r0 */
3617 if (insize < 8)
3618 {
3619 cost = 3 + shift_insns[left];
3620 if (cost < best_cost)
3621 {
3622 kind = 6;
3623 best_cost = cost;
3624 }
3625 /* Try the same with a final signed shift. */
3626 if (left < 31)
3627 {
3628 cost = 3 + ext_shift_insns[left + 1] + 1;
3629 if (cost < best_cost)
3630 {
3631 kind = 7;
3632 best_cost = cost;
3633 }
3634 }
3635 }
3636 if (TARGET_SH3)
3637 {
3638 /* Try to use a dynamic shift. */
1245df60 3639 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
8d481241
JW		 3640 if (cost < best_cost)
3641 {
3642 kind = 0;
3643 best_cost = cost;
3644 }
3645 }
3646 if (costp)
3647 *costp = cost;
3648 return kind;
3649}
3650
3651/* Function to be used in the length attribute of the instructions
3652 implementing this pattern. */
3653
3654int
cf277499 3655shl_sext_length (rtx insn)
8d481241
JW		 3656{
3657 rtx set_src, left_rtx, size_rtx;
3658 int cost;
3659
3660 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3661 left_rtx = XEXP (XEXP (set_src, 0), 1);
3662 size_rtx = XEXP (set_src, 1);
3663 shl_sext_kind (left_rtx, size_rtx, &cost);
3664 return cost;
3665}
3666
3667/* Generate rtl for this pattern */
3668
3669int
cf277499 3670gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
8d481241
JW		 3671{
3672 int kind;
d00d338c 3673 int left, size, insize, cost;
8d481241
JW		 3674 rtx operands[3];
3675
d00d338c 3676 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
8d481241
JW		 3677 left = INTVAL (left_rtx);
3678 size = INTVAL (size_rtx);
3679 insize = size - left;
3680 switch (kind)
3681 {
3682 case 1:
3683 case 2:
3684 case 3:
3685 case 4:
3686 {
3687 int ext = kind & 1 ? 8 : 16;
3688 int shift2 = size - ext;
3689
3690 /* Don't expand fine-grained when combining, because that will
3691 make the pattern fail. */
4586b4ca 3692 if (! currently_expanding_to_rtl
8d481241
JW		 3693 && ! reload_in_progress && ! reload_completed)
3694 {
3695 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3696 emit_insn (gen_movsi (dest, source));
3697 break;
3698 }
3699 if (dest != source)
3700 emit_insn (gen_movsi (dest, source));
3701 operands[0] = dest;
afad3d2c
JW		 3702 if (ext - insize)
3703 {
3704 operands[2] = GEN_INT (ext - insize);
3705 gen_shifty_hi_op (ASHIFT, operands);
3706 }
8d481241 3707 emit_insn (kind & 1
832a3292
KH		 3708 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3709 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
8d481241
JW		 3710 if (kind <= 2)
3711 {
afad3d2c
JW		 3712 if (shift2)
3713 {
3714 operands[2] = GEN_INT (shift2);
3715 gen_shifty_op (ASHIFT, operands);
3716 }
8d481241
JW		 3717 }
3718 else
3719 {
afad3d2c 3720 if (shift2 > 0)
8d481241 3721 {
ae9d19c0
JR		 3722 if (EXT_SHIFT_SIGNED (shift2))
3723 {
3724 operands[2] = GEN_INT (shift2 + 1);
3725 gen_shifty_op (ASHIFT, operands);
a556fd39 3726 operands[2] = const1_rtx;
ae9d19c0
JR		 3727 gen_shifty_op (ASHIFTRT, operands);
3728 break;
3729 }
8d481241
JW		 3730 operands[2] = GEN_INT (shift2);
3731 gen_shifty_hi_op (ASHIFT, operands);
3732 }
afad3d2c 3733 else if (shift2)
8d481241
JW		 3734 {
3735 operands[2] = GEN_INT (-shift2);
3736 gen_shifty_hi_op (LSHIFTRT, operands);
3737 }
3738 emit_insn (size <= 8
afad3d2c
JW		 3739 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3740 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
8d481241
JW		 3741 }
3742 break;
3743 }
3744 case 5:
afad3d2c
JW		 3745 {
3746 int i = 16 - size;
4586b4ca 3747 if (! currently_expanding_to_rtl
913d8e13
R		 3748 && ! reload_in_progress && ! reload_completed)
3749 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3750 else
3751 {
3752 operands[0] = dest;
3753 operands[2] = GEN_INT (16 - insize);
3754 gen_shifty_hi_op (ASHIFT, operands);
3755 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3756 }
afad3d2c
JW		 3757 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3758 while (--i >= 0)
3759 gen_ashift (ASHIFTRT, 1, dest);
3760 break;
3761 }
8d481241
JW		 3762 case 6:
3763 case 7:
3764 /* Don't expand fine-grained when combining, because that will
3765 make the pattern fail. */
4586b4ca 3766 if (! currently_expanding_to_rtl
8d481241
JW		 3767 && ! reload_in_progress && ! reload_completed)
3768 {
3769 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3770 emit_insn (gen_movsi (dest, source));
3771 break;
3772 }
3773 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3774 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3775 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3776 operands[0] = dest;
3777 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3778 gen_shifty_op (ASHIFT, operands);
3779 if (kind == 7)
a556fd39 3780 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
8d481241
JW		 3781 break;
3782 default:
3783 return -1;
3784 }
3785 return 0;
3786}
fa5322fa
AO		 3787
3788/* Prefix a symbol_ref name with "datalabel". */
3789
3790rtx
cf277499 3791gen_datalabel_ref (rtx sym)
fa5322fa 3792{
73a4d10b
R		 3793 const char *str;
3794
fa5322fa
AO		 3795 if (GET_CODE (sym) == LABEL_REF)
3796 return gen_rtx_CONST (GET_MODE (sym),
3797 gen_rtx_UNSPEC (GET_MODE (sym),
3798 gen_rtvec (1, sym),
3799 UNSPEC_DATALABEL));
f676971a 3800
f5b9e7c9 3801 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
fa5322fa 3802
73a4d10b
R		 3803 str = XSTR (sym, 0);
3804 /* Share all SYMBOL_REF strings with the same value - that is important
3805 for cse. */
3806 str = IDENTIFIER_POINTER (get_identifier (str));
3807 XSTR (sym, 0) = str;
3808
fa5322fa
AO		 3809 return sym;
3810}
3811
8aa2a305 3812\f
6dd3c0a5
SB		 3813static alloc_pool label_ref_list_pool;
3814
3815typedef struct label_ref_list_d
3816{
3817 rtx label;
3818 struct label_ref_list_d *next;
3819} *label_ref_list_t;
3820
8aa2a305
JW		 3821/* The SH cannot load a large constant into a register, constants have to
3822 come from a pc relative load. The reference of a pc relative load
0fa2e4df 3823 instruction must be less than 1k in front of the instruction. This
8aa2a305
JW		 3824 means that we often have to dump a constant inside a function, and
3825 generate code to branch around it.
bc45ade3 3826
8aa2a305
JW		 3827 It is important to minimize this, since the branches will slow things
3828 down and make things bigger.
3829
3830 Worst case code looks like:
3831
3832 mov.l L1,rn
3833 bra L2
3834 nop
3835 align
3836 L1: .long value
3837 L2:
3838 ..
3839
3840 mov.l L3,rn
3841 bra L4
3842 nop
3843 align
3844 L3: .long value
3845 L4:
3846 ..
3847
3848 We fix this by performing a scan before scheduling, which notices which
3849 instructions need to have their operands fetched from the constant table
3850 and builds the table.
3851
3852 The algorithm is:
3853
3854 scan, find an instruction which needs a pcrel move. Look forward, find the
3855 last barrier which is within MAX_COUNT bytes of the requirement.
3856 If there isn't one, make one. Process all the instructions between
3857 the find and the barrier.
3858
3859 In the above example, we can tell that L3 is within 1k of L1, so
3860 the first move can be shrunk from the 3 insn+constant sequence into
3861 just 1 insn, and the constant moved to L3 to make:
3862
3863 mov.l L1,rn
3864 ..
3865 mov.l L3,rn
3866 bra L4
3867 nop
3868 align
3869 L3:.long value
3870 L4:.long value
3871
3872 Then the second move becomes the target for the shortening process. */
3873
3874typedef struct
3875{
3876 rtx value; /* Value in table. */
3877 rtx label; /* Label of value. */
6dd3c0a5 3878 label_ref_list_t wend; /* End of window. */
8aa2a305 3879 enum machine_mode mode; /* Mode of value. */
3503150c
RS		 3880
3881 /* True if this constant is accessed as part of a post-increment
3882 sequence. Note that HImode constants are never accessed in this way. */
3883 bool part_of_sequence_p;
8aa2a305
JW		 3884} pool_node;
3885
3886/* The maximum number of constants that can fit into one pool, since
73a4d10b
R		 3887 constants in the range 0..510 are at least 2 bytes long, and in the
3888 range from there to 1018 at least 4 bytes. */
8aa2a305 3889
73a4d10b 3890#define MAX_POOL_SIZE 372
8aa2a305
JW		 3891static pool_node pool_vector[MAX_POOL_SIZE];
3892static int pool_size;
b91455de
KK		 3893static rtx pool_window_label;
3894static int pool_window_last;
8aa2a305 3895
4241ecb0
R		 3896static int max_labelno_before_reorg;
3897
8aa2a305
JW		 3898/* ??? If we need a constant in HImode which is the truncated value of a
3899 constant we need in SImode, we could combine the two entries thus saving
3900 two bytes. Is this common enough to be worth the effort of implementing
3901 it? */
3902
3903/* ??? This stuff should be done at the same time that we shorten branches.
3904 As it is now, we must assume that all branches are the maximum size, and
3905 this causes us to almost always output constant pools sooner than
3906 necessary. */
3907
3908/* Add a constant to the pool and return its label. */
3909
3910static rtx
cf277499 3911add_constant (rtx x, enum machine_mode mode, rtx last_value)
0d7e008e
SC		 3912{
3913 int i;
0a2aaacc 3914 rtx lab, new_rtx;
6dd3c0a5 3915 label_ref_list_t ref, newref;
8aa2a305
JW		 3916
3917 /* First see if we've already got it. */
3918 for (i = 0; i < pool_size; i++)
0d7e008e 3919 {
8aa2a305
JW		 3920 if (x->code == pool_vector[i].value->code
3921 && mode == pool_vector[i].mode)
0d7e008e 3922 {
8aa2a305
JW		 3923 if (x->code == CODE_LABEL)
3924 {
3925 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3926 continue;
3927 }
3928 if (rtx_equal_p (x, pool_vector[i].value))
225e4f43 3929 {
0a2aaacc 3930 lab = new_rtx = 0;
225e4f43
R		 3931 if (! last_value
3932 || ! i
3933 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3934 {
0a2aaacc
KG		 3935 new_rtx = gen_label_rtx ();
3936 LABEL_REFS (new_rtx) = pool_vector[i].label;
3937 pool_vector[i].label = lab = new_rtx;
225e4f43 3938 }
b91455de
KK		 3939 if (lab && pool_window_label)
3940 {
6dd3c0a5
SB		 3941 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3942 newref->label = pool_window_label;
b91455de 3943 ref = pool_vector[pool_window_last].wend;
6dd3c0a5 3944 newref->next = ref;
b91455de
KK		 3945 pool_vector[pool_window_last].wend = newref;
3946 }
0a2aaacc
KG		 3947 if (new_rtx)
3948 pool_window_label = new_rtx;
b91455de 3949 pool_window_last = i;
225e4f43
R		 3950 return lab;
3951 }
0d7e008e 3952 }
0d7e008e 3953 }
b9654711 3954
8aa2a305
JW		 3955 /* Need a new one. */
3956 pool_vector[pool_size].value = x;
225e4f43 3957 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3503150c
RS		 3958 {
3959 lab = 0;
3960 pool_vector[pool_size - 1].part_of_sequence_p = true;
3961 }
225e4f43
R		 3962 else
3963 lab = gen_label_rtx ();
8aa2a305
JW		 3964 pool_vector[pool_size].mode = mode;
3965 pool_vector[pool_size].label = lab;
6dd3c0a5 3966 pool_vector[pool_size].wend = NULL;
3503150c 3967 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
b91455de
KK		 3968 if (lab && pool_window_label)
3969 {
6dd3c0a5
SB		 3970 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3971 newref->label = pool_window_label;
b91455de 3972 ref = pool_vector[pool_window_last].wend;
6dd3c0a5 3973 newref->next = ref;
b91455de
KK		 3974 pool_vector[pool_window_last].wend = newref;
3975 }
3976 if (lab)
3977 pool_window_label = lab;
3978 pool_window_last = pool_size;
8aa2a305
JW		 3979 pool_size++;
3980 return lab;
0d7e008e 3981}
16bea517 3982
078c8b08
R		 3983/* Output the literal table. START, if nonzero, is the first instruction
3984 this table is needed for, and also indicates that there is at least one
3985 casesi_worker_2 instruction; We have to emit the operand3 labels from
3986 these insns at a 4-byte aligned position. BARRIER is the barrier
3987 after which we are to place the table. */
b9654711 3988
b9654711 3989static void
078c8b08 3990dump_table (rtx start, rtx barrier)
b9654711 3991{
078c8b08 3992 rtx scan = barrier;
0d7e008e 3993 int i;
0d7e008e 3994 int need_align = 1;
6dd3c0a5
SB		 3995 rtx lab;
3996 label_ref_list_t ref;
aa06e8f5 3997 int have_df = 0;
b9654711 3998
16bea517 3999 /* Do two passes, first time dump out the HI sized constants. */
b9654711 4000
0d7e008e 4001 for (i = 0; i < pool_size; i++)
b9654711 4002 {
8aa2a305
JW		 4003 pool_node *p = &pool_vector[i];
4004
0d7e008e
SC		 4005 if (p->mode == HImode)
4006 {
4007 if (need_align)
4008 {
4009 scan = emit_insn_after (gen_align_2 (), scan);
4010 need_align = 0;
4011 }
b91455de
KK		 4012 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4013 scan = emit_label_after (lab, scan);
4014 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
4015 scan);
6dd3c0a5 4016 for (ref = p->wend; ref; ref = ref->next)
b91455de 4017 {
6dd3c0a5 4018 lab = ref->label;
b91455de
KK		 4019 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4020 }
0d7e008e 4021 }
aa06e8f5
R		 4022 else if (p->mode == DFmode)
4023 have_df = 1;
b9654711 4024 }
8aa2a305 4025
0d7e008e 4026 need_align = 1;
b9654711 4027
078c8b08
R		 4028 if (start)
4029 {
4030 scan = emit_insn_after (gen_align_4 (), scan);
4031 need_align = 0;
4032 for (; start != barrier; start = NEXT_INSN (start))
f3536097 4033 if (NONJUMP_INSN_P (start)
078c8b08
R		 4034 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
4035 {
4036 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
4037 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
4038
4039 scan = emit_label_after (lab, scan);
4040 }
4041 }
aa06e8f5 4042 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
fa5322fa
AO		 4043 {
4044 rtx align_insn = NULL_RTX;
4045
4046 scan = emit_label_after (gen_label_rtx (), scan);
4047 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4048 need_align = 0;
4049
4050 for (i = 0; i < pool_size; i++)
4051 {
4052 pool_node *p = &pool_vector[i];
4053
4054 switch (p->mode)
4055 {
4056 case HImode:
4057 break;
4058 case SImode:
4059 case SFmode:
3503150c 4060 if (align_insn && !p->part_of_sequence_p)
fa5322fa
AO		 4061 {
4062 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4063 emit_label_before (lab, align_insn);
4064 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
4065 align_insn);
6dd3c0a5 4066 for (ref = p->wend; ref; ref = ref->next)
fa5322fa 4067 {
6dd3c0a5 4068 lab = ref->label;
fa5322fa 4069 emit_insn_before (gen_consttable_window_end (lab),
832a3292 4070 align_insn);
fa5322fa
AO		 4071 }
4072 delete_insn (align_insn);
4073 align_insn = NULL_RTX;
4074 continue;
4075 }
4076 else
4077 {
4078 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4079 scan = emit_label_after (lab, scan);
4080 scan = emit_insn_after (gen_consttable_4 (p->value,
4081 const0_rtx), scan);
4082 need_align = ! need_align;
4083 }
4084 break;
4085 case DFmode:
fa5322fa
AO		 4086 if (need_align)
4087 {
4088 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4089 align_insn = scan;
4090 need_align = 0;
4091 }
aa06e8f5 4092 case DImode:
fa5322fa
AO		 4093 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4094 scan = emit_label_after (lab, scan);
4095 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4096 scan);
4097 break;
4098 default:
f5b9e7c9 4099 gcc_unreachable ();
fa5322fa
AO		 4100 }
4101
4102 if (p->mode != HImode)
4103 {
6dd3c0a5 4104 for (ref = p->wend; ref; ref = ref->next)
fa5322fa 4105 {
6dd3c0a5 4106 lab = ref->label;
fa5322fa
AO		 4107 scan = emit_insn_after (gen_consttable_window_end (lab),
4108 scan);
4109 }
4110 }
4111 }
4112
4113 pool_size = 0;
4114 }
f676971a 4115
0d7e008e 4116 for (i = 0; i < pool_size; i++)
b9654711 4117 {
8aa2a305 4118 pool_node *p = &pool_vector[i];
b9654711 4119
0d7e008e 4120 switch (p->mode)
b9654711 4121 {
0d7e008e
SC		 4122 case HImode:
4123 break;
4124 case SImode:
e577c183 4125 case SFmode:
0d7e008e 4126 if (need_align)
b9654711 4127 {
0d7e008e 4128 need_align = 0;
d3ae8277 4129 scan = emit_label_after (gen_label_rtx (), scan);
0d7e008e 4130 scan = emit_insn_after (gen_align_4 (), scan);
b9654711 4131 }
b91455de
KK		 4132 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4133 scan = emit_label_after (lab, scan);
4134 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
4135 scan);
0d7e008e 4136 break;
e577c183 4137 case DFmode:
0d7e008e
SC		 4138 case DImode:
4139 if (need_align)
4140 {
4141 need_align = 0;
d3ae8277 4142 scan = emit_label_after (gen_label_rtx (), scan);
0d7e008e
SC		 4143 scan = emit_insn_after (gen_align_4 (), scan);
4144 }
b91455de
KK		 4145 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4146 scan = emit_label_after (lab, scan);
4147 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4148 scan);
0d7e008e
SC		 4149 break;
4150 default:
f5b9e7c9 4151 gcc_unreachable ();
b9654711 4152 }
b91455de
KK		 4153
4154 if (p->mode != HImode)
4155 {
6dd3c0a5 4156 for (ref = p->wend; ref; ref = ref->next)
b91455de 4157 {
6dd3c0a5 4158 lab = ref->label;
b91455de
KK		 4159 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4160 }
4161 }
b9654711 4162 }
b9654711 4163
0d7e008e
SC		 4164 scan = emit_insn_after (gen_consttable_end (), scan);
4165 scan = emit_barrier_after (scan);
4166 pool_size = 0;
b91455de
KK		 4167 pool_window_label = NULL_RTX;
4168 pool_window_last = 0;
0d7e008e 4169}
b9654711 4170
5e7a8ee0 4171/* Return nonzero if constant would be an ok source for a
8aa2a305 4172 mov.w instead of a mov.l. */
b9654711 4173
16bea517 4174static int
cf277499 4175hi_const (rtx src)
0d7e008e 4176{
f3536097 4177 return (CONST_INT_P (src)
8aa2a305
JW		 4178 && INTVAL (src) >= -32768
4179 && INTVAL (src) <= 32767);
b9654711
SC		 4180}
4181
4241ecb0
R		 4182#define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4183
5e7a8ee0 4184/* Nonzero if the insn is a move instruction which needs to be fixed. */
8aa2a305
JW		 4185
4186/* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
735cb76e
R		 4187 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4188 need to fix it if the input value is CONST_OK_FOR_I08. */
8aa2a305
JW		 4189
4190static int
cf277499 4191broken_move (rtx insn)
b9654711 4192{
f3536097 4193 if (NONJUMP_INSN_P (insn))
e577c183
JR		 4194 {
4195 rtx pat = PATTERN (insn);
4196 if (GET_CODE (pat) == PARALLEL)
4197 pat = XVECEXP (pat, 0, 0);
4198 if (GET_CODE (pat) == SET
3b962ea0 4199 /* We can load any 8-bit value if we don't care what the high
e577c183
JR		 4200 order bits end up as. */
4201 && GET_MODE (SET_DEST (pat)) != QImode
43c05634
AO		 4202 && (CONSTANT_P (SET_SRC (pat))
4203 /* Match mova_const. */
4204 || (GET_CODE (SET_SRC (pat)) == UNSPEC
4205 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
4206 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
3a8699c7 4207 && ! (TARGET_SH2E
1245df60 4208 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
e577c183
JR		 4209 && (fp_zero_operand (SET_SRC (pat))
4210 || fp_one_operand (SET_SRC (pat)))
18778292
R		 4211 /* ??? If this is a -m4 or -m4-single compilation, in general
4212 we don't know the current setting of fpscr, so disable fldi.
4213 There is an exception if this was a register-register move
4214 before reload - and hence it was ascertained that we have
4215 single precision setting - and in a post-reload optimization
4216 we changed this to do a constant load. In that case
4217 we don't have an r0 clobber, hence we must use fldi. */
4218 && (! TARGET_SH4 || TARGET_FMOVD
4219 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
4220 == SCRATCH))
f3536097 4221 && REG_P (SET_DEST (pat))
104ee20b 4222 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
157371cf
AO		 4223 && ! (TARGET_SH2A
4224 && GET_MODE (SET_DEST (pat)) == SImode
e990551a
JS		 4225 && (satisfies_constraint_I20 (SET_SRC (pat))
4226 || satisfies_constraint_I28 (SET_SRC (pat))))
32a7ab3d 4227 && ! satisfies_constraint_I08 (SET_SRC (pat)))
e577c183
JR		 4228 return 1;
4229 }
d3ae8277 4230
8aa2a305 4231 return 0;
b9654711 4232}
b9654711 4233
1245df60 4234static int
cf277499 4235mova_p (rtx insn)
1245df60 4236{
f3536097 4237 return (NONJUMP_INSN_P (insn)
1245df60
R		 4238 && GET_CODE (PATTERN (insn)) == SET
4239 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
43c05634
AO		 4240 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
4241 /* Don't match mova_const. */
4241ecb0 4242 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
1245df60
R		 4243}
4244
078c8b08
R		 4245/* Fix up a mova from a switch that went out of range. */
4246static void
4247fixup_mova (rtx mova)
4248{
4241ecb0 4249 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
078c8b08
R		 4250 if (! flag_pic)
4251 {
4241ecb0 4252 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
078c8b08
R		 4253 INSN_CODE (mova) = -1;
4254 }
4255 else
4256 {
4257 rtx worker = mova;
4258 rtx lab = gen_label_rtx ();
dc3ba671 4259 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
078c8b08
R		 4260
4261 do
4262 {
4263 worker = NEXT_INSN (worker);
f5b9e7c9 4264 gcc_assert (worker
f3536097
SZ		 4265 && !LABEL_P (worker)
4266 && !JUMP_P (worker));
4267 } while (NOTE_P (worker)
0bf72672 4268 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
078c8b08
R		 4269 wpat = PATTERN (worker);
4270 wpat0 = XVECEXP (wpat, 0, 0);
4271 wpat1 = XVECEXP (wpat, 0, 1);
4272 wsrc = SET_SRC (wpat0);
4273 PATTERN (worker) = (gen_casesi_worker_2
4274 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
4275 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
4276 XEXP (wpat1, 0)));
4277 INSN_CODE (worker) = -1;
dc3ba671
RS		 4278 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4279 base = gen_rtx_LABEL_REF (Pmode, lab);
4280 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
078c8b08
R		 4281 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
4282 INSN_CODE (mova) = -1;
4283 }
4284}
4285
4241ecb0
R		 4286/* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4287 *num_mova, and check if the new mova is not nested within the first one.
4288 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4289 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4290static int
4291untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
4292{
c6d56443
KK		 4293 int n_addr = 0; /* Initialization to shut up spurious warning. */
4294 int f_target, n_target = 0; /* Likewise. */
4241ecb0
R		 4295
4296 if (optimize)
4297 {
77253e56
KK		 4298 /* If NEW_MOVA has no address yet, it will be handled later. */
4299 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4300 return -1;
4301
4241ecb0
R		 4302 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4303 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4304 if (n_addr > n_target || n_addr + 1022 < n_target)
4305 {
4306 /* Change the mova into a load.
4307 broken_move will then return true for it. */
4308 fixup_mova (new_mova);
4309 return 1;
4310 }
4311 }
4312 if (!(*num_mova)++)
4313 {
4314 *first_mova = new_mova;
4315 return 2;
4316 }
4317 if (!optimize
4318 || ((f_target
4319 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4320 >= n_target))
4321 return -1;
4322
4323 (*num_mova)--;
4324 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4325 > n_target - n_addr)
4326 {
4327 fixup_mova (*first_mova);
4328 return 0;
4329 }
4330 else
4331 {
4332 fixup_mova (new_mova);
4333 return 1;
4334 }
4335}
4336
8aa2a305
JW		 4337/* Find the last barrier from insn FROM which is close enough to hold the
4338 constant pool. If we can't find one, then create one near the end of
4339 the range. */
b9654711 4340
8aa2a305 4341static rtx
cf277499 4342find_barrier (int num_mova, rtx mova, rtx from)
b9654711 4343{
0d7e008e
SC		 4344 int count_si = 0;
4345 int count_hi = 0;
4346 int found_hi = 0;
4347 int found_si = 0;
fa5322fa 4348 int found_di = 0;
33f7f353
JR		 4349 int hi_align = 2;
4350 int si_align = 2;
1245df60 4351 int leading_mova = num_mova;
3a8699c7 4352 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
c17f53a8
JW		 4353 int si_limit;
4354 int hi_limit;
7a3cb3ab 4355 rtx orig = from;
8aa2a305
JW		 4356
4357 /* For HImode: range is 510, add 4 because pc counts from address of
4358 second instruction after this one, subtract 2 for the jump instruction
3adbde60
JW		 4359 that we may need to emit before the table, subtract 2 for the instruction
4360 that fills the jump delay slot (in very rare cases, reorg will take an
4361 instruction from after the constant pool or will leave the delay slot
4362 empty). This gives 510.
8aa2a305
JW		 4363 For SImode: range is 1020, add 4 because pc counts from address of
4364 second instruction after this one, subtract 2 in case pc is 2 byte
4365 aligned, subtract 2 for the jump instruction that we may need to emit
3adbde60
JW		 4366 before the table, subtract 2 for the instruction that fills the jump
4367 delay slot. This gives 1018. */
c17f53a8 4368
1245df60 4369 /* The branch will always be shortened now that the reference address for
956d6950 4370 forward branches is the successor address, thus we need no longer make
1245df60 4371 adjustments to the [sh]i_limit for -O0. */
c17f53a8 4372
1245df60
R		 4373 si_limit = 1018;
4374 hi_limit = 510;
e4fa6b06 4375
c17f53a8 4376 while (from && count_si < si_limit && count_hi < hi_limit)
0d7e008e 4377 {
33f7f353
JR		 4378 int inc = get_attr_length (from);
4379 int new_align = 1;
1245df60 4380
4241ecb0
R		 4381 /* If this is a label that existed at the time of the compute_alignments
4382 call, determine the alignment. N.B. When find_barrier recurses for
4383 an out-of-reach mova, we might see labels at the start of previously
4384 inserted constant tables. */
f3536097 4385 if (LABEL_P (from)
4241ecb0 4386 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
77008a44
R		 4387 {
4388 if (optimize)
4389 new_align = 1 << label_to_alignment (from);
f3536097 4390 else if (BARRIER_P (prev_nonnote_insn (from)))
77008a44
R		 4391 new_align = 1 << barrier_align (from);
4392 else
4393 new_align = 1;
4394 inc = 0;
4395 }
4241ecb0
R		 4396 /* In case we are scanning a constant table because of recursion, check
4397 for explicit alignments. If the table is long, we might be forced
4398 to emit the new table in front of it; the length of the alignment
4399 might be the last straw. */
f3536097 4400 else if (NONJUMP_INSN_P (from)
4241ecb0
R		 4401 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4402 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4403 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4404 /* When we find the end of a constant table, paste the new constant
4405 at the end. That is better than putting it in front because
4406 this way, we don't need extra alignment for adding a 4-byte-aligned
4407 mov(a) label to a 2/4 or 8/4 byte aligned table. */
f3536097 4408 else if (NONJUMP_INSN_P (from)
4241ecb0
R		 4409 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4410 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4411 return from;
8aa2a305 4412
f3536097 4413 if (BARRIER_P (from))
1245df60 4414 {
6d4d15b8 4415 rtx next;
33f7f353 4416
1245df60 4417 found_barrier = from;
33f7f353 4418
956d6950 4419 /* If we are at the end of the function, or in front of an alignment
1245df60
R		 4420 instruction, we need not insert an extra alignment. We prefer
4421 this kind of barrier. */
33f7f353 4422 if (barrier_align (from) > 2)
1245df60 4423 good_barrier = from;
6d4d15b8
KK		 4424
4425 /* If we are at the end of a hot/cold block, dump the constants
4426 here. */
4427 next = NEXT_INSN (from);
4428 if (next
4429 && NOTE_P (next)
4430 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4431 break;
1245df60 4432 }
8aa2a305 4433
8aa2a305 4434 if (broken_move (from))
0d7e008e 4435 {
1245df60
R		 4436 rtx pat, src, dst;
4437 enum machine_mode mode;
4438
4439 pat = PATTERN (from);
4440 if (GET_CODE (pat) == PARALLEL)
4441 pat = XVECEXP (pat, 0, 0);
4442 src = SET_SRC (pat);
4443 dst = SET_DEST (pat);
4444 mode = GET_MODE (dst);
c17f53a8
JW		 4445
4446 /* We must explicitly check the mode, because sometimes the
4447 front end will generate code to load unsigned constants into
4448 HImode targets without properly sign extending them. */
225e4f43
R		 4449 if (mode == HImode
4450 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
00e94d65 4451 {
1245df60 4452 found_hi += 2;
00e94d65
RK		 4453 /* We put the short constants before the long constants, so
4454 we must count the length of short constants in the range
4455 for the long constants. */
4456 /* ??? This isn't optimal, but is easy to do. */
1245df60 4457 si_limit -= 2;
00e94d65 4458 }
0d7e008e 4459 else
1245df60 4460 {
fa5322fa
AO		 4461 /* We dump DF/DI constants before SF/SI ones, because
4462 the limit is the same, but the alignment requirements
4463 are higher. We may waste up to 4 additional bytes
4464 for alignment, and the DF/DI constant may have
24746a42 4465 another SF/SI constant placed before it. */
fa5322fa
AO		 4466 if (TARGET_SHCOMPACT
4467 && ! found_di
4468 && (mode == DFmode || mode == DImode))
4469 {
4470 found_di = 1;
4471 si_limit -= 8;
4472 }
33f7f353
JR		 4473 while (si_align > 2 && found_si + si_align - 2 > count_si)
4474 si_align >>= 1;
1245df60
R		 4475 if (found_si > count_si)
4476 count_si = found_si;
4477 found_si += GET_MODE_SIZE (mode);
4478 if (num_mova)
4479 si_limit -= GET_MODE_SIZE (mode);
4480 }
0d7e008e 4481 }
5325c0fa 4482
33f7f353 4483 if (mova_p (from))
1245df60 4484 {
4241ecb0 4485 switch (untangle_mova (&num_mova, &mova, from))
1245df60 4486 {
4241ecb0
R		 4487 case 0: return find_barrier (0, 0, mova);
4488 case 2:
4489 {
4490 leading_mova = 0;
4491 barrier_before_mova
4492 = good_barrier ? good_barrier : found_barrier;
4493 }
4494 default: break;
1245df60
R		 4495 }
4496 if (found_si > count_si)
4497 count_si = found_si;
4498 }
f3536097 4499 else if (JUMP_TABLE_DATA_P (from))
1245df60 4500 {
4241ecb0
R		 4501 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4502 || (num_mova
4503 && (prev_nonnote_insn (from)
4504 == XEXP (MOVA_LABELREF (mova), 0))))
1245df60 4505 num_mova--;
10f4f635 4506 if (barrier_align (next_real_insn (from)) == align_jumps_log)
1245df60 4507 {
38e01259 4508 /* We have just passed the barrier in front of the
a0798779
R		 4509 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4510 the ADDR_DIFF_VEC is accessed as data, just like our pool
4511 constants, this is a good opportunity to accommodate what
4512 we have gathered so far.
1245df60
R		 4513 If we waited any longer, we could end up at a barrier in
4514 front of code, which gives worse cache usage for separated
4515 instruction / data caches. */
a0798779 4516 good_barrier = found_barrier;
1245df60
R		 4517 break;
4518 }
a0798779
R		 4519 else
4520 {
4521 rtx body = PATTERN (from);
4522 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4523 }
1245df60 4524 }
50ceefc2 4525 /* For the SH1, we generate alignments even after jumps-around-jumps. */
f3536097 4526 else if (JUMP_P (from)
50ceefc2
R		 4527 && ! TARGET_SH2
4528 && ! TARGET_SMALLCODE)
4529 new_align = 4;
5325c0fa 4530
0d7e008e 4531 if (found_si)
33f7f353 4532 {
50ceefc2 4533 count_si += inc;
33f7f353
JR		 4534 if (new_align > si_align)
4535 {
318881c0 4536 si_limit -= (count_si - 1) & (new_align - si_align);
33f7f353
JR		 4537 si_align = new_align;
4538 }
318881c0 4539 count_si = (count_si + new_align - 1) & -new_align;
33f7f353 4540 }
0d7e008e 4541 if (found_hi)
33f7f353 4542 {
50ceefc2 4543 count_hi += inc;
33f7f353
JR		 4544 if (new_align > hi_align)
4545 {
318881c0 4546 hi_limit -= (count_hi - 1) & (new_align - hi_align);
33f7f353
JR		 4547 hi_align = new_align;
4548 }
318881c0 4549 count_hi = (count_hi + new_align - 1) & -new_align;
33f7f353 4550 }
0d7e008e
SC		 4551 from = NEXT_INSN (from);
4552 }
4553
1245df60 4554 if (num_mova)
eda44c78
R		 4555 {
4556 if (leading_mova)
4557 {
4558 /* Try as we might, the leading mova is out of range. Change
4559 it into a load (which will become a pcload) and retry. */
078c8b08 4560 fixup_mova (mova);
eda44c78
R		 4561 return find_barrier (0, 0, mova);
4562 }
4563 else
4564 {
4565 /* Insert the constant pool table before the mova instruction,
4566 to prevent the mova label reference from going out of range. */
4567 from = mova;
4568 good_barrier = found_barrier = barrier_before_mova;
4569 }
4570 }
5325c0fa 4571
1245df60
R		 4572 if (found_barrier)
4573 {
33f7f353 4574 if (good_barrier && next_real_insn (found_barrier))
1245df60 4575 found_barrier = good_barrier;
1245df60
R		 4576 }
4577 else
b9654711 4578 {
8aa2a305
JW		 4579 /* We didn't find a barrier in time to dump our stuff,
4580 so we'll make one. */
0d7e008e 4581 rtx label = gen_label_rtx ();
8aa2a305 4582
5dbcc9c0
RK		 4583 /* If we exceeded the range, then we must back up over the last
4584 instruction we looked at. Otherwise, we just need to undo the
4585 NEXT_INSN at the end of the loop. */
7a3cb3ab
KK		 4586 if (PREV_INSN (from) != orig
4587 && (count_hi > hi_limit || count_si > si_limit))
5dbcc9c0
RK		 4588 from = PREV_INSN (PREV_INSN (from));
4589 else
4590 from = PREV_INSN (from);
4591
8aa2a305
JW		 4592 /* Walk back to be just before any jump or label.
4593 Putting it before a label reduces the number of times the branch
4594 around the constant pool table will be hit. Putting it before
4595 a jump makes it more likely that the bra delay slot will be
4596 filled. */
f3536097
SZ		 4597 while (NOTE_P (from) || JUMP_P (from)
4598 || LABEL_P (from))
8aa2a305
JW		 4599 from = PREV_INSN (from);
4600
0d7e008e
SC		 4601 from = emit_jump_insn_after (gen_jump (label), from);
4602 JUMP_LABEL (from) = label;
e081ed26 4603 LABEL_NUSES (label) = 1;
0d7e008e
SC		 4604 found_barrier = emit_barrier_after (from);
4605 emit_label_after (label, found_barrier);
b9654711 4606 }
b9654711 4607
8aa2a305 4608 return found_barrier;
0d7e008e 4609}
b9654711 4610
4787bce0
JW		 4611/* If the instruction INSN is implemented by a special function, and we can
4612 positively find the register that is used to call the sfunc, and this
4613 register is not used anywhere else in this instruction - except as the
4614 destination of a set, return this register; else, return 0. */
1245df60 4615rtx
cf277499 4616sfunc_uses_reg (rtx insn)
4787bce0
JW		 4617{
4618 int i;
4619 rtx pattern, part, reg_part, reg;
4620
f3536097 4621 if (!NONJUMP_INSN_P (insn))
4787bce0
JW		 4622 return 0;
4623 pattern = PATTERN (insn);
4624 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4625 return 0;
4626
4627 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4628 {
4629 part = XVECEXP (pattern, 0, i);
1245df60 4630 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4787bce0
JW		 4631 reg_part = part;
4632 }
4633 if (! reg_part)
4634 return 0;
4635 reg = XEXP (reg_part, 0);
4636 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4637 {
4638 part = XVECEXP (pattern, 0, i);
225e4f43 4639 if (part == reg_part || GET_CODE (part) == CLOBBER)
4787bce0
JW		 4640 continue;
4641 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
f3536097 4642 && REG_P (SET_DEST (part)))
4787bce0
JW		 4643 ? SET_SRC (part) : part)))
4644 return 0;
4645 }
4646 return reg;
4647}
4648
933c3ba3
JW		 4649/* See if the only way in which INSN uses REG is by calling it, or by
4650 setting it while calling it. Set *SET to a SET rtx if the register
4651 is set by INSN. */
4652
4653static int
cf277499 4654noncall_uses_reg (rtx reg, rtx insn, rtx *set)
933c3ba3 4655{
4787bce0 4656 rtx pattern, reg2;
933c3ba3
JW		 4657
4658 *set = NULL_RTX;
4659
4787bce0
JW		 4660 reg2 = sfunc_uses_reg (insn);
4661 if (reg2 && REGNO (reg2) == REGNO (reg))
4662 {
4663 pattern = single_set (insn);
4664 if (pattern
f3536097 4665 && REG_P (SET_DEST (pattern))
4787bce0
JW		 4666 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4667 *set = pattern;
4668 return 0;
4669 }
f3536097 4670 if (!CALL_P (insn))
933c3ba3
JW		 4671 {
4672 /* We don't use rtx_equal_p because we don't care if the mode is
4673 different. */
4674 pattern = single_set (insn);
4675 if (pattern
f3536097 4676 && REG_P (SET_DEST (pattern))
933c3ba3
JW		 4677 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4678 {
4787bce0
JW		 4679 rtx par, part;
4680 int i;
4681
933c3ba3 4682 *set = pattern;
4787bce0
JW		 4683 par = PATTERN (insn);
4684 if (GET_CODE (par) == PARALLEL)
4685 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4686 {
4687 part = XVECEXP (par, 0, i);
4688 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4689 return 1;
4690 }
4691 return reg_mentioned_p (reg, SET_SRC (pattern));
933c3ba3
JW		 4692 }
4693
4694 return 1;
4695 }
4696
4697 pattern = PATTERN (insn);
4698
4699 if (GET_CODE (pattern) == PARALLEL)
4700 {
4701 int i;
4702
4703 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4704 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4705 return 1;
4706 pattern = XVECEXP (pattern, 0, 0);
4707 }
4708
4709 if (GET_CODE (pattern) == SET)
4710 {
4711 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4712 {
4713 /* We don't use rtx_equal_p, because we don't care if the
4714 mode is different. */
f3536097 4715 if (!REG_P (SET_DEST (pattern))
933c3ba3
JW		 4716 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4717 return 1;
4718
4719 *set = pattern;
4720 }
4721
4722 pattern = SET_SRC (pattern);
4723 }
4724
4725 if (GET_CODE (pattern) != CALL
f3536097 4726 || !MEM_P (XEXP (pattern, 0))
933c3ba3
JW		 4727 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4728 return 1;
4729
4730 return 0;
4731}
4732
1245df60
R		 4733/* Given a X, a pattern of an insn or a part of it, return a mask of used
4734 general registers. Bits 0..15 mean that the respective registers
4735 are used as inputs in the instruction. Bits 16..31 mean that the
4736 registers 0..15, respectively, are used as outputs, or are clobbered.
4737 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4738int
cf277499 4739regs_used (rtx x, int is_dest)
1245df60
R		 4740{
4741 enum rtx_code code;
6f7d635c 4742 const char *fmt;
1245df60
R		 4743 int i, used = 0;
4744
4745 if (! x)
4746 return used;
4747 code = GET_CODE (x);
4748 switch (code)
4749 {
4750 case REG:
4751 if (REGNO (x) < 16)
4752 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4753 << (REGNO (x) + is_dest));
4754 return 0;
4755 case SUBREG:
4756 {
4757 rtx y = SUBREG_REG (x);
f676971a 4758
f3536097 4759 if (!REG_P (y))
1245df60
R		 4760 break;
4761 if (REGNO (y) < 16)
4762 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
ddef6bc7
JJ		 4763 << (REGNO (y) +
4764 subreg_regno_offset (REGNO (y),
4765 GET_MODE (y),
4766 SUBREG_BYTE (x),
4767 GET_MODE (x)) + is_dest));
1245df60
R		 4768 return 0;
4769 }
4770 case SET:
4771 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4772 case RETURN:
4773 /* If there was a return value, it must have been indicated with USE. */
4774 return 0x00ffff00;
4775 case CLOBBER:
4776 is_dest = 1;
4777 break;
4778 case MEM:
4779 is_dest = 0;
4780 break;
4781 case CALL:
4782 used |= 0x00ff00f0;
4783 break;
318881c0
KG		 4784 default:
4785 break;
1245df60
R		 4786 }
4787
4788 fmt = GET_RTX_FORMAT (code);
4789
4790 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4791 {
4792 if (fmt[i] == 'E')
4793 {
4794 register int j;
4795 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4796 used |= regs_used (XVECEXP (x, i, j), is_dest);
4797 }
4798 else if (fmt[i] == 'e')
4799 used |= regs_used (XEXP (x, i), is_dest);
4800 }
4801 return used;
4802}
4803
4804/* Create an instruction that prevents redirection of a conditional branch
956d6950 4805 to the destination of the JUMP with address ADDR.
1245df60
R		 4806 If the branch needs to be implemented as an indirect jump, try to find
4807 a scratch register for it.
4808 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4809 If any preceding insn that doesn't fit into a delay slot is good enough,
4810 pass 1. Pass 2 if a definite blocking insn is needed.
4811 -1 is used internally to avoid deep recursion.
4812 If a blocking instruction is made or recognized, return it. */
f676971a 4813
1245df60 4814static rtx
cf277499 4815gen_block_redirect (rtx jump, int addr, int need_block)
1245df60
R		 4816{
4817 int dead = 0;
4818 rtx prev = prev_nonnote_insn (jump);
4819 rtx dest;
4820
4821 /* First, check if we already have an instruction that satisfies our need. */
f3536097 4822 if (prev && NONJUMP_INSN_P (prev) && ! INSN_DELETED_P (prev))
1245df60
R		 4823 {
4824 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4825 return prev;
4826 if (GET_CODE (PATTERN (prev)) == USE
4827 || GET_CODE (PATTERN (prev)) == CLOBBER
4828 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4829 prev = jump;
4830 else if ((need_block &= ~1) < 0)
4831 return prev;
4832 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4833 need_block = 0;
4834 }
f9654065
R		 4835 if (GET_CODE (PATTERN (jump)) == RETURN)
4836 {
4837 if (! need_block)
4838 return prev;
4839 /* Reorg even does nasty things with return insns that cause branches
4840 to go out of range - see find_end_label and callers. */
a556fd39 4841 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
f9654065 4842 }
1245df60
R		 4843 /* We can't use JUMP_LABEL here because it might be undefined
4844 when not optimizing. */
4845 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4846 /* If the branch is out of range, try to find a scratch register for it. */
4847 if (optimize
11f9ed1a
KG		 4848 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4849 > 4092 + 4098))
1245df60
R		 4850 {
4851 rtx scan;
4852 /* Don't look for the stack pointer as a scratch register,
956d6950 4853 it would cause trouble if an interrupt occurred. */
0a2aaacc 4854 unsigned attempt = 0x7fff, used;
1245df60 4855 int jump_left = flag_expensive_optimizations + 1;
f676971a 4856
1245df60
R		 4857 /* It is likely that the most recent eligible instruction is wanted for
4858 the delay slot. Therefore, find out which registers it uses, and
4859 try to avoid using them. */
f676971a 4860
318881c0 4861 for (scan = jump; (scan = PREV_INSN (scan)); )
1245df60
R		 4862 {
4863 enum rtx_code code;
4864
4865 if (INSN_DELETED_P (scan))
4866 continue;
4867 code = GET_CODE (scan);
4868 if (code == CODE_LABEL || code == JUMP_INSN)
4869 break;
4870 if (code == INSN
4871 && GET_CODE (PATTERN (scan)) != USE
4872 && GET_CODE (PATTERN (scan)) != CLOBBER
4873 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4874 {
0a2aaacc 4875 attempt &= ~regs_used (PATTERN (scan), 0);
1245df60
R		 4876 break;
4877 }
4878 }
eda44c78
R		 4879 for (used = dead = 0, scan = JUMP_LABEL (jump);
4880 (scan = NEXT_INSN (scan)); )
1245df60
R		 4881 {
4882 enum rtx_code code;
4883
4884 if (INSN_DELETED_P (scan))
4885 continue;
4886 code = GET_CODE (scan);
ec8e098d 4887 if (INSN_P (scan))
1245df60
R		 4888 {
4889 used |= regs_used (PATTERN (scan), 0);
4890 if (code == CALL_INSN)
4891 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4892 dead |= (used >> 16) & ~used;
0a2aaacc 4893 if (dead & attempt)
1245df60 4894 {
0a2aaacc 4895 dead &= attempt;
1245df60
R		 4896 break;
4897 }
4898 if (code == JUMP_INSN)
eda44c78
R		 4899 {
4900 if (jump_left-- && simplejump_p (scan))
4901 scan = JUMP_LABEL (scan);
4902 else
4903 break;
4904 }
1245df60
R		 4905 }
4906 }
4907 /* Mask out the stack pointer again, in case it was
4908 the only 'free' register we have found. */
4909 dead &= 0x7fff;
4910 }
4911 /* If the immediate destination is still in range, check for possible
4912 threading with a jump beyond the delay slot insn.
4913 Don't check if we are called recursively; the jump has been or will be
956d6950 4914 checked in a different invocation then. */
f676971a 4915
1245df60
R		 4916 else if (optimize && need_block >= 0)
4917 {
4918 rtx next = next_active_insn (next_active_insn (dest));
f3536097 4919 if (next && JUMP_P (next)
1245df60 4920 && GET_CODE (PATTERN (next)) == SET
ddf8ec7e 4921 && recog_memoized (next) == CODE_FOR_jump_compact)
1245df60
R		 4922 {
4923 dest = JUMP_LABEL (next);
4924 if (dest
11f9ed1a 4925 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
9d98a694
AO		 4926 > 4092 + 4098))
4927 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
1245df60
R		 4928 }
4929 }
4930
4931 if (dead)
4932 {
c5c76735 4933 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
1245df60
R		 4934
4935 /* It would be nice if we could convert the jump into an indirect
956d6950 4936 jump / far branch right now, and thus exposing all constituent
1245df60
R		 4937 instructions to further optimization. However, reorg uses
4938 simplejump_p to determine if there is an unconditional jump where
4939 it should try to schedule instructions from the target of the
4940 branch; simplejump_p fails for indirect jumps even if they have
4941 a JUMP_LABEL. */
4942 rtx insn = emit_insn_before (gen_indirect_jump_scratch
4943 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
4944 , jump);
10f4f635
R		 4945 /* ??? We would like this to have the scope of the jump, but that
4946 scope will change when a delay slot insn of an inner scope is added.
4947 Hence, after delay slot scheduling, we'll have to expect
4948 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
4949 the jump. */
f676971a 4950
86143cb4 4951 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
1245df60
R		 4952 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
4953 return insn;
4954 }
4955 else if (need_block)
4956 /* We can't use JUMP_LABEL here because it might be undefined
4957 when not optimizing. */
4958 return emit_insn_before (gen_block_branch_redirect
4959 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
4960 , jump);
4961 return prev;
4962}
4963
4964#define CONDJUMP_MIN -252
4965#define CONDJUMP_MAX 262
4966struct far_branch
4967{
4968 /* A label (to be placed) in front of the jump
4969 that jumps to our ultimate destination. */
4970 rtx near_label;
4971 /* Where we are going to insert it if we cannot move the jump any farther,
4972 or the jump itself if we have picked up an existing jump. */
4973 rtx insert_place;
4974 /* The ultimate destination. */
4975 rtx far_label;
4976 struct far_branch *prev;
4977 /* If the branch has already been created, its address;
4978 else the address of its first prospective user. */
4979 int address;
4980};
4981
cf277499 4982static void gen_far_branch (struct far_branch *);
1245df60 4983enum mdep_reorg_phase_e mdep_reorg_phase;
c5b9ef02 4984static void
cf277499 4985gen_far_branch (struct far_branch *bp)
1245df60
R		 4986{
4987 rtx insn = bp->insert_place;
4988 rtx jump;
4989 rtx label = gen_label_rtx ();
f5b9e7c9 4990 int ok;
1245df60
R		 4991
4992 emit_label_after (label, insn);
4993 if (bp->far_label)
4994 {
4995 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
4996 LABEL_NUSES (bp->far_label)++;
4997 }
4998 else
4999 jump = emit_jump_insn_after (gen_return (), insn);
225e4f43
R		 5000 /* Emit a barrier so that reorg knows that any following instructions
5001 are not reachable via a fall-through path.
fae778eb 5002 But don't do this when not optimizing, since we wouldn't suppress the
225e4f43
R		 5003 alignment for the barrier then, and could end up with out-of-range
5004 pc-relative loads. */
5005 if (optimize)
5006 emit_barrier_after (jump);
1245df60
R		 5007 emit_label_after (bp->near_label, insn);
5008 JUMP_LABEL (jump) = bp->far_label;
f5b9e7c9
NS		 5009 ok = invert_jump (insn, label, 1);
5010 gcc_assert (ok);
5011
f9654065
R		 5012 /* If we are branching around a jump (rather than a return), prevent
5013 reorg from using an insn from the jump target as the delay slot insn -
5014 when reorg did this, it pessimized code (we rather hide the delay slot)
5015 and it could cause branches to go out of range. */
5016 if (bp->far_label)
5017 (emit_insn_after
5018 (gen_stuff_delay_slot
5019 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
5020 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
5021 insn));
1245df60
R		 5022 /* Prevent reorg from undoing our splits. */
5023 gen_block_redirect (jump, bp->address += 2, 2);
5024}
5025
1245df60
R		 5026/* Fix up ADDR_DIFF_VECs. */
5027void
cf277499 5028fixup_addr_diff_vecs (rtx first)
1245df60
R		 5029{
5030 rtx insn;
33f7f353 5031
1245df60
R		 5032 for (insn = first; insn; insn = NEXT_INSN (insn))
5033 {
eb3881bf 5034 rtx vec_lab, pat, prev, prevpat, x, braf_label;
1245df60 5035
f3536097 5036 if (!JUMP_P (insn)
1245df60
R		 5037 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
5038 continue;
5039 pat = PATTERN (insn);
33f7f353 5040 vec_lab = XEXP (XEXP (pat, 0), 0);
1245df60 5041
33f7f353
JR		 5042 /* Search the matching casesi_jump_2. */
5043 for (prev = vec_lab; ; prev = PREV_INSN (prev))
1245df60 5044 {
f3536097 5045 if (!JUMP_P (prev))
33f7f353
JR		 5046 continue;
5047 prevpat = PATTERN (prev);
5048 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
5049 continue;
5050 x = XVECEXP (prevpat, 0, 1);
5051 if (GET_CODE (x) != USE)
5052 continue;
5053 x = XEXP (x, 0);
5054 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
5055 break;
1245df60 5056 }
157371cf
AO		 5057 /* FIXME: This is a bug in the optimizer, but it seems harmless
5058 to just avoid panicing. */
5059 if (!prev)
5060 continue;
eb3881bf
R		 5061
5062 /* Emit the reference label of the braf where it belongs, right after
5063 the casesi_jump_2 (i.e. braf). */
5064 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
5065 emit_label_after (braf_label, prev);
5066
33f7f353
JR		 5067 /* Fix up the ADDR_DIF_VEC to be relative
5068 to the reference address of the braf. */
eb3881bf 5069 XEXP (XEXP (pat, 0), 0) = braf_label;
1245df60 5070 }
1245df60
R		 5071}
5072
33f7f353
JR		 5073/* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5074 a barrier. Return the base 2 logarithm of the desired alignment. */
1245df60 5075int
cf277499 5076barrier_align (rtx barrier_or_label)
1245df60 5077{
33f7f353 5078 rtx next = next_real_insn (barrier_or_label), pat, prev;
3a8699c7 5079 int slot, credit, jump_to_next = 0;
f676971a 5080
33f7f353 5081 if (! next)
1245df60 5082 return 0;
1245df60 5083
33f7f353 5084 pat = PATTERN (next);
1245df60 5085
33f7f353
JR		 5086 if (GET_CODE (pat) == ADDR_DIFF_VEC)
5087 return 2;
1245df60 5088
4773afa4 5089 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
33f7f353
JR		 5090 /* This is a barrier in front of a constant table. */
5091 return 0;
5092
5093 prev = prev_real_insn (barrier_or_label);
5094 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
1245df60 5095 {
33f7f353
JR		 5096 pat = PATTERN (prev);
5097 /* If this is a very small table, we want to keep the alignment after
5098 the table to the minimum for proper code alignment. */
5099 return ((TARGET_SMALLCODE
d042370e 5100 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
832a3292 5101 <= (unsigned) 1 << (CACHE_LOG - 2)))
10f4f635 5102 ? 1 << TARGET_SHMEDIA : align_jumps_log);
1245df60 5103 }
33f7f353
JR		 5104
5105 if (TARGET_SMALLCODE)
5106 return 0;
5107
4d070fd3 5108 if (! TARGET_SH2 || ! optimize)
10f4f635 5109 return align_jumps_log;
33f7f353 5110
225e4f43
R		 5111 /* When fixing up pcloads, a constant table might be inserted just before
5112 the basic block that ends with the barrier. Thus, we can't trust the
5113 instruction lengths before that. */
5114 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
1245df60 5115 {
225e4f43
R		 5116 /* Check if there is an immediately preceding branch to the insn beyond
5117 the barrier. We must weight the cost of discarding useful information
5118 from the current cache line when executing this branch and there is
5119 an alignment, against that of fetching unneeded insn in front of the
5120 branch target when there is no alignment. */
5121
f676971a
EC		 5122 /* There are two delay_slot cases to consider. One is the simple case
5123 where the preceding branch is to the insn beyond the barrier (simple
5124 delay slot filling), and the other is where the preceding branch has
5125 a delay slot that is a duplicate of the insn after the barrier
5126 (fill_eager_delay_slots) and the branch is to the insn after the insn
b1b41fe4
CP		 5127 after the barrier. */
5128
225e4f43
R		 5129 /* PREV is presumed to be the JUMP_INSN for the barrier under
5130 investigation. Skip to the insn before it. */
5131 prev = prev_real_insn (prev);
5132
c5b9ef02 5133 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
f3536097 5134 credit >= 0 && prev && NONJUMP_INSN_P (prev);
225e4f43
R		 5135 prev = prev_real_insn (prev))
5136 {
b1b41fe4 5137 jump_to_next = 0;
225e4f43
R		 5138 if (GET_CODE (PATTERN (prev)) == USE
5139 || GET_CODE (PATTERN (prev)) == CLOBBER)
5140 continue;
5141 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
b1b41fe4
CP		 5142 {
5143 prev = XVECEXP (PATTERN (prev), 0, 1);
f676971a 5144 if (INSN_UID (prev) == INSN_UID (next))
b1b41fe4
CP		 5145 {
5146 /* Delay slot was filled with insn at jump target. */
5147 jump_to_next = 1;
5148 continue;
5149 }
5150 }
5151
225e4f43
R		 5152 if (slot &&
5153 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5154 slot = 0;
5155 credit -= get_attr_length (prev);
5156 }
5157 if (prev
f3536097 5158 && JUMP_P (prev)
2b9d17c7
AH		 5159 && JUMP_LABEL (prev))
5160 {
5161 rtx x;
300c5453 5162 if (jump_to_next
2b9d17c7 5163 || next_real_insn (JUMP_LABEL (prev)) == next
1594c6bc
AO		 5164 /* If relax_delay_slots() decides NEXT was redundant
5165 with some previous instruction, it will have
5166 redirected PREV's jump to the following insn. */
5d291213 5167 || JUMP_LABEL (prev) == next_nonnote_insn (next)
300c5453
AO		 5168 /* There is no upper bound on redundant instructions
5169 that might have been skipped, but we must not put an
2b9d17c7 5170 alignment where none had been before. */
f676971a
EC		 5171 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
5172 (INSN_P (x)
2b9d17c7 5173 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
9959c8c7
R		 5174 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
5175 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
2b9d17c7
AH		 5176 {
5177 rtx pat = PATTERN (prev);
5178 if (GET_CODE (pat) == PARALLEL)
300c5453 5179 pat = XVECEXP (pat, 0, 0);
2b9d17c7
AH		 5180 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
5181 return 0;
5182 }
300c5453 5183 }
33f7f353 5184 }
f676971a 5185
10f4f635 5186 return align_jumps_log;
1245df60
R		 5187}
5188
2148624a
R		 5189/* If we are inside a phony loop, almost any kind of label can turn up as the
5190 first one in the loop. Aligning a braf label causes incorrect switch
5191 destination addresses; we can detect braf labels because they are
5192 followed by a BARRIER.
5193 Applying loop alignment to small constant or switch tables is a waste
5194 of space, so we suppress this too. */
5195int
cf277499 5196sh_loop_align (rtx label)
2148624a
R		 5197{
5198 rtx next = label;
5199
5200 do
5201 next = next_nonnote_insn (next);
f3536097 5202 while (next && LABEL_P (next));
2148624a
R		 5203
5204 if (! next
2c3c49de 5205 || ! INSN_P (next)
2148624a
R		 5206 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
5207 || recog_memoized (next) == CODE_FOR_consttable_2)
5208 return 0;
fa5322fa 5209
10f4f635 5210 return align_loops_log;
2148624a
R		 5211}
5212
18dbd950 5213/* Do a final pass over the function, just before delayed branch
933c3ba3 5214 scheduling. */
b9654711 5215
18dbd950 5216static void
cf277499 5217sh_reorg (void)
0d7e008e 5218{
18dbd950 5219 rtx first, insn, mova = NULL_RTX;
1245df60 5220 int num_mova;
c5c76735
JL		 5221 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
5222 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
8aa2a305 5223
18dbd950 5224 first = get_insns ();
4241ecb0 5225 max_labelno_before_reorg = max_label_num ();
18dbd950 5226
cb51ecd2
AO		 5227 /* We must split call insns before introducing `mova's. If we're
5228 optimizing, they'll have already been split. Otherwise, make
5229 sure we don't split them too late. */
5230 if (! optimize)
6f862f2f 5231 split_all_insns_noflow ();
cb51ecd2 5232
fa5322fa
AO		 5233 if (TARGET_SHMEDIA)
5234 return;
5235
933c3ba3
JW		 5236 /* If relaxing, generate pseudo-ops to associate function calls with
5237 the symbols they call. It does no harm to not generate these
5238 pseudo-ops. However, when we can generate them, it enables to
5239 linker to potentially relax the jsr to a bsr, and eliminate the
5240 register load and, possibly, the constant pool entry. */
5241
1245df60 5242 mdep_reorg_phase = SH_INSERT_USES_LABELS;
933c3ba3
JW		 5243 if (TARGET_RELAX)
5244 {
cf7c4aa6
HPN		 5245 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5246 own purposes. This works because none of the remaining passes
933c3ba3
JW		 5247 need to look at them.
5248
5249 ??? But it may break in the future. We should use a machine
5250 dependent REG_NOTE, or some other approach entirely. */
5251 for (insn = first; insn; insn = NEXT_INSN (insn))
5252 {
2c3c49de 5253 if (INSN_P (insn))
933c3ba3
JW		 5254 {
5255 rtx note;
5256
cf7c4aa6
HPN		 5257 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
5258 NULL_RTX)) != 0)
933c3ba3
JW		 5259 remove_note (insn, note);
5260 }
5261 }
5262
5263 for (insn = first; insn; insn = NEXT_INSN (insn))
5264 {
5265 rtx pattern, reg, link, set, scan, dies, label;
5266 int rescan = 0, foundinsn = 0;
5267
f3536097 5268 if (CALL_P (insn))
4787bce0
JW		 5269 {
5270 pattern = PATTERN (insn);
933c3ba3 5271
4787bce0
JW		 5272 if (GET_CODE (pattern) == PARALLEL)
5273 pattern = XVECEXP (pattern, 0, 0);
5274 if (GET_CODE (pattern) == SET)
5275 pattern = SET_SRC (pattern);
933c3ba3 5276
4787bce0 5277 if (GET_CODE (pattern) != CALL
f3536097 5278 || !MEM_P (XEXP (pattern, 0)))
4787bce0 5279 continue;
933c3ba3 5280
4787bce0
JW		 5281 reg = XEXP (XEXP (pattern, 0), 0);
5282 }
5283 else
5284 {
5285 reg = sfunc_uses_reg (insn);
5286 if (! reg)
5287 continue;
5288 }
933c3ba3 5289
f3536097 5290 if (!REG_P (reg))
933c3ba3
JW		 5291 continue;
5292
6fb5fa3c
DB		 5293 /* Try scanning backward to find where the register is set. */
5294 link = NULL;
5295 for (scan = PREV_INSN (insn);
f3536097 5296 scan && !LABEL_P (scan);
6fb5fa3c 5297 scan = PREV_INSN (scan))
933c3ba3 5298 {
6fb5fa3c
DB		 5299 if (! INSN_P (scan))
5300 continue;
933c3ba3 5301
6fb5fa3c
DB		 5302 if (! reg_mentioned_p (reg, scan))
5303 continue;
933c3ba3 5304
6fb5fa3c
DB		 5305 if (noncall_uses_reg (reg, scan, &set))
5306 break;
933c3ba3 5307
6fb5fa3c
DB		 5308 if (set)
5309 {
5310 link = scan;
5311 break;
933c3ba3
JW		 5312 }
5313 }
5314
5315 if (! link)
5316 continue;
5317
5318 /* The register is set at LINK. */
5319
5320 /* We can only optimize the function call if the register is
5321 being set to a symbol. In theory, we could sometimes
5322 optimize calls to a constant location, but the assembler
5323 and linker do not support that at present. */
5324 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5325 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5326 continue;
5327
5328 /* Scan forward from LINK to the place where REG dies, and
5329 make sure that the only insns which use REG are
5330 themselves function calls. */
5331
c1e8e6bd
JW		 5332 /* ??? This doesn't work for call targets that were allocated
5333 by reload, since there may not be a REG_DEAD note for the
5334 register. */
5335
933c3ba3
JW		 5336 dies = NULL_RTX;
5337 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5338 {
5339 rtx scanset;
5340
c1e8e6bd
JW		 5341 /* Don't try to trace forward past a CODE_LABEL if we haven't
5342 seen INSN yet. Ordinarily, we will only find the setting insn
6fb5fa3c 5343 if it is in the same basic block. However,
c1e8e6bd
JW		 5344 cross-jumping can insert code labels in between the load and
5345 the call, and can result in situations where a single call
5346 insn may have two targets depending on where we came from. */
5347
f3536097 5348 if (LABEL_P (scan) && ! foundinsn)
c1e8e6bd
JW		 5349 break;
5350
2c3c49de 5351 if (! INSN_P (scan))
933c3ba3
JW		 5352 continue;
5353
5354 /* Don't try to trace forward past a JUMP. To optimize
5355 safely, we would have to check that all the
c1e8e6bd 5356 instructions at the jump destination did not use REG. */
933c3ba3 5357
f3536097 5358 if (JUMP_P (scan))
933c3ba3
JW		 5359 break;
5360
5361 if (! reg_mentioned_p (reg, scan))
5362 continue;
5363
5364 if (noncall_uses_reg (reg, scan, &scanset))
5365 break;
5366
5367 if (scan == insn)
5368 foundinsn = 1;
5369
4787bce0 5370 if (scan != insn
f3536097 5371 && (CALL_P (scan) || sfunc_uses_reg (scan)))
933c3ba3
JW		 5372 {
5373 /* There is a function call to this register other
5374 than the one we are checking. If we optimize
5375 this call, we need to rescan again below. */
5376 rescan = 1;
5377 }
5378
5379 /* ??? We shouldn't have to worry about SCANSET here.
5380 We should just be able to check for a REG_DEAD note
5381 on a function call. However, the REG_DEAD notes are
5382 apparently not dependable around libcalls; c-torture
5383 execute/920501-2 is a test case. If SCANSET is set,
5384 then this insn sets the register, so it must have
5385 died earlier. Unfortunately, this will only handle
5386 the cases in which the register is, in fact, set in a
5387 later insn. */
5388
5389 /* ??? We shouldn't have to use FOUNDINSN here.
6fb5fa3c
DB		 5390 This dates back to when we used LOG_LINKS to find
5391 the most recent insn which sets the register. */
933c3ba3
JW		 5392
5393 if (foundinsn
5394 && (scanset
5395 || find_reg_note (scan, REG_DEAD, reg)))
5396 {
5397 dies = scan;
5398 break;
5399 }
5400 }
5401
5402 if (! dies)
5403 {
5404 /* Either there was a branch, or some insn used REG
5405 other than as a function call address. */
5406 continue;
5407 }
5408
cf7c4aa6
HPN		 5409 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5410 on the insn which sets the register, and on each call insn
5411 which uses the register. In final_prescan_insn we look for
5412 the REG_LABEL_OPERAND notes, and output the appropriate label
933c3ba3
JW		 5413 or pseudo-op. */
5414
5415 label = gen_label_rtx ();
65c5f2a6
ILT		 5416 add_reg_note (link, REG_LABEL_OPERAND, label);
5417 add_reg_note (insn, REG_LABEL_OPERAND, label);
933c3ba3
JW		 5418 if (rescan)
5419 {
5420 scan = link;
5421 do
5422 {
4787bce0
JW		 5423 rtx reg2;
5424
933c3ba3
JW		 5425 scan = NEXT_INSN (scan);
5426 if (scan != insn
f3536097 5427 && ((CALL_P (scan)
4787bce0
JW		 5428 && reg_mentioned_p (reg, scan))
5429 || ((reg2 = sfunc_uses_reg (scan))
5430 && REGNO (reg2) == REGNO (reg))))
65c5f2a6 5431 add_reg_note (scan, REG_LABEL_OPERAND, label);
933c3ba3
JW		 5432 }
5433 while (scan != dies);
5434 }
5435 }
5436 }
5437
33f7f353
JR		 5438 if (TARGET_SH2)
5439 fixup_addr_diff_vecs (first);
1245df60
R		 5440
5441 if (optimize)
5442 {
1245df60
R		 5443 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5444 shorten_branches (first);
5445 }
6dd3c0a5 5446
933c3ba3
JW		 5447 /* Scan the function looking for move instructions which have to be
5448 changed to pc-relative loads and insert the literal tables. */
6dd3c0a5
SB		 5449 label_ref_list_pool = create_alloc_pool ("label references list",
5450 sizeof (struct label_ref_list_d),
5451 30);
1245df60
R		 5452 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5453 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
0d7e008e 5454 {
1245df60
R		 5455 if (mova_p (insn))
5456 {
078c8b08
R		 5457 /* ??? basic block reordering can move a switch table dispatch
5458 below the switch table. Check if that has happened.
5459 We only have the addresses available when optimizing; but then,
5460 this check shouldn't be needed when not optimizing. */
4241ecb0 5461 if (!untangle_mova (&num_mova, &mova, insn))
078c8b08 5462 {
4241ecb0
R		 5463 insn = mova;
5464 num_mova = 0;
078c8b08 5465 }
1245df60 5466 }
f3536097 5467 else if (JUMP_P (insn)
1245df60 5468 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
4241ecb0
R		 5469 && num_mova
5470 /* ??? loop invariant motion can also move a mova out of a
5471 loop. Since loop does this code motion anyway, maybe we
5472 should wrap UNSPEC_MOVA into a CONST, so that reload can
5473 move it back. */
5474 && ((num_mova > 1
5475 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5476 || (prev_nonnote_insn (insn)
5477 == XEXP (MOVA_LABELREF (mova), 0))))
1245df60
R		 5478 {
5479 rtx scan;
5480 int total;
5481
5482 num_mova--;
5483
5484 /* Some code might have been inserted between the mova and
5485 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5486 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
33f7f353 5487 total += get_attr_length (scan);
1245df60
R		 5488
5489 /* range of mova is 1020, add 4 because pc counts from address of
5490 second instruction after this one, subtract 2 in case pc is 2
5491 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
956d6950 5492 cancels out with alignment effects of the mova itself. */
1245df60
R		 5493 if (total > 1022)
5494 {
5495 /* Change the mova into a load, and restart scanning
5496 there. broken_move will then return true for mova. */
078c8b08 5497 fixup_mova (mova);
1245df60
R		 5498 insn = mova;
5499 }
5500 }
078c8b08 5501 if (broken_move (insn)
f3536097 5502 || (NONJUMP_INSN_P (insn)
078c8b08 5503 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
0d7e008e 5504 {
0d7e008e 5505 rtx scan;
8aa2a305
JW		 5506 /* Scan ahead looking for a barrier to stick the constant table
5507 behind. */
1245df60 5508 rtx barrier = find_barrier (num_mova, mova, insn);
3a8699c7 5509 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
078c8b08 5510 int need_aligned_label = 0;
b9654711 5511
1245df60
R		 5512 if (num_mova && ! mova_p (mova))
5513 {
5514 /* find_barrier had to change the first mova into a
5515 pcload; thus, we have to start with this new pcload. */
5516 insn = mova;
5517 num_mova = 0;
5518 }
16bea517 5519 /* Now find all the moves between the points and modify them. */
0d7e008e
SC		 5520 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5521 {
f3536097 5522 if (LABEL_P (scan))
1245df60 5523 last_float = 0;
f3536097 5524 if (NONJUMP_INSN_P (scan)
078c8b08
R		 5525 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5526 need_aligned_label = 1;
0d7e008e
SC		 5527 if (broken_move (scan))
5528 {
e577c183
JR		 5529 rtx *patp = &PATTERN (scan), pat = *patp;
5530 rtx src, dst;
0d7e008e 5531 rtx lab;
0d7e008e 5532 rtx newsrc;
e577c183
JR		 5533 enum machine_mode mode;
5534
5535 if (GET_CODE (pat) == PARALLEL)
5536 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5537 src = SET_SRC (pat);
5538 dst = SET_DEST (pat);
5539 mode = GET_MODE (dst);
0d7e008e 5540
225e4f43
R		 5541 if (mode == SImode && hi_const (src)
5542 && REGNO (dst) != FPUL_REG)
0d7e008e 5543 {
23ed92ca 5544 int offset = 0;
8aa2a305 5545
0d7e008e 5546 mode = HImode;
d3ae8277 5547 while (GET_CODE (dst) == SUBREG)
23ed92ca 5548 {
ddef6bc7
JJ		 5549 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5550 GET_MODE (SUBREG_REG (dst)),
5551 SUBREG_BYTE (dst),
5552 GET_MODE (dst));
23ed92ca
JW		 5553 dst = SUBREG_REG (dst);
5554 }
c5c76735 5555 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
0d7e008e 5556 }
f3536097 5557 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
1245df60 5558 {
b8794099 5559 /* This must be an insn that clobbers r0. */
0f2b41b2
AO		 5560 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5561 XVECLEN (PATTERN (scan), 0)
5562 - 1);
5563 rtx clobber = *clobberp;
b8794099 5564
f5b9e7c9
NS		 5565 gcc_assert (GET_CODE (clobber) == CLOBBER
5566 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
b8794099 5567
1245df60
R		 5568 if (last_float
5569 && reg_set_between_p (r0_rtx, last_float_move, scan))
5570 last_float = 0;
3503150c
RS		 5571 if (last_float
5572 && TARGET_SHCOMPACT
5573 && GET_MODE_SIZE (mode) != 4
5574 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5575 last_float = 0;
1245df60
R		 5576 lab = add_constant (src, mode, last_float);
5577 if (lab)
5578 emit_insn_before (gen_mova (lab), scan);
5579 else
b8794099
R		 5580 {
5581 /* There will be a REG_UNUSED note for r0 on
5582 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5583 lest reorg:mark_target_live_regs will not
5584 consider r0 to be used, and we end up with delay
475f26dd 5585 slot insn in front of SCAN that clobbers r0. */
b8794099
R		 5586 rtx note
5587 = find_regno_note (last_float_move, REG_UNUSED, 0);
5588
ab1672a3
JW		 5589 /* If we are not optimizing, then there may not be
5590 a note. */
5591 if (note)
81f40b79 5592 PUT_REG_NOTE_KIND (note, REG_INC);
b8794099
R		 5593
5594 *last_float_addr = r0_inc_rtx;
5595 }
1245df60
R		 5596 last_float_move = scan;
5597 last_float = src;
57d38024 5598 newsrc = gen_const_mem (mode,
318881c0 5599 (((TARGET_SH4 && ! TARGET_FMOVD)
225e4f43 5600 || REGNO (dst) == FPUL_REG)
1245df60
R		 5601 ? r0_inc_rtx
5602 : r0_rtx));
5603 last_float_addr = &XEXP (newsrc, 0);
b8794099
R		 5604
5605 /* Remove the clobber of r0. */
0f2b41b2
AO		 5606 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5607 gen_rtx_SCRATCH (Pmode));
1245df60 5608 }
1a66cd67 5609 /* This is a mova needing a label. Create it. */
43c05634
AO		 5610 else if (GET_CODE (src) == UNSPEC
5611 && XINT (src, 1) == UNSPEC_MOVA
5612 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
1a66cd67 5613 {
43c05634 5614 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
1a66cd67 5615 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
e69d1422 5616 newsrc = gen_rtx_UNSPEC (SImode,
4773afa4
AO		 5617 gen_rtvec (1, newsrc),
5618 UNSPEC_MOVA);
1a66cd67 5619 }
1245df60
R		 5620 else
5621 {
5622 lab = add_constant (src, mode, 0);
542a8afa
RH		 5623 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5624 newsrc = gen_const_mem (mode, newsrc);
1245df60 5625 }
c5c76735 5626 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
e577c183 5627 INSN_CODE (scan) = -1;
0d7e008e
SC		 5628 }
5629 }
078c8b08 5630 dump_table (need_aligned_label ? insn : 0, barrier);
1245df60 5631 insn = barrier;
0d7e008e
SC		 5632 }
5633 }
6dd3c0a5 5634 free_alloc_pool (label_ref_list_pool);
4241ecb0
R		 5635 for (insn = first; insn; insn = NEXT_INSN (insn))
5636 PUT_MODE (insn, VOIDmode);
5637
1245df60 5638 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
9d98a694 5639 INSN_ADDRESSES_FREE ();
1245df60
R		 5640 split_branches (first);
5641
5642 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
a920aefe 5643 also has an effect on the register that holds the address of the sfunc.
1245df60
R		 5644 Insert an extra dummy insn in front of each sfunc that pretends to
5645 use this register. */
5646 if (flag_delayed_branch)
5647 {
5648 for (insn = first; insn; insn = NEXT_INSN (insn))
5649 {
5650 rtx reg = sfunc_uses_reg (insn);
5651
5652 if (! reg)
5653 continue;
5654 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5655 }
5656 }
225e4f43
R		 5657#if 0
5658 /* fpscr is not actually a user variable, but we pretend it is for the
5659 sake of the previous optimization passes, since we want it handled like
9f09b1f2 5660 one. However, we don't have any debugging information for it, so turn
225e4f43
R		 5661 it into a non-user variable now. */
5662 if (TARGET_SH4)
5663 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5664#endif
1245df60
R		 5665 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5666}
5667
5668int
cf277499 5669get_dest_uid (rtx label, int max_uid)
1245df60
R		 5670{
5671 rtx dest = next_real_insn (label);
5672 int dest_uid;
5673 if (! dest)
5674 /* This can happen for an undefined label. */
5675 return 0;
5676 dest_uid = INSN_UID (dest);
5677 /* If this is a newly created branch redirection blocking instruction,
5678 we cannot index the branch_uid or insn_addresses arrays with its
5679 uid. But then, we won't need to, because the actual destination is
5680 the following branch. */
5681 while (dest_uid >= max_uid)
5682 {
5683 dest = NEXT_INSN (dest);
5684 dest_uid = INSN_UID (dest);
5685 }
f3536097 5686 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
1245df60
R		 5687 return 0;
5688 return dest_uid;
5689}
5690
5691/* Split condbranches that are out of range. Also add clobbers for
5692 scratch registers that are needed in far jumps.
5693 We do this before delay slot scheduling, so that it can take our
5694 newly created instructions into account. It also allows us to
5695 find branches with common targets more easily. */
5696
5697static void
cf277499 5698split_branches (rtx first)
1245df60
R		 5699{
5700 rtx insn;
5701 struct far_branch **uid_branch, *far_branch_list = 0;
5702 int max_uid = get_max_uid ();
f5b9e7c9 5703 int ok;
1245df60
R		 5704
5705 /* Find out which branches are out of range. */
1245df60
R		 5706 shorten_branches (first);
5707
5708 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
2e09e75a 5709 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
1245df60
R		 5710
5711 for (insn = first; insn; insn = NEXT_INSN (insn))
2c3c49de 5712 if (! INSN_P (insn))
1245df60
R		 5713 continue;
5714 else if (INSN_DELETED_P (insn))
5715 {
5716 /* Shorten_branches would split this instruction again,
5717 so transform it into a note. */
a38e7aa5 5718 SET_INSN_DELETED (insn);
1245df60 5719 }
f3536097 5720 else if (JUMP_P (insn)
1245df60
R		 5721 /* Don't mess with ADDR_DIFF_VEC */
5722 && (GET_CODE (PATTERN (insn)) == SET
5723 || GET_CODE (PATTERN (insn)) == RETURN))
5724 {
5725 enum attr_type type = get_attr_type (insn);
5726 if (type == TYPE_CBRANCH)
5727 {
5728 rtx next, beyond;
f676971a 5729
1245df60
R		 5730 if (get_attr_length (insn) > 4)
5731 {
5732 rtx src = SET_SRC (PATTERN (insn));
1245df60 5733 rtx olabel = XEXP (XEXP (src, 1), 0);
9d98a694 5734 int addr = INSN_ADDRESSES (INSN_UID (insn));
1245df60
R		 5735 rtx label = 0;
5736 int dest_uid = get_dest_uid (olabel, max_uid);
5737 struct far_branch *bp = uid_branch[dest_uid];
f676971a 5738
1245df60 5739 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
25938114 5740 the label if the LABEL_NUSES count drops to zero. There is
1245df60
R		 5741 always a jump_optimize pass that sets these values, but it
5742 proceeds to delete unreferenced code, and then if not
956d6950 5743 optimizing, to un-delete the deleted instructions, thus
1245df60
R		 5744 leaving labels with too low uses counts. */
5745 if (! optimize)
5746 {
5747 JUMP_LABEL (insn) = olabel;
5748 LABEL_NUSES (olabel)++;
5749 }
5750 if (! bp)
5751 {
5752 bp = (struct far_branch *) alloca (sizeof *bp);
5753 uid_branch[dest_uid] = bp;
5754 bp->prev = far_branch_list;
5755 far_branch_list = bp;
5756 bp->far_label
5757 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5758 LABEL_NUSES (bp->far_label)++;
5759 }
5760 else
5761 {
5762 label = bp->near_label;
5763 if (! label && bp->address - addr >= CONDJUMP_MIN)
5764 {
5765 rtx block = bp->insert_place;
5766
5767 if (GET_CODE (PATTERN (block)) == RETURN)
5768 block = PREV_INSN (block);
5769 else
5770 block = gen_block_redirect (block,
5771 bp->address, 2);
5772 label = emit_label_after (gen_label_rtx (),
5773 PREV_INSN (block));
5774 bp->near_label = label;
5775 }
5776 else if (label && ! NEXT_INSN (label))
eda44c78
R		 5777 {
5778 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5779 bp->insert_place = insn;
5780 else
5781 gen_far_branch (bp);
5782 }
1245df60
R		 5783 }
5784 if (! label
318881c0 5785 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
1245df60
R		 5786 {
5787 bp->near_label = label = gen_label_rtx ();
5788 bp->insert_place = insn;
5789 bp->address = addr;
5790 }
2acdc1fb 5791 ok = redirect_jump (insn, label, 0);
f5b9e7c9 5792 gcc_assert (ok);
1245df60
R		 5793 }
5794 else
5795 {
5796 /* get_attr_length (insn) == 2 */
5797 /* Check if we have a pattern where reorg wants to redirect
5798 the branch to a label from an unconditional branch that
5799 is too far away. */
5800 /* We can't use JUMP_LABEL here because it might be undefined
5801 when not optimizing. */
33f7f353 5802 /* A syntax error might cause beyond to be NULL_RTX. */
1245df60
R		 5803 beyond
5804 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5805 0));
f676971a 5806
33f7f353 5807 if (beyond
f3536097 5808 && (JUMP_P (beyond)
b94544e4 5809 || ((beyond = next_active_insn (beyond))
f3536097 5810 && JUMP_P (beyond)))
1245df60 5811 && GET_CODE (PATTERN (beyond)) == SET
ddf8ec7e 5812 && recog_memoized (beyond) == CODE_FOR_jump_compact
9d98a694
AO		 5813 && ((INSN_ADDRESSES
5814 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
11f9ed1a 5815 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
1245df60
R		 5816 > 252 + 258 + 2))
5817 gen_block_redirect (beyond,
9d98a694 5818 INSN_ADDRESSES (INSN_UID (beyond)), 1);
1245df60 5819 }
f676971a 5820
1245df60
R		 5821 next = next_active_insn (insn);
5822
f3536097 5823 if ((JUMP_P (next)
03904fb3 5824 || ((next = next_active_insn (next))
f3536097 5825 && JUMP_P (next)))
1245df60 5826 && GET_CODE (PATTERN (next)) == SET
ddf8ec7e 5827 && recog_memoized (next) == CODE_FOR_jump_compact
9d98a694
AO		 5828 && ((INSN_ADDRESSES
5829 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
11f9ed1a 5830 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
1245df60 5831 > 252 + 258 + 2))
9d98a694 5832 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
1245df60
R		 5833 }
5834 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5835 {
9d98a694 5836 int addr = INSN_ADDRESSES (INSN_UID (insn));
1245df60
R		 5837 rtx far_label = 0;
5838 int dest_uid = 0;
5839 struct far_branch *bp;
5840
5841 if (type == TYPE_JUMP)
5842 {
5843 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5844 dest_uid = get_dest_uid (far_label, max_uid);
5845 if (! dest_uid)
5846 {
5847 /* Parse errors can lead to labels outside
5848 the insn stream. */
5849 if (! NEXT_INSN (far_label))
5850 continue;
5851
5852 if (! optimize)
5853 {
5854 JUMP_LABEL (insn) = far_label;
5855 LABEL_NUSES (far_label)++;
5856 }
8ceaac3c 5857 redirect_jump (insn, NULL_RTX, 1);
1245df60
R		 5858 far_label = 0;
5859 }
5860 }
5861 bp = uid_branch[dest_uid];
5862 if (! bp)
5863 {
5864 bp = (struct far_branch *) alloca (sizeof *bp);
5865 uid_branch[dest_uid] = bp;
5866 bp->prev = far_branch_list;
5867 far_branch_list = bp;
5868 bp->near_label = 0;
5869 bp->far_label = far_label;
5870 if (far_label)
5871 LABEL_NUSES (far_label)++;
5872 }
5873 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5874 if (addr - bp->address <= CONDJUMP_MAX)
5875 emit_label_after (bp->near_label, PREV_INSN (insn));
5876 else
5877 {
5878 gen_far_branch (bp);
5879 bp->near_label = 0;
5880 }
5881 else
5882 bp->near_label = 0;
5883 bp->address = addr;
5884 bp->insert_place = insn;
5885 if (! far_label)
5886 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5887 else
5888 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5889 }
5890 }
5891 /* Generate all pending far branches,
5892 and free our references to the far labels. */
5893 while (far_branch_list)
5894 {
5895 if (far_branch_list->near_label
5896 && ! NEXT_INSN (far_branch_list->near_label))
5897 gen_far_branch (far_branch_list);
5898 if (optimize
5899 && far_branch_list->far_label
5900 && ! --LABEL_NUSES (far_branch_list->far_label))
5901 delete_insn (far_branch_list->far_label);
5902 far_branch_list = far_branch_list->prev;
5903 }
a0798779
R		 5904
5905 /* Instruction length information is no longer valid due to the new
5906 instructions that have been generated. */
5907 init_insn_lengths ();
b9654711
SC		 5908}
5909
8aa2a305 5910/* Dump out instruction addresses, which is useful for debugging the
933c3ba3
JW		 5911 constant pool table stuff.
5912
5913 If relaxing, output the label and pseudo-ops used to link together
5914 calls and the instruction which set the registers. */
8aa2a305 5915
8aa2a305
JW		 5916/* ??? The addresses printed by this routine for insns are nonsense for
5917 insns which are inside of a sequence where none of the inner insns have
5918 variable length. This is because the second pass of shorten_branches
5919 does not bother to update them. */
0d7e008e 5920
8e87e161 5921void
cf277499
SB		 5922final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
5923 int noperands ATTRIBUTE_UNUSED)
b9654711 5924{
8aa2a305 5925 if (TARGET_DUMPISIZE)
9d98a694 5926 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
933c3ba3
JW		 5927
5928 if (TARGET_RELAX)
5929 {
5930 rtx note;
5931
cf7c4aa6 5932 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
933c3ba3
JW		 5933 if (note)
5934 {
5935 rtx pattern;
5936
5937 pattern = PATTERN (insn);
4b7d2f07
R		 5938 if (GET_CODE (pattern) == PARALLEL)
5939 pattern = XVECEXP (pattern, 0, 0);
f5b9e7c9
NS		 5940 switch (GET_CODE (pattern))
5941 {
f5b9e7c9
NS		 5942 case SET:
5943 if (GET_CODE (SET_SRC (pattern)) != CALL
5944 && get_attr_type (insn) != TYPE_SFUNC)
5945 {
5946 targetm.asm_out.internal_label
5947 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
5948 break;
5949 }
5950 /* else FALLTHROUGH */
5951 case CALL:
5952 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
5953 CODE_LABEL_NUMBER (XEXP (note, 0)));
5954 break;
5955
5956 default:
5957 gcc_unreachable ();
5958 }
933c3ba3
JW		 5959 }
5960 }
0d7e008e 5961}
b9654711 5962
8aa2a305 5963/* Dump out any constants accumulated in the final pass. These will
38e01259 5964 only be labels. */
b9654711 5965
318881c0 5966const char *
cf277499 5967output_jump_label_table (void)
0d7e008e 5968{
8aa2a305
JW		 5969 int i;
5970
5971 if (pool_size)
5972 {
5973 fprintf (asm_out_file, "\t.align 2\n");
5974 for (i = 0; i < pool_size; i++)
5975 {
5976 pool_node *p = &pool_vector[i];
5977
4977bab6 5978 (*targetm.asm_out.internal_label) (asm_out_file, "L",
8aa2a305
JW		 5979 CODE_LABEL_NUMBER (p->label));
5980 output_asm_insn (".long %O0", &p->value);
5981 }
5982 pool_size = 0;
5983 }
b9654711 5984
8aa2a305
JW		 5985 return "";
5986}
5987\f
5988/* A full frame looks like:
16bea517
JW		 5989
5990 arg-5
5991 arg-4
5992 [ if current_function_anonymous_args
5993 arg-3
5994 arg-2
5995 arg-1
5996 arg-0 ]
5997 saved-fp
5998 saved-r10
5999 saved-r11
6000 saved-r12
6001 saved-pr
6002 local-n
6003 ..
6004 local-1
6005 local-0 <- fp points here. */
8e87e161 6006
8aa2a305
JW		 6007/* Number of bytes pushed for anonymous args, used to pass information
6008 between expand_prologue and expand_epilogue. */
6009
fada1961
R		 6010/* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6011 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
726d4cb7
KK		 6012 for an epilogue and a negative value means that it's for a sibcall
6013 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6014 all the registers that are about to be restored, and hence dead. */
8aa2a305
JW		 6015
6016static void
fada1961
R		 6017output_stack_adjust (int size, rtx reg, int epilogue_p,
6018 HARD_REG_SET *live_regs_mask)
8aa2a305 6019{
fada1961 6020 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
8aa2a305
JW		 6021 if (size)
6022 {
fa5322fa
AO		 6023 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6024
157371cf
AO		 6025/* This test is bogus, as output_stack_adjust is used to re-align the
6026 stack. */
6027#if 0
f5b9e7c9 6028 gcc_assert (!(size % align));
157371cf 6029#endif
fa5322fa
AO		 6030
6031 if (CONST_OK_FOR_ADD (size))
2754d3c5 6032 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
f3cd5375
JW		 6033 /* Try to do it with two partial adjustments; however, we must make
6034 sure that the stack is properly aligned at all times, in case
6f317ef3 6035 an interrupt occurs between the two partial adjustments. */
fa5322fa
AO		 6036 else if (CONST_OK_FOR_ADD (size / 2 & -align)
6037 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
f3cd5375 6038 {
2754d3c5
R		 6039 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
6040 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
f3cd5375
JW		 6041 }
6042 else
8aa2a305 6043 {
f3cd5375 6044 rtx const_reg;
2754d3c5 6045 rtx insn;
fada1961
R		 6046 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
6047 int i;
f3cd5375
JW		 6048
6049 /* If TEMP is invalid, we could temporarily save a general
6050 register to MACL. However, there is currently no need
f5b9e7c9 6051 to handle this case, so just die when we see it. */
726d4cb7
KK		 6052 if (epilogue_p < 0
6053 || current_function_interrupt
62164eb4 6054 || ! call_really_used_regs[temp] || fixed_regs[temp])
fada1961 6055 temp = -1;
726d4cb7
KK		 6056 if (temp < 0 && ! current_function_interrupt
6057 && (TARGET_SHMEDIA || epilogue_p >= 0))
fada1961
R		 6058 {
6059 HARD_REG_SET temps;
6060 COPY_HARD_REG_SET (temps, call_used_reg_set);
6061 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
726d4cb7 6062 if (epilogue_p > 0)
fada1961 6063 {
726d4cb7 6064 int nreg = 0;
38173d38 6065 if (crtl->return_rtx)
726d4cb7
KK		 6066 {
6067 enum machine_mode mode;
38173d38 6068 mode = GET_MODE (crtl->return_rtx);
726d4cb7
KK		 6069 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
6070 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
6071 }
6072 for (i = 0; i < nreg; i++)
fada1961 6073 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
e3b5732b 6074 if (crtl->calls_eh_return)
fada1961
R		 6075 {
6076 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
6077 for (i = 0; i <= 3; i++)
6078 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
6079 }
6080 }
726d4cb7
KK		 6081 if (TARGET_SHMEDIA && epilogue_p < 0)
6082 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
6083 CLEAR_HARD_REG_BIT (temps, i);
6084 if (epilogue_p <= 0)
fada1961
R		 6085 {
6086 for (i = FIRST_PARM_REG;
6087 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
6088 CLEAR_HARD_REG_BIT (temps, i);
6de9cd9a 6089 if (cfun->static_chain_decl != NULL)
fada1961
R		 6090 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
6091 }
6092 temp = scavenge_reg (&temps);
6093 }
6094 if (temp < 0 && live_regs_mask)
eb996a4a
KK		 6095 {
6096 HARD_REG_SET temps;
6097
6098 COPY_HARD_REG_SET (temps, *live_regs_mask);
6099 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
6100 temp = scavenge_reg (&temps);
6101 }
f3cd5375 6102 if (temp < 0)
726d4cb7 6103 {
f5b9e7c9
NS		 6104 rtx adj_reg, tmp_reg, mem;
6105
726d4cb7
KK		 6106 /* If we reached here, the most likely case is the (sibcall)
6107 epilogue for non SHmedia. Put a special push/pop sequence
6108 for such case as the last resort. This looks lengthy but
f5b9e7c9
NS		 6109 would not be problem because it seems to be very
6110 rare. */
6111
6112 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
6113
6114
6115 /* ??? There is still the slight possibility that r4 or
6116 r5 have been reserved as fixed registers or assigned
6117 as global registers, and they change during an
6118 interrupt. There are possible ways to handle this:
6119
6120 - If we are adjusting the frame pointer (r14), we can do
6121 with a single temp register and an ordinary push / pop
6122 on the stack.
6123 - Grab any call-used or call-saved registers (i.e. not
6124 fixed or globals) for the temps we need. We might
6125 also grab r14 if we are adjusting the stack pointer.
6126 If we can't find enough available registers, issue
6127 a diagnostic and die - the user must have reserved
6128 way too many registers.
6129 But since all this is rather unlikely to happen and
6130 would require extra testing, we just die if r4 / r5
6131 are not available. */
6132 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
6133 && !global_regs[4] && !global_regs[5]);
6134
6135 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
6136 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
57d38024 6137 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
f5b9e7c9
NS		 6138 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
6139 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
57d38024 6140 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
f5b9e7c9 6141 emit_move_insn (mem, tmp_reg);
57d38024
R		 6142 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
6143 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6144 emit_move_insn (mem, tmp_reg);
6145 emit_move_insn (reg, adj_reg);
6146 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6147 emit_move_insn (adj_reg, mem);
6148 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6149 emit_move_insn (tmp_reg, mem);
eb996a4a 6150 /* Tell flow the insns that pop r4/r5 aren't dead. */
c41c1387
RS		 6151 emit_use (tmp_reg);
6152 emit_use (adj_reg);
57d38024 6153 return;
726d4cb7 6154 }
fa5322fa 6155 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
f3cd5375
JW		 6156
6157 /* If SIZE is negative, subtract the positive value.
6158 This sometimes allows a constant pool entry to be shared
6159 between prologue and epilogue code. */
6160 if (size < 0)
885c9a39 6161 {
fa5322fa 6162 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
2754d3c5 6163 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
885c9a39
JR		 6164 }
6165 else
6166 {
fa5322fa 6167 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
2754d3c5 6168 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
885c9a39 6169 }
fada1961 6170 if (! epilogue_p)
b757d36f
KK		 6171 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
6172 gen_rtx_SET (VOIDmode, reg,
6173 gen_rtx_PLUS (SImode, reg,
6174 GEN_INT (size))));
8aa2a305 6175 }
8aa2a305
JW		 6176 }
6177}
6178
2754d3c5 6179static rtx
cf277499 6180frame_insn (rtx x)
2754d3c5
R		 6181{
6182 x = emit_insn (x);
6183 RTX_FRAME_RELATED_P (x) = 1;
6184 return x;
6185}
6186
8aa2a305
JW		 6187/* Output RTL to push register RN onto the stack. */
6188
2754d3c5 6189static rtx
cf277499 6190push (int rn)
8aa2a305
JW		 6191{
6192 rtx x;
225e4f43
R		 6193 if (rn == FPUL_REG)
6194 x = gen_push_fpul ();
7144b2d8
DD		 6195 else if (rn == FPSCR_REG)
6196 x = gen_push_fpscr ();
157371cf 6197 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
104ee20b 6198 && FP_OR_XD_REGISTER_P (rn))
225e4f43 6199 {
104ee20b 6200 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
d042370e 6201 return NULL_RTX;
c5c76735 6202 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
225e4f43 6203 }
3a8699c7 6204 else if (TARGET_SH2E && FP_REGISTER_P (rn))
c5c76735 6205 x = gen_push_e (gen_rtx_REG (SFmode, rn));
1a95a963 6206 else
c5c76735 6207 x = gen_push (gen_rtx_REG (SImode, rn));
1a95a963 6208
2754d3c5 6209 x = frame_insn (x);
b757d36f 6210 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
2754d3c5 6211 return x;
8aa2a305
JW		 6212}
6213
6214/* Output RTL to pop register RN from the stack. */
6215
6216static void
cf277499 6217pop (int rn)
8aa2a305
JW		 6218{
6219 rtx x;
225e4f43
R		 6220 if (rn == FPUL_REG)
6221 x = gen_pop_fpul ();
7144b2d8
DD		 6222 else if (rn == FPSCR_REG)
6223 x = gen_pop_fpscr ();
157371cf 6224 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
104ee20b 6225 && FP_OR_XD_REGISTER_P (rn))
225e4f43 6226 {
104ee20b 6227 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
225e4f43 6228 return;
c5c76735 6229 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
225e4f43 6230 }
3a8699c7 6231 else if (TARGET_SH2E && FP_REGISTER_P (rn))
c5c76735 6232 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
1a95a963 6233 else
c5c76735 6234 x = gen_pop (gen_rtx_REG (SImode, rn));
f676971a 6235
1245df60 6236 x = emit_insn (x);
b757d36f 6237 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
8aa2a305
JW		 6238}
6239
1245df60 6240/* Generate code to push the regs specified in the mask. */
8aa2a305
JW		 6241
6242static void
cf277499 6243push_regs (HARD_REG_SET *mask, int interrupt_handler)
8aa2a305 6244{
5c7cafa8 6245 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
ac55736a 6246 int skip_fpscr = 0;
8aa2a305 6247
1245df60
R		 6248 /* Push PR last; this gives better latencies after the prologue, and
6249 candidates for the return delay slot when there are no general
6250 registers pushed. */
5c7cafa8 6251 for (; i < FIRST_PSEUDO_REGISTER; i++)
ac55736a
R		 6252 {
6253 /* If this is an interrupt handler, and the SZ bit varies,
6254 and we have to push any floating point register, we need
6255 to switch to the correct precision first. */
6256 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
56b138ae 6257 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
ac55736a
R		 6258 {
6259 HARD_REG_SET unsaved;
6260
6261 push (FPSCR_REG);
832a3292 6262 COMPL_HARD_REG_SET (unsaved, *mask);
ac55736a
R		 6263 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
6264 skip_fpscr = 1;
6265 }
6266 if (i != PR_REG
6267 && (i != FPSCR_REG || ! skip_fpscr)
6268 && TEST_HARD_REG_BIT (*mask, i))
561642fa
AP		 6269 {
6270 /* If the ISR has RESBANK attribute assigned, don't push any of
6271 the following registers - R0-R14, MACH, MACL and GBR. */
6272 if (! (sh_cfun_resbank_handler_p ()
6273 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
6274 || i == MACH_REG
6275 || i == MACL_REG
6276 || i == GBR_REG)))
6277 push (i);
6278 }
ac55736a 6279 }
5c7cafa8
CB		 6280
6281 /* Push banked registers last to improve delay slot opportunities. */
6282 if (interrupt_handler)
6283 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6284 if (TEST_HARD_REG_BIT (*mask, i))
6285 push (i);
6286
561642fa
AP		 6287 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6288 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
1245df60 6289 push (PR_REG);
8aa2a305
JW		 6290}
6291
fe3ad572
SC		 6292/* Calculate how much extra space is needed to save all callee-saved
6293 target registers.
6294 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6295
6296static int
6297shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
6298{
6299 int reg;
6300 int stack_space = 0;
6301 int interrupt_handler = sh_cfun_interrupt_handler_p ();
6302
6303 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
62164eb4 6304 if ((! call_really_used_regs[reg] || interrupt_handler)
fe3ad572
SC		 6305 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6306 /* Leave space to save this target register on the stack,
24746a42 6307 in case target register allocation wants to use it. */
fe3ad572
SC		 6308 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6309 return stack_space;
6310}
f676971a 6311
fe3ad572
SC		 6312/* Decide whether we should reserve space for callee-save target registers,
6313 in case target register allocation wants to use them. REGS_SAVED is
6314 the space, in bytes, that is already required for register saves.
6315 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6316
6317static int
6318shmedia_reserve_space_for_target_registers_p (int regs_saved,
6319 HARD_REG_SET *live_regs_mask)
6320{
6321 if (optimize_size)
6322 return 0;
6323 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
6324}
6325
6326/* Decide how much space to reserve for callee-save target registers
6327 in case target register allocation wants to use them.
6328 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6329
6330static int
6331shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
6332{
6333 if (shmedia_space_reserved_for_target_registers)
6334 return shmedia_target_regs_stack_space (live_regs_mask);
6335 else
6336 return 0;
6337}
6338
8aa2a305 6339/* Work out the registers which need to be saved, both as a mask and a
490dbac7 6340 count of saved words. Return the count.
8aa2a305
JW		 6341
6342 If doing a pragma interrupt function, then push all regs used by the
6343 function, and if we call another function (we can tell by looking at PR),
6344 make sure that all the regs it clobbers are safe too. */
6345
490dbac7 6346static int
cf277499 6347calc_live_regs (HARD_REG_SET *live_regs_mask)
8aa2a305 6348{
0ef2c525 6349 unsigned int reg;
1245df60 6350 int count;
a6ab9fc0
R		 6351 tree attrs;
6352 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6353 bool nosave_low_regs;
fada1961 6354 int pr_live, has_call;
157131d7 6355
a6ab9fc0
R		 6356 attrs = DECL_ATTRIBUTES (current_function_decl);
6357 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6358 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6359 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6360 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
8aa2a305 6361
fada1961 6362 CLEAR_HARD_REG_SET (*live_regs_mask);
157371cf 6363 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
6fb5fa3c 6364 && df_regs_ever_live_p (FPSCR_REG))
c0fb94d7 6365 target_flags &= ~MASK_FPU_SINGLE;
225e4f43 6366 /* If we can save a lot of saves by switching to double mode, do that. */
157371cf 6367 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
225e4f43 6368 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6fb5fa3c 6369 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
62164eb4 6370 && (! call_really_used_regs[reg]
a6ab9fc0 6371 || interrupt_handler)
225e4f43
R		 6372 && ++count > 2)
6373 {
c0fb94d7 6374 target_flags &= ~MASK_FPU_SINGLE;
225e4f43
R		 6375 break;
6376 }
9d7ed806
R		 6377 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6378 knows how to use it. That means the pseudo originally allocated for
6379 the initial value can become the PR_MEDIA_REG hard register, as seen for
6380 execute/20010122-1.c:test9. */
6381 if (TARGET_SHMEDIA)
7d73a2ba
R		 6382 /* ??? this function is called from initial_elimination_offset, hence we
6383 can't use the result of sh_media_register_for_return here. */
97b3d0f0 6384 pr_live = sh_pr_n_sets ();
9d7ed806
R		 6385 else
6386 {
6387 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
6388 pr_live = (pr_initial
f3536097 6389 ? (!REG_P (pr_initial)
29db2a1e 6390 || REGNO (pr_initial) != (PR_REG))
6fb5fa3c 6391 : df_regs_ever_live_p (PR_REG));
7d73a2ba
R		 6392 /* For Shcompact, if not optimizing, we end up with a memory reference
6393 using the return address pointer for __builtin_return_address even
6394 though there is no actual need to put the PR register on the stack. */
6fb5fa3c 6395 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
9d7ed806 6396 }
fa5322fa
AO		 6397 /* Force PR to be live if the prologue has to call the SHmedia
6398 argument decoder or register saver. */
6399 if (TARGET_SHCOMPACT
38173d38 6400 && ((crtl->args.info.call_cookie
fa5322fa 6401 & ~ CALL_COOKIE_RET_TRAMP (1))
e3b5732b 6402 || crtl->saves_all_registers))
fa5322fa 6403 pr_live = 1;
fada1961 6404 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
0ef2c525 6405 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
8aa2a305 6406 {
97b3d0f0 6407 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
3007d592 6408 ? pr_live
a6ab9fc0 6409 : interrupt_handler
1245df60 6410 ? (/* Need to save all the regs ever live. */
6fb5fa3c 6411 (df_regs_ever_live_p (reg)
62164eb4
R		 6412 || (call_really_used_regs[reg]
6413 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
6414 || reg == PIC_OFFSET_TABLE_REGNUM)
fada1961 6415 && has_call)
a6ab9fc0
R		 6416 || (TARGET_SHMEDIA && has_call
6417 && REGISTER_NATURAL_MODE (reg) == SImode
fada1961 6418 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
1245df60
R		 6419 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
6420 && reg != RETURN_ADDRESS_POINTER_REGNUM
7144b2d8
DD		 6421 && reg != T_REG && reg != GBR_REG
6422 /* Push fpscr only on targets which have FPU */
6423 && (reg != FPSCR_REG || TARGET_FPU_ANY))
1245df60 6424 : (/* Only push those regs which are used and need to be saved. */
180bde4f
RS		 6425 (TARGET_SHCOMPACT
6426 && flag_pic
38173d38 6427 && crtl->args.info.call_cookie
0ef2c525 6428 && reg == PIC_OFFSET_TABLE_REGNUM)
6fb5fa3c 6429 || (df_regs_ever_live_p (reg)
9fdcdc74
KK		 6430 && ((!call_really_used_regs[reg]
6431 && !(reg != PIC_OFFSET_TABLE_REGNUM
6432 && fixed_regs[reg] && call_used_regs[reg]))
a6ab9fc0 6433 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
e3b5732b 6434 || (crtl->calls_eh_return
0ef2c525
KK		 6435 && (reg == EH_RETURN_DATA_REGNO (0)
6436 || reg == EH_RETURN_DATA_REGNO (1)
6437 || reg == EH_RETURN_DATA_REGNO (2)
6438 || reg == EH_RETURN_DATA_REGNO (3)))
61f71b34 6439 || ((reg == MACL_REG || reg == MACH_REG)
6fb5fa3c 6440 && df_regs_ever_live_p (reg)
61f71b34
DD		 6441 && sh_cfun_attr_renesas_p ())
6442 ))
8aa2a305 6443 {
490dbac7 6444 SET_HARD_REG_BIT (*live_regs_mask, reg);
fa5322fa
AO		 6445 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6446
157371cf 6447 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
fa5322fa 6448 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
eda44c78 6449 {
104ee20b 6450 if (FP_REGISTER_P (reg))
eda44c78 6451 {
6fb5fa3c 6452 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
eda44c78 6453 {
490dbac7 6454 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
fa5322fa 6455 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
eda44c78
R		 6456 }
6457 }
fa5322fa 6458 else if (XD_REGISTER_P (reg))
eda44c78
R		 6459 {
6460 /* Must switch to double mode to access these registers. */
c0fb94d7 6461 target_flags &= ~MASK_FPU_SINGLE;
eda44c78
R		 6462 }
6463 }
8aa2a305 6464 }
a6ab9fc0
R		 6465 if (nosave_low_regs && reg == R8_REG)
6466 break;
8aa2a305 6467 }
fe3ad572
SC		 6468 /* If we have a target register optimization pass after prologue / epilogue
6469 threading, we need to assume all target registers will be live even if
6470 they aren't now. */
6471 if (flag_branch_target_load_optimize2
6472 && TARGET_SAVE_ALL_TARGET_REGS
6473 && shmedia_space_reserved_for_target_registers)
6474 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
62164eb4 6475 if ((! call_really_used_regs[reg] || interrupt_handler)
fe3ad572
SC		 6476 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6477 {
6478 SET_HARD_REG_BIT (*live_regs_mask, reg);
6479 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6480 }
fada1961
R		 6481 /* If this is an interrupt handler, we don't have any call-clobbered
6482 registers we can conveniently use for target register save/restore.
6483 Make sure we save at least one general purpose register when we need
6484 to save target registers. */
6485 if (interrupt_handler
56b138ae
RS		 6486 && hard_reg_set_intersect_p (*live_regs_mask,
6487 reg_class_contents[TARGET_REGS])
6488 && ! hard_reg_set_intersect_p (*live_regs_mask,
6489 reg_class_contents[GENERAL_REGS]))
fada1961
R		 6490 {
6491 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6492 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6493 }
8aa2a305 6494
490dbac7 6495 return count;
8aa2a305
JW		 6496}
6497
6498/* Code to generate prologue and epilogue sequences */
b9654711 6499
a93d1ba2 6500/* PUSHED is the number of bytes that are being pushed on the
0ad913af
R		 6501 stack for register saves. Return the frame size, padded
6502 appropriately so that the stack stays properly aligned. */
e5f8d4c0 6503static HOST_WIDE_INT
cf277499 6504rounded_frame_size (int pushed)
e5f8d4c0
R		 6505{
6506 HOST_WIDE_INT size = get_frame_size ();
6507 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6508
c5b9ef02 6509 return ((size + pushed + align - 1) & -align) - pushed;
e5f8d4c0
R		 6510}
6511
fa5322fa
AO		 6512/* Choose a call-clobbered target-branch register that remains
6513 unchanged along the whole function. We set it up as the return
6514 value in the prologue. */
6515int
cf277499 6516sh_media_register_for_return (void)
fa5322fa
AO		 6517{
6518 int regno;
6519 int tr0_used;
6520
6521 if (! current_function_is_leaf)
6522 return -1;
fada1961
R		 6523 if (lookup_attribute ("interrupt_handler",
6524 DECL_ATTRIBUTES (current_function_decl)))
6525 return -1;
73a4d10b
R		 6526 if (sh_cfun_interrupt_handler_p ())
6527 return -1;
fa5322fa 6528
6fb5fa3c 6529 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
fa5322fa
AO		 6530
6531 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6fb5fa3c 6532 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
fa5322fa
AO		 6533 return regno;
6534
6535 return -1;
6536}
6537
fada1961
R		 6538/* The maximum registers we need to save are:
6539 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6540 - 32 floating point registers (for each pair, we save none,
6541 one single precision value, or a double precision value).
6542 - 8 target registers
6543 - add 1 entry for a delimiter. */
6544#define MAX_SAVED_REGS (62+32+8)
6545
6546typedef struct save_entry_s
6547{
6548 unsigned char reg;
6549 unsigned char mode;
6550 short offset;
6551} save_entry;
6552
6553#define MAX_TEMPS 4
6554
6555/* There will be a delimiter entry with VOIDmode both at the start and the
6556 end of a filled in schedule. The end delimiter has the offset of the
6557 save with the smallest (i.e. most negative) offset. */
6558typedef struct save_schedule_s
6559{
6560 save_entry entries[MAX_SAVED_REGS + 2];
6561 int temps[MAX_TEMPS+1];
6562} save_schedule;
6563
6564/* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6565 use reverse order. Returns the last entry written to (not counting
6566 the delimiter). OFFSET_BASE is a number to be added to all offset
6567 entries. */
f676971a 6568
fada1961
R		 6569static save_entry *
6570sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6571 int offset_base)
6572{
6573 int align, i;
6574 save_entry *entry = schedule->entries;
6575 int tmpx = 0;
6576 int offset;
6577
6578 if (! current_function_interrupt)
6579 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
62164eb4 6580 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
fada1961
R		 6581 && ! FUNCTION_ARG_REGNO_P (i)
6582 && i != FIRST_RET_REG
6de9cd9a 6583 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
e3b5732b 6584 && ! (crtl->calls_eh_return
fada1961 6585 && (i == EH_RETURN_STACKADJ_REGNO
f94cef0a
KK		 6586 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6587 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
fada1961
R		 6588 schedule->temps[tmpx++] = i;
6589 entry->reg = -1;
6590 entry->mode = VOIDmode;
6591 entry->offset = offset_base;
6592 entry++;
6593 /* We loop twice: first, we save 8-byte aligned registers in the
6594 higher addresses, that are known to be aligned. Then, we
6595 proceed to saving 32-bit registers that don't need 8-byte
6596 alignment.
6597 If this is an interrupt function, all registers that need saving
6598 need to be saved in full. moreover, we need to postpone saving
6599 target registers till we have saved some general purpose registers
6600 we can then use as scratch registers. */
6601 offset = offset_base;
6602 for (align = 1; align >= 0; align--)
6603 {
6604 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6605 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6606 {
6607 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6608 int reg = i;
6609
6610 if (current_function_interrupt)
6611 {
6612 if (TARGET_REGISTER_P (i))
6613 continue;
6614 if (GENERAL_REGISTER_P (i))
6615 mode = DImode;
6616 }
6617 if (mode == SFmode && (i % 2) == 1
6618 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6619 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6620 {
6621 mode = DFmode;
6622 i--;
6623 reg--;
6624 }
6625
6626 /* If we're doing the aligned pass and this is not aligned,
6627 or we're doing the unaligned pass and this is aligned,
6628 skip it. */
6629 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6630 != align)
6631 continue;
6632
6633 if (current_function_interrupt
6634 && GENERAL_REGISTER_P (i)
6635 && tmpx < MAX_TEMPS)
6636 schedule->temps[tmpx++] = i;
6637
6638 offset -= GET_MODE_SIZE (mode);
6639 entry->reg = i;
6640 entry->mode = mode;
6641 entry->offset = offset;
6642 entry++;
6643 }
6644 if (align && current_function_interrupt)
6645 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6646 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6647 {
6648 offset -= GET_MODE_SIZE (DImode);
6649 entry->reg = i;
6650 entry->mode = DImode;
6651 entry->offset = offset;
6652 entry++;
6653 }
6654 }
6655 entry->reg = -1;
6656 entry->mode = VOIDmode;
6657 entry->offset = offset;
6658 schedule->temps[tmpx] = -1;
6659 return entry - 1;
6660}
6661
b9654711 6662void
cf277499 6663sh_expand_prologue (void)
b9654711 6664{
490dbac7 6665 HARD_REG_SET live_regs_mask;
40d2032b 6666 int d, i;
fa5322fa 6667 int d_rounding = 0;
225e4f43 6668 int save_flags = target_flags;
49616835 6669 int pretend_args;
a6ab9fc0
R		 6670 tree sp_switch_attr
6671 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
b9654711 6672
e3ba8d11 6673 current_function_interrupt = sh_cfun_interrupt_handler_p ();
552ecbd9 6674
0d7e008e 6675 /* We have pretend args if we had an object sent partially in registers
8aa2a305 6676 and partially on the stack, e.g. a large structure. */
38173d38 6677 pretend_args = crtl->args.pretend_args_size;
49616835
JR		 6678 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6679 && (NPARM_REGS(SImode)
38173d38 6680 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
49616835
JR		 6681 pretend_args = 0;
6682 output_stack_adjust (-pretend_args
38173d38 6683 - crtl->args.info.stack_regs * 8,
fada1961 6684 stack_pointer_rtx, 0, NULL);
b9654711 6685
38173d38 6686 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
2b1fd83f
AO		 6687 /* We're going to use the PIC register to load the address of the
6688 incoming-argument decoder and/or of the return trampoline from
6689 the GOT, so make sure the PIC register is preserved and
6690 initialized. */
6fb5fa3c 6691 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
2b1fd83f 6692
fa5322fa 6693 if (TARGET_SHCOMPACT
38173d38 6694 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
fa5322fa
AO		 6695 {
6696 int reg;
6697
6698 /* First, make all registers with incoming arguments that will
6699 be pushed onto the stack live, so that register renaming
6700 doesn't overwrite them. */
6701 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
38173d38 6702 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
fa5322fa
AO		 6703 >= NPARM_REGS (SImode) - reg)
6704 for (; reg < NPARM_REGS (SImode); reg++)
6705 emit_insn (gen_shcompact_preserve_incoming_args
6706 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6707 else if (CALL_COOKIE_INT_REG_GET
38173d38 6708 (crtl->args.info.call_cookie, reg) == 1)
fa5322fa
AO		 6709 emit_insn (gen_shcompact_preserve_incoming_args
6710 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6711
6712 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6713 stack_pointer_rtx);
6714 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
38173d38 6715 GEN_INT (crtl->args.info.call_cookie));
fa5322fa
AO		 6716 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6717 gen_rtx_REG (SImode, R0_REG));
6718 }
6719 else if (TARGET_SHMEDIA)
6720 {
6721 int tr = sh_media_register_for_return ();
6722
6723 if (tr >= 0)
6fb5fa3c
DB		 6724 emit_move_insn (gen_rtx_REG (DImode, tr),
6725 gen_rtx_REG (DImode, PR_MEDIA_REG));
fa5322fa
AO		 6726 }
6727
7ab56274 6728 /* Emit the code for SETUP_VARARGS. */
e3b5732b 6729 if (cfun->stdarg)
b9654711 6730 {
49616835 6731 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
1245df60 6732 {
1a95a963
JW		 6733 /* Push arg regs as if they'd been provided by caller in stack. */
6734 for (i = 0; i < NPARM_REGS(SImode); i++)
6735 {
6736 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
2754d3c5
R		 6737 rtx insn;
6738
f676971a 6739 if (i >= (NPARM_REGS(SImode)
38173d38 6740 - crtl->args.info.arg_count[(int) SH_ARG_INT]
aec373f1 6741 ))
1a95a963 6742 break;
2754d3c5 6743 insn = push (rn);
1a95a963 6744 }
1245df60 6745 }
b9654711 6746 }
1a95a963 6747
4408efce 6748 /* If we're supposed to switch stacks at function entry, do so now. */
a6ab9fc0
R		 6749 if (sp_switch_attr)
6750 {
6751 /* The argument specifies a variable holding the address of the
6752 stack the interrupt function should switch to/from at entry/exit. */
6753 const char *s
6754 = ggc_strdup (TREE_STRING_POINTER (TREE_VALUE (sp_switch_attr)));
6755 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6756
6757 emit_insn (gen_sp_switch_1 (sp_switch));
6758 }
4408efce 6759
490dbac7 6760 d = calc_live_regs (&live_regs_mask);
225e4f43
R		 6761 /* ??? Maybe we could save some switching if we can move a mode switch
6762 that already happens to be at the function start into the prologue. */
ac55736a 6763 if (target_flags != save_flags && ! current_function_interrupt)
225e4f43 6764 emit_insn (gen_toggle_sz ());
f676971a 6765
fa5322fa
AO		 6766 if (TARGET_SH5)
6767 {
fada1961
R		 6768 int offset_base, offset;
6769 rtx r0 = NULL_RTX;
fa5322fa
AO		 6770 int offset_in_r0 = -1;
6771 int sp_in_r0 = 0;
fe3ad572
SC		 6772 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6773 int total_size, save_size;
fada1961
R		 6774 save_schedule schedule;
6775 save_entry *entry;
6776 int *tmp_pnt;
6777
62164eb4 6778 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
fada1961
R		 6779 && ! current_function_interrupt)
6780 r0 = gen_rtx_REG (Pmode, R0_REG);
fe3ad572
SC		 6781
6782 /* D is the actual number of bytes that we need for saving registers,
6783 however, in initial_elimination_offset we have committed to using
6784 an additional TREGS_SPACE amount of bytes - in order to keep both
6785 addresses to arguments supplied by the caller and local variables
6786 valid, we must keep this gap. Place it between the incoming
6787 arguments and the actually saved registers in a bid to optimize
6788 locality of reference. */
6789 total_size = d + tregs_space;
6790 total_size += rounded_frame_size (total_size);
6791 save_size = total_size - rounded_frame_size (d);
6792 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
fa5322fa 6793 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
fe3ad572
SC		 6794 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6795
6796 /* If adjusting the stack in a single step costs nothing extra, do so.
6797 I.e. either if a single addi is enough, or we need a movi anyway,
6798 and we don't exceed the maximum offset range (the test for the
6799 latter is conservative for simplicity). */
6800 if (TARGET_SHMEDIA
6801 && (CONST_OK_FOR_I10 (-total_size)
6802 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6803 && total_size <= 2044)))
6804 d_rounding = total_size - save_size;
fa5322fa 6805
fada1961 6806 offset_base = d + d_rounding;
fe3ad572
SC		 6807
6808 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
fada1961 6809 0, NULL);
fa5322fa 6810
fada1961
R		 6811 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6812 tmp_pnt = schedule.temps;
6813 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6814 {
81f40b79 6815 enum machine_mode mode = (enum machine_mode) entry->mode;
0ef2c525 6816 unsigned int reg = entry->reg;
fada1961 6817 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
455786b6 6818 rtx orig_reg_rtx;
fa5322fa 6819
fada1961 6820 offset = entry->offset;
fa5322fa 6821
fada1961 6822 reg_rtx = gen_rtx_REG (mode, reg);
fa5322fa 6823
57d38024
R		 6824 mem_rtx = gen_frame_mem (mode,
6825 gen_rtx_PLUS (Pmode,
6826 stack_pointer_rtx,
6827 GEN_INT (offset)));
fa5322fa 6828
6de7a512
PB		 6829 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
6830 {
6831 gcc_assert (r0);
6832 mem_rtx = NULL_RTX;
6833 }
fa5322fa 6834
6de7a512
PB		 6835 if (HAVE_PRE_DECREMENT
6836 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6837 || mem_rtx == NULL_RTX
6838 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6839 {
6840 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
fa5322fa 6841
6de7a512 6842 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
fada1961 6843 pre_dec = NULL_RTX;
6de7a512
PB		 6844 else
6845 {
6846 mem_rtx = NULL_RTX;
6847 offset += GET_MODE_SIZE (mode);
6848 }
6849 }
fa5322fa 6850
fada1961
R		 6851 if (mem_rtx != NULL_RTX)
6852 goto addr_ok;
fa5322fa 6853
fada1961
R		 6854 if (offset_in_r0 == -1)
6855 {
6856 emit_move_insn (r0, GEN_INT (offset));
6857 offset_in_r0 = offset;
6858 }
6859 else if (offset != offset_in_r0)
6860 {
6861 emit_move_insn (r0,
6862 gen_rtx_PLUS
6863 (Pmode, r0,
6864 GEN_INT (offset - offset_in_r0)));
6865 offset_in_r0 += offset - offset_in_r0;
6866 }
f676971a 6867
fada1961
R		 6868 if (pre_dec != NULL_RTX)
6869 {
6870 if (! sp_in_r0)
fa5322fa
AO		 6871 {
6872 emit_move_insn (r0,
6873 gen_rtx_PLUS
fada1961
R		 6874 (Pmode, r0, stack_pointer_rtx));
6875 sp_in_r0 = 1;
fa5322fa 6876 }
fa5322fa 6877
fada1961
R		 6878 offset -= GET_MODE_SIZE (mode);
6879 offset_in_r0 -= GET_MODE_SIZE (mode);
fa5322fa 6880
fada1961
R		 6881 mem_rtx = pre_dec;
6882 }
6883 else if (sp_in_r0)
57d38024 6884 mem_rtx = gen_frame_mem (mode, r0);
fada1961 6885 else
57d38024
R		 6886 mem_rtx = gen_frame_mem (mode,
6887 gen_rtx_PLUS (Pmode,
6888 stack_pointer_rtx,
6889 r0));
fada1961
R		 6890
6891 /* We must not use an r0-based address for target-branch
6892 registers or for special registers without pre-dec
6893 memory addresses, since we store their values in r0
6894 first. */
f5b9e7c9
NS		 6895 gcc_assert (!TARGET_REGISTER_P (reg)
6896 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6897 || mem_rtx == pre_dec));
6898
fada1961 6899 addr_ok:
455786b6 6900 orig_reg_rtx = reg_rtx;
fada1961
R		 6901 if (TARGET_REGISTER_P (reg)
6902 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6903 && mem_rtx != pre_dec))
6904 {
6905 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
fa5322fa 6906
fada1961 6907 emit_move_insn (tmp_reg, reg_rtx);
fa5322fa 6908
fada1961
R		 6909 if (REGNO (tmp_reg) == R0_REG)
6910 {
fa5322fa
AO		 6911 offset_in_r0 = -1;
6912 sp_in_r0 = 0;
f5b9e7c9
NS		 6913 gcc_assert (!refers_to_regno_p
6914 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
fa5322fa
AO		 6915 }
6916
fada1961
R		 6917 if (*++tmp_pnt <= 0)
6918 tmp_pnt = schedule.temps;
6919
6920 reg_rtx = tmp_reg;
fa5322fa 6921 }
fada1961
R		 6922 {
6923 rtx insn;
6924
6925 /* Mark as interesting for dwarf cfi generator */
6926 insn = emit_move_insn (mem_rtx, reg_rtx);
6927 RTX_FRAME_RELATED_P (insn) = 1;
455786b6
KK		 6928 /* If we use an intermediate register for the save, we can't
6929 describe this exactly in cfi as a copy of the to-be-saved
6930 register into the temporary register and then the temporary
6931 register on the stack, because the temporary register can
6932 have a different natural size than the to-be-saved register.
6933 Thus, we gloss over the intermediate copy and pretend we do
6934 a direct save from the to-be-saved register. */
6935 if (REGNO (reg_rtx) != reg)
6936 {
b757d36f 6937 rtx set;
455786b6
KK		 6938
6939 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
b757d36f 6940 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
455786b6 6941 }
fada1961 6942
f676971a 6943 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
fada1961
R		 6944 {
6945 rtx reg_rtx = gen_rtx_REG (mode, reg);
b757d36f 6946 rtx set;
57d38024
R		 6947 rtx mem_rtx = gen_frame_mem (mode,
6948 gen_rtx_PLUS (Pmode,
6949 stack_pointer_rtx,
6950 GEN_INT (offset)));
fada1961
R		 6951
6952 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
b757d36f 6953 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
fada1961
R		 6954 }
6955 }
6956 }
fa5322fa 6957
f5b9e7c9 6958 gcc_assert (entry->offset == d_rounding);
fa5322fa
AO		 6959 }
6960 else
ac55736a 6961 push_regs (&live_regs_mask, current_function_interrupt);
1a66cd67 6962
6fb5fa3c
DB		 6963 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
6964 emit_insn (gen_GOTaddr2picreg ());
1a66cd67 6965
fa5322fa
AO		 6966 if (SHMEDIA_REGS_STACK_ADJUST ())
6967 {
fa5322fa
AO		 6968 /* This must NOT go through the PLT, otherwise mach and macl
6969 may be clobbered. */
73a4d10b
R		 6970 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6971 (TARGET_FPU_ANY
6972 ? "__GCC_push_shmedia_regs"
6973 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
fa5322fa
AO		 6974 emit_insn (gen_shmedia_save_restore_regs_compact
6975 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
6976 }
6977
ac55736a 6978 if (target_flags != save_flags && ! current_function_interrupt)
6fb5fa3c 6979 emit_insn (gen_toggle_sz ());
1a95a963 6980
225e4f43
R		 6981 target_flags = save_flags;
6982
fa5322fa 6983 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
fada1961 6984 stack_pointer_rtx, 0, NULL);
b9654711
SC		 6985
6986 if (frame_pointer_needed)
96a2347e 6987 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
fa5322fa 6988
fa5322fa 6989 if (TARGET_SHCOMPACT
38173d38 6990 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
fa5322fa
AO		 6991 {
6992 /* This must NOT go through the PLT, otherwise mach and macl
6993 may be clobbered. */
73a4d10b
R		 6994 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6995 "__GCC_shcompact_incoming_args", SFUNC_GOT);
fa5322fa
AO		 6996 emit_insn (gen_shcompact_incoming_args ());
6997 }
b9654711
SC		 6998}
6999
7000void
726d4cb7 7001sh_expand_epilogue (bool sibcall_p)
b9654711 7002{
490dbac7 7003 HARD_REG_SET live_regs_mask;
40d2032b 7004 int d, i;
fa5322fa 7005 int d_rounding = 0;
b9654711 7006
225e4f43 7007 int save_flags = target_flags;
fe3ad572 7008 int frame_size, save_size;
ac55736a 7009 int fpscr_deferred = 0;
726d4cb7 7010 int e = sibcall_p ? -1 : 1;
3d5a0820 7011
490dbac7 7012 d = calc_live_regs (&live_regs_mask);
3d5a0820 7013
fe3ad572
SC		 7014 save_size = d;
7015 frame_size = rounded_frame_size (d);
7016
7017 if (TARGET_SH5)
7018 {
7019 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
7020 int total_size;
7021 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
7022 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7023 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
7024
7025 total_size = d + tregs_space;
7026 total_size += rounded_frame_size (total_size);
7027 save_size = total_size - frame_size;
7028
7029 /* If adjusting the stack in a single step costs nothing extra, do so.
7030 I.e. either if a single addi is enough, or we need a movi anyway,
7031 and we don't exceed the maximum offset range (the test for the
7032 latter is conservative for simplicity). */
7033 if (TARGET_SHMEDIA
7034 && ! frame_pointer_needed
7035 && (CONST_OK_FOR_I10 (total_size)
7036 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
7037 && total_size <= 2044)))
7038 d_rounding = frame_size;
fa5322fa 7039
fe3ad572
SC		 7040 frame_size -= d_rounding;
7041 }
16bea517 7042
b9654711 7043 if (frame_pointer_needed)
46d81ffa 7044 {
1964788a 7045 /* We must avoid scheduling the epilogue with previous basic blocks.
47ea8d4e 7046 See PR/18032 and PR/40313. */
1964788a 7047 emit_insn (gen_blockage ());
96a2347e
KK		 7048 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
7049 &live_regs_mask);
07f5b9aa
JL		 7050
7051 /* We must avoid moving the stack pointer adjustment past code
7052 which reads from the local frame, else an interrupt could
7053 occur after the SP adjustment and clobber data in the local
7054 frame. */
7055 emit_insn (gen_blockage ());
96a2347e 7056 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
46d81ffa 7057 }
3d5a0820 7058 else if (frame_size)
07f5b9aa
JL		 7059 {
7060 /* We must avoid moving the stack pointer adjustment past code
7061 which reads from the local frame, else an interrupt could
7062 occur after the SP adjustment and clobber data in the local
7063 frame. */
7064 emit_insn (gen_blockage ());
726d4cb7 7065 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
07f5b9aa 7066 }
b9654711 7067
fa5322fa
AO		 7068 if (SHMEDIA_REGS_STACK_ADJUST ())
7069 {
73a4d10b
R		 7070 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7071 (TARGET_FPU_ANY
7072 ? "__GCC_pop_shmedia_regs"
7073 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
fa5322fa
AO		 7074 /* This must NOT go through the PLT, otherwise mach and macl
7075 may be clobbered. */
7076 emit_insn (gen_shmedia_save_restore_regs_compact
7077 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
7078 }
7079
16bea517 7080 /* Pop all the registers. */
0d7e008e 7081
ac55736a 7082 if (target_flags != save_flags && ! current_function_interrupt)
225e4f43 7083 emit_insn (gen_toggle_sz ());
fa5322fa
AO		 7084 if (TARGET_SH5)
7085 {
fada1961 7086 int offset_base, offset;
fa5322fa
AO		 7087 int offset_in_r0 = -1;
7088 int sp_in_r0 = 0;
fa5322fa 7089 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
fada1961
R		 7090 save_schedule schedule;
7091 save_entry *entry;
7092 int *tmp_pnt;
7d73a2ba 7093
fada1961
R		 7094 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
7095 offset_base = -entry[1].offset + d_rounding;
7096 tmp_pnt = schedule.temps;
7097 for (; entry->mode != VOIDmode; entry--)
7098 {
81f40b79 7099 enum machine_mode mode = (enum machine_mode) entry->mode;
fada1961
R		 7100 int reg = entry->reg;
7101 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
fa5322fa 7102
fada1961
R		 7103 offset = offset_base + entry->offset;
7104 reg_rtx = gen_rtx_REG (mode, reg);
fa5322fa 7105
57d38024
R		 7106 mem_rtx = gen_frame_mem (mode,
7107 gen_rtx_PLUS (Pmode,
7108 stack_pointer_rtx,
7109 GEN_INT (offset)));
fa5322fa 7110
6de7a512
PB		 7111 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7112 mem_rtx = NULL_RTX;
fa5322fa 7113
6de7a512
PB		 7114 if (HAVE_POST_INCREMENT
7115 && (offset == offset_in_r0
7116 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
7117 && mem_rtx == NULL_RTX)
7118 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7119 {
7120 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
fa5322fa 7121
6de7a512 7122 if (!memory_address_p (mode, XEXP (post_inc, 0)))
fada1961 7123 post_inc = NULL_RTX;
6de7a512 7124 else
fada1961 7125 mem_rtx = NULL_RTX;
6de7a512 7126 }
f676971a 7127
fada1961
R		 7128 if (mem_rtx != NULL_RTX)
7129 goto addr_ok;
fa5322fa 7130
fada1961
R		 7131 if (offset_in_r0 == -1)
7132 {
7133 emit_move_insn (r0, GEN_INT (offset));
7134 offset_in_r0 = offset;
7135 }
7136 else if (offset != offset_in_r0)
7137 {
7138 emit_move_insn (r0,
7139 gen_rtx_PLUS
7140 (Pmode, r0,
7141 GEN_INT (offset - offset_in_r0)));
7142 offset_in_r0 += offset - offset_in_r0;
7143 }
f676971a 7144
fada1961
R		 7145 if (post_inc != NULL_RTX)
7146 {
7147 if (! sp_in_r0)
fa5322fa
AO		 7148 {
7149 emit_move_insn (r0,
7150 gen_rtx_PLUS
fada1961
R		 7151 (Pmode, r0, stack_pointer_rtx));
7152 sp_in_r0 = 1;
fa5322fa 7153 }
f676971a 7154
fada1961 7155 mem_rtx = post_inc;
fa5322fa 7156
fada1961
R		 7157 offset_in_r0 += GET_MODE_SIZE (mode);
7158 }
7159 else if (sp_in_r0)
57d38024 7160 mem_rtx = gen_frame_mem (mode, r0);
fada1961 7161 else
57d38024
R		 7162 mem_rtx = gen_frame_mem (mode,
7163 gen_rtx_PLUS (Pmode,
7164 stack_pointer_rtx,
7165 r0));
fa5322fa 7166
f5b9e7c9
NS		 7167 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7168 || mem_rtx == post_inc);
fa5322fa 7169
fada1961
R		 7170 addr_ok:
7171 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7172 && mem_rtx != post_inc)
7173 {
7174 insn = emit_move_insn (r0, mem_rtx);
7175 mem_rtx = r0;
7176 }
7177 else if (TARGET_REGISTER_P (reg))
7178 {
7179 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
7180
7181 /* Give the scheduler a bit of freedom by using up to
7182 MAX_TEMPS registers in a round-robin fashion. */
7183 insn = emit_move_insn (tmp_reg, mem_rtx);
7184 mem_rtx = tmp_reg;
7185 if (*++tmp_pnt < 0)
7186 tmp_pnt = schedule.temps;
fa5322fa
AO		 7187 }
7188
fada1961 7189 insn = emit_move_insn (reg_rtx, mem_rtx);
fada1961
R		 7190 }
7191
f5b9e7c9 7192 gcc_assert (entry->offset + offset_base == d + d_rounding);
fa5322fa 7193 }
fe3ad572 7194 else /* ! TARGET_SH5 */
b9654711 7195 {
5c7cafa8
CB		 7196 int last_reg;
7197
fe3ad572 7198 save_size = 0;
561642fa
AP		 7199 /* For an ISR with RESBANK attribute assigned, don't pop PR
7200 register. */
7201 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
7202 && !sh_cfun_resbank_handler_p ())
6fb5fa3c
DB		 7203 {
7204 if (!frame_pointer_needed)
7205 emit_insn (gen_blockage ());
7206 pop (PR_REG);
7207 }
5c7cafa8
CB		 7208
7209 /* Banked registers are poped first to avoid being scheduled in the
7210 delay slot. RTE switches banks before the ds instruction. */
7211 if (current_function_interrupt)
7212 {
7213 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
7214 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7215 pop (LAST_BANKED_REG - i);
7216
7217 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
7218 }
7219 else
7220 last_reg = FIRST_PSEUDO_REGISTER;
7221
7222 for (i = 0; i < last_reg; i++)
fe3ad572
SC		 7223 {
7224 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
f676971a 7225
fe3ad572 7226 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
56b138ae
RS		 7227 && hard_reg_set_intersect_p (live_regs_mask,
7228 reg_class_contents[DF_REGS]))
fe3ad572 7229 fpscr_deferred = 1;
561642fa
AP		 7230 /* For an ISR with RESBANK attribute assigned, don't pop
7231 following registers, R0-R14, MACH, MACL and GBR. */
7232 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
7233 && ! (sh_cfun_resbank_handler_p ()
7234 && ((j >= FIRST_GENERAL_REG
7235 && j < LAST_GENERAL_REG)
7236 || j == MACH_REG
7237 || j == MACL_REG
7238 || j == GBR_REG)))
fe3ad572 7239 pop (j);
5c7cafa8 7240
fe3ad572
SC		 7241 if (j == FIRST_FP_REG && fpscr_deferred)
7242 pop (FPSCR_REG);
fe3ad572 7243 }
b9654711 7244 }
ac55736a 7245 if (target_flags != save_flags && ! current_function_interrupt)
225e4f43
R		 7246 emit_insn (gen_toggle_sz ());
7247 target_flags = save_flags;
b9654711 7248
38173d38 7249 output_stack_adjust (crtl->args.pretend_args_size
fe3ad572 7250 + save_size + d_rounding
38173d38 7251 + crtl->args.info.stack_regs * 8,
726d4cb7 7252 stack_pointer_rtx, e, NULL);
4408efce 7253
e3b5732b 7254 if (crtl->calls_eh_return)
4977bab6
ZW		 7255 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
7256 EH_RETURN_STACKADJ_RTX));
7257
4408efce 7258 /* Switch back to the normal stack if necessary. */
a6ab9fc0 7259 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
4408efce 7260 emit_insn (gen_sp_switch_2 ());
89d4bc35
AO		 7261
7262 /* Tell flow the insn that pops PR isn't dead. */
fa5322fa
AO		 7263 /* PR_REG will never be live in SHmedia mode, and we don't need to
7264 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
7265 by the return pattern. */
490dbac7 7266 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
c41c1387 7267 emit_use (gen_rtx_REG (SImode, PR_REG));
b9654711
SC		 7268}
7269
afbc2905
R		 7270static int sh_need_epilogue_known = 0;
7271
7272int
cf277499 7273sh_need_epilogue (void)
afbc2905
R		 7274{
7275 if (! sh_need_epilogue_known)
7276 {
7277 rtx epilogue;
7278
7279 start_sequence ();
726d4cb7 7280 sh_expand_epilogue (0);
2f937369 7281 epilogue = get_insns ();
afbc2905 7282 end_sequence ();
2f937369 7283 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
afbc2905
R		 7284 }
7285 return sh_need_epilogue_known > 0;
7286}
7287
4977bab6
ZW		 7288/* Emit code to change the current function's return address to RA.
7289 TEMP is available as a scratch register, if needed. */
7290
7291void
cf277499 7292sh_set_return_address (rtx ra, rtx tmp)
4977bab6 7293{
490dbac7 7294 HARD_REG_SET live_regs_mask;
4977bab6 7295 int d;
4977bab6
ZW		 7296 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7297 int pr_offset;
7298
490dbac7 7299 d = calc_live_regs (&live_regs_mask);
4977bab6
ZW		 7300
7301 /* If pr_reg isn't life, we can set it (or the register given in
7302 sh_media_register_for_return) directly. */
490dbac7 7303 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
4977bab6
ZW		 7304 {
7305 rtx rr;
7306
7307 if (TARGET_SHMEDIA)
7308 {
7309 int rr_regno = sh_media_register_for_return ();
7310
7311 if (rr_regno < 0)
7312 rr_regno = pr_reg;
7313
7314 rr = gen_rtx_REG (DImode, rr_regno);
7315 }
7316 else
7317 rr = gen_rtx_REG (SImode, pr_reg);
7318
7319 emit_insn (GEN_MOV (rr, ra));
7320 /* Tell flow the register for return isn't dead. */
c41c1387 7321 emit_use (rr);
4977bab6
ZW		 7322 return;
7323 }
7324
7325 if (TARGET_SH5)
7326 {
4977bab6 7327 int offset;
fada1961
R		 7328 save_schedule schedule;
7329 save_entry *entry;
f676971a 7330
fada1961
R		 7331 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
7332 offset = entry[1].offset;
7333 for (; entry->mode != VOIDmode; entry--)
7334 if (entry->reg == pr_reg)
7335 goto found;
4977bab6
ZW		 7336
7337 /* We can't find pr register. */
f5b9e7c9 7338 gcc_unreachable ();
4977bab6
ZW		 7339
7340 found:
fada1961
R		 7341 offset = entry->offset - offset;
7342 pr_offset = (rounded_frame_size (d) + offset
4977bab6
ZW		 7343 + SHMEDIA_REGS_STACK_ADJUST ());
7344 }
7345 else
fada1961 7346 pr_offset = rounded_frame_size (d);
4977bab6
ZW		 7347
7348 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
96a2347e 7349 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
4977bab6 7350
57d38024 7351 tmp = gen_frame_mem (Pmode, tmp);
4977bab6 7352 emit_insn (GEN_MOV (tmp, ra));
7f9a14e3
KK		 7353 /* Tell this store isn't dead. */
7354 emit_use (tmp);
4977bab6
ZW		 7355}
7356
8aa2a305
JW		 7357/* Clear variables at function end. */
7358
08c148a8 7359static void
cf277499
SB		 7360sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7361 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8aa2a305 7362{
afbc2905 7363 sh_need_epilogue_known = 0;
8aa2a305
JW		 7364}
7365
61f71b34 7366static rtx
cf277499 7367sh_builtin_saveregs (void)
1a95a963 7368{
1a95a963 7369 /* First unnamed integer register. */
38173d38 7370 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
1a95a963
JW		 7371 /* Number of integer registers we need to save. */
7372 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7373 /* First unnamed SFmode float reg */
38173d38 7374 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
1a95a963
JW		 7375 /* Number of SFmode float regs to save. */
7376 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
318881c0 7377 rtx regbuf, fpregs;
ba4828e0 7378 int bufsize, regno;
4862826d 7379 alias_set_type alias_set;
1a95a963 7380
fa5322fa
AO		 7381 if (TARGET_SH5)
7382 {
7383 if (n_intregs)
7384 {
7385 int pushregs = n_intregs;
7386
7387 while (pushregs < NPARM_REGS (SImode) - 1
7388 && (CALL_COOKIE_INT_REG_GET
38173d38 7389 (crtl->args.info.call_cookie,
fa5322fa
AO		 7390 NPARM_REGS (SImode) - pushregs)
7391 == 1))
7392 {
38173d38 7393 crtl->args.info.call_cookie
fa5322fa
AO		 7394 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7395 - pushregs, 1);
7396 pushregs++;
7397 }
7398
7399 if (pushregs == NPARM_REGS (SImode))
38173d38 7400 crtl->args.info.call_cookie
fa5322fa
AO		 7401 |= (CALL_COOKIE_INT_REG (0, 1)
7402 | CALL_COOKIE_STACKSEQ (pushregs - 1));
7403 else
38173d38 7404 crtl->args.info.call_cookie
fa5322fa
AO		 7405 |= CALL_COOKIE_STACKSEQ (pushregs);
7406
38173d38 7407 crtl->args.pretend_args_size += 8 * n_intregs;
fa5322fa
AO		 7408 }
7409 if (TARGET_SHCOMPACT)
7410 return const0_rtx;
7411 }
f676971a 7412
3a8699c7 7413 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
fa5322fa
AO		 7414 {
7415 error ("__builtin_saveregs not supported by this subtarget");
7416 return const0_rtx;
7417 }
7418
7419 if (TARGET_SHMEDIA)
7420 n_floatregs = 0;
7421
6f317ef3 7422 /* Allocate block of memory for the regs. */
1a95a963
JW		 7423 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7424 Or can assign_stack_local accept a 0 SIZE argument? */
7425 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7426
fa5322fa 7427 if (TARGET_SHMEDIA)
57d38024 7428 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
f78ec36a
R		 7429 else if (n_floatregs & 1)
7430 {
7431 rtx addr;
7432
7433 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7434 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7435 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7436 regbuf = change_address (regbuf, BLKmode, addr);
7437 }
a11c004b
R		 7438 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7439 {
7440 rtx addr, mask;
7441
7442 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7443 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7444 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7445 emit_insn (gen_andsi3 (addr, addr, mask));
7446 regbuf = change_address (regbuf, BLKmode, addr);
7447 }
fa5322fa 7448 else
a11c004b 7449 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
514066a1 7450 alias_set = get_varargs_alias_set ();
ba4828e0 7451 set_mem_alias_set (regbuf, alias_set);
1a95a963
JW		 7452
7453 /* Save int args.
7454 This is optimized to only save the regs that are necessary. Explicitly
7455 named args need not be saved. */
7456 if (n_intregs > 0)
7457 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
f4ef873c
RK		 7458 adjust_address (regbuf, BLKmode,
7459 n_floatregs * UNITS_PER_WORD),
c6b97fac 7460 n_intregs);
1a95a963 7461
fa5322fa
AO		 7462 if (TARGET_SHMEDIA)
7463 /* Return the address of the regbuf. */
7464 return XEXP (regbuf, 0);
7465
1a95a963
JW		 7466 /* Save float args.
7467 This is optimized to only save the regs that are necessary. Explicitly
7468 named args need not be saved.
7469 We explicitly build a pointer to the buffer because it halves the insn
7470 count when not optimizing (otherwise the pointer is built for each reg
1245df60
R		 7471 saved).
7472 We emit the moves in reverse order so that we can use predecrement. */
1a95a963 7473
7d9c5aa1
R		 7474 fpregs = copy_to_mode_reg (Pmode,
7475 plus_constant (XEXP (regbuf, 0),
7476 n_floatregs * UNITS_PER_WORD));
157371cf 7477 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
225e4f43 7478 {
514066a1 7479 rtx mem;
225e4f43
R		 7480 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7481 {
7482 emit_insn (gen_addsi3 (fpregs, fpregs,
7483 GEN_INT (-2 * UNITS_PER_WORD)));
57d38024 7484 mem = change_address (regbuf, DFmode, fpregs);
f676971a 7485 emit_move_insn (mem,
c0d4e710 7486 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
225e4f43
R		 7487 }
7488 regno = first_floatreg;
7489 if (regno & 1)
7490 {
832a3292 7491 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
57d38024 7492 mem = change_address (regbuf, SFmode, fpregs);
514066a1 7493 emit_move_insn (mem,
c0d4e710 7494 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
225e4f43
R		 7495 - (TARGET_LITTLE_ENDIAN != 0)));
7496 }
7497 }
7498 else
1245df60
R		 7499 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7500 {
514066a1 7501 rtx mem;
ba4828e0 7502
832a3292 7503 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
57d38024 7504 mem = change_address (regbuf, SFmode, fpregs);
514066a1 7505 emit_move_insn (mem,
c5c76735 7506 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
1245df60 7507 }
1a95a963
JW		 7508
7509 /* Return the address of the regbuf. */
7510 return XEXP (regbuf, 0);
7511}
7512
514066a1
RH		 7513/* Define the `__builtin_va_list' type for the ABI. */
7514
c35d187f
RH		 7515static tree
7516sh_build_builtin_va_list (void)
514066a1
RH		 7517{
7518 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7519 tree record;
7520
61f71b34
DD		 7521 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7522 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
514066a1
RH		 7523 return ptr_type_node;
7524
5d27ef94 7525 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
514066a1 7526
4c4bde29
AH		 7527 f_next_o = build_decl (BUILTINS_LOCATION,
7528 FIELD_DECL, get_identifier ("__va_next_o"),
514066a1 7529 ptr_type_node);
4c4bde29
AH		 7530 f_next_o_limit = build_decl (BUILTINS_LOCATION,
7531 FIELD_DECL,
514066a1
RH		 7532 get_identifier ("__va_next_o_limit"),
7533 ptr_type_node);
4c4bde29
AH		 7534 f_next_fp = build_decl (BUILTINS_LOCATION,
7535 FIELD_DECL, get_identifier ("__va_next_fp"),
514066a1 7536 ptr_type_node);
4c4bde29
AH		 7537 f_next_fp_limit = build_decl (BUILTINS_LOCATION,
7538 FIELD_DECL,
514066a1
RH		 7539 get_identifier ("__va_next_fp_limit"),
7540 ptr_type_node);
4c4bde29
AH		 7541 f_next_stack = build_decl (BUILTINS_LOCATION,
7542 FIELD_DECL, get_identifier ("__va_next_stack"),
514066a1
RH		 7543 ptr_type_node);
7544
7545 DECL_FIELD_CONTEXT (f_next_o) = record;
7546 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7547 DECL_FIELD_CONTEXT (f_next_fp) = record;
7548 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7549 DECL_FIELD_CONTEXT (f_next_stack) = record;
7550
7551 TYPE_FIELDS (record) = f_next_o;
7552 TREE_CHAIN (f_next_o) = f_next_o_limit;
7553 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7554 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7555 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7556
7557 layout_type (record);
7558
7559 return record;
7560}
7561
7562/* Implement `va_start' for varargs and stdarg. */
7563
d7bd8aeb 7564static void
cf277499 7565sh_va_start (tree valist, rtx nextarg)
514066a1
RH		 7566{
7567 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7568 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7569 tree t, u;
7570 int nfp, nint;
7571
fa5322fa
AO		 7572 if (TARGET_SH5)
7573 {
7574 expand_builtin_saveregs ();
e5faf155 7575 std_expand_builtin_va_start (valist, nextarg);
fa5322fa
AO		 7576 return;
7577 }
7578
61f71b34
DD		 7579 if ((! TARGET_SH2E && ! TARGET_SH4)
7580 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
514066a1 7581 {
e5faf155 7582 std_expand_builtin_va_start (valist, nextarg);
514066a1
RH		 7583 return;
7584 }
7585
7586 f_next_o = TYPE_FIELDS (va_list_type_node);
7587 f_next_o_limit = TREE_CHAIN (f_next_o);
7588 f_next_fp = TREE_CHAIN (f_next_o_limit);
7589 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7590 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7591
47a25a46 7592 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
44de5aeb 7593 NULL_TREE);
47a25a46
RG		 7594 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7595 valist, f_next_o_limit, NULL_TREE);
7596 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7597 NULL_TREE);
7598 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7599 valist, f_next_fp_limit, NULL_TREE);
7600 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7601 valist, f_next_stack, NULL_TREE);
514066a1
RH		 7602
7603 /* Call __builtin_saveregs. */
5be014d5
AP		 7604 u = make_tree (sizetype, expand_builtin_saveregs ());
7605 u = fold_convert (ptr_type_node, u);
726a989a 7606 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
514066a1
RH		 7607 TREE_SIDE_EFFECTS (t) = 1;
7608 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7609
38173d38 7610 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
514066a1
RH		 7611 if (nfp < 8)
7612 nfp = 8 - nfp;
7613 else
7614 nfp = 0;
5be014d5
AP		 7615 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7616 size_int (UNITS_PER_WORD * nfp));
726a989a 7617 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
514066a1
RH		 7618 TREE_SIDE_EFFECTS (t) = 1;
7619 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7620
726a989a 7621 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
514066a1
RH		 7622 TREE_SIDE_EFFECTS (t) = 1;
7623 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7624
38173d38 7625 nint = crtl->args.info.arg_count[SH_ARG_INT];
514066a1
RH		 7626 if (nint < 4)
7627 nint = 4 - nint;
7628 else
7629 nint = 0;
5be014d5
AP		 7630 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7631 size_int (UNITS_PER_WORD * nint));
726a989a 7632 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
514066a1
RH		 7633 TREE_SIDE_EFFECTS (t) = 1;
7634 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7635
7636 u = make_tree (ptr_type_node, nextarg);
726a989a 7637 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
514066a1
RH		 7638 TREE_SIDE_EFFECTS (t) = 1;
7639 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7640}
7641
917f1b7e 7642/* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
21bdb106
JR		 7643 member, return it. */
7644static tree
7645find_sole_member (tree type)
7646{
7647 tree field, member = NULL_TREE;
7648
7649 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7650 {
7651 if (TREE_CODE (field) != FIELD_DECL)
7652 continue;
7653 if (!DECL_SIZE (field))
7654 return NULL_TREE;
7655 if (integer_zerop (DECL_SIZE (field)))
7656 continue;
7657 if (member)
7658 return NULL_TREE;
7659 member = field;
7660 }
7661 return member;
7662}
514066a1
RH		 7663/* Implement `va_arg'. */
7664
5fac2ed2 7665static tree
726a989a
RB		 7666sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7667 gimple_seq *post_p ATTRIBUTE_UNUSED)
514066a1
RH		 7668{
7669 HOST_WIDE_INT size, rsize;
318881c0 7670 tree tmp, pptr_type_node;
0ef2c525 7671 tree addr, lab_over = NULL, result = NULL;
03603192 7672 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
11160b58 7673 tree eff_type;
5fac2ed2
RH		 7674
7675 if (pass_by_ref)
7676 type = build_pointer_type (type);
514066a1
RH		 7677
7678 size = int_size_in_bytes (type);
7679 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7680 pptr_type_node = build_pointer_type (ptr_type_node);
7681
61f71b34
DD		 7682 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7683 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
514066a1
RH		 7684 {
7685 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7686 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7687 int pass_as_float;
5fac2ed2 7688 tree lab_false;
21bdb106 7689 tree member;
514066a1
RH		 7690
7691 f_next_o = TYPE_FIELDS (va_list_type_node);
7692 f_next_o_limit = TREE_CHAIN (f_next_o);
7693 f_next_fp = TREE_CHAIN (f_next_o_limit);
7694 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7695 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7696
47a25a46
RG		 7697 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7698 NULL_TREE);
7699 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7700 valist, f_next_o_limit, NULL_TREE);
7701 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7702 valist, f_next_fp, NULL_TREE);
7703 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7704 valist, f_next_fp_limit, NULL_TREE);
7705 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7706 valist, f_next_stack, NULL_TREE);
514066a1 7707
6d1cb95f
R		 7708 /* Structures with a single member with a distinct mode are passed
7709 like their member. This is relevant if the latter has a REAL_TYPE
7710 or COMPLEX_TYPE type. */
11160b58
R		 7711 eff_type = type;
7712 while (TREE_CODE (eff_type) == RECORD_TYPE
7713 && (member = find_sole_member (eff_type))
21bdb106
JR		 7714 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7715 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7716 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
c26104e4 7717 {
21bdb106 7718 tree field_type = TREE_TYPE (member);
c26104e4 7719
11160b58
R		 7720 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7721 eff_type = field_type;
c26104e4 7722 else
8a2209bf 7723 {
11160b58 7724 gcc_assert ((TYPE_ALIGN (eff_type)
21bdb106 7725 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
11160b58 7726 || (TYPE_ALIGN (eff_type)
21bdb106
JR		 7727 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7728 break;
8a2209bf 7729 }
c26104e4 7730 }
5fac2ed2 7731
bdf57c40 7732 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
514066a1 7733 {
11160b58
R		 7734 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7735 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7736 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
514066a1
RH		 7737 && size <= 16));
7738 }
7739 else
7740 {
11160b58 7741 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
514066a1
RH		 7742 }
7743
5fac2ed2 7744 addr = create_tmp_var (pptr_type_node, NULL);
4c4bde29
AH		 7745 lab_false = create_artificial_label (UNKNOWN_LOCATION);
7746 lab_over = create_artificial_label (UNKNOWN_LOCATION);
514066a1 7747
5fac2ed2 7748 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
6d1cb95f 7749
514066a1
RH		 7750 if (pass_as_float)
7751 {
a11c004b
R		 7752 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7753 tree cmp;
11160b58 7754 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
f78ec36a 7755
8c54989a
KK		 7756 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
7757 gimplify_assign (unshare_expr (addr), tmp, pre_p);
a11c004b 7758
8c54989a 7759 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
a11c004b
R		 7760 tmp = next_fp_limit;
7761 if (size > 4 && !is_double)
8c54989a
KK		 7762 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp),
7763 unshare_expr (tmp), size_int (4 - size));
7764 tmp = build2 (GE_EXPR, boolean_type_node,
7765 unshare_expr (next_fp_tmp), unshare_expr (tmp));
47a25a46 7766 cmp = build3 (COND_EXPR, void_type_node, tmp,
8c54989a
KK		 7767 build1 (GOTO_EXPR, void_type_node,
7768 unshare_expr (lab_false)), NULL_TREE);
a11c004b
R		 7769 if (!is_double)
7770 gimplify_and_add (cmp, pre_p);
514066a1 7771
11160b58
R		 7772 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7773 || (is_double || size == 16))
514066a1 7774 {
5be014d5
AP		 7775 tmp = fold_convert (sizetype, next_fp_tmp);
7776 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7777 size_int (UNITS_PER_WORD));
7778 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
8c54989a
KK		 7779 unshare_expr (next_fp_tmp), tmp);
7780 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
514066a1 7781 }
a11c004b
R		 7782 if (is_double)
7783 gimplify_and_add (cmp, pre_p);
514066a1 7784
6d1cb95f 7785#ifdef FUNCTION_ARG_SCmode_WART
11160b58
R		 7786 if (TYPE_MODE (eff_type) == SCmode
7787 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
6d1cb95f 7788 {
11160b58 7789 tree subtype = TREE_TYPE (eff_type);
5fac2ed2 7790 tree real, imag;
6d1cb95f 7791
a11c004b
R		 7792 imag
7793 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
5fac2ed2 7794 imag = get_initialized_tmp_var (imag, pre_p, NULL);
6d1cb95f 7795
a11c004b
R		 7796 real
7797 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
5fac2ed2
RH		 7798 real = get_initialized_tmp_var (real, pre_p, NULL);
7799
f2a945b1
KK		 7800 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
7801 if (type != eff_type)
7802 result = build1 (VIEW_CONVERT_EXPR, type, result);
5fac2ed2 7803 result = get_initialized_tmp_var (result, pre_p, NULL);
6d1cb95f
R		 7804 }
7805#endif /* FUNCTION_ARG_SCmode_WART */
7806
8c54989a 7807 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
5fac2ed2
RH		 7808 gimplify_and_add (tmp, pre_p);
7809
8c54989a 7810 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
5fac2ed2 7811 gimplify_and_add (tmp, pre_p);
514066a1 7812
8c54989a
KK		 7813 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7814 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7815 gimplify_assign (unshare_expr (next_fp_tmp),
7816 unshare_expr (valist), pre_p);
a11c004b 7817
8c54989a
KK		 7818 gimplify_assign (unshare_expr (valist),
7819 unshare_expr (next_fp_tmp), post_p);
a11c004b 7820 valist = next_fp_tmp;
514066a1
RH		 7821 }
7822 else
7823 {
8c54989a
KK		 7824 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7825 unshare_expr (next_o), size_int (rsize));
7826 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
7827 unshare_expr (next_o_limit));
47a25a46 7828 tmp = build3 (COND_EXPR, void_type_node, tmp,
8c54989a
KK		 7829 build1 (GOTO_EXPR, void_type_node,
7830 unshare_expr (lab_false)),
7831 NULL_TREE);
5fac2ed2 7832 gimplify_and_add (tmp, pre_p);
514066a1 7833
8c54989a
KK		 7834 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
7835 gimplify_assign (unshare_expr (addr), tmp, pre_p);
514066a1 7836
8c54989a 7837 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
5fac2ed2
RH		 7838 gimplify_and_add (tmp, pre_p);
7839
8c54989a 7840 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
5fac2ed2 7841 gimplify_and_add (tmp, pre_p);
514066a1 7842
bdf57c40 7843 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
8c54989a
KK		 7844 gimplify_assign (unshare_expr (next_o),
7845 unshare_expr (next_o_limit), pre_p);
514066a1 7846
8c54989a
KK		 7847 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7848 gimplify_assign (unshare_expr (addr), tmp, pre_p);
514066a1
RH		 7849 }
7850
5fac2ed2
RH		 7851 if (!result)
7852 {
8c54989a 7853 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
5fac2ed2
RH		 7854 gimplify_and_add (tmp, pre_p);
7855 }
514066a1
RH		 7856 }
7857
7858 /* ??? In va-sh.h, there had been code to make values larger than
7859 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7860
5fac2ed2 7861 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
6d1cb95f
R		 7862 if (result)
7863 {
726a989a 7864 gimplify_assign (result, tmp, pre_p);
5fac2ed2 7865
8c54989a 7866 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
5fac2ed2 7867 gimplify_and_add (tmp, pre_p);
6d1cb95f
R		 7868 }
7869 else
5fac2ed2 7870 result = tmp;
6d1cb95f 7871
5e039e6b 7872 if (pass_by_ref)
d6e9821f 7873 result = build_va_arg_indirect_ref (result);
5fac2ed2 7874
5e039e6b 7875 return result;
514066a1
RH		 7876}
7877
63a9de54
CB		 7878/* 64 bit floating points memory transfers are paired single precision loads
7879 or store. So DWARF information needs fixing in little endian (unless
7880 PR=SZ=1 in FPSCR). */
7881rtx
7882sh_dwarf_register_span (rtx reg)
7883{
7884 unsigned regno = REGNO (reg);
7885
7886 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
7887 return NULL_RTX;
7888
7889 return
7890 gen_rtx_PARALLEL (VOIDmode,
7891 gen_rtvec (2,
7892 gen_rtx_REG (SFmode,
7893 DBX_REGISTER_NUMBER (regno+1)),
7894 gen_rtx_REG (SFmode,
7895 DBX_REGISTER_NUMBER (regno))));
7896}
7897
150e407a 7898bool
586de218 7899sh_promote_prototypes (const_tree type)
61f71b34
DD		 7900{
7901 if (TARGET_HITACHI)
7902 return 0;
7903 if (! type)
7904 return 1;
7905 return ! sh_attr_renesas_p (type);
7906}
7907
8cd5a4e0
RH		 7908/* Whether an argument must be passed by reference. On SHcompact, we
7909 pretend arguments wider than 32-bits that would have been passed in
7910 registers are passed by reference, so that an SHmedia trampoline
7911 loads them into the full 64-bits registers. */
7912
7913static int
586de218
KG		 7914shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
7915 const_tree type, bool named)
8cd5a4e0
RH		 7916{
7917 unsigned HOST_WIDE_INT size;
7918
7919 if (type)
7920 size = int_size_in_bytes (type);
7921 else
7922 size = GET_MODE_SIZE (mode);
7923
7924 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
7925 && (!named
7926 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
7927 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
7928 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
7929 && size > 4
7930 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
7931 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7932 return size;
7933 else
7934 return 0;
7935}
7936
7937static bool
7938sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
586de218 7939 const_tree type, bool named)
8cd5a4e0
RH		 7940{
7941 if (targetm.calls.must_pass_in_stack (mode, type))
7942 return true;
7943
03603192
JR		 7944 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7945 wants to know about pass-by-reference semantics for incoming
7946 arguments. */
7947 if (! cum)
7948 return false;
7949
8cd5a4e0
RH		 7950 if (TARGET_SHCOMPACT)
7951 {
7952 cum->byref = shcompact_byref (cum, mode, type, named);
7953 return cum->byref != 0;
7954 }
7955
7956 return false;
7957}
7958
6cdd5672
RH		 7959static bool
7960sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
586de218 7961 const_tree type, bool named ATTRIBUTE_UNUSED)
6cdd5672
RH		 7962{
7963 /* ??? How can it possibly be correct to return true only on the
7964 caller side of the equation? Is there someplace else in the
7965 sh backend that's magically producing the copies? */
7966 return (cum->outgoing
7967 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
7968 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
7969}
7970
78a52f11
RH		 7971static int
7972sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7973 tree type, bool named ATTRIBUTE_UNUSED)
7974{
7975 int words = 0;
7976
7977 if (!TARGET_SH5
7978 && PASS_IN_REG_P (*cum, mode, type)
7979 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7980 && (ROUND_REG (*cum, mode)
7981 + (mode != BLKmode
7982 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
7983 : ROUND_ADVANCE (int_size_in_bytes (type)))
7984 > NPARM_REGS (mode)))
7985 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
7986
7987 else if (!TARGET_SHCOMPACT
7988 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7989 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
7990
7991 return words * UNITS_PER_WORD;
7992}
7993
7994
61f71b34
DD		 7995/* Define where to put the arguments to a function.
7996 Value is zero to push the argument on the stack,
7997 or a hard register in which to store the argument.
7998
7999 MODE is the argument's machine mode.
8000 TYPE is the data type of the argument (as a tree).
8001 This is null for libcalls where that information may
8002 not be available.
8003 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8004 the preceding args and about the function being called.
8005 NAMED is nonzero if this argument is a named parameter
8006 (otherwise it is an extra parameter matching an ellipsis).
8007
8008 On SH the first args are normally in registers
8009 and the rest are pushed. Any arg that starts within the first
8010 NPARM_REGS words is at least partially passed in a register unless
8011 its data type forbids. */
8012
8013
8014rtx
cf277499
SB		 8015sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8016 tree type, int named)
61f71b34
DD		 8017{
8018 if (! TARGET_SH5 && mode == VOIDmode)
8019 return GEN_INT (ca->renesas_abi ? 1 : 0);
8020
8021 if (! TARGET_SH5
8022 && PASS_IN_REG_P (*ca, mode, type)
8023 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
8024 {
8025 int regno;
8026
8027 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
8028 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
8029 {
8030 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
8031 gen_rtx_REG (SFmode,
8032 BASE_ARG_REG (mode)
8033 + (ROUND_REG (*ca, mode) ^ 1)),
8034 const0_rtx);
832a3292
KH		 8035 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
8036 gen_rtx_REG (SFmode,
8037 BASE_ARG_REG (mode)
8038 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
8039 GEN_INT (4));
61f71b34
DD		 8040 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
8041 }
8042
8043 /* If the alignment of a DF value causes an SF register to be
8044 skipped, we will use that skipped register for the next SF
8045 value. */
8046 if ((TARGET_HITACHI || ca->renesas_abi)
8047 && ca->free_single_fp_reg
8048 && mode == SFmode)
8049 return gen_rtx_REG (mode, ca->free_single_fp_reg);
8050
8051 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
8052 ^ (mode == SFmode && TARGET_SH4
8053 && TARGET_LITTLE_ENDIAN != 0
8054 && ! TARGET_HITACHI && ! ca->renesas_abi);
8055 return gen_rtx_REG (mode, regno);
8056
8057 }
f676971a 8058
61f71b34
DD		 8059 if (TARGET_SH5)
8060 {
8061 if (mode == VOIDmode && TARGET_SHCOMPACT)
8062 return GEN_INT (ca->call_cookie);
8063
8064 /* The following test assumes unnamed arguments are promoted to
8065 DFmode. */
8066 if (mode == SFmode && ca->free_single_fp_reg)
8067 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
8068
8069 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
8070 && (named || ! ca->prototype_p)
8071 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
8072 {
8073 if (! ca->prototype_p && TARGET_SHMEDIA)
8074 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
8075
8076 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
8077 FIRST_FP_PARM_REG
8078 + ca->arg_count[(int) SH_ARG_FLOAT]);
8079 }
8080
8081 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
8082 && (! TARGET_SHCOMPACT
8083 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
8084 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
8085 type, named))))
8086 {
8087 return gen_rtx_REG (mode, (FIRST_PARM_REG
8088 + ca->arg_count[(int) SH_ARG_INT]));
8089 }
8090
8091 return 0;
8092 }
8093
8094 return 0;
8095}
f676971a 8096
61f71b34
DD		 8097/* Update the data in CUM to advance over an argument
8098 of mode MODE and data type TYPE.
8099 (TYPE is null for libcalls where that information may not be
8100 available.) */
8101
8102void
cf277499
SB		 8103sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8104 tree type, int named)
61f71b34 8105{
832a3292
KH		 8106 if (ca->force_mem)
8107 ca->force_mem = 0;
8108 else if (TARGET_SH5)
8109 {
8110 tree type2 = (ca->byref && type
8111 ? TREE_TYPE (type)
8112 : type);
8113 enum machine_mode mode2 = (ca->byref && type
8114 ? TYPE_MODE (type2)
8115 : mode);
8116 int dwords = ((ca->byref
8117 ? ca->byref
8118 : mode2 == BLKmode
8119 ? int_size_in_bytes (type2)
8120 : GET_MODE_SIZE (mode2)) + 7) / 8;
8121 int numregs = MIN (dwords, NPARM_REGS (SImode)
8122 - ca->arg_count[(int) SH_ARG_INT]);
8123
8124 if (numregs)
8125 {
8126 ca->arg_count[(int) SH_ARG_INT] += numregs;
8127 if (TARGET_SHCOMPACT
8128 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
8129 {
8130 ca->call_cookie
8131 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8132 - numregs, 1);
8133 /* N.B. We want this also for outgoing. */
8134 ca->stack_regs += numregs;
8135 }
8136 else if (ca->byref)
8137 {
8138 if (! ca->outgoing)
8139 ca->stack_regs += numregs;
8140 ca->byref_regs += numregs;
8141 ca->byref = 0;
8142 do
8143 ca->call_cookie
8144 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8145 - numregs, 2);
8146 while (--numregs);
8147 ca->call_cookie
8148 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8149 - 1, 1);
8150 }
8151 else if (dwords > numregs)
8152 {
8153 int pushregs = numregs;
8154
8155 if (TARGET_SHCOMPACT)
8156 ca->stack_regs += numregs;
8157 while (pushregs < NPARM_REGS (SImode) - 1
8158 && (CALL_COOKIE_INT_REG_GET
8159 (ca->call_cookie,
8160 NPARM_REGS (SImode) - pushregs)
8161 == 1))
8162 {
8163 ca->call_cookie
8164 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
8165 - pushregs, 1);
8166 pushregs++;
8167 }
8168 if (numregs == NPARM_REGS (SImode))
8169 ca->call_cookie
8170 |= CALL_COOKIE_INT_REG (0, 1)
8171 | CALL_COOKIE_STACKSEQ (numregs - 1);
8172 else
8173 ca->call_cookie
8174 |= CALL_COOKIE_STACKSEQ (numregs);
8175 }
8176 }
8177 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
8178 && (named || ! ca->prototype_p))
8179 {
8180 if (mode2 == SFmode && ca->free_single_fp_reg)
8181 ca->free_single_fp_reg = 0;
8182 else if (ca->arg_count[(int) SH_ARG_FLOAT]
8183 < NPARM_REGS (SFmode))
8184 {
8185 int numfpregs
8186 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
8187 NPARM_REGS (SFmode)
8188 - ca->arg_count[(int) SH_ARG_FLOAT]);
8189
8190 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
8191
8192 if (TARGET_SHCOMPACT && ! ca->prototype_p)
8193 {
8194 if (ca->outgoing && numregs > 0)
8195 do
8196 {
8197 ca->call_cookie
8198 |= (CALL_COOKIE_INT_REG
8199 (ca->arg_count[(int) SH_ARG_INT]
8200 - numregs + ((numfpregs - 2) / 2),
8201 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
8202 - numfpregs) / 2));
8203 }
8204 while (numfpregs -= 2);
8205 }
8206 else if (mode2 == SFmode && (named)
8207 && (ca->arg_count[(int) SH_ARG_FLOAT]
8208 < NPARM_REGS (SFmode)))
8209 ca->free_single_fp_reg
8210 = FIRST_FP_PARM_REG - numfpregs
8211 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
8212 }
8213 }
8214 return;
8215 }
8216
8217 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
8218 {
8219 /* Note that we've used the skipped register. */
8220 if (mode == SFmode && ca->free_single_fp_reg)
8221 {
8222 ca->free_single_fp_reg = 0;
8223 return;
8224 }
8225 /* When we have a DF after an SF, there's an SF register that get
8226 skipped in order to align the DF value. We note this skipped
8227 register, because the next SF value will use it, and not the
8228 SF that follows the DF. */
8229 if (mode == DFmode
8230 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
8231 {
8232 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
8233 + BASE_ARG_REG (mode));
8234 }
8235 }
8236
157371cf 8237 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
832a3292
KH		 8238 || PASS_IN_REG_P (*ca, mode, type))
8239 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
8240 = (ROUND_REG (*ca, mode)
8241 + (mode == BLKmode
8242 ? ROUND_ADVANCE (int_size_in_bytes (type))
8243 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
61f71b34
DD		 8244}
8245
61f71b34
DD		 8246/* The Renesas calling convention doesn't quite fit into this scheme since
8247 the address is passed like an invisible argument, but one that is always
8248 passed in memory. */
8249static rtx
cf277499 8250sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
61f71b34
DD		 8251{
8252 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8253 return 0;
8254 return gen_rtx_REG (Pmode, 2);
8255}
8256
bd5bd7ac
KH		 8257/* Worker function for TARGET_RETURN_IN_MEMORY. */
8258
61f71b34 8259static bool
586de218 8260sh_return_in_memory (const_tree type, const_tree fndecl)
61f71b34
DD		 8261{
8262 if (TARGET_SH5)
8263 {
8264 if (TYPE_MODE (type) == BLKmode)
8265 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
8266 else
8267 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
8268 }
8269 else
8270 {
8271 return (TYPE_MODE (type) == BLKmode
8272 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8273 && TREE_CODE (type) == RECORD_TYPE));
8274 }
8275}
8276
8277/* We actually emit the code in sh_expand_prologue. We used to use
8278 a static variable to flag that we need to emit this code, but that
8279 doesn't when inlining, when functions are deferred and then emitted
8280 later. Fortunately, we already have two flags that are part of struct
8281 function that tell if a function uses varargs or stdarg. */
8282static void
49616835
JR		 8283sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
8284 enum machine_mode mode,
8285 tree type,
8286 int *pretend_arg_size,
cf277499 8287 int second_time ATTRIBUTE_UNUSED)
61f71b34 8288{
e3b5732b 8289 gcc_assert (cfun->stdarg);
49616835
JR		 8290 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8291 {
8292 int named_parm_regs, anon_parm_regs;
8293
8294 named_parm_regs = (ROUND_REG (*ca, mode)
8295 + (mode == BLKmode
8296 ? ROUND_ADVANCE (int_size_in_bytes (type))
8297 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
8298 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
8299 if (anon_parm_regs > 0)
8300 *pretend_arg_size = anon_parm_regs * 4;
8301 }
61f71b34
DD		 8302}
8303
8304static bool
cf277499 8305sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
61f71b34
DD		 8306{
8307 return TARGET_SH5;
8308}
8309
8310static bool
cf277499 8311sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
61f71b34
DD		 8312{
8313 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
8314}
8315
8316
0d7e008e
SC		 8317/* Define the offset between two registers, one to be eliminated, and
8318 the other its replacement, at the start of a routine. */
8319
8320int
cf277499 8321initial_elimination_offset (int from, int to)
0d7e008e
SC		 8322{
8323 int regs_saved;
fa5322fa 8324 int regs_saved_rounding = 0;
0d7e008e 8325 int total_saved_regs_space;
e5f8d4c0 8326 int total_auto_space;
1245df60 8327 int save_flags = target_flags;
fa5322fa 8328 int copy_flags;
490dbac7 8329 HARD_REG_SET live_regs_mask;
fe3ad572
SC		 8330
8331 shmedia_space_reserved_for_target_registers = false;
490dbac7 8332 regs_saved = calc_live_regs (&live_regs_mask);
fa5322fa 8333 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
fe3ad572
SC		 8334
8335 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
8336 {
8337 shmedia_space_reserved_for_target_registers = true;
8338 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
8339 }
8340
fa5322fa
AO		 8341 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
8342 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8343 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
8e87e161 8344
fa5322fa
AO		 8345 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8346 copy_flags = target_flags;
1245df60 8347 target_flags = save_flags;
1a95a963 8348
fa5322fa 8349 total_saved_regs_space = regs_saved + regs_saved_rounding;
b9654711 8350
96a2347e 8351 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
fa5322fa 8352 return total_saved_regs_space + total_auto_space
38173d38 8353 + crtl->args.info.byref_regs * 8;
8aa2a305 8354
0d7e008e 8355 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
fa5322fa 8356 return total_saved_regs_space + total_auto_space
38173d38 8357 + crtl->args.info.byref_regs * 8;
8aa2a305
JW		 8358
8359 /* Initial gap between fp and sp is 0. */
96a2347e 8360 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8aa2a305
JW		 8361 return 0;
8362
96a2347e
KK		 8363 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8364 return rounded_frame_size (0);
8365
8366 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8367 return rounded_frame_size (0);
8368
f5b9e7c9 8369 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
96a2347e
KK		 8370 && (to == HARD_FRAME_POINTER_REGNUM
8371 || to == STACK_POINTER_REGNUM));
f5b9e7c9 8372 if (TARGET_SH5)
d042370e 8373 {
f5b9e7c9
NS		 8374 int n = total_saved_regs_space;
8375 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
8376 save_schedule schedule;
8377 save_entry *entry;
8378
8379 n += total_auto_space;
8380
8381 /* If it wasn't saved, there's not much we can do. */
8382 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
8383 return n;
8384
8385 target_flags = copy_flags;
8386
8387 sh5_schedule_saves (&live_regs_mask, &schedule, n);
8388 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
8389 if (entry->reg == pr_reg)
8390 {
8391 target_flags = save_flags;
8392 return entry->offset;
8393 }
8394 gcc_unreachable ();
d042370e 8395 }
f5b9e7c9
NS		 8396 else
8397 return total_auto_space;
0d7e008e 8398}
3217af3e
KK		 8399
8400/* Parse the -mfixed-range= option string. */
8401void
8402sh_fix_range (const char *const_str)
8403{
8404 int i, first, last;
8405 char *str, *dash, *comma;
8406
8407 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8408 REG2 are either register names or register numbers. The effect
8409 of this option is to mark the registers in the range from REG1 to
8410 REG2 as ``fixed'' so they won't be used by the compiler. */
8411
8412 i = strlen (const_str);
8413 str = (char *) alloca (i + 1);
8414 memcpy (str, const_str, i + 1);
8415
8416 while (1)
8417 {
8418 dash = strchr (str, '-');
8419 if (!dash)
8420 {
8421 warning (0, "value of -mfixed-range must have form REG1-REG2");
8422 return;
8423 }
8424 *dash = '\0';
8425 comma = strchr (dash + 1, ',');
8426 if (comma)
8427 *comma = '\0';
8428
8429 first = decode_reg_name (str);
8430 if (first < 0)
8431 {
8432 warning (0, "unknown register name: %s", str);
8433 return;
8434 }
8435
8436 last = decode_reg_name (dash + 1);
8437 if (last < 0)
8438 {
8439 warning (0, "unknown register name: %s", dash + 1);
8440 return;
8441 }
8442
8443 *dash = '-';
8444
8445 if (first > last)
8446 {
8447 warning (0, "%s-%s is an empty range", str, dash + 1);
8448 return;
8449 }
8450
8451 for (i = first; i <= last; ++i)
8452 fixed_regs[i] = call_used_regs[i] = 1;
8453
8454 if (!comma)
8455 break;
8456
8457 *comma = ',';
8458 str = comma + 1;
8459 }
8460}
8aa2a305 8461\f
a6ab9fc0 8462/* Insert any deferred function attributes from earlier pragmas. */
12a68f1f 8463static void
cf277499 8464sh_insert_attributes (tree node, tree *attributes)
157131d7 8465{
a6ab9fc0
R		 8466 tree attrs;
8467
8468 if (TREE_CODE (node) != FUNCTION_DECL)
157131d7
SC		 8469 return;
8470
8471 /* We are only interested in fields. */
6615c446 8472 if (!DECL_P (node))
157131d7
SC		 8473 return;
8474
a6ab9fc0
R		 8475 /* Append the attributes to the deferred attributes. */
8476 *sh_deferred_function_attributes_tail = *attributes;
8477 attrs = sh_deferred_function_attributes;
8478 if (!attrs)
8479 return;
8480
8481 /* Some attributes imply or require the interrupt attribute. */
8482 if (!lookup_attribute ("interrupt_handler", attrs)
8483 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8484 {
8485 /* If we have a trapa_handler, but no interrupt_handler attribute,
8486 insert an interrupt_handler attribute. */
8487 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8488 /* We can't use sh_pr_interrupt here because that's not in the
8489 java frontend. */
8490 attrs
8491 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
561642fa
AP		 8492 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8493 if the interrupt attribute is missing, we ignore the attribute
8494 and warn. */
a6ab9fc0
R		 8495 else if (lookup_attribute ("sp_switch", attrs)
8496 || lookup_attribute ("trap_exit", attrs)
561642fa
AP		 8497 || lookup_attribute ("nosave_low_regs", attrs)
8498 || lookup_attribute ("resbank", attrs))
a6ab9fc0
R		 8499 {
8500 tree *tail;
8501
8502 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8503 {
8504 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8505 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
561642fa
AP		 8506 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8507 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
a6ab9fc0 8508 warning (OPT_Wattributes,
29d08eba
JM		 8509 "%qE attribute only applies to interrupt functions",
8510 TREE_PURPOSE (attrs));
a6ab9fc0
R		 8511 else
8512 {
8513 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8514 NULL_TREE);
8515 tail = &TREE_CHAIN (*tail);
8516 }
8517 }
8518 attrs = *attributes;
8519 }
8520 }
8521
8522 /* Install the processed list. */
8523 *attributes = attrs;
8524
8525 /* Clear deferred attributes. */
8526 sh_deferred_function_attributes = NULL_TREE;
8527 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
157131d7
SC		 8528
8529 return;
8530}
8531
91d231cb 8532/* Supported attributes:
4408efce
JL		 8533
8534 interrupt_handler -- specifies this function is an interrupt handler.
8535
a6ab9fc0
R		 8536 trapa_handler - like above, but don't save all registers.
8537
4408efce
JL		 8538 sp_switch -- specifies an alternate stack for an interrupt handler
8539 to run on.
8540
956d6950 8541 trap_exit -- use a trapa to exit an interrupt function instead of
61f71b34
DD		 8542 an rte instruction.
8543
a6ab9fc0
R		 8544 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8545 This is useful on the SH3 and upwards,
8546 which has a separate set of low regs for User and Supervisor modes.
8547 This should only be used for the lowest level of interrupts. Higher levels
8548 of interrupts must save the registers in case they themselves are
8549 interrupted.
8550
61f71b34
DD		 8551 renesas -- use Renesas calling/layout conventions (functions and
8552 structures).
8553
561642fa
AP		 8554 resbank -- In case of an ISR, use a register bank to save registers
8555 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
61f71b34 8556*/
4408efce 8557
561642fa
AP		 8558/* Handle a 'resbank' attribute. */
8559static tree
8560sh_handle_resbank_handler_attribute (tree * node, tree name,
8561 tree args ATTRIBUTE_UNUSED,
8562 int flags ATTRIBUTE_UNUSED,
8563 bool * no_add_attrs)
8564{
8565 if (!TARGET_SH2A)
8566 {
29d08eba
JM		 8567 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8568 name);
561642fa
AP		 8569 *no_add_attrs = true;
8570 }
8571 if (TREE_CODE (*node) != FUNCTION_DECL)
8572 {
29d08eba
JM		 8573 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8574 name);
561642fa
AP		 8575 *no_add_attrs = true;
8576 }
8577
8578 return NULL_TREE;
8579}
8580
91d231cb
JM		 8581/* Handle an "interrupt_handler" attribute; arguments as in
8582 struct attribute_spec.handler. */
8583static tree
cf277499 8584sh_handle_interrupt_handler_attribute (tree *node, tree name,
561642fa
AP		 8585 tree args ATTRIBUTE_UNUSED,
8586 int flags ATTRIBUTE_UNUSED,
8587 bool *no_add_attrs)
91d231cb
JM		 8588{
8589 if (TREE_CODE (*node) != FUNCTION_DECL)
4408efce 8590 {
29d08eba
JM		 8591 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8592 name);
91d231cb 8593 *no_add_attrs = true;
4408efce 8594 }
58ab7171
R		 8595 else if (TARGET_SHCOMPACT)
8596 {
8597 error ("attribute interrupt_handler is not compatible with -m5-compact");
8598 *no_add_attrs = true;
8599 }
4408efce 8600
91d231cb
JM		 8601 return NULL_TREE;
8602}
8603
561642fa
AP		 8604/* Handle an 'function_vector' attribute; arguments as in
8605 struct attribute_spec.handler. */
8606static tree
8607sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8608 tree args ATTRIBUTE_UNUSED,
8609 int flags ATTRIBUTE_UNUSED,
8610 bool * no_add_attrs)
8611{
8612 if (!TARGET_SH2A)
8613 {
29d08eba
JM		 8614 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8615 name);
561642fa
AP		 8616 *no_add_attrs = true;
8617 }
8618 else if (TREE_CODE (*node) != FUNCTION_DECL)
8619 {
29d08eba
JM		 8620 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8621 name);
561642fa
AP		 8622 *no_add_attrs = true;
8623 }
8624 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8625 {
8626 /* The argument must be a constant integer. */
8627 warning (OPT_Wattributes,
29d08eba
JM		 8628 "%qE attribute argument not an integer constant",
8629 name);
561642fa
AP		 8630 *no_add_attrs = true;
8631 }
8632 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8633 {
8634 /* The argument value must be between 0 to 255. */
8635 warning (OPT_Wattributes,
29d08eba
JM		 8636 "%qE attribute argument should be between 0 to 255",
8637 name);
561642fa
AP		 8638 *no_add_attrs = true;
8639 }
8640 return NULL_TREE;
8641}
8642
8643/* Returns 1 if current function has been assigned the attribute
8644 'function_vector'. */
8645int
8646sh2a_is_function_vector_call (rtx x)
8647{
8648 if (GET_CODE (x) == SYMBOL_REF
8649 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8650 {
8651 tree tr = SYMBOL_REF_DECL (x);
8652
8653 if (sh2a_function_vector_p (tr))
8654 return 1;
8655 }
8656
8657 return 0;
8658}
8659
8660/* Returns the function vector number, if the the attribute
8661 'function_vector' is assigned, otherwise returns zero. */
8662int
8663sh2a_get_function_vector_number (rtx x)
8664{
8665 int num;
8666 tree list, t;
8667
8668 if ((GET_CODE (x) == SYMBOL_REF)
8669 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8670 {
8671 t = SYMBOL_REF_DECL (x);
8672
8673 if (TREE_CODE (t) != FUNCTION_DECL)
8674 return 0;
8675
8676 list = SH_ATTRIBUTES (t);
8677 while (list)
8678 {
8679 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8680 {
8681 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8682 return num;
8683 }
8684
8685 list = TREE_CHAIN (list);
8686 }
8687
8688 return 0;
8689 }
8690 else
8691 return 0;
8692}
8693
91d231cb
JM		 8694/* Handle an "sp_switch" attribute; arguments as in
8695 struct attribute_spec.handler. */
8696static tree
cf277499
SB		 8697sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8698 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
91d231cb
JM		 8699{
8700 if (TREE_CODE (*node) != FUNCTION_DECL)
8701 {
29d08eba
JM		 8702 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8703 name);
91d231cb
JM		 8704 *no_add_attrs = true;
8705 }
91d231cb
JM		 8706 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8707 {
4408efce 8708 /* The argument must be a constant string. */
29d08eba
JM		 8709 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
8710 name);
91d231cb
JM		 8711 *no_add_attrs = true;
8712 }
4408efce 8713
91d231cb
JM		 8714 return NULL_TREE;
8715}
8716
8717/* Handle an "trap_exit" attribute; arguments as in
8718 struct attribute_spec.handler. */
8719static tree
cf277499
SB		 8720sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8721 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
91d231cb
JM		 8722{
8723 if (TREE_CODE (*node) != FUNCTION_DECL)
8724 {
29d08eba
JM		 8725 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8726 name);
91d231cb
JM		 8727 *no_add_attrs = true;
8728 }
a6ab9fc0
R		 8729 /* The argument specifies a trap number to be used in a trapa instruction
8730 at function exit (instead of an rte instruction). */
91d231cb
JM		 8731 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8732 {
4408efce 8733 /* The argument must be a constant integer. */
29d08eba
JM		 8734 warning (OPT_Wattributes, "%qE attribute argument not an "
8735 "integer constant", name);
91d231cb
JM		 8736 *no_add_attrs = true;
8737 }
318881c0 8738
91d231cb 8739 return NULL_TREE;
4408efce
JL		 8740}
8741
61f71b34 8742static tree
cf277499
SB		 8743sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8744 tree name ATTRIBUTE_UNUSED,
8745 tree args ATTRIBUTE_UNUSED,
8746 int flags ATTRIBUTE_UNUSED,
8747 bool *no_add_attrs ATTRIBUTE_UNUSED)
61f71b34
DD		 8748{
8749 return NULL_TREE;
8750}
8751
8752/* True if __attribute__((renesas)) or -mrenesas. */
8753int
586de218 8754sh_attr_renesas_p (const_tree td)
61f71b34
DD		 8755{
8756 if (TARGET_HITACHI)
8757 return 1;
8758 if (td == 0)
8759 return 0;
8760 if (DECL_P (td))
8761 td = TREE_TYPE (td);
a11c004b
R		 8762 if (td == error_mark_node)
8763 return 0;
61f71b34
DD		 8764 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8765 != NULL_TREE);
8766}
8767
8768/* True if __attribute__((renesas)) or -mrenesas, for the current
8769 function. */
8770int
cf277499 8771sh_cfun_attr_renesas_p (void)
61f71b34
DD		 8772{
8773 return sh_attr_renesas_p (current_function_decl);
8774}
8775
e3ba8d11 8776int
cf277499 8777sh_cfun_interrupt_handler_p (void)
e3ba8d11
R		 8778{
8779 return (lookup_attribute ("interrupt_handler",
8780 DECL_ATTRIBUTES (current_function_decl))
8781 != NULL_TREE);
8782}
bcc8cc82 8783
561642fa
AP		 8784/* Returns 1 if FUNC has been assigned the attribute
8785 "function_vector". */
8786int
8787sh2a_function_vector_p (tree func)
8788{
8789 tree list;
8790 if (TREE_CODE (func) != FUNCTION_DECL)
8791 return 0;
8792
8793 list = SH_ATTRIBUTES (func);
8794 while (list)
8795 {
8796 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8797 return 1;
8798
8799 list = TREE_CHAIN (list);
8800 }
8801 return 0;
8802}
8803
8804/* Returns TRUE if given tree has the "resbank" attribute. */
8805
8806int
8807sh_cfun_resbank_handler_p (void)
8808{
8809 return ((lookup_attribute ("resbank",
8810 DECL_ATTRIBUTES (current_function_decl))
8811 != NULL_TREE)
8812 && (lookup_attribute ("interrupt_handler",
8813 DECL_ATTRIBUTES (current_function_decl))
8814 != NULL_TREE) && TARGET_SH2A);
8815}
8816
8d932be3 8817/* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
73a4d10b 8818
8d932be3
RS		 8819static const char *
8820sh_check_pch_target_flags (int old_flags)
8821{
c0fb94d7
RS		 8822 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8823 | MASK_SH_E | MASK_HARD_SH4
8824 | MASK_FPU_SINGLE | MASK_SH4))
8825 return _("created and used with different architectures / ABIs");
8826 if ((old_flags ^ target_flags) & MASK_HITACHI)
8827 return _("created and used with different ABIs");
8828 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8829 return _("created and used with different endianness");
bcc8cc82 8830 return NULL;
bcc8cc82 8831}
0d7e008e 8832\f
8aa2a305 8833/* Predicates used by the templates. */
0d7e008e 8834
8aa2a305
JW		 8835/* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
8836 Used only in general_movsrc_operand. */
0d7e008e 8837
8aa2a305 8838int
cf277499 8839system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
0d7e008e 8840{
8aa2a305 8841 switch (REGNO (op))
0d7e008e 8842 {
8aa2a305
JW		 8843 case PR_REG:
8844 case MACL_REG:
8845 case MACH_REG:
8846 return 1;
0d7e008e 8847 }
8aa2a305 8848 return 0;
0d7e008e 8849}
0d7e008e 8850
1a95a963
JW		 8851/* Nonzero if OP is a floating point value with value 0.0. */
8852
8853int
cf277499 8854fp_zero_operand (rtx op)
d3ae8277 8855{
1a95a963 8856 REAL_VALUE_TYPE r;
d3ae8277 8857
1a95a963
JW		 8858 if (GET_MODE (op) != SFmode)
8859 return 0;
8860
8861 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
e4fa6b06 8862 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
d3ae8277
SC		 8863}
8864
1a95a963 8865/* Nonzero if OP is a floating point value with value 1.0. */
d3ae8277
SC		 8866
8867int
cf277499 8868fp_one_operand (rtx op)
d3ae8277 8869{
1a95a963
JW		 8870 REAL_VALUE_TYPE r;
8871
8872 if (GET_MODE (op) != SFmode)
8873 return 0;
8874
8875 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8876 return REAL_VALUES_EQUAL (r, dconst1);
d3ae8277 8877}
1245df60 8878
9f09b1f2
R		 8879/* For -m4 and -m4-single-only, mode switching is used. If we are
8880 compiling without -mfmovd, movsf_ie isn't taken into account for
8881 mode switching. We could check in machine_dependent_reorg for
8882 cases where we know we are in single precision mode, but there is
8883 interface to find that out during reload, so we must avoid
8884 choosing an fldi alternative during reload and thus failing to
8885 allocate a scratch register for the constant loading. */
8886int
cf277499 8887fldi_ok (void)
9f09b1f2
R		 8888{
8889 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
8890}
8891
225e4f43 8892int
cf277499 8893tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
225e4f43
R		 8894{
8895 enum rtx_code code = GET_CODE (op);
8896 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
8897}
8898
463f02cd 8899/* Return the TLS type for TLS symbols, 0 for otherwise. */
81f40b79 8900enum tls_model
cf277499 8901tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
463f02cd 8902{
463f02cd 8903 if (GET_CODE (op) != SYMBOL_REF)
81f40b79 8904 return TLS_MODEL_NONE;
675ff4c7 8905 return SYMBOL_REF_TLS_MODEL (op);
463f02cd 8906}
1245df60 8907\f
33f7f353 8908/* Return the destination address of a branch. */
f676971a 8909
318881c0 8910static int
cf277499 8911branch_dest (rtx branch)
1245df60 8912{
33f7f353
JR		 8913 rtx dest = SET_SRC (PATTERN (branch));
8914 int dest_uid;
1245df60
R		 8915
8916 if (GET_CODE (dest) == IF_THEN_ELSE)
8917 dest = XEXP (dest, 1);
8918 dest = XEXP (dest, 0);
8919 dest_uid = INSN_UID (dest);
9d98a694 8920 return INSN_ADDRESSES (dest_uid);
1245df60 8921}
a55e9d2b 8922\f
5e7a8ee0 8923/* Return nonzero if REG is not used after INSN.
a55e9d2b 8924 We assume REG is a reload reg, and therefore does
8b760293 8925 not live past labels. It may live past calls or jumps though. */
a55e9d2b 8926int
cf277499 8927reg_unused_after (rtx reg, rtx insn)
a55e9d2b 8928{
8783b15e 8929 enum rtx_code code;
a55e9d2b
RK		 8930 rtx set;
8931
8932 /* If the reg is set by this instruction, then it is safe for our
8933 case. Disregard the case where this is a store to memory, since
8934 we are checking a register used in the store address. */
8935 set = single_set (insn);
f3536097 8936 if (set && !MEM_P (SET_DEST (set))
a55e9d2b
RK		 8937 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8938 return 1;
8939
318881c0 8940 while ((insn = NEXT_INSN (insn)))
a55e9d2b 8941 {
ec8e098d
PB		 8942 rtx set;
8943 if (!INSN_P (insn))
8944 continue;
8945
a55e9d2b 8946 code = GET_CODE (insn);
8783b15e 8947
c8f6f18d
RK		 8948#if 0
8949 /* If this is a label that existed before reload, then the register
8950 if dead here. However, if this is a label added by reorg, then
8951 the register may still be live here. We can't tell the difference,
8952 so we just ignore labels completely. */
8783b15e 8953 if (code == CODE_LABEL)
a55e9d2b 8954 return 1;
c8f6f18d
RK		 8955 /* else */
8956#endif
a55e9d2b 8957
8b760293
JW		 8958 if (code == JUMP_INSN)
8959 return 0;
8960
8783b15e
RK		 8961 /* If this is a sequence, we must handle them all at once.
8962 We could have for instance a call that sets the target register,
e03f5d43 8963 and an insn in a delay slot that uses the register. In this case,
8783b15e 8964 we must return 0. */
8b760293 8965 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
a55e9d2b 8966 {
8783b15e
RK		 8967 int i;
8968 int retval = 0;
8969
8970 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8971 {
8972 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
8973 rtx set = single_set (this_insn);
8974
f3536097 8975 if (CALL_P (this_insn))
8783b15e 8976 code = CALL_INSN;
f3536097 8977 else if (JUMP_P (this_insn))
38f35781
JW		 8978 {
8979 if (INSN_ANNULLED_BRANCH_P (this_insn))
8980 return 0;
8981 code = JUMP_INSN;
8982 }
a55e9d2b 8983
8783b15e
RK		 8984 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8985 return 0;
8986 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8987 {
f3536097 8988 if (!MEM_P (SET_DEST (set)))
8783b15e
RK		 8989 retval = 1;
8990 else
8991 return 0;
8992 }
8993 if (set == 0
8994 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
8995 return 0;
8996 }
8997 if (retval == 1)
8998 return 1;
38f35781
JW		 8999 else if (code == JUMP_INSN)
9000 return 0;
8783b15e 9001 }
a55e9d2b 9002
ec8e098d
PB		 9003 set = single_set (insn);
9004 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9005 return 0;
9006 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
f3536097 9007 return !MEM_P (SET_DEST (set));
ec8e098d
PB		 9008 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9009 return 0;
8783b15e 9010
62164eb4 9011 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
8783b15e 9012 return 1;
a55e9d2b
RK		 9013 }
9014 return 1;
9015}
225e4f43 9016\f
c5b9ef02 9017#include "ggc.h"
225e4f43 9018
e2500fed 9019static GTY(()) rtx fpscr_rtx;
225e4f43 9020rtx
cf277499 9021get_fpscr_rtx (void)
225e4f43 9022{
225e4f43
R		 9023 if (! fpscr_rtx)
9024 {
c0d4e710 9025 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
225e4f43 9026 REG_USERVAR_P (fpscr_rtx) = 1;
225e4f43
R		 9027 mark_user_reg (fpscr_rtx);
9028 }
9029 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
9030 mark_user_reg (fpscr_rtx);
9031 return fpscr_rtx;
9032}
9033
24c2fde2
RH		 9034static GTY(()) tree fpscr_values;
9035
9036static void
9037emit_fpu_switch (rtx scratch, int index)
9038{
9039 rtx dst, src;
9040
9041 if (fpscr_values == NULL)
9042 {
9043 tree t;
9044
9045 t = build_index_type (integer_one_node);
9046 t = build_array_type (integer_type_node, t);
4c4bde29
AH		 9047 t = build_decl (BUILTINS_LOCATION,
9048 VAR_DECL, get_identifier ("__fpscr_values"), t);
24c2fde2
RH		 9049 DECL_ARTIFICIAL (t) = 1;
9050 DECL_IGNORED_P (t) = 1;
9051 DECL_EXTERNAL (t) = 1;
9052 TREE_STATIC (t) = 1;
a5f5c6be 9053 TREE_PUBLIC (t) = 1;
24c2fde2
RH		 9054 TREE_USED (t) = 1;
9055
9056 fpscr_values = t;
9057 }
9058
9059 src = DECL_RTL (fpscr_values);
b3a13419 9060 if (!can_create_pseudo_p ())
24c2fde2
RH		 9061 {
9062 emit_move_insn (scratch, XEXP (src, 0));
9063 if (index != 0)
9064 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
9065 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
9066 }
9067 else
9068 src = adjust_address (src, PSImode, index * 4);
9069
9070 dst = get_fpscr_rtx ();
9071 emit_move_insn (dst, src);
9072}
9073
225e4f43 9074void
cf277499 9075emit_sf_insn (rtx pat)
225e4f43 9076{
225e4f43 9077 emit_insn (pat);
225e4f43
R		 9078}
9079
9080void
cf277499 9081emit_df_insn (rtx pat)
225e4f43 9082{
225e4f43 9083 emit_insn (pat);
225e4f43
R		 9084}
9085
9086void
cf277499 9087expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
225e4f43
R		 9088{
9089 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9090}
9091
9092void
cf277499 9093expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
225e4f43
R		 9094{
9095 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
9096 get_fpscr_rtx ()));
9097}
9098
9099void
cf277499 9100expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
225e4f43
R		 9101{
9102 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9103}
9104
9105void
cf277499 9106expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
225e4f43
R		 9107{
9108 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
832a3292 9109 get_fpscr_rtx ()));
225e4f43 9110}
225e4f43 9111\f
cf277499 9112static rtx get_free_reg (HARD_REG_SET);
9f09b1f2
R		 9113
9114/* This function returns a register to use to load the address to load
9115 the fpscr from. Currently it always returns r1 or r7, but when we are
9116 able to use pseudo registers after combine, or have a better mechanism
9117 for choosing a register, it should be done here. */
9118/* REGS_LIVE is the liveness information for the point for which we
9119 need this allocation. In some bare-bones exit blocks, r1 is live at the
9120 start. We can even have all of r0..r3 being live:
9121__complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
9122 INSN before which new insns are placed with will clobber the register
9123 we return. If a basic block consists only of setting the return value
9124 register to a pseudo and using that register, the return value is not
9125 live before or after this block, yet we we'll insert our insns right in
9126 the middle. */
225e4f43 9127
9f09b1f2 9128static rtx
cf277499 9129get_free_reg (HARD_REG_SET regs_live)
225e4f43 9130{
9f09b1f2
R		 9131 if (! TEST_HARD_REG_BIT (regs_live, 1))
9132 return gen_rtx_REG (Pmode, 1);
225e4f43 9133
9f09b1f2
R		 9134 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
9135 there shouldn't be anything but a jump before the function end. */
f5b9e7c9
NS		 9136 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
9137 return gen_rtx_REG (Pmode, 7);
9f09b1f2 9138}
225e4f43 9139
f676971a 9140/* This function will set the fpscr from memory.
9f09b1f2
R		 9141 MODE is the mode we are setting it to. */
9142void
cf277499 9143fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
9f09b1f2 9144{
81f40b79 9145 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
24c2fde2 9146 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
5e77c6f9 9147 rtx addr_reg;
9f09b1f2 9148
b3a13419 9149 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
24c2fde2 9150 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
225e4f43 9151}
9342c0c4
R		 9152
9153/* Is the given character a logical line separator for the assembler? */
9154#ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
980d8882 9155#define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
9342c0c4
R		 9156#endif
9157
9158int
cf277499 9159sh_insn_length_adjustment (rtx insn)
9342c0c4
R		 9160{
9161 /* Instructions with unfilled delay slots take up an extra two bytes for
9162 the nop in the delay slot. */
f3536097 9163 if (((NONJUMP_INSN_P (insn)
c1b92d09
R		 9164 && GET_CODE (PATTERN (insn)) != USE
9165 && GET_CODE (PATTERN (insn)) != CLOBBER)
f3536097
SZ		 9166 || CALL_P (insn)
9167 || (JUMP_P (insn)
9342c0c4
R		 9168 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9169 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
9170 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
9171 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
9172 return 2;
9173
3a8699c7
AO		 9174 /* SH2e has a bug that prevents the use of annulled branches, so if
9175 the delay slot is not filled, we'll have to put a NOP in it. */
b757d36f 9176 if (sh_cpu_attr == CPU_SH2E
f3536097 9177 && JUMP_P (insn)
3a8699c7
AO		 9178 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9179 && GET_CODE (PATTERN (insn)) != ADDR_VEC
9180 && get_attr_type (insn) == TYPE_CBRANCH
9181 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
9182 return 2;
9183
9342c0c4 9184 /* sh-dsp parallel processing insn take four bytes instead of two. */
f676971a 9185
f3536097 9186 if (NONJUMP_INSN_P (insn))
9342c0c4
R		 9187 {
9188 int sum = 0;
9189 rtx body = PATTERN (insn);
0a2aaacc 9190 const char *templ;
8ceaac3c 9191 char c;
9342c0c4
R		 9192 int maybe_label = 1;
9193
9194 if (GET_CODE (body) == ASM_INPUT)
0a2aaacc 9195 templ = XSTR (body, 0);
9342c0c4 9196 else if (asm_noperands (body) >= 0)
0a2aaacc 9197 templ
343d66ad 9198 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
9342c0c4
R		 9199 else
9200 return 0;
9201 do
9202 {
9203 int ppi_adjust = 0;
9204
9205 do
0a2aaacc 9206 c = *templ++;
9342c0c4
R		 9207 while (c == ' ' || c == '\t');
9208 /* all sh-dsp parallel-processing insns start with p.
9209 The only non-ppi sh insn starting with p is pref.
9210 The only ppi starting with pr is prnd. */
0a2aaacc 9211 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
9342c0c4
R		 9212 ppi_adjust = 2;
9213 /* The repeat pseudo-insn expands two three insns, a total of
9214 six bytes in size. */
9215 else if ((c == 'r' || c == 'R')
0a2aaacc 9216 && ! strncasecmp ("epeat", templ, 5))
9342c0c4 9217 ppi_adjust = 4;
980d8882 9218 while (c && c != '\n'
0a2aaacc 9219 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
9342c0c4
R		 9220 {
9221 /* If this is a label, it is obviously not a ppi insn. */
9222 if (c == ':' && maybe_label)
9223 {
9224 ppi_adjust = 0;
9225 break;
9226 }
9227 else if (c == '\'' || c == '"')
9228 maybe_label = 0;
0a2aaacc 9229 c = *templ++;
9342c0c4
R		 9230 }
9231 sum += ppi_adjust;
9232 maybe_label = c != ':';
9233 }
9234 while (c);
9235 return sum;
9236 }
9237 return 0;
9238}
1a66cd67 9239\f
cdeed45a
KK		 9240/* Return TRUE for a valid displacement for the REG+disp addressing
9241 with MODE. */
9242
9243/* ??? The SH2e does not have the REG+disp addressing mode when loading values
9244 into the FRx registers. We implement this by setting the maximum offset
9245 to zero when the value is SFmode. This also restricts loading of SFmode
9246 values into the integer registers, but that can't be helped. */
9247
9248/* The SH allows a displacement in a QI or HI amode, but only when the
9249 other operand is R0. GCC doesn't handle this very well, so we forgot
9250 all of that.
9251
9252 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
9253 DI can be any number 0..60. */
9254
9255bool
9256sh_legitimate_index_p (enum machine_mode mode, rtx op)
9257{
f3536097 9258 if (CONST_INT_P (op))
cdeed45a
KK		 9259 {
9260 if (TARGET_SHMEDIA)
9261 {
9262 int size;
9263
9264 /* Check if this the address of an unaligned load / store. */
9265 if (mode == VOIDmode)
9266 return CONST_OK_FOR_I06 (INTVAL (op));
9267
9268 size = GET_MODE_SIZE (mode);
9269 return (!(INTVAL (op) & (size - 1))
9270 && INTVAL (op) >= -512 * size
9271 && INTVAL (op) < 512 * size);
9272 }
9273
9274 if (TARGET_SH2A)
9275 {
9276 if (GET_MODE_SIZE (mode) == 1
9277 && (unsigned) INTVAL (op) < 4096)
9278 return true;
9279 }
9280
9281 if ((GET_MODE_SIZE (mode) == 4
9282 && (unsigned) INTVAL (op) < 64
9283 && !(INTVAL (op) & 3)
9284 && !(TARGET_SH2E && mode == SFmode))
9285 || (GET_MODE_SIZE (mode) == 4
9286 && (unsigned) INTVAL (op) < 16383
9287 && !(INTVAL (op) & 3) && TARGET_SH2A))
9288 return true;
9289
9290 if ((GET_MODE_SIZE (mode) == 8
9291 && (unsigned) INTVAL (op) < 60
9292 && !(INTVAL (op) & 3)
9293 && !((TARGET_SH4 || TARGET_SH2A) && mode == DFmode))
9294 || ((GET_MODE_SIZE (mode)==8)
9295 && (unsigned) INTVAL (op) < 8192
9296 && !(INTVAL (op) & (TARGET_SH2A_DOUBLE ? 7 : 3))
9297 && (TARGET_SH2A && mode == DFmode)))
9298 return true;
9299 }
9300
9301 return false;
9302}
9303
9304/* Recognize an RTL expression that is a valid memory address for
9305 an instruction.
9306 The MODE argument is the machine mode for the MEM expression
9307 that wants to use this address.
9308 Allow REG
9309 REG+disp
9310 REG+r0
9311 REG++
9312 --REG */
9313
1bb99877 9314static bool
cdeed45a
KK		 9315sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9316{
9317 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9318 return true;
9319 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9320 && ! TARGET_SHMEDIA
9321 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9322 return true;
9323 else if (GET_CODE (x) == PLUS
9324 && (mode != PSImode || reload_completed))
9325 {
9326 rtx xop0 = XEXP (x, 0);
9327 rtx xop1 = XEXP (x, 1);
9328
9329 if (GET_MODE_SIZE (mode) <= 8
9330 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9331 && sh_legitimate_index_p (mode, xop1))
9332 return true;
9333
9334 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode
9335 || ((xop0 == stack_pointer_rtx
9336 || xop0 == hard_frame_pointer_rtx)
9337 && REG_P (xop1) && REGNO (xop1) == R0_REG)
9338 || ((xop1 == stack_pointer_rtx
9339 || xop1 == hard_frame_pointer_rtx)
9340 && REG_P (xop0) && REGNO (xop0) == R0_REG))
9341 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4)
9342 || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8)
9343 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
9344 && TARGET_FMOVD && mode == DFmode)))
9345 {
9346 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9347 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9348 return true;
9349 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9350 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9351 return true;
9352 }
9353 }
9354
9355 return false;
9356}
9357\f
55eec660
AO		 9358/* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9359 isn't protected by a PIC unspec. */
1a66cd67 9360int
cf277499 9361nonpic_symbol_mentioned_p (rtx x)
1a66cd67
AO		 9362{
9363 register const char *fmt;
9364 register int i;
9365
fa5322fa
AO		 9366 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9367 || GET_CODE (x) == PC)
1a66cd67
AO		 9368 return 1;
9369
fa5322fa
AO		 9370 /* We don't want to look into the possible MEM location of a
9371 CONST_DOUBLE, since we're not going to use it, in general. */
9372 if (GET_CODE (x) == CONST_DOUBLE)
9373 return 0;
9374
1a66cd67 9375 if (GET_CODE (x) == UNSPEC
4773afa4
AO		 9376 && (XINT (x, 1) == UNSPEC_PIC
9377 || XINT (x, 1) == UNSPEC_GOT
9378 || XINT (x, 1) == UNSPEC_GOTOFF
fa5322fa 9379 || XINT (x, 1) == UNSPEC_GOTPLT
463f02cd
KK		 9380 || XINT (x, 1) == UNSPEC_GOTTPOFF
9381 || XINT (x, 1) == UNSPEC_DTPOFF
dc3ba671
RS		 9382 || XINT (x, 1) == UNSPEC_PLT
9383 || XINT (x, 1) == UNSPEC_SYMOFF
9384 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
832a3292 9385 return 0;
1a66cd67
AO		 9386
9387 fmt = GET_RTX_FORMAT (GET_CODE (x));
9388 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9389 {
9390 if (fmt[i] == 'E')
9391 {
9392 register int j;
9393
9394 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9395 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9396 return 1;
9397 }
9398 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9399 return 1;
9400 }
9401
9402 return 0;
9403}
9404
9405/* Convert a non-PIC address in `orig' to a PIC address using @GOT or
6f317ef3 9406 @GOTOFF in `reg'. */
1a66cd67 9407rtx
cf277499
SB		 9408legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
9409 rtx reg)
1a66cd67 9410{
81f40b79 9411 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
463f02cd
KK		 9412 return orig;
9413
1a66cd67 9414 if (GET_CODE (orig) == LABEL_REF
675ff4c7 9415 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
1a66cd67
AO		 9416 {
9417 if (reg == 0)
9418 reg = gen_reg_rtx (Pmode);
9419
9420 emit_insn (gen_symGOTOFF2reg (reg, orig));
9421 return reg;
9422 }
9423 else if (GET_CODE (orig) == SYMBOL_REF)
9424 {
9425 if (reg == 0)
9426 reg = gen_reg_rtx (Pmode);
9427
9428 emit_insn (gen_symGOT2reg (reg, orig));
9429 return reg;
9430 }
9431 return orig;
9432}
b91455de 9433
506d7b68
PB		 9434/* Try machine-dependent ways of modifying an illegitimate address
9435 to be legitimate. If we find one, return the new, valid address.
9436 Otherwise, return X.
9437
9438 For the SH, if X is almost suitable for indexing, but the offset is
9439 out of range, convert it into a normal form so that CSE has a chance
9440 of reducing the number of address registers used. */
9441
9442static rtx
9443sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
9444{
9445 if (flag_pic)
9446 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9447
9448 if (GET_CODE (x) == PLUS
9449 && (GET_MODE_SIZE (mode) == 4
9450 || GET_MODE_SIZE (mode) == 8)
f3536097 9451 && CONST_INT_P (XEXP (x, 1))
506d7b68
PB		 9452 && BASE_REGISTER_RTX_P (XEXP (x, 0))
9453 && ! TARGET_SHMEDIA
9454 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
9455 && ! (TARGET_SH2E && mode == SFmode))
9456 {
9457 rtx index_rtx = XEXP (x, 1);
9458 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9459 rtx sum;
9460
9461 /* On rare occasions, we might get an unaligned pointer
9462 that is indexed in a way to give an aligned address.
9463 Therefore, keep the lower two bits in offset_base. */
9464 /* Instead of offset_base 128..131 use 124..127, so that
9465 simple add suffices. */
9466 if (offset > 127)
9467 offset_base = ((offset + 4) & ~60) - 4;
9468 else
9469 offset_base = offset & ~60;
9470
9471 /* Sometimes the normal form does not suit DImode. We
9472 could avoid that by using smaller ranges, but that
9473 would give less optimized code when SImode is
9474 prevalent. */
9475 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9476 {
9477 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9478 GEN_INT (offset_base), NULL_RTX, 0,
9479 OPTAB_LIB_WIDEN);
9480
9481 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9482 }
9483 }
9484
9485 return x;
9486}
9487
b91455de
KK		 9488/* Mark the use of a constant in the literal table. If the constant
9489 has multiple labels, make it unique. */
c1b92d09 9490static rtx
cf277499 9491mark_constant_pool_use (rtx x)
b91455de
KK		 9492{
9493 rtx insn, lab, pattern;
9494
9495 if (x == NULL)
9496 return x;
9497
9498 switch (GET_CODE (x))
9499 {
9500 case LABEL_REF:
9501 x = XEXP (x, 0);
9502 case CODE_LABEL:
9503 break;
9504 default:
9505 return x;
9506 }
9507
9508 /* Get the first label in the list of labels for the same constant
9509 and delete another labels in the list. */
9510 lab = x;
9511 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
9512 {
f3536097 9513 if (!LABEL_P (insn)
b91455de
KK		 9514 || LABEL_REFS (insn) != NEXT_INSN (insn))
9515 break;
9516 lab = insn;
9517 }
9518
9519 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
9520 INSN_DELETED_P (insn) = 1;
9521
9522 /* Mark constants in a window. */
9523 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
9524 {
f3536097 9525 if (!NONJUMP_INSN_P (insn))
b91455de
KK		 9526 continue;
9527
9528 pattern = PATTERN (insn);
9529 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
9530 continue;
9531
9532 switch (XINT (pattern, 1))
9533 {
9534 case UNSPECV_CONST2:
9535 case UNSPECV_CONST4:
9536 case UNSPECV_CONST8:
9537 XVECEXP (pattern, 0, 1) = const1_rtx;
9538 break;
9539 case UNSPECV_WINDOW_END:
9540 if (XVECEXP (pattern, 0, 0) == x)
9541 return lab;
9542 break;
9543 case UNSPECV_CONST_END:
9544 return lab;
9545 default:
9546 break;
9547 }
9548 }
9549
9550 return lab;
9551}
6e7b03e1
AH		 9552\f
9553/* Return true if it's possible to redirect BRANCH1 to the destination
9554 of an unconditional jump BRANCH2. We only want to do this if the
9555 resulting branch will have a short displacement. */
f676971a 9556int
cf277499 9557sh_can_redirect_branch (rtx branch1, rtx branch2)
6e7b03e1
AH		 9558{
9559 if (flag_expensive_optimizations && simplejump_p (branch2))
9560 {
9561 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
9562 rtx insn;
9563 int distance;
f676971a
EC		 9564
9565 for (distance = 0, insn = NEXT_INSN (branch1);
9566 insn && distance < 256;
6e7b03e1
AH		 9567 insn = PREV_INSN (insn))
9568 {
f676971a 9569 if (insn == dest)
6e7b03e1
AH		 9570 return 1;
9571 else
9572 distance += get_attr_length (insn);
9573 }
f676971a
EC		 9574 for (distance = 0, insn = NEXT_INSN (branch1);
9575 insn && distance < 256;
6e7b03e1
AH		 9576 insn = NEXT_INSN (insn))
9577 {
f676971a 9578 if (insn == dest)
6e7b03e1
AH		 9579 return 1;
9580 else
9581 distance += get_attr_length (insn);
9582 }
9583 }
9584 return 0;
9585}
9586
5e7a8ee0 9587/* Return nonzero if register old_reg can be renamed to register new_reg. */
03b8ec29 9588int
cf277499
SB		 9589sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
9590 unsigned int new_reg)
03b8ec29 9591{
832a3292
KH		 9592 /* Interrupt functions can only use registers that have already been
9593 saved by the prologue, even if they would normally be
9594 call-clobbered. */
03b8ec29 9595
6fb5fa3c 9596 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
832a3292 9597 return 0;
03b8ec29 9598
832a3292 9599 return 1;
03b8ec29
DD		 9600}
9601
95c0af87 9602/* Function to update the integer COST
c237e94a
ZW		 9603 based on the relationship between INSN that is dependent on
9604 DEP_INSN through the dependence LINK. The default is to make no
9605 adjustment to COST. This can be used for example to specify to
9606 the scheduler that an output- or anti-dependence does not incur
95c0af87
JR		 9607 the same cost as a data-dependence. The return value should be
9608 the new value for COST. */
c237e94a 9609static int
cf277499 9610sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
c237e94a 9611{
c49439f1 9612 rtx reg, use_pat;
c237e94a 9613
2ad65b0e
SC		 9614 if (TARGET_SHMEDIA)
9615 {
9616 /* On SHmedia, if the dependence is an anti-dependence or
24746a42 9617 output-dependence, there is no cost. */
2ad65b0e 9618 if (REG_NOTE_KIND (link) != 0)
73a4d10b
R		 9619 {
9620 /* However, dependencies between target register loads and
9621 uses of the register in a subsequent block that are separated
9622 by a conditional branch are not modelled - we have to do with
9623 the anti-dependency between the target register load and the
9624 conditional branch that ends the current block. */
9625 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
9626 && GET_CODE (PATTERN (dep_insn)) == SET
9627 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
9628 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
9629 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
9630 {
9631 int orig_cost = cost;
9632 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
9633 rtx target = ((! note
9634 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
9635 ? insn : JUMP_LABEL (insn));
9636 /* On the likely path, the branch costs 1, on the unlikely path,
9637 it costs 3. */
9638 cost--;
9639 do
9640 target = next_active_insn (target);
9641 while (target && ! flow_dependent_p (target, dep_insn)
9642 && --cost > 0);
9643 /* If two branches are executed in immediate succession, with the
9644 first branch properly predicted, this causes a stall at the
9645 second branch, hence we won't need the target for the
9646 second branch for two cycles after the launch of the first
9647 branch. */
9648 if (cost > orig_cost - 2)
9649 cost = orig_cost - 2;
9650 }
9651 else
9652 cost = 0;
9653 }
2ad65b0e 9654
73a4d10b
R		 9655 else if (get_attr_is_mac_media (insn)
9656 && get_attr_is_mac_media (dep_insn))
9657 cost = 1;
9658
9659 else if (! reload_completed
9660 && GET_CODE (PATTERN (insn)) == SET
9661 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
9662 && GET_CODE (PATTERN (dep_insn)) == SET
9663 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
9664 && cost < 4)
9665 cost = 4;
9666 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
9667 that is needed at the target. */
9668 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
9669 && ! flow_dependent_p (insn, dep_insn))
9670 cost--;
2ad65b0e 9671 }
c49439f1 9672 else if (REG_NOTE_KIND (link) == 0)
c237e94a 9673 {
78d310c2
R		 9674 enum attr_type type;
9675 rtx dep_set;
c49439f1
R		 9676
9677 if (recog_memoized (insn) < 0
9678 || recog_memoized (dep_insn) < 0)
95c0af87 9679 return cost;
c49439f1 9680
78d310c2 9681 dep_set = single_set (dep_insn);
c49439f1 9682
78d310c2
R		 9683 /* The latency that we specify in the scheduling description refers
9684 to the actual output, not to an auto-increment register; for that,
9685 the latency is one. */
9686 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9687 {
9688 rtx set = single_set (insn);
9689
9690 if (set
9691 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9692 && (!MEM_P (SET_DEST (set))
9693 || !reg_mentioned_p (SET_DEST (dep_set),
9694 XEXP (SET_DEST (set), 0))))
9695 cost = 1;
9696 }
c237e94a
ZW		 9697 /* The only input for a call that is timing-critical is the
9698 function's address. */
f3536097 9699 if (CALL_P (insn))
c49439f1
R		 9700 {
9701 rtx call = PATTERN (insn);
9702
9703 if (GET_CODE (call) == PARALLEL)
9704 call = XVECEXP (call, 0 ,0);
9705 if (GET_CODE (call) == SET)
9706 call = SET_SRC (call);
f3536097 9707 if (GET_CODE (call) == CALL && MEM_P (XEXP (call, 0))
73a4d10b
R		 9708 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9709 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9710 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
78d310c2 9711 cost -= TARGET_SH4_300 ? 3 : 6;
c49439f1 9712 }
c237e94a
ZW		 9713 /* Likewise, the most timing critical input for an sfuncs call
9714 is the function address. However, sfuncs typically start
9715 using their arguments pretty quickly.
78d310c2
R		 9716 Assume a four cycle delay for SH4 before they are needed.
9717 Cached ST40-300 calls are quicker, so assume only a one
9718 cycle delay there.
9719 ??? Maybe we should encode the delays till input registers
9720 are needed by sfuncs into the sfunc call insn. */
c49439f1
R		 9721 /* All sfunc calls are parallels with at least four components.
9722 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9723 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9724 && XVECLEN (PATTERN (insn), 0) >= 4
9725 && (reg = sfunc_uses_reg (insn)))
9726 {
9727 if (! reg_set_p (reg, dep_insn))
78d310c2
R		 9728 cost -= TARGET_SH4_300 ? 1 : 4;
9729 }
9730 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9731 {
9732 enum attr_type dep_type = get_attr_type (dep_insn);
9733
9734 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9735 cost--;
9736 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9737 && (type = get_attr_type (insn)) != TYPE_CALL
9738 && type != TYPE_SFUNC)
9739 cost--;
9740 /* When the preceding instruction loads the shift amount of
9741 the following SHAD/SHLD, the latency of the load is increased
9742 by 1 cycle. */
9743 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9744 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
c6ac6e82 9745 && reg_overlap_mentioned_p (SET_DEST (dep_set),
78d310c2
R		 9746 XEXP (SET_SRC (single_set (insn)),
9747 1)))
9748 cost++;
9749 /* When an LS group instruction with a latency of less than
9750 3 cycles is followed by a double-precision floating-point
9751 instruction, FIPR, or FTRV, the latency of the first
9752 instruction is increased to 3 cycles. */
9753 else if (cost < 3
9754 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9755 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9756 cost = 3;
9757 /* The lsw register of a double-precision computation is ready one
9758 cycle earlier. */
9759 else if (reload_completed
9760 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9761 && (use_pat = single_set (insn))
9762 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9763 SET_SRC (use_pat)))
9764 cost -= 1;
9765
9766 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9767 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9768 cost -= 1;
9769 }
9770 else if (TARGET_SH4_300)
9771 {
9772 /* Stores need their input register two cycles later. */
9773 if (dep_set && cost >= 1
9774 && ((type = get_attr_type (insn)) == TYPE_STORE
9775 || type == TYPE_PSTORE
9776 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9777 {
9778 rtx set = single_set (insn);
9779
9780 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9781 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9782 {
9783 cost -= 2;
9784 /* But don't reduce the cost below 1 if the address depends
9785 on a side effect of dep_insn. */
9786 if (cost < 1
9787 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9788 cost = 1;
9789 }
9790 }
9791 }
c49439f1
R		 9792 }
9793 /* An anti-dependence penalty of two applies if the first insn is a double
9794 precision fadd / fsub / fmul. */
78d310c2
R		 9795 else if (!TARGET_SH4_300
9796 && REG_NOTE_KIND (link) == REG_DEP_ANTI
c49439f1 9797 && recog_memoized (dep_insn) >= 0
78d310c2
R		 9798 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9799 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
c49439f1
R		 9800 /* A lot of alleged anti-flow dependences are fake,
9801 so check this one is real. */
9802 && flow_dependent_p (dep_insn, insn))
c237e94a 9803 cost = 2;
c49439f1 9804
c237e94a
ZW		 9805 return cost;
9806}
3007d592 9807
c49439f1
R		 9808/* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9809 if DEP_INSN is anti-flow dependent on INSN. */
9810static int
cf277499 9811flow_dependent_p (rtx insn, rtx dep_insn)
c49439f1
R		 9812{
9813 rtx tmp = PATTERN (insn);
9814
9815 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9816 return tmp == NULL_RTX;
9817}
9818
9819/* A helper function for flow_dependent_p called through note_stores. */
9820static void
7bc980e1 9821flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
c49439f1
R		 9822{
9823 rtx * pinsn = (rtx *) data;
9824
9825 if (*pinsn && reg_referenced_p (x, *pinsn))
9826 *pinsn = NULL_RTX;
9827}
9828
b48f503c 9829/* For use by sh_allocate_initial_value. Note that sh.md contains some
3007d592
R		 9830 'special function' patterns (type sfunc) that clobber pr, but that
9831 do not look like function calls to leaf_function_p. Hence we must
9832 do this extra check. */
b48f503c 9833static int
cf277499 9834sh_pr_n_sets (void)
3007d592 9835{
6fb5fa3c 9836 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
3007d592 9837}
fa5322fa 9838
b48f503c
KK		 9839/* Return where to allocate pseudo for a given hard register initial
9840 value. */
9841static rtx
9842sh_allocate_initial_value (rtx hard_reg)
9843{
9844 rtx x;
9845
9846 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
9847 {
9848 if (current_function_is_leaf
9849 && ! sh_pr_n_sets ()
9850 && ! (TARGET_SHCOMPACT
38173d38 9851 && ((crtl->args.info.call_cookie
b48f503c 9852 & ~ CALL_COOKIE_RET_TRAMP (1))
e3b5732b 9853 || crtl->saves_all_registers)))
b48f503c
KK		 9854 x = hard_reg;
9855 else
57d38024 9856 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
b48f503c
KK		 9857 }
9858 else
9859 x = NULL_RTX;
9860
9861 return x;
9862}
9863
c49439f1
R		 9864/* This function returns "2" to indicate dual issue for the SH4
9865 processor. To be used by the DFA pipeline description. */
fae15c93 9866static int
832a3292 9867sh_issue_rate (void)
fae15c93 9868{
c49439f1
R		 9869 if (TARGET_SUPERSCALAR)
9870 return 2;
9871 else
9872 return 1;
fae15c93
VM		 9873}
9874
58565a33
SKG		 9875/* Functions for ready queue reordering for sched1. */
9876
9877/* Get weight for mode for a set x. */
9878static short
508ea1c5 9879find_set_regmode_weight (rtx x, enum machine_mode mode)
58565a33
SKG		 9880{
9881 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9882 return 1;
9883 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9884 {
f3536097 9885 if (REG_P (SET_DEST (x)))
58565a33
SKG		 9886 {
9887 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9888 return 1;
9889 else
9890 return 0;
9891 }
9892 return 1;
9893 }
9894 return 0;
9895}
9896
9897/* Get regmode weight for insn. */
9898static short
508ea1c5 9899find_insn_regmode_weight (rtx insn, enum machine_mode mode)
58565a33
SKG		 9900{
9901 short reg_weight = 0;
9902 rtx x;
9903
9904 /* Increment weight for each register born here. */
9905 x = PATTERN (insn);
9906 reg_weight += find_set_regmode_weight (x, mode);
9907 if (GET_CODE (x) == PARALLEL)
9908 {
9909 int j;
9910 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9911 {
9912 x = XVECEXP (PATTERN (insn), 0, j);
9913 reg_weight += find_set_regmode_weight (x, mode);
9914 }
9915 }
9916 /* Decrement weight for each register that dies here. */
9917 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9918 {
9919 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9920 {
9921 rtx note = XEXP (x, 0);
f3536097 9922 if (REG_P (note) && GET_MODE (note) == mode)
58565a33
SKG		 9923 reg_weight--;
9924 }
9925 }
9926 return reg_weight;
9927}
9928
9929/* Calculate regmode weights for all insns of a basic block. */
9930static void
c6d56443 9931find_regmode_weight (basic_block b, enum machine_mode mode)
58565a33
SKG		 9932{
9933 rtx insn, next_tail, head, tail;
9934
c6d56443 9935 get_ebb_head_tail (b, b, &head, &tail);
58565a33
SKG		 9936 next_tail = NEXT_INSN (tail);
9937
9938 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9939 {
9940 /* Handle register life information. */
9941 if (!INSN_P (insn))
9942 continue;
9943
9944 if (mode == SFmode)
9945 INSN_REGMODE_WEIGHT (insn, mode) =
9946 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
9947 else if (mode == SImode)
9948 INSN_REGMODE_WEIGHT (insn, mode) =
9949 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
9950 }
9951}
9952
9953/* Comparison function for ready queue sorting. */
9954static int
508ea1c5 9955rank_for_reorder (const void *x, const void *y)
58565a33
SKG		 9956{
9957 rtx tmp = *(const rtx *) y;
9958 rtx tmp2 = *(const rtx *) x;
9959
9960 /* The insn in a schedule group should be issued the first. */
9961 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
9962 return SCHED_GROUP_P (tmp2) ? 1 : -1;
9963
f676971a 9964 /* If insns are equally good, sort by INSN_LUID (original insn order), This
58565a33
SKG		 9965 minimizes instruction movement, thus minimizing sched's effect on
9966 register pressure. */
9967 return INSN_LUID (tmp) - INSN_LUID (tmp2);
9968}
9969
9970/* Resort the array A in which only element at index N may be out of order. */
9971static void
508ea1c5 9972swap_reorder (rtx *a, int n)
58565a33
SKG		 9973{
9974 rtx insn = a[n - 1];
9975 int i = n - 2;
9976
9977 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
9978 {
9979 a[i + 1] = a[i];
9980 i -= 1;
9981 }
9982 a[i + 1] = insn;
9983}
9984
832a3292
KH		 9985#define SCHED_REORDER(READY, N_READY) \
9986 do \
9987 { \
9988 if ((N_READY) == 2) \
9989 swap_reorder (READY, N_READY); \
9990 else if ((N_READY) > 2) \
9991 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
9992 } \
9993 while (0)
58565a33
SKG		 9994
9995/* Sort the ready list READY by ascending priority, using the SCHED_REORDER
9996 macro. */
9997static void
508ea1c5 9998ready_reorder (rtx *ready, int nready)
58565a33
SKG		 9999{
10000 SCHED_REORDER (ready, nready);
10001}
10002
6fb5fa3c
DB		 10003/* Count life regions of r0 for a block. */
10004static int
10005find_r0_life_regions (basic_block b)
10006{
10007 rtx end, insn;
10008 rtx pset;
10009 rtx r0_reg;
10010 int live;
10011 int set;
10012 int death = 0;
10013
89a95777 10014 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
6fb5fa3c
DB		 10015 {
10016 set = 1;
10017 live = 1;
10018 }
10019 else
10020 {
10021 set = 0;
10022 live = 0;
10023 }
10024
10025 insn = BB_HEAD (b);
10026 end = BB_END (b);
10027 r0_reg = gen_rtx_REG (SImode, R0_REG);
10028 while (1)
10029 {
10030 if (INSN_P (insn))
10031 {
10032 if (find_regno_note (insn, REG_DEAD, R0_REG))
10033 {
10034 death++;
10035 live = 0;
10036 }
10037 if (!live
10038 && (pset = single_set (insn))
10039 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
10040 && !find_regno_note (insn, REG_UNUSED, R0_REG))
10041 {
10042 set++;
10043 live = 1;
10044 }
10045 }
10046 if (insn == end)
10047 break;
10048 insn = NEXT_INSN (insn);
10049 }
10050 return set - death;
10051}
10052
58565a33
SKG		 10053/* Calculate regmode weights for all insns of all basic block. */
10054static void
508ea1c5
KH		 10055sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
10056 int verbose ATTRIBUTE_UNUSED,
10057 int old_max_uid)
58565a33
SKG		 10058{
10059 basic_block b;
10060
10061 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
10062 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
6fb5fa3c 10063 r0_life_regions = 0;
58565a33
SKG		 10064
10065 FOR_EACH_BB_REVERSE (b)
10066 {
c6d56443
KK		 10067 find_regmode_weight (b, SImode);
10068 find_regmode_weight (b, SFmode);
6fb5fa3c
DB		 10069 if (!reload_completed)
10070 r0_life_regions += find_r0_life_regions (b);
58565a33
SKG		 10071 }
10072
10073 CURR_REGMODE_PRESSURE (SImode) = 0;
10074 CURR_REGMODE_PRESSURE (SFmode) = 0;
10075
10076}
10077
10078/* Cleanup. */
10079static void
508ea1c5
KH		 10080sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
10081 int verbose ATTRIBUTE_UNUSED)
58565a33
SKG		 10082{
10083 if (regmode_weight[0])
10084 {
10085 free (regmode_weight[0]);
10086 regmode_weight[0] = NULL;
10087 }
10088 if (regmode_weight[1])
10089 {
10090 free (regmode_weight[1]);
10091 regmode_weight[1] = NULL;
10092 }
10093}
10094
b0fbea13
KK		 10095/* The scalar modes supported differs from the default version in TImode
10096 for 32-bit SHMEDIA. */
10097static bool
10098sh_scalar_mode_supported_p (enum machine_mode mode)
10099{
10100 if (TARGET_SHMEDIA32 && mode == TImode)
10101 return false;
10102
10103 return default_scalar_mode_supported_p (mode);
10104}
10105
58565a33
SKG		 10106/* Cache the can_issue_more so that we can return it from reorder2. Also,
10107 keep count of register pressures on SImode and SFmode. */
10108static int
508ea1c5
KH		 10109sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
10110 int sched_verbose ATTRIBUTE_UNUSED,
10111 rtx insn,
10112 int can_issue_more)
58565a33
SKG		 10113{
10114 if (GET_CODE (PATTERN (insn)) != USE
10115 && GET_CODE (PATTERN (insn)) != CLOBBER)
10116 cached_can_issue_more = can_issue_more - 1;
10117 else
10118 cached_can_issue_more = can_issue_more;
10119
10120 if (reload_completed)
10121 return cached_can_issue_more;
10122
10123 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
10124 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
10125
10126 return cached_can_issue_more;
10127}
10128
10129static void
508ea1c5
KH		 10130sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
10131 int verbose ATTRIBUTE_UNUSED,
10132 int veclen ATTRIBUTE_UNUSED)
58565a33
SKG		 10133{
10134 CURR_REGMODE_PRESSURE (SImode) = 0;
10135 CURR_REGMODE_PRESSURE (SFmode) = 0;
10136}
10137
10138/* Some magic numbers. */
10139/* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10140 functions that already have high pressure on r0. */
10141#define R0_MAX_LIFE_REGIONS 2
4ee31f1e 10142/* Register Pressure thresholds for SImode and SFmode registers. */
58565a33
SKG		 10143#define SIMODE_MAX_WEIGHT 5
10144#define SFMODE_MAX_WEIGHT 10
10145
10146/* Return true if the pressure is high for MODE. */
10147static short
508ea1c5 10148high_pressure (enum machine_mode mode)
58565a33
SKG		 10149{
10150 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10151 functions that already have high pressure on r0. */
6fb5fa3c
DB		 10152 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
10153 return 1;
58565a33
SKG		 10154
10155 if (mode == SFmode)
10156 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
10157 else
10158 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
10159}
10160
10161/* Reorder ready queue if register pressure is high. */
10162static int
508ea1c5
KH		 10163sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
10164 int sched_verbose ATTRIBUTE_UNUSED,
10165 rtx *ready,
10166 int *n_readyp,
10167 int clock_var ATTRIBUTE_UNUSED)
58565a33
SKG		 10168{
10169 if (reload_completed)
10170 return sh_issue_rate ();
10171
10172 if (high_pressure (SFmode) || high_pressure (SImode))
10173 {
10174 ready_reorder (ready, *n_readyp);
10175 }
10176
10177 return sh_issue_rate ();
10178}
10179
10180/* Skip cycles if the current register pressure is high. */
f676971a 10181static int
508ea1c5
KH		 10182sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
10183 int sched_verbose ATTRIBUTE_UNUSED,
10184 rtx *ready ATTRIBUTE_UNUSED,
10185 int *n_readyp ATTRIBUTE_UNUSED,
10186 int clock_var ATTRIBUTE_UNUSED)
58565a33
SKG		 10187{
10188 if (reload_completed)
10189 return cached_can_issue_more;
10190
f676971a 10191 if (high_pressure(SFmode) || high_pressure (SImode))
58565a33
SKG		 10192 skip_cycles = 1;
10193
10194 return cached_can_issue_more;
10195}
10196
10197/* Skip cycles without sorting the ready queue. This will move insn from
10198 Q->R. If this is the last cycle we are skipping; allow sorting of ready
f676971a 10199 queue by sh_reorder. */
58565a33 10200
f676971a
EC		 10201/* Generally, skipping these many cycles are sufficient for all insns to move
10202 from Q -> R. */
10203#define MAX_SKIPS 8
58565a33
SKG		 10204
10205static int
508ea1c5
KH		 10206sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
10207 int sched_verbose ATTRIBUTE_UNUSED,
10208 rtx insn ATTRIBUTE_UNUSED,
10209 int last_clock_var,
10210 int clock_var,
10211 int *sort_p)
58565a33
SKG		 10212{
10213 if (reload_completed)
832a3292 10214 return 0;
58565a33 10215
f676971a 10216 if (skip_cycles)
58565a33 10217 {
832a3292
KH		 10218 if ((clock_var - last_clock_var) < MAX_SKIPS)
10219 {
10220 *sort_p = 0;
10221 return 1;
10222 }
10223 /* If this is the last cycle we are skipping, allow reordering of R. */
10224 if ((clock_var - last_clock_var) == MAX_SKIPS)
10225 {
10226 *sort_p = 1;
10227 return 1;
10228 }
58565a33 10229 }
58565a33
SKG		 10230
10231 skip_cycles = 0;
10232
10233 return 0;
10234}
10235
fa5322fa
AO		 10236/* SHmedia requires registers for branches, so we can't generate new
10237 branches past reload. */
10238static bool
cf277499 10239sh_cannot_modify_jumps_p (void)
fa5322fa
AO		 10240{
10241 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
10242}
10243
81f40b79 10244static enum reg_class
fe3ad572
SC		 10245sh_target_reg_class (void)
10246{
10247 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
10248}
10249
10250static bool
10251sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
10252{
73a4d10b 10253 HARD_REG_SET dummy;
cb3d3842 10254#if 0
73a4d10b 10255 rtx insn;
cb3d3842 10256#endif
73a4d10b
R		 10257
10258 if (! shmedia_space_reserved_for_target_registers)
10259 return 0;
10260 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
10261 return 0;
10262 if (calc_live_regs (&dummy) >= 6 * 8)
10263 return 1;
73a4d10b 10264 return 0;
fe3ad572
SC		 10265}
10266
fa5322fa 10267static bool
3101faab 10268sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
fa5322fa 10269{
61f71b34 10270 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
fa5322fa 10271}
ca903bba 10272\f
f676971a 10273/*
ca903bba
R		 10274 On the SH1..SH4, the trampoline looks like
10275 2 0002 D202 mov.l l2,r2
10276 1 0000 D301 mov.l l1,r3
10277 3 0004 422B jmp @r2
10278 4 0006 0009 nop
10279 5 0008 00000000 l1: .long area
10280 6 000c 00000000 l2: .long function
10281
10282 SH5 (compact) uses r1 instead of r3 for the static chain. */
10283
10284
10285/* Emit RTL insns to initialize the variable parts of a trampoline.
10286 FNADDR is an RTX for the address of the function's pure code.
10287 CXT is an RTX for the static chain value for the function. */
10288
10289void
cf277499 10290sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
ca903bba 10291{
57d38024
R		 10292 rtx tramp_mem = gen_frame_mem (BLKmode, tramp);
10293
ca903bba
R		 10294 if (TARGET_SHMEDIA64)
10295 {
10296 rtx tramp_templ;
10297 int fixed_len;
10298
10299 rtx movi1 = GEN_INT (0xcc000010);
10300 rtx shori1 = GEN_INT (0xc8000010);
10301 rtx src, dst;
10302
10303 /* The following trampoline works within a +- 128 KB range for cxt:
10304 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10305 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10306 gettr tr1,r1; blink tr0,r63 */
10307 /* Address rounding makes it hard to compute the exact bounds of the
10308 offset for this trampoline, but we have a rather generous offset
10309 range, so frame_offset should do fine as an upper bound. */
10310 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
10311 {
10312 /* ??? could optimize this trampoline initialization
10313 by writing DImode words with two insns each. */
10314 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
10315 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
10316 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
10317 insn = gen_rtx_AND (DImode, insn, mask);
10318 /* Or in ptb/u .,tr1 pattern */
10319 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
10320 insn = force_operand (insn, NULL_RTX);
10321 insn = gen_lowpart (SImode, insn);
57d38024 10322 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
ca903bba
R		 10323 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
10324 insn = gen_rtx_AND (DImode, insn, mask);
10325 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
10326 insn = gen_lowpart (SImode, insn);
57d38024 10327 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
ca903bba
R		 10328 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
10329 insn = gen_rtx_AND (DImode, insn, mask);
10330 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10331 insn = gen_lowpart (SImode, insn);
57d38024 10332 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
ca903bba
R		 10333 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
10334 insn = gen_rtx_AND (DImode, insn, mask);
10335 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10336 insn = gen_lowpart (SImode, insn);
57d38024 10337 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
ca903bba
R		 10338 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
10339 insn = gen_rtx_AND (DImode, insn, mask);
10340 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10341 insn = gen_lowpart (SImode, insn);
57d38024
R		 10342 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
10343 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
ca903bba 10344 GEN_INT (0x6bf10600));
57d38024 10345 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
ca903bba 10346 GEN_INT (0x4415fc10));
57d38024 10347 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
ca903bba
R		 10348 GEN_INT (0x4401fff0));
10349 emit_insn (gen_ic_invalidate_line (tramp));
10350 return;
10351 }
10352 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
10353 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
10354
10355 tramp_templ = gen_datalabel_ref (tramp_templ);
57d38024
R		 10356 dst = tramp_mem;
10357 src = gen_const_mem (BLKmode, tramp_templ);
ca903bba
R		 10358 set_mem_align (dst, 256);
10359 set_mem_align (src, 64);
44bb111a 10360 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
ca903bba 10361
57d38024
R		 10362 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
10363 emit_move_insn (adjust_address (tramp_mem, Pmode,
10364 fixed_len + GET_MODE_SIZE (Pmode)),
ca903bba
R		 10365 cxt);
10366 emit_insn (gen_ic_invalidate_line (tramp));
10367 return;
10368 }
10369 else if (TARGET_SHMEDIA)
10370 {
10371 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10372 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10373 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
10374 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
10375 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
825db093 10376 rotated 10 right, and higher 16 bit of every 32 selected. */
ca903bba
R		 10377 rtx movishori
10378 = force_reg (V2HImode, (simplify_gen_subreg
10379 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
10380 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
10381 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
10382
10383 tramp = force_reg (Pmode, tramp);
10384 fnaddr = force_reg (SImode, fnaddr);
10385 cxt = force_reg (SImode, cxt);
10386 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
10387 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
10388 movishori));
f1e2239f 10389 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
ca903bba 10390 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
a556fd39 10391 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
57d38024 10392 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
ca903bba
R		 10393 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
10394 gen_rtx_SUBREG (V2HImode, cxt, 0),
10395 movishori));
f1e2239f 10396 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
ca903bba 10397 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
a556fd39 10398 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
ca903bba
R		 10399 if (TARGET_LITTLE_ENDIAN)
10400 {
10401 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
10402 emit_insn (gen_mextr4 (quad2, cxtload, blink));
10403 }
10404 else
10405 {
10406 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
10407 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
10408 }
57d38024
R		 10409 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
10410 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
ca903bba
R		 10411 emit_insn (gen_ic_invalidate_line (tramp));
10412 return;
10413 }
10414 else if (TARGET_SHCOMPACT)
10415 {
10416 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
10417 return;
10418 }
57d38024 10419 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
ca903bba
R		 10420 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
10421 SImode));
57d38024 10422 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
ca903bba
R		 10423 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
10424 SImode));
57d38024
R		 10425 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
10426 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
ca903bba
R		 10427 if (TARGET_HARVARD)
10428 {
dc557046 10429 if (!TARGET_INLINE_IC_INVALIDATE
6f8eec29 10430 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
73a4d10b
R		 10431 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10432 FUNCTION_ORDINARY),
b757d36f 10433 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
ca903bba
R		 10434 else
10435 emit_insn (gen_ic_invalidate_line (tramp));
10436 }
10437}
10438
4977bab6
ZW		 10439/* FIXME: This is overly conservative. A SHcompact function that
10440 receives arguments ``by reference'' will have them stored in its
10441 own stack frame, so it must not pass pointers or references to
10442 these arguments to other functions by means of sibling calls. */
73a4d10b
R		 10443/* If PIC, we cannot make sibling calls to global functions
10444 because the PLT requires r12 to be live. */
4977bab6 10445static bool
cf277499 10446sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
4977bab6 10447{
73a4d10b 10448 return (1
4977bab6 10449 && (! TARGET_SHCOMPACT
38173d38 10450 || crtl->args.info.stack_regs == 0)
73a4d10b
R		 10451 && ! sh_cfun_interrupt_handler_p ()
10452 && (! flag_pic
10453 || (decl && ! TREE_PUBLIC (decl))
10454 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
4977bab6 10455}
c1b92d09
R		 10456\f
10457/* Machine specific built-in functions. */
10458
10459struct builtin_description
10460{
10461 const enum insn_code icode;
10462 const char *const name;
10463 int signature;
10464};
10465
10466/* describe number and signedness of arguments; arg[0] == result
10467 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
3b962ea0 10468/* 9: 64-bit pointer, 10: 32-bit pointer */
c1b92d09
R		 10469static const char signature_args[][4] =
10470{
10471#define SH_BLTIN_V2SI2 0
10472 { 4, 4 },
10473#define SH_BLTIN_V4HI2 1
10474 { 4, 4 },
10475#define SH_BLTIN_V2SI3 2
10476 { 4, 4, 4 },
10477#define SH_BLTIN_V4HI3 3
10478 { 4, 4, 4 },
10479#define SH_BLTIN_V8QI3 4
10480 { 4, 4, 4 },
10481#define SH_BLTIN_MAC_HISI 5
10482 { 1, 4, 4, 1 },
10483#define SH_BLTIN_SH_HI 6
10484 { 4, 4, 1 },
10485#define SH_BLTIN_SH_SI 7
10486 { 4, 4, 1 },
10487#define SH_BLTIN_V4HI2V2SI 8
10488 { 4, 4, 4 },
10489#define SH_BLTIN_V4HI2V8QI 9
10490 { 4, 4, 4 },
10491#define SH_BLTIN_SISF 10
10492 { 4, 2 },
10493#define SH_BLTIN_LDUA_L 11
73a4d10b 10494 { 2, 10 },
c1b92d09 10495#define SH_BLTIN_LDUA_Q 12
73a4d10b 10496 { 1, 10 },
c1b92d09 10497#define SH_BLTIN_STUA_L 13
73a4d10b 10498 { 0, 10, 2 },
c1b92d09 10499#define SH_BLTIN_STUA_Q 14
73a4d10b
R		 10500 { 0, 10, 1 },
10501#define SH_BLTIN_LDUA_L64 15
10502 { 2, 9 },
10503#define SH_BLTIN_LDUA_Q64 16
10504 { 1, 9 },
10505#define SH_BLTIN_STUA_L64 17
10506 { 0, 9, 2 },
10507#define SH_BLTIN_STUA_Q64 18
10508 { 0, 9, 1 },
10509#define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10510#define SH_BLTIN_2 19
10511#define SH_BLTIN_SU 19
c1b92d09 10512 { 1, 2 },
73a4d10b
R		 10513#define SH_BLTIN_3 20
10514#define SH_BLTIN_SUS 20
c1b92d09 10515 { 2, 2, 1 },
73a4d10b 10516#define SH_BLTIN_PSSV 21
c1b92d09 10517 { 0, 8, 2, 2 },
73a4d10b
R		 10518#define SH_BLTIN_XXUU 22
10519#define SH_BLTIN_UUUU 22
c1b92d09 10520 { 1, 1, 1, 1 },
73a4d10b 10521#define SH_BLTIN_PV 23
c1b92d09
R		 10522 { 0, 8 },
10523};
24746a42 10524/* mcmv: operands considered unsigned. */
c1b92d09 10525/* mmulsum_wq, msad_ubq: result considered unsigned long long. */
24746a42
KH		 10526/* mperm: control value considered unsigned int. */
10527/* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
c1b92d09
R		 10528/* mshards_q: returns signed short. */
10529/* nsb: takes long long arg, returns unsigned char. */
10530static const struct builtin_description bdesc[] =
10531{
10532 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
10533 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
10534 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
10535 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
10536 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
10537 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
10538 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
73a4d10b 10539 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
c1b92d09
R		 10540 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
10541 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
10542 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
10543 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
10544 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
10545 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
10546 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
10547 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
10548 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
10549 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
73a4d10b
R		 10550 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 },
10551 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 },
10552 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 },
10553 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 },
10554 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 },
10555 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 },
10556 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 },
c1b92d09
R		 10557 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
10558 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
10559 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
10560 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
10561 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
10562 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
10563 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
10564 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
10565 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
10566 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
10567 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
10568 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
10569 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
10570 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
10571 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
10572 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
10573 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
10574 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
10575 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
10576 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
10577 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
10578 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
10579 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
10580 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
10581 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
10582 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
10583 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
10584 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
10585 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
10586 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
10587 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
10588 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
10589 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
10590 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
10591 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
10592 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
73a4d10b
R		 10593 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 },
10594 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 },
10595 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 },
c1b92d09 10596 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
c1b92d09
R		 10597 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
10598 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
10599 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
10600 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
10601 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
10602 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
10603 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
10604 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
73a4d10b
R		 10605 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 },
10606 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 },
10607 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 },
10608 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 },
10609 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 },
10610 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 },
10611 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 },
10612 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 },
c1b92d09
R		 10613 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
10614 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
73a4d10b 10615 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
c1b92d09
R		 10616};
10617
10618static void
cf277499 10619sh_media_init_builtins (void)
c1b92d09
R		 10620{
10621 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
10622 const struct builtin_description *d;
10623
a3acdc0c 10624 memset (shared, 0, sizeof shared);
e97a46ce 10625 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
c1b92d09 10626 {
73a4d10b 10627 tree type, arg_type = 0;
c1b92d09
R		 10628 int signature = d->signature;
10629 int i;
10630
10631 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
10632 type = shared[signature];
10633 else
10634 {
10635 int has_result = signature_args[signature][0] != 0;
10636
73a4d10b
R		 10637 if ((signature_args[signature][1] & 8)
10638 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
10639 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
c1b92d09
R		 10640 continue;
10641 if (! TARGET_FPU_ANY
10642 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
10643 continue;
10644 type = void_list_node;
10645 for (i = 3; ; i--)
10646 {
10647 int arg = signature_args[signature][i];
10648 int opno = i - 1 + has_result;
10649
73a4d10b 10650 if (arg & 8)
c1b92d09
R		 10651 arg_type = ptr_type_node;
10652 else if (arg)
73a4d10b
R		 10653 arg_type = (*lang_hooks.types.type_for_mode)
10654 (insn_data[d->icode].operand[opno].mode,
10655 (arg & 1));
c1b92d09
R		 10656 else if (i)
10657 continue;
10658 else
10659 arg_type = void_type_node;
10660 if (i == 0)
10661 break;
10662 type = tree_cons (NULL_TREE, arg_type, type);
10663 }
10664 type = build_function_type (arg_type, type);
10665 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10666 shared[signature] = type;
10667 }
c79efc4d
RÁE		 10668 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10669 NULL, NULL_TREE);
c1b92d09
R		 10670 }
10671}
10672
f676971a
EC		 10673/* Implements target hook vector_mode_supported_p. */
10674bool
10675sh_vector_mode_supported_p (enum machine_mode mode)
10676{
10677 if (TARGET_FPU_ANY
10678 && ((mode == V2SFmode)
10679 || (mode == V4SFmode)
10680 || (mode == V16SFmode)))
10681 return true;
10682
10683 else if (TARGET_SHMEDIA
10684 && ((mode == V8QImode)
10685 || (mode == V2HImode)
10686 || (mode == V4HImode)
10687 || (mode == V2SImode)))
10688 return true;
10689
10690 return false;
10691}
10692
a1c496cb
EC		 10693/* Implements target hook dwarf_calling_convention. Return an enum
10694 of dwarf_calling_convention. */
10695int
3101faab 10696sh_dwarf_calling_convention (const_tree func)
a1c496cb
EC		 10697{
10698 if (sh_attr_renesas_p (func))
29832164 10699 return DW_CC_GNU_renesas_sh;
a1c496cb
EC		 10700
10701 return DW_CC_normal;
10702}
10703
c1b92d09 10704static void
cf277499 10705sh_init_builtins (void)
c1b92d09
R		 10706{
10707 if (TARGET_SHMEDIA)
10708 sh_media_init_builtins ();
10709}
10710
10711/* Expand an expression EXP that calls a built-in function,
10712 with result going to TARGET if that's convenient
10713 (and in mode MODE if that's convenient).
10714 SUBTARGET may be used as the target for computing one of EXP's operands.
10715 IGNORE is nonzero if the value is to be ignored. */
10716
10717static rtx
cf277499
SB		 10718sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10719 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
c1b92d09 10720{
5039610b 10721 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
c1b92d09
R		 10722 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10723 const struct builtin_description *d = &bdesc[fcode];
10724 enum insn_code icode = d->icode;
10725 int signature = d->signature;
10726 enum machine_mode tmode = VOIDmode;
10727 int nop = 0, i;
10728 rtx op[4];
73a4d10b 10729 rtx pat = 0;
c1b92d09
R		 10730
10731 if (signature_args[signature][0])
10732 {
10733 if (ignore)
10734 return 0;
10735
10736 tmode = insn_data[icode].operand[0].mode;
10737 if (! target
10738 || GET_MODE (target) != tmode
10739 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10740 target = gen_reg_rtx (tmode);
10741 op[nop++] = target;
10742 }
10743 else
10744 target = 0;
10745
10746 for (i = 1; i <= 3; i++, nop++)
10747 {
10748 tree arg;
10749 enum machine_mode opmode, argmode;
73a4d10b 10750 tree optype;
c1b92d09
R		 10751
10752 if (! signature_args[signature][i])
10753 break;
5039610b 10754 arg = CALL_EXPR_ARG (exp, i - 1);
3578cf63
R		 10755 if (arg == error_mark_node)
10756 return const0_rtx;
73a4d10b
R		 10757 if (signature_args[signature][i] & 8)
10758 {
10759 opmode = ptr_mode;
10760 optype = ptr_type_node;
10761 }
10762 else
10763 {
10764 opmode = insn_data[icode].operand[nop].mode;
10765 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10766 }
c1b92d09
R		 10767 argmode = TYPE_MODE (TREE_TYPE (arg));
10768 if (argmode != opmode)
73a4d10b 10769 arg = build1 (NOP_EXPR, optype, arg);
b757d36f 10770 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
c1b92d09
R		 10771 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10772 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10773 }
10774
10775 switch (nop)
10776 {
10777 case 1:
10778 pat = (*insn_data[d->icode].genfun) (op[0]);
10779 break;
10780 case 2:
10781 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10782 break;
10783 case 3:
10784 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10785 break;
10786 case 4:
10787 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10788 break;
95c0af87 10789 default:
f5b9e7c9 10790 gcc_unreachable ();
c1b92d09
R		 10791 }
10792 if (! pat)
10793 return 0;
10794 emit_insn (pat);
10795 return target;
10796}
0ac78517
R		 10797
10798void
cf277499 10799sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
0ac78517
R		 10800{
10801 rtx sel0 = const0_rtx;
10802 rtx sel1 = const1_rtx;
cf277499 10803 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
0ac78517
R		 10804 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
10805
10806 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
10807 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
10808}
10809
10810void
cf277499 10811sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
0ac78517 10812{
0ac78517
R		 10813 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
10814
f8be3f56
KK		 10815 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
10816 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
0ac78517
R		 10817}
10818
347146a4
KK		 10819/* Return true if hard register REGNO can hold a value of machine-mode MODE.
10820 We can allow any mode in any general register. The special registers
10821 only allow SImode. Don't allow any mode in the PR.
10822
10823 We cannot hold DCmode values in the XD registers because alter_reg
10824 handles subregs of them incorrectly. We could work around this by
10825 spacing the XD registers like the DR registers, but this would require
10826 additional memory in every compilation to hold larger register vectors.
10827 We could hold SFmode / SCmode values in XD registers, but that
10828 would require a tertiary reload when reloading from / to memory,
10829 and a secondary reload to reload from / to general regs; that
10830 seems to be a loosing proposition.
10831
10832 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
10833 it won't be ferried through GP registers first. */
10834
10835bool
10836sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
10837{
10838 if (SPECIAL_REGISTER_P (regno))
10839 return mode == SImode;
10840
10841 if (regno == FPUL_REG)
10842 return (mode == SImode || mode == SFmode);
10843
10844 if (FP_REGISTER_P (regno) && mode == SFmode)
10845 return true;
10846
10847 if (mode == V2SFmode)
10848 {
10849 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
10850 || GENERAL_REGISTER_P (regno)))
10851 return true;
10852 else
10853 return false;
10854 }
10855
10856 if (mode == V4SFmode)
10857 {
10858 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
10859 || GENERAL_REGISTER_P (regno))
10860 return true;
10861 else
10862 return false;
10863 }
10864
10865 if (mode == V16SFmode)
10866 {
10867 if (TARGET_SHMEDIA)
10868 {
10869 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
10870 return true;
10871 else
10872 return false;
10873 }
10874 else
10875 return regno == FIRST_XD_REG;
10876 }
10877
10878 if (FP_REGISTER_P (regno))
10879 {
10880 if (mode == SFmode
10881 || mode == SImode
10882 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
10883 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
10884 || mode == DCmode
10885 || (TARGET_SHMEDIA
10886 && (mode == DFmode || mode == DImode
10887 || mode == V2SFmode || mode == TImode)))
10888 && ((regno - FIRST_FP_REG) & 1) == 0)
10889 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
10890 && ((regno - FIRST_FP_REG) & 3) == 0))
10891 return true;
10892 else
10893 return false;
10894 }
10895
10896 if (XD_REGISTER_P (regno))
10897 return mode == DFmode;
10898
10899 if (TARGET_REGISTER_P (regno))
10900 return (mode == DImode || mode == SImode || mode == PDImode);
10901
10902 if (regno == PR_REG)
10903 return mode == SImode;
10904
10905 if (regno == FPSCR_REG)
10906 return mode == PSImode;
10907
10908 /* FIXME. This works around PR target/37633 for -O0. */
10909 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
10910 {
10911 unsigned int n = GET_MODE_SIZE (mode) / 8;
10912
10913 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
10914 && regno <= FIRST_GENERAL_REG + 14)
10915 return false;
10916 }
10917
10918 return true;
10919}
10920
cff9f8d5
AH		 10921/* Return the class of registers for which a mode change from FROM to TO
10922 is invalid. */
b0c42aed 10923bool
cf277499 10924sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
0a2aaacc 10925 enum reg_class rclass)
cff9f8d5 10926{
312209c6
AO		 10927 /* We want to enable the use of SUBREGs as a means to
10928 VEC_SELECT a single element of a vector. */
10929 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
0a2aaacc 10930 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
312209c6 10931
cff9f8d5
AH		 10932 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10933 {
832a3292
KH		 10934 if (TARGET_LITTLE_ENDIAN)
10935 {
10936 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
0a2aaacc 10937 return reg_classes_intersect_p (DF_REGS, rclass);
832a3292
KH		 10938 }
10939 else
10940 {
10941 if (GET_MODE_SIZE (from) < 8)
0a2aaacc 10942 return reg_classes_intersect_p (DF_HI_REGS, rclass);
832a3292 10943 }
cff9f8d5 10944 }
b0c42aed 10945 return 0;
cff9f8d5
AH		 10946}
10947
ea4210ef
RS		 10948
10949/* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10950 that label is used. */
10951
10952void
cf277499 10953sh_mark_label (rtx address, int nuses)
ea4210ef
RS		 10954{
10955 if (GOTOFF_P (address))
10956 {
10957 /* Extract the label or symbol. */
10958 address = XEXP (address, 0);
10959 if (GET_CODE (address) == PLUS)
10960 address = XEXP (address, 0);
10961 address = XVECEXP (address, 0, 0);
10962 }
10963 if (GET_CODE (address) == LABEL_REF
f3536097 10964 && LABEL_P (XEXP (address, 0)))
ea4210ef
RS		 10965 LABEL_NUSES (XEXP (address, 0)) += nuses;
10966}
10967
95c0af87
JR		 10968/* Compute extra cost of moving data between one register class
10969 and another. */
10970
ec555f32
R		 10971/* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10972 uses this information. Hence, the general register <-> floating point
95c0af87
JR		 10973 register information here is not used for SFmode. */
10974
10975int
cf277499
SB		 10976sh_register_move_cost (enum machine_mode mode,
10977 enum reg_class srcclass, enum reg_class dstclass)
95c0af87
JR		 10978{
10979 if (dstclass == T_REGS || dstclass == PR_REGS)
10980 return 10;
10981
b1dcf523
DD		 10982 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
10983 return 4;
10984
ec555f32
R		 10985 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
10986 && REGCLASS_HAS_FP_REG (srcclass)
10987 && REGCLASS_HAS_FP_REG (dstclass))
10988 return 4;
10989
9c24200c
KK		 10990 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
10991 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
10992
a60a9553 10993 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
832a3292 10994 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
a60a9553
R		 10995 return 9;
10996
95c0af87
JR		 10997 if ((REGCLASS_HAS_FP_REG (dstclass)
10998 && REGCLASS_HAS_GENERAL_REG (srcclass))
10999 || (REGCLASS_HAS_GENERAL_REG (dstclass)
11000 && REGCLASS_HAS_FP_REG (srcclass)))
832a3292
KH		 11001 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
11002 * ((GET_MODE_SIZE (mode) + 7) / 8U));
95c0af87
JR		 11003
11004 if ((dstclass == FPUL_REGS
11005 && REGCLASS_HAS_GENERAL_REG (srcclass))
11006 || (srcclass == FPUL_REGS
11007 && REGCLASS_HAS_GENERAL_REG (dstclass)))
11008 return 5;
11009
11010 if ((dstclass == FPUL_REGS
11011 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
f676971a 11012 || (srcclass == FPUL_REGS
95c0af87
JR		 11013 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
11014 return 7;
11015
11016 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11017 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11018 return 20;
11019
73a4d10b
R		 11020 /* ??? ptabs faults on (value & 0x3) == 0x3 */
11021 if (TARGET_SHMEDIA
11022 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
11023 {
7dd2f19b
RS		 11024 if (sh_gettrcost >= 0)
11025 return sh_gettrcost;
73a4d10b
R		 11026 else if (!TARGET_PT_FIXED)
11027 return 100;
11028 }
11029
95c0af87
JR		 11030 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11031 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11032 return 4;
11033
ec555f32
R		 11034 if (TARGET_SHMEDIA
11035 || (TARGET_FMOVD
11036 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
11037 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
11038 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
11039
11040 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
95c0af87
JR		 11041}
11042
cf277499 11043static rtx emit_load_ptr (rtx, rtx);
1aa03f38
R		 11044
11045static rtx
cf277499 11046emit_load_ptr (rtx reg, rtx addr)
1aa03f38 11047{
57d38024 11048 rtx mem = gen_const_mem (ptr_mode, addr);
1aa03f38
R		 11049
11050 if (Pmode != ptr_mode)
11051 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
11052 return emit_move_insn (reg, mem);
11053}
11054
73a4d10b 11055static void
cf277499
SB		 11056sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11057 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11058 tree function)
1aa03f38
R		 11059{
11060 CUMULATIVE_ARGS cum;
11061 int structure_value_byref = 0;
0a2aaacc 11062 rtx this_rtx, this_value, sibcall, insns, funexp;
1aa03f38 11063 tree funtype = TREE_TYPE (function);
735cb76e 11064 int simple_add = CONST_OK_FOR_ADD (delta);
1aa03f38
R		 11065 int did_load = 0;
11066 rtx scratch0, scratch1, scratch2;
73a4d10b 11067 unsigned i;
1aa03f38
R		 11068
11069 reload_completed = 1;
fe3ad572 11070 epilogue_completed = 1;
1aa03f38
R		 11071 current_function_uses_only_leaf_regs = 1;
11072
2e040219 11073 emit_note (NOTE_INSN_PROLOGUE_END);
1aa03f38
R		 11074
11075 /* Find the "this" pointer. We have such a wide range of ABIs for the
11076 SH that it's best to do this completely machine independently.
f676971a 11077 "this" is passed as first argument, unless a structure return pointer
1aa03f38 11078 comes first, in which case "this" comes second. */
0f6937fe 11079 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
1aa03f38 11080#ifndef PCC_STATIC_STRUCT_RETURN
61f71b34 11081 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
1aa03f38
R		 11082 structure_value_byref = 1;
11083#endif /* not PCC_STATIC_STRUCT_RETURN */
61f71b34 11084 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
f676971a 11085 {
1aa03f38
R		 11086 tree ptype = build_pointer_type (TREE_TYPE (funtype));
11087
11088 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
11089 }
0a2aaacc 11090 this_rtx = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
1aa03f38
R		 11091
11092 /* For SHcompact, we only have r0 for a scratch register: r1 is the
11093 static chain pointer (even if you can't have nested virtual functions
11094 right now, someone might implement them sometime), and the rest of the
11095 registers are used for argument passing, are callee-saved, or reserved. */
73a4d10b
R		 11096 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
11097 -ffixed-reg has been used. */
11098 if (! call_used_regs[0] || fixed_regs[0])
11099 error ("r0 needs to be available as a call-clobbered register");
1aa03f38
R		 11100 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
11101 if (! TARGET_SH5)
11102 {
73a4d10b
R		 11103 if (call_used_regs[1] && ! fixed_regs[1])
11104 scratch1 = gen_rtx_REG (ptr_mode, 1);
1aa03f38
R		 11105 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
11106 pointing where to return struct values. */
73a4d10b
R		 11107 if (call_used_regs[3] && ! fixed_regs[3])
11108 scratch2 = gen_rtx_REG (Pmode, 3);
1aa03f38
R		 11109 }
11110 else if (TARGET_SHMEDIA)
11111 {
73a4d10b
R		 11112 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
11113 if (i != REGNO (scratch0) &&
11114 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
11115 {
11116 scratch1 = gen_rtx_REG (ptr_mode, i);
11117 break;
11118 }
11119 if (scratch1 == scratch0)
11120 error ("Need a second call-clobbered general purpose register");
11121 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
11122 if (call_used_regs[i] && ! fixed_regs[i])
11123 {
11124 scratch2 = gen_rtx_REG (Pmode, i);
11125 break;
11126 }
11127 if (scratch2 == scratch0)
11128 error ("Need a call-clobbered target register");
1aa03f38
R		 11129 }
11130
0a2aaacc 11131 this_value = plus_constant (this_rtx, delta);
1aa03f38
R		 11132 if (vcall_offset
11133 && (simple_add || scratch0 != scratch1)
11134 && strict_memory_address_p (ptr_mode, this_value))
11135 {
11136 emit_load_ptr (scratch0, this_value);
11137 did_load = 1;
11138 }
11139
11140 if (!delta)
11141 ; /* Do nothing. */
11142 else if (simple_add)
0a2aaacc 11143 emit_move_insn (this_rtx, this_value);
1aa03f38
R		 11144 else
11145 {
11146 emit_move_insn (scratch1, GEN_INT (delta));
0a2aaacc 11147 emit_insn (gen_add2_insn (this_rtx, scratch1));
1aa03f38
R		 11148 }
11149
11150 if (vcall_offset)
11151 {
11152 rtx offset_addr;
11153
11154 if (!did_load)
0a2aaacc 11155 emit_load_ptr (scratch0, this_rtx);
1aa03f38
R		 11156
11157 offset_addr = plus_constant (scratch0, vcall_offset);
11158 if (strict_memory_address_p (ptr_mode, offset_addr))
11159 ; /* Do nothing. */
73a4d10b 11160 else if (! TARGET_SH5 && scratch0 != scratch1)
1aa03f38
R		 11161 {
11162 /* scratch0 != scratch1, and we have indexed loads. Get better
11163 schedule by loading the offset into r1 and using an indexed
11164 load - then the load of r1 can issue before the load from
0a2aaacc 11165 (this_rtx + delta) finishes. */
1aa03f38
R		 11166 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11167 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
11168 }
735cb76e 11169 else if (CONST_OK_FOR_ADD (vcall_offset))
1aa03f38
R		 11170 {
11171 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
11172 offset_addr = scratch0;
11173 }
11174 else if (scratch0 != scratch1)
11175 {
11176 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11177 emit_insn (gen_add2_insn (scratch0, scratch1));
11178 offset_addr = scratch0;
11179 }
11180 else
f5b9e7c9 11181 gcc_unreachable (); /* FIXME */
1aa03f38
R		 11182 emit_load_ptr (scratch0, offset_addr);
11183
832a3292 11184 if (Pmode != ptr_mode)
1aa03f38 11185 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
0a2aaacc 11186 emit_insn (gen_add2_insn (this_rtx, scratch0));
1aa03f38
R		 11187 }
11188
11189 /* Generate a tail call to the target function. */
11190 if (! TREE_USED (function))
11191 {
11192 assemble_external (function);
11193 TREE_USED (function) = 1;
11194 }
11195 funexp = XEXP (DECL_RTL (function), 0);
73a4d10b
R		 11196 /* If the function is overridden, so is the thunk, hence we don't
11197 need GOT addressing even if this is a public symbol. */
11198#if 0
11199 if (TARGET_SH1 && ! flag_weak)
11200 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
11201 else
11202#endif
11203 if (TARGET_SH2 && flag_pic)
11204 {
11205 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
11206 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
11207 }
11208 else
11209 {
11210 if (TARGET_SHMEDIA && flag_pic)
11211 {
11212 funexp = gen_sym2PIC (funexp);
11213 PUT_MODE (funexp, Pmode);
11214 }
11215 emit_move_insn (scratch2, funexp);
11216 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
11217 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
11218 }
11219 sibcall = emit_call_insn (sibcall);
1aa03f38 11220 SIBLING_CALL_P (sibcall) = 1;
0a2aaacc 11221 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
1aa03f38
R		 11222 emit_barrier ();
11223
a2855205 11224 /* Run just enough of rest_of_compilation to do scheduling and get
1aa03f38
R		 11225 the insns emitted. Note that use_thunk calls
11226 assemble_start_function and assemble_end_function. */
a2855205 11227
55e092c4 11228 insn_locators_alloc ();
1aa03f38
R		 11229 insns = get_insns ();
11230
6fb5fa3c
DB		 11231 if (optimize > 0)
11232 {
11233 if (! cfun->cfg)
eb6cbf91 11234 init_flow (cfun);
6fb5fa3c
DB		 11235 split_all_insns_noflow ();
11236 }
1aa03f38 11237
18dbd950 11238 sh_reorg ();
1aa03f38
R		 11239
11240 if (optimize > 0 && flag_delayed_branch)
10d22567 11241 dbr_schedule (insns);
384a8760 11242
1aa03f38
R		 11243 shorten_branches (insns);
11244 final_start_function (insns, file, 1);
c9d691e9 11245 final (insns, file, 1);
1aa03f38 11246 final_end_function ();
2a7428c0 11247 free_after_compilation (cfun);
1aa03f38 11248
1aa03f38 11249 reload_completed = 0;
fe3ad572 11250 epilogue_completed = 0;
1aa03f38
R		 11251}
11252
90534361 11253rtx
73a4d10b 11254function_symbol (rtx target, const char *name, enum sh_function_kind kind)
90534361 11255{
73a4d10b
R		 11256 rtx sym;
11257
11258 /* If this is not an ordinary function, the name usually comes from a
11259 string literal or an sprintf buffer. Make sure we use the same
11260 string consistently, so that cse will be able to unify address loads. */
11261 if (kind != FUNCTION_ORDINARY)
11262 name = IDENTIFIER_POINTER (get_identifier (name));
11263 sym = gen_rtx_SYMBOL_REF (Pmode, name);
90534361 11264 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
73a4d10b
R		 11265 if (flag_pic)
11266 switch (kind)
11267 {
11268 case FUNCTION_ORDINARY:
11269 break;
11270 case SFUNC_GOT:
11271 {
11272 rtx reg = target ? target : gen_reg_rtx (Pmode);
11273
11274 emit_insn (gen_symGOT2reg (reg, sym));
11275 sym = reg;
11276 break;
11277 }
11278 case SFUNC_STATIC:
11279 {
11280 /* ??? To allow cse to work, we use GOTOFF relocations.
11281 we could add combiner patterns to transform this into
11282 straight pc-relative calls with sym2PIC / bsrf when
11283 label load and function call are still 1:1 and in the
11284 same basic block during combine. */
11285 rtx reg = target ? target : gen_reg_rtx (Pmode);
11286
11287 emit_insn (gen_symGOTOFF2reg (reg, sym));
11288 sym = reg;
11289 break;
11290 }
11291 }
11292 if (target && sym != target)
11293 {
11294 emit_move_insn (target, sym);
11295 return target;
11296 }
90534361
R		 11297 return sym;
11298}
11299
fada1961
R		 11300/* Find the number of a general purpose register in S. */
11301static int
11302scavenge_reg (HARD_REG_SET *s)
11303{
11304 int r;
11305 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11306 if (TEST_HARD_REG_BIT (*s, r))
11307 return r;
11308 return -1;
11309}
11310
11311rtx
11312sh_get_pr_initial_val (void)
11313{
7d73a2ba
R		 11314 rtx val;
11315
b869f904
R		 11316 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11317 PR register on SHcompact, because it might be clobbered by the prologue.
7d73a2ba 11318 We check first if that is known to be the case. */
b869f904 11319 if (TARGET_SHCOMPACT
38173d38 11320 && ((crtl->args.info.call_cookie
7d73a2ba 11321 & ~ CALL_COOKIE_RET_TRAMP (1))
e3b5732b 11322 || crtl->saves_all_registers))
57d38024 11323 return gen_frame_mem (SImode, return_address_pointer_rtx);
7d73a2ba
R		 11324
11325 /* If we haven't finished rtl generation, there might be a nonlocal label
11326 that we haven't seen yet.
b3a13419
ILT		 11327 ??? get_hard_reg_initial_val fails if it is called after register
11328 allocation has started, unless it has been called before for the
11329 same register. And even then, we end in trouble if we didn't use
11330 the register in the same basic block before. So call
11331 get_hard_reg_initial_val now and wrap it in an unspec if we might
11332 need to replace it. */
dce20bbc
R		 11333 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11334 combine can put the pseudo returned by get_hard_reg_initial_val into
11335 instructions that need a general purpose registers, which will fail to
11336 be recognized when the pseudo becomes allocated to PR. */
7d73a2ba
R		 11337 val
11338 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
dce20bbc 11339 if (TARGET_SH1)
7d73a2ba
R		 11340 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11341 return val;
fada1961
R		 11342}
11343
3db1b434 11344int
f90b7a5a 11345sh_expand_t_scc (rtx operands[])
3db1b434 11346{
f90b7a5a
PB		 11347 enum rtx_code code = GET_CODE (operands[1]);
11348 rtx target = operands[0];
11349 rtx op0 = operands[2];
11350 rtx op1 = operands[3];
3db1b434
R		 11351 rtx result = target;
11352 HOST_WIDE_INT val;
11353
f3536097
SZ		 11354 if (!REG_P (op0) || REGNO (op0) != T_REG
11355 || !CONST_INT_P (op1))
3db1b434 11356 return 0;
f3536097 11357 if (!REG_P (result))
3db1b434 11358 result = gen_reg_rtx (SImode);
f90b7a5a 11359 val = INTVAL (op1);
3db1b434
R		 11360 if ((code == EQ && val == 1) || (code == NE && val == 0))
11361 emit_insn (gen_movt (result));
f326a6cb
N		 11362 else if (TARGET_SH2A && ((code == EQ && val == 0)
11363 || (code == NE && val == 1)))
c185de40 11364 emit_insn (gen_xorsi3_movrt (result));
3db1b434
R		 11365 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11366 {
c41c1387 11367 emit_clobber (result);
3db1b434 11368 emit_insn (gen_subc (result, result, result));
a556fd39 11369 emit_insn (gen_addsi3 (result, result, const1_rtx));
3db1b434
R		 11370 }
11371 else if (code == EQ || code == NE)
11372 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11373 else
11374 return 0;
11375 if (result != target)
11376 emit_move_insn (target, result);
11377 return 1;
11378}
11379
07d7d2f4
R		 11380/* INSN is an sfunc; return the rtx that describes the address used. */
11381static rtx
11382extract_sfunc_addr (rtx insn)
11383{
11384 rtx pattern, part = NULL_RTX;
11385 int len, i;
11386
11387 pattern = PATTERN (insn);
11388 len = XVECLEN (pattern, 0);
11389 for (i = 0; i < len; i++)
11390 {
11391 part = XVECEXP (pattern, 0, i);
11392 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
11393 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
11394 return XEXP (part, 0);
11395 }
f5b9e7c9
NS		 11396 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
11397 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
07d7d2f4
R		 11398}
11399
11400/* Verify that the register in use_sfunc_addr still agrees with the address
11401 used in the sfunc. This prevents fill_slots_from_thread from changing
11402 use_sfunc_addr.
11403 INSN is the use_sfunc_addr instruction, and REG is the register it
11404 guards. */
11405int
11406check_use_sfunc_addr (rtx insn, rtx reg)
11407{
11408 /* Search for the sfunc. It should really come right after INSN. */
11409 while ((insn = NEXT_INSN (insn)))
11410 {
f3536097 11411 if (LABEL_P (insn) || JUMP_P (insn))
07d7d2f4
R		 11412 break;
11413 if (! INSN_P (insn))
11414 continue;
f676971a 11415
07d7d2f4
R		 11416 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11417 insn = XVECEXP (PATTERN (insn), 0, 0);
11418 if (GET_CODE (PATTERN (insn)) != PARALLEL
11419 || get_attr_type (insn) != TYPE_SFUNC)
11420 continue;
11421 return rtx_equal_p (extract_sfunc_addr (insn), reg);
11422 }
f5b9e7c9 11423 gcc_unreachable ();
07d7d2f4
R		 11424}
11425
312209c6
AO		 11426/* This function returns a constant rtx that represents pi / 2**15 in
11427 SFmode. it's used to scale SFmode angles, in radians, to a
11428 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11429 maps to 0x10000). */
11430
11431static GTY(()) rtx sh_fsca_sf2int_rtx;
11432
11433rtx
11434sh_fsca_sf2int (void)
11435{
11436 if (! sh_fsca_sf2int_rtx)
11437 {
11438 REAL_VALUE_TYPE rv;
11439
11440 real_from_string (&rv, "10430.378350470453");
11441 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
11442 }
11443
11444 return sh_fsca_sf2int_rtx;
11445}
f676971a 11446
312209c6
AO		 11447/* This function returns a constant rtx that represents pi / 2**15 in
11448 DFmode. it's used to scale DFmode angles, in radians, to a
11449 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11450 maps to 0x10000). */
11451
11452static GTY(()) rtx sh_fsca_df2int_rtx;
11453
11454rtx
11455sh_fsca_df2int (void)
11456{
11457 if (! sh_fsca_df2int_rtx)
11458 {
11459 REAL_VALUE_TYPE rv;
11460
11461 real_from_string (&rv, "10430.378350470453");
11462 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
11463 }
11464
11465 return sh_fsca_df2int_rtx;
11466}
f676971a 11467
312209c6
AO		 11468/* This function returns a constant rtx that represents 2**15 / pi in
11469 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
11470 of a full circle back to a SFmode value, i.e., 0x10000 maps to
11471 2*pi). */
11472
11473static GTY(()) rtx sh_fsca_int2sf_rtx;
11474
11475rtx
11476sh_fsca_int2sf (void)
11477{
11478 if (! sh_fsca_int2sf_rtx)
11479 {
11480 REAL_VALUE_TYPE rv;
11481
11482 real_from_string (&rv, "9.587379924285257e-5");
11483 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
11484 }
11485
11486 return sh_fsca_int2sf_rtx;
11487}
cc15e98f 11488
8b0add27 11489/* Initialize the CUMULATIVE_ARGS structure. */
cc15e98f
NC		 11490
11491void
11492sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
11493 tree fntype,
11494 rtx libname ATTRIBUTE_UNUSED,
11495 tree fndecl,
11496 signed int n_named_args,
11497 enum machine_mode mode)
11498{
11499 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
11500 pcum->free_single_fp_reg = 0;
11501 pcum->stack_regs = 0;
11502 pcum->byref_regs = 0;
11503 pcum->byref = 0;
11504 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
11505
11506 /* XXX - Should we check TARGET_HITACHI here ??? */
11507 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
11508
11509 if (fntype)
11510 {
11511 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
11512 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
11513 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
11514 pcum->arg_count [(int) SH_ARG_INT]
11515 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
11516
11517 pcum->call_cookie
11518 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11519 && pcum->arg_count [(int) SH_ARG_INT] == 0
11520 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
11521 ? int_size_in_bytes (TREE_TYPE (fntype))
11522 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
11523 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
11524 == FIRST_RET_REG));
11525 }
11526 else
11527 {
11528 pcum->arg_count [(int) SH_ARG_INT] = 0;
11529 pcum->prototype_p = FALSE;
11530 if (mode != VOIDmode)
11531 {
29832164 11532 pcum->call_cookie =
cc15e98f
NC		 11533 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11534 && GET_MODE_SIZE (mode) > 4
11535 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
11536
11537 /* If the default ABI is the Renesas ABI then all library
11538 calls must assume that the library will be using the
11539 Renesas ABI. So if the function would return its result
11540 in memory then we must force the address of this memory
11541 block onto the stack. Ideally we would like to call
11542 targetm.calls.return_in_memory() here but we do not have
8b0add27 11543 the TYPE or the FNDECL available so we synthesize the
cc15e98f
NC		 11544 contents of that function as best we can. */
11545 pcum->force_mem =
c0fb94d7 11546 (TARGET_DEFAULT & MASK_HITACHI)
cc15e98f
NC		 11547 && (mode == BLKmode
11548 || (GET_MODE_SIZE (mode) > 4
11549 && !(mode == DFmode
11550 && TARGET_FPU_DOUBLE)));
11551 }
11552 else
11553 {
11554 pcum->call_cookie = 0;
11555 pcum->force_mem = FALSE;
11556 }
11557 }
11558}
11559
73a4d10b
R		 11560/* Replace any occurrence of FROM(n) in X with TO(n). The function does
11561 not enter into CONST_DOUBLE for the replace.
11562
11563 Note that copying is not done so X must not be shared unless all copies
11564 are to be modified.
11565
11566 This is like replace_rtx, except that we operate on N_REPLACEMENTS
30dc60c7 11567 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
73a4d10b
R		 11568 replacements[n*2+1] - and that we take mode changes into account.
11569
30dc60c7 11570 If a replacement is ambiguous, return NULL_RTX.
73a4d10b
R		 11571
11572 If MODIFY is zero, don't modify any rtl in place,
11573 just return zero or nonzero for failure / success. */
11574
11575rtx
11576replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
11577{
11578 int i, j;
11579 const char *fmt;
11580
11581 /* The following prevents loops occurrence when we change MEM in
11582 CONST_DOUBLE onto the same CONST_DOUBLE. */
11583 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
11584 return x;
11585
11586 for (i = n_replacements - 1; i >= 0 ; i--)
11587 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
11588 return replacements[i*2+1];
11589
11590 /* Allow this function to make replacements in EXPR_LISTs. */
11591 if (x == 0)
11592 return 0;
11593
11594 if (GET_CODE (x) == SUBREG)
11595 {
0a2aaacc 11596 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
73a4d10b
R		 11597 n_replacements, modify);
11598
f3536097 11599 if (CONST_INT_P (new_rtx))
73a4d10b 11600 {
0a2aaacc 11601 x = simplify_subreg (GET_MODE (x), new_rtx,
73a4d10b
R		 11602 GET_MODE (SUBREG_REG (x)),
11603 SUBREG_BYTE (x));
11604 if (! x)
11605 abort ();
11606 }
11607 else if (modify)
0a2aaacc 11608 SUBREG_REG (x) = new_rtx;
73a4d10b
R		 11609
11610 return x;
11611 }
f3536097 11612 else if (REG_P (x))
73a4d10b
R		 11613 {
11614 unsigned regno = REGNO (x);
11615 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
11616 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11617 rtx result = NULL_RTX;
11618
11619 for (i = n_replacements - 1; i >= 0; i--)
11620 {
11621 rtx from = replacements[i*2];
11622 rtx to = replacements[i*2+1];
11623 unsigned from_regno, from_nregs, to_regno, new_regno;
11624
f3536097 11625 if (!REG_P (from))
73a4d10b
R		 11626 continue;
11627 from_regno = REGNO (from);
11628 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
11629 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
11630 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
11631 {
11632 if (regno < from_regno
11633 || regno + nregs > from_regno + nregs
f3536097 11634 || !REG_P (to)
73a4d10b
R		 11635 || result)
11636 return NULL_RTX;
11637 to_regno = REGNO (to);
11638 if (to_regno < FIRST_PSEUDO_REGISTER)
11639 {
11640 new_regno = regno + to_regno - from_regno;
11641 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
11642 != nregs)
11643 return NULL_RTX;
11644 result = gen_rtx_REG (GET_MODE (x), new_regno);
11645 }
11646 else if (GET_MODE (x) <= GET_MODE (to))
11647 result = gen_lowpart_common (GET_MODE (x), to);
11648 else
11649 result = gen_lowpart_SUBREG (GET_MODE (x), to);
11650 }
11651 }
11652 return result ? result : x;
11653 }
11654 else if (GET_CODE (x) == ZERO_EXTEND)
11655 {
0a2aaacc 11656 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
73a4d10b
R		 11657 n_replacements, modify);
11658
f3536097 11659 if (CONST_INT_P (new_rtx))
73a4d10b
R		 11660 {
11661 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
0a2aaacc 11662 new_rtx, GET_MODE (XEXP (x, 0)));
73a4d10b
R		 11663 if (! x)
11664 abort ();
11665 }
11666 else if (modify)
0a2aaacc 11667 XEXP (x, 0) = new_rtx;
73a4d10b
R		 11668
11669 return x;
11670 }
11671
11672 fmt = GET_RTX_FORMAT (GET_CODE (x));
11673 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
11674 {
0a2aaacc 11675 rtx new_rtx;
73a4d10b
R		 11676
11677 if (fmt[i] == 'e')
11678 {
0a2aaacc 11679 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
73a4d10b 11680 n_replacements, modify);
0a2aaacc 11681 if (!new_rtx)
73a4d10b
R		 11682 return NULL_RTX;
11683 if (modify)
0a2aaacc 11684 XEXP (x, i) = new_rtx;
73a4d10b
R		 11685 }
11686 else if (fmt[i] == 'E')
11687 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11688 {
0a2aaacc 11689 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
73a4d10b 11690 n_replacements, modify);
0a2aaacc 11691 if (!new_rtx)
73a4d10b
R		 11692 return NULL_RTX;
11693 if (modify)
0a2aaacc 11694 XVECEXP (x, i, j) = new_rtx;
73a4d10b
R		 11695 }
11696 }
11697
11698 return x;
11699}
11700
11701rtx
11702sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
11703{
11704 enum rtx_code code = TRUNCATE;
11705
11706 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
11707 {
11708 rtx inner = XEXP (x, 0);
11709 enum machine_mode inner_mode = GET_MODE (inner);
11710
11711 if (inner_mode == mode)
11712 return inner;
11713 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
11714 x = inner;
11715 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
11716 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
11717 {
11718 code = GET_CODE (x);
11719 x = inner;
11720 }
11721 }
11722 return gen_rtx_fmt_e (code, mode, x);
11723}
11724
11725/* called via for_each_rtx after reload, to clean up truncates of
11726 registers that span multiple actual hard registers. */
11727int
11728shmedia_cleanup_truncate (rtx *p, void *n_changes)
11729{
11730 rtx x = *p, reg;
11731
11732 if (GET_CODE (x) != TRUNCATE)
11733 return 0;
11734 reg = XEXP (x, 0);
f3536097 11735 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && REG_P (reg))
73a4d10b
R		 11736 {
11737 enum machine_mode reg_mode = GET_MODE (reg);
11738 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
11739 subreg_lowpart_offset (DImode, reg_mode));
11740 *(int*) n_changes += 1;
11741 return -1;
11742 }
11743 return 0;
11744}
11745
11746/* Load and store depend on the highpart of the address. However,
11747 set_attr_alternative does not give well-defined results before reload,
11748 so we must look at the rtl ourselves to see if any of the feeding
11749 registers is used in a memref. */
11750
11751/* Called by sh_contains_memref_p via for_each_rtx. */
11752static int
11753sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
11754{
f3536097 11755 return (MEM_P (*loc));
73a4d10b
R		 11756}
11757
a4d05547 11758/* Return nonzero iff INSN contains a MEM. */
73a4d10b
R		 11759int
11760sh_contains_memref_p (rtx insn)
11761{
11762 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
11763}
11764
5c7cafa8
CB		 11765/* Return nonzero iff INSN loads a banked register. */
11766int
11767sh_loads_bankedreg_p (rtx insn)
11768{
11769 if (GET_CODE (PATTERN (insn)) == SET)
11770 {
11771 rtx op = SET_DEST (PATTERN(insn));
11772 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11773 return 1;
11774 }
11775
11776 return 0;
11777}
11778
73a4d10b
R		 11779/* FNADDR is the MEM expression from a call expander. Return an address
11780 to use in an SHmedia insn pattern. */
11781rtx
11782shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
11783{
11784 int is_sym;
11785
11786 fnaddr = XEXP (fnaddr, 0);
11787 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
11788 if (flag_pic && is_sym)
11789 {
11790 if (! SYMBOL_REF_LOCAL_P (fnaddr))
11791 {
11792 rtx reg = gen_reg_rtx (Pmode);
11793
11794 /* We must not use GOTPLT for sibcalls, because PIC_REG
11795 must be restored before the PLT code gets to run. */
11796 if (is_sibcall)
11797 emit_insn (gen_symGOT2reg (reg, fnaddr));
11798 else
11799 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
11800 fnaddr = reg;
11801 }
11802 else
11803 {
11804 fnaddr = gen_sym2PIC (fnaddr);
11805 PUT_MODE (fnaddr, Pmode);
11806 }
11807 }
11808 /* If ptabs might trap, make this visible to the rest of the compiler.
11809 We generally assume that symbols pertain to valid locations, but
11810 it is possible to generate invalid symbols with asm or linker tricks.
30dc60c7 11811 In a list of functions where each returns its successor, an invalid
73a4d10b
R		 11812 symbol might denote an empty list. */
11813 if (!TARGET_PT_FIXED
11814 && (!is_sym || TARGET_INVALID_SYMBOLS)
11815 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
11816 {
11817 rtx tr = gen_reg_rtx (PDImode);
11818
11819 emit_insn (gen_ptabs (tr, fnaddr));
11820 fnaddr = tr;
11821 }
11822 else if (! target_reg_operand (fnaddr, Pmode))
11823 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
11824 return fnaddr;
11825}
11826
8a99f6f9 11827enum reg_class
0a2aaacc 11828sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
8a99f6f9
R		 11829 enum machine_mode mode, secondary_reload_info *sri)
11830{
11831 if (in_p)
11832 {
0a2aaacc 11833 if (REGCLASS_HAS_FP_REG (rclass)
8a99f6f9
R		 11834 && ! TARGET_SHMEDIA
11835 && immediate_operand ((x), mode)
11836 && ! ((fp_zero_operand (x) || fp_one_operand (x))
11837 && mode == SFmode && fldi_ok ()))
11838 switch (mode)
11839 {
11840 case SFmode:
11841 sri->icode = CODE_FOR_reload_insf__frn;
11842 return NO_REGS;
11843 case DFmode:
11844 sri->icode = CODE_FOR_reload_indf__frn;
11845 return NO_REGS;
11846 case SImode:
11847 /* ??? If we knew that we are in the appropriate mode -
11848 single precision - we could use a reload pattern directly. */
11849 return FPUL_REGS;
11850 default:
11851 abort ();
11852 }
0a2aaacc 11853 if (rclass == FPUL_REGS
f3536097 11854 && ((REG_P (x)
8a99f6f9
R		 11855 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11856 || REGNO (x) == T_REG))
11857 || GET_CODE (x) == PLUS))
11858 return GENERAL_REGS;
0a2aaacc 11859 if (rclass == FPUL_REGS && immediate_operand (x, mode))
8a99f6f9 11860 {
d973ac5a 11861 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
8a99f6f9 11862 return GENERAL_REGS;
d973ac5a
KK		 11863 else if (mode == SFmode)
11864 return FP_REGS;
8a99f6f9
R		 11865 sri->icode = CODE_FOR_reload_insi__i_fpul;
11866 return NO_REGS;
11867 }
0a2aaacc 11868 if (rclass == FPSCR_REGS
f3536097
SZ		 11869 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11870 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
8a99f6f9 11871 return GENERAL_REGS;
0a2aaacc 11872 if (REGCLASS_HAS_FP_REG (rclass)
8a99f6f9
R		 11873 && TARGET_SHMEDIA
11874 && immediate_operand (x, mode)
11875 && x != CONST0_RTX (GET_MODE (x))
11876 && GET_MODE (x) != V4SFmode)
11877 return GENERAL_REGS;
11878 if ((mode == QImode || mode == HImode)
11879 && TARGET_SHMEDIA && inqhi_operand (x, mode))
11880 {
11881 sri->icode = ((mode == QImode)
11882 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
11883 return NO_REGS;
11884 }
0a2aaacc 11885 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
dc3ba671 11886 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
8a99f6f9
R		 11887 return TARGET_REGS;
11888 } /* end of input-only processing. */
11889
0a2aaacc 11890 if (((REGCLASS_HAS_FP_REG (rclass)
f3536097 11891 && (REG_P (x)
8a99f6f9
R		 11892 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11893 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11894 && TARGET_FMOVD))))
0a2aaacc 11895 || (REGCLASS_HAS_GENERAL_REG (rclass)
f3536097 11896 && REG_P (x)
8a99f6f9
R		 11897 && FP_REGISTER_P (REGNO (x))))
11898 && ! TARGET_SHMEDIA
11899 && (mode == SFmode || mode == SImode))
11900 return FPUL_REGS;
0a2aaacc
KG		 11901 if ((rclass == FPUL_REGS
11902 || (REGCLASS_HAS_FP_REG (rclass)
8a99f6f9 11903 && ! TARGET_SHMEDIA && mode == SImode))
f3536097
SZ		 11904 && (MEM_P (x)
11905 || (REG_P (x)
8a99f6f9
R		 11906 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11907 || REGNO (x) == T_REG
11908 || system_reg_operand (x, VOIDmode)))))
11909 {
0a2aaacc 11910 if (rclass == FPUL_REGS)
8a99f6f9
R		 11911 return GENERAL_REGS;
11912 return FPUL_REGS;
11913 }
0a2aaacc
KG		 11914 if ((rclass == TARGET_REGS
11915 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
32a7ab3d 11916 && !satisfies_constraint_Csy (x)
f3536097 11917 && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
8a99f6f9 11918 return GENERAL_REGS;
0a2aaacc 11919 if ((rclass == MAC_REGS || rclass == PR_REGS)
f3536097 11920 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
0a2aaacc 11921 && rclass != REGNO_REG_CLASS (REGNO (x)))
8a99f6f9 11922 return GENERAL_REGS;
f3536097 11923 if (rclass != GENERAL_REGS && REG_P (x)
8a99f6f9
R		 11924 && TARGET_REGISTER_P (REGNO (x)))
11925 return GENERAL_REGS;
11926 return NO_REGS;
11927}
11928
73a4d10b
R		 11929enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;
11930
e2500fed 11931#include "gt-sh.h"
Mirror of https://gcc.gnu.org/git/gcc.git