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Commit | Line | Data |
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7ab56274 | 1 | /* Output routines for GCC for Hitachi / SuperH SH. |
e03f5d43 | 2 | Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002 |
4592bdcb | 3 | Free Software Foundation, Inc. |
c5c76735 JL |
4 | Contributed by Steve Chamberlain (sac@cygnus.com). |
5 | Improved by Jim Wilson (wilson@cygnus.com). | |
bc45ade3 | 6 | |
c15c9075 RK |
7 | This file is part of GNU CC. |
8 | ||
9 | GNU CC is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GNU CC is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GNU CC; see the file COPYING. If not, write to | |
21 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
22 | Boston, MA 02111-1307, USA. */ | |
bc45ade3 | 23 | |
bc45ade3 | 24 | #include "config.h" |
c5c76735 | 25 | #include "system.h" |
318881c0 | 26 | #include "insn-config.h" |
bc45ade3 | 27 | #include "rtl.h" |
bc45ade3 | 28 | #include "tree.h" |
bc45ade3 | 29 | #include "flags.h" |
bc45ade3 | 30 | #include "expr.h" |
e78d8e51 | 31 | #include "optabs.h" |
49ad7cfa | 32 | #include "function.h" |
8aa2a305 JW |
33 | #include "regs.h" |
34 | #include "hard-reg-set.h" | |
35 | #include "output.h" | |
956a5206 | 36 | #include "insn-attr.h" |
318881c0 KG |
37 | #include "toplev.h" |
38 | #include "recog.h" | |
8b97c5f8 | 39 | #include "c-pragma.h" |
950a3816 | 40 | #include "integrate.h" |
318881c0 | 41 | #include "tm_p.h" |
672a6f42 NB |
42 | #include "target.h" |
43 | #include "target-def.h" | |
62526ec3 | 44 | #include "real.h" |
bc45ade3 | 45 | |
1245df60 R |
46 | int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch; |
47 | ||
00f8ff66 SC |
48 | #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0) |
49 | #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1) | |
50 | ||
fa5322fa AO |
51 | /* These are some macros to abstract register modes. */ |
52 | #define CONST_OK_FOR_ADD(size) \ | |
53 | (TARGET_SHMEDIA ? CONST_OK_FOR_P (size) : CONST_OK_FOR_I (size)) | |
54 | #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi)) | |
55 | #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3)) | |
56 | #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3)) | |
57 | ||
552ecbd9 AH |
58 | /* Set to 1 by expand_prologue() when the function is an interrupt handler. */ |
59 | int current_function_interrupt; | |
60 | ||
20b04867 | 61 | /* ??? The pragma interrupt support will not work for SH3. */ |
8aa2a305 JW |
62 | /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to |
63 | output code for the next function appropriate for an interrupt handler. */ | |
0d7e008e | 64 | int pragma_interrupt; |
bc45ade3 | 65 | |
4408efce JL |
66 | /* This is set by the trap_exit attribute for functions. It specifies |
67 | a trap number to be used in a trapa instruction at function exit | |
68 | (instead of an rte instruction). */ | |
69 | int trap_exit; | |
70 | ||
71 | /* This is used by the sp_switch attribute for functions. It specifies | |
72 | a variable holding the address of the stack the interrupt function | |
73 | should switch to/from at entry/exit. */ | |
74 | rtx sp_switch; | |
75 | ||
8aa2a305 JW |
76 | /* This is set by #pragma trapa, and is similar to the above, except that |
77 | the compiler doesn't emit code to preserve all registers. */ | |
78 | static int pragma_trapa; | |
79 | ||
956a5206 JW |
80 | /* This is set by #pragma nosave_low_regs. This is useful on the SH3, |
81 | which has a separate set of low regs for User and Supervisor modes. | |
82 | This should only be used for the lowest level of interrupts. Higher levels | |
83 | of interrupts must save the registers in case they themselves are | |
84 | interrupted. */ | |
85 | int pragma_nosave_low_regs; | |
86 | ||
8aa2a305 JW |
87 | /* This is used for communication between SETUP_INCOMING_VARARGS and |
88 | sh_expand_prologue. */ | |
bc45ade3 | 89 | int current_function_anonymous_args; |
16bea517 | 90 | |
6f317ef3 | 91 | /* Global variables for machine-dependent things. */ |
bc45ade3 | 92 | |
16bea517 JW |
93 | /* Which cpu are we scheduling for. */ |
94 | enum processor_type sh_cpu; | |
95 | ||
bc45ade3 | 96 | /* Saved operands from the last compare to use when we generate an scc |
16bea517 | 97 | or bcc insn. */ |
bc45ade3 SC |
98 | |
99 | rtx sh_compare_op0; | |
100 | rtx sh_compare_op1; | |
101 | ||
102 | /* Provides the class number of the smallest class containing | |
16bea517 | 103 | reg number. */ |
bc45ade3 SC |
104 | |
105 | int regno_reg_class[FIRST_PSEUDO_REGISTER] = | |
106 | { | |
8e87e161 | 107 | R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, |
bc45ade3 SC |
108 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, |
109 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
110 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
fa5322fa AO |
111 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, |
112 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
113 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
114 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
115 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
116 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
117 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
118 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
119 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
120 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
121 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
122 | GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, | |
1a95a963 JW |
123 | FP0_REGS,FP_REGS, FP_REGS, FP_REGS, |
124 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
125 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
126 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
fa5322fa AO |
127 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, |
128 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
129 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
130 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
131 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
132 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
133 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
134 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
135 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
136 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
137 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
138 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
139 | TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS, | |
140 | TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS, | |
225e4f43 R |
141 | DF_REGS, DF_REGS, DF_REGS, DF_REGS, |
142 | DF_REGS, DF_REGS, DF_REGS, DF_REGS, | |
fa5322fa AO |
143 | NO_REGS, GENERAL_REGS, PR_REGS, T_REGS, |
144 | MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS, | |
145 | GENERAL_REGS, | |
225e4f43 R |
146 | }; |
147 | ||
fa5322fa AO |
148 | char sh_register_names[FIRST_PSEUDO_REGISTER] \ |
149 | [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER; | |
150 | ||
151 | char sh_additional_register_names[ADDREGNAMES_SIZE] \ | |
152 | [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1] | |
153 | = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER; | |
bc45ade3 SC |
154 | |
155 | /* Provide reg_class from a letter such as appears in the machine | |
16bea517 | 156 | description. */ |
bc45ade3 | 157 | |
0b5826ac | 158 | const enum reg_class reg_class_from_letter[] = |
bc45ade3 | 159 | { |
fa5322fa | 160 | /* a */ ALL_REGS, /* b */ TARGET_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS, |
1a95a963 | 161 | /* e */ NO_REGS, /* f */ FP_REGS, /* g */ NO_REGS, /* h */ NO_REGS, |
cb51ecd2 | 162 | /* i */ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS, |
bc45ade3 SC |
163 | /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS, |
164 | /* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS, | |
1a95a963 JW |
165 | /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS, |
166 | /* y */ FPUL_REGS, /* z */ R0_REGS | |
bc45ade3 | 167 | }; |
1245df60 | 168 | |
225e4f43 R |
169 | int assembler_dialect; |
170 | ||
318881c0 KG |
171 | static void split_branches PARAMS ((rtx)); |
172 | static int branch_dest PARAMS ((rtx)); | |
173 | static void force_into PARAMS ((rtx, rtx)); | |
174 | static void print_slot PARAMS ((rtx)); | |
175 | static rtx add_constant PARAMS ((rtx, enum machine_mode, rtx)); | |
176 | static void dump_table PARAMS ((rtx)); | |
177 | static int hi_const PARAMS ((rtx)); | |
178 | static int broken_move PARAMS ((rtx)); | |
179 | static int mova_p PARAMS ((rtx)); | |
180 | static rtx find_barrier PARAMS ((int, rtx, rtx)); | |
181 | static int noncall_uses_reg PARAMS ((rtx, rtx, rtx *)); | |
182 | static rtx gen_block_redirect PARAMS ((rtx, int, int)); | |
183 | static void output_stack_adjust PARAMS ((int, rtx, int)); | |
184 | static void push PARAMS ((int)); | |
185 | static void pop PARAMS ((int)); | |
fa5322fa AO |
186 | static void push_regs PARAMS ((HOST_WIDE_INT *)); |
187 | static void calc_live_regs PARAMS ((int *, HOST_WIDE_INT *)); | |
318881c0 | 188 | static void mark_use PARAMS ((rtx, rtx *)); |
e5f8d4c0 | 189 | static HOST_WIDE_INT rounded_frame_size PARAMS ((int)); |
b91455de | 190 | static rtx mark_constant_pool_use PARAMS ((rtx)); |
91d231cb JM |
191 | const struct attribute_spec sh_attribute_table[]; |
192 | static tree sh_handle_interrupt_handler_attribute PARAMS ((tree *, tree, tree, int, bool *)); | |
193 | static tree sh_handle_sp_switch_attribute PARAMS ((tree *, tree, tree, int, bool *)); | |
194 | static tree sh_handle_trap_exit_attribute PARAMS ((tree *, tree, tree, int, bool *)); | |
08c148a8 | 195 | static void sh_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); |
12a68f1f | 196 | static void sh_insert_attributes PARAMS ((tree, tree *)); |
c237e94a | 197 | static int sh_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
fae15c93 VM |
198 | static int sh_use_dfa_interface PARAMS ((void)); |
199 | static int sh_issue_rate PARAMS ((void)); | |
200 | ||
fa5322fa | 201 | static bool sh_cannot_modify_jumps_p PARAMS ((void)); |
fa5322fa | 202 | static bool sh_ms_bitfield_layout_p PARAMS ((tree)); |
fb49053f RH |
203 | |
204 | static void sh_encode_section_info PARAMS ((tree, int)); | |
772c5265 | 205 | static const char *sh_strip_name_encoding PARAMS ((const char *)); |
672a6f42 NB |
206 | \f |
207 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
208 | #undef TARGET_ATTRIBUTE_TABLE |
209 | #define TARGET_ATTRIBUTE_TABLE sh_attribute_table | |
672a6f42 | 210 | |
301d03af RS |
211 | /* The next two are used for debug info when compiling with -gdwarf. */ |
212 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
213 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t" | |
214 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
215 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t" | |
216 | ||
fa5322fa AO |
217 | /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */ |
218 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
219 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t" | |
220 | #undef TARGET_ASM_ALIGNED_DI_OP | |
221 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
222 | ||
08c148a8 NB |
223 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
224 | #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue | |
225 | ||
12a68f1f JM |
226 | #undef TARGET_INSERT_ATTRIBUTES |
227 | #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes | |
228 | ||
c237e94a ZW |
229 | #undef TARGET_SCHED_ADJUST_COST |
230 | #define TARGET_SCHED_ADJUST_COST sh_adjust_cost | |
231 | ||
fae15c93 VM |
232 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE |
233 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \ | |
234 | sh_use_dfa_interface | |
235 | #undef TARGET_SCHED_ISSUE_RATE | |
236 | #define TARGET_SCHED_ISSUE_RATE sh_issue_rate | |
237 | ||
fa5322fa AO |
238 | #undef TARGET_CANNOT_MODIFY_JUMPS_P |
239 | #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p | |
240 | ||
241 | #undef TARGET_MS_BITFIELD_LAYOUT_P | |
242 | #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p | |
243 | ||
772c5265 RH |
244 | #undef TARGET_ENCODE_SECTION_INFO |
245 | #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info | |
246 | #undef TARGET_STRIP_NAME_ENCODING | |
247 | #define TARGET_STRIP_NAME_ENCODING sh_strip_name_encoding | |
248 | ||
f6897b10 | 249 | struct gcc_target targetm = TARGET_INITIALIZER; |
b9654711 | 250 | \f |
16bea517 | 251 | /* Print the operand address in x to the stream. */ |
bc45ade3 SC |
252 | |
253 | void | |
254 | print_operand_address (stream, x) | |
255 | FILE *stream; | |
256 | rtx x; | |
257 | { | |
258 | switch (GET_CODE (x)) | |
259 | { | |
260 | case REG: | |
225e4f43 R |
261 | case SUBREG: |
262 | fprintf (stream, "@%s", reg_names[true_regnum (x)]); | |
bc45ade3 | 263 | break; |
8aa2a305 | 264 | |
bc45ade3 SC |
265 | case PLUS: |
266 | { | |
267 | rtx base = XEXP (x, 0); | |
268 | rtx index = XEXP (x, 1); | |
269 | ||
bc45ade3 SC |
270 | switch (GET_CODE (index)) |
271 | { | |
272 | case CONST_INT: | |
c5b9ef02 | 273 | fprintf (stream, "@(%d,%s)", (int) INTVAL (index), |
225e4f43 | 274 | reg_names[true_regnum (base)]); |
bc45ade3 SC |
275 | break; |
276 | ||
277 | case REG: | |
225e4f43 R |
278 | case SUBREG: |
279 | { | |
280 | int base_num = true_regnum (base); | |
281 | int index_num = true_regnum (index); | |
282 | ||
283 | fprintf (stream, "@(r0,%s)", | |
284 | reg_names[MAX (base_num, index_num)]); | |
285 | break; | |
286 | } | |
bc45ade3 SC |
287 | |
288 | default: | |
b9654711 | 289 | debug_rtx (x); |
bc45ade3 SC |
290 | abort (); |
291 | } | |
292 | } | |
bc45ade3 | 293 | break; |
8aa2a305 | 294 | |
bc45ade3 | 295 | case PRE_DEC: |
225e4f43 | 296 | fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]); |
bc45ade3 SC |
297 | break; |
298 | ||
299 | case POST_INC: | |
225e4f43 | 300 | fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]); |
bc45ade3 SC |
301 | break; |
302 | ||
303 | default: | |
b91455de | 304 | x = mark_constant_pool_use (x); |
422be3c3 | 305 | output_addr_const (stream, x); |
bc45ade3 SC |
306 | break; |
307 | } | |
308 | } | |
309 | ||
310 | /* Print operand x (an rtx) in assembler syntax to file stream | |
311 | according to modifier code. | |
312 | ||
b9654711 | 313 | '.' print a .s if insn needs delay slot |
1245df60 | 314 | ',' print LOCAL_LABEL_PREFIX |
4408efce | 315 | '@' print trap, rte or rts depending upon pragma interruptness |
8aa2a305 JW |
316 | '#' output a nop if there is nothing to put in the delay slot |
317 | 'O' print a constant without the # | |
00f8ff66 | 318 | 'R' print the LSW of a dp value - changes if in little endian |
00f8ff66 | 319 | 'S' print the MSW of a dp value - changes if in little endian |
225e4f43 | 320 | 'T' print the next word of a dp value - same as 'R' in big endian mode. |
fa5322fa AO |
321 | 'M' print an `x' if `m' will print `base,index'. |
322 | 'm' print a pair `base,offset' or `base,index', for LD and ST. | |
323 | 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value. | |
225e4f43 | 324 | 'o' output an operator. */ |
bc45ade3 SC |
325 | |
326 | void | |
327 | print_operand (stream, x, code) | |
328 | FILE *stream; | |
329 | rtx x; | |
330 | int code; | |
331 | { | |
332 | switch (code) | |
333 | { | |
b9654711 | 334 | case '.': |
79b2746a JW |
335 | if (final_sequence |
336 | && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))) | |
1245df60 R |
337 | fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s"); |
338 | break; | |
339 | case ',': | |
340 | fprintf (stream, "%s", LOCAL_LABEL_PREFIX); | |
b9654711 | 341 | break; |
d3ae8277 | 342 | case '@': |
157131d7 SC |
343 | { |
344 | int interrupt_handler; | |
345 | ||
346 | if ((lookup_attribute | |
347 | ("interrupt_handler", | |
91d231cb | 348 | DECL_ATTRIBUTES (current_function_decl))) |
157131d7 SC |
349 | != NULL_TREE) |
350 | interrupt_handler = 1; | |
351 | else | |
352 | interrupt_handler = 0; | |
353 | ||
4408efce JL |
354 | if (trap_exit) |
355 | fprintf (stream, "trapa #%d", trap_exit); | |
157131d7 | 356 | else if (interrupt_handler) |
8e87e161 | 357 | fprintf (stream, "rte"); |
d3ae8277 | 358 | else |
8e87e161 | 359 | fprintf (stream, "rts"); |
d3ae8277 | 360 | break; |
157131d7 | 361 | } |
bc45ade3 | 362 | case '#': |
16bea517 | 363 | /* Output a nop if there's nothing in the delay slot. */ |
bc45ade3 | 364 | if (dbr_sequence_length () == 0) |
8aa2a305 | 365 | fprintf (stream, "\n\tnop"); |
bc45ade3 | 366 | break; |
b9654711 | 367 | case 'O': |
b91455de | 368 | x = mark_constant_pool_use (x); |
0d7e008e | 369 | output_addr_const (stream, x); |
bc45ade3 | 370 | break; |
bc45ade3 | 371 | case 'R': |
8aa2a305 JW |
372 | fputs (reg_names[REGNO (x) + LSW], (stream)); |
373 | break; | |
374 | case 'S': | |
375 | fputs (reg_names[REGNO (x) + MSW], (stream)); | |
00f8ff66 SC |
376 | break; |
377 | case 'T': | |
16bea517 | 378 | /* Next word of a double. */ |
bc45ade3 SC |
379 | switch (GET_CODE (x)) |
380 | { | |
381 | case REG: | |
382 | fputs (reg_names[REGNO (x) + 1], (stream)); | |
383 | break; | |
384 | case MEM: | |
225e4f43 R |
385 | if (GET_CODE (XEXP (x, 0)) != PRE_DEC |
386 | && GET_CODE (XEXP (x, 0)) != POST_INC) | |
b72f00af | 387 | x = adjust_address (x, SImode, 4); |
225e4f43 | 388 | print_operand_address (stream, XEXP (x, 0)); |
bc45ade3 | 389 | break; |
318881c0 KG |
390 | default: |
391 | break; | |
bc45ade3 SC |
392 | } |
393 | break; | |
225e4f43 R |
394 | case 'o': |
395 | switch (GET_CODE (x)) | |
396 | { | |
397 | case PLUS: fputs ("add", stream); break; | |
398 | case MINUS: fputs ("sub", stream); break; | |
399 | case MULT: fputs ("mul", stream); break; | |
400 | case DIV: fputs ("div", stream); break; | |
318881c0 KG |
401 | default: |
402 | break; | |
225e4f43 R |
403 | } |
404 | break; | |
fa5322fa AO |
405 | case 'M': |
406 | if (GET_CODE (x) == MEM | |
407 | && GET_CODE (XEXP (x, 0)) == PLUS | |
408 | && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG | |
409 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG)) | |
410 | fputc ('x', stream); | |
411 | break; | |
412 | ||
413 | case 'm': | |
414 | if (GET_CODE (x) != MEM) | |
415 | abort (); | |
416 | x = XEXP (x, 0); | |
417 | switch (GET_CODE (x)) | |
418 | { | |
419 | case REG: | |
420 | case SUBREG: | |
421 | print_operand (stream, x, 0); | |
422 | fputs (", 0", stream); | |
423 | break; | |
424 | ||
425 | case PLUS: | |
426 | print_operand (stream, XEXP (x, 0), 0); | |
427 | fputs (", ", stream); | |
428 | print_operand (stream, XEXP (x, 1), 0); | |
429 | break; | |
430 | ||
431 | default: | |
432 | abort (); | |
433 | } | |
434 | break; | |
435 | ||
436 | case 'u': | |
437 | if (GET_CODE (x) == CONST_INT) | |
438 | { | |
439 | fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1)); | |
440 | break; | |
441 | } | |
442 | /* Fall through. */ | |
443 | ||
bc45ade3 SC |
444 | default: |
445 | switch (GET_CODE (x)) | |
446 | { | |
fa5322fa AO |
447 | /* FIXME: We need this on SHmedia32 because reload generates |
448 | some sign-extended HI or QI loads into DImode registers | |
449 | but, because Pmode is SImode, the address ends up with a | |
450 | subreg:SI of the DImode register. Maybe reload should be | |
451 | fixed so as to apply alter_subreg to such loads? */ | |
452 | case SUBREG: | |
453 | if (SUBREG_BYTE (x) != 0 | |
454 | || GET_CODE (SUBREG_REG (x)) != REG) | |
455 | abort (); | |
456 | ||
457 | x = SUBREG_REG (x); | |
458 | /* Fall through. */ | |
459 | ||
bc45ade3 | 460 | case REG: |
104ee20b | 461 | if (FP_REGISTER_P (REGNO (x)) |
fa5322fa AO |
462 | && GET_MODE (x) == V16SFmode) |
463 | fprintf ((stream), "mtrx%s", reg_names[REGNO (x)] + 2); | |
464 | else if (FP_REGISTER_P (REGNO (x)) | |
465 | && GET_MODE (x) == V4SFmode) | |
466 | fprintf ((stream), "fv%s", reg_names[REGNO (x)] + 2); | |
467 | else if (GET_CODE (x) == REG | |
468 | && GET_MODE (x) == V2SFmode) | |
469 | fprintf ((stream), "fp%s", reg_names[REGNO (x)] + 2); | |
470 | else if (FP_REGISTER_P (REGNO (x)) | |
471 | && GET_MODE_SIZE (GET_MODE (x)) > 4) | |
472 | fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1); | |
225e4f43 R |
473 | else |
474 | fputs (reg_names[REGNO (x)], (stream)); | |
bc45ade3 | 475 | break; |
fa5322fa | 476 | |
bc45ade3 SC |
477 | case MEM: |
478 | output_address (XEXP (x, 0)); | |
479 | break; | |
fa5322fa AO |
480 | |
481 | case CONST: | |
482 | if (TARGET_SHMEDIA | |
483 | && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND | |
484 | && GET_MODE (XEXP (x, 0)) == DImode | |
485 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE | |
486 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode) | |
487 | { | |
488 | rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0); | |
489 | ||
490 | fputc ('(', stream); | |
491 | if (GET_CODE (val) == ASHIFTRT) | |
492 | { | |
493 | fputc ('(', stream); | |
494 | if (GET_CODE (XEXP (val, 0)) == CONST) | |
495 | fputc ('(', stream); | |
496 | output_addr_const (stream, XEXP (val, 0)); | |
497 | if (GET_CODE (XEXP (val, 0)) == CONST) | |
498 | fputc (')', stream); | |
499 | fputs (" >> ", stream); | |
500 | output_addr_const (stream, XEXP (val, 1)); | |
501 | fputc (')', stream); | |
502 | } | |
503 | else | |
504 | { | |
505 | if (GET_CODE (val) == CONST) | |
506 | fputc ('(', stream); | |
507 | output_addr_const (stream, val); | |
508 | if (GET_CODE (val) == CONST) | |
509 | fputc (')', stream); | |
510 | } | |
511 | fputs (" & 65535)", stream); | |
512 | break; | |
513 | } | |
514 | ||
515 | /* Fall through. */ | |
bc45ade3 | 516 | default: |
fa5322fa AO |
517 | if (TARGET_SH1) |
518 | fputc ('#', stream); | |
bc45ade3 SC |
519 | output_addr_const (stream, x); |
520 | break; | |
bc45ade3 SC |
521 | } |
522 | break; | |
523 | } | |
524 | } | |
bc45ade3 | 525 | \f |
0aa692fc R |
526 | /* Like force_operand, but guarantees that VALUE ends up in TARGET. */ |
527 | static void | |
528 | force_into (value, target) | |
529 | rtx value, target; | |
530 | { | |
531 | value = force_operand (value, target); | |
532 | if (! rtx_equal_p (value, target)) | |
533 | emit_insn (gen_move_insn (target, value)); | |
534 | } | |
535 | ||
0d7e008e SC |
536 | /* Emit code to perform a block move. Choose the best method. |
537 | ||
538 | OPERANDS[0] is the destination. | |
539 | OPERANDS[1] is the source. | |
540 | OPERANDS[2] is the size. | |
541 | OPERANDS[3] is the alignment safe to use. */ | |
542 | ||
0d7e008e SC |
543 | int |
544 | expand_block_move (operands) | |
545 | rtx *operands; | |
546 | { | |
547 | int align = INTVAL (operands[3]); | |
548 | int constp = (GET_CODE (operands[2]) == CONST_INT); | |
549 | int bytes = (constp ? INTVAL (operands[2]) : 0); | |
0d7e008e | 550 | |
8aa2a305 JW |
551 | /* If it isn't a constant number of bytes, or if it doesn't have 4 byte |
552 | alignment, or if it isn't a multiple of 4 bytes, then fail. */ | |
553 | if (! constp || align < 4 || (bytes % 4 != 0)) | |
d3ae8277 SC |
554 | return 0; |
555 | ||
225e4f43 R |
556 | if (TARGET_HARD_SH4) |
557 | { | |
558 | if (bytes < 12) | |
559 | return 0; | |
560 | else if (bytes == 12) | |
561 | { | |
562 | tree entry_name; | |
a6f463a0 | 563 | rtx sym; |
225e4f43 R |
564 | rtx func_addr_rtx; |
565 | rtx r4 = gen_rtx (REG, SImode, 4); | |
566 | rtx r5 = gen_rtx (REG, SImode, 5); | |
567 | ||
568 | entry_name = get_identifier ("__movstrSI12_i4"); | |
569 | ||
a6f463a0 AO |
570 | sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name)); |
571 | func_addr_rtx = copy_to_mode_reg (Pmode, sym); | |
0aa692fc R |
572 | force_into (XEXP (operands[0], 0), r4); |
573 | force_into (XEXP (operands[1], 0), r5); | |
225e4f43 R |
574 | emit_insn (gen_block_move_real_i4 (func_addr_rtx)); |
575 | return 1; | |
576 | } | |
577 | else if (! TARGET_SMALLCODE) | |
578 | { | |
579 | tree entry_name; | |
a6f463a0 | 580 | rtx sym; |
225e4f43 R |
581 | rtx func_addr_rtx; |
582 | int dwords; | |
583 | rtx r4 = gen_rtx (REG, SImode, 4); | |
584 | rtx r5 = gen_rtx (REG, SImode, 5); | |
585 | rtx r6 = gen_rtx (REG, SImode, 6); | |
586 | ||
587 | entry_name = get_identifier (bytes & 4 | |
588 | ? "__movstr_i4_odd" | |
589 | : "__movstr_i4_even"); | |
a6f463a0 AO |
590 | sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name)); |
591 | func_addr_rtx = copy_to_mode_reg (Pmode, sym); | |
0aa692fc R |
592 | force_into (XEXP (operands[0], 0), r4); |
593 | force_into (XEXP (operands[1], 0), r5); | |
225e4f43 R |
594 | |
595 | dwords = bytes >> 3; | |
596 | emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1))); | |
597 | emit_insn (gen_block_lump_real_i4 (func_addr_rtx)); | |
598 | return 1; | |
599 | } | |
600 | else | |
601 | return 0; | |
602 | } | |
8aa2a305 | 603 | if (bytes < 64) |
0d7e008e SC |
604 | { |
605 | char entry[30]; | |
606 | tree entry_name; | |
a6f463a0 | 607 | rtx sym; |
0d7e008e | 608 | rtx func_addr_rtx; |
c5c76735 JL |
609 | rtx r4 = gen_rtx_REG (SImode, 4); |
610 | rtx r5 = gen_rtx_REG (SImode, 5); | |
8aa2a305 JW |
611 | |
612 | sprintf (entry, "__movstrSI%d", bytes); | |
0d7e008e | 613 | entry_name = get_identifier (entry); |
a6f463a0 AO |
614 | sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name)); |
615 | func_addr_rtx = copy_to_mode_reg (Pmode, sym); | |
0aa692fc R |
616 | force_into (XEXP (operands[0], 0), r4); |
617 | force_into (XEXP (operands[1], 0), r5); | |
0d7e008e SC |
618 | emit_insn (gen_block_move_real (func_addr_rtx)); |
619 | return 1; | |
620 | } | |
8aa2a305 JW |
621 | |
622 | /* This is the same number of bytes as a memcpy call, but to a different | |
623 | less common function name, so this will occasionally use more space. */ | |
624 | if (! TARGET_SMALLCODE) | |
0d7e008e | 625 | { |
0d7e008e | 626 | tree entry_name; |
a6f463a0 | 627 | rtx sym; |
0d7e008e | 628 | rtx func_addr_rtx; |
8aa2a305 | 629 | int final_switch, while_loop; |
c5c76735 JL |
630 | rtx r4 = gen_rtx_REG (SImode, 4); |
631 | rtx r5 = gen_rtx_REG (SImode, 5); | |
632 | rtx r6 = gen_rtx_REG (SImode, 6); | |
0d7e008e | 633 | |
8aa2a305 | 634 | entry_name = get_identifier ("__movstr"); |
a6f463a0 AO |
635 | sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name)); |
636 | func_addr_rtx = copy_to_mode_reg (Pmode, sym); | |
0aa692fc R |
637 | force_into (XEXP (operands[0], 0), r4); |
638 | force_into (XEXP (operands[1], 0), r5); | |
0d7e008e | 639 | |
8aa2a305 JW |
640 | /* r6 controls the size of the move. 16 is decremented from it |
641 | for each 64 bytes moved. Then the negative bit left over is used | |
642 | as an index into a list of move instructions. e.g., a 72 byte move | |
643 | would be set up with size(r6) = 14, for one iteration through the | |
644 | big while loop, and a switch of -2 for the last part. */ | |
0d7e008e | 645 | |
8aa2a305 JW |
646 | final_switch = 16 - ((bytes / 4) % 16); |
647 | while_loop = ((bytes / 4) / 16 - 1) * 16; | |
648 | emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch))); | |
649 | emit_insn (gen_block_lump_real (func_addr_rtx)); | |
650 | return 1; | |
0d7e008e | 651 | } |
0d7e008e | 652 | |
d3ae8277 | 653 | return 0; |
0d7e008e SC |
654 | } |
655 | ||
bc45ade3 | 656 | /* Prepare operands for a move define_expand; specifically, one of the |
8aa2a305 | 657 | operands must be in a register. */ |
bc45ade3 | 658 | |
b9654711 | 659 | int |
bc45ade3 SC |
660 | prepare_move_operands (operands, mode) |
661 | rtx operands[]; | |
662 | enum machine_mode mode; | |
663 | { | |
fa5322fa | 664 | if ((mode == SImode || mode == DImode) && flag_pic) |
1a66cd67 AO |
665 | { |
666 | rtx temp; | |
667 | if (SYMBOLIC_CONST_P (operands[1])) | |
668 | { | |
669 | if (GET_CODE (operands[0]) == MEM) | |
670 | operands[1] = force_reg (Pmode, operands[1]); | |
fa5322fa AO |
671 | else if (GET_CODE (operands[1]) == LABEL_REF |
672 | && target_reg_operand (operands[0], mode)) | |
673 | /* It's ok. */; | |
1a66cd67 AO |
674 | else |
675 | { | |
676 | temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode); | |
fa5322fa | 677 | operands[1] = legitimize_pic_address (operands[1], mode, temp); |
1a66cd67 AO |
678 | } |
679 | } | |
680 | else if (GET_CODE (operands[1]) == CONST | |
681 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
682 | && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0))) | |
683 | { | |
68c37dc9 | 684 | temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode); |
1a66cd67 | 685 | temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0), |
fa5322fa AO |
686 | mode, temp); |
687 | operands[1] = expand_binop (mode, add_optab, temp, | |
1a66cd67 | 688 | XEXP (XEXP (operands[1], 0), 1), |
68c37dc9 AO |
689 | no_new_pseudos ? temp |
690 | : gen_reg_rtx (Pmode), | |
691 | 0, OPTAB_LIB_WIDEN); | |
1a66cd67 AO |
692 | } |
693 | } | |
694 | ||
e22856e8 JW |
695 | if (! reload_in_progress && ! reload_completed) |
696 | { | |
697 | /* Copy the source to a register if both operands aren't registers. */ | |
698 | if (! register_operand (operands[0], mode) | |
699 | && ! register_operand (operands[1], mode)) | |
700 | operands[1] = copy_to_mode_reg (mode, operands[1]); | |
701 | ||
702 | /* This case can happen while generating code to move the result | |
703 | of a library call to the target. Reject `st r0,@(rX,rY)' because | |
704 | reload will fail to find a spill register for rX, since r0 is already | |
705 | being used for the source. */ | |
706 | else if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 0 | |
707 | && GET_CODE (operands[0]) == MEM | |
708 | && GET_CODE (XEXP (operands[0], 0)) == PLUS | |
709 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG) | |
710 | operands[1] = copy_to_mode_reg (mode, operands[1]); | |
711 | } | |
8aa2a305 JW |
712 | |
713 | return 0; | |
714 | } | |
715 | ||
716 | /* Prepare the operands for an scc instruction; make sure that the | |
717 | compare has been done. */ | |
718 | rtx | |
719 | prepare_scc_operands (code) | |
720 | enum rtx_code code; | |
721 | { | |
c5c76735 | 722 | rtx t_reg = gen_rtx_REG (SImode, T_REG); |
8aa2a305 | 723 | enum rtx_code oldcode = code; |
9374bd85 | 724 | enum machine_mode mode; |
8aa2a305 JW |
725 | |
726 | /* First need a compare insn. */ | |
727 | switch (code) | |
bc45ade3 | 728 | { |
8aa2a305 JW |
729 | case NE: |
730 | /* It isn't possible to handle this case. */ | |
731 | abort (); | |
732 | case LT: | |
733 | code = GT; | |
734 | break; | |
735 | case LE: | |
736 | code = GE; | |
737 | break; | |
738 | case LTU: | |
739 | code = GTU; | |
740 | break; | |
741 | case LEU: | |
742 | code = GEU; | |
743 | break; | |
10db12e0 R |
744 | default: |
745 | break; | |
bc45ade3 | 746 | } |
8aa2a305 | 747 | if (code != oldcode) |
b9654711 | 748 | { |
8aa2a305 JW |
749 | rtx tmp = sh_compare_op0; |
750 | sh_compare_op0 = sh_compare_op1; | |
751 | sh_compare_op1 = tmp; | |
0d7e008e | 752 | } |
b9654711 | 753 | |
9374bd85 RK |
754 | mode = GET_MODE (sh_compare_op0); |
755 | if (mode == VOIDmode) | |
756 | mode = GET_MODE (sh_compare_op1); | |
757 | ||
758 | sh_compare_op0 = force_reg (mode, sh_compare_op0); | |
1245df60 R |
759 | if ((code != EQ && code != NE |
760 | && (sh_compare_op1 != const0_rtx | |
761 | || code == GTU || code == GEU || code == LTU || code == LEU)) | |
89e43e33 | 762 | || (mode == DImode && sh_compare_op1 != const0_rtx) |
318881c0 | 763 | || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT)) |
9374bd85 | 764 | sh_compare_op1 = force_reg (mode, sh_compare_op1); |
0d7e008e | 765 | |
225e4f43 R |
766 | if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT) |
767 | (mode == SFmode ? emit_sf_insn : emit_df_insn) | |
768 | (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, | |
769 | gen_rtx (SET, VOIDmode, t_reg, | |
770 | gen_rtx (code, SImode, | |
771 | sh_compare_op0, sh_compare_op1)), | |
772 | gen_rtx (USE, VOIDmode, get_fpscr_rtx ())))); | |
773 | else | |
774 | emit_insn (gen_rtx (SET, VOIDmode, t_reg, | |
775 | gen_rtx (code, SImode, sh_compare_op0, | |
776 | sh_compare_op1))); | |
0d7e008e | 777 | |
8aa2a305 | 778 | return t_reg; |
bc45ade3 SC |
779 | } |
780 | ||
8aa2a305 JW |
781 | /* Called from the md file, set up the operands of a compare instruction. */ |
782 | ||
783 | void | |
784 | from_compare (operands, code) | |
785 | rtx *operands; | |
8e87e161 | 786 | int code; |
bc45ade3 | 787 | { |
1245df60 R |
788 | enum machine_mode mode = GET_MODE (sh_compare_op0); |
789 | rtx insn; | |
790 | if (mode == VOIDmode) | |
791 | mode = GET_MODE (sh_compare_op1); | |
792 | if (code != EQ | |
793 | || mode == DImode | |
794 | || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT)) | |
bc45ade3 | 795 | { |
8aa2a305 | 796 | /* Force args into regs, since we can't use constants here. */ |
24a25d45 | 797 | sh_compare_op0 = force_reg (mode, sh_compare_op0); |
8aa2a305 | 798 | if (sh_compare_op1 != const0_rtx |
1245df60 R |
799 | || code == GTU || code == GEU |
800 | || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT)) | |
24a25d45 | 801 | sh_compare_op1 = force_reg (mode, sh_compare_op1); |
bc45ade3 | 802 | } |
1245df60 R |
803 | if (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE) |
804 | { | |
805 | from_compare (operands, GT); | |
806 | insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1); | |
807 | } | |
808 | else | |
c5c76735 | 809 | insn = gen_rtx_SET (VOIDmode, |
4773afa4 | 810 | gen_rtx_REG (SImode, T_REG), |
c5c76735 JL |
811 | gen_rtx (code, SImode, sh_compare_op0, |
812 | sh_compare_op1)); | |
225e4f43 R |
813 | if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT) |
814 | { | |
815 | insn = gen_rtx (PARALLEL, VOIDmode, | |
816 | gen_rtvec (2, insn, | |
817 | gen_rtx (USE, VOIDmode, get_fpscr_rtx ()))); | |
818 | (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn); | |
819 | } | |
820 | else | |
821 | emit_insn (insn); | |
bc45ade3 SC |
822 | } |
823 | \f | |
16bea517 | 824 | /* Functions to output assembly code. */ |
bc45ade3 | 825 | |
b9654711 | 826 | /* Return a sequence of instructions to perform DI or DF move. |
bc45ade3 | 827 | |
b9654711 | 828 | Since the SH cannot move a DI or DF in one instruction, we have |
16bea517 | 829 | to take care when we see overlapping source and dest registers. */ |
0d7e008e | 830 | |
318881c0 | 831 | const char * |
0d7e008e | 832 | output_movedouble (insn, operands, mode) |
318881c0 | 833 | rtx insn ATTRIBUTE_UNUSED; |
bc45ade3 SC |
834 | rtx operands[]; |
835 | enum machine_mode mode; | |
836 | { | |
b9654711 SC |
837 | rtx dst = operands[0]; |
838 | rtx src = operands[1]; | |
b9654711 | 839 | |
0d7e008e | 840 | if (GET_CODE (dst) == MEM |
16bea517 | 841 | && GET_CODE (XEXP (dst, 0)) == PRE_DEC) |
8aa2a305 JW |
842 | return "mov.l %T1,%0\n\tmov.l %1,%0"; |
843 | ||
b9654711 SC |
844 | if (register_operand (dst, mode) |
845 | && register_operand (src, mode)) | |
bc45ade3 | 846 | { |
b9654711 | 847 | if (REGNO (src) == MACH_REG) |
00f8ff66 | 848 | return "sts mach,%S0\n\tsts macl,%R0"; |
bc45ade3 | 849 | |
8aa2a305 JW |
850 | /* When mov.d r1,r2 do r2->r3 then r1->r2; |
851 | when mov.d r1,r0 do r1->r0 then r2->r1. */ | |
b9654711 SC |
852 | |
853 | if (REGNO (src) + 1 == REGNO (dst)) | |
5325c0fa | 854 | return "mov %T1,%T0\n\tmov %1,%0"; |
b9654711 | 855 | else |
5325c0fa | 856 | return "mov %1,%0\n\tmov %T1,%T0"; |
b9654711 SC |
857 | } |
858 | else if (GET_CODE (src) == CONST_INT) | |
bc45ade3 | 859 | { |
8aa2a305 JW |
860 | if (INTVAL (src) < 0) |
861 | output_asm_insn ("mov #-1,%S0", operands); | |
bc45ade3 | 862 | else |
8aa2a305 | 863 | output_asm_insn ("mov #0,%S0", operands); |
bc45ade3 | 864 | |
8aa2a305 | 865 | return "mov %1,%R0"; |
0d7e008e | 866 | } |
b9654711 | 867 | else if (GET_CODE (src) == MEM) |
bc45ade3 | 868 | { |
8aa2a305 | 869 | int ptrreg = -1; |
b9654711 SC |
870 | int dreg = REGNO (dst); |
871 | rtx inside = XEXP (src, 0); | |
bc45ade3 SC |
872 | |
873 | if (GET_CODE (inside) == REG) | |
8aa2a305 | 874 | ptrreg = REGNO (inside); |
79b2746a | 875 | else if (GET_CODE (inside) == SUBREG) |
ddef6bc7 | 876 | ptrreg = subreg_regno (inside); |
bc45ade3 SC |
877 | else if (GET_CODE (inside) == PLUS) |
878 | { | |
8aa2a305 JW |
879 | ptrreg = REGNO (XEXP (inside, 0)); |
880 | /* ??? A r0+REG address shouldn't be possible here, because it isn't | |
881 | an offsettable address. Unfortunately, offsettable addresses use | |
882 | QImode to check the offset, and a QImode offsettable address | |
883 | requires r0 for the other operand, which is not currently | |
884 | supported, so we can't use the 'o' constraint. | |
885 | Thus we must check for and handle r0+REG addresses here. | |
886 | We punt for now, since this is likely very rare. */ | |
887 | if (GET_CODE (XEXP (inside, 1)) == REG) | |
888 | abort (); | |
bc45ade3 | 889 | } |
0d7e008e | 890 | else if (GET_CODE (inside) == LABEL_REF) |
8aa2a305 | 891 | return "mov.l %1,%0\n\tmov.l %1+4,%T0"; |
8e87e161 | 892 | else if (GET_CODE (inside) == POST_INC) |
8aa2a305 | 893 | return "mov.l %1,%0\n\tmov.l %1,%T0"; |
bc45ade3 SC |
894 | else |
895 | abort (); | |
896 | ||
8aa2a305 JW |
897 | /* Work out the safe way to copy. Copy into the second half first. */ |
898 | if (dreg == ptrreg) | |
899 | return "mov.l %T1,%T0\n\tmov.l %1,%0"; | |
bc45ade3 SC |
900 | } |
901 | ||
00f8ff66 | 902 | return "mov.l %1,%0\n\tmov.l %T1,%T0"; |
bc45ade3 SC |
903 | } |
904 | ||
8aa2a305 JW |
905 | /* Print an instruction which would have gone into a delay slot after |
906 | another instruction, but couldn't because the other instruction expanded | |
907 | into a sequence where putting the slot insn at the end wouldn't work. */ | |
0d7e008e | 908 | |
8aa2a305 JW |
909 | static void |
910 | print_slot (insn) | |
911 | rtx insn; | |
912 | { | |
913 | final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1); | |
b9654711 | 914 | |
8aa2a305 JW |
915 | INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1; |
916 | } | |
0d7e008e | 917 | |
318881c0 | 918 | const char * |
0d7e008e SC |
919 | output_far_jump (insn, op) |
920 | rtx insn; | |
921 | rtx op; | |
922 | { | |
1245df60 | 923 | struct { rtx lab, reg, op; } this; |
950a3816 | 924 | rtx braf_base_lab = NULL_RTX; |
318881c0 | 925 | const char *jump; |
1245df60 | 926 | int far; |
9d98a694 | 927 | int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn)); |
0d7e008e | 928 | |
1245df60 | 929 | this.lab = gen_label_rtx (); |
b9654711 | 930 | |
1a953d0f R |
931 | if (TARGET_SH2 |
932 | && offset >= -32764 | |
933 | && offset - get_attr_length (insn) <= 32766) | |
1245df60 R |
934 | { |
935 | far = 0; | |
e6dfd05f | 936 | jump = "mov.w %O0,%1; braf %1"; |
1245df60 R |
937 | } |
938 | else | |
939 | { | |
940 | far = 1; | |
1a66cd67 | 941 | if (flag_pic) |
e6dfd05f AO |
942 | { |
943 | if (TARGET_SH2) | |
944 | jump = "mov.l %O0,%1; braf %1"; | |
945 | else | |
946 | jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1"; | |
947 | } | |
1a66cd67 | 948 | else |
e6dfd05f | 949 | jump = "mov.l %O0,%1; jmp @%1"; |
1245df60 R |
950 | } |
951 | /* If we have a scratch register available, use it. */ | |
952 | if (GET_CODE (PREV_INSN (insn)) == INSN | |
953 | && INSN_CODE (PREV_INSN (insn)) == CODE_FOR_indirect_jump_scratch) | |
954 | { | |
955 | this.reg = SET_DEST (PATTERN (PREV_INSN (insn))); | |
e6dfd05f AO |
956 | if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2) |
957 | jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1"; | |
1245df60 R |
958 | output_asm_insn (jump, &this.lab); |
959 | if (dbr_sequence_length ()) | |
960 | print_slot (final_sequence); | |
961 | else | |
962 | output_asm_insn ("nop", 0); | |
963 | } | |
964 | else | |
965 | { | |
966 | /* Output the delay slot insn first if any. */ | |
967 | if (dbr_sequence_length ()) | |
968 | print_slot (final_sequence); | |
969 | ||
c5c76735 | 970 | this.reg = gen_rtx_REG (SImode, 13); |
fa5322fa AO |
971 | /* We must keep the stack aligned to 8-byte boundaries on SH5. |
972 | Fortunately, MACL is fixed and call-clobbered, and we never | |
973 | need its value across jumps, so save r13 in it instead of in | |
974 | the stack. */ | |
975 | if (TARGET_SH5) | |
976 | output_asm_insn ("lds r13, macl", 0); | |
977 | else | |
978 | output_asm_insn ("mov.l r13,@-r15", 0); | |
1245df60 | 979 | output_asm_insn (jump, &this.lab); |
fa5322fa AO |
980 | if (TARGET_SH5) |
981 | output_asm_insn ("sts macl, r13", 0); | |
982 | else | |
983 | output_asm_insn ("mov.l @r15+,r13", 0); | |
1245df60 | 984 | } |
e6dfd05f AO |
985 | if (far && flag_pic && TARGET_SH2) |
986 | { | |
987 | braf_base_lab = gen_label_rtx (); | |
988 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", | |
989 | CODE_LABEL_NUMBER (braf_base_lab)); | |
990 | } | |
1245df60 R |
991 | if (far) |
992 | output_asm_insn (".align 2", 0); | |
993 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab)); | |
994 | this.op = op; | |
1a66cd67 | 995 | if (far && flag_pic) |
e6dfd05f AO |
996 | { |
997 | if (TARGET_SH2) | |
998 | this.lab = braf_base_lab; | |
999 | output_asm_insn (".long %O2-%O0", &this.lab); | |
1000 | } | |
1a66cd67 AO |
1001 | else |
1002 | output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab); | |
0d7e008e SC |
1003 | return ""; |
1004 | } | |
bc45ade3 | 1005 | |
8aa2a305 JW |
1006 | /* Local label counter, used for constants in the pool and inside |
1007 | pattern branches. */ | |
1008 | ||
1009 | static int lf = 100; | |
1010 | ||
1011 | /* Output code for ordinary branches. */ | |
1012 | ||
318881c0 | 1013 | const char * |
8aa2a305 | 1014 | output_branch (logic, insn, operands) |
bc45ade3 | 1015 | int logic; |
b9654711 | 1016 | rtx insn; |
8aa2a305 | 1017 | rtx *operands; |
bc45ade3 | 1018 | { |
afbc5d86 | 1019 | switch (get_attr_length (insn)) |
bc45ade3 | 1020 | { |
33f7f353 JR |
1021 | case 6: |
1022 | /* This can happen if filling the delay slot has caused a forward | |
1023 | branch to exceed its range (we could reverse it, but only | |
1024 | when we know we won't overextend other branches; this should | |
1025 | best be handled by relaxation). | |
1026 | It can also happen when other condbranches hoist delay slot insn | |
1245df60 R |
1027 | from their destination, thus leading to code size increase. |
1028 | But the branch will still be in the range -4092..+4098 bytes. */ | |
bc45ade3 | 1029 | |
33f7f353 | 1030 | if (! TARGET_RELAX) |
1245df60 | 1031 | { |
33f7f353 JR |
1032 | int label = lf++; |
1033 | /* The call to print_slot will clobber the operands. */ | |
1034 | rtx op0 = operands[0]; | |
1035 | ||
1036 | /* If the instruction in the delay slot is annulled (true), then | |
1037 | there is no delay slot where we can put it now. The only safe | |
1038 | place for it is after the label. final will do that by default. */ | |
1039 | ||
1040 | if (final_sequence | |
1041 | && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))) | |
1042 | { | |
afbc5d86 | 1043 | asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t", |
33f7f353 JR |
1044 | ASSEMBLER_DIALECT ? "/" : ".", label); |
1045 | print_slot (final_sequence); | |
1046 | } | |
1047 | else | |
afbc5d86 | 1048 | asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label); |
33f7f353 | 1049 | |
afbc5d86 R |
1050 | output_asm_insn ("bra\t%l0", &op0); |
1051 | fprintf (asm_out_file, "\tnop\n"); | |
1052 | ASM_OUTPUT_INTERNAL_LABEL(asm_out_file, "LF", label); | |
33f7f353 JR |
1053 | |
1054 | return ""; | |
1245df60 | 1055 | } |
33f7f353 JR |
1056 | /* When relaxing, handle this like a short branch. The linker |
1057 | will fix it up if it still doesn't fit after relaxation. */ | |
1058 | case 2: | |
1059 | return logic ? "bt%.\t%l0" : "bf%.\t%l0"; | |
1060 | default: | |
afbc5d86 R |
1061 | /* There should be no longer branches now - that would |
1062 | indicate that something has destroyed the branches set | |
1063 | up in machine_dependent_reorg. */ | |
33f7f353 | 1064 | abort (); |
1245df60 | 1065 | } |
1245df60 | 1066 | } |
bc45ade3 | 1067 | |
318881c0 | 1068 | const char * |
1245df60 | 1069 | output_branchy_insn (code, template, insn, operands) |
1245df60 | 1070 | enum rtx_code code; |
318881c0 | 1071 | const char *template; |
1245df60 R |
1072 | rtx insn; |
1073 | rtx *operands; | |
1074 | { | |
1075 | rtx next_insn = NEXT_INSN (insn); | |
79b2746a | 1076 | |
1245df60 R |
1077 | if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn)) |
1078 | { | |
1079 | rtx src = SET_SRC (PATTERN (next_insn)); | |
1080 | if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code) | |
1081 | { | |
1082 | /* Following branch not taken */ | |
1083 | operands[9] = gen_label_rtx (); | |
1084 | emit_label_after (operands[9], next_insn); | |
9d98a694 AO |
1085 | INSN_ADDRESSES_NEW (operands[9], |
1086 | INSN_ADDRESSES (INSN_UID (next_insn)) | |
1087 | + get_attr_length (next_insn)); | |
1245df60 R |
1088 | return template; |
1089 | } | |
1090 | else | |
1091 | { | |
33f7f353 | 1092 | int offset = (branch_dest (next_insn) |
9d98a694 | 1093 | - INSN_ADDRESSES (INSN_UID (next_insn)) + 4); |
33f7f353 | 1094 | if (offset >= -252 && offset <= 258) |
1245df60 R |
1095 | { |
1096 | if (GET_CODE (src) == IF_THEN_ELSE) | |
1097 | /* branch_true */ | |
1098 | src = XEXP (src, 1); | |
1099 | operands[9] = src; | |
1100 | return template; | |
1101 | } | |
1102 | } | |
bc45ade3 | 1103 | } |
1245df60 R |
1104 | operands[9] = gen_label_rtx (); |
1105 | emit_label_after (operands[9], insn); | |
9d98a694 AO |
1106 | INSN_ADDRESSES_NEW (operands[9], |
1107 | INSN_ADDRESSES (INSN_UID (insn)) | |
1108 | + get_attr_length (insn)); | |
1245df60 R |
1109 | return template; |
1110 | } | |
e4fa6b06 | 1111 | |
318881c0 | 1112 | const char * |
1245df60 | 1113 | output_ieee_ccmpeq (insn, operands) |
318881c0 | 1114 | rtx insn, *operands; |
1245df60 | 1115 | { |
318881c0 | 1116 | return output_branchy_insn (NE, "bt\t%l9\\;fcmp/eq\t%1,%0", insn, operands); |
bc45ade3 | 1117 | } |
8e87e161 | 1118 | \f |
8aa2a305 JW |
1119 | /* Output to FILE the start of the assembler file. */ |
1120 | ||
0d7e008e | 1121 | void |
adade868 | 1122 | output_file_start (file) |
0d7e008e | 1123 | FILE *file; |
bc45ade3 | 1124 | { |
0d7e008e | 1125 | output_file_directive (file, main_input_filename); |
b9654711 | 1126 | |
acb0db7b ZW |
1127 | /* Switch to the data section so that the coffsem symbol |
1128 | isn't in the text section. */ | |
0d7e008e | 1129 | data_section (); |
b9654711 | 1130 | |
8aa2a305 JW |
1131 | if (TARGET_LITTLE_ENDIAN) |
1132 | fprintf (file, "\t.little\n"); | |
fa5322fa AO |
1133 | |
1134 | if (TARGET_SHCOMPACT) | |
1135 | fprintf (file, "\t.mode\tSHcompact\n"); | |
1136 | else if (TARGET_SHMEDIA) | |
1137 | fprintf (file, "\t.mode\tSHmedia\n\t.abi\t%i\n", | |
1138 | TARGET_SHMEDIA64 ? 64 : 32); | |
bc45ade3 | 1139 | } |
0d7e008e | 1140 | \f |
16bea517 | 1141 | /* Actual number of instructions used to make a shift by N. */ |
0b5826ac | 1142 | static const char ashiftrt_insns[] = |
16bea517 JW |
1143 | { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2}; |
1144 | ||
1145 | /* Left shift and logical right shift are the same. */ | |
0b5826ac | 1146 | static const char shift_insns[] = |
16bea517 | 1147 | { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3}; |
8aa2a305 | 1148 | |
16bea517 JW |
1149 | /* Individual shift amounts needed to get the above length sequences. |
1150 | One bit right shifts clobber the T bit, so when possible, put one bit | |
1151 | shifts in the middle of the sequence, so the ends are eligible for | |
1152 | branch delay slots. */ | |
0139adca | 1153 | static const short shift_amounts[32][5] = { |
16bea517 JW |
1154 | {0}, {1}, {2}, {2, 1}, |
1155 | {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2}, | |
1156 | {8}, {8, 1}, {8, 2}, {8, 1, 2}, | |
1157 | {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8}, | |
1158 | {16}, {16, 1}, {16, 2}, {16, 1, 2}, | |
1159 | {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8}, | |
1160 | {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2}, | |
1d3534c0 | 1161 | {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}}; |
16bea517 | 1162 | |
8d481241 JW |
1163 | /* Likewise, but for shift amounts < 16, up to three highmost bits |
1164 | might be clobbered. This is typically used when combined with some | |
1165 | kind of sign or zero extension. */ | |
1166 | ||
0b5826ac | 1167 | static const char ext_shift_insns[] = |
8d481241 JW |
1168 | { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3}; |
1169 | ||
0b5826ac | 1170 | static const short ext_shift_amounts[32][4] = { |
8d481241 JW |
1171 | {0}, {1}, {2}, {2, 1}, |
1172 | {2, 2}, {2, 1, 2}, {8, -2}, {8, -1}, | |
1173 | {8}, {8, 1}, {8, 2}, {8, 1, 2}, | |
1174 | {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1}, | |
1175 | {16}, {16, 1}, {16, 2}, {16, 1, 2}, | |
1176 | {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8}, | |
1177 | {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2}, | |
1178 | {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}}; | |
1179 | ||
ae9d19c0 JR |
1180 | /* Assuming we have a value that has been sign-extended by at least one bit, |
1181 | can we use the ext_shift_amounts with the last shift turned to an arithmetic shift | |
1182 | to shift it by N without data loss, and quicker than by other means? */ | |
1183 | #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15) | |
1184 | ||
16bea517 JW |
1185 | /* This is used in length attributes in sh.md to help compute the length |
1186 | of arbitrary constant shift instructions. */ | |
bc45ade3 | 1187 | |
16bea517 JW |
1188 | int |
1189 | shift_insns_rtx (insn) | |
1190 | rtx insn; | |
1191 | { | |
1192 | rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
1193 | int shift_count = INTVAL (XEXP (set_src, 1)); | |
1194 | enum rtx_code shift_code = GET_CODE (set_src); | |
00f8ff66 | 1195 | |
16bea517 JW |
1196 | switch (shift_code) |
1197 | { | |
1198 | case ASHIFTRT: | |
1199 | return ashiftrt_insns[shift_count]; | |
1200 | case LSHIFTRT: | |
1201 | case ASHIFT: | |
1202 | return shift_insns[shift_count]; | |
1203 | default: | |
1204 | abort(); | |
1205 | } | |
1206 | } | |
1207 | ||
16bea517 | 1208 | /* Return the cost of a shift. */ |
bc45ade3 | 1209 | |
0d7e008e | 1210 | int |
8aa2a305 JW |
1211 | shiftcosts (x) |
1212 | rtx x; | |
bc45ade3 | 1213 | { |
3d422cb1 | 1214 | int value; |
8aa2a305 | 1215 | |
fa5322fa AO |
1216 | if (TARGET_SHMEDIA) |
1217 | return 1; | |
1218 | ||
c762ab6e R |
1219 | if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) |
1220 | { | |
1221 | if (GET_MODE (x) == DImode | |
1222 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1223 | && INTVAL (XEXP (x, 1)) == 1) | |
1224 | return 2; | |
1225 | ||
1226 | /* Everything else is invalid, because there is no pattern for it. */ | |
1227 | return 10000; | |
1228 | } | |
16bea517 | 1229 | /* If shift by a non constant, then this will be expensive. */ |
8aa2a305 | 1230 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) |
1245df60 | 1231 | return SH_DYNAMIC_SHIFT_COST; |
bc45ade3 | 1232 | |
3d422cb1 AO |
1233 | value = INTVAL (XEXP (x, 1)); |
1234 | ||
16bea517 | 1235 | /* Otherwise, return the true cost in instructions. */ |
8aa2a305 | 1236 | if (GET_CODE (x) == ASHIFTRT) |
49b6d06b JW |
1237 | { |
1238 | int cost = ashiftrt_insns[value]; | |
1239 | /* If SH3, then we put the constant in a reg and use shad. */ | |
1245df60 R |
1240 | if (cost > 1 + SH_DYNAMIC_SHIFT_COST) |
1241 | cost = 1 + SH_DYNAMIC_SHIFT_COST; | |
49b6d06b JW |
1242 | return cost; |
1243 | } | |
8aa2a305 JW |
1244 | else |
1245 | return shift_insns[value]; | |
0d7e008e | 1246 | } |
b9654711 | 1247 | |
8aa2a305 JW |
1248 | /* Return the cost of an AND operation. */ |
1249 | ||
8e87e161 | 1250 | int |
8aa2a305 JW |
1251 | andcosts (x) |
1252 | rtx x; | |
0d7e008e SC |
1253 | { |
1254 | int i; | |
8aa2a305 | 1255 | |
a6f71af5 | 1256 | /* Anding with a register is a single cycle and instruction. */ |
8aa2a305 | 1257 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) |
a6f71af5 | 1258 | return 1; |
8aa2a305 JW |
1259 | |
1260 | i = INTVAL (XEXP (x, 1)); | |
fa5322fa AO |
1261 | |
1262 | if (TARGET_SHMEDIA) | |
1263 | { | |
1264 | if ((GET_CODE (XEXP (x, 1)) == CONST_INT | |
1265 | && CONST_OK_FOR_J (INTVAL (XEXP (x, 1)))) | |
1266 | || EXTRA_CONSTRAINT_S (XEXP (x, 1))) | |
1267 | return 1; | |
1268 | else | |
1269 | return 2; | |
1270 | } | |
1271 | ||
a6f71af5 | 1272 | /* These constants are single cycle extu.[bw] instructions. */ |
0d7e008e | 1273 | if (i == 0xff || i == 0xffff) |
a6f71af5 JW |
1274 | return 1; |
1275 | /* Constants that can be used in an and immediate instruction is a single | |
1276 | cycle, but this requires r0, so make it a little more expensive. */ | |
1277 | if (CONST_OK_FOR_L (i)) | |
0d7e008e | 1278 | return 2; |
a6f71af5 JW |
1279 | /* Constants that can be loaded with a mov immediate and an and. |
1280 | This case is probably unnecessary. */ | |
0d7e008e | 1281 | if (CONST_OK_FOR_I (i)) |
a6f71af5 JW |
1282 | return 2; |
1283 | /* Any other constants requires a 2 cycle pc-relative load plus an and. | |
1284 | This case is probably unnecessary. */ | |
1285 | return 3; | |
0d7e008e | 1286 | } |
d3ae8277 | 1287 | |
630c79be BS |
1288 | /* Return the cost of an addition or a subtraction. */ |
1289 | ||
1290 | int | |
1291 | addsubcosts (x) | |
1292 | rtx x; | |
1293 | { | |
1294 | /* Adding a register is a single cycle insn. */ | |
50ceefc2 R |
1295 | if (GET_CODE (XEXP (x, 1)) == REG |
1296 | || GET_CODE (XEXP (x, 1)) == SUBREG) | |
630c79be BS |
1297 | return 1; |
1298 | ||
1299 | /* Likewise for small constants. */ | |
3d422cb1 | 1300 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
fa5322fa | 1301 | && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1)))) |
630c79be BS |
1302 | return 1; |
1303 | ||
fa5322fa AO |
1304 | if (TARGET_SHMEDIA) |
1305 | switch (GET_CODE (XEXP (x, 1))) | |
1306 | { | |
1307 | case CONST: | |
1308 | case LABEL_REF: | |
1309 | case SYMBOL_REF: | |
1310 | return TARGET_SHMEDIA64 ? 5 : 3; | |
1311 | ||
1312 | case CONST_INT: | |
1313 | if (CONST_OK_FOR_J (INTVAL (XEXP (x, 1)))) | |
1314 | return 2; | |
1315 | else if (CONST_OK_FOR_J (INTVAL (XEXP (x, 1)) >> 16)) | |
1316 | return 3; | |
1317 | else if (CONST_OK_FOR_J ((INTVAL (XEXP (x, 1)) >> 16) >> 16)) | |
1318 | return 4; | |
1319 | ||
1320 | /* Fall through. */ | |
1321 | default: | |
1322 | return 5; | |
1323 | } | |
1324 | ||
630c79be BS |
1325 | /* Any other constant requires a 2 cycle pc-relative load plus an |
1326 | addition. */ | |
1327 | return 3; | |
1328 | } | |
1329 | ||
16bea517 | 1330 | /* Return the cost of a multiply. */ |
0d7e008e | 1331 | int |
8aa2a305 | 1332 | multcosts (x) |
318881c0 | 1333 | rtx x ATTRIBUTE_UNUSED; |
0d7e008e | 1334 | { |
fa5322fa AO |
1335 | if (TARGET_SHMEDIA) |
1336 | return 3; | |
1337 | ||
0d7e008e | 1338 | if (TARGET_SH2) |
d3ae8277 SC |
1339 | { |
1340 | /* We have a mul insn, so we can never take more than the mul and the | |
a7771f78 | 1341 | read of the mac reg, but count more because of the latency and extra |
16bea517 | 1342 | reg usage. */ |
d3ae8277 | 1343 | if (TARGET_SMALLCODE) |
8e87e161 | 1344 | return 2; |
a7771f78 | 1345 | return 3; |
d3ae8277 SC |
1346 | } |
1347 | ||
a7771f78 | 1348 | /* If we're aiming at small code, then just count the number of |
16bea517 | 1349 | insns in a multiply call sequence. */ |
8e87e161 | 1350 | if (TARGET_SMALLCODE) |
8aa2a305 | 1351 | return 5; |
d3ae8277 | 1352 | |
16bea517 | 1353 | /* Otherwise count all the insns in the routine we'd be calling too. */ |
d3ae8277 | 1354 | return 20; |
0d7e008e | 1355 | } |
b9654711 | 1356 | |
16bea517 | 1357 | /* Code to expand a shift. */ |
b9654711 | 1358 | |
0d7e008e SC |
1359 | void |
1360 | gen_ashift (type, n, reg) | |
1361 | int type; | |
1362 | int n; | |
1363 | rtx reg; | |
1364 | { | |
16bea517 JW |
1365 | /* Negative values here come from the shift_amounts array. */ |
1366 | if (n < 0) | |
1367 | { | |
1368 | if (type == ASHIFT) | |
1369 | type = LSHIFTRT; | |
1370 | else | |
1371 | type = ASHIFT; | |
1372 | n = -n; | |
1373 | } | |
1374 | ||
0d7e008e | 1375 | switch (type) |
bc45ade3 | 1376 | { |
0d7e008e SC |
1377 | case ASHIFTRT: |
1378 | emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n))); | |
1379 | break; | |
1380 | case LSHIFTRT: | |
16bea517 JW |
1381 | if (n == 1) |
1382 | emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n))); | |
1383 | else | |
1384 | emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n))); | |
0d7e008e SC |
1385 | break; |
1386 | case ASHIFT: | |
7e2fda6e | 1387 | emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n))); |
0d7e008e | 1388 | break; |
bc45ade3 | 1389 | } |
bc45ade3 | 1390 | } |
bc45ade3 | 1391 | |
8d481241 JW |
1392 | /* Same for HImode */ |
1393 | ||
1394 | void | |
1395 | gen_ashift_hi (type, n, reg) | |
1396 | int type; | |
1397 | int n; | |
1398 | rtx reg; | |
1399 | { | |
1400 | /* Negative values here come from the shift_amounts array. */ | |
1401 | if (n < 0) | |
1402 | { | |
1403 | if (type == ASHIFT) | |
1404 | type = LSHIFTRT; | |
1405 | else | |
1406 | type = ASHIFT; | |
1407 | n = -n; | |
1408 | } | |
1409 | ||
1410 | switch (type) | |
1411 | { | |
1412 | case ASHIFTRT: | |
8d481241 | 1413 | case LSHIFTRT: |
d0c42859 R |
1414 | /* We don't have HImode right shift operations because using the |
1415 | ordinary 32 bit shift instructions for that doesn't generate proper | |
1416 | zero/sign extension. | |
1417 | gen_ashift_hi is only called in contexts where we know that the | |
1418 | sign extension works out correctly. */ | |
97d6fd65 | 1419 | { |
ddef6bc7 | 1420 | int offset = 0; |
97d6fd65 R |
1421 | if (GET_CODE (reg) == SUBREG) |
1422 | { | |
ddef6bc7 | 1423 | offset = SUBREG_BYTE (reg); |
97d6fd65 R |
1424 | reg = SUBREG_REG (reg); |
1425 | } | |
ddef6bc7 | 1426 | gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset)); |
97d6fd65 R |
1427 | break; |
1428 | } | |
8d481241 JW |
1429 | case ASHIFT: |
1430 | emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n))); | |
1431 | break; | |
1432 | } | |
1433 | } | |
1434 | ||
8aa2a305 JW |
1435 | /* Output RTL to split a constant shift into its component SH constant |
1436 | shift instructions. */ | |
1437 | ||
318881c0 | 1438 | void |
0d7e008e SC |
1439 | gen_shifty_op (code, operands) |
1440 | int code; | |
1441 | rtx *operands; | |
bc45ade3 | 1442 | { |
16bea517 | 1443 | int value = INTVAL (operands[2]); |
8aa2a305 | 1444 | int max, i; |
00f8ff66 | 1445 | |
cff3d762 JW |
1446 | /* Truncate the shift count in case it is out of bounds. */ |
1447 | value = value & 0x1f; | |
1448 | ||
8aa2a305 | 1449 | if (value == 31) |
16bea517 | 1450 | { |
8aa2a305 | 1451 | if (code == LSHIFTRT) |
0d7e008e | 1452 | { |
8aa2a305 JW |
1453 | emit_insn (gen_rotlsi3_1 (operands[0], operands[0])); |
1454 | emit_insn (gen_movt (operands[0])); | |
1455 | return; | |
16bea517 | 1456 | } |
8aa2a305 | 1457 | else if (code == ASHIFT) |
16bea517 | 1458 | { |
8aa2a305 JW |
1459 | /* There is a two instruction sequence for 31 bit left shifts, |
1460 | but it requires r0. */ | |
1461 | if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0) | |
0d7e008e | 1462 | { |
8aa2a305 JW |
1463 | emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx)); |
1464 | emit_insn (gen_rotlsi3_31 (operands[0], operands[0])); | |
1465 | return; | |
0d7e008e | 1466 | } |
16bea517 | 1467 | } |
8aa2a305 | 1468 | } |
c17f53a8 JW |
1469 | else if (value == 0) |
1470 | { | |
1471 | /* This can happen when not optimizing. We must output something here | |
1472 | to prevent the compiler from aborting in final.c after the try_split | |
1473 | call. */ | |
1474 | emit_insn (gen_nop ()); | |
1475 | return; | |
1476 | } | |
a9f71ad8 | 1477 | |
8aa2a305 JW |
1478 | max = shift_insns[value]; |
1479 | for (i = 0; i < max; i++) | |
1480 | gen_ashift (code, shift_amounts[value][i], operands[0]); | |
1481 | } | |
8d481241 JW |
1482 | |
1483 | /* Same as above, but optimized for values where the topmost bits don't | |
1484 | matter. */ | |
1485 | ||
318881c0 | 1486 | void |
8d481241 JW |
1487 | gen_shifty_hi_op (code, operands) |
1488 | int code; | |
1489 | rtx *operands; | |
1490 | { | |
1491 | int value = INTVAL (operands[2]); | |
1492 | int max, i; | |
318881c0 | 1493 | void (*gen_fun) PARAMS ((int, int, rtx)); |
8d481241 JW |
1494 | |
1495 | /* This operation is used by and_shl for SImode values with a few | |
1496 | high bits known to be cleared. */ | |
1497 | value &= 31; | |
1498 | if (value == 0) | |
1499 | { | |
1500 | emit_insn (gen_nop ()); | |
1501 | return; | |
1502 | } | |
1503 | ||
1504 | gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift; | |
1505 | if (code == ASHIFT) | |
1506 | { | |
1507 | max = ext_shift_insns[value]; | |
1508 | for (i = 0; i < max; i++) | |
1509 | gen_fun (code, ext_shift_amounts[value][i], operands[0]); | |
1510 | } | |
1511 | else | |
1512 | /* When shifting right, emit the shifts in reverse order, so that | |
1513 | solitary negative values come first. */ | |
1514 | for (i = ext_shift_insns[value] - 1; i >= 0; i--) | |
1515 | gen_fun (code, ext_shift_amounts[value][i], operands[0]); | |
1516 | } | |
8aa2a305 JW |
1517 | |
1518 | /* Output RTL for an arithmetic right shift. */ | |
1519 | ||
1520 | /* ??? Rewrite to use super-optimizer sequences. */ | |
1521 | ||
1522 | int | |
1523 | expand_ashiftrt (operands) | |
1524 | rtx *operands; | |
1525 | { | |
a6f463a0 | 1526 | rtx sym; |
8aa2a305 JW |
1527 | rtx wrk; |
1528 | char func[18]; | |
1529 | tree func_name; | |
1530 | int value; | |
1531 | ||
49b6d06b | 1532 | if (TARGET_SH3) |
20b04867 | 1533 | { |
49b6d06b JW |
1534 | if (GET_CODE (operands[2]) != CONST_INT) |
1535 | { | |
1536 | rtx count = copy_to_mode_reg (SImode, operands[2]); | |
1537 | emit_insn (gen_negsi2 (count, count)); | |
1538 | emit_insn (gen_ashrsi3_d (operands[0], operands[1], count)); | |
1539 | return 1; | |
1540 | } | |
1245df60 R |
1541 | else if (ashiftrt_insns[INTVAL (operands[2]) & 31] |
1542 | > 1 + SH_DYNAMIC_SHIFT_COST) | |
49b6d06b | 1543 | { |
1245df60 R |
1544 | rtx count |
1545 | = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31))); | |
49b6d06b JW |
1546 | emit_insn (gen_ashrsi3_d (operands[0], operands[1], count)); |
1547 | return 1; | |
1548 | } | |
20b04867 | 1549 | } |
8aa2a305 JW |
1550 | if (GET_CODE (operands[2]) != CONST_INT) |
1551 | return 0; | |
1552 | ||
1245df60 | 1553 | value = INTVAL (operands[2]) & 31; |
8aa2a305 JW |
1554 | |
1555 | if (value == 31) | |
1556 | { | |
1557 | emit_insn (gen_ashrsi2_31 (operands[0], operands[1])); | |
1558 | return 1; | |
1559 | } | |
1560 | else if (value >= 16 && value <= 19) | |
1561 | { | |
1562 | wrk = gen_reg_rtx (SImode); | |
1563 | emit_insn (gen_ashrsi2_16 (wrk, operands[1])); | |
1564 | value -= 16; | |
1565 | while (value--) | |
1566 | gen_ashift (ASHIFTRT, 1, wrk); | |
1567 | emit_move_insn (operands[0], wrk); | |
1568 | return 1; | |
a9f71ad8 | 1569 | } |
8aa2a305 JW |
1570 | /* Expand a short sequence inline, longer call a magic routine. */ |
1571 | else if (value <= 5) | |
1572 | { | |
1573 | wrk = gen_reg_rtx (SImode); | |
1574 | emit_move_insn (wrk, operands[1]); | |
1575 | while (value--) | |
1576 | gen_ashift (ASHIFTRT, 1, wrk); | |
1577 | emit_move_insn (operands[0], wrk); | |
1578 | return 1; | |
1579 | } | |
1580 | ||
1581 | wrk = gen_reg_rtx (Pmode); | |
1582 | ||
1583 | /* Load the value into an arg reg and call a helper. */ | |
c5c76735 | 1584 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]); |
8aa2a305 JW |
1585 | sprintf (func, "__ashiftrt_r4_%d", value); |
1586 | func_name = get_identifier (func); | |
a6f463a0 AO |
1587 | sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (func_name)); |
1588 | emit_move_insn (wrk, sym); | |
8aa2a305 | 1589 | emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk)); |
c5c76735 | 1590 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 4)); |
8aa2a305 | 1591 | return 1; |
bc45ade3 | 1592 | } |
8d481241 | 1593 | |
318881c0 KG |
1594 | int |
1595 | sh_dynamicalize_shift_p (count) | |
1245df60 R |
1596 | rtx count; |
1597 | { | |
1598 | return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST; | |
1599 | } | |
1600 | ||
8d481241 JW |
1601 | /* Try to find a good way to implement the combiner pattern |
1602 | [(set (match_operand:SI 0 "register_operand" "r") | |
1603 | (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") | |
1604 | (match_operand:SI 2 "const_int_operand" "n")) | |
1605 | (match_operand:SI 3 "const_int_operand" "n"))) . | |
1606 | LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3. | |
1607 | return 0 for simple right / left or left/right shift combination. | |
1608 | return 1 for a combination of shifts with zero_extend. | |
1609 | return 2 for a combination of shifts with an AND that needs r0. | |
1610 | return 3 for a combination of shifts with an AND that needs an extra | |
1611 | scratch register, when the three highmost bits of the AND mask are clear. | |
1612 | return 4 for a combination of shifts with an AND that needs an extra | |
1613 | scratch register, when any of the three highmost bits of the AND mask | |
1614 | is set. | |
1615 | If ATTRP is set, store an initial right shift width in ATTRP[0], | |
1616 | and the instruction length in ATTRP[1] . These values are not valid | |
1617 | when returning 0. | |
1618 | When ATTRP is set and returning 1, ATTRP[2] gets set to the index into | |
1619 | shift_amounts for the last shift value that is to be used before the | |
1620 | sign extend. */ | |
1621 | int | |
1622 | shl_and_kind (left_rtx, mask_rtx, attrp) | |
1623 | rtx left_rtx, mask_rtx; | |
1624 | int *attrp; | |
1625 | { | |
1626 | unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2; | |
1627 | int left = INTVAL (left_rtx), right; | |
1628 | int best = 0; | |
1629 | int cost, best_cost = 10000; | |
1630 | int best_right = 0, best_len = 0; | |
1631 | int i; | |
1632 | int can_ext; | |
1633 | ||
1634 | if (left < 0 || left > 31) | |
1635 | return 0; | |
1636 | if (GET_CODE (mask_rtx) == CONST_INT) | |
1637 | mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left; | |
1638 | else | |
1639 | mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left; | |
1640 | /* Can this be expressed as a right shift / left shift pair ? */ | |
1641 | lsb = ((mask ^ (mask - 1)) >> 1) + 1; | |
1642 | right = exact_log2 (lsb); | |
1643 | mask2 = ~(mask + lsb - 1); | |
1644 | lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1; | |
1645 | /* mask has no zeroes but trailing zeroes <==> ! mask2 */ | |
1646 | if (! mask2) | |
1647 | best_cost = shift_insns[right] + shift_insns[right + left]; | |
1648 | /* mask has no trailing zeroes <==> ! right */ | |
1649 | else if (! right && mask2 == ~(lsb2 - 1)) | |
1650 | { | |
1651 | int late_right = exact_log2 (lsb2); | |
1652 | best_cost = shift_insns[left + late_right] + shift_insns[late_right]; | |
1653 | } | |
1654 | /* Try to use zero extend */ | |
1655 | if (mask2 == ~(lsb2 - 1)) | |
1656 | { | |
1657 | int width, first; | |
1658 | ||
1659 | for (width = 8; width <= 16; width += 8) | |
1660 | { | |
1661 | /* Can we zero-extend right away? */ | |
318881c0 | 1662 | if (lsb2 == (unsigned HOST_WIDE_INT)1 << width) |
8d481241 JW |
1663 | { |
1664 | cost | |
1665 | = 1 + ext_shift_insns[right] + ext_shift_insns[left + right]; | |
1666 | if (cost < best_cost) | |
1667 | { | |
1668 | best = 1; | |
1669 | best_cost = cost; | |
1670 | best_right = right; | |
1671 | best_len = cost; | |
1672 | if (attrp) | |
1673 | attrp[2] = -1; | |
1674 | } | |
1675 | continue; | |
1676 | } | |
1677 | /* ??? Could try to put zero extend into initial right shift, | |
6f317ef3 | 1678 | or even shift a bit left before the right shift. */ |
8d481241 JW |
1679 | /* Determine value of first part of left shift, to get to the |
1680 | zero extend cut-off point. */ | |
1681 | first = width - exact_log2 (lsb2) + right; | |
1682 | if (first >= 0 && right + left - first >= 0) | |
1683 | { | |
1684 | cost = ext_shift_insns[right] + ext_shift_insns[first] + 1 | |
1685 | + ext_shift_insns[right + left - first]; | |
1686 | if (cost < best_cost) | |
1687 | { | |
1688 | best = 1; | |
1689 | best_cost = cost; | |
1690 | best_right = right; | |
1691 | best_len = cost; | |
1692 | if (attrp) | |
1693 | attrp[2] = first; | |
1694 | } | |
1695 | } | |
1696 | } | |
1697 | } | |
1698 | /* Try to use r0 AND pattern */ | |
1699 | for (i = 0; i <= 2; i++) | |
1700 | { | |
1701 | if (i > right) | |
1702 | break; | |
1703 | if (! CONST_OK_FOR_L (mask >> i)) | |
1704 | continue; | |
1705 | cost = (i != 0) + 2 + ext_shift_insns[left + i]; | |
1706 | if (cost < best_cost) | |
1707 | { | |
1708 | best = 2; | |
1709 | best_cost = cost; | |
1710 | best_right = i; | |
1711 | best_len = cost - 1; | |
1712 | } | |
1713 | } | |
1714 | /* Try to use a scratch register to hold the AND operand. */ | |
c5b9ef02 | 1715 | can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT)3 << 30)) == 0; |
8d481241 JW |
1716 | for (i = 0; i <= 2; i++) |
1717 | { | |
1718 | if (i > right) | |
1719 | break; | |
1720 | cost = (i != 0) + (CONST_OK_FOR_I (mask >> i) ? 2 : 3) | |
6ab911bb | 1721 | + (can_ext ? ext_shift_insns : shift_insns)[left + i]; |
8d481241 JW |
1722 | if (cost < best_cost) |
1723 | { | |
1724 | best = 4 - can_ext; | |
1725 | best_cost = cost; | |
1726 | best_right = i; | |
1727 | best_len = cost - 1 - ! CONST_OK_FOR_I (mask >> i); | |
1728 | } | |
1729 | } | |
1730 | ||
1731 | if (attrp) | |
1732 | { | |
1733 | attrp[0] = best_right; | |
1734 | attrp[1] = best_len; | |
1735 | } | |
1736 | return best; | |
1737 | } | |
1738 | ||
1739 | /* This is used in length attributes of the unnamed instructions | |
1740 | corresponding to shl_and_kind return values of 1 and 2. */ | |
1741 | int | |
1742 | shl_and_length (insn) | |
1743 | rtx insn; | |
1744 | { | |
1745 | rtx set_src, left_rtx, mask_rtx; | |
1746 | int attributes[3]; | |
1747 | ||
1748 | set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
1749 | left_rtx = XEXP (XEXP (set_src, 0), 1); | |
1750 | mask_rtx = XEXP (set_src, 1); | |
1751 | shl_and_kind (left_rtx, mask_rtx, attributes); | |
1752 | return attributes[1]; | |
1753 | } | |
1754 | ||
1755 | /* This is used in length attribute of the and_shl_scratch instruction. */ | |
1756 | ||
1757 | int | |
1758 | shl_and_scr_length (insn) | |
1759 | rtx insn; | |
1760 | { | |
1761 | rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
1762 | int len = shift_insns[INTVAL (XEXP (set_src, 1))]; | |
1763 | rtx op = XEXP (set_src, 0); | |
1764 | len += shift_insns[INTVAL (XEXP (op, 1))] + 1; | |
1765 | op = XEXP (XEXP (op, 0), 0); | |
1766 | return len + shift_insns[INTVAL (XEXP (op, 1))]; | |
1767 | } | |
1768 | ||
1769 | /* Generating rtl? */ | |
1770 | extern int rtx_equal_function_value_matters; | |
1771 | ||
1772 | /* Generate rtl for instructions for which shl_and_kind advised a particular | |
1773 | method of generating them, i.e. returned zero. */ | |
1774 | ||
1775 | int | |
1776 | gen_shl_and (dest, left_rtx, mask_rtx, source) | |
1777 | rtx dest, left_rtx, mask_rtx, source; | |
1778 | { | |
1779 | int attributes[3]; | |
1780 | unsigned HOST_WIDE_INT mask; | |
1781 | int kind = shl_and_kind (left_rtx, mask_rtx, attributes); | |
1782 | int right, total_shift; | |
318881c0 | 1783 | void (*shift_gen_fun) PARAMS ((int, rtx*)) = gen_shifty_hi_op; |
8d481241 JW |
1784 | |
1785 | right = attributes[0]; | |
1786 | total_shift = INTVAL (left_rtx) + right; | |
1787 | mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift; | |
1788 | switch (kind) | |
1789 | { | |
1790 | default: | |
1791 | return -1; | |
1792 | case 1: | |
1793 | { | |
1794 | int first = attributes[2]; | |
1795 | rtx operands[3]; | |
1796 | ||
1797 | if (first < 0) | |
1798 | { | |
7174c937 | 1799 | emit_insn ((mask << right) <= 0xff |
afad3d2c JW |
1800 | ? gen_zero_extendqisi2(dest, |
1801 | gen_lowpart (QImode, source)) | |
1802 | : gen_zero_extendhisi2(dest, | |
1803 | gen_lowpart (HImode, source))); | |
8d481241 JW |
1804 | source = dest; |
1805 | } | |
1806 | if (source != dest) | |
1807 | emit_insn (gen_movsi (dest, source)); | |
1808 | operands[0] = dest; | |
1809 | if (right) | |
1810 | { | |
1811 | operands[2] = GEN_INT (right); | |
1812 | gen_shifty_hi_op (LSHIFTRT, operands); | |
1813 | } | |
1814 | if (first > 0) | |
1815 | { | |
1816 | operands[2] = GEN_INT (first); | |
1817 | gen_shifty_hi_op (ASHIFT, operands); | |
1818 | total_shift -= first; | |
1819 | mask <<= first; | |
1820 | } | |
1821 | if (first >= 0) | |
7174c937 | 1822 | emit_insn (mask <= 0xff |
afad3d2c JW |
1823 | ? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest)) |
1824 | : gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest))); | |
8d481241 JW |
1825 | if (total_shift > 0) |
1826 | { | |
1827 | operands[2] = GEN_INT (total_shift); | |
1828 | gen_shifty_hi_op (ASHIFT, operands); | |
1829 | } | |
1830 | break; | |
1831 | } | |
1832 | case 4: | |
1833 | shift_gen_fun = gen_shifty_op; | |
8d481241 | 1834 | case 3: |
24c50999 JR |
1835 | /* If the topmost bit that matters is set, set the topmost bits |
1836 | that don't matter. This way, we might be able to get a shorter | |
1837 | signed constant. */ | |
318881c0 | 1838 | if (mask & ((HOST_WIDE_INT)1 << (31 - total_shift))) |
24c50999 | 1839 | mask |= (HOST_WIDE_INT)~0 << (31 - total_shift); |
61fb6bac | 1840 | case 2: |
8d481241 JW |
1841 | /* Don't expand fine-grained when combining, because that will |
1842 | make the pattern fail. */ | |
1843 | if (rtx_equal_function_value_matters | |
1844 | || reload_in_progress || reload_completed) | |
1845 | { | |
1846 | rtx operands[3]; | |
1847 | ||
61fb6bac R |
1848 | /* Cases 3 and 4 should be handled by this split |
1849 | only while combining */ | |
1850 | if (kind > 2) | |
1851 | abort (); | |
8d481241 JW |
1852 | if (right) |
1853 | { | |
1854 | emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right))); | |
1855 | source = dest; | |
1856 | } | |
1857 | emit_insn (gen_andsi3 (dest, source, GEN_INT (mask))); | |
afad3d2c JW |
1858 | if (total_shift) |
1859 | { | |
1860 | operands[0] = dest; | |
1861 | operands[1] = dest; | |
1862 | operands[2] = GEN_INT (total_shift); | |
1863 | shift_gen_fun (ASHIFT, operands); | |
1864 | } | |
8d481241 JW |
1865 | break; |
1866 | } | |
1867 | else | |
1868 | { | |
1869 | int neg = 0; | |
1870 | if (kind != 4 && total_shift < 16) | |
1871 | { | |
1872 | neg = -ext_shift_amounts[total_shift][1]; | |
1873 | if (neg > 0) | |
1874 | neg -= ext_shift_amounts[total_shift][2]; | |
1875 | else | |
1876 | neg = 0; | |
1877 | } | |
1878 | emit_insn (gen_and_shl_scratch (dest, source, | |
1879 | GEN_INT (right), | |
1880 | GEN_INT (mask), | |
1881 | GEN_INT (total_shift + neg), | |
1882 | GEN_INT (neg))); | |
1883 | emit_insn (gen_movsi (dest, dest)); | |
1884 | break; | |
1885 | } | |
1886 | } | |
1887 | return 0; | |
1888 | } | |
1889 | ||
1890 | /* Try to find a good way to implement the combiner pattern | |
1891 | [(set (match_operand:SI 0 "register_operand" "=r") | |
1892 | (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") | |
1893 | (match_operand:SI 2 "const_int_operand" "n") | |
1894 | (match_operand:SI 3 "const_int_operand" "n") | |
1895 | (const_int 0))) | |
4773afa4 | 1896 | (clobber (reg:SI T_REG))] |
8d481241 JW |
1897 | LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3. |
1898 | return 0 for simple left / right shift combination. | |
1899 | return 1 for left shift / 8 bit sign extend / left shift. | |
1900 | return 2 for left shift / 16 bit sign extend / left shift. | |
1901 | return 3 for left shift / 8 bit sign extend / shift / sign extend. | |
1902 | return 4 for left shift / 16 bit sign extend / shift / sign extend. | |
1903 | return 5 for left shift / 16 bit sign extend / right shift | |
1904 | return 6 for < 8 bit sign extend / left shift. | |
1905 | return 7 for < 8 bit sign extend / left shift / single right shift. | |
1906 | If COSTP is nonzero, assign the calculated cost to *COSTP. */ | |
1907 | ||
1908 | int | |
1909 | shl_sext_kind (left_rtx, size_rtx, costp) | |
1910 | rtx left_rtx, size_rtx; | |
1911 | int *costp; | |
1912 | { | |
1913 | int left, size, insize, ext; | |
1914 | int cost, best_cost; | |
1915 | int kind; | |
1916 | ||
1917 | left = INTVAL (left_rtx); | |
1918 | size = INTVAL (size_rtx); | |
1919 | insize = size - left; | |
1920 | if (insize <= 0) | |
1921 | abort (); | |
1922 | /* Default to left / right shift. */ | |
1923 | kind = 0; | |
1924 | best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size]; | |
1925 | if (size <= 16) | |
1926 | { | |
1927 | /* 16 bit shift / sign extend / 16 bit shift */ | |
1928 | cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size]; | |
afad3d2c JW |
1929 | /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden |
1930 | below, by alternative 3 or something even better. */ | |
8d481241 JW |
1931 | if (cost < best_cost) |
1932 | { | |
1933 | kind = 5; | |
1934 | best_cost = cost; | |
1935 | } | |
1936 | } | |
1937 | /* Try a plain sign extend between two shifts. */ | |
1938 | for (ext = 16; ext >= insize; ext -= 8) | |
1939 | { | |
1940 | if (ext <= size) | |
1941 | { | |
1942 | cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext]; | |
1943 | if (cost < best_cost) | |
1944 | { | |
11f9ed1a | 1945 | kind = ext / (unsigned) 8; |
8d481241 JW |
1946 | best_cost = cost; |
1947 | } | |
1948 | } | |
ae9d19c0 JR |
1949 | /* Check if we can do a sloppy shift with a final signed shift |
1950 | restoring the sign. */ | |
1951 | if (EXT_SHIFT_SIGNED (size - ext)) | |
1952 | cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1; | |
1953 | /* If not, maybe it's still cheaper to do the second shift sloppy, | |
1954 | and do a final sign extend? */ | |
1955 | else if (size <= 16) | |
1956 | cost = ext_shift_insns[ext - insize] + 1 | |
1957 | + ext_shift_insns[size > ext ? size - ext : ext - size] + 1; | |
1958 | else | |
1959 | continue; | |
1960 | if (cost < best_cost) | |
8d481241 | 1961 | { |
11f9ed1a | 1962 | kind = ext / (unsigned) 8 + 2; |
ae9d19c0 | 1963 | best_cost = cost; |
8d481241 JW |
1964 | } |
1965 | } | |
1966 | /* Check if we can sign extend in r0 */ | |
1967 | if (insize < 8) | |
1968 | { | |
1969 | cost = 3 + shift_insns[left]; | |
1970 | if (cost < best_cost) | |
1971 | { | |
1972 | kind = 6; | |
1973 | best_cost = cost; | |
1974 | } | |
1975 | /* Try the same with a final signed shift. */ | |
1976 | if (left < 31) | |
1977 | { | |
1978 | cost = 3 + ext_shift_insns[left + 1] + 1; | |
1979 | if (cost < best_cost) | |
1980 | { | |
1981 | kind = 7; | |
1982 | best_cost = cost; | |
1983 | } | |
1984 | } | |
1985 | } | |
1986 | if (TARGET_SH3) | |
1987 | { | |
1988 | /* Try to use a dynamic shift. */ | |
1245df60 | 1989 | cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST; |
8d481241 JW |
1990 | if (cost < best_cost) |
1991 | { | |
1992 | kind = 0; | |
1993 | best_cost = cost; | |
1994 | } | |
1995 | } | |
1996 | if (costp) | |
1997 | *costp = cost; | |
1998 | return kind; | |
1999 | } | |
2000 | ||
2001 | /* Function to be used in the length attribute of the instructions | |
2002 | implementing this pattern. */ | |
2003 | ||
2004 | int | |
2005 | shl_sext_length (insn) | |
2006 | rtx insn; | |
2007 | { | |
2008 | rtx set_src, left_rtx, size_rtx; | |
2009 | int cost; | |
2010 | ||
2011 | set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
2012 | left_rtx = XEXP (XEXP (set_src, 0), 1); | |
2013 | size_rtx = XEXP (set_src, 1); | |
2014 | shl_sext_kind (left_rtx, size_rtx, &cost); | |
2015 | return cost; | |
2016 | } | |
2017 | ||
2018 | /* Generate rtl for this pattern */ | |
2019 | ||
2020 | int | |
2021 | gen_shl_sext (dest, left_rtx, size_rtx, source) | |
2022 | rtx dest, left_rtx, size_rtx, source; | |
2023 | { | |
2024 | int kind; | |
d00d338c | 2025 | int left, size, insize, cost; |
8d481241 JW |
2026 | rtx operands[3]; |
2027 | ||
d00d338c | 2028 | kind = shl_sext_kind (left_rtx, size_rtx, &cost); |
8d481241 JW |
2029 | left = INTVAL (left_rtx); |
2030 | size = INTVAL (size_rtx); | |
2031 | insize = size - left; | |
2032 | switch (kind) | |
2033 | { | |
2034 | case 1: | |
2035 | case 2: | |
2036 | case 3: | |
2037 | case 4: | |
2038 | { | |
2039 | int ext = kind & 1 ? 8 : 16; | |
2040 | int shift2 = size - ext; | |
2041 | ||
2042 | /* Don't expand fine-grained when combining, because that will | |
2043 | make the pattern fail. */ | |
2044 | if (! rtx_equal_function_value_matters | |
2045 | && ! reload_in_progress && ! reload_completed) | |
2046 | { | |
2047 | emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx)); | |
2048 | emit_insn (gen_movsi (dest, source)); | |
2049 | break; | |
2050 | } | |
2051 | if (dest != source) | |
2052 | emit_insn (gen_movsi (dest, source)); | |
2053 | operands[0] = dest; | |
afad3d2c JW |
2054 | if (ext - insize) |
2055 | { | |
2056 | operands[2] = GEN_INT (ext - insize); | |
2057 | gen_shifty_hi_op (ASHIFT, operands); | |
2058 | } | |
8d481241 | 2059 | emit_insn (kind & 1 |
afad3d2c JW |
2060 | ? gen_extendqisi2(dest, gen_lowpart (QImode, dest)) |
2061 | : gen_extendhisi2(dest, gen_lowpart (HImode, dest))); | |
8d481241 JW |
2062 | if (kind <= 2) |
2063 | { | |
afad3d2c JW |
2064 | if (shift2) |
2065 | { | |
2066 | operands[2] = GEN_INT (shift2); | |
2067 | gen_shifty_op (ASHIFT, operands); | |
2068 | } | |
8d481241 JW |
2069 | } |
2070 | else | |
2071 | { | |
afad3d2c | 2072 | if (shift2 > 0) |
8d481241 | 2073 | { |
ae9d19c0 JR |
2074 | if (EXT_SHIFT_SIGNED (shift2)) |
2075 | { | |
2076 | operands[2] = GEN_INT (shift2 + 1); | |
2077 | gen_shifty_op (ASHIFT, operands); | |
2078 | operands[2] = GEN_INT (1); | |
2079 | gen_shifty_op (ASHIFTRT, operands); | |
2080 | break; | |
2081 | } | |
8d481241 JW |
2082 | operands[2] = GEN_INT (shift2); |
2083 | gen_shifty_hi_op (ASHIFT, operands); | |
2084 | } | |
afad3d2c | 2085 | else if (shift2) |
8d481241 JW |
2086 | { |
2087 | operands[2] = GEN_INT (-shift2); | |
2088 | gen_shifty_hi_op (LSHIFTRT, operands); | |
2089 | } | |
2090 | emit_insn (size <= 8 | |
afad3d2c JW |
2091 | ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest)) |
2092 | : gen_extendhisi2 (dest, gen_lowpart (HImode, dest))); | |
8d481241 JW |
2093 | } |
2094 | break; | |
2095 | } | |
2096 | case 5: | |
afad3d2c JW |
2097 | { |
2098 | int i = 16 - size; | |
913d8e13 R |
2099 | if (! rtx_equal_function_value_matters |
2100 | && ! reload_in_progress && ! reload_completed) | |
2101 | emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx)); | |
2102 | else | |
2103 | { | |
2104 | operands[0] = dest; | |
2105 | operands[2] = GEN_INT (16 - insize); | |
2106 | gen_shifty_hi_op (ASHIFT, operands); | |
2107 | emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest))); | |
2108 | } | |
afad3d2c JW |
2109 | /* Don't use gen_ashrsi3 because it generates new pseudos. */ |
2110 | while (--i >= 0) | |
2111 | gen_ashift (ASHIFTRT, 1, dest); | |
2112 | break; | |
2113 | } | |
8d481241 JW |
2114 | case 6: |
2115 | case 7: | |
2116 | /* Don't expand fine-grained when combining, because that will | |
2117 | make the pattern fail. */ | |
2118 | if (! rtx_equal_function_value_matters | |
2119 | && ! reload_in_progress && ! reload_completed) | |
2120 | { | |
2121 | emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx)); | |
2122 | emit_insn (gen_movsi (dest, source)); | |
2123 | break; | |
2124 | } | |
2125 | emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1))); | |
2126 | emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1)))); | |
2127 | emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1)))); | |
2128 | operands[0] = dest; | |
2129 | operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx; | |
2130 | gen_shifty_op (ASHIFT, operands); | |
2131 | if (kind == 7) | |
2132 | emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1))); | |
2133 | break; | |
2134 | default: | |
2135 | return -1; | |
2136 | } | |
2137 | return 0; | |
2138 | } | |
fa5322fa AO |
2139 | |
2140 | /* Prefix a symbol_ref name with "datalabel". */ | |
2141 | ||
2142 | rtx | |
2143 | gen_datalabel_ref (sym) | |
2144 | rtx sym; | |
2145 | { | |
2146 | if (GET_CODE (sym) == LABEL_REF) | |
2147 | return gen_rtx_CONST (GET_MODE (sym), | |
2148 | gen_rtx_UNSPEC (GET_MODE (sym), | |
2149 | gen_rtvec (1, sym), | |
2150 | UNSPEC_DATALABEL)); | |
2151 | ||
2152 | if (GET_CODE (sym) != SYMBOL_REF) | |
2153 | abort (); | |
2154 | ||
2155 | XSTR (sym, 0) = concat (SH_DATALABEL_ENCODING, XSTR (sym, 0), NULL); | |
2156 | ||
2157 | return sym; | |
2158 | } | |
2159 | ||
8aa2a305 JW |
2160 | \f |
2161 | /* The SH cannot load a large constant into a register, constants have to | |
2162 | come from a pc relative load. The reference of a pc relative load | |
2163 | instruction must be less than 1k infront of the instruction. This | |
2164 | means that we often have to dump a constant inside a function, and | |
2165 | generate code to branch around it. | |
bc45ade3 | 2166 | |
8aa2a305 JW |
2167 | It is important to minimize this, since the branches will slow things |
2168 | down and make things bigger. | |
2169 | ||
2170 | Worst case code looks like: | |
2171 | ||
2172 | mov.l L1,rn | |
2173 | bra L2 | |
2174 | nop | |
2175 | align | |
2176 | L1: .long value | |
2177 | L2: | |
2178 | .. | |
2179 | ||
2180 | mov.l L3,rn | |
2181 | bra L4 | |
2182 | nop | |
2183 | align | |
2184 | L3: .long value | |
2185 | L4: | |
2186 | .. | |
2187 | ||
2188 | We fix this by performing a scan before scheduling, which notices which | |
2189 | instructions need to have their operands fetched from the constant table | |
2190 | and builds the table. | |
2191 | ||
2192 | The algorithm is: | |
2193 | ||
2194 | scan, find an instruction which needs a pcrel move. Look forward, find the | |
2195 | last barrier which is within MAX_COUNT bytes of the requirement. | |
2196 | If there isn't one, make one. Process all the instructions between | |
2197 | the find and the barrier. | |
2198 | ||
2199 | In the above example, we can tell that L3 is within 1k of L1, so | |
2200 | the first move can be shrunk from the 3 insn+constant sequence into | |
2201 | just 1 insn, and the constant moved to L3 to make: | |
2202 | ||
2203 | mov.l L1,rn | |
2204 | .. | |
2205 | mov.l L3,rn | |
2206 | bra L4 | |
2207 | nop | |
2208 | align | |
2209 | L3:.long value | |
2210 | L4:.long value | |
2211 | ||
2212 | Then the second move becomes the target for the shortening process. */ | |
2213 | ||
2214 | typedef struct | |
2215 | { | |
2216 | rtx value; /* Value in table. */ | |
2217 | rtx label; /* Label of value. */ | |
b91455de | 2218 | rtx wend; /* End of window. */ |
8aa2a305 JW |
2219 | enum machine_mode mode; /* Mode of value. */ |
2220 | } pool_node; | |
2221 | ||
2222 | /* The maximum number of constants that can fit into one pool, since | |
2223 | the pc relative range is 0...1020 bytes and constants are at least 4 | |
2224 | bytes long. */ | |
2225 | ||
2226 | #define MAX_POOL_SIZE (1020/4) | |
2227 | static pool_node pool_vector[MAX_POOL_SIZE]; | |
2228 | static int pool_size; | |
b91455de KK |
2229 | static rtx pool_window_label; |
2230 | static int pool_window_last; | |
8aa2a305 JW |
2231 | |
2232 | /* ??? If we need a constant in HImode which is the truncated value of a | |
2233 | constant we need in SImode, we could combine the two entries thus saving | |
2234 | two bytes. Is this common enough to be worth the effort of implementing | |
2235 | it? */ | |
2236 | ||
2237 | /* ??? This stuff should be done at the same time that we shorten branches. | |
2238 | As it is now, we must assume that all branches are the maximum size, and | |
2239 | this causes us to almost always output constant pools sooner than | |
2240 | necessary. */ | |
2241 | ||
2242 | /* Add a constant to the pool and return its label. */ | |
2243 | ||
2244 | static rtx | |
225e4f43 | 2245 | add_constant (x, mode, last_value) |
8aa2a305 JW |
2246 | rtx x; |
2247 | enum machine_mode mode; | |
318881c0 | 2248 | rtx last_value; |
0d7e008e SC |
2249 | { |
2250 | int i; | |
b91455de | 2251 | rtx lab, new, ref, newref; |
8aa2a305 JW |
2252 | |
2253 | /* First see if we've already got it. */ | |
2254 | for (i = 0; i < pool_size; i++) | |
0d7e008e | 2255 | { |
8aa2a305 JW |
2256 | if (x->code == pool_vector[i].value->code |
2257 | && mode == pool_vector[i].mode) | |
0d7e008e | 2258 | { |
8aa2a305 JW |
2259 | if (x->code == CODE_LABEL) |
2260 | { | |
2261 | if (XINT (x, 3) != XINT (pool_vector[i].value, 3)) | |
2262 | continue; | |
2263 | } | |
2264 | if (rtx_equal_p (x, pool_vector[i].value)) | |
225e4f43 | 2265 | { |
b91455de | 2266 | lab = new = 0; |
225e4f43 R |
2267 | if (! last_value |
2268 | || ! i | |
2269 | || ! rtx_equal_p (last_value, pool_vector[i-1].value)) | |
2270 | { | |
b91455de KK |
2271 | new = gen_label_rtx (); |
2272 | LABEL_REFS (new) = pool_vector[i].label; | |
2273 | pool_vector[i].label = lab = new; | |
225e4f43 | 2274 | } |
b91455de KK |
2275 | if (lab && pool_window_label) |
2276 | { | |
2277 | newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label); | |
2278 | ref = pool_vector[pool_window_last].wend; | |
2279 | LABEL_NEXTREF (newref) = ref; | |
2280 | pool_vector[pool_window_last].wend = newref; | |
2281 | } | |
2282 | if (new) | |
2283 | pool_window_label = new; | |
2284 | pool_window_last = i; | |
225e4f43 R |
2285 | return lab; |
2286 | } | |
0d7e008e | 2287 | } |
0d7e008e | 2288 | } |
b9654711 | 2289 | |
8aa2a305 JW |
2290 | /* Need a new one. */ |
2291 | pool_vector[pool_size].value = x; | |
225e4f43 R |
2292 | if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value)) |
2293 | lab = 0; | |
2294 | else | |
2295 | lab = gen_label_rtx (); | |
8aa2a305 JW |
2296 | pool_vector[pool_size].mode = mode; |
2297 | pool_vector[pool_size].label = lab; | |
b91455de KK |
2298 | pool_vector[pool_size].wend = NULL_RTX; |
2299 | if (lab && pool_window_label) | |
2300 | { | |
2301 | newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label); | |
2302 | ref = pool_vector[pool_window_last].wend; | |
2303 | LABEL_NEXTREF (newref) = ref; | |
2304 | pool_vector[pool_window_last].wend = newref; | |
2305 | } | |
2306 | if (lab) | |
2307 | pool_window_label = lab; | |
2308 | pool_window_last = pool_size; | |
8aa2a305 JW |
2309 | pool_size++; |
2310 | return lab; | |
0d7e008e | 2311 | } |
16bea517 JW |
2312 | |
2313 | /* Output the literal table. */ | |
b9654711 | 2314 | |
b9654711 | 2315 | static void |
0d7e008e SC |
2316 | dump_table (scan) |
2317 | rtx scan; | |
b9654711 | 2318 | { |
0d7e008e | 2319 | int i; |
0d7e008e | 2320 | int need_align = 1; |
b91455de | 2321 | rtx lab, ref; |
fa5322fa | 2322 | int have_di = 0; |
b9654711 | 2323 | |
16bea517 | 2324 | /* Do two passes, first time dump out the HI sized constants. */ |
b9654711 | 2325 | |
0d7e008e | 2326 | for (i = 0; i < pool_size; i++) |
b9654711 | 2327 | { |
8aa2a305 JW |
2328 | pool_node *p = &pool_vector[i]; |
2329 | ||
0d7e008e SC |
2330 | if (p->mode == HImode) |
2331 | { | |
2332 | if (need_align) | |
2333 | { | |
2334 | scan = emit_insn_after (gen_align_2 (), scan); | |
2335 | need_align = 0; | |
2336 | } | |
b91455de KK |
2337 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) |
2338 | scan = emit_label_after (lab, scan); | |
2339 | scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx), | |
2340 | scan); | |
2341 | for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref)) | |
2342 | { | |
2343 | lab = XEXP (ref, 0); | |
2344 | scan = emit_insn_after (gen_consttable_window_end (lab), scan); | |
2345 | } | |
0d7e008e | 2346 | } |
fa5322fa AO |
2347 | else if (p->mode == DImode || p->mode == DFmode) |
2348 | have_di = 1; | |
b9654711 | 2349 | } |
8aa2a305 | 2350 | |
0d7e008e | 2351 | need_align = 1; |
b9654711 | 2352 | |
fa5322fa AO |
2353 | if (TARGET_SHCOMPACT && have_di) |
2354 | { | |
2355 | rtx align_insn = NULL_RTX; | |
2356 | ||
2357 | scan = emit_label_after (gen_label_rtx (), scan); | |
2358 | scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan); | |
2359 | need_align = 0; | |
2360 | ||
2361 | for (i = 0; i < pool_size; i++) | |
2362 | { | |
2363 | pool_node *p = &pool_vector[i]; | |
2364 | ||
2365 | switch (p->mode) | |
2366 | { | |
2367 | case HImode: | |
2368 | break; | |
2369 | case SImode: | |
2370 | case SFmode: | |
2371 | if (align_insn) | |
2372 | { | |
2373 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) | |
2374 | emit_label_before (lab, align_insn); | |
2375 | emit_insn_before (gen_consttable_4 (p->value, const0_rtx), | |
2376 | align_insn); | |
2377 | for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref)) | |
2378 | { | |
2379 | lab = XEXP (ref, 0); | |
2380 | emit_insn_before (gen_consttable_window_end (lab), | |
2381 | align_insn); | |
2382 | } | |
2383 | delete_insn (align_insn); | |
2384 | align_insn = NULL_RTX; | |
2385 | continue; | |
2386 | } | |
2387 | else | |
2388 | { | |
2389 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) | |
2390 | scan = emit_label_after (lab, scan); | |
2391 | scan = emit_insn_after (gen_consttable_4 (p->value, | |
2392 | const0_rtx), scan); | |
2393 | need_align = ! need_align; | |
2394 | } | |
2395 | break; | |
2396 | case DFmode: | |
2397 | case DImode: | |
2398 | if (need_align) | |
2399 | { | |
2400 | scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan); | |
2401 | align_insn = scan; | |
2402 | need_align = 0; | |
2403 | } | |
2404 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) | |
2405 | scan = emit_label_after (lab, scan); | |
2406 | scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx), | |
2407 | scan); | |
2408 | break; | |
2409 | default: | |
2410 | abort (); | |
2411 | break; | |
2412 | } | |
2413 | ||
2414 | if (p->mode != HImode) | |
2415 | { | |
2416 | for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref)) | |
2417 | { | |
2418 | lab = XEXP (ref, 0); | |
2419 | scan = emit_insn_after (gen_consttable_window_end (lab), | |
2420 | scan); | |
2421 | } | |
2422 | } | |
2423 | } | |
2424 | ||
2425 | pool_size = 0; | |
2426 | } | |
2427 | ||
0d7e008e | 2428 | for (i = 0; i < pool_size; i++) |
b9654711 | 2429 | { |
8aa2a305 | 2430 | pool_node *p = &pool_vector[i]; |
b9654711 | 2431 | |
0d7e008e | 2432 | switch (p->mode) |
b9654711 | 2433 | { |
0d7e008e SC |
2434 | case HImode: |
2435 | break; | |
2436 | case SImode: | |
e577c183 | 2437 | case SFmode: |
0d7e008e | 2438 | if (need_align) |
b9654711 | 2439 | { |
0d7e008e | 2440 | need_align = 0; |
d3ae8277 | 2441 | scan = emit_label_after (gen_label_rtx (), scan); |
0d7e008e | 2442 | scan = emit_insn_after (gen_align_4 (), scan); |
b9654711 | 2443 | } |
b91455de KK |
2444 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) |
2445 | scan = emit_label_after (lab, scan); | |
2446 | scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx), | |
2447 | scan); | |
0d7e008e | 2448 | break; |
e577c183 | 2449 | case DFmode: |
0d7e008e SC |
2450 | case DImode: |
2451 | if (need_align) | |
2452 | { | |
2453 | need_align = 0; | |
d3ae8277 | 2454 | scan = emit_label_after (gen_label_rtx (), scan); |
0d7e008e SC |
2455 | scan = emit_insn_after (gen_align_4 (), scan); |
2456 | } | |
b91455de KK |
2457 | for (lab = p->label; lab; lab = LABEL_REFS (lab)) |
2458 | scan = emit_label_after (lab, scan); | |
2459 | scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx), | |
2460 | scan); | |
0d7e008e SC |
2461 | break; |
2462 | default: | |
2463 | abort (); | |
2464 | break; | |
b9654711 | 2465 | } |
b91455de KK |
2466 | |
2467 | if (p->mode != HImode) | |
2468 | { | |
2469 | for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref)) | |
2470 | { | |
2471 | lab = XEXP (ref, 0); | |
2472 | scan = emit_insn_after (gen_consttable_window_end (lab), scan); | |
2473 | } | |
2474 | } | |
b9654711 | 2475 | } |
b9654711 | 2476 | |
0d7e008e SC |
2477 | scan = emit_insn_after (gen_consttable_end (), scan); |
2478 | scan = emit_barrier_after (scan); | |
2479 | pool_size = 0; | |
b91455de KK |
2480 | pool_window_label = NULL_RTX; |
2481 | pool_window_last = 0; | |
0d7e008e | 2482 | } |
b9654711 | 2483 | |
8aa2a305 JW |
2484 | /* Return non-zero if constant would be an ok source for a |
2485 | mov.w instead of a mov.l. */ | |
b9654711 | 2486 | |
16bea517 | 2487 | static int |
8aa2a305 | 2488 | hi_const (src) |
0d7e008e | 2489 | rtx src; |
0d7e008e | 2490 | { |
8aa2a305 JW |
2491 | return (GET_CODE (src) == CONST_INT |
2492 | && INTVAL (src) >= -32768 | |
2493 | && INTVAL (src) <= 32767); | |
b9654711 SC |
2494 | } |
2495 | ||
8aa2a305 JW |
2496 | /* Non-zero if the insn is a move instruction which needs to be fixed. */ |
2497 | ||
2498 | /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the | |
2499 | CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't | |
2500 | need to fix it if the input value is CONST_OK_FOR_I. */ | |
2501 | ||
2502 | static int | |
2503 | broken_move (insn) | |
2504 | rtx insn; | |
b9654711 | 2505 | { |
e577c183 JR |
2506 | if (GET_CODE (insn) == INSN) |
2507 | { | |
2508 | rtx pat = PATTERN (insn); | |
2509 | if (GET_CODE (pat) == PARALLEL) | |
2510 | pat = XVECEXP (pat, 0, 0); | |
2511 | if (GET_CODE (pat) == SET | |
2512 | /* We can load any 8 bit value if we don't care what the high | |
2513 | order bits end up as. */ | |
2514 | && GET_MODE (SET_DEST (pat)) != QImode | |
43c05634 AO |
2515 | && (CONSTANT_P (SET_SRC (pat)) |
2516 | /* Match mova_const. */ | |
2517 | || (GET_CODE (SET_SRC (pat)) == UNSPEC | |
2518 | && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA | |
2519 | && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST)) | |
1245df60 R |
2520 | && ! (TARGET_SH3E |
2521 | && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE | |
e577c183 JR |
2522 | && (fp_zero_operand (SET_SRC (pat)) |
2523 | || fp_one_operand (SET_SRC (pat))) | |
18778292 R |
2524 | /* ??? If this is a -m4 or -m4-single compilation, in general |
2525 | we don't know the current setting of fpscr, so disable fldi. | |
2526 | There is an exception if this was a register-register move | |
2527 | before reload - and hence it was ascertained that we have | |
2528 | single precision setting - and in a post-reload optimization | |
2529 | we changed this to do a constant load. In that case | |
2530 | we don't have an r0 clobber, hence we must use fldi. */ | |
2531 | && (! TARGET_SH4 || TARGET_FMOVD | |
2532 | || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0)) | |
2533 | == SCRATCH)) | |
e577c183 | 2534 | && GET_CODE (SET_DEST (pat)) == REG |
104ee20b | 2535 | && FP_REGISTER_P (REGNO (SET_DEST (pat)))) |
e577c183 JR |
2536 | && (GET_CODE (SET_SRC (pat)) != CONST_INT |
2537 | || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat))))) | |
2538 | return 1; | |
2539 | } | |
d3ae8277 | 2540 | |
8aa2a305 | 2541 | return 0; |
b9654711 | 2542 | } |
b9654711 | 2543 | |
1245df60 R |
2544 | static int |
2545 | mova_p (insn) | |
2546 | rtx insn; | |
2547 | { | |
2548 | return (GET_CODE (insn) == INSN | |
2549 | && GET_CODE (PATTERN (insn)) == SET | |
2550 | && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC | |
43c05634 AO |
2551 | && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA |
2552 | /* Don't match mova_const. */ | |
35ef2880 | 2553 | && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn)), 0, 0)) == LABEL_REF); |
1245df60 R |
2554 | } |
2555 | ||
8aa2a305 JW |
2556 | /* Find the last barrier from insn FROM which is close enough to hold the |
2557 | constant pool. If we can't find one, then create one near the end of | |
2558 | the range. */ | |
b9654711 | 2559 | |
8aa2a305 | 2560 | static rtx |
1245df60 R |
2561 | find_barrier (num_mova, mova, from) |
2562 | int num_mova; | |
2563 | rtx mova, from; | |
b9654711 | 2564 | { |
0d7e008e SC |
2565 | int count_si = 0; |
2566 | int count_hi = 0; | |
2567 | int found_hi = 0; | |
2568 | int found_si = 0; | |
fa5322fa | 2569 | int found_di = 0; |
33f7f353 JR |
2570 | int hi_align = 2; |
2571 | int si_align = 2; | |
1245df60 R |
2572 | int leading_mova = num_mova; |
2573 | rtx barrier_before_mova, found_barrier = 0, good_barrier = 0; | |
c17f53a8 JW |
2574 | int si_limit; |
2575 | int hi_limit; | |
8aa2a305 JW |
2576 | |
2577 | /* For HImode: range is 510, add 4 because pc counts from address of | |
2578 | second instruction after this one, subtract 2 for the jump instruction | |
3adbde60 JW |
2579 | that we may need to emit before the table, subtract 2 for the instruction |
2580 | that fills the jump delay slot (in very rare cases, reorg will take an | |
2581 | instruction from after the constant pool or will leave the delay slot | |
2582 | empty). This gives 510. | |
8aa2a305 JW |
2583 | For SImode: range is 1020, add 4 because pc counts from address of |
2584 | second instruction after this one, subtract 2 in case pc is 2 byte | |
2585 | aligned, subtract 2 for the jump instruction that we may need to emit | |
3adbde60 JW |
2586 | before the table, subtract 2 for the instruction that fills the jump |
2587 | delay slot. This gives 1018. */ | |
c17f53a8 | 2588 | |
1245df60 | 2589 | /* The branch will always be shortened now that the reference address for |
956d6950 | 2590 | forward branches is the successor address, thus we need no longer make |
1245df60 | 2591 | adjustments to the [sh]i_limit for -O0. */ |
c17f53a8 | 2592 | |
1245df60 R |
2593 | si_limit = 1018; |
2594 | hi_limit = 510; | |
e4fa6b06 | 2595 | |
c17f53a8 | 2596 | while (from && count_si < si_limit && count_hi < hi_limit) |
0d7e008e | 2597 | { |
33f7f353 JR |
2598 | int inc = get_attr_length (from); |
2599 | int new_align = 1; | |
1245df60 | 2600 | |
33f7f353 | 2601 | if (GET_CODE (from) == CODE_LABEL) |
77008a44 R |
2602 | { |
2603 | if (optimize) | |
2604 | new_align = 1 << label_to_alignment (from); | |
2605 | else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER) | |
2606 | new_align = 1 << barrier_align (from); | |
2607 | else | |
2608 | new_align = 1; | |
2609 | inc = 0; | |
2610 | } | |
8aa2a305 | 2611 | |
0d7e008e | 2612 | if (GET_CODE (from) == BARRIER) |
1245df60 | 2613 | { |
33f7f353 | 2614 | |
1245df60 | 2615 | found_barrier = from; |
33f7f353 | 2616 | |
956d6950 | 2617 | /* If we are at the end of the function, or in front of an alignment |
1245df60 R |
2618 | instruction, we need not insert an extra alignment. We prefer |
2619 | this kind of barrier. */ | |
33f7f353 | 2620 | if (barrier_align (from) > 2) |
1245df60 R |
2621 | good_barrier = from; |
2622 | } | |
8aa2a305 | 2623 | |
8aa2a305 | 2624 | if (broken_move (from)) |
0d7e008e | 2625 | { |
1245df60 R |
2626 | rtx pat, src, dst; |
2627 | enum machine_mode mode; | |
2628 | ||
2629 | pat = PATTERN (from); | |
2630 | if (GET_CODE (pat) == PARALLEL) | |
2631 | pat = XVECEXP (pat, 0, 0); | |
2632 | src = SET_SRC (pat); | |
2633 | dst = SET_DEST (pat); | |
2634 | mode = GET_MODE (dst); | |
c17f53a8 JW |
2635 | |
2636 | /* We must explicitly check the mode, because sometimes the | |
2637 | front end will generate code to load unsigned constants into | |
2638 | HImode targets without properly sign extending them. */ | |
225e4f43 R |
2639 | if (mode == HImode |
2640 | || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG)) | |
00e94d65 | 2641 | { |
1245df60 | 2642 | found_hi += 2; |
00e94d65 RK |
2643 | /* We put the short constants before the long constants, so |
2644 | we must count the length of short constants in the range | |
2645 | for the long constants. */ | |
2646 | /* ??? This isn't optimal, but is easy to do. */ | |
1245df60 | 2647 | si_limit -= 2; |
00e94d65 | 2648 | } |
0d7e008e | 2649 | else |
1245df60 | 2650 | { |
fa5322fa AO |
2651 | /* We dump DF/DI constants before SF/SI ones, because |
2652 | the limit is the same, but the alignment requirements | |
2653 | are higher. We may waste up to 4 additional bytes | |
2654 | for alignment, and the DF/DI constant may have | |
2655 | another SF/SI constant placed before it. */ | |
2656 | if (TARGET_SHCOMPACT | |
2657 | && ! found_di | |
2658 | && (mode == DFmode || mode == DImode)) | |
2659 | { | |
2660 | found_di = 1; | |
2661 | si_limit -= 8; | |
2662 | } | |
33f7f353 JR |
2663 | while (si_align > 2 && found_si + si_align - 2 > count_si) |
2664 | si_align >>= 1; | |
1245df60 R |
2665 | if (found_si > count_si) |
2666 | count_si = found_si; | |
2667 | found_si += GET_MODE_SIZE (mode); | |
2668 | if (num_mova) | |
2669 | si_limit -= GET_MODE_SIZE (mode); | |
2670 | } | |
42d5d0f1 BS |
2671 | |
2672 | /* See the code in machine_dependent_reorg, which has a similar if | |
1c32dd2b | 2673 | statement that generates a new mova insn in many cases. */ |
104ee20b | 2674 | if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst))) |
42d5d0f1 | 2675 | inc += 2; |
0d7e008e | 2676 | } |
5325c0fa | 2677 | |
33f7f353 | 2678 | if (mova_p (from)) |
1245df60 R |
2679 | { |
2680 | if (! num_mova++) | |
2681 | { | |
2682 | leading_mova = 0; | |
2683 | mova = from; | |
2684 | barrier_before_mova = good_barrier ? good_barrier : found_barrier; | |
2685 | } | |
2686 | if (found_si > count_si) | |
2687 | count_si = found_si; | |
2688 | } | |
5325c0fa JW |
2689 | else if (GET_CODE (from) == JUMP_INSN |
2690 | && (GET_CODE (PATTERN (from)) == ADDR_VEC | |
2691 | || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC)) | |
1245df60 R |
2692 | { |
2693 | if (num_mova) | |
2694 | num_mova--; | |
a0798779 | 2695 | if (barrier_align (next_real_insn (from)) == CACHE_LOG) |
1245df60 | 2696 | { |
38e01259 | 2697 | /* We have just passed the barrier in front of the |
a0798779 R |
2698 | ADDR_DIFF_VEC, which is stored in found_barrier. Since |
2699 | the ADDR_DIFF_VEC is accessed as data, just like our pool | |
2700 | constants, this is a good opportunity to accommodate what | |
2701 | we have gathered so far. | |
1245df60 R |
2702 | If we waited any longer, we could end up at a barrier in |
2703 | front of code, which gives worse cache usage for separated | |
2704 | instruction / data caches. */ | |
a0798779 | 2705 | good_barrier = found_barrier; |
1245df60 R |
2706 | break; |
2707 | } | |
a0798779 R |
2708 | else |
2709 | { | |
2710 | rtx body = PATTERN (from); | |
2711 | inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body)); | |
2712 | } | |
1245df60 | 2713 | } |
50ceefc2 R |
2714 | /* For the SH1, we generate alignments even after jumps-around-jumps. */ |
2715 | else if (GET_CODE (from) == JUMP_INSN | |
2716 | && ! TARGET_SH2 | |
2717 | && ! TARGET_SMALLCODE) | |
2718 | new_align = 4; | |
5325c0fa | 2719 | |
0d7e008e | 2720 | if (found_si) |
33f7f353 | 2721 | { |
50ceefc2 | 2722 | count_si += inc; |
33f7f353 JR |
2723 | if (new_align > si_align) |
2724 | { | |
318881c0 | 2725 | si_limit -= (count_si - 1) & (new_align - si_align); |
33f7f353 JR |
2726 | si_align = new_align; |
2727 | } | |
318881c0 | 2728 | count_si = (count_si + new_align - 1) & -new_align; |
33f7f353 | 2729 | } |
0d7e008e | 2730 | if (found_hi) |
33f7f353 | 2731 | { |
50ceefc2 | 2732 | count_hi += inc; |
33f7f353 JR |
2733 | if (new_align > hi_align) |
2734 | { | |
318881c0 | 2735 | hi_limit -= (count_hi - 1) & (new_align - hi_align); |
33f7f353 JR |
2736 | hi_align = new_align; |
2737 | } | |
318881c0 | 2738 | count_hi = (count_hi + new_align - 1) & -new_align; |
33f7f353 | 2739 | } |
0d7e008e SC |
2740 | from = NEXT_INSN (from); |
2741 | } | |
2742 | ||
1245df60 | 2743 | if (num_mova) |
eda44c78 R |
2744 | { |
2745 | if (leading_mova) | |
2746 | { | |
2747 | /* Try as we might, the leading mova is out of range. Change | |
2748 | it into a load (which will become a pcload) and retry. */ | |
2749 | SET_SRC (PATTERN (mova)) = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0); | |
2750 | INSN_CODE (mova) = -1; | |
2751 | return find_barrier (0, 0, mova); | |
2752 | } | |
2753 | else | |
2754 | { | |
2755 | /* Insert the constant pool table before the mova instruction, | |
2756 | to prevent the mova label reference from going out of range. */ | |
2757 | from = mova; | |
2758 | good_barrier = found_barrier = barrier_before_mova; | |
2759 | } | |
2760 | } | |
5325c0fa | 2761 | |
1245df60 R |
2762 | if (found_barrier) |
2763 | { | |
33f7f353 | 2764 | if (good_barrier && next_real_insn (found_barrier)) |
1245df60 | 2765 | found_barrier = good_barrier; |
1245df60 R |
2766 | } |
2767 | else | |
b9654711 | 2768 | { |
8aa2a305 JW |
2769 | /* We didn't find a barrier in time to dump our stuff, |
2770 | so we'll make one. */ | |
0d7e008e | 2771 | rtx label = gen_label_rtx (); |
8aa2a305 | 2772 | |
5dbcc9c0 RK |
2773 | /* If we exceeded the range, then we must back up over the last |
2774 | instruction we looked at. Otherwise, we just need to undo the | |
2775 | NEXT_INSN at the end of the loop. */ | |
c17f53a8 | 2776 | if (count_hi > hi_limit || count_si > si_limit) |
5dbcc9c0 RK |
2777 | from = PREV_INSN (PREV_INSN (from)); |
2778 | else | |
2779 | from = PREV_INSN (from); | |
2780 | ||
8aa2a305 JW |
2781 | /* Walk back to be just before any jump or label. |
2782 | Putting it before a label reduces the number of times the branch | |
2783 | around the constant pool table will be hit. Putting it before | |
2784 | a jump makes it more likely that the bra delay slot will be | |
2785 | filled. */ | |
2786 | while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE | |
8e87e161 | 2787 | || GET_CODE (from) == CODE_LABEL) |
8aa2a305 JW |
2788 | from = PREV_INSN (from); |
2789 | ||
0d7e008e SC |
2790 | from = emit_jump_insn_after (gen_jump (label), from); |
2791 | JUMP_LABEL (from) = label; | |
e081ed26 | 2792 | LABEL_NUSES (label) = 1; |
0d7e008e SC |
2793 | found_barrier = emit_barrier_after (from); |
2794 | emit_label_after (label, found_barrier); | |
b9654711 | 2795 | } |
b9654711 | 2796 | |
8aa2a305 | 2797 | return found_barrier; |
0d7e008e | 2798 | } |
b9654711 | 2799 | |
4787bce0 JW |
2800 | /* If the instruction INSN is implemented by a special function, and we can |
2801 | positively find the register that is used to call the sfunc, and this | |
2802 | register is not used anywhere else in this instruction - except as the | |
2803 | destination of a set, return this register; else, return 0. */ | |
1245df60 | 2804 | rtx |
4787bce0 JW |
2805 | sfunc_uses_reg (insn) |
2806 | rtx insn; | |
2807 | { | |
2808 | int i; | |
2809 | rtx pattern, part, reg_part, reg; | |
2810 | ||
2811 | if (GET_CODE (insn) != INSN) | |
2812 | return 0; | |
2813 | pattern = PATTERN (insn); | |
2814 | if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC) | |
2815 | return 0; | |
2816 | ||
2817 | for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--) | |
2818 | { | |
2819 | part = XVECEXP (pattern, 0, i); | |
1245df60 | 2820 | if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode) |
4787bce0 JW |
2821 | reg_part = part; |
2822 | } | |
2823 | if (! reg_part) | |
2824 | return 0; | |
2825 | reg = XEXP (reg_part, 0); | |
2826 | for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--) | |
2827 | { | |
2828 | part = XVECEXP (pattern, 0, i); | |
225e4f43 | 2829 | if (part == reg_part || GET_CODE (part) == CLOBBER) |
4787bce0 JW |
2830 | continue; |
2831 | if (reg_mentioned_p (reg, ((GET_CODE (part) == SET | |
2832 | && GET_CODE (SET_DEST (part)) == REG) | |
2833 | ? SET_SRC (part) : part))) | |
2834 | return 0; | |
2835 | } | |
2836 | return reg; | |
2837 | } | |
2838 | ||
933c3ba3 JW |
2839 | /* See if the only way in which INSN uses REG is by calling it, or by |
2840 | setting it while calling it. Set *SET to a SET rtx if the register | |
2841 | is set by INSN. */ | |
2842 | ||
2843 | static int | |
2844 | noncall_uses_reg (reg, insn, set) | |
2845 | rtx reg; | |
2846 | rtx insn; | |
2847 | rtx *set; | |
2848 | { | |
4787bce0 | 2849 | rtx pattern, reg2; |
933c3ba3 JW |
2850 | |
2851 | *set = NULL_RTX; | |
2852 | ||
4787bce0 JW |
2853 | reg2 = sfunc_uses_reg (insn); |
2854 | if (reg2 && REGNO (reg2) == REGNO (reg)) | |
2855 | { | |
2856 | pattern = single_set (insn); | |
2857 | if (pattern | |
2858 | && GET_CODE (SET_DEST (pattern)) == REG | |
2859 | && REGNO (reg) == REGNO (SET_DEST (pattern))) | |
2860 | *set = pattern; | |
2861 | return 0; | |
2862 | } | |
933c3ba3 JW |
2863 | if (GET_CODE (insn) != CALL_INSN) |
2864 | { | |
2865 | /* We don't use rtx_equal_p because we don't care if the mode is | |
2866 | different. */ | |
2867 | pattern = single_set (insn); | |
2868 | if (pattern | |
2869 | && GET_CODE (SET_DEST (pattern)) == REG | |
2870 | && REGNO (reg) == REGNO (SET_DEST (pattern))) | |
2871 | { | |
4787bce0 JW |
2872 | rtx par, part; |
2873 | int i; | |
2874 | ||
933c3ba3 | 2875 | *set = pattern; |
4787bce0 JW |
2876 | par = PATTERN (insn); |
2877 | if (GET_CODE (par) == PARALLEL) | |
2878 | for (i = XVECLEN (par, 0) - 1; i >= 0; i--) | |
2879 | { | |
2880 | part = XVECEXP (par, 0, i); | |
2881 | if (GET_CODE (part) != SET && reg_mentioned_p (reg, part)) | |
2882 | return 1; | |
2883 | } | |
2884 | return reg_mentioned_p (reg, SET_SRC (pattern)); | |
933c3ba3 JW |
2885 | } |
2886 | ||
2887 | return 1; | |
2888 | } | |
2889 | ||
2890 | pattern = PATTERN (insn); | |
2891 | ||
2892 | if (GET_CODE (pattern) == PARALLEL) | |
2893 | { | |
2894 | int i; | |
2895 | ||
2896 | for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--) | |
2897 | if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i))) | |
2898 | return 1; | |
2899 | pattern = XVECEXP (pattern, 0, 0); | |
2900 | } | |
2901 | ||
2902 | if (GET_CODE (pattern) == SET) | |
2903 | { | |
2904 | if (reg_mentioned_p (reg, SET_DEST (pattern))) | |
2905 | { | |
2906 | /* We don't use rtx_equal_p, because we don't care if the | |
2907 | mode is different. */ | |
2908 | if (GET_CODE (SET_DEST (pattern)) != REG | |
2909 | || REGNO (reg) != REGNO (SET_DEST (pattern))) | |
2910 | return 1; | |
2911 | ||
2912 | *set = pattern; | |
2913 | } | |
2914 | ||
2915 | pattern = SET_SRC (pattern); | |
2916 | } | |
2917 | ||
2918 | if (GET_CODE (pattern) != CALL | |
2919 | || GET_CODE (XEXP (pattern, 0)) != MEM | |
2920 | || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0))) | |
2921 | return 1; | |
2922 | ||
2923 | return 0; | |
2924 | } | |
2925 | ||
1245df60 R |
2926 | /* Given a X, a pattern of an insn or a part of it, return a mask of used |
2927 | general registers. Bits 0..15 mean that the respective registers | |
2928 | are used as inputs in the instruction. Bits 16..31 mean that the | |
2929 | registers 0..15, respectively, are used as outputs, or are clobbered. | |
2930 | IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */ | |
2931 | int | |
2932 | regs_used (x, is_dest) | |
2933 | rtx x; int is_dest; | |
2934 | { | |
2935 | enum rtx_code code; | |
6f7d635c | 2936 | const char *fmt; |
1245df60 R |
2937 | int i, used = 0; |
2938 | ||
2939 | if (! x) | |
2940 | return used; | |
2941 | code = GET_CODE (x); | |
2942 | switch (code) | |
2943 | { | |
2944 | case REG: | |
2945 | if (REGNO (x) < 16) | |
2946 | return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1) | |
2947 | << (REGNO (x) + is_dest)); | |
2948 | return 0; | |
2949 | case SUBREG: | |
2950 | { | |
2951 | rtx y = SUBREG_REG (x); | |
2952 | ||
2953 | if (GET_CODE (y) != REG) | |
2954 | break; | |
2955 | if (REGNO (y) < 16) | |
2956 | return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1) | |
ddef6bc7 JJ |
2957 | << (REGNO (y) + |
2958 | subreg_regno_offset (REGNO (y), | |
2959 | GET_MODE (y), | |
2960 | SUBREG_BYTE (x), | |
2961 | GET_MODE (x)) + is_dest)); | |
1245df60 R |
2962 | return 0; |
2963 | } | |
2964 | case SET: | |
2965 | return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16); | |
2966 | case RETURN: | |
2967 | /* If there was a return value, it must have been indicated with USE. */ | |
2968 | return 0x00ffff00; | |
2969 | case CLOBBER: | |
2970 | is_dest = 1; | |
2971 | break; | |
2972 | case MEM: | |
2973 | is_dest = 0; | |
2974 | break; | |
2975 | case CALL: | |
2976 | used |= 0x00ff00f0; | |
2977 | break; | |
318881c0 KG |
2978 | default: |
2979 | break; | |
1245df60 R |
2980 | } |
2981 | ||
2982 | fmt = GET_RTX_FORMAT (code); | |
2983 | ||
2984 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2985 | { | |
2986 | if (fmt[i] == 'E') | |
2987 | { | |
2988 | register int j; | |
2989 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2990 | used |= regs_used (XVECEXP (x, i, j), is_dest); | |
2991 | } | |
2992 | else if (fmt[i] == 'e') | |
2993 | used |= regs_used (XEXP (x, i), is_dest); | |
2994 | } | |
2995 | return used; | |
2996 | } | |
2997 | ||
2998 | /* Create an instruction that prevents redirection of a conditional branch | |
956d6950 | 2999 | to the destination of the JUMP with address ADDR. |
1245df60 R |
3000 | If the branch needs to be implemented as an indirect jump, try to find |
3001 | a scratch register for it. | |
3002 | If NEED_BLOCK is 0, don't do anything unless we need a scratch register. | |
3003 | If any preceding insn that doesn't fit into a delay slot is good enough, | |
3004 | pass 1. Pass 2 if a definite blocking insn is needed. | |
3005 | -1 is used internally to avoid deep recursion. | |
3006 | If a blocking instruction is made or recognized, return it. */ | |
3007 | ||
3008 | static rtx | |
3009 | gen_block_redirect (jump, addr, need_block) | |
3010 | rtx jump; | |
3011 | int addr, need_block; | |
3012 | { | |
3013 | int dead = 0; | |
3014 | rtx prev = prev_nonnote_insn (jump); | |
3015 | rtx dest; | |
3016 | ||
3017 | /* First, check if we already have an instruction that satisfies our need. */ | |
3018 | if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev)) | |
3019 | { | |
3020 | if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch) | |
3021 | return prev; | |
3022 | if (GET_CODE (PATTERN (prev)) == USE | |
3023 | || GET_CODE (PATTERN (prev)) == CLOBBER | |
3024 | || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES) | |
3025 | prev = jump; | |
3026 | else if ((need_block &= ~1) < 0) | |
3027 | return prev; | |
3028 | else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect) | |
3029 | need_block = 0; | |
3030 | } | |
3031 | /* We can't use JUMP_LABEL here because it might be undefined | |
3032 | when not optimizing. */ | |
3033 | dest = XEXP (SET_SRC (PATTERN (jump)), 0); | |
3034 | /* If the branch is out of range, try to find a scratch register for it. */ | |
3035 | if (optimize | |
11f9ed1a KG |
3036 | && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092 |
3037 | > 4092 + 4098)) | |
1245df60 R |
3038 | { |
3039 | rtx scan; | |
3040 | /* Don't look for the stack pointer as a scratch register, | |
956d6950 | 3041 | it would cause trouble if an interrupt occurred. */ |
1245df60 R |
3042 | unsigned try = 0x7fff, used; |
3043 | int jump_left = flag_expensive_optimizations + 1; | |
3044 | ||
3045 | /* It is likely that the most recent eligible instruction is wanted for | |
3046 | the delay slot. Therefore, find out which registers it uses, and | |
3047 | try to avoid using them. */ | |
3048 | ||
318881c0 | 3049 | for (scan = jump; (scan = PREV_INSN (scan)); ) |
1245df60 R |
3050 | { |
3051 | enum rtx_code code; | |
3052 | ||
3053 | if (INSN_DELETED_P (scan)) | |
3054 | continue; | |
3055 | code = GET_CODE (scan); | |
3056 | if (code == CODE_LABEL || code == JUMP_INSN) | |
3057 | break; | |
3058 | if (code == INSN | |
3059 | && GET_CODE (PATTERN (scan)) != USE | |
3060 | && GET_CODE (PATTERN (scan)) != CLOBBER | |
3061 | && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES) | |
3062 | { | |
3063 | try &= ~regs_used (PATTERN (scan), 0); | |
3064 | break; | |
3065 | } | |
3066 | } | |
eda44c78 R |
3067 | for (used = dead = 0, scan = JUMP_LABEL (jump); |
3068 | (scan = NEXT_INSN (scan)); ) | |
1245df60 R |
3069 | { |
3070 | enum rtx_code code; | |
3071 | ||
3072 | if (INSN_DELETED_P (scan)) | |
3073 | continue; | |
3074 | code = GET_CODE (scan); | |
3075 | if (GET_RTX_CLASS (code) == 'i') | |
3076 | { | |
3077 | used |= regs_used (PATTERN (scan), 0); | |
3078 | if (code == CALL_INSN) | |
3079 | used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0); | |
3080 | dead |= (used >> 16) & ~used; | |
3081 | if (dead & try) | |
3082 | { | |
3083 | dead &= try; | |
3084 | break; | |
3085 | } | |
3086 | if (code == JUMP_INSN) | |
eda44c78 R |
3087 | { |
3088 | if (jump_left-- && simplejump_p (scan)) | |
3089 | scan = JUMP_LABEL (scan); | |
3090 | else | |
3091 | break; | |
3092 | } | |
1245df60 R |
3093 | } |
3094 | } | |
3095 | /* Mask out the stack pointer again, in case it was | |
3096 | the only 'free' register we have found. */ | |
3097 | dead &= 0x7fff; | |
3098 | } | |
3099 | /* If the immediate destination is still in range, check for possible | |
3100 | threading with a jump beyond the delay slot insn. | |
3101 | Don't check if we are called recursively; the jump has been or will be | |
956d6950 | 3102 | checked in a different invocation then. */ |
1245df60 R |
3103 | |
3104 | else if (optimize && need_block >= 0) | |
3105 | { | |
3106 | rtx next = next_active_insn (next_active_insn (dest)); | |
3107 | if (next && GET_CODE (next) == JUMP_INSN | |
3108 | && GET_CODE (PATTERN (next)) == SET | |
3109 | && recog_memoized (next) == CODE_FOR_jump) | |
3110 | { | |
3111 | dest = JUMP_LABEL (next); | |
3112 | if (dest | |
11f9ed1a | 3113 | && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092 |
9d98a694 AO |
3114 | > 4092 + 4098)) |
3115 | gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1); | |
1245df60 R |
3116 | } |
3117 | } | |
3118 | ||
3119 | if (dead) | |
3120 | { | |
c5c76735 | 3121 | rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead)); |
1245df60 R |
3122 | |
3123 | /* It would be nice if we could convert the jump into an indirect | |
956d6950 | 3124 | jump / far branch right now, and thus exposing all constituent |
1245df60 R |
3125 | instructions to further optimization. However, reorg uses |
3126 | simplejump_p to determine if there is an unconditional jump where | |
3127 | it should try to schedule instructions from the target of the | |
3128 | branch; simplejump_p fails for indirect jumps even if they have | |
3129 | a JUMP_LABEL. */ | |
3130 | rtx insn = emit_insn_before (gen_indirect_jump_scratch | |
3131 | (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump)))) | |
3132 | , jump); | |
3133 | INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch; | |
3134 | return insn; | |
3135 | } | |
3136 | else if (need_block) | |
3137 | /* We can't use JUMP_LABEL here because it might be undefined | |
3138 | when not optimizing. */ | |
3139 | return emit_insn_before (gen_block_branch_redirect | |
3140 | (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0)))) | |
3141 | , jump); | |
3142 | return prev; | |
3143 | } | |
3144 | ||
3145 | #define CONDJUMP_MIN -252 | |
3146 | #define CONDJUMP_MAX 262 | |
3147 | struct far_branch | |
3148 | { | |
3149 | /* A label (to be placed) in front of the jump | |
3150 | that jumps to our ultimate destination. */ | |
3151 | rtx near_label; | |
3152 | /* Where we are going to insert it if we cannot move the jump any farther, | |
3153 | or the jump itself if we have picked up an existing jump. */ | |
3154 | rtx insert_place; | |
3155 | /* The ultimate destination. */ | |
3156 | rtx far_label; | |
3157 | struct far_branch *prev; | |
3158 | /* If the branch has already been created, its address; | |
3159 | else the address of its first prospective user. */ | |
3160 | int address; | |
3161 | }; | |
3162 | ||
eda44c78 | 3163 | static void gen_far_branch PARAMS ((struct far_branch *)); |
1245df60 | 3164 | enum mdep_reorg_phase_e mdep_reorg_phase; |
c5b9ef02 | 3165 | static void |
1245df60 R |
3166 | gen_far_branch (bp) |
3167 | struct far_branch *bp; | |
3168 | { | |
3169 | rtx insn = bp->insert_place; | |
3170 | rtx jump; | |
3171 | rtx label = gen_label_rtx (); | |
3172 | ||
3173 | emit_label_after (label, insn); | |
3174 | if (bp->far_label) | |
3175 | { | |
3176 | jump = emit_jump_insn_after (gen_jump (bp->far_label), insn); | |
3177 | LABEL_NUSES (bp->far_label)++; | |
3178 | } | |
3179 | else | |
3180 | jump = emit_jump_insn_after (gen_return (), insn); | |
225e4f43 R |
3181 | /* Emit a barrier so that reorg knows that any following instructions |
3182 | are not reachable via a fall-through path. | |
3183 | But don't do this when not optimizing, since we wouldn't supress the | |
3184 | alignment for the barrier then, and could end up with out-of-range | |
3185 | pc-relative loads. */ | |
3186 | if (optimize) | |
3187 | emit_barrier_after (jump); | |
1245df60 R |
3188 | emit_label_after (bp->near_label, insn); |
3189 | JUMP_LABEL (jump) = bp->far_label; | |
8ceaac3c | 3190 | if (! invert_jump (insn, label, 1)) |
1245df60 R |
3191 | abort (); |
3192 | /* Prevent reorg from undoing our splits. */ | |
3193 | gen_block_redirect (jump, bp->address += 2, 2); | |
3194 | } | |
3195 | ||
1245df60 R |
3196 | /* Fix up ADDR_DIFF_VECs. */ |
3197 | void | |
3198 | fixup_addr_diff_vecs (first) | |
3199 | rtx first; | |
3200 | { | |
3201 | rtx insn; | |
33f7f353 | 3202 | |
1245df60 R |
3203 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
3204 | { | |
eb3881bf | 3205 | rtx vec_lab, pat, prev, prevpat, x, braf_label; |
1245df60 R |
3206 | |
3207 | if (GET_CODE (insn) != JUMP_INSN | |
3208 | || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) | |
3209 | continue; | |
3210 | pat = PATTERN (insn); | |
33f7f353 | 3211 | vec_lab = XEXP (XEXP (pat, 0), 0); |
1245df60 | 3212 | |
33f7f353 JR |
3213 | /* Search the matching casesi_jump_2. */ |
3214 | for (prev = vec_lab; ; prev = PREV_INSN (prev)) | |
1245df60 | 3215 | { |
33f7f353 JR |
3216 | if (GET_CODE (prev) != JUMP_INSN) |
3217 | continue; | |
3218 | prevpat = PATTERN (prev); | |
3219 | if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2) | |
3220 | continue; | |
3221 | x = XVECEXP (prevpat, 0, 1); | |
3222 | if (GET_CODE (x) != USE) | |
3223 | continue; | |
3224 | x = XEXP (x, 0); | |
3225 | if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab) | |
3226 | break; | |
1245df60 | 3227 | } |
eb3881bf R |
3228 | |
3229 | /* Emit the reference label of the braf where it belongs, right after | |
3230 | the casesi_jump_2 (i.e. braf). */ | |
3231 | braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0); | |
3232 | emit_label_after (braf_label, prev); | |
3233 | ||
33f7f353 JR |
3234 | /* Fix up the ADDR_DIF_VEC to be relative |
3235 | to the reference address of the braf. */ | |
eb3881bf | 3236 | XEXP (XEXP (pat, 0), 0) = braf_label; |
1245df60 | 3237 | } |
1245df60 R |
3238 | } |
3239 | ||
33f7f353 JR |
3240 | /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following |
3241 | a barrier. Return the base 2 logarithm of the desired alignment. */ | |
1245df60 | 3242 | int |
33f7f353 JR |
3243 | barrier_align (barrier_or_label) |
3244 | rtx barrier_or_label; | |
1245df60 | 3245 | { |
33f7f353 | 3246 | rtx next = next_real_insn (barrier_or_label), pat, prev; |
b1b41fe4 | 3247 | int slot, credit, jump_to_next; |
33f7f353 JR |
3248 | |
3249 | if (! next) | |
1245df60 | 3250 | return 0; |
1245df60 | 3251 | |
33f7f353 | 3252 | pat = PATTERN (next); |
1245df60 | 3253 | |
33f7f353 JR |
3254 | if (GET_CODE (pat) == ADDR_DIFF_VEC) |
3255 | return 2; | |
1245df60 | 3256 | |
4773afa4 | 3257 | if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN) |
33f7f353 JR |
3258 | /* This is a barrier in front of a constant table. */ |
3259 | return 0; | |
3260 | ||
3261 | prev = prev_real_insn (barrier_or_label); | |
3262 | if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC) | |
1245df60 | 3263 | { |
33f7f353 JR |
3264 | pat = PATTERN (prev); |
3265 | /* If this is a very small table, we want to keep the alignment after | |
3266 | the table to the minimum for proper code alignment. */ | |
3267 | return ((TARGET_SMALLCODE | |
3268 | || (XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat)) | |
c5b9ef02 | 3269 | <= (unsigned)1 << (CACHE_LOG - 2))) |
fa5322fa | 3270 | ? 1 << TARGET_SHMEDIA : CACHE_LOG); |
1245df60 | 3271 | } |
33f7f353 JR |
3272 | |
3273 | if (TARGET_SMALLCODE) | |
3274 | return 0; | |
3275 | ||
4d070fd3 | 3276 | if (! TARGET_SH2 || ! optimize) |
33f7f353 JR |
3277 | return CACHE_LOG; |
3278 | ||
225e4f43 R |
3279 | /* When fixing up pcloads, a constant table might be inserted just before |
3280 | the basic block that ends with the barrier. Thus, we can't trust the | |
3281 | instruction lengths before that. */ | |
3282 | if (mdep_reorg_phase > SH_FIXUP_PCLOAD) | |
1245df60 | 3283 | { |
225e4f43 R |
3284 | /* Check if there is an immediately preceding branch to the insn beyond |
3285 | the barrier. We must weight the cost of discarding useful information | |
3286 | from the current cache line when executing this branch and there is | |
3287 | an alignment, against that of fetching unneeded insn in front of the | |
3288 | branch target when there is no alignment. */ | |
3289 | ||
b1b41fe4 CP |
3290 | /* There are two delay_slot cases to consider. One is the simple case |
3291 | where the preceding branch is to the insn beyond the barrier (simple | |
3292 | delay slot filling), and the other is where the preceding branch has | |
3293 | a delay slot that is a duplicate of the insn after the barrier | |
3294 | (fill_eager_delay_slots) and the branch is to the insn after the insn | |
3295 | after the barrier. */ | |
3296 | ||
225e4f43 R |
3297 | /* PREV is presumed to be the JUMP_INSN for the barrier under |
3298 | investigation. Skip to the insn before it. */ | |
3299 | prev = prev_real_insn (prev); | |
3300 | ||
c5b9ef02 | 3301 | for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2; |
225e4f43 R |
3302 | credit >= 0 && prev && GET_CODE (prev) == INSN; |
3303 | prev = prev_real_insn (prev)) | |
3304 | { | |
b1b41fe4 | 3305 | jump_to_next = 0; |
225e4f43 R |
3306 | if (GET_CODE (PATTERN (prev)) == USE |
3307 | || GET_CODE (PATTERN (prev)) == CLOBBER) | |
3308 | continue; | |
3309 | if (GET_CODE (PATTERN (prev)) == SEQUENCE) | |
b1b41fe4 CP |
3310 | { |
3311 | prev = XVECEXP (PATTERN (prev), 0, 1); | |
3312 | if (INSN_UID (prev) == INSN_UID (next)) | |
3313 | { | |
3314 | /* Delay slot was filled with insn at jump target. */ | |
3315 | jump_to_next = 1; | |
3316 | continue; | |
3317 | } | |
3318 | } | |
3319 | ||
225e4f43 R |
3320 | if (slot && |
3321 | get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES) | |
3322 | slot = 0; | |
3323 | credit -= get_attr_length (prev); | |
3324 | } | |
3325 | if (prev | |
3326 | && GET_CODE (prev) == JUMP_INSN | |
2b9d17c7 AH |
3327 | && JUMP_LABEL (prev)) |
3328 | { | |
3329 | rtx x; | |
300c5453 | 3330 | if (jump_to_next |
2b9d17c7 | 3331 | || next_real_insn (JUMP_LABEL (prev)) == next |
1594c6bc AO |
3332 | /* If relax_delay_slots() decides NEXT was redundant |
3333 | with some previous instruction, it will have | |
3334 | redirected PREV's jump to the following insn. */ | |
5d291213 | 3335 | || JUMP_LABEL (prev) == next_nonnote_insn (next) |
300c5453 AO |
3336 | /* There is no upper bound on redundant instructions |
3337 | that might have been skipped, but we must not put an | |
2b9d17c7 AH |
3338 | alignment where none had been before. */ |
3339 | || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))), | |
3340 | (INSN_P (x) | |
3341 | && (INSN_CODE (x) == CODE_FOR_block_branch_redirect | |
3342 | || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch)))) | |
3343 | { | |
3344 | rtx pat = PATTERN (prev); | |
3345 | if (GET_CODE (pat) == PARALLEL) | |
300c5453 | 3346 | pat = XVECEXP (pat, 0, 0); |
2b9d17c7 AH |
3347 | if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0)) |
3348 | return 0; | |
3349 | } | |
300c5453 | 3350 | } |
33f7f353 | 3351 | } |
2b9d17c7 | 3352 | |
33f7f353 | 3353 | return CACHE_LOG; |
1245df60 R |
3354 | } |
3355 | ||
2148624a R |
3356 | /* If we are inside a phony loop, almost any kind of label can turn up as the |
3357 | first one in the loop. Aligning a braf label causes incorrect switch | |
3358 | destination addresses; we can detect braf labels because they are | |
3359 | followed by a BARRIER. | |
3360 | Applying loop alignment to small constant or switch tables is a waste | |
3361 | of space, so we suppress this too. */ | |
3362 | int | |
3363 | sh_loop_align (label) | |
3364 | rtx label; | |
3365 | { | |
3366 | rtx next = label; | |
3367 | ||
3368 | do | |
3369 | next = next_nonnote_insn (next); | |
3370 | while (next && GET_CODE (next) == CODE_LABEL); | |
3371 | ||
3372 | if (! next | |
2c3c49de | 3373 | || ! INSN_P (next) |
2148624a R |
3374 | || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC |
3375 | || recog_memoized (next) == CODE_FOR_consttable_2) | |
3376 | return 0; | |
fa5322fa AO |
3377 | |
3378 | if (TARGET_SH5) | |
3379 | return 3; | |
3380 | ||
2148624a R |
3381 | return 2; |
3382 | } | |
3383 | ||
8aa2a305 | 3384 | /* Exported to toplev.c. |
b9654711 | 3385 | |
933c3ba3 JW |
3386 | Do a final pass over the function, just before delayed branch |
3387 | scheduling. */ | |
b9654711 | 3388 | |
0d7e008e SC |
3389 | void |
3390 | machine_dependent_reorg (first) | |
3391 | rtx first; | |
3392 | { | |
1245df60 R |
3393 | rtx insn, mova; |
3394 | int num_mova; | |
c5c76735 JL |
3395 | rtx r0_rtx = gen_rtx_REG (Pmode, 0); |
3396 | rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx); | |
8aa2a305 | 3397 | |
cb51ecd2 AO |
3398 | /* We must split call insns before introducing `mova's. If we're |
3399 | optimizing, they'll have already been split. Otherwise, make | |
3400 | sure we don't split them too late. */ | |
3401 | if (! optimize) | |
6f862f2f | 3402 | split_all_insns_noflow (); |
cb51ecd2 | 3403 | |
fa5322fa AO |
3404 | if (TARGET_SHMEDIA) |
3405 | return; | |
3406 | ||
933c3ba3 JW |
3407 | /* If relaxing, generate pseudo-ops to associate function calls with |
3408 | the symbols they call. It does no harm to not generate these | |
3409 | pseudo-ops. However, when we can generate them, it enables to | |
3410 | linker to potentially relax the jsr to a bsr, and eliminate the | |
3411 | register load and, possibly, the constant pool entry. */ | |
3412 | ||
1245df60 | 3413 | mdep_reorg_phase = SH_INSERT_USES_LABELS; |
933c3ba3 JW |
3414 | if (TARGET_RELAX) |
3415 | { | |
3416 | /* Remove all REG_LABEL notes. We want to use them for our own | |
3417 | purposes. This works because none of the remaining passes | |
3418 | need to look at them. | |
3419 | ||
3420 | ??? But it may break in the future. We should use a machine | |
3421 | dependent REG_NOTE, or some other approach entirely. */ | |
3422 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
3423 | { | |
2c3c49de | 3424 | if (INSN_P (insn)) |
933c3ba3 JW |
3425 | { |
3426 | rtx note; | |
3427 | ||
3428 | while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0) | |
3429 | remove_note (insn, note); | |
3430 | } | |
3431 | } | |
3432 | ||
3433 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
3434 | { | |
3435 | rtx pattern, reg, link, set, scan, dies, label; | |
3436 | int rescan = 0, foundinsn = 0; | |
3437 | ||
4787bce0 JW |
3438 | if (GET_CODE (insn) == CALL_INSN) |
3439 | { | |
3440 | pattern = PATTERN (insn); | |
933c3ba3 | 3441 | |
4787bce0 JW |
3442 | if (GET_CODE (pattern) == PARALLEL) |
3443 | pattern = XVECEXP (pattern, 0, 0); | |
3444 | if (GET_CODE (pattern) == SET) | |
3445 | pattern = SET_SRC (pattern); | |
933c3ba3 | 3446 | |
4787bce0 JW |
3447 | if (GET_CODE (pattern) != CALL |
3448 | || GET_CODE (XEXP (pattern, 0)) != MEM) | |
3449 | continue; | |
933c3ba3 | 3450 | |
4787bce0 JW |
3451 | reg = XEXP (XEXP (pattern, 0), 0); |
3452 | } | |
3453 | else | |
3454 | { | |
3455 | reg = sfunc_uses_reg (insn); | |
3456 | if (! reg) | |
3457 | continue; | |
3458 | } | |
933c3ba3 | 3459 | |
933c3ba3 JW |
3460 | if (GET_CODE (reg) != REG) |
3461 | continue; | |
3462 | ||
3463 | /* This is a function call via REG. If the only uses of REG | |
3464 | between the time that it is set and the time that it dies | |
3465 | are in function calls, then we can associate all the | |
3466 | function calls with the setting of REG. */ | |
3467 | ||
3468 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
3469 | { | |
1075deda ILT |
3470 | if (REG_NOTE_KIND (link) != 0) |
3471 | continue; | |
933c3ba3 JW |
3472 | set = single_set (XEXP (link, 0)); |
3473 | if (set && rtx_equal_p (reg, SET_DEST (set))) | |
3474 | { | |
3475 | link = XEXP (link, 0); | |
3476 | break; | |
3477 | } | |
3478 | } | |
3479 | ||
3480 | if (! link) | |
3481 | { | |
3482 | /* ??? Sometimes global register allocation will have | |
3483 | deleted the insn pointed to by LOG_LINKS. Try | |
3484 | scanning backward to find where the register is set. */ | |
3485 | for (scan = PREV_INSN (insn); | |
3486 | scan && GET_CODE (scan) != CODE_LABEL; | |
3487 | scan = PREV_INSN (scan)) | |
3488 | { | |
2c3c49de | 3489 | if (! INSN_P (scan)) |
933c3ba3 JW |
3490 | continue; |
3491 | ||
3492 | if (! reg_mentioned_p (reg, scan)) | |
3493 | continue; | |
3494 | ||
3495 | if (noncall_uses_reg (reg, scan, &set)) | |
3496 | break; | |
3497 | ||
3498 | if (set) | |
3499 | { | |
3500 | link = scan; | |
3501 | break; | |
3502 | } | |
3503 | } | |
3504 | } | |
3505 | ||
3506 | if (! link) | |
3507 | continue; | |
3508 | ||
3509 | /* The register is set at LINK. */ | |
3510 | ||
3511 | /* We can only optimize the function call if the register is | |
3512 | being set to a symbol. In theory, we could sometimes | |
3513 | optimize calls to a constant location, but the assembler | |
3514 | and linker do not support that at present. */ | |
3515 | if (GET_CODE (SET_SRC (set)) != SYMBOL_REF | |
3516 | && GET_CODE (SET_SRC (set)) != LABEL_REF) | |
3517 | continue; | |
3518 | ||
3519 | /* Scan forward from LINK to the place where REG dies, and | |
3520 | make sure that the only insns which use REG are | |
3521 | themselves function calls. */ | |
3522 | ||
c1e8e6bd JW |
3523 | /* ??? This doesn't work for call targets that were allocated |
3524 | by reload, since there may not be a REG_DEAD note for the | |
3525 | register. */ | |
3526 | ||
933c3ba3 JW |
3527 | dies = NULL_RTX; |
3528 | for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan)) | |
3529 | { | |
3530 | rtx scanset; | |
3531 | ||
c1e8e6bd JW |
3532 | /* Don't try to trace forward past a CODE_LABEL if we haven't |
3533 | seen INSN yet. Ordinarily, we will only find the setting insn | |
3534 | in LOG_LINKS if it is in the same basic block. However, | |
3535 | cross-jumping can insert code labels in between the load and | |
3536 | the call, and can result in situations where a single call | |
3537 | insn may have two targets depending on where we came from. */ | |
3538 | ||
3539 | if (GET_CODE (scan) == CODE_LABEL && ! foundinsn) | |
3540 | break; | |
3541 | ||
2c3c49de | 3542 | if (! INSN_P (scan)) |
933c3ba3 JW |
3543 | continue; |
3544 | ||
3545 | /* Don't try to trace forward past a JUMP. To optimize | |
3546 | safely, we would have to check that all the | |
c1e8e6bd | 3547 | instructions at the jump destination did not use REG. */ |
933c3ba3 | 3548 | |
c1e8e6bd | 3549 | if (GET_CODE (scan) == JUMP_INSN) |
933c3ba3 JW |
3550 | break; |
3551 | ||
3552 | if (! reg_mentioned_p (reg, scan)) | |
3553 | continue; | |
3554 | ||
3555 | if (noncall_uses_reg (reg, scan, &scanset)) | |
3556 | break; | |
3557 | ||
3558 | if (scan == insn) | |
3559 | foundinsn = 1; | |
3560 | ||
4787bce0 JW |
3561 | if (scan != insn |
3562 | && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan))) | |
933c3ba3 JW |
3563 | { |
3564 | /* There is a function call to this register other | |
3565 | than the one we are checking. If we optimize | |
3566 | this call, we need to rescan again below. */ | |
3567 | rescan = 1; | |
3568 | } | |
3569 | ||
3570 | /* ??? We shouldn't have to worry about SCANSET here. | |
3571 | We should just be able to check for a REG_DEAD note | |
3572 | on a function call. However, the REG_DEAD notes are | |
3573 | apparently not dependable around libcalls; c-torture | |
3574 | execute/920501-2 is a test case. If SCANSET is set, | |
3575 | then this insn sets the register, so it must have | |
3576 | died earlier. Unfortunately, this will only handle | |
3577 | the cases in which the register is, in fact, set in a | |
3578 | later insn. */ | |
3579 | ||
3580 | /* ??? We shouldn't have to use FOUNDINSN here. | |
3581 | However, the LOG_LINKS fields are apparently not | |
3582 | entirely reliable around libcalls; | |
3583 | newlib/libm/math/e_pow.c is a test case. Sometimes | |
3584 | an insn will appear in LOG_LINKS even though it is | |
6f317ef3 | 3585 | not the most recent insn which sets the register. */ |
933c3ba3 JW |
3586 | |
3587 | if (foundinsn | |
3588 | && (scanset | |
3589 | || find_reg_note (scan, REG_DEAD, reg))) | |
3590 | { | |
3591 | dies = scan; | |
3592 | break; | |
3593 | } | |
3594 | } | |
3595 | ||
3596 | if (! dies) | |
3597 | { | |
3598 | /* Either there was a branch, or some insn used REG | |
3599 | other than as a function call address. */ | |
3600 | continue; | |
3601 | } | |
3602 | ||
3603 | /* Create a code label, and put it in a REG_LABEL note on | |
3604 | the insn which sets the register, and on each call insn | |
3605 | which uses the register. In final_prescan_insn we look | |
3606 | for the REG_LABEL notes, and output the appropriate label | |
3607 | or pseudo-op. */ | |
3608 | ||
3609 | label = gen_label_rtx (); | |
6b8c9327 | 3610 | REG_NOTES (link) = gen_rtx_INSN_LIST (REG_LABEL, label, |
c5c76735 | 3611 | REG_NOTES (link)); |
6b8c9327 | 3612 | REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, label, |
c5c76735 | 3613 | REG_NOTES (insn)); |
933c3ba3 JW |
3614 | if (rescan) |
3615 | { | |
3616 | scan = link; | |
3617 | do | |
3618 | { | |
4787bce0 JW |
3619 | rtx reg2; |
3620 | ||
933c3ba3 JW |
3621 | scan = NEXT_INSN (scan); |
3622 | if (scan != insn | |
4787bce0 JW |
3623 | && ((GET_CODE (scan) == CALL_INSN |
3624 | && reg_mentioned_p (reg, scan)) | |
3625 | || ((reg2 = sfunc_uses_reg (scan)) | |
3626 | && REGNO (reg2) == REGNO (reg)))) | |
c5c76735 | 3627 | REG_NOTES (scan) |
6b8c9327 | 3628 | = gen_rtx_INSN_LIST (REG_LABEL, label, REG_NOTES (scan)); |
933c3ba3 JW |
3629 | } |
3630 | while (scan != dies); | |
3631 | } | |
3632 | } | |
3633 | } | |
3634 | ||
33f7f353 JR |
3635 | if (TARGET_SH2) |
3636 | fixup_addr_diff_vecs (first); | |
1245df60 R |
3637 | |
3638 | if (optimize) | |
3639 | { | |
1245df60 R |
3640 | mdep_reorg_phase = SH_SHORTEN_BRANCHES0; |
3641 | shorten_branches (first); | |
3642 | } | |
933c3ba3 JW |
3643 | /* Scan the function looking for move instructions which have to be |
3644 | changed to pc-relative loads and insert the literal tables. */ | |
3645 | ||
1245df60 R |
3646 | mdep_reorg_phase = SH_FIXUP_PCLOAD; |
3647 | for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn)) | |
0d7e008e | 3648 | { |
1245df60 R |
3649 | if (mova_p (insn)) |
3650 | { | |
3651 | if (! num_mova++) | |
3652 | mova = insn; | |
3653 | } | |
3654 | else if (GET_CODE (insn) == JUMP_INSN | |
3655 | && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
3656 | && num_mova) | |
3657 | { | |
3658 | rtx scan; | |
3659 | int total; | |
3660 | ||
3661 | num_mova--; | |
3662 | ||
3663 | /* Some code might have been inserted between the mova and | |
3664 | its ADDR_DIFF_VEC. Check if the mova is still in range. */ | |
3665 | for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan)) | |
33f7f353 | 3666 | total += get_attr_length (scan); |
1245df60 R |
3667 | |
3668 | /* range of mova is 1020, add 4 because pc counts from address of | |
3669 | second instruction after this one, subtract 2 in case pc is 2 | |
3670 | byte aligned. Possible alignment needed for the ADDR_DIFF_VEC | |
956d6950 | 3671 | cancels out with alignment effects of the mova itself. */ |
1245df60 R |
3672 | if (total > 1022) |
3673 | { | |
3674 | /* Change the mova into a load, and restart scanning | |
3675 | there. broken_move will then return true for mova. */ | |
3676 | SET_SRC (PATTERN (mova)) | |
3677 | = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0); | |
3678 | INSN_CODE (mova) = -1; | |
3679 | insn = mova; | |
3680 | } | |
3681 | } | |
0d7e008e SC |
3682 | if (broken_move (insn)) |
3683 | { | |
0d7e008e | 3684 | rtx scan; |
8aa2a305 JW |
3685 | /* Scan ahead looking for a barrier to stick the constant table |
3686 | behind. */ | |
1245df60 R |
3687 | rtx barrier = find_barrier (num_mova, mova, insn); |
3688 | rtx last_float_move, last_float = 0, *last_float_addr; | |
fa5322fa | 3689 | int may_need_align = 1; |
b9654711 | 3690 | |
1245df60 R |
3691 | if (num_mova && ! mova_p (mova)) |
3692 | { | |
3693 | /* find_barrier had to change the first mova into a | |
3694 | pcload; thus, we have to start with this new pcload. */ | |
3695 | insn = mova; | |
3696 | num_mova = 0; | |
3697 | } | |
16bea517 | 3698 | /* Now find all the moves between the points and modify them. */ |
0d7e008e SC |
3699 | for (scan = insn; scan != barrier; scan = NEXT_INSN (scan)) |
3700 | { | |
1245df60 R |
3701 | if (GET_CODE (scan) == CODE_LABEL) |
3702 | last_float = 0; | |
0d7e008e SC |
3703 | if (broken_move (scan)) |
3704 | { | |
e577c183 JR |
3705 | rtx *patp = &PATTERN (scan), pat = *patp; |
3706 | rtx src, dst; | |
0d7e008e | 3707 | rtx lab; |
0d7e008e | 3708 | rtx newsrc; |
e577c183 JR |
3709 | enum machine_mode mode; |
3710 | ||
3711 | if (GET_CODE (pat) == PARALLEL) | |
3712 | patp = &XVECEXP (pat, 0, 0), pat = *patp; | |
3713 | src = SET_SRC (pat); | |
3714 | dst = SET_DEST (pat); | |
3715 | mode = GET_MODE (dst); | |
0d7e008e | 3716 | |
225e4f43 R |
3717 | if (mode == SImode && hi_const (src) |
3718 | && REGNO (dst) != FPUL_REG) | |
0d7e008e | 3719 | { |
23ed92ca | 3720 | int offset = 0; |
8aa2a305 | 3721 | |
0d7e008e | 3722 | mode = HImode; |
d3ae8277 | 3723 | while (GET_CODE (dst) == SUBREG) |
23ed92ca | 3724 | { |
ddef6bc7 JJ |
3725 | offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)), |
3726 | GET_MODE (SUBREG_REG (dst)), | |
3727 | SUBREG_BYTE (dst), | |
3728 | GET_MODE (dst)); | |
23ed92ca JW |
3729 | dst = SUBREG_REG (dst); |
3730 | } | |
c5c76735 | 3731 | dst = gen_rtx_REG (HImode, REGNO (dst) + offset); |
0d7e008e | 3732 | } |
8aa2a305 | 3733 | |
104ee20b | 3734 | if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst))) |
1245df60 | 3735 | { |
b8794099 R |
3736 | /* This must be an insn that clobbers r0. */ |
3737 | rtx clobber = XVECEXP (PATTERN (scan), 0, | |
3738 | XVECLEN (PATTERN (scan), 0) - 1); | |
3739 | ||
3740 | if (GET_CODE (clobber) != CLOBBER | |
3741 | || ! rtx_equal_p (XEXP (clobber, 0), r0_rtx)) | |
3742 | abort (); | |
3743 | ||
1245df60 R |
3744 | if (last_float |
3745 | && reg_set_between_p (r0_rtx, last_float_move, scan)) | |
3746 | last_float = 0; | |
fa5322fa AO |
3747 | if (TARGET_SHCOMPACT) |
3748 | { | |
3749 | /* The first SFmode constant after a DFmode | |
3750 | constant may be pulled before a sequence | |
3751 | of DFmode constants, so the second SFmode | |
3752 | needs a label, just in case. */ | |
3753 | if (GET_MODE_SIZE (mode) == 4) | |
3754 | { | |
3755 | if (last_float && may_need_align) | |
3756 | last_float = 0; | |
3757 | may_need_align = 0; | |
3758 | } | |
3759 | if (last_float | |
3760 | && (GET_MODE_SIZE (GET_MODE (last_float)) | |
3761 | != GET_MODE_SIZE (mode))) | |
3762 | { | |
3763 | last_float = 0; | |
3764 | if (GET_MODE_SIZE (mode) == 4) | |
3765 | may_need_align = 1; | |
3766 | } | |
3767 | } | |
1245df60 R |
3768 | lab = add_constant (src, mode, last_float); |
3769 | if (lab) | |
3770 | emit_insn_before (gen_mova (lab), scan); | |
3771 | else | |
b8794099 R |
3772 | { |
3773 | /* There will be a REG_UNUSED note for r0 on | |
3774 | LAST_FLOAT_MOVE; we have to change it to REG_INC, | |
3775 | lest reorg:mark_target_live_regs will not | |
3776 | consider r0 to be used, and we end up with delay | |
475f26dd | 3777 | slot insn in front of SCAN that clobbers r0. */ |
b8794099 R |
3778 | rtx note |
3779 | = find_regno_note (last_float_move, REG_UNUSED, 0); | |
3780 | ||
ab1672a3 JW |
3781 | /* If we are not optimizing, then there may not be |
3782 | a note. */ | |
3783 | if (note) | |
3784 | PUT_MODE (note, REG_INC); | |
b8794099 R |
3785 | |
3786 | *last_float_addr = r0_inc_rtx; | |
3787 | } | |
1245df60 R |
3788 | last_float_move = scan; |
3789 | last_float = src; | |
3790 | newsrc = gen_rtx (MEM, mode, | |
318881c0 | 3791 | (((TARGET_SH4 && ! TARGET_FMOVD) |
225e4f43 | 3792 | || REGNO (dst) == FPUL_REG) |
1245df60 R |
3793 | ? r0_inc_rtx |
3794 | : r0_rtx)); | |
3795 | last_float_addr = &XEXP (newsrc, 0); | |
b8794099 R |
3796 | |
3797 | /* Remove the clobber of r0. */ | |
3798 | XEXP (clobber, 0) = gen_rtx_SCRATCH (Pmode); | |
1245df60 | 3799 | } |
1a66cd67 | 3800 | /* This is a mova needing a label. Create it. */ |
43c05634 AO |
3801 | else if (GET_CODE (src) == UNSPEC |
3802 | && XINT (src, 1) == UNSPEC_MOVA | |
3803 | && GET_CODE (XVECEXP (src, 0, 0)) == CONST) | |
1a66cd67 | 3804 | { |
43c05634 | 3805 | lab = add_constant (XVECEXP (src, 0, 0), mode, 0); |
1a66cd67 AO |
3806 | newsrc = gen_rtx_LABEL_REF (VOIDmode, lab); |
3807 | newsrc = gen_rtx_UNSPEC (VOIDmode, | |
4773afa4 AO |
3808 | gen_rtvec (1, newsrc), |
3809 | UNSPEC_MOVA); | |
1a66cd67 | 3810 | } |
1245df60 R |
3811 | else |
3812 | { | |
3813 | lab = add_constant (src, mode, 0); | |
c5c76735 JL |
3814 | newsrc = gen_rtx_MEM (mode, |
3815 | gen_rtx_LABEL_REF (VOIDmode, lab)); | |
1245df60 | 3816 | } |
8aa2a305 | 3817 | RTX_UNCHANGING_P (newsrc) = 1; |
c5c76735 | 3818 | *patp = gen_rtx_SET (VOIDmode, dst, newsrc); |
e577c183 | 3819 | INSN_CODE (scan) = -1; |
0d7e008e SC |
3820 | } |
3821 | } | |
3822 | dump_table (barrier); | |
1245df60 | 3823 | insn = barrier; |
0d7e008e SC |
3824 | } |
3825 | } | |
1245df60 R |
3826 | |
3827 | mdep_reorg_phase = SH_SHORTEN_BRANCHES1; | |
9d98a694 | 3828 | INSN_ADDRESSES_FREE (); |
1245df60 R |
3829 | split_branches (first); |
3830 | ||
3831 | /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it | |
3832 | also has an effect on the register that holds the addres of the sfunc. | |
3833 | Insert an extra dummy insn in front of each sfunc that pretends to | |
3834 | use this register. */ | |
3835 | if (flag_delayed_branch) | |
3836 | { | |
3837 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
3838 | { | |
3839 | rtx reg = sfunc_uses_reg (insn); | |
3840 | ||
3841 | if (! reg) | |
3842 | continue; | |
3843 | emit_insn_before (gen_use_sfunc_addr (reg), insn); | |
3844 | } | |
3845 | } | |
225e4f43 R |
3846 | #if 0 |
3847 | /* fpscr is not actually a user variable, but we pretend it is for the | |
3848 | sake of the previous optimization passes, since we want it handled like | |
9f09b1f2 | 3849 | one. However, we don't have any debugging information for it, so turn |
225e4f43 R |
3850 | it into a non-user variable now. */ |
3851 | if (TARGET_SH4) | |
3852 | REG_USERVAR_P (get_fpscr_rtx ()) = 0; | |
3853 | #endif | |
1245df60 R |
3854 | mdep_reorg_phase = SH_AFTER_MDEP_REORG; |
3855 | } | |
3856 | ||
3857 | int | |
3858 | get_dest_uid (label, max_uid) | |
3859 | rtx label; | |
3860 | int max_uid; | |
3861 | { | |
3862 | rtx dest = next_real_insn (label); | |
3863 | int dest_uid; | |
3864 | if (! dest) | |
3865 | /* This can happen for an undefined label. */ | |
3866 | return 0; | |
3867 | dest_uid = INSN_UID (dest); | |
3868 | /* If this is a newly created branch redirection blocking instruction, | |
3869 | we cannot index the branch_uid or insn_addresses arrays with its | |
3870 | uid. But then, we won't need to, because the actual destination is | |
3871 | the following branch. */ | |
3872 | while (dest_uid >= max_uid) | |
3873 | { | |
3874 | dest = NEXT_INSN (dest); | |
3875 | dest_uid = INSN_UID (dest); | |
3876 | } | |
3877 | if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN) | |
3878 | return 0; | |
3879 | return dest_uid; | |
3880 | } | |
3881 | ||
3882 | /* Split condbranches that are out of range. Also add clobbers for | |
3883 | scratch registers that are needed in far jumps. | |
3884 | We do this before delay slot scheduling, so that it can take our | |
3885 | newly created instructions into account. It also allows us to | |
3886 | find branches with common targets more easily. */ | |
3887 | ||
3888 | static void | |
3889 | split_branches (first) | |
3890 | rtx first; | |
3891 | { | |
3892 | rtx insn; | |
3893 | struct far_branch **uid_branch, *far_branch_list = 0; | |
3894 | int max_uid = get_max_uid (); | |
3895 | ||
3896 | /* Find out which branches are out of range. */ | |
1245df60 R |
3897 | shorten_branches (first); |
3898 | ||
3899 | uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch); | |
2e09e75a | 3900 | memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch); |
1245df60 R |
3901 | |
3902 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 3903 | if (! INSN_P (insn)) |
1245df60 R |
3904 | continue; |
3905 | else if (INSN_DELETED_P (insn)) | |
3906 | { | |
3907 | /* Shorten_branches would split this instruction again, | |
3908 | so transform it into a note. */ | |
3909 | PUT_CODE (insn, NOTE); | |
3910 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
3911 | NOTE_SOURCE_FILE (insn) = 0; | |
3912 | } | |
3913 | else if (GET_CODE (insn) == JUMP_INSN | |
3914 | /* Don't mess with ADDR_DIFF_VEC */ | |
3915 | && (GET_CODE (PATTERN (insn)) == SET | |
3916 | || GET_CODE (PATTERN (insn)) == RETURN)) | |
3917 | { | |
3918 | enum attr_type type = get_attr_type (insn); | |
3919 | if (type == TYPE_CBRANCH) | |
3920 | { | |
3921 | rtx next, beyond; | |
3922 | ||
3923 | if (get_attr_length (insn) > 4) | |
3924 | { | |
3925 | rtx src = SET_SRC (PATTERN (insn)); | |
1245df60 | 3926 | rtx olabel = XEXP (XEXP (src, 1), 0); |
9d98a694 | 3927 | int addr = INSN_ADDRESSES (INSN_UID (insn)); |
1245df60 R |
3928 | rtx label = 0; |
3929 | int dest_uid = get_dest_uid (olabel, max_uid); | |
3930 | struct far_branch *bp = uid_branch[dest_uid]; | |
3931 | ||
3932 | /* redirect_jump needs a valid JUMP_LABEL, and it might delete | |
25938114 | 3933 | the label if the LABEL_NUSES count drops to zero. There is |
1245df60 R |
3934 | always a jump_optimize pass that sets these values, but it |
3935 | proceeds to delete unreferenced code, and then if not | |
956d6950 | 3936 | optimizing, to un-delete the deleted instructions, thus |
1245df60 R |
3937 | leaving labels with too low uses counts. */ |
3938 | if (! optimize) | |
3939 | { | |
3940 | JUMP_LABEL (insn) = olabel; | |
3941 | LABEL_NUSES (olabel)++; | |
3942 | } | |
3943 | if (! bp) | |
3944 | { | |
3945 | bp = (struct far_branch *) alloca (sizeof *bp); | |
3946 | uid_branch[dest_uid] = bp; | |
3947 | bp->prev = far_branch_list; | |
3948 | far_branch_list = bp; | |
3949 | bp->far_label | |
3950 | = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0); | |
3951 | LABEL_NUSES (bp->far_label)++; | |
3952 | } | |
3953 | else | |
3954 | { | |
3955 | label = bp->near_label; | |
3956 | if (! label && bp->address - addr >= CONDJUMP_MIN) | |
3957 | { | |
3958 | rtx block = bp->insert_place; | |
3959 | ||
3960 | if (GET_CODE (PATTERN (block)) == RETURN) | |
3961 | block = PREV_INSN (block); | |
3962 | else | |
3963 | block = gen_block_redirect (block, | |
3964 | bp->address, 2); | |
3965 | label = emit_label_after (gen_label_rtx (), | |
3966 | PREV_INSN (block)); | |
3967 | bp->near_label = label; | |
3968 | } | |
3969 | else if (label && ! NEXT_INSN (label)) | |
eda44c78 R |
3970 | { |
3971 | if (addr + 2 - bp->address <= CONDJUMP_MAX) | |
3972 | bp->insert_place = insn; | |
3973 | else | |
3974 | gen_far_branch (bp); | |
3975 | } | |
1245df60 R |
3976 | } |
3977 | if (! label | |
318881c0 | 3978 | || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN)) |
1245df60 R |
3979 | { |
3980 | bp->near_label = label = gen_label_rtx (); | |
3981 | bp->insert_place = insn; | |
3982 | bp->address = addr; | |
3983 | } | |
8ceaac3c | 3984 | if (! redirect_jump (insn, label, 1)) |
1245df60 R |
3985 | abort (); |
3986 | } | |
3987 | else | |
3988 | { | |
3989 | /* get_attr_length (insn) == 2 */ | |
3990 | /* Check if we have a pattern where reorg wants to redirect | |
3991 | the branch to a label from an unconditional branch that | |
3992 | is too far away. */ | |
3993 | /* We can't use JUMP_LABEL here because it might be undefined | |
3994 | when not optimizing. */ | |
33f7f353 | 3995 | /* A syntax error might cause beyond to be NULL_RTX. */ |
1245df60 R |
3996 | beyond |
3997 | = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), | |
3998 | 0)); | |
3999 | ||
33f7f353 JR |
4000 | if (beyond |
4001 | && (GET_CODE (beyond) == JUMP_INSN | |
b94544e4 AO |
4002 | || ((beyond = next_active_insn (beyond)) |
4003 | && GET_CODE (beyond) == JUMP_INSN)) | |
1245df60 R |
4004 | && GET_CODE (PATTERN (beyond)) == SET |
4005 | && recog_memoized (beyond) == CODE_FOR_jump | |
9d98a694 AO |
4006 | && ((INSN_ADDRESSES |
4007 | (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0))) | |
11f9ed1a | 4008 | - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252) |
1245df60 R |
4009 | > 252 + 258 + 2)) |
4010 | gen_block_redirect (beyond, | |
9d98a694 | 4011 | INSN_ADDRESSES (INSN_UID (beyond)), 1); |
1245df60 R |
4012 | } |
4013 | ||
4014 | next = next_active_insn (insn); | |
4015 | ||
4016 | if ((GET_CODE (next) == JUMP_INSN | |
4017 | || GET_CODE (next = next_active_insn (next)) == JUMP_INSN) | |
4018 | && GET_CODE (PATTERN (next)) == SET | |
4019 | && recog_memoized (next) == CODE_FOR_jump | |
9d98a694 AO |
4020 | && ((INSN_ADDRESSES |
4021 | (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0))) | |
11f9ed1a | 4022 | - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252) |
1245df60 | 4023 | > 252 + 258 + 2)) |
9d98a694 | 4024 | gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1); |
1245df60 R |
4025 | } |
4026 | else if (type == TYPE_JUMP || type == TYPE_RETURN) | |
4027 | { | |
9d98a694 | 4028 | int addr = INSN_ADDRESSES (INSN_UID (insn)); |
1245df60 R |
4029 | rtx far_label = 0; |
4030 | int dest_uid = 0; | |
4031 | struct far_branch *bp; | |
4032 | ||
4033 | if (type == TYPE_JUMP) | |
4034 | { | |
4035 | far_label = XEXP (SET_SRC (PATTERN (insn)), 0); | |
4036 | dest_uid = get_dest_uid (far_label, max_uid); | |
4037 | if (! dest_uid) | |
4038 | { | |
4039 | /* Parse errors can lead to labels outside | |
4040 | the insn stream. */ | |
4041 | if (! NEXT_INSN (far_label)) | |
4042 | continue; | |
4043 | ||
4044 | if (! optimize) | |
4045 | { | |
4046 | JUMP_LABEL (insn) = far_label; | |
4047 | LABEL_NUSES (far_label)++; | |
4048 | } | |
8ceaac3c | 4049 | redirect_jump (insn, NULL_RTX, 1); |
1245df60 R |
4050 | far_label = 0; |
4051 | } | |
4052 | } | |
4053 | bp = uid_branch[dest_uid]; | |
4054 | if (! bp) | |
4055 | { | |
4056 | bp = (struct far_branch *) alloca (sizeof *bp); | |
4057 | uid_branch[dest_uid] = bp; | |
4058 | bp->prev = far_branch_list; | |
4059 | far_branch_list = bp; | |
4060 | bp->near_label = 0; | |
4061 | bp->far_label = far_label; | |
4062 | if (far_label) | |
4063 | LABEL_NUSES (far_label)++; | |
4064 | } | |
4065 | else if (bp->near_label && ! NEXT_INSN (bp->near_label)) | |
4066 | if (addr - bp->address <= CONDJUMP_MAX) | |
4067 | emit_label_after (bp->near_label, PREV_INSN (insn)); | |
4068 | else | |
4069 | { | |
4070 | gen_far_branch (bp); | |
4071 | bp->near_label = 0; | |
4072 | } | |
4073 | else | |
4074 | bp->near_label = 0; | |
4075 | bp->address = addr; | |
4076 | bp->insert_place = insn; | |
4077 | if (! far_label) | |
4078 | emit_insn_before (gen_block_branch_redirect (const0_rtx), insn); | |
4079 | else | |
4080 | gen_block_redirect (insn, addr, bp->near_label ? 2 : 0); | |
4081 | } | |
4082 | } | |
4083 | /* Generate all pending far branches, | |
4084 | and free our references to the far labels. */ | |
4085 | while (far_branch_list) | |
4086 | { | |
4087 | if (far_branch_list->near_label | |
4088 | && ! NEXT_INSN (far_branch_list->near_label)) | |
4089 | gen_far_branch (far_branch_list); | |
4090 | if (optimize | |
4091 | && far_branch_list->far_label | |
4092 | && ! --LABEL_NUSES (far_branch_list->far_label)) | |
4093 | delete_insn (far_branch_list->far_label); | |
4094 | far_branch_list = far_branch_list->prev; | |
4095 | } | |
a0798779 R |
4096 | |
4097 | /* Instruction length information is no longer valid due to the new | |
4098 | instructions that have been generated. */ | |
4099 | init_insn_lengths (); | |
b9654711 SC |
4100 | } |
4101 | ||
8aa2a305 | 4102 | /* Dump out instruction addresses, which is useful for debugging the |
933c3ba3 JW |
4103 | constant pool table stuff. |
4104 | ||
4105 | If relaxing, output the label and pseudo-ops used to link together | |
4106 | calls and the instruction which set the registers. */ | |
8aa2a305 JW |
4107 | |
4108 | /* ??? This is unnecessary, and probably should be deleted. This makes | |
4109 | the insn_addresses declaration above unnecessary. */ | |
4110 | ||
4111 | /* ??? The addresses printed by this routine for insns are nonsense for | |
4112 | insns which are inside of a sequence where none of the inner insns have | |
4113 | variable length. This is because the second pass of shorten_branches | |
4114 | does not bother to update them. */ | |
0d7e008e | 4115 | |
8e87e161 | 4116 | void |
8aa2a305 JW |
4117 | final_prescan_insn (insn, opvec, noperands) |
4118 | rtx insn; | |
318881c0 KG |
4119 | rtx *opvec ATTRIBUTE_UNUSED; |
4120 | int noperands ATTRIBUTE_UNUSED; | |
b9654711 | 4121 | { |
8aa2a305 | 4122 | if (TARGET_DUMPISIZE) |
9d98a694 | 4123 | fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn))); |
933c3ba3 JW |
4124 | |
4125 | if (TARGET_RELAX) | |
4126 | { | |
4127 | rtx note; | |
4128 | ||
4129 | note = find_reg_note (insn, REG_LABEL, NULL_RTX); | |
4130 | if (note) | |
4131 | { | |
4132 | rtx pattern; | |
4133 | ||
4134 | pattern = PATTERN (insn); | |
4135 | if (GET_CODE (pattern) == PARALLEL) | |
4136 | pattern = XVECEXP (pattern, 0, 0); | |
4137 | if (GET_CODE (pattern) == CALL | |
4138 | || (GET_CODE (pattern) == SET | |
4787bce0 JW |
4139 | && (GET_CODE (SET_SRC (pattern)) == CALL |
4140 | || get_attr_type (insn) == TYPE_SFUNC))) | |
4d7b7169 R |
4141 | asm_fprintf (asm_out_file, "\t.uses %LL%d\n", |
4142 | CODE_LABEL_NUMBER (XEXP (note, 0))); | |
933c3ba3 JW |
4143 | else if (GET_CODE (pattern) == SET) |
4144 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", | |
4145 | CODE_LABEL_NUMBER (XEXP (note, 0))); | |
4146 | else | |
4147 | abort (); | |
4148 | } | |
4149 | } | |
0d7e008e | 4150 | } |
b9654711 | 4151 | |
8aa2a305 | 4152 | /* Dump out any constants accumulated in the final pass. These will |
38e01259 | 4153 | only be labels. */ |
b9654711 | 4154 | |
318881c0 | 4155 | const char * |
8aa2a305 | 4156 | output_jump_label_table () |
0d7e008e | 4157 | { |
8aa2a305 JW |
4158 | int i; |
4159 | ||
4160 | if (pool_size) | |
4161 | { | |
4162 | fprintf (asm_out_file, "\t.align 2\n"); | |
4163 | for (i = 0; i < pool_size; i++) | |
4164 | { | |
4165 | pool_node *p = &pool_vector[i]; | |
4166 | ||
4167 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", | |
4168 | CODE_LABEL_NUMBER (p->label)); | |
4169 | output_asm_insn (".long %O0", &p->value); | |
4170 | } | |
4171 | pool_size = 0; | |
4172 | } | |
b9654711 | 4173 | |
8aa2a305 JW |
4174 | return ""; |
4175 | } | |
4176 | \f | |
4177 | /* A full frame looks like: | |
16bea517 JW |
4178 | |
4179 | arg-5 | |
4180 | arg-4 | |
4181 | [ if current_function_anonymous_args | |
4182 | arg-3 | |
4183 | arg-2 | |
4184 | arg-1 | |
4185 | arg-0 ] | |
4186 | saved-fp | |
4187 | saved-r10 | |
4188 | saved-r11 | |
4189 | saved-r12 | |
4190 | saved-pr | |
4191 | local-n | |
4192 | .. | |
4193 | local-1 | |
4194 | local-0 <- fp points here. */ | |
8e87e161 | 4195 | |
8aa2a305 JW |
4196 | /* Number of bytes pushed for anonymous args, used to pass information |
4197 | between expand_prologue and expand_epilogue. */ | |
4198 | ||
4199 | static int extra_push; | |
4200 | ||
885c9a39 JR |
4201 | /* Adjust the stack by SIZE bytes. REG holds the rtl of the register |
4202 | to be adjusted, and TEMP, if nonnegative, holds the register number | |
4203 | of a general register that we may clobber. */ | |
8aa2a305 JW |
4204 | |
4205 | static void | |
885c9a39 | 4206 | output_stack_adjust (size, reg, temp) |
8aa2a305 | 4207 | int size; |
46d81ffa | 4208 | rtx reg; |
885c9a39 | 4209 | int temp; |
8aa2a305 JW |
4210 | { |
4211 | if (size) | |
4212 | { | |
fa5322fa AO |
4213 | HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT; |
4214 | ||
4215 | if (size % align) | |
4216 | abort (); | |
4217 | ||
4218 | if (CONST_OK_FOR_ADD (size)) | |
4219 | emit_insn (GEN_ADD3 (reg, reg, GEN_INT (size))); | |
f3cd5375 JW |
4220 | /* Try to do it with two partial adjustments; however, we must make |
4221 | sure that the stack is properly aligned at all times, in case | |
6f317ef3 | 4222 | an interrupt occurs between the two partial adjustments. */ |
fa5322fa AO |
4223 | else if (CONST_OK_FOR_ADD (size / 2 & -align) |
4224 | && CONST_OK_FOR_ADD (size - (size / 2 & -align))) | |
f3cd5375 | 4225 | { |
fa5322fa AO |
4226 | emit_insn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align))); |
4227 | emit_insn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align)))); | |
f3cd5375 JW |
4228 | } |
4229 | else | |
8aa2a305 | 4230 | { |
f3cd5375 JW |
4231 | rtx const_reg; |
4232 | ||
4233 | /* If TEMP is invalid, we could temporarily save a general | |
4234 | register to MACL. However, there is currently no need | |
4235 | to handle this case, so just abort when we see it. */ | |
4236 | if (temp < 0) | |
4237 | abort (); | |
fa5322fa | 4238 | const_reg = gen_rtx_REG (GET_MODE (reg), temp); |
f3cd5375 JW |
4239 | |
4240 | /* If SIZE is negative, subtract the positive value. | |
4241 | This sometimes allows a constant pool entry to be shared | |
4242 | between prologue and epilogue code. */ | |
4243 | if (size < 0) | |
885c9a39 | 4244 | { |
fa5322fa AO |
4245 | emit_insn (GEN_MOV (const_reg, GEN_INT (-size))); |
4246 | emit_insn (GEN_SUB3 (reg, reg, const_reg)); | |
885c9a39 JR |
4247 | } |
4248 | else | |
4249 | { | |
fa5322fa AO |
4250 | emit_insn (GEN_MOV (const_reg, GEN_INT (size))); |
4251 | emit_insn (GEN_ADD3 (reg, reg, const_reg)); | |
885c9a39 | 4252 | } |
8aa2a305 | 4253 | } |
8aa2a305 JW |
4254 | } |
4255 | } | |
4256 | ||
4257 | /* Output RTL to push register RN onto the stack. */ | |
4258 | ||
4259 | static void | |
4260 | push (rn) | |
4261 | int rn; | |
4262 | { | |
4263 | rtx x; | |
225e4f43 R |
4264 | if (rn == FPUL_REG) |
4265 | x = gen_push_fpul (); | |
4266 | else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE | |
104ee20b | 4267 | && FP_OR_XD_REGISTER_P (rn)) |
225e4f43 | 4268 | { |
104ee20b | 4269 | if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1) |
225e4f43 | 4270 | return; |
c5c76735 | 4271 | x = gen_push_4 (gen_rtx_REG (DFmode, rn)); |
225e4f43 | 4272 | } |
104ee20b | 4273 | else if (TARGET_SH3E && FP_REGISTER_P (rn)) |
c5c76735 | 4274 | x = gen_push_e (gen_rtx_REG (SFmode, rn)); |
1a95a963 | 4275 | else |
c5c76735 | 4276 | x = gen_push (gen_rtx_REG (SImode, rn)); |
1a95a963 | 4277 | |
1245df60 | 4278 | x = emit_insn (x); |
c5c76735 JL |
4279 | REG_NOTES (x) |
4280 | = gen_rtx_EXPR_LIST (REG_INC, | |
4281 | gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0); | |
8aa2a305 JW |
4282 | } |
4283 | ||
4284 | /* Output RTL to pop register RN from the stack. */ | |
4285 | ||
4286 | static void | |
4287 | pop (rn) | |
4288 | int rn; | |
4289 | { | |
4290 | rtx x; | |
225e4f43 R |
4291 | if (rn == FPUL_REG) |
4292 | x = gen_pop_fpul (); | |
4293 | else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE | |
104ee20b | 4294 | && FP_OR_XD_REGISTER_P (rn)) |
225e4f43 | 4295 | { |
104ee20b | 4296 | if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1) |
225e4f43 | 4297 | return; |
c5c76735 | 4298 | x = gen_pop_4 (gen_rtx_REG (DFmode, rn)); |
225e4f43 | 4299 | } |
104ee20b | 4300 | else if (TARGET_SH3E && FP_REGISTER_P (rn)) |
c5c76735 | 4301 | x = gen_pop_e (gen_rtx_REG (SFmode, rn)); |
1a95a963 | 4302 | else |
c5c76735 | 4303 | x = gen_pop (gen_rtx_REG (SImode, rn)); |
1a95a963 | 4304 | |
1245df60 | 4305 | x = emit_insn (x); |
c5c76735 JL |
4306 | REG_NOTES (x) |
4307 | = gen_rtx_EXPR_LIST (REG_INC, | |
4308 | gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0); | |
8aa2a305 JW |
4309 | } |
4310 | ||
1245df60 | 4311 | /* Generate code to push the regs specified in the mask. */ |
8aa2a305 JW |
4312 | |
4313 | static void | |
fa5322fa AO |
4314 | push_regs (mask) |
4315 | HOST_WIDE_INT *mask; | |
8aa2a305 JW |
4316 | { |
4317 | int i; | |
4318 | ||
1245df60 R |
4319 | /* Push PR last; this gives better latencies after the prologue, and |
4320 | candidates for the return delay slot when there are no general | |
4321 | registers pushed. */ | |
fa5322fa AO |
4322 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
4323 | if (i != PR_REG && mask[i / 32] & (1 << (i % 32))) | |
1a95a963 | 4324 | push (i); |
fa5322fa | 4325 | if (mask[PR_REG / 32] & (1 << (PR_REG % 32))) |
1245df60 | 4326 | push (PR_REG); |
8aa2a305 JW |
4327 | } |
4328 | ||
4329 | /* Work out the registers which need to be saved, both as a mask and a | |
1245df60 | 4330 | count of saved words. |
8aa2a305 JW |
4331 | |
4332 | If doing a pragma interrupt function, then push all regs used by the | |
4333 | function, and if we call another function (we can tell by looking at PR), | |
4334 | make sure that all the regs it clobbers are safe too. */ | |
4335 | ||
fa5322fa AO |
4336 | static void |
4337 | calc_live_regs (count_ptr, live_regs_mask) | |
8aa2a305 | 4338 | int *count_ptr; |
fa5322fa | 4339 | HOST_WIDE_INT *live_regs_mask; |
8aa2a305 JW |
4340 | { |
4341 | int reg; | |
1245df60 | 4342 | int count; |
157131d7 | 4343 | int interrupt_handler; |
3007d592 R |
4344 | rtx pr_initial; |
4345 | int pr_live; | |
157131d7 SC |
4346 | |
4347 | if ((lookup_attribute | |
4348 | ("interrupt_handler", | |
91d231cb | 4349 | DECL_ATTRIBUTES (current_function_decl))) |
157131d7 SC |
4350 | != NULL_TREE) |
4351 | interrupt_handler = 1; | |
4352 | else | |
4353 | interrupt_handler = 0; | |
8aa2a305 | 4354 | |
fa5322fa AO |
4355 | for (count = 0; 32 * count < FIRST_PSEUDO_REGISTER; count++) |
4356 | live_regs_mask[count] = 0; | |
225e4f43 R |
4357 | /* If we can save a lot of saves by switching to double mode, do that. */ |
4358 | if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE) | |
4359 | for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2) | |
4360 | if (regs_ever_live[reg] && regs_ever_live[reg+1] | |
157131d7 | 4361 | && (! call_used_regs[reg] || (interrupt_handler && ! pragma_trapa)) |
225e4f43 R |
4362 | && ++count > 2) |
4363 | { | |
4364 | target_flags &= ~FPU_SINGLE_BIT; | |
4365 | break; | |
4366 | } | |
1951818c | 4367 | pr_initial = has_hard_reg_initial_val (Pmode, |
12e85a0e R |
4368 | TARGET_SHMEDIA |
4369 | ? PR_MEDIA_REG : PR_REG); | |
3007d592 | 4370 | pr_live = (pr_initial |
12e85a0e R |
4371 | ? REGNO (pr_initial) != (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) |
4372 | : regs_ever_live[TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG]); | |
fa5322fa AO |
4373 | /* Force PR to be live if the prologue has to call the SHmedia |
4374 | argument decoder or register saver. */ | |
4375 | if (TARGET_SHCOMPACT | |
4376 | && ((current_function_args_info.call_cookie | |
4377 | & ~ CALL_COOKIE_RET_TRAMP (1)) | |
4378 | || current_function_has_nonlocal_label)) | |
4379 | pr_live = 1; | |
1245df60 | 4380 | for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--) |
8aa2a305 | 4381 | { |
12e85a0e | 4382 | if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) |
3007d592 R |
4383 | ? pr_live |
4384 | : (interrupt_handler && ! pragma_trapa) | |
1245df60 R |
4385 | ? (/* Need to save all the regs ever live. */ |
4386 | (regs_ever_live[reg] | |
4387 | || (call_used_regs[reg] | |
4388 | && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG) | |
3007d592 | 4389 | && pr_live)) |
1245df60 R |
4390 | && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM |
4391 | && reg != RETURN_ADDRESS_POINTER_REGNUM | |
225e4f43 | 4392 | && reg != T_REG && reg != GBR_REG && reg != FPSCR_REG) |
1245df60 R |
4393 | : (/* Only push those regs which are used and need to be saved. */ |
4394 | regs_ever_live[reg] && ! call_used_regs[reg])) | |
8aa2a305 | 4395 | { |
fa5322fa AO |
4396 | live_regs_mask[reg / 32] |= 1 << (reg % 32); |
4397 | count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg)); | |
4398 | ||
4399 | if ((TARGET_SH4 || TARGET_SH5) && TARGET_FMOVD | |
4400 | && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT) | |
eda44c78 | 4401 | { |
104ee20b | 4402 | if (FP_REGISTER_P (reg)) |
eda44c78 R |
4403 | { |
4404 | if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1]) | |
4405 | { | |
fa5322fa AO |
4406 | live_regs_mask[(reg ^ 1) / 32] |= 1 << ((reg ^ 1) % 32); |
4407 | count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1)); | |
eda44c78 R |
4408 | } |
4409 | } | |
fa5322fa | 4410 | else if (XD_REGISTER_P (reg)) |
eda44c78 R |
4411 | { |
4412 | /* Must switch to double mode to access these registers. */ | |
4413 | target_flags &= ~FPU_SINGLE_BIT; | |
eda44c78 R |
4414 | } |
4415 | } | |
8aa2a305 JW |
4416 | } |
4417 | } | |
4418 | ||
fa5322fa | 4419 | *count_ptr = count; |
8aa2a305 JW |
4420 | } |
4421 | ||
4422 | /* Code to generate prologue and epilogue sequences */ | |
b9654711 | 4423 | |
0ad913af R |
4424 | /* PUSHED is the number of bytes that are bing pushed on the |
4425 | stack for register saves. Return the frame size, padded | |
4426 | appropriately so that the stack stays properly aligned. */ | |
e5f8d4c0 R |
4427 | static HOST_WIDE_INT |
4428 | rounded_frame_size (pushed) | |
4429 | int pushed; | |
4430 | { | |
4431 | HOST_WIDE_INT size = get_frame_size (); | |
4432 | HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT; | |
4433 | ||
c5b9ef02 | 4434 | return ((size + pushed + align - 1) & -align) - pushed; |
e5f8d4c0 R |
4435 | } |
4436 | ||
fa5322fa AO |
4437 | /* Choose a call-clobbered target-branch register that remains |
4438 | unchanged along the whole function. We set it up as the return | |
4439 | value in the prologue. */ | |
4440 | int | |
4441 | sh_media_register_for_return () | |
4442 | { | |
4443 | int regno; | |
4444 | int tr0_used; | |
4445 | ||
4446 | if (! current_function_is_leaf) | |
4447 | return -1; | |
4448 | ||
4449 | tr0_used = flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]; | |
4450 | ||
4451 | for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++) | |
4452 | if (call_used_regs[regno] && ! regs_ever_live[regno]) | |
4453 | return regno; | |
4454 | ||
4455 | return -1; | |
4456 | } | |
4457 | ||
b9654711 SC |
4458 | void |
4459 | sh_expand_prologue () | |
4460 | { | |
fa5322fa | 4461 | HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32]; |
40d2032b | 4462 | int d, i; |
fa5322fa | 4463 | int d_rounding = 0; |
225e4f43 | 4464 | int save_flags = target_flags; |
b9654711 | 4465 | |
552ecbd9 AH |
4466 | current_function_interrupt |
4467 | = lookup_attribute ("interrupt_handler", | |
91d231cb | 4468 | DECL_ATTRIBUTES (current_function_decl)) |
552ecbd9 AH |
4469 | != NULL_TREE; |
4470 | ||
0d7e008e | 4471 | /* We have pretend args if we had an object sent partially in registers |
8aa2a305 | 4472 | and partially on the stack, e.g. a large structure. */ |
fa5322fa AO |
4473 | output_stack_adjust (-current_function_pretend_args_size |
4474 | - current_function_args_info.stack_regs * 8, | |
4475 | stack_pointer_rtx, TARGET_SH5 ? 0 : 1); | |
b9654711 | 4476 | |
40d2032b JW |
4477 | extra_push = 0; |
4478 | ||
2b1fd83f AO |
4479 | if (TARGET_SHCOMPACT && flag_pic && current_function_args_info.call_cookie) |
4480 | /* We're going to use the PIC register to load the address of the | |
4481 | incoming-argument decoder and/or of the return trampoline from | |
4482 | the GOT, so make sure the PIC register is preserved and | |
4483 | initialized. */ | |
4484 | regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; | |
4485 | ||
fa5322fa AO |
4486 | if (TARGET_SHCOMPACT |
4487 | && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1))) | |
4488 | { | |
4489 | int reg; | |
4490 | ||
4491 | /* First, make all registers with incoming arguments that will | |
4492 | be pushed onto the stack live, so that register renaming | |
4493 | doesn't overwrite them. */ | |
4494 | for (reg = 0; reg < NPARM_REGS (SImode); reg++) | |
4495 | if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info.call_cookie) | |
4496 | >= NPARM_REGS (SImode) - reg) | |
4497 | for (; reg < NPARM_REGS (SImode); reg++) | |
4498 | emit_insn (gen_shcompact_preserve_incoming_args | |
4499 | (gen_rtx_REG (SImode, FIRST_PARM_REG + reg))); | |
4500 | else if (CALL_COOKIE_INT_REG_GET | |
4501 | (current_function_args_info.call_cookie, reg) == 1) | |
4502 | emit_insn (gen_shcompact_preserve_incoming_args | |
4503 | (gen_rtx_REG (SImode, FIRST_PARM_REG + reg))); | |
4504 | ||
4505 | emit_move_insn (gen_rtx_REG (Pmode, MACL_REG), | |
4506 | stack_pointer_rtx); | |
4507 | emit_move_insn (gen_rtx_REG (SImode, R0_REG), | |
4508 | GEN_INT (current_function_args_info.call_cookie)); | |
4509 | emit_move_insn (gen_rtx_REG (SImode, MACH_REG), | |
4510 | gen_rtx_REG (SImode, R0_REG)); | |
4511 | } | |
4512 | else if (TARGET_SHMEDIA) | |
4513 | { | |
4514 | int tr = sh_media_register_for_return (); | |
4515 | ||
4516 | if (tr >= 0) | |
4517 | { | |
4518 | rtx insn = emit_move_insn (gen_rtx_REG (DImode, tr), | |
4519 | gen_rtx_REG (DImode, PR_MEDIA_REG)); | |
4520 | ||
4521 | /* If this function only exits with sibcalls, this copy | |
4522 | will be flagged as dead. */ | |
4523 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
4524 | const0_rtx, | |
4525 | REG_NOTES (insn)); | |
4526 | } | |
4527 | } | |
4528 | ||
7ab56274 R |
4529 | /* Emit the code for SETUP_VARARGS. */ |
4530 | if (current_function_varargs || current_function_stdarg) | |
b9654711 | 4531 | { |
1a95a963 | 4532 | /* This is not used by the SH3E calling convention */ |
7ab56274 | 4533 | if (TARGET_SH1 && ! TARGET_SH3E && ! TARGET_SH5 && ! TARGET_HITACHI) |
1245df60 | 4534 | { |
1a95a963 JW |
4535 | /* Push arg regs as if they'd been provided by caller in stack. */ |
4536 | for (i = 0; i < NPARM_REGS(SImode); i++) | |
4537 | { | |
4538 | int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1; | |
aec373f1 R |
4539 | if (i >= (NPARM_REGS(SImode) |
4540 | - current_function_args_info.arg_count[(int) SH_ARG_INT] | |
4541 | )) | |
1a95a963 JW |
4542 | break; |
4543 | push (rn); | |
4544 | extra_push += 4; | |
4545 | } | |
1245df60 | 4546 | } |
b9654711 | 4547 | } |
1a95a963 | 4548 | |
4408efce JL |
4549 | /* If we're supposed to switch stacks at function entry, do so now. */ |
4550 | if (sp_switch) | |
4551 | emit_insn (gen_sp_switch_1 ()); | |
4552 | ||
fa5322fa | 4553 | calc_live_regs (&d, live_regs_mask); |
225e4f43 R |
4554 | /* ??? Maybe we could save some switching if we can move a mode switch |
4555 | that already happens to be at the function start into the prologue. */ | |
4556 | if (target_flags != save_flags) | |
4557 | emit_insn (gen_toggle_sz ()); | |
6915629f | 4558 | |
fa5322fa AO |
4559 | if (TARGET_SH5) |
4560 | { | |
4561 | int i; | |
4562 | int offset; | |
4563 | int align; | |
4564 | rtx r0 = gen_rtx_REG (Pmode, R0_REG); | |
4565 | int offset_in_r0 = -1; | |
4566 | int sp_in_r0 = 0; | |
4567 | ||
4568 | if (d % (STACK_BOUNDARY / BITS_PER_UNIT)) | |
4569 | d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT) | |
4570 | - d % (STACK_BOUNDARY / BITS_PER_UNIT)); | |
4571 | ||
4572 | offset = d + d_rounding; | |
4573 | output_stack_adjust (-offset, stack_pointer_rtx, 1); | |
4574 | ||
4575 | /* We loop twice: first, we save 8-byte aligned registers in the | |
4576 | higher addresses, that are known to be aligned. Then, we | |
4577 | proceed to saving 32-bit registers that don't need 8-byte | |
4578 | alignment. */ | |
4579 | for (align = 1; align >= 0; align--) | |
4580 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
4581 | if (live_regs_mask[i/32] & (1 << (i % 32))) | |
4582 | { | |
4583 | enum machine_mode mode = REGISTER_NATURAL_MODE (i); | |
4584 | int reg = i; | |
4585 | rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX; | |
4586 | ||
4587 | if (mode == SFmode && (i % 2) == 1 | |
4588 | && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i) | |
4589 | && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32)))) | |
4590 | { | |
4591 | mode = DFmode; | |
4592 | i--; | |
4593 | reg--; | |
4594 | } | |
4595 | ||
4596 | /* If we're doing the aligned pass and this is not aligned, | |
4597 | or we're doing the unaligned pass and this is aligned, | |
4598 | skip it. */ | |
4599 | if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) | |
4600 | == 0) != align) | |
4601 | continue; | |
4602 | ||
4603 | offset -= GET_MODE_SIZE (mode); | |
4604 | ||
4605 | reg_rtx = gen_rtx_REG (mode, reg); | |
4606 | ||
4607 | mem_rtx = gen_rtx_MEM (mode, | |
4608 | gen_rtx_PLUS (Pmode, | |
4609 | stack_pointer_rtx, | |
4610 | GEN_INT (offset))); | |
4611 | ||
4612 | GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec); | |
4613 | ||
4614 | mem_rtx = NULL_RTX; | |
4615 | ||
4616 | try_pre_dec: | |
4617 | do | |
4618 | if (HAVE_PRE_DECREMENT | |
4619 | && (offset_in_r0 - offset == GET_MODE_SIZE (mode) | |
4620 | || mem_rtx == NULL_RTX | |
4621 | || i == PR_REG || SPECIAL_REGISTER_P (i))) | |
4622 | { | |
4623 | pre_dec = gen_rtx_MEM (mode, | |
4624 | gen_rtx_PRE_DEC (Pmode, r0)); | |
4625 | ||
4626 | GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0), | |
4627 | pre_dec_ok); | |
4628 | ||
4629 | pre_dec = NULL_RTX; | |
4630 | ||
4631 | break; | |
4632 | ||
4633 | pre_dec_ok: | |
4634 | mem_rtx = NULL_RTX; | |
4635 | offset += GET_MODE_SIZE (mode); | |
4636 | } | |
4637 | while (0); | |
4638 | ||
4639 | if (mem_rtx != NULL_RTX) | |
4640 | goto addr_ok; | |
4641 | ||
4642 | if (offset_in_r0 == -1) | |
4643 | { | |
4644 | emit_move_insn (r0, GEN_INT (offset)); | |
4645 | offset_in_r0 = offset; | |
4646 | } | |
4647 | else if (offset != offset_in_r0) | |
4648 | { | |
4649 | emit_move_insn (r0, | |
4650 | gen_rtx_PLUS | |
4651 | (Pmode, r0, | |
4652 | GEN_INT (offset - offset_in_r0))); | |
4653 | offset_in_r0 += offset - offset_in_r0; | |
4654 | } | |
4655 | ||
4656 | if (pre_dec != NULL_RTX) | |
4657 | { | |
4658 | if (! sp_in_r0) | |
4659 | { | |
4660 | emit_move_insn (r0, | |
4661 | gen_rtx_PLUS | |
4662 | (Pmode, r0, stack_pointer_rtx)); | |
4663 | sp_in_r0 = 1; | |
4664 | } | |
4665 | ||
4666 | offset -= GET_MODE_SIZE (mode); | |
4667 | offset_in_r0 -= GET_MODE_SIZE (mode); | |
4668 | ||
4669 | mem_rtx = pre_dec; | |
4670 | } | |
4671 | else if (sp_in_r0) | |
4672 | mem_rtx = gen_rtx_MEM (mode, r0); | |
4673 | else | |
4674 | mem_rtx = gen_rtx_MEM (mode, | |
4675 | gen_rtx_PLUS (Pmode, | |
4676 | stack_pointer_rtx, | |
4677 | r0)); | |
4678 | ||
4679 | /* We must not use an r0-based address for target-branch | |
4680 | registers or for special registers without pre-dec | |
4681 | memory addresses, since we store their values in r0 | |
4682 | first. */ | |
4683 | if (TARGET_REGISTER_P (i) | |
4684 | || ((i == PR_REG || SPECIAL_REGISTER_P (i)) | |
4685 | && mem_rtx != pre_dec)) | |
4686 | abort (); | |
4687 | ||
4688 | addr_ok: | |
4689 | if (TARGET_REGISTER_P (i) | |
4690 | || ((i == PR_REG || SPECIAL_REGISTER_P (i)) | |
4691 | && mem_rtx != pre_dec)) | |
4692 | { | |
4693 | rtx r0mode = gen_rtx_REG (GET_MODE (reg_rtx), R0_REG); | |
4694 | ||
4695 | emit_move_insn (r0mode, reg_rtx); | |
4696 | ||
4697 | offset_in_r0 = -1; | |
4698 | sp_in_r0 = 0; | |
4699 | ||
4700 | reg_rtx = r0mode; | |
4701 | } | |
4702 | ||
4703 | emit_move_insn (mem_rtx, reg_rtx); | |
4704 | } | |
4705 | ||
4706 | if (offset != d_rounding) | |
4707 | abort (); | |
4708 | } | |
4709 | else | |
4710 | push_regs (live_regs_mask); | |
1a66cd67 | 4711 | |
6915629f | 4712 | if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
fd969c7c AO |
4713 | { |
4714 | rtx insn = get_last_insn (); | |
4715 | rtx last = emit_insn (gen_GOTaddr2picreg ()); | |
4716 | ||
4717 | /* Mark these insns as possibly dead. Sometimes, flow2 may | |
4718 | delete all uses of the PIC register. In this case, let it | |
4719 | delete the initialization too. */ | |
4720 | do | |
4721 | { | |
4722 | insn = NEXT_INSN (insn); | |
4723 | ||
4724 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
4725 | const0_rtx, | |
4726 | REG_NOTES (insn)); | |
4727 | } | |
4728 | while (insn != last); | |
4729 | } | |
1a66cd67 | 4730 | |
fa5322fa AO |
4731 | if (SHMEDIA_REGS_STACK_ADJUST ()) |
4732 | { | |
4733 | emit_move_insn (gen_rtx_REG (Pmode, R0_REG), | |
4734 | gen_rtx_SYMBOL_REF (Pmode, | |
4735 | TARGET_FPU_ANY | |
4736 | ? "__GCC_push_shmedia_regs" | |
4737 | : "__GCC_push_shmedia_regs_nofpu")); | |
4738 | /* This must NOT go through the PLT, otherwise mach and macl | |
4739 | may be clobbered. */ | |
4740 | emit_insn (gen_shmedia_save_restore_regs_compact | |
4741 | (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ()))); | |
4742 | } | |
4743 | ||
225e4f43 | 4744 | if (target_flags != save_flags) |
b90dbca6 AO |
4745 | { |
4746 | rtx insn = emit_insn (gen_toggle_sz ()); | |
4747 | ||
4748 | /* If we're lucky, a mode switch in the function body will | |
4749 | overwrite fpscr, turning this insn dead. Tell flow this | |
4750 | insn is ok to delete. */ | |
4751 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
4752 | const0_rtx, | |
4753 | REG_NOTES (insn)); | |
4754 | } | |
1a95a963 | 4755 | |
225e4f43 R |
4756 | target_flags = save_flags; |
4757 | ||
fa5322fa AO |
4758 | output_stack_adjust (-rounded_frame_size (d) + d_rounding, |
4759 | stack_pointer_rtx, TARGET_SH5 ? 0 : 1); | |
b9654711 SC |
4760 | |
4761 | if (frame_pointer_needed) | |
fa5322fa AO |
4762 | emit_insn (GEN_MOV (frame_pointer_rtx, stack_pointer_rtx)); |
4763 | ||
fa5322fa AO |
4764 | if (TARGET_SHCOMPACT |
4765 | && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1))) | |
4766 | { | |
4767 | /* This must NOT go through the PLT, otherwise mach and macl | |
4768 | may be clobbered. */ | |
4769 | emit_move_insn (gen_rtx_REG (Pmode, R0_REG), | |
4770 | gen_rtx_SYMBOL_REF (Pmode, | |
4771 | "__GCC_shcompact_incoming_args")); | |
4772 | emit_insn (gen_shcompact_incoming_args ()); | |
4773 | } | |
b9654711 SC |
4774 | } |
4775 | ||
4776 | void | |
4777 | sh_expand_epilogue () | |
4778 | { | |
fa5322fa | 4779 | HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32]; |
40d2032b | 4780 | int d, i; |
fa5322fa | 4781 | int d_rounding = 0; |
b9654711 | 4782 | |
225e4f43 | 4783 | int save_flags = target_flags; |
e5f8d4c0 | 4784 | int frame_size; |
3d5a0820 | 4785 | |
fa5322fa | 4786 | calc_live_regs (&d, live_regs_mask); |
3d5a0820 | 4787 | |
fa5322fa AO |
4788 | if (TARGET_SH5 && d % (STACK_BOUNDARY / BITS_PER_UNIT)) |
4789 | d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT) | |
4790 | - d % (STACK_BOUNDARY / BITS_PER_UNIT)); | |
4791 | ||
4792 | frame_size = rounded_frame_size (d) - d_rounding; | |
16bea517 | 4793 | |
b9654711 | 4794 | if (frame_pointer_needed) |
46d81ffa | 4795 | { |
3d5a0820 | 4796 | output_stack_adjust (frame_size, frame_pointer_rtx, 7); |
07f5b9aa JL |
4797 | |
4798 | /* We must avoid moving the stack pointer adjustment past code | |
4799 | which reads from the local frame, else an interrupt could | |
4800 | occur after the SP adjustment and clobber data in the local | |
4801 | frame. */ | |
4802 | emit_insn (gen_blockage ()); | |
fa5322fa | 4803 | emit_insn (GEN_MOV (stack_pointer_rtx, frame_pointer_rtx)); |
46d81ffa | 4804 | } |
3d5a0820 | 4805 | else if (frame_size) |
07f5b9aa JL |
4806 | { |
4807 | /* We must avoid moving the stack pointer adjustment past code | |
4808 | which reads from the local frame, else an interrupt could | |
4809 | occur after the SP adjustment and clobber data in the local | |
4810 | frame. */ | |
4811 | emit_insn (gen_blockage ()); | |
3d5a0820 | 4812 | output_stack_adjust (frame_size, stack_pointer_rtx, 7); |
07f5b9aa | 4813 | } |
b9654711 | 4814 | |
fa5322fa AO |
4815 | if (SHMEDIA_REGS_STACK_ADJUST ()) |
4816 | { | |
4817 | emit_move_insn (gen_rtx_REG (Pmode, R0_REG), | |
4818 | gen_rtx_SYMBOL_REF (Pmode, | |
4819 | TARGET_FPU_ANY | |
4820 | ? "__GCC_pop_shmedia_regs" | |
4821 | : "__GCC_pop_shmedia_regs_nofpu")); | |
4822 | /* This must NOT go through the PLT, otherwise mach and macl | |
4823 | may be clobbered. */ | |
4824 | emit_insn (gen_shmedia_save_restore_regs_compact | |
4825 | (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ()))); | |
4826 | } | |
4827 | ||
16bea517 | 4828 | /* Pop all the registers. */ |
0d7e008e | 4829 | |
225e4f43 R |
4830 | if (target_flags != save_flags) |
4831 | emit_insn (gen_toggle_sz ()); | |
fa5322fa AO |
4832 | if (TARGET_SH5) |
4833 | { | |
4834 | int offset = d_rounding; | |
4835 | int offset_in_r0 = -1; | |
4836 | int sp_in_r0 = 0; | |
4837 | int align; | |
4838 | rtx r0 = gen_rtx_REG (Pmode, R0_REG); | |
4839 | ||
4840 | /* We loop twice: first, we save 8-byte aligned registers in the | |
4841 | higher addresses, that are known to be aligned. Then, we | |
4842 | proceed to saving 32-bit registers that don't need 8-byte | |
4843 | alignment. */ | |
4844 | for (align = 0; align <= 1; align++) | |
4845 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
4846 | if (live_regs_mask[i/32] & (1 << (i % 32))) | |
4847 | { | |
4848 | enum machine_mode mode = REGISTER_NATURAL_MODE (i); | |
4849 | int reg = i; | |
4850 | rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn; | |
4851 | ||
4852 | if (mode == SFmode && (i % 2) == 0 | |
4853 | && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i) | |
4854 | && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32)))) | |
4855 | { | |
4856 | mode = DFmode; | |
4857 | i++; | |
4858 | } | |
4859 | ||
4860 | /* If we're doing the aligned pass and this is not aligned, | |
4861 | or we're doing the unaligned pass and this is aligned, | |
4862 | skip it. */ | |
4863 | if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) | |
4864 | == 0) != align) | |
4865 | continue; | |
4866 | ||
4867 | reg_rtx = gen_rtx_REG (mode, reg); | |
4868 | ||
4869 | mem_rtx = gen_rtx_MEM (mode, | |
4870 | gen_rtx_PLUS (Pmode, | |
4871 | stack_pointer_rtx, | |
4872 | GEN_INT (offset))); | |
4873 | ||
4874 | GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc); | |
4875 | ||
4876 | mem_rtx = NULL_RTX; | |
4877 | ||
4878 | try_post_inc: | |
4879 | do | |
4880 | if (HAVE_POST_INCREMENT | |
4881 | && (offset == offset_in_r0 | |
4882 | || (offset + GET_MODE_SIZE (mode) != d + d_rounding | |
4883 | && mem_rtx == NULL_RTX) | |
4884 | || i == PR_REG || SPECIAL_REGISTER_P (i))) | |
4885 | { | |
4886 | post_inc = gen_rtx_MEM (mode, | |
4887 | gen_rtx_POST_INC (Pmode, r0)); | |
4888 | ||
4889 | GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0), | |
4890 | post_inc_ok); | |
4891 | ||
4892 | post_inc = NULL_RTX; | |
4893 | ||
4894 | break; | |
4895 | ||
4896 | post_inc_ok: | |
4897 | mem_rtx = NULL_RTX; | |
4898 | } | |
4899 | while (0); | |
4900 | ||
4901 | if (mem_rtx != NULL_RTX) | |
4902 | goto addr_ok; | |
4903 | ||
4904 | if (offset_in_r0 == -1) | |
4905 | { | |
4906 | emit_move_insn (r0, GEN_INT (offset)); | |
4907 | offset_in_r0 = offset; | |
4908 | } | |
4909 | else if (offset != offset_in_r0) | |
4910 | { | |
4911 | emit_move_insn (r0, | |
4912 | gen_rtx_PLUS | |
4913 | (Pmode, r0, | |
4914 | GEN_INT (offset - offset_in_r0))); | |
4915 | offset_in_r0 += offset - offset_in_r0; | |
4916 | } | |
4917 | ||
4918 | if (post_inc != NULL_RTX) | |
4919 | { | |
4920 | if (! sp_in_r0) | |
4921 | { | |
4922 | emit_move_insn (r0, | |
4923 | gen_rtx_PLUS | |
4924 | (Pmode, r0, stack_pointer_rtx)); | |
4925 | sp_in_r0 = 1; | |
4926 | } | |
4927 | ||
4928 | mem_rtx = post_inc; | |
4929 | ||
4930 | offset_in_r0 += GET_MODE_SIZE (mode); | |
4931 | } | |
4932 | else if (sp_in_r0) | |
4933 | mem_rtx = gen_rtx_MEM (mode, r0); | |
4934 | else | |
4935 | mem_rtx = gen_rtx_MEM (mode, | |
4936 | gen_rtx_PLUS (Pmode, | |
4937 | stack_pointer_rtx, | |
4938 | r0)); | |
4939 | ||
4940 | if ((i == PR_REG || SPECIAL_REGISTER_P (i)) | |
4941 | && mem_rtx != post_inc) | |
4942 | abort (); | |
4943 | ||
4944 | addr_ok: | |
4945 | if ((i == PR_REG || SPECIAL_REGISTER_P (i)) | |
4946 | && mem_rtx != post_inc) | |
4947 | { | |
4948 | insn = emit_move_insn (r0, mem_rtx); | |
4949 | mem_rtx = r0; | |
4950 | } | |
4951 | else if (TARGET_REGISTER_P (i)) | |
4952 | { | |
4953 | rtx r1 = gen_rtx_REG (mode, R1_REG); | |
4954 | ||
4955 | insn = emit_move_insn (r1, mem_rtx); | |
4956 | mem_rtx = r1; | |
4957 | } | |
4958 | ||
4959 | insn = emit_move_insn (reg_rtx, mem_rtx); | |
4960 | ||
4961 | offset += GET_MODE_SIZE (mode); | |
4962 | } | |
4963 | ||
4964 | if (offset != d + d_rounding) | |
4965 | abort (); | |
4966 | ||
4967 | goto finish; | |
4968 | } | |
4969 | else | |
4970 | d = 0; | |
4971 | if (live_regs_mask[PR_REG / 32] & (1 << (PR_REG % 32))) | |
1245df60 | 4972 | pop (PR_REG); |
b9654711 SC |
4973 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
4974 | { | |
4975 | int j = (FIRST_PSEUDO_REGISTER - 1) - i; | |
fa5322fa AO |
4976 | |
4977 | if (j != PR_REG && live_regs_mask[j / 32] & (1 << (j % 32))) | |
8aa2a305 | 4978 | pop (j); |
b9654711 | 4979 | } |
fa5322fa | 4980 | finish: |
225e4f43 R |
4981 | if (target_flags != save_flags) |
4982 | emit_insn (gen_toggle_sz ()); | |
4983 | target_flags = save_flags; | |
b9654711 | 4984 | |
fa5322fa AO |
4985 | output_stack_adjust (extra_push + current_function_pretend_args_size |
4986 | + d + d_rounding | |
4987 | + current_function_args_info.stack_regs * 8, | |
885c9a39 | 4988 | stack_pointer_rtx, 7); |
4408efce JL |
4989 | |
4990 | /* Switch back to the normal stack if necessary. */ | |
4991 | if (sp_switch) | |
4992 | emit_insn (gen_sp_switch_2 ()); | |
89d4bc35 AO |
4993 | |
4994 | /* Tell flow the insn that pops PR isn't dead. */ | |
fa5322fa AO |
4995 | /* PR_REG will never be live in SHmedia mode, and we don't need to |
4996 | USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG | |
4997 | by the return pattern. */ | |
4998 | if (live_regs_mask[PR_REG / 32] & (1 << (PR_REG % 32))) | |
89d4bc35 | 4999 | emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG))); |
b9654711 SC |
5000 | } |
5001 | ||
afbc2905 R |
5002 | static int sh_need_epilogue_known = 0; |
5003 | ||
5004 | int | |
5005 | sh_need_epilogue () | |
5006 | { | |
5007 | if (! sh_need_epilogue_known) | |
5008 | { | |
5009 | rtx epilogue; | |
5010 | ||
5011 | start_sequence (); | |
5012 | sh_expand_epilogue (); | |
5013 | epilogue = gen_sequence (); | |
5014 | end_sequence (); | |
5015 | sh_need_epilogue_known | |
5016 | = (GET_CODE (epilogue) == SEQUENCE && XVECLEN (epilogue, 0) == 0 | |
5017 | ? -1 : 1); | |
5018 | } | |
5019 | return sh_need_epilogue_known > 0; | |
5020 | } | |
5021 | ||
8aa2a305 JW |
5022 | /* Clear variables at function end. */ |
5023 | ||
08c148a8 NB |
5024 | static void |
5025 | sh_output_function_epilogue (file, size) | |
5026 | FILE *file ATTRIBUTE_UNUSED; | |
5027 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; | |
8aa2a305 | 5028 | { |
4408efce | 5029 | trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0; |
afbc2905 | 5030 | sh_need_epilogue_known = 0; |
4408efce | 5031 | sp_switch = NULL_RTX; |
8aa2a305 JW |
5032 | } |
5033 | ||
1a95a963 | 5034 | rtx |
648d2ffc | 5035 | sh_builtin_saveregs () |
1a95a963 | 5036 | { |
1a95a963 JW |
5037 | /* First unnamed integer register. */ |
5038 | int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT]; | |
5039 | /* Number of integer registers we need to save. */ | |
5040 | int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg); | |
5041 | /* First unnamed SFmode float reg */ | |
5042 | int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT]; | |
5043 | /* Number of SFmode float regs to save. */ | |
5044 | int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg); | |
318881c0 | 5045 | rtx regbuf, fpregs; |
ba4828e0 RK |
5046 | int bufsize, regno; |
5047 | HOST_WIDE_INT alias_set; | |
1a95a963 | 5048 | |
fa5322fa AO |
5049 | if (TARGET_SH5) |
5050 | { | |
5051 | if (n_intregs) | |
5052 | { | |
5053 | int pushregs = n_intregs; | |
5054 | ||
5055 | while (pushregs < NPARM_REGS (SImode) - 1 | |
5056 | && (CALL_COOKIE_INT_REG_GET | |
5057 | (current_function_args_info.call_cookie, | |
5058 | NPARM_REGS (SImode) - pushregs) | |
5059 | == 1)) | |
5060 | { | |
5061 | current_function_args_info.call_cookie | |
5062 | &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) | |
5063 | - pushregs, 1); | |
5064 | pushregs++; | |
5065 | } | |
5066 | ||
5067 | if (pushregs == NPARM_REGS (SImode)) | |
5068 | current_function_args_info.call_cookie | |
5069 | |= (CALL_COOKIE_INT_REG (0, 1) | |
5070 | | CALL_COOKIE_STACKSEQ (pushregs - 1)); | |
5071 | else | |
5072 | current_function_args_info.call_cookie | |
5073 | |= CALL_COOKIE_STACKSEQ (pushregs); | |
5074 | ||
5075 | current_function_pretend_args_size += 8 * n_intregs; | |
5076 | } | |
5077 | if (TARGET_SHCOMPACT) | |
5078 | return const0_rtx; | |
5079 | } | |
5080 | ||
5081 | if (! TARGET_SH3E && ! TARGET_SH4 && ! TARGET_SH5) | |
5082 | { | |
5083 | error ("__builtin_saveregs not supported by this subtarget"); | |
5084 | return const0_rtx; | |
5085 | } | |
5086 | ||
5087 | if (TARGET_SHMEDIA) | |
5088 | n_floatregs = 0; | |
5089 | ||
6f317ef3 | 5090 | /* Allocate block of memory for the regs. */ |
1a95a963 JW |
5091 | /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte? |
5092 | Or can assign_stack_local accept a 0 SIZE argument? */ | |
5093 | bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD); | |
5094 | ||
fa5322fa AO |
5095 | if (TARGET_SHMEDIA) |
5096 | regbuf = gen_rtx_MEM (BLKmode, | |
5097 | gen_rtx_REG (Pmode, ARG_POINTER_REGNUM)); | |
f78ec36a R |
5098 | else if (n_floatregs & 1) |
5099 | { | |
5100 | rtx addr; | |
5101 | ||
5102 | regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0); | |
5103 | addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0)); | |
5104 | emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD))); | |
5105 | regbuf = change_address (regbuf, BLKmode, addr); | |
5106 | } | |
fa5322fa AO |
5107 | else |
5108 | regbuf = assign_stack_local (BLKmode, bufsize, 0); | |
514066a1 | 5109 | alias_set = get_varargs_alias_set (); |
ba4828e0 | 5110 | set_mem_alias_set (regbuf, alias_set); |
1a95a963 JW |
5111 | |
5112 | /* Save int args. | |
5113 | This is optimized to only save the regs that are necessary. Explicitly | |
5114 | named args need not be saved. */ | |
5115 | if (n_intregs > 0) | |
5116 | move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg, | |
f4ef873c RK |
5117 | adjust_address (regbuf, BLKmode, |
5118 | n_floatregs * UNITS_PER_WORD), | |
1a95a963 JW |
5119 | n_intregs, n_intregs * UNITS_PER_WORD); |
5120 | ||
fa5322fa AO |
5121 | if (TARGET_SHMEDIA) |
5122 | /* Return the address of the regbuf. */ | |
5123 | return XEXP (regbuf, 0); | |
5124 | ||
1a95a963 JW |
5125 | /* Save float args. |
5126 | This is optimized to only save the regs that are necessary. Explicitly | |
5127 | named args need not be saved. | |
5128 | We explicitly build a pointer to the buffer because it halves the insn | |
5129 | count when not optimizing (otherwise the pointer is built for each reg | |
1245df60 R |
5130 | saved). |
5131 | We emit the moves in reverse order so that we can use predecrement. */ | |
1a95a963 JW |
5132 | |
5133 | fpregs = gen_reg_rtx (Pmode); | |
5134 | emit_move_insn (fpregs, XEXP (regbuf, 0)); | |
1245df60 R |
5135 | emit_insn (gen_addsi3 (fpregs, fpregs, |
5136 | GEN_INT (n_floatregs * UNITS_PER_WORD))); | |
225e4f43 R |
5137 | if (TARGET_SH4) |
5138 | { | |
514066a1 | 5139 | rtx mem; |
225e4f43 R |
5140 | for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2) |
5141 | { | |
5142 | emit_insn (gen_addsi3 (fpregs, fpregs, | |
5143 | GEN_INT (-2 * UNITS_PER_WORD))); | |
514066a1 | 5144 | mem = gen_rtx_MEM (DFmode, fpregs); |
ba4828e0 | 5145 | set_mem_alias_set (mem, alias_set); |
514066a1 | 5146 | emit_move_insn (mem, |
225e4f43 R |
5147 | gen_rtx (REG, DFmode, BASE_ARG_REG (DFmode) + regno)); |
5148 | } | |
5149 | regno = first_floatreg; | |
5150 | if (regno & 1) | |
5151 | { | |
5152 | emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD))); | |
514066a1 | 5153 | mem = gen_rtx_MEM (SFmode, fpregs); |
ba4828e0 | 5154 | set_mem_alias_set (mem, alias_set); |
514066a1 | 5155 | emit_move_insn (mem, |
225e4f43 R |
5156 | gen_rtx (REG, SFmode, BASE_ARG_REG (SFmode) + regno |
5157 | - (TARGET_LITTLE_ENDIAN != 0))); | |
5158 | } | |
5159 | } | |
5160 | else | |
1245df60 R |
5161 | for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--) |
5162 | { | |
514066a1 | 5163 | rtx mem; |
ba4828e0 | 5164 | |
1245df60 | 5165 | emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD))); |
514066a1 | 5166 | mem = gen_rtx_MEM (SFmode, fpregs); |
ba4828e0 | 5167 | set_mem_alias_set (mem, alias_set); |
514066a1 | 5168 | emit_move_insn (mem, |
c5c76735 | 5169 | gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno)); |
1245df60 | 5170 | } |
1a95a963 JW |
5171 | |
5172 | /* Return the address of the regbuf. */ | |
5173 | return XEXP (regbuf, 0); | |
5174 | } | |
5175 | ||
514066a1 RH |
5176 | /* Define the `__builtin_va_list' type for the ABI. */ |
5177 | ||
5178 | tree | |
5179 | sh_build_va_list () | |
5180 | { | |
5181 | tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack; | |
5182 | tree record; | |
5183 | ||
fa5322fa | 5184 | if (TARGET_SH5 || (! TARGET_SH3E && ! TARGET_SH4) || TARGET_HITACHI) |
514066a1 RH |
5185 | return ptr_type_node; |
5186 | ||
5187 | record = make_node (RECORD_TYPE); | |
5188 | ||
5189 | f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"), | |
5190 | ptr_type_node); | |
5191 | f_next_o_limit = build_decl (FIELD_DECL, | |
5192 | get_identifier ("__va_next_o_limit"), | |
5193 | ptr_type_node); | |
5194 | f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"), | |
5195 | ptr_type_node); | |
5196 | f_next_fp_limit = build_decl (FIELD_DECL, | |
5197 | get_identifier ("__va_next_fp_limit"), | |
5198 | ptr_type_node); | |
5199 | f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"), | |
5200 | ptr_type_node); | |
5201 | ||
5202 | DECL_FIELD_CONTEXT (f_next_o) = record; | |
5203 | DECL_FIELD_CONTEXT (f_next_o_limit) = record; | |
5204 | DECL_FIELD_CONTEXT (f_next_fp) = record; | |
5205 | DECL_FIELD_CONTEXT (f_next_fp_limit) = record; | |
5206 | DECL_FIELD_CONTEXT (f_next_stack) = record; | |
5207 | ||
5208 | TYPE_FIELDS (record) = f_next_o; | |
5209 | TREE_CHAIN (f_next_o) = f_next_o_limit; | |
5210 | TREE_CHAIN (f_next_o_limit) = f_next_fp; | |
5211 | TREE_CHAIN (f_next_fp) = f_next_fp_limit; | |
5212 | TREE_CHAIN (f_next_fp_limit) = f_next_stack; | |
5213 | ||
5214 | layout_type (record); | |
5215 | ||
5216 | return record; | |
5217 | } | |
5218 | ||
5219 | /* Implement `va_start' for varargs and stdarg. */ | |
5220 | ||
5221 | void | |
5222 | sh_va_start (stdarg_p, valist, nextarg) | |
5223 | int stdarg_p; | |
5224 | tree valist; | |
5225 | rtx nextarg; | |
5226 | { | |
5227 | tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack; | |
5228 | tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack; | |
5229 | tree t, u; | |
5230 | int nfp, nint; | |
5231 | ||
fa5322fa AO |
5232 | if (TARGET_SH5) |
5233 | { | |
5234 | expand_builtin_saveregs (); | |
5235 | /* When the varargs dummy argument is ``passed'' on a register, | |
5236 | we don't want std_expand_builtin_va_start() to apply any | |
5237 | correction for it, so set stdarg_p so as to pretend there's | |
5238 | no such dummy argument. */ | |
5239 | if (current_function_args_info.arg_count[(int) SH_ARG_INT] | |
5240 | < NPARM_REGS (SImode)) | |
5241 | stdarg_p = 1; | |
5242 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
5243 | return; | |
5244 | } | |
5245 | ||
514066a1 RH |
5246 | if ((! TARGET_SH3E && ! TARGET_SH4) || TARGET_HITACHI) |
5247 | { | |
5248 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
5249 | return; | |
5250 | } | |
5251 | ||
5252 | f_next_o = TYPE_FIELDS (va_list_type_node); | |
5253 | f_next_o_limit = TREE_CHAIN (f_next_o); | |
5254 | f_next_fp = TREE_CHAIN (f_next_o_limit); | |
5255 | f_next_fp_limit = TREE_CHAIN (f_next_fp); | |
5256 | f_next_stack = TREE_CHAIN (f_next_fp_limit); | |
5257 | ||
5258 | next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o); | |
5259 | next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit), | |
5260 | valist, f_next_o_limit); | |
5261 | next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp); | |
5262 | next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit), | |
5263 | valist, f_next_fp_limit); | |
5264 | next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack), | |
5265 | valist, f_next_stack); | |
5266 | ||
5267 | /* Call __builtin_saveregs. */ | |
5268 | u = make_tree (ptr_type_node, expand_builtin_saveregs ()); | |
5269 | t = build (MODIFY_EXPR, ptr_type_node, next_fp, u); | |
5270 | TREE_SIDE_EFFECTS (t) = 1; | |
5271 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5272 | ||
5273 | nfp = current_function_args_info.arg_count[SH_ARG_FLOAT]; | |
5274 | if (nfp < 8) | |
5275 | nfp = 8 - nfp; | |
5276 | else | |
5277 | nfp = 0; | |
5278 | u = fold (build (PLUS_EXPR, ptr_type_node, u, | |
5279 | build_int_2 (UNITS_PER_WORD * nfp, 0))); | |
5280 | t = build (MODIFY_EXPR, ptr_type_node, next_fp_limit, u); | |
5281 | TREE_SIDE_EFFECTS (t) = 1; | |
5282 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5283 | ||
5284 | t = build (MODIFY_EXPR, ptr_type_node, next_o, u); | |
5285 | TREE_SIDE_EFFECTS (t) = 1; | |
5286 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5287 | ||
5288 | nint = current_function_args_info.arg_count[SH_ARG_INT]; | |
5289 | if (nint < 4) | |
5290 | nint = 4 - nint; | |
5291 | else | |
5292 | nint = 0; | |
5293 | u = fold (build (PLUS_EXPR, ptr_type_node, u, | |
5294 | build_int_2 (UNITS_PER_WORD * nint, 0))); | |
5295 | t = build (MODIFY_EXPR, ptr_type_node, next_o_limit, u); | |
5296 | TREE_SIDE_EFFECTS (t) = 1; | |
5297 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5298 | ||
5299 | u = make_tree (ptr_type_node, nextarg); | |
5300 | if (! stdarg_p && (nint == 0 || nfp == 0)) | |
5301 | { | |
5302 | u = fold (build (PLUS_EXPR, ptr_type_node, u, | |
5303 | build_int_2 (-UNITS_PER_WORD, -1))); | |
5304 | } | |
5305 | t = build (MODIFY_EXPR, ptr_type_node, next_stack, u); | |
5306 | TREE_SIDE_EFFECTS (t) = 1; | |
5307 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5308 | } | |
5309 | ||
5310 | /* Implement `va_arg'. */ | |
5311 | ||
5312 | rtx | |
5313 | sh_va_arg (valist, type) | |
5314 | tree valist, type; | |
5315 | { | |
5316 | HOST_WIDE_INT size, rsize; | |
318881c0 | 5317 | tree tmp, pptr_type_node; |
514066a1 | 5318 | rtx addr_rtx, r; |
5e039e6b R |
5319 | rtx result; |
5320 | int pass_by_ref = MUST_PASS_IN_STACK (TYPE_MODE (type), type); | |
514066a1 RH |
5321 | |
5322 | size = int_size_in_bytes (type); | |
5323 | rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; | |
5324 | pptr_type_node = build_pointer_type (ptr_type_node); | |
5325 | ||
5e039e6b R |
5326 | if (pass_by_ref) |
5327 | type = build_pointer_type (type); | |
5328 | ||
fa5322fa | 5329 | if (! TARGET_SH5 && (TARGET_SH3E || TARGET_SH4) && ! TARGET_HITACHI) |
514066a1 RH |
5330 | { |
5331 | tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack; | |
5332 | tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack; | |
5333 | int pass_as_float; | |
5334 | rtx lab_false, lab_over; | |
5335 | ||
5336 | f_next_o = TYPE_FIELDS (va_list_type_node); | |
5337 | f_next_o_limit = TREE_CHAIN (f_next_o); | |
5338 | f_next_fp = TREE_CHAIN (f_next_o_limit); | |
5339 | f_next_fp_limit = TREE_CHAIN (f_next_fp); | |
5340 | f_next_stack = TREE_CHAIN (f_next_fp_limit); | |
5341 | ||
5342 | next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o); | |
5343 | next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit), | |
5344 | valist, f_next_o_limit); | |
5345 | next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp), | |
5346 | valist, f_next_fp); | |
5347 | next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit), | |
5348 | valist, f_next_fp_limit); | |
5349 | next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack), | |
5350 | valist, f_next_stack); | |
5351 | ||
5352 | if (TARGET_SH4) | |
5353 | { | |
5354 | pass_as_float = ((TREE_CODE (type) == REAL_TYPE && size <= 8) | |
5355 | || (TREE_CODE (type) == COMPLEX_TYPE | |
5356 | && TREE_CODE (TREE_TYPE (type)) == REAL_TYPE | |
5357 | && size <= 16)); | |
5358 | } | |
5359 | else | |
5360 | { | |
5361 | pass_as_float = (TREE_CODE (type) == REAL_TYPE && size == 4); | |
5362 | } | |
5363 | ||
5364 | addr_rtx = gen_reg_rtx (Pmode); | |
5365 | lab_false = gen_label_rtx (); | |
5366 | lab_over = gen_label_rtx (); | |
5367 | ||
5368 | if (pass_as_float) | |
5369 | { | |
f78ec36a R |
5370 | int first_floatreg |
5371 | = current_function_args_info.arg_count[(int) SH_ARG_FLOAT]; | |
5372 | int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg); | |
5373 | ||
514066a1 RH |
5374 | emit_cmp_and_jump_insns (expand_expr (next_fp, NULL_RTX, Pmode, |
5375 | EXPAND_NORMAL), | |
5376 | expand_expr (next_fp_limit, NULL_RTX, | |
5377 | Pmode, EXPAND_NORMAL), | |
a06ef755 | 5378 | GE, const1_rtx, Pmode, 1, lab_false); |
514066a1 | 5379 | |
f78ec36a R |
5380 | if (TYPE_ALIGN (type) > BITS_PER_WORD |
5381 | || (((TREE_CODE (type) == REAL_TYPE && size == 8) || size == 16) | |
5382 | && (n_floatregs & 1))) | |
514066a1 RH |
5383 | { |
5384 | tmp = build (BIT_AND_EXPR, ptr_type_node, next_fp, | |
5385 | build_int_2 (UNITS_PER_WORD, 0)); | |
5386 | tmp = build (PLUS_EXPR, ptr_type_node, next_fp, tmp); | |
5387 | tmp = build (MODIFY_EXPR, ptr_type_node, next_fp, tmp); | |
5388 | TREE_SIDE_EFFECTS (tmp) = 1; | |
5389 | expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5390 | } | |
5391 | ||
5392 | tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp); | |
5393 | r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL); | |
5394 | if (r != addr_rtx) | |
5395 | emit_move_insn (addr_rtx, r); | |
5396 | ||
5397 | emit_jump_insn (gen_jump (lab_over)); | |
5398 | emit_barrier (); | |
5399 | emit_label (lab_false); | |
5400 | ||
5401 | tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack); | |
5402 | r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL); | |
5403 | if (r != addr_rtx) | |
5404 | emit_move_insn (addr_rtx, r); | |
5405 | } | |
5406 | else | |
5407 | { | |
5408 | tmp = build (PLUS_EXPR, ptr_type_node, next_o, | |
5409 | build_int_2 (rsize, 0)); | |
5410 | ||
5411 | emit_cmp_and_jump_insns (expand_expr (tmp, NULL_RTX, Pmode, | |
5412 | EXPAND_NORMAL), | |
5413 | expand_expr (next_o_limit, NULL_RTX, | |
5414 | Pmode, EXPAND_NORMAL), | |
a06ef755 | 5415 | GT, const1_rtx, Pmode, 1, lab_false); |
514066a1 RH |
5416 | |
5417 | tmp = build1 (ADDR_EXPR, pptr_type_node, next_o); | |
5418 | r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL); | |
5419 | if (r != addr_rtx) | |
5420 | emit_move_insn (addr_rtx, r); | |
5421 | ||
5422 | emit_jump_insn (gen_jump (lab_over)); | |
5423 | emit_barrier (); | |
5424 | emit_label (lab_false); | |
5425 | ||
5426 | if (size > 4 && ! TARGET_SH4) | |
5427 | { | |
5428 | tmp = build (MODIFY_EXPR, ptr_type_node, next_o, next_o_limit); | |
5429 | TREE_SIDE_EFFECTS (tmp) = 1; | |
5430 | expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5431 | } | |
5432 | ||
5433 | tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack); | |
5434 | r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL); | |
5435 | if (r != addr_rtx) | |
5436 | emit_move_insn (addr_rtx, r); | |
5437 | } | |
5438 | ||
5439 | emit_label (lab_over); | |
5440 | ||
5441 | tmp = make_tree (pptr_type_node, addr_rtx); | |
5442 | valist = build1 (INDIRECT_REF, ptr_type_node, tmp); | |
5443 | } | |
5444 | ||
5445 | /* ??? In va-sh.h, there had been code to make values larger than | |
5446 | size 8 indirect. This does not match the FUNCTION_ARG macros. */ | |
5447 | ||
5e039e6b R |
5448 | result = std_expand_builtin_va_arg (valist, type); |
5449 | if (pass_by_ref) | |
5450 | { | |
5451 | #ifdef POINTERS_EXTEND_UNSIGNED | |
5452 | if (GET_MODE (addr) != Pmode) | |
5453 | addr = convert_memory_address (Pmode, result); | |
5454 | #endif | |
5455 | result = gen_rtx_MEM (ptr_mode, force_reg (Pmode, result)); | |
5456 | set_mem_alias_set (result, get_varargs_alias_set ()); | |
5457 | } | |
5458 | /* ??? expand_builtin_va_arg will also set the alias set of the dereferenced | |
5459 | argument to the varargs alias set. */ | |
5460 | return result; | |
514066a1 RH |
5461 | } |
5462 | ||
0d7e008e SC |
5463 | /* Define the offset between two registers, one to be eliminated, and |
5464 | the other its replacement, at the start of a routine. */ | |
5465 | ||
5466 | int | |
5467 | initial_elimination_offset (from, to) | |
8e87e161 SC |
5468 | int from; |
5469 | int to; | |
0d7e008e SC |
5470 | { |
5471 | int regs_saved; | |
fa5322fa | 5472 | int regs_saved_rounding = 0; |
0d7e008e | 5473 | int total_saved_regs_space; |
e5f8d4c0 | 5474 | int total_auto_space; |
1245df60 | 5475 | int save_flags = target_flags; |
fa5322fa AO |
5476 | int copy_flags; |
5477 | ||
5478 | HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32]; | |
5479 | calc_live_regs (®s_saved, live_regs_mask); | |
5480 | regs_saved += SHMEDIA_REGS_STACK_ADJUST (); | |
5481 | if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT)) | |
5482 | regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT) | |
5483 | - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT)); | |
8e87e161 | 5484 | |
fa5322fa AO |
5485 | total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding; |
5486 | copy_flags = target_flags; | |
1245df60 | 5487 | target_flags = save_flags; |
1a95a963 | 5488 | |
fa5322fa | 5489 | total_saved_regs_space = regs_saved + regs_saved_rounding; |
b9654711 | 5490 | |
0d7e008e | 5491 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
fa5322fa AO |
5492 | return total_saved_regs_space + total_auto_space |
5493 | + current_function_args_info.byref_regs * 8; | |
8aa2a305 | 5494 | |
0d7e008e | 5495 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
fa5322fa AO |
5496 | return total_saved_regs_space + total_auto_space |
5497 | + current_function_args_info.byref_regs * 8; | |
8aa2a305 JW |
5498 | |
5499 | /* Initial gap between fp and sp is 0. */ | |
0d7e008e | 5500 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
8aa2a305 JW |
5501 | return 0; |
5502 | ||
2afeea0f JW |
5503 | if (from == RETURN_ADDRESS_POINTER_REGNUM |
5504 | && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM)) | |
fa5322fa AO |
5505 | if (TARGET_SH5) |
5506 | { | |
5507 | int i, n = total_saved_regs_space; | |
5508 | int align; | |
5509 | int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG; | |
5510 | ||
5511 | n += total_auto_space; | |
5512 | ||
5513 | /* If it wasn't saved, there's not much we can do. */ | |
5514 | if ((live_regs_mask[pr_reg / 32] & (1 << (pr_reg % 32))) == 0) | |
5515 | return n; | |
5516 | ||
5517 | target_flags = copy_flags; | |
5518 | ||
5519 | /* We loop twice: first, check 8-byte aligned registers, | |
5520 | that are stored in the higher addresses, that are known | |
5521 | to be aligned. Then, check 32-bit registers that don't | |
5522 | need 8-byte alignment. */ | |
5523 | for (align = 1; align >= 0; align--) | |
5524 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
5525 | if (live_regs_mask[i/32] & (1 << (i % 32))) | |
5526 | { | |
5527 | enum machine_mode mode = REGISTER_NATURAL_MODE (i); | |
5528 | ||
5529 | if (mode == SFmode && (i % 2) == 1 | |
5530 | && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i) | |
5531 | && (live_regs_mask[(i ^ 1) / 32] | |
5532 | & (1 << ((i ^ 1) % 32)))) | |
5533 | { | |
5534 | mode = DFmode; | |
5535 | i--; | |
5536 | } | |
5537 | ||
5538 | /* If we're doing the aligned pass and this is not aligned, | |
5539 | or we're doing the unaligned pass and this is aligned, | |
5540 | skip it. */ | |
5541 | if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) | |
5542 | == 0) != align) | |
5543 | continue; | |
5544 | ||
5545 | n -= GET_MODE_SIZE (mode); | |
5546 | ||
5547 | if (i == pr_reg) | |
5548 | { | |
5549 | target_flags = save_flags; | |
5550 | return n; | |
5551 | } | |
5552 | } | |
5553 | ||
5554 | abort (); | |
5555 | } | |
5556 | else | |
3007d592 | 5557 | return total_auto_space; |
2afeea0f | 5558 | |
0d7e008e SC |
5559 | abort (); |
5560 | } | |
8aa2a305 | 5561 | \f |
0d7e008e | 5562 | /* Handle machine specific pragmas to be semi-compatible with Hitachi |
16bea517 | 5563 | compiler. */ |
b9654711 | 5564 | |
8b97c5f8 ZW |
5565 | void |
5566 | sh_pr_interrupt (pfile) | |
5567 | cpp_reader *pfile ATTRIBUTE_UNUSED; | |
b9654711 | 5568 | { |
8b97c5f8 ZW |
5569 | pragma_interrupt = 1; |
5570 | } | |
05a81fe5 | 5571 | |
8b97c5f8 ZW |
5572 | void |
5573 | sh_pr_trapa (pfile) | |
5574 | cpp_reader *pfile ATTRIBUTE_UNUSED; | |
5575 | { | |
5576 | pragma_interrupt = pragma_trapa = 1; | |
5577 | } | |
05a81fe5 | 5578 | |
8b97c5f8 ZW |
5579 | void |
5580 | sh_pr_nosave_low_regs (pfile) | |
5581 | cpp_reader *pfile ATTRIBUTE_UNUSED; | |
5582 | { | |
5583 | pragma_nosave_low_regs = 1; | |
0d7e008e | 5584 | } |
157131d7 SC |
5585 | |
5586 | /* Generate 'handle_interrupt' attribute for decls */ | |
5587 | ||
12a68f1f JM |
5588 | static void |
5589 | sh_insert_attributes (node, attributes) | |
157131d7 SC |
5590 | tree node; |
5591 | tree * attributes; | |
157131d7 | 5592 | { |
157131d7 SC |
5593 | if (! pragma_interrupt |
5594 | || TREE_CODE (node) != FUNCTION_DECL) | |
5595 | return; | |
5596 | ||
5597 | /* We are only interested in fields. */ | |
5598 | if (TREE_CODE_CLASS (TREE_CODE (node)) != 'd') | |
5599 | return; | |
5600 | ||
5601 | /* Add a 'handle_interrupt' attribute. */ | |
5602 | * attributes = tree_cons (get_identifier ("interrupt_handler"), NULL, * attributes); | |
5603 | ||
5604 | return; | |
5605 | } | |
5606 | ||
91d231cb | 5607 | /* Supported attributes: |
4408efce JL |
5608 | |
5609 | interrupt_handler -- specifies this function is an interrupt handler. | |
5610 | ||
5611 | sp_switch -- specifies an alternate stack for an interrupt handler | |
5612 | to run on. | |
5613 | ||
956d6950 | 5614 | trap_exit -- use a trapa to exit an interrupt function instead of |
4408efce JL |
5615 | an rte instruction. */ |
5616 | ||
91d231cb | 5617 | const struct attribute_spec sh_attribute_table[] = |
4408efce | 5618 | { |
91d231cb JM |
5619 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
5620 | { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute }, | |
5621 | { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute }, | |
5622 | { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute }, | |
5623 | { NULL, 0, 0, false, false, false, NULL } | |
5624 | }; | |
4408efce | 5625 | |
91d231cb JM |
5626 | /* Handle an "interrupt_handler" attribute; arguments as in |
5627 | struct attribute_spec.handler. */ | |
5628 | static tree | |
5629 | sh_handle_interrupt_handler_attribute (node, name, args, flags, no_add_attrs) | |
5630 | tree *node; | |
5631 | tree name; | |
5632 | tree args ATTRIBUTE_UNUSED; | |
5633 | int flags ATTRIBUTE_UNUSED; | |
5634 | bool *no_add_attrs; | |
5635 | { | |
5636 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
4408efce | 5637 | { |
91d231cb JM |
5638 | warning ("`%s' attribute only applies to functions", |
5639 | IDENTIFIER_POINTER (name)); | |
5640 | *no_add_attrs = true; | |
4408efce JL |
5641 | } |
5642 | ||
91d231cb JM |
5643 | return NULL_TREE; |
5644 | } | |
5645 | ||
5646 | /* Handle an "sp_switch" attribute; arguments as in | |
5647 | struct attribute_spec.handler. */ | |
5648 | static tree | |
5649 | sh_handle_sp_switch_attribute (node, name, args, flags, no_add_attrs) | |
5650 | tree *node; | |
5651 | tree name; | |
5652 | tree args; | |
5653 | int flags ATTRIBUTE_UNUSED; | |
5654 | bool *no_add_attrs; | |
5655 | { | |
5656 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
5657 | { | |
5658 | warning ("`%s' attribute only applies to functions", | |
5659 | IDENTIFIER_POINTER (name)); | |
5660 | *no_add_attrs = true; | |
5661 | } | |
5662 | else if (!pragma_interrupt) | |
4408efce JL |
5663 | { |
5664 | /* The sp_switch attribute only has meaning for interrupt functions. */ | |
91d231cb JM |
5665 | warning ("`%s' attribute only applies to interrupt functions", |
5666 | IDENTIFIER_POINTER (name)); | |
5667 | *no_add_attrs = true; | |
5668 | } | |
5669 | else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST) | |
5670 | { | |
4408efce | 5671 | /* The argument must be a constant string. */ |
91d231cb JM |
5672 | warning ("`%s' attribute argument not a string constant", |
5673 | IDENTIFIER_POINTER (name)); | |
5674 | *no_add_attrs = true; | |
5675 | } | |
5676 | else | |
5677 | { | |
c5c76735 JL |
5678 | sp_switch = gen_rtx_SYMBOL_REF (VOIDmode, |
5679 | TREE_STRING_POINTER (TREE_VALUE (args))); | |
4408efce JL |
5680 | } |
5681 | ||
91d231cb JM |
5682 | return NULL_TREE; |
5683 | } | |
5684 | ||
5685 | /* Handle an "trap_exit" attribute; arguments as in | |
5686 | struct attribute_spec.handler. */ | |
5687 | static tree | |
5688 | sh_handle_trap_exit_attribute (node, name, args, flags, no_add_attrs) | |
5689 | tree *node; | |
5690 | tree name; | |
5691 | tree args; | |
5692 | int flags ATTRIBUTE_UNUSED; | |
5693 | bool *no_add_attrs; | |
5694 | { | |
5695 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
5696 | { | |
5697 | warning ("`%s' attribute only applies to functions", | |
5698 | IDENTIFIER_POINTER (name)); | |
5699 | *no_add_attrs = true; | |
5700 | } | |
5701 | else if (!pragma_interrupt) | |
4408efce JL |
5702 | { |
5703 | /* The trap_exit attribute only has meaning for interrupt functions. */ | |
91d231cb JM |
5704 | warning ("`%s' attribute only applies to interrupt functions", |
5705 | IDENTIFIER_POINTER (name)); | |
5706 | *no_add_attrs = true; | |
5707 | } | |
5708 | else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST) | |
5709 | { | |
4408efce | 5710 | /* The argument must be a constant integer. */ |
91d231cb JM |
5711 | warning ("`%s' attribute argument not an integer constant", |
5712 | IDENTIFIER_POINTER (name)); | |
5713 | *no_add_attrs = true; | |
5714 | } | |
5715 | else | |
5716 | { | |
4408efce | 5717 | trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args)); |
4408efce | 5718 | } |
318881c0 | 5719 | |
91d231cb | 5720 | return NULL_TREE; |
4408efce JL |
5721 | } |
5722 | ||
0d7e008e | 5723 | \f |
8aa2a305 | 5724 | /* Predicates used by the templates. */ |
0d7e008e | 5725 | |
8aa2a305 JW |
5726 | /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx. |
5727 | Used only in general_movsrc_operand. */ | |
0d7e008e | 5728 | |
8aa2a305 JW |
5729 | int |
5730 | system_reg_operand (op, mode) | |
5731 | rtx op; | |
318881c0 | 5732 | enum machine_mode mode ATTRIBUTE_UNUSED; |
0d7e008e | 5733 | { |
8aa2a305 | 5734 | switch (REGNO (op)) |
0d7e008e | 5735 | { |
8aa2a305 JW |
5736 | case PR_REG: |
5737 | case MACL_REG: | |
5738 | case MACH_REG: | |
5739 | return 1; | |
0d7e008e | 5740 | } |
8aa2a305 | 5741 | return 0; |
0d7e008e | 5742 | } |
0d7e008e SC |
5743 | |
5744 | /* Returns 1 if OP can be source of a simple move operation. | |
5745 | Same as general_operand, but a LABEL_REF is valid, PRE_DEC is | |
16bea517 | 5746 | invalid as are subregs of system registers. */ |
0d7e008e SC |
5747 | |
5748 | int | |
5749 | general_movsrc_operand (op, mode) | |
5750 | rtx op; | |
5751 | enum machine_mode mode; | |
5752 | { | |
06c386ea SC |
5753 | if (GET_CODE (op) == MEM) |
5754 | { | |
5755 | rtx inside = XEXP (op, 0); | |
5756 | if (GET_CODE (inside) == CONST) | |
5757 | inside = XEXP (inside, 0); | |
0d7e008e | 5758 | |
06c386ea SC |
5759 | if (GET_CODE (inside) == LABEL_REF) |
5760 | return 1; | |
8e87e161 | 5761 | |
06c386ea | 5762 | if (GET_CODE (inside) == PLUS |
8aa2a305 JW |
5763 | && GET_CODE (XEXP (inside, 0)) == LABEL_REF |
5764 | && GET_CODE (XEXP (inside, 1)) == CONST_INT) | |
06c386ea | 5765 | return 1; |
16bea517 JW |
5766 | |
5767 | /* Only post inc allowed. */ | |
97f8690b | 5768 | if (GET_CODE (inside) == PRE_DEC) |
06c386ea | 5769 | return 0; |
06c386ea | 5770 | } |
0d7e008e SC |
5771 | |
5772 | if ((mode == QImode || mode == HImode) | |
5773 | && (GET_CODE (op) == SUBREG | |
5774 | && GET_CODE (XEXP (op, 0)) == REG | |
5775 | && system_reg_operand (XEXP (op, 0), mode))) | |
5776 | return 0; | |
5777 | ||
0d7e008e | 5778 | return general_operand (op, mode); |
b9654711 SC |
5779 | } |
5780 | ||
0d7e008e SC |
5781 | /* Returns 1 if OP can be a destination of a move. |
5782 | Same as general_operand, but no preinc allowed. */ | |
5783 | ||
b9654711 | 5784 | int |
0d7e008e SC |
5785 | general_movdst_operand (op, mode) |
5786 | rtx op; | |
5787 | enum machine_mode mode; | |
b9654711 | 5788 | { |
16bea517 | 5789 | /* Only pre dec allowed. */ |
97f8690b | 5790 | if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC) |
0d7e008e | 5791 | return 0; |
d3ae8277 | 5792 | |
0d7e008e SC |
5793 | return general_operand (op, mode); |
5794 | } | |
5795 | ||
fa5322fa AO |
5796 | /* Accept a register, but not a subreg of any kind. This allows us to |
5797 | avoid pathological cases in reload wrt data movement common in | |
5798 | int->fp conversion. */ | |
5799 | ||
5800 | int | |
5801 | reg_no_subreg_operand (op, mode) | |
5802 | register rtx op; | |
5803 | enum machine_mode mode; | |
5804 | { | |
5805 | if (GET_CODE (op) == SUBREG) | |
5806 | return 0; | |
5807 | return register_operand (op, mode); | |
5808 | } | |
5809 | ||
0d7e008e SC |
5810 | /* Returns 1 if OP is a normal arithmetic register. */ |
5811 | ||
5812 | int | |
5813 | arith_reg_operand (op, mode) | |
5814 | rtx op; | |
5815 | enum machine_mode mode; | |
5816 | { | |
5817 | if (register_operand (op, mode)) | |
5818 | { | |
519164a9 JW |
5819 | int regno; |
5820 | ||
0d7e008e | 5821 | if (GET_CODE (op) == REG) |
519164a9 JW |
5822 | regno = REGNO (op); |
5823 | else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG) | |
5824 | regno = REGNO (SUBREG_REG (op)); | |
5825 | else | |
5826 | return 1; | |
5827 | ||
225e4f43 | 5828 | return (regno != T_REG && regno != PR_REG |
fa5322fa | 5829 | && ! TARGET_REGISTER_P (regno) |
225e4f43 R |
5830 | && (regno != FPUL_REG || TARGET_SH4) |
5831 | && regno != MACH_REG && regno != MACL_REG); | |
5832 | } | |
5833 | return 0; | |
5834 | } | |
5835 | ||
5836 | int | |
5837 | fp_arith_reg_operand (op, mode) | |
5838 | rtx op; | |
5839 | enum machine_mode mode; | |
5840 | { | |
5841 | if (register_operand (op, mode)) | |
5842 | { | |
5843 | int regno; | |
5844 | ||
5845 | if (GET_CODE (op) == REG) | |
5846 | regno = REGNO (op); | |
5847 | else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG) | |
5848 | regno = REGNO (SUBREG_REG (op)); | |
5849 | else | |
5850 | return 1; | |
5851 | ||
66c0b347 | 5852 | return (regno >= FIRST_PSEUDO_REGISTER |
104ee20b | 5853 | || FP_REGISTER_P (regno)); |
0d7e008e SC |
5854 | } |
5855 | return 0; | |
5856 | } | |
5857 | ||
0d7e008e SC |
5858 | /* Returns 1 if OP is a valid source operand for an arithmetic insn. */ |
5859 | ||
5860 | int | |
5861 | arith_operand (op, mode) | |
5862 | rtx op; | |
5863 | enum machine_mode mode; | |
5864 | { | |
5865 | if (arith_reg_operand (op, mode)) | |
5866 | return 1; | |
5867 | ||
fa5322fa AO |
5868 | if (TARGET_SHMEDIA) |
5869 | { | |
5870 | /* FIXME: We should be checking whether the CONST_INT fits in a | |
5871 | CONST_OK_FOR_J here, but this causes reload_cse to crash when | |
5872 | attempting to transform a sequence of two 64-bit sets of the | |
5873 | same register from literal constants into a set and an add, | |
5874 | when the difference is too wide for an add. */ | |
5875 | if (GET_CODE (op) == CONST_INT | |
5876 | || EXTRA_CONSTRAINT_S (op)) | |
5877 | return 1; | |
5878 | else | |
5879 | return 0; | |
5880 | } | |
5881 | else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op))) | |
8aa2a305 JW |
5882 | return 1; |
5883 | ||
0d7e008e SC |
5884 | return 0; |
5885 | } | |
5886 | ||
22e1ebf1 JW |
5887 | /* Returns 1 if OP is a valid source operand for a compare insn. */ |
5888 | ||
5889 | int | |
5890 | arith_reg_or_0_operand (op, mode) | |
5891 | rtx op; | |
5892 | enum machine_mode mode; | |
5893 | { | |
5894 | if (arith_reg_operand (op, mode)) | |
5895 | return 1; | |
5896 | ||
8aa2a305 JW |
5897 | if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_N (INTVAL (op))) |
5898 | return 1; | |
5899 | ||
22e1ebf1 JW |
5900 | return 0; |
5901 | } | |
5902 | ||
fa5322fa AO |
5903 | /* Return 1 if OP is a valid source operand for an SHmedia operation |
5904 | that takes either a register or a 6-bit immediate. */ | |
5905 | ||
5906 | int | |
5907 | shmedia_6bit_operand (op, mode) | |
5908 | rtx op; | |
5909 | enum machine_mode mode; | |
5910 | { | |
5911 | return (arith_reg_operand (op, mode) | |
5912 | || (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op)))); | |
5913 | } | |
5914 | ||
16bea517 | 5915 | /* Returns 1 if OP is a valid source operand for a logical operation. */ |
0d7e008e SC |
5916 | |
5917 | int | |
5918 | logical_operand (op, mode) | |
5919 | rtx op; | |
5920 | enum machine_mode mode; | |
5921 | { | |
5922 | if (arith_reg_operand (op, mode)) | |
5923 | return 1; | |
5924 | ||
fa5322fa AO |
5925 | if (TARGET_SHMEDIA) |
5926 | { | |
5927 | if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_P (INTVAL (op))) | |
5928 | return 1; | |
5929 | else | |
5930 | return 0; | |
5931 | } | |
5932 | else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op))) | |
8aa2a305 JW |
5933 | return 1; |
5934 | ||
0d7e008e | 5935 | return 0; |
b9654711 | 5936 | } |
d3ae8277 | 5937 | |
1a95a963 JW |
5938 | /* Nonzero if OP is a floating point value with value 0.0. */ |
5939 | ||
5940 | int | |
5941 | fp_zero_operand (op) | |
5942 | rtx op; | |
d3ae8277 | 5943 | { |
1a95a963 | 5944 | REAL_VALUE_TYPE r; |
d3ae8277 | 5945 | |
1a95a963 JW |
5946 | if (GET_MODE (op) != SFmode) |
5947 | return 0; | |
5948 | ||
5949 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
e4fa6b06 | 5950 | return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r); |
d3ae8277 SC |
5951 | } |
5952 | ||
1a95a963 | 5953 | /* Nonzero if OP is a floating point value with value 1.0. */ |
d3ae8277 SC |
5954 | |
5955 | int | |
1a95a963 JW |
5956 | fp_one_operand (op) |
5957 | rtx op; | |
d3ae8277 | 5958 | { |
1a95a963 JW |
5959 | REAL_VALUE_TYPE r; |
5960 | ||
5961 | if (GET_MODE (op) != SFmode) | |
5962 | return 0; | |
5963 | ||
5964 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
5965 | return REAL_VALUES_EQUAL (r, dconst1); | |
d3ae8277 | 5966 | } |
1245df60 | 5967 | |
9f09b1f2 R |
5968 | /* For -m4 and -m4-single-only, mode switching is used. If we are |
5969 | compiling without -mfmovd, movsf_ie isn't taken into account for | |
5970 | mode switching. We could check in machine_dependent_reorg for | |
5971 | cases where we know we are in single precision mode, but there is | |
5972 | interface to find that out during reload, so we must avoid | |
5973 | choosing an fldi alternative during reload and thus failing to | |
5974 | allocate a scratch register for the constant loading. */ | |
5975 | int | |
5976 | fldi_ok () | |
5977 | { | |
5978 | return ! TARGET_SH4 || TARGET_FMOVD || reload_completed; | |
5979 | } | |
5980 | ||
225e4f43 R |
5981 | int |
5982 | tertiary_reload_operand (op, mode) | |
5983 | rtx op; | |
318881c0 | 5984 | enum machine_mode mode ATTRIBUTE_UNUSED; |
225e4f43 R |
5985 | { |
5986 | enum rtx_code code = GET_CODE (op); | |
5987 | return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE); | |
5988 | } | |
5989 | ||
5990 | int | |
318881c0 | 5991 | fpscr_operand (op, mode) |
225e4f43 | 5992 | rtx op; |
318881c0 | 5993 | enum machine_mode mode ATTRIBUTE_UNUSED; |
225e4f43 R |
5994 | { |
5995 | return (GET_CODE (op) == REG && REGNO (op) == FPSCR_REG | |
5996 | && GET_MODE (op) == PSImode); | |
5997 | } | |
5998 | ||
4b9580a5 R |
5999 | int |
6000 | fpul_operand (op, mode) | |
6001 | rtx op; | |
975d393a | 6002 | enum machine_mode mode; |
4b9580a5 | 6003 | { |
fa5322fa AO |
6004 | if (TARGET_SHMEDIA) |
6005 | return fp_arith_reg_operand (op, mode); | |
6006 | ||
4b9580a5 R |
6007 | return (GET_CODE (op) == REG |
6008 | && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
6009 | && GET_MODE (op) == mode); | |
6010 | } | |
6011 | ||
2d01e445 AO |
6012 | int |
6013 | symbol_ref_operand (op, mode) | |
6014 | rtx op; | |
6015 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
6016 | { | |
6017 | return (GET_CODE (op) == SYMBOL_REF); | |
6018 | } | |
6019 | ||
225e4f43 R |
6020 | int |
6021 | commutative_float_operator (op, mode) | |
6022 | rtx op; | |
6023 | enum machine_mode mode; | |
6024 | { | |
6025 | if (GET_MODE (op) != mode) | |
6026 | return 0; | |
6027 | switch (GET_CODE (op)) | |
6028 | { | |
6029 | case PLUS: | |
6030 | case MULT: | |
6031 | return 1; | |
318881c0 KG |
6032 | default: |
6033 | break; | |
225e4f43 R |
6034 | } |
6035 | return 0; | |
6036 | } | |
6037 | ||
6038 | int | |
6039 | noncommutative_float_operator (op, mode) | |
6040 | rtx op; | |
6041 | enum machine_mode mode; | |
6042 | { | |
6043 | if (GET_MODE (op) != mode) | |
6044 | return 0; | |
6045 | switch (GET_CODE (op)) | |
6046 | { | |
6047 | case MINUS: | |
6048 | case DIV: | |
6049 | return 1; | |
318881c0 KG |
6050 | default: |
6051 | break; | |
225e4f43 R |
6052 | } |
6053 | return 0; | |
6054 | } | |
6055 | ||
6056 | int | |
6057 | binary_float_operator (op, mode) | |
6058 | rtx op; | |
6059 | enum machine_mode mode; | |
6060 | { | |
6061 | if (GET_MODE (op) != mode) | |
6062 | return 0; | |
6063 | switch (GET_CODE (op)) | |
6064 | { | |
6065 | case PLUS: | |
6066 | case MINUS: | |
6067 | case MULT: | |
6068 | case DIV: | |
6069 | return 1; | |
318881c0 KG |
6070 | default: |
6071 | break; | |
225e4f43 R |
6072 | } |
6073 | return 0; | |
6074 | } | |
fa5322fa AO |
6075 | |
6076 | /* Accept pseudos and branch target registers. */ | |
6077 | int | |
6078 | target_reg_operand (op, mode) | |
6079 | rtx op; | |
6080 | enum machine_mode mode; | |
6081 | { | |
6082 | if (mode != DImode | |
6083 | || GET_MODE (op) != DImode) | |
6084 | return 0; | |
6085 | ||
6086 | if (GET_CODE (op) == SUBREG) | |
6087 | op = XEXP (op, 0); | |
6088 | ||
6089 | if (GET_CODE (op) != REG) | |
6090 | return 0; | |
6091 | ||
6092 | /* We must protect ourselves from matching pseudos that are virtual | |
6093 | register, because they will eventually be replaced with hardware | |
6094 | registers that aren't branch-target registers. */ | |
6095 | if (REGNO (op) > LAST_VIRTUAL_REGISTER | |
6096 | || TARGET_REGISTER_P (REGNO (op))) | |
6097 | return 1; | |
6098 | ||
6099 | return 0; | |
6100 | } | |
6101 | ||
6102 | /* Same as target_reg_operand, except that label_refs and symbol_refs | |
6103 | are accepted before reload. */ | |
6104 | int | |
6105 | target_operand (op, mode) | |
6106 | rtx op; | |
6107 | enum machine_mode mode; | |
6108 | { | |
6109 | if (mode != DImode) | |
6110 | return 0; | |
6111 | ||
6112 | if ((GET_MODE (op) == DImode || GET_MODE (op) == VOIDmode) | |
6113 | && EXTRA_CONSTRAINT_T (op)) | |
6114 | return ! reload_completed; | |
6115 | ||
6116 | return target_reg_operand (op, mode); | |
6117 | } | |
6118 | ||
1245df60 | 6119 | \f |
33f7f353 | 6120 | /* Return the destination address of a branch. */ |
1245df60 | 6121 | |
318881c0 | 6122 | static int |
33f7f353 | 6123 | branch_dest (branch) |
1245df60 R |
6124 | rtx branch; |
6125 | { | |
33f7f353 JR |
6126 | rtx dest = SET_SRC (PATTERN (branch)); |
6127 | int dest_uid; | |
1245df60 R |
6128 | |
6129 | if (GET_CODE (dest) == IF_THEN_ELSE) | |
6130 | dest = XEXP (dest, 1); | |
6131 | dest = XEXP (dest, 0); | |
6132 | dest_uid = INSN_UID (dest); | |
9d98a694 | 6133 | return INSN_ADDRESSES (dest_uid); |
1245df60 | 6134 | } |
a55e9d2b RK |
6135 | \f |
6136 | /* Return non-zero if REG is not used after INSN. | |
6137 | We assume REG is a reload reg, and therefore does | |
8b760293 | 6138 | not live past labels. It may live past calls or jumps though. */ |
a55e9d2b RK |
6139 | int |
6140 | reg_unused_after (reg, insn) | |
6141 | rtx reg; | |
6142 | rtx insn; | |
6143 | { | |
8783b15e | 6144 | enum rtx_code code; |
a55e9d2b RK |
6145 | rtx set; |
6146 | ||
6147 | /* If the reg is set by this instruction, then it is safe for our | |
6148 | case. Disregard the case where this is a store to memory, since | |
6149 | we are checking a register used in the store address. */ | |
6150 | set = single_set (insn); | |
6151 | if (set && GET_CODE (SET_DEST (set)) != MEM | |
6152 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
6153 | return 1; | |
6154 | ||
318881c0 | 6155 | while ((insn = NEXT_INSN (insn))) |
a55e9d2b | 6156 | { |
a55e9d2b | 6157 | code = GET_CODE (insn); |
8783b15e | 6158 | |
c8f6f18d RK |
6159 | #if 0 |
6160 | /* If this is a label that existed before reload, then the register | |
6161 | if dead here. However, if this is a label added by reorg, then | |
6162 | the register may still be live here. We can't tell the difference, | |
6163 | so we just ignore labels completely. */ | |
8783b15e | 6164 | if (code == CODE_LABEL) |
a55e9d2b | 6165 | return 1; |
c8f6f18d RK |
6166 | /* else */ |
6167 | #endif | |
a55e9d2b | 6168 | |
8b760293 JW |
6169 | if (code == JUMP_INSN) |
6170 | return 0; | |
6171 | ||
8783b15e RK |
6172 | /* If this is a sequence, we must handle them all at once. |
6173 | We could have for instance a call that sets the target register, | |
e03f5d43 | 6174 | and an insn in a delay slot that uses the register. In this case, |
8783b15e | 6175 | we must return 0. */ |
8b760293 | 6176 | else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) |
a55e9d2b | 6177 | { |
8783b15e RK |
6178 | int i; |
6179 | int retval = 0; | |
6180 | ||
6181 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
6182 | { | |
6183 | rtx this_insn = XVECEXP (PATTERN (insn), 0, i); | |
6184 | rtx set = single_set (this_insn); | |
6185 | ||
6186 | if (GET_CODE (this_insn) == CALL_INSN) | |
6187 | code = CALL_INSN; | |
38f35781 JW |
6188 | else if (GET_CODE (this_insn) == JUMP_INSN) |
6189 | { | |
6190 | if (INSN_ANNULLED_BRANCH_P (this_insn)) | |
6191 | return 0; | |
6192 | code = JUMP_INSN; | |
6193 | } | |
a55e9d2b | 6194 | |
8783b15e RK |
6195 | if (set && reg_overlap_mentioned_p (reg, SET_SRC (set))) |
6196 | return 0; | |
6197 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
6198 | { | |
6199 | if (GET_CODE (SET_DEST (set)) != MEM) | |
6200 | retval = 1; | |
6201 | else | |
6202 | return 0; | |
6203 | } | |
6204 | if (set == 0 | |
6205 | && reg_overlap_mentioned_p (reg, PATTERN (this_insn))) | |
6206 | return 0; | |
6207 | } | |
6208 | if (retval == 1) | |
6209 | return 1; | |
38f35781 JW |
6210 | else if (code == JUMP_INSN) |
6211 | return 0; | |
8783b15e RK |
6212 | } |
6213 | else if (GET_RTX_CLASS (code) == 'i') | |
a55e9d2b RK |
6214 | { |
6215 | rtx set = single_set (insn); | |
6216 | ||
6217 | if (set && reg_overlap_mentioned_p (reg, SET_SRC (set))) | |
6218 | return 0; | |
6219 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
6220 | return GET_CODE (SET_DEST (set)) != MEM; | |
6221 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
6222 | return 0; | |
6223 | } | |
8783b15e RK |
6224 | |
6225 | if (code == CALL_INSN && call_used_regs[REGNO (reg)]) | |
6226 | return 1; | |
a55e9d2b RK |
6227 | } |
6228 | return 1; | |
6229 | } | |
225e4f43 | 6230 | \f |
c5b9ef02 | 6231 | #include "ggc.h" |
225e4f43 | 6232 | |
e2500fed | 6233 | static GTY(()) rtx fpscr_rtx; |
225e4f43 R |
6234 | rtx |
6235 | get_fpscr_rtx () | |
6236 | { | |
225e4f43 R |
6237 | if (! fpscr_rtx) |
6238 | { | |
4773afa4 | 6239 | fpscr_rtx = gen_rtx (REG, PSImode, FPSCR_REG); |
225e4f43 | 6240 | REG_USERVAR_P (fpscr_rtx) = 1; |
225e4f43 R |
6241 | mark_user_reg (fpscr_rtx); |
6242 | } | |
6243 | if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG) | |
6244 | mark_user_reg (fpscr_rtx); | |
6245 | return fpscr_rtx; | |
6246 | } | |
6247 | ||
6248 | void | |
6249 | emit_sf_insn (pat) | |
6250 | rtx pat; | |
6251 | { | |
225e4f43 | 6252 | emit_insn (pat); |
225e4f43 R |
6253 | } |
6254 | ||
6255 | void | |
6256 | emit_df_insn (pat) | |
6257 | rtx pat; | |
6258 | { | |
225e4f43 | 6259 | emit_insn (pat); |
225e4f43 R |
6260 | } |
6261 | ||
6262 | void | |
6263 | expand_sf_unop (fun, operands) | |
318881c0 | 6264 | rtx (*fun) PARAMS ((rtx, rtx, rtx)); |
225e4f43 R |
6265 | rtx *operands; |
6266 | { | |
6267 | emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ())); | |
6268 | } | |
6269 | ||
6270 | void | |
6271 | expand_sf_binop (fun, operands) | |
318881c0 | 6272 | rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx)); |
225e4f43 R |
6273 | rtx *operands; |
6274 | { | |
6275 | emit_sf_insn ((*fun) (operands[0], operands[1], operands[2], | |
6276 | get_fpscr_rtx ())); | |
6277 | } | |
6278 | ||
6279 | void | |
6280 | expand_df_unop (fun, operands) | |
318881c0 | 6281 | rtx (*fun) PARAMS ((rtx, rtx, rtx)); |
225e4f43 R |
6282 | rtx *operands; |
6283 | { | |
6284 | emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ())); | |
6285 | } | |
6286 | ||
6287 | void | |
6288 | expand_df_binop (fun, operands) | |
318881c0 | 6289 | rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx)); |
225e4f43 R |
6290 | rtx *operands; |
6291 | { | |
6292 | emit_df_insn ((*fun) (operands[0], operands[1], operands[2], | |
6293 | get_fpscr_rtx ())); | |
6294 | } | |
225e4f43 R |
6295 | \f |
6296 | /* ??? gcc does flow analysis strictly after common subexpression | |
6297 | elimination. As a result, common subespression elimination fails | |
6298 | when there are some intervening statements setting the same register. | |
6299 | If we did nothing about this, this would hurt the precision switching | |
6300 | for SH4 badly. There is some cse after reload, but it is unable to | |
6301 | undo the extra register pressure from the unused instructions, and | |
6302 | it cannot remove auto-increment loads. | |
6303 | ||
6304 | A C code example that shows this flow/cse weakness for (at least) SH | |
6305 | and sparc (as of gcc ss-970706) is this: | |
6306 | ||
6307 | double | |
6308 | f(double a) | |
6309 | { | |
6310 | double d; | |
6311 | d = 0.1; | |
6312 | a += d; | |
6313 | d = 1.1; | |
6314 | d = 0.1; | |
6315 | a *= d; | |
6316 | return a; | |
6317 | } | |
6318 | ||
6319 | So we add another pass before common subexpression elimination, to | |
6320 | remove assignments that are dead due to a following assignment in the | |
6321 | same basic block. */ | |
6322 | ||
225e4f43 R |
6323 | static void |
6324 | mark_use (x, reg_set_block) | |
6325 | rtx x, *reg_set_block; | |
6326 | { | |
6327 | enum rtx_code code; | |
6328 | ||
6329 | if (! x) | |
6330 | return; | |
6331 | code = GET_CODE (x); | |
6332 | switch (code) | |
6333 | { | |
6334 | case REG: | |
6335 | { | |
6336 | int regno = REGNO (x); | |
6337 | int nregs = (regno < FIRST_PSEUDO_REGISTER | |
6338 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) | |
6339 | : 1); | |
6340 | do | |
6341 | { | |
6342 | reg_set_block[regno + nregs - 1] = 0; | |
6343 | } | |
6344 | while (--nregs); | |
6345 | break; | |
6346 | } | |
6347 | case SET: | |
6348 | { | |
6349 | rtx dest = SET_DEST (x); | |
6350 | ||
6351 | if (GET_CODE (dest) == SUBREG) | |
6352 | dest = SUBREG_REG (dest); | |
6353 | if (GET_CODE (dest) != REG) | |
6354 | mark_use (dest, reg_set_block); | |
6355 | mark_use (SET_SRC (x), reg_set_block); | |
6356 | break; | |
6357 | } | |
6358 | case CLOBBER: | |
6359 | break; | |
6360 | default: | |
6361 | { | |
6f7d635c | 6362 | const char *fmt = GET_RTX_FORMAT (code); |
225e4f43 R |
6363 | int i, j; |
6364 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6365 | { | |
6366 | if (fmt[i] == 'e') | |
6367 | mark_use (XEXP (x, i), reg_set_block); | |
6368 | else if (fmt[i] == 'E') | |
6369 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
6370 | mark_use (XVECEXP (x, i, j), reg_set_block); | |
6371 | } | |
6372 | break; | |
6373 | } | |
6374 | } | |
6375 | } | |
9f09b1f2 R |
6376 | \f |
6377 | static rtx get_free_reg PARAMS ((HARD_REG_SET)); | |
6378 | ||
6379 | /* This function returns a register to use to load the address to load | |
6380 | the fpscr from. Currently it always returns r1 or r7, but when we are | |
6381 | able to use pseudo registers after combine, or have a better mechanism | |
6382 | for choosing a register, it should be done here. */ | |
6383 | /* REGS_LIVE is the liveness information for the point for which we | |
6384 | need this allocation. In some bare-bones exit blocks, r1 is live at the | |
6385 | start. We can even have all of r0..r3 being live: | |
6386 | __complex__ long long f (double d) { if (d == 0) return 2; else return 3; } | |
6387 | INSN before which new insns are placed with will clobber the register | |
6388 | we return. If a basic block consists only of setting the return value | |
6389 | register to a pseudo and using that register, the return value is not | |
6390 | live before or after this block, yet we we'll insert our insns right in | |
6391 | the middle. */ | |
225e4f43 | 6392 | |
9f09b1f2 R |
6393 | static rtx |
6394 | get_free_reg (regs_live) | |
6395 | HARD_REG_SET regs_live; | |
225e4f43 | 6396 | { |
9f09b1f2 R |
6397 | if (! TEST_HARD_REG_BIT (regs_live, 1)) |
6398 | return gen_rtx_REG (Pmode, 1); | |
225e4f43 | 6399 | |
9f09b1f2 R |
6400 | /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target, |
6401 | there shouldn't be anything but a jump before the function end. */ | |
6402 | if (! TEST_HARD_REG_BIT (regs_live, 7)) | |
6403 | return gen_rtx_REG (Pmode, 7); | |
225e4f43 | 6404 | |
9f09b1f2 R |
6405 | abort (); |
6406 | } | |
225e4f43 | 6407 | |
9f09b1f2 R |
6408 | /* This function will set the fpscr from memory. |
6409 | MODE is the mode we are setting it to. */ | |
6410 | void | |
6411 | fpscr_set_from_mem (mode, regs_live) | |
6412 | int mode; | |
6413 | HARD_REG_SET regs_live; | |
6414 | { | |
6415 | enum attr_fp_mode fp_mode = mode; | |
9f09b1f2 R |
6416 | rtx addr_reg = get_free_reg (regs_live); |
6417 | ||
c5b9ef02 AO |
6418 | if (fp_mode == (enum attr_fp_mode) NORMAL_MODE (FP_MODE)) |
6419 | emit_insn (gen_fpu_switch1 (addr_reg)); | |
6420 | else | |
6421 | emit_insn (gen_fpu_switch0 (addr_reg)); | |
225e4f43 | 6422 | } |
9342c0c4 R |
6423 | |
6424 | /* Is the given character a logical line separator for the assembler? */ | |
6425 | #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR | |
6426 | #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';') | |
6427 | #endif | |
6428 | ||
6429 | int | |
6430 | sh_insn_length_adjustment (insn) | |
6431 | rtx insn; | |
6432 | { | |
6433 | /* Instructions with unfilled delay slots take up an extra two bytes for | |
6434 | the nop in the delay slot. */ | |
6435 | if (((GET_CODE (insn) == INSN | |
6436 | && GET_CODE (PATTERN (insn)) != USE | |
6437 | && GET_CODE (PATTERN (insn)) != CLOBBER) | |
6438 | || GET_CODE (insn) == CALL_INSN | |
6439 | || (GET_CODE (insn) == JUMP_INSN | |
6440 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
6441 | && GET_CODE (PATTERN (insn)) != ADDR_VEC)) | |
6442 | && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE | |
6443 | && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES) | |
6444 | return 2; | |
6445 | ||
6446 | /* sh-dsp parallel processing insn take four bytes instead of two. */ | |
6447 | ||
6448 | if (GET_CODE (insn) == INSN) | |
6449 | { | |
6450 | int sum = 0; | |
6451 | rtx body = PATTERN (insn); | |
8ceaac3c CP |
6452 | const char *template; |
6453 | char c; | |
9342c0c4 R |
6454 | int maybe_label = 1; |
6455 | ||
6456 | if (GET_CODE (body) == ASM_INPUT) | |
6457 | template = XSTR (body, 0); | |
6458 | else if (asm_noperands (body) >= 0) | |
6459 | template | |
df4ae160 | 6460 | = decode_asm_operands (body, NULL, NULL, NULL, NULL); |
9342c0c4 R |
6461 | else |
6462 | return 0; | |
6463 | do | |
6464 | { | |
6465 | int ppi_adjust = 0; | |
6466 | ||
6467 | do | |
6468 | c = *template++; | |
6469 | while (c == ' ' || c == '\t'); | |
6470 | /* all sh-dsp parallel-processing insns start with p. | |
6471 | The only non-ppi sh insn starting with p is pref. | |
6472 | The only ppi starting with pr is prnd. */ | |
6473 | if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2)) | |
6474 | ppi_adjust = 2; | |
6475 | /* The repeat pseudo-insn expands two three insns, a total of | |
6476 | six bytes in size. */ | |
6477 | else if ((c == 'r' || c == 'R') | |
6478 | && ! strncasecmp ("epeat", template, 5)) | |
6479 | ppi_adjust = 4; | |
6480 | while (c && c != '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c)) | |
6481 | { | |
6482 | /* If this is a label, it is obviously not a ppi insn. */ | |
6483 | if (c == ':' && maybe_label) | |
6484 | { | |
6485 | ppi_adjust = 0; | |
6486 | break; | |
6487 | } | |
6488 | else if (c == '\'' || c == '"') | |
6489 | maybe_label = 0; | |
6490 | c = *template++; | |
6491 | } | |
6492 | sum += ppi_adjust; | |
6493 | maybe_label = c != ':'; | |
6494 | } | |
6495 | while (c); | |
6496 | return sum; | |
6497 | } | |
6498 | return 0; | |
6499 | } | |
1a66cd67 | 6500 | \f |
55eec660 AO |
6501 | /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol |
6502 | isn't protected by a PIC unspec. */ | |
1a66cd67 AO |
6503 | int |
6504 | nonpic_symbol_mentioned_p (x) | |
6505 | rtx x; | |
6506 | { | |
6507 | register const char *fmt; | |
6508 | register int i; | |
6509 | ||
fa5322fa AO |
6510 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF |
6511 | || GET_CODE (x) == PC) | |
1a66cd67 AO |
6512 | return 1; |
6513 | ||
fa5322fa AO |
6514 | /* We don't want to look into the possible MEM location of a |
6515 | CONST_DOUBLE, since we're not going to use it, in general. */ | |
6516 | if (GET_CODE (x) == CONST_DOUBLE) | |
6517 | return 0; | |
6518 | ||
1a66cd67 | 6519 | if (GET_CODE (x) == UNSPEC |
4773afa4 AO |
6520 | && (XINT (x, 1) == UNSPEC_PIC |
6521 | || XINT (x, 1) == UNSPEC_GOT | |
6522 | || XINT (x, 1) == UNSPEC_GOTOFF | |
fa5322fa | 6523 | || XINT (x, 1) == UNSPEC_GOTPLT |
4773afa4 | 6524 | || XINT (x, 1) == UNSPEC_PLT)) |
1a66cd67 AO |
6525 | return 0; |
6526 | ||
6527 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
6528 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
6529 | { | |
6530 | if (fmt[i] == 'E') | |
6531 | { | |
6532 | register int j; | |
6533 | ||
6534 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
6535 | if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j))) | |
6536 | return 1; | |
6537 | } | |
6538 | else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i))) | |
6539 | return 1; | |
6540 | } | |
6541 | ||
6542 | return 0; | |
6543 | } | |
6544 | ||
6545 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or | |
6f317ef3 | 6546 | @GOTOFF in `reg'. */ |
1a66cd67 AO |
6547 | rtx |
6548 | legitimize_pic_address (orig, mode, reg) | |
6549 | rtx orig; | |
c5b9ef02 | 6550 | enum machine_mode mode ATTRIBUTE_UNUSED; |
1a66cd67 AO |
6551 | rtx reg; |
6552 | { | |
6553 | if (GET_CODE (orig) == LABEL_REF | |
6554 | || (GET_CODE (orig) == SYMBOL_REF | |
6555 | && (CONSTANT_POOL_ADDRESS_P (orig) | |
6556 | /* SYMBOL_REF_FLAG is set on static symbols. */ | |
6557 | || SYMBOL_REF_FLAG (orig)))) | |
6558 | { | |
6559 | if (reg == 0) | |
6560 | reg = gen_reg_rtx (Pmode); | |
6561 | ||
6562 | emit_insn (gen_symGOTOFF2reg (reg, orig)); | |
6563 | return reg; | |
6564 | } | |
6565 | else if (GET_CODE (orig) == SYMBOL_REF) | |
6566 | { | |
6567 | if (reg == 0) | |
6568 | reg = gen_reg_rtx (Pmode); | |
6569 | ||
6570 | emit_insn (gen_symGOT2reg (reg, orig)); | |
6571 | return reg; | |
6572 | } | |
6573 | return orig; | |
6574 | } | |
b91455de KK |
6575 | |
6576 | /* Mark the use of a constant in the literal table. If the constant | |
6577 | has multiple labels, make it unique. */ | |
6578 | static rtx mark_constant_pool_use (x) | |
6579 | rtx x; | |
6580 | { | |
6581 | rtx insn, lab, pattern; | |
6582 | ||
6583 | if (x == NULL) | |
6584 | return x; | |
6585 | ||
6586 | switch (GET_CODE (x)) | |
6587 | { | |
6588 | case LABEL_REF: | |
6589 | x = XEXP (x, 0); | |
6590 | case CODE_LABEL: | |
6591 | break; | |
6592 | default: | |
6593 | return x; | |
6594 | } | |
6595 | ||
6596 | /* Get the first label in the list of labels for the same constant | |
6597 | and delete another labels in the list. */ | |
6598 | lab = x; | |
6599 | for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn)) | |
6600 | { | |
6601 | if (GET_CODE (insn) != CODE_LABEL | |
6602 | || LABEL_REFS (insn) != NEXT_INSN (insn)) | |
6603 | break; | |
6604 | lab = insn; | |
6605 | } | |
6606 | ||
6607 | for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn)) | |
6608 | INSN_DELETED_P (insn) = 1; | |
6609 | ||
6610 | /* Mark constants in a window. */ | |
6611 | for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn)) | |
6612 | { | |
6613 | if (GET_CODE (insn) != INSN) | |
6614 | continue; | |
6615 | ||
6616 | pattern = PATTERN (insn); | |
6617 | if (GET_CODE (pattern) != UNSPEC_VOLATILE) | |
6618 | continue; | |
6619 | ||
6620 | switch (XINT (pattern, 1)) | |
6621 | { | |
6622 | case UNSPECV_CONST2: | |
6623 | case UNSPECV_CONST4: | |
6624 | case UNSPECV_CONST8: | |
6625 | XVECEXP (pattern, 0, 1) = const1_rtx; | |
6626 | break; | |
6627 | case UNSPECV_WINDOW_END: | |
6628 | if (XVECEXP (pattern, 0, 0) == x) | |
6629 | return lab; | |
6630 | break; | |
6631 | case UNSPECV_CONST_END: | |
6632 | return lab; | |
6633 | default: | |
6634 | break; | |
6635 | } | |
6636 | } | |
6637 | ||
6638 | return lab; | |
6639 | } | |
6e7b03e1 AH |
6640 | \f |
6641 | /* Return true if it's possible to redirect BRANCH1 to the destination | |
6642 | of an unconditional jump BRANCH2. We only want to do this if the | |
6643 | resulting branch will have a short displacement. */ | |
6644 | int | |
6645 | sh_can_redirect_branch (branch1, branch2) | |
6646 | rtx branch1; | |
6647 | rtx branch2; | |
6648 | { | |
6649 | if (flag_expensive_optimizations && simplejump_p (branch2)) | |
6650 | { | |
6651 | rtx dest = XEXP (SET_SRC (single_set (branch2)), 0); | |
6652 | rtx insn; | |
6653 | int distance; | |
6654 | ||
6655 | for (distance = 0, insn = NEXT_INSN (branch1); | |
6656 | insn && distance < 256; | |
6657 | insn = PREV_INSN (insn)) | |
6658 | { | |
6659 | if (insn == dest) | |
6660 | return 1; | |
6661 | else | |
6662 | distance += get_attr_length (insn); | |
6663 | } | |
6664 | for (distance = 0, insn = NEXT_INSN (branch1); | |
6665 | insn && distance < 256; | |
6666 | insn = NEXT_INSN (insn)) | |
6667 | { | |
6668 | if (insn == dest) | |
6669 | return 1; | |
6670 | else | |
6671 | distance += get_attr_length (insn); | |
6672 | } | |
6673 | } | |
6674 | return 0; | |
6675 | } | |
6676 | ||
c237e94a ZW |
6677 | /* A C statement (sans semicolon) to update the integer variable COST |
6678 | based on the relationship between INSN that is dependent on | |
6679 | DEP_INSN through the dependence LINK. The default is to make no | |
6680 | adjustment to COST. This can be used for example to specify to | |
6681 | the scheduler that an output- or anti-dependence does not incur | |
6682 | the same cost as a data-dependence. */ | |
6683 | static int | |
6684 | sh_adjust_cost (insn, link, dep_insn, cost) | |
6685 | rtx insn; | |
55710451 | 6686 | rtx link ATTRIBUTE_UNUSED; |
c237e94a ZW |
6687 | rtx dep_insn; |
6688 | int cost; | |
6689 | { | |
6690 | rtx reg; | |
6691 | ||
6692 | if (GET_CODE(insn) == CALL_INSN) | |
6693 | { | |
6694 | /* The only input for a call that is timing-critical is the | |
6695 | function's address. */ | |
6696 | rtx call = PATTERN (insn); | |
6697 | ||
6698 | if (GET_CODE (call) == PARALLEL) | |
6699 | call = XVECEXP (call, 0 ,0); | |
6700 | if (GET_CODE (call) == SET) | |
6701 | call = SET_SRC (call); | |
6702 | if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM | |
6703 | && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)) | |
6704 | cost = 0; | |
6705 | } | |
6706 | /* All sfunc calls are parallels with at least four components. | |
6707 | Exploit this to avoid unnecessary calls to sfunc_uses_reg. */ | |
6708 | else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
6709 | && XVECLEN (PATTERN (insn), 0) >= 4 | |
6710 | && (reg = sfunc_uses_reg (insn))) | |
6711 | { | |
6712 | /* Likewise, the most timing critical input for an sfuncs call | |
6713 | is the function address. However, sfuncs typically start | |
6714 | using their arguments pretty quickly. | |
6715 | Assume a four cycle delay before they are needed. */ | |
6716 | if (! reg_set_p (reg, dep_insn)) | |
6717 | cost -= TARGET_SUPERSCALAR ? 40 : 4; | |
6718 | } | |
6719 | /* Adjust load_si / pcload_si type insns latency. Use the known | |
6720 | nominal latency and form of the insn to speed up the check. */ | |
6721 | else if (cost == 3 | |
6722 | && GET_CODE (PATTERN (dep_insn)) == SET | |
6723 | /* Latency for dmpy type insns is also 3, so check the that | |
6724 | it's actually a move insn. */ | |
6725 | && general_movsrc_operand (SET_SRC (PATTERN (dep_insn)), SImode)) | |
6726 | cost = 2; | |
6727 | else if (cost == 30 | |
6728 | && GET_CODE (PATTERN (dep_insn)) == SET | |
6729 | && GET_MODE (SET_SRC (PATTERN (dep_insn))) == SImode) | |
6730 | cost = 20; | |
6731 | ||
6732 | return cost; | |
6733 | } | |
3007d592 R |
6734 | |
6735 | /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some | |
6736 | 'special function' patterns (type sfunc) that clobber pr, but that | |
6737 | do not look like function calls to leaf_function_p. Hence we must | |
6738 | do this extra check. */ | |
6739 | int | |
6740 | sh_pr_n_sets () | |
6741 | { | |
12e85a0e | 6742 | return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG); |
3007d592 | 6743 | } |
fa5322fa | 6744 | |
fae15c93 VM |
6745 | /* This Function Returns non zero if DFA based scheduler |
6746 | interface is to be used.At present supported only for | |
6747 | SH4. */ | |
6748 | static int | |
6749 | sh_use_dfa_interface() | |
6750 | { | |
6751 | if (TARGET_SH4) | |
6752 | return 1; | |
6753 | else | |
6754 | return 0; | |
6755 | } | |
6756 | ||
6757 | /* This function returns "2" that signifies dual issue | |
6758 | for SH4 processor.To be used by DFA pipeline description. */ | |
6759 | static int | |
6760 | sh_issue_rate() | |
6761 | { | |
6762 | if(TARGET_SH4) | |
6763 | return 2; | |
6764 | else | |
6765 | return 1; | |
6766 | } | |
6767 | ||
fa5322fa AO |
6768 | /* SHmedia requires registers for branches, so we can't generate new |
6769 | branches past reload. */ | |
6770 | static bool | |
6771 | sh_cannot_modify_jumps_p () | |
6772 | { | |
6773 | return (TARGET_SHMEDIA && (reload_in_progress || reload_completed)); | |
6774 | } | |
6775 | ||
6776 | static bool | |
6777 | sh_ms_bitfield_layout_p (record_type) | |
6778 | tree record_type ATTRIBUTE_UNUSED; | |
6779 | { | |
6780 | return TARGET_SH5; | |
6781 | } | |
fb49053f RH |
6782 | |
6783 | /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we | |
6784 | may access it using GOTOFF instead of GOT. */ | |
6785 | ||
6786 | static void | |
6787 | sh_encode_section_info (decl, first) | |
6788 | tree decl; | |
6789 | int first; | |
6790 | { | |
6791 | rtx rtl, symbol; | |
6792 | ||
6793 | if (DECL_P (decl)) | |
6794 | rtl = DECL_RTL (decl); | |
6795 | else | |
6796 | rtl = TREE_CST_RTL (decl); | |
6797 | if (GET_CODE (rtl) != MEM) | |
6798 | return; | |
6799 | symbol = XEXP (rtl, 0); | |
6800 | if (GET_CODE (symbol) != SYMBOL_REF) | |
6801 | return; | |
6802 | ||
6803 | if (flag_pic) | |
47754fd5 | 6804 | SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl); |
fb49053f RH |
6805 | |
6806 | if (TARGET_SH5 && first && TREE_CODE (decl) != FUNCTION_DECL) | |
6807 | XEXP (rtl, 0) = gen_datalabel_ref (symbol); | |
6808 | } | |
772c5265 RH |
6809 | |
6810 | /* Undo the effects of the above. */ | |
6811 | ||
6812 | static const char * | |
6813 | sh_strip_name_encoding (str) | |
6814 | const char *str; | |
6815 | { | |
6816 | STRIP_DATALABEL_ENCODING (str, str); | |
6817 | str += *str == '*'; | |
6818 | return str; | |
6819 | } | |
e2500fed GK |
6820 | |
6821 | #include "gt-sh.h" |