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7b23765d | 1 | /* Definitions of target machine for GNU compiler for Renesas / SuperH SH. |
aad93da1 | 2 | Copyright (C) 1993-2017 Free Software Foundation, Inc. |
dda0acb2 | 3 | Contributed by Steve Chamberlain (sac@cygnus.com). |
4 | Improved by Jim Wilson (wilson@cygnus.com). | |
7208c779 | 5 | |
187b36cf | 6 | This file is part of GCC. |
7208c779 | 7 | |
187b36cf | 8 | GCC is free software; you can redistribute it and/or modify |
7208c779 | 9 | it under the terms of the GNU General Public License as published by |
038d1e19 | 10 | the Free Software Foundation; either version 3, or (at your option) |
7208c779 | 11 | any later version. |
12 | ||
187b36cf | 13 | GCC is distributed in the hope that it will be useful, |
7208c779 | 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
038d1e19 | 19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
7208c779 | 21 | |
1fcd08b1 | 22 | #ifndef GCC_SH_H |
23 | #define GCC_SH_H | |
97a18f26 | 24 | |
a9cfe83b | 25 | #include "config/vxworks-dummy.h" |
26 | ||
0dbd1c74 | 27 | /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't |
805e22b2 | 28 | include it here, because bconfig.h is also included by gencodes.c . */ |
5645dcc7 | 29 | /* ??? No longer true. */ |
0dbd1c74 | 30 | extern int code_for_indirect_jump_scratch; |
31 | ||
cfaba078 | 32 | #define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile) |
3dfc1807 | 33 | |
992d172c | 34 | /* Value should be nonzero if functions must have frame pointers. |
35 | Zero means the frame pointer need not be set up (and parms may be accessed | |
36 | via the stack pointer) in functions that seem suitable. */ | |
37 | ||
38 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
39 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
40 | #endif | |
97595bfd | 41 | |
7208c779 | 42 | \f |
92c473b8 | 43 | /* Nonzero if this is an ELF target - compile time only */ |
44 | #define TARGET_ELF 0 | |
45 | ||
87ed74ef | 46 | /* Nonzero if we should generate code using type 2E insns. */ |
156fac8b | 47 | #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E) |
87ed74ef | 48 | |
7105fb72 | 49 | /* Nonzero if we should generate code using type 2A insns. */ |
156fac8b | 50 | #define TARGET_SH2A TARGET_HARD_SH2A |
7105fb72 | 51 | /* Nonzero if we should generate code using type 2A SF insns. */ |
156fac8b | 52 | #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E) |
7105fb72 | 53 | /* Nonzero if we should generate code using type 2A DF insns. */ |
156fac8b | 54 | #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A) |
7208c779 | 55 | |
07a356f1 | 56 | /* Nonzero if we should generate code using type 3E insns. */ |
156fac8b | 57 | #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E) |
07a356f1 | 58 | |
9df03d69 | 59 | /* Nonzero if we schedule for a superscalar implementation. */ |
2e752f00 | 60 | #define TARGET_SUPERSCALAR (TARGET_HARD_SH4 || TARGET_SH2A) |
1b61190c | 61 | |
87e19636 | 62 | /* Nonzero if a double-precision FPU is available. */ |
09c4fd25 | 63 | #define TARGET_FPU_DOUBLE (TARGET_SH4 || TARGET_SH2A_DOUBLE) |
87e19636 | 64 | |
65 | /* Nonzero if an FPU is available. */ | |
87ed74ef | 66 | #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE) |
87e19636 | 67 | |
9435e831 | 68 | /* Nonzero if we're generating code for SH4a, unless the use of the |
69 | FPU is disabled (which makes it compatible with SH4al-dsp). */ | |
5b271aff | 70 | #define TARGET_SH4A_FP (TARGET_SH4A && TARGET_FPU_ANY) |
9435e831 | 71 | |
8af3db02 | 72 | |
09a512b9 | 73 | /* This is not used by the SH2E calling convention */ |
74 | #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \ | |
a0b78918 | 75 | (! TARGET_SH2E \ |
09a512b9 | 76 | && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL))) |
77 | ||
07168dd9 | 78 | #ifndef TARGET_CPU_DEFAULT |
79 | #define TARGET_CPU_DEFAULT SELECT_SH1 | |
156fac8b | 80 | #define SUPPORT_SH1 1 |
81 | #define SUPPORT_SH2E 1 | |
82 | #define SUPPORT_SH4 1 | |
83 | #define SUPPORT_SH4_SINGLE 1 | |
84 | #define SUPPORT_SH2A 1 | |
85 | #define SUPPORT_SH2A_SINGLE 1 | |
07168dd9 | 86 | #endif |
87 | ||
d6005df3 | 88 | #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) |
89 | #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP) | |
90 | #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE) | |
59312820 | 91 | |
6c049e03 | 92 | #define SELECT_SH1 (MASK_SH1) |
93 | #define SELECT_SH2 (MASK_SH2 | SELECT_SH1) | |
94 | #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \ | |
156fac8b | 95 | | MASK_FPU_SINGLE) |
6c049e03 | 96 | #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \ |
156fac8b | 97 | | MASK_HARD_SH2A_DOUBLE \ |
98 | | MASK_SH2 | MASK_SH1) | |
6c049e03 | 99 | #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1) |
156fac8b | 100 | #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \ |
bb057878 | 101 | | MASK_SH1 | MASK_FPU_SINGLE \ |
102 | | MASK_FPU_SINGLE_ONLY) | |
6c049e03 | 103 | #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \ |
156fac8b | 104 | | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \ |
105 | | MASK_SH2 | MASK_SH1) | |
6c049e03 | 106 | #define SELECT_SH3 (MASK_SH3 | SELECT_SH2) |
107 | #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3) | |
108 | #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3) | |
bb057878 | 109 | #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E \ |
110 | | MASK_FPU_SINGLE_ONLY) | |
6c049e03 | 111 | #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \ |
156fac8b | 112 | | SELECT_SH3) |
6c049e03 | 113 | #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4) |
114 | #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU) | |
156fac8b | 115 | #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) |
6c049e03 | 116 | #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) |
117 | #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) | |
07168dd9 | 118 | |
156fac8b | 119 | #if SUPPORT_SH1 |
120 | #define SUPPORT_SH2 1 | |
07168dd9 | 121 | #endif |
156fac8b | 122 | #if SUPPORT_SH2 |
123 | #define SUPPORT_SH3 1 | |
5be30882 | 124 | #define SUPPORT_SH2A_NOFPU 1 |
07168dd9 | 125 | #endif |
156fac8b | 126 | #if SUPPORT_SH3 |
127 | #define SUPPORT_SH4_NOFPU 1 | |
9435e831 | 128 | #endif |
156fac8b | 129 | #if SUPPORT_SH4_NOFPU |
130 | #define SUPPORT_SH4A_NOFPU 1 | |
131 | #define SUPPORT_SH4AL 1 | |
07168dd9 | 132 | #endif |
133 | ||
156fac8b | 134 | #if SUPPORT_SH2E |
135 | #define SUPPORT_SH3E 1 | |
5be30882 | 136 | #define SUPPORT_SH2A_SINGLE_ONLY 1 |
07168dd9 | 137 | #endif |
156fac8b | 138 | #if SUPPORT_SH3E |
139 | #define SUPPORT_SH4_SINGLE_ONLY 1 | |
5be30882 | 140 | #endif |
141 | #if SUPPORT_SH4_SINGLE_ONLY | |
156fac8b | 142 | #define SUPPORT_SH4A_SINGLE_ONLY 1 |
7105fb72 | 143 | #endif |
144 | ||
156fac8b | 145 | #if SUPPORT_SH4 |
146 | #define SUPPORT_SH4A 1 | |
7105fb72 | 147 | #endif |
148 | ||
156fac8b | 149 | #if SUPPORT_SH4_SINGLE |
150 | #define SUPPORT_SH4A_SINGLE 1 | |
07168dd9 | 151 | #endif |
152 | ||
27461bd2 | 153 | /* Reset all target-selection flags. */ |
156fac8b | 154 | #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ |
155 | | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ | |
65d02209 | 156 | | MASK_HARD_SH4 | MASK_FPU_SINGLE \ |
bb057878 | 157 | | MASK_FPU_SINGLE_ONLY) |
6c8e3918 | 158 | |
87ab0a3d | 159 | /* This defaults us to big-endian. */ |
160 | #ifndef TARGET_ENDIAN_DEFAULT | |
161 | #define TARGET_ENDIAN_DEFAULT 0 | |
162 | #endif | |
163 | ||
59312820 | 164 | #ifndef TARGET_OPT_DEFAULT |
11e875c9 | 165 | #define TARGET_OPT_DEFAULT 0 |
59312820 | 166 | #endif |
167 | ||
168 | #define TARGET_DEFAULT \ | |
169 | (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT) | |
170 | ||
07168dd9 | 171 | #ifndef SH_MULTILIB_CPU_DEFAULT |
172 | #define SH_MULTILIB_CPU_DEFAULT "m1" | |
493914a8 | 173 | #endif |
174 | ||
07168dd9 | 175 | #if TARGET_ENDIAN_DEFAULT |
176 | #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT } | |
177 | #else | |
178 | #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT } | |
179 | #endif | |
87ab0a3d | 180 | |
181 | #define CPP_SPEC " %(subtarget_cpp_spec) " | |
182 | ||
183 | #ifndef SUBTARGET_CPP_SPEC | |
184 | #define SUBTARGET_CPP_SPEC "" | |
185 | #endif | |
186 | ||
7b635b7e | 187 | #ifndef SUBTARGET_EXTRA_SPECS |
188 | #define SUBTARGET_EXTRA_SPECS | |
189 | #endif | |
190 | ||
87ab0a3d | 191 | #define EXTRA_SPECS \ |
192 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ | |
193 | { "link_emul_prefix", LINK_EMUL_PREFIX }, \ | |
194 | { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \ | |
195 | { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \ | |
196 | { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \ | |
7b635b7e | 197 | { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \ |
c999a707 | 198 | { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \ |
59312820 | 199 | { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \ |
200 | { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ | |
7b635b7e | 201 | SUBTARGET_EXTRA_SPECS |
87ab0a3d | 202 | |
156fac8b | 203 | #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 |
4d3fbc37 | 204 | #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:-isa=sh4-up}}}" |
c999a707 | 205 | #else |
a363d423 | 206 | #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}" |
c999a707 | 207 | #endif |
208 | ||
5e8551bd | 209 | /* Define which ISA type to pass to the assembler. |
210 | For SH4 we pass SH4A to allow using some instructions that are available | |
211 | on some SH4 variants, but officially are part of the SH4A ISA. */ | |
c999a707 | 212 | #define SH_ASM_SPEC \ |
81b46c0d | 213 | "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)} \ |
214 | %(subtarget_asm_isa_spec) %(subtarget_asm_spec) \ | |
5e8551bd | 215 | %{m1:--isa=sh} \ |
216 | %{m2:--isa=sh2} \ | |
217 | %{m2e:--isa=sh2e} \ | |
218 | %{m3:--isa=sh3} \ | |
219 | %{m3e:--isa=sh3e} \ | |
220 | %{m4:--isa=sh4a} \ | |
221 | %{m4-single:--isa=sh4a} \ | |
222 | %{m4-single-only:--isa=sh4a} \ | |
223 | %{m4-nofpu:--isa=sh4a-nofpu} \ | |
224 | %{m4a:--isa=sh4a} \ | |
225 | %{m4a-single:--isa=sh4a} \ | |
226 | %{m4a-single-only:--isa=sh4a} \ | |
227 | %{m4a-nofpu:--isa=sh4a-nofpu} \ | |
59312820 | 228 | %{m2a:--isa=sh2a} \ |
229 | %{m2a-single:--isa=sh2a} \ | |
230 | %{m2a-single-only:--isa=sh2a} \ | |
231 | %{m2a-nofpu:--isa=sh2a-nofpu} \ | |
65d02209 | 232 | %{m4al:-dsp}" |
c999a707 | 233 | |
234 | #define ASM_SPEC SH_ASM_SPEC | |
87ab0a3d | 235 | |
236 | #ifndef SUBTARGET_ASM_ENDIAN_SPEC | |
156fac8b | 237 | #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN |
87ab0a3d | 238 | #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}" |
239 | #else | |
240 | #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}" | |
241 | #endif | |
242 | #endif | |
243 | ||
59312820 | 244 | #if STRICT_NOFPU == 1 |
245 | /* Strict nofpu means that the compiler should tell the assembler | |
246 | to reject FPU instructions. E.g. from ASM inserts. */ | |
156fac8b | 247 | #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E) |
4d3fbc37 | 248 | #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" |
59312820 | 249 | #else |
65d02209 | 250 | |
59312820 | 251 | #define SUBTARGET_ASM_ISA_SPEC \ |
252 | "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC | |
253 | #endif | |
254 | #else /* ! STRICT_NOFPU */ | |
255 | #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC | |
256 | #endif | |
c999a707 | 257 | |
59312820 | 258 | #ifndef SUBTARGET_ASM_SPEC |
bcc58dc6 | 259 | #define SUBTARGET_ASM_SPEC "%{mfdpic:--fdpic}" |
59312820 | 260 | #endif |
261 | ||
156fac8b | 262 | #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN |
59312820 | 263 | #define LINK_EMUL_PREFIX "sh%{!mb:l}" |
264 | #else | |
87ab0a3d | 265 | #define LINK_EMUL_PREFIX "sh%{ml:l}" |
59312820 | 266 | #endif |
493914a8 | 267 | |
87ab0a3d | 268 | #define LINK_DEFAULT_CPU_EMUL "" |
07168dd9 | 269 | #define ASM_ISA_DEFAULT_SPEC "" |
493914a8 | 270 | |
bcc58dc6 | 271 | #define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd}" |
87ab0a3d | 272 | #define SUBTARGET_LINK_SPEC "" |
273 | ||
91276c47 | 274 | /* Go via SH_LINK_SPEC to avoid code replication. */ |
87ab0a3d | 275 | #define LINK_SPEC SH_LINK_SPEC |
276 | ||
277 | #define SH_LINK_SPEC "\ | |
278 | -m %(link_emul_prefix)\ | |
65d02209 | 279 | %{!m1:%{!m2:%{!m3*:%{!m4*:%(link_default_cpu_emul)}}}}\ |
87ab0a3d | 280 | %(subtarget_link_emul_suffix) \ |
281 | %{mrelax:-relax} %(subtarget_link_spec)" | |
3dfc1807 | 282 | |
59312820 | 283 | #ifndef SH_DIV_STR_FOR_SIZE |
284 | #define SH_DIV_STR_FOR_SIZE "call" | |
285 | #endif | |
286 | ||
3dfda760 | 287 | /* SH2A does not support little-endian. Catch such combinations |
288 | taking into account the default configuration. */ | |
289 | #if TARGET_ENDIAN_DEFAULT == MASK_BIG_ENDIAN | |
290 | #define IS_LITTLE_ENDIAN_OPTION "%{ml:" | |
291 | #else | |
292 | #define IS_LITTLE_ENDIAN_OPTION "%{!mb:" | |
293 | #endif | |
294 | ||
295 | #if TARGET_CPU_DEFAULT & MASK_HARD_SH2A | |
296 | #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \ | |
bf8ce8ad | 297 | "%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:%eSH2a does not support little-endian}}}}}" |
3dfda760 | 298 | #else |
299 | #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \ | |
300 | "%{m2a*:%eSH2a does not support little-endian}}" | |
301 | #endif | |
302 | ||
bcc58dc6 | 303 | #ifdef FDPIC_DEFAULT |
304 | #define FDPIC_SELF_SPECS "%{!mno-fdpic:-mfdpic}" | |
305 | #else | |
306 | #define FDPIC_SELF_SPECS | |
307 | #endif | |
308 | ||
e10782c9 | 309 | #undef DRIVER_SELF_SPECS |
bcc58dc6 | 310 | #define DRIVER_SELF_SPECS UNSUPPORTED_SH2A SUBTARGET_DRIVER_SELF_SPECS \ |
311 | FDPIC_SELF_SPECS | |
312 | ||
313 | #undef SUBTARGET_DRIVER_SELF_SPECS | |
314 | #define SUBTARGET_DRIVER_SELF_SPECS | |
9b8dc018 | 315 | |
1b61190c | 316 | #define ASSEMBLER_DIALECT assembler_dialect |
317 | ||
318 | extern int assembler_dialect; | |
319 | ||
59312820 | 320 | enum sh_divide_strategy_e { |
d6005df3 | 321 | /* SH1 .. SH4 strategies. Because of the small number of registers |
9ca2c29a | 322 | available, the compiler uses knowledge of the actual set of registers |
323 | being clobbered by the different functions called. */ | |
d6005df3 | 324 | SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */ |
325 | SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */ | |
326 | SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */ | |
327 | SH_DIV_INTRINSIC | |
59312820 | 328 | }; |
329 | ||
330 | extern enum sh_divide_strategy_e sh_div_strategy; | |
331 | ||
332 | #ifndef SH_DIV_STRATEGY_DEFAULT | |
65d02209 | 333 | #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL_DIV1 |
59312820 | 334 | #endif |
335 | ||
c6bc8374 | 336 | #ifdef __cplusplus |
337 | ||
338 | /* Atomic model. */ | |
339 | struct sh_atomic_model | |
340 | { | |
341 | enum enum_type | |
342 | { | |
343 | none = 0, | |
344 | soft_gusa, | |
345 | hard_llcs, | |
346 | soft_tcb, | |
347 | soft_imask, | |
348 | ||
349 | num_models | |
350 | }; | |
351 | ||
352 | /* If strict is set, disallow mixing of different models, as it would | |
353 | happen on SH4A. */ | |
354 | bool strict; | |
355 | enum_type type; | |
356 | ||
357 | /* Name string as it was specified on the command line. */ | |
358 | const char* name; | |
359 | ||
360 | /* Name string as it is used in C/C++ defines. */ | |
361 | const char* cdef_name; | |
362 | ||
363 | /* GBR offset variable for TCB model. */ | |
364 | int tcb_gbr_offset; | |
365 | }; | |
366 | ||
367 | extern const sh_atomic_model& selected_atomic_model (void); | |
368 | ||
369 | /* Shortcuts to check the currently selected atomic model. */ | |
370 | #define TARGET_ATOMIC_ANY \ | |
371 | (selected_atomic_model ().type != sh_atomic_model::none) | |
372 | ||
373 | #define TARGET_ATOMIC_STRICT \ | |
374 | (selected_atomic_model ().strict) | |
375 | ||
376 | #define TARGET_ATOMIC_SOFT_GUSA \ | |
377 | (selected_atomic_model ().type == sh_atomic_model::soft_gusa) | |
378 | ||
379 | #define TARGET_ATOMIC_HARD_LLCS \ | |
380 | (selected_atomic_model ().type == sh_atomic_model::hard_llcs) | |
381 | ||
382 | #define TARGET_ATOMIC_SOFT_TCB \ | |
383 | (selected_atomic_model ().type == sh_atomic_model::soft_tcb) | |
384 | ||
385 | #define TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX \ | |
386 | GEN_INT (selected_atomic_model ().tcb_gbr_offset) | |
387 | ||
388 | #define TARGET_ATOMIC_SOFT_IMASK \ | |
389 | (selected_atomic_model ().type == sh_atomic_model::soft_imask) | |
390 | ||
391 | #endif // __cplusplus | |
392 | ||
a9cfe83b | 393 | #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 |
394 | ||
7208c779 | 395 | \f |
9d1ff654 | 396 | /* Target machine storage layout. */ |
7208c779 | 397 | |
adb7af07 | 398 | #define TARGET_BIG_ENDIAN (!TARGET_LITTLE_ENDIAN) |
399 | ||
400 | #define SH_REG_MSW_OFFSET (TARGET_LITTLE_ENDIAN ? 1 : 0) | |
401 | #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) | |
402 | ||
7208c779 | 403 | /* Define this if most significant bit is lowest numbered |
404 | in instructions that operate on numbered bit-fields. */ | |
405 | #define BITS_BIG_ENDIAN 0 | |
406 | ||
407 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
adb7af07 | 408 | #define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN |
7208c779 | 409 | |
410 | /* Define this if most significant word of a multiword number is the lowest | |
411 | numbered. */ | |
adb7af07 | 412 | #define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN |
3dfc1807 | 413 | |
87e19636 | 414 | #define MAX_BITS_PER_WORD 64 |
415 | ||
87e19636 | 416 | /* Width in bits of an `int'. We want just 32-bits, even if words are |
ada8cf8b | 417 | longer. */ |
87e19636 | 418 | #define INT_TYPE_SIZE 32 |
419 | ||
420 | /* Width in bits of a `long'. */ | |
65d02209 | 421 | #define LONG_TYPE_SIZE (32) |
87e19636 | 422 | |
423 | /* Width in bits of a `long long'. */ | |
424 | #define LONG_LONG_TYPE_SIZE 64 | |
425 | ||
426 | /* Width in bits of a `long double'. */ | |
427 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
7208c779 | 428 | |
429 | /* Width of a word, in units (bytes). */ | |
65d02209 | 430 | #define UNITS_PER_WORD (4) |
87e19636 | 431 | #define MIN_UNITS_PER_WORD 4 |
7208c779 | 432 | |
41fafa66 | 433 | /* Scaling factor for Dwarf data offsets for CFI information. |
bf8ce8ad | 434 | The dwarf2out.c default would use -UNITS_PER_WORD. */ |
41fafa66 | 435 | #define DWARF_CIE_DATA_ALIGNMENT -4 |
436 | ||
7208c779 | 437 | /* Width in bits of a pointer. |
438 | See also the macro `Pmode' defined below. */ | |
65d02209 | 439 | #define POINTER_SIZE (32) |
7208c779 | 440 | |
441 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
65d02209 | 442 | #define PARM_BOUNDARY (32) |
7208c779 | 443 | |
444 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
ba46e0eb | 445 | #define STACK_BOUNDARY BIGGEST_ALIGNMENT |
7208c779 | 446 | |
0dbd1c74 | 447 | /* The log (base 2) of the cache line size, in bytes. Processors prior to |
f0a494e6 | 448 | SH2 have no actual cache, but they fetch code in chunks of 4 bytes. |
449 | The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */ | |
65d02209 | 450 | #define CACHE_LOG (TARGET_HARD_SH4 ? 5 : TARGET_SH2 ? 4 : 2) |
0dbd1c74 | 451 | |
154b29aa | 452 | /* ABI given & required minimum allocation boundary (in *bits*) for the |
453 | code of a function. */ | |
65d02209 | 454 | #define FUNCTION_BOUNDARY (16) |
87e19636 | 455 | |
7208c779 | 456 | /* Alignment of field after `int : 0' in a structure. */ |
457 | #define EMPTY_FIELD_BOUNDARY 32 | |
458 | ||
459 | /* No data type wants to be aligned rounder than this. */ | |
460 | #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) | |
461 | ||
462 | /* The best alignment to use in cases where we have a choice. */ | |
65d02209 | 463 | #define FASTEST_ALIGNMENT (32) |
7208c779 | 464 | |
7208c779 | 465 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
9d1ff654 | 466 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
7208c779 | 467 | ((TREE_CODE (EXP) == STRING_CST \ |
468 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
97595bfd | 469 | ? FASTEST_ALIGNMENT : (ALIGN)) |
7208c779 | 470 | |
1fe27026 | 471 | /* get_mode_alignment assumes complex values are always held in multiple |
472 | registers, but that is not the case on the SH; CQImode and CHImode are | |
bf8ce8ad | 473 | held in a single integer register. */ |
1fe27026 | 474 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ |
475 | ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \ | |
476 | || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \ | |
41fafa66 | 477 | ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \ |
5be30882 | 478 | : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN)) |
1fe27026 | 479 | |
7208c779 | 480 | /* Make arrays of chars word-aligned for the same reasons. */ |
481 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
482 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
483 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
484 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
485 | ||
2e3d4844 | 486 | /* Number of bits which any structure or union's size must be a |
487 | multiple of. Each structure or union's size is rounded up to a | |
641e8334 | 488 | multiple of this. */ |
2717207c | 489 | #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8) |
2e3d4844 | 490 | |
7208c779 | 491 | /* Set this nonzero if move instructions will actually fail to work |
492 | when given unaligned data. */ | |
493 | #define STRICT_ALIGNMENT 1 | |
9eaab178 | 494 | |
495 | /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */ | |
496 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \ | |
497 | barrier_align (LABEL_AFTER_BARRIER) | |
498 | ||
164fbbdf | 499 | #define LOOP_ALIGN(A_LABEL) sh_loop_align (A_LABEL) |
9eaab178 | 500 | |
501 | #define LABEL_ALIGN(A_LABEL) \ | |
502 | ( \ | |
503 | (PREV_INSN (A_LABEL) \ | |
cbb16986 | 504 | && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \ |
9eaab178 | 505 | && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \ |
8f87ecd5 | 506 | && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \ |
9df03d69 | 507 | /* explicit alignment insn in constant tables. */ \ |
9eaab178 | 508 | ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \ |
509 | : 0) | |
510 | ||
511 | /* Jump tables must be 32 bit aligned, no matter the size of the element. */ | |
512 | #define ADDR_VEC_ALIGN(ADDR_VEC) 2 | |
513 | ||
514 | /* The base two logarithm of the known minimum alignment of an insn length. */ | |
65d02209 | 515 | #define INSN_LENGTH_ALIGNMENT(A_INSN) \ |
516 | (NONJUMP_INSN_P (A_INSN) \ | |
517 | ? 1 \ | |
518 | : JUMP_P (A_INSN) || CALL_P (A_INSN) \ | |
519 | ? 1 \ | |
9eaab178 | 520 | : CACHE_LOG) |
7208c779 | 521 | \f |
522 | /* Standard register usage. */ | |
523 | ||
7b23765d | 524 | /* Register allocation for the Renesas calling convention: |
7208c779 | 525 | |
6c049e03 | 526 | r0 arg return |
527 | r1..r3 scratch | |
9d1ff654 | 528 | r4..r7 args in |
97595bfd | 529 | r8..r13 call saved |
530 | r14 frame pointer/call saved | |
7208c779 | 531 | r15 stack pointer |
532 | ap arg pointer (doesn't really exist, always eliminated) | |
533 | pr subroutine return address | |
6c049e03 | 534 | t t bit |
641e8334 | 535 | mach multiply/accumulate result, high part |
07a356f1 | 536 | macl multiply/accumulate result, low part. |
537 | fpul fp/int communication register | |
1ae4c297 | 538 | rap return address pointer register |
07a356f1 | 539 | fr0 fp arg return |
540 | fr1..fr3 scratch floating point registers | |
541 | fr4..fr11 fp args in | |
542 | fr12..fr15 call saved floating point registers */ | |
7208c779 | 543 | |
b0fa59a9 | 544 | #define MAX_REGISTER_NAME_LENGTH 6 |
87e19636 | 545 | extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1]; |
546 | ||
547 | #define SH_REGISTER_NAMES_INITIALIZER \ | |
6c049e03 | 548 | { \ |
87e19636 | 549 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ |
550 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
551 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ | |
552 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ | |
553 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ | |
554 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \ | |
555 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ | |
556 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \ | |
557 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \ | |
558 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \ | |
559 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \ | |
560 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \ | |
561 | "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \ | |
562 | "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \ | |
563 | "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \ | |
564 | "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \ | |
565 | "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \ | |
566 | "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \ | |
567 | "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \ | |
b0fa59a9 | 568 | "rap", "sfp", "fpscr0", "fpscr1" \ |
87e19636 | 569 | } |
570 | ||
87e19636 | 571 | #define REGNAMES_ARR_INDEX_1(index) \ |
572 | (sh_register_names[index]) | |
573 | #define REGNAMES_ARR_INDEX_2(index) \ | |
574 | REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1) | |
575 | #define REGNAMES_ARR_INDEX_4(index) \ | |
576 | REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2) | |
577 | #define REGNAMES_ARR_INDEX_8(index) \ | |
578 | REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4) | |
579 | #define REGNAMES_ARR_INDEX_16(index) \ | |
580 | REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8) | |
581 | #define REGNAMES_ARR_INDEX_32(index) \ | |
582 | REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16) | |
583 | #define REGNAMES_ARR_INDEX_64(index) \ | |
584 | REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32) | |
585 | ||
586 | #define REGISTER_NAMES \ | |
587 | { \ | |
588 | REGNAMES_ARR_INDEX_64 (0), \ | |
589 | REGNAMES_ARR_INDEX_64 (64), \ | |
590 | REGNAMES_ARR_INDEX_8 (128), \ | |
591 | REGNAMES_ARR_INDEX_8 (136), \ | |
592 | REGNAMES_ARR_INDEX_8 (144), \ | |
b0fa59a9 | 593 | REGNAMES_ARR_INDEX_4 (152) \ |
87e19636 | 594 | } |
595 | ||
596 | #define ADDREGNAMES_SIZE 32 | |
597 | #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4 | |
598 | extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ | |
599 | [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]; | |
600 | ||
601 | #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \ | |
602 | { \ | |
603 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \ | |
604 | "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \ | |
605 | "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \ | |
606 | "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \ | |
607 | } | |
608 | ||
609 | #define ADDREGNAMES_REGNO(index) \ | |
610 | ((index < 32) ? (FIRST_FP_REG + (index) * 2) \ | |
611 | : (-1)) | |
612 | ||
613 | #define ADDREGNAMES_ARR_INDEX_1(index) \ | |
614 | { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) } | |
615 | #define ADDREGNAMES_ARR_INDEX_2(index) \ | |
616 | ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1) | |
617 | #define ADDREGNAMES_ARR_INDEX_4(index) \ | |
618 | ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2) | |
619 | #define ADDREGNAMES_ARR_INDEX_8(index) \ | |
620 | ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4) | |
621 | #define ADDREGNAMES_ARR_INDEX_16(index) \ | |
622 | ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8) | |
623 | #define ADDREGNAMES_ARR_INDEX_32(index) \ | |
624 | ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16) | |
625 | ||
626 | #define ADDITIONAL_REGISTER_NAMES \ | |
627 | { \ | |
628 | ADDREGNAMES_ARR_INDEX_32 (0) \ | |
629 | } | |
630 | ||
7208c779 | 631 | /* Number of actual hardware registers. |
632 | The hardware registers are assigned numbers for the compiler | |
633 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
634 | All registers that the compiler knows about must be given numbers, | |
641e8334 | 635 | even those that are not normally considered general registers. */ |
7208c779 | 636 | |
a5bd34f1 | 637 | /* There are many other relevant definitions in sh.md's md_constants. */ |
638 | ||
639 | #define FIRST_GENERAL_REG R0_REG | |
65d02209 | 640 | #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (15)) |
a5bd34f1 | 641 | #define FIRST_FP_REG DR0_REG |
65d02209 | 642 | #define LAST_FP_REG (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)) |
a5bd34f1 | 643 | #define FIRST_XD_REG XD0_REG |
87e19636 | 644 | #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1)) |
a5bd34f1 | 645 | |
2f8b8488 | 646 | /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */ |
2f8b8488 | 647 | #define FIRST_BANKED_REG R0_REG |
648 | #define LAST_BANKED_REG R7_REG | |
649 | ||
6c049e03 | 650 | #define BANKED_REGISTER_P(REGNO) \ |
651 | IN_RANGE ((REGNO), \ | |
2f8b8488 | 652 | (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \ |
653 | (unsigned HOST_WIDE_INT) LAST_BANKED_REG) | |
654 | ||
e2142b04 | 655 | #define GENERAL_REGISTER_P(REGNO) \ |
41fafa66 | 656 | IN_RANGE ((REGNO), \ |
657 | (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ | |
658 | (unsigned HOST_WIDE_INT) LAST_GENERAL_REG) | |
e2142b04 | 659 | |
660 | #define GENERAL_OR_AP_REGISTER_P(REGNO) \ | |
6c049e03 | 661 | (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \ |
b9a602c6 | 662 | || ((REGNO) == FRAME_POINTER_REGNUM)) |
e2142b04 | 663 | |
664 | #define FP_REGISTER_P(REGNO) \ | |
41fafa66 | 665 | ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG) |
e2142b04 | 666 | |
667 | #define XD_REGISTER_P(REGNO) \ | |
41fafa66 | 668 | ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG) |
e2142b04 | 669 | |
670 | #define FP_OR_XD_REGISTER_P(REGNO) \ | |
671 | (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO)) | |
672 | ||
673 | #define FP_ANY_REGISTER_P(REGNO) \ | |
674 | (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG) | |
675 | ||
676 | #define SPECIAL_REGISTER_P(REGNO) \ | |
a5bd34f1 | 677 | ((REGNO) == GBR_REG || (REGNO) == T_REG \ |
b0fa59a9 | 678 | || (REGNO) == MACH_REG || (REGNO) == MACL_REG \ |
679 | || (REGNO) == FPSCR_MODES_REG || (REGNO) == FPSCR_STAT_REG) | |
7208c779 | 680 | |
87e19636 | 681 | #define VALID_REGISTER_P(REGNO) \ |
65d02209 | 682 | (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \ |
683 | || XD_REGISTER_P (REGNO) \ | |
87e19636 | 684 | || (REGNO) == AP_REG || (REGNO) == RAP_REG \ |
b9a602c6 | 685 | || (REGNO) == FRAME_POINTER_REGNUM \ |
a0b78918 | 686 | || ((SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \ |
87ed74ef | 687 | || (TARGET_SH2E && (REGNO) == FPUL_REG)) |
87e19636 | 688 | |
689 | /* The mode that should be generally used to store a register by | |
690 | itself in the stack, or to load it back. */ | |
691 | #define REGISTER_NATURAL_MODE(REGNO) \ | |
1e0295b9 | 692 | (FP_REGISTER_P (REGNO) ? E_SFmode \ |
693 | : XD_REGISTER_P (REGNO) ? E_DFmode : E_SImode) | |
65d02209 | 694 | |
87e19636 | 695 | |
b0fa59a9 | 696 | #define FIRST_PSEUDO_REGISTER 156 |
b9a602c6 | 697 | |
698 | /* Don't count soft frame pointer. */ | |
b0fa59a9 | 699 | #define DWARF_FRAME_REGISTERS (153) |
7208c779 | 700 | |
701 | /* 1 for registers that have pervasive standard uses | |
641e8334 | 702 | and are not available for the register allocator. |
f3d93547 | 703 | |
13d406a0 | 704 | Mach register is fixed 'cause it's only 10 bits wide for SH1. |
705 | It is 32 bits wide for SH2. */ | |
6c049e03 | 706 | #define FIXED_REGISTERS \ |
707 | { \ | |
87e19636 | 708 | /* Regular registers. */ \ |
709 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
710 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
711 | /* r16 is reserved, r18 is the former pr. */ \ | |
712 | 1, 0, 0, 0, 0, 0, 0, 0, \ | |
713 | /* r24 is reserved for the OS; r25, for the assembler or linker. */ \ | |
714 | /* r26 is a global variable data pointer; r27 is for constants. */ \ | |
715 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
716 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
717 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
718 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
719 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
720 | /* FP registers. */ \ | |
721 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
722 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
723 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
724 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
725 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
726 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
727 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
728 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
729 | /* Branch target registers. */ \ | |
730 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
731 | /* XD registers. */ \ | |
732 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
733 | /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ | |
734 | 1, 1, 1, 1, 1, 1, 0, 1, \ | |
b0fa59a9 | 735 | /*"rap", "sfp","fpscr0","fpscr1" */ \ |
736 | 1, 1, 1, 1, \ | |
07a356f1 | 737 | } |
7208c779 | 738 | |
739 | /* 1 for registers not available across function calls. | |
740 | These must include the FIXED_REGISTERS and also any | |
741 | registers that can be used without being saved. | |
742 | The latter must include the registers where values are returned | |
743 | and the register where structure-value addresses are passed. | |
744 | Aside from that, you can include as many other registers as you like. */ | |
6c049e03 | 745 | #define CALL_USED_REGISTERS \ |
746 | { \ | |
87e19636 | 747 | /* Regular registers. */ \ |
748 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
749 | /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \ | |
750 | Only the lower 32bits of R10-R14 are guaranteed to be preserved \ | |
751 | across SH5 function calls. */ \ | |
752 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
93ea47c4 | 753 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
87e19636 | 754 | 1, 1, 1, 1, 0, 0, 0, 0, \ |
755 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
756 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
757 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
758 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
759 | /* FP registers. */ \ | |
760 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
761 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
762 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
763 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
764 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
765 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
766 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
767 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
768 | /* Branch target registers. */ \ | |
769 | 1, 1, 1, 1, 1, 0, 0, 0, \ | |
770 | /* XD registers. */ \ | |
771 | 1, 1, 1, 1, 1, 1, 0, 0, \ | |
772 | /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ | |
93ea47c4 | 773 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
b0fa59a9 | 774 | /*"rap", "sfp","fpscr0","fpscr1" */ \ |
775 | 1, 1, 1, 1, \ | |
07a356f1 | 776 | } |
7208c779 | 777 | |
92f082e0 | 778 | /* CALL_REALLY_USED_REGISTERS is used as a default setting, which is then |
779 | overridden by -fcall-saved-* and -fcall-used-* options and then by | |
780 | TARGET_CONDITIONAL_REGISTER_USAGE. There we might want to make a | |
781 | register call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */ | |
782 | #define CALL_REALLY_USED_REGISTERS \ | |
783 | { \ | |
784 | /* Regular registers. */ \ | |
785 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
786 | /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \ | |
787 | Only the lower 32bits of R10-R14 are guaranteed to be preserved \ | |
788 | across SH5 function calls. */ \ | |
789 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
790 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
791 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
792 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
793 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
794 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
795 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
796 | /* FP registers. */ \ | |
797 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
798 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
799 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
800 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
801 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
802 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
803 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
804 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
805 | /* Branch target registers. */ \ | |
806 | 1, 1, 1, 1, 1, 0, 0, 0, \ | |
807 | /* XD registers. */ \ | |
808 | 1, 1, 1, 1, 1, 1, 0, 0, \ | |
809 | /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ | |
810 | 0, 1, 1, 1, 1, 1, 1, 1, \ | |
811 | /*"rap", "sfp","fpscr0","fpscr1" */ \ | |
812 | 1, 1, 0, 0, \ | |
813 | } | |
956dd562 | 814 | |
7208c779 | 815 | /* Return number of consecutive hard regs needed starting at reg REGNO |
816 | to hold something of mode MODE. | |
817 | This is ordinarily the length in words of a value of mode MODE | |
818 | but can be less for certain modes in special long registers. | |
819 | ||
1b61190c | 820 | On the SH all but the XD regs are UNITS_PER_WORD bits wide. */ |
9d1ff654 | 821 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
e2142b04 | 822 | (XD_REGISTER_P (REGNO) \ |
7da7e24b | 823 | ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \ |
7da7e24b | 824 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) |
7208c779 | 825 | |
32e68083 | 826 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ |
6c049e03 | 827 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
32e68083 | 828 | sh_hard_regno_mode_ok ((REGNO), (MODE)) |
7208c779 | 829 | |
830 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
831 | when one has mode MODE1 and one has mode MODE2. | |
832 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
6109c3ff | 833 | for any hard reg, then this must be 0 for correct output. |
834 | That's the case for xd registers: we don't hold SFmode values in | |
835 | them, so we can't tie an SFmode pseudos with one in another | |
836 | floating-point mode. */ | |
7208c779 | 837 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
6109c3ff | 838 | ((MODE1) == (MODE2) \ |
839 | || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ | |
65d02209 | 840 | && (((MODE1) != SFmode && (MODE2) != SFmode)))) |
7208c779 | 841 | |
ea68d4ba | 842 | /* Specify the modes required to caller save a given hard regno. */ |
843 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
844 | sh_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) | |
845 | ||
c67138a9 | 846 | /* A C expression that is nonzero if hard register NEW_REG can be |
847 | considered for use as a rename register for OLD_REG register */ | |
c67138a9 | 848 | #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ |
849 | sh_hard_regno_rename_ok (OLD_REG, NEW_REG) | |
850 | ||
7208c779 | 851 | /* Specify the registers used for certain standard purposes. |
852 | The values of these macros are register numbers. */ | |
853 | ||
854 | /* Define this if the program counter is overloaded on a register. */ | |
855 | /* #define PC_REGNUM 15*/ | |
856 | ||
857 | /* Register to use for pushing function arguments. */ | |
a5bd34f1 | 858 | #define STACK_POINTER_REGNUM SP_REG |
7208c779 | 859 | |
860 | /* Base register for access to local variables of the function. */ | |
b9a602c6 | 861 | #define HARD_FRAME_POINTER_REGNUM FP_REG |
862 | ||
863 | /* Base register for access to local variables of the function. */ | |
864 | #define FRAME_POINTER_REGNUM 153 | |
7208c779 | 865 | |
1ae4c297 | 866 | /* Fake register that holds the address on the stack of the |
867 | current function's return address. */ | |
a5bd34f1 | 868 | #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG |
1ae4c297 | 869 | |
0abf894c | 870 | /* Register to hold the addressing base for position independent |
871 | code access to data items. */ | |
575fdeec | 872 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM) |
0abf894c | 873 | |
bcc58dc6 | 874 | /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT |
875 | entries would need to handle saving and restoring it). */ | |
876 | #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC | |
877 | ||
0abf894c | 878 | #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_" |
879 | ||
7208c779 | 880 | /* Definitions for register eliminations. |
881 | ||
55a1ab6f | 882 | We have three registers that can be eliminated on the SH. First, the |
7208c779 | 883 | frame pointer register can often be eliminated in favor of the stack |
884 | pointer register. Secondly, the argument pointer register can always be | |
55a1ab6f | 885 | eliminated; it is replaced with either the stack or frame pointer. |
ad87de1e | 886 | Third, there is the return address pointer, which can also be replaced |
6c049e03 | 887 | with either the stack or the frame pointer. |
7208c779 | 888 | |
6c049e03 | 889 | This is an array of structures. Each structure initializes one pair |
7208c779 | 890 | of eliminable registers. The "from" register number is given first, |
891 | followed by "to". Eliminations of the same "from" register are listed | |
6c049e03 | 892 | in order of preference. |
7208c779 | 893 | |
6c049e03 | 894 | If you add any registers here that are not actually hard registers, |
55a1ab6f | 895 | and that have any alternative of elimination that doesn't always |
896 | apply, you need to amend calc_live_regs to exclude it, because | |
897 | reload spills all eliminable registers where it sees an | |
898 | can_eliminate == 0 entry, thus making them 'live' . | |
899 | If you add any hard registers that can be eliminated in different | |
900 | ways, you have to patch reload to spill them only when all alternatives | |
901 | of elimination fail. */ | |
1ae4c297 | 902 | #define ELIMINABLE_REGS \ |
b9a602c6 | 903 | {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
904 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
905 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1ae4c297 | 906 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
b9a602c6 | 907 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ |
1ae4c297 | 908 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
b9a602c6 | 909 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},} |
7208c779 | 910 | |
7208c779 | 911 | /* Define the offset between two registers, one to be eliminated, and the other |
912 | its replacement, at the start of a routine. */ | |
7208c779 | 913 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
0dbd1c74 | 914 | OFFSET = initial_elimination_offset ((FROM), (TO)) |
7208c779 | 915 | |
916 | /* Base register for access to arguments of the function. */ | |
bd579652 | 917 | #define ARG_POINTER_REGNUM AP_REG |
7208c779 | 918 | |
919 | /* Register in which the static-chain is passed to a function. */ | |
65d02209 | 920 | #define STATIC_CHAIN_REGNUM (3) |
7208c779 | 921 | |
97595bfd | 922 | /* Don't default to pcc-struct-return, because we have already specified |
6644435d | 923 | exactly how to return structures in the TARGET_RETURN_IN_MEMORY |
924 | target hook. */ | |
97595bfd | 925 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
87e19636 | 926 | |
7208c779 | 927 | \f |
928 | /* Define the classes of registers for register constraints in the | |
929 | machine description. Also define ranges of constants. | |
930 | ||
931 | One of the classes must always be named ALL_REGS and include all hard regs. | |
932 | If there is more than one class, another class must be named NO_REGS | |
933 | and contain no registers. | |
934 | ||
935 | The name GENERAL_REGS must be the name of a class (or an alias for | |
936 | another name such as ALL_REGS). This is the class of registers | |
937 | that is allowed by "g" or "r" in a register constraint. | |
938 | Also, registers outside this class are allocated only when | |
939 | instructions express preferences for them. | |
940 | ||
941 | The classes must be numbered in nondecreasing order; that is, | |
942 | a larger-numbered class must never be contained completely | |
943 | in a smaller-numbered class. | |
944 | ||
945 | For any two classes, it is very desirable that there be another | |
6c049e03 | 946 | class that represents their union. |
7208c779 | 947 | |
6c049e03 | 948 | The SH has two sorts of general registers, R0 and the rest. R0 can |
7208c779 | 949 | be used as the destination of some of the arithmetic ops. There are |
950 | also some special purpose registers; the T bit register, the | |
6c049e03 | 951 | Procedure Return Register and the Multiply Accumulate Registers. |
952 | ||
953 | Place GENERAL_REGS after FPUL_REGS so that it will be preferred by | |
0dbd1c74 | 954 | reg_class_subunion. We don't want to have an actual union class |
955 | of these, because it would only be used when both classes are calculated | |
956 | to give the same cost, but there is only one FPUL register. | |
957 | Besides, regclass fails to notice the different REGISTER_MOVE_COSTS | |
958 | applying to the actual instruction alternative considered. E.g., the | |
959 | y/r alternative of movsi_ie is considered to have no more cost that | |
960 | the r/r alternative, which is patently untrue. */ | |
7208c779 | 961 | enum reg_class |
962 | { | |
963 | NO_REGS, | |
964 | R0_REGS, | |
7208c779 | 965 | PR_REGS, |
966 | T_REGS, | |
967 | MAC_REGS, | |
07a356f1 | 968 | FPUL_REGS, |
5acd0683 | 969 | SIBCALL_REGS, |
2a0b1a37 | 970 | NON_SP_REGS, |
0dbd1c74 | 971 | GENERAL_REGS, |
07a356f1 | 972 | FP0_REGS, |
973 | FP_REGS, | |
1b61190c | 974 | DF_REGS, |
975 | FPSCR_REGS, | |
301209b2 | 976 | GENERAL_FP_REGS, |
c3c6d729 | 977 | GENERAL_DF_REGS, |
87e19636 | 978 | TARGET_REGS, |
7208c779 | 979 | ALL_REGS, |
980 | LIM_REG_CLASSES | |
981 | }; | |
982 | ||
983 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
984 | ||
641e8334 | 985 | /* Give names of register classes as strings for dump file. */ |
9d1ff654 | 986 | #define REG_CLASS_NAMES \ |
7208c779 | 987 | { \ |
988 | "NO_REGS", \ | |
989 | "R0_REGS", \ | |
7208c779 | 990 | "PR_REGS", \ |
991 | "T_REGS", \ | |
992 | "MAC_REGS", \ | |
07a356f1 | 993 | "FPUL_REGS", \ |
5acd0683 | 994 | "SIBCALL_REGS", \ |
2a0b1a37 | 995 | "NON_SP_REGS", \ |
0dbd1c74 | 996 | "GENERAL_REGS", \ |
07a356f1 | 997 | "FP0_REGS", \ |
998 | "FP_REGS", \ | |
1b61190c | 999 | "DF_REGS", \ |
1000 | "FPSCR_REGS", \ | |
301209b2 | 1001 | "GENERAL_FP_REGS", \ |
c3c6d729 | 1002 | "GENERAL_DF_REGS", \ |
87e19636 | 1003 | "TARGET_REGS", \ |
7208c779 | 1004 | "ALL_REGS", \ |
1005 | } | |
1006 | ||
1007 | /* Define which registers fit in which classes. | |
1008 | This is an initializer for a vector of HARD_REG_SET | |
1009 | of length N_REG_CLASSES. */ | |
87e19636 | 1010 | #define REG_CLASS_CONTENTS \ |
1011 | { \ | |
1012 | /* NO_REGS: */ \ | |
1013 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ | |
1014 | /* R0_REGS: */ \ | |
1015 | { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ | |
1016 | /* PR_REGS: */ \ | |
1017 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \ | |
1018 | /* T_REGS: */ \ | |
1019 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \ | |
1020 | /* MAC_REGS: */ \ | |
1021 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \ | |
1022 | /* FPUL_REGS: */ \ | |
cb44aa06 | 1023 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \ |
b2d7ede1 | 1024 | /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \ |
87e19636 | 1025 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ |
2a0b1a37 | 1026 | /* NON_SP_REGS: */ \ |
1027 | { 0xffff7fff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ | |
87e19636 | 1028 | /* GENERAL_REGS: */ \ |
b9a602c6 | 1029 | { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ |
87e19636 | 1030 | /* FP0_REGS: */ \ |
1031 | { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \ | |
1032 | /* FP_REGS: */ \ | |
1033 | { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ | |
1034 | /* DF_REGS: */ \ | |
1035 | { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ | |
1036 | /* FPSCR_REGS: */ \ | |
1037 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \ | |
1038 | /* GENERAL_FP_REGS: */ \ | |
c3c6d729 | 1039 | { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \ |
1040 | /* GENERAL_DF_REGS: */ \ | |
1041 | { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \ | |
87e19636 | 1042 | /* TARGET_REGS: */ \ |
1043 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \ | |
1044 | /* ALL_REGS: */ \ | |
b0fa59a9 | 1045 | { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0fffffff }, \ |
894b8fd9 | 1046 | } |
7208c779 | 1047 | |
1048 | /* The same information, inverted: | |
1049 | Return the class number of the smallest class containing | |
1050 | reg number REGNO. This could be a conditional expression | |
1051 | or could index an array. */ | |
41fafa66 | 1052 | extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; |
0dbd1c74 | 1053 | #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)] |
7208c779 | 1054 | |
ed5527ca | 1055 | /* When this hook returns true for MODE, the compiler allows |
1056 | registers explicitly used in the rtl to be used as spill registers | |
1057 | but prevents the compiler from extending the lifetime of these | |
1058 | registers. */ | |
1059 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ | |
1060 | sh_small_register_classes_for_mode_p | |
97595bfd | 1061 | |
7208c779 | 1062 | /* The order in which register should be allocated. */ |
0dbd1c74 | 1063 | /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo, |
1064 | and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be | |
1065 | spilled or used otherwise, we better have the FP_REGS allocated first. */ | |
9d1ff654 | 1066 | #define REG_ALLOC_ORDER \ |
1fe27026 | 1067 | {/* Caller-saved FPRs */ \ |
1068 | 65, 66, 67, 68, 69, 70, 71, 64, \ | |
1069 | 72, 73, 74, 75, 80, 81, 82, 83, \ | |
1070 | 84, 85, 86, 87, 88, 89, 90, 91, \ | |
1071 | 92, 93, 94, 95, 96, 97, 98, 99, \ | |
1072 | /* Callee-saved FPRs */ \ | |
1073 | 76, 77, 78, 79,100,101,102,103, \ | |
87e19636 | 1074 | 104,105,106,107,108,109,110,111, \ |
1075 | 112,113,114,115,116,117,118,119, \ | |
1076 | 120,121,122,123,124,125,126,127, \ | |
1fe27026 | 1077 | 136,137,138,139,140,141,142,143, \ |
1078 | /* FPSCR */ 151, \ | |
1079 | /* Caller-saved GPRs (except 8/9 on SH1-4) */ \ | |
1080 | 1, 2, 3, 7, 6, 5, 4, 0, \ | |
1081 | 8, 9, 17, 19, 20, 21, 22, 23, \ | |
1082 | 36, 37, 38, 39, 40, 41, 42, 43, \ | |
1083 | 60, 61, 62, \ | |
1084 | /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \ | |
1085 | 10, 11, 12, 13, 14, 18, \ | |
1086 | /* SH5 callee-saved GPRs */ \ | |
1087 | 28, 29, 30, 31, 32, 33, 34, 35, \ | |
1088 | 44, 45, 46, 47, 48, 49, 50, 51, \ | |
1089 | 52, 53, 54, 55, 56, 57, 58, 59, \ | |
1090 | /* FPUL */ 150, \ | |
1fe27026 | 1091 | /* Fixed registers */ \ |
1092 | 15, 16, 24, 25, 26, 27, 63,144, \ | |
b0fa59a9 | 1093 | 145,146,147,148,149,152,153,154,155 } |
7208c779 | 1094 | |
1095 | /* The class value for index registers, and the one for base regs. */ | |
65d02209 | 1096 | #define INDEX_REG_CLASS R0_REGS |
1097 | #define BASE_REG_CLASS GENERAL_REGS | |
9d1ff654 | 1098 | \f |
abff7a2e | 1099 | /* Defines for sh.md and constraints.md. */ |
7208c779 | 1100 | |
af2c1324 | 1101 | #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \ |
1102 | && ((HOST_WIDE_INT)(VALUE)) <= 127) | |
af2c1324 | 1103 | |
1104 | #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \ | |
1105 | && ((HOST_WIDE_INT)(VALUE)) <= 255) | |
07a356f1 | 1106 | |
74cf552d | 1107 | #define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\ |
1108 | (((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX)) | |
1109 | ||
7208c779 | 1110 | /* Return the maximum number of consecutive registers |
641e8334 | 1111 | needed to represent mode MODE in a register of class CLASS. |
7208c779 | 1112 | |
c87f89be | 1113 | If TARGET_SHMEDIA, we need two FP registers per word. |
1114 | Otherwise we will need at most one register per word. */ | |
9d1ff654 | 1115 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
65d02209 | 1116 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
1b61190c | 1117 | |
1118 | /* If defined, gives a class of registers that cannot be used as the | |
6c049e03 | 1119 | operand of a SUBREG that changes the mode of the object illegally. |
1120 | ??? We need to renumber the internal numbers for the frnn registers | |
d3b29bbd | 1121 | when in little endian in order to allow mode size changes. */ |
6c049e03 | 1122 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
22aae821 | 1123 | sh_cannot_change_mode_class (FROM, TO, CLASS) |
7208c779 | 1124 | \f |
1125 | /* Stack layout; function entry, exit and calling. */ | |
1126 | ||
9d1ff654 | 1127 | /* Define the number of registers that can hold parameters. |
07a356f1 | 1128 | These macros are used only in other macro definitions below. */ |
07a356f1 | 1129 | #define NPARM_REGS(MODE) \ |
87e19636 | 1130 | (TARGET_FPU_ANY && (MODE) == SFmode \ |
65d02209 | 1131 | ? 8 \ |
09c4fd25 | 1132 | : TARGET_FPU_DOUBLE \ |
6c049e03 | 1133 | && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
1134 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ | |
65d02209 | 1135 | ? 8 \ |
1136 | : 4) | |
07a356f1 | 1137 | |
65d02209 | 1138 | #define FIRST_PARM_REG (FIRST_GENERAL_REG + 4) |
1139 | #define FIRST_RET_REG (FIRST_GENERAL_REG + 0) | |
7208c779 | 1140 | |
65d02209 | 1141 | #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4) |
07a356f1 | 1142 | #define FIRST_FP_RET_REG FIRST_FP_REG |
1143 | ||
7208c779 | 1144 | /* Define this if pushing a word on the stack |
1145 | makes the stack pointer a smaller address. */ | |
2b785411 | 1146 | #define STACK_GROWS_DOWNWARD 1 |
7208c779 | 1147 | |
3ce7ff97 | 1148 | /* Define this macro to nonzero if the addresses of local variable slots |
b9a602c6 | 1149 | are at negative offsets from the frame pointer. */ |
1150 | #define FRAME_GROWS_DOWNWARD 1 | |
97595bfd | 1151 | |
1152 | /* Offset from the frame pointer to the first local variable slot to | |
641e8334 | 1153 | be allocated. */ |
7208c779 | 1154 | #define STARTING_FRAME_OFFSET 0 |
1155 | ||
1156 | /* If we generate an insn to push BYTES bytes, | |
1157 | this says how many the stack pointer really advances by. */ | |
0dbd1c74 | 1158 | /* Don't define PUSH_ROUNDING, since the hardware doesn't do this. |
1159 | When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to | |
1160 | do correct alignment. */ | |
1161 | #if 0 | |
7208c779 | 1162 | #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) |
0dbd1c74 | 1163 | #endif |
7208c779 | 1164 | |
1165 | /* Offset of first parameter from the argument pointer register value. */ | |
1166 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1167 | ||
87e19636 | 1168 | /* Value is the number of bytes of arguments automatically popped when |
1169 | calling a subroutine. | |
65d02209 | 1170 | CUM is the accumulated argument list. */ |
1171 | #define CALL_POPS_ARGS(CUM) (0) | |
87e19636 | 1172 | |
9df03d69 | 1173 | /* Some subroutine macros specific to this machine. */ |
07a356f1 | 1174 | |
1175 | #define BASE_RETURN_VALUE_REG(MODE) \ | |
6c049e03 | 1176 | ((TARGET_FPU_ANY && ((MODE) == SFmode)) \ |
07a356f1 | 1177 | ? FIRST_FP_RET_REG \ |
6c049e03 | 1178 | : TARGET_FPU_ANY && (MODE) == SCmode \ |
1b61190c | 1179 | ? FIRST_FP_RET_REG \ |
87e19636 | 1180 | : (TARGET_FPU_DOUBLE \ |
1b61190c | 1181 | && ((MODE) == DFmode || (MODE) == SFmode \ |
1182 | || (MODE) == DCmode || (MODE) == SCmode )) \ | |
1183 | ? FIRST_FP_RET_REG \ | |
07a356f1 | 1184 | : FIRST_RET_REG) |
1185 | ||
1186 | #define BASE_ARG_REG(MODE) \ | |
87ed74ef | 1187 | ((TARGET_SH2E && ((MODE) == SFmode)) \ |
07a356f1 | 1188 | ? FIRST_FP_PARM_REG \ |
09c4fd25 | 1189 | : TARGET_FPU_DOUBLE \ |
1190 | && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1191 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\ | |
1b61190c | 1192 | ? FIRST_FP_PARM_REG \ |
07a356f1 | 1193 | : FIRST_PARM_REG) |
1194 | ||
641e8334 | 1195 | /* 1 if N is a possible register number for function argument passing. */ |
41fafa66 | 1196 | /* ??? There are some callers that pass REGNO as int, and others that pass |
1197 | it as unsigned. We get warnings unless we do casts everywhere. */ | |
9d1ff654 | 1198 | #define FUNCTION_ARG_REGNO_P(REGNO) \ |
41fafa66 | 1199 | (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \ |
1200 | && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\ | |
6c049e03 | 1201 | || (TARGET_FPU_ANY \ |
41fafa66 | 1202 | && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \ |
1203 | && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \ | |
1204 | + NPARM_REGS (SFmode)))) | |
7208c779 | 1205 | \f |
910d6e82 | 1206 | #ifdef __cplusplus |
1207 | ||
7208c779 | 1208 | /* Define a data type for recording info about an argument list |
1209 | during the scan of that argument list. This data type should | |
1210 | hold all necessary information about the function itself | |
1211 | and about the args processed so far, enough to enable macros | |
1212 | such as FUNCTION_ARG to determine where the next arg should go. | |
1213 | ||
1214 | On SH, this is a single integer, which is a number of words | |
1215 | of arguments scanned so far (including the invisible argument, | |
1216 | if any, which holds the structure-value-address). | |
1217 | Thus NARGREGS or more means all following args should go on the stack. */ | |
910d6e82 | 1218 | |
07a356f1 | 1219 | enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 }; |
910d6e82 | 1220 | |
1221 | struct sh_args | |
1222 | { | |
1223 | /* How many SH_ARG_INT and how many SH_ARG_FLOAT args there are. */ | |
1224 | int arg_count[2]; | |
1225 | ||
1226 | bool force_mem; | |
1227 | ||
808a491c | 1228 | /* Nonzero if a prototype is available for the function. */ |
910d6e82 | 1229 | bool prototype_p; |
1230 | ||
87e19636 | 1231 | /* The number of an odd floating-point register, that should be used |
1232 | for the next argument of type float. */ | |
910d6e82 | 1233 | int free_single_fp_reg; |
1234 | ||
87e19636 | 1235 | /* Whether we're processing an outgoing function call. */ |
910d6e82 | 1236 | bool outgoing; |
87e19636 | 1237 | |
f328f118 | 1238 | /* This is set to nonzero when the call in question must use the Renesas ABI, |
1239 | even without the -mrenesas option. */ | |
910d6e82 | 1240 | bool renesas_abi; |
f328f118 | 1241 | }; |
1242 | ||
910d6e82 | 1243 | typedef sh_args CUMULATIVE_ARGS; |
1244 | ||
1245 | /* Set when processing a function with interrupt attribute. */ | |
1246 | extern bool current_function_interrupt; | |
1247 | ||
1248 | #endif // __cplusplus | |
07a356f1 | 1249 | |
7208c779 | 1250 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1251 | for a call to a function whose data type is FNTYPE. | |
1252 | For a library call, FNTYPE is 0. | |
1253 | ||
1254 | On SH, the offset always starts at 0: the first parm reg is always | |
5be96103 | 1255 | the same reg for a given argument class. |
1256 | ||
1257 | For TARGET_HITACHI, the structure value pointer is passed in memory. */ | |
30c70355 | 1258 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
6c049e03 | 1259 | sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL),\ |
1260 | (N_NAMED_ARGS), VOIDmode) | |
87e19636 | 1261 | |
1262 | #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
43b3dabf | 1263 | sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE)) |
7208c779 | 1264 | |
d8e6ba8f | 1265 | /* By accident we got stuck with passing SCmode on SH4 little endian |
1266 | in two registers that are nominally successive - which is different from | |
1267 | two single SFmode values, where we take endianness translation into | |
1268 | account. That does not work at all if an odd number of registers is | |
1269 | already in use, so that got fixed, but library functions are still more | |
1270 | likely to use complex numbers without mixing them with SFmode arguments | |
1271 | (which in C would have to be structures), so for the sake of ABI | |
1272 | compatibility the way SCmode values are passed when an even number of | |
1273 | FP registers is in use remains different from a pair of SFmode values for | |
1274 | now. | |
1275 | I.e.: | |
1276 | foo (double); a: fr5,fr4 | |
1277 | foo (float a, float b); a: fr5 b: fr4 | |
1278 | foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency, | |
6c049e03 | 1279 | this should be the other way round... |
d8e6ba8f | 1280 | foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */ |
1281 | #define FUNCTION_ARG_SCmode_WART 1 | |
1282 | ||
87e19636 | 1283 | /* Minimum alignment for an argument to be passed by callee-copy |
1284 | reference. We need such arguments to be aligned to 8 byte | |
1285 | boundaries, because they'll be loaded using quad loads. */ | |
1286 | #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT) | |
1287 | ||
7208c779 | 1288 | /* Perform any needed actions needed for a function that is receiving a |
641e8334 | 1289 | variable number of arguments. */ |
7208c779 | 1290 | |
24c4b61a | 1291 | /* Call the function profiler with a given profile label. |
1292 | We use two .aligns, so as to make sure that both the .long is aligned | |
1293 | on a 4 byte boundary, and that the .long is a fixed distance (2 bytes) | |
1294 | from the trapa instruction. */ | |
47c009e5 | 1295 | #define FUNCTION_PROFILER(STREAM,LABELNO) \ |
1296 | { \ | |
65d02209 | 1297 | fprintf((STREAM), "\t.align\t2\n"); \ |
1298 | fprintf((STREAM), "\ttrapa\t#33\n"); \ | |
1299 | fprintf((STREAM), "\t.align\t2\n"); \ | |
1300 | asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ | |
7208c779 | 1301 | } |
1302 | ||
9461e7f0 | 1303 | /* Define this macro if the code for function profiling should come |
1304 | before the function prologue. Normally, the profiling code comes | |
1305 | after. */ | |
9461e7f0 | 1306 | #define PROFILE_BEFORE_PROLOGUE |
1307 | ||
7208c779 | 1308 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1309 | the stack pointer does not matter. The value is tested only in | |
1310 | functions that have frame pointers. | |
1311 | No definition is equivalent to always zero. */ | |
5cbb8e38 | 1312 | #define EXIT_IGNORE_STACK 1 |
7208c779 | 1313 | |
894b8fd9 | 1314 | /* |
01cc3b75 | 1315 | On the SH, the trampoline looks like |
6c049e03 | 1316 | 2 0002 D202 mov.l l2,r2 |
1317 | 1 0000 D301 mov.l l1,r3 | |
1318 | 3 0004 422B jmp @r2 | |
1319 | 4 0006 0009 nop | |
d67085f7 | 1320 | 5 0008 00000000 l1: .long area |
1321 | 6 000c 00000000 l2: .long function */ | |
7208c779 | 1322 | |
1323 | /* Length in units of the trampoline for entering a nested function. */ | |
65d02209 | 1324 | #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : 16) |
7208c779 | 1325 | |
2e752f00 | 1326 | /* Alignment required for a trampoline in bits. */ |
0dbd1c74 | 1327 | #define TRAMPOLINE_ALIGNMENT \ |
2e752f00 | 1328 | ((CACHE_LOG < 3 \ |
65d02209 | 1329 | || (optimize_size && ! (TARGET_HARD_SH4))) ? 32 \ |
1330 | : 64) | |
7208c779 | 1331 | |
1ae4c297 | 1332 | /* A C expression whose value is RTL representing the value of the return |
1333 | address for the frame COUNT steps up from the current frame. | |
1334 | FRAMEADDR is already the frame pointer of the COUNT frame, so we | |
1335 | can ignore COUNT. */ | |
1ae4c297 | 1336 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
c3583c9c | 1337 | (((COUNT) == 0) ? sh_get_pr_initial_val () : NULL_RTX) |
363600c8 | 1338 | |
1339 | /* A C expression whose value is RTL representing the location of the | |
1340 | incoming return address at the beginning of any function, before the | |
1341 | prologue. This RTL is either a REG, indicating that the return | |
1342 | value is saved in REG, or a MEM representing a location in | |
1343 | the stack. */ | |
65d02209 | 1344 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, PR_REG) |
7208c779 | 1345 | \f |
1346 | /* Addressing modes, and classification of registers for them. */ | |
87e19636 | 1347 | #define HAVE_POST_INCREMENT TARGET_SH1 |
87e19636 | 1348 | #define HAVE_PRE_DECREMENT TARGET_SH1 |
7208c779 | 1349 | |
12132986 | 1350 | #define USE_LOAD_POST_INCREMENT(mode) TARGET_SH1 |
1351 | #define USE_LOAD_PRE_DECREMENT(mode) TARGET_SH2A | |
1352 | #define USE_STORE_POST_INCREMENT(mode) TARGET_SH2A | |
1353 | #define USE_STORE_PRE_DECREMENT(mode) TARGET_SH1 | |
53bd09ab | 1354 | |
1878fb5b | 1355 | /* If a memory clear move would take CLEAR_RATIO or more simple |
1356 | move-instruction pairs, we will do a setmem instead. */ | |
1357 | ||
1358 | #define CLEAR_RATIO(speed) ((speed) ? 15 : 3) | |
1359 | ||
7208c779 | 1360 | /* Macros to check register numbers against specific register classes. */ |
1361 | ||
1362 | /* These assume that REGNO is a hard or pseudo reg number. | |
1363 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1364 | or a pseudo reg currently allocated to a suitable hard reg. | |
1365 | Since they use reg_renumber, they are safe only once reg_renumber | |
957b2bdc | 1366 | has been allocated, which happens in reginfo.c during register |
1367 | allocation. */ | |
9d1ff654 | 1368 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
e2142b04 | 1369 | (GENERAL_OR_AP_REGISTER_P (REGNO) \ |
1370 | || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)])) | |
9d1ff654 | 1371 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
65d02209 | 1372 | ((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG) |
7208c779 | 1373 | |
bcc58dc6 | 1374 | /* True if SYMBOL + OFFSET constants must refer to something within |
1375 | SYMBOL's section. */ | |
1376 | #define SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P TARGET_FDPIC | |
1377 | ||
641e8334 | 1378 | /* Maximum number of registers that can appear in a valid memory |
1379 | address. */ | |
97595bfd | 1380 | #define MAX_REGS_PER_ADDRESS 2 |
7208c779 | 1381 | |
1382 | /* Recognize any constant value that is a valid address. */ | |
9d1ff654 | 1383 | #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) |
7208c779 | 1384 | |
7208c779 | 1385 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1386 | and check its validity for a certain class. | |
36fa166c | 1387 | The suitable hard regs are always accepted and all pseudo regs |
1388 | are also accepted if STRICT is not set. */ | |
1389 | ||
1390 | /* Nonzero if X is a reg that can be used as a base reg. */ | |
1391 | #define REG_OK_FOR_BASE_P(X, STRICT) \ | |
1392 | (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \ | |
1393 | || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) | |
1394 | ||
1395 | /* Nonzero if X is a reg that can be used as an index. */ | |
1396 | #define REG_OK_FOR_INDEX_P(X, STRICT) \ | |
65d02209 | 1397 | ((REGNO (X) == R0_REG) \ |
36fa166c | 1398 | || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) |
1399 | ||
1400 | /* Nonzero if X/OFFSET is a reg that can be used as an index. */ | |
1401 | #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \ | |
65d02209 | 1402 | ((REGNO (X) == R0_REG && OFFSET == 0) \ |
36fa166c | 1403 | || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) |
97595bfd | 1404 | |
abff7a2e | 1405 | /* Macros for extra constraints. */ |
97595bfd | 1406 | |
6c049e03 | 1407 | #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \ |
abff7a2e | 1408 | ((GET_CODE ((OP)) == LABEL_REF) \ |
1409 | || (GET_CODE ((OP)) == CONST \ | |
1410 | && GET_CODE (XEXP ((OP), 0)) == PLUS \ | |
1411 | && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \ | |
cbb16986 | 1412 | && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))) |
af2c1324 | 1413 | |
abff7a2e | 1414 | #define IS_NON_EXPLICIT_CONSTANT_P(OP) \ |
1415 | (CONSTANT_P (OP) \ | |
6c049e03 | 1416 | && !CONST_INT_P (OP) \ |
abff7a2e | 1417 | && GET_CODE (OP) != CONST_DOUBLE \ |
1418 | && (!flag_pic \ | |
1419 | || (LEGITIMATE_PIC_OPERAND_P (OP) \ | |
20ba855a | 1420 | && !PIC_ADDR_P (OP) \ |
abff7a2e | 1421 | && GET_CODE (OP) != LABEL_REF))) |
561c35b4 | 1422 | |
87e19636 | 1423 | #define GOT_ENTRY_P(OP) \ |
1424 | (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
1425 | && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT) | |
1426 | ||
1427 | #define GOTPLT_ENTRY_P(OP) \ | |
1428 | (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
1429 | && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT) | |
1430 | ||
2aa0e8cc | 1431 | #define UNSPEC_GOTOFF_P(OP) \ |
1432 | (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF) | |
1433 | ||
87e19636 | 1434 | #define GOTOFF_P(OP) \ |
2aa0e8cc | 1435 | (GET_CODE (OP) == CONST \ |
1436 | && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \ | |
1437 | || (GET_CODE (XEXP ((OP), 0)) == PLUS \ | |
6c049e03 | 1438 | && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \ |
cbb16986 | 1439 | && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))) |
87e19636 | 1440 | |
1441 | #define PIC_ADDR_P(OP) \ | |
1442 | (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
1443 | && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC) | |
1444 | ||
20ba855a | 1445 | #define PCREL_SYMOFF_P(OP) \ |
1446 | (GET_CODE (OP) == CONST \ | |
1447 | && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
1448 | && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF) | |
af2c1324 | 1449 | |
87e19636 | 1450 | #define NON_PIC_REFERENCE_P(OP) \ |
1451 | (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \ | |
59312820 | 1452 | || (GET_CODE (OP) == CONST \ |
1453 | && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \ | |
65d02209 | 1454 | || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF)) \ |
87e19636 | 1455 | || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \ |
1456 | && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \ | |
65d02209 | 1457 | || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF) \ |
cbb16986 | 1458 | && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))) |
87e19636 | 1459 | |
1460 | #define PIC_REFERENCE_P(OP) \ | |
1461 | (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \ | |
1462 | || GOTOFF_P (OP) || PIC_ADDR_P (OP)) | |
1463 | ||
36fa166c | 1464 | #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \ |
cbb16986 | 1465 | ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \ |
36fa166c | 1466 | || (GET_CODE (X) == SUBREG \ |
1467 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \ | |
59312820 | 1468 | GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \ |
cbb16986 | 1469 | && REG_P (SUBREG_REG (X)) \ |
36fa166c | 1470 | && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT))) |
7208c779 | 1471 | |
8e5606b5 | 1472 | /* Since this must be r0, which is a single register class, we must check |
1473 | SUBREGs more carefully, to be sure that we don't accept one that extends | |
1474 | outside the class. */ | |
36fa166c | 1475 | #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \ |
cbb16986 | 1476 | ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \ |
36fa166c | 1477 | || (GET_CODE (X) == SUBREG \ |
59312820 | 1478 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \ |
1479 | GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \ | |
cbb16986 | 1480 | && REG_P (SUBREG_REG (X)) \ |
36fa166c | 1481 | && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT))) |
1482 | ||
1483 | #ifdef REG_OK_STRICT | |
1484 | #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true) | |
1485 | #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true) | |
1486 | #else | |
1487 | #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false) | |
1488 | #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false) | |
1489 | #endif | |
7208c779 | 1490 | |
641e8334 | 1491 | \f |
35b7d8f7 | 1492 | /* A C compound statement that attempts to replace X, which is an address |
1493 | that needs reloading, with a valid memory address for an operand of | |
299fa1f5 | 1494 | mode MODE. WIN is a C statement label elsewhere in the code. */ |
35b7d8f7 | 1495 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
299fa1f5 | 1496 | do { \ |
1497 | if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \ | |
35b7d8f7 | 1498 | goto WIN; \ |
299fa1f5 | 1499 | } while (0) |
7208c779 | 1500 | \f |
1501 | /* Specify the machine mode that this machine uses | |
1502 | for the index in the tablejump instruction. */ | |
9df2aa62 | 1503 | #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode) |
7208c779 | 1504 | |
9eaab178 | 1505 | #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ |
1506 | ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \ | |
9eaab178 | 1507 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ |
a8c876a4 | 1508 | : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ |
1509 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ | |
9eaab178 | 1510 | : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \ |
1511 | : SImode) | |
1512 | ||
25d1d1e9 | 1513 | /* Define as C expression which evaluates to nonzero if the tablejump |
1514 | instruction expects the table to contain offsets from the address of the | |
1515 | table. | |
9df03d69 | 1516 | Do not define this if the table should contain absolute addresses. */ |
25d1d1e9 | 1517 | #define CASE_VECTOR_PC_RELATIVE 1 |
7208c779 | 1518 | |
87e19636 | 1519 | /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */ |
1520 | #define FLOAT_TYPE_SIZE 32 | |
1521 | ||
87ed74ef | 1522 | /* Since the SH2e has only `float' support, it is desirable to make all |
07a356f1 | 1523 | floating point types equivalent to `float'. */ |
09c4fd25 | 1524 | #define DOUBLE_TYPE_SIZE (TARGET_FPU_SINGLE_ONLY ? 32 : 64) |
07a356f1 | 1525 | |
641e8334 | 1526 | /* 'char' is signed by default. */ |
7208c779 | 1527 | #define DEFAULT_SIGNED_CHAR 1 |
1528 | ||
1529 | /* The type of size_t unsigned int. */ | |
65d02209 | 1530 | #define SIZE_TYPE ("unsigned int") |
87e19636 | 1531 | |
87e19636 | 1532 | #undef PTRDIFF_TYPE |
65d02209 | 1533 | #define PTRDIFF_TYPE ("int") |
7208c779 | 1534 | |
2e3d4844 | 1535 | #define WCHAR_TYPE "short unsigned int" |
1536 | #define WCHAR_TYPE_SIZE 16 | |
3f67d569 | 1537 | |
1538 | #define SH_ELF_WCHAR_TYPE "long int" | |
2e3d4844 | 1539 | |
7208c779 | 1540 | /* Max number of bytes we can move from memory to memory |
1541 | in one reasonably fast instruction. */ | |
65d02209 | 1542 | #define MOVE_MAX (4) |
87e19636 | 1543 | |
1544 | /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever | |
1545 | MOVE_MAX is not a compile-time constant. */ | |
1546 | #define MAX_MOVE_MAX 8 | |
7208c779 | 1547 | |
53bd09ab | 1548 | /* Max number of bytes we want move_by_pieces to be able to copy |
1549 | efficiently. */ | |
65d02209 | 1550 | #define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4) |
53bd09ab | 1551 | |
29701bb8 | 1552 | /* Define if operations between registers always perform the operation |
1553 | on the full register even if a narrower mode is specified. */ | |
94f1fba7 | 1554 | #define WORD_REGISTER_OPERATIONS 1 |
29701bb8 | 1555 | |
1556 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1557 | will either zero-extend or sign-extend. The value of this macro should | |
1558 | be the code that says which one of the two operations is implicitly | |
7d8567f5 | 1559 | done, UNKNOWN if none. */ |
65d02209 | 1560 | #define LOAD_EXTEND_OP(MODE) ((MODE) != SImode ? SIGN_EXTEND : UNKNOWN) |
7208c779 | 1561 | |
cfbbbcdb | 1562 | /* Define if loading short immediate values into registers sign extends. */ |
d0b99710 | 1563 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
cfbbbcdb | 1564 | |
b3b66a54 | 1565 | /* Nonzero if access to memory by bytes is no faster than for words. */ |
1566 | #define SLOW_BYTE_ACCESS 1 | |
1567 | ||
5e3df43c | 1568 | /* Nonzero if the target supports dynamic shift instructions |
1569 | like shad and shld. */ | |
1570 | #define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) | |
1571 | ||
6e7c6395 | 1572 | /* The cost of using the dynamic shift insns (shad, shld) are the same |
1573 | if they are available. If they are not available a library function will | |
1574 | be emitted instead, which is more expensive. */ | |
1575 | #define SH_DYNAMIC_SHIFT_COST (TARGET_DYNSHIFT ? 1 : 20) | |
1576 | ||
1577 | /* Defining SHIFT_COUNT_TRUNCATED tells the combine pass that code like | |
1578 | (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
1579 | This is not generally true when hardware dynamic shifts (shad, shld) are | |
1580 | used, because they check the sign bit _before_ the modulo op. The sign | |
1581 | bit determines whether it is a left shift or a right shift: | |
1582 | if (Y < 0) | |
1583 | return X << (Y & 31); | |
1584 | else | |
1585 | return X >> (-Y) & 31); | |
1586 | ||
1587 | The dynamic shift library routines in lib1funcs.S do not use the sign bit | |
1588 | like the hardware dynamic shifts and truncate the shift count to 31. | |
1589 | We define SHIFT_COUNT_TRUNCATED to 0 and express the implied shift count | |
1590 | truncation in the library function call patterns, as this gives slightly | |
1591 | more compact code. */ | |
1592 | #define SHIFT_COUNT_TRUNCATED (0) | |
7208c779 | 1593 | |
7208c779 | 1594 | /* All integers have the same format so truncation is easy. */ |
65d02209 | 1595 | #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) (true) |
7208c779 | 1596 | |
1597 | /* Define this if addresses of constant functions | |
1598 | shouldn't be put through pseudo regs where they can be cse'd. | |
1599 | Desirable on machines where ordinary constants are expensive | |
1600 | but a CALL with constant address is cheap. */ | |
1601 | /*#define NO_FUNCTION_CSE 1*/ | |
1602 | ||
641e8334 | 1603 | /* The machine modes of pointers and functions. */ |
65d02209 | 1604 | #define Pmode (SImode) |
7208c779 | 1605 | #define FUNCTION_MODE Pmode |
1606 | ||
13d406a0 | 1607 | /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2 |
1608 | are actually function calls with some special constraints on arguments | |
1609 | and register usage. | |
97595bfd | 1610 | |
641e8334 | 1611 | These macros tell reorg that the references to arguments and |
1612 | register clobbers for insns of type sfunc do not appear to happen | |
97595bfd | 1613 | until after the millicode call. This allows reorg to put insns |
1614 | which set the argument registers into the delay slot of the millicode | |
1615 | call -- thus they act more like traditional CALL_INSNs. | |
1616 | ||
75e90991 | 1617 | get_attr_is_sfunc will try to recognize the given insn, so make sure to |
97595bfd | 1618 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns |
1619 | in particular. */ | |
1620 | ||
1621 | #define INSN_SETS_ARE_DELAYED(X) \ | |
6c049e03 | 1622 | ((NONJUMP_INSN_P (X) \ |
97595bfd | 1623 | && GET_CODE (PATTERN (X)) != SEQUENCE \ |
1624 | && GET_CODE (PATTERN (X)) != USE \ | |
1625 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
75e90991 | 1626 | && get_attr_is_sfunc (X))) |
97595bfd | 1627 | |
1628 | #define INSN_REFERENCES_ARE_DELAYED(X) \ | |
6c049e03 | 1629 | ((NONJUMP_INSN_P (X) \ |
97595bfd | 1630 | && GET_CODE (PATTERN (X)) != SEQUENCE \ |
1631 | && GET_CODE (PATTERN (X)) != USE \ | |
1632 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
75e90991 | 1633 | && get_attr_is_sfunc (X))) |
97595bfd | 1634 | |
0abf894c | 1635 | \f |
1636 | /* Position Independent Code. */ | |
0abf894c | 1637 | |
2607b1ba | 1638 | /* We can't directly access anything that contains a symbol, |
1639 | nor can we indirect via the constant pool. */ | |
1640 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
1fe27026 | 1641 | ((! nonpic_symbol_mentioned_p (X) \ |
1642 | && (GET_CODE (X) != SYMBOL_REF \ | |
1643 | || ! CONSTANT_POOL_ADDRESS_P (X) \ | |
65d02209 | 1644 | || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))) |
2607b1ba | 1645 | |
0abf894c | 1646 | #define SYMBOLIC_CONST_P(X) \ |
1647 | ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \ | |
1648 | && nonpic_symbol_mentioned_p (X)) | |
1649 | \f | |
7208c779 | 1650 | /* Compute extra cost of moving data between one register class |
0dbd1c74 | 1651 | and another. */ |
7208c779 | 1652 | |
e04da7b6 | 1653 | /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass |
1654 | uses this information. Hence, the general register <-> floating point | |
1b61190c | 1655 | register information here is not used for SFmode. */ |
49607c69 | 1656 | #define REGCLASS_HAS_GENERAL_REG(CLASS) \ |
2a0b1a37 | 1657 | ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \ |
65d02209 | 1658 | || ((CLASS) == SIBCALL_REGS)) |
71c9de4b | 1659 | |
49607c69 | 1660 | #define REGCLASS_HAS_FP_REG(CLASS) \ |
1661 | ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \ | |
ec3c739c | 1662 | || (CLASS) == DF_REGS) |
49607c69 | 1663 | |
05f17f54 | 1664 | /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This |
5e164fba | 1665 | would be so that people with slow memory systems could generate |
05f17f54 | 1666 | different code that does fewer memory accesses. */ |
5e164fba | 1667 | |
1668 | /* A C expression for the cost of a branch instruction. A value of 1 | |
96d93b11 | 1669 | is the default; other values are interpreted relative to that. */ |
1670 | #define BRANCH_COST(speed_p, predictable_p) sh_branch_cost | |
7208c779 | 1671 | \f |
641e8334 | 1672 | /* Assembler output control. */ |
7208c779 | 1673 | |
61322ae9 | 1674 | /* A C string constant describing how to begin a comment in the target |
1675 | assembler language. The compiler assumes that the comment will end at | |
1676 | the end of the line. */ | |
1677 | #define ASM_COMMENT_START "!" | |
1678 | ||
97595bfd | 1679 | #define ASM_APP_ON "" |
1680 | #define ASM_APP_OFF "" | |
1681 | #define FILE_ASM_OP "\t.file\n" | |
327b40b7 | 1682 | #define SET_ASM_OP "\t.set\t" |
7208c779 | 1683 | |
641e8334 | 1684 | /* How to change between sections. */ |
65d02209 | 1685 | #define TEXT_SECTION_ASM_OP "\t.text" |
6c049e03 | 1686 | #define DATA_SECTION_ASM_OP "\t.data" |
47c009e5 | 1687 | |
87e19636 | 1688 | #if defined CRT_BEGIN || defined CRT_END |
1689 | /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */ | |
65d02209 | 1690 | #undef TEXT_SECTION_ASM_OP |
1691 | #define TEXT_SECTION_ASM_OP "\t.text" | |
87e19636 | 1692 | #endif |
1693 | ||
ea50d488 | 1694 | #ifndef BSS_SECTION_ASM_OP |
327b40b7 | 1695 | #define BSS_SECTION_ASM_OP "\t.section\t.bss" |
ea50d488 | 1696 | #endif |
1697 | ||
ea50d488 | 1698 | #ifndef ASM_OUTPUT_ALIGNED_BSS |
1699 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
1700 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
1701 | #endif | |
1702 | ||
12e95e94 | 1703 | /* Define this so that jump tables go in same section as the current function, |
1704 | which could be text or it could be a user defined section. */ | |
6b5be7f8 | 1705 | #define JUMP_TABLES_IN_TEXT_SECTION 1 |
12e95e94 | 1706 | |
641e8334 | 1707 | #undef DO_GLOBAL_CTORS_BODY |
47c009e5 | 1708 | #define DO_GLOBAL_CTORS_BODY \ |
1709 | { \ | |
6392d503 | 1710 | typedef void (*pfunc) (void); \ |
47c009e5 | 1711 | extern pfunc __ctors[]; \ |
1712 | extern pfunc __ctors_end[]; \ | |
1713 | pfunc *p; \ | |
2c5a14aa | 1714 | for (p = __ctors_end; p > __ctors; ) \ |
47c009e5 | 1715 | { \ |
2c5a14aa | 1716 | (*--p)(); \ |
47c009e5 | 1717 | } \ |
641e8334 | 1718 | } |
47c009e5 | 1719 | |
641e8334 | 1720 | #undef DO_GLOBAL_DTORS_BODY |
9d1ff654 | 1721 | #define DO_GLOBAL_DTORS_BODY \ |
47c009e5 | 1722 | { \ |
6392d503 | 1723 | typedef void (*pfunc) (void); \ |
47c009e5 | 1724 | extern pfunc __dtors[]; \ |
1725 | extern pfunc __dtors_end[]; \ | |
1726 | pfunc *p; \ | |
1727 | for (p = __dtors; p < __dtors_end; p++) \ | |
1728 | { \ | |
1729 | (*p)(); \ | |
1730 | } \ | |
641e8334 | 1731 | } |
47c009e5 | 1732 | |
47c009e5 | 1733 | #define ASM_OUTPUT_REG_PUSH(file, v) \ |
59312820 | 1734 | { \ |
65d02209 | 1735 | fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \ |
59312820 | 1736 | } |
7208c779 | 1737 | |
47c009e5 | 1738 | #define ASM_OUTPUT_REG_POP(file, v) \ |
59312820 | 1739 | { \ |
65d02209 | 1740 | fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \ |
59312820 | 1741 | } |
47c009e5 | 1742 | |
641e8334 | 1743 | /* DBX register number for a given compiler register number. */ |
07a356f1 | 1744 | /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers |
1745 | to match gdb. */ | |
805e22b2 | 1746 | /* expand_builtin_init_dwarf_reg_sizes uses this to test if a |
1747 | register exists, so we should return -1 for invalid register numbers. */ | |
3f67d569 | 1748 | #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO) |
1749 | ||
1750 | #define SH_DBX_REGISTER_NUMBER(REGNO) \ | |
7a1492b5 | 1751 | (IN_RANGE ((REGNO), \ |
1752 | (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ | |
65d02209 | 1753 | FIRST_GENERAL_REG + 15U) \ |
41fafa66 | 1754 | ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \ |
6c049e03 | 1755 | : ((int) (REGNO) >= FIRST_FP_REG \ |
7a1492b5 | 1756 | && ((int) (REGNO) \ |
65d02209 | 1757 | <= (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)))) \ |
1758 | ? ((unsigned) (REGNO) - FIRST_FP_REG + 25) \ | |
87e19636 | 1759 | : XD_REGISTER_P (REGNO) \ |
65d02209 | 1760 | ? ((unsigned) (REGNO) - FIRST_XD_REG + 87) \ |
87e19636 | 1761 | : (REGNO) == PR_REG \ |
65d02209 | 1762 | ? (17) \ |
87e19636 | 1763 | : (REGNO) == GBR_REG \ |
65d02209 | 1764 | ? (18) \ |
87e19636 | 1765 | : (REGNO) == MACH_REG \ |
65d02209 | 1766 | ? (20) \ |
87e19636 | 1767 | : (REGNO) == MACL_REG \ |
65d02209 | 1768 | ? (21) \ |
c5cff8fc | 1769 | : (REGNO) == T_REG \ |
65d02209 | 1770 | ? (22) \ |
87e19636 | 1771 | : (REGNO) == FPUL_REG \ |
65d02209 | 1772 | ? (23) \ |
c5cff8fc | 1773 | : (REGNO) == FPSCR_REG \ |
65d02209 | 1774 | ? (24) \ |
41fafa66 | 1775 | : (unsigned) -1) |
87e19636 | 1776 | |
7208c779 | 1777 | /* This is how to output an assembler line |
1778 | that says to advance the location counter | |
1779 | to a multiple of 2**LOG bytes. */ | |
1780 | ||
1781 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1782 | if ((LOG) != 0) \ | |
0dbd1c74 | 1783 | fprintf ((FILE), "\t.align %d\n", (LOG)) |
7208c779 | 1784 | |
0036ad94 | 1785 | /* Globalizing directive for a label. */ |
1786 | #define GLOBAL_ASM_OP "\t.global\t" | |
7208c779 | 1787 | |
6c049e03 | 1788 | /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ |
7208c779 | 1789 | |
641e8334 | 1790 | /* Output a relative address table. */ |
6c049e03 | 1791 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ |
9eaab178 | 1792 | switch (GET_MODE (BODY)) \ |
0dbd1c74 | 1793 | { \ |
916ace94 | 1794 | case E_SImode: \ |
0dbd1c74 | 1795 | asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \ |
1796 | break; \ | |
916ace94 | 1797 | case E_HImode: \ |
0dbd1c74 | 1798 | asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \ |
1799 | break; \ | |
916ace94 | 1800 | case E_QImode: \ |
0dbd1c74 | 1801 | asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \ |
1802 | break; \ | |
b7dbbdb2 | 1803 | default: \ |
1804 | break; \ | |
0dbd1c74 | 1805 | } |
7208c779 | 1806 | |
641e8334 | 1807 | /* Output an absolute table element. */ |
97595bfd | 1808 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ |
9df2aa62 | 1809 | if (! optimize || TARGET_BIGTABLE) \ |
87ab0a3d | 1810 | asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \ |
97595bfd | 1811 | else \ |
87ab0a3d | 1812 | asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); |
7208c779 | 1813 | |
7208c779 | 1814 | \f |
0dbd1c74 | 1815 | /* A C statement to be executed just prior to the output of |
1816 | assembler code for INSN, to modify the extracted operands so | |
1817 | they will be output differently. | |
1818 | ||
1819 | Here the argument OPVEC is the vector containing the operands | |
1820 | extracted from INSN, and NOPERANDS is the number of elements of | |
1821 | the vector which contain meaningful data for this insn. | |
1822 | The contents of this vector are what will be used to convert the insn | |
1823 | template into assembler code, so you can change the assembler output | |
1824 | by changing the contents of the vector. */ | |
9d1ff654 | 1825 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
0dbd1c74 | 1826 | final_prescan_insn ((INSN), (OPVEC), (NOPERANDS)) |
7208c779 | 1827 | |
641e8334 | 1828 | /* Which processor to schedule for. The elements of the enumeration must |
1829 | match exactly the cpu attribute in the sh.md file. */ | |
641e8334 | 1830 | enum processor_type { |
641e8334 | 1831 | PROCESSOR_SH1, |
1832 | PROCESSOR_SH2, | |
87ed74ef | 1833 | PROCESSOR_SH2E, |
7105fb72 | 1834 | PROCESSOR_SH2A, |
07a356f1 | 1835 | PROCESSOR_SH3, |
1b61190c | 1836 | PROCESSOR_SH3E, |
87e19636 | 1837 | PROCESSOR_SH4, |
65d02209 | 1838 | PROCESSOR_SH4A |
641e8334 | 1839 | }; |
1840 | ||
1841 | #define sh_cpu_attr ((enum attr_cpu)sh_cpu) | |
1842 | extern enum processor_type sh_cpu; | |
1843 | ||
0dbd1c74 | 1844 | enum mdep_reorg_phase_e |
1845 | { | |
1846 | SH_BEFORE_MDEP_REORG, | |
1847 | SH_INSERT_USES_LABELS, | |
1848 | SH_SHORTEN_BRANCHES0, | |
1849 | SH_FIXUP_PCLOAD, | |
1850 | SH_SHORTEN_BRANCHES1, | |
1851 | SH_AFTER_MDEP_REORG | |
1852 | }; | |
1853 | ||
9eaab178 | 1854 | extern enum mdep_reorg_phase_e mdep_reorg_phase; |
1855 | ||
7b23765d | 1856 | /* Handle Renesas compiler's pragmas. */ |
eb180587 | 1857 | #define REGISTER_TARGET_PRAGMAS() do { \ |
1858 | c_register_pragma (0, "interrupt", sh_pr_interrupt); \ | |
1859 | c_register_pragma (0, "trapa", sh_pr_trapa); \ | |
1860 | c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \ | |
1fcd08b1 | 1861 | } while (0) |
47c009e5 | 1862 | |
57d5535b | 1863 | extern tree sh_deferred_function_attributes; |
1864 | extern tree *sh_deferred_function_attributes_tail; | |
47c009e5 | 1865 | |
0d687b6d | 1866 | |
bacf717a | 1867 | \f |
2522e445 | 1868 | /* Instructions with unfilled delay slots take up an |
1869 | extra two bytes for the nop in the delay slot. | |
1870 | sh-dsp parallel processing insns are four bytes long. */ | |
bacf717a | 1871 | #define ADJUST_INSN_LENGTH(X, LENGTH) \ |
2522e445 | 1872 | (LENGTH) += sh_insn_length_adjustment (X); |
9d1ff654 | 1873 | \f |
9d1ff654 | 1874 | /* Define this macro if it is advisable to hold scalars in registers |
894b8fd9 | 1875 | in a wider mode than that declared by the program. In such cases, |
9d1ff654 | 1876 | the value is constrained to be within the bounds of the declared |
1877 | type, but kept valid in the wider mode. The signedness of the | |
1878 | extension may differ from that of the type. | |
1879 | ||
1880 | Leaving the unsignedp unchanged gives better code than always setting it | |
1881 | to 0. This is despite the fact that we have only signed char and short | |
1882 | load instructions. */ | |
1883 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
1884 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
59312820 | 1885 | && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\ |
a0b78918 | 1886 | (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), (MODE) = SImode; |
9d1ff654 | 1887 | |
65d02209 | 1888 | #define MAX_FIXED_MODE_SIZE (64) |
030466b7 | 1889 | |
992d172c | 1890 | /* Better to allocate once the maximum space for outgoing args in the |
1891 | prologue rather than duplicate around each call. */ | |
1892 | #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS | |
9d1ff654 | 1893 | |
18862b5a | 1894 | #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE } |
1895 | ||
09c4fd25 | 1896 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_FPU_DOUBLE) |
18862b5a | 1897 | |
ab5ad604 | 1898 | #define ACTUAL_NORMAL_MODE(ENTITY) \ |
1899 | (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE) | |
1900 | ||
7dff60c8 | 1901 | #define NORMAL_MODE(ENTITY) \ |
36a2dfdb | 1902 | (sh_cfun_interrupt_handler_p () \ |
1903 | ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \ | |
ab5ad604 | 1904 | : ACTUAL_NORMAL_MODE (ENTITY)) |
7dff60c8 | 1905 | |
910d6e82 | 1906 | #define EPILOGUE_USES(REGNO) (TARGET_FPU_ANY && REGNO == FPSCR_REG) |
18862b5a | 1907 | |
65d02209 | 1908 | #define DWARF_FRAME_RETURN_COLUMN (DWARF_FRAME_REGNUM (PR_REG)) |
363600c8 | 1909 | |
65d02209 | 1910 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 4U : INVALID_REGNUM) |
805e22b2 | 1911 | |
41fafa66 | 1912 | #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM |
1913 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) | |
805e22b2 | 1914 | |
7a1492b5 | 1915 | /* We have to distinguish between code and data, so that we apply |
06e58b52 | 1916 | datalabel where and only where appropriate. Use sdataN for data. */ |
7a1492b5 | 1917 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
bcc58dc6 | 1918 | ((TARGET_FDPIC \ |
1919 | ? ((GLOBAL) ? DW_EH_PE_indirect | DW_EH_PE_datarel : DW_EH_PE_pcrel) \ | |
1920 | : ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \ | |
1921 | | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))) \ | |
65d02209 | 1922 | | ((CODE) ? 0 : DW_EH_PE_sdata4)) |
7a1492b5 | 1923 | |
1924 | /* Handle special EH pointer encodings. Absolute, pc-relative, and | |
1925 | indirect are handled automatically. */ | |
1926 | #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \ | |
1927 | do { \ | |
06e58b52 | 1928 | if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \ |
1929 | && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \ | |
7a1492b5 | 1930 | { \ |
1a6a7a27 | 1931 | gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \ |
7a1492b5 | 1932 | SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \ |
1933 | if (0) goto DONE; \ | |
1934 | } \ | |
bcc58dc6 | 1935 | if (TARGET_FDPIC \ |
1936 | && ((ENCODING) & 0xf0) == (DW_EH_PE_indirect | DW_EH_PE_datarel)) \ | |
1937 | { \ | |
1938 | fputs ("\t.ualong ", FILE); \ | |
1939 | output_addr_const (FILE, ADDR); \ | |
1940 | if (GET_CODE (ADDR) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (ADDR)) \ | |
1941 | fputs ("@GOTFUNCDESC", FILE); \ | |
1942 | else \ | |
1943 | fputs ("@GOT", FILE); \ | |
1944 | goto DONE; \ | |
1945 | } \ | |
7a1492b5 | 1946 | } while (0) |
1947 | ||
65d02209 | 1948 | #if (defined CRT_BEGIN || defined CRT_END) |
0abf894c | 1949 | /* SH constant pool breaks the devices in crtstuff.c to control section |
1950 | in where code resides. We have to write it as asm code. */ | |
e1ff7102 | 1951 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ |
1952 | asm (SECTION_OP "\n\ | |
1953 | mov.l 1f,r1\n\ | |
0abf894c | 1954 | mova 2f,r0\n\ |
1955 | braf r1\n\ | |
1956 | lds r0,pr\n\ | |
1957 | 0: .p2align 2\n\ | |
e1ff7102 | 1958 | 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\ |
1959 | 2:\n" TEXT_SECTION_ASM_OP); | |
65d02209 | 1960 | #endif /* (defined CRT_BEGIN || defined CRT_END) */ |
1fcd08b1 | 1961 | |
2a281353 | 1962 | #endif /* ! GCC_SH_H */ |