]>
Commit | Line | Data |
---|---|---|
7b23765d | 1 | /* Definitions of target machine for GNU compiler for Renesas / SuperH SH. |
f1717362 | 2 | Copyright (C) 1993-2016 Free Software Foundation, Inc. |
dda0acb2 | 3 | Contributed by Steve Chamberlain (sac@cygnus.com). |
4 | Improved by Jim Wilson (wilson@cygnus.com). | |
7208c779 | 5 | |
187b36cf | 6 | This file is part of GCC. |
7208c779 | 7 | |
187b36cf | 8 | GCC is free software; you can redistribute it and/or modify |
7208c779 | 9 | it under the terms of the GNU General Public License as published by |
038d1e19 | 10 | the Free Software Foundation; either version 3, or (at your option) |
7208c779 | 11 | any later version. |
12 | ||
187b36cf | 13 | GCC is distributed in the hope that it will be useful, |
7208c779 | 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
038d1e19 | 19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
7208c779 | 21 | |
1fcd08b1 | 22 | #ifndef GCC_SH_H |
23 | #define GCC_SH_H | |
97a18f26 | 24 | |
a9cfe83b | 25 | #include "config/vxworks-dummy.h" |
26 | ||
0dbd1c74 | 27 | /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't |
805e22b2 | 28 | include it here, because bconfig.h is also included by gencodes.c . */ |
5645dcc7 | 29 | /* ??? No longer true. */ |
0dbd1c74 | 30 | extern int code_for_indirect_jump_scratch; |
31 | ||
cfaba078 | 32 | #define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile) |
3dfc1807 | 33 | |
992d172c | 34 | /* Value should be nonzero if functions must have frame pointers. |
35 | Zero means the frame pointer need not be set up (and parms may be accessed | |
36 | via the stack pointer) in functions that seem suitable. */ | |
37 | ||
38 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
39 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
40 | #endif | |
97595bfd | 41 | |
7208c779 | 42 | \f |
92c473b8 | 43 | /* Nonzero if this is an ELF target - compile time only */ |
44 | #define TARGET_ELF 0 | |
45 | ||
87ed74ef | 46 | /* Nonzero if we should generate code using type 2E insns. */ |
156fac8b | 47 | #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E) |
87ed74ef | 48 | |
7105fb72 | 49 | /* Nonzero if we should generate code using type 2A insns. */ |
156fac8b | 50 | #define TARGET_SH2A TARGET_HARD_SH2A |
7105fb72 | 51 | /* Nonzero if we should generate code using type 2A SF insns. */ |
156fac8b | 52 | #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E) |
7105fb72 | 53 | /* Nonzero if we should generate code using type 2A DF insns. */ |
156fac8b | 54 | #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A) |
7208c779 | 55 | |
07a356f1 | 56 | /* Nonzero if we should generate code using type 3E insns. */ |
156fac8b | 57 | #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E) |
07a356f1 | 58 | |
9df03d69 | 59 | /* Nonzero if we schedule for a superscalar implementation. */ |
2e752f00 | 60 | #define TARGET_SUPERSCALAR (TARGET_HARD_SH4 || TARGET_SH2A) |
1b61190c | 61 | |
87e19636 | 62 | /* Nonzero if a double-precision FPU is available. */ |
746b7c9e | 63 | #define TARGET_FPU_DOUBLE \ |
64 | ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE) | |
87e19636 | 65 | |
66 | /* Nonzero if an FPU is available. */ | |
87ed74ef | 67 | #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE) |
87e19636 | 68 | |
1b61190c | 69 | /* Nonzero if we should generate code using type 4 insns. */ |
156fac8b | 70 | #undef TARGET_SH4 |
71 | #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1) | |
87e19636 | 72 | |
9435e831 | 73 | /* Nonzero if we're generating code for SH4a, unless the use of the |
74 | FPU is disabled (which makes it compatible with SH4al-dsp). */ | |
5b271aff | 75 | #define TARGET_SH4A_FP (TARGET_SH4A && TARGET_FPU_ANY) |
9435e831 | 76 | |
87e19636 | 77 | /* Nonzero if we should generate code using the SHcompact instruction |
78 | set and 32-bit ABI. */ | |
79 | #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1) | |
80 | ||
81 | /* Nonzero if we should generate code using the SHmedia instruction | |
82 | set and ABI. */ | |
83 | #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1) | |
1b61190c | 84 | |
87e19636 | 85 | /* Nonzero if we should generate code using the SHmedia ISA and 32-bit |
86 | ABI. */ | |
156fac8b | 87 | #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E) |
87e19636 | 88 | |
89 | /* Nonzero if we should generate code using the SHmedia ISA and 64-bit | |
90 | ABI. */ | |
156fac8b | 91 | #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E) |
87e19636 | 92 | |
93 | /* Nonzero if we should generate code using SHmedia FPU instructions. */ | |
94 | #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE) | |
8af3db02 | 95 | |
09a512b9 | 96 | /* This is not used by the SH2E calling convention */ |
97 | #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \ | |
98 | (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \ | |
99 | && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL))) | |
100 | ||
07168dd9 | 101 | #ifndef TARGET_CPU_DEFAULT |
102 | #define TARGET_CPU_DEFAULT SELECT_SH1 | |
156fac8b | 103 | #define SUPPORT_SH1 1 |
104 | #define SUPPORT_SH2E 1 | |
105 | #define SUPPORT_SH4 1 | |
106 | #define SUPPORT_SH4_SINGLE 1 | |
107 | #define SUPPORT_SH2A 1 | |
108 | #define SUPPORT_SH2A_SINGLE 1 | |
07168dd9 | 109 | #endif |
110 | ||
59312820 | 111 | #define TARGET_DIVIDE_INV \ |
112 | (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \ | |
113 | || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \ | |
114 | || sh_div_strategy == SH_DIV_INV_CALL \ | |
115 | || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP) | |
116 | #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP) | |
117 | #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP) | |
118 | #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2) | |
119 | #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT) | |
120 | #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U) | |
121 | #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L) | |
122 | #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL) | |
123 | #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2) | |
d6005df3 | 124 | #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) |
125 | #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP) | |
126 | #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE) | |
59312820 | 127 | |
6c049e03 | 128 | #define SELECT_SH1 (MASK_SH1) |
129 | #define SELECT_SH2 (MASK_SH2 | SELECT_SH1) | |
130 | #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \ | |
156fac8b | 131 | | MASK_FPU_SINGLE) |
6c049e03 | 132 | #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \ |
156fac8b | 133 | | MASK_HARD_SH2A_DOUBLE \ |
134 | | MASK_SH2 | MASK_SH1) | |
6c049e03 | 135 | #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1) |
156fac8b | 136 | #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \ |
bb057878 | 137 | | MASK_SH1 | MASK_FPU_SINGLE \ |
138 | | MASK_FPU_SINGLE_ONLY) | |
6c049e03 | 139 | #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \ |
156fac8b | 140 | | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \ |
141 | | MASK_SH2 | MASK_SH1) | |
6c049e03 | 142 | #define SELECT_SH3 (MASK_SH3 | SELECT_SH2) |
143 | #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3) | |
144 | #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3) | |
bb057878 | 145 | #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E \ |
146 | | MASK_FPU_SINGLE_ONLY) | |
6c049e03 | 147 | #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \ |
156fac8b | 148 | | SELECT_SH3) |
6c049e03 | 149 | #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4) |
150 | #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU) | |
156fac8b | 151 | #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) |
6c049e03 | 152 | #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) |
153 | #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) | |
154 | #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4) | |
156fac8b | 155 | #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5) |
6c049e03 | 156 | #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E) |
156fac8b | 157 | #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E) |
6c049e03 | 158 | #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E) |
156fac8b | 159 | #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3) |
07168dd9 | 160 | |
156fac8b | 161 | #if SUPPORT_SH1 |
162 | #define SUPPORT_SH2 1 | |
07168dd9 | 163 | #endif |
156fac8b | 164 | #if SUPPORT_SH2 |
165 | #define SUPPORT_SH3 1 | |
5be30882 | 166 | #define SUPPORT_SH2A_NOFPU 1 |
07168dd9 | 167 | #endif |
156fac8b | 168 | #if SUPPORT_SH3 |
169 | #define SUPPORT_SH4_NOFPU 1 | |
9435e831 | 170 | #endif |
156fac8b | 171 | #if SUPPORT_SH4_NOFPU |
172 | #define SUPPORT_SH4A_NOFPU 1 | |
173 | #define SUPPORT_SH4AL 1 | |
07168dd9 | 174 | #endif |
175 | ||
156fac8b | 176 | #if SUPPORT_SH2E |
177 | #define SUPPORT_SH3E 1 | |
5be30882 | 178 | #define SUPPORT_SH2A_SINGLE_ONLY 1 |
07168dd9 | 179 | #endif |
156fac8b | 180 | #if SUPPORT_SH3E |
181 | #define SUPPORT_SH4_SINGLE_ONLY 1 | |
5be30882 | 182 | #endif |
183 | #if SUPPORT_SH4_SINGLE_ONLY | |
156fac8b | 184 | #define SUPPORT_SH4A_SINGLE_ONLY 1 |
7105fb72 | 185 | #endif |
186 | ||
156fac8b | 187 | #if SUPPORT_SH4 |
188 | #define SUPPORT_SH4A 1 | |
7105fb72 | 189 | #endif |
190 | ||
156fac8b | 191 | #if SUPPORT_SH4_SINGLE |
192 | #define SUPPORT_SH4A_SINGLE 1 | |
07168dd9 | 193 | #endif |
194 | ||
156fac8b | 195 | #if SUPPORT_SH5_COMPAT |
196 | #define SUPPORT_SH5_32MEDIA 1 | |
07168dd9 | 197 | #endif |
198 | ||
156fac8b | 199 | #if SUPPORT_SH5_COMPACT_NOFPU |
200 | #define SUPPORT_SH5_32MEDIA_NOFPU 1 | |
07168dd9 | 201 | #endif |
202 | ||
156fac8b | 203 | #define SUPPORT_ANY_SH5_32MEDIA \ |
204 | (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU) | |
205 | #define SUPPORT_ANY_SH5_64MEDIA \ | |
206 | (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU) | |
207 | #define SUPPORT_ANY_SH5 \ | |
208 | (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA) | |
59312820 | 209 | |
27461bd2 | 210 | /* Reset all target-selection flags. */ |
156fac8b | 211 | #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ |
212 | | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ | |
bb057878 | 213 | | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \ |
214 | | MASK_FPU_SINGLE_ONLY) | |
6c8e3918 | 215 | |
87ab0a3d | 216 | /* This defaults us to big-endian. */ |
217 | #ifndef TARGET_ENDIAN_DEFAULT | |
218 | #define TARGET_ENDIAN_DEFAULT 0 | |
219 | #endif | |
220 | ||
59312820 | 221 | #ifndef TARGET_OPT_DEFAULT |
11e875c9 | 222 | #define TARGET_OPT_DEFAULT 0 |
59312820 | 223 | #endif |
224 | ||
225 | #define TARGET_DEFAULT \ | |
226 | (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT) | |
227 | ||
07168dd9 | 228 | #ifndef SH_MULTILIB_CPU_DEFAULT |
229 | #define SH_MULTILIB_CPU_DEFAULT "m1" | |
493914a8 | 230 | #endif |
231 | ||
07168dd9 | 232 | #if TARGET_ENDIAN_DEFAULT |
233 | #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT } | |
234 | #else | |
235 | #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT } | |
236 | #endif | |
87ab0a3d | 237 | |
238 | #define CPP_SPEC " %(subtarget_cpp_spec) " | |
239 | ||
240 | #ifndef SUBTARGET_CPP_SPEC | |
241 | #define SUBTARGET_CPP_SPEC "" | |
242 | #endif | |
243 | ||
7b635b7e | 244 | #ifndef SUBTARGET_EXTRA_SPECS |
245 | #define SUBTARGET_EXTRA_SPECS | |
246 | #endif | |
247 | ||
87ab0a3d | 248 | #define EXTRA_SPECS \ |
249 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ | |
250 | { "link_emul_prefix", LINK_EMUL_PREFIX }, \ | |
251 | { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \ | |
252 | { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \ | |
253 | { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \ | |
7b635b7e | 254 | { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \ |
c999a707 | 255 | { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \ |
59312820 | 256 | { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \ |
257 | { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ | |
7b635b7e | 258 | SUBTARGET_EXTRA_SPECS |
87ab0a3d | 259 | |
156fac8b | 260 | #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 |
a363d423 | 261 | #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}" |
c999a707 | 262 | #else |
a363d423 | 263 | #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}" |
c999a707 | 264 | #endif |
265 | ||
5e8551bd | 266 | /* Define which ISA type to pass to the assembler. |
267 | For SH4 we pass SH4A to allow using some instructions that are available | |
268 | on some SH4 variants, but officially are part of the SH4A ISA. */ | |
c999a707 | 269 | #define SH_ASM_SPEC \ |
81b46c0d | 270 | "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)} \ |
271 | %(subtarget_asm_isa_spec) %(subtarget_asm_spec) \ | |
5e8551bd | 272 | %{m1:--isa=sh} \ |
273 | %{m2:--isa=sh2} \ | |
274 | %{m2e:--isa=sh2e} \ | |
275 | %{m3:--isa=sh3} \ | |
276 | %{m3e:--isa=sh3e} \ | |
277 | %{m4:--isa=sh4a} \ | |
278 | %{m4-single:--isa=sh4a} \ | |
279 | %{m4-single-only:--isa=sh4a} \ | |
280 | %{m4-nofpu:--isa=sh4a-nofpu} \ | |
281 | %{m4a:--isa=sh4a} \ | |
282 | %{m4a-single:--isa=sh4a} \ | |
283 | %{m4a-single-only:--isa=sh4a} \ | |
284 | %{m4a-nofpu:--isa=sh4a-nofpu} \ | |
59312820 | 285 | %{m2a:--isa=sh2a} \ |
286 | %{m2a-single:--isa=sh2a} \ | |
287 | %{m2a-single-only:--isa=sh2a} \ | |
288 | %{m2a-nofpu:--isa=sh2a-nofpu} \ | |
289 | %{m5-compact*:--isa=SHcompact} \ | |
290 | %{m5-32media*:--isa=SHmedia --abi=32} \ | |
291 | %{m5-64media*:--isa=SHmedia --abi=64} \ | |
292 | %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}" | |
c999a707 | 293 | |
294 | #define ASM_SPEC SH_ASM_SPEC | |
87ab0a3d | 295 | |
296 | #ifndef SUBTARGET_ASM_ENDIAN_SPEC | |
156fac8b | 297 | #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN |
87ab0a3d | 298 | #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}" |
299 | #else | |
300 | #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}" | |
301 | #endif | |
302 | #endif | |
303 | ||
59312820 | 304 | #if STRICT_NOFPU == 1 |
305 | /* Strict nofpu means that the compiler should tell the assembler | |
306 | to reject FPU instructions. E.g. from ASM inserts. */ | |
156fac8b | 307 | #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E) |
59312820 | 308 | #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}" |
309 | #else | |
310 | /* If there were an -isa option for sh5-nofpu then it would also go here. */ | |
311 | #define SUBTARGET_ASM_ISA_SPEC \ | |
312 | "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC | |
313 | #endif | |
314 | #else /* ! STRICT_NOFPU */ | |
315 | #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC | |
316 | #endif | |
c999a707 | 317 | |
59312820 | 318 | #ifndef SUBTARGET_ASM_SPEC |
bcc58dc6 | 319 | #define SUBTARGET_ASM_SPEC "%{mfdpic:--fdpic}" |
59312820 | 320 | #endif |
321 | ||
156fac8b | 322 | #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN |
59312820 | 323 | #define LINK_EMUL_PREFIX "sh%{!mb:l}" |
324 | #else | |
87ab0a3d | 325 | #define LINK_EMUL_PREFIX "sh%{ml:l}" |
59312820 | 326 | #endif |
493914a8 | 327 | |
156fac8b | 328 | #if TARGET_CPU_DEFAULT & MASK_SH5 |
329 | #if TARGET_CPU_DEFAULT & MASK_SH_E | |
493914a8 | 330 | #define LINK_DEFAULT_CPU_EMUL "32" |
156fac8b | 331 | #if TARGET_CPU_DEFAULT & MASK_SH1 |
07168dd9 | 332 | #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact" |
493914a8 | 333 | #else |
07168dd9 | 334 | #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32" |
156fac8b | 335 | #endif /* MASK_SH1 */ |
336 | #else /* !MASK_SH_E */ | |
493914a8 | 337 | #define LINK_DEFAULT_CPU_EMUL "64" |
07168dd9 | 338 | #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64" |
156fac8b | 339 | #endif /* MASK_SH_E */ |
07168dd9 | 340 | #define ASM_ISA_DEFAULT_SPEC \ |
341 | " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}" | |
156fac8b | 342 | #else /* !MASK_SH5 */ |
87ab0a3d | 343 | #define LINK_DEFAULT_CPU_EMUL "" |
07168dd9 | 344 | #define ASM_ISA_DEFAULT_SPEC "" |
156fac8b | 345 | #endif /* MASK_SH5 */ |
493914a8 | 346 | |
bcc58dc6 | 347 | #define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd}" |
87ab0a3d | 348 | #define SUBTARGET_LINK_SPEC "" |
349 | ||
91276c47 | 350 | /* Go via SH_LINK_SPEC to avoid code replication. */ |
87ab0a3d | 351 | #define LINK_SPEC SH_LINK_SPEC |
352 | ||
353 | #define SH_LINK_SPEC "\ | |
354 | -m %(link_emul_prefix)\ | |
355 | %{m5-compact*|m5-32media*:32}\ | |
356 | %{m5-64media*:64}\ | |
357 | %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\ | |
358 | %(subtarget_link_emul_suffix) \ | |
359 | %{mrelax:-relax} %(subtarget_link_spec)" | |
3dfc1807 | 360 | |
59312820 | 361 | #ifndef SH_DIV_STR_FOR_SIZE |
362 | #define SH_DIV_STR_FOR_SIZE "call" | |
363 | #endif | |
364 | ||
3dfda760 | 365 | /* SH2A does not support little-endian. Catch such combinations |
366 | taking into account the default configuration. */ | |
367 | #if TARGET_ENDIAN_DEFAULT == MASK_BIG_ENDIAN | |
368 | #define IS_LITTLE_ENDIAN_OPTION "%{ml:" | |
369 | #else | |
370 | #define IS_LITTLE_ENDIAN_OPTION "%{!mb:" | |
371 | #endif | |
372 | ||
373 | #if TARGET_CPU_DEFAULT & MASK_HARD_SH2A | |
374 | #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \ | |
375 | "%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:{!m5*:%eSH2a does not support little-endian}}}}}}" | |
376 | #else | |
377 | #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \ | |
378 | "%{m2a*:%eSH2a does not support little-endian}}" | |
379 | #endif | |
380 | ||
bcc58dc6 | 381 | #ifdef FDPIC_DEFAULT |
382 | #define FDPIC_SELF_SPECS "%{!mno-fdpic:-mfdpic}" | |
383 | #else | |
384 | #define FDPIC_SELF_SPECS | |
385 | #endif | |
386 | ||
e10782c9 | 387 | #undef DRIVER_SELF_SPECS |
bcc58dc6 | 388 | #define DRIVER_SELF_SPECS UNSUPPORTED_SH2A SUBTARGET_DRIVER_SELF_SPECS \ |
389 | FDPIC_SELF_SPECS | |
390 | ||
391 | #undef SUBTARGET_DRIVER_SELF_SPECS | |
392 | #define SUBTARGET_DRIVER_SELF_SPECS | |
9b8dc018 | 393 | |
1b61190c | 394 | #define ASSEMBLER_DIALECT assembler_dialect |
395 | ||
396 | extern int assembler_dialect; | |
397 | ||
59312820 | 398 | enum sh_divide_strategy_e { |
d6005df3 | 399 | /* SH5 strategies. */ |
59312820 | 400 | SH_DIV_CALL, |
401 | SH_DIV_CALL2, | |
d6005df3 | 402 | SH_DIV_FP, /* We could do this also for SH4. */ |
59312820 | 403 | SH_DIV_INV, |
404 | SH_DIV_INV_MINLAT, | |
405 | SH_DIV_INV20U, | |
406 | SH_DIV_INV20L, | |
407 | SH_DIV_INV_CALL, | |
408 | SH_DIV_INV_CALL2, | |
d6005df3 | 409 | SH_DIV_INV_FP, |
410 | /* SH1 .. SH4 strategies. Because of the small number of registers | |
9ca2c29a | 411 | available, the compiler uses knowledge of the actual set of registers |
412 | being clobbered by the different functions called. */ | |
d6005df3 | 413 | SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */ |
414 | SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */ | |
415 | SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */ | |
416 | SH_DIV_INTRINSIC | |
59312820 | 417 | }; |
418 | ||
419 | extern enum sh_divide_strategy_e sh_div_strategy; | |
420 | ||
421 | #ifndef SH_DIV_STRATEGY_DEFAULT | |
422 | #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL | |
423 | #endif | |
424 | ||
a9cfe83b | 425 | #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 |
426 | ||
7208c779 | 427 | \f |
9d1ff654 | 428 | /* Target machine storage layout. */ |
7208c779 | 429 | |
adb7af07 | 430 | #define TARGET_BIG_ENDIAN (!TARGET_LITTLE_ENDIAN) |
431 | ||
432 | #define SH_REG_MSW_OFFSET (TARGET_LITTLE_ENDIAN ? 1 : 0) | |
433 | #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) | |
434 | ||
7208c779 | 435 | /* Define this if most significant bit is lowest numbered |
436 | in instructions that operate on numbered bit-fields. */ | |
437 | #define BITS_BIG_ENDIAN 0 | |
438 | ||
439 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
adb7af07 | 440 | #define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN |
7208c779 | 441 | |
442 | /* Define this if most significant word of a multiword number is the lowest | |
443 | numbered. */ | |
adb7af07 | 444 | #define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN |
3dfc1807 | 445 | |
87e19636 | 446 | #define MAX_BITS_PER_WORD 64 |
447 | ||
87e19636 | 448 | /* Width in bits of an `int'. We want just 32-bits, even if words are |
ada8cf8b | 449 | longer. */ |
87e19636 | 450 | #define INT_TYPE_SIZE 32 |
451 | ||
452 | /* Width in bits of a `long'. */ | |
453 | #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32) | |
454 | ||
455 | /* Width in bits of a `long long'. */ | |
456 | #define LONG_LONG_TYPE_SIZE 64 | |
457 | ||
458 | /* Width in bits of a `long double'. */ | |
459 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
7208c779 | 460 | |
461 | /* Width of a word, in units (bytes). */ | |
87e19636 | 462 | #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4) |
463 | #define MIN_UNITS_PER_WORD 4 | |
7208c779 | 464 | |
41fafa66 | 465 | /* Scaling factor for Dwarf data offsets for CFI information. |
466 | The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for | |
467 | SHmedia; however, since we do partial register saves for the registers | |
468 | visible to SHcompact, and for target registers for SHMEDIA32, we have | |
469 | to allow saves that are only 4-byte aligned. */ | |
470 | #define DWARF_CIE_DATA_ALIGNMENT -4 | |
471 | ||
7208c779 | 472 | /* Width in bits of a pointer. |
473 | See also the macro `Pmode' defined below. */ | |
87e19636 | 474 | #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32) |
7208c779 | 475 | |
476 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
87e19636 | 477 | #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32) |
7208c779 | 478 | |
479 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
ba46e0eb | 480 | #define STACK_BOUNDARY BIGGEST_ALIGNMENT |
7208c779 | 481 | |
0dbd1c74 | 482 | /* The log (base 2) of the cache line size, in bytes. Processors prior to |
f0a494e6 | 483 | SH2 have no actual cache, but they fetch code in chunks of 4 bytes. |
484 | The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */ | |
2e752f00 | 485 | #define CACHE_LOG ((TARGET_HARD_SH4 || TARGET_SH5) ? 5 : TARGET_SH2 ? 4 : 2) |
0dbd1c74 | 486 | |
154b29aa | 487 | /* ABI given & required minimum allocation boundary (in *bits*) for the |
488 | code of a function. */ | |
489 | #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA) | |
87e19636 | 490 | |
491 | /* On SH5, the lowest bit is used to indicate SHmedia functions, so | |
492 | the vbit must go into the delta field of | |
493 | pointers-to-member-functions. */ | |
494 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION \ | |
495 | (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn) | |
7208c779 | 496 | |
497 | /* Alignment of field after `int : 0' in a structure. */ | |
498 | #define EMPTY_FIELD_BOUNDARY 32 | |
499 | ||
500 | /* No data type wants to be aligned rounder than this. */ | |
501 | #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) | |
502 | ||
503 | /* The best alignment to use in cases where we have a choice. */ | |
87e19636 | 504 | #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32) |
7208c779 | 505 | |
7208c779 | 506 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
9d1ff654 | 507 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
7208c779 | 508 | ((TREE_CODE (EXP) == STRING_CST \ |
509 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
97595bfd | 510 | ? FASTEST_ALIGNMENT : (ALIGN)) |
7208c779 | 511 | |
1fe27026 | 512 | /* get_mode_alignment assumes complex values are always held in multiple |
513 | registers, but that is not the case on the SH; CQImode and CHImode are | |
514 | held in a single integer register. SH5 also holds CSImode and SCmode | |
1fc184ee | 515 | values in integer registers. This is relevant for argument passing on |
82335f34 | 516 | SHcompact as we use a stack temp in order to pass CSImode by reference. */ |
1fe27026 | 517 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ |
518 | ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \ | |
519 | || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \ | |
41fafa66 | 520 | ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \ |
5be30882 | 521 | : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN)) |
1fe27026 | 522 | |
7208c779 | 523 | /* Make arrays of chars word-aligned for the same reasons. */ |
524 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
525 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
526 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
527 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
528 | ||
2e3d4844 | 529 | /* Number of bits which any structure or union's size must be a |
530 | multiple of. Each structure or union's size is rounded up to a | |
641e8334 | 531 | multiple of this. */ |
2717207c | 532 | #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8) |
2e3d4844 | 533 | |
7208c779 | 534 | /* Set this nonzero if move instructions will actually fail to work |
535 | when given unaligned data. */ | |
536 | #define STRICT_ALIGNMENT 1 | |
9eaab178 | 537 | |
538 | /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */ | |
539 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \ | |
540 | barrier_align (LABEL_AFTER_BARRIER) | |
541 | ||
164fbbdf | 542 | #define LOOP_ALIGN(A_LABEL) sh_loop_align (A_LABEL) |
9eaab178 | 543 | |
544 | #define LABEL_ALIGN(A_LABEL) \ | |
545 | ( \ | |
546 | (PREV_INSN (A_LABEL) \ | |
cbb16986 | 547 | && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \ |
9eaab178 | 548 | && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \ |
8f87ecd5 | 549 | && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \ |
9df03d69 | 550 | /* explicit alignment insn in constant tables. */ \ |
9eaab178 | 551 | ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \ |
552 | : 0) | |
553 | ||
554 | /* Jump tables must be 32 bit aligned, no matter the size of the element. */ | |
555 | #define ADDR_VEC_ALIGN(ADDR_VEC) 2 | |
556 | ||
557 | /* The base two logarithm of the known minimum alignment of an insn length. */ | |
558 | #define INSN_LENGTH_ALIGNMENT(A_INSN) \ | |
cbb16986 | 559 | (NONJUMP_INSN_P (A_INSN) \ |
87e19636 | 560 | ? 1 << TARGET_SHMEDIA \ |
cbb16986 | 561 | : JUMP_P (A_INSN) || CALL_P (A_INSN) \ |
87e19636 | 562 | ? 1 << TARGET_SHMEDIA \ |
9eaab178 | 563 | : CACHE_LOG) |
7208c779 | 564 | \f |
565 | /* Standard register usage. */ | |
566 | ||
7b23765d | 567 | /* Register allocation for the Renesas calling convention: |
7208c779 | 568 | |
6c049e03 | 569 | r0 arg return |
570 | r1..r3 scratch | |
9d1ff654 | 571 | r4..r7 args in |
97595bfd | 572 | r8..r13 call saved |
573 | r14 frame pointer/call saved | |
7208c779 | 574 | r15 stack pointer |
575 | ap arg pointer (doesn't really exist, always eliminated) | |
576 | pr subroutine return address | |
6c049e03 | 577 | t t bit |
641e8334 | 578 | mach multiply/accumulate result, high part |
07a356f1 | 579 | macl multiply/accumulate result, low part. |
580 | fpul fp/int communication register | |
1ae4c297 | 581 | rap return address pointer register |
07a356f1 | 582 | fr0 fp arg return |
583 | fr1..fr3 scratch floating point registers | |
584 | fr4..fr11 fp args in | |
585 | fr12..fr15 call saved floating point registers */ | |
7208c779 | 586 | |
b0fa59a9 | 587 | #define MAX_REGISTER_NAME_LENGTH 6 |
87e19636 | 588 | extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1]; |
589 | ||
590 | #define SH_REGISTER_NAMES_INITIALIZER \ | |
6c049e03 | 591 | { \ |
87e19636 | 592 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ |
593 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
594 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ | |
595 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ | |
596 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ | |
597 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \ | |
598 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ | |
599 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \ | |
600 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \ | |
601 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \ | |
602 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \ | |
603 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \ | |
604 | "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \ | |
605 | "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \ | |
606 | "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \ | |
607 | "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \ | |
608 | "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \ | |
609 | "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \ | |
610 | "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \ | |
b0fa59a9 | 611 | "rap", "sfp", "fpscr0", "fpscr1" \ |
87e19636 | 612 | } |
613 | ||
87e19636 | 614 | #define REGNAMES_ARR_INDEX_1(index) \ |
615 | (sh_register_names[index]) | |
616 | #define REGNAMES_ARR_INDEX_2(index) \ | |
617 | REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1) | |
618 | #define REGNAMES_ARR_INDEX_4(index) \ | |
619 | REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2) | |
620 | #define REGNAMES_ARR_INDEX_8(index) \ | |
621 | REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4) | |
622 | #define REGNAMES_ARR_INDEX_16(index) \ | |
623 | REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8) | |
624 | #define REGNAMES_ARR_INDEX_32(index) \ | |
625 | REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16) | |
626 | #define REGNAMES_ARR_INDEX_64(index) \ | |
627 | REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32) | |
628 | ||
629 | #define REGISTER_NAMES \ | |
630 | { \ | |
631 | REGNAMES_ARR_INDEX_64 (0), \ | |
632 | REGNAMES_ARR_INDEX_64 (64), \ | |
633 | REGNAMES_ARR_INDEX_8 (128), \ | |
634 | REGNAMES_ARR_INDEX_8 (136), \ | |
635 | REGNAMES_ARR_INDEX_8 (144), \ | |
b0fa59a9 | 636 | REGNAMES_ARR_INDEX_4 (152) \ |
87e19636 | 637 | } |
638 | ||
639 | #define ADDREGNAMES_SIZE 32 | |
640 | #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4 | |
641 | extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ | |
642 | [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]; | |
643 | ||
644 | #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \ | |
645 | { \ | |
646 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \ | |
647 | "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \ | |
648 | "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \ | |
649 | "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \ | |
650 | } | |
651 | ||
652 | #define ADDREGNAMES_REGNO(index) \ | |
653 | ((index < 32) ? (FIRST_FP_REG + (index) * 2) \ | |
654 | : (-1)) | |
655 | ||
656 | #define ADDREGNAMES_ARR_INDEX_1(index) \ | |
657 | { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) } | |
658 | #define ADDREGNAMES_ARR_INDEX_2(index) \ | |
659 | ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1) | |
660 | #define ADDREGNAMES_ARR_INDEX_4(index) \ | |
661 | ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2) | |
662 | #define ADDREGNAMES_ARR_INDEX_8(index) \ | |
663 | ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4) | |
664 | #define ADDREGNAMES_ARR_INDEX_16(index) \ | |
665 | ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8) | |
666 | #define ADDREGNAMES_ARR_INDEX_32(index) \ | |
667 | ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16) | |
668 | ||
669 | #define ADDITIONAL_REGISTER_NAMES \ | |
670 | { \ | |
671 | ADDREGNAMES_ARR_INDEX_32 (0) \ | |
672 | } | |
673 | ||
7208c779 | 674 | /* Number of actual hardware registers. |
675 | The hardware registers are assigned numbers for the compiler | |
676 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
677 | All registers that the compiler knows about must be given numbers, | |
641e8334 | 678 | even those that are not normally considered general registers. */ |
7208c779 | 679 | |
a5bd34f1 | 680 | /* There are many other relevant definitions in sh.md's md_constants. */ |
681 | ||
682 | #define FIRST_GENERAL_REG R0_REG | |
87e19636 | 683 | #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15)) |
a5bd34f1 | 684 | #define FIRST_FP_REG DR0_REG |
87e19636 | 685 | #define LAST_FP_REG (FIRST_FP_REG + \ |
87ed74ef | 686 | (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1)) |
a5bd34f1 | 687 | #define FIRST_XD_REG XD0_REG |
87e19636 | 688 | #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1)) |
689 | #define FIRST_TARGET_REG TR0_REG | |
690 | #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1)) | |
a5bd34f1 | 691 | |
2f8b8488 | 692 | /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */ |
2f8b8488 | 693 | #define FIRST_BANKED_REG R0_REG |
694 | #define LAST_BANKED_REG R7_REG | |
695 | ||
6c049e03 | 696 | #define BANKED_REGISTER_P(REGNO) \ |
697 | IN_RANGE ((REGNO), \ | |
2f8b8488 | 698 | (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \ |
699 | (unsigned HOST_WIDE_INT) LAST_BANKED_REG) | |
700 | ||
e2142b04 | 701 | #define GENERAL_REGISTER_P(REGNO) \ |
41fafa66 | 702 | IN_RANGE ((REGNO), \ |
703 | (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ | |
704 | (unsigned HOST_WIDE_INT) LAST_GENERAL_REG) | |
e2142b04 | 705 | |
706 | #define GENERAL_OR_AP_REGISTER_P(REGNO) \ | |
6c049e03 | 707 | (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \ |
b9a602c6 | 708 | || ((REGNO) == FRAME_POINTER_REGNUM)) |
e2142b04 | 709 | |
710 | #define FP_REGISTER_P(REGNO) \ | |
41fafa66 | 711 | ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG) |
e2142b04 | 712 | |
713 | #define XD_REGISTER_P(REGNO) \ | |
41fafa66 | 714 | ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG) |
e2142b04 | 715 | |
716 | #define FP_OR_XD_REGISTER_P(REGNO) \ | |
717 | (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO)) | |
718 | ||
719 | #define FP_ANY_REGISTER_P(REGNO) \ | |
720 | (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG) | |
721 | ||
722 | #define SPECIAL_REGISTER_P(REGNO) \ | |
a5bd34f1 | 723 | ((REGNO) == GBR_REG || (REGNO) == T_REG \ |
b0fa59a9 | 724 | || (REGNO) == MACH_REG || (REGNO) == MACL_REG \ |
725 | || (REGNO) == FPSCR_MODES_REG || (REGNO) == FPSCR_STAT_REG) | |
7208c779 | 726 | |
87e19636 | 727 | #define TARGET_REGISTER_P(REGNO) \ |
41fafa66 | 728 | ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG) |
87e19636 | 729 | |
730 | #define SHMEDIA_REGISTER_P(REGNO) \ | |
731 | (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \ | |
732 | || TARGET_REGISTER_P (REGNO)) | |
733 | ||
b2d7ede1 | 734 | /* This is to be used in TARGET_CONDITIONAL_REGISTER_USAGE, to mark |
735 | registers that should be fixed. */ | |
87e19636 | 736 | #define VALID_REGISTER_P(REGNO) \ |
737 | (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \ | |
738 | || (REGNO) == AP_REG || (REGNO) == RAP_REG \ | |
b9a602c6 | 739 | || (REGNO) == FRAME_POINTER_REGNUM \ |
87e19636 | 740 | || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \ |
87ed74ef | 741 | || (TARGET_SH2E && (REGNO) == FPUL_REG)) |
87e19636 | 742 | |
743 | /* The mode that should be generally used to store a register by | |
744 | itself in the stack, or to load it back. */ | |
745 | #define REGISTER_NATURAL_MODE(REGNO) \ | |
746 | (FP_REGISTER_P (REGNO) ? SFmode \ | |
747 | : XD_REGISTER_P (REGNO) ? DFmode \ | |
fcd4cb57 | 748 | : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \ |
749 | ? DImode \ | |
750 | : SImode) | |
87e19636 | 751 | |
b0fa59a9 | 752 | #define FIRST_PSEUDO_REGISTER 156 |
b9a602c6 | 753 | |
754 | /* Don't count soft frame pointer. */ | |
b0fa59a9 | 755 | #define DWARF_FRAME_REGISTERS (153) |
7208c779 | 756 | |
757 | /* 1 for registers that have pervasive standard uses | |
641e8334 | 758 | and are not available for the register allocator. |
f3d93547 | 759 | |
13d406a0 | 760 | Mach register is fixed 'cause it's only 10 bits wide for SH1. |
761 | It is 32 bits wide for SH2. */ | |
6c049e03 | 762 | #define FIXED_REGISTERS \ |
763 | { \ | |
87e19636 | 764 | /* Regular registers. */ \ |
765 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
766 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
767 | /* r16 is reserved, r18 is the former pr. */ \ | |
768 | 1, 0, 0, 0, 0, 0, 0, 0, \ | |
769 | /* r24 is reserved for the OS; r25, for the assembler or linker. */ \ | |
770 | /* r26 is a global variable data pointer; r27 is for constants. */ \ | |
771 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
772 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
773 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
774 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
775 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
776 | /* FP registers. */ \ | |
777 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
778 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
779 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
780 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
781 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
782 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
783 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
784 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
785 | /* Branch target registers. */ \ | |
786 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
787 | /* XD registers. */ \ | |
788 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
789 | /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ | |
790 | 1, 1, 1, 1, 1, 1, 0, 1, \ | |
b0fa59a9 | 791 | /*"rap", "sfp","fpscr0","fpscr1" */ \ |
792 | 1, 1, 1, 1, \ | |
07a356f1 | 793 | } |
7208c779 | 794 | |
795 | /* 1 for registers not available across function calls. | |
796 | These must include the FIXED_REGISTERS and also any | |
797 | registers that can be used without being saved. | |
798 | The latter must include the registers where values are returned | |
799 | and the register where structure-value addresses are passed. | |
800 | Aside from that, you can include as many other registers as you like. */ | |
6c049e03 | 801 | #define CALL_USED_REGISTERS \ |
802 | { \ | |
87e19636 | 803 | /* Regular registers. */ \ |
804 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
805 | /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \ | |
806 | Only the lower 32bits of R10-R14 are guaranteed to be preserved \ | |
807 | across SH5 function calls. */ \ | |
808 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
93ea47c4 | 809 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
87e19636 | 810 | 1, 1, 1, 1, 0, 0, 0, 0, \ |
811 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
812 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
813 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
814 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
815 | /* FP registers. */ \ | |
816 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
817 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
818 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
819 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
820 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
821 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
822 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
823 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
824 | /* Branch target registers. */ \ | |
825 | 1, 1, 1, 1, 1, 0, 0, 0, \ | |
826 | /* XD registers. */ \ | |
827 | 1, 1, 1, 1, 1, 1, 0, 0, \ | |
828 | /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ | |
93ea47c4 | 829 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
b0fa59a9 | 830 | /*"rap", "sfp","fpscr0","fpscr1" */ \ |
831 | 1, 1, 1, 1, \ | |
07a356f1 | 832 | } |
7208c779 | 833 | |
92f082e0 | 834 | /* CALL_REALLY_USED_REGISTERS is used as a default setting, which is then |
835 | overridden by -fcall-saved-* and -fcall-used-* options and then by | |
836 | TARGET_CONDITIONAL_REGISTER_USAGE. There we might want to make a | |
837 | register call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */ | |
838 | #define CALL_REALLY_USED_REGISTERS \ | |
839 | { \ | |
840 | /* Regular registers. */ \ | |
841 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
842 | /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \ | |
843 | Only the lower 32bits of R10-R14 are guaranteed to be preserved \ | |
844 | across SH5 function calls. */ \ | |
845 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
846 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
847 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
848 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
849 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
850 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
851 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
852 | /* FP registers. */ \ | |
853 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
854 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
855 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
856 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
857 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
858 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
859 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
860 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
861 | /* Branch target registers. */ \ | |
862 | 1, 1, 1, 1, 1, 0, 0, 0, \ | |
863 | /* XD registers. */ \ | |
864 | 1, 1, 1, 1, 1, 1, 0, 0, \ | |
865 | /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ | |
866 | 0, 1, 1, 1, 1, 1, 1, 1, \ | |
867 | /*"rap", "sfp","fpscr0","fpscr1" */ \ | |
868 | 1, 1, 0, 0, \ | |
869 | } | |
956dd562 | 870 | |
87e19636 | 871 | /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved |
872 | across SHcompact function calls. We can't tell whether a called | |
873 | function is SHmedia or SHcompact, so we assume it may be when | |
874 | compiling SHmedia code with the 32-bit ABI, since that's the only | |
875 | ABI that can be linked with SHcompact code. */ | |
876 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \ | |
877 | (TARGET_SHMEDIA32 \ | |
878 | && GET_MODE_SIZE (MODE) > 4 \ | |
fcd4cb57 | 879 | && (((REGNO) >= FIRST_GENERAL_REG + 10 \ |
6c049e03 | 880 | && (REGNO) <= FIRST_GENERAL_REG + 15) \ |
41fafa66 | 881 | || TARGET_REGISTER_P (REGNO) \ |
fcd4cb57 | 882 | || (REGNO) == PR_MEDIA_REG)) |
87e19636 | 883 | |
7208c779 | 884 | /* Return number of consecutive hard regs needed starting at reg REGNO |
885 | to hold something of mode MODE. | |
886 | This is ordinarily the length in words of a value of mode MODE | |
887 | but can be less for certain modes in special long registers. | |
888 | ||
1b61190c | 889 | On the SH all but the XD regs are UNITS_PER_WORD bits wide. */ |
9d1ff654 | 890 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
e2142b04 | 891 | (XD_REGISTER_P (REGNO) \ |
7da7e24b | 892 | ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \ |
87e19636 | 893 | : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \ |
894 | ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \ | |
7da7e24b | 895 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) |
7208c779 | 896 | |
32e68083 | 897 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ |
6c049e03 | 898 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
32e68083 | 899 | sh_hard_regno_mode_ok ((REGNO), (MODE)) |
7208c779 | 900 | |
901 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
902 | when one has mode MODE1 and one has mode MODE2. | |
903 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
6109c3ff | 904 | for any hard reg, then this must be 0 for correct output. |
905 | That's the case for xd registers: we don't hold SFmode values in | |
906 | them, so we can't tie an SFmode pseudos with one in another | |
907 | floating-point mode. */ | |
7208c779 | 908 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
6109c3ff | 909 | ((MODE1) == (MODE2) \ |
59312820 | 910 | || (TARGET_SHMEDIA \ |
911 | && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \ | |
912 | && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \ | |
6109c3ff | 913 | || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ |
87e19636 | 914 | && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \ |
915 | && (GET_MODE_SIZE (MODE2) <= 4)) \ | |
916 | : ((MODE1) != SFmode && (MODE2) != SFmode)))) | |
7208c779 | 917 | |
ea68d4ba | 918 | /* Specify the modes required to caller save a given hard regno. */ |
919 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
920 | sh_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) | |
921 | ||
c67138a9 | 922 | /* A C expression that is nonzero if hard register NEW_REG can be |
923 | considered for use as a rename register for OLD_REG register */ | |
c67138a9 | 924 | #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ |
925 | sh_hard_regno_rename_ok (OLD_REG, NEW_REG) | |
926 | ||
7208c779 | 927 | /* Specify the registers used for certain standard purposes. |
928 | The values of these macros are register numbers. */ | |
929 | ||
930 | /* Define this if the program counter is overloaded on a register. */ | |
931 | /* #define PC_REGNUM 15*/ | |
932 | ||
933 | /* Register to use for pushing function arguments. */ | |
a5bd34f1 | 934 | #define STACK_POINTER_REGNUM SP_REG |
7208c779 | 935 | |
936 | /* Base register for access to local variables of the function. */ | |
b9a602c6 | 937 | #define HARD_FRAME_POINTER_REGNUM FP_REG |
938 | ||
939 | /* Base register for access to local variables of the function. */ | |
940 | #define FRAME_POINTER_REGNUM 153 | |
7208c779 | 941 | |
1ae4c297 | 942 | /* Fake register that holds the address on the stack of the |
943 | current function's return address. */ | |
a5bd34f1 | 944 | #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG |
1ae4c297 | 945 | |
0abf894c | 946 | /* Register to hold the addressing base for position independent |
947 | code access to data items. */ | |
575fdeec | 948 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM) |
0abf894c | 949 | |
bcc58dc6 | 950 | /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT |
951 | entries would need to handle saving and restoring it). */ | |
952 | #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC | |
953 | ||
0abf894c | 954 | #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_" |
955 | ||
7208c779 | 956 | /* Definitions for register eliminations. |
957 | ||
55a1ab6f | 958 | We have three registers that can be eliminated on the SH. First, the |
7208c779 | 959 | frame pointer register can often be eliminated in favor of the stack |
960 | pointer register. Secondly, the argument pointer register can always be | |
55a1ab6f | 961 | eliminated; it is replaced with either the stack or frame pointer. |
ad87de1e | 962 | Third, there is the return address pointer, which can also be replaced |
6c049e03 | 963 | with either the stack or the frame pointer. |
7208c779 | 964 | |
6c049e03 | 965 | This is an array of structures. Each structure initializes one pair |
7208c779 | 966 | of eliminable registers. The "from" register number is given first, |
967 | followed by "to". Eliminations of the same "from" register are listed | |
6c049e03 | 968 | in order of preference. |
7208c779 | 969 | |
6c049e03 | 970 | If you add any registers here that are not actually hard registers, |
55a1ab6f | 971 | and that have any alternative of elimination that doesn't always |
972 | apply, you need to amend calc_live_regs to exclude it, because | |
973 | reload spills all eliminable registers where it sees an | |
974 | can_eliminate == 0 entry, thus making them 'live' . | |
975 | If you add any hard registers that can be eliminated in different | |
976 | ways, you have to patch reload to spill them only when all alternatives | |
977 | of elimination fail. */ | |
1ae4c297 | 978 | #define ELIMINABLE_REGS \ |
b9a602c6 | 979 | {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
980 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
981 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1ae4c297 | 982 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
b9a602c6 | 983 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ |
1ae4c297 | 984 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
b9a602c6 | 985 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},} |
7208c779 | 986 | |
7208c779 | 987 | /* Define the offset between two registers, one to be eliminated, and the other |
988 | its replacement, at the start of a routine. */ | |
7208c779 | 989 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
0dbd1c74 | 990 | OFFSET = initial_elimination_offset ((FROM), (TO)) |
7208c779 | 991 | |
992 | /* Base register for access to arguments of the function. */ | |
bd579652 | 993 | #define ARG_POINTER_REGNUM AP_REG |
7208c779 | 994 | |
995 | /* Register in which the static-chain is passed to a function. */ | |
87e19636 | 996 | #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3) |
7208c779 | 997 | |
97595bfd | 998 | /* Don't default to pcc-struct-return, because we have already specified |
6644435d | 999 | exactly how to return structures in the TARGET_RETURN_IN_MEMORY |
1000 | target hook. */ | |
97595bfd | 1001 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
87e19636 | 1002 | |
1003 | #define SHMEDIA_REGS_STACK_ADJUST() \ | |
18d50ae6 | 1004 | (TARGET_SHCOMPACT && crtl->saves_all_registers \ |
87e19636 | 1005 | ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \ |
1006 | + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \ | |
1007 | : 0) | |
1008 | ||
7208c779 | 1009 | \f |
1010 | /* Define the classes of registers for register constraints in the | |
1011 | machine description. Also define ranges of constants. | |
1012 | ||
1013 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1014 | If there is more than one class, another class must be named NO_REGS | |
1015 | and contain no registers. | |
1016 | ||
1017 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1018 | another name such as ALL_REGS). This is the class of registers | |
1019 | that is allowed by "g" or "r" in a register constraint. | |
1020 | Also, registers outside this class are allocated only when | |
1021 | instructions express preferences for them. | |
1022 | ||
1023 | The classes must be numbered in nondecreasing order; that is, | |
1024 | a larger-numbered class must never be contained completely | |
1025 | in a smaller-numbered class. | |
1026 | ||
1027 | For any two classes, it is very desirable that there be another | |
6c049e03 | 1028 | class that represents their union. |
7208c779 | 1029 | |
6c049e03 | 1030 | The SH has two sorts of general registers, R0 and the rest. R0 can |
7208c779 | 1031 | be used as the destination of some of the arithmetic ops. There are |
1032 | also some special purpose registers; the T bit register, the | |
6c049e03 | 1033 | Procedure Return Register and the Multiply Accumulate Registers. |
1034 | ||
1035 | Place GENERAL_REGS after FPUL_REGS so that it will be preferred by | |
0dbd1c74 | 1036 | reg_class_subunion. We don't want to have an actual union class |
1037 | of these, because it would only be used when both classes are calculated | |
1038 | to give the same cost, but there is only one FPUL register. | |
1039 | Besides, regclass fails to notice the different REGISTER_MOVE_COSTS | |
1040 | applying to the actual instruction alternative considered. E.g., the | |
1041 | y/r alternative of movsi_ie is considered to have no more cost that | |
1042 | the r/r alternative, which is patently untrue. */ | |
7208c779 | 1043 | enum reg_class |
1044 | { | |
1045 | NO_REGS, | |
1046 | R0_REGS, | |
7208c779 | 1047 | PR_REGS, |
1048 | T_REGS, | |
1049 | MAC_REGS, | |
07a356f1 | 1050 | FPUL_REGS, |
5acd0683 | 1051 | SIBCALL_REGS, |
2a0b1a37 | 1052 | NON_SP_REGS, |
0dbd1c74 | 1053 | GENERAL_REGS, |
07a356f1 | 1054 | FP0_REGS, |
1055 | FP_REGS, | |
1b61190c | 1056 | DF_REGS, |
1057 | FPSCR_REGS, | |
301209b2 | 1058 | GENERAL_FP_REGS, |
c3c6d729 | 1059 | GENERAL_DF_REGS, |
87e19636 | 1060 | TARGET_REGS, |
7208c779 | 1061 | ALL_REGS, |
1062 | LIM_REG_CLASSES | |
1063 | }; | |
1064 | ||
1065 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1066 | ||
641e8334 | 1067 | /* Give names of register classes as strings for dump file. */ |
9d1ff654 | 1068 | #define REG_CLASS_NAMES \ |
7208c779 | 1069 | { \ |
1070 | "NO_REGS", \ | |
1071 | "R0_REGS", \ | |
7208c779 | 1072 | "PR_REGS", \ |
1073 | "T_REGS", \ | |
1074 | "MAC_REGS", \ | |
07a356f1 | 1075 | "FPUL_REGS", \ |
5acd0683 | 1076 | "SIBCALL_REGS", \ |
2a0b1a37 | 1077 | "NON_SP_REGS", \ |
0dbd1c74 | 1078 | "GENERAL_REGS", \ |
07a356f1 | 1079 | "FP0_REGS", \ |
1080 | "FP_REGS", \ | |
1b61190c | 1081 | "DF_REGS", \ |
1082 | "FPSCR_REGS", \ | |
301209b2 | 1083 | "GENERAL_FP_REGS", \ |
c3c6d729 | 1084 | "GENERAL_DF_REGS", \ |
87e19636 | 1085 | "TARGET_REGS", \ |
7208c779 | 1086 | "ALL_REGS", \ |
1087 | } | |
1088 | ||
1089 | /* Define which registers fit in which classes. | |
1090 | This is an initializer for a vector of HARD_REG_SET | |
1091 | of length N_REG_CLASSES. */ | |
87e19636 | 1092 | #define REG_CLASS_CONTENTS \ |
1093 | { \ | |
1094 | /* NO_REGS: */ \ | |
1095 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ | |
1096 | /* R0_REGS: */ \ | |
1097 | { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ | |
1098 | /* PR_REGS: */ \ | |
1099 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \ | |
1100 | /* T_REGS: */ \ | |
1101 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \ | |
1102 | /* MAC_REGS: */ \ | |
1103 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \ | |
1104 | /* FPUL_REGS: */ \ | |
cb44aa06 | 1105 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \ |
b2d7ede1 | 1106 | /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \ |
87e19636 | 1107 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ |
2a0b1a37 | 1108 | /* NON_SP_REGS: */ \ |
1109 | { 0xffff7fff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ | |
87e19636 | 1110 | /* GENERAL_REGS: */ \ |
b9a602c6 | 1111 | { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ |
87e19636 | 1112 | /* FP0_REGS: */ \ |
1113 | { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \ | |
1114 | /* FP_REGS: */ \ | |
1115 | { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ | |
1116 | /* DF_REGS: */ \ | |
1117 | { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ | |
1118 | /* FPSCR_REGS: */ \ | |
1119 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \ | |
1120 | /* GENERAL_FP_REGS: */ \ | |
c3c6d729 | 1121 | { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \ |
1122 | /* GENERAL_DF_REGS: */ \ | |
1123 | { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \ | |
87e19636 | 1124 | /* TARGET_REGS: */ \ |
1125 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \ | |
1126 | /* ALL_REGS: */ \ | |
b0fa59a9 | 1127 | { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0fffffff }, \ |
894b8fd9 | 1128 | } |
7208c779 | 1129 | |
1130 | /* The same information, inverted: | |
1131 | Return the class number of the smallest class containing | |
1132 | reg number REGNO. This could be a conditional expression | |
1133 | or could index an array. */ | |
41fafa66 | 1134 | extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; |
0dbd1c74 | 1135 | #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)] |
7208c779 | 1136 | |
ed5527ca | 1137 | /* When this hook returns true for MODE, the compiler allows |
1138 | registers explicitly used in the rtl to be used as spill registers | |
1139 | but prevents the compiler from extending the lifetime of these | |
1140 | registers. */ | |
1141 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ | |
1142 | sh_small_register_classes_for_mode_p | |
97595bfd | 1143 | |
7208c779 | 1144 | /* The order in which register should be allocated. */ |
0dbd1c74 | 1145 | /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo, |
1146 | and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be | |
1147 | spilled or used otherwise, we better have the FP_REGS allocated first. */ | |
9d1ff654 | 1148 | #define REG_ALLOC_ORDER \ |
1fe27026 | 1149 | {/* Caller-saved FPRs */ \ |
1150 | 65, 66, 67, 68, 69, 70, 71, 64, \ | |
1151 | 72, 73, 74, 75, 80, 81, 82, 83, \ | |
1152 | 84, 85, 86, 87, 88, 89, 90, 91, \ | |
1153 | 92, 93, 94, 95, 96, 97, 98, 99, \ | |
1154 | /* Callee-saved FPRs */ \ | |
1155 | 76, 77, 78, 79,100,101,102,103, \ | |
87e19636 | 1156 | 104,105,106,107,108,109,110,111, \ |
1157 | 112,113,114,115,116,117,118,119, \ | |
1158 | 120,121,122,123,124,125,126,127, \ | |
1fe27026 | 1159 | 136,137,138,139,140,141,142,143, \ |
1160 | /* FPSCR */ 151, \ | |
1161 | /* Caller-saved GPRs (except 8/9 on SH1-4) */ \ | |
1162 | 1, 2, 3, 7, 6, 5, 4, 0, \ | |
1163 | 8, 9, 17, 19, 20, 21, 22, 23, \ | |
1164 | 36, 37, 38, 39, 40, 41, 42, 43, \ | |
1165 | 60, 61, 62, \ | |
1166 | /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \ | |
1167 | 10, 11, 12, 13, 14, 18, \ | |
1168 | /* SH5 callee-saved GPRs */ \ | |
1169 | 28, 29, 30, 31, 32, 33, 34, 35, \ | |
1170 | 44, 45, 46, 47, 48, 49, 50, 51, \ | |
1171 | 52, 53, 54, 55, 56, 57, 58, 59, \ | |
1172 | /* FPUL */ 150, \ | |
1173 | /* SH5 branch target registers */ \ | |
87e19636 | 1174 | 128,129,130,131,132,133,134,135, \ |
1fe27026 | 1175 | /* Fixed registers */ \ |
1176 | 15, 16, 24, 25, 26, 27, 63,144, \ | |
b0fa59a9 | 1177 | 145,146,147,148,149,152,153,154,155 } |
7208c779 | 1178 | |
1179 | /* The class value for index registers, and the one for base regs. */ | |
59312820 | 1180 | #define INDEX_REG_CLASS \ |
1181 | (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS) | |
7208c779 | 1182 | #define BASE_REG_CLASS GENERAL_REGS |
9d1ff654 | 1183 | \f |
abff7a2e | 1184 | /* Defines for sh.md and constraints.md. */ |
7208c779 | 1185 | |
af2c1324 | 1186 | #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \ |
1187 | && ((HOST_WIDE_INT)(VALUE)) <= 127) | |
af2c1324 | 1188 | #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \ |
1189 | && ((HOST_WIDE_INT)(VALUE)) <= 32767) | |
af2c1324 | 1190 | |
1191 | #define CONST_OK_FOR_J16(VALUE) \ | |
34809a77 | 1192 | ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \ |
69535619 | 1193 | || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) (HOST_WIDE_INT_M1U << 32))) |
af2c1324 | 1194 | |
1195 | #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \ | |
1196 | && ((HOST_WIDE_INT)(VALUE)) <= 255) | |
07a356f1 | 1197 | |
74cf552d | 1198 | #define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\ |
1199 | (((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX)) | |
1200 | ||
7208c779 | 1201 | /* Return the maximum number of consecutive registers |
641e8334 | 1202 | needed to represent mode MODE in a register of class CLASS. |
7208c779 | 1203 | |
c87f89be | 1204 | If TARGET_SHMEDIA, we need two FP registers per word. |
1205 | Otherwise we will need at most one register per word. */ | |
9d1ff654 | 1206 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
c87f89be | 1207 | (TARGET_SHMEDIA \ |
1208 | && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \ | |
1209 | ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \ | |
1210 | : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
1b61190c | 1211 | |
1212 | /* If defined, gives a class of registers that cannot be used as the | |
6c049e03 | 1213 | operand of a SUBREG that changes the mode of the object illegally. |
1214 | ??? We need to renumber the internal numbers for the frnn registers | |
d3b29bbd | 1215 | when in little endian in order to allow mode size changes. */ |
6c049e03 | 1216 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
22aae821 | 1217 | sh_cannot_change_mode_class (FROM, TO, CLASS) |
7208c779 | 1218 | \f |
1219 | /* Stack layout; function entry, exit and calling. */ | |
1220 | ||
9d1ff654 | 1221 | /* Define the number of registers that can hold parameters. |
07a356f1 | 1222 | These macros are used only in other macro definitions below. */ |
07a356f1 | 1223 | #define NPARM_REGS(MODE) \ |
87e19636 | 1224 | (TARGET_FPU_ANY && (MODE) == SFmode \ |
1225 | ? (TARGET_SH5 ? 12 : 8) \ | |
6c049e03 | 1226 | : (TARGET_SH4 || TARGET_SH2A_DOUBLE) \ |
1227 | && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1228 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ | |
87e19636 | 1229 | ? (TARGET_SH5 ? 12 : 8) \ |
1230 | : (TARGET_SH5 ? 8 : 4)) | |
07a356f1 | 1231 | |
87e19636 | 1232 | #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4)) |
1233 | #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0)) | |
7208c779 | 1234 | |
87e19636 | 1235 | #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4)) |
07a356f1 | 1236 | #define FIRST_FP_RET_REG FIRST_FP_REG |
1237 | ||
7208c779 | 1238 | /* Define this if pushing a word on the stack |
1239 | makes the stack pointer a smaller address. */ | |
2b785411 | 1240 | #define STACK_GROWS_DOWNWARD 1 |
7208c779 | 1241 | |
3ce7ff97 | 1242 | /* Define this macro to nonzero if the addresses of local variable slots |
b9a602c6 | 1243 | are at negative offsets from the frame pointer. */ |
1244 | #define FRAME_GROWS_DOWNWARD 1 | |
97595bfd | 1245 | |
1246 | /* Offset from the frame pointer to the first local variable slot to | |
641e8334 | 1247 | be allocated. */ |
7208c779 | 1248 | #define STARTING_FRAME_OFFSET 0 |
1249 | ||
1250 | /* If we generate an insn to push BYTES bytes, | |
1251 | this says how many the stack pointer really advances by. */ | |
0dbd1c74 | 1252 | /* Don't define PUSH_ROUNDING, since the hardware doesn't do this. |
1253 | When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to | |
1254 | do correct alignment. */ | |
1255 | #if 0 | |
7208c779 | 1256 | #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) |
0dbd1c74 | 1257 | #endif |
7208c779 | 1258 | |
1259 | /* Offset of first parameter from the argument pointer register value. */ | |
1260 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1261 | ||
87e19636 | 1262 | /* Value is the number of bytes of arguments automatically popped when |
1263 | calling a subroutine. | |
1264 | CUM is the accumulated argument list. | |
1265 | ||
1266 | On SHcompact, the call trampoline pops arguments off the stack. */ | |
1267 | #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0) | |
1268 | ||
9df03d69 | 1269 | /* Some subroutine macros specific to this machine. */ |
07a356f1 | 1270 | |
1271 | #define BASE_RETURN_VALUE_REG(MODE) \ | |
6c049e03 | 1272 | ((TARGET_FPU_ANY && ((MODE) == SFmode)) \ |
07a356f1 | 1273 | ? FIRST_FP_RET_REG \ |
6c049e03 | 1274 | : TARGET_FPU_ANY && (MODE) == SCmode \ |
1b61190c | 1275 | ? FIRST_FP_RET_REG \ |
87e19636 | 1276 | : (TARGET_FPU_DOUBLE \ |
1b61190c | 1277 | && ((MODE) == DFmode || (MODE) == SFmode \ |
1278 | || (MODE) == DCmode || (MODE) == SCmode )) \ | |
1279 | ? FIRST_FP_RET_REG \ | |
07a356f1 | 1280 | : FIRST_RET_REG) |
1281 | ||
1282 | #define BASE_ARG_REG(MODE) \ | |
87ed74ef | 1283 | ((TARGET_SH2E && ((MODE) == SFmode)) \ |
07a356f1 | 1284 | ? FIRST_FP_PARM_REG \ |
7105fb72 | 1285 | : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
1b61190c | 1286 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\ |
1287 | ? FIRST_FP_PARM_REG \ | |
07a356f1 | 1288 | : FIRST_PARM_REG) |
1289 | ||
641e8334 | 1290 | /* 1 if N is a possible register number for function argument passing. */ |
41fafa66 | 1291 | /* ??? There are some callers that pass REGNO as int, and others that pass |
1292 | it as unsigned. We get warnings unless we do casts everywhere. */ | |
9d1ff654 | 1293 | #define FUNCTION_ARG_REGNO_P(REGNO) \ |
41fafa66 | 1294 | (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \ |
1295 | && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\ | |
6c049e03 | 1296 | || (TARGET_FPU_ANY \ |
41fafa66 | 1297 | && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \ |
1298 | && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \ | |
1299 | + NPARM_REGS (SFmode)))) | |
7208c779 | 1300 | \f |
1301 | /* Define a data type for recording info about an argument list | |
1302 | during the scan of that argument list. This data type should | |
1303 | hold all necessary information about the function itself | |
1304 | and about the args processed so far, enough to enable macros | |
1305 | such as FUNCTION_ARG to determine where the next arg should go. | |
1306 | ||
1307 | On SH, this is a single integer, which is a number of words | |
1308 | of arguments scanned so far (including the invisible argument, | |
1309 | if any, which holds the structure-value-address). | |
1310 | Thus NARGREGS or more means all following args should go on the stack. */ | |
07a356f1 | 1311 | enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 }; |
1312 | struct sh_args { | |
1313 | int arg_count[2]; | |
5be96103 | 1314 | int force_mem; |
808a491c | 1315 | /* Nonzero if a prototype is available for the function. */ |
87e19636 | 1316 | int prototype_p; |
1317 | /* The number of an odd floating-point register, that should be used | |
1318 | for the next argument of type float. */ | |
1319 | int free_single_fp_reg; | |
1320 | /* Whether we're processing an outgoing function call. */ | |
1321 | int outgoing; | |
1322 | /* The number of general-purpose registers that should have been | |
1323 | used to pass partial arguments, that are passed totally on the | |
1324 | stack. On SHcompact, a call trampoline will pop them off the | |
1325 | stack before calling the actual function, and, if the called | |
1326 | function is implemented in SHcompact mode, the incoming arguments | |
1327 | decoder will push such arguments back onto the stack. For | |
1328 | incoming arguments, STACK_REGS also takes into account other | |
1329 | arguments passed by reference, that the decoder will also push | |
1330 | onto the stack. */ | |
1331 | int stack_regs; | |
1332 | /* The number of general-purpose registers that should have been | |
1333 | used to pass arguments, if the arguments didn't have to be passed | |
1334 | by reference. */ | |
1335 | int byref_regs; | |
b981d932 | 1336 | /* Set as by shcompact_byref if the current argument is to be passed |
1337 | by reference. */ | |
87e19636 | 1338 | int byref; |
1339 | ||
1340 | /* call_cookie is a bitmask used by call expanders, as well as | |
1341 | function prologue and epilogues, to allow SHcompact to comply | |
1342 | with the SH5 32-bit ABI, that requires 64-bit registers to be | |
1343 | used even though only the lower 32-bit half is visible in | |
1344 | SHcompact mode. The strategy is to call SHmedia trampolines. | |
1345 | ||
1346 | The alternatives for each of the argument-passing registers are | |
1347 | (a) leave it unchanged; (b) pop it off the stack; (c) load its | |
1348 | contents from the address in it; (d) add 8 to it, storing the | |
1349 | result in the next register, then (c); (e) copy it from some | |
1350 | floating-point register, | |
1351 | ||
1352 | Regarding copies from floating-point registers, r2 may only be | |
1353 | copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe | |
1354 | copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2, | |
1355 | dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8. | |
1356 | r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or | |
1357 | dr10. | |
1358 | ||
1359 | The bit mask is structured as follows: | |
1360 | ||
1361 | - 1 bit to tell whether to set up a return trampoline. | |
1362 | ||
1363 | - 3 bits to count the number consecutive registers to pop off the | |
1364 | stack. | |
1365 | ||
1366 | - 4 bits for each of r9, r8, r7 and r6. | |
1367 | ||
1368 | - 3 bits for each of r5, r4, r3 and r2. | |
1369 | ||
1370 | - 3 bits set to 0 (the most significant ones) | |
1371 | ||
1372 | 3 2 1 0 | |
1373 | 1098 7654 3210 9876 5432 1098 7654 3210 | |
1374 | FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST | |
1375 | 2223 3344 4555 6666 7777 8888 9999 SSS- | |
1376 | ||
1377 | - If F is set, the register must be copied from an FP register, | |
1378 | whose number is encoded in the remaining bits. | |
1379 | ||
1380 | - Else, if L is set, the register must be loaded from the address | |
1381 | contained in it. If the P bit is *not* set, the address of the | |
1382 | following dword should be computed first, and stored in the | |
1383 | following register. | |
1384 | ||
1385 | - Else, if P is set, the register alone should be popped off the | |
1386 | stack. | |
1387 | ||
1388 | - After all this processing, the number of registers represented | |
1389 | in SSS will be popped off the stack. This is an optimization | |
1390 | for pushing/popping consecutive registers, typically used for | |
1391 | varargs and large arguments partially passed in registers. | |
1392 | ||
1393 | - If T is set, a return trampoline will be set up for 64-bit | |
1394 | return values to be split into 2 32-bit registers. */ | |
f328f118 | 1395 | long call_cookie; |
1396 | ||
1397 | /* This is set to nonzero when the call in question must use the Renesas ABI, | |
1398 | even without the -mrenesas option. */ | |
1399 | int renesas_abi; | |
1400 | }; | |
1401 | ||
87e19636 | 1402 | #define CALL_COOKIE_RET_TRAMP_SHIFT 0 |
1403 | #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT) | |
1404 | #define CALL_COOKIE_STACKSEQ_SHIFT 1 | |
1405 | #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT) | |
1406 | #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \ | |
1407 | (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7) | |
1408 | #define CALL_COOKIE_INT_REG_SHIFT(REG) \ | |
1409 | (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3) | |
1410 | #define CALL_COOKIE_INT_REG(REG, VAL) \ | |
1411 | ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG)) | |
1412 | #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \ | |
1413 | (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15)) | |
07a356f1 | 1414 | |
1415 | #define CUMULATIVE_ARGS struct sh_args | |
1416 | ||
1417 | #define GET_SH_ARG_CLASS(MODE) \ | |
87e19636 | 1418 | ((TARGET_FPU_ANY && (MODE) == SFmode) \ |
1b61190c | 1419 | ? SH_ARG_FLOAT \ |
87e19636 | 1420 | /* There's no mention of complex float types in the SH5 ABI, so we |
1421 | should presumably handle them as aggregate types. */ \ | |
1422 | : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \ | |
1423 | ? SH_ARG_INT \ | |
1424 | : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1425 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ | |
1b61190c | 1426 | ? SH_ARG_FLOAT : SH_ARG_INT) |
7208c779 | 1427 | |
7208c779 | 1428 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1429 | for a call to a function whose data type is FNTYPE. | |
1430 | For a library call, FNTYPE is 0. | |
1431 | ||
1432 | On SH, the offset always starts at 0: the first parm reg is always | |
5be96103 | 1433 | the same reg for a given argument class. |
1434 | ||
1435 | For TARGET_HITACHI, the structure value pointer is passed in memory. */ | |
30c70355 | 1436 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
6c049e03 | 1437 | sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL),\ |
1438 | (N_NAMED_ARGS), VOIDmode) | |
87e19636 | 1439 | |
1440 | #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
43b3dabf | 1441 | sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE)) |
7208c779 | 1442 | |
d8e6ba8f | 1443 | /* By accident we got stuck with passing SCmode on SH4 little endian |
1444 | in two registers that are nominally successive - which is different from | |
1445 | two single SFmode values, where we take endianness translation into | |
1446 | account. That does not work at all if an odd number of registers is | |
1447 | already in use, so that got fixed, but library functions are still more | |
1448 | likely to use complex numbers without mixing them with SFmode arguments | |
1449 | (which in C would have to be structures), so for the sake of ABI | |
1450 | compatibility the way SCmode values are passed when an even number of | |
1451 | FP registers is in use remains different from a pair of SFmode values for | |
1452 | now. | |
1453 | I.e.: | |
1454 | foo (double); a: fr5,fr4 | |
1455 | foo (float a, float b); a: fr5 b: fr4 | |
1456 | foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency, | |
6c049e03 | 1457 | this should be the other way round... |
d8e6ba8f | 1458 | foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */ |
1459 | #define FUNCTION_ARG_SCmode_WART 1 | |
1460 | ||
87e19636 | 1461 | /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit |
1462 | register in SHcompact mode, it must be padded in the most | |
1463 | significant end. This means that passing it by reference wouldn't | |
1464 | pad properly on a big-endian machine. In this particular case, we | |
1465 | pass this argument on the stack, in a way that the call trampoline | |
1466 | will load its value into the appropriate register. */ | |
1467 | #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \ | |
1468 | ((MODE) == BLKmode \ | |
1469 | && TARGET_SHCOMPACT \ | |
adb7af07 | 1470 | && TARGET_BIG_ENDIAN \ |
87e19636 | 1471 | && int_size_in_bytes (TYPE) > 4 \ |
1472 | && int_size_in_bytes (TYPE) < 8) | |
1473 | ||
1474 | /* Minimum alignment for an argument to be passed by callee-copy | |
1475 | reference. We need such arguments to be aligned to 8 byte | |
1476 | boundaries, because they'll be loaded using quad loads. */ | |
1477 | #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT) | |
1478 | ||
87e19636 | 1479 | /* The SH5 ABI requires floating-point arguments to be passed to |
1480 | functions without a prototype in both an FP register and a regular | |
1481 | register or the stack. When passing the argument in both FP and | |
1482 | general-purpose registers, list the FP register first. */ | |
1483 | #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \ | |
1484 | (gen_rtx_PARALLEL \ | |
1485 | ((MODE), \ | |
1486 | gen_rtvec (2, \ | |
1487 | gen_rtx_EXPR_LIST \ | |
1488 | (VOIDmode, \ | |
1489 | ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ | |
1490 | ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \ | |
1491 | + (CUM).arg_count[(int) SH_ARG_FLOAT]) \ | |
1492 | : NULL_RTX), \ | |
1493 | const0_rtx), \ | |
1494 | gen_rtx_EXPR_LIST \ | |
1495 | (VOIDmode, \ | |
1496 | ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ | |
1497 | ? gen_rtx_REG ((MODE), FIRST_PARM_REG \ | |
1498 | + (CUM).arg_count[(int) SH_ARG_INT]) \ | |
1499 | : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \ | |
1500 | + (CUM).arg_count[(int) SH_ARG_FLOAT])), \ | |
1501 | const0_rtx)))) | |
1502 | ||
1503 | /* The SH5 ABI requires regular registers or stack slots to be | |
1504 | reserved for floating-point arguments. Registers are taken care of | |
1505 | in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here. | |
1506 | Unfortunately, there's no way to just reserve a stack slot, so | |
1507 | we'll end up needlessly storing a copy of the argument in the | |
1508 | stack. For incoming arguments, however, the PARALLEL will be | |
1509 | optimized to the register-only form, and the value in the stack | |
1510 | slot won't be used at all. */ | |
1511 | #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \ | |
1512 | ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ | |
1513 | ? gen_rtx_REG ((MODE), (REG)) \ | |
1514 | : gen_rtx_PARALLEL ((MODE), \ | |
1515 | gen_rtvec (2, \ | |
1516 | gen_rtx_EXPR_LIST \ | |
1517 | (VOIDmode, NULL_RTX, \ | |
1518 | const0_rtx), \ | |
1519 | gen_rtx_EXPR_LIST \ | |
1520 | (VOIDmode, gen_rtx_REG ((MODE), \ | |
1521 | (REG)), \ | |
1522 | const0_rtx)))) | |
1523 | ||
87e19636 | 1524 | #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
1fe27026 | 1525 | (TARGET_SH5 \ |
1526 | && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \ | |
1527 | || (MODE) == DCmode) \ | |
87e19636 | 1528 | && ((CUM).arg_count[(int) SH_ARG_INT] \ |
f01e5412 | 1529 | + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \ |
1530 | : GET_MODE_SIZE (MODE)) \ | |
1531 | + 7) / 8) > NPARM_REGS (SImode)) | |
87e19636 | 1532 | |
7208c779 | 1533 | /* Perform any needed actions needed for a function that is receiving a |
641e8334 | 1534 | variable number of arguments. */ |
7208c779 | 1535 | |
24c4b61a | 1536 | /* Call the function profiler with a given profile label. |
1537 | We use two .aligns, so as to make sure that both the .long is aligned | |
1538 | on a 4 byte boundary, and that the .long is a fixed distance (2 bytes) | |
1539 | from the trapa instruction. */ | |
47c009e5 | 1540 | #define FUNCTION_PROFILER(STREAM,LABELNO) \ |
1541 | { \ | |
59312820 | 1542 | if (TARGET_SHMEDIA) \ |
1543 | { \ | |
1544 | fprintf((STREAM), "\tmovi\t33,r0\n"); \ | |
1545 | fprintf((STREAM), "\ttrapa\tr0\n"); \ | |
1546 | asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ | |
1547 | } \ | |
1548 | else \ | |
1549 | { \ | |
1550 | fprintf((STREAM), "\t.align\t2\n"); \ | |
1551 | fprintf((STREAM), "\ttrapa\t#33\n"); \ | |
1552 | fprintf((STREAM), "\t.align\t2\n"); \ | |
1553 | asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ | |
1554 | } \ | |
7208c779 | 1555 | } |
1556 | ||
9461e7f0 | 1557 | /* Define this macro if the code for function profiling should come |
1558 | before the function prologue. Normally, the profiling code comes | |
1559 | after. */ | |
9461e7f0 | 1560 | #define PROFILE_BEFORE_PROLOGUE |
1561 | ||
7208c779 | 1562 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1563 | the stack pointer does not matter. The value is tested only in | |
1564 | functions that have frame pointers. | |
1565 | No definition is equivalent to always zero. */ | |
5cbb8e38 | 1566 | #define EXIT_IGNORE_STACK 1 |
7208c779 | 1567 | |
894b8fd9 | 1568 | /* |
01cc3b75 | 1569 | On the SH, the trampoline looks like |
6c049e03 | 1570 | 2 0002 D202 mov.l l2,r2 |
1571 | 1 0000 D301 mov.l l1,r3 | |
1572 | 3 0004 422B jmp @r2 | |
1573 | 4 0006 0009 nop | |
d67085f7 | 1574 | 5 0008 00000000 l1: .long area |
1575 | 6 000c 00000000 l2: .long function */ | |
7208c779 | 1576 | |
1577 | /* Length in units of the trampoline for entering a nested function. */ | |
bcc58dc6 | 1578 | #define TRAMPOLINE_SIZE \ |
1579 | (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : TARGET_FDPIC ? 32 : 16) | |
7208c779 | 1580 | |
2e752f00 | 1581 | /* Alignment required for a trampoline in bits. */ |
0dbd1c74 | 1582 | #define TRAMPOLINE_ALIGNMENT \ |
2e752f00 | 1583 | ((CACHE_LOG < 3 \ |
1584 | || (optimize_size && ! (TARGET_HARD_SH4 || TARGET_SH5))) ? 32 \ | |
e40c2d35 | 1585 | : TARGET_SHMEDIA ? 256 : 64) |
7208c779 | 1586 | |
1ae4c297 | 1587 | /* A C expression whose value is RTL representing the value of the return |
1588 | address for the frame COUNT steps up from the current frame. | |
1589 | FRAMEADDR is already the frame pointer of the COUNT frame, so we | |
1590 | can ignore COUNT. */ | |
1ae4c297 | 1591 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
c3583c9c | 1592 | (((COUNT) == 0) ? sh_get_pr_initial_val () : NULL_RTX) |
363600c8 | 1593 | |
1594 | /* A C expression whose value is RTL representing the location of the | |
1595 | incoming return address at the beginning of any function, before the | |
1596 | prologue. This RTL is either a REG, indicating that the return | |
1597 | value is saved in REG, or a MEM representing a location in | |
1598 | the stack. */ | |
1599 | #define INCOMING_RETURN_ADDR_RTX \ | |
1600 | gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) | |
7208c779 | 1601 | \f |
1602 | /* Addressing modes, and classification of registers for them. */ | |
87e19636 | 1603 | #define HAVE_POST_INCREMENT TARGET_SH1 |
87e19636 | 1604 | #define HAVE_PRE_DECREMENT TARGET_SH1 |
7208c779 | 1605 | |
53bd09ab | 1606 | #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \ |
6c049e03 | 1607 | ? 0 : TARGET_SH1) |
53bd09ab | 1608 | #define USE_LOAD_PRE_DECREMENT(mode) 0 |
1609 | #define USE_STORE_POST_INCREMENT(mode) 0 | |
1610 | #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \ | |
6c049e03 | 1611 | ? 0 : TARGET_SH1) |
53bd09ab | 1612 | |
1878fb5b | 1613 | /* If a memory clear move would take CLEAR_RATIO or more simple |
1614 | move-instruction pairs, we will do a setmem instead. */ | |
1615 | ||
1616 | #define CLEAR_RATIO(speed) ((speed) ? 15 : 3) | |
1617 | ||
7208c779 | 1618 | /* Macros to check register numbers against specific register classes. */ |
1619 | ||
1620 | /* These assume that REGNO is a hard or pseudo reg number. | |
1621 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1622 | or a pseudo reg currently allocated to a suitable hard reg. | |
1623 | Since they use reg_renumber, they are safe only once reg_renumber | |
957b2bdc | 1624 | has been allocated, which happens in reginfo.c during register |
1625 | allocation. */ | |
9d1ff654 | 1626 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
e2142b04 | 1627 | (GENERAL_OR_AP_REGISTER_P (REGNO) \ |
1628 | || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)])) | |
9d1ff654 | 1629 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
87e19636 | 1630 | (TARGET_SHMEDIA \ |
1631 | ? (GENERAL_REGISTER_P (REGNO) \ | |
1632 | || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \ | |
1633 | : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG) | |
7208c779 | 1634 | |
bcc58dc6 | 1635 | /* True if SYMBOL + OFFSET constants must refer to something within |
1636 | SYMBOL's section. */ | |
1637 | #define SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P TARGET_FDPIC | |
1638 | ||
641e8334 | 1639 | /* Maximum number of registers that can appear in a valid memory |
1640 | address. */ | |
97595bfd | 1641 | #define MAX_REGS_PER_ADDRESS 2 |
7208c779 | 1642 | |
1643 | /* Recognize any constant value that is a valid address. */ | |
9d1ff654 | 1644 | #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) |
7208c779 | 1645 | |
7208c779 | 1646 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1647 | and check its validity for a certain class. | |
36fa166c | 1648 | The suitable hard regs are always accepted and all pseudo regs |
1649 | are also accepted if STRICT is not set. */ | |
1650 | ||
1651 | /* Nonzero if X is a reg that can be used as a base reg. */ | |
1652 | #define REG_OK_FOR_BASE_P(X, STRICT) \ | |
1653 | (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \ | |
1654 | || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) | |
1655 | ||
1656 | /* Nonzero if X is a reg that can be used as an index. */ | |
1657 | #define REG_OK_FOR_INDEX_P(X, STRICT) \ | |
1658 | ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \ | |
1659 | : REGNO (X) == R0_REG) \ | |
1660 | || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) | |
1661 | ||
1662 | /* Nonzero if X/OFFSET is a reg that can be used as an index. */ | |
1663 | #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \ | |
1664 | ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \ | |
1665 | : REGNO (X) == R0_REG && OFFSET == 0) \ | |
1666 | || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) | |
97595bfd | 1667 | |
abff7a2e | 1668 | /* Macros for extra constraints. */ |
97595bfd | 1669 | |
6c049e03 | 1670 | #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \ |
abff7a2e | 1671 | ((GET_CODE ((OP)) == LABEL_REF) \ |
1672 | || (GET_CODE ((OP)) == CONST \ | |
1673 | && GET_CODE (XEXP ((OP), 0)) == PLUS \ | |
1674 | && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \ | |
cbb16986 | 1675 | && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))) |
af2c1324 | 1676 | |
abff7a2e | 1677 | #define IS_NON_EXPLICIT_CONSTANT_P(OP) \ |
1678 | (CONSTANT_P (OP) \ | |
6c049e03 | 1679 | && !CONST_INT_P (OP) \ |
abff7a2e | 1680 | && GET_CODE (OP) != CONST_DOUBLE \ |
1681 | && (!flag_pic \ | |
1682 | || (LEGITIMATE_PIC_OPERAND_P (OP) \ | |
20ba855a | 1683 | && !PIC_ADDR_P (OP) \ |
abff7a2e | 1684 | && GET_CODE (OP) != LABEL_REF))) |
561c35b4 | 1685 | |
87e19636 | 1686 | /* Check whether OP is a datalabel unspec. */ |
1687 | #define DATALABEL_REF_NO_CONST_P(OP) \ | |
1688 | (GET_CODE (OP) == UNSPEC \ | |
1689 | && XINT ((OP), 1) == UNSPEC_DATALABEL \ | |
1690 | && XVECLEN ((OP), 0) == 1 \ | |
59312820 | 1691 | && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF) |
87e19636 | 1692 | |
1693 | #define GOT_ENTRY_P(OP) \ | |
1694 | (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
1695 | && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT) | |
1696 | ||
1697 | #define GOTPLT_ENTRY_P(OP) \ | |
1698 | (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
1699 | && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT) | |
1700 | ||
2aa0e8cc | 1701 | #define UNSPEC_GOTOFF_P(OP) \ |
1702 | (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF) | |
1703 | ||
87e19636 | 1704 | #define GOTOFF_P(OP) \ |
2aa0e8cc | 1705 | (GET_CODE (OP) == CONST \ |
1706 | && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \ | |
1707 | || (GET_CODE (XEXP ((OP), 0)) == PLUS \ | |
6c049e03 | 1708 | && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \ |
cbb16986 | 1709 | && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))) |
87e19636 | 1710 | |
1711 | #define PIC_ADDR_P(OP) \ | |
1712 | (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
1713 | && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC) | |
1714 | ||
20ba855a | 1715 | #define PCREL_SYMOFF_P(OP) \ |
1716 | (GET_CODE (OP) == CONST \ | |
1717 | && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
1718 | && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF) | |
af2c1324 | 1719 | |
87e19636 | 1720 | #define NON_PIC_REFERENCE_P(OP) \ |
1721 | (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \ | |
59312820 | 1722 | || (GET_CODE (OP) == CONST \ |
1723 | && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \ | |
1724 | || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \ | |
1725 | || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \ | |
87e19636 | 1726 | || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \ |
1727 | && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \ | |
59312820 | 1728 | || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \ |
1729 | || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \ | |
cbb16986 | 1730 | && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))) |
87e19636 | 1731 | |
1732 | #define PIC_REFERENCE_P(OP) \ | |
1733 | (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \ | |
1734 | || GOTOFF_P (OP) || PIC_ADDR_P (OP)) | |
1735 | ||
1736 | #define MOVI_SHORI_BASE_OPERAND_P(OP) \ | |
af2c1324 | 1737 | (flag_pic \ |
1738 | ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \ | |
20ba855a | 1739 | || PCREL_SYMOFF_P (OP)) \ |
af2c1324 | 1740 | : NON_PIC_REFERENCE_P (OP)) |
7208c779 | 1741 | \f |
36fa166c | 1742 | #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \ |
cbb16986 | 1743 | ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \ |
36fa166c | 1744 | || (GET_CODE (X) == SUBREG \ |
1745 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \ | |
59312820 | 1746 | GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \ |
cbb16986 | 1747 | && REG_P (SUBREG_REG (X)) \ |
36fa166c | 1748 | && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT))) |
7208c779 | 1749 | |
8e5606b5 | 1750 | /* Since this must be r0, which is a single register class, we must check |
1751 | SUBREGs more carefully, to be sure that we don't accept one that extends | |
1752 | outside the class. */ | |
36fa166c | 1753 | #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \ |
cbb16986 | 1754 | ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \ |
36fa166c | 1755 | || (GET_CODE (X) == SUBREG \ |
59312820 | 1756 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \ |
1757 | GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \ | |
cbb16986 | 1758 | && REG_P (SUBREG_REG (X)) \ |
36fa166c | 1759 | && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT))) |
1760 | ||
1761 | #ifdef REG_OK_STRICT | |
1762 | #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true) | |
1763 | #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true) | |
1764 | #else | |
1765 | #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false) | |
1766 | #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false) | |
1767 | #endif | |
7208c779 | 1768 | |
59312820 | 1769 | #define ALLOW_INDEXED_ADDRESS \ |
1770 | ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS) | |
641e8334 | 1771 | \f |
35b7d8f7 | 1772 | /* A C compound statement that attempts to replace X, which is an address |
1773 | that needs reloading, with a valid memory address for an operand of | |
299fa1f5 | 1774 | mode MODE. WIN is a C statement label elsewhere in the code. */ |
35b7d8f7 | 1775 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
299fa1f5 | 1776 | do { \ |
1777 | if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \ | |
35b7d8f7 | 1778 | goto WIN; \ |
299fa1f5 | 1779 | } while (0) |
7208c779 | 1780 | \f |
1781 | /* Specify the machine mode that this machine uses | |
1782 | for the index in the tablejump instruction. */ | |
9df2aa62 | 1783 | #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode) |
7208c779 | 1784 | |
9eaab178 | 1785 | #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ |
1786 | ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \ | |
9eaab178 | 1787 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ |
a8c876a4 | 1788 | : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ |
1789 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ | |
9eaab178 | 1790 | : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \ |
1791 | : SImode) | |
1792 | ||
25d1d1e9 | 1793 | /* Define as C expression which evaluates to nonzero if the tablejump |
1794 | instruction expects the table to contain offsets from the address of the | |
1795 | table. | |
9df03d69 | 1796 | Do not define this if the table should contain absolute addresses. */ |
25d1d1e9 | 1797 | #define CASE_VECTOR_PC_RELATIVE 1 |
7208c779 | 1798 | |
87e19636 | 1799 | /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */ |
1800 | #define FLOAT_TYPE_SIZE 32 | |
1801 | ||
87ed74ef | 1802 | /* Since the SH2e has only `float' support, it is desirable to make all |
07a356f1 | 1803 | floating point types equivalent to `float'. */ |
6c049e03 | 1804 | #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE)\ |
1805 | ? 32 : 64) | |
07a356f1 | 1806 | |
641e8334 | 1807 | /* 'char' is signed by default. */ |
7208c779 | 1808 | #define DEFAULT_SIGNED_CHAR 1 |
1809 | ||
1810 | /* The type of size_t unsigned int. */ | |
87e19636 | 1811 | #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int") |
1812 | ||
87e19636 | 1813 | #undef PTRDIFF_TYPE |
1814 | #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int") | |
7208c779 | 1815 | |
2e3d4844 | 1816 | #define WCHAR_TYPE "short unsigned int" |
1817 | #define WCHAR_TYPE_SIZE 16 | |
3f67d569 | 1818 | |
1819 | #define SH_ELF_WCHAR_TYPE "long int" | |
2e3d4844 | 1820 | |
7208c779 | 1821 | /* Max number of bytes we can move from memory to memory |
1822 | in one reasonably fast instruction. */ | |
87e19636 | 1823 | #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4) |
1824 | ||
1825 | /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever | |
1826 | MOVE_MAX is not a compile-time constant. */ | |
1827 | #define MAX_MOVE_MAX 8 | |
7208c779 | 1828 | |
53bd09ab | 1829 | /* Max number of bytes we want move_by_pieces to be able to copy |
1830 | efficiently. */ | |
87e19636 | 1831 | #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4) |
53bd09ab | 1832 | |
29701bb8 | 1833 | /* Define if operations between registers always perform the operation |
1834 | on the full register even if a narrower mode is specified. */ | |
94f1fba7 | 1835 | #define WORD_REGISTER_OPERATIONS 1 |
29701bb8 | 1836 | |
1837 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1838 | will either zero-extend or sign-extend. The value of this macro should | |
1839 | be the code that says which one of the two operations is implicitly | |
6c049e03 | 1840 | done, UNKNOWN if none. |
1841 | For SHmedia, we can truncate to QImode easier using zero extension. | |
1842 | FP registers can load SImode values, but don't implicitly sign-extend | |
d3b29bbd | 1843 | them to DImode. */ |
e7196bd7 | 1844 | #define LOAD_EXTEND_OP(MODE) \ |
1845 | (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \ | |
21f1e711 | 1846 | : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN) |
7208c779 | 1847 | |
cfbbbcdb | 1848 | /* Define if loading short immediate values into registers sign extends. */ |
d0b99710 | 1849 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
cfbbbcdb | 1850 | |
b3b66a54 | 1851 | /* Nonzero if access to memory by bytes is no faster than for words. */ |
1852 | #define SLOW_BYTE_ACCESS 1 | |
1853 | ||
5e3df43c | 1854 | /* Nonzero if the target supports dynamic shift instructions |
1855 | like shad and shld. */ | |
1856 | #define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) | |
1857 | ||
6e7c6395 | 1858 | /* The cost of using the dynamic shift insns (shad, shld) are the same |
1859 | if they are available. If they are not available a library function will | |
1860 | be emitted instead, which is more expensive. */ | |
1861 | #define SH_DYNAMIC_SHIFT_COST (TARGET_DYNSHIFT ? 1 : 20) | |
1862 | ||
1863 | /* Defining SHIFT_COUNT_TRUNCATED tells the combine pass that code like | |
1864 | (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
1865 | This is not generally true when hardware dynamic shifts (shad, shld) are | |
1866 | used, because they check the sign bit _before_ the modulo op. The sign | |
1867 | bit determines whether it is a left shift or a right shift: | |
1868 | if (Y < 0) | |
1869 | return X << (Y & 31); | |
1870 | else | |
1871 | return X >> (-Y) & 31); | |
1872 | ||
1873 | The dynamic shift library routines in lib1funcs.S do not use the sign bit | |
1874 | like the hardware dynamic shifts and truncate the shift count to 31. | |
1875 | We define SHIFT_COUNT_TRUNCATED to 0 and express the implied shift count | |
1876 | truncation in the library function call patterns, as this gives slightly | |
1877 | more compact code. */ | |
1878 | #define SHIFT_COUNT_TRUNCATED (0) | |
7208c779 | 1879 | |
7208c779 | 1880 | /* All integers have the same format so truncation is easy. */ |
59312820 | 1881 | /* But SHmedia must sign-extend DImode when truncating to SImode. */ |
1882 | #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \ | |
1883 | (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64) | |
7208c779 | 1884 | |
1885 | /* Define this if addresses of constant functions | |
1886 | shouldn't be put through pseudo regs where they can be cse'd. | |
1887 | Desirable on machines where ordinary constants are expensive | |
1888 | but a CALL with constant address is cheap. */ | |
1889 | /*#define NO_FUNCTION_CSE 1*/ | |
1890 | ||
641e8334 | 1891 | /* The machine modes of pointers and functions. */ |
87e19636 | 1892 | #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode) |
7208c779 | 1893 | #define FUNCTION_MODE Pmode |
1894 | ||
13d406a0 | 1895 | /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2 |
1896 | are actually function calls with some special constraints on arguments | |
1897 | and register usage. | |
97595bfd | 1898 | |
641e8334 | 1899 | These macros tell reorg that the references to arguments and |
1900 | register clobbers for insns of type sfunc do not appear to happen | |
97595bfd | 1901 | until after the millicode call. This allows reorg to put insns |
1902 | which set the argument registers into the delay slot of the millicode | |
1903 | call -- thus they act more like traditional CALL_INSNs. | |
1904 | ||
75e90991 | 1905 | get_attr_is_sfunc will try to recognize the given insn, so make sure to |
97595bfd | 1906 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns |
1907 | in particular. */ | |
1908 | ||
1909 | #define INSN_SETS_ARE_DELAYED(X) \ | |
6c049e03 | 1910 | ((NONJUMP_INSN_P (X) \ |
97595bfd | 1911 | && GET_CODE (PATTERN (X)) != SEQUENCE \ |
1912 | && GET_CODE (PATTERN (X)) != USE \ | |
1913 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
75e90991 | 1914 | && get_attr_is_sfunc (X))) |
97595bfd | 1915 | |
1916 | #define INSN_REFERENCES_ARE_DELAYED(X) \ | |
6c049e03 | 1917 | ((NONJUMP_INSN_P (X) \ |
97595bfd | 1918 | && GET_CODE (PATTERN (X)) != SEQUENCE \ |
1919 | && GET_CODE (PATTERN (X)) != USE \ | |
1920 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
75e90991 | 1921 | && get_attr_is_sfunc (X))) |
97595bfd | 1922 | |
0abf894c | 1923 | \f |
1924 | /* Position Independent Code. */ | |
0abf894c | 1925 | |
2607b1ba | 1926 | /* We can't directly access anything that contains a symbol, |
1927 | nor can we indirect via the constant pool. */ | |
1928 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
1fe27026 | 1929 | ((! nonpic_symbol_mentioned_p (X) \ |
1930 | && (GET_CODE (X) != SYMBOL_REF \ | |
1931 | || ! CONSTANT_POOL_ADDRESS_P (X) \ | |
1932 | || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \ | |
1933 | || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF)) | |
2607b1ba | 1934 | |
0abf894c | 1935 | #define SYMBOLIC_CONST_P(X) \ |
1936 | ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \ | |
1937 | && nonpic_symbol_mentioned_p (X)) | |
1938 | \f | |
7208c779 | 1939 | /* Compute extra cost of moving data between one register class |
0dbd1c74 | 1940 | and another. */ |
7208c779 | 1941 | |
e04da7b6 | 1942 | /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass |
1943 | uses this information. Hence, the general register <-> floating point | |
1b61190c | 1944 | register information here is not used for SFmode. */ |
49607c69 | 1945 | #define REGCLASS_HAS_GENERAL_REG(CLASS) \ |
2a0b1a37 | 1946 | ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \ |
49607c69 | 1947 | || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) |
71c9de4b | 1948 | |
49607c69 | 1949 | #define REGCLASS_HAS_FP_REG(CLASS) \ |
1950 | ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \ | |
ec3c739c | 1951 | || (CLASS) == DF_REGS) |
49607c69 | 1952 | |
05f17f54 | 1953 | /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This |
5e164fba | 1954 | would be so that people with slow memory systems could generate |
05f17f54 | 1955 | different code that does fewer memory accesses. */ |
5e164fba | 1956 | |
1957 | /* A C expression for the cost of a branch instruction. A value of 1 | |
96d93b11 | 1958 | is the default; other values are interpreted relative to that. */ |
1959 | #define BRANCH_COST(speed_p, predictable_p) sh_branch_cost | |
7208c779 | 1960 | \f |
641e8334 | 1961 | /* Assembler output control. */ |
7208c779 | 1962 | |
61322ae9 | 1963 | /* A C string constant describing how to begin a comment in the target |
1964 | assembler language. The compiler assumes that the comment will end at | |
1965 | the end of the line. */ | |
1966 | #define ASM_COMMENT_START "!" | |
1967 | ||
97595bfd | 1968 | #define ASM_APP_ON "" |
1969 | #define ASM_APP_OFF "" | |
1970 | #define FILE_ASM_OP "\t.file\n" | |
327b40b7 | 1971 | #define SET_ASM_OP "\t.set\t" |
7208c779 | 1972 | |
641e8334 | 1973 | /* How to change between sections. */ |
6c049e03 | 1974 | #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 \ |
1975 | ? "\t.section\t.text..SHmedia32,\"ax\"" \ | |
1976 | : "\t.text") | |
1977 | #define DATA_SECTION_ASM_OP "\t.data" | |
47c009e5 | 1978 | |
87e19636 | 1979 | #if defined CRT_BEGIN || defined CRT_END |
1980 | /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */ | |
1981 | # undef TEXT_SECTION_ASM_OP | |
1982 | # if __SHMEDIA__ == 1 && __SH5__ == 32 | |
1983 | # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\"" | |
1984 | # else | |
1985 | # define TEXT_SECTION_ASM_OP "\t.text" | |
1986 | # endif | |
1987 | #endif | |
1988 | ||
ea50d488 | 1989 | #ifndef BSS_SECTION_ASM_OP |
327b40b7 | 1990 | #define BSS_SECTION_ASM_OP "\t.section\t.bss" |
ea50d488 | 1991 | #endif |
1992 | ||
ea50d488 | 1993 | #ifndef ASM_OUTPUT_ALIGNED_BSS |
1994 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
1995 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
1996 | #endif | |
1997 | ||
12e95e94 | 1998 | /* Define this so that jump tables go in same section as the current function, |
1999 | which could be text or it could be a user defined section. */ | |
6b5be7f8 | 2000 | #define JUMP_TABLES_IN_TEXT_SECTION 1 |
12e95e94 | 2001 | |
641e8334 | 2002 | #undef DO_GLOBAL_CTORS_BODY |
47c009e5 | 2003 | #define DO_GLOBAL_CTORS_BODY \ |
2004 | { \ | |
6392d503 | 2005 | typedef void (*pfunc) (void); \ |
47c009e5 | 2006 | extern pfunc __ctors[]; \ |
2007 | extern pfunc __ctors_end[]; \ | |
2008 | pfunc *p; \ | |
2c5a14aa | 2009 | for (p = __ctors_end; p > __ctors; ) \ |
47c009e5 | 2010 | { \ |
2c5a14aa | 2011 | (*--p)(); \ |
47c009e5 | 2012 | } \ |
641e8334 | 2013 | } |
47c009e5 | 2014 | |
641e8334 | 2015 | #undef DO_GLOBAL_DTORS_BODY |
9d1ff654 | 2016 | #define DO_GLOBAL_DTORS_BODY \ |
47c009e5 | 2017 | { \ |
6392d503 | 2018 | typedef void (*pfunc) (void); \ |
47c009e5 | 2019 | extern pfunc __dtors[]; \ |
2020 | extern pfunc __dtors_end[]; \ | |
2021 | pfunc *p; \ | |
2022 | for (p = __dtors; p < __dtors_end; p++) \ | |
2023 | { \ | |
2024 | (*p)(); \ | |
2025 | } \ | |
641e8334 | 2026 | } |
47c009e5 | 2027 | |
47c009e5 | 2028 | #define ASM_OUTPUT_REG_PUSH(file, v) \ |
59312820 | 2029 | { \ |
2030 | if (TARGET_SHMEDIA) \ | |
2031 | { \ | |
2032 | fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \ | |
2033 | fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \ | |
2034 | } \ | |
2035 | else \ | |
2036 | fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \ | |
2037 | } | |
7208c779 | 2038 | |
47c009e5 | 2039 | #define ASM_OUTPUT_REG_POP(file, v) \ |
59312820 | 2040 | { \ |
2041 | if (TARGET_SHMEDIA) \ | |
2042 | { \ | |
2043 | fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \ | |
2044 | fprintf ((file), "\taddi.l\tr15,8,r15\n"); \ | |
2045 | } \ | |
2046 | else \ | |
2047 | fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \ | |
2048 | } | |
47c009e5 | 2049 | |
641e8334 | 2050 | /* DBX register number for a given compiler register number. */ |
07a356f1 | 2051 | /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers |
2052 | to match gdb. */ | |
805e22b2 | 2053 | /* expand_builtin_init_dwarf_reg_sizes uses this to test if a |
2054 | register exists, so we should return -1 for invalid register numbers. */ | |
3f67d569 | 2055 | #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO) |
2056 | ||
7a1492b5 | 2057 | /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers |
2058 | used to use the encodings 245..260, but that doesn't make sense: | |
2059 | PR_REG and PR_MEDIA_REG are actually the same register, and likewise | |
2060 | the FP registers stay the same when switching between compact and media | |
efee20da | 2061 | mode. Hence, we also need to use the same dwarf frame columns. |
7a1492b5 | 2062 | Likewise, we need to support unwind information for SHmedia registers |
2063 | even in compact code. */ | |
3f67d569 | 2064 | #define SH_DBX_REGISTER_NUMBER(REGNO) \ |
7a1492b5 | 2065 | (IN_RANGE ((REGNO), \ |
2066 | (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ | |
2067 | FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \ | |
41fafa66 | 2068 | ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \ |
6c049e03 | 2069 | : ((int) (REGNO) >= FIRST_FP_REG \ |
7a1492b5 | 2070 | && ((int) (REGNO) \ |
2071 | <= (FIRST_FP_REG + \ | |
2072 | ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \ | |
41fafa66 | 2073 | ? ((unsigned) (REGNO) - FIRST_FP_REG \ |
7a1492b5 | 2074 | + (TARGET_SH5 ? 77 : 25)) \ |
87e19636 | 2075 | : XD_REGISTER_P (REGNO) \ |
41fafa66 | 2076 | ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \ |
87e19636 | 2077 | : TARGET_REGISTER_P (REGNO) \ |
41fafa66 | 2078 | ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \ |
87e19636 | 2079 | : (REGNO) == PR_REG \ |
7a1492b5 | 2080 | ? (TARGET_SH5 ? 18 : 17) \ |
1242cc7b | 2081 | : (REGNO) == PR_MEDIA_REG \ |
41fafa66 | 2082 | ? (TARGET_SH5 ? 18 : (unsigned) -1) \ |
87e19636 | 2083 | : (REGNO) == GBR_REG \ |
c5cff8fc | 2084 | ? (TARGET_SH5 ? 238 : 18) \ |
87e19636 | 2085 | : (REGNO) == MACH_REG \ |
2086 | ? (TARGET_SH5 ? 239 : 20) \ | |
2087 | : (REGNO) == MACL_REG \ | |
2088 | ? (TARGET_SH5 ? 240 : 21) \ | |
c5cff8fc | 2089 | : (REGNO) == T_REG \ |
2090 | ? (TARGET_SH5 ? 242 : 22) \ | |
87e19636 | 2091 | : (REGNO) == FPUL_REG \ |
2092 | ? (TARGET_SH5 ? 244 : 23) \ | |
c5cff8fc | 2093 | : (REGNO) == FPSCR_REG \ |
2094 | ? (TARGET_SH5 ? 243 : 24) \ | |
41fafa66 | 2095 | : (unsigned) -1) |
87e19636 | 2096 | |
87e19636 | 2097 | /* This is how to output a reference to a symbol_ref. On SH5, |
2098 | references to non-code symbols must be preceded by `datalabel'. */ | |
2099 | #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \ | |
2100 | do \ | |
2101 | { \ | |
2fb8cf90 | 2102 | if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \ |
87e19636 | 2103 | fputs ("datalabel ", (FILE)); \ |
2104 | assemble_name ((FILE), XSTR ((SYM), 0)); \ | |
2105 | } \ | |
2106 | while (0) | |
7208c779 | 2107 | |
7208c779 | 2108 | /* This is how to output an assembler line |
2109 | that says to advance the location counter | |
2110 | to a multiple of 2**LOG bytes. */ | |
2111 | ||
2112 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2113 | if ((LOG) != 0) \ | |
0dbd1c74 | 2114 | fprintf ((FILE), "\t.align %d\n", (LOG)) |
7208c779 | 2115 | |
0036ad94 | 2116 | /* Globalizing directive for a label. */ |
2117 | #define GLOBAL_ASM_OP "\t.global\t" | |
7208c779 | 2118 | |
6c049e03 | 2119 | /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ |
7208c779 | 2120 | |
641e8334 | 2121 | /* Output a relative address table. */ |
6c049e03 | 2122 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ |
9eaab178 | 2123 | switch (GET_MODE (BODY)) \ |
0dbd1c74 | 2124 | { \ |
2125 | case SImode: \ | |
87e19636 | 2126 | if (TARGET_SH5) \ |
2127 | { \ | |
2128 | asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \ | |
2129 | (VALUE), (REL)); \ | |
2130 | break; \ | |
2131 | } \ | |
0dbd1c74 | 2132 | asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \ |
2133 | break; \ | |
2134 | case HImode: \ | |
87e19636 | 2135 | if (TARGET_SH5) \ |
2136 | { \ | |
2137 | asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \ | |
2138 | (VALUE), (REL)); \ | |
2139 | break; \ | |
2140 | } \ | |
0dbd1c74 | 2141 | asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \ |
2142 | break; \ | |
2143 | case QImode: \ | |
87e19636 | 2144 | if (TARGET_SH5) \ |
2145 | { \ | |
2146 | asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \ | |
2147 | (VALUE), (REL)); \ | |
2148 | break; \ | |
2149 | } \ | |
0dbd1c74 | 2150 | asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \ |
2151 | break; \ | |
b7dbbdb2 | 2152 | default: \ |
2153 | break; \ | |
0dbd1c74 | 2154 | } |
7208c779 | 2155 | |
641e8334 | 2156 | /* Output an absolute table element. */ |
97595bfd | 2157 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ |
9df2aa62 | 2158 | if (! optimize || TARGET_BIGTABLE) \ |
87ab0a3d | 2159 | asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \ |
97595bfd | 2160 | else \ |
87ab0a3d | 2161 | asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); |
7208c779 | 2162 | |
7208c779 | 2163 | \f |
0dbd1c74 | 2164 | /* A C statement to be executed just prior to the output of |
2165 | assembler code for INSN, to modify the extracted operands so | |
2166 | they will be output differently. | |
2167 | ||
2168 | Here the argument OPVEC is the vector containing the operands | |
2169 | extracted from INSN, and NOPERANDS is the number of elements of | |
2170 | the vector which contain meaningful data for this insn. | |
2171 | The contents of this vector are what will be used to convert the insn | |
2172 | template into assembler code, so you can change the assembler output | |
2173 | by changing the contents of the vector. */ | |
9d1ff654 | 2174 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
0dbd1c74 | 2175 | final_prescan_insn ((INSN), (OPVEC), (NOPERANDS)) |
7208c779 | 2176 | |
7208c779 | 2177 | \f |
842ae815 | 2178 | extern rtx sh_compare_op0; |
2179 | extern rtx sh_compare_op1; | |
7208c779 | 2180 | |
641e8334 | 2181 | /* Which processor to schedule for. The elements of the enumeration must |
2182 | match exactly the cpu attribute in the sh.md file. */ | |
641e8334 | 2183 | enum processor_type { |
641e8334 | 2184 | PROCESSOR_SH1, |
2185 | PROCESSOR_SH2, | |
87ed74ef | 2186 | PROCESSOR_SH2E, |
7105fb72 | 2187 | PROCESSOR_SH2A, |
07a356f1 | 2188 | PROCESSOR_SH3, |
1b61190c | 2189 | PROCESSOR_SH3E, |
87e19636 | 2190 | PROCESSOR_SH4, |
9435e831 | 2191 | PROCESSOR_SH4A, |
87e19636 | 2192 | PROCESSOR_SH5 |
641e8334 | 2193 | }; |
2194 | ||
2195 | #define sh_cpu_attr ((enum attr_cpu)sh_cpu) | |
2196 | extern enum processor_type sh_cpu; | |
2197 | ||
0dbd1c74 | 2198 | enum mdep_reorg_phase_e |
2199 | { | |
2200 | SH_BEFORE_MDEP_REORG, | |
2201 | SH_INSERT_USES_LABELS, | |
2202 | SH_SHORTEN_BRANCHES0, | |
2203 | SH_FIXUP_PCLOAD, | |
2204 | SH_SHORTEN_BRANCHES1, | |
2205 | SH_AFTER_MDEP_REORG | |
2206 | }; | |
2207 | ||
9eaab178 | 2208 | extern enum mdep_reorg_phase_e mdep_reorg_phase; |
2209 | ||
7b23765d | 2210 | /* Handle Renesas compiler's pragmas. */ |
eb180587 | 2211 | #define REGISTER_TARGET_PRAGMAS() do { \ |
2212 | c_register_pragma (0, "interrupt", sh_pr_interrupt); \ | |
2213 | c_register_pragma (0, "trapa", sh_pr_trapa); \ | |
2214 | c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \ | |
1fcd08b1 | 2215 | } while (0) |
47c009e5 | 2216 | |
57d5535b | 2217 | extern tree sh_deferred_function_attributes; |
2218 | extern tree *sh_deferred_function_attributes_tail; | |
47c009e5 | 2219 | |
0d687b6d | 2220 | /* Set when processing a function with interrupt attribute. */ |
0d687b6d | 2221 | extern int current_function_interrupt; |
2222 | ||
bacf717a | 2223 | \f |
2522e445 | 2224 | /* Instructions with unfilled delay slots take up an |
2225 | extra two bytes for the nop in the delay slot. | |
2226 | sh-dsp parallel processing insns are four bytes long. */ | |
bacf717a | 2227 | #define ADJUST_INSN_LENGTH(X, LENGTH) \ |
2522e445 | 2228 | (LENGTH) += sh_insn_length_adjustment (X); |
9d1ff654 | 2229 | \f |
9d1ff654 | 2230 | /* Define this macro if it is advisable to hold scalars in registers |
894b8fd9 | 2231 | in a wider mode than that declared by the program. In such cases, |
9d1ff654 | 2232 | the value is constrained to be within the bounds of the declared |
2233 | type, but kept valid in the wider mode. The signedness of the | |
2234 | extension may differ from that of the type. | |
2235 | ||
2236 | Leaving the unsignedp unchanged gives better code than always setting it | |
2237 | to 0. This is despite the fact that we have only signed char and short | |
2238 | load instructions. */ | |
2239 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
2240 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
59312820 | 2241 | && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\ |
87e19636 | 2242 | (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \ |
59312820 | 2243 | (MODE) = (TARGET_SH1 ? SImode \ |
2244 | : TARGET_SHMEDIA32 ? SImode : DImode); | |
9d1ff654 | 2245 | |
030466b7 | 2246 | #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64) |
2247 | ||
992d172c | 2248 | /* Better to allocate once the maximum space for outgoing args in the |
2249 | prologue rather than duplicate around each call. */ | |
2250 | #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS | |
9d1ff654 | 2251 | |
18862b5a | 2252 | #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE } |
2253 | ||
7105fb72 | 2254 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE) |
18862b5a | 2255 | |
ab5ad604 | 2256 | #define ACTUAL_NORMAL_MODE(ENTITY) \ |
2257 | (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE) | |
2258 | ||
7dff60c8 | 2259 | #define NORMAL_MODE(ENTITY) \ |
36a2dfdb | 2260 | (sh_cfun_interrupt_handler_p () \ |
2261 | ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \ | |
ab5ad604 | 2262 | : ACTUAL_NORMAL_MODE (ENTITY)) |
7dff60c8 | 2263 | |
6c049e03 | 2264 | #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \ |
2265 | && (REGNO) == FPSCR_REG) | |
18862b5a | 2266 | |
ce8e8292 | 2267 | #define DWARF_FRAME_RETURN_COLUMN \ |
2268 | (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG)) | |
363600c8 | 2269 | |
805e22b2 | 2270 | #define EH_RETURN_DATA_REGNO(N) \ |
41fafa66 | 2271 | ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM) |
805e22b2 | 2272 | |
41fafa66 | 2273 | #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM |
2274 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) | |
805e22b2 | 2275 | |
7a1492b5 | 2276 | /* We have to distinguish between code and data, so that we apply |
06e58b52 | 2277 | datalabel where and only where appropriate. Use sdataN for data. */ |
7a1492b5 | 2278 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
bcc58dc6 | 2279 | ((TARGET_FDPIC \ |
2280 | ? ((GLOBAL) ? DW_EH_PE_indirect | DW_EH_PE_datarel : DW_EH_PE_pcrel) \ | |
2281 | : ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \ | |
2282 | | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))) \ | |
2283 | | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4))) | |
7a1492b5 | 2284 | |
2285 | /* Handle special EH pointer encodings. Absolute, pc-relative, and | |
2286 | indirect are handled automatically. */ | |
2287 | #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \ | |
2288 | do { \ | |
06e58b52 | 2289 | if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \ |
2290 | && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \ | |
7a1492b5 | 2291 | { \ |
1a6a7a27 | 2292 | gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \ |
7a1492b5 | 2293 | SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \ |
2294 | if (0) goto DONE; \ | |
2295 | } \ | |
bcc58dc6 | 2296 | if (TARGET_FDPIC \ |
2297 | && ((ENCODING) & 0xf0) == (DW_EH_PE_indirect | DW_EH_PE_datarel)) \ | |
2298 | { \ | |
2299 | fputs ("\t.ualong ", FILE); \ | |
2300 | output_addr_const (FILE, ADDR); \ | |
2301 | if (GET_CODE (ADDR) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (ADDR)) \ | |
2302 | fputs ("@GOTFUNCDESC", FILE); \ | |
2303 | else \ | |
2304 | fputs ("@GOT", FILE); \ | |
2305 | goto DONE; \ | |
2306 | } \ | |
7a1492b5 | 2307 | } while (0) |
2308 | ||
87e19636 | 2309 | #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ |
0abf894c | 2310 | /* SH constant pool breaks the devices in crtstuff.c to control section |
2311 | in where code resides. We have to write it as asm code. */ | |
e1ff7102 | 2312 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ |
2313 | asm (SECTION_OP "\n\ | |
2314 | mov.l 1f,r1\n\ | |
0abf894c | 2315 | mova 2f,r0\n\ |
2316 | braf r1\n\ | |
2317 | lds r0,pr\n\ | |
2318 | 0: .p2align 2\n\ | |
e1ff7102 | 2319 | 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\ |
2320 | 2:\n" TEXT_SECTION_ASM_OP); | |
87e19636 | 2321 | #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */ |
1fcd08b1 | 2322 | |
2a281353 | 2323 | #endif /* ! GCC_SH_H */ |