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c8f0269d | 1 | /* Definitions of target machine for GNU compiler for Renesas / SuperH SH. |
cbe34bb5 | 2 | Copyright (C) 1993-2017 Free Software Foundation, Inc. |
058f9bb5 JW |
3 | Contributed by Steve Chamberlain (sac@cygnus.com). |
4 | Improved by Jim Wilson (wilson@cygnus.com). | |
bc45ade3 | 5 | |
7ec022b2 | 6 | This file is part of GCC. |
bc45ade3 | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
bc45ade3 | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
bc45ade3 SC |
11 | any later version. |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
bc45ade3 SC |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
bc45ade3 | 21 | |
8b97c5f8 ZW |
22 | #ifndef GCC_SH_H |
23 | #define GCC_SH_H | |
8b109b37 | 24 | |
f5c7290e RS |
25 | #include "config/vxworks-dummy.h" |
26 | ||
e9a25f70 | 27 | /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't |
4977bab6 | 28 | include it here, because bconfig.h is also included by gencodes.c . */ |
5e7f4a4a | 29 | /* ??? No longer true. */ |
e9a25f70 JL |
30 | extern int code_for_indirect_jump_scratch; |
31 | ||
9597375a | 32 | #define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile) |
00f8ff66 | 33 | |
7a296495 CB |
34 | /* Value should be nonzero if functions must have frame pointers. |
35 | Zero means the frame pointer need not be set up (and parms may be accessed | |
36 | via the stack pointer) in functions that seem suitable. */ | |
37 | ||
38 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
39 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
40 | #endif | |
0d7e008e | 41 | |
bc45ade3 | 42 | \f |
1bc7c5b6 ZW |
43 | /* Nonzero if this is an ELF target - compile time only */ |
44 | #define TARGET_ELF 0 | |
45 | ||
3a8699c7 | 46 | /* Nonzero if we should generate code using type 2E insns. */ |
c0fb94d7 | 47 | #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E) |
3a8699c7 | 48 | |
157371cf | 49 | /* Nonzero if we should generate code using type 2A insns. */ |
c0fb94d7 | 50 | #define TARGET_SH2A TARGET_HARD_SH2A |
157371cf | 51 | /* Nonzero if we should generate code using type 2A SF insns. */ |
c0fb94d7 | 52 | #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E) |
157371cf | 53 | /* Nonzero if we should generate code using type 2A DF insns. */ |
c0fb94d7 | 54 | #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A) |
bc45ade3 | 55 | |
5c3ea805 | 56 | /* Nonzero if we should generate code using type 3E insns. */ |
c0fb94d7 | 57 | #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E) |
5c3ea805 | 58 | |
6f317ef3 | 59 | /* Nonzero if we schedule for a superscalar implementation. */ |
ead4af4f | 60 | #define TARGET_SUPERSCALAR (TARGET_HARD_SH4 || TARGET_SH2A) |
225e4f43 | 61 | |
fa5322fa | 62 | /* Nonzero if a double-precision FPU is available. */ |
d5dd0a62 | 63 | #define TARGET_FPU_DOUBLE (TARGET_SH4 || TARGET_SH2A_DOUBLE) |
fa5322fa AO |
64 | |
65 | /* Nonzero if an FPU is available. */ | |
3a8699c7 | 66 | #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE) |
fa5322fa | 67 | |
312209c6 AO |
68 | /* Nonzero if we're generating code for SH4a, unless the use of the |
69 | FPU is disabled (which makes it compatible with SH4al-dsp). */ | |
f3ca7111 | 70 | #define TARGET_SH4A_FP (TARGET_SH4A && TARGET_FPU_ANY) |
312209c6 | 71 | |
fe3ad572 | 72 | |
49616835 JR |
73 | /* This is not used by the SH2E calling convention */ |
74 | #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \ | |
f1bebab6 | 75 | (! TARGET_SH2E \ |
49616835 JR |
76 | && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL))) |
77 | ||
da28a3b9 JR |
78 | #ifndef TARGET_CPU_DEFAULT |
79 | #define TARGET_CPU_DEFAULT SELECT_SH1 | |
c0fb94d7 RS |
80 | #define SUPPORT_SH1 1 |
81 | #define SUPPORT_SH2E 1 | |
82 | #define SUPPORT_SH4 1 | |
83 | #define SUPPORT_SH4_SINGLE 1 | |
84 | #define SUPPORT_SH2A 1 | |
85 | #define SUPPORT_SH2A_SINGLE 1 | |
da28a3b9 JR |
86 | #endif |
87 | ||
b368d6b8 R |
88 | #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) |
89 | #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP) | |
90 | #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE) | |
73a4d10b | 91 | |
50fe8924 OE |
92 | #define SELECT_SH1 (MASK_SH1) |
93 | #define SELECT_SH2 (MASK_SH2 | SELECT_SH1) | |
94 | #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \ | |
c0fb94d7 | 95 | | MASK_FPU_SINGLE) |
50fe8924 | 96 | #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \ |
c0fb94d7 RS |
97 | | MASK_HARD_SH2A_DOUBLE \ |
98 | | MASK_SH2 | MASK_SH1) | |
50fe8924 | 99 | #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1) |
c0fb94d7 | 100 | #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \ |
decc676e OE |
101 | | MASK_SH1 | MASK_FPU_SINGLE \ |
102 | | MASK_FPU_SINGLE_ONLY) | |
50fe8924 | 103 | #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \ |
c0fb94d7 RS |
104 | | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \ |
105 | | MASK_SH2 | MASK_SH1) | |
50fe8924 OE |
106 | #define SELECT_SH3 (MASK_SH3 | SELECT_SH2) |
107 | #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3) | |
108 | #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3) | |
decc676e OE |
109 | #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E \ |
110 | | MASK_FPU_SINGLE_ONLY) | |
50fe8924 | 111 | #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \ |
c0fb94d7 | 112 | | SELECT_SH3) |
50fe8924 OE |
113 | #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4) |
114 | #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU) | |
c0fb94d7 | 115 | #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) |
50fe8924 OE |
116 | #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) |
117 | #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) | |
da28a3b9 | 118 | |
c0fb94d7 RS |
119 | #if SUPPORT_SH1 |
120 | #define SUPPORT_SH2 1 | |
da28a3b9 | 121 | #endif |
c0fb94d7 RS |
122 | #if SUPPORT_SH2 |
123 | #define SUPPORT_SH3 1 | |
78d310c2 | 124 | #define SUPPORT_SH2A_NOFPU 1 |
da28a3b9 | 125 | #endif |
c0fb94d7 RS |
126 | #if SUPPORT_SH3 |
127 | #define SUPPORT_SH4_NOFPU 1 | |
312209c6 | 128 | #endif |
c0fb94d7 RS |
129 | #if SUPPORT_SH4_NOFPU |
130 | #define SUPPORT_SH4A_NOFPU 1 | |
131 | #define SUPPORT_SH4AL 1 | |
da28a3b9 JR |
132 | #endif |
133 | ||
c0fb94d7 RS |
134 | #if SUPPORT_SH2E |
135 | #define SUPPORT_SH3E 1 | |
78d310c2 | 136 | #define SUPPORT_SH2A_SINGLE_ONLY 1 |
da28a3b9 | 137 | #endif |
c0fb94d7 RS |
138 | #if SUPPORT_SH3E |
139 | #define SUPPORT_SH4_SINGLE_ONLY 1 | |
78d310c2 R |
140 | #endif |
141 | #if SUPPORT_SH4_SINGLE_ONLY | |
c0fb94d7 | 142 | #define SUPPORT_SH4A_SINGLE_ONLY 1 |
157371cf AO |
143 | #endif |
144 | ||
c0fb94d7 RS |
145 | #if SUPPORT_SH4 |
146 | #define SUPPORT_SH4A 1 | |
157371cf AO |
147 | #endif |
148 | ||
c0fb94d7 RS |
149 | #if SUPPORT_SH4_SINGLE |
150 | #define SUPPORT_SH4A_SINGLE 1 | |
da28a3b9 JR |
151 | #endif |
152 | ||
ae010e43 | 153 | /* Reset all target-selection flags. */ |
c0fb94d7 RS |
154 | #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ |
155 | | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ | |
e1fab8ba | 156 | | MASK_HARD_SH4 | MASK_FPU_SINGLE \ |
decc676e | 157 | | MASK_FPU_SINGLE_ONLY) |
5d84b57e | 158 | |
f1a58d92 R |
159 | /* This defaults us to big-endian. */ |
160 | #ifndef TARGET_ENDIAN_DEFAULT | |
161 | #define TARGET_ENDIAN_DEFAULT 0 | |
162 | #endif | |
163 | ||
73a4d10b | 164 | #ifndef TARGET_OPT_DEFAULT |
3e4907f4 | 165 | #define TARGET_OPT_DEFAULT 0 |
73a4d10b R |
166 | #endif |
167 | ||
168 | #define TARGET_DEFAULT \ | |
169 | (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT) | |
170 | ||
da28a3b9 JR |
171 | #ifndef SH_MULTILIB_CPU_DEFAULT |
172 | #define SH_MULTILIB_CPU_DEFAULT "m1" | |
8bc6e101 R |
173 | #endif |
174 | ||
da28a3b9 JR |
175 | #if TARGET_ENDIAN_DEFAULT |
176 | #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT } | |
177 | #else | |
178 | #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT } | |
179 | #endif | |
f1a58d92 R |
180 | |
181 | #define CPP_SPEC " %(subtarget_cpp_spec) " | |
182 | ||
183 | #ifndef SUBTARGET_CPP_SPEC | |
184 | #define SUBTARGET_CPP_SPEC "" | |
185 | #endif | |
186 | ||
6a79bb0a JT |
187 | #ifndef SUBTARGET_EXTRA_SPECS |
188 | #define SUBTARGET_EXTRA_SPECS | |
189 | #endif | |
190 | ||
f1a58d92 R |
191 | #define EXTRA_SPECS \ |
192 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ | |
193 | { "link_emul_prefix", LINK_EMUL_PREFIX }, \ | |
194 | { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \ | |
195 | { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \ | |
196 | { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \ | |
6a79bb0a | 197 | { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \ |
d44cc404 | 198 | { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \ |
73a4d10b R |
199 | { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \ |
200 | { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ | |
6a79bb0a | 201 | SUBTARGET_EXTRA_SPECS |
f1a58d92 | 202 | |
c0fb94d7 | 203 | #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 |
aec12a46 | 204 | #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:-isa=sh4-up}}}" |
d44cc404 | 205 | #else |
45e49d96 | 206 | #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}" |
d44cc404 R |
207 | #endif |
208 | ||
1b8da635 OE |
209 | /* Define which ISA type to pass to the assembler. |
210 | For SH4 we pass SH4A to allow using some instructions that are available | |
211 | on some SH4 variants, but officially are part of the SH4A ISA. */ | |
d44cc404 | 212 | #define SH_ASM_SPEC \ |
9b024103 AS |
213 | "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)} \ |
214 | %(subtarget_asm_isa_spec) %(subtarget_asm_spec) \ | |
1b8da635 OE |
215 | %{m1:--isa=sh} \ |
216 | %{m2:--isa=sh2} \ | |
217 | %{m2e:--isa=sh2e} \ | |
218 | %{m3:--isa=sh3} \ | |
219 | %{m3e:--isa=sh3e} \ | |
220 | %{m4:--isa=sh4a} \ | |
221 | %{m4-single:--isa=sh4a} \ | |
222 | %{m4-single-only:--isa=sh4a} \ | |
223 | %{m4-nofpu:--isa=sh4a-nofpu} \ | |
224 | %{m4a:--isa=sh4a} \ | |
225 | %{m4a-single:--isa=sh4a} \ | |
226 | %{m4a-single-only:--isa=sh4a} \ | |
227 | %{m4a-nofpu:--isa=sh4a-nofpu} \ | |
73a4d10b R |
228 | %{m2a:--isa=sh2a} \ |
229 | %{m2a-single:--isa=sh2a} \ | |
230 | %{m2a-single-only:--isa=sh2a} \ | |
231 | %{m2a-nofpu:--isa=sh2a-nofpu} \ | |
e1fab8ba | 232 | %{m4al:-dsp}" |
d44cc404 R |
233 | |
234 | #define ASM_SPEC SH_ASM_SPEC | |
f1a58d92 R |
235 | |
236 | #ifndef SUBTARGET_ASM_ENDIAN_SPEC | |
c0fb94d7 | 237 | #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN |
f1a58d92 R |
238 | #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}" |
239 | #else | |
240 | #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}" | |
241 | #endif | |
242 | #endif | |
243 | ||
73a4d10b R |
244 | #if STRICT_NOFPU == 1 |
245 | /* Strict nofpu means that the compiler should tell the assembler | |
246 | to reject FPU instructions. E.g. from ASM inserts. */ | |
c0fb94d7 | 247 | #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E) |
aec12a46 | 248 | #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" |
73a4d10b | 249 | #else |
e1fab8ba | 250 | |
73a4d10b R |
251 | #define SUBTARGET_ASM_ISA_SPEC \ |
252 | "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC | |
253 | #endif | |
254 | #else /* ! STRICT_NOFPU */ | |
255 | #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC | |
256 | #endif | |
d44cc404 | 257 | |
73a4d10b | 258 | #ifndef SUBTARGET_ASM_SPEC |
1e44e857 | 259 | #define SUBTARGET_ASM_SPEC "%{mfdpic:--fdpic}" |
73a4d10b R |
260 | #endif |
261 | ||
c0fb94d7 | 262 | #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN |
73a4d10b R |
263 | #define LINK_EMUL_PREFIX "sh%{!mb:l}" |
264 | #else | |
f1a58d92 | 265 | #define LINK_EMUL_PREFIX "sh%{ml:l}" |
73a4d10b | 266 | #endif |
8bc6e101 | 267 | |
f1a58d92 | 268 | #define LINK_DEFAULT_CPU_EMUL "" |
da28a3b9 | 269 | #define ASM_ISA_DEFAULT_SPEC "" |
8bc6e101 | 270 | |
1e44e857 | 271 | #define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd}" |
f1a58d92 R |
272 | #define SUBTARGET_LINK_SPEC "" |
273 | ||
57809813 | 274 | /* Go via SH_LINK_SPEC to avoid code replication. */ |
f1a58d92 R |
275 | #define LINK_SPEC SH_LINK_SPEC |
276 | ||
277 | #define SH_LINK_SPEC "\ | |
278 | -m %(link_emul_prefix)\ | |
e1fab8ba | 279 | %{!m1:%{!m2:%{!m3*:%{!m4*:%(link_default_cpu_emul)}}}}\ |
f1a58d92 R |
280 | %(subtarget_link_emul_suffix) \ |
281 | %{mrelax:-relax} %(subtarget_link_spec)" | |
00f8ff66 | 282 | |
73a4d10b R |
283 | #ifndef SH_DIV_STR_FOR_SIZE |
284 | #define SH_DIV_STR_FOR_SIZE "call" | |
285 | #endif | |
286 | ||
f36348b3 OE |
287 | /* SH2A does not support little-endian. Catch such combinations |
288 | taking into account the default configuration. */ | |
289 | #if TARGET_ENDIAN_DEFAULT == MASK_BIG_ENDIAN | |
290 | #define IS_LITTLE_ENDIAN_OPTION "%{ml:" | |
291 | #else | |
292 | #define IS_LITTLE_ENDIAN_OPTION "%{!mb:" | |
293 | #endif | |
294 | ||
295 | #if TARGET_CPU_DEFAULT & MASK_HARD_SH2A | |
296 | #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \ | |
af952763 | 297 | "%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:%eSH2a does not support little-endian}}}}}" |
f36348b3 OE |
298 | #else |
299 | #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \ | |
300 | "%{m2a*:%eSH2a does not support little-endian}}" | |
301 | #endif | |
302 | ||
1e44e857 DJ |
303 | #ifdef FDPIC_DEFAULT |
304 | #define FDPIC_SELF_SPECS "%{!mno-fdpic:-mfdpic}" | |
305 | #else | |
306 | #define FDPIC_SELF_SPECS | |
307 | #endif | |
308 | ||
c11394f8 | 309 | #undef DRIVER_SELF_SPECS |
1e44e857 DJ |
310 | #define DRIVER_SELF_SPECS UNSUPPORTED_SH2A SUBTARGET_DRIVER_SELF_SPECS \ |
311 | FDPIC_SELF_SPECS | |
312 | ||
313 | #undef SUBTARGET_DRIVER_SELF_SPECS | |
314 | #define SUBTARGET_DRIVER_SELF_SPECS | |
bd9a3465 | 315 | |
225e4f43 R |
316 | #define ASSEMBLER_DIALECT assembler_dialect |
317 | ||
318 | extern int assembler_dialect; | |
319 | ||
73a4d10b | 320 | enum sh_divide_strategy_e { |
b368d6b8 | 321 | /* SH1 .. SH4 strategies. Because of the small number of registers |
917f1b7e KH |
322 | available, the compiler uses knowledge of the actual set of registers |
323 | being clobbered by the different functions called. */ | |
b368d6b8 R |
324 | SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */ |
325 | SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */ | |
326 | SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */ | |
327 | SH_DIV_INTRINSIC | |
73a4d10b R |
328 | }; |
329 | ||
330 | extern enum sh_divide_strategy_e sh_div_strategy; | |
331 | ||
332 | #ifndef SH_DIV_STRATEGY_DEFAULT | |
e1fab8ba | 333 | #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL_DIV1 |
73a4d10b R |
334 | #endif |
335 | ||
9bed5535 KK |
336 | #ifdef __cplusplus |
337 | ||
338 | /* Atomic model. */ | |
339 | struct sh_atomic_model | |
340 | { | |
341 | enum enum_type | |
342 | { | |
343 | none = 0, | |
344 | soft_gusa, | |
345 | hard_llcs, | |
346 | soft_tcb, | |
347 | soft_imask, | |
348 | ||
349 | num_models | |
350 | }; | |
351 | ||
352 | /* If strict is set, disallow mixing of different models, as it would | |
353 | happen on SH4A. */ | |
354 | bool strict; | |
355 | enum_type type; | |
356 | ||
357 | /* Name string as it was specified on the command line. */ | |
358 | const char* name; | |
359 | ||
360 | /* Name string as it is used in C/C++ defines. */ | |
361 | const char* cdef_name; | |
362 | ||
363 | /* GBR offset variable for TCB model. */ | |
364 | int tcb_gbr_offset; | |
365 | }; | |
366 | ||
367 | extern const sh_atomic_model& selected_atomic_model (void); | |
368 | ||
369 | /* Shortcuts to check the currently selected atomic model. */ | |
370 | #define TARGET_ATOMIC_ANY \ | |
371 | (selected_atomic_model ().type != sh_atomic_model::none) | |
372 | ||
373 | #define TARGET_ATOMIC_STRICT \ | |
374 | (selected_atomic_model ().strict) | |
375 | ||
376 | #define TARGET_ATOMIC_SOFT_GUSA \ | |
377 | (selected_atomic_model ().type == sh_atomic_model::soft_gusa) | |
378 | ||
379 | #define TARGET_ATOMIC_HARD_LLCS \ | |
380 | (selected_atomic_model ().type == sh_atomic_model::hard_llcs) | |
381 | ||
382 | #define TARGET_ATOMIC_SOFT_TCB \ | |
383 | (selected_atomic_model ().type == sh_atomic_model::soft_tcb) | |
384 | ||
385 | #define TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX \ | |
386 | GEN_INT (selected_atomic_model ().tcb_gbr_offset) | |
387 | ||
388 | #define TARGET_ATOMIC_SOFT_IMASK \ | |
389 | (selected_atomic_model ().type == sh_atomic_model::soft_imask) | |
390 | ||
391 | #endif // __cplusplus | |
392 | ||
f5c7290e RS |
393 | #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 |
394 | ||
bc45ade3 | 395 | \f |
c5d67833 | 396 | /* Target machine storage layout. */ |
bc45ade3 | 397 | |
277772f6 OE |
398 | #define TARGET_BIG_ENDIAN (!TARGET_LITTLE_ENDIAN) |
399 | ||
400 | #define SH_REG_MSW_OFFSET (TARGET_LITTLE_ENDIAN ? 1 : 0) | |
401 | #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) | |
402 | ||
bc45ade3 SC |
403 | /* Define this if most significant bit is lowest numbered |
404 | in instructions that operate on numbered bit-fields. */ | |
405 | #define BITS_BIG_ENDIAN 0 | |
406 | ||
407 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
277772f6 | 408 | #define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN |
bc45ade3 SC |
409 | |
410 | /* Define this if most significant word of a multiword number is the lowest | |
411 | numbered. */ | |
277772f6 | 412 | #define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN |
00f8ff66 | 413 | |
fa5322fa AO |
414 | #define MAX_BITS_PER_WORD 64 |
415 | ||
fa5322fa | 416 | /* Width in bits of an `int'. We want just 32-bits, even if words are |
24746a42 | 417 | longer. */ |
fa5322fa AO |
418 | #define INT_TYPE_SIZE 32 |
419 | ||
420 | /* Width in bits of a `long'. */ | |
e1fab8ba | 421 | #define LONG_TYPE_SIZE (32) |
fa5322fa AO |
422 | |
423 | /* Width in bits of a `long long'. */ | |
424 | #define LONG_LONG_TYPE_SIZE 64 | |
425 | ||
426 | /* Width in bits of a `long double'. */ | |
427 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
bc45ade3 SC |
428 | |
429 | /* Width of a word, in units (bytes). */ | |
e1fab8ba | 430 | #define UNITS_PER_WORD (4) |
fa5322fa | 431 | #define MIN_UNITS_PER_WORD 4 |
bc45ade3 | 432 | |
fada1961 | 433 | /* Scaling factor for Dwarf data offsets for CFI information. |
af952763 | 434 | The dwarf2out.c default would use -UNITS_PER_WORD. */ |
fada1961 R |
435 | #define DWARF_CIE_DATA_ALIGNMENT -4 |
436 | ||
bc45ade3 SC |
437 | /* Width in bits of a pointer. |
438 | See also the macro `Pmode' defined below. */ | |
e1fab8ba | 439 | #define POINTER_SIZE (32) |
bc45ade3 SC |
440 | |
441 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
e1fab8ba | 442 | #define PARM_BOUNDARY (32) |
bc45ade3 SC |
443 | |
444 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
3d5a0820 | 445 | #define STACK_BOUNDARY BIGGEST_ALIGNMENT |
bc45ade3 | 446 | |
e9a25f70 | 447 | /* The log (base 2) of the cache line size, in bytes. Processors prior to |
b4d34be1 R |
448 | SH2 have no actual cache, but they fetch code in chunks of 4 bytes. |
449 | The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */ | |
e1fab8ba | 450 | #define CACHE_LOG (TARGET_HARD_SH4 ? 5 : TARGET_SH2 ? 4 : 2) |
e9a25f70 | 451 | |
58ab7171 R |
452 | /* ABI given & required minimum allocation boundary (in *bits*) for the |
453 | code of a function. */ | |
e1fab8ba | 454 | #define FUNCTION_BOUNDARY (16) |
fa5322fa | 455 | |
bc45ade3 SC |
456 | /* Alignment of field after `int : 0' in a structure. */ |
457 | #define EMPTY_FIELD_BOUNDARY 32 | |
458 | ||
459 | /* No data type wants to be aligned rounder than this. */ | |
460 | #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) | |
461 | ||
462 | /* The best alignment to use in cases where we have a choice. */ | |
e1fab8ba | 463 | #define FASTEST_ALIGNMENT (32) |
bc45ade3 | 464 | |
bc45ade3 | 465 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
c5d67833 | 466 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
bc45ade3 SC |
467 | ((TREE_CODE (EXP) == STRING_CST \ |
468 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
0d7e008e | 469 | ? FASTEST_ALIGNMENT : (ALIGN)) |
bc45ade3 | 470 | |
1bf93c14 R |
471 | /* get_mode_alignment assumes complex values are always held in multiple |
472 | registers, but that is not the case on the SH; CQImode and CHImode are | |
af952763 | 473 | held in a single integer register. */ |
1bf93c14 R |
474 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ |
475 | ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \ | |
476 | || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \ | |
fada1961 | 477 | ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \ |
78d310c2 | 478 | : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN)) |
1bf93c14 | 479 | |
bc45ade3 SC |
480 | /* Make arrays of chars word-aligned for the same reasons. */ |
481 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
482 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
483 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
484 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
485 | ||
8e87e161 SC |
486 | /* Number of bits which any structure or union's size must be a |
487 | multiple of. Each structure or union's size is rounded up to a | |
994295f2 | 488 | multiple of this. */ |
9791111f | 489 | #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8) |
8e87e161 | 490 | |
bc45ade3 SC |
491 | /* Set this nonzero if move instructions will actually fail to work |
492 | when given unaligned data. */ | |
493 | #define STRICT_ALIGNMENT 1 | |
33f7f353 JR |
494 | |
495 | /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */ | |
496 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \ | |
497 | barrier_align (LABEL_AFTER_BARRIER) | |
498 | ||
b6a0df6c | 499 | #define LOOP_ALIGN(A_LABEL) sh_loop_align (A_LABEL) |
33f7f353 JR |
500 | |
501 | #define LABEL_ALIGN(A_LABEL) \ | |
502 | ( \ | |
503 | (PREV_INSN (A_LABEL) \ | |
f3536097 | 504 | && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \ |
33f7f353 | 505 | && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \ |
f6f1dc95 | 506 | && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \ |
6f317ef3 | 507 | /* explicit alignment insn in constant tables. */ \ |
33f7f353 JR |
508 | ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \ |
509 | : 0) | |
510 | ||
511 | /* Jump tables must be 32 bit aligned, no matter the size of the element. */ | |
512 | #define ADDR_VEC_ALIGN(ADDR_VEC) 2 | |
513 | ||
514 | /* The base two logarithm of the known minimum alignment of an insn length. */ | |
e1fab8ba OE |
515 | #define INSN_LENGTH_ALIGNMENT(A_INSN) \ |
516 | (NONJUMP_INSN_P (A_INSN) \ | |
517 | ? 1 \ | |
518 | : JUMP_P (A_INSN) || CALL_P (A_INSN) \ | |
519 | ? 1 \ | |
33f7f353 | 520 | : CACHE_LOG) |
bc45ade3 SC |
521 | \f |
522 | /* Standard register usage. */ | |
523 | ||
c8f0269d | 524 | /* Register allocation for the Renesas calling convention: |
bc45ade3 | 525 | |
50fe8924 OE |
526 | r0 arg return |
527 | r1..r3 scratch | |
c5d67833 | 528 | r4..r7 args in |
0d7e008e SC |
529 | r8..r13 call saved |
530 | r14 frame pointer/call saved | |
bc45ade3 SC |
531 | r15 stack pointer |
532 | ap arg pointer (doesn't really exist, always eliminated) | |
533 | pr subroutine return address | |
50fe8924 | 534 | t t bit |
994295f2 | 535 | mach multiply/accumulate result, high part |
5c3ea805 JW |
536 | macl multiply/accumulate result, low part. |
537 | fpul fp/int communication register | |
d1405d89 | 538 | rap return address pointer register |
5c3ea805 JW |
539 | fr0 fp arg return |
540 | fr1..fr3 scratch floating point registers | |
541 | fr4..fr11 fp args in | |
542 | fr12..fr15 call saved floating point registers */ | |
bc45ade3 | 543 | |
3a2317d1 | 544 | #define MAX_REGISTER_NAME_LENGTH 6 |
fa5322fa AO |
545 | extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1]; |
546 | ||
547 | #define SH_REGISTER_NAMES_INITIALIZER \ | |
50fe8924 | 548 | { \ |
fa5322fa AO |
549 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ |
550 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
551 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ | |
552 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ | |
553 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ | |
554 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \ | |
555 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ | |
556 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \ | |
557 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \ | |
558 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \ | |
559 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \ | |
560 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \ | |
561 | "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \ | |
562 | "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \ | |
563 | "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \ | |
564 | "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \ | |
565 | "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \ | |
566 | "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \ | |
567 | "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \ | |
3a2317d1 | 568 | "rap", "sfp", "fpscr0", "fpscr1" \ |
fa5322fa AO |
569 | } |
570 | ||
fa5322fa AO |
571 | #define REGNAMES_ARR_INDEX_1(index) \ |
572 | (sh_register_names[index]) | |
573 | #define REGNAMES_ARR_INDEX_2(index) \ | |
574 | REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1) | |
575 | #define REGNAMES_ARR_INDEX_4(index) \ | |
576 | REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2) | |
577 | #define REGNAMES_ARR_INDEX_8(index) \ | |
578 | REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4) | |
579 | #define REGNAMES_ARR_INDEX_16(index) \ | |
580 | REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8) | |
581 | #define REGNAMES_ARR_INDEX_32(index) \ | |
582 | REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16) | |
583 | #define REGNAMES_ARR_INDEX_64(index) \ | |
584 | REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32) | |
585 | ||
586 | #define REGISTER_NAMES \ | |
587 | { \ | |
588 | REGNAMES_ARR_INDEX_64 (0), \ | |
589 | REGNAMES_ARR_INDEX_64 (64), \ | |
590 | REGNAMES_ARR_INDEX_8 (128), \ | |
591 | REGNAMES_ARR_INDEX_8 (136), \ | |
592 | REGNAMES_ARR_INDEX_8 (144), \ | |
3a2317d1 | 593 | REGNAMES_ARR_INDEX_4 (152) \ |
fa5322fa AO |
594 | } |
595 | ||
596 | #define ADDREGNAMES_SIZE 32 | |
597 | #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4 | |
598 | extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ | |
599 | [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]; | |
600 | ||
601 | #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \ | |
602 | { \ | |
603 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \ | |
604 | "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \ | |
605 | "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \ | |
606 | "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \ | |
607 | } | |
608 | ||
609 | #define ADDREGNAMES_REGNO(index) \ | |
610 | ((index < 32) ? (FIRST_FP_REG + (index) * 2) \ | |
611 | : (-1)) | |
612 | ||
613 | #define ADDREGNAMES_ARR_INDEX_1(index) \ | |
614 | { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) } | |
615 | #define ADDREGNAMES_ARR_INDEX_2(index) \ | |
616 | ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1) | |
617 | #define ADDREGNAMES_ARR_INDEX_4(index) \ | |
618 | ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2) | |
619 | #define ADDREGNAMES_ARR_INDEX_8(index) \ | |
620 | ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4) | |
621 | #define ADDREGNAMES_ARR_INDEX_16(index) \ | |
622 | ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8) | |
623 | #define ADDREGNAMES_ARR_INDEX_32(index) \ | |
624 | ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16) | |
625 | ||
626 | #define ADDITIONAL_REGISTER_NAMES \ | |
627 | { \ | |
628 | ADDREGNAMES_ARR_INDEX_32 (0) \ | |
629 | } | |
630 | ||
bc45ade3 SC |
631 | /* Number of actual hardware registers. |
632 | The hardware registers are assigned numbers for the compiler | |
633 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
634 | All registers that the compiler knows about must be given numbers, | |
994295f2 | 635 | even those that are not normally considered general registers. */ |
bc45ade3 | 636 | |
4773afa4 AO |
637 | /* There are many other relevant definitions in sh.md's md_constants. */ |
638 | ||
639 | #define FIRST_GENERAL_REG R0_REG | |
e1fab8ba | 640 | #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (15)) |
4773afa4 | 641 | #define FIRST_FP_REG DR0_REG |
e1fab8ba | 642 | #define LAST_FP_REG (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)) |
4773afa4 | 643 | #define FIRST_XD_REG XD0_REG |
fa5322fa | 644 | #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1)) |
4773afa4 | 645 | |
5c7cafa8 | 646 | /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */ |
5c7cafa8 CB |
647 | #define FIRST_BANKED_REG R0_REG |
648 | #define LAST_BANKED_REG R7_REG | |
649 | ||
50fe8924 OE |
650 | #define BANKED_REGISTER_P(REGNO) \ |
651 | IN_RANGE ((REGNO), \ | |
5c7cafa8 CB |
652 | (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \ |
653 | (unsigned HOST_WIDE_INT) LAST_BANKED_REG) | |
654 | ||
104ee20b | 655 | #define GENERAL_REGISTER_P(REGNO) \ |
fada1961 R |
656 | IN_RANGE ((REGNO), \ |
657 | (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ | |
658 | (unsigned HOST_WIDE_INT) LAST_GENERAL_REG) | |
104ee20b AO |
659 | |
660 | #define GENERAL_OR_AP_REGISTER_P(REGNO) \ | |
50fe8924 | 661 | (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \ |
96a2347e | 662 | || ((REGNO) == FRAME_POINTER_REGNUM)) |
104ee20b AO |
663 | |
664 | #define FP_REGISTER_P(REGNO) \ | |
fada1961 | 665 | ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG) |
104ee20b AO |
666 | |
667 | #define XD_REGISTER_P(REGNO) \ | |
fada1961 | 668 | ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG) |
104ee20b AO |
669 | |
670 | #define FP_OR_XD_REGISTER_P(REGNO) \ | |
671 | (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO)) | |
672 | ||
673 | #define FP_ANY_REGISTER_P(REGNO) \ | |
674 | (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG) | |
675 | ||
676 | #define SPECIAL_REGISTER_P(REGNO) \ | |
4773afa4 | 677 | ((REGNO) == GBR_REG || (REGNO) == T_REG \ |
3a2317d1 OE |
678 | || (REGNO) == MACH_REG || (REGNO) == MACL_REG \ |
679 | || (REGNO) == FPSCR_MODES_REG || (REGNO) == FPSCR_STAT_REG) | |
bc45ade3 | 680 | |
fa5322fa | 681 | #define VALID_REGISTER_P(REGNO) \ |
e1fab8ba OE |
682 | (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \ |
683 | || XD_REGISTER_P (REGNO) \ | |
fa5322fa | 684 | || (REGNO) == AP_REG || (REGNO) == RAP_REG \ |
96a2347e | 685 | || (REGNO) == FRAME_POINTER_REGNUM \ |
f1bebab6 | 686 | || ((SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \ |
3a8699c7 | 687 | || (TARGET_SH2E && (REGNO) == FPUL_REG)) |
fa5322fa AO |
688 | |
689 | /* The mode that should be generally used to store a register by | |
690 | itself in the stack, or to load it back. */ | |
691 | #define REGISTER_NATURAL_MODE(REGNO) \ | |
0d4a1197 RS |
692 | (FP_REGISTER_P (REGNO) ? E_SFmode \ |
693 | : XD_REGISTER_P (REGNO) ? E_DFmode : E_SImode) | |
e1fab8ba | 694 | |
fa5322fa | 695 | |
3a2317d1 | 696 | #define FIRST_PSEUDO_REGISTER 156 |
96a2347e KK |
697 | |
698 | /* Don't count soft frame pointer. */ | |
3a2317d1 | 699 | #define DWARF_FRAME_REGISTERS (153) |
bc45ade3 SC |
700 | |
701 | /* 1 for registers that have pervasive standard uses | |
994295f2 | 702 | and are not available for the register allocator. |
d3ae8277 | 703 | |
97b65a3e JW |
704 | Mach register is fixed 'cause it's only 10 bits wide for SH1. |
705 | It is 32 bits wide for SH2. */ | |
50fe8924 OE |
706 | #define FIXED_REGISTERS \ |
707 | { \ | |
fa5322fa AO |
708 | /* Regular registers. */ \ |
709 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
710 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
711 | /* r16 is reserved, r18 is the former pr. */ \ | |
712 | 1, 0, 0, 0, 0, 0, 0, 0, \ | |
713 | /* r24 is reserved for the OS; r25, for the assembler or linker. */ \ | |
714 | /* r26 is a global variable data pointer; r27 is for constants. */ \ | |
715 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
716 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
717 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
718 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
719 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
720 | /* FP registers. */ \ | |
721 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
722 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
723 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
724 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
725 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
726 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
727 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
728 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
729 | /* Branch target registers. */ \ | |
730 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
731 | /* XD registers. */ \ | |
732 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
733 | /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ | |
734 | 1, 1, 1, 1, 1, 1, 0, 1, \ | |
3a2317d1 OE |
735 | /*"rap", "sfp","fpscr0","fpscr1" */ \ |
736 | 1, 1, 1, 1, \ | |
5c3ea805 | 737 | } |
bc45ade3 SC |
738 | |
739 | /* 1 for registers not available across function calls. | |
740 | These must include the FIXED_REGISTERS and also any | |
741 | registers that can be used without being saved. | |
742 | The latter must include the registers where values are returned | |
743 | and the register where structure-value addresses are passed. | |
744 | Aside from that, you can include as many other registers as you like. */ | |
50fe8924 OE |
745 | #define CALL_USED_REGISTERS \ |
746 | { \ | |
fa5322fa AO |
747 | /* Regular registers. */ \ |
748 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
749 | /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \ | |
750 | Only the lower 32bits of R10-R14 are guaranteed to be preserved \ | |
751 | across SH5 function calls. */ \ | |
752 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
97b3d0f0 | 753 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
fa5322fa AO |
754 | 1, 1, 1, 1, 0, 0, 0, 0, \ |
755 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
756 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
757 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
758 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
759 | /* FP registers. */ \ | |
760 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
761 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
762 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
763 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
764 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
765 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
766 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
767 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
768 | /* Branch target registers. */ \ | |
769 | 1, 1, 1, 1, 1, 0, 0, 0, \ | |
770 | /* XD registers. */ \ | |
771 | 1, 1, 1, 1, 1, 1, 0, 0, \ | |
772 | /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ | |
97b3d0f0 | 773 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
3a2317d1 OE |
774 | /*"rap", "sfp","fpscr0","fpscr1" */ \ |
775 | 1, 1, 1, 1, \ | |
5c3ea805 | 776 | } |
bc45ade3 | 777 | |
b7359edc OE |
778 | /* CALL_REALLY_USED_REGISTERS is used as a default setting, which is then |
779 | overridden by -fcall-saved-* and -fcall-used-* options and then by | |
780 | TARGET_CONDITIONAL_REGISTER_USAGE. There we might want to make a | |
781 | register call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */ | |
782 | #define CALL_REALLY_USED_REGISTERS \ | |
783 | { \ | |
784 | /* Regular registers. */ \ | |
785 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
786 | /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \ | |
787 | Only the lower 32bits of R10-R14 are guaranteed to be preserved \ | |
788 | across SH5 function calls. */ \ | |
789 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
790 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
791 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
792 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
793 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
794 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
795 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
796 | /* FP registers. */ \ | |
797 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
798 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
799 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
800 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
801 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
802 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
803 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
804 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
805 | /* Branch target registers. */ \ | |
806 | 1, 1, 1, 1, 1, 0, 0, 0, \ | |
807 | /* XD registers. */ \ | |
808 | 1, 1, 1, 1, 1, 1, 0, 0, \ | |
809 | /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ | |
810 | 0, 1, 1, 1, 1, 1, 1, 1, \ | |
811 | /*"rap", "sfp","fpscr0","fpscr1" */ \ | |
812 | 1, 1, 0, 0, \ | |
813 | } | |
62164eb4 | 814 | |
fc1fcfa0 KK |
815 | /* Specify the modes required to caller save a given hard regno. */ |
816 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
817 | sh_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) | |
818 | ||
03b8ec29 DD |
819 | /* A C expression that is nonzero if hard register NEW_REG can be |
820 | considered for use as a rename register for OLD_REG register */ | |
03b8ec29 DD |
821 | #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ |
822 | sh_hard_regno_rename_ok (OLD_REG, NEW_REG) | |
823 | ||
bc45ade3 SC |
824 | /* Specify the registers used for certain standard purposes. |
825 | The values of these macros are register numbers. */ | |
826 | ||
827 | /* Define this if the program counter is overloaded on a register. */ | |
828 | /* #define PC_REGNUM 15*/ | |
829 | ||
830 | /* Register to use for pushing function arguments. */ | |
4773afa4 | 831 | #define STACK_POINTER_REGNUM SP_REG |
bc45ade3 SC |
832 | |
833 | /* Base register for access to local variables of the function. */ | |
96a2347e KK |
834 | #define HARD_FRAME_POINTER_REGNUM FP_REG |
835 | ||
836 | /* Base register for access to local variables of the function. */ | |
837 | #define FRAME_POINTER_REGNUM 153 | |
bc45ade3 | 838 | |
d1405d89 JW |
839 | /* Fake register that holds the address on the stack of the |
840 | current function's return address. */ | |
4773afa4 | 841 | #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG |
d1405d89 | 842 | |
1a66cd67 AO |
843 | /* Register to hold the addressing base for position independent |
844 | code access to data items. */ | |
309d8365 | 845 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM) |
1a66cd67 | 846 | |
1e44e857 DJ |
847 | /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT |
848 | entries would need to handle saving and restoring it). */ | |
849 | #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC | |
850 | ||
1a66cd67 AO |
851 | #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_" |
852 | ||
bc45ade3 SC |
853 | /* Definitions for register eliminations. |
854 | ||
cc27ef74 | 855 | We have three registers that can be eliminated on the SH. First, the |
bc45ade3 SC |
856 | frame pointer register can often be eliminated in favor of the stack |
857 | pointer register. Secondly, the argument pointer register can always be | |
cc27ef74 | 858 | eliminated; it is replaced with either the stack or frame pointer. |
956d6950 | 859 | Third, there is the return address pointer, which can also be replaced |
50fe8924 | 860 | with either the stack or the frame pointer. |
bc45ade3 | 861 | |
50fe8924 | 862 | This is an array of structures. Each structure initializes one pair |
bc45ade3 SC |
863 | of eliminable registers. The "from" register number is given first, |
864 | followed by "to". Eliminations of the same "from" register are listed | |
50fe8924 | 865 | in order of preference. |
bc45ade3 | 866 | |
50fe8924 | 867 | If you add any registers here that are not actually hard registers, |
cc27ef74 JR |
868 | and that have any alternative of elimination that doesn't always |
869 | apply, you need to amend calc_live_regs to exclude it, because | |
870 | reload spills all eliminable registers where it sees an | |
871 | can_eliminate == 0 entry, thus making them 'live' . | |
872 | If you add any hard registers that can be eliminated in different | |
873 | ways, you have to patch reload to spill them only when all alternatives | |
874 | of elimination fail. */ | |
d1405d89 | 875 | #define ELIMINABLE_REGS \ |
96a2347e KK |
876 | {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
877 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
878 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
d1405d89 | 879 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
96a2347e | 880 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ |
d1405d89 | 881 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
96a2347e | 882 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},} |
bc45ade3 | 883 | |
bc45ade3 SC |
884 | /* Define the offset between two registers, one to be eliminated, and the other |
885 | its replacement, at the start of a routine. */ | |
bc45ade3 | 886 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
e9a25f70 | 887 | OFFSET = initial_elimination_offset ((FROM), (TO)) |
bc45ade3 SC |
888 | |
889 | /* Base register for access to arguments of the function. */ | |
f00018dd | 890 | #define ARG_POINTER_REGNUM AP_REG |
bc45ade3 SC |
891 | |
892 | /* Register in which the static-chain is passed to a function. */ | |
e1fab8ba | 893 | #define STATIC_CHAIN_REGNUM (3) |
bc45ade3 | 894 | |
0d7e008e | 895 | /* Don't default to pcc-struct-return, because we have already specified |
bd5bd7ac KH |
896 | exactly how to return structures in the TARGET_RETURN_IN_MEMORY |
897 | target hook. */ | |
0d7e008e | 898 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
fa5322fa | 899 | |
bc45ade3 SC |
900 | \f |
901 | /* Define the classes of registers for register constraints in the | |
902 | machine description. Also define ranges of constants. | |
903 | ||
904 | One of the classes must always be named ALL_REGS and include all hard regs. | |
905 | If there is more than one class, another class must be named NO_REGS | |
906 | and contain no registers. | |
907 | ||
908 | The name GENERAL_REGS must be the name of a class (or an alias for | |
909 | another name such as ALL_REGS). This is the class of registers | |
910 | that is allowed by "g" or "r" in a register constraint. | |
911 | Also, registers outside this class are allocated only when | |
912 | instructions express preferences for them. | |
913 | ||
914 | The classes must be numbered in nondecreasing order; that is, | |
915 | a larger-numbered class must never be contained completely | |
916 | in a smaller-numbered class. | |
917 | ||
918 | For any two classes, it is very desirable that there be another | |
50fe8924 | 919 | class that represents their union. |
bc45ade3 | 920 | |
50fe8924 | 921 | The SH has two sorts of general registers, R0 and the rest. R0 can |
bc45ade3 SC |
922 | be used as the destination of some of the arithmetic ops. There are |
923 | also some special purpose registers; the T bit register, the | |
50fe8924 OE |
924 | Procedure Return Register and the Multiply Accumulate Registers. |
925 | ||
926 | Place GENERAL_REGS after FPUL_REGS so that it will be preferred by | |
e9a25f70 JL |
927 | reg_class_subunion. We don't want to have an actual union class |
928 | of these, because it would only be used when both classes are calculated | |
929 | to give the same cost, but there is only one FPUL register. | |
930 | Besides, regclass fails to notice the different REGISTER_MOVE_COSTS | |
931 | applying to the actual instruction alternative considered. E.g., the | |
932 | y/r alternative of movsi_ie is considered to have no more cost that | |
933 | the r/r alternative, which is patently untrue. */ | |
bc45ade3 SC |
934 | enum reg_class |
935 | { | |
936 | NO_REGS, | |
937 | R0_REGS, | |
bc45ade3 SC |
938 | PR_REGS, |
939 | T_REGS, | |
940 | MAC_REGS, | |
5c3ea805 | 941 | FPUL_REGS, |
cb51ecd2 | 942 | SIBCALL_REGS, |
a4f71b01 | 943 | NON_SP_REGS, |
e9a25f70 | 944 | GENERAL_REGS, |
5c3ea805 JW |
945 | FP0_REGS, |
946 | FP_REGS, | |
225e4f43 R |
947 | DF_REGS, |
948 | FPSCR_REGS, | |
5c5eb4ef | 949 | GENERAL_FP_REGS, |
cd41bae5 | 950 | GENERAL_DF_REGS, |
fa5322fa | 951 | TARGET_REGS, |
bc45ade3 SC |
952 | ALL_REGS, |
953 | LIM_REG_CLASSES | |
954 | }; | |
955 | ||
956 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
957 | ||
994295f2 | 958 | /* Give names of register classes as strings for dump file. */ |
c5d67833 | 959 | #define REG_CLASS_NAMES \ |
bc45ade3 SC |
960 | { \ |
961 | "NO_REGS", \ | |
962 | "R0_REGS", \ | |
bc45ade3 SC |
963 | "PR_REGS", \ |
964 | "T_REGS", \ | |
965 | "MAC_REGS", \ | |
5c3ea805 | 966 | "FPUL_REGS", \ |
cb51ecd2 | 967 | "SIBCALL_REGS", \ |
a4f71b01 | 968 | "NON_SP_REGS", \ |
e9a25f70 | 969 | "GENERAL_REGS", \ |
5c3ea805 JW |
970 | "FP0_REGS", \ |
971 | "FP_REGS", \ | |
225e4f43 R |
972 | "DF_REGS", \ |
973 | "FPSCR_REGS", \ | |
5c5eb4ef | 974 | "GENERAL_FP_REGS", \ |
cd41bae5 | 975 | "GENERAL_DF_REGS", \ |
fa5322fa | 976 | "TARGET_REGS", \ |
bc45ade3 SC |
977 | "ALL_REGS", \ |
978 | } | |
979 | ||
980 | /* Define which registers fit in which classes. | |
981 | This is an initializer for a vector of HARD_REG_SET | |
982 | of length N_REG_CLASSES. */ | |
fa5322fa AO |
983 | #define REG_CLASS_CONTENTS \ |
984 | { \ | |
985 | /* NO_REGS: */ \ | |
986 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ | |
987 | /* R0_REGS: */ \ | |
988 | { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ | |
989 | /* PR_REGS: */ \ | |
990 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \ | |
991 | /* T_REGS: */ \ | |
992 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \ | |
993 | /* MAC_REGS: */ \ | |
994 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \ | |
995 | /* FPUL_REGS: */ \ | |
d4d46566 | 996 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \ |
5efd84c5 | 997 | /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \ |
fa5322fa | 998 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ |
a4f71b01 JM |
999 | /* NON_SP_REGS: */ \ |
1000 | { 0xffff7fff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ | |
fa5322fa | 1001 | /* GENERAL_REGS: */ \ |
96a2347e | 1002 | { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ |
fa5322fa AO |
1003 | /* FP0_REGS: */ \ |
1004 | { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \ | |
1005 | /* FP_REGS: */ \ | |
1006 | { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ | |
1007 | /* DF_REGS: */ \ | |
1008 | { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ | |
1009 | /* FPSCR_REGS: */ \ | |
1010 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \ | |
1011 | /* GENERAL_FP_REGS: */ \ | |
cd41bae5 R |
1012 | { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \ |
1013 | /* GENERAL_DF_REGS: */ \ | |
1014 | { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \ | |
fa5322fa AO |
1015 | /* TARGET_REGS: */ \ |
1016 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \ | |
1017 | /* ALL_REGS: */ \ | |
3a2317d1 | 1018 | { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0fffffff }, \ |
73774972 | 1019 | } |
bc45ade3 SC |
1020 | |
1021 | /* The same information, inverted: | |
1022 | Return the class number of the smallest class containing | |
1023 | reg number REGNO. This could be a conditional expression | |
1024 | or could index an array. */ | |
fada1961 | 1025 | extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; |
e9a25f70 | 1026 | #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)] |
bc45ade3 | 1027 | |
42db504c SB |
1028 | /* When this hook returns true for MODE, the compiler allows |
1029 | registers explicitly used in the rtl to be used as spill registers | |
1030 | but prevents the compiler from extending the lifetime of these | |
1031 | registers. */ | |
1032 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ | |
1033 | sh_small_register_classes_for_mode_p | |
0d7e008e | 1034 | |
bc45ade3 | 1035 | /* The order in which register should be allocated. */ |
e9a25f70 JL |
1036 | /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo, |
1037 | and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be | |
1038 | spilled or used otherwise, we better have the FP_REGS allocated first. */ | |
c5d67833 | 1039 | #define REG_ALLOC_ORDER \ |
1bf93c14 R |
1040 | {/* Caller-saved FPRs */ \ |
1041 | 65, 66, 67, 68, 69, 70, 71, 64, \ | |
1042 | 72, 73, 74, 75, 80, 81, 82, 83, \ | |
1043 | 84, 85, 86, 87, 88, 89, 90, 91, \ | |
1044 | 92, 93, 94, 95, 96, 97, 98, 99, \ | |
1045 | /* Callee-saved FPRs */ \ | |
1046 | 76, 77, 78, 79,100,101,102,103, \ | |
fa5322fa AO |
1047 | 104,105,106,107,108,109,110,111, \ |
1048 | 112,113,114,115,116,117,118,119, \ | |
1049 | 120,121,122,123,124,125,126,127, \ | |
1bf93c14 R |
1050 | 136,137,138,139,140,141,142,143, \ |
1051 | /* FPSCR */ 151, \ | |
1052 | /* Caller-saved GPRs (except 8/9 on SH1-4) */ \ | |
1053 | 1, 2, 3, 7, 6, 5, 4, 0, \ | |
1054 | 8, 9, 17, 19, 20, 21, 22, 23, \ | |
1055 | 36, 37, 38, 39, 40, 41, 42, 43, \ | |
1056 | 60, 61, 62, \ | |
1057 | /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \ | |
1058 | 10, 11, 12, 13, 14, 18, \ | |
1059 | /* SH5 callee-saved GPRs */ \ | |
1060 | 28, 29, 30, 31, 32, 33, 34, 35, \ | |
1061 | 44, 45, 46, 47, 48, 49, 50, 51, \ | |
1062 | 52, 53, 54, 55, 56, 57, 58, 59, \ | |
1063 | /* FPUL */ 150, \ | |
1bf93c14 R |
1064 | /* Fixed registers */ \ |
1065 | 15, 16, 24, 25, 26, 27, 63,144, \ | |
3a2317d1 | 1066 | 145,146,147,148,149,152,153,154,155 } |
bc45ade3 SC |
1067 | |
1068 | /* The class value for index registers, and the one for base regs. */ | |
e1fab8ba OE |
1069 | #define INDEX_REG_CLASS R0_REGS |
1070 | #define BASE_REG_CLASS GENERAL_REGS | |
c5d67833 | 1071 | \f |
32a7ab3d | 1072 | /* Defines for sh.md and constraints.md. */ |
bc45ade3 | 1073 | |
735cb76e R |
1074 | #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \ |
1075 | && ((HOST_WIDE_INT)(VALUE)) <= 127) | |
735cb76e R |
1076 | |
1077 | #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \ | |
1078 | && ((HOST_WIDE_INT)(VALUE)) <= 255) | |
5c3ea805 | 1079 | |
6ff9d294 OE |
1080 | #define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\ |
1081 | (((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX)) | |
1082 | ||
bc45ade3 | 1083 | /* Return the maximum number of consecutive registers |
994295f2 | 1084 | needed to represent mode MODE in a register of class CLASS. |
bc45ade3 | 1085 | |
3620944c RS |
1086 | If TARGET_SHMEDIA, we need two FP registers per word. |
1087 | Otherwise we will need at most one register per word. */ | |
c5d67833 | 1088 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
e1fab8ba | 1089 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
225e4f43 R |
1090 | |
1091 | /* If defined, gives a class of registers that cannot be used as the | |
50fe8924 OE |
1092 | operand of a SUBREG that changes the mode of the object illegally. |
1093 | ??? We need to renumber the internal numbers for the frnn registers | |
0ac78517 | 1094 | when in little endian in order to allow mode size changes. */ |
50fe8924 | 1095 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
b0c42aed | 1096 | sh_cannot_change_mode_class (FROM, TO, CLASS) |
bc45ade3 SC |
1097 | \f |
1098 | /* Stack layout; function entry, exit and calling. */ | |
1099 | ||
c5d67833 | 1100 | /* Define the number of registers that can hold parameters. |
5c3ea805 | 1101 | These macros are used only in other macro definitions below. */ |
5c3ea805 | 1102 | #define NPARM_REGS(MODE) \ |
fa5322fa | 1103 | (TARGET_FPU_ANY && (MODE) == SFmode \ |
e1fab8ba | 1104 | ? 8 \ |
d5dd0a62 | 1105 | : TARGET_FPU_DOUBLE \ |
50fe8924 OE |
1106 | && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
1107 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ | |
e1fab8ba OE |
1108 | ? 8 \ |
1109 | : 4) | |
5c3ea805 | 1110 | |
e1fab8ba OE |
1111 | #define FIRST_PARM_REG (FIRST_GENERAL_REG + 4) |
1112 | #define FIRST_RET_REG (FIRST_GENERAL_REG + 0) | |
bc45ade3 | 1113 | |
e1fab8ba | 1114 | #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4) |
5c3ea805 JW |
1115 | #define FIRST_FP_RET_REG FIRST_FP_REG |
1116 | ||
bc45ade3 SC |
1117 | /* Define this if pushing a word on the stack |
1118 | makes the stack pointer a smaller address. */ | |
62f9f30b | 1119 | #define STACK_GROWS_DOWNWARD 1 |
bc45ade3 | 1120 | |
a4d05547 | 1121 | /* Define this macro to nonzero if the addresses of local variable slots |
96a2347e KK |
1122 | are at negative offsets from the frame pointer. */ |
1123 | #define FRAME_GROWS_DOWNWARD 1 | |
0d7e008e SC |
1124 | |
1125 | /* Offset from the frame pointer to the first local variable slot to | |
994295f2 | 1126 | be allocated. */ |
bc45ade3 SC |
1127 | #define STARTING_FRAME_OFFSET 0 |
1128 | ||
1129 | /* If we generate an insn to push BYTES bytes, | |
1130 | this says how many the stack pointer really advances by. */ | |
e9a25f70 JL |
1131 | /* Don't define PUSH_ROUNDING, since the hardware doesn't do this. |
1132 | When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to | |
1133 | do correct alignment. */ | |
1134 | #if 0 | |
bc45ade3 | 1135 | #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) |
e9a25f70 | 1136 | #endif |
bc45ade3 SC |
1137 | |
1138 | /* Offset of first parameter from the argument pointer register value. */ | |
1139 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1140 | ||
fa5322fa AO |
1141 | /* Value is the number of bytes of arguments automatically popped when |
1142 | calling a subroutine. | |
e1fab8ba OE |
1143 | CUM is the accumulated argument list. */ |
1144 | #define CALL_POPS_ARGS(CUM) (0) | |
fa5322fa | 1145 | |
6f317ef3 | 1146 | /* Some subroutine macros specific to this machine. */ |
5c3ea805 JW |
1147 | |
1148 | #define BASE_RETURN_VALUE_REG(MODE) \ | |
50fe8924 | 1149 | ((TARGET_FPU_ANY && ((MODE) == SFmode)) \ |
5c3ea805 | 1150 | ? FIRST_FP_RET_REG \ |
50fe8924 | 1151 | : TARGET_FPU_ANY && (MODE) == SCmode \ |
225e4f43 | 1152 | ? FIRST_FP_RET_REG \ |
fa5322fa | 1153 | : (TARGET_FPU_DOUBLE \ |
225e4f43 R |
1154 | && ((MODE) == DFmode || (MODE) == SFmode \ |
1155 | || (MODE) == DCmode || (MODE) == SCmode )) \ | |
1156 | ? FIRST_FP_RET_REG \ | |
5c3ea805 JW |
1157 | : FIRST_RET_REG) |
1158 | ||
1159 | #define BASE_ARG_REG(MODE) \ | |
3a8699c7 | 1160 | ((TARGET_SH2E && ((MODE) == SFmode)) \ |
5c3ea805 | 1161 | ? FIRST_FP_PARM_REG \ |
d5dd0a62 OE |
1162 | : TARGET_FPU_DOUBLE \ |
1163 | && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1164 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\ | |
225e4f43 | 1165 | ? FIRST_FP_PARM_REG \ |
5c3ea805 JW |
1166 | : FIRST_PARM_REG) |
1167 | ||
994295f2 | 1168 | /* 1 if N is a possible register number for function argument passing. */ |
fada1961 R |
1169 | /* ??? There are some callers that pass REGNO as int, and others that pass |
1170 | it as unsigned. We get warnings unless we do casts everywhere. */ | |
c5d67833 | 1171 | #define FUNCTION_ARG_REGNO_P(REGNO) \ |
fada1961 R |
1172 | (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \ |
1173 | && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\ | |
50fe8924 | 1174 | || (TARGET_FPU_ANY \ |
fada1961 R |
1175 | && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \ |
1176 | && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \ | |
1177 | + NPARM_REGS (SFmode)))) | |
bc45ade3 | 1178 | \f |
df4bacab OE |
1179 | #ifdef __cplusplus |
1180 | ||
bc45ade3 SC |
1181 | /* Define a data type for recording info about an argument list |
1182 | during the scan of that argument list. This data type should | |
1183 | hold all necessary information about the function itself | |
1184 | and about the args processed so far, enough to enable macros | |
1185 | such as FUNCTION_ARG to determine where the next arg should go. | |
1186 | ||
1187 | On SH, this is a single integer, which is a number of words | |
1188 | of arguments scanned so far (including the invisible argument, | |
1189 | if any, which holds the structure-value-address). | |
1190 | Thus NARGREGS or more means all following args should go on the stack. */ | |
df4bacab | 1191 | |
5c3ea805 | 1192 | enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 }; |
df4bacab OE |
1193 | |
1194 | struct sh_args | |
1195 | { | |
1196 | /* How many SH_ARG_INT and how many SH_ARG_FLOAT args there are. */ | |
1197 | int arg_count[2]; | |
1198 | ||
1199 | bool force_mem; | |
1200 | ||
5e7a8ee0 | 1201 | /* Nonzero if a prototype is available for the function. */ |
df4bacab OE |
1202 | bool prototype_p; |
1203 | ||
fa5322fa AO |
1204 | /* The number of an odd floating-point register, that should be used |
1205 | for the next argument of type float. */ | |
df4bacab OE |
1206 | int free_single_fp_reg; |
1207 | ||
fa5322fa | 1208 | /* Whether we're processing an outgoing function call. */ |
df4bacab | 1209 | bool outgoing; |
fa5322fa | 1210 | |
e318fc8f KK |
1211 | /* This is set to nonzero when the call in question must use the Renesas ABI, |
1212 | even without the -mrenesas option. */ | |
df4bacab | 1213 | bool renesas_abi; |
e318fc8f KK |
1214 | }; |
1215 | ||
df4bacab OE |
1216 | typedef sh_args CUMULATIVE_ARGS; |
1217 | ||
1218 | /* Set when processing a function with interrupt attribute. */ | |
1219 | extern bool current_function_interrupt; | |
1220 | ||
1221 | #endif // __cplusplus | |
5c3ea805 | 1222 | |
bc45ade3 SC |
1223 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1224 | for a call to a function whose data type is FNTYPE. | |
1225 | For a library call, FNTYPE is 0. | |
1226 | ||
1227 | On SH, the offset always starts at 0: the first parm reg is always | |
07385c49 R |
1228 | the same reg for a given argument class. |
1229 | ||
1230 | For TARGET_HITACHI, the structure value pointer is passed in memory. */ | |
0f6937fe | 1231 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
50fe8924 OE |
1232 | sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL),\ |
1233 | (N_NAMED_ARGS), VOIDmode) | |
fa5322fa AO |
1234 | |
1235 | #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
cc15e98f | 1236 | sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE)) |
bc45ade3 | 1237 | |
6d1cb95f R |
1238 | /* By accident we got stuck with passing SCmode on SH4 little endian |
1239 | in two registers that are nominally successive - which is different from | |
1240 | two single SFmode values, where we take endianness translation into | |
1241 | account. That does not work at all if an odd number of registers is | |
1242 | already in use, so that got fixed, but library functions are still more | |
1243 | likely to use complex numbers without mixing them with SFmode arguments | |
1244 | (which in C would have to be structures), so for the sake of ABI | |
1245 | compatibility the way SCmode values are passed when an even number of | |
1246 | FP registers is in use remains different from a pair of SFmode values for | |
1247 | now. | |
1248 | I.e.: | |
1249 | foo (double); a: fr5,fr4 | |
1250 | foo (float a, float b); a: fr5 b: fr4 | |
1251 | foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency, | |
50fe8924 | 1252 | this should be the other way round... |
6d1cb95f R |
1253 | foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */ |
1254 | #define FUNCTION_ARG_SCmode_WART 1 | |
1255 | ||
fa5322fa AO |
1256 | /* Minimum alignment for an argument to be passed by callee-copy |
1257 | reference. We need such arguments to be aligned to 8 byte | |
1258 | boundaries, because they'll be loaded using quad loads. */ | |
1259 | #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT) | |
1260 | ||
bc45ade3 | 1261 | /* Perform any needed actions needed for a function that is receiving a |
994295f2 | 1262 | variable number of arguments. */ |
bc45ade3 | 1263 | |
1bad666c JW |
1264 | /* Call the function profiler with a given profile label. |
1265 | We use two .aligns, so as to make sure that both the .long is aligned | |
1266 | on a 4 byte boundary, and that the .long is a fixed distance (2 bytes) | |
1267 | from the trapa instruction. */ | |
b9654711 SC |
1268 | #define FUNCTION_PROFILER(STREAM,LABELNO) \ |
1269 | { \ | |
e1fab8ba OE |
1270 | fprintf((STREAM), "\t.align\t2\n"); \ |
1271 | fprintf((STREAM), "\ttrapa\t#33\n"); \ | |
1272 | fprintf((STREAM), "\t.align\t2\n"); \ | |
1273 | asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ | |
bc45ade3 SC |
1274 | } |
1275 | ||
d59c4c8e JW |
1276 | /* Define this macro if the code for function profiling should come |
1277 | before the function prologue. Normally, the profiling code comes | |
1278 | after. */ | |
d59c4c8e JW |
1279 | #define PROFILE_BEFORE_PROLOGUE |
1280 | ||
bc45ade3 SC |
1281 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1282 | the stack pointer does not matter. The value is tested only in | |
1283 | functions that have frame pointers. | |
1284 | No definition is equivalent to always zero. */ | |
4fdd1f85 | 1285 | #define EXIT_IGNORE_STACK 1 |
bc45ade3 | 1286 | |
73774972 | 1287 | /* |
ddd5a7c1 | 1288 | On the SH, the trampoline looks like |
50fe8924 OE |
1289 | 2 0002 D202 mov.l l2,r2 |
1290 | 1 0000 D301 mov.l l1,r3 | |
1291 | 3 0004 422B jmp @r2 | |
1292 | 4 0006 0009 nop | |
ec4ad0f9 AO |
1293 | 5 0008 00000000 l1: .long area |
1294 | 6 000c 00000000 l2: .long function */ | |
bc45ade3 SC |
1295 | |
1296 | /* Length in units of the trampoline for entering a nested function. */ | |
e1fab8ba | 1297 | #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : 16) |
bc45ade3 | 1298 | |
ead4af4f | 1299 | /* Alignment required for a trampoline in bits. */ |
e9a25f70 | 1300 | #define TRAMPOLINE_ALIGNMENT \ |
ead4af4f | 1301 | ((CACHE_LOG < 3 \ |
e1fab8ba OE |
1302 | || (optimize_size && ! (TARGET_HARD_SH4))) ? 32 \ |
1303 | : 64) | |
bc45ade3 | 1304 | |
d1405d89 JW |
1305 | /* A C expression whose value is RTL representing the value of the return |
1306 | address for the frame COUNT steps up from the current frame. | |
1307 | FRAMEADDR is already the frame pointer of the COUNT frame, so we | |
1308 | can ignore COUNT. */ | |
d1405d89 | 1309 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
23d0939b | 1310 | (((COUNT) == 0) ? sh_get_pr_initial_val () : NULL_RTX) |
2754d3c5 R |
1311 | |
1312 | /* A C expression whose value is RTL representing the location of the | |
1313 | incoming return address at the beginning of any function, before the | |
1314 | prologue. This RTL is either a REG, indicating that the return | |
1315 | value is saved in REG, or a MEM representing a location in | |
1316 | the stack. */ | |
e1fab8ba | 1317 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, PR_REG) |
bc45ade3 SC |
1318 | \f |
1319 | /* Addressing modes, and classification of registers for them. */ | |
fa5322fa | 1320 | #define HAVE_POST_INCREMENT TARGET_SH1 |
fa5322fa | 1321 | #define HAVE_PRE_DECREMENT TARGET_SH1 |
bc45ade3 | 1322 | |
da5b1ec1 OE |
1323 | #define USE_LOAD_POST_INCREMENT(mode) TARGET_SH1 |
1324 | #define USE_LOAD_PRE_DECREMENT(mode) TARGET_SH2A | |
1325 | #define USE_STORE_POST_INCREMENT(mode) TARGET_SH2A | |
1326 | #define USE_STORE_PRE_DECREMENT(mode) TARGET_SH1 | |
fbe1758d | 1327 | |
fa1aecc1 CB |
1328 | /* If a memory clear move would take CLEAR_RATIO or more simple |
1329 | move-instruction pairs, we will do a setmem instead. */ | |
1330 | ||
1331 | #define CLEAR_RATIO(speed) ((speed) ? 15 : 3) | |
1332 | ||
bc45ade3 SC |
1333 | /* Macros to check register numbers against specific register classes. */ |
1334 | ||
1335 | /* These assume that REGNO is a hard or pseudo reg number. | |
1336 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1337 | or a pseudo reg currently allocated to a suitable hard reg. | |
1338 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
1339 | has been allocated, which happens in reginfo.c during register |
1340 | allocation. */ | |
c5d67833 | 1341 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
104ee20b AO |
1342 | (GENERAL_OR_AP_REGISTER_P (REGNO) \ |
1343 | || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)])) | |
c5d67833 | 1344 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
e1fab8ba | 1345 | ((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG) |
bc45ade3 | 1346 | |
1e44e857 DJ |
1347 | /* True if SYMBOL + OFFSET constants must refer to something within |
1348 | SYMBOL's section. */ | |
1349 | #define SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P TARGET_FDPIC | |
1350 | ||
994295f2 JW |
1351 | /* Maximum number of registers that can appear in a valid memory |
1352 | address. */ | |
0d7e008e | 1353 | #define MAX_REGS_PER_ADDRESS 2 |
bc45ade3 SC |
1354 | |
1355 | /* Recognize any constant value that is a valid address. */ | |
c5d67833 | 1356 | #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) |
bc45ade3 | 1357 | |
bc45ade3 SC |
1358 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1359 | and check its validity for a certain class. | |
cdeed45a KK |
1360 | The suitable hard regs are always accepted and all pseudo regs |
1361 | are also accepted if STRICT is not set. */ | |
1362 | ||
1363 | /* Nonzero if X is a reg that can be used as a base reg. */ | |
1364 | #define REG_OK_FOR_BASE_P(X, STRICT) \ | |
1365 | (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \ | |
1366 | || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) | |
1367 | ||
1368 | /* Nonzero if X is a reg that can be used as an index. */ | |
1369 | #define REG_OK_FOR_INDEX_P(X, STRICT) \ | |
e1fab8ba | 1370 | ((REGNO (X) == R0_REG) \ |
cdeed45a KK |
1371 | || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) |
1372 | ||
1373 | /* Nonzero if X/OFFSET is a reg that can be used as an index. */ | |
1374 | #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \ | |
e1fab8ba | 1375 | ((REGNO (X) == R0_REG && OFFSET == 0) \ |
cdeed45a | 1376 | || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) |
0d7e008e | 1377 | |
32a7ab3d | 1378 | /* Macros for extra constraints. */ |
0d7e008e | 1379 | |
50fe8924 | 1380 | #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \ |
32a7ab3d KK |
1381 | ((GET_CODE ((OP)) == LABEL_REF) \ |
1382 | || (GET_CODE ((OP)) == CONST \ | |
1383 | && GET_CODE (XEXP ((OP), 0)) == PLUS \ | |
1384 | && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \ | |
f3536097 | 1385 | && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))) |
735cb76e | 1386 | |
32a7ab3d KK |
1387 | #define IS_NON_EXPLICIT_CONSTANT_P(OP) \ |
1388 | (CONSTANT_P (OP) \ | |
50fe8924 | 1389 | && !CONST_INT_P (OP) \ |
32a7ab3d KK |
1390 | && GET_CODE (OP) != CONST_DOUBLE \ |
1391 | && (!flag_pic \ | |
1392 | || (LEGITIMATE_PIC_OPERAND_P (OP) \ | |
dc3ba671 | 1393 | && !PIC_ADDR_P (OP) \ |
32a7ab3d | 1394 | && GET_CODE (OP) != LABEL_REF))) |
42201282 | 1395 | |
fa5322fa AO |
1396 | #define GOT_ENTRY_P(OP) \ |
1397 | (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
1398 | && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT) | |
1399 | ||
1400 | #define GOTPLT_ENTRY_P(OP) \ | |
1401 | (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
1402 | && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT) | |
1403 | ||
fff08fd8 SC |
1404 | #define UNSPEC_GOTOFF_P(OP) \ |
1405 | (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF) | |
1406 | ||
fa5322fa | 1407 | #define GOTOFF_P(OP) \ |
fff08fd8 SC |
1408 | (GET_CODE (OP) == CONST \ |
1409 | && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \ | |
1410 | || (GET_CODE (XEXP ((OP), 0)) == PLUS \ | |
50fe8924 | 1411 | && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \ |
f3536097 | 1412 | && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))) |
fa5322fa AO |
1413 | |
1414 | #define PIC_ADDR_P(OP) \ | |
1415 | (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
1416 | && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC) | |
1417 | ||
dc3ba671 RS |
1418 | #define PCREL_SYMOFF_P(OP) \ |
1419 | (GET_CODE (OP) == CONST \ | |
1420 | && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ | |
1421 | && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF) | |
735cb76e | 1422 | |
fa5322fa AO |
1423 | #define NON_PIC_REFERENCE_P(OP) \ |
1424 | (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \ | |
73a4d10b R |
1425 | || (GET_CODE (OP) == CONST \ |
1426 | && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \ | |
e1fab8ba | 1427 | || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF)) \ |
fa5322fa AO |
1428 | || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \ |
1429 | && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \ | |
e1fab8ba | 1430 | || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF) \ |
f3536097 | 1431 | && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))) |
fa5322fa AO |
1432 | |
1433 | #define PIC_REFERENCE_P(OP) \ | |
1434 | (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \ | |
1435 | || GOTOFF_P (OP) || PIC_ADDR_P (OP)) | |
1436 | ||
cdeed45a | 1437 | #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \ |
f3536097 | 1438 | ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \ |
cdeed45a KK |
1439 | || (GET_CODE (X) == SUBREG \ |
1440 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \ | |
73a4d10b | 1441 | GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \ |
f3536097 | 1442 | && REG_P (SUBREG_REG (X)) \ |
cdeed45a | 1443 | && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT))) |
bc45ade3 | 1444 | |
53c8870f RK |
1445 | /* Since this must be r0, which is a single register class, we must check |
1446 | SUBREGs more carefully, to be sure that we don't accept one that extends | |
1447 | outside the class. */ | |
cdeed45a | 1448 | #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \ |
f3536097 | 1449 | ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \ |
cdeed45a | 1450 | || (GET_CODE (X) == SUBREG \ |
73a4d10b R |
1451 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \ |
1452 | GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \ | |
f3536097 | 1453 | && REG_P (SUBREG_REG (X)) \ |
cdeed45a KK |
1454 | && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT))) |
1455 | ||
1456 | #ifdef REG_OK_STRICT | |
1457 | #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true) | |
1458 | #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true) | |
1459 | #else | |
1460 | #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false) | |
1461 | #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false) | |
1462 | #endif | |
bc45ade3 | 1463 | |
994295f2 | 1464 | \f |
ef41dabb R |
1465 | /* A C compound statement that attempts to replace X, which is an address |
1466 | that needs reloading, with a valid memory address for an operand of | |
6f50eb9c | 1467 | mode MODE. WIN is a C statement label elsewhere in the code. */ |
ef41dabb | 1468 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
6f50eb9c KK |
1469 | do { \ |
1470 | if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \ | |
ef41dabb | 1471 | goto WIN; \ |
6f50eb9c | 1472 | } while (0) |
bc45ade3 SC |
1473 | \f |
1474 | /* Specify the machine mode that this machine uses | |
1475 | for the index in the tablejump instruction. */ | |
8b26829f | 1476 | #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode) |
bc45ade3 | 1477 | |
33f7f353 JR |
1478 | #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ |
1479 | ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \ | |
33f7f353 | 1480 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ |
64ad9df2 R |
1481 | : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ |
1482 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ | |
33f7f353 JR |
1483 | : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \ |
1484 | : SImode) | |
1485 | ||
18543a22 ILT |
1486 | /* Define as C expression which evaluates to nonzero if the tablejump |
1487 | instruction expects the table to contain offsets from the address of the | |
1488 | table. | |
6f317ef3 | 1489 | Do not define this if the table should contain absolute addresses. */ |
18543a22 | 1490 | #define CASE_VECTOR_PC_RELATIVE 1 |
bc45ade3 | 1491 | |
fa5322fa AO |
1492 | /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */ |
1493 | #define FLOAT_TYPE_SIZE 32 | |
1494 | ||
3a8699c7 | 1495 | /* Since the SH2e has only `float' support, it is desirable to make all |
5c3ea805 | 1496 | floating point types equivalent to `float'. */ |
d5dd0a62 | 1497 | #define DOUBLE_TYPE_SIZE (TARGET_FPU_SINGLE_ONLY ? 32 : 64) |
5c3ea805 | 1498 | |
994295f2 | 1499 | /* 'char' is signed by default. */ |
bc45ade3 SC |
1500 | #define DEFAULT_SIGNED_CHAR 1 |
1501 | ||
1502 | /* The type of size_t unsigned int. */ | |
e1fab8ba | 1503 | #define SIZE_TYPE ("unsigned int") |
fa5322fa | 1504 | |
fa5322fa | 1505 | #undef PTRDIFF_TYPE |
e1fab8ba | 1506 | #define PTRDIFF_TYPE ("int") |
bc45ade3 | 1507 | |
8e87e161 SC |
1508 | #define WCHAR_TYPE "short unsigned int" |
1509 | #define WCHAR_TYPE_SIZE 16 | |
1951818c R |
1510 | |
1511 | #define SH_ELF_WCHAR_TYPE "long int" | |
8e87e161 | 1512 | |
bc45ade3 SC |
1513 | /* Max number of bytes we can move from memory to memory |
1514 | in one reasonably fast instruction. */ | |
e1fab8ba | 1515 | #define MOVE_MAX (4) |
fa5322fa AO |
1516 | |
1517 | /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever | |
1518 | MOVE_MAX is not a compile-time constant. */ | |
1519 | #define MAX_MOVE_MAX 8 | |
bc45ade3 | 1520 | |
fbe1758d AM |
1521 | /* Max number of bytes we want move_by_pieces to be able to copy |
1522 | efficiently. */ | |
e1fab8ba | 1523 | #define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4) |
fbe1758d | 1524 | |
9a63901f RK |
1525 | /* Define if operations between registers always perform the operation |
1526 | on the full register even if a narrower mode is specified. */ | |
9e11bfef | 1527 | #define WORD_REGISTER_OPERATIONS 1 |
9a63901f RK |
1528 | |
1529 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1530 | will either zero-extend or sign-extend. The value of this macro should | |
1531 | be the code that says which one of the two operations is implicitly | |
5a2fc4d7 | 1532 | done, UNKNOWN if none. */ |
e1fab8ba | 1533 | #define LOAD_EXTEND_OP(MODE) ((MODE) != SImode ? SIGN_EXTEND : UNKNOWN) |
bc45ade3 | 1534 | |
211a0f85 | 1535 | /* Define if loading short immediate values into registers sign extends. */ |
58f2ae18 | 1536 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
211a0f85 | 1537 | |
9a5bb317 R |
1538 | /* Nonzero if access to memory by bytes is no faster than for words. */ |
1539 | #define SLOW_BYTE_ACCESS 1 | |
1540 | ||
a594120b OE |
1541 | /* Nonzero if the target supports dynamic shift instructions |
1542 | like shad and shld. */ | |
1543 | #define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) | |
1544 | ||
aadb5b43 OE |
1545 | /* The cost of using the dynamic shift insns (shad, shld) are the same |
1546 | if they are available. If they are not available a library function will | |
1547 | be emitted instead, which is more expensive. */ | |
1548 | #define SH_DYNAMIC_SHIFT_COST (TARGET_DYNSHIFT ? 1 : 20) | |
1549 | ||
1550 | /* Defining SHIFT_COUNT_TRUNCATED tells the combine pass that code like | |
1551 | (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
1552 | This is not generally true when hardware dynamic shifts (shad, shld) are | |
1553 | used, because they check the sign bit _before_ the modulo op. The sign | |
1554 | bit determines whether it is a left shift or a right shift: | |
1555 | if (Y < 0) | |
1556 | return X << (Y & 31); | |
1557 | else | |
1558 | return X >> (-Y) & 31); | |
1559 | ||
1560 | The dynamic shift library routines in lib1funcs.S do not use the sign bit | |
1561 | like the hardware dynamic shifts and truncate the shift count to 31. | |
1562 | We define SHIFT_COUNT_TRUNCATED to 0 and express the implied shift count | |
1563 | truncation in the library function call patterns, as this gives slightly | |
1564 | more compact code. */ | |
1565 | #define SHIFT_COUNT_TRUNCATED (0) | |
bc45ade3 | 1566 | |
bc45ade3 | 1567 | /* All integers have the same format so truncation is easy. */ |
e1fab8ba | 1568 | #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) (true) |
bc45ade3 SC |
1569 | |
1570 | /* Define this if addresses of constant functions | |
1571 | shouldn't be put through pseudo regs where they can be cse'd. | |
1572 | Desirable on machines where ordinary constants are expensive | |
1573 | but a CALL with constant address is cheap. */ | |
1574 | /*#define NO_FUNCTION_CSE 1*/ | |
1575 | ||
994295f2 | 1576 | /* The machine modes of pointers and functions. */ |
e1fab8ba | 1577 | #define Pmode (SImode) |
bc45ade3 SC |
1578 | #define FUNCTION_MODE Pmode |
1579 | ||
97b65a3e JW |
1580 | /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2 |
1581 | are actually function calls with some special constraints on arguments | |
1582 | and register usage. | |
0d7e008e | 1583 | |
994295f2 JW |
1584 | These macros tell reorg that the references to arguments and |
1585 | register clobbers for insns of type sfunc do not appear to happen | |
0d7e008e SC |
1586 | until after the millicode call. This allows reorg to put insns |
1587 | which set the argument registers into the delay slot of the millicode | |
1588 | call -- thus they act more like traditional CALL_INSNs. | |
1589 | ||
0603a39d | 1590 | get_attr_is_sfunc will try to recognize the given insn, so make sure to |
0d7e008e SC |
1591 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns |
1592 | in particular. */ | |
1593 | ||
1594 | #define INSN_SETS_ARE_DELAYED(X) \ | |
50fe8924 | 1595 | ((NONJUMP_INSN_P (X) \ |
0d7e008e SC |
1596 | && GET_CODE (PATTERN (X)) != SEQUENCE \ |
1597 | && GET_CODE (PATTERN (X)) != USE \ | |
1598 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
0603a39d | 1599 | && get_attr_is_sfunc (X))) |
0d7e008e SC |
1600 | |
1601 | #define INSN_REFERENCES_ARE_DELAYED(X) \ | |
50fe8924 | 1602 | ((NONJUMP_INSN_P (X) \ |
0d7e008e SC |
1603 | && GET_CODE (PATTERN (X)) != SEQUENCE \ |
1604 | && GET_CODE (PATTERN (X)) != USE \ | |
1605 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
0603a39d | 1606 | && get_attr_is_sfunc (X))) |
0d7e008e | 1607 | |
1a66cd67 AO |
1608 | \f |
1609 | /* Position Independent Code. */ | |
1a66cd67 | 1610 | |
2cef831c KK |
1611 | /* We can't directly access anything that contains a symbol, |
1612 | nor can we indirect via the constant pool. */ | |
1613 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
1bf93c14 R |
1614 | ((! nonpic_symbol_mentioned_p (X) \ |
1615 | && (GET_CODE (X) != SYMBOL_REF \ | |
1616 | || ! CONSTANT_POOL_ADDRESS_P (X) \ | |
e1fab8ba | 1617 | || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))) |
2cef831c | 1618 | |
1a66cd67 AO |
1619 | #define SYMBOLIC_CONST_P(X) \ |
1620 | ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \ | |
1621 | && nonpic_symbol_mentioned_p (X)) | |
1622 | \f | |
bc45ade3 | 1623 | /* Compute extra cost of moving data between one register class |
e9a25f70 | 1624 | and another. */ |
bc45ade3 | 1625 | |
ec555f32 R |
1626 | /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass |
1627 | uses this information. Hence, the general register <-> floating point | |
225e4f43 | 1628 | register information here is not used for SFmode. */ |
9a4816af | 1629 | #define REGCLASS_HAS_GENERAL_REG(CLASS) \ |
a4f71b01 | 1630 | ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \ |
e1fab8ba | 1631 | || ((CLASS) == SIBCALL_REGS)) |
70a72ca4 | 1632 | |
9a4816af R |
1633 | #define REGCLASS_HAS_FP_REG(CLASS) \ |
1634 | ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \ | |
1818d01c | 1635 | || (CLASS) == DF_REGS) |
9a4816af | 1636 | |
85256f8a | 1637 | /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This |
ec4c28e5 | 1638 | would be so that people with slow memory systems could generate |
85256f8a | 1639 | different code that does fewer memory accesses. */ |
ec4c28e5 R |
1640 | |
1641 | /* A C expression for the cost of a branch instruction. A value of 1 | |
91afd29b OE |
1642 | is the default; other values are interpreted relative to that. */ |
1643 | #define BRANCH_COST(speed_p, predictable_p) sh_branch_cost | |
bc45ade3 | 1644 | \f |
994295f2 | 1645 | /* Assembler output control. */ |
bc45ade3 | 1646 | |
17b65371 DE |
1647 | /* A C string constant describing how to begin a comment in the target |
1648 | assembler language. The compiler assumes that the comment will end at | |
1649 | the end of the line. */ | |
1650 | #define ASM_COMMENT_START "!" | |
1651 | ||
0d7e008e SC |
1652 | #define ASM_APP_ON "" |
1653 | #define ASM_APP_OFF "" | |
1654 | #define FILE_ASM_OP "\t.file\n" | |
471b6f1b | 1655 | #define SET_ASM_OP "\t.set\t" |
bc45ade3 | 1656 | |
994295f2 | 1657 | /* How to change between sections. */ |
e1fab8ba | 1658 | #define TEXT_SECTION_ASM_OP "\t.text" |
50fe8924 | 1659 | #define DATA_SECTION_ASM_OP "\t.data" |
b9654711 | 1660 | |
fa5322fa AO |
1661 | #if defined CRT_BEGIN || defined CRT_END |
1662 | /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */ | |
e1fab8ba OE |
1663 | #undef TEXT_SECTION_ASM_OP |
1664 | #define TEXT_SECTION_ASM_OP "\t.text" | |
fa5322fa AO |
1665 | #endif |
1666 | ||
48b1580e | 1667 | #ifndef BSS_SECTION_ASM_OP |
471b6f1b | 1668 | #define BSS_SECTION_ASM_OP "\t.section\t.bss" |
48b1580e VM |
1669 | #endif |
1670 | ||
48b1580e VM |
1671 | #ifndef ASM_OUTPUT_ALIGNED_BSS |
1672 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
1673 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
1674 | #endif | |
1675 | ||
e115e436 JW |
1676 | /* Define this so that jump tables go in same section as the current function, |
1677 | which could be text or it could be a user defined section. */ | |
75197b37 | 1678 | #define JUMP_TABLES_IN_TEXT_SECTION 1 |
e115e436 | 1679 | |
994295f2 | 1680 | #undef DO_GLOBAL_CTORS_BODY |
b9654711 SC |
1681 | #define DO_GLOBAL_CTORS_BODY \ |
1682 | { \ | |
00f46785 | 1683 | typedef void (*pfunc) (void); \ |
b9654711 SC |
1684 | extern pfunc __ctors[]; \ |
1685 | extern pfunc __ctors_end[]; \ | |
1686 | pfunc *p; \ | |
c1fe41cb | 1687 | for (p = __ctors_end; p > __ctors; ) \ |
b9654711 | 1688 | { \ |
c1fe41cb | 1689 | (*--p)(); \ |
b9654711 | 1690 | } \ |
994295f2 | 1691 | } |
b9654711 | 1692 | |
994295f2 | 1693 | #undef DO_GLOBAL_DTORS_BODY |
c5d67833 | 1694 | #define DO_GLOBAL_DTORS_BODY \ |
b9654711 | 1695 | { \ |
00f46785 | 1696 | typedef void (*pfunc) (void); \ |
b9654711 SC |
1697 | extern pfunc __dtors[]; \ |
1698 | extern pfunc __dtors_end[]; \ | |
1699 | pfunc *p; \ | |
1700 | for (p = __dtors; p < __dtors_end; p++) \ | |
1701 | { \ | |
1702 | (*p)(); \ | |
1703 | } \ | |
994295f2 | 1704 | } |
b9654711 | 1705 | |
b9654711 | 1706 | #define ASM_OUTPUT_REG_PUSH(file, v) \ |
73a4d10b | 1707 | { \ |
e1fab8ba | 1708 | fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \ |
73a4d10b | 1709 | } |
bc45ade3 | 1710 | |
b9654711 | 1711 | #define ASM_OUTPUT_REG_POP(file, v) \ |
73a4d10b | 1712 | { \ |
e1fab8ba | 1713 | fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \ |
73a4d10b | 1714 | } |
b9654711 | 1715 | |
994295f2 | 1716 | /* DBX register number for a given compiler register number. */ |
5c3ea805 JW |
1717 | /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers |
1718 | to match gdb. */ | |
4977bab6 ZW |
1719 | /* expand_builtin_init_dwarf_reg_sizes uses this to test if a |
1720 | register exists, so we should return -1 for invalid register numbers. */ | |
1951818c R |
1721 | #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO) |
1722 | ||
1723 | #define SH_DBX_REGISTER_NUMBER(REGNO) \ | |
b869f904 R |
1724 | (IN_RANGE ((REGNO), \ |
1725 | (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ | |
e1fab8ba | 1726 | FIRST_GENERAL_REG + 15U) \ |
fada1961 | 1727 | ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \ |
50fe8924 | 1728 | : ((int) (REGNO) >= FIRST_FP_REG \ |
b869f904 | 1729 | && ((int) (REGNO) \ |
e1fab8ba OE |
1730 | <= (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)))) \ |
1731 | ? ((unsigned) (REGNO) - FIRST_FP_REG + 25) \ | |
fa5322fa | 1732 | : XD_REGISTER_P (REGNO) \ |
e1fab8ba | 1733 | ? ((unsigned) (REGNO) - FIRST_XD_REG + 87) \ |
fa5322fa | 1734 | : (REGNO) == PR_REG \ |
e1fab8ba | 1735 | ? (17) \ |
fa5322fa | 1736 | : (REGNO) == GBR_REG \ |
e1fab8ba | 1737 | ? (18) \ |
fa5322fa | 1738 | : (REGNO) == MACH_REG \ |
e1fab8ba | 1739 | ? (20) \ |
fa5322fa | 1740 | : (REGNO) == MACL_REG \ |
e1fab8ba | 1741 | ? (21) \ |
926e663e | 1742 | : (REGNO) == T_REG \ |
e1fab8ba | 1743 | ? (22) \ |
fa5322fa | 1744 | : (REGNO) == FPUL_REG \ |
e1fab8ba | 1745 | ? (23) \ |
926e663e | 1746 | : (REGNO) == FPSCR_REG \ |
e1fab8ba | 1747 | ? (24) \ |
fada1961 | 1748 | : (unsigned) -1) |
fa5322fa | 1749 | |
bc45ade3 SC |
1750 | /* This is how to output an assembler line |
1751 | that says to advance the location counter | |
1752 | to a multiple of 2**LOG bytes. */ | |
1753 | ||
1754 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1755 | if ((LOG) != 0) \ | |
e9a25f70 | 1756 | fprintf ((FILE), "\t.align %d\n", (LOG)) |
bc45ade3 | 1757 | |
506a61b1 KG |
1758 | /* Globalizing directive for a label. */ |
1759 | #define GLOBAL_ASM_OP "\t.global\t" | |
bc45ade3 | 1760 | |
50fe8924 | 1761 | /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ |
bc45ade3 | 1762 | |
994295f2 | 1763 | /* Output a relative address table. */ |
50fe8924 | 1764 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ |
33f7f353 | 1765 | switch (GET_MODE (BODY)) \ |
e9a25f70 | 1766 | { \ |
4e10a5a7 | 1767 | case E_SImode: \ |
e9a25f70 JL |
1768 | asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \ |
1769 | break; \ | |
4e10a5a7 | 1770 | case E_HImode: \ |
e9a25f70 JL |
1771 | asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \ |
1772 | break; \ | |
4e10a5a7 | 1773 | case E_QImode: \ |
e9a25f70 JL |
1774 | asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \ |
1775 | break; \ | |
318881c0 KG |
1776 | default: \ |
1777 | break; \ | |
e9a25f70 | 1778 | } |
bc45ade3 | 1779 | |
994295f2 | 1780 | /* Output an absolute table element. */ |
0d7e008e | 1781 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ |
8b26829f | 1782 | if (! optimize || TARGET_BIGTABLE) \ |
f1a58d92 | 1783 | asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \ |
0d7e008e | 1784 | else \ |
f1a58d92 | 1785 | asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); |
bc45ade3 | 1786 | |
bc45ade3 | 1787 | \f |
e9a25f70 JL |
1788 | /* A C statement to be executed just prior to the output of |
1789 | assembler code for INSN, to modify the extracted operands so | |
1790 | they will be output differently. | |
1791 | ||
1792 | Here the argument OPVEC is the vector containing the operands | |
1793 | extracted from INSN, and NOPERANDS is the number of elements of | |
1794 | the vector which contain meaningful data for this insn. | |
1795 | The contents of this vector are what will be used to convert the insn | |
1796 | template into assembler code, so you can change the assembler output | |
1797 | by changing the contents of the vector. */ | |
c5d67833 | 1798 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
e9a25f70 | 1799 | final_prescan_insn ((INSN), (OPVEC), (NOPERANDS)) |
bc45ade3 | 1800 | |
994295f2 JW |
1801 | /* Which processor to schedule for. The elements of the enumeration must |
1802 | match exactly the cpu attribute in the sh.md file. */ | |
994295f2 | 1803 | enum processor_type { |
994295f2 JW |
1804 | PROCESSOR_SH1, |
1805 | PROCESSOR_SH2, | |
3a8699c7 | 1806 | PROCESSOR_SH2E, |
157371cf | 1807 | PROCESSOR_SH2A, |
5c3ea805 | 1808 | PROCESSOR_SH3, |
225e4f43 | 1809 | PROCESSOR_SH3E, |
fa5322fa | 1810 | PROCESSOR_SH4, |
e1fab8ba | 1811 | PROCESSOR_SH4A |
994295f2 JW |
1812 | }; |
1813 | ||
1814 | #define sh_cpu_attr ((enum attr_cpu)sh_cpu) | |
1815 | extern enum processor_type sh_cpu; | |
1816 | ||
e9a25f70 JL |
1817 | enum mdep_reorg_phase_e |
1818 | { | |
1819 | SH_BEFORE_MDEP_REORG, | |
1820 | SH_INSERT_USES_LABELS, | |
1821 | SH_SHORTEN_BRANCHES0, | |
1822 | SH_FIXUP_PCLOAD, | |
1823 | SH_SHORTEN_BRANCHES1, | |
1824 | SH_AFTER_MDEP_REORG | |
1825 | }; | |
1826 | ||
33f7f353 JR |
1827 | extern enum mdep_reorg_phase_e mdep_reorg_phase; |
1828 | ||
c8f0269d | 1829 | /* Handle Renesas compiler's pragmas. */ |
c58b209a NB |
1830 | #define REGISTER_TARGET_PRAGMAS() do { \ |
1831 | c_register_pragma (0, "interrupt", sh_pr_interrupt); \ | |
1832 | c_register_pragma (0, "trapa", sh_pr_trapa); \ | |
1833 | c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \ | |
8b97c5f8 | 1834 | } while (0) |
b9654711 | 1835 | |
a6ab9fc0 R |
1836 | extern tree sh_deferred_function_attributes; |
1837 | extern tree *sh_deferred_function_attributes_tail; | |
b9654711 | 1838 | |
552ecbd9 | 1839 | |
b52cd365 | 1840 | \f |
9342c0c4 R |
1841 | /* Instructions with unfilled delay slots take up an |
1842 | extra two bytes for the nop in the delay slot. | |
1843 | sh-dsp parallel processing insns are four bytes long. */ | |
b52cd365 | 1844 | #define ADJUST_INSN_LENGTH(X, LENGTH) \ |
9342c0c4 | 1845 | (LENGTH) += sh_insn_length_adjustment (X); |
c5d67833 | 1846 | \f |
c5d67833 | 1847 | /* Define this macro if it is advisable to hold scalars in registers |
73774972 | 1848 | in a wider mode than that declared by the program. In such cases, |
c5d67833 JW |
1849 | the value is constrained to be within the bounds of the declared |
1850 | type, but kept valid in the wider mode. The signedness of the | |
1851 | extension may differ from that of the type. | |
1852 | ||
1853 | Leaving the unsignedp unchanged gives better code than always setting it | |
1854 | to 0. This is despite the fact that we have only signed char and short | |
1855 | load instructions. */ | |
1856 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
1857 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
73a4d10b | 1858 | && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\ |
f1bebab6 | 1859 | (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), (MODE) = SImode; |
c5d67833 | 1860 | |
e1fab8ba | 1861 | #define MAX_FIXED_MODE_SIZE (64) |
dcb44500 | 1862 | |
7a296495 CB |
1863 | /* Better to allocate once the maximum space for outgoing args in the |
1864 | prologue rather than duplicate around each call. */ | |
1865 | #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS | |
c5d67833 | 1866 | |
9f09b1f2 R |
1867 | #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE } |
1868 | ||
d5dd0a62 | 1869 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_FPU_DOUBLE) |
9f09b1f2 | 1870 | |
5d806217 R |
1871 | #define ACTUAL_NORMAL_MODE(ENTITY) \ |
1872 | (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE) | |
1873 | ||
1270c255 | 1874 | #define NORMAL_MODE(ENTITY) \ |
ac55736a R |
1875 | (sh_cfun_interrupt_handler_p () \ |
1876 | ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \ | |
5d806217 | 1877 | : ACTUAL_NORMAL_MODE (ENTITY)) |
1270c255 | 1878 | |
df4bacab | 1879 | #define EPILOGUE_USES(REGNO) (TARGET_FPU_ANY && REGNO == FPSCR_REG) |
9f09b1f2 | 1880 | |
e1fab8ba | 1881 | #define DWARF_FRAME_RETURN_COLUMN (DWARF_FRAME_REGNUM (PR_REG)) |
2754d3c5 | 1882 | |
e1fab8ba | 1883 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 4U : INVALID_REGNUM) |
4977bab6 | 1884 | |
fada1961 R |
1885 | #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM |
1886 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) | |
4977bab6 | 1887 | |
b869f904 | 1888 | /* We have to distinguish between code and data, so that we apply |
f4966f8c | 1889 | datalabel where and only where appropriate. Use sdataN for data. */ |
b869f904 | 1890 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
1e44e857 DJ |
1891 | ((TARGET_FDPIC \ |
1892 | ? ((GLOBAL) ? DW_EH_PE_indirect | DW_EH_PE_datarel : DW_EH_PE_pcrel) \ | |
1893 | : ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \ | |
1894 | | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))) \ | |
e1fab8ba | 1895 | | ((CODE) ? 0 : DW_EH_PE_sdata4)) |
b869f904 R |
1896 | |
1897 | /* Handle special EH pointer encodings. Absolute, pc-relative, and | |
1898 | indirect are handled automatically. */ | |
1899 | #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \ | |
1900 | do { \ | |
f4966f8c KK |
1901 | if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \ |
1902 | && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \ | |
b869f904 | 1903 | { \ |
f5b9e7c9 | 1904 | gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \ |
b869f904 R |
1905 | SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \ |
1906 | if (0) goto DONE; \ | |
1907 | } \ | |
1e44e857 DJ |
1908 | if (TARGET_FDPIC \ |
1909 | && ((ENCODING) & 0xf0) == (DW_EH_PE_indirect | DW_EH_PE_datarel)) \ | |
1910 | { \ | |
1911 | fputs ("\t.ualong ", FILE); \ | |
1912 | output_addr_const (FILE, ADDR); \ | |
1913 | if (GET_CODE (ADDR) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (ADDR)) \ | |
1914 | fputs ("@GOTFUNCDESC", FILE); \ | |
1915 | else \ | |
1916 | fputs ("@GOT", FILE); \ | |
1917 | goto DONE; \ | |
1918 | } \ | |
b869f904 R |
1919 | } while (0) |
1920 | ||
e1fab8ba | 1921 | #if (defined CRT_BEGIN || defined CRT_END) |
1a66cd67 AO |
1922 | /* SH constant pool breaks the devices in crtstuff.c to control section |
1923 | in where code resides. We have to write it as asm code. */ | |
cea3bd3e RH |
1924 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ |
1925 | asm (SECTION_OP "\n\ | |
1926 | mov.l 1f,r1\n\ | |
1a66cd67 AO |
1927 | mova 2f,r0\n\ |
1928 | braf r1\n\ | |
1929 | lds r0,pr\n\ | |
1930 | 0: .p2align 2\n\ | |
cea3bd3e RH |
1931 | 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\ |
1932 | 2:\n" TEXT_SECTION_ASM_OP); | |
e1fab8ba | 1933 | #endif /* (defined CRT_BEGIN || defined CRT_END) */ |
8b97c5f8 | 1934 | |
88657302 | 1935 | #endif /* ! GCC_SH_H */ |