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8b109b37 | 1 | /* Definitions of target machine for GNU compiler for Hitachi Super-H. |
c5c76735 | 2 | Copyright (C) 1993-1998, 1999 Free Software Foundation, Inc. |
058f9bb5 JW |
3 | Contributed by Steve Chamberlain (sac@cygnus.com). |
4 | Improved by Jim Wilson (wilson@cygnus.com). | |
bc45ade3 SC |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
bc45ade3 | 22 | |
8b109b37 | 23 | |
c5d67833 | 24 | #define TARGET_VERSION \ |
bc45ade3 SC |
25 | fputs (" (Hitachi SH)", stderr); |
26 | ||
e9a25f70 JL |
27 | /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't |
28 | include it here, because hconfig.h is also included by gencodes.c . */ | |
29 | extern int code_for_indirect_jump_scratch; | |
30 | ||
bc45ade3 SC |
31 | /* Generate SDB debugging information. */ |
32 | ||
c5d67833 | 33 | #define SDB_DEBUGGING_INFO |
bc45ade3 | 34 | |
60033bb7 DE |
35 | /* Output DBX (stabs) debugging information if doing -gstabs. */ |
36 | ||
3c35520e | 37 | #include "dbxcoff.h" |
60033bb7 | 38 | |
bc45ade3 SC |
39 | #define SDB_DELIM ";" |
40 | ||
cd9784db JW |
41 | #define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__} \ |
42 | %{m1:-D__sh1__} \ | |
43 | %{m2:-D__sh2__} \ | |
44 | %{m3:-D__sh3__} \ | |
e9a25f70 | 45 | %{m3e:-D__SH3E__} \ |
225e4f43 R |
46 | %{m4-single-only:-D__SH4_SINGLE_ONLY__} \ |
47 | %{m4-single:-D__SH4_SINGLE__} \ | |
48 | %{m4:-D__SH4__} \ | |
9ab70a9b R |
49 | %{!m1:%{!m2:%{!m3:%{!m3e:%{!m4:%{!m4-single:%{!m4-single-only:-D__sh1__}}}}}}} \ |
50 | %{mhitachi:-D__HITACHI__}" | |
00f8ff66 | 51 | |
65c42379 | 52 | #define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)" |
bc45ade3 | 53 | |
8b32b684 | 54 | #define ASM_SPEC "%{ml:-little} %{mrelax:-relax}" |
00f8ff66 | 55 | |
8b32b684 | 56 | #define LINK_SPEC "%{ml:-m shl} %{mrelax:-relax}" |
00f8ff66 | 57 | |
d8ace44f RK |
58 | /* We can not debug without a frame pointer. */ |
59 | /* #define CAN_DEBUG_WITHOUT_FP */ | |
0d7e008e | 60 | |
225e4f43 R |
61 | #define CONDITIONAL_REGISTER_USAGE \ |
62 | if (! TARGET_SH4 || ! TARGET_FMOVD) \ | |
63 | { \ | |
64 | int regno; \ | |
65 | for (regno = FIRST_XD_REG; regno <= LAST_XD_REG; regno++) \ | |
66 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
67 | if (! TARGET_SH4) \ | |
68 | { \ | |
69 | if (! TARGET_SH3E) \ | |
70 | { \ | |
71 | int regno; \ | |
72 | for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \ | |
73 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
74 | fixed_regs[FPUL_REG] = call_used_regs[FPUL_REG] = 1; \ | |
75 | } \ | |
76 | } \ | |
77 | } \ | |
78 | /* Hitachi saves and restores mac registers on call. */ \ | |
79 | if (TARGET_HITACHI) \ | |
80 | { \ | |
81 | call_used_regs[MACH_REG] = 0; \ | |
82 | call_used_regs[MACL_REG] = 0; \ | |
5a463884 | 83 | } |
bc45ade3 | 84 | \f |
85256f8a JW |
85 | /* ??? Need to write documentation for all SH options and add it to the |
86 | invoke.texi file. */ | |
87 | ||
994295f2 | 88 | /* Run-time compilation parameters selecting different hardware subsets. */ |
bc45ade3 SC |
89 | |
90 | extern int target_flags; | |
0d7e008e | 91 | #define ISIZE_BIT (1<<1) |
0d7e008e | 92 | #define DALIGN_BIT (1<<6) |
0d7e008e SC |
93 | #define SH1_BIT (1<<8) |
94 | #define SH2_BIT (1<<9) | |
95 | #define SH3_BIT (1<<10) | |
5c3ea805 | 96 | #define SH3E_BIT (1<<11) |
225e4f43 R |
97 | #define HARD_SH4_BIT (1<<5) |
98 | #define FPU_SINGLE_BIT (1<<7) | |
99 | #define SH4_BIT (1<<12) | |
100 | #define FMOVD_BIT (1<<4) | |
0d7e008e SC |
101 | #define SPACE_BIT (1<<13) |
102 | #define BIGTABLE_BIT (1<<14) | |
8b32b684 | 103 | #define RELAX_BIT (1<<15) |
0d7e008e | 104 | #define HITACHI_BIT (1<<22) |
9791111f | 105 | #define PADSTRUCT_BIT (1<<28) |
00f8ff66 | 106 | #define LITTLE_ENDIAN_BIT (1<<29) |
e9a25f70 | 107 | #define IEEE_BIT (1<<30) |
b9654711 | 108 | |
c5d67833 JW |
109 | /* Nonzero if we should dump out instruction size info. */ |
110 | #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT) | |
111 | ||
112 | /* Nonzero to align doubles on 64 bit boundaries. */ | |
113 | #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT) | |
114 | ||
994295f2 | 115 | /* Nonzero if we should generate code using type 1 insns. */ |
b9654711 SC |
116 | #define TARGET_SH1 (target_flags & SH1_BIT) |
117 | ||
994295f2 | 118 | /* Nonzero if we should generate code using type 2 insns. */ |
b9654711 | 119 | #define TARGET_SH2 (target_flags & SH2_BIT) |
bc45ade3 | 120 | |
994295f2 | 121 | /* Nonzero if we should generate code using type 3 insns. */ |
b9654711 | 122 | #define TARGET_SH3 (target_flags & SH3_BIT) |
bc45ade3 | 123 | |
5c3ea805 JW |
124 | /* Nonzero if we should generate code using type 3E insns. */ |
125 | #define TARGET_SH3E (target_flags & SH3E_BIT) | |
126 | ||
225e4f43 R |
127 | /* Nonzero if the cache line size is 32. */ |
128 | #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT) | |
129 | ||
130 | /* Nonzero if we schedule for a superscalar implementation. */ | |
131 | #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT) | |
132 | ||
133 | /* Nonzero if the target has separate instruction and data caches. */ | |
0aa54da2 | 134 | #define TARGET_HARVARD (target_flags & HARD_SH4_BIT) |
225e4f43 R |
135 | |
136 | /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */ | |
137 | #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT) | |
138 | ||
139 | /* Nonzero if the default precision of th FPU is single */ | |
140 | #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT) | |
141 | ||
142 | /* Nonzero if we should generate code using type 4 insns. */ | |
143 | #define TARGET_SH4 (target_flags & SH4_BIT) | |
144 | ||
145 | /* Nonzero if we should generate fmovd. */ | |
146 | #define TARGET_FMOVD (target_flags & FMOVD_BIT) | |
147 | ||
e9a25f70 JL |
148 | /* Nonzero if we respect NANs. */ |
149 | #define TARGET_IEEE (target_flags & IEEE_BIT) | |
150 | ||
994295f2 | 151 | /* Nonzero if we should generate smaller code rather than faster code. */ |
b9654711 SC |
152 | #define TARGET_SMALLCODE (target_flags & SPACE_BIT) |
153 | ||
994295f2 | 154 | /* Nonzero to use long jump tables. */ |
0d7e008e | 155 | #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT) |
b9654711 | 156 | |
8b32b684 JW |
157 | /* Nonzero to generate pseudo-ops needed by the assembler and linker |
158 | to do function call relaxing. */ | |
159 | #define TARGET_RELAX (target_flags & RELAX_BIT) | |
160 | ||
994295f2 | 161 | /* Nonzero if using Hitachi's calling convention. */ |
d3ae8277 | 162 | #define TARGET_HITACHI (target_flags & HITACHI_BIT) |
8e87e161 | 163 | |
9791111f JW |
164 | /* Nonzero if padding structures to a multiple of 4 bytes. This is |
165 | incompatible with Hitachi's compiler, and gives unusual structure layouts | |
166 | which confuse programmers. | |
167 | ??? This option is not useful, but is retained in case there are people | |
168 | who are still relying on it. It may be deleted in the future. */ | |
169 | #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT) | |
00f8ff66 | 170 | |
c5d67833 | 171 | /* Nonzero if generating code for a little endian SH. */ |
00f8ff66 SC |
172 | #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT) |
173 | ||
174 | #define TARGET_SWITCHES \ | |
e9a25f70 | 175 | { {"1", SH1_BIT}, \ |
c5d67833 JW |
176 | {"2", SH2_BIT}, \ |
177 | {"3", SH3_BIT|SH2_BIT}, \ | |
225e4f43 R |
178 | {"3e", SH3E_BIT|SH3_BIT|SH2_BIT|FPU_SINGLE_BIT}, \ |
179 | {"4-single-only", SH3E_BIT|SH3_BIT|SH2_BIT|SH3E_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT}, \ | |
180 | {"4-single", SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT},\ | |
181 | {"4", SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|HARD_SH4_BIT}, \ | |
c5d67833 JW |
182 | {"b", -LITTLE_ENDIAN_BIT}, \ |
183 | {"bigtable", BIGTABLE_BIT}, \ | |
184 | {"dalign", DALIGN_BIT}, \ | |
225e4f43 | 185 | {"fmovd", FMOVD_BIT}, \ |
c5d67833 | 186 | {"hitachi", HITACHI_BIT}, \ |
e9a25f70 | 187 | {"ieee", IEEE_BIT}, \ |
c5d67833 JW |
188 | {"isize", ISIZE_BIT}, \ |
189 | {"l", LITTLE_ENDIAN_BIT}, \ | |
e9a25f70 | 190 | {"no-ieee", -IEEE_BIT}, \ |
c5d67833 | 191 | {"padstruct", PADSTRUCT_BIT}, \ |
8b32b684 | 192 | {"relax", RELAX_BIT}, \ |
c5d67833 | 193 | {"space", SPACE_BIT}, \ |
5d84b57e | 194 | SUBTARGET_SWITCHES \ |
00f8ff66 | 195 | {"", TARGET_DEFAULT} \ |
bc45ade3 SC |
196 | } |
197 | ||
5d84b57e JS |
198 | /* This are meant to be redefined in the host dependent files */ |
199 | #define SUBTARGET_SWITCHES | |
200 | ||
058f9bb5 | 201 | #define TARGET_DEFAULT (0) |
00f8ff66 | 202 | |
04d02ece R |
203 | #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ |
204 | do { \ | |
225e4f43 R |
205 | if (LEVEL) \ |
206 | flag_omit_frame_pointer = -1; \ | |
207 | if (LEVEL) \ | |
208 | sh_flag_remove_dead_before_cse = 1; \ | |
04d02ece R |
209 | if (SIZE) \ |
210 | target_flags |= SPACE_BIT; \ | |
211 | } while (0) | |
212 | ||
225e4f43 R |
213 | #define ASSEMBLER_DIALECT assembler_dialect |
214 | ||
215 | extern int assembler_dialect; | |
216 | ||
217 | #define OVERRIDE_OPTIONS \ | |
218 | do { \ | |
219 | sh_cpu = CPU_SH1; \ | |
220 | assembler_dialect = 0; \ | |
221 | if (TARGET_SH2) \ | |
222 | sh_cpu = CPU_SH2; \ | |
223 | if (TARGET_SH3) \ | |
224 | sh_cpu = CPU_SH3; \ | |
225 | if (TARGET_SH3E) \ | |
226 | sh_cpu = CPU_SH3E; \ | |
227 | if (TARGET_SH4) \ | |
228 | { \ | |
229 | assembler_dialect = 1; \ | |
230 | sh_cpu = CPU_SH4; \ | |
231 | } \ | |
232 | if (! TARGET_SH4 || ! TARGET_FMOVD) \ | |
233 | { \ | |
234 | /* Prevent usage of explicit register names for variables \ | |
235 | for registers not present / not addressable in the \ | |
236 | target architecture. */ \ | |
237 | int regno; \ | |
238 | for (regno = (TARGET_SH3E) ? 17 : 0; \ | |
239 | regno <= 24; regno++) \ | |
240 | fp_reg_names[regno][0] = 0; \ | |
241 | } \ | |
242 | if (flag_omit_frame_pointer < 0) \ | |
243 | /* The debugging information is sufficient, \ | |
244 | but gdb doesn't implement this yet */ \ | |
245 | if (0) \ | |
246 | flag_omit_frame_pointer \ | |
247 | = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \ | |
248 | || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \ | |
249 | else \ | |
250 | flag_omit_frame_pointer = 0; \ | |
251 | \ | |
252 | /* Never run scheduling before reload, since that can \ | |
253 | break global alloc, and generates slower code anyway due \ | |
254 | to the pressure on R0. */ \ | |
255 | flag_schedule_insns = 0; \ | |
256 | sh_addr_diff_vec_mode = TARGET_BIGTABLE ? SImode : HImode; \ | |
0d7e008e | 257 | } while (0) |
bc45ade3 | 258 | \f |
c5d67833 | 259 | /* Target machine storage layout. */ |
bc45ade3 | 260 | |
b9654711 | 261 | /* Define to use software floating point emulator for REAL_ARITHMETIC and |
994295f2 | 262 | decimal <-> binary conversion. */ |
b9654711 SC |
263 | #define REAL_ARITHMETIC |
264 | ||
bc45ade3 SC |
265 | /* Define this if most significant bit is lowest numbered |
266 | in instructions that operate on numbered bit-fields. */ | |
00f8ff66 | 267 | |
bc45ade3 SC |
268 | #define BITS_BIG_ENDIAN 0 |
269 | ||
270 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
00f8ff66 | 271 | #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) |
bc45ade3 SC |
272 | |
273 | /* Define this if most significant word of a multiword number is the lowest | |
274 | numbered. */ | |
00f8ff66 SC |
275 | #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) |
276 | ||
00f8ff66 SC |
277 | /* Define this to set the endianness to use in libgcc2.c, which can |
278 | not depend on target_flags. */ | |
279 | #if defined(__LITTLE_ENDIAN__) | |
280 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
281 | #else | |
282 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
283 | #endif | |
bc45ade3 | 284 | |
994295f2 | 285 | /* Number of bits in an addressable storage unit. */ |
bc45ade3 SC |
286 | #define BITS_PER_UNIT 8 |
287 | ||
288 | /* Width in bits of a "word", which is the contents of a machine register. | |
289 | Note that this is not necessarily the width of data type `int'; | |
290 | if using 16-bit ints on a 68000, this would still be 32. | |
291 | But on a machine with 16-bit registers, this would be 16. */ | |
292 | #define BITS_PER_WORD 32 | |
293 | #define MAX_BITS_PER_WORD 32 | |
294 | ||
295 | /* Width of a word, in units (bytes). */ | |
296 | #define UNITS_PER_WORD 4 | |
297 | ||
298 | /* Width in bits of a pointer. | |
299 | See also the macro `Pmode' defined below. */ | |
300 | #define POINTER_SIZE 32 | |
301 | ||
302 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
303 | #define PARM_BOUNDARY 32 | |
304 | ||
305 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
3d5a0820 | 306 | #define STACK_BOUNDARY BIGGEST_ALIGNMENT |
bc45ade3 | 307 | |
e9a25f70 | 308 | /* The log (base 2) of the cache line size, in bytes. Processors prior to |
b4d34be1 R |
309 | SH2 have no actual cache, but they fetch code in chunks of 4 bytes. |
310 | The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */ | |
311 | #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2) | |
e9a25f70 | 312 | |
97b65a3e JW |
313 | /* Allocation boundary (in *bits*) for the code of a function. |
314 | 32 bit alignment is faster, because instructions are always fetched as a | |
315 | pair from a longword boundary. */ | |
e9a25f70 | 316 | #define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : (1 << CACHE_LOG) * 8) |
bc45ade3 SC |
317 | |
318 | /* Alignment of field after `int : 0' in a structure. */ | |
319 | #define EMPTY_FIELD_BOUNDARY 32 | |
320 | ||
321 | /* No data type wants to be aligned rounder than this. */ | |
322 | #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) | |
323 | ||
324 | /* The best alignment to use in cases where we have a choice. */ | |
325 | #define FASTEST_ALIGNMENT 32 | |
326 | ||
bc45ade3 | 327 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
c5d67833 | 328 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
bc45ade3 SC |
329 | ((TREE_CODE (EXP) == STRING_CST \ |
330 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
0d7e008e | 331 | ? FASTEST_ALIGNMENT : (ALIGN)) |
bc45ade3 | 332 | |
44ec7e59 CM |
333 | #ifndef MAX_OFILE_ALIGNMENT |
334 | #define MAX_OFILE_ALIGNMENT 128 | |
335 | #endif | |
336 | ||
bc45ade3 SC |
337 | /* Make arrays of chars word-aligned for the same reasons. */ |
338 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
339 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
340 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
341 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
342 | ||
8e87e161 SC |
343 | /* Number of bits which any structure or union's size must be a |
344 | multiple of. Each structure or union's size is rounded up to a | |
994295f2 | 345 | multiple of this. */ |
9791111f | 346 | #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8) |
8e87e161 | 347 | |
bc45ade3 SC |
348 | /* Set this nonzero if move instructions will actually fail to work |
349 | when given unaligned data. */ | |
350 | #define STRICT_ALIGNMENT 1 | |
33f7f353 JR |
351 | |
352 | /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */ | |
353 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \ | |
354 | barrier_align (LABEL_AFTER_BARRIER) | |
355 | ||
77008a44 | 356 | #define LOOP_ALIGN(A_LABEL) \ |
0aa54da2 | 357 | ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) ? 0 : 2) |
33f7f353 JR |
358 | |
359 | #define LABEL_ALIGN(A_LABEL) \ | |
360 | ( \ | |
361 | (PREV_INSN (A_LABEL) \ | |
362 | && GET_CODE (PREV_INSN (A_LABEL)) == INSN \ | |
363 | && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \ | |
364 | && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == 1) \ | |
365 | /* explicit alignment insn in constant tables. */ \ | |
366 | ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \ | |
367 | : 0) | |
368 | ||
369 | /* Jump tables must be 32 bit aligned, no matter the size of the element. */ | |
370 | #define ADDR_VEC_ALIGN(ADDR_VEC) 2 | |
371 | ||
372 | /* The base two logarithm of the known minimum alignment of an insn length. */ | |
373 | #define INSN_LENGTH_ALIGNMENT(A_INSN) \ | |
374 | (GET_CODE (A_INSN) == INSN \ | |
375 | ? 1 \ | |
376 | : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \ | |
377 | ? 1 \ | |
378 | : CACHE_LOG) | |
bc45ade3 SC |
379 | \f |
380 | /* Standard register usage. */ | |
381 | ||
0d7e008e | 382 | /* Register allocation for the Hitachi calling convention: |
bc45ade3 | 383 | |
0d7e008e SC |
384 | r0 arg return |
385 | r1..r3 scratch | |
c5d67833 | 386 | r4..r7 args in |
0d7e008e SC |
387 | r8..r13 call saved |
388 | r14 frame pointer/call saved | |
bc45ade3 SC |
389 | r15 stack pointer |
390 | ap arg pointer (doesn't really exist, always eliminated) | |
391 | pr subroutine return address | |
392 | t t bit | |
994295f2 | 393 | mach multiply/accumulate result, high part |
5c3ea805 JW |
394 | macl multiply/accumulate result, low part. |
395 | fpul fp/int communication register | |
d1405d89 | 396 | rap return address pointer register |
5c3ea805 JW |
397 | fr0 fp arg return |
398 | fr1..fr3 scratch floating point registers | |
399 | fr4..fr11 fp args in | |
400 | fr12..fr15 call saved floating point registers */ | |
bc45ade3 SC |
401 | |
402 | /* Number of actual hardware registers. | |
403 | The hardware registers are assigned numbers for the compiler | |
404 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
405 | All registers that the compiler knows about must be given numbers, | |
994295f2 | 406 | even those that are not normally considered general registers. */ |
bc45ade3 | 407 | |
994295f2 | 408 | #define AP_REG 16 |
bc45ade3 SC |
409 | #define PR_REG 17 |
410 | #define T_REG 18 | |
411 | #define GBR_REG 19 | |
412 | #define MACH_REG 20 | |
413 | #define MACL_REG 21 | |
058f9bb5 | 414 | #define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21) |
5c3ea805 | 415 | #define FPUL_REG 22 |
d1405d89 | 416 | #define RAP_REG 23 |
5c3ea805 JW |
417 | #define FIRST_FP_REG 24 |
418 | #define LAST_FP_REG 39 | |
225e4f43 R |
419 | #define FIRST_XD_REG 40 |
420 | #define LAST_XD_REG 47 | |
421 | #define FPSCR_REG 48 | |
bc45ade3 | 422 | |
225e4f43 | 423 | #define FIRST_PSEUDO_REGISTER 49 |
bc45ade3 SC |
424 | |
425 | /* 1 for registers that have pervasive standard uses | |
994295f2 | 426 | and are not available for the register allocator. |
d3ae8277 | 427 | |
97b65a3e JW |
428 | Mach register is fixed 'cause it's only 10 bits wide for SH1. |
429 | It is 32 bits wide for SH2. */ | |
d3ae8277 | 430 | |
0d7e008e SC |
431 | #define FIXED_REGISTERS \ |
432 | { 0, 0, 0, 0, \ | |
433 | 0, 0, 0, 0, \ | |
434 | 0, 0, 0, 0, \ | |
435 | 0, 0, 0, 1, \ | |
436 | 1, 1, 1, 1, \ | |
e9a25f70 JL |
437 | 1, 1, 0, 1, \ |
438 | 0, 0, 0, 0, \ | |
5c3ea805 JW |
439 | 0, 0, 0, 0, \ |
440 | 0, 0, 0, 0, \ | |
441 | 0, 0, 0, 0, \ | |
225e4f43 R |
442 | 0, 0, 0, 0, \ |
443 | 0, 0, 0, 0, \ | |
444 | 1, \ | |
5c3ea805 | 445 | } |
bc45ade3 SC |
446 | |
447 | /* 1 for registers not available across function calls. | |
448 | These must include the FIXED_REGISTERS and also any | |
449 | registers that can be used without being saved. | |
450 | The latter must include the registers where values are returned | |
451 | and the register where structure-value addresses are passed. | |
452 | Aside from that, you can include as many other registers as you like. */ | |
453 | ||
0d7e008e | 454 | #define CALL_USED_REGISTERS \ |
5c3ea805 JW |
455 | { 1, 1, 1, 1, \ |
456 | 1, 1, 1, 1, \ | |
457 | 0, 0, 0, 0, \ | |
458 | 0, 0, 0, 1, \ | |
459 | 1, 0, 1, 1, \ | |
460 | 1, 1, 1, 1, \ | |
461 | 1, 1, 1, 1, \ | |
462 | 1, 1, 1, 1, \ | |
463 | 1, 1, 1, 1, \ | |
e9a25f70 | 464 | 0, 0, 0, 0, \ |
225e4f43 R |
465 | 1, 1, 1, 1, \ |
466 | 1, 1, 0, 0, \ | |
467 | 1, \ | |
5c3ea805 | 468 | } |
bc45ade3 SC |
469 | |
470 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
471 | to hold something of mode MODE. | |
472 | This is ordinarily the length in words of a value of mode MODE | |
473 | but can be less for certain modes in special long registers. | |
474 | ||
225e4f43 | 475 | On the SH all but the XD regs are UNITS_PER_WORD bits wide. */ |
0d7e008e | 476 | |
c5d67833 | 477 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
225e4f43 R |
478 | ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG \ |
479 | ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \ | |
480 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \ | |
bc45ade3 SC |
481 | |
482 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
058f9bb5 JW |
483 | We can allow any mode in any general register. The special registers |
484 | only allow SImode. Don't allow any mode in the PR. */ | |
bc45ade3 | 485 | |
225e4f43 R |
486 | /* We cannot hold DCmode values in the XD registers because alter_reg |
487 | handles subregs of them incorrectly. We could work around this by | |
488 | spacing the XD registers like the DR registers, but this would require | |
489 | additional memory in every compilation to hold larger register vectors. | |
490 | We could hold SFmode / SCmode values in XD registers, but that | |
491 | would require a tertiary reload when reloading from / to memory, | |
492 | and a secondary reload to reload from / to general regs; that | |
493 | seems to be a loosing proposition. */ | |
c5d67833 | 494 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
058f9bb5 | 495 | (SPECIAL_REG (REGNO) ? (MODE) == SImode \ |
5c3ea805 | 496 | : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \ |
225e4f43 R |
497 | : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG && (MODE) == SFmode \ |
498 | ? 1 \ | |
499 | : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG \ | |
500 | ? ((MODE) == SFmode \ | |
501 | || (TARGET_SH3E && (MODE) == SCmode) \ | |
502 | || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode) \ | |
503 | && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \ | |
504 | : (REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG \ | |
505 | ? (MODE) == DFmode \ | |
058f9bb5 | 506 | : (REGNO) == PR_REG ? 0 \ |
225e4f43 | 507 | : (REGNO) == FPSCR_REG ? (MODE) == PSImode \ |
058f9bb5 | 508 | : 1) |
bc45ade3 SC |
509 | |
510 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
511 | when one has mode MODE1 and one has mode MODE2. | |
512 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
513 | for any hard reg, then this must be 0 for correct output. */ | |
514 | ||
515 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
516 | ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
517 | ||
518 | /* Specify the registers used for certain standard purposes. | |
519 | The values of these macros are register numbers. */ | |
520 | ||
521 | /* Define this if the program counter is overloaded on a register. */ | |
522 | /* #define PC_REGNUM 15*/ | |
523 | ||
524 | /* Register to use for pushing function arguments. */ | |
525 | #define STACK_POINTER_REGNUM 15 | |
526 | ||
527 | /* Base register for access to local variables of the function. */ | |
528 | #define FRAME_POINTER_REGNUM 14 | |
529 | ||
d1405d89 JW |
530 | /* Fake register that holds the address on the stack of the |
531 | current function's return address. */ | |
532 | #define RETURN_ADDRESS_POINTER_REGNUM 23 | |
533 | ||
bc45ade3 SC |
534 | /* Value should be nonzero if functions must have frame pointers. |
535 | Zero means the frame pointer need not be set up (and parms may be accessed | |
536 | via the stack pointer) in functions that seem suitable. */ | |
b9654711 | 537 | |
0d7e008e | 538 | #define FRAME_POINTER_REQUIRED 0 |
bc45ade3 SC |
539 | |
540 | /* Definitions for register eliminations. | |
541 | ||
cc27ef74 | 542 | We have three registers that can be eliminated on the SH. First, the |
bc45ade3 SC |
543 | frame pointer register can often be eliminated in favor of the stack |
544 | pointer register. Secondly, the argument pointer register can always be | |
cc27ef74 | 545 | eliminated; it is replaced with either the stack or frame pointer. |
956d6950 | 546 | Third, there is the return address pointer, which can also be replaced |
cc27ef74 | 547 | with either the stack or the frame pointer. */ |
bc45ade3 SC |
548 | |
549 | /* This is an array of structures. Each structure initializes one pair | |
550 | of eliminable registers. The "from" register number is given first, | |
551 | followed by "to". Eliminations of the same "from" register are listed | |
552 | in order of preference. */ | |
553 | ||
cc27ef74 JR |
554 | /* If you add any registers here that are not actually hard registers, |
555 | and that have any alternative of elimination that doesn't always | |
556 | apply, you need to amend calc_live_regs to exclude it, because | |
557 | reload spills all eliminable registers where it sees an | |
558 | can_eliminate == 0 entry, thus making them 'live' . | |
559 | If you add any hard registers that can be eliminated in different | |
560 | ways, you have to patch reload to spill them only when all alternatives | |
561 | of elimination fail. */ | |
562 | ||
d1405d89 JW |
563 | #define ELIMINABLE_REGS \ |
564 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
565 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
566 | { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ | |
567 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
568 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},} | |
bc45ade3 SC |
569 | |
570 | /* Given FROM and TO register numbers, say whether this elimination | |
571 | is allowed. */ | |
572 | #define CAN_ELIMINATE(FROM, TO) \ | |
573 | (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)) | |
574 | ||
575 | /* Define the offset between two registers, one to be eliminated, and the other | |
576 | its replacement, at the start of a routine. */ | |
577 | ||
578 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
e9a25f70 | 579 | OFFSET = initial_elimination_offset ((FROM), (TO)) |
bc45ade3 SC |
580 | |
581 | /* Base register for access to arguments of the function. */ | |
582 | #define ARG_POINTER_REGNUM 16 | |
583 | ||
584 | /* Register in which the static-chain is passed to a function. */ | |
585 | #define STATIC_CHAIN_REGNUM 13 | |
586 | ||
994295f2 | 587 | /* The register in which a struct value address is passed. */ |
b9654711 | 588 | |
0d7e008e SC |
589 | #define STRUCT_VALUE_REGNUM 2 |
590 | ||
591 | /* If the structure value address is not passed in a register, define | |
592 | `STRUCT_VALUE' as an expression returning an RTX for the place | |
593 | where the address is passed. If it returns 0, the address is | |
594 | passed as an "invisible" first argument. */ | |
595 | ||
596 | /*#define STRUCT_VALUE ((rtx)0)*/ | |
bc45ade3 | 597 | |
0d7e008e SC |
598 | /* Don't default to pcc-struct-return, because we have already specified |
599 | exactly how to return structures in the RETURN_IN_MEMORY macro. */ | |
600 | ||
601 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
bc45ade3 SC |
602 | \f |
603 | /* Define the classes of registers for register constraints in the | |
604 | machine description. Also define ranges of constants. | |
605 | ||
606 | One of the classes must always be named ALL_REGS and include all hard regs. | |
607 | If there is more than one class, another class must be named NO_REGS | |
608 | and contain no registers. | |
609 | ||
610 | The name GENERAL_REGS must be the name of a class (or an alias for | |
611 | another name such as ALL_REGS). This is the class of registers | |
612 | that is allowed by "g" or "r" in a register constraint. | |
613 | Also, registers outside this class are allocated only when | |
614 | instructions express preferences for them. | |
615 | ||
616 | The classes must be numbered in nondecreasing order; that is, | |
617 | a larger-numbered class must never be contained completely | |
618 | in a smaller-numbered class. | |
619 | ||
620 | For any two classes, it is very desirable that there be another | |
621 | class that represents their union. */ | |
622 | ||
994295f2 | 623 | /* The SH has two sorts of general registers, R0 and the rest. R0 can |
bc45ade3 SC |
624 | be used as the destination of some of the arithmetic ops. There are |
625 | also some special purpose registers; the T bit register, the | |
ddd5a7c1 | 626 | Procedure Return Register and the Multiply Accumulate Registers. */ |
e9a25f70 JL |
627 | /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by |
628 | reg_class_subunion. We don't want to have an actual union class | |
629 | of these, because it would only be used when both classes are calculated | |
630 | to give the same cost, but there is only one FPUL register. | |
631 | Besides, regclass fails to notice the different REGISTER_MOVE_COSTS | |
632 | applying to the actual instruction alternative considered. E.g., the | |
633 | y/r alternative of movsi_ie is considered to have no more cost that | |
634 | the r/r alternative, which is patently untrue. */ | |
bc45ade3 SC |
635 | |
636 | enum reg_class | |
637 | { | |
638 | NO_REGS, | |
639 | R0_REGS, | |
bc45ade3 SC |
640 | PR_REGS, |
641 | T_REGS, | |
642 | MAC_REGS, | |
5c3ea805 | 643 | FPUL_REGS, |
e9a25f70 | 644 | GENERAL_REGS, |
5c3ea805 JW |
645 | FP0_REGS, |
646 | FP_REGS, | |
225e4f43 R |
647 | DF_REGS, |
648 | FPSCR_REGS, | |
5c5eb4ef | 649 | GENERAL_FP_REGS, |
bc45ade3 SC |
650 | ALL_REGS, |
651 | LIM_REG_CLASSES | |
652 | }; | |
653 | ||
654 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
655 | ||
994295f2 | 656 | /* Give names of register classes as strings for dump file. */ |
c5d67833 | 657 | #define REG_CLASS_NAMES \ |
bc45ade3 SC |
658 | { \ |
659 | "NO_REGS", \ | |
660 | "R0_REGS", \ | |
bc45ade3 SC |
661 | "PR_REGS", \ |
662 | "T_REGS", \ | |
663 | "MAC_REGS", \ | |
5c3ea805 | 664 | "FPUL_REGS", \ |
e9a25f70 | 665 | "GENERAL_REGS", \ |
5c3ea805 JW |
666 | "FP0_REGS", \ |
667 | "FP_REGS", \ | |
225e4f43 R |
668 | "DF_REGS", \ |
669 | "FPSCR_REGS", \ | |
5c5eb4ef | 670 | "GENERAL_FP_REGS", \ |
bc45ade3 SC |
671 | "ALL_REGS", \ |
672 | } | |
673 | ||
674 | /* Define which registers fit in which classes. | |
675 | This is an initializer for a vector of HARD_REG_SET | |
676 | of length N_REG_CLASSES. */ | |
677 | ||
5c3ea805 JW |
678 | #define REG_CLASS_CONTENTS \ |
679 | { \ | |
680 | { 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
681 | { 0x00000001, 0x00000000 }, /* R0_REGS */ \ | |
682 | { 0x00020000, 0x00000000 }, /* PR_REGS */ \ | |
683 | { 0x00040000, 0x00000000 }, /* T_REGS */ \ | |
684 | { 0x00300000, 0x00000000 }, /* MAC_REGS */ \ | |
5c3ea805 | 685 | { 0x00400000, 0x00000000 }, /* FPUL_REGS */ \ |
e9a25f70 | 686 | { 0x0081FFFF, 0x00000000 }, /* GENERAL_REGS */ \ |
5c3ea805 JW |
687 | { 0x01000000, 0x00000000 }, /* FP0_REGS */ \ |
688 | { 0xFF000000, 0x000000FF }, /* FP_REGS */ \ | |
225e4f43 R |
689 | { 0xFF000000, 0x0000FFFF }, /* DF_REGS */ \ |
690 | { 0x00000000, 0x00010000 }, /* FPSCR_REGS */ \ | |
691 | { 0xFF81FFFF, 0x0000FFFF }, /* GENERAL_FP_REGS */ \ | |
692 | { 0xFFFFFFFF, 0x0001FFFF }, /* ALL_REGS */ \ | |
bc45ade3 SC |
693 | } |
694 | ||
695 | /* The same information, inverted: | |
696 | Return the class number of the smallest class containing | |
697 | reg number REGNO. This could be a conditional expression | |
698 | or could index an array. */ | |
699 | ||
700 | extern int regno_reg_class[]; | |
e9a25f70 | 701 | #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)] |
bc45ade3 | 702 | |
0d7e008e SC |
703 | /* When defined, the compiler allows registers explicitly used in the |
704 | rtl to be used as spill registers but prevents the compiler from | |
994295f2 | 705 | extending the lifetime of these registers. */ |
0d7e008e | 706 | |
2922fe9e | 707 | #define SMALL_REGISTER_CLASSES 1 |
0d7e008e | 708 | |
bc45ade3 | 709 | /* The order in which register should be allocated. */ |
e9a25f70 JL |
710 | /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo, |
711 | and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be | |
712 | spilled or used otherwise, we better have the FP_REGS allocated first. */ | |
c5d67833 | 713 | #define REG_ALLOC_ORDER \ |
e9a25f70 | 714 | { 25,26,27,28,29,30,31,24,32,33,34,35,36,37,38,39, \ |
225e4f43 | 715 | 40,41,42,43,44,45,46,47,48, \ |
e9a25f70 | 716 | 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14, \ |
5c3ea805 | 717 | 22,15,16,17,18,19,20,21,23 } |
bc45ade3 SC |
718 | |
719 | /* The class value for index registers, and the one for base regs. */ | |
720 | #define INDEX_REG_CLASS R0_REGS | |
721 | #define BASE_REG_CLASS GENERAL_REGS | |
722 | ||
994295f2 JW |
723 | /* Get reg_class from a letter such as appears in the machine |
724 | description. */ | |
bc45ade3 SC |
725 | extern enum reg_class reg_class_from_letter[]; |
726 | ||
727 | #define REG_CLASS_FROM_LETTER(C) \ | |
728 | ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS ) | |
c5d67833 | 729 | \f |
bc45ade3 SC |
730 | /* The letters I, J, K, L and M in a register constraint string |
731 | can be used to stand for particular ranges of immediate operands. | |
732 | This macro defines what the ranges are. | |
733 | C is the letter, and VALUE is a constant value. | |
734 | Return 1 if VALUE is in the range specified by C. | |
735 | I: arithmetic operand -127..128, as used in add, sub, etc | |
b52cd365 | 736 | K: shift operand 1,2,8 or 16 |
b9654711 | 737 | L: logical operand 0..255, as used in and, or, etc. |
bc45ade3 | 738 | M: constant 1 |
b52cd365 | 739 | N: constant 0 */ |
bc45ade3 | 740 | |
679dcddb R |
741 | #define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \ |
742 | && ((HOST_WIDE_INT)(VALUE)) <= 127) | |
b52cd365 | 743 | #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16) |
679dcddb R |
744 | #define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \ |
745 | && ((HOST_WIDE_INT)(VALUE)) <= 255) | |
bc45ade3 | 746 | #define CONST_OK_FOR_M(VALUE) ((VALUE)==1) |
0d7e008e | 747 | #define CONST_OK_FOR_N(VALUE) ((VALUE)==0) |
c5d67833 JW |
748 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
749 | ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \ | |
750 | : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \ | |
751 | : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \ | |
752 | : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \ | |
753 | : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \ | |
bc45ade3 SC |
754 | : 0) |
755 | ||
756 | /* Similar, but for floating constants, and defining letters G and H. | |
757 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
758 | ||
5c3ea805 JW |
759 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ |
760 | ((C) == 'G' ? fp_zero_operand (VALUE) \ | |
761 | : (C) == 'H' ? fp_one_operand (VALUE) \ | |
b1bbe732 | 762 | : (C) == 'F') |
5c3ea805 | 763 | |
bc45ade3 SC |
764 | /* Given an rtx X being reloaded into a reg required to be |
765 | in class CLASS, return the class of reg to actually use. | |
766 | In general this is just CLASS; but on some machines | |
767 | in some cases it is preferable to use a more restrictive class. */ | |
768 | ||
e9a25f70 | 769 | #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) |
bc45ade3 | 770 | |
0f68f06b | 771 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ |
225e4f43 R |
772 | ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \ |
773 | || (CLASS) == DF_REGS) \ | |
e9a25f70 JL |
774 | && (GET_CODE (X) == REG && REGNO (X) <= AP_REG)) \ |
775 | || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \ | |
776 | && GET_CODE (X) == REG \ | |
777 | && REGNO (X) >= FIRST_FP_REG && REGNO (X) <= LAST_FP_REG)) \ | |
778 | && MODE == SFmode) \ | |
779 | ? FPUL_REGS \ | |
780 | : ((CLASS) == FPUL_REGS \ | |
781 | && (GET_CODE (X) == MEM \ | |
225e4f43 | 782 | || (GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER)))\ |
e9a25f70 JL |
783 | ? GENERAL_REGS \ |
784 | : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \ | |
785 | && GET_CODE (X) == REG && REGNO (X) > 15 \ | |
786 | && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \ | |
787 | ? GENERAL_REGS : NO_REGS) | |
0f68f06b JR |
788 | |
789 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \ | |
225e4f43 | 790 | ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS) \ |
e9a25f70 | 791 | && immediate_operand ((X), (MODE)) \ |
225e4f43 R |
792 | && ! ((fp_zero_operand (X) || fp_one_operand (X)) && (MODE) == SFmode))\ |
793 | ? R0_REGS \ | |
794 | : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \ | |
795 | ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \ | |
796 | ? GENERAL_REGS \ | |
797 | : R0_REGS) \ | |
798 | : (CLASS == FPSCR_REGS \ | |
799 | && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
800 | || GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)) \ | |
801 | ? GENERAL_REGS \ | |
802 | : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X))) | |
0f68f06b | 803 | |
bc45ade3 | 804 | /* Return the maximum number of consecutive registers |
994295f2 | 805 | needed to represent mode MODE in a register of class CLASS. |
bc45ade3 | 806 | |
994295f2 | 807 | On SH this is the size of MODE in words. */ |
c5d67833 | 808 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
bc45ade3 | 809 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
225e4f43 R |
810 | |
811 | /* If defined, gives a class of registers that cannot be used as the | |
812 | operand of a SUBREG that changes the size of the object. */ | |
813 | ||
814 | #define CLASS_CANNOT_CHANGE_SIZE DF_REGS | |
bc45ade3 SC |
815 | \f |
816 | /* Stack layout; function entry, exit and calling. */ | |
817 | ||
c5d67833 | 818 | /* Define the number of registers that can hold parameters. |
5c3ea805 JW |
819 | These macros are used only in other macro definitions below. */ |
820 | ||
821 | #define NPARM_REGS(MODE) \ | |
e9a25f70 JL |
822 | (TARGET_SH3E && (MODE) == SFmode \ |
823 | ? 8 \ | |
225e4f43 R |
824 | : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
825 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ | |
826 | ? 8 \ | |
e9a25f70 | 827 | : 4) |
5c3ea805 | 828 | |
bc45ade3 | 829 | #define FIRST_PARM_REG 4 |
97b65a3e | 830 | #define FIRST_RET_REG 0 |
bc45ade3 | 831 | |
5c3ea805 JW |
832 | #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4) |
833 | #define FIRST_FP_RET_REG FIRST_FP_REG | |
834 | ||
bc45ade3 SC |
835 | /* Define this if pushing a word on the stack |
836 | makes the stack pointer a smaller address. */ | |
994295f2 | 837 | #define STACK_GROWS_DOWNWARD |
bc45ade3 | 838 | |
0d7e008e SC |
839 | /* Define this macro if the addresses of local variable slots are at |
840 | negative offsets from the frame pointer. | |
bc45ade3 | 841 | |
994295f2 | 842 | The SH only has positive indexes, so grow the frame up. */ |
0d7e008e SC |
843 | /* #define FRAME_GROWS_DOWNWARD */ |
844 | ||
845 | /* Offset from the frame pointer to the first local variable slot to | |
994295f2 | 846 | be allocated. */ |
bc45ade3 SC |
847 | #define STARTING_FRAME_OFFSET 0 |
848 | ||
849 | /* If we generate an insn to push BYTES bytes, | |
850 | this says how many the stack pointer really advances by. */ | |
e9a25f70 JL |
851 | /* Don't define PUSH_ROUNDING, since the hardware doesn't do this. |
852 | When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to | |
853 | do correct alignment. */ | |
854 | #if 0 | |
bc45ade3 | 855 | #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) |
e9a25f70 | 856 | #endif |
bc45ade3 SC |
857 | |
858 | /* Offset of first parameter from the argument pointer register value. */ | |
859 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
860 | ||
861 | /* Value is the number of byte of arguments automatically | |
862 | popped when returning from a subroutine call. | |
8b109b37 | 863 | FUNDECL is the declaration node of the function (as a tree), |
bc45ade3 SC |
864 | FUNTYPE is the data type of the function (as a tree), |
865 | or for a library call it is an identifier node for the subroutine name. | |
866 | SIZE is the number of bytes of arguments passed on the stack. | |
867 | ||
868 | On the SH, the caller does not pop any of its arguments that were passed | |
869 | on the stack. */ | |
8b109b37 | 870 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
bc45ade3 | 871 | |
97e3c422 R |
872 | /* Nonzero if we do not know how to pass TYPE solely in registers. |
873 | Values that come in registers with inconvenient padding are stored | |
874 | to memory at the function start. */ | |
875 | ||
876 | #define MUST_PASS_IN_STACK(MODE,TYPE) \ | |
877 | ((TYPE) != 0 \ | |
878 | && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ | |
879 | || TREE_ADDRESSABLE (TYPE))) | |
5c3ea805 JW |
880 | /* Some subroutine macros specific to this machine. */ |
881 | ||
882 | #define BASE_RETURN_VALUE_REG(MODE) \ | |
883 | ((TARGET_SH3E && ((MODE) == SFmode)) \ | |
884 | ? FIRST_FP_RET_REG \ | |
225e4f43 R |
885 | : TARGET_SH3E && (MODE) == SCmode \ |
886 | ? FIRST_FP_RET_REG \ | |
887 | : (TARGET_SH4 \ | |
888 | && ((MODE) == DFmode || (MODE) == SFmode \ | |
889 | || (MODE) == DCmode || (MODE) == SCmode )) \ | |
890 | ? FIRST_FP_RET_REG \ | |
5c3ea805 JW |
891 | : FIRST_RET_REG) |
892 | ||
893 | #define BASE_ARG_REG(MODE) \ | |
894 | ((TARGET_SH3E && ((MODE) == SFmode)) \ | |
895 | ? FIRST_FP_PARM_REG \ | |
225e4f43 R |
896 | : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
897 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\ | |
898 | ? FIRST_FP_PARM_REG \ | |
5c3ea805 JW |
899 | : FIRST_PARM_REG) |
900 | ||
bc45ade3 SC |
901 | /* Define how to find the value returned by a function. |
902 | VALTYPE is the data type of the value (as a tree). | |
903 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
225e4f43 R |
904 | otherwise, FUNC is 0. |
905 | For the SH, this is like LIBCALL_VALUE, except that we must change the | |
906 | mode like PROMOTE_MODE does. | |
907 | ??? PROMOTE_MODE is ignored for non-scalar types. The set of types | |
908 | tested here has to be kept in sync with the one in explow.c:promote_mode. */ | |
909 | ||
910 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
911 | gen_rtx (REG, \ | |
912 | ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \ | |
913 | && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \ | |
914 | && (TREE_CODE (VALTYPE) == INTEGER_TYPE \ | |
915 | || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \ | |
916 | || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \ | |
917 | || TREE_CODE (VALTYPE) == CHAR_TYPE \ | |
918 | || TREE_CODE (VALTYPE) == REAL_TYPE \ | |
919 | || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \ | |
920 | ? SImode : TYPE_MODE (VALTYPE)), \ | |
921 | BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE))) | |
5c3ea805 | 922 | |
bc45ade3 SC |
923 | /* Define how to find the value returned by a library function |
924 | assuming the value has mode MODE. */ | |
5c3ea805 | 925 | #define LIBCALL_VALUE(MODE) \ |
c5c76735 | 926 | gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE)); |
bc45ade3 | 927 | |
5c3ea805 JW |
928 | /* 1 if N is a possible register number for a function value. */ |
929 | #define FUNCTION_VALUE_REGNO_P(REGNO) \ | |
58b57c2c | 930 | ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG)) |
bc45ade3 | 931 | |
994295f2 | 932 | /* 1 if N is a possible register number for function argument passing. */ |
c5d67833 | 933 | #define FUNCTION_ARG_REGNO_P(REGNO) \ |
e9a25f70 JL |
934 | (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG + 4)) \ |
935 | || (TARGET_SH3E \ | |
58b57c2c | 936 | && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG + 8))) |
bc45ade3 SC |
937 | \f |
938 | /* Define a data type for recording info about an argument list | |
939 | during the scan of that argument list. This data type should | |
940 | hold all necessary information about the function itself | |
941 | and about the args processed so far, enough to enable macros | |
942 | such as FUNCTION_ARG to determine where the next arg should go. | |
943 | ||
944 | On SH, this is a single integer, which is a number of words | |
945 | of arguments scanned so far (including the invisible argument, | |
946 | if any, which holds the structure-value-address). | |
947 | Thus NARGREGS or more means all following args should go on the stack. */ | |
948 | ||
5c3ea805 JW |
949 | enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 }; |
950 | struct sh_args { | |
951 | int arg_count[2]; | |
952 | }; | |
953 | ||
954 | #define CUMULATIVE_ARGS struct sh_args | |
955 | ||
956 | #define GET_SH_ARG_CLASS(MODE) \ | |
225e4f43 R |
957 | ((TARGET_SH3E && (MODE) == SFmode) \ |
958 | ? SH_ARG_FLOAT \ | |
959 | : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
960 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ | |
961 | ? SH_ARG_FLOAT : SH_ARG_INT) | |
bc45ade3 | 962 | |
c5d67833 | 963 | #define ROUND_ADVANCE(SIZE) \ |
e9a25f70 | 964 | (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
bc45ade3 | 965 | |
994295f2 JW |
966 | /* Round a register number up to a proper boundary for an arg of mode |
967 | MODE. | |
968 | ||
d3ae8277 | 969 | The SH doesn't care about double alignment, so we only |
994295f2 | 970 | round doubles to even regs when asked to explicitly. */ |
bc45ade3 | 971 | |
5c3ea805 | 972 | #define ROUND_REG(CUM, MODE) \ |
225e4f43 R |
973 | (((TARGET_ALIGN_DOUBLE \ |
974 | || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \ | |
975 | && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\ | |
5c3ea805 JW |
976 | && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ |
977 | ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \ | |
978 | + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \ | |
979 | : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)]) | |
bc45ade3 | 980 | |
bc45ade3 SC |
981 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
982 | for a call to a function whose data type is FNTYPE. | |
983 | For a library call, FNTYPE is 0. | |
984 | ||
985 | On SH, the offset always starts at 0: the first parm reg is always | |
e9a25f70 | 986 | the same reg for a given argument class. */ |
bc45ade3 | 987 | |
2c7ee1a6 | 988 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ |
5c3ea805 JW |
989 | do { \ |
990 | (CUM).arg_count[(int) SH_ARG_INT] = 0; \ | |
991 | (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \ | |
992 | } while (0) | |
bc45ade3 SC |
993 | |
994 | /* Update the data in CUM to advance over an argument | |
995 | of mode MODE and data type TYPE. | |
996 | (TYPE is null for libcalls where that information may not be | |
997 | available.) */ | |
998 | ||
999 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
225e4f43 R |
1000 | if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \ |
1001 | ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \ | |
1002 | = (ROUND_REG ((CUM), (MODE)) \ | |
1003 | + ((MODE) == BLKmode \ | |
1004 | ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ | |
1005 | : ROUND_ADVANCE (GET_MODE_SIZE (MODE))))) | |
bc45ade3 | 1006 | |
5c3ea805 JW |
1007 | /* Return boolean indicating arg of mode MODE will be passed in a reg. |
1008 | This macro is only used in this file. */ | |
1009 | ||
1010 | #define PASS_IN_REG_P(CUM, MODE, TYPE) \ | |
9ab70a9b R |
1011 | (((TYPE) == 0 \ |
1012 | || (! TREE_ADDRESSABLE ((tree)(TYPE))) \ | |
1013 | && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE))) \ | |
1245df60 R |
1014 | && (TARGET_SH3E \ |
1015 | ? ((MODE) == BLKmode \ | |
1016 | ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \ | |
1017 | + int_size_in_bytes (TYPE)) \ | |
1018 | <= NPARM_REGS (SImode) * UNITS_PER_WORD) \ | |
1019 | : ((ROUND_REG((CUM), (MODE)) \ | |
1020 | + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \ | |
1021 | <= NPARM_REGS (MODE))) \ | |
1022 | : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE))) | |
5c3ea805 | 1023 | |
bc45ade3 SC |
1024 | /* Define where to put the arguments to a function. |
1025 | Value is zero to push the argument on the stack, | |
1026 | or a hard register in which to store the argument. | |
1027 | ||
1028 | MODE is the argument's machine mode. | |
1029 | TYPE is the data type of the argument (as a tree). | |
1030 | This is null for libcalls where that information may | |
1031 | not be available. | |
1032 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1033 | the preceding args and about the function being called. | |
1034 | NAMED is nonzero if this argument is a named parameter | |
1035 | (otherwise it is an extra parameter matching an ellipsis). | |
1036 | ||
1037 | On SH the first args are normally in registers | |
1038 | and the rest are pushed. Any arg that starts within the first | |
1039 | NPARM_REGS words is at least partially passed in a register unless | |
1040 | its data type forbids. */ | |
1041 | ||
d3ae8277 | 1042 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
e9a25f70 | 1043 | ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ |
9ab70a9b R |
1044 | && ((NAMED) \ |
1045 | || (! TARGET_HITACHI && (TARGET_SH3E || ! current_function_varargs)))) \ | |
c5c76735 JL |
1046 | ? gen_rtx_REG ((MODE), \ |
1047 | ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \ | |
1048 | ^ ((MODE) == SFmode && TARGET_SH4 \ | |
1049 | && TARGET_LITTLE_ENDIAN != 0))) \ | |
5c3ea805 | 1050 | : 0) |
bc45ade3 | 1051 | |
9ab70a9b R |
1052 | #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI) |
1053 | ||
bc45ade3 SC |
1054 | /* For an arg passed partly in registers and partly in memory, |
1055 | this is the number of registers used. | |
1056 | For args passed entirely in registers or entirely in memory, zero. | |
994295f2 JW |
1057 | |
1058 | We sometimes split args. */ | |
0d7e008e | 1059 | |
d3ae8277 | 1060 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
5c3ea805 | 1061 | ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ |
225e4f43 | 1062 | && ! TARGET_SH4 \ |
5c3ea805 | 1063 | && (ROUND_REG ((CUM), (MODE)) \ |
225e4f43 | 1064 | + ((MODE) != BLKmode \ |
5c3ea805 JW |
1065 | ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \ |
1066 | : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \ | |
1067 | - NPARM_REGS (MODE) > 0)) \ | |
1068 | ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \ | |
1069 | : 0) | |
bc45ade3 SC |
1070 | |
1071 | extern int current_function_anonymous_args; | |
1072 | ||
1073 | /* Perform any needed actions needed for a function that is receiving a | |
994295f2 | 1074 | variable number of arguments. */ |
bc45ade3 SC |
1075 | |
1076 | #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \ | |
1077 | current_function_anonymous_args = 1; | |
1078 | ||
1bad666c JW |
1079 | /* Call the function profiler with a given profile label. |
1080 | We use two .aligns, so as to make sure that both the .long is aligned | |
1081 | on a 4 byte boundary, and that the .long is a fixed distance (2 bytes) | |
1082 | from the trapa instruction. */ | |
bc45ade3 | 1083 | |
b9654711 SC |
1084 | #define FUNCTION_PROFILER(STREAM,LABELNO) \ |
1085 | { \ | |
e9a25f70 JL |
1086 | fprintf((STREAM), "\t.align\t2\n"); \ |
1087 | fprintf((STREAM), "\ttrapa\t#33\n"); \ | |
1088 | fprintf((STREAM), "\t.align\t2\n"); \ | |
1089 | asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ | |
bc45ade3 SC |
1090 | } |
1091 | ||
d59c4c8e JW |
1092 | /* Define this macro if the code for function profiling should come |
1093 | before the function prologue. Normally, the profiling code comes | |
1094 | after. */ | |
1095 | ||
1096 | #define PROFILE_BEFORE_PROLOGUE | |
1097 | ||
bc45ade3 SC |
1098 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1099 | the stack pointer does not matter. The value is tested only in | |
1100 | functions that have frame pointers. | |
1101 | No definition is equivalent to always zero. */ | |
1102 | ||
4fdd1f85 | 1103 | #define EXIT_IGNORE_STACK 1 |
bc45ade3 | 1104 | |
994295f2 JW |
1105 | /* Generate the assembly code for function exit |
1106 | Just dump out any accumulated constant table. */ | |
bc45ade3 | 1107 | |
e9a25f70 | 1108 | #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue ((STREAM), (SIZE)) |
bc45ade3 | 1109 | |
e9a25f70 | 1110 | /* |
ddd5a7c1 | 1111 | On the SH, the trampoline looks like |
bc45ade3 | 1112 | 2 0002 DD02 mov.l l2,r13 |
e9a25f70 | 1113 | 1 0000 D301 mov.l l1,r3 |
bc45ade3 | 1114 | 3 0004 4D2B jmp @r13 |
e9a25f70 | 1115 | 4 0006 0009 nop |
bc45ade3 | 1116 | 5 0008 00000000 l1: .long function |
994295f2 | 1117 | 6 000c 00000000 l2: .long area */ |
bc45ade3 SC |
1118 | |
1119 | /* Length in units of the trampoline for entering a nested function. */ | |
1120 | #define TRAMPOLINE_SIZE 16 | |
1121 | ||
e9a25f70 JL |
1122 | /* Alignment required for a trampoline in bits . */ |
1123 | #define TRAMPOLINE_ALIGNMENT \ | |
0aa54da2 | 1124 | ((CACHE_LOG < 3 || TARGET_SMALLCODE && ! TARGET_HARVARD) ? 32 : 64) |
bc45ade3 SC |
1125 | |
1126 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1127 | FNADDR is an RTX for the address of the function's pure code. | |
1128 | CXT is an RTX for the static chain value for the function. */ | |
1129 | ||
c5d67833 | 1130 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
bc45ade3 | 1131 | { \ |
c5c76735 | 1132 | emit_move_insn (gen_rtx_MEM (SImode, (TRAMP)), \ |
e9a25f70 | 1133 | GEN_INT (TARGET_LITTLE_ENDIAN ? 0xd301dd02 : 0xdd02d301));\ |
c5c76735 | 1134 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 4)), \ |
e9a25f70 | 1135 | GEN_INT (TARGET_LITTLE_ENDIAN ? 0x00094d2b : 0x4d2b0009));\ |
c5c76735 | 1136 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \ |
bc45ade3 | 1137 | (CXT)); \ |
c5c76735 | 1138 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \ |
bc45ade3 | 1139 | (FNADDR)); \ |
0aa54da2 | 1140 | if (TARGET_HARVARD) \ |
225e4f43 | 1141 | emit_insn (gen_ic_invalidate_line (TRAMP)); \ |
bc45ade3 | 1142 | } |
d1405d89 JW |
1143 | |
1144 | /* A C expression whose value is RTL representing the value of the return | |
1145 | address for the frame COUNT steps up from the current frame. | |
1146 | FRAMEADDR is already the frame pointer of the COUNT frame, so we | |
1147 | can ignore COUNT. */ | |
1148 | ||
1149 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
e9a25f70 | 1150 | (((COUNT) == 0) \ |
c5c76735 | 1151 | ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM)) \ |
d1405d89 | 1152 | : (rtx) 0) |
bc45ade3 | 1153 | \f |
648d2ffc | 1154 | /* Generate necessary RTL for __builtin_saveregs(). */ |
5c3ea805 | 1155 | extern struct rtx_def *sh_builtin_saveregs (); |
648d2ffc | 1156 | #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs () |
5c3ea805 | 1157 | \f |
bc45ade3 | 1158 | /* Addressing modes, and classification of registers for them. */ |
d3ae8277 | 1159 | #define HAVE_POST_INCREMENT 1 |
bc45ade3 SC |
1160 | /*#define HAVE_PRE_INCREMENT 1*/ |
1161 | /*#define HAVE_POST_DECREMENT 1*/ | |
d3ae8277 | 1162 | #define HAVE_PRE_DECREMENT 1 |
bc45ade3 | 1163 | |
fbe1758d AM |
1164 | #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \ |
1165 | ? 0 : 1) | |
1166 | #define USE_LOAD_PRE_DECREMENT(mode) 0 | |
1167 | #define USE_STORE_POST_INCREMENT(mode) 0 | |
1168 | #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \ | |
1169 | ? 0 : 1) | |
1170 | ||
1171 | #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \ | |
1172 | < (TARGET_SMALLCODE ? 2 : \ | |
1173 | ((ALIGN >= 4) ? 16 : 2))) | |
1174 | ||
bc45ade3 SC |
1175 | /* Macros to check register numbers against specific register classes. */ |
1176 | ||
1177 | /* These assume that REGNO is a hard or pseudo reg number. | |
1178 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1179 | or a pseudo reg currently allocated to a suitable hard reg. | |
1180 | Since they use reg_renumber, they are safe only once reg_renumber | |
994295f2 | 1181 | has been allocated, which happens in local-alloc.c. */ |
0d7e008e | 1182 | |
c5d67833 | 1183 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
bc45ade3 | 1184 | ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG) |
c5d67833 | 1185 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
0d7e008e | 1186 | ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0) |
bc45ade3 | 1187 | |
994295f2 JW |
1188 | /* Maximum number of registers that can appear in a valid memory |
1189 | address. */ | |
bc45ade3 | 1190 | |
0d7e008e | 1191 | #define MAX_REGS_PER_ADDRESS 2 |
bc45ade3 SC |
1192 | |
1193 | /* Recognize any constant value that is a valid address. */ | |
1194 | ||
c5d67833 | 1195 | #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) |
bc45ade3 | 1196 | |
994295f2 | 1197 | /* Nonzero if the constant value X is a legitimate general operand. */ |
bc45ade3 | 1198 | |
5c3ea805 JW |
1199 | #define LEGITIMATE_CONSTANT_P(X) \ |
1200 | (GET_CODE (X) != CONST_DOUBLE \ | |
b1bbe732 | 1201 | || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \ |
5c3ea805 | 1202 | || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X)))) |
bc45ade3 | 1203 | |
bc45ade3 SC |
1204 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1205 | and check its validity for a certain class. | |
1206 | We have two alternate definitions for each of them. | |
1207 | The usual definition accepts all pseudo regs; the other rejects | |
1208 | them unless they have been allocated suitable hard regs. | |
1209 | The symbol REG_OK_STRICT causes the latter definition to be used. */ | |
1210 | ||
1211 | #ifndef REG_OK_STRICT | |
b9654711 | 1212 | |
bc45ade3 SC |
1213 | /* Nonzero if X is a hard reg that can be used as a base reg |
1214 | or if it is a pseudo reg. */ | |
1215 | #define REG_OK_FOR_BASE_P(X) \ | |
53c8870f | 1216 | (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c5d67833 | 1217 | |
bc45ade3 SC |
1218 | /* Nonzero if X is a hard reg that can be used as an index |
1219 | or if it is a pseudo reg. */ | |
1220 | #define REG_OK_FOR_INDEX_P(X) \ | |
53c8870f RK |
1221 | (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1222 | ||
1223 | /* Nonzero if X/OFFSET is a hard reg that can be used as an index | |
1224 | or if X is a pseudo reg. */ | |
1225 | #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \ | |
1226 | ((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
b9654711 | 1227 | |
bc45ade3 | 1228 | #else |
c5d67833 | 1229 | |
bc45ade3 | 1230 | /* Nonzero if X is a hard reg that can be used as a base reg. */ |
c5d67833 | 1231 | #define REG_OK_FOR_BASE_P(X) \ |
53c8870f | 1232 | REGNO_OK_FOR_BASE_P (REGNO (X)) |
b9654711 | 1233 | |
bc45ade3 | 1234 | /* Nonzero if X is a hard reg that can be used as an index. */ |
c5d67833 | 1235 | #define REG_OK_FOR_INDEX_P(X) \ |
53c8870f RK |
1236 | REGNO_OK_FOR_INDEX_P (REGNO (X)) |
1237 | ||
1238 | /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */ | |
1239 | #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \ | |
e9a25f70 | 1240 | (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0) |
b9654711 | 1241 | |
bc45ade3 | 1242 | #endif |
0d7e008e | 1243 | |
c5d67833 | 1244 | /* The 'Q' constraint is a pc relative load operand. */ |
06c386ea SC |
1245 | #define EXTRA_CONSTRAINT_Q(OP) \ |
1246 | (GET_CODE (OP) == MEM && \ | |
e9a25f70 JL |
1247 | ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \ |
1248 | || (GET_CODE (XEXP ((OP), 0)) == CONST \ | |
1249 | && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \ | |
1250 | && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \ | |
1251 | && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT))) | |
0d7e008e | 1252 | |
c5d67833 JW |
1253 | #define EXTRA_CONSTRAINT(OP, C) \ |
1254 | ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \ | |
1255 | : 0) | |
bc45ade3 SC |
1256 | \f |
1257 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1258 | that is a valid memory address for an instruction. | |
1259 | The MODE argument is the machine mode for the MEM expression | |
1260 | that wants to use this address. | |
1261 | ||
1262 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ | |
b9654711 | 1263 | |
5c3ea805 JW |
1264 | #define MODE_DISP_OK_4(X,MODE) \ |
1265 | (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \ | |
e9a25f70 | 1266 | && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode)) |
225e4f43 R |
1267 | |
1268 | #define MODE_DISP_OK_8(X,MODE) \ | |
1269 | ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \ | |
1270 | && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode)) | |
5a463884 | 1271 | |
c5d67833 JW |
1272 | #define BASE_REGISTER_RTX_P(X) \ |
1273 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
1274 | || (GET_CODE (X) == SUBREG \ | |
1275 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
1276 | && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) | |
bc45ade3 | 1277 | |
53c8870f RK |
1278 | /* Since this must be r0, which is a single register class, we must check |
1279 | SUBREGs more carefully, to be sure that we don't accept one that extends | |
1280 | outside the class. */ | |
c5d67833 JW |
1281 | #define INDEX_REGISTER_RTX_P(X) \ |
1282 | ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ | |
1283 | || (GET_CODE (X) == SUBREG \ | |
1284 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
53c8870f | 1285 | && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X)))) |
bc45ade3 SC |
1286 | |
1287 | /* Jump to LABEL if X is a valid address RTX. This must also take | |
1288 | REG_OK_STRICT into account when deciding about valid registers, but it uses | |
994295f2 JW |
1289 | the above macros so we are in luck. |
1290 | ||
bc45ade3 SC |
1291 | Allow REG |
1292 | REG+disp | |
1293 | REG+r0 | |
1294 | REG++ | |
994295f2 | 1295 | --REG */ |
bc45ade3 | 1296 | |
5c3ea805 JW |
1297 | /* ??? The SH3e does not have the REG+disp addressing mode when loading values |
1298 | into the FRx registers. We implement this by setting the maximum offset | |
1299 | to zero when the value is SFmode. This also restricts loading of SFmode | |
1300 | values into the integer registers, but that can't be helped. */ | |
1301 | ||
994295f2 | 1302 | /* The SH allows a displacement in a QI or HI amode, but only when the |
b9654711 SC |
1303 | other operand is R0. GCC doesn't handle this very well, so we forgo |
1304 | all of that. | |
1305 | ||
c5d67833 JW |
1306 | A legitimate index for a QI or HI is 0, SI can be any number 0..63, |
1307 | DI can be any number 0..60. */ | |
bc45ade3 | 1308 | |
c5d67833 | 1309 | #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \ |
0d7e008e SC |
1310 | do { \ |
1311 | if (GET_CODE (OP) == CONST_INT) \ | |
1312 | { \ | |
e9a25f70 JL |
1313 | if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \ |
1314 | if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \ | |
0d7e008e | 1315 | } \ |
bc45ade3 SC |
1316 | } while(0) |
1317 | ||
c5d67833 JW |
1318 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ |
1319 | { \ | |
1320 | if (BASE_REGISTER_RTX_P (X)) \ | |
1321 | goto LABEL; \ | |
1322 | else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ | |
e9a25f70 | 1323 | && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \ |
c5d67833 | 1324 | goto LABEL; \ |
225e4f43 R |
1325 | else if (GET_CODE (X) == PLUS \ |
1326 | && ((MODE) != PSImode || reload_completed)) \ | |
c5d67833 | 1327 | { \ |
e9a25f70 JL |
1328 | rtx xop0 = XEXP ((X), 0); \ |
1329 | rtx xop1 = XEXP ((X), 1); \ | |
c5d67833 | 1330 | if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \ |
e9a25f70 | 1331 | GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \ |
225e4f43 R |
1332 | if (GET_MODE_SIZE (MODE) <= 4 \ |
1333 | || TARGET_SH4 && TARGET_FMOVD && MODE == DFmode) \ | |
c5d67833 JW |
1334 | { \ |
1335 | if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\ | |
1336 | goto LABEL; \ | |
1337 | if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\ | |
1338 | goto LABEL; \ | |
1339 | } \ | |
1340 | } \ | |
994295f2 JW |
1341 | } |
1342 | \f | |
1343 | /* Try machine-dependent ways of modifying an illegitimate address | |
bc45ade3 SC |
1344 | to be legitimate. If we find one, return the new, valid address. |
1345 | This macro is used in only one place: `memory_address' in explow.c. | |
1346 | ||
1347 | OLDX is the address as it was before break_out_memory_refs was called. | |
1348 | In some cases it is useful to look at this to decide what needs to be done. | |
1349 | ||
1350 | MODE and WIN are passed so that this macro can use | |
1351 | GO_IF_LEGITIMATE_ADDRESS. | |
1352 | ||
1353 | It is always safe for this macro to do nothing. It exists to recognize | |
a73a5114 | 1354 | opportunities to optimize the output. |
bc45ade3 | 1355 | |
a73a5114 JW |
1356 | For the SH, if X is almost suitable for indexing, but the offset is |
1357 | out of range, convert it into a normal form so that cse has a chance | |
1358 | of reducing the number of address registers used. */ | |
1359 | ||
1360 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1361 | { \ | |
55ebdce3 | 1362 | if (GET_CODE (X) == PLUS \ |
a73a5114 JW |
1363 | && (GET_MODE_SIZE (MODE) == 4 \ |
1364 | || GET_MODE_SIZE (MODE) == 8) \ | |
e9a25f70 JL |
1365 | && GET_CODE (XEXP ((X), 1)) == CONST_INT \ |
1366 | && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \ | |
225e4f43 | 1367 | && ! (TARGET_SH4 && (MODE) == DFmode) \ |
e9a25f70 | 1368 | && ! (TARGET_SH3E && (MODE) == SFmode)) \ |
a73a5114 | 1369 | { \ |
e9a25f70 | 1370 | rtx index_rtx = XEXP ((X), 1); \ |
a73a5114 JW |
1371 | HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \ |
1372 | rtx sum; \ | |
1373 | \ | |
e9a25f70 | 1374 | GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \ |
24f72d76 | 1375 | /* On rare occasions, we might get an unaligned pointer \ |
a73a5114 JW |
1376 | that is indexed in a way to give an aligned address. \ |
1377 | Therefore, keep the lower two bits in offset_base. */ \ | |
1378 | /* Instead of offset_base 128..131 use 124..127, so that \ | |
1379 | simple add suffices. */ \ | |
1380 | if (offset > 127) \ | |
1381 | { \ | |
1382 | offset_base = ((offset + 4) & ~60) - 4; \ | |
1383 | } \ | |
1384 | else \ | |
1385 | offset_base = offset & ~60; \ | |
1386 | /* Sometimes the normal form does not suit DImode. We \ | |
1387 | could avoid that by using smaller ranges, but that \ | |
55ebdce3 | 1388 | would give less optimized code when SImode is \ |
a73a5114 JW |
1389 | prevalent. */ \ |
1390 | if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \ | |
1391 | { \ | |
e9a25f70 | 1392 | sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \ |
a73a5114 JW |
1393 | GEN_INT (offset_base), NULL_RTX, 0, \ |
1394 | OPTAB_LIB_WIDEN); \ | |
1395 | \ | |
c5c76735 | 1396 | (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \ |
a73a5114 JW |
1397 | goto WIN; \ |
1398 | } \ | |
1399 | } \ | |
1400 | } | |
bc45ade3 | 1401 | |
ef41dabb R |
1402 | /* A C compound statement that attempts to replace X, which is an address |
1403 | that needs reloading, with a valid memory address for an operand of | |
1404 | mode MODE. WIN is a C statement label elsewhere in the code. | |
1405 | ||
1406 | Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form | |
1407 | of the address. That will allow inheritance of the address reloads. */ | |
1408 | ||
1409 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
1410 | { \ | |
1411 | if (GET_CODE (X) == PLUS \ | |
1412 | && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \ | |
1413 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1414 | && BASE_REGISTER_RTX_P (XEXP (X, 0)) \ | |
225e4f43 R |
1415 | && ! (TARGET_SH4 && (MODE) == DFmode) \ |
1416 | && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \ | |
ef41dabb R |
1417 | { \ |
1418 | rtx index_rtx = XEXP (X, 1); \ | |
1419 | HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \ | |
1420 | rtx sum; \ | |
1421 | \ | |
225e4f43 R |
1422 | if (TARGET_SH3E && MODE == SFmode) \ |
1423 | { \ | |
1424 | X = copy_rtx (X); \ | |
1425 | push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL_PTR, \ | |
1426 | INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \ | |
1427 | (TYPE)); \ | |
1428 | goto WIN; \ | |
1429 | } \ | |
ef41dabb R |
1430 | /* Instead of offset_base 128..131 use 124..127, so that \ |
1431 | simple add suffices. */ \ | |
1432 | if (offset > 127) \ | |
1433 | { \ | |
1434 | offset_base = ((offset + 4) & ~60) - 4; \ | |
1435 | } \ | |
1436 | else \ | |
1437 | offset_base = offset & ~60; \ | |
1438 | /* Sometimes the normal form does not suit DImode. We \ | |
1439 | could avoid that by using smaller ranges, but that \ | |
1440 | would give less optimized code when SImode is \ | |
1441 | prevalent. */ \ | |
1442 | if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \ | |
1443 | { \ | |
1444 | sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ | |
1445 | GEN_INT (offset_base)); \ | |
1446 | X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\ | |
1447 | push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL_PTR, \ | |
1448 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \ | |
1449 | (TYPE)); \ | |
1450 | goto WIN; \ | |
1451 | } \ | |
1452 | } \ | |
1453 | /* We must re-recognize what we created before. */ \ | |
1454 | else if (GET_CODE (X) == PLUS \ | |
1455 | && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \ | |
1456 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
1457 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ | |
1458 | && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \ | |
1459 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1460 | && ! (TARGET_SH3E && MODE == SFmode)) \ | |
1461 | { \ | |
1462 | /* Because this address is so complex, we know it must have \ | |
1463 | been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \ | |
1464 | it is already unshared, and needs no further unsharing. */ \ | |
1465 | push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL_PTR, \ | |
1466 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\ | |
1467 | goto WIN; \ | |
1468 | } \ | |
1469 | } | |
1470 | ||
bc45ade3 | 1471 | /* Go to LABEL if ADDR (a legitimate address expression) |
e9a25f70 JL |
1472 | has an effect that depends on the machine mode it is used for. |
1473 | ||
1474 | ??? Strictly speaking, we should also include all indexed addressing, | |
1475 | because the index scale factor is the length of the operand. | |
1476 | However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to | |
1477 | high if we did that. So we rely on reload to fix things up. */ | |
1478 | ||
c5d67833 | 1479 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ |
bc45ade3 | 1480 | { \ |
c5d67833 | 1481 | if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \ |
bc45ade3 SC |
1482 | goto LABEL; \ |
1483 | } | |
1484 | \f | |
1485 | /* Specify the machine mode that this machine uses | |
1486 | for the index in the tablejump instruction. */ | |
0d7e008e | 1487 | #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode) |
bc45ade3 | 1488 | |
33f7f353 JR |
1489 | #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ |
1490 | ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \ | |
33f7f353 | 1491 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ |
64ad9df2 R |
1492 | : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ |
1493 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ | |
33f7f353 JR |
1494 | : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \ |
1495 | : SImode) | |
1496 | ||
18543a22 ILT |
1497 | /* Define as C expression which evaluates to nonzero if the tablejump |
1498 | instruction expects the table to contain offsets from the address of the | |
1499 | table. | |
1500 | Do not define this if the table should contain absolute addresses. */ | |
1501 | #define CASE_VECTOR_PC_RELATIVE 1 | |
bc45ade3 SC |
1502 | |
1503 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1504 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1505 | ||
1506 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1507 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1508 | ||
5c3ea805 JW |
1509 | /* Since the SH3e has only `float' support, it is desirable to make all |
1510 | floating point types equivalent to `float'. */ | |
225e4f43 | 1511 | #define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64) |
5c3ea805 | 1512 | |
994295f2 | 1513 | /* 'char' is signed by default. */ |
bc45ade3 SC |
1514 | #define DEFAULT_SIGNED_CHAR 1 |
1515 | ||
1516 | /* The type of size_t unsigned int. */ | |
1517 | #define SIZE_TYPE "unsigned int" | |
1518 | ||
8e87e161 SC |
1519 | #define WCHAR_TYPE "short unsigned int" |
1520 | #define WCHAR_TYPE_SIZE 16 | |
1521 | ||
bc45ade3 | 1522 | /* Don't cse the address of the function being compiled. */ |
0d7e008e | 1523 | /*#define NO_RECURSIVE_FUNCTION_CSE 1*/ |
bc45ade3 SC |
1524 | |
1525 | /* Max number of bytes we can move from memory to memory | |
1526 | in one reasonably fast instruction. */ | |
1527 | #define MOVE_MAX 4 | |
1528 | ||
fbe1758d AM |
1529 | /* Max number of bytes we want move_by_pieces to be able to copy |
1530 | efficiently. */ | |
1531 | #define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4) | |
1532 | ||
9a63901f RK |
1533 | /* Define if operations between registers always perform the operation |
1534 | on the full register even if a narrower mode is specified. */ | |
1535 | #define WORD_REGISTER_OPERATIONS | |
1536 | ||
1537 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1538 | will either zero-extend or sign-extend. The value of this macro should | |
1539 | be the code that says which one of the two operations is implicitly | |
1540 | done, NIL if none. */ | |
1541 | #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND | |
bc45ade3 | 1542 | |
211a0f85 JW |
1543 | /* Define if loading short immediate values into registers sign extends. */ |
1544 | #define SHORT_IMMEDIATES_SIGN_EXTEND | |
1545 | ||
bc45ade3 | 1546 | /* Define this if zero-extension is slow (more than one real instruction). |
994295f2 | 1547 | On the SH, it's only one instruction. */ |
bc45ade3 SC |
1548 | /* #define SLOW_ZERO_EXTEND */ |
1549 | ||
9a5bb317 R |
1550 | /* Nonzero if access to memory by bytes is no faster than for words. */ |
1551 | #define SLOW_BYTE_ACCESS 1 | |
1552 | ||
1553 | /* Force sizeof(bool) == 1 to maintain binary compatibility; otherwise, the | |
1554 | change in SLOW_BYTE_ACCESS would have changed it to 4. */ | |
1555 | ||
1556 | #define BOOL_TYPE_SIZE (flag_new_abi ? INT_TYPE_SIZE : CHAR_TYPE_SIZE) | |
bc45ade3 SC |
1557 | |
1558 | /* We assume that the store-condition-codes instructions store 0 for false | |
1559 | and some other value for true. This is the value stored for true. */ | |
1560 | ||
1561 | #define STORE_FLAG_VALUE 1 | |
1562 | ||
1563 | /* Immediate shift counts are truncated by the output routines (or was it | |
97b65a3e | 1564 | the assembler?). Shift counts in a register are truncated by SH. Note |
bc45ade3 | 1565 | that the native compiler puts too large (> 32) immediate shift counts |
97b65a3e | 1566 | into a register and shifts by the register, letting the SH decide what |
bc45ade3 | 1567 | to do instead of doing that itself. */ |
e9a25f70 JL |
1568 | /* ??? The library routines in lib1funcs.asm truncate the shift count. |
1569 | However, the SH3 has hardware shifts that do not truncate exactly as gcc | |
1570 | expects - the sign bit is significant - so it appears that we need to | |
1571 | leave this zero for correct SH3 code. */ | |
1572 | #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3) | |
bc45ade3 | 1573 | |
bc45ade3 SC |
1574 | /* All integers have the same format so truncation is easy. */ |
1575 | #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 | |
1576 | ||
1577 | /* Define this if addresses of constant functions | |
1578 | shouldn't be put through pseudo regs where they can be cse'd. | |
1579 | Desirable on machines where ordinary constants are expensive | |
1580 | but a CALL with constant address is cheap. */ | |
1581 | /*#define NO_FUNCTION_CSE 1*/ | |
1582 | ||
1583 | /* Chars and shorts should be passed as ints. */ | |
1584 | #define PROMOTE_PROTOTYPES 1 | |
1585 | ||
994295f2 | 1586 | /* The machine modes of pointers and functions. */ |
bc45ade3 SC |
1587 | #define Pmode SImode |
1588 | #define FUNCTION_MODE Pmode | |
1589 | ||
bc45ade3 SC |
1590 | /* The relative costs of various types of constants. Note that cse.c defines |
1591 | REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ | |
1592 | ||
c5d67833 | 1593 | #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ |
bc45ade3 | 1594 | case CONST_INT: \ |
97b65a3e JW |
1595 | if (INTVAL (RTX) == 0) \ |
1596 | return 0; \ | |
1597 | else if (CONST_OK_FOR_I (INTVAL (RTX))) \ | |
1598 | return 1; \ | |
e9a25f70 | 1599 | else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \ |
97b65a3e | 1600 | && CONST_OK_FOR_L (INTVAL (RTX))) \ |
bc45ade3 SC |
1601 | return 1; \ |
1602 | else \ | |
b9654711 | 1603 | return 8; \ |
bc45ade3 SC |
1604 | case CONST: \ |
1605 | case LABEL_REF: \ | |
1606 | case SYMBOL_REF: \ | |
b9654711 | 1607 | return 5; \ |
bc45ade3 SC |
1608 | case CONST_DOUBLE: \ |
1609 | return 10; | |
1610 | ||
1611 | #define RTX_COSTS(X, CODE, OUTER_CODE) \ | |
225e4f43 R |
1612 | case PLUS: \ |
1613 | return (COSTS_N_INSNS (1) \ | |
1614 | + rtx_cost (XEXP ((X), 0), PLUS) \ | |
1615 | + (rtx_equal_p (XEXP ((X), 0), XEXP ((X), 1))\ | |
1616 | ? 0 : rtx_cost (XEXP ((X), 1), PLUS)));\ | |
0d7e008e | 1617 | case AND: \ |
c5d67833 | 1618 | return COSTS_N_INSNS (andcosts (X)); \ |
bc45ade3 | 1619 | case MULT: \ |
b9654711 SC |
1620 | return COSTS_N_INSNS (multcosts (X)); \ |
1621 | case ASHIFT: \ | |
1622 | case ASHIFTRT: \ | |
994295f2 | 1623 | case LSHIFTRT: \ |
225e4f43 R |
1624 | /* Add one extra unit for the matching constraint. \ |
1625 | Otherwise loop strength reduction would think that\ | |
1626 | a shift with different sourc and destination is \ | |
1627 | as cheap as adding a constant to a register. */ \ | |
1628 | return (COSTS_N_INSNS (shiftcosts (X)) \ | |
1629 | + rtx_cost (XEXP ((X), 0), (CODE)) \ | |
1630 | + 1); \ | |
bc45ade3 SC |
1631 | case DIV: \ |
1632 | case UDIV: \ | |
1633 | case MOD: \ | |
1634 | case UMOD: \ | |
00f8ff66 | 1635 | return COSTS_N_INSNS (20); \ |
bc45ade3 SC |
1636 | case FLOAT: \ |
1637 | case FIX: \ | |
1638 | return 100; | |
1639 | ||
97b65a3e JW |
1640 | /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2 |
1641 | are actually function calls with some special constraints on arguments | |
1642 | and register usage. | |
0d7e008e | 1643 | |
994295f2 JW |
1644 | These macros tell reorg that the references to arguments and |
1645 | register clobbers for insns of type sfunc do not appear to happen | |
0d7e008e SC |
1646 | until after the millicode call. This allows reorg to put insns |
1647 | which set the argument registers into the delay slot of the millicode | |
1648 | call -- thus they act more like traditional CALL_INSNs. | |
1649 | ||
0603a39d | 1650 | get_attr_is_sfunc will try to recognize the given insn, so make sure to |
0d7e008e SC |
1651 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns |
1652 | in particular. */ | |
1653 | ||
1654 | #define INSN_SETS_ARE_DELAYED(X) \ | |
1655 | ((GET_CODE (X) == INSN \ | |
1656 | && GET_CODE (PATTERN (X)) != SEQUENCE \ | |
1657 | && GET_CODE (PATTERN (X)) != USE \ | |
1658 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
0603a39d | 1659 | && get_attr_is_sfunc (X))) |
0d7e008e SC |
1660 | |
1661 | #define INSN_REFERENCES_ARE_DELAYED(X) \ | |
1662 | ((GET_CODE (X) == INSN \ | |
1663 | && GET_CODE (PATTERN (X)) != SEQUENCE \ | |
1664 | && GET_CODE (PATTERN (X)) != USE \ | |
1665 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
0603a39d | 1666 | && get_attr_is_sfunc (X))) |
0d7e008e | 1667 | |
06ada9d1 JW |
1668 | /* Compute the cost of an address. For the SH, all valid addresses are |
1669 | the same cost. */ | |
1670 | /* ??? Perhaps we should make reg+reg addresses have higher cost because | |
1671 | they add to register pressure on r0. */ | |
1672 | ||
1673 | #define ADDRESS_COST(RTX) 1 | |
1674 | ||
bc45ade3 | 1675 | /* Compute extra cost of moving data between one register class |
e9a25f70 | 1676 | and another. */ |
bc45ade3 | 1677 | |
225e4f43 R |
1678 | /* Regclass always uses 2 for moves in the same register class; |
1679 | If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, | |
1680 | it uses this information. Hence, the general register <-> floating point | |
1681 | register information here is not used for SFmode. */ | |
c5d67833 | 1682 | #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \ |
225e4f43 R |
1683 | ((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REG)) ? 10 \ |
1684 | : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS || (DSTCLASS) == DF_REGS) \ | |
1685 | && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \ | |
1686 | || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \ | |
1687 | && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \ | |
1688 | || (SRCCLASS) == DF_REGS))) \ | |
1689 | ? TARGET_FMOVD ? 8 : 12 \ | |
1690 | : (((DSTCLASS) == FPUL_REGS \ | |
1691 | && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \ | |
1692 | || (SRCCLASS == FPUL_REGS \ | |
1693 | && ((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS))) \ | |
1694 | ? 5 \ | |
1695 | : (((DSTCLASS) == FPUL_REGS \ | |
1696 | && ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS)) \ | |
1697 | || ((SRCCLASS) == FPUL_REGS \ | |
1698 | && ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \ | |
1699 | ? 7 \ | |
1700 | : 2) | |
85256f8a JW |
1701 | |
1702 | /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This | |
ec4c28e5 | 1703 | would be so that people with slow memory systems could generate |
85256f8a | 1704 | different code that does fewer memory accesses. */ |
ec4c28e5 R |
1705 | |
1706 | /* A C expression for the cost of a branch instruction. A value of 1 | |
1707 | is the default; other values are interpreted relative to that. | |
1708 | The SH1 does not have delay slots, hence we get a pipeline stall | |
1709 | at every branch. The SH4 is superscalar, so the single delay slot | |
7df87939 | 1710 | is not sufficient to keep both pipelines filled. */ |
ec4c28e5 | 1711 | #define BRANCH_COST (! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1) |
bc45ade3 | 1712 | \f |
994295f2 | 1713 | /* Assembler output control. */ |
bc45ade3 | 1714 | |
17b65371 DE |
1715 | /* A C string constant describing how to begin a comment in the target |
1716 | assembler language. The compiler assumes that the comment will end at | |
1717 | the end of the line. */ | |
1718 | #define ASM_COMMENT_START "!" | |
1719 | ||
994295f2 | 1720 | /* The text to go at the start of the assembler file. */ |
17b65371 DE |
1721 | #define ASM_FILE_START(STREAM) \ |
1722 | output_file_start (STREAM) | |
bc45ade3 | 1723 | |
994295f2 | 1724 | #define ASM_FILE_END(STREAM) |
bc45ade3 | 1725 | |
0d7e008e SC |
1726 | #define ASM_APP_ON "" |
1727 | #define ASM_APP_OFF "" | |
1728 | #define FILE_ASM_OP "\t.file\n" | |
1729 | #define IDENT_ASM_OP "\t.ident\n" | |
6303b9ba | 1730 | #define SET_ASM_OP ".set" |
bc45ade3 | 1731 | |
994295f2 | 1732 | /* How to change between sections. */ |
bc45ade3 | 1733 | |
8e87e161 SC |
1734 | #define TEXT_SECTION_ASM_OP "\t.text" |
1735 | #define DATA_SECTION_ASM_OP "\t.data" | |
8e87e161 SC |
1736 | #define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n" |
1737 | #define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n" | |
06c386ea | 1738 | #define EXTRA_SECTIONS in_ctors, in_dtors |
c5d67833 JW |
1739 | #define EXTRA_SECTION_FUNCTIONS \ |
1740 | void \ | |
1741 | ctors_section() \ | |
1742 | { \ | |
1743 | if (in_section != in_ctors) \ | |
1744 | { \ | |
1745 | fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \ | |
1746 | in_section = in_ctors; \ | |
1747 | } \ | |
1748 | } \ | |
1749 | void \ | |
1750 | dtors_section() \ | |
1751 | { \ | |
1752 | if (in_section != in_dtors) \ | |
1753 | { \ | |
1754 | fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \ | |
1755 | in_section = in_dtors; \ | |
1756 | } \ | |
994295f2 | 1757 | } |
b9654711 | 1758 | |
48b1580e VM |
1759 | /* If defined, a C expression whose value is a string containing the |
1760 | assembler operation to identify the following data as | |
1761 | uninitialized global data. If not defined, and neither | |
1762 | `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined, | |
1763 | uninitialized global data will be output in the data section if | |
1764 | `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be | |
1765 | used. */ | |
1766 | #ifndef BSS_SECTION_ASM_OP | |
1767 | #define BSS_SECTION_ASM_OP ".section\t.bss" | |
1768 | #endif | |
1769 | ||
1770 | /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a | |
1771 | separate, explicit argument. If you define this macro, it is used | |
1772 | in place of `ASM_OUTPUT_BSS', and gives you more flexibility in | |
1773 | handling the required alignment of the variable. The alignment is | |
1774 | specified as the number of bits. | |
1775 | ||
1776 | Try to use function `asm_output_aligned_bss' defined in file | |
1777 | `varasm.c' when defining this macro. */ | |
1778 | #ifndef ASM_OUTPUT_ALIGNED_BSS | |
1779 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
1780 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
1781 | #endif | |
1782 | ||
e115e436 JW |
1783 | /* Define this so that jump tables go in same section as the current function, |
1784 | which could be text or it could be a user defined section. */ | |
75197b37 | 1785 | #define JUMP_TABLES_IN_TEXT_SECTION 1 |
e115e436 | 1786 | |
7e7be9c3 DE |
1787 | /* A C statement to output something to the assembler file to switch to section |
1788 | NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or | |
1789 | NULL_TREE. Some target formats do not support arbitrary sections. Do not | |
1790 | define this macro in such cases. */ | |
d3ae8277 | 1791 | |
ad4ff310 | 1792 | #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \ |
d3ae8277 SC |
1793 | do { fprintf (FILE, ".section\t%s\n", NAME); } while (0) |
1794 | ||
c5d67833 | 1795 | #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ |
e9a25f70 | 1796 | do { ctors_section(); asm_fprintf((FILE),"\t.long\t%U%s\n", (NAME)); } while (0) |
b9654711 | 1797 | |
c5d67833 | 1798 | #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ |
e9a25f70 | 1799 | do { dtors_section(); asm_fprintf((FILE),"\t.long\t%U%s\n", (NAME)); } while (0) |
b9654711 | 1800 | |
994295f2 | 1801 | #undef DO_GLOBAL_CTORS_BODY |
0d7e008e | 1802 | |
b9654711 SC |
1803 | #define DO_GLOBAL_CTORS_BODY \ |
1804 | { \ | |
1805 | typedef (*pfunc)(); \ | |
1806 | extern pfunc __ctors[]; \ | |
1807 | extern pfunc __ctors_end[]; \ | |
1808 | pfunc *p; \ | |
c1fe41cb | 1809 | for (p = __ctors_end; p > __ctors; ) \ |
b9654711 | 1810 | { \ |
c1fe41cb | 1811 | (*--p)(); \ |
b9654711 | 1812 | } \ |
994295f2 | 1813 | } |
b9654711 | 1814 | |
994295f2 | 1815 | #undef DO_GLOBAL_DTORS_BODY |
c5d67833 | 1816 | #define DO_GLOBAL_DTORS_BODY \ |
b9654711 SC |
1817 | { \ |
1818 | typedef (*pfunc)(); \ | |
1819 | extern pfunc __dtors[]; \ | |
1820 | extern pfunc __dtors_end[]; \ | |
1821 | pfunc *p; \ | |
1822 | for (p = __dtors; p < __dtors_end; p++) \ | |
1823 | { \ | |
1824 | (*p)(); \ | |
1825 | } \ | |
994295f2 | 1826 | } |
b9654711 | 1827 | |
b9654711 | 1828 | #define ASM_OUTPUT_REG_PUSH(file, v) \ |
e9a25f70 | 1829 | fprintf ((file), "\tmov.l\tr%s,-@r15\n", (v)); |
bc45ade3 | 1830 | |
b9654711 | 1831 | #define ASM_OUTPUT_REG_POP(file, v) \ |
e9a25f70 | 1832 | fprintf ((file), "\tmov.l\t@r15+,r%s\n", (v)); |
b9654711 | 1833 | |
bc45ade3 SC |
1834 | /* The assembler's names for the registers. RFP need not always be used as |
1835 | the Real framepointer; it can also be used as a normal general register. | |
1836 | Note that the name `fp' is horribly misleading since `fp' is in fact only | |
1837 | the argument-and-return-context pointer. */ | |
225e4f43 R |
1838 | |
1839 | extern char fp_reg_names[][5]; | |
1840 | ||
bc45ade3 | 1841 | #define REGISTER_NAMES \ |
225e4f43 R |
1842 | { \ |
1843 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
1844 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
1845 | "ap", "pr", "t", "gbr", "mach","macl", fp_reg_names[16], "rap", \ | |
1846 | fp_reg_names[0], fp_reg_names[1] , fp_reg_names[2], fp_reg_names[3], \ | |
1847 | fp_reg_names[4], fp_reg_names[5], fp_reg_names[6], fp_reg_names[7], \ | |
1848 | fp_reg_names[8], fp_reg_names[9], fp_reg_names[10], fp_reg_names[11], \ | |
1849 | fp_reg_names[12], fp_reg_names[13], fp_reg_names[14], fp_reg_names[15], \ | |
1850 | fp_reg_names[17], fp_reg_names[18], fp_reg_names[19], fp_reg_names[20], \ | |
1851 | fp_reg_names[21], fp_reg_names[22], fp_reg_names[23], fp_reg_names[24], \ | |
1852 | "fpscr", \ | |
1853 | } | |
1854 | ||
1855 | #define DEBUG_REGISTER_NAMES \ | |
bc45ade3 SC |
1856 | { \ |
1857 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
1858 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
d1405d89 | 1859 | "ap", "pr", "t", "gbr", "mach","macl", "fpul","rap", \ |
5c3ea805 JW |
1860 | "fr0","fr1","fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \ |
1861 | "fr8","fr9","fr10","fr11","fr12","fr13","fr14","fr15",\ | |
225e4f43 R |
1862 | "xd0","xd2","xd4", "xd6", "xd8", "xd10","xd12","xd14", \ |
1863 | "fpscr", \ | |
bc45ade3 SC |
1864 | } |
1865 | ||
994295f2 | 1866 | /* DBX register number for a given compiler register number. */ |
5c3ea805 JW |
1867 | /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers |
1868 | to match gdb. */ | |
1869 | #define DBX_REGISTER_NUMBER(REGNO) \ | |
1870 | (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO)) | |
bc45ade3 SC |
1871 | |
1872 | /* Output a label definition. */ | |
c5d67833 | 1873 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ |
e9a25f70 | 1874 | do { assemble_name ((FILE), (NAME)); fputs (":\n", (FILE)); } while (0) |
bc45ade3 | 1875 | |
bc45ade3 SC |
1876 | /* This is how to output an assembler line |
1877 | that says to advance the location counter | |
1878 | to a multiple of 2**LOG bytes. */ | |
1879 | ||
1880 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1881 | if ((LOG) != 0) \ | |
e9a25f70 | 1882 | fprintf ((FILE), "\t.align %d\n", (LOG)) |
bc45ade3 SC |
1883 | |
1884 | /* Output a function label definition. */ | |
1885 | #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ | |
e9a25f70 | 1886 | ASM_OUTPUT_LABEL((STREAM), (NAME)) |
bc45ade3 SC |
1887 | |
1888 | /* Output a globalising directive for a label. */ | |
c5d67833 | 1889 | #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ |
e9a25f70 JL |
1890 | (fprintf ((STREAM), "\t.global\t"), \ |
1891 | assemble_name ((STREAM), (NAME)), \ | |
1892 | fputc ('\n', (STREAM))) | |
bc45ade3 | 1893 | |
4e0c8ad2 RK |
1894 | /* The prefix to add to user-visible assembler symbols. */ |
1895 | ||
1896 | #define USER_LABEL_PREFIX "_" | |
bc45ade3 | 1897 | |
e9a25f70 JL |
1898 | /* The prefix to add to an internally generated label. */ |
1899 | ||
1900 | #define LOCAL_LABEL_PREFIX "" | |
1901 | ||
bc45ade3 | 1902 | /* Make an internal label into a string. */ |
c5d67833 | 1903 | #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ |
e9a25f70 | 1904 | sprintf ((STRING), "*%s%s%d", LOCAL_LABEL_PREFIX, (PREFIX), (NUM)) |
bc45ade3 SC |
1905 | |
1906 | /* Output an internal label definition. */ | |
c5d67833 | 1907 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ |
e9a25f70 | 1908 | asm_fprintf ((FILE), "%L%s%d:\n", (PREFIX), (NUM)) |
bc45ade3 | 1909 | |
bc45ade3 SC |
1910 | /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ |
1911 | ||
1912 | /* Construct a private name. */ | |
c5d67833 JW |
1913 | #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \ |
1914 | ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \ | |
bc45ade3 SC |
1915 | sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER))) |
1916 | ||
994295f2 | 1917 | /* Output a relative address table. */ |
bc1ebe63 | 1918 | |
33f7f353 JR |
1919 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ |
1920 | switch (GET_MODE (BODY)) \ | |
e9a25f70 JL |
1921 | { \ |
1922 | case SImode: \ | |
1923 | asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \ | |
1924 | break; \ | |
1925 | case HImode: \ | |
1926 | asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \ | |
1927 | break; \ | |
1928 | case QImode: \ | |
1929 | asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \ | |
1930 | break; \ | |
1931 | } | |
bc45ade3 | 1932 | |
994295f2 | 1933 | /* Output an absolute table element. */ |
0d7e008e SC |
1934 | |
1935 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ | |
1936 | if (TARGET_BIGTABLE) \ | |
e9a25f70 | 1937 | asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \ |
0d7e008e | 1938 | else \ |
e9a25f70 | 1939 | asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); \ |
bc45ade3 SC |
1940 | |
1941 | /* Output various types of constants. */ | |
1942 | ||
994295f2 | 1943 | /* This is how to output an assembler line defining a `double'. */ |
bc45ade3 | 1944 | |
b9654711 SC |
1945 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ |
1946 | do { char dstr[30]; \ | |
1947 | REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ | |
e9a25f70 | 1948 | fprintf ((FILE), "\t.double %s\n", dstr); \ |
b9654711 SC |
1949 | } while (0) |
1950 | ||
bc45ade3 | 1951 | /* This is how to output an assembler line defining a `float' constant. */ |
c5d67833 | 1952 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ |
b9654711 SC |
1953 | do { char dstr[30]; \ |
1954 | REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ | |
e9a25f70 | 1955 | fprintf ((FILE), "\t.float %s\n", dstr); \ |
b9654711 | 1956 | } while (0) |
bc45ade3 | 1957 | |
e9a25f70 JL |
1958 | #define ASM_OUTPUT_INT(STREAM, EXP) \ |
1959 | (fprintf ((STREAM), "\t.long\t"), \ | |
1960 | output_addr_const ((STREAM), (EXP)), \ | |
1961 | fputc ('\n', (STREAM))) | |
bc45ade3 | 1962 | |
c5d67833 | 1963 | #define ASM_OUTPUT_SHORT(STREAM, EXP) \ |
e9a25f70 JL |
1964 | (fprintf ((STREAM), "\t.short\t"), \ |
1965 | output_addr_const ((STREAM), (EXP)), \ | |
1966 | fputc ('\n', (STREAM))) | |
bc45ade3 | 1967 | |
e9a25f70 JL |
1968 | #define ASM_OUTPUT_CHAR(STREAM, EXP) \ |
1969 | (fprintf ((STREAM), "\t.byte\t"), \ | |
1970 | output_addr_const ((STREAM), (EXP)), \ | |
1971 | fputc ('\n', (STREAM))) | |
bc45ade3 SC |
1972 | |
1973 | #define ASM_OUTPUT_BYTE(STREAM, VALUE) \ | |
e9a25f70 | 1974 | fprintf ((STREAM), "\t.byte\t%d\n", (VALUE)) \ |
bc45ade3 | 1975 | |
e9a25f70 JL |
1976 | /* The next two are used for debug info when compiling with -gdwarf. */ |
1977 | #define UNALIGNED_SHORT_ASM_OP ".uaword" | |
1978 | #define UNALIGNED_INT_ASM_OP ".ualong" | |
446b03af | 1979 | |
e9a25f70 JL |
1980 | /* Loop alignment is now done in machine_dependent_reorg, so that |
1981 | branch shortening can know about it. */ | |
446b03af | 1982 | |
bc45ade3 SC |
1983 | /* This is how to output an assembler line |
1984 | that says to advance the location counter by SIZE bytes. */ | |
1985 | ||
c5d67833 | 1986 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ |
e9a25f70 | 1987 | fprintf ((FILE), "\t.space %d\n", (SIZE)) |
bc45ade3 SC |
1988 | |
1989 | /* This says how to output an assembler line | |
1990 | to define a global common symbol. */ | |
1991 | ||
c5d67833 | 1992 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ |
bc45ade3 SC |
1993 | ( fputs ("\t.comm ", (FILE)), \ |
1994 | assemble_name ((FILE), (NAME)), \ | |
1995 | fprintf ((FILE), ",%d\n", (SIZE))) | |
1996 | ||
1997 | /* This says how to output an assembler line | |
1998 | to define a local common symbol. */ | |
1999 | ||
e9a25f70 | 2000 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ |
bc45ade3 SC |
2001 | ( fputs ("\t.lcomm ", (FILE)), \ |
2002 | assemble_name ((FILE), (NAME)), \ | |
2003 | fprintf ((FILE), ",%d\n", (SIZE))) | |
2004 | ||
bc45ade3 SC |
2005 | /* The assembler's parentheses characters. */ |
2006 | #define ASM_OPEN_PAREN "(" | |
2007 | #define ASM_CLOSE_PAREN ")" | |
2008 | ||
2009 | /* Target characters. */ | |
2010 | #define TARGET_BELL 007 | |
2011 | #define TARGET_BS 010 | |
2012 | #define TARGET_TAB 011 | |
2013 | #define TARGET_NEWLINE 012 | |
2014 | #define TARGET_VT 013 | |
2015 | #define TARGET_FF 014 | |
2016 | #define TARGET_CR 015 | |
2017 | \f | |
e9a25f70 JL |
2018 | /* A C statement to be executed just prior to the output of |
2019 | assembler code for INSN, to modify the extracted operands so | |
2020 | they will be output differently. | |
2021 | ||
2022 | Here the argument OPVEC is the vector containing the operands | |
2023 | extracted from INSN, and NOPERANDS is the number of elements of | |
2024 | the vector which contain meaningful data for this insn. | |
2025 | The contents of this vector are what will be used to convert the insn | |
2026 | template into assembler code, so you can change the assembler output | |
2027 | by changing the contents of the vector. */ | |
2028 | ||
c5d67833 | 2029 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
e9a25f70 | 2030 | final_prescan_insn ((INSN), (OPVEC), (NOPERANDS)) |
bc45ade3 SC |
2031 | |
2032 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
2033 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2034 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2035 | ||
e9a25f70 | 2036 | #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE)) |
bc45ade3 SC |
2037 | |
2038 | /* Print a memory address as an operand to reference that memory location. */ | |
2039 | ||
e9a25f70 | 2040 | #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X)) |
bc45ade3 SC |
2041 | |
2042 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
e9a25f70 JL |
2043 | ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \ |
2044 | || (CHAR) == '$') | |
bc45ade3 | 2045 | \f |
bc45ade3 SC |
2046 | extern struct rtx_def *sh_compare_op0; |
2047 | extern struct rtx_def *sh_compare_op1; | |
2048 | extern struct rtx_def *prepare_scc_operands(); | |
2049 | ||
994295f2 JW |
2050 | /* Which processor to schedule for. The elements of the enumeration must |
2051 | match exactly the cpu attribute in the sh.md file. */ | |
bc45ade3 | 2052 | |
994295f2 | 2053 | enum processor_type { |
994295f2 JW |
2054 | PROCESSOR_SH1, |
2055 | PROCESSOR_SH2, | |
5c3ea805 | 2056 | PROCESSOR_SH3, |
225e4f43 R |
2057 | PROCESSOR_SH3E, |
2058 | PROCESSOR_SH4 | |
994295f2 JW |
2059 | }; |
2060 | ||
2061 | #define sh_cpu_attr ((enum attr_cpu)sh_cpu) | |
2062 | extern enum processor_type sh_cpu; | |
2063 | ||
e9a25f70 JL |
2064 | extern enum machine_mode sh_addr_diff_vec_mode; |
2065 | ||
33f7f353 JR |
2066 | extern int optimize; /* needed for gen_casesi. */ |
2067 | ||
994295f2 | 2068 | /* Declare functions defined in sh.c and used in templates. */ |
bc45ade3 SC |
2069 | |
2070 | extern char *output_branch(); | |
e9a25f70 JL |
2071 | extern char *output_ieee_ccmpeq(); |
2072 | extern char *output_branchy_insn(); | |
bc45ade3 SC |
2073 | extern char *output_shift(); |
2074 | extern char *output_movedouble(); | |
2075 | extern char *output_movepcrel(); | |
0d7e008e SC |
2076 | extern char *output_jump_label_table(); |
2077 | extern char *output_far_jump(); | |
2078 | ||
e9a25f70 JL |
2079 | enum mdep_reorg_phase_e |
2080 | { | |
2081 | SH_BEFORE_MDEP_REORG, | |
2082 | SH_INSERT_USES_LABELS, | |
2083 | SH_SHORTEN_BRANCHES0, | |
2084 | SH_FIXUP_PCLOAD, | |
2085 | SH_SHORTEN_BRANCHES1, | |
2086 | SH_AFTER_MDEP_REORG | |
2087 | }; | |
2088 | ||
33f7f353 JR |
2089 | extern enum mdep_reorg_phase_e mdep_reorg_phase; |
2090 | ||
e9a25f70 | 2091 | void machine_dependent_reorg (); |
e9a25f70 | 2092 | struct rtx_def *sfunc_uses_reg (); |
33f7f353 | 2093 | int barrier_align (); |
e9a25f70 | 2094 | |
0d7e008e | 2095 | #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X) |
bc45ade3 | 2096 | |
0d7e008e | 2097 | /* Generate calls to memcpy, memcmp and memset. */ |
b9654711 | 2098 | |
0d7e008e | 2099 | #define TARGET_MEM_FUNCTIONS |
b9654711 | 2100 | |
05a81fe5 | 2101 | /* Define this macro if you want to implement any pragmas. If defined, it |
f43a85ca NC |
2102 | is a C expression whose value is 1 if the pragma was handled by the |
2103 | macro, zero otherwise. */ | |
2104 | #define HANDLE_PRAGMA(GETC, UNGETC, NODE) sh_handle_pragma (GETC, UNGETC, NODE) | |
2105 | extern int sh_handle_pragma (); | |
b9654711 | 2106 | |
994295f2 | 2107 | /* Set when processing a function with pragma interrupt turned on. */ |
b9654711 | 2108 | |
0d7e008e | 2109 | extern int pragma_interrupt; |
b9654711 | 2110 | |
4408efce JL |
2111 | /* Set to an RTX containing the address of the stack to switch to |
2112 | for interrupt functions. */ | |
2113 | extern struct rtx_def *sp_switch; | |
2114 | ||
2115 | /* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS | |
2116 | is a valid machine specific attribute for DECL. | |
2117 | The attributes in ATTRIBUTES have previously been assigned to DECL. */ | |
2118 | extern int sh_valid_machine_decl_attribute (); | |
2119 | #define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \ | |
2120 | sh_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS) | |
2121 | ||
157131d7 SC |
2122 | extern void sh_pragma_insert_attributes (); |
2123 | #define PRAGMA_INSERT_ATTRIBUTES(node, pattr, prefix_attr) \ | |
2124 | sh_pragma_insert_attributes (node, pattr, prefix_attr) | |
2125 | ||
225e4f43 R |
2126 | extern int sh_flag_remove_dead_before_cse; |
2127 | extern int rtx_equal_function_value_matters; | |
2128 | extern struct rtx_def *fpscr_rtx; | |
2129 | extern struct rtx_def *get_fpscr_rtx (); | |
2130 | ||
b52cd365 JW |
2131 | \f |
2132 | /* Instructions with unfilled delay slots take up an extra two bytes for | |
33f7f353 | 2133 | the nop in the delay slot. */ |
b52cd365 JW |
2134 | |
2135 | #define ADJUST_INSN_LENGTH(X, LENGTH) \ | |
2136 | if (((GET_CODE (X) == INSN \ | |
b52cd365 JW |
2137 | && GET_CODE (PATTERN (X)) != USE \ |
2138 | && GET_CODE (PATTERN (X)) != CLOBBER) \ | |
2139 | || GET_CODE (X) == CALL_INSN \ | |
2140 | || (GET_CODE (X) == JUMP_INSN \ | |
2141 | && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \ | |
2142 | && GET_CODE (PATTERN (X)) != ADDR_VEC)) \ | |
e9a25f70 | 2143 | && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (X)))) != SEQUENCE \ |
b52cd365 | 2144 | && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \ |
33f7f353 | 2145 | (LENGTH) += 2; |
c5d67833 JW |
2146 | \f |
2147 | /* Define the codes that are matched by predicates in sh.c. */ | |
2148 | #define PREDICATE_CODES \ | |
c5d67833 | 2149 | {"arith_operand", {SUBREG, REG, CONST_INT}}, \ |
e9a25f70 | 2150 | {"arith_reg_operand", {SUBREG, REG}}, \ |
c5d67833 | 2151 | {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ |
225e4f43 | 2152 | {"binary_float_operator", {PLUS, MULT}}, \ |
225e4f43 R |
2153 | {"commutative_float_operator", {PLUS, MULT}}, \ |
2154 | {"fp_arith_reg_operand", {SUBREG, REG}}, \ | |
2155 | {"fp_extended_operand", {SUBREG, REG, FLOAT_EXTEND}}, \ | |
2156 | {"fpscr_operand", {REG}}, \ | |
c5d67833 | 2157 | {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}}, \ |
e9a25f70 JL |
2158 | {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}}, \ |
2159 | {"logical_operand", {SUBREG, REG, CONST_INT}}, \ | |
225e4f43 | 2160 | {"noncommutative_float_operator", {MINUS, DIV}}, \ |
e9a25f70 | 2161 | {"register_operand", {SUBREG, REG}}, |
c5d67833 JW |
2162 | |
2163 | /* Define this macro if it is advisable to hold scalars in registers | |
2164 | in a wider mode than that declared by the program. In such cases, | |
2165 | the value is constrained to be within the bounds of the declared | |
2166 | type, but kept valid in the wider mode. The signedness of the | |
2167 | extension may differ from that of the type. | |
2168 | ||
2169 | Leaving the unsignedp unchanged gives better code than always setting it | |
2170 | to 0. This is despite the fact that we have only signed char and short | |
2171 | load instructions. */ | |
2172 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
2173 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
2174 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
e9a25f70 | 2175 | (MODE) = SImode; |
c5d67833 | 2176 | |
32c5cac2 RK |
2177 | /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign |
2178 | extensions applied to char/short functions arguments. Defining | |
2179 | PROMOTE_FUNCTION_RETURN does the same for function returns. */ | |
2180 | ||
2181 | #define PROMOTE_FUNCTION_ARGS | |
2182 | #define PROMOTE_FUNCTION_RETURN | |
c5d67833 JW |
2183 | |
2184 | /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing | |
2185 | and poping arguments. However, we do have push/pop instructions, and | |
2186 | rather limited offsets (4 bits) in load/store instructions, so it isn't | |
2187 | clear if this would give better code. If implemented, should check for | |
2188 | compatibility problems. */ | |
2189 | ||
a62de84f JR |
2190 | /* A C statement (sans semicolon) to update the integer variable COST |
2191 | based on the relationship between INSN that is dependent on | |
2192 | DEP_INSN through the dependence LINK. The default is to make no | |
2193 | adjustment to COST. This can be used for example to specify to | |
2194 | the scheduler that an output- or anti-dependence does not incur | |
2195 | the same cost as a data-dependence. */ | |
2196 | ||
a62de84f | 2197 | #define ADJUST_COST(insn,link,dep_insn,cost) \ |
e9a25f70 JL |
2198 | do { \ |
2199 | rtx reg; \ | |
2200 | \ | |
a62de84f JR |
2201 | if (GET_CODE(insn) == CALL_INSN) \ |
2202 | { \ | |
2203 | /* The only input for a call that is timing-critical is the \ | |
2204 | function's address. */ \ | |
2205 | rtx call = PATTERN (insn); \ | |
2206 | \ | |
2207 | if (GET_CODE (call) == PARALLEL) \ | |
2208 | call = XVECEXP (call, 0 ,0); \ | |
2209 | if (GET_CODE (call) == SET) \ | |
2210 | call = SET_SRC (call); \ | |
e9a25f70 JL |
2211 | if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM \ |
2212 | && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)) \ | |
2213 | (cost) = 0; \ | |
2214 | } \ | |
2215 | /* All sfunc calls are parallels with at least four components. \ | |
2216 | Exploit this to avoid unnecessary calls to sfunc_uses_reg. */ \ | |
2217 | else if (GET_CODE (PATTERN (insn)) == PARALLEL \ | |
2218 | && XVECLEN (PATTERN (insn), 0) >= 4 \ | |
2219 | && (reg = sfunc_uses_reg (insn))) \ | |
2220 | { \ | |
2221 | /* Likewise, the most timing critical input for an sfuncs call \ | |
2222 | is the function address. However, sfuncs typically start \ | |
2223 | using their arguments pretty quickly. \ | |
2224 | Assume a four cycle delay before they are needed. */ \ | |
2225 | if (! reg_set_p (reg, dep_insn)) \ | |
225e4f43 | 2226 | cost -= TARGET_SUPERSCALAR ? 40 : 4; \ |
e9a25f70 JL |
2227 | } \ |
2228 | /* Adjust load_si / pcload_si type insns latency. Use the known \ | |
2229 | nominal latency and form of the insn to speed up the check. */ \ | |
2230 | else if (cost == 3 \ | |
2231 | && GET_CODE (PATTERN (dep_insn)) == SET \ | |
2232 | /* Latency for dmpy type insns is also 3, so check the that \ | |
2233 | it's actually a move insn. */ \ | |
2234 | && general_movsrc_operand (SET_SRC (PATTERN (dep_insn)), SImode))\ | |
2235 | cost = 2; \ | |
225e4f43 R |
2236 | else if (cost == 30 \ |
2237 | && GET_CODE (PATTERN (dep_insn)) == SET \ | |
2238 | && GET_MODE (SET_SRC (PATTERN (dep_insn))) == SImode) \ | |
2239 | cost = 20; \ | |
e9a25f70 | 2240 | } while (0) \ |
c77bb813 RK |
2241 | |
2242 | /* For the sake of libgcc2.c, indicate target supports atexit. */ | |
2243 | #define HAVE_ATEXIT | |
e9a25f70 | 2244 | |
225e4f43 R |
2245 | #define SH_DYNAMIC_SHIFT_COST \ |
2246 | (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20) |