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8b109b37 | 1 | /* Definitions of target machine for GNU compiler for Hitachi Super-H. |
e9a25f70 | 2 | Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. |
058f9bb5 JW |
3 | Contributed by Steve Chamberlain (sac@cygnus.com). |
4 | Improved by Jim Wilson (wilson@cygnus.com). | |
bc45ade3 SC |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
bc45ade3 | 22 | |
8b109b37 | 23 | |
c5d67833 | 24 | #define TARGET_VERSION \ |
bc45ade3 SC |
25 | fputs (" (Hitachi SH)", stderr); |
26 | ||
e9a25f70 JL |
27 | /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't |
28 | include it here, because hconfig.h is also included by gencodes.c . */ | |
29 | extern int code_for_indirect_jump_scratch; | |
30 | ||
bc45ade3 SC |
31 | /* Generate SDB debugging information. */ |
32 | ||
c5d67833 | 33 | #define SDB_DEBUGGING_INFO |
bc45ade3 | 34 | |
60033bb7 DE |
35 | /* Output DBX (stabs) debugging information if doing -gstabs. */ |
36 | ||
3c35520e | 37 | #include "dbxcoff.h" |
60033bb7 | 38 | |
bc45ade3 SC |
39 | #define SDB_DELIM ";" |
40 | ||
cd9784db JW |
41 | #define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__} \ |
42 | %{m1:-D__sh1__} \ | |
43 | %{m2:-D__sh2__} \ | |
44 | %{m3:-D__sh3__} \ | |
e9a25f70 JL |
45 | %{m3e:-D__SH3E__} \ |
46 | %{!m1:%{!m2:%{!m3:%{!m3e:-D__sh1__}}}}" | |
00f8ff66 | 47 | |
65c42379 | 48 | #define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)" |
bc45ade3 | 49 | |
8b32b684 | 50 | #define ASM_SPEC "%{ml:-little} %{mrelax:-relax}" |
00f8ff66 | 51 | |
8b32b684 | 52 | #define LINK_SPEC "%{ml:-m shl} %{mrelax:-relax}" |
00f8ff66 | 53 | |
d8ace44f RK |
54 | /* We can not debug without a frame pointer. */ |
55 | /* #define CAN_DEBUG_WITHOUT_FP */ | |
0d7e008e | 56 | |
0d7e008e | 57 | #define CONDITIONAL_REGISTER_USAGE \ |
5c3ea805 JW |
58 | if (! TARGET_SH3E) \ |
59 | { \ | |
60 | int regno; \ | |
61 | for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \ | |
62 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
e9a25f70 | 63 | fixed_regs[FPUL_REG] = call_used_regs[FPUL_REG] = 1; \ |
5c3ea805 | 64 | } \ |
994295f2 | 65 | /* Hitachi saves and restores mac registers on call. */ \ |
0d7e008e | 66 | if (TARGET_HITACHI) \ |
5a463884 JW |
67 | { \ |
68 | call_used_regs[MACH_REG] = 0; \ | |
69 | call_used_regs[MACL_REG] = 0; \ | |
70 | } | |
bc45ade3 | 71 | \f |
85256f8a JW |
72 | /* ??? Need to write documentation for all SH options and add it to the |
73 | invoke.texi file. */ | |
74 | ||
994295f2 | 75 | /* Run-time compilation parameters selecting different hardware subsets. */ |
bc45ade3 SC |
76 | |
77 | extern int target_flags; | |
0d7e008e | 78 | #define ISIZE_BIT (1<<1) |
0d7e008e | 79 | #define DALIGN_BIT (1<<6) |
0d7e008e SC |
80 | #define SH1_BIT (1<<8) |
81 | #define SH2_BIT (1<<9) | |
82 | #define SH3_BIT (1<<10) | |
5c3ea805 | 83 | #define SH3E_BIT (1<<11) |
0d7e008e SC |
84 | #define SPACE_BIT (1<<13) |
85 | #define BIGTABLE_BIT (1<<14) | |
8b32b684 | 86 | #define RELAX_BIT (1<<15) |
0d7e008e | 87 | #define HITACHI_BIT (1<<22) |
9791111f | 88 | #define PADSTRUCT_BIT (1<<28) |
00f8ff66 | 89 | #define LITTLE_ENDIAN_BIT (1<<29) |
e9a25f70 | 90 | #define IEEE_BIT (1<<30) |
b9654711 | 91 | |
c5d67833 JW |
92 | /* Nonzero if we should dump out instruction size info. */ |
93 | #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT) | |
94 | ||
95 | /* Nonzero to align doubles on 64 bit boundaries. */ | |
96 | #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT) | |
97 | ||
994295f2 | 98 | /* Nonzero if we should generate code using type 1 insns. */ |
b9654711 SC |
99 | #define TARGET_SH1 (target_flags & SH1_BIT) |
100 | ||
994295f2 | 101 | /* Nonzero if we should generate code using type 2 insns. */ |
b9654711 | 102 | #define TARGET_SH2 (target_flags & SH2_BIT) |
bc45ade3 | 103 | |
994295f2 | 104 | /* Nonzero if we should generate code using type 3 insns. */ |
b9654711 | 105 | #define TARGET_SH3 (target_flags & SH3_BIT) |
bc45ade3 | 106 | |
5c3ea805 JW |
107 | /* Nonzero if we should generate code using type 3E insns. */ |
108 | #define TARGET_SH3E (target_flags & SH3E_BIT) | |
109 | ||
e9a25f70 JL |
110 | /* Nonzero if we respect NANs. */ |
111 | #define TARGET_IEEE (target_flags & IEEE_BIT) | |
112 | ||
994295f2 | 113 | /* Nonzero if we should generate smaller code rather than faster code. */ |
b9654711 SC |
114 | #define TARGET_SMALLCODE (target_flags & SPACE_BIT) |
115 | ||
994295f2 | 116 | /* Nonzero to use long jump tables. */ |
0d7e008e | 117 | #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT) |
b9654711 | 118 | |
8b32b684 JW |
119 | /* Nonzero to generate pseudo-ops needed by the assembler and linker |
120 | to do function call relaxing. */ | |
121 | #define TARGET_RELAX (target_flags & RELAX_BIT) | |
122 | ||
994295f2 | 123 | /* Nonzero if using Hitachi's calling convention. */ |
d3ae8277 | 124 | #define TARGET_HITACHI (target_flags & HITACHI_BIT) |
8e87e161 | 125 | |
9791111f JW |
126 | /* Nonzero if padding structures to a multiple of 4 bytes. This is |
127 | incompatible with Hitachi's compiler, and gives unusual structure layouts | |
128 | which confuse programmers. | |
129 | ??? This option is not useful, but is retained in case there are people | |
130 | who are still relying on it. It may be deleted in the future. */ | |
131 | #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT) | |
00f8ff66 | 132 | |
c5d67833 | 133 | /* Nonzero if generating code for a little endian SH. */ |
00f8ff66 SC |
134 | #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT) |
135 | ||
136 | #define TARGET_SWITCHES \ | |
e9a25f70 | 137 | { {"1", SH1_BIT}, \ |
c5d67833 JW |
138 | {"2", SH2_BIT}, \ |
139 | {"3", SH3_BIT|SH2_BIT}, \ | |
5c3ea805 | 140 | {"3e", SH3E_BIT|SH3_BIT|SH2_BIT}, \ |
c5d67833 JW |
141 | {"b", -LITTLE_ENDIAN_BIT}, \ |
142 | {"bigtable", BIGTABLE_BIT}, \ | |
143 | {"dalign", DALIGN_BIT}, \ | |
144 | {"hitachi", HITACHI_BIT}, \ | |
e9a25f70 | 145 | {"ieee", IEEE_BIT}, \ |
c5d67833 JW |
146 | {"isize", ISIZE_BIT}, \ |
147 | {"l", LITTLE_ENDIAN_BIT}, \ | |
e9a25f70 | 148 | {"no-ieee", -IEEE_BIT}, \ |
c5d67833 | 149 | {"padstruct", PADSTRUCT_BIT}, \ |
8b32b684 | 150 | {"relax", RELAX_BIT}, \ |
c5d67833 | 151 | {"space", SPACE_BIT}, \ |
5d84b57e | 152 | SUBTARGET_SWITCHES \ |
00f8ff66 | 153 | {"", TARGET_DEFAULT} \ |
bc45ade3 SC |
154 | } |
155 | ||
5d84b57e JS |
156 | /* This are meant to be redefined in the host dependent files */ |
157 | #define SUBTARGET_SWITCHES | |
158 | ||
058f9bb5 | 159 | #define TARGET_DEFAULT (0) |
00f8ff66 | 160 | |
227665e7 JW |
161 | #define PRESERVE_DEATH_INFO_REGNO_P(regno) (TARGET_RELAX || optimize) |
162 | ||
e9a25f70 | 163 | #define ASSEMBLER_DIALECT 0 /* will allow to distinguish b[tf].s and b[tf]/s . */ |
0d7e008e SC |
164 | #define OVERRIDE_OPTIONS \ |
165 | do { \ | |
e9a25f70 | 166 | sh_cpu = CPU_SH1; \ |
0d7e008e SC |
167 | if (TARGET_SH2) \ |
168 | sh_cpu = CPU_SH2; \ | |
7c596205 JW |
169 | if (TARGET_SH3) \ |
170 | sh_cpu = CPU_SH3; \ | |
5c3ea805 JW |
171 | if (TARGET_SH3E) \ |
172 | sh_cpu = CPU_SH3E; \ | |
0d7e008e | 173 | \ |
403aec4f | 174 | /* Never run scheduling before reload, since that can \ |
c5d67833 JW |
175 | break global alloc, and generates slower code anyway due \ |
176 | to the pressure on R0. */ \ | |
177 | flag_schedule_insns = 0; \ | |
e9a25f70 | 178 | sh_addr_diff_vec_mode = TARGET_BIGTABLE ? SImode : HImode; \ |
0d7e008e | 179 | } while (0) |
bc45ade3 | 180 | \f |
c5d67833 | 181 | /* Target machine storage layout. */ |
bc45ade3 | 182 | |
b9654711 | 183 | /* Define to use software floating point emulator for REAL_ARITHMETIC and |
994295f2 | 184 | decimal <-> binary conversion. */ |
b9654711 SC |
185 | #define REAL_ARITHMETIC |
186 | ||
bc45ade3 SC |
187 | /* Define this if most significant bit is lowest numbered |
188 | in instructions that operate on numbered bit-fields. */ | |
00f8ff66 | 189 | |
bc45ade3 SC |
190 | #define BITS_BIG_ENDIAN 0 |
191 | ||
192 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
00f8ff66 | 193 | #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) |
bc45ade3 SC |
194 | |
195 | /* Define this if most significant word of a multiword number is the lowest | |
196 | numbered. */ | |
00f8ff66 SC |
197 | #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) |
198 | ||
00f8ff66 SC |
199 | /* Define this to set the endianness to use in libgcc2.c, which can |
200 | not depend on target_flags. */ | |
201 | #if defined(__LITTLE_ENDIAN__) | |
202 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
203 | #else | |
204 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
205 | #endif | |
bc45ade3 | 206 | |
994295f2 | 207 | /* Number of bits in an addressable storage unit. */ |
bc45ade3 SC |
208 | #define BITS_PER_UNIT 8 |
209 | ||
210 | /* Width in bits of a "word", which is the contents of a machine register. | |
211 | Note that this is not necessarily the width of data type `int'; | |
212 | if using 16-bit ints on a 68000, this would still be 32. | |
213 | But on a machine with 16-bit registers, this would be 16. */ | |
214 | #define BITS_PER_WORD 32 | |
215 | #define MAX_BITS_PER_WORD 32 | |
216 | ||
217 | /* Width of a word, in units (bytes). */ | |
218 | #define UNITS_PER_WORD 4 | |
219 | ||
220 | /* Width in bits of a pointer. | |
221 | See also the macro `Pmode' defined below. */ | |
222 | #define POINTER_SIZE 32 | |
223 | ||
224 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
225 | #define PARM_BOUNDARY 32 | |
226 | ||
227 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
228 | #define STACK_BOUNDARY 32 | |
229 | ||
e9a25f70 JL |
230 | /* The log (base 2) of the cache line size, in bytes. Processors prior to |
231 | SH3 have no actual cache, but they fetch code in chunks of 4 bytes. */ | |
232 | #define CACHE_LOG (TARGET_SH3 ? 4 : 2) | |
233 | ||
97b65a3e JW |
234 | /* Allocation boundary (in *bits*) for the code of a function. |
235 | 32 bit alignment is faster, because instructions are always fetched as a | |
236 | pair from a longword boundary. */ | |
e9a25f70 | 237 | #define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : (1 << CACHE_LOG) * 8) |
bc45ade3 SC |
238 | |
239 | /* Alignment of field after `int : 0' in a structure. */ | |
240 | #define EMPTY_FIELD_BOUNDARY 32 | |
241 | ||
242 | /* No data type wants to be aligned rounder than this. */ | |
243 | #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) | |
244 | ||
245 | /* The best alignment to use in cases where we have a choice. */ | |
246 | #define FASTEST_ALIGNMENT 32 | |
247 | ||
bc45ade3 | 248 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
c5d67833 | 249 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
bc45ade3 SC |
250 | ((TREE_CODE (EXP) == STRING_CST \ |
251 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
0d7e008e | 252 | ? FASTEST_ALIGNMENT : (ALIGN)) |
bc45ade3 SC |
253 | |
254 | /* Make arrays of chars word-aligned for the same reasons. */ | |
255 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
256 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
257 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
258 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
259 | ||
8e87e161 SC |
260 | /* Number of bits which any structure or union's size must be a |
261 | multiple of. Each structure or union's size is rounded up to a | |
994295f2 | 262 | multiple of this. */ |
9791111f | 263 | #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8) |
8e87e161 | 264 | |
bc45ade3 SC |
265 | /* Set this nonzero if move instructions will actually fail to work |
266 | when given unaligned data. */ | |
267 | #define STRICT_ALIGNMENT 1 | |
bc45ade3 SC |
268 | \f |
269 | /* Standard register usage. */ | |
270 | ||
0d7e008e | 271 | /* Register allocation for the Hitachi calling convention: |
bc45ade3 | 272 | |
0d7e008e SC |
273 | r0 arg return |
274 | r1..r3 scratch | |
c5d67833 | 275 | r4..r7 args in |
0d7e008e SC |
276 | r8..r13 call saved |
277 | r14 frame pointer/call saved | |
bc45ade3 SC |
278 | r15 stack pointer |
279 | ap arg pointer (doesn't really exist, always eliminated) | |
280 | pr subroutine return address | |
281 | t t bit | |
994295f2 | 282 | mach multiply/accumulate result, high part |
5c3ea805 JW |
283 | macl multiply/accumulate result, low part. |
284 | fpul fp/int communication register | |
d1405d89 | 285 | rap return address pointer register |
5c3ea805 JW |
286 | fr0 fp arg return |
287 | fr1..fr3 scratch floating point registers | |
288 | fr4..fr11 fp args in | |
289 | fr12..fr15 call saved floating point registers */ | |
bc45ade3 SC |
290 | |
291 | /* Number of actual hardware registers. | |
292 | The hardware registers are assigned numbers for the compiler | |
293 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
294 | All registers that the compiler knows about must be given numbers, | |
994295f2 | 295 | even those that are not normally considered general registers. */ |
bc45ade3 | 296 | |
994295f2 | 297 | #define AP_REG 16 |
bc45ade3 SC |
298 | #define PR_REG 17 |
299 | #define T_REG 18 | |
300 | #define GBR_REG 19 | |
301 | #define MACH_REG 20 | |
302 | #define MACL_REG 21 | |
058f9bb5 | 303 | #define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21) |
5c3ea805 | 304 | #define FPUL_REG 22 |
d1405d89 | 305 | #define RAP_REG 23 |
5c3ea805 JW |
306 | #define FIRST_FP_REG 24 |
307 | #define LAST_FP_REG 39 | |
bc45ade3 | 308 | |
5c3ea805 | 309 | #define FIRST_PSEUDO_REGISTER 40 |
bc45ade3 SC |
310 | |
311 | /* 1 for registers that have pervasive standard uses | |
994295f2 | 312 | and are not available for the register allocator. |
d3ae8277 | 313 | |
97b65a3e JW |
314 | Mach register is fixed 'cause it's only 10 bits wide for SH1. |
315 | It is 32 bits wide for SH2. */ | |
d3ae8277 | 316 | |
0d7e008e SC |
317 | #define FIXED_REGISTERS \ |
318 | { 0, 0, 0, 0, \ | |
319 | 0, 0, 0, 0, \ | |
320 | 0, 0, 0, 0, \ | |
321 | 0, 0, 0, 1, \ | |
322 | 1, 1, 1, 1, \ | |
e9a25f70 JL |
323 | 1, 1, 0, 1, \ |
324 | 0, 0, 0, 0, \ | |
5c3ea805 JW |
325 | 0, 0, 0, 0, \ |
326 | 0, 0, 0, 0, \ | |
327 | 0, 0, 0, 0, \ | |
5c3ea805 | 328 | } |
bc45ade3 SC |
329 | |
330 | /* 1 for registers not available across function calls. | |
331 | These must include the FIXED_REGISTERS and also any | |
332 | registers that can be used without being saved. | |
333 | The latter must include the registers where values are returned | |
334 | and the register where structure-value addresses are passed. | |
335 | Aside from that, you can include as many other registers as you like. */ | |
336 | ||
0d7e008e | 337 | #define CALL_USED_REGISTERS \ |
5c3ea805 JW |
338 | { 1, 1, 1, 1, \ |
339 | 1, 1, 1, 1, \ | |
340 | 0, 0, 0, 0, \ | |
341 | 0, 0, 0, 1, \ | |
342 | 1, 0, 1, 1, \ | |
343 | 1, 1, 1, 1, \ | |
344 | 1, 1, 1, 1, \ | |
345 | 1, 1, 1, 1, \ | |
346 | 1, 1, 1, 1, \ | |
e9a25f70 | 347 | 0, 0, 0, 0, \ |
5c3ea805 | 348 | } |
bc45ade3 SC |
349 | |
350 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
351 | to hold something of mode MODE. | |
352 | This is ordinarily the length in words of a value of mode MODE | |
353 | but can be less for certain modes in special long registers. | |
354 | ||
994295f2 | 355 | On the SH regs are UNITS_PER_WORD bits wide. */ |
0d7e008e | 356 | |
c5d67833 | 357 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
bc45ade3 SC |
358 | (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) |
359 | ||
360 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
058f9bb5 JW |
361 | We can allow any mode in any general register. The special registers |
362 | only allow SImode. Don't allow any mode in the PR. */ | |
bc45ade3 | 363 | |
c5d67833 | 364 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
058f9bb5 | 365 | (SPECIAL_REG (REGNO) ? (MODE) == SImode \ |
5c3ea805 JW |
366 | : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \ |
367 | : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG ? (MODE) == SFmode \ | |
058f9bb5 JW |
368 | : (REGNO) == PR_REG ? 0 \ |
369 | : 1) | |
bc45ade3 SC |
370 | |
371 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
372 | when one has mode MODE1 and one has mode MODE2. | |
373 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
374 | for any hard reg, then this must be 0 for correct output. */ | |
375 | ||
376 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
377 | ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
378 | ||
379 | /* Specify the registers used for certain standard purposes. | |
380 | The values of these macros are register numbers. */ | |
381 | ||
382 | /* Define this if the program counter is overloaded on a register. */ | |
383 | /* #define PC_REGNUM 15*/ | |
384 | ||
385 | /* Register to use for pushing function arguments. */ | |
386 | #define STACK_POINTER_REGNUM 15 | |
387 | ||
388 | /* Base register for access to local variables of the function. */ | |
389 | #define FRAME_POINTER_REGNUM 14 | |
390 | ||
d1405d89 JW |
391 | /* Fake register that holds the address on the stack of the |
392 | current function's return address. */ | |
393 | #define RETURN_ADDRESS_POINTER_REGNUM 23 | |
394 | ||
bc45ade3 SC |
395 | /* Value should be nonzero if functions must have frame pointers. |
396 | Zero means the frame pointer need not be set up (and parms may be accessed | |
397 | via the stack pointer) in functions that seem suitable. */ | |
b9654711 | 398 | |
0d7e008e | 399 | #define FRAME_POINTER_REQUIRED 0 |
bc45ade3 SC |
400 | |
401 | /* Definitions for register eliminations. | |
402 | ||
cc27ef74 | 403 | We have three registers that can be eliminated on the SH. First, the |
bc45ade3 SC |
404 | frame pointer register can often be eliminated in favor of the stack |
405 | pointer register. Secondly, the argument pointer register can always be | |
cc27ef74 JR |
406 | eliminated; it is replaced with either the stack or frame pointer. |
407 | Third, there is the retuen address pointer, which can also be replaced | |
408 | with either the stack or the frame pointer. */ | |
bc45ade3 SC |
409 | |
410 | /* This is an array of structures. Each structure initializes one pair | |
411 | of eliminable registers. The "from" register number is given first, | |
412 | followed by "to". Eliminations of the same "from" register are listed | |
413 | in order of preference. */ | |
414 | ||
cc27ef74 JR |
415 | /* If you add any registers here that are not actually hard registers, |
416 | and that have any alternative of elimination that doesn't always | |
417 | apply, you need to amend calc_live_regs to exclude it, because | |
418 | reload spills all eliminable registers where it sees an | |
419 | can_eliminate == 0 entry, thus making them 'live' . | |
420 | If you add any hard registers that can be eliminated in different | |
421 | ways, you have to patch reload to spill them only when all alternatives | |
422 | of elimination fail. */ | |
423 | ||
d1405d89 JW |
424 | #define ELIMINABLE_REGS \ |
425 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
426 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
427 | { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ | |
428 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
429 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},} | |
bc45ade3 SC |
430 | |
431 | /* Given FROM and TO register numbers, say whether this elimination | |
432 | is allowed. */ | |
433 | #define CAN_ELIMINATE(FROM, TO) \ | |
434 | (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)) | |
435 | ||
436 | /* Define the offset between two registers, one to be eliminated, and the other | |
437 | its replacement, at the start of a routine. */ | |
438 | ||
439 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
e9a25f70 | 440 | OFFSET = initial_elimination_offset ((FROM), (TO)) |
bc45ade3 SC |
441 | |
442 | /* Base register for access to arguments of the function. */ | |
443 | #define ARG_POINTER_REGNUM 16 | |
444 | ||
445 | /* Register in which the static-chain is passed to a function. */ | |
446 | #define STATIC_CHAIN_REGNUM 13 | |
447 | ||
994295f2 | 448 | /* The register in which a struct value address is passed. */ |
b9654711 | 449 | |
0d7e008e SC |
450 | #define STRUCT_VALUE_REGNUM 2 |
451 | ||
452 | /* If the structure value address is not passed in a register, define | |
453 | `STRUCT_VALUE' as an expression returning an RTX for the place | |
454 | where the address is passed. If it returns 0, the address is | |
455 | passed as an "invisible" first argument. */ | |
456 | ||
457 | /*#define STRUCT_VALUE ((rtx)0)*/ | |
bc45ade3 | 458 | |
0d7e008e SC |
459 | /* Don't default to pcc-struct-return, because we have already specified |
460 | exactly how to return structures in the RETURN_IN_MEMORY macro. */ | |
461 | ||
462 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
bc45ade3 SC |
463 | \f |
464 | /* Define the classes of registers for register constraints in the | |
465 | machine description. Also define ranges of constants. | |
466 | ||
467 | One of the classes must always be named ALL_REGS and include all hard regs. | |
468 | If there is more than one class, another class must be named NO_REGS | |
469 | and contain no registers. | |
470 | ||
471 | The name GENERAL_REGS must be the name of a class (or an alias for | |
472 | another name such as ALL_REGS). This is the class of registers | |
473 | that is allowed by "g" or "r" in a register constraint. | |
474 | Also, registers outside this class are allocated only when | |
475 | instructions express preferences for them. | |
476 | ||
477 | The classes must be numbered in nondecreasing order; that is, | |
478 | a larger-numbered class must never be contained completely | |
479 | in a smaller-numbered class. | |
480 | ||
481 | For any two classes, it is very desirable that there be another | |
482 | class that represents their union. */ | |
483 | ||
994295f2 | 484 | /* The SH has two sorts of general registers, R0 and the rest. R0 can |
bc45ade3 SC |
485 | be used as the destination of some of the arithmetic ops. There are |
486 | also some special purpose registers; the T bit register, the | |
ddd5a7c1 | 487 | Procedure Return Register and the Multiply Accumulate Registers. */ |
e9a25f70 JL |
488 | /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by |
489 | reg_class_subunion. We don't want to have an actual union class | |
490 | of these, because it would only be used when both classes are calculated | |
491 | to give the same cost, but there is only one FPUL register. | |
492 | Besides, regclass fails to notice the different REGISTER_MOVE_COSTS | |
493 | applying to the actual instruction alternative considered. E.g., the | |
494 | y/r alternative of movsi_ie is considered to have no more cost that | |
495 | the r/r alternative, which is patently untrue. */ | |
bc45ade3 SC |
496 | |
497 | enum reg_class | |
498 | { | |
499 | NO_REGS, | |
500 | R0_REGS, | |
bc45ade3 SC |
501 | PR_REGS, |
502 | T_REGS, | |
503 | MAC_REGS, | |
5c3ea805 | 504 | FPUL_REGS, |
e9a25f70 | 505 | GENERAL_REGS, |
5c3ea805 JW |
506 | FP0_REGS, |
507 | FP_REGS, | |
5c5eb4ef | 508 | GENERAL_FP_REGS, |
bc45ade3 SC |
509 | ALL_REGS, |
510 | LIM_REG_CLASSES | |
511 | }; | |
512 | ||
513 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
514 | ||
994295f2 | 515 | /* Give names of register classes as strings for dump file. */ |
c5d67833 | 516 | #define REG_CLASS_NAMES \ |
bc45ade3 SC |
517 | { \ |
518 | "NO_REGS", \ | |
519 | "R0_REGS", \ | |
bc45ade3 SC |
520 | "PR_REGS", \ |
521 | "T_REGS", \ | |
522 | "MAC_REGS", \ | |
5c3ea805 | 523 | "FPUL_REGS", \ |
e9a25f70 | 524 | "GENERAL_REGS", \ |
5c3ea805 JW |
525 | "FP0_REGS", \ |
526 | "FP_REGS", \ | |
5c5eb4ef | 527 | "GENERAL_FP_REGS", \ |
bc45ade3 SC |
528 | "ALL_REGS", \ |
529 | } | |
530 | ||
531 | /* Define which registers fit in which classes. | |
532 | This is an initializer for a vector of HARD_REG_SET | |
533 | of length N_REG_CLASSES. */ | |
534 | ||
5c3ea805 JW |
535 | #define REG_CLASS_CONTENTS \ |
536 | { \ | |
537 | { 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
538 | { 0x00000001, 0x00000000 }, /* R0_REGS */ \ | |
539 | { 0x00020000, 0x00000000 }, /* PR_REGS */ \ | |
540 | { 0x00040000, 0x00000000 }, /* T_REGS */ \ | |
541 | { 0x00300000, 0x00000000 }, /* MAC_REGS */ \ | |
5c3ea805 | 542 | { 0x00400000, 0x00000000 }, /* FPUL_REGS */ \ |
e9a25f70 | 543 | { 0x0081FFFF, 0x00000000 }, /* GENERAL_REGS */ \ |
5c3ea805 JW |
544 | { 0x01000000, 0x00000000 }, /* FP0_REGS */ \ |
545 | { 0xFF000000, 0x000000FF }, /* FP_REGS */ \ | |
f8aa1f6e JR |
546 | { 0xFF81FFFF, 0x000000FF }, /* GENERAL_FP_REGS */ \ |
547 | { 0xFFFFFFFF, 0x000000FF }, /* ALL_REGS */ \ | |
bc45ade3 SC |
548 | } |
549 | ||
550 | /* The same information, inverted: | |
551 | Return the class number of the smallest class containing | |
552 | reg number REGNO. This could be a conditional expression | |
553 | or could index an array. */ | |
554 | ||
555 | extern int regno_reg_class[]; | |
e9a25f70 | 556 | #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)] |
bc45ade3 | 557 | |
0d7e008e SC |
558 | /* When defined, the compiler allows registers explicitly used in the |
559 | rtl to be used as spill registers but prevents the compiler from | |
994295f2 | 560 | extending the lifetime of these registers. */ |
0d7e008e | 561 | |
2922fe9e | 562 | #define SMALL_REGISTER_CLASSES 1 |
0d7e008e | 563 | |
bc45ade3 | 564 | /* The order in which register should be allocated. */ |
e9a25f70 JL |
565 | /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo, |
566 | and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be | |
567 | spilled or used otherwise, we better have the FP_REGS allocated first. */ | |
c5d67833 | 568 | #define REG_ALLOC_ORDER \ |
e9a25f70 JL |
569 | { 25,26,27,28,29,30,31,24,32,33,34,35,36,37,38,39, \ |
570 | 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14, \ | |
5c3ea805 | 571 | 22,15,16,17,18,19,20,21,23 } |
bc45ade3 SC |
572 | |
573 | /* The class value for index registers, and the one for base regs. */ | |
574 | #define INDEX_REG_CLASS R0_REGS | |
575 | #define BASE_REG_CLASS GENERAL_REGS | |
576 | ||
994295f2 JW |
577 | /* Get reg_class from a letter such as appears in the machine |
578 | description. */ | |
bc45ade3 SC |
579 | extern enum reg_class reg_class_from_letter[]; |
580 | ||
581 | #define REG_CLASS_FROM_LETTER(C) \ | |
582 | ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS ) | |
c5d67833 | 583 | \f |
bc45ade3 SC |
584 | /* The letters I, J, K, L and M in a register constraint string |
585 | can be used to stand for particular ranges of immediate operands. | |
586 | This macro defines what the ranges are. | |
587 | C is the letter, and VALUE is a constant value. | |
588 | Return 1 if VALUE is in the range specified by C. | |
589 | I: arithmetic operand -127..128, as used in add, sub, etc | |
b52cd365 | 590 | K: shift operand 1,2,8 or 16 |
b9654711 | 591 | L: logical operand 0..255, as used in and, or, etc. |
bc45ade3 | 592 | M: constant 1 |
b52cd365 | 593 | N: constant 0 */ |
bc45ade3 | 594 | |
b9654711 | 595 | #define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127) |
b52cd365 | 596 | #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16) |
b9654711 | 597 | #define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255) |
bc45ade3 | 598 | #define CONST_OK_FOR_M(VALUE) ((VALUE)==1) |
0d7e008e | 599 | #define CONST_OK_FOR_N(VALUE) ((VALUE)==0) |
c5d67833 JW |
600 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
601 | ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \ | |
602 | : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \ | |
603 | : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \ | |
604 | : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \ | |
605 | : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \ | |
bc45ade3 SC |
606 | : 0) |
607 | ||
608 | /* Similar, but for floating constants, and defining letters G and H. | |
609 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
610 | ||
5c3ea805 JW |
611 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ |
612 | ((C) == 'G' ? fp_zero_operand (VALUE) \ | |
613 | : (C) == 'H' ? fp_one_operand (VALUE) \ | |
b1bbe732 | 614 | : (C) == 'F') |
5c3ea805 | 615 | |
bc45ade3 SC |
616 | /* Given an rtx X being reloaded into a reg required to be |
617 | in class CLASS, return the class of reg to actually use. | |
618 | In general this is just CLASS; but on some machines | |
619 | in some cases it is preferable to use a more restrictive class. */ | |
620 | ||
e9a25f70 | 621 | #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) |
bc45ade3 | 622 | |
0f68f06b | 623 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ |
e9a25f70 JL |
624 | ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS) \ |
625 | && (GET_CODE (X) == REG && REGNO (X) <= AP_REG)) \ | |
626 | || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \ | |
627 | && GET_CODE (X) == REG \ | |
628 | && REGNO (X) >= FIRST_FP_REG && REGNO (X) <= LAST_FP_REG)) \ | |
629 | && MODE == SFmode) \ | |
630 | ? FPUL_REGS \ | |
631 | : ((CLASS) == FPUL_REGS \ | |
632 | && (GET_CODE (X) == MEM \ | |
633 | || GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER))\ | |
634 | ? GENERAL_REGS \ | |
635 | : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \ | |
636 | && GET_CODE (X) == REG && REGNO (X) > 15 \ | |
637 | && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \ | |
638 | ? GENERAL_REGS : NO_REGS) | |
0f68f06b JR |
639 | |
640 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \ | |
e9a25f70 JL |
641 | ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS) \ |
642 | && immediate_operand ((X), (MODE)) \ | |
643 | && ! (fp_zero_operand (X) || fp_one_operand (X))) \ | |
644 | ? R0_REGS : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X))) | |
0f68f06b | 645 | |
bc45ade3 | 646 | /* Return the maximum number of consecutive registers |
994295f2 | 647 | needed to represent mode MODE in a register of class CLASS. |
bc45ade3 | 648 | |
994295f2 | 649 | On SH this is the size of MODE in words. */ |
c5d67833 | 650 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
bc45ade3 | 651 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
bc45ade3 SC |
652 | \f |
653 | /* Stack layout; function entry, exit and calling. */ | |
654 | ||
c5d67833 | 655 | /* Define the number of registers that can hold parameters. |
5c3ea805 JW |
656 | These macros are used only in other macro definitions below. */ |
657 | ||
658 | #define NPARM_REGS(MODE) \ | |
e9a25f70 JL |
659 | (TARGET_SH3E && (MODE) == SFmode \ |
660 | ? 8 \ | |
661 | : 4) | |
5c3ea805 | 662 | |
bc45ade3 | 663 | #define FIRST_PARM_REG 4 |
97b65a3e | 664 | #define FIRST_RET_REG 0 |
bc45ade3 | 665 | |
5c3ea805 JW |
666 | #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4) |
667 | #define FIRST_FP_RET_REG FIRST_FP_REG | |
668 | ||
bc45ade3 SC |
669 | /* Define this if pushing a word on the stack |
670 | makes the stack pointer a smaller address. */ | |
994295f2 | 671 | #define STACK_GROWS_DOWNWARD |
bc45ade3 | 672 | |
0d7e008e SC |
673 | /* Define this macro if the addresses of local variable slots are at |
674 | negative offsets from the frame pointer. | |
bc45ade3 | 675 | |
994295f2 | 676 | The SH only has positive indexes, so grow the frame up. */ |
0d7e008e SC |
677 | /* #define FRAME_GROWS_DOWNWARD */ |
678 | ||
679 | /* Offset from the frame pointer to the first local variable slot to | |
994295f2 | 680 | be allocated. */ |
bc45ade3 SC |
681 | #define STARTING_FRAME_OFFSET 0 |
682 | ||
683 | /* If we generate an insn to push BYTES bytes, | |
684 | this says how many the stack pointer really advances by. */ | |
e9a25f70 JL |
685 | /* Don't define PUSH_ROUNDING, since the hardware doesn't do this. |
686 | When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to | |
687 | do correct alignment. */ | |
688 | #if 0 | |
bc45ade3 | 689 | #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) |
e9a25f70 | 690 | #endif |
bc45ade3 SC |
691 | |
692 | /* Offset of first parameter from the argument pointer register value. */ | |
693 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
694 | ||
695 | /* Value is the number of byte of arguments automatically | |
696 | popped when returning from a subroutine call. | |
8b109b37 | 697 | FUNDECL is the declaration node of the function (as a tree), |
bc45ade3 SC |
698 | FUNTYPE is the data type of the function (as a tree), |
699 | or for a library call it is an identifier node for the subroutine name. | |
700 | SIZE is the number of bytes of arguments passed on the stack. | |
701 | ||
702 | On the SH, the caller does not pop any of its arguments that were passed | |
703 | on the stack. */ | |
8b109b37 | 704 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
bc45ade3 | 705 | |
5c3ea805 JW |
706 | /* Some subroutine macros specific to this machine. */ |
707 | ||
708 | #define BASE_RETURN_VALUE_REG(MODE) \ | |
709 | ((TARGET_SH3E && ((MODE) == SFmode)) \ | |
710 | ? FIRST_FP_RET_REG \ | |
711 | : FIRST_RET_REG) | |
712 | ||
713 | #define BASE_ARG_REG(MODE) \ | |
714 | ((TARGET_SH3E && ((MODE) == SFmode)) \ | |
715 | ? FIRST_FP_PARM_REG \ | |
716 | : FIRST_PARM_REG) | |
717 | ||
bc45ade3 SC |
718 | /* Define how to find the value returned by a function. |
719 | VALTYPE is the data type of the value (as a tree). | |
720 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
721 | otherwise, FUNC is 0. */ | |
0d7e008e SC |
722 | |
723 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
5c3ea805 JW |
724 | LIBCALL_VALUE (TYPE_MODE (VALTYPE)) |
725 | ||
bc45ade3 SC |
726 | /* Define how to find the value returned by a library function |
727 | assuming the value has mode MODE. */ | |
5c3ea805 | 728 | #define LIBCALL_VALUE(MODE) \ |
e9a25f70 | 729 | gen_rtx (REG, (MODE), BASE_RETURN_VALUE_REG (MODE)); |
bc45ade3 | 730 | |
5c3ea805 JW |
731 | /* 1 if N is a possible register number for a function value. */ |
732 | #define FUNCTION_VALUE_REGNO_P(REGNO) \ | |
58b57c2c | 733 | ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG)) |
bc45ade3 | 734 | |
994295f2 | 735 | /* 1 if N is a possible register number for function argument passing. */ |
c5d67833 | 736 | #define FUNCTION_ARG_REGNO_P(REGNO) \ |
e9a25f70 JL |
737 | (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG + 4)) \ |
738 | || (TARGET_SH3E \ | |
58b57c2c | 739 | && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG + 8))) |
bc45ade3 SC |
740 | \f |
741 | /* Define a data type for recording info about an argument list | |
742 | during the scan of that argument list. This data type should | |
743 | hold all necessary information about the function itself | |
744 | and about the args processed so far, enough to enable macros | |
745 | such as FUNCTION_ARG to determine where the next arg should go. | |
746 | ||
747 | On SH, this is a single integer, which is a number of words | |
748 | of arguments scanned so far (including the invisible argument, | |
749 | if any, which holds the structure-value-address). | |
750 | Thus NARGREGS or more means all following args should go on the stack. */ | |
751 | ||
5c3ea805 JW |
752 | enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 }; |
753 | struct sh_args { | |
754 | int arg_count[2]; | |
755 | }; | |
756 | ||
757 | #define CUMULATIVE_ARGS struct sh_args | |
758 | ||
759 | #define GET_SH_ARG_CLASS(MODE) \ | |
760 | ((TARGET_SH3E && ((MODE) == SFmode)) ? SH_ARG_FLOAT : SH_ARG_INT) | |
bc45ade3 | 761 | |
c5d67833 | 762 | #define ROUND_ADVANCE(SIZE) \ |
e9a25f70 | 763 | (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
bc45ade3 | 764 | |
994295f2 JW |
765 | /* Round a register number up to a proper boundary for an arg of mode |
766 | MODE. | |
767 | ||
d3ae8277 | 768 | The SH doesn't care about double alignment, so we only |
994295f2 | 769 | round doubles to even regs when asked to explicitly. */ |
bc45ade3 | 770 | |
5c3ea805 JW |
771 | #define ROUND_REG(CUM, MODE) \ |
772 | ((TARGET_ALIGN_DOUBLE \ | |
773 | && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ | |
774 | ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \ | |
775 | + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \ | |
776 | : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)]) | |
bc45ade3 | 777 | |
bc45ade3 SC |
778 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
779 | for a call to a function whose data type is FNTYPE. | |
780 | For a library call, FNTYPE is 0. | |
781 | ||
782 | On SH, the offset always starts at 0: the first parm reg is always | |
e9a25f70 | 783 | the same reg for a given argument class. */ |
bc45ade3 | 784 | |
2c7ee1a6 | 785 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ |
5c3ea805 JW |
786 | do { \ |
787 | (CUM).arg_count[(int) SH_ARG_INT] = 0; \ | |
788 | (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \ | |
789 | } while (0) | |
bc45ade3 SC |
790 | |
791 | /* Update the data in CUM to advance over an argument | |
792 | of mode MODE and data type TYPE. | |
793 | (TYPE is null for libcalls where that information may not be | |
794 | available.) */ | |
795 | ||
796 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
5c3ea805 JW |
797 | ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] = \ |
798 | (ROUND_REG ((CUM), (MODE)) \ | |
bc45ade3 SC |
799 | + ((MODE) != BLKmode \ |
800 | ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \ | |
801 | : ROUND_ADVANCE (int_size_in_bytes (TYPE))))) | |
802 | ||
5c3ea805 JW |
803 | /* Return boolean indicating arg of mode MODE will be passed in a reg. |
804 | This macro is only used in this file. */ | |
805 | ||
806 | #define PASS_IN_REG_P(CUM, MODE, TYPE) \ | |
807 | (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \ | |
58b57c2c | 808 | && ((TYPE) == 0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ |
05066d29 | 809 | && (! TARGET_SH3E || (ROUND_REG((CUM), (MODE)) + (GET_MODE_SIZE(MODE)/4) <= NPARM_REGS (MODE)))) |
5c3ea805 | 810 | |
bc45ade3 SC |
811 | /* Define where to put the arguments to a function. |
812 | Value is zero to push the argument on the stack, | |
813 | or a hard register in which to store the argument. | |
814 | ||
815 | MODE is the argument's machine mode. | |
816 | TYPE is the data type of the argument (as a tree). | |
817 | This is null for libcalls where that information may | |
818 | not be available. | |
819 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
820 | the preceding args and about the function being called. | |
821 | NAMED is nonzero if this argument is a named parameter | |
822 | (otherwise it is an extra parameter matching an ellipsis). | |
823 | ||
824 | On SH the first args are normally in registers | |
825 | and the rest are pushed. Any arg that starts within the first | |
826 | NPARM_REGS words is at least partially passed in a register unless | |
827 | its data type forbids. */ | |
828 | ||
d3ae8277 | 829 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
e9a25f70 JL |
830 | ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ |
831 | && ((NAMED) || TARGET_SH3E)) \ | |
832 | ? gen_rtx (REG, (MODE), \ | |
5c3ea805 JW |
833 | (BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \ |
834 | : 0) | |
bc45ade3 SC |
835 | |
836 | /* For an arg passed partly in registers and partly in memory, | |
837 | this is the number of registers used. | |
838 | For args passed entirely in registers or entirely in memory, zero. | |
994295f2 JW |
839 | |
840 | We sometimes split args. */ | |
0d7e008e | 841 | |
d3ae8277 | 842 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
5c3ea805 | 843 | ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ |
e9a25f70 | 844 | && ((NAMED) || TARGET_SH3E) \ |
5c3ea805 JW |
845 | && (ROUND_REG ((CUM), (MODE)) \ |
846 | + (MODE != BLKmode \ | |
847 | ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \ | |
848 | : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \ | |
849 | - NPARM_REGS (MODE) > 0)) \ | |
850 | ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \ | |
851 | : 0) | |
bc45ade3 SC |
852 | |
853 | extern int current_function_anonymous_args; | |
854 | ||
855 | /* Perform any needed actions needed for a function that is receiving a | |
994295f2 | 856 | variable number of arguments. */ |
bc45ade3 SC |
857 | |
858 | #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \ | |
859 | current_function_anonymous_args = 1; | |
860 | ||
1bad666c JW |
861 | /* Call the function profiler with a given profile label. |
862 | We use two .aligns, so as to make sure that both the .long is aligned | |
863 | on a 4 byte boundary, and that the .long is a fixed distance (2 bytes) | |
864 | from the trapa instruction. */ | |
bc45ade3 | 865 | |
b9654711 SC |
866 | #define FUNCTION_PROFILER(STREAM,LABELNO) \ |
867 | { \ | |
e9a25f70 JL |
868 | fprintf((STREAM), "\t.align\t2\n"); \ |
869 | fprintf((STREAM), "\ttrapa\t#33\n"); \ | |
870 | fprintf((STREAM), "\t.align\t2\n"); \ | |
871 | asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ | |
bc45ade3 SC |
872 | } |
873 | ||
d59c4c8e JW |
874 | /* Define this macro if the code for function profiling should come |
875 | before the function prologue. Normally, the profiling code comes | |
876 | after. */ | |
877 | ||
878 | #define PROFILE_BEFORE_PROLOGUE | |
879 | ||
bc45ade3 SC |
880 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
881 | the stack pointer does not matter. The value is tested only in | |
882 | functions that have frame pointers. | |
883 | No definition is equivalent to always zero. */ | |
884 | ||
4fdd1f85 | 885 | #define EXIT_IGNORE_STACK 1 |
bc45ade3 | 886 | |
994295f2 JW |
887 | /* Generate the assembly code for function exit |
888 | Just dump out any accumulated constant table. */ | |
bc45ade3 | 889 | |
e9a25f70 | 890 | #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue ((STREAM), (SIZE)) |
bc45ade3 | 891 | |
e9a25f70 | 892 | /* |
ddd5a7c1 | 893 | On the SH, the trampoline looks like |
bc45ade3 | 894 | 2 0002 DD02 mov.l l2,r13 |
e9a25f70 | 895 | 1 0000 D301 mov.l l1,r3 |
bc45ade3 | 896 | 3 0004 4D2B jmp @r13 |
e9a25f70 | 897 | 4 0006 0009 nop |
bc45ade3 | 898 | 5 0008 00000000 l1: .long function |
994295f2 | 899 | 6 000c 00000000 l2: .long area */ |
bc45ade3 SC |
900 | |
901 | /* Length in units of the trampoline for entering a nested function. */ | |
902 | #define TRAMPOLINE_SIZE 16 | |
903 | ||
e9a25f70 JL |
904 | /* Alignment required for a trampoline in bits . */ |
905 | #define TRAMPOLINE_ALIGNMENT \ | |
906 | ((CACHE_LOG < 3 || TARGET_SMALLCODE) ? 32 : 64) \ | |
bc45ade3 SC |
907 | |
908 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
909 | FNADDR is an RTX for the address of the function's pure code. | |
910 | CXT is an RTX for the static chain value for the function. */ | |
911 | ||
c5d67833 | 912 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
bc45ade3 | 913 | { \ |
e9a25f70 JL |
914 | emit_move_insn (gen_rtx (MEM, SImode, (TRAMP)), \ |
915 | GEN_INT (TARGET_LITTLE_ENDIAN ? 0xd301dd02 : 0xdd02d301));\ | |
916 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 4)), \ | |
917 | GEN_INT (TARGET_LITTLE_ENDIAN ? 0x00094d2b : 0x4d2b0009));\ | |
bc45ade3 SC |
918 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \ |
919 | (CXT)); \ | |
920 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \ | |
921 | (FNADDR)); \ | |
922 | } | |
d1405d89 JW |
923 | |
924 | /* A C expression whose value is RTL representing the value of the return | |
925 | address for the frame COUNT steps up from the current frame. | |
926 | FRAMEADDR is already the frame pointer of the COUNT frame, so we | |
927 | can ignore COUNT. */ | |
928 | ||
929 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
e9a25f70 | 930 | (((COUNT) == 0) \ |
d1405d89 JW |
931 | ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM)) \ |
932 | : (rtx) 0) | |
bc45ade3 | 933 | \f |
5c3ea805 JW |
934 | /* Generate necessary RTL for __builtin_saveregs(). |
935 | ARGLIST is the argument list; see expr.c. */ | |
936 | extern struct rtx_def *sh_builtin_saveregs (); | |
937 | #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sh_builtin_saveregs (ARGLIST) | |
938 | \f | |
bc45ade3 | 939 | /* Addressing modes, and classification of registers for them. */ |
d3ae8277 | 940 | #define HAVE_POST_INCREMENT 1 |
bc45ade3 SC |
941 | /*#define HAVE_PRE_INCREMENT 1*/ |
942 | /*#define HAVE_POST_DECREMENT 1*/ | |
d3ae8277 | 943 | #define HAVE_PRE_DECREMENT 1 |
bc45ade3 SC |
944 | |
945 | /* Macros to check register numbers against specific register classes. */ | |
946 | ||
947 | /* These assume that REGNO is a hard or pseudo reg number. | |
948 | They give nonzero only if REGNO is a hard reg of the suitable class | |
949 | or a pseudo reg currently allocated to a suitable hard reg. | |
950 | Since they use reg_renumber, they are safe only once reg_renumber | |
994295f2 | 951 | has been allocated, which happens in local-alloc.c. */ |
0d7e008e | 952 | |
c5d67833 | 953 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
bc45ade3 | 954 | ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG) |
c5d67833 | 955 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
0d7e008e | 956 | ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0) |
bc45ade3 | 957 | |
994295f2 JW |
958 | /* Maximum number of registers that can appear in a valid memory |
959 | address. */ | |
bc45ade3 | 960 | |
0d7e008e | 961 | #define MAX_REGS_PER_ADDRESS 2 |
bc45ade3 SC |
962 | |
963 | /* Recognize any constant value that is a valid address. */ | |
964 | ||
c5d67833 | 965 | #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) |
bc45ade3 | 966 | |
994295f2 | 967 | /* Nonzero if the constant value X is a legitimate general operand. */ |
bc45ade3 | 968 | |
5c3ea805 JW |
969 | #define LEGITIMATE_CONSTANT_P(X) \ |
970 | (GET_CODE (X) != CONST_DOUBLE \ | |
b1bbe732 | 971 | || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \ |
5c3ea805 | 972 | || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X)))) |
bc45ade3 | 973 | |
bc45ade3 SC |
974 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
975 | and check its validity for a certain class. | |
976 | We have two alternate definitions for each of them. | |
977 | The usual definition accepts all pseudo regs; the other rejects | |
978 | them unless they have been allocated suitable hard regs. | |
979 | The symbol REG_OK_STRICT causes the latter definition to be used. */ | |
980 | ||
981 | #ifndef REG_OK_STRICT | |
b9654711 | 982 | |
bc45ade3 SC |
983 | /* Nonzero if X is a hard reg that can be used as a base reg |
984 | or if it is a pseudo reg. */ | |
985 | #define REG_OK_FOR_BASE_P(X) \ | |
53c8870f | 986 | (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c5d67833 | 987 | |
bc45ade3 SC |
988 | /* Nonzero if X is a hard reg that can be used as an index |
989 | or if it is a pseudo reg. */ | |
990 | #define REG_OK_FOR_INDEX_P(X) \ | |
53c8870f RK |
991 | (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
992 | ||
993 | /* Nonzero if X/OFFSET is a hard reg that can be used as an index | |
994 | or if X is a pseudo reg. */ | |
995 | #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \ | |
996 | ((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
b9654711 | 997 | |
bc45ade3 | 998 | #else |
c5d67833 | 999 | |
bc45ade3 | 1000 | /* Nonzero if X is a hard reg that can be used as a base reg. */ |
c5d67833 | 1001 | #define REG_OK_FOR_BASE_P(X) \ |
53c8870f | 1002 | REGNO_OK_FOR_BASE_P (REGNO (X)) |
b9654711 | 1003 | |
bc45ade3 | 1004 | /* Nonzero if X is a hard reg that can be used as an index. */ |
c5d67833 | 1005 | #define REG_OK_FOR_INDEX_P(X) \ |
53c8870f RK |
1006 | REGNO_OK_FOR_INDEX_P (REGNO (X)) |
1007 | ||
1008 | /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */ | |
1009 | #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \ | |
e9a25f70 | 1010 | (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0) |
b9654711 | 1011 | |
bc45ade3 | 1012 | #endif |
0d7e008e | 1013 | |
c5d67833 | 1014 | /* The 'Q' constraint is a pc relative load operand. */ |
06c386ea SC |
1015 | #define EXTRA_CONSTRAINT_Q(OP) \ |
1016 | (GET_CODE (OP) == MEM && \ | |
e9a25f70 JL |
1017 | ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \ |
1018 | || (GET_CODE (XEXP ((OP), 0)) == CONST \ | |
1019 | && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \ | |
1020 | && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \ | |
1021 | && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT))) | |
0d7e008e | 1022 | |
c5d67833 JW |
1023 | #define EXTRA_CONSTRAINT(OP, C) \ |
1024 | ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \ | |
1025 | : 0) | |
bc45ade3 SC |
1026 | \f |
1027 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1028 | that is a valid memory address for an instruction. | |
1029 | The MODE argument is the machine mode for the MEM expression | |
1030 | that wants to use this address. | |
1031 | ||
1032 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ | |
b9654711 | 1033 | |
5c3ea805 JW |
1034 | #define MODE_DISP_OK_4(X,MODE) \ |
1035 | (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \ | |
e9a25f70 | 1036 | && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode)) |
5a463884 JW |
1037 | #define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3))) |
1038 | ||
c5d67833 JW |
1039 | #define BASE_REGISTER_RTX_P(X) \ |
1040 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
1041 | || (GET_CODE (X) == SUBREG \ | |
1042 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
1043 | && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) | |
bc45ade3 | 1044 | |
53c8870f RK |
1045 | /* Since this must be r0, which is a single register class, we must check |
1046 | SUBREGs more carefully, to be sure that we don't accept one that extends | |
1047 | outside the class. */ | |
c5d67833 JW |
1048 | #define INDEX_REGISTER_RTX_P(X) \ |
1049 | ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ | |
1050 | || (GET_CODE (X) == SUBREG \ | |
1051 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
53c8870f | 1052 | && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X)))) |
bc45ade3 SC |
1053 | |
1054 | /* Jump to LABEL if X is a valid address RTX. This must also take | |
1055 | REG_OK_STRICT into account when deciding about valid registers, but it uses | |
994295f2 JW |
1056 | the above macros so we are in luck. |
1057 | ||
bc45ade3 SC |
1058 | Allow REG |
1059 | REG+disp | |
1060 | REG+r0 | |
1061 | REG++ | |
994295f2 | 1062 | --REG */ |
bc45ade3 | 1063 | |
5c3ea805 JW |
1064 | /* ??? The SH3e does not have the REG+disp addressing mode when loading values |
1065 | into the FRx registers. We implement this by setting the maximum offset | |
1066 | to zero when the value is SFmode. This also restricts loading of SFmode | |
1067 | values into the integer registers, but that can't be helped. */ | |
1068 | ||
994295f2 | 1069 | /* The SH allows a displacement in a QI or HI amode, but only when the |
b9654711 SC |
1070 | other operand is R0. GCC doesn't handle this very well, so we forgo |
1071 | all of that. | |
1072 | ||
c5d67833 JW |
1073 | A legitimate index for a QI or HI is 0, SI can be any number 0..63, |
1074 | DI can be any number 0..60. */ | |
bc45ade3 | 1075 | |
c5d67833 | 1076 | #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \ |
0d7e008e SC |
1077 | do { \ |
1078 | if (GET_CODE (OP) == CONST_INT) \ | |
1079 | { \ | |
e9a25f70 JL |
1080 | if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \ |
1081 | if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \ | |
0d7e008e | 1082 | } \ |
bc45ade3 SC |
1083 | } while(0) |
1084 | ||
c5d67833 JW |
1085 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ |
1086 | { \ | |
1087 | if (BASE_REGISTER_RTX_P (X)) \ | |
1088 | goto LABEL; \ | |
1089 | else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ | |
e9a25f70 | 1090 | && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \ |
c5d67833 | 1091 | goto LABEL; \ |
e9a25f70 | 1092 | else if (GET_CODE (X) == PLUS && MODE != PSImode) \ |
c5d67833 | 1093 | { \ |
e9a25f70 JL |
1094 | rtx xop0 = XEXP ((X), 0); \ |
1095 | rtx xop1 = XEXP ((X), 1); \ | |
c5d67833 | 1096 | if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \ |
e9a25f70 | 1097 | GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \ |
c5d67833 JW |
1098 | if (GET_MODE_SIZE (MODE) <= 4) \ |
1099 | { \ | |
1100 | if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\ | |
1101 | goto LABEL; \ | |
1102 | if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\ | |
1103 | goto LABEL; \ | |
1104 | } \ | |
1105 | } \ | |
994295f2 JW |
1106 | } |
1107 | \f | |
1108 | /* Try machine-dependent ways of modifying an illegitimate address | |
bc45ade3 SC |
1109 | to be legitimate. If we find one, return the new, valid address. |
1110 | This macro is used in only one place: `memory_address' in explow.c. | |
1111 | ||
1112 | OLDX is the address as it was before break_out_memory_refs was called. | |
1113 | In some cases it is useful to look at this to decide what needs to be done. | |
1114 | ||
1115 | MODE and WIN are passed so that this macro can use | |
1116 | GO_IF_LEGITIMATE_ADDRESS. | |
1117 | ||
1118 | It is always safe for this macro to do nothing. It exists to recognize | |
a73a5114 | 1119 | opportunities to optimize the output. |
bc45ade3 | 1120 | |
a73a5114 JW |
1121 | For the SH, if X is almost suitable for indexing, but the offset is |
1122 | out of range, convert it into a normal form so that cse has a chance | |
1123 | of reducing the number of address registers used. */ | |
1124 | ||
1125 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1126 | { \ | |
55ebdce3 | 1127 | if (GET_CODE (X) == PLUS \ |
a73a5114 JW |
1128 | && (GET_MODE_SIZE (MODE) == 4 \ |
1129 | || GET_MODE_SIZE (MODE) == 8) \ | |
e9a25f70 JL |
1130 | && GET_CODE (XEXP ((X), 1)) == CONST_INT \ |
1131 | && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \ | |
1132 | && ! (TARGET_SH3E && (MODE) == SFmode)) \ | |
a73a5114 | 1133 | { \ |
e9a25f70 | 1134 | rtx index_rtx = XEXP ((X), 1); \ |
a73a5114 JW |
1135 | HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \ |
1136 | rtx sum; \ | |
1137 | \ | |
e9a25f70 | 1138 | GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \ |
24f72d76 | 1139 | /* On rare occasions, we might get an unaligned pointer \ |
a73a5114 JW |
1140 | that is indexed in a way to give an aligned address. \ |
1141 | Therefore, keep the lower two bits in offset_base. */ \ | |
1142 | /* Instead of offset_base 128..131 use 124..127, so that \ | |
1143 | simple add suffices. */ \ | |
1144 | if (offset > 127) \ | |
1145 | { \ | |
1146 | offset_base = ((offset + 4) & ~60) - 4; \ | |
1147 | } \ | |
1148 | else \ | |
1149 | offset_base = offset & ~60; \ | |
1150 | /* Sometimes the normal form does not suit DImode. We \ | |
1151 | could avoid that by using smaller ranges, but that \ | |
55ebdce3 | 1152 | would give less optimized code when SImode is \ |
a73a5114 JW |
1153 | prevalent. */ \ |
1154 | if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \ | |
1155 | { \ | |
e9a25f70 | 1156 | sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \ |
a73a5114 JW |
1157 | GEN_INT (offset_base), NULL_RTX, 0, \ |
1158 | OPTAB_LIB_WIDEN); \ | |
1159 | \ | |
1160 | (X) = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base)); \ | |
1161 | goto WIN; \ | |
1162 | } \ | |
1163 | } \ | |
1164 | } | |
bc45ade3 SC |
1165 | |
1166 | /* Go to LABEL if ADDR (a legitimate address expression) | |
e9a25f70 JL |
1167 | has an effect that depends on the machine mode it is used for. |
1168 | ||
1169 | ??? Strictly speaking, we should also include all indexed addressing, | |
1170 | because the index scale factor is the length of the operand. | |
1171 | However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to | |
1172 | high if we did that. So we rely on reload to fix things up. */ | |
1173 | ||
c5d67833 | 1174 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ |
bc45ade3 | 1175 | { \ |
c5d67833 | 1176 | if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \ |
bc45ade3 SC |
1177 | goto LABEL; \ |
1178 | } | |
1179 | \f | |
1180 | /* Specify the machine mode that this machine uses | |
1181 | for the index in the tablejump instruction. */ | |
0d7e008e | 1182 | #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode) |
bc45ade3 SC |
1183 | |
1184 | /* Define this if the tablejump instruction expects the table | |
1185 | to contain offsets from the address of the table. | |
1186 | Do not define this if the table should contain absolute addresses. */ | |
994295f2 | 1187 | #define CASE_VECTOR_PC_RELATIVE |
bc45ade3 SC |
1188 | |
1189 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1190 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1191 | ||
1192 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1193 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1194 | ||
5c3ea805 JW |
1195 | /* Since the SH3e has only `float' support, it is desirable to make all |
1196 | floating point types equivalent to `float'. */ | |
1197 | #define DOUBLE_TYPE_SIZE (TARGET_SH3E ? 32 : 64) | |
1198 | ||
994295f2 | 1199 | /* 'char' is signed by default. */ |
bc45ade3 SC |
1200 | #define DEFAULT_SIGNED_CHAR 1 |
1201 | ||
1202 | /* The type of size_t unsigned int. */ | |
1203 | #define SIZE_TYPE "unsigned int" | |
1204 | ||
8e87e161 SC |
1205 | #define WCHAR_TYPE "short unsigned int" |
1206 | #define WCHAR_TYPE_SIZE 16 | |
1207 | ||
bc45ade3 | 1208 | /* Don't cse the address of the function being compiled. */ |
0d7e008e | 1209 | /*#define NO_RECURSIVE_FUNCTION_CSE 1*/ |
bc45ade3 SC |
1210 | |
1211 | /* Max number of bytes we can move from memory to memory | |
1212 | in one reasonably fast instruction. */ | |
1213 | #define MOVE_MAX 4 | |
1214 | ||
9a63901f RK |
1215 | /* Define if operations between registers always perform the operation |
1216 | on the full register even if a narrower mode is specified. */ | |
1217 | #define WORD_REGISTER_OPERATIONS | |
1218 | ||
1219 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1220 | will either zero-extend or sign-extend. The value of this macro should | |
1221 | be the code that says which one of the two operations is implicitly | |
1222 | done, NIL if none. */ | |
1223 | #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND | |
bc45ade3 | 1224 | |
211a0f85 JW |
1225 | /* Define if loading short immediate values into registers sign extends. */ |
1226 | #define SHORT_IMMEDIATES_SIGN_EXTEND | |
1227 | ||
bc45ade3 | 1228 | /* Define this if zero-extension is slow (more than one real instruction). |
994295f2 | 1229 | On the SH, it's only one instruction. */ |
bc45ade3 SC |
1230 | /* #define SLOW_ZERO_EXTEND */ |
1231 | ||
1232 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
1233 | #define SLOW_BYTE_ACCESS 0 | |
1234 | ||
1235 | /* We assume that the store-condition-codes instructions store 0 for false | |
1236 | and some other value for true. This is the value stored for true. */ | |
1237 | ||
1238 | #define STORE_FLAG_VALUE 1 | |
1239 | ||
1240 | /* Immediate shift counts are truncated by the output routines (or was it | |
97b65a3e | 1241 | the assembler?). Shift counts in a register are truncated by SH. Note |
bc45ade3 | 1242 | that the native compiler puts too large (> 32) immediate shift counts |
97b65a3e | 1243 | into a register and shifts by the register, letting the SH decide what |
bc45ade3 | 1244 | to do instead of doing that itself. */ |
e9a25f70 JL |
1245 | /* ??? The library routines in lib1funcs.asm truncate the shift count. |
1246 | However, the SH3 has hardware shifts that do not truncate exactly as gcc | |
1247 | expects - the sign bit is significant - so it appears that we need to | |
1248 | leave this zero for correct SH3 code. */ | |
1249 | #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3) | |
bc45ade3 | 1250 | |
bc45ade3 SC |
1251 | /* All integers have the same format so truncation is easy. */ |
1252 | #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 | |
1253 | ||
1254 | /* Define this if addresses of constant functions | |
1255 | shouldn't be put through pseudo regs where they can be cse'd. | |
1256 | Desirable on machines where ordinary constants are expensive | |
1257 | but a CALL with constant address is cheap. */ | |
1258 | /*#define NO_FUNCTION_CSE 1*/ | |
1259 | ||
1260 | /* Chars and shorts should be passed as ints. */ | |
1261 | #define PROMOTE_PROTOTYPES 1 | |
1262 | ||
994295f2 | 1263 | /* The machine modes of pointers and functions. */ |
bc45ade3 SC |
1264 | #define Pmode SImode |
1265 | #define FUNCTION_MODE Pmode | |
1266 | ||
bc45ade3 SC |
1267 | /* The relative costs of various types of constants. Note that cse.c defines |
1268 | REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ | |
1269 | ||
c5d67833 | 1270 | #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ |
bc45ade3 | 1271 | case CONST_INT: \ |
97b65a3e JW |
1272 | if (INTVAL (RTX) == 0) \ |
1273 | return 0; \ | |
1274 | else if (CONST_OK_FOR_I (INTVAL (RTX))) \ | |
1275 | return 1; \ | |
e9a25f70 | 1276 | else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \ |
97b65a3e | 1277 | && CONST_OK_FOR_L (INTVAL (RTX))) \ |
bc45ade3 SC |
1278 | return 1; \ |
1279 | else \ | |
b9654711 | 1280 | return 8; \ |
bc45ade3 SC |
1281 | case CONST: \ |
1282 | case LABEL_REF: \ | |
1283 | case SYMBOL_REF: \ | |
b9654711 | 1284 | return 5; \ |
bc45ade3 SC |
1285 | case CONST_DOUBLE: \ |
1286 | return 10; | |
1287 | ||
1288 | #define RTX_COSTS(X, CODE, OUTER_CODE) \ | |
0d7e008e | 1289 | case AND: \ |
c5d67833 | 1290 | return COSTS_N_INSNS (andcosts (X)); \ |
bc45ade3 | 1291 | case MULT: \ |
b9654711 SC |
1292 | return COSTS_N_INSNS (multcosts (X)); \ |
1293 | case ASHIFT: \ | |
1294 | case ASHIFTRT: \ | |
994295f2 | 1295 | case LSHIFTRT: \ |
b9654711 | 1296 | return COSTS_N_INSNS (shiftcosts (X)) ; \ |
bc45ade3 SC |
1297 | case DIV: \ |
1298 | case UDIV: \ | |
1299 | case MOD: \ | |
1300 | case UMOD: \ | |
00f8ff66 | 1301 | return COSTS_N_INSNS (20); \ |
bc45ade3 SC |
1302 | case FLOAT: \ |
1303 | case FIX: \ | |
1304 | return 100; | |
1305 | ||
97b65a3e JW |
1306 | /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2 |
1307 | are actually function calls with some special constraints on arguments | |
1308 | and register usage. | |
0d7e008e | 1309 | |
994295f2 JW |
1310 | These macros tell reorg that the references to arguments and |
1311 | register clobbers for insns of type sfunc do not appear to happen | |
0d7e008e SC |
1312 | until after the millicode call. This allows reorg to put insns |
1313 | which set the argument registers into the delay slot of the millicode | |
1314 | call -- thus they act more like traditional CALL_INSNs. | |
1315 | ||
1316 | get_attr_type will try to recognize the given insn, so make sure to | |
1317 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns | |
1318 | in particular. */ | |
1319 | ||
1320 | #define INSN_SETS_ARE_DELAYED(X) \ | |
1321 | ((GET_CODE (X) == INSN \ | |
1322 | && GET_CODE (PATTERN (X)) != SEQUENCE \ | |
1323 | && GET_CODE (PATTERN (X)) != USE \ | |
1324 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
1325 | && get_attr_type (X) == TYPE_SFUNC)) | |
1326 | ||
1327 | #define INSN_REFERENCES_ARE_DELAYED(X) \ | |
1328 | ((GET_CODE (X) == INSN \ | |
1329 | && GET_CODE (PATTERN (X)) != SEQUENCE \ | |
1330 | && GET_CODE (PATTERN (X)) != USE \ | |
1331 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
994295f2 | 1332 | && get_attr_type (X) == TYPE_SFUNC)) |
0d7e008e | 1333 | |
06ada9d1 JW |
1334 | /* Compute the cost of an address. For the SH, all valid addresses are |
1335 | the same cost. */ | |
1336 | /* ??? Perhaps we should make reg+reg addresses have higher cost because | |
1337 | they add to register pressure on r0. */ | |
1338 | ||
1339 | #define ADDRESS_COST(RTX) 1 | |
1340 | ||
bc45ade3 | 1341 | /* Compute extra cost of moving data between one register class |
e9a25f70 | 1342 | and another. */ |
bc45ade3 | 1343 | |
c5d67833 | 1344 | #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \ |
e9a25f70 JL |
1345 | ((DSTCLASS) == PR_REG ? 10 \ |
1346 | : (((DSTCLASS) == FP_REGS && (SRCCLASS) == GENERAL_REGS) \ | |
1347 | || ((DSTCLASS) == GENERAL_REGS && (SRCCLASS) == FP_REGS)) ? 4 \ | |
5c3ea805 | 1348 | : 1) |
85256f8a JW |
1349 | |
1350 | /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This | |
1351 | would be so that people would slow memory systems could generate | |
1352 | different code that does fewer memory accesses. */ | |
bc45ade3 | 1353 | \f |
994295f2 | 1354 | /* Assembler output control. */ |
bc45ade3 | 1355 | |
17b65371 DE |
1356 | /* A C string constant describing how to begin a comment in the target |
1357 | assembler language. The compiler assumes that the comment will end at | |
1358 | the end of the line. */ | |
1359 | #define ASM_COMMENT_START "!" | |
1360 | ||
994295f2 | 1361 | /* The text to go at the start of the assembler file. */ |
17b65371 DE |
1362 | #define ASM_FILE_START(STREAM) \ |
1363 | output_file_start (STREAM) | |
bc45ade3 | 1364 | |
994295f2 | 1365 | #define ASM_FILE_END(STREAM) |
bc45ade3 | 1366 | |
0d7e008e SC |
1367 | #define ASM_APP_ON "" |
1368 | #define ASM_APP_OFF "" | |
1369 | #define FILE_ASM_OP "\t.file\n" | |
1370 | #define IDENT_ASM_OP "\t.ident\n" | |
6303b9ba | 1371 | #define SET_ASM_OP ".set" |
bc45ade3 | 1372 | |
994295f2 | 1373 | /* How to change between sections. */ |
bc45ade3 | 1374 | |
8e87e161 SC |
1375 | #define TEXT_SECTION_ASM_OP "\t.text" |
1376 | #define DATA_SECTION_ASM_OP "\t.data" | |
8e87e161 SC |
1377 | #define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n" |
1378 | #define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n" | |
06c386ea | 1379 | #define EXTRA_SECTIONS in_ctors, in_dtors |
c5d67833 JW |
1380 | #define EXTRA_SECTION_FUNCTIONS \ |
1381 | void \ | |
1382 | ctors_section() \ | |
1383 | { \ | |
1384 | if (in_section != in_ctors) \ | |
1385 | { \ | |
1386 | fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \ | |
1387 | in_section = in_ctors; \ | |
1388 | } \ | |
1389 | } \ | |
1390 | void \ | |
1391 | dtors_section() \ | |
1392 | { \ | |
1393 | if (in_section != in_dtors) \ | |
1394 | { \ | |
1395 | fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \ | |
1396 | in_section = in_dtors; \ | |
1397 | } \ | |
994295f2 | 1398 | } |
b9654711 | 1399 | |
e115e436 JW |
1400 | /* Define this so that jump tables go in same section as the current function, |
1401 | which could be text or it could be a user defined section. */ | |
1402 | #define JUMP_TABLES_IN_TEXT_SECTION | |
1403 | ||
7e7be9c3 DE |
1404 | /* A C statement to output something to the assembler file to switch to section |
1405 | NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or | |
1406 | NULL_TREE. Some target formats do not support arbitrary sections. Do not | |
1407 | define this macro in such cases. */ | |
d3ae8277 | 1408 | |
ad4ff310 | 1409 | #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \ |
d3ae8277 SC |
1410 | do { fprintf (FILE, ".section\t%s\n", NAME); } while (0) |
1411 | ||
c5d67833 | 1412 | #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ |
e9a25f70 | 1413 | do { ctors_section(); asm_fprintf((FILE),"\t.long\t%U%s\n", (NAME)); } while (0) |
b9654711 | 1414 | |
c5d67833 | 1415 | #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ |
e9a25f70 | 1416 | do { dtors_section(); asm_fprintf((FILE),"\t.long\t%U%s\n", (NAME)); } while (0) |
b9654711 | 1417 | |
994295f2 | 1418 | #undef DO_GLOBAL_CTORS_BODY |
0d7e008e | 1419 | |
b9654711 SC |
1420 | #define DO_GLOBAL_CTORS_BODY \ |
1421 | { \ | |
1422 | typedef (*pfunc)(); \ | |
1423 | extern pfunc __ctors[]; \ | |
1424 | extern pfunc __ctors_end[]; \ | |
1425 | pfunc *p; \ | |
c1fe41cb | 1426 | for (p = __ctors_end; p > __ctors; ) \ |
b9654711 | 1427 | { \ |
c1fe41cb | 1428 | (*--p)(); \ |
b9654711 | 1429 | } \ |
994295f2 | 1430 | } |
b9654711 | 1431 | |
994295f2 | 1432 | #undef DO_GLOBAL_DTORS_BODY |
c5d67833 | 1433 | #define DO_GLOBAL_DTORS_BODY \ |
b9654711 SC |
1434 | { \ |
1435 | typedef (*pfunc)(); \ | |
1436 | extern pfunc __dtors[]; \ | |
1437 | extern pfunc __dtors_end[]; \ | |
1438 | pfunc *p; \ | |
1439 | for (p = __dtors; p < __dtors_end; p++) \ | |
1440 | { \ | |
1441 | (*p)(); \ | |
1442 | } \ | |
994295f2 | 1443 | } |
b9654711 | 1444 | |
b9654711 | 1445 | #define ASM_OUTPUT_REG_PUSH(file, v) \ |
e9a25f70 | 1446 | fprintf ((file), "\tmov.l\tr%s,-@r15\n", (v)); |
bc45ade3 | 1447 | |
b9654711 | 1448 | #define ASM_OUTPUT_REG_POP(file, v) \ |
e9a25f70 | 1449 | fprintf ((file), "\tmov.l\t@r15+,r%s\n", (v)); |
b9654711 | 1450 | |
bc45ade3 SC |
1451 | /* The assembler's names for the registers. RFP need not always be used as |
1452 | the Real framepointer; it can also be used as a normal general register. | |
1453 | Note that the name `fp' is horribly misleading since `fp' is in fact only | |
1454 | the argument-and-return-context pointer. */ | |
1455 | #define REGISTER_NAMES \ | |
1456 | { \ | |
1457 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
1458 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
d1405d89 | 1459 | "ap", "pr", "t", "gbr", "mach","macl", "fpul","rap", \ |
5c3ea805 JW |
1460 | "fr0","fr1","fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \ |
1461 | "fr8","fr9","fr10","fr11","fr12","fr13","fr14","fr15",\ | |
bc45ade3 SC |
1462 | } |
1463 | ||
994295f2 | 1464 | /* DBX register number for a given compiler register number. */ |
5c3ea805 JW |
1465 | /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers |
1466 | to match gdb. */ | |
1467 | #define DBX_REGISTER_NUMBER(REGNO) \ | |
1468 | (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO)) | |
bc45ade3 SC |
1469 | |
1470 | /* Output a label definition. */ | |
c5d67833 | 1471 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ |
e9a25f70 | 1472 | do { assemble_name ((FILE), (NAME)); fputs (":\n", (FILE)); } while (0) |
bc45ade3 | 1473 | |
bc45ade3 SC |
1474 | /* This is how to output an assembler line |
1475 | that says to advance the location counter | |
1476 | to a multiple of 2**LOG bytes. */ | |
1477 | ||
1478 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1479 | if ((LOG) != 0) \ | |
e9a25f70 | 1480 | fprintf ((FILE), "\t.align %d\n", (LOG)) |
bc45ade3 SC |
1481 | |
1482 | /* Output a function label definition. */ | |
1483 | #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ | |
e9a25f70 | 1484 | ASM_OUTPUT_LABEL((STREAM), (NAME)) |
bc45ade3 SC |
1485 | |
1486 | /* Output a globalising directive for a label. */ | |
c5d67833 | 1487 | #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ |
e9a25f70 JL |
1488 | (fprintf ((STREAM), "\t.global\t"), \ |
1489 | assemble_name ((STREAM), (NAME)), \ | |
1490 | fputc ('\n', (STREAM))) | |
bc45ade3 | 1491 | |
4e0c8ad2 RK |
1492 | /* The prefix to add to user-visible assembler symbols. */ |
1493 | ||
1494 | #define USER_LABEL_PREFIX "_" | |
bc45ade3 | 1495 | |
e9a25f70 JL |
1496 | /* The prefix to add to an internally generated label. */ |
1497 | ||
1498 | #define LOCAL_LABEL_PREFIX "" | |
1499 | ||
bc45ade3 | 1500 | /* Make an internal label into a string. */ |
c5d67833 | 1501 | #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ |
e9a25f70 | 1502 | sprintf ((STRING), "*%s%s%d", LOCAL_LABEL_PREFIX, (PREFIX), (NUM)) |
bc45ade3 SC |
1503 | |
1504 | /* Output an internal label definition. */ | |
c5d67833 | 1505 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ |
e9a25f70 | 1506 | asm_fprintf ((FILE), "%L%s%d:\n", (PREFIX), (NUM)) |
bc45ade3 | 1507 | |
bc45ade3 SC |
1508 | /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ |
1509 | ||
1510 | /* Construct a private name. */ | |
c5d67833 JW |
1511 | #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \ |
1512 | ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \ | |
bc45ade3 SC |
1513 | sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER))) |
1514 | ||
994295f2 | 1515 | /* Jump tables must be 32 bit aligned, no matter the size of the element. */ |
bc1ebe63 | 1516 | #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \ |
e9a25f70 | 1517 | fprintf ((STREAM), "\t.align 2\n%s%d:\n", (PREFIX), (NUM)); |
0d7e008e | 1518 | |
994295f2 | 1519 | /* Output a relative address table. */ |
bc1ebe63 | 1520 | |
0d7e008e | 1521 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \ |
e9a25f70 JL |
1522 | switch (sh_addr_diff_vec_mode) \ |
1523 | { \ | |
1524 | case SImode: \ | |
1525 | asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \ | |
1526 | break; \ | |
1527 | case HImode: \ | |
1528 | asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \ | |
1529 | break; \ | |
1530 | case QImode: \ | |
1531 | asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \ | |
1532 | break; \ | |
1533 | } | |
bc45ade3 | 1534 | |
994295f2 | 1535 | /* Output an absolute table element. */ |
0d7e008e SC |
1536 | |
1537 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ | |
1538 | if (TARGET_BIGTABLE) \ | |
e9a25f70 | 1539 | asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \ |
0d7e008e | 1540 | else \ |
e9a25f70 | 1541 | asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); \ |
bc45ade3 SC |
1542 | |
1543 | /* Output various types of constants. */ | |
1544 | ||
994295f2 | 1545 | /* This is how to output an assembler line defining a `double'. */ |
bc45ade3 | 1546 | |
b9654711 SC |
1547 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ |
1548 | do { char dstr[30]; \ | |
1549 | REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ | |
e9a25f70 | 1550 | fprintf ((FILE), "\t.double %s\n", dstr); \ |
b9654711 SC |
1551 | } while (0) |
1552 | ||
bc45ade3 | 1553 | /* This is how to output an assembler line defining a `float' constant. */ |
c5d67833 | 1554 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ |
b9654711 SC |
1555 | do { char dstr[30]; \ |
1556 | REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ | |
e9a25f70 | 1557 | fprintf ((FILE), "\t.float %s\n", dstr); \ |
b9654711 | 1558 | } while (0) |
bc45ade3 | 1559 | |
e9a25f70 JL |
1560 | #define ASM_OUTPUT_INT(STREAM, EXP) \ |
1561 | (fprintf ((STREAM), "\t.long\t"), \ | |
1562 | output_addr_const ((STREAM), (EXP)), \ | |
1563 | fputc ('\n', (STREAM))) | |
bc45ade3 | 1564 | |
c5d67833 | 1565 | #define ASM_OUTPUT_SHORT(STREAM, EXP) \ |
e9a25f70 JL |
1566 | (fprintf ((STREAM), "\t.short\t"), \ |
1567 | output_addr_const ((STREAM), (EXP)), \ | |
1568 | fputc ('\n', (STREAM))) | |
bc45ade3 | 1569 | |
e9a25f70 JL |
1570 | #define ASM_OUTPUT_CHAR(STREAM, EXP) \ |
1571 | (fprintf ((STREAM), "\t.byte\t"), \ | |
1572 | output_addr_const ((STREAM), (EXP)), \ | |
1573 | fputc ('\n', (STREAM))) | |
bc45ade3 SC |
1574 | |
1575 | #define ASM_OUTPUT_BYTE(STREAM, VALUE) \ | |
e9a25f70 | 1576 | fprintf ((STREAM), "\t.byte\t%d\n", (VALUE)) \ |
bc45ade3 | 1577 | |
e9a25f70 JL |
1578 | /* The next two are used for debug info when compiling with -gdwarf. */ |
1579 | #define UNALIGNED_SHORT_ASM_OP ".uaword" | |
1580 | #define UNALIGNED_INT_ASM_OP ".ualong" | |
446b03af | 1581 | |
e9a25f70 JL |
1582 | /* Loop alignment is now done in machine_dependent_reorg, so that |
1583 | branch shortening can know about it. */ | |
446b03af | 1584 | |
bc45ade3 SC |
1585 | /* This is how to output an assembler line |
1586 | that says to advance the location counter by SIZE bytes. */ | |
1587 | ||
c5d67833 | 1588 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ |
e9a25f70 | 1589 | fprintf ((FILE), "\t.space %d\n", (SIZE)) |
bc45ade3 SC |
1590 | |
1591 | /* This says how to output an assembler line | |
1592 | to define a global common symbol. */ | |
1593 | ||
c5d67833 | 1594 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ |
bc45ade3 SC |
1595 | ( fputs ("\t.comm ", (FILE)), \ |
1596 | assemble_name ((FILE), (NAME)), \ | |
1597 | fprintf ((FILE), ",%d\n", (SIZE))) | |
1598 | ||
1599 | /* This says how to output an assembler line | |
1600 | to define a local common symbol. */ | |
1601 | ||
e9a25f70 | 1602 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ |
bc45ade3 SC |
1603 | ( fputs ("\t.lcomm ", (FILE)), \ |
1604 | assemble_name ((FILE), (NAME)), \ | |
1605 | fprintf ((FILE), ",%d\n", (SIZE))) | |
1606 | ||
bc45ade3 SC |
1607 | /* The assembler's parentheses characters. */ |
1608 | #define ASM_OPEN_PAREN "(" | |
1609 | #define ASM_CLOSE_PAREN ")" | |
1610 | ||
1611 | /* Target characters. */ | |
1612 | #define TARGET_BELL 007 | |
1613 | #define TARGET_BS 010 | |
1614 | #define TARGET_TAB 011 | |
1615 | #define TARGET_NEWLINE 012 | |
1616 | #define TARGET_VT 013 | |
1617 | #define TARGET_FF 014 | |
1618 | #define TARGET_CR 015 | |
1619 | \f | |
e9a25f70 JL |
1620 | /* A C statement to be executed just prior to the output of |
1621 | assembler code for INSN, to modify the extracted operands so | |
1622 | they will be output differently. | |
1623 | ||
1624 | Here the argument OPVEC is the vector containing the operands | |
1625 | extracted from INSN, and NOPERANDS is the number of elements of | |
1626 | the vector which contain meaningful data for this insn. | |
1627 | The contents of this vector are what will be used to convert the insn | |
1628 | template into assembler code, so you can change the assembler output | |
1629 | by changing the contents of the vector. */ | |
1630 | ||
c5d67833 | 1631 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
e9a25f70 | 1632 | final_prescan_insn ((INSN), (OPVEC), (NOPERANDS)) |
bc45ade3 SC |
1633 | |
1634 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
1635 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1636 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1637 | ||
e9a25f70 | 1638 | #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE)) |
bc45ade3 SC |
1639 | |
1640 | /* Print a memory address as an operand to reference that memory location. */ | |
1641 | ||
e9a25f70 | 1642 | #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X)) |
bc45ade3 SC |
1643 | |
1644 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
e9a25f70 JL |
1645 | ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \ |
1646 | || (CHAR) == '$') | |
bc45ade3 | 1647 | \f |
bc45ade3 SC |
1648 | extern struct rtx_def *sh_compare_op0; |
1649 | extern struct rtx_def *sh_compare_op1; | |
1650 | extern struct rtx_def *prepare_scc_operands(); | |
1651 | ||
994295f2 JW |
1652 | /* Which processor to schedule for. The elements of the enumeration must |
1653 | match exactly the cpu attribute in the sh.md file. */ | |
bc45ade3 | 1654 | |
994295f2 | 1655 | enum processor_type { |
994295f2 JW |
1656 | PROCESSOR_SH1, |
1657 | PROCESSOR_SH2, | |
5c3ea805 JW |
1658 | PROCESSOR_SH3, |
1659 | PROCESSOR_SH3E | |
994295f2 JW |
1660 | }; |
1661 | ||
1662 | #define sh_cpu_attr ((enum attr_cpu)sh_cpu) | |
1663 | extern enum processor_type sh_cpu; | |
1664 | ||
e9a25f70 JL |
1665 | extern enum machine_mode sh_addr_diff_vec_mode; |
1666 | ||
1667 | extern int optimize; /* needed for gen_casesi, and addr_diff_vec_adjust. */ | |
1668 | ||
994295f2 | 1669 | /* Declare functions defined in sh.c and used in templates. */ |
bc45ade3 SC |
1670 | |
1671 | extern char *output_branch(); | |
e9a25f70 JL |
1672 | extern char *output_ieee_ccmpeq(); |
1673 | extern char *output_branchy_insn(); | |
bc45ade3 SC |
1674 | extern char *output_shift(); |
1675 | extern char *output_movedouble(); | |
1676 | extern char *output_movepcrel(); | |
0d7e008e SC |
1677 | extern char *output_jump_label_table(); |
1678 | extern char *output_far_jump(); | |
1679 | ||
e9a25f70 JL |
1680 | enum mdep_reorg_phase_e |
1681 | { | |
1682 | SH_BEFORE_MDEP_REORG, | |
1683 | SH_INSERT_USES_LABELS, | |
1684 | SH_SHORTEN_BRANCHES0, | |
1685 | SH_FIXUP_PCLOAD, | |
1686 | SH_SHORTEN_BRANCHES1, | |
1687 | SH_AFTER_MDEP_REORG | |
1688 | }; | |
1689 | ||
1690 | void machine_dependent_reorg (); | |
1691 | int short_cbranch_p (); | |
1692 | int med_branch_p (); | |
1693 | int braf_branch_p (); | |
1694 | int align_length (); | |
1695 | int addr_diff_vec_adjust (); | |
1696 | struct rtx_def *sfunc_uses_reg (); | |
1697 | ||
0d7e008e | 1698 | #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X) |
bc45ade3 | 1699 | |
0d7e008e | 1700 | /* Generate calls to memcpy, memcmp and memset. */ |
b9654711 | 1701 | |
0d7e008e | 1702 | #define TARGET_MEM_FUNCTIONS |
b9654711 | 1703 | |
05a81fe5 | 1704 | /* Define this macro if you want to implement any pragmas. If defined, it |
7ec6d4d9 | 1705 | is a C expression to be executed when #pragma is seen. The |
92fd6199 | 1706 | argument FILE is the stdio input stream from which the source |
05a81fe5 | 1707 | text can be read. CH is the first character after the #pragma. The |
7ec6d4d9 | 1708 | result of the expression is the terminating character found |
05a81fe5 | 1709 | (newline or EOF). */ |
e9a25f70 | 1710 | #define HANDLE_PRAGMA(FILE, NODE) handle_pragma ((FILE), (NODE)) |
b9654711 | 1711 | |
994295f2 | 1712 | /* Set when processing a function with pragma interrupt turned on. */ |
b9654711 | 1713 | |
0d7e008e | 1714 | extern int pragma_interrupt; |
b9654711 | 1715 | |
4408efce JL |
1716 | /* Set to an RTX containing the address of the stack to switch to |
1717 | for interrupt functions. */ | |
1718 | extern struct rtx_def *sp_switch; | |
1719 | ||
1720 | /* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS | |
1721 | is a valid machine specific attribute for DECL. | |
1722 | The attributes in ATTRIBUTES have previously been assigned to DECL. */ | |
1723 | extern int sh_valid_machine_decl_attribute (); | |
1724 | #define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \ | |
1725 | sh_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS) | |
1726 | ||
1727 | ||
058f9bb5 | 1728 | #define MOVE_RATIO (TARGET_SMALLCODE ? 2 : 16) |
b52cd365 JW |
1729 | \f |
1730 | /* Instructions with unfilled delay slots take up an extra two bytes for | |
446b03af ILT |
1731 | the nop in the delay slot. Instructions at the start of loops, or |
1732 | after unconditional branches, may take up extra room when they are | |
1733 | aligned. ??? We would get more accurate results if we did instruction | |
1734 | alignment based on the value of INSN_CURRENT_ADDRESS; the approach used | |
1735 | here is too conservative. */ | |
b52cd365 JW |
1736 | |
1737 | #define ADJUST_INSN_LENGTH(X, LENGTH) \ | |
1738 | if (((GET_CODE (X) == INSN \ | |
b52cd365 JW |
1739 | && GET_CODE (PATTERN (X)) != USE \ |
1740 | && GET_CODE (PATTERN (X)) != CLOBBER) \ | |
1741 | || GET_CODE (X) == CALL_INSN \ | |
1742 | || (GET_CODE (X) == JUMP_INSN \ | |
1743 | && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \ | |
1744 | && GET_CODE (PATTERN (X)) != ADDR_VEC)) \ | |
e9a25f70 | 1745 | && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (X)))) != SEQUENCE \ |
b52cd365 | 1746 | && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \ |
e9a25f70 JL |
1747 | (LENGTH) += 2; \ |
1748 | if (GET_CODE (X) == INSN \ | |
1749 | && GET_CODE (PATTERN (X)) == UNSPEC_VOLATILE \ | |
1750 | && XINT (PATTERN (X), 1) == 7) \ | |
1751 | (LENGTH) -= addr_diff_vec_adjust (X, LENGTH); \ | |
1752 | if (GET_CODE (X) == INSN \ | |
1753 | && GET_CODE (PATTERN (X)) == UNSPEC_VOLATILE \ | |
1754 | && XINT (PATTERN (X), 1) == 1) \ | |
1755 | (LENGTH) = align_length (X); \ | |
1756 | if (GET_CODE (X) == JUMP_INSN \ | |
1757 | && GET_CODE (PATTERN (X)) == ADDR_DIFF_VEC) \ | |
1758 | /* The code before an ADDR_DIFF_VEC is even aligned, thus \ | |
1759 | any odd estimate is wrong. */ \ | |
1760 | (LENGTH) &= ~1; | |
b52cd365 JW |
1761 | |
1762 | /* Enable a bug fix for the shorten_branches pass. */ | |
1763 | #define SHORTEN_WITH_ADJUST_INSN_LENGTH | |
c5d67833 JW |
1764 | \f |
1765 | /* Define the codes that are matched by predicates in sh.c. */ | |
1766 | #define PREDICATE_CODES \ | |
c5d67833 | 1767 | {"arith_operand", {SUBREG, REG, CONST_INT}}, \ |
e9a25f70 | 1768 | {"arith_reg_operand", {SUBREG, REG}}, \ |
c5d67833 | 1769 | {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ |
e9a25f70 | 1770 | {"braf_label_ref_operand", {LABEL_REF}}, \ |
c5d67833 | 1771 | {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}}, \ |
e9a25f70 JL |
1772 | {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}}, \ |
1773 | {"logical_operand", {SUBREG, REG, CONST_INT}}, \ | |
1774 | {"register_operand", {SUBREG, REG}}, | |
c5d67833 JW |
1775 | |
1776 | /* Define this macro if it is advisable to hold scalars in registers | |
1777 | in a wider mode than that declared by the program. In such cases, | |
1778 | the value is constrained to be within the bounds of the declared | |
1779 | type, but kept valid in the wider mode. The signedness of the | |
1780 | extension may differ from that of the type. | |
1781 | ||
1782 | Leaving the unsignedp unchanged gives better code than always setting it | |
1783 | to 0. This is despite the fact that we have only signed char and short | |
1784 | load instructions. */ | |
1785 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
1786 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
1787 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
e9a25f70 | 1788 | (MODE) = SImode; |
c5d67833 | 1789 | |
32c5cac2 RK |
1790 | /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign |
1791 | extensions applied to char/short functions arguments. Defining | |
1792 | PROMOTE_FUNCTION_RETURN does the same for function returns. */ | |
1793 | ||
1794 | #define PROMOTE_FUNCTION_ARGS | |
1795 | #define PROMOTE_FUNCTION_RETURN | |
c5d67833 JW |
1796 | |
1797 | /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing | |
1798 | and poping arguments. However, we do have push/pop instructions, and | |
1799 | rather limited offsets (4 bits) in load/store instructions, so it isn't | |
1800 | clear if this would give better code. If implemented, should check for | |
1801 | compatibility problems. */ | |
1802 | ||
a62de84f JR |
1803 | /* A C statement (sans semicolon) to update the integer variable COST |
1804 | based on the relationship between INSN that is dependent on | |
1805 | DEP_INSN through the dependence LINK. The default is to make no | |
1806 | adjustment to COST. This can be used for example to specify to | |
1807 | the scheduler that an output- or anti-dependence does not incur | |
1808 | the same cost as a data-dependence. */ | |
1809 | ||
a62de84f | 1810 | #define ADJUST_COST(insn,link,dep_insn,cost) \ |
e9a25f70 JL |
1811 | do { \ |
1812 | rtx reg; \ | |
1813 | \ | |
a62de84f JR |
1814 | if (GET_CODE(insn) == CALL_INSN) \ |
1815 | { \ | |
1816 | /* The only input for a call that is timing-critical is the \ | |
1817 | function's address. */ \ | |
1818 | rtx call = PATTERN (insn); \ | |
1819 | \ | |
1820 | if (GET_CODE (call) == PARALLEL) \ | |
1821 | call = XVECEXP (call, 0 ,0); \ | |
1822 | if (GET_CODE (call) == SET) \ | |
1823 | call = SET_SRC (call); \ | |
e9a25f70 JL |
1824 | if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM \ |
1825 | && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)) \ | |
1826 | (cost) = 0; \ | |
1827 | } \ | |
1828 | /* All sfunc calls are parallels with at least four components. \ | |
1829 | Exploit this to avoid unnecessary calls to sfunc_uses_reg. */ \ | |
1830 | else if (GET_CODE (PATTERN (insn)) == PARALLEL \ | |
1831 | && XVECLEN (PATTERN (insn), 0) >= 4 \ | |
1832 | && (reg = sfunc_uses_reg (insn))) \ | |
1833 | { \ | |
1834 | /* Likewise, the most timing critical input for an sfuncs call \ | |
1835 | is the function address. However, sfuncs typically start \ | |
1836 | using their arguments pretty quickly. \ | |
1837 | Assume a four cycle delay before they are needed. */ \ | |
1838 | if (! reg_set_p (reg, dep_insn)) \ | |
1839 | cost -= 4; \ | |
1840 | } \ | |
1841 | /* Adjust load_si / pcload_si type insns latency. Use the known \ | |
1842 | nominal latency and form of the insn to speed up the check. */ \ | |
1843 | else if (cost == 3 \ | |
1844 | && GET_CODE (PATTERN (dep_insn)) == SET \ | |
1845 | /* Latency for dmpy type insns is also 3, so check the that \ | |
1846 | it's actually a move insn. */ \ | |
1847 | && general_movsrc_operand (SET_SRC (PATTERN (dep_insn)), SImode))\ | |
1848 | cost = 2; \ | |
1849 | } while (0) \ | |
c77bb813 | 1850 | |
a8d762e1 JW |
1851 | /* Since the SH architecture lacks negative address offsets, |
1852 | the givs should be sorted smallest to largest so combine_givs | |
1853 | has maximum opportunity to combine givs. */ | |
1854 | #define GIV_SORT_CRITERION(X, Y) \ | |
1855 | if (GET_CODE ((X)->add_val) == CONST_INT \ | |
1856 | && GET_CODE ((Y)->add_val) == CONST_INT) \ | |
1857 | return INTVAL ((X)->add_val) - INTVAL ((Y)->add_val); | |
1858 | ||
c77bb813 RK |
1859 | /* For the sake of libgcc2.c, indicate target supports atexit. */ |
1860 | #define HAVE_ATEXIT | |
e9a25f70 JL |
1861 | |
1862 | #define SH_DYNAMIC_SHIFT_COST (TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20) |