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c39b724a | 1 | ;; DFA scheduling description for Renesas / SuperH SH. |
f1717362 | 2 | ;; Copyright (C) 2004-2016 Free Software Foundation, Inc. |
c39b724a | 3 | |
4 | ;; This file is part of GCC. | |
5 | ||
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
038d1e19 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
c39b724a | 9 | ;; any later version. |
10 | ||
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ||
16 | ;; You should have received a copy of the GNU General Public License | |
038d1e19 | 17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
c39b724a | 19 | |
20 | ;; Load and store instructions save a cycle if they are aligned on a | |
21 | ;; four byte boundary. Using a function unit for stores encourages | |
22 | ;; gcc to separate load and store instructions by one instruction, | |
23 | ;; which makes it more likely that the linker will be able to word | |
24 | ;; align them when relaxing. | |
25 | ||
26 | ;; SH-1 scheduling. This is just a conversion of the old scheduling | |
27 | ;; model, using define_function_unit. | |
28 | ||
29 | (define_automaton "sh1") | |
30 | (define_cpu_unit "sh1memory,sh1int,sh1mpy,sh1fp" "sh1") | |
31 | ||
32 | ;; Loads have a latency of two. | |
33 | ;; However, call insns can have a delay slot, so that we want one more | |
34 | ;; insn to be scheduled between the load of the function address and the call. | |
35 | ;; This is equivalent to a latency of three. | |
36 | ;; ADJUST_COST can only properly handle reductions of the cost, so we | |
37 | ;; use a latency of three here. | |
38 | ;; We only do this for SImode loads of general registers, to make the work | |
39 | ;; for ADJUST_COST easier. | |
40 | (define_insn_reservation "sh1_load_si" 3 | |
41 | (and (eq_attr "pipe_model" "sh1") | |
42 | (eq_attr "type" "load_si,pcload_si")) | |
43 | "sh1memory*2") | |
44 | ||
45 | (define_insn_reservation "sh1_load_store" 2 | |
46 | (and (eq_attr "pipe_model" "sh1") | |
5be30882 | 47 | (eq_attr "type" "load,pcload,pload,mem_mac,store,fstore,pstore,mac_mem")) |
c39b724a | 48 | "sh1memory*2") |
49 | ||
50 | (define_insn_reservation "sh1_arith3" 3 | |
51 | (and (eq_attr "pipe_model" "sh1") | |
52 | (eq_attr "type" "arith3,arith3b")) | |
53 | "sh1int*3") | |
54 | ||
55 | (define_insn_reservation "sh1_dyn_shift" 2 | |
56 | (and (eq_attr "pipe_model" "sh1") | |
57 | (eq_attr "type" "dyn_shift")) | |
58 | "sh1int*2") | |
59 | ||
60 | (define_insn_reservation "sh1_int" 1 | |
61 | (and (eq_attr "pipe_model" "sh1") | |
62 | (eq_attr "type" "!arith3,arith3b,dyn_shift")) | |
63 | "sh1int") | |
64 | ||
65 | ;; ??? These are approximations. | |
66 | (define_insn_reservation "sh1_smpy" 2 | |
67 | (and (eq_attr "pipe_model" "sh1") | |
68 | (eq_attr "type" "smpy")) | |
69 | "sh1mpy*2") | |
70 | ||
71 | (define_insn_reservation "sh1_dmpy" 3 | |
72 | (and (eq_attr "pipe_model" "sh1") | |
73 | (eq_attr "type" "dmpy")) | |
74 | "sh1mpy*3") | |
75 | ||
76 | (define_insn_reservation "sh1_fp" 2 | |
77 | (and (eq_attr "pipe_model" "sh1") | |
5be30882 | 78 | (eq_attr "type" "fp,fpscr_toggle,fp_cmp,fmove")) |
c39b724a | 79 | "sh1fp") |
80 | ||
81 | (define_insn_reservation "sh1_fdiv" 13 | |
82 | (and (eq_attr "pipe_model" "sh1") | |
83 | (eq_attr "type" "fdiv")) | |
84 | "sh1fp*12") | |
85 |