]>
Commit | Line | Data |
---|---|---|
157891a3 | 1 | ;; Constraint definitions for SPARC. |
99dee823 | 2 | ;; Copyright (C) 2008-2021 Free Software Foundation, Inc. |
157891a3 EB |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ||
20 | ;;; Unused letters: | |
8b98b5fd | 21 | ;;; B |
bcc3c3f1 | 22 | ;;; a jkl uv xyz |
157891a3 EB |
23 | |
24 | ||
25 | ;; Register constraints | |
26 | ||
27 | (define_register_constraint "b" "(TARGET_V9 && TARGET_VIS ? EXTRA_FP_REGS : NO_REGS)" | |
28 | "Any floating-point register in VIS mode") | |
29 | ||
30 | (define_register_constraint "c" "FPCC_REGS" | |
31 | "Floating-point condition code register") | |
32 | ||
33 | (define_register_constraint "d" "(TARGET_V9 && TARGET_VIS ? FP_REGS : NO_REGS)" | |
34 | "Lower floating-point register in VIS mode") | |
35 | ||
36 | ;; In the non-V9 case, coerce V9 'e' class to 'f', so we can use 'e' in the | |
37 | ;; MD file for V8 and V9. | |
77167b6f | 38 | (define_register_constraint "e" "(TARGET_FPU ? (TARGET_V9 ? EXTRA_FP_REGS : FP_REGS) : NO_REGS)" |
157891a3 EB |
39 | "Any floating-point register") |
40 | ||
77167b6f | 41 | (define_register_constraint "f" "(TARGET_FPU ? FP_REGS : NO_REGS)" |
157891a3 EB |
42 | "Lower floating-point register") |
43 | ||
44 | (define_register_constraint "h" "(TARGET_V9 && TARGET_V8PLUS ? I64_REGS : NO_REGS)" | |
45 | "64-bit global or out register in V8+ mode") | |
46 | ||
157891a3 EB |
47 | ;; Floating-point constant constraints |
48 | ||
49 | (define_constraint "G" | |
50 | "The floating-point zero constant" | |
51 | (and (match_code "const_double") | |
52 | (match_test "const_zero_operand (op, mode)"))) | |
53 | ||
7cbcf85b DM |
54 | (define_constraint "C" |
55 | "The floating-point all-ones constant" | |
56 | (and (match_code "const_double") | |
57 | (match_test "const_all_ones_operand (op, mode)"))) | |
157891a3 EB |
58 | |
59 | ;; Integer constant constraints | |
60 | ||
bcc3c3f1 JM |
61 | (define_constraint "q" |
62 | "Unsigned 2-bit integer constant" | |
63 | (and (match_code "const_int") | |
64 | (match_test "SPARC_IMM2_P (ival)"))) | |
65 | ||
66 | (define_constraint "t" | |
67 | "Unsigned 5-bit integer constant" | |
68 | (and (match_code "const_int") | |
69 | (match_test "SPARC_IMM5_P (ival)"))) | |
70 | ||
8b98b5fd DM |
71 | (define_constraint "A" |
72 | "Signed 5-bit integer constant" | |
73 | (and (match_code "const_int") | |
74 | (match_test "SPARC_SIMM5_P (ival)"))) | |
75 | ||
157891a3 EB |
76 | (define_constraint "H" |
77 | "Valid operand of double arithmetic operation" | |
78 | (and (match_code "const_double") | |
79 | (match_test "arith_double_operand (op, DImode)"))) | |
80 | ||
81 | (define_constraint "I" | |
82 | "Signed 13-bit integer constant" | |
83 | (and (match_code "const_int") | |
84 | (match_test "SPARC_SIMM13_P (ival)"))) | |
85 | ||
86 | (define_constraint "J" | |
87 | "The integer zero constant" | |
88 | (and (match_code "const_int") | |
89 | (match_test "ival == 0"))) | |
90 | ||
91 | (define_constraint "K" | |
92 | "Signed 32-bit constant that can be loaded with a sethi instruction" | |
93 | (and (match_code "const_int") | |
94 | (match_test "SPARC_SETHI32_P (ival)"))) | |
95 | ||
96 | (define_constraint "L" | |
97 | "Signed 11-bit integer constant" | |
98 | (and (match_code "const_int") | |
99 | (match_test "SPARC_SIMM11_P (ival)"))) | |
100 | ||
101 | (define_constraint "M" | |
102 | "Signed 10-bit integer constant" | |
103 | (and (match_code "const_int") | |
104 | (match_test "SPARC_SIMM10_P (ival)"))) | |
105 | ||
106 | (define_constraint "N" | |
107 | "Signed constant that can be loaded with a sethi instruction" | |
108 | (and (match_code "const_int") | |
109 | (match_test "SPARC_SETHI_P (ival)"))) | |
110 | ||
111 | (define_constraint "O" | |
112 | "The 4096 constant" | |
113 | (and (match_code "const_int") | |
114 | (match_test "ival == 4096"))) | |
115 | ||
7cbcf85b DM |
116 | (define_constraint "P" |
117 | "The integer constant -1" | |
118 | (and (match_code "const_int") | |
119 | (match_test "ival == -1"))) | |
157891a3 | 120 | |
66e62b49 KH |
121 | (define_constraint "D" |
122 | "const_vector" | |
123 | (and (match_code "const_vector") | |
124 | (match_test "GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT"))) | |
125 | ||
157891a3 EB |
126 | (define_constraint "Q" |
127 | "Floating-point constant that can be loaded with a sethi instruction" | |
128 | (and (match_code "const_double") | |
129 | (match_test "fp_sethi_p (op)"))) | |
130 | ||
131 | (define_constraint "R" | |
132 | "Floating-point constant that can be loaded with a move instruction" | |
133 | (and (match_code "const_double") | |
134 | (match_test "fp_mov_p (op)"))) | |
135 | ||
136 | (define_constraint "S" | |
137 | "Floating-point constant that can be loaded with a high/lo_sum sequence" | |
138 | (and (match_code "const_double") | |
139 | (match_test "fp_high_losum_p (op)"))) | |
140 | ||
5c2ee2f1 EB |
141 | ;; We need a special memory constraint because of the alignment requirement |
142 | (define_special_memory_constraint "T" | |
157891a3 | 143 | "Memory reference whose address is aligned to 8-byte boundary" |
5c2ee2f1 EB |
144 | (and (match_code "mem") |
145 | (match_test "TARGET_ARCH32") | |
157891a3 EB |
146 | (match_test "memory_ok_for_ldd (op)"))) |
147 | ||
dc2a24ed DM |
148 | ;; This awkward register constraint is necessary because it is not |
149 | ;; possible to express the "must be even numbered register" condition | |
150 | ;; using register classes. The problem is that membership in a | |
151 | ;; register class requires that all registers of a multi-regno | |
152 | ;; register be included in the set. It is add_to_hard_reg_set | |
153 | ;; and in_hard_reg_set_p which populate and test regsets with these | |
154 | ;; semantics. | |
155 | ;; | |
156 | ;; So this means that we would have to put both the even and odd | |
157 | ;; register into the register class, which would not restrict things | |
158 | ;; at all. | |
159 | ;; | |
f939c3e6 RS |
160 | ;; Using a combination of GENERAL_REGS and TARGET_HARD_REGNO_MODE_OK is |
161 | ;; not a full solution either. In fact, even though IRA uses the macro | |
162 | ;; TARGET_HARD_REGNO_MODE_OK to calculate which registers are prohibited | |
163 | ;; from use in certain modes, it still can allocate an odd hard register | |
dc2a24ed DM |
164 | ;; for DImode values. This is due to how IRA populates the table |
165 | ;; ira_useful_class_mode_regs[][]. It suffers from the same problem | |
166 | ;; as using a register class to describe this restriction. Namely, it | |
167 | ;; sets both the odd and even part of an even register pair in the | |
168 | ;; regset. Therefore IRA can and will allocate odd registers for | |
169 | ;; DImode values on 32-bit. | |
170 | ;; | |
171 | ;; There are legitimate cases where DImode values can end up in odd | |
172 | ;; hard registers, the most notable example is argument passing. | |
173 | ;; | |
174 | ;; What saves us is reload and the DImode splitters. Both are | |
175 | ;; necessary. The odd register splitters cannot match if, for | |
176 | ;; example, we have a non-offsetable MEM. Reload will notice this | |
177 | ;; case and reload the address into a single hard register. | |
178 | ;; | |
7c3cace1 EB |
179 | ;; The real downfall of this awkward register constraint is that it |
180 | ;; does not evaluate to a true register class like a bonafide use of | |
181 | ;; define_register_constraint would. This means that we cannot use | |
182 | ;; it with LRA, since the constraint processing of LRA really depends | |
dc2a24ed DM |
183 | ;; upon whether an extra constraint is for registers or not. It uses |
184 | ;; reg_class_for_constraint, and checks it against NO_REGS. | |
185 | (define_constraint "U" | |
186 | "Pseudo-register or hard even-numbered integer register" | |
5c2ee2f1 | 187 | (and (match_code "reg") |
dc2a24ed DM |
188 | (ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER") |
189 | (not (match_test "reload_in_progress && reg_renumber [REGNO (op)] < 0"))) | |
5c2ee2f1 | 190 | (match_test "TARGET_ARCH32") |
dc2a24ed DM |
191 | (match_test "register_ok_for_ldd (op)"))) |
192 | ||
5c2ee2f1 | 193 | ;; Equivalent to 'T' but in 64-bit mode without alignment requirement |
9106d8d2 | 194 | (define_memory_constraint "W" |
157891a3 | 195 | "Memory reference for 'e' constraint floating-point register" |
9106d8d2 | 196 | (and (match_code "mem") |
5c2ee2f1 | 197 | (match_test "TARGET_ARCH64") |
157891a3 EB |
198 | (match_test "memory_ok_for_ldd (op)"))) |
199 | ||
923f9ded DM |
200 | (define_memory_constraint "w" |
201 | "A memory with only a base register" | |
202 | (match_operand 0 "mem_noofs_operand")) | |
203 | ||
157891a3 EB |
204 | (define_constraint "Y" |
205 | "The vector zero constant" | |
206 | (and (match_code "const_vector") | |
207 | (match_test "const_zero_operand (op, mode)"))) | |
7cbcf85b DM |
208 | |
209 | (define_constraint "Z" | |
210 | "The vector all ones constant" | |
211 | (and (match_code "const_vector") | |
212 | (match_test "const_all_ones_operand (op, mode)"))) |