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27b36d57 | 1 | ;; Predicate definitions for SPARC. |
fbd26352 | 2 | ;; Copyright (C) 2005-2019 Free Software Foundation, Inc. |
27b36d57 | 3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
038d1e19 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
27b36d57 | 9 | ;; any later version. |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
038d1e19 | 17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
27b36d57 | 19 | |
20 | ;; Predicates for numerical constants. | |
21 | ||
22 | ;; Return true if OP is the zero constant for MODE. | |
23 | (define_predicate "const_zero_operand" | |
543530a7 | 24 | (and (match_code "const_int,const_wide_int,const_double,const_vector") |
27b36d57 | 25 | (match_test "op == CONST0_RTX (mode)"))) |
26 | ||
543530a7 | 27 | ;; Return true if the integer representation of OP is all ones. |
bbfdec17 | 28 | (define_predicate "const_all_ones_operand" |
543530a7 | 29 | (and (match_code "const_int,const_wide_int,const_double,const_vector") |
10340a85 | 30 | (match_test "INTEGRAL_MODE_P (GET_MODE (op))") |
31 | (match_test "op == CONSTM1_RTX (GET_MODE (op))"))) | |
bbfdec17 | 32 | |
27b36d57 | 33 | ;; Return true if OP is the integer constant 4096. |
34 | (define_predicate "const_4096_operand" | |
35 | (and (match_code "const_int") | |
36 | (match_test "INTVAL (op) == 4096"))) | |
37 | ||
38 | ;; Return true if OP is a constant that is representable by a 13-bit | |
39 | ;; signed field. This is an acceptable immediate operand for most | |
40 | ;; 3-address instructions. | |
41 | (define_predicate "small_int_operand" | |
42 | (and (match_code "const_int") | |
43 | (match_test "SPARC_SIMM13_P (INTVAL (op))"))) | |
44 | ||
45 | ;; Return true if OP is a constant operand for the umul instruction. That | |
46 | ;; instruction sign-extends immediate values just like all other SPARC | |
47 | ;; instructions, but interprets the extended result as an unsigned number. | |
48 | (define_predicate "uns_small_int_operand" | |
543530a7 | 49 | (and (match_code "const_int") |
50 | (match_test "((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) | |
51 | || (INTVAL (op) >= 0xFFFFF000 | |
52 | && INTVAL (op) <= 0xFFFFFFFF))"))) | |
27b36d57 | 53 | |
54 | ;; Return true if OP is a constant that can be loaded by the sethi instruction. | |
55 | ;; The first test avoids emitting sethi to load zero for example. | |
56 | (define_predicate "const_high_operand" | |
57 | (and (match_code "const_int") | |
c3f211ea | 58 | (and (not (match_operand 0 "small_int_operand")) |
27b36d57 | 59 | (match_test "SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))")))) |
60 | ||
35f85e39 | 61 | ;; Return true if OP is a constant whose 1's complement can be loaded by the |
62 | ;; sethi instruction. | |
63 | (define_predicate "const_compl_high_operand" | |
64 | (and (match_code "const_int") | |
65 | (and (not (match_operand 0 "small_int_operand")) | |
66 | (match_test "SPARC_SETHI_P (~INTVAL (op) & GET_MODE_MASK (mode))")))) | |
27b36d57 | 67 | |
c3f211ea | 68 | ;; Return true if OP is a FP constant that needs to be loaded by the sethi/losum |
69 | ;; pair of instructions. | |
70 | (define_predicate "fp_const_high_losum_operand" | |
71 | (match_operand 0 "const_double_operand") | |
72 | { | |
73 | gcc_assert (mode == SFmode); | |
74 | return fp_high_losum_p (op); | |
75 | }) | |
76 | ||
83c0aede | 77 | ;; Return true if OP is a const_double or const_vector. |
78 | (define_predicate "const_double_or_vector_operand" | |
79 | (match_code "const_double,const_vector")) | |
80 | ||
a3664b60 | 81 | ;; Return true if OP is Zero, or if the target is V7. |
82 | (define_predicate "zero_or_v7_operand" | |
803dea20 | 83 | (and (match_code "const_int") |
84 | (ior (match_test "INTVAL (op) == 0") | |
85 | (match_test "!TARGET_V8 && !TARGET_V9")))) | |
c3f211ea | 86 | |
27b36d57 | 87 | ;; Predicates for symbolic constants. |
88 | ||
89 | ;; Return true if OP is either a symbol reference or a sum of a symbol | |
90 | ;; reference and a constant. | |
91 | (define_predicate "symbolic_operand" | |
92 | (match_code "symbol_ref,label_ref,const") | |
93 | { | |
3754d046 | 94 | machine_mode omode = GET_MODE (op); |
27b36d57 | 95 | |
96 | if (omode != mode && omode != VOIDmode && mode != VOIDmode) | |
97 | return false; | |
98 | ||
99 | switch (GET_CODE (op)) | |
100 | { | |
101 | case SYMBOL_REF: | |
102 | return !SYMBOL_REF_TLS_MODEL (op); | |
103 | ||
104 | case LABEL_REF: | |
105 | return true; | |
106 | ||
107 | case CONST: | |
108 | op = XEXP (op, 0); | |
109 | return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
110 | && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0))) | |
111 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
112 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
113 | ||
114 | default: | |
115 | gcc_unreachable (); | |
116 | } | |
117 | }) | |
118 | ||
119 | ;; Return true if OP is a symbolic operand for the TLS Global Dynamic model. | |
120 | (define_predicate "tgd_symbolic_operand" | |
121 | (and (match_code "symbol_ref") | |
76d4bacb | 122 | (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_GLOBAL_DYNAMIC"))) |
27b36d57 | 123 | |
124 | ;; Return true if OP is a symbolic operand for the TLS Local Dynamic model. | |
125 | (define_predicate "tld_symbolic_operand" | |
126 | (and (match_code "symbol_ref") | |
76d4bacb | 127 | (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_DYNAMIC"))) |
27b36d57 | 128 | |
129 | ;; Return true if OP is a symbolic operand for the TLS Initial Exec model. | |
130 | (define_predicate "tie_symbolic_operand" | |
131 | (and (match_code "symbol_ref") | |
76d4bacb | 132 | (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC"))) |
27b36d57 | 133 | |
134 | ;; Return true if OP is a symbolic operand for the TLS Local Exec model. | |
135 | (define_predicate "tle_symbolic_operand" | |
136 | (and (match_code "symbol_ref") | |
76d4bacb | 137 | (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC"))) |
27b36d57 | 138 | |
139 | ;; Return true if the operand is an argument used in generating PIC references | |
140 | ;; in either the medium/low or embedded medium/anywhere code models on V9. | |
141 | ;; Check for (const (minus (symbol_ref:GOT) | |
142 | ;; (const (minus (label) (pc))))) | |
143 | (define_predicate "medium_pic_operand" | |
144 | (match_code "const") | |
145 | { | |
146 | /* Check for (const (minus (symbol_ref:GOT) | |
147 | (const (minus (label) (pc))))). */ | |
148 | op = XEXP (op, 0); | |
149 | return GET_CODE (op) == MINUS | |
150 | && GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
151 | && GET_CODE (XEXP (op, 1)) == CONST | |
152 | && GET_CODE (XEXP (XEXP (op, 1), 0)) == MINUS; | |
153 | }) | |
154 | ||
155 | ;; Return true if OP is a LABEL_REF of mode MODE. | |
156 | (define_predicate "label_ref_operand" | |
157 | (and (match_code "label_ref") | |
158 | (match_test "GET_MODE (op) == mode"))) | |
159 | ||
160 | ;; Return true if OP is a data segment reference. This includes the readonly | |
161 | ;; data segment or, in other words, anything but the text segment. | |
162 | ;; This is needed in the embedded medium/anywhere code model on V9. These | |
163 | ;; values are accessed with EMBMEDANY_BASE_REG. */ | |
164 | (define_predicate "data_segment_operand" | |
165 | (match_code "symbol_ref,plus,const") | |
166 | { | |
167 | switch (GET_CODE (op)) | |
168 | { | |
169 | case SYMBOL_REF : | |
170 | return ! SYMBOL_REF_FUNCTION_P (op); | |
171 | case PLUS : | |
172 | /* Assume canonical format of symbol + constant. | |
173 | Fall through. */ | |
174 | case CONST : | |
175 | return data_segment_operand (XEXP (op, 0), VOIDmode); | |
176 | default : | |
177 | gcc_unreachable (); | |
178 | } | |
179 | }) | |
180 | ||
181 | ;; Return true if OP is a text segment reference. | |
182 | ;; This is needed in the embedded medium/anywhere code model on V9. | |
183 | (define_predicate "text_segment_operand" | |
184 | (match_code "label_ref,symbol_ref,plus,const") | |
185 | { | |
186 | switch (GET_CODE (op)) | |
187 | { | |
188 | case LABEL_REF : | |
189 | return true; | |
190 | case SYMBOL_REF : | |
191 | return SYMBOL_REF_FUNCTION_P (op); | |
192 | case PLUS : | |
193 | /* Assume canonical format of symbol + constant. | |
194 | Fall through. */ | |
195 | case CONST : | |
196 | return text_segment_operand (XEXP (op, 0), VOIDmode); | |
197 | default : | |
198 | gcc_unreachable (); | |
199 | } | |
200 | }) | |
201 | ||
202 | ||
203 | ;; Predicates for registers. | |
204 | ||
205 | ;; Return true if OP is either the zero constant or a register. | |
206 | (define_predicate "register_or_zero_operand" | |
207 | (ior (match_operand 0 "register_operand") | |
208 | (match_operand 0 "const_zero_operand"))) | |
209 | ||
bef6482d | 210 | (define_predicate "register_or_v9_zero_operand" |
211 | (ior (match_operand 0 "register_operand") | |
212 | (and (match_test "TARGET_V9") | |
213 | (match_operand 0 "const_zero_operand")))) | |
214 | ||
bbfdec17 | 215 | ;; Return true if OP is either the zero constant, the all-ones |
216 | ;; constant, or a register. | |
217 | (define_predicate "register_or_zero_or_all_ones_operand" | |
218 | (ior (match_operand 0 "register_or_zero_operand") | |
219 | (match_operand 0 "const_all_ones_operand"))) | |
220 | ||
27b36d57 | 221 | ;; Return true if OP is a register operand in a floating point register. |
222 | (define_predicate "fp_register_operand" | |
223 | (match_operand 0 "register_operand") | |
224 | { | |
225 | if (GET_CODE (op) == SUBREG) | |
226 | op = SUBREG_REG (op); /* Possibly a MEM */ | |
227 | return REG_P (op) && SPARC_FP_REG_P (REGNO (op)); | |
228 | }) | |
229 | ||
17f446a0 | 230 | ;; Return true if OP is an integer register of the appropriate mode |
231 | ;; for a cstore result. | |
232 | (define_special_predicate "cstore_result_operand" | |
233 | (match_test "register_operand (op, TARGET_ARCH64 ? DImode : SImode)")) | |
234 | ||
27b36d57 | 235 | ;; Return true if OP is a floating point condition code register. |
236 | (define_predicate "fcc_register_operand" | |
94ec1a50 | 237 | (and (match_code "reg") |
238 | (match_test "((unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG) < 4"))) | |
27b36d57 | 239 | |
240 | ;; Return true if OP is the floating point condition code register fcc0. | |
241 | (define_predicate "fcc0_register_operand" | |
94ec1a50 | 242 | (and (match_code "reg") |
243 | (match_test "REGNO (op) == SPARC_FCC_REG"))) | |
27b36d57 | 244 | |
94ec1a50 | 245 | ;; Return true if OP is an integer condition code register. |
246 | (define_predicate "icc_register_operand" | |
247 | (and (match_code "reg") | |
248 | (match_test "REGNO (op) == SPARC_ICC_REG"))) | |
27b36d57 | 249 | |
250 | ;; Return true if OP is an integer or floating point condition code register. | |
251 | (define_predicate "icc_or_fcc_register_operand" | |
94ec1a50 | 252 | (ior (match_operand 0 "icc_register_operand") |
253 | (match_operand 0 "fcc_register_operand"))) | |
27b36d57 | 254 | |
255 | ||
256 | ;; Predicates for arithmetic instructions. | |
257 | ||
258 | ;; Return true if OP is a register, or is a constant that is representable | |
259 | ;; by a 13-bit signed field. This is an acceptable operand for most | |
260 | ;; 3-address instructions. | |
261 | (define_predicate "arith_operand" | |
262 | (ior (match_operand 0 "register_operand") | |
263 | (match_operand 0 "small_int_operand"))) | |
264 | ||
265 | ;; 64-bit: Same as above. | |
266 | ;; 32-bit: Return true if OP is a register, or is a constant that is | |
267 | ;; representable by a couple of 13-bit signed fields. This is an | |
268 | ;; acceptable operand for most 3-address splitters. | |
269 | (define_predicate "arith_double_operand" | |
543530a7 | 270 | (match_code "const_int,reg,subreg") |
27b36d57 | 271 | { |
272 | bool arith_simple_operand = arith_operand (op, mode); | |
273 | HOST_WIDE_INT m1, m2; | |
274 | ||
275 | if (TARGET_ARCH64 || arith_simple_operand) | |
276 | return arith_simple_operand; | |
277 | ||
27b36d57 | 278 | if (GET_CODE (op) != CONST_INT) |
279 | return false; | |
543530a7 | 280 | |
3bb6b41e | 281 | m1 = trunc_int_for_mode (INTVAL (op), SImode); |
282 | m2 = trunc_int_for_mode (INTVAL (op) >> 32, SImode); | |
27b36d57 | 283 | |
284 | return SPARC_SIMM13_P (m1) && SPARC_SIMM13_P (m2); | |
285 | }) | |
286 | ||
287 | ;; Return true if OP is suitable as second operand for add/sub. | |
288 | (define_predicate "arith_add_operand" | |
289 | (ior (match_operand 0 "arith_operand") | |
290 | (match_operand 0 "const_4096_operand"))) | |
635e0e88 | 291 | |
27b36d57 | 292 | ;; Return true if OP is suitable as second double operand for add/sub. |
293 | (define_predicate "arith_double_add_operand" | |
543530a7 | 294 | (match_code "const_int,reg,subreg") |
27b36d57 | 295 | { |
543530a7 | 296 | if (arith_double_operand (op, mode)) |
27b36d57 | 297 | return true; |
298 | ||
299 | return TARGET_ARCH64 && const_4096_operand (op, mode); | |
300 | }) | |
301 | ||
302 | ;; Return true if OP is a register, or is a CONST_INT that can fit in a | |
303 | ;; signed 10-bit immediate field. This is an acceptable SImode operand for | |
304 | ;; the movrcc instructions. | |
305 | (define_predicate "arith10_operand" | |
306 | (ior (match_operand 0 "register_operand") | |
307 | (and (match_code "const_int") | |
308 | (match_test "SPARC_SIMM10_P (INTVAL (op))")))) | |
309 | ||
310 | ;; Return true if OP is a register, or is a CONST_INT that can fit in a | |
311 | ;; signed 11-bit immediate field. This is an acceptable SImode operand for | |
312 | ;; the movcc instructions. | |
313 | (define_predicate "arith11_operand" | |
314 | (ior (match_operand 0 "register_operand") | |
315 | (and (match_code "const_int") | |
316 | (match_test "SPARC_SIMM11_P (INTVAL (op))")))) | |
317 | ||
318 | ;; Return true if OP is a register or a constant for the umul instruction. | |
319 | (define_predicate "uns_arith_operand" | |
320 | (ior (match_operand 0 "register_operand") | |
321 | (match_operand 0 "uns_small_int_operand"))) | |
322 | ||
6c940e8d | 323 | ;; Return true if OP is a register, or is a CONST_INT that can fit in a |
324 | ;; signed 5-bit immediate field. This is an acceptable second operand for | |
325 | ;; the cbcond instructions. | |
326 | (define_predicate "arith5_operand" | |
327 | (ior (match_operand 0 "register_operand") | |
328 | (and (match_code "const_int") | |
329 | (match_test "SPARC_SIMM5_P (INTVAL (op))")))) | |
330 | ||
95f09db7 | 331 | ;; Return true if OP is a constant in the range 0..7. This is an |
332 | ;; acceptable second operand for dictunpack instructions setting a | |
333 | ;; V8QI mode in the destination register. | |
334 | (define_predicate "imm5_operand_dictunpack8" | |
335 | (and (match_code "const_int") | |
336 | (match_test "(INTVAL (op) >= 0 && INTVAL (op) < 8)"))) | |
337 | ||
338 | ;; Return true if OP is a constant in the range 7..15. This is an | |
339 | ;; acceptable second operand for dictunpack instructions setting a | |
340 | ;; V4HI mode in the destination register. | |
341 | (define_predicate "imm5_operand_dictunpack16" | |
342 | (and (match_code "const_int") | |
343 | (match_test "(INTVAL (op) >= 8 && INTVAL (op) < 16)"))) | |
344 | ||
345 | ;; Return true if OP is a constant in the range 15..31. This is an | |
346 | ;; acceptable second operand for dictunpack instructions setting a | |
347 | ;; V2SI mode in the destination register. | |
348 | (define_predicate "imm5_operand_dictunpack32" | |
349 | (and (match_code "const_int") | |
350 | (match_test "(INTVAL (op) >= 16 && INTVAL (op) < 32)"))) | |
351 | ||
352 | ;; Return true if OP is a constant that is representable by a 2-bit | |
353 | ;; unsigned field. This is an acceptable third operand for | |
354 | ;; fpcmp*shl instructions. | |
355 | (define_predicate "imm2_operand" | |
356 | (and (match_code "const_int") | |
357 | (match_test "SPARC_IMM2_P (INTVAL (op))"))) | |
27b36d57 | 358 | |
2bd0405c | 359 | ;; Predicates for miscellaneous instructions. |
27b36d57 | 360 | |
361 | ;; Return true if OP is valid for the lhs of a comparison insn. | |
362 | (define_predicate "compare_operand" | |
3bb6b41e | 363 | (match_code "reg,subreg,zero_extract") |
27b36d57 | 364 | { |
365 | if (GET_CODE (op) == ZERO_EXTRACT) | |
366 | return (register_operand (XEXP (op, 0), mode) | |
367 | && small_int_operand (XEXP (op, 1), mode) | |
368 | && small_int_operand (XEXP (op, 2), mode) | |
369 | /* This matches cmp_zero_extract. */ | |
370 | && ((mode == SImode | |
371 | && INTVAL (XEXP (op, 2)) > 19) | |
372 | /* This matches cmp_zero_extract_sp64. */ | |
373 | || (TARGET_ARCH64 | |
374 | && mode == DImode | |
375 | && INTVAL (XEXP (op, 2)) > 51))); | |
543530a7 | 376 | |
377 | return register_operand (op, mode); | |
27b36d57 | 378 | }) |
379 | ||
380 | ;; Return true if OP is a valid operand for the source of a move insn. | |
381 | (define_predicate "input_operand" | |
382 | (match_code "const_int,const_double,const_vector,reg,subreg,mem") | |
383 | { | |
384 | enum mode_class mclass; | |
385 | ||
386 | /* If both modes are non-void they must be the same. */ | |
387 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) | |
388 | return false; | |
389 | ||
b6a32a23 | 390 | mclass = GET_MODE_CLASS (mode); |
391 | ||
27b36d57 | 392 | /* Allow any 1-instruction integer constant. */ |
b6a32a23 | 393 | if (mclass == MODE_INT |
635e0e88 | 394 | && mode != TImode |
27b36d57 | 395 | && (small_int_operand (op, mode) || const_high_operand (op, mode))) |
396 | return true; | |
397 | ||
398 | /* If 32-bit mode and this is a DImode constant, allow it | |
399 | so that the splits can be generated. */ | |
543530a7 | 400 | if (TARGET_ARCH32 && mode == DImode && GET_CODE (op) == CONST_INT) |
27b36d57 | 401 | return true; |
402 | ||
b8c71fd1 | 403 | /* Allow FP constants to be built in integer registers. */ |
e76144f9 | 404 | if (mclass == MODE_FLOAT && GET_CODE (op) == CONST_DOUBLE) |
405 | return true; | |
406 | ||
635e0e88 | 407 | if (mclass == MODE_VECTOR_INT && const_all_ones_operand (op, mode)) |
27b36d57 | 408 | return true; |
409 | ||
635e0e88 | 410 | if (register_or_zero_operand (op, mode)) |
b6a32a23 | 411 | return true; |
412 | ||
413 | /* If this is a SUBREG, look inside so that we handle paradoxical ones. */ | |
27b36d57 | 414 | if (GET_CODE (op) == SUBREG) |
415 | op = SUBREG_REG (op); | |
416 | ||
417 | /* Check for valid MEM forms. */ | |
418 | if (GET_CODE (op) == MEM) | |
b8c71fd1 | 419 | { |
420 | /* Except when LRA is precisely working hard to make them valid | |
421 | and relying entirely on the constraints. */ | |
422 | if (lra_in_progress) | |
423 | return true; | |
424 | ||
425 | return memory_address_p (mode, XEXP (op, 0)); | |
426 | } | |
27b36d57 | 427 | |
428 | return false; | |
429 | }) | |
430 | ||
431 | ;; Return true if OP is an address suitable for a call insn. | |
432 | ;; Call insn on SPARC can take a PC-relative constant address | |
433 | ;; or any regular memory address. | |
434 | (define_predicate "call_address_operand" | |
435 | (ior (match_operand 0 "symbolic_operand") | |
436 | (match_test "memory_address_p (Pmode, op)"))) | |
437 | ||
438 | ;; Return true if OP is an operand suitable for a call insn. | |
439 | (define_predicate "call_operand" | |
440 | (and (match_code "mem") | |
441 | (match_test "call_address_operand (XEXP (op, 0), mode)"))) | |
442 | ||
443 | ||
66533357 | 444 | (define_predicate "mem_noofs_operand" |
445 | (and (match_code "mem") | |
446 | (match_code "reg" "0"))) | |
447 | ||
27b36d57 | 448 | ;; Predicates for operators. |
449 | ||
94ec1a50 | 450 | ;; Return true if OP is a valid comparison operator for CCNZmode. |
451 | (define_predicate "nz_comparison_operator" | |
452 | (match_code "eq,ne,lt,ge")) | |
453 | ||
454 | ;; Return true if OP is a valid comparison operator for CCCmode. | |
455 | (define_predicate "c_comparison_operator" | |
456 | (match_code "ltu,geu")) | |
457 | ||
121d313b | 458 | ;; Return true if OP is a valid comparison operator for CCVmode. |
459 | (define_predicate "v_comparison_operator" | |
460 | (match_code "eq,ne")) | |
461 | ||
94ec1a50 | 462 | ;; Return true if OP is an integer comparison operator. This allows |
463 | ;; the use of MATCH_OPERATOR to recognize all the branch insns. | |
464 | (define_predicate "icc_comparison_operator" | |
465 | (match_operand 0 "ordered_comparison_operator") | |
27b36d57 | 466 | { |
94ec1a50 | 467 | switch (GET_MODE (XEXP (op, 0))) |
468 | { | |
916ace94 | 469 | case E_CCmode: |
470 | case E_CCXmode: | |
94ec1a50 | 471 | return true; |
916ace94 | 472 | case E_CCNZmode: |
473 | case E_CCXNZmode: | |
94ec1a50 | 474 | return nz_comparison_operator (op, mode); |
916ace94 | 475 | case E_CCCmode: |
476 | case E_CCXCmode: | |
94ec1a50 | 477 | return c_comparison_operator (op, mode); |
916ace94 | 478 | case E_CCVmode: |
479 | case E_CCXVmode: | |
121d313b | 480 | return v_comparison_operator (op, mode); |
94ec1a50 | 481 | default: |
482 | return false; | |
483 | } | |
27b36d57 | 484 | }) |
485 | ||
94ec1a50 | 486 | ;; Return true if OP is a FP comparison operator. |
487 | (define_predicate "fcc_comparison_operator" | |
488 | (match_operand 0 "comparison_operator") | |
27b36d57 | 489 | { |
94ec1a50 | 490 | switch (GET_MODE (XEXP (op, 0))) |
491 | { | |
916ace94 | 492 | case E_CCFPmode: |
493 | case E_CCFPEmode: | |
94ec1a50 | 494 | return true; |
495 | default: | |
496 | return false; | |
497 | } | |
27b36d57 | 498 | }) |
499 | ||
94ec1a50 | 500 | ;; Return true if OP is an integer or FP comparison operator. This allows |
501 | ;; the use of MATCH_OPERATOR to recognize all the conditional move insns. | |
502 | (define_predicate "icc_or_fcc_comparison_operator" | |
503 | (ior (match_operand 0 "icc_comparison_operator") | |
504 | (match_operand 0 "fcc_comparison_operator"))) | |
505 | ||
506 | ;; Return true if OP is an integer comparison operator for V9. | |
507 | (define_predicate "v9_comparison_operator" | |
508 | (and (match_operand 0 "ordered_comparison_operator") | |
509 | (match_test "TARGET_V9"))) | |
510 | ||
27b36d57 | 511 | ;; Return true if OP is a comparison operator suitable for use in V9 |
512 | ;; conditional move or branch on register contents instructions. | |
94ec1a50 | 513 | (define_predicate "v9_register_comparison_operator" |
27b36d57 | 514 | (match_code "eq,ne,ge,lt,le,gt")) |
515 | ||
516 | ;; Return true if OP is an operator which can set the condition codes | |
94ec1a50 | 517 | ;; explicitly. We do not include PLUS/MINUS/NEG/ASHIFT because these |
518 | ;; require CCNZmode, which we handle explicitly. | |
27b36d57 | 519 | (define_predicate "cc_arith_operator" |
520 | (match_code "and,ior,xor")) | |
521 | ||
522 | ;; Return true if OP is an operator which can bitwise complement its | |
523 | ;; second operand and set the condition codes explicitly. | |
524 | ;; XOR is not here because combine canonicalizes (xor (not ...) ...) | |
94ec1a50 | 525 | ;; and (xor ... (not ...)) to (not (xor ...)). |
27b36d57 | 526 | (define_predicate "cc_arith_not_operator" |
527 | (match_code "and,ior")) |