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bfe73f0a 1/* Prototypes of target machine for SPARC.
71e45bc2 2 Copyright (C) 1999, 2000, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011,
3 2012 Free Software Foundation, Inc.
075136a2 4 Contributed by Michael Tiemann (tiemann@cygnus.com).
bfe73f0a 5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
075136a2 6 at Cygnus Support.
7
aea155fd 8This file is part of GCC.
075136a2 9
aea155fd 10GCC is free software; you can redistribute it and/or modify
075136a2 11it under the terms of the GNU General Public License as published by
038d1e19 12the Free Software Foundation; either version 3, or (at your option)
075136a2 13any later version.
14
aea155fd 15GCC is distributed in the hope that it will be useful,
075136a2 16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
038d1e19 21along with GCC; see the file COPYING3. If not see
22<http://www.gnu.org/licenses/>. */
075136a2 23
24#ifndef __SPARC_PROTOS_H__
25#define __SPARC_PROTOS_H__
26
27#ifdef TREE_CODE
075136a2 28#ifdef RTX_CODE
ebe0bc1f 29extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
075136a2 30#endif
ebe0bc1f 31extern unsigned long sparc_type_code (tree);
075136a2 32#ifdef ARGS_SIZE_RTX
33/* expr.h defines ARGS_SIZE_RTX and `enum direction' */
fb80456a 34extern enum direction function_arg_padding (enum machine_mode, const_tree);
075136a2 35#endif /* ARGS_SIZE_RTX */
36#endif /* TREE_CODE */
37
ebe0bc1f 38extern void order_regs_for_local_alloc (void);
f317b732 39extern HOST_WIDE_INT sparc_compute_frame_size (HOST_WIDE_INT, int);
1ecd9aaf 40extern int sparc_initial_elimination_offset (int);
f317b732 41extern void sparc_expand_prologue (void);
47529489 42extern void sparc_flat_expand_prologue (void);
43extern void sparc_expand_epilogue (bool);
44extern void sparc_flat_expand_epilogue (bool);
644b3b25 45extern bool sparc_can_use_return_insn_p (void);
ebe0bc1f 46extern int check_pic (int);
ebe0bc1f 47extern void sparc_profile_hook (int);
48extern void sparc_override_options (void);
ebe0bc1f 49extern void sparc_output_scratch_registers (FILE *);
9e64c9a4 50extern void sparc_target_macros (void);
075136a2 51
52#ifdef RTX_CODE
ebe0bc1f 53extern enum machine_mode select_cc_mode (enum rtx_code, rtx, rtx);
075136a2 54/* Define the function that build the compare insn for scc and bcc. */
74f4459c 55extern rtx gen_compare_reg (rtx cmp);
56extern rtx sparc_emit_float_lib_cmp (rtx, rtx, enum rtx_code);
520b7351 57extern void sparc_emit_floatunsdi (rtx [2], enum machine_mode);
58extern void sparc_emit_fixunsdi (rtx [2], enum machine_mode);
ebe0bc1f 59extern void emit_tfmode_binop (enum rtx_code, rtx *);
60extern void emit_tfmode_unop (enum rtx_code, rtx *);
61extern void emit_tfmode_cvt (enum rtx_code, rtx *);
05b3a83f 62extern bool constant_address_p (rtx);
63extern bool legitimate_pic_operand_p (rtx);
bb269b2f 64extern rtx sparc_legitimize_reload_address (rtx, enum machine_mode, int, int,
65 int, int *win);
d1ff492e 66extern void load_got_register (void);
723e1902 67extern void sparc_emit_call_insn (rtx, rtx);
ebe0bc1f 68extern void sparc_defer_case_vector (rtx, rtx, int);
b6a32a23 69extern bool sparc_expand_move (enum machine_mode, rtx *);
ebe0bc1f 70extern void sparc_emit_set_symbolic_const64 (rtx, rtx, rtx);
71extern int sparc_splitdi_legitimate (rtx, rtx);
f8b63509 72extern int sparc_split_regreg_legitimate (rtx, rtx);
ebe0bc1f 73extern int sparc_absnegfloat_split_legitimate (rtx, rtx);
6c940e8d 74extern const char *output_ubranch (rtx, rtx);
461a1f48 75extern const char *output_cbranch (rtx, rtx, int, int, int, rtx);
f317b732 76extern const char *output_return (rtx);
ebe0bc1f 77extern const char *output_sibcall (rtx, rtx);
091f282f 78extern const char *output_v8plus_shift (rtx, rtx *, const char *);
79extern const char *output_v8plus_mult (rtx, rtx *, const char *);
461a1f48 80extern const char *output_v9branch (rtx, rtx, int, int, int, int, rtx);
f164c08a 81extern const char *output_probe_stack_range (rtx, rtx);
6c940e8d 82extern const char *output_cbcond (rtx, rtx, rtx);
74f4459c 83extern bool emit_scc_insn (rtx []);
84extern void emit_conditional_branch_insn (rtx []);
ebe0bc1f 85extern int mems_ok_for_ldd_peep (rtx, rtx, rtx);
ebe0bc1f 86extern int empty_delay_slot (rtx);
6c940e8d 87extern int emit_cbcond_nop (rtx);
f317b732 88extern int eligible_for_return_delay (rtx);
ebe0bc1f 89extern int eligible_for_sibcall_delay (rtx);
05b3a83f 90extern int tls_call_delay (rtx);
ebe0bc1f 91extern int emit_move_sequence (rtx, enum machine_mode);
92extern int fp_sethi_p (rtx);
93extern int fp_mov_p (rtx);
94extern int fp_high_losum_p (rtx);
95extern int mem_min_alignment (rtx, int);
96extern int pic_address_needs_scratch (rtx);
ebe0bc1f 97extern int register_ok_for_ldd (rtx);
187a5b29 98extern int memory_ok_for_ldd (rtx);
ebe0bc1f 99extern int registers_ok_for_ldd_peep (rtx, rtx);
ebe0bc1f 100extern int v9_regcmp_p (enum rtx_code);
075136a2 101/* Function used for V8+ code generation. Returns 1 if the high
102 32 bits of REG are 0 before INSN. */
ebe0bc1f 103extern int sparc_check_64 (rtx, rtx);
104extern rtx gen_df_reg (rtx, int);
66533357 105extern void sparc_expand_compare_and_swap (rtx op[]);
bc963728 106extern void sparc_expand_vector_init (rtx, rtx);
05d36c46 107extern void sparc_expand_vec_perm_bmask(enum machine_mode, rtx);
6c53772f 108extern bool sparc_expand_conditional_move (enum machine_mode, rtx *);
efa273f5 109extern void sparc_expand_vcond (enum machine_mode, rtx *, int, int);
8e1606d2 110unsigned int sparc_regmode_natural_size (enum machine_mode);
111bool sparc_modes_tieable_p (enum machine_mode, enum machine_mode);
075136a2 112#endif /* RTX_CODE */
113
a3664b60 114extern void sparc_emit_membar_for_model (enum memmodel, int, int);
115
075136a2 116#endif /* __SPARC_PROTOS_H__ */