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6a151f87 | 1 | /* Prototypes of target machine for SPARC. |
23a5b65a | 2 | Copyright (C) 1999-2014 Free Software Foundation, Inc. |
b1474bb7 | 3 | Contributed by Michael Tiemann (tiemann@cygnus.com). |
6a151f87 | 4 | 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
b1474bb7 KG |
5 | at Cygnus Support. |
6 | ||
de0a398e | 7 | This file is part of GCC. |
b1474bb7 | 8 | |
de0a398e | 9 | GCC is free software; you can redistribute it and/or modify |
b1474bb7 | 10 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 11 | the Free Software Foundation; either version 3, or (at your option) |
b1474bb7 KG |
12 | any later version. |
13 | ||
de0a398e | 14 | GCC is distributed in the hope that it will be useful, |
b1474bb7 KG |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
b1474bb7 KG |
22 | |
23 | #ifndef __SPARC_PROTOS_H__ | |
24 | #define __SPARC_PROTOS_H__ | |
25 | ||
26 | #ifdef TREE_CODE | |
b1474bb7 | 27 | #ifdef RTX_CODE |
e80d5f80 | 28 | extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree); |
b1474bb7 | 29 | #endif |
e80d5f80 | 30 | extern unsigned long sparc_type_code (tree); |
b1474bb7 KG |
31 | #ifdef ARGS_SIZE_RTX |
32 | /* expr.h defines ARGS_SIZE_RTX and `enum direction' */ | |
586de218 | 33 | extern enum direction function_arg_padding (enum machine_mode, const_tree); |
b1474bb7 KG |
34 | #endif /* ARGS_SIZE_RTX */ |
35 | #endif /* TREE_CODE */ | |
36 | ||
e80d5f80 | 37 | extern void order_regs_for_local_alloc (void); |
9ac617d4 | 38 | extern HOST_WIDE_INT sparc_compute_frame_size (HOST_WIDE_INT, int); |
9e6a4b77 | 39 | extern int sparc_initial_elimination_offset (int); |
9ac617d4 | 40 | extern void sparc_expand_prologue (void); |
b11b0904 EB |
41 | extern void sparc_flat_expand_prologue (void); |
42 | extern void sparc_expand_epilogue (bool); | |
43 | extern void sparc_flat_expand_epilogue (bool); | |
5be9b7a1 | 44 | extern bool sparc_can_use_return_insn_p (void); |
e80d5f80 | 45 | extern int check_pic (int); |
e80d5f80 KG |
46 | extern void sparc_profile_hook (int); |
47 | extern void sparc_override_options (void); | |
e80d5f80 | 48 | extern void sparc_output_scratch_registers (FILE *); |
8d12174d | 49 | extern void sparc_target_macros (void); |
b1474bb7 KG |
50 | |
51 | #ifdef RTX_CODE | |
e80d5f80 | 52 | extern enum machine_mode select_cc_mode (enum rtx_code, rtx, rtx); |
b1474bb7 | 53 | /* Define the function that build the compare insn for scc and bcc. */ |
f90b7a5a PB |
54 | extern rtx gen_compare_reg (rtx cmp); |
55 | extern rtx sparc_emit_float_lib_cmp (rtx, rtx, enum rtx_code); | |
b178305d EB |
56 | extern void sparc_emit_floatunsdi (rtx [2], enum machine_mode); |
57 | extern void sparc_emit_fixunsdi (rtx [2], enum machine_mode); | |
e80d5f80 KG |
58 | extern void emit_tfmode_binop (enum rtx_code, rtx *); |
59 | extern void emit_tfmode_unop (enum rtx_code, rtx *); | |
60 | extern void emit_tfmode_cvt (enum rtx_code, rtx *); | |
5751a10b JJ |
61 | extern bool constant_address_p (rtx); |
62 | extern bool legitimate_pic_operand_p (rtx); | |
58e6223e EB |
63 | extern rtx sparc_legitimize_reload_address (rtx, enum machine_mode, int, int, |
64 | int, int *win); | |
bc6d3f91 | 65 | extern void load_got_register (void); |
1910440e | 66 | extern void sparc_emit_call_insn (rtx, rtx); |
e80d5f80 | 67 | extern void sparc_defer_case_vector (rtx, rtx, int); |
bea5071f | 68 | extern bool sparc_expand_move (enum machine_mode, rtx *); |
e80d5f80 KG |
69 | extern void sparc_emit_set_symbolic_const64 (rtx, rtx, rtx); |
70 | extern int sparc_splitdi_legitimate (rtx, rtx); | |
b1fc9f8b | 71 | extern int sparc_split_regreg_legitimate (rtx, rtx); |
e1faf324 DM |
72 | extern const char *output_ubranch (rtx, rtx_insn *); |
73 | extern const char *output_cbranch (rtx, rtx, int, int, int, rtx_insn *); | |
74 | extern const char *output_return (rtx_insn *); | |
75 | extern const char *output_sibcall (rtx_insn *, rtx); | |
76 | extern const char *output_v8plus_shift (rtx_insn *, rtx *, const char *); | |
77 | extern const char *output_v8plus_mult (rtx_insn *, rtx *, const char *); | |
78 | extern const char *output_v9branch (rtx, rtx, int, int, int, int, rtx_insn *); | |
260c8ba3 | 79 | extern const char *output_probe_stack_range (rtx, rtx); |
e1faf324 | 80 | extern const char *output_cbcond (rtx, rtx, rtx_insn *); |
f90b7a5a PB |
81 | extern bool emit_scc_insn (rtx []); |
82 | extern void emit_conditional_branch_insn (rtx []); | |
b5ccb9ed | 83 | extern int registers_ok_for_ldd_peep (rtx, rtx); |
e80d5f80 | 84 | extern int mems_ok_for_ldd_peep (rtx, rtx, rtx); |
b5ccb9ed | 85 | extern rtx widen_mem_for_ldd_peep (rtx, rtx, enum machine_mode); |
b32d5189 | 86 | extern int empty_delay_slot (rtx_insn *); |
8b98b5fd | 87 | extern int emit_cbcond_nop (rtx); |
890fa568 | 88 | extern int eligible_for_call_delay (rtx); |
9ac617d4 | 89 | extern int eligible_for_return_delay (rtx); |
e80d5f80 KG |
90 | extern int eligible_for_sibcall_delay (rtx); |
91 | extern int emit_move_sequence (rtx, enum machine_mode); | |
92 | extern int fp_sethi_p (rtx); | |
93 | extern int fp_mov_p (rtx); | |
94 | extern int fp_high_losum_p (rtx); | |
95 | extern int mem_min_alignment (rtx, int); | |
96 | extern int pic_address_needs_scratch (rtx); | |
e80d5f80 | 97 | extern int register_ok_for_ldd (rtx); |
157891a3 | 98 | extern int memory_ok_for_ldd (rtx); |
e80d5f80 | 99 | extern int v9_regcmp_p (enum rtx_code); |
b1474bb7 KG |
100 | /* Function used for V8+ code generation. Returns 1 if the high |
101 | 32 bits of REG are 0 before INSN. */ | |
b32d5189 | 102 | extern int sparc_check_64 (rtx, rtx_insn *); |
e80d5f80 | 103 | extern rtx gen_df_reg (rtx, int); |
470b6e51 | 104 | extern void sparc_expand_compare_and_swap (rtx op[]); |
e00560c2 | 105 | extern void sparc_expand_vector_init (rtx, rtx); |
9d4dedaa | 106 | extern void sparc_expand_vec_perm_bmask(enum machine_mode, rtx); |
bf84f42d | 107 | extern bool sparc_expand_conditional_move (enum machine_mode, rtx *); |
1f9ed162 | 108 | extern void sparc_expand_vcond (enum machine_mode, rtx *, int, int); |
98ccb32d DM |
109 | unsigned int sparc_regmode_natural_size (enum machine_mode); |
110 | bool sparc_modes_tieable_p (enum machine_mode, enum machine_mode); | |
b1474bb7 KG |
111 | #endif /* RTX_CODE */ |
112 | ||
9a738908 RH |
113 | extern void sparc_emit_membar_for_model (enum memmodel, int, int); |
114 | ||
b1474bb7 | 115 | #endif /* __SPARC_PROTOS_H__ */ |