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ab835497 | 1 | /* Subroutines for insn-output.c for Sun SPARC. |
4592bdcb | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3276910d | 3 | 1999, 2000, 2001 Free Software Foundation, Inc. |
ab835497 | 4 | Contributed by Michael Tiemann (tiemann@cygnus.com) |
61a55e8b DE |
5 | 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
6 | at Cygnus Support. | |
ab835497 RK |
7 | |
8 | This file is part of GNU CC. | |
9 | ||
10 | GNU CC is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GNU CC is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, |
23 | Boston, MA 02111-1307, USA. */ | |
ab835497 | 24 | |
ab835497 | 25 | #include "config.h" |
284d86e9 | 26 | #include "system.h" |
210aa14a | 27 | #include "tree.h" |
ab835497 RK |
28 | #include "rtl.h" |
29 | #include "regs.h" | |
30 | #include "hard-reg-set.h" | |
31 | #include "real.h" | |
32 | #include "insn-config.h" | |
33 | #include "conditions.h" | |
ab835497 RK |
34 | #include "output.h" |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
49ad7cfa | 37 | #include "function.h" |
ab835497 | 38 | #include "expr.h" |
e78d8e51 ZW |
39 | #include "optabs.h" |
40 | #include "libfuncs.h" | |
ab835497 | 41 | #include "recog.h" |
487a6e06 | 42 | #include "toplev.h" |
d07d525a | 43 | #include "ggc.h" |
b1474bb7 | 44 | #include "tm_p.h" |
e78d8e51 | 45 | #include "debug.h" |
672a6f42 NB |
46 | #include "target.h" |
47 | #include "target-def.h" | |
ab835497 | 48 | |
61a55e8b DE |
49 | /* 1 if the caller has placed an "unimp" insn immediately after the call. |
50 | This is used in v8 code when calling a function that returns a structure. | |
06b967f9 RK |
51 | v9 doesn't have this. Be careful to have this test be the same as that |
52 | used on the call. */ | |
53 | ||
54 | #define SKIP_CALLERS_UNIMP_P \ | |
55 | (!TARGET_ARCH64 && current_function_returns_struct \ | |
56 | && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
57 | && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
58 | == INTEGER_CST)) | |
61a55e8b | 59 | |
ab835497 RK |
60 | /* Global variables for machine-dependent things. */ |
61 | ||
61a55e8b DE |
62 | /* Size of frame. Need to know this to emit return insns from leaf procedures. |
63 | ACTUAL_FSIZE is set by compute_frame_size() which is called during the | |
64 | reload pass. This is important as the value is later used in insn | |
65 | scheduling (to see what can go in a delay slot). | |
66 | APPARENT_FSIZE is the size of the stack less the register save area and less | |
67 | the outgoing argument area. It is used when saving call preserved regs. */ | |
68 | static int apparent_fsize; | |
69 | static int actual_fsize; | |
70 | ||
e48addee JJ |
71 | /* Number of live general or floating point registers needed to be saved |
72 | (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */ | |
73 | static int num_gfregs; | |
74 | ||
ab835497 RK |
75 | /* Save the operands last given to a compare for use when we |
76 | generate a scc or bcc insn. */ | |
77 | ||
78 | rtx sparc_compare_op0, sparc_compare_op1; | |
79 | ||
80 | /* We may need an epilogue if we spill too many registers. | |
81 | If this is non-zero, then we branch here for the epilogue. */ | |
82 | static rtx leaf_label; | |
83 | ||
84 | #ifdef LEAF_REGISTERS | |
85 | ||
86 | /* Vector to say how input registers are mapped to output | |
87 | registers. FRAME_POINTER_REGNUM cannot be remapped by | |
88 | this function to eliminate it. You must use -fomit-frame-pointer | |
89 | to get that. */ | |
90 | char leaf_reg_remap[] = | |
91 | { 0, 1, 2, 3, 4, 5, 6, 7, | |
92 | -1, -1, -1, -1, -1, -1, 14, -1, | |
93 | -1, -1, -1, -1, -1, -1, -1, -1, | |
94 | 8, 9, 10, 11, 12, 13, -1, 15, | |
95 | ||
96 | 32, 33, 34, 35, 36, 37, 38, 39, | |
97 | 40, 41, 42, 43, 44, 45, 46, 47, | |
98 | 48, 49, 50, 51, 52, 53, 54, 55, | |
61a55e8b DE |
99 | 56, 57, 58, 59, 60, 61, 62, 63, |
100 | 64, 65, 66, 67, 68, 69, 70, 71, | |
101 | 72, 73, 74, 75, 76, 77, 78, 79, | |
102 | 80, 81, 82, 83, 84, 85, 86, 87, | |
103 | 88, 89, 90, 91, 92, 93, 94, 95, | |
c4ce6853 | 104 | 96, 97, 98, 99, 100}; |
ab835497 | 105 | |
7d167afd JJ |
106 | /* Vector, indexed by hard register number, which contains 1 |
107 | for a register that is allowable in a candidate for leaf | |
108 | function treatment. */ | |
109 | char sparc_leaf_regs[] = | |
110 | { 1, 1, 1, 1, 1, 1, 1, 1, | |
111 | 0, 0, 0, 0, 0, 0, 1, 0, | |
112 | 0, 0, 0, 0, 0, 0, 0, 0, | |
113 | 1, 1, 1, 1, 1, 1, 0, 1, | |
114 | 1, 1, 1, 1, 1, 1, 1, 1, | |
115 | 1, 1, 1, 1, 1, 1, 1, 1, | |
116 | 1, 1, 1, 1, 1, 1, 1, 1, | |
117 | 1, 1, 1, 1, 1, 1, 1, 1, | |
118 | 1, 1, 1, 1, 1, 1, 1, 1, | |
119 | 1, 1, 1, 1, 1, 1, 1, 1, | |
120 | 1, 1, 1, 1, 1, 1, 1, 1, | |
121 | 1, 1, 1, 1, 1, 1, 1, 1, | |
122 | 1, 1, 1, 1, 1}; | |
123 | ||
6a4bb1fa | 124 | #endif |
ab835497 | 125 | |
ab835497 RK |
126 | /* Name of where we pretend to think the frame pointer points. |
127 | Normally, this is "%fp", but if we are in a leaf procedure, | |
61a55e8b DE |
128 | this is "%sp+something". We record "something" separately as it may be |
129 | too big for reg+constant addressing. */ | |
130 | ||
3bb5de61 | 131 | static const char *frame_base_name; |
61a55e8b | 132 | static int frame_base_offset; |
ab835497 | 133 | |
f6da8bc3 KG |
134 | static void sparc_init_modes PARAMS ((void)); |
135 | static int save_regs PARAMS ((FILE *, int, int, const char *, | |
c85f7c16 | 136 | int, int, int)); |
f6da8bc3 KG |
137 | static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int)); |
138 | static void build_big_number PARAMS ((FILE *, int, const char *)); | |
139 | static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *, | |
c85f7c16 JL |
140 | enum machine_mode, tree, int, int, |
141 | int *, int *)); | |
8947065c | 142 | |
f6da8bc3 KG |
143 | static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
144 | static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); | |
145 | static int ultrasparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); | |
146 | ||
147 | static void sparc_output_addr_vec PARAMS ((rtx)); | |
148 | static void sparc_output_addr_diff_vec PARAMS ((rtx)); | |
149 | static void sparc_output_deferred_case_vectors PARAMS ((void)); | |
150 | static void sparc_add_gc_roots PARAMS ((void)); | |
151 | static void mark_ultrasparc_pipeline_state PARAMS ((void *)); | |
152 | static int check_return_regs PARAMS ((rtx)); | |
153 | static int epilogue_renumber PARAMS ((rtx *, int)); | |
154 | static int ultra_cmove_results_ready_p PARAMS ((rtx)); | |
155 | static int ultra_fpmode_conflict_exists PARAMS ((enum machine_mode)); | |
156 | static rtx *ultra_find_type PARAMS ((int, rtx *, int)); | |
157 | static void ultra_build_types_avail PARAMS ((rtx *, int)); | |
158 | static void ultra_flush_pipeline PARAMS ((void)); | |
159 | static void ultra_rescan_pipeline_state PARAMS ((rtx *, int)); | |
4df1190a | 160 | static int set_extends PARAMS ((rtx)); |
e77d72cb | 161 | static void output_restore_regs PARAMS ((FILE *, int)); |
08c148a8 NB |
162 | static void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
163 | static void sparc_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
164 | static void sparc_flat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
165 | static void sparc_flat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); | |
166 | static void sparc_nonflat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT, | |
167 | int)); | |
168 | static void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT, | |
169 | int)); | |
715bdd29 | 170 | static void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int)); |
c237e94a ZW |
171 | |
172 | static void ultrasparc_sched_reorder PARAMS ((FILE *, int, rtx *, int)); | |
173 | static int ultrasparc_variable_issue PARAMS ((rtx)); | |
174 | static void ultrasparc_sched_init PARAMS ((void)); | |
175 | ||
176 | static int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); | |
177 | static int sparc_issue_rate PARAMS ((void)); | |
178 | static int sparc_variable_issue PARAMS ((FILE *, int, rtx, int)); | |
179 | static void sparc_sched_init PARAMS ((FILE *, int, int)); | |
180 | static int sparc_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int)); | |
61a55e8b DE |
181 | \f |
182 | /* Option handling. */ | |
183 | ||
a0a301fc | 184 | /* Code model option as passed by user. */ |
3bb5de61 | 185 | const char *sparc_cmodel_string; |
a0a301fc DE |
186 | /* Parsed value. */ |
187 | enum cmodel sparc_cmodel; | |
188 | ||
1cb36a98 RH |
189 | char sparc_hard_reg_printed[8]; |
190 | ||
16956f6e DE |
191 | struct sparc_cpu_select sparc_select[] = |
192 | { | |
193 | /* switch name, tune arch */ | |
194 | { (char *)0, "default", 1, 1 }, | |
195 | { (char *)0, "-mcpu=", 1, 1 }, | |
196 | { (char *)0, "-mtune=", 1, 0 }, | |
db3d4438 | 197 | { 0, 0, 0, 0 } |
16956f6e | 198 | }; |
733f53f5 | 199 | |
16956f6e DE |
200 | /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ |
201 | enum processor_type sparc_cpu; | |
672a6f42 NB |
202 | \f |
203 | /* Initialize the GCC target structure. */ | |
08c148a8 NB |
204 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
205 | #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue | |
206 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
207 | #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue | |
733f53f5 | 208 | |
c237e94a ZW |
209 | #undef TARGET_SCHED_ADJUST_COST |
210 | #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost | |
211 | #undef TARGET_SCHED_ISSUE_RATE | |
212 | #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate | |
213 | #undef TARGET_SCHED_VARIABLE_ISSUE | |
214 | #define TARGET_SCHED_VARIABLE_ISSUE sparc_variable_issue | |
215 | #undef TARGET_SCHED_INIT | |
216 | #define TARGET_SCHED_INIT sparc_sched_init | |
217 | #undef TARGET_SCHED_REORDER | |
218 | #define TARGET_SCHED_REORDER sparc_sched_reorder | |
219 | ||
f6897b10 | 220 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 221 | \f |
61a55e8b DE |
222 | /* Validate and override various options, and do some machine dependent |
223 | initialization. */ | |
224 | ||
225 | void | |
226 | sparc_override_options () | |
227 | { | |
a0a301fc | 228 | static struct code_model { |
3bb5de61 | 229 | const char *name; |
a0a301fc DE |
230 | int value; |
231 | } cmodels[] = { | |
232 | { "32", CM_32 }, | |
233 | { "medlow", CM_MEDLOW }, | |
234 | { "medmid", CM_MEDMID }, | |
235 | { "medany", CM_MEDANY }, | |
236 | { "embmedany", CM_EMBMEDANY }, | |
237 | { 0, 0 } | |
238 | }; | |
239 | struct code_model *cmodel; | |
16956f6e | 240 | /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ |
733f53f5 DE |
241 | static struct cpu_default { |
242 | int cpu; | |
3bb5de61 | 243 | const char *name; |
733f53f5 | 244 | } cpu_default[] = { |
a0a301fc | 245 | /* There must be one entry here for each TARGET_CPU value. */ |
16956f6e | 246 | { TARGET_CPU_sparc, "cypress" }, |
3592ea0d | 247 | { TARGET_CPU_sparclet, "tsc701" }, |
16956f6e | 248 | { TARGET_CPU_sparclite, "f930" }, |
a0a301fc | 249 | { TARGET_CPU_v8, "v8" }, |
8947065c RH |
250 | { TARGET_CPU_hypersparc, "hypersparc" }, |
251 | { TARGET_CPU_sparclite86x, "sparclite86x" }, | |
a0a301fc DE |
252 | { TARGET_CPU_supersparc, "supersparc" }, |
253 | { TARGET_CPU_v9, "v9" }, | |
ba542005 | 254 | { TARGET_CPU_ultrasparc, "ultrasparc" }, |
db3d4438 | 255 | { 0, 0 } |
733f53f5 | 256 | }; |
16956f6e DE |
257 | struct cpu_default *def; |
258 | /* Table of values for -m{cpu,tune}=. */ | |
733f53f5 | 259 | static struct cpu_table { |
3bb5de61 | 260 | const char *name; |
16956f6e | 261 | enum processor_type processor; |
733f53f5 DE |
262 | int disable; |
263 | int enable; | |
264 | } cpu_table[] = { | |
16956f6e DE |
265 | { "v7", PROCESSOR_V7, MASK_ISA, 0 }, |
266 | { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, | |
267 | { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, | |
733f53f5 | 268 | /* TI TMS390Z55 supersparc */ |
16956f6e DE |
269 | { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, |
270 | { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, | |
733f53f5 DE |
271 | /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. |
272 | The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ | |
16956f6e DE |
273 | { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, |
274 | { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, | |
8947065c | 275 | { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, |
d3ec6b06 VM |
276 | { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, |
277 | MASK_SPARCLITE }, | |
16956f6e | 278 | { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, |
733f53f5 | 279 | /* TEMIC sparclet */ |
3592ea0d | 280 | { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, |
16956f6e | 281 | { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, |
5cb01b65 JJ |
282 | /* TI ultrasparc I, II, IIi */ |
283 | { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 | |
284 | /* Although insns using %y are deprecated, it is a clear win on current | |
285 | ultrasparcs. */ | |
3276910d | 286 | |MASK_DEPRECATED_V8_INSNS}, |
db3d4438 | 287 | { 0, 0, 0, 0 } |
733f53f5 | 288 | }; |
16956f6e DE |
289 | struct cpu_table *cpu; |
290 | struct sparc_cpu_select *sel; | |
a0a301fc | 291 | int fpu; |
345a6161 | 292 | |
a0a301fc DE |
293 | #ifndef SPARC_BI_ARCH |
294 | /* Check for unsupported architecture size. */ | |
295 | if (! TARGET_64BIT != DEFAULT_ARCH32_P) | |
3276910d RK |
296 | error ("%s is not supported by this configuration", |
297 | DEFAULT_ARCH32_P ? "-m64" : "-m32"); | |
a0a301fc DE |
298 | #endif |
299 | ||
4710d3eb JJ |
300 | /* We force all 64bit archs to use 128 bit long double */ |
301 | if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128) | |
302 | { | |
303 | error ("-mlong-double-64 not allowed with -m64"); | |
304 | target_flags |= MASK_LONG_DOUBLE_128; | |
305 | } | |
306 | ||
a0a301fc DE |
307 | /* Code model selection. */ |
308 | sparc_cmodel = SPARC_DEFAULT_CMODEL; | |
345a6161 DM |
309 | |
310 | #ifdef SPARC_BI_ARCH | |
311 | if (TARGET_ARCH32) | |
312 | sparc_cmodel = CM_32; | |
313 | #endif | |
314 | ||
a0a301fc DE |
315 | if (sparc_cmodel_string != NULL) |
316 | { | |
317 | if (TARGET_ARCH64) | |
318 | { | |
319 | for (cmodel = &cmodels[0]; cmodel->name; cmodel++) | |
320 | if (strcmp (sparc_cmodel_string, cmodel->name) == 0) | |
321 | break; | |
322 | if (cmodel->name == NULL) | |
323 | error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); | |
324 | else | |
325 | sparc_cmodel = cmodel->value; | |
326 | } | |
327 | else | |
328 | error ("-mcmodel= is not supported on 32 bit systems"); | |
329 | } | |
16956f6e | 330 | |
a0a301fc | 331 | fpu = TARGET_FPU; /* save current -mfpu status */ |
1f1406b4 | 332 | |
a0a301fc | 333 | /* Set the default CPU. */ |
16956f6e DE |
334 | for (def = &cpu_default[0]; def->name; ++def) |
335 | if (def->cpu == TARGET_CPU_DEFAULT) | |
336 | break; | |
337 | if (! def->name) | |
338 | abort (); | |
339 | sparc_select[0].string = def->name; | |
340 | ||
341 | for (sel = &sparc_select[0]; sel->name; ++sel) | |
61a55e8b | 342 | { |
16956f6e | 343 | if (sel->string) |
733f53f5 | 344 | { |
16956f6e DE |
345 | for (cpu = &cpu_table[0]; cpu->name; ++cpu) |
346 | if (! strcmp (sel->string, cpu->name)) | |
347 | { | |
348 | if (sel->set_tune_p) | |
349 | sparc_cpu = cpu->processor; | |
350 | ||
351 | if (sel->set_arch_p) | |
352 | { | |
353 | target_flags &= ~cpu->disable; | |
354 | target_flags |= cpu->enable; | |
355 | } | |
356 | break; | |
357 | } | |
358 | ||
359 | if (! cpu->name) | |
360 | error ("bad value (%s) for %s switch", sel->string, sel->name); | |
733f53f5 | 361 | } |
61a55e8b | 362 | } |
97da85b7 | 363 | |
1f1406b4 | 364 | /* If -mfpu or -mno-fpu was explicitly used, don't override with |
46cc13b3 RO |
365 | the processor default. Clear MASK_FPU_SET to avoid confusing |
366 | the reverse mapping from switch values to names. */ | |
1f1406b4 | 367 | if (TARGET_FPU_SET) |
46cc13b3 RO |
368 | { |
369 | target_flags = (target_flags & ~MASK_FPU) | fpu; | |
370 | target_flags &= ~MASK_FPU_SET; | |
371 | } | |
1f1406b4 | 372 | |
a5774a7d JJ |
373 | /* Don't allow -mvis if FPU is disabled. */ |
374 | if (! TARGET_FPU) | |
375 | target_flags &= ~MASK_VIS; | |
376 | ||
377 | /* -mvis assumes UltraSPARC+, so we are sure v9 instructions | |
378 | are available. | |
379 | -m64 also implies v9. */ | |
380 | if (TARGET_VIS || TARGET_ARCH64) | |
381 | target_flags |= MASK_V9; | |
382 | ||
16956f6e DE |
383 | /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ |
384 | if (TARGET_V9 && TARGET_ARCH32) | |
733f53f5 | 385 | target_flags |= MASK_DEPRECATED_V8_INSNS; |
61a55e8b | 386 | |
345a6161 DM |
387 | /* V8PLUS requires V9, makes no sense in 64 bit mode. */ |
388 | if (! TARGET_V9 || TARGET_ARCH64) | |
284d86e9 JC |
389 | target_flags &= ~MASK_V8PLUS; |
390 | ||
82d6b402 RH |
391 | /* Don't use stack biasing in 32 bit mode. */ |
392 | if (TARGET_ARCH32) | |
393 | target_flags &= ~MASK_STACK_BIAS; | |
f952a238 | 394 | |
efa3896a GK |
395 | /* Supply a default value for align_functions. */ |
396 | if (align_functions == 0 && sparc_cpu == PROCESSOR_ULTRASPARC) | |
397 | align_functions = 32; | |
bf62bbf1 | 398 | |
82d6b402 RH |
399 | /* Validate PCC_STRUCT_RETURN. */ |
400 | if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) | |
401 | flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); | |
402 | ||
61a55e8b DE |
403 | /* Do various machine dependent initializations. */ |
404 | sparc_init_modes (); | |
2be15d0f RH |
405 | |
406 | if ((profile_flag || profile_block_flag) | |
a330e73b | 407 | && sparc_cmodel != CM_32 && sparc_cmodel != CM_MEDLOW) |
2be15d0f RH |
408 | { |
409 | error ("profiling does not support code models other than medlow"); | |
410 | } | |
d07d525a MM |
411 | |
412 | /* Register global variables with the garbage collector. */ | |
413 | sparc_add_gc_roots (); | |
61a55e8b DE |
414 | } |
415 | \f | |
cd5fb1ee DE |
416 | /* Miscellaneous utilities. */ |
417 | ||
418 | /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move | |
419 | or branch on register contents instructions. */ | |
420 | ||
421 | int | |
422 | v9_regcmp_p (code) | |
423 | enum rtx_code code; | |
424 | { | |
425 | return (code == EQ || code == NE || code == GE || code == LT | |
426 | || code == LE || code == GT); | |
427 | } | |
bfd6bc60 | 428 | |
cd5fb1ee DE |
429 | \f |
430 | /* Operand constraints. */ | |
431 | ||
ab835497 | 432 | /* Return non-zero only if OP is a register of mode MODE, |
e6c1be7e | 433 | or const0_rtx. */ |
c4ce6853 | 434 | |
ab835497 RK |
435 | int |
436 | reg_or_0_operand (op, mode) | |
437 | rtx op; | |
438 | enum machine_mode mode; | |
439 | { | |
c4ce6853 DE |
440 | if (register_operand (op, mode)) |
441 | return 1; | |
c4ce6853 | 442 | if (op == const0_rtx) |
ab835497 | 443 | return 1; |
5b486ce0 | 444 | if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE |
ab835497 RK |
445 | && CONST_DOUBLE_HIGH (op) == 0 |
446 | && CONST_DOUBLE_LOW (op) == 0) | |
447 | return 1; | |
7ce86678 | 448 | if (fp_zero_operand (op, mode)) |
302484ff | 449 | return 1; |
ab835497 RK |
450 | return 0; |
451 | } | |
452 | ||
302484ff | 453 | /* Nonzero if OP is a floating point value with value 0.0. */ |
c4ce6853 | 454 | |
302484ff | 455 | int |
7ce86678 | 456 | fp_zero_operand (op, mode) |
302484ff | 457 | rtx op; |
7ce86678 | 458 | enum machine_mode mode; |
302484ff | 459 | { |
7ce86678 RH |
460 | if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT) |
461 | return 0; | |
462 | return op == CONST0_RTX (mode); | |
302484ff JW |
463 | } |
464 | ||
62190128 DM |
465 | /* Nonzero if OP is a floating point constant which can |
466 | be loaded into an integer register using a single | |
467 | sethi instruction. */ | |
468 | ||
469 | int | |
470 | fp_sethi_p (op) | |
471 | rtx op; | |
472 | { | |
473 | if (GET_CODE (op) == CONST_DOUBLE) | |
474 | { | |
475 | REAL_VALUE_TYPE r; | |
476 | long i; | |
477 | ||
478 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
479 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
480 | ! REAL_VALUE_MINUS_ZERO (r)) | |
481 | return 0; | |
482 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
483 | if (SPARC_SETHI_P (i)) | |
484 | return 1; | |
485 | } | |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
490 | /* Nonzero if OP is a floating point constant which can | |
491 | be loaded into an integer register using a single | |
492 | mov instruction. */ | |
493 | ||
494 | int | |
495 | fp_mov_p (op) | |
496 | rtx op; | |
497 | { | |
498 | if (GET_CODE (op) == CONST_DOUBLE) | |
499 | { | |
500 | REAL_VALUE_TYPE r; | |
501 | long i; | |
502 | ||
503 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
504 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
505 | ! REAL_VALUE_MINUS_ZERO (r)) | |
506 | return 0; | |
507 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
508 | if (SPARC_SIMM13_P (i)) | |
509 | return 1; | |
510 | } | |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
515 | /* Nonzero if OP is a floating point constant which can | |
516 | be loaded into an integer register using a high/losum | |
517 | instruction sequence. */ | |
518 | ||
519 | int | |
520 | fp_high_losum_p (op) | |
521 | rtx op; | |
522 | { | |
523 | /* The constraints calling this should only be in | |
524 | SFmode move insns, so any constant which cannot | |
525 | be moved using a single insn will do. */ | |
526 | if (GET_CODE (op) == CONST_DOUBLE) | |
527 | { | |
528 | REAL_VALUE_TYPE r; | |
529 | long i; | |
530 | ||
531 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
532 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
533 | ! REAL_VALUE_MINUS_ZERO (r)) | |
534 | return 0; | |
535 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
536 | if (! SPARC_SETHI_P (i) | |
537 | && ! SPARC_SIMM13_P (i)) | |
538 | return 1; | |
539 | } | |
540 | ||
541 | return 0; | |
542 | } | |
543 | ||
61a55e8b DE |
544 | /* Nonzero if OP is an integer register. */ |
545 | ||
546 | int | |
547 | intreg_operand (op, mode) | |
548 | rtx op; | |
487a6e06 | 549 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
550 | { |
551 | return (register_operand (op, SImode) | |
a9e27770 | 552 | || (TARGET_ARCH64 && register_operand (op, DImode))); |
61a55e8b DE |
553 | } |
554 | ||
555 | /* Nonzero if OP is a floating point condition code register. */ | |
556 | ||
557 | int | |
c4ce6853 | 558 | fcc_reg_operand (op, mode) |
61a55e8b DE |
559 | rtx op; |
560 | enum machine_mode mode; | |
561 | { | |
562 | /* This can happen when recog is called from combine. Op may be a MEM. | |
563 | Fail instead of calling abort in this case. */ | |
c4ce6853 | 564 | if (GET_CODE (op) != REG) |
61a55e8b | 565 | return 0; |
304b7a23 | 566 | |
c4ce6853 | 567 | if (mode != VOIDmode && mode != GET_MODE (op)) |
61a55e8b | 568 | return 0; |
304b7a23 DE |
569 | if (mode == VOIDmode |
570 | && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) | |
571 | return 0; | |
61a55e8b | 572 | |
c4ce6853 | 573 | #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ |
61a55e8b DE |
574 | if (reg_renumber == 0) |
575 | return REGNO (op) >= FIRST_PSEUDO_REGISTER; | |
576 | return REGNO_OK_FOR_CCFP_P (REGNO (op)); | |
577 | #else | |
c4ce6853 | 578 | return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; |
61a55e8b DE |
579 | #endif |
580 | } | |
581 | ||
c4ce6853 DE |
582 | /* Nonzero if OP is an integer or floating point condition code register. */ |
583 | ||
584 | int | |
585 | icc_or_fcc_reg_operand (op, mode) | |
586 | rtx op; | |
587 | enum machine_mode mode; | |
588 | { | |
589 | if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) | |
304b7a23 DE |
590 | { |
591 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
592 | return 0; | |
593 | if (mode == VOIDmode | |
594 | && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) | |
595 | return 0; | |
596 | return 1; | |
597 | } | |
598 | ||
c4ce6853 DE |
599 | return fcc_reg_operand (op, mode); |
600 | } | |
601 | ||
ab835497 RK |
602 | /* Nonzero if OP can appear as the dest of a RESTORE insn. */ |
603 | int | |
604 | restore_operand (op, mode) | |
605 | rtx op; | |
606 | enum machine_mode mode; | |
607 | { | |
608 | return (GET_CODE (op) == REG && GET_MODE (op) == mode | |
609 | && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); | |
610 | } | |
611 | ||
401cec23 JW |
612 | /* Call insn on SPARC can take a PC-relative constant address, or any regular |
613 | memory address. */ | |
ab835497 RK |
614 | |
615 | int | |
616 | call_operand (op, mode) | |
617 | rtx op; | |
618 | enum machine_mode mode; | |
619 | { | |
620 | if (GET_CODE (op) != MEM) | |
621 | abort (); | |
622 | op = XEXP (op, 0); | |
2445f289 | 623 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
624 | } |
625 | ||
626 | int | |
627 | call_operand_address (op, mode) | |
628 | rtx op; | |
629 | enum machine_mode mode; | |
630 | { | |
2445f289 | 631 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
632 | } |
633 | ||
634 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
635 | reference and a constant. */ | |
636 | ||
637 | int | |
638 | symbolic_operand (op, mode) | |
639 | register rtx op; | |
640 | enum machine_mode mode; | |
641 | { | |
6871dd65 RH |
642 | enum machine_mode omode = GET_MODE (op); |
643 | ||
644 | if (omode != mode && omode != VOIDmode && mode != VOIDmode) | |
645 | return 0; | |
646 | ||
ab835497 RK |
647 | switch (GET_CODE (op)) |
648 | { | |
649 | case SYMBOL_REF: | |
650 | case LABEL_REF: | |
651 | return 1; | |
652 | ||
653 | case CONST: | |
654 | op = XEXP (op, 0); | |
655 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
656 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
657 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
658 | ||
ab835497 RK |
659 | default: |
660 | return 0; | |
661 | } | |
662 | } | |
663 | ||
664 | /* Return truth value of statement that OP is a symbolic memory | |
665 | operand of mode MODE. */ | |
666 | ||
667 | int | |
668 | symbolic_memory_operand (op, mode) | |
669 | rtx op; | |
487a6e06 | 670 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
671 | { |
672 | if (GET_CODE (op) == SUBREG) | |
673 | op = SUBREG_REG (op); | |
674 | if (GET_CODE (op) != MEM) | |
675 | return 0; | |
676 | op = XEXP (op, 0); | |
677 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST | |
678 | || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); | |
679 | } | |
680 | ||
5ab7138b DE |
681 | /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ |
682 | ||
683 | int | |
684 | label_ref_operand (op, mode) | |
685 | rtx op; | |
686 | enum machine_mode mode; | |
687 | { | |
688 | if (GET_CODE (op) != LABEL_REF) | |
689 | return 0; | |
690 | if (GET_MODE (op) != mode) | |
691 | return 0; | |
692 | return 1; | |
693 | } | |
694 | ||
95726648 DE |
695 | /* Return 1 if the operand is an argument used in generating pic references |
696 | in either the medium/low or medium/anywhere code models of sparc64. */ | |
697 | ||
698 | int | |
699 | sp64_medium_pic_operand (op, mode) | |
700 | rtx op; | |
487a6e06 | 701 | enum machine_mode mode ATTRIBUTE_UNUSED; |
95726648 DE |
702 | { |
703 | /* Check for (const (minus (symbol_ref:GOT) | |
704 | (const (minus (label) (pc))))). */ | |
705 | if (GET_CODE (op) != CONST) | |
706 | return 0; | |
707 | op = XEXP (op, 0); | |
708 | if (GET_CODE (op) != MINUS) | |
709 | return 0; | |
710 | if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) | |
711 | return 0; | |
712 | /* ??? Ensure symbol is GOT. */ | |
713 | if (GET_CODE (XEXP (op, 1)) != CONST) | |
714 | return 0; | |
715 | if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) | |
716 | return 0; | |
717 | return 1; | |
718 | } | |
719 | ||
61a55e8b DE |
720 | /* Return 1 if the operand is a data segment reference. This includes |
721 | the readonly data segment, or in other words anything but the text segment. | |
722 | This is needed in the medium/anywhere code model on v9. These values | |
a0a301fc | 723 | are accessed with EMBMEDANY_BASE_REG. */ |
61a55e8b DE |
724 | |
725 | int | |
726 | data_segment_operand (op, mode) | |
727 | rtx op; | |
487a6e06 | 728 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
729 | { |
730 | switch (GET_CODE (op)) | |
731 | { | |
732 | case SYMBOL_REF : | |
733 | return ! SYMBOL_REF_FLAG (op); | |
734 | case PLUS : | |
95726648 DE |
735 | /* Assume canonical format of symbol + constant. |
736 | Fall through. */ | |
61a55e8b | 737 | case CONST : |
b1474bb7 | 738 | return data_segment_operand (XEXP (op, 0), VOIDmode); |
61a55e8b DE |
739 | default : |
740 | return 0; | |
741 | } | |
742 | } | |
743 | ||
744 | /* Return 1 if the operand is a text segment reference. | |
745 | This is needed in the medium/anywhere code model on v9. */ | |
746 | ||
747 | int | |
748 | text_segment_operand (op, mode) | |
749 | rtx op; | |
487a6e06 | 750 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
751 | { |
752 | switch (GET_CODE (op)) | |
753 | { | |
754 | case LABEL_REF : | |
755 | return 1; | |
756 | case SYMBOL_REF : | |
757 | return SYMBOL_REF_FLAG (op); | |
758 | case PLUS : | |
95726648 DE |
759 | /* Assume canonical format of symbol + constant. |
760 | Fall through. */ | |
61a55e8b | 761 | case CONST : |
b1474bb7 | 762 | return text_segment_operand (XEXP (op, 0), VOIDmode); |
61a55e8b DE |
763 | default : |
764 | return 0; | |
765 | } | |
766 | } | |
767 | ||
ab835497 RK |
768 | /* Return 1 if the operand is either a register or a memory operand that is |
769 | not symbolic. */ | |
770 | ||
771 | int | |
772 | reg_or_nonsymb_mem_operand (op, mode) | |
773 | register rtx op; | |
774 | enum machine_mode mode; | |
775 | { | |
776 | if (register_operand (op, mode)) | |
777 | return 1; | |
778 | ||
779 | if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) | |
780 | return 1; | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
ab835497 | 785 | int |
6ac34277 | 786 | splittable_symbolic_memory_operand (op, mode) |
ab835497 | 787 | rtx op; |
487a6e06 | 788 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 | 789 | { |
6ac34277 DE |
790 | if (GET_CODE (op) != MEM) |
791 | return 0; | |
792 | if (! symbolic_operand (XEXP (op, 0), Pmode)) | |
793 | return 0; | |
794 | return 1; | |
795 | } | |
796 | ||
797 | int | |
798 | splittable_immediate_memory_operand (op, mode) | |
799 | rtx op; | |
487a6e06 | 800 | enum machine_mode mode ATTRIBUTE_UNUSED; |
6ac34277 DE |
801 | { |
802 | if (GET_CODE (op) != MEM) | |
803 | return 0; | |
804 | if (! immediate_operand (XEXP (op, 0), Pmode)) | |
805 | return 0; | |
806 | return 1; | |
ab835497 RK |
807 | } |
808 | ||
809 | /* Return truth value of whether OP is EQ or NE. */ | |
810 | ||
811 | int | |
812 | eq_or_neq (op, mode) | |
813 | rtx op; | |
487a6e06 | 814 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
815 | { |
816 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
817 | } | |
818 | ||
819 | /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, | |
820 | or LTU for non-floating-point. We handle those specially. */ | |
821 | ||
822 | int | |
823 | normal_comp_operator (op, mode) | |
824 | rtx op; | |
487a6e06 | 825 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
826 | { |
827 | enum rtx_code code = GET_CODE (op); | |
828 | ||
829 | if (GET_RTX_CLASS (code) != '<') | |
830 | return 0; | |
831 | ||
4d449554 JW |
832 | if (GET_MODE (XEXP (op, 0)) == CCFPmode |
833 | || GET_MODE (XEXP (op, 0)) == CCFPEmode) | |
ab835497 RK |
834 | return 1; |
835 | ||
836 | return (code != NE && code != EQ && code != GEU && code != LTU); | |
837 | } | |
838 | ||
839 | /* Return 1 if this is a comparison operator. This allows the use of | |
840 | MATCH_OPERATOR to recognize all the branch insns. */ | |
841 | ||
842 | int | |
843 | noov_compare_op (op, mode) | |
844 | register rtx op; | |
487a6e06 | 845 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
846 | { |
847 | enum rtx_code code = GET_CODE (op); | |
848 | ||
849 | if (GET_RTX_CLASS (code) != '<') | |
850 | return 0; | |
851 | ||
852 | if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode) | |
853 | /* These are the only branches which work with CC_NOOVmode. */ | |
854 | return (code == EQ || code == NE || code == GE || code == LT); | |
855 | return 1; | |
856 | } | |
857 | ||
61a55e8b DE |
858 | /* Nonzero if OP is a comparison operator suitable for use in v9 |
859 | conditional move or branch on register contents instructions. */ | |
860 | ||
861 | int | |
862 | v9_regcmp_op (op, mode) | |
863 | register rtx op; | |
487a6e06 | 864 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
865 | { |
866 | enum rtx_code code = GET_CODE (op); | |
867 | ||
868 | if (GET_RTX_CLASS (code) != '<') | |
869 | return 0; | |
870 | ||
cd5fb1ee | 871 | return v9_regcmp_p (code); |
61a55e8b DE |
872 | } |
873 | ||
ab835497 RK |
874 | /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ |
875 | ||
876 | int | |
877 | extend_op (op, mode) | |
878 | rtx op; | |
487a6e06 | 879 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
880 | { |
881 | return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; | |
882 | } | |
883 | ||
884 | /* Return nonzero if OP is an operator of mode MODE which can set | |
885 | the condition codes explicitly. We do not include PLUS and MINUS | |
886 | because these require CC_NOOVmode, which we handle explicitly. */ | |
887 | ||
888 | int | |
889 | cc_arithop (op, mode) | |
890 | rtx op; | |
487a6e06 | 891 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
892 | { |
893 | if (GET_CODE (op) == AND | |
894 | || GET_CODE (op) == IOR | |
895 | || GET_CODE (op) == XOR) | |
896 | return 1; | |
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
901 | /* Return nonzero if OP is an operator of mode MODE which can bitwise | |
902 | complement its second operand and set the condition codes explicitly. */ | |
903 | ||
904 | int | |
905 | cc_arithopn (op, mode) | |
906 | rtx op; | |
487a6e06 | 907 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
908 | { |
909 | /* XOR is not here because combine canonicalizes (xor (not ...) ...) | |
910 | and (xor ... (not ...)) to (not (xor ...)). */ | |
911 | return (GET_CODE (op) == AND | |
912 | || GET_CODE (op) == IOR); | |
913 | } | |
914 | \f | |
58cbf20e DE |
915 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
916 | signed 13 bit immediate field. This is an acceptable SImode operand for | |
917 | most 3 address instructions. */ | |
ab835497 RK |
918 | |
919 | int | |
920 | arith_operand (op, mode) | |
921 | rtx op; | |
922 | enum machine_mode mode; | |
923 | { | |
284d86e9 | 924 | int val; |
11301057 | 925 | if (register_operand (op, mode)) |
284d86e9 JC |
926 | return 1; |
927 | if (GET_CODE (op) != CONST_INT) | |
928 | return 0; | |
929 | val = INTVAL (op) & 0xffffffff; | |
930 | return SPARC_SIMM13_P (val); | |
ab835497 RK |
931 | } |
932 | ||
5d6d3339 JJ |
933 | /* Return true if OP is a constant 4096 */ |
934 | ||
935 | int | |
936 | arith_4096_operand (op, mode) | |
937 | rtx op; | |
ddf80874 | 938 | enum machine_mode mode ATTRIBUTE_UNUSED; |
5d6d3339 JJ |
939 | { |
940 | int val; | |
941 | if (GET_CODE (op) != CONST_INT) | |
942 | return 0; | |
943 | val = INTVAL (op) & 0xffffffff; | |
944 | return val == 4096; | |
945 | } | |
946 | ||
947 | /* Return true if OP is suitable as second operand for add/sub */ | |
948 | ||
949 | int | |
950 | arith_add_operand (op, mode) | |
951 | rtx op; | |
952 | enum machine_mode mode; | |
953 | { | |
954 | return arith_operand (op, mode) || arith_4096_operand (op, mode); | |
955 | } | |
956 | ||
89e65674 DM |
957 | /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the |
958 | immediate field of OR and XOR instructions. Used for 64-bit | |
959 | constant formation patterns. */ | |
960 | int | |
961 | const64_operand (op, mode) | |
962 | rtx op; | |
ddf80874 | 963 | enum machine_mode mode ATTRIBUTE_UNUSED; |
89e65674 DM |
964 | { |
965 | return ((GET_CODE (op) == CONST_INT | |
966 | && SPARC_SIMM13_P (INTVAL (op))) | |
9208e4b2 | 967 | #if HOST_BITS_PER_WIDE_INT != 64 |
89e65674 | 968 | || (GET_CODE (op) == CONST_DOUBLE |
9208e4b2 DM |
969 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) |
970 | && (CONST_DOUBLE_HIGH (op) == | |
971 | ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? | |
ddf80874 | 972 | (HOST_WIDE_INT)0xffffffff : 0))) |
9208e4b2 | 973 | #endif |
11301057 | 974 | ); |
89e65674 DM |
975 | } |
976 | ||
9208e4b2 | 977 | /* The same, but only for sethi instructions. */ |
89e65674 DM |
978 | int |
979 | const64_high_operand (op, mode) | |
980 | rtx op; | |
ddf80874 | 981 | enum machine_mode mode ATTRIBUTE_UNUSED; |
89e65674 DM |
982 | { |
983 | return ((GET_CODE (op) == CONST_INT | |
9208e4b2 DM |
984 | && (INTVAL (op) & 0xfffffc00) != 0 |
985 | && SPARC_SETHI_P (INTVAL (op)) | |
986 | #if HOST_BITS_PER_WIDE_INT != 64 | |
987 | /* Must be positive on non-64bit host else the | |
988 | optimizer is fooled into thinking that sethi | |
989 | sign extends, even though it does not. */ | |
990 | && INTVAL (op) >= 0 | |
991 | #endif | |
992 | ) | |
89e65674 DM |
993 | || (GET_CODE (op) == CONST_DOUBLE |
994 | && CONST_DOUBLE_HIGH (op) == 0 | |
9208e4b2 | 995 | && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0 |
11301057 | 996 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))); |
89e65674 DM |
997 | } |
998 | ||
58cbf20e DE |
999 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
1000 | signed 11 bit immediate field. This is an acceptable SImode operand for | |
1001 | the movcc instructions. */ | |
61a55e8b DE |
1002 | |
1003 | int | |
1004 | arith11_operand (op, mode) | |
1005 | rtx op; | |
1006 | enum machine_mode mode; | |
1007 | { | |
1008 | return (register_operand (op, mode) | |
58cbf20e | 1009 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); |
61a55e8b DE |
1010 | } |
1011 | ||
58cbf20e DE |
1012 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
1013 | signed 10 bit immediate field. This is an acceptable SImode operand for | |
1014 | the movrcc instructions. */ | |
61a55e8b DE |
1015 | |
1016 | int | |
1017 | arith10_operand (op, mode) | |
1018 | rtx op; | |
1019 | enum machine_mode mode; | |
1020 | { | |
1021 | return (register_operand (op, mode) | |
58cbf20e | 1022 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); |
61a55e8b DE |
1023 | } |
1024 | ||
23b8a89f JW |
1025 | /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit |
1026 | immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit | |
61a55e8b DE |
1027 | immediate field. |
1028 | v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
1029 | can fit in a 13 bit immediate field. This is an acceptable DImode operand | |
1030 | for most 3 address instructions. */ | |
ab835497 RK |
1031 | |
1032 | int | |
1033 | arith_double_operand (op, mode) | |
1034 | rtx op; | |
1035 | enum machine_mode mode; | |
1036 | { | |
1037 | return (register_operand (op, mode) | |
23b8a89f | 1038 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) |
a9e27770 | 1039 | || (! TARGET_ARCH64 |
61a55e8b | 1040 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 DE |
1041 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
1042 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) | |
a9e27770 | 1043 | || (TARGET_ARCH64 |
61a55e8b | 1044 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 | 1045 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
61a55e8b DE |
1046 | && ((CONST_DOUBLE_HIGH (op) == -1 |
1047 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) | |
1048 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1049 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); | |
1050 | } | |
1051 | ||
5d6d3339 JJ |
1052 | /* Return true if OP is a constant 4096 for DImode on ARCH64 */ |
1053 | ||
1054 | int | |
1055 | arith_double_4096_operand (op, mode) | |
1056 | rtx op; | |
ddf80874 | 1057 | enum machine_mode mode ATTRIBUTE_UNUSED; |
5d6d3339 JJ |
1058 | { |
1059 | return (TARGET_ARCH64 && | |
1060 | ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || | |
1061 | (GET_CODE (op) == CONST_DOUBLE && | |
1062 | CONST_DOUBLE_LOW (op) == 4096 && | |
1063 | CONST_DOUBLE_HIGH (op) == 0))); | |
1064 | } | |
1065 | ||
1066 | /* Return true if OP is suitable as second operand for add/sub in DImode */ | |
1067 | ||
1068 | int | |
1069 | arith_double_add_operand (op, mode) | |
1070 | rtx op; | |
1071 | enum machine_mode mode; | |
1072 | { | |
1073 | return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode); | |
1074 | } | |
1075 | ||
61a55e8b DE |
1076 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that |
1077 | can fit in an 11 bit immediate field. This is an acceptable DImode | |
1078 | operand for the movcc instructions. */ | |
1079 | /* ??? Replace with arith11_operand? */ | |
1080 | ||
1081 | int | |
1082 | arith11_double_operand (op, mode) | |
1083 | rtx op; | |
1084 | enum machine_mode mode; | |
1085 | { | |
1086 | return (register_operand (op, mode) | |
1087 | || (GET_CODE (op) == CONST_DOUBLE | |
1088 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1089 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 |
61a55e8b DE |
1090 | && ((CONST_DOUBLE_HIGH (op) == -1 |
1091 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) | |
1092 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1093 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) | |
1094 | || (GET_CODE (op) == CONST_INT | |
1095 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1096 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800)); |
61a55e8b DE |
1097 | } |
1098 | ||
1099 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
1100 | can fit in an 10 bit immediate field. This is an acceptable DImode | |
1101 | operand for the movrcc instructions. */ | |
1102 | /* ??? Replace with arith10_operand? */ | |
1103 | ||
1104 | int | |
1105 | arith10_double_operand (op, mode) | |
1106 | rtx op; | |
1107 | enum machine_mode mode; | |
1108 | { | |
1109 | return (register_operand (op, mode) | |
1110 | || (GET_CODE (op) == CONST_DOUBLE | |
1111 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
1112 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 | |
1113 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
1114 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) | |
1115 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1116 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) | |
1117 | || (GET_CODE (op) == CONST_INT | |
1118 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1119 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400)); |
ab835497 RK |
1120 | } |
1121 | ||
1122 | /* Return truth value of whether OP is a integer which fits the | |
228b4037 JW |
1123 | range constraining immediate operands in most three-address insns, |
1124 | which have a 13 bit immediate field. */ | |
ab835497 RK |
1125 | |
1126 | int | |
1127 | small_int (op, mode) | |
1128 | rtx op; | |
487a6e06 | 1129 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 | 1130 | { |
11301057 | 1131 | return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); |
ab835497 RK |
1132 | } |
1133 | ||
e0d80184 DM |
1134 | int |
1135 | small_int_or_double (op, mode) | |
1136 | rtx op; | |
1137 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1138 | { | |
1139 | return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) | |
1140 | || (GET_CODE (op) == CONST_DOUBLE | |
1141 | && CONST_DOUBLE_HIGH (op) == 0 | |
11301057 | 1142 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))); |
e0d80184 DM |
1143 | } |
1144 | ||
9b3fad96 JW |
1145 | /* Recognize operand values for the umul instruction. That instruction sign |
1146 | extends immediate values just like all other sparc instructions, but | |
1147 | interprets the extended result as an unsigned number. */ | |
1148 | ||
1149 | int | |
1150 | uns_small_int (op, mode) | |
1151 | rtx op; | |
487a6e06 | 1152 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9b3fad96 JW |
1153 | { |
1154 | #if HOST_BITS_PER_WIDE_INT > 32 | |
1155 | /* All allowed constants will fit a CONST_INT. */ | |
11301057 RH |
1156 | return (GET_CODE (op) == CONST_INT |
1157 | && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) | |
1158 | || (INTVAL (op) >= 0xFFFFF000 | |
0d587737 | 1159 | && INTVAL (op) <= 0xFFFFFFFF))); |
9b3fad96 | 1160 | #else |
11301057 RH |
1161 | return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) |
1162 | || (GET_CODE (op) == CONST_DOUBLE | |
1163 | && CONST_DOUBLE_HIGH (op) == 0 | |
1164 | && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); | |
9b3fad96 JW |
1165 | #endif |
1166 | } | |
1167 | ||
1168 | int | |
1169 | uns_arith_operand (op, mode) | |
1170 | rtx op; | |
1171 | enum machine_mode mode; | |
1172 | { | |
1173 | return register_operand (op, mode) || uns_small_int (op, mode); | |
1174 | } | |
1175 | ||
ab835497 RK |
1176 | /* Return truth value of statement that OP is a call-clobbered register. */ |
1177 | int | |
1178 | clobbered_register (op, mode) | |
1179 | rtx op; | |
487a6e06 | 1180 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
1181 | { |
1182 | return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); | |
1183 | } | |
ab835497 | 1184 | |
e0d80184 | 1185 | /* Return 1 if OP is a valid operand for the source of a move insn. */ |
61a55e8b | 1186 | |
e0d80184 DM |
1187 | int |
1188 | input_operand (op, mode) | |
1189 | rtx op; | |
1190 | enum machine_mode mode; | |
1191 | { | |
1192 | /* If both modes are non-void they must be the same. */ | |
1193 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) | |
1194 | return 0; | |
61a55e8b | 1195 | |
11301057 RH |
1196 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
1197 | if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX) | |
1198 | return 1; | |
1199 | ||
e0d80184 DM |
1200 | /* Allow any one instruction integer constant, and all CONST_INT |
1201 | variants when we are working in DImode and !arch64. */ | |
1202 | if (GET_MODE_CLASS (mode) == MODE_INT | |
9208e4b2 DM |
1203 | && ((GET_CODE (op) == CONST_INT |
1204 | && ((SPARC_SETHI_P (INTVAL (op)) | |
1205 | && (! TARGET_ARCH64 | |
1206 | || (INTVAL (op) >= 0) | |
dcee55a2 JJ |
1207 | || mode == SImode |
1208 | || mode == HImode | |
1209 | || mode == QImode)) | |
9208e4b2 DM |
1210 | || SPARC_SIMM13_P (INTVAL (op)) |
1211 | || (mode == DImode | |
1212 | && ! TARGET_ARCH64))) | |
1213 | || (TARGET_ARCH64 | |
1214 | && GET_CODE (op) == CONST_DOUBLE | |
1215 | && ((CONST_DOUBLE_HIGH (op) == 0 | |
1216 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) | |
1217 | || | |
1218 | #if HOST_BITS_PER_WIDE_INT == 64 | |
1219 | (CONST_DOUBLE_HIGH (op) == 0 | |
1220 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) | |
1221 | #else | |
1222 | (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) | |
1223 | && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0 | |
1224 | && CONST_DOUBLE_HIGH (op) == 0) | |
4746e0fe RK |
1225 | || (CONST_DOUBLE_HIGH (op) == -1 |
1226 | && CONST_DOUBLE_LOW (op) & 0x80000000) != 0)) | |
9208e4b2 DM |
1227 | #endif |
1228 | )))) | |
e0d80184 DM |
1229 | return 1; |
1230 | ||
e0d80184 DM |
1231 | /* If !arch64 and this is a DImode const, allow it so that |
1232 | the splits can be generated. */ | |
1233 | if (! TARGET_ARCH64 | |
1234 | && mode == DImode | |
1235 | && GET_CODE (op) == CONST_DOUBLE) | |
1236 | return 1; | |
1237 | ||
1238 | if (register_operand (op, mode)) | |
1239 | return 1; | |
1240 | ||
62190128 DM |
1241 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1242 | && GET_CODE (op) == CONST_DOUBLE) | |
1243 | return 1; | |
1244 | ||
e0d80184 DM |
1245 | /* If this is a SUBREG, look inside so that we handle |
1246 | paradoxical ones. */ | |
1247 | if (GET_CODE (op) == SUBREG) | |
1248 | op = SUBREG_REG (op); | |
1249 | ||
1250 | /* Check for valid MEM forms. */ | |
1251 | if (GET_CODE (op) == MEM) | |
61a55e8b | 1252 | { |
e0d80184 | 1253 | rtx inside = XEXP (op, 0); |
61a55e8b | 1254 | |
e0d80184 | 1255 | if (GET_CODE (inside) == LO_SUM) |
03ad6f4d DM |
1256 | { |
1257 | /* We can't allow these because all of the splits | |
1258 | (eventually as they trickle down into DFmode | |
1259 | splits) require offsettable memory references. */ | |
1260 | if (! TARGET_V9 | |
1261 | && GET_MODE (op) == TFmode) | |
1262 | return 0; | |
1263 | ||
1264 | return (register_operand (XEXP (inside, 0), Pmode) | |
1265 | && CONSTANT_P (XEXP (inside, 1))); | |
1266 | } | |
e0d80184 | 1267 | return memory_address_p (mode, inside); |
61a55e8b | 1268 | } |
ab835497 | 1269 | |
e0d80184 DM |
1270 | return 0; |
1271 | } | |
1272 | ||
1273 | \f | |
1274 | /* We know it can't be done in one insn when we get here, | |
1275 | the movsi expander guarentees this. */ | |
1276 | void | |
1277 | sparc_emit_set_const32 (op0, op1) | |
1278 | rtx op0; | |
1279 | rtx op1; | |
1280 | { | |
1281 | enum machine_mode mode = GET_MODE (op0); | |
1282 | rtx temp; | |
1283 | ||
1284 | if (GET_CODE (op1) == CONST_INT) | |
284d86e9 | 1285 | { |
2a01c939 | 1286 | HOST_WIDE_INT value = INTVAL (op1); |
e0d80184 DM |
1287 | |
1288 | if (SPARC_SETHI_P (value) | |
1289 | || SPARC_SIMM13_P (value)) | |
1290 | abort (); | |
284d86e9 | 1291 | } |
e0d80184 DM |
1292 | |
1293 | /* Full 2-insn decomposition is needed. */ | |
1294 | if (reload_in_progress || reload_completed) | |
1295 | temp = op0; | |
284d86e9 | 1296 | else |
e0d80184 DM |
1297 | temp = gen_reg_rtx (mode); |
1298 | ||
71648202 DM |
1299 | if (GET_CODE (op1) == CONST_INT) |
1300 | { | |
1301 | /* Emit them as real moves instead of a HIGH/LO_SUM, | |
1302 | this way CSE can see everything and reuse intermediate | |
1303 | values if it wants. */ | |
1304 | if (TARGET_ARCH64 | |
1305 | && HOST_BITS_PER_WIDE_INT != 64 | |
1306 | && (INTVAL (op1) & 0x80000000) != 0) | |
1307 | { | |
1308 | emit_insn (gen_rtx_SET (VOIDmode, | |
1309 | temp, | |
1310 | gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, | |
1311 | INTVAL (op1) & 0xfffffc00, 0))); | |
1312 | } | |
1313 | else | |
1314 | { | |
1315 | emit_insn (gen_rtx_SET (VOIDmode, | |
1316 | temp, | |
1317 | GEN_INT (INTVAL (op1) & 0xfffffc00))); | |
1318 | } | |
1319 | emit_insn (gen_rtx_SET (VOIDmode, | |
1320 | op0, | |
1321 | gen_rtx_IOR (mode, | |
1322 | temp, | |
1323 | GEN_INT (INTVAL (op1) & 0x3ff)))); | |
1324 | } | |
1325 | else | |
1326 | { | |
1327 | /* A symbol, emit in the traditional way. */ | |
1328 | emit_insn (gen_rtx_SET (VOIDmode, | |
1329 | temp, | |
1330 | gen_rtx_HIGH (mode, | |
1331 | op1))); | |
1332 | emit_insn (gen_rtx_SET (VOIDmode, | |
1333 | op0, | |
1334 | gen_rtx_LO_SUM (mode, | |
1335 | temp, | |
1336 | op1))); | |
1337 | ||
1338 | } | |
e0d80184 DM |
1339 | } |
1340 | ||
1341 | \f | |
1342 | /* Sparc-v9 code-model support. */ | |
1343 | void | |
1344 | sparc_emit_set_symbolic_const64 (op0, op1, temp1) | |
1345 | rtx op0; | |
1346 | rtx op1; | |
1347 | rtx temp1; | |
1348 | { | |
1349 | switch (sparc_cmodel) | |
284d86e9 | 1350 | { |
e0d80184 DM |
1351 | case CM_MEDLOW: |
1352 | /* The range spanned by all instructions in the object is less | |
1353 | than 2^31 bytes (2GB) and the distance from any instruction | |
1354 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1355 | than 2^31 bytes (2GB). | |
ab835497 | 1356 | |
e0d80184 DM |
1357 | The executable must be in the low 4TB of the virtual address |
1358 | space. | |
61a55e8b | 1359 | |
e0d80184 DM |
1360 | sethi %hi(symbol), %temp |
1361 | or %temp, %lo(symbol), %reg */ | |
9208e4b2 DM |
1362 | emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); |
1363 | emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); | |
e0d80184 | 1364 | break; |
61a55e8b | 1365 | |
e0d80184 DM |
1366 | case CM_MEDMID: |
1367 | /* The range spanned by all instructions in the object is less | |
1368 | than 2^31 bytes (2GB) and the distance from any instruction | |
1369 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1370 | than 2^31 bytes (2GB). | |
1371 | ||
1372 | The executable must be in the low 16TB of the virtual address | |
1373 | space. | |
1374 | ||
1375 | sethi %h44(symbol), %temp1 | |
1376 | or %temp1, %m44(symbol), %temp2 | |
1377 | sllx %temp2, 12, %temp3 | |
1378 | or %temp3, %l44(symbol), %reg */ | |
1379 | emit_insn (gen_seth44 (op0, op1)); | |
1380 | emit_insn (gen_setm44 (op0, op0, op1)); | |
9208e4b2 | 1381 | emit_insn (gen_rtx_SET (VOIDmode, temp1, |
e0d80184 DM |
1382 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (12)))); |
1383 | emit_insn (gen_setl44 (op0, temp1, op1)); | |
1384 | break; | |
61a55e8b | 1385 | |
e0d80184 DM |
1386 | case CM_MEDANY: |
1387 | /* The range spanned by all instructions in the object is less | |
1388 | than 2^31 bytes (2GB) and the distance from any instruction | |
1389 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1390 | than 2^31 bytes (2GB). | |
1391 | ||
1392 | The executable can be placed anywhere in the virtual address | |
1393 | space. | |
1394 | ||
1395 | sethi %hh(symbol), %temp1 | |
1396 | sethi %lm(symbol), %temp2 | |
1397 | or %temp1, %hm(symbol), %temp3 | |
1398 | or %temp2, %lo(symbol), %temp4 | |
1399 | sllx %temp3, 32, %temp5 | |
1400 | or %temp4, %temp5, %reg */ | |
1401 | ||
1402 | /* Getting this right wrt. reloading is really tricky. | |
5722d61c | 1403 | We _MUST_ have a separate temporary at this point, |
e0d80184 DM |
1404 | if we don't barf immediately instead of generating |
1405 | incorrect code. */ | |
1406 | if (temp1 == op0) | |
1407 | abort (); | |
61a55e8b | 1408 | |
e0d80184 DM |
1409 | emit_insn (gen_sethh (op0, op1)); |
1410 | emit_insn (gen_setlm (temp1, op1)); | |
1411 | emit_insn (gen_sethm (op0, op0, op1)); | |
9208e4b2 | 1412 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1413 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1414 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1415 | gen_rtx_PLUS (DImode, op0, temp1))); |
1416 | emit_insn (gen_setlo (op0, op0, op1)); | |
1417 | break; | |
61a55e8b | 1418 | |
e0d80184 DM |
1419 | case CM_EMBMEDANY: |
1420 | /* Old old old backwards compatibility kruft here. | |
1421 | Essentially it is MEDLOW with a fixed 64-bit | |
1422 | virtual base added to all data segment addresses. | |
1423 | Text-segment stuff is computed like MEDANY, we can't | |
1424 | reuse the code above because the relocation knobs | |
1425 | look different. | |
1426 | ||
1427 | Data segment: sethi %hi(symbol), %temp1 | |
1428 | or %temp1, %lo(symbol), %temp2 | |
1429 | add %temp2, EMBMEDANY_BASE_REG, %reg | |
1430 | ||
1431 | Text segment: sethi %uhi(symbol), %temp1 | |
1432 | sethi %hi(symbol), %temp2 | |
1433 | or %temp1, %ulo(symbol), %temp3 | |
1434 | or %temp2, %lo(symbol), %temp4 | |
1435 | sllx %temp3, 32, %temp5 | |
1436 | or %temp4, %temp5, %reg */ | |
1437 | if (data_segment_operand (op1, GET_MODE (op1))) | |
1438 | { | |
1439 | emit_insn (gen_embmedany_sethi (temp1, op1)); | |
1440 | emit_insn (gen_embmedany_brsum (op0, temp1)); | |
1441 | emit_insn (gen_embmedany_losum (op0, op0, op1)); | |
1442 | } | |
1443 | else | |
1444 | { | |
1445 | /* Getting this right wrt. reloading is really tricky. | |
5722d61c | 1446 | We _MUST_ have a separate temporary at this point, |
f710f868 | 1447 | so we barf immediately instead of generating |
e0d80184 DM |
1448 | incorrect code. */ |
1449 | if (temp1 == op0) | |
1450 | abort (); | |
61a55e8b | 1451 | |
e0d80184 DM |
1452 | emit_insn (gen_embmedany_textuhi (op0, op1)); |
1453 | emit_insn (gen_embmedany_texthi (temp1, op1)); | |
1454 | emit_insn (gen_embmedany_textulo (op0, op0, op1)); | |
9208e4b2 | 1455 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1456 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1457 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1458 | gen_rtx_PLUS (DImode, op0, temp1))); |
1459 | emit_insn (gen_embmedany_textlo (op0, op0, op1)); | |
1460 | } | |
1461 | break; | |
1462 | ||
1463 | default: | |
1464 | abort(); | |
1465 | } | |
1466 | } | |
1467 | ||
9208e4b2 DM |
1468 | /* These avoid problems when cross compiling. If we do not |
1469 | go through all this hair then the optimizer will see | |
1470 | invalid REG_EQUAL notes or in some cases none at all. */ | |
f6da8bc3 KG |
1471 | static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT)); |
1472 | static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT)); | |
1473 | static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT)); | |
1474 | static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT)); | |
9208e4b2 DM |
1475 | |
1476 | #if HOST_BITS_PER_WIDE_INT == 64 | |
1477 | #define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00) | |
1478 | #define GEN_INT64(__x) GEN_INT (__x) | |
1479 | #else | |
1480 | #define GEN_HIGHINT64(__x) \ | |
1481 | gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \ | |
1482 | (__x) & 0xfffffc00, 0) | |
1483 | #define GEN_INT64(__x) \ | |
1484 | gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \ | |
1485 | (__x) & 0xffffffff, \ | |
1486 | ((__x) & 0x80000000 \ | |
1487 | ? 0xffffffff : 0)) | |
1488 | #endif | |
1489 | ||
1490 | /* The optimizer is not to assume anything about exactly | |
1491 | which bits are set for a HIGH, they are unspecified. | |
1492 | Unfortunately this leads to many missed optimizations | |
1493 | during CSE. We mask out the non-HIGH bits, and matches | |
1494 | a plain movdi, to alleviate this problem. */ | |
1495 | static void | |
1496 | sparc_emit_set_safe_HIGH64 (dest, val) | |
1497 | rtx dest; | |
1498 | HOST_WIDE_INT val; | |
1499 | { | |
1500 | emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val))); | |
1501 | } | |
2a01c939 | 1502 | |
e0d80184 | 1503 | static rtx |
9208e4b2 DM |
1504 | gen_safe_SET64 (dest, val) |
1505 | rtx dest; | |
e0d80184 | 1506 | HOST_WIDE_INT val; |
61a55e8b | 1507 | { |
9208e4b2 DM |
1508 | return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val)); |
1509 | } | |
1510 | ||
1511 | static rtx | |
1512 | gen_safe_OR64 (src, val) | |
1513 | rtx src; | |
1514 | HOST_WIDE_INT val; | |
1515 | { | |
1516 | return gen_rtx_IOR (DImode, src, GEN_INT64 (val)); | |
1517 | } | |
1518 | ||
1519 | static rtx | |
1520 | gen_safe_XOR64 (src, val) | |
1521 | rtx src; | |
1522 | HOST_WIDE_INT val; | |
1523 | { | |
1524 | return gen_rtx_XOR (DImode, src, GEN_INT64 (val)); | |
e0d80184 | 1525 | } |
61a55e8b | 1526 | |
e0d80184 DM |
1527 | /* Worker routines for 64-bit constant formation on arch64. |
1528 | One of the key things to be doing in these emissions is | |
1529 | to create as many temp REGs as possible. This makes it | |
1530 | possible for half-built constants to be used later when | |
1531 | such values are similar to something required later on. | |
1532 | Without doing this, the optimizer cannot see such | |
1533 | opportunities. */ | |
2a01c939 DM |
1534 | |
1535 | static void sparc_emit_set_const64_quick1 | |
f6da8bc3 | 1536 | PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int)); |
2a01c939 | 1537 | |
e0d80184 DM |
1538 | static void |
1539 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg) | |
1540 | rtx op0; | |
1541 | rtx temp; | |
2a01c939 | 1542 | unsigned HOST_WIDE_INT low_bits; |
e0d80184 DM |
1543 | int is_neg; |
1544 | { | |
2a01c939 | 1545 | unsigned HOST_WIDE_INT high_bits; |
a9e27770 | 1546 | |
e0d80184 | 1547 | if (is_neg) |
2a01c939 | 1548 | high_bits = (~low_bits) & 0xffffffff; |
31bc9eba | 1549 | else |
e0d80184 | 1550 | high_bits = low_bits; |
31bc9eba | 1551 | |
9208e4b2 | 1552 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1553 | if (!is_neg) |
5108f3e5 DM |
1554 | { |
1555 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1556 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
1557 | } | |
e0d80184 | 1558 | else |
5108f3e5 DM |
1559 | { |
1560 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
1561 | instead. This way the combiner will notice logical operations | |
1562 | such as ANDN later on and substitute. */ | |
1563 | if ((low_bits & 0x3ff) == 0x3ff) | |
1564 | { | |
1565 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1566 | gen_rtx_NOT (DImode, temp))); | |
1567 | } | |
1568 | else | |
1569 | { | |
1570 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1571 | gen_safe_XOR64 (temp, | |
1572 | (-0x400 | (low_bits & 0x3ff))))); | |
1573 | } | |
1574 | } | |
e0d80184 | 1575 | } |
61a55e8b | 1576 | |
2a01c939 | 1577 | static void sparc_emit_set_const64_quick2 |
f6da8bc3 | 1578 | PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, |
2a01c939 DM |
1579 | unsigned HOST_WIDE_INT, int)); |
1580 | ||
e0d80184 DM |
1581 | static void |
1582 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count) | |
1583 | rtx op0; | |
1584 | rtx temp; | |
2a01c939 DM |
1585 | unsigned HOST_WIDE_INT high_bits; |
1586 | unsigned HOST_WIDE_INT low_immediate; | |
e0d80184 DM |
1587 | int shift_count; |
1588 | { | |
1589 | rtx temp2 = op0; | |
61a55e8b | 1590 | |
e0d80184 DM |
1591 | if ((high_bits & 0xfffffc00) != 0) |
1592 | { | |
9208e4b2 | 1593 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1594 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 DM |
1595 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1596 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
61a55e8b | 1597 | else |
e0d80184 | 1598 | temp2 = temp; |
61a55e8b DE |
1599 | } |
1600 | else | |
1601 | { | |
f710f868 | 1602 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 DM |
1603 | temp2 = temp; |
1604 | } | |
61a55e8b | 1605 | |
e0d80184 | 1606 | /* Now shift it up into place. */ |
9208e4b2 | 1607 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1608 | gen_rtx_ASHIFT (DImode, temp2, |
1609 | GEN_INT (shift_count)))); | |
61a55e8b | 1610 | |
e0d80184 DM |
1611 | /* If there is a low immediate part piece, finish up by |
1612 | putting that in as well. */ | |
1613 | if (low_immediate != 0) | |
9208e4b2 DM |
1614 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1615 | gen_safe_OR64 (op0, low_immediate))); | |
ab835497 RK |
1616 | } |
1617 | ||
2a01c939 | 1618 | static void sparc_emit_set_const64_longway |
f6da8bc3 | 1619 | PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); |
2a01c939 | 1620 | |
e0d80184 DM |
1621 | /* Full 64-bit constant decomposition. Even though this is the |
1622 | 'worst' case, we still optimize a few things away. */ | |
1623 | static void | |
1624 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits) | |
1625 | rtx op0; | |
1626 | rtx temp; | |
2a01c939 DM |
1627 | unsigned HOST_WIDE_INT high_bits; |
1628 | unsigned HOST_WIDE_INT low_bits; | |
ab835497 | 1629 | { |
e0d80184 | 1630 | rtx sub_temp; |
4bf7135b | 1631 | |
e0d80184 DM |
1632 | if (reload_in_progress || reload_completed) |
1633 | sub_temp = op0; | |
1634 | else | |
1635 | sub_temp = gen_reg_rtx (DImode); | |
1636 | ||
1637 | if ((high_bits & 0xfffffc00) != 0) | |
1638 | { | |
9208e4b2 | 1639 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1640 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 | 1641 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1642 | sub_temp, |
9208e4b2 | 1643 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); |
e0d80184 DM |
1644 | else |
1645 | sub_temp = temp; | |
1646 | } | |
1647 | else | |
ab835497 | 1648 | { |
f710f868 | 1649 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 | 1650 | sub_temp = temp; |
ab835497 | 1651 | } |
4bf7135b | 1652 | |
e0d80184 | 1653 | if (!reload_in_progress && !reload_completed) |
284d86e9 | 1654 | { |
e0d80184 DM |
1655 | rtx temp2 = gen_reg_rtx (DImode); |
1656 | rtx temp3 = gen_reg_rtx (DImode); | |
1657 | rtx temp4 = gen_reg_rtx (DImode); | |
284d86e9 | 1658 | |
9208e4b2 | 1659 | emit_insn (gen_rtx_SET (VOIDmode, temp4, |
e0d80184 DM |
1660 | gen_rtx_ASHIFT (DImode, sub_temp, |
1661 | GEN_INT (32)))); | |
4bf7135b | 1662 | |
9208e4b2 | 1663 | sparc_emit_set_safe_HIGH64 (temp2, low_bits); |
e0d80184 | 1664 | if ((low_bits & ~0xfffffc00) != 0) |
f710f868 DM |
1665 | { |
1666 | emit_insn (gen_rtx_SET (VOIDmode, temp3, | |
1667 | gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); | |
1668 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1669 | gen_rtx_PLUS (DImode, temp4, temp3))); | |
1670 | } | |
1671 | else | |
1672 | { | |
1673 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1674 | gen_rtx_PLUS (DImode, temp4, temp2))); | |
1675 | } | |
284d86e9 | 1676 | } |
e0d80184 DM |
1677 | else |
1678 | { | |
9208e4b2 DM |
1679 | rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); |
1680 | rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); | |
1681 | rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); | |
e0d80184 | 1682 | int to_shift = 12; |
284d86e9 | 1683 | |
e0d80184 DM |
1684 | /* We are in the middle of reload, so this is really |
1685 | painful. However we do still make an attempt to | |
5108f3e5 | 1686 | avoid emitting truly stupid code. */ |
e0d80184 DM |
1687 | if (low1 != const0_rtx) |
1688 | { | |
9208e4b2 | 1689 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1690 | gen_rtx_ASHIFT (DImode, sub_temp, |
2a01c939 | 1691 | GEN_INT (to_shift)))); |
9208e4b2 | 1692 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1693 | gen_rtx_IOR (DImode, op0, low1))); |
1694 | sub_temp = op0; | |
1695 | to_shift = 12; | |
1696 | } | |
1697 | else | |
1698 | { | |
1699 | to_shift += 12; | |
1700 | } | |
1701 | if (low2 != const0_rtx) | |
1702 | { | |
9208e4b2 | 1703 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1704 | gen_rtx_ASHIFT (DImode, sub_temp, |
1705 | GEN_INT (to_shift)))); | |
9208e4b2 | 1706 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1707 | gen_rtx_IOR (DImode, op0, low2))); |
1708 | sub_temp = op0; | |
1709 | to_shift = 8; | |
1710 | } | |
1711 | else | |
1712 | { | |
1713 | to_shift += 8; | |
1714 | } | |
9208e4b2 | 1715 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1716 | gen_rtx_ASHIFT (DImode, sub_temp, |
1717 | GEN_INT (to_shift)))); | |
1718 | if (low3 != const0_rtx) | |
9208e4b2 | 1719 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1720 | gen_rtx_IOR (DImode, op0, low3))); |
1721 | /* phew... */ | |
1722 | } | |
284d86e9 JC |
1723 | } |
1724 | ||
e0d80184 | 1725 | /* Analyze a 64-bit constant for certain properties. */ |
2a01c939 | 1726 | static void analyze_64bit_constant |
f6da8bc3 | 1727 | PARAMS ((unsigned HOST_WIDE_INT, |
2a01c939 DM |
1728 | unsigned HOST_WIDE_INT, |
1729 | int *, int *, int *)); | |
1730 | ||
e0d80184 DM |
1731 | static void |
1732 | analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp) | |
2a01c939 | 1733 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 | 1734 | int *hbsp, *lbsp, *abbasp; |
ab835497 | 1735 | { |
e0d80184 DM |
1736 | int lowest_bit_set, highest_bit_set, all_bits_between_are_set; |
1737 | int i; | |
ab835497 | 1738 | |
e0d80184 DM |
1739 | lowest_bit_set = highest_bit_set = -1; |
1740 | i = 0; | |
1741 | do | |
ab835497 | 1742 | { |
e0d80184 DM |
1743 | if ((lowest_bit_set == -1) |
1744 | && ((low_bits >> i) & 1)) | |
1745 | lowest_bit_set = i; | |
1746 | if ((highest_bit_set == -1) | |
1747 | && ((high_bits >> (32 - i - 1)) & 1)) | |
1748 | highest_bit_set = (64 - i - 1); | |
1749 | } | |
1750 | while (++i < 32 | |
1751 | && ((highest_bit_set == -1) | |
1752 | || (lowest_bit_set == -1))); | |
1753 | if (i == 32) | |
1754 | { | |
1755 | i = 0; | |
1756 | do | |
ab835497 | 1757 | { |
e0d80184 DM |
1758 | if ((lowest_bit_set == -1) |
1759 | && ((high_bits >> i) & 1)) | |
1760 | lowest_bit_set = i + 32; | |
1761 | if ((highest_bit_set == -1) | |
1762 | && ((low_bits >> (32 - i - 1)) & 1)) | |
1763 | highest_bit_set = 32 - i - 1; | |
ab835497 | 1764 | } |
e0d80184 DM |
1765 | while (++i < 32 |
1766 | && ((highest_bit_set == -1) | |
1767 | || (lowest_bit_set == -1))); | |
1768 | } | |
1769 | /* If there are no bits set this should have gone out | |
1770 | as one instruction! */ | |
1771 | if (lowest_bit_set == -1 | |
1772 | || highest_bit_set == -1) | |
9208e4b2 | 1773 | abort (); |
e0d80184 DM |
1774 | all_bits_between_are_set = 1; |
1775 | for (i = lowest_bit_set; i <= highest_bit_set; i++) | |
1776 | { | |
1777 | if (i < 32) | |
1778 | { | |
1779 | if ((low_bits & (1 << i)) != 0) | |
1780 | continue; | |
1781 | } | |
1782 | else | |
1783 | { | |
1784 | if ((high_bits & (1 << (i - 32))) != 0) | |
1785 | continue; | |
1786 | } | |
1787 | all_bits_between_are_set = 0; | |
1788 | break; | |
ab835497 | 1789 | } |
e0d80184 DM |
1790 | *hbsp = highest_bit_set; |
1791 | *lbsp = lowest_bit_set; | |
1792 | *abbasp = all_bits_between_are_set; | |
ab835497 | 1793 | } |
6a4bb1fa | 1794 | |
2a01c939 | 1795 | static int const64_is_2insns |
f6da8bc3 | 1796 | PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); |
2a01c939 | 1797 | |
e0d80184 DM |
1798 | static int |
1799 | const64_is_2insns (high_bits, low_bits) | |
2a01c939 | 1800 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1801 | { |
1802 | int highest_bit_set, lowest_bit_set, all_bits_between_are_set; | |
284d86e9 | 1803 | |
e0d80184 | 1804 | if (high_bits == 0 |
2a01c939 | 1805 | || high_bits == 0xffffffff) |
e0d80184 | 1806 | return 1; |
6a4bb1fa | 1807 | |
e0d80184 DM |
1808 | analyze_64bit_constant (high_bits, low_bits, |
1809 | &highest_bit_set, &lowest_bit_set, | |
1810 | &all_bits_between_are_set); | |
6a4bb1fa | 1811 | |
f710f868 DM |
1812 | if ((highest_bit_set == 63 |
1813 | || lowest_bit_set == 0) | |
e0d80184 DM |
1814 | && all_bits_between_are_set != 0) |
1815 | return 1; | |
6a4bb1fa | 1816 | |
9208e4b2 DM |
1817 | if ((highest_bit_set - lowest_bit_set) < 21) |
1818 | return 1; | |
1819 | ||
6a4bb1fa DE |
1820 | return 0; |
1821 | } | |
1822 | ||
2a01c939 | 1823 | static unsigned HOST_WIDE_INT create_simple_focus_bits |
f6da8bc3 | 1824 | PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, |
ddf80874 | 1825 | int, int)); |
2a01c939 DM |
1826 | |
1827 | static unsigned HOST_WIDE_INT | |
ddf80874 | 1828 | create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift) |
2a01c939 | 1829 | unsigned HOST_WIDE_INT high_bits, low_bits; |
ddf80874 | 1830 | int lowest_bit_set, shift; |
ab835497 | 1831 | { |
f710f868 | 1832 | HOST_WIDE_INT hi, lo; |
ab835497 | 1833 | |
e0d80184 DM |
1834 | if (lowest_bit_set < 32) |
1835 | { | |
1836 | lo = (low_bits >> lowest_bit_set) << shift; | |
1837 | hi = ((high_bits << (32 - lowest_bit_set)) << shift); | |
1838 | } | |
1839 | else | |
1840 | { | |
1841 | lo = 0; | |
1842 | hi = ((high_bits >> (lowest_bit_set - 32)) << shift); | |
1843 | } | |
1844 | if (hi & lo) | |
9208e4b2 | 1845 | abort (); |
e0d80184 DM |
1846 | return (hi | lo); |
1847 | } | |
ab835497 | 1848 | |
e0d80184 DM |
1849 | /* Here we are sure to be arch64 and this is an integer constant |
1850 | being loaded into a register. Emit the most efficient | |
1851 | insn sequence possible. Detection of all the 1-insn cases | |
1852 | has been done already. */ | |
1853 | void | |
1854 | sparc_emit_set_const64 (op0, op1) | |
1855 | rtx op0; | |
1856 | rtx op1; | |
1857 | { | |
2a01c939 | 1858 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1859 | int lowest_bit_set, highest_bit_set; |
1860 | int all_bits_between_are_set; | |
e0d80184 | 1861 | rtx temp; |
ab835497 | 1862 | |
e0d80184 | 1863 | /* Sanity check that we know what we are working with. */ |
380f6ad3 | 1864 | if (! TARGET_ARCH64) |
9208e4b2 | 1865 | abort (); |
95726648 | 1866 | |
380f6ad3 JJ |
1867 | if (GET_CODE (op0) != SUBREG) |
1868 | { | |
1869 | if (GET_CODE (op0) != REG | |
1870 | || (REGNO (op0) >= SPARC_FIRST_FP_REG | |
1871 | && REGNO (op0) <= SPARC_LAST_V9_FP_REG)) | |
1872 | abort (); | |
1873 | } | |
1874 | ||
f710f868 DM |
1875 | if (reload_in_progress || reload_completed) |
1876 | temp = op0; | |
1877 | else | |
1878 | temp = gen_reg_rtx (DImode); | |
1879 | ||
e0d80184 DM |
1880 | if (GET_CODE (op1) != CONST_DOUBLE |
1881 | && GET_CODE (op1) != CONST_INT) | |
1882 | { | |
5f78aa30 JC |
1883 | sparc_emit_set_symbolic_const64 (op0, op1, temp); |
1884 | return; | |
e0d80184 | 1885 | } |
ab835497 | 1886 | |
e0d80184 DM |
1887 | if (GET_CODE (op1) == CONST_DOUBLE) |
1888 | { | |
1889 | #if HOST_BITS_PER_WIDE_INT == 64 | |
2a01c939 | 1890 | high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff; |
e0d80184 DM |
1891 | low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff; |
1892 | #else | |
1893 | high_bits = CONST_DOUBLE_HIGH (op1); | |
1894 | low_bits = CONST_DOUBLE_LOW (op1); | |
1895 | #endif | |
ab835497 | 1896 | } |
e0d80184 | 1897 | else |
ab835497 | 1898 | { |
e0d80184 | 1899 | #if HOST_BITS_PER_WIDE_INT == 64 |
2a01c939 | 1900 | high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); |
e0d80184 DM |
1901 | low_bits = (INTVAL (op1) & 0xffffffff); |
1902 | #else | |
1903 | high_bits = ((INTVAL (op1) < 0) ? | |
1904 | 0xffffffff : | |
1905 | 0x00000000); | |
1906 | low_bits = INTVAL (op1); | |
1907 | #endif | |
1908 | } | |
ab835497 | 1909 | |
e0d80184 DM |
1910 | /* low_bits bits 0 --> 31 |
1911 | high_bits bits 32 --> 63 */ | |
ab835497 | 1912 | |
e0d80184 DM |
1913 | analyze_64bit_constant (high_bits, low_bits, |
1914 | &highest_bit_set, &lowest_bit_set, | |
1915 | &all_bits_between_are_set); | |
1916 | ||
1917 | /* First try for a 2-insn sequence. */ | |
1918 | ||
1919 | /* These situations are preferred because the optimizer can | |
1920 | * do more things with them: | |
1921 | * 1) mov -1, %reg | |
1922 | * sllx %reg, shift, %reg | |
1923 | * 2) mov -1, %reg | |
1924 | * srlx %reg, shift, %reg | |
1925 | * 3) mov some_small_const, %reg | |
1926 | * sllx %reg, shift, %reg | |
1927 | */ | |
1928 | if (((highest_bit_set == 63 | |
1929 | || lowest_bit_set == 0) | |
1930 | && all_bits_between_are_set != 0) | |
2a01c939 | 1931 | || ((highest_bit_set - lowest_bit_set) < 12)) |
e0d80184 | 1932 | { |
9208e4b2 | 1933 | HOST_WIDE_INT the_const = -1; |
e0d80184 DM |
1934 | int shift = lowest_bit_set; |
1935 | ||
f710f868 DM |
1936 | if ((highest_bit_set != 63 |
1937 | && lowest_bit_set != 0) | |
1938 | || all_bits_between_are_set == 0) | |
ab835497 | 1939 | { |
e0d80184 | 1940 | the_const = |
9208e4b2 | 1941 | create_simple_focus_bits (high_bits, low_bits, |
9208e4b2 | 1942 | lowest_bit_set, 0); |
ab835497 | 1943 | } |
e0d80184 | 1944 | else if (lowest_bit_set == 0) |
9208e4b2 | 1945 | shift = -(63 - highest_bit_set); |
e0d80184 | 1946 | |
f710f868 DM |
1947 | if (! SPARC_SIMM13_P (the_const)) |
1948 | abort (); | |
1949 | ||
9208e4b2 | 1950 | emit_insn (gen_safe_SET64 (temp, the_const)); |
e0d80184 | 1951 | if (shift > 0) |
9208e4b2 | 1952 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 DM |
1953 | op0, |
1954 | gen_rtx_ASHIFT (DImode, | |
1955 | temp, | |
1956 | GEN_INT (shift)))); | |
1957 | else if (shift < 0) | |
9208e4b2 | 1958 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1959 | op0, |
9208e4b2 | 1960 | gen_rtx_LSHIFTRT (DImode, |
e0d80184 DM |
1961 | temp, |
1962 | GEN_INT (-shift)))); | |
ab835497 RK |
1963 | else |
1964 | abort (); | |
e0d80184 DM |
1965 | return; |
1966 | } | |
ab835497 | 1967 | |
e0d80184 DM |
1968 | /* Now a range of 22 or less bits set somewhere. |
1969 | * 1) sethi %hi(focus_bits), %reg | |
1970 | * sllx %reg, shift, %reg | |
1971 | * 2) sethi %hi(focus_bits), %reg | |
1972 | * srlx %reg, shift, %reg | |
1973 | */ | |
2a01c939 | 1974 | if ((highest_bit_set - lowest_bit_set) < 21) |
e0d80184 | 1975 | { |
2a01c939 | 1976 | unsigned HOST_WIDE_INT focus_bits = |
e0d80184 | 1977 | create_simple_focus_bits (high_bits, low_bits, |
ddf80874 | 1978 | lowest_bit_set, 10); |
f710f868 DM |
1979 | |
1980 | if (! SPARC_SETHI_P (focus_bits)) | |
1981 | abort (); | |
1982 | ||
9208e4b2 | 1983 | sparc_emit_set_safe_HIGH64 (temp, focus_bits); |
e0d80184 | 1984 | |
9208e4b2 | 1985 | /* If lowest_bit_set == 10 then a sethi alone could have done it. */ |
e0d80184 | 1986 | if (lowest_bit_set < 10) |
9208e4b2 | 1987 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1988 | op0, |
9208e4b2 | 1989 | gen_rtx_LSHIFTRT (DImode, temp, |
e0d80184 | 1990 | GEN_INT (10 - lowest_bit_set)))); |
9208e4b2 DM |
1991 | else if (lowest_bit_set > 10) |
1992 | emit_insn (gen_rtx_SET (VOIDmode, | |
e0d80184 DM |
1993 | op0, |
1994 | gen_rtx_ASHIFT (DImode, temp, | |
1995 | GEN_INT (lowest_bit_set - 10)))); | |
1996 | else | |
9208e4b2 | 1997 | abort (); |
e0d80184 DM |
1998 | return; |
1999 | } | |
2000 | ||
2001 | /* 1) sethi %hi(low_bits), %reg | |
2002 | * or %reg, %lo(low_bits), %reg | |
2003 | * 2) sethi %hi(~low_bits), %reg | |
2004 | * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg | |
2005 | */ | |
2006 | if (high_bits == 0 | |
2a01c939 | 2007 | || high_bits == 0xffffffff) |
5f78aa30 JC |
2008 | { |
2009 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, | |
2010 | (high_bits == 0xffffffff)); | |
2011 | return; | |
2012 | } | |
e0d80184 | 2013 | |
f710f868 DM |
2014 | /* Now, try 3-insn sequences. */ |
2015 | ||
e0d80184 DM |
2016 | /* 1) sethi %hi(high_bits), %reg |
2017 | * or %reg, %lo(high_bits), %reg | |
2018 | * sllx %reg, 32, %reg | |
2019 | */ | |
f710f868 | 2020 | if (low_bits == 0) |
5f78aa30 | 2021 | { |
f710f868 | 2022 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); |
5f78aa30 JC |
2023 | return; |
2024 | } | |
e0d80184 | 2025 | |
f710f868 DM |
2026 | /* We may be able to do something quick |
2027 | when the constant is negated, so try that. */ | |
e0d80184 DM |
2028 | if (const64_is_2insns ((~high_bits) & 0xffffffff, |
2029 | (~low_bits) & 0xfffffc00)) | |
2030 | { | |
5108f3e5 DM |
2031 | /* NOTE: The trailing bits get XOR'd so we need the |
2032 | non-negated bits, not the negated ones. */ | |
2033 | unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; | |
e0d80184 DM |
2034 | |
2035 | if ((((~high_bits) & 0xffffffff) == 0 | |
2036 | && ((~low_bits) & 0x80000000) == 0) | |
2037 | || (((~high_bits) & 0xffffffff) == 0xffffffff | |
2038 | && ((~low_bits) & 0x80000000) != 0)) | |
ab835497 | 2039 | { |
5108f3e5 | 2040 | int fast_int = (~low_bits & 0xffffffff); |
e0d80184 | 2041 | |
5108f3e5 DM |
2042 | if ((SPARC_SETHI_P (fast_int) |
2043 | && (~high_bits & 0xffffffff) == 0) | |
2044 | || SPARC_SIMM13_P (fast_int)) | |
9208e4b2 | 2045 | emit_insn (gen_safe_SET64 (temp, fast_int)); |
ab835497 | 2046 | else |
9208e4b2 | 2047 | sparc_emit_set_const64 (temp, GEN_INT64 (fast_int)); |
ab835497 | 2048 | } |
e0d80184 DM |
2049 | else |
2050 | { | |
2051 | rtx negated_const; | |
2052 | #if HOST_BITS_PER_WIDE_INT == 64 | |
2053 | negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | | |
2054 | (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); | |
2055 | #else | |
9208e4b2 | 2056 | negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx, |
e0d80184 DM |
2057 | (~low_bits) & 0xfffffc00, |
2058 | (~high_bits) & 0xffffffff); | |
2059 | #endif | |
2060 | sparc_emit_set_const64 (temp, negated_const); | |
2061 | } | |
5108f3e5 DM |
2062 | |
2063 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
2064 | instead. This way the combiner will notice logical operations | |
2065 | such as ANDN later on and substitute. */ | |
2066 | if (trailing_bits == 0x3ff) | |
2067 | { | |
2068 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
2069 | gen_rtx_NOT (DImode, temp))); | |
2070 | } | |
2071 | else | |
2072 | { | |
2073 | emit_insn (gen_rtx_SET (VOIDmode, | |
2074 | op0, | |
2075 | gen_safe_XOR64 (temp, | |
2076 | (-0x400 | trailing_bits)))); | |
2077 | } | |
e0d80184 | 2078 | return; |
ab835497 | 2079 | } |
ab835497 | 2080 | |
e0d80184 DM |
2081 | /* 1) sethi %hi(xxx), %reg |
2082 | * or %reg, %lo(xxx), %reg | |
2083 | * sllx %reg, yyy, %reg | |
f710f868 DM |
2084 | * |
2085 | * ??? This is just a generalized version of the low_bits==0 | |
2086 | * thing above, FIXME... | |
e0d80184 DM |
2087 | */ |
2088 | if ((highest_bit_set - lowest_bit_set) < 32) | |
2089 | { | |
f710f868 DM |
2090 | unsigned HOST_WIDE_INT focus_bits = |
2091 | create_simple_focus_bits (high_bits, low_bits, | |
ddf80874 | 2092 | lowest_bit_set, 0); |
ab835497 | 2093 | |
e0d80184 DM |
2094 | /* We can't get here in this state. */ |
2095 | if (highest_bit_set < 32 | |
2096 | || lowest_bit_set >= 32) | |
9208e4b2 | 2097 | abort (); |
95726648 | 2098 | |
e0d80184 DM |
2099 | /* So what we know is that the set bits straddle the |
2100 | middle of the 64-bit word. */ | |
5f78aa30 JC |
2101 | sparc_emit_set_const64_quick2 (op0, temp, |
2102 | focus_bits, 0, | |
2103 | lowest_bit_set); | |
2104 | return; | |
e0d80184 | 2105 | } |
c85f7c16 | 2106 | |
f710f868 DM |
2107 | /* 1) sethi %hi(high_bits), %reg |
2108 | * or %reg, %lo(high_bits), %reg | |
2109 | * sllx %reg, 32, %reg | |
2110 | * or %reg, low_bits, %reg | |
2111 | */ | |
2112 | if (SPARC_SIMM13_P(low_bits) | |
2113 | && ((int)low_bits > 0)) | |
2114 | { | |
2115 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); | |
2116 | return; | |
2117 | } | |
2118 | ||
e0d80184 DM |
2119 | /* The easiest way when all else fails, is full decomposition. */ |
2120 | #if 0 | |
2121 | printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", | |
2122 | high_bits, low_bits, ~high_bits, ~low_bits); | |
2123 | #endif | |
2124 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); | |
c85f7c16 JL |
2125 | } |
2126 | ||
e267e177 RH |
2127 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
2128 | return the mode to be used for the comparison. For floating-point, | |
2129 | CCFP[E]mode is used. CC_NOOVmode should be used when the first operand | |
2130 | is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special | |
2131 | processing is needed. */ | |
2132 | ||
2133 | enum machine_mode | |
2134 | select_cc_mode (op, x, y) | |
2135 | enum rtx_code op; | |
2136 | rtx x; | |
2137 | rtx y ATTRIBUTE_UNUSED; | |
2138 | { | |
2139 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2140 | { | |
2141 | switch (op) | |
2142 | { | |
2143 | case EQ: | |
2144 | case NE: | |
2145 | case UNORDERED: | |
2146 | case ORDERED: | |
2147 | case UNLT: | |
2148 | case UNLE: | |
2149 | case UNGT: | |
2150 | case UNGE: | |
2151 | case UNEQ: | |
7913f3d0 | 2152 | case LTGT: |
e267e177 RH |
2153 | return CCFPmode; |
2154 | ||
2155 | case LT: | |
2156 | case LE: | |
2157 | case GT: | |
2158 | case GE: | |
2159 | return CCFPEmode; | |
2160 | ||
2161 | default: | |
2162 | abort (); | |
2163 | } | |
2164 | } | |
2165 | else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
2166 | || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) | |
2167 | { | |
2168 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
2169 | return CCX_NOOVmode; | |
2170 | else | |
2171 | return CC_NOOVmode; | |
2172 | } | |
2173 | else | |
2174 | { | |
2175 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
2176 | return CCXmode; | |
2177 | else | |
2178 | return CCmode; | |
2179 | } | |
2180 | } | |
2181 | ||
e0d80184 DM |
2182 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
2183 | return the rtx for the cc reg in the proper mode. */ | |
c85f7c16 | 2184 | |
e0d80184 DM |
2185 | rtx |
2186 | gen_compare_reg (code, x, y) | |
2187 | enum rtx_code code; | |
2188 | rtx x, y; | |
c85f7c16 | 2189 | { |
e0d80184 DM |
2190 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); |
2191 | rtx cc_reg; | |
c85f7c16 | 2192 | |
e0d80184 DM |
2193 | /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the |
2194 | fcc regs (cse can't tell they're really call clobbered regs and will | |
2195 | remove a duplicate comparison even if there is an intervening function | |
2196 | call - it will then try to reload the cc reg via an int reg which is why | |
2197 | we need the movcc patterns). It is possible to provide the movcc | |
2198 | patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two | |
2199 | registers (say %g1,%g5) and it takes about 6 insns. A better fix would be | |
2200 | to tell cse that CCFPE mode registers (even pseudos) are call | |
2201 | clobbered. */ | |
c85f7c16 | 2202 | |
e0d80184 DM |
2203 | /* ??? This is an experiment. Rather than making changes to cse which may |
2204 | or may not be easy/clean, we do our own cse. This is possible because | |
2205 | we will generate hard registers. Cse knows they're call clobbered (it | |
2206 | doesn't know the same thing about pseudos). If we guess wrong, no big | |
2207 | deal, but if we win, great! */ | |
c85f7c16 | 2208 | |
e0d80184 DM |
2209 | if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) |
2210 | #if 1 /* experiment */ | |
284d86e9 | 2211 | { |
e0d80184 DM |
2212 | int reg; |
2213 | /* We cycle through the registers to ensure they're all exercised. */ | |
2214 | static int next_fcc_reg = 0; | |
2215 | /* Previous x,y for each fcc reg. */ | |
2216 | static rtx prev_args[4][2]; | |
284d86e9 | 2217 | |
e0d80184 DM |
2218 | /* Scan prev_args for x,y. */ |
2219 | for (reg = 0; reg < 4; reg++) | |
2220 | if (prev_args[reg][0] == x && prev_args[reg][1] == y) | |
2221 | break; | |
2222 | if (reg == 4) | |
2223 | { | |
2224 | reg = next_fcc_reg; | |
2225 | prev_args[reg][0] = x; | |
2226 | prev_args[reg][1] = y; | |
2227 | next_fcc_reg = (next_fcc_reg + 1) & 3; | |
2228 | } | |
2229 | cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); | |
284d86e9 | 2230 | } |
e0d80184 DM |
2231 | #else |
2232 | cc_reg = gen_reg_rtx (mode); | |
2233 | #endif /* ! experiment */ | |
2234 | else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2235 | cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); | |
2236 | else | |
2237 | cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); | |
284d86e9 | 2238 | |
e0d80184 DM |
2239 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, |
2240 | gen_rtx_COMPARE (mode, x, y))); | |
c85f7c16 | 2241 | |
e0d80184 DM |
2242 | return cc_reg; |
2243 | } | |
c85f7c16 | 2244 | |
e0d80184 DM |
2245 | /* This function is used for v9 only. |
2246 | CODE is the code for an Scc's comparison. | |
2247 | OPERANDS[0] is the target of the Scc insn. | |
2248 | OPERANDS[1] is the value we compare against const0_rtx (which hasn't | |
2249 | been generated yet). | |
c85f7c16 | 2250 | |
e0d80184 | 2251 | This function is needed to turn |
ab835497 | 2252 | |
e0d80184 DM |
2253 | (set (reg:SI 110) |
2254 | (gt (reg:CCX 100 %icc) | |
2255 | (const_int 0))) | |
2256 | into | |
2257 | (set (reg:SI 110) | |
2258 | (gt:DI (reg:CCX 100 %icc) | |
2259 | (const_int 0))) | |
2260 | ||
2261 | IE: The instruction recognizer needs to see the mode of the comparison to | |
2262 | find the right instruction. We could use "gt:DI" right in the | |
2263 | define_expand, but leaving it out allows us to handle DI, SI, etc. | |
ab835497 | 2264 | |
e0d80184 DM |
2265 | We refer to the global sparc compare operands sparc_compare_op0 and |
2266 | sparc_compare_op1. */ | |
ab835497 RK |
2267 | |
2268 | int | |
e0d80184 DM |
2269 | gen_v9_scc (compare_code, operands) |
2270 | enum rtx_code compare_code; | |
2271 | register rtx *operands; | |
ab835497 | 2272 | { |
e0d80184 | 2273 | rtx temp, op0, op1; |
ab835497 | 2274 | |
e0d80184 DM |
2275 | if (! TARGET_ARCH64 |
2276 | && (GET_MODE (sparc_compare_op0) == DImode | |
2277 | || GET_MODE (operands[0]) == DImode)) | |
2278 | return 0; | |
7e2feebf | 2279 | |
e0d80184 DM |
2280 | /* Handle the case where operands[0] == sparc_compare_op0. |
2281 | We "early clobber" the result. */ | |
2282 | if (REGNO (operands[0]) == REGNO (sparc_compare_op0)) | |
ab835497 | 2283 | { |
e0d80184 DM |
2284 | op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); |
2285 | emit_move_insn (op0, sparc_compare_op0); | |
ab835497 | 2286 | } |
e0d80184 DM |
2287 | else |
2288 | op0 = sparc_compare_op0; | |
2289 | /* For consistency in the following. */ | |
2290 | op1 = sparc_compare_op1; | |
2291 | ||
2292 | /* Try to use the movrCC insns. */ | |
2293 | if (TARGET_ARCH64 | |
2294 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
2295 | && op1 == const0_rtx | |
2296 | && v9_regcmp_p (compare_code)) | |
ab835497 | 2297 | { |
e0d80184 DM |
2298 | /* Special case for op0 != 0. This can be done with one instruction if |
2299 | operands[0] == sparc_compare_op0. We don't assume they are equal | |
2300 | now though. */ | |
2301 | ||
2302 | if (compare_code == NE | |
2303 | && GET_MODE (operands[0]) == DImode | |
2304 | && GET_MODE (op0) == DImode) | |
ab835497 | 2305 | { |
e0d80184 DM |
2306 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0)); |
2307 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2308 | gen_rtx_IF_THEN_ELSE (DImode, | |
2309 | gen_rtx_fmt_ee (compare_code, DImode, | |
2310 | op0, const0_rtx), | |
2311 | const1_rtx, | |
2312 | operands[0]))); | |
ab835497 RK |
2313 | return 1; |
2314 | } | |
e0d80184 DM |
2315 | |
2316 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); | |
2317 | if (GET_MODE (op0) != DImode) | |
ab835497 | 2318 | { |
e0d80184 DM |
2319 | temp = gen_reg_rtx (DImode); |
2320 | convert_move (temp, op0, 0); | |
ab835497 | 2321 | } |
e0d80184 DM |
2322 | else |
2323 | temp = op0; | |
2324 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2325 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2326 | gen_rtx_fmt_ee (compare_code, DImode, | |
2327 | temp, const0_rtx), | |
2328 | const1_rtx, | |
2329 | operands[0]))); | |
95726648 DE |
2330 | return 1; |
2331 | } | |
e0d80184 | 2332 | else |
ab835497 | 2333 | { |
e0d80184 | 2334 | operands[1] = gen_compare_reg (compare_code, op0, op1); |
ab835497 | 2335 | |
e0d80184 | 2336 | switch (GET_MODE (operands[1])) |
ab835497 | 2337 | { |
e0d80184 DM |
2338 | case CCmode : |
2339 | case CCXmode : | |
2340 | case CCFPEmode : | |
2341 | case CCFPmode : | |
2342 | break; | |
2343 | default : | |
2344 | abort (); | |
ab835497 | 2345 | } |
e0d80184 DM |
2346 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); |
2347 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2348 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2349 | gen_rtx_fmt_ee (compare_code, | |
2350 | GET_MODE (operands[1]), | |
2351 | operands[1], const0_rtx), | |
2352 | const1_rtx, operands[0]))); | |
2353 | return 1; | |
ab835497 | 2354 | } |
ab835497 | 2355 | } |
4fb4e4b8 | 2356 | |
e0d80184 DM |
2357 | /* Emit a conditional jump insn for the v9 architecture using comparison code |
2358 | CODE and jump target LABEL. | |
2359 | This function exists to take advantage of the v9 brxx insns. */ | |
ab835497 | 2360 | |
e0d80184 DM |
2361 | void |
2362 | emit_v9_brxx_insn (code, op0, label) | |
2363 | enum rtx_code code; | |
2364 | rtx op0, label; | |
ab835497 | 2365 | { |
e0d80184 DM |
2366 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
2367 | pc_rtx, | |
2368 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
2369 | gen_rtx_fmt_ee (code, GET_MODE (op0), | |
2370 | op0, const0_rtx), | |
2371 | gen_rtx_LABEL_REF (VOIDmode, label), | |
2372 | pc_rtx))); | |
2373 | } | |
7b1ac798 JJ |
2374 | |
2375 | /* Generate a DFmode part of a hard TFmode register. | |
2376 | REG is the TFmode hard register, LOW is 1 for the | |
2377 | low 64bit of the register and 0 otherwise. | |
2378 | */ | |
2379 | rtx | |
2380 | gen_df_reg (reg, low) | |
2381 | rtx reg; | |
2382 | int low; | |
2383 | { | |
2384 | int regno = REGNO (reg); | |
2385 | ||
2386 | if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) | |
2aac41d6 | 2387 | regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2; |
7b1ac798 JJ |
2388 | return gen_rtx_REG (DFmode, regno); |
2389 | } | |
e0d80184 DM |
2390 | \f |
2391 | /* Return nonzero if a return peephole merging return with | |
2392 | setting of output register is ok. */ | |
2393 | int | |
2394 | leaf_return_peephole_ok () | |
2395 | { | |
2396 | return (actual_fsize == 0); | |
2397 | } | |
284d86e9 | 2398 | |
e0d80184 DM |
2399 | /* Return nonzero if TRIAL can go into the function epilogue's |
2400 | delay slot. SLOT is the slot we are trying to fill. */ | |
ab835497 | 2401 | |
e0d80184 DM |
2402 | int |
2403 | eligible_for_epilogue_delay (trial, slot) | |
2404 | rtx trial; | |
2405 | int slot; | |
2406 | { | |
2407 | rtx pat, src; | |
4fb4e4b8 | 2408 | |
e0d80184 DM |
2409 | if (slot >= 1) |
2410 | return 0; | |
4fb4e4b8 | 2411 | |
e0d80184 DM |
2412 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) |
2413 | return 0; | |
4fb4e4b8 | 2414 | |
e0d80184 DM |
2415 | if (get_attr_length (trial) != 1) |
2416 | return 0; | |
4fb4e4b8 | 2417 | |
e48addee JJ |
2418 | /* If there are any call-saved registers, we should scan TRIAL if it |
2419 | does not reference them. For now just make it easy. */ | |
2420 | if (num_gfregs) | |
2421 | return 0; | |
4fb4e4b8 | 2422 | |
1150a841 RH |
2423 | /* If the function uses __builtin_eh_return, the eh_return machinery |
2424 | occupies the delay slot. */ | |
2425 | if (current_function_calls_eh_return) | |
2426 | return 0; | |
2427 | ||
e0d80184 DM |
2428 | /* In the case of a true leaf function, anything can go into the delay slot. |
2429 | A delay slot only exists however if the frame size is zero, otherwise | |
2430 | we will put an insn to adjust the stack after the return. */ | |
54ff41b7 | 2431 | if (current_function_uses_only_leaf_regs) |
4fb4e4b8 | 2432 | { |
e0d80184 DM |
2433 | if (leaf_return_peephole_ok ()) |
2434 | return ((get_attr_in_uncond_branch_delay (trial) | |
2435 | == IN_BRANCH_DELAY_TRUE)); | |
2436 | return 0; | |
4fb4e4b8 | 2437 | } |
4fb4e4b8 | 2438 | |
e0d80184 | 2439 | pat = PATTERN (trial); |
795068a4 | 2440 | |
e0d80184 | 2441 | /* Otherwise, only operations which can be done in tandem with |
e48addee | 2442 | a `restore' or `return' insn can go into the delay slot. */ |
e0d80184 | 2443 | if (GET_CODE (SET_DEST (pat)) != REG |
e0d80184 DM |
2444 | || REGNO (SET_DEST (pat)) < 24) |
2445 | return 0; | |
795068a4 | 2446 | |
c137830f JJ |
2447 | /* If this instruction sets up floating point register and we have a return |
2448 | instruction, it can probably go in. But restore will not work | |
2449 | with FP_REGS. */ | |
2450 | if (REGNO (SET_DEST (pat)) >= 32) | |
2451 | { | |
2452 | if (TARGET_V9 && ! epilogue_renumber (&pat, 1) | |
2453 | && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) | |
2454 | return 1; | |
2455 | return 0; | |
2456 | } | |
2457 | ||
e0d80184 DM |
2458 | /* The set of insns matched here must agree precisely with the set of |
2459 | patterns paired with a RETURN in sparc.md. */ | |
795068a4 | 2460 | |
e0d80184 | 2461 | src = SET_SRC (pat); |
795068a4 | 2462 | |
3c6088d2 | 2463 | /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */ |
3ec6f1a9 RK |
2464 | if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2465 | && arith_operand (src, GET_MODE (src))) | |
3c6088d2 JJ |
2466 | { |
2467 | if (TARGET_ARCH64) | |
2468 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2469 | else | |
2470 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
2471 | } | |
e48addee | 2472 | |
e0d80184 | 2473 | /* This matches "*return_di". */ |
3ec6f1a9 RK |
2474 | else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2475 | && arith_double_operand (src, GET_MODE (src))) | |
e0d80184 | 2476 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); |
795068a4 | 2477 | |
e0d80184 DM |
2478 | /* This matches "*return_sf_no_fpu". */ |
2479 | else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) | |
2480 | && register_operand (src, SFmode)) | |
2481 | return 1; | |
f5da225e | 2482 | |
e48addee JJ |
2483 | /* If we have return instruction, anything that does not use |
2484 | local or output registers and can go into a delay slot wins. */ | |
2485 | else if (TARGET_V9 && ! epilogue_renumber (&pat, 1) | |
2486 | && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) | |
2487 | return 1; | |
2488 | ||
e0d80184 DM |
2489 | /* This matches "*return_addsi". */ |
2490 | else if (GET_CODE (src) == PLUS | |
2491 | && arith_operand (XEXP (src, 0), SImode) | |
2492 | && arith_operand (XEXP (src, 1), SImode) | |
2493 | && (register_operand (XEXP (src, 0), SImode) | |
2494 | || register_operand (XEXP (src, 1), SImode))) | |
2495 | return 1; | |
2496 | ||
2497 | /* This matches "*return_adddi". */ | |
2498 | else if (GET_CODE (src) == PLUS | |
2499 | && arith_double_operand (XEXP (src, 0), DImode) | |
2500 | && arith_double_operand (XEXP (src, 1), DImode) | |
2501 | && (register_operand (XEXP (src, 0), DImode) | |
2502 | || register_operand (XEXP (src, 1), DImode))) | |
795068a4 | 2503 | return 1; |
795068a4 | 2504 | |
e48addee JJ |
2505 | /* This can match "*return_losum_[sd]i". |
2506 | Catch only some cases, so that return_losum* don't have | |
2507 | to be too big. */ | |
2508 | else if (GET_CODE (src) == LO_SUM | |
2509 | && ! TARGET_CM_MEDMID | |
2510 | && ((register_operand (XEXP (src, 0), SImode) | |
2511 | && immediate_operand (XEXP (src, 1), SImode)) | |
2512 | || (TARGET_ARCH64 | |
2513 | && register_operand (XEXP (src, 0), DImode) | |
2514 | && immediate_operand (XEXP (src, 1), DImode)))) | |
2515 | return 1; | |
2516 | ||
2517 | /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */ | |
2518 | else if (GET_CODE (src) == ASHIFT | |
2519 | && (register_operand (XEXP (src, 0), SImode) | |
2520 | || register_operand (XEXP (src, 0), DImode)) | |
2521 | && XEXP (src, 1) == const1_rtx) | |
2522 | return 1; | |
2523 | ||
795068a4 JW |
2524 | return 0; |
2525 | } | |
2526 | ||
7d167afd JJ |
2527 | /* Return nonzero if TRIAL can go into the sibling call |
2528 | delay slot. */ | |
2529 | ||
2530 | int | |
2531 | eligible_for_sibcall_delay (trial) | |
2532 | rtx trial; | |
2533 | { | |
2534 | rtx pat, src; | |
2535 | ||
2536 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) | |
2537 | return 0; | |
2538 | ||
2539 | if (get_attr_length (trial) != 1 || profile_block_flag == 2) | |
2540 | return 0; | |
2541 | ||
2542 | pat = PATTERN (trial); | |
2543 | ||
2544 | if (current_function_uses_only_leaf_regs) | |
2545 | { | |
2546 | /* If the tail call is done using the call instruction, | |
2547 | we have to restore %o7 in the delay slot. */ | |
2be5e524 | 2548 | if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic) |
7d167afd JJ |
2549 | return 0; |
2550 | ||
2551 | /* %g1 is used to build the function address */ | |
2552 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) | |
2553 | return 0; | |
2554 | ||
2555 | return 1; | |
2556 | } | |
2557 | ||
2558 | /* Otherwise, only operations which can be done in tandem with | |
2559 | a `restore' insn can go into the delay slot. */ | |
2560 | if (GET_CODE (SET_DEST (pat)) != REG | |
2561 | || REGNO (SET_DEST (pat)) < 24 | |
2562 | || REGNO (SET_DEST (pat)) >= 32) | |
2563 | return 0; | |
2564 | ||
2565 | /* If it mentions %o7, it can't go in, because sibcall will clobber it | |
2566 | in most cases. */ | |
2567 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) | |
2568 | return 0; | |
2569 | ||
2570 | src = SET_SRC (pat); | |
2571 | ||
3ec6f1a9 RK |
2572 | if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2573 | && arith_operand (src, GET_MODE (src))) | |
7d167afd JJ |
2574 | { |
2575 | if (TARGET_ARCH64) | |
2576 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2577 | else | |
2578 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
2579 | } | |
2580 | ||
3ec6f1a9 RK |
2581 | else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2582 | && arith_double_operand (src, GET_MODE (src))) | |
7d167afd JJ |
2583 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); |
2584 | ||
2585 | else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) | |
2586 | && register_operand (src, SFmode)) | |
2587 | return 1; | |
2588 | ||
2589 | else if (GET_CODE (src) == PLUS | |
2590 | && arith_operand (XEXP (src, 0), SImode) | |
2591 | && arith_operand (XEXP (src, 1), SImode) | |
2592 | && (register_operand (XEXP (src, 0), SImode) | |
2593 | || register_operand (XEXP (src, 1), SImode))) | |
2594 | return 1; | |
2595 | ||
2596 | else if (GET_CODE (src) == PLUS | |
2597 | && arith_double_operand (XEXP (src, 0), DImode) | |
2598 | && arith_double_operand (XEXP (src, 1), DImode) | |
2599 | && (register_operand (XEXP (src, 0), DImode) | |
2600 | || register_operand (XEXP (src, 1), DImode))) | |
2601 | return 1; | |
2602 | ||
2603 | else if (GET_CODE (src) == LO_SUM | |
2604 | && ! TARGET_CM_MEDMID | |
2605 | && ((register_operand (XEXP (src, 0), SImode) | |
2606 | && immediate_operand (XEXP (src, 1), SImode)) | |
2607 | || (TARGET_ARCH64 | |
2608 | && register_operand (XEXP (src, 0), DImode) | |
2609 | && immediate_operand (XEXP (src, 1), DImode)))) | |
2610 | return 1; | |
2611 | ||
2612 | else if (GET_CODE (src) == ASHIFT | |
2613 | && (register_operand (XEXP (src, 0), SImode) | |
2614 | || register_operand (XEXP (src, 0), DImode)) | |
2615 | && XEXP (src, 1) == const1_rtx) | |
2616 | return 1; | |
2617 | ||
2618 | return 0; | |
2619 | } | |
2620 | ||
e0d80184 DM |
2621 | static int |
2622 | check_return_regs (x) | |
2623 | rtx x; | |
ab835497 | 2624 | { |
e0d80184 DM |
2625 | switch (GET_CODE (x)) |
2626 | { | |
2627 | case REG: | |
2628 | return IN_OR_GLOBAL_P (x); | |
ab835497 | 2629 | |
e0d80184 DM |
2630 | case CONST_INT: |
2631 | case CONST_DOUBLE: | |
2632 | case CONST: | |
2633 | case SYMBOL_REF: | |
2634 | case LABEL_REF: | |
2635 | return 1; | |
ab835497 | 2636 | |
e0d80184 DM |
2637 | case SET: |
2638 | case IOR: | |
2639 | case AND: | |
2640 | case XOR: | |
2641 | case PLUS: | |
2642 | case MINUS: | |
2643 | if (check_return_regs (XEXP (x, 1)) == 0) | |
2644 | return 0; | |
2645 | case NOT: | |
2646 | case NEG: | |
2647 | case MEM: | |
2648 | return check_return_regs (XEXP (x, 0)); | |
2649 | ||
2650 | default: | |
2651 | return 0; | |
2652 | } | |
ab835497 | 2653 | |
e0d80184 | 2654 | } |
ab835497 | 2655 | |
e0d80184 DM |
2656 | /* Return 1 if TRIAL references only in and global registers. */ |
2657 | int | |
2658 | eligible_for_return_delay (trial) | |
2659 | rtx trial; | |
2660 | { | |
2661 | if (GET_CODE (PATTERN (trial)) != SET) | |
2662 | return 0; | |
ab835497 | 2663 | |
e0d80184 DM |
2664 | return check_return_regs (PATTERN (trial)); |
2665 | } | |
ab835497 | 2666 | |
e0d80184 DM |
2667 | int |
2668 | short_branch (uid1, uid2) | |
2669 | int uid1, uid2; | |
2670 | { | |
9d98a694 | 2671 | int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2); |
77b91512 RK |
2672 | |
2673 | /* Leave a few words of "slop". */ | |
2674 | if (delta >= -1023 && delta <= 1022) | |
e0d80184 | 2675 | return 1; |
77b91512 | 2676 | |
e0d80184 DM |
2677 | return 0; |
2678 | } | |
ab835497 | 2679 | |
e0d80184 DM |
2680 | /* Return non-zero if REG is not used after INSN. |
2681 | We assume REG is a reload reg, and therefore does | |
2682 | not live past labels or calls or jumps. */ | |
2683 | int | |
2684 | reg_unused_after (reg, insn) | |
2685 | rtx reg; | |
2686 | rtx insn; | |
2687 | { | |
2688 | enum rtx_code code, prev_code = UNKNOWN; | |
ab835497 | 2689 | |
e0d80184 | 2690 | while ((insn = NEXT_INSN (insn))) |
61a55e8b | 2691 | { |
e0d80184 DM |
2692 | if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) |
2693 | return 1; | |
ab835497 | 2694 | |
e0d80184 DM |
2695 | code = GET_CODE (insn); |
2696 | if (GET_CODE (insn) == CODE_LABEL) | |
2697 | return 1; | |
bc961ed7 | 2698 | |
e0d80184 | 2699 | if (GET_RTX_CLASS (code) == 'i') |
61a55e8b | 2700 | { |
e0d80184 DM |
2701 | rtx set = single_set (insn); |
2702 | int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); | |
2703 | if (set && in_src) | |
2704 | return 0; | |
2705 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
2706 | return 1; | |
2707 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
2708 | return 0; | |
61a55e8b | 2709 | } |
e0d80184 | 2710 | prev_code = code; |
61a55e8b | 2711 | } |
e0d80184 DM |
2712 | return 1; |
2713 | } | |
2714 | \f | |
2715 | /* The table we use to reference PIC data. */ | |
2716 | static rtx global_offset_table; | |
bc961ed7 | 2717 | |
e0d80184 DM |
2718 | /* The function we use to get at it. */ |
2719 | static rtx get_pc_symbol; | |
2720 | static char get_pc_symbol_name[256]; | |
ab835497 | 2721 | |
e0d80184 | 2722 | /* Ensure that we are not using patterns that are not OK with PIC. */ |
795068a4 | 2723 | |
e0d80184 DM |
2724 | int |
2725 | check_pic (i) | |
2726 | int i; | |
2727 | { | |
2728 | switch (flag_pic) | |
ab835497 | 2729 | { |
e0d80184 | 2730 | case 1: |
1ccbefce RH |
2731 | if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF |
2732 | || (GET_CODE (recog_data.operand[i]) == CONST | |
2733 | && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS | |
2734 | && (XEXP (XEXP (recog_data.operand[i], 0), 0) | |
e0d80184 | 2735 | == global_offset_table) |
1ccbefce | 2736 | && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) |
e0d80184 DM |
2737 | == CONST)))) |
2738 | abort (); | |
2739 | case 2: | |
2740 | default: | |
2741 | return 1; | |
ab835497 | 2742 | } |
ab835497 | 2743 | } |
795068a4 | 2744 | |
e0d80184 DM |
2745 | /* Return true if X is an address which needs a temporary register when |
2746 | reloaded while generating PIC code. */ | |
795068a4 | 2747 | |
e0d80184 DM |
2748 | int |
2749 | pic_address_needs_scratch (x) | |
2750 | rtx x; | |
795068a4 | 2751 | { |
e0d80184 DM |
2752 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ |
2753 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
2754 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
2755 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2756 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
2757 | return 1; | |
795068a4 | 2758 | |
e0d80184 DM |
2759 | return 0; |
2760 | } | |
795068a4 | 2761 | |
e0d80184 DM |
2762 | /* Legitimize PIC addresses. If the address is already position-independent, |
2763 | we return ORIG. Newly generated position-independent addresses go into a | |
2764 | reg. This is REG if non zero, otherwise we allocate register(s) as | |
2765 | necessary. */ | |
795068a4 | 2766 | |
e0d80184 DM |
2767 | rtx |
2768 | legitimize_pic_address (orig, mode, reg) | |
2769 | rtx orig; | |
2770 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
2771 | rtx reg; | |
2772 | { | |
2773 | if (GET_CODE (orig) == SYMBOL_REF) | |
82d6b402 | 2774 | { |
e0d80184 DM |
2775 | rtx pic_ref, address; |
2776 | rtx insn; | |
82d6b402 | 2777 | |
e0d80184 | 2778 | if (reg == 0) |
82d6b402 | 2779 | { |
e0d80184 DM |
2780 | if (reload_in_progress || reload_completed) |
2781 | abort (); | |
2782 | else | |
2783 | reg = gen_reg_rtx (Pmode); | |
82d6b402 | 2784 | } |
795068a4 | 2785 | |
e0d80184 | 2786 | if (flag_pic == 2) |
4fb4e4b8 | 2787 | { |
e0d80184 DM |
2788 | /* If not during reload, allocate another temp reg here for loading |
2789 | in the address, so that these instructions can be optimized | |
2790 | properly. */ | |
2791 | rtx temp_reg = ((reload_in_progress || reload_completed) | |
2792 | ? reg : gen_reg_rtx (Pmode)); | |
2793 | ||
2794 | /* Must put the SYMBOL_REF inside an UNSPEC here so that cse | |
2795 | won't get confused into thinking that these two instructions | |
2796 | are loading in the true address of the symbol. If in the | |
2797 | future a PIC rtx exists, that should be used instead. */ | |
be3f1ff5 DM |
2798 | if (Pmode == SImode) |
2799 | { | |
2800 | emit_insn (gen_movsi_high_pic (temp_reg, orig)); | |
2801 | emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
2802 | } | |
2803 | else | |
2804 | { | |
2805 | emit_insn (gen_movdi_high_pic (temp_reg, orig)); | |
2806 | emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
2807 | } | |
e0d80184 | 2808 | address = temp_reg; |
4fb4e4b8 DE |
2809 | } |
2810 | else | |
e0d80184 DM |
2811 | address = orig; |
2812 | ||
2813 | pic_ref = gen_rtx_MEM (Pmode, | |
2814 | gen_rtx_PLUS (Pmode, | |
2815 | pic_offset_table_rtx, address)); | |
2816 | current_function_uses_pic_offset_table = 1; | |
2817 | RTX_UNCHANGING_P (pic_ref) = 1; | |
2818 | insn = emit_move_insn (reg, pic_ref); | |
2819 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
2820 | by loop. */ | |
2821 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, | |
2822 | REG_NOTES (insn)); | |
2823 | return reg; | |
795068a4 | 2824 | } |
e0d80184 | 2825 | else if (GET_CODE (orig) == CONST) |
795068a4 | 2826 | { |
e0d80184 | 2827 | rtx base, offset; |
795068a4 | 2828 | |
e0d80184 DM |
2829 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
2830 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
2831 | return orig; | |
82d6b402 | 2832 | |
e0d80184 | 2833 | if (reg == 0) |
4fb4e4b8 | 2834 | { |
e0d80184 DM |
2835 | if (reload_in_progress || reload_completed) |
2836 | abort (); | |
2837 | else | |
2838 | reg = gen_reg_rtx (Pmode); | |
4fb4e4b8 | 2839 | } |
e0d80184 DM |
2840 | |
2841 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
4fb4e4b8 | 2842 | { |
e0d80184 DM |
2843 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
2844 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
2845 | base == reg ? 0 : reg); | |
4fb4e4b8 DE |
2846 | } |
2847 | else | |
61a66555 JW |
2848 | abort (); |
2849 | ||
e0d80184 DM |
2850 | if (GET_CODE (offset) == CONST_INT) |
2851 | { | |
2852 | if (SMALL_INT (offset)) | |
ed8908e7 | 2853 | return plus_constant (base, INTVAL (offset)); |
e0d80184 DM |
2854 | else if (! reload_in_progress && ! reload_completed) |
2855 | offset = force_reg (Pmode, offset); | |
2856 | else | |
2857 | /* If we reach here, then something is seriously wrong. */ | |
2858 | abort (); | |
2859 | } | |
2860 | return gen_rtx_PLUS (Pmode, base, offset); | |
795068a4 | 2861 | } |
e0d80184 DM |
2862 | else if (GET_CODE (orig) == LABEL_REF) |
2863 | /* ??? Why do we do this? */ | |
2864 | /* Now movsi_pic_label_ref uses it, but we ought to be checking that | |
2865 | the register is live instead, in case it is eliminated. */ | |
2866 | current_function_uses_pic_offset_table = 1; | |
795068a4 | 2867 | |
e0d80184 DM |
2868 | return orig; |
2869 | } | |
795068a4 | 2870 | |
fccf9848 | 2871 | /* Emit special PIC prologues. */ |
795068a4 | 2872 | |
e0d80184 | 2873 | void |
fccf9848 | 2874 | load_pic_register () |
e0d80184 DM |
2875 | { |
2876 | /* Labels to get the PC in the prologue of this function. */ | |
2877 | int orig_flag_pic = flag_pic; | |
4fb4e4b8 | 2878 | |
e0d80184 DM |
2879 | if (! flag_pic) |
2880 | abort (); | |
2881 | ||
2882 | /* If we havn't emitted the special get_pc helper function, do so now. */ | |
2883 | if (get_pc_symbol_name[0] == 0) | |
4fb4e4b8 | 2884 | { |
d676da68 | 2885 | int align; |
82d6b402 | 2886 | |
d676da68 | 2887 | ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0); |
e0d80184 | 2888 | text_section (); |
d676da68 DM |
2889 | |
2890 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
2891 | if (align > 0) | |
2892 | ASM_OUTPUT_ALIGN (asm_out_file, align); | |
e0d80184 | 2893 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0); |
4df1190a | 2894 | fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file); |
e0d80184 | 2895 | } |
82d6b402 | 2896 | |
e0d80184 DM |
2897 | /* Initialize every time through, since we can't easily |
2898 | know this to be permanent. */ | |
2899 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
2900 | get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name); | |
2901 | flag_pic = 0; | |
82d6b402 | 2902 | |
fccf9848 JJ |
2903 | emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, |
2904 | get_pc_symbol)); | |
82d6b402 | 2905 | |
e0d80184 | 2906 | flag_pic = orig_flag_pic; |
82d6b402 | 2907 | |
e0d80184 DM |
2908 | /* Need to emit this whether or not we obey regdecls, |
2909 | since setjmp/longjmp can cause life info to screw up. | |
2910 | ??? In the case where we don't obey regdecls, this is not sufficient | |
2911 | since we may not fall out the bottom. */ | |
2912 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); | |
795068a4 | 2913 | } |
ab835497 | 2914 | \f |
e0d80184 DM |
2915 | /* Return 1 if RTX is a MEM which is known to be aligned to at |
2916 | least an 8 byte boundary. */ | |
a3ee5899 | 2917 | |
e0d80184 DM |
2918 | int |
2919 | mem_min_alignment (mem, desired) | |
2920 | rtx mem; | |
2921 | int desired; | |
ab835497 | 2922 | { |
e0d80184 DM |
2923 | rtx addr, base, offset; |
2924 | ||
2925 | /* If it's not a MEM we can't accept it. */ | |
2926 | if (GET_CODE (mem) != MEM) | |
2927 | return 0; | |
2928 | ||
2929 | addr = XEXP (mem, 0); | |
2930 | base = offset = NULL_RTX; | |
2931 | if (GET_CODE (addr) == PLUS) | |
ab835497 | 2932 | { |
e0d80184 | 2933 | if (GET_CODE (XEXP (addr, 0)) == REG) |
61a55e8b | 2934 | { |
e0d80184 DM |
2935 | base = XEXP (addr, 0); |
2936 | ||
2937 | /* What we are saying here is that if the base | |
2938 | REG is aligned properly, the compiler will make | |
2939 | sure any REG based index upon it will be so | |
2940 | as well. */ | |
2941 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
2942 | offset = XEXP (addr, 1); | |
61a55e8b | 2943 | else |
e0d80184 | 2944 | offset = const0_rtx; |
61a55e8b | 2945 | } |
ab835497 | 2946 | } |
e0d80184 | 2947 | else if (GET_CODE (addr) == REG) |
ab835497 | 2948 | { |
e0d80184 DM |
2949 | base = addr; |
2950 | offset = const0_rtx; | |
ab835497 | 2951 | } |
82d6b402 | 2952 | |
e0d80184 | 2953 | if (base != NULL_RTX) |
795068a4 | 2954 | { |
e0d80184 DM |
2955 | int regno = REGNO (base); |
2956 | ||
2957 | if (regno != FRAME_POINTER_REGNUM | |
2958 | && regno != STACK_POINTER_REGNUM) | |
61a55e8b | 2959 | { |
e0d80184 DM |
2960 | /* Check if the compiler has recorded some information |
2961 | about the alignment of the base REG. If reload has | |
021e2ecc JJ |
2962 | completed, we already matched with proper alignments. |
2963 | If not running global_alloc, reload might give us | |
2964 | unaligned pointer to local stack though. */ | |
bdb429a5 RK |
2965 | if (((cfun != 0 |
2966 | && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT) | |
021e2ecc | 2967 | || (optimize && reload_completed)) |
bdb429a5 | 2968 | && (INTVAL (offset) & (desired - 1)) == 0) |
e0d80184 | 2969 | return 1; |
61a55e8b | 2970 | } |
795068a4 | 2971 | else |
e0d80184 DM |
2972 | { |
2973 | if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) | |
2974 | return 1; | |
2975 | } | |
795068a4 | 2976 | } |
e0d80184 DM |
2977 | else if (! TARGET_UNALIGNED_DOUBLES |
2978 | || CONSTANT_P (addr) | |
2979 | || GET_CODE (addr) == LO_SUM) | |
795068a4 | 2980 | { |
e0d80184 DM |
2981 | /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES |
2982 | is true, in which case we can only assume that an access is aligned if | |
2983 | it is to a constant address, or the address involves a LO_SUM. */ | |
2984 | return 1; | |
795068a4 | 2985 | } |
e0d80184 DM |
2986 | |
2987 | /* An obviously unaligned address. */ | |
2988 | return 0; | |
795068a4 | 2989 | } |
e0d80184 | 2990 | |
ab835497 | 2991 | \f |
61a55e8b DE |
2992 | /* Vectors to keep interesting information about registers where it can easily |
2993 | be got. We use to use the actual mode value as the bit number, but there | |
2994 | are more than 32 modes now. Instead we use two tables: one indexed by | |
2995 | hard register number, and one indexed by mode. */ | |
2996 | ||
2997 | /* The purpose of sparc_mode_class is to shrink the range of modes so that | |
2998 | they all fit (as bit numbers) in a 32 bit word (again). Each real mode is | |
2999 | mapped into one sparc_mode_class mode. */ | |
3000 | ||
3001 | enum sparc_mode_class { | |
61a55e8b | 3002 | S_MODE, D_MODE, T_MODE, O_MODE, |
c4ce6853 DE |
3003 | SF_MODE, DF_MODE, TF_MODE, OF_MODE, |
3004 | CC_MODE, CCFP_MODE | |
61a55e8b | 3005 | }; |
ab835497 | 3006 | |
61a55e8b DE |
3007 | /* Modes for single-word and smaller quantities. */ |
3008 | #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
3009 | ||
3010 | /* Modes for double-word and smaller quantities. */ | |
3011 | #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) | |
3012 | ||
3013 | /* Modes for quad-word and smaller quantities. */ | |
3014 | #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
ab835497 | 3015 | |
d0cee9ba JJ |
3016 | /* Modes for 8-word and smaller quantities. */ |
3017 | #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) | |
3018 | ||
1e4eb8d1 JW |
3019 | /* Modes for single-float quantities. We must allow any single word or |
3020 | smaller quantity. This is because the fix/float conversion instructions | |
3021 | take integer inputs/outputs from the float registers. */ | |
3022 | #define SF_MODES (S_MODES) | |
ab835497 | 3023 | |
61a55e8b DE |
3024 | /* Modes for double-float and smaller quantities. */ |
3025 | #define DF_MODES (S_MODES | D_MODES) | |
3026 | ||
61a55e8b | 3027 | /* Modes for double-float only quantities. */ |
d0cee9ba | 3028 | #define DF_MODES_NO_S (D_MODES) |
ab835497 | 3029 | |
61a55e8b DE |
3030 | /* Modes for quad-float only quantities. */ |
3031 | #define TF_ONLY_MODES (1 << (int) TF_MODE) | |
3032 | ||
3033 | /* Modes for quad-float and smaller quantities. */ | |
3034 | #define TF_MODES (DF_MODES | TF_ONLY_MODES) | |
3035 | ||
d0cee9ba JJ |
3036 | /* Modes for quad-float and double-float quantities. */ |
3037 | #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES) | |
3038 | ||
3039 | /* Modes for quad-float pair only quantities. */ | |
3040 | #define OF_ONLY_MODES (1 << (int) OF_MODE) | |
3041 | ||
3042 | /* Modes for quad-float pairs and smaller quantities. */ | |
3043 | #define OF_MODES (TF_MODES | OF_ONLY_MODES) | |
3044 | ||
3045 | #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES) | |
ab835497 | 3046 | |
c4ce6853 DE |
3047 | /* Modes for condition codes. */ |
3048 | #define CC_MODES (1 << (int) CC_MODE) | |
3049 | #define CCFP_MODES (1 << (int) CCFP_MODE) | |
3050 | ||
ab835497 RK |
3051 | /* Value is 1 if register/mode pair is acceptable on sparc. |
3052 | The funny mixture of D and T modes is because integer operations | |
3053 | do not specially operate on tetra quantities, so non-quad-aligned | |
3054 | registers can hold quadword quantities (except %o4 and %i4 because | |
c4ce6853 | 3055 | they cross fixed registers). */ |
ab835497 | 3056 | |
61a55e8b DE |
3057 | /* This points to either the 32 bit or the 64 bit version. */ |
3058 | int *hard_regno_mode_classes; | |
3059 | ||
3060 | static int hard_32bit_mode_classes[] = { | |
c4ce6853 | 3061 | S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, |
ab835497 RK |
3062 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, |
3063 | T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
3064 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
3065 | ||
d0cee9ba JJ |
3066 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
3067 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3068 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3069 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
a9e27770 DE |
3070 | |
3071 | /* FP regs f32 to f63. Only the even numbered registers actually exist, | |
3072 | and none can hold SFmode/SImode values. */ | |
d0cee9ba JJ |
3073 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
3074 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3075 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3076 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
a9e27770 DE |
3077 | |
3078 | /* %fcc[0123] */ | |
c4ce6853 DE |
3079 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
3080 | ||
3081 | /* %icc */ | |
3082 | CC_MODES | |
61a55e8b DE |
3083 | }; |
3084 | ||
3085 | static int hard_64bit_mode_classes[] = { | |
c4ce6853 | 3086 | D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 3087 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 3088 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 3089 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 3090 | |
d0cee9ba JJ |
3091 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
3092 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3093 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3094 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
61a55e8b | 3095 | |
a9e27770 | 3096 | /* FP regs f32 to f63. Only the even numbered registers actually exist, |
61a55e8b | 3097 | and none can hold SFmode/SImode values. */ |
d0cee9ba JJ |
3098 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
3099 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3100 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3101 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
61a55e8b DE |
3102 | |
3103 | /* %fcc[0123] */ | |
c4ce6853 DE |
3104 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
3105 | ||
3106 | /* %icc */ | |
3107 | CC_MODES | |
61a55e8b DE |
3108 | }; |
3109 | ||
3110 | int sparc_mode_class [NUM_MACHINE_MODES]; | |
3111 | ||
c4ce6853 DE |
3112 | enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
3113 | ||
61a55e8b DE |
3114 | static void |
3115 | sparc_init_modes () | |
3116 | { | |
3117 | int i; | |
3118 | ||
61a55e8b DE |
3119 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
3120 | { | |
3121 | switch (GET_MODE_CLASS (i)) | |
3122 | { | |
3123 | case MODE_INT: | |
3124 | case MODE_PARTIAL_INT: | |
3125 | case MODE_COMPLEX_INT: | |
3126 | if (GET_MODE_SIZE (i) <= 4) | |
3127 | sparc_mode_class[i] = 1 << (int) S_MODE; | |
3128 | else if (GET_MODE_SIZE (i) == 8) | |
3129 | sparc_mode_class[i] = 1 << (int) D_MODE; | |
3130 | else if (GET_MODE_SIZE (i) == 16) | |
3131 | sparc_mode_class[i] = 1 << (int) T_MODE; | |
3132 | else if (GET_MODE_SIZE (i) == 32) | |
3133 | sparc_mode_class[i] = 1 << (int) O_MODE; | |
3134 | else | |
3135 | sparc_mode_class[i] = 0; | |
3136 | break; | |
3137 | case MODE_FLOAT: | |
3138 | case MODE_COMPLEX_FLOAT: | |
3139 | if (GET_MODE_SIZE (i) <= 4) | |
3140 | sparc_mode_class[i] = 1 << (int) SF_MODE; | |
3141 | else if (GET_MODE_SIZE (i) == 8) | |
3142 | sparc_mode_class[i] = 1 << (int) DF_MODE; | |
3143 | else if (GET_MODE_SIZE (i) == 16) | |
3144 | sparc_mode_class[i] = 1 << (int) TF_MODE; | |
3145 | else if (GET_MODE_SIZE (i) == 32) | |
3146 | sparc_mode_class[i] = 1 << (int) OF_MODE; | |
3147 | else | |
3148 | sparc_mode_class[i] = 0; | |
3149 | break; | |
3150 | case MODE_CC: | |
3151 | default: | |
3152 | /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so | |
3153 | we must explicitly check for them here. */ | |
3154 | if (i == (int) CCFPmode || i == (int) CCFPEmode) | |
3155 | sparc_mode_class[i] = 1 << (int) CCFP_MODE; | |
3156 | else if (i == (int) CCmode || i == (int) CC_NOOVmode | |
a9e27770 | 3157 | || i == (int) CCXmode || i == (int) CCX_NOOVmode) |
c4ce6853 | 3158 | sparc_mode_class[i] = 1 << (int) CC_MODE; |
61a55e8b DE |
3159 | else |
3160 | sparc_mode_class[i] = 0; | |
3161 | break; | |
3162 | } | |
3163 | } | |
3164 | ||
a9e27770 | 3165 | if (TARGET_ARCH64) |
61a55e8b DE |
3166 | hard_regno_mode_classes = hard_64bit_mode_classes; |
3167 | else | |
3168 | hard_regno_mode_classes = hard_32bit_mode_classes; | |
c4ce6853 DE |
3169 | |
3170 | /* Initialize the array used by REGNO_REG_CLASS. */ | |
3171 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3172 | { | |
284d86e9 JC |
3173 | if (i < 16 && TARGET_V8PLUS) |
3174 | sparc_regno_reg_class[i] = I64_REGS; | |
3175 | else if (i < 32) | |
c4ce6853 DE |
3176 | sparc_regno_reg_class[i] = GENERAL_REGS; |
3177 | else if (i < 64) | |
3178 | sparc_regno_reg_class[i] = FP_REGS; | |
3179 | else if (i < 96) | |
3180 | sparc_regno_reg_class[i] = EXTRA_FP_REGS; | |
3181 | else if (i < 100) | |
3182 | sparc_regno_reg_class[i] = FPCC_REGS; | |
3183 | else | |
3184 | sparc_regno_reg_class[i] = NO_REGS; | |
3185 | } | |
61a55e8b | 3186 | } |
ab835497 | 3187 | \f |
61a55e8b DE |
3188 | /* Save non call used registers from LOW to HIGH at BASE+OFFSET. |
3189 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
3190 | v9 int regs as it simplifies the code. */ | |
3191 | ||
ab835497 | 3192 | static int |
c53aa195 | 3193 | save_regs (file, low, high, base, offset, n_regs, real_offset) |
ab835497 RK |
3194 | FILE *file; |
3195 | int low, high; | |
3bb5de61 | 3196 | const char *base; |
ab835497 | 3197 | int offset; |
61a55e8b | 3198 | int n_regs; |
c53aa195 | 3199 | int real_offset; |
ab835497 RK |
3200 | { |
3201 | int i; | |
3202 | ||
a9e27770 | 3203 | if (TARGET_ARCH64 && high <= 32) |
ab835497 | 3204 | { |
61a55e8b DE |
3205 | for (i = low; i < high; i++) |
3206 | { | |
3207 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 3208 | { |
e0d80184 | 3209 | fprintf (file, "\tstx\t%s, [%s+%d]\n", |
c53aa195 | 3210 | reg_names[i], base, offset + 4 * n_regs); |
0021b564 | 3211 | if (dwarf2out_do_frame ()) |
c53aa195 | 3212 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); |
c53aa195 JM |
3213 | n_regs += 2; |
3214 | } | |
61a55e8b | 3215 | } |
ab835497 | 3216 | } |
61a55e8b DE |
3217 | else |
3218 | { | |
3219 | for (i = low; i < high; i += 2) | |
3220 | { | |
3221 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 3222 | { |
5e9defae KG |
3223 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) |
3224 | { | |
e0d80184 | 3225 | fprintf (file, "\tstd\t%s, [%s+%d]\n", |
5e9defae KG |
3226 | reg_names[i], base, offset + 4 * n_regs); |
3227 | if (dwarf2out_do_frame ()) | |
3228 | { | |
3229 | char *l = dwarf2out_cfi_label (); | |
3230 | dwarf2out_reg_save (l, i, real_offset + 4 * n_regs); | |
3231 | dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4); | |
3232 | } | |
3233 | n_regs += 2; | |
3234 | } | |
3235 | else | |
3236 | { | |
e0d80184 | 3237 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
3238 | reg_names[i], base, offset + 4 * n_regs); |
3239 | if (dwarf2out_do_frame ()) | |
3240 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); | |
3241 | n_regs += 2; | |
3242 | } | |
3243 | } | |
3244 | else | |
3245 | { | |
3246 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
3247 | { | |
e0d80184 | 3248 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
3249 | reg_names[i+1], base, offset + 4 * n_regs + 4); |
3250 | if (dwarf2out_do_frame ()) | |
3251 | dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4); | |
3252 | n_regs += 2; | |
3253 | } | |
c53aa195 | 3254 | } |
61a55e8b DE |
3255 | } |
3256 | } | |
3257 | return n_regs; | |
ab835497 RK |
3258 | } |
3259 | ||
61a55e8b DE |
3260 | /* Restore non call used registers from LOW to HIGH at BASE+OFFSET. |
3261 | ||
3262 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
3263 | v9 int regs as it simplifies the code. */ | |
3264 | ||
ab835497 | 3265 | static int |
61a55e8b | 3266 | restore_regs (file, low, high, base, offset, n_regs) |
ab835497 RK |
3267 | FILE *file; |
3268 | int low, high; | |
3bb5de61 | 3269 | const char *base; |
ab835497 | 3270 | int offset; |
61a55e8b | 3271 | int n_regs; |
ab835497 RK |
3272 | { |
3273 | int i; | |
3274 | ||
a9e27770 | 3275 | if (TARGET_ARCH64 && high <= 32) |
61a55e8b DE |
3276 | { |
3277 | for (i = low; i < high; i++) | |
3278 | { | |
3279 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
e0d80184 | 3280 | fprintf (file, "\tldx\t[%s+%d], %s\n", |
61a55e8b DE |
3281 | base, offset + 4 * n_regs, reg_names[i]), |
3282 | n_regs += 2; | |
3283 | } | |
3284 | } | |
3285 | else | |
ab835497 | 3286 | { |
61a55e8b DE |
3287 | for (i = low; i < high; i += 2) |
3288 | { | |
3289 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
3290 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
e0d80184 | 3291 | fprintf (file, "\tldd\t[%s+%d], %s\n", |
61a55e8b DE |
3292 | base, offset + 4 * n_regs, reg_names[i]), |
3293 | n_regs += 2; | |
3294 | else | |
4df1190a | 3295 | fprintf (file, "\tld\t[%s+%d], %s\n", |
61a55e8b DE |
3296 | base, offset + 4 * n_regs, reg_names[i]), |
3297 | n_regs += 2; | |
3298 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
4df1190a | 3299 | fprintf (file, "\tld\t[%s+%d], %s\n", |
61a55e8b DE |
3300 | base, offset + 4 * n_regs + 4, reg_names[i+1]), |
3301 | n_regs += 2; | |
3302 | } | |
ab835497 | 3303 | } |
61a55e8b | 3304 | return n_regs; |
ab835497 RK |
3305 | } |
3306 | ||
61a55e8b DE |
3307 | /* Compute the frame size required by the function. This function is called |
3308 | during the reload pass and also by output_function_prologue(). */ | |
ab835497 | 3309 | |
ab835497 RK |
3310 | int |
3311 | compute_frame_size (size, leaf_function) | |
3312 | int size; | |
3313 | int leaf_function; | |
3314 | { | |
61a55e8b | 3315 | int n_regs = 0, i; |
ab835497 | 3316 | int outgoing_args_size = (current_function_outgoing_args_size |
4fb4e4b8 | 3317 | + REG_PARM_STACK_SPACE (current_function_decl)); |
ab835497 | 3318 | |
61a55e8b | 3319 | if (TARGET_EPILOGUE) |
ab835497 | 3320 | { |
61a55e8b DE |
3321 | /* N_REGS is the number of 4-byte regs saved thus far. This applies |
3322 | even to v9 int regs to be consistent with save_regs/restore_regs. */ | |
3323 | ||
a9e27770 | 3324 | if (TARGET_ARCH64) |
61a55e8b DE |
3325 | { |
3326 | for (i = 0; i < 8; i++) | |
3327 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
3328 | n_regs += 2; | |
3329 | } | |
3330 | else | |
3331 | { | |
3332 | for (i = 0; i < 8; i += 2) | |
3333 | if ((regs_ever_live[i] && ! call_used_regs[i]) | |
3334 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
3335 | n_regs += 2; | |
3336 | } | |
3337 | ||
3338 | for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) | |
ab835497 RK |
3339 | if ((regs_ever_live[i] && ! call_used_regs[i]) |
3340 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
61a55e8b | 3341 | n_regs += 2; |
ab835497 RK |
3342 | } |
3343 | ||
3344 | /* Set up values for use in `function_epilogue'. */ | |
61a55e8b | 3345 | num_gfregs = n_regs; |
ab835497 | 3346 | |
61a55e8b DE |
3347 | if (leaf_function && n_regs == 0 |
3348 | && size == 0 && current_function_outgoing_args_size == 0) | |
3349 | { | |
3350 | actual_fsize = apparent_fsize = 0; | |
3351 | } | |
3352 | else | |
3353 | { | |
3354 | /* We subtract STARTING_FRAME_OFFSET, remember it's negative. | |
3355 | The stack bias (if any) is taken out to undo its effects. */ | |
3356 | apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8; | |
3357 | apparent_fsize += n_regs * 4; | |
3358 | actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); | |
3359 | } | |
ab835497 RK |
3360 | |
3361 | /* Make sure nothing can clobber our register windows. | |
3362 | If a SAVE must be done, or there is a stack-local variable, | |
61a55e8b | 3363 | the register window area must be allocated. |
4fb4e4b8 | 3364 | ??? For v8 we apparently need an additional 8 bytes of reserved space. */ |
ab835497 | 3365 | if (leaf_function == 0 || size > 0) |
4fb4e4b8 | 3366 | actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8); |
ab835497 | 3367 | |
61a55e8b DE |
3368 | return SPARC_STACK_ALIGN (actual_fsize); |
3369 | } | |
3370 | ||
3371 | /* Build a (32 bit) big number in a register. */ | |
86735b02 | 3372 | /* ??? We may be able to use the set macro here too. */ |
61a55e8b DE |
3373 | |
3374 | static void | |
3375 | build_big_number (file, num, reg) | |
3376 | FILE *file; | |
3377 | int num; | |
3bb5de61 | 3378 | const char *reg; |
61a55e8b | 3379 | { |
a9e27770 | 3380 | if (num >= 0 || ! TARGET_ARCH64) |
61a55e8b | 3381 | { |
e0d80184 | 3382 | fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg); |
61a55e8b | 3383 | if ((num & 0x3ff) != 0) |
e0d80184 | 3384 | fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg); |
61a55e8b | 3385 | } |
a9e27770 | 3386 | else /* num < 0 && TARGET_ARCH64 */ |
61a55e8b DE |
3387 | { |
3388 | /* Sethi does not sign extend, so we must use a little trickery | |
3389 | to use it for negative numbers. Invert the constant before | |
3390 | loading it in, then use xor immediate to invert the loaded bits | |
3391 | (along with the upper 32 bits) to the desired constant. This | |
3392 | works because the sethi and immediate fields overlap. */ | |
3393 | int asize = num; | |
3394 | int inv = ~asize; | |
3395 | int low = -0x400 + (asize & 0x3FF); | |
3396 | ||
e0d80184 | 3397 | fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n", |
61a55e8b DE |
3398 | inv, reg, reg, low, reg); |
3399 | } | |
ab835497 RK |
3400 | } |
3401 | ||
1cb36a98 RH |
3402 | /* Output any necessary .register pseudo-ops. */ |
3403 | void | |
3404 | sparc_output_scratch_registers (file) | |
fbd039b2 | 3405 | FILE *file ATTRIBUTE_UNUSED; |
1cb36a98 RH |
3406 | { |
3407 | #ifdef HAVE_AS_REGISTER_PSEUDO_OP | |
3408 | int i; | |
3409 | ||
3410 | if (TARGET_ARCH32) | |
3411 | return; | |
3412 | ||
3413 | /* Check if %g[2367] were used without | |
3414 | .register being printed for them already. */ | |
3415 | for (i = 2; i < 8; i++) | |
3416 | { | |
3417 | if (regs_ever_live [i] | |
3418 | && ! sparc_hard_reg_printed [i]) | |
3419 | { | |
3420 | sparc_hard_reg_printed [i] = 1; | |
3421 | fprintf (file, "\t.register\t%%g%d, #scratch\n", i); | |
3422 | } | |
3423 | if (i == 3) i = 5; | |
3424 | } | |
3425 | #endif | |
3426 | } | |
3427 | ||
08c148a8 NB |
3428 | /* This function generates the assembly code for function entry. |
3429 | FILE is a stdio stream to output the code to. | |
3430 | SIZE is an int: how many units of temporary storage to allocate. | |
3431 | Refer to the array `regs_ever_live' to determine which registers | |
3432 | to save; `regs_ever_live[I]' is nonzero if register number I | |
3433 | is ever used in the function. This macro is responsible for | |
3434 | knowing which registers should not be saved even if used. */ | |
3435 | ||
3436 | /* On SPARC, move-double insns between fpu and cpu need an 8-byte block | |
3437 | of memory. If any fpu reg is used in the function, we allocate | |
3438 | such a block here, at the bottom of the frame, just in case it's needed. | |
3439 | ||
3440 | If this function is a leaf procedure, then we may choose not | |
3441 | to do a "save" insn. The decision about whether or not | |
3442 | to do this is made in regclass.c. */ | |
3443 | ||
3444 | static void | |
3445 | sparc_output_function_prologue (file, size) | |
3446 | FILE *file; | |
3447 | HOST_WIDE_INT size; | |
3448 | { | |
3449 | if (TARGET_FLAT) | |
3450 | sparc_flat_function_prologue (file, size); | |
3451 | else | |
3452 | sparc_nonflat_function_prologue (file, size, | |
3453 | current_function_uses_only_leaf_regs); | |
3454 | } | |
3455 | ||
915f619f JW |
3456 | /* Output code for the function prologue. */ |
3457 | ||
08c148a8 NB |
3458 | static void |
3459 | sparc_nonflat_function_prologue (file, size, leaf_function) | |
ab835497 | 3460 | FILE *file; |
08c148a8 | 3461 | HOST_WIDE_INT size; |
915f619f | 3462 | int leaf_function; |
ab835497 | 3463 | { |
1cb36a98 RH |
3464 | sparc_output_scratch_registers (file); |
3465 | ||
915f619f JW |
3466 | /* Need to use actual_fsize, since we are also allocating |
3467 | space for our callee (and our own register save area). */ | |
ab835497 RK |
3468 | actual_fsize = compute_frame_size (size, leaf_function); |
3469 | ||
61a55e8b DE |
3470 | if (leaf_function) |
3471 | { | |
3472 | frame_base_name = "%sp"; | |
3473 | frame_base_offset = actual_fsize + SPARC_STACK_BIAS; | |
3474 | } | |
3475 | else | |
3476 | { | |
3477 | frame_base_name = "%fp"; | |
3478 | frame_base_offset = SPARC_STACK_BIAS; | |
3479 | } | |
3480 | ||
c6aa9ce1 | 3481 | /* This is only for the human reader. */ |
bf62bbf1 | 3482 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
c6aa9ce1 | 3483 | |
915f619f JW |
3484 | if (actual_fsize == 0) |
3485 | /* do nothing. */ ; | |
e6c1be7e | 3486 | else if (! leaf_function) |
ab835497 | 3487 | { |
3592ea0d | 3488 | if (actual_fsize <= 4096) |
e0d80184 | 3489 | fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize); |
3592ea0d | 3490 | else if (actual_fsize <= 8192) |
915f619f | 3491 | { |
e0d80184 DM |
3492 | fprintf (file, "\tsave\t%%sp, -4096, %%sp\n"); |
3493 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); | |
915f619f JW |
3494 | } |
3495 | else | |
3496 | { | |
3592ea0d | 3497 | build_big_number (file, -actual_fsize, "%g1"); |
e0d80184 | 3498 | fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); |
915f619f | 3499 | } |
ab835497 | 3500 | } |
5f4241d5 DE |
3501 | else /* leaf function */ |
3502 | { | |
3592ea0d | 3503 | if (actual_fsize <= 4096) |
e0d80184 | 3504 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize); |
3592ea0d DE |
3505 | else if (actual_fsize <= 8192) |
3506 | { | |
e0d80184 DM |
3507 | fprintf (file, "\tadd\t%%sp, -4096, %%sp\n"); |
3508 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); | |
3592ea0d | 3509 | } |
915f619f | 3510 | else |
3592ea0d DE |
3511 | { |
3512 | build_big_number (file, -actual_fsize, "%g1"); | |
e0d80184 | 3513 | fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n"); |
3592ea0d | 3514 | } |
ab835497 RK |
3515 | } |
3516 | ||
0021b564 | 3517 | if (dwarf2out_do_frame () && actual_fsize) |
c53aa195 | 3518 | { |
96987e96 | 3519 | char *label = dwarf2out_cfi_label (); |
c53aa195 JM |
3520 | |
3521 | /* The canonical frame address refers to the top of the frame. */ | |
3522 | dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM | |
3523 | : FRAME_POINTER_REGNUM), | |
3524 | frame_base_offset); | |
3525 | ||
3526 | if (! leaf_function) | |
3527 | { | |
3528 | /* Note the register window save. This tells the unwinder that | |
3529 | it needs to restore the window registers from the previous | |
3530 | frame's window save area at 0(cfa). */ | |
3531 | dwarf2out_window_save (label); | |
3532 | ||
3533 | /* The return address (-8) is now in %i7. */ | |
3534 | dwarf2out_return_reg (label, 31); | |
3535 | } | |
3536 | } | |
c53aa195 | 3537 | |
ab835497 RK |
3538 | /* If doing anything with PIC, do it now. */ |
3539 | if (! flag_pic) | |
bf62bbf1 | 3540 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
ab835497 | 3541 | |
61a55e8b DE |
3542 | /* Call saved registers are saved just above the outgoing argument area. */ |
3543 | if (num_gfregs) | |
ab835497 | 3544 | { |
c53aa195 | 3545 | int offset, real_offset, n_regs; |
3bb5de61 | 3546 | const char *base; |
ab835497 | 3547 | |
84e884e9 JM |
3548 | real_offset = -apparent_fsize; |
3549 | offset = -apparent_fsize + frame_base_offset; | |
61a55e8b DE |
3550 | if (offset < -4096 || offset + num_gfregs * 4 > 4096) |
3551 | { | |
3552 | /* ??? This might be optimized a little as %g1 might already have a | |
3553 | value close enough that a single add insn will do. */ | |
3554 | /* ??? Although, all of this is probably only a temporary fix | |
3555 | because if %g1 can hold a function result, then | |
3556 | output_function_epilogue will lose (the result will get | |
3557 | clobbered). */ | |
3558 | build_big_number (file, offset, "%g1"); | |
e0d80184 | 3559 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); |
61a55e8b DE |
3560 | base = "%g1"; |
3561 | offset = 0; | |
3562 | } | |
ab835497 | 3563 | else |
61a55e8b DE |
3564 | { |
3565 | base = frame_base_name; | |
3566 | } | |
ab835497 | 3567 | |
db3d4438 | 3568 | n_regs = 0; |
ab835497 | 3569 | if (TARGET_EPILOGUE && ! leaf_function) |
61a55e8b | 3570 | /* ??? Originally saved regs 0-15 here. */ |
c53aa195 | 3571 | n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); |
ab835497 | 3572 | else if (leaf_function) |
61a55e8b | 3573 | /* ??? Originally saved regs 0-31 here. */ |
c53aa195 | 3574 | n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); |
ab835497 | 3575 | if (TARGET_EPILOGUE) |
c53aa195 JM |
3576 | save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs, |
3577 | real_offset); | |
ab835497 RK |
3578 | } |
3579 | ||
ab835497 RK |
3580 | leaf_label = 0; |
3581 | if (leaf_function && actual_fsize != 0) | |
3582 | { | |
3583 | /* warning ("leaf procedure with frame size %d", actual_fsize); */ | |
3584 | if (! TARGET_EPILOGUE) | |
3585 | leaf_label = gen_label_rtx (); | |
3586 | } | |
3587 | } | |
3588 | ||
7d167afd JJ |
3589 | /* Output code to restore any call saved registers. */ |
3590 | ||
3591 | static void | |
3592 | output_restore_regs (file, leaf_function) | |
3593 | FILE *file; | |
3594 | int leaf_function; | |
3595 | { | |
3596 | int offset, n_regs; | |
3597 | const char *base; | |
3598 | ||
3599 | offset = -apparent_fsize + frame_base_offset; | |
3600 | if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) | |
3601 | { | |
3602 | build_big_number (file, offset, "%g1"); | |
3603 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); | |
3604 | base = "%g1"; | |
3605 | offset = 0; | |
3606 | } | |
3607 | else | |
3608 | { | |
3609 | base = frame_base_name; | |
3610 | } | |
3611 | ||
3612 | n_regs = 0; | |
3613 | if (TARGET_EPILOGUE && ! leaf_function) | |
3614 | /* ??? Originally saved regs 0-15 here. */ | |
3615 | n_regs = restore_regs (file, 0, 8, base, offset, 0); | |
3616 | else if (leaf_function) | |
3617 | /* ??? Originally saved regs 0-31 here. */ | |
3618 | n_regs = restore_regs (file, 0, 8, base, offset, 0); | |
3619 | if (TARGET_EPILOGUE) | |
3620 | restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); | |
3621 | } | |
3622 | ||
08c148a8 NB |
3623 | /* This function generates the assembly code for function exit, |
3624 | on machines that need it. | |
3625 | ||
3626 | The function epilogue should not depend on the current stack pointer! | |
3627 | It should use the frame pointer only. This is mandatory because | |
3628 | of alloca; we also take advantage of it to omit stack adjustments | |
3629 | before returning. */ | |
3630 | ||
3631 | static void | |
3632 | sparc_output_function_epilogue (file, size) | |
3633 | FILE *file; | |
3634 | HOST_WIDE_INT size; | |
3635 | { | |
3636 | if (TARGET_FLAT) | |
3637 | sparc_flat_function_epilogue (file, size); | |
3638 | else | |
3639 | sparc_nonflat_function_epilogue (file, size, | |
3640 | current_function_uses_only_leaf_regs); | |
3641 | } | |
3642 | ||
915f619f JW |
3643 | /* Output code for the function epilogue. */ |
3644 | ||
08c148a8 NB |
3645 | static void |
3646 | sparc_nonflat_function_epilogue (file, size, leaf_function) | |
ab835497 | 3647 | FILE *file; |
08c148a8 | 3648 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
ef8200df | 3649 | int leaf_function; |
ab835497 | 3650 | { |
3bb5de61 | 3651 | const char *ret; |
ab835497 RK |
3652 | |
3653 | if (leaf_label) | |
3654 | { | |
ab835497 RK |
3655 | emit_label_after (leaf_label, get_last_insn ()); |
3656 | final_scan_insn (get_last_insn (), file, 0, 0, 1); | |
3657 | } | |
3658 | ||
b69649e4 RK |
3659 | #ifdef FUNCTION_BLOCK_PROFILER_EXIT |
3660 | else if (profile_block_flag == 2) | |
3661 | { | |
3662 | FUNCTION_BLOCK_PROFILER_EXIT(file); | |
3663 | } | |
3664 | #endif | |
3665 | ||
bfd6bc60 | 3666 | else if (current_function_epilogue_delay_list == 0) |
e48addee | 3667 | { |
e0d80184 DM |
3668 | /* If code does not drop into the epilogue, we need |
3669 | do nothing except output pending case vectors. */ | |
bfd6bc60 JC |
3670 | rtx insn = get_last_insn (); |
3671 | if (GET_CODE (insn) == NOTE) | |
3672 | insn = prev_nonnote_insn (insn); | |
3673 | if (insn && GET_CODE (insn) == BARRIER) | |
e0d80184 | 3674 | goto output_vectors; |
bfd6bc60 JC |
3675 | } |
3676 | ||
61a55e8b | 3677 | if (num_gfregs) |
7d167afd | 3678 | output_restore_regs (file, leaf_function); |
ab835497 RK |
3679 | |
3680 | /* Work out how to skip the caller's unimp instruction if required. */ | |
3681 | if (leaf_function) | |
e0d80184 | 3682 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl"); |
ab835497 | 3683 | else |
e0d80184 | 3684 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret"); |
ab835497 | 3685 | |
ef8200df | 3686 | if (TARGET_EPILOGUE || leaf_label) |
ab835497 | 3687 | { |
ef8200df JW |
3688 | int old_target_epilogue = TARGET_EPILOGUE; |
3689 | target_flags &= ~old_target_epilogue; | |
ab835497 | 3690 | |
ef8200df JW |
3691 | if (! leaf_function) |
3692 | { | |
1150a841 RH |
3693 | if (current_function_calls_eh_return) |
3694 | { | |
3695 | if (current_function_epilogue_delay_list) | |
3696 | abort (); | |
3697 | if (SKIP_CALLERS_UNIMP_P) | |
3698 | abort (); | |
3699 | ||
3700 | fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file); | |
3701 | } | |
ef8200df | 3702 | /* If we wound up with things in our delay slot, flush them here. */ |
1150a841 | 3703 | else if (current_function_epilogue_delay_list) |
ab835497 | 3704 | { |
e48addee JJ |
3705 | rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0)); |
3706 | ||
3707 | if (TARGET_V9 && ! epilogue_renumber (&delay, 1)) | |
3708 | { | |
3709 | epilogue_renumber (&delay, 0); | |
3710 | fputs (SKIP_CALLERS_UNIMP_P | |
3711 | ? "\treturn\t%i7+12\n" | |
3712 | : "\treturn\t%i7+8\n", file); | |
3713 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), file, 1, 0, 0); | |
3714 | } | |
3715 | else | |
3716 | { | |
3717 | rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode), | |
3718 | get_last_insn ()); | |
3719 | rtx src; | |
3720 | ||
3721 | if (GET_CODE (delay) != SET) | |
3722 | abort(); | |
3723 | ||
3724 | src = SET_SRC (delay); | |
3725 | if (GET_CODE (src) == ASHIFT) | |
3726 | { | |
3727 | if (XEXP (src, 1) != const1_rtx) | |
3728 | abort(); | |
3729 | SET_SRC (delay) = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0), | |
3730 | XEXP (src, 0)); | |
3731 | } | |
3732 | ||
3733 | PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, | |
3734 | gen_rtvec (2, delay, PATTERN (insn))); | |
3735 | final_scan_insn (insn, file, 1, 0, 1); | |
3736 | } | |
ab835497 | 3737 | } |
284d86e9 | 3738 | else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P) |
e0d80184 | 3739 | fputs ("\treturn\t%i7+8\n\tnop\n", file); |
ab835497 | 3740 | else |
ef8200df JW |
3741 | fprintf (file, "\t%s\n\trestore\n", ret); |
3742 | } | |
1150a841 RH |
3743 | else if (current_function_calls_eh_return) |
3744 | abort (); | |
915f619f JW |
3745 | /* All of the following cases are for leaf functions. */ |
3746 | else if (current_function_epilogue_delay_list) | |
ef8200df | 3747 | { |
915f619f JW |
3748 | /* eligible_for_epilogue_delay_slot ensures that if this is a |
3749 | leaf function, then we will only have insn in the delay slot | |
3750 | if the frame size is zero, thus no adjust for the stack is | |
3751 | needed here. */ | |
3752 | if (actual_fsize != 0) | |
ef8200df | 3753 | abort (); |
915f619f JW |
3754 | fprintf (file, "\t%s\n", ret); |
3755 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
3756 | file, 1, 0, 1); | |
ab835497 | 3757 | } |
9bb7ffda JW |
3758 | /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to |
3759 | avoid generating confusing assembly language output. */ | |
3760 | else if (actual_fsize == 0) | |
3761 | fprintf (file, "\t%s\n\tnop\n", ret); | |
915f619f | 3762 | else if (actual_fsize <= 4096) |
e0d80184 | 3763 | fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize); |
915f619f | 3764 | else if (actual_fsize <= 8192) |
e0d80184 | 3765 | fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n", |
915f619f JW |
3766 | ret, actual_fsize - 4096); |
3767 | else if ((actual_fsize & 0x3ff) == 0) | |
e0d80184 | 3768 | fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", |
915f619f JW |
3769 | actual_fsize, ret); |
3770 | else | |
e0d80184 | 3771 | fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", |
915f619f | 3772 | actual_fsize, actual_fsize, ret); |
ef8200df | 3773 | target_flags |= old_target_epilogue; |
ab835497 | 3774 | } |
e0d80184 DM |
3775 | |
3776 | output_vectors: | |
3777 | sparc_output_deferred_case_vectors (); | |
ab835497 | 3778 | } |
7d167afd JJ |
3779 | |
3780 | /* Output a sibling call. */ | |
3781 | ||
3782 | const char * | |
3783 | output_sibcall (insn, call_operand) | |
3784 | rtx insn, call_operand; | |
3785 | { | |
3786 | int leaf_regs = current_function_uses_only_leaf_regs; | |
3787 | rtx operands[3]; | |
3788 | int delay_slot = dbr_sequence_length () > 0; | |
3789 | ||
3790 | if (num_gfregs) | |
3791 | { | |
3792 | /* Call to restore global regs might clobber | |
3793 | the delay slot. Instead of checking for this | |
3794 | output the delay slot now. */ | |
3795 | if (delay_slot) | |
3796 | { | |
3797 | rtx delay = NEXT_INSN (insn); | |
3798 | ||
3799 | if (! delay) | |
3800 | abort (); | |
3801 | ||
3802 | final_scan_insn (delay, asm_out_file, 1, 0, 1); | |
3803 | PATTERN (delay) = gen_blockage (); | |
3804 | INSN_CODE (delay) = -1; | |
3805 | delay_slot = 0; | |
3806 | } | |
3807 | output_restore_regs (asm_out_file, leaf_regs); | |
3808 | } | |
3809 | ||
3810 | operands[0] = call_operand; | |
3811 | ||
3812 | if (leaf_regs) | |
3813 | { | |
e95b1e6a JJ |
3814 | #ifdef HAVE_AS_RELAX_OPTION |
3815 | /* If as and ld are relaxing tail call insns into branch always, | |
3816 | use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can | |
3817 | be optimized. With sethi/jmpl as nor ld has no easy way how to | |
3818 | find out if somebody does not branch between the sethi and jmpl. */ | |
3819 | int spare_slot = 0; | |
3820 | #else | |
2be5e524 | 3821 | int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic); |
e95b1e6a | 3822 | #endif |
7d167afd JJ |
3823 | int size = 0; |
3824 | ||
3825 | if ((actual_fsize || ! spare_slot) && delay_slot) | |
3826 | { | |
3827 | rtx delay = NEXT_INSN (insn); | |
3828 | ||
3829 | if (! delay) | |
3830 | abort (); | |
3831 | ||
3832 | final_scan_insn (delay, asm_out_file, 1, 0, 1); | |
3833 | PATTERN (delay) = gen_blockage (); | |
3834 | INSN_CODE (delay) = -1; | |
3835 | delay_slot = 0; | |
3836 | } | |
3837 | if (actual_fsize) | |
3838 | { | |
3839 | if (actual_fsize <= 4096) | |
3840 | size = actual_fsize; | |
3841 | else if (actual_fsize <= 8192) | |
3842 | { | |
3843 | fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file); | |
3844 | size = actual_fsize - 4096; | |
3845 | } | |
3846 | else if ((actual_fsize & 0x3ff) == 0) | |
3847 | fprintf (asm_out_file, | |
3848 | "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n", | |
3849 | actual_fsize); | |
3850 | else | |
3851 | { | |
3852 | fprintf (asm_out_file, | |
3853 | "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n", | |
3854 | actual_fsize, actual_fsize); | |
3855 | fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file); | |
3856 | } | |
3857 | } | |
3858 | if (spare_slot) | |
3859 | { | |
3860 | output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands); | |
3861 | output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands); | |
3862 | if (size) | |
3863 | fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size); | |
3864 | else if (! delay_slot) | |
3865 | fputs ("\t nop\n", asm_out_file); | |
3866 | } | |
3867 | else | |
3868 | { | |
3869 | if (size) | |
3870 | fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size); | |
e95b1e6a JJ |
3871 | /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize |
3872 | it into branch if possible. */ | |
3873 | output_asm_insn ("or\t%%o7, %%g0, %%g1", operands); | |
7d167afd | 3874 | output_asm_insn ("call\t%a0, 0", operands); |
e95b1e6a | 3875 | output_asm_insn (" or\t%%g1, %%g0, %%o7", operands); |
7d167afd JJ |
3876 | } |
3877 | return ""; | |
3878 | } | |
3879 | ||
3880 | output_asm_insn ("call\t%a0, 0", operands); | |
3881 | if (delay_slot) | |
3882 | { | |
3883 | rtx delay = NEXT_INSN (insn), pat; | |
3884 | ||
3885 | if (! delay) | |
3886 | abort (); | |
3887 | ||
3888 | pat = PATTERN (delay); | |
3889 | if (GET_CODE (pat) != SET) | |
3890 | abort (); | |
3891 | ||
3892 | operands[0] = SET_DEST (pat); | |
3893 | pat = SET_SRC (pat); | |
3894 | switch (GET_CODE (pat)) | |
3895 | { | |
3896 | case PLUS: | |
3897 | operands[1] = XEXP (pat, 0); | |
3898 | operands[2] = XEXP (pat, 1); | |
3899 | output_asm_insn (" restore %r1, %2, %Y0", operands); | |
3900 | break; | |
3901 | case LO_SUM: | |
3902 | operands[1] = XEXP (pat, 0); | |
3903 | operands[2] = XEXP (pat, 1); | |
3904 | output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); | |
3905 | break; | |
3906 | case ASHIFT: | |
3907 | operands[1] = XEXP (pat, 0); | |
3908 | output_asm_insn (" restore %r1, %r1, %Y0", operands); | |
3909 | break; | |
3910 | default: | |
3911 | operands[1] = pat; | |
3912 | output_asm_insn (" restore %%g0, %1, %Y0", operands); | |
3913 | break; | |
3914 | } | |
3915 | PATTERN (delay) = gen_blockage (); | |
3916 | INSN_CODE (delay) = -1; | |
3917 | } | |
3918 | else | |
3919 | fputs ("\t restore\n", asm_out_file); | |
3920 | return ""; | |
3921 | } | |
4fb4e4b8 DE |
3922 | \f |
3923 | /* Functions for handling argument passing. | |
3924 | ||
3925 | For v8 the first six args are normally in registers and the rest are | |
3926 | pushed. Any arg that starts within the first 6 words is at least | |
3927 | partially passed in a register unless its data type forbids. | |
3928 | ||
3929 | For v9, the argument registers are laid out as an array of 16 elements | |
3930 | and arguments are added sequentially. The first 6 int args and up to the | |
3931 | first 16 fp args (depending on size) are passed in regs. | |
3932 | ||
3933 | Slot Stack Integral Float Float in structure Double Long Double | |
3934 | ---- ----- -------- ----- ------------------ ------ ----------- | |
3935 | 15 [SP+248] %f31 %f30,%f31 %d30 | |
3936 | 14 [SP+240] %f29 %f28,%f29 %d28 %q28 | |
3937 | 13 [SP+232] %f27 %f26,%f27 %d26 | |
3938 | 12 [SP+224] %f25 %f24,%f25 %d24 %q24 | |
3939 | 11 [SP+216] %f23 %f22,%f23 %d22 | |
3940 | 10 [SP+208] %f21 %f20,%f21 %d20 %q20 | |
3941 | 9 [SP+200] %f19 %f18,%f19 %d18 | |
3942 | 8 [SP+192] %f17 %f16,%f17 %d16 %q16 | |
3943 | 7 [SP+184] %f15 %f14,%f15 %d14 | |
3944 | 6 [SP+176] %f13 %f12,%f13 %d12 %q12 | |
3945 | 5 [SP+168] %o5 %f11 %f10,%f11 %d10 | |
3946 | 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 | |
3947 | 3 [SP+152] %o3 %f7 %f6,%f7 %d6 | |
3948 | 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 | |
3949 | 1 [SP+136] %o1 %f3 %f2,%f3 %d2 | |
3950 | 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 | |
3951 | ||
3952 | Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. | |
3953 | ||
3954 | Integral arguments are always passed as 64 bit quantities appropriately | |
3955 | extended. | |
3956 | ||
3957 | Passing of floating point values is handled as follows. | |
3958 | If a prototype is in scope: | |
3959 | If the value is in a named argument (i.e. not a stdarg function or a | |
3960 | value not part of the `...') then the value is passed in the appropriate | |
3961 | fp reg. | |
3962 | If the value is part of the `...' and is passed in one of the first 6 | |
3963 | slots then the value is passed in the appropriate int reg. | |
3964 | If the value is part of the `...' and is not passed in one of the first 6 | |
3965 | slots then the value is passed in memory. | |
3966 | If a prototype is not in scope: | |
3967 | If the value is one of the first 6 arguments the value is passed in the | |
3968 | appropriate integer reg and the appropriate fp reg. | |
3969 | If the value is not one of the first 6 arguments the value is passed in | |
3970 | the appropriate fp reg and in memory. | |
3971 | */ | |
3972 | ||
3973 | /* Maximum number of int regs for args. */ | |
3974 | #define SPARC_INT_ARG_MAX 6 | |
3975 | /* Maximum number of fp regs for args. */ | |
3976 | #define SPARC_FP_ARG_MAX 16 | |
3977 | ||
3978 | #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
3979 | ||
3980 | /* Handle the INIT_CUMULATIVE_ARGS macro. | |
3981 | Initialize a variable CUM of type CUMULATIVE_ARGS | |
3982 | for a call to a function whose data type is FNTYPE. | |
3983 | For a library call, FNTYPE is 0. */ | |
3ea1fdd3 | 3984 | |
4fb4e4b8 DE |
3985 | void |
3986 | init_cumulative_args (cum, fntype, libname, indirect) | |
3987 | CUMULATIVE_ARGS *cum; | |
db3d4438 | 3988 | tree fntype; |
88430453 | 3989 | rtx libname ATTRIBUTE_UNUSED; |
db3d4438 | 3990 | int indirect ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
3991 | { |
3992 | cum->words = 0; | |
3993 | cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); | |
3994 | cum->libcall_p = fntype == 0; | |
3995 | } | |
61a55e8b | 3996 | |
4fb4e4b8 DE |
3997 | /* Compute the slot number to pass an argument in. |
3998 | Returns the slot number or -1 if passing on the stack. | |
3999 | ||
4000 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4001 | the preceding args and about the function being called. | |
4002 | MODE is the argument's machine mode. | |
4003 | TYPE is the data type of the argument (as a tree). | |
4004 | This is null for libcalls where that information may | |
4005 | not be available. | |
4006 | NAMED is nonzero if this argument is a named parameter | |
4007 | (otherwise it is an extra parameter matching an ellipsis). | |
4008 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. | |
4009 | *PREGNO records the register number to use if scalar type. | |
4010 | *PPADDING records the amount of padding needed in words. */ | |
4011 | ||
4012 | static int | |
4013 | function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding) | |
4014 | const CUMULATIVE_ARGS *cum; | |
4015 | enum machine_mode mode; | |
4016 | tree type; | |
4017 | int named; | |
4018 | int incoming_p; | |
4019 | int *pregno; | |
4020 | int *ppadding; | |
4021 | { | |
4022 | int regbase = (incoming_p | |
4023 | ? SPARC_INCOMING_INT_ARG_FIRST | |
4024 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
4025 | int slotno = cum->words; | |
4026 | int regno; | |
4027 | ||
4028 | *ppadding = 0; | |
4029 | ||
4030 | if (type != 0 && TREE_ADDRESSABLE (type)) | |
4031 | return -1; | |
4032 | if (TARGET_ARCH32 | |
4033 | && type != 0 && mode == BLKmode | |
4034 | && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) | |
4035 | return -1; | |
4036 | ||
4037 | switch (mode) | |
4038 | { | |
4039 | case VOIDmode : | |
4040 | /* MODE is VOIDmode when generating the actual call. | |
4041 | See emit_call_1. */ | |
4042 | return -1; | |
4043 | ||
4044 | case QImode : case CQImode : | |
4045 | case HImode : case CHImode : | |
4046 | case SImode : case CSImode : | |
4047 | case DImode : case CDImode : | |
380f6ad3 | 4048 | case TImode : case CTImode : |
4fb4e4b8 DE |
4049 | if (slotno >= SPARC_INT_ARG_MAX) |
4050 | return -1; | |
4051 | regno = regbase + slotno; | |
4052 | break; | |
4053 | ||
4054 | case SFmode : case SCmode : | |
4055 | case DFmode : case DCmode : | |
4056 | case TFmode : case TCmode : | |
4057 | if (TARGET_ARCH32) | |
4058 | { | |
4059 | if (slotno >= SPARC_INT_ARG_MAX) | |
4060 | return -1; | |
4061 | regno = regbase + slotno; | |
4062 | } | |
4063 | else | |
4064 | { | |
4065 | if ((mode == TFmode || mode == TCmode) | |
4066 | && (slotno & 1) != 0) | |
4067 | slotno++, *ppadding = 1; | |
4068 | if (TARGET_FPU && named) | |
4069 | { | |
4070 | if (slotno >= SPARC_FP_ARG_MAX) | |
82d6b402 | 4071 | return -1; |
4fb4e4b8 DE |
4072 | regno = SPARC_FP_ARG_FIRST + slotno * 2; |
4073 | if (mode == SFmode) | |
4074 | regno++; | |
4075 | } | |
4076 | else | |
4077 | { | |
4078 | if (slotno >= SPARC_INT_ARG_MAX) | |
4079 | return -1; | |
4080 | regno = regbase + slotno; | |
4081 | } | |
4082 | } | |
4083 | break; | |
4084 | ||
4085 | case BLKmode : | |
4086 | /* For sparc64, objects requiring 16 byte alignment get it. */ | |
4087 | if (TARGET_ARCH64) | |
4088 | { | |
4089 | if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0) | |
4090 | slotno++, *ppadding = 1; | |
4091 | } | |
4092 | ||
4093 | if (TARGET_ARCH32 | |
5e9defae | 4094 | || (type && TREE_CODE (type) == UNION_TYPE)) |
4fb4e4b8 DE |
4095 | { |
4096 | if (slotno >= SPARC_INT_ARG_MAX) | |
4097 | return -1; | |
4098 | regno = regbase + slotno; | |
4099 | } | |
4100 | else | |
4101 | { | |
4102 | tree field; | |
4103 | int intregs_p = 0, fpregs_p = 0; | |
4104 | /* The ABI obviously doesn't specify how packed | |
4105 | structures are passed. These are defined to be passed | |
4106 | in int regs if possible, otherwise memory. */ | |
4107 | int packed_p = 0; | |
4108 | ||
4109 | /* First see what kinds of registers we need. */ | |
4110 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4111 | { | |
4112 | if (TREE_CODE (field) == FIELD_DECL) | |
4113 | { | |
4114 | if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
4115 | && TARGET_FPU) | |
4116 | fpregs_p = 1; | |
4117 | else | |
4118 | intregs_p = 1; | |
4119 | if (DECL_PACKED (field)) | |
4120 | packed_p = 1; | |
4121 | } | |
4122 | } | |
4123 | if (packed_p || !named) | |
4124 | fpregs_p = 0, intregs_p = 1; | |
4125 | ||
4126 | /* If all arg slots are filled, then must pass on stack. */ | |
4127 | if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) | |
4128 | return -1; | |
4129 | /* If there are only int args and all int arg slots are filled, | |
4130 | then must pass on stack. */ | |
4131 | if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) | |
4132 | return -1; | |
4133 | /* Note that even if all int arg slots are filled, fp members may | |
4134 | still be passed in regs if such regs are available. | |
4135 | *PREGNO isn't set because there may be more than one, it's up | |
4136 | to the caller to compute them. */ | |
4137 | return slotno; | |
4138 | } | |
4139 | break; | |
4140 | ||
4141 | default : | |
4142 | abort (); | |
4143 | } | |
4144 | ||
4145 | *pregno = regno; | |
4146 | return slotno; | |
4147 | } | |
4148 | ||
82d6b402 RH |
4149 | /* Handle recursive register counting for structure field layout. */ |
4150 | ||
4151 | struct function_arg_record_value_parms | |
4152 | { | |
4153 | rtx ret; | |
4154 | int slotno, named, regbase; | |
75131237 RK |
4155 | unsigned int nregs; |
4156 | int intoffset; | |
82d6b402 RH |
4157 | }; |
4158 | ||
2a01c939 | 4159 | static void function_arg_record_value_3 |
75131237 | 4160 | PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *)); |
2a01c939 | 4161 | static void function_arg_record_value_2 |
75131237 RK |
4162 | PARAMS ((tree, HOST_WIDE_INT, |
4163 | struct function_arg_record_value_parms *)); | |
b1474bb7 | 4164 | static void function_arg_record_value_1 |
75131237 RK |
4165 | PARAMS ((tree, HOST_WIDE_INT, |
4166 | struct function_arg_record_value_parms *)); | |
2a01c939 | 4167 | static rtx function_arg_record_value |
f6da8bc3 | 4168 | PARAMS ((tree, enum machine_mode, int, int, int)); |
2a01c939 | 4169 | |
0020b823 RH |
4170 | /* A subroutine of function_arg_record_value. Traverse the structure |
4171 | recusively and determine how many registers will be required. */ | |
4172 | ||
82d6b402 RH |
4173 | static void |
4174 | function_arg_record_value_1 (type, startbitpos, parms) | |
4175 | tree type; | |
75131237 | 4176 | HOST_WIDE_INT startbitpos; |
82d6b402 RH |
4177 | struct function_arg_record_value_parms *parms; |
4178 | { | |
4179 | tree field; | |
4180 | ||
4181 | /* The ABI obviously doesn't specify how packed structures are | |
4182 | passed. These are defined to be passed in int regs if possible, | |
4183 | otherwise memory. */ | |
4184 | int packed_p = 0; | |
4185 | ||
4186 | /* We need to compute how many registers are needed so we can | |
4187 | allocate the PARALLEL but before we can do that we need to know | |
4188 | whether there are any packed fields. If there are, int regs are | |
4189 | used regardless of whether there are fp values present. */ | |
4190 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4191 | { | |
4192 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
4193 | { | |
4194 | packed_p = 1; | |
4195 | break; | |
4196 | } | |
4197 | } | |
4198 | ||
4199 | /* Compute how many registers we need. */ | |
4200 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4201 | { | |
4202 | if (TREE_CODE (field) == FIELD_DECL) | |
4203 | { | |
75131237 RK |
4204 | HOST_WIDE_INT bitpos = startbitpos; |
4205 | ||
4206 | if (DECL_SIZE (field) != 0 | |
4207 | && host_integerp (bit_position (field), 1)) | |
4208 | bitpos += int_bit_position (field); | |
4209 | ||
82d6b402 RH |
4210 | /* ??? FIXME: else assume zero offset. */ |
4211 | ||
4212 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
75131237 | 4213 | function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms); |
82d6b402 RH |
4214 | else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE |
4215 | && TARGET_FPU | |
4216 | && ! packed_p | |
4217 | && parms->named) | |
4218 | { | |
4219 | if (parms->intoffset != -1) | |
4220 | { | |
4221 | int intslots, this_slotno; | |
4222 | ||
4223 | intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1) | |
4224 | / BITS_PER_WORD; | |
4225 | this_slotno = parms->slotno + parms->intoffset | |
4226 | / BITS_PER_WORD; | |
4227 | ||
4228 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
4229 | intslots = MAX (intslots, 0); | |
4230 | parms->nregs += intslots; | |
4231 | parms->intoffset = -1; | |
4232 | } | |
4233 | ||
4234 | /* There's no need to check this_slotno < SPARC_FP_ARG MAX. | |
4235 | If it wasn't true we wouldn't be here. */ | |
4236 | parms->nregs += 1; | |
4237 | } | |
4238 | else | |
4239 | { | |
4240 | if (parms->intoffset == -1) | |
4241 | parms->intoffset = bitpos; | |
4242 | } | |
4243 | } | |
4244 | } | |
4245 | } | |
4246 | ||
0020b823 RH |
4247 | /* A subroutine of function_arg_record_value. Assign the bits of the |
4248 | structure between parms->intoffset and bitpos to integer registers. */ | |
82d6b402 RH |
4249 | |
4250 | static void | |
4251 | function_arg_record_value_3 (bitpos, parms) | |
75131237 | 4252 | HOST_WIDE_INT bitpos; |
82d6b402 RH |
4253 | struct function_arg_record_value_parms *parms; |
4254 | { | |
4255 | enum machine_mode mode; | |
75131237 | 4256 | unsigned int regno; |
0020b823 | 4257 | unsigned int startbit, endbit; |
75131237 | 4258 | int this_slotno, intslots, intoffset; |
82d6b402 RH |
4259 | rtx reg; |
4260 | ||
4261 | if (parms->intoffset == -1) | |
4262 | return; | |
75131237 | 4263 | |
82d6b402 RH |
4264 | intoffset = parms->intoffset; |
4265 | parms->intoffset = -1; | |
4266 | ||
0020b823 RH |
4267 | startbit = intoffset & -BITS_PER_WORD; |
4268 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4269 | intslots = (endbit - startbit) / BITS_PER_WORD; | |
82d6b402 RH |
4270 | this_slotno = parms->slotno + intoffset / BITS_PER_WORD; |
4271 | ||
4272 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
4273 | if (intslots <= 0) | |
4274 | return; | |
4275 | ||
4276 | /* If this is the trailing part of a word, only load that much into | |
4277 | the register. Otherwise load the whole register. Note that in | |
4278 | the latter case we may pick up unwanted bits. It's not a problem | |
4279 | at the moment but may wish to revisit. */ | |
4280 | ||
4281 | if (intoffset % BITS_PER_WORD != 0) | |
75131237 RK |
4282 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, |
4283 | MODE_INT, 0); | |
82d6b402 RH |
4284 | else |
4285 | mode = word_mode; | |
4286 | ||
4287 | intoffset /= BITS_PER_UNIT; | |
4288 | do | |
4289 | { | |
4290 | regno = parms->regbase + this_slotno; | |
254110c2 | 4291 | reg = gen_rtx_REG (mode, regno); |
82d6b402 | 4292 | XVECEXP (parms->ret, 0, parms->nregs) |
254110c2 | 4293 | = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); |
82d6b402 RH |
4294 | |
4295 | this_slotno += 1; | |
4296 | intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; | |
4297 | parms->nregs += 1; | |
4298 | intslots -= 1; | |
4299 | } | |
4300 | while (intslots > 0); | |
4301 | } | |
4302 | ||
0020b823 RH |
4303 | /* A subroutine of function_arg_record_value. Traverse the structure |
4304 | recursively and assign bits to floating point registers. Track which | |
4305 | bits in between need integer registers; invoke function_arg_record_value_3 | |
4306 | to make that happen. */ | |
4307 | ||
82d6b402 RH |
4308 | static void |
4309 | function_arg_record_value_2 (type, startbitpos, parms) | |
4310 | tree type; | |
75131237 | 4311 | HOST_WIDE_INT startbitpos; |
82d6b402 RH |
4312 | struct function_arg_record_value_parms *parms; |
4313 | { | |
4314 | tree field; | |
4315 | int packed_p = 0; | |
4316 | ||
4317 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4318 | { | |
4319 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
4320 | { | |
4321 | packed_p = 1; | |
4322 | break; | |
4323 | } | |
4324 | } | |
4325 | ||
4326 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4327 | { | |
4328 | if (TREE_CODE (field) == FIELD_DECL) | |
4329 | { | |
75131237 RK |
4330 | HOST_WIDE_INT bitpos = startbitpos; |
4331 | ||
4332 | if (DECL_SIZE (field) != 0 | |
4333 | && host_integerp (bit_position (field), 1)) | |
4334 | bitpos += int_bit_position (field); | |
4335 | ||
82d6b402 RH |
4336 | /* ??? FIXME: else assume zero offset. */ |
4337 | ||
4338 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
75131237 | 4339 | function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms); |
82d6b402 RH |
4340 | else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE |
4341 | && TARGET_FPU | |
4342 | && ! packed_p | |
4343 | && parms->named) | |
4344 | { | |
4345 | int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; | |
4346 | rtx reg; | |
4347 | ||
4348 | function_arg_record_value_3 (bitpos, parms); | |
4349 | ||
254110c2 | 4350 | reg = gen_rtx_REG (DECL_MODE (field), |
82d6b402 RH |
4351 | (SPARC_FP_ARG_FIRST + this_slotno * 2 |
4352 | + (DECL_MODE (field) == SFmode | |
4353 | && (bitpos & 32) != 0))); | |
4354 | XVECEXP (parms->ret, 0, parms->nregs) | |
254110c2 | 4355 | = gen_rtx_EXPR_LIST (VOIDmode, reg, |
82d6b402 RH |
4356 | GEN_INT (bitpos / BITS_PER_UNIT)); |
4357 | parms->nregs += 1; | |
4358 | } | |
4359 | else | |
4360 | { | |
4361 | if (parms->intoffset == -1) | |
4362 | parms->intoffset = bitpos; | |
4363 | } | |
4364 | } | |
4365 | } | |
4366 | } | |
4367 | ||
0020b823 RH |
4368 | /* Used by function_arg and function_value to implement the complex |
4369 | Sparc64 structure calling conventions. */ | |
4370 | ||
82d6b402 | 4371 | static rtx |
1eac9f59 | 4372 | function_arg_record_value (type, mode, slotno, named, regbase) |
82d6b402 | 4373 | tree type; |
1eac9f59 | 4374 | enum machine_mode mode; |
82d6b402 RH |
4375 | int slotno, named, regbase; |
4376 | { | |
4377 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
4378 | struct function_arg_record_value_parms parms; | |
75131237 | 4379 | unsigned int nregs; |
82d6b402 RH |
4380 | |
4381 | parms.ret = NULL_RTX; | |
4382 | parms.slotno = slotno; | |
4383 | parms.named = named; | |
4384 | parms.regbase = regbase; | |
4385 | ||
4386 | /* Compute how many registers we need. */ | |
4387 | parms.nregs = 0; | |
4388 | parms.intoffset = 0; | |
4389 | function_arg_record_value_1 (type, 0, &parms); | |
4390 | ||
4391 | if (parms.intoffset != -1) | |
4392 | { | |
0020b823 | 4393 | unsigned int startbit, endbit; |
82d6b402 RH |
4394 | int intslots, this_slotno; |
4395 | ||
0020b823 RH |
4396 | startbit = parms.intoffset & -BITS_PER_WORD; |
4397 | endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4398 | intslots = (endbit - startbit) / BITS_PER_WORD; | |
82d6b402 RH |
4399 | this_slotno = slotno + parms.intoffset / BITS_PER_WORD; |
4400 | ||
4401 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
4402 | intslots = MAX (intslots, 0); | |
4403 | ||
4404 | parms.nregs += intslots; | |
4405 | } | |
4406 | nregs = parms.nregs; | |
4407 | ||
4408 | /* Allocate the vector and handle some annoying special cases. */ | |
4409 | if (nregs == 0) | |
4410 | { | |
4411 | /* ??? Empty structure has no value? Duh? */ | |
4412 | if (typesize <= 0) | |
4413 | { | |
4414 | /* Though there's nothing really to store, return a word register | |
4415 | anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL | |
4416 | leads to breakage due to the fact that there are zero bytes to | |
4417 | load. */ | |
1eac9f59 | 4418 | return gen_rtx_REG (mode, regbase); |
82d6b402 RH |
4419 | } |
4420 | else | |
4421 | { | |
4422 | /* ??? C++ has structures with no fields, and yet a size. Give up | |
4423 | for now and pass everything back in integer registers. */ | |
4424 | nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4425 | } | |
4426 | if (nregs + slotno > SPARC_INT_ARG_MAX) | |
4427 | nregs = SPARC_INT_ARG_MAX - slotno; | |
4428 | } | |
4429 | if (nregs == 0) | |
9208e4b2 | 4430 | abort (); |
82d6b402 | 4431 | |
1eac9f59 | 4432 | parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs)); |
82d6b402 RH |
4433 | |
4434 | /* Fill in the entries. */ | |
4435 | parms.nregs = 0; | |
4436 | parms.intoffset = 0; | |
4437 | function_arg_record_value_2 (type, 0, &parms); | |
4438 | function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); | |
4439 | ||
4440 | if (parms.nregs != nregs) | |
4441 | abort (); | |
4442 | ||
4443 | return parms.ret; | |
4444 | } | |
4445 | ||
4fb4e4b8 DE |
4446 | /* Handle the FUNCTION_ARG macro. |
4447 | Determine where to put an argument to a function. | |
4448 | Value is zero to push the argument on the stack, | |
4449 | or a hard register in which to store the argument. | |
4450 | ||
4451 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4452 | the preceding args and about the function being called. | |
4453 | MODE is the argument's machine mode. | |
4454 | TYPE is the data type of the argument (as a tree). | |
4455 | This is null for libcalls where that information may | |
4456 | not be available. | |
4457 | NAMED is nonzero if this argument is a named parameter | |
4458 | (otherwise it is an extra parameter matching an ellipsis). | |
4459 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ | |
61a55e8b DE |
4460 | |
4461 | rtx | |
4fb4e4b8 DE |
4462 | function_arg (cum, mode, type, named, incoming_p) |
4463 | const CUMULATIVE_ARGS *cum; | |
4464 | enum machine_mode mode; | |
4465 | tree type; | |
4466 | int named; | |
4467 | int incoming_p; | |
61a55e8b | 4468 | { |
4fb4e4b8 DE |
4469 | int regbase = (incoming_p |
4470 | ? SPARC_INCOMING_INT_ARG_FIRST | |
4471 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
4472 | int slotno, regno, padding; | |
4473 | rtx reg; | |
4474 | ||
4475 | slotno = function_arg_slotno (cum, mode, type, named, incoming_p, | |
4476 | ®no, &padding); | |
4477 | ||
4478 | if (slotno == -1) | |
4479 | return 0; | |
4480 | ||
4481 | if (TARGET_ARCH32) | |
4482 | { | |
254110c2 | 4483 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
4484 | return reg; |
4485 | } | |
4486 | ||
4487 | /* v9 fp args in reg slots beyond the int reg slots get passed in regs | |
4488 | but also have the slot allocated for them. | |
4489 | If no prototype is in scope fp values in register slots get passed | |
4490 | in two places, either fp regs and int regs or fp regs and memory. */ | |
4491 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
4492 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
4493 | && SPARC_FP_REG_P (regno)) | |
4494 | { | |
254110c2 | 4495 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
4496 | if (cum->prototype_p || cum->libcall_p) |
4497 | { | |
4498 | /* "* 2" because fp reg numbers are recorded in 4 byte | |
4499 | quantities. */ | |
82d6b402 | 4500 | #if 0 |
4fb4e4b8 DE |
4501 | /* ??? This will cause the value to be passed in the fp reg and |
4502 | in the stack. When a prototype exists we want to pass the | |
4503 | value in the reg but reserve space on the stack. That's an | |
956d6950 | 4504 | optimization, and is deferred [for a bit]. */ |
4fb4e4b8 | 4505 | if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) |
254110c2 | 4506 | return gen_rtx_PARALLEL (mode, |
4fb4e4b8 | 4507 | gen_rtvec (2, |
254110c2 | 4508 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 | 4509 | NULL_RTX, const0_rtx), |
254110c2 | 4510 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 DE |
4511 | reg, const0_rtx))); |
4512 | else | |
82d6b402 RH |
4513 | #else |
4514 | /* ??? It seems that passing back a register even when past | |
4515 | the area declared by REG_PARM_STACK_SPACE will allocate | |
4516 | space appropriately, and will not copy the data onto the | |
4517 | stack, exactly as we desire. | |
4518 | ||
4519 | This is due to locate_and_pad_parm being called in | |
4520 | expand_call whenever reg_parm_stack_space > 0, which | |
4521 | while benefical to our example here, would seem to be | |
4522 | in error from what had been intended. Ho hum... -- r~ */ | |
4523 | #endif | |
4fb4e4b8 DE |
4524 | return reg; |
4525 | } | |
4526 | else | |
4527 | { | |
82d6b402 RH |
4528 | rtx v0, v1; |
4529 | ||
4fb4e4b8 DE |
4530 | if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) |
4531 | { | |
82d6b402 RH |
4532 | int intreg; |
4533 | ||
4534 | /* On incoming, we don't need to know that the value | |
4535 | is passed in %f0 and %i0, and it confuses other parts | |
4536 | causing needless spillage even on the simplest cases. */ | |
4537 | if (incoming_p) | |
4538 | return reg; | |
4539 | ||
4540 | intreg = (SPARC_OUTGOING_INT_ARG_FIRST | |
4541 | + (regno - SPARC_FP_ARG_FIRST) / 2); | |
4542 | ||
4543 | v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
4544 | v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), | |
4545 | const0_rtx); | |
4546 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4fb4e4b8 DE |
4547 | } |
4548 | else | |
82d6b402 RH |
4549 | { |
4550 | v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
4551 | v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
4552 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4553 | } | |
4fb4e4b8 DE |
4554 | } |
4555 | } | |
4556 | else if (type && TREE_CODE (type) == RECORD_TYPE) | |
4557 | { | |
4558 | /* Structures up to 16 bytes in size are passed in arg slots on the | |
4559 | stack and are promoted to registers where possible. */ | |
4fb4e4b8 DE |
4560 | |
4561 | if (int_size_in_bytes (type) > 16) | |
4562 | abort (); /* shouldn't get here */ | |
4563 | ||
1eac9f59 | 4564 | return function_arg_record_value (type, mode, slotno, named, regbase); |
4fb4e4b8 DE |
4565 | } |
4566 | else if (type && TREE_CODE (type) == UNION_TYPE) | |
4567 | { | |
4568 | enum machine_mode mode; | |
4569 | int bytes = int_size_in_bytes (type); | |
4570 | ||
4571 | if (bytes > 16) | |
4572 | abort (); | |
4573 | ||
4574 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
254110c2 | 4575 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 | 4576 | } |
a7acd911 | 4577 | else |
4fb4e4b8 DE |
4578 | { |
4579 | /* Scalar or complex int. */ | |
254110c2 | 4580 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
4581 | } |
4582 | ||
4583 | return reg; | |
4584 | } | |
a7acd911 | 4585 | |
4fb4e4b8 DE |
4586 | /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro. |
4587 | For an arg passed partly in registers and partly in memory, | |
4588 | this is the number of registers used. | |
4589 | For args passed entirely in registers or entirely in memory, zero. | |
61a55e8b | 4590 | |
4fb4e4b8 DE |
4591 | Any arg that starts in the first 6 regs but won't entirely fit in them |
4592 | needs partial registers on v8. On v9, structures with integer | |
4593 | values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp | |
4594 | values that begin in the last fp reg [where "last fp reg" varies with the | |
4595 | mode] will be split between that reg and memory. */ | |
61a55e8b | 4596 | |
4fb4e4b8 DE |
4597 | int |
4598 | function_arg_partial_nregs (cum, mode, type, named) | |
4599 | const CUMULATIVE_ARGS *cum; | |
4600 | enum machine_mode mode; | |
4601 | tree type; | |
4602 | int named; | |
4603 | { | |
4604 | int slotno, regno, padding; | |
61a55e8b | 4605 | |
4fb4e4b8 DE |
4606 | /* We pass 0 for incoming_p here, it doesn't matter. */ |
4607 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
4608 | ||
4609 | if (slotno == -1) | |
4610 | return 0; | |
4611 | ||
4612 | if (TARGET_ARCH32) | |
bf62bbf1 | 4613 | { |
4fb4e4b8 DE |
4614 | if ((slotno + (mode == BLKmode |
4615 | ? ROUND_ADVANCE (int_size_in_bytes (type)) | |
4616 | : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) | |
4617 | > NPARM_REGS (SImode)) | |
4618 | return NPARM_REGS (SImode) - slotno; | |
4619 | return 0; | |
4620 | } | |
4621 | else | |
4622 | { | |
4623 | if (type && AGGREGATE_TYPE_P (type)) | |
4624 | { | |
4625 | int size = int_size_in_bytes (type); | |
4626 | int align = TYPE_ALIGN (type); | |
bf62bbf1 | 4627 | |
4fb4e4b8 DE |
4628 | if (align == 16) |
4629 | slotno += slotno & 1; | |
4630 | if (size > 8 && size <= 16 | |
4631 | && slotno == SPARC_INT_ARG_MAX - 1) | |
4632 | return 1; | |
4633 | } | |
4634 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT | |
4635 | || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
4636 | && ! TARGET_FPU)) | |
4637 | { | |
4638 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
4639 | { | |
4640 | slotno += slotno & 1; | |
4641 | if (slotno == SPARC_INT_ARG_MAX - 2) | |
4642 | return 1; | |
4643 | } | |
4644 | else | |
4645 | { | |
4646 | if (slotno == SPARC_INT_ARG_MAX - 1) | |
4647 | return 1; | |
4648 | } | |
4649 | } | |
4650 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
4651 | { | |
4652 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
4653 | slotno += slotno & 1; | |
4654 | if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) | |
4655 | > SPARC_FP_ARG_MAX) | |
4656 | return 1; | |
4657 | } | |
4658 | return 0; | |
bf62bbf1 | 4659 | } |
4fb4e4b8 | 4660 | } |
61a55e8b | 4661 | |
4fb4e4b8 DE |
4662 | /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro. |
4663 | !v9: The SPARC ABI stipulates passing struct arguments (of any size) and | |
4664 | quad-precision floats by invisible reference. | |
82d6b402 | 4665 | v9: Aggregates greater than 16 bytes are passed by reference. |
4fb4e4b8 DE |
4666 | For Pascal, also pass arrays by reference. */ |
4667 | ||
4668 | int | |
4669 | function_arg_pass_by_reference (cum, mode, type, named) | |
db3d4438 | 4670 | const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
4671 | enum machine_mode mode; |
4672 | tree type; | |
db3d4438 | 4673 | int named ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
4674 | { |
4675 | if (TARGET_ARCH32) | |
eadceb59 | 4676 | { |
5e9defae | 4677 | return ((type && AGGREGATE_TYPE_P (type)) |
4fb4e4b8 DE |
4678 | || mode == TFmode || mode == TCmode); |
4679 | } | |
4680 | else | |
4681 | { | |
4682 | return ((type && TREE_CODE (type) == ARRAY_TYPE) | |
82d6b402 RH |
4683 | /* Consider complex values as aggregates, so care for TCmode. */ |
4684 | || GET_MODE_SIZE (mode) > 16 | |
4fb4e4b8 DE |
4685 | || (type && AGGREGATE_TYPE_P (type) |
4686 | && int_size_in_bytes (type) > 16)); | |
4687 | } | |
4688 | } | |
4689 | ||
4690 | /* Handle the FUNCTION_ARG_ADVANCE macro. | |
4691 | Update the data in CUM to advance over an argument | |
4692 | of mode MODE and data type TYPE. | |
4693 | TYPE is null for libcalls where that information may not be available. */ | |
4694 | ||
4695 | void | |
4696 | function_arg_advance (cum, mode, type, named) | |
4697 | CUMULATIVE_ARGS *cum; | |
4698 | enum machine_mode mode; | |
4699 | tree type; | |
4700 | int named; | |
4701 | { | |
4702 | int slotno, regno, padding; | |
4703 | ||
4704 | /* We pass 0 for incoming_p here, it doesn't matter. */ | |
4705 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
4706 | ||
4707 | /* If register required leading padding, add it. */ | |
4708 | if (slotno != -1) | |
4709 | cum->words += padding; | |
eadceb59 | 4710 | |
4fb4e4b8 DE |
4711 | if (TARGET_ARCH32) |
4712 | { | |
4713 | cum->words += (mode != BLKmode | |
4714 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
4715 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
4716 | } | |
4717 | else | |
4718 | { | |
4719 | if (type && AGGREGATE_TYPE_P (type)) | |
4720 | { | |
4721 | int size = int_size_in_bytes (type); | |
4722 | ||
4723 | if (size <= 8) | |
4724 | ++cum->words; | |
4725 | else if (size <= 16) | |
4726 | cum->words += 2; | |
4727 | else /* passed by reference */ | |
4728 | ++cum->words; | |
4729 | } | |
4730 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) | |
4731 | { | |
4732 | cum->words += 2; | |
4733 | } | |
4734 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
4735 | { | |
4736 | cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD; | |
4737 | } | |
4738 | else | |
4739 | { | |
4740 | cum->words += (mode != BLKmode | |
4741 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
4742 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
4743 | } | |
eadceb59 | 4744 | } |
4fb4e4b8 | 4745 | } |
eadceb59 | 4746 | |
4fb4e4b8 DE |
4747 | /* Handle the FUNCTION_ARG_PADDING macro. |
4748 | For the 64 bit ABI structs are always stored left shifted in their | |
4749 | argument slot. */ | |
4750 | ||
4751 | enum direction | |
4752 | function_arg_padding (mode, type) | |
4753 | enum machine_mode mode; | |
4754 | tree type; | |
4755 | { | |
c85f7c16 JL |
4756 | if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) |
4757 | return upward; | |
61a55e8b | 4758 | |
4fb4e4b8 DE |
4759 | /* This is the default definition. */ |
4760 | return (! BYTES_BIG_ENDIAN | |
4761 | ? upward | |
4762 | : ((mode == BLKmode | |
4763 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
4764 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
4765 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
4766 | ? downward : upward)); | |
61a55e8b | 4767 | } |
82d6b402 RH |
4768 | |
4769 | /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. | |
4770 | For v9, function return values are subject to the same rules as arguments, | |
4771 | except that up to 32-bytes may be returned in registers. */ | |
4772 | ||
4773 | rtx | |
4774 | function_value (type, mode, incoming_p) | |
4775 | tree type; | |
4776 | enum machine_mode mode; | |
4777 | int incoming_p; | |
4778 | { | |
4779 | int regno; | |
4780 | int regbase = (incoming_p | |
4781 | ? SPARC_OUTGOING_INT_ARG_FIRST | |
4782 | : SPARC_INCOMING_INT_ARG_FIRST); | |
4783 | ||
4784 | if (TARGET_ARCH64 && type) | |
4785 | { | |
4786 | if (TREE_CODE (type) == RECORD_TYPE) | |
4787 | { | |
4788 | /* Structures up to 32 bytes in size are passed in registers, | |
4789 | promoted to fp registers where possible. */ | |
4790 | ||
4791 | if (int_size_in_bytes (type) > 32) | |
4792 | abort (); /* shouldn't get here */ | |
4793 | ||
1eac9f59 | 4794 | return function_arg_record_value (type, mode, 0, 1, regbase); |
82d6b402 | 4795 | } |
8a7199ad | 4796 | else if (AGGREGATE_TYPE_P (type)) |
82d6b402 | 4797 | { |
8a7199ad RK |
4798 | /* All other aggregate types are passed in an integer register |
4799 | in a mode corresponding to the size of the type. */ | |
4800 | HOST_WIDE_INT bytes = int_size_in_bytes (type); | |
82d6b402 RH |
4801 | |
4802 | if (bytes > 32) | |
4803 | abort (); | |
4804 | ||
4805 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
4806 | } | |
4807 | } | |
3c6088d2 JJ |
4808 | |
4809 | if (TARGET_ARCH64 | |
4810 | && GET_MODE_CLASS (mode) == MODE_INT | |
4811 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
8a7199ad | 4812 | && type && ! AGGREGATE_TYPE_P (type)) |
3c6088d2 | 4813 | mode = DImode; |
82d6b402 RH |
4814 | |
4815 | if (incoming_p) | |
4816 | regno = BASE_RETURN_VALUE_REG (mode); | |
4817 | else | |
4818 | regno = BASE_OUTGOING_VALUE_REG (mode); | |
4819 | ||
254110c2 | 4820 | return gen_rtx_REG (mode, regno); |
82d6b402 RH |
4821 | } |
4822 | ||
648d2ffc RH |
4823 | /* Do what is necessary for `va_start'. We look at the current function |
4824 | to determine if stdarg or varargs is used and return the address of | |
4825 | the first unnamed parameter. */ | |
3ea1fdd3 JW |
4826 | |
4827 | rtx | |
648d2ffc | 4828 | sparc_builtin_saveregs () |
3ea1fdd3 | 4829 | { |
4fb4e4b8 | 4830 | int first_reg = current_function_args_info.words; |
3ea1fdd3 JW |
4831 | rtx address; |
4832 | int regno; | |
4833 | ||
4fb4e4b8 | 4834 | for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++) |
254110c2 DM |
4835 | emit_move_insn (gen_rtx_MEM (word_mode, |
4836 | gen_rtx_PLUS (Pmode, | |
3ea1fdd3 JW |
4837 | frame_pointer_rtx, |
4838 | GEN_INT (STACK_POINTER_OFFSET | |
4839 | + UNITS_PER_WORD * regno))), | |
254110c2 | 4840 | gen_rtx_REG (word_mode, |
4fb4e4b8 | 4841 | BASE_INCOMING_ARG_REG (word_mode) + regno)); |
3ea1fdd3 | 4842 | |
254110c2 | 4843 | address = gen_rtx_PLUS (Pmode, |
3ea1fdd3 JW |
4844 | frame_pointer_rtx, |
4845 | GEN_INT (STACK_POINTER_OFFSET | |
4846 | + UNITS_PER_WORD * first_reg)); | |
4847 | ||
7d384cc0 | 4848 | if (current_function_check_memory_usage |
4fb4e4b8 | 4849 | && first_reg < NPARM_REGS (word_mode)) |
eadceb59 RK |
4850 | emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3, |
4851 | address, ptr_mode, | |
4852 | GEN_INT (UNITS_PER_WORD | |
4fb4e4b8 | 4853 | * (NPARM_REGS (word_mode) - first_reg)), |
956d6950 JL |
4854 | TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW), |
4855 | TYPE_MODE (integer_type_node)); | |
eadceb59 | 4856 | |
3ea1fdd3 JW |
4857 | return address; |
4858 | } | |
a8b2c8a1 RH |
4859 | |
4860 | /* Implement `va_start' for varargs and stdarg. */ | |
4861 | ||
4862 | void | |
4863 | sparc_va_start (stdarg_p, valist, nextarg) | |
4864 | int stdarg_p ATTRIBUTE_UNUSED; | |
4865 | tree valist; | |
4866 | rtx nextarg; | |
4867 | { | |
4868 | nextarg = expand_builtin_saveregs (); | |
4869 | std_expand_builtin_va_start (1, valist, nextarg); | |
4870 | } | |
4871 | ||
4872 | /* Implement `va_arg'. */ | |
4873 | ||
4874 | rtx | |
4875 | sparc_va_arg (valist, type) | |
4876 | tree valist, type; | |
4877 | { | |
4878 | HOST_WIDE_INT size, rsize, align; | |
da09e317 | 4879 | tree addr, incr; |
a8b2c8a1 RH |
4880 | rtx addr_rtx; |
4881 | int indirect = 0; | |
4882 | ||
4883 | /* Round up sizeof(type) to a word. */ | |
4884 | size = int_size_in_bytes (type); | |
4885 | rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; | |
4886 | align = 0; | |
4887 | ||
4888 | if (TARGET_ARCH64) | |
4889 | { | |
fbd039b2 | 4890 | if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) |
a8b2c8a1 RH |
4891 | align = 2 * UNITS_PER_WORD; |
4892 | ||
f34e52f7 | 4893 | if (AGGREGATE_TYPE_P (type)) |
a8b2c8a1 | 4894 | { |
f34e52f7 JJ |
4895 | if (size > 16) |
4896 | { | |
4897 | indirect = 1; | |
4898 | size = rsize = UNITS_PER_WORD; | |
4899 | } | |
4900 | else | |
4901 | size = rsize; | |
a8b2c8a1 RH |
4902 | } |
4903 | } | |
4904 | else | |
4905 | { | |
4906 | if (AGGREGATE_TYPE_P (type) | |
4907 | || TYPE_MODE (type) == TFmode | |
4908 | || TYPE_MODE (type) == TCmode) | |
4909 | { | |
4910 | indirect = 1; | |
4911 | size = rsize = UNITS_PER_WORD; | |
4912 | } | |
a8b2c8a1 RH |
4913 | } |
4914 | ||
4915 | incr = valist; | |
4916 | if (align) | |
4917 | { | |
4918 | incr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
4919 | build_int_2 (align - 1, 0))); | |
4920 | incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr, | |
4921 | build_int_2 (-align, -1))); | |
4922 | } | |
4923 | ||
4924 | addr = incr = save_expr (incr); | |
4925 | if (BYTES_BIG_ENDIAN && size < rsize) | |
4926 | { | |
4927 | addr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
4928 | build_int_2 (rsize - size, 0))); | |
4929 | } | |
4930 | incr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
4931 | build_int_2 (rsize, 0))); | |
4932 | ||
4933 | incr = build (MODIFY_EXPR, ptr_type_node, valist, incr); | |
4934 | TREE_SIDE_EFFECTS (incr) = 1; | |
4935 | expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4936 | ||
4937 | addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); | |
4938 | ||
9a0662b4 GK |
4939 | /* If the address isn't aligned properly for the type, |
4940 | we may need to copy to a temporary. | |
4941 | FIXME: This is inefficient. Usually we can do this | |
4942 | in registers. */ | |
4943 | if (align == 0 | |
4944 | && TYPE_ALIGN (type) > BITS_PER_WORD | |
4945 | && !indirect) | |
4946 | { | |
4947 | /* FIXME: We really need to specify that the temporary is live | |
4948 | for the whole function because expand_builtin_va_arg wants | |
4949 | the alias set to be get_varargs_alias_set (), but in this | |
4950 | case the alias set is that for TYPE and if the memory gets | |
4951 | reused it will be reused with alias set TYPE. */ | |
4952 | rtx tmp = assign_temp (type, 0, 1, 0); | |
4953 | rtx dest_addr; | |
4954 | ||
4955 | addr_rtx = force_reg (Pmode, addr_rtx); | |
4956 | addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx); | |
ba4828e0 | 4957 | set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); |
9a0662b4 GK |
4958 | tmp = shallow_copy_rtx (tmp); |
4959 | PUT_MODE (tmp, BLKmode); | |
ba4828e0 | 4960 | set_mem_alias_set (tmp, 0); |
9a0662b4 GK |
4961 | |
4962 | dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize), | |
4963 | BITS_PER_WORD); | |
4964 | if (dest_addr != NULL_RTX) | |
4965 | addr_rtx = dest_addr; | |
4966 | else | |
4967 | addr_rtx = XCEXP (tmp, 0, MEM); | |
4968 | } | |
4969 | ||
a8b2c8a1 RH |
4970 | if (indirect) |
4971 | { | |
4972 | addr_rtx = force_reg (Pmode, addr_rtx); | |
4973 | addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 4974 | set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); |
a8b2c8a1 RH |
4975 | } |
4976 | ||
4977 | return addr_rtx; | |
4978 | } | |
ab835497 RK |
4979 | \f |
4980 | /* Return the string to output a conditional branch to LABEL, which is | |
c4ce6853 DE |
4981 | the operand number of the label. OP is the conditional expression. |
4982 | XEXP (OP, 0) is assumed to be a condition code register (integer or | |
4983 | floating point) and its mode specifies what kind of comparison we made. | |
61a55e8b | 4984 | |
ab835497 RK |
4985 | REVERSED is non-zero if we should reverse the sense of the comparison. |
4986 | ||
4987 | ANNUL is non-zero if we should generate an annulling branch. | |
4988 | ||
c6b0465b JC |
4989 | NOOP is non-zero if we have to follow this branch by a noop. |
4990 | ||
4991 | INSN, if set, is the insn. */ | |
ab835497 RK |
4992 | |
4993 | char * | |
c6b0465b | 4994 | output_cbranch (op, label, reversed, annul, noop, insn) |
c4ce6853 | 4995 | rtx op; |
ab835497 RK |
4996 | int label; |
4997 | int reversed, annul, noop; | |
c6b0465b | 4998 | rtx insn; |
ab835497 | 4999 | { |
e0d80184 | 5000 | static char string[32]; |
ab835497 | 5001 | enum rtx_code code = GET_CODE (op); |
c4ce6853 DE |
5002 | rtx cc_reg = XEXP (op, 0); |
5003 | enum machine_mode mode = GET_MODE (cc_reg); | |
e0d80184 DM |
5004 | static char v8_labelno[] = "%lX"; |
5005 | static char v9_icc_labelno[] = "%%icc, %lX"; | |
5006 | static char v9_xcc_labelno[] = "%%xcc, %lX"; | |
5007 | static char v9_fcc_labelno[] = "%%fccX, %lY"; | |
61a55e8b | 5008 | char *labelno; |
e267e177 | 5009 | const char *branch; |
e0d80184 | 5010 | int labeloff, spaces = 8; |
61a55e8b | 5011 | |
e267e177 | 5012 | if (reversed) |
ab835497 | 5013 | { |
e267e177 RH |
5014 | /* Reversal of FP compares takes care -- an ordered compare |
5015 | becomes an unordered compare and vice versa. */ | |
4d449554 | 5016 | if (mode == CCFPmode || mode == CCFPEmode) |
7913f3d0 | 5017 | code = reverse_condition_maybe_unordered (code); |
ab835497 | 5018 | else |
e267e177 | 5019 | code = reverse_condition (code); |
ab835497 RK |
5020 | } |
5021 | ||
e267e177 RH |
5022 | /* Start by writing the branch condition. */ |
5023 | if (mode == CCFPmode || mode == CCFPEmode) | |
5850dc00 RH |
5024 | { |
5025 | switch (code) | |
5026 | { | |
5027 | case NE: | |
5028 | branch = "fbne"; | |
5029 | break; | |
5030 | case EQ: | |
5031 | branch = "fbe"; | |
5032 | break; | |
5033 | case GE: | |
5034 | branch = "fbge"; | |
5035 | break; | |
5036 | case GT: | |
5037 | branch = "fbg"; | |
5038 | break; | |
5039 | case LE: | |
5040 | branch = "fble"; | |
5041 | break; | |
5042 | case LT: | |
5043 | branch = "fbl"; | |
5044 | break; | |
5045 | case UNORDERED: | |
5046 | branch = "fbu"; | |
5047 | break; | |
5048 | case ORDERED: | |
5049 | branch = "fbo"; | |
5050 | break; | |
5051 | case UNGT: | |
5052 | branch = "fbug"; | |
5053 | break; | |
5054 | case UNLT: | |
5055 | branch = "fbul"; | |
5056 | break; | |
5057 | case UNEQ: | |
5058 | branch = "fbue"; | |
5059 | break; | |
5060 | case UNGE: | |
5061 | branch = "fbuge"; | |
5062 | break; | |
5063 | case UNLE: | |
5064 | branch = "fbule"; | |
5065 | break; | |
5066 | case LTGT: | |
5067 | branch = "fblg"; | |
5068 | break; | |
5069 | ||
5070 | default: | |
5071 | abort (); | |
5072 | } | |
5073 | ||
5074 | /* ??? !v9: FP branches cannot be preceded by another floating point | |
5075 | insn. Because there is currently no concept of pre-delay slots, | |
5076 | we can fix this only by always emitting a nop before a floating | |
5077 | point branch. */ | |
5078 | ||
5079 | string[0] = '\0'; | |
5080 | if (! TARGET_V9) | |
5081 | strcpy (string, "nop\n\t"); | |
5082 | strcat (string, branch); | |
5083 | } | |
e267e177 | 5084 | else |
5850dc00 RH |
5085 | { |
5086 | switch (code) | |
5087 | { | |
5088 | case NE: | |
5089 | branch = "bne"; | |
5090 | break; | |
5091 | case EQ: | |
5092 | branch = "be"; | |
5093 | break; | |
5094 | case GE: | |
5095 | if (mode == CC_NOOVmode) | |
5096 | branch = "bpos"; | |
5097 | else | |
5098 | branch = "bge"; | |
5099 | break; | |
5100 | case GT: | |
5101 | branch = "bg"; | |
5102 | break; | |
5103 | case LE: | |
5104 | branch = "ble"; | |
5105 | break; | |
5106 | case LT: | |
5107 | if (mode == CC_NOOVmode) | |
5108 | branch = "bneg"; | |
5109 | else | |
5110 | branch = "bl"; | |
5111 | break; | |
5112 | case GEU: | |
5113 | branch = "bgeu"; | |
5114 | break; | |
5115 | case GTU: | |
5116 | branch = "bgu"; | |
5117 | break; | |
5118 | case LEU: | |
5119 | branch = "bleu"; | |
5120 | break; | |
5121 | case LTU: | |
5122 | branch = "blu"; | |
5123 | break; | |
5124 | ||
5125 | default: | |
5126 | abort (); | |
5127 | } | |
5128 | strcpy (string, branch); | |
5129 | } | |
e267e177 RH |
5130 | spaces -= strlen (branch); |
5131 | ||
ab835497 RK |
5132 | /* Now add the annulling, the label, and a possible noop. */ |
5133 | if (annul) | |
e0d80184 DM |
5134 | { |
5135 | strcat (string, ",a"); | |
5136 | spaces -= 2; | |
5137 | } | |
ab835497 | 5138 | |
61a55e8b DE |
5139 | if (! TARGET_V9) |
5140 | { | |
e0d80184 | 5141 | labeloff = 2; |
61a55e8b DE |
5142 | labelno = v8_labelno; |
5143 | } | |
5144 | else | |
5145 | { | |
c6b0465b JC |
5146 | rtx note; |
5147 | ||
5148 | if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX))) | |
e0d80184 DM |
5149 | { |
5150 | strcat (string, | |
5151 | INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn"); | |
5152 | spaces -= 3; | |
5153 | } | |
c6b0465b | 5154 | |
61a55e8b DE |
5155 | labeloff = 9; |
5156 | if (mode == CCFPmode || mode == CCFPEmode) | |
5157 | { | |
5158 | labeloff = 10; | |
5159 | labelno = v9_fcc_labelno; | |
5160 | /* Set the char indicating the number of the fcc reg to use. */ | |
e0d80184 | 5161 | labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; |
61a55e8b DE |
5162 | } |
5163 | else if (mode == CCXmode || mode == CCX_NOOVmode) | |
5164 | labelno = v9_xcc_labelno; | |
5165 | else | |
5166 | labelno = v9_icc_labelno; | |
5167 | } | |
5168 | /* Set the char indicating the number of the operand containing the | |
5169 | label_ref. */ | |
5170 | labelno[labeloff] = label + '0'; | |
e0d80184 DM |
5171 | if (spaces > 0) |
5172 | strcat (string, "\t"); | |
5173 | else | |
5174 | strcat (string, " "); | |
61a55e8b DE |
5175 | strcat (string, labelno); |
5176 | ||
5177 | if (noop) | |
5178 | strcat (string, "\n\tnop"); | |
5179 | ||
5180 | return string; | |
5181 | } | |
5182 | ||
47ac041c JJ |
5183 | /* Emit a library call comparison between floating point X and Y. |
5184 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). | |
5185 | TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode | |
5186 | values as arguments instead of the TFmode registers themselves, | |
5187 | that's why we cannot call emit_float_lib_cmp. */ | |
5188 | void | |
5189 | sparc_emit_float_lib_cmp (x, y, comparison) | |
5190 | rtx x, y; | |
5191 | enum rtx_code comparison; | |
5192 | { | |
e77d72cb | 5193 | const char *qpfunc; |
5c5c34a4 JJ |
5194 | rtx slot0, slot1, result, tem, tem2; |
5195 | enum machine_mode mode; | |
47ac041c JJ |
5196 | |
5197 | switch (comparison) | |
5198 | { | |
5199 | case EQ: | |
5c5c34a4 | 5200 | qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq"; |
47ac041c JJ |
5201 | break; |
5202 | ||
5203 | case NE: | |
5c5c34a4 | 5204 | qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne"; |
47ac041c JJ |
5205 | break; |
5206 | ||
5207 | case GT: | |
5c5c34a4 | 5208 | qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt"; |
47ac041c JJ |
5209 | break; |
5210 | ||
5211 | case GE: | |
5c5c34a4 | 5212 | qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge"; |
47ac041c JJ |
5213 | break; |
5214 | ||
5215 | case LT: | |
5c5c34a4 | 5216 | qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt"; |
47ac041c JJ |
5217 | break; |
5218 | ||
5219 | case LE: | |
5c5c34a4 JJ |
5220 | qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle"; |
5221 | break; | |
5222 | ||
5223 | case ORDERED: | |
5224 | case UNORDERED: | |
5225 | case UNGT: | |
5226 | case UNLT: | |
5227 | case UNEQ: | |
5228 | case UNGE: | |
5229 | case UNLE: | |
5230 | case LTGT: | |
5231 | qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp"; | |
47ac041c JJ |
5232 | break; |
5233 | ||
5234 | default: | |
5235 | abort(); | |
5236 | break; | |
5237 | } | |
5238 | ||
5c5c34a4 | 5239 | if (TARGET_ARCH64) |
47ac041c | 5240 | { |
5c5c34a4 JJ |
5241 | if (GET_CODE (x) != MEM) |
5242 | { | |
5243 | slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); | |
5244 | emit_insn (gen_rtx_SET (VOIDmode, slot0, x)); | |
5245 | } | |
5246 | else | |
5247 | slot0 = x; | |
5248 | ||
5249 | if (GET_CODE (y) != MEM) | |
5250 | { | |
5251 | slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); | |
5252 | emit_insn (gen_rtx_SET (VOIDmode, slot1, y)); | |
5253 | } | |
5254 | else | |
5255 | slot1 = y; | |
47ac041c | 5256 | |
5c5c34a4 JJ |
5257 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), 1, |
5258 | DImode, 2, | |
5259 | XEXP (slot0, 0), Pmode, | |
5260 | XEXP (slot1, 0), Pmode); | |
5261 | ||
5262 | mode = DImode; | |
5263 | } | |
5264 | else | |
47ac041c | 5265 | { |
5c5c34a4 JJ |
5266 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), 1, |
5267 | SImode, 2, | |
5268 | x, TFmode, y, TFmode); | |
5269 | ||
5270 | mode = SImode; | |
47ac041c JJ |
5271 | } |
5272 | ||
47ac041c JJ |
5273 | |
5274 | /* Immediately move the result of the libcall into a pseudo | |
5275 | register so reload doesn't clobber the value if it needs | |
5276 | the return register for a spill reg. */ | |
5c5c34a4 JJ |
5277 | result = gen_reg_rtx (mode); |
5278 | emit_move_insn (result, hard_libcall_value (mode)); | |
47ac041c | 5279 | |
5c5c34a4 JJ |
5280 | switch (comparison) |
5281 | { | |
5282 | default: | |
5283 | emit_cmp_insn (result, const0_rtx, NE, | |
5284 | NULL_RTX, mode, 0, 0); | |
5285 | break; | |
5286 | case ORDERED: | |
5287 | case UNORDERED: | |
5288 | emit_cmp_insn (result, GEN_INT(3), | |
5289 | (comparison == UNORDERED) ? EQ : NE, | |
5290 | NULL_RTX, mode, 0, 0); | |
5291 | break; | |
5292 | case UNGT: | |
5293 | case UNGE: | |
5294 | emit_cmp_insn (result, const1_rtx, | |
5295 | (comparison == UNGT) ? GT : NE, | |
5296 | NULL_RTX, mode, 0, 0); | |
5297 | break; | |
5298 | case UNLE: | |
5299 | emit_cmp_insn (result, const2_rtx, NE, | |
5300 | NULL_RTX, mode, 0, 0); | |
5301 | break; | |
5302 | case UNLT: | |
5303 | tem = gen_reg_rtx (mode); | |
5304 | if (TARGET_ARCH32) | |
5305 | emit_insn (gen_andsi3 (tem, result, const1_rtx)); | |
5306 | else | |
5307 | emit_insn (gen_anddi3 (tem, result, const1_rtx)); | |
5308 | emit_cmp_insn (tem, const0_rtx, NE, | |
5309 | NULL_RTX, mode, 0, 0); | |
5310 | break; | |
5311 | case UNEQ: | |
5312 | case LTGT: | |
5313 | tem = gen_reg_rtx (mode); | |
5314 | if (TARGET_ARCH32) | |
5315 | emit_insn (gen_addsi3 (tem, result, const1_rtx)); | |
5316 | else | |
5317 | emit_insn (gen_adddi3 (tem, result, const1_rtx)); | |
5318 | tem2 = gen_reg_rtx (mode); | |
5319 | if (TARGET_ARCH32) | |
5320 | emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); | |
5321 | else | |
5322 | emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); | |
5323 | emit_cmp_insn (tem2, const0_rtx, | |
5324 | (comparison == UNEQ) ? EQ : NE, | |
5325 | NULL_RTX, mode, 0, 0); | |
5326 | break; | |
5327 | } | |
47ac041c | 5328 | } |
5c5c34a4 | 5329 | |
61a55e8b DE |
5330 | /* Return the string to output a conditional branch to LABEL, testing |
5331 | register REG. LABEL is the operand number of the label; REG is the | |
5332 | operand number of the reg. OP is the conditional expression. The mode | |
5333 | of REG says what kind of comparison we made. | |
5334 | ||
5335 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
5336 | ||
5337 | ANNUL is non-zero if we should generate an annulling branch. | |
5338 | ||
5339 | NOOP is non-zero if we have to follow this branch by a noop. */ | |
5340 | ||
5341 | char * | |
e0d80184 | 5342 | output_v9branch (op, reg, label, reversed, annul, noop, insn) |
61a55e8b DE |
5343 | rtx op; |
5344 | int reg, label; | |
5345 | int reversed, annul, noop; | |
e0d80184 | 5346 | rtx insn; |
61a55e8b DE |
5347 | { |
5348 | static char string[20]; | |
5349 | enum rtx_code code = GET_CODE (op); | |
5350 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
e0d80184 DM |
5351 | static char labelno[] = "%X, %lX"; |
5352 | rtx note; | |
5353 | int spaces = 8; | |
61a55e8b DE |
5354 | |
5355 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
5356 | if (reversed) | |
5357 | code = reverse_condition (code), reversed = 0; | |
5358 | ||
5359 | /* Only 64 bit versions of these instructions exist. */ | |
5360 | if (mode != DImode) | |
5361 | abort (); | |
5362 | ||
5363 | /* Start by writing the branch condition. */ | |
5364 | ||
5365 | switch (code) | |
5366 | { | |
5367 | case NE: | |
5368 | strcpy (string, "brnz"); | |
e0d80184 | 5369 | spaces -= 4; |
61a55e8b DE |
5370 | break; |
5371 | ||
5372 | case EQ: | |
5373 | strcpy (string, "brz"); | |
e0d80184 | 5374 | spaces -= 3; |
61a55e8b DE |
5375 | break; |
5376 | ||
5377 | case GE: | |
5378 | strcpy (string, "brgez"); | |
e0d80184 | 5379 | spaces -= 5; |
61a55e8b DE |
5380 | break; |
5381 | ||
5382 | case LT: | |
5383 | strcpy (string, "brlz"); | |
e0d80184 | 5384 | spaces -= 4; |
61a55e8b DE |
5385 | break; |
5386 | ||
5387 | case LE: | |
5388 | strcpy (string, "brlez"); | |
e0d80184 | 5389 | spaces -= 5; |
61a55e8b DE |
5390 | break; |
5391 | ||
5392 | case GT: | |
5393 | strcpy (string, "brgz"); | |
e0d80184 | 5394 | spaces -= 4; |
61a55e8b DE |
5395 | break; |
5396 | ||
5397 | default: | |
5398 | abort (); | |
5399 | } | |
5400 | ||
5401 | /* Now add the annulling, reg, label, and nop. */ | |
5402 | if (annul) | |
e0d80184 DM |
5403 | { |
5404 | strcat (string, ",a"); | |
5405 | spaces -= 2; | |
5406 | } | |
61a55e8b | 5407 | |
e0d80184 DM |
5408 | if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX))) |
5409 | { | |
5410 | strcat (string, | |
5411 | INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn"); | |
5412 | spaces -= 3; | |
5413 | } | |
61a55e8b | 5414 | |
e0d80184 | 5415 | labelno[1] = reg + '0'; |
61a55e8b | 5416 | labelno[6] = label + '0'; |
e0d80184 DM |
5417 | if (spaces > 0) |
5418 | strcat (string, "\t"); | |
5419 | else | |
5420 | strcat (string, " "); | |
ab835497 RK |
5421 | strcat (string, labelno); |
5422 | ||
5423 | if (noop) | |
5424 | strcat (string, "\n\tnop"); | |
5425 | ||
5426 | return string; | |
5427 | } | |
5428 | ||
e48addee JJ |
5429 | /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. |
5430 | Such instructions cannot be used in the delay slot of return insn on v9. | |
5431 | If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. | |
5432 | */ | |
284d86e9 | 5433 | |
e48addee JJ |
5434 | static int |
5435 | epilogue_renumber (where, test) | |
5436 | register rtx *where; | |
5437 | int test; | |
284d86e9 | 5438 | { |
e48addee JJ |
5439 | register const char *fmt; |
5440 | register int i; | |
5441 | register enum rtx_code code; | |
5442 | ||
5443 | if (*where == 0) | |
5444 | return 0; | |
5445 | ||
5446 | code = GET_CODE (*where); | |
284d86e9 JC |
5447 | |
5448 | switch (code) | |
5449 | { | |
284d86e9 | 5450 | case REG: |
e48addee JJ |
5451 | if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ |
5452 | return 1; | |
5453 | if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) | |
5454 | *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); | |
5455 | case SCRATCH: | |
5456 | case CC0: | |
5457 | case PC: | |
284d86e9 JC |
5458 | case CONST_INT: |
5459 | case CONST_DOUBLE: | |
e48addee | 5460 | return 0; |
76a7c776 DM |
5461 | |
5462 | default: | |
5463 | break; | |
e48addee | 5464 | } |
284d86e9 | 5465 | |
e48addee | 5466 | fmt = GET_RTX_FORMAT (code); |
284d86e9 | 5467 | |
e48addee JJ |
5468 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
5469 | { | |
5470 | if (fmt[i] == 'E') | |
5471 | { | |
5472 | register int j; | |
5473 | for (j = XVECLEN (*where, i) - 1; j >= 0; j--) | |
5474 | if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) | |
5475 | return 1; | |
5476 | } | |
5477 | else if (fmt[i] == 'e' | |
5478 | && epilogue_renumber (&(XEXP (*where, i)), test)) | |
5479 | return 1; | |
284d86e9 | 5480 | } |
e48addee | 5481 | return 0; |
284d86e9 JC |
5482 | } |
5483 | ||
5484 | /* Output assembler code to return from a function. */ | |
61a55e8b | 5485 | |
3bb5de61 | 5486 | const char * |
ab835497 RK |
5487 | output_return (operands) |
5488 | rtx *operands; | |
5489 | { | |
284d86e9 JC |
5490 | rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0; |
5491 | ||
ab835497 RK |
5492 | if (leaf_label) |
5493 | { | |
5494 | operands[0] = leaf_label; | |
284d86e9 | 5495 | return "b%* %l0%("; |
ab835497 | 5496 | } |
54ff41b7 | 5497 | else if (current_function_uses_only_leaf_regs) |
ab835497 | 5498 | { |
284d86e9 JC |
5499 | /* No delay slot in a leaf function. */ |
5500 | if (delay) | |
5501 | abort (); | |
5502 | ||
915f619f JW |
5503 | /* If we didn't allocate a frame pointer for the current function, |
5504 | the stack pointer might have been adjusted. Output code to | |
5505 | restore it now. */ | |
5506 | ||
3a598fbe | 5507 | operands[0] = GEN_INT (actual_fsize); |
915f619f JW |
5508 | |
5509 | /* Use sub of negated value in first two cases instead of add to | |
5510 | allow actual_fsize == 4096. */ | |
5511 | ||
5512 | if (actual_fsize <= 4096) | |
ab835497 | 5513 | { |
61a55e8b | 5514 | if (SKIP_CALLERS_UNIMP_P) |
e0d80184 | 5515 | return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp"; |
ab835497 | 5516 | else |
e0d80184 | 5517 | return "retl\n\tsub\t%%sp, -%0, %%sp"; |
ab835497 | 5518 | } |
915f619f | 5519 | else if (actual_fsize <= 8192) |
ab835497 | 5520 | { |
3a598fbe | 5521 | operands[0] = GEN_INT (actual_fsize - 4096); |
61a55e8b | 5522 | if (SKIP_CALLERS_UNIMP_P) |
e0d80184 | 5523 | return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp"; |
915f619f | 5524 | else |
e0d80184 | 5525 | return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp"; |
915f619f | 5526 | } |
61a55e8b | 5527 | else if (SKIP_CALLERS_UNIMP_P) |
915f619f JW |
5528 | { |
5529 | if ((actual_fsize & 0x3ff) != 0) | |
e0d80184 | 5530 | return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp"; |
ab835497 | 5531 | else |
e0d80184 | 5532 | return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp"; |
915f619f JW |
5533 | } |
5534 | else | |
5535 | { | |
5536 | if ((actual_fsize & 0x3ff) != 0) | |
4df1190a | 5537 | return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tretl\n\tadd\t%%sp, %%g1, %%sp"; |
915f619f | 5538 | else |
4df1190a | 5539 | return "sethi\t%%hi(%a0), %%g1\n\tretl\n\tadd\t%%sp, %%g1, %%sp"; |
ab835497 RK |
5540 | } |
5541 | } | |
284d86e9 JC |
5542 | else if (TARGET_V9) |
5543 | { | |
5544 | if (delay) | |
5545 | { | |
e48addee JJ |
5546 | epilogue_renumber (&SET_DEST (PATTERN (delay)), 0); |
5547 | epilogue_renumber (&SET_SRC (PATTERN (delay)), 0); | |
284d86e9 JC |
5548 | } |
5549 | if (SKIP_CALLERS_UNIMP_P) | |
e0d80184 | 5550 | return "return\t%%i7+12%#"; |
284d86e9 | 5551 | else |
e0d80184 | 5552 | return "return\t%%i7+8%#"; |
284d86e9 | 5553 | } |
ab835497 RK |
5554 | else |
5555 | { | |
284d86e9 JC |
5556 | if (delay) |
5557 | abort (); | |
61a55e8b | 5558 | if (SKIP_CALLERS_UNIMP_P) |
e0d80184 | 5559 | return "jmp\t%%i7+12\n\trestore"; |
ab835497 RK |
5560 | else |
5561 | return "ret\n\trestore"; | |
5562 | } | |
5563 | } | |
ab835497 RK |
5564 | \f |
5565 | /* Leaf functions and non-leaf functions have different needs. */ | |
5566 | ||
5567 | static int | |
5568 | reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; | |
5569 | ||
5570 | static int | |
5571 | reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; | |
5572 | ||
5573 | static int *reg_alloc_orders[] = { | |
5574 | reg_leaf_alloc_order, | |
5575 | reg_nonleaf_alloc_order}; | |
5576 | ||
5577 | void | |
5578 | order_regs_for_local_alloc () | |
5579 | { | |
5580 | static int last_order_nonleaf = 1; | |
5581 | ||
5582 | if (regs_ever_live[15] != last_order_nonleaf) | |
5583 | { | |
5584 | last_order_nonleaf = !last_order_nonleaf; | |
2e09e75a JM |
5585 | memcpy ((char *) reg_alloc_order, |
5586 | (char *) reg_alloc_orders[last_order_nonleaf], | |
5587 | FIRST_PSEUDO_REGISTER * sizeof (int)); | |
ab835497 RK |
5588 | } |
5589 | } | |
5590 | \f | |
e0d80184 DM |
5591 | /* Return 1 if REG and MEM are legitimate enough to allow the various |
5592 | mem<-->reg splits to be run. */ | |
5593 | ||
5594 | int | |
e61c29e9 | 5595 | sparc_splitdi_legitimate (reg, mem) |
e0d80184 DM |
5596 | rtx reg; |
5597 | rtx mem; | |
5598 | { | |
e0d80184 DM |
5599 | /* Punt if we are here by mistake. */ |
5600 | if (! reload_completed) | |
9208e4b2 | 5601 | abort (); |
e0d80184 DM |
5602 | |
5603 | /* We must have an offsettable memory reference. */ | |
5604 | if (! offsettable_memref_p (mem)) | |
5605 | return 0; | |
5606 | ||
5607 | /* If we have legitimate args for ldd/std, we do not want | |
5608 | the split to happen. */ | |
5609 | if ((REGNO (reg) % 2) == 0 | |
5610 | && mem_min_alignment (mem, 8)) | |
5611 | return 0; | |
5612 | ||
5613 | /* Success. */ | |
5614 | return 1; | |
5615 | } | |
5616 | ||
e61c29e9 DM |
5617 | /* Return 1 if x and y are some kind of REG and they refer to |
5618 | different hard registers. This test is guarenteed to be | |
5619 | run after reload. */ | |
5620 | ||
5621 | int | |
5622 | sparc_absnegfloat_split_legitimate (x, y) | |
5623 | rtx x, y; | |
5624 | { | |
5625 | if (GET_CODE (x) == SUBREG) | |
5626 | x = alter_subreg (x); | |
5627 | if (GET_CODE (x) != REG) | |
5628 | return 0; | |
5629 | if (GET_CODE (y) == SUBREG) | |
5630 | y = alter_subreg (y); | |
5631 | if (GET_CODE (y) != REG) | |
5632 | return 0; | |
5633 | if (REGNO (x) == REGNO (y)) | |
5634 | return 0; | |
5635 | return 1; | |
5636 | } | |
5637 | ||
35016322 JW |
5638 | /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. |
5639 | This makes them candidates for using ldd and std insns. | |
5640 | ||
bfd6bc60 | 5641 | Note reg1 and reg2 *must* be hard registers. */ |
35016322 JW |
5642 | |
5643 | int | |
7c56249d | 5644 | registers_ok_for_ldd_peep (reg1, reg2) |
35016322 JW |
5645 | rtx reg1, reg2; |
5646 | { | |
35016322 JW |
5647 | /* We might have been passed a SUBREG. */ |
5648 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
5649 | return 0; | |
5650 | ||
35016322 JW |
5651 | if (REGNO (reg1) % 2 != 0) |
5652 | return 0; | |
5653 | ||
bfd6bc60 JC |
5654 | /* Integer ldd is deprecated in SPARC V9 */ |
5655 | if (TARGET_V9 && REGNO (reg1) < 32) | |
5656 | return 0; | |
5657 | ||
35016322 | 5658 | return (REGNO (reg1) == REGNO (reg2) - 1); |
35016322 JW |
5659 | } |
5660 | ||
5661 | /* Return 1 if addr1 and addr2 are suitable for use in an ldd or | |
5662 | std insn. | |
5663 | ||
5664 | This can only happen when addr1 and addr2 are consecutive memory | |
5665 | locations (addr1 + 4 == addr2). addr1 must also be aligned on a | |
5666 | 64 bit boundary (addr1 % 8 == 0). | |
5667 | ||
5668 | We know %sp and %fp are kept aligned on a 64 bit boundary. Other | |
5669 | registers are assumed to *never* be properly aligned and are | |
5670 | rejected. | |
5671 | ||
5672 | Knowing %sp and %fp are kept aligned on a 64 bit boundary, we | |
5673 | need only check that the offset for addr1 % 8 == 0. */ | |
5674 | ||
5675 | int | |
7c56249d | 5676 | addrs_ok_for_ldd_peep (addr1, addr2) |
35016322 JW |
5677 | rtx addr1, addr2; |
5678 | { | |
0d587737 KG |
5679 | unsigned int reg1; |
5680 | int offset1; | |
35016322 JW |
5681 | |
5682 | /* Extract a register number and offset (if used) from the first addr. */ | |
5683 | if (GET_CODE (addr1) == PLUS) | |
5684 | { | |
5685 | /* If not a REG, return zero. */ | |
5686 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
5687 | return 0; | |
5688 | else | |
5689 | { | |
5690 | reg1 = REGNO (XEXP (addr1, 0)); | |
5691 | /* The offset must be constant! */ | |
5692 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
5693 | return 0; | |
5694 | offset1 = INTVAL (XEXP (addr1, 1)); | |
5695 | } | |
5696 | } | |
5697 | else if (GET_CODE (addr1) != REG) | |
5698 | return 0; | |
5699 | else | |
5700 | { | |
5701 | reg1 = REGNO (addr1); | |
5702 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
5703 | offset1 = 0; | |
5704 | } | |
5705 | ||
5706 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
5707 | if (GET_CODE (addr2) != PLUS) | |
5708 | return 0; | |
5709 | ||
5710 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
5711 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
5712 | return 0; | |
5713 | ||
5714 | /* Only %fp and %sp are allowed. Additionally both addresses must | |
5715 | use the same register. */ | |
5716 | if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM) | |
5717 | return 0; | |
5718 | ||
5719 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
5720 | return 0; | |
5721 | ||
2296cba3 | 5722 | /* The first offset must be evenly divisible by 8 to ensure the |
35016322 JW |
5723 | address is 64 bit aligned. */ |
5724 | if (offset1 % 8 != 0) | |
5725 | return 0; | |
5726 | ||
5727 | /* The offset for the second addr must be 4 more than the first addr. */ | |
5728 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) | |
5729 | return 0; | |
5730 | ||
5731 | /* All the tests passed. addr1 and addr2 are valid for ldd and std | |
5732 | instructions. */ | |
5733 | return 1; | |
5734 | } | |
7c56249d JL |
5735 | |
5736 | /* Return 1 if reg is a pseudo, or is the first register in | |
5737 | a hard register pair. This makes it a candidate for use in | |
5738 | ldd and std insns. */ | |
5739 | ||
5740 | int | |
5741 | register_ok_for_ldd (reg) | |
5742 | rtx reg; | |
5743 | { | |
7c56249d JL |
5744 | /* We might have been passed a SUBREG. */ |
5745 | if (GET_CODE (reg) != REG) | |
5746 | return 0; | |
5747 | ||
5748 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
5749 | return (REGNO (reg) % 2 == 0); | |
5750 | else | |
5751 | return 1; | |
7c56249d | 5752 | } |
ab835497 | 5753 | \f |
ab835497 RK |
5754 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
5755 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
5756 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
5757 | ||
5758 | void | |
5759 | print_operand (file, x, code) | |
5760 | FILE *file; | |
5761 | rtx x; | |
5762 | int code; | |
5763 | { | |
5764 | switch (code) | |
5765 | { | |
5766 | case '#': | |
5767 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
5768 | if (dbr_sequence_length () == 0) | |
e0d80184 | 5769 | fputs ("\n\t nop", file); |
ab835497 RK |
5770 | return; |
5771 | case '*': | |
c6ce0969 JW |
5772 | /* Output an annul flag if there's nothing for the delay slot and we |
5773 | are optimizing. This is always used with '(' below. */ | |
5774 | /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; | |
5775 | this is a dbx bug. So, we only do this when optimizing. */ | |
bfd6bc60 JC |
5776 | /* On UltraSPARC, a branch in a delay slot causes a pipeline flush. |
5777 | Always emit a nop in case the next instruction is a branch. */ | |
5778 | if (dbr_sequence_length () == 0 | |
284d86e9 | 5779 | && (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
c6ce0969 JW |
5780 | fputs (",a", file); |
5781 | return; | |
5782 | case '(': | |
5783 | /* Output a 'nop' if there's nothing for the delay slot and we are | |
5784 | not optimizing. This is always used with '*' above. */ | |
bfd6bc60 | 5785 | if (dbr_sequence_length () == 0 |
284d86e9 | 5786 | && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
e0d80184 | 5787 | fputs ("\n\t nop", file); |
ab835497 | 5788 | return; |
61a55e8b | 5789 | case '_': |
a0a301fc DE |
5790 | /* Output the Embedded Medium/Anywhere code model base register. */ |
5791 | fputs (EMBMEDANY_BASE_REG, file); | |
61a55e8b DE |
5792 | return; |
5793 | case '@': | |
5794 | /* Print out what we are using as the frame pointer. This might | |
5795 | be %fp, or might be %sp+offset. */ | |
5796 | /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ | |
5797 | fprintf (file, "%s+%d", frame_base_name, frame_base_offset); | |
5798 | return; | |
ab835497 RK |
5799 | case 'Y': |
5800 | /* Adjust the operand to take into account a RESTORE operation. */ | |
bfd6bc60 JC |
5801 | if (GET_CODE (x) == CONST_INT) |
5802 | break; | |
5803 | else if (GET_CODE (x) != REG) | |
b3b1e8bd JW |
5804 | output_operand_lossage ("Invalid %%Y operand"); |
5805 | else if (REGNO (x) < 8) | |
ab835497 RK |
5806 | fputs (reg_names[REGNO (x)], file); |
5807 | else if (REGNO (x) >= 24 && REGNO (x) < 32) | |
5808 | fputs (reg_names[REGNO (x)-16], file); | |
5809 | else | |
b3b1e8bd | 5810 | output_operand_lossage ("Invalid %%Y operand"); |
ab835497 | 5811 | return; |
0f39a9aa DE |
5812 | case 'L': |
5813 | /* Print out the low order register name of a register pair. */ | |
5814 | if (WORDS_BIG_ENDIAN) | |
5815 | fputs (reg_names[REGNO (x)+1], file); | |
5816 | else | |
5817 | fputs (reg_names[REGNO (x)], file); | |
5818 | return; | |
5819 | case 'H': | |
5820 | /* Print out the high order register name of a register pair. */ | |
5821 | if (WORDS_BIG_ENDIAN) | |
5822 | fputs (reg_names[REGNO (x)], file); | |
5823 | else | |
5824 | fputs (reg_names[REGNO (x)+1], file); | |
5825 | return; | |
ab835497 | 5826 | case 'R': |
795068a4 | 5827 | /* Print out the second register name of a register pair or quad. |
ab835497 RK |
5828 | I.e., R (%o0) => %o1. */ |
5829 | fputs (reg_names[REGNO (x)+1], file); | |
5830 | return; | |
795068a4 JW |
5831 | case 'S': |
5832 | /* Print out the third register name of a register quad. | |
5833 | I.e., S (%o0) => %o2. */ | |
5834 | fputs (reg_names[REGNO (x)+2], file); | |
5835 | return; | |
5836 | case 'T': | |
5837 | /* Print out the fourth register name of a register quad. | |
5838 | I.e., T (%o0) => %o3. */ | |
5839 | fputs (reg_names[REGNO (x)+3], file); | |
5840 | return; | |
304b7a23 DE |
5841 | case 'x': |
5842 | /* Print a condition code register. */ | |
5843 | if (REGNO (x) == SPARC_ICC_REG) | |
5844 | { | |
5845 | /* We don't handle CC[X]_NOOVmode because they're not supposed | |
5846 | to occur here. */ | |
5847 | if (GET_MODE (x) == CCmode) | |
5848 | fputs ("%icc", file); | |
5849 | else if (GET_MODE (x) == CCXmode) | |
5850 | fputs ("%xcc", file); | |
5851 | else | |
5852 | abort (); | |
5853 | } | |
5854 | else | |
5855 | /* %fccN register */ | |
5856 | fputs (reg_names[REGNO (x)], file); | |
5857 | return; | |
ab835497 RK |
5858 | case 'm': |
5859 | /* Print the operand's address only. */ | |
5860 | output_address (XEXP (x, 0)); | |
5861 | return; | |
5862 | case 'r': | |
5863 | /* In this case we need a register. Use %g0 if the | |
77a02b01 | 5864 | operand is const0_rtx. */ |
76052e74 RS |
5865 | if (x == const0_rtx |
5866 | || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) | |
ab835497 RK |
5867 | { |
5868 | fputs ("%g0", file); | |
5869 | return; | |
5870 | } | |
5871 | else | |
5872 | break; | |
5873 | ||
61a55e8b | 5874 | case 'A': |
ab835497 RK |
5875 | switch (GET_CODE (x)) |
5876 | { | |
5877 | case IOR: fputs ("or", file); break; | |
5878 | case AND: fputs ("and", file); break; | |
5879 | case XOR: fputs ("xor", file); break; | |
b3b1e8bd | 5880 | default: output_operand_lossage ("Invalid %%A operand"); |
ab835497 RK |
5881 | } |
5882 | return; | |
5883 | ||
5884 | case 'B': | |
5885 | switch (GET_CODE (x)) | |
5886 | { | |
5887 | case IOR: fputs ("orn", file); break; | |
5888 | case AND: fputs ("andn", file); break; | |
5889 | case XOR: fputs ("xnor", file); break; | |
b3b1e8bd | 5890 | default: output_operand_lossage ("Invalid %%B operand"); |
ab835497 RK |
5891 | } |
5892 | return; | |
5893 | ||
304b7a23 DE |
5894 | /* These are used by the conditional move instructions. */ |
5895 | case 'c' : | |
61a55e8b | 5896 | case 'C': |
304b7a23 | 5897 | { |
5c5c34a4 JJ |
5898 | enum rtx_code rc = GET_CODE (x); |
5899 | ||
5900 | if (code == 'c') | |
5901 | { | |
5902 | enum machine_mode mode = GET_MODE (XEXP (x, 0)); | |
5903 | if (mode == CCFPmode || mode == CCFPEmode) | |
5904 | rc = reverse_condition_maybe_unordered (GET_CODE (x)); | |
5905 | else | |
5906 | rc = reverse_condition (GET_CODE (x)); | |
5907 | } | |
304b7a23 DE |
5908 | switch (rc) |
5909 | { | |
5910 | case NE: fputs ("ne", file); break; | |
5911 | case EQ: fputs ("e", file); break; | |
5912 | case GE: fputs ("ge", file); break; | |
5913 | case GT: fputs ("g", file); break; | |
5914 | case LE: fputs ("le", file); break; | |
5915 | case LT: fputs ("l", file); break; | |
5916 | case GEU: fputs ("geu", file); break; | |
5917 | case GTU: fputs ("gu", file); break; | |
5918 | case LEU: fputs ("leu", file); break; | |
5919 | case LTU: fputs ("lu", file); break; | |
5c5c34a4 JJ |
5920 | case LTGT: fputs ("lg", file); break; |
5921 | case UNORDERED: fputs ("u", file); break; | |
5922 | case ORDERED: fputs ("o", file); break; | |
5923 | case UNLT: fputs ("ul", file); break; | |
5924 | case UNLE: fputs ("ule", file); break; | |
5925 | case UNGT: fputs ("ug", file); break; | |
5926 | case UNGE: fputs ("uge", file); break; | |
5927 | case UNEQ: fputs ("ue", file); break; | |
304b7a23 DE |
5928 | default: output_operand_lossage (code == 'c' |
5929 | ? "Invalid %%c operand" | |
5930 | : "Invalid %%C operand"); | |
5931 | } | |
5932 | return; | |
5933 | } | |
5934 | ||
5935 | /* These are used by the movr instruction pattern. */ | |
5936 | case 'd': | |
61a55e8b | 5937 | case 'D': |
304b7a23 DE |
5938 | { |
5939 | enum rtx_code rc = (code == 'd' | |
5940 | ? reverse_condition (GET_CODE (x)) | |
5941 | : GET_CODE (x)); | |
5942 | switch (rc) | |
5943 | { | |
5944 | case NE: fputs ("ne", file); break; | |
5945 | case EQ: fputs ("e", file); break; | |
5946 | case GE: fputs ("gez", file); break; | |
5947 | case LT: fputs ("lz", file); break; | |
5948 | case LE: fputs ("lez", file); break; | |
5949 | case GT: fputs ("gz", file); break; | |
5950 | default: output_operand_lossage (code == 'd' | |
5951 | ? "Invalid %%d operand" | |
5952 | : "Invalid %%D operand"); | |
5953 | } | |
5954 | return; | |
5955 | } | |
61a55e8b | 5956 | |
ab835497 RK |
5957 | case 'b': |
5958 | { | |
5959 | /* Print a sign-extended character. */ | |
5960 | int i = INTVAL (x) & 0xff; | |
5961 | if (i & 0x80) | |
5962 | i |= 0xffffff00; | |
5963 | fprintf (file, "%d", i); | |
5964 | return; | |
5965 | } | |
5966 | ||
d2889939 RK |
5967 | case 'f': |
5968 | /* Operand must be a MEM; write its address. */ | |
5969 | if (GET_CODE (x) != MEM) | |
5970 | output_operand_lossage ("Invalid %%f operand"); | |
5971 | output_address (XEXP (x, 0)); | |
5972 | return; | |
5973 | ||
ab835497 RK |
5974 | case 0: |
5975 | /* Do nothing special. */ | |
5976 | break; | |
5977 | ||
5978 | default: | |
5979 | /* Undocumented flag. */ | |
415f583e | 5980 | output_operand_lossage ("invalid operand output code"); |
ab835497 RK |
5981 | } |
5982 | ||
5983 | if (GET_CODE (x) == REG) | |
5984 | fputs (reg_names[REGNO (x)], file); | |
5985 | else if (GET_CODE (x) == MEM) | |
5986 | { | |
5987 | fputc ('[', file); | |
ab835497 | 5988 | /* Poor Sun assembler doesn't understand absolute addressing. */ |
e6c1be7e | 5989 | if (CONSTANT_P (XEXP (x, 0))) |
ab835497 RK |
5990 | fputs ("%g0+", file); |
5991 | output_address (XEXP (x, 0)); | |
5992 | fputc (']', file); | |
5993 | } | |
5994 | else if (GET_CODE (x) == HIGH) | |
5995 | { | |
5996 | fputs ("%hi(", file); | |
5997 | output_addr_const (file, XEXP (x, 0)); | |
5998 | fputc (')', file); | |
5999 | } | |
6000 | else if (GET_CODE (x) == LO_SUM) | |
6001 | { | |
6002 | print_operand (file, XEXP (x, 0), 0); | |
e0d80184 DM |
6003 | if (TARGET_CM_MEDMID) |
6004 | fputs ("+%l44(", file); | |
6005 | else | |
6006 | fputs ("+%lo(", file); | |
ab835497 RK |
6007 | output_addr_const (file, XEXP (x, 1)); |
6008 | fputc (')', file); | |
6009 | } | |
e601abce JW |
6010 | else if (GET_CODE (x) == CONST_DOUBLE |
6011 | && (GET_MODE (x) == VOIDmode | |
6012 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) | |
ab835497 RK |
6013 | { |
6014 | if (CONST_DOUBLE_HIGH (x) == 0) | |
0d9484c5 | 6015 | fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x)); |
ab835497 RK |
6016 | else if (CONST_DOUBLE_HIGH (x) == -1 |
6017 | && CONST_DOUBLE_LOW (x) < 0) | |
0d9484c5 | 6018 | fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x)); |
ab835497 | 6019 | else |
e601abce | 6020 | output_operand_lossage ("long long constant not a valid immediate operand"); |
ab835497 | 6021 | } |
e601abce JW |
6022 | else if (GET_CODE (x) == CONST_DOUBLE) |
6023 | output_operand_lossage ("floating point constant not a valid immediate operand"); | |
ab835497 RK |
6024 | else { output_addr_const (file, x); } |
6025 | } | |
6026 | \f | |
6027 | /* This function outputs assembler code for VALUE to FILE, where VALUE is | |
6028 | a 64 bit (DImode) value. */ | |
6029 | ||
6030 | /* ??? If there is a 64 bit counterpart to .word that the assembler | |
6031 | understands, then using that would simply this code greatly. */ | |
61a55e8b DE |
6032 | /* ??? We only output .xword's for symbols and only then in environments |
6033 | where the assembler can handle them. */ | |
ab835497 RK |
6034 | |
6035 | void | |
6036 | output_double_int (file, value) | |
6037 | FILE *file; | |
6038 | rtx value; | |
6039 | { | |
6040 | if (GET_CODE (value) == CONST_INT) | |
6041 | { | |
f4f8e370 DE |
6042 | /* ??? This has endianness issues. */ |
6043 | #if HOST_BITS_PER_WIDE_INT == 64 | |
6044 | HOST_WIDE_INT xword = INTVAL (value); | |
6045 | HOST_WIDE_INT high, low; | |
6046 | ||
6047 | high = (xword >> 32) & 0xffffffff; | |
6048 | low = xword & 0xffffffff; | |
3a598fbe JL |
6049 | ASM_OUTPUT_INT (file, GEN_INT (high)); |
6050 | ASM_OUTPUT_INT (file, GEN_INT (low)); | |
f4f8e370 | 6051 | #else |
ab835497 RK |
6052 | if (INTVAL (value) < 0) |
6053 | ASM_OUTPUT_INT (file, constm1_rtx); | |
6054 | else | |
6055 | ASM_OUTPUT_INT (file, const0_rtx); | |
6056 | ASM_OUTPUT_INT (file, value); | |
f4f8e370 | 6057 | #endif |
ab835497 RK |
6058 | } |
6059 | else if (GET_CODE (value) == CONST_DOUBLE) | |
6060 | { | |
3a598fbe JL |
6061 | ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value))); |
6062 | ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value))); | |
ab835497 RK |
6063 | } |
6064 | else if (GET_CODE (value) == SYMBOL_REF | |
6065 | || GET_CODE (value) == CONST | |
61a55e8b | 6066 | || GET_CODE (value) == PLUS |
a9e27770 | 6067 | || (TARGET_ARCH64 && |
61a55e8b | 6068 | (GET_CODE (value) == LABEL_REF |
9fa9626b | 6069 | || GET_CODE (value) == CODE_LABEL |
61a55e8b | 6070 | || GET_CODE (value) == MINUS))) |
ab835497 | 6071 | { |
f3b8847b | 6072 | if (! TARGET_V9) |
61a55e8b DE |
6073 | { |
6074 | ASM_OUTPUT_INT (file, const0_rtx); | |
6075 | ASM_OUTPUT_INT (file, value); | |
6076 | } | |
6077 | else | |
6078 | { | |
6079 | fprintf (file, "\t%s\t", ASM_LONGLONG); | |
6080 | output_addr_const (file, value); | |
6081 | fprintf (file, "\n"); | |
6082 | } | |
ab835497 RK |
6083 | } |
6084 | else | |
6085 | abort (); | |
6086 | } | |
210aa14a | 6087 | \f |
b0468b84 RK |
6088 | /* Return the value of a code used in the .proc pseudo-op that says |
6089 | what kind of result this function returns. For non-C types, we pick | |
6090 | the closest C type. */ | |
6091 | ||
77a02b01 JW |
6092 | #ifndef CHAR_TYPE_SIZE |
6093 | #define CHAR_TYPE_SIZE BITS_PER_UNIT | |
6094 | #endif | |
6095 | ||
6096 | #ifndef SHORT_TYPE_SIZE | |
6097 | #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) | |
6098 | #endif | |
6099 | ||
6100 | #ifndef INT_TYPE_SIZE | |
6101 | #define INT_TYPE_SIZE BITS_PER_WORD | |
6102 | #endif | |
6103 | ||
6104 | #ifndef LONG_TYPE_SIZE | |
6105 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
6106 | #endif | |
6107 | ||
6108 | #ifndef LONG_LONG_TYPE_SIZE | |
6109 | #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) | |
6110 | #endif | |
6111 | ||
6112 | #ifndef FLOAT_TYPE_SIZE | |
6113 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
6114 | #endif | |
6115 | ||
6116 | #ifndef DOUBLE_TYPE_SIZE | |
6117 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
6118 | #endif | |
6119 | ||
6120 | #ifndef LONG_DOUBLE_TYPE_SIZE | |
6121 | #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
6122 | #endif | |
210aa14a RS |
6123 | |
6124 | unsigned long | |
6125 | sparc_type_code (type) | |
6126 | register tree type; | |
6127 | { | |
6128 | register unsigned long qualifiers = 0; | |
e5e809f4 | 6129 | register unsigned shift; |
210aa14a | 6130 | |
abc95ed3 | 6131 | /* Only the first 30 bits of the qualifier are valid. We must refrain from |
aee2c3c5 JW |
6132 | setting more, since some assemblers will give an error for this. Also, |
6133 | we must be careful to avoid shifts of 32 bits or more to avoid getting | |
6134 | unpredictable results. */ | |
6135 | ||
e5e809f4 | 6136 | for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) |
210aa14a RS |
6137 | { |
6138 | switch (TREE_CODE (type)) | |
6139 | { | |
6140 | case ERROR_MARK: | |
6141 | return qualifiers; | |
6142 | ||
6143 | case ARRAY_TYPE: | |
e5e809f4 | 6144 | qualifiers |= (3 << shift); |
210aa14a RS |
6145 | break; |
6146 | ||
6147 | case FUNCTION_TYPE: | |
6148 | case METHOD_TYPE: | |
e5e809f4 | 6149 | qualifiers |= (2 << shift); |
210aa14a RS |
6150 | break; |
6151 | ||
6152 | case POINTER_TYPE: | |
6153 | case REFERENCE_TYPE: | |
6154 | case OFFSET_TYPE: | |
e5e809f4 | 6155 | qualifiers |= (1 << shift); |
210aa14a | 6156 | break; |
ab835497 | 6157 | |
210aa14a RS |
6158 | case RECORD_TYPE: |
6159 | return (qualifiers | 8); | |
6160 | ||
6161 | case UNION_TYPE: | |
b0468b84 | 6162 | case QUAL_UNION_TYPE: |
210aa14a RS |
6163 | return (qualifiers | 9); |
6164 | ||
6165 | case ENUMERAL_TYPE: | |
6166 | return (qualifiers | 10); | |
6167 | ||
6168 | case VOID_TYPE: | |
6169 | return (qualifiers | 16); | |
6170 | ||
6171 | case INTEGER_TYPE: | |
654209e6 JW |
6172 | /* If this is a range type, consider it to be the underlying |
6173 | type. */ | |
6174 | if (TREE_TYPE (type) != 0) | |
e5e809f4 | 6175 | break; |
654209e6 | 6176 | |
77a02b01 | 6177 | /* Carefully distinguish all the standard types of C, |
b0468b84 RK |
6178 | without messing up if the language is not C. We do this by |
6179 | testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to | |
6180 | look at both the names and the above fields, but that's redundant. | |
6181 | Any type whose size is between two C types will be considered | |
6182 | to be the wider of the two types. Also, we do not have a | |
6183 | special code to use for "long long", so anything wider than | |
6184 | long is treated the same. Note that we can't distinguish | |
6185 | between "int" and "long" in this code if they are the same | |
6186 | size, but that's fine, since neither can the assembler. */ | |
6187 | ||
6188 | if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) | |
6189 | return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); | |
77a02b01 | 6190 | |
b0468b84 RK |
6191 | else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) |
6192 | return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); | |
77a02b01 | 6193 | |
b0468b84 | 6194 | else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) |
77a02b01 JW |
6195 | return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); |
6196 | ||
b0468b84 | 6197 | else |
77a02b01 JW |
6198 | return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); |
6199 | ||
210aa14a | 6200 | case REAL_TYPE: |
e5e809f4 JL |
6201 | /* If this is a range type, consider it to be the underlying |
6202 | type. */ | |
6203 | if (TREE_TYPE (type) != 0) | |
6204 | break; | |
6205 | ||
77a02b01 JW |
6206 | /* Carefully distinguish all the standard types of C, |
6207 | without messing up if the language is not C. */ | |
b0468b84 | 6208 | |
77a02b01 | 6209 | if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) |
210aa14a | 6210 | return (qualifiers | 6); |
b0468b84 RK |
6211 | |
6212 | else | |
6213 | return (qualifiers | 7); | |
210aa14a RS |
6214 | |
6215 | case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ | |
13d39dbc | 6216 | /* ??? We need to distinguish between double and float complex types, |
c82aa69a JW |
6217 | but I don't know how yet because I can't reach this code from |
6218 | existing front-ends. */ | |
6219 | return (qualifiers | 7); /* Who knows? */ | |
6220 | ||
210aa14a RS |
6221 | case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ |
6222 | case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ | |
6223 | case FILE_TYPE: /* GNU Pascal FILE type. */ | |
26902ae0 | 6224 | case SET_TYPE: /* GNU Pascal SET type. */ |
210aa14a | 6225 | case LANG_TYPE: /* ? */ |
26902ae0 | 6226 | return qualifiers; |
210aa14a RS |
6227 | |
6228 | default: | |
6229 | abort (); /* Not a type! */ | |
6230 | } | |
6231 | } | |
e5e809f4 JL |
6232 | |
6233 | return qualifiers; | |
210aa14a | 6234 | } |
ead69aea | 6235 | \f |
61a55e8b DE |
6236 | /* Nested function support. */ |
6237 | ||
6238 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
6239 | FNADDR is an RTX for the address of the function's pure code. | |
6240 | CXT is an RTX for the static chain value for the function. | |
6241 | ||
6242 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
6243 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
6244 | (to store insns). This is a bit excessive. Perhaps a different | |
6245 | mechanism would be better here. | |
6246 | ||
849a528d | 6247 | Emit enough FLUSH insns to synchronize the data and instruction caches. */ |
61a55e8b DE |
6248 | |
6249 | void | |
6250 | sparc_initialize_trampoline (tramp, fnaddr, cxt) | |
6251 | rtx tramp, fnaddr, cxt; | |
6252 | { | |
c6b0465b JC |
6253 | /* SPARC 32 bit trampoline: |
6254 | ||
e0d80184 DM |
6255 | sethi %hi(fn), %g1 |
6256 | sethi %hi(static), %g2 | |
6257 | jmp %g1+%lo(fn) | |
6258 | or %g2, %lo(static), %g2 | |
c6b0465b JC |
6259 | |
6260 | SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii | |
6261 | JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii | |
6262 | */ | |
959eb758 DM |
6263 | #ifdef TRANSFER_FROM_TRAMPOLINE |
6264 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
6265 | 0, VOIDmode, 1, tramp, Pmode); | |
6266 | #endif | |
c6b0465b JC |
6267 | |
6268 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), | |
6269 | expand_binop (SImode, ior_optab, | |
6270 | expand_shift (RSHIFT_EXPR, SImode, fnaddr, | |
6271 | size_int (10), 0, 1), | |
6272 | GEN_INT (0x03000000), | |
6273 | NULL_RTX, 1, OPTAB_DIRECT)); | |
6274 | ||
6275 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), | |
6276 | expand_binop (SImode, ior_optab, | |
6277 | expand_shift (RSHIFT_EXPR, SImode, cxt, | |
6278 | size_int (10), 0, 1), | |
6279 | GEN_INT (0x05000000), | |
6280 | NULL_RTX, 1, OPTAB_DIRECT)); | |
6281 | ||
6282 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), | |
6283 | expand_binop (SImode, ior_optab, | |
6284 | expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX), | |
6285 | GEN_INT (0x81c06000), | |
6286 | NULL_RTX, 1, OPTAB_DIRECT)); | |
6287 | ||
6288 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), | |
6289 | expand_binop (SImode, ior_optab, | |
6290 | expand_and (cxt, GEN_INT (0x3ff), NULL_RTX), | |
6291 | GEN_INT (0x8410a000), | |
6292 | NULL_RTX, 1, OPTAB_DIRECT)); | |
6293 | ||
254110c2 | 6294 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); |
c6b0465b JC |
6295 | /* On UltraSPARC a flush flushes an entire cache line. The trampoline is |
6296 | aligned on a 16 byte boundary so one flush clears it all. */ | |
6297 | if (sparc_cpu != PROCESSOR_ULTRASPARC) | |
6298 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, | |
6299 | plus_constant (tramp, 8))))); | |
61a55e8b DE |
6300 | } |
6301 | ||
849a528d RK |
6302 | /* The 64 bit version is simpler because it makes more sense to load the |
6303 | values as "immediate" data out of the trampoline. It's also easier since | |
6304 | we can read the PC without clobbering a register. */ | |
6305 | ||
61a55e8b DE |
6306 | void |
6307 | sparc64_initialize_trampoline (tramp, fnaddr, cxt) | |
6308 | rtx tramp, fnaddr, cxt; | |
6309 | { | |
345a6161 DM |
6310 | #ifdef TRANSFER_FROM_TRAMPOLINE |
6311 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
6312 | 0, VOIDmode, 1, tramp, Pmode); | |
6313 | #endif | |
6314 | ||
c6b0465b | 6315 | /* |
e0d80184 DM |
6316 | rd %pc, %g1 |
6317 | ldx [%g1+24], %g5 | |
6318 | jmp %g5 | |
6319 | ldx [%g1+16], %g5 | |
c6b0465b JC |
6320 | +16 bytes data |
6321 | */ | |
6322 | ||
6323 | emit_move_insn (gen_rtx_MEM (SImode, tramp), | |
6324 | GEN_INT (0x83414000)); | |
6325 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), | |
6326 | GEN_INT (0xca586018)); | |
6327 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), | |
345a6161 | 6328 | GEN_INT (0x81c14000)); |
c6b0465b JC |
6329 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), |
6330 | GEN_INT (0xca586010)); | |
6331 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); | |
345a6161 | 6332 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); |
d4203cb4 | 6333 | emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp)))); |
345a6161 | 6334 | |
c6b0465b | 6335 | if (sparc_cpu != PROCESSOR_ULTRASPARC) |
d4203cb4 | 6336 | emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); |
61a55e8b DE |
6337 | } |
6338 | \f | |
c819be5b JW |
6339 | /* Subroutines to support a flat (single) register window calling |
6340 | convention. */ | |
6341 | ||
6342 | /* Single-register window sparc stack frames look like: | |
6343 | ||
6344 | Before call After call | |
6345 | +-----------------------+ +-----------------------+ | |
86735b02 DE |
6346 | high | | | | |
6347 | mem | caller's temps. | | caller's temps. | | |
c819be5b JW |
6348 | | | | | |
6349 | +-----------------------+ +-----------------------+ | |
6350 | | | | | | |
6351 | | arguments on stack. | | arguments on stack. | | |
86735b02 DE |
6352 | | | | | |
6353 | +-----------------------+FP+92->+-----------------------+ | |
c819be5b JW |
6354 | | 6 words to save | | 6 words to save | |
6355 | | arguments passed | | arguments passed | | |
6356 | | in registers, even | | in registers, even | | |
86735b02 DE |
6357 | | if not passed. | | if not passed. | |
6358 | SP+68->+-----------------------+FP+68->+-----------------------+ | |
6359 | | 1 word struct addr | | 1 word struct addr | | |
6360 | +-----------------------+FP+64->+-----------------------+ | |
6361 | | | | | | |
6362 | | 16 word reg save area | | 16 word reg save area | | |
6363 | | | | | | |
6364 | SP->+-----------------------+ FP->+-----------------------+ | |
6365 | | 4 word area for | | |
6366 | | fp/alu reg moves | | |
6367 | FP-16->+-----------------------+ | |
6368 | | | | |
6369 | | local variables | | |
6370 | | | | |
6371 | +-----------------------+ | |
6372 | | | | |
c819be5b | 6373 | | fp register save | |
86735b02 DE |
6374 | | | |
6375 | +-----------------------+ | |
6376 | | | | |
c819be5b JW |
6377 | | gp register save | |
6378 | | | | |
86735b02 DE |
6379 | +-----------------------+ |
6380 | | | | |
c819be5b | 6381 | | alloca allocations | |
86735b02 DE |
6382 | | | |
6383 | +-----------------------+ | |
6384 | | | | |
c819be5b | 6385 | | arguments on stack | |
86735b02 DE |
6386 | | | |
6387 | SP+92->+-----------------------+ | |
c819be5b | 6388 | | 6 words to save | |
86735b02 | 6389 | | arguments passed | |
c819be5b | 6390 | | in registers, even | |
86735b02 DE |
6391 | low | if not passed. | |
6392 | memory SP+68->+-----------------------+ | |
6393 | | 1 word struct addr | | |
6394 | SP+64->+-----------------------+ | |
6395 | | | | |
6396 | I 16 word reg save area | | |
6397 | | | | |
6398 | SP->+-----------------------+ */ | |
c819be5b | 6399 | |
c6aa9ce1 | 6400 | /* Structure to be filled in by sparc_flat_compute_frame_size with register |
c819be5b JW |
6401 | save masks, and offsets for the current function. */ |
6402 | ||
6403 | struct sparc_frame_info | |
6404 | { | |
6405 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
6406 | unsigned long var_size; /* # bytes that variables take up. */ | |
6407 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
6408 | unsigned long extra_size; /* # bytes of extra gunk. */ | |
6409 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
6410 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 6411 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 6412 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 | 6413 | unsigned long reg_offset; /* Offset from new sp to store regs. */ |
c819be5b JW |
6414 | int initialized; /* Nonzero if frame size already calculated. */ |
6415 | }; | |
6416 | ||
c6aa9ce1 | 6417 | /* Current frame information calculated by sparc_flat_compute_frame_size. */ |
c819be5b JW |
6418 | struct sparc_frame_info current_frame_info; |
6419 | ||
6420 | /* Zero structure to initialize current_frame_info. */ | |
6421 | struct sparc_frame_info zero_frame_info; | |
6422 | ||
6423 | /* Tell prologue and epilogue if register REGNO should be saved / restored. */ | |
6424 | ||
86735b02 DE |
6425 | #define RETURN_ADDR_REGNUM 15 |
6426 | #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM)) | |
6427 | #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) | |
6428 | ||
c819be5b JW |
6429 | #define MUST_SAVE_REGISTER(regno) \ |
6430 | ((regs_ever_live[regno] && !call_used_regs[regno]) \ | |
6431 | || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \ | |
86735b02 | 6432 | || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM])) |
c819be5b JW |
6433 | |
6434 | /* Return the bytes needed to compute the frame pointer from the current | |
6435 | stack pointer. */ | |
6436 | ||
6437 | unsigned long | |
c6aa9ce1 | 6438 | sparc_flat_compute_frame_size (size) |
c819be5b JW |
6439 | int size; /* # of var. bytes allocated. */ |
6440 | { | |
6441 | int regno; | |
6442 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
6443 | unsigned long var_size; /* # bytes that variables take up. */ | |
6444 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
6445 | unsigned long extra_size; /* # extra bytes. */ | |
6446 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
6447 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 6448 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 6449 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 DE |
6450 | unsigned long reg_offset; /* Offset to register save area. */ |
6451 | int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ | |
c819be5b JW |
6452 | |
6453 | /* This is the size of the 16 word reg save area, 1 word struct addr | |
6454 | area, and 4 word fp/alu register copy area. */ | |
8c64be75 SC |
6455 | extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); |
6456 | var_size = size; | |
6457 | gp_reg_size = 0; | |
6458 | fp_reg_size = 0; | |
6459 | gmask = 0; | |
6460 | fmask = 0; | |
6461 | reg_offset = 0; | |
86735b02 | 6462 | need_aligned_p = 0; |
c819be5b | 6463 | |
8c64be75 SC |
6464 | args_size = 0; |
6465 | if (!leaf_function_p ()) | |
6466 | { | |
6467 | /* Also include the size needed for the 6 parameter registers. */ | |
6468 | args_size = current_function_outgoing_args_size + 24; | |
6469 | } | |
6470 | total_size = var_size + args_size; | |
6471 | ||
c819be5b JW |
6472 | /* Calculate space needed for gp registers. */ |
6473 | for (regno = 1; regno <= 31; regno++) | |
6474 | { | |
6475 | if (MUST_SAVE_REGISTER (regno)) | |
6476 | { | |
86735b02 DE |
6477 | /* If we need to save two regs in a row, ensure there's room to bump |
6478 | up the address to align it to a doubleword boundary. */ | |
c819be5b JW |
6479 | if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) |
6480 | { | |
6481 | if (gp_reg_size % 8 != 0) | |
86735b02 | 6482 | gp_reg_size += 4; |
c819be5b | 6483 | gp_reg_size += 2 * UNITS_PER_WORD; |
86735b02 | 6484 | gmask |= 3 << regno; |
c819be5b | 6485 | regno++; |
86735b02 | 6486 | need_aligned_p = 1; |
c819be5b JW |
6487 | } |
6488 | else | |
6489 | { | |
6490 | gp_reg_size += UNITS_PER_WORD; | |
86735b02 | 6491 | gmask |= 1 << regno; |
c819be5b JW |
6492 | } |
6493 | } | |
6494 | } | |
c819be5b JW |
6495 | |
6496 | /* Calculate space needed for fp registers. */ | |
6497 | for (regno = 32; regno <= 63; regno++) | |
6498 | { | |
6499 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
6500 | { | |
6501 | fp_reg_size += UNITS_PER_WORD; | |
6502 | fmask |= 1 << (regno - 32); | |
6503 | } | |
6504 | } | |
6505 | ||
86735b02 DE |
6506 | if (gmask || fmask) |
6507 | { | |
6508 | int n; | |
6509 | reg_offset = FIRST_PARM_OFFSET(0) + args_size; | |
6510 | /* Ensure save area is 8 byte aligned if we need it. */ | |
6511 | n = reg_offset % 8; | |
6512 | if (need_aligned_p && n != 0) | |
6513 | { | |
6514 | total_size += 8 - n; | |
6515 | reg_offset += 8 - n; | |
6516 | } | |
6517 | total_size += gp_reg_size + fp_reg_size; | |
6518 | } | |
c819be5b | 6519 | |
8c64be75 SC |
6520 | /* If we must allocate a stack frame at all, we must also allocate |
6521 | room for register window spillage, so as to be binary compatible | |
6522 | with libraries and operating systems that do not use -mflat. */ | |
6523 | if (total_size > 0) | |
6524 | total_size += extra_size; | |
6525 | else | |
6526 | extra_size = 0; | |
c819be5b JW |
6527 | |
6528 | total_size = SPARC_STACK_ALIGN (total_size); | |
6529 | ||
6530 | /* Save other computed information. */ | |
6531 | current_frame_info.total_size = total_size; | |
6532 | current_frame_info.var_size = var_size; | |
6533 | current_frame_info.args_size = args_size; | |
6534 | current_frame_info.extra_size = extra_size; | |
6535 | current_frame_info.gp_reg_size = gp_reg_size; | |
6536 | current_frame_info.fp_reg_size = fp_reg_size; | |
86735b02 | 6537 | current_frame_info.gmask = gmask; |
c819be5b | 6538 | current_frame_info.fmask = fmask; |
86735b02 | 6539 | current_frame_info.reg_offset = reg_offset; |
c819be5b JW |
6540 | current_frame_info.initialized = reload_completed; |
6541 | ||
c819be5b JW |
6542 | /* Ok, we're done. */ |
6543 | return total_size; | |
6544 | } | |
6545 | \f | |
86735b02 DE |
6546 | /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset |
6547 | OFFSET. | |
6548 | ||
6549 | BASE_REG must be 8 byte aligned. This allows us to test OFFSET for | |
6550 | appropriate alignment and use DOUBLEWORD_OP when we can. We assume | |
6551 | [BASE_REG+OFFSET] will always be a valid address. | |
6552 | ||
6553 | WORD_OP is either "st" for save, "ld" for restore. | |
6554 | DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ | |
c819be5b JW |
6555 | |
6556 | void | |
96987e96 DE |
6557 | sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op, |
6558 | doubleword_op, base_offset) | |
86735b02 | 6559 | FILE *file; |
b1474bb7 | 6560 | const char *base_reg; |
86735b02 DE |
6561 | unsigned int offset; |
6562 | unsigned long gmask; | |
6563 | unsigned long fmask; | |
b1474bb7 KG |
6564 | const char *word_op; |
6565 | const char *doubleword_op; | |
c53aa195 | 6566 | unsigned long base_offset; |
c819be5b JW |
6567 | { |
6568 | int regno; | |
c819be5b | 6569 | |
86735b02 DE |
6570 | if (gmask == 0 && fmask == 0) |
6571 | return; | |
c819be5b | 6572 | |
86735b02 DE |
6573 | /* Save registers starting from high to low. We've already saved the |
6574 | previous frame pointer and previous return address for the debugger's | |
6575 | sake. The debugger allows us to not need a nop in the epilog if at least | |
6576 | one register is reloaded in addition to return address. */ | |
c819be5b | 6577 | |
86735b02 | 6578 | if (gmask) |
c819be5b JW |
6579 | { |
6580 | for (regno = 1; regno <= 31; regno++) | |
6581 | { | |
86735b02 | 6582 | if ((gmask & (1L << regno)) != 0) |
c819be5b | 6583 | { |
86735b02 | 6584 | if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) |
c819be5b | 6585 | { |
86735b02 DE |
6586 | /* We can save two registers in a row. If we're not at a |
6587 | double word boundary, move to one. | |
6588 | sparc_flat_compute_frame_size ensures there's room to do | |
6589 | this. */ | |
6590 | if (offset % 8 != 0) | |
6591 | offset += UNITS_PER_WORD; | |
6592 | ||
c819be5b | 6593 | if (word_op[0] == 's') |
c53aa195 | 6594 | { |
e0d80184 | 6595 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
6596 | doubleword_op, reg_names[regno], |
6597 | base_reg, offset); | |
0021b564 | 6598 | if (dwarf2out_do_frame ()) |
c53aa195 | 6599 | { |
96987e96 | 6600 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
6601 | dwarf2out_reg_save (l, regno, offset + base_offset); |
6602 | dwarf2out_reg_save | |
6603 | (l, regno+1, offset+base_offset + UNITS_PER_WORD); | |
6604 | } | |
c53aa195 | 6605 | } |
c819be5b | 6606 | else |
e0d80184 | 6607 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 6608 | doubleword_op, base_reg, offset, |
c819be5b JW |
6609 | reg_names[regno]); |
6610 | ||
86735b02 | 6611 | offset += 2 * UNITS_PER_WORD; |
c819be5b JW |
6612 | regno++; |
6613 | } | |
6614 | else | |
6615 | { | |
6616 | if (word_op[0] == 's') | |
c53aa195 | 6617 | { |
e0d80184 | 6618 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
6619 | word_op, reg_names[regno], |
6620 | base_reg, offset); | |
0021b564 | 6621 | if (dwarf2out_do_frame ()) |
c53aa195 | 6622 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 6623 | } |
c819be5b | 6624 | else |
e0d80184 | 6625 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 6626 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 6627 | |
86735b02 | 6628 | offset += UNITS_PER_WORD; |
c819be5b JW |
6629 | } |
6630 | } | |
6631 | } | |
6632 | } | |
6633 | ||
6634 | if (fmask) | |
6635 | { | |
6636 | for (regno = 32; regno <= 63; regno++) | |
6637 | { | |
6638 | if ((fmask & (1L << (regno - 32))) != 0) | |
6639 | { | |
6640 | if (word_op[0] == 's') | |
c53aa195 | 6641 | { |
e0d80184 | 6642 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
6643 | word_op, reg_names[regno], |
6644 | base_reg, offset); | |
0021b564 | 6645 | if (dwarf2out_do_frame ()) |
c53aa195 | 6646 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 6647 | } |
c819be5b | 6648 | else |
e0d80184 | 6649 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 6650 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 6651 | |
86735b02 | 6652 | offset += UNITS_PER_WORD; |
c819be5b JW |
6653 | } |
6654 | } | |
6655 | } | |
6656 | } | |
6657 | \f | |
6658 | /* Set up the stack and frame (if desired) for the function. */ | |
6659 | ||
08c148a8 NB |
6660 | static void |
6661 | sparc_flat_function_prologue (file, size) | |
c819be5b | 6662 | FILE *file; |
08c148a8 | 6663 | HOST_WIDE_INT size; |
c819be5b | 6664 | { |
99f44eba | 6665 | const char *sp_str = reg_names[STACK_POINTER_REGNUM]; |
86735b02 | 6666 | unsigned long gmask = current_frame_info.gmask; |
a07c1915 | 6667 | |
1cb36a98 RH |
6668 | sparc_output_scratch_registers (file); |
6669 | ||
c6aa9ce1 | 6670 | /* This is only for the human reader. */ |
bf62bbf1 | 6671 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
5e9defae | 6672 | fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n", |
bf62bbf1 | 6673 | ASM_COMMENT_START, |
86735b02 DE |
6674 | current_frame_info.var_size, |
6675 | current_frame_info.gp_reg_size / 4, | |
9f8b85b8 | 6676 | current_frame_info.fp_reg_size / 4, |
86735b02 DE |
6677 | current_function_outgoing_args_size, |
6678 | current_frame_info.extra_size); | |
c819be5b JW |
6679 | |
6680 | size = SPARC_STACK_ALIGN (size); | |
86735b02 DE |
6681 | size = (! current_frame_info.initialized |
6682 | ? sparc_flat_compute_frame_size (size) | |
6683 | : current_frame_info.total_size); | |
c819be5b | 6684 | |
86735b02 DE |
6685 | /* These cases shouldn't happen. Catch them now. */ |
6686 | if (size == 0 && (gmask || current_frame_info.fmask)) | |
6687 | abort (); | |
c819be5b | 6688 | |
86735b02 DE |
6689 | /* Allocate our stack frame by decrementing %sp. |
6690 | At present, the only algorithm gdb can use to determine if this is a | |
6691 | flat frame is if we always set %i7 if we set %sp. This can be optimized | |
6692 | in the future by putting in some sort of debugging information that says | |
6693 | this is a `flat' function. However, there is still the case of debugging | |
6694 | code without such debugging information (including cases where most fns | |
6695 | have such info, but there is one that doesn't). So, always do this now | |
6696 | so we don't get a lot of code out there that gdb can't handle. | |
6697 | If the frame pointer isn't needn't then that's ok - gdb won't be able to | |
6698 | distinguish us from a non-flat function but there won't (and shouldn't) | |
6699 | be any differences anyway. The return pc is saved (if necessary) right | |
6700 | after %i7 so gdb won't have to look too far to find it. */ | |
6701 | if (size > 0) | |
c819be5b | 6702 | { |
86735b02 | 6703 | unsigned int reg_offset = current_frame_info.reg_offset; |
99f44eba | 6704 | const char *fp_str = reg_names[FRAME_POINTER_REGNUM]; |
3bb5de61 | 6705 | const char *t1_str = "%g1"; |
86735b02 DE |
6706 | |
6707 | /* Things get a little tricky if local variables take up more than ~4096 | |
6708 | bytes and outgoing arguments take up more than ~4096 bytes. When that | |
6709 | happens, the register save area can't be accessed from either end of | |
6710 | the frame. Handle this by decrementing %sp to the start of the gp | |
6711 | register save area, save the regs, update %i7, and then set %sp to its | |
6712 | final value. Given that we only have one scratch register to play | |
6713 | with it is the cheapest solution, and it helps gdb out as it won't | |
6714 | slow down recognition of flat functions. | |
6715 | Don't change the order of insns emitted here without checking with | |
6716 | the gdb folk first. */ | |
6717 | ||
ddd5a7c1 | 6718 | /* Is the entire register save area offsettable from %sp? */ |
fbd039b2 | 6719 | if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) |
86735b02 DE |
6720 | { |
6721 | if (size <= 4096) | |
6722 | { | |
e0d80184 | 6723 | fprintf (file, "\tadd\t%s, %d, %s\n", |
0d587737 | 6724 | sp_str, (int) -size, sp_str); |
86735b02 DE |
6725 | if (gmask & FRAME_POINTER_MASK) |
6726 | { | |
e0d80184 | 6727 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 6728 | fp_str, sp_str, reg_offset); |
e0d80184 | 6729 | fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n", |
0d587737 | 6730 | sp_str, (int) -size, fp_str, ASM_COMMENT_START); |
86735b02 DE |
6731 | reg_offset += 4; |
6732 | } | |
6733 | } | |
6734 | else | |
6735 | { | |
0d587737 KG |
6736 | fprintf (file, "\tset\t"); |
6737 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); | |
6738 | fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", | |
6739 | t1_str, sp_str, t1_str, sp_str); | |
86735b02 DE |
6740 | if (gmask & FRAME_POINTER_MASK) |
6741 | { | |
e0d80184 | 6742 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 6743 | fp_str, sp_str, reg_offset); |
e0d80184 | 6744 | fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
bf62bbf1 | 6745 | sp_str, t1_str, fp_str, ASM_COMMENT_START); |
86735b02 DE |
6746 | reg_offset += 4; |
6747 | } | |
6748 | } | |
0021b564 | 6749 | if (dwarf2out_do_frame ()) |
c53aa195 | 6750 | { |
96987e96 | 6751 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
6752 | if (gmask & FRAME_POINTER_MASK) |
6753 | { | |
6754 | dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, | |
6755 | reg_offset - 4 - size); | |
6756 | dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0); | |
6757 | } | |
6758 | else | |
6759 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size); | |
6760 | } | |
86735b02 DE |
6761 | if (gmask & RETURN_ADDR_MASK) |
6762 | { | |
e0d80184 | 6763 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 6764 | reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); |
0021b564 | 6765 | if (dwarf2out_do_frame ()) |
c53aa195 | 6766 | dwarf2out_return_save ("", reg_offset - size); |
86735b02 DE |
6767 | reg_offset += 4; |
6768 | } | |
6769 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
6770 | gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
6771 | current_frame_info.fmask, | |
84e884e9 | 6772 | "st", "std", -size); |
86735b02 | 6773 | } |
c819be5b | 6774 | else |
86735b02 DE |
6775 | { |
6776 | /* Subtract %sp in two steps, but make sure there is always a | |
6777 | 64 byte register save area, and %sp is properly aligned. */ | |
6778 | /* Amount to decrement %sp by, the first time. */ | |
08c148a8 | 6779 | unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16; |
86735b02 | 6780 | /* Offset to register save area from %sp. */ |
08c148a8 | 6781 | unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset); |
86735b02 DE |
6782 | |
6783 | if (size1 <= 4096) | |
6784 | { | |
e0d80184 | 6785 | fprintf (file, "\tadd\t%s, %d, %s\n", |
0d587737 | 6786 | sp_str, (int) -size1, sp_str); |
86735b02 DE |
6787 | if (gmask & FRAME_POINTER_MASK) |
6788 | { | |
e0d80184 | 6789 | fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n", |
0d587737 KG |
6790 | fp_str, sp_str, (int) offset, sp_str, (int) -size1, |
6791 | fp_str, ASM_COMMENT_START); | |
86735b02 DE |
6792 | offset += 4; |
6793 | } | |
6794 | } | |
6795 | else | |
6796 | { | |
0d587737 KG |
6797 | fprintf (file, "\tset\t"); |
6798 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1); | |
6799 | fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", | |
6800 | t1_str, sp_str, t1_str, sp_str); | |
86735b02 DE |
6801 | if (gmask & FRAME_POINTER_MASK) |
6802 | { | |
e0d80184 | 6803 | fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
0d587737 KG |
6804 | fp_str, sp_str, (int) offset, sp_str, t1_str, |
6805 | fp_str, ASM_COMMENT_START); | |
86735b02 DE |
6806 | offset += 4; |
6807 | } | |
6808 | } | |
0021b564 | 6809 | if (dwarf2out_do_frame ()) |
c53aa195 | 6810 | { |
96987e96 | 6811 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
6812 | if (gmask & FRAME_POINTER_MASK) |
6813 | { | |
6814 | dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, | |
6815 | offset - 4 - size1); | |
6816 | dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0); | |
6817 | } | |
6818 | else | |
6819 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1); | |
6820 | } | |
86735b02 DE |
6821 | if (gmask & RETURN_ADDR_MASK) |
6822 | { | |
e0d80184 | 6823 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
0d587737 | 6824 | reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset); |
0021b564 | 6825 | if (dwarf2out_do_frame ()) |
c53aa195 JM |
6826 | /* offset - size1 == reg_offset - size |
6827 | if reg_offset were updated above like offset. */ | |
6828 | dwarf2out_return_save ("", offset - size1); | |
86735b02 DE |
6829 | offset += 4; |
6830 | } | |
6831 | sparc_flat_save_restore (file, sp_str, offset, | |
6832 | gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
6833 | current_frame_info.fmask, | |
84e884e9 | 6834 | "st", "std", -size1); |
0d587737 KG |
6835 | fprintf (file, "\tset\t"); |
6836 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, size - size1); | |
6837 | fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", | |
6838 | t1_str, sp_str, t1_str, sp_str); | |
0021b564 | 6839 | if (dwarf2out_do_frame ()) |
c53aa195 JM |
6840 | if (! (gmask & FRAME_POINTER_MASK)) |
6841 | dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size); | |
86735b02 | 6842 | } |
c819be5b | 6843 | } |
c6aa9ce1 | 6844 | |
bf62bbf1 | 6845 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
c819be5b JW |
6846 | } |
6847 | \f | |
6848 | /* Do any necessary cleanup after a function to restore stack, frame, | |
6849 | and regs. */ | |
6850 | ||
08c148a8 NB |
6851 | static void |
6852 | sparc_flat_function_epilogue (file, size) | |
c819be5b | 6853 | FILE *file; |
08c148a8 | 6854 | HOST_WIDE_INT size; |
c819be5b | 6855 | { |
c819be5b JW |
6856 | rtx epilogue_delay = current_function_epilogue_delay_list; |
6857 | int noepilogue = FALSE; | |
c819be5b | 6858 | |
c6aa9ce1 | 6859 | /* This is only for the human reader. */ |
bf62bbf1 | 6860 | fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START); |
c6aa9ce1 | 6861 | |
c819be5b JW |
6862 | /* The epilogue does not depend on any registers, but the stack |
6863 | registers, so we assume that if we have 1 pending nop, it can be | |
6864 | ignored, and 2 it must be filled (2 nops occur for integer | |
6865 | multiply and divide). */ | |
6866 | ||
6867 | size = SPARC_STACK_ALIGN (size); | |
86735b02 | 6868 | size = (!current_frame_info.initialized |
c6aa9ce1 | 6869 | ? sparc_flat_compute_frame_size (size) |
c819be5b JW |
6870 | : current_frame_info.total_size); |
6871 | ||
86735b02 | 6872 | if (size == 0 && epilogue_delay == 0) |
c819be5b JW |
6873 | { |
6874 | rtx insn = get_last_insn (); | |
6875 | ||
6876 | /* If the last insn was a BARRIER, we don't have to write any code | |
6877 | because a jump (aka return) was put there. */ | |
6878 | if (GET_CODE (insn) == NOTE) | |
6879 | insn = prev_nonnote_insn (insn); | |
6880 | if (insn && GET_CODE (insn) == BARRIER) | |
6881 | noepilogue = TRUE; | |
6882 | } | |
6883 | ||
6884 | if (!noepilogue) | |
6885 | { | |
08c148a8 NB |
6886 | unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset; |
6887 | unsigned HOST_WIDE_INT size1; | |
99f44eba KG |
6888 | const char *sp_str = reg_names[STACK_POINTER_REGNUM]; |
6889 | const char *fp_str = reg_names[FRAME_POINTER_REGNUM]; | |
3bb5de61 | 6890 | const char *t1_str = "%g1"; |
86735b02 | 6891 | |
c819be5b JW |
6892 | /* In the reload sequence, we don't need to fill the load delay |
6893 | slots for most of the loads, also see if we can fill the final | |
6894 | delay slot if not otherwise filled by the reload sequence. */ | |
6895 | ||
86735b02 | 6896 | if (size > 4095) |
0d587737 KG |
6897 | { |
6898 | fprintf (file, "\tset\t"); | |
6899 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); | |
6900 | fprintf (file, ", %s\n", t1_str); | |
6901 | } | |
c819be5b JW |
6902 | |
6903 | if (frame_pointer_needed) | |
6904 | { | |
86735b02 | 6905 | if (size > 4095) |
e0d80184 | 6906 | fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n", |
bf62bbf1 | 6907 | fp_str, t1_str, sp_str, ASM_COMMENT_START); |
c819be5b | 6908 | else |
e0d80184 | 6909 | fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n", |
0d587737 | 6910 | fp_str, (int) size, sp_str, ASM_COMMENT_START); |
c819be5b JW |
6911 | } |
6912 | ||
ddd5a7c1 | 6913 | /* Is the entire register save area offsettable from %sp? */ |
fbd039b2 | 6914 | if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) |
86735b02 DE |
6915 | { |
6916 | size1 = 0; | |
6917 | } | |
6918 | else | |
6919 | { | |
6920 | /* Restore %sp in two steps, but make sure there is always a | |
6921 | 64 byte register save area, and %sp is properly aligned. */ | |
6922 | /* Amount to increment %sp by, the first time. */ | |
6923 | size1 = ((reg_offset - 64 - 16) + 15) & -16; | |
6924 | /* Offset to register save area from %sp. */ | |
6925 | reg_offset = size1 - reg_offset; | |
6926 | ||
0d587737 KG |
6927 | fprintf (file, "\tset\t"); |
6928 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1); | |
6929 | fprintf (file, ", %s\n\tadd\t%s, %s, %s\n", | |
6930 | t1_str, sp_str, t1_str, sp_str); | |
86735b02 DE |
6931 | } |
6932 | ||
6933 | /* We must restore the frame pointer and return address reg first | |
6934 | because they are treated specially by the prologue output code. */ | |
6935 | if (current_frame_info.gmask & FRAME_POINTER_MASK) | |
6936 | { | |
e0d80184 | 6937 | fprintf (file, "\tld\t[%s+%d], %s\n", |
0d587737 | 6938 | sp_str, (int) reg_offset, fp_str); |
86735b02 DE |
6939 | reg_offset += 4; |
6940 | } | |
6941 | if (current_frame_info.gmask & RETURN_ADDR_MASK) | |
6942 | { | |
e0d80184 | 6943 | fprintf (file, "\tld\t[%s+%d], %s\n", |
0d587737 | 6944 | sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]); |
86735b02 DE |
6945 | reg_offset += 4; |
6946 | } | |
6947 | ||
6948 | /* Restore any remaining saved registers. */ | |
6949 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
6950 | current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
6951 | current_frame_info.fmask, | |
c53aa195 | 6952 | "ld", "ldd", 0); |
86735b02 DE |
6953 | |
6954 | /* If we had to increment %sp in two steps, record it so the second | |
6955 | restoration in the epilogue finishes up. */ | |
6956 | if (size1 > 0) | |
6957 | { | |
6958 | size -= size1; | |
6959 | if (size > 4095) | |
0d587737 KG |
6960 | { |
6961 | fprintf (file, "\tset\t"); | |
6962 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); | |
6963 | fprintf (file, ", %s\n", t1_str); | |
6964 | } | |
86735b02 | 6965 | } |
c819be5b | 6966 | |
c819be5b | 6967 | if (current_function_returns_struct) |
e0d80184 | 6968 | fprintf (file, "\tjmp\t%%o7+12\n"); |
c819be5b JW |
6969 | else |
6970 | fprintf (file, "\tretl\n"); | |
6971 | ||
6972 | /* If the only register saved is the return address, we need a | |
6973 | nop, unless we have an instruction to put into it. Otherwise | |
6974 | we don't since reloading multiple registers doesn't reference | |
6975 | the register being loaded. */ | |
6976 | ||
6977 | if (epilogue_delay) | |
6978 | { | |
86735b02 | 6979 | if (size) |
c819be5b JW |
6980 | abort (); |
6981 | final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); | |
6982 | } | |
6983 | ||
86735b02 | 6984 | else if (size > 4095) |
e0d80184 | 6985 | fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); |
c819be5b | 6986 | |
86735b02 | 6987 | else if (size > 0) |
0d587737 | 6988 | fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str); |
c819be5b JW |
6989 | |
6990 | else | |
6991 | fprintf (file, "\tnop\n"); | |
6992 | } | |
6993 | ||
6994 | /* Reset state info for each function. */ | |
6995 | current_frame_info = zero_frame_info; | |
e0d80184 DM |
6996 | |
6997 | sparc_output_deferred_case_vectors (); | |
c819be5b JW |
6998 | } |
6999 | \f | |
7000 | /* Define the number of delay slots needed for the function epilogue. | |
7001 | ||
7002 | On the sparc, we need a slot if either no stack has been allocated, | |
7003 | or the only register saved is the return register. */ | |
7004 | ||
7005 | int | |
c6aa9ce1 | 7006 | sparc_flat_epilogue_delay_slots () |
c819be5b JW |
7007 | { |
7008 | if (!current_frame_info.initialized) | |
c6aa9ce1 | 7009 | (void) sparc_flat_compute_frame_size (get_frame_size ()); |
c819be5b JW |
7010 | |
7011 | if (current_frame_info.total_size == 0) | |
7012 | return 1; | |
7013 | ||
c819be5b JW |
7014 | return 0; |
7015 | } | |
7016 | ||
51f26c45 | 7017 | /* Return true if TRIAL is a valid insn for the epilogue delay slot. |
c819be5b JW |
7018 | Any single length instruction which doesn't reference the stack or frame |
7019 | pointer is OK. */ | |
7020 | ||
7021 | int | |
c6aa9ce1 | 7022 | sparc_flat_eligible_for_epilogue_delay (trial, slot) |
c819be5b | 7023 | rtx trial; |
db3d4438 | 7024 | int slot ATTRIBUTE_UNUSED; |
c819be5b | 7025 | { |
c4ce6853 DE |
7026 | rtx pat = PATTERN (trial); |
7027 | ||
7028 | if (get_attr_length (trial) != 1) | |
7029 | return 0; | |
7030 | ||
c4ce6853 DE |
7031 | if (! reg_mentioned_p (stack_pointer_rtx, pat) |
7032 | && ! reg_mentioned_p (frame_pointer_rtx, pat)) | |
c819be5b | 7033 | return 1; |
c4ce6853 | 7034 | |
c819be5b JW |
7035 | return 0; |
7036 | } | |
dbb54862 JW |
7037 | \f |
7038 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
7039 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
7040 | ||
8947065c | 7041 | static int |
dbb54862 JW |
7042 | supersparc_adjust_cost (insn, link, dep_insn, cost) |
7043 | rtx insn; | |
7044 | rtx link; | |
7045 | rtx dep_insn; | |
7046 | int cost; | |
7047 | { | |
7048 | enum attr_type insn_type; | |
7049 | ||
7050 | if (! recog_memoized (insn)) | |
7051 | return 0; | |
7052 | ||
7053 | insn_type = get_attr_type (insn); | |
7054 | ||
7055 | if (REG_NOTE_KIND (link) == 0) | |
7056 | { | |
7057 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7058 | cycles later. */ | |
7059 | ||
7060 | /* if a load, then the dependence must be on the memory address; | |
3bc8b61e DM |
7061 | add an extra "cycle". Note that the cost could be two cycles |
7062 | if the reg was written late in an instruction group; we ca not tell | |
dbb54862 JW |
7063 | here. */ |
7064 | if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) | |
7065 | return cost + 3; | |
7066 | ||
7067 | /* Get the delay only if the address of the store is the dependence. */ | |
7068 | if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) | |
7069 | { | |
7070 | rtx pat = PATTERN(insn); | |
7071 | rtx dep_pat = PATTERN (dep_insn); | |
7072 | ||
7073 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
3bc8b61e | 7074 | return cost; /* This should not happen! */ |
dbb54862 JW |
7075 | |
7076 | /* The dependency between the two instructions was on the data that | |
7077 | is being stored. Assume that this implies that the address of the | |
7078 | store is not dependent. */ | |
7079 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
7080 | return cost; | |
7081 | ||
7082 | return cost + 3; /* An approximation. */ | |
7083 | } | |
7084 | ||
7085 | /* A shift instruction cannot receive its data from an instruction | |
7086 | in the same cycle; add a one cycle penalty. */ | |
7087 | if (insn_type == TYPE_SHIFT) | |
7088 | return cost + 3; /* Split before cascade into shift. */ | |
7089 | } | |
7090 | else | |
7091 | { | |
7092 | /* Anti- or output- dependency; DEP_INSN reads/writes a register that | |
7093 | INSN writes some cycles later. */ | |
7094 | ||
7095 | /* These are only significant for the fpu unit; writing a fp reg before | |
7096 | the fpu has finished with it stalls the processor. */ | |
7097 | ||
7098 | /* Reusing an integer register causes no problems. */ | |
7099 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
7100 | return 0; | |
7101 | } | |
7102 | ||
7103 | return cost; | |
7104 | } | |
bfd6bc60 | 7105 | |
8947065c RH |
7106 | static int |
7107 | hypersparc_adjust_cost (insn, link, dep_insn, cost) | |
7108 | rtx insn; | |
7109 | rtx link; | |
7110 | rtx dep_insn; | |
7111 | int cost; | |
7112 | { | |
7113 | enum attr_type insn_type, dep_type; | |
7114 | rtx pat = PATTERN(insn); | |
7115 | rtx dep_pat = PATTERN (dep_insn); | |
7116 | ||
7117 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) | |
7118 | return cost; | |
7119 | ||
7120 | insn_type = get_attr_type (insn); | |
7121 | dep_type = get_attr_type (dep_insn); | |
7122 | ||
7123 | switch (REG_NOTE_KIND (link)) | |
7124 | { | |
7125 | case 0: | |
7126 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7127 | cycles later. */ | |
7128 | ||
7129 | switch (insn_type) | |
7130 | { | |
7131 | case TYPE_STORE: | |
7132 | case TYPE_FPSTORE: | |
7133 | /* Get the delay iff the address of the store is the dependence. */ | |
7134 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
7135 | return cost; | |
7136 | ||
7137 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
7138 | return cost; | |
7139 | return cost + 3; | |
7140 | ||
7141 | case TYPE_LOAD: | |
7142 | case TYPE_SLOAD: | |
7143 | case TYPE_FPLOAD: | |
7144 | /* If a load, then the dependence must be on the memory address. If | |
7145 | the addresses aren't equal, then it might be a false dependency */ | |
7146 | if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) | |
7147 | { | |
7148 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET | |
7149 | || GET_CODE (SET_DEST (dep_pat)) != MEM | |
7150 | || GET_CODE (SET_SRC (pat)) != MEM | |
7151 | || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), | |
7152 | XEXP (SET_SRC (pat), 0))) | |
7153 | return cost + 2; | |
7154 | ||
7155 | return cost + 8; | |
7156 | } | |
7157 | break; | |
7158 | ||
7159 | case TYPE_BRANCH: | |
7160 | /* Compare to branch latency is 0. There is no benefit from | |
7161 | separating compare and branch. */ | |
7162 | if (dep_type == TYPE_COMPARE) | |
7163 | return 0; | |
7164 | /* Floating point compare to branch latency is less than | |
7165 | compare to conditional move. */ | |
7166 | if (dep_type == TYPE_FPCMP) | |
7167 | return cost - 1; | |
7168 | break; | |
3bb5de61 KG |
7169 | default: |
7170 | break; | |
8947065c RH |
7171 | } |
7172 | break; | |
7173 | ||
7174 | case REG_DEP_ANTI: | |
7175 | /* Anti-dependencies only penalize the fpu unit. */ | |
7176 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
7177 | return 0; | |
7178 | break; | |
7179 | ||
7180 | default: | |
7181 | break; | |
7182 | } | |
7183 | ||
7184 | return cost; | |
7185 | } | |
7186 | ||
7187 | static int | |
7188 | ultrasparc_adjust_cost (insn, link, dep_insn, cost) | |
7189 | rtx insn; | |
7190 | rtx link; | |
7191 | rtx dep_insn; | |
7192 | int cost; | |
7193 | { | |
7194 | enum attr_type insn_type, dep_type; | |
7195 | rtx pat = PATTERN(insn); | |
7196 | rtx dep_pat = PATTERN (dep_insn); | |
7197 | ||
7198 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) | |
7199 | return cost; | |
7200 | ||
7201 | insn_type = get_attr_type (insn); | |
7202 | dep_type = get_attr_type (dep_insn); | |
7203 | ||
7204 | /* Nothing issues in parallel with integer multiplies, so | |
7205 | mark as zero cost since the scheduler can not do anything | |
7206 | about it. */ | |
7207 | if (insn_type == TYPE_IMUL) | |
7208 | return 0; | |
7209 | ||
7210 | #define SLOW_FP(dep_type) \ | |
c0ec7a75 DM |
7211 | (dep_type == TYPE_FPSQRTS || dep_type == TYPE_FPSQRTD || \ |
7212 | dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD) | |
8947065c RH |
7213 | |
7214 | switch (REG_NOTE_KIND (link)) | |
7215 | { | |
7216 | case 0: | |
7217 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7218 | cycles later. */ | |
7219 | ||
7220 | if (dep_type == TYPE_CMOVE) | |
7221 | { | |
7222 | /* Instructions that read the result of conditional moves cannot | |
7223 | be in the same group or the following group. */ | |
7224 | return cost + 1; | |
7225 | } | |
7226 | ||
7227 | switch (insn_type) | |
7228 | { | |
7229 | /* UltraSPARC can dual issue a store and an instruction setting | |
7230 | the value stored, except for divide and square root. */ | |
7231 | case TYPE_FPSTORE: | |
7232 | if (! SLOW_FP (dep_type)) | |
7233 | return 0; | |
7234 | return cost; | |
7235 | ||
7236 | case TYPE_STORE: | |
7237 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
7238 | return cost; | |
7239 | ||
7240 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
7241 | /* The dependency between the two instructions is on the data | |
7242 | that is being stored. Assume that the address of the store | |
7243 | is not also dependent. */ | |
7244 | return 0; | |
7245 | return cost; | |
7246 | ||
7247 | case TYPE_LOAD: | |
7248 | case TYPE_SLOAD: | |
7249 | case TYPE_FPLOAD: | |
7250 | /* A load does not return data until at least 11 cycles after | |
7251 | a store to the same location. 3 cycles are accounted for | |
7252 | in the load latency; add the other 8 here. */ | |
7253 | if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) | |
7254 | { | |
7255 | /* If the addresses are not equal this may be a false | |
7256 | dependency because pointer aliasing could not be | |
7257 | determined. Add only 2 cycles in that case. 2 is | |
7258 | an arbitrary compromise between 8, which would cause | |
7259 | the scheduler to generate worse code elsewhere to | |
7260 | compensate for a dependency which might not really | |
7261 | exist, and 0. */ | |
7262 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET | |
7263 | || GET_CODE (SET_SRC (pat)) != MEM | |
7264 | || GET_CODE (SET_DEST (dep_pat)) != MEM | |
7265 | || ! rtx_equal_p (XEXP (SET_SRC (pat), 0), | |
7266 | XEXP (SET_DEST (dep_pat), 0))) | |
7267 | return cost + 2; | |
7268 | ||
7269 | return cost + 8; | |
7270 | } | |
7271 | return cost; | |
7272 | ||
7273 | case TYPE_BRANCH: | |
7274 | /* Compare to branch latency is 0. There is no benefit from | |
7275 | separating compare and branch. */ | |
7276 | if (dep_type == TYPE_COMPARE) | |
7277 | return 0; | |
7278 | /* Floating point compare to branch latency is less than | |
7279 | compare to conditional move. */ | |
7280 | if (dep_type == TYPE_FPCMP) | |
7281 | return cost - 1; | |
7282 | return cost; | |
7283 | ||
7284 | case TYPE_FPCMOVE: | |
7285 | /* FMOVR class instructions can not issue in the same cycle | |
7286 | or the cycle after an instruction which writes any | |
7287 | integer register. Model this as cost 2 for dependent | |
7288 | instructions. */ | |
7fbb2f84 | 7289 | if (dep_type == TYPE_IALU |
8947065c RH |
7290 | && cost < 2) |
7291 | return 2; | |
7292 | /* Otherwise check as for integer conditional moves. */ | |
7293 | ||
7294 | case TYPE_CMOVE: | |
7295 | /* Conditional moves involving integer registers wait until | |
7296 | 3 cycles after loads return data. The interlock applies | |
7297 | to all loads, not just dependent loads, but that is hard | |
7298 | to model. */ | |
7299 | if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD) | |
7300 | return cost + 3; | |
7301 | return cost; | |
7302 | ||
7303 | default: | |
7304 | break; | |
7305 | } | |
7306 | break; | |
7307 | ||
7308 | case REG_DEP_ANTI: | |
7309 | /* Divide and square root lock destination registers for full latency. */ | |
7310 | if (! SLOW_FP (dep_type)) | |
7311 | return 0; | |
7312 | break; | |
7313 | ||
7314 | case REG_DEP_OUTPUT: | |
7315 | /* IEU and FPU instruction that have the same destination | |
7316 | register cannot be grouped together. */ | |
7317 | return cost + 1; | |
7318 | ||
7319 | default: | |
7320 | break; | |
7321 | } | |
7322 | ||
7323 | /* Other costs not accounted for: | |
7324 | - Single precision floating point loads lock the other half of | |
7325 | the even/odd register pair. | |
7326 | - Several hazards associated with ldd/std are ignored because these | |
7327 | instructions are rarely generated for V9. | |
7328 | - The floating point pipeline can not have both a single and double | |
7329 | precision operation active at the same time. Format conversions | |
7330 | and graphics instructions are given honorary double precision status. | |
7331 | - call and jmpl are always the first instruction in a group. */ | |
7332 | ||
7333 | return cost; | |
7334 | ||
7335 | #undef SLOW_FP | |
7336 | } | |
7337 | ||
c237e94a | 7338 | static int |
8947065c RH |
7339 | sparc_adjust_cost(insn, link, dep, cost) |
7340 | rtx insn; | |
7341 | rtx link; | |
7342 | rtx dep; | |
7343 | int cost; | |
7344 | { | |
7345 | switch (sparc_cpu) | |
7346 | { | |
7347 | case PROCESSOR_SUPERSPARC: | |
7348 | cost = supersparc_adjust_cost (insn, link, dep, cost); | |
7349 | break; | |
7350 | case PROCESSOR_HYPERSPARC: | |
7351 | case PROCESSOR_SPARCLITE86X: | |
7352 | cost = hypersparc_adjust_cost (insn, link, dep, cost); | |
7353 | break; | |
7354 | case PROCESSOR_ULTRASPARC: | |
7355 | cost = ultrasparc_adjust_cost (insn, link, dep, cost); | |
7356 | break; | |
7357 | default: | |
7358 | break; | |
7359 | } | |
7360 | return cost; | |
7361 | } | |
7362 | ||
3bc8b61e DM |
7363 | /* This describes the state of the UltraSPARC pipeline during |
7364 | instruction scheduling. */ | |
7365 | ||
b96a5ea5 KG |
7366 | #define TMASK(__x) ((unsigned)1 << ((int)(__x))) |
7367 | #define UMASK(__x) ((unsigned)1 << ((int)(__x))) | |
3bc8b61e DM |
7368 | |
7369 | enum ultra_code { NONE=0, /* no insn at all */ | |
7370 | IEU0, /* shifts and conditional moves */ | |
7371 | IEU1, /* condition code setting insns, calls+jumps */ | |
7372 | IEUN, /* all other single cycle ieu insns */ | |
7373 | LSU, /* loads and stores */ | |
7374 | CTI, /* branches */ | |
7375 | FPM, /* FPU pipeline 1, multiplies and divides */ | |
7376 | FPA, /* FPU pipeline 2, all other operations */ | |
7377 | SINGLE, /* single issue instructions */ | |
7378 | NUM_ULTRA_CODES }; | |
7379 | ||
f6da8bc3 KG |
7380 | static enum ultra_code ultra_code_from_mask PARAMS ((int)); |
7381 | static void ultra_schedule_insn PARAMS ((rtx *, rtx *, int, enum ultra_code)); | |
b1474bb7 | 7382 | |
3bb5de61 | 7383 | static const char *ultra_code_names[NUM_ULTRA_CODES] = { |
3bc8b61e DM |
7384 | "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI", |
7385 | "FPM", "FPA", "SINGLE" }; | |
7386 | ||
7387 | struct ultrasparc_pipeline_state { | |
7388 | /* The insns in this group. */ | |
7389 | rtx group[4]; | |
7390 | ||
7391 | /* The code for each insn. */ | |
7392 | enum ultra_code codes[4]; | |
7393 | ||
7394 | /* Which insns in this group have been committed by the | |
7395 | scheduler. This is how we determine how many more | |
7396 | can issue this cycle. */ | |
7397 | char commit[4]; | |
7398 | ||
7399 | /* How many insns in this group. */ | |
7400 | char group_size; | |
7401 | ||
7402 | /* Mask of free slots still in this group. */ | |
7403 | char free_slot_mask; | |
7404 | ||
7405 | /* The slotter uses the following to determine what other | |
7406 | insn types can still make their way into this group. */ | |
7407 | char contents [NUM_ULTRA_CODES]; | |
7408 | char num_ieu_insns; | |
7409 | }; | |
7410 | ||
7411 | #define ULTRA_NUM_HIST 8 | |
7412 | static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST]; | |
7413 | static int ultra_cur_hist; | |
7414 | static int ultra_cycles_elapsed; | |
7415 | ||
7416 | #define ultra_pipe (ultra_pipe_hist[ultra_cur_hist]) | |
7417 | ||
7418 | /* Given TYPE_MASK compute the ultra_code it has. */ | |
7419 | static enum ultra_code | |
7420 | ultra_code_from_mask (type_mask) | |
7421 | int type_mask; | |
7422 | { | |
3bc8b61e DM |
7423 | if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE))) |
7424 | return IEU0; | |
7425 | else if (type_mask & (TMASK (TYPE_COMPARE) | | |
7426 | TMASK (TYPE_CALL) | | |
7d167afd | 7427 | TMASK (TYPE_SIBCALL) | |
3bc8b61e DM |
7428 | TMASK (TYPE_UNCOND_BRANCH))) |
7429 | return IEU1; | |
7fbb2f84 | 7430 | else if (type_mask & TMASK (TYPE_IALU)) |
3bc8b61e DM |
7431 | return IEUN; |
7432 | else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) | | |
7433 | TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) | | |
7434 | TMASK (TYPE_FPSTORE))) | |
7435 | return LSU; | |
7436 | else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) | | |
c0ec7a75 DM |
7437 | TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRTS) | |
7438 | TMASK (TYPE_FPSQRTD))) | |
3bc8b61e DM |
7439 | return FPM; |
7440 | else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | | |
7441 | TMASK (TYPE_FP) | TMASK (TYPE_FPCMP))) | |
7442 | return FPA; | |
7443 | else if (type_mask & TMASK (TYPE_BRANCH)) | |
7444 | return CTI; | |
7445 | ||
7446 | return SINGLE; | |
7447 | } | |
7448 | ||
7449 | /* Check INSN (a conditional move) and make sure that it's | |
7450 | results are available at this cycle. Return 1 if the | |
7451 | results are in fact ready. */ | |
7452 | static int | |
7453 | ultra_cmove_results_ready_p (insn) | |
7454 | rtx insn; | |
7455 | { | |
7456 | struct ultrasparc_pipeline_state *up; | |
7457 | int entry, slot; | |
7458 | ||
7459 | /* If this got dispatched in the previous | |
7460 | group, the results are not ready. */ | |
1f0e6e28 | 7461 | entry = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
7462 | up = &ultra_pipe_hist[entry]; |
7463 | slot = 4; | |
7464 | while (--slot >= 0) | |
7465 | if (up->group[slot] == insn) | |
c305b1a7 | 7466 | return 0; |
3bc8b61e | 7467 | |
c305b1a7 | 7468 | return 1; |
3bc8b61e DM |
7469 | } |
7470 | ||
7471 | /* Walk backwards in pipeline history looking for FPU | |
7472 | operations which use a mode different than FPMODE and | |
7473 | will create a stall if an insn using FPMODE were to be | |
7474 | dispatched this cycle. */ | |
7475 | static int | |
7476 | ultra_fpmode_conflict_exists (fpmode) | |
7477 | enum machine_mode fpmode; | |
7478 | { | |
7479 | int hist_ent; | |
7480 | int hist_lim; | |
7481 | ||
1f0e6e28 | 7482 | hist_ent = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
7483 | if (ultra_cycles_elapsed < 4) |
7484 | hist_lim = ultra_cycles_elapsed; | |
7485 | else | |
7486 | hist_lim = 4; | |
7487 | while (hist_lim > 0) | |
7488 | { | |
7489 | struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent]; | |
7490 | int slot = 4; | |
7491 | ||
7492 | while (--slot >= 0) | |
7493 | { | |
7494 | rtx insn = up->group[slot]; | |
7495 | enum machine_mode this_mode; | |
3bc8b61e DM |
7496 | rtx pat; |
7497 | ||
7498 | if (! insn | |
7499 | || GET_CODE (insn) != INSN | |
7500 | || (pat = PATTERN (insn)) == 0 | |
7501 | || GET_CODE (pat) != SET) | |
7502 | continue; | |
7503 | ||
7504 | this_mode = GET_MODE (SET_DEST (pat)); | |
7505 | if ((this_mode != SFmode | |
7506 | && this_mode != DFmode) | |
7507 | || this_mode == fpmode) | |
7508 | continue; | |
7509 | ||
7510 | /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then | |
ddf80874 DM |
7511 | we will get a stall. Loads and stores are independant |
7512 | of these rules. */ | |
3bc8b61e DM |
7513 | if (GET_CODE (SET_SRC (pat)) != ABS |
7514 | && GET_CODE (SET_SRC (pat)) != NEG | |
7515 | && ((TMASK (get_attr_type (insn)) & | |
7516 | (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) | | |
c0ec7a75 DM |
7517 | TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRTS) | |
7518 | TMASK (TYPE_FPSQRTD) | | |
ddf80874 | 7519 | TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0)) |
3bc8b61e DM |
7520 | return 1; |
7521 | } | |
7522 | hist_lim--; | |
1f0e6e28 | 7523 | hist_ent = (hist_ent - 1) & (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
7524 | } |
7525 | ||
7526 | /* No conflicts, safe to dispatch. */ | |
7527 | return 0; | |
7528 | } | |
7529 | ||
7530 | /* Find an instruction in LIST which has one of the | |
7531 | type attributes enumerated in TYPE_MASK. START | |
7532 | says where to begin the search. | |
7533 | ||
7534 | NOTE: This scheme depends upon the fact that we | |
7535 | have less than 32 distinct type attributes. */ | |
5a5325cb DM |
7536 | |
7537 | static int ultra_types_avail; | |
7538 | ||
3bc8b61e DM |
7539 | static rtx * |
7540 | ultra_find_type (type_mask, list, start) | |
7541 | int type_mask; | |
7542 | rtx *list; | |
7543 | int start; | |
7544 | { | |
7545 | int i; | |
7546 | ||
5a5325cb DM |
7547 | /* Short circuit if no such insn exists in the ready |
7548 | at the moment. */ | |
7549 | if ((type_mask & ultra_types_avail) == 0) | |
7550 | return 0; | |
7551 | ||
3bc8b61e DM |
7552 | for (i = start; i >= 0; i--) |
7553 | { | |
7554 | rtx insn = list[i]; | |
7555 | ||
7556 | if (recog_memoized (insn) >= 0 | |
7557 | && (TMASK(get_attr_type (insn)) & type_mask)) | |
7558 | { | |
ddf80874 | 7559 | enum machine_mode fpmode = SFmode; |
3bc8b61e DM |
7560 | rtx pat = 0; |
7561 | int slot; | |
7562 | int check_depend = 0; | |
7563 | int check_fpmode_conflict = 0; | |
7564 | ||
7565 | if (GET_CODE (insn) == INSN | |
7566 | && (pat = PATTERN(insn)) != 0 | |
7567 | && GET_CODE (pat) == SET | |
7568 | && !(type_mask & (TMASK (TYPE_STORE) | | |
7569 | TMASK (TYPE_FPSTORE)))) | |
7570 | { | |
7571 | check_depend = 1; | |
7572 | if (GET_MODE (SET_DEST (pat)) == SFmode | |
7573 | || GET_MODE (SET_DEST (pat)) == DFmode) | |
7574 | { | |
7575 | fpmode = GET_MODE (SET_DEST (pat)); | |
7576 | check_fpmode_conflict = 1; | |
7577 | } | |
7578 | } | |
7579 | ||
7580 | slot = 4; | |
7581 | while(--slot >= 0) | |
7582 | { | |
7583 | rtx slot_insn = ultra_pipe.group[slot]; | |
7584 | rtx slot_pat; | |
7585 | ||
7586 | /* Already issued, bad dependency, or FPU | |
7587 | mode conflict. */ | |
7588 | if (slot_insn != 0 | |
7589 | && (slot_pat = PATTERN (slot_insn)) != 0 | |
7590 | && ((insn == slot_insn) | |
7591 | || (check_depend == 1 | |
7592 | && GET_CODE (slot_insn) == INSN | |
7593 | && GET_CODE (slot_pat) == SET | |
5a5325cb DM |
7594 | && ((GET_CODE (SET_DEST (slot_pat)) == REG |
7595 | && GET_CODE (SET_SRC (pat)) == REG | |
7596 | && REGNO (SET_DEST (slot_pat)) == | |
7597 | REGNO (SET_SRC (pat))) | |
7598 | || (GET_CODE (SET_DEST (slot_pat)) == SUBREG | |
7599 | && GET_CODE (SET_SRC (pat)) == SUBREG | |
7600 | && REGNO (SUBREG_REG (SET_DEST (slot_pat))) == | |
7601 | REGNO (SUBREG_REG (SET_SRC (pat))) | |
ddef6bc7 JJ |
7602 | && SUBREG_BYTE (SET_DEST (slot_pat)) == |
7603 | SUBREG_BYTE (SET_SRC (pat))))) | |
3bc8b61e DM |
7604 | || (check_fpmode_conflict == 1 |
7605 | && GET_CODE (slot_insn) == INSN | |
7606 | && GET_CODE (slot_pat) == SET | |
ddf80874 DM |
7607 | && (GET_MODE (SET_DEST (slot_pat)) == SFmode |
7608 | || GET_MODE (SET_DEST (slot_pat)) == DFmode) | |
7609 | && GET_MODE (SET_DEST (slot_pat)) != fpmode))) | |
3bc8b61e DM |
7610 | goto next; |
7611 | } | |
7612 | ||
7613 | /* Check for peculiar result availability and dispatch | |
7614 | interference situations. */ | |
7615 | if (pat != 0 | |
7616 | && ultra_cycles_elapsed > 0) | |
7617 | { | |
7618 | rtx link; | |
7619 | ||
7620 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
7621 | { | |
7622 | rtx link_insn = XEXP (link, 0); | |
7623 | if (GET_CODE (link_insn) == INSN | |
7624 | && recog_memoized (link_insn) >= 0 | |
7625 | && (TMASK (get_attr_type (link_insn)) & | |
7626 | (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE))) | |
7627 | && ! ultra_cmove_results_ready_p (link_insn)) | |
7628 | goto next; | |
7629 | } | |
7630 | ||
7631 | if (check_fpmode_conflict | |
7632 | && ultra_fpmode_conflict_exists (fpmode)) | |
7633 | goto next; | |
7634 | } | |
7635 | ||
7636 | return &list[i]; | |
7637 | } | |
7638 | next: | |
5a5325cb | 7639 | ; |
3bc8b61e DM |
7640 | } |
7641 | return 0; | |
7642 | } | |
7643 | ||
5a5325cb DM |
7644 | static void |
7645 | ultra_build_types_avail (ready, n_ready) | |
7646 | rtx *ready; | |
7647 | int n_ready; | |
7648 | { | |
7649 | int i = n_ready - 1; | |
7650 | ||
7651 | ultra_types_avail = 0; | |
7652 | while(i >= 0) | |
7653 | { | |
7654 | rtx insn = ready[i]; | |
7655 | ||
7656 | if (recog_memoized (insn) >= 0) | |
7657 | ultra_types_avail |= TMASK (get_attr_type (insn)); | |
7658 | ||
7659 | i -= 1; | |
7660 | } | |
7661 | } | |
7662 | ||
3bc8b61e DM |
7663 | /* Place insn pointed to my IP into the pipeline. |
7664 | Make element THIS of READY be that insn if it | |
7665 | is not already. TYPE indicates the pipeline class | |
7666 | this insn falls into. */ | |
7667 | static void | |
7668 | ultra_schedule_insn (ip, ready, this, type) | |
7669 | rtx *ip; | |
7670 | rtx *ready; | |
7671 | int this; | |
7672 | enum ultra_code type; | |
7673 | { | |
7674 | int pipe_slot; | |
7675 | char mask = ultra_pipe.free_slot_mask; | |
c0ec7a75 | 7676 | rtx temp; |
3bc8b61e DM |
7677 | |
7678 | /* Obtain free slot. */ | |
7679 | for (pipe_slot = 0; pipe_slot < 4; pipe_slot++) | |
7680 | if ((mask & (1 << pipe_slot)) != 0) | |
7681 | break; | |
7682 | if (pipe_slot == 4) | |
7683 | abort (); | |
7684 | ||
7685 | /* In it goes, and it hasn't been committed yet. */ | |
7686 | ultra_pipe.group[pipe_slot] = *ip; | |
7687 | ultra_pipe.codes[pipe_slot] = type; | |
7688 | ultra_pipe.contents[type] = 1; | |
7689 | if (UMASK (type) & | |
7690 | (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1))) | |
7691 | ultra_pipe.num_ieu_insns += 1; | |
7692 | ||
7693 | ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot)); | |
7694 | ultra_pipe.group_size += 1; | |
7695 | ultra_pipe.commit[pipe_slot] = 0; | |
7696 | ||
7697 | /* Update ready list. */ | |
c0ec7a75 DM |
7698 | temp = *ip; |
7699 | while (ip != &ready[this]) | |
3bc8b61e | 7700 | { |
c0ec7a75 DM |
7701 | ip[0] = ip[1]; |
7702 | ++ip; | |
3bc8b61e | 7703 | } |
c0ec7a75 | 7704 | *ip = temp; |
3bc8b61e DM |
7705 | } |
7706 | ||
7707 | /* Advance to the next pipeline group. */ | |
7708 | static void | |
7709 | ultra_flush_pipeline () | |
7710 | { | |
1f0e6e28 | 7711 | ultra_cur_hist = (ultra_cur_hist + 1) & (ULTRA_NUM_HIST - 1); |
3bc8b61e | 7712 | ultra_cycles_elapsed += 1; |
2e09e75a | 7713 | memset ((char *) &ultra_pipe, 0, sizeof ultra_pipe); |
3bc8b61e DM |
7714 | ultra_pipe.free_slot_mask = 0xf; |
7715 | } | |
7716 | ||
3bc8b61e | 7717 | /* Init our data structures for this current block. */ |
c237e94a ZW |
7718 | static void |
7719 | ultrasparc_sched_init () | |
3bc8b61e | 7720 | { |
2e09e75a | 7721 | memset ((char *) ultra_pipe_hist, 0, sizeof ultra_pipe_hist); |
3bc8b61e DM |
7722 | ultra_cur_hist = 0; |
7723 | ultra_cycles_elapsed = 0; | |
ddf80874 | 7724 | ultra_pipe.free_slot_mask = 0xf; |
3bc8b61e DM |
7725 | } |
7726 | ||
c237e94a ZW |
7727 | static void |
7728 | sparc_sched_init (dump, sched_verbose, max_ready) | |
7729 | FILE *dump ATTRIBUTE_UNUSED; | |
7730 | int sched_verbose ATTRIBUTE_UNUSED; | |
7731 | int max_ready ATTRIBUTE_UNUSED; | |
7732 | { | |
7733 | if (sparc_cpu == PROCESSOR_ULTRASPARC) | |
7734 | ultrasparc_sched_init (); | |
7735 | } | |
7736 | ||
3bc8b61e DM |
7737 | /* INSN has been scheduled, update pipeline commit state |
7738 | and return how many instructions are still to be | |
7739 | scheduled in this group. */ | |
c237e94a | 7740 | static int |
3bc8b61e DM |
7741 | ultrasparc_variable_issue (insn) |
7742 | rtx insn; | |
7743 | { | |
7744 | struct ultrasparc_pipeline_state *up = &ultra_pipe; | |
7745 | int i, left_to_fire; | |
7746 | ||
7747 | left_to_fire = 0; | |
7748 | for (i = 0; i < 4; i++) | |
7749 | { | |
7750 | if (up->group[i] == 0) | |
7751 | continue; | |
7752 | ||
7753 | if (up->group[i] == insn) | |
7754 | { | |
7755 | up->commit[i] = 1; | |
7756 | } | |
7757 | else if (! up->commit[i]) | |
7758 | left_to_fire++; | |
7759 | } | |
7760 | ||
7761 | return left_to_fire; | |
7762 | } | |
7763 | ||
c237e94a ZW |
7764 | static int |
7765 | sparc_variable_issue (dump, sched_verbose, insn, cim) | |
7766 | FILE *dump ATTRIBUTE_UNUSED; | |
7767 | int sched_verbose ATTRIBUTE_UNUSED; | |
7768 | rtx insn; | |
7769 | int cim; | |
7770 | { | |
7771 | if (sparc_cpu == PROCESSOR_ULTRASPARC) | |
96bd19a7 | 7772 | return ultrasparc_variable_issue (insn); |
c237e94a ZW |
7773 | else |
7774 | return cim - 1; | |
7775 | } | |
7776 | ||
3bc8b61e DM |
7777 | /* In actual_hazard_this_instance, we may have yanked some |
7778 | instructions from the ready list due to conflict cost | |
7779 | adjustments. If so, and such an insn was in our pipeline | |
7780 | group, remove it and update state. */ | |
7781 | static void | |
7782 | ultra_rescan_pipeline_state (ready, n_ready) | |
7783 | rtx *ready; | |
7784 | int n_ready; | |
7785 | { | |
7786 | struct ultrasparc_pipeline_state *up = &ultra_pipe; | |
7787 | int i; | |
7788 | ||
7789 | for (i = 0; i < 4; i++) | |
7790 | { | |
7791 | rtx insn = up->group[i]; | |
3bc8b61e DM |
7792 | int j; |
7793 | ||
7794 | if (! insn) | |
7795 | continue; | |
7796 | ||
7797 | /* If it has been committed, then it was removed from | |
7798 | the ready list because it was actually scheduled, | |
7799 | and that is not the case we are searching for here. */ | |
7800 | if (up->commit[i] != 0) | |
7801 | continue; | |
7802 | ||
7803 | for (j = n_ready - 1; j >= 0; j--) | |
7804 | if (ready[j] == insn) | |
7805 | break; | |
7806 | ||
7807 | /* If we didn't find it, toss it. */ | |
7808 | if (j < 0) | |
7809 | { | |
7810 | enum ultra_code ucode = up->codes[i]; | |
7811 | ||
7812 | up->group[i] = 0; | |
7813 | up->codes[i] = NONE; | |
7814 | up->contents[ucode] = 0; | |
7815 | if (UMASK (ucode) & | |
7816 | (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1))) | |
7817 | up->num_ieu_insns -= 1; | |
7818 | ||
7819 | up->free_slot_mask |= (1 << i); | |
7820 | up->group_size -= 1; | |
7821 | up->commit[i] = 0; | |
7822 | } | |
7823 | } | |
7824 | } | |
7825 | ||
c237e94a | 7826 | static void |
3bc8b61e DM |
7827 | ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready) |
7828 | FILE *dump; | |
7829 | int sched_verbose; | |
7830 | rtx *ready; | |
7831 | int n_ready; | |
7832 | { | |
7833 | struct ultrasparc_pipeline_state *up = &ultra_pipe; | |
7834 | int i, this_insn; | |
7835 | ||
3bc8b61e DM |
7836 | if (sched_verbose) |
7837 | { | |
7838 | int n; | |
7839 | ||
7840 | fprintf (dump, "\n;;\tUltraSPARC Looking at ["); | |
7841 | for (n = n_ready - 1; n >= 0; n--) | |
7842 | { | |
7843 | rtx insn = ready[n]; | |
7844 | enum ultra_code ucode; | |
7845 | ||
7846 | if (recog_memoized (insn) < 0) | |
7847 | continue; | |
7848 | ucode = ultra_code_from_mask (TMASK (get_attr_type (insn))); | |
7849 | if (n != 0) | |
7850 | fprintf (dump, "%s(%d) ", | |
7851 | ultra_code_names[ucode], | |
7852 | INSN_UID (insn)); | |
7853 | else | |
7854 | fprintf (dump, "%s(%d)", | |
7855 | ultra_code_names[ucode], | |
7856 | INSN_UID (insn)); | |
7857 | } | |
7858 | fprintf (dump, "]\n"); | |
7859 | } | |
7860 | ||
7861 | this_insn = n_ready - 1; | |
7862 | ||
7863 | /* Skip over junk we don't understand. */ | |
7864 | while ((this_insn >= 0) | |
7865 | && recog_memoized (ready[this_insn]) < 0) | |
7866 | this_insn--; | |
7867 | ||
5a5325cb DM |
7868 | ultra_build_types_avail (ready, this_insn + 1); |
7869 | ||
3bc8b61e DM |
7870 | while (this_insn >= 0) { |
7871 | int old_group_size = up->group_size; | |
7872 | ||
7873 | if (up->group_size != 0) | |
7874 | { | |
7875 | int num_committed; | |
7876 | ||
7877 | num_committed = (up->commit[0] + up->commit[1] + | |
7878 | up->commit[2] + up->commit[3]); | |
7879 | /* If nothing has been commited from our group, or all of | |
7880 | them have. Clear out the (current cycle's) pipeline | |
7881 | state and start afresh. */ | |
7882 | if (num_committed == 0 | |
7883 | || num_committed == up->group_size) | |
7884 | { | |
ddf80874 DM |
7885 | ultra_flush_pipeline (); |
7886 | up = &ultra_pipe; | |
3bc8b61e DM |
7887 | old_group_size = 0; |
7888 | } | |
7889 | else | |
7890 | { | |
7891 | /* OK, some ready list insns got requeued and thus removed | |
7892 | from the ready list. Account for this fact. */ | |
7893 | ultra_rescan_pipeline_state (ready, n_ready); | |
7894 | ||
7895 | /* Something "changed", make this look like a newly | |
7896 | formed group so the code at the end of the loop | |
7897 | knows that progress was in fact made. */ | |
7898 | if (up->group_size != old_group_size) | |
ddf80874 | 7899 | old_group_size = 0; |
3bc8b61e DM |
7900 | } |
7901 | } | |
7902 | ||
7903 | if (up->group_size == 0) | |
7904 | { | |
7905 | /* If the pipeline is (still) empty and we have any single | |
7906 | group insns, get them out now as this is a good time. */ | |
7fbb2f84 | 7907 | rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | |
3bc8b61e DM |
7908 | TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) | |
7909 | TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)), | |
7910 | ready, this_insn); | |
7911 | if (ip) | |
7912 | { | |
7913 | ultra_schedule_insn (ip, ready, this_insn, SINGLE); | |
7914 | break; | |
7915 | } | |
7916 | ||
7917 | /* If we are not in the process of emptying out the pipe, try to | |
7918 | obtain an instruction which must be the first in it's group. */ | |
7919 | ip = ultra_find_type ((TMASK (TYPE_CALL) | | |
7d167afd | 7920 | TMASK (TYPE_SIBCALL) | |
3bc8b61e DM |
7921 | TMASK (TYPE_CALL_NO_DELAY_SLOT) | |
7922 | TMASK (TYPE_UNCOND_BRANCH)), | |
7923 | ready, this_insn); | |
7924 | if (ip) | |
7925 | { | |
7926 | ultra_schedule_insn (ip, ready, this_insn, IEU1); | |
7927 | this_insn--; | |
7928 | } | |
7929 | else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) | | |
7930 | TMASK (TYPE_FPDIVD) | | |
c0ec7a75 DM |
7931 | TMASK (TYPE_FPSQRTS) | |
7932 | TMASK (TYPE_FPSQRTD)), | |
3bc8b61e DM |
7933 | ready, this_insn)) != 0) |
7934 | { | |
7935 | ultra_schedule_insn (ip, ready, this_insn, FPM); | |
7936 | this_insn--; | |
7937 | } | |
7938 | } | |
7939 | ||
7940 | /* Try to fill the integer pipeline. First, look for an IEU0 specific | |
7941 | operation. We can't do more IEU operations if the first 3 slots are | |
7942 | all full or we have dispatched two IEU insns already. */ | |
7943 | if ((up->free_slot_mask & 0x7) != 0 | |
7944 | && up->num_ieu_insns < 2 | |
7945 | && up->contents[IEU0] == 0 | |
7946 | && up->contents[IEUN] == 0) | |
7947 | { | |
7948 | rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn); | |
7949 | if (ip) | |
7950 | { | |
7951 | ultra_schedule_insn (ip, ready, this_insn, IEU0); | |
7952 | this_insn--; | |
7953 | } | |
7954 | } | |
7955 | ||
7956 | /* If we can, try to find an IEU1 specific or an unnamed | |
7957 | IEU instruction. */ | |
7958 | if ((up->free_slot_mask & 0x7) != 0 | |
7959 | && up->num_ieu_insns < 2) | |
7960 | { | |
7fbb2f84 | 7961 | rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | |
3bc8b61e DM |
7962 | (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)), |
7963 | ready, this_insn); | |
7964 | if (ip) | |
7965 | { | |
7966 | rtx insn = *ip; | |
7967 | ||
7968 | ultra_schedule_insn (ip, ready, this_insn, | |
7969 | (!up->contents[IEU1] | |
7970 | && get_attr_type (insn) == TYPE_COMPARE) | |
7971 | ? IEU1 : IEUN); | |
7972 | this_insn--; | |
7973 | } | |
7974 | } | |
7975 | ||
7976 | /* If only one IEU insn has been found, try to find another unnamed | |
7977 | IEU operation or an IEU1 specific one. */ | |
7978 | if ((up->free_slot_mask & 0x7) != 0 | |
7979 | && up->num_ieu_insns < 2) | |
7980 | { | |
7981 | rtx *ip; | |
7fbb2f84 | 7982 | int tmask = TMASK (TYPE_IALU); |
3bc8b61e DM |
7983 | |
7984 | if (!up->contents[IEU1]) | |
7985 | tmask |= TMASK (TYPE_COMPARE); | |
7986 | ip = ultra_find_type (tmask, ready, this_insn); | |
7987 | if (ip) | |
7988 | { | |
7989 | rtx insn = *ip; | |
7990 | ||
7991 | ultra_schedule_insn (ip, ready, this_insn, | |
7992 | (!up->contents[IEU1] | |
7993 | && get_attr_type (insn) == TYPE_COMPARE) | |
7994 | ? IEU1 : IEUN); | |
7995 | this_insn--; | |
7996 | } | |
7997 | } | |
7998 | ||
7999 | /* Try for a load or store, but such an insn can only be issued | |
8000 | if it is within' one of the first 3 slots. */ | |
8001 | if ((up->free_slot_mask & 0x7) != 0 | |
8002 | && up->contents[LSU] == 0) | |
8003 | { | |
8004 | rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) | | |
8005 | TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) | | |
8006 | TMASK (TYPE_FPSTORE)), ready, this_insn); | |
8007 | if (ip) | |
8008 | { | |
8009 | ultra_schedule_insn (ip, ready, this_insn, LSU); | |
8010 | this_insn--; | |
8011 | } | |
8012 | } | |
8013 | ||
8014 | /* Now find FPU operations, first FPM class. But not divisions or | |
8015 | square-roots because those will break the group up. Unlike all | |
8016 | the previous types, these can go in any slot. */ | |
8017 | if (up->free_slot_mask != 0 | |
8018 | && up->contents[FPM] == 0) | |
8019 | { | |
8020 | rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn); | |
8021 | if (ip) | |
8022 | { | |
8023 | ultra_schedule_insn (ip, ready, this_insn, FPM); | |
8024 | this_insn--; | |
8025 | } | |
8026 | } | |
8027 | ||
8028 | /* Continue on with FPA class if we have not filled the group already. */ | |
8029 | if (up->free_slot_mask != 0 | |
8030 | && up->contents[FPA] == 0) | |
8031 | { | |
8032 | rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | | |
8033 | TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)), | |
8034 | ready, this_insn); | |
8035 | if (ip) | |
8036 | { | |
8037 | ultra_schedule_insn (ip, ready, this_insn, FPA); | |
8038 | this_insn--; | |
8039 | } | |
8040 | } | |
8041 | ||
8042 | /* Finally, maybe stick a branch in here. */ | |
8043 | if (up->free_slot_mask != 0 | |
8044 | && up->contents[CTI] == 0) | |
8045 | { | |
8046 | rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn); | |
8047 | ||
8048 | /* Try to slip in a branch only if it is one of the | |
8049 | next 2 in the ready list. */ | |
8050 | if (ip && ((&ready[this_insn] - ip) < 2)) | |
8051 | { | |
8052 | ultra_schedule_insn (ip, ready, this_insn, CTI); | |
8053 | this_insn--; | |
8054 | } | |
8055 | } | |
8056 | ||
8057 | up->group_size = 0; | |
8058 | for (i = 0; i < 4; i++) | |
8059 | if ((up->free_slot_mask & (1 << i)) == 0) | |
8060 | up->group_size++; | |
8061 | ||
8062 | /* See if we made any progress... */ | |
8063 | if (old_group_size != up->group_size) | |
8064 | break; | |
8065 | ||
8066 | /* Clean out the (current cycle's) pipeline state | |
ddf80874 DM |
8067 | and try once more. If we placed no instructions |
8068 | into the pipeline at all, it means a real hard | |
8069 | conflict exists with some earlier issued instruction | |
8070 | so we must advance to the next cycle to clear it up. */ | |
8071 | if (up->group_size == 0) | |
8072 | { | |
8073 | ultra_flush_pipeline (); | |
8074 | up = &ultra_pipe; | |
8075 | } | |
8076 | else | |
8077 | { | |
2e09e75a | 8078 | memset ((char *) &ultra_pipe, 0, sizeof ultra_pipe); |
ddf80874 DM |
8079 | ultra_pipe.free_slot_mask = 0xf; |
8080 | } | |
3bc8b61e DM |
8081 | } |
8082 | ||
8083 | if (sched_verbose) | |
8084 | { | |
8085 | int n, gsize; | |
8086 | ||
8087 | fprintf (dump, ";;\tUltraSPARC Launched ["); | |
8088 | gsize = up->group_size; | |
8089 | for (n = 0; n < 4; n++) | |
8090 | { | |
8091 | rtx insn = up->group[n]; | |
8092 | ||
8093 | if (! insn) | |
8094 | continue; | |
8095 | ||
8096 | gsize -= 1; | |
8097 | if (gsize != 0) | |
8098 | fprintf (dump, "%s(%d) ", | |
8099 | ultra_code_names[up->codes[n]], | |
8100 | INSN_UID (insn)); | |
8101 | else | |
8102 | fprintf (dump, "%s(%d)", | |
8103 | ultra_code_names[up->codes[n]], | |
8104 | INSN_UID (insn)); | |
8105 | } | |
8106 | fprintf (dump, "]\n"); | |
8107 | } | |
8108 | } | |
8109 | ||
c237e94a ZW |
8110 | static int |
8111 | sparc_sched_reorder (dump, sched_verbose, ready, n_readyp, clock) | |
8112 | FILE *dump; | |
8113 | int sched_verbose; | |
8114 | rtx *ready; | |
8115 | int *n_readyp; | |
0d587737 | 8116 | int clock ATTRIBUTE_UNUSED; |
c237e94a ZW |
8117 | { |
8118 | if (sparc_cpu == PROCESSOR_ULTRASPARC) | |
8119 | ultrasparc_sched_reorder (dump, sched_verbose, ready, *n_readyp); | |
8120 | return sparc_issue_rate (); | |
8121 | } | |
8122 | ||
8123 | static int | |
bfd6bc60 JC |
8124 | sparc_issue_rate () |
8125 | { | |
8126 | switch (sparc_cpu) | |
8127 | { | |
8128 | default: | |
8129 | return 1; | |
bfd6bc60 | 8130 | case PROCESSOR_V9: |
284d86e9 | 8131 | /* Assume V9 processors are capable of at least dual-issue. */ |
bfd6bc60 JC |
8132 | return 2; |
8133 | case PROCESSOR_SUPERSPARC: | |
8134 | return 3; | |
393049a9 RH |
8135 | case PROCESSOR_HYPERSPARC: |
8136 | case PROCESSOR_SPARCLITE86X: | |
8137 | return 2; | |
bfd6bc60 JC |
8138 | case PROCESSOR_ULTRASPARC: |
8139 | return 4; | |
8140 | } | |
8141 | } | |
284d86e9 JC |
8142 | |
8143 | static int | |
4df1190a JJ |
8144 | set_extends (insn) |
8145 | rtx insn; | |
284d86e9 JC |
8146 | { |
8147 | register rtx pat = PATTERN (insn); | |
8148 | ||
8149 | switch (GET_CODE (SET_SRC (pat))) | |
8150 | { | |
8151 | /* Load and some shift instructions zero extend. */ | |
8152 | case MEM: | |
8153 | case ZERO_EXTEND: | |
8154 | /* sethi clears the high bits */ | |
8155 | case HIGH: | |
8156 | /* LO_SUM is used with sethi. sethi cleared the high | |
8157 | bits and the values used with lo_sum are positive */ | |
8158 | case LO_SUM: | |
284d86e9 JC |
8159 | /* Store flag stores 0 or 1 */ |
8160 | case LT: case LTU: | |
8161 | case GT: case GTU: | |
8162 | case LE: case LEU: | |
8163 | case GE: case GEU: | |
8164 | case EQ: | |
8165 | case NE: | |
8166 | return 1; | |
8167 | case AND: | |
8168 | { | |
4df1190a | 8169 | rtx op0 = XEXP (SET_SRC (pat), 0); |
284d86e9 JC |
8170 | rtx op1 = XEXP (SET_SRC (pat), 1); |
8171 | if (GET_CODE (op1) == CONST_INT) | |
8172 | return INTVAL (op1) >= 0; | |
4df1190a JJ |
8173 | if (GET_CODE (op0) != REG) |
8174 | return 0; | |
8175 | if (sparc_check_64 (op0, insn) == 1) | |
284d86e9 | 8176 | return 1; |
4df1190a JJ |
8177 | return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); |
8178 | } | |
8179 | case IOR: | |
8180 | case XOR: | |
8181 | { | |
8182 | rtx op0 = XEXP (SET_SRC (pat), 0); | |
8183 | rtx op1 = XEXP (SET_SRC (pat), 1); | |
8184 | if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) | |
8185 | return 0; | |
8186 | if (GET_CODE (op1) == CONST_INT) | |
8187 | return INTVAL (op1) >= 0; | |
8188 | return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); | |
284d86e9 JC |
8189 | } |
8190 | case ASHIFT: | |
8191 | case LSHIFTRT: | |
8192 | return GET_MODE (SET_SRC (pat)) == SImode; | |
8193 | /* Positive integers leave the high bits zero. */ | |
8194 | case CONST_DOUBLE: | |
4df1190a | 8195 | return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000); |
284d86e9 | 8196 | case CONST_INT: |
4df1190a | 8197 | return ! (INTVAL (SET_SRC (pat)) & 0x80000000); |
284d86e9 JC |
8198 | case ASHIFTRT: |
8199 | case SIGN_EXTEND: | |
8200 | return - (GET_MODE (SET_SRC (pat)) == SImode); | |
4df1190a JJ |
8201 | case REG: |
8202 | return sparc_check_64 (SET_SRC (pat), insn); | |
284d86e9 JC |
8203 | default: |
8204 | return 0; | |
8205 | } | |
8206 | } | |
8207 | ||
e0d80184 DM |
8208 | /* We _ought_ to have only one kind per function, but... */ |
8209 | static rtx sparc_addr_diff_list; | |
8210 | static rtx sparc_addr_list; | |
8211 | ||
8212 | void | |
8213 | sparc_defer_case_vector (lab, vec, diff) | |
8214 | rtx lab, vec; | |
8215 | int diff; | |
8216 | { | |
8217 | vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); | |
8218 | if (diff) | |
8219 | sparc_addr_diff_list | |
8220 | = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); | |
8221 | else | |
8222 | sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); | |
8223 | } | |
8224 | ||
8225 | static void | |
8226 | sparc_output_addr_vec (vec) | |
8227 | rtx vec; | |
8228 | { | |
8229 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
8230 | int idx, vlen = XVECLEN (body, 0); | |
8231 | ||
d1accaa3 JJ |
8232 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
8233 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
8234 | #endif | |
8235 | ||
e0d80184 DM |
8236 | #ifdef ASM_OUTPUT_CASE_LABEL |
8237 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
8238 | NEXT_INSN (lab)); | |
8239 | #else | |
8240 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); | |
8241 | #endif | |
8242 | ||
8243 | for (idx = 0; idx < vlen; idx++) | |
8244 | { | |
8245 | ASM_OUTPUT_ADDR_VEC_ELT | |
8246 | (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); | |
8247 | } | |
d1accaa3 JJ |
8248 | |
8249 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
8250 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
8251 | #endif | |
e0d80184 DM |
8252 | } |
8253 | ||
8254 | static void | |
8255 | sparc_output_addr_diff_vec (vec) | |
8256 | rtx vec; | |
8257 | { | |
8258 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
8259 | rtx base = XEXP (XEXP (body, 0), 0); | |
8260 | int idx, vlen = XVECLEN (body, 1); | |
8261 | ||
d1accaa3 JJ |
8262 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
8263 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
8264 | #endif | |
8265 | ||
e0d80184 DM |
8266 | #ifdef ASM_OUTPUT_CASE_LABEL |
8267 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
8268 | NEXT_INSN (lab)); | |
8269 | #else | |
8270 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); | |
8271 | #endif | |
8272 | ||
8273 | for (idx = 0; idx < vlen; idx++) | |
8274 | { | |
8275 | ASM_OUTPUT_ADDR_DIFF_ELT | |
8276 | (asm_out_file, | |
8277 | body, | |
8278 | CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), | |
8279 | CODE_LABEL_NUMBER (base)); | |
8280 | } | |
d1accaa3 JJ |
8281 | |
8282 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
8283 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
8284 | #endif | |
e0d80184 DM |
8285 | } |
8286 | ||
8287 | static void | |
8288 | sparc_output_deferred_case_vectors () | |
8289 | { | |
8290 | rtx t; | |
d676da68 | 8291 | int align; |
e0d80184 | 8292 | |
f3b8847b DM |
8293 | if (sparc_addr_list == NULL_RTX |
8294 | && sparc_addr_diff_list == NULL_RTX) | |
8295 | return; | |
8296 | ||
e0d80184 DM |
8297 | /* Align to cache line in the function's code section. */ |
8298 | function_section (current_function_decl); | |
d676da68 DM |
8299 | |
8300 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
8301 | if (align > 0) | |
f3b8847b | 8302 | ASM_OUTPUT_ALIGN (asm_out_file, align); |
e0d80184 DM |
8303 | |
8304 | for (t = sparc_addr_list; t ; t = XEXP (t, 1)) | |
8305 | sparc_output_addr_vec (XEXP (t, 0)); | |
8306 | for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) | |
8307 | sparc_output_addr_diff_vec (XEXP (t, 0)); | |
8308 | ||
8309 | sparc_addr_list = sparc_addr_diff_list = NULL_RTX; | |
8310 | } | |
8311 | ||
284d86e9 JC |
8312 | /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are |
8313 | unknown. Return 1 if the high bits are zero, -1 if the register is | |
8314 | sign extended. */ | |
8315 | int | |
8316 | sparc_check_64 (x, insn) | |
8317 | rtx x, insn; | |
8318 | { | |
8319 | /* If a register is set only once it is safe to ignore insns this | |
8320 | code does not know how to handle. The loop will either recognize | |
8321 | the single set and return the correct value or fail to recognize | |
8322 | it and return 0. */ | |
8323 | int set_once = 0; | |
4df1190a JJ |
8324 | rtx y = x; |
8325 | ||
8326 | if (GET_CODE (x) != REG) | |
8327 | abort (); | |
8328 | ||
8329 | if (GET_MODE (x) == DImode) | |
8330 | y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN); | |
284d86e9 | 8331 | |
4df1190a JJ |
8332 | if (flag_expensive_optimizations |
8333 | && REG_N_SETS (REGNO (y)) == 1) | |
284d86e9 JC |
8334 | set_once = 1; |
8335 | ||
8336 | if (insn == 0) | |
d6f4ec51 KG |
8337 | { |
8338 | if (set_once) | |
8339 | insn = get_last_insn_anywhere (); | |
8340 | else | |
8341 | return 0; | |
8342 | } | |
284d86e9 | 8343 | |
d6f4ec51 | 8344 | while ((insn = PREV_INSN (insn))) |
284d86e9 JC |
8345 | { |
8346 | switch (GET_CODE (insn)) | |
8347 | { | |
8348 | case JUMP_INSN: | |
8349 | case NOTE: | |
8350 | break; | |
8351 | case CODE_LABEL: | |
8352 | case CALL_INSN: | |
8353 | default: | |
8354 | if (! set_once) | |
8355 | return 0; | |
8356 | break; | |
8357 | case INSN: | |
8358 | { | |
8359 | rtx pat = PATTERN (insn); | |
8360 | if (GET_CODE (pat) != SET) | |
8361 | return 0; | |
8362 | if (rtx_equal_p (x, SET_DEST (pat))) | |
4df1190a JJ |
8363 | return set_extends (insn); |
8364 | if (y && rtx_equal_p (y, SET_DEST (pat))) | |
8365 | return set_extends (insn); | |
8366 | if (reg_overlap_mentioned_p (SET_DEST (pat), y)) | |
284d86e9 JC |
8367 | return 0; |
8368 | } | |
8369 | } | |
8370 | } | |
8371 | return 0; | |
8372 | } | |
8373 | ||
8374 | char * | |
8375 | sparc_v8plus_shift (operands, insn, opcode) | |
8376 | rtx *operands; | |
8377 | rtx insn; | |
b1474bb7 | 8378 | const char *opcode; |
284d86e9 JC |
8379 | { |
8380 | static char asm_code[60]; | |
8381 | ||
8382 | if (GET_CODE (operands[3]) == SCRATCH) | |
8383 | operands[3] = operands[0]; | |
c6b0465b JC |
8384 | if (GET_CODE (operands[1]) == CONST_INT) |
8385 | { | |
4df1190a | 8386 | output_asm_insn ("mov\t%1, %3", operands); |
c6b0465b JC |
8387 | } |
8388 | else | |
8389 | { | |
4df1190a | 8390 | output_asm_insn ("sllx\t%H1, 32, %3", operands); |
c6b0465b | 8391 | if (sparc_check_64 (operands[1], insn) <= 0) |
4df1190a JJ |
8392 | output_asm_insn ("srl\t%L1, 0, %L1", operands); |
8393 | output_asm_insn ("or\t%L1, %3, %3", operands); | |
c6b0465b | 8394 | } |
284d86e9 JC |
8395 | |
8396 | strcpy(asm_code, opcode); | |
8397 | if (which_alternative != 2) | |
4df1190a | 8398 | return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); |
284d86e9 | 8399 | else |
4df1190a | 8400 | return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"); |
284d86e9 JC |
8401 | } |
8402 | ||
8403 | ||
8404 | /* Return 1 if DEST and SRC reference only global and in registers. */ | |
8405 | ||
8406 | int | |
8407 | sparc_return_peephole_ok (dest, src) | |
8408 | rtx dest, src; | |
8409 | { | |
8410 | if (! TARGET_V9) | |
8411 | return 0; | |
54ff41b7 | 8412 | if (current_function_uses_only_leaf_regs) |
284d86e9 JC |
8413 | return 0; |
8414 | if (GET_CODE (src) != CONST_INT | |
8415 | && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src))) | |
8416 | return 0; | |
8417 | return IN_OR_GLOBAL_P (dest); | |
8418 | } | |
2be15d0f RH |
8419 | \f |
8420 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
8421 | for profiling a function entry. | |
8422 | ||
8423 | 32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered | |
8424 | during profiling so we need to save/restore it around the call to mcount. | |
8425 | We're guaranteed that a save has just been done, and we use the space | |
8426 | allocated for intreg/fpreg value passing. */ | |
8427 | ||
8428 | void | |
8429 | sparc_function_profiler (file, labelno) | |
8430 | FILE *file; | |
8431 | int labelno; | |
8432 | { | |
8433 | char buf[32]; | |
8434 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
8435 | ||
8436 | if (! TARGET_ARCH64) | |
4df1190a | 8437 | fputs ("\tst\t%g2, [%fp-4]\n", file); |
2be15d0f RH |
8438 | |
8439 | fputs ("\tsethi\t%hi(", file); | |
8440 | assemble_name (file, buf); | |
4df1190a | 8441 | fputs ("), %o0\n", file); |
2be15d0f RH |
8442 | |
8443 | fputs ("\tcall\t", file); | |
8444 | assemble_name (file, MCOUNT_FUNCTION); | |
8445 | putc ('\n', file); | |
8446 | ||
4df1190a | 8447 | fputs ("\t or\t%o0, %lo(", file); |
2be15d0f | 8448 | assemble_name (file, buf); |
4df1190a | 8449 | fputs ("), %o0\n", file); |
2be15d0f RH |
8450 | |
8451 | if (! TARGET_ARCH64) | |
4df1190a | 8452 | fputs ("\tld\t[%fp-4], %g2\n", file); |
2be15d0f RH |
8453 | } |
8454 | ||
8455 | ||
8456 | /* The following macro shall output assembler code to FILE | |
8457 | to initialize basic-block profiling. | |
8458 | ||
8459 | If profile_block_flag == 2 | |
8460 | ||
8461 | Output code to call the subroutine `__bb_init_trace_func' | |
8462 | and pass two parameters to it. The first parameter is | |
8463 | the address of a block allocated in the object module. | |
8464 | The second parameter is the number of the first basic block | |
8465 | of the function. | |
8466 | ||
8467 | The name of the block is a local symbol made with this statement: | |
8468 | ||
8469 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); | |
8470 | ||
8471 | Of course, since you are writing the definition of | |
8472 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
8473 | can take a short cut in the definition of this macro and use the | |
8474 | name that you know will result. | |
8475 | ||
8476 | The number of the first basic block of the function is | |
8477 | passed to the macro in BLOCK_OR_LABEL. | |
8478 | ||
8479 | If described in a virtual assembler language the code to be | |
8480 | output looks like: | |
8481 | ||
8482 | parameter1 <- LPBX0 | |
8483 | parameter2 <- BLOCK_OR_LABEL | |
8484 | call __bb_init_trace_func | |
8485 | ||
8486 | else if profile_block_flag != 0 | |
8487 | ||
8488 | Output code to call the subroutine `__bb_init_func' | |
8489 | and pass one single parameter to it, which is the same | |
8490 | as the first parameter to `__bb_init_trace_func'. | |
8491 | ||
8492 | The first word of this parameter is a flag which will be nonzero if | |
8493 | the object module has already been initialized. So test this word | |
8494 | first, and do not call `__bb_init_func' if the flag is nonzero. | |
8495 | Note: When profile_block_flag == 2 the test need not be done | |
8496 | but `__bb_init_trace_func' *must* be called. | |
8497 | ||
8498 | BLOCK_OR_LABEL may be used to generate a label number as a | |
8499 | branch destination in case `__bb_init_func' will not be called. | |
8500 | ||
8501 | If described in a virtual assembler language the code to be | |
8502 | output looks like: | |
8503 | ||
8504 | cmp (LPBX0),0 | |
8505 | jne local_label | |
8506 | parameter1 <- LPBX0 | |
8507 | call __bb_init_func | |
8508 | local_label: | |
8509 | ||
8510 | */ | |
8511 | ||
8512 | void | |
8513 | sparc_function_block_profiler(file, block_or_label) | |
8514 | FILE *file; | |
8515 | int block_or_label; | |
8516 | { | |
8517 | char LPBX[32]; | |
8518 | ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0); | |
8519 | ||
8520 | if (profile_block_flag == 2) | |
8521 | { | |
8522 | fputs ("\tsethi\t%hi(", file); | |
8523 | assemble_name (file, LPBX); | |
4df1190a | 8524 | fputs ("), %o0\n", file); |
2be15d0f | 8525 | |
4df1190a | 8526 | fprintf (file, "\tsethi\t%%hi(%d), %%o1\n", block_or_label); |
2be15d0f | 8527 | |
4df1190a | 8528 | fputs ("\tor\t%o0, %lo(", file); |
2be15d0f | 8529 | assemble_name (file, LPBX); |
4df1190a | 8530 | fputs ("), %o0\n", file); |
2be15d0f RH |
8531 | |
8532 | fprintf (file, "\tcall\t%s__bb_init_trace_func\n", user_label_prefix); | |
8533 | ||
4df1190a | 8534 | fprintf (file, "\t or\t%%o1, %%lo(%d), %%o1\n", block_or_label); |
2be15d0f RH |
8535 | } |
8536 | else if (profile_block_flag != 0) | |
8537 | { | |
8538 | char LPBY[32]; | |
8539 | ASM_GENERATE_INTERNAL_LABEL (LPBY, "LPBY", block_or_label); | |
8540 | ||
8541 | fputs ("\tsethi\t%hi(", file); | |
8542 | assemble_name (file, LPBX); | |
4df1190a | 8543 | fputs ("), %o0\n", file); |
2be15d0f RH |
8544 | |
8545 | fputs ("\tld\t[%lo(", file); | |
8546 | assemble_name (file, LPBX); | |
4df1190a | 8547 | fputs (")+%o0], %o1\n", file); |
2be15d0f RH |
8548 | |
8549 | fputs ("\ttst\t%o1\n", file); | |
8550 | ||
8551 | if (TARGET_V9) | |
8552 | { | |
8553 | fputs ("\tbne,pn\t%icc,", file); | |
8554 | assemble_name (file, LPBY); | |
8555 | putc ('\n', file); | |
8556 | } | |
8557 | else | |
8558 | { | |
8559 | fputs ("\tbne\t", file); | |
8560 | assemble_name (file, LPBY); | |
8561 | putc ('\n', file); | |
8562 | } | |
8563 | ||
4df1190a | 8564 | fputs ("\t or\t%o0, %lo(", file); |
2be15d0f | 8565 | assemble_name (file, LPBX); |
4df1190a | 8566 | fputs ("), %o0\n", file); |
2be15d0f RH |
8567 | |
8568 | fprintf (file, "\tcall\t%s__bb_init_func\n\t nop\n", user_label_prefix); | |
8569 | ||
8570 | ASM_OUTPUT_INTERNAL_LABEL (file, "LPBY", block_or_label); | |
8571 | } | |
8572 | } | |
8573 | ||
8574 | /* The following macro shall output assembler code to FILE | |
8575 | to increment a counter associated with basic block number BLOCKNO. | |
8576 | ||
8577 | If profile_block_flag == 2 | |
8578 | ||
8579 | Output code to initialize the global structure `__bb' and | |
8580 | call the function `__bb_trace_func' which will increment the | |
8581 | counter. | |
8582 | ||
8583 | `__bb' consists of two words. In the first word the number | |
8584 | of the basic block has to be stored. In the second word | |
8585 | the address of a block allocated in the object module | |
8586 | has to be stored. | |
8587 | ||
8588 | The basic block number is given by BLOCKNO. | |
8589 | ||
8590 | The address of the block is given by the label created with | |
8591 | ||
8592 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); | |
8593 | ||
8594 | by FUNCTION_BLOCK_PROFILER. | |
8595 | ||
8596 | Of course, since you are writing the definition of | |
8597 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
8598 | can take a short cut in the definition of this macro and use the | |
8599 | name that you know will result. | |
8600 | ||
8601 | If described in a virtual assembler language the code to be | |
8602 | output looks like: | |
8603 | ||
8604 | move BLOCKNO -> (__bb) | |
8605 | move LPBX0 -> (__bb+4) | |
8606 | call __bb_trace_func | |
8607 | ||
8608 | Note that function `__bb_trace_func' must not change the | |
8609 | machine state, especially the flag register. To grant | |
8610 | this, you must output code to save and restore registers | |
8611 | either in this macro or in the macros MACHINE_STATE_SAVE | |
8612 | and MACHINE_STATE_RESTORE. The last two macros will be | |
8613 | used in the function `__bb_trace_func', so you must make | |
8614 | sure that the function prologue does not change any | |
8615 | register prior to saving it with MACHINE_STATE_SAVE. | |
8616 | ||
8617 | else if profile_block_flag != 0 | |
8618 | ||
8619 | Output code to increment the counter directly. | |
8620 | Basic blocks are numbered separately from zero within each | |
8621 | compiled object module. The count associated with block number | |
8622 | BLOCKNO is at index BLOCKNO in an array of words; the name of | |
8623 | this array is a local symbol made with this statement: | |
8624 | ||
8625 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2); | |
8626 | ||
8627 | Of course, since you are writing the definition of | |
8628 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
8629 | can take a short cut in the definition of this macro and use the | |
8630 | name that you know will result. | |
8631 | ||
8632 | If described in a virtual assembler language, the code to be | |
8633 | output looks like: | |
8634 | ||
8635 | inc (LPBX2+4*BLOCKNO) | |
8636 | ||
8637 | */ | |
8638 | ||
8639 | void | |
8640 | sparc_block_profiler(file, blockno) | |
8641 | FILE *file; | |
8642 | int blockno; | |
8643 | { | |
8644 | char LPBX[32]; | |
a330e73b | 8645 | int bbreg = TARGET_ARCH64 ? 4 : 2; |
2be15d0f RH |
8646 | |
8647 | if (profile_block_flag == 2) | |
8648 | { | |
8649 | ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0); | |
8650 | ||
4df1190a JJ |
8651 | fprintf (file, "\tsethi\t%%hi(%s__bb), %%g1\n", user_label_prefix); |
8652 | fprintf (file, "\tsethi\t%%hi(%d), %%g%d\n", blockno, bbreg); | |
8653 | fprintf (file, "\tor\t%%g1, %%lo(%s__bb), %%g1\n", user_label_prefix); | |
8654 | fprintf (file, "\tor\t%%g%d, %%lo(%d), %%g%d\n", bbreg, blockno, bbreg); | |
2be15d0f | 8655 | |
4df1190a | 8656 | fprintf (file, "\tst\t%%g%d, [%%g1]\n", bbreg); |
2be15d0f RH |
8657 | |
8658 | fputs ("\tsethi\t%hi(", file); | |
8659 | assemble_name (file, LPBX); | |
4df1190a | 8660 | fprintf (file, "), %%g%d\n", bbreg); |
2be15d0f | 8661 | |
4df1190a | 8662 | fputs ("\tor\t%o2, %lo(", file); |
2be15d0f | 8663 | assemble_name (file, LPBX); |
4df1190a | 8664 | fprintf (file, "), %%g%d\n", bbreg); |
2be15d0f | 8665 | |
4df1190a JJ |
8666 | fprintf (file, "\tst\t%%g%d, [%%g1 + 4]\n", bbreg); |
8667 | fprintf (file, "\tmov\t%%o7, %%g%d\n", bbreg); | |
2be15d0f RH |
8668 | |
8669 | fprintf (file, "\tcall\t%s__bb_trace_func\n\t nop\n", user_label_prefix); | |
8670 | ||
4df1190a | 8671 | fprintf (file, "\tmov\t%%g%d, %%o7\n", bbreg); |
2be15d0f RH |
8672 | } |
8673 | else if (profile_block_flag != 0) | |
8674 | { | |
8675 | ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 2); | |
8676 | ||
8677 | fputs ("\tsethi\t%hi(", file); | |
8678 | assemble_name (file, LPBX); | |
4df1190a | 8679 | fprintf (file, "+%d), %%g1\n", blockno*4); |
2be15d0f RH |
8680 | |
8681 | fputs ("\tld\t[%g1+%lo(", file); | |
8682 | assemble_name (file, LPBX); | |
a330e73b | 8683 | if (TARGET_ARCH64 && USE_AS_OFFSETABLE_LO10) |
4df1190a | 8684 | fprintf (file, ")+%d], %%g%d\n", blockno*4, bbreg); |
a330e73b | 8685 | else |
4df1190a | 8686 | fprintf (file, "+%d)], %%g%d\n", blockno*4, bbreg); |
2be15d0f | 8687 | |
4df1190a | 8688 | fprintf (file, "\tadd\t%%g%d, 1, %%g%d\n", bbreg, bbreg); |
2be15d0f | 8689 | |
4df1190a | 8690 | fprintf (file, "\tst\t%%g%d, [%%g1+%%lo(", bbreg); |
2be15d0f | 8691 | assemble_name (file, LPBX); |
a330e73b JJ |
8692 | if (TARGET_ARCH64 && USE_AS_OFFSETABLE_LO10) |
8693 | fprintf (file, ")+%d]\n", blockno*4); | |
8694 | else | |
8695 | fprintf (file, "+%d)]\n", blockno*4); | |
2be15d0f RH |
8696 | } |
8697 | } | |
8698 | ||
8699 | /* The following macro shall output assembler code to FILE | |
8700 | to indicate a return from function during basic-block profiling. | |
8701 | ||
8702 | If profile_block_flag == 2: | |
8703 | ||
8704 | Output assembler code to call function `__bb_trace_ret'. | |
8705 | ||
8706 | Note that function `__bb_trace_ret' must not change the | |
8707 | machine state, especially the flag register. To grant | |
8708 | this, you must output code to save and restore registers | |
8709 | either in this macro or in the macros MACHINE_STATE_SAVE_RET | |
8710 | and MACHINE_STATE_RESTORE_RET. The last two macros will be | |
8711 | used in the function `__bb_trace_ret', so you must make | |
8712 | sure that the function prologue does not change any | |
8713 | register prior to saving it with MACHINE_STATE_SAVE_RET. | |
8714 | ||
8715 | else if profile_block_flag != 0: | |
8716 | ||
8717 | The macro will not be used, so it need not distinguish | |
8718 | these cases. | |
8719 | */ | |
8720 | ||
8721 | void | |
8722 | sparc_function_block_profiler_exit(file) | |
8723 | FILE *file; | |
8724 | { | |
8725 | if (profile_block_flag == 2) | |
8726 | fprintf (file, "\tcall\t%s__bb_trace_ret\n\t nop\n", user_label_prefix); | |
8727 | else | |
8728 | abort (); | |
8729 | } | |
d07d525a MM |
8730 | |
8731 | /* Mark ARG, which is really a struct ultrasparc_pipline_state *, for | |
8732 | GC. */ | |
8733 | ||
8734 | static void | |
8735 | mark_ultrasparc_pipeline_state (arg) | |
8736 | void *arg; | |
8737 | { | |
8738 | struct ultrasparc_pipeline_state *ups; | |
8739 | size_t i; | |
8740 | ||
8741 | ups = (struct ultrasparc_pipeline_state *) arg; | |
8742 | for (i = 0; i < sizeof (ups->group) / sizeof (rtx); ++i) | |
8743 | ggc_mark_rtx (ups->group[i]); | |
8744 | } | |
8745 | ||
8746 | /* Called to register all of our global variables with the garbage | |
8747 | collector. */ | |
8748 | ||
8749 | static void | |
8750 | sparc_add_gc_roots () | |
8751 | { | |
8752 | ggc_add_rtx_root (&sparc_compare_op0, 1); | |
8753 | ggc_add_rtx_root (&sparc_compare_op1, 1); | |
8754 | ggc_add_rtx_root (&leaf_label, 1); | |
8755 | ggc_add_rtx_root (&global_offset_table, 1); | |
8756 | ggc_add_rtx_root (&get_pc_symbol, 1); | |
8757 | ggc_add_rtx_root (&sparc_addr_diff_list, 1); | |
8758 | ggc_add_rtx_root (&sparc_addr_list, 1); | |
b6a1cbae GM |
8759 | ggc_add_root (ultra_pipe_hist, ARRAY_SIZE (ultra_pipe_hist), |
8760 | sizeof (ultra_pipe_hist[0]), &mark_ultrasparc_pipeline_state); | |
d07d525a | 8761 | } |
7c262518 RH |
8762 | |
8763 | static void | |
715bdd29 | 8764 | sparc_elf_asm_named_section (name, flags) |
7c262518 RH |
8765 | const char *name; |
8766 | unsigned int flags; | |
7c262518 | 8767 | { |
201556f0 JJ |
8768 | if (flags & SECTION_MERGE) |
8769 | { | |
8770 | /* entsize cannot be expressed in this section attributes | |
8771 | encoding style. */ | |
8772 | default_elf_asm_named_section (name, flags); | |
8773 | return; | |
8774 | } | |
8775 | ||
7c262518 RH |
8776 | fprintf (asm_out_file, "\t.section\t\"%s\"", name); |
8777 | ||
8778 | if (!(flags & SECTION_DEBUG)) | |
8779 | fputs (",#alloc", asm_out_file); | |
8780 | if (flags & SECTION_WRITE) | |
8781 | fputs (",#write", asm_out_file); | |
8782 | if (flags & SECTION_CODE) | |
8783 | fputs (",#execinstr", asm_out_file); | |
8784 | ||
8785 | /* ??? Handle SECTION_BSS. */ | |
8786 | ||
8787 | fputc ('\n', asm_out_file); | |
8788 | } |