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c3427c7d | 1 | /* Subroutines for insn-output.c for SPARC. |
4592bdcb | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
5cfc5f84 | 3 | 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
ab835497 | 4 | Contributed by Michael Tiemann (tiemann@cygnus.com) |
c3427c7d | 5 | 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
61a55e8b | 6 | at Cygnus Support. |
ab835497 | 7 | |
4d8af13f | 8 | This file is part of GCC. |
ab835497 | 9 | |
4d8af13f | 10 | GCC is free software; you can redistribute it and/or modify |
ab835497 RK |
11 | it under the terms of the GNU General Public License as published by |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
4d8af13f | 15 | GCC is distributed in the hope that it will be useful, |
ab835497 RK |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
4d8af13f | 21 | along with GCC; see the file COPYING. If not, write to |
c15c9075 RK |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, |
23 | Boston, MA 02111-1307, USA. */ | |
ab835497 | 24 | |
ab835497 | 25 | #include "config.h" |
284d86e9 | 26 | #include "system.h" |
4977bab6 ZW |
27 | #include "coretypes.h" |
28 | #include "tm.h" | |
210aa14a | 29 | #include "tree.h" |
ab835497 RK |
30 | #include "rtl.h" |
31 | #include "regs.h" | |
32 | #include "hard-reg-set.h" | |
33 | #include "real.h" | |
34 | #include "insn-config.h" | |
35 | #include "conditions.h" | |
ab835497 RK |
36 | #include "output.h" |
37 | #include "insn-attr.h" | |
38 | #include "flags.h" | |
49ad7cfa | 39 | #include "function.h" |
ab835497 | 40 | #include "expr.h" |
e78d8e51 | 41 | #include "optabs.h" |
ab835497 | 42 | #include "recog.h" |
487a6e06 | 43 | #include "toplev.h" |
d07d525a | 44 | #include "ggc.h" |
b1474bb7 | 45 | #include "tm_p.h" |
e78d8e51 | 46 | #include "debug.h" |
672a6f42 NB |
47 | #include "target.h" |
48 | #include "target-def.h" | |
117dca74 | 49 | #include "cfglayout.h" |
ab835497 | 50 | |
61a55e8b DE |
51 | /* 1 if the caller has placed an "unimp" insn immediately after the call. |
52 | This is used in v8 code when calling a function that returns a structure. | |
06b967f9 RK |
53 | v9 doesn't have this. Be careful to have this test be the same as that |
54 | used on the call. */ | |
55 | ||
56 | #define SKIP_CALLERS_UNIMP_P \ | |
57 | (!TARGET_ARCH64 && current_function_returns_struct \ | |
58 | && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
59 | && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
60 | == INTEGER_CST)) | |
61a55e8b | 61 | |
ab835497 RK |
62 | /* Global variables for machine-dependent things. */ |
63 | ||
61a55e8b DE |
64 | /* Size of frame. Need to know this to emit return insns from leaf procedures. |
65 | ACTUAL_FSIZE is set by compute_frame_size() which is called during the | |
66 | reload pass. This is important as the value is later used in insn | |
67 | scheduling (to see what can go in a delay slot). | |
68 | APPARENT_FSIZE is the size of the stack less the register save area and less | |
69 | the outgoing argument area. It is used when saving call preserved regs. */ | |
6a151f87 EB |
70 | static HOST_WIDE_INT apparent_fsize; |
71 | static HOST_WIDE_INT actual_fsize; | |
61a55e8b | 72 | |
33074e5f RH |
73 | /* Number of live general or floating point registers needed to be |
74 | saved (as 4-byte quantities). */ | |
e48addee JJ |
75 | static int num_gfregs; |
76 | ||
ab835497 RK |
77 | /* Save the operands last given to a compare for use when we |
78 | generate a scc or bcc insn. */ | |
ab835497 RK |
79 | rtx sparc_compare_op0, sparc_compare_op1; |
80 | ||
33074e5f RH |
81 | /* Coordinate with the md file wrt special insns created by |
82 | sparc_nonflat_function_epilogue. */ | |
83 | bool sparc_emitting_epilogue; | |
ab835497 | 84 | |
563c12b0 RH |
85 | /* Vector to say how input registers are mapped to output registers. |
86 | HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to | |
87 | eliminate it. You must use -fomit-frame-pointer to get that. */ | |
d70e94ec | 88 | char leaf_reg_remap[] = |
ab835497 RK |
89 | { 0, 1, 2, 3, 4, 5, 6, 7, |
90 | -1, -1, -1, -1, -1, -1, 14, -1, | |
91 | -1, -1, -1, -1, -1, -1, -1, -1, | |
92 | 8, 9, 10, 11, 12, 13, -1, 15, | |
93 | ||
94 | 32, 33, 34, 35, 36, 37, 38, 39, | |
95 | 40, 41, 42, 43, 44, 45, 46, 47, | |
96 | 48, 49, 50, 51, 52, 53, 54, 55, | |
61a55e8b DE |
97 | 56, 57, 58, 59, 60, 61, 62, 63, |
98 | 64, 65, 66, 67, 68, 69, 70, 71, | |
99 | 72, 73, 74, 75, 76, 77, 78, 79, | |
100 | 80, 81, 82, 83, 84, 85, 86, 87, | |
101 | 88, 89, 90, 91, 92, 93, 94, 95, | |
c4ce6853 | 102 | 96, 97, 98, 99, 100}; |
ab835497 | 103 | |
7d167afd JJ |
104 | /* Vector, indexed by hard register number, which contains 1 |
105 | for a register that is allowable in a candidate for leaf | |
106 | function treatment. */ | |
107 | char sparc_leaf_regs[] = | |
108 | { 1, 1, 1, 1, 1, 1, 1, 1, | |
109 | 0, 0, 0, 0, 0, 0, 1, 0, | |
110 | 0, 0, 0, 0, 0, 0, 0, 0, | |
111 | 1, 1, 1, 1, 1, 1, 0, 1, | |
112 | 1, 1, 1, 1, 1, 1, 1, 1, | |
113 | 1, 1, 1, 1, 1, 1, 1, 1, | |
114 | 1, 1, 1, 1, 1, 1, 1, 1, | |
115 | 1, 1, 1, 1, 1, 1, 1, 1, | |
116 | 1, 1, 1, 1, 1, 1, 1, 1, | |
117 | 1, 1, 1, 1, 1, 1, 1, 1, | |
118 | 1, 1, 1, 1, 1, 1, 1, 1, | |
119 | 1, 1, 1, 1, 1, 1, 1, 1, | |
120 | 1, 1, 1, 1, 1}; | |
121 | ||
5751a10b JJ |
122 | struct machine_function GTY(()) |
123 | { | |
124 | /* Some local-dynamic TLS symbol name. */ | |
125 | const char *some_ld_name; | |
126 | }; | |
127 | ||
ab835497 RK |
128 | /* Name of where we pretend to think the frame pointer points. |
129 | Normally, this is "%fp", but if we are in a leaf procedure, | |
61a55e8b DE |
130 | this is "%sp+something". We record "something" separately as it may be |
131 | too big for reg+constant addressing. */ | |
132 | ||
3bb5de61 | 133 | static const char *frame_base_name; |
6a151f87 | 134 | static HOST_WIDE_INT frame_base_offset; |
ab835497 | 135 | |
e80d5f80 | 136 | static void sparc_init_modes (void); |
6a151f87 | 137 | static int save_regs (FILE *, int, int, const char *, int, int, HOST_WIDE_INT); |
e80d5f80 | 138 | static int restore_regs (FILE *, int, int, const char *, int, int); |
6a151f87 | 139 | static void build_big_number (FILE *, HOST_WIDE_INT, const char *); |
e80d5f80 KG |
140 | static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode, |
141 | tree, int, int, int *, int *); | |
142 | ||
143 | static int supersparc_adjust_cost (rtx, rtx, rtx, int); | |
144 | static int hypersparc_adjust_cost (rtx, rtx, rtx, int); | |
145 | ||
146 | static void sparc_output_addr_vec (rtx); | |
147 | static void sparc_output_addr_diff_vec (rtx); | |
148 | static void sparc_output_deferred_case_vectors (void); | |
149 | static int check_return_regs (rtx); | |
150 | static int epilogue_renumber (rtx *, int); | |
151 | static bool sparc_assemble_integer (rtx, unsigned int, int); | |
152 | static int set_extends (rtx); | |
153 | static void output_restore_regs (FILE *, int); | |
154 | static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT); | |
155 | static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
156 | static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT); | |
157 | static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT); | |
6a151f87 EB |
158 | static void sparc_flat_save_restore (FILE *, const char *, int, |
159 | unsigned long, unsigned long, | |
160 | const char *, const char *, | |
161 | HOST_WIDE_INT); | |
e80d5f80 KG |
162 | static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int); |
163 | static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int); | |
ede75ee8 | 164 | #ifdef OBJECT_FORMAT_ELF |
e80d5f80 | 165 | static void sparc_elf_asm_named_section (const char *, unsigned int); |
ede75ee8 | 166 | #endif |
e80d5f80 | 167 | static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT) |
ae46c4e0 | 168 | ATTRIBUTE_UNUSED; |
e80d5f80 KG |
169 | static void sparc_aout_select_rtx_section (enum machine_mode, rtx, |
170 | unsigned HOST_WIDE_INT) | |
b64a1b53 | 171 | ATTRIBUTE_UNUSED; |
c237e94a | 172 | |
e80d5f80 KG |
173 | static int sparc_adjust_cost (rtx, rtx, rtx, int); |
174 | static int sparc_issue_rate (void); | |
175 | static void sparc_sched_init (FILE *, int, int); | |
176 | static int sparc_use_dfa_pipeline_interface (void); | |
177 | static int sparc_use_sched_lookahead (void); | |
178 | ||
179 | static void emit_soft_tfmode_libcall (const char *, int, rtx *); | |
180 | static void emit_soft_tfmode_binop (enum rtx_code, rtx *); | |
181 | static void emit_soft_tfmode_unop (enum rtx_code, rtx *); | |
182 | static void emit_soft_tfmode_cvt (enum rtx_code, rtx *); | |
183 | static void emit_hard_tfmode_operation (enum rtx_code, rtx *); | |
184 | ||
185 | static bool sparc_function_ok_for_sibcall (tree, tree); | |
c15c90bb | 186 | static void sparc_init_libfuncs (void); |
e80d5f80 KG |
187 | static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
188 | HOST_WIDE_INT, tree); | |
5751a10b JJ |
189 | static struct machine_function * sparc_init_machine_status (void); |
190 | static bool sparc_cannot_force_const_mem (rtx); | |
191 | static rtx sparc_tls_get_addr (void); | |
192 | static rtx sparc_tls_got (void); | |
193 | static const char *get_some_local_dynamic_name (void); | |
194 | static int get_some_local_dynamic_name_1 (rtx *, void *); | |
e80d5f80 | 195 | static bool sparc_rtx_costs (rtx, int, int, int *); |
61a55e8b DE |
196 | \f |
197 | /* Option handling. */ | |
198 | ||
a0a301fc | 199 | /* Code model option as passed by user. */ |
3bb5de61 | 200 | const char *sparc_cmodel_string; |
a0a301fc DE |
201 | /* Parsed value. */ |
202 | enum cmodel sparc_cmodel; | |
203 | ||
1cb36a98 RH |
204 | char sparc_hard_reg_printed[8]; |
205 | ||
16956f6e DE |
206 | struct sparc_cpu_select sparc_select[] = |
207 | { | |
208 | /* switch name, tune arch */ | |
209 | { (char *)0, "default", 1, 1 }, | |
210 | { (char *)0, "-mcpu=", 1, 1 }, | |
211 | { (char *)0, "-mtune=", 1, 0 }, | |
db3d4438 | 212 | { 0, 0, 0, 0 } |
16956f6e | 213 | }; |
733f53f5 | 214 | |
16956f6e DE |
215 | /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ |
216 | enum processor_type sparc_cpu; | |
672a6f42 NB |
217 | \f |
218 | /* Initialize the GCC target structure. */ | |
301d03af RS |
219 | |
220 | /* The sparc default is to use .half rather than .short for aligned | |
221 | HI objects. Use .word instead of .long on non-ELF systems. */ | |
222 | #undef TARGET_ASM_ALIGNED_HI_OP | |
223 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
224 | #ifndef OBJECT_FORMAT_ELF | |
225 | #undef TARGET_ASM_ALIGNED_SI_OP | |
226 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
227 | #endif | |
228 | ||
229 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
230 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t" | |
231 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
232 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t" | |
233 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
234 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t" | |
235 | ||
236 | /* The target hook has to handle DI-mode values. */ | |
237 | #undef TARGET_ASM_INTEGER | |
238 | #define TARGET_ASM_INTEGER sparc_assemble_integer | |
239 | ||
08c148a8 NB |
240 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
241 | #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue | |
242 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
243 | #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue | |
733f53f5 | 244 | |
c237e94a ZW |
245 | #undef TARGET_SCHED_ADJUST_COST |
246 | #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost | |
247 | #undef TARGET_SCHED_ISSUE_RATE | |
248 | #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate | |
c237e94a ZW |
249 | #undef TARGET_SCHED_INIT |
250 | #define TARGET_SCHED_INIT sparc_sched_init | |
fae15c93 VM |
251 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE |
252 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface | |
253 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD | |
254 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead | |
c237e94a | 255 | |
4977bab6 ZW |
256 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
257 | #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall | |
258 | ||
c15c90bb ZW |
259 | #undef TARGET_INIT_LIBFUNCS |
260 | #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs | |
261 | ||
5751a10b JJ |
262 | #ifdef HAVE_AS_TLS |
263 | #undef TARGET_HAVE_TLS | |
264 | #define TARGET_HAVE_TLS true | |
265 | #endif | |
266 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
267 | #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem | |
268 | ||
c590b625 RH |
269 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
270 | #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk | |
3961e8fe RH |
271 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
272 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 273 | |
3c50106f RH |
274 | #undef TARGET_RTX_COSTS |
275 | #define TARGET_RTX_COSTS sparc_rtx_costs | |
dcefdf67 RH |
276 | #undef TARGET_ADDRESS_COST |
277 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
3c50106f | 278 | |
f6897b10 | 279 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 280 | \f |
61a55e8b DE |
281 | /* Validate and override various options, and do some machine dependent |
282 | initialization. */ | |
283 | ||
284 | void | |
fc27d102 | 285 | sparc_override_options (void) |
61a55e8b | 286 | { |
a0a301fc | 287 | static struct code_model { |
8b60264b KG |
288 | const char *const name; |
289 | const int value; | |
290 | } const cmodels[] = { | |
a0a301fc DE |
291 | { "32", CM_32 }, |
292 | { "medlow", CM_MEDLOW }, | |
293 | { "medmid", CM_MEDMID }, | |
294 | { "medany", CM_MEDANY }, | |
295 | { "embmedany", CM_EMBMEDANY }, | |
296 | { 0, 0 } | |
297 | }; | |
8b60264b | 298 | const struct code_model *cmodel; |
16956f6e | 299 | /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ |
733f53f5 | 300 | static struct cpu_default { |
8b60264b KG |
301 | const int cpu; |
302 | const char *const name; | |
303 | } const cpu_default[] = { | |
a0a301fc | 304 | /* There must be one entry here for each TARGET_CPU value. */ |
16956f6e | 305 | { TARGET_CPU_sparc, "cypress" }, |
3592ea0d | 306 | { TARGET_CPU_sparclet, "tsc701" }, |
16956f6e | 307 | { TARGET_CPU_sparclite, "f930" }, |
a0a301fc | 308 | { TARGET_CPU_v8, "v8" }, |
8947065c RH |
309 | { TARGET_CPU_hypersparc, "hypersparc" }, |
310 | { TARGET_CPU_sparclite86x, "sparclite86x" }, | |
a0a301fc DE |
311 | { TARGET_CPU_supersparc, "supersparc" }, |
312 | { TARGET_CPU_v9, "v9" }, | |
ba542005 | 313 | { TARGET_CPU_ultrasparc, "ultrasparc" }, |
fae15c93 | 314 | { TARGET_CPU_ultrasparc3, "ultrasparc3" }, |
db3d4438 | 315 | { 0, 0 } |
733f53f5 | 316 | }; |
8b60264b | 317 | const struct cpu_default *def; |
16956f6e | 318 | /* Table of values for -m{cpu,tune}=. */ |
733f53f5 | 319 | static struct cpu_table { |
8b60264b KG |
320 | const char *const name; |
321 | const enum processor_type processor; | |
322 | const int disable; | |
323 | const int enable; | |
324 | } const cpu_table[] = { | |
16956f6e DE |
325 | { "v7", PROCESSOR_V7, MASK_ISA, 0 }, |
326 | { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, | |
327 | { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, | |
733f53f5 | 328 | /* TI TMS390Z55 supersparc */ |
16956f6e DE |
329 | { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, |
330 | { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, | |
733f53f5 DE |
331 | /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. |
332 | The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ | |
16956f6e DE |
333 | { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, |
334 | { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, | |
8947065c | 335 | { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, |
d3ec6b06 VM |
336 | { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, |
337 | MASK_SPARCLITE }, | |
16956f6e | 338 | { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, |
733f53f5 | 339 | /* TEMIC sparclet */ |
3592ea0d | 340 | { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, |
16956f6e | 341 | { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, |
5cb01b65 JJ |
342 | /* TI ultrasparc I, II, IIi */ |
343 | { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 | |
344 | /* Although insns using %y are deprecated, it is a clear win on current | |
80ffc95e | 345 | ultrasparcs. */ |
3276910d | 346 | |MASK_DEPRECATED_V8_INSNS}, |
fae15c93 VM |
347 | /* TI ultrasparc III */ |
348 | /* ??? Check if %y issue still holds true in ultra3. */ | |
349 | { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, | |
db3d4438 | 350 | { 0, 0, 0, 0 } |
733f53f5 | 351 | }; |
8b60264b KG |
352 | const struct cpu_table *cpu; |
353 | const struct sparc_cpu_select *sel; | |
a0a301fc | 354 | int fpu; |
345a6161 | 355 | |
a0a301fc DE |
356 | #ifndef SPARC_BI_ARCH |
357 | /* Check for unsupported architecture size. */ | |
358 | if (! TARGET_64BIT != DEFAULT_ARCH32_P) | |
3276910d RK |
359 | error ("%s is not supported by this configuration", |
360 | DEFAULT_ARCH32_P ? "-m64" : "-m32"); | |
a0a301fc DE |
361 | #endif |
362 | ||
4710d3eb JJ |
363 | /* We force all 64bit archs to use 128 bit long double */ |
364 | if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128) | |
365 | { | |
366 | error ("-mlong-double-64 not allowed with -m64"); | |
367 | target_flags |= MASK_LONG_DOUBLE_128; | |
368 | } | |
369 | ||
a0a301fc DE |
370 | /* Code model selection. */ |
371 | sparc_cmodel = SPARC_DEFAULT_CMODEL; | |
345a6161 DM |
372 | |
373 | #ifdef SPARC_BI_ARCH | |
374 | if (TARGET_ARCH32) | |
375 | sparc_cmodel = CM_32; | |
376 | #endif | |
377 | ||
a0a301fc DE |
378 | if (sparc_cmodel_string != NULL) |
379 | { | |
380 | if (TARGET_ARCH64) | |
381 | { | |
382 | for (cmodel = &cmodels[0]; cmodel->name; cmodel++) | |
383 | if (strcmp (sparc_cmodel_string, cmodel->name) == 0) | |
384 | break; | |
385 | if (cmodel->name == NULL) | |
386 | error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); | |
387 | else | |
388 | sparc_cmodel = cmodel->value; | |
389 | } | |
390 | else | |
391 | error ("-mcmodel= is not supported on 32 bit systems"); | |
392 | } | |
16956f6e | 393 | |
a0a301fc | 394 | fpu = TARGET_FPU; /* save current -mfpu status */ |
1f1406b4 | 395 | |
a0a301fc | 396 | /* Set the default CPU. */ |
16956f6e DE |
397 | for (def = &cpu_default[0]; def->name; ++def) |
398 | if (def->cpu == TARGET_CPU_DEFAULT) | |
399 | break; | |
400 | if (! def->name) | |
401 | abort (); | |
402 | sparc_select[0].string = def->name; | |
403 | ||
404 | for (sel = &sparc_select[0]; sel->name; ++sel) | |
61a55e8b | 405 | { |
16956f6e | 406 | if (sel->string) |
733f53f5 | 407 | { |
16956f6e DE |
408 | for (cpu = &cpu_table[0]; cpu->name; ++cpu) |
409 | if (! strcmp (sel->string, cpu->name)) | |
410 | { | |
411 | if (sel->set_tune_p) | |
412 | sparc_cpu = cpu->processor; | |
413 | ||
414 | if (sel->set_arch_p) | |
415 | { | |
416 | target_flags &= ~cpu->disable; | |
417 | target_flags |= cpu->enable; | |
418 | } | |
419 | break; | |
420 | } | |
421 | ||
422 | if (! cpu->name) | |
423 | error ("bad value (%s) for %s switch", sel->string, sel->name); | |
733f53f5 | 424 | } |
61a55e8b | 425 | } |
97da85b7 | 426 | |
1f1406b4 | 427 | /* If -mfpu or -mno-fpu was explicitly used, don't override with |
46cc13b3 RO |
428 | the processor default. Clear MASK_FPU_SET to avoid confusing |
429 | the reverse mapping from switch values to names. */ | |
1f1406b4 | 430 | if (TARGET_FPU_SET) |
46cc13b3 RO |
431 | { |
432 | target_flags = (target_flags & ~MASK_FPU) | fpu; | |
433 | target_flags &= ~MASK_FPU_SET; | |
434 | } | |
1f1406b4 | 435 | |
a5774a7d JJ |
436 | /* Don't allow -mvis if FPU is disabled. */ |
437 | if (! TARGET_FPU) | |
438 | target_flags &= ~MASK_VIS; | |
439 | ||
440 | /* -mvis assumes UltraSPARC+, so we are sure v9 instructions | |
441 | are available. | |
442 | -m64 also implies v9. */ | |
443 | if (TARGET_VIS || TARGET_ARCH64) | |
c4031a04 JJ |
444 | { |
445 | target_flags |= MASK_V9; | |
446 | target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); | |
447 | } | |
a5774a7d | 448 | |
16956f6e DE |
449 | /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ |
450 | if (TARGET_V9 && TARGET_ARCH32) | |
733f53f5 | 451 | target_flags |= MASK_DEPRECATED_V8_INSNS; |
61a55e8b | 452 | |
345a6161 DM |
453 | /* V8PLUS requires V9, makes no sense in 64 bit mode. */ |
454 | if (! TARGET_V9 || TARGET_ARCH64) | |
284d86e9 JC |
455 | target_flags &= ~MASK_V8PLUS; |
456 | ||
82d6b402 RH |
457 | /* Don't use stack biasing in 32 bit mode. */ |
458 | if (TARGET_ARCH32) | |
459 | target_flags &= ~MASK_STACK_BIAS; | |
f952a238 | 460 | |
efa3896a | 461 | /* Supply a default value for align_functions. */ |
fae15c93 VM |
462 | if (align_functions == 0 |
463 | && (sparc_cpu == PROCESSOR_ULTRASPARC | |
464 | || sparc_cpu == PROCESSOR_ULTRASPARC3)) | |
efa3896a | 465 | align_functions = 32; |
bf62bbf1 | 466 | |
82d6b402 RH |
467 | /* Validate PCC_STRUCT_RETURN. */ |
468 | if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) | |
469 | flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); | |
470 | ||
301d03af RS |
471 | /* Only use .uaxword when compiling for a 64-bit target. */ |
472 | if (!TARGET_ARCH64) | |
473 | targetm.asm_out.unaligned_op.di = NULL; | |
474 | ||
61a55e8b DE |
475 | /* Do various machine dependent initializations. */ |
476 | sparc_init_modes (); | |
5751a10b JJ |
477 | |
478 | /* Set up function hooks. */ | |
479 | init_machine_status = sparc_init_machine_status; | |
61a55e8b DE |
480 | } |
481 | \f | |
cd5fb1ee DE |
482 | /* Miscellaneous utilities. */ |
483 | ||
484 | /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move | |
485 | or branch on register contents instructions. */ | |
486 | ||
487 | int | |
fc27d102 | 488 | v9_regcmp_p (enum rtx_code code) |
cd5fb1ee DE |
489 | { |
490 | return (code == EQ || code == NE || code == GE || code == LT | |
491 | || code == LE || code == GT); | |
492 | } | |
bfd6bc60 | 493 | |
cd5fb1ee DE |
494 | \f |
495 | /* Operand constraints. */ | |
496 | ||
5e7a8ee0 | 497 | /* Return nonzero only if OP is a register of mode MODE, |
e6c1be7e | 498 | or const0_rtx. */ |
c4ce6853 | 499 | |
ab835497 | 500 | int |
fc27d102 | 501 | reg_or_0_operand (rtx op, enum machine_mode mode) |
ab835497 | 502 | { |
c4ce6853 DE |
503 | if (register_operand (op, mode)) |
504 | return 1; | |
c4ce6853 | 505 | if (op == const0_rtx) |
ab835497 | 506 | return 1; |
5b486ce0 | 507 | if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE |
ab835497 RK |
508 | && CONST_DOUBLE_HIGH (op) == 0 |
509 | && CONST_DOUBLE_LOW (op) == 0) | |
510 | return 1; | |
7ce86678 | 511 | if (fp_zero_operand (op, mode)) |
302484ff | 512 | return 1; |
ab835497 RK |
513 | return 0; |
514 | } | |
515 | ||
5e7a8ee0 | 516 | /* Return nonzero only if OP is const1_rtx. */ |
84ea5bc1 JJ |
517 | |
518 | int | |
fc27d102 | 519 | const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
84ea5bc1 JJ |
520 | { |
521 | return op == const1_rtx; | |
522 | } | |
523 | ||
302484ff | 524 | /* Nonzero if OP is a floating point value with value 0.0. */ |
c4ce6853 | 525 | |
302484ff | 526 | int |
fc27d102 | 527 | fp_zero_operand (rtx op, enum machine_mode mode) |
302484ff | 528 | { |
7ce86678 RH |
529 | if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT) |
530 | return 0; | |
531 | return op == CONST0_RTX (mode); | |
302484ff JW |
532 | } |
533 | ||
2a732575 JJ |
534 | /* Nonzero if OP is a register operand in floating point register. */ |
535 | ||
536 | int | |
fc27d102 | 537 | fp_register_operand (rtx op, enum machine_mode mode) |
2a732575 JJ |
538 | { |
539 | if (! register_operand (op, mode)) | |
540 | return 0; | |
541 | if (GET_CODE (op) == SUBREG) | |
542 | op = SUBREG_REG (op); | |
543 | return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op)); | |
544 | } | |
545 | ||
62190128 DM |
546 | /* Nonzero if OP is a floating point constant which can |
547 | be loaded into an integer register using a single | |
548 | sethi instruction. */ | |
549 | ||
550 | int | |
fc27d102 | 551 | fp_sethi_p (rtx op) |
62190128 DM |
552 | { |
553 | if (GET_CODE (op) == CONST_DOUBLE) | |
554 | { | |
555 | REAL_VALUE_TYPE r; | |
556 | long i; | |
557 | ||
558 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
559 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
560 | ! REAL_VALUE_MINUS_ZERO (r)) | |
561 | return 0; | |
562 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
563 | if (SPARC_SETHI_P (i)) | |
564 | return 1; | |
565 | } | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | /* Nonzero if OP is a floating point constant which can | |
571 | be loaded into an integer register using a single | |
572 | mov instruction. */ | |
573 | ||
574 | int | |
fc27d102 | 575 | fp_mov_p (rtx op) |
62190128 DM |
576 | { |
577 | if (GET_CODE (op) == CONST_DOUBLE) | |
578 | { | |
579 | REAL_VALUE_TYPE r; | |
580 | long i; | |
581 | ||
582 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
583 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
584 | ! REAL_VALUE_MINUS_ZERO (r)) | |
585 | return 0; | |
586 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
587 | if (SPARC_SIMM13_P (i)) | |
588 | return 1; | |
589 | } | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
594 | /* Nonzero if OP is a floating point constant which can | |
595 | be loaded into an integer register using a high/losum | |
596 | instruction sequence. */ | |
597 | ||
598 | int | |
fc27d102 | 599 | fp_high_losum_p (rtx op) |
62190128 DM |
600 | { |
601 | /* The constraints calling this should only be in | |
602 | SFmode move insns, so any constant which cannot | |
603 | be moved using a single insn will do. */ | |
604 | if (GET_CODE (op) == CONST_DOUBLE) | |
605 | { | |
606 | REAL_VALUE_TYPE r; | |
607 | long i; | |
608 | ||
609 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
610 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
611 | ! REAL_VALUE_MINUS_ZERO (r)) | |
612 | return 0; | |
613 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
614 | if (! SPARC_SETHI_P (i) | |
615 | && ! SPARC_SIMM13_P (i)) | |
616 | return 1; | |
617 | } | |
618 | ||
619 | return 0; | |
620 | } | |
621 | ||
61a55e8b DE |
622 | /* Nonzero if OP is an integer register. */ |
623 | ||
624 | int | |
fc27d102 | 625 | intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
61a55e8b DE |
626 | { |
627 | return (register_operand (op, SImode) | |
a9e27770 | 628 | || (TARGET_ARCH64 && register_operand (op, DImode))); |
61a55e8b DE |
629 | } |
630 | ||
631 | /* Nonzero if OP is a floating point condition code register. */ | |
632 | ||
633 | int | |
fc27d102 | 634 | fcc_reg_operand (rtx op, enum machine_mode mode) |
61a55e8b DE |
635 | { |
636 | /* This can happen when recog is called from combine. Op may be a MEM. | |
637 | Fail instead of calling abort in this case. */ | |
c4ce6853 | 638 | if (GET_CODE (op) != REG) |
61a55e8b | 639 | return 0; |
304b7a23 | 640 | |
c4ce6853 | 641 | if (mode != VOIDmode && mode != GET_MODE (op)) |
61a55e8b | 642 | return 0; |
304b7a23 DE |
643 | if (mode == VOIDmode |
644 | && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) | |
645 | return 0; | |
61a55e8b | 646 | |
c4ce6853 | 647 | #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ |
61a55e8b DE |
648 | if (reg_renumber == 0) |
649 | return REGNO (op) >= FIRST_PSEUDO_REGISTER; | |
650 | return REGNO_OK_FOR_CCFP_P (REGNO (op)); | |
651 | #else | |
c4ce6853 | 652 | return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; |
61a55e8b DE |
653 | #endif |
654 | } | |
655 | ||
0b82d204 JJ |
656 | /* Nonzero if OP is a floating point condition code fcc0 register. */ |
657 | ||
658 | int | |
fc27d102 | 659 | fcc0_reg_operand (rtx op, enum machine_mode mode) |
0b82d204 JJ |
660 | { |
661 | /* This can happen when recog is called from combine. Op may be a MEM. | |
662 | Fail instead of calling abort in this case. */ | |
663 | if (GET_CODE (op) != REG) | |
664 | return 0; | |
665 | ||
666 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
667 | return 0; | |
668 | if (mode == VOIDmode | |
669 | && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) | |
670 | return 0; | |
671 | ||
672 | return REGNO (op) == SPARC_FCC_REG; | |
673 | } | |
674 | ||
c4ce6853 DE |
675 | /* Nonzero if OP is an integer or floating point condition code register. */ |
676 | ||
677 | int | |
fc27d102 | 678 | icc_or_fcc_reg_operand (rtx op, enum machine_mode mode) |
c4ce6853 DE |
679 | { |
680 | if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) | |
304b7a23 DE |
681 | { |
682 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
683 | return 0; | |
684 | if (mode == VOIDmode | |
685 | && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) | |
686 | return 0; | |
687 | return 1; | |
688 | } | |
689 | ||
c4ce6853 DE |
690 | return fcc_reg_operand (op, mode); |
691 | } | |
692 | ||
ab835497 RK |
693 | /* Nonzero if OP can appear as the dest of a RESTORE insn. */ |
694 | int | |
fc27d102 | 695 | restore_operand (rtx op, enum machine_mode mode) |
ab835497 RK |
696 | { |
697 | return (GET_CODE (op) == REG && GET_MODE (op) == mode | |
698 | && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); | |
699 | } | |
700 | ||
401cec23 JW |
701 | /* Call insn on SPARC can take a PC-relative constant address, or any regular |
702 | memory address. */ | |
ab835497 RK |
703 | |
704 | int | |
fc27d102 | 705 | call_operand (rtx op, enum machine_mode mode) |
ab835497 RK |
706 | { |
707 | if (GET_CODE (op) != MEM) | |
708 | abort (); | |
709 | op = XEXP (op, 0); | |
2445f289 | 710 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
711 | } |
712 | ||
713 | int | |
fc27d102 | 714 | call_operand_address (rtx op, enum machine_mode mode) |
ab835497 | 715 | { |
2445f289 | 716 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
717 | } |
718 | ||
5751a10b JJ |
719 | /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode, |
720 | otherwise return 0. */ | |
721 | ||
722 | int | |
723 | tls_symbolic_operand (rtx op) | |
724 | { | |
725 | if (GET_CODE (op) != SYMBOL_REF) | |
726 | return 0; | |
727 | return SYMBOL_REF_TLS_MODEL (op); | |
728 | } | |
729 | ||
730 | int | |
731 | tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
732 | { | |
733 | return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC; | |
734 | } | |
735 | ||
736 | int | |
737 | tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
738 | { | |
739 | return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC; | |
740 | } | |
741 | ||
742 | int | |
743 | tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
744 | { | |
745 | return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC; | |
746 | } | |
747 | ||
748 | int | |
749 | tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
750 | { | |
751 | return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC; | |
752 | } | |
753 | ||
ab835497 RK |
754 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol |
755 | reference and a constant. */ | |
756 | ||
757 | int | |
fc27d102 | 758 | symbolic_operand (register rtx op, enum machine_mode mode) |
ab835497 | 759 | { |
6871dd65 RH |
760 | enum machine_mode omode = GET_MODE (op); |
761 | ||
762 | if (omode != mode && omode != VOIDmode && mode != VOIDmode) | |
763 | return 0; | |
764 | ||
ab835497 RK |
765 | switch (GET_CODE (op)) |
766 | { | |
767 | case SYMBOL_REF: | |
5751a10b JJ |
768 | return !SYMBOL_REF_TLS_MODEL (op); |
769 | ||
ab835497 RK |
770 | case LABEL_REF: |
771 | return 1; | |
772 | ||
773 | case CONST: | |
774 | op = XEXP (op, 0); | |
5751a10b JJ |
775 | return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF |
776 | && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0))) | |
ab835497 RK |
777 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) |
778 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
779 | ||
ab835497 RK |
780 | default: |
781 | return 0; | |
782 | } | |
783 | } | |
784 | ||
785 | /* Return truth value of statement that OP is a symbolic memory | |
786 | operand of mode MODE. */ | |
787 | ||
788 | int | |
fc27d102 | 789 | symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
790 | { |
791 | if (GET_CODE (op) == SUBREG) | |
792 | op = SUBREG_REG (op); | |
793 | if (GET_CODE (op) != MEM) | |
794 | return 0; | |
795 | op = XEXP (op, 0); | |
5751a10b JJ |
796 | return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op)) |
797 | || GET_CODE (op) == CONST || GET_CODE (op) == HIGH | |
798 | || GET_CODE (op) == LABEL_REF); | |
ab835497 RK |
799 | } |
800 | ||
5ab7138b DE |
801 | /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ |
802 | ||
803 | int | |
fc27d102 | 804 | label_ref_operand (rtx op, enum machine_mode mode) |
5ab7138b DE |
805 | { |
806 | if (GET_CODE (op) != LABEL_REF) | |
807 | return 0; | |
808 | if (GET_MODE (op) != mode) | |
809 | return 0; | |
810 | return 1; | |
811 | } | |
812 | ||
95726648 DE |
813 | /* Return 1 if the operand is an argument used in generating pic references |
814 | in either the medium/low or medium/anywhere code models of sparc64. */ | |
815 | ||
816 | int | |
fc27d102 | 817 | sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
95726648 DE |
818 | { |
819 | /* Check for (const (minus (symbol_ref:GOT) | |
820 | (const (minus (label) (pc))))). */ | |
821 | if (GET_CODE (op) != CONST) | |
822 | return 0; | |
823 | op = XEXP (op, 0); | |
824 | if (GET_CODE (op) != MINUS) | |
825 | return 0; | |
826 | if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) | |
827 | return 0; | |
828 | /* ??? Ensure symbol is GOT. */ | |
829 | if (GET_CODE (XEXP (op, 1)) != CONST) | |
830 | return 0; | |
831 | if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) | |
832 | return 0; | |
833 | return 1; | |
834 | } | |
835 | ||
61a55e8b DE |
836 | /* Return 1 if the operand is a data segment reference. This includes |
837 | the readonly data segment, or in other words anything but the text segment. | |
838 | This is needed in the medium/anywhere code model on v9. These values | |
a0a301fc | 839 | are accessed with EMBMEDANY_BASE_REG. */ |
61a55e8b DE |
840 | |
841 | int | |
fc27d102 | 842 | data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
61a55e8b DE |
843 | { |
844 | switch (GET_CODE (op)) | |
845 | { | |
846 | case SYMBOL_REF : | |
72628c61 | 847 | return ! SYMBOL_REF_FUNCTION_P (op); |
61a55e8b | 848 | case PLUS : |
95726648 DE |
849 | /* Assume canonical format of symbol + constant. |
850 | Fall through. */ | |
61a55e8b | 851 | case CONST : |
b1474bb7 | 852 | return data_segment_operand (XEXP (op, 0), VOIDmode); |
61a55e8b DE |
853 | default : |
854 | return 0; | |
855 | } | |
856 | } | |
857 | ||
858 | /* Return 1 if the operand is a text segment reference. | |
859 | This is needed in the medium/anywhere code model on v9. */ | |
860 | ||
861 | int | |
fc27d102 | 862 | text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
61a55e8b DE |
863 | { |
864 | switch (GET_CODE (op)) | |
865 | { | |
866 | case LABEL_REF : | |
867 | return 1; | |
868 | case SYMBOL_REF : | |
72628c61 | 869 | return SYMBOL_REF_FUNCTION_P (op); |
61a55e8b | 870 | case PLUS : |
95726648 DE |
871 | /* Assume canonical format of symbol + constant. |
872 | Fall through. */ | |
61a55e8b | 873 | case CONST : |
b1474bb7 | 874 | return text_segment_operand (XEXP (op, 0), VOIDmode); |
61a55e8b DE |
875 | default : |
876 | return 0; | |
877 | } | |
878 | } | |
879 | ||
ab835497 RK |
880 | /* Return 1 if the operand is either a register or a memory operand that is |
881 | not symbolic. */ | |
882 | ||
883 | int | |
fc27d102 | 884 | reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode) |
ab835497 RK |
885 | { |
886 | if (register_operand (op, mode)) | |
887 | return 1; | |
888 | ||
889 | if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) | |
890 | return 1; | |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
ab835497 | 895 | int |
fc27d102 KG |
896 | splittable_symbolic_memory_operand (rtx op, |
897 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
ab835497 | 898 | { |
6ac34277 DE |
899 | if (GET_CODE (op) != MEM) |
900 | return 0; | |
901 | if (! symbolic_operand (XEXP (op, 0), Pmode)) | |
902 | return 0; | |
903 | return 1; | |
904 | } | |
905 | ||
906 | int | |
fc27d102 KG |
907 | splittable_immediate_memory_operand (rtx op, |
908 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
6ac34277 DE |
909 | { |
910 | if (GET_CODE (op) != MEM) | |
911 | return 0; | |
912 | if (! immediate_operand (XEXP (op, 0), Pmode)) | |
913 | return 0; | |
914 | return 1; | |
ab835497 RK |
915 | } |
916 | ||
917 | /* Return truth value of whether OP is EQ or NE. */ | |
918 | ||
919 | int | |
fc27d102 | 920 | eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
921 | { |
922 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
923 | } | |
924 | ||
925 | /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, | |
926 | or LTU for non-floating-point. We handle those specially. */ | |
927 | ||
928 | int | |
fc27d102 | 929 | normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
930 | { |
931 | enum rtx_code code = GET_CODE (op); | |
932 | ||
933 | if (GET_RTX_CLASS (code) != '<') | |
934 | return 0; | |
935 | ||
4d449554 JW |
936 | if (GET_MODE (XEXP (op, 0)) == CCFPmode |
937 | || GET_MODE (XEXP (op, 0)) == CCFPEmode) | |
ab835497 RK |
938 | return 1; |
939 | ||
940 | return (code != NE && code != EQ && code != GEU && code != LTU); | |
941 | } | |
942 | ||
943 | /* Return 1 if this is a comparison operator. This allows the use of | |
944 | MATCH_OPERATOR to recognize all the branch insns. */ | |
945 | ||
946 | int | |
fc27d102 | 947 | noov_compare_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
948 | { |
949 | enum rtx_code code = GET_CODE (op); | |
950 | ||
951 | if (GET_RTX_CLASS (code) != '<') | |
952 | return 0; | |
953 | ||
0b82d204 JJ |
954 | if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode |
955 | || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) | |
ab835497 RK |
956 | /* These are the only branches which work with CC_NOOVmode. */ |
957 | return (code == EQ || code == NE || code == GE || code == LT); | |
958 | return 1; | |
959 | } | |
960 | ||
0b82d204 JJ |
961 | /* Return 1 if this is a 64-bit comparison operator. This allows the use of |
962 | MATCH_OPERATOR to recognize all the branch insns. */ | |
963 | ||
964 | int | |
fc27d102 | 965 | noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0b82d204 JJ |
966 | { |
967 | enum rtx_code code = GET_CODE (op); | |
968 | ||
969 | if (! TARGET_V9) | |
970 | return 0; | |
971 | ||
972 | if (GET_RTX_CLASS (code) != '<') | |
973 | return 0; | |
974 | ||
975 | if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) | |
976 | /* These are the only branches which work with CCX_NOOVmode. */ | |
977 | return (code == EQ || code == NE || code == GE || code == LT); | |
978 | return (GET_MODE (XEXP (op, 0)) == CCXmode); | |
979 | } | |
980 | ||
61a55e8b DE |
981 | /* Nonzero if OP is a comparison operator suitable for use in v9 |
982 | conditional move or branch on register contents instructions. */ | |
983 | ||
984 | int | |
fc27d102 | 985 | v9_regcmp_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
61a55e8b DE |
986 | { |
987 | enum rtx_code code = GET_CODE (op); | |
988 | ||
989 | if (GET_RTX_CLASS (code) != '<') | |
990 | return 0; | |
991 | ||
cd5fb1ee | 992 | return v9_regcmp_p (code); |
61a55e8b DE |
993 | } |
994 | ||
ab835497 RK |
995 | /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ |
996 | ||
997 | int | |
fc27d102 | 998 | extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
999 | { |
1000 | return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; | |
1001 | } | |
1002 | ||
1003 | /* Return nonzero if OP is an operator of mode MODE which can set | |
1004 | the condition codes explicitly. We do not include PLUS and MINUS | |
1005 | because these require CC_NOOVmode, which we handle explicitly. */ | |
1006 | ||
1007 | int | |
fc27d102 | 1008 | cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
1009 | { |
1010 | if (GET_CODE (op) == AND | |
1011 | || GET_CODE (op) == IOR | |
1012 | || GET_CODE (op) == XOR) | |
1013 | return 1; | |
1014 | ||
1015 | return 0; | |
1016 | } | |
1017 | ||
1018 | /* Return nonzero if OP is an operator of mode MODE which can bitwise | |
1019 | complement its second operand and set the condition codes explicitly. */ | |
1020 | ||
1021 | int | |
fc27d102 | 1022 | cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
1023 | { |
1024 | /* XOR is not here because combine canonicalizes (xor (not ...) ...) | |
80ffc95e | 1025 | and (xor ... (not ...)) to (not (xor ...)). */ |
ab835497 RK |
1026 | return (GET_CODE (op) == AND |
1027 | || GET_CODE (op) == IOR); | |
1028 | } | |
1029 | \f | |
58cbf20e DE |
1030 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
1031 | signed 13 bit immediate field. This is an acceptable SImode operand for | |
1032 | most 3 address instructions. */ | |
ab835497 RK |
1033 | |
1034 | int | |
fc27d102 | 1035 | arith_operand (rtx op, enum machine_mode mode) |
ab835497 | 1036 | { |
11301057 | 1037 | if (register_operand (op, mode)) |
284d86e9 JC |
1038 | return 1; |
1039 | if (GET_CODE (op) != CONST_INT) | |
1040 | return 0; | |
9e0625a3 | 1041 | return SMALL_INT32 (op); |
ab835497 RK |
1042 | } |
1043 | ||
5d6d3339 JJ |
1044 | /* Return true if OP is a constant 4096 */ |
1045 | ||
1046 | int | |
fc27d102 | 1047 | arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
5d6d3339 | 1048 | { |
5d6d3339 JJ |
1049 | if (GET_CODE (op) != CONST_INT) |
1050 | return 0; | |
3070dd00 KG |
1051 | else |
1052 | return INTVAL (op) == 4096; | |
5d6d3339 JJ |
1053 | } |
1054 | ||
1055 | /* Return true if OP is suitable as second operand for add/sub */ | |
1056 | ||
1057 | int | |
fc27d102 | 1058 | arith_add_operand (rtx op, enum machine_mode mode) |
5d6d3339 JJ |
1059 | { |
1060 | return arith_operand (op, mode) || arith_4096_operand (op, mode); | |
1061 | } | |
1062 | ||
89e65674 DM |
1063 | /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the |
1064 | immediate field of OR and XOR instructions. Used for 64-bit | |
1065 | constant formation patterns. */ | |
1066 | int | |
fc27d102 | 1067 | const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
89e65674 DM |
1068 | { |
1069 | return ((GET_CODE (op) == CONST_INT | |
1070 | && SPARC_SIMM13_P (INTVAL (op))) | |
9208e4b2 | 1071 | #if HOST_BITS_PER_WIDE_INT != 64 |
89e65674 | 1072 | || (GET_CODE (op) == CONST_DOUBLE |
9208e4b2 DM |
1073 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) |
1074 | && (CONST_DOUBLE_HIGH (op) == | |
1075 | ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? | |
9e0625a3 | 1076 | (HOST_WIDE_INT)-1 : 0))) |
9208e4b2 | 1077 | #endif |
11301057 | 1078 | ); |
89e65674 DM |
1079 | } |
1080 | ||
9208e4b2 | 1081 | /* The same, but only for sethi instructions. */ |
89e65674 | 1082 | int |
fc27d102 | 1083 | const64_high_operand (rtx op, enum machine_mode mode) |
89e65674 DM |
1084 | { |
1085 | return ((GET_CODE (op) == CONST_INT | |
9e0625a3 | 1086 | && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0 |
7d6040e8 | 1087 | && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) |
9208e4b2 | 1088 | ) |
89e65674 DM |
1089 | || (GET_CODE (op) == CONST_DOUBLE |
1090 | && CONST_DOUBLE_HIGH (op) == 0 | |
9e0625a3 | 1091 | && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0 |
11301057 | 1092 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))); |
89e65674 DM |
1093 | } |
1094 | ||
58cbf20e DE |
1095 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
1096 | signed 11 bit immediate field. This is an acceptable SImode operand for | |
1097 | the movcc instructions. */ | |
61a55e8b DE |
1098 | |
1099 | int | |
fc27d102 | 1100 | arith11_operand (rtx op, enum machine_mode mode) |
61a55e8b DE |
1101 | { |
1102 | return (register_operand (op, mode) | |
58cbf20e | 1103 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); |
61a55e8b DE |
1104 | } |
1105 | ||
58cbf20e DE |
1106 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
1107 | signed 10 bit immediate field. This is an acceptable SImode operand for | |
1108 | the movrcc instructions. */ | |
61a55e8b DE |
1109 | |
1110 | int | |
fc27d102 | 1111 | arith10_operand (rtx op, enum machine_mode mode) |
61a55e8b DE |
1112 | { |
1113 | return (register_operand (op, mode) | |
58cbf20e | 1114 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); |
61a55e8b DE |
1115 | } |
1116 | ||
23b8a89f JW |
1117 | /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit |
1118 | immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit | |
61a55e8b DE |
1119 | immediate field. |
1120 | v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
1121 | can fit in a 13 bit immediate field. This is an acceptable DImode operand | |
1122 | for most 3 address instructions. */ | |
ab835497 RK |
1123 | |
1124 | int | |
fc27d102 | 1125 | arith_double_operand (rtx op, enum machine_mode mode) |
ab835497 RK |
1126 | { |
1127 | return (register_operand (op, mode) | |
23b8a89f | 1128 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) |
a9e27770 | 1129 | || (! TARGET_ARCH64 |
61a55e8b | 1130 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 DE |
1131 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
1132 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) | |
a9e27770 | 1133 | || (TARGET_ARCH64 |
61a55e8b | 1134 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 | 1135 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
61a55e8b DE |
1136 | && ((CONST_DOUBLE_HIGH (op) == -1 |
1137 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) | |
1138 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1139 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); | |
1140 | } | |
1141 | ||
5d6d3339 JJ |
1142 | /* Return true if OP is a constant 4096 for DImode on ARCH64 */ |
1143 | ||
1144 | int | |
fc27d102 | 1145 | arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
5d6d3339 JJ |
1146 | { |
1147 | return (TARGET_ARCH64 && | |
1148 | ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || | |
1149 | (GET_CODE (op) == CONST_DOUBLE && | |
1150 | CONST_DOUBLE_LOW (op) == 4096 && | |
1151 | CONST_DOUBLE_HIGH (op) == 0))); | |
1152 | } | |
1153 | ||
1154 | /* Return true if OP is suitable as second operand for add/sub in DImode */ | |
1155 | ||
1156 | int | |
fc27d102 | 1157 | arith_double_add_operand (rtx op, enum machine_mode mode) |
5d6d3339 JJ |
1158 | { |
1159 | return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode); | |
1160 | } | |
1161 | ||
61a55e8b DE |
1162 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that |
1163 | can fit in an 11 bit immediate field. This is an acceptable DImode | |
1164 | operand for the movcc instructions. */ | |
1165 | /* ??? Replace with arith11_operand? */ | |
1166 | ||
1167 | int | |
fc27d102 | 1168 | arith11_double_operand (rtx op, enum machine_mode mode) |
61a55e8b DE |
1169 | { |
1170 | return (register_operand (op, mode) | |
1171 | || (GET_CODE (op) == CONST_DOUBLE | |
1172 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1173 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 |
61a55e8b DE |
1174 | && ((CONST_DOUBLE_HIGH (op) == -1 |
1175 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) | |
1176 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1177 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) | |
1178 | || (GET_CODE (op) == CONST_INT | |
1179 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1180 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800)); |
61a55e8b DE |
1181 | } |
1182 | ||
1183 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
1184 | can fit in an 10 bit immediate field. This is an acceptable DImode | |
1185 | operand for the movrcc instructions. */ | |
1186 | /* ??? Replace with arith10_operand? */ | |
1187 | ||
1188 | int | |
fc27d102 | 1189 | arith10_double_operand (rtx op, enum machine_mode mode) |
61a55e8b DE |
1190 | { |
1191 | return (register_operand (op, mode) | |
1192 | || (GET_CODE (op) == CONST_DOUBLE | |
1193 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
1194 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 | |
1195 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
1196 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) | |
1197 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1198 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) | |
1199 | || (GET_CODE (op) == CONST_INT | |
1200 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1201 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400)); |
ab835497 RK |
1202 | } |
1203 | ||
5519a4f9 | 1204 | /* Return truth value of whether OP is an integer which fits the |
228b4037 JW |
1205 | range constraining immediate operands in most three-address insns, |
1206 | which have a 13 bit immediate field. */ | |
ab835497 RK |
1207 | |
1208 | int | |
fc27d102 | 1209 | small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 | 1210 | { |
11301057 | 1211 | return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); |
ab835497 RK |
1212 | } |
1213 | ||
e0d80184 | 1214 | int |
fc27d102 | 1215 | small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
e0d80184 DM |
1216 | { |
1217 | return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) | |
1218 | || (GET_CODE (op) == CONST_DOUBLE | |
1219 | && CONST_DOUBLE_HIGH (op) == 0 | |
11301057 | 1220 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))); |
e0d80184 DM |
1221 | } |
1222 | ||
9b3fad96 JW |
1223 | /* Recognize operand values for the umul instruction. That instruction sign |
1224 | extends immediate values just like all other sparc instructions, but | |
1225 | interprets the extended result as an unsigned number. */ | |
1226 | ||
1227 | int | |
fc27d102 | 1228 | uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9b3fad96 JW |
1229 | { |
1230 | #if HOST_BITS_PER_WIDE_INT > 32 | |
1231 | /* All allowed constants will fit a CONST_INT. */ | |
11301057 RH |
1232 | return (GET_CODE (op) == CONST_INT |
1233 | && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) | |
1234 | || (INTVAL (op) >= 0xFFFFF000 | |
0d587737 | 1235 | && INTVAL (op) <= 0xFFFFFFFF))); |
9b3fad96 | 1236 | #else |
11301057 RH |
1237 | return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) |
1238 | || (GET_CODE (op) == CONST_DOUBLE | |
1239 | && CONST_DOUBLE_HIGH (op) == 0 | |
1240 | && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); | |
9b3fad96 JW |
1241 | #endif |
1242 | } | |
1243 | ||
1244 | int | |
fc27d102 | 1245 | uns_arith_operand (rtx op, enum machine_mode mode) |
9b3fad96 JW |
1246 | { |
1247 | return register_operand (op, mode) || uns_small_int (op, mode); | |
1248 | } | |
1249 | ||
ab835497 RK |
1250 | /* Return truth value of statement that OP is a call-clobbered register. */ |
1251 | int | |
fc27d102 | 1252 | clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
1253 | { |
1254 | return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); | |
1255 | } | |
ab835497 | 1256 | |
e0d80184 | 1257 | /* Return 1 if OP is a valid operand for the source of a move insn. */ |
61a55e8b | 1258 | |
e0d80184 | 1259 | int |
fc27d102 | 1260 | input_operand (rtx op, enum machine_mode mode) |
e0d80184 DM |
1261 | { |
1262 | /* If both modes are non-void they must be the same. */ | |
1263 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) | |
1264 | return 0; | |
61a55e8b | 1265 | |
375ffbe6 EB |
1266 | /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */ |
1267 | if (GET_CODE (op) == CONSTANT_P_RTX) | |
11301057 RH |
1268 | return 1; |
1269 | ||
e0d80184 DM |
1270 | /* Allow any one instruction integer constant, and all CONST_INT |
1271 | variants when we are working in DImode and !arch64. */ | |
1272 | if (GET_MODE_CLASS (mode) == MODE_INT | |
9208e4b2 | 1273 | && ((GET_CODE (op) == CONST_INT |
7d6040e8 | 1274 | && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) |
9208e4b2 DM |
1275 | || SPARC_SIMM13_P (INTVAL (op)) |
1276 | || (mode == DImode | |
1277 | && ! TARGET_ARCH64))) | |
1278 | || (TARGET_ARCH64 | |
1279 | && GET_CODE (op) == CONST_DOUBLE | |
1280 | && ((CONST_DOUBLE_HIGH (op) == 0 | |
1281 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) | |
1282 | || | |
1283 | #if HOST_BITS_PER_WIDE_INT == 64 | |
1284 | (CONST_DOUBLE_HIGH (op) == 0 | |
1285 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) | |
1286 | #else | |
1287 | (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) | |
1288 | && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0 | |
1289 | && CONST_DOUBLE_HIGH (op) == 0) | |
4746e0fe RK |
1290 | || (CONST_DOUBLE_HIGH (op) == -1 |
1291 | && CONST_DOUBLE_LOW (op) & 0x80000000) != 0)) | |
9208e4b2 DM |
1292 | #endif |
1293 | )))) | |
e0d80184 DM |
1294 | return 1; |
1295 | ||
e0d80184 DM |
1296 | /* If !arch64 and this is a DImode const, allow it so that |
1297 | the splits can be generated. */ | |
1298 | if (! TARGET_ARCH64 | |
1299 | && mode == DImode | |
1300 | && GET_CODE (op) == CONST_DOUBLE) | |
1301 | return 1; | |
1302 | ||
1303 | if (register_operand (op, mode)) | |
1304 | return 1; | |
1305 | ||
62190128 DM |
1306 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1307 | && GET_CODE (op) == CONST_DOUBLE) | |
1308 | return 1; | |
1309 | ||
e0d80184 DM |
1310 | /* If this is a SUBREG, look inside so that we handle |
1311 | paradoxical ones. */ | |
1312 | if (GET_CODE (op) == SUBREG) | |
1313 | op = SUBREG_REG (op); | |
1314 | ||
1315 | /* Check for valid MEM forms. */ | |
1316 | if (GET_CODE (op) == MEM) | |
61a55e8b | 1317 | { |
e0d80184 | 1318 | rtx inside = XEXP (op, 0); |
61a55e8b | 1319 | |
e0d80184 | 1320 | if (GET_CODE (inside) == LO_SUM) |
03ad6f4d DM |
1321 | { |
1322 | /* We can't allow these because all of the splits | |
1323 | (eventually as they trickle down into DFmode | |
1324 | splits) require offsettable memory references. */ | |
1325 | if (! TARGET_V9 | |
1326 | && GET_MODE (op) == TFmode) | |
1327 | return 0; | |
1328 | ||
1329 | return (register_operand (XEXP (inside, 0), Pmode) | |
1330 | && CONSTANT_P (XEXP (inside, 1))); | |
1331 | } | |
e0d80184 | 1332 | return memory_address_p (mode, inside); |
61a55e8b | 1333 | } |
ab835497 | 1334 | |
e0d80184 DM |
1335 | return 0; |
1336 | } | |
1337 | ||
1338 | \f | |
1339 | /* We know it can't be done in one insn when we get here, | |
fae778eb | 1340 | the movsi expander guarantees this. */ |
e0d80184 | 1341 | void |
fc27d102 | 1342 | sparc_emit_set_const32 (rtx op0, rtx op1) |
e0d80184 DM |
1343 | { |
1344 | enum machine_mode mode = GET_MODE (op0); | |
1345 | rtx temp; | |
1346 | ||
1347 | if (GET_CODE (op1) == CONST_INT) | |
284d86e9 | 1348 | { |
2a01c939 | 1349 | HOST_WIDE_INT value = INTVAL (op1); |
e0d80184 | 1350 | |
7d6040e8 | 1351 | if (SPARC_SETHI_P (value & GET_MODE_MASK (mode)) |
e0d80184 DM |
1352 | || SPARC_SIMM13_P (value)) |
1353 | abort (); | |
284d86e9 | 1354 | } |
e0d80184 DM |
1355 | |
1356 | /* Full 2-insn decomposition is needed. */ | |
1357 | if (reload_in_progress || reload_completed) | |
1358 | temp = op0; | |
284d86e9 | 1359 | else |
e0d80184 DM |
1360 | temp = gen_reg_rtx (mode); |
1361 | ||
71648202 DM |
1362 | if (GET_CODE (op1) == CONST_INT) |
1363 | { | |
1364 | /* Emit them as real moves instead of a HIGH/LO_SUM, | |
1365 | this way CSE can see everything and reuse intermediate | |
1366 | values if it wants. */ | |
1367 | if (TARGET_ARCH64 | |
1368 | && HOST_BITS_PER_WIDE_INT != 64 | |
1369 | && (INTVAL (op1) & 0x80000000) != 0) | |
f2827474 RK |
1370 | emit_insn (gen_rtx_SET |
1371 | (VOIDmode, temp, | |
5692c7bc ZW |
1372 | immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff, |
1373 | 0, DImode))); | |
71648202 | 1374 | else |
f2827474 | 1375 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
9e0625a3 AO |
1376 | GEN_INT (INTVAL (op1) |
1377 | & ~(HOST_WIDE_INT)0x3ff))); | |
f2827474 | 1378 | |
71648202 DM |
1379 | emit_insn (gen_rtx_SET (VOIDmode, |
1380 | op0, | |
f2827474 | 1381 | gen_rtx_IOR (mode, temp, |
71648202 DM |
1382 | GEN_INT (INTVAL (op1) & 0x3ff)))); |
1383 | } | |
1384 | else | |
1385 | { | |
1386 | /* A symbol, emit in the traditional way. */ | |
f2827474 RK |
1387 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
1388 | gen_rtx_HIGH (mode, op1))); | |
71648202 | 1389 | emit_insn (gen_rtx_SET (VOIDmode, |
f2827474 | 1390 | op0, gen_rtx_LO_SUM (mode, temp, op1))); |
71648202 DM |
1391 | |
1392 | } | |
e0d80184 DM |
1393 | } |
1394 | ||
1395 | \f | |
56149abc | 1396 | /* SPARC-v9 code-model support. */ |
e0d80184 | 1397 | void |
fc27d102 | 1398 | sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp1) |
e0d80184 | 1399 | { |
3968de80 DD |
1400 | rtx ti_temp1 = 0; |
1401 | ||
1402 | if (temp1 && GET_MODE (temp1) == TImode) | |
1403 | { | |
1404 | ti_temp1 = temp1; | |
1405 | temp1 = gen_rtx_REG (DImode, REGNO (temp1)); | |
1406 | } | |
1407 | ||
e0d80184 | 1408 | switch (sparc_cmodel) |
284d86e9 | 1409 | { |
e0d80184 DM |
1410 | case CM_MEDLOW: |
1411 | /* The range spanned by all instructions in the object is less | |
1412 | than 2^31 bytes (2GB) and the distance from any instruction | |
1413 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1414 | than 2^31 bytes (2GB). | |
ab835497 | 1415 | |
e0d80184 DM |
1416 | The executable must be in the low 4TB of the virtual address |
1417 | space. | |
61a55e8b | 1418 | |
e0d80184 DM |
1419 | sethi %hi(symbol), %temp |
1420 | or %temp, %lo(symbol), %reg */ | |
9208e4b2 DM |
1421 | emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); |
1422 | emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); | |
e0d80184 | 1423 | break; |
61a55e8b | 1424 | |
e0d80184 DM |
1425 | case CM_MEDMID: |
1426 | /* The range spanned by all instructions in the object is less | |
1427 | than 2^31 bytes (2GB) and the distance from any instruction | |
1428 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1429 | than 2^31 bytes (2GB). | |
1430 | ||
1431 | The executable must be in the low 16TB of the virtual address | |
1432 | space. | |
1433 | ||
1434 | sethi %h44(symbol), %temp1 | |
1435 | or %temp1, %m44(symbol), %temp2 | |
1436 | sllx %temp2, 12, %temp3 | |
1437 | or %temp3, %l44(symbol), %reg */ | |
1438 | emit_insn (gen_seth44 (op0, op1)); | |
1439 | emit_insn (gen_setm44 (op0, op0, op1)); | |
9208e4b2 | 1440 | emit_insn (gen_rtx_SET (VOIDmode, temp1, |
e0d80184 DM |
1441 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (12)))); |
1442 | emit_insn (gen_setl44 (op0, temp1, op1)); | |
1443 | break; | |
61a55e8b | 1444 | |
e0d80184 DM |
1445 | case CM_MEDANY: |
1446 | /* The range spanned by all instructions in the object is less | |
1447 | than 2^31 bytes (2GB) and the distance from any instruction | |
1448 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1449 | than 2^31 bytes (2GB). | |
1450 | ||
1451 | The executable can be placed anywhere in the virtual address | |
1452 | space. | |
1453 | ||
1454 | sethi %hh(symbol), %temp1 | |
1455 | sethi %lm(symbol), %temp2 | |
1456 | or %temp1, %hm(symbol), %temp3 | |
1457 | or %temp2, %lo(symbol), %temp4 | |
1458 | sllx %temp3, 32, %temp5 | |
1459 | or %temp4, %temp5, %reg */ | |
1460 | ||
3968de80 DD |
1461 | /* It is possible that one of the registers we got for operands[2] |
1462 | might coincide with that of operands[0] (which is why we made | |
1463 | it TImode). Pick the other one to use as our scratch. */ | |
6cd444b4 | 1464 | if (rtx_equal_p (temp1, op0)) |
3968de80 DD |
1465 | { |
1466 | if (ti_temp1) | |
1467 | temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1); | |
1468 | else | |
1469 | abort(); | |
1470 | } | |
61a55e8b | 1471 | |
e0d80184 DM |
1472 | emit_insn (gen_sethh (op0, op1)); |
1473 | emit_insn (gen_setlm (temp1, op1)); | |
1474 | emit_insn (gen_sethm (op0, op0, op1)); | |
9208e4b2 | 1475 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1476 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1477 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1478 | gen_rtx_PLUS (DImode, op0, temp1))); |
1479 | emit_insn (gen_setlo (op0, op0, op1)); | |
1480 | break; | |
61a55e8b | 1481 | |
e0d80184 DM |
1482 | case CM_EMBMEDANY: |
1483 | /* Old old old backwards compatibility kruft here. | |
1484 | Essentially it is MEDLOW with a fixed 64-bit | |
1485 | virtual base added to all data segment addresses. | |
1486 | Text-segment stuff is computed like MEDANY, we can't | |
1487 | reuse the code above because the relocation knobs | |
1488 | look different. | |
1489 | ||
1490 | Data segment: sethi %hi(symbol), %temp1 | |
1491 | or %temp1, %lo(symbol), %temp2 | |
1492 | add %temp2, EMBMEDANY_BASE_REG, %reg | |
1493 | ||
1494 | Text segment: sethi %uhi(symbol), %temp1 | |
1495 | sethi %hi(symbol), %temp2 | |
1496 | or %temp1, %ulo(symbol), %temp3 | |
1497 | or %temp2, %lo(symbol), %temp4 | |
1498 | sllx %temp3, 32, %temp5 | |
1499 | or %temp4, %temp5, %reg */ | |
1500 | if (data_segment_operand (op1, GET_MODE (op1))) | |
1501 | { | |
1502 | emit_insn (gen_embmedany_sethi (temp1, op1)); | |
1503 | emit_insn (gen_embmedany_brsum (op0, temp1)); | |
1504 | emit_insn (gen_embmedany_losum (op0, op0, op1)); | |
1505 | } | |
1506 | else | |
1507 | { | |
3968de80 DD |
1508 | /* It is possible that one of the registers we got for operands[2] |
1509 | might coincide with that of operands[0] (which is why we made | |
1510 | it TImode). Pick the other one to use as our scratch. */ | |
1511 | if (rtx_equal_p (temp1, op0)) | |
1512 | { | |
1513 | if (ti_temp1) | |
1514 | temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1); | |
1515 | else | |
1516 | abort(); | |
1517 | } | |
61a55e8b | 1518 | |
e0d80184 DM |
1519 | emit_insn (gen_embmedany_textuhi (op0, op1)); |
1520 | emit_insn (gen_embmedany_texthi (temp1, op1)); | |
1521 | emit_insn (gen_embmedany_textulo (op0, op0, op1)); | |
9208e4b2 | 1522 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1523 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1524 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1525 | gen_rtx_PLUS (DImode, op0, temp1))); |
1526 | emit_insn (gen_embmedany_textlo (op0, op0, op1)); | |
1527 | } | |
1528 | break; | |
1529 | ||
1530 | default: | |
1531 | abort(); | |
1532 | } | |
1533 | } | |
1534 | ||
9208e4b2 DM |
1535 | /* These avoid problems when cross compiling. If we do not |
1536 | go through all this hair then the optimizer will see | |
1537 | invalid REG_EQUAL notes or in some cases none at all. */ | |
e80d5f80 KG |
1538 | static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT); |
1539 | static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT); | |
1540 | static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT); | |
1541 | static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT); | |
9208e4b2 DM |
1542 | |
1543 | #if HOST_BITS_PER_WIDE_INT == 64 | |
9e0625a3 | 1544 | #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff) |
9208e4b2 DM |
1545 | #define GEN_INT64(__x) GEN_INT (__x) |
1546 | #else | |
1547 | #define GEN_HIGHINT64(__x) \ | |
5692c7bc | 1548 | immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode) |
9208e4b2 | 1549 | #define GEN_INT64(__x) \ |
5692c7bc ZW |
1550 | immed_double_const ((__x) & 0xffffffff, \ |
1551 | ((__x) & 0x80000000 ? -1 : 0), DImode) | |
9208e4b2 DM |
1552 | #endif |
1553 | ||
1554 | /* The optimizer is not to assume anything about exactly | |
1555 | which bits are set for a HIGH, they are unspecified. | |
1556 | Unfortunately this leads to many missed optimizations | |
1557 | during CSE. We mask out the non-HIGH bits, and matches | |
1558 | a plain movdi, to alleviate this problem. */ | |
1559 | static void | |
fc27d102 | 1560 | sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val) |
9208e4b2 DM |
1561 | { |
1562 | emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val))); | |
1563 | } | |
2a01c939 | 1564 | |
e0d80184 | 1565 | static rtx |
fc27d102 | 1566 | gen_safe_SET64 (rtx dest, HOST_WIDE_INT val) |
61a55e8b | 1567 | { |
9208e4b2 DM |
1568 | return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val)); |
1569 | } | |
1570 | ||
1571 | static rtx | |
fc27d102 | 1572 | gen_safe_OR64 (rtx src, HOST_WIDE_INT val) |
9208e4b2 DM |
1573 | { |
1574 | return gen_rtx_IOR (DImode, src, GEN_INT64 (val)); | |
1575 | } | |
1576 | ||
1577 | static rtx | |
fc27d102 | 1578 | gen_safe_XOR64 (rtx src, HOST_WIDE_INT val) |
9208e4b2 DM |
1579 | { |
1580 | return gen_rtx_XOR (DImode, src, GEN_INT64 (val)); | |
e0d80184 | 1581 | } |
61a55e8b | 1582 | |
e0d80184 DM |
1583 | /* Worker routines for 64-bit constant formation on arch64. |
1584 | One of the key things to be doing in these emissions is | |
1585 | to create as many temp REGs as possible. This makes it | |
1586 | possible for half-built constants to be used later when | |
1587 | such values are similar to something required later on. | |
1588 | Without doing this, the optimizer cannot see such | |
1589 | opportunities. */ | |
2a01c939 | 1590 | |
e80d5f80 KG |
1591 | static void sparc_emit_set_const64_quick1 (rtx, rtx, |
1592 | unsigned HOST_WIDE_INT, int); | |
2a01c939 | 1593 | |
e0d80184 | 1594 | static void |
fc27d102 KG |
1595 | sparc_emit_set_const64_quick1 (rtx op0, rtx temp, |
1596 | unsigned HOST_WIDE_INT low_bits, int is_neg) | |
e0d80184 | 1597 | { |
2a01c939 | 1598 | unsigned HOST_WIDE_INT high_bits; |
a9e27770 | 1599 | |
e0d80184 | 1600 | if (is_neg) |
2a01c939 | 1601 | high_bits = (~low_bits) & 0xffffffff; |
31bc9eba | 1602 | else |
e0d80184 | 1603 | high_bits = low_bits; |
31bc9eba | 1604 | |
9208e4b2 | 1605 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1606 | if (!is_neg) |
5108f3e5 DM |
1607 | { |
1608 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1609 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
1610 | } | |
e0d80184 | 1611 | else |
5108f3e5 DM |
1612 | { |
1613 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
1614 | instead. This way the combiner will notice logical operations | |
1615 | such as ANDN later on and substitute. */ | |
1616 | if ((low_bits & 0x3ff) == 0x3ff) | |
1617 | { | |
1618 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1619 | gen_rtx_NOT (DImode, temp))); | |
1620 | } | |
1621 | else | |
1622 | { | |
1623 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1624 | gen_safe_XOR64 (temp, | |
9e0625a3 AO |
1625 | (-(HOST_WIDE_INT)0x400 |
1626 | | (low_bits & 0x3ff))))); | |
5108f3e5 DM |
1627 | } |
1628 | } | |
e0d80184 | 1629 | } |
61a55e8b | 1630 | |
e80d5f80 KG |
1631 | static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT, |
1632 | unsigned HOST_WIDE_INT, int); | |
2a01c939 | 1633 | |
e0d80184 | 1634 | static void |
fc27d102 KG |
1635 | sparc_emit_set_const64_quick2 (rtx op0, rtx temp, |
1636 | unsigned HOST_WIDE_INT high_bits, | |
1637 | unsigned HOST_WIDE_INT low_immediate, | |
1638 | int shift_count) | |
e0d80184 DM |
1639 | { |
1640 | rtx temp2 = op0; | |
61a55e8b | 1641 | |
e0d80184 DM |
1642 | if ((high_bits & 0xfffffc00) != 0) |
1643 | { | |
9208e4b2 | 1644 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1645 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 DM |
1646 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1647 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
61a55e8b | 1648 | else |
e0d80184 | 1649 | temp2 = temp; |
61a55e8b DE |
1650 | } |
1651 | else | |
1652 | { | |
f710f868 | 1653 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 DM |
1654 | temp2 = temp; |
1655 | } | |
61a55e8b | 1656 | |
80ffc95e | 1657 | /* Now shift it up into place. */ |
9208e4b2 | 1658 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1659 | gen_rtx_ASHIFT (DImode, temp2, |
1660 | GEN_INT (shift_count)))); | |
61a55e8b | 1661 | |
e0d80184 DM |
1662 | /* If there is a low immediate part piece, finish up by |
1663 | putting that in as well. */ | |
1664 | if (low_immediate != 0) | |
9208e4b2 DM |
1665 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1666 | gen_safe_OR64 (op0, low_immediate))); | |
ab835497 RK |
1667 | } |
1668 | ||
e80d5f80 KG |
1669 | static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT, |
1670 | unsigned HOST_WIDE_INT); | |
2a01c939 | 1671 | |
e0d80184 DM |
1672 | /* Full 64-bit constant decomposition. Even though this is the |
1673 | 'worst' case, we still optimize a few things away. */ | |
1674 | static void | |
fc27d102 KG |
1675 | sparc_emit_set_const64_longway (rtx op0, rtx temp, |
1676 | unsigned HOST_WIDE_INT high_bits, | |
1677 | unsigned HOST_WIDE_INT low_bits) | |
ab835497 | 1678 | { |
e0d80184 | 1679 | rtx sub_temp; |
4bf7135b | 1680 | |
e0d80184 DM |
1681 | if (reload_in_progress || reload_completed) |
1682 | sub_temp = op0; | |
1683 | else | |
1684 | sub_temp = gen_reg_rtx (DImode); | |
1685 | ||
1686 | if ((high_bits & 0xfffffc00) != 0) | |
1687 | { | |
9208e4b2 | 1688 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1689 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 | 1690 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1691 | sub_temp, |
9208e4b2 | 1692 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); |
e0d80184 DM |
1693 | else |
1694 | sub_temp = temp; | |
1695 | } | |
1696 | else | |
ab835497 | 1697 | { |
f710f868 | 1698 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 | 1699 | sub_temp = temp; |
ab835497 | 1700 | } |
4bf7135b | 1701 | |
e0d80184 | 1702 | if (!reload_in_progress && !reload_completed) |
284d86e9 | 1703 | { |
e0d80184 DM |
1704 | rtx temp2 = gen_reg_rtx (DImode); |
1705 | rtx temp3 = gen_reg_rtx (DImode); | |
1706 | rtx temp4 = gen_reg_rtx (DImode); | |
284d86e9 | 1707 | |
9208e4b2 | 1708 | emit_insn (gen_rtx_SET (VOIDmode, temp4, |
e0d80184 DM |
1709 | gen_rtx_ASHIFT (DImode, sub_temp, |
1710 | GEN_INT (32)))); | |
4bf7135b | 1711 | |
9208e4b2 | 1712 | sparc_emit_set_safe_HIGH64 (temp2, low_bits); |
e0d80184 | 1713 | if ((low_bits & ~0xfffffc00) != 0) |
f710f868 DM |
1714 | { |
1715 | emit_insn (gen_rtx_SET (VOIDmode, temp3, | |
1716 | gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); | |
1717 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1718 | gen_rtx_PLUS (DImode, temp4, temp3))); | |
1719 | } | |
1720 | else | |
1721 | { | |
1722 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1723 | gen_rtx_PLUS (DImode, temp4, temp2))); | |
1724 | } | |
284d86e9 | 1725 | } |
e0d80184 DM |
1726 | else |
1727 | { | |
9208e4b2 DM |
1728 | rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); |
1729 | rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); | |
1730 | rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); | |
e0d80184 | 1731 | int to_shift = 12; |
284d86e9 | 1732 | |
e0d80184 DM |
1733 | /* We are in the middle of reload, so this is really |
1734 | painful. However we do still make an attempt to | |
5108f3e5 | 1735 | avoid emitting truly stupid code. */ |
e0d80184 DM |
1736 | if (low1 != const0_rtx) |
1737 | { | |
9208e4b2 | 1738 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1739 | gen_rtx_ASHIFT (DImode, sub_temp, |
2a01c939 | 1740 | GEN_INT (to_shift)))); |
9208e4b2 | 1741 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1742 | gen_rtx_IOR (DImode, op0, low1))); |
1743 | sub_temp = op0; | |
1744 | to_shift = 12; | |
1745 | } | |
1746 | else | |
1747 | { | |
1748 | to_shift += 12; | |
1749 | } | |
1750 | if (low2 != const0_rtx) | |
1751 | { | |
9208e4b2 | 1752 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1753 | gen_rtx_ASHIFT (DImode, sub_temp, |
1754 | GEN_INT (to_shift)))); | |
9208e4b2 | 1755 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1756 | gen_rtx_IOR (DImode, op0, low2))); |
1757 | sub_temp = op0; | |
1758 | to_shift = 8; | |
1759 | } | |
1760 | else | |
1761 | { | |
1762 | to_shift += 8; | |
1763 | } | |
9208e4b2 | 1764 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1765 | gen_rtx_ASHIFT (DImode, sub_temp, |
1766 | GEN_INT (to_shift)))); | |
1767 | if (low3 != const0_rtx) | |
9208e4b2 | 1768 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1769 | gen_rtx_IOR (DImode, op0, low3))); |
80ffc95e | 1770 | /* phew... */ |
e0d80184 | 1771 | } |
284d86e9 JC |
1772 | } |
1773 | ||
80ffc95e | 1774 | /* Analyze a 64-bit constant for certain properties. */ |
e80d5f80 KG |
1775 | static void analyze_64bit_constant (unsigned HOST_WIDE_INT, |
1776 | unsigned HOST_WIDE_INT, | |
1777 | int *, int *, int *); | |
2a01c939 | 1778 | |
e0d80184 | 1779 | static void |
fc27d102 KG |
1780 | analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits, |
1781 | unsigned HOST_WIDE_INT low_bits, | |
1782 | int *hbsp, int *lbsp, int *abbasp) | |
ab835497 | 1783 | { |
e0d80184 DM |
1784 | int lowest_bit_set, highest_bit_set, all_bits_between_are_set; |
1785 | int i; | |
ab835497 | 1786 | |
e0d80184 DM |
1787 | lowest_bit_set = highest_bit_set = -1; |
1788 | i = 0; | |
1789 | do | |
ab835497 | 1790 | { |
e0d80184 DM |
1791 | if ((lowest_bit_set == -1) |
1792 | && ((low_bits >> i) & 1)) | |
1793 | lowest_bit_set = i; | |
1794 | if ((highest_bit_set == -1) | |
1795 | && ((high_bits >> (32 - i - 1)) & 1)) | |
1796 | highest_bit_set = (64 - i - 1); | |
1797 | } | |
1798 | while (++i < 32 | |
1799 | && ((highest_bit_set == -1) | |
1800 | || (lowest_bit_set == -1))); | |
1801 | if (i == 32) | |
1802 | { | |
1803 | i = 0; | |
1804 | do | |
ab835497 | 1805 | { |
e0d80184 DM |
1806 | if ((lowest_bit_set == -1) |
1807 | && ((high_bits >> i) & 1)) | |
1808 | lowest_bit_set = i + 32; | |
1809 | if ((highest_bit_set == -1) | |
1810 | && ((low_bits >> (32 - i - 1)) & 1)) | |
1811 | highest_bit_set = 32 - i - 1; | |
ab835497 | 1812 | } |
e0d80184 DM |
1813 | while (++i < 32 |
1814 | && ((highest_bit_set == -1) | |
1815 | || (lowest_bit_set == -1))); | |
1816 | } | |
1817 | /* If there are no bits set this should have gone out | |
1818 | as one instruction! */ | |
1819 | if (lowest_bit_set == -1 | |
1820 | || highest_bit_set == -1) | |
9208e4b2 | 1821 | abort (); |
e0d80184 DM |
1822 | all_bits_between_are_set = 1; |
1823 | for (i = lowest_bit_set; i <= highest_bit_set; i++) | |
1824 | { | |
1825 | if (i < 32) | |
1826 | { | |
1827 | if ((low_bits & (1 << i)) != 0) | |
1828 | continue; | |
1829 | } | |
1830 | else | |
1831 | { | |
1832 | if ((high_bits & (1 << (i - 32))) != 0) | |
1833 | continue; | |
1834 | } | |
1835 | all_bits_between_are_set = 0; | |
1836 | break; | |
ab835497 | 1837 | } |
e0d80184 DM |
1838 | *hbsp = highest_bit_set; |
1839 | *lbsp = lowest_bit_set; | |
1840 | *abbasp = all_bits_between_are_set; | |
ab835497 | 1841 | } |
6a4bb1fa | 1842 | |
e80d5f80 | 1843 | static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT); |
2a01c939 | 1844 | |
e0d80184 | 1845 | static int |
fc27d102 KG |
1846 | const64_is_2insns (unsigned HOST_WIDE_INT high_bits, |
1847 | unsigned HOST_WIDE_INT low_bits) | |
e0d80184 DM |
1848 | { |
1849 | int highest_bit_set, lowest_bit_set, all_bits_between_are_set; | |
284d86e9 | 1850 | |
e0d80184 | 1851 | if (high_bits == 0 |
f451b552 | 1852 | || high_bits == 0xffffffff) |
e0d80184 | 1853 | return 1; |
6a4bb1fa | 1854 | |
e0d80184 DM |
1855 | analyze_64bit_constant (high_bits, low_bits, |
1856 | &highest_bit_set, &lowest_bit_set, | |
1857 | &all_bits_between_are_set); | |
6a4bb1fa | 1858 | |
f710f868 DM |
1859 | if ((highest_bit_set == 63 |
1860 | || lowest_bit_set == 0) | |
e0d80184 DM |
1861 | && all_bits_between_are_set != 0) |
1862 | return 1; | |
6a4bb1fa | 1863 | |
9208e4b2 DM |
1864 | if ((highest_bit_set - lowest_bit_set) < 21) |
1865 | return 1; | |
1866 | ||
6a4bb1fa DE |
1867 | return 0; |
1868 | } | |
1869 | ||
e80d5f80 KG |
1870 | static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT, |
1871 | unsigned HOST_WIDE_INT, | |
1872 | int, int); | |
2a01c939 DM |
1873 | |
1874 | static unsigned HOST_WIDE_INT | |
fc27d102 KG |
1875 | create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits, |
1876 | unsigned HOST_WIDE_INT low_bits, | |
1877 | int lowest_bit_set, int shift) | |
ab835497 | 1878 | { |
f710f868 | 1879 | HOST_WIDE_INT hi, lo; |
ab835497 | 1880 | |
e0d80184 DM |
1881 | if (lowest_bit_set < 32) |
1882 | { | |
1883 | lo = (low_bits >> lowest_bit_set) << shift; | |
1884 | hi = ((high_bits << (32 - lowest_bit_set)) << shift); | |
1885 | } | |
1886 | else | |
1887 | { | |
1888 | lo = 0; | |
1889 | hi = ((high_bits >> (lowest_bit_set - 32)) << shift); | |
1890 | } | |
1891 | if (hi & lo) | |
9208e4b2 | 1892 | abort (); |
e0d80184 DM |
1893 | return (hi | lo); |
1894 | } | |
ab835497 | 1895 | |
e0d80184 DM |
1896 | /* Here we are sure to be arch64 and this is an integer constant |
1897 | being loaded into a register. Emit the most efficient | |
1898 | insn sequence possible. Detection of all the 1-insn cases | |
1899 | has been done already. */ | |
1900 | void | |
fc27d102 | 1901 | sparc_emit_set_const64 (rtx op0, rtx op1) |
e0d80184 | 1902 | { |
2a01c939 | 1903 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1904 | int lowest_bit_set, highest_bit_set; |
1905 | int all_bits_between_are_set; | |
e0d80184 | 1906 | rtx temp; |
ab835497 | 1907 | |
e0d80184 | 1908 | /* Sanity check that we know what we are working with. */ |
380f6ad3 | 1909 | if (! TARGET_ARCH64) |
9208e4b2 | 1910 | abort (); |
95726648 | 1911 | |
380f6ad3 JJ |
1912 | if (GET_CODE (op0) != SUBREG) |
1913 | { | |
1914 | if (GET_CODE (op0) != REG | |
1915 | || (REGNO (op0) >= SPARC_FIRST_FP_REG | |
1916 | && REGNO (op0) <= SPARC_LAST_V9_FP_REG)) | |
1917 | abort (); | |
1918 | } | |
1919 | ||
f710f868 DM |
1920 | if (reload_in_progress || reload_completed) |
1921 | temp = op0; | |
1922 | else | |
1923 | temp = gen_reg_rtx (DImode); | |
1924 | ||
e0d80184 DM |
1925 | if (GET_CODE (op1) != CONST_DOUBLE |
1926 | && GET_CODE (op1) != CONST_INT) | |
1927 | { | |
5f78aa30 JC |
1928 | sparc_emit_set_symbolic_const64 (op0, op1, temp); |
1929 | return; | |
e0d80184 | 1930 | } |
ab835497 | 1931 | |
e0d80184 DM |
1932 | if (GET_CODE (op1) == CONST_DOUBLE) |
1933 | { | |
1934 | #if HOST_BITS_PER_WIDE_INT == 64 | |
2a01c939 | 1935 | high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff; |
e0d80184 DM |
1936 | low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff; |
1937 | #else | |
1938 | high_bits = CONST_DOUBLE_HIGH (op1); | |
1939 | low_bits = CONST_DOUBLE_LOW (op1); | |
1940 | #endif | |
ab835497 | 1941 | } |
e0d80184 | 1942 | else |
ab835497 | 1943 | { |
e0d80184 | 1944 | #if HOST_BITS_PER_WIDE_INT == 64 |
2a01c939 | 1945 | high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); |
e0d80184 DM |
1946 | low_bits = (INTVAL (op1) & 0xffffffff); |
1947 | #else | |
1948 | high_bits = ((INTVAL (op1) < 0) ? | |
1949 | 0xffffffff : | |
1950 | 0x00000000); | |
1951 | low_bits = INTVAL (op1); | |
1952 | #endif | |
1953 | } | |
ab835497 | 1954 | |
e0d80184 DM |
1955 | /* low_bits bits 0 --> 31 |
1956 | high_bits bits 32 --> 63 */ | |
ab835497 | 1957 | |
e0d80184 DM |
1958 | analyze_64bit_constant (high_bits, low_bits, |
1959 | &highest_bit_set, &lowest_bit_set, | |
1960 | &all_bits_between_are_set); | |
1961 | ||
1962 | /* First try for a 2-insn sequence. */ | |
1963 | ||
1964 | /* These situations are preferred because the optimizer can | |
1965 | * do more things with them: | |
1966 | * 1) mov -1, %reg | |
1967 | * sllx %reg, shift, %reg | |
1968 | * 2) mov -1, %reg | |
1969 | * srlx %reg, shift, %reg | |
1970 | * 3) mov some_small_const, %reg | |
1971 | * sllx %reg, shift, %reg | |
1972 | */ | |
1973 | if (((highest_bit_set == 63 | |
1974 | || lowest_bit_set == 0) | |
1975 | && all_bits_between_are_set != 0) | |
2a01c939 | 1976 | || ((highest_bit_set - lowest_bit_set) < 12)) |
e0d80184 | 1977 | { |
9208e4b2 | 1978 | HOST_WIDE_INT the_const = -1; |
e0d80184 DM |
1979 | int shift = lowest_bit_set; |
1980 | ||
f710f868 DM |
1981 | if ((highest_bit_set != 63 |
1982 | && lowest_bit_set != 0) | |
1983 | || all_bits_between_are_set == 0) | |
ab835497 | 1984 | { |
e0d80184 | 1985 | the_const = |
9208e4b2 | 1986 | create_simple_focus_bits (high_bits, low_bits, |
9208e4b2 | 1987 | lowest_bit_set, 0); |
ab835497 | 1988 | } |
e0d80184 | 1989 | else if (lowest_bit_set == 0) |
9208e4b2 | 1990 | shift = -(63 - highest_bit_set); |
e0d80184 | 1991 | |
f710f868 DM |
1992 | if (! SPARC_SIMM13_P (the_const)) |
1993 | abort (); | |
1994 | ||
9208e4b2 | 1995 | emit_insn (gen_safe_SET64 (temp, the_const)); |
e0d80184 | 1996 | if (shift > 0) |
9208e4b2 | 1997 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 DM |
1998 | op0, |
1999 | gen_rtx_ASHIFT (DImode, | |
2000 | temp, | |
2001 | GEN_INT (shift)))); | |
2002 | else if (shift < 0) | |
9208e4b2 | 2003 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 2004 | op0, |
9208e4b2 | 2005 | gen_rtx_LSHIFTRT (DImode, |
e0d80184 DM |
2006 | temp, |
2007 | GEN_INT (-shift)))); | |
ab835497 RK |
2008 | else |
2009 | abort (); | |
e0d80184 DM |
2010 | return; |
2011 | } | |
ab835497 | 2012 | |
e0d80184 DM |
2013 | /* Now a range of 22 or less bits set somewhere. |
2014 | * 1) sethi %hi(focus_bits), %reg | |
2015 | * sllx %reg, shift, %reg | |
2016 | * 2) sethi %hi(focus_bits), %reg | |
2017 | * srlx %reg, shift, %reg | |
2018 | */ | |
2a01c939 | 2019 | if ((highest_bit_set - lowest_bit_set) < 21) |
e0d80184 | 2020 | { |
2a01c939 | 2021 | unsigned HOST_WIDE_INT focus_bits = |
e0d80184 | 2022 | create_simple_focus_bits (high_bits, low_bits, |
ddf80874 | 2023 | lowest_bit_set, 10); |
f710f868 DM |
2024 | |
2025 | if (! SPARC_SETHI_P (focus_bits)) | |
2026 | abort (); | |
2027 | ||
9208e4b2 | 2028 | sparc_emit_set_safe_HIGH64 (temp, focus_bits); |
e0d80184 | 2029 | |
9208e4b2 | 2030 | /* If lowest_bit_set == 10 then a sethi alone could have done it. */ |
e0d80184 | 2031 | if (lowest_bit_set < 10) |
9208e4b2 | 2032 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 2033 | op0, |
9208e4b2 | 2034 | gen_rtx_LSHIFTRT (DImode, temp, |
e0d80184 | 2035 | GEN_INT (10 - lowest_bit_set)))); |
9208e4b2 DM |
2036 | else if (lowest_bit_set > 10) |
2037 | emit_insn (gen_rtx_SET (VOIDmode, | |
e0d80184 DM |
2038 | op0, |
2039 | gen_rtx_ASHIFT (DImode, temp, | |
2040 | GEN_INT (lowest_bit_set - 10)))); | |
2041 | else | |
9208e4b2 | 2042 | abort (); |
e0d80184 DM |
2043 | return; |
2044 | } | |
2045 | ||
2046 | /* 1) sethi %hi(low_bits), %reg | |
2047 | * or %reg, %lo(low_bits), %reg | |
2048 | * 2) sethi %hi(~low_bits), %reg | |
2049 | * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg | |
2050 | */ | |
2051 | if (high_bits == 0 | |
2a01c939 | 2052 | || high_bits == 0xffffffff) |
5f78aa30 JC |
2053 | { |
2054 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, | |
2055 | (high_bits == 0xffffffff)); | |
2056 | return; | |
2057 | } | |
e0d80184 | 2058 | |
f710f868 DM |
2059 | /* Now, try 3-insn sequences. */ |
2060 | ||
e0d80184 DM |
2061 | /* 1) sethi %hi(high_bits), %reg |
2062 | * or %reg, %lo(high_bits), %reg | |
2063 | * sllx %reg, 32, %reg | |
2064 | */ | |
f710f868 | 2065 | if (low_bits == 0) |
5f78aa30 | 2066 | { |
f710f868 | 2067 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); |
5f78aa30 JC |
2068 | return; |
2069 | } | |
e0d80184 | 2070 | |
f710f868 DM |
2071 | /* We may be able to do something quick |
2072 | when the constant is negated, so try that. */ | |
e0d80184 DM |
2073 | if (const64_is_2insns ((~high_bits) & 0xffffffff, |
2074 | (~low_bits) & 0xfffffc00)) | |
2075 | { | |
5108f3e5 DM |
2076 | /* NOTE: The trailing bits get XOR'd so we need the |
2077 | non-negated bits, not the negated ones. */ | |
2078 | unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; | |
e0d80184 DM |
2079 | |
2080 | if ((((~high_bits) & 0xffffffff) == 0 | |
2081 | && ((~low_bits) & 0x80000000) == 0) | |
2082 | || (((~high_bits) & 0xffffffff) == 0xffffffff | |
2083 | && ((~low_bits) & 0x80000000) != 0)) | |
ab835497 | 2084 | { |
5108f3e5 | 2085 | int fast_int = (~low_bits & 0xffffffff); |
e0d80184 | 2086 | |
5108f3e5 DM |
2087 | if ((SPARC_SETHI_P (fast_int) |
2088 | && (~high_bits & 0xffffffff) == 0) | |
2089 | || SPARC_SIMM13_P (fast_int)) | |
9208e4b2 | 2090 | emit_insn (gen_safe_SET64 (temp, fast_int)); |
ab835497 | 2091 | else |
9208e4b2 | 2092 | sparc_emit_set_const64 (temp, GEN_INT64 (fast_int)); |
ab835497 | 2093 | } |
e0d80184 DM |
2094 | else |
2095 | { | |
2096 | rtx negated_const; | |
2097 | #if HOST_BITS_PER_WIDE_INT == 64 | |
2098 | negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | | |
2099 | (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); | |
2100 | #else | |
5692c7bc ZW |
2101 | negated_const = immed_double_const ((~low_bits) & 0xfffffc00, |
2102 | (~high_bits) & 0xffffffff, | |
2103 | DImode); | |
e0d80184 DM |
2104 | #endif |
2105 | sparc_emit_set_const64 (temp, negated_const); | |
2106 | } | |
5108f3e5 DM |
2107 | |
2108 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
2109 | instead. This way the combiner will notice logical operations | |
2110 | such as ANDN later on and substitute. */ | |
2111 | if (trailing_bits == 0x3ff) | |
2112 | { | |
2113 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
2114 | gen_rtx_NOT (DImode, temp))); | |
2115 | } | |
2116 | else | |
2117 | { | |
2118 | emit_insn (gen_rtx_SET (VOIDmode, | |
2119 | op0, | |
2120 | gen_safe_XOR64 (temp, | |
2121 | (-0x400 | trailing_bits)))); | |
2122 | } | |
e0d80184 | 2123 | return; |
ab835497 | 2124 | } |
ab835497 | 2125 | |
e0d80184 DM |
2126 | /* 1) sethi %hi(xxx), %reg |
2127 | * or %reg, %lo(xxx), %reg | |
2128 | * sllx %reg, yyy, %reg | |
f710f868 DM |
2129 | * |
2130 | * ??? This is just a generalized version of the low_bits==0 | |
2131 | * thing above, FIXME... | |
e0d80184 DM |
2132 | */ |
2133 | if ((highest_bit_set - lowest_bit_set) < 32) | |
2134 | { | |
f710f868 DM |
2135 | unsigned HOST_WIDE_INT focus_bits = |
2136 | create_simple_focus_bits (high_bits, low_bits, | |
ddf80874 | 2137 | lowest_bit_set, 0); |
ab835497 | 2138 | |
e0d80184 DM |
2139 | /* We can't get here in this state. */ |
2140 | if (highest_bit_set < 32 | |
2141 | || lowest_bit_set >= 32) | |
9208e4b2 | 2142 | abort (); |
95726648 | 2143 | |
e0d80184 DM |
2144 | /* So what we know is that the set bits straddle the |
2145 | middle of the 64-bit word. */ | |
5f78aa30 JC |
2146 | sparc_emit_set_const64_quick2 (op0, temp, |
2147 | focus_bits, 0, | |
2148 | lowest_bit_set); | |
2149 | return; | |
e0d80184 | 2150 | } |
c85f7c16 | 2151 | |
f710f868 DM |
2152 | /* 1) sethi %hi(high_bits), %reg |
2153 | * or %reg, %lo(high_bits), %reg | |
2154 | * sllx %reg, 32, %reg | |
2155 | * or %reg, low_bits, %reg | |
2156 | */ | |
2157 | if (SPARC_SIMM13_P(low_bits) | |
2158 | && ((int)low_bits > 0)) | |
2159 | { | |
2160 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); | |
2161 | return; | |
2162 | } | |
2163 | ||
80ffc95e | 2164 | /* The easiest way when all else fails, is full decomposition. */ |
e0d80184 DM |
2165 | #if 0 |
2166 | printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", | |
2167 | high_bits, low_bits, ~high_bits, ~low_bits); | |
2168 | #endif | |
2169 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); | |
c85f7c16 JL |
2170 | } |
2171 | ||
e267e177 RH |
2172 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
2173 | return the mode to be used for the comparison. For floating-point, | |
2174 | CCFP[E]mode is used. CC_NOOVmode should be used when the first operand | |
2175 | is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special | |
2176 | processing is needed. */ | |
2177 | ||
2178 | enum machine_mode | |
fc27d102 | 2179 | select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED) |
e267e177 RH |
2180 | { |
2181 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2182 | { | |
2183 | switch (op) | |
2184 | { | |
2185 | case EQ: | |
2186 | case NE: | |
2187 | case UNORDERED: | |
2188 | case ORDERED: | |
2189 | case UNLT: | |
2190 | case UNLE: | |
2191 | case UNGT: | |
2192 | case UNGE: | |
2193 | case UNEQ: | |
7913f3d0 | 2194 | case LTGT: |
e267e177 RH |
2195 | return CCFPmode; |
2196 | ||
2197 | case LT: | |
2198 | case LE: | |
2199 | case GT: | |
2200 | case GE: | |
2201 | return CCFPEmode; | |
2202 | ||
2203 | default: | |
2204 | abort (); | |
2205 | } | |
2206 | } | |
2207 | else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
2208 | || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) | |
2209 | { | |
2210 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
2211 | return CCX_NOOVmode; | |
2212 | else | |
2213 | return CC_NOOVmode; | |
2214 | } | |
2215 | else | |
2216 | { | |
2217 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
2218 | return CCXmode; | |
2219 | else | |
2220 | return CCmode; | |
2221 | } | |
2222 | } | |
2223 | ||
e0d80184 DM |
2224 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
2225 | return the rtx for the cc reg in the proper mode. */ | |
c85f7c16 | 2226 | |
e0d80184 | 2227 | rtx |
fc27d102 | 2228 | gen_compare_reg (enum rtx_code code, rtx x, rtx y) |
c85f7c16 | 2229 | { |
e0d80184 DM |
2230 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); |
2231 | rtx cc_reg; | |
c85f7c16 | 2232 | |
e0d80184 DM |
2233 | /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the |
2234 | fcc regs (cse can't tell they're really call clobbered regs and will | |
2235 | remove a duplicate comparison even if there is an intervening function | |
2236 | call - it will then try to reload the cc reg via an int reg which is why | |
2237 | we need the movcc patterns). It is possible to provide the movcc | |
2238 | patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two | |
2239 | registers (say %g1,%g5) and it takes about 6 insns. A better fix would be | |
2240 | to tell cse that CCFPE mode registers (even pseudos) are call | |
2241 | clobbered. */ | |
c85f7c16 | 2242 | |
e0d80184 DM |
2243 | /* ??? This is an experiment. Rather than making changes to cse which may |
2244 | or may not be easy/clean, we do our own cse. This is possible because | |
2245 | we will generate hard registers. Cse knows they're call clobbered (it | |
2246 | doesn't know the same thing about pseudos). If we guess wrong, no big | |
2247 | deal, but if we win, great! */ | |
c85f7c16 | 2248 | |
e0d80184 DM |
2249 | if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) |
2250 | #if 1 /* experiment */ | |
284d86e9 | 2251 | { |
e0d80184 DM |
2252 | int reg; |
2253 | /* We cycle through the registers to ensure they're all exercised. */ | |
2254 | static int next_fcc_reg = 0; | |
2255 | /* Previous x,y for each fcc reg. */ | |
2256 | static rtx prev_args[4][2]; | |
284d86e9 | 2257 | |
e0d80184 DM |
2258 | /* Scan prev_args for x,y. */ |
2259 | for (reg = 0; reg < 4; reg++) | |
2260 | if (prev_args[reg][0] == x && prev_args[reg][1] == y) | |
2261 | break; | |
2262 | if (reg == 4) | |
2263 | { | |
2264 | reg = next_fcc_reg; | |
2265 | prev_args[reg][0] = x; | |
2266 | prev_args[reg][1] = y; | |
2267 | next_fcc_reg = (next_fcc_reg + 1) & 3; | |
2268 | } | |
2269 | cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); | |
284d86e9 | 2270 | } |
e0d80184 DM |
2271 | #else |
2272 | cc_reg = gen_reg_rtx (mode); | |
2273 | #endif /* ! experiment */ | |
2274 | else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2275 | cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); | |
2276 | else | |
2277 | cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); | |
284d86e9 | 2278 | |
e0d80184 DM |
2279 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, |
2280 | gen_rtx_COMPARE (mode, x, y))); | |
c85f7c16 | 2281 | |
e0d80184 DM |
2282 | return cc_reg; |
2283 | } | |
c85f7c16 | 2284 | |
e0d80184 DM |
2285 | /* This function is used for v9 only. |
2286 | CODE is the code for an Scc's comparison. | |
2287 | OPERANDS[0] is the target of the Scc insn. | |
2288 | OPERANDS[1] is the value we compare against const0_rtx (which hasn't | |
2289 | been generated yet). | |
c85f7c16 | 2290 | |
e0d80184 | 2291 | This function is needed to turn |
ab835497 | 2292 | |
e0d80184 DM |
2293 | (set (reg:SI 110) |
2294 | (gt (reg:CCX 100 %icc) | |
2295 | (const_int 0))) | |
2296 | into | |
2297 | (set (reg:SI 110) | |
2298 | (gt:DI (reg:CCX 100 %icc) | |
2299 | (const_int 0))) | |
2300 | ||
2301 | IE: The instruction recognizer needs to see the mode of the comparison to | |
2302 | find the right instruction. We could use "gt:DI" right in the | |
2303 | define_expand, but leaving it out allows us to handle DI, SI, etc. | |
ab835497 | 2304 | |
e0d80184 DM |
2305 | We refer to the global sparc compare operands sparc_compare_op0 and |
2306 | sparc_compare_op1. */ | |
ab835497 RK |
2307 | |
2308 | int | |
fc27d102 | 2309 | gen_v9_scc (enum rtx_code compare_code, register rtx *operands) |
ab835497 | 2310 | { |
e0d80184 | 2311 | rtx temp, op0, op1; |
ab835497 | 2312 | |
e0d80184 DM |
2313 | if (! TARGET_ARCH64 |
2314 | && (GET_MODE (sparc_compare_op0) == DImode | |
2315 | || GET_MODE (operands[0]) == DImode)) | |
2316 | return 0; | |
7e2feebf | 2317 | |
a42519be | 2318 | op0 = sparc_compare_op0; |
e0d80184 DM |
2319 | op1 = sparc_compare_op1; |
2320 | ||
2321 | /* Try to use the movrCC insns. */ | |
2322 | if (TARGET_ARCH64 | |
2323 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
2324 | && op1 == const0_rtx | |
2325 | && v9_regcmp_p (compare_code)) | |
ab835497 | 2326 | { |
e0d80184 | 2327 | /* Special case for op0 != 0. This can be done with one instruction if |
a42519be | 2328 | operands[0] == sparc_compare_op0. */ |
e0d80184 DM |
2329 | |
2330 | if (compare_code == NE | |
2331 | && GET_MODE (operands[0]) == DImode | |
a42519be | 2332 | && rtx_equal_p (op0, operands[0])) |
ab835497 | 2333 | { |
e0d80184 DM |
2334 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], |
2335 | gen_rtx_IF_THEN_ELSE (DImode, | |
2336 | gen_rtx_fmt_ee (compare_code, DImode, | |
2337 | op0, const0_rtx), | |
2338 | const1_rtx, | |
2339 | operands[0]))); | |
ab835497 RK |
2340 | return 1; |
2341 | } | |
e0d80184 | 2342 | |
a42519be JJ |
2343 | if (reg_overlap_mentioned_p (operands[0], op0)) |
2344 | { | |
2345 | /* Handle the case where operands[0] == sparc_compare_op0. | |
2346 | We "early clobber" the result. */ | |
2347 | op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); | |
2348 | emit_move_insn (op0, sparc_compare_op0); | |
2349 | } | |
2350 | ||
e0d80184 DM |
2351 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); |
2352 | if (GET_MODE (op0) != DImode) | |
ab835497 | 2353 | { |
e0d80184 DM |
2354 | temp = gen_reg_rtx (DImode); |
2355 | convert_move (temp, op0, 0); | |
ab835497 | 2356 | } |
e0d80184 DM |
2357 | else |
2358 | temp = op0; | |
2359 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2360 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2361 | gen_rtx_fmt_ee (compare_code, DImode, | |
2362 | temp, const0_rtx), | |
2363 | const1_rtx, | |
2364 | operands[0]))); | |
95726648 DE |
2365 | return 1; |
2366 | } | |
e0d80184 | 2367 | else |
ab835497 | 2368 | { |
e0d80184 | 2369 | operands[1] = gen_compare_reg (compare_code, op0, op1); |
ab835497 | 2370 | |
e0d80184 | 2371 | switch (GET_MODE (operands[1])) |
ab835497 | 2372 | { |
e0d80184 DM |
2373 | case CCmode : |
2374 | case CCXmode : | |
2375 | case CCFPEmode : | |
2376 | case CCFPmode : | |
2377 | break; | |
2378 | default : | |
2379 | abort (); | |
ab835497 | 2380 | } |
e0d80184 DM |
2381 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); |
2382 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2383 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2384 | gen_rtx_fmt_ee (compare_code, | |
2385 | GET_MODE (operands[1]), | |
2386 | operands[1], const0_rtx), | |
2387 | const1_rtx, operands[0]))); | |
2388 | return 1; | |
ab835497 | 2389 | } |
ab835497 | 2390 | } |
4fb4e4b8 | 2391 | |
e0d80184 DM |
2392 | /* Emit a conditional jump insn for the v9 architecture using comparison code |
2393 | CODE and jump target LABEL. | |
2394 | This function exists to take advantage of the v9 brxx insns. */ | |
ab835497 | 2395 | |
e0d80184 | 2396 | void |
fc27d102 | 2397 | emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label) |
ab835497 | 2398 | { |
e0d80184 DM |
2399 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
2400 | pc_rtx, | |
2401 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
2402 | gen_rtx_fmt_ee (code, GET_MODE (op0), | |
2403 | op0, const0_rtx), | |
2404 | gen_rtx_LABEL_REF (VOIDmode, label), | |
2405 | pc_rtx))); | |
2406 | } | |
7b1ac798 JJ |
2407 | |
2408 | /* Generate a DFmode part of a hard TFmode register. | |
2409 | REG is the TFmode hard register, LOW is 1 for the | |
2410 | low 64bit of the register and 0 otherwise. | |
2411 | */ | |
2412 | rtx | |
fc27d102 | 2413 | gen_df_reg (rtx reg, int low) |
7b1ac798 JJ |
2414 | { |
2415 | int regno = REGNO (reg); | |
2416 | ||
2417 | if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) | |
2aac41d6 | 2418 | regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2; |
7b1ac798 JJ |
2419 | return gen_rtx_REG (DFmode, regno); |
2420 | } | |
e0d80184 | 2421 | \f |
73985940 RH |
2422 | /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value. |
2423 | Unlike normal calls, TFmode operands are passed by reference. It is | |
2424 | assumed that no more than 3 operands are required. */ | |
2425 | ||
2426 | static void | |
fc27d102 | 2427 | emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands) |
73985940 RH |
2428 | { |
2429 | rtx ret_slot = NULL, arg[3], func_sym; | |
4e7d5d27 | 2430 | int i; |
73985940 RH |
2431 | |
2432 | /* We only expect to be called for conversions, unary, and binary ops. */ | |
2433 | if (nargs < 2 || nargs > 3) | |
2434 | abort (); | |
2435 | ||
2436 | for (i = 0; i < nargs; ++i) | |
2437 | { | |
2438 | rtx this_arg = operands[i]; | |
2439 | rtx this_slot; | |
2440 | ||
2441 | /* TFmode arguments and return values are passed by reference. */ | |
2442 | if (GET_MODE (this_arg) == TFmode) | |
2443 | { | |
4e7d5d27 DM |
2444 | int force_stack_temp; |
2445 | ||
2446 | force_stack_temp = 0; | |
2447 | if (TARGET_BUGGY_QP_LIB && i == 0) | |
2448 | force_stack_temp = 1; | |
2449 | ||
2450 | if (GET_CODE (this_arg) == MEM | |
2451 | && ! force_stack_temp) | |
2452 | this_arg = XEXP (this_arg, 0); | |
2453 | else if (CONSTANT_P (this_arg) | |
2454 | && ! force_stack_temp) | |
73985940 RH |
2455 | { |
2456 | this_slot = force_const_mem (TFmode, this_arg); | |
2457 | this_arg = XEXP (this_slot, 0); | |
2458 | } | |
2459 | else | |
2460 | { | |
2461 | this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0); | |
2462 | ||
2463 | /* Operand 0 is the return value. We'll copy it out later. */ | |
2464 | if (i > 0) | |
2465 | emit_move_insn (this_slot, this_arg); | |
2466 | else | |
2467 | ret_slot = this_slot; | |
2468 | ||
2469 | this_arg = XEXP (this_slot, 0); | |
2470 | } | |
2471 | } | |
2472 | ||
2473 | arg[i] = this_arg; | |
2474 | } | |
2475 | ||
2476 | func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name); | |
2477 | ||
2478 | if (GET_MODE (operands[0]) == TFmode) | |
2479 | { | |
2480 | if (nargs == 2) | |
2481 | emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2, | |
2482 | arg[0], GET_MODE (arg[0]), | |
2483 | arg[1], GET_MODE (arg[1])); | |
2484 | else | |
2485 | emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3, | |
2486 | arg[0], GET_MODE (arg[0]), | |
2487 | arg[1], GET_MODE (arg[1]), | |
2488 | arg[2], GET_MODE (arg[2])); | |
2489 | ||
2490 | if (ret_slot) | |
2491 | emit_move_insn (operands[0], ret_slot); | |
2492 | } | |
2493 | else | |
2494 | { | |
2495 | rtx ret; | |
2496 | ||
2497 | if (nargs != 2) | |
2498 | abort (); | |
2499 | ||
2500 | ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL, | |
2501 | GET_MODE (operands[0]), 1, | |
2502 | arg[1], GET_MODE (arg[1])); | |
2503 | ||
2504 | if (ret != operands[0]) | |
2505 | emit_move_insn (operands[0], ret); | |
2506 | } | |
2507 | } | |
2508 | ||
2509 | /* Expand soft-float TFmode calls to sparc abi routines. */ | |
2510 | ||
2511 | static void | |
fc27d102 | 2512 | emit_soft_tfmode_binop (enum rtx_code code, rtx *operands) |
73985940 RH |
2513 | { |
2514 | const char *func; | |
2515 | ||
2516 | switch (code) | |
2517 | { | |
2518 | case PLUS: | |
2519 | func = "_Qp_add"; | |
2520 | break; | |
2521 | case MINUS: | |
2522 | func = "_Qp_sub"; | |
2523 | break; | |
2524 | case MULT: | |
2525 | func = "_Qp_mul"; | |
2526 | break; | |
2527 | case DIV: | |
2528 | func = "_Qp_div"; | |
2529 | break; | |
2530 | default: | |
2531 | abort (); | |
2532 | } | |
2533 | ||
2534 | emit_soft_tfmode_libcall (func, 3, operands); | |
2535 | } | |
2536 | ||
2537 | static void | |
fc27d102 | 2538 | emit_soft_tfmode_unop (enum rtx_code code, rtx *operands) |
73985940 RH |
2539 | { |
2540 | const char *func; | |
2541 | ||
2542 | switch (code) | |
2543 | { | |
2544 | case SQRT: | |
2545 | func = "_Qp_sqrt"; | |
2546 | break; | |
2547 | default: | |
2548 | abort (); | |
2549 | } | |
2550 | ||
2551 | emit_soft_tfmode_libcall (func, 2, operands); | |
2552 | } | |
2553 | ||
2554 | static void | |
fc27d102 | 2555 | emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands) |
73985940 RH |
2556 | { |
2557 | const char *func; | |
2558 | ||
2559 | switch (code) | |
2560 | { | |
2561 | case FLOAT_EXTEND: | |
2562 | switch (GET_MODE (operands[1])) | |
2563 | { | |
2564 | case SFmode: | |
2565 | func = "_Qp_stoq"; | |
2566 | break; | |
2567 | case DFmode: | |
2568 | func = "_Qp_dtoq"; | |
2569 | break; | |
2570 | default: | |
2571 | abort (); | |
2572 | } | |
2573 | break; | |
2574 | ||
2575 | case FLOAT_TRUNCATE: | |
2576 | switch (GET_MODE (operands[0])) | |
2577 | { | |
2578 | case SFmode: | |
2579 | func = "_Qp_qtos"; | |
2580 | break; | |
2581 | case DFmode: | |
2582 | func = "_Qp_qtod"; | |
2583 | break; | |
2584 | default: | |
2585 | abort (); | |
2586 | } | |
2587 | break; | |
2588 | ||
2589 | case FLOAT: | |
2590 | switch (GET_MODE (operands[1])) | |
2591 | { | |
2592 | case SImode: | |
2593 | func = "_Qp_itoq"; | |
2594 | break; | |
2595 | case DImode: | |
2596 | func = "_Qp_xtoq"; | |
2597 | break; | |
2598 | default: | |
2599 | abort (); | |
2600 | } | |
2601 | break; | |
2602 | ||
2603 | case UNSIGNED_FLOAT: | |
2604 | switch (GET_MODE (operands[1])) | |
2605 | { | |
2606 | case SImode: | |
2607 | func = "_Qp_uitoq"; | |
2608 | break; | |
2609 | case DImode: | |
2610 | func = "_Qp_uxtoq"; | |
2611 | break; | |
2612 | default: | |
2613 | abort (); | |
2614 | } | |
2615 | break; | |
2616 | ||
2617 | case FIX: | |
2618 | switch (GET_MODE (operands[0])) | |
2619 | { | |
2620 | case SImode: | |
2621 | func = "_Qp_qtoi"; | |
2622 | break; | |
2623 | case DImode: | |
2624 | func = "_Qp_qtox"; | |
2625 | break; | |
2626 | default: | |
2627 | abort (); | |
2628 | } | |
2629 | break; | |
2630 | ||
2631 | case UNSIGNED_FIX: | |
2632 | switch (GET_MODE (operands[0])) | |
2633 | { | |
2634 | case SImode: | |
2635 | func = "_Qp_qtoui"; | |
2636 | break; | |
2637 | case DImode: | |
2638 | func = "_Qp_qtoux"; | |
2639 | break; | |
2640 | default: | |
2641 | abort (); | |
2642 | } | |
2643 | break; | |
2644 | ||
2645 | default: | |
2646 | abort (); | |
2647 | } | |
2648 | ||
2649 | emit_soft_tfmode_libcall (func, 2, operands); | |
2650 | } | |
2651 | ||
2652 | /* Expand a hard-float tfmode operation. All arguments must be in | |
2653 | registers. */ | |
2654 | ||
2655 | static void | |
fc27d102 | 2656 | emit_hard_tfmode_operation (enum rtx_code code, rtx *operands) |
73985940 RH |
2657 | { |
2658 | rtx op, dest; | |
2659 | ||
2660 | if (GET_RTX_CLASS (code) == '1') | |
2661 | { | |
2662 | operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); | |
2663 | op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]); | |
2664 | } | |
2665 | else | |
2666 | { | |
2667 | operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); | |
2668 | operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); | |
2669 | op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]), | |
2670 | operands[1], operands[2]); | |
2671 | } | |
2672 | ||
2673 | if (register_operand (operands[0], VOIDmode)) | |
2674 | dest = operands[0]; | |
2675 | else | |
2676 | dest = gen_reg_rtx (GET_MODE (operands[0])); | |
2677 | ||
2678 | emit_insn (gen_rtx_SET (VOIDmode, dest, op)); | |
2679 | ||
2680 | if (dest != operands[0]) | |
2681 | emit_move_insn (operands[0], dest); | |
2682 | } | |
2683 | ||
2684 | void | |
fc27d102 | 2685 | emit_tfmode_binop (enum rtx_code code, rtx *operands) |
73985940 RH |
2686 | { |
2687 | if (TARGET_HARD_QUAD) | |
2688 | emit_hard_tfmode_operation (code, operands); | |
2689 | else | |
2690 | emit_soft_tfmode_binop (code, operands); | |
2691 | } | |
2692 | ||
2693 | void | |
fc27d102 | 2694 | emit_tfmode_unop (enum rtx_code code, rtx *operands) |
73985940 RH |
2695 | { |
2696 | if (TARGET_HARD_QUAD) | |
2697 | emit_hard_tfmode_operation (code, operands); | |
2698 | else | |
2699 | emit_soft_tfmode_unop (code, operands); | |
2700 | } | |
2701 | ||
2702 | void | |
fc27d102 | 2703 | emit_tfmode_cvt (enum rtx_code code, rtx *operands) |
73985940 RH |
2704 | { |
2705 | if (TARGET_HARD_QUAD) | |
2706 | emit_hard_tfmode_operation (code, operands); | |
2707 | else | |
2708 | emit_soft_tfmode_cvt (code, operands); | |
2709 | } | |
2710 | \f | |
e0d80184 DM |
2711 | /* Return nonzero if a return peephole merging return with |
2712 | setting of output register is ok. */ | |
2713 | int | |
fc27d102 | 2714 | leaf_return_peephole_ok (void) |
e0d80184 DM |
2715 | { |
2716 | return (actual_fsize == 0); | |
2717 | } | |
284d86e9 | 2718 | |
f17f9332 JJ |
2719 | /* Return nonzero if a branch/jump/call instruction will be emitting |
2720 | nop into its delay slot. */ | |
2721 | ||
2722 | int | |
fc27d102 | 2723 | empty_delay_slot (rtx insn) |
f17f9332 JJ |
2724 | { |
2725 | rtx seq; | |
2726 | ||
2727 | /* If no previous instruction (should not happen), return true. */ | |
2728 | if (PREV_INSN (insn) == NULL) | |
2729 | return 1; | |
2730 | ||
2731 | seq = NEXT_INSN (PREV_INSN (insn)); | |
2732 | if (GET_CODE (PATTERN (seq)) == SEQUENCE) | |
2733 | return 0; | |
2734 | ||
2735 | return 1; | |
2736 | } | |
2737 | ||
e0d80184 DM |
2738 | /* Return nonzero if TRIAL can go into the function epilogue's |
2739 | delay slot. SLOT is the slot we are trying to fill. */ | |
ab835497 | 2740 | |
e0d80184 | 2741 | int |
fc27d102 | 2742 | eligible_for_epilogue_delay (rtx trial, int slot) |
e0d80184 DM |
2743 | { |
2744 | rtx pat, src; | |
4fb4e4b8 | 2745 | |
e0d80184 DM |
2746 | if (slot >= 1) |
2747 | return 0; | |
4fb4e4b8 | 2748 | |
e0d80184 DM |
2749 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) |
2750 | return 0; | |
4fb4e4b8 | 2751 | |
e0d80184 DM |
2752 | if (get_attr_length (trial) != 1) |
2753 | return 0; | |
4fb4e4b8 | 2754 | |
e48addee JJ |
2755 | /* If there are any call-saved registers, we should scan TRIAL if it |
2756 | does not reference them. For now just make it easy. */ | |
2757 | if (num_gfregs) | |
2758 | return 0; | |
4fb4e4b8 | 2759 | |
1150a841 RH |
2760 | /* If the function uses __builtin_eh_return, the eh_return machinery |
2761 | occupies the delay slot. */ | |
2762 | if (current_function_calls_eh_return) | |
2763 | return 0; | |
2764 | ||
e0d80184 DM |
2765 | /* In the case of a true leaf function, anything can go into the delay slot. |
2766 | A delay slot only exists however if the frame size is zero, otherwise | |
2767 | we will put an insn to adjust the stack after the return. */ | |
54ff41b7 | 2768 | if (current_function_uses_only_leaf_regs) |
4fb4e4b8 | 2769 | { |
e0d80184 DM |
2770 | if (leaf_return_peephole_ok ()) |
2771 | return ((get_attr_in_uncond_branch_delay (trial) | |
2772 | == IN_BRANCH_DELAY_TRUE)); | |
2773 | return 0; | |
4fb4e4b8 | 2774 | } |
4fb4e4b8 | 2775 | |
e0d80184 | 2776 | pat = PATTERN (trial); |
795068a4 | 2777 | |
e0d80184 | 2778 | /* Otherwise, only operations which can be done in tandem with |
e48addee | 2779 | a `restore' or `return' insn can go into the delay slot. */ |
e0d80184 | 2780 | if (GET_CODE (SET_DEST (pat)) != REG |
e0d80184 DM |
2781 | || REGNO (SET_DEST (pat)) < 24) |
2782 | return 0; | |
795068a4 | 2783 | |
c137830f JJ |
2784 | /* If this instruction sets up floating point register and we have a return |
2785 | instruction, it can probably go in. But restore will not work | |
2786 | with FP_REGS. */ | |
2787 | if (REGNO (SET_DEST (pat)) >= 32) | |
2788 | { | |
2789 | if (TARGET_V9 && ! epilogue_renumber (&pat, 1) | |
2790 | && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) | |
2791 | return 1; | |
2792 | return 0; | |
2793 | } | |
2794 | ||
e0d80184 DM |
2795 | /* The set of insns matched here must agree precisely with the set of |
2796 | patterns paired with a RETURN in sparc.md. */ | |
795068a4 | 2797 | |
e0d80184 | 2798 | src = SET_SRC (pat); |
795068a4 | 2799 | |
3c6088d2 | 2800 | /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */ |
3ec6f1a9 RK |
2801 | if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2802 | && arith_operand (src, GET_MODE (src))) | |
3c6088d2 JJ |
2803 | { |
2804 | if (TARGET_ARCH64) | |
2805 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2806 | else | |
2807 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
2808 | } | |
e48addee | 2809 | |
e0d80184 | 2810 | /* This matches "*return_di". */ |
3ec6f1a9 RK |
2811 | else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2812 | && arith_double_operand (src, GET_MODE (src))) | |
e0d80184 | 2813 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); |
795068a4 | 2814 | |
e0d80184 DM |
2815 | /* This matches "*return_sf_no_fpu". */ |
2816 | else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) | |
2817 | && register_operand (src, SFmode)) | |
2818 | return 1; | |
f5da225e | 2819 | |
e48addee JJ |
2820 | /* If we have return instruction, anything that does not use |
2821 | local or output registers and can go into a delay slot wins. */ | |
2822 | else if (TARGET_V9 && ! epilogue_renumber (&pat, 1) | |
2823 | && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) | |
2824 | return 1; | |
2825 | ||
e0d80184 DM |
2826 | /* This matches "*return_addsi". */ |
2827 | else if (GET_CODE (src) == PLUS | |
2828 | && arith_operand (XEXP (src, 0), SImode) | |
2829 | && arith_operand (XEXP (src, 1), SImode) | |
2830 | && (register_operand (XEXP (src, 0), SImode) | |
2831 | || register_operand (XEXP (src, 1), SImode))) | |
2832 | return 1; | |
2833 | ||
2834 | /* This matches "*return_adddi". */ | |
2835 | else if (GET_CODE (src) == PLUS | |
2836 | && arith_double_operand (XEXP (src, 0), DImode) | |
2837 | && arith_double_operand (XEXP (src, 1), DImode) | |
2838 | && (register_operand (XEXP (src, 0), DImode) | |
2839 | || register_operand (XEXP (src, 1), DImode))) | |
795068a4 | 2840 | return 1; |
795068a4 | 2841 | |
e48addee JJ |
2842 | /* This can match "*return_losum_[sd]i". |
2843 | Catch only some cases, so that return_losum* don't have | |
2844 | to be too big. */ | |
2845 | else if (GET_CODE (src) == LO_SUM | |
2846 | && ! TARGET_CM_MEDMID | |
2847 | && ((register_operand (XEXP (src, 0), SImode) | |
2848 | && immediate_operand (XEXP (src, 1), SImode)) | |
2849 | || (TARGET_ARCH64 | |
2850 | && register_operand (XEXP (src, 0), DImode) | |
2851 | && immediate_operand (XEXP (src, 1), DImode)))) | |
2852 | return 1; | |
2853 | ||
2854 | /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */ | |
2855 | else if (GET_CODE (src) == ASHIFT | |
2856 | && (register_operand (XEXP (src, 0), SImode) | |
2857 | || register_operand (XEXP (src, 0), DImode)) | |
2858 | && XEXP (src, 1) == const1_rtx) | |
2859 | return 1; | |
2860 | ||
795068a4 JW |
2861 | return 0; |
2862 | } | |
2863 | ||
5751a10b JJ |
2864 | /* Return nonzero if TRIAL can go into the call delay slot. */ |
2865 | int | |
2866 | tls_call_delay (rtx trial) | |
2867 | { | |
2868 | rtx pat, unspec; | |
2869 | ||
2870 | /* Binutils allows | |
2871 | call __tls_get_addr, %tgd_call (foo) | |
2872 | add %l7, %o0, %o0, %tgd_add (foo) | |
2873 | while Sun as/ld does not. */ | |
2874 | if (TARGET_GNU_TLS || !TARGET_TLS) | |
2875 | return 1; | |
2876 | ||
2877 | pat = PATTERN (trial); | |
2878 | if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS) | |
2879 | return 1; | |
2880 | ||
2881 | unspec = XEXP (SET_DEST (pat), 1); | |
2882 | if (GET_CODE (unspec) != UNSPEC | |
2883 | || (XINT (unspec, 1) != UNSPEC_TLSGD | |
2884 | && XINT (unspec, 1) != UNSPEC_TLSLDM)) | |
2885 | return 1; | |
2886 | ||
2887 | return 0; | |
2888 | } | |
2889 | ||
7d167afd JJ |
2890 | /* Return nonzero if TRIAL can go into the sibling call |
2891 | delay slot. */ | |
2892 | ||
2893 | int | |
fc27d102 | 2894 | eligible_for_sibcall_delay (rtx trial) |
7d167afd JJ |
2895 | { |
2896 | rtx pat, src; | |
2897 | ||
2898 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) | |
2899 | return 0; | |
2900 | ||
8456b95a | 2901 | if (get_attr_length (trial) != 1) |
7d167afd JJ |
2902 | return 0; |
2903 | ||
2904 | pat = PATTERN (trial); | |
2905 | ||
2906 | if (current_function_uses_only_leaf_regs) | |
2907 | { | |
2908 | /* If the tail call is done using the call instruction, | |
2909 | we have to restore %o7 in the delay slot. */ | |
2be5e524 | 2910 | if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic) |
7d167afd JJ |
2911 | return 0; |
2912 | ||
2913 | /* %g1 is used to build the function address */ | |
2914 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) | |
2915 | return 0; | |
2916 | ||
2917 | return 1; | |
2918 | } | |
2919 | ||
2920 | /* Otherwise, only operations which can be done in tandem with | |
2921 | a `restore' insn can go into the delay slot. */ | |
2922 | if (GET_CODE (SET_DEST (pat)) != REG | |
2923 | || REGNO (SET_DEST (pat)) < 24 | |
2924 | || REGNO (SET_DEST (pat)) >= 32) | |
2925 | return 0; | |
2926 | ||
2927 | /* If it mentions %o7, it can't go in, because sibcall will clobber it | |
2928 | in most cases. */ | |
2929 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) | |
2930 | return 0; | |
2931 | ||
2932 | src = SET_SRC (pat); | |
2933 | ||
3ec6f1a9 RK |
2934 | if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2935 | && arith_operand (src, GET_MODE (src))) | |
7d167afd JJ |
2936 | { |
2937 | if (TARGET_ARCH64) | |
2938 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2939 | else | |
2940 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
2941 | } | |
2942 | ||
3ec6f1a9 RK |
2943 | else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2944 | && arith_double_operand (src, GET_MODE (src))) | |
7d167afd JJ |
2945 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); |
2946 | ||
2947 | else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) | |
2948 | && register_operand (src, SFmode)) | |
2949 | return 1; | |
2950 | ||
2951 | else if (GET_CODE (src) == PLUS | |
2952 | && arith_operand (XEXP (src, 0), SImode) | |
2953 | && arith_operand (XEXP (src, 1), SImode) | |
2954 | && (register_operand (XEXP (src, 0), SImode) | |
2955 | || register_operand (XEXP (src, 1), SImode))) | |
2956 | return 1; | |
2957 | ||
2958 | else if (GET_CODE (src) == PLUS | |
2959 | && arith_double_operand (XEXP (src, 0), DImode) | |
2960 | && arith_double_operand (XEXP (src, 1), DImode) | |
2961 | && (register_operand (XEXP (src, 0), DImode) | |
2962 | || register_operand (XEXP (src, 1), DImode))) | |
2963 | return 1; | |
2964 | ||
2965 | else if (GET_CODE (src) == LO_SUM | |
2966 | && ! TARGET_CM_MEDMID | |
2967 | && ((register_operand (XEXP (src, 0), SImode) | |
2968 | && immediate_operand (XEXP (src, 1), SImode)) | |
2969 | || (TARGET_ARCH64 | |
2970 | && register_operand (XEXP (src, 0), DImode) | |
2971 | && immediate_operand (XEXP (src, 1), DImode)))) | |
2972 | return 1; | |
2973 | ||
2974 | else if (GET_CODE (src) == ASHIFT | |
2975 | && (register_operand (XEXP (src, 0), SImode) | |
2976 | || register_operand (XEXP (src, 0), DImode)) | |
2977 | && XEXP (src, 1) == const1_rtx) | |
2978 | return 1; | |
2979 | ||
2980 | return 0; | |
2981 | } | |
2982 | ||
e0d80184 | 2983 | static int |
fc27d102 | 2984 | check_return_regs (rtx x) |
ab835497 | 2985 | { |
e0d80184 DM |
2986 | switch (GET_CODE (x)) |
2987 | { | |
2988 | case REG: | |
2989 | return IN_OR_GLOBAL_P (x); | |
ab835497 | 2990 | |
e0d80184 DM |
2991 | case CONST_INT: |
2992 | case CONST_DOUBLE: | |
2993 | case CONST: | |
2994 | case SYMBOL_REF: | |
2995 | case LABEL_REF: | |
2996 | return 1; | |
ab835497 | 2997 | |
e0d80184 DM |
2998 | case SET: |
2999 | case IOR: | |
3000 | case AND: | |
3001 | case XOR: | |
3002 | case PLUS: | |
3003 | case MINUS: | |
3004 | if (check_return_regs (XEXP (x, 1)) == 0) | |
3005 | return 0; | |
3006 | case NOT: | |
3007 | case NEG: | |
3008 | case MEM: | |
3009 | return check_return_regs (XEXP (x, 0)); | |
3010 | ||
3011 | default: | |
3012 | return 0; | |
3013 | } | |
ab835497 | 3014 | |
e0d80184 | 3015 | } |
ab835497 | 3016 | |
e0d80184 | 3017 | int |
fc27d102 | 3018 | short_branch (int uid1, int uid2) |
e0d80184 | 3019 | { |
9d98a694 | 3020 | int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2); |
77b91512 RK |
3021 | |
3022 | /* Leave a few words of "slop". */ | |
3023 | if (delta >= -1023 && delta <= 1022) | |
e0d80184 | 3024 | return 1; |
77b91512 | 3025 | |
e0d80184 DM |
3026 | return 0; |
3027 | } | |
ab835497 | 3028 | |
5e7a8ee0 | 3029 | /* Return nonzero if REG is not used after INSN. |
e0d80184 DM |
3030 | We assume REG is a reload reg, and therefore does |
3031 | not live past labels or calls or jumps. */ | |
3032 | int | |
fc27d102 | 3033 | reg_unused_after (rtx reg, rtx insn) |
e0d80184 DM |
3034 | { |
3035 | enum rtx_code code, prev_code = UNKNOWN; | |
ab835497 | 3036 | |
e0d80184 | 3037 | while ((insn = NEXT_INSN (insn))) |
61a55e8b | 3038 | { |
e0d80184 DM |
3039 | if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) |
3040 | return 1; | |
ab835497 | 3041 | |
e0d80184 DM |
3042 | code = GET_CODE (insn); |
3043 | if (GET_CODE (insn) == CODE_LABEL) | |
3044 | return 1; | |
bc961ed7 | 3045 | |
e0d80184 | 3046 | if (GET_RTX_CLASS (code) == 'i') |
61a55e8b | 3047 | { |
e0d80184 DM |
3048 | rtx set = single_set (insn); |
3049 | int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); | |
3050 | if (set && in_src) | |
3051 | return 0; | |
3052 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
3053 | return 1; | |
3054 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
3055 | return 0; | |
61a55e8b | 3056 | } |
e0d80184 | 3057 | prev_code = code; |
61a55e8b | 3058 | } |
e0d80184 DM |
3059 | return 1; |
3060 | } | |
3061 | \f | |
5751a10b JJ |
3062 | /* Determine if it's legal to put X into the constant pool. This |
3063 | is not possible if X contains the address of a symbol that is | |
3064 | not constant (TLS) or not known at final link time (PIC). */ | |
3065 | ||
3066 | static bool | |
3067 | sparc_cannot_force_const_mem (rtx x) | |
3068 | { | |
3069 | switch (GET_CODE (x)) | |
3070 | { | |
3071 | case CONST_INT: | |
3072 | case CONST_DOUBLE: | |
3073 | /* Accept all non-symbolic constants. */ | |
3074 | return false; | |
3075 | ||
3076 | case LABEL_REF: | |
3077 | /* Labels are OK iff we are non-PIC. */ | |
3078 | return flag_pic != 0; | |
3079 | ||
3080 | case SYMBOL_REF: | |
3081 | /* 'Naked' TLS symbol references are never OK, | |
3082 | non-TLS symbols are OK iff we are non-PIC. */ | |
3083 | if (SYMBOL_REF_TLS_MODEL (x)) | |
3084 | return true; | |
3085 | else | |
3086 | return flag_pic != 0; | |
3087 | ||
3088 | case CONST: | |
3089 | return sparc_cannot_force_const_mem (XEXP (x, 0)); | |
3090 | case PLUS: | |
3091 | case MINUS: | |
3092 | return sparc_cannot_force_const_mem (XEXP (x, 0)) | |
3093 | || sparc_cannot_force_const_mem (XEXP (x, 1)); | |
3094 | case UNSPEC: | |
3095 | return true; | |
3096 | default: | |
3097 | abort (); | |
3098 | } | |
3099 | } | |
3100 | \f | |
e0d80184 | 3101 | /* The table we use to reference PIC data. */ |
e2500fed | 3102 | static GTY(()) rtx global_offset_table; |
bc961ed7 | 3103 | |
e0d80184 | 3104 | /* The function we use to get at it. */ |
e2500fed | 3105 | static GTY(()) rtx get_pc_symbol; |
e0d80184 | 3106 | static char get_pc_symbol_name[256]; |
ab835497 | 3107 | |
e0d80184 | 3108 | /* Ensure that we are not using patterns that are not OK with PIC. */ |
795068a4 | 3109 | |
e0d80184 | 3110 | int |
fc27d102 | 3111 | check_pic (int i) |
e0d80184 DM |
3112 | { |
3113 | switch (flag_pic) | |
ab835497 | 3114 | { |
e0d80184 | 3115 | case 1: |
1ccbefce RH |
3116 | if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF |
3117 | || (GET_CODE (recog_data.operand[i]) == CONST | |
3118 | && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS | |
3119 | && (XEXP (XEXP (recog_data.operand[i], 0), 0) | |
e0d80184 | 3120 | == global_offset_table) |
1ccbefce | 3121 | && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) |
e0d80184 DM |
3122 | == CONST)))) |
3123 | abort (); | |
3124 | case 2: | |
3125 | default: | |
3126 | return 1; | |
ab835497 | 3127 | } |
ab835497 | 3128 | } |
795068a4 | 3129 | |
e0d80184 DM |
3130 | /* Return true if X is an address which needs a temporary register when |
3131 | reloaded while generating PIC code. */ | |
795068a4 | 3132 | |
e0d80184 | 3133 | int |
fc27d102 | 3134 | pic_address_needs_scratch (rtx x) |
795068a4 | 3135 | { |
e0d80184 DM |
3136 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ |
3137 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
3138 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
3139 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3140 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
3141 | return 1; | |
795068a4 | 3142 | |
e0d80184 DM |
3143 | return 0; |
3144 | } | |
795068a4 | 3145 | |
5751a10b JJ |
3146 | /* Determine if a given RTX is a valid constant. We already know this |
3147 | satisfies CONSTANT_P. */ | |
3148 | ||
3149 | bool | |
3150 | legitimate_constant_p (rtx x) | |
3151 | { | |
3152 | rtx inner; | |
3153 | ||
3154 | switch (GET_CODE (x)) | |
3155 | { | |
3156 | case SYMBOL_REF: | |
3157 | /* TLS symbols are not constant. */ | |
3158 | if (SYMBOL_REF_TLS_MODEL (x)) | |
3159 | return false; | |
3160 | break; | |
3161 | ||
3162 | case CONST: | |
3163 | inner = XEXP (x, 0); | |
3164 | ||
3165 | /* Offsets of TLS symbols are never valid. | |
3166 | Discourage CSE from creating them. */ | |
3167 | if (GET_CODE (inner) == PLUS | |
3168 | && tls_symbolic_operand (XEXP (inner, 0))) | |
3169 | return false; | |
3170 | break; | |
3171 | ||
3172 | case CONST_DOUBLE: | |
3173 | if (GET_MODE (x) == VOIDmode) | |
3174 | return true; | |
3175 | ||
3176 | /* Floating point constants are generally not ok. | |
3177 | The only exception is 0.0 in VIS. */ | |
3178 | if (TARGET_VIS | |
3179 | && (GET_MODE (x) == SFmode | |
3180 | || GET_MODE (x) == DFmode | |
3181 | || GET_MODE (x) == TFmode) | |
3182 | && fp_zero_operand (x, GET_MODE (x))) | |
3183 | return true; | |
3184 | ||
3185 | return false; | |
3186 | ||
3187 | default: | |
3188 | break; | |
3189 | } | |
3190 | ||
3191 | return true; | |
3192 | } | |
3193 | ||
3194 | /* Determine if a given RTX is a valid constant address. */ | |
3195 | ||
3196 | bool | |
3197 | constant_address_p (rtx x) | |
3198 | { | |
3199 | switch (GET_CODE (x)) | |
3200 | { | |
3201 | case LABEL_REF: | |
3202 | case CONST_INT: | |
3203 | case HIGH: | |
3204 | return true; | |
3205 | ||
3206 | case CONST: | |
3207 | if (flag_pic && pic_address_needs_scratch (x)) | |
3208 | return false; | |
3209 | return legitimate_constant_p (x); | |
3210 | ||
3211 | case SYMBOL_REF: | |
3212 | return !flag_pic && legitimate_constant_p (x); | |
3213 | ||
3214 | default: | |
3215 | return false; | |
3216 | } | |
3217 | } | |
3218 | ||
3219 | /* Nonzero if the constant value X is a legitimate general operand | |
3220 | when generating PIC code. It is given that flag_pic is on and | |
3221 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
3222 | ||
3223 | bool | |
3224 | legitimate_pic_operand_p (rtx x) | |
3225 | { | |
3226 | if (pic_address_needs_scratch (x)) | |
3227 | return false; | |
3228 | if (tls_symbolic_operand (x) | |
3229 | || (GET_CODE (x) == CONST | |
3230 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3231 | && tls_symbolic_operand (XEXP (XEXP (x, 0), 0)))) | |
3232 | return false; | |
3233 | return true; | |
3234 | } | |
3235 | ||
3236 | /* Return nonzero if ADDR is a valid memory address. | |
3237 | STRICT specifies whether strict register checking applies. */ | |
3238 | ||
3239 | int | |
3240 | legitimate_address_p (enum machine_mode mode, rtx addr, int strict) | |
3241 | { | |
3242 | rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2; | |
3243 | ||
3244 | if (REG_P (addr) || GET_CODE (addr) == SUBREG) | |
3245 | rs1 = addr; | |
3246 | else if (GET_CODE (addr) == PLUS) | |
3247 | { | |
3248 | rs1 = XEXP (addr, 0); | |
3249 | rs2 = XEXP (addr, 1); | |
3250 | ||
3251 | /* Canonicalize. REG comes first, if there are no regs, | |
3252 | LO_SUM comes first. */ | |
3253 | if (!REG_P (rs1) | |
3254 | && GET_CODE (rs1) != SUBREG | |
3255 | && (REG_P (rs2) | |
3256 | || GET_CODE (rs2) == SUBREG | |
3257 | || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM))) | |
3258 | { | |
3259 | rs1 = XEXP (addr, 1); | |
3260 | rs2 = XEXP (addr, 0); | |
3261 | } | |
3262 | ||
3263 | if ((flag_pic == 1 | |
3264 | && rs1 == pic_offset_table_rtx | |
3265 | && !REG_P (rs2) | |
3266 | && GET_CODE (rs2) != SUBREG | |
3267 | && GET_CODE (rs2) != LO_SUM | |
3268 | && GET_CODE (rs2) != MEM | |
3269 | && !tls_symbolic_operand (rs2) | |
3270 | && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode) | |
3271 | && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2))) | |
3272 | || ((REG_P (rs1) | |
3273 | || GET_CODE (rs1) == SUBREG) | |
3274 | && RTX_OK_FOR_OFFSET_P (rs2))) | |
3275 | { | |
3276 | imm1 = rs2; | |
3277 | rs2 = NULL; | |
3278 | } | |
3279 | else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG) | |
3280 | && (REG_P (rs2) || GET_CODE (rs2) == SUBREG)) | |
3281 | { | |
3282 | /* We prohibit REG + REG for TFmode when there are no instructions | |
3283 | which accept REG+REG instructions. We do this because REG+REG | |
3284 | is not an offsetable address. If we get the situation in reload | |
3285 | where source and destination of a movtf pattern are both MEMs with | |
3286 | REG+REG address, then only one of them gets converted to an | |
3287 | offsetable address. */ | |
3288 | if (mode == TFmode | |
3289 | && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9 | |
3290 | && TARGET_HARD_QUAD)) | |
3291 | return 0; | |
3292 | ||
3293 | /* We prohibit REG + REG on ARCH32 if not optimizing for | |
3294 | DFmode/DImode because then mem_min_alignment is likely to be zero | |
3295 | after reload and the forced split would lack a matching splitter | |
3296 | pattern. */ | |
3297 | if (TARGET_ARCH32 && !optimize | |
3298 | && (mode == DFmode || mode == DImode)) | |
3299 | return 0; | |
3300 | } | |
3301 | else if (USE_AS_OFFSETABLE_LO10 | |
3302 | && GET_CODE (rs1) == LO_SUM | |
3303 | && TARGET_ARCH64 | |
3304 | && ! TARGET_CM_MEDMID | |
3305 | && RTX_OK_FOR_OLO10_P (rs2)) | |
3306 | { | |
3307 | imm2 = rs2; | |
3308 | rs2 = NULL; | |
3309 | imm1 = XEXP (rs1, 1); | |
3310 | rs1 = XEXP (rs1, 0); | |
3311 | if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1)) | |
3312 | return 0; | |
3313 | } | |
3314 | } | |
3315 | else if (GET_CODE (addr) == LO_SUM) | |
3316 | { | |
3317 | rs1 = XEXP (addr, 0); | |
3318 | imm1 = XEXP (addr, 1); | |
3319 | ||
3320 | if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1)) | |
3321 | return 0; | |
3322 | ||
3323 | /* We can't allow TFmode, because an offset greater than or equal to the | |
3324 | alignment (8) may cause the LO_SUM to overflow if !v9. */ | |
3325 | if (mode == TFmode && !TARGET_V9) | |
3326 | return 0; | |
3327 | } | |
3328 | else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr)) | |
3329 | return 1; | |
3330 | else | |
3331 | return 0; | |
3332 | ||
3333 | if (GET_CODE (rs1) == SUBREG) | |
3334 | rs1 = SUBREG_REG (rs1); | |
3335 | if (!REG_P (rs1)) | |
3336 | return 0; | |
3337 | ||
3338 | if (rs2) | |
3339 | { | |
3340 | if (GET_CODE (rs2) == SUBREG) | |
3341 | rs2 = SUBREG_REG (rs2); | |
3342 | if (!REG_P (rs2)) | |
3343 | return 0; | |
3344 | } | |
3345 | ||
3346 | if (strict) | |
3347 | { | |
3348 | if (!REGNO_OK_FOR_BASE_P (REGNO (rs1)) | |
3349 | || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2)))) | |
3350 | return 0; | |
3351 | } | |
3352 | else | |
3353 | { | |
3354 | if ((REGNO (rs1) >= 32 | |
3355 | && REGNO (rs1) != FRAME_POINTER_REGNUM | |
3356 | && REGNO (rs1) < FIRST_PSEUDO_REGISTER) | |
3357 | || (rs2 | |
3358 | && (REGNO (rs2) >= 32 | |
3359 | && REGNO (rs2) != FRAME_POINTER_REGNUM | |
3360 | && REGNO (rs2) < FIRST_PSEUDO_REGISTER))) | |
3361 | return 0; | |
3362 | } | |
3363 | return 1; | |
3364 | } | |
3365 | ||
3366 | /* Construct the SYMBOL_REF for the tls_get_offset function. */ | |
3367 | ||
3368 | static GTY(()) rtx sparc_tls_symbol; | |
3369 | static rtx | |
3370 | sparc_tls_get_addr (void) | |
3371 | { | |
3372 | if (!sparc_tls_symbol) | |
3373 | sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr"); | |
3374 | ||
3375 | return sparc_tls_symbol; | |
3376 | } | |
3377 | ||
3378 | static rtx | |
3379 | sparc_tls_got (void) | |
3380 | { | |
3381 | rtx temp; | |
3382 | if (flag_pic) | |
3383 | { | |
3384 | current_function_uses_pic_offset_table = 1; | |
3385 | return pic_offset_table_rtx; | |
3386 | } | |
3387 | ||
3388 | if (!global_offset_table) | |
3389 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
3390 | temp = gen_reg_rtx (Pmode); | |
3391 | emit_move_insn (temp, global_offset_table); | |
3392 | return temp; | |
3393 | } | |
3394 | ||
3395 | ||
3396 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
3397 | this (thread-local) address. */ | |
3398 | ||
3399 | rtx | |
3400 | legitimize_tls_address (rtx addr) | |
3401 | { | |
3402 | rtx temp1, temp2, temp3, ret, o0, got, insn; | |
3403 | ||
3404 | if (no_new_pseudos) | |
3405 | abort (); | |
3406 | ||
3407 | if (GET_CODE (addr) == SYMBOL_REF) | |
3408 | switch (SYMBOL_REF_TLS_MODEL (addr)) | |
3409 | { | |
3410 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
3411 | start_sequence (); | |
3412 | temp1 = gen_reg_rtx (SImode); | |
3413 | temp2 = gen_reg_rtx (SImode); | |
3414 | ret = gen_reg_rtx (Pmode); | |
3415 | o0 = gen_rtx_REG (Pmode, 8); | |
3416 | got = sparc_tls_got (); | |
3417 | emit_insn (gen_tgd_hi22 (temp1, addr)); | |
3418 | emit_insn (gen_tgd_lo10 (temp2, temp1, addr)); | |
3419 | if (TARGET_ARCH32) | |
3420 | { | |
3421 | emit_insn (gen_tgd_add32 (o0, got, temp2, addr)); | |
3422 | insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (), | |
3423 | addr, const1_rtx)); | |
3424 | } | |
3425 | else | |
3426 | { | |
3427 | emit_insn (gen_tgd_add64 (o0, got, temp2, addr)); | |
3428 | insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (), | |
3429 | addr, const1_rtx)); | |
3430 | } | |
3431 | CALL_INSN_FUNCTION_USAGE (insn) | |
3432 | = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0), | |
3433 | CALL_INSN_FUNCTION_USAGE (insn)); | |
3434 | insn = get_insns (); | |
3435 | end_sequence (); | |
3436 | emit_libcall_block (insn, ret, o0, addr); | |
3437 | break; | |
3438 | ||
3439 | case TLS_MODEL_LOCAL_DYNAMIC: | |
3440 | start_sequence (); | |
3441 | temp1 = gen_reg_rtx (SImode); | |
3442 | temp2 = gen_reg_rtx (SImode); | |
3443 | temp3 = gen_reg_rtx (Pmode); | |
3444 | ret = gen_reg_rtx (Pmode); | |
3445 | o0 = gen_rtx_REG (Pmode, 8); | |
3446 | got = sparc_tls_got (); | |
3447 | emit_insn (gen_tldm_hi22 (temp1)); | |
3448 | emit_insn (gen_tldm_lo10 (temp2, temp1)); | |
3449 | if (TARGET_ARCH32) | |
3450 | { | |
3451 | emit_insn (gen_tldm_add32 (o0, got, temp2)); | |
3452 | insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (), | |
3453 | const1_rtx)); | |
3454 | } | |
3455 | else | |
3456 | { | |
3457 | emit_insn (gen_tldm_add64 (o0, got, temp2)); | |
3458 | insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (), | |
3459 | const1_rtx)); | |
3460 | } | |
3461 | CALL_INSN_FUNCTION_USAGE (insn) | |
3462 | = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0), | |
3463 | CALL_INSN_FUNCTION_USAGE (insn)); | |
3464 | insn = get_insns (); | |
3465 | end_sequence (); | |
3466 | emit_libcall_block (insn, temp3, o0, | |
3467 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
3468 | UNSPEC_TLSLD_BASE)); | |
3469 | temp1 = gen_reg_rtx (SImode); | |
3470 | temp2 = gen_reg_rtx (SImode); | |
3471 | emit_insn (gen_tldo_hix22 (temp1, addr)); | |
3472 | emit_insn (gen_tldo_lox10 (temp2, temp1, addr)); | |
3473 | if (TARGET_ARCH32) | |
3474 | emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr)); | |
3475 | else | |
3476 | emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr)); | |
3477 | break; | |
3478 | ||
3479 | case TLS_MODEL_INITIAL_EXEC: | |
3480 | temp1 = gen_reg_rtx (SImode); | |
3481 | temp2 = gen_reg_rtx (SImode); | |
3482 | temp3 = gen_reg_rtx (Pmode); | |
3483 | got = sparc_tls_got (); | |
3484 | emit_insn (gen_tie_hi22 (temp1, addr)); | |
3485 | emit_insn (gen_tie_lo10 (temp2, temp1, addr)); | |
3486 | if (TARGET_ARCH32) | |
3487 | emit_insn (gen_tie_ld32 (temp3, got, temp2, addr)); | |
3488 | else | |
3489 | emit_insn (gen_tie_ld64 (temp3, got, temp2, addr)); | |
3490 | if (TARGET_SUN_TLS) | |
3491 | { | |
3492 | ret = gen_reg_rtx (Pmode); | |
3493 | if (TARGET_ARCH32) | |
3494 | emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7), | |
3495 | temp3, addr)); | |
3496 | else | |
3497 | emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7), | |
3498 | temp3, addr)); | |
3499 | } | |
3500 | else | |
3501 | ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3); | |
3502 | break; | |
3503 | ||
3504 | case TLS_MODEL_LOCAL_EXEC: | |
3505 | temp1 = gen_reg_rtx (Pmode); | |
3506 | temp2 = gen_reg_rtx (Pmode); | |
3507 | if (TARGET_ARCH32) | |
3508 | { | |
3509 | emit_insn (gen_tle_hix22_sp32 (temp1, addr)); | |
3510 | emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr)); | |
3511 | } | |
3512 | else | |
3513 | { | |
3514 | emit_insn (gen_tle_hix22_sp64 (temp1, addr)); | |
3515 | emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr)); | |
3516 | } | |
3517 | ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2); | |
3518 | break; | |
3519 | ||
3520 | default: | |
3521 | abort (); | |
3522 | } | |
3523 | ||
3524 | else | |
3525 | abort (); /* for now ... */ | |
3526 | ||
3527 | return ret; | |
3528 | } | |
3529 | ||
3530 | ||
e0d80184 DM |
3531 | /* Legitimize PIC addresses. If the address is already position-independent, |
3532 | we return ORIG. Newly generated position-independent addresses go into a | |
88cad84b | 3533 | reg. This is REG if nonzero, otherwise we allocate register(s) as |
e0d80184 | 3534 | necessary. */ |
795068a4 | 3535 | |
e0d80184 | 3536 | rtx |
fc27d102 KG |
3537 | legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, |
3538 | rtx reg) | |
e0d80184 DM |
3539 | { |
3540 | if (GET_CODE (orig) == SYMBOL_REF) | |
82d6b402 | 3541 | { |
e0d80184 DM |
3542 | rtx pic_ref, address; |
3543 | rtx insn; | |
82d6b402 | 3544 | |
e0d80184 | 3545 | if (reg == 0) |
82d6b402 | 3546 | { |
e0d80184 DM |
3547 | if (reload_in_progress || reload_completed) |
3548 | abort (); | |
3549 | else | |
3550 | reg = gen_reg_rtx (Pmode); | |
82d6b402 | 3551 | } |
795068a4 | 3552 | |
e0d80184 | 3553 | if (flag_pic == 2) |
4fb4e4b8 | 3554 | { |
e0d80184 DM |
3555 | /* If not during reload, allocate another temp reg here for loading |
3556 | in the address, so that these instructions can be optimized | |
3557 | properly. */ | |
3558 | rtx temp_reg = ((reload_in_progress || reload_completed) | |
3559 | ? reg : gen_reg_rtx (Pmode)); | |
3560 | ||
3561 | /* Must put the SYMBOL_REF inside an UNSPEC here so that cse | |
3562 | won't get confused into thinking that these two instructions | |
3563 | are loading in the true address of the symbol. If in the | |
3564 | future a PIC rtx exists, that should be used instead. */ | |
be3f1ff5 DM |
3565 | if (Pmode == SImode) |
3566 | { | |
3567 | emit_insn (gen_movsi_high_pic (temp_reg, orig)); | |
3568 | emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
3569 | } | |
3570 | else | |
3571 | { | |
3572 | emit_insn (gen_movdi_high_pic (temp_reg, orig)); | |
3573 | emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
3574 | } | |
e0d80184 | 3575 | address = temp_reg; |
4fb4e4b8 DE |
3576 | } |
3577 | else | |
e0d80184 DM |
3578 | address = orig; |
3579 | ||
3580 | pic_ref = gen_rtx_MEM (Pmode, | |
8ac61af7 RK |
3581 | gen_rtx_PLUS (Pmode, |
3582 | pic_offset_table_rtx, address)); | |
e0d80184 DM |
3583 | current_function_uses_pic_offset_table = 1; |
3584 | RTX_UNCHANGING_P (pic_ref) = 1; | |
3585 | insn = emit_move_insn (reg, pic_ref); | |
3586 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
3587 | by loop. */ | |
3588 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, | |
3589 | REG_NOTES (insn)); | |
3590 | return reg; | |
795068a4 | 3591 | } |
e0d80184 | 3592 | else if (GET_CODE (orig) == CONST) |
795068a4 | 3593 | { |
e0d80184 | 3594 | rtx base, offset; |
795068a4 | 3595 | |
e0d80184 DM |
3596 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
3597 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
3598 | return orig; | |
82d6b402 | 3599 | |
e0d80184 | 3600 | if (reg == 0) |
4fb4e4b8 | 3601 | { |
e0d80184 DM |
3602 | if (reload_in_progress || reload_completed) |
3603 | abort (); | |
3604 | else | |
3605 | reg = gen_reg_rtx (Pmode); | |
4fb4e4b8 | 3606 | } |
e0d80184 DM |
3607 | |
3608 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
4fb4e4b8 | 3609 | { |
e0d80184 DM |
3610 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
3611 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
3612 | base == reg ? 0 : reg); | |
4fb4e4b8 DE |
3613 | } |
3614 | else | |
61a66555 JW |
3615 | abort (); |
3616 | ||
e0d80184 DM |
3617 | if (GET_CODE (offset) == CONST_INT) |
3618 | { | |
3619 | if (SMALL_INT (offset)) | |
ed8908e7 | 3620 | return plus_constant (base, INTVAL (offset)); |
e0d80184 DM |
3621 | else if (! reload_in_progress && ! reload_completed) |
3622 | offset = force_reg (Pmode, offset); | |
3623 | else | |
3624 | /* If we reach here, then something is seriously wrong. */ | |
3625 | abort (); | |
3626 | } | |
3627 | return gen_rtx_PLUS (Pmode, base, offset); | |
795068a4 | 3628 | } |
e0d80184 DM |
3629 | else if (GET_CODE (orig) == LABEL_REF) |
3630 | /* ??? Why do we do this? */ | |
3631 | /* Now movsi_pic_label_ref uses it, but we ought to be checking that | |
3632 | the register is live instead, in case it is eliminated. */ | |
3633 | current_function_uses_pic_offset_table = 1; | |
795068a4 | 3634 | |
e0d80184 DM |
3635 | return orig; |
3636 | } | |
795068a4 | 3637 | |
5751a10b JJ |
3638 | /* Try machine-dependent ways of modifying an illegitimate address X |
3639 | to be legitimate. If we find one, return the new, valid address. | |
3640 | ||
3641 | OLDX is the address as it was before break_out_memory_refs was called. | |
3642 | In some cases it is useful to look at this to decide what needs to be done. | |
3643 | ||
3644 | MODE is the mode of the operand pointed to by X. */ | |
3645 | ||
3646 | rtx | |
3647 | legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode) | |
3648 | { | |
3649 | rtx orig_x = x; | |
3650 | ||
3651 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT) | |
3652 | x = gen_rtx_PLUS (Pmode, XEXP (x, 1), | |
3653 | force_operand (XEXP (x, 0), NULL_RTX)); | |
3654 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT) | |
3655 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
3656 | force_operand (XEXP (x, 1), NULL_RTX)); | |
3657 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS) | |
3658 | x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX), | |
3659 | XEXP (x, 1)); | |
3660 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS) | |
3661 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
3662 | force_operand (XEXP (x, 1), NULL_RTX)); | |
3663 | ||
3664 | if (x != orig_x && legitimate_address_p (mode, x, FALSE)) | |
3665 | return x; | |
3666 | ||
3667 | if (tls_symbolic_operand (x)) | |
3668 | x = legitimize_tls_address (x); | |
3669 | else if (flag_pic) | |
3670 | x = legitimize_pic_address (x, mode, 0); | |
3671 | else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1))) | |
3672 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
3673 | copy_to_mode_reg (Pmode, XEXP (x, 1))); | |
3674 | else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0))) | |
3675 | x = gen_rtx_PLUS (Pmode, XEXP (x, 1), | |
3676 | copy_to_mode_reg (Pmode, XEXP (x, 0))); | |
3677 | else if (GET_CODE (x) == SYMBOL_REF | |
3678 | || GET_CODE (x) == CONST | |
3679 | || GET_CODE (x) == LABEL_REF) | |
3680 | x = copy_to_suggested_reg (x, NULL_RTX, Pmode); | |
3681 | return x; | |
3682 | } | |
3683 | ||
fccf9848 | 3684 | /* Emit special PIC prologues. */ |
795068a4 | 3685 | |
e0d80184 | 3686 | void |
fc27d102 | 3687 | load_pic_register (void) |
e0d80184 DM |
3688 | { |
3689 | /* Labels to get the PC in the prologue of this function. */ | |
3690 | int orig_flag_pic = flag_pic; | |
4fb4e4b8 | 3691 | |
e0d80184 DM |
3692 | if (! flag_pic) |
3693 | abort (); | |
3694 | ||
d6a7951f | 3695 | /* If we haven't emitted the special get_pc helper function, do so now. */ |
e0d80184 | 3696 | if (get_pc_symbol_name[0] == 0) |
4fb4e4b8 | 3697 | { |
d676da68 | 3698 | int align; |
82d6b402 | 3699 | |
d676da68 | 3700 | ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0); |
e0d80184 | 3701 | text_section (); |
d676da68 DM |
3702 | |
3703 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
3704 | if (align > 0) | |
3705 | ASM_OUTPUT_ALIGN (asm_out_file, align); | |
4977bab6 | 3706 | (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0); |
4df1190a | 3707 | fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file); |
e0d80184 | 3708 | } |
82d6b402 | 3709 | |
e0d80184 DM |
3710 | /* Initialize every time through, since we can't easily |
3711 | know this to be permanent. */ | |
3712 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
3713 | get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name); | |
3714 | flag_pic = 0; | |
82d6b402 | 3715 | |
fccf9848 JJ |
3716 | emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, |
3717 | get_pc_symbol)); | |
82d6b402 | 3718 | |
e0d80184 | 3719 | flag_pic = orig_flag_pic; |
82d6b402 | 3720 | |
e0d80184 DM |
3721 | /* Need to emit this whether or not we obey regdecls, |
3722 | since setjmp/longjmp can cause life info to screw up. | |
3723 | ??? In the case where we don't obey regdecls, this is not sufficient | |
3724 | since we may not fall out the bottom. */ | |
3725 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); | |
795068a4 | 3726 | } |
ab835497 | 3727 | \f |
e0d80184 | 3728 | /* Return 1 if RTX is a MEM which is known to be aligned to at |
7a31a340 | 3729 | least a DESIRED byte boundary. */ |
a3ee5899 | 3730 | |
e0d80184 | 3731 | int |
fc27d102 | 3732 | mem_min_alignment (rtx mem, int desired) |
ab835497 | 3733 | { |
e0d80184 DM |
3734 | rtx addr, base, offset; |
3735 | ||
3736 | /* If it's not a MEM we can't accept it. */ | |
3737 | if (GET_CODE (mem) != MEM) | |
3738 | return 0; | |
3739 | ||
3740 | addr = XEXP (mem, 0); | |
3741 | base = offset = NULL_RTX; | |
3742 | if (GET_CODE (addr) == PLUS) | |
ab835497 | 3743 | { |
e0d80184 | 3744 | if (GET_CODE (XEXP (addr, 0)) == REG) |
61a55e8b | 3745 | { |
e0d80184 DM |
3746 | base = XEXP (addr, 0); |
3747 | ||
3748 | /* What we are saying here is that if the base | |
3749 | REG is aligned properly, the compiler will make | |
3750 | sure any REG based index upon it will be so | |
3751 | as well. */ | |
3752 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3753 | offset = XEXP (addr, 1); | |
61a55e8b | 3754 | else |
e0d80184 | 3755 | offset = const0_rtx; |
61a55e8b | 3756 | } |
ab835497 | 3757 | } |
e0d80184 | 3758 | else if (GET_CODE (addr) == REG) |
ab835497 | 3759 | { |
e0d80184 DM |
3760 | base = addr; |
3761 | offset = const0_rtx; | |
ab835497 | 3762 | } |
82d6b402 | 3763 | |
e0d80184 | 3764 | if (base != NULL_RTX) |
795068a4 | 3765 | { |
e0d80184 DM |
3766 | int regno = REGNO (base); |
3767 | ||
563c12b0 | 3768 | if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM) |
61a55e8b | 3769 | { |
e0d80184 DM |
3770 | /* Check if the compiler has recorded some information |
3771 | about the alignment of the base REG. If reload has | |
021e2ecc JJ |
3772 | completed, we already matched with proper alignments. |
3773 | If not running global_alloc, reload might give us | |
3774 | unaligned pointer to local stack though. */ | |
bdb429a5 RK |
3775 | if (((cfun != 0 |
3776 | && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT) | |
021e2ecc | 3777 | || (optimize && reload_completed)) |
bdb429a5 | 3778 | && (INTVAL (offset) & (desired - 1)) == 0) |
e0d80184 | 3779 | return 1; |
61a55e8b | 3780 | } |
795068a4 | 3781 | else |
e0d80184 DM |
3782 | { |
3783 | if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) | |
3784 | return 1; | |
3785 | } | |
795068a4 | 3786 | } |
e0d80184 DM |
3787 | else if (! TARGET_UNALIGNED_DOUBLES |
3788 | || CONSTANT_P (addr) | |
3789 | || GET_CODE (addr) == LO_SUM) | |
795068a4 | 3790 | { |
e0d80184 DM |
3791 | /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES |
3792 | is true, in which case we can only assume that an access is aligned if | |
3793 | it is to a constant address, or the address involves a LO_SUM. */ | |
3794 | return 1; | |
795068a4 | 3795 | } |
e0d80184 DM |
3796 | |
3797 | /* An obviously unaligned address. */ | |
3798 | return 0; | |
795068a4 | 3799 | } |
e0d80184 | 3800 | |
ab835497 | 3801 | \f |
61a55e8b | 3802 | /* Vectors to keep interesting information about registers where it can easily |
01d3224a | 3803 | be got. We used to use the actual mode value as the bit number, but there |
61a55e8b DE |
3804 | are more than 32 modes now. Instead we use two tables: one indexed by |
3805 | hard register number, and one indexed by mode. */ | |
3806 | ||
3807 | /* The purpose of sparc_mode_class is to shrink the range of modes so that | |
3808 | they all fit (as bit numbers) in a 32 bit word (again). Each real mode is | |
3809 | mapped into one sparc_mode_class mode. */ | |
3810 | ||
3811 | enum sparc_mode_class { | |
61a55e8b | 3812 | S_MODE, D_MODE, T_MODE, O_MODE, |
c4ce6853 DE |
3813 | SF_MODE, DF_MODE, TF_MODE, OF_MODE, |
3814 | CC_MODE, CCFP_MODE | |
61a55e8b | 3815 | }; |
ab835497 | 3816 | |
61a55e8b DE |
3817 | /* Modes for single-word and smaller quantities. */ |
3818 | #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
3819 | ||
3820 | /* Modes for double-word and smaller quantities. */ | |
3821 | #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) | |
3822 | ||
3823 | /* Modes for quad-word and smaller quantities. */ | |
3824 | #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
ab835497 | 3825 | |
d0cee9ba JJ |
3826 | /* Modes for 8-word and smaller quantities. */ |
3827 | #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) | |
3828 | ||
1e4eb8d1 JW |
3829 | /* Modes for single-float quantities. We must allow any single word or |
3830 | smaller quantity. This is because the fix/float conversion instructions | |
3831 | take integer inputs/outputs from the float registers. */ | |
3832 | #define SF_MODES (S_MODES) | |
ab835497 | 3833 | |
61a55e8b DE |
3834 | /* Modes for double-float and smaller quantities. */ |
3835 | #define DF_MODES (S_MODES | D_MODES) | |
3836 | ||
61a55e8b | 3837 | /* Modes for double-float only quantities. */ |
38875aba | 3838 | #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) |
ab835497 | 3839 | |
61a55e8b DE |
3840 | /* Modes for quad-float only quantities. */ |
3841 | #define TF_ONLY_MODES (1 << (int) TF_MODE) | |
3842 | ||
3843 | /* Modes for quad-float and smaller quantities. */ | |
3844 | #define TF_MODES (DF_MODES | TF_ONLY_MODES) | |
3845 | ||
d0cee9ba JJ |
3846 | /* Modes for quad-float and double-float quantities. */ |
3847 | #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES) | |
3848 | ||
3849 | /* Modes for quad-float pair only quantities. */ | |
3850 | #define OF_ONLY_MODES (1 << (int) OF_MODE) | |
3851 | ||
3852 | /* Modes for quad-float pairs and smaller quantities. */ | |
3853 | #define OF_MODES (TF_MODES | OF_ONLY_MODES) | |
3854 | ||
3855 | #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES) | |
ab835497 | 3856 | |
c4ce6853 DE |
3857 | /* Modes for condition codes. */ |
3858 | #define CC_MODES (1 << (int) CC_MODE) | |
3859 | #define CCFP_MODES (1 << (int) CCFP_MODE) | |
3860 | ||
ab835497 RK |
3861 | /* Value is 1 if register/mode pair is acceptable on sparc. |
3862 | The funny mixture of D and T modes is because integer operations | |
3863 | do not specially operate on tetra quantities, so non-quad-aligned | |
3864 | registers can hold quadword quantities (except %o4 and %i4 because | |
c4ce6853 | 3865 | they cross fixed registers). */ |
ab835497 | 3866 | |
61a55e8b | 3867 | /* This points to either the 32 bit or the 64 bit version. */ |
0b5826ac | 3868 | const int *hard_regno_mode_classes; |
61a55e8b | 3869 | |
0b5826ac | 3870 | static const int hard_32bit_mode_classes[] = { |
c4ce6853 | 3871 | S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, |
ab835497 RK |
3872 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, |
3873 | T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
3874 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
3875 | ||
d0cee9ba JJ |
3876 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
3877 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3878 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3879 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
a9e27770 DE |
3880 | |
3881 | /* FP regs f32 to f63. Only the even numbered registers actually exist, | |
3882 | and none can hold SFmode/SImode values. */ | |
d0cee9ba JJ |
3883 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
3884 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3885 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3886 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
a9e27770 DE |
3887 | |
3888 | /* %fcc[0123] */ | |
c4ce6853 DE |
3889 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
3890 | ||
3891 | /* %icc */ | |
3892 | CC_MODES | |
61a55e8b DE |
3893 | }; |
3894 | ||
0b5826ac | 3895 | static const int hard_64bit_mode_classes[] = { |
c4ce6853 | 3896 | D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 3897 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 3898 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 3899 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 3900 | |
d0cee9ba JJ |
3901 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
3902 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3903 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3904 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
61a55e8b | 3905 | |
a9e27770 | 3906 | /* FP regs f32 to f63. Only the even numbered registers actually exist, |
61a55e8b | 3907 | and none can hold SFmode/SImode values. */ |
d0cee9ba JJ |
3908 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
3909 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3910 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3911 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
61a55e8b DE |
3912 | |
3913 | /* %fcc[0123] */ | |
c4ce6853 DE |
3914 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
3915 | ||
3916 | /* %icc */ | |
3917 | CC_MODES | |
61a55e8b DE |
3918 | }; |
3919 | ||
3920 | int sparc_mode_class [NUM_MACHINE_MODES]; | |
3921 | ||
c4ce6853 DE |
3922 | enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
3923 | ||
61a55e8b | 3924 | static void |
fc27d102 | 3925 | sparc_init_modes (void) |
61a55e8b DE |
3926 | { |
3927 | int i; | |
3928 | ||
61a55e8b DE |
3929 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
3930 | { | |
3931 | switch (GET_MODE_CLASS (i)) | |
3932 | { | |
3933 | case MODE_INT: | |
3934 | case MODE_PARTIAL_INT: | |
3935 | case MODE_COMPLEX_INT: | |
3936 | if (GET_MODE_SIZE (i) <= 4) | |
3937 | sparc_mode_class[i] = 1 << (int) S_MODE; | |
3938 | else if (GET_MODE_SIZE (i) == 8) | |
3939 | sparc_mode_class[i] = 1 << (int) D_MODE; | |
3940 | else if (GET_MODE_SIZE (i) == 16) | |
3941 | sparc_mode_class[i] = 1 << (int) T_MODE; | |
3942 | else if (GET_MODE_SIZE (i) == 32) | |
3943 | sparc_mode_class[i] = 1 << (int) O_MODE; | |
3944 | else | |
3945 | sparc_mode_class[i] = 0; | |
3946 | break; | |
3947 | case MODE_FLOAT: | |
3948 | case MODE_COMPLEX_FLOAT: | |
3949 | if (GET_MODE_SIZE (i) <= 4) | |
3950 | sparc_mode_class[i] = 1 << (int) SF_MODE; | |
3951 | else if (GET_MODE_SIZE (i) == 8) | |
3952 | sparc_mode_class[i] = 1 << (int) DF_MODE; | |
3953 | else if (GET_MODE_SIZE (i) == 16) | |
3954 | sparc_mode_class[i] = 1 << (int) TF_MODE; | |
3955 | else if (GET_MODE_SIZE (i) == 32) | |
3956 | sparc_mode_class[i] = 1 << (int) OF_MODE; | |
3957 | else | |
3958 | sparc_mode_class[i] = 0; | |
3959 | break; | |
3960 | case MODE_CC: | |
61a55e8b DE |
3961 | if (i == (int) CCFPmode || i == (int) CCFPEmode) |
3962 | sparc_mode_class[i] = 1 << (int) CCFP_MODE; | |
61a55e8b | 3963 | else |
94134f42 ZW |
3964 | sparc_mode_class[i] = 1 << (int) CC_MODE; |
3965 | break; | |
3966 | default: | |
3967 | sparc_mode_class[i] = 0; | |
61a55e8b DE |
3968 | break; |
3969 | } | |
3970 | } | |
3971 | ||
a9e27770 | 3972 | if (TARGET_ARCH64) |
61a55e8b DE |
3973 | hard_regno_mode_classes = hard_64bit_mode_classes; |
3974 | else | |
3975 | hard_regno_mode_classes = hard_32bit_mode_classes; | |
c4ce6853 DE |
3976 | |
3977 | /* Initialize the array used by REGNO_REG_CLASS. */ | |
3978 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3979 | { | |
284d86e9 JC |
3980 | if (i < 16 && TARGET_V8PLUS) |
3981 | sparc_regno_reg_class[i] = I64_REGS; | |
563c12b0 | 3982 | else if (i < 32 || i == FRAME_POINTER_REGNUM) |
c4ce6853 DE |
3983 | sparc_regno_reg_class[i] = GENERAL_REGS; |
3984 | else if (i < 64) | |
3985 | sparc_regno_reg_class[i] = FP_REGS; | |
3986 | else if (i < 96) | |
3987 | sparc_regno_reg_class[i] = EXTRA_FP_REGS; | |
3988 | else if (i < 100) | |
3989 | sparc_regno_reg_class[i] = FPCC_REGS; | |
3990 | else | |
3991 | sparc_regno_reg_class[i] = NO_REGS; | |
3992 | } | |
61a55e8b | 3993 | } |
ab835497 | 3994 | \f |
61a55e8b DE |
3995 | /* Save non call used registers from LOW to HIGH at BASE+OFFSET. |
3996 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
3997 | v9 int regs as it simplifies the code. */ | |
3998 | ||
ab835497 | 3999 | static int |
fc27d102 | 4000 | save_regs (FILE *file, int low, int high, const char *base, |
6a151f87 | 4001 | int offset, int n_regs, HOST_WIDE_INT real_offset) |
ab835497 RK |
4002 | { |
4003 | int i; | |
4004 | ||
a9e27770 | 4005 | if (TARGET_ARCH64 && high <= 32) |
ab835497 | 4006 | { |
61a55e8b DE |
4007 | for (i = low; i < high; i++) |
4008 | { | |
4009 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 4010 | { |
e0d80184 | 4011 | fprintf (file, "\tstx\t%s, [%s+%d]\n", |
c53aa195 | 4012 | reg_names[i], base, offset + 4 * n_regs); |
0021b564 | 4013 | if (dwarf2out_do_frame ()) |
c53aa195 | 4014 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); |
c53aa195 JM |
4015 | n_regs += 2; |
4016 | } | |
61a55e8b | 4017 | } |
ab835497 | 4018 | } |
61a55e8b DE |
4019 | else |
4020 | { | |
4021 | for (i = low; i < high; i += 2) | |
4022 | { | |
4023 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 4024 | { |
5e9defae KG |
4025 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) |
4026 | { | |
e0d80184 | 4027 | fprintf (file, "\tstd\t%s, [%s+%d]\n", |
5e9defae KG |
4028 | reg_names[i], base, offset + 4 * n_regs); |
4029 | if (dwarf2out_do_frame ()) | |
4030 | { | |
4031 | char *l = dwarf2out_cfi_label (); | |
4032 | dwarf2out_reg_save (l, i, real_offset + 4 * n_regs); | |
4033 | dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4); | |
4034 | } | |
4035 | n_regs += 2; | |
4036 | } | |
4037 | else | |
4038 | { | |
e0d80184 | 4039 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
4040 | reg_names[i], base, offset + 4 * n_regs); |
4041 | if (dwarf2out_do_frame ()) | |
4042 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); | |
4043 | n_regs += 2; | |
4044 | } | |
4045 | } | |
4046 | else | |
4047 | { | |
4048 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
4049 | { | |
e0d80184 | 4050 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
4051 | reg_names[i+1], base, offset + 4 * n_regs + 4); |
4052 | if (dwarf2out_do_frame ()) | |
4053 | dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4); | |
4054 | n_regs += 2; | |
4055 | } | |
c53aa195 | 4056 | } |
61a55e8b DE |
4057 | } |
4058 | } | |
4059 | return n_regs; | |
ab835497 RK |
4060 | } |
4061 | ||
61a55e8b DE |
4062 | /* Restore non call used registers from LOW to HIGH at BASE+OFFSET. |
4063 | ||
4064 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
4065 | v9 int regs as it simplifies the code. */ | |
4066 | ||
ab835497 | 4067 | static int |
fc27d102 KG |
4068 | restore_regs (FILE *file, int low, int high, const char *base, |
4069 | int offset, int n_regs) | |
ab835497 RK |
4070 | { |
4071 | int i; | |
4072 | ||
a9e27770 | 4073 | if (TARGET_ARCH64 && high <= 32) |
61a55e8b DE |
4074 | { |
4075 | for (i = low; i < high; i++) | |
4076 | { | |
4077 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
e0d80184 | 4078 | fprintf (file, "\tldx\t[%s+%d], %s\n", |
61a55e8b DE |
4079 | base, offset + 4 * n_regs, reg_names[i]), |
4080 | n_regs += 2; | |
4081 | } | |
4082 | } | |
4083 | else | |
ab835497 | 4084 | { |
61a55e8b DE |
4085 | for (i = low; i < high; i += 2) |
4086 | { | |
4087 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
4088 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
e0d80184 | 4089 | fprintf (file, "\tldd\t[%s+%d], %s\n", |
61a55e8b DE |
4090 | base, offset + 4 * n_regs, reg_names[i]), |
4091 | n_regs += 2; | |
4092 | else | |
4df1190a | 4093 | fprintf (file, "\tld\t[%s+%d], %s\n", |
61a55e8b DE |
4094 | base, offset + 4 * n_regs, reg_names[i]), |
4095 | n_regs += 2; | |
4096 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
4df1190a | 4097 | fprintf (file, "\tld\t[%s+%d], %s\n", |
61a55e8b DE |
4098 | base, offset + 4 * n_regs + 4, reg_names[i+1]), |
4099 | n_regs += 2; | |
4100 | } | |
ab835497 | 4101 | } |
61a55e8b | 4102 | return n_regs; |
ab835497 RK |
4103 | } |
4104 | ||
61a55e8b DE |
4105 | /* Compute the frame size required by the function. This function is called |
4106 | during the reload pass and also by output_function_prologue(). */ | |
ab835497 | 4107 | |
6a151f87 EB |
4108 | HOST_WIDE_INT |
4109 | compute_frame_size (HOST_WIDE_INT size, int leaf_function) | |
ab835497 | 4110 | { |
61a55e8b | 4111 | int n_regs = 0, i; |
ab835497 | 4112 | int outgoing_args_size = (current_function_outgoing_args_size |
4fb4e4b8 | 4113 | + REG_PARM_STACK_SPACE (current_function_decl)); |
ab835497 | 4114 | |
33074e5f RH |
4115 | /* N_REGS is the number of 4-byte regs saved thus far. This applies |
4116 | even to v9 int regs to be consistent with save_regs/restore_regs. */ | |
61a55e8b | 4117 | |
33074e5f RH |
4118 | if (TARGET_ARCH64) |
4119 | { | |
4120 | for (i = 0; i < 8; i++) | |
4121 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
4122 | n_regs += 2; | |
4123 | } | |
4124 | else | |
4125 | { | |
4126 | for (i = 0; i < 8; i += 2) | |
ab835497 RK |
4127 | if ((regs_ever_live[i] && ! call_used_regs[i]) |
4128 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
61a55e8b | 4129 | n_regs += 2; |
ab835497 RK |
4130 | } |
4131 | ||
33074e5f RH |
4132 | for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) |
4133 | if ((regs_ever_live[i] && ! call_used_regs[i]) | |
4134 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
4135 | n_regs += 2; | |
4136 | ||
ab835497 | 4137 | /* Set up values for use in `function_epilogue'. */ |
61a55e8b | 4138 | num_gfregs = n_regs; |
ab835497 | 4139 | |
61a55e8b DE |
4140 | if (leaf_function && n_regs == 0 |
4141 | && size == 0 && current_function_outgoing_args_size == 0) | |
4142 | { | |
4143 | actual_fsize = apparent_fsize = 0; | |
4144 | } | |
4145 | else | |
4146 | { | |
225909c3 JS |
4147 | /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */ |
4148 | apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8; | |
61a55e8b DE |
4149 | apparent_fsize += n_regs * 4; |
4150 | actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); | |
4151 | } | |
ab835497 RK |
4152 | |
4153 | /* Make sure nothing can clobber our register windows. | |
4154 | If a SAVE must be done, or there is a stack-local variable, | |
61a55e8b | 4155 | the register window area must be allocated. |
4fb4e4b8 | 4156 | ??? For v8 we apparently need an additional 8 bytes of reserved space. */ |
ab835497 | 4157 | if (leaf_function == 0 || size > 0) |
4fb4e4b8 | 4158 | actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8); |
ab835497 | 4159 | |
61a55e8b DE |
4160 | return SPARC_STACK_ALIGN (actual_fsize); |
4161 | } | |
4162 | ||
6a151f87 EB |
4163 | /* Build big number NUM in register REG and output the result to FILE. |
4164 | REG is guaranteed to be the only clobbered register. The function | |
4165 | will very likely emit several instructions, so it must not be called | |
4166 | from within a delay slot. */ | |
61a55e8b DE |
4167 | |
4168 | static void | |
6a151f87 | 4169 | build_big_number (FILE *file, HOST_WIDE_INT num, const char *reg) |
61a55e8b | 4170 | { |
6a151f87 EB |
4171 | #if HOST_BITS_PER_WIDE_INT == 64 |
4172 | HOST_WIDE_INT high_bits = (num >> 32) & 0xffffffff; | |
4173 | ||
4174 | if (high_bits == 0 | |
4175 | #else | |
4176 | if (num >= 0 | |
4177 | #endif | |
4178 | || ! TARGET_ARCH64) | |
61a55e8b | 4179 | { |
6a151f87 EB |
4180 | /* We don't use the 'set' macro because it appears to be broken |
4181 | in the Solaris 7 assembler. */ | |
4182 | fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n", | |
4183 | num, reg); | |
61a55e8b | 4184 | if ((num & 0x3ff) != 0) |
6a151f87 EB |
4185 | fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n", |
4186 | reg, num, reg); | |
61a55e8b | 4187 | } |
6a151f87 EB |
4188 | #if HOST_BITS_PER_WIDE_INT == 64 |
4189 | else if (high_bits == 0xffffffff) /* && TARGET_ARCH64 */ | |
4190 | #else | |
a9e27770 | 4191 | else /* num < 0 && TARGET_ARCH64 */ |
6a151f87 | 4192 | #endif |
61a55e8b DE |
4193 | { |
4194 | /* Sethi does not sign extend, so we must use a little trickery | |
4195 | to use it for negative numbers. Invert the constant before | |
4196 | loading it in, then use xor immediate to invert the loaded bits | |
4197 | (along with the upper 32 bits) to the desired constant. This | |
4198 | works because the sethi and immediate fields overlap. */ | |
6a151f87 EB |
4199 | HOST_WIDE_INT inv = ~num; |
4200 | HOST_WIDE_INT low = -0x400 + (num & 0x3ff); | |
61a55e8b | 4201 | |
6a151f87 EB |
4202 | fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n", |
4203 | inv, reg); | |
4204 | fprintf (file, "\txor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n", | |
4205 | reg, low, reg); | |
61a55e8b | 4206 | } |
6a151f87 EB |
4207 | #if HOST_BITS_PER_WIDE_INT == 64 |
4208 | else /* TARGET_ARCH64 */ | |
4209 | { | |
4210 | /* We don't use the 'setx' macro because if requires a scratch register. | |
4211 | This is the translation of sparc_emit_set_const64_longway into asm. | |
4212 | Hopefully we will soon have prologue/epilogue emitted as RTL. */ | |
4213 | HOST_WIDE_INT low1 = (num >> (32 - 12)) & 0xfff; | |
4214 | HOST_WIDE_INT low2 = (num >> (32 - 12 - 12)) & 0xfff; | |
4215 | HOST_WIDE_INT low3 = (num >> (32 - 12 - 12 - 8)) & 0x0ff; | |
4216 | int to_shift = 12; | |
4217 | ||
4218 | /* We don't use the 'set' macro because it appears to be broken | |
4219 | in the Solaris 7 assembler. */ | |
4220 | fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n", | |
4221 | high_bits, reg); | |
4222 | if ((high_bits & 0x3ff) != 0) | |
4223 | fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n", | |
4224 | reg, high_bits, reg); | |
4225 | ||
4226 | if (low1 != 0) | |
4227 | { | |
4228 | fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg); | |
4229 | fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n", | |
4230 | reg, low1, reg); | |
4231 | to_shift = 12; | |
4232 | } | |
4233 | else | |
4234 | { | |
4235 | to_shift += 12; | |
4236 | } | |
4237 | if (low2 != 0) | |
4238 | { | |
4239 | fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg); | |
4240 | fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n", | |
4241 | reg, low2, reg); | |
4242 | to_shift = 8; | |
4243 | } | |
4244 | else | |
4245 | { | |
4246 | to_shift += 8; | |
4247 | } | |
4248 | fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg); | |
4249 | if (low3 != 0) | |
4250 | fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n", | |
4251 | reg, low3, reg); | |
4252 | } | |
4253 | #endif | |
ab835497 RK |
4254 | } |
4255 | ||
1cb36a98 RH |
4256 | /* Output any necessary .register pseudo-ops. */ |
4257 | void | |
fc27d102 | 4258 | sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED) |
1cb36a98 RH |
4259 | { |
4260 | #ifdef HAVE_AS_REGISTER_PSEUDO_OP | |
4261 | int i; | |
4262 | ||
4263 | if (TARGET_ARCH32) | |
4264 | return; | |
4265 | ||
4266 | /* Check if %g[2367] were used without | |
4267 | .register being printed for them already. */ | |
4268 | for (i = 2; i < 8; i++) | |
4269 | { | |
4270 | if (regs_ever_live [i] | |
4271 | && ! sparc_hard_reg_printed [i]) | |
4272 | { | |
4273 | sparc_hard_reg_printed [i] = 1; | |
4274 | fprintf (file, "\t.register\t%%g%d, #scratch\n", i); | |
4275 | } | |
4276 | if (i == 3) i = 5; | |
4277 | } | |
4278 | #endif | |
4279 | } | |
4280 | ||
08c148a8 NB |
4281 | /* This function generates the assembly code for function entry. |
4282 | FILE is a stdio stream to output the code to. | |
4283 | SIZE is an int: how many units of temporary storage to allocate. | |
4284 | Refer to the array `regs_ever_live' to determine which registers | |
4285 | to save; `regs_ever_live[I]' is nonzero if register number I | |
4286 | is ever used in the function. This macro is responsible for | |
4287 | knowing which registers should not be saved even if used. */ | |
4288 | ||
4289 | /* On SPARC, move-double insns between fpu and cpu need an 8-byte block | |
4290 | of memory. If any fpu reg is used in the function, we allocate | |
4291 | such a block here, at the bottom of the frame, just in case it's needed. | |
4292 | ||
4293 | If this function is a leaf procedure, then we may choose not | |
4294 | to do a "save" insn. The decision about whether or not | |
4295 | to do this is made in regclass.c. */ | |
4296 | ||
4297 | static void | |
fc27d102 | 4298 | sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size) |
08c148a8 NB |
4299 | { |
4300 | if (TARGET_FLAT) | |
4301 | sparc_flat_function_prologue (file, size); | |
4302 | else | |
4303 | sparc_nonflat_function_prologue (file, size, | |
4304 | current_function_uses_only_leaf_regs); | |
4305 | } | |
4306 | ||
915f619f JW |
4307 | /* Output code for the function prologue. */ |
4308 | ||
08c148a8 | 4309 | static void |
fc27d102 KG |
4310 | sparc_nonflat_function_prologue (FILE *file, HOST_WIDE_INT size, |
4311 | int leaf_function) | |
ab835497 | 4312 | { |
1cb36a98 RH |
4313 | sparc_output_scratch_registers (file); |
4314 | ||
915f619f JW |
4315 | /* Need to use actual_fsize, since we are also allocating |
4316 | space for our callee (and our own register save area). */ | |
ab835497 RK |
4317 | actual_fsize = compute_frame_size (size, leaf_function); |
4318 | ||
61a55e8b DE |
4319 | if (leaf_function) |
4320 | { | |
4321 | frame_base_name = "%sp"; | |
4322 | frame_base_offset = actual_fsize + SPARC_STACK_BIAS; | |
4323 | } | |
4324 | else | |
4325 | { | |
4326 | frame_base_name = "%fp"; | |
4327 | frame_base_offset = SPARC_STACK_BIAS; | |
4328 | } | |
4329 | ||
c6aa9ce1 | 4330 | /* This is only for the human reader. */ |
bf62bbf1 | 4331 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
c6aa9ce1 | 4332 | |
915f619f JW |
4333 | if (actual_fsize == 0) |
4334 | /* do nothing. */ ; | |
e6c1be7e | 4335 | else if (! leaf_function) |
ab835497 | 4336 | { |
3592ea0d | 4337 | if (actual_fsize <= 4096) |
6a151f87 EB |
4338 | fprintf (file, "\tsave\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", |
4339 | actual_fsize); | |
3592ea0d | 4340 | else if (actual_fsize <= 8192) |
915f619f | 4341 | { |
e0d80184 | 4342 | fprintf (file, "\tsave\t%%sp, -4096, %%sp\n"); |
6a151f87 EB |
4343 | fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", |
4344 | actual_fsize - 4096); | |
915f619f JW |
4345 | } |
4346 | else | |
4347 | { | |
3592ea0d | 4348 | build_big_number (file, -actual_fsize, "%g1"); |
e0d80184 | 4349 | fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); |
915f619f | 4350 | } |
ab835497 | 4351 | } |
5f4241d5 DE |
4352 | else /* leaf function */ |
4353 | { | |
3592ea0d | 4354 | if (actual_fsize <= 4096) |
6a151f87 EB |
4355 | fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", |
4356 | actual_fsize); | |
3592ea0d DE |
4357 | else if (actual_fsize <= 8192) |
4358 | { | |
e0d80184 | 4359 | fprintf (file, "\tadd\t%%sp, -4096, %%sp\n"); |
6a151f87 EB |
4360 | fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", |
4361 | actual_fsize - 4096); | |
3592ea0d | 4362 | } |
915f619f | 4363 | else |
3592ea0d DE |
4364 | { |
4365 | build_big_number (file, -actual_fsize, "%g1"); | |
e0d80184 | 4366 | fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n"); |
3592ea0d | 4367 | } |
ab835497 RK |
4368 | } |
4369 | ||
0021b564 | 4370 | if (dwarf2out_do_frame () && actual_fsize) |
c53aa195 | 4371 | { |
96987e96 | 4372 | char *label = dwarf2out_cfi_label (); |
c53aa195 JM |
4373 | |
4374 | /* The canonical frame address refers to the top of the frame. */ | |
4375 | dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM | |
563c12b0 | 4376 | : HARD_FRAME_POINTER_REGNUM), |
c53aa195 JM |
4377 | frame_base_offset); |
4378 | ||
4379 | if (! leaf_function) | |
4380 | { | |
4381 | /* Note the register window save. This tells the unwinder that | |
4382 | it needs to restore the window registers from the previous | |
4383 | frame's window save area at 0(cfa). */ | |
4384 | dwarf2out_window_save (label); | |
4385 | ||
4386 | /* The return address (-8) is now in %i7. */ | |
4387 | dwarf2out_return_reg (label, 31); | |
4388 | } | |
4389 | } | |
c53aa195 | 4390 | |
ab835497 RK |
4391 | /* If doing anything with PIC, do it now. */ |
4392 | if (! flag_pic) | |
bf62bbf1 | 4393 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
ab835497 | 4394 | |
61a55e8b DE |
4395 | /* Call saved registers are saved just above the outgoing argument area. */ |
4396 | if (num_gfregs) | |
ab835497 | 4397 | { |
6a151f87 EB |
4398 | HOST_WIDE_INT offset, real_offset; |
4399 | int n_regs; | |
3bb5de61 | 4400 | const char *base; |
ab835497 | 4401 | |
84e884e9 JM |
4402 | real_offset = -apparent_fsize; |
4403 | offset = -apparent_fsize + frame_base_offset; | |
61a55e8b DE |
4404 | if (offset < -4096 || offset + num_gfregs * 4 > 4096) |
4405 | { | |
4406 | /* ??? This might be optimized a little as %g1 might already have a | |
4407 | value close enough that a single add insn will do. */ | |
4408 | /* ??? Although, all of this is probably only a temporary fix | |
4409 | because if %g1 can hold a function result, then | |
4410 | output_function_epilogue will lose (the result will get | |
4411 | clobbered). */ | |
4412 | build_big_number (file, offset, "%g1"); | |
e0d80184 | 4413 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); |
61a55e8b DE |
4414 | base = "%g1"; |
4415 | offset = 0; | |
4416 | } | |
ab835497 | 4417 | else |
61a55e8b DE |
4418 | { |
4419 | base = frame_base_name; | |
4420 | } | |
ab835497 | 4421 | |
33074e5f RH |
4422 | n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); |
4423 | save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs, | |
4424 | real_offset); | |
ab835497 RK |
4425 | } |
4426 | } | |
4427 | ||
7d167afd JJ |
4428 | /* Output code to restore any call saved registers. */ |
4429 | ||
4430 | static void | |
fc27d102 | 4431 | output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED) |
7d167afd | 4432 | { |
6a151f87 EB |
4433 | HOST_WIDE_INT offset; |
4434 | int n_regs; | |
7d167afd JJ |
4435 | const char *base; |
4436 | ||
4437 | offset = -apparent_fsize + frame_base_offset; | |
4438 | if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) | |
4439 | { | |
4440 | build_big_number (file, offset, "%g1"); | |
4441 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); | |
4442 | base = "%g1"; | |
4443 | offset = 0; | |
4444 | } | |
4445 | else | |
4446 | { | |
4447 | base = frame_base_name; | |
4448 | } | |
4449 | ||
33074e5f RH |
4450 | n_regs = restore_regs (file, 0, 8, base, offset, 0); |
4451 | restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); | |
7d167afd JJ |
4452 | } |
4453 | ||
08c148a8 NB |
4454 | /* This function generates the assembly code for function exit, |
4455 | on machines that need it. | |
4456 | ||
4457 | The function epilogue should not depend on the current stack pointer! | |
4458 | It should use the frame pointer only. This is mandatory because | |
4459 | of alloca; we also take advantage of it to omit stack adjustments | |
4460 | before returning. */ | |
4461 | ||
4462 | static void | |
fc27d102 | 4463 | sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size) |
08c148a8 NB |
4464 | { |
4465 | if (TARGET_FLAT) | |
4466 | sparc_flat_function_epilogue (file, size); | |
4467 | else | |
4468 | sparc_nonflat_function_epilogue (file, size, | |
4469 | current_function_uses_only_leaf_regs); | |
4470 | } | |
4471 | ||
915f619f JW |
4472 | /* Output code for the function epilogue. */ |
4473 | ||
08c148a8 | 4474 | static void |
fc27d102 KG |
4475 | sparc_nonflat_function_epilogue (FILE *file, |
4476 | HOST_WIDE_INT size ATTRIBUTE_UNUSED, | |
4477 | int leaf_function) | |
ab835497 | 4478 | { |
3bb5de61 | 4479 | const char *ret; |
ab835497 | 4480 | |
8456b95a | 4481 | if (current_function_epilogue_delay_list == 0) |
e48addee | 4482 | { |
e0d80184 | 4483 | /* If code does not drop into the epilogue, we need |
7a31a340 DM |
4484 | do nothing except output pending case vectors. |
4485 | ||
4486 | We have to still output a dummy nop for the sake of | |
4487 | sane backtraces. Otherwise, if the last two instructions | |
4488 | of a function were call foo; dslot; this can make the return | |
4489 | PC of foo (ie. address of call instruction plus 8) point to | |
4490 | the first instruction in the next function. */ | |
ac59ed37 | 4491 | rtx insn, last_real_insn; |
7a31a340 DM |
4492 | |
4493 | insn = get_last_insn (); | |
ac59ed37 DM |
4494 | |
4495 | last_real_insn = prev_real_insn (insn); | |
4496 | if (last_real_insn | |
4497 | && GET_CODE (last_real_insn) == INSN | |
4498 | && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE) | |
4499 | last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0); | |
4500 | ||
4501 | if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN) | |
4502 | fputs("\tnop\n", file); | |
4503 | ||
7a31a340 DM |
4504 | if (GET_CODE (insn) == NOTE) |
4505 | insn = prev_nonnote_insn (insn); | |
4506 | if (insn && GET_CODE (insn) == BARRIER) | |
4507 | goto output_vectors; | |
bfd6bc60 JC |
4508 | } |
4509 | ||
61a55e8b | 4510 | if (num_gfregs) |
7d167afd | 4511 | output_restore_regs (file, leaf_function); |
ab835497 RK |
4512 | |
4513 | /* Work out how to skip the caller's unimp instruction if required. */ | |
4514 | if (leaf_function) | |
e0d80184 | 4515 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl"); |
ab835497 | 4516 | else |
e0d80184 | 4517 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret"); |
ab835497 | 4518 | |
33074e5f | 4519 | if (! leaf_function) |
ab835497 | 4520 | { |
33074e5f RH |
4521 | if (current_function_calls_eh_return) |
4522 | { | |
4523 | if (current_function_epilogue_delay_list) | |
4524 | abort (); | |
4525 | if (SKIP_CALLERS_UNIMP_P) | |
4526 | abort (); | |
ab835497 | 4527 | |
33074e5f RH |
4528 | fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file); |
4529 | } | |
4530 | /* If we wound up with things in our delay slot, flush them here. */ | |
4531 | else if (current_function_epilogue_delay_list) | |
ef8200df | 4532 | { |
33074e5f | 4533 | rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0)); |
1150a841 | 4534 | |
33074e5f RH |
4535 | if (TARGET_V9 && ! epilogue_renumber (&delay, 1)) |
4536 | { | |
4537 | epilogue_renumber (&delay, 0); | |
4538 | fputs (SKIP_CALLERS_UNIMP_P | |
4539 | ? "\treturn\t%i7+12\n" | |
4540 | : "\treturn\t%i7+8\n", file); | |
4541 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
5cfc5f84 | 4542 | file, 1, 0, 0, NULL); |
1150a841 | 4543 | } |
33074e5f | 4544 | else |
ab835497 | 4545 | { |
33074e5f | 4546 | rtx insn, src; |
e48addee | 4547 | |
33074e5f RH |
4548 | if (GET_CODE (delay) != SET) |
4549 | abort(); | |
e48addee | 4550 | |
33074e5f RH |
4551 | src = SET_SRC (delay); |
4552 | if (GET_CODE (src) == ASHIFT) | |
4553 | { | |
4554 | if (XEXP (src, 1) != const1_rtx) | |
e48addee | 4555 | abort(); |
33074e5f RH |
4556 | SET_SRC (delay) |
4557 | = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0), | |
4558 | XEXP (src, 0)); | |
4559 | } | |
e48addee | 4560 | |
33074e5f RH |
4561 | insn = gen_rtx_PARALLEL (VOIDmode, |
4562 | gen_rtvec (2, delay, | |
4563 | gen_rtx_RETURN (VOIDmode))); | |
4564 | insn = emit_jump_insn (insn); | |
e48addee | 4565 | |
33074e5f | 4566 | sparc_emitting_epilogue = true; |
5cfc5f84 | 4567 | final_scan_insn (insn, file, 1, 0, 1, NULL); |
33074e5f | 4568 | sparc_emitting_epilogue = false; |
ab835497 | 4569 | } |
ef8200df | 4570 | } |
33074e5f RH |
4571 | else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P) |
4572 | fputs ("\treturn\t%i7+8\n\tnop\n", file); | |
4573 | else | |
4574 | fprintf (file, "\t%s\n\trestore\n", ret); | |
4575 | } | |
4576 | /* All of the following cases are for leaf functions. */ | |
4577 | else if (current_function_calls_eh_return) | |
4578 | abort (); | |
4579 | else if (current_function_epilogue_delay_list) | |
4580 | { | |
4581 | /* eligible_for_epilogue_delay_slot ensures that if this is a | |
4582 | leaf function, then we will only have insn in the delay slot | |
4583 | if the frame size is zero, thus no adjust for the stack is | |
4584 | needed here. */ | |
4585 | if (actual_fsize != 0) | |
1150a841 | 4586 | abort (); |
33074e5f RH |
4587 | fprintf (file, "\t%s\n", ret); |
4588 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
5cfc5f84 | 4589 | file, 1, 0, 1, NULL); |
ab835497 | 4590 | } |
33074e5f RH |
4591 | /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to |
4592 | avoid generating confusing assembly language output. */ | |
4593 | else if (actual_fsize == 0) | |
4594 | fprintf (file, "\t%s\n\tnop\n", ret); | |
4595 | else if (actual_fsize <= 4096) | |
6a151f87 EB |
4596 | fprintf (file, "\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", |
4597 | ret, actual_fsize); | |
33074e5f | 4598 | else if (actual_fsize <= 8192) |
6a151f87 | 4599 | fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", |
33074e5f | 4600 | ret, actual_fsize - 4096); |
6a151f87 EB |
4601 | else |
4602 | { | |
4603 | build_big_number (file, actual_fsize, "%g1"); | |
4604 | fprintf (file, "\t%s\n\tadd\t%%sp, %%g1, %%sp\n", ret); | |
4605 | } | |
e0d80184 DM |
4606 | |
4607 | output_vectors: | |
4608 | sparc_output_deferred_case_vectors (); | |
ab835497 | 4609 | } |
7d167afd JJ |
4610 | |
4611 | /* Output a sibling call. */ | |
4612 | ||
4613 | const char * | |
fc27d102 | 4614 | output_sibcall (rtx insn, rtx call_operand) |
7d167afd JJ |
4615 | { |
4616 | int leaf_regs = current_function_uses_only_leaf_regs; | |
4617 | rtx operands[3]; | |
4618 | int delay_slot = dbr_sequence_length () > 0; | |
4619 | ||
4620 | if (num_gfregs) | |
4621 | { | |
4622 | /* Call to restore global regs might clobber | |
4623 | the delay slot. Instead of checking for this | |
4624 | output the delay slot now. */ | |
4625 | if (delay_slot) | |
4626 | { | |
4627 | rtx delay = NEXT_INSN (insn); | |
4628 | ||
4629 | if (! delay) | |
4630 | abort (); | |
4631 | ||
5cfc5f84 | 4632 | final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL); |
7d167afd JJ |
4633 | PATTERN (delay) = gen_blockage (); |
4634 | INSN_CODE (delay) = -1; | |
4635 | delay_slot = 0; | |
4636 | } | |
4637 | output_restore_regs (asm_out_file, leaf_regs); | |
4638 | } | |
4639 | ||
4640 | operands[0] = call_operand; | |
4641 | ||
4642 | if (leaf_regs) | |
4643 | { | |
e95b1e6a JJ |
4644 | #ifdef HAVE_AS_RELAX_OPTION |
4645 | /* If as and ld are relaxing tail call insns into branch always, | |
4646 | use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can | |
4647 | be optimized. With sethi/jmpl as nor ld has no easy way how to | |
4648 | find out if somebody does not branch between the sethi and jmpl. */ | |
4649 | int spare_slot = 0; | |
4650 | #else | |
2be5e524 | 4651 | int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic); |
e95b1e6a | 4652 | #endif |
6a151f87 | 4653 | HOST_WIDE_INT size = 0; |
7d167afd JJ |
4654 | |
4655 | if ((actual_fsize || ! spare_slot) && delay_slot) | |
4656 | { | |
4657 | rtx delay = NEXT_INSN (insn); | |
4658 | ||
4659 | if (! delay) | |
4660 | abort (); | |
4661 | ||
5cfc5f84 | 4662 | final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL); |
7d167afd JJ |
4663 | PATTERN (delay) = gen_blockage (); |
4664 | INSN_CODE (delay) = -1; | |
4665 | delay_slot = 0; | |
4666 | } | |
4667 | if (actual_fsize) | |
4668 | { | |
4669 | if (actual_fsize <= 4096) | |
4670 | size = actual_fsize; | |
4671 | else if (actual_fsize <= 8192) | |
4672 | { | |
4673 | fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file); | |
4674 | size = actual_fsize - 4096; | |
4675 | } | |
7d167afd JJ |
4676 | else |
4677 | { | |
6a151f87 | 4678 | build_big_number (asm_out_file, actual_fsize, "%g1"); |
7d167afd JJ |
4679 | fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file); |
4680 | } | |
4681 | } | |
4682 | if (spare_slot) | |
4683 | { | |
4684 | output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands); | |
4685 | output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands); | |
4686 | if (size) | |
6a151f87 | 4687 | fprintf (asm_out_file, "\t sub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size); |
7d167afd JJ |
4688 | else if (! delay_slot) |
4689 | fputs ("\t nop\n", asm_out_file); | |
4690 | } | |
4691 | else | |
4692 | { | |
4693 | if (size) | |
6a151f87 | 4694 | fprintf (asm_out_file, "\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size); |
e95b1e6a JJ |
4695 | /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize |
4696 | it into branch if possible. */ | |
4697 | output_asm_insn ("or\t%%o7, %%g0, %%g1", operands); | |
7d167afd | 4698 | output_asm_insn ("call\t%a0, 0", operands); |
e95b1e6a | 4699 | output_asm_insn (" or\t%%g1, %%g0, %%o7", operands); |
7d167afd JJ |
4700 | } |
4701 | return ""; | |
4702 | } | |
4703 | ||
4704 | output_asm_insn ("call\t%a0, 0", operands); | |
4705 | if (delay_slot) | |
4706 | { | |
4707 | rtx delay = NEXT_INSN (insn), pat; | |
4708 | ||
4709 | if (! delay) | |
4710 | abort (); | |
4711 | ||
4712 | pat = PATTERN (delay); | |
4713 | if (GET_CODE (pat) != SET) | |
4714 | abort (); | |
4715 | ||
4716 | operands[0] = SET_DEST (pat); | |
4717 | pat = SET_SRC (pat); | |
4718 | switch (GET_CODE (pat)) | |
4719 | { | |
4720 | case PLUS: | |
4721 | operands[1] = XEXP (pat, 0); | |
4722 | operands[2] = XEXP (pat, 1); | |
4723 | output_asm_insn (" restore %r1, %2, %Y0", operands); | |
4724 | break; | |
4725 | case LO_SUM: | |
4726 | operands[1] = XEXP (pat, 0); | |
4727 | operands[2] = XEXP (pat, 1); | |
4728 | output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); | |
4729 | break; | |
4730 | case ASHIFT: | |
4731 | operands[1] = XEXP (pat, 0); | |
4732 | output_asm_insn (" restore %r1, %r1, %Y0", operands); | |
4733 | break; | |
4734 | default: | |
4735 | operands[1] = pat; | |
4736 | output_asm_insn (" restore %%g0, %1, %Y0", operands); | |
4737 | break; | |
4738 | } | |
4739 | PATTERN (delay) = gen_blockage (); | |
4740 | INSN_CODE (delay) = -1; | |
4741 | } | |
4742 | else | |
4743 | fputs ("\t restore\n", asm_out_file); | |
4744 | return ""; | |
4745 | } | |
4fb4e4b8 DE |
4746 | \f |
4747 | /* Functions for handling argument passing. | |
4748 | ||
4749 | For v8 the first six args are normally in registers and the rest are | |
4750 | pushed. Any arg that starts within the first 6 words is at least | |
4751 | partially passed in a register unless its data type forbids. | |
4752 | ||
4753 | For v9, the argument registers are laid out as an array of 16 elements | |
4754 | and arguments are added sequentially. The first 6 int args and up to the | |
4755 | first 16 fp args (depending on size) are passed in regs. | |
4756 | ||
4757 | Slot Stack Integral Float Float in structure Double Long Double | |
4758 | ---- ----- -------- ----- ------------------ ------ ----------- | |
4759 | 15 [SP+248] %f31 %f30,%f31 %d30 | |
4760 | 14 [SP+240] %f29 %f28,%f29 %d28 %q28 | |
4761 | 13 [SP+232] %f27 %f26,%f27 %d26 | |
4762 | 12 [SP+224] %f25 %f24,%f25 %d24 %q24 | |
4763 | 11 [SP+216] %f23 %f22,%f23 %d22 | |
4764 | 10 [SP+208] %f21 %f20,%f21 %d20 %q20 | |
4765 | 9 [SP+200] %f19 %f18,%f19 %d18 | |
4766 | 8 [SP+192] %f17 %f16,%f17 %d16 %q16 | |
4767 | 7 [SP+184] %f15 %f14,%f15 %d14 | |
4768 | 6 [SP+176] %f13 %f12,%f13 %d12 %q12 | |
4769 | 5 [SP+168] %o5 %f11 %f10,%f11 %d10 | |
4770 | 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 | |
4771 | 3 [SP+152] %o3 %f7 %f6,%f7 %d6 | |
4772 | 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 | |
4773 | 1 [SP+136] %o1 %f3 %f2,%f3 %d2 | |
4774 | 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 | |
4775 | ||
4776 | Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. | |
4777 | ||
4778 | Integral arguments are always passed as 64 bit quantities appropriately | |
4779 | extended. | |
4780 | ||
4781 | Passing of floating point values is handled as follows. | |
4782 | If a prototype is in scope: | |
4783 | If the value is in a named argument (i.e. not a stdarg function or a | |
4784 | value not part of the `...') then the value is passed in the appropriate | |
4785 | fp reg. | |
4786 | If the value is part of the `...' and is passed in one of the first 6 | |
4787 | slots then the value is passed in the appropriate int reg. | |
4788 | If the value is part of the `...' and is not passed in one of the first 6 | |
4789 | slots then the value is passed in memory. | |
4790 | If a prototype is not in scope: | |
4791 | If the value is one of the first 6 arguments the value is passed in the | |
4792 | appropriate integer reg and the appropriate fp reg. | |
4793 | If the value is not one of the first 6 arguments the value is passed in | |
4794 | the appropriate fp reg and in memory. | |
4795 | */ | |
4796 | ||
4797 | /* Maximum number of int regs for args. */ | |
4798 | #define SPARC_INT_ARG_MAX 6 | |
4799 | /* Maximum number of fp regs for args. */ | |
4800 | #define SPARC_FP_ARG_MAX 16 | |
4801 | ||
4802 | #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
4803 | ||
4804 | /* Handle the INIT_CUMULATIVE_ARGS macro. | |
4805 | Initialize a variable CUM of type CUMULATIVE_ARGS | |
4806 | for a call to a function whose data type is FNTYPE. | |
4807 | For a library call, FNTYPE is 0. */ | |
3ea1fdd3 | 4808 | |
4fb4e4b8 | 4809 | void |
fc27d102 KG |
4810 | init_cumulative_args (struct sparc_args *cum, tree fntype, |
4811 | rtx libname ATTRIBUTE_UNUSED, | |
4812 | tree fndecl ATTRIBUTE_UNUSED) | |
4fb4e4b8 DE |
4813 | { |
4814 | cum->words = 0; | |
4815 | cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); | |
4816 | cum->libcall_p = fntype == 0; | |
4817 | } | |
61a55e8b | 4818 | |
4fb4e4b8 DE |
4819 | /* Compute the slot number to pass an argument in. |
4820 | Returns the slot number or -1 if passing on the stack. | |
4821 | ||
4822 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4823 | the preceding args and about the function being called. | |
4824 | MODE is the argument's machine mode. | |
4825 | TYPE is the data type of the argument (as a tree). | |
4826 | This is null for libcalls where that information may | |
4827 | not be available. | |
4828 | NAMED is nonzero if this argument is a named parameter | |
4829 | (otherwise it is an extra parameter matching an ellipsis). | |
4830 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. | |
4831 | *PREGNO records the register number to use if scalar type. | |
4832 | *PPADDING records the amount of padding needed in words. */ | |
4833 | ||
4834 | static int | |
fc27d102 KG |
4835 | function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode, |
4836 | tree type, int named, int incoming_p, | |
4837 | int *pregno, int *ppadding) | |
4fb4e4b8 DE |
4838 | { |
4839 | int regbase = (incoming_p | |
4840 | ? SPARC_INCOMING_INT_ARG_FIRST | |
4841 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
4842 | int slotno = cum->words; | |
4843 | int regno; | |
4844 | ||
4845 | *ppadding = 0; | |
4846 | ||
4847 | if (type != 0 && TREE_ADDRESSABLE (type)) | |
4848 | return -1; | |
4849 | if (TARGET_ARCH32 | |
4850 | && type != 0 && mode == BLKmode | |
4851 | && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) | |
4852 | return -1; | |
4853 | ||
4854 | switch (mode) | |
4855 | { | |
4856 | case VOIDmode : | |
4857 | /* MODE is VOIDmode when generating the actual call. | |
4858 | See emit_call_1. */ | |
4859 | return -1; | |
4860 | ||
4861 | case QImode : case CQImode : | |
4862 | case HImode : case CHImode : | |
4863 | case SImode : case CSImode : | |
4864 | case DImode : case CDImode : | |
380f6ad3 | 4865 | case TImode : case CTImode : |
4fb4e4b8 DE |
4866 | if (slotno >= SPARC_INT_ARG_MAX) |
4867 | return -1; | |
4868 | regno = regbase + slotno; | |
4869 | break; | |
4870 | ||
4871 | case SFmode : case SCmode : | |
4872 | case DFmode : case DCmode : | |
4873 | case TFmode : case TCmode : | |
4874 | if (TARGET_ARCH32) | |
4875 | { | |
4876 | if (slotno >= SPARC_INT_ARG_MAX) | |
4877 | return -1; | |
4878 | regno = regbase + slotno; | |
4879 | } | |
4880 | else | |
4881 | { | |
4882 | if ((mode == TFmode || mode == TCmode) | |
4883 | && (slotno & 1) != 0) | |
4884 | slotno++, *ppadding = 1; | |
4885 | if (TARGET_FPU && named) | |
4886 | { | |
4887 | if (slotno >= SPARC_FP_ARG_MAX) | |
82d6b402 | 4888 | return -1; |
4fb4e4b8 DE |
4889 | regno = SPARC_FP_ARG_FIRST + slotno * 2; |
4890 | if (mode == SFmode) | |
4891 | regno++; | |
4892 | } | |
4893 | else | |
4894 | { | |
4895 | if (slotno >= SPARC_INT_ARG_MAX) | |
4896 | return -1; | |
4897 | regno = regbase + slotno; | |
4898 | } | |
4899 | } | |
4900 | break; | |
4901 | ||
4902 | case BLKmode : | |
4903 | /* For sparc64, objects requiring 16 byte alignment get it. */ | |
4904 | if (TARGET_ARCH64) | |
4905 | { | |
4906 | if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0) | |
4907 | slotno++, *ppadding = 1; | |
4908 | } | |
4909 | ||
4910 | if (TARGET_ARCH32 | |
5e9defae | 4911 | || (type && TREE_CODE (type) == UNION_TYPE)) |
4fb4e4b8 DE |
4912 | { |
4913 | if (slotno >= SPARC_INT_ARG_MAX) | |
4914 | return -1; | |
4915 | regno = regbase + slotno; | |
4916 | } | |
4917 | else | |
4918 | { | |
4919 | tree field; | |
4920 | int intregs_p = 0, fpregs_p = 0; | |
4921 | /* The ABI obviously doesn't specify how packed | |
4922 | structures are passed. These are defined to be passed | |
4923 | in int regs if possible, otherwise memory. */ | |
4924 | int packed_p = 0; | |
4925 | ||
4926 | /* First see what kinds of registers we need. */ | |
4927 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4928 | { | |
4929 | if (TREE_CODE (field) == FIELD_DECL) | |
4930 | { | |
4931 | if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
4932 | && TARGET_FPU) | |
4933 | fpregs_p = 1; | |
4934 | else | |
4935 | intregs_p = 1; | |
4936 | if (DECL_PACKED (field)) | |
4937 | packed_p = 1; | |
4938 | } | |
4939 | } | |
4940 | if (packed_p || !named) | |
4941 | fpregs_p = 0, intregs_p = 1; | |
4942 | ||
4943 | /* If all arg slots are filled, then must pass on stack. */ | |
4944 | if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) | |
4945 | return -1; | |
4946 | /* If there are only int args and all int arg slots are filled, | |
4947 | then must pass on stack. */ | |
4948 | if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) | |
4949 | return -1; | |
4950 | /* Note that even if all int arg slots are filled, fp members may | |
4951 | still be passed in regs if such regs are available. | |
4952 | *PREGNO isn't set because there may be more than one, it's up | |
4953 | to the caller to compute them. */ | |
4954 | return slotno; | |
4955 | } | |
4956 | break; | |
4957 | ||
4958 | default : | |
4959 | abort (); | |
4960 | } | |
4961 | ||
4962 | *pregno = regno; | |
4963 | return slotno; | |
4964 | } | |
4965 | ||
82d6b402 RH |
4966 | /* Handle recursive register counting for structure field layout. */ |
4967 | ||
4968 | struct function_arg_record_value_parms | |
4969 | { | |
48028e21 EB |
4970 | rtx ret; /* return expression being built. */ |
4971 | int slotno; /* slot number of the argument. */ | |
4972 | int named; /* whether the argument is named. */ | |
4973 | int regbase; /* regno of the base register. */ | |
4974 | int stack; /* 1 if part of the argument is on the stack. */ | |
4975 | int intoffset; /* offset of the pending integer field. */ | |
4976 | unsigned int nregs; /* number of words passed in registers. */ | |
82d6b402 RH |
4977 | }; |
4978 | ||
2a01c939 | 4979 | static void function_arg_record_value_3 |
e80d5f80 | 4980 | (HOST_WIDE_INT, struct function_arg_record_value_parms *); |
2a01c939 | 4981 | static void function_arg_record_value_2 |
cde85594 | 4982 | (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool); |
b1474bb7 | 4983 | static void function_arg_record_value_1 |
cde85594 | 4984 | (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool); |
e80d5f80 | 4985 | static rtx function_arg_record_value (tree, enum machine_mode, int, int, int); |
2a01c939 | 4986 | |
0020b823 | 4987 | /* A subroutine of function_arg_record_value. Traverse the structure |
fae778eb | 4988 | recursively and determine how many registers will be required. */ |
0020b823 | 4989 | |
82d6b402 | 4990 | static void |
fc27d102 | 4991 | function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos, |
cde85594 EB |
4992 | struct function_arg_record_value_parms *parms, |
4993 | bool packed_p) | |
82d6b402 RH |
4994 | { |
4995 | tree field; | |
4996 | ||
82d6b402 RH |
4997 | /* We need to compute how many registers are needed so we can |
4998 | allocate the PARALLEL but before we can do that we need to know | |
cde85594 EB |
4999 | whether there are any packed fields. The ABI obviously doesn't |
5000 | specify how structures are passed in this case, so they are | |
5001 | defined to be passed in int regs if possible, otherwise memory, | |
5002 | regardless of whether there are fp values present. */ | |
5003 | ||
5004 | if (! packed_p) | |
5005 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
5006 | { | |
5007 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
5008 | { | |
5009 | packed_p = true; | |
5010 | break; | |
5011 | } | |
5012 | } | |
82d6b402 RH |
5013 | |
5014 | /* Compute how many registers we need. */ | |
5015 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
5016 | { | |
5017 | if (TREE_CODE (field) == FIELD_DECL) | |
5018 | { | |
75131237 RK |
5019 | HOST_WIDE_INT bitpos = startbitpos; |
5020 | ||
5021 | if (DECL_SIZE (field) != 0 | |
5022 | && host_integerp (bit_position (field), 1)) | |
5023 | bitpos += int_bit_position (field); | |
5024 | ||
82d6b402 RH |
5025 | /* ??? FIXME: else assume zero offset. */ |
5026 | ||
5027 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
cde85594 EB |
5028 | function_arg_record_value_1 (TREE_TYPE (field), |
5029 | bitpos, | |
5030 | parms, | |
5031 | packed_p); | |
105b2084 JJ |
5032 | else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE |
5033 | || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE | |
5034 | && (TREE_CODE (TREE_TYPE (TREE_TYPE (field))) | |
5035 | == REAL_TYPE))) | |
82d6b402 RH |
5036 | && TARGET_FPU |
5037 | && ! packed_p | |
5038 | && parms->named) | |
5039 | { | |
5040 | if (parms->intoffset != -1) | |
5041 | { | |
5042 | int intslots, this_slotno; | |
5043 | ||
5044 | intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1) | |
5045 | / BITS_PER_WORD; | |
5046 | this_slotno = parms->slotno + parms->intoffset | |
5047 | / BITS_PER_WORD; | |
5048 | ||
48028e21 EB |
5049 | if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) |
5050 | { | |
5051 | intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); | |
5052 | /* We need to pass this field on the stack. */ | |
5053 | parms->stack = 1; | |
5054 | } | |
5055 | ||
82d6b402 RH |
5056 | parms->nregs += intslots; |
5057 | parms->intoffset = -1; | |
5058 | } | |
5059 | ||
5060 | /* There's no need to check this_slotno < SPARC_FP_ARG MAX. | |
5061 | If it wasn't true we wouldn't be here. */ | |
5062 | parms->nregs += 1; | |
105b2084 JJ |
5063 | if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) |
5064 | parms->nregs += 1; | |
82d6b402 RH |
5065 | } |
5066 | else | |
5067 | { | |
5068 | if (parms->intoffset == -1) | |
5069 | parms->intoffset = bitpos; | |
5070 | } | |
5071 | } | |
5072 | } | |
5073 | } | |
5074 | ||
0020b823 RH |
5075 | /* A subroutine of function_arg_record_value. Assign the bits of the |
5076 | structure between parms->intoffset and bitpos to integer registers. */ | |
82d6b402 RH |
5077 | |
5078 | static void | |
fc27d102 KG |
5079 | function_arg_record_value_3 (HOST_WIDE_INT bitpos, |
5080 | struct function_arg_record_value_parms *parms) | |
82d6b402 RH |
5081 | { |
5082 | enum machine_mode mode; | |
75131237 | 5083 | unsigned int regno; |
0020b823 | 5084 | unsigned int startbit, endbit; |
75131237 | 5085 | int this_slotno, intslots, intoffset; |
82d6b402 RH |
5086 | rtx reg; |
5087 | ||
5088 | if (parms->intoffset == -1) | |
5089 | return; | |
75131237 | 5090 | |
82d6b402 RH |
5091 | intoffset = parms->intoffset; |
5092 | parms->intoffset = -1; | |
5093 | ||
0020b823 RH |
5094 | startbit = intoffset & -BITS_PER_WORD; |
5095 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
5096 | intslots = (endbit - startbit) / BITS_PER_WORD; | |
82d6b402 RH |
5097 | this_slotno = parms->slotno + intoffset / BITS_PER_WORD; |
5098 | ||
5099 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
5100 | if (intslots <= 0) | |
5101 | return; | |
5102 | ||
5103 | /* If this is the trailing part of a word, only load that much into | |
5104 | the register. Otherwise load the whole register. Note that in | |
5105 | the latter case we may pick up unwanted bits. It's not a problem | |
5106 | at the moment but may wish to revisit. */ | |
5107 | ||
5108 | if (intoffset % BITS_PER_WORD != 0) | |
75131237 RK |
5109 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, |
5110 | MODE_INT, 0); | |
82d6b402 RH |
5111 | else |
5112 | mode = word_mode; | |
5113 | ||
5114 | intoffset /= BITS_PER_UNIT; | |
5115 | do | |
5116 | { | |
5117 | regno = parms->regbase + this_slotno; | |
254110c2 | 5118 | reg = gen_rtx_REG (mode, regno); |
48028e21 | 5119 | XVECEXP (parms->ret, 0, parms->stack + parms->nregs) |
254110c2 | 5120 | = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); |
82d6b402 RH |
5121 | |
5122 | this_slotno += 1; | |
5123 | intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; | |
5124 | parms->nregs += 1; | |
5125 | intslots -= 1; | |
5126 | } | |
5127 | while (intslots > 0); | |
5128 | } | |
5129 | ||
0020b823 RH |
5130 | /* A subroutine of function_arg_record_value. Traverse the structure |
5131 | recursively and assign bits to floating point registers. Track which | |
5132 | bits in between need integer registers; invoke function_arg_record_value_3 | |
5133 | to make that happen. */ | |
5134 | ||
82d6b402 | 5135 | static void |
fc27d102 | 5136 | function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos, |
cde85594 EB |
5137 | struct function_arg_record_value_parms *parms, |
5138 | bool packed_p) | |
82d6b402 RH |
5139 | { |
5140 | tree field; | |
82d6b402 | 5141 | |
cde85594 EB |
5142 | if (! packed_p) |
5143 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
5144 | { | |
5145 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
5146 | { | |
5147 | packed_p = true; | |
5148 | break; | |
5149 | } | |
5150 | } | |
82d6b402 RH |
5151 | |
5152 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
5153 | { | |
5154 | if (TREE_CODE (field) == FIELD_DECL) | |
5155 | { | |
75131237 RK |
5156 | HOST_WIDE_INT bitpos = startbitpos; |
5157 | ||
5158 | if (DECL_SIZE (field) != 0 | |
5159 | && host_integerp (bit_position (field), 1)) | |
5160 | bitpos += int_bit_position (field); | |
5161 | ||
82d6b402 RH |
5162 | /* ??? FIXME: else assume zero offset. */ |
5163 | ||
5164 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
cde85594 EB |
5165 | function_arg_record_value_2 (TREE_TYPE (field), |
5166 | bitpos, | |
5167 | parms, | |
5168 | packed_p); | |
105b2084 JJ |
5169 | else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE |
5170 | || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE | |
5171 | && (TREE_CODE (TREE_TYPE (TREE_TYPE (field))) | |
5172 | == REAL_TYPE))) | |
82d6b402 RH |
5173 | && TARGET_FPU |
5174 | && ! packed_p | |
5175 | && parms->named) | |
5176 | { | |
5177 | int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; | |
105b2084 JJ |
5178 | int regno; |
5179 | enum machine_mode mode = DECL_MODE (field); | |
82d6b402 RH |
5180 | rtx reg; |
5181 | ||
5182 | function_arg_record_value_3 (bitpos, parms); | |
105b2084 JJ |
5183 | regno = SPARC_FP_ARG_FIRST + this_slotno * 2 |
5184 | + ((mode == SFmode || mode == SCmode) | |
5185 | && (bitpos & 32) != 0); | |
5186 | switch (mode) | |
5187 | { | |
5188 | case SCmode: mode = SFmode; break; | |
5189 | case DCmode: mode = DFmode; break; | |
5190 | case TCmode: mode = TFmode; break; | |
5191 | default: break; | |
5192 | } | |
5193 | reg = gen_rtx_REG (mode, regno); | |
48028e21 | 5194 | XVECEXP (parms->ret, 0, parms->stack + parms->nregs) |
254110c2 | 5195 | = gen_rtx_EXPR_LIST (VOIDmode, reg, |
82d6b402 RH |
5196 | GEN_INT (bitpos / BITS_PER_UNIT)); |
5197 | parms->nregs += 1; | |
105b2084 JJ |
5198 | if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) |
5199 | { | |
5200 | regno += GET_MODE_SIZE (mode) / 4; | |
5201 | reg = gen_rtx_REG (mode, regno); | |
48028e21 | 5202 | XVECEXP (parms->ret, 0, parms->stack + parms->nregs) |
105b2084 JJ |
5203 | = gen_rtx_EXPR_LIST (VOIDmode, reg, |
5204 | GEN_INT ((bitpos + GET_MODE_BITSIZE (mode)) | |
5205 | / BITS_PER_UNIT)); | |
5206 | parms->nregs += 1; | |
5207 | } | |
82d6b402 RH |
5208 | } |
5209 | else | |
5210 | { | |
5211 | if (parms->intoffset == -1) | |
5212 | parms->intoffset = bitpos; | |
5213 | } | |
5214 | } | |
5215 | } | |
5216 | } | |
5217 | ||
0020b823 | 5218 | /* Used by function_arg and function_value to implement the complex |
48028e21 EB |
5219 | conventions of the 64-bit ABI for passing and returning structures. |
5220 | Return an expression valid as a return value for the two macros | |
5221 | FUNCTION_ARG and FUNCTION_VALUE. | |
0020b823 | 5222 | |
48028e21 EB |
5223 | TYPE is the data type of the argument (as a tree). |
5224 | This is null for libcalls where that information may | |
5225 | not be available. | |
5226 | MODE is the argument's machine mode. | |
5227 | SLOTNO is the index number of the argument's slot in the parameter array. | |
5228 | NAMED is nonzero if this argument is a named parameter | |
5229 | (otherwise it is an extra parameter matching an ellipsis). | |
5230 | REGBASE is the regno of the base register for the parameter array. */ | |
5231 | ||
82d6b402 | 5232 | static rtx |
fc27d102 KG |
5233 | function_arg_record_value (tree type, enum machine_mode mode, |
5234 | int slotno, int named, int regbase) | |
82d6b402 RH |
5235 | { |
5236 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
5237 | struct function_arg_record_value_parms parms; | |
75131237 | 5238 | unsigned int nregs; |
82d6b402 RH |
5239 | |
5240 | parms.ret = NULL_RTX; | |
5241 | parms.slotno = slotno; | |
5242 | parms.named = named; | |
5243 | parms.regbase = regbase; | |
48028e21 | 5244 | parms.stack = 0; |
82d6b402 RH |
5245 | |
5246 | /* Compute how many registers we need. */ | |
5247 | parms.nregs = 0; | |
5248 | parms.intoffset = 0; | |
cde85594 | 5249 | function_arg_record_value_1 (type, 0, &parms, false); |
82d6b402 RH |
5250 | |
5251 | if (parms.intoffset != -1) | |
5252 | { | |
0020b823 | 5253 | unsigned int startbit, endbit; |
82d6b402 RH |
5254 | int intslots, this_slotno; |
5255 | ||
0020b823 RH |
5256 | startbit = parms.intoffset & -BITS_PER_WORD; |
5257 | endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
5258 | intslots = (endbit - startbit) / BITS_PER_WORD; | |
82d6b402 RH |
5259 | this_slotno = slotno + parms.intoffset / BITS_PER_WORD; |
5260 | ||
48028e21 EB |
5261 | if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) |
5262 | { | |
5263 | intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); | |
5264 | /* We need to pass this field on the stack. */ | |
5265 | parms.stack = 1; | |
5266 | } | |
82d6b402 RH |
5267 | |
5268 | parms.nregs += intslots; | |
5269 | } | |
5270 | nregs = parms.nregs; | |
5271 | ||
5272 | /* Allocate the vector and handle some annoying special cases. */ | |
5273 | if (nregs == 0) | |
5274 | { | |
5275 | /* ??? Empty structure has no value? Duh? */ | |
5276 | if (typesize <= 0) | |
5277 | { | |
5278 | /* Though there's nothing really to store, return a word register | |
5279 | anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL | |
5280 | leads to breakage due to the fact that there are zero bytes to | |
5281 | load. */ | |
1eac9f59 | 5282 | return gen_rtx_REG (mode, regbase); |
82d6b402 RH |
5283 | } |
5284 | else | |
5285 | { | |
5286 | /* ??? C++ has structures with no fields, and yet a size. Give up | |
5287 | for now and pass everything back in integer registers. */ | |
5288 | nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
5289 | } | |
5290 | if (nregs + slotno > SPARC_INT_ARG_MAX) | |
5291 | nregs = SPARC_INT_ARG_MAX - slotno; | |
5292 | } | |
5293 | if (nregs == 0) | |
9208e4b2 | 5294 | abort (); |
82d6b402 | 5295 | |
48028e21 EB |
5296 | parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs)); |
5297 | ||
5298 | /* If at least one field must be passed on the stack, generate | |
5299 | (parallel [(expr_list (nil) ...) ...]) so that all fields will | |
5300 | also be passed on the stack. We can't do much better because the | |
5301 | semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case | |
5302 | of structures for which the fields passed exclusively in registers | |
5303 | are not at the beginning of the structure. */ | |
5304 | if (parms.stack) | |
5305 | XVECEXP (parms.ret, 0, 0) | |
5306 | = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
82d6b402 RH |
5307 | |
5308 | /* Fill in the entries. */ | |
5309 | parms.nregs = 0; | |
5310 | parms.intoffset = 0; | |
cde85594 | 5311 | function_arg_record_value_2 (type, 0, &parms, false); |
82d6b402 RH |
5312 | function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); |
5313 | ||
5314 | if (parms.nregs != nregs) | |
5315 | abort (); | |
5316 | ||
5317 | return parms.ret; | |
5318 | } | |
5319 | ||
4fb4e4b8 DE |
5320 | /* Handle the FUNCTION_ARG macro. |
5321 | Determine where to put an argument to a function. | |
5322 | Value is zero to push the argument on the stack, | |
5323 | or a hard register in which to store the argument. | |
5324 | ||
5325 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
5326 | the preceding args and about the function being called. | |
5327 | MODE is the argument's machine mode. | |
5328 | TYPE is the data type of the argument (as a tree). | |
5329 | This is null for libcalls where that information may | |
5330 | not be available. | |
5331 | NAMED is nonzero if this argument is a named parameter | |
5332 | (otherwise it is an extra parameter matching an ellipsis). | |
5333 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ | |
61a55e8b DE |
5334 | |
5335 | rtx | |
fc27d102 KG |
5336 | function_arg (const struct sparc_args *cum, enum machine_mode mode, |
5337 | tree type, int named, int incoming_p) | |
61a55e8b | 5338 | { |
4fb4e4b8 DE |
5339 | int regbase = (incoming_p |
5340 | ? SPARC_INCOMING_INT_ARG_FIRST | |
5341 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
5342 | int slotno, regno, padding; | |
5343 | rtx reg; | |
5344 | ||
5345 | slotno = function_arg_slotno (cum, mode, type, named, incoming_p, | |
5346 | ®no, &padding); | |
5347 | ||
5348 | if (slotno == -1) | |
5349 | return 0; | |
5350 | ||
5351 | if (TARGET_ARCH32) | |
5352 | { | |
254110c2 | 5353 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
5354 | return reg; |
5355 | } | |
5356 | ||
5357 | /* v9 fp args in reg slots beyond the int reg slots get passed in regs | |
5358 | but also have the slot allocated for them. | |
5359 | If no prototype is in scope fp values in register slots get passed | |
5360 | in two places, either fp regs and int regs or fp regs and memory. */ | |
5361 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
5362 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5363 | && SPARC_FP_REG_P (regno)) | |
5364 | { | |
254110c2 | 5365 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
5366 | if (cum->prototype_p || cum->libcall_p) |
5367 | { | |
5368 | /* "* 2" because fp reg numbers are recorded in 4 byte | |
5369 | quantities. */ | |
82d6b402 | 5370 | #if 0 |
4fb4e4b8 DE |
5371 | /* ??? This will cause the value to be passed in the fp reg and |
5372 | in the stack. When a prototype exists we want to pass the | |
5373 | value in the reg but reserve space on the stack. That's an | |
956d6950 | 5374 | optimization, and is deferred [for a bit]. */ |
4fb4e4b8 | 5375 | if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) |
254110c2 | 5376 | return gen_rtx_PARALLEL (mode, |
4fb4e4b8 | 5377 | gen_rtvec (2, |
254110c2 | 5378 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 | 5379 | NULL_RTX, const0_rtx), |
254110c2 | 5380 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 DE |
5381 | reg, const0_rtx))); |
5382 | else | |
82d6b402 RH |
5383 | #else |
5384 | /* ??? It seems that passing back a register even when past | |
5385 | the area declared by REG_PARM_STACK_SPACE will allocate | |
5386 | space appropriately, and will not copy the data onto the | |
5387 | stack, exactly as we desire. | |
5388 | ||
5389 | This is due to locate_and_pad_parm being called in | |
5390 | expand_call whenever reg_parm_stack_space > 0, which | |
fae778eb | 5391 | while beneficial to our example here, would seem to be |
82d6b402 RH |
5392 | in error from what had been intended. Ho hum... -- r~ */ |
5393 | #endif | |
4fb4e4b8 DE |
5394 | return reg; |
5395 | } | |
5396 | else | |
5397 | { | |
82d6b402 RH |
5398 | rtx v0, v1; |
5399 | ||
4fb4e4b8 DE |
5400 | if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) |
5401 | { | |
82d6b402 RH |
5402 | int intreg; |
5403 | ||
5404 | /* On incoming, we don't need to know that the value | |
5405 | is passed in %f0 and %i0, and it confuses other parts | |
5406 | causing needless spillage even on the simplest cases. */ | |
5407 | if (incoming_p) | |
5408 | return reg; | |
5409 | ||
5410 | intreg = (SPARC_OUTGOING_INT_ARG_FIRST | |
5411 | + (regno - SPARC_FP_ARG_FIRST) / 2); | |
5412 | ||
5413 | v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
5414 | v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), | |
5415 | const0_rtx); | |
5416 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4fb4e4b8 DE |
5417 | } |
5418 | else | |
82d6b402 RH |
5419 | { |
5420 | v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
5421 | v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
5422 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
5423 | } | |
4fb4e4b8 DE |
5424 | } |
5425 | } | |
5426 | else if (type && TREE_CODE (type) == RECORD_TYPE) | |
5427 | { | |
5428 | /* Structures up to 16 bytes in size are passed in arg slots on the | |
5429 | stack and are promoted to registers where possible. */ | |
4fb4e4b8 DE |
5430 | |
5431 | if (int_size_in_bytes (type) > 16) | |
5432 | abort (); /* shouldn't get here */ | |
5433 | ||
1eac9f59 | 5434 | return function_arg_record_value (type, mode, slotno, named, regbase); |
4fb4e4b8 DE |
5435 | } |
5436 | else if (type && TREE_CODE (type) == UNION_TYPE) | |
5437 | { | |
5438 | enum machine_mode mode; | |
5439 | int bytes = int_size_in_bytes (type); | |
5440 | ||
5441 | if (bytes > 16) | |
5442 | abort (); | |
5443 | ||
5444 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
254110c2 | 5445 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 | 5446 | } |
a7acd911 | 5447 | else |
4fb4e4b8 DE |
5448 | { |
5449 | /* Scalar or complex int. */ | |
254110c2 | 5450 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
5451 | } |
5452 | ||
5453 | return reg; | |
5454 | } | |
a7acd911 | 5455 | |
4fb4e4b8 DE |
5456 | /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro. |
5457 | For an arg passed partly in registers and partly in memory, | |
5458 | this is the number of registers used. | |
5459 | For args passed entirely in registers or entirely in memory, zero. | |
61a55e8b | 5460 | |
4fb4e4b8 DE |
5461 | Any arg that starts in the first 6 regs but won't entirely fit in them |
5462 | needs partial registers on v8. On v9, structures with integer | |
5463 | values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp | |
5464 | values that begin in the last fp reg [where "last fp reg" varies with the | |
5465 | mode] will be split between that reg and memory. */ | |
61a55e8b | 5466 | |
4fb4e4b8 | 5467 | int |
fc27d102 KG |
5468 | function_arg_partial_nregs (const struct sparc_args *cum, |
5469 | enum machine_mode mode, tree type, int named) | |
4fb4e4b8 DE |
5470 | { |
5471 | int slotno, regno, padding; | |
61a55e8b | 5472 | |
4fb4e4b8 DE |
5473 | /* We pass 0 for incoming_p here, it doesn't matter. */ |
5474 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
5475 | ||
5476 | if (slotno == -1) | |
5477 | return 0; | |
5478 | ||
5479 | if (TARGET_ARCH32) | |
bf62bbf1 | 5480 | { |
4fb4e4b8 DE |
5481 | if ((slotno + (mode == BLKmode |
5482 | ? ROUND_ADVANCE (int_size_in_bytes (type)) | |
5483 | : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) | |
5484 | > NPARM_REGS (SImode)) | |
5485 | return NPARM_REGS (SImode) - slotno; | |
5486 | return 0; | |
5487 | } | |
5488 | else | |
5489 | { | |
5490 | if (type && AGGREGATE_TYPE_P (type)) | |
5491 | { | |
5492 | int size = int_size_in_bytes (type); | |
5493 | int align = TYPE_ALIGN (type); | |
bf62bbf1 | 5494 | |
4fb4e4b8 DE |
5495 | if (align == 16) |
5496 | slotno += slotno & 1; | |
5497 | if (size > 8 && size <= 16 | |
5498 | && slotno == SPARC_INT_ARG_MAX - 1) | |
5499 | return 1; | |
5500 | } | |
0a9e65f9 | 5501 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT |
4fb4e4b8 | 5502 | || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT |
c3427c7d | 5503 | && ! (TARGET_FPU && named))) |
4fb4e4b8 | 5504 | { |
0a9e65f9 EB |
5505 | /* The complex types are passed as packed types. */ |
5506 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
5507 | return 0; | |
5508 | ||
4fb4e4b8 DE |
5509 | if (GET_MODE_ALIGNMENT (mode) == 128) |
5510 | { | |
5511 | slotno += slotno & 1; | |
0a9e65f9 EB |
5512 | |
5513 | /* ??? The mode needs 3 slots? */ | |
4fb4e4b8 DE |
5514 | if (slotno == SPARC_INT_ARG_MAX - 2) |
5515 | return 1; | |
5516 | } | |
5517 | else | |
5518 | { | |
5519 | if (slotno == SPARC_INT_ARG_MAX - 1) | |
5520 | return 1; | |
5521 | } | |
5522 | } | |
5523 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5524 | { | |
5525 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
5526 | slotno += slotno & 1; | |
5527 | if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) | |
5528 | > SPARC_FP_ARG_MAX) | |
5529 | return 1; | |
5530 | } | |
5531 | return 0; | |
bf62bbf1 | 5532 | } |
4fb4e4b8 | 5533 | } |
61a55e8b | 5534 | |
4fb4e4b8 DE |
5535 | /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro. |
5536 | !v9: The SPARC ABI stipulates passing struct arguments (of any size) and | |
5537 | quad-precision floats by invisible reference. | |
82d6b402 | 5538 | v9: Aggregates greater than 16 bytes are passed by reference. |
4fb4e4b8 DE |
5539 | For Pascal, also pass arrays by reference. */ |
5540 | ||
5541 | int | |
fc27d102 KG |
5542 | function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED, |
5543 | enum machine_mode mode, tree type, | |
5544 | int named ATTRIBUTE_UNUSED) | |
4fb4e4b8 DE |
5545 | { |
5546 | if (TARGET_ARCH32) | |
eadceb59 | 5547 | { |
5e9defae | 5548 | return ((type && AGGREGATE_TYPE_P (type)) |
4fb4e4b8 DE |
5549 | || mode == TFmode || mode == TCmode); |
5550 | } | |
5551 | else | |
5552 | { | |
5553 | return ((type && TREE_CODE (type) == ARRAY_TYPE) | |
69494148 EB |
5554 | /* Consider complex values as aggregates, so care |
5555 | for CTImode and TCmode. */ | |
82d6b402 | 5556 | || GET_MODE_SIZE (mode) > 16 |
f36dea3c RH |
5557 | || (type |
5558 | && AGGREGATE_TYPE_P (type) | |
5559 | && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)); | |
4fb4e4b8 DE |
5560 | } |
5561 | } | |
5562 | ||
5563 | /* Handle the FUNCTION_ARG_ADVANCE macro. | |
5564 | Update the data in CUM to advance over an argument | |
5565 | of mode MODE and data type TYPE. | |
5566 | TYPE is null for libcalls where that information may not be available. */ | |
5567 | ||
5568 | void | |
fc27d102 KG |
5569 | function_arg_advance (struct sparc_args *cum, enum machine_mode mode, |
5570 | tree type, int named) | |
4fb4e4b8 DE |
5571 | { |
5572 | int slotno, regno, padding; | |
5573 | ||
5574 | /* We pass 0 for incoming_p here, it doesn't matter. */ | |
5575 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
5576 | ||
5577 | /* If register required leading padding, add it. */ | |
5578 | if (slotno != -1) | |
5579 | cum->words += padding; | |
eadceb59 | 5580 | |
4fb4e4b8 DE |
5581 | if (TARGET_ARCH32) |
5582 | { | |
5583 | cum->words += (mode != BLKmode | |
5584 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
5585 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
5586 | } | |
5587 | else | |
5588 | { | |
5589 | if (type && AGGREGATE_TYPE_P (type)) | |
5590 | { | |
5591 | int size = int_size_in_bytes (type); | |
5592 | ||
5593 | if (size <= 8) | |
5594 | ++cum->words; | |
5595 | else if (size <= 16) | |
5596 | cum->words += 2; | |
5597 | else /* passed by reference */ | |
5598 | ++cum->words; | |
5599 | } | |
4fb4e4b8 DE |
5600 | else |
5601 | { | |
5602 | cum->words += (mode != BLKmode | |
5603 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
5604 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
5605 | } | |
eadceb59 | 5606 | } |
4fb4e4b8 | 5607 | } |
eadceb59 | 5608 | |
4fb4e4b8 DE |
5609 | /* Handle the FUNCTION_ARG_PADDING macro. |
5610 | For the 64 bit ABI structs are always stored left shifted in their | |
5611 | argument slot. */ | |
5612 | ||
5613 | enum direction | |
fc27d102 | 5614 | function_arg_padding (enum machine_mode mode, tree type) |
4fb4e4b8 | 5615 | { |
c85f7c16 JL |
5616 | if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) |
5617 | return upward; | |
61a55e8b | 5618 | |
d3704c46 KH |
5619 | /* Fall back to the default. */ |
5620 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
61a55e8b | 5621 | } |
82d6b402 RH |
5622 | |
5623 | /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. | |
5624 | For v9, function return values are subject to the same rules as arguments, | |
5625 | except that up to 32-bytes may be returned in registers. */ | |
5626 | ||
5627 | rtx | |
fc27d102 | 5628 | function_value (tree type, enum machine_mode mode, int incoming_p) |
82d6b402 RH |
5629 | { |
5630 | int regno; | |
5631 | int regbase = (incoming_p | |
5632 | ? SPARC_OUTGOING_INT_ARG_FIRST | |
5633 | : SPARC_INCOMING_INT_ARG_FIRST); | |
5634 | ||
5635 | if (TARGET_ARCH64 && type) | |
5636 | { | |
5637 | if (TREE_CODE (type) == RECORD_TYPE) | |
5638 | { | |
5639 | /* Structures up to 32 bytes in size are passed in registers, | |
5640 | promoted to fp registers where possible. */ | |
5641 | ||
5642 | if (int_size_in_bytes (type) > 32) | |
5643 | abort (); /* shouldn't get here */ | |
5644 | ||
1eac9f59 | 5645 | return function_arg_record_value (type, mode, 0, 1, regbase); |
82d6b402 | 5646 | } |
8a7199ad | 5647 | else if (AGGREGATE_TYPE_P (type)) |
82d6b402 | 5648 | { |
8a7199ad RK |
5649 | /* All other aggregate types are passed in an integer register |
5650 | in a mode corresponding to the size of the type. */ | |
5651 | HOST_WIDE_INT bytes = int_size_in_bytes (type); | |
82d6b402 RH |
5652 | |
5653 | if (bytes > 32) | |
5654 | abort (); | |
5655 | ||
5656 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
5657 | } | |
5658 | } | |
3c6088d2 JJ |
5659 | |
5660 | if (TARGET_ARCH64 | |
5661 | && GET_MODE_CLASS (mode) == MODE_INT | |
5662 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
8a7199ad | 5663 | && type && ! AGGREGATE_TYPE_P (type)) |
3c6088d2 | 5664 | mode = DImode; |
82d6b402 RH |
5665 | |
5666 | if (incoming_p) | |
5667 | regno = BASE_RETURN_VALUE_REG (mode); | |
5668 | else | |
5669 | regno = BASE_OUTGOING_VALUE_REG (mode); | |
5670 | ||
254110c2 | 5671 | return gen_rtx_REG (mode, regno); |
82d6b402 RH |
5672 | } |
5673 | ||
648d2ffc RH |
5674 | /* Do what is necessary for `va_start'. We look at the current function |
5675 | to determine if stdarg or varargs is used and return the address of | |
5676 | the first unnamed parameter. */ | |
3ea1fdd3 JW |
5677 | |
5678 | rtx | |
fc27d102 | 5679 | sparc_builtin_saveregs (void) |
3ea1fdd3 | 5680 | { |
4fb4e4b8 | 5681 | int first_reg = current_function_args_info.words; |
3ea1fdd3 JW |
5682 | rtx address; |
5683 | int regno; | |
5684 | ||
4fb4e4b8 | 5685 | for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++) |
254110c2 | 5686 | emit_move_insn (gen_rtx_MEM (word_mode, |
8ac61af7 RK |
5687 | gen_rtx_PLUS (Pmode, |
5688 | frame_pointer_rtx, | |
563c12b0 | 5689 | GEN_INT (FIRST_PARM_OFFSET (0) |
8ac61af7 RK |
5690 | + (UNITS_PER_WORD |
5691 | * regno)))), | |
254110c2 | 5692 | gen_rtx_REG (word_mode, |
8ac61af7 | 5693 | BASE_INCOMING_ARG_REG (word_mode) + regno)); |
3ea1fdd3 | 5694 | |
254110c2 | 5695 | address = gen_rtx_PLUS (Pmode, |
8ac61af7 | 5696 | frame_pointer_rtx, |
563c12b0 | 5697 | GEN_INT (FIRST_PARM_OFFSET (0) |
8ac61af7 | 5698 | + UNITS_PER_WORD * first_reg)); |
3ea1fdd3 JW |
5699 | |
5700 | return address; | |
5701 | } | |
a8b2c8a1 RH |
5702 | |
5703 | /* Implement `va_start' for varargs and stdarg. */ | |
5704 | ||
5705 | void | |
fc27d102 | 5706 | sparc_va_start (tree valist, rtx nextarg) |
a8b2c8a1 RH |
5707 | { |
5708 | nextarg = expand_builtin_saveregs (); | |
e5faf155 | 5709 | std_expand_builtin_va_start (valist, nextarg); |
a8b2c8a1 RH |
5710 | } |
5711 | ||
5712 | /* Implement `va_arg'. */ | |
5713 | ||
5714 | rtx | |
fc27d102 | 5715 | sparc_va_arg (tree valist, tree type) |
a8b2c8a1 RH |
5716 | { |
5717 | HOST_WIDE_INT size, rsize, align; | |
da09e317 | 5718 | tree addr, incr; |
a8b2c8a1 RH |
5719 | rtx addr_rtx; |
5720 | int indirect = 0; | |
5721 | ||
5722 | /* Round up sizeof(type) to a word. */ | |
5723 | size = int_size_in_bytes (type); | |
5724 | rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; | |
5725 | align = 0; | |
5726 | ||
5727 | if (TARGET_ARCH64) | |
5728 | { | |
fbd039b2 | 5729 | if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) |
a8b2c8a1 RH |
5730 | align = 2 * UNITS_PER_WORD; |
5731 | ||
69494148 EB |
5732 | /* Consider complex values as aggregates, so care |
5733 | for CTImode and TCmode. */ | |
5734 | if ((unsigned HOST_WIDE_INT) size > 16) | |
a8b2c8a1 | 5735 | { |
69494148 EB |
5736 | indirect = 1; |
5737 | size = rsize = UNITS_PER_WORD; | |
5738 | align = 0; | |
5739 | } | |
5740 | else if (AGGREGATE_TYPE_P (type)) | |
5741 | { | |
5742 | /* SPARC-V9 ABI states that structures up to 16 bytes in size | |
5743 | are given whole slots as needed. */ | |
5744 | if (size == 0) | |
014c0998 | 5745 | size = rsize = UNITS_PER_WORD; |
f34e52f7 JJ |
5746 | else |
5747 | size = rsize; | |
a8b2c8a1 RH |
5748 | } |
5749 | } | |
5750 | else | |
5751 | { | |
5752 | if (AGGREGATE_TYPE_P (type) | |
5753 | || TYPE_MODE (type) == TFmode | |
5754 | || TYPE_MODE (type) == TCmode) | |
5755 | { | |
5756 | indirect = 1; | |
5757 | size = rsize = UNITS_PER_WORD; | |
5758 | } | |
a8b2c8a1 RH |
5759 | } |
5760 | ||
5761 | incr = valist; | |
5762 | if (align) | |
5763 | { | |
5764 | incr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
5765 | build_int_2 (align - 1, 0))); | |
5766 | incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr, | |
5767 | build_int_2 (-align, -1))); | |
5768 | } | |
5769 | ||
5770 | addr = incr = save_expr (incr); | |
5771 | if (BYTES_BIG_ENDIAN && size < rsize) | |
5772 | { | |
5773 | addr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
5774 | build_int_2 (rsize - size, 0))); | |
5775 | } | |
5776 | incr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
5777 | build_int_2 (rsize, 0))); | |
5778 | ||
5779 | incr = build (MODIFY_EXPR, ptr_type_node, valist, incr); | |
5780 | TREE_SIDE_EFFECTS (incr) = 1; | |
5781 | expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5782 | ||
5783 | addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); | |
5784 | ||
9a0662b4 GK |
5785 | /* If the address isn't aligned properly for the type, |
5786 | we may need to copy to a temporary. | |
5787 | FIXME: This is inefficient. Usually we can do this | |
5788 | in registers. */ | |
5789 | if (align == 0 | |
5790 | && TYPE_ALIGN (type) > BITS_PER_WORD | |
5791 | && !indirect) | |
5792 | { | |
5793 | /* FIXME: We really need to specify that the temporary is live | |
5794 | for the whole function because expand_builtin_va_arg wants | |
5795 | the alias set to be get_varargs_alias_set (), but in this | |
5796 | case the alias set is that for TYPE and if the memory gets | |
5797 | reused it will be reused with alias set TYPE. */ | |
5798 | rtx tmp = assign_temp (type, 0, 1, 0); | |
5799 | rtx dest_addr; | |
5800 | ||
5801 | addr_rtx = force_reg (Pmode, addr_rtx); | |
5802 | addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx); | |
ba4828e0 | 5803 | set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); |
8ac61af7 | 5804 | set_mem_align (addr_rtx, BITS_PER_WORD); |
9a0662b4 GK |
5805 | tmp = shallow_copy_rtx (tmp); |
5806 | PUT_MODE (tmp, BLKmode); | |
ba4828e0 | 5807 | set_mem_alias_set (tmp, 0); |
9a0662b4 | 5808 | |
44bb111a RH |
5809 | dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize), |
5810 | BLOCK_OP_NORMAL); | |
9a0662b4 GK |
5811 | if (dest_addr != NULL_RTX) |
5812 | addr_rtx = dest_addr; | |
5813 | else | |
5814 | addr_rtx = XCEXP (tmp, 0, MEM); | |
5815 | } | |
5816 | ||
a8b2c8a1 RH |
5817 | if (indirect) |
5818 | { | |
5819 | addr_rtx = force_reg (Pmode, addr_rtx); | |
5820 | addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 5821 | set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); |
a8b2c8a1 RH |
5822 | } |
5823 | ||
5824 | return addr_rtx; | |
5825 | } | |
ab835497 RK |
5826 | \f |
5827 | /* Return the string to output a conditional branch to LABEL, which is | |
c4ce6853 DE |
5828 | the operand number of the label. OP is the conditional expression. |
5829 | XEXP (OP, 0) is assumed to be a condition code register (integer or | |
5830 | floating point) and its mode specifies what kind of comparison we made. | |
61a55e8b | 5831 | |
5e7a8ee0 | 5832 | REVERSED is nonzero if we should reverse the sense of the comparison. |
ab835497 | 5833 | |
5e7a8ee0 | 5834 | ANNUL is nonzero if we should generate an annulling branch. |
ab835497 | 5835 | |
5e7a8ee0 | 5836 | NOOP is nonzero if we have to follow this branch by a noop. |
c6b0465b JC |
5837 | |
5838 | INSN, if set, is the insn. */ | |
ab835497 RK |
5839 | |
5840 | char * | |
fc27d102 KG |
5841 | output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, |
5842 | int noop, rtx insn) | |
ab835497 | 5843 | { |
0b82d204 | 5844 | static char string[50]; |
ab835497 | 5845 | enum rtx_code code = GET_CODE (op); |
c4ce6853 DE |
5846 | rtx cc_reg = XEXP (op, 0); |
5847 | enum machine_mode mode = GET_MODE (cc_reg); | |
0b82d204 JJ |
5848 | const char *labelno, *branch; |
5849 | int spaces = 8, far; | |
5850 | char *p; | |
5851 | ||
5852 | /* v9 branches are limited to +-1MB. If it is too far away, | |
5853 | change | |
5854 | ||
5855 | bne,pt %xcc, .LC30 | |
5856 | ||
5857 | to | |
5858 | ||
5859 | be,pn %xcc, .+12 | |
5860 | nop | |
5861 | ba .LC30 | |
5862 | ||
5863 | and | |
5864 | ||
5865 | fbne,a,pn %fcc2, .LC29 | |
61a55e8b | 5866 | |
0b82d204 JJ |
5867 | to |
5868 | ||
5869 | fbe,pt %fcc2, .+16 | |
5870 | nop | |
5871 | ba .LC29 */ | |
5872 | ||
5873 | far = get_attr_length (insn) >= 3; | |
5874 | if (reversed ^ far) | |
ab835497 | 5875 | { |
e267e177 RH |
5876 | /* Reversal of FP compares takes care -- an ordered compare |
5877 | becomes an unordered compare and vice versa. */ | |
4d449554 | 5878 | if (mode == CCFPmode || mode == CCFPEmode) |
7913f3d0 | 5879 | code = reverse_condition_maybe_unordered (code); |
ab835497 | 5880 | else |
e267e177 | 5881 | code = reverse_condition (code); |
ab835497 RK |
5882 | } |
5883 | ||
e267e177 RH |
5884 | /* Start by writing the branch condition. */ |
5885 | if (mode == CCFPmode || mode == CCFPEmode) | |
5850dc00 RH |
5886 | { |
5887 | switch (code) | |
5888 | { | |
5889 | case NE: | |
5890 | branch = "fbne"; | |
5891 | break; | |
5892 | case EQ: | |
5893 | branch = "fbe"; | |
5894 | break; | |
5895 | case GE: | |
5896 | branch = "fbge"; | |
5897 | break; | |
5898 | case GT: | |
5899 | branch = "fbg"; | |
5900 | break; | |
5901 | case LE: | |
5902 | branch = "fble"; | |
5903 | break; | |
5904 | case LT: | |
5905 | branch = "fbl"; | |
5906 | break; | |
5907 | case UNORDERED: | |
5908 | branch = "fbu"; | |
5909 | break; | |
5910 | case ORDERED: | |
5911 | branch = "fbo"; | |
5912 | break; | |
5913 | case UNGT: | |
5914 | branch = "fbug"; | |
5915 | break; | |
5916 | case UNLT: | |
5917 | branch = "fbul"; | |
5918 | break; | |
5919 | case UNEQ: | |
5920 | branch = "fbue"; | |
5921 | break; | |
5922 | case UNGE: | |
5923 | branch = "fbuge"; | |
5924 | break; | |
5925 | case UNLE: | |
5926 | branch = "fbule"; | |
5927 | break; | |
5928 | case LTGT: | |
5929 | branch = "fblg"; | |
5930 | break; | |
5931 | ||
5932 | default: | |
5933 | abort (); | |
5934 | } | |
5935 | ||
5936 | /* ??? !v9: FP branches cannot be preceded by another floating point | |
5937 | insn. Because there is currently no concept of pre-delay slots, | |
5938 | we can fix this only by always emitting a nop before a floating | |
5939 | point branch. */ | |
5940 | ||
5941 | string[0] = '\0'; | |
5942 | if (! TARGET_V9) | |
5943 | strcpy (string, "nop\n\t"); | |
5944 | strcat (string, branch); | |
5945 | } | |
e267e177 | 5946 | else |
5850dc00 RH |
5947 | { |
5948 | switch (code) | |
5949 | { | |
5950 | case NE: | |
5951 | branch = "bne"; | |
5952 | break; | |
5953 | case EQ: | |
5954 | branch = "be"; | |
5955 | break; | |
5956 | case GE: | |
0b82d204 | 5957 | if (mode == CC_NOOVmode || mode == CCX_NOOVmode) |
5850dc00 RH |
5958 | branch = "bpos"; |
5959 | else | |
5960 | branch = "bge"; | |
5961 | break; | |
5962 | case GT: | |
5963 | branch = "bg"; | |
5964 | break; | |
5965 | case LE: | |
5966 | branch = "ble"; | |
5967 | break; | |
5968 | case LT: | |
0b82d204 | 5969 | if (mode == CC_NOOVmode || mode == CCX_NOOVmode) |
5850dc00 RH |
5970 | branch = "bneg"; |
5971 | else | |
5972 | branch = "bl"; | |
5973 | break; | |
5974 | case GEU: | |
5975 | branch = "bgeu"; | |
5976 | break; | |
5977 | case GTU: | |
5978 | branch = "bgu"; | |
5979 | break; | |
5980 | case LEU: | |
5981 | branch = "bleu"; | |
5982 | break; | |
5983 | case LTU: | |
5984 | branch = "blu"; | |
5985 | break; | |
5986 | ||
5987 | default: | |
5988 | abort (); | |
5989 | } | |
5990 | strcpy (string, branch); | |
5991 | } | |
e267e177 | 5992 | spaces -= strlen (branch); |
0b82d204 | 5993 | p = strchr (string, '\0'); |
e267e177 | 5994 | |
ab835497 | 5995 | /* Now add the annulling, the label, and a possible noop. */ |
0b82d204 | 5996 | if (annul && ! far) |
e0d80184 | 5997 | { |
0b82d204 JJ |
5998 | strcpy (p, ",a"); |
5999 | p += 2; | |
e0d80184 DM |
6000 | spaces -= 2; |
6001 | } | |
ab835497 | 6002 | |
61a55e8b | 6003 | if (! TARGET_V9) |
0b82d204 | 6004 | labelno = ""; |
61a55e8b DE |
6005 | else |
6006 | { | |
c6b0465b | 6007 | rtx note; |
0b82d204 | 6008 | int v8 = 0; |
c6b0465b | 6009 | |
0b82d204 | 6010 | if (! far && insn && INSN_ADDRESSES_SET_P ()) |
e0d80184 | 6011 | { |
0b82d204 JJ |
6012 | int delta = (INSN_ADDRESSES (INSN_UID (dest)) |
6013 | - INSN_ADDRESSES (INSN_UID (insn))); | |
6014 | /* Leave some instructions for "slop". */ | |
6015 | if (delta < -260000 || delta >= 260000) | |
6016 | v8 = 1; | |
e0d80184 | 6017 | } |
c6b0465b | 6018 | |
61a55e8b DE |
6019 | if (mode == CCFPmode || mode == CCFPEmode) |
6020 | { | |
0b82d204 | 6021 | static char v9_fcc_labelno[] = "%%fccX, "; |
61a55e8b | 6022 | /* Set the char indicating the number of the fcc reg to use. */ |
0b82d204 JJ |
6023 | v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; |
6024 | labelno = v9_fcc_labelno; | |
6025 | if (v8) | |
6026 | { | |
6027 | if (REGNO (cc_reg) == SPARC_FCC_REG) | |
6028 | labelno = ""; | |
6029 | else | |
6030 | abort (); | |
6031 | } | |
61a55e8b DE |
6032 | } |
6033 | else if (mode == CCXmode || mode == CCX_NOOVmode) | |
0b82d204 JJ |
6034 | { |
6035 | labelno = "%%xcc, "; | |
6036 | if (v8) | |
6037 | abort (); | |
6038 | } | |
61a55e8b | 6039 | else |
0b82d204 JJ |
6040 | { |
6041 | labelno = "%%icc, "; | |
6042 | if (v8) | |
6043 | labelno = ""; | |
6044 | } | |
6045 | ||
4f31cce8 | 6046 | if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) |
0b82d204 JJ |
6047 | { |
6048 | strcpy (p, | |
4f31cce8 | 6049 | ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) |
0b82d204 JJ |
6050 | ? ",pt" : ",pn"); |
6051 | p += 3; | |
6052 | spaces -= 3; | |
6053 | } | |
61a55e8b | 6054 | } |
e0d80184 | 6055 | if (spaces > 0) |
0b82d204 | 6056 | *p++ = '\t'; |
e0d80184 | 6057 | else |
0b82d204 JJ |
6058 | *p++ = ' '; |
6059 | strcpy (p, labelno); | |
6060 | p = strchr (p, '\0'); | |
6061 | if (far) | |
6062 | { | |
6063 | strcpy (p, ".+12\n\tnop\n\tb\t"); | |
6064 | if (annul || noop) | |
6065 | p[3] = '6'; | |
6066 | p += 13; | |
6067 | } | |
6068 | *p++ = '%'; | |
6069 | *p++ = 'l'; | |
6070 | /* Set the char indicating the number of the operand containing the | |
6071 | label_ref. */ | |
6072 | *p++ = label + '0'; | |
6073 | *p = '\0'; | |
61a55e8b | 6074 | if (noop) |
0b82d204 | 6075 | strcpy (p, "\n\tnop"); |
61a55e8b DE |
6076 | |
6077 | return string; | |
6078 | } | |
6079 | ||
47ac041c JJ |
6080 | /* Emit a library call comparison between floating point X and Y. |
6081 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). | |
6082 | TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode | |
6083 | values as arguments instead of the TFmode registers themselves, | |
6084 | that's why we cannot call emit_float_lib_cmp. */ | |
6085 | void | |
fc27d102 | 6086 | sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison) |
47ac041c | 6087 | { |
e77d72cb | 6088 | const char *qpfunc; |
5c5c34a4 JJ |
6089 | rtx slot0, slot1, result, tem, tem2; |
6090 | enum machine_mode mode; | |
47ac041c JJ |
6091 | |
6092 | switch (comparison) | |
6093 | { | |
6094 | case EQ: | |
5c5c34a4 | 6095 | qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq"; |
47ac041c JJ |
6096 | break; |
6097 | ||
6098 | case NE: | |
5c5c34a4 | 6099 | qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne"; |
47ac041c JJ |
6100 | break; |
6101 | ||
6102 | case GT: | |
5c5c34a4 | 6103 | qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt"; |
47ac041c JJ |
6104 | break; |
6105 | ||
6106 | case GE: | |
5c5c34a4 | 6107 | qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge"; |
47ac041c JJ |
6108 | break; |
6109 | ||
6110 | case LT: | |
5c5c34a4 | 6111 | qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt"; |
47ac041c JJ |
6112 | break; |
6113 | ||
6114 | case LE: | |
5c5c34a4 JJ |
6115 | qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle"; |
6116 | break; | |
6117 | ||
6118 | case ORDERED: | |
6119 | case UNORDERED: | |
6120 | case UNGT: | |
6121 | case UNLT: | |
6122 | case UNEQ: | |
6123 | case UNGE: | |
6124 | case UNLE: | |
6125 | case LTGT: | |
6126 | qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp"; | |
47ac041c JJ |
6127 | break; |
6128 | ||
6129 | default: | |
6130 | abort(); | |
6131 | break; | |
6132 | } | |
6133 | ||
5c5c34a4 | 6134 | if (TARGET_ARCH64) |
47ac041c | 6135 | { |
5c5c34a4 JJ |
6136 | if (GET_CODE (x) != MEM) |
6137 | { | |
6138 | slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); | |
6139 | emit_insn (gen_rtx_SET (VOIDmode, slot0, x)); | |
6140 | } | |
6141 | else | |
6142 | slot0 = x; | |
6143 | ||
6144 | if (GET_CODE (y) != MEM) | |
6145 | { | |
6146 | slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); | |
6147 | emit_insn (gen_rtx_SET (VOIDmode, slot1, y)); | |
6148 | } | |
6149 | else | |
6150 | slot1 = y; | |
47ac041c | 6151 | |
eb29ddb6 | 6152 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, |
5c5c34a4 JJ |
6153 | DImode, 2, |
6154 | XEXP (slot0, 0), Pmode, | |
6155 | XEXP (slot1, 0), Pmode); | |
6156 | ||
6157 | mode = DImode; | |
6158 | } | |
6159 | else | |
47ac041c | 6160 | { |
eb29ddb6 | 6161 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, |
5c5c34a4 JJ |
6162 | SImode, 2, |
6163 | x, TFmode, y, TFmode); | |
6164 | ||
6165 | mode = SImode; | |
47ac041c JJ |
6166 | } |
6167 | ||
47ac041c JJ |
6168 | |
6169 | /* Immediately move the result of the libcall into a pseudo | |
6170 | register so reload doesn't clobber the value if it needs | |
6171 | the return register for a spill reg. */ | |
5c5c34a4 JJ |
6172 | result = gen_reg_rtx (mode); |
6173 | emit_move_insn (result, hard_libcall_value (mode)); | |
47ac041c | 6174 | |
5c5c34a4 JJ |
6175 | switch (comparison) |
6176 | { | |
6177 | default: | |
3b2d1507 | 6178 | emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
6179 | break; |
6180 | case ORDERED: | |
6181 | case UNORDERED: | |
3b2d1507 AT |
6182 | emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE, |
6183 | NULL_RTX, mode, 0); | |
5c5c34a4 JJ |
6184 | break; |
6185 | case UNGT: | |
6186 | case UNGE: | |
6187 | emit_cmp_insn (result, const1_rtx, | |
3b2d1507 | 6188 | comparison == UNGT ? GT : NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
6189 | break; |
6190 | case UNLE: | |
3b2d1507 | 6191 | emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
6192 | break; |
6193 | case UNLT: | |
6194 | tem = gen_reg_rtx (mode); | |
6195 | if (TARGET_ARCH32) | |
6196 | emit_insn (gen_andsi3 (tem, result, const1_rtx)); | |
6197 | else | |
6198 | emit_insn (gen_anddi3 (tem, result, const1_rtx)); | |
3b2d1507 | 6199 | emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
6200 | break; |
6201 | case UNEQ: | |
6202 | case LTGT: | |
6203 | tem = gen_reg_rtx (mode); | |
6204 | if (TARGET_ARCH32) | |
6205 | emit_insn (gen_addsi3 (tem, result, const1_rtx)); | |
6206 | else | |
6207 | emit_insn (gen_adddi3 (tem, result, const1_rtx)); | |
6208 | tem2 = gen_reg_rtx (mode); | |
6209 | if (TARGET_ARCH32) | |
6210 | emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); | |
6211 | else | |
6212 | emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); | |
3b2d1507 AT |
6213 | emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE, |
6214 | NULL_RTX, mode, 0); | |
5c5c34a4 JJ |
6215 | break; |
6216 | } | |
47ac041c | 6217 | } |
5c5c34a4 | 6218 | |
d88e57d1 RH |
6219 | /* Generate an unsigned DImode to FP conversion. This is the same code |
6220 | optabs would emit if we didn't have TFmode patterns. */ | |
6221 | ||
6222 | void | |
fc27d102 | 6223 | sparc_emit_floatunsdi (rtx *operands) |
d88e57d1 RH |
6224 | { |
6225 | rtx neglab, donelab, i0, i1, f0, in, out; | |
6226 | enum machine_mode mode; | |
6227 | ||
6228 | out = operands[0]; | |
6229 | in = force_reg (DImode, operands[1]); | |
6230 | mode = GET_MODE (out); | |
6231 | neglab = gen_label_rtx (); | |
6232 | donelab = gen_label_rtx (); | |
6233 | i0 = gen_reg_rtx (DImode); | |
6234 | i1 = gen_reg_rtx (DImode); | |
6235 | f0 = gen_reg_rtx (mode); | |
6236 | ||
6237 | emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); | |
6238 | ||
6239 | emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in))); | |
6240 | emit_jump_insn (gen_jump (donelab)); | |
6241 | emit_barrier (); | |
6242 | ||
6243 | emit_label (neglab); | |
6244 | ||
6245 | emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); | |
6246 | emit_insn (gen_anddi3 (i1, in, const1_rtx)); | |
6247 | emit_insn (gen_iordi3 (i0, i0, i1)); | |
6248 | emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0))); | |
6249 | emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0))); | |
6250 | ||
6251 | emit_label (donelab); | |
6252 | } | |
6253 | ||
61a55e8b DE |
6254 | /* Return the string to output a conditional branch to LABEL, testing |
6255 | register REG. LABEL is the operand number of the label; REG is the | |
6256 | operand number of the reg. OP is the conditional expression. The mode | |
6257 | of REG says what kind of comparison we made. | |
6258 | ||
5e7a8ee0 | 6259 | REVERSED is nonzero if we should reverse the sense of the comparison. |
61a55e8b | 6260 | |
5e7a8ee0 | 6261 | ANNUL is nonzero if we should generate an annulling branch. |
61a55e8b | 6262 | |
5e7a8ee0 | 6263 | NOOP is nonzero if we have to follow this branch by a noop. */ |
61a55e8b DE |
6264 | |
6265 | char * | |
fc27d102 KG |
6266 | output_v9branch (rtx op, rtx dest, int reg, int label, int reversed, |
6267 | int annul, int noop, rtx insn) | |
61a55e8b | 6268 | { |
0b82d204 | 6269 | static char string[50]; |
61a55e8b DE |
6270 | enum rtx_code code = GET_CODE (op); |
6271 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
e0d80184 | 6272 | rtx note; |
0b82d204 JJ |
6273 | int far; |
6274 | char *p; | |
6275 | ||
6276 | /* branch on register are limited to +-128KB. If it is too far away, | |
6277 | change | |
6278 | ||
6279 | brnz,pt %g1, .LC30 | |
6280 | ||
6281 | to | |
6282 | ||
6283 | brz,pn %g1, .+12 | |
6284 | nop | |
6285 | ba,pt %xcc, .LC30 | |
6286 | ||
6287 | and | |
6288 | ||
6289 | brgez,a,pn %o1, .LC29 | |
6290 | ||
6291 | to | |
6292 | ||
6293 | brlz,pt %o1, .+16 | |
6294 | nop | |
6295 | ba,pt %xcc, .LC29 */ | |
6296 | ||
6297 | far = get_attr_length (insn) >= 3; | |
61a55e8b DE |
6298 | |
6299 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
0b82d204 JJ |
6300 | if (reversed ^ far) |
6301 | code = reverse_condition (code); | |
61a55e8b DE |
6302 | |
6303 | /* Only 64 bit versions of these instructions exist. */ | |
6304 | if (mode != DImode) | |
6305 | abort (); | |
6306 | ||
6307 | /* Start by writing the branch condition. */ | |
6308 | ||
6309 | switch (code) | |
6310 | { | |
6311 | case NE: | |
6312 | strcpy (string, "brnz"); | |
6313 | break; | |
6314 | ||
6315 | case EQ: | |
6316 | strcpy (string, "brz"); | |
6317 | break; | |
6318 | ||
6319 | case GE: | |
6320 | strcpy (string, "brgez"); | |
6321 | break; | |
6322 | ||
6323 | case LT: | |
6324 | strcpy (string, "brlz"); | |
6325 | break; | |
6326 | ||
6327 | case LE: | |
6328 | strcpy (string, "brlez"); | |
6329 | break; | |
6330 | ||
6331 | case GT: | |
6332 | strcpy (string, "brgz"); | |
6333 | break; | |
6334 | ||
6335 | default: | |
6336 | abort (); | |
6337 | } | |
6338 | ||
0b82d204 JJ |
6339 | p = strchr (string, '\0'); |
6340 | ||
61a55e8b | 6341 | /* Now add the annulling, reg, label, and nop. */ |
0b82d204 | 6342 | if (annul && ! far) |
e0d80184 | 6343 | { |
0b82d204 JJ |
6344 | strcpy (p, ",a"); |
6345 | p += 2; | |
e0d80184 | 6346 | } |
61a55e8b | 6347 | |
4f31cce8 | 6348 | if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) |
e0d80184 | 6349 | { |
0b82d204 | 6350 | strcpy (p, |
4f31cce8 | 6351 | ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) |
0b82d204 JJ |
6352 | ? ",pt" : ",pn"); |
6353 | p += 3; | |
e0d80184 | 6354 | } |
61a55e8b | 6355 | |
0b82d204 JJ |
6356 | *p = p < string + 8 ? '\t' : ' '; |
6357 | p++; | |
6358 | *p++ = '%'; | |
6359 | *p++ = '0' + reg; | |
6360 | *p++ = ','; | |
6361 | *p++ = ' '; | |
6362 | if (far) | |
6363 | { | |
6364 | int veryfar = 1, delta; | |
6365 | ||
6366 | if (INSN_ADDRESSES_SET_P ()) | |
6367 | { | |
6368 | delta = (INSN_ADDRESSES (INSN_UID (dest)) | |
6369 | - INSN_ADDRESSES (INSN_UID (insn))); | |
6370 | /* Leave some instructions for "slop". */ | |
6371 | if (delta >= -260000 && delta < 260000) | |
6372 | veryfar = 0; | |
6373 | } | |
6374 | ||
6375 | strcpy (p, ".+12\n\tnop\n\t"); | |
6376 | if (annul || noop) | |
6377 | p[3] = '6'; | |
6378 | p += 11; | |
6379 | if (veryfar) | |
6380 | { | |
6381 | strcpy (p, "b\t"); | |
6382 | p += 2; | |
6383 | } | |
6384 | else | |
6385 | { | |
6386 | strcpy (p, "ba,pt\t%%xcc, "); | |
6387 | p += 13; | |
6388 | } | |
6389 | } | |
6390 | *p++ = '%'; | |
6391 | *p++ = 'l'; | |
6392 | *p++ = '0' + label; | |
6393 | *p = '\0'; | |
ab835497 RK |
6394 | |
6395 | if (noop) | |
0b82d204 | 6396 | strcpy (p, "\n\tnop"); |
ab835497 RK |
6397 | |
6398 | return string; | |
6399 | } | |
6400 | ||
e48addee JJ |
6401 | /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. |
6402 | Such instructions cannot be used in the delay slot of return insn on v9. | |
6403 | If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. | |
6404 | */ | |
284d86e9 | 6405 | |
e48addee | 6406 | static int |
fc27d102 | 6407 | epilogue_renumber (register rtx *where, int test) |
284d86e9 | 6408 | { |
e48addee JJ |
6409 | register const char *fmt; |
6410 | register int i; | |
6411 | register enum rtx_code code; | |
6412 | ||
6413 | if (*where == 0) | |
6414 | return 0; | |
6415 | ||
6416 | code = GET_CODE (*where); | |
284d86e9 JC |
6417 | |
6418 | switch (code) | |
6419 | { | |
284d86e9 | 6420 | case REG: |
e48addee JJ |
6421 | if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ |
6422 | return 1; | |
6423 | if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) | |
6424 | *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); | |
6425 | case SCRATCH: | |
6426 | case CC0: | |
6427 | case PC: | |
284d86e9 JC |
6428 | case CONST_INT: |
6429 | case CONST_DOUBLE: | |
e48addee | 6430 | return 0; |
76a7c776 | 6431 | |
09ebda1b SC |
6432 | /* Do not replace the frame pointer with the stack pointer because |
6433 | it can cause the delayed instruction to load below the stack. | |
6434 | This occurs when instructions like: | |
6435 | ||
6436 | (set (reg/i:SI 24 %i0) | |
6437 | (mem/f:SI (plus:SI (reg/f:SI 30 %fp) | |
6438 | (const_int -20 [0xffffffec])) 0)) | |
6439 | ||
6440 | are in the return delayed slot. */ | |
6441 | case PLUS: | |
6442 | if (GET_CODE (XEXP (*where, 0)) == REG | |
563c12b0 | 6443 | && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM |
09ebda1b SC |
6444 | && (GET_CODE (XEXP (*where, 1)) != CONST_INT |
6445 | || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS)) | |
6446 | return 1; | |
6447 | break; | |
6448 | ||
6449 | case MEM: | |
6450 | if (SPARC_STACK_BIAS | |
6451 | && GET_CODE (XEXP (*where, 0)) == REG | |
563c12b0 | 6452 | && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM) |
09ebda1b SC |
6453 | return 1; |
6454 | break; | |
6455 | ||
76a7c776 DM |
6456 | default: |
6457 | break; | |
e48addee | 6458 | } |
284d86e9 | 6459 | |
e48addee | 6460 | fmt = GET_RTX_FORMAT (code); |
284d86e9 | 6461 | |
e48addee JJ |
6462 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
6463 | { | |
6464 | if (fmt[i] == 'E') | |
6465 | { | |
6466 | register int j; | |
6467 | for (j = XVECLEN (*where, i) - 1; j >= 0; j--) | |
6468 | if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) | |
6469 | return 1; | |
6470 | } | |
6471 | else if (fmt[i] == 'e' | |
6472 | && epilogue_renumber (&(XEXP (*where, i)), test)) | |
6473 | return 1; | |
284d86e9 | 6474 | } |
e48addee | 6475 | return 0; |
284d86e9 | 6476 | } |
ab835497 RK |
6477 | \f |
6478 | /* Leaf functions and non-leaf functions have different needs. */ | |
6479 | ||
8b60264b | 6480 | static const int |
ab835497 RK |
6481 | reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; |
6482 | ||
8b60264b | 6483 | static const int |
ab835497 RK |
6484 | reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; |
6485 | ||
8b60264b | 6486 | static const int *const reg_alloc_orders[] = { |
ab835497 RK |
6487 | reg_leaf_alloc_order, |
6488 | reg_nonleaf_alloc_order}; | |
6489 | ||
6490 | void | |
fc27d102 | 6491 | order_regs_for_local_alloc (void) |
ab835497 RK |
6492 | { |
6493 | static int last_order_nonleaf = 1; | |
6494 | ||
6495 | if (regs_ever_live[15] != last_order_nonleaf) | |
6496 | { | |
6497 | last_order_nonleaf = !last_order_nonleaf; | |
2e09e75a | 6498 | memcpy ((char *) reg_alloc_order, |
8b60264b | 6499 | (const char *) reg_alloc_orders[last_order_nonleaf], |
2e09e75a | 6500 | FIRST_PSEUDO_REGISTER * sizeof (int)); |
ab835497 RK |
6501 | } |
6502 | } | |
6503 | \f | |
e0d80184 DM |
6504 | /* Return 1 if REG and MEM are legitimate enough to allow the various |
6505 | mem<-->reg splits to be run. */ | |
6506 | ||
6507 | int | |
fc27d102 | 6508 | sparc_splitdi_legitimate (rtx reg, rtx mem) |
e0d80184 | 6509 | { |
e0d80184 DM |
6510 | /* Punt if we are here by mistake. */ |
6511 | if (! reload_completed) | |
9208e4b2 | 6512 | abort (); |
e0d80184 DM |
6513 | |
6514 | /* We must have an offsettable memory reference. */ | |
6515 | if (! offsettable_memref_p (mem)) | |
6516 | return 0; | |
6517 | ||
6518 | /* If we have legitimate args for ldd/std, we do not want | |
6519 | the split to happen. */ | |
6520 | if ((REGNO (reg) % 2) == 0 | |
6521 | && mem_min_alignment (mem, 8)) | |
6522 | return 0; | |
6523 | ||
6524 | /* Success. */ | |
6525 | return 1; | |
6526 | } | |
6527 | ||
e61c29e9 | 6528 | /* Return 1 if x and y are some kind of REG and they refer to |
fae778eb | 6529 | different hard registers. This test is guaranteed to be |
e61c29e9 DM |
6530 | run after reload. */ |
6531 | ||
6532 | int | |
fc27d102 | 6533 | sparc_absnegfloat_split_legitimate (rtx x, rtx y) |
e61c29e9 | 6534 | { |
e61c29e9 DM |
6535 | if (GET_CODE (x) != REG) |
6536 | return 0; | |
e61c29e9 DM |
6537 | if (GET_CODE (y) != REG) |
6538 | return 0; | |
6539 | if (REGNO (x) == REGNO (y)) | |
6540 | return 0; | |
6541 | return 1; | |
6542 | } | |
6543 | ||
35016322 JW |
6544 | /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. |
6545 | This makes them candidates for using ldd and std insns. | |
6546 | ||
bfd6bc60 | 6547 | Note reg1 and reg2 *must* be hard registers. */ |
35016322 JW |
6548 | |
6549 | int | |
fc27d102 | 6550 | registers_ok_for_ldd_peep (rtx reg1, rtx reg2) |
35016322 | 6551 | { |
35016322 JW |
6552 | /* We might have been passed a SUBREG. */ |
6553 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
6554 | return 0; | |
6555 | ||
35016322 JW |
6556 | if (REGNO (reg1) % 2 != 0) |
6557 | return 0; | |
6558 | ||
bfd6bc60 JC |
6559 | /* Integer ldd is deprecated in SPARC V9 */ |
6560 | if (TARGET_V9 && REGNO (reg1) < 32) | |
6561 | return 0; | |
6562 | ||
35016322 | 6563 | return (REGNO (reg1) == REGNO (reg2) - 1); |
35016322 JW |
6564 | } |
6565 | ||
2aad5d68 | 6566 | /* Return 1 if the addresses in mem1 and mem2 are suitable for use in |
303f8933 DN |
6567 | an ldd or std insn. |
6568 | ||
2aad5d68 DN |
6569 | This can only happen when addr1 and addr2, the addresses in mem1 |
6570 | and mem2, are consecutive memory locations (addr1 + 4 == addr2). | |
303f8933 DN |
6571 | addr1 must also be aligned on a 64-bit boundary. |
6572 | ||
6573 | Also iff dependent_reg_rtx is not null it should not be used to | |
6574 | compute the address for mem1, i.e. we cannot optimize a sequence | |
6575 | like: | |
6576 | ld [%o0], %o0 | |
6577 | ld [%o0 + 4], %o1 | |
6578 | to | |
bcdd764b | 6579 | ldd [%o0], %o0 |
0acf409f DM |
6580 | nor: |
6581 | ld [%g3 + 4], %g3 | |
6582 | ld [%g3], %g2 | |
6583 | to | |
6584 | ldd [%g3], %g2 | |
6585 | ||
6586 | But, note that the transformation from: | |
6587 | ld [%g2 + 4], %g3 | |
6588 | ld [%g2], %g2 | |
6589 | to | |
6590 | ldd [%g2], %g2 | |
6591 | is perfectly fine. Thus, the peephole2 patterns always pass us | |
6592 | the destination register of the first load, never the second one. | |
6593 | ||
303f8933 DN |
6594 | For stores we don't have a similar problem, so dependent_reg_rtx is |
6595 | NULL_RTX. */ | |
35016322 JW |
6596 | |
6597 | int | |
fc27d102 | 6598 | mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx) |
35016322 | 6599 | { |
2aad5d68 | 6600 | rtx addr1, addr2; |
0d587737 | 6601 | unsigned int reg1; |
6a151f87 | 6602 | HOST_WIDE_INT offset1; |
35016322 | 6603 | |
303f8933 DN |
6604 | /* The mems cannot be volatile. */ |
6605 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
6606 | return 0; | |
2aad5d68 | 6607 | |
303f8933 | 6608 | /* MEM1 should be aligned on a 64-bit boundary. */ |
2aad5d68 DN |
6609 | if (MEM_ALIGN (mem1) < 64) |
6610 | return 0; | |
6611 | ||
303f8933 DN |
6612 | addr1 = XEXP (mem1, 0); |
6613 | addr2 = XEXP (mem2, 0); | |
6614 | ||
35016322 JW |
6615 | /* Extract a register number and offset (if used) from the first addr. */ |
6616 | if (GET_CODE (addr1) == PLUS) | |
6617 | { | |
6618 | /* If not a REG, return zero. */ | |
6619 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
6620 | return 0; | |
6621 | else | |
6622 | { | |
6623 | reg1 = REGNO (XEXP (addr1, 0)); | |
6624 | /* The offset must be constant! */ | |
6625 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
6626 | return 0; | |
6627 | offset1 = INTVAL (XEXP (addr1, 1)); | |
6628 | } | |
6629 | } | |
6630 | else if (GET_CODE (addr1) != REG) | |
6631 | return 0; | |
6632 | else | |
6633 | { | |
6634 | reg1 = REGNO (addr1); | |
6635 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
6636 | offset1 = 0; | |
6637 | } | |
6638 | ||
6639 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
6640 | if (GET_CODE (addr2) != PLUS) | |
6641 | return 0; | |
6642 | ||
6643 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
6644 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
6645 | return 0; | |
6646 | ||
35016322 JW |
6647 | if (reg1 != REGNO (XEXP (addr2, 0))) |
6648 | return 0; | |
6649 | ||
303f8933 DN |
6650 | if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx)) |
6651 | return 0; | |
6652 | ||
2296cba3 | 6653 | /* The first offset must be evenly divisible by 8 to ensure the |
35016322 JW |
6654 | address is 64 bit aligned. */ |
6655 | if (offset1 % 8 != 0) | |
6656 | return 0; | |
6657 | ||
6658 | /* The offset for the second addr must be 4 more than the first addr. */ | |
6659 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) | |
6660 | return 0; | |
6661 | ||
6662 | /* All the tests passed. addr1 and addr2 are valid for ldd and std | |
6663 | instructions. */ | |
6664 | return 1; | |
6665 | } | |
7c56249d JL |
6666 | |
6667 | /* Return 1 if reg is a pseudo, or is the first register in | |
6668 | a hard register pair. This makes it a candidate for use in | |
6669 | ldd and std insns. */ | |
6670 | ||
6671 | int | |
fc27d102 | 6672 | register_ok_for_ldd (rtx reg) |
7c56249d | 6673 | { |
7c56249d JL |
6674 | /* We might have been passed a SUBREG. */ |
6675 | if (GET_CODE (reg) != REG) | |
6676 | return 0; | |
6677 | ||
6678 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
6679 | return (REGNO (reg) % 2 == 0); | |
6680 | else | |
6681 | return 1; | |
7c56249d | 6682 | } |
ab835497 | 6683 | \f |
ab835497 RK |
6684 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
6685 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
6686 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
6687 | ||
6688 | void | |
fc27d102 | 6689 | print_operand (FILE *file, rtx x, int code) |
ab835497 RK |
6690 | { |
6691 | switch (code) | |
6692 | { | |
6693 | case '#': | |
6694 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
6695 | if (dbr_sequence_length () == 0) | |
e0d80184 | 6696 | fputs ("\n\t nop", file); |
ab835497 RK |
6697 | return; |
6698 | case '*': | |
c6ce0969 JW |
6699 | /* Output an annul flag if there's nothing for the delay slot and we |
6700 | are optimizing. This is always used with '(' below. */ | |
6701 | /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; | |
6702 | this is a dbx bug. So, we only do this when optimizing. */ | |
bfd6bc60 JC |
6703 | /* On UltraSPARC, a branch in a delay slot causes a pipeline flush. |
6704 | Always emit a nop in case the next instruction is a branch. */ | |
6705 | if (dbr_sequence_length () == 0 | |
284d86e9 | 6706 | && (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
c6ce0969 JW |
6707 | fputs (",a", file); |
6708 | return; | |
6709 | case '(': | |
6710 | /* Output a 'nop' if there's nothing for the delay slot and we are | |
6711 | not optimizing. This is always used with '*' above. */ | |
bfd6bc60 | 6712 | if (dbr_sequence_length () == 0 |
284d86e9 | 6713 | && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
e0d80184 | 6714 | fputs ("\n\t nop", file); |
ab835497 | 6715 | return; |
61a55e8b | 6716 | case '_': |
a0a301fc DE |
6717 | /* Output the Embedded Medium/Anywhere code model base register. */ |
6718 | fputs (EMBMEDANY_BASE_REG, file); | |
61a55e8b DE |
6719 | return; |
6720 | case '@': | |
6721 | /* Print out what we are using as the frame pointer. This might | |
6722 | be %fp, or might be %sp+offset. */ | |
6723 | /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ | |
6a151f87 | 6724 | fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC, frame_base_name, frame_base_offset); |
61a55e8b | 6725 | return; |
5751a10b JJ |
6726 | case '&': |
6727 | /* Print some local dynamic TLS name. */ | |
6728 | assemble_name (file, get_some_local_dynamic_name ()); | |
6729 | return; | |
ab835497 RK |
6730 | case 'Y': |
6731 | /* Adjust the operand to take into account a RESTORE operation. */ | |
bfd6bc60 JC |
6732 | if (GET_CODE (x) == CONST_INT) |
6733 | break; | |
6734 | else if (GET_CODE (x) != REG) | |
c725bd79 | 6735 | output_operand_lossage ("invalid %%Y operand"); |
b3b1e8bd | 6736 | else if (REGNO (x) < 8) |
ab835497 RK |
6737 | fputs (reg_names[REGNO (x)], file); |
6738 | else if (REGNO (x) >= 24 && REGNO (x) < 32) | |
6739 | fputs (reg_names[REGNO (x)-16], file); | |
6740 | else | |
c725bd79 | 6741 | output_operand_lossage ("invalid %%Y operand"); |
ab835497 | 6742 | return; |
0f39a9aa DE |
6743 | case 'L': |
6744 | /* Print out the low order register name of a register pair. */ | |
6745 | if (WORDS_BIG_ENDIAN) | |
6746 | fputs (reg_names[REGNO (x)+1], file); | |
6747 | else | |
6748 | fputs (reg_names[REGNO (x)], file); | |
6749 | return; | |
6750 | case 'H': | |
6751 | /* Print out the high order register name of a register pair. */ | |
6752 | if (WORDS_BIG_ENDIAN) | |
6753 | fputs (reg_names[REGNO (x)], file); | |
6754 | else | |
6755 | fputs (reg_names[REGNO (x)+1], file); | |
6756 | return; | |
ab835497 | 6757 | case 'R': |
795068a4 | 6758 | /* Print out the second register name of a register pair or quad. |
ab835497 RK |
6759 | I.e., R (%o0) => %o1. */ |
6760 | fputs (reg_names[REGNO (x)+1], file); | |
6761 | return; | |
795068a4 JW |
6762 | case 'S': |
6763 | /* Print out the third register name of a register quad. | |
6764 | I.e., S (%o0) => %o2. */ | |
6765 | fputs (reg_names[REGNO (x)+2], file); | |
6766 | return; | |
6767 | case 'T': | |
6768 | /* Print out the fourth register name of a register quad. | |
6769 | I.e., T (%o0) => %o3. */ | |
6770 | fputs (reg_names[REGNO (x)+3], file); | |
6771 | return; | |
304b7a23 DE |
6772 | case 'x': |
6773 | /* Print a condition code register. */ | |
6774 | if (REGNO (x) == SPARC_ICC_REG) | |
6775 | { | |
6776 | /* We don't handle CC[X]_NOOVmode because they're not supposed | |
6777 | to occur here. */ | |
6778 | if (GET_MODE (x) == CCmode) | |
6779 | fputs ("%icc", file); | |
6780 | else if (GET_MODE (x) == CCXmode) | |
6781 | fputs ("%xcc", file); | |
6782 | else | |
6783 | abort (); | |
6784 | } | |
6785 | else | |
6786 | /* %fccN register */ | |
6787 | fputs (reg_names[REGNO (x)], file); | |
6788 | return; | |
ab835497 RK |
6789 | case 'm': |
6790 | /* Print the operand's address only. */ | |
6791 | output_address (XEXP (x, 0)); | |
6792 | return; | |
6793 | case 'r': | |
6794 | /* In this case we need a register. Use %g0 if the | |
77a02b01 | 6795 | operand is const0_rtx. */ |
76052e74 RS |
6796 | if (x == const0_rtx |
6797 | || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) | |
ab835497 RK |
6798 | { |
6799 | fputs ("%g0", file); | |
6800 | return; | |
6801 | } | |
6802 | else | |
6803 | break; | |
6804 | ||
61a55e8b | 6805 | case 'A': |
ab835497 RK |
6806 | switch (GET_CODE (x)) |
6807 | { | |
6808 | case IOR: fputs ("or", file); break; | |
6809 | case AND: fputs ("and", file); break; | |
6810 | case XOR: fputs ("xor", file); break; | |
c725bd79 | 6811 | default: output_operand_lossage ("invalid %%A operand"); |
ab835497 RK |
6812 | } |
6813 | return; | |
6814 | ||
6815 | case 'B': | |
6816 | switch (GET_CODE (x)) | |
6817 | { | |
6818 | case IOR: fputs ("orn", file); break; | |
6819 | case AND: fputs ("andn", file); break; | |
6820 | case XOR: fputs ("xnor", file); break; | |
c725bd79 | 6821 | default: output_operand_lossage ("invalid %%B operand"); |
ab835497 RK |
6822 | } |
6823 | return; | |
6824 | ||
304b7a23 DE |
6825 | /* These are used by the conditional move instructions. */ |
6826 | case 'c' : | |
61a55e8b | 6827 | case 'C': |
304b7a23 | 6828 | { |
5c5c34a4 JJ |
6829 | enum rtx_code rc = GET_CODE (x); |
6830 | ||
6831 | if (code == 'c') | |
6832 | { | |
6833 | enum machine_mode mode = GET_MODE (XEXP (x, 0)); | |
6834 | if (mode == CCFPmode || mode == CCFPEmode) | |
6835 | rc = reverse_condition_maybe_unordered (GET_CODE (x)); | |
6836 | else | |
6837 | rc = reverse_condition (GET_CODE (x)); | |
6838 | } | |
304b7a23 DE |
6839 | switch (rc) |
6840 | { | |
6841 | case NE: fputs ("ne", file); break; | |
6842 | case EQ: fputs ("e", file); break; | |
6843 | case GE: fputs ("ge", file); break; | |
6844 | case GT: fputs ("g", file); break; | |
6845 | case LE: fputs ("le", file); break; | |
6846 | case LT: fputs ("l", file); break; | |
6847 | case GEU: fputs ("geu", file); break; | |
6848 | case GTU: fputs ("gu", file); break; | |
6849 | case LEU: fputs ("leu", file); break; | |
6850 | case LTU: fputs ("lu", file); break; | |
5c5c34a4 JJ |
6851 | case LTGT: fputs ("lg", file); break; |
6852 | case UNORDERED: fputs ("u", file); break; | |
6853 | case ORDERED: fputs ("o", file); break; | |
6854 | case UNLT: fputs ("ul", file); break; | |
6855 | case UNLE: fputs ("ule", file); break; | |
6856 | case UNGT: fputs ("ug", file); break; | |
6857 | case UNGE: fputs ("uge", file); break; | |
6858 | case UNEQ: fputs ("ue", file); break; | |
304b7a23 | 6859 | default: output_operand_lossage (code == 'c' |
c725bd79 NB |
6860 | ? "invalid %%c operand" |
6861 | : "invalid %%C operand"); | |
304b7a23 DE |
6862 | } |
6863 | return; | |
6864 | } | |
6865 | ||
6866 | /* These are used by the movr instruction pattern. */ | |
6867 | case 'd': | |
61a55e8b | 6868 | case 'D': |
304b7a23 DE |
6869 | { |
6870 | enum rtx_code rc = (code == 'd' | |
6871 | ? reverse_condition (GET_CODE (x)) | |
6872 | : GET_CODE (x)); | |
6873 | switch (rc) | |
6874 | { | |
6875 | case NE: fputs ("ne", file); break; | |
6876 | case EQ: fputs ("e", file); break; | |
6877 | case GE: fputs ("gez", file); break; | |
6878 | case LT: fputs ("lz", file); break; | |
6879 | case LE: fputs ("lez", file); break; | |
6880 | case GT: fputs ("gz", file); break; | |
6881 | default: output_operand_lossage (code == 'd' | |
c725bd79 NB |
6882 | ? "invalid %%d operand" |
6883 | : "invalid %%D operand"); | |
304b7a23 DE |
6884 | } |
6885 | return; | |
6886 | } | |
61a55e8b | 6887 | |
ab835497 RK |
6888 | case 'b': |
6889 | { | |
6890 | /* Print a sign-extended character. */ | |
9e0625a3 | 6891 | int i = trunc_int_for_mode (INTVAL (x), QImode); |
ab835497 RK |
6892 | fprintf (file, "%d", i); |
6893 | return; | |
6894 | } | |
6895 | ||
d2889939 RK |
6896 | case 'f': |
6897 | /* Operand must be a MEM; write its address. */ | |
6898 | if (GET_CODE (x) != MEM) | |
c725bd79 | 6899 | output_operand_lossage ("invalid %%f operand"); |
d2889939 RK |
6900 | output_address (XEXP (x, 0)); |
6901 | return; | |
6902 | ||
8707fe93 RH |
6903 | case 's': |
6904 | { | |
6905 | /* Print a sign-extended 32-bit value. */ | |
6906 | HOST_WIDE_INT i; | |
6907 | if (GET_CODE(x) == CONST_INT) | |
6908 | i = INTVAL (x); | |
6909 | else if (GET_CODE(x) == CONST_DOUBLE) | |
6910 | i = CONST_DOUBLE_LOW (x); | |
6911 | else | |
ffa916ba KG |
6912 | { |
6913 | output_operand_lossage ("invalid %%s operand"); | |
6914 | return; | |
6915 | } | |
8707fe93 RH |
6916 | i = trunc_int_for_mode (i, SImode); |
6917 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, i); | |
6918 | return; | |
6919 | } | |
6920 | ||
ab835497 RK |
6921 | case 0: |
6922 | /* Do nothing special. */ | |
6923 | break; | |
6924 | ||
6925 | default: | |
6926 | /* Undocumented flag. */ | |
415f583e | 6927 | output_operand_lossage ("invalid operand output code"); |
ab835497 RK |
6928 | } |
6929 | ||
6930 | if (GET_CODE (x) == REG) | |
6931 | fputs (reg_names[REGNO (x)], file); | |
6932 | else if (GET_CODE (x) == MEM) | |
6933 | { | |
6934 | fputc ('[', file); | |
ab835497 | 6935 | /* Poor Sun assembler doesn't understand absolute addressing. */ |
e6c1be7e | 6936 | if (CONSTANT_P (XEXP (x, 0))) |
ab835497 RK |
6937 | fputs ("%g0+", file); |
6938 | output_address (XEXP (x, 0)); | |
6939 | fputc (']', file); | |
6940 | } | |
6941 | else if (GET_CODE (x) == HIGH) | |
6942 | { | |
6943 | fputs ("%hi(", file); | |
6944 | output_addr_const (file, XEXP (x, 0)); | |
6945 | fputc (')', file); | |
6946 | } | |
6947 | else if (GET_CODE (x) == LO_SUM) | |
6948 | { | |
6949 | print_operand (file, XEXP (x, 0), 0); | |
e0d80184 DM |
6950 | if (TARGET_CM_MEDMID) |
6951 | fputs ("+%l44(", file); | |
6952 | else | |
6953 | fputs ("+%lo(", file); | |
ab835497 RK |
6954 | output_addr_const (file, XEXP (x, 1)); |
6955 | fputc (')', file); | |
6956 | } | |
e601abce JW |
6957 | else if (GET_CODE (x) == CONST_DOUBLE |
6958 | && (GET_MODE (x) == VOIDmode | |
6959 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) | |
ab835497 RK |
6960 | { |
6961 | if (CONST_DOUBLE_HIGH (x) == 0) | |
0d9484c5 | 6962 | fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x)); |
ab835497 RK |
6963 | else if (CONST_DOUBLE_HIGH (x) == -1 |
6964 | && CONST_DOUBLE_LOW (x) < 0) | |
0d9484c5 | 6965 | fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x)); |
ab835497 | 6966 | else |
e601abce | 6967 | output_operand_lossage ("long long constant not a valid immediate operand"); |
ab835497 | 6968 | } |
e601abce JW |
6969 | else if (GET_CODE (x) == CONST_DOUBLE) |
6970 | output_operand_lossage ("floating point constant not a valid immediate operand"); | |
ab835497 RK |
6971 | else { output_addr_const (file, x); } |
6972 | } | |
6973 | \f | |
301d03af RS |
6974 | /* Target hook for assembling integer objects. The sparc version has |
6975 | special handling for aligned DI-mode objects. */ | |
ab835497 | 6976 | |
301d03af | 6977 | static bool |
fc27d102 | 6978 | sparc_assemble_integer (rtx x, unsigned int size, int aligned_p) |
ab835497 | 6979 | { |
301d03af RS |
6980 | /* ??? We only output .xword's for symbols and only then in environments |
6981 | where the assembler can handle them. */ | |
6982 | if (aligned_p && size == 8 | |
6983 | && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE)) | |
ab835497 | 6984 | { |
301d03af | 6985 | if (TARGET_V9) |
61a55e8b | 6986 | { |
301d03af RS |
6987 | assemble_integer_with_op ("\t.xword\t", x); |
6988 | return true; | |
61a55e8b DE |
6989 | } |
6990 | else | |
6991 | { | |
301d03af RS |
6992 | assemble_aligned_integer (4, const0_rtx); |
6993 | assemble_aligned_integer (4, x); | |
6994 | return true; | |
61a55e8b | 6995 | } |
ab835497 | 6996 | } |
301d03af | 6997 | return default_assemble_integer (x, size, aligned_p); |
ab835497 | 6998 | } |
210aa14a | 6999 | \f |
b0468b84 RK |
7000 | /* Return the value of a code used in the .proc pseudo-op that says |
7001 | what kind of result this function returns. For non-C types, we pick | |
7002 | the closest C type. */ | |
7003 | ||
77a02b01 JW |
7004 | #ifndef SHORT_TYPE_SIZE |
7005 | #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) | |
7006 | #endif | |
7007 | ||
7008 | #ifndef INT_TYPE_SIZE | |
7009 | #define INT_TYPE_SIZE BITS_PER_WORD | |
7010 | #endif | |
7011 | ||
7012 | #ifndef LONG_TYPE_SIZE | |
7013 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
7014 | #endif | |
7015 | ||
7016 | #ifndef LONG_LONG_TYPE_SIZE | |
7017 | #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) | |
7018 | #endif | |
7019 | ||
7020 | #ifndef FLOAT_TYPE_SIZE | |
7021 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
7022 | #endif | |
7023 | ||
7024 | #ifndef DOUBLE_TYPE_SIZE | |
7025 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
7026 | #endif | |
7027 | ||
7028 | #ifndef LONG_DOUBLE_TYPE_SIZE | |
7029 | #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
7030 | #endif | |
210aa14a RS |
7031 | |
7032 | unsigned long | |
fc27d102 | 7033 | sparc_type_code (register tree type) |
210aa14a RS |
7034 | { |
7035 | register unsigned long qualifiers = 0; | |
e5e809f4 | 7036 | register unsigned shift; |
210aa14a | 7037 | |
abc95ed3 | 7038 | /* Only the first 30 bits of the qualifier are valid. We must refrain from |
aee2c3c5 JW |
7039 | setting more, since some assemblers will give an error for this. Also, |
7040 | we must be careful to avoid shifts of 32 bits or more to avoid getting | |
7041 | unpredictable results. */ | |
7042 | ||
e5e809f4 | 7043 | for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) |
210aa14a RS |
7044 | { |
7045 | switch (TREE_CODE (type)) | |
7046 | { | |
7047 | case ERROR_MARK: | |
7048 | return qualifiers; | |
7049 | ||
7050 | case ARRAY_TYPE: | |
e5e809f4 | 7051 | qualifiers |= (3 << shift); |
210aa14a RS |
7052 | break; |
7053 | ||
7054 | case FUNCTION_TYPE: | |
7055 | case METHOD_TYPE: | |
e5e809f4 | 7056 | qualifiers |= (2 << shift); |
210aa14a RS |
7057 | break; |
7058 | ||
7059 | case POINTER_TYPE: | |
7060 | case REFERENCE_TYPE: | |
7061 | case OFFSET_TYPE: | |
e5e809f4 | 7062 | qualifiers |= (1 << shift); |
210aa14a | 7063 | break; |
ab835497 | 7064 | |
210aa14a RS |
7065 | case RECORD_TYPE: |
7066 | return (qualifiers | 8); | |
7067 | ||
7068 | case UNION_TYPE: | |
b0468b84 | 7069 | case QUAL_UNION_TYPE: |
210aa14a RS |
7070 | return (qualifiers | 9); |
7071 | ||
7072 | case ENUMERAL_TYPE: | |
7073 | return (qualifiers | 10); | |
7074 | ||
7075 | case VOID_TYPE: | |
7076 | return (qualifiers | 16); | |
7077 | ||
7078 | case INTEGER_TYPE: | |
654209e6 JW |
7079 | /* If this is a range type, consider it to be the underlying |
7080 | type. */ | |
7081 | if (TREE_TYPE (type) != 0) | |
e5e809f4 | 7082 | break; |
654209e6 | 7083 | |
77a02b01 | 7084 | /* Carefully distinguish all the standard types of C, |
b0468b84 RK |
7085 | without messing up if the language is not C. We do this by |
7086 | testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to | |
7087 | look at both the names and the above fields, but that's redundant. | |
7088 | Any type whose size is between two C types will be considered | |
7089 | to be the wider of the two types. Also, we do not have a | |
7090 | special code to use for "long long", so anything wider than | |
7091 | long is treated the same. Note that we can't distinguish | |
7092 | between "int" and "long" in this code if they are the same | |
7093 | size, but that's fine, since neither can the assembler. */ | |
7094 | ||
7095 | if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) | |
7096 | return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); | |
77a02b01 | 7097 | |
b0468b84 RK |
7098 | else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) |
7099 | return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); | |
77a02b01 | 7100 | |
b0468b84 | 7101 | else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) |
77a02b01 JW |
7102 | return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); |
7103 | ||
b0468b84 | 7104 | else |
77a02b01 JW |
7105 | return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); |
7106 | ||
210aa14a | 7107 | case REAL_TYPE: |
e5e809f4 JL |
7108 | /* If this is a range type, consider it to be the underlying |
7109 | type. */ | |
7110 | if (TREE_TYPE (type) != 0) | |
7111 | break; | |
7112 | ||
77a02b01 JW |
7113 | /* Carefully distinguish all the standard types of C, |
7114 | without messing up if the language is not C. */ | |
b0468b84 | 7115 | |
77a02b01 | 7116 | if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) |
210aa14a | 7117 | return (qualifiers | 6); |
b0468b84 RK |
7118 | |
7119 | else | |
7120 | return (qualifiers | 7); | |
210aa14a RS |
7121 | |
7122 | case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ | |
13d39dbc | 7123 | /* ??? We need to distinguish between double and float complex types, |
c82aa69a JW |
7124 | but I don't know how yet because I can't reach this code from |
7125 | existing front-ends. */ | |
7126 | return (qualifiers | 7); /* Who knows? */ | |
7127 | ||
210aa14a RS |
7128 | case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ |
7129 | case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ | |
7130 | case FILE_TYPE: /* GNU Pascal FILE type. */ | |
26902ae0 | 7131 | case SET_TYPE: /* GNU Pascal SET type. */ |
210aa14a | 7132 | case LANG_TYPE: /* ? */ |
26902ae0 | 7133 | return qualifiers; |
210aa14a RS |
7134 | |
7135 | default: | |
7136 | abort (); /* Not a type! */ | |
7137 | } | |
7138 | } | |
e5e809f4 JL |
7139 | |
7140 | return qualifiers; | |
210aa14a | 7141 | } |
ead69aea | 7142 | \f |
61a55e8b DE |
7143 | /* Nested function support. */ |
7144 | ||
7145 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
7146 | FNADDR is an RTX for the address of the function's pure code. | |
7147 | CXT is an RTX for the static chain value for the function. | |
7148 | ||
7149 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
7150 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
7151 | (to store insns). This is a bit excessive. Perhaps a different | |
7152 | mechanism would be better here. | |
7153 | ||
849a528d | 7154 | Emit enough FLUSH insns to synchronize the data and instruction caches. */ |
61a55e8b DE |
7155 | |
7156 | void | |
fc27d102 | 7157 | sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt) |
61a55e8b | 7158 | { |
1ec0c607 | 7159 | /* SPARC 32-bit trampoline: |
c6b0465b | 7160 | |
e0d80184 DM |
7161 | sethi %hi(fn), %g1 |
7162 | sethi %hi(static), %g2 | |
7163 | jmp %g1+%lo(fn) | |
7164 | or %g2, %lo(static), %g2 | |
c6b0465b JC |
7165 | |
7166 | SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii | |
7167 | JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii | |
7168 | */ | |
7169 | ||
35aa3c1c RK |
7170 | emit_move_insn |
7171 | (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), | |
7172 | expand_binop (SImode, ior_optab, | |
7173 | expand_shift (RSHIFT_EXPR, SImode, fnaddr, | |
7174 | size_int (10), 0, 1), | |
7175 | GEN_INT (trunc_int_for_mode (0x03000000, SImode)), | |
7176 | NULL_RTX, 1, OPTAB_DIRECT)); | |
7177 | ||
7178 | emit_move_insn | |
7179 | (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), | |
7180 | expand_binop (SImode, ior_optab, | |
7181 | expand_shift (RSHIFT_EXPR, SImode, cxt, | |
7182 | size_int (10), 0, 1), | |
7183 | GEN_INT (trunc_int_for_mode (0x05000000, SImode)), | |
7184 | NULL_RTX, 1, OPTAB_DIRECT)); | |
7185 | ||
7186 | emit_move_insn | |
7187 | (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), | |
7188 | expand_binop (SImode, ior_optab, | |
7189 | expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX), | |
7190 | GEN_INT (trunc_int_for_mode (0x81c06000, SImode)), | |
7191 | NULL_RTX, 1, OPTAB_DIRECT)); | |
7192 | ||
7193 | emit_move_insn | |
7194 | (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), | |
7195 | expand_binop (SImode, ior_optab, | |
7196 | expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX), | |
7197 | GEN_INT (trunc_int_for_mode (0x8410a000, SImode)), | |
7198 | NULL_RTX, 1, OPTAB_DIRECT)); | |
c6b0465b | 7199 | |
c6b0465b JC |
7200 | /* On UltraSPARC a flush flushes an entire cache line. The trampoline is |
7201 | aligned on a 16 byte boundary so one flush clears it all. */ | |
35aa3c1c | 7202 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); |
84643cbf DM |
7203 | if (sparc_cpu != PROCESSOR_ULTRASPARC |
7204 | && sparc_cpu != PROCESSOR_ULTRASPARC3) | |
c6b0465b JC |
7205 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, |
7206 | plus_constant (tramp, 8))))); | |
1ec0c607 WH |
7207 | |
7208 | /* Call __enable_execute_stack after writing onto the stack to make sure | |
7209 | the stack address is accessible. */ | |
7210 | #ifdef TRANSFER_FROM_TRAMPOLINE | |
7211 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
7212 | LCT_NORMAL, VOIDmode, 1, tramp, Pmode); | |
7213 | #endif | |
7214 | ||
61a55e8b DE |
7215 | } |
7216 | ||
1ec0c607 | 7217 | /* The 64-bit version is simpler because it makes more sense to load the |
849a528d RK |
7218 | values as "immediate" data out of the trampoline. It's also easier since |
7219 | we can read the PC without clobbering a register. */ | |
7220 | ||
61a55e8b | 7221 | void |
fc27d102 | 7222 | sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt) |
61a55e8b | 7223 | { |
1ec0c607 | 7224 | /* SPARC 64-bit trampoline: |
345a6161 | 7225 | |
e0d80184 DM |
7226 | rd %pc, %g1 |
7227 | ldx [%g1+24], %g5 | |
7228 | jmp %g5 | |
7229 | ldx [%g1+16], %g5 | |
c6b0465b JC |
7230 | +16 bytes data |
7231 | */ | |
7232 | ||
7233 | emit_move_insn (gen_rtx_MEM (SImode, tramp), | |
e3aaacf4 | 7234 | GEN_INT (trunc_int_for_mode (0x83414000, SImode))); |
c6b0465b | 7235 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), |
e3aaacf4 | 7236 | GEN_INT (trunc_int_for_mode (0xca586018, SImode))); |
c6b0465b | 7237 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), |
e3aaacf4 | 7238 | GEN_INT (trunc_int_for_mode (0x81c14000, SImode))); |
c6b0465b | 7239 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), |
e3aaacf4 | 7240 | GEN_INT (trunc_int_for_mode (0xca586010, SImode))); |
c6b0465b | 7241 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); |
345a6161 | 7242 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); |
d4203cb4 | 7243 | emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp)))); |
345a6161 | 7244 | |
fae15c93 VM |
7245 | if (sparc_cpu != PROCESSOR_ULTRASPARC |
7246 | && sparc_cpu != PROCESSOR_ULTRASPARC3) | |
d4203cb4 | 7247 | emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); |
1ec0c607 WH |
7248 | |
7249 | /* Call __enable_execute_stack after writing onto the stack to make sure | |
7250 | the stack address is accessible. */ | |
7251 | #ifdef TRANSFER_FROM_TRAMPOLINE | |
7252 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
7253 | LCT_NORMAL, VOIDmode, 1, tramp, Pmode); | |
7254 | #endif | |
61a55e8b DE |
7255 | } |
7256 | \f | |
c819be5b JW |
7257 | /* Subroutines to support a flat (single) register window calling |
7258 | convention. */ | |
7259 | ||
7260 | /* Single-register window sparc stack frames look like: | |
7261 | ||
7262 | Before call After call | |
7263 | +-----------------------+ +-----------------------+ | |
86735b02 DE |
7264 | high | | | | |
7265 | mem | caller's temps. | | caller's temps. | | |
c819be5b JW |
7266 | | | | | |
7267 | +-----------------------+ +-----------------------+ | |
7268 | | | | | | |
7269 | | arguments on stack. | | arguments on stack. | | |
86735b02 DE |
7270 | | | | | |
7271 | +-----------------------+FP+92->+-----------------------+ | |
c819be5b JW |
7272 | | 6 words to save | | 6 words to save | |
7273 | | arguments passed | | arguments passed | | |
7274 | | in registers, even | | in registers, even | | |
86735b02 DE |
7275 | | if not passed. | | if not passed. | |
7276 | SP+68->+-----------------------+FP+68->+-----------------------+ | |
7277 | | 1 word struct addr | | 1 word struct addr | | |
7278 | +-----------------------+FP+64->+-----------------------+ | |
7279 | | | | | | |
7280 | | 16 word reg save area | | 16 word reg save area | | |
7281 | | | | | | |
7282 | SP->+-----------------------+ FP->+-----------------------+ | |
7283 | | 4 word area for | | |
7284 | | fp/alu reg moves | | |
7285 | FP-16->+-----------------------+ | |
7286 | | | | |
7287 | | local variables | | |
7288 | | | | |
7289 | +-----------------------+ | |
7290 | | | | |
c819be5b | 7291 | | fp register save | |
86735b02 DE |
7292 | | | |
7293 | +-----------------------+ | |
7294 | | | | |
c819be5b JW |
7295 | | gp register save | |
7296 | | | | |
86735b02 DE |
7297 | +-----------------------+ |
7298 | | | | |
c819be5b | 7299 | | alloca allocations | |
86735b02 DE |
7300 | | | |
7301 | +-----------------------+ | |
7302 | | | | |
c819be5b | 7303 | | arguments on stack | |
86735b02 DE |
7304 | | | |
7305 | SP+92->+-----------------------+ | |
c819be5b | 7306 | | 6 words to save | |
86735b02 | 7307 | | arguments passed | |
c819be5b | 7308 | | in registers, even | |
86735b02 DE |
7309 | low | if not passed. | |
7310 | memory SP+68->+-----------------------+ | |
7311 | | 1 word struct addr | | |
7312 | SP+64->+-----------------------+ | |
7313 | | | | |
7314 | I 16 word reg save area | | |
7315 | | | | |
7316 | SP->+-----------------------+ */ | |
c819be5b | 7317 | |
c6aa9ce1 | 7318 | /* Structure to be filled in by sparc_flat_compute_frame_size with register |
c819be5b JW |
7319 | save masks, and offsets for the current function. */ |
7320 | ||
7321 | struct sparc_frame_info | |
7322 | { | |
6a151f87 EB |
7323 | HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */ |
7324 | HOST_WIDE_INT var_size; /* # bytes that variables take up. */ | |
7325 | int args_size; /* # bytes that outgoing arguments take up. */ | |
7326 | int extra_size; /* # bytes of extra gunk. */ | |
7327 | int gp_reg_size; /* # bytes needed to store gp regs. */ | |
7328 | int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 7329 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 7330 | unsigned long fmask; /* Mask of saved fp registers. */ |
6a151f87 EB |
7331 | int reg_offset; /* Offset from new sp to store regs. */ |
7332 | int initialized; /* Nonzero if frame size already calculated. */ | |
c819be5b JW |
7333 | }; |
7334 | ||
c6aa9ce1 | 7335 | /* Current frame information calculated by sparc_flat_compute_frame_size. */ |
c819be5b JW |
7336 | struct sparc_frame_info current_frame_info; |
7337 | ||
7338 | /* Zero structure to initialize current_frame_info. */ | |
7339 | struct sparc_frame_info zero_frame_info; | |
7340 | ||
86735b02 | 7341 | #define RETURN_ADDR_REGNUM 15 |
563c12b0 | 7342 | #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM)) |
86735b02 | 7343 | #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) |
4f0504d9 EB |
7344 | \f |
7345 | /* Tell prologue and epilogue if register REGNO should be saved / restored. */ | |
86735b02 | 7346 | |
4f0504d9 EB |
7347 | static bool |
7348 | sparc_flat_must_save_register_p (int regno) | |
7349 | { | |
7350 | /* General case: call-saved registers live at some point. */ | |
7351 | if (!call_used_regs[regno] && regs_ever_live[regno]) | |
7352 | return true; | |
7353 | ||
7354 | /* Frame pointer register (%i7) if needed. */ | |
7355 | if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) | |
7356 | return true; | |
7357 | ||
7358 | /* PIC register (%l7) if needed. */ | |
7359 | if (regno == (int) PIC_OFFSET_TABLE_REGNUM | |
7360 | && flag_pic && current_function_uses_pic_offset_table) | |
7361 | return true; | |
7362 | ||
7363 | /* Return address register (%o7) if needed. */ | |
7364 | if (regno == RETURN_ADDR_REGNUM | |
7365 | && (regs_ever_live[RETURN_ADDR_REGNUM] | |
7366 | /* When the PIC offset table is used, the PIC register | |
7367 | is set by using a bare call that clobbers %o7. */ | |
7368 | || (flag_pic && current_function_uses_pic_offset_table))) | |
7369 | return true; | |
c819be5b | 7370 | |
4f0504d9 EB |
7371 | return false; |
7372 | } | |
7373 | \f | |
c819be5b JW |
7374 | /* Return the bytes needed to compute the frame pointer from the current |
7375 | stack pointer. */ | |
7376 | ||
6a151f87 EB |
7377 | HOST_WIDE_INT |
7378 | sparc_flat_compute_frame_size (HOST_WIDE_INT size) | |
fc27d102 | 7379 | /* # of var. bytes allocated. */ |
c819be5b JW |
7380 | { |
7381 | int regno; | |
6a151f87 EB |
7382 | HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */ |
7383 | HOST_WIDE_INT var_size; /* # bytes that variables take up. */ | |
7384 | int args_size; /* # bytes that outgoing arguments take up. */ | |
7385 | int extra_size; /* # extra bytes. */ | |
7386 | int gp_reg_size; /* # bytes needed to store gp regs. */ | |
7387 | int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 7388 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 7389 | unsigned long fmask; /* Mask of saved fp registers. */ |
6a151f87 | 7390 | int reg_offset; /* Offset to register save area. */ |
86735b02 | 7391 | int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ |
c819be5b JW |
7392 | |
7393 | /* This is the size of the 16 word reg save area, 1 word struct addr | |
7394 | area, and 4 word fp/alu register copy area. */ | |
8c64be75 SC |
7395 | extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); |
7396 | var_size = size; | |
7397 | gp_reg_size = 0; | |
7398 | fp_reg_size = 0; | |
7399 | gmask = 0; | |
7400 | fmask = 0; | |
7401 | reg_offset = 0; | |
86735b02 | 7402 | need_aligned_p = 0; |
c819be5b | 7403 | |
8c64be75 SC |
7404 | args_size = 0; |
7405 | if (!leaf_function_p ()) | |
7406 | { | |
7407 | /* Also include the size needed for the 6 parameter registers. */ | |
7408 | args_size = current_function_outgoing_args_size + 24; | |
7409 | } | |
7410 | total_size = var_size + args_size; | |
7411 | ||
c819be5b JW |
7412 | /* Calculate space needed for gp registers. */ |
7413 | for (regno = 1; regno <= 31; regno++) | |
7414 | { | |
4f0504d9 | 7415 | if (sparc_flat_must_save_register_p (regno)) |
c819be5b | 7416 | { |
86735b02 DE |
7417 | /* If we need to save two regs in a row, ensure there's room to bump |
7418 | up the address to align it to a doubleword boundary. */ | |
4f0504d9 | 7419 | if ((regno & 0x1) == 0 && sparc_flat_must_save_register_p (regno+1)) |
c819be5b JW |
7420 | { |
7421 | if (gp_reg_size % 8 != 0) | |
86735b02 | 7422 | gp_reg_size += 4; |
c819be5b | 7423 | gp_reg_size += 2 * UNITS_PER_WORD; |
86735b02 | 7424 | gmask |= 3 << regno; |
c819be5b | 7425 | regno++; |
86735b02 | 7426 | need_aligned_p = 1; |
c819be5b JW |
7427 | } |
7428 | else | |
7429 | { | |
7430 | gp_reg_size += UNITS_PER_WORD; | |
86735b02 | 7431 | gmask |= 1 << regno; |
c819be5b JW |
7432 | } |
7433 | } | |
7434 | } | |
c819be5b JW |
7435 | |
7436 | /* Calculate space needed for fp registers. */ | |
7437 | for (regno = 32; regno <= 63; regno++) | |
7438 | { | |
7439 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
7440 | { | |
7441 | fp_reg_size += UNITS_PER_WORD; | |
7442 | fmask |= 1 << (regno - 32); | |
7443 | } | |
7444 | } | |
7445 | ||
86735b02 DE |
7446 | if (gmask || fmask) |
7447 | { | |
7448 | int n; | |
7449 | reg_offset = FIRST_PARM_OFFSET(0) + args_size; | |
7450 | /* Ensure save area is 8 byte aligned if we need it. */ | |
7451 | n = reg_offset % 8; | |
7452 | if (need_aligned_p && n != 0) | |
7453 | { | |
7454 | total_size += 8 - n; | |
7455 | reg_offset += 8 - n; | |
7456 | } | |
7457 | total_size += gp_reg_size + fp_reg_size; | |
7458 | } | |
c819be5b | 7459 | |
8c64be75 SC |
7460 | /* If we must allocate a stack frame at all, we must also allocate |
7461 | room for register window spillage, so as to be binary compatible | |
7462 | with libraries and operating systems that do not use -mflat. */ | |
7463 | if (total_size > 0) | |
7464 | total_size += extra_size; | |
7465 | else | |
7466 | extra_size = 0; | |
c819be5b JW |
7467 | |
7468 | total_size = SPARC_STACK_ALIGN (total_size); | |
7469 | ||
7470 | /* Save other computed information. */ | |
7471 | current_frame_info.total_size = total_size; | |
7472 | current_frame_info.var_size = var_size; | |
7473 | current_frame_info.args_size = args_size; | |
7474 | current_frame_info.extra_size = extra_size; | |
7475 | current_frame_info.gp_reg_size = gp_reg_size; | |
7476 | current_frame_info.fp_reg_size = fp_reg_size; | |
86735b02 | 7477 | current_frame_info.gmask = gmask; |
c819be5b | 7478 | current_frame_info.fmask = fmask; |
86735b02 | 7479 | current_frame_info.reg_offset = reg_offset; |
c819be5b JW |
7480 | current_frame_info.initialized = reload_completed; |
7481 | ||
c819be5b JW |
7482 | /* Ok, we're done. */ |
7483 | return total_size; | |
7484 | } | |
7485 | \f | |
86735b02 DE |
7486 | /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset |
7487 | OFFSET. | |
7488 | ||
7489 | BASE_REG must be 8 byte aligned. This allows us to test OFFSET for | |
7490 | appropriate alignment and use DOUBLEWORD_OP when we can. We assume | |
7491 | [BASE_REG+OFFSET] will always be a valid address. | |
7492 | ||
7493 | WORD_OP is either "st" for save, "ld" for restore. | |
7494 | DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ | |
c819be5b | 7495 | |
6a151f87 EB |
7496 | static void |
7497 | sparc_flat_save_restore (FILE *file, const char *base_reg, int offset, | |
7498 | unsigned long gmask, unsigned long fmask, | |
7499 | const char *word_op, const char *doubleword_op, | |
7500 | HOST_WIDE_INT base_offset) | |
c819be5b JW |
7501 | { |
7502 | int regno; | |
c819be5b | 7503 | |
86735b02 DE |
7504 | if (gmask == 0 && fmask == 0) |
7505 | return; | |
c819be5b | 7506 | |
86735b02 DE |
7507 | /* Save registers starting from high to low. We've already saved the |
7508 | previous frame pointer and previous return address for the debugger's | |
7509 | sake. The debugger allows us to not need a nop in the epilog if at least | |
7510 | one register is reloaded in addition to return address. */ | |
c819be5b | 7511 | |
86735b02 | 7512 | if (gmask) |
c819be5b JW |
7513 | { |
7514 | for (regno = 1; regno <= 31; regno++) | |
7515 | { | |
86735b02 | 7516 | if ((gmask & (1L << regno)) != 0) |
c819be5b | 7517 | { |
86735b02 | 7518 | if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) |
c819be5b | 7519 | { |
86735b02 DE |
7520 | /* We can save two registers in a row. If we're not at a |
7521 | double word boundary, move to one. | |
7522 | sparc_flat_compute_frame_size ensures there's room to do | |
7523 | this. */ | |
7524 | if (offset % 8 != 0) | |
7525 | offset += UNITS_PER_WORD; | |
7526 | ||
c819be5b | 7527 | if (word_op[0] == 's') |
c53aa195 | 7528 | { |
e0d80184 | 7529 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
7530 | doubleword_op, reg_names[regno], |
7531 | base_reg, offset); | |
0021b564 | 7532 | if (dwarf2out_do_frame ()) |
c53aa195 | 7533 | { |
96987e96 | 7534 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
7535 | dwarf2out_reg_save (l, regno, offset + base_offset); |
7536 | dwarf2out_reg_save | |
7537 | (l, regno+1, offset+base_offset + UNITS_PER_WORD); | |
7538 | } | |
c53aa195 | 7539 | } |
c819be5b | 7540 | else |
e0d80184 | 7541 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 7542 | doubleword_op, base_reg, offset, |
c819be5b JW |
7543 | reg_names[regno]); |
7544 | ||
86735b02 | 7545 | offset += 2 * UNITS_PER_WORD; |
c819be5b JW |
7546 | regno++; |
7547 | } | |
7548 | else | |
7549 | { | |
7550 | if (word_op[0] == 's') | |
c53aa195 | 7551 | { |
e0d80184 | 7552 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
7553 | word_op, reg_names[regno], |
7554 | base_reg, offset); | |
0021b564 | 7555 | if (dwarf2out_do_frame ()) |
c53aa195 | 7556 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 7557 | } |
c819be5b | 7558 | else |
e0d80184 | 7559 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 7560 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 7561 | |
86735b02 | 7562 | offset += UNITS_PER_WORD; |
c819be5b JW |
7563 | } |
7564 | } | |
7565 | } | |
7566 | } | |
7567 | ||
7568 | if (fmask) | |
7569 | { | |
7570 | for (regno = 32; regno <= 63; regno++) | |
7571 | { | |
7572 | if ((fmask & (1L << (regno - 32))) != 0) | |
7573 | { | |
7574 | if (word_op[0] == 's') | |
c53aa195 | 7575 | { |
e0d80184 | 7576 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
7577 | word_op, reg_names[regno], |
7578 | base_reg, offset); | |
0021b564 | 7579 | if (dwarf2out_do_frame ()) |
c53aa195 | 7580 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 7581 | } |
c819be5b | 7582 | else |
e0d80184 | 7583 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 7584 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 7585 | |
86735b02 | 7586 | offset += UNITS_PER_WORD; |
c819be5b JW |
7587 | } |
7588 | } | |
7589 | } | |
7590 | } | |
7591 | \f | |
7592 | /* Set up the stack and frame (if desired) for the function. */ | |
7593 | ||
08c148a8 | 7594 | static void |
fc27d102 | 7595 | sparc_flat_function_prologue (FILE *file, HOST_WIDE_INT size) |
c819be5b | 7596 | { |
99f44eba | 7597 | const char *sp_str = reg_names[STACK_POINTER_REGNUM]; |
86735b02 | 7598 | unsigned long gmask = current_frame_info.gmask; |
a07c1915 | 7599 | |
1cb36a98 RH |
7600 | sparc_output_scratch_registers (file); |
7601 | ||
c6aa9ce1 | 7602 | /* This is only for the human reader. */ |
bf62bbf1 | 7603 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
6a151f87 EB |
7604 | fprintf (file, "\t%s# vars= "HOST_WIDE_INT_PRINT_DEC", " |
7605 | "regs= %d/%d, args= %d, extra= %d\n", | |
bf62bbf1 | 7606 | ASM_COMMENT_START, |
86735b02 DE |
7607 | current_frame_info.var_size, |
7608 | current_frame_info.gp_reg_size / 4, | |
9f8b85b8 | 7609 | current_frame_info.fp_reg_size / 4, |
86735b02 DE |
7610 | current_function_outgoing_args_size, |
7611 | current_frame_info.extra_size); | |
c819be5b JW |
7612 | |
7613 | size = SPARC_STACK_ALIGN (size); | |
86735b02 DE |
7614 | size = (! current_frame_info.initialized |
7615 | ? sparc_flat_compute_frame_size (size) | |
7616 | : current_frame_info.total_size); | |
c819be5b | 7617 | |
86735b02 DE |
7618 | /* These cases shouldn't happen. Catch them now. */ |
7619 | if (size == 0 && (gmask || current_frame_info.fmask)) | |
7620 | abort (); | |
c819be5b | 7621 | |
86735b02 DE |
7622 | /* Allocate our stack frame by decrementing %sp. |
7623 | At present, the only algorithm gdb can use to determine if this is a | |
7624 | flat frame is if we always set %i7 if we set %sp. This can be optimized | |
7625 | in the future by putting in some sort of debugging information that says | |
7626 | this is a `flat' function. However, there is still the case of debugging | |
7627 | code without such debugging information (including cases where most fns | |
7628 | have such info, but there is one that doesn't). So, always do this now | |
7629 | so we don't get a lot of code out there that gdb can't handle. | |
7630 | If the frame pointer isn't needn't then that's ok - gdb won't be able to | |
7631 | distinguish us from a non-flat function but there won't (and shouldn't) | |
7632 | be any differences anyway. The return pc is saved (if necessary) right | |
7633 | after %i7 so gdb won't have to look too far to find it. */ | |
7634 | if (size > 0) | |
c819be5b | 7635 | { |
6a151f87 | 7636 | int reg_offset = current_frame_info.reg_offset; |
563c12b0 | 7637 | const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; |
83182544 | 7638 | static const char *const t1_str = "%g1"; |
86735b02 DE |
7639 | |
7640 | /* Things get a little tricky if local variables take up more than ~4096 | |
7641 | bytes and outgoing arguments take up more than ~4096 bytes. When that | |
7642 | happens, the register save area can't be accessed from either end of | |
7643 | the frame. Handle this by decrementing %sp to the start of the gp | |
7644 | register save area, save the regs, update %i7, and then set %sp to its | |
7645 | final value. Given that we only have one scratch register to play | |
7646 | with it is the cheapest solution, and it helps gdb out as it won't | |
7647 | slow down recognition of flat functions. | |
7648 | Don't change the order of insns emitted here without checking with | |
7649 | the gdb folk first. */ | |
7650 | ||
ddd5a7c1 | 7651 | /* Is the entire register save area offsettable from %sp? */ |
6a151f87 | 7652 | if (reg_offset < 4096 - 64 * UNITS_PER_WORD) |
86735b02 DE |
7653 | { |
7654 | if (size <= 4096) | |
7655 | { | |
6a151f87 EB |
7656 | fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n", |
7657 | sp_str, size, sp_str); | |
563c12b0 | 7658 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7659 | { |
e0d80184 | 7660 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 7661 | fp_str, sp_str, reg_offset); |
6a151f87 EB |
7662 | fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s" |
7663 | "\t%s# set up frame pointer\n", | |
7664 | sp_str, size, fp_str, ASM_COMMENT_START); | |
86735b02 DE |
7665 | reg_offset += 4; |
7666 | } | |
7667 | } | |
7668 | else | |
7669 | { | |
6a151f87 EB |
7670 | build_big_number (file, size, t1_str); |
7671 | fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str); | |
563c12b0 | 7672 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7673 | { |
e0d80184 | 7674 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 7675 | fp_str, sp_str, reg_offset); |
e0d80184 | 7676 | fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
bf62bbf1 | 7677 | sp_str, t1_str, fp_str, ASM_COMMENT_START); |
86735b02 DE |
7678 | reg_offset += 4; |
7679 | } | |
7680 | } | |
0021b564 | 7681 | if (dwarf2out_do_frame ()) |
c53aa195 | 7682 | { |
96987e96 | 7683 | char *l = dwarf2out_cfi_label (); |
563c12b0 | 7684 | if (gmask & HARD_FRAME_POINTER_MASK) |
c53aa195 | 7685 | { |
563c12b0 | 7686 | dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, |
c53aa195 | 7687 | reg_offset - 4 - size); |
563c12b0 | 7688 | dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); |
c53aa195 JM |
7689 | } |
7690 | else | |
7691 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size); | |
7692 | } | |
86735b02 DE |
7693 | if (gmask & RETURN_ADDR_MASK) |
7694 | { | |
e0d80184 | 7695 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 7696 | reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); |
0021b564 | 7697 | if (dwarf2out_do_frame ()) |
c53aa195 | 7698 | dwarf2out_return_save ("", reg_offset - size); |
86735b02 DE |
7699 | reg_offset += 4; |
7700 | } | |
7701 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
563c12b0 | 7702 | gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), |
86735b02 | 7703 | current_frame_info.fmask, |
84e884e9 | 7704 | "st", "std", -size); |
86735b02 | 7705 | } |
c819be5b | 7706 | else |
86735b02 DE |
7707 | { |
7708 | /* Subtract %sp in two steps, but make sure there is always a | |
6a151f87 EB |
7709 | 64-byte register save area, and %sp is properly aligned. */ |
7710 | ||
86735b02 | 7711 | /* Amount to decrement %sp by, the first time. */ |
6a151f87 EB |
7712 | HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16; |
7713 | ||
7714 | /* Amount to decrement %sp by, the second time. */ | |
7715 | HOST_WIDE_INT size2 = size - size1; | |
7716 | ||
7717 | /* Offset to register save area from %sp after first decrement. */ | |
7718 | int offset = (int)(size1 - (size - reg_offset)); | |
86735b02 DE |
7719 | |
7720 | if (size1 <= 4096) | |
7721 | { | |
6a151f87 EB |
7722 | fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n", |
7723 | sp_str, size1, sp_str); | |
563c12b0 | 7724 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7725 | { |
6a151f87 EB |
7726 | fprintf (file, "\tst\t%s, [%s+%d]\n" |
7727 | "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s" | |
7728 | "\t%s# set up frame pointer\n", | |
7729 | fp_str, sp_str, offset, sp_str, size1, | |
0d587737 | 7730 | fp_str, ASM_COMMENT_START); |
86735b02 DE |
7731 | offset += 4; |
7732 | } | |
7733 | } | |
7734 | else | |
7735 | { | |
6a151f87 EB |
7736 | build_big_number (file, size1, t1_str); |
7737 | fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str); | |
563c12b0 | 7738 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7739 | { |
6a151f87 EB |
7740 | fprintf (file, "\tst\t%s, [%s+%d]\n" |
7741 | "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", | |
7742 | fp_str, sp_str, offset, sp_str, t1_str, | |
0d587737 | 7743 | fp_str, ASM_COMMENT_START); |
86735b02 DE |
7744 | offset += 4; |
7745 | } | |
7746 | } | |
0021b564 | 7747 | if (dwarf2out_do_frame ()) |
c53aa195 | 7748 | { |
96987e96 | 7749 | char *l = dwarf2out_cfi_label (); |
563c12b0 | 7750 | if (gmask & HARD_FRAME_POINTER_MASK) |
c53aa195 | 7751 | { |
563c12b0 | 7752 | dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, |
c53aa195 | 7753 | offset - 4 - size1); |
563c12b0 | 7754 | dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); |
c53aa195 JM |
7755 | } |
7756 | else | |
7757 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1); | |
7758 | } | |
86735b02 DE |
7759 | if (gmask & RETURN_ADDR_MASK) |
7760 | { | |
e0d80184 | 7761 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
6a151f87 | 7762 | reg_names[RETURN_ADDR_REGNUM], sp_str, offset); |
0021b564 | 7763 | if (dwarf2out_do_frame ()) |
c53aa195 JM |
7764 | /* offset - size1 == reg_offset - size |
7765 | if reg_offset were updated above like offset. */ | |
7766 | dwarf2out_return_save ("", offset - size1); | |
86735b02 DE |
7767 | offset += 4; |
7768 | } | |
7769 | sparc_flat_save_restore (file, sp_str, offset, | |
563c12b0 | 7770 | gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), |
86735b02 | 7771 | current_frame_info.fmask, |
84e884e9 | 7772 | "st", "std", -size1); |
6a151f87 EB |
7773 | if (size2 <= 4096) |
7774 | fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n", | |
7775 | sp_str, size2, sp_str); | |
7776 | else | |
7777 | { | |
7778 | build_big_number (file, size2, t1_str); | |
7779 | fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str); | |
7780 | } | |
0021b564 | 7781 | if (dwarf2out_do_frame ()) |
563c12b0 | 7782 | if (! (gmask & HARD_FRAME_POINTER_MASK)) |
c53aa195 | 7783 | dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size); |
86735b02 | 7784 | } |
c819be5b | 7785 | } |
c6aa9ce1 | 7786 | |
bf62bbf1 | 7787 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
c819be5b JW |
7788 | } |
7789 | \f | |
7790 | /* Do any necessary cleanup after a function to restore stack, frame, | |
80ffc95e | 7791 | and regs. */ |
c819be5b | 7792 | |
08c148a8 | 7793 | static void |
fc27d102 | 7794 | sparc_flat_function_epilogue (FILE *file, HOST_WIDE_INT size) |
c819be5b | 7795 | { |
c819be5b JW |
7796 | rtx epilogue_delay = current_function_epilogue_delay_list; |
7797 | int noepilogue = FALSE; | |
c819be5b | 7798 | |
c6aa9ce1 | 7799 | /* This is only for the human reader. */ |
bf62bbf1 | 7800 | fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START); |
c6aa9ce1 | 7801 | |
c819be5b JW |
7802 | /* The epilogue does not depend on any registers, but the stack |
7803 | registers, so we assume that if we have 1 pending nop, it can be | |
7804 | ignored, and 2 it must be filled (2 nops occur for integer | |
7805 | multiply and divide). */ | |
7806 | ||
7807 | size = SPARC_STACK_ALIGN (size); | |
86735b02 | 7808 | size = (!current_frame_info.initialized |
c6aa9ce1 | 7809 | ? sparc_flat_compute_frame_size (size) |
c819be5b JW |
7810 | : current_frame_info.total_size); |
7811 | ||
86735b02 | 7812 | if (size == 0 && epilogue_delay == 0) |
c819be5b JW |
7813 | { |
7814 | rtx insn = get_last_insn (); | |
7815 | ||
7816 | /* If the last insn was a BARRIER, we don't have to write any code | |
7817 | because a jump (aka return) was put there. */ | |
7818 | if (GET_CODE (insn) == NOTE) | |
7819 | insn = prev_nonnote_insn (insn); | |
7820 | if (insn && GET_CODE (insn) == BARRIER) | |
7821 | noepilogue = TRUE; | |
7822 | } | |
7823 | ||
7824 | if (!noepilogue) | |
7825 | { | |
6a151f87 EB |
7826 | int reg_offset = current_frame_info.reg_offset; |
7827 | int reg_offset1; | |
27c38fbe | 7828 | const char *const sp_str = reg_names[STACK_POINTER_REGNUM]; |
563c12b0 | 7829 | const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; |
83182544 | 7830 | static const char *const t1_str = "%g1"; |
86735b02 | 7831 | |
c819be5b JW |
7832 | /* In the reload sequence, we don't need to fill the load delay |
7833 | slots for most of the loads, also see if we can fill the final | |
7834 | delay slot if not otherwise filled by the reload sequence. */ | |
7835 | ||
6a151f87 EB |
7836 | if (size > 4096) |
7837 | build_big_number (file, size, t1_str); | |
c819be5b JW |
7838 | |
7839 | if (frame_pointer_needed) | |
7840 | { | |
6a151f87 | 7841 | if (size > 4096) |
e0d80184 | 7842 | fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n", |
bf62bbf1 | 7843 | fp_str, t1_str, sp_str, ASM_COMMENT_START); |
c819be5b | 7844 | else |
6a151f87 EB |
7845 | fprintf (file,"\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s" |
7846 | "\t\t%s# sp not trusted here\n", | |
7847 | fp_str, size, sp_str, ASM_COMMENT_START); | |
c819be5b JW |
7848 | } |
7849 | ||
ddd5a7c1 | 7850 | /* Is the entire register save area offsettable from %sp? */ |
6a151f87 | 7851 | if (reg_offset < 4096 - 64 * UNITS_PER_WORD) |
86735b02 | 7852 | { |
6a151f87 | 7853 | reg_offset1 = 0; |
86735b02 DE |
7854 | } |
7855 | else | |
7856 | { | |
7857 | /* Restore %sp in two steps, but make sure there is always a | |
6a151f87 EB |
7858 | 64-byte register save area, and %sp is properly aligned. */ |
7859 | ||
86735b02 | 7860 | /* Amount to increment %sp by, the first time. */ |
6a151f87 EB |
7861 | reg_offset1 = ((reg_offset - 64 - 16) + 15) & -16; |
7862 | ||
86735b02 | 7863 | /* Offset to register save area from %sp. */ |
6a151f87 | 7864 | reg_offset = reg_offset1 - reg_offset; |
86735b02 | 7865 | |
6a151f87 EB |
7866 | if (reg_offset1 > 4096) |
7867 | { | |
7868 | build_big_number (file, reg_offset1, t1_str); | |
7869 | fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); | |
7870 | } | |
7871 | else | |
7872 | fprintf (file, "\tsub\t%s, -%d, %s\n", sp_str, reg_offset1, sp_str); | |
86735b02 DE |
7873 | } |
7874 | ||
7875 | /* We must restore the frame pointer and return address reg first | |
7876 | because they are treated specially by the prologue output code. */ | |
563c12b0 | 7877 | if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7878 | { |
e0d80184 | 7879 | fprintf (file, "\tld\t[%s+%d], %s\n", |
6a151f87 | 7880 | sp_str, reg_offset, fp_str); |
86735b02 DE |
7881 | reg_offset += 4; |
7882 | } | |
7883 | if (current_frame_info.gmask & RETURN_ADDR_MASK) | |
7884 | { | |
e0d80184 | 7885 | fprintf (file, "\tld\t[%s+%d], %s\n", |
6a151f87 | 7886 | sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]); |
86735b02 DE |
7887 | reg_offset += 4; |
7888 | } | |
7889 | ||
7890 | /* Restore any remaining saved registers. */ | |
7891 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
563c12b0 | 7892 | current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), |
86735b02 | 7893 | current_frame_info.fmask, |
c53aa195 | 7894 | "ld", "ldd", 0); |
86735b02 DE |
7895 | |
7896 | /* If we had to increment %sp in two steps, record it so the second | |
7897 | restoration in the epilogue finishes up. */ | |
6a151f87 | 7898 | if (reg_offset1 > 0) |
86735b02 | 7899 | { |
6a151f87 EB |
7900 | size -= reg_offset1; |
7901 | if (size > 4096) | |
7902 | build_big_number (file, size, t1_str); | |
86735b02 | 7903 | } |
c819be5b | 7904 | |
c819be5b | 7905 | if (current_function_returns_struct) |
e0d80184 | 7906 | fprintf (file, "\tjmp\t%%o7+12\n"); |
c819be5b JW |
7907 | else |
7908 | fprintf (file, "\tretl\n"); | |
7909 | ||
7910 | /* If the only register saved is the return address, we need a | |
7911 | nop, unless we have an instruction to put into it. Otherwise | |
7912 | we don't since reloading multiple registers doesn't reference | |
7913 | the register being loaded. */ | |
7914 | ||
7915 | if (epilogue_delay) | |
7916 | { | |
86735b02 | 7917 | if (size) |
c819be5b | 7918 | abort (); |
5cfc5f84 | 7919 | final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1, NULL); |
c819be5b JW |
7920 | } |
7921 | ||
6a151f87 | 7922 | else if (size > 4096) |
e0d80184 | 7923 | fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); |
c819be5b | 7924 | |
86735b02 | 7925 | else if (size > 0) |
6a151f87 EB |
7926 | fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n", |
7927 | sp_str, size, sp_str); | |
c819be5b JW |
7928 | |
7929 | else | |
7930 | fprintf (file, "\tnop\n"); | |
7931 | } | |
7932 | ||
7933 | /* Reset state info for each function. */ | |
7934 | current_frame_info = zero_frame_info; | |
e0d80184 DM |
7935 | |
7936 | sparc_output_deferred_case_vectors (); | |
c819be5b JW |
7937 | } |
7938 | \f | |
7939 | /* Define the number of delay slots needed for the function epilogue. | |
7940 | ||
7941 | On the sparc, we need a slot if either no stack has been allocated, | |
7942 | or the only register saved is the return register. */ | |
7943 | ||
7944 | int | |
fc27d102 | 7945 | sparc_flat_epilogue_delay_slots (void) |
c819be5b JW |
7946 | { |
7947 | if (!current_frame_info.initialized) | |
c6aa9ce1 | 7948 | (void) sparc_flat_compute_frame_size (get_frame_size ()); |
c819be5b JW |
7949 | |
7950 | if (current_frame_info.total_size == 0) | |
7951 | return 1; | |
7952 | ||
c819be5b JW |
7953 | return 0; |
7954 | } | |
7955 | ||
51f26c45 | 7956 | /* Return true if TRIAL is a valid insn for the epilogue delay slot. |
c819be5b JW |
7957 | Any single length instruction which doesn't reference the stack or frame |
7958 | pointer is OK. */ | |
7959 | ||
7960 | int | |
fc27d102 | 7961 | sparc_flat_eligible_for_epilogue_delay (rtx trial, int slot ATTRIBUTE_UNUSED) |
c819be5b | 7962 | { |
c4ce6853 DE |
7963 | rtx pat = PATTERN (trial); |
7964 | ||
7965 | if (get_attr_length (trial) != 1) | |
7966 | return 0; | |
7967 | ||
c4ce6853 DE |
7968 | if (! reg_mentioned_p (stack_pointer_rtx, pat) |
7969 | && ! reg_mentioned_p (frame_pointer_rtx, pat)) | |
c819be5b | 7970 | return 1; |
c4ce6853 | 7971 | |
c819be5b JW |
7972 | return 0; |
7973 | } | |
dbb54862 JW |
7974 | \f |
7975 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
7976 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
7977 | ||
8947065c | 7978 | static int |
fc27d102 | 7979 | supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
dbb54862 JW |
7980 | { |
7981 | enum attr_type insn_type; | |
7982 | ||
7983 | if (! recog_memoized (insn)) | |
7984 | return 0; | |
7985 | ||
7986 | insn_type = get_attr_type (insn); | |
7987 | ||
7988 | if (REG_NOTE_KIND (link) == 0) | |
7989 | { | |
7990 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7991 | cycles later. */ | |
7992 | ||
7993 | /* if a load, then the dependence must be on the memory address; | |
3bc8b61e DM |
7994 | add an extra "cycle". Note that the cost could be two cycles |
7995 | if the reg was written late in an instruction group; we ca not tell | |
dbb54862 JW |
7996 | here. */ |
7997 | if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) | |
7998 | return cost + 3; | |
7999 | ||
8000 | /* Get the delay only if the address of the store is the dependence. */ | |
8001 | if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) | |
8002 | { | |
8003 | rtx pat = PATTERN(insn); | |
8004 | rtx dep_pat = PATTERN (dep_insn); | |
8005 | ||
8006 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
3bc8b61e | 8007 | return cost; /* This should not happen! */ |
dbb54862 JW |
8008 | |
8009 | /* The dependency between the two instructions was on the data that | |
8010 | is being stored. Assume that this implies that the address of the | |
8011 | store is not dependent. */ | |
8012 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
8013 | return cost; | |
8014 | ||
8015 | return cost + 3; /* An approximation. */ | |
8016 | } | |
8017 | ||
8018 | /* A shift instruction cannot receive its data from an instruction | |
8019 | in the same cycle; add a one cycle penalty. */ | |
8020 | if (insn_type == TYPE_SHIFT) | |
8021 | return cost + 3; /* Split before cascade into shift. */ | |
8022 | } | |
8023 | else | |
8024 | { | |
8025 | /* Anti- or output- dependency; DEP_INSN reads/writes a register that | |
8026 | INSN writes some cycles later. */ | |
8027 | ||
8028 | /* These are only significant for the fpu unit; writing a fp reg before | |
8029 | the fpu has finished with it stalls the processor. */ | |
8030 | ||
8031 | /* Reusing an integer register causes no problems. */ | |
8032 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
8033 | return 0; | |
8034 | } | |
8035 | ||
8036 | return cost; | |
8037 | } | |
bfd6bc60 | 8038 | |
8947065c | 8039 | static int |
fc27d102 | 8040 | hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
8947065c RH |
8041 | { |
8042 | enum attr_type insn_type, dep_type; | |
8043 | rtx pat = PATTERN(insn); | |
8044 | rtx dep_pat = PATTERN (dep_insn); | |
8045 | ||
8046 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) | |
8047 | return cost; | |
8048 | ||
8049 | insn_type = get_attr_type (insn); | |
8050 | dep_type = get_attr_type (dep_insn); | |
8051 | ||
8052 | switch (REG_NOTE_KIND (link)) | |
8053 | { | |
8054 | case 0: | |
8055 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
8056 | cycles later. */ | |
8057 | ||
8058 | switch (insn_type) | |
8059 | { | |
8060 | case TYPE_STORE: | |
8061 | case TYPE_FPSTORE: | |
80ffc95e | 8062 | /* Get the delay iff the address of the store is the dependence. */ |
8947065c RH |
8063 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) |
8064 | return cost; | |
8065 | ||
8066 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
8067 | return cost; | |
8068 | return cost + 3; | |
8069 | ||
8070 | case TYPE_LOAD: | |
8071 | case TYPE_SLOAD: | |
8072 | case TYPE_FPLOAD: | |
8073 | /* If a load, then the dependence must be on the memory address. If | |
8074 | the addresses aren't equal, then it might be a false dependency */ | |
8075 | if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) | |
8076 | { | |
8077 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET | |
8078 | || GET_CODE (SET_DEST (dep_pat)) != MEM | |
8079 | || GET_CODE (SET_SRC (pat)) != MEM | |
8080 | || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), | |
8081 | XEXP (SET_SRC (pat), 0))) | |
8082 | return cost + 2; | |
8083 | ||
8084 | return cost + 8; | |
8085 | } | |
8086 | break; | |
8087 | ||
8088 | case TYPE_BRANCH: | |
8089 | /* Compare to branch latency is 0. There is no benefit from | |
8090 | separating compare and branch. */ | |
8091 | if (dep_type == TYPE_COMPARE) | |
8092 | return 0; | |
8093 | /* Floating point compare to branch latency is less than | |
8094 | compare to conditional move. */ | |
8095 | if (dep_type == TYPE_FPCMP) | |
8096 | return cost - 1; | |
8097 | break; | |
3bb5de61 KG |
8098 | default: |
8099 | break; | |
8947065c RH |
8100 | } |
8101 | break; | |
8102 | ||
8103 | case REG_DEP_ANTI: | |
80ffc95e | 8104 | /* Anti-dependencies only penalize the fpu unit. */ |
8947065c RH |
8105 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) |
8106 | return 0; | |
8107 | break; | |
8108 | ||
8109 | default: | |
8110 | break; | |
8111 | } | |
8112 | ||
8113 | return cost; | |
8114 | } | |
8115 | ||
c237e94a | 8116 | static int |
fc27d102 | 8117 | sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost) |
8947065c RH |
8118 | { |
8119 | switch (sparc_cpu) | |
8120 | { | |
8121 | case PROCESSOR_SUPERSPARC: | |
8122 | cost = supersparc_adjust_cost (insn, link, dep, cost); | |
8123 | break; | |
8124 | case PROCESSOR_HYPERSPARC: | |
8125 | case PROCESSOR_SPARCLITE86X: | |
8126 | cost = hypersparc_adjust_cost (insn, link, dep, cost); | |
8127 | break; | |
8947065c RH |
8128 | default: |
8129 | break; | |
8130 | } | |
8131 | return cost; | |
8132 | } | |
8133 | ||
fae15c93 | 8134 | static void |
fc27d102 KG |
8135 | sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED, |
8136 | int sched_verbose ATTRIBUTE_UNUSED, | |
8137 | int max_ready ATTRIBUTE_UNUSED) | |
3bc8b61e | 8138 | { |
3bc8b61e | 8139 | } |
fae15c93 | 8140 | |
3bc8b61e | 8141 | static int |
fc27d102 | 8142 | sparc_use_dfa_pipeline_interface (void) |
3bc8b61e | 8143 | { |
fae15c93 VM |
8144 | if ((1 << sparc_cpu) & |
8145 | ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) | | |
8146 | (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | | |
8147 | (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) | | |
8148 | (1 << PROCESSOR_ULTRASPARC3))) | |
8149 | return 1; | |
3bc8b61e DM |
8150 | return 0; |
8151 | } | |
8152 | ||
fae15c93 | 8153 | static int |
fc27d102 | 8154 | sparc_use_sched_lookahead (void) |
fae15c93 VM |
8155 | { |
8156 | if (sparc_cpu == PROCESSOR_ULTRASPARC | |
8157 | || sparc_cpu == PROCESSOR_ULTRASPARC3) | |
8158 | return 4; | |
8159 | if ((1 << sparc_cpu) & | |
8160 | ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | | |
8161 | (1 << PROCESSOR_SPARCLITE86X))) | |
8162 | return 3; | |
3bc8b61e DM |
8163 | return 0; |
8164 | } | |
8165 | ||
fae15c93 | 8166 | static int |
fc27d102 | 8167 | sparc_issue_rate (void) |
bfd6bc60 JC |
8168 | { |
8169 | switch (sparc_cpu) | |
8170 | { | |
fae15c93 VM |
8171 | default: |
8172 | return 1; | |
8173 | case PROCESSOR_V9: | |
284d86e9 | 8174 | /* Assume V9 processors are capable of at least dual-issue. */ |
bfd6bc60 | 8175 | return 2; |
fae15c93 VM |
8176 | case PROCESSOR_SUPERSPARC: |
8177 | return 3; | |
393049a9 RH |
8178 | case PROCESSOR_HYPERSPARC: |
8179 | case PROCESSOR_SPARCLITE86X: | |
8180 | return 2; | |
fae15c93 VM |
8181 | case PROCESSOR_ULTRASPARC: |
8182 | case PROCESSOR_ULTRASPARC3: | |
8183 | return 4; | |
bfd6bc60 JC |
8184 | } |
8185 | } | |
284d86e9 JC |
8186 | |
8187 | static int | |
fc27d102 | 8188 | set_extends (rtx insn) |
284d86e9 JC |
8189 | { |
8190 | register rtx pat = PATTERN (insn); | |
8191 | ||
8192 | switch (GET_CODE (SET_SRC (pat))) | |
8193 | { | |
80ffc95e | 8194 | /* Load and some shift instructions zero extend. */ |
284d86e9 JC |
8195 | case MEM: |
8196 | case ZERO_EXTEND: | |
8197 | /* sethi clears the high bits */ | |
8198 | case HIGH: | |
8199 | /* LO_SUM is used with sethi. sethi cleared the high | |
8200 | bits and the values used with lo_sum are positive */ | |
8201 | case LO_SUM: | |
284d86e9 JC |
8202 | /* Store flag stores 0 or 1 */ |
8203 | case LT: case LTU: | |
8204 | case GT: case GTU: | |
8205 | case LE: case LEU: | |
8206 | case GE: case GEU: | |
8207 | case EQ: | |
8208 | case NE: | |
8209 | return 1; | |
8210 | case AND: | |
8211 | { | |
4df1190a | 8212 | rtx op0 = XEXP (SET_SRC (pat), 0); |
284d86e9 JC |
8213 | rtx op1 = XEXP (SET_SRC (pat), 1); |
8214 | if (GET_CODE (op1) == CONST_INT) | |
8215 | return INTVAL (op1) >= 0; | |
4df1190a JJ |
8216 | if (GET_CODE (op0) != REG) |
8217 | return 0; | |
8218 | if (sparc_check_64 (op0, insn) == 1) | |
284d86e9 | 8219 | return 1; |
4df1190a JJ |
8220 | return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); |
8221 | } | |
8222 | case IOR: | |
8223 | case XOR: | |
8224 | { | |
8225 | rtx op0 = XEXP (SET_SRC (pat), 0); | |
8226 | rtx op1 = XEXP (SET_SRC (pat), 1); | |
8227 | if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) | |
8228 | return 0; | |
8229 | if (GET_CODE (op1) == CONST_INT) | |
8230 | return INTVAL (op1) >= 0; | |
8231 | return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); | |
284d86e9 | 8232 | } |
284d86e9 JC |
8233 | case LSHIFTRT: |
8234 | return GET_MODE (SET_SRC (pat)) == SImode; | |
80ffc95e | 8235 | /* Positive integers leave the high bits zero. */ |
284d86e9 | 8236 | case CONST_DOUBLE: |
4df1190a | 8237 | return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000); |
284d86e9 | 8238 | case CONST_INT: |
4df1190a | 8239 | return ! (INTVAL (SET_SRC (pat)) & 0x80000000); |
284d86e9 JC |
8240 | case ASHIFTRT: |
8241 | case SIGN_EXTEND: | |
8242 | return - (GET_MODE (SET_SRC (pat)) == SImode); | |
4df1190a JJ |
8243 | case REG: |
8244 | return sparc_check_64 (SET_SRC (pat), insn); | |
284d86e9 JC |
8245 | default: |
8246 | return 0; | |
8247 | } | |
8248 | } | |
8249 | ||
80ffc95e | 8250 | /* We _ought_ to have only one kind per function, but... */ |
e2500fed GK |
8251 | static GTY(()) rtx sparc_addr_diff_list; |
8252 | static GTY(()) rtx sparc_addr_list; | |
e0d80184 DM |
8253 | |
8254 | void | |
fc27d102 | 8255 | sparc_defer_case_vector (rtx lab, rtx vec, int diff) |
e0d80184 DM |
8256 | { |
8257 | vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); | |
8258 | if (diff) | |
8259 | sparc_addr_diff_list | |
8260 | = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); | |
8261 | else | |
8262 | sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); | |
8263 | } | |
8264 | ||
8265 | static void | |
fc27d102 | 8266 | sparc_output_addr_vec (rtx vec) |
e0d80184 DM |
8267 | { |
8268 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
8269 | int idx, vlen = XVECLEN (body, 0); | |
8270 | ||
d1accaa3 JJ |
8271 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
8272 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
8273 | #endif | |
8274 | ||
e0d80184 DM |
8275 | #ifdef ASM_OUTPUT_CASE_LABEL |
8276 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
8277 | NEXT_INSN (lab)); | |
8278 | #else | |
4977bab6 | 8279 | (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); |
e0d80184 DM |
8280 | #endif |
8281 | ||
8282 | for (idx = 0; idx < vlen; idx++) | |
8283 | { | |
8284 | ASM_OUTPUT_ADDR_VEC_ELT | |
8285 | (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); | |
8286 | } | |
d1accaa3 JJ |
8287 | |
8288 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
8289 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
8290 | #endif | |
e0d80184 DM |
8291 | } |
8292 | ||
8293 | static void | |
fc27d102 | 8294 | sparc_output_addr_diff_vec (rtx vec) |
e0d80184 DM |
8295 | { |
8296 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
8297 | rtx base = XEXP (XEXP (body, 0), 0); | |
8298 | int idx, vlen = XVECLEN (body, 1); | |
8299 | ||
d1accaa3 JJ |
8300 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
8301 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
8302 | #endif | |
8303 | ||
e0d80184 DM |
8304 | #ifdef ASM_OUTPUT_CASE_LABEL |
8305 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
8306 | NEXT_INSN (lab)); | |
8307 | #else | |
4977bab6 | 8308 | (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); |
e0d80184 DM |
8309 | #endif |
8310 | ||
8311 | for (idx = 0; idx < vlen; idx++) | |
8312 | { | |
8313 | ASM_OUTPUT_ADDR_DIFF_ELT | |
8314 | (asm_out_file, | |
8315 | body, | |
8316 | CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), | |
8317 | CODE_LABEL_NUMBER (base)); | |
8318 | } | |
d1accaa3 JJ |
8319 | |
8320 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
8321 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
8322 | #endif | |
e0d80184 DM |
8323 | } |
8324 | ||
8325 | static void | |
fc27d102 | 8326 | sparc_output_deferred_case_vectors (void) |
e0d80184 DM |
8327 | { |
8328 | rtx t; | |
d676da68 | 8329 | int align; |
e0d80184 | 8330 | |
f3b8847b DM |
8331 | if (sparc_addr_list == NULL_RTX |
8332 | && sparc_addr_diff_list == NULL_RTX) | |
8333 | return; | |
8334 | ||
e0d80184 DM |
8335 | /* Align to cache line in the function's code section. */ |
8336 | function_section (current_function_decl); | |
d676da68 DM |
8337 | |
8338 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
8339 | if (align > 0) | |
f3b8847b | 8340 | ASM_OUTPUT_ALIGN (asm_out_file, align); |
e0d80184 DM |
8341 | |
8342 | for (t = sparc_addr_list; t ; t = XEXP (t, 1)) | |
8343 | sparc_output_addr_vec (XEXP (t, 0)); | |
8344 | for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) | |
8345 | sparc_output_addr_diff_vec (XEXP (t, 0)); | |
8346 | ||
8347 | sparc_addr_list = sparc_addr_diff_list = NULL_RTX; | |
8348 | } | |
8349 | ||
284d86e9 JC |
8350 | /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are |
8351 | unknown. Return 1 if the high bits are zero, -1 if the register is | |
8352 | sign extended. */ | |
8353 | int | |
fc27d102 | 8354 | sparc_check_64 (rtx x, rtx insn) |
284d86e9 JC |
8355 | { |
8356 | /* If a register is set only once it is safe to ignore insns this | |
8357 | code does not know how to handle. The loop will either recognize | |
8358 | the single set and return the correct value or fail to recognize | |
8359 | it and return 0. */ | |
8360 | int set_once = 0; | |
4df1190a JJ |
8361 | rtx y = x; |
8362 | ||
8363 | if (GET_CODE (x) != REG) | |
8364 | abort (); | |
8365 | ||
8366 | if (GET_MODE (x) == DImode) | |
8367 | y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN); | |
284d86e9 | 8368 | |
4df1190a JJ |
8369 | if (flag_expensive_optimizations |
8370 | && REG_N_SETS (REGNO (y)) == 1) | |
284d86e9 JC |
8371 | set_once = 1; |
8372 | ||
8373 | if (insn == 0) | |
d6f4ec51 KG |
8374 | { |
8375 | if (set_once) | |
8376 | insn = get_last_insn_anywhere (); | |
8377 | else | |
8378 | return 0; | |
8379 | } | |
284d86e9 | 8380 | |
d6f4ec51 | 8381 | while ((insn = PREV_INSN (insn))) |
284d86e9 JC |
8382 | { |
8383 | switch (GET_CODE (insn)) | |
8384 | { | |
8385 | case JUMP_INSN: | |
8386 | case NOTE: | |
8387 | break; | |
8388 | case CODE_LABEL: | |
8389 | case CALL_INSN: | |
8390 | default: | |
8391 | if (! set_once) | |
8392 | return 0; | |
8393 | break; | |
8394 | case INSN: | |
8395 | { | |
8396 | rtx pat = PATTERN (insn); | |
8397 | if (GET_CODE (pat) != SET) | |
8398 | return 0; | |
8399 | if (rtx_equal_p (x, SET_DEST (pat))) | |
4df1190a JJ |
8400 | return set_extends (insn); |
8401 | if (y && rtx_equal_p (y, SET_DEST (pat))) | |
8402 | return set_extends (insn); | |
8403 | if (reg_overlap_mentioned_p (SET_DEST (pat), y)) | |
284d86e9 JC |
8404 | return 0; |
8405 | } | |
8406 | } | |
8407 | } | |
8408 | return 0; | |
8409 | } | |
8410 | ||
01d3224a EB |
8411 | /* Returns assembly code to perform a DImode shift using |
8412 | a 64-bit global or out register on SPARC-V8+. */ | |
284d86e9 | 8413 | char * |
fc27d102 | 8414 | sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode) |
284d86e9 JC |
8415 | { |
8416 | static char asm_code[60]; | |
8417 | ||
01d3224a EB |
8418 | /* The scratch register is only required when the destination |
8419 | register is not a 64-bit global or out register. */ | |
8420 | if (which_alternative != 2) | |
284d86e9 | 8421 | operands[3] = operands[0]; |
01d3224a | 8422 | |
1c8b4e29 EB |
8423 | /* We can only shift by constants <= 63. */ |
8424 | if (GET_CODE (operands[2]) == CONST_INT) | |
8425 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); | |
8426 | ||
c6b0465b JC |
8427 | if (GET_CODE (operands[1]) == CONST_INT) |
8428 | { | |
4df1190a | 8429 | output_asm_insn ("mov\t%1, %3", operands); |
c6b0465b JC |
8430 | } |
8431 | else | |
8432 | { | |
4df1190a | 8433 | output_asm_insn ("sllx\t%H1, 32, %3", operands); |
c6b0465b | 8434 | if (sparc_check_64 (operands[1], insn) <= 0) |
4df1190a JJ |
8435 | output_asm_insn ("srl\t%L1, 0, %L1", operands); |
8436 | output_asm_insn ("or\t%L1, %3, %3", operands); | |
c6b0465b | 8437 | } |
284d86e9 JC |
8438 | |
8439 | strcpy(asm_code, opcode); | |
01d3224a | 8440 | |
284d86e9 | 8441 | if (which_alternative != 2) |
4df1190a | 8442 | return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); |
284d86e9 | 8443 | else |
4df1190a | 8444 | return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"); |
284d86e9 | 8445 | } |
2be15d0f | 8446 | \f |
89a8b315 RH |
8447 | /* Output rtl to increment the profiler label LABELNO |
8448 | for profiling a function entry. */ | |
2be15d0f RH |
8449 | |
8450 | void | |
fc27d102 | 8451 | sparc_profile_hook (int labelno) |
2be15d0f RH |
8452 | { |
8453 | char buf[32]; | |
89a8b315 | 8454 | rtx lab, fun; |
2be15d0f | 8455 | |
89a8b315 RH |
8456 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
8457 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
8458 | fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION); | |
2be15d0f | 8459 | |
eb29ddb6 | 8460 | emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode); |
2be15d0f | 8461 | } |
89a8b315 | 8462 | \f |
ede75ee8 | 8463 | #ifdef OBJECT_FORMAT_ELF |
7c262518 | 8464 | static void |
fc27d102 | 8465 | sparc_elf_asm_named_section (const char *name, unsigned int flags) |
7c262518 | 8466 | { |
201556f0 JJ |
8467 | if (flags & SECTION_MERGE) |
8468 | { | |
8469 | /* entsize cannot be expressed in this section attributes | |
8470 | encoding style. */ | |
8471 | default_elf_asm_named_section (name, flags); | |
8472 | return; | |
8473 | } | |
8474 | ||
7c262518 RH |
8475 | fprintf (asm_out_file, "\t.section\t\"%s\"", name); |
8476 | ||
8477 | if (!(flags & SECTION_DEBUG)) | |
8478 | fputs (",#alloc", asm_out_file); | |
8479 | if (flags & SECTION_WRITE) | |
8480 | fputs (",#write", asm_out_file); | |
2f3321ca EB |
8481 | if (flags & SECTION_TLS) |
8482 | fputs (",#tls", asm_out_file); | |
7c262518 RH |
8483 | if (flags & SECTION_CODE) |
8484 | fputs (",#execinstr", asm_out_file); | |
8485 | ||
8486 | /* ??? Handle SECTION_BSS. */ | |
8487 | ||
8488 | fputc ('\n', asm_out_file); | |
8489 | } | |
ede75ee8 | 8490 | #endif /* OBJECT_FORMAT_ELF */ |
f451b552 | 8491 | |
4977bab6 ZW |
8492 | /* We do not allow sibling calls if -mflat, nor |
8493 | we do not allow indirect calls to be optimized into sibling calls. | |
8494 | ||
8495 | Also, on sparc 32-bit we cannot emit a sibling call when the | |
8496 | current function returns a structure. This is because the "unimp | |
8497 | after call" convention would cause the callee to return to the | |
8498 | wrong place. The generic code already disallows cases where the | |
8499 | function being called returns a structure. | |
8500 | ||
8501 | It may seem strange how this last case could occur. Usually there | |
8502 | is code after the call which jumps to epilogue code which dumps the | |
8503 | return value into the struct return area. That ought to invalidate | |
8504 | the sibling call right? Well, in the c++ case we can end up passing | |
8505 | the pointer to the struct return area to a constructor (which returns | |
8506 | void) and then nothing else happens. Such a sibling call would look | |
8507 | valid without the added check here. */ | |
8508 | static bool | |
fc27d102 | 8509 | sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
4977bab6 ZW |
8510 | { |
8511 | return (decl | |
8512 | && ! TARGET_FLAT | |
8513 | && (TARGET_ARCH64 || ! current_function_returns_struct)); | |
8514 | } | |
c15c90bb ZW |
8515 | \f |
8516 | /* libfunc renaming. */ | |
8517 | #include "config/gofast.h" | |
8518 | ||
8519 | static void | |
8520 | sparc_init_libfuncs (void) | |
8521 | { | |
8522 | if (TARGET_ARCH32) | |
8523 | { | |
8524 | /* Use the subroutines that Sun's library provides for integer | |
8525 | multiply and divide. The `*' prevents an underscore from | |
8526 | being prepended by the compiler. .umul is a little faster | |
8527 | than .mul. */ | |
8528 | set_optab_libfunc (smul_optab, SImode, "*.umul"); | |
8529 | set_optab_libfunc (sdiv_optab, SImode, "*.div"); | |
8530 | set_optab_libfunc (udiv_optab, SImode, "*.udiv"); | |
8531 | set_optab_libfunc (smod_optab, SImode, "*.rem"); | |
8532 | set_optab_libfunc (umod_optab, SImode, "*.urem"); | |
8533 | ||
8534 | /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */ | |
8535 | set_optab_libfunc (add_optab, TFmode, "_Q_add"); | |
8536 | set_optab_libfunc (sub_optab, TFmode, "_Q_sub"); | |
8537 | set_optab_libfunc (neg_optab, TFmode, "_Q_neg"); | |
8538 | set_optab_libfunc (smul_optab, TFmode, "_Q_mul"); | |
8539 | set_optab_libfunc (sdiv_optab, TFmode, "_Q_div"); | |
8540 | ||
8541 | /* We can define the TFmode sqrt optab only if TARGET_FPU. This | |
8542 | is because with soft-float, the SFmode and DFmode sqrt | |
8543 | instructions will be absent, and the compiler will notice and | |
8544 | try to use the TFmode sqrt instruction for calls to the | |
8545 | builtin function sqrt, but this fails. */ | |
8546 | if (TARGET_FPU) | |
8547 | set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt"); | |
8548 | ||
c9034561 ZW |
8549 | set_optab_libfunc (eq_optab, TFmode, "_Q_feq"); |
8550 | set_optab_libfunc (ne_optab, TFmode, "_Q_fne"); | |
8551 | set_optab_libfunc (gt_optab, TFmode, "_Q_fgt"); | |
8552 | set_optab_libfunc (ge_optab, TFmode, "_Q_fge"); | |
8553 | set_optab_libfunc (lt_optab, TFmode, "_Q_flt"); | |
8554 | set_optab_libfunc (le_optab, TFmode, "_Q_fle"); | |
c15c90bb | 8555 | |
85363ca0 ZW |
8556 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq"); |
8557 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq"); | |
8558 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos"); | |
8559 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod"); | |
8560 | ||
8561 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi"); | |
8562 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou"); | |
8563 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq"); | |
c15c90bb ZW |
8564 | |
8565 | if (SUN_CONVERSION_LIBFUNCS) | |
8566 | { | |
85363ca0 ZW |
8567 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); |
8568 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); | |
8569 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); | |
8570 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); | |
c15c90bb ZW |
8571 | } |
8572 | } | |
8573 | if (TARGET_ARCH64) | |
8574 | { | |
8575 | /* In the SPARC 64bit ABI, SImode multiply and divide functions | |
8576 | do not exist in the library. Make sure the compiler does not | |
8577 | emit calls to them by accident. (It should always use the | |
8578 | hardware instructions.) */ | |
8579 | set_optab_libfunc (smul_optab, SImode, 0); | |
8580 | set_optab_libfunc (sdiv_optab, SImode, 0); | |
8581 | set_optab_libfunc (udiv_optab, SImode, 0); | |
8582 | set_optab_libfunc (smod_optab, SImode, 0); | |
8583 | set_optab_libfunc (umod_optab, SImode, 0); | |
8584 | ||
8585 | if (SUN_INTEGER_MULTIPLY_64) | |
8586 | { | |
8587 | set_optab_libfunc (smul_optab, DImode, "__mul64"); | |
8588 | set_optab_libfunc (sdiv_optab, DImode, "__div64"); | |
8589 | set_optab_libfunc (udiv_optab, DImode, "__udiv64"); | |
8590 | set_optab_libfunc (smod_optab, DImode, "__rem64"); | |
8591 | set_optab_libfunc (umod_optab, DImode, "__urem64"); | |
8592 | } | |
8593 | ||
8594 | if (SUN_CONVERSION_LIBFUNCS) | |
8595 | { | |
85363ca0 ZW |
8596 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol"); |
8597 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul"); | |
8598 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol"); | |
8599 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul"); | |
c15c90bb ZW |
8600 | } |
8601 | } | |
4977bab6 | 8602 | |
c15c90bb ZW |
8603 | gofast_maybe_init_libfuncs (); |
8604 | } | |
8605 | \f | |
ae46c4e0 RH |
8606 | /* ??? Similar to the standard section selection, but force reloc-y-ness |
8607 | if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to | |
8608 | pretending PIC always on), but that's what the old code did. */ | |
8609 | ||
8610 | static void | |
fc27d102 | 8611 | sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align) |
ae46c4e0 | 8612 | { |
508bc172 | 8613 | default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align); |
ae46c4e0 RH |
8614 | } |
8615 | ||
b64a1b53 RH |
8616 | /* Use text section for a constant unless we need more alignment than |
8617 | that offers. */ | |
8618 | ||
8619 | static void | |
fc27d102 KG |
8620 | sparc_aout_select_rtx_section (enum machine_mode mode, rtx x, |
8621 | unsigned HOST_WIDE_INT align) | |
b64a1b53 RH |
8622 | { |
8623 | if (align <= MAX_TEXT_ALIGN | |
8624 | && ! (flag_pic && (symbolic_operand (x, mode) | |
8625 | || SUNOS4_SHARED_LIBRARIES))) | |
8626 | readonly_data_section (); | |
8627 | else | |
8628 | data_section (); | |
8629 | } | |
8630 | ||
f451b552 | 8631 | int |
fc27d102 | 8632 | sparc_extra_constraint_check (rtx op, int c, int strict) |
f451b552 DM |
8633 | { |
8634 | int reload_ok_mem; | |
8635 | ||
8636 | if (TARGET_ARCH64 | |
8637 | && (c == 'T' || c == 'U')) | |
8638 | return 0; | |
8639 | ||
8640 | switch (c) | |
8641 | { | |
8642 | case 'Q': | |
8643 | return fp_sethi_p (op); | |
8644 | ||
8645 | case 'R': | |
8646 | return fp_mov_p (op); | |
8647 | ||
8648 | case 'S': | |
8649 | return fp_high_losum_p (op); | |
8650 | ||
8651 | case 'U': | |
8652 | if (! strict | |
8653 | || (GET_CODE (op) == REG | |
8654 | && (REGNO (op) < FIRST_PSEUDO_REGISTER | |
8655 | || reg_renumber[REGNO (op)] >= 0))) | |
8656 | return register_ok_for_ldd (op); | |
8657 | ||
8658 | return 0; | |
8659 | ||
8660 | case 'W': | |
8661 | case 'T': | |
8662 | break; | |
8663 | ||
8664 | default: | |
8665 | return 0; | |
8666 | } | |
8667 | ||
8668 | /* Our memory extra constraints have to emulate the | |
8669 | behavior of 'm' and 'o' in order for reload to work | |
8670 | correctly. */ | |
8671 | if (GET_CODE (op) == MEM) | |
8672 | { | |
8673 | reload_ok_mem = 0; | |
8674 | if ((TARGET_ARCH64 || mem_min_alignment (op, 8)) | |
8675 | && (! strict | |
8676 | || strict_memory_address_p (Pmode, XEXP (op, 0)))) | |
8677 | reload_ok_mem = 1; | |
8678 | } | |
8679 | else | |
8680 | { | |
8681 | reload_ok_mem = (reload_in_progress | |
8682 | && GET_CODE (op) == REG | |
8683 | && REGNO (op) >= FIRST_PSEUDO_REGISTER | |
8684 | && reg_renumber [REGNO (op)] < 0); | |
8685 | } | |
8686 | ||
8687 | return reload_ok_mem; | |
8688 | } | |
2ce04b6b | 8689 | |
214c6394 DM |
8690 | /* ??? This duplicates information provided to the compiler by the |
8691 | ??? scheduler description. Some day, teach genautomata to output | |
8692 | ??? the latencies and then CSE will just use that. */ | |
8693 | ||
3c50106f | 8694 | static bool |
fc27d102 | 8695 | sparc_rtx_costs (rtx x, int code, int outer_code, int *total) |
2ce04b6b DM |
8696 | { |
8697 | switch (code) | |
8698 | { | |
214c6394 DM |
8699 | case PLUS: case MINUS: case ABS: case NEG: |
8700 | case FLOAT: case UNSIGNED_FLOAT: | |
8701 | case FIX: case UNSIGNED_FIX: | |
8702 | case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
8703 | if (FLOAT_MODE_P (GET_MODE (x))) | |
8704 | { | |
8705 | switch (sparc_cpu) | |
8706 | { | |
8707 | case PROCESSOR_ULTRASPARC: | |
8708 | case PROCESSOR_ULTRASPARC3: | |
3c50106f RH |
8709 | *total = COSTS_N_INSNS (4); |
8710 | return true; | |
214c6394 DM |
8711 | |
8712 | case PROCESSOR_SUPERSPARC: | |
3c50106f RH |
8713 | *total = COSTS_N_INSNS (3); |
8714 | return true; | |
214c6394 DM |
8715 | |
8716 | case PROCESSOR_CYPRESS: | |
3c50106f RH |
8717 | *total = COSTS_N_INSNS (5); |
8718 | return true; | |
214c6394 DM |
8719 | |
8720 | case PROCESSOR_HYPERSPARC: | |
8721 | case PROCESSOR_SPARCLITE86X: | |
8722 | default: | |
3c50106f RH |
8723 | *total = COSTS_N_INSNS (1); |
8724 | return true; | |
214c6394 DM |
8725 | } |
8726 | } | |
8727 | ||
3c50106f RH |
8728 | *total = COSTS_N_INSNS (1); |
8729 | return true; | |
214c6394 DM |
8730 | |
8731 | case SQRT: | |
8732 | switch (sparc_cpu) | |
8733 | { | |
8734 | case PROCESSOR_ULTRASPARC: | |
8735 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8736 | *total = COSTS_N_INSNS (13); |
214c6394 | 8737 | else |
3c50106f RH |
8738 | *total = COSTS_N_INSNS (23); |
8739 | return true; | |
214c6394 DM |
8740 | |
8741 | case PROCESSOR_ULTRASPARC3: | |
8742 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8743 | *total = COSTS_N_INSNS (20); |
214c6394 | 8744 | else |
3c50106f RH |
8745 | *total = COSTS_N_INSNS (29); |
8746 | return true; | |
214c6394 DM |
8747 | |
8748 | case PROCESSOR_SUPERSPARC: | |
3c50106f RH |
8749 | *total = COSTS_N_INSNS (12); |
8750 | return true; | |
214c6394 DM |
8751 | |
8752 | case PROCESSOR_CYPRESS: | |
3c50106f RH |
8753 | *total = COSTS_N_INSNS (63); |
8754 | return true; | |
214c6394 DM |
8755 | |
8756 | case PROCESSOR_HYPERSPARC: | |
8757 | case PROCESSOR_SPARCLITE86X: | |
3c50106f RH |
8758 | *total = COSTS_N_INSNS (17); |
8759 | return true; | |
214c6394 DM |
8760 | |
8761 | default: | |
3c50106f RH |
8762 | *total = COSTS_N_INSNS (30); |
8763 | return true; | |
214c6394 DM |
8764 | } |
8765 | ||
8766 | case COMPARE: | |
8767 | if (FLOAT_MODE_P (GET_MODE (x))) | |
8768 | { | |
8769 | switch (sparc_cpu) | |
8770 | { | |
8771 | case PROCESSOR_ULTRASPARC: | |
8772 | case PROCESSOR_ULTRASPARC3: | |
3c50106f RH |
8773 | *total = COSTS_N_INSNS (1); |
8774 | return true; | |
214c6394 DM |
8775 | |
8776 | case PROCESSOR_SUPERSPARC: | |
3c50106f RH |
8777 | *total = COSTS_N_INSNS (3); |
8778 | return true; | |
214c6394 DM |
8779 | |
8780 | case PROCESSOR_CYPRESS: | |
3c50106f RH |
8781 | *total = COSTS_N_INSNS (5); |
8782 | return true; | |
214c6394 DM |
8783 | |
8784 | case PROCESSOR_HYPERSPARC: | |
8785 | case PROCESSOR_SPARCLITE86X: | |
8786 | default: | |
3c50106f RH |
8787 | *total = COSTS_N_INSNS (1); |
8788 | return true; | |
214c6394 DM |
8789 | } |
8790 | } | |
8791 | ||
8792 | /* ??? Maybe mark integer compares as zero cost on | |
8793 | ??? all UltraSPARC processors because the result | |
8794 | ??? can be bypassed to a branch in the same group. */ | |
8795 | ||
3c50106f RH |
8796 | *total = COSTS_N_INSNS (1); |
8797 | return true; | |
214c6394 | 8798 | |
2ce04b6b | 8799 | case MULT: |
214c6394 DM |
8800 | if (FLOAT_MODE_P (GET_MODE (x))) |
8801 | { | |
8802 | switch (sparc_cpu) | |
8803 | { | |
8804 | case PROCESSOR_ULTRASPARC: | |
8805 | case PROCESSOR_ULTRASPARC3: | |
3c50106f RH |
8806 | *total = COSTS_N_INSNS (4); |
8807 | return true; | |
214c6394 DM |
8808 | |
8809 | case PROCESSOR_SUPERSPARC: | |
3c50106f RH |
8810 | *total = COSTS_N_INSNS (3); |
8811 | return true; | |
214c6394 DM |
8812 | |
8813 | case PROCESSOR_CYPRESS: | |
3c50106f RH |
8814 | *total = COSTS_N_INSNS (7); |
8815 | return true; | |
214c6394 DM |
8816 | |
8817 | case PROCESSOR_HYPERSPARC: | |
8818 | case PROCESSOR_SPARCLITE86X: | |
3c50106f RH |
8819 | *total = COSTS_N_INSNS (1); |
8820 | return true; | |
214c6394 DM |
8821 | |
8822 | default: | |
3c50106f RH |
8823 | *total = COSTS_N_INSNS (5); |
8824 | return true; | |
214c6394 DM |
8825 | } |
8826 | } | |
8827 | ||
8828 | /* The latency is actually variable for Ultra-I/II | |
8829 | And if one of the inputs have a known constant | |
8830 | value, we could calculate this precisely. | |
8831 | ||
8832 | However, for that to be useful we would need to | |
8833 | add some machine description changes which would | |
8834 | make sure small constants ended up in rs1 of the | |
8835 | multiply instruction. This is because the multiply | |
8836 | latency is determined by the number of clear (or | |
8837 | set if the value is negative) bits starting from | |
8838 | the most significant bit of the first input. | |
8839 | ||
8840 | The algorithm for computing num_cycles of a multiply | |
8841 | on Ultra-I/II is: | |
8842 | ||
8843 | if (rs1 < 0) | |
8844 | highest_bit = highest_clear_bit(rs1); | |
8845 | else | |
8846 | highest_bit = highest_set_bit(rs1); | |
8847 | if (num_bits < 3) | |
8848 | highest_bit = 3; | |
8849 | num_cycles = 4 + ((highest_bit - 3) / 2); | |
8850 | ||
8851 | If we did that we would have to also consider register | |
8852 | allocation issues that would result from forcing such | |
8853 | a value into a register. | |
8854 | ||
8855 | There are other similar tricks we could play if we | |
8856 | knew, for example, that one input was an array index. | |
8857 | ||
8858 | Since we do not play any such tricks currently the | |
8859 | safest thing to do is report the worst case latency. */ | |
2ce04b6b | 8860 | if (sparc_cpu == PROCESSOR_ULTRASPARC) |
3c50106f RH |
8861 | { |
8862 | *total = (GET_MODE (x) == DImode | |
8863 | ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); | |
8864 | return true; | |
8865 | } | |
2ce04b6b | 8866 | |
214c6394 | 8867 | /* Multiply latency on Ultra-III, fortunately, is constant. */ |
2ce04b6b | 8868 | if (sparc_cpu == PROCESSOR_ULTRASPARC3) |
3c50106f RH |
8869 | { |
8870 | *total = COSTS_N_INSNS (6); | |
8871 | return true; | |
8872 | } | |
2ce04b6b | 8873 | |
214c6394 DM |
8874 | if (sparc_cpu == PROCESSOR_HYPERSPARC |
8875 | || sparc_cpu == PROCESSOR_SPARCLITE86X) | |
3c50106f RH |
8876 | { |
8877 | *total = COSTS_N_INSNS (17); | |
8878 | return true; | |
8879 | } | |
214c6394 | 8880 | |
3c50106f RH |
8881 | *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25)); |
8882 | return true; | |
2ce04b6b DM |
8883 | |
8884 | case DIV: | |
8885 | case UDIV: | |
8886 | case MOD: | |
8887 | case UMOD: | |
214c6394 DM |
8888 | if (FLOAT_MODE_P (GET_MODE (x))) |
8889 | { | |
8890 | switch (sparc_cpu) | |
8891 | { | |
8892 | case PROCESSOR_ULTRASPARC: | |
8893 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8894 | *total = COSTS_N_INSNS (13); |
214c6394 | 8895 | else |
3c50106f RH |
8896 | *total = COSTS_N_INSNS (23); |
8897 | return true; | |
214c6394 DM |
8898 | |
8899 | case PROCESSOR_ULTRASPARC3: | |
8900 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8901 | *total = COSTS_N_INSNS (17); |
214c6394 | 8902 | else |
3c50106f RH |
8903 | *total = COSTS_N_INSNS (20); |
8904 | return true; | |
214c6394 DM |
8905 | |
8906 | case PROCESSOR_SUPERSPARC: | |
8907 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8908 | *total = COSTS_N_INSNS (6); |
214c6394 | 8909 | else |
3c50106f RH |
8910 | *total = COSTS_N_INSNS (9); |
8911 | return true; | |
214c6394 DM |
8912 | |
8913 | case PROCESSOR_HYPERSPARC: | |
8914 | case PROCESSOR_SPARCLITE86X: | |
8915 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8916 | *total = COSTS_N_INSNS (8); |
214c6394 | 8917 | else |
3c50106f RH |
8918 | *total = COSTS_N_INSNS (12); |
8919 | return true; | |
214c6394 DM |
8920 | |
8921 | default: | |
3c50106f RH |
8922 | *total = COSTS_N_INSNS (7); |
8923 | return true; | |
214c6394 DM |
8924 | } |
8925 | } | |
8926 | ||
2ce04b6b | 8927 | if (sparc_cpu == PROCESSOR_ULTRASPARC) |
3c50106f RH |
8928 | *total = (GET_MODE (x) == DImode |
8929 | ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); | |
8930 | else if (sparc_cpu == PROCESSOR_ULTRASPARC3) | |
8931 | *total = (GET_MODE (x) == DImode | |
8932 | ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40)); | |
8933 | else | |
8934 | *total = COSTS_N_INSNS (25); | |
8935 | return true; | |
2ce04b6b | 8936 | |
214c6394 DM |
8937 | case IF_THEN_ELSE: |
8938 | /* Conditional moves. */ | |
8939 | switch (sparc_cpu) | |
8940 | { | |
8941 | case PROCESSOR_ULTRASPARC: | |
3c50106f RH |
8942 | *total = COSTS_N_INSNS (2); |
8943 | return true; | |
214c6394 DM |
8944 | |
8945 | case PROCESSOR_ULTRASPARC3: | |
8946 | if (FLOAT_MODE_P (GET_MODE (x))) | |
3c50106f | 8947 | *total = COSTS_N_INSNS (3); |
214c6394 | 8948 | else |
3c50106f RH |
8949 | *total = COSTS_N_INSNS (2); |
8950 | return true; | |
214c6394 DM |
8951 | |
8952 | default: | |
3c50106f RH |
8953 | *total = COSTS_N_INSNS (1); |
8954 | return true; | |
214c6394 DM |
8955 | } |
8956 | ||
8957 | case MEM: | |
8958 | /* If outer-code is SIGN/ZERO extension we have to subtract | |
8959 | out COSTS_N_INSNS (1) from whatever we return in determining | |
8960 | the cost. */ | |
8961 | switch (sparc_cpu) | |
8962 | { | |
8963 | case PROCESSOR_ULTRASPARC: | |
8964 | if (outer_code == ZERO_EXTEND) | |
3c50106f | 8965 | *total = COSTS_N_INSNS (1); |
214c6394 | 8966 | else |
3c50106f RH |
8967 | *total = COSTS_N_INSNS (2); |
8968 | return true; | |
214c6394 DM |
8969 | |
8970 | case PROCESSOR_ULTRASPARC3: | |
8971 | if (outer_code == ZERO_EXTEND) | |
8972 | { | |
8973 | if (GET_MODE (x) == QImode | |
8974 | || GET_MODE (x) == HImode | |
8975 | || outer_code == SIGN_EXTEND) | |
3c50106f | 8976 | *total = COSTS_N_INSNS (2); |
214c6394 | 8977 | else |
3c50106f | 8978 | *total = COSTS_N_INSNS (1); |
214c6394 DM |
8979 | } |
8980 | else | |
8981 | { | |
8982 | /* This handles sign extension (3 cycles) | |
8983 | and everything else (2 cycles). */ | |
3c50106f | 8984 | *total = COSTS_N_INSNS (2); |
214c6394 | 8985 | } |
3c50106f | 8986 | return true; |
214c6394 DM |
8987 | |
8988 | case PROCESSOR_SUPERSPARC: | |
8989 | if (FLOAT_MODE_P (GET_MODE (x)) | |
8990 | || outer_code == ZERO_EXTEND | |
8991 | || outer_code == SIGN_EXTEND) | |
3c50106f | 8992 | *total = COSTS_N_INSNS (0); |
214c6394 | 8993 | else |
3c50106f RH |
8994 | *total = COSTS_N_INSNS (1); |
8995 | return true; | |
214c6394 DM |
8996 | |
8997 | case PROCESSOR_TSC701: | |
8998 | if (outer_code == ZERO_EXTEND | |
8999 | || outer_code == SIGN_EXTEND) | |
3c50106f | 9000 | *total = COSTS_N_INSNS (2); |
214c6394 | 9001 | else |
3c50106f RH |
9002 | *total = COSTS_N_INSNS (3); |
9003 | return true; | |
214c6394 DM |
9004 | |
9005 | case PROCESSOR_CYPRESS: | |
9006 | if (outer_code == ZERO_EXTEND | |
9007 | || outer_code == SIGN_EXTEND) | |
3c50106f | 9008 | *total = COSTS_N_INSNS (1); |
214c6394 | 9009 | else |
3c50106f RH |
9010 | *total = COSTS_N_INSNS (2); |
9011 | return true; | |
214c6394 DM |
9012 | |
9013 | case PROCESSOR_HYPERSPARC: | |
9014 | case PROCESSOR_SPARCLITE86X: | |
9015 | default: | |
9016 | if (outer_code == ZERO_EXTEND | |
9017 | || outer_code == SIGN_EXTEND) | |
3c50106f | 9018 | *total = COSTS_N_INSNS (0); |
214c6394 | 9019 | else |
3c50106f RH |
9020 | *total = COSTS_N_INSNS (1); |
9021 | return true; | |
214c6394 | 9022 | } |
2ce04b6b DM |
9023 | |
9024 | case CONST_INT: | |
9025 | if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000) | |
3c50106f RH |
9026 | { |
9027 | *total = 0; | |
9028 | return true; | |
9029 | } | |
9030 | /* FALLTHRU */ | |
2ce04b6b | 9031 | |
2ce04b6b | 9032 | case HIGH: |
3c50106f RH |
9033 | *total = 2; |
9034 | return true; | |
2ce04b6b DM |
9035 | |
9036 | case CONST: | |
9037 | case LABEL_REF: | |
9038 | case SYMBOL_REF: | |
3c50106f RH |
9039 | *total = 4; |
9040 | return true; | |
2ce04b6b DM |
9041 | |
9042 | case CONST_DOUBLE: | |
3c50106f RH |
9043 | if (GET_MODE (x) == DImode |
9044 | && ((XINT (x, 3) == 0 | |
9045 | && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000) | |
9046 | || (XINT (x, 3) == -1 | |
9047 | && XINT (x, 2) < 0 | |
9048 | && XINT (x, 2) >= -0x1000))) | |
9049 | *total = 0; | |
9050 | else | |
9051 | *total = 8; | |
9052 | return true; | |
2ce04b6b DM |
9053 | |
9054 | default: | |
3c50106f RH |
9055 | return false; |
9056 | } | |
2ce04b6b | 9057 | } |
fb49053f | 9058 | |
e133041b RH |
9059 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. |
9060 | Used for C++ multiple inheritance. */ | |
9061 | ||
c590b625 | 9062 | static void |
fc27d102 KG |
9063 | sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
9064 | HOST_WIDE_INT delta, | |
9065 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
9066 | tree function) | |
e133041b RH |
9067 | { |
9068 | rtx this, insn, funexp, delta_rtx, tmp; | |
9069 | ||
9070 | reload_completed = 1; | |
fe3ad572 | 9071 | epilogue_completed = 1; |
e133041b RH |
9072 | no_new_pseudos = 1; |
9073 | current_function_uses_only_leaf_regs = 1; | |
9074 | ||
2e040219 | 9075 | emit_note (NOTE_INSN_PROLOGUE_END); |
e133041b RH |
9076 | |
9077 | /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function | |
9078 | returns a structure, the structure return pointer is there instead. */ | |
61f71b34 | 9079 | if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
e133041b RH |
9080 | this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1); |
9081 | else | |
9082 | this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST); | |
9083 | ||
9084 | /* Add DELTA. When possible use a plain add, otherwise load it into | |
9085 | a register first. */ | |
9086 | delta_rtx = GEN_INT (delta); | |
9087 | if (!SPARC_SIMM13_P (delta)) | |
9088 | { | |
9089 | rtx scratch = gen_rtx_REG (Pmode, 1); | |
ed1fe829 EB |
9090 | |
9091 | if (input_operand (delta_rtx, GET_MODE (scratch))) | |
9092 | emit_insn (gen_rtx_SET (VOIDmode, scratch, delta_rtx)); | |
e133041b | 9093 | else |
ed1fe829 EB |
9094 | { |
9095 | if (TARGET_ARCH64) | |
9096 | sparc_emit_set_const64 (scratch, delta_rtx); | |
9097 | else | |
9098 | sparc_emit_set_const32 (scratch, delta_rtx); | |
9099 | } | |
9100 | ||
e133041b RH |
9101 | delta_rtx = scratch; |
9102 | } | |
9103 | ||
9104 | tmp = gen_rtx_PLUS (Pmode, this, delta_rtx); | |
9105 | emit_insn (gen_rtx_SET (VOIDmode, this, tmp)); | |
9106 | ||
9107 | /* Generate a tail call to the target function. */ | |
9108 | if (! TREE_USED (function)) | |
9109 | { | |
9110 | assemble_external (function); | |
9111 | TREE_USED (function) = 1; | |
9112 | } | |
9113 | funexp = XEXP (DECL_RTL (function), 0); | |
9114 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); | |
9115 | insn = emit_call_insn (gen_sibcall (funexp)); | |
9116 | SIBLING_CALL_P (insn) = 1; | |
9117 | emit_barrier (); | |
9118 | ||
9119 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
9120 | There's not really enough bulk here to make other passes such as | |
9121 | instruction scheduling worth while. Note that use_thunk calls | |
9122 | assemble_start_function and assemble_end_function. */ | |
9123 | insn = get_insns (); | |
a2855205 | 9124 | insn_locators_initialize (); |
e133041b RH |
9125 | shorten_branches (insn); |
9126 | final_start_function (insn, file, 1); | |
9127 | final (insn, file, 1, 0); | |
9128 | final_end_function (); | |
9129 | ||
9130 | reload_completed = 0; | |
fe3ad572 | 9131 | epilogue_completed = 0; |
e133041b RH |
9132 | no_new_pseudos = 0; |
9133 | } | |
e2500fed | 9134 | |
5751a10b JJ |
9135 | /* How to allocate a 'struct machine_function'. */ |
9136 | ||
9137 | static struct machine_function * | |
9138 | sparc_init_machine_status (void) | |
9139 | { | |
9140 | return ggc_alloc_cleared (sizeof (struct machine_function)); | |
9141 | } | |
9142 | ||
9143 | /* Locate some local-dynamic symbol still in use by this function | |
9144 | so that we can print its name in local-dynamic base patterns. */ | |
9145 | ||
9146 | static const char * | |
9147 | get_some_local_dynamic_name (void) | |
9148 | { | |
9149 | rtx insn; | |
9150 | ||
9151 | if (cfun->machine->some_ld_name) | |
9152 | return cfun->machine->some_ld_name; | |
9153 | ||
9154 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
9155 | if (INSN_P (insn) | |
9156 | && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0)) | |
9157 | return cfun->machine->some_ld_name; | |
9158 | ||
9159 | abort (); | |
9160 | } | |
9161 | ||
9162 | static int | |
9163 | get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) | |
9164 | { | |
9165 | rtx x = *px; | |
9166 | ||
9167 | if (x | |
9168 | && GET_CODE (x) == SYMBOL_REF | |
9169 | && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
9170 | { | |
9171 | cfun->machine->some_ld_name = XSTR (x, 0); | |
9172 | return 1; | |
9173 | } | |
9174 | ||
9175 | return 0; | |
9176 | } | |
9177 | ||
9178 | /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL. | |
9179 | We need to emit DTP-relative relocations. */ | |
9180 | ||
9181 | void | |
9182 | sparc_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
9183 | { | |
9184 | switch (size) | |
9185 | { | |
9186 | case 4: | |
9187 | fputs ("\t.word\t%r_tls_dtpoff32(", file); | |
9188 | break; | |
9189 | case 8: | |
9190 | fputs ("\t.xword\t%r_tls_dtpoff64(", file); | |
9191 | break; | |
9192 | default: | |
9193 | abort (); | |
9194 | } | |
9195 | output_addr_const (file, x); | |
9196 | fputs (")", file); | |
9197 | } | |
9198 | ||
e2500fed | 9199 | #include "gt-sparc.h" |