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823baf68 1/* Subroutines for insn-output.c for Sun SPARC.
533e0227 2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
52470889 3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
823baf68 4 Contributed by Michael Tiemann (tiemann@cygnus.com)
6dac3578 5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
6 at Cygnus Support.
823baf68 7
8This file is part of GNU CC.
9
10GNU CC is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2, or (at your option)
13any later version.
14
15GNU CC is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
21along with GNU CC; see the file COPYING. If not, write to
9b754436 22the Free Software Foundation, 59 Temple Place - Suite 330,
23Boston, MA 02111-1307, USA. */
823baf68 24
823baf68 25#include "config.h"
367242d3 26#include "system.h"
805e22b2 27#include "coretypes.h"
28#include "tm.h"
0f6f82ff 29#include "tree.h"
823baf68 30#include "rtl.h"
31#include "regs.h"
32#include "hard-reg-set.h"
33#include "real.h"
34#include "insn-config.h"
35#include "conditions.h"
823baf68 36#include "output.h"
37#include "insn-attr.h"
38#include "flags.h"
0a893c29 39#include "function.h"
823baf68 40#include "expr.h"
d8fc4d0b 41#include "optabs.h"
42#include "libfuncs.h"
823baf68 43#include "recog.h"
0e93a6ac 44#include "toplev.h"
5cb4669a 45#include "ggc.h"
075136a2 46#include "tm_p.h"
d8fc4d0b 47#include "debug.h"
a767736d 48#include "target.h"
49#include "target-def.h"
823baf68 50
6dac3578 51/* 1 if the caller has placed an "unimp" insn immediately after the call.
52 This is used in v8 code when calling a function that returns a structure.
0e05caf0 53 v9 doesn't have this. Be careful to have this test be the same as that
54 used on the call. */
55
56#define SKIP_CALLERS_UNIMP_P \
57(!TARGET_ARCH64 && current_function_returns_struct \
58 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
59 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
60 == INTEGER_CST))
6dac3578 61
823baf68 62/* Global variables for machine-dependent things. */
63
6dac3578 64/* Size of frame. Need to know this to emit return insns from leaf procedures.
65 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
66 reload pass. This is important as the value is later used in insn
67 scheduling (to see what can go in a delay slot).
68 APPARENT_FSIZE is the size of the stack less the register save area and less
69 the outgoing argument area. It is used when saving call preserved regs. */
70static int apparent_fsize;
71static int actual_fsize;
72
8b7a298d 73/* Number of live general or floating point registers needed to be
74 saved (as 4-byte quantities). */
5a1acad9 75static int num_gfregs;
76
823baf68 77/* Save the operands last given to a compare for use when we
78 generate a scc or bcc insn. */
823baf68 79rtx sparc_compare_op0, sparc_compare_op1;
80
8b7a298d 81/* Coordinate with the md file wrt special insns created by
82 sparc_nonflat_function_epilogue. */
83bool sparc_emitting_epilogue;
823baf68 84
04a917bf 85/* Vector to say how input registers are mapped to output registers.
86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
87 eliminate it. You must use -fomit-frame-pointer to get that. */
626dd758 88char leaf_reg_remap[] =
823baf68 89{ 0, 1, 2, 3, 4, 5, 6, 7,
90 -1, -1, -1, -1, -1, -1, 14, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1,
92 8, 9, 10, 11, 12, 13, -1, 15,
93
94 32, 33, 34, 35, 36, 37, 38, 39,
95 40, 41, 42, 43, 44, 45, 46, 47,
96 48, 49, 50, 51, 52, 53, 54, 55,
6dac3578 97 56, 57, 58, 59, 60, 61, 62, 63,
98 64, 65, 66, 67, 68, 69, 70, 71,
99 72, 73, 74, 75, 76, 77, 78, 79,
100 80, 81, 82, 83, 84, 85, 86, 87,
101 88, 89, 90, 91, 92, 93, 94, 95,
946e12d1 102 96, 97, 98, 99, 100};
823baf68 103
7a8d641b 104/* Vector, indexed by hard register number, which contains 1
105 for a register that is allowable in a candidate for leaf
106 function treatment. */
107char sparc_leaf_regs[] =
108{ 1, 1, 1, 1, 1, 1, 1, 1,
109 0, 0, 0, 0, 0, 0, 1, 0,
110 0, 0, 0, 0, 0, 0, 0, 0,
111 1, 1, 1, 1, 1, 1, 0, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
120 1, 1, 1, 1, 1};
121
823baf68 122/* Name of where we pretend to think the frame pointer points.
123 Normally, this is "%fp", but if we are in a leaf procedure,
6dac3578 124 this is "%sp+something". We record "something" separately as it may be
125 too big for reg+constant addressing. */
126
c4f04114 127static const char *frame_base_name;
6dac3578 128static int frame_base_offset;
823baf68 129
32bd1bda 130static void sparc_init_modes PARAMS ((void));
131static int save_regs PARAMS ((FILE *, int, int, const char *,
220345e0 132 int, int, int));
32bd1bda 133static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int));
134static void build_big_number PARAMS ((FILE *, int, const char *));
135static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *,
220345e0 136 enum machine_mode, tree, int, int,
137 int *, int *));
32933b3c 138
32bd1bda 139static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
140static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
32bd1bda 141
142static void sparc_output_addr_vec PARAMS ((rtx));
143static void sparc_output_addr_diff_vec PARAMS ((rtx));
144static void sparc_output_deferred_case_vectors PARAMS ((void));
32bd1bda 145static int check_return_regs PARAMS ((rtx));
146static int epilogue_renumber PARAMS ((rtx *, int));
58356836 147static bool sparc_assemble_integer PARAMS ((rtx, unsigned int, int));
0ca827a6 148static int set_extends PARAMS ((rtx));
5e431971 149static void output_restore_regs PARAMS ((FILE *, int));
17d9b0c3 150static void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
151static void sparc_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
152static void sparc_flat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
153static void sparc_flat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
154static void sparc_nonflat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT,
155 int));
156static void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT,
157 int));
6e4758ce 158#ifdef OBJECT_FORMAT_ELF
29a0ebee 159static void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int));
6e4758ce 160#endif
52470889 161static void sparc_aout_select_section PARAMS ((tree, int,
162 unsigned HOST_WIDE_INT))
163 ATTRIBUTE_UNUSED;
bbfbe351 164static void sparc_aout_select_rtx_section PARAMS ((enum machine_mode, rtx,
165 unsigned HOST_WIDE_INT))
166 ATTRIBUTE_UNUSED;
747af5e7 167
168static int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
169static int sparc_issue_rate PARAMS ((void));
747af5e7 170static void sparc_sched_init PARAMS ((FILE *, int, int));
bea4bad2 171static int sparc_use_dfa_pipeline_interface PARAMS ((void));
172static int sparc_use_sched_lookahead PARAMS ((void));
c00088b6 173
174static void emit_soft_tfmode_libcall PARAMS ((const char *, int, rtx *));
175static void emit_soft_tfmode_binop PARAMS ((enum rtx_code, rtx *));
176static void emit_soft_tfmode_unop PARAMS ((enum rtx_code, rtx *));
177static void emit_soft_tfmode_cvt PARAMS ((enum rtx_code, rtx *));
178static void emit_hard_tfmode_operation PARAMS ((enum rtx_code, rtx *));
7811991d 179
180static void sparc_encode_section_info PARAMS ((tree, int));
805e22b2 181static bool sparc_function_ok_for_sibcall PARAMS ((tree, tree));
eb344f43 182static void sparc_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
183 HOST_WIDE_INT, tree));
6dac3578 184\f
185/* Option handling. */
186
adf09a2f 187/* Code model option as passed by user. */
c4f04114 188const char *sparc_cmodel_string;
adf09a2f 189/* Parsed value. */
190enum cmodel sparc_cmodel;
191
d300bd48 192char sparc_hard_reg_printed[8];
193
5d1a1653 194struct sparc_cpu_select sparc_select[] =
195{
196 /* switch name, tune arch */
197 { (char *)0, "default", 1, 1 },
198 { (char *)0, "-mcpu=", 1, 1 },
199 { (char *)0, "-mtune=", 1, 0 },
b8430a2d 200 { 0, 0, 0, 0 }
5d1a1653 201};
a954dfd7 202
5d1a1653 203/* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
204enum processor_type sparc_cpu;
a767736d 205\f
206/* Initialize the GCC target structure. */
58356836 207
208/* The sparc default is to use .half rather than .short for aligned
209 HI objects. Use .word instead of .long on non-ELF systems. */
210#undef TARGET_ASM_ALIGNED_HI_OP
211#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
212#ifndef OBJECT_FORMAT_ELF
213#undef TARGET_ASM_ALIGNED_SI_OP
214#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
215#endif
216
217#undef TARGET_ASM_UNALIGNED_HI_OP
218#define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
219#undef TARGET_ASM_UNALIGNED_SI_OP
220#define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
221#undef TARGET_ASM_UNALIGNED_DI_OP
222#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
223
224/* The target hook has to handle DI-mode values. */
225#undef TARGET_ASM_INTEGER
226#define TARGET_ASM_INTEGER sparc_assemble_integer
227
17d9b0c3 228#undef TARGET_ASM_FUNCTION_PROLOGUE
229#define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
230#undef TARGET_ASM_FUNCTION_EPILOGUE
231#define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
a954dfd7 232
747af5e7 233#undef TARGET_SCHED_ADJUST_COST
234#define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
235#undef TARGET_SCHED_ISSUE_RATE
236#define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
747af5e7 237#undef TARGET_SCHED_INIT
238#define TARGET_SCHED_INIT sparc_sched_init
bea4bad2 239#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
240#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
241#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
242#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
747af5e7 243
7811991d 244#undef TARGET_ENCODE_SECTION_INFO
245#define TARGET_ENCODE_SECTION_INFO sparc_encode_section_info
246
805e22b2 247#undef TARGET_FUNCTION_OK_FOR_SIBCALL
248#define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
249
6988553d 250#undef TARGET_ASM_OUTPUT_MI_THUNK
251#define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
eb344f43 252#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
253#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
6988553d 254
57e4bbfb 255struct gcc_target targetm = TARGET_INITIALIZER;
a767736d 256\f
6dac3578 257/* Validate and override various options, and do some machine dependent
258 initialization. */
259
260void
261sparc_override_options ()
262{
adf09a2f 263 static struct code_model {
e99c3a1d 264 const char *const name;
265 const int value;
266 } const cmodels[] = {
adf09a2f 267 { "32", CM_32 },
268 { "medlow", CM_MEDLOW },
269 { "medmid", CM_MEDMID },
270 { "medany", CM_MEDANY },
271 { "embmedany", CM_EMBMEDANY },
272 { 0, 0 }
273 };
e99c3a1d 274 const struct code_model *cmodel;
5d1a1653 275 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
a954dfd7 276 static struct cpu_default {
e99c3a1d 277 const int cpu;
278 const char *const name;
279 } const cpu_default[] = {
adf09a2f 280 /* There must be one entry here for each TARGET_CPU value. */
5d1a1653 281 { TARGET_CPU_sparc, "cypress" },
224cac7b 282 { TARGET_CPU_sparclet, "tsc701" },
5d1a1653 283 { TARGET_CPU_sparclite, "f930" },
adf09a2f 284 { TARGET_CPU_v8, "v8" },
32933b3c 285 { TARGET_CPU_hypersparc, "hypersparc" },
286 { TARGET_CPU_sparclite86x, "sparclite86x" },
adf09a2f 287 { TARGET_CPU_supersparc, "supersparc" },
288 { TARGET_CPU_v9, "v9" },
830a8fc4 289 { TARGET_CPU_ultrasparc, "ultrasparc" },
bea4bad2 290 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
b8430a2d 291 { 0, 0 }
a954dfd7 292 };
e99c3a1d 293 const struct cpu_default *def;
5d1a1653 294 /* Table of values for -m{cpu,tune}=. */
a954dfd7 295 static struct cpu_table {
e99c3a1d 296 const char *const name;
297 const enum processor_type processor;
298 const int disable;
299 const int enable;
300 } const cpu_table[] = {
5d1a1653 301 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
302 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
303 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
a954dfd7 304 /* TI TMS390Z55 supersparc */
5d1a1653 305 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
306 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
a954dfd7 307 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
308 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
5d1a1653 309 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
310 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
32933b3c 311 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
2bcb629e 312 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
313 MASK_SPARCLITE },
5d1a1653 314 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
a954dfd7 315 /* TEMIC sparclet */
224cac7b 316 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
5d1a1653 317 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
99227eff 318 /* TI ultrasparc I, II, IIi */
319 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
320 /* Although insns using %y are deprecated, it is a clear win on current
8eba0400 321 ultrasparcs. */
bb0456e6 322 |MASK_DEPRECATED_V8_INSNS},
bea4bad2 323 /* TI ultrasparc III */
324 /* ??? Check if %y issue still holds true in ultra3. */
325 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
b8430a2d 326 { 0, 0, 0, 0 }
a954dfd7 327 };
e99c3a1d 328 const struct cpu_table *cpu;
329 const struct sparc_cpu_select *sel;
adf09a2f 330 int fpu;
447b4bf2 331
adf09a2f 332#ifndef SPARC_BI_ARCH
333 /* Check for unsupported architecture size. */
334 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
bb0456e6 335 error ("%s is not supported by this configuration",
336 DEFAULT_ARCH32_P ? "-m64" : "-m32");
adf09a2f 337#endif
338
a8bfd4e9 339 /* We force all 64bit archs to use 128 bit long double */
340 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
341 {
342 error ("-mlong-double-64 not allowed with -m64");
343 target_flags |= MASK_LONG_DOUBLE_128;
344 }
345
adf09a2f 346 /* Code model selection. */
347 sparc_cmodel = SPARC_DEFAULT_CMODEL;
447b4bf2 348
349#ifdef SPARC_BI_ARCH
350 if (TARGET_ARCH32)
351 sparc_cmodel = CM_32;
352#endif
353
adf09a2f 354 if (sparc_cmodel_string != NULL)
355 {
356 if (TARGET_ARCH64)
357 {
358 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
359 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
360 break;
361 if (cmodel->name == NULL)
362 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
363 else
364 sparc_cmodel = cmodel->value;
365 }
366 else
367 error ("-mcmodel= is not supported on 32 bit systems");
368 }
5d1a1653 369
adf09a2f 370 fpu = TARGET_FPU; /* save current -mfpu status */
382b9b85 371
adf09a2f 372 /* Set the default CPU. */
5d1a1653 373 for (def = &cpu_default[0]; def->name; ++def)
374 if (def->cpu == TARGET_CPU_DEFAULT)
375 break;
376 if (! def->name)
377 abort ();
378 sparc_select[0].string = def->name;
379
380 for (sel = &sparc_select[0]; sel->name; ++sel)
6dac3578 381 {
5d1a1653 382 if (sel->string)
a954dfd7 383 {
5d1a1653 384 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
385 if (! strcmp (sel->string, cpu->name))
386 {
387 if (sel->set_tune_p)
388 sparc_cpu = cpu->processor;
389
390 if (sel->set_arch_p)
391 {
392 target_flags &= ~cpu->disable;
393 target_flags |= cpu->enable;
394 }
395 break;
396 }
397
398 if (! cpu->name)
399 error ("bad value (%s) for %s switch", sel->string, sel->name);
a954dfd7 400 }
6dac3578 401 }
3afdcd5a 402
382b9b85 403 /* If -mfpu or -mno-fpu was explicitly used, don't override with
bf6acc7e 404 the processor default. Clear MASK_FPU_SET to avoid confusing
405 the reverse mapping from switch values to names. */
382b9b85 406 if (TARGET_FPU_SET)
bf6acc7e 407 {
408 target_flags = (target_flags & ~MASK_FPU) | fpu;
409 target_flags &= ~MASK_FPU_SET;
410 }
382b9b85 411
14a72bf6 412 /* Don't allow -mvis if FPU is disabled. */
413 if (! TARGET_FPU)
414 target_flags &= ~MASK_VIS;
415
416 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
417 are available.
418 -m64 also implies v9. */
419 if (TARGET_VIS || TARGET_ARCH64)
13153281 420 {
421 target_flags |= MASK_V9;
422 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
423 }
14a72bf6 424
5d1a1653 425 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
426 if (TARGET_V9 && TARGET_ARCH32)
a954dfd7 427 target_flags |= MASK_DEPRECATED_V8_INSNS;
6dac3578 428
447b4bf2 429 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
430 if (! TARGET_V9 || TARGET_ARCH64)
367242d3 431 target_flags &= ~MASK_V8PLUS;
432
8e1581a1 433 /* Don't use stack biasing in 32 bit mode. */
434 if (TARGET_ARCH32)
435 target_flags &= ~MASK_STACK_BIAS;
c90458a1 436
61e95947 437 /* Supply a default value for align_functions. */
bea4bad2 438 if (align_functions == 0
439 && (sparc_cpu == PROCESSOR_ULTRASPARC
440 || sparc_cpu == PROCESSOR_ULTRASPARC3))
61e95947 441 align_functions = 32;
77d3d2a4 442
8e1581a1 443 /* Validate PCC_STRUCT_RETURN. */
444 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
445 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
446
58356836 447 /* Only use .uaxword when compiling for a 64-bit target. */
448 if (!TARGET_ARCH64)
449 targetm.asm_out.unaligned_op.di = NULL;
450
6dac3578 451 /* Do various machine dependent initializations. */
452 sparc_init_modes ();
453}
454\f
3a7728cc 455/* Miscellaneous utilities. */
456
457/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
458 or branch on register contents instructions. */
459
460int
461v9_regcmp_p (code)
462 enum rtx_code code;
463{
464 return (code == EQ || code == NE || code == GE || code == LT
465 || code == LE || code == GT);
466}
f618d313 467
3a7728cc 468\f
469/* Operand constraints. */
470
808a491c 471/* Return nonzero only if OP is a register of mode MODE,
f8be3dfc 472 or const0_rtx. */
946e12d1 473
823baf68 474int
475reg_or_0_operand (op, mode)
476 rtx op;
477 enum machine_mode mode;
478{
946e12d1 479 if (register_operand (op, mode))
480 return 1;
946e12d1 481 if (op == const0_rtx)
823baf68 482 return 1;
b72aafc4 483 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
823baf68 484 && CONST_DOUBLE_HIGH (op) == 0
485 && CONST_DOUBLE_LOW (op) == 0)
486 return 1;
909e6c77 487 if (fp_zero_operand (op, mode))
ef9331b0 488 return 1;
823baf68 489 return 0;
490}
491
808a491c 492/* Return nonzero only if OP is const1_rtx. */
15f8e49b 493
494int
495const1_operand (op, mode)
496 rtx op;
497 enum machine_mode mode ATTRIBUTE_UNUSED;
498{
499 return op == const1_rtx;
500}
501
ef9331b0 502/* Nonzero if OP is a floating point value with value 0.0. */
946e12d1 503
ef9331b0 504int
909e6c77 505fp_zero_operand (op, mode)
ef9331b0 506 rtx op;
909e6c77 507 enum machine_mode mode;
ef9331b0 508{
909e6c77 509 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
510 return 0;
511 return op == CONST0_RTX (mode);
ef9331b0 512}
513
fbeafc33 514/* Nonzero if OP is a register operand in floating point register. */
515
516int
517fp_register_operand (op, mode)
518 rtx op;
519 enum machine_mode mode;
520{
521 if (! register_operand (op, mode))
522 return 0;
523 if (GET_CODE (op) == SUBREG)
524 op = SUBREG_REG (op);
525 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
526}
527
a495126b 528/* Nonzero if OP is a floating point constant which can
529 be loaded into an integer register using a single
530 sethi instruction. */
531
532int
533fp_sethi_p (op)
534 rtx op;
535{
536 if (GET_CODE (op) == CONST_DOUBLE)
537 {
538 REAL_VALUE_TYPE r;
539 long i;
540
541 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
542 if (REAL_VALUES_EQUAL (r, dconst0) &&
543 ! REAL_VALUE_MINUS_ZERO (r))
544 return 0;
545 REAL_VALUE_TO_TARGET_SINGLE (r, i);
546 if (SPARC_SETHI_P (i))
547 return 1;
548 }
549
550 return 0;
551}
552
553/* Nonzero if OP is a floating point constant which can
554 be loaded into an integer register using a single
555 mov instruction. */
556
557int
558fp_mov_p (op)
559 rtx op;
560{
561 if (GET_CODE (op) == CONST_DOUBLE)
562 {
563 REAL_VALUE_TYPE r;
564 long i;
565
566 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
567 if (REAL_VALUES_EQUAL (r, dconst0) &&
568 ! REAL_VALUE_MINUS_ZERO (r))
569 return 0;
570 REAL_VALUE_TO_TARGET_SINGLE (r, i);
571 if (SPARC_SIMM13_P (i))
572 return 1;
573 }
574
575 return 0;
576}
577
578/* Nonzero if OP is a floating point constant which can
579 be loaded into an integer register using a high/losum
580 instruction sequence. */
581
582int
583fp_high_losum_p (op)
584 rtx op;
585{
586 /* The constraints calling this should only be in
587 SFmode move insns, so any constant which cannot
588 be moved using a single insn will do. */
589 if (GET_CODE (op) == CONST_DOUBLE)
590 {
591 REAL_VALUE_TYPE r;
592 long i;
593
594 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
595 if (REAL_VALUES_EQUAL (r, dconst0) &&
596 ! REAL_VALUE_MINUS_ZERO (r))
597 return 0;
598 REAL_VALUE_TO_TARGET_SINGLE (r, i);
599 if (! SPARC_SETHI_P (i)
600 && ! SPARC_SIMM13_P (i))
601 return 1;
602 }
603
604 return 0;
605}
606
6dac3578 607/* Nonzero if OP is an integer register. */
608
609int
610intreg_operand (op, mode)
611 rtx op;
0e93a6ac 612 enum machine_mode mode ATTRIBUTE_UNUSED;
6dac3578 613{
614 return (register_operand (op, SImode)
07569960 615 || (TARGET_ARCH64 && register_operand (op, DImode)));
6dac3578 616}
617
618/* Nonzero if OP is a floating point condition code register. */
619
620int
946e12d1 621fcc_reg_operand (op, mode)
6dac3578 622 rtx op;
623 enum machine_mode mode;
624{
625 /* This can happen when recog is called from combine. Op may be a MEM.
626 Fail instead of calling abort in this case. */
946e12d1 627 if (GET_CODE (op) != REG)
6dac3578 628 return 0;
c74468c0 629
946e12d1 630 if (mode != VOIDmode && mode != GET_MODE (op))
6dac3578 631 return 0;
c74468c0 632 if (mode == VOIDmode
633 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
634 return 0;
6dac3578 635
946e12d1 636#if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
6dac3578 637 if (reg_renumber == 0)
638 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
639 return REGNO_OK_FOR_CCFP_P (REGNO (op));
640#else
946e12d1 641 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
6dac3578 642#endif
643}
644
ebd2c2bf 645/* Nonzero if OP is a floating point condition code fcc0 register. */
646
647int
648fcc0_reg_operand (op, mode)
649 rtx op;
650 enum machine_mode mode;
651{
652 /* This can happen when recog is called from combine. Op may be a MEM.
653 Fail instead of calling abort in this case. */
654 if (GET_CODE (op) != REG)
655 return 0;
656
657 if (mode != VOIDmode && mode != GET_MODE (op))
658 return 0;
659 if (mode == VOIDmode
660 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
661 return 0;
662
663 return REGNO (op) == SPARC_FCC_REG;
664}
665
946e12d1 666/* Nonzero if OP is an integer or floating point condition code register. */
667
668int
669icc_or_fcc_reg_operand (op, mode)
670 rtx op;
671 enum machine_mode mode;
672{
673 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
c74468c0 674 {
675 if (mode != VOIDmode && mode != GET_MODE (op))
676 return 0;
677 if (mode == VOIDmode
678 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
679 return 0;
680 return 1;
681 }
682
946e12d1 683 return fcc_reg_operand (op, mode);
684}
685
823baf68 686/* Nonzero if OP can appear as the dest of a RESTORE insn. */
687int
688restore_operand (op, mode)
689 rtx op;
690 enum machine_mode mode;
691{
692 return (GET_CODE (op) == REG && GET_MODE (op) == mode
693 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
694}
695
bd7a5ff0 696/* Call insn on SPARC can take a PC-relative constant address, or any regular
697 memory address. */
823baf68 698
699int
700call_operand (op, mode)
701 rtx op;
702 enum machine_mode mode;
703{
704 if (GET_CODE (op) != MEM)
705 abort ();
706 op = XEXP (op, 0);
a3e463c6 707 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
823baf68 708}
709
710int
711call_operand_address (op, mode)
712 rtx op;
713 enum machine_mode mode;
714{
a3e463c6 715 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
823baf68 716}
717
718/* Returns 1 if OP is either a symbol reference or a sum of a symbol
719 reference and a constant. */
720
721int
722symbolic_operand (op, mode)
723 register rtx op;
724 enum machine_mode mode;
725{
a277275f 726 enum machine_mode omode = GET_MODE (op);
727
728 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
729 return 0;
730
823baf68 731 switch (GET_CODE (op))
732 {
733 case SYMBOL_REF:
734 case LABEL_REF:
735 return 1;
736
737 case CONST:
738 op = XEXP (op, 0);
739 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
740 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
741 && GET_CODE (XEXP (op, 1)) == CONST_INT);
742
823baf68 743 default:
744 return 0;
745 }
746}
747
748/* Return truth value of statement that OP is a symbolic memory
749 operand of mode MODE. */
750
751int
752symbolic_memory_operand (op, mode)
753 rtx op;
0e93a6ac 754 enum machine_mode mode ATTRIBUTE_UNUSED;
823baf68 755{
756 if (GET_CODE (op) == SUBREG)
757 op = SUBREG_REG (op);
758 if (GET_CODE (op) != MEM)
759 return 0;
760 op = XEXP (op, 0);
761 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
762 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
763}
764
9fa9a0ed 765/* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
766
767int
768label_ref_operand (op, mode)
769 rtx op;
770 enum machine_mode mode;
771{
772 if (GET_CODE (op) != LABEL_REF)
773 return 0;
774 if (GET_MODE (op) != mode)
775 return 0;
776 return 1;
777}
778
b0344bad 779/* Return 1 if the operand is an argument used in generating pic references
780 in either the medium/low or medium/anywhere code models of sparc64. */
781
782int
783sp64_medium_pic_operand (op, mode)
784 rtx op;
0e93a6ac 785 enum machine_mode mode ATTRIBUTE_UNUSED;
b0344bad 786{
787 /* Check for (const (minus (symbol_ref:GOT)
788 (const (minus (label) (pc))))). */
789 if (GET_CODE (op) != CONST)
790 return 0;
791 op = XEXP (op, 0);
792 if (GET_CODE (op) != MINUS)
793 return 0;
794 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
795 return 0;
796 /* ??? Ensure symbol is GOT. */
797 if (GET_CODE (XEXP (op, 1)) != CONST)
798 return 0;
799 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
800 return 0;
801 return 1;
802}
803
6dac3578 804/* Return 1 if the operand is a data segment reference. This includes
805 the readonly data segment, or in other words anything but the text segment.
806 This is needed in the medium/anywhere code model on v9. These values
adf09a2f 807 are accessed with EMBMEDANY_BASE_REG. */
6dac3578 808
809int
810data_segment_operand (op, mode)
811 rtx op;
0e93a6ac 812 enum machine_mode mode ATTRIBUTE_UNUSED;
6dac3578 813{
814 switch (GET_CODE (op))
815 {
816 case SYMBOL_REF :
817 return ! SYMBOL_REF_FLAG (op);
818 case PLUS :
b0344bad 819 /* Assume canonical format of symbol + constant.
820 Fall through. */
6dac3578 821 case CONST :
075136a2 822 return data_segment_operand (XEXP (op, 0), VOIDmode);
6dac3578 823 default :
824 return 0;
825 }
826}
827
828/* Return 1 if the operand is a text segment reference.
829 This is needed in the medium/anywhere code model on v9. */
830
831int
832text_segment_operand (op, mode)
833 rtx op;
0e93a6ac 834 enum machine_mode mode ATTRIBUTE_UNUSED;
6dac3578 835{
836 switch (GET_CODE (op))
837 {
838 case LABEL_REF :
839 return 1;
840 case SYMBOL_REF :
841 return SYMBOL_REF_FLAG (op);
842 case PLUS :
b0344bad 843 /* Assume canonical format of symbol + constant.
844 Fall through. */
6dac3578 845 case CONST :
075136a2 846 return text_segment_operand (XEXP (op, 0), VOIDmode);
6dac3578 847 default :
848 return 0;
849 }
850}
851
823baf68 852/* Return 1 if the operand is either a register or a memory operand that is
853 not symbolic. */
854
855int
856reg_or_nonsymb_mem_operand (op, mode)
857 register rtx op;
858 enum machine_mode mode;
859{
860 if (register_operand (op, mode))
861 return 1;
862
863 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
864 return 1;
865
866 return 0;
867}
868
823baf68 869int
3e59abae 870splittable_symbolic_memory_operand (op, mode)
823baf68 871 rtx op;
0e93a6ac 872 enum machine_mode mode ATTRIBUTE_UNUSED;
823baf68 873{
3e59abae 874 if (GET_CODE (op) != MEM)
875 return 0;
876 if (! symbolic_operand (XEXP (op, 0), Pmode))
877 return 0;
878 return 1;
879}
880
881int
882splittable_immediate_memory_operand (op, mode)
883 rtx op;
0e93a6ac 884 enum machine_mode mode ATTRIBUTE_UNUSED;
3e59abae 885{
886 if (GET_CODE (op) != MEM)
887 return 0;
888 if (! immediate_operand (XEXP (op, 0), Pmode))
889 return 0;
890 return 1;
823baf68 891}
892
893/* Return truth value of whether OP is EQ or NE. */
894
895int
896eq_or_neq (op, mode)
897 rtx op;
0e93a6ac 898 enum machine_mode mode ATTRIBUTE_UNUSED;
823baf68 899{
900 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
901}
902
903/* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
904 or LTU for non-floating-point. We handle those specially. */
905
906int
907normal_comp_operator (op, mode)
908 rtx op;
0e93a6ac 909 enum machine_mode mode ATTRIBUTE_UNUSED;
823baf68 910{
911 enum rtx_code code = GET_CODE (op);
912
913 if (GET_RTX_CLASS (code) != '<')
914 return 0;
915
7dd970bc 916 if (GET_MODE (XEXP (op, 0)) == CCFPmode
917 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
823baf68 918 return 1;
919
920 return (code != NE && code != EQ && code != GEU && code != LTU);
921}
922
923/* Return 1 if this is a comparison operator. This allows the use of
924 MATCH_OPERATOR to recognize all the branch insns. */
925
926int
927noov_compare_op (op, mode)
928 register rtx op;
0e93a6ac 929 enum machine_mode mode ATTRIBUTE_UNUSED;
823baf68 930{
931 enum rtx_code code = GET_CODE (op);
932
933 if (GET_RTX_CLASS (code) != '<')
934 return 0;
935
ebd2c2bf 936 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
937 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
823baf68 938 /* These are the only branches which work with CC_NOOVmode. */
939 return (code == EQ || code == NE || code == GE || code == LT);
940 return 1;
941}
942
ebd2c2bf 943/* Return 1 if this is a 64-bit comparison operator. This allows the use of
944 MATCH_OPERATOR to recognize all the branch insns. */
945
946int
947noov_compare64_op (op, mode)
948 register rtx op;
949 enum machine_mode mode ATTRIBUTE_UNUSED;
950{
951 enum rtx_code code = GET_CODE (op);
952
953 if (! TARGET_V9)
954 return 0;
955
956 if (GET_RTX_CLASS (code) != '<')
957 return 0;
958
959 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
960 /* These are the only branches which work with CCX_NOOVmode. */
961 return (code == EQ || code == NE || code == GE || code == LT);
962 return (GET_MODE (XEXP (op, 0)) == CCXmode);
963}
964
6dac3578 965/* Nonzero if OP is a comparison operator suitable for use in v9
966 conditional move or branch on register contents instructions. */
967
968int
969v9_regcmp_op (op, mode)
970 register rtx op;
0e93a6ac 971 enum machine_mode mode ATTRIBUTE_UNUSED;
6dac3578 972{
973 enum rtx_code code = GET_CODE (op);
974
975 if (GET_RTX_CLASS (code) != '<')
976 return 0;
977
3a7728cc 978 return v9_regcmp_p (code);
6dac3578 979}
980
823baf68 981/* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
982
983int
984extend_op (op, mode)
985 rtx op;
0e93a6ac 986 enum machine_mode mode ATTRIBUTE_UNUSED;
823baf68 987{
988 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
989}
990
991/* Return nonzero if OP is an operator of mode MODE which can set
992 the condition codes explicitly. We do not include PLUS and MINUS
993 because these require CC_NOOVmode, which we handle explicitly. */
994
995int
996cc_arithop (op, mode)
997 rtx op;
0e93a6ac 998 enum machine_mode mode ATTRIBUTE_UNUSED;
823baf68 999{
1000 if (GET_CODE (op) == AND
1001 || GET_CODE (op) == IOR
1002 || GET_CODE (op) == XOR)
1003 return 1;
1004
1005 return 0;
1006}
1007
1008/* Return nonzero if OP is an operator of mode MODE which can bitwise
1009 complement its second operand and set the condition codes explicitly. */
1010
1011int
1012cc_arithopn (op, mode)
1013 rtx op;
0e93a6ac 1014 enum machine_mode mode ATTRIBUTE_UNUSED;
823baf68 1015{
1016 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
8eba0400 1017 and (xor ... (not ...)) to (not (xor ...)). */
823baf68 1018 return (GET_CODE (op) == AND
1019 || GET_CODE (op) == IOR);
1020}
1021\f
c9463047 1022/* Return true if OP is a register, or is a CONST_INT that can fit in a
1023 signed 13 bit immediate field. This is an acceptable SImode operand for
1024 most 3 address instructions. */
823baf68 1025
1026int
1027arith_operand (op, mode)
1028 rtx op;
1029 enum machine_mode mode;
1030{
908608cc 1031 if (register_operand (op, mode))
367242d3 1032 return 1;
1033 if (GET_CODE (op) != CONST_INT)
1034 return 0;
fb124916 1035 return SMALL_INT32 (op);
823baf68 1036}
1037
2aafe30f 1038/* Return true if OP is a constant 4096 */
1039
1040int
1041arith_4096_operand (op, mode)
1042 rtx op;
bd814422 1043 enum machine_mode mode ATTRIBUTE_UNUSED;
2aafe30f 1044{
2aafe30f 1045 if (GET_CODE (op) != CONST_INT)
1046 return 0;
56c1f669 1047 else
1048 return INTVAL (op) == 4096;
2aafe30f 1049}
1050
1051/* Return true if OP is suitable as second operand for add/sub */
1052
1053int
1054arith_add_operand (op, mode)
1055 rtx op;
1056 enum machine_mode mode;
1057{
1058 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1059}
1060
adb58b3c 1061/* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1062 immediate field of OR and XOR instructions. Used for 64-bit
1063 constant formation patterns. */
1064int
1065const64_operand (op, mode)
1066 rtx op;
bd814422 1067 enum machine_mode mode ATTRIBUTE_UNUSED;
adb58b3c 1068{
1069 return ((GET_CODE (op) == CONST_INT
1070 && SPARC_SIMM13_P (INTVAL (op)))
8703a12c 1071#if HOST_BITS_PER_WIDE_INT != 64
adb58b3c 1072 || (GET_CODE (op) == CONST_DOUBLE
8703a12c 1073 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1074 && (CONST_DOUBLE_HIGH (op) ==
1075 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
fb124916 1076 (HOST_WIDE_INT)-1 : 0)))
8703a12c 1077#endif
908608cc 1078 );
adb58b3c 1079}
1080
8703a12c 1081/* The same, but only for sethi instructions. */
adb58b3c 1082int
1083const64_high_operand (op, mode)
1084 rtx op;
73e0f929 1085 enum machine_mode mode;
adb58b3c 1086{
1087 return ((GET_CODE (op) == CONST_INT
fb124916 1088 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
73e0f929 1089 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
8703a12c 1090 )
adb58b3c 1091 || (GET_CODE (op) == CONST_DOUBLE
1092 && CONST_DOUBLE_HIGH (op) == 0
fb124916 1093 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
908608cc 1094 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
adb58b3c 1095}
1096
c9463047 1097/* Return true if OP is a register, or is a CONST_INT that can fit in a
1098 signed 11 bit immediate field. This is an acceptable SImode operand for
1099 the movcc instructions. */
6dac3578 1100
1101int
1102arith11_operand (op, mode)
1103 rtx op;
1104 enum machine_mode mode;
1105{
1106 return (register_operand (op, mode)
c9463047 1107 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
6dac3578 1108}
1109
c9463047 1110/* Return true if OP is a register, or is a CONST_INT that can fit in a
1111 signed 10 bit immediate field. This is an acceptable SImode operand for
1112 the movrcc instructions. */
6dac3578 1113
1114int
1115arith10_operand (op, mode)
1116 rtx op;
1117 enum machine_mode mode;
1118{
1119 return (register_operand (op, mode)
c9463047 1120 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
6dac3578 1121}
1122
6afeff1f 1123/* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1124 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
6dac3578 1125 immediate field.
1126 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1127 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1128 for most 3 address instructions. */
823baf68 1129
1130int
1131arith_double_operand (op, mode)
1132 rtx op;
1133 enum machine_mode mode;
1134{
1135 return (register_operand (op, mode)
6afeff1f 1136 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
07569960 1137 || (! TARGET_ARCH64
6dac3578 1138 && GET_CODE (op) == CONST_DOUBLE
77d3d2a4 1139 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1140 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
07569960 1141 || (TARGET_ARCH64
6dac3578 1142 && GET_CODE (op) == CONST_DOUBLE
77d3d2a4 1143 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
6dac3578 1144 && ((CONST_DOUBLE_HIGH (op) == -1
1145 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1146 || (CONST_DOUBLE_HIGH (op) == 0
1147 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1148}
1149
2aafe30f 1150/* Return true if OP is a constant 4096 for DImode on ARCH64 */
1151
1152int
1153arith_double_4096_operand (op, mode)
1154 rtx op;
bd814422 1155 enum machine_mode mode ATTRIBUTE_UNUSED;
2aafe30f 1156{
1157 return (TARGET_ARCH64 &&
1158 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1159 (GET_CODE (op) == CONST_DOUBLE &&
1160 CONST_DOUBLE_LOW (op) == 4096 &&
1161 CONST_DOUBLE_HIGH (op) == 0)));
1162}
1163
1164/* Return true if OP is suitable as second operand for add/sub in DImode */
1165
1166int
1167arith_double_add_operand (op, mode)
1168 rtx op;
1169 enum machine_mode mode;
1170{
1171 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1172}
1173
6dac3578 1174/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1175 can fit in an 11 bit immediate field. This is an acceptable DImode
1176 operand for the movcc instructions. */
1177/* ??? Replace with arith11_operand? */
1178
1179int
1180arith11_double_operand (op, mode)
1181 rtx op;
1182 enum machine_mode mode;
1183{
1184 return (register_operand (op, mode)
1185 || (GET_CODE (op) == CONST_DOUBLE
1186 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
77d3d2a4 1187 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
6dac3578 1188 && ((CONST_DOUBLE_HIGH (op) == -1
1189 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1190 || (CONST_DOUBLE_HIGH (op) == 0
1191 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1192 || (GET_CODE (op) == CONST_INT
1193 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
77d3d2a4 1194 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
6dac3578 1195}
1196
1197/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1198 can fit in an 10 bit immediate field. This is an acceptable DImode
1199 operand for the movrcc instructions. */
1200/* ??? Replace with arith10_operand? */
1201
1202int
1203arith10_double_operand (op, mode)
1204 rtx op;
1205 enum machine_mode mode;
1206{
1207 return (register_operand (op, mode)
1208 || (GET_CODE (op) == CONST_DOUBLE
1209 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1210 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1211 && ((CONST_DOUBLE_HIGH (op) == -1
1212 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1213 || (CONST_DOUBLE_HIGH (op) == 0
1214 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1215 || (GET_CODE (op) == CONST_INT
1216 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
77d3d2a4 1217 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
823baf68 1218}
1219
45981c0a 1220/* Return truth value of whether OP is an integer which fits the
01c4b00c 1221 range constraining immediate operands in most three-address insns,
1222 which have a 13 bit immediate field. */
823baf68 1223
1224int
1225small_int (op, mode)
1226 rtx op;
0e93a6ac 1227 enum machine_mode mode ATTRIBUTE_UNUSED;
823baf68 1228{
908608cc 1229 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
823baf68 1230}
1231
998032ba 1232int
1233small_int_or_double (op, mode)
1234 rtx op;
1235 enum machine_mode mode ATTRIBUTE_UNUSED;
1236{
1237 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1238 || (GET_CODE (op) == CONST_DOUBLE
1239 && CONST_DOUBLE_HIGH (op) == 0
908608cc 1240 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
998032ba 1241}
1242
ed09825e 1243/* Recognize operand values for the umul instruction. That instruction sign
1244 extends immediate values just like all other sparc instructions, but
1245 interprets the extended result as an unsigned number. */
1246
1247int
1248uns_small_int (op, mode)
1249 rtx op;
0e93a6ac 1250 enum machine_mode mode ATTRIBUTE_UNUSED;
ed09825e 1251{
1252#if HOST_BITS_PER_WIDE_INT > 32
1253 /* All allowed constants will fit a CONST_INT. */
908608cc 1254 return (GET_CODE (op) == CONST_INT
1255 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1256 || (INTVAL (op) >= 0xFFFFF000
0a544228 1257 && INTVAL (op) <= 0xFFFFFFFF)));
ed09825e 1258#else
908608cc 1259 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1260 || (GET_CODE (op) == CONST_DOUBLE
1261 && CONST_DOUBLE_HIGH (op) == 0
1262 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
ed09825e 1263#endif
1264}
1265
1266int
1267uns_arith_operand (op, mode)
1268 rtx op;
1269 enum machine_mode mode;
1270{
1271 return register_operand (op, mode) || uns_small_int (op, mode);
1272}
1273
823baf68 1274/* Return truth value of statement that OP is a call-clobbered register. */
1275int
1276clobbered_register (op, mode)
1277 rtx op;
0e93a6ac 1278 enum machine_mode mode ATTRIBUTE_UNUSED;
823baf68 1279{
1280 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1281}
823baf68 1282
998032ba 1283/* Return 1 if OP is a valid operand for the source of a move insn. */
6dac3578 1284
998032ba 1285int
1286input_operand (op, mode)
1287 rtx op;
1288 enum machine_mode mode;
1289{
1290 /* If both modes are non-void they must be the same. */
1291 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1292 return 0;
6dac3578 1293
908608cc 1294 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1295 if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX)
1296 return 1;
1297
998032ba 1298 /* Allow any one instruction integer constant, and all CONST_INT
1299 variants when we are working in DImode and !arch64. */
1300 if (GET_MODE_CLASS (mode) == MODE_INT
8703a12c 1301 && ((GET_CODE (op) == CONST_INT
73e0f929 1302 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
8703a12c 1303 || SPARC_SIMM13_P (INTVAL (op))
1304 || (mode == DImode
1305 && ! TARGET_ARCH64)))
1306 || (TARGET_ARCH64
1307 && GET_CODE (op) == CONST_DOUBLE
1308 && ((CONST_DOUBLE_HIGH (op) == 0
1309 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1310 ||
1311#if HOST_BITS_PER_WIDE_INT == 64
1312 (CONST_DOUBLE_HIGH (op) == 0
1313 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1314#else
1315 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1316 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1317 && CONST_DOUBLE_HIGH (op) == 0)
7ea8bf17 1318 || (CONST_DOUBLE_HIGH (op) == -1
1319 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
8703a12c 1320#endif
1321 ))))
998032ba 1322 return 1;
1323
998032ba 1324 /* If !arch64 and this is a DImode const, allow it so that
1325 the splits can be generated. */
1326 if (! TARGET_ARCH64
1327 && mode == DImode
1328 && GET_CODE (op) == CONST_DOUBLE)
1329 return 1;
1330
1331 if (register_operand (op, mode))
1332 return 1;
1333
a495126b 1334 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1335 && GET_CODE (op) == CONST_DOUBLE)
1336 return 1;
1337
998032ba 1338 /* If this is a SUBREG, look inside so that we handle
1339 paradoxical ones. */
1340 if (GET_CODE (op) == SUBREG)
1341 op = SUBREG_REG (op);
1342
1343 /* Check for valid MEM forms. */
1344 if (GET_CODE (op) == MEM)
6dac3578 1345 {
998032ba 1346 rtx inside = XEXP (op, 0);
6dac3578 1347
998032ba 1348 if (GET_CODE (inside) == LO_SUM)
7cfb2ce0 1349 {
1350 /* We can't allow these because all of the splits
1351 (eventually as they trickle down into DFmode
1352 splits) require offsettable memory references. */
1353 if (! TARGET_V9
1354 && GET_MODE (op) == TFmode)
1355 return 0;
1356
1357 return (register_operand (XEXP (inside, 0), Pmode)
1358 && CONSTANT_P (XEXP (inside, 1)));
1359 }
998032ba 1360 return memory_address_p (mode, inside);
6dac3578 1361 }
823baf68 1362
998032ba 1363 return 0;
1364}
1365
1366\f
1367/* We know it can't be done in one insn when we get here,
1368 the movsi expander guarentees this. */
1369void
1370sparc_emit_set_const32 (op0, op1)
1371 rtx op0;
1372 rtx op1;
1373{
1374 enum machine_mode mode = GET_MODE (op0);
1375 rtx temp;
1376
1377 if (GET_CODE (op1) == CONST_INT)
367242d3 1378 {
35415df4 1379 HOST_WIDE_INT value = INTVAL (op1);
998032ba 1380
73e0f929 1381 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
998032ba 1382 || SPARC_SIMM13_P (value))
1383 abort ();
367242d3 1384 }
998032ba 1385
1386 /* Full 2-insn decomposition is needed. */
1387 if (reload_in_progress || reload_completed)
1388 temp = op0;
367242d3 1389 else
998032ba 1390 temp = gen_reg_rtx (mode);
1391
611209d4 1392 if (GET_CODE (op1) == CONST_INT)
1393 {
1394 /* Emit them as real moves instead of a HIGH/LO_SUM,
1395 this way CSE can see everything and reuse intermediate
1396 values if it wants. */
1397 if (TARGET_ARCH64
1398 && HOST_BITS_PER_WIDE_INT != 64
1399 && (INTVAL (op1) & 0x80000000) != 0)
6dbdb8b9 1400 emit_insn (gen_rtx_SET
1401 (VOIDmode, temp,
2ff23ed0 1402 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1403 0, DImode)));
611209d4 1404 else
6dbdb8b9 1405 emit_insn (gen_rtx_SET (VOIDmode, temp,
fb124916 1406 GEN_INT (INTVAL (op1)
1407 & ~(HOST_WIDE_INT)0x3ff)));
6dbdb8b9 1408
611209d4 1409 emit_insn (gen_rtx_SET (VOIDmode,
1410 op0,
6dbdb8b9 1411 gen_rtx_IOR (mode, temp,
611209d4 1412 GEN_INT (INTVAL (op1) & 0x3ff))));
1413 }
1414 else
1415 {
1416 /* A symbol, emit in the traditional way. */
6dbdb8b9 1417 emit_insn (gen_rtx_SET (VOIDmode, temp,
1418 gen_rtx_HIGH (mode, op1)));
611209d4 1419 emit_insn (gen_rtx_SET (VOIDmode,
6dbdb8b9 1420 op0, gen_rtx_LO_SUM (mode, temp, op1)));
611209d4 1421
1422 }
998032ba 1423}
1424
1425\f
f25a48be 1426/* SPARC-v9 code-model support. */
998032ba 1427void
1428sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1429 rtx op0;
1430 rtx op1;
1431 rtx temp1;
1432{
c3479b10 1433 rtx ti_temp1 = 0;
1434
1435 if (temp1 && GET_MODE (temp1) == TImode)
1436 {
1437 ti_temp1 = temp1;
1438 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1439 }
1440
998032ba 1441 switch (sparc_cmodel)
367242d3 1442 {
998032ba 1443 case CM_MEDLOW:
1444 /* The range spanned by all instructions in the object is less
1445 than 2^31 bytes (2GB) and the distance from any instruction
1446 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1447 than 2^31 bytes (2GB).
823baf68 1448
998032ba 1449 The executable must be in the low 4TB of the virtual address
1450 space.
6dac3578 1451
998032ba 1452 sethi %hi(symbol), %temp
1453 or %temp, %lo(symbol), %reg */
8703a12c 1454 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1455 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
998032ba 1456 break;
6dac3578 1457
998032ba 1458 case CM_MEDMID:
1459 /* The range spanned by all instructions in the object is less
1460 than 2^31 bytes (2GB) and the distance from any instruction
1461 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1462 than 2^31 bytes (2GB).
1463
1464 The executable must be in the low 16TB of the virtual address
1465 space.
1466
1467 sethi %h44(symbol), %temp1
1468 or %temp1, %m44(symbol), %temp2
1469 sllx %temp2, 12, %temp3
1470 or %temp3, %l44(symbol), %reg */
1471 emit_insn (gen_seth44 (op0, op1));
1472 emit_insn (gen_setm44 (op0, op0, op1));
8703a12c 1473 emit_insn (gen_rtx_SET (VOIDmode, temp1,
998032ba 1474 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1475 emit_insn (gen_setl44 (op0, temp1, op1));
1476 break;
6dac3578 1477
998032ba 1478 case CM_MEDANY:
1479 /* The range spanned by all instructions in the object is less
1480 than 2^31 bytes (2GB) and the distance from any instruction
1481 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1482 than 2^31 bytes (2GB).
1483
1484 The executable can be placed anywhere in the virtual address
1485 space.
1486
1487 sethi %hh(symbol), %temp1
1488 sethi %lm(symbol), %temp2
1489 or %temp1, %hm(symbol), %temp3
1490 or %temp2, %lo(symbol), %temp4
1491 sllx %temp3, 32, %temp5
1492 or %temp4, %temp5, %reg */
1493
c3479b10 1494 /* It is possible that one of the registers we got for operands[2]
1495 might coincide with that of operands[0] (which is why we made
1496 it TImode). Pick the other one to use as our scratch. */
7f63e91b 1497 if (rtx_equal_p (temp1, op0))
c3479b10 1498 {
1499 if (ti_temp1)
1500 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1501 else
1502 abort();
1503 }
6dac3578 1504
998032ba 1505 emit_insn (gen_sethh (op0, op1));
1506 emit_insn (gen_setlm (temp1, op1));
1507 emit_insn (gen_sethm (op0, op0, op1));
8703a12c 1508 emit_insn (gen_rtx_SET (VOIDmode, op0,
998032ba 1509 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
8703a12c 1510 emit_insn (gen_rtx_SET (VOIDmode, op0,
998032ba 1511 gen_rtx_PLUS (DImode, op0, temp1)));
1512 emit_insn (gen_setlo (op0, op0, op1));
1513 break;
6dac3578 1514
998032ba 1515 case CM_EMBMEDANY:
1516 /* Old old old backwards compatibility kruft here.
1517 Essentially it is MEDLOW with a fixed 64-bit
1518 virtual base added to all data segment addresses.
1519 Text-segment stuff is computed like MEDANY, we can't
1520 reuse the code above because the relocation knobs
1521 look different.
1522
1523 Data segment: sethi %hi(symbol), %temp1
1524 or %temp1, %lo(symbol), %temp2
1525 add %temp2, EMBMEDANY_BASE_REG, %reg
1526
1527 Text segment: sethi %uhi(symbol), %temp1
1528 sethi %hi(symbol), %temp2
1529 or %temp1, %ulo(symbol), %temp3
1530 or %temp2, %lo(symbol), %temp4
1531 sllx %temp3, 32, %temp5
1532 or %temp4, %temp5, %reg */
1533 if (data_segment_operand (op1, GET_MODE (op1)))
1534 {
1535 emit_insn (gen_embmedany_sethi (temp1, op1));
1536 emit_insn (gen_embmedany_brsum (op0, temp1));
1537 emit_insn (gen_embmedany_losum (op0, op0, op1));
1538 }
1539 else
1540 {
c3479b10 1541 /* It is possible that one of the registers we got for operands[2]
1542 might coincide with that of operands[0] (which is why we made
1543 it TImode). Pick the other one to use as our scratch. */
1544 if (rtx_equal_p (temp1, op0))
1545 {
1546 if (ti_temp1)
1547 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1548 else
1549 abort();
1550 }
6dac3578 1551
998032ba 1552 emit_insn (gen_embmedany_textuhi (op0, op1));
1553 emit_insn (gen_embmedany_texthi (temp1, op1));
1554 emit_insn (gen_embmedany_textulo (op0, op0, op1));
8703a12c 1555 emit_insn (gen_rtx_SET (VOIDmode, op0,
998032ba 1556 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
8703a12c 1557 emit_insn (gen_rtx_SET (VOIDmode, op0,
998032ba 1558 gen_rtx_PLUS (DImode, op0, temp1)));
1559 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1560 }
1561 break;
1562
1563 default:
1564 abort();
1565 }
1566}
1567
8703a12c 1568/* These avoid problems when cross compiling. If we do not
1569 go through all this hair then the optimizer will see
1570 invalid REG_EQUAL notes or in some cases none at all. */
32bd1bda 1571static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT));
1572static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT));
1573static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT));
1574static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
8703a12c 1575
1576#if HOST_BITS_PER_WIDE_INT == 64
fb124916 1577#define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
8703a12c 1578#define GEN_INT64(__x) GEN_INT (__x)
1579#else
1580#define GEN_HIGHINT64(__x) \
2ff23ed0 1581 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
8703a12c 1582#define GEN_INT64(__x) \
2ff23ed0 1583 immed_double_const ((__x) & 0xffffffff, \
1584 ((__x) & 0x80000000 ? -1 : 0), DImode)
8703a12c 1585#endif
1586
1587/* The optimizer is not to assume anything about exactly
1588 which bits are set for a HIGH, they are unspecified.
1589 Unfortunately this leads to many missed optimizations
1590 during CSE. We mask out the non-HIGH bits, and matches
1591 a plain movdi, to alleviate this problem. */
1592static void
1593sparc_emit_set_safe_HIGH64 (dest, val)
1594 rtx dest;
1595 HOST_WIDE_INT val;
1596{
1597 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1598}
35415df4 1599
998032ba 1600static rtx
8703a12c 1601gen_safe_SET64 (dest, val)
1602 rtx dest;
998032ba 1603 HOST_WIDE_INT val;
6dac3578 1604{
8703a12c 1605 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1606}
1607
1608static rtx
1609gen_safe_OR64 (src, val)
1610 rtx src;
1611 HOST_WIDE_INT val;
1612{
1613 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1614}
1615
1616static rtx
1617gen_safe_XOR64 (src, val)
1618 rtx src;
1619 HOST_WIDE_INT val;
1620{
1621 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
998032ba 1622}
6dac3578 1623
998032ba 1624/* Worker routines for 64-bit constant formation on arch64.
1625 One of the key things to be doing in these emissions is
1626 to create as many temp REGs as possible. This makes it
1627 possible for half-built constants to be used later when
1628 such values are similar to something required later on.
1629 Without doing this, the optimizer cannot see such
1630 opportunities. */
35415df4 1631
1632static void sparc_emit_set_const64_quick1
32bd1bda 1633 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int));
35415df4 1634
998032ba 1635static void
1636sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1637 rtx op0;
1638 rtx temp;
35415df4 1639 unsigned HOST_WIDE_INT low_bits;
998032ba 1640 int is_neg;
1641{
35415df4 1642 unsigned HOST_WIDE_INT high_bits;
07569960 1643
998032ba 1644 if (is_neg)
35415df4 1645 high_bits = (~low_bits) & 0xffffffff;
9c1a19d0 1646 else
998032ba 1647 high_bits = low_bits;
9c1a19d0 1648
8703a12c 1649 sparc_emit_set_safe_HIGH64 (temp, high_bits);
998032ba 1650 if (!is_neg)
0cbaa167 1651 {
1652 emit_insn (gen_rtx_SET (VOIDmode, op0,
1653 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1654 }
998032ba 1655 else
0cbaa167 1656 {
1657 /* If we are XOR'ing with -1, then we should emit a one's complement
1658 instead. This way the combiner will notice logical operations
1659 such as ANDN later on and substitute. */
1660 if ((low_bits & 0x3ff) == 0x3ff)
1661 {
1662 emit_insn (gen_rtx_SET (VOIDmode, op0,
1663 gen_rtx_NOT (DImode, temp)));
1664 }
1665 else
1666 {
1667 emit_insn (gen_rtx_SET (VOIDmode, op0,
1668 gen_safe_XOR64 (temp,
fb124916 1669 (-(HOST_WIDE_INT)0x400
1670 | (low_bits & 0x3ff)))));
0cbaa167 1671 }
1672 }
998032ba 1673}
6dac3578 1674
35415df4 1675static void sparc_emit_set_const64_quick2
32bd1bda 1676 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT,
35415df4 1677 unsigned HOST_WIDE_INT, int));
1678
998032ba 1679static void
1680sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1681 rtx op0;
1682 rtx temp;
35415df4 1683 unsigned HOST_WIDE_INT high_bits;
1684 unsigned HOST_WIDE_INT low_immediate;
998032ba 1685 int shift_count;
1686{
1687 rtx temp2 = op0;
6dac3578 1688
998032ba 1689 if ((high_bits & 0xfffffc00) != 0)
1690 {
8703a12c 1691 sparc_emit_set_safe_HIGH64 (temp, high_bits);
998032ba 1692 if ((high_bits & ~0xfffffc00) != 0)
8703a12c 1693 emit_insn (gen_rtx_SET (VOIDmode, op0,
1694 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
6dac3578 1695 else
998032ba 1696 temp2 = temp;
6dac3578 1697 }
1698 else
1699 {
19e6708e 1700 emit_insn (gen_safe_SET64 (temp, high_bits));
998032ba 1701 temp2 = temp;
1702 }
6dac3578 1703
8eba0400 1704 /* Now shift it up into place. */
8703a12c 1705 emit_insn (gen_rtx_SET (VOIDmode, op0,
998032ba 1706 gen_rtx_ASHIFT (DImode, temp2,
1707 GEN_INT (shift_count))));
6dac3578 1708
998032ba 1709 /* If there is a low immediate part piece, finish up by
1710 putting that in as well. */
1711 if (low_immediate != 0)
8703a12c 1712 emit_insn (gen_rtx_SET (VOIDmode, op0,
1713 gen_safe_OR64 (op0, low_immediate)));
823baf68 1714}
1715
35415df4 1716static void sparc_emit_set_const64_longway
32bd1bda 1717 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
35415df4 1718
998032ba 1719/* Full 64-bit constant decomposition. Even though this is the
1720 'worst' case, we still optimize a few things away. */
1721static void
1722sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1723 rtx op0;
1724 rtx temp;
35415df4 1725 unsigned HOST_WIDE_INT high_bits;
1726 unsigned HOST_WIDE_INT low_bits;
823baf68 1727{
998032ba 1728 rtx sub_temp;
5104a735 1729
998032ba 1730 if (reload_in_progress || reload_completed)
1731 sub_temp = op0;
1732 else
1733 sub_temp = gen_reg_rtx (DImode);
1734
1735 if ((high_bits & 0xfffffc00) != 0)
1736 {
8703a12c 1737 sparc_emit_set_safe_HIGH64 (temp, high_bits);
998032ba 1738 if ((high_bits & ~0xfffffc00) != 0)
8703a12c 1739 emit_insn (gen_rtx_SET (VOIDmode,
998032ba 1740 sub_temp,
8703a12c 1741 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
998032ba 1742 else
1743 sub_temp = temp;
1744 }
1745 else
823baf68 1746 {
19e6708e 1747 emit_insn (gen_safe_SET64 (temp, high_bits));
998032ba 1748 sub_temp = temp;
823baf68 1749 }
5104a735 1750
998032ba 1751 if (!reload_in_progress && !reload_completed)
367242d3 1752 {
998032ba 1753 rtx temp2 = gen_reg_rtx (DImode);
1754 rtx temp3 = gen_reg_rtx (DImode);
1755 rtx temp4 = gen_reg_rtx (DImode);
367242d3 1756
8703a12c 1757 emit_insn (gen_rtx_SET (VOIDmode, temp4,
998032ba 1758 gen_rtx_ASHIFT (DImode, sub_temp,
1759 GEN_INT (32))));
5104a735 1760
8703a12c 1761 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
998032ba 1762 if ((low_bits & ~0xfffffc00) != 0)
19e6708e 1763 {
1764 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1765 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1766 emit_insn (gen_rtx_SET (VOIDmode, op0,
1767 gen_rtx_PLUS (DImode, temp4, temp3)));
1768 }
1769 else
1770 {
1771 emit_insn (gen_rtx_SET (VOIDmode, op0,
1772 gen_rtx_PLUS (DImode, temp4, temp2)));
1773 }
367242d3 1774 }
998032ba 1775 else
1776 {
8703a12c 1777 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1778 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1779 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
998032ba 1780 int to_shift = 12;
367242d3 1781
998032ba 1782 /* We are in the middle of reload, so this is really
1783 painful. However we do still make an attempt to
0cbaa167 1784 avoid emitting truly stupid code. */
998032ba 1785 if (low1 != const0_rtx)
1786 {
8703a12c 1787 emit_insn (gen_rtx_SET (VOIDmode, op0,
998032ba 1788 gen_rtx_ASHIFT (DImode, sub_temp,
35415df4 1789 GEN_INT (to_shift))));
8703a12c 1790 emit_insn (gen_rtx_SET (VOIDmode, op0,
998032ba 1791 gen_rtx_IOR (DImode, op0, low1)));
1792 sub_temp = op0;
1793 to_shift = 12;
1794 }
1795 else
1796 {
1797 to_shift += 12;
1798 }
1799 if (low2 != const0_rtx)
1800 {
8703a12c 1801 emit_insn (gen_rtx_SET (VOIDmode, op0,
998032ba 1802 gen_rtx_ASHIFT (DImode, sub_temp,
1803 GEN_INT (to_shift))));
8703a12c 1804 emit_insn (gen_rtx_SET (VOIDmode, op0,
998032ba 1805 gen_rtx_IOR (DImode, op0, low2)));
1806 sub_temp = op0;
1807 to_shift = 8;
1808 }
1809 else
1810 {
1811 to_shift += 8;
1812 }
8703a12c 1813 emit_insn (gen_rtx_SET (VOIDmode, op0,
998032ba 1814 gen_rtx_ASHIFT (DImode, sub_temp,
1815 GEN_INT (to_shift))));
1816 if (low3 != const0_rtx)
8703a12c 1817 emit_insn (gen_rtx_SET (VOIDmode, op0,
998032ba 1818 gen_rtx_IOR (DImode, op0, low3)));
8eba0400 1819 /* phew... */
998032ba 1820 }
367242d3 1821}
1822
8eba0400 1823/* Analyze a 64-bit constant for certain properties. */
35415df4 1824static void analyze_64bit_constant
32bd1bda 1825 PARAMS ((unsigned HOST_WIDE_INT,
35415df4 1826 unsigned HOST_WIDE_INT,
1827 int *, int *, int *));
1828
998032ba 1829static void
1830analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
35415df4 1831 unsigned HOST_WIDE_INT high_bits, low_bits;
998032ba 1832 int *hbsp, *lbsp, *abbasp;
823baf68 1833{
998032ba 1834 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1835 int i;
823baf68 1836
998032ba 1837 lowest_bit_set = highest_bit_set = -1;
1838 i = 0;
1839 do
823baf68 1840 {
998032ba 1841 if ((lowest_bit_set == -1)
1842 && ((low_bits >> i) & 1))
1843 lowest_bit_set = i;
1844 if ((highest_bit_set == -1)
1845 && ((high_bits >> (32 - i - 1)) & 1))
1846 highest_bit_set = (64 - i - 1);
1847 }
1848 while (++i < 32
1849 && ((highest_bit_set == -1)
1850 || (lowest_bit_set == -1)));
1851 if (i == 32)
1852 {
1853 i = 0;
1854 do
823baf68 1855 {
998032ba 1856 if ((lowest_bit_set == -1)
1857 && ((high_bits >> i) & 1))
1858 lowest_bit_set = i + 32;
1859 if ((highest_bit_set == -1)
1860 && ((low_bits >> (32 - i - 1)) & 1))
1861 highest_bit_set = 32 - i - 1;
823baf68 1862 }
998032ba 1863 while (++i < 32
1864 && ((highest_bit_set == -1)
1865 || (lowest_bit_set == -1)));
1866 }
1867 /* If there are no bits set this should have gone out
1868 as one instruction! */
1869 if (lowest_bit_set == -1
1870 || highest_bit_set == -1)
8703a12c 1871 abort ();
998032ba 1872 all_bits_between_are_set = 1;
1873 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1874 {
1875 if (i < 32)
1876 {
1877 if ((low_bits & (1 << i)) != 0)
1878 continue;
1879 }
1880 else
1881 {
1882 if ((high_bits & (1 << (i - 32))) != 0)
1883 continue;
1884 }
1885 all_bits_between_are_set = 0;
1886 break;
823baf68 1887 }
998032ba 1888 *hbsp = highest_bit_set;
1889 *lbsp = lowest_bit_set;
1890 *abbasp = all_bits_between_are_set;
823baf68 1891}
1ee01ec7 1892
35415df4 1893static int const64_is_2insns
32bd1bda 1894 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
35415df4 1895
998032ba 1896static int
1897const64_is_2insns (high_bits, low_bits)
35415df4 1898 unsigned HOST_WIDE_INT high_bits, low_bits;
998032ba 1899{
1900 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
367242d3 1901
998032ba 1902 if (high_bits == 0
3dcaebeb 1903 || high_bits == 0xffffffff)
998032ba 1904 return 1;
1ee01ec7 1905
998032ba 1906 analyze_64bit_constant (high_bits, low_bits,
1907 &highest_bit_set, &lowest_bit_set,
1908 &all_bits_between_are_set);
1ee01ec7 1909
19e6708e 1910 if ((highest_bit_set == 63
1911 || lowest_bit_set == 0)
998032ba 1912 && all_bits_between_are_set != 0)
1913 return 1;
1ee01ec7 1914
8703a12c 1915 if ((highest_bit_set - lowest_bit_set) < 21)
1916 return 1;
1917
1ee01ec7 1918 return 0;
1919}
1920
35415df4 1921static unsigned HOST_WIDE_INT create_simple_focus_bits
32bd1bda 1922 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
bd814422 1923 int, int));
35415df4 1924
1925static unsigned HOST_WIDE_INT
bd814422 1926create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
35415df4 1927 unsigned HOST_WIDE_INT high_bits, low_bits;
bd814422 1928 int lowest_bit_set, shift;
823baf68 1929{
19e6708e 1930 HOST_WIDE_INT hi, lo;
823baf68 1931
998032ba 1932 if (lowest_bit_set < 32)
1933 {
1934 lo = (low_bits >> lowest_bit_set) << shift;
1935 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1936 }
1937 else
1938 {
1939 lo = 0;
1940 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1941 }
1942 if (hi & lo)
8703a12c 1943 abort ();
998032ba 1944 return (hi | lo);
1945}
823baf68 1946
998032ba 1947/* Here we are sure to be arch64 and this is an integer constant
1948 being loaded into a register. Emit the most efficient
1949 insn sequence possible. Detection of all the 1-insn cases
1950 has been done already. */
1951void
1952sparc_emit_set_const64 (op0, op1)
1953 rtx op0;
1954 rtx op1;
1955{
35415df4 1956 unsigned HOST_WIDE_INT high_bits, low_bits;
998032ba 1957 int lowest_bit_set, highest_bit_set;
1958 int all_bits_between_are_set;
998032ba 1959 rtx temp;
823baf68 1960
998032ba 1961 /* Sanity check that we know what we are working with. */
c5b3ce24 1962 if (! TARGET_ARCH64)
8703a12c 1963 abort ();
b0344bad 1964
c5b3ce24 1965 if (GET_CODE (op0) != SUBREG)
1966 {
1967 if (GET_CODE (op0) != REG
1968 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1969 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1970 abort ();
1971 }
1972
19e6708e 1973 if (reload_in_progress || reload_completed)
1974 temp = op0;
1975 else
1976 temp = gen_reg_rtx (DImode);
1977
998032ba 1978 if (GET_CODE (op1) != CONST_DOUBLE
1979 && GET_CODE (op1) != CONST_INT)
1980 {
ec57cca3 1981 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1982 return;
998032ba 1983 }
823baf68 1984
998032ba 1985 if (GET_CODE (op1) == CONST_DOUBLE)
1986 {
1987#if HOST_BITS_PER_WIDE_INT == 64
35415df4 1988 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
998032ba 1989 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1990#else
1991 high_bits = CONST_DOUBLE_HIGH (op1);
1992 low_bits = CONST_DOUBLE_LOW (op1);
1993#endif
823baf68 1994 }
998032ba 1995 else
823baf68 1996 {
998032ba 1997#if HOST_BITS_PER_WIDE_INT == 64
35415df4 1998 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
998032ba 1999 low_bits = (INTVAL (op1) & 0xffffffff);
2000#else
2001 high_bits = ((INTVAL (op1) < 0) ?
2002 0xffffffff :
2003 0x00000000);
2004 low_bits = INTVAL (op1);
2005#endif
2006 }
823baf68 2007
998032ba 2008 /* low_bits bits 0 --> 31
2009 high_bits bits 32 --> 63 */
823baf68 2010
998032ba 2011 analyze_64bit_constant (high_bits, low_bits,
2012 &highest_bit_set, &lowest_bit_set,
2013 &all_bits_between_are_set);
2014
2015 /* First try for a 2-insn sequence. */
2016
2017 /* These situations are preferred because the optimizer can
2018 * do more things with them:
2019 * 1) mov -1, %reg
2020 * sllx %reg, shift, %reg
2021 * 2) mov -1, %reg
2022 * srlx %reg, shift, %reg
2023 * 3) mov some_small_const, %reg
2024 * sllx %reg, shift, %reg
2025 */
2026 if (((highest_bit_set == 63
2027 || lowest_bit_set == 0)
2028 && all_bits_between_are_set != 0)
35415df4 2029 || ((highest_bit_set - lowest_bit_set) < 12))
998032ba 2030 {
8703a12c 2031 HOST_WIDE_INT the_const = -1;
998032ba 2032 int shift = lowest_bit_set;
2033
19e6708e 2034 if ((highest_bit_set != 63
2035 && lowest_bit_set != 0)
2036 || all_bits_between_are_set == 0)
823baf68 2037 {
998032ba 2038 the_const =
8703a12c 2039 create_simple_focus_bits (high_bits, low_bits,
8703a12c 2040 lowest_bit_set, 0);
823baf68 2041 }
998032ba 2042 else if (lowest_bit_set == 0)
8703a12c 2043 shift = -(63 - highest_bit_set);
998032ba 2044
19e6708e 2045 if (! SPARC_SIMM13_P (the_const))
2046 abort ();
2047
8703a12c 2048 emit_insn (gen_safe_SET64 (temp, the_const));
998032ba 2049 if (shift > 0)
8703a12c 2050 emit_insn (gen_rtx_SET (VOIDmode,
998032ba 2051 op0,
2052 gen_rtx_ASHIFT (DImode,
2053 temp,
2054 GEN_INT (shift))));
2055 else if (shift < 0)
8703a12c 2056 emit_insn (gen_rtx_SET (VOIDmode,
998032ba 2057 op0,
8703a12c 2058 gen_rtx_LSHIFTRT (DImode,
998032ba 2059 temp,
2060 GEN_INT (-shift))));
823baf68 2061 else
2062 abort ();
998032ba 2063 return;
2064 }
823baf68 2065
998032ba 2066 /* Now a range of 22 or less bits set somewhere.
2067 * 1) sethi %hi(focus_bits), %reg
2068 * sllx %reg, shift, %reg
2069 * 2) sethi %hi(focus_bits), %reg
2070 * srlx %reg, shift, %reg
2071 */
35415df4 2072 if ((highest_bit_set - lowest_bit_set) < 21)
998032ba 2073 {
35415df4 2074 unsigned HOST_WIDE_INT focus_bits =
998032ba 2075 create_simple_focus_bits (high_bits, low_bits,
bd814422 2076 lowest_bit_set, 10);
19e6708e 2077
2078 if (! SPARC_SETHI_P (focus_bits))
2079 abort ();
2080
8703a12c 2081 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
998032ba 2082
8703a12c 2083 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
998032ba 2084 if (lowest_bit_set < 10)
8703a12c 2085 emit_insn (gen_rtx_SET (VOIDmode,
998032ba 2086 op0,
8703a12c 2087 gen_rtx_LSHIFTRT (DImode, temp,
998032ba 2088 GEN_INT (10 - lowest_bit_set))));
8703a12c 2089 else if (lowest_bit_set > 10)
2090 emit_insn (gen_rtx_SET (VOIDmode,
998032ba 2091 op0,
2092 gen_rtx_ASHIFT (DImode, temp,
2093 GEN_INT (lowest_bit_set - 10))));
2094 else
8703a12c 2095 abort ();
998032ba 2096 return;
2097 }
2098
2099 /* 1) sethi %hi(low_bits), %reg
2100 * or %reg, %lo(low_bits), %reg
2101 * 2) sethi %hi(~low_bits), %reg
2102 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2103 */
2104 if (high_bits == 0
35415df4 2105 || high_bits == 0xffffffff)
ec57cca3 2106 {
2107 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2108 (high_bits == 0xffffffff));
2109 return;
2110 }
998032ba 2111
19e6708e 2112 /* Now, try 3-insn sequences. */
2113
998032ba 2114 /* 1) sethi %hi(high_bits), %reg
2115 * or %reg, %lo(high_bits), %reg
2116 * sllx %reg, 32, %reg
2117 */
19e6708e 2118 if (low_bits == 0)
ec57cca3 2119 {
19e6708e 2120 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
ec57cca3 2121 return;
2122 }
998032ba 2123
19e6708e 2124 /* We may be able to do something quick
2125 when the constant is negated, so try that. */
998032ba 2126 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2127 (~low_bits) & 0xfffffc00))
2128 {
0cbaa167 2129 /* NOTE: The trailing bits get XOR'd so we need the
2130 non-negated bits, not the negated ones. */
2131 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
998032ba 2132
2133 if ((((~high_bits) & 0xffffffff) == 0
2134 && ((~low_bits) & 0x80000000) == 0)
2135 || (((~high_bits) & 0xffffffff) == 0xffffffff
2136 && ((~low_bits) & 0x80000000) != 0))
823baf68 2137 {
0cbaa167 2138 int fast_int = (~low_bits & 0xffffffff);
998032ba 2139
0cbaa167 2140 if ((SPARC_SETHI_P (fast_int)
2141 && (~high_bits & 0xffffffff) == 0)
2142 || SPARC_SIMM13_P (fast_int))
8703a12c 2143 emit_insn (gen_safe_SET64 (temp, fast_int));
823baf68 2144 else
8703a12c 2145 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
823baf68 2146 }
998032ba 2147 else
2148 {
2149 rtx negated_const;
2150#if HOST_BITS_PER_WIDE_INT == 64
2151 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2152 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2153#else
2ff23ed0 2154 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2155 (~high_bits) & 0xffffffff,
2156 DImode);
998032ba 2157#endif
2158 sparc_emit_set_const64 (temp, negated_const);
2159 }
0cbaa167 2160
2161 /* If we are XOR'ing with -1, then we should emit a one's complement
2162 instead. This way the combiner will notice logical operations
2163 such as ANDN later on and substitute. */
2164 if (trailing_bits == 0x3ff)
2165 {
2166 emit_insn (gen_rtx_SET (VOIDmode, op0,
2167 gen_rtx_NOT (DImode, temp)));
2168 }
2169 else
2170 {
2171 emit_insn (gen_rtx_SET (VOIDmode,
2172 op0,
2173 gen_safe_XOR64 (temp,
2174 (-0x400 | trailing_bits))));
2175 }
998032ba 2176 return;
823baf68 2177 }
823baf68 2178
998032ba 2179 /* 1) sethi %hi(xxx), %reg
2180 * or %reg, %lo(xxx), %reg
2181 * sllx %reg, yyy, %reg
19e6708e 2182 *
2183 * ??? This is just a generalized version of the low_bits==0
2184 * thing above, FIXME...
998032ba 2185 */
2186 if ((highest_bit_set - lowest_bit_set) < 32)
2187 {
19e6708e 2188 unsigned HOST_WIDE_INT focus_bits =
2189 create_simple_focus_bits (high_bits, low_bits,
bd814422 2190 lowest_bit_set, 0);
823baf68 2191
998032ba 2192 /* We can't get here in this state. */
2193 if (highest_bit_set < 32
2194 || lowest_bit_set >= 32)
8703a12c 2195 abort ();
b0344bad 2196
998032ba 2197 /* So what we know is that the set bits straddle the
2198 middle of the 64-bit word. */
ec57cca3 2199 sparc_emit_set_const64_quick2 (op0, temp,
2200 focus_bits, 0,
2201 lowest_bit_set);
2202 return;
998032ba 2203 }
220345e0 2204
19e6708e 2205 /* 1) sethi %hi(high_bits), %reg
2206 * or %reg, %lo(high_bits), %reg
2207 * sllx %reg, 32, %reg
2208 * or %reg, low_bits, %reg
2209 */
2210 if (SPARC_SIMM13_P(low_bits)
2211 && ((int)low_bits > 0))
2212 {
2213 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2214 return;
2215 }
2216
8eba0400 2217 /* The easiest way when all else fails, is full decomposition. */
998032ba 2218#if 0
2219 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2220 high_bits, low_bits, ~high_bits, ~low_bits);
2221#endif
2222 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
220345e0 2223}
2224
9312a956 2225/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2226 return the mode to be used for the comparison. For floating-point,
2227 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2228 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2229 processing is needed. */
2230
2231enum machine_mode
2232select_cc_mode (op, x, y)
2233 enum rtx_code op;
2234 rtx x;
2235 rtx y ATTRIBUTE_UNUSED;
2236{
2237 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2238 {
2239 switch (op)
2240 {
2241 case EQ:
2242 case NE:
2243 case UNORDERED:
2244 case ORDERED:
2245 case UNLT:
2246 case UNLE:
2247 case UNGT:
2248 case UNGE:
2249 case UNEQ:
79777bad 2250 case LTGT:
9312a956 2251 return CCFPmode;
2252
2253 case LT:
2254 case LE:
2255 case GT:
2256 case GE:
2257 return CCFPEmode;
2258
2259 default:
2260 abort ();
2261 }
2262 }
2263 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2264 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2265 {
2266 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2267 return CCX_NOOVmode;
2268 else
2269 return CC_NOOVmode;
2270 }
2271 else
2272 {
2273 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2274 return CCXmode;
2275 else
2276 return CCmode;
2277 }
2278}
2279
998032ba 2280/* X and Y are two things to compare using CODE. Emit the compare insn and
2281 return the rtx for the cc reg in the proper mode. */
220345e0 2282
998032ba 2283rtx
2284gen_compare_reg (code, x, y)
2285 enum rtx_code code;
2286 rtx x, y;
220345e0 2287{
998032ba 2288 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2289 rtx cc_reg;
220345e0 2290
998032ba 2291 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2292 fcc regs (cse can't tell they're really call clobbered regs and will
2293 remove a duplicate comparison even if there is an intervening function
2294 call - it will then try to reload the cc reg via an int reg which is why
2295 we need the movcc patterns). It is possible to provide the movcc
2296 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2297 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2298 to tell cse that CCFPE mode registers (even pseudos) are call
2299 clobbered. */
220345e0 2300
998032ba 2301 /* ??? This is an experiment. Rather than making changes to cse which may
2302 or may not be easy/clean, we do our own cse. This is possible because
2303 we will generate hard registers. Cse knows they're call clobbered (it
2304 doesn't know the same thing about pseudos). If we guess wrong, no big
2305 deal, but if we win, great! */
220345e0 2306
998032ba 2307 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2308#if 1 /* experiment */
367242d3 2309 {
998032ba 2310 int reg;
2311 /* We cycle through the registers to ensure they're all exercised. */
2312 static int next_fcc_reg = 0;
2313 /* Previous x,y for each fcc reg. */
2314 static rtx prev_args[4][2];
367242d3 2315
998032ba 2316 /* Scan prev_args for x,y. */
2317 for (reg = 0; reg < 4; reg++)
2318 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2319 break;
2320 if (reg == 4)
2321 {
2322 reg = next_fcc_reg;
2323 prev_args[reg][0] = x;
2324 prev_args[reg][1] = y;
2325 next_fcc_reg = (next_fcc_reg + 1) & 3;
2326 }
2327 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
367242d3 2328 }
998032ba 2329#else
2330 cc_reg = gen_reg_rtx (mode);
2331#endif /* ! experiment */
2332 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2333 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2334 else
2335 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
367242d3 2336
998032ba 2337 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2338 gen_rtx_COMPARE (mode, x, y)));
220345e0 2339
998032ba 2340 return cc_reg;
2341}
220345e0 2342
998032ba 2343/* This function is used for v9 only.
2344 CODE is the code for an Scc's comparison.
2345 OPERANDS[0] is the target of the Scc insn.
2346 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2347 been generated yet).
220345e0 2348
998032ba 2349 This function is needed to turn
823baf68 2350
998032ba 2351 (set (reg:SI 110)
2352 (gt (reg:CCX 100 %icc)
2353 (const_int 0)))
2354 into
2355 (set (reg:SI 110)
2356 (gt:DI (reg:CCX 100 %icc)
2357 (const_int 0)))
2358
2359 IE: The instruction recognizer needs to see the mode of the comparison to
2360 find the right instruction. We could use "gt:DI" right in the
2361 define_expand, but leaving it out allows us to handle DI, SI, etc.
823baf68 2362
998032ba 2363 We refer to the global sparc compare operands sparc_compare_op0 and
2364 sparc_compare_op1. */
823baf68 2365
2366int
998032ba 2367gen_v9_scc (compare_code, operands)
2368 enum rtx_code compare_code;
2369 register rtx *operands;
823baf68 2370{
998032ba 2371 rtx temp, op0, op1;
823baf68 2372
998032ba 2373 if (! TARGET_ARCH64
2374 && (GET_MODE (sparc_compare_op0) == DImode
2375 || GET_MODE (operands[0]) == DImode))
2376 return 0;
710ab3ed 2377
075f5855 2378 op0 = sparc_compare_op0;
998032ba 2379 op1 = sparc_compare_op1;
2380
2381 /* Try to use the movrCC insns. */
2382 if (TARGET_ARCH64
2383 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2384 && op1 == const0_rtx
2385 && v9_regcmp_p (compare_code))
823baf68 2386 {
998032ba 2387 /* Special case for op0 != 0. This can be done with one instruction if
075f5855 2388 operands[0] == sparc_compare_op0. */
998032ba 2389
2390 if (compare_code == NE
2391 && GET_MODE (operands[0]) == DImode
075f5855 2392 && rtx_equal_p (op0, operands[0]))
823baf68 2393 {
998032ba 2394 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2395 gen_rtx_IF_THEN_ELSE (DImode,
2396 gen_rtx_fmt_ee (compare_code, DImode,
2397 op0, const0_rtx),
2398 const1_rtx,
2399 operands[0])));
823baf68 2400 return 1;
2401 }
998032ba 2402
075f5855 2403 if (reg_overlap_mentioned_p (operands[0], op0))
2404 {
2405 /* Handle the case where operands[0] == sparc_compare_op0.
2406 We "early clobber" the result. */
2407 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2408 emit_move_insn (op0, sparc_compare_op0);
2409 }
2410
998032ba 2411 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2412 if (GET_MODE (op0) != DImode)
823baf68 2413 {
998032ba 2414 temp = gen_reg_rtx (DImode);
2415 convert_move (temp, op0, 0);
823baf68 2416 }
998032ba 2417 else
2418 temp = op0;
2419 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2420 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2421 gen_rtx_fmt_ee (compare_code, DImode,
2422 temp, const0_rtx),
2423 const1_rtx,
2424 operands[0])));
b0344bad 2425 return 1;
2426 }
998032ba 2427 else
823baf68 2428 {
998032ba 2429 operands[1] = gen_compare_reg (compare_code, op0, op1);
823baf68 2430
998032ba 2431 switch (GET_MODE (operands[1]))
823baf68 2432 {
998032ba 2433 case CCmode :
2434 case CCXmode :
2435 case CCFPEmode :
2436 case CCFPmode :
2437 break;
2438 default :
2439 abort ();
823baf68 2440 }
998032ba 2441 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2442 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2443 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2444 gen_rtx_fmt_ee (compare_code,
2445 GET_MODE (operands[1]),
2446 operands[1], const0_rtx),
2447 const1_rtx, operands[0])));
2448 return 1;
823baf68 2449 }
823baf68 2450}
279e8405 2451
998032ba 2452/* Emit a conditional jump insn for the v9 architecture using comparison code
2453 CODE and jump target LABEL.
2454 This function exists to take advantage of the v9 brxx insns. */
823baf68 2455
998032ba 2456void
2457emit_v9_brxx_insn (code, op0, label)
2458 enum rtx_code code;
2459 rtx op0, label;
823baf68 2460{
998032ba 2461 emit_jump_insn (gen_rtx_SET (VOIDmode,
2462 pc_rtx,
2463 gen_rtx_IF_THEN_ELSE (VOIDmode,
2464 gen_rtx_fmt_ee (code, GET_MODE (op0),
2465 op0, const0_rtx),
2466 gen_rtx_LABEL_REF (VOIDmode, label),
2467 pc_rtx)));
2468}
ab151623 2469
2470/* Generate a DFmode part of a hard TFmode register.
2471 REG is the TFmode hard register, LOW is 1 for the
2472 low 64bit of the register and 0 otherwise.
2473 */
2474rtx
2475gen_df_reg (reg, low)
2476 rtx reg;
2477 int low;
2478{
2479 int regno = REGNO (reg);
2480
2481 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
60310566 2482 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
ab151623 2483 return gen_rtx_REG (DFmode, regno);
2484}
998032ba 2485\f
c00088b6 2486/* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2487 Unlike normal calls, TFmode operands are passed by reference. It is
2488 assumed that no more than 3 operands are required. */
2489
2490static void
2491emit_soft_tfmode_libcall (func_name, nargs, operands)
2492 const char *func_name;
2493 int nargs;
2494 rtx *operands;
2495{
2496 rtx ret_slot = NULL, arg[3], func_sym;
3044c70d 2497 int i;
c00088b6 2498
2499 /* We only expect to be called for conversions, unary, and binary ops. */
2500 if (nargs < 2 || nargs > 3)
2501 abort ();
2502
2503 for (i = 0; i < nargs; ++i)
2504 {
2505 rtx this_arg = operands[i];
2506 rtx this_slot;
2507
2508 /* TFmode arguments and return values are passed by reference. */
2509 if (GET_MODE (this_arg) == TFmode)
2510 {
3044c70d 2511 int force_stack_temp;
2512
2513 force_stack_temp = 0;
2514 if (TARGET_BUGGY_QP_LIB && i == 0)
2515 force_stack_temp = 1;
2516
2517 if (GET_CODE (this_arg) == MEM
2518 && ! force_stack_temp)
2519 this_arg = XEXP (this_arg, 0);
2520 else if (CONSTANT_P (this_arg)
2521 && ! force_stack_temp)
c00088b6 2522 {
2523 this_slot = force_const_mem (TFmode, this_arg);
2524 this_arg = XEXP (this_slot, 0);
2525 }
2526 else
2527 {
2528 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2529
2530 /* Operand 0 is the return value. We'll copy it out later. */
2531 if (i > 0)
2532 emit_move_insn (this_slot, this_arg);
2533 else
2534 ret_slot = this_slot;
2535
2536 this_arg = XEXP (this_slot, 0);
2537 }
2538 }
2539
2540 arg[i] = this_arg;
2541 }
2542
2543 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2544
2545 if (GET_MODE (operands[0]) == TFmode)
2546 {
2547 if (nargs == 2)
2548 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2549 arg[0], GET_MODE (arg[0]),
2550 arg[1], GET_MODE (arg[1]));
2551 else
2552 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2553 arg[0], GET_MODE (arg[0]),
2554 arg[1], GET_MODE (arg[1]),
2555 arg[2], GET_MODE (arg[2]));
2556
2557 if (ret_slot)
2558 emit_move_insn (operands[0], ret_slot);
2559 }
2560 else
2561 {
2562 rtx ret;
2563
2564 if (nargs != 2)
2565 abort ();
2566
2567 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2568 GET_MODE (operands[0]), 1,
2569 arg[1], GET_MODE (arg[1]));
2570
2571 if (ret != operands[0])
2572 emit_move_insn (operands[0], ret);
2573 }
2574}
2575
2576/* Expand soft-float TFmode calls to sparc abi routines. */
2577
2578static void
2579emit_soft_tfmode_binop (code, operands)
2580 enum rtx_code code;
2581 rtx *operands;
2582{
2583 const char *func;
2584
2585 switch (code)
2586 {
2587 case PLUS:
2588 func = "_Qp_add";
2589 break;
2590 case MINUS:
2591 func = "_Qp_sub";
2592 break;
2593 case MULT:
2594 func = "_Qp_mul";
2595 break;
2596 case DIV:
2597 func = "_Qp_div";
2598 break;
2599 default:
2600 abort ();
2601 }
2602
2603 emit_soft_tfmode_libcall (func, 3, operands);
2604}
2605
2606static void
2607emit_soft_tfmode_unop (code, operands)
2608 enum rtx_code code;
2609 rtx *operands;
2610{
2611 const char *func;
2612
2613 switch (code)
2614 {
2615 case SQRT:
2616 func = "_Qp_sqrt";
2617 break;
2618 default:
2619 abort ();
2620 }
2621
2622 emit_soft_tfmode_libcall (func, 2, operands);
2623}
2624
2625static void
2626emit_soft_tfmode_cvt (code, operands)
2627 enum rtx_code code;
2628 rtx *operands;
2629{
2630 const char *func;
2631
2632 switch (code)
2633 {
2634 case FLOAT_EXTEND:
2635 switch (GET_MODE (operands[1]))
2636 {
2637 case SFmode:
2638 func = "_Qp_stoq";
2639 break;
2640 case DFmode:
2641 func = "_Qp_dtoq";
2642 break;
2643 default:
2644 abort ();
2645 }
2646 break;
2647
2648 case FLOAT_TRUNCATE:
2649 switch (GET_MODE (operands[0]))
2650 {
2651 case SFmode:
2652 func = "_Qp_qtos";
2653 break;
2654 case DFmode:
2655 func = "_Qp_qtod";
2656 break;
2657 default:
2658 abort ();
2659 }
2660 break;
2661
2662 case FLOAT:
2663 switch (GET_MODE (operands[1]))
2664 {
2665 case SImode:
2666 func = "_Qp_itoq";
2667 break;
2668 case DImode:
2669 func = "_Qp_xtoq";
2670 break;
2671 default:
2672 abort ();
2673 }
2674 break;
2675
2676 case UNSIGNED_FLOAT:
2677 switch (GET_MODE (operands[1]))
2678 {
2679 case SImode:
2680 func = "_Qp_uitoq";
2681 break;
2682 case DImode:
2683 func = "_Qp_uxtoq";
2684 break;
2685 default:
2686 abort ();
2687 }
2688 break;
2689
2690 case FIX:
2691 switch (GET_MODE (operands[0]))
2692 {
2693 case SImode:
2694 func = "_Qp_qtoi";
2695 break;
2696 case DImode:
2697 func = "_Qp_qtox";
2698 break;
2699 default:
2700 abort ();
2701 }
2702 break;
2703
2704 case UNSIGNED_FIX:
2705 switch (GET_MODE (operands[0]))
2706 {
2707 case SImode:
2708 func = "_Qp_qtoui";
2709 break;
2710 case DImode:
2711 func = "_Qp_qtoux";
2712 break;
2713 default:
2714 abort ();
2715 }
2716 break;
2717
2718 default:
2719 abort ();
2720 }
2721
2722 emit_soft_tfmode_libcall (func, 2, operands);
2723}
2724
2725/* Expand a hard-float tfmode operation. All arguments must be in
2726 registers. */
2727
2728static void
2729emit_hard_tfmode_operation (code, operands)
2730 enum rtx_code code;
2731 rtx *operands;
2732{
2733 rtx op, dest;
2734
2735 if (GET_RTX_CLASS (code) == '1')
2736 {
2737 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2738 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2739 }
2740 else
2741 {
2742 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2743 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2744 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2745 operands[1], operands[2]);
2746 }
2747
2748 if (register_operand (operands[0], VOIDmode))
2749 dest = operands[0];
2750 else
2751 dest = gen_reg_rtx (GET_MODE (operands[0]));
2752
2753 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2754
2755 if (dest != operands[0])
2756 emit_move_insn (operands[0], dest);
2757}
2758
2759void
2760emit_tfmode_binop (code, operands)
2761 enum rtx_code code;
2762 rtx *operands;
2763{
2764 if (TARGET_HARD_QUAD)
2765 emit_hard_tfmode_operation (code, operands);
2766 else
2767 emit_soft_tfmode_binop (code, operands);
2768}
2769
2770void
2771emit_tfmode_unop (code, operands)
2772 enum rtx_code code;
2773 rtx *operands;
2774{
2775 if (TARGET_HARD_QUAD)
2776 emit_hard_tfmode_operation (code, operands);
2777 else
2778 emit_soft_tfmode_unop (code, operands);
2779}
2780
2781void
2782emit_tfmode_cvt (code, operands)
2783 enum rtx_code code;
2784 rtx *operands;
2785{
2786 if (TARGET_HARD_QUAD)
2787 emit_hard_tfmode_operation (code, operands);
2788 else
2789 emit_soft_tfmode_cvt (code, operands);
2790}
2791\f
998032ba 2792/* Return nonzero if a return peephole merging return with
2793 setting of output register is ok. */
2794int
2795leaf_return_peephole_ok ()
2796{
2797 return (actual_fsize == 0);
2798}
367242d3 2799
258103e3 2800/* Return nonzero if a branch/jump/call instruction will be emitting
2801 nop into its delay slot. */
2802
2803int
2804empty_delay_slot (insn)
2805 rtx insn;
2806{
2807 rtx seq;
2808
2809 /* If no previous instruction (should not happen), return true. */
2810 if (PREV_INSN (insn) == NULL)
2811 return 1;
2812
2813 seq = NEXT_INSN (PREV_INSN (insn));
2814 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2815 return 0;
2816
2817 return 1;
2818}
2819
998032ba 2820/* Return nonzero if TRIAL can go into the function epilogue's
2821 delay slot. SLOT is the slot we are trying to fill. */
823baf68 2822
998032ba 2823int
2824eligible_for_epilogue_delay (trial, slot)
2825 rtx trial;
2826 int slot;
2827{
2828 rtx pat, src;
279e8405 2829
998032ba 2830 if (slot >= 1)
2831 return 0;
279e8405 2832
998032ba 2833 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2834 return 0;
279e8405 2835
998032ba 2836 if (get_attr_length (trial) != 1)
2837 return 0;
279e8405 2838
5a1acad9 2839 /* If there are any call-saved registers, we should scan TRIAL if it
2840 does not reference them. For now just make it easy. */
2841 if (num_gfregs)
2842 return 0;
279e8405 2843
e4acc523 2844 /* If the function uses __builtin_eh_return, the eh_return machinery
2845 occupies the delay slot. */
2846 if (current_function_calls_eh_return)
2847 return 0;
2848
998032ba 2849 /* In the case of a true leaf function, anything can go into the delay slot.
2850 A delay slot only exists however if the frame size is zero, otherwise
2851 we will put an insn to adjust the stack after the return. */
b3b67b7c 2852 if (current_function_uses_only_leaf_regs)
279e8405 2853 {
998032ba 2854 if (leaf_return_peephole_ok ())
2855 return ((get_attr_in_uncond_branch_delay (trial)
2856 == IN_BRANCH_DELAY_TRUE));
2857 return 0;
279e8405 2858 }
279e8405 2859
998032ba 2860 pat = PATTERN (trial);
93fed860 2861
998032ba 2862 /* Otherwise, only operations which can be done in tandem with
5a1acad9 2863 a `restore' or `return' insn can go into the delay slot. */
998032ba 2864 if (GET_CODE (SET_DEST (pat)) != REG
998032ba 2865 || REGNO (SET_DEST (pat)) < 24)
2866 return 0;
93fed860 2867
a7ec4a7e 2868 /* If this instruction sets up floating point register and we have a return
2869 instruction, it can probably go in. But restore will not work
2870 with FP_REGS. */
2871 if (REGNO (SET_DEST (pat)) >= 32)
2872 {
2873 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2874 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2875 return 1;
2876 return 0;
2877 }
2878
998032ba 2879 /* The set of insns matched here must agree precisely with the set of
2880 patterns paired with a RETURN in sparc.md. */
93fed860 2881
998032ba 2882 src = SET_SRC (pat);
93fed860 2883
71d83a98 2884 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
e4e07cc6 2885 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2886 && arith_operand (src, GET_MODE (src)))
71d83a98 2887 {
2888 if (TARGET_ARCH64)
2889 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2890 else
2891 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2892 }
5a1acad9 2893
998032ba 2894 /* This matches "*return_di". */
e4e07cc6 2895 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2896 && arith_double_operand (src, GET_MODE (src)))
998032ba 2897 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
93fed860 2898
998032ba 2899 /* This matches "*return_sf_no_fpu". */
2900 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2901 && register_operand (src, SFmode))
2902 return 1;
5174a13e 2903
5a1acad9 2904 /* If we have return instruction, anything that does not use
2905 local or output registers and can go into a delay slot wins. */
2906 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2907 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2908 return 1;
2909
998032ba 2910 /* This matches "*return_addsi". */
2911 else if (GET_CODE (src) == PLUS
2912 && arith_operand (XEXP (src, 0), SImode)
2913 && arith_operand (XEXP (src, 1), SImode)
2914 && (register_operand (XEXP (src, 0), SImode)
2915 || register_operand (XEXP (src, 1), SImode)))
2916 return 1;
2917
2918 /* This matches "*return_adddi". */
2919 else if (GET_CODE (src) == PLUS
2920 && arith_double_operand (XEXP (src, 0), DImode)
2921 && arith_double_operand (XEXP (src, 1), DImode)
2922 && (register_operand (XEXP (src, 0), DImode)
2923 || register_operand (XEXP (src, 1), DImode)))
93fed860 2924 return 1;
93fed860 2925
5a1acad9 2926 /* This can match "*return_losum_[sd]i".
2927 Catch only some cases, so that return_losum* don't have
2928 to be too big. */
2929 else if (GET_CODE (src) == LO_SUM
2930 && ! TARGET_CM_MEDMID
2931 && ((register_operand (XEXP (src, 0), SImode)
2932 && immediate_operand (XEXP (src, 1), SImode))
2933 || (TARGET_ARCH64
2934 && register_operand (XEXP (src, 0), DImode)
2935 && immediate_operand (XEXP (src, 1), DImode))))
2936 return 1;
2937
2938 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2939 else if (GET_CODE (src) == ASHIFT
2940 && (register_operand (XEXP (src, 0), SImode)
2941 || register_operand (XEXP (src, 0), DImode))
2942 && XEXP (src, 1) == const1_rtx)
2943 return 1;
2944
93fed860 2945 return 0;
2946}
2947
7a8d641b 2948/* Return nonzero if TRIAL can go into the sibling call
2949 delay slot. */
2950
2951int
2952eligible_for_sibcall_delay (trial)
2953 rtx trial;
2954{
2955 rtx pat, src;
2956
2957 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2958 return 0;
2959
644a1400 2960 if (get_attr_length (trial) != 1)
7a8d641b 2961 return 0;
2962
2963 pat = PATTERN (trial);
2964
2965 if (current_function_uses_only_leaf_regs)
2966 {
2967 /* If the tail call is done using the call instruction,
2968 we have to restore %o7 in the delay slot. */
f3619338 2969 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
7a8d641b 2970 return 0;
2971
2972 /* %g1 is used to build the function address */
2973 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2974 return 0;
2975
2976 return 1;
2977 }
2978
2979 /* Otherwise, only operations which can be done in tandem with
2980 a `restore' insn can go into the delay slot. */
2981 if (GET_CODE (SET_DEST (pat)) != REG
2982 || REGNO (SET_DEST (pat)) < 24
2983 || REGNO (SET_DEST (pat)) >= 32)
2984 return 0;
2985
2986 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2987 in most cases. */
2988 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2989 return 0;
2990
2991 src = SET_SRC (pat);
2992
e4e07cc6 2993 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2994 && arith_operand (src, GET_MODE (src)))
7a8d641b 2995 {
2996 if (TARGET_ARCH64)
2997 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2998 else
2999 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3000 }
3001
e4e07cc6 3002 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3003 && arith_double_operand (src, GET_MODE (src)))
7a8d641b 3004 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3005
3006 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
3007 && register_operand (src, SFmode))
3008 return 1;
3009
3010 else if (GET_CODE (src) == PLUS
3011 && arith_operand (XEXP (src, 0), SImode)
3012 && arith_operand (XEXP (src, 1), SImode)
3013 && (register_operand (XEXP (src, 0), SImode)
3014 || register_operand (XEXP (src, 1), SImode)))
3015 return 1;
3016
3017 else if (GET_CODE (src) == PLUS
3018 && arith_double_operand (XEXP (src, 0), DImode)
3019 && arith_double_operand (XEXP (src, 1), DImode)
3020 && (register_operand (XEXP (src, 0), DImode)
3021 || register_operand (XEXP (src, 1), DImode)))
3022 return 1;
3023
3024 else if (GET_CODE (src) == LO_SUM
3025 && ! TARGET_CM_MEDMID
3026 && ((register_operand (XEXP (src, 0), SImode)
3027 && immediate_operand (XEXP (src, 1), SImode))
3028 || (TARGET_ARCH64
3029 && register_operand (XEXP (src, 0), DImode)
3030 && immediate_operand (XEXP (src, 1), DImode))))
3031 return 1;
3032
3033 else if (GET_CODE (src) == ASHIFT
3034 && (register_operand (XEXP (src, 0), SImode)
3035 || register_operand (XEXP (src, 0), DImode))
3036 && XEXP (src, 1) == const1_rtx)
3037 return 1;
3038
3039 return 0;
3040}
3041
998032ba 3042static int
3043check_return_regs (x)
3044 rtx x;
823baf68 3045{
998032ba 3046 switch (GET_CODE (x))
3047 {
3048 case REG:
3049 return IN_OR_GLOBAL_P (x);
823baf68 3050
998032ba 3051 case CONST_INT:
3052 case CONST_DOUBLE:
3053 case CONST:
3054 case SYMBOL_REF:
3055 case LABEL_REF:
3056 return 1;
823baf68 3057
998032ba 3058 case SET:
3059 case IOR:
3060 case AND:
3061 case XOR:
3062 case PLUS:
3063 case MINUS:
3064 if (check_return_regs (XEXP (x, 1)) == 0)
3065 return 0;
3066 case NOT:
3067 case NEG:
3068 case MEM:
3069 return check_return_regs (XEXP (x, 0));
3070
3071 default:
3072 return 0;
3073 }
823baf68 3074
998032ba 3075}
823baf68 3076
998032ba 3077int
3078short_branch (uid1, uid2)
3079 int uid1, uid2;
3080{
47fc0706 3081 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
f5348769 3082
3083 /* Leave a few words of "slop". */
3084 if (delta >= -1023 && delta <= 1022)
998032ba 3085 return 1;
f5348769 3086
998032ba 3087 return 0;
3088}
823baf68 3089
808a491c 3090/* Return nonzero if REG is not used after INSN.
998032ba 3091 We assume REG is a reload reg, and therefore does
3092 not live past labels or calls or jumps. */
3093int
3094reg_unused_after (reg, insn)
3095 rtx reg;
3096 rtx insn;
3097{
3098 enum rtx_code code, prev_code = UNKNOWN;
823baf68 3099
998032ba 3100 while ((insn = NEXT_INSN (insn)))
6dac3578 3101 {
998032ba 3102 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3103 return 1;
823baf68 3104
998032ba 3105 code = GET_CODE (insn);
3106 if (GET_CODE (insn) == CODE_LABEL)
3107 return 1;
76d1906a 3108
998032ba 3109 if (GET_RTX_CLASS (code) == 'i')
6dac3578 3110 {
998032ba 3111 rtx set = single_set (insn);
3112 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3113 if (set && in_src)
3114 return 0;
3115 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3116 return 1;
3117 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3118 return 0;
6dac3578 3119 }
998032ba 3120 prev_code = code;
6dac3578 3121 }
998032ba 3122 return 1;
3123}
3124\f
3125/* The table we use to reference PIC data. */
1f3233d1 3126static GTY(()) rtx global_offset_table;
76d1906a 3127
998032ba 3128/* The function we use to get at it. */
1f3233d1 3129static GTY(()) rtx get_pc_symbol;
998032ba 3130static char get_pc_symbol_name[256];
823baf68 3131
998032ba 3132/* Ensure that we are not using patterns that are not OK with PIC. */
93fed860 3133
998032ba 3134int
3135check_pic (i)
3136 int i;
3137{
3138 switch (flag_pic)
823baf68 3139 {
998032ba 3140 case 1:
ed420a25 3141 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3142 || (GET_CODE (recog_data.operand[i]) == CONST
3143 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3144 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
998032ba 3145 == global_offset_table)
ed420a25 3146 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
998032ba 3147 == CONST))))
3148 abort ();
3149 case 2:
3150 default:
3151 return 1;
823baf68 3152 }
823baf68 3153}
93fed860 3154
998032ba 3155/* Return true if X is an address which needs a temporary register when
3156 reloaded while generating PIC code. */
93fed860 3157
998032ba 3158int
3159pic_address_needs_scratch (x)
3160 rtx x;
93fed860 3161{
998032ba 3162 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3163 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3164 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3165 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3166 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3167 return 1;
93fed860 3168
998032ba 3169 return 0;
3170}
93fed860 3171
998032ba 3172/* Legitimize PIC addresses. If the address is already position-independent,
3173 we return ORIG. Newly generated position-independent addresses go into a
c8515df4 3174 reg. This is REG if nonzero, otherwise we allocate register(s) as
998032ba 3175 necessary. */
93fed860 3176
998032ba 3177rtx
3178legitimize_pic_address (orig, mode, reg)
3179 rtx orig;
3180 enum machine_mode mode ATTRIBUTE_UNUSED;
3181 rtx reg;
3182{
3183 if (GET_CODE (orig) == SYMBOL_REF)
8e1581a1 3184 {
998032ba 3185 rtx pic_ref, address;
3186 rtx insn;
8e1581a1 3187
998032ba 3188 if (reg == 0)
8e1581a1 3189 {
998032ba 3190 if (reload_in_progress || reload_completed)
3191 abort ();
3192 else
3193 reg = gen_reg_rtx (Pmode);
8e1581a1 3194 }
93fed860 3195
998032ba 3196 if (flag_pic == 2)
279e8405 3197 {
998032ba 3198 /* If not during reload, allocate another temp reg here for loading
3199 in the address, so that these instructions can be optimized
3200 properly. */
3201 rtx temp_reg = ((reload_in_progress || reload_completed)
3202 ? reg : gen_reg_rtx (Pmode));
3203
3204 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3205 won't get confused into thinking that these two instructions
3206 are loading in the true address of the symbol. If in the
3207 future a PIC rtx exists, that should be used instead. */
abce7786 3208 if (Pmode == SImode)
3209 {
3210 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3211 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3212 }
3213 else
3214 {
3215 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3216 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3217 }
998032ba 3218 address = temp_reg;
279e8405 3219 }
3220 else
998032ba 3221 address = orig;
3222
3223 pic_ref = gen_rtx_MEM (Pmode,
2a631e19 3224 gen_rtx_PLUS (Pmode,
3225 pic_offset_table_rtx, address));
998032ba 3226 current_function_uses_pic_offset_table = 1;
3227 RTX_UNCHANGING_P (pic_ref) = 1;
3228 insn = emit_move_insn (reg, pic_ref);
3229 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3230 by loop. */
3231 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3232 REG_NOTES (insn));
3233 return reg;
93fed860 3234 }
998032ba 3235 else if (GET_CODE (orig) == CONST)
93fed860 3236 {
998032ba 3237 rtx base, offset;
93fed860 3238
998032ba 3239 if (GET_CODE (XEXP (orig, 0)) == PLUS
3240 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3241 return orig;
8e1581a1 3242
998032ba 3243 if (reg == 0)
279e8405 3244 {
998032ba 3245 if (reload_in_progress || reload_completed)
3246 abort ();
3247 else
3248 reg = gen_reg_rtx (Pmode);
279e8405 3249 }
998032ba 3250
3251 if (GET_CODE (XEXP (orig, 0)) == PLUS)
279e8405 3252 {
998032ba 3253 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3254 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3255 base == reg ? 0 : reg);
279e8405 3256 }
3257 else
fc62c240 3258 abort ();
3259
998032ba 3260 if (GET_CODE (offset) == CONST_INT)
3261 {
3262 if (SMALL_INT (offset))
b244d4c7 3263 return plus_constant (base, INTVAL (offset));
998032ba 3264 else if (! reload_in_progress && ! reload_completed)
3265 offset = force_reg (Pmode, offset);
3266 else
3267 /* If we reach here, then something is seriously wrong. */
3268 abort ();
3269 }
3270 return gen_rtx_PLUS (Pmode, base, offset);
93fed860 3271 }
998032ba 3272 else if (GET_CODE (orig) == LABEL_REF)
3273 /* ??? Why do we do this? */
3274 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3275 the register is live instead, in case it is eliminated. */
3276 current_function_uses_pic_offset_table = 1;
93fed860 3277
998032ba 3278 return orig;
3279}
93fed860 3280
b35c8874 3281/* Emit special PIC prologues. */
93fed860 3282
998032ba 3283void
b35c8874 3284load_pic_register ()
998032ba 3285{
3286 /* Labels to get the PC in the prologue of this function. */
3287 int orig_flag_pic = flag_pic;
279e8405 3288
998032ba 3289 if (! flag_pic)
3290 abort ();
3291
cb0ccc1e 3292 /* If we haven't emitted the special get_pc helper function, do so now. */
998032ba 3293 if (get_pc_symbol_name[0] == 0)
279e8405 3294 {
164b9556 3295 int align;
8e1581a1 3296
164b9556 3297 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
998032ba 3298 text_section ();
164b9556 3299
3300 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3301 if (align > 0)
3302 ASM_OUTPUT_ALIGN (asm_out_file, align);
805e22b2 3303 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
0ca827a6 3304 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
998032ba 3305 }
8e1581a1 3306
998032ba 3307 /* Initialize every time through, since we can't easily
3308 know this to be permanent. */
3309 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3310 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3311 flag_pic = 0;
8e1581a1 3312
b35c8874 3313 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3314 get_pc_symbol));
8e1581a1 3315
998032ba 3316 flag_pic = orig_flag_pic;
8e1581a1 3317
998032ba 3318 /* Need to emit this whether or not we obey regdecls,
3319 since setjmp/longjmp can cause life info to screw up.
3320 ??? In the case where we don't obey regdecls, this is not sufficient
3321 since we may not fall out the bottom. */
3322 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
93fed860 3323}
823baf68 3324\f
998032ba 3325/* Return 1 if RTX is a MEM which is known to be aligned to at
87515218 3326 least a DESIRED byte boundary. */
4495c759 3327
998032ba 3328int
3329mem_min_alignment (mem, desired)
3330 rtx mem;
3331 int desired;
823baf68 3332{
998032ba 3333 rtx addr, base, offset;
3334
3335 /* If it's not a MEM we can't accept it. */
3336 if (GET_CODE (mem) != MEM)
3337 return 0;
3338
3339 addr = XEXP (mem, 0);
3340 base = offset = NULL_RTX;
3341 if (GET_CODE (addr) == PLUS)
823baf68 3342 {
998032ba 3343 if (GET_CODE (XEXP (addr, 0)) == REG)
6dac3578 3344 {
998032ba 3345 base = XEXP (addr, 0);
3346
3347 /* What we are saying here is that if the base
3348 REG is aligned properly, the compiler will make
3349 sure any REG based index upon it will be so
3350 as well. */
3351 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3352 offset = XEXP (addr, 1);
6dac3578 3353 else
998032ba 3354 offset = const0_rtx;
6dac3578 3355 }
823baf68 3356 }
998032ba 3357 else if (GET_CODE (addr) == REG)
823baf68 3358 {
998032ba 3359 base = addr;
3360 offset = const0_rtx;
823baf68 3361 }
8e1581a1 3362
998032ba 3363 if (base != NULL_RTX)
93fed860 3364 {
998032ba 3365 int regno = REGNO (base);
3366
04a917bf 3367 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
6dac3578 3368 {
998032ba 3369 /* Check if the compiler has recorded some information
3370 about the alignment of the base REG. If reload has
d28ce9d3 3371 completed, we already matched with proper alignments.
3372 If not running global_alloc, reload might give us
3373 unaligned pointer to local stack though. */
80909c64 3374 if (((cfun != 0
3375 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
d28ce9d3 3376 || (optimize && reload_completed))
80909c64 3377 && (INTVAL (offset) & (desired - 1)) == 0)
998032ba 3378 return 1;
6dac3578 3379 }
93fed860 3380 else
998032ba 3381 {
3382 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3383 return 1;
3384 }
93fed860 3385 }
998032ba 3386 else if (! TARGET_UNALIGNED_DOUBLES
3387 || CONSTANT_P (addr)
3388 || GET_CODE (addr) == LO_SUM)
93fed860 3389 {
998032ba 3390 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3391 is true, in which case we can only assume that an access is aligned if
3392 it is to a constant address, or the address involves a LO_SUM. */
3393 return 1;
93fed860 3394 }
998032ba 3395
3396 /* An obviously unaligned address. */
3397 return 0;
93fed860 3398}
998032ba 3399
823baf68 3400\f
6dac3578 3401/* Vectors to keep interesting information about registers where it can easily
3402 be got. We use to use the actual mode value as the bit number, but there
3403 are more than 32 modes now. Instead we use two tables: one indexed by
3404 hard register number, and one indexed by mode. */
3405
3406/* The purpose of sparc_mode_class is to shrink the range of modes so that
3407 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3408 mapped into one sparc_mode_class mode. */
3409
3410enum sparc_mode_class {
6dac3578 3411 S_MODE, D_MODE, T_MODE, O_MODE,
946e12d1 3412 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3413 CC_MODE, CCFP_MODE
6dac3578 3414};
823baf68 3415
6dac3578 3416/* Modes for single-word and smaller quantities. */
3417#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3418
3419/* Modes for double-word and smaller quantities. */
3420#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3421
3422/* Modes for quad-word and smaller quantities. */
3423#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
823baf68 3424
efd0ee2a 3425/* Modes for 8-word and smaller quantities. */
3426#define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3427
9fd10e39 3428/* Modes for single-float quantities. We must allow any single word or
3429 smaller quantity. This is because the fix/float conversion instructions
3430 take integer inputs/outputs from the float registers. */
3431#define SF_MODES (S_MODES)
823baf68 3432
6dac3578 3433/* Modes for double-float and smaller quantities. */
3434#define DF_MODES (S_MODES | D_MODES)
3435
6dac3578 3436/* Modes for double-float only quantities. */
213fb6cc 3437#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
823baf68 3438
6dac3578 3439/* Modes for quad-float only quantities. */
3440#define TF_ONLY_MODES (1 << (int) TF_MODE)
3441
3442/* Modes for quad-float and smaller quantities. */
3443#define TF_MODES (DF_MODES | TF_ONLY_MODES)
3444
efd0ee2a 3445/* Modes for quad-float and double-float quantities. */
3446#define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3447
3448/* Modes for quad-float pair only quantities. */
3449#define OF_ONLY_MODES (1 << (int) OF_MODE)
3450
3451/* Modes for quad-float pairs and smaller quantities. */
3452#define OF_MODES (TF_MODES | OF_ONLY_MODES)
3453
3454#define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
823baf68 3455
946e12d1 3456/* Modes for condition codes. */
3457#define CC_MODES (1 << (int) CC_MODE)
3458#define CCFP_MODES (1 << (int) CCFP_MODE)
3459
823baf68 3460/* Value is 1 if register/mode pair is acceptable on sparc.
3461 The funny mixture of D and T modes is because integer operations
3462 do not specially operate on tetra quantities, so non-quad-aligned
3463 registers can hold quadword quantities (except %o4 and %i4 because
946e12d1 3464 they cross fixed registers). */
823baf68 3465
6dac3578 3466/* This points to either the 32 bit or the 64 bit version. */
e7c691ac 3467const int *hard_regno_mode_classes;
6dac3578 3468
e7c691ac 3469static const int hard_32bit_mode_classes[] = {
946e12d1 3470 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
823baf68 3471 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3472 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3473 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3474
efd0ee2a 3475 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3476 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3477 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3478 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
07569960 3479
3480 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3481 and none can hold SFmode/SImode values. */
efd0ee2a 3482 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3483 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3484 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3485 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
07569960 3486
3487 /* %fcc[0123] */
946e12d1 3488 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3489
3490 /* %icc */
3491 CC_MODES
6dac3578 3492};
3493
e7c691ac 3494static const int hard_64bit_mode_classes[] = {
946e12d1 3495 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
efd0ee2a 3496 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
6dac3578 3497 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
efd0ee2a 3498 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
6dac3578 3499
efd0ee2a 3500 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3501 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3502 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3503 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
6dac3578 3504
07569960 3505 /* FP regs f32 to f63. Only the even numbered registers actually exist,
6dac3578 3506 and none can hold SFmode/SImode values. */
efd0ee2a 3507 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3508 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3509 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3510 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
6dac3578 3511
3512 /* %fcc[0123] */
946e12d1 3513 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3514
3515 /* %icc */
3516 CC_MODES
6dac3578 3517};
3518
3519int sparc_mode_class [NUM_MACHINE_MODES];
3520
946e12d1 3521enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3522
6dac3578 3523static void
3524sparc_init_modes ()
3525{
3526 int i;
3527
6dac3578 3528 for (i = 0; i < NUM_MACHINE_MODES; i++)
3529 {
3530 switch (GET_MODE_CLASS (i))
3531 {
3532 case MODE_INT:
3533 case MODE_PARTIAL_INT:
3534 case MODE_COMPLEX_INT:
3535 if (GET_MODE_SIZE (i) <= 4)
3536 sparc_mode_class[i] = 1 << (int) S_MODE;
3537 else if (GET_MODE_SIZE (i) == 8)
3538 sparc_mode_class[i] = 1 << (int) D_MODE;
3539 else if (GET_MODE_SIZE (i) == 16)
3540 sparc_mode_class[i] = 1 << (int) T_MODE;
3541 else if (GET_MODE_SIZE (i) == 32)
3542 sparc_mode_class[i] = 1 << (int) O_MODE;
3543 else
3544 sparc_mode_class[i] = 0;
3545 break;
3546 case MODE_FLOAT:
3547 case MODE_COMPLEX_FLOAT:
3548 if (GET_MODE_SIZE (i) <= 4)
3549 sparc_mode_class[i] = 1 << (int) SF_MODE;
3550 else if (GET_MODE_SIZE (i) == 8)
3551 sparc_mode_class[i] = 1 << (int) DF_MODE;
3552 else if (GET_MODE_SIZE (i) == 16)
3553 sparc_mode_class[i] = 1 << (int) TF_MODE;
3554 else if (GET_MODE_SIZE (i) == 32)
3555 sparc_mode_class[i] = 1 << (int) OF_MODE;
3556 else
3557 sparc_mode_class[i] = 0;
3558 break;
3559 case MODE_CC:
3560 default:
3561 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3562 we must explicitly check for them here. */
3563 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3564 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3565 else if (i == (int) CCmode || i == (int) CC_NOOVmode
07569960 3566 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
946e12d1 3567 sparc_mode_class[i] = 1 << (int) CC_MODE;
6dac3578 3568 else
3569 sparc_mode_class[i] = 0;
3570 break;
3571 }
3572 }
3573
07569960 3574 if (TARGET_ARCH64)
6dac3578 3575 hard_regno_mode_classes = hard_64bit_mode_classes;
3576 else
3577 hard_regno_mode_classes = hard_32bit_mode_classes;
946e12d1 3578
3579 /* Initialize the array used by REGNO_REG_CLASS. */
3580 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3581 {
367242d3 3582 if (i < 16 && TARGET_V8PLUS)
3583 sparc_regno_reg_class[i] = I64_REGS;
04a917bf 3584 else if (i < 32 || i == FRAME_POINTER_REGNUM)
946e12d1 3585 sparc_regno_reg_class[i] = GENERAL_REGS;
3586 else if (i < 64)
3587 sparc_regno_reg_class[i] = FP_REGS;
3588 else if (i < 96)
3589 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3590 else if (i < 100)
3591 sparc_regno_reg_class[i] = FPCC_REGS;
3592 else
3593 sparc_regno_reg_class[i] = NO_REGS;
3594 }
6dac3578 3595}
823baf68 3596\f
6dac3578 3597/* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3598 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3599 v9 int regs as it simplifies the code. */
3600
823baf68 3601static int
4ad3f9b3 3602save_regs (file, low, high, base, offset, n_regs, real_offset)
823baf68 3603 FILE *file;
3604 int low, high;
c4f04114 3605 const char *base;
823baf68 3606 int offset;
6dac3578 3607 int n_regs;
4ad3f9b3 3608 int real_offset;
823baf68 3609{
3610 int i;
3611
07569960 3612 if (TARGET_ARCH64 && high <= 32)
823baf68 3613 {
6dac3578 3614 for (i = low; i < high; i++)
3615 {
3616 if (regs_ever_live[i] && ! call_used_regs[i])
4ad3f9b3 3617 {
998032ba 3618 fprintf (file, "\tstx\t%s, [%s+%d]\n",
4ad3f9b3 3619 reg_names[i], base, offset + 4 * n_regs);
d757b8c9 3620 if (dwarf2out_do_frame ())
4ad3f9b3 3621 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4ad3f9b3 3622 n_regs += 2;
3623 }
6dac3578 3624 }
823baf68 3625 }
6dac3578 3626 else
3627 {
3628 for (i = low; i < high; i += 2)
3629 {
3630 if (regs_ever_live[i] && ! call_used_regs[i])
4ad3f9b3 3631 {
07e64d6e 3632 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3633 {
998032ba 3634 fprintf (file, "\tstd\t%s, [%s+%d]\n",
07e64d6e 3635 reg_names[i], base, offset + 4 * n_regs);
3636 if (dwarf2out_do_frame ())
3637 {
3638 char *l = dwarf2out_cfi_label ();
3639 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
3640 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
3641 }
3642 n_regs += 2;
3643 }
3644 else
3645 {
998032ba 3646 fprintf (file, "\tst\t%s, [%s+%d]\n",
07e64d6e 3647 reg_names[i], base, offset + 4 * n_regs);
3648 if (dwarf2out_do_frame ())
3649 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3650 n_regs += 2;
3651 }
3652 }
3653 else
3654 {
3655 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3656 {
998032ba 3657 fprintf (file, "\tst\t%s, [%s+%d]\n",
07e64d6e 3658 reg_names[i+1], base, offset + 4 * n_regs + 4);
3659 if (dwarf2out_do_frame ())
3660 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
3661 n_regs += 2;
3662 }
4ad3f9b3 3663 }
6dac3578 3664 }
3665 }
3666 return n_regs;
823baf68 3667}
3668
6dac3578 3669/* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3670
3671 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3672 v9 int regs as it simplifies the code. */
3673
823baf68 3674static int
6dac3578 3675restore_regs (file, low, high, base, offset, n_regs)
823baf68 3676 FILE *file;
3677 int low, high;
c4f04114 3678 const char *base;
823baf68 3679 int offset;
6dac3578 3680 int n_regs;
823baf68 3681{
3682 int i;
3683
07569960 3684 if (TARGET_ARCH64 && high <= 32)
6dac3578 3685 {
3686 for (i = low; i < high; i++)
3687 {
3688 if (regs_ever_live[i] && ! call_used_regs[i])
998032ba 3689 fprintf (file, "\tldx\t[%s+%d], %s\n",
6dac3578 3690 base, offset + 4 * n_regs, reg_names[i]),
3691 n_regs += 2;
3692 }
3693 }
3694 else
823baf68 3695 {
6dac3578 3696 for (i = low; i < high; i += 2)
3697 {
3698 if (regs_ever_live[i] && ! call_used_regs[i])
3699 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
998032ba 3700 fprintf (file, "\tldd\t[%s+%d], %s\n",
6dac3578 3701 base, offset + 4 * n_regs, reg_names[i]),
3702 n_regs += 2;
3703 else
0ca827a6 3704 fprintf (file, "\tld\t[%s+%d], %s\n",
6dac3578 3705 base, offset + 4 * n_regs, reg_names[i]),
3706 n_regs += 2;
3707 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
0ca827a6 3708 fprintf (file, "\tld\t[%s+%d], %s\n",
6dac3578 3709 base, offset + 4 * n_regs + 4, reg_names[i+1]),
3710 n_regs += 2;
3711 }
823baf68 3712 }
6dac3578 3713 return n_regs;
823baf68 3714}
3715
6dac3578 3716/* Compute the frame size required by the function. This function is called
3717 during the reload pass and also by output_function_prologue(). */
823baf68 3718
823baf68 3719int
3720compute_frame_size (size, leaf_function)
3721 int size;
3722 int leaf_function;
3723{
6dac3578 3724 int n_regs = 0, i;
823baf68 3725 int outgoing_args_size = (current_function_outgoing_args_size
279e8405 3726 + REG_PARM_STACK_SPACE (current_function_decl));
823baf68 3727
8b7a298d 3728 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3729 even to v9 int regs to be consistent with save_regs/restore_regs. */
6dac3578 3730
8b7a298d 3731 if (TARGET_ARCH64)
3732 {
3733 for (i = 0; i < 8; i++)
3734 if (regs_ever_live[i] && ! call_used_regs[i])
3735 n_regs += 2;
3736 }
3737 else
3738 {
3739 for (i = 0; i < 8; i += 2)
823baf68 3740 if ((regs_ever_live[i] && ! call_used_regs[i])
3741 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
6dac3578 3742 n_regs += 2;
823baf68 3743 }
3744
8b7a298d 3745 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3746 if ((regs_ever_live[i] && ! call_used_regs[i])
3747 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3748 n_regs += 2;
3749
823baf68 3750 /* Set up values for use in `function_epilogue'. */
6dac3578 3751 num_gfregs = n_regs;
823baf68 3752
6dac3578 3753 if (leaf_function && n_regs == 0
3754 && size == 0 && current_function_outgoing_args_size == 0)
3755 {
3756 actual_fsize = apparent_fsize = 0;
3757 }
3758 else
3759 {
9b2e8d38 3760 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3761 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
6dac3578 3762 apparent_fsize += n_regs * 4;
3763 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3764 }
823baf68 3765
3766 /* Make sure nothing can clobber our register windows.
3767 If a SAVE must be done, or there is a stack-local variable,
6dac3578 3768 the register window area must be allocated.
279e8405 3769 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
823baf68 3770 if (leaf_function == 0 || size > 0)
279e8405 3771 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
823baf68 3772
6dac3578 3773 return SPARC_STACK_ALIGN (actual_fsize);
3774}
3775
3776/* Build a (32 bit) big number in a register. */
5c648c1a 3777/* ??? We may be able to use the set macro here too. */
6dac3578 3778
3779static void
3780build_big_number (file, num, reg)
3781 FILE *file;
3782 int num;
c4f04114 3783 const char *reg;
6dac3578 3784{
07569960 3785 if (num >= 0 || ! TARGET_ARCH64)
6dac3578 3786 {
998032ba 3787 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
6dac3578 3788 if ((num & 0x3ff) != 0)
998032ba 3789 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
6dac3578 3790 }
07569960 3791 else /* num < 0 && TARGET_ARCH64 */
6dac3578 3792 {
3793 /* Sethi does not sign extend, so we must use a little trickery
3794 to use it for negative numbers. Invert the constant before
3795 loading it in, then use xor immediate to invert the loaded bits
3796 (along with the upper 32 bits) to the desired constant. This
3797 works because the sethi and immediate fields overlap. */
3798 int asize = num;
3799 int inv = ~asize;
3800 int low = -0x400 + (asize & 0x3FF);
3801
998032ba 3802 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
6dac3578 3803 inv, reg, reg, low, reg);
3804 }
823baf68 3805}
3806
d300bd48 3807/* Output any necessary .register pseudo-ops. */
3808void
3809sparc_output_scratch_registers (file)
779433ea 3810 FILE *file ATTRIBUTE_UNUSED;
d300bd48 3811{
3812#ifdef HAVE_AS_REGISTER_PSEUDO_OP
3813 int i;
3814
3815 if (TARGET_ARCH32)
3816 return;
3817
3818 /* Check if %g[2367] were used without
3819 .register being printed for them already. */
3820 for (i = 2; i < 8; i++)
3821 {
3822 if (regs_ever_live [i]
3823 && ! sparc_hard_reg_printed [i])
3824 {
3825 sparc_hard_reg_printed [i] = 1;
3826 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
3827 }
3828 if (i == 3) i = 5;
3829 }
3830#endif
3831}
3832
17d9b0c3 3833/* This function generates the assembly code for function entry.
3834 FILE is a stdio stream to output the code to.
3835 SIZE is an int: how many units of temporary storage to allocate.
3836 Refer to the array `regs_ever_live' to determine which registers
3837 to save; `regs_ever_live[I]' is nonzero if register number I
3838 is ever used in the function. This macro is responsible for
3839 knowing which registers should not be saved even if used. */
3840
3841/* On SPARC, move-double insns between fpu and cpu need an 8-byte block
3842 of memory. If any fpu reg is used in the function, we allocate
3843 such a block here, at the bottom of the frame, just in case it's needed.
3844
3845 If this function is a leaf procedure, then we may choose not
3846 to do a "save" insn. The decision about whether or not
3847 to do this is made in regclass.c. */
3848
3849static void
3850sparc_output_function_prologue (file, size)
3851 FILE *file;
3852 HOST_WIDE_INT size;
3853{
3854 if (TARGET_FLAT)
3855 sparc_flat_function_prologue (file, size);
3856 else
3857 sparc_nonflat_function_prologue (file, size,
3858 current_function_uses_only_leaf_regs);
3859}
3860
d2d45541 3861/* Output code for the function prologue. */
3862
17d9b0c3 3863static void
3864sparc_nonflat_function_prologue (file, size, leaf_function)
823baf68 3865 FILE *file;
17d9b0c3 3866 HOST_WIDE_INT size;
d2d45541 3867 int leaf_function;
823baf68 3868{
d300bd48 3869 sparc_output_scratch_registers (file);
3870
d2d45541 3871 /* Need to use actual_fsize, since we are also allocating
3872 space for our callee (and our own register save area). */
823baf68 3873 actual_fsize = compute_frame_size (size, leaf_function);
3874
6dac3578 3875 if (leaf_function)
3876 {
3877 frame_base_name = "%sp";
3878 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3879 }
3880 else
3881 {
3882 frame_base_name = "%fp";
3883 frame_base_offset = SPARC_STACK_BIAS;
3884 }
3885
7775000f 3886 /* This is only for the human reader. */
77d3d2a4 3887 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7775000f 3888
d2d45541 3889 if (actual_fsize == 0)
3890 /* do nothing. */ ;
f8be3dfc 3891 else if (! leaf_function)
823baf68 3892 {
224cac7b 3893 if (actual_fsize <= 4096)
998032ba 3894 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
224cac7b 3895 else if (actual_fsize <= 8192)
d2d45541 3896 {
998032ba 3897 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3898 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
d2d45541 3899 }
3900 else
3901 {
224cac7b 3902 build_big_number (file, -actual_fsize, "%g1");
998032ba 3903 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
d2d45541 3904 }
823baf68 3905 }
a82f26af 3906 else /* leaf function */
3907 {
224cac7b 3908 if (actual_fsize <= 4096)
998032ba 3909 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
224cac7b 3910 else if (actual_fsize <= 8192)
3911 {
998032ba 3912 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3913 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
224cac7b 3914 }
d2d45541 3915 else
224cac7b 3916 {
3917 build_big_number (file, -actual_fsize, "%g1");
998032ba 3918 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
224cac7b 3919 }
823baf68 3920 }
3921
d757b8c9 3922 if (dwarf2out_do_frame () && actual_fsize)
4ad3f9b3 3923 {
f164689f 3924 char *label = dwarf2out_cfi_label ();
4ad3f9b3 3925
3926 /* The canonical frame address refers to the top of the frame. */
3927 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
04a917bf 3928 : HARD_FRAME_POINTER_REGNUM),
4ad3f9b3 3929 frame_base_offset);
3930
3931 if (! leaf_function)
3932 {
3933 /* Note the register window save. This tells the unwinder that
3934 it needs to restore the window registers from the previous
3935 frame's window save area at 0(cfa). */
3936 dwarf2out_window_save (label);
3937
3938 /* The return address (-8) is now in %i7. */
3939 dwarf2out_return_reg (label, 31);
3940 }
3941 }
4ad3f9b3 3942
823baf68 3943 /* If doing anything with PIC, do it now. */
3944 if (! flag_pic)
77d3d2a4 3945 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
823baf68 3946
6dac3578 3947 /* Call saved registers are saved just above the outgoing argument area. */
3948 if (num_gfregs)
823baf68 3949 {
4ad3f9b3 3950 int offset, real_offset, n_regs;
c4f04114 3951 const char *base;
823baf68 3952
32612dd3 3953 real_offset = -apparent_fsize;
3954 offset = -apparent_fsize + frame_base_offset;
6dac3578 3955 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3956 {
3957 /* ??? This might be optimized a little as %g1 might already have a
3958 value close enough that a single add insn will do. */
3959 /* ??? Although, all of this is probably only a temporary fix
3960 because if %g1 can hold a function result, then
3961 output_function_epilogue will lose (the result will get
3962 clobbered). */
3963 build_big_number (file, offset, "%g1");
998032ba 3964 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
6dac3578 3965 base = "%g1";
3966 offset = 0;
3967 }
823baf68 3968 else
6dac3578 3969 {
3970 base = frame_base_name;
3971 }
823baf68 3972
8b7a298d 3973 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3974 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3975 real_offset);
823baf68 3976 }
3977}
3978
7a8d641b 3979/* Output code to restore any call saved registers. */
3980
3981static void
3982output_restore_regs (file, leaf_function)
3983 FILE *file;
3dcaebeb 3984 int leaf_function ATTRIBUTE_UNUSED;
7a8d641b 3985{
3986 int offset, n_regs;
3987 const char *base;
3988
3989 offset = -apparent_fsize + frame_base_offset;
3990 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3991 {
3992 build_big_number (file, offset, "%g1");
3993 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3994 base = "%g1";
3995 offset = 0;
3996 }
3997 else
3998 {
3999 base = frame_base_name;
4000 }
4001
8b7a298d 4002 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4003 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
7a8d641b 4004}
4005
17d9b0c3 4006/* This function generates the assembly code for function exit,
4007 on machines that need it.
4008
4009 The function epilogue should not depend on the current stack pointer!
4010 It should use the frame pointer only. This is mandatory because
4011 of alloca; we also take advantage of it to omit stack adjustments
4012 before returning. */
4013
4014static void
4015sparc_output_function_epilogue (file, size)
4016 FILE *file;
4017 HOST_WIDE_INT size;
4018{
4019 if (TARGET_FLAT)
4020 sparc_flat_function_epilogue (file, size);
4021 else
4022 sparc_nonflat_function_epilogue (file, size,
4023 current_function_uses_only_leaf_regs);
4024}
4025
d2d45541 4026/* Output code for the function epilogue. */
4027
17d9b0c3 4028static void
4029sparc_nonflat_function_epilogue (file, size, leaf_function)
823baf68 4030 FILE *file;
17d9b0c3 4031 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
c2b076cd 4032 int leaf_function;
823baf68 4033{
c4f04114 4034 const char *ret;
823baf68 4035
644a1400 4036 if (current_function_epilogue_delay_list == 0)
5a1acad9 4037 {
998032ba 4038 /* If code does not drop into the epilogue, we need
87515218 4039 do nothing except output pending case vectors.
4040
4041 We have to still output a dummy nop for the sake of
4042 sane backtraces. Otherwise, if the last two instructions
4043 of a function were call foo; dslot; this can make the return
4044 PC of foo (ie. address of call instruction plus 8) point to
4045 the first instruction in the next function. */
4046 rtx insn;
4047
4048 fputs("\tnop\n", file);
4049
4050 insn = get_last_insn ();
4051 if (GET_CODE (insn) == NOTE)
4052 insn = prev_nonnote_insn (insn);
4053 if (insn && GET_CODE (insn) == BARRIER)
4054 goto output_vectors;
f618d313 4055 }
4056
6dac3578 4057 if (num_gfregs)
7a8d641b 4058 output_restore_regs (file, leaf_function);
823baf68 4059
4060 /* Work out how to skip the caller's unimp instruction if required. */
4061 if (leaf_function)
998032ba 4062 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
823baf68 4063 else
998032ba 4064 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
823baf68 4065
8b7a298d 4066 if (! leaf_function)
823baf68 4067 {
8b7a298d 4068 if (current_function_calls_eh_return)
4069 {
4070 if (current_function_epilogue_delay_list)
4071 abort ();
4072 if (SKIP_CALLERS_UNIMP_P)
4073 abort ();
823baf68 4074
8b7a298d 4075 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4076 }
4077 /* If we wound up with things in our delay slot, flush them here. */
4078 else if (current_function_epilogue_delay_list)
c2b076cd 4079 {
8b7a298d 4080 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
e4acc523 4081
8b7a298d 4082 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4083 {
4084 epilogue_renumber (&delay, 0);
4085 fputs (SKIP_CALLERS_UNIMP_P
4086 ? "\treturn\t%i7+12\n"
4087 : "\treturn\t%i7+8\n", file);
4088 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4089 file, 1, 0, 0);
e4acc523 4090 }
8b7a298d 4091 else
823baf68 4092 {
8b7a298d 4093 rtx insn, src;
5a1acad9 4094
8b7a298d 4095 if (GET_CODE (delay) != SET)
4096 abort();
5a1acad9 4097
8b7a298d 4098 src = SET_SRC (delay);
4099 if (GET_CODE (src) == ASHIFT)
4100 {
4101 if (XEXP (src, 1) != const1_rtx)
5a1acad9 4102 abort();
8b7a298d 4103 SET_SRC (delay)
4104 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4105 XEXP (src, 0));
4106 }
5a1acad9 4107
8b7a298d 4108 insn = gen_rtx_PARALLEL (VOIDmode,
4109 gen_rtvec (2, delay,
4110 gen_rtx_RETURN (VOIDmode)));
4111 insn = emit_jump_insn (insn);
5a1acad9 4112
8b7a298d 4113 sparc_emitting_epilogue = true;
4114 final_scan_insn (insn, file, 1, 0, 1);
4115 sparc_emitting_epilogue = false;
823baf68 4116 }
c2b076cd 4117 }
8b7a298d 4118 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4119 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4120 else
4121 fprintf (file, "\t%s\n\trestore\n", ret);
4122 }
4123 /* All of the following cases are for leaf functions. */
4124 else if (current_function_calls_eh_return)
4125 abort ();
4126 else if (current_function_epilogue_delay_list)
4127 {
4128 /* eligible_for_epilogue_delay_slot ensures that if this is a
4129 leaf function, then we will only have insn in the delay slot
4130 if the frame size is zero, thus no adjust for the stack is
4131 needed here. */
4132 if (actual_fsize != 0)
e4acc523 4133 abort ();
8b7a298d 4134 fprintf (file, "\t%s\n", ret);
4135 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4136 file, 1, 0, 1);
823baf68 4137 }
8b7a298d 4138 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4139 avoid generating confusing assembly language output. */
4140 else if (actual_fsize == 0)
4141 fprintf (file, "\t%s\n\tnop\n", ret);
4142 else if (actual_fsize <= 4096)
4143 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
4144 else if (actual_fsize <= 8192)
4145 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4146 ret, actual_fsize - 4096);
4147 else if ((actual_fsize & 0x3ff) == 0)
4148 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4149 actual_fsize, ret);
4150 else
4151 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4152 actual_fsize, actual_fsize, ret);
998032ba 4153
4154 output_vectors:
4155 sparc_output_deferred_case_vectors ();
823baf68 4156}
7a8d641b 4157
4158/* Output a sibling call. */
4159
4160const char *
4161output_sibcall (insn, call_operand)
4162 rtx insn, call_operand;
4163{
4164 int leaf_regs = current_function_uses_only_leaf_regs;
4165 rtx operands[3];
4166 int delay_slot = dbr_sequence_length () > 0;
4167
4168 if (num_gfregs)
4169 {
4170 /* Call to restore global regs might clobber
4171 the delay slot. Instead of checking for this
4172 output the delay slot now. */
4173 if (delay_slot)
4174 {
4175 rtx delay = NEXT_INSN (insn);
4176
4177 if (! delay)
4178 abort ();
4179
4180 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4181 PATTERN (delay) = gen_blockage ();
4182 INSN_CODE (delay) = -1;
4183 delay_slot = 0;
4184 }
4185 output_restore_regs (asm_out_file, leaf_regs);
4186 }
4187
4188 operands[0] = call_operand;
4189
4190 if (leaf_regs)
4191 {
4c335027 4192#ifdef HAVE_AS_RELAX_OPTION
4193 /* If as and ld are relaxing tail call insns into branch always,
4194 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4195 be optimized. With sethi/jmpl as nor ld has no easy way how to
4196 find out if somebody does not branch between the sethi and jmpl. */
4197 int spare_slot = 0;
4198#else
f3619338 4199 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4c335027 4200#endif
7a8d641b 4201 int size = 0;
4202
4203 if ((actual_fsize || ! spare_slot) && delay_slot)
4204 {
4205 rtx delay = NEXT_INSN (insn);
4206
4207 if (! delay)
4208 abort ();
4209
4210 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4211 PATTERN (delay) = gen_blockage ();
4212 INSN_CODE (delay) = -1;
4213 delay_slot = 0;
4214 }
4215 if (actual_fsize)
4216 {
4217 if (actual_fsize <= 4096)
4218 size = actual_fsize;
4219 else if (actual_fsize <= 8192)
4220 {
4221 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4222 size = actual_fsize - 4096;
4223 }
4224 else if ((actual_fsize & 0x3ff) == 0)
4225 fprintf (asm_out_file,
4226 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4227 actual_fsize);
4228 else
4229 {
4230 fprintf (asm_out_file,
4231 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4232 actual_fsize, actual_fsize);
4233 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4234 }
4235 }
4236 if (spare_slot)
4237 {
4238 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4239 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4240 if (size)
4241 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size);
4242 else if (! delay_slot)
4243 fputs ("\t nop\n", asm_out_file);
4244 }
4245 else
4246 {
4247 if (size)
4248 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size);
4c335027 4249 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4250 it into branch if possible. */
4251 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
7a8d641b 4252 output_asm_insn ("call\t%a0, 0", operands);
4c335027 4253 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
7a8d641b 4254 }
4255 return "";
4256 }
4257
4258 output_asm_insn ("call\t%a0, 0", operands);
4259 if (delay_slot)
4260 {
4261 rtx delay = NEXT_INSN (insn), pat;
4262
4263 if (! delay)
4264 abort ();
4265
4266 pat = PATTERN (delay);
4267 if (GET_CODE (pat) != SET)
4268 abort ();
4269
4270 operands[0] = SET_DEST (pat);
4271 pat = SET_SRC (pat);
4272 switch (GET_CODE (pat))
4273 {
4274 case PLUS:
4275 operands[1] = XEXP (pat, 0);
4276 operands[2] = XEXP (pat, 1);
4277 output_asm_insn (" restore %r1, %2, %Y0", operands);
4278 break;
4279 case LO_SUM:
4280 operands[1] = XEXP (pat, 0);
4281 operands[2] = XEXP (pat, 1);
4282 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4283 break;
4284 case ASHIFT:
4285 operands[1] = XEXP (pat, 0);
4286 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4287 break;
4288 default:
4289 operands[1] = pat;
4290 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4291 break;
4292 }
4293 PATTERN (delay) = gen_blockage ();
4294 INSN_CODE (delay) = -1;
4295 }
4296 else
4297 fputs ("\t restore\n", asm_out_file);
4298 return "";
4299}
279e8405 4300\f
4301/* Functions for handling argument passing.
4302
4303 For v8 the first six args are normally in registers and the rest are
4304 pushed. Any arg that starts within the first 6 words is at least
4305 partially passed in a register unless its data type forbids.
4306
4307 For v9, the argument registers are laid out as an array of 16 elements
4308 and arguments are added sequentially. The first 6 int args and up to the
4309 first 16 fp args (depending on size) are passed in regs.
4310
4311 Slot Stack Integral Float Float in structure Double Long Double
4312 ---- ----- -------- ----- ------------------ ------ -----------
4313 15 [SP+248] %f31 %f30,%f31 %d30
4314 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4315 13 [SP+232] %f27 %f26,%f27 %d26
4316 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4317 11 [SP+216] %f23 %f22,%f23 %d22
4318 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4319 9 [SP+200] %f19 %f18,%f19 %d18
4320 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4321 7 [SP+184] %f15 %f14,%f15 %d14
4322 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4323 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4324 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4325 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4326 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4327 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4328 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4329
4330 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4331
4332 Integral arguments are always passed as 64 bit quantities appropriately
4333 extended.
4334
4335 Passing of floating point values is handled as follows.
4336 If a prototype is in scope:
4337 If the value is in a named argument (i.e. not a stdarg function or a
4338 value not part of the `...') then the value is passed in the appropriate
4339 fp reg.
4340 If the value is part of the `...' and is passed in one of the first 6
4341 slots then the value is passed in the appropriate int reg.
4342 If the value is part of the `...' and is not passed in one of the first 6
4343 slots then the value is passed in memory.
4344 If a prototype is not in scope:
4345 If the value is one of the first 6 arguments the value is passed in the
4346 appropriate integer reg and the appropriate fp reg.
4347 If the value is not one of the first 6 arguments the value is passed in
4348 the appropriate fp reg and in memory.
4349 */
4350
4351/* Maximum number of int regs for args. */
4352#define SPARC_INT_ARG_MAX 6
4353/* Maximum number of fp regs for args. */
4354#define SPARC_FP_ARG_MAX 16
4355
4356#define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4357
4358/* Handle the INIT_CUMULATIVE_ARGS macro.
4359 Initialize a variable CUM of type CUMULATIVE_ARGS
4360 for a call to a function whose data type is FNTYPE.
4361 For a library call, FNTYPE is 0. */
d9a5f7c9 4362
279e8405 4363void
4364init_cumulative_args (cum, fntype, libname, indirect)
4365 CUMULATIVE_ARGS *cum;
b8430a2d 4366 tree fntype;
79fa31ab 4367 rtx libname ATTRIBUTE_UNUSED;
b8430a2d 4368 int indirect ATTRIBUTE_UNUSED;
279e8405 4369{
4370 cum->words = 0;
4371 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4372 cum->libcall_p = fntype == 0;
4373}
6dac3578 4374
279e8405 4375/* Compute the slot number to pass an argument in.
4376 Returns the slot number or -1 if passing on the stack.
4377
4378 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4379 the preceding args and about the function being called.
4380 MODE is the argument's machine mode.
4381 TYPE is the data type of the argument (as a tree).
4382 This is null for libcalls where that information may
4383 not be available.
4384 NAMED is nonzero if this argument is a named parameter
4385 (otherwise it is an extra parameter matching an ellipsis).
4386 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4387 *PREGNO records the register number to use if scalar type.
4388 *PPADDING records the amount of padding needed in words. */
4389
4390static int
4391function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
4392 const CUMULATIVE_ARGS *cum;
4393 enum machine_mode mode;
4394 tree type;
4395 int named;
4396 int incoming_p;
4397 int *pregno;
4398 int *ppadding;
4399{
4400 int regbase = (incoming_p
4401 ? SPARC_INCOMING_INT_ARG_FIRST
4402 : SPARC_OUTGOING_INT_ARG_FIRST);
4403 int slotno = cum->words;
4404 int regno;
4405
4406 *ppadding = 0;
4407
4408 if (type != 0 && TREE_ADDRESSABLE (type))
4409 return -1;
4410 if (TARGET_ARCH32
4411 && type != 0 && mode == BLKmode
4412 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4413 return -1;
4414
4415 switch (mode)
4416 {
4417 case VOIDmode :
4418 /* MODE is VOIDmode when generating the actual call.
4419 See emit_call_1. */
4420 return -1;
4421
4422 case QImode : case CQImode :
4423 case HImode : case CHImode :
4424 case SImode : case CSImode :
4425 case DImode : case CDImode :
c5b3ce24 4426 case TImode : case CTImode :
279e8405 4427 if (slotno >= SPARC_INT_ARG_MAX)
4428 return -1;
4429 regno = regbase + slotno;
4430 break;
4431
4432 case SFmode : case SCmode :
4433 case DFmode : case DCmode :
4434 case TFmode : case TCmode :
4435 if (TARGET_ARCH32)
4436 {
4437 if (slotno >= SPARC_INT_ARG_MAX)
4438 return -1;
4439 regno = regbase + slotno;
4440 }
4441 else
4442 {
4443 if ((mode == TFmode || mode == TCmode)
4444 && (slotno & 1) != 0)
4445 slotno++, *ppadding = 1;
4446 if (TARGET_FPU && named)
4447 {
4448 if (slotno >= SPARC_FP_ARG_MAX)
8e1581a1 4449 return -1;
279e8405 4450 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4451 if (mode == SFmode)
4452 regno++;
4453 }
4454 else
4455 {
4456 if (slotno >= SPARC_INT_ARG_MAX)
4457 return -1;
4458 regno = regbase + slotno;
4459 }
4460 }
4461 break;
4462
4463 case BLKmode :
4464 /* For sparc64, objects requiring 16 byte alignment get it. */
4465 if (TARGET_ARCH64)
4466 {
4467 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
4468 slotno++, *ppadding = 1;
4469 }
4470
4471 if (TARGET_ARCH32
07e64d6e 4472 || (type && TREE_CODE (type) == UNION_TYPE))
279e8405 4473 {
4474 if (slotno >= SPARC_INT_ARG_MAX)
4475 return -1;
4476 regno = regbase + slotno;
4477 }
4478 else
4479 {
4480 tree field;
4481 int intregs_p = 0, fpregs_p = 0;
4482 /* The ABI obviously doesn't specify how packed
4483 structures are passed. These are defined to be passed
4484 in int regs if possible, otherwise memory. */
4485 int packed_p = 0;
4486
4487 /* First see what kinds of registers we need. */
4488 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4489 {
4490 if (TREE_CODE (field) == FIELD_DECL)
4491 {
4492 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4493 && TARGET_FPU)
4494 fpregs_p = 1;
4495 else
4496 intregs_p = 1;
4497 if (DECL_PACKED (field))
4498 packed_p = 1;
4499 }
4500 }
4501 if (packed_p || !named)
4502 fpregs_p = 0, intregs_p = 1;
4503
4504 /* If all arg slots are filled, then must pass on stack. */
4505 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4506 return -1;
4507 /* If there are only int args and all int arg slots are filled,
4508 then must pass on stack. */
4509 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4510 return -1;
4511 /* Note that even if all int arg slots are filled, fp members may
4512 still be passed in regs if such regs are available.
4513 *PREGNO isn't set because there may be more than one, it's up
4514 to the caller to compute them. */
4515 return slotno;
4516 }
4517 break;
4518
4519 default :
4520 abort ();
4521 }
4522
4523 *pregno = regno;
4524 return slotno;
4525}
4526
8e1581a1 4527/* Handle recursive register counting for structure field layout. */
4528
4529struct function_arg_record_value_parms
4530{
4531 rtx ret;
4532 int slotno, named, regbase;
0eacd412 4533 unsigned int nregs;
4534 int intoffset;
8e1581a1 4535};
4536
35415df4 4537static void function_arg_record_value_3
0eacd412 4538 PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *));
35415df4 4539static void function_arg_record_value_2
0eacd412 4540 PARAMS ((tree, HOST_WIDE_INT,
4541 struct function_arg_record_value_parms *));
075136a2 4542static void function_arg_record_value_1
0eacd412 4543 PARAMS ((tree, HOST_WIDE_INT,
4544 struct function_arg_record_value_parms *));
35415df4 4545static rtx function_arg_record_value
32bd1bda 4546 PARAMS ((tree, enum machine_mode, int, int, int));
35415df4 4547
a41c9e1b 4548/* A subroutine of function_arg_record_value. Traverse the structure
4549 recusively and determine how many registers will be required. */
4550
8e1581a1 4551static void
4552function_arg_record_value_1 (type, startbitpos, parms)
4553 tree type;
0eacd412 4554 HOST_WIDE_INT startbitpos;
8e1581a1 4555 struct function_arg_record_value_parms *parms;
4556{
4557 tree field;
4558
4559 /* The ABI obviously doesn't specify how packed structures are
4560 passed. These are defined to be passed in int regs if possible,
4561 otherwise memory. */
4562 int packed_p = 0;
4563
4564 /* We need to compute how many registers are needed so we can
4565 allocate the PARALLEL but before we can do that we need to know
4566 whether there are any packed fields. If there are, int regs are
4567 used regardless of whether there are fp values present. */
4568 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4569 {
4570 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4571 {
4572 packed_p = 1;
4573 break;
4574 }
4575 }
4576
4577 /* Compute how many registers we need. */
4578 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4579 {
4580 if (TREE_CODE (field) == FIELD_DECL)
4581 {
0eacd412 4582 HOST_WIDE_INT bitpos = startbitpos;
4583
4584 if (DECL_SIZE (field) != 0
4585 && host_integerp (bit_position (field), 1))
4586 bitpos += int_bit_position (field);
4587
8e1581a1 4588 /* ??? FIXME: else assume zero offset. */
4589
4590 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
0eacd412 4591 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
d85b9058 4592 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4593 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4594 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4595 == REAL_TYPE)))
8e1581a1 4596 && TARGET_FPU
4597 && ! packed_p
4598 && parms->named)
4599 {
4600 if (parms->intoffset != -1)
4601 {
4602 int intslots, this_slotno;
4603
4604 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
4605 / BITS_PER_WORD;
4606 this_slotno = parms->slotno + parms->intoffset
4607 / BITS_PER_WORD;
4608
4609 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4610 intslots = MAX (intslots, 0);
4611 parms->nregs += intslots;
4612 parms->intoffset = -1;
4613 }
4614
4615 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4616 If it wasn't true we wouldn't be here. */
4617 parms->nregs += 1;
d85b9058 4618 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4619 parms->nregs += 1;
8e1581a1 4620 }
4621 else
4622 {
4623 if (parms->intoffset == -1)
4624 parms->intoffset = bitpos;
4625 }
4626 }
4627 }
4628}
4629
a41c9e1b 4630/* A subroutine of function_arg_record_value. Assign the bits of the
4631 structure between parms->intoffset and bitpos to integer registers. */
8e1581a1 4632
4633static void
4634function_arg_record_value_3 (bitpos, parms)
0eacd412 4635 HOST_WIDE_INT bitpos;
8e1581a1 4636 struct function_arg_record_value_parms *parms;
4637{
4638 enum machine_mode mode;
0eacd412 4639 unsigned int regno;
a41c9e1b 4640 unsigned int startbit, endbit;
0eacd412 4641 int this_slotno, intslots, intoffset;
8e1581a1 4642 rtx reg;
4643
4644 if (parms->intoffset == -1)
4645 return;
0eacd412 4646
8e1581a1 4647 intoffset = parms->intoffset;
4648 parms->intoffset = -1;
4649
a41c9e1b 4650 startbit = intoffset & -BITS_PER_WORD;
4651 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4652 intslots = (endbit - startbit) / BITS_PER_WORD;
8e1581a1 4653 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
4654
4655 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4656 if (intslots <= 0)
4657 return;
4658
4659 /* If this is the trailing part of a word, only load that much into
4660 the register. Otherwise load the whole register. Note that in
4661 the latter case we may pick up unwanted bits. It's not a problem
4662 at the moment but may wish to revisit. */
4663
4664 if (intoffset % BITS_PER_WORD != 0)
0eacd412 4665 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4666 MODE_INT, 0);
8e1581a1 4667 else
4668 mode = word_mode;
4669
4670 intoffset /= BITS_PER_UNIT;
4671 do
4672 {
4673 regno = parms->regbase + this_slotno;
5a5d82d2 4674 reg = gen_rtx_REG (mode, regno);
8e1581a1 4675 XVECEXP (parms->ret, 0, parms->nregs)
5a5d82d2 4676 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
8e1581a1 4677
4678 this_slotno += 1;
4679 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4680 parms->nregs += 1;
4681 intslots -= 1;
4682 }
4683 while (intslots > 0);
4684}
4685
a41c9e1b 4686/* A subroutine of function_arg_record_value. Traverse the structure
4687 recursively and assign bits to floating point registers. Track which
4688 bits in between need integer registers; invoke function_arg_record_value_3
4689 to make that happen. */
4690
8e1581a1 4691static void
4692function_arg_record_value_2 (type, startbitpos, parms)
4693 tree type;
0eacd412 4694 HOST_WIDE_INT startbitpos;
8e1581a1 4695 struct function_arg_record_value_parms *parms;
4696{
4697 tree field;
4698 int packed_p = 0;
4699
4700 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4701 {
4702 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4703 {
4704 packed_p = 1;
4705 break;
4706 }
4707 }
4708
4709 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4710 {
4711 if (TREE_CODE (field) == FIELD_DECL)
4712 {
0eacd412 4713 HOST_WIDE_INT bitpos = startbitpos;
4714
4715 if (DECL_SIZE (field) != 0
4716 && host_integerp (bit_position (field), 1))
4717 bitpos += int_bit_position (field);
4718
8e1581a1 4719 /* ??? FIXME: else assume zero offset. */
4720
4721 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
0eacd412 4722 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
d85b9058 4723 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4724 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4725 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4726 == REAL_TYPE)))
8e1581a1 4727 && TARGET_FPU
4728 && ! packed_p
4729 && parms->named)
4730 {
4731 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
d85b9058 4732 int regno;
4733 enum machine_mode mode = DECL_MODE (field);
8e1581a1 4734 rtx reg;
4735
4736 function_arg_record_value_3 (bitpos, parms);
d85b9058 4737 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
4738 + ((mode == SFmode || mode == SCmode)
4739 && (bitpos & 32) != 0);
4740 switch (mode)
4741 {
4742 case SCmode: mode = SFmode; break;
4743 case DCmode: mode = DFmode; break;
4744 case TCmode: mode = TFmode; break;
4745 default: break;
4746 }
4747 reg = gen_rtx_REG (mode, regno);
8e1581a1 4748 XVECEXP (parms->ret, 0, parms->nregs)
5a5d82d2 4749 = gen_rtx_EXPR_LIST (VOIDmode, reg,
8e1581a1 4750 GEN_INT (bitpos / BITS_PER_UNIT));
4751 parms->nregs += 1;
d85b9058 4752 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4753 {
4754 regno += GET_MODE_SIZE (mode) / 4;
4755 reg = gen_rtx_REG (mode, regno);
4756 XVECEXP (parms->ret, 0, parms->nregs)
4757 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4758 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
4759 / BITS_PER_UNIT));
4760 parms->nregs += 1;
4761 }
8e1581a1 4762 }
4763 else
4764 {
4765 if (parms->intoffset == -1)
4766 parms->intoffset = bitpos;
4767 }
4768 }
4769 }
4770}
4771
a41c9e1b 4772/* Used by function_arg and function_value to implement the complex
f25a48be 4773 SPARC64 structure calling conventions. */
a41c9e1b 4774
8e1581a1 4775static rtx
5382622f 4776function_arg_record_value (type, mode, slotno, named, regbase)
8e1581a1 4777 tree type;
5382622f 4778 enum machine_mode mode;
8e1581a1 4779 int slotno, named, regbase;
4780{
4781 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4782 struct function_arg_record_value_parms parms;
0eacd412 4783 unsigned int nregs;
8e1581a1 4784
4785 parms.ret = NULL_RTX;
4786 parms.slotno = slotno;
4787 parms.named = named;
4788 parms.regbase = regbase;
4789
4790 /* Compute how many registers we need. */
4791 parms.nregs = 0;
4792 parms.intoffset = 0;
4793 function_arg_record_value_1 (type, 0, &parms);
4794
4795 if (parms.intoffset != -1)
4796 {
a41c9e1b 4797 unsigned int startbit, endbit;
8e1581a1 4798 int intslots, this_slotno;
4799
a41c9e1b 4800 startbit = parms.intoffset & -BITS_PER_WORD;
4801 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4802 intslots = (endbit - startbit) / BITS_PER_WORD;
8e1581a1 4803 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
4804
4805 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4806 intslots = MAX (intslots, 0);
4807
4808 parms.nregs += intslots;
4809 }
4810 nregs = parms.nregs;
4811
4812 /* Allocate the vector and handle some annoying special cases. */
4813 if (nregs == 0)
4814 {
4815 /* ??? Empty structure has no value? Duh? */
4816 if (typesize <= 0)
4817 {
4818 /* Though there's nothing really to store, return a word register
4819 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4820 leads to breakage due to the fact that there are zero bytes to
4821 load. */
5382622f 4822 return gen_rtx_REG (mode, regbase);
8e1581a1 4823 }
4824 else
4825 {
4826 /* ??? C++ has structures with no fields, and yet a size. Give up
4827 for now and pass everything back in integer registers. */
4828 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4829 }
4830 if (nregs + slotno > SPARC_INT_ARG_MAX)
4831 nregs = SPARC_INT_ARG_MAX - slotno;
4832 }
4833 if (nregs == 0)
8703a12c 4834 abort ();
8e1581a1 4835
5382622f 4836 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
8e1581a1 4837
4838 /* Fill in the entries. */
4839 parms.nregs = 0;
4840 parms.intoffset = 0;
4841 function_arg_record_value_2 (type, 0, &parms);
4842 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
4843
4844 if (parms.nregs != nregs)
4845 abort ();
4846
4847 return parms.ret;
4848}
4849
279e8405 4850/* Handle the FUNCTION_ARG macro.
4851 Determine where to put an argument to a function.
4852 Value is zero to push the argument on the stack,
4853 or a hard register in which to store the argument.
4854
4855 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4856 the preceding args and about the function being called.
4857 MODE is the argument's machine mode.
4858 TYPE is the data type of the argument (as a tree).
4859 This is null for libcalls where that information may
4860 not be available.
4861 NAMED is nonzero if this argument is a named parameter
4862 (otherwise it is an extra parameter matching an ellipsis).
4863 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
6dac3578 4864
4865rtx
279e8405 4866function_arg (cum, mode, type, named, incoming_p)
4867 const CUMULATIVE_ARGS *cum;
4868 enum machine_mode mode;
4869 tree type;
4870 int named;
4871 int incoming_p;
6dac3578 4872{
279e8405 4873 int regbase = (incoming_p
4874 ? SPARC_INCOMING_INT_ARG_FIRST
4875 : SPARC_OUTGOING_INT_ARG_FIRST);
4876 int slotno, regno, padding;
4877 rtx reg;
4878
4879 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
4880 &regno, &padding);
4881
4882 if (slotno == -1)
4883 return 0;
4884
4885 if (TARGET_ARCH32)
4886 {
5a5d82d2 4887 reg = gen_rtx_REG (mode, regno);
279e8405 4888 return reg;
4889 }
4890
4891 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4892 but also have the slot allocated for them.
4893 If no prototype is in scope fp values in register slots get passed
4894 in two places, either fp regs and int regs or fp regs and memory. */
4895 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4896 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4897 && SPARC_FP_REG_P (regno))
4898 {
5a5d82d2 4899 reg = gen_rtx_REG (mode, regno);
279e8405 4900 if (cum->prototype_p || cum->libcall_p)
4901 {
4902 /* "* 2" because fp reg numbers are recorded in 4 byte
4903 quantities. */
8e1581a1 4904#if 0
279e8405 4905 /* ??? This will cause the value to be passed in the fp reg and
4906 in the stack. When a prototype exists we want to pass the
4907 value in the reg but reserve space on the stack. That's an
ad87de1e 4908 optimization, and is deferred [for a bit]. */
279e8405 4909 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5a5d82d2 4910 return gen_rtx_PARALLEL (mode,
279e8405 4911 gen_rtvec (2,
5a5d82d2 4912 gen_rtx_EXPR_LIST (VOIDmode,
279e8405 4913 NULL_RTX, const0_rtx),
5a5d82d2 4914 gen_rtx_EXPR_LIST (VOIDmode,
279e8405 4915 reg, const0_rtx)));
4916 else
8e1581a1 4917#else
4918 /* ??? It seems that passing back a register even when past
4919 the area declared by REG_PARM_STACK_SPACE will allocate
4920 space appropriately, and will not copy the data onto the
4921 stack, exactly as we desire.
4922
4923 This is due to locate_and_pad_parm being called in
4924 expand_call whenever reg_parm_stack_space > 0, which
4925 while benefical to our example here, would seem to be
4926 in error from what had been intended. Ho hum... -- r~ */
4927#endif
279e8405 4928 return reg;
4929 }
4930 else
4931 {
8e1581a1 4932 rtx v0, v1;
4933
279e8405 4934 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
4935 {
8e1581a1 4936 int intreg;
4937
4938 /* On incoming, we don't need to know that the value
4939 is passed in %f0 and %i0, and it confuses other parts
4940 causing needless spillage even on the simplest cases. */
4941 if (incoming_p)
4942 return reg;
4943
4944 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
4945 + (regno - SPARC_FP_ARG_FIRST) / 2);
4946
4947 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4948 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
4949 const0_rtx);
4950 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
279e8405 4951 }
4952 else
8e1581a1 4953 {
4954 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4955 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4956 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4957 }
279e8405 4958 }
4959 }
4960 else if (type && TREE_CODE (type) == RECORD_TYPE)
4961 {
4962 /* Structures up to 16 bytes in size are passed in arg slots on the
4963 stack and are promoted to registers where possible. */
279e8405 4964
4965 if (int_size_in_bytes (type) > 16)
4966 abort (); /* shouldn't get here */
4967
5382622f 4968 return function_arg_record_value (type, mode, slotno, named, regbase);
279e8405 4969 }
4970 else if (type && TREE_CODE (type) == UNION_TYPE)
4971 {
4972 enum machine_mode mode;
4973 int bytes = int_size_in_bytes (type);
4974
4975 if (bytes > 16)
4976 abort ();
4977
4978 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5a5d82d2 4979 reg = gen_rtx_REG (mode, regno);
279e8405 4980 }
6e8d7882 4981 else
279e8405 4982 {
4983 /* Scalar or complex int. */
5a5d82d2 4984 reg = gen_rtx_REG (mode, regno);
279e8405 4985 }
4986
4987 return reg;
4988}
6e8d7882 4989
279e8405 4990/* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4991 For an arg passed partly in registers and partly in memory,
4992 this is the number of registers used.
4993 For args passed entirely in registers or entirely in memory, zero.
6dac3578 4994
279e8405 4995 Any arg that starts in the first 6 regs but won't entirely fit in them
4996 needs partial registers on v8. On v9, structures with integer
4997 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4998 values that begin in the last fp reg [where "last fp reg" varies with the
4999 mode] will be split between that reg and memory. */
6dac3578 5000
279e8405 5001int
5002function_arg_partial_nregs (cum, mode, type, named)
5003 const CUMULATIVE_ARGS *cum;
5004 enum machine_mode mode;
5005 tree type;
5006 int named;
5007{
5008 int slotno, regno, padding;
6dac3578 5009
279e8405 5010 /* We pass 0 for incoming_p here, it doesn't matter. */
5011 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5012
5013 if (slotno == -1)
5014 return 0;
5015
5016 if (TARGET_ARCH32)
77d3d2a4 5017 {
279e8405 5018 if ((slotno + (mode == BLKmode
5019 ? ROUND_ADVANCE (int_size_in_bytes (type))
5020 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5021 > NPARM_REGS (SImode))
5022 return NPARM_REGS (SImode) - slotno;
5023 return 0;
5024 }
5025 else
5026 {
5027 if (type && AGGREGATE_TYPE_P (type))
5028 {
5029 int size = int_size_in_bytes (type);
5030 int align = TYPE_ALIGN (type);
77d3d2a4 5031
279e8405 5032 if (align == 16)
5033 slotno += slotno & 1;
5034 if (size > 8 && size <= 16
5035 && slotno == SPARC_INT_ARG_MAX - 1)
5036 return 1;
5037 }
5038 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5039 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5040 && ! TARGET_FPU))
5041 {
5042 if (GET_MODE_ALIGNMENT (mode) == 128)
5043 {
5044 slotno += slotno & 1;
5045 if (slotno == SPARC_INT_ARG_MAX - 2)
5046 return 1;
5047 }
5048 else
5049 {
5050 if (slotno == SPARC_INT_ARG_MAX - 1)
5051 return 1;
5052 }
5053 }
5054 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5055 {
5056 if (GET_MODE_ALIGNMENT (mode) == 128)
5057 slotno += slotno & 1;
5058 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5059 > SPARC_FP_ARG_MAX)
5060 return 1;
5061 }
5062 return 0;
77d3d2a4 5063 }
279e8405 5064}
6dac3578 5065
279e8405 5066/* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5067 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5068 quad-precision floats by invisible reference.
8e1581a1 5069 v9: Aggregates greater than 16 bytes are passed by reference.
279e8405 5070 For Pascal, also pass arrays by reference. */
5071
5072int
5073function_arg_pass_by_reference (cum, mode, type, named)
b8430a2d 5074 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
279e8405 5075 enum machine_mode mode;
5076 tree type;
b8430a2d 5077 int named ATTRIBUTE_UNUSED;
279e8405 5078{
5079 if (TARGET_ARCH32)
83804c70 5080 {
07e64d6e 5081 return ((type && AGGREGATE_TYPE_P (type))
279e8405 5082 || mode == TFmode || mode == TCmode);
5083 }
5084 else
5085 {
5086 return ((type && TREE_CODE (type) == ARRAY_TYPE)
8eba0400 5087 /* Consider complex values as aggregates, so care for TCmode. */
8e1581a1 5088 || GET_MODE_SIZE (mode) > 16
a719ae01 5089 || (type
5090 && AGGREGATE_TYPE_P (type)
5091 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
279e8405 5092 }
5093}
5094
5095/* Handle the FUNCTION_ARG_ADVANCE macro.
5096 Update the data in CUM to advance over an argument
5097 of mode MODE and data type TYPE.
5098 TYPE is null for libcalls where that information may not be available. */
5099
5100void
5101function_arg_advance (cum, mode, type, named)
5102 CUMULATIVE_ARGS *cum;
5103 enum machine_mode mode;
5104 tree type;
5105 int named;
5106{
5107 int slotno, regno, padding;
5108
5109 /* We pass 0 for incoming_p here, it doesn't matter. */
5110 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5111
5112 /* If register required leading padding, add it. */
5113 if (slotno != -1)
5114 cum->words += padding;
83804c70 5115
279e8405 5116 if (TARGET_ARCH32)
5117 {
5118 cum->words += (mode != BLKmode
5119 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5120 : ROUND_ADVANCE (int_size_in_bytes (type)));
5121 }
5122 else
5123 {
5124 if (type && AGGREGATE_TYPE_P (type))
5125 {
5126 int size = int_size_in_bytes (type);
5127
5128 if (size <= 8)
5129 ++cum->words;
5130 else if (size <= 16)
5131 cum->words += 2;
5132 else /* passed by reference */
5133 ++cum->words;
5134 }
5135 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
5136 {
5137 cum->words += 2;
5138 }
5139 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5140 {
5141 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
5142 }
5143 else
5144 {
5145 cum->words += (mode != BLKmode
5146 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5147 : ROUND_ADVANCE (int_size_in_bytes (type)));
5148 }
83804c70 5149 }
279e8405 5150}
83804c70 5151
279e8405 5152/* Handle the FUNCTION_ARG_PADDING macro.
5153 For the 64 bit ABI structs are always stored left shifted in their
5154 argument slot. */
5155
5156enum direction
5157function_arg_padding (mode, type)
5158 enum machine_mode mode;
5159 tree type;
5160{
220345e0 5161 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5162 return upward;
6dac3578 5163
279e8405 5164 /* This is the default definition. */
5165 return (! BYTES_BIG_ENDIAN
5166 ? upward
5167 : ((mode == BLKmode
5168 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5169 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
5170 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5171 ? downward : upward));
6dac3578 5172}
8e1581a1 5173
5174/* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5175 For v9, function return values are subject to the same rules as arguments,
5176 except that up to 32-bytes may be returned in registers. */
5177
5178rtx
5179function_value (type, mode, incoming_p)
5180 tree type;
5181 enum machine_mode mode;
5182 int incoming_p;
5183{
5184 int regno;
5185 int regbase = (incoming_p
5186 ? SPARC_OUTGOING_INT_ARG_FIRST
5187 : SPARC_INCOMING_INT_ARG_FIRST);
5188
5189 if (TARGET_ARCH64 && type)
5190 {
5191 if (TREE_CODE (type) == RECORD_TYPE)
5192 {
5193 /* Structures up to 32 bytes in size are passed in registers,
5194 promoted to fp registers where possible. */
5195
5196 if (int_size_in_bytes (type) > 32)
5197 abort (); /* shouldn't get here */
5198
5382622f 5199 return function_arg_record_value (type, mode, 0, 1, regbase);
8e1581a1 5200 }
e6986def 5201 else if (AGGREGATE_TYPE_P (type))
8e1581a1 5202 {
e6986def 5203 /* All other aggregate types are passed in an integer register
5204 in a mode corresponding to the size of the type. */
5205 HOST_WIDE_INT bytes = int_size_in_bytes (type);
8e1581a1 5206
5207 if (bytes > 32)
5208 abort ();
5209
5210 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5211 }
5212 }
71d83a98 5213
5214 if (TARGET_ARCH64
5215 && GET_MODE_CLASS (mode) == MODE_INT
5216 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
e6986def 5217 && type && ! AGGREGATE_TYPE_P (type))
71d83a98 5218 mode = DImode;
8e1581a1 5219
5220 if (incoming_p)
5221 regno = BASE_RETURN_VALUE_REG (mode);
5222 else
5223 regno = BASE_OUTGOING_VALUE_REG (mode);
5224
5a5d82d2 5225 return gen_rtx_REG (mode, regno);
8e1581a1 5226}
5227
55f54832 5228/* Do what is necessary for `va_start'. We look at the current function
5229 to determine if stdarg or varargs is used and return the address of
5230 the first unnamed parameter. */
d9a5f7c9 5231
5232rtx
55f54832 5233sparc_builtin_saveregs ()
d9a5f7c9 5234{
279e8405 5235 int first_reg = current_function_args_info.words;
d9a5f7c9 5236 rtx address;
5237 int regno;
5238
279e8405 5239 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5a5d82d2 5240 emit_move_insn (gen_rtx_MEM (word_mode,
2a631e19 5241 gen_rtx_PLUS (Pmode,
5242 frame_pointer_rtx,
04a917bf 5243 GEN_INT (FIRST_PARM_OFFSET (0)
2a631e19 5244 + (UNITS_PER_WORD
5245 * regno)))),
5a5d82d2 5246 gen_rtx_REG (word_mode,
2a631e19 5247 BASE_INCOMING_ARG_REG (word_mode) + regno));
d9a5f7c9 5248
5a5d82d2 5249 address = gen_rtx_PLUS (Pmode,
2a631e19 5250 frame_pointer_rtx,
04a917bf 5251 GEN_INT (FIRST_PARM_OFFSET (0)
2a631e19 5252 + UNITS_PER_WORD * first_reg));
d9a5f7c9 5253
5254 return address;
5255}
a9592900 5256
5257/* Implement `va_start' for varargs and stdarg. */
5258
5259void
7df226a2 5260sparc_va_start (valist, nextarg)
a9592900 5261 tree valist;
5262 rtx nextarg;
5263{
5264 nextarg = expand_builtin_saveregs ();
7df226a2 5265 std_expand_builtin_va_start (valist, nextarg);
a9592900 5266}
5267
5268/* Implement `va_arg'. */
5269
5270rtx
5271sparc_va_arg (valist, type)
5272 tree valist, type;
5273{
5274 HOST_WIDE_INT size, rsize, align;
9b7006ea 5275 tree addr, incr;
a9592900 5276 rtx addr_rtx;
5277 int indirect = 0;
5278
5279 /* Round up sizeof(type) to a word. */
5280 size = int_size_in_bytes (type);
5281 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5282 align = 0;
5283
5284 if (TARGET_ARCH64)
5285 {
779433ea 5286 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
a9592900 5287 align = 2 * UNITS_PER_WORD;
5288
3fcfb723 5289 if (AGGREGATE_TYPE_P (type))
a9592900 5290 {
a719ae01 5291 if ((unsigned HOST_WIDE_INT) size > 16)
3fcfb723 5292 {
5293 indirect = 1;
5294 size = rsize = UNITS_PER_WORD;
5295 }
992443f3 5296 /* SPARC v9 ABI states that structures up to 8 bytes in size are
5297 given one 8 byte slot. */
5298 else if (size == 0)
5299 size = rsize = UNITS_PER_WORD;
3fcfb723 5300 else
5301 size = rsize;
a9592900 5302 }
5303 }
5304 else
5305 {
5306 if (AGGREGATE_TYPE_P (type)
5307 || TYPE_MODE (type) == TFmode
5308 || TYPE_MODE (type) == TCmode)
5309 {
5310 indirect = 1;
5311 size = rsize = UNITS_PER_WORD;
5312 }
a9592900 5313 }
5314
5315 incr = valist;
5316 if (align)
5317 {
5318 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5319 build_int_2 (align - 1, 0)));
5320 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5321 build_int_2 (-align, -1)));
5322 }
5323
5324 addr = incr = save_expr (incr);
5325 if (BYTES_BIG_ENDIAN && size < rsize)
5326 {
5327 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5328 build_int_2 (rsize - size, 0)));
5329 }
5330 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5331 build_int_2 (rsize, 0)));
5332
5333 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5334 TREE_SIDE_EFFECTS (incr) = 1;
5335 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5336
5337 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5338
83b2aef3 5339 /* If the address isn't aligned properly for the type,
5340 we may need to copy to a temporary.
5341 FIXME: This is inefficient. Usually we can do this
5342 in registers. */
5343 if (align == 0
5344 && TYPE_ALIGN (type) > BITS_PER_WORD
5345 && !indirect)
5346 {
5347 /* FIXME: We really need to specify that the temporary is live
5348 for the whole function because expand_builtin_va_arg wants
5349 the alias set to be get_varargs_alias_set (), but in this
5350 case the alias set is that for TYPE and if the memory gets
5351 reused it will be reused with alias set TYPE. */
5352 rtx tmp = assign_temp (type, 0, 1, 0);
5353 rtx dest_addr;
5354
5355 addr_rtx = force_reg (Pmode, addr_rtx);
5356 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
ab6ab77e 5357 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
2a631e19 5358 set_mem_align (addr_rtx, BITS_PER_WORD);
83b2aef3 5359 tmp = shallow_copy_rtx (tmp);
5360 PUT_MODE (tmp, BLKmode);
ab6ab77e 5361 set_mem_alias_set (tmp, 0);
83b2aef3 5362
0378dbdc 5363 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
5364 BLOCK_OP_NORMAL);
83b2aef3 5365 if (dest_addr != NULL_RTX)
5366 addr_rtx = dest_addr;
5367 else
5368 addr_rtx = XCEXP (tmp, 0, MEM);
5369 }
5370
a9592900 5371 if (indirect)
5372 {
5373 addr_rtx = force_reg (Pmode, addr_rtx);
5374 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
ab6ab77e 5375 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
a9592900 5376 }
5377
5378 return addr_rtx;
5379}
823baf68 5380\f
5381/* Return the string to output a conditional branch to LABEL, which is
946e12d1 5382 the operand number of the label. OP is the conditional expression.
5383 XEXP (OP, 0) is assumed to be a condition code register (integer or
5384 floating point) and its mode specifies what kind of comparison we made.
6dac3578 5385
808a491c 5386 REVERSED is nonzero if we should reverse the sense of the comparison.
823baf68 5387
808a491c 5388 ANNUL is nonzero if we should generate an annulling branch.
823baf68 5389
808a491c 5390 NOOP is nonzero if we have to follow this branch by a noop.
58dc6b1f 5391
5392 INSN, if set, is the insn. */
823baf68 5393
5394char *
ebd2c2bf 5395output_cbranch (op, dest, label, reversed, annul, noop, insn)
5396 rtx op, dest;
823baf68 5397 int label;
5398 int reversed, annul, noop;
58dc6b1f 5399 rtx insn;
823baf68 5400{
ebd2c2bf 5401 static char string[50];
823baf68 5402 enum rtx_code code = GET_CODE (op);
946e12d1 5403 rtx cc_reg = XEXP (op, 0);
5404 enum machine_mode mode = GET_MODE (cc_reg);
ebd2c2bf 5405 const char *labelno, *branch;
5406 int spaces = 8, far;
5407 char *p;
5408
5409 /* v9 branches are limited to +-1MB. If it is too far away,
5410 change
5411
5412 bne,pt %xcc, .LC30
5413
5414 to
5415
5416 be,pn %xcc, .+12
5417 nop
5418 ba .LC30
5419
5420 and
5421
5422 fbne,a,pn %fcc2, .LC29
6dac3578 5423
ebd2c2bf 5424 to
5425
5426 fbe,pt %fcc2, .+16
5427 nop
5428 ba .LC29 */
5429
5430 far = get_attr_length (insn) >= 3;
5431 if (reversed ^ far)
823baf68 5432 {
9312a956 5433 /* Reversal of FP compares takes care -- an ordered compare
5434 becomes an unordered compare and vice versa. */
7dd970bc 5435 if (mode == CCFPmode || mode == CCFPEmode)
79777bad 5436 code = reverse_condition_maybe_unordered (code);
823baf68 5437 else
9312a956 5438 code = reverse_condition (code);
823baf68 5439 }
5440
9312a956 5441 /* Start by writing the branch condition. */
5442 if (mode == CCFPmode || mode == CCFPEmode)
b76e5a9b 5443 {
5444 switch (code)
5445 {
5446 case NE:
5447 branch = "fbne";
5448 break;
5449 case EQ:
5450 branch = "fbe";
5451 break;
5452 case GE:
5453 branch = "fbge";
5454 break;
5455 case GT:
5456 branch = "fbg";
5457 break;
5458 case LE:
5459 branch = "fble";
5460 break;
5461 case LT:
5462 branch = "fbl";
5463 break;
5464 case UNORDERED:
5465 branch = "fbu";
5466 break;
5467 case ORDERED:
5468 branch = "fbo";
5469 break;
5470 case UNGT:
5471 branch = "fbug";
5472 break;
5473 case UNLT:
5474 branch = "fbul";
5475 break;
5476 case UNEQ:
5477 branch = "fbue";
5478 break;
5479 case UNGE:
5480 branch = "fbuge";
5481 break;
5482 case UNLE:
5483 branch = "fbule";
5484 break;
5485 case LTGT:
5486 branch = "fblg";
5487 break;
5488
5489 default:
5490 abort ();
5491 }
5492
5493 /* ??? !v9: FP branches cannot be preceded by another floating point
5494 insn. Because there is currently no concept of pre-delay slots,
5495 we can fix this only by always emitting a nop before a floating
5496 point branch. */
5497
5498 string[0] = '\0';
5499 if (! TARGET_V9)
5500 strcpy (string, "nop\n\t");
5501 strcat (string, branch);
5502 }
9312a956 5503 else
b76e5a9b 5504 {
5505 switch (code)
5506 {
5507 case NE:
5508 branch = "bne";
5509 break;
5510 case EQ:
5511 branch = "be";
5512 break;
5513 case GE:
ebd2c2bf 5514 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
b76e5a9b 5515 branch = "bpos";
5516 else
5517 branch = "bge";
5518 break;
5519 case GT:
5520 branch = "bg";
5521 break;
5522 case LE:
5523 branch = "ble";
5524 break;
5525 case LT:
ebd2c2bf 5526 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
b76e5a9b 5527 branch = "bneg";
5528 else
5529 branch = "bl";
5530 break;
5531 case GEU:
5532 branch = "bgeu";
5533 break;
5534 case GTU:
5535 branch = "bgu";
5536 break;
5537 case LEU:
5538 branch = "bleu";
5539 break;
5540 case LTU:
5541 branch = "blu";
5542 break;
5543
5544 default:
5545 abort ();
5546 }
5547 strcpy (string, branch);
5548 }
9312a956 5549 spaces -= strlen (branch);
ebd2c2bf 5550 p = strchr (string, '\0');
9312a956 5551
823baf68 5552 /* Now add the annulling, the label, and a possible noop. */
ebd2c2bf 5553 if (annul && ! far)
998032ba 5554 {
ebd2c2bf 5555 strcpy (p, ",a");
5556 p += 2;
998032ba 5557 spaces -= 2;
5558 }
823baf68 5559
6dac3578 5560 if (! TARGET_V9)
ebd2c2bf 5561 labelno = "";
6dac3578 5562 else
5563 {
58dc6b1f 5564 rtx note;
ebd2c2bf 5565 int v8 = 0;
58dc6b1f 5566
ebd2c2bf 5567 if (! far && insn && INSN_ADDRESSES_SET_P ())
998032ba 5568 {
ebd2c2bf 5569 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5570 - INSN_ADDRESSES (INSN_UID (insn)));
5571 /* Leave some instructions for "slop". */
5572 if (delta < -260000 || delta >= 260000)
5573 v8 = 1;
998032ba 5574 }
58dc6b1f 5575
6dac3578 5576 if (mode == CCFPmode || mode == CCFPEmode)
5577 {
ebd2c2bf 5578 static char v9_fcc_labelno[] = "%%fccX, ";
6dac3578 5579 /* Set the char indicating the number of the fcc reg to use. */
ebd2c2bf 5580 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5581 labelno = v9_fcc_labelno;
5582 if (v8)
5583 {
5584 if (REGNO (cc_reg) == SPARC_FCC_REG)
5585 labelno = "";
5586 else
5587 abort ();
5588 }
6dac3578 5589 }
5590 else if (mode == CCXmode || mode == CCX_NOOVmode)
ebd2c2bf 5591 {
5592 labelno = "%%xcc, ";
5593 if (v8)
5594 abort ();
5595 }
6dac3578 5596 else
ebd2c2bf 5597 {
5598 labelno = "%%icc, ";
5599 if (v8)
5600 labelno = "";
5601 }
5602
c3037f18 5603 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
ebd2c2bf 5604 {
5605 strcpy (p,
c3037f18 5606 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
ebd2c2bf 5607 ? ",pt" : ",pn");
5608 p += 3;
5609 spaces -= 3;
5610 }
6dac3578 5611 }
998032ba 5612 if (spaces > 0)
ebd2c2bf 5613 *p++ = '\t';
998032ba 5614 else
ebd2c2bf 5615 *p++ = ' ';
5616 strcpy (p, labelno);
5617 p = strchr (p, '\0');
5618 if (far)
5619 {
5620 strcpy (p, ".+12\n\tnop\n\tb\t");
5621 if (annul || noop)
5622 p[3] = '6';
5623 p += 13;
5624 }
5625 *p++ = '%';
5626 *p++ = 'l';
5627 /* Set the char indicating the number of the operand containing the
5628 label_ref. */
5629 *p++ = label + '0';
5630 *p = '\0';
6dac3578 5631 if (noop)
ebd2c2bf 5632 strcpy (p, "\n\tnop");
6dac3578 5633
5634 return string;
5635}
5636
75997b31 5637/* Emit a library call comparison between floating point X and Y.
5638 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5639 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5640 values as arguments instead of the TFmode registers themselves,
5641 that's why we cannot call emit_float_lib_cmp. */
5642void
5643sparc_emit_float_lib_cmp (x, y, comparison)
5644 rtx x, y;
5645 enum rtx_code comparison;
5646{
5e431971 5647 const char *qpfunc;
b59496fa 5648 rtx slot0, slot1, result, tem, tem2;
5649 enum machine_mode mode;
75997b31 5650
5651 switch (comparison)
5652 {
5653 case EQ:
b59496fa 5654 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
75997b31 5655 break;
5656
5657 case NE:
b59496fa 5658 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
75997b31 5659 break;
5660
5661 case GT:
b59496fa 5662 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
75997b31 5663 break;
5664
5665 case GE:
b59496fa 5666 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
75997b31 5667 break;
5668
5669 case LT:
b59496fa 5670 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
75997b31 5671 break;
5672
5673 case LE:
b59496fa 5674 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
5675 break;
5676
5677 case ORDERED:
5678 case UNORDERED:
5679 case UNGT:
5680 case UNLT:
5681 case UNEQ:
5682 case UNGE:
5683 case UNLE:
5684 case LTGT:
5685 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
75997b31 5686 break;
5687
5688 default:
5689 abort();
5690 break;
5691 }
5692
b59496fa 5693 if (TARGET_ARCH64)
75997b31 5694 {
b59496fa 5695 if (GET_CODE (x) != MEM)
5696 {
5697 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5698 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
5699 }
5700 else
5701 slot0 = x;
5702
5703 if (GET_CODE (y) != MEM)
5704 {
5705 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5706 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
5707 }
5708 else
5709 slot1 = y;
75997b31 5710
61f83895 5711 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
b59496fa 5712 DImode, 2,
5713 XEXP (slot0, 0), Pmode,
5714 XEXP (slot1, 0), Pmode);
5715
5716 mode = DImode;
5717 }
5718 else
75997b31 5719 {
61f83895 5720 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
b59496fa 5721 SImode, 2,
5722 x, TFmode, y, TFmode);
5723
5724 mode = SImode;
75997b31 5725 }
5726
75997b31 5727
5728 /* Immediately move the result of the libcall into a pseudo
5729 register so reload doesn't clobber the value if it needs
5730 the return register for a spill reg. */
b59496fa 5731 result = gen_reg_rtx (mode);
5732 emit_move_insn (result, hard_libcall_value (mode));
75997b31 5733
b59496fa 5734 switch (comparison)
5735 {
5736 default:
44a2b912 5737 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
b59496fa 5738 break;
5739 case ORDERED:
5740 case UNORDERED:
44a2b912 5741 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
5742 NULL_RTX, mode, 0);
b59496fa 5743 break;
5744 case UNGT:
5745 case UNGE:
5746 emit_cmp_insn (result, const1_rtx,
44a2b912 5747 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
b59496fa 5748 break;
5749 case UNLE:
44a2b912 5750 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
b59496fa 5751 break;
5752 case UNLT:
5753 tem = gen_reg_rtx (mode);
5754 if (TARGET_ARCH32)
5755 emit_insn (gen_andsi3 (tem, result, const1_rtx));
5756 else
5757 emit_insn (gen_anddi3 (tem, result, const1_rtx));
44a2b912 5758 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
b59496fa 5759 break;
5760 case UNEQ:
5761 case LTGT:
5762 tem = gen_reg_rtx (mode);
5763 if (TARGET_ARCH32)
5764 emit_insn (gen_addsi3 (tem, result, const1_rtx));
5765 else
5766 emit_insn (gen_adddi3 (tem, result, const1_rtx));
5767 tem2 = gen_reg_rtx (mode);
5768 if (TARGET_ARCH32)
5769 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
5770 else
5771 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
44a2b912 5772 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
5773 NULL_RTX, mode, 0);
b59496fa 5774 break;
5775 }
75997b31 5776}
b59496fa 5777
eef858ab 5778/* Generate an unsigned DImode to FP conversion. This is the same code
5779 optabs would emit if we didn't have TFmode patterns. */
5780
5781void
5782sparc_emit_floatunsdi (operands)
5783 rtx operands[2];
5784{
5785 rtx neglab, donelab, i0, i1, f0, in, out;
5786 enum machine_mode mode;
5787
5788 out = operands[0];
5789 in = force_reg (DImode, operands[1]);
5790 mode = GET_MODE (out);
5791 neglab = gen_label_rtx ();
5792 donelab = gen_label_rtx ();
5793 i0 = gen_reg_rtx (DImode);
5794 i1 = gen_reg_rtx (DImode);
5795 f0 = gen_reg_rtx (mode);
5796
5797 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
5798
5799 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
5800 emit_jump_insn (gen_jump (donelab));
5801 emit_barrier ();
5802
5803 emit_label (neglab);
5804
5805 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
5806 emit_insn (gen_anddi3 (i1, in, const1_rtx));
5807 emit_insn (gen_iordi3 (i0, i0, i1));
5808 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
5809 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
5810
5811 emit_label (donelab);
5812}
5813
6dac3578 5814/* Return the string to output a conditional branch to LABEL, testing
5815 register REG. LABEL is the operand number of the label; REG is the
5816 operand number of the reg. OP is the conditional expression. The mode
5817 of REG says what kind of comparison we made.
5818
808a491c 5819 REVERSED is nonzero if we should reverse the sense of the comparison.
6dac3578 5820
808a491c 5821 ANNUL is nonzero if we should generate an annulling branch.
6dac3578 5822
808a491c 5823 NOOP is nonzero if we have to follow this branch by a noop. */
6dac3578 5824
5825char *
ebd2c2bf 5826output_v9branch (op, dest, reg, label, reversed, annul, noop, insn)
5827 rtx op, dest;
6dac3578 5828 int reg, label;
5829 int reversed, annul, noop;
998032ba 5830 rtx insn;
6dac3578 5831{
ebd2c2bf 5832 static char string[50];
6dac3578 5833 enum rtx_code code = GET_CODE (op);
5834 enum machine_mode mode = GET_MODE (XEXP (op, 0));
998032ba 5835 rtx note;
ebd2c2bf 5836 int far;
5837 char *p;
5838
5839 /* branch on register are limited to +-128KB. If it is too far away,
5840 change
5841
5842 brnz,pt %g1, .LC30
5843
5844 to
5845
5846 brz,pn %g1, .+12
5847 nop
5848 ba,pt %xcc, .LC30
5849
5850 and
5851
5852 brgez,a,pn %o1, .LC29
5853
5854 to
5855
5856 brlz,pt %o1, .+16
5857 nop
5858 ba,pt %xcc, .LC29 */
5859
5860 far = get_attr_length (insn) >= 3;
6dac3578 5861
5862 /* If not floating-point or if EQ or NE, we can just reverse the code. */
ebd2c2bf 5863 if (reversed ^ far)
5864 code = reverse_condition (code);
6dac3578 5865
5866 /* Only 64 bit versions of these instructions exist. */
5867 if (mode != DImode)
5868 abort ();
5869
5870 /* Start by writing the branch condition. */
5871
5872 switch (code)
5873 {
5874 case NE:
5875 strcpy (string, "brnz");
5876 break;
5877
5878 case EQ:
5879 strcpy (string, "brz");
5880 break;
5881
5882 case GE:
5883 strcpy (string, "brgez");
5884 break;
5885
5886 case LT:
5887 strcpy (string, "brlz");
5888 break;
5889
5890 case LE:
5891 strcpy (string, "brlez");
5892 break;
5893
5894 case GT:
5895 strcpy (string, "brgz");
5896 break;
5897
5898 default:
5899 abort ();
5900 }
5901
ebd2c2bf 5902 p = strchr (string, '\0');
5903
6dac3578 5904 /* Now add the annulling, reg, label, and nop. */
ebd2c2bf 5905 if (annul && ! far)
998032ba 5906 {
ebd2c2bf 5907 strcpy (p, ",a");
5908 p += 2;
998032ba 5909 }
6dac3578 5910
c3037f18 5911 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
998032ba 5912 {
ebd2c2bf 5913 strcpy (p,
c3037f18 5914 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
ebd2c2bf 5915 ? ",pt" : ",pn");
5916 p += 3;
998032ba 5917 }
6dac3578 5918
ebd2c2bf 5919 *p = p < string + 8 ? '\t' : ' ';
5920 p++;
5921 *p++ = '%';
5922 *p++ = '0' + reg;
5923 *p++ = ',';
5924 *p++ = ' ';
5925 if (far)
5926 {
5927 int veryfar = 1, delta;
5928
5929 if (INSN_ADDRESSES_SET_P ())
5930 {
5931 delta = (INSN_ADDRESSES (INSN_UID (dest))
5932 - INSN_ADDRESSES (INSN_UID (insn)));
5933 /* Leave some instructions for "slop". */
5934 if (delta >= -260000 && delta < 260000)
5935 veryfar = 0;
5936 }
5937
5938 strcpy (p, ".+12\n\tnop\n\t");
5939 if (annul || noop)
5940 p[3] = '6';
5941 p += 11;
5942 if (veryfar)
5943 {
5944 strcpy (p, "b\t");
5945 p += 2;
5946 }
5947 else
5948 {
5949 strcpy (p, "ba,pt\t%%xcc, ");
5950 p += 13;
5951 }
5952 }
5953 *p++ = '%';
5954 *p++ = 'l';
5955 *p++ = '0' + label;
5956 *p = '\0';
823baf68 5957
5958 if (noop)
ebd2c2bf 5959 strcpy (p, "\n\tnop");
823baf68 5960
5961 return string;
5962}
5963
5a1acad9 5964/* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
5965 Such instructions cannot be used in the delay slot of return insn on v9.
5966 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
5967 */
367242d3 5968
5a1acad9 5969static int
5970epilogue_renumber (where, test)
5971 register rtx *where;
5972 int test;
367242d3 5973{
5a1acad9 5974 register const char *fmt;
5975 register int i;
5976 register enum rtx_code code;
5977
5978 if (*where == 0)
5979 return 0;
5980
5981 code = GET_CODE (*where);
367242d3 5982
5983 switch (code)
5984 {
367242d3 5985 case REG:
5a1acad9 5986 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
5987 return 1;
5988 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
5989 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
5990 case SCRATCH:
5991 case CC0:
5992 case PC:
367242d3 5993 case CONST_INT:
5994 case CONST_DOUBLE:
5a1acad9 5995 return 0;
93e3200a 5996
d815c751 5997 /* Do not replace the frame pointer with the stack pointer because
5998 it can cause the delayed instruction to load below the stack.
5999 This occurs when instructions like:
6000
6001 (set (reg/i:SI 24 %i0)
6002 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6003 (const_int -20 [0xffffffec])) 0))
6004
6005 are in the return delayed slot. */
6006 case PLUS:
6007 if (GET_CODE (XEXP (*where, 0)) == REG
04a917bf 6008 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
d815c751 6009 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6010 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6011 return 1;
6012 break;
6013
6014 case MEM:
6015 if (SPARC_STACK_BIAS
6016 && GET_CODE (XEXP (*where, 0)) == REG
04a917bf 6017 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
d815c751 6018 return 1;
6019 break;
6020
93e3200a 6021 default:
6022 break;
5a1acad9 6023 }
367242d3 6024
5a1acad9 6025 fmt = GET_RTX_FORMAT (code);
367242d3 6026
5a1acad9 6027 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6028 {
6029 if (fmt[i] == 'E')
6030 {
6031 register int j;
6032 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6033 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6034 return 1;
6035 }
6036 else if (fmt[i] == 'e'
6037 && epilogue_renumber (&(XEXP (*where, i)), test))
6038 return 1;
367242d3 6039 }
5a1acad9 6040 return 0;
367242d3 6041}
823baf68 6042\f
6043/* Leaf functions and non-leaf functions have different needs. */
6044
e99c3a1d 6045static const int
823baf68 6046reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6047
e99c3a1d 6048static const int
823baf68 6049reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6050
e99c3a1d 6051static const int *const reg_alloc_orders[] = {
823baf68 6052 reg_leaf_alloc_order,
6053 reg_nonleaf_alloc_order};
6054
6055void
6056order_regs_for_local_alloc ()
6057{
6058 static int last_order_nonleaf = 1;
6059
6060 if (regs_ever_live[15] != last_order_nonleaf)
6061 {
6062 last_order_nonleaf = !last_order_nonleaf;
8e547276 6063 memcpy ((char *) reg_alloc_order,
e99c3a1d 6064 (const char *) reg_alloc_orders[last_order_nonleaf],
8e547276 6065 FIRST_PSEUDO_REGISTER * sizeof (int));
823baf68 6066 }
6067}
6068\f
998032ba 6069/* Return 1 if REG and MEM are legitimate enough to allow the various
6070 mem<-->reg splits to be run. */
6071
6072int
9ef15f91 6073sparc_splitdi_legitimate (reg, mem)
998032ba 6074 rtx reg;
6075 rtx mem;
6076{
998032ba 6077 /* Punt if we are here by mistake. */
6078 if (! reload_completed)
8703a12c 6079 abort ();
998032ba 6080
6081 /* We must have an offsettable memory reference. */
6082 if (! offsettable_memref_p (mem))
6083 return 0;
6084
6085 /* If we have legitimate args for ldd/std, we do not want
6086 the split to happen. */
6087 if ((REGNO (reg) % 2) == 0
6088 && mem_min_alignment (mem, 8))
6089 return 0;
6090
6091 /* Success. */
6092 return 1;
6093}
6094
9ef15f91 6095/* Return 1 if x and y are some kind of REG and they refer to
6096 different hard registers. This test is guarenteed to be
6097 run after reload. */
6098
6099int
6100sparc_absnegfloat_split_legitimate (x, y)
6101 rtx x, y;
6102{
9ef15f91 6103 if (GET_CODE (x) != REG)
6104 return 0;
9ef15f91 6105 if (GET_CODE (y) != REG)
6106 return 0;
6107 if (REGNO (x) == REGNO (y))
6108 return 0;
6109 return 1;
6110}
6111
94e3b728 6112/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6113 This makes them candidates for using ldd and std insns.
6114
f618d313 6115 Note reg1 and reg2 *must* be hard registers. */
94e3b728 6116
6117int
927ae8b5 6118registers_ok_for_ldd_peep (reg1, reg2)
94e3b728 6119 rtx reg1, reg2;
6120{
94e3b728 6121 /* We might have been passed a SUBREG. */
6122 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6123 return 0;
6124
94e3b728 6125 if (REGNO (reg1) % 2 != 0)
6126 return 0;
6127
f618d313 6128 /* Integer ldd is deprecated in SPARC V9 */
6129 if (TARGET_V9 && REGNO (reg1) < 32)
6130 return 0;
6131
94e3b728 6132 return (REGNO (reg1) == REGNO (reg2) - 1);
94e3b728 6133}
6134
55d52cfe 6135/* Return 1 if the addresses in mem1 and mem2 are suitable for use in
b409d1e2 6136 an ldd or std insn.
6137
55d52cfe 6138 This can only happen when addr1 and addr2, the addresses in mem1
6139 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
b409d1e2 6140 addr1 must also be aligned on a 64-bit boundary.
6141
6142 Also iff dependent_reg_rtx is not null it should not be used to
6143 compute the address for mem1, i.e. we cannot optimize a sequence
6144 like:
6145 ld [%o0], %o0
6146 ld [%o0 + 4], %o1
6147 to
178bf3fd 6148 ldd [%o0], %o0
a3c7ab5f 6149 nor:
6150 ld [%g3 + 4], %g3
6151 ld [%g3], %g2
6152 to
6153 ldd [%g3], %g2
6154
6155 But, note that the transformation from:
6156 ld [%g2 + 4], %g3
6157 ld [%g2], %g2
6158 to
6159 ldd [%g2], %g2
6160 is perfectly fine. Thus, the peephole2 patterns always pass us
6161 the destination register of the first load, never the second one.
6162
b409d1e2 6163 For stores we don't have a similar problem, so dependent_reg_rtx is
6164 NULL_RTX. */
94e3b728 6165
6166int
b409d1e2 6167mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx)
6168 rtx mem1, mem2, dependent_reg_rtx;
94e3b728 6169{
55d52cfe 6170 rtx addr1, addr2;
0a544228 6171 unsigned int reg1;
6172 int offset1;
94e3b728 6173
b409d1e2 6174 /* The mems cannot be volatile. */
6175 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6176 return 0;
55d52cfe 6177
b409d1e2 6178 /* MEM1 should be aligned on a 64-bit boundary. */
55d52cfe 6179 if (MEM_ALIGN (mem1) < 64)
6180 return 0;
6181
b409d1e2 6182 addr1 = XEXP (mem1, 0);
6183 addr2 = XEXP (mem2, 0);
6184
94e3b728 6185 /* Extract a register number and offset (if used) from the first addr. */
6186 if (GET_CODE (addr1) == PLUS)
6187 {
6188 /* If not a REG, return zero. */
6189 if (GET_CODE (XEXP (addr1, 0)) != REG)
6190 return 0;
6191 else
6192 {
6193 reg1 = REGNO (XEXP (addr1, 0));
6194 /* The offset must be constant! */
6195 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6196 return 0;
6197 offset1 = INTVAL (XEXP (addr1, 1));
6198 }
6199 }
6200 else if (GET_CODE (addr1) != REG)
6201 return 0;
6202 else
6203 {
6204 reg1 = REGNO (addr1);
6205 /* This was a simple (mem (reg)) expression. Offset is 0. */
6206 offset1 = 0;
6207 }
6208
6209 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6210 if (GET_CODE (addr2) != PLUS)
6211 return 0;
6212
6213 if (GET_CODE (XEXP (addr2, 0)) != REG
6214 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6215 return 0;
6216
94e3b728 6217 if (reg1 != REGNO (XEXP (addr2, 0)))
6218 return 0;
6219
b409d1e2 6220 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6221 return 0;
6222
c5f6f35e 6223 /* The first offset must be evenly divisible by 8 to ensure the
94e3b728 6224 address is 64 bit aligned. */
6225 if (offset1 % 8 != 0)
6226 return 0;
6227
6228 /* The offset for the second addr must be 4 more than the first addr. */
6229 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6230 return 0;
6231
6232 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6233 instructions. */
6234 return 1;
6235}
927ae8b5 6236
6237/* Return 1 if reg is a pseudo, or is the first register in
6238 a hard register pair. This makes it a candidate for use in
6239 ldd and std insns. */
6240
6241int
6242register_ok_for_ldd (reg)
6243 rtx reg;
6244{
927ae8b5 6245 /* We might have been passed a SUBREG. */
6246 if (GET_CODE (reg) != REG)
6247 return 0;
6248
6249 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6250 return (REGNO (reg) % 2 == 0);
6251 else
6252 return 1;
927ae8b5 6253}
823baf68 6254\f
823baf68 6255/* Print operand X (an rtx) in assembler syntax to file FILE.
6256 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6257 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6258
6259void
6260print_operand (file, x, code)
6261 FILE *file;
6262 rtx x;
6263 int code;
6264{
6265 switch (code)
6266 {
6267 case '#':
6268 /* Output a 'nop' if there's nothing for the delay slot. */
6269 if (dbr_sequence_length () == 0)
998032ba 6270 fputs ("\n\t nop", file);
823baf68 6271 return;
6272 case '*':
1891c3cd 6273 /* Output an annul flag if there's nothing for the delay slot and we
6274 are optimizing. This is always used with '(' below. */
6275 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6276 this is a dbx bug. So, we only do this when optimizing. */
f618d313 6277 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6278 Always emit a nop in case the next instruction is a branch. */
6279 if (dbr_sequence_length () == 0
367242d3 6280 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
1891c3cd 6281 fputs (",a", file);
6282 return;
6283 case '(':
6284 /* Output a 'nop' if there's nothing for the delay slot and we are
6285 not optimizing. This is always used with '*' above. */
f618d313 6286 if (dbr_sequence_length () == 0
367242d3 6287 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
998032ba 6288 fputs ("\n\t nop", file);
823baf68 6289 return;
6dac3578 6290 case '_':
adf09a2f 6291 /* Output the Embedded Medium/Anywhere code model base register. */
6292 fputs (EMBMEDANY_BASE_REG, file);
6dac3578 6293 return;
6294 case '@':
6295 /* Print out what we are using as the frame pointer. This might
6296 be %fp, or might be %sp+offset. */
6297 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6298 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
6299 return;
823baf68 6300 case 'Y':
6301 /* Adjust the operand to take into account a RESTORE operation. */
f618d313 6302 if (GET_CODE (x) == CONST_INT)
6303 break;
6304 else if (GET_CODE (x) != REG)
68435912 6305 output_operand_lossage ("invalid %%Y operand");
b3002924 6306 else if (REGNO (x) < 8)
823baf68 6307 fputs (reg_names[REGNO (x)], file);
6308 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6309 fputs (reg_names[REGNO (x)-16], file);
6310 else
68435912 6311 output_operand_lossage ("invalid %%Y operand");
823baf68 6312 return;
bccf482a 6313 case 'L':
6314 /* Print out the low order register name of a register pair. */
6315 if (WORDS_BIG_ENDIAN)
6316 fputs (reg_names[REGNO (x)+1], file);
6317 else
6318 fputs (reg_names[REGNO (x)], file);
6319 return;
6320 case 'H':
6321 /* Print out the high order register name of a register pair. */
6322 if (WORDS_BIG_ENDIAN)
6323 fputs (reg_names[REGNO (x)], file);
6324 else
6325 fputs (reg_names[REGNO (x)+1], file);
6326 return;
823baf68 6327 case 'R':
93fed860 6328 /* Print out the second register name of a register pair or quad.
823baf68 6329 I.e., R (%o0) => %o1. */
6330 fputs (reg_names[REGNO (x)+1], file);
6331 return;
93fed860 6332 case 'S':
6333 /* Print out the third register name of a register quad.
6334 I.e., S (%o0) => %o2. */
6335 fputs (reg_names[REGNO (x)+2], file);
6336 return;
6337 case 'T':
6338 /* Print out the fourth register name of a register quad.
6339 I.e., T (%o0) => %o3. */
6340 fputs (reg_names[REGNO (x)+3], file);
6341 return;
c74468c0 6342 case 'x':
6343 /* Print a condition code register. */
6344 if (REGNO (x) == SPARC_ICC_REG)
6345 {
6346 /* We don't handle CC[X]_NOOVmode because they're not supposed
6347 to occur here. */
6348 if (GET_MODE (x) == CCmode)
6349 fputs ("%icc", file);
6350 else if (GET_MODE (x) == CCXmode)
6351 fputs ("%xcc", file);
6352 else
6353 abort ();
6354 }
6355 else
6356 /* %fccN register */
6357 fputs (reg_names[REGNO (x)], file);
6358 return;
823baf68 6359 case 'm':
6360 /* Print the operand's address only. */
6361 output_address (XEXP (x, 0));
6362 return;
6363 case 'r':
6364 /* In this case we need a register. Use %g0 if the
7466c783 6365 operand is const0_rtx. */
cbd236ca 6366 if (x == const0_rtx
6367 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
823baf68 6368 {
6369 fputs ("%g0", file);
6370 return;
6371 }
6372 else
6373 break;
6374
6dac3578 6375 case 'A':
823baf68 6376 switch (GET_CODE (x))
6377 {
6378 case IOR: fputs ("or", file); break;
6379 case AND: fputs ("and", file); break;
6380 case XOR: fputs ("xor", file); break;
68435912 6381 default: output_operand_lossage ("invalid %%A operand");
823baf68 6382 }
6383 return;
6384
6385 case 'B':
6386 switch (GET_CODE (x))
6387 {
6388 case IOR: fputs ("orn", file); break;
6389 case AND: fputs ("andn", file); break;
6390 case XOR: fputs ("xnor", file); break;
68435912 6391 default: output_operand_lossage ("invalid %%B operand");
823baf68 6392 }
6393 return;
6394
c74468c0 6395 /* These are used by the conditional move instructions. */
6396 case 'c' :
6dac3578 6397 case 'C':
c74468c0 6398 {
b59496fa 6399 enum rtx_code rc = GET_CODE (x);
6400
6401 if (code == 'c')
6402 {
6403 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6404 if (mode == CCFPmode || mode == CCFPEmode)
6405 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6406 else
6407 rc = reverse_condition (GET_CODE (x));
6408 }
c74468c0 6409 switch (rc)
6410 {
6411 case NE: fputs ("ne", file); break;
6412 case EQ: fputs ("e", file); break;
6413 case GE: fputs ("ge", file); break;
6414 case GT: fputs ("g", file); break;
6415 case LE: fputs ("le", file); break;
6416 case LT: fputs ("l", file); break;
6417 case GEU: fputs ("geu", file); break;
6418 case GTU: fputs ("gu", file); break;
6419 case LEU: fputs ("leu", file); break;
6420 case LTU: fputs ("lu", file); break;
b59496fa 6421 case LTGT: fputs ("lg", file); break;
6422 case UNORDERED: fputs ("u", file); break;
6423 case ORDERED: fputs ("o", file); break;
6424 case UNLT: fputs ("ul", file); break;
6425 case UNLE: fputs ("ule", file); break;
6426 case UNGT: fputs ("ug", file); break;
6427 case UNGE: fputs ("uge", file); break;
6428 case UNEQ: fputs ("ue", file); break;
c74468c0 6429 default: output_operand_lossage (code == 'c'
68435912 6430 ? "invalid %%c operand"
6431 : "invalid %%C operand");
c74468c0 6432 }
6433 return;
6434 }
6435
6436 /* These are used by the movr instruction pattern. */
6437 case 'd':
6dac3578 6438 case 'D':
c74468c0 6439 {
6440 enum rtx_code rc = (code == 'd'
6441 ? reverse_condition (GET_CODE (x))
6442 : GET_CODE (x));
6443 switch (rc)
6444 {
6445 case NE: fputs ("ne", file); break;
6446 case EQ: fputs ("e", file); break;
6447 case GE: fputs ("gez", file); break;
6448 case LT: fputs ("lz", file); break;
6449 case LE: fputs ("lez", file); break;
6450 case GT: fputs ("gz", file); break;
6451 default: output_operand_lossage (code == 'd'
68435912 6452 ? "invalid %%d operand"
6453 : "invalid %%D operand");
c74468c0 6454 }
6455 return;
6456 }
6dac3578 6457
823baf68 6458 case 'b':
6459 {
6460 /* Print a sign-extended character. */
fb124916 6461 int i = trunc_int_for_mode (INTVAL (x), QImode);
823baf68 6462 fprintf (file, "%d", i);
6463 return;
6464 }
6465
f35e3636 6466 case 'f':
6467 /* Operand must be a MEM; write its address. */
6468 if (GET_CODE (x) != MEM)
68435912 6469 output_operand_lossage ("invalid %%f operand");
f35e3636 6470 output_address (XEXP (x, 0));
6471 return;
6472
823baf68 6473 case 0:
6474 /* Do nothing special. */
6475 break;
6476
6477 default:
6478 /* Undocumented flag. */
e3cf6f20 6479 output_operand_lossage ("invalid operand output code");
823baf68 6480 }
6481
6482 if (GET_CODE (x) == REG)
6483 fputs (reg_names[REGNO (x)], file);
6484 else if (GET_CODE (x) == MEM)
6485 {
6486 fputc ('[', file);
823baf68 6487 /* Poor Sun assembler doesn't understand absolute addressing. */
f8be3dfc 6488 if (CONSTANT_P (XEXP (x, 0)))
823baf68 6489 fputs ("%g0+", file);
6490 output_address (XEXP (x, 0));
6491 fputc (']', file);
6492 }
6493 else if (GET_CODE (x) == HIGH)
6494 {
6495 fputs ("%hi(", file);
6496 output_addr_const (file, XEXP (x, 0));
6497 fputc (')', file);
6498 }
6499 else if (GET_CODE (x) == LO_SUM)
6500 {
6501 print_operand (file, XEXP (x, 0), 0);
998032ba 6502 if (TARGET_CM_MEDMID)
6503 fputs ("+%l44(", file);
6504 else
6505 fputs ("+%lo(", file);
823baf68 6506 output_addr_const (file, XEXP (x, 1));
6507 fputc (')', file);
6508 }
1801226e 6509 else if (GET_CODE (x) == CONST_DOUBLE
6510 && (GET_MODE (x) == VOIDmode
6511 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
823baf68 6512 {
6513 if (CONST_DOUBLE_HIGH (x) == 0)
f27284b4 6514 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
823baf68 6515 else if (CONST_DOUBLE_HIGH (x) == -1
6516 && CONST_DOUBLE_LOW (x) < 0)
f27284b4 6517 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
823baf68 6518 else
1801226e 6519 output_operand_lossage ("long long constant not a valid immediate operand");
823baf68 6520 }
1801226e 6521 else if (GET_CODE (x) == CONST_DOUBLE)
6522 output_operand_lossage ("floating point constant not a valid immediate operand");
823baf68 6523 else { output_addr_const (file, x); }
6524}
6525\f
58356836 6526/* Target hook for assembling integer objects. The sparc version has
6527 special handling for aligned DI-mode objects. */
823baf68 6528
58356836 6529static bool
6530sparc_assemble_integer (x, size, aligned_p)
6531 rtx x;
6532 unsigned int size;
6533 int aligned_p;
823baf68 6534{
58356836 6535 /* ??? We only output .xword's for symbols and only then in environments
6536 where the assembler can handle them. */
6537 if (aligned_p && size == 8
6538 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
823baf68 6539 {
58356836 6540 if (TARGET_V9)
6dac3578 6541 {
58356836 6542 assemble_integer_with_op ("\t.xword\t", x);
6543 return true;
6dac3578 6544 }
6545 else
6546 {
58356836 6547 assemble_aligned_integer (4, const0_rtx);
6548 assemble_aligned_integer (4, x);
6549 return true;
6dac3578 6550 }
823baf68 6551 }
58356836 6552 return default_assemble_integer (x, size, aligned_p);
823baf68 6553}
0f6f82ff 6554\f
94f6af1e 6555/* Return the value of a code used in the .proc pseudo-op that says
6556 what kind of result this function returns. For non-C types, we pick
6557 the closest C type. */
6558
7466c783 6559#ifndef SHORT_TYPE_SIZE
6560#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6561#endif
6562
6563#ifndef INT_TYPE_SIZE
6564#define INT_TYPE_SIZE BITS_PER_WORD
6565#endif
6566
6567#ifndef LONG_TYPE_SIZE
6568#define LONG_TYPE_SIZE BITS_PER_WORD
6569#endif
6570
6571#ifndef LONG_LONG_TYPE_SIZE
6572#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6573#endif
6574
6575#ifndef FLOAT_TYPE_SIZE
6576#define FLOAT_TYPE_SIZE BITS_PER_WORD
6577#endif
6578
6579#ifndef DOUBLE_TYPE_SIZE
6580#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6581#endif
6582
6583#ifndef LONG_DOUBLE_TYPE_SIZE
6584#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6585#endif
0f6f82ff 6586
6587unsigned long
6588sparc_type_code (type)
6589 register tree type;
6590{
6591 register unsigned long qualifiers = 0;
997d68fe 6592 register unsigned shift;
0f6f82ff 6593
b090827b 6594 /* Only the first 30 bits of the qualifier are valid. We must refrain from
ba5b7b2a 6595 setting more, since some assemblers will give an error for this. Also,
6596 we must be careful to avoid shifts of 32 bits or more to avoid getting
6597 unpredictable results. */
6598
997d68fe 6599 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
0f6f82ff 6600 {
6601 switch (TREE_CODE (type))
6602 {
6603 case ERROR_MARK:
6604 return qualifiers;
6605
6606 case ARRAY_TYPE:
997d68fe 6607 qualifiers |= (3 << shift);
0f6f82ff 6608 break;
6609
6610 case FUNCTION_TYPE:
6611 case METHOD_TYPE:
997d68fe 6612 qualifiers |= (2 << shift);
0f6f82ff 6613 break;
6614
6615 case POINTER_TYPE:
6616 case REFERENCE_TYPE:
6617 case OFFSET_TYPE:
997d68fe 6618 qualifiers |= (1 << shift);
0f6f82ff 6619 break;
823baf68 6620
0f6f82ff 6621 case RECORD_TYPE:
6622 return (qualifiers | 8);
6623
6624 case UNION_TYPE:
94f6af1e 6625 case QUAL_UNION_TYPE:
0f6f82ff 6626 return (qualifiers | 9);
6627
6628 case ENUMERAL_TYPE:
6629 return (qualifiers | 10);
6630
6631 case VOID_TYPE:
6632 return (qualifiers | 16);
6633
6634 case INTEGER_TYPE:
ce43328f 6635 /* If this is a range type, consider it to be the underlying
6636 type. */
6637 if (TREE_TYPE (type) != 0)
997d68fe 6638 break;
ce43328f 6639
7466c783 6640 /* Carefully distinguish all the standard types of C,
94f6af1e 6641 without messing up if the language is not C. We do this by
6642 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6643 look at both the names and the above fields, but that's redundant.
6644 Any type whose size is between two C types will be considered
6645 to be the wider of the two types. Also, we do not have a
6646 special code to use for "long long", so anything wider than
6647 long is treated the same. Note that we can't distinguish
6648 between "int" and "long" in this code if they are the same
6649 size, but that's fine, since neither can the assembler. */
6650
6651 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
6652 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
7466c783 6653
94f6af1e 6654 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
6655 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
7466c783 6656
94f6af1e 6657 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7466c783 6658 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
6659
94f6af1e 6660 else
7466c783 6661 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
6662
0f6f82ff 6663 case REAL_TYPE:
997d68fe 6664 /* If this is a range type, consider it to be the underlying
6665 type. */
6666 if (TREE_TYPE (type) != 0)
6667 break;
6668
7466c783 6669 /* Carefully distinguish all the standard types of C,
6670 without messing up if the language is not C. */
94f6af1e 6671
7466c783 6672 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
0f6f82ff 6673 return (qualifiers | 6);
94f6af1e 6674
6675 else
6676 return (qualifiers | 7);
0f6f82ff 6677
6678 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
064d9c8f 6679 /* ??? We need to distinguish between double and float complex types,
5e76b7bd 6680 but I don't know how yet because I can't reach this code from
6681 existing front-ends. */
6682 return (qualifiers | 7); /* Who knows? */
6683
0f6f82ff 6684 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
6685 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
6686 case FILE_TYPE: /* GNU Pascal FILE type. */
63f04736 6687 case SET_TYPE: /* GNU Pascal SET type. */
0f6f82ff 6688 case LANG_TYPE: /* ? */
63f04736 6689 return qualifiers;
0f6f82ff 6690
6691 default:
6692 abort (); /* Not a type! */
6693 }
6694 }
997d68fe 6695
6696 return qualifiers;
0f6f82ff 6697}
835348d6 6698\f
6dac3578 6699/* Nested function support. */
6700
6701/* Emit RTL insns to initialize the variable parts of a trampoline.
6702 FNADDR is an RTX for the address of the function's pure code.
6703 CXT is an RTX for the static chain value for the function.
6704
6705 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6706 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6707 (to store insns). This is a bit excessive. Perhaps a different
6708 mechanism would be better here.
6709
d466251f 6710 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6dac3578 6711
6712void
6713sparc_initialize_trampoline (tramp, fnaddr, cxt)
6714 rtx tramp, fnaddr, cxt;
6715{
58dc6b1f 6716 /* SPARC 32 bit trampoline:
6717
998032ba 6718 sethi %hi(fn), %g1
6719 sethi %hi(static), %g2
6720 jmp %g1+%lo(fn)
6721 or %g2, %lo(static), %g2
58dc6b1f 6722
6723 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6724 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6725 */
75591caa 6726#ifdef TRANSFER_FROM_TRAMPOLINE
6727 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
61f83895 6728 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
75591caa 6729#endif
58dc6b1f 6730
a262ec1f 6731 emit_move_insn
6732 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
6733 expand_binop (SImode, ior_optab,
6734 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
6735 size_int (10), 0, 1),
6736 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
6737 NULL_RTX, 1, OPTAB_DIRECT));
6738
6739 emit_move_insn
6740 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6741 expand_binop (SImode, ior_optab,
6742 expand_shift (RSHIFT_EXPR, SImode, cxt,
6743 size_int (10), 0, 1),
6744 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
6745 NULL_RTX, 1, OPTAB_DIRECT));
6746
6747 emit_move_insn
6748 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6749 expand_binop (SImode, ior_optab,
6750 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
6751 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
6752 NULL_RTX, 1, OPTAB_DIRECT));
6753
6754 emit_move_insn
6755 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6756 expand_binop (SImode, ior_optab,
6757 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
6758 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
6759 NULL_RTX, 1, OPTAB_DIRECT));
58dc6b1f 6760
58dc6b1f 6761 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6762 aligned on a 16 byte boundary so one flush clears it all. */
a262ec1f 6763 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
55ebdd65 6764 if (sparc_cpu != PROCESSOR_ULTRASPARC
6765 && sparc_cpu != PROCESSOR_ULTRASPARC3)
58dc6b1f 6766 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
6767 plus_constant (tramp, 8)))));
6dac3578 6768}
6769
d466251f 6770/* The 64 bit version is simpler because it makes more sense to load the
6771 values as "immediate" data out of the trampoline. It's also easier since
6772 we can read the PC without clobbering a register. */
6773
6dac3578 6774void
6775sparc64_initialize_trampoline (tramp, fnaddr, cxt)
6776 rtx tramp, fnaddr, cxt;
6777{
447b4bf2 6778#ifdef TRANSFER_FROM_TRAMPOLINE
6779 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
61f83895 6780 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
447b4bf2 6781#endif
6782
58dc6b1f 6783 /*
998032ba 6784 rd %pc, %g1
6785 ldx [%g1+24], %g5
6786 jmp %g5
6787 ldx [%g1+16], %g5
58dc6b1f 6788 +16 bytes data
6789 */
6790
6791 emit_move_insn (gen_rtx_MEM (SImode, tramp),
d5819eb8 6792 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
58dc6b1f 6793 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
d5819eb8 6794 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
58dc6b1f 6795 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
d5819eb8 6796 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
58dc6b1f 6797 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
d5819eb8 6798 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
58dc6b1f 6799 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
447b4bf2 6800 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
25e379ea 6801 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
447b4bf2 6802
bea4bad2 6803 if (sparc_cpu != PROCESSOR_ULTRASPARC
6804 && sparc_cpu != PROCESSOR_ULTRASPARC3)
25e379ea 6805 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
6dac3578 6806}
6807\f
7f6c1d27 6808/* Subroutines to support a flat (single) register window calling
6809 convention. */
6810
6811/* Single-register window sparc stack frames look like:
6812
6813 Before call After call
6814 +-----------------------+ +-----------------------+
5c648c1a 6815 high | | | |
6816 mem | caller's temps. | | caller's temps. |
7f6c1d27 6817 | | | |
6818 +-----------------------+ +-----------------------+
6819 | | | |
6820 | arguments on stack. | | arguments on stack. |
5c648c1a 6821 | | | |
6822 +-----------------------+FP+92->+-----------------------+
7f6c1d27 6823 | 6 words to save | | 6 words to save |
6824 | arguments passed | | arguments passed |
6825 | in registers, even | | in registers, even |
5c648c1a 6826 | if not passed. | | if not passed. |
6827 SP+68->+-----------------------+FP+68->+-----------------------+
6828 | 1 word struct addr | | 1 word struct addr |
6829 +-----------------------+FP+64->+-----------------------+
6830 | | | |
6831 | 16 word reg save area | | 16 word reg save area |
6832 | | | |
6833 SP->+-----------------------+ FP->+-----------------------+
6834 | 4 word area for |
6835 | fp/alu reg moves |
6836 FP-16->+-----------------------+
6837 | |
6838 | local variables |
6839 | |
6840 +-----------------------+
6841 | |
7f6c1d27 6842 | fp register save |
5c648c1a 6843 | |
6844 +-----------------------+
6845 | |
7f6c1d27 6846 | gp register save |
6847 | |
5c648c1a 6848 +-----------------------+
6849 | |
7f6c1d27 6850 | alloca allocations |
5c648c1a 6851 | |
6852 +-----------------------+
6853 | |
7f6c1d27 6854 | arguments on stack |
5c648c1a 6855 | |
6856 SP+92->+-----------------------+
7f6c1d27 6857 | 6 words to save |
5c648c1a 6858 | arguments passed |
7f6c1d27 6859 | in registers, even |
5c648c1a 6860 low | if not passed. |
6861 memory SP+68->+-----------------------+
6862 | 1 word struct addr |
6863 SP+64->+-----------------------+
6864 | |
6865 I 16 word reg save area |
6866 | |
6867 SP->+-----------------------+ */
7f6c1d27 6868
7775000f 6869/* Structure to be filled in by sparc_flat_compute_frame_size with register
7f6c1d27 6870 save masks, and offsets for the current function. */
6871
6872struct sparc_frame_info
6873{
6874 unsigned long total_size; /* # bytes that the entire frame takes up. */
6875 unsigned long var_size; /* # bytes that variables take up. */
6876 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6877 unsigned long extra_size; /* # bytes of extra gunk. */
6878 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6879 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5c648c1a 6880 unsigned long gmask; /* Mask of saved gp registers. */
7f6c1d27 6881 unsigned long fmask; /* Mask of saved fp registers. */
5c648c1a 6882 unsigned long reg_offset; /* Offset from new sp to store regs. */
7f6c1d27 6883 int initialized; /* Nonzero if frame size already calculated. */
6884};
6885
7775000f 6886/* Current frame information calculated by sparc_flat_compute_frame_size. */
7f6c1d27 6887struct sparc_frame_info current_frame_info;
6888
6889/* Zero structure to initialize current_frame_info. */
6890struct sparc_frame_info zero_frame_info;
6891
6892/* Tell prologue and epilogue if register REGNO should be saved / restored. */
6893
5c648c1a 6894#define RETURN_ADDR_REGNUM 15
04a917bf 6895#define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
5c648c1a 6896#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6897
7f6c1d27 6898#define MUST_SAVE_REGISTER(regno) \
04a917bf 6899 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6900 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
5c648c1a 6901 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
7f6c1d27 6902
6903/* Return the bytes needed to compute the frame pointer from the current
6904 stack pointer. */
6905
6906unsigned long
7775000f 6907sparc_flat_compute_frame_size (size)
7f6c1d27 6908 int size; /* # of var. bytes allocated. */
6909{
6910 int regno;
6911 unsigned long total_size; /* # bytes that the entire frame takes up. */
6912 unsigned long var_size; /* # bytes that variables take up. */
6913 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6914 unsigned long extra_size; /* # extra bytes. */
6915 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6916 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5c648c1a 6917 unsigned long gmask; /* Mask of saved gp registers. */
7f6c1d27 6918 unsigned long fmask; /* Mask of saved fp registers. */
5c648c1a 6919 unsigned long reg_offset; /* Offset to register save area. */
6920 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
7f6c1d27 6921
6922 /* This is the size of the 16 word reg save area, 1 word struct addr
6923 area, and 4 word fp/alu register copy area. */
73fffacd 6924 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
6925 var_size = size;
6926 gp_reg_size = 0;
6927 fp_reg_size = 0;
6928 gmask = 0;
6929 fmask = 0;
6930 reg_offset = 0;
5c648c1a 6931 need_aligned_p = 0;
7f6c1d27 6932
73fffacd 6933 args_size = 0;
6934 if (!leaf_function_p ())
6935 {
6936 /* Also include the size needed for the 6 parameter registers. */
6937 args_size = current_function_outgoing_args_size + 24;
6938 }
6939 total_size = var_size + args_size;
6940
7f6c1d27 6941 /* Calculate space needed for gp registers. */
6942 for (regno = 1; regno <= 31; regno++)
6943 {
6944 if (MUST_SAVE_REGISTER (regno))
6945 {
5c648c1a 6946 /* If we need to save two regs in a row, ensure there's room to bump
6947 up the address to align it to a doubleword boundary. */
7f6c1d27 6948 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
6949 {
6950 if (gp_reg_size % 8 != 0)
5c648c1a 6951 gp_reg_size += 4;
7f6c1d27 6952 gp_reg_size += 2 * UNITS_PER_WORD;
5c648c1a 6953 gmask |= 3 << regno;
7f6c1d27 6954 regno++;
5c648c1a 6955 need_aligned_p = 1;
7f6c1d27 6956 }
6957 else
6958 {
6959 gp_reg_size += UNITS_PER_WORD;
5c648c1a 6960 gmask |= 1 << regno;
7f6c1d27 6961 }
6962 }
6963 }
7f6c1d27 6964
6965 /* Calculate space needed for fp registers. */
6966 for (regno = 32; regno <= 63; regno++)
6967 {
6968 if (regs_ever_live[regno] && !call_used_regs[regno])
6969 {
6970 fp_reg_size += UNITS_PER_WORD;
6971 fmask |= 1 << (regno - 32);
6972 }
6973 }
6974
5c648c1a 6975 if (gmask || fmask)
6976 {
6977 int n;
6978 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
6979 /* Ensure save area is 8 byte aligned if we need it. */
6980 n = reg_offset % 8;
6981 if (need_aligned_p && n != 0)
6982 {
6983 total_size += 8 - n;
6984 reg_offset += 8 - n;
6985 }
6986 total_size += gp_reg_size + fp_reg_size;
6987 }
7f6c1d27 6988
73fffacd 6989 /* If we must allocate a stack frame at all, we must also allocate
6990 room for register window spillage, so as to be binary compatible
6991 with libraries and operating systems that do not use -mflat. */
6992 if (total_size > 0)
6993 total_size += extra_size;
6994 else
6995 extra_size = 0;
7f6c1d27 6996
6997 total_size = SPARC_STACK_ALIGN (total_size);
6998
6999 /* Save other computed information. */
7000 current_frame_info.total_size = total_size;
7001 current_frame_info.var_size = var_size;
7002 current_frame_info.args_size = args_size;
7003 current_frame_info.extra_size = extra_size;
7004 current_frame_info.gp_reg_size = gp_reg_size;
7005 current_frame_info.fp_reg_size = fp_reg_size;
5c648c1a 7006 current_frame_info.gmask = gmask;
7f6c1d27 7007 current_frame_info.fmask = fmask;
5c648c1a 7008 current_frame_info.reg_offset = reg_offset;
7f6c1d27 7009 current_frame_info.initialized = reload_completed;
7010
7f6c1d27 7011 /* Ok, we're done. */
7012 return total_size;
7013}
7014\f
5c648c1a 7015/* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7016 OFFSET.
7017
7018 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7019 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7020 [BASE_REG+OFFSET] will always be a valid address.
7021
7022 WORD_OP is either "st" for save, "ld" for restore.
7023 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7f6c1d27 7024
7025void
f164689f 7026sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
7027 doubleword_op, base_offset)
5c648c1a 7028 FILE *file;
075136a2 7029 const char *base_reg;
5c648c1a 7030 unsigned int offset;
7031 unsigned long gmask;
7032 unsigned long fmask;
075136a2 7033 const char *word_op;
7034 const char *doubleword_op;
4ad3f9b3 7035 unsigned long base_offset;
7f6c1d27 7036{
7037 int regno;
7f6c1d27 7038
5c648c1a 7039 if (gmask == 0 && fmask == 0)
7040 return;
7f6c1d27 7041
5c648c1a 7042 /* Save registers starting from high to low. We've already saved the
7043 previous frame pointer and previous return address for the debugger's
7044 sake. The debugger allows us to not need a nop in the epilog if at least
7045 one register is reloaded in addition to return address. */
7f6c1d27 7046
5c648c1a 7047 if (gmask)
7f6c1d27 7048 {
7049 for (regno = 1; regno <= 31; regno++)
7050 {
5c648c1a 7051 if ((gmask & (1L << regno)) != 0)
7f6c1d27 7052 {
5c648c1a 7053 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7f6c1d27 7054 {
5c648c1a 7055 /* We can save two registers in a row. If we're not at a
7056 double word boundary, move to one.
7057 sparc_flat_compute_frame_size ensures there's room to do
7058 this. */
7059 if (offset % 8 != 0)
7060 offset += UNITS_PER_WORD;
7061
7f6c1d27 7062 if (word_op[0] == 's')
4ad3f9b3 7063 {
998032ba 7064 fprintf (file, "\t%s\t%s, [%s+%d]\n",
4ad3f9b3 7065 doubleword_op, reg_names[regno],
7066 base_reg, offset);
d757b8c9 7067 if (dwarf2out_do_frame ())
4ad3f9b3 7068 {
f164689f 7069 char *l = dwarf2out_cfi_label ();
4ad3f9b3 7070 dwarf2out_reg_save (l, regno, offset + base_offset);
7071 dwarf2out_reg_save
7072 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7073 }
4ad3f9b3 7074 }
7f6c1d27 7075 else
998032ba 7076 fprintf (file, "\t%s\t[%s+%d], %s\n",
5c648c1a 7077 doubleword_op, base_reg, offset,
7f6c1d27 7078 reg_names[regno]);
7079
5c648c1a 7080 offset += 2 * UNITS_PER_WORD;
7f6c1d27 7081 regno++;
7082 }
7083 else
7084 {
7085 if (word_op[0] == 's')
4ad3f9b3 7086 {
998032ba 7087 fprintf (file, "\t%s\t%s, [%s+%d]\n",
4ad3f9b3 7088 word_op, reg_names[regno],
7089 base_reg, offset);
d757b8c9 7090 if (dwarf2out_do_frame ())
4ad3f9b3 7091 dwarf2out_reg_save ("", regno, offset + base_offset);
4ad3f9b3 7092 }
7f6c1d27 7093 else
998032ba 7094 fprintf (file, "\t%s\t[%s+%d], %s\n",
5c648c1a 7095 word_op, base_reg, offset, reg_names[regno]);
7f6c1d27 7096
5c648c1a 7097 offset += UNITS_PER_WORD;
7f6c1d27 7098 }
7099 }
7100 }
7101 }
7102
7103 if (fmask)
7104 {
7105 for (regno = 32; regno <= 63; regno++)
7106 {
7107 if ((fmask & (1L << (regno - 32))) != 0)
7108 {
7109 if (word_op[0] == 's')
4ad3f9b3 7110 {
998032ba 7111 fprintf (file, "\t%s\t%s, [%s+%d]\n",
4ad3f9b3 7112 word_op, reg_names[regno],
7113 base_reg, offset);
d757b8c9 7114 if (dwarf2out_do_frame ())
4ad3f9b3 7115 dwarf2out_reg_save ("", regno, offset + base_offset);
4ad3f9b3 7116 }
7f6c1d27 7117 else
998032ba 7118 fprintf (file, "\t%s\t[%s+%d], %s\n",
5c648c1a 7119 word_op, base_reg, offset, reg_names[regno]);
7f6c1d27 7120
5c648c1a 7121 offset += UNITS_PER_WORD;
7f6c1d27 7122 }
7123 }
7124 }
7125}
7126\f
7127/* Set up the stack and frame (if desired) for the function. */
7128
17d9b0c3 7129static void
7130sparc_flat_function_prologue (file, size)
7f6c1d27 7131 FILE *file;
17d9b0c3 7132 HOST_WIDE_INT size;
7f6c1d27 7133{
08c762a3 7134 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
5c648c1a 7135 unsigned long gmask = current_frame_info.gmask;
f7437517 7136
d300bd48 7137 sparc_output_scratch_registers (file);
7138
7775000f 7139 /* This is only for the human reader. */
77d3d2a4 7140 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
07e64d6e 7141 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
77d3d2a4 7142 ASM_COMMENT_START,
5c648c1a 7143 current_frame_info.var_size,
7144 current_frame_info.gp_reg_size / 4,
9bf86052 7145 current_frame_info.fp_reg_size / 4,
5c648c1a 7146 current_function_outgoing_args_size,
7147 current_frame_info.extra_size);
7f6c1d27 7148
7149 size = SPARC_STACK_ALIGN (size);
5c648c1a 7150 size = (! current_frame_info.initialized
7151 ? sparc_flat_compute_frame_size (size)
7152 : current_frame_info.total_size);
7f6c1d27 7153
5c648c1a 7154 /* These cases shouldn't happen. Catch them now. */
7155 if (size == 0 && (gmask || current_frame_info.fmask))
7156 abort ();
7f6c1d27 7157
5c648c1a 7158 /* Allocate our stack frame by decrementing %sp.
7159 At present, the only algorithm gdb can use to determine if this is a
7160 flat frame is if we always set %i7 if we set %sp. This can be optimized
7161 in the future by putting in some sort of debugging information that says
7162 this is a `flat' function. However, there is still the case of debugging
7163 code without such debugging information (including cases where most fns
7164 have such info, but there is one that doesn't). So, always do this now
7165 so we don't get a lot of code out there that gdb can't handle.
7166 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7167 distinguish us from a non-flat function but there won't (and shouldn't)
7168 be any differences anyway. The return pc is saved (if necessary) right
7169 after %i7 so gdb won't have to look too far to find it. */
7170 if (size > 0)
7f6c1d27 7171 {
5c648c1a 7172 unsigned int reg_offset = current_frame_info.reg_offset;
04a917bf 7173 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
0d95286f 7174 static const char *const t1_str = "%g1";
5c648c1a 7175
7176 /* Things get a little tricky if local variables take up more than ~4096
7177 bytes and outgoing arguments take up more than ~4096 bytes. When that
7178 happens, the register save area can't be accessed from either end of
7179 the frame. Handle this by decrementing %sp to the start of the gp
7180 register save area, save the regs, update %i7, and then set %sp to its
7181 final value. Given that we only have one scratch register to play
7182 with it is the cheapest solution, and it helps gdb out as it won't
7183 slow down recognition of flat functions.
7184 Don't change the order of insns emitted here without checking with
7185 the gdb folk first. */
7186
01cc3b75 7187 /* Is the entire register save area offsettable from %sp? */
779433ea 7188 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
5c648c1a 7189 {
7190 if (size <= 4096)
7191 {
998032ba 7192 fprintf (file, "\tadd\t%s, %d, %s\n",
0a544228 7193 sp_str, (int) -size, sp_str);
04a917bf 7194 if (gmask & HARD_FRAME_POINTER_MASK)
5c648c1a 7195 {
998032ba 7196 fprintf (file, "\tst\t%s, [%s+%d]\n",
5c648c1a 7197 fp_str, sp_str, reg_offset);
998032ba 7198 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
0a544228 7199 sp_str, (int) -size, fp_str, ASM_COMMENT_START);
5c648c1a 7200 reg_offset += 4;
7201 }
7202 }
7203 else
7204 {
0a544228 7205 fprintf (file, "\tset\t");
7206 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7207 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7208 t1_str, sp_str, t1_str, sp_str);
04a917bf 7209 if (gmask & HARD_FRAME_POINTER_MASK)
5c648c1a 7210 {
998032ba 7211 fprintf (file, "\tst\t%s, [%s+%d]\n",
5c648c1a 7212 fp_str, sp_str, reg_offset);
998032ba 7213 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
77d3d2a4 7214 sp_str, t1_str, fp_str, ASM_COMMENT_START);
5c648c1a 7215 reg_offset += 4;
7216 }
7217 }
d757b8c9 7218 if (dwarf2out_do_frame ())
4ad3f9b3 7219 {
f164689f 7220 char *l = dwarf2out_cfi_label ();
04a917bf 7221 if (gmask & HARD_FRAME_POINTER_MASK)
4ad3f9b3 7222 {
04a917bf 7223 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
4ad3f9b3 7224 reg_offset - 4 - size);
04a917bf 7225 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
4ad3f9b3 7226 }
7227 else
7228 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7229 }
5c648c1a 7230 if (gmask & RETURN_ADDR_MASK)
7231 {
998032ba 7232 fprintf (file, "\tst\t%s, [%s+%d]\n",
5c648c1a 7233 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
d757b8c9 7234 if (dwarf2out_do_frame ())
4ad3f9b3 7235 dwarf2out_return_save ("", reg_offset - size);
5c648c1a 7236 reg_offset += 4;
7237 }
7238 sparc_flat_save_restore (file, sp_str, reg_offset,
04a917bf 7239 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5c648c1a 7240 current_frame_info.fmask,
32612dd3 7241 "st", "std", -size);
5c648c1a 7242 }
7f6c1d27 7243 else
5c648c1a 7244 {
7245 /* Subtract %sp in two steps, but make sure there is always a
7246 64 byte register save area, and %sp is properly aligned. */
7247 /* Amount to decrement %sp by, the first time. */
17d9b0c3 7248 unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
5c648c1a 7249 /* Offset to register save area from %sp. */
17d9b0c3 7250 unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset);
5c648c1a 7251
7252 if (size1 <= 4096)
7253 {
998032ba 7254 fprintf (file, "\tadd\t%s, %d, %s\n",
0a544228 7255 sp_str, (int) -size1, sp_str);
04a917bf 7256 if (gmask & HARD_FRAME_POINTER_MASK)
5c648c1a 7257 {
998032ba 7258 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
0a544228 7259 fp_str, sp_str, (int) offset, sp_str, (int) -size1,
7260 fp_str, ASM_COMMENT_START);
5c648c1a 7261 offset += 4;
7262 }
7263 }
7264 else
7265 {
0a544228 7266 fprintf (file, "\tset\t");
7267 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1);
7268 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7269 t1_str, sp_str, t1_str, sp_str);
04a917bf 7270 if (gmask & HARD_FRAME_POINTER_MASK)
5c648c1a 7271 {
998032ba 7272 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
0a544228 7273 fp_str, sp_str, (int) offset, sp_str, t1_str,
7274 fp_str, ASM_COMMENT_START);
5c648c1a 7275 offset += 4;
7276 }
7277 }
d757b8c9 7278 if (dwarf2out_do_frame ())
4ad3f9b3 7279 {
f164689f 7280 char *l = dwarf2out_cfi_label ();
04a917bf 7281 if (gmask & HARD_FRAME_POINTER_MASK)
4ad3f9b3 7282 {
04a917bf 7283 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
4ad3f9b3 7284 offset - 4 - size1);
04a917bf 7285 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
4ad3f9b3 7286 }
7287 else
7288 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7289 }
5c648c1a 7290 if (gmask & RETURN_ADDR_MASK)
7291 {
998032ba 7292 fprintf (file, "\tst\t%s, [%s+%d]\n",
0a544228 7293 reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset);
d757b8c9 7294 if (dwarf2out_do_frame ())
4ad3f9b3 7295 /* offset - size1 == reg_offset - size
7296 if reg_offset were updated above like offset. */
7297 dwarf2out_return_save ("", offset - size1);
5c648c1a 7298 offset += 4;
7299 }
7300 sparc_flat_save_restore (file, sp_str, offset,
04a917bf 7301 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5c648c1a 7302 current_frame_info.fmask,
32612dd3 7303 "st", "std", -size1);
0a544228 7304 fprintf (file, "\tset\t");
7305 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size - size1);
7306 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7307 t1_str, sp_str, t1_str, sp_str);
d757b8c9 7308 if (dwarf2out_do_frame ())
04a917bf 7309 if (! (gmask & HARD_FRAME_POINTER_MASK))
4ad3f9b3 7310 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
5c648c1a 7311 }
7f6c1d27 7312 }
7775000f 7313
77d3d2a4 7314 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
7f6c1d27 7315}
7316\f
7317/* Do any necessary cleanup after a function to restore stack, frame,
8eba0400 7318 and regs. */
7f6c1d27 7319
17d9b0c3 7320static void
7321sparc_flat_function_epilogue (file, size)
7f6c1d27 7322 FILE *file;
17d9b0c3 7323 HOST_WIDE_INT size;
7f6c1d27 7324{
7f6c1d27 7325 rtx epilogue_delay = current_function_epilogue_delay_list;
7326 int noepilogue = FALSE;
7f6c1d27 7327
7775000f 7328 /* This is only for the human reader. */
77d3d2a4 7329 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
7775000f 7330
7f6c1d27 7331 /* The epilogue does not depend on any registers, but the stack
7332 registers, so we assume that if we have 1 pending nop, it can be
7333 ignored, and 2 it must be filled (2 nops occur for integer
7334 multiply and divide). */
7335
7336 size = SPARC_STACK_ALIGN (size);
5c648c1a 7337 size = (!current_frame_info.initialized
7775000f 7338 ? sparc_flat_compute_frame_size (size)
7f6c1d27 7339 : current_frame_info.total_size);
7340
5c648c1a 7341 if (size == 0 && epilogue_delay == 0)
7f6c1d27 7342 {
7343 rtx insn = get_last_insn ();
7344
7345 /* If the last insn was a BARRIER, we don't have to write any code
7346 because a jump (aka return) was put there. */
7347 if (GET_CODE (insn) == NOTE)
7348 insn = prev_nonnote_insn (insn);
7349 if (insn && GET_CODE (insn) == BARRIER)
7350 noepilogue = TRUE;
7351 }
7352
7353 if (!noepilogue)
7354 {
17d9b0c3 7355 unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset;
7356 unsigned HOST_WIDE_INT size1;
35823b64 7357 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
04a917bf 7358 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
0d95286f 7359 static const char *const t1_str = "%g1";
5c648c1a 7360
7f6c1d27 7361 /* In the reload sequence, we don't need to fill the load delay
7362 slots for most of the loads, also see if we can fill the final
7363 delay slot if not otherwise filled by the reload sequence. */
7364
5c648c1a 7365 if (size > 4095)
0a544228 7366 {
7367 fprintf (file, "\tset\t");
7368 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7369 fprintf (file, ", %s\n", t1_str);
7370 }
7f6c1d27 7371
7372 if (frame_pointer_needed)
7373 {
5c648c1a 7374 if (size > 4095)
998032ba 7375 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
77d3d2a4 7376 fp_str, t1_str, sp_str, ASM_COMMENT_START);
7f6c1d27 7377 else
998032ba 7378 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
0a544228 7379 fp_str, (int) size, sp_str, ASM_COMMENT_START);
7f6c1d27 7380 }
7381
01cc3b75 7382 /* Is the entire register save area offsettable from %sp? */
779433ea 7383 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
5c648c1a 7384 {
7385 size1 = 0;
7386 }
7387 else
7388 {
7389 /* Restore %sp in two steps, but make sure there is always a
7390 64 byte register save area, and %sp is properly aligned. */
7391 /* Amount to increment %sp by, the first time. */
7392 size1 = ((reg_offset - 64 - 16) + 15) & -16;
7393 /* Offset to register save area from %sp. */
7394 reg_offset = size1 - reg_offset;
7395
0a544228 7396 fprintf (file, "\tset\t");
7397 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1);
7398 fprintf (file, ", %s\n\tadd\t%s, %s, %s\n",
7399 t1_str, sp_str, t1_str, sp_str);
5c648c1a 7400 }
7401
7402 /* We must restore the frame pointer and return address reg first
7403 because they are treated specially by the prologue output code. */
04a917bf 7404 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
5c648c1a 7405 {
998032ba 7406 fprintf (file, "\tld\t[%s+%d], %s\n",
0a544228 7407 sp_str, (int) reg_offset, fp_str);
5c648c1a 7408 reg_offset += 4;
7409 }
7410 if (current_frame_info.gmask & RETURN_ADDR_MASK)
7411 {
998032ba 7412 fprintf (file, "\tld\t[%s+%d], %s\n",
0a544228 7413 sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]);
5c648c1a 7414 reg_offset += 4;
7415 }
7416
7417 /* Restore any remaining saved registers. */
7418 sparc_flat_save_restore (file, sp_str, reg_offset,
04a917bf 7419 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5c648c1a 7420 current_frame_info.fmask,
4ad3f9b3 7421 "ld", "ldd", 0);
5c648c1a 7422
7423 /* If we had to increment %sp in two steps, record it so the second
7424 restoration in the epilogue finishes up. */
7425 if (size1 > 0)
7426 {
7427 size -= size1;
7428 if (size > 4095)
0a544228 7429 {
7430 fprintf (file, "\tset\t");
7431 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7432 fprintf (file, ", %s\n", t1_str);
7433 }
5c648c1a 7434 }
7f6c1d27 7435
7f6c1d27 7436 if (current_function_returns_struct)
998032ba 7437 fprintf (file, "\tjmp\t%%o7+12\n");
7f6c1d27 7438 else
7439 fprintf (file, "\tretl\n");
7440
7441 /* If the only register saved is the return address, we need a
7442 nop, unless we have an instruction to put into it. Otherwise
7443 we don't since reloading multiple registers doesn't reference
7444 the register being loaded. */
7445
7446 if (epilogue_delay)
7447 {
5c648c1a 7448 if (size)
7f6c1d27 7449 abort ();
7450 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
7451 }
7452
5c648c1a 7453 else if (size > 4095)
998032ba 7454 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7f6c1d27 7455
5c648c1a 7456 else if (size > 0)
0a544228 7457 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str);
7f6c1d27 7458
7459 else
7460 fprintf (file, "\tnop\n");
7461 }
7462
7463 /* Reset state info for each function. */
7464 current_frame_info = zero_frame_info;
998032ba 7465
7466 sparc_output_deferred_case_vectors ();
7f6c1d27 7467}
7468\f
7469/* Define the number of delay slots needed for the function epilogue.
7470
7471 On the sparc, we need a slot if either no stack has been allocated,
7472 or the only register saved is the return register. */
7473
7474int
7775000f 7475sparc_flat_epilogue_delay_slots ()
7f6c1d27 7476{
7477 if (!current_frame_info.initialized)
7775000f 7478 (void) sparc_flat_compute_frame_size (get_frame_size ());
7f6c1d27 7479
7480 if (current_frame_info.total_size == 0)
7481 return 1;
7482
7f6c1d27 7483 return 0;
7484}
7485
f229c3f2 7486/* Return true if TRIAL is a valid insn for the epilogue delay slot.
7f6c1d27 7487 Any single length instruction which doesn't reference the stack or frame
7488 pointer is OK. */
7489
7490int
7775000f 7491sparc_flat_eligible_for_epilogue_delay (trial, slot)
7f6c1d27 7492 rtx trial;
b8430a2d 7493 int slot ATTRIBUTE_UNUSED;
7f6c1d27 7494{
946e12d1 7495 rtx pat = PATTERN (trial);
7496
7497 if (get_attr_length (trial) != 1)
7498 return 0;
7499
946e12d1 7500 if (! reg_mentioned_p (stack_pointer_rtx, pat)
7501 && ! reg_mentioned_p (frame_pointer_rtx, pat))
7f6c1d27 7502 return 1;
946e12d1 7503
7f6c1d27 7504 return 0;
7505}
d342fef5 7506\f
7507/* Adjust the cost of a scheduling dependency. Return the new cost of
7508 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7509
32933b3c 7510static int
d342fef5 7511supersparc_adjust_cost (insn, link, dep_insn, cost)
7512 rtx insn;
7513 rtx link;
7514 rtx dep_insn;
7515 int cost;
7516{
7517 enum attr_type insn_type;
7518
7519 if (! recog_memoized (insn))
7520 return 0;
7521
7522 insn_type = get_attr_type (insn);
7523
7524 if (REG_NOTE_KIND (link) == 0)
7525 {
7526 /* Data dependency; DEP_INSN writes a register that INSN reads some
7527 cycles later. */
7528
7529 /* if a load, then the dependence must be on the memory address;
0b0f0553 7530 add an extra "cycle". Note that the cost could be two cycles
7531 if the reg was written late in an instruction group; we ca not tell
d342fef5 7532 here. */
7533 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7534 return cost + 3;
7535
7536 /* Get the delay only if the address of the store is the dependence. */
7537 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7538 {
7539 rtx pat = PATTERN(insn);
7540 rtx dep_pat = PATTERN (dep_insn);
7541
7542 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
0b0f0553 7543 return cost; /* This should not happen! */
d342fef5 7544
7545 /* The dependency between the two instructions was on the data that
7546 is being stored. Assume that this implies that the address of the
7547 store is not dependent. */
7548 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7549 return cost;
7550
7551 return cost + 3; /* An approximation. */
7552 }
7553
7554 /* A shift instruction cannot receive its data from an instruction
7555 in the same cycle; add a one cycle penalty. */
7556 if (insn_type == TYPE_SHIFT)
7557 return cost + 3; /* Split before cascade into shift. */
7558 }
7559 else
7560 {
7561 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7562 INSN writes some cycles later. */
7563
7564 /* These are only significant for the fpu unit; writing a fp reg before
7565 the fpu has finished with it stalls the processor. */
7566
7567 /* Reusing an integer register causes no problems. */
7568 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7569 return 0;
7570 }
7571
7572 return cost;
7573}
f618d313 7574
32933b3c 7575static int
7576hypersparc_adjust_cost (insn, link, dep_insn, cost)
7577 rtx insn;
7578 rtx link;
7579 rtx dep_insn;
7580 int cost;
7581{
7582 enum attr_type insn_type, dep_type;
7583 rtx pat = PATTERN(insn);
7584 rtx dep_pat = PATTERN (dep_insn);
7585
7586 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7587 return cost;
7588
7589 insn_type = get_attr_type (insn);
7590 dep_type = get_attr_type (dep_insn);
7591
7592 switch (REG_NOTE_KIND (link))
7593 {
7594 case 0:
7595 /* Data dependency; DEP_INSN writes a register that INSN reads some
7596 cycles later. */
7597
7598 switch (insn_type)
7599 {
7600 case TYPE_STORE:
7601 case TYPE_FPSTORE:
8eba0400 7602 /* Get the delay iff the address of the store is the dependence. */
32933b3c 7603 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7604 return cost;
7605
7606 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7607 return cost;
7608 return cost + 3;
7609
7610 case TYPE_LOAD:
7611 case TYPE_SLOAD:
7612 case TYPE_FPLOAD:
7613 /* If a load, then the dependence must be on the memory address. If
7614 the addresses aren't equal, then it might be a false dependency */
7615 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7616 {
7617 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7618 || GET_CODE (SET_DEST (dep_pat)) != MEM
7619 || GET_CODE (SET_SRC (pat)) != MEM
7620 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7621 XEXP (SET_SRC (pat), 0)))
7622 return cost + 2;
7623
7624 return cost + 8;
7625 }
7626 break;
7627
7628 case TYPE_BRANCH:
7629 /* Compare to branch latency is 0. There is no benefit from
7630 separating compare and branch. */
7631 if (dep_type == TYPE_COMPARE)
7632 return 0;
7633 /* Floating point compare to branch latency is less than
7634 compare to conditional move. */
7635 if (dep_type == TYPE_FPCMP)
7636 return cost - 1;
7637 break;
c4f04114 7638 default:
7639 break;
32933b3c 7640 }
7641 break;
7642
7643 case REG_DEP_ANTI:
8eba0400 7644 /* Anti-dependencies only penalize the fpu unit. */
32933b3c 7645 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7646 return 0;
7647 break;
7648
7649 default:
7650 break;
7651 }
7652
7653 return cost;
7654}
7655
747af5e7 7656static int
32933b3c 7657sparc_adjust_cost(insn, link, dep, cost)
7658 rtx insn;
7659 rtx link;
7660 rtx dep;
7661 int cost;
7662{
7663 switch (sparc_cpu)
7664 {
7665 case PROCESSOR_SUPERSPARC:
7666 cost = supersparc_adjust_cost (insn, link, dep, cost);
7667 break;
7668 case PROCESSOR_HYPERSPARC:
7669 case PROCESSOR_SPARCLITE86X:
7670 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7671 break;
32933b3c 7672 default:
7673 break;
7674 }
7675 return cost;
7676}
7677
bea4bad2 7678static void
7679sparc_sched_init (dump, sched_verbose, max_ready)
7680 FILE *dump ATTRIBUTE_UNUSED;
7681 int sched_verbose ATTRIBUTE_UNUSED;
7682 int max_ready ATTRIBUTE_UNUSED;
0b0f0553 7683{
0b0f0553 7684}
bea4bad2 7685
0b0f0553 7686static int
bea4bad2 7687sparc_use_dfa_pipeline_interface ()
0b0f0553 7688{
bea4bad2 7689 if ((1 << sparc_cpu) &
7690 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
7691 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7692 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
7693 (1 << PROCESSOR_ULTRASPARC3)))
7694 return 1;
0b0f0553 7695 return 0;
7696}
7697
bea4bad2 7698static int
7699sparc_use_sched_lookahead ()
7700{
7701 if (sparc_cpu == PROCESSOR_ULTRASPARC
7702 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7703 return 4;
7704 if ((1 << sparc_cpu) &
7705 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7706 (1 << PROCESSOR_SPARCLITE86X)))
7707 return 3;
0b0f0553 7708 return 0;
7709}
7710
bea4bad2 7711static int
f618d313 7712sparc_issue_rate ()
7713{
7714 switch (sparc_cpu)
7715 {
bea4bad2 7716 default:
7717 return 1;
7718 case PROCESSOR_V9:
367242d3 7719 /* Assume V9 processors are capable of at least dual-issue. */
f618d313 7720 return 2;
bea4bad2 7721 case PROCESSOR_SUPERSPARC:
7722 return 3;
48403cd2 7723 case PROCESSOR_HYPERSPARC:
7724 case PROCESSOR_SPARCLITE86X:
7725 return 2;
bea4bad2 7726 case PROCESSOR_ULTRASPARC:
7727 case PROCESSOR_ULTRASPARC3:
7728 return 4;
f618d313 7729 }
7730}
367242d3 7731
7732static int
0ca827a6 7733set_extends (insn)
7734 rtx insn;
367242d3 7735{
7736 register rtx pat = PATTERN (insn);
7737
7738 switch (GET_CODE (SET_SRC (pat)))
7739 {
8eba0400 7740 /* Load and some shift instructions zero extend. */
367242d3 7741 case MEM:
7742 case ZERO_EXTEND:
7743 /* sethi clears the high bits */
7744 case HIGH:
7745 /* LO_SUM is used with sethi. sethi cleared the high
7746 bits and the values used with lo_sum are positive */
7747 case LO_SUM:
367242d3 7748 /* Store flag stores 0 or 1 */
7749 case LT: case LTU:
7750 case GT: case GTU:
7751 case LE: case LEU:
7752 case GE: case GEU:
7753 case EQ:
7754 case NE:
7755 return 1;
7756 case AND:
7757 {
0ca827a6 7758 rtx op0 = XEXP (SET_SRC (pat), 0);
367242d3 7759 rtx op1 = XEXP (SET_SRC (pat), 1);
7760 if (GET_CODE (op1) == CONST_INT)
7761 return INTVAL (op1) >= 0;
0ca827a6 7762 if (GET_CODE (op0) != REG)
7763 return 0;
7764 if (sparc_check_64 (op0, insn) == 1)
367242d3 7765 return 1;
0ca827a6 7766 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7767 }
7768 case IOR:
7769 case XOR:
7770 {
7771 rtx op0 = XEXP (SET_SRC (pat), 0);
7772 rtx op1 = XEXP (SET_SRC (pat), 1);
7773 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7774 return 0;
7775 if (GET_CODE (op1) == CONST_INT)
7776 return INTVAL (op1) >= 0;
7777 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
367242d3 7778 }
367242d3 7779 case LSHIFTRT:
7780 return GET_MODE (SET_SRC (pat)) == SImode;
8eba0400 7781 /* Positive integers leave the high bits zero. */
367242d3 7782 case CONST_DOUBLE:
0ca827a6 7783 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
367242d3 7784 case CONST_INT:
0ca827a6 7785 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
367242d3 7786 case ASHIFTRT:
7787 case SIGN_EXTEND:
7788 return - (GET_MODE (SET_SRC (pat)) == SImode);
0ca827a6 7789 case REG:
7790 return sparc_check_64 (SET_SRC (pat), insn);
367242d3 7791 default:
7792 return 0;
7793 }
7794}
7795
8eba0400 7796/* We _ought_ to have only one kind per function, but... */
1f3233d1 7797static GTY(()) rtx sparc_addr_diff_list;
7798static GTY(()) rtx sparc_addr_list;
998032ba 7799
7800void
7801sparc_defer_case_vector (lab, vec, diff)
7802 rtx lab, vec;
7803 int diff;
7804{
7805 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7806 if (diff)
7807 sparc_addr_diff_list
7808 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7809 else
7810 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7811}
7812
7813static void
7814sparc_output_addr_vec (vec)
7815 rtx vec;
7816{
7817 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7818 int idx, vlen = XVECLEN (body, 0);
7819
b6d28b19 7820#ifdef ASM_OUTPUT_ADDR_VEC_START
7821 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7822#endif
7823
998032ba 7824#ifdef ASM_OUTPUT_CASE_LABEL
7825 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7826 NEXT_INSN (lab));
7827#else
805e22b2 7828 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
998032ba 7829#endif
7830
7831 for (idx = 0; idx < vlen; idx++)
7832 {
7833 ASM_OUTPUT_ADDR_VEC_ELT
7834 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7835 }
b6d28b19 7836
7837#ifdef ASM_OUTPUT_ADDR_VEC_END
7838 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7839#endif
998032ba 7840}
7841
7842static void
7843sparc_output_addr_diff_vec (vec)
7844 rtx vec;
7845{
7846 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7847 rtx base = XEXP (XEXP (body, 0), 0);
7848 int idx, vlen = XVECLEN (body, 1);
7849
b6d28b19 7850#ifdef ASM_OUTPUT_ADDR_VEC_START
7851 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7852#endif
7853
998032ba 7854#ifdef ASM_OUTPUT_CASE_LABEL
7855 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7856 NEXT_INSN (lab));
7857#else
805e22b2 7858 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
998032ba 7859#endif
7860
7861 for (idx = 0; idx < vlen; idx++)
7862 {
7863 ASM_OUTPUT_ADDR_DIFF_ELT
7864 (asm_out_file,
7865 body,
7866 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7867 CODE_LABEL_NUMBER (base));
7868 }
b6d28b19 7869
7870#ifdef ASM_OUTPUT_ADDR_VEC_END
7871 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7872#endif
998032ba 7873}
7874
7875static void
7876sparc_output_deferred_case_vectors ()
7877{
7878 rtx t;
164b9556 7879 int align;
998032ba 7880
1832b872 7881 if (sparc_addr_list == NULL_RTX
7882 && sparc_addr_diff_list == NULL_RTX)
7883 return;
7884
998032ba 7885 /* Align to cache line in the function's code section. */
7886 function_section (current_function_decl);
164b9556 7887
7888 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7889 if (align > 0)
1832b872 7890 ASM_OUTPUT_ALIGN (asm_out_file, align);
998032ba 7891
7892 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7893 sparc_output_addr_vec (XEXP (t, 0));
7894 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7895 sparc_output_addr_diff_vec (XEXP (t, 0));
7896
7897 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7898}
7899
367242d3 7900/* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7901 unknown. Return 1 if the high bits are zero, -1 if the register is
7902 sign extended. */
7903int
7904sparc_check_64 (x, insn)
7905 rtx x, insn;
7906{
7907 /* If a register is set only once it is safe to ignore insns this
7908 code does not know how to handle. The loop will either recognize
7909 the single set and return the correct value or fail to recognize
7910 it and return 0. */
7911 int set_once = 0;
0ca827a6 7912 rtx y = x;
7913
7914 if (GET_CODE (x) != REG)
7915 abort ();
7916
7917 if (GET_MODE (x) == DImode)
7918 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
367242d3 7919
0ca827a6 7920 if (flag_expensive_optimizations
7921 && REG_N_SETS (REGNO (y)) == 1)
367242d3 7922 set_once = 1;
7923
7924 if (insn == 0)
cd03a192 7925 {
7926 if (set_once)
7927 insn = get_last_insn_anywhere ();
7928 else
7929 return 0;
7930 }
367242d3 7931
cd03a192 7932 while ((insn = PREV_INSN (insn)))
367242d3 7933 {
7934 switch (GET_CODE (insn))
7935 {
7936 case JUMP_INSN:
7937 case NOTE:
7938 break;
7939 case CODE_LABEL:
7940 case CALL_INSN:
7941 default:
7942 if (! set_once)
7943 return 0;
7944 break;
7945 case INSN:
7946 {
7947 rtx pat = PATTERN (insn);
7948 if (GET_CODE (pat) != SET)
7949 return 0;
7950 if (rtx_equal_p (x, SET_DEST (pat)))
0ca827a6 7951 return set_extends (insn);
7952 if (y && rtx_equal_p (y, SET_DEST (pat)))
7953 return set_extends (insn);
7954 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
367242d3 7955 return 0;
7956 }
7957 }
7958 }
7959 return 0;
7960}
7961
7962char *
7963sparc_v8plus_shift (operands, insn, opcode)
7964 rtx *operands;
7965 rtx insn;
075136a2 7966 const char *opcode;
367242d3 7967{
7968 static char asm_code[60];
7969
7970 if (GET_CODE (operands[3]) == SCRATCH)
7971 operands[3] = operands[0];
58dc6b1f 7972 if (GET_CODE (operands[1]) == CONST_INT)
7973 {
0ca827a6 7974 output_asm_insn ("mov\t%1, %3", operands);
58dc6b1f 7975 }
7976 else
7977 {
0ca827a6 7978 output_asm_insn ("sllx\t%H1, 32, %3", operands);
58dc6b1f 7979 if (sparc_check_64 (operands[1], insn) <= 0)
0ca827a6 7980 output_asm_insn ("srl\t%L1, 0, %L1", operands);
7981 output_asm_insn ("or\t%L1, %3, %3", operands);
58dc6b1f 7982 }
367242d3 7983
7984 strcpy(asm_code, opcode);
7985 if (which_alternative != 2)
0ca827a6 7986 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
367242d3 7987 else
0ca827a6 7988 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
367242d3 7989}
290fa2d3 7990\f
06ac282f 7991/* Output rtl to increment the profiler label LABELNO
7992 for profiling a function entry. */
290fa2d3 7993
7994void
06ac282f 7995sparc_profile_hook (labelno)
290fa2d3 7996 int labelno;
7997{
7998 char buf[32];
06ac282f 7999 rtx lab, fun;
290fa2d3 8000
06ac282f 8001 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8002 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8003 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
290fa2d3 8004
61f83895 8005 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
290fa2d3 8006}
06ac282f 8007\f
6e4758ce 8008#ifdef OBJECT_FORMAT_ELF
2cb4ac60 8009static void
29a0ebee 8010sparc_elf_asm_named_section (name, flags)
2cb4ac60 8011 const char *name;
8012 unsigned int flags;
2cb4ac60 8013{
bb2821c0 8014 if (flags & SECTION_MERGE)
8015 {
8016 /* entsize cannot be expressed in this section attributes
8017 encoding style. */
8018 default_elf_asm_named_section (name, flags);
8019 return;
8020 }
8021
2cb4ac60 8022 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8023
8024 if (!(flags & SECTION_DEBUG))
8025 fputs (",#alloc", asm_out_file);
8026 if (flags & SECTION_WRITE)
8027 fputs (",#write", asm_out_file);
8028 if (flags & SECTION_CODE)
8029 fputs (",#execinstr", asm_out_file);
8030
8031 /* ??? Handle SECTION_BSS. */
8032
8033 fputc ('\n', asm_out_file);
8034}
6e4758ce 8035#endif /* OBJECT_FORMAT_ELF */
3dcaebeb 8036
805e22b2 8037/* We do not allow sibling calls if -mflat, nor
8038 we do not allow indirect calls to be optimized into sibling calls.
8039
8040 Also, on sparc 32-bit we cannot emit a sibling call when the
8041 current function returns a structure. This is because the "unimp
8042 after call" convention would cause the callee to return to the
8043 wrong place. The generic code already disallows cases where the
8044 function being called returns a structure.
8045
8046 It may seem strange how this last case could occur. Usually there
8047 is code after the call which jumps to epilogue code which dumps the
8048 return value into the struct return area. That ought to invalidate
8049 the sibling call right? Well, in the c++ case we can end up passing
8050 the pointer to the struct return area to a constructor (which returns
8051 void) and then nothing else happens. Such a sibling call would look
8052 valid without the added check here. */
8053static bool
8054sparc_function_ok_for_sibcall (decl, exp)
8055 tree decl;
8056 tree exp ATTRIBUTE_UNUSED;
8057{
8058 return (decl
8059 && ! TARGET_FLAT
8060 && (TARGET_ARCH64 || ! current_function_returns_struct));
8061}
8062
52470889 8063/* ??? Similar to the standard section selection, but force reloc-y-ness
8064 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8065 pretending PIC always on), but that's what the old code did. */
8066
8067static void
8068sparc_aout_select_section (t, reloc, align)
8069 tree t;
8070 int reloc;
8071 unsigned HOST_WIDE_INT align;
8072{
39eb84bc 8073 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
52470889 8074}
8075
bbfbe351 8076/* Use text section for a constant unless we need more alignment than
8077 that offers. */
8078
8079static void
8080sparc_aout_select_rtx_section (mode, x, align)
8081 enum machine_mode mode;
8082 rtx x;
8083 unsigned HOST_WIDE_INT align;
8084{
8085 if (align <= MAX_TEXT_ALIGN
8086 && ! (flag_pic && (symbolic_operand (x, mode)
8087 || SUNOS4_SHARED_LIBRARIES)))
8088 readonly_data_section ();
8089 else
8090 data_section ();
8091}
8092
3dcaebeb 8093int
8094sparc_extra_constraint_check (op, c, strict)
8095 rtx op;
61f83895 8096 int c;
3dcaebeb 8097 int strict;
8098{
8099 int reload_ok_mem;
8100
8101 if (TARGET_ARCH64
8102 && (c == 'T' || c == 'U'))
8103 return 0;
8104
8105 switch (c)
8106 {
8107 case 'Q':
8108 return fp_sethi_p (op);
8109
8110 case 'R':
8111 return fp_mov_p (op);
8112
8113 case 'S':
8114 return fp_high_losum_p (op);
8115
8116 case 'U':
8117 if (! strict
8118 || (GET_CODE (op) == REG
8119 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8120 || reg_renumber[REGNO (op)] >= 0)))
8121 return register_ok_for_ldd (op);
8122
8123 return 0;
8124
8125 case 'W':
8126 case 'T':
8127 break;
8128
8129 default:
8130 return 0;
8131 }
8132
8133 /* Our memory extra constraints have to emulate the
8134 behavior of 'm' and 'o' in order for reload to work
8135 correctly. */
8136 if (GET_CODE (op) == MEM)
8137 {
8138 reload_ok_mem = 0;
8139 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8140 && (! strict
8141 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8142 reload_ok_mem = 1;
8143 }
8144 else
8145 {
8146 reload_ok_mem = (reload_in_progress
8147 && GET_CODE (op) == REG
8148 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8149 && reg_renumber [REGNO (op)] < 0);
8150 }
8151
8152 return reload_ok_mem;
8153}
7c27ad86 8154
7987fb04 8155/* ??? This duplicates information provided to the compiler by the
8156 ??? scheduler description. Some day, teach genautomata to output
8157 ??? the latencies and then CSE will just use that. */
8158
7c27ad86 8159int
8160sparc_rtx_costs (x, code, outer_code)
8161 rtx x;
8162 enum rtx_code code, outer_code;
8163{
8164 switch (code)
8165 {
7987fb04 8166 case PLUS: case MINUS: case ABS: case NEG:
8167 case FLOAT: case UNSIGNED_FLOAT:
8168 case FIX: case UNSIGNED_FIX:
8169 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8170 if (FLOAT_MODE_P (GET_MODE (x)))
8171 {
8172 switch (sparc_cpu)
8173 {
8174 case PROCESSOR_ULTRASPARC:
8175 case PROCESSOR_ULTRASPARC3:
8176 return COSTS_N_INSNS (4);
8177
8178 case PROCESSOR_SUPERSPARC:
8179 return COSTS_N_INSNS (3);
8180
8181 case PROCESSOR_CYPRESS:
8182 return COSTS_N_INSNS (5);
8183
8184 case PROCESSOR_HYPERSPARC:
8185 case PROCESSOR_SPARCLITE86X:
8186 default:
8187 return COSTS_N_INSNS (1);
8188 }
8189 }
8190
8191 return COSTS_N_INSNS (1);
8192
8193 case SQRT:
8194 switch (sparc_cpu)
8195 {
8196 case PROCESSOR_ULTRASPARC:
8197 if (GET_MODE (x) == SFmode)
8198 return COSTS_N_INSNS (13);
8199 else
8200 return COSTS_N_INSNS (23);
8201
8202 case PROCESSOR_ULTRASPARC3:
8203 if (GET_MODE (x) == SFmode)
8204 return COSTS_N_INSNS (20);
8205 else
8206 return COSTS_N_INSNS (29);
8207
8208 case PROCESSOR_SUPERSPARC:
8209 return COSTS_N_INSNS (12);
8210
8211 case PROCESSOR_CYPRESS:
8212 return COSTS_N_INSNS (63);
8213
8214 case PROCESSOR_HYPERSPARC:
8215 case PROCESSOR_SPARCLITE86X:
8216 return COSTS_N_INSNS (17);
8217
8218 default:
8219 return COSTS_N_INSNS (30);
8220 }
8221
8222 case COMPARE:
8223 if (FLOAT_MODE_P (GET_MODE (x)))
8224 {
8225 switch (sparc_cpu)
8226 {
8227 case PROCESSOR_ULTRASPARC:
8228 case PROCESSOR_ULTRASPARC3:
8229 return COSTS_N_INSNS (1);
8230
8231 case PROCESSOR_SUPERSPARC:
8232 return COSTS_N_INSNS (3);
8233
8234 case PROCESSOR_CYPRESS:
8235 return COSTS_N_INSNS (5);
8236
8237 case PROCESSOR_HYPERSPARC:
8238 case PROCESSOR_SPARCLITE86X:
8239 default:
8240 return COSTS_N_INSNS (1);
8241 }
8242 }
8243
8244 /* ??? Maybe mark integer compares as zero cost on
8245 ??? all UltraSPARC processors because the result
8246 ??? can be bypassed to a branch in the same group. */
8247
8248 return COSTS_N_INSNS (1);
8249
7c27ad86 8250 case MULT:
7987fb04 8251 if (FLOAT_MODE_P (GET_MODE (x)))
8252 {
8253 switch (sparc_cpu)
8254 {
8255 case PROCESSOR_ULTRASPARC:
8256 case PROCESSOR_ULTRASPARC3:
8257 return COSTS_N_INSNS (4);
8258
8259 case PROCESSOR_SUPERSPARC:
8260 return COSTS_N_INSNS (3);
8261
8262 case PROCESSOR_CYPRESS:
8263 return COSTS_N_INSNS (7);
8264
8265 case PROCESSOR_HYPERSPARC:
8266 case PROCESSOR_SPARCLITE86X:
8267 return COSTS_N_INSNS (1);
8268
8269 default:
8270 return COSTS_N_INSNS (5);
8271 }
8272 }
8273
8274 /* The latency is actually variable for Ultra-I/II
8275 And if one of the inputs have a known constant
8276 value, we could calculate this precisely.
8277
8278 However, for that to be useful we would need to
8279 add some machine description changes which would
8280 make sure small constants ended up in rs1 of the
8281 multiply instruction. This is because the multiply
8282 latency is determined by the number of clear (or
8283 set if the value is negative) bits starting from
8284 the most significant bit of the first input.
8285
8286 The algorithm for computing num_cycles of a multiply
8287 on Ultra-I/II is:
8288
8289 if (rs1 < 0)
8290 highest_bit = highest_clear_bit(rs1);
8291 else
8292 highest_bit = highest_set_bit(rs1);
8293 if (num_bits < 3)
8294 highest_bit = 3;
8295 num_cycles = 4 + ((highest_bit - 3) / 2);
8296
8297 If we did that we would have to also consider register
8298 allocation issues that would result from forcing such
8299 a value into a register.
8300
8301 There are other similar tricks we could play if we
8302 knew, for example, that one input was an array index.
8303
8304 Since we do not play any such tricks currently the
8305 safest thing to do is report the worst case latency. */
7c27ad86 8306 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8307 return (GET_MODE (x) == DImode ?
8308 COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8309
7987fb04 8310 /* Multiply latency on Ultra-III, fortunately, is constant. */
7c27ad86 8311 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8312 return COSTS_N_INSNS (6);
8313
7987fb04 8314 if (sparc_cpu == PROCESSOR_HYPERSPARC
8315 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8316 return COSTS_N_INSNS (17);
8317
7c27ad86 8318 return (TARGET_HARD_MUL
8319 ? COSTS_N_INSNS (5)
8320 : COSTS_N_INSNS (25));
8321
8322 case DIV:
8323 case UDIV:
8324 case MOD:
8325 case UMOD:
7987fb04 8326 if (FLOAT_MODE_P (GET_MODE (x)))
8327 {
8328 switch (sparc_cpu)
8329 {
8330 case PROCESSOR_ULTRASPARC:
8331 if (GET_MODE (x) == SFmode)
8332 return COSTS_N_INSNS (13);
8333 else
8334 return COSTS_N_INSNS (23);
8335
8336 case PROCESSOR_ULTRASPARC3:
8337 if (GET_MODE (x) == SFmode)
8338 return COSTS_N_INSNS (17);
8339 else
8340 return COSTS_N_INSNS (20);
8341
8342 case PROCESSOR_SUPERSPARC:
8343 if (GET_MODE (x) == SFmode)
8344 return COSTS_N_INSNS (6);
8345 else
8346 return COSTS_N_INSNS (9);
8347
8348 case PROCESSOR_HYPERSPARC:
8349 case PROCESSOR_SPARCLITE86X:
8350 if (GET_MODE (x) == SFmode)
8351 return COSTS_N_INSNS (8);
8352 else
8353 return COSTS_N_INSNS (12);
8354
8355 default:
8356 return COSTS_N_INSNS (7);
8357 }
8358 }
8359
7c27ad86 8360 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8361 return (GET_MODE (x) == DImode ?
8362 COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8363 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8364 return (GET_MODE (x) == DImode ?
8365 COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8366 return COSTS_N_INSNS (25);
8367
7987fb04 8368 case IF_THEN_ELSE:
8369 /* Conditional moves. */
8370 switch (sparc_cpu)
8371 {
8372 case PROCESSOR_ULTRASPARC:
8373 return COSTS_N_INSNS (2);
8374
8375 case PROCESSOR_ULTRASPARC3:
8376 if (FLOAT_MODE_P (GET_MODE (x)))
8377 return COSTS_N_INSNS (3);
8378 else
8379 return COSTS_N_INSNS (2);
8380
8381 default:
8382 return COSTS_N_INSNS (1);
8383 }
8384
8385 case MEM:
8386 /* If outer-code is SIGN/ZERO extension we have to subtract
8387 out COSTS_N_INSNS (1) from whatever we return in determining
8388 the cost. */
8389 switch (sparc_cpu)
8390 {
8391 case PROCESSOR_ULTRASPARC:
8392 if (outer_code == ZERO_EXTEND)
8393 return COSTS_N_INSNS (1);
8394 else
8395 return COSTS_N_INSNS (2);
8396
8397 case PROCESSOR_ULTRASPARC3:
8398 if (outer_code == ZERO_EXTEND)
8399 {
8400 if (GET_MODE (x) == QImode
8401 || GET_MODE (x) == HImode
8402 || outer_code == SIGN_EXTEND)
8403 return COSTS_N_INSNS (2);
8404 else
8405 return COSTS_N_INSNS (1);
8406 }
8407 else
8408 {
8409 /* This handles sign extension (3 cycles)
8410 and everything else (2 cycles). */
8411 return COSTS_N_INSNS (2);
8412 }
8413
8414 case PROCESSOR_SUPERSPARC:
8415 if (FLOAT_MODE_P (GET_MODE (x))
8416 || outer_code == ZERO_EXTEND
8417 || outer_code == SIGN_EXTEND)
8418 return COSTS_N_INSNS (0);
8419 else
8420 return COSTS_N_INSNS (1);
8421
8422 case PROCESSOR_TSC701:
8423 if (outer_code == ZERO_EXTEND
8424 || outer_code == SIGN_EXTEND)
8425 return COSTS_N_INSNS (2);
8426 else
8427 return COSTS_N_INSNS (3);
8428
8429 case PROCESSOR_CYPRESS:
8430 if (outer_code == ZERO_EXTEND
8431 || outer_code == SIGN_EXTEND)
8432 return COSTS_N_INSNS (1);
8433 else
8434 return COSTS_N_INSNS (2);
8435
8436 case PROCESSOR_HYPERSPARC:
8437 case PROCESSOR_SPARCLITE86X:
8438 default:
8439 if (outer_code == ZERO_EXTEND
8440 || outer_code == SIGN_EXTEND)
8441 return COSTS_N_INSNS (0);
8442 else
8443 return COSTS_N_INSNS (1);
8444 }
7c27ad86 8445
8446 case CONST_INT:
8447 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8448 return 0;
8449
8450 /* fallthru */
8451 case HIGH:
8452 return 2;
8453
8454 case CONST:
8455 case LABEL_REF:
8456 case SYMBOL_REF:
8457 return 4;
8458
8459 case CONST_DOUBLE:
8460 if (GET_MODE (x) == DImode)
8461 if ((XINT (x, 3) == 0
8462 && (unsigned) XINT (x, 2) < 0x1000)
8463 || (XINT (x, 3) == -1
8464 && XINT (x, 2) < 0
8465 && XINT (x, 2) >= -0x1000))
8466 return 0;
8467 return 8;
8468
8469 default:
8470 abort();
8471 };
8472}
7811991d 8473
8474/* If we are referencing a function make the SYMBOL_REF special. In
8475 the Embedded Medium/Anywhere code model, %g4 points to the data
8476 segment so we must not add it to function addresses. */
8477
8478static void
8479sparc_encode_section_info (decl, first)
8480 tree decl;
8481 int first ATTRIBUTE_UNUSED;
8482{
8483 if (TARGET_CM_EMBMEDANY && TREE_CODE (decl) == FUNCTION_DECL)
8484 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
8485}
776507d0 8486
8487/* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8488 Used for C++ multiple inheritance. */
8489
6988553d 8490static void
eb344f43 8491sparc_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
776507d0 8492 FILE *file;
8493 tree thunk_fndecl ATTRIBUTE_UNUSED;
8494 HOST_WIDE_INT delta;
eb344f43 8495 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
776507d0 8496 tree function;
8497{
8498 rtx this, insn, funexp, delta_rtx, tmp;
8499
8500 reload_completed = 1;
8501 no_new_pseudos = 1;
8502 current_function_uses_only_leaf_regs = 1;
8503
8504 emit_note (NULL, NOTE_INSN_PROLOGUE_END);
8505
8506 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8507 returns a structure, the structure return pointer is there instead. */
8508 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
8509 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
8510 else
8511 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
8512
8513 /* Add DELTA. When possible use a plain add, otherwise load it into
8514 a register first. */
8515 delta_rtx = GEN_INT (delta);
8516 if (!SPARC_SIMM13_P (delta))
8517 {
8518 rtx scratch = gen_rtx_REG (Pmode, 1);
8519 if (TARGET_ARCH64)
8520 sparc_emit_set_const64 (scratch, delta_rtx);
8521 else
8522 sparc_emit_set_const32 (scratch, delta_rtx);
8523 delta_rtx = scratch;
8524 }
8525
8526 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
8527 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
8528
8529 /* Generate a tail call to the target function. */
8530 if (! TREE_USED (function))
8531 {
8532 assemble_external (function);
8533 TREE_USED (function) = 1;
8534 }
8535 funexp = XEXP (DECL_RTL (function), 0);
8536 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8537 insn = emit_call_insn (gen_sibcall (funexp));
8538 SIBLING_CALL_P (insn) = 1;
8539 emit_barrier ();
8540
8541 /* Run just enough of rest_of_compilation to get the insns emitted.
8542 There's not really enough bulk here to make other passes such as
8543 instruction scheduling worth while. Note that use_thunk calls
8544 assemble_start_function and assemble_end_function. */
8545 insn = get_insns ();
8546 shorten_branches (insn);
8547 final_start_function (insn, file, 1);
8548 final (insn, file, 1, 0);
8549 final_end_function ();
8550
8551 reload_completed = 0;
8552 no_new_pseudos = 0;
8553}
1f3233d1 8554
8555#include "gt-sparc.h"
Mirror of https://gcc.gnu.org/git/gcc.git