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c3427c7d | 1 | /* Subroutines for insn-output.c for SPARC. |
4592bdcb | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
85009435 | 3 | 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
ab835497 | 4 | Contributed by Michael Tiemann (tiemann@cygnus.com) |
c3427c7d | 5 | 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
61a55e8b | 6 | at Cygnus Support. |
ab835497 | 7 | |
4d8af13f | 8 | This file is part of GCC. |
ab835497 | 9 | |
4d8af13f | 10 | GCC is free software; you can redistribute it and/or modify |
ab835497 RK |
11 | it under the terms of the GNU General Public License as published by |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
4d8af13f | 15 | GCC is distributed in the hope that it will be useful, |
ab835497 RK |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
4d8af13f | 21 | along with GCC; see the file COPYING. If not, write to |
c15c9075 RK |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, |
23 | Boston, MA 02111-1307, USA. */ | |
ab835497 | 24 | |
ab835497 | 25 | #include "config.h" |
284d86e9 | 26 | #include "system.h" |
4977bab6 ZW |
27 | #include "coretypes.h" |
28 | #include "tm.h" | |
210aa14a | 29 | #include "tree.h" |
ab835497 RK |
30 | #include "rtl.h" |
31 | #include "regs.h" | |
32 | #include "hard-reg-set.h" | |
33 | #include "real.h" | |
34 | #include "insn-config.h" | |
35 | #include "conditions.h" | |
ab835497 RK |
36 | #include "output.h" |
37 | #include "insn-attr.h" | |
38 | #include "flags.h" | |
49ad7cfa | 39 | #include "function.h" |
ab835497 | 40 | #include "expr.h" |
e78d8e51 | 41 | #include "optabs.h" |
ab835497 | 42 | #include "recog.h" |
487a6e06 | 43 | #include "toplev.h" |
d07d525a | 44 | #include "ggc.h" |
b1474bb7 | 45 | #include "tm_p.h" |
e78d8e51 | 46 | #include "debug.h" |
672a6f42 NB |
47 | #include "target.h" |
48 | #include "target-def.h" | |
117dca74 | 49 | #include "cfglayout.h" |
ab835497 | 50 | |
61a55e8b DE |
51 | /* 1 if the caller has placed an "unimp" insn immediately after the call. |
52 | This is used in v8 code when calling a function that returns a structure. | |
06b967f9 RK |
53 | v9 doesn't have this. Be careful to have this test be the same as that |
54 | used on the call. */ | |
55 | ||
56 | #define SKIP_CALLERS_UNIMP_P \ | |
57 | (!TARGET_ARCH64 && current_function_returns_struct \ | |
58 | && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
59 | && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
60 | == INTEGER_CST)) | |
61a55e8b | 61 | |
ab835497 RK |
62 | /* Global variables for machine-dependent things. */ |
63 | ||
61a55e8b DE |
64 | /* Size of frame. Need to know this to emit return insns from leaf procedures. |
65 | ACTUAL_FSIZE is set by compute_frame_size() which is called during the | |
66 | reload pass. This is important as the value is later used in insn | |
67 | scheduling (to see what can go in a delay slot). | |
68 | APPARENT_FSIZE is the size of the stack less the register save area and less | |
69 | the outgoing argument area. It is used when saving call preserved regs. */ | |
70 | static int apparent_fsize; | |
71 | static int actual_fsize; | |
72 | ||
33074e5f RH |
73 | /* Number of live general or floating point registers needed to be |
74 | saved (as 4-byte quantities). */ | |
e48addee JJ |
75 | static int num_gfregs; |
76 | ||
ab835497 RK |
77 | /* Save the operands last given to a compare for use when we |
78 | generate a scc or bcc insn. */ | |
ab835497 RK |
79 | rtx sparc_compare_op0, sparc_compare_op1; |
80 | ||
33074e5f RH |
81 | /* Coordinate with the md file wrt special insns created by |
82 | sparc_nonflat_function_epilogue. */ | |
83 | bool sparc_emitting_epilogue; | |
ab835497 | 84 | |
563c12b0 RH |
85 | /* Vector to say how input registers are mapped to output registers. |
86 | HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to | |
87 | eliminate it. You must use -fomit-frame-pointer to get that. */ | |
d70e94ec | 88 | char leaf_reg_remap[] = |
ab835497 RK |
89 | { 0, 1, 2, 3, 4, 5, 6, 7, |
90 | -1, -1, -1, -1, -1, -1, 14, -1, | |
91 | -1, -1, -1, -1, -1, -1, -1, -1, | |
92 | 8, 9, 10, 11, 12, 13, -1, 15, | |
93 | ||
94 | 32, 33, 34, 35, 36, 37, 38, 39, | |
95 | 40, 41, 42, 43, 44, 45, 46, 47, | |
96 | 48, 49, 50, 51, 52, 53, 54, 55, | |
61a55e8b DE |
97 | 56, 57, 58, 59, 60, 61, 62, 63, |
98 | 64, 65, 66, 67, 68, 69, 70, 71, | |
99 | 72, 73, 74, 75, 76, 77, 78, 79, | |
100 | 80, 81, 82, 83, 84, 85, 86, 87, | |
101 | 88, 89, 90, 91, 92, 93, 94, 95, | |
c4ce6853 | 102 | 96, 97, 98, 99, 100}; |
ab835497 | 103 | |
7d167afd JJ |
104 | /* Vector, indexed by hard register number, which contains 1 |
105 | for a register that is allowable in a candidate for leaf | |
106 | function treatment. */ | |
107 | char sparc_leaf_regs[] = | |
108 | { 1, 1, 1, 1, 1, 1, 1, 1, | |
109 | 0, 0, 0, 0, 0, 0, 1, 0, | |
110 | 0, 0, 0, 0, 0, 0, 0, 0, | |
111 | 1, 1, 1, 1, 1, 1, 0, 1, | |
112 | 1, 1, 1, 1, 1, 1, 1, 1, | |
113 | 1, 1, 1, 1, 1, 1, 1, 1, | |
114 | 1, 1, 1, 1, 1, 1, 1, 1, | |
115 | 1, 1, 1, 1, 1, 1, 1, 1, | |
116 | 1, 1, 1, 1, 1, 1, 1, 1, | |
117 | 1, 1, 1, 1, 1, 1, 1, 1, | |
118 | 1, 1, 1, 1, 1, 1, 1, 1, | |
119 | 1, 1, 1, 1, 1, 1, 1, 1, | |
120 | 1, 1, 1, 1, 1}; | |
121 | ||
5751a10b JJ |
122 | struct machine_function GTY(()) |
123 | { | |
124 | /* Some local-dynamic TLS symbol name. */ | |
125 | const char *some_ld_name; | |
126 | }; | |
127 | ||
ab835497 RK |
128 | /* Name of where we pretend to think the frame pointer points. |
129 | Normally, this is "%fp", but if we are in a leaf procedure, | |
61a55e8b DE |
130 | this is "%sp+something". We record "something" separately as it may be |
131 | too big for reg+constant addressing. */ | |
132 | ||
3bb5de61 | 133 | static const char *frame_base_name; |
61a55e8b | 134 | static int frame_base_offset; |
ab835497 | 135 | |
e80d5f80 KG |
136 | static void sparc_init_modes (void); |
137 | static int save_regs (FILE *, int, int, const char *, int, int, int); | |
138 | static int restore_regs (FILE *, int, int, const char *, int, int); | |
139 | static void build_big_number (FILE *, int, const char *); | |
140 | static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode, | |
141 | tree, int, int, int *, int *); | |
142 | ||
143 | static int supersparc_adjust_cost (rtx, rtx, rtx, int); | |
144 | static int hypersparc_adjust_cost (rtx, rtx, rtx, int); | |
145 | ||
146 | static void sparc_output_addr_vec (rtx); | |
147 | static void sparc_output_addr_diff_vec (rtx); | |
148 | static void sparc_output_deferred_case_vectors (void); | |
149 | static int check_return_regs (rtx); | |
150 | static int epilogue_renumber (rtx *, int); | |
151 | static bool sparc_assemble_integer (rtx, unsigned int, int); | |
152 | static int set_extends (rtx); | |
153 | static void output_restore_regs (FILE *, int); | |
154 | static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT); | |
155 | static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
156 | static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT); | |
157 | static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT); | |
158 | static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int); | |
159 | static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int); | |
ede75ee8 | 160 | #ifdef OBJECT_FORMAT_ELF |
e80d5f80 | 161 | static void sparc_elf_asm_named_section (const char *, unsigned int); |
ede75ee8 | 162 | #endif |
e80d5f80 | 163 | static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT) |
ae46c4e0 | 164 | ATTRIBUTE_UNUSED; |
e80d5f80 KG |
165 | static void sparc_aout_select_rtx_section (enum machine_mode, rtx, |
166 | unsigned HOST_WIDE_INT) | |
b64a1b53 | 167 | ATTRIBUTE_UNUSED; |
c237e94a | 168 | |
e80d5f80 KG |
169 | static int sparc_adjust_cost (rtx, rtx, rtx, int); |
170 | static int sparc_issue_rate (void); | |
171 | static void sparc_sched_init (FILE *, int, int); | |
172 | static int sparc_use_dfa_pipeline_interface (void); | |
173 | static int sparc_use_sched_lookahead (void); | |
174 | ||
175 | static void emit_soft_tfmode_libcall (const char *, int, rtx *); | |
176 | static void emit_soft_tfmode_binop (enum rtx_code, rtx *); | |
177 | static void emit_soft_tfmode_unop (enum rtx_code, rtx *); | |
178 | static void emit_soft_tfmode_cvt (enum rtx_code, rtx *); | |
179 | static void emit_hard_tfmode_operation (enum rtx_code, rtx *); | |
180 | ||
181 | static bool sparc_function_ok_for_sibcall (tree, tree); | |
c15c90bb | 182 | static void sparc_init_libfuncs (void); |
e80d5f80 KG |
183 | static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
184 | HOST_WIDE_INT, tree); | |
5751a10b JJ |
185 | static struct machine_function * sparc_init_machine_status (void); |
186 | static bool sparc_cannot_force_const_mem (rtx); | |
187 | static rtx sparc_tls_get_addr (void); | |
188 | static rtx sparc_tls_got (void); | |
189 | static const char *get_some_local_dynamic_name (void); | |
190 | static int get_some_local_dynamic_name_1 (rtx *, void *); | |
e80d5f80 | 191 | static bool sparc_rtx_costs (rtx, int, int, int *); |
61a55e8b DE |
192 | \f |
193 | /* Option handling. */ | |
194 | ||
a0a301fc | 195 | /* Code model option as passed by user. */ |
3bb5de61 | 196 | const char *sparc_cmodel_string; |
a0a301fc DE |
197 | /* Parsed value. */ |
198 | enum cmodel sparc_cmodel; | |
199 | ||
1cb36a98 RH |
200 | char sparc_hard_reg_printed[8]; |
201 | ||
16956f6e DE |
202 | struct sparc_cpu_select sparc_select[] = |
203 | { | |
204 | /* switch name, tune arch */ | |
205 | { (char *)0, "default", 1, 1 }, | |
206 | { (char *)0, "-mcpu=", 1, 1 }, | |
207 | { (char *)0, "-mtune=", 1, 0 }, | |
db3d4438 | 208 | { 0, 0, 0, 0 } |
16956f6e | 209 | }; |
733f53f5 | 210 | |
16956f6e DE |
211 | /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ |
212 | enum processor_type sparc_cpu; | |
672a6f42 NB |
213 | \f |
214 | /* Initialize the GCC target structure. */ | |
301d03af RS |
215 | |
216 | /* The sparc default is to use .half rather than .short for aligned | |
217 | HI objects. Use .word instead of .long on non-ELF systems. */ | |
218 | #undef TARGET_ASM_ALIGNED_HI_OP | |
219 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
220 | #ifndef OBJECT_FORMAT_ELF | |
221 | #undef TARGET_ASM_ALIGNED_SI_OP | |
222 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
223 | #endif | |
224 | ||
225 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
226 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t" | |
227 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
228 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t" | |
229 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
230 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t" | |
231 | ||
232 | /* The target hook has to handle DI-mode values. */ | |
233 | #undef TARGET_ASM_INTEGER | |
234 | #define TARGET_ASM_INTEGER sparc_assemble_integer | |
235 | ||
08c148a8 NB |
236 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
237 | #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue | |
238 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
239 | #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue | |
733f53f5 | 240 | |
c237e94a ZW |
241 | #undef TARGET_SCHED_ADJUST_COST |
242 | #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost | |
243 | #undef TARGET_SCHED_ISSUE_RATE | |
244 | #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate | |
c237e94a ZW |
245 | #undef TARGET_SCHED_INIT |
246 | #define TARGET_SCHED_INIT sparc_sched_init | |
fae15c93 VM |
247 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE |
248 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface | |
249 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD | |
250 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead | |
c237e94a | 251 | |
4977bab6 ZW |
252 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
253 | #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall | |
254 | ||
c15c90bb ZW |
255 | #undef TARGET_INIT_LIBFUNCS |
256 | #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs | |
257 | ||
5751a10b JJ |
258 | #ifdef HAVE_AS_TLS |
259 | #undef TARGET_HAVE_TLS | |
260 | #define TARGET_HAVE_TLS true | |
261 | #endif | |
262 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
263 | #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem | |
264 | ||
c590b625 RH |
265 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
266 | #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk | |
3961e8fe RH |
267 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
268 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 269 | |
3c50106f RH |
270 | #undef TARGET_RTX_COSTS |
271 | #define TARGET_RTX_COSTS sparc_rtx_costs | |
dcefdf67 RH |
272 | #undef TARGET_ADDRESS_COST |
273 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
3c50106f | 274 | |
f6897b10 | 275 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 276 | \f |
61a55e8b DE |
277 | /* Validate and override various options, and do some machine dependent |
278 | initialization. */ | |
279 | ||
280 | void | |
fc27d102 | 281 | sparc_override_options (void) |
61a55e8b | 282 | { |
a0a301fc | 283 | static struct code_model { |
8b60264b KG |
284 | const char *const name; |
285 | const int value; | |
286 | } const cmodels[] = { | |
a0a301fc DE |
287 | { "32", CM_32 }, |
288 | { "medlow", CM_MEDLOW }, | |
289 | { "medmid", CM_MEDMID }, | |
290 | { "medany", CM_MEDANY }, | |
291 | { "embmedany", CM_EMBMEDANY }, | |
292 | { 0, 0 } | |
293 | }; | |
8b60264b | 294 | const struct code_model *cmodel; |
16956f6e | 295 | /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ |
733f53f5 | 296 | static struct cpu_default { |
8b60264b KG |
297 | const int cpu; |
298 | const char *const name; | |
299 | } const cpu_default[] = { | |
a0a301fc | 300 | /* There must be one entry here for each TARGET_CPU value. */ |
16956f6e | 301 | { TARGET_CPU_sparc, "cypress" }, |
3592ea0d | 302 | { TARGET_CPU_sparclet, "tsc701" }, |
16956f6e | 303 | { TARGET_CPU_sparclite, "f930" }, |
a0a301fc | 304 | { TARGET_CPU_v8, "v8" }, |
8947065c RH |
305 | { TARGET_CPU_hypersparc, "hypersparc" }, |
306 | { TARGET_CPU_sparclite86x, "sparclite86x" }, | |
a0a301fc DE |
307 | { TARGET_CPU_supersparc, "supersparc" }, |
308 | { TARGET_CPU_v9, "v9" }, | |
ba542005 | 309 | { TARGET_CPU_ultrasparc, "ultrasparc" }, |
fae15c93 | 310 | { TARGET_CPU_ultrasparc3, "ultrasparc3" }, |
db3d4438 | 311 | { 0, 0 } |
733f53f5 | 312 | }; |
8b60264b | 313 | const struct cpu_default *def; |
16956f6e | 314 | /* Table of values for -m{cpu,tune}=. */ |
733f53f5 | 315 | static struct cpu_table { |
8b60264b KG |
316 | const char *const name; |
317 | const enum processor_type processor; | |
318 | const int disable; | |
319 | const int enable; | |
320 | } const cpu_table[] = { | |
16956f6e DE |
321 | { "v7", PROCESSOR_V7, MASK_ISA, 0 }, |
322 | { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, | |
323 | { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, | |
733f53f5 | 324 | /* TI TMS390Z55 supersparc */ |
16956f6e DE |
325 | { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, |
326 | { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, | |
733f53f5 DE |
327 | /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. |
328 | The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ | |
16956f6e DE |
329 | { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, |
330 | { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, | |
8947065c | 331 | { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, |
d3ec6b06 VM |
332 | { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, |
333 | MASK_SPARCLITE }, | |
16956f6e | 334 | { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, |
733f53f5 | 335 | /* TEMIC sparclet */ |
3592ea0d | 336 | { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, |
16956f6e | 337 | { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, |
5cb01b65 JJ |
338 | /* TI ultrasparc I, II, IIi */ |
339 | { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 | |
340 | /* Although insns using %y are deprecated, it is a clear win on current | |
80ffc95e | 341 | ultrasparcs. */ |
3276910d | 342 | |MASK_DEPRECATED_V8_INSNS}, |
fae15c93 VM |
343 | /* TI ultrasparc III */ |
344 | /* ??? Check if %y issue still holds true in ultra3. */ | |
345 | { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, | |
db3d4438 | 346 | { 0, 0, 0, 0 } |
733f53f5 | 347 | }; |
8b60264b KG |
348 | const struct cpu_table *cpu; |
349 | const struct sparc_cpu_select *sel; | |
a0a301fc | 350 | int fpu; |
345a6161 | 351 | |
a0a301fc DE |
352 | #ifndef SPARC_BI_ARCH |
353 | /* Check for unsupported architecture size. */ | |
354 | if (! TARGET_64BIT != DEFAULT_ARCH32_P) | |
3276910d RK |
355 | error ("%s is not supported by this configuration", |
356 | DEFAULT_ARCH32_P ? "-m64" : "-m32"); | |
a0a301fc DE |
357 | #endif |
358 | ||
4710d3eb JJ |
359 | /* We force all 64bit archs to use 128 bit long double */ |
360 | if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128) | |
361 | { | |
362 | error ("-mlong-double-64 not allowed with -m64"); | |
363 | target_flags |= MASK_LONG_DOUBLE_128; | |
364 | } | |
365 | ||
a0a301fc DE |
366 | /* Code model selection. */ |
367 | sparc_cmodel = SPARC_DEFAULT_CMODEL; | |
345a6161 DM |
368 | |
369 | #ifdef SPARC_BI_ARCH | |
370 | if (TARGET_ARCH32) | |
371 | sparc_cmodel = CM_32; | |
372 | #endif | |
373 | ||
a0a301fc DE |
374 | if (sparc_cmodel_string != NULL) |
375 | { | |
376 | if (TARGET_ARCH64) | |
377 | { | |
378 | for (cmodel = &cmodels[0]; cmodel->name; cmodel++) | |
379 | if (strcmp (sparc_cmodel_string, cmodel->name) == 0) | |
380 | break; | |
381 | if (cmodel->name == NULL) | |
382 | error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); | |
383 | else | |
384 | sparc_cmodel = cmodel->value; | |
385 | } | |
386 | else | |
387 | error ("-mcmodel= is not supported on 32 bit systems"); | |
388 | } | |
16956f6e | 389 | |
a0a301fc | 390 | fpu = TARGET_FPU; /* save current -mfpu status */ |
1f1406b4 | 391 | |
a0a301fc | 392 | /* Set the default CPU. */ |
16956f6e DE |
393 | for (def = &cpu_default[0]; def->name; ++def) |
394 | if (def->cpu == TARGET_CPU_DEFAULT) | |
395 | break; | |
396 | if (! def->name) | |
397 | abort (); | |
398 | sparc_select[0].string = def->name; | |
399 | ||
400 | for (sel = &sparc_select[0]; sel->name; ++sel) | |
61a55e8b | 401 | { |
16956f6e | 402 | if (sel->string) |
733f53f5 | 403 | { |
16956f6e DE |
404 | for (cpu = &cpu_table[0]; cpu->name; ++cpu) |
405 | if (! strcmp (sel->string, cpu->name)) | |
406 | { | |
407 | if (sel->set_tune_p) | |
408 | sparc_cpu = cpu->processor; | |
409 | ||
410 | if (sel->set_arch_p) | |
411 | { | |
412 | target_flags &= ~cpu->disable; | |
413 | target_flags |= cpu->enable; | |
414 | } | |
415 | break; | |
416 | } | |
417 | ||
418 | if (! cpu->name) | |
419 | error ("bad value (%s) for %s switch", sel->string, sel->name); | |
733f53f5 | 420 | } |
61a55e8b | 421 | } |
97da85b7 | 422 | |
1f1406b4 | 423 | /* If -mfpu or -mno-fpu was explicitly used, don't override with |
46cc13b3 RO |
424 | the processor default. Clear MASK_FPU_SET to avoid confusing |
425 | the reverse mapping from switch values to names. */ | |
1f1406b4 | 426 | if (TARGET_FPU_SET) |
46cc13b3 RO |
427 | { |
428 | target_flags = (target_flags & ~MASK_FPU) | fpu; | |
429 | target_flags &= ~MASK_FPU_SET; | |
430 | } | |
1f1406b4 | 431 | |
a5774a7d JJ |
432 | /* Don't allow -mvis if FPU is disabled. */ |
433 | if (! TARGET_FPU) | |
434 | target_flags &= ~MASK_VIS; | |
435 | ||
436 | /* -mvis assumes UltraSPARC+, so we are sure v9 instructions | |
437 | are available. | |
438 | -m64 also implies v9. */ | |
439 | if (TARGET_VIS || TARGET_ARCH64) | |
c4031a04 JJ |
440 | { |
441 | target_flags |= MASK_V9; | |
442 | target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); | |
443 | } | |
a5774a7d | 444 | |
16956f6e DE |
445 | /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ |
446 | if (TARGET_V9 && TARGET_ARCH32) | |
733f53f5 | 447 | target_flags |= MASK_DEPRECATED_V8_INSNS; |
61a55e8b | 448 | |
345a6161 DM |
449 | /* V8PLUS requires V9, makes no sense in 64 bit mode. */ |
450 | if (! TARGET_V9 || TARGET_ARCH64) | |
284d86e9 JC |
451 | target_flags &= ~MASK_V8PLUS; |
452 | ||
82d6b402 RH |
453 | /* Don't use stack biasing in 32 bit mode. */ |
454 | if (TARGET_ARCH32) | |
455 | target_flags &= ~MASK_STACK_BIAS; | |
f952a238 | 456 | |
efa3896a | 457 | /* Supply a default value for align_functions. */ |
fae15c93 VM |
458 | if (align_functions == 0 |
459 | && (sparc_cpu == PROCESSOR_ULTRASPARC | |
460 | || sparc_cpu == PROCESSOR_ULTRASPARC3)) | |
efa3896a | 461 | align_functions = 32; |
bf62bbf1 | 462 | |
82d6b402 RH |
463 | /* Validate PCC_STRUCT_RETURN. */ |
464 | if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) | |
465 | flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); | |
466 | ||
301d03af RS |
467 | /* Only use .uaxword when compiling for a 64-bit target. */ |
468 | if (!TARGET_ARCH64) | |
469 | targetm.asm_out.unaligned_op.di = NULL; | |
470 | ||
61a55e8b DE |
471 | /* Do various machine dependent initializations. */ |
472 | sparc_init_modes (); | |
5751a10b JJ |
473 | |
474 | /* Set up function hooks. */ | |
475 | init_machine_status = sparc_init_machine_status; | |
61a55e8b DE |
476 | } |
477 | \f | |
cd5fb1ee DE |
478 | /* Miscellaneous utilities. */ |
479 | ||
480 | /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move | |
481 | or branch on register contents instructions. */ | |
482 | ||
483 | int | |
fc27d102 | 484 | v9_regcmp_p (enum rtx_code code) |
cd5fb1ee DE |
485 | { |
486 | return (code == EQ || code == NE || code == GE || code == LT | |
487 | || code == LE || code == GT); | |
488 | } | |
bfd6bc60 | 489 | |
cd5fb1ee DE |
490 | \f |
491 | /* Operand constraints. */ | |
492 | ||
5e7a8ee0 | 493 | /* Return nonzero only if OP is a register of mode MODE, |
e6c1be7e | 494 | or const0_rtx. */ |
c4ce6853 | 495 | |
ab835497 | 496 | int |
fc27d102 | 497 | reg_or_0_operand (rtx op, enum machine_mode mode) |
ab835497 | 498 | { |
c4ce6853 DE |
499 | if (register_operand (op, mode)) |
500 | return 1; | |
c4ce6853 | 501 | if (op == const0_rtx) |
ab835497 | 502 | return 1; |
5b486ce0 | 503 | if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE |
ab835497 RK |
504 | && CONST_DOUBLE_HIGH (op) == 0 |
505 | && CONST_DOUBLE_LOW (op) == 0) | |
506 | return 1; | |
7ce86678 | 507 | if (fp_zero_operand (op, mode)) |
302484ff | 508 | return 1; |
ab835497 RK |
509 | return 0; |
510 | } | |
511 | ||
5e7a8ee0 | 512 | /* Return nonzero only if OP is const1_rtx. */ |
84ea5bc1 JJ |
513 | |
514 | int | |
fc27d102 | 515 | const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
84ea5bc1 JJ |
516 | { |
517 | return op == const1_rtx; | |
518 | } | |
519 | ||
302484ff | 520 | /* Nonzero if OP is a floating point value with value 0.0. */ |
c4ce6853 | 521 | |
302484ff | 522 | int |
fc27d102 | 523 | fp_zero_operand (rtx op, enum machine_mode mode) |
302484ff | 524 | { |
7ce86678 RH |
525 | if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT) |
526 | return 0; | |
527 | return op == CONST0_RTX (mode); | |
302484ff JW |
528 | } |
529 | ||
2a732575 JJ |
530 | /* Nonzero if OP is a register operand in floating point register. */ |
531 | ||
532 | int | |
fc27d102 | 533 | fp_register_operand (rtx op, enum machine_mode mode) |
2a732575 JJ |
534 | { |
535 | if (! register_operand (op, mode)) | |
536 | return 0; | |
537 | if (GET_CODE (op) == SUBREG) | |
538 | op = SUBREG_REG (op); | |
539 | return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op)); | |
540 | } | |
541 | ||
62190128 DM |
542 | /* Nonzero if OP is a floating point constant which can |
543 | be loaded into an integer register using a single | |
544 | sethi instruction. */ | |
545 | ||
546 | int | |
fc27d102 | 547 | fp_sethi_p (rtx op) |
62190128 DM |
548 | { |
549 | if (GET_CODE (op) == CONST_DOUBLE) | |
550 | { | |
551 | REAL_VALUE_TYPE r; | |
552 | long i; | |
553 | ||
554 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
555 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
556 | ! REAL_VALUE_MINUS_ZERO (r)) | |
557 | return 0; | |
558 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
559 | if (SPARC_SETHI_P (i)) | |
560 | return 1; | |
561 | } | |
562 | ||
563 | return 0; | |
564 | } | |
565 | ||
566 | /* Nonzero if OP is a floating point constant which can | |
567 | be loaded into an integer register using a single | |
568 | mov instruction. */ | |
569 | ||
570 | int | |
fc27d102 | 571 | fp_mov_p (rtx op) |
62190128 DM |
572 | { |
573 | if (GET_CODE (op) == CONST_DOUBLE) | |
574 | { | |
575 | REAL_VALUE_TYPE r; | |
576 | long i; | |
577 | ||
578 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
579 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
580 | ! REAL_VALUE_MINUS_ZERO (r)) | |
581 | return 0; | |
582 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
583 | if (SPARC_SIMM13_P (i)) | |
584 | return 1; | |
585 | } | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | /* Nonzero if OP is a floating point constant which can | |
591 | be loaded into an integer register using a high/losum | |
592 | instruction sequence. */ | |
593 | ||
594 | int | |
fc27d102 | 595 | fp_high_losum_p (rtx op) |
62190128 DM |
596 | { |
597 | /* The constraints calling this should only be in | |
598 | SFmode move insns, so any constant which cannot | |
599 | be moved using a single insn will do. */ | |
600 | if (GET_CODE (op) == CONST_DOUBLE) | |
601 | { | |
602 | REAL_VALUE_TYPE r; | |
603 | long i; | |
604 | ||
605 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
606 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
607 | ! REAL_VALUE_MINUS_ZERO (r)) | |
608 | return 0; | |
609 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
610 | if (! SPARC_SETHI_P (i) | |
611 | && ! SPARC_SIMM13_P (i)) | |
612 | return 1; | |
613 | } | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
61a55e8b DE |
618 | /* Nonzero if OP is an integer register. */ |
619 | ||
620 | int | |
fc27d102 | 621 | intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
61a55e8b DE |
622 | { |
623 | return (register_operand (op, SImode) | |
a9e27770 | 624 | || (TARGET_ARCH64 && register_operand (op, DImode))); |
61a55e8b DE |
625 | } |
626 | ||
627 | /* Nonzero if OP is a floating point condition code register. */ | |
628 | ||
629 | int | |
fc27d102 | 630 | fcc_reg_operand (rtx op, enum machine_mode mode) |
61a55e8b DE |
631 | { |
632 | /* This can happen when recog is called from combine. Op may be a MEM. | |
633 | Fail instead of calling abort in this case. */ | |
c4ce6853 | 634 | if (GET_CODE (op) != REG) |
61a55e8b | 635 | return 0; |
304b7a23 | 636 | |
c4ce6853 | 637 | if (mode != VOIDmode && mode != GET_MODE (op)) |
61a55e8b | 638 | return 0; |
304b7a23 DE |
639 | if (mode == VOIDmode |
640 | && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) | |
641 | return 0; | |
61a55e8b | 642 | |
c4ce6853 | 643 | #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ |
61a55e8b DE |
644 | if (reg_renumber == 0) |
645 | return REGNO (op) >= FIRST_PSEUDO_REGISTER; | |
646 | return REGNO_OK_FOR_CCFP_P (REGNO (op)); | |
647 | #else | |
c4ce6853 | 648 | return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; |
61a55e8b DE |
649 | #endif |
650 | } | |
651 | ||
0b82d204 JJ |
652 | /* Nonzero if OP is a floating point condition code fcc0 register. */ |
653 | ||
654 | int | |
fc27d102 | 655 | fcc0_reg_operand (rtx op, enum machine_mode mode) |
0b82d204 JJ |
656 | { |
657 | /* This can happen when recog is called from combine. Op may be a MEM. | |
658 | Fail instead of calling abort in this case. */ | |
659 | if (GET_CODE (op) != REG) | |
660 | return 0; | |
661 | ||
662 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
663 | return 0; | |
664 | if (mode == VOIDmode | |
665 | && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) | |
666 | return 0; | |
667 | ||
668 | return REGNO (op) == SPARC_FCC_REG; | |
669 | } | |
670 | ||
c4ce6853 DE |
671 | /* Nonzero if OP is an integer or floating point condition code register. */ |
672 | ||
673 | int | |
fc27d102 | 674 | icc_or_fcc_reg_operand (rtx op, enum machine_mode mode) |
c4ce6853 DE |
675 | { |
676 | if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) | |
304b7a23 DE |
677 | { |
678 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
679 | return 0; | |
680 | if (mode == VOIDmode | |
681 | && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) | |
682 | return 0; | |
683 | return 1; | |
684 | } | |
685 | ||
c4ce6853 DE |
686 | return fcc_reg_operand (op, mode); |
687 | } | |
688 | ||
ab835497 RK |
689 | /* Nonzero if OP can appear as the dest of a RESTORE insn. */ |
690 | int | |
fc27d102 | 691 | restore_operand (rtx op, enum machine_mode mode) |
ab835497 RK |
692 | { |
693 | return (GET_CODE (op) == REG && GET_MODE (op) == mode | |
694 | && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); | |
695 | } | |
696 | ||
401cec23 JW |
697 | /* Call insn on SPARC can take a PC-relative constant address, or any regular |
698 | memory address. */ | |
ab835497 RK |
699 | |
700 | int | |
fc27d102 | 701 | call_operand (rtx op, enum machine_mode mode) |
ab835497 RK |
702 | { |
703 | if (GET_CODE (op) != MEM) | |
704 | abort (); | |
705 | op = XEXP (op, 0); | |
2445f289 | 706 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
707 | } |
708 | ||
709 | int | |
fc27d102 | 710 | call_operand_address (rtx op, enum machine_mode mode) |
ab835497 | 711 | { |
2445f289 | 712 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
713 | } |
714 | ||
5751a10b JJ |
715 | /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode, |
716 | otherwise return 0. */ | |
717 | ||
718 | int | |
719 | tls_symbolic_operand (rtx op) | |
720 | { | |
721 | if (GET_CODE (op) != SYMBOL_REF) | |
722 | return 0; | |
723 | return SYMBOL_REF_TLS_MODEL (op); | |
724 | } | |
725 | ||
726 | int | |
727 | tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
728 | { | |
729 | return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC; | |
730 | } | |
731 | ||
732 | int | |
733 | tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
734 | { | |
735 | return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC; | |
736 | } | |
737 | ||
738 | int | |
739 | tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
740 | { | |
741 | return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC; | |
742 | } | |
743 | ||
744 | int | |
745 | tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
746 | { | |
747 | return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC; | |
748 | } | |
749 | ||
ab835497 RK |
750 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol |
751 | reference and a constant. */ | |
752 | ||
753 | int | |
fc27d102 | 754 | symbolic_operand (register rtx op, enum machine_mode mode) |
ab835497 | 755 | { |
6871dd65 RH |
756 | enum machine_mode omode = GET_MODE (op); |
757 | ||
758 | if (omode != mode && omode != VOIDmode && mode != VOIDmode) | |
759 | return 0; | |
760 | ||
ab835497 RK |
761 | switch (GET_CODE (op)) |
762 | { | |
763 | case SYMBOL_REF: | |
5751a10b JJ |
764 | return !SYMBOL_REF_TLS_MODEL (op); |
765 | ||
ab835497 RK |
766 | case LABEL_REF: |
767 | return 1; | |
768 | ||
769 | case CONST: | |
770 | op = XEXP (op, 0); | |
5751a10b JJ |
771 | return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF |
772 | && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0))) | |
ab835497 RK |
773 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) |
774 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
775 | ||
ab835497 RK |
776 | default: |
777 | return 0; | |
778 | } | |
779 | } | |
780 | ||
781 | /* Return truth value of statement that OP is a symbolic memory | |
782 | operand of mode MODE. */ | |
783 | ||
784 | int | |
fc27d102 | 785 | symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
786 | { |
787 | if (GET_CODE (op) == SUBREG) | |
788 | op = SUBREG_REG (op); | |
789 | if (GET_CODE (op) != MEM) | |
790 | return 0; | |
791 | op = XEXP (op, 0); | |
5751a10b JJ |
792 | return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op)) |
793 | || GET_CODE (op) == CONST || GET_CODE (op) == HIGH | |
794 | || GET_CODE (op) == LABEL_REF); | |
ab835497 RK |
795 | } |
796 | ||
5ab7138b DE |
797 | /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ |
798 | ||
799 | int | |
fc27d102 | 800 | label_ref_operand (rtx op, enum machine_mode mode) |
5ab7138b DE |
801 | { |
802 | if (GET_CODE (op) != LABEL_REF) | |
803 | return 0; | |
804 | if (GET_MODE (op) != mode) | |
805 | return 0; | |
806 | return 1; | |
807 | } | |
808 | ||
95726648 DE |
809 | /* Return 1 if the operand is an argument used in generating pic references |
810 | in either the medium/low or medium/anywhere code models of sparc64. */ | |
811 | ||
812 | int | |
fc27d102 | 813 | sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
95726648 DE |
814 | { |
815 | /* Check for (const (minus (symbol_ref:GOT) | |
816 | (const (minus (label) (pc))))). */ | |
817 | if (GET_CODE (op) != CONST) | |
818 | return 0; | |
819 | op = XEXP (op, 0); | |
820 | if (GET_CODE (op) != MINUS) | |
821 | return 0; | |
822 | if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) | |
823 | return 0; | |
824 | /* ??? Ensure symbol is GOT. */ | |
825 | if (GET_CODE (XEXP (op, 1)) != CONST) | |
826 | return 0; | |
827 | if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) | |
828 | return 0; | |
829 | return 1; | |
830 | } | |
831 | ||
61a55e8b DE |
832 | /* Return 1 if the operand is a data segment reference. This includes |
833 | the readonly data segment, or in other words anything but the text segment. | |
834 | This is needed in the medium/anywhere code model on v9. These values | |
a0a301fc | 835 | are accessed with EMBMEDANY_BASE_REG. */ |
61a55e8b DE |
836 | |
837 | int | |
fc27d102 | 838 | data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
61a55e8b DE |
839 | { |
840 | switch (GET_CODE (op)) | |
841 | { | |
842 | case SYMBOL_REF : | |
72628c61 | 843 | return ! SYMBOL_REF_FUNCTION_P (op); |
61a55e8b | 844 | case PLUS : |
95726648 DE |
845 | /* Assume canonical format of symbol + constant. |
846 | Fall through. */ | |
61a55e8b | 847 | case CONST : |
b1474bb7 | 848 | return data_segment_operand (XEXP (op, 0), VOIDmode); |
61a55e8b DE |
849 | default : |
850 | return 0; | |
851 | } | |
852 | } | |
853 | ||
854 | /* Return 1 if the operand is a text segment reference. | |
855 | This is needed in the medium/anywhere code model on v9. */ | |
856 | ||
857 | int | |
fc27d102 | 858 | text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
61a55e8b DE |
859 | { |
860 | switch (GET_CODE (op)) | |
861 | { | |
862 | case LABEL_REF : | |
863 | return 1; | |
864 | case SYMBOL_REF : | |
72628c61 | 865 | return SYMBOL_REF_FUNCTION_P (op); |
61a55e8b | 866 | case PLUS : |
95726648 DE |
867 | /* Assume canonical format of symbol + constant. |
868 | Fall through. */ | |
61a55e8b | 869 | case CONST : |
b1474bb7 | 870 | return text_segment_operand (XEXP (op, 0), VOIDmode); |
61a55e8b DE |
871 | default : |
872 | return 0; | |
873 | } | |
874 | } | |
875 | ||
ab835497 RK |
876 | /* Return 1 if the operand is either a register or a memory operand that is |
877 | not symbolic. */ | |
878 | ||
879 | int | |
fc27d102 | 880 | reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode) |
ab835497 RK |
881 | { |
882 | if (register_operand (op, mode)) | |
883 | return 1; | |
884 | ||
885 | if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) | |
886 | return 1; | |
887 | ||
888 | return 0; | |
889 | } | |
890 | ||
ab835497 | 891 | int |
fc27d102 KG |
892 | splittable_symbolic_memory_operand (rtx op, |
893 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
ab835497 | 894 | { |
6ac34277 DE |
895 | if (GET_CODE (op) != MEM) |
896 | return 0; | |
897 | if (! symbolic_operand (XEXP (op, 0), Pmode)) | |
898 | return 0; | |
899 | return 1; | |
900 | } | |
901 | ||
902 | int | |
fc27d102 KG |
903 | splittable_immediate_memory_operand (rtx op, |
904 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
6ac34277 DE |
905 | { |
906 | if (GET_CODE (op) != MEM) | |
907 | return 0; | |
908 | if (! immediate_operand (XEXP (op, 0), Pmode)) | |
909 | return 0; | |
910 | return 1; | |
ab835497 RK |
911 | } |
912 | ||
913 | /* Return truth value of whether OP is EQ or NE. */ | |
914 | ||
915 | int | |
fc27d102 | 916 | eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
917 | { |
918 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
919 | } | |
920 | ||
921 | /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, | |
922 | or LTU for non-floating-point. We handle those specially. */ | |
923 | ||
924 | int | |
fc27d102 | 925 | normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
926 | { |
927 | enum rtx_code code = GET_CODE (op); | |
928 | ||
929 | if (GET_RTX_CLASS (code) != '<') | |
930 | return 0; | |
931 | ||
4d449554 JW |
932 | if (GET_MODE (XEXP (op, 0)) == CCFPmode |
933 | || GET_MODE (XEXP (op, 0)) == CCFPEmode) | |
ab835497 RK |
934 | return 1; |
935 | ||
936 | return (code != NE && code != EQ && code != GEU && code != LTU); | |
937 | } | |
938 | ||
939 | /* Return 1 if this is a comparison operator. This allows the use of | |
940 | MATCH_OPERATOR to recognize all the branch insns. */ | |
941 | ||
942 | int | |
fc27d102 | 943 | noov_compare_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
944 | { |
945 | enum rtx_code code = GET_CODE (op); | |
946 | ||
947 | if (GET_RTX_CLASS (code) != '<') | |
948 | return 0; | |
949 | ||
0b82d204 JJ |
950 | if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode |
951 | || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) | |
ab835497 RK |
952 | /* These are the only branches which work with CC_NOOVmode. */ |
953 | return (code == EQ || code == NE || code == GE || code == LT); | |
954 | return 1; | |
955 | } | |
956 | ||
0b82d204 JJ |
957 | /* Return 1 if this is a 64-bit comparison operator. This allows the use of |
958 | MATCH_OPERATOR to recognize all the branch insns. */ | |
959 | ||
960 | int | |
fc27d102 | 961 | noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0b82d204 JJ |
962 | { |
963 | enum rtx_code code = GET_CODE (op); | |
964 | ||
965 | if (! TARGET_V9) | |
966 | return 0; | |
967 | ||
968 | if (GET_RTX_CLASS (code) != '<') | |
969 | return 0; | |
970 | ||
971 | if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) | |
972 | /* These are the only branches which work with CCX_NOOVmode. */ | |
973 | return (code == EQ || code == NE || code == GE || code == LT); | |
974 | return (GET_MODE (XEXP (op, 0)) == CCXmode); | |
975 | } | |
976 | ||
61a55e8b DE |
977 | /* Nonzero if OP is a comparison operator suitable for use in v9 |
978 | conditional move or branch on register contents instructions. */ | |
979 | ||
980 | int | |
fc27d102 | 981 | v9_regcmp_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
61a55e8b DE |
982 | { |
983 | enum rtx_code code = GET_CODE (op); | |
984 | ||
985 | if (GET_RTX_CLASS (code) != '<') | |
986 | return 0; | |
987 | ||
cd5fb1ee | 988 | return v9_regcmp_p (code); |
61a55e8b DE |
989 | } |
990 | ||
ab835497 RK |
991 | /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ |
992 | ||
993 | int | |
fc27d102 | 994 | extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
995 | { |
996 | return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; | |
997 | } | |
998 | ||
999 | /* Return nonzero if OP is an operator of mode MODE which can set | |
1000 | the condition codes explicitly. We do not include PLUS and MINUS | |
1001 | because these require CC_NOOVmode, which we handle explicitly. */ | |
1002 | ||
1003 | int | |
fc27d102 | 1004 | cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
1005 | { |
1006 | if (GET_CODE (op) == AND | |
1007 | || GET_CODE (op) == IOR | |
1008 | || GET_CODE (op) == XOR) | |
1009 | return 1; | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | /* Return nonzero if OP is an operator of mode MODE which can bitwise | |
1015 | complement its second operand and set the condition codes explicitly. */ | |
1016 | ||
1017 | int | |
fc27d102 | 1018 | cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
1019 | { |
1020 | /* XOR is not here because combine canonicalizes (xor (not ...) ...) | |
80ffc95e | 1021 | and (xor ... (not ...)) to (not (xor ...)). */ |
ab835497 RK |
1022 | return (GET_CODE (op) == AND |
1023 | || GET_CODE (op) == IOR); | |
1024 | } | |
1025 | \f | |
58cbf20e DE |
1026 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
1027 | signed 13 bit immediate field. This is an acceptable SImode operand for | |
1028 | most 3 address instructions. */ | |
ab835497 RK |
1029 | |
1030 | int | |
fc27d102 | 1031 | arith_operand (rtx op, enum machine_mode mode) |
ab835497 | 1032 | { |
11301057 | 1033 | if (register_operand (op, mode)) |
284d86e9 JC |
1034 | return 1; |
1035 | if (GET_CODE (op) != CONST_INT) | |
1036 | return 0; | |
9e0625a3 | 1037 | return SMALL_INT32 (op); |
ab835497 RK |
1038 | } |
1039 | ||
5d6d3339 JJ |
1040 | /* Return true if OP is a constant 4096 */ |
1041 | ||
1042 | int | |
fc27d102 | 1043 | arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
5d6d3339 | 1044 | { |
5d6d3339 JJ |
1045 | if (GET_CODE (op) != CONST_INT) |
1046 | return 0; | |
3070dd00 KG |
1047 | else |
1048 | return INTVAL (op) == 4096; | |
5d6d3339 JJ |
1049 | } |
1050 | ||
1051 | /* Return true if OP is suitable as second operand for add/sub */ | |
1052 | ||
1053 | int | |
fc27d102 | 1054 | arith_add_operand (rtx op, enum machine_mode mode) |
5d6d3339 JJ |
1055 | { |
1056 | return arith_operand (op, mode) || arith_4096_operand (op, mode); | |
1057 | } | |
1058 | ||
89e65674 DM |
1059 | /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the |
1060 | immediate field of OR and XOR instructions. Used for 64-bit | |
1061 | constant formation patterns. */ | |
1062 | int | |
fc27d102 | 1063 | const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
89e65674 DM |
1064 | { |
1065 | return ((GET_CODE (op) == CONST_INT | |
1066 | && SPARC_SIMM13_P (INTVAL (op))) | |
9208e4b2 | 1067 | #if HOST_BITS_PER_WIDE_INT != 64 |
89e65674 | 1068 | || (GET_CODE (op) == CONST_DOUBLE |
9208e4b2 DM |
1069 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) |
1070 | && (CONST_DOUBLE_HIGH (op) == | |
1071 | ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? | |
9e0625a3 | 1072 | (HOST_WIDE_INT)-1 : 0))) |
9208e4b2 | 1073 | #endif |
11301057 | 1074 | ); |
89e65674 DM |
1075 | } |
1076 | ||
9208e4b2 | 1077 | /* The same, but only for sethi instructions. */ |
89e65674 | 1078 | int |
fc27d102 | 1079 | const64_high_operand (rtx op, enum machine_mode mode) |
89e65674 DM |
1080 | { |
1081 | return ((GET_CODE (op) == CONST_INT | |
9e0625a3 | 1082 | && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0 |
7d6040e8 | 1083 | && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) |
9208e4b2 | 1084 | ) |
89e65674 DM |
1085 | || (GET_CODE (op) == CONST_DOUBLE |
1086 | && CONST_DOUBLE_HIGH (op) == 0 | |
9e0625a3 | 1087 | && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0 |
11301057 | 1088 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))); |
89e65674 DM |
1089 | } |
1090 | ||
58cbf20e DE |
1091 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
1092 | signed 11 bit immediate field. This is an acceptable SImode operand for | |
1093 | the movcc instructions. */ | |
61a55e8b DE |
1094 | |
1095 | int | |
fc27d102 | 1096 | arith11_operand (rtx op, enum machine_mode mode) |
61a55e8b DE |
1097 | { |
1098 | return (register_operand (op, mode) | |
58cbf20e | 1099 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); |
61a55e8b DE |
1100 | } |
1101 | ||
58cbf20e DE |
1102 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
1103 | signed 10 bit immediate field. This is an acceptable SImode operand for | |
1104 | the movrcc instructions. */ | |
61a55e8b DE |
1105 | |
1106 | int | |
fc27d102 | 1107 | arith10_operand (rtx op, enum machine_mode mode) |
61a55e8b DE |
1108 | { |
1109 | return (register_operand (op, mode) | |
58cbf20e | 1110 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); |
61a55e8b DE |
1111 | } |
1112 | ||
23b8a89f JW |
1113 | /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit |
1114 | immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit | |
61a55e8b DE |
1115 | immediate field. |
1116 | v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
1117 | can fit in a 13 bit immediate field. This is an acceptable DImode operand | |
1118 | for most 3 address instructions. */ | |
ab835497 RK |
1119 | |
1120 | int | |
fc27d102 | 1121 | arith_double_operand (rtx op, enum machine_mode mode) |
ab835497 RK |
1122 | { |
1123 | return (register_operand (op, mode) | |
23b8a89f | 1124 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) |
a9e27770 | 1125 | || (! TARGET_ARCH64 |
61a55e8b | 1126 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 DE |
1127 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
1128 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) | |
a9e27770 | 1129 | || (TARGET_ARCH64 |
61a55e8b | 1130 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 | 1131 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
61a55e8b DE |
1132 | && ((CONST_DOUBLE_HIGH (op) == -1 |
1133 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) | |
1134 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1135 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); | |
1136 | } | |
1137 | ||
5d6d3339 JJ |
1138 | /* Return true if OP is a constant 4096 for DImode on ARCH64 */ |
1139 | ||
1140 | int | |
fc27d102 | 1141 | arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
5d6d3339 JJ |
1142 | { |
1143 | return (TARGET_ARCH64 && | |
1144 | ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || | |
1145 | (GET_CODE (op) == CONST_DOUBLE && | |
1146 | CONST_DOUBLE_LOW (op) == 4096 && | |
1147 | CONST_DOUBLE_HIGH (op) == 0))); | |
1148 | } | |
1149 | ||
1150 | /* Return true if OP is suitable as second operand for add/sub in DImode */ | |
1151 | ||
1152 | int | |
fc27d102 | 1153 | arith_double_add_operand (rtx op, enum machine_mode mode) |
5d6d3339 JJ |
1154 | { |
1155 | return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode); | |
1156 | } | |
1157 | ||
61a55e8b DE |
1158 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that |
1159 | can fit in an 11 bit immediate field. This is an acceptable DImode | |
1160 | operand for the movcc instructions. */ | |
1161 | /* ??? Replace with arith11_operand? */ | |
1162 | ||
1163 | int | |
fc27d102 | 1164 | arith11_double_operand (rtx op, enum machine_mode mode) |
61a55e8b DE |
1165 | { |
1166 | return (register_operand (op, mode) | |
1167 | || (GET_CODE (op) == CONST_DOUBLE | |
1168 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1169 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 |
61a55e8b DE |
1170 | && ((CONST_DOUBLE_HIGH (op) == -1 |
1171 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) | |
1172 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1173 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) | |
1174 | || (GET_CODE (op) == CONST_INT | |
1175 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1176 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800)); |
61a55e8b DE |
1177 | } |
1178 | ||
1179 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
1180 | can fit in an 10 bit immediate field. This is an acceptable DImode | |
1181 | operand for the movrcc instructions. */ | |
1182 | /* ??? Replace with arith10_operand? */ | |
1183 | ||
1184 | int | |
fc27d102 | 1185 | arith10_double_operand (rtx op, enum machine_mode mode) |
61a55e8b DE |
1186 | { |
1187 | return (register_operand (op, mode) | |
1188 | || (GET_CODE (op) == CONST_DOUBLE | |
1189 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
1190 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 | |
1191 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
1192 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) | |
1193 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1194 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) | |
1195 | || (GET_CODE (op) == CONST_INT | |
1196 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1197 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400)); |
ab835497 RK |
1198 | } |
1199 | ||
5519a4f9 | 1200 | /* Return truth value of whether OP is an integer which fits the |
228b4037 JW |
1201 | range constraining immediate operands in most three-address insns, |
1202 | which have a 13 bit immediate field. */ | |
ab835497 RK |
1203 | |
1204 | int | |
fc27d102 | 1205 | small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 | 1206 | { |
11301057 | 1207 | return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); |
ab835497 RK |
1208 | } |
1209 | ||
e0d80184 | 1210 | int |
fc27d102 | 1211 | small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
e0d80184 DM |
1212 | { |
1213 | return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) | |
1214 | || (GET_CODE (op) == CONST_DOUBLE | |
1215 | && CONST_DOUBLE_HIGH (op) == 0 | |
11301057 | 1216 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))); |
e0d80184 DM |
1217 | } |
1218 | ||
9b3fad96 JW |
1219 | /* Recognize operand values for the umul instruction. That instruction sign |
1220 | extends immediate values just like all other sparc instructions, but | |
1221 | interprets the extended result as an unsigned number. */ | |
1222 | ||
1223 | int | |
fc27d102 | 1224 | uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9b3fad96 JW |
1225 | { |
1226 | #if HOST_BITS_PER_WIDE_INT > 32 | |
1227 | /* All allowed constants will fit a CONST_INT. */ | |
11301057 RH |
1228 | return (GET_CODE (op) == CONST_INT |
1229 | && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) | |
1230 | || (INTVAL (op) >= 0xFFFFF000 | |
0d587737 | 1231 | && INTVAL (op) <= 0xFFFFFFFF))); |
9b3fad96 | 1232 | #else |
11301057 RH |
1233 | return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) |
1234 | || (GET_CODE (op) == CONST_DOUBLE | |
1235 | && CONST_DOUBLE_HIGH (op) == 0 | |
1236 | && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); | |
9b3fad96 JW |
1237 | #endif |
1238 | } | |
1239 | ||
1240 | int | |
fc27d102 | 1241 | uns_arith_operand (rtx op, enum machine_mode mode) |
9b3fad96 JW |
1242 | { |
1243 | return register_operand (op, mode) || uns_small_int (op, mode); | |
1244 | } | |
1245 | ||
ab835497 RK |
1246 | /* Return truth value of statement that OP is a call-clobbered register. */ |
1247 | int | |
fc27d102 | 1248 | clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ab835497 RK |
1249 | { |
1250 | return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); | |
1251 | } | |
ab835497 | 1252 | |
e0d80184 | 1253 | /* Return 1 if OP is a valid operand for the source of a move insn. */ |
61a55e8b | 1254 | |
e0d80184 | 1255 | int |
fc27d102 | 1256 | input_operand (rtx op, enum machine_mode mode) |
e0d80184 DM |
1257 | { |
1258 | /* If both modes are non-void they must be the same. */ | |
1259 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) | |
1260 | return 0; | |
61a55e8b | 1261 | |
375ffbe6 EB |
1262 | /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */ |
1263 | if (GET_CODE (op) == CONSTANT_P_RTX) | |
11301057 RH |
1264 | return 1; |
1265 | ||
e0d80184 DM |
1266 | /* Allow any one instruction integer constant, and all CONST_INT |
1267 | variants when we are working in DImode and !arch64. */ | |
1268 | if (GET_MODE_CLASS (mode) == MODE_INT | |
9208e4b2 | 1269 | && ((GET_CODE (op) == CONST_INT |
7d6040e8 | 1270 | && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) |
9208e4b2 DM |
1271 | || SPARC_SIMM13_P (INTVAL (op)) |
1272 | || (mode == DImode | |
1273 | && ! TARGET_ARCH64))) | |
1274 | || (TARGET_ARCH64 | |
1275 | && GET_CODE (op) == CONST_DOUBLE | |
1276 | && ((CONST_DOUBLE_HIGH (op) == 0 | |
1277 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) | |
1278 | || | |
1279 | #if HOST_BITS_PER_WIDE_INT == 64 | |
1280 | (CONST_DOUBLE_HIGH (op) == 0 | |
1281 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) | |
1282 | #else | |
1283 | (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) | |
1284 | && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0 | |
1285 | && CONST_DOUBLE_HIGH (op) == 0) | |
4746e0fe RK |
1286 | || (CONST_DOUBLE_HIGH (op) == -1 |
1287 | && CONST_DOUBLE_LOW (op) & 0x80000000) != 0)) | |
9208e4b2 DM |
1288 | #endif |
1289 | )))) | |
e0d80184 DM |
1290 | return 1; |
1291 | ||
e0d80184 DM |
1292 | /* If !arch64 and this is a DImode const, allow it so that |
1293 | the splits can be generated. */ | |
1294 | if (! TARGET_ARCH64 | |
1295 | && mode == DImode | |
1296 | && GET_CODE (op) == CONST_DOUBLE) | |
1297 | return 1; | |
1298 | ||
1299 | if (register_operand (op, mode)) | |
1300 | return 1; | |
1301 | ||
62190128 DM |
1302 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1303 | && GET_CODE (op) == CONST_DOUBLE) | |
1304 | return 1; | |
1305 | ||
e0d80184 DM |
1306 | /* If this is a SUBREG, look inside so that we handle |
1307 | paradoxical ones. */ | |
1308 | if (GET_CODE (op) == SUBREG) | |
1309 | op = SUBREG_REG (op); | |
1310 | ||
1311 | /* Check for valid MEM forms. */ | |
1312 | if (GET_CODE (op) == MEM) | |
61a55e8b | 1313 | { |
e0d80184 | 1314 | rtx inside = XEXP (op, 0); |
61a55e8b | 1315 | |
e0d80184 | 1316 | if (GET_CODE (inside) == LO_SUM) |
03ad6f4d DM |
1317 | { |
1318 | /* We can't allow these because all of the splits | |
1319 | (eventually as they trickle down into DFmode | |
1320 | splits) require offsettable memory references. */ | |
1321 | if (! TARGET_V9 | |
1322 | && GET_MODE (op) == TFmode) | |
1323 | return 0; | |
1324 | ||
1325 | return (register_operand (XEXP (inside, 0), Pmode) | |
1326 | && CONSTANT_P (XEXP (inside, 1))); | |
1327 | } | |
e0d80184 | 1328 | return memory_address_p (mode, inside); |
61a55e8b | 1329 | } |
ab835497 | 1330 | |
e0d80184 DM |
1331 | return 0; |
1332 | } | |
1333 | ||
1334 | \f | |
1335 | /* We know it can't be done in one insn when we get here, | |
fae778eb | 1336 | the movsi expander guarantees this. */ |
e0d80184 | 1337 | void |
fc27d102 | 1338 | sparc_emit_set_const32 (rtx op0, rtx op1) |
e0d80184 DM |
1339 | { |
1340 | enum machine_mode mode = GET_MODE (op0); | |
1341 | rtx temp; | |
1342 | ||
1343 | if (GET_CODE (op1) == CONST_INT) | |
284d86e9 | 1344 | { |
2a01c939 | 1345 | HOST_WIDE_INT value = INTVAL (op1); |
e0d80184 | 1346 | |
7d6040e8 | 1347 | if (SPARC_SETHI_P (value & GET_MODE_MASK (mode)) |
e0d80184 DM |
1348 | || SPARC_SIMM13_P (value)) |
1349 | abort (); | |
284d86e9 | 1350 | } |
e0d80184 DM |
1351 | |
1352 | /* Full 2-insn decomposition is needed. */ | |
1353 | if (reload_in_progress || reload_completed) | |
1354 | temp = op0; | |
284d86e9 | 1355 | else |
e0d80184 DM |
1356 | temp = gen_reg_rtx (mode); |
1357 | ||
71648202 DM |
1358 | if (GET_CODE (op1) == CONST_INT) |
1359 | { | |
1360 | /* Emit them as real moves instead of a HIGH/LO_SUM, | |
1361 | this way CSE can see everything and reuse intermediate | |
1362 | values if it wants. */ | |
1363 | if (TARGET_ARCH64 | |
1364 | && HOST_BITS_PER_WIDE_INT != 64 | |
1365 | && (INTVAL (op1) & 0x80000000) != 0) | |
f2827474 RK |
1366 | emit_insn (gen_rtx_SET |
1367 | (VOIDmode, temp, | |
5692c7bc ZW |
1368 | immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff, |
1369 | 0, DImode))); | |
71648202 | 1370 | else |
f2827474 | 1371 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
9e0625a3 AO |
1372 | GEN_INT (INTVAL (op1) |
1373 | & ~(HOST_WIDE_INT)0x3ff))); | |
f2827474 | 1374 | |
71648202 DM |
1375 | emit_insn (gen_rtx_SET (VOIDmode, |
1376 | op0, | |
f2827474 | 1377 | gen_rtx_IOR (mode, temp, |
71648202 DM |
1378 | GEN_INT (INTVAL (op1) & 0x3ff)))); |
1379 | } | |
1380 | else | |
1381 | { | |
1382 | /* A symbol, emit in the traditional way. */ | |
f2827474 RK |
1383 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
1384 | gen_rtx_HIGH (mode, op1))); | |
71648202 | 1385 | emit_insn (gen_rtx_SET (VOIDmode, |
f2827474 | 1386 | op0, gen_rtx_LO_SUM (mode, temp, op1))); |
71648202 DM |
1387 | |
1388 | } | |
e0d80184 DM |
1389 | } |
1390 | ||
1391 | \f | |
56149abc | 1392 | /* SPARC-v9 code-model support. */ |
e0d80184 | 1393 | void |
fc27d102 | 1394 | sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp1) |
e0d80184 | 1395 | { |
3968de80 DD |
1396 | rtx ti_temp1 = 0; |
1397 | ||
1398 | if (temp1 && GET_MODE (temp1) == TImode) | |
1399 | { | |
1400 | ti_temp1 = temp1; | |
1401 | temp1 = gen_rtx_REG (DImode, REGNO (temp1)); | |
1402 | } | |
1403 | ||
e0d80184 | 1404 | switch (sparc_cmodel) |
284d86e9 | 1405 | { |
e0d80184 DM |
1406 | case CM_MEDLOW: |
1407 | /* The range spanned by all instructions in the object is less | |
1408 | than 2^31 bytes (2GB) and the distance from any instruction | |
1409 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1410 | than 2^31 bytes (2GB). | |
ab835497 | 1411 | |
e0d80184 DM |
1412 | The executable must be in the low 4TB of the virtual address |
1413 | space. | |
61a55e8b | 1414 | |
e0d80184 DM |
1415 | sethi %hi(symbol), %temp |
1416 | or %temp, %lo(symbol), %reg */ | |
9208e4b2 DM |
1417 | emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); |
1418 | emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); | |
e0d80184 | 1419 | break; |
61a55e8b | 1420 | |
e0d80184 DM |
1421 | case CM_MEDMID: |
1422 | /* The range spanned by all instructions in the object is less | |
1423 | than 2^31 bytes (2GB) and the distance from any instruction | |
1424 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1425 | than 2^31 bytes (2GB). | |
1426 | ||
1427 | The executable must be in the low 16TB of the virtual address | |
1428 | space. | |
1429 | ||
1430 | sethi %h44(symbol), %temp1 | |
1431 | or %temp1, %m44(symbol), %temp2 | |
1432 | sllx %temp2, 12, %temp3 | |
1433 | or %temp3, %l44(symbol), %reg */ | |
1434 | emit_insn (gen_seth44 (op0, op1)); | |
1435 | emit_insn (gen_setm44 (op0, op0, op1)); | |
9208e4b2 | 1436 | emit_insn (gen_rtx_SET (VOIDmode, temp1, |
e0d80184 DM |
1437 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (12)))); |
1438 | emit_insn (gen_setl44 (op0, temp1, op1)); | |
1439 | break; | |
61a55e8b | 1440 | |
e0d80184 DM |
1441 | case CM_MEDANY: |
1442 | /* The range spanned by all instructions in the object is less | |
1443 | than 2^31 bytes (2GB) and the distance from any instruction | |
1444 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1445 | than 2^31 bytes (2GB). | |
1446 | ||
1447 | The executable can be placed anywhere in the virtual address | |
1448 | space. | |
1449 | ||
1450 | sethi %hh(symbol), %temp1 | |
1451 | sethi %lm(symbol), %temp2 | |
1452 | or %temp1, %hm(symbol), %temp3 | |
1453 | or %temp2, %lo(symbol), %temp4 | |
1454 | sllx %temp3, 32, %temp5 | |
1455 | or %temp4, %temp5, %reg */ | |
1456 | ||
3968de80 DD |
1457 | /* It is possible that one of the registers we got for operands[2] |
1458 | might coincide with that of operands[0] (which is why we made | |
1459 | it TImode). Pick the other one to use as our scratch. */ | |
6cd444b4 | 1460 | if (rtx_equal_p (temp1, op0)) |
3968de80 DD |
1461 | { |
1462 | if (ti_temp1) | |
1463 | temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1); | |
1464 | else | |
1465 | abort(); | |
1466 | } | |
61a55e8b | 1467 | |
e0d80184 DM |
1468 | emit_insn (gen_sethh (op0, op1)); |
1469 | emit_insn (gen_setlm (temp1, op1)); | |
1470 | emit_insn (gen_sethm (op0, op0, op1)); | |
9208e4b2 | 1471 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1472 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1473 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1474 | gen_rtx_PLUS (DImode, op0, temp1))); |
1475 | emit_insn (gen_setlo (op0, op0, op1)); | |
1476 | break; | |
61a55e8b | 1477 | |
e0d80184 DM |
1478 | case CM_EMBMEDANY: |
1479 | /* Old old old backwards compatibility kruft here. | |
1480 | Essentially it is MEDLOW with a fixed 64-bit | |
1481 | virtual base added to all data segment addresses. | |
1482 | Text-segment stuff is computed like MEDANY, we can't | |
1483 | reuse the code above because the relocation knobs | |
1484 | look different. | |
1485 | ||
1486 | Data segment: sethi %hi(symbol), %temp1 | |
1487 | or %temp1, %lo(symbol), %temp2 | |
1488 | add %temp2, EMBMEDANY_BASE_REG, %reg | |
1489 | ||
1490 | Text segment: sethi %uhi(symbol), %temp1 | |
1491 | sethi %hi(symbol), %temp2 | |
1492 | or %temp1, %ulo(symbol), %temp3 | |
1493 | or %temp2, %lo(symbol), %temp4 | |
1494 | sllx %temp3, 32, %temp5 | |
1495 | or %temp4, %temp5, %reg */ | |
1496 | if (data_segment_operand (op1, GET_MODE (op1))) | |
1497 | { | |
1498 | emit_insn (gen_embmedany_sethi (temp1, op1)); | |
1499 | emit_insn (gen_embmedany_brsum (op0, temp1)); | |
1500 | emit_insn (gen_embmedany_losum (op0, op0, op1)); | |
1501 | } | |
1502 | else | |
1503 | { | |
3968de80 DD |
1504 | /* It is possible that one of the registers we got for operands[2] |
1505 | might coincide with that of operands[0] (which is why we made | |
1506 | it TImode). Pick the other one to use as our scratch. */ | |
1507 | if (rtx_equal_p (temp1, op0)) | |
1508 | { | |
1509 | if (ti_temp1) | |
1510 | temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1); | |
1511 | else | |
1512 | abort(); | |
1513 | } | |
61a55e8b | 1514 | |
e0d80184 DM |
1515 | emit_insn (gen_embmedany_textuhi (op0, op1)); |
1516 | emit_insn (gen_embmedany_texthi (temp1, op1)); | |
1517 | emit_insn (gen_embmedany_textulo (op0, op0, op1)); | |
9208e4b2 | 1518 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1519 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1520 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1521 | gen_rtx_PLUS (DImode, op0, temp1))); |
1522 | emit_insn (gen_embmedany_textlo (op0, op0, op1)); | |
1523 | } | |
1524 | break; | |
1525 | ||
1526 | default: | |
1527 | abort(); | |
1528 | } | |
1529 | } | |
1530 | ||
9208e4b2 DM |
1531 | /* These avoid problems when cross compiling. If we do not |
1532 | go through all this hair then the optimizer will see | |
1533 | invalid REG_EQUAL notes or in some cases none at all. */ | |
e80d5f80 KG |
1534 | static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT); |
1535 | static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT); | |
1536 | static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT); | |
1537 | static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT); | |
9208e4b2 DM |
1538 | |
1539 | #if HOST_BITS_PER_WIDE_INT == 64 | |
9e0625a3 | 1540 | #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff) |
9208e4b2 DM |
1541 | #define GEN_INT64(__x) GEN_INT (__x) |
1542 | #else | |
1543 | #define GEN_HIGHINT64(__x) \ | |
5692c7bc | 1544 | immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode) |
9208e4b2 | 1545 | #define GEN_INT64(__x) \ |
5692c7bc ZW |
1546 | immed_double_const ((__x) & 0xffffffff, \ |
1547 | ((__x) & 0x80000000 ? -1 : 0), DImode) | |
9208e4b2 DM |
1548 | #endif |
1549 | ||
1550 | /* The optimizer is not to assume anything about exactly | |
1551 | which bits are set for a HIGH, they are unspecified. | |
1552 | Unfortunately this leads to many missed optimizations | |
1553 | during CSE. We mask out the non-HIGH bits, and matches | |
1554 | a plain movdi, to alleviate this problem. */ | |
1555 | static void | |
fc27d102 | 1556 | sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val) |
9208e4b2 DM |
1557 | { |
1558 | emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val))); | |
1559 | } | |
2a01c939 | 1560 | |
e0d80184 | 1561 | static rtx |
fc27d102 | 1562 | gen_safe_SET64 (rtx dest, HOST_WIDE_INT val) |
61a55e8b | 1563 | { |
9208e4b2 DM |
1564 | return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val)); |
1565 | } | |
1566 | ||
1567 | static rtx | |
fc27d102 | 1568 | gen_safe_OR64 (rtx src, HOST_WIDE_INT val) |
9208e4b2 DM |
1569 | { |
1570 | return gen_rtx_IOR (DImode, src, GEN_INT64 (val)); | |
1571 | } | |
1572 | ||
1573 | static rtx | |
fc27d102 | 1574 | gen_safe_XOR64 (rtx src, HOST_WIDE_INT val) |
9208e4b2 DM |
1575 | { |
1576 | return gen_rtx_XOR (DImode, src, GEN_INT64 (val)); | |
e0d80184 | 1577 | } |
61a55e8b | 1578 | |
e0d80184 DM |
1579 | /* Worker routines for 64-bit constant formation on arch64. |
1580 | One of the key things to be doing in these emissions is | |
1581 | to create as many temp REGs as possible. This makes it | |
1582 | possible for half-built constants to be used later when | |
1583 | such values are similar to something required later on. | |
1584 | Without doing this, the optimizer cannot see such | |
1585 | opportunities. */ | |
2a01c939 | 1586 | |
e80d5f80 KG |
1587 | static void sparc_emit_set_const64_quick1 (rtx, rtx, |
1588 | unsigned HOST_WIDE_INT, int); | |
2a01c939 | 1589 | |
e0d80184 | 1590 | static void |
fc27d102 KG |
1591 | sparc_emit_set_const64_quick1 (rtx op0, rtx temp, |
1592 | unsigned HOST_WIDE_INT low_bits, int is_neg) | |
e0d80184 | 1593 | { |
2a01c939 | 1594 | unsigned HOST_WIDE_INT high_bits; |
a9e27770 | 1595 | |
e0d80184 | 1596 | if (is_neg) |
2a01c939 | 1597 | high_bits = (~low_bits) & 0xffffffff; |
31bc9eba | 1598 | else |
e0d80184 | 1599 | high_bits = low_bits; |
31bc9eba | 1600 | |
9208e4b2 | 1601 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1602 | if (!is_neg) |
5108f3e5 DM |
1603 | { |
1604 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1605 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
1606 | } | |
e0d80184 | 1607 | else |
5108f3e5 DM |
1608 | { |
1609 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
1610 | instead. This way the combiner will notice logical operations | |
1611 | such as ANDN later on and substitute. */ | |
1612 | if ((low_bits & 0x3ff) == 0x3ff) | |
1613 | { | |
1614 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1615 | gen_rtx_NOT (DImode, temp))); | |
1616 | } | |
1617 | else | |
1618 | { | |
1619 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1620 | gen_safe_XOR64 (temp, | |
9e0625a3 AO |
1621 | (-(HOST_WIDE_INT)0x400 |
1622 | | (low_bits & 0x3ff))))); | |
5108f3e5 DM |
1623 | } |
1624 | } | |
e0d80184 | 1625 | } |
61a55e8b | 1626 | |
e80d5f80 KG |
1627 | static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT, |
1628 | unsigned HOST_WIDE_INT, int); | |
2a01c939 | 1629 | |
e0d80184 | 1630 | static void |
fc27d102 KG |
1631 | sparc_emit_set_const64_quick2 (rtx op0, rtx temp, |
1632 | unsigned HOST_WIDE_INT high_bits, | |
1633 | unsigned HOST_WIDE_INT low_immediate, | |
1634 | int shift_count) | |
e0d80184 DM |
1635 | { |
1636 | rtx temp2 = op0; | |
61a55e8b | 1637 | |
e0d80184 DM |
1638 | if ((high_bits & 0xfffffc00) != 0) |
1639 | { | |
9208e4b2 | 1640 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1641 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 DM |
1642 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1643 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
61a55e8b | 1644 | else |
e0d80184 | 1645 | temp2 = temp; |
61a55e8b DE |
1646 | } |
1647 | else | |
1648 | { | |
f710f868 | 1649 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 DM |
1650 | temp2 = temp; |
1651 | } | |
61a55e8b | 1652 | |
80ffc95e | 1653 | /* Now shift it up into place. */ |
9208e4b2 | 1654 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1655 | gen_rtx_ASHIFT (DImode, temp2, |
1656 | GEN_INT (shift_count)))); | |
61a55e8b | 1657 | |
e0d80184 DM |
1658 | /* If there is a low immediate part piece, finish up by |
1659 | putting that in as well. */ | |
1660 | if (low_immediate != 0) | |
9208e4b2 DM |
1661 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1662 | gen_safe_OR64 (op0, low_immediate))); | |
ab835497 RK |
1663 | } |
1664 | ||
e80d5f80 KG |
1665 | static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT, |
1666 | unsigned HOST_WIDE_INT); | |
2a01c939 | 1667 | |
e0d80184 DM |
1668 | /* Full 64-bit constant decomposition. Even though this is the |
1669 | 'worst' case, we still optimize a few things away. */ | |
1670 | static void | |
fc27d102 KG |
1671 | sparc_emit_set_const64_longway (rtx op0, rtx temp, |
1672 | unsigned HOST_WIDE_INT high_bits, | |
1673 | unsigned HOST_WIDE_INT low_bits) | |
ab835497 | 1674 | { |
e0d80184 | 1675 | rtx sub_temp; |
4bf7135b | 1676 | |
e0d80184 DM |
1677 | if (reload_in_progress || reload_completed) |
1678 | sub_temp = op0; | |
1679 | else | |
1680 | sub_temp = gen_reg_rtx (DImode); | |
1681 | ||
1682 | if ((high_bits & 0xfffffc00) != 0) | |
1683 | { | |
9208e4b2 | 1684 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1685 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 | 1686 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1687 | sub_temp, |
9208e4b2 | 1688 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); |
e0d80184 DM |
1689 | else |
1690 | sub_temp = temp; | |
1691 | } | |
1692 | else | |
ab835497 | 1693 | { |
f710f868 | 1694 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 | 1695 | sub_temp = temp; |
ab835497 | 1696 | } |
4bf7135b | 1697 | |
e0d80184 | 1698 | if (!reload_in_progress && !reload_completed) |
284d86e9 | 1699 | { |
e0d80184 DM |
1700 | rtx temp2 = gen_reg_rtx (DImode); |
1701 | rtx temp3 = gen_reg_rtx (DImode); | |
1702 | rtx temp4 = gen_reg_rtx (DImode); | |
284d86e9 | 1703 | |
9208e4b2 | 1704 | emit_insn (gen_rtx_SET (VOIDmode, temp4, |
e0d80184 DM |
1705 | gen_rtx_ASHIFT (DImode, sub_temp, |
1706 | GEN_INT (32)))); | |
4bf7135b | 1707 | |
9208e4b2 | 1708 | sparc_emit_set_safe_HIGH64 (temp2, low_bits); |
e0d80184 | 1709 | if ((low_bits & ~0xfffffc00) != 0) |
f710f868 DM |
1710 | { |
1711 | emit_insn (gen_rtx_SET (VOIDmode, temp3, | |
1712 | gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); | |
1713 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1714 | gen_rtx_PLUS (DImode, temp4, temp3))); | |
1715 | } | |
1716 | else | |
1717 | { | |
1718 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1719 | gen_rtx_PLUS (DImode, temp4, temp2))); | |
1720 | } | |
284d86e9 | 1721 | } |
e0d80184 DM |
1722 | else |
1723 | { | |
9208e4b2 DM |
1724 | rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); |
1725 | rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); | |
1726 | rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); | |
e0d80184 | 1727 | int to_shift = 12; |
284d86e9 | 1728 | |
e0d80184 DM |
1729 | /* We are in the middle of reload, so this is really |
1730 | painful. However we do still make an attempt to | |
5108f3e5 | 1731 | avoid emitting truly stupid code. */ |
e0d80184 DM |
1732 | if (low1 != const0_rtx) |
1733 | { | |
9208e4b2 | 1734 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1735 | gen_rtx_ASHIFT (DImode, sub_temp, |
2a01c939 | 1736 | GEN_INT (to_shift)))); |
9208e4b2 | 1737 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1738 | gen_rtx_IOR (DImode, op0, low1))); |
1739 | sub_temp = op0; | |
1740 | to_shift = 12; | |
1741 | } | |
1742 | else | |
1743 | { | |
1744 | to_shift += 12; | |
1745 | } | |
1746 | if (low2 != const0_rtx) | |
1747 | { | |
9208e4b2 | 1748 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1749 | gen_rtx_ASHIFT (DImode, sub_temp, |
1750 | GEN_INT (to_shift)))); | |
9208e4b2 | 1751 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1752 | gen_rtx_IOR (DImode, op0, low2))); |
1753 | sub_temp = op0; | |
1754 | to_shift = 8; | |
1755 | } | |
1756 | else | |
1757 | { | |
1758 | to_shift += 8; | |
1759 | } | |
9208e4b2 | 1760 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1761 | gen_rtx_ASHIFT (DImode, sub_temp, |
1762 | GEN_INT (to_shift)))); | |
1763 | if (low3 != const0_rtx) | |
9208e4b2 | 1764 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1765 | gen_rtx_IOR (DImode, op0, low3))); |
80ffc95e | 1766 | /* phew... */ |
e0d80184 | 1767 | } |
284d86e9 JC |
1768 | } |
1769 | ||
80ffc95e | 1770 | /* Analyze a 64-bit constant for certain properties. */ |
e80d5f80 KG |
1771 | static void analyze_64bit_constant (unsigned HOST_WIDE_INT, |
1772 | unsigned HOST_WIDE_INT, | |
1773 | int *, int *, int *); | |
2a01c939 | 1774 | |
e0d80184 | 1775 | static void |
fc27d102 KG |
1776 | analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits, |
1777 | unsigned HOST_WIDE_INT low_bits, | |
1778 | int *hbsp, int *lbsp, int *abbasp) | |
ab835497 | 1779 | { |
e0d80184 DM |
1780 | int lowest_bit_set, highest_bit_set, all_bits_between_are_set; |
1781 | int i; | |
ab835497 | 1782 | |
e0d80184 DM |
1783 | lowest_bit_set = highest_bit_set = -1; |
1784 | i = 0; | |
1785 | do | |
ab835497 | 1786 | { |
e0d80184 DM |
1787 | if ((lowest_bit_set == -1) |
1788 | && ((low_bits >> i) & 1)) | |
1789 | lowest_bit_set = i; | |
1790 | if ((highest_bit_set == -1) | |
1791 | && ((high_bits >> (32 - i - 1)) & 1)) | |
1792 | highest_bit_set = (64 - i - 1); | |
1793 | } | |
1794 | while (++i < 32 | |
1795 | && ((highest_bit_set == -1) | |
1796 | || (lowest_bit_set == -1))); | |
1797 | if (i == 32) | |
1798 | { | |
1799 | i = 0; | |
1800 | do | |
ab835497 | 1801 | { |
e0d80184 DM |
1802 | if ((lowest_bit_set == -1) |
1803 | && ((high_bits >> i) & 1)) | |
1804 | lowest_bit_set = i + 32; | |
1805 | if ((highest_bit_set == -1) | |
1806 | && ((low_bits >> (32 - i - 1)) & 1)) | |
1807 | highest_bit_set = 32 - i - 1; | |
ab835497 | 1808 | } |
e0d80184 DM |
1809 | while (++i < 32 |
1810 | && ((highest_bit_set == -1) | |
1811 | || (lowest_bit_set == -1))); | |
1812 | } | |
1813 | /* If there are no bits set this should have gone out | |
1814 | as one instruction! */ | |
1815 | if (lowest_bit_set == -1 | |
1816 | || highest_bit_set == -1) | |
9208e4b2 | 1817 | abort (); |
e0d80184 DM |
1818 | all_bits_between_are_set = 1; |
1819 | for (i = lowest_bit_set; i <= highest_bit_set; i++) | |
1820 | { | |
1821 | if (i < 32) | |
1822 | { | |
1823 | if ((low_bits & (1 << i)) != 0) | |
1824 | continue; | |
1825 | } | |
1826 | else | |
1827 | { | |
1828 | if ((high_bits & (1 << (i - 32))) != 0) | |
1829 | continue; | |
1830 | } | |
1831 | all_bits_between_are_set = 0; | |
1832 | break; | |
ab835497 | 1833 | } |
e0d80184 DM |
1834 | *hbsp = highest_bit_set; |
1835 | *lbsp = lowest_bit_set; | |
1836 | *abbasp = all_bits_between_are_set; | |
ab835497 | 1837 | } |
6a4bb1fa | 1838 | |
e80d5f80 | 1839 | static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT); |
2a01c939 | 1840 | |
e0d80184 | 1841 | static int |
fc27d102 KG |
1842 | const64_is_2insns (unsigned HOST_WIDE_INT high_bits, |
1843 | unsigned HOST_WIDE_INT low_bits) | |
e0d80184 DM |
1844 | { |
1845 | int highest_bit_set, lowest_bit_set, all_bits_between_are_set; | |
284d86e9 | 1846 | |
e0d80184 | 1847 | if (high_bits == 0 |
f451b552 | 1848 | || high_bits == 0xffffffff) |
e0d80184 | 1849 | return 1; |
6a4bb1fa | 1850 | |
e0d80184 DM |
1851 | analyze_64bit_constant (high_bits, low_bits, |
1852 | &highest_bit_set, &lowest_bit_set, | |
1853 | &all_bits_between_are_set); | |
6a4bb1fa | 1854 | |
f710f868 DM |
1855 | if ((highest_bit_set == 63 |
1856 | || lowest_bit_set == 0) | |
e0d80184 DM |
1857 | && all_bits_between_are_set != 0) |
1858 | return 1; | |
6a4bb1fa | 1859 | |
9208e4b2 DM |
1860 | if ((highest_bit_set - lowest_bit_set) < 21) |
1861 | return 1; | |
1862 | ||
6a4bb1fa DE |
1863 | return 0; |
1864 | } | |
1865 | ||
e80d5f80 KG |
1866 | static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT, |
1867 | unsigned HOST_WIDE_INT, | |
1868 | int, int); | |
2a01c939 DM |
1869 | |
1870 | static unsigned HOST_WIDE_INT | |
fc27d102 KG |
1871 | create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits, |
1872 | unsigned HOST_WIDE_INT low_bits, | |
1873 | int lowest_bit_set, int shift) | |
ab835497 | 1874 | { |
f710f868 | 1875 | HOST_WIDE_INT hi, lo; |
ab835497 | 1876 | |
e0d80184 DM |
1877 | if (lowest_bit_set < 32) |
1878 | { | |
1879 | lo = (low_bits >> lowest_bit_set) << shift; | |
1880 | hi = ((high_bits << (32 - lowest_bit_set)) << shift); | |
1881 | } | |
1882 | else | |
1883 | { | |
1884 | lo = 0; | |
1885 | hi = ((high_bits >> (lowest_bit_set - 32)) << shift); | |
1886 | } | |
1887 | if (hi & lo) | |
9208e4b2 | 1888 | abort (); |
e0d80184 DM |
1889 | return (hi | lo); |
1890 | } | |
ab835497 | 1891 | |
e0d80184 DM |
1892 | /* Here we are sure to be arch64 and this is an integer constant |
1893 | being loaded into a register. Emit the most efficient | |
1894 | insn sequence possible. Detection of all the 1-insn cases | |
1895 | has been done already. */ | |
1896 | void | |
fc27d102 | 1897 | sparc_emit_set_const64 (rtx op0, rtx op1) |
e0d80184 | 1898 | { |
2a01c939 | 1899 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1900 | int lowest_bit_set, highest_bit_set; |
1901 | int all_bits_between_are_set; | |
e0d80184 | 1902 | rtx temp; |
ab835497 | 1903 | |
e0d80184 | 1904 | /* Sanity check that we know what we are working with. */ |
380f6ad3 | 1905 | if (! TARGET_ARCH64) |
9208e4b2 | 1906 | abort (); |
95726648 | 1907 | |
380f6ad3 JJ |
1908 | if (GET_CODE (op0) != SUBREG) |
1909 | { | |
1910 | if (GET_CODE (op0) != REG | |
1911 | || (REGNO (op0) >= SPARC_FIRST_FP_REG | |
1912 | && REGNO (op0) <= SPARC_LAST_V9_FP_REG)) | |
1913 | abort (); | |
1914 | } | |
1915 | ||
f710f868 DM |
1916 | if (reload_in_progress || reload_completed) |
1917 | temp = op0; | |
1918 | else | |
1919 | temp = gen_reg_rtx (DImode); | |
1920 | ||
e0d80184 DM |
1921 | if (GET_CODE (op1) != CONST_DOUBLE |
1922 | && GET_CODE (op1) != CONST_INT) | |
1923 | { | |
5f78aa30 JC |
1924 | sparc_emit_set_symbolic_const64 (op0, op1, temp); |
1925 | return; | |
e0d80184 | 1926 | } |
ab835497 | 1927 | |
e0d80184 DM |
1928 | if (GET_CODE (op1) == CONST_DOUBLE) |
1929 | { | |
1930 | #if HOST_BITS_PER_WIDE_INT == 64 | |
2a01c939 | 1931 | high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff; |
e0d80184 DM |
1932 | low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff; |
1933 | #else | |
1934 | high_bits = CONST_DOUBLE_HIGH (op1); | |
1935 | low_bits = CONST_DOUBLE_LOW (op1); | |
1936 | #endif | |
ab835497 | 1937 | } |
e0d80184 | 1938 | else |
ab835497 | 1939 | { |
e0d80184 | 1940 | #if HOST_BITS_PER_WIDE_INT == 64 |
2a01c939 | 1941 | high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); |
e0d80184 DM |
1942 | low_bits = (INTVAL (op1) & 0xffffffff); |
1943 | #else | |
1944 | high_bits = ((INTVAL (op1) < 0) ? | |
1945 | 0xffffffff : | |
1946 | 0x00000000); | |
1947 | low_bits = INTVAL (op1); | |
1948 | #endif | |
1949 | } | |
ab835497 | 1950 | |
e0d80184 DM |
1951 | /* low_bits bits 0 --> 31 |
1952 | high_bits bits 32 --> 63 */ | |
ab835497 | 1953 | |
e0d80184 DM |
1954 | analyze_64bit_constant (high_bits, low_bits, |
1955 | &highest_bit_set, &lowest_bit_set, | |
1956 | &all_bits_between_are_set); | |
1957 | ||
1958 | /* First try for a 2-insn sequence. */ | |
1959 | ||
1960 | /* These situations are preferred because the optimizer can | |
1961 | * do more things with them: | |
1962 | * 1) mov -1, %reg | |
1963 | * sllx %reg, shift, %reg | |
1964 | * 2) mov -1, %reg | |
1965 | * srlx %reg, shift, %reg | |
1966 | * 3) mov some_small_const, %reg | |
1967 | * sllx %reg, shift, %reg | |
1968 | */ | |
1969 | if (((highest_bit_set == 63 | |
1970 | || lowest_bit_set == 0) | |
1971 | && all_bits_between_are_set != 0) | |
2a01c939 | 1972 | || ((highest_bit_set - lowest_bit_set) < 12)) |
e0d80184 | 1973 | { |
9208e4b2 | 1974 | HOST_WIDE_INT the_const = -1; |
e0d80184 DM |
1975 | int shift = lowest_bit_set; |
1976 | ||
f710f868 DM |
1977 | if ((highest_bit_set != 63 |
1978 | && lowest_bit_set != 0) | |
1979 | || all_bits_between_are_set == 0) | |
ab835497 | 1980 | { |
e0d80184 | 1981 | the_const = |
9208e4b2 | 1982 | create_simple_focus_bits (high_bits, low_bits, |
9208e4b2 | 1983 | lowest_bit_set, 0); |
ab835497 | 1984 | } |
e0d80184 | 1985 | else if (lowest_bit_set == 0) |
9208e4b2 | 1986 | shift = -(63 - highest_bit_set); |
e0d80184 | 1987 | |
f710f868 DM |
1988 | if (! SPARC_SIMM13_P (the_const)) |
1989 | abort (); | |
1990 | ||
9208e4b2 | 1991 | emit_insn (gen_safe_SET64 (temp, the_const)); |
e0d80184 | 1992 | if (shift > 0) |
9208e4b2 | 1993 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 DM |
1994 | op0, |
1995 | gen_rtx_ASHIFT (DImode, | |
1996 | temp, | |
1997 | GEN_INT (shift)))); | |
1998 | else if (shift < 0) | |
9208e4b2 | 1999 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 2000 | op0, |
9208e4b2 | 2001 | gen_rtx_LSHIFTRT (DImode, |
e0d80184 DM |
2002 | temp, |
2003 | GEN_INT (-shift)))); | |
ab835497 RK |
2004 | else |
2005 | abort (); | |
e0d80184 DM |
2006 | return; |
2007 | } | |
ab835497 | 2008 | |
e0d80184 DM |
2009 | /* Now a range of 22 or less bits set somewhere. |
2010 | * 1) sethi %hi(focus_bits), %reg | |
2011 | * sllx %reg, shift, %reg | |
2012 | * 2) sethi %hi(focus_bits), %reg | |
2013 | * srlx %reg, shift, %reg | |
2014 | */ | |
2a01c939 | 2015 | if ((highest_bit_set - lowest_bit_set) < 21) |
e0d80184 | 2016 | { |
2a01c939 | 2017 | unsigned HOST_WIDE_INT focus_bits = |
e0d80184 | 2018 | create_simple_focus_bits (high_bits, low_bits, |
ddf80874 | 2019 | lowest_bit_set, 10); |
f710f868 DM |
2020 | |
2021 | if (! SPARC_SETHI_P (focus_bits)) | |
2022 | abort (); | |
2023 | ||
9208e4b2 | 2024 | sparc_emit_set_safe_HIGH64 (temp, focus_bits); |
e0d80184 | 2025 | |
9208e4b2 | 2026 | /* If lowest_bit_set == 10 then a sethi alone could have done it. */ |
e0d80184 | 2027 | if (lowest_bit_set < 10) |
9208e4b2 | 2028 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 2029 | op0, |
9208e4b2 | 2030 | gen_rtx_LSHIFTRT (DImode, temp, |
e0d80184 | 2031 | GEN_INT (10 - lowest_bit_set)))); |
9208e4b2 DM |
2032 | else if (lowest_bit_set > 10) |
2033 | emit_insn (gen_rtx_SET (VOIDmode, | |
e0d80184 DM |
2034 | op0, |
2035 | gen_rtx_ASHIFT (DImode, temp, | |
2036 | GEN_INT (lowest_bit_set - 10)))); | |
2037 | else | |
9208e4b2 | 2038 | abort (); |
e0d80184 DM |
2039 | return; |
2040 | } | |
2041 | ||
2042 | /* 1) sethi %hi(low_bits), %reg | |
2043 | * or %reg, %lo(low_bits), %reg | |
2044 | * 2) sethi %hi(~low_bits), %reg | |
2045 | * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg | |
2046 | */ | |
2047 | if (high_bits == 0 | |
2a01c939 | 2048 | || high_bits == 0xffffffff) |
5f78aa30 JC |
2049 | { |
2050 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, | |
2051 | (high_bits == 0xffffffff)); | |
2052 | return; | |
2053 | } | |
e0d80184 | 2054 | |
f710f868 DM |
2055 | /* Now, try 3-insn sequences. */ |
2056 | ||
e0d80184 DM |
2057 | /* 1) sethi %hi(high_bits), %reg |
2058 | * or %reg, %lo(high_bits), %reg | |
2059 | * sllx %reg, 32, %reg | |
2060 | */ | |
f710f868 | 2061 | if (low_bits == 0) |
5f78aa30 | 2062 | { |
f710f868 | 2063 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); |
5f78aa30 JC |
2064 | return; |
2065 | } | |
e0d80184 | 2066 | |
f710f868 DM |
2067 | /* We may be able to do something quick |
2068 | when the constant is negated, so try that. */ | |
e0d80184 DM |
2069 | if (const64_is_2insns ((~high_bits) & 0xffffffff, |
2070 | (~low_bits) & 0xfffffc00)) | |
2071 | { | |
5108f3e5 DM |
2072 | /* NOTE: The trailing bits get XOR'd so we need the |
2073 | non-negated bits, not the negated ones. */ | |
2074 | unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; | |
e0d80184 DM |
2075 | |
2076 | if ((((~high_bits) & 0xffffffff) == 0 | |
2077 | && ((~low_bits) & 0x80000000) == 0) | |
2078 | || (((~high_bits) & 0xffffffff) == 0xffffffff | |
2079 | && ((~low_bits) & 0x80000000) != 0)) | |
ab835497 | 2080 | { |
5108f3e5 | 2081 | int fast_int = (~low_bits & 0xffffffff); |
e0d80184 | 2082 | |
5108f3e5 DM |
2083 | if ((SPARC_SETHI_P (fast_int) |
2084 | && (~high_bits & 0xffffffff) == 0) | |
2085 | || SPARC_SIMM13_P (fast_int)) | |
9208e4b2 | 2086 | emit_insn (gen_safe_SET64 (temp, fast_int)); |
ab835497 | 2087 | else |
9208e4b2 | 2088 | sparc_emit_set_const64 (temp, GEN_INT64 (fast_int)); |
ab835497 | 2089 | } |
e0d80184 DM |
2090 | else |
2091 | { | |
2092 | rtx negated_const; | |
2093 | #if HOST_BITS_PER_WIDE_INT == 64 | |
2094 | negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | | |
2095 | (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); | |
2096 | #else | |
5692c7bc ZW |
2097 | negated_const = immed_double_const ((~low_bits) & 0xfffffc00, |
2098 | (~high_bits) & 0xffffffff, | |
2099 | DImode); | |
e0d80184 DM |
2100 | #endif |
2101 | sparc_emit_set_const64 (temp, negated_const); | |
2102 | } | |
5108f3e5 DM |
2103 | |
2104 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
2105 | instead. This way the combiner will notice logical operations | |
2106 | such as ANDN later on and substitute. */ | |
2107 | if (trailing_bits == 0x3ff) | |
2108 | { | |
2109 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
2110 | gen_rtx_NOT (DImode, temp))); | |
2111 | } | |
2112 | else | |
2113 | { | |
2114 | emit_insn (gen_rtx_SET (VOIDmode, | |
2115 | op0, | |
2116 | gen_safe_XOR64 (temp, | |
2117 | (-0x400 | trailing_bits)))); | |
2118 | } | |
e0d80184 | 2119 | return; |
ab835497 | 2120 | } |
ab835497 | 2121 | |
e0d80184 DM |
2122 | /* 1) sethi %hi(xxx), %reg |
2123 | * or %reg, %lo(xxx), %reg | |
2124 | * sllx %reg, yyy, %reg | |
f710f868 DM |
2125 | * |
2126 | * ??? This is just a generalized version of the low_bits==0 | |
2127 | * thing above, FIXME... | |
e0d80184 DM |
2128 | */ |
2129 | if ((highest_bit_set - lowest_bit_set) < 32) | |
2130 | { | |
f710f868 DM |
2131 | unsigned HOST_WIDE_INT focus_bits = |
2132 | create_simple_focus_bits (high_bits, low_bits, | |
ddf80874 | 2133 | lowest_bit_set, 0); |
ab835497 | 2134 | |
e0d80184 DM |
2135 | /* We can't get here in this state. */ |
2136 | if (highest_bit_set < 32 | |
2137 | || lowest_bit_set >= 32) | |
9208e4b2 | 2138 | abort (); |
95726648 | 2139 | |
e0d80184 DM |
2140 | /* So what we know is that the set bits straddle the |
2141 | middle of the 64-bit word. */ | |
5f78aa30 JC |
2142 | sparc_emit_set_const64_quick2 (op0, temp, |
2143 | focus_bits, 0, | |
2144 | lowest_bit_set); | |
2145 | return; | |
e0d80184 | 2146 | } |
c85f7c16 | 2147 | |
f710f868 DM |
2148 | /* 1) sethi %hi(high_bits), %reg |
2149 | * or %reg, %lo(high_bits), %reg | |
2150 | * sllx %reg, 32, %reg | |
2151 | * or %reg, low_bits, %reg | |
2152 | */ | |
2153 | if (SPARC_SIMM13_P(low_bits) | |
2154 | && ((int)low_bits > 0)) | |
2155 | { | |
2156 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); | |
2157 | return; | |
2158 | } | |
2159 | ||
80ffc95e | 2160 | /* The easiest way when all else fails, is full decomposition. */ |
e0d80184 DM |
2161 | #if 0 |
2162 | printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", | |
2163 | high_bits, low_bits, ~high_bits, ~low_bits); | |
2164 | #endif | |
2165 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); | |
c85f7c16 JL |
2166 | } |
2167 | ||
e267e177 RH |
2168 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
2169 | return the mode to be used for the comparison. For floating-point, | |
2170 | CCFP[E]mode is used. CC_NOOVmode should be used when the first operand | |
2171 | is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special | |
2172 | processing is needed. */ | |
2173 | ||
2174 | enum machine_mode | |
fc27d102 | 2175 | select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED) |
e267e177 RH |
2176 | { |
2177 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2178 | { | |
2179 | switch (op) | |
2180 | { | |
2181 | case EQ: | |
2182 | case NE: | |
2183 | case UNORDERED: | |
2184 | case ORDERED: | |
2185 | case UNLT: | |
2186 | case UNLE: | |
2187 | case UNGT: | |
2188 | case UNGE: | |
2189 | case UNEQ: | |
7913f3d0 | 2190 | case LTGT: |
e267e177 RH |
2191 | return CCFPmode; |
2192 | ||
2193 | case LT: | |
2194 | case LE: | |
2195 | case GT: | |
2196 | case GE: | |
2197 | return CCFPEmode; | |
2198 | ||
2199 | default: | |
2200 | abort (); | |
2201 | } | |
2202 | } | |
2203 | else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
2204 | || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) | |
2205 | { | |
2206 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
2207 | return CCX_NOOVmode; | |
2208 | else | |
2209 | return CC_NOOVmode; | |
2210 | } | |
2211 | else | |
2212 | { | |
2213 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
2214 | return CCXmode; | |
2215 | else | |
2216 | return CCmode; | |
2217 | } | |
2218 | } | |
2219 | ||
e0d80184 DM |
2220 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
2221 | return the rtx for the cc reg in the proper mode. */ | |
c85f7c16 | 2222 | |
e0d80184 | 2223 | rtx |
fc27d102 | 2224 | gen_compare_reg (enum rtx_code code, rtx x, rtx y) |
c85f7c16 | 2225 | { |
e0d80184 DM |
2226 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); |
2227 | rtx cc_reg; | |
c85f7c16 | 2228 | |
e0d80184 DM |
2229 | /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the |
2230 | fcc regs (cse can't tell they're really call clobbered regs and will | |
2231 | remove a duplicate comparison even if there is an intervening function | |
2232 | call - it will then try to reload the cc reg via an int reg which is why | |
2233 | we need the movcc patterns). It is possible to provide the movcc | |
2234 | patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two | |
2235 | registers (say %g1,%g5) and it takes about 6 insns. A better fix would be | |
2236 | to tell cse that CCFPE mode registers (even pseudos) are call | |
2237 | clobbered. */ | |
c85f7c16 | 2238 | |
e0d80184 DM |
2239 | /* ??? This is an experiment. Rather than making changes to cse which may |
2240 | or may not be easy/clean, we do our own cse. This is possible because | |
2241 | we will generate hard registers. Cse knows they're call clobbered (it | |
2242 | doesn't know the same thing about pseudos). If we guess wrong, no big | |
2243 | deal, but if we win, great! */ | |
c85f7c16 | 2244 | |
e0d80184 DM |
2245 | if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) |
2246 | #if 1 /* experiment */ | |
284d86e9 | 2247 | { |
e0d80184 DM |
2248 | int reg; |
2249 | /* We cycle through the registers to ensure they're all exercised. */ | |
2250 | static int next_fcc_reg = 0; | |
2251 | /* Previous x,y for each fcc reg. */ | |
2252 | static rtx prev_args[4][2]; | |
284d86e9 | 2253 | |
e0d80184 DM |
2254 | /* Scan prev_args for x,y. */ |
2255 | for (reg = 0; reg < 4; reg++) | |
2256 | if (prev_args[reg][0] == x && prev_args[reg][1] == y) | |
2257 | break; | |
2258 | if (reg == 4) | |
2259 | { | |
2260 | reg = next_fcc_reg; | |
2261 | prev_args[reg][0] = x; | |
2262 | prev_args[reg][1] = y; | |
2263 | next_fcc_reg = (next_fcc_reg + 1) & 3; | |
2264 | } | |
2265 | cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); | |
284d86e9 | 2266 | } |
e0d80184 DM |
2267 | #else |
2268 | cc_reg = gen_reg_rtx (mode); | |
2269 | #endif /* ! experiment */ | |
2270 | else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2271 | cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); | |
2272 | else | |
2273 | cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); | |
284d86e9 | 2274 | |
e0d80184 DM |
2275 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, |
2276 | gen_rtx_COMPARE (mode, x, y))); | |
c85f7c16 | 2277 | |
e0d80184 DM |
2278 | return cc_reg; |
2279 | } | |
c85f7c16 | 2280 | |
e0d80184 DM |
2281 | /* This function is used for v9 only. |
2282 | CODE is the code for an Scc's comparison. | |
2283 | OPERANDS[0] is the target of the Scc insn. | |
2284 | OPERANDS[1] is the value we compare against const0_rtx (which hasn't | |
2285 | been generated yet). | |
c85f7c16 | 2286 | |
e0d80184 | 2287 | This function is needed to turn |
ab835497 | 2288 | |
e0d80184 DM |
2289 | (set (reg:SI 110) |
2290 | (gt (reg:CCX 100 %icc) | |
2291 | (const_int 0))) | |
2292 | into | |
2293 | (set (reg:SI 110) | |
2294 | (gt:DI (reg:CCX 100 %icc) | |
2295 | (const_int 0))) | |
2296 | ||
2297 | IE: The instruction recognizer needs to see the mode of the comparison to | |
2298 | find the right instruction. We could use "gt:DI" right in the | |
2299 | define_expand, but leaving it out allows us to handle DI, SI, etc. | |
ab835497 | 2300 | |
e0d80184 DM |
2301 | We refer to the global sparc compare operands sparc_compare_op0 and |
2302 | sparc_compare_op1. */ | |
ab835497 RK |
2303 | |
2304 | int | |
fc27d102 | 2305 | gen_v9_scc (enum rtx_code compare_code, register rtx *operands) |
ab835497 | 2306 | { |
e0d80184 | 2307 | rtx temp, op0, op1; |
ab835497 | 2308 | |
e0d80184 DM |
2309 | if (! TARGET_ARCH64 |
2310 | && (GET_MODE (sparc_compare_op0) == DImode | |
2311 | || GET_MODE (operands[0]) == DImode)) | |
2312 | return 0; | |
7e2feebf | 2313 | |
a42519be | 2314 | op0 = sparc_compare_op0; |
e0d80184 DM |
2315 | op1 = sparc_compare_op1; |
2316 | ||
2317 | /* Try to use the movrCC insns. */ | |
2318 | if (TARGET_ARCH64 | |
2319 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
2320 | && op1 == const0_rtx | |
2321 | && v9_regcmp_p (compare_code)) | |
ab835497 | 2322 | { |
e0d80184 | 2323 | /* Special case for op0 != 0. This can be done with one instruction if |
a42519be | 2324 | operands[0] == sparc_compare_op0. */ |
e0d80184 DM |
2325 | |
2326 | if (compare_code == NE | |
2327 | && GET_MODE (operands[0]) == DImode | |
a42519be | 2328 | && rtx_equal_p (op0, operands[0])) |
ab835497 | 2329 | { |
e0d80184 DM |
2330 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], |
2331 | gen_rtx_IF_THEN_ELSE (DImode, | |
2332 | gen_rtx_fmt_ee (compare_code, DImode, | |
2333 | op0, const0_rtx), | |
2334 | const1_rtx, | |
2335 | operands[0]))); | |
ab835497 RK |
2336 | return 1; |
2337 | } | |
e0d80184 | 2338 | |
a42519be JJ |
2339 | if (reg_overlap_mentioned_p (operands[0], op0)) |
2340 | { | |
2341 | /* Handle the case where operands[0] == sparc_compare_op0. | |
2342 | We "early clobber" the result. */ | |
2343 | op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); | |
2344 | emit_move_insn (op0, sparc_compare_op0); | |
2345 | } | |
2346 | ||
e0d80184 DM |
2347 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); |
2348 | if (GET_MODE (op0) != DImode) | |
ab835497 | 2349 | { |
e0d80184 DM |
2350 | temp = gen_reg_rtx (DImode); |
2351 | convert_move (temp, op0, 0); | |
ab835497 | 2352 | } |
e0d80184 DM |
2353 | else |
2354 | temp = op0; | |
2355 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2356 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2357 | gen_rtx_fmt_ee (compare_code, DImode, | |
2358 | temp, const0_rtx), | |
2359 | const1_rtx, | |
2360 | operands[0]))); | |
95726648 DE |
2361 | return 1; |
2362 | } | |
e0d80184 | 2363 | else |
ab835497 | 2364 | { |
e0d80184 | 2365 | operands[1] = gen_compare_reg (compare_code, op0, op1); |
ab835497 | 2366 | |
e0d80184 | 2367 | switch (GET_MODE (operands[1])) |
ab835497 | 2368 | { |
e0d80184 DM |
2369 | case CCmode : |
2370 | case CCXmode : | |
2371 | case CCFPEmode : | |
2372 | case CCFPmode : | |
2373 | break; | |
2374 | default : | |
2375 | abort (); | |
ab835497 | 2376 | } |
e0d80184 DM |
2377 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); |
2378 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2379 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2380 | gen_rtx_fmt_ee (compare_code, | |
2381 | GET_MODE (operands[1]), | |
2382 | operands[1], const0_rtx), | |
2383 | const1_rtx, operands[0]))); | |
2384 | return 1; | |
ab835497 | 2385 | } |
ab835497 | 2386 | } |
4fb4e4b8 | 2387 | |
e0d80184 DM |
2388 | /* Emit a conditional jump insn for the v9 architecture using comparison code |
2389 | CODE and jump target LABEL. | |
2390 | This function exists to take advantage of the v9 brxx insns. */ | |
ab835497 | 2391 | |
e0d80184 | 2392 | void |
fc27d102 | 2393 | emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label) |
ab835497 | 2394 | { |
e0d80184 DM |
2395 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
2396 | pc_rtx, | |
2397 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
2398 | gen_rtx_fmt_ee (code, GET_MODE (op0), | |
2399 | op0, const0_rtx), | |
2400 | gen_rtx_LABEL_REF (VOIDmode, label), | |
2401 | pc_rtx))); | |
2402 | } | |
7b1ac798 JJ |
2403 | |
2404 | /* Generate a DFmode part of a hard TFmode register. | |
2405 | REG is the TFmode hard register, LOW is 1 for the | |
2406 | low 64bit of the register and 0 otherwise. | |
2407 | */ | |
2408 | rtx | |
fc27d102 | 2409 | gen_df_reg (rtx reg, int low) |
7b1ac798 JJ |
2410 | { |
2411 | int regno = REGNO (reg); | |
2412 | ||
2413 | if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) | |
2aac41d6 | 2414 | regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2; |
7b1ac798 JJ |
2415 | return gen_rtx_REG (DFmode, regno); |
2416 | } | |
e0d80184 | 2417 | \f |
73985940 RH |
2418 | /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value. |
2419 | Unlike normal calls, TFmode operands are passed by reference. It is | |
2420 | assumed that no more than 3 operands are required. */ | |
2421 | ||
2422 | static void | |
fc27d102 | 2423 | emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands) |
73985940 RH |
2424 | { |
2425 | rtx ret_slot = NULL, arg[3], func_sym; | |
4e7d5d27 | 2426 | int i; |
73985940 RH |
2427 | |
2428 | /* We only expect to be called for conversions, unary, and binary ops. */ | |
2429 | if (nargs < 2 || nargs > 3) | |
2430 | abort (); | |
2431 | ||
2432 | for (i = 0; i < nargs; ++i) | |
2433 | { | |
2434 | rtx this_arg = operands[i]; | |
2435 | rtx this_slot; | |
2436 | ||
2437 | /* TFmode arguments and return values are passed by reference. */ | |
2438 | if (GET_MODE (this_arg) == TFmode) | |
2439 | { | |
4e7d5d27 DM |
2440 | int force_stack_temp; |
2441 | ||
2442 | force_stack_temp = 0; | |
2443 | if (TARGET_BUGGY_QP_LIB && i == 0) | |
2444 | force_stack_temp = 1; | |
2445 | ||
2446 | if (GET_CODE (this_arg) == MEM | |
2447 | && ! force_stack_temp) | |
2448 | this_arg = XEXP (this_arg, 0); | |
2449 | else if (CONSTANT_P (this_arg) | |
2450 | && ! force_stack_temp) | |
73985940 RH |
2451 | { |
2452 | this_slot = force_const_mem (TFmode, this_arg); | |
2453 | this_arg = XEXP (this_slot, 0); | |
2454 | } | |
2455 | else | |
2456 | { | |
2457 | this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0); | |
2458 | ||
2459 | /* Operand 0 is the return value. We'll copy it out later. */ | |
2460 | if (i > 0) | |
2461 | emit_move_insn (this_slot, this_arg); | |
2462 | else | |
2463 | ret_slot = this_slot; | |
2464 | ||
2465 | this_arg = XEXP (this_slot, 0); | |
2466 | } | |
2467 | } | |
2468 | ||
2469 | arg[i] = this_arg; | |
2470 | } | |
2471 | ||
2472 | func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name); | |
2473 | ||
2474 | if (GET_MODE (operands[0]) == TFmode) | |
2475 | { | |
2476 | if (nargs == 2) | |
2477 | emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2, | |
2478 | arg[0], GET_MODE (arg[0]), | |
2479 | arg[1], GET_MODE (arg[1])); | |
2480 | else | |
2481 | emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3, | |
2482 | arg[0], GET_MODE (arg[0]), | |
2483 | arg[1], GET_MODE (arg[1]), | |
2484 | arg[2], GET_MODE (arg[2])); | |
2485 | ||
2486 | if (ret_slot) | |
2487 | emit_move_insn (operands[0], ret_slot); | |
2488 | } | |
2489 | else | |
2490 | { | |
2491 | rtx ret; | |
2492 | ||
2493 | if (nargs != 2) | |
2494 | abort (); | |
2495 | ||
2496 | ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL, | |
2497 | GET_MODE (operands[0]), 1, | |
2498 | arg[1], GET_MODE (arg[1])); | |
2499 | ||
2500 | if (ret != operands[0]) | |
2501 | emit_move_insn (operands[0], ret); | |
2502 | } | |
2503 | } | |
2504 | ||
2505 | /* Expand soft-float TFmode calls to sparc abi routines. */ | |
2506 | ||
2507 | static void | |
fc27d102 | 2508 | emit_soft_tfmode_binop (enum rtx_code code, rtx *operands) |
73985940 RH |
2509 | { |
2510 | const char *func; | |
2511 | ||
2512 | switch (code) | |
2513 | { | |
2514 | case PLUS: | |
2515 | func = "_Qp_add"; | |
2516 | break; | |
2517 | case MINUS: | |
2518 | func = "_Qp_sub"; | |
2519 | break; | |
2520 | case MULT: | |
2521 | func = "_Qp_mul"; | |
2522 | break; | |
2523 | case DIV: | |
2524 | func = "_Qp_div"; | |
2525 | break; | |
2526 | default: | |
2527 | abort (); | |
2528 | } | |
2529 | ||
2530 | emit_soft_tfmode_libcall (func, 3, operands); | |
2531 | } | |
2532 | ||
2533 | static void | |
fc27d102 | 2534 | emit_soft_tfmode_unop (enum rtx_code code, rtx *operands) |
73985940 RH |
2535 | { |
2536 | const char *func; | |
2537 | ||
2538 | switch (code) | |
2539 | { | |
2540 | case SQRT: | |
2541 | func = "_Qp_sqrt"; | |
2542 | break; | |
2543 | default: | |
2544 | abort (); | |
2545 | } | |
2546 | ||
2547 | emit_soft_tfmode_libcall (func, 2, operands); | |
2548 | } | |
2549 | ||
2550 | static void | |
fc27d102 | 2551 | emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands) |
73985940 RH |
2552 | { |
2553 | const char *func; | |
2554 | ||
2555 | switch (code) | |
2556 | { | |
2557 | case FLOAT_EXTEND: | |
2558 | switch (GET_MODE (operands[1])) | |
2559 | { | |
2560 | case SFmode: | |
2561 | func = "_Qp_stoq"; | |
2562 | break; | |
2563 | case DFmode: | |
2564 | func = "_Qp_dtoq"; | |
2565 | break; | |
2566 | default: | |
2567 | abort (); | |
2568 | } | |
2569 | break; | |
2570 | ||
2571 | case FLOAT_TRUNCATE: | |
2572 | switch (GET_MODE (operands[0])) | |
2573 | { | |
2574 | case SFmode: | |
2575 | func = "_Qp_qtos"; | |
2576 | break; | |
2577 | case DFmode: | |
2578 | func = "_Qp_qtod"; | |
2579 | break; | |
2580 | default: | |
2581 | abort (); | |
2582 | } | |
2583 | break; | |
2584 | ||
2585 | case FLOAT: | |
2586 | switch (GET_MODE (operands[1])) | |
2587 | { | |
2588 | case SImode: | |
2589 | func = "_Qp_itoq"; | |
2590 | break; | |
2591 | case DImode: | |
2592 | func = "_Qp_xtoq"; | |
2593 | break; | |
2594 | default: | |
2595 | abort (); | |
2596 | } | |
2597 | break; | |
2598 | ||
2599 | case UNSIGNED_FLOAT: | |
2600 | switch (GET_MODE (operands[1])) | |
2601 | { | |
2602 | case SImode: | |
2603 | func = "_Qp_uitoq"; | |
2604 | break; | |
2605 | case DImode: | |
2606 | func = "_Qp_uxtoq"; | |
2607 | break; | |
2608 | default: | |
2609 | abort (); | |
2610 | } | |
2611 | break; | |
2612 | ||
2613 | case FIX: | |
2614 | switch (GET_MODE (operands[0])) | |
2615 | { | |
2616 | case SImode: | |
2617 | func = "_Qp_qtoi"; | |
2618 | break; | |
2619 | case DImode: | |
2620 | func = "_Qp_qtox"; | |
2621 | break; | |
2622 | default: | |
2623 | abort (); | |
2624 | } | |
2625 | break; | |
2626 | ||
2627 | case UNSIGNED_FIX: | |
2628 | switch (GET_MODE (operands[0])) | |
2629 | { | |
2630 | case SImode: | |
2631 | func = "_Qp_qtoui"; | |
2632 | break; | |
2633 | case DImode: | |
2634 | func = "_Qp_qtoux"; | |
2635 | break; | |
2636 | default: | |
2637 | abort (); | |
2638 | } | |
2639 | break; | |
2640 | ||
2641 | default: | |
2642 | abort (); | |
2643 | } | |
2644 | ||
2645 | emit_soft_tfmode_libcall (func, 2, operands); | |
2646 | } | |
2647 | ||
2648 | /* Expand a hard-float tfmode operation. All arguments must be in | |
2649 | registers. */ | |
2650 | ||
2651 | static void | |
fc27d102 | 2652 | emit_hard_tfmode_operation (enum rtx_code code, rtx *operands) |
73985940 RH |
2653 | { |
2654 | rtx op, dest; | |
2655 | ||
2656 | if (GET_RTX_CLASS (code) == '1') | |
2657 | { | |
2658 | operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); | |
2659 | op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]); | |
2660 | } | |
2661 | else | |
2662 | { | |
2663 | operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); | |
2664 | operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); | |
2665 | op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]), | |
2666 | operands[1], operands[2]); | |
2667 | } | |
2668 | ||
2669 | if (register_operand (operands[0], VOIDmode)) | |
2670 | dest = operands[0]; | |
2671 | else | |
2672 | dest = gen_reg_rtx (GET_MODE (operands[0])); | |
2673 | ||
2674 | emit_insn (gen_rtx_SET (VOIDmode, dest, op)); | |
2675 | ||
2676 | if (dest != operands[0]) | |
2677 | emit_move_insn (operands[0], dest); | |
2678 | } | |
2679 | ||
2680 | void | |
fc27d102 | 2681 | emit_tfmode_binop (enum rtx_code code, rtx *operands) |
73985940 RH |
2682 | { |
2683 | if (TARGET_HARD_QUAD) | |
2684 | emit_hard_tfmode_operation (code, operands); | |
2685 | else | |
2686 | emit_soft_tfmode_binop (code, operands); | |
2687 | } | |
2688 | ||
2689 | void | |
fc27d102 | 2690 | emit_tfmode_unop (enum rtx_code code, rtx *operands) |
73985940 RH |
2691 | { |
2692 | if (TARGET_HARD_QUAD) | |
2693 | emit_hard_tfmode_operation (code, operands); | |
2694 | else | |
2695 | emit_soft_tfmode_unop (code, operands); | |
2696 | } | |
2697 | ||
2698 | void | |
fc27d102 | 2699 | emit_tfmode_cvt (enum rtx_code code, rtx *operands) |
73985940 RH |
2700 | { |
2701 | if (TARGET_HARD_QUAD) | |
2702 | emit_hard_tfmode_operation (code, operands); | |
2703 | else | |
2704 | emit_soft_tfmode_cvt (code, operands); | |
2705 | } | |
2706 | \f | |
e0d80184 DM |
2707 | /* Return nonzero if a return peephole merging return with |
2708 | setting of output register is ok. */ | |
2709 | int | |
fc27d102 | 2710 | leaf_return_peephole_ok (void) |
e0d80184 DM |
2711 | { |
2712 | return (actual_fsize == 0); | |
2713 | } | |
284d86e9 | 2714 | |
f17f9332 JJ |
2715 | /* Return nonzero if a branch/jump/call instruction will be emitting |
2716 | nop into its delay slot. */ | |
2717 | ||
2718 | int | |
fc27d102 | 2719 | empty_delay_slot (rtx insn) |
f17f9332 JJ |
2720 | { |
2721 | rtx seq; | |
2722 | ||
2723 | /* If no previous instruction (should not happen), return true. */ | |
2724 | if (PREV_INSN (insn) == NULL) | |
2725 | return 1; | |
2726 | ||
2727 | seq = NEXT_INSN (PREV_INSN (insn)); | |
2728 | if (GET_CODE (PATTERN (seq)) == SEQUENCE) | |
2729 | return 0; | |
2730 | ||
2731 | return 1; | |
2732 | } | |
2733 | ||
e0d80184 DM |
2734 | /* Return nonzero if TRIAL can go into the function epilogue's |
2735 | delay slot. SLOT is the slot we are trying to fill. */ | |
ab835497 | 2736 | |
e0d80184 | 2737 | int |
fc27d102 | 2738 | eligible_for_epilogue_delay (rtx trial, int slot) |
e0d80184 DM |
2739 | { |
2740 | rtx pat, src; | |
4fb4e4b8 | 2741 | |
e0d80184 DM |
2742 | if (slot >= 1) |
2743 | return 0; | |
4fb4e4b8 | 2744 | |
e0d80184 DM |
2745 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) |
2746 | return 0; | |
4fb4e4b8 | 2747 | |
e0d80184 DM |
2748 | if (get_attr_length (trial) != 1) |
2749 | return 0; | |
4fb4e4b8 | 2750 | |
e48addee JJ |
2751 | /* If there are any call-saved registers, we should scan TRIAL if it |
2752 | does not reference them. For now just make it easy. */ | |
2753 | if (num_gfregs) | |
2754 | return 0; | |
4fb4e4b8 | 2755 | |
1150a841 RH |
2756 | /* If the function uses __builtin_eh_return, the eh_return machinery |
2757 | occupies the delay slot. */ | |
2758 | if (current_function_calls_eh_return) | |
2759 | return 0; | |
2760 | ||
e0d80184 DM |
2761 | /* In the case of a true leaf function, anything can go into the delay slot. |
2762 | A delay slot only exists however if the frame size is zero, otherwise | |
2763 | we will put an insn to adjust the stack after the return. */ | |
54ff41b7 | 2764 | if (current_function_uses_only_leaf_regs) |
4fb4e4b8 | 2765 | { |
e0d80184 DM |
2766 | if (leaf_return_peephole_ok ()) |
2767 | return ((get_attr_in_uncond_branch_delay (trial) | |
2768 | == IN_BRANCH_DELAY_TRUE)); | |
2769 | return 0; | |
4fb4e4b8 | 2770 | } |
4fb4e4b8 | 2771 | |
e0d80184 | 2772 | pat = PATTERN (trial); |
795068a4 | 2773 | |
e0d80184 | 2774 | /* Otherwise, only operations which can be done in tandem with |
e48addee | 2775 | a `restore' or `return' insn can go into the delay slot. */ |
e0d80184 | 2776 | if (GET_CODE (SET_DEST (pat)) != REG |
e0d80184 DM |
2777 | || REGNO (SET_DEST (pat)) < 24) |
2778 | return 0; | |
795068a4 | 2779 | |
c137830f JJ |
2780 | /* If this instruction sets up floating point register and we have a return |
2781 | instruction, it can probably go in. But restore will not work | |
2782 | with FP_REGS. */ | |
2783 | if (REGNO (SET_DEST (pat)) >= 32) | |
2784 | { | |
2785 | if (TARGET_V9 && ! epilogue_renumber (&pat, 1) | |
2786 | && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) | |
2787 | return 1; | |
2788 | return 0; | |
2789 | } | |
2790 | ||
e0d80184 DM |
2791 | /* The set of insns matched here must agree precisely with the set of |
2792 | patterns paired with a RETURN in sparc.md. */ | |
795068a4 | 2793 | |
e0d80184 | 2794 | src = SET_SRC (pat); |
795068a4 | 2795 | |
3c6088d2 | 2796 | /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */ |
3ec6f1a9 RK |
2797 | if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2798 | && arith_operand (src, GET_MODE (src))) | |
3c6088d2 JJ |
2799 | { |
2800 | if (TARGET_ARCH64) | |
2801 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2802 | else | |
2803 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
2804 | } | |
e48addee | 2805 | |
e0d80184 | 2806 | /* This matches "*return_di". */ |
3ec6f1a9 RK |
2807 | else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2808 | && arith_double_operand (src, GET_MODE (src))) | |
e0d80184 | 2809 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); |
795068a4 | 2810 | |
e0d80184 DM |
2811 | /* This matches "*return_sf_no_fpu". */ |
2812 | else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) | |
2813 | && register_operand (src, SFmode)) | |
2814 | return 1; | |
f5da225e | 2815 | |
e48addee JJ |
2816 | /* If we have return instruction, anything that does not use |
2817 | local or output registers and can go into a delay slot wins. */ | |
2818 | else if (TARGET_V9 && ! epilogue_renumber (&pat, 1) | |
2819 | && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) | |
2820 | return 1; | |
2821 | ||
e0d80184 DM |
2822 | /* This matches "*return_addsi". */ |
2823 | else if (GET_CODE (src) == PLUS | |
2824 | && arith_operand (XEXP (src, 0), SImode) | |
2825 | && arith_operand (XEXP (src, 1), SImode) | |
2826 | && (register_operand (XEXP (src, 0), SImode) | |
2827 | || register_operand (XEXP (src, 1), SImode))) | |
2828 | return 1; | |
2829 | ||
2830 | /* This matches "*return_adddi". */ | |
2831 | else if (GET_CODE (src) == PLUS | |
2832 | && arith_double_operand (XEXP (src, 0), DImode) | |
2833 | && arith_double_operand (XEXP (src, 1), DImode) | |
2834 | && (register_operand (XEXP (src, 0), DImode) | |
2835 | || register_operand (XEXP (src, 1), DImode))) | |
795068a4 | 2836 | return 1; |
795068a4 | 2837 | |
e48addee JJ |
2838 | /* This can match "*return_losum_[sd]i". |
2839 | Catch only some cases, so that return_losum* don't have | |
2840 | to be too big. */ | |
2841 | else if (GET_CODE (src) == LO_SUM | |
2842 | && ! TARGET_CM_MEDMID | |
2843 | && ((register_operand (XEXP (src, 0), SImode) | |
2844 | && immediate_operand (XEXP (src, 1), SImode)) | |
2845 | || (TARGET_ARCH64 | |
2846 | && register_operand (XEXP (src, 0), DImode) | |
2847 | && immediate_operand (XEXP (src, 1), DImode)))) | |
2848 | return 1; | |
2849 | ||
2850 | /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */ | |
2851 | else if (GET_CODE (src) == ASHIFT | |
2852 | && (register_operand (XEXP (src, 0), SImode) | |
2853 | || register_operand (XEXP (src, 0), DImode)) | |
2854 | && XEXP (src, 1) == const1_rtx) | |
2855 | return 1; | |
2856 | ||
795068a4 JW |
2857 | return 0; |
2858 | } | |
2859 | ||
5751a10b JJ |
2860 | /* Return nonzero if TRIAL can go into the call delay slot. */ |
2861 | int | |
2862 | tls_call_delay (rtx trial) | |
2863 | { | |
2864 | rtx pat, unspec; | |
2865 | ||
2866 | /* Binutils allows | |
2867 | call __tls_get_addr, %tgd_call (foo) | |
2868 | add %l7, %o0, %o0, %tgd_add (foo) | |
2869 | while Sun as/ld does not. */ | |
2870 | if (TARGET_GNU_TLS || !TARGET_TLS) | |
2871 | return 1; | |
2872 | ||
2873 | pat = PATTERN (trial); | |
2874 | if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS) | |
2875 | return 1; | |
2876 | ||
2877 | unspec = XEXP (SET_DEST (pat), 1); | |
2878 | if (GET_CODE (unspec) != UNSPEC | |
2879 | || (XINT (unspec, 1) != UNSPEC_TLSGD | |
2880 | && XINT (unspec, 1) != UNSPEC_TLSLDM)) | |
2881 | return 1; | |
2882 | ||
2883 | return 0; | |
2884 | } | |
2885 | ||
7d167afd JJ |
2886 | /* Return nonzero if TRIAL can go into the sibling call |
2887 | delay slot. */ | |
2888 | ||
2889 | int | |
fc27d102 | 2890 | eligible_for_sibcall_delay (rtx trial) |
7d167afd JJ |
2891 | { |
2892 | rtx pat, src; | |
2893 | ||
2894 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) | |
2895 | return 0; | |
2896 | ||
8456b95a | 2897 | if (get_attr_length (trial) != 1) |
7d167afd JJ |
2898 | return 0; |
2899 | ||
2900 | pat = PATTERN (trial); | |
2901 | ||
2902 | if (current_function_uses_only_leaf_regs) | |
2903 | { | |
2904 | /* If the tail call is done using the call instruction, | |
2905 | we have to restore %o7 in the delay slot. */ | |
2be5e524 | 2906 | if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic) |
7d167afd JJ |
2907 | return 0; |
2908 | ||
2909 | /* %g1 is used to build the function address */ | |
2910 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) | |
2911 | return 0; | |
2912 | ||
2913 | return 1; | |
2914 | } | |
2915 | ||
2916 | /* Otherwise, only operations which can be done in tandem with | |
2917 | a `restore' insn can go into the delay slot. */ | |
2918 | if (GET_CODE (SET_DEST (pat)) != REG | |
2919 | || REGNO (SET_DEST (pat)) < 24 | |
2920 | || REGNO (SET_DEST (pat)) >= 32) | |
2921 | return 0; | |
2922 | ||
2923 | /* If it mentions %o7, it can't go in, because sibcall will clobber it | |
2924 | in most cases. */ | |
2925 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) | |
2926 | return 0; | |
2927 | ||
2928 | src = SET_SRC (pat); | |
2929 | ||
3ec6f1a9 RK |
2930 | if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2931 | && arith_operand (src, GET_MODE (src))) | |
7d167afd JJ |
2932 | { |
2933 | if (TARGET_ARCH64) | |
2934 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2935 | else | |
2936 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
2937 | } | |
2938 | ||
3ec6f1a9 RK |
2939 | else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2940 | && arith_double_operand (src, GET_MODE (src))) | |
7d167afd JJ |
2941 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); |
2942 | ||
2943 | else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) | |
2944 | && register_operand (src, SFmode)) | |
2945 | return 1; | |
2946 | ||
2947 | else if (GET_CODE (src) == PLUS | |
2948 | && arith_operand (XEXP (src, 0), SImode) | |
2949 | && arith_operand (XEXP (src, 1), SImode) | |
2950 | && (register_operand (XEXP (src, 0), SImode) | |
2951 | || register_operand (XEXP (src, 1), SImode))) | |
2952 | return 1; | |
2953 | ||
2954 | else if (GET_CODE (src) == PLUS | |
2955 | && arith_double_operand (XEXP (src, 0), DImode) | |
2956 | && arith_double_operand (XEXP (src, 1), DImode) | |
2957 | && (register_operand (XEXP (src, 0), DImode) | |
2958 | || register_operand (XEXP (src, 1), DImode))) | |
2959 | return 1; | |
2960 | ||
2961 | else if (GET_CODE (src) == LO_SUM | |
2962 | && ! TARGET_CM_MEDMID | |
2963 | && ((register_operand (XEXP (src, 0), SImode) | |
2964 | && immediate_operand (XEXP (src, 1), SImode)) | |
2965 | || (TARGET_ARCH64 | |
2966 | && register_operand (XEXP (src, 0), DImode) | |
2967 | && immediate_operand (XEXP (src, 1), DImode)))) | |
2968 | return 1; | |
2969 | ||
2970 | else if (GET_CODE (src) == ASHIFT | |
2971 | && (register_operand (XEXP (src, 0), SImode) | |
2972 | || register_operand (XEXP (src, 0), DImode)) | |
2973 | && XEXP (src, 1) == const1_rtx) | |
2974 | return 1; | |
2975 | ||
2976 | return 0; | |
2977 | } | |
2978 | ||
e0d80184 | 2979 | static int |
fc27d102 | 2980 | check_return_regs (rtx x) |
ab835497 | 2981 | { |
e0d80184 DM |
2982 | switch (GET_CODE (x)) |
2983 | { | |
2984 | case REG: | |
2985 | return IN_OR_GLOBAL_P (x); | |
ab835497 | 2986 | |
e0d80184 DM |
2987 | case CONST_INT: |
2988 | case CONST_DOUBLE: | |
2989 | case CONST: | |
2990 | case SYMBOL_REF: | |
2991 | case LABEL_REF: | |
2992 | return 1; | |
ab835497 | 2993 | |
e0d80184 DM |
2994 | case SET: |
2995 | case IOR: | |
2996 | case AND: | |
2997 | case XOR: | |
2998 | case PLUS: | |
2999 | case MINUS: | |
3000 | if (check_return_regs (XEXP (x, 1)) == 0) | |
3001 | return 0; | |
3002 | case NOT: | |
3003 | case NEG: | |
3004 | case MEM: | |
3005 | return check_return_regs (XEXP (x, 0)); | |
3006 | ||
3007 | default: | |
3008 | return 0; | |
3009 | } | |
ab835497 | 3010 | |
e0d80184 | 3011 | } |
ab835497 | 3012 | |
e0d80184 | 3013 | int |
fc27d102 | 3014 | short_branch (int uid1, int uid2) |
e0d80184 | 3015 | { |
9d98a694 | 3016 | int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2); |
77b91512 RK |
3017 | |
3018 | /* Leave a few words of "slop". */ | |
3019 | if (delta >= -1023 && delta <= 1022) | |
e0d80184 | 3020 | return 1; |
77b91512 | 3021 | |
e0d80184 DM |
3022 | return 0; |
3023 | } | |
ab835497 | 3024 | |
5e7a8ee0 | 3025 | /* Return nonzero if REG is not used after INSN. |
e0d80184 DM |
3026 | We assume REG is a reload reg, and therefore does |
3027 | not live past labels or calls or jumps. */ | |
3028 | int | |
fc27d102 | 3029 | reg_unused_after (rtx reg, rtx insn) |
e0d80184 DM |
3030 | { |
3031 | enum rtx_code code, prev_code = UNKNOWN; | |
ab835497 | 3032 | |
e0d80184 | 3033 | while ((insn = NEXT_INSN (insn))) |
61a55e8b | 3034 | { |
e0d80184 DM |
3035 | if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) |
3036 | return 1; | |
ab835497 | 3037 | |
e0d80184 DM |
3038 | code = GET_CODE (insn); |
3039 | if (GET_CODE (insn) == CODE_LABEL) | |
3040 | return 1; | |
bc961ed7 | 3041 | |
e0d80184 | 3042 | if (GET_RTX_CLASS (code) == 'i') |
61a55e8b | 3043 | { |
e0d80184 DM |
3044 | rtx set = single_set (insn); |
3045 | int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); | |
3046 | if (set && in_src) | |
3047 | return 0; | |
3048 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
3049 | return 1; | |
3050 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
3051 | return 0; | |
61a55e8b | 3052 | } |
e0d80184 | 3053 | prev_code = code; |
61a55e8b | 3054 | } |
e0d80184 DM |
3055 | return 1; |
3056 | } | |
3057 | \f | |
5751a10b JJ |
3058 | /* Determine if it's legal to put X into the constant pool. This |
3059 | is not possible if X contains the address of a symbol that is | |
3060 | not constant (TLS) or not known at final link time (PIC). */ | |
3061 | ||
3062 | static bool | |
3063 | sparc_cannot_force_const_mem (rtx x) | |
3064 | { | |
3065 | switch (GET_CODE (x)) | |
3066 | { | |
3067 | case CONST_INT: | |
3068 | case CONST_DOUBLE: | |
3069 | /* Accept all non-symbolic constants. */ | |
3070 | return false; | |
3071 | ||
3072 | case LABEL_REF: | |
3073 | /* Labels are OK iff we are non-PIC. */ | |
3074 | return flag_pic != 0; | |
3075 | ||
3076 | case SYMBOL_REF: | |
3077 | /* 'Naked' TLS symbol references are never OK, | |
3078 | non-TLS symbols are OK iff we are non-PIC. */ | |
3079 | if (SYMBOL_REF_TLS_MODEL (x)) | |
3080 | return true; | |
3081 | else | |
3082 | return flag_pic != 0; | |
3083 | ||
3084 | case CONST: | |
3085 | return sparc_cannot_force_const_mem (XEXP (x, 0)); | |
3086 | case PLUS: | |
3087 | case MINUS: | |
3088 | return sparc_cannot_force_const_mem (XEXP (x, 0)) | |
3089 | || sparc_cannot_force_const_mem (XEXP (x, 1)); | |
3090 | case UNSPEC: | |
3091 | return true; | |
3092 | default: | |
3093 | abort (); | |
3094 | } | |
3095 | } | |
3096 | \f | |
e0d80184 | 3097 | /* The table we use to reference PIC data. */ |
e2500fed | 3098 | static GTY(()) rtx global_offset_table; |
bc961ed7 | 3099 | |
e0d80184 | 3100 | /* The function we use to get at it. */ |
e2500fed | 3101 | static GTY(()) rtx get_pc_symbol; |
e0d80184 | 3102 | static char get_pc_symbol_name[256]; |
ab835497 | 3103 | |
e0d80184 | 3104 | /* Ensure that we are not using patterns that are not OK with PIC. */ |
795068a4 | 3105 | |
e0d80184 | 3106 | int |
fc27d102 | 3107 | check_pic (int i) |
e0d80184 DM |
3108 | { |
3109 | switch (flag_pic) | |
ab835497 | 3110 | { |
e0d80184 | 3111 | case 1: |
1ccbefce RH |
3112 | if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF |
3113 | || (GET_CODE (recog_data.operand[i]) == CONST | |
3114 | && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS | |
3115 | && (XEXP (XEXP (recog_data.operand[i], 0), 0) | |
e0d80184 | 3116 | == global_offset_table) |
1ccbefce | 3117 | && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) |
e0d80184 DM |
3118 | == CONST)))) |
3119 | abort (); | |
3120 | case 2: | |
3121 | default: | |
3122 | return 1; | |
ab835497 | 3123 | } |
ab835497 | 3124 | } |
795068a4 | 3125 | |
e0d80184 DM |
3126 | /* Return true if X is an address which needs a temporary register when |
3127 | reloaded while generating PIC code. */ | |
795068a4 | 3128 | |
e0d80184 | 3129 | int |
fc27d102 | 3130 | pic_address_needs_scratch (rtx x) |
795068a4 | 3131 | { |
e0d80184 DM |
3132 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ |
3133 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
3134 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
3135 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3136 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
3137 | return 1; | |
795068a4 | 3138 | |
e0d80184 DM |
3139 | return 0; |
3140 | } | |
795068a4 | 3141 | |
5751a10b JJ |
3142 | /* Determine if a given RTX is a valid constant. We already know this |
3143 | satisfies CONSTANT_P. */ | |
3144 | ||
3145 | bool | |
3146 | legitimate_constant_p (rtx x) | |
3147 | { | |
3148 | rtx inner; | |
3149 | ||
3150 | switch (GET_CODE (x)) | |
3151 | { | |
3152 | case SYMBOL_REF: | |
3153 | /* TLS symbols are not constant. */ | |
3154 | if (SYMBOL_REF_TLS_MODEL (x)) | |
3155 | return false; | |
3156 | break; | |
3157 | ||
3158 | case CONST: | |
3159 | inner = XEXP (x, 0); | |
3160 | ||
3161 | /* Offsets of TLS symbols are never valid. | |
3162 | Discourage CSE from creating them. */ | |
3163 | if (GET_CODE (inner) == PLUS | |
3164 | && tls_symbolic_operand (XEXP (inner, 0))) | |
3165 | return false; | |
3166 | break; | |
3167 | ||
3168 | case CONST_DOUBLE: | |
3169 | if (GET_MODE (x) == VOIDmode) | |
3170 | return true; | |
3171 | ||
3172 | /* Floating point constants are generally not ok. | |
3173 | The only exception is 0.0 in VIS. */ | |
3174 | if (TARGET_VIS | |
3175 | && (GET_MODE (x) == SFmode | |
3176 | || GET_MODE (x) == DFmode | |
3177 | || GET_MODE (x) == TFmode) | |
3178 | && fp_zero_operand (x, GET_MODE (x))) | |
3179 | return true; | |
3180 | ||
3181 | return false; | |
3182 | ||
3183 | default: | |
3184 | break; | |
3185 | } | |
3186 | ||
3187 | return true; | |
3188 | } | |
3189 | ||
3190 | /* Determine if a given RTX is a valid constant address. */ | |
3191 | ||
3192 | bool | |
3193 | constant_address_p (rtx x) | |
3194 | { | |
3195 | switch (GET_CODE (x)) | |
3196 | { | |
3197 | case LABEL_REF: | |
3198 | case CONST_INT: | |
3199 | case HIGH: | |
3200 | return true; | |
3201 | ||
3202 | case CONST: | |
3203 | if (flag_pic && pic_address_needs_scratch (x)) | |
3204 | return false; | |
3205 | return legitimate_constant_p (x); | |
3206 | ||
3207 | case SYMBOL_REF: | |
3208 | return !flag_pic && legitimate_constant_p (x); | |
3209 | ||
3210 | default: | |
3211 | return false; | |
3212 | } | |
3213 | } | |
3214 | ||
3215 | /* Nonzero if the constant value X is a legitimate general operand | |
3216 | when generating PIC code. It is given that flag_pic is on and | |
3217 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
3218 | ||
3219 | bool | |
3220 | legitimate_pic_operand_p (rtx x) | |
3221 | { | |
3222 | if (pic_address_needs_scratch (x)) | |
3223 | return false; | |
3224 | if (tls_symbolic_operand (x) | |
3225 | || (GET_CODE (x) == CONST | |
3226 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3227 | && tls_symbolic_operand (XEXP (XEXP (x, 0), 0)))) | |
3228 | return false; | |
3229 | return true; | |
3230 | } | |
3231 | ||
3232 | /* Return nonzero if ADDR is a valid memory address. | |
3233 | STRICT specifies whether strict register checking applies. */ | |
3234 | ||
3235 | int | |
3236 | legitimate_address_p (enum machine_mode mode, rtx addr, int strict) | |
3237 | { | |
3238 | rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2; | |
3239 | ||
3240 | if (REG_P (addr) || GET_CODE (addr) == SUBREG) | |
3241 | rs1 = addr; | |
3242 | else if (GET_CODE (addr) == PLUS) | |
3243 | { | |
3244 | rs1 = XEXP (addr, 0); | |
3245 | rs2 = XEXP (addr, 1); | |
3246 | ||
3247 | /* Canonicalize. REG comes first, if there are no regs, | |
3248 | LO_SUM comes first. */ | |
3249 | if (!REG_P (rs1) | |
3250 | && GET_CODE (rs1) != SUBREG | |
3251 | && (REG_P (rs2) | |
3252 | || GET_CODE (rs2) == SUBREG | |
3253 | || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM))) | |
3254 | { | |
3255 | rs1 = XEXP (addr, 1); | |
3256 | rs2 = XEXP (addr, 0); | |
3257 | } | |
3258 | ||
3259 | if ((flag_pic == 1 | |
3260 | && rs1 == pic_offset_table_rtx | |
3261 | && !REG_P (rs2) | |
3262 | && GET_CODE (rs2) != SUBREG | |
3263 | && GET_CODE (rs2) != LO_SUM | |
3264 | && GET_CODE (rs2) != MEM | |
3265 | && !tls_symbolic_operand (rs2) | |
3266 | && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode) | |
3267 | && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2))) | |
3268 | || ((REG_P (rs1) | |
3269 | || GET_CODE (rs1) == SUBREG) | |
3270 | && RTX_OK_FOR_OFFSET_P (rs2))) | |
3271 | { | |
3272 | imm1 = rs2; | |
3273 | rs2 = NULL; | |
3274 | } | |
3275 | else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG) | |
3276 | && (REG_P (rs2) || GET_CODE (rs2) == SUBREG)) | |
3277 | { | |
3278 | /* We prohibit REG + REG for TFmode when there are no instructions | |
3279 | which accept REG+REG instructions. We do this because REG+REG | |
3280 | is not an offsetable address. If we get the situation in reload | |
3281 | where source and destination of a movtf pattern are both MEMs with | |
3282 | REG+REG address, then only one of them gets converted to an | |
3283 | offsetable address. */ | |
3284 | if (mode == TFmode | |
3285 | && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9 | |
3286 | && TARGET_HARD_QUAD)) | |
3287 | return 0; | |
3288 | ||
3289 | /* We prohibit REG + REG on ARCH32 if not optimizing for | |
3290 | DFmode/DImode because then mem_min_alignment is likely to be zero | |
3291 | after reload and the forced split would lack a matching splitter | |
3292 | pattern. */ | |
3293 | if (TARGET_ARCH32 && !optimize | |
3294 | && (mode == DFmode || mode == DImode)) | |
3295 | return 0; | |
3296 | } | |
3297 | else if (USE_AS_OFFSETABLE_LO10 | |
3298 | && GET_CODE (rs1) == LO_SUM | |
3299 | && TARGET_ARCH64 | |
3300 | && ! TARGET_CM_MEDMID | |
3301 | && RTX_OK_FOR_OLO10_P (rs2)) | |
3302 | { | |
3303 | imm2 = rs2; | |
3304 | rs2 = NULL; | |
3305 | imm1 = XEXP (rs1, 1); | |
3306 | rs1 = XEXP (rs1, 0); | |
3307 | if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1)) | |
3308 | return 0; | |
3309 | } | |
3310 | } | |
3311 | else if (GET_CODE (addr) == LO_SUM) | |
3312 | { | |
3313 | rs1 = XEXP (addr, 0); | |
3314 | imm1 = XEXP (addr, 1); | |
3315 | ||
3316 | if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1)) | |
3317 | return 0; | |
3318 | ||
3319 | /* We can't allow TFmode, because an offset greater than or equal to the | |
3320 | alignment (8) may cause the LO_SUM to overflow if !v9. */ | |
3321 | if (mode == TFmode && !TARGET_V9) | |
3322 | return 0; | |
3323 | } | |
3324 | else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr)) | |
3325 | return 1; | |
3326 | else | |
3327 | return 0; | |
3328 | ||
3329 | if (GET_CODE (rs1) == SUBREG) | |
3330 | rs1 = SUBREG_REG (rs1); | |
3331 | if (!REG_P (rs1)) | |
3332 | return 0; | |
3333 | ||
3334 | if (rs2) | |
3335 | { | |
3336 | if (GET_CODE (rs2) == SUBREG) | |
3337 | rs2 = SUBREG_REG (rs2); | |
3338 | if (!REG_P (rs2)) | |
3339 | return 0; | |
3340 | } | |
3341 | ||
3342 | if (strict) | |
3343 | { | |
3344 | if (!REGNO_OK_FOR_BASE_P (REGNO (rs1)) | |
3345 | || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2)))) | |
3346 | return 0; | |
3347 | } | |
3348 | else | |
3349 | { | |
3350 | if ((REGNO (rs1) >= 32 | |
3351 | && REGNO (rs1) != FRAME_POINTER_REGNUM | |
3352 | && REGNO (rs1) < FIRST_PSEUDO_REGISTER) | |
3353 | || (rs2 | |
3354 | && (REGNO (rs2) >= 32 | |
3355 | && REGNO (rs2) != FRAME_POINTER_REGNUM | |
3356 | && REGNO (rs2) < FIRST_PSEUDO_REGISTER))) | |
3357 | return 0; | |
3358 | } | |
3359 | return 1; | |
3360 | } | |
3361 | ||
3362 | /* Construct the SYMBOL_REF for the tls_get_offset function. */ | |
3363 | ||
3364 | static GTY(()) rtx sparc_tls_symbol; | |
3365 | static rtx | |
3366 | sparc_tls_get_addr (void) | |
3367 | { | |
3368 | if (!sparc_tls_symbol) | |
3369 | sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr"); | |
3370 | ||
3371 | return sparc_tls_symbol; | |
3372 | } | |
3373 | ||
3374 | static rtx | |
3375 | sparc_tls_got (void) | |
3376 | { | |
3377 | rtx temp; | |
3378 | if (flag_pic) | |
3379 | { | |
3380 | current_function_uses_pic_offset_table = 1; | |
3381 | return pic_offset_table_rtx; | |
3382 | } | |
3383 | ||
3384 | if (!global_offset_table) | |
3385 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
3386 | temp = gen_reg_rtx (Pmode); | |
3387 | emit_move_insn (temp, global_offset_table); | |
3388 | return temp; | |
3389 | } | |
3390 | ||
3391 | ||
3392 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
3393 | this (thread-local) address. */ | |
3394 | ||
3395 | rtx | |
3396 | legitimize_tls_address (rtx addr) | |
3397 | { | |
3398 | rtx temp1, temp2, temp3, ret, o0, got, insn; | |
3399 | ||
3400 | if (no_new_pseudos) | |
3401 | abort (); | |
3402 | ||
3403 | if (GET_CODE (addr) == SYMBOL_REF) | |
3404 | switch (SYMBOL_REF_TLS_MODEL (addr)) | |
3405 | { | |
3406 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
3407 | start_sequence (); | |
3408 | temp1 = gen_reg_rtx (SImode); | |
3409 | temp2 = gen_reg_rtx (SImode); | |
3410 | ret = gen_reg_rtx (Pmode); | |
3411 | o0 = gen_rtx_REG (Pmode, 8); | |
3412 | got = sparc_tls_got (); | |
3413 | emit_insn (gen_tgd_hi22 (temp1, addr)); | |
3414 | emit_insn (gen_tgd_lo10 (temp2, temp1, addr)); | |
3415 | if (TARGET_ARCH32) | |
3416 | { | |
3417 | emit_insn (gen_tgd_add32 (o0, got, temp2, addr)); | |
3418 | insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (), | |
3419 | addr, const1_rtx)); | |
3420 | } | |
3421 | else | |
3422 | { | |
3423 | emit_insn (gen_tgd_add64 (o0, got, temp2, addr)); | |
3424 | insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (), | |
3425 | addr, const1_rtx)); | |
3426 | } | |
3427 | CALL_INSN_FUNCTION_USAGE (insn) | |
3428 | = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0), | |
3429 | CALL_INSN_FUNCTION_USAGE (insn)); | |
3430 | insn = get_insns (); | |
3431 | end_sequence (); | |
3432 | emit_libcall_block (insn, ret, o0, addr); | |
3433 | break; | |
3434 | ||
3435 | case TLS_MODEL_LOCAL_DYNAMIC: | |
3436 | start_sequence (); | |
3437 | temp1 = gen_reg_rtx (SImode); | |
3438 | temp2 = gen_reg_rtx (SImode); | |
3439 | temp3 = gen_reg_rtx (Pmode); | |
3440 | ret = gen_reg_rtx (Pmode); | |
3441 | o0 = gen_rtx_REG (Pmode, 8); | |
3442 | got = sparc_tls_got (); | |
3443 | emit_insn (gen_tldm_hi22 (temp1)); | |
3444 | emit_insn (gen_tldm_lo10 (temp2, temp1)); | |
3445 | if (TARGET_ARCH32) | |
3446 | { | |
3447 | emit_insn (gen_tldm_add32 (o0, got, temp2)); | |
3448 | insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (), | |
3449 | const1_rtx)); | |
3450 | } | |
3451 | else | |
3452 | { | |
3453 | emit_insn (gen_tldm_add64 (o0, got, temp2)); | |
3454 | insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (), | |
3455 | const1_rtx)); | |
3456 | } | |
3457 | CALL_INSN_FUNCTION_USAGE (insn) | |
3458 | = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0), | |
3459 | CALL_INSN_FUNCTION_USAGE (insn)); | |
3460 | insn = get_insns (); | |
3461 | end_sequence (); | |
3462 | emit_libcall_block (insn, temp3, o0, | |
3463 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
3464 | UNSPEC_TLSLD_BASE)); | |
3465 | temp1 = gen_reg_rtx (SImode); | |
3466 | temp2 = gen_reg_rtx (SImode); | |
3467 | emit_insn (gen_tldo_hix22 (temp1, addr)); | |
3468 | emit_insn (gen_tldo_lox10 (temp2, temp1, addr)); | |
3469 | if (TARGET_ARCH32) | |
3470 | emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr)); | |
3471 | else | |
3472 | emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr)); | |
3473 | break; | |
3474 | ||
3475 | case TLS_MODEL_INITIAL_EXEC: | |
3476 | temp1 = gen_reg_rtx (SImode); | |
3477 | temp2 = gen_reg_rtx (SImode); | |
3478 | temp3 = gen_reg_rtx (Pmode); | |
3479 | got = sparc_tls_got (); | |
3480 | emit_insn (gen_tie_hi22 (temp1, addr)); | |
3481 | emit_insn (gen_tie_lo10 (temp2, temp1, addr)); | |
3482 | if (TARGET_ARCH32) | |
3483 | emit_insn (gen_tie_ld32 (temp3, got, temp2, addr)); | |
3484 | else | |
3485 | emit_insn (gen_tie_ld64 (temp3, got, temp2, addr)); | |
3486 | if (TARGET_SUN_TLS) | |
3487 | { | |
3488 | ret = gen_reg_rtx (Pmode); | |
3489 | if (TARGET_ARCH32) | |
3490 | emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7), | |
3491 | temp3, addr)); | |
3492 | else | |
3493 | emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7), | |
3494 | temp3, addr)); | |
3495 | } | |
3496 | else | |
3497 | ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3); | |
3498 | break; | |
3499 | ||
3500 | case TLS_MODEL_LOCAL_EXEC: | |
3501 | temp1 = gen_reg_rtx (Pmode); | |
3502 | temp2 = gen_reg_rtx (Pmode); | |
3503 | if (TARGET_ARCH32) | |
3504 | { | |
3505 | emit_insn (gen_tle_hix22_sp32 (temp1, addr)); | |
3506 | emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr)); | |
3507 | } | |
3508 | else | |
3509 | { | |
3510 | emit_insn (gen_tle_hix22_sp64 (temp1, addr)); | |
3511 | emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr)); | |
3512 | } | |
3513 | ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2); | |
3514 | break; | |
3515 | ||
3516 | default: | |
3517 | abort (); | |
3518 | } | |
3519 | ||
3520 | else | |
3521 | abort (); /* for now ... */ | |
3522 | ||
3523 | return ret; | |
3524 | } | |
3525 | ||
3526 | ||
e0d80184 DM |
3527 | /* Legitimize PIC addresses. If the address is already position-independent, |
3528 | we return ORIG. Newly generated position-independent addresses go into a | |
88cad84b | 3529 | reg. This is REG if nonzero, otherwise we allocate register(s) as |
e0d80184 | 3530 | necessary. */ |
795068a4 | 3531 | |
e0d80184 | 3532 | rtx |
fc27d102 KG |
3533 | legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, |
3534 | rtx reg) | |
e0d80184 DM |
3535 | { |
3536 | if (GET_CODE (orig) == SYMBOL_REF) | |
82d6b402 | 3537 | { |
e0d80184 DM |
3538 | rtx pic_ref, address; |
3539 | rtx insn; | |
82d6b402 | 3540 | |
e0d80184 | 3541 | if (reg == 0) |
82d6b402 | 3542 | { |
e0d80184 DM |
3543 | if (reload_in_progress || reload_completed) |
3544 | abort (); | |
3545 | else | |
3546 | reg = gen_reg_rtx (Pmode); | |
82d6b402 | 3547 | } |
795068a4 | 3548 | |
e0d80184 | 3549 | if (flag_pic == 2) |
4fb4e4b8 | 3550 | { |
e0d80184 DM |
3551 | /* If not during reload, allocate another temp reg here for loading |
3552 | in the address, so that these instructions can be optimized | |
3553 | properly. */ | |
3554 | rtx temp_reg = ((reload_in_progress || reload_completed) | |
3555 | ? reg : gen_reg_rtx (Pmode)); | |
3556 | ||
3557 | /* Must put the SYMBOL_REF inside an UNSPEC here so that cse | |
3558 | won't get confused into thinking that these two instructions | |
3559 | are loading in the true address of the symbol. If in the | |
3560 | future a PIC rtx exists, that should be used instead. */ | |
be3f1ff5 DM |
3561 | if (Pmode == SImode) |
3562 | { | |
3563 | emit_insn (gen_movsi_high_pic (temp_reg, orig)); | |
3564 | emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
3565 | } | |
3566 | else | |
3567 | { | |
3568 | emit_insn (gen_movdi_high_pic (temp_reg, orig)); | |
3569 | emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
3570 | } | |
e0d80184 | 3571 | address = temp_reg; |
4fb4e4b8 DE |
3572 | } |
3573 | else | |
e0d80184 DM |
3574 | address = orig; |
3575 | ||
3576 | pic_ref = gen_rtx_MEM (Pmode, | |
8ac61af7 RK |
3577 | gen_rtx_PLUS (Pmode, |
3578 | pic_offset_table_rtx, address)); | |
e0d80184 DM |
3579 | current_function_uses_pic_offset_table = 1; |
3580 | RTX_UNCHANGING_P (pic_ref) = 1; | |
3581 | insn = emit_move_insn (reg, pic_ref); | |
3582 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
3583 | by loop. */ | |
3584 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, | |
3585 | REG_NOTES (insn)); | |
3586 | return reg; | |
795068a4 | 3587 | } |
e0d80184 | 3588 | else if (GET_CODE (orig) == CONST) |
795068a4 | 3589 | { |
e0d80184 | 3590 | rtx base, offset; |
795068a4 | 3591 | |
e0d80184 DM |
3592 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
3593 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
3594 | return orig; | |
82d6b402 | 3595 | |
e0d80184 | 3596 | if (reg == 0) |
4fb4e4b8 | 3597 | { |
e0d80184 DM |
3598 | if (reload_in_progress || reload_completed) |
3599 | abort (); | |
3600 | else | |
3601 | reg = gen_reg_rtx (Pmode); | |
4fb4e4b8 | 3602 | } |
e0d80184 DM |
3603 | |
3604 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
4fb4e4b8 | 3605 | { |
e0d80184 DM |
3606 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
3607 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
3608 | base == reg ? 0 : reg); | |
4fb4e4b8 DE |
3609 | } |
3610 | else | |
61a66555 JW |
3611 | abort (); |
3612 | ||
e0d80184 DM |
3613 | if (GET_CODE (offset) == CONST_INT) |
3614 | { | |
3615 | if (SMALL_INT (offset)) | |
ed8908e7 | 3616 | return plus_constant (base, INTVAL (offset)); |
e0d80184 DM |
3617 | else if (! reload_in_progress && ! reload_completed) |
3618 | offset = force_reg (Pmode, offset); | |
3619 | else | |
3620 | /* If we reach here, then something is seriously wrong. */ | |
3621 | abort (); | |
3622 | } | |
3623 | return gen_rtx_PLUS (Pmode, base, offset); | |
795068a4 | 3624 | } |
e0d80184 DM |
3625 | else if (GET_CODE (orig) == LABEL_REF) |
3626 | /* ??? Why do we do this? */ | |
3627 | /* Now movsi_pic_label_ref uses it, but we ought to be checking that | |
3628 | the register is live instead, in case it is eliminated. */ | |
3629 | current_function_uses_pic_offset_table = 1; | |
795068a4 | 3630 | |
e0d80184 DM |
3631 | return orig; |
3632 | } | |
795068a4 | 3633 | |
5751a10b JJ |
3634 | /* Try machine-dependent ways of modifying an illegitimate address X |
3635 | to be legitimate. If we find one, return the new, valid address. | |
3636 | ||
3637 | OLDX is the address as it was before break_out_memory_refs was called. | |
3638 | In some cases it is useful to look at this to decide what needs to be done. | |
3639 | ||
3640 | MODE is the mode of the operand pointed to by X. */ | |
3641 | ||
3642 | rtx | |
3643 | legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode) | |
3644 | { | |
3645 | rtx orig_x = x; | |
3646 | ||
3647 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT) | |
3648 | x = gen_rtx_PLUS (Pmode, XEXP (x, 1), | |
3649 | force_operand (XEXP (x, 0), NULL_RTX)); | |
3650 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT) | |
3651 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
3652 | force_operand (XEXP (x, 1), NULL_RTX)); | |
3653 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS) | |
3654 | x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX), | |
3655 | XEXP (x, 1)); | |
3656 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS) | |
3657 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
3658 | force_operand (XEXP (x, 1), NULL_RTX)); | |
3659 | ||
3660 | if (x != orig_x && legitimate_address_p (mode, x, FALSE)) | |
3661 | return x; | |
3662 | ||
3663 | if (tls_symbolic_operand (x)) | |
3664 | x = legitimize_tls_address (x); | |
3665 | else if (flag_pic) | |
3666 | x = legitimize_pic_address (x, mode, 0); | |
3667 | else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1))) | |
3668 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
3669 | copy_to_mode_reg (Pmode, XEXP (x, 1))); | |
3670 | else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0))) | |
3671 | x = gen_rtx_PLUS (Pmode, XEXP (x, 1), | |
3672 | copy_to_mode_reg (Pmode, XEXP (x, 0))); | |
3673 | else if (GET_CODE (x) == SYMBOL_REF | |
3674 | || GET_CODE (x) == CONST | |
3675 | || GET_CODE (x) == LABEL_REF) | |
3676 | x = copy_to_suggested_reg (x, NULL_RTX, Pmode); | |
3677 | return x; | |
3678 | } | |
3679 | ||
fccf9848 | 3680 | /* Emit special PIC prologues. */ |
795068a4 | 3681 | |
e0d80184 | 3682 | void |
fc27d102 | 3683 | load_pic_register (void) |
e0d80184 DM |
3684 | { |
3685 | /* Labels to get the PC in the prologue of this function. */ | |
3686 | int orig_flag_pic = flag_pic; | |
4fb4e4b8 | 3687 | |
e0d80184 DM |
3688 | if (! flag_pic) |
3689 | abort (); | |
3690 | ||
d6a7951f | 3691 | /* If we haven't emitted the special get_pc helper function, do so now. */ |
e0d80184 | 3692 | if (get_pc_symbol_name[0] == 0) |
4fb4e4b8 | 3693 | { |
d676da68 | 3694 | int align; |
82d6b402 | 3695 | |
d676da68 | 3696 | ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0); |
e0d80184 | 3697 | text_section (); |
d676da68 DM |
3698 | |
3699 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
3700 | if (align > 0) | |
3701 | ASM_OUTPUT_ALIGN (asm_out_file, align); | |
4977bab6 | 3702 | (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0); |
4df1190a | 3703 | fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file); |
e0d80184 | 3704 | } |
82d6b402 | 3705 | |
e0d80184 DM |
3706 | /* Initialize every time through, since we can't easily |
3707 | know this to be permanent. */ | |
3708 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
3709 | get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name); | |
3710 | flag_pic = 0; | |
82d6b402 | 3711 | |
fccf9848 JJ |
3712 | emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, |
3713 | get_pc_symbol)); | |
82d6b402 | 3714 | |
e0d80184 | 3715 | flag_pic = orig_flag_pic; |
82d6b402 | 3716 | |
e0d80184 DM |
3717 | /* Need to emit this whether or not we obey regdecls, |
3718 | since setjmp/longjmp can cause life info to screw up. | |
3719 | ??? In the case where we don't obey regdecls, this is not sufficient | |
3720 | since we may not fall out the bottom. */ | |
3721 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); | |
795068a4 | 3722 | } |
ab835497 | 3723 | \f |
e0d80184 | 3724 | /* Return 1 if RTX is a MEM which is known to be aligned to at |
7a31a340 | 3725 | least a DESIRED byte boundary. */ |
a3ee5899 | 3726 | |
e0d80184 | 3727 | int |
fc27d102 | 3728 | mem_min_alignment (rtx mem, int desired) |
ab835497 | 3729 | { |
e0d80184 DM |
3730 | rtx addr, base, offset; |
3731 | ||
3732 | /* If it's not a MEM we can't accept it. */ | |
3733 | if (GET_CODE (mem) != MEM) | |
3734 | return 0; | |
3735 | ||
3736 | addr = XEXP (mem, 0); | |
3737 | base = offset = NULL_RTX; | |
3738 | if (GET_CODE (addr) == PLUS) | |
ab835497 | 3739 | { |
e0d80184 | 3740 | if (GET_CODE (XEXP (addr, 0)) == REG) |
61a55e8b | 3741 | { |
e0d80184 DM |
3742 | base = XEXP (addr, 0); |
3743 | ||
3744 | /* What we are saying here is that if the base | |
3745 | REG is aligned properly, the compiler will make | |
3746 | sure any REG based index upon it will be so | |
3747 | as well. */ | |
3748 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3749 | offset = XEXP (addr, 1); | |
61a55e8b | 3750 | else |
e0d80184 | 3751 | offset = const0_rtx; |
61a55e8b | 3752 | } |
ab835497 | 3753 | } |
e0d80184 | 3754 | else if (GET_CODE (addr) == REG) |
ab835497 | 3755 | { |
e0d80184 DM |
3756 | base = addr; |
3757 | offset = const0_rtx; | |
ab835497 | 3758 | } |
82d6b402 | 3759 | |
e0d80184 | 3760 | if (base != NULL_RTX) |
795068a4 | 3761 | { |
e0d80184 DM |
3762 | int regno = REGNO (base); |
3763 | ||
563c12b0 | 3764 | if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM) |
61a55e8b | 3765 | { |
e0d80184 DM |
3766 | /* Check if the compiler has recorded some information |
3767 | about the alignment of the base REG. If reload has | |
021e2ecc JJ |
3768 | completed, we already matched with proper alignments. |
3769 | If not running global_alloc, reload might give us | |
3770 | unaligned pointer to local stack though. */ | |
bdb429a5 RK |
3771 | if (((cfun != 0 |
3772 | && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT) | |
021e2ecc | 3773 | || (optimize && reload_completed)) |
bdb429a5 | 3774 | && (INTVAL (offset) & (desired - 1)) == 0) |
e0d80184 | 3775 | return 1; |
61a55e8b | 3776 | } |
795068a4 | 3777 | else |
e0d80184 DM |
3778 | { |
3779 | if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) | |
3780 | return 1; | |
3781 | } | |
795068a4 | 3782 | } |
e0d80184 DM |
3783 | else if (! TARGET_UNALIGNED_DOUBLES |
3784 | || CONSTANT_P (addr) | |
3785 | || GET_CODE (addr) == LO_SUM) | |
795068a4 | 3786 | { |
e0d80184 DM |
3787 | /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES |
3788 | is true, in which case we can only assume that an access is aligned if | |
3789 | it is to a constant address, or the address involves a LO_SUM. */ | |
3790 | return 1; | |
795068a4 | 3791 | } |
e0d80184 DM |
3792 | |
3793 | /* An obviously unaligned address. */ | |
3794 | return 0; | |
795068a4 | 3795 | } |
e0d80184 | 3796 | |
ab835497 | 3797 | \f |
61a55e8b | 3798 | /* Vectors to keep interesting information about registers where it can easily |
01d3224a | 3799 | be got. We used to use the actual mode value as the bit number, but there |
61a55e8b DE |
3800 | are more than 32 modes now. Instead we use two tables: one indexed by |
3801 | hard register number, and one indexed by mode. */ | |
3802 | ||
3803 | /* The purpose of sparc_mode_class is to shrink the range of modes so that | |
3804 | they all fit (as bit numbers) in a 32 bit word (again). Each real mode is | |
3805 | mapped into one sparc_mode_class mode. */ | |
3806 | ||
3807 | enum sparc_mode_class { | |
61a55e8b | 3808 | S_MODE, D_MODE, T_MODE, O_MODE, |
c4ce6853 DE |
3809 | SF_MODE, DF_MODE, TF_MODE, OF_MODE, |
3810 | CC_MODE, CCFP_MODE | |
61a55e8b | 3811 | }; |
ab835497 | 3812 | |
61a55e8b DE |
3813 | /* Modes for single-word and smaller quantities. */ |
3814 | #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
3815 | ||
3816 | /* Modes for double-word and smaller quantities. */ | |
3817 | #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) | |
3818 | ||
3819 | /* Modes for quad-word and smaller quantities. */ | |
3820 | #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
ab835497 | 3821 | |
d0cee9ba JJ |
3822 | /* Modes for 8-word and smaller quantities. */ |
3823 | #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) | |
3824 | ||
1e4eb8d1 JW |
3825 | /* Modes for single-float quantities. We must allow any single word or |
3826 | smaller quantity. This is because the fix/float conversion instructions | |
3827 | take integer inputs/outputs from the float registers. */ | |
3828 | #define SF_MODES (S_MODES) | |
ab835497 | 3829 | |
61a55e8b DE |
3830 | /* Modes for double-float and smaller quantities. */ |
3831 | #define DF_MODES (S_MODES | D_MODES) | |
3832 | ||
61a55e8b | 3833 | /* Modes for double-float only quantities. */ |
38875aba | 3834 | #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) |
ab835497 | 3835 | |
61a55e8b DE |
3836 | /* Modes for quad-float only quantities. */ |
3837 | #define TF_ONLY_MODES (1 << (int) TF_MODE) | |
3838 | ||
3839 | /* Modes for quad-float and smaller quantities. */ | |
3840 | #define TF_MODES (DF_MODES | TF_ONLY_MODES) | |
3841 | ||
d0cee9ba JJ |
3842 | /* Modes for quad-float and double-float quantities. */ |
3843 | #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES) | |
3844 | ||
3845 | /* Modes for quad-float pair only quantities. */ | |
3846 | #define OF_ONLY_MODES (1 << (int) OF_MODE) | |
3847 | ||
3848 | /* Modes for quad-float pairs and smaller quantities. */ | |
3849 | #define OF_MODES (TF_MODES | OF_ONLY_MODES) | |
3850 | ||
3851 | #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES) | |
ab835497 | 3852 | |
c4ce6853 DE |
3853 | /* Modes for condition codes. */ |
3854 | #define CC_MODES (1 << (int) CC_MODE) | |
3855 | #define CCFP_MODES (1 << (int) CCFP_MODE) | |
3856 | ||
ab835497 RK |
3857 | /* Value is 1 if register/mode pair is acceptable on sparc. |
3858 | The funny mixture of D and T modes is because integer operations | |
3859 | do not specially operate on tetra quantities, so non-quad-aligned | |
3860 | registers can hold quadword quantities (except %o4 and %i4 because | |
c4ce6853 | 3861 | they cross fixed registers). */ |
ab835497 | 3862 | |
61a55e8b | 3863 | /* This points to either the 32 bit or the 64 bit version. */ |
0b5826ac | 3864 | const int *hard_regno_mode_classes; |
61a55e8b | 3865 | |
0b5826ac | 3866 | static const int hard_32bit_mode_classes[] = { |
c4ce6853 | 3867 | S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, |
ab835497 RK |
3868 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, |
3869 | T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
3870 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
3871 | ||
d0cee9ba JJ |
3872 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
3873 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3874 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3875 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
a9e27770 DE |
3876 | |
3877 | /* FP regs f32 to f63. Only the even numbered registers actually exist, | |
3878 | and none can hold SFmode/SImode values. */ | |
d0cee9ba JJ |
3879 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
3880 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3881 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3882 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
a9e27770 DE |
3883 | |
3884 | /* %fcc[0123] */ | |
c4ce6853 DE |
3885 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
3886 | ||
3887 | /* %icc */ | |
3888 | CC_MODES | |
61a55e8b DE |
3889 | }; |
3890 | ||
0b5826ac | 3891 | static const int hard_64bit_mode_classes[] = { |
c4ce6853 | 3892 | D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 3893 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 3894 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 3895 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 3896 | |
d0cee9ba JJ |
3897 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
3898 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3899 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3900 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
61a55e8b | 3901 | |
a9e27770 | 3902 | /* FP regs f32 to f63. Only the even numbered registers actually exist, |
61a55e8b | 3903 | and none can hold SFmode/SImode values. */ |
d0cee9ba JJ |
3904 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
3905 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3906 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3907 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
61a55e8b DE |
3908 | |
3909 | /* %fcc[0123] */ | |
c4ce6853 DE |
3910 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
3911 | ||
3912 | /* %icc */ | |
3913 | CC_MODES | |
61a55e8b DE |
3914 | }; |
3915 | ||
3916 | int sparc_mode_class [NUM_MACHINE_MODES]; | |
3917 | ||
c4ce6853 DE |
3918 | enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
3919 | ||
61a55e8b | 3920 | static void |
fc27d102 | 3921 | sparc_init_modes (void) |
61a55e8b DE |
3922 | { |
3923 | int i; | |
3924 | ||
61a55e8b DE |
3925 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
3926 | { | |
3927 | switch (GET_MODE_CLASS (i)) | |
3928 | { | |
3929 | case MODE_INT: | |
3930 | case MODE_PARTIAL_INT: | |
3931 | case MODE_COMPLEX_INT: | |
3932 | if (GET_MODE_SIZE (i) <= 4) | |
3933 | sparc_mode_class[i] = 1 << (int) S_MODE; | |
3934 | else if (GET_MODE_SIZE (i) == 8) | |
3935 | sparc_mode_class[i] = 1 << (int) D_MODE; | |
3936 | else if (GET_MODE_SIZE (i) == 16) | |
3937 | sparc_mode_class[i] = 1 << (int) T_MODE; | |
3938 | else if (GET_MODE_SIZE (i) == 32) | |
3939 | sparc_mode_class[i] = 1 << (int) O_MODE; | |
3940 | else | |
3941 | sparc_mode_class[i] = 0; | |
3942 | break; | |
3943 | case MODE_FLOAT: | |
3944 | case MODE_COMPLEX_FLOAT: | |
3945 | if (GET_MODE_SIZE (i) <= 4) | |
3946 | sparc_mode_class[i] = 1 << (int) SF_MODE; | |
3947 | else if (GET_MODE_SIZE (i) == 8) | |
3948 | sparc_mode_class[i] = 1 << (int) DF_MODE; | |
3949 | else if (GET_MODE_SIZE (i) == 16) | |
3950 | sparc_mode_class[i] = 1 << (int) TF_MODE; | |
3951 | else if (GET_MODE_SIZE (i) == 32) | |
3952 | sparc_mode_class[i] = 1 << (int) OF_MODE; | |
3953 | else | |
3954 | sparc_mode_class[i] = 0; | |
3955 | break; | |
3956 | case MODE_CC: | |
3957 | default: | |
3958 | /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so | |
3959 | we must explicitly check for them here. */ | |
3960 | if (i == (int) CCFPmode || i == (int) CCFPEmode) | |
3961 | sparc_mode_class[i] = 1 << (int) CCFP_MODE; | |
3962 | else if (i == (int) CCmode || i == (int) CC_NOOVmode | |
a9e27770 | 3963 | || i == (int) CCXmode || i == (int) CCX_NOOVmode) |
c4ce6853 | 3964 | sparc_mode_class[i] = 1 << (int) CC_MODE; |
61a55e8b DE |
3965 | else |
3966 | sparc_mode_class[i] = 0; | |
3967 | break; | |
3968 | } | |
3969 | } | |
3970 | ||
a9e27770 | 3971 | if (TARGET_ARCH64) |
61a55e8b DE |
3972 | hard_regno_mode_classes = hard_64bit_mode_classes; |
3973 | else | |
3974 | hard_regno_mode_classes = hard_32bit_mode_classes; | |
c4ce6853 DE |
3975 | |
3976 | /* Initialize the array used by REGNO_REG_CLASS. */ | |
3977 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3978 | { | |
284d86e9 JC |
3979 | if (i < 16 && TARGET_V8PLUS) |
3980 | sparc_regno_reg_class[i] = I64_REGS; | |
563c12b0 | 3981 | else if (i < 32 || i == FRAME_POINTER_REGNUM) |
c4ce6853 DE |
3982 | sparc_regno_reg_class[i] = GENERAL_REGS; |
3983 | else if (i < 64) | |
3984 | sparc_regno_reg_class[i] = FP_REGS; | |
3985 | else if (i < 96) | |
3986 | sparc_regno_reg_class[i] = EXTRA_FP_REGS; | |
3987 | else if (i < 100) | |
3988 | sparc_regno_reg_class[i] = FPCC_REGS; | |
3989 | else | |
3990 | sparc_regno_reg_class[i] = NO_REGS; | |
3991 | } | |
61a55e8b | 3992 | } |
ab835497 | 3993 | \f |
61a55e8b DE |
3994 | /* Save non call used registers from LOW to HIGH at BASE+OFFSET. |
3995 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
3996 | v9 int regs as it simplifies the code. */ | |
3997 | ||
ab835497 | 3998 | static int |
fc27d102 KG |
3999 | save_regs (FILE *file, int low, int high, const char *base, |
4000 | int offset, int n_regs, int real_offset) | |
ab835497 RK |
4001 | { |
4002 | int i; | |
4003 | ||
a9e27770 | 4004 | if (TARGET_ARCH64 && high <= 32) |
ab835497 | 4005 | { |
61a55e8b DE |
4006 | for (i = low; i < high; i++) |
4007 | { | |
4008 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 4009 | { |
e0d80184 | 4010 | fprintf (file, "\tstx\t%s, [%s+%d]\n", |
c53aa195 | 4011 | reg_names[i], base, offset + 4 * n_regs); |
0021b564 | 4012 | if (dwarf2out_do_frame ()) |
c53aa195 | 4013 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); |
c53aa195 JM |
4014 | n_regs += 2; |
4015 | } | |
61a55e8b | 4016 | } |
ab835497 | 4017 | } |
61a55e8b DE |
4018 | else |
4019 | { | |
4020 | for (i = low; i < high; i += 2) | |
4021 | { | |
4022 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 4023 | { |
5e9defae KG |
4024 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) |
4025 | { | |
e0d80184 | 4026 | fprintf (file, "\tstd\t%s, [%s+%d]\n", |
5e9defae KG |
4027 | reg_names[i], base, offset + 4 * n_regs); |
4028 | if (dwarf2out_do_frame ()) | |
4029 | { | |
4030 | char *l = dwarf2out_cfi_label (); | |
4031 | dwarf2out_reg_save (l, i, real_offset + 4 * n_regs); | |
4032 | dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4); | |
4033 | } | |
4034 | n_regs += 2; | |
4035 | } | |
4036 | else | |
4037 | { | |
e0d80184 | 4038 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
4039 | reg_names[i], base, offset + 4 * n_regs); |
4040 | if (dwarf2out_do_frame ()) | |
4041 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); | |
4042 | n_regs += 2; | |
4043 | } | |
4044 | } | |
4045 | else | |
4046 | { | |
4047 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
4048 | { | |
e0d80184 | 4049 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
4050 | reg_names[i+1], base, offset + 4 * n_regs + 4); |
4051 | if (dwarf2out_do_frame ()) | |
4052 | dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4); | |
4053 | n_regs += 2; | |
4054 | } | |
c53aa195 | 4055 | } |
61a55e8b DE |
4056 | } |
4057 | } | |
4058 | return n_regs; | |
ab835497 RK |
4059 | } |
4060 | ||
61a55e8b DE |
4061 | /* Restore non call used registers from LOW to HIGH at BASE+OFFSET. |
4062 | ||
4063 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
4064 | v9 int regs as it simplifies the code. */ | |
4065 | ||
ab835497 | 4066 | static int |
fc27d102 KG |
4067 | restore_regs (FILE *file, int low, int high, const char *base, |
4068 | int offset, int n_regs) | |
ab835497 RK |
4069 | { |
4070 | int i; | |
4071 | ||
a9e27770 | 4072 | if (TARGET_ARCH64 && high <= 32) |
61a55e8b DE |
4073 | { |
4074 | for (i = low; i < high; i++) | |
4075 | { | |
4076 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
e0d80184 | 4077 | fprintf (file, "\tldx\t[%s+%d], %s\n", |
61a55e8b DE |
4078 | base, offset + 4 * n_regs, reg_names[i]), |
4079 | n_regs += 2; | |
4080 | } | |
4081 | } | |
4082 | else | |
ab835497 | 4083 | { |
61a55e8b DE |
4084 | for (i = low; i < high; i += 2) |
4085 | { | |
4086 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
4087 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
e0d80184 | 4088 | fprintf (file, "\tldd\t[%s+%d], %s\n", |
61a55e8b DE |
4089 | base, offset + 4 * n_regs, reg_names[i]), |
4090 | n_regs += 2; | |
4091 | else | |
4df1190a | 4092 | fprintf (file, "\tld\t[%s+%d], %s\n", |
61a55e8b DE |
4093 | base, offset + 4 * n_regs, reg_names[i]), |
4094 | n_regs += 2; | |
4095 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
4df1190a | 4096 | fprintf (file, "\tld\t[%s+%d], %s\n", |
61a55e8b DE |
4097 | base, offset + 4 * n_regs + 4, reg_names[i+1]), |
4098 | n_regs += 2; | |
4099 | } | |
ab835497 | 4100 | } |
61a55e8b | 4101 | return n_regs; |
ab835497 RK |
4102 | } |
4103 | ||
61a55e8b DE |
4104 | /* Compute the frame size required by the function. This function is called |
4105 | during the reload pass and also by output_function_prologue(). */ | |
ab835497 | 4106 | |
ab835497 | 4107 | int |
fc27d102 | 4108 | compute_frame_size (int size, int leaf_function) |
ab835497 | 4109 | { |
61a55e8b | 4110 | int n_regs = 0, i; |
ab835497 | 4111 | int outgoing_args_size = (current_function_outgoing_args_size |
4fb4e4b8 | 4112 | + REG_PARM_STACK_SPACE (current_function_decl)); |
ab835497 | 4113 | |
33074e5f RH |
4114 | /* N_REGS is the number of 4-byte regs saved thus far. This applies |
4115 | even to v9 int regs to be consistent with save_regs/restore_regs. */ | |
61a55e8b | 4116 | |
33074e5f RH |
4117 | if (TARGET_ARCH64) |
4118 | { | |
4119 | for (i = 0; i < 8; i++) | |
4120 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
4121 | n_regs += 2; | |
4122 | } | |
4123 | else | |
4124 | { | |
4125 | for (i = 0; i < 8; i += 2) | |
ab835497 RK |
4126 | if ((regs_ever_live[i] && ! call_used_regs[i]) |
4127 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
61a55e8b | 4128 | n_regs += 2; |
ab835497 RK |
4129 | } |
4130 | ||
33074e5f RH |
4131 | for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) |
4132 | if ((regs_ever_live[i] && ! call_used_regs[i]) | |
4133 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
4134 | n_regs += 2; | |
4135 | ||
ab835497 | 4136 | /* Set up values for use in `function_epilogue'. */ |
61a55e8b | 4137 | num_gfregs = n_regs; |
ab835497 | 4138 | |
61a55e8b DE |
4139 | if (leaf_function && n_regs == 0 |
4140 | && size == 0 && current_function_outgoing_args_size == 0) | |
4141 | { | |
4142 | actual_fsize = apparent_fsize = 0; | |
4143 | } | |
4144 | else | |
4145 | { | |
225909c3 JS |
4146 | /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */ |
4147 | apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8; | |
61a55e8b DE |
4148 | apparent_fsize += n_regs * 4; |
4149 | actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); | |
4150 | } | |
ab835497 RK |
4151 | |
4152 | /* Make sure nothing can clobber our register windows. | |
4153 | If a SAVE must be done, or there is a stack-local variable, | |
61a55e8b | 4154 | the register window area must be allocated. |
4fb4e4b8 | 4155 | ??? For v8 we apparently need an additional 8 bytes of reserved space. */ |
ab835497 | 4156 | if (leaf_function == 0 || size > 0) |
4fb4e4b8 | 4157 | actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8); |
ab835497 | 4158 | |
61a55e8b DE |
4159 | return SPARC_STACK_ALIGN (actual_fsize); |
4160 | } | |
4161 | ||
4162 | /* Build a (32 bit) big number in a register. */ | |
86735b02 | 4163 | /* ??? We may be able to use the set macro here too. */ |
61a55e8b DE |
4164 | |
4165 | static void | |
fc27d102 | 4166 | build_big_number (FILE *file, int num, const char *reg) |
61a55e8b | 4167 | { |
a9e27770 | 4168 | if (num >= 0 || ! TARGET_ARCH64) |
61a55e8b | 4169 | { |
e0d80184 | 4170 | fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg); |
61a55e8b | 4171 | if ((num & 0x3ff) != 0) |
e0d80184 | 4172 | fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg); |
61a55e8b | 4173 | } |
a9e27770 | 4174 | else /* num < 0 && TARGET_ARCH64 */ |
61a55e8b DE |
4175 | { |
4176 | /* Sethi does not sign extend, so we must use a little trickery | |
4177 | to use it for negative numbers. Invert the constant before | |
4178 | loading it in, then use xor immediate to invert the loaded bits | |
4179 | (along with the upper 32 bits) to the desired constant. This | |
4180 | works because the sethi and immediate fields overlap. */ | |
4181 | int asize = num; | |
4182 | int inv = ~asize; | |
4183 | int low = -0x400 + (asize & 0x3FF); | |
4184 | ||
e0d80184 | 4185 | fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n", |
61a55e8b DE |
4186 | inv, reg, reg, low, reg); |
4187 | } | |
ab835497 RK |
4188 | } |
4189 | ||
1cb36a98 RH |
4190 | /* Output any necessary .register pseudo-ops. */ |
4191 | void | |
fc27d102 | 4192 | sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED) |
1cb36a98 RH |
4193 | { |
4194 | #ifdef HAVE_AS_REGISTER_PSEUDO_OP | |
4195 | int i; | |
4196 | ||
4197 | if (TARGET_ARCH32) | |
4198 | return; | |
4199 | ||
4200 | /* Check if %g[2367] were used without | |
4201 | .register being printed for them already. */ | |
4202 | for (i = 2; i < 8; i++) | |
4203 | { | |
4204 | if (regs_ever_live [i] | |
4205 | && ! sparc_hard_reg_printed [i]) | |
4206 | { | |
4207 | sparc_hard_reg_printed [i] = 1; | |
4208 | fprintf (file, "\t.register\t%%g%d, #scratch\n", i); | |
4209 | } | |
4210 | if (i == 3) i = 5; | |
4211 | } | |
4212 | #endif | |
4213 | } | |
4214 | ||
08c148a8 NB |
4215 | /* This function generates the assembly code for function entry. |
4216 | FILE is a stdio stream to output the code to. | |
4217 | SIZE is an int: how many units of temporary storage to allocate. | |
4218 | Refer to the array `regs_ever_live' to determine which registers | |
4219 | to save; `regs_ever_live[I]' is nonzero if register number I | |
4220 | is ever used in the function. This macro is responsible for | |
4221 | knowing which registers should not be saved even if used. */ | |
4222 | ||
4223 | /* On SPARC, move-double insns between fpu and cpu need an 8-byte block | |
4224 | of memory. If any fpu reg is used in the function, we allocate | |
4225 | such a block here, at the bottom of the frame, just in case it's needed. | |
4226 | ||
4227 | If this function is a leaf procedure, then we may choose not | |
4228 | to do a "save" insn. The decision about whether or not | |
4229 | to do this is made in regclass.c. */ | |
4230 | ||
4231 | static void | |
fc27d102 | 4232 | sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size) |
08c148a8 NB |
4233 | { |
4234 | if (TARGET_FLAT) | |
4235 | sparc_flat_function_prologue (file, size); | |
4236 | else | |
4237 | sparc_nonflat_function_prologue (file, size, | |
4238 | current_function_uses_only_leaf_regs); | |
4239 | } | |
4240 | ||
915f619f JW |
4241 | /* Output code for the function prologue. */ |
4242 | ||
08c148a8 | 4243 | static void |
fc27d102 KG |
4244 | sparc_nonflat_function_prologue (FILE *file, HOST_WIDE_INT size, |
4245 | int leaf_function) | |
ab835497 | 4246 | { |
1cb36a98 RH |
4247 | sparc_output_scratch_registers (file); |
4248 | ||
915f619f JW |
4249 | /* Need to use actual_fsize, since we are also allocating |
4250 | space for our callee (and our own register save area). */ | |
ab835497 RK |
4251 | actual_fsize = compute_frame_size (size, leaf_function); |
4252 | ||
61a55e8b DE |
4253 | if (leaf_function) |
4254 | { | |
4255 | frame_base_name = "%sp"; | |
4256 | frame_base_offset = actual_fsize + SPARC_STACK_BIAS; | |
4257 | } | |
4258 | else | |
4259 | { | |
4260 | frame_base_name = "%fp"; | |
4261 | frame_base_offset = SPARC_STACK_BIAS; | |
4262 | } | |
4263 | ||
c6aa9ce1 | 4264 | /* This is only for the human reader. */ |
bf62bbf1 | 4265 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
c6aa9ce1 | 4266 | |
915f619f JW |
4267 | if (actual_fsize == 0) |
4268 | /* do nothing. */ ; | |
e6c1be7e | 4269 | else if (! leaf_function) |
ab835497 | 4270 | { |
3592ea0d | 4271 | if (actual_fsize <= 4096) |
e0d80184 | 4272 | fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize); |
3592ea0d | 4273 | else if (actual_fsize <= 8192) |
915f619f | 4274 | { |
e0d80184 DM |
4275 | fprintf (file, "\tsave\t%%sp, -4096, %%sp\n"); |
4276 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); | |
915f619f JW |
4277 | } |
4278 | else | |
4279 | { | |
3592ea0d | 4280 | build_big_number (file, -actual_fsize, "%g1"); |
e0d80184 | 4281 | fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); |
915f619f | 4282 | } |
ab835497 | 4283 | } |
5f4241d5 DE |
4284 | else /* leaf function */ |
4285 | { | |
3592ea0d | 4286 | if (actual_fsize <= 4096) |
e0d80184 | 4287 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize); |
3592ea0d DE |
4288 | else if (actual_fsize <= 8192) |
4289 | { | |
e0d80184 DM |
4290 | fprintf (file, "\tadd\t%%sp, -4096, %%sp\n"); |
4291 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); | |
3592ea0d | 4292 | } |
915f619f | 4293 | else |
3592ea0d DE |
4294 | { |
4295 | build_big_number (file, -actual_fsize, "%g1"); | |
e0d80184 | 4296 | fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n"); |
3592ea0d | 4297 | } |
ab835497 RK |
4298 | } |
4299 | ||
0021b564 | 4300 | if (dwarf2out_do_frame () && actual_fsize) |
c53aa195 | 4301 | { |
96987e96 | 4302 | char *label = dwarf2out_cfi_label (); |
c53aa195 JM |
4303 | |
4304 | /* The canonical frame address refers to the top of the frame. */ | |
4305 | dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM | |
563c12b0 | 4306 | : HARD_FRAME_POINTER_REGNUM), |
c53aa195 JM |
4307 | frame_base_offset); |
4308 | ||
4309 | if (! leaf_function) | |
4310 | { | |
4311 | /* Note the register window save. This tells the unwinder that | |
4312 | it needs to restore the window registers from the previous | |
4313 | frame's window save area at 0(cfa). */ | |
4314 | dwarf2out_window_save (label); | |
4315 | ||
4316 | /* The return address (-8) is now in %i7. */ | |
4317 | dwarf2out_return_reg (label, 31); | |
4318 | } | |
4319 | } | |
c53aa195 | 4320 | |
ab835497 RK |
4321 | /* If doing anything with PIC, do it now. */ |
4322 | if (! flag_pic) | |
bf62bbf1 | 4323 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
ab835497 | 4324 | |
61a55e8b DE |
4325 | /* Call saved registers are saved just above the outgoing argument area. */ |
4326 | if (num_gfregs) | |
ab835497 | 4327 | { |
c53aa195 | 4328 | int offset, real_offset, n_regs; |
3bb5de61 | 4329 | const char *base; |
ab835497 | 4330 | |
84e884e9 JM |
4331 | real_offset = -apparent_fsize; |
4332 | offset = -apparent_fsize + frame_base_offset; | |
61a55e8b DE |
4333 | if (offset < -4096 || offset + num_gfregs * 4 > 4096) |
4334 | { | |
4335 | /* ??? This might be optimized a little as %g1 might already have a | |
4336 | value close enough that a single add insn will do. */ | |
4337 | /* ??? Although, all of this is probably only a temporary fix | |
4338 | because if %g1 can hold a function result, then | |
4339 | output_function_epilogue will lose (the result will get | |
4340 | clobbered). */ | |
4341 | build_big_number (file, offset, "%g1"); | |
e0d80184 | 4342 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); |
61a55e8b DE |
4343 | base = "%g1"; |
4344 | offset = 0; | |
4345 | } | |
ab835497 | 4346 | else |
61a55e8b DE |
4347 | { |
4348 | base = frame_base_name; | |
4349 | } | |
ab835497 | 4350 | |
33074e5f RH |
4351 | n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); |
4352 | save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs, | |
4353 | real_offset); | |
ab835497 RK |
4354 | } |
4355 | } | |
4356 | ||
7d167afd JJ |
4357 | /* Output code to restore any call saved registers. */ |
4358 | ||
4359 | static void | |
fc27d102 | 4360 | output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED) |
7d167afd JJ |
4361 | { |
4362 | int offset, n_regs; | |
4363 | const char *base; | |
4364 | ||
4365 | offset = -apparent_fsize + frame_base_offset; | |
4366 | if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) | |
4367 | { | |
4368 | build_big_number (file, offset, "%g1"); | |
4369 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); | |
4370 | base = "%g1"; | |
4371 | offset = 0; | |
4372 | } | |
4373 | else | |
4374 | { | |
4375 | base = frame_base_name; | |
4376 | } | |
4377 | ||
33074e5f RH |
4378 | n_regs = restore_regs (file, 0, 8, base, offset, 0); |
4379 | restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); | |
7d167afd JJ |
4380 | } |
4381 | ||
08c148a8 NB |
4382 | /* This function generates the assembly code for function exit, |
4383 | on machines that need it. | |
4384 | ||
4385 | The function epilogue should not depend on the current stack pointer! | |
4386 | It should use the frame pointer only. This is mandatory because | |
4387 | of alloca; we also take advantage of it to omit stack adjustments | |
4388 | before returning. */ | |
4389 | ||
4390 | static void | |
fc27d102 | 4391 | sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size) |
08c148a8 NB |
4392 | { |
4393 | if (TARGET_FLAT) | |
4394 | sparc_flat_function_epilogue (file, size); | |
4395 | else | |
4396 | sparc_nonflat_function_epilogue (file, size, | |
4397 | current_function_uses_only_leaf_regs); | |
4398 | } | |
4399 | ||
915f619f JW |
4400 | /* Output code for the function epilogue. */ |
4401 | ||
08c148a8 | 4402 | static void |
fc27d102 KG |
4403 | sparc_nonflat_function_epilogue (FILE *file, |
4404 | HOST_WIDE_INT size ATTRIBUTE_UNUSED, | |
4405 | int leaf_function) | |
ab835497 | 4406 | { |
3bb5de61 | 4407 | const char *ret; |
ab835497 | 4408 | |
8456b95a | 4409 | if (current_function_epilogue_delay_list == 0) |
e48addee | 4410 | { |
e0d80184 | 4411 | /* If code does not drop into the epilogue, we need |
7a31a340 DM |
4412 | do nothing except output pending case vectors. |
4413 | ||
4414 | We have to still output a dummy nop for the sake of | |
4415 | sane backtraces. Otherwise, if the last two instructions | |
4416 | of a function were call foo; dslot; this can make the return | |
4417 | PC of foo (ie. address of call instruction plus 8) point to | |
4418 | the first instruction in the next function. */ | |
ac59ed37 | 4419 | rtx insn, last_real_insn; |
7a31a340 DM |
4420 | |
4421 | insn = get_last_insn (); | |
ac59ed37 DM |
4422 | |
4423 | last_real_insn = prev_real_insn (insn); | |
4424 | if (last_real_insn | |
4425 | && GET_CODE (last_real_insn) == INSN | |
4426 | && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE) | |
4427 | last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0); | |
4428 | ||
4429 | if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN) | |
4430 | fputs("\tnop\n", file); | |
4431 | ||
7a31a340 DM |
4432 | if (GET_CODE (insn) == NOTE) |
4433 | insn = prev_nonnote_insn (insn); | |
4434 | if (insn && GET_CODE (insn) == BARRIER) | |
4435 | goto output_vectors; | |
bfd6bc60 JC |
4436 | } |
4437 | ||
61a55e8b | 4438 | if (num_gfregs) |
7d167afd | 4439 | output_restore_regs (file, leaf_function); |
ab835497 RK |
4440 | |
4441 | /* Work out how to skip the caller's unimp instruction if required. */ | |
4442 | if (leaf_function) | |
e0d80184 | 4443 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl"); |
ab835497 | 4444 | else |
e0d80184 | 4445 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret"); |
ab835497 | 4446 | |
33074e5f | 4447 | if (! leaf_function) |
ab835497 | 4448 | { |
33074e5f RH |
4449 | if (current_function_calls_eh_return) |
4450 | { | |
4451 | if (current_function_epilogue_delay_list) | |
4452 | abort (); | |
4453 | if (SKIP_CALLERS_UNIMP_P) | |
4454 | abort (); | |
ab835497 | 4455 | |
33074e5f RH |
4456 | fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file); |
4457 | } | |
4458 | /* If we wound up with things in our delay slot, flush them here. */ | |
4459 | else if (current_function_epilogue_delay_list) | |
ef8200df | 4460 | { |
33074e5f | 4461 | rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0)); |
1150a841 | 4462 | |
33074e5f RH |
4463 | if (TARGET_V9 && ! epilogue_renumber (&delay, 1)) |
4464 | { | |
4465 | epilogue_renumber (&delay, 0); | |
4466 | fputs (SKIP_CALLERS_UNIMP_P | |
4467 | ? "\treturn\t%i7+12\n" | |
4468 | : "\treturn\t%i7+8\n", file); | |
4469 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
4470 | file, 1, 0, 0); | |
1150a841 | 4471 | } |
33074e5f | 4472 | else |
ab835497 | 4473 | { |
33074e5f | 4474 | rtx insn, src; |
e48addee | 4475 | |
33074e5f RH |
4476 | if (GET_CODE (delay) != SET) |
4477 | abort(); | |
e48addee | 4478 | |
33074e5f RH |
4479 | src = SET_SRC (delay); |
4480 | if (GET_CODE (src) == ASHIFT) | |
4481 | { | |
4482 | if (XEXP (src, 1) != const1_rtx) | |
e48addee | 4483 | abort(); |
33074e5f RH |
4484 | SET_SRC (delay) |
4485 | = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0), | |
4486 | XEXP (src, 0)); | |
4487 | } | |
e48addee | 4488 | |
33074e5f RH |
4489 | insn = gen_rtx_PARALLEL (VOIDmode, |
4490 | gen_rtvec (2, delay, | |
4491 | gen_rtx_RETURN (VOIDmode))); | |
4492 | insn = emit_jump_insn (insn); | |
e48addee | 4493 | |
33074e5f RH |
4494 | sparc_emitting_epilogue = true; |
4495 | final_scan_insn (insn, file, 1, 0, 1); | |
4496 | sparc_emitting_epilogue = false; | |
ab835497 | 4497 | } |
ef8200df | 4498 | } |
33074e5f RH |
4499 | else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P) |
4500 | fputs ("\treturn\t%i7+8\n\tnop\n", file); | |
4501 | else | |
4502 | fprintf (file, "\t%s\n\trestore\n", ret); | |
4503 | } | |
4504 | /* All of the following cases are for leaf functions. */ | |
4505 | else if (current_function_calls_eh_return) | |
4506 | abort (); | |
4507 | else if (current_function_epilogue_delay_list) | |
4508 | { | |
4509 | /* eligible_for_epilogue_delay_slot ensures that if this is a | |
4510 | leaf function, then we will only have insn in the delay slot | |
4511 | if the frame size is zero, thus no adjust for the stack is | |
4512 | needed here. */ | |
4513 | if (actual_fsize != 0) | |
1150a841 | 4514 | abort (); |
33074e5f RH |
4515 | fprintf (file, "\t%s\n", ret); |
4516 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
4517 | file, 1, 0, 1); | |
ab835497 | 4518 | } |
33074e5f RH |
4519 | /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to |
4520 | avoid generating confusing assembly language output. */ | |
4521 | else if (actual_fsize == 0) | |
4522 | fprintf (file, "\t%s\n\tnop\n", ret); | |
4523 | else if (actual_fsize <= 4096) | |
4524 | fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize); | |
4525 | else if (actual_fsize <= 8192) | |
4526 | fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n", | |
4527 | ret, actual_fsize - 4096); | |
4528 | else if ((actual_fsize & 0x3ff) == 0) | |
4529 | fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", | |
4530 | actual_fsize, ret); | |
4531 | else | |
4532 | fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", | |
4533 | actual_fsize, actual_fsize, ret); | |
e0d80184 DM |
4534 | |
4535 | output_vectors: | |
4536 | sparc_output_deferred_case_vectors (); | |
ab835497 | 4537 | } |
7d167afd JJ |
4538 | |
4539 | /* Output a sibling call. */ | |
4540 | ||
4541 | const char * | |
fc27d102 | 4542 | output_sibcall (rtx insn, rtx call_operand) |
7d167afd JJ |
4543 | { |
4544 | int leaf_regs = current_function_uses_only_leaf_regs; | |
4545 | rtx operands[3]; | |
4546 | int delay_slot = dbr_sequence_length () > 0; | |
4547 | ||
4548 | if (num_gfregs) | |
4549 | { | |
4550 | /* Call to restore global regs might clobber | |
4551 | the delay slot. Instead of checking for this | |
4552 | output the delay slot now. */ | |
4553 | if (delay_slot) | |
4554 | { | |
4555 | rtx delay = NEXT_INSN (insn); | |
4556 | ||
4557 | if (! delay) | |
4558 | abort (); | |
4559 | ||
4560 | final_scan_insn (delay, asm_out_file, 1, 0, 1); | |
4561 | PATTERN (delay) = gen_blockage (); | |
4562 | INSN_CODE (delay) = -1; | |
4563 | delay_slot = 0; | |
4564 | } | |
4565 | output_restore_regs (asm_out_file, leaf_regs); | |
4566 | } | |
4567 | ||
4568 | operands[0] = call_operand; | |
4569 | ||
4570 | if (leaf_regs) | |
4571 | { | |
e95b1e6a JJ |
4572 | #ifdef HAVE_AS_RELAX_OPTION |
4573 | /* If as and ld are relaxing tail call insns into branch always, | |
4574 | use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can | |
4575 | be optimized. With sethi/jmpl as nor ld has no easy way how to | |
4576 | find out if somebody does not branch between the sethi and jmpl. */ | |
4577 | int spare_slot = 0; | |
4578 | #else | |
2be5e524 | 4579 | int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic); |
e95b1e6a | 4580 | #endif |
7d167afd JJ |
4581 | int size = 0; |
4582 | ||
4583 | if ((actual_fsize || ! spare_slot) && delay_slot) | |
4584 | { | |
4585 | rtx delay = NEXT_INSN (insn); | |
4586 | ||
4587 | if (! delay) | |
4588 | abort (); | |
4589 | ||
4590 | final_scan_insn (delay, asm_out_file, 1, 0, 1); | |
4591 | PATTERN (delay) = gen_blockage (); | |
4592 | INSN_CODE (delay) = -1; | |
4593 | delay_slot = 0; | |
4594 | } | |
4595 | if (actual_fsize) | |
4596 | { | |
4597 | if (actual_fsize <= 4096) | |
4598 | size = actual_fsize; | |
4599 | else if (actual_fsize <= 8192) | |
4600 | { | |
4601 | fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file); | |
4602 | size = actual_fsize - 4096; | |
4603 | } | |
4604 | else if ((actual_fsize & 0x3ff) == 0) | |
4605 | fprintf (asm_out_file, | |
4606 | "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n", | |
4607 | actual_fsize); | |
4608 | else | |
4609 | { | |
4610 | fprintf (asm_out_file, | |
4611 | "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n", | |
4612 | actual_fsize, actual_fsize); | |
4613 | fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file); | |
4614 | } | |
4615 | } | |
4616 | if (spare_slot) | |
4617 | { | |
4618 | output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands); | |
4619 | output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands); | |
4620 | if (size) | |
4621 | fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size); | |
4622 | else if (! delay_slot) | |
4623 | fputs ("\t nop\n", asm_out_file); | |
4624 | } | |
4625 | else | |
4626 | { | |
4627 | if (size) | |
4628 | fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size); | |
e95b1e6a JJ |
4629 | /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize |
4630 | it into branch if possible. */ | |
4631 | output_asm_insn ("or\t%%o7, %%g0, %%g1", operands); | |
7d167afd | 4632 | output_asm_insn ("call\t%a0, 0", operands); |
e95b1e6a | 4633 | output_asm_insn (" or\t%%g1, %%g0, %%o7", operands); |
7d167afd JJ |
4634 | } |
4635 | return ""; | |
4636 | } | |
4637 | ||
4638 | output_asm_insn ("call\t%a0, 0", operands); | |
4639 | if (delay_slot) | |
4640 | { | |
4641 | rtx delay = NEXT_INSN (insn), pat; | |
4642 | ||
4643 | if (! delay) | |
4644 | abort (); | |
4645 | ||
4646 | pat = PATTERN (delay); | |
4647 | if (GET_CODE (pat) != SET) | |
4648 | abort (); | |
4649 | ||
4650 | operands[0] = SET_DEST (pat); | |
4651 | pat = SET_SRC (pat); | |
4652 | switch (GET_CODE (pat)) | |
4653 | { | |
4654 | case PLUS: | |
4655 | operands[1] = XEXP (pat, 0); | |
4656 | operands[2] = XEXP (pat, 1); | |
4657 | output_asm_insn (" restore %r1, %2, %Y0", operands); | |
4658 | break; | |
4659 | case LO_SUM: | |
4660 | operands[1] = XEXP (pat, 0); | |
4661 | operands[2] = XEXP (pat, 1); | |
4662 | output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); | |
4663 | break; | |
4664 | case ASHIFT: | |
4665 | operands[1] = XEXP (pat, 0); | |
4666 | output_asm_insn (" restore %r1, %r1, %Y0", operands); | |
4667 | break; | |
4668 | default: | |
4669 | operands[1] = pat; | |
4670 | output_asm_insn (" restore %%g0, %1, %Y0", operands); | |
4671 | break; | |
4672 | } | |
4673 | PATTERN (delay) = gen_blockage (); | |
4674 | INSN_CODE (delay) = -1; | |
4675 | } | |
4676 | else | |
4677 | fputs ("\t restore\n", asm_out_file); | |
4678 | return ""; | |
4679 | } | |
4fb4e4b8 DE |
4680 | \f |
4681 | /* Functions for handling argument passing. | |
4682 | ||
4683 | For v8 the first six args are normally in registers and the rest are | |
4684 | pushed. Any arg that starts within the first 6 words is at least | |
4685 | partially passed in a register unless its data type forbids. | |
4686 | ||
4687 | For v9, the argument registers are laid out as an array of 16 elements | |
4688 | and arguments are added sequentially. The first 6 int args and up to the | |
4689 | first 16 fp args (depending on size) are passed in regs. | |
4690 | ||
4691 | Slot Stack Integral Float Float in structure Double Long Double | |
4692 | ---- ----- -------- ----- ------------------ ------ ----------- | |
4693 | 15 [SP+248] %f31 %f30,%f31 %d30 | |
4694 | 14 [SP+240] %f29 %f28,%f29 %d28 %q28 | |
4695 | 13 [SP+232] %f27 %f26,%f27 %d26 | |
4696 | 12 [SP+224] %f25 %f24,%f25 %d24 %q24 | |
4697 | 11 [SP+216] %f23 %f22,%f23 %d22 | |
4698 | 10 [SP+208] %f21 %f20,%f21 %d20 %q20 | |
4699 | 9 [SP+200] %f19 %f18,%f19 %d18 | |
4700 | 8 [SP+192] %f17 %f16,%f17 %d16 %q16 | |
4701 | 7 [SP+184] %f15 %f14,%f15 %d14 | |
4702 | 6 [SP+176] %f13 %f12,%f13 %d12 %q12 | |
4703 | 5 [SP+168] %o5 %f11 %f10,%f11 %d10 | |
4704 | 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 | |
4705 | 3 [SP+152] %o3 %f7 %f6,%f7 %d6 | |
4706 | 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 | |
4707 | 1 [SP+136] %o1 %f3 %f2,%f3 %d2 | |
4708 | 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 | |
4709 | ||
4710 | Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. | |
4711 | ||
4712 | Integral arguments are always passed as 64 bit quantities appropriately | |
4713 | extended. | |
4714 | ||
4715 | Passing of floating point values is handled as follows. | |
4716 | If a prototype is in scope: | |
4717 | If the value is in a named argument (i.e. not a stdarg function or a | |
4718 | value not part of the `...') then the value is passed in the appropriate | |
4719 | fp reg. | |
4720 | If the value is part of the `...' and is passed in one of the first 6 | |
4721 | slots then the value is passed in the appropriate int reg. | |
4722 | If the value is part of the `...' and is not passed in one of the first 6 | |
4723 | slots then the value is passed in memory. | |
4724 | If a prototype is not in scope: | |
4725 | If the value is one of the first 6 arguments the value is passed in the | |
4726 | appropriate integer reg and the appropriate fp reg. | |
4727 | If the value is not one of the first 6 arguments the value is passed in | |
4728 | the appropriate fp reg and in memory. | |
4729 | */ | |
4730 | ||
4731 | /* Maximum number of int regs for args. */ | |
4732 | #define SPARC_INT_ARG_MAX 6 | |
4733 | /* Maximum number of fp regs for args. */ | |
4734 | #define SPARC_FP_ARG_MAX 16 | |
4735 | ||
4736 | #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
4737 | ||
4738 | /* Handle the INIT_CUMULATIVE_ARGS macro. | |
4739 | Initialize a variable CUM of type CUMULATIVE_ARGS | |
4740 | for a call to a function whose data type is FNTYPE. | |
4741 | For a library call, FNTYPE is 0. */ | |
3ea1fdd3 | 4742 | |
4fb4e4b8 | 4743 | void |
fc27d102 KG |
4744 | init_cumulative_args (struct sparc_args *cum, tree fntype, |
4745 | rtx libname ATTRIBUTE_UNUSED, | |
4746 | tree fndecl ATTRIBUTE_UNUSED) | |
4fb4e4b8 DE |
4747 | { |
4748 | cum->words = 0; | |
4749 | cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); | |
4750 | cum->libcall_p = fntype == 0; | |
4751 | } | |
61a55e8b | 4752 | |
4fb4e4b8 DE |
4753 | /* Compute the slot number to pass an argument in. |
4754 | Returns the slot number or -1 if passing on the stack. | |
4755 | ||
4756 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4757 | the preceding args and about the function being called. | |
4758 | MODE is the argument's machine mode. | |
4759 | TYPE is the data type of the argument (as a tree). | |
4760 | This is null for libcalls where that information may | |
4761 | not be available. | |
4762 | NAMED is nonzero if this argument is a named parameter | |
4763 | (otherwise it is an extra parameter matching an ellipsis). | |
4764 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. | |
4765 | *PREGNO records the register number to use if scalar type. | |
4766 | *PPADDING records the amount of padding needed in words. */ | |
4767 | ||
4768 | static int | |
fc27d102 KG |
4769 | function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode, |
4770 | tree type, int named, int incoming_p, | |
4771 | int *pregno, int *ppadding) | |
4fb4e4b8 DE |
4772 | { |
4773 | int regbase = (incoming_p | |
4774 | ? SPARC_INCOMING_INT_ARG_FIRST | |
4775 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
4776 | int slotno = cum->words; | |
4777 | int regno; | |
4778 | ||
4779 | *ppadding = 0; | |
4780 | ||
4781 | if (type != 0 && TREE_ADDRESSABLE (type)) | |
4782 | return -1; | |
4783 | if (TARGET_ARCH32 | |
4784 | && type != 0 && mode == BLKmode | |
4785 | && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) | |
4786 | return -1; | |
4787 | ||
4788 | switch (mode) | |
4789 | { | |
4790 | case VOIDmode : | |
4791 | /* MODE is VOIDmode when generating the actual call. | |
4792 | See emit_call_1. */ | |
4793 | return -1; | |
4794 | ||
4795 | case QImode : case CQImode : | |
4796 | case HImode : case CHImode : | |
4797 | case SImode : case CSImode : | |
4798 | case DImode : case CDImode : | |
380f6ad3 | 4799 | case TImode : case CTImode : |
4fb4e4b8 DE |
4800 | if (slotno >= SPARC_INT_ARG_MAX) |
4801 | return -1; | |
4802 | regno = regbase + slotno; | |
4803 | break; | |
4804 | ||
4805 | case SFmode : case SCmode : | |
4806 | case DFmode : case DCmode : | |
4807 | case TFmode : case TCmode : | |
4808 | if (TARGET_ARCH32) | |
4809 | { | |
4810 | if (slotno >= SPARC_INT_ARG_MAX) | |
4811 | return -1; | |
4812 | regno = regbase + slotno; | |
4813 | } | |
4814 | else | |
4815 | { | |
4816 | if ((mode == TFmode || mode == TCmode) | |
4817 | && (slotno & 1) != 0) | |
4818 | slotno++, *ppadding = 1; | |
4819 | if (TARGET_FPU && named) | |
4820 | { | |
4821 | if (slotno >= SPARC_FP_ARG_MAX) | |
82d6b402 | 4822 | return -1; |
4fb4e4b8 DE |
4823 | regno = SPARC_FP_ARG_FIRST + slotno * 2; |
4824 | if (mode == SFmode) | |
4825 | regno++; | |
4826 | } | |
4827 | else | |
4828 | { | |
4829 | if (slotno >= SPARC_INT_ARG_MAX) | |
4830 | return -1; | |
4831 | regno = regbase + slotno; | |
4832 | } | |
4833 | } | |
4834 | break; | |
4835 | ||
4836 | case BLKmode : | |
4837 | /* For sparc64, objects requiring 16 byte alignment get it. */ | |
4838 | if (TARGET_ARCH64) | |
4839 | { | |
4840 | if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0) | |
4841 | slotno++, *ppadding = 1; | |
4842 | } | |
4843 | ||
4844 | if (TARGET_ARCH32 | |
5e9defae | 4845 | || (type && TREE_CODE (type) == UNION_TYPE)) |
4fb4e4b8 DE |
4846 | { |
4847 | if (slotno >= SPARC_INT_ARG_MAX) | |
4848 | return -1; | |
4849 | regno = regbase + slotno; | |
4850 | } | |
4851 | else | |
4852 | { | |
4853 | tree field; | |
4854 | int intregs_p = 0, fpregs_p = 0; | |
4855 | /* The ABI obviously doesn't specify how packed | |
4856 | structures are passed. These are defined to be passed | |
4857 | in int regs if possible, otherwise memory. */ | |
4858 | int packed_p = 0; | |
4859 | ||
4860 | /* First see what kinds of registers we need. */ | |
4861 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4862 | { | |
4863 | if (TREE_CODE (field) == FIELD_DECL) | |
4864 | { | |
4865 | if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
4866 | && TARGET_FPU) | |
4867 | fpregs_p = 1; | |
4868 | else | |
4869 | intregs_p = 1; | |
4870 | if (DECL_PACKED (field)) | |
4871 | packed_p = 1; | |
4872 | } | |
4873 | } | |
4874 | if (packed_p || !named) | |
4875 | fpregs_p = 0, intregs_p = 1; | |
4876 | ||
4877 | /* If all arg slots are filled, then must pass on stack. */ | |
4878 | if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) | |
4879 | return -1; | |
4880 | /* If there are only int args and all int arg slots are filled, | |
4881 | then must pass on stack. */ | |
4882 | if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) | |
4883 | return -1; | |
4884 | /* Note that even if all int arg slots are filled, fp members may | |
4885 | still be passed in regs if such regs are available. | |
4886 | *PREGNO isn't set because there may be more than one, it's up | |
4887 | to the caller to compute them. */ | |
4888 | return slotno; | |
4889 | } | |
4890 | break; | |
4891 | ||
4892 | default : | |
4893 | abort (); | |
4894 | } | |
4895 | ||
4896 | *pregno = regno; | |
4897 | return slotno; | |
4898 | } | |
4899 | ||
82d6b402 RH |
4900 | /* Handle recursive register counting for structure field layout. */ |
4901 | ||
4902 | struct function_arg_record_value_parms | |
4903 | { | |
48028e21 EB |
4904 | rtx ret; /* return expression being built. */ |
4905 | int slotno; /* slot number of the argument. */ | |
4906 | int named; /* whether the argument is named. */ | |
4907 | int regbase; /* regno of the base register. */ | |
4908 | int stack; /* 1 if part of the argument is on the stack. */ | |
4909 | int intoffset; /* offset of the pending integer field. */ | |
4910 | unsigned int nregs; /* number of words passed in registers. */ | |
82d6b402 RH |
4911 | }; |
4912 | ||
2a01c939 | 4913 | static void function_arg_record_value_3 |
e80d5f80 | 4914 | (HOST_WIDE_INT, struct function_arg_record_value_parms *); |
2a01c939 | 4915 | static void function_arg_record_value_2 |
e80d5f80 | 4916 | (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *); |
b1474bb7 | 4917 | static void function_arg_record_value_1 |
e80d5f80 KG |
4918 | (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *); |
4919 | static rtx function_arg_record_value (tree, enum machine_mode, int, int, int); | |
2a01c939 | 4920 | |
0020b823 | 4921 | /* A subroutine of function_arg_record_value. Traverse the structure |
fae778eb | 4922 | recursively and determine how many registers will be required. */ |
0020b823 | 4923 | |
82d6b402 | 4924 | static void |
fc27d102 KG |
4925 | function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos, |
4926 | struct function_arg_record_value_parms *parms) | |
82d6b402 RH |
4927 | { |
4928 | tree field; | |
4929 | ||
4930 | /* The ABI obviously doesn't specify how packed structures are | |
4931 | passed. These are defined to be passed in int regs if possible, | |
4932 | otherwise memory. */ | |
4933 | int packed_p = 0; | |
4934 | ||
4935 | /* We need to compute how many registers are needed so we can | |
4936 | allocate the PARALLEL but before we can do that we need to know | |
4937 | whether there are any packed fields. If there are, int regs are | |
4938 | used regardless of whether there are fp values present. */ | |
4939 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4940 | { | |
4941 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
4942 | { | |
4943 | packed_p = 1; | |
4944 | break; | |
4945 | } | |
4946 | } | |
4947 | ||
4948 | /* Compute how many registers we need. */ | |
4949 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4950 | { | |
4951 | if (TREE_CODE (field) == FIELD_DECL) | |
4952 | { | |
75131237 RK |
4953 | HOST_WIDE_INT bitpos = startbitpos; |
4954 | ||
4955 | if (DECL_SIZE (field) != 0 | |
4956 | && host_integerp (bit_position (field), 1)) | |
4957 | bitpos += int_bit_position (field); | |
4958 | ||
82d6b402 RH |
4959 | /* ??? FIXME: else assume zero offset. */ |
4960 | ||
4961 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
75131237 | 4962 | function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms); |
105b2084 JJ |
4963 | else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE |
4964 | || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE | |
4965 | && (TREE_CODE (TREE_TYPE (TREE_TYPE (field))) | |
4966 | == REAL_TYPE))) | |
82d6b402 RH |
4967 | && TARGET_FPU |
4968 | && ! packed_p | |
4969 | && parms->named) | |
4970 | { | |
4971 | if (parms->intoffset != -1) | |
4972 | { | |
4973 | int intslots, this_slotno; | |
4974 | ||
4975 | intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1) | |
4976 | / BITS_PER_WORD; | |
4977 | this_slotno = parms->slotno + parms->intoffset | |
4978 | / BITS_PER_WORD; | |
4979 | ||
48028e21 EB |
4980 | if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) |
4981 | { | |
4982 | intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); | |
4983 | /* We need to pass this field on the stack. */ | |
4984 | parms->stack = 1; | |
4985 | } | |
4986 | ||
82d6b402 RH |
4987 | parms->nregs += intslots; |
4988 | parms->intoffset = -1; | |
4989 | } | |
4990 | ||
4991 | /* There's no need to check this_slotno < SPARC_FP_ARG MAX. | |
4992 | If it wasn't true we wouldn't be here. */ | |
4993 | parms->nregs += 1; | |
105b2084 JJ |
4994 | if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) |
4995 | parms->nregs += 1; | |
82d6b402 RH |
4996 | } |
4997 | else | |
4998 | { | |
4999 | if (parms->intoffset == -1) | |
5000 | parms->intoffset = bitpos; | |
5001 | } | |
5002 | } | |
5003 | } | |
5004 | } | |
5005 | ||
0020b823 RH |
5006 | /* A subroutine of function_arg_record_value. Assign the bits of the |
5007 | structure between parms->intoffset and bitpos to integer registers. */ | |
82d6b402 RH |
5008 | |
5009 | static void | |
fc27d102 KG |
5010 | function_arg_record_value_3 (HOST_WIDE_INT bitpos, |
5011 | struct function_arg_record_value_parms *parms) | |
82d6b402 RH |
5012 | { |
5013 | enum machine_mode mode; | |
75131237 | 5014 | unsigned int regno; |
0020b823 | 5015 | unsigned int startbit, endbit; |
75131237 | 5016 | int this_slotno, intslots, intoffset; |
82d6b402 RH |
5017 | rtx reg; |
5018 | ||
5019 | if (parms->intoffset == -1) | |
5020 | return; | |
75131237 | 5021 | |
82d6b402 RH |
5022 | intoffset = parms->intoffset; |
5023 | parms->intoffset = -1; | |
5024 | ||
0020b823 RH |
5025 | startbit = intoffset & -BITS_PER_WORD; |
5026 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
5027 | intslots = (endbit - startbit) / BITS_PER_WORD; | |
82d6b402 RH |
5028 | this_slotno = parms->slotno + intoffset / BITS_PER_WORD; |
5029 | ||
5030 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
5031 | if (intslots <= 0) | |
5032 | return; | |
5033 | ||
5034 | /* If this is the trailing part of a word, only load that much into | |
5035 | the register. Otherwise load the whole register. Note that in | |
5036 | the latter case we may pick up unwanted bits. It's not a problem | |
5037 | at the moment but may wish to revisit. */ | |
5038 | ||
5039 | if (intoffset % BITS_PER_WORD != 0) | |
75131237 RK |
5040 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, |
5041 | MODE_INT, 0); | |
82d6b402 RH |
5042 | else |
5043 | mode = word_mode; | |
5044 | ||
5045 | intoffset /= BITS_PER_UNIT; | |
5046 | do | |
5047 | { | |
5048 | regno = parms->regbase + this_slotno; | |
254110c2 | 5049 | reg = gen_rtx_REG (mode, regno); |
48028e21 | 5050 | XVECEXP (parms->ret, 0, parms->stack + parms->nregs) |
254110c2 | 5051 | = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); |
82d6b402 RH |
5052 | |
5053 | this_slotno += 1; | |
5054 | intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; | |
5055 | parms->nregs += 1; | |
5056 | intslots -= 1; | |
5057 | } | |
5058 | while (intslots > 0); | |
5059 | } | |
5060 | ||
0020b823 RH |
5061 | /* A subroutine of function_arg_record_value. Traverse the structure |
5062 | recursively and assign bits to floating point registers. Track which | |
5063 | bits in between need integer registers; invoke function_arg_record_value_3 | |
5064 | to make that happen. */ | |
5065 | ||
82d6b402 | 5066 | static void |
fc27d102 KG |
5067 | function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos, |
5068 | struct function_arg_record_value_parms *parms) | |
82d6b402 RH |
5069 | { |
5070 | tree field; | |
5071 | int packed_p = 0; | |
5072 | ||
5073 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
5074 | { | |
5075 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
5076 | { | |
5077 | packed_p = 1; | |
5078 | break; | |
5079 | } | |
5080 | } | |
5081 | ||
5082 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
5083 | { | |
5084 | if (TREE_CODE (field) == FIELD_DECL) | |
5085 | { | |
75131237 RK |
5086 | HOST_WIDE_INT bitpos = startbitpos; |
5087 | ||
5088 | if (DECL_SIZE (field) != 0 | |
5089 | && host_integerp (bit_position (field), 1)) | |
5090 | bitpos += int_bit_position (field); | |
5091 | ||
82d6b402 RH |
5092 | /* ??? FIXME: else assume zero offset. */ |
5093 | ||
5094 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
75131237 | 5095 | function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms); |
105b2084 JJ |
5096 | else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE |
5097 | || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE | |
5098 | && (TREE_CODE (TREE_TYPE (TREE_TYPE (field))) | |
5099 | == REAL_TYPE))) | |
82d6b402 RH |
5100 | && TARGET_FPU |
5101 | && ! packed_p | |
5102 | && parms->named) | |
5103 | { | |
5104 | int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; | |
105b2084 JJ |
5105 | int regno; |
5106 | enum machine_mode mode = DECL_MODE (field); | |
82d6b402 RH |
5107 | rtx reg; |
5108 | ||
5109 | function_arg_record_value_3 (bitpos, parms); | |
105b2084 JJ |
5110 | regno = SPARC_FP_ARG_FIRST + this_slotno * 2 |
5111 | + ((mode == SFmode || mode == SCmode) | |
5112 | && (bitpos & 32) != 0); | |
5113 | switch (mode) | |
5114 | { | |
5115 | case SCmode: mode = SFmode; break; | |
5116 | case DCmode: mode = DFmode; break; | |
5117 | case TCmode: mode = TFmode; break; | |
5118 | default: break; | |
5119 | } | |
5120 | reg = gen_rtx_REG (mode, regno); | |
48028e21 | 5121 | XVECEXP (parms->ret, 0, parms->stack + parms->nregs) |
254110c2 | 5122 | = gen_rtx_EXPR_LIST (VOIDmode, reg, |
82d6b402 RH |
5123 | GEN_INT (bitpos / BITS_PER_UNIT)); |
5124 | parms->nregs += 1; | |
105b2084 JJ |
5125 | if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) |
5126 | { | |
5127 | regno += GET_MODE_SIZE (mode) / 4; | |
5128 | reg = gen_rtx_REG (mode, regno); | |
48028e21 | 5129 | XVECEXP (parms->ret, 0, parms->stack + parms->nregs) |
105b2084 JJ |
5130 | = gen_rtx_EXPR_LIST (VOIDmode, reg, |
5131 | GEN_INT ((bitpos + GET_MODE_BITSIZE (mode)) | |
5132 | / BITS_PER_UNIT)); | |
5133 | parms->nregs += 1; | |
5134 | } | |
82d6b402 RH |
5135 | } |
5136 | else | |
5137 | { | |
5138 | if (parms->intoffset == -1) | |
5139 | parms->intoffset = bitpos; | |
5140 | } | |
5141 | } | |
5142 | } | |
5143 | } | |
5144 | ||
0020b823 | 5145 | /* Used by function_arg and function_value to implement the complex |
48028e21 EB |
5146 | conventions of the 64-bit ABI for passing and returning structures. |
5147 | Return an expression valid as a return value for the two macros | |
5148 | FUNCTION_ARG and FUNCTION_VALUE. | |
0020b823 | 5149 | |
48028e21 EB |
5150 | TYPE is the data type of the argument (as a tree). |
5151 | This is null for libcalls where that information may | |
5152 | not be available. | |
5153 | MODE is the argument's machine mode. | |
5154 | SLOTNO is the index number of the argument's slot in the parameter array. | |
5155 | NAMED is nonzero if this argument is a named parameter | |
5156 | (otherwise it is an extra parameter matching an ellipsis). | |
5157 | REGBASE is the regno of the base register for the parameter array. */ | |
5158 | ||
82d6b402 | 5159 | static rtx |
fc27d102 KG |
5160 | function_arg_record_value (tree type, enum machine_mode mode, |
5161 | int slotno, int named, int regbase) | |
82d6b402 RH |
5162 | { |
5163 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
5164 | struct function_arg_record_value_parms parms; | |
75131237 | 5165 | unsigned int nregs; |
82d6b402 RH |
5166 | |
5167 | parms.ret = NULL_RTX; | |
5168 | parms.slotno = slotno; | |
5169 | parms.named = named; | |
5170 | parms.regbase = regbase; | |
48028e21 | 5171 | parms.stack = 0; |
82d6b402 RH |
5172 | |
5173 | /* Compute how many registers we need. */ | |
5174 | parms.nregs = 0; | |
5175 | parms.intoffset = 0; | |
5176 | function_arg_record_value_1 (type, 0, &parms); | |
5177 | ||
5178 | if (parms.intoffset != -1) | |
5179 | { | |
0020b823 | 5180 | unsigned int startbit, endbit; |
82d6b402 RH |
5181 | int intslots, this_slotno; |
5182 | ||
0020b823 RH |
5183 | startbit = parms.intoffset & -BITS_PER_WORD; |
5184 | endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
5185 | intslots = (endbit - startbit) / BITS_PER_WORD; | |
82d6b402 RH |
5186 | this_slotno = slotno + parms.intoffset / BITS_PER_WORD; |
5187 | ||
48028e21 EB |
5188 | if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) |
5189 | { | |
5190 | intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); | |
5191 | /* We need to pass this field on the stack. */ | |
5192 | parms.stack = 1; | |
5193 | } | |
82d6b402 RH |
5194 | |
5195 | parms.nregs += intslots; | |
5196 | } | |
5197 | nregs = parms.nregs; | |
5198 | ||
5199 | /* Allocate the vector and handle some annoying special cases. */ | |
5200 | if (nregs == 0) | |
5201 | { | |
5202 | /* ??? Empty structure has no value? Duh? */ | |
5203 | if (typesize <= 0) | |
5204 | { | |
5205 | /* Though there's nothing really to store, return a word register | |
5206 | anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL | |
5207 | leads to breakage due to the fact that there are zero bytes to | |
5208 | load. */ | |
1eac9f59 | 5209 | return gen_rtx_REG (mode, regbase); |
82d6b402 RH |
5210 | } |
5211 | else | |
5212 | { | |
5213 | /* ??? C++ has structures with no fields, and yet a size. Give up | |
5214 | for now and pass everything back in integer registers. */ | |
5215 | nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
5216 | } | |
5217 | if (nregs + slotno > SPARC_INT_ARG_MAX) | |
5218 | nregs = SPARC_INT_ARG_MAX - slotno; | |
5219 | } | |
5220 | if (nregs == 0) | |
9208e4b2 | 5221 | abort (); |
82d6b402 | 5222 | |
48028e21 EB |
5223 | parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs)); |
5224 | ||
5225 | /* If at least one field must be passed on the stack, generate | |
5226 | (parallel [(expr_list (nil) ...) ...]) so that all fields will | |
5227 | also be passed on the stack. We can't do much better because the | |
5228 | semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case | |
5229 | of structures for which the fields passed exclusively in registers | |
5230 | are not at the beginning of the structure. */ | |
5231 | if (parms.stack) | |
5232 | XVECEXP (parms.ret, 0, 0) | |
5233 | = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
82d6b402 RH |
5234 | |
5235 | /* Fill in the entries. */ | |
5236 | parms.nregs = 0; | |
5237 | parms.intoffset = 0; | |
5238 | function_arg_record_value_2 (type, 0, &parms); | |
5239 | function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); | |
5240 | ||
5241 | if (parms.nregs != nregs) | |
5242 | abort (); | |
5243 | ||
5244 | return parms.ret; | |
5245 | } | |
5246 | ||
4fb4e4b8 DE |
5247 | /* Handle the FUNCTION_ARG macro. |
5248 | Determine where to put an argument to a function. | |
5249 | Value is zero to push the argument on the stack, | |
5250 | or a hard register in which to store the argument. | |
5251 | ||
5252 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
5253 | the preceding args and about the function being called. | |
5254 | MODE is the argument's machine mode. | |
5255 | TYPE is the data type of the argument (as a tree). | |
5256 | This is null for libcalls where that information may | |
5257 | not be available. | |
5258 | NAMED is nonzero if this argument is a named parameter | |
5259 | (otherwise it is an extra parameter matching an ellipsis). | |
5260 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ | |
61a55e8b DE |
5261 | |
5262 | rtx | |
fc27d102 KG |
5263 | function_arg (const struct sparc_args *cum, enum machine_mode mode, |
5264 | tree type, int named, int incoming_p) | |
61a55e8b | 5265 | { |
4fb4e4b8 DE |
5266 | int regbase = (incoming_p |
5267 | ? SPARC_INCOMING_INT_ARG_FIRST | |
5268 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
5269 | int slotno, regno, padding; | |
5270 | rtx reg; | |
5271 | ||
5272 | slotno = function_arg_slotno (cum, mode, type, named, incoming_p, | |
5273 | ®no, &padding); | |
5274 | ||
5275 | if (slotno == -1) | |
5276 | return 0; | |
5277 | ||
5278 | if (TARGET_ARCH32) | |
5279 | { | |
254110c2 | 5280 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
5281 | return reg; |
5282 | } | |
5283 | ||
5284 | /* v9 fp args in reg slots beyond the int reg slots get passed in regs | |
5285 | but also have the slot allocated for them. | |
5286 | If no prototype is in scope fp values in register slots get passed | |
5287 | in two places, either fp regs and int regs or fp regs and memory. */ | |
5288 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
5289 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5290 | && SPARC_FP_REG_P (regno)) | |
5291 | { | |
254110c2 | 5292 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
5293 | if (cum->prototype_p || cum->libcall_p) |
5294 | { | |
5295 | /* "* 2" because fp reg numbers are recorded in 4 byte | |
5296 | quantities. */ | |
82d6b402 | 5297 | #if 0 |
4fb4e4b8 DE |
5298 | /* ??? This will cause the value to be passed in the fp reg and |
5299 | in the stack. When a prototype exists we want to pass the | |
5300 | value in the reg but reserve space on the stack. That's an | |
956d6950 | 5301 | optimization, and is deferred [for a bit]. */ |
4fb4e4b8 | 5302 | if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) |
254110c2 | 5303 | return gen_rtx_PARALLEL (mode, |
4fb4e4b8 | 5304 | gen_rtvec (2, |
254110c2 | 5305 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 | 5306 | NULL_RTX, const0_rtx), |
254110c2 | 5307 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 DE |
5308 | reg, const0_rtx))); |
5309 | else | |
82d6b402 RH |
5310 | #else |
5311 | /* ??? It seems that passing back a register even when past | |
5312 | the area declared by REG_PARM_STACK_SPACE will allocate | |
5313 | space appropriately, and will not copy the data onto the | |
5314 | stack, exactly as we desire. | |
5315 | ||
5316 | This is due to locate_and_pad_parm being called in | |
5317 | expand_call whenever reg_parm_stack_space > 0, which | |
fae778eb | 5318 | while beneficial to our example here, would seem to be |
82d6b402 RH |
5319 | in error from what had been intended. Ho hum... -- r~ */ |
5320 | #endif | |
4fb4e4b8 DE |
5321 | return reg; |
5322 | } | |
5323 | else | |
5324 | { | |
82d6b402 RH |
5325 | rtx v0, v1; |
5326 | ||
4fb4e4b8 DE |
5327 | if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) |
5328 | { | |
82d6b402 RH |
5329 | int intreg; |
5330 | ||
5331 | /* On incoming, we don't need to know that the value | |
5332 | is passed in %f0 and %i0, and it confuses other parts | |
5333 | causing needless spillage even on the simplest cases. */ | |
5334 | if (incoming_p) | |
5335 | return reg; | |
5336 | ||
5337 | intreg = (SPARC_OUTGOING_INT_ARG_FIRST | |
5338 | + (regno - SPARC_FP_ARG_FIRST) / 2); | |
5339 | ||
5340 | v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
5341 | v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), | |
5342 | const0_rtx); | |
5343 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4fb4e4b8 DE |
5344 | } |
5345 | else | |
82d6b402 RH |
5346 | { |
5347 | v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
5348 | v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
5349 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
5350 | } | |
4fb4e4b8 DE |
5351 | } |
5352 | } | |
5353 | else if (type && TREE_CODE (type) == RECORD_TYPE) | |
5354 | { | |
5355 | /* Structures up to 16 bytes in size are passed in arg slots on the | |
5356 | stack and are promoted to registers where possible. */ | |
4fb4e4b8 DE |
5357 | |
5358 | if (int_size_in_bytes (type) > 16) | |
5359 | abort (); /* shouldn't get here */ | |
5360 | ||
1eac9f59 | 5361 | return function_arg_record_value (type, mode, slotno, named, regbase); |
4fb4e4b8 DE |
5362 | } |
5363 | else if (type && TREE_CODE (type) == UNION_TYPE) | |
5364 | { | |
5365 | enum machine_mode mode; | |
5366 | int bytes = int_size_in_bytes (type); | |
5367 | ||
5368 | if (bytes > 16) | |
5369 | abort (); | |
5370 | ||
5371 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
254110c2 | 5372 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 | 5373 | } |
a7acd911 | 5374 | else |
4fb4e4b8 DE |
5375 | { |
5376 | /* Scalar or complex int. */ | |
254110c2 | 5377 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
5378 | } |
5379 | ||
5380 | return reg; | |
5381 | } | |
a7acd911 | 5382 | |
4fb4e4b8 DE |
5383 | /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro. |
5384 | For an arg passed partly in registers and partly in memory, | |
5385 | this is the number of registers used. | |
5386 | For args passed entirely in registers or entirely in memory, zero. | |
61a55e8b | 5387 | |
4fb4e4b8 DE |
5388 | Any arg that starts in the first 6 regs but won't entirely fit in them |
5389 | needs partial registers on v8. On v9, structures with integer | |
5390 | values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp | |
5391 | values that begin in the last fp reg [where "last fp reg" varies with the | |
5392 | mode] will be split between that reg and memory. */ | |
61a55e8b | 5393 | |
4fb4e4b8 | 5394 | int |
fc27d102 KG |
5395 | function_arg_partial_nregs (const struct sparc_args *cum, |
5396 | enum machine_mode mode, tree type, int named) | |
4fb4e4b8 DE |
5397 | { |
5398 | int slotno, regno, padding; | |
61a55e8b | 5399 | |
4fb4e4b8 DE |
5400 | /* We pass 0 for incoming_p here, it doesn't matter. */ |
5401 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
5402 | ||
5403 | if (slotno == -1) | |
5404 | return 0; | |
5405 | ||
5406 | if (TARGET_ARCH32) | |
bf62bbf1 | 5407 | { |
4fb4e4b8 DE |
5408 | if ((slotno + (mode == BLKmode |
5409 | ? ROUND_ADVANCE (int_size_in_bytes (type)) | |
5410 | : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) | |
5411 | > NPARM_REGS (SImode)) | |
5412 | return NPARM_REGS (SImode) - slotno; | |
5413 | return 0; | |
5414 | } | |
5415 | else | |
5416 | { | |
5417 | if (type && AGGREGATE_TYPE_P (type)) | |
5418 | { | |
5419 | int size = int_size_in_bytes (type); | |
5420 | int align = TYPE_ALIGN (type); | |
bf62bbf1 | 5421 | |
4fb4e4b8 DE |
5422 | if (align == 16) |
5423 | slotno += slotno & 1; | |
5424 | if (size > 8 && size <= 16 | |
5425 | && slotno == SPARC_INT_ARG_MAX - 1) | |
5426 | return 1; | |
5427 | } | |
5428 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT | |
5429 | || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
c3427c7d | 5430 | && ! (TARGET_FPU && named))) |
4fb4e4b8 DE |
5431 | { |
5432 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
5433 | { | |
5434 | slotno += slotno & 1; | |
5435 | if (slotno == SPARC_INT_ARG_MAX - 2) | |
5436 | return 1; | |
5437 | } | |
5438 | else | |
5439 | { | |
5440 | if (slotno == SPARC_INT_ARG_MAX - 1) | |
5441 | return 1; | |
5442 | } | |
5443 | } | |
5444 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5445 | { | |
5446 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
5447 | slotno += slotno & 1; | |
5448 | if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) | |
5449 | > SPARC_FP_ARG_MAX) | |
5450 | return 1; | |
5451 | } | |
5452 | return 0; | |
bf62bbf1 | 5453 | } |
4fb4e4b8 | 5454 | } |
61a55e8b | 5455 | |
4fb4e4b8 DE |
5456 | /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro. |
5457 | !v9: The SPARC ABI stipulates passing struct arguments (of any size) and | |
5458 | quad-precision floats by invisible reference. | |
82d6b402 | 5459 | v9: Aggregates greater than 16 bytes are passed by reference. |
4fb4e4b8 DE |
5460 | For Pascal, also pass arrays by reference. */ |
5461 | ||
5462 | int | |
fc27d102 KG |
5463 | function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED, |
5464 | enum machine_mode mode, tree type, | |
5465 | int named ATTRIBUTE_UNUSED) | |
4fb4e4b8 DE |
5466 | { |
5467 | if (TARGET_ARCH32) | |
eadceb59 | 5468 | { |
5e9defae | 5469 | return ((type && AGGREGATE_TYPE_P (type)) |
4fb4e4b8 DE |
5470 | || mode == TFmode || mode == TCmode); |
5471 | } | |
5472 | else | |
5473 | { | |
5474 | return ((type && TREE_CODE (type) == ARRAY_TYPE) | |
80ffc95e | 5475 | /* Consider complex values as aggregates, so care for TCmode. */ |
82d6b402 | 5476 | || GET_MODE_SIZE (mode) > 16 |
f36dea3c RH |
5477 | || (type |
5478 | && AGGREGATE_TYPE_P (type) | |
5479 | && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)); | |
4fb4e4b8 DE |
5480 | } |
5481 | } | |
5482 | ||
5483 | /* Handle the FUNCTION_ARG_ADVANCE macro. | |
5484 | Update the data in CUM to advance over an argument | |
5485 | of mode MODE and data type TYPE. | |
5486 | TYPE is null for libcalls where that information may not be available. */ | |
5487 | ||
5488 | void | |
fc27d102 KG |
5489 | function_arg_advance (struct sparc_args *cum, enum machine_mode mode, |
5490 | tree type, int named) | |
4fb4e4b8 DE |
5491 | { |
5492 | int slotno, regno, padding; | |
5493 | ||
5494 | /* We pass 0 for incoming_p here, it doesn't matter. */ | |
5495 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
5496 | ||
5497 | /* If register required leading padding, add it. */ | |
5498 | if (slotno != -1) | |
5499 | cum->words += padding; | |
eadceb59 | 5500 | |
4fb4e4b8 DE |
5501 | if (TARGET_ARCH32) |
5502 | { | |
5503 | cum->words += (mode != BLKmode | |
5504 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
5505 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
5506 | } | |
5507 | else | |
5508 | { | |
5509 | if (type && AGGREGATE_TYPE_P (type)) | |
5510 | { | |
5511 | int size = int_size_in_bytes (type); | |
5512 | ||
5513 | if (size <= 8) | |
5514 | ++cum->words; | |
5515 | else if (size <= 16) | |
5516 | cum->words += 2; | |
5517 | else /* passed by reference */ | |
5518 | ++cum->words; | |
5519 | } | |
5520 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) | |
5521 | { | |
5522 | cum->words += 2; | |
5523 | } | |
5524 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5525 | { | |
5526 | cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD; | |
5527 | } | |
5528 | else | |
5529 | { | |
5530 | cum->words += (mode != BLKmode | |
5531 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
5532 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
5533 | } | |
eadceb59 | 5534 | } |
4fb4e4b8 | 5535 | } |
eadceb59 | 5536 | |
4fb4e4b8 DE |
5537 | /* Handle the FUNCTION_ARG_PADDING macro. |
5538 | For the 64 bit ABI structs are always stored left shifted in their | |
5539 | argument slot. */ | |
5540 | ||
5541 | enum direction | |
fc27d102 | 5542 | function_arg_padding (enum machine_mode mode, tree type) |
4fb4e4b8 | 5543 | { |
c85f7c16 JL |
5544 | if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) |
5545 | return upward; | |
61a55e8b | 5546 | |
d3704c46 KH |
5547 | /* Fall back to the default. */ |
5548 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
61a55e8b | 5549 | } |
82d6b402 RH |
5550 | |
5551 | /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. | |
5552 | For v9, function return values are subject to the same rules as arguments, | |
5553 | except that up to 32-bytes may be returned in registers. */ | |
5554 | ||
5555 | rtx | |
fc27d102 | 5556 | function_value (tree type, enum machine_mode mode, int incoming_p) |
82d6b402 RH |
5557 | { |
5558 | int regno; | |
5559 | int regbase = (incoming_p | |
5560 | ? SPARC_OUTGOING_INT_ARG_FIRST | |
5561 | : SPARC_INCOMING_INT_ARG_FIRST); | |
5562 | ||
5563 | if (TARGET_ARCH64 && type) | |
5564 | { | |
5565 | if (TREE_CODE (type) == RECORD_TYPE) | |
5566 | { | |
5567 | /* Structures up to 32 bytes in size are passed in registers, | |
5568 | promoted to fp registers where possible. */ | |
5569 | ||
5570 | if (int_size_in_bytes (type) > 32) | |
5571 | abort (); /* shouldn't get here */ | |
5572 | ||
1eac9f59 | 5573 | return function_arg_record_value (type, mode, 0, 1, regbase); |
82d6b402 | 5574 | } |
8a7199ad | 5575 | else if (AGGREGATE_TYPE_P (type)) |
82d6b402 | 5576 | { |
8a7199ad RK |
5577 | /* All other aggregate types are passed in an integer register |
5578 | in a mode corresponding to the size of the type. */ | |
5579 | HOST_WIDE_INT bytes = int_size_in_bytes (type); | |
82d6b402 RH |
5580 | |
5581 | if (bytes > 32) | |
5582 | abort (); | |
5583 | ||
5584 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
5585 | } | |
5586 | } | |
3c6088d2 JJ |
5587 | |
5588 | if (TARGET_ARCH64 | |
5589 | && GET_MODE_CLASS (mode) == MODE_INT | |
5590 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
8a7199ad | 5591 | && type && ! AGGREGATE_TYPE_P (type)) |
3c6088d2 | 5592 | mode = DImode; |
82d6b402 RH |
5593 | |
5594 | if (incoming_p) | |
5595 | regno = BASE_RETURN_VALUE_REG (mode); | |
5596 | else | |
5597 | regno = BASE_OUTGOING_VALUE_REG (mode); | |
5598 | ||
254110c2 | 5599 | return gen_rtx_REG (mode, regno); |
82d6b402 RH |
5600 | } |
5601 | ||
648d2ffc RH |
5602 | /* Do what is necessary for `va_start'. We look at the current function |
5603 | to determine if stdarg or varargs is used and return the address of | |
5604 | the first unnamed parameter. */ | |
3ea1fdd3 JW |
5605 | |
5606 | rtx | |
fc27d102 | 5607 | sparc_builtin_saveregs (void) |
3ea1fdd3 | 5608 | { |
4fb4e4b8 | 5609 | int first_reg = current_function_args_info.words; |
3ea1fdd3 JW |
5610 | rtx address; |
5611 | int regno; | |
5612 | ||
4fb4e4b8 | 5613 | for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++) |
254110c2 | 5614 | emit_move_insn (gen_rtx_MEM (word_mode, |
8ac61af7 RK |
5615 | gen_rtx_PLUS (Pmode, |
5616 | frame_pointer_rtx, | |
563c12b0 | 5617 | GEN_INT (FIRST_PARM_OFFSET (0) |
8ac61af7 RK |
5618 | + (UNITS_PER_WORD |
5619 | * regno)))), | |
254110c2 | 5620 | gen_rtx_REG (word_mode, |
8ac61af7 | 5621 | BASE_INCOMING_ARG_REG (word_mode) + regno)); |
3ea1fdd3 | 5622 | |
254110c2 | 5623 | address = gen_rtx_PLUS (Pmode, |
8ac61af7 | 5624 | frame_pointer_rtx, |
563c12b0 | 5625 | GEN_INT (FIRST_PARM_OFFSET (0) |
8ac61af7 | 5626 | + UNITS_PER_WORD * first_reg)); |
3ea1fdd3 JW |
5627 | |
5628 | return address; | |
5629 | } | |
a8b2c8a1 RH |
5630 | |
5631 | /* Implement `va_start' for varargs and stdarg. */ | |
5632 | ||
5633 | void | |
fc27d102 | 5634 | sparc_va_start (tree valist, rtx nextarg) |
a8b2c8a1 RH |
5635 | { |
5636 | nextarg = expand_builtin_saveregs (); | |
e5faf155 | 5637 | std_expand_builtin_va_start (valist, nextarg); |
a8b2c8a1 RH |
5638 | } |
5639 | ||
5640 | /* Implement `va_arg'. */ | |
5641 | ||
5642 | rtx | |
fc27d102 | 5643 | sparc_va_arg (tree valist, tree type) |
a8b2c8a1 RH |
5644 | { |
5645 | HOST_WIDE_INT size, rsize, align; | |
da09e317 | 5646 | tree addr, incr; |
a8b2c8a1 RH |
5647 | rtx addr_rtx; |
5648 | int indirect = 0; | |
5649 | ||
5650 | /* Round up sizeof(type) to a word. */ | |
5651 | size = int_size_in_bytes (type); | |
5652 | rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; | |
5653 | align = 0; | |
5654 | ||
5655 | if (TARGET_ARCH64) | |
5656 | { | |
fbd039b2 | 5657 | if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) |
a8b2c8a1 RH |
5658 | align = 2 * UNITS_PER_WORD; |
5659 | ||
f34e52f7 | 5660 | if (AGGREGATE_TYPE_P (type)) |
a8b2c8a1 | 5661 | { |
f36dea3c | 5662 | if ((unsigned HOST_WIDE_INT) size > 16) |
f34e52f7 JJ |
5663 | { |
5664 | indirect = 1; | |
5665 | size = rsize = UNITS_PER_WORD; | |
97587cfa | 5666 | align = 0; |
f34e52f7 | 5667 | } |
014c0998 JJ |
5668 | /* SPARC v9 ABI states that structures up to 8 bytes in size are |
5669 | given one 8 byte slot. */ | |
5670 | else if (size == 0) | |
5671 | size = rsize = UNITS_PER_WORD; | |
f34e52f7 JJ |
5672 | else |
5673 | size = rsize; | |
a8b2c8a1 RH |
5674 | } |
5675 | } | |
5676 | else | |
5677 | { | |
5678 | if (AGGREGATE_TYPE_P (type) | |
5679 | || TYPE_MODE (type) == TFmode | |
5680 | || TYPE_MODE (type) == TCmode) | |
5681 | { | |
5682 | indirect = 1; | |
5683 | size = rsize = UNITS_PER_WORD; | |
5684 | } | |
a8b2c8a1 RH |
5685 | } |
5686 | ||
5687 | incr = valist; | |
5688 | if (align) | |
5689 | { | |
5690 | incr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
5691 | build_int_2 (align - 1, 0))); | |
5692 | incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr, | |
5693 | build_int_2 (-align, -1))); | |
5694 | } | |
5695 | ||
5696 | addr = incr = save_expr (incr); | |
5697 | if (BYTES_BIG_ENDIAN && size < rsize) | |
5698 | { | |
5699 | addr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
5700 | build_int_2 (rsize - size, 0))); | |
5701 | } | |
5702 | incr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
5703 | build_int_2 (rsize, 0))); | |
5704 | ||
5705 | incr = build (MODIFY_EXPR, ptr_type_node, valist, incr); | |
5706 | TREE_SIDE_EFFECTS (incr) = 1; | |
5707 | expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5708 | ||
5709 | addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); | |
5710 | ||
9a0662b4 GK |
5711 | /* If the address isn't aligned properly for the type, |
5712 | we may need to copy to a temporary. | |
5713 | FIXME: This is inefficient. Usually we can do this | |
5714 | in registers. */ | |
5715 | if (align == 0 | |
5716 | && TYPE_ALIGN (type) > BITS_PER_WORD | |
5717 | && !indirect) | |
5718 | { | |
5719 | /* FIXME: We really need to specify that the temporary is live | |
5720 | for the whole function because expand_builtin_va_arg wants | |
5721 | the alias set to be get_varargs_alias_set (), but in this | |
5722 | case the alias set is that for TYPE and if the memory gets | |
5723 | reused it will be reused with alias set TYPE. */ | |
5724 | rtx tmp = assign_temp (type, 0, 1, 0); | |
5725 | rtx dest_addr; | |
5726 | ||
5727 | addr_rtx = force_reg (Pmode, addr_rtx); | |
5728 | addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx); | |
ba4828e0 | 5729 | set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); |
8ac61af7 | 5730 | set_mem_align (addr_rtx, BITS_PER_WORD); |
9a0662b4 GK |
5731 | tmp = shallow_copy_rtx (tmp); |
5732 | PUT_MODE (tmp, BLKmode); | |
ba4828e0 | 5733 | set_mem_alias_set (tmp, 0); |
9a0662b4 | 5734 | |
44bb111a RH |
5735 | dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize), |
5736 | BLOCK_OP_NORMAL); | |
9a0662b4 GK |
5737 | if (dest_addr != NULL_RTX) |
5738 | addr_rtx = dest_addr; | |
5739 | else | |
5740 | addr_rtx = XCEXP (tmp, 0, MEM); | |
5741 | } | |
5742 | ||
a8b2c8a1 RH |
5743 | if (indirect) |
5744 | { | |
5745 | addr_rtx = force_reg (Pmode, addr_rtx); | |
5746 | addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 5747 | set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); |
a8b2c8a1 RH |
5748 | } |
5749 | ||
5750 | return addr_rtx; | |
5751 | } | |
ab835497 RK |
5752 | \f |
5753 | /* Return the string to output a conditional branch to LABEL, which is | |
c4ce6853 DE |
5754 | the operand number of the label. OP is the conditional expression. |
5755 | XEXP (OP, 0) is assumed to be a condition code register (integer or | |
5756 | floating point) and its mode specifies what kind of comparison we made. | |
61a55e8b | 5757 | |
5e7a8ee0 | 5758 | REVERSED is nonzero if we should reverse the sense of the comparison. |
ab835497 | 5759 | |
5e7a8ee0 | 5760 | ANNUL is nonzero if we should generate an annulling branch. |
ab835497 | 5761 | |
5e7a8ee0 | 5762 | NOOP is nonzero if we have to follow this branch by a noop. |
c6b0465b JC |
5763 | |
5764 | INSN, if set, is the insn. */ | |
ab835497 RK |
5765 | |
5766 | char * | |
fc27d102 KG |
5767 | output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, |
5768 | int noop, rtx insn) | |
ab835497 | 5769 | { |
0b82d204 | 5770 | static char string[50]; |
ab835497 | 5771 | enum rtx_code code = GET_CODE (op); |
c4ce6853 DE |
5772 | rtx cc_reg = XEXP (op, 0); |
5773 | enum machine_mode mode = GET_MODE (cc_reg); | |
0b82d204 JJ |
5774 | const char *labelno, *branch; |
5775 | int spaces = 8, far; | |
5776 | char *p; | |
5777 | ||
5778 | /* v9 branches are limited to +-1MB. If it is too far away, | |
5779 | change | |
5780 | ||
5781 | bne,pt %xcc, .LC30 | |
5782 | ||
5783 | to | |
5784 | ||
5785 | be,pn %xcc, .+12 | |
5786 | nop | |
5787 | ba .LC30 | |
5788 | ||
5789 | and | |
5790 | ||
5791 | fbne,a,pn %fcc2, .LC29 | |
61a55e8b | 5792 | |
0b82d204 JJ |
5793 | to |
5794 | ||
5795 | fbe,pt %fcc2, .+16 | |
5796 | nop | |
5797 | ba .LC29 */ | |
5798 | ||
5799 | far = get_attr_length (insn) >= 3; | |
5800 | if (reversed ^ far) | |
ab835497 | 5801 | { |
e267e177 RH |
5802 | /* Reversal of FP compares takes care -- an ordered compare |
5803 | becomes an unordered compare and vice versa. */ | |
4d449554 | 5804 | if (mode == CCFPmode || mode == CCFPEmode) |
7913f3d0 | 5805 | code = reverse_condition_maybe_unordered (code); |
ab835497 | 5806 | else |
e267e177 | 5807 | code = reverse_condition (code); |
ab835497 RK |
5808 | } |
5809 | ||
e267e177 RH |
5810 | /* Start by writing the branch condition. */ |
5811 | if (mode == CCFPmode || mode == CCFPEmode) | |
5850dc00 RH |
5812 | { |
5813 | switch (code) | |
5814 | { | |
5815 | case NE: | |
5816 | branch = "fbne"; | |
5817 | break; | |
5818 | case EQ: | |
5819 | branch = "fbe"; | |
5820 | break; | |
5821 | case GE: | |
5822 | branch = "fbge"; | |
5823 | break; | |
5824 | case GT: | |
5825 | branch = "fbg"; | |
5826 | break; | |
5827 | case LE: | |
5828 | branch = "fble"; | |
5829 | break; | |
5830 | case LT: | |
5831 | branch = "fbl"; | |
5832 | break; | |
5833 | case UNORDERED: | |
5834 | branch = "fbu"; | |
5835 | break; | |
5836 | case ORDERED: | |
5837 | branch = "fbo"; | |
5838 | break; | |
5839 | case UNGT: | |
5840 | branch = "fbug"; | |
5841 | break; | |
5842 | case UNLT: | |
5843 | branch = "fbul"; | |
5844 | break; | |
5845 | case UNEQ: | |
5846 | branch = "fbue"; | |
5847 | break; | |
5848 | case UNGE: | |
5849 | branch = "fbuge"; | |
5850 | break; | |
5851 | case UNLE: | |
5852 | branch = "fbule"; | |
5853 | break; | |
5854 | case LTGT: | |
5855 | branch = "fblg"; | |
5856 | break; | |
5857 | ||
5858 | default: | |
5859 | abort (); | |
5860 | } | |
5861 | ||
5862 | /* ??? !v9: FP branches cannot be preceded by another floating point | |
5863 | insn. Because there is currently no concept of pre-delay slots, | |
5864 | we can fix this only by always emitting a nop before a floating | |
5865 | point branch. */ | |
5866 | ||
5867 | string[0] = '\0'; | |
5868 | if (! TARGET_V9) | |
5869 | strcpy (string, "nop\n\t"); | |
5870 | strcat (string, branch); | |
5871 | } | |
e267e177 | 5872 | else |
5850dc00 RH |
5873 | { |
5874 | switch (code) | |
5875 | { | |
5876 | case NE: | |
5877 | branch = "bne"; | |
5878 | break; | |
5879 | case EQ: | |
5880 | branch = "be"; | |
5881 | break; | |
5882 | case GE: | |
0b82d204 | 5883 | if (mode == CC_NOOVmode || mode == CCX_NOOVmode) |
5850dc00 RH |
5884 | branch = "bpos"; |
5885 | else | |
5886 | branch = "bge"; | |
5887 | break; | |
5888 | case GT: | |
5889 | branch = "bg"; | |
5890 | break; | |
5891 | case LE: | |
5892 | branch = "ble"; | |
5893 | break; | |
5894 | case LT: | |
0b82d204 | 5895 | if (mode == CC_NOOVmode || mode == CCX_NOOVmode) |
5850dc00 RH |
5896 | branch = "bneg"; |
5897 | else | |
5898 | branch = "bl"; | |
5899 | break; | |
5900 | case GEU: | |
5901 | branch = "bgeu"; | |
5902 | break; | |
5903 | case GTU: | |
5904 | branch = "bgu"; | |
5905 | break; | |
5906 | case LEU: | |
5907 | branch = "bleu"; | |
5908 | break; | |
5909 | case LTU: | |
5910 | branch = "blu"; | |
5911 | break; | |
5912 | ||
5913 | default: | |
5914 | abort (); | |
5915 | } | |
5916 | strcpy (string, branch); | |
5917 | } | |
e267e177 | 5918 | spaces -= strlen (branch); |
0b82d204 | 5919 | p = strchr (string, '\0'); |
e267e177 | 5920 | |
ab835497 | 5921 | /* Now add the annulling, the label, and a possible noop. */ |
0b82d204 | 5922 | if (annul && ! far) |
e0d80184 | 5923 | { |
0b82d204 JJ |
5924 | strcpy (p, ",a"); |
5925 | p += 2; | |
e0d80184 DM |
5926 | spaces -= 2; |
5927 | } | |
ab835497 | 5928 | |
61a55e8b | 5929 | if (! TARGET_V9) |
0b82d204 | 5930 | labelno = ""; |
61a55e8b DE |
5931 | else |
5932 | { | |
c6b0465b | 5933 | rtx note; |
0b82d204 | 5934 | int v8 = 0; |
c6b0465b | 5935 | |
0b82d204 | 5936 | if (! far && insn && INSN_ADDRESSES_SET_P ()) |
e0d80184 | 5937 | { |
0b82d204 JJ |
5938 | int delta = (INSN_ADDRESSES (INSN_UID (dest)) |
5939 | - INSN_ADDRESSES (INSN_UID (insn))); | |
5940 | /* Leave some instructions for "slop". */ | |
5941 | if (delta < -260000 || delta >= 260000) | |
5942 | v8 = 1; | |
e0d80184 | 5943 | } |
c6b0465b | 5944 | |
61a55e8b DE |
5945 | if (mode == CCFPmode || mode == CCFPEmode) |
5946 | { | |
0b82d204 | 5947 | static char v9_fcc_labelno[] = "%%fccX, "; |
61a55e8b | 5948 | /* Set the char indicating the number of the fcc reg to use. */ |
0b82d204 JJ |
5949 | v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; |
5950 | labelno = v9_fcc_labelno; | |
5951 | if (v8) | |
5952 | { | |
5953 | if (REGNO (cc_reg) == SPARC_FCC_REG) | |
5954 | labelno = ""; | |
5955 | else | |
5956 | abort (); | |
5957 | } | |
61a55e8b DE |
5958 | } |
5959 | else if (mode == CCXmode || mode == CCX_NOOVmode) | |
0b82d204 JJ |
5960 | { |
5961 | labelno = "%%xcc, "; | |
5962 | if (v8) | |
5963 | abort (); | |
5964 | } | |
61a55e8b | 5965 | else |
0b82d204 JJ |
5966 | { |
5967 | labelno = "%%icc, "; | |
5968 | if (v8) | |
5969 | labelno = ""; | |
5970 | } | |
5971 | ||
4f31cce8 | 5972 | if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) |
0b82d204 JJ |
5973 | { |
5974 | strcpy (p, | |
4f31cce8 | 5975 | ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) |
0b82d204 JJ |
5976 | ? ",pt" : ",pn"); |
5977 | p += 3; | |
5978 | spaces -= 3; | |
5979 | } | |
61a55e8b | 5980 | } |
e0d80184 | 5981 | if (spaces > 0) |
0b82d204 | 5982 | *p++ = '\t'; |
e0d80184 | 5983 | else |
0b82d204 JJ |
5984 | *p++ = ' '; |
5985 | strcpy (p, labelno); | |
5986 | p = strchr (p, '\0'); | |
5987 | if (far) | |
5988 | { | |
5989 | strcpy (p, ".+12\n\tnop\n\tb\t"); | |
5990 | if (annul || noop) | |
5991 | p[3] = '6'; | |
5992 | p += 13; | |
5993 | } | |
5994 | *p++ = '%'; | |
5995 | *p++ = 'l'; | |
5996 | /* Set the char indicating the number of the operand containing the | |
5997 | label_ref. */ | |
5998 | *p++ = label + '0'; | |
5999 | *p = '\0'; | |
61a55e8b | 6000 | if (noop) |
0b82d204 | 6001 | strcpy (p, "\n\tnop"); |
61a55e8b DE |
6002 | |
6003 | return string; | |
6004 | } | |
6005 | ||
47ac041c JJ |
6006 | /* Emit a library call comparison between floating point X and Y. |
6007 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). | |
6008 | TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode | |
6009 | values as arguments instead of the TFmode registers themselves, | |
6010 | that's why we cannot call emit_float_lib_cmp. */ | |
6011 | void | |
fc27d102 | 6012 | sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison) |
47ac041c | 6013 | { |
e77d72cb | 6014 | const char *qpfunc; |
5c5c34a4 JJ |
6015 | rtx slot0, slot1, result, tem, tem2; |
6016 | enum machine_mode mode; | |
47ac041c JJ |
6017 | |
6018 | switch (comparison) | |
6019 | { | |
6020 | case EQ: | |
5c5c34a4 | 6021 | qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq"; |
47ac041c JJ |
6022 | break; |
6023 | ||
6024 | case NE: | |
5c5c34a4 | 6025 | qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne"; |
47ac041c JJ |
6026 | break; |
6027 | ||
6028 | case GT: | |
5c5c34a4 | 6029 | qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt"; |
47ac041c JJ |
6030 | break; |
6031 | ||
6032 | case GE: | |
5c5c34a4 | 6033 | qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge"; |
47ac041c JJ |
6034 | break; |
6035 | ||
6036 | case LT: | |
5c5c34a4 | 6037 | qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt"; |
47ac041c JJ |
6038 | break; |
6039 | ||
6040 | case LE: | |
5c5c34a4 JJ |
6041 | qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle"; |
6042 | break; | |
6043 | ||
6044 | case ORDERED: | |
6045 | case UNORDERED: | |
6046 | case UNGT: | |
6047 | case UNLT: | |
6048 | case UNEQ: | |
6049 | case UNGE: | |
6050 | case UNLE: | |
6051 | case LTGT: | |
6052 | qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp"; | |
47ac041c JJ |
6053 | break; |
6054 | ||
6055 | default: | |
6056 | abort(); | |
6057 | break; | |
6058 | } | |
6059 | ||
5c5c34a4 | 6060 | if (TARGET_ARCH64) |
47ac041c | 6061 | { |
5c5c34a4 JJ |
6062 | if (GET_CODE (x) != MEM) |
6063 | { | |
6064 | slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); | |
6065 | emit_insn (gen_rtx_SET (VOIDmode, slot0, x)); | |
6066 | } | |
6067 | else | |
6068 | slot0 = x; | |
6069 | ||
6070 | if (GET_CODE (y) != MEM) | |
6071 | { | |
6072 | slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); | |
6073 | emit_insn (gen_rtx_SET (VOIDmode, slot1, y)); | |
6074 | } | |
6075 | else | |
6076 | slot1 = y; | |
47ac041c | 6077 | |
eb29ddb6 | 6078 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, |
5c5c34a4 JJ |
6079 | DImode, 2, |
6080 | XEXP (slot0, 0), Pmode, | |
6081 | XEXP (slot1, 0), Pmode); | |
6082 | ||
6083 | mode = DImode; | |
6084 | } | |
6085 | else | |
47ac041c | 6086 | { |
eb29ddb6 | 6087 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, |
5c5c34a4 JJ |
6088 | SImode, 2, |
6089 | x, TFmode, y, TFmode); | |
6090 | ||
6091 | mode = SImode; | |
47ac041c JJ |
6092 | } |
6093 | ||
47ac041c JJ |
6094 | |
6095 | /* Immediately move the result of the libcall into a pseudo | |
6096 | register so reload doesn't clobber the value if it needs | |
6097 | the return register for a spill reg. */ | |
5c5c34a4 JJ |
6098 | result = gen_reg_rtx (mode); |
6099 | emit_move_insn (result, hard_libcall_value (mode)); | |
47ac041c | 6100 | |
5c5c34a4 JJ |
6101 | switch (comparison) |
6102 | { | |
6103 | default: | |
3b2d1507 | 6104 | emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
6105 | break; |
6106 | case ORDERED: | |
6107 | case UNORDERED: | |
3b2d1507 AT |
6108 | emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE, |
6109 | NULL_RTX, mode, 0); | |
5c5c34a4 JJ |
6110 | break; |
6111 | case UNGT: | |
6112 | case UNGE: | |
6113 | emit_cmp_insn (result, const1_rtx, | |
3b2d1507 | 6114 | comparison == UNGT ? GT : NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
6115 | break; |
6116 | case UNLE: | |
3b2d1507 | 6117 | emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
6118 | break; |
6119 | case UNLT: | |
6120 | tem = gen_reg_rtx (mode); | |
6121 | if (TARGET_ARCH32) | |
6122 | emit_insn (gen_andsi3 (tem, result, const1_rtx)); | |
6123 | else | |
6124 | emit_insn (gen_anddi3 (tem, result, const1_rtx)); | |
3b2d1507 | 6125 | emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
6126 | break; |
6127 | case UNEQ: | |
6128 | case LTGT: | |
6129 | tem = gen_reg_rtx (mode); | |
6130 | if (TARGET_ARCH32) | |
6131 | emit_insn (gen_addsi3 (tem, result, const1_rtx)); | |
6132 | else | |
6133 | emit_insn (gen_adddi3 (tem, result, const1_rtx)); | |
6134 | tem2 = gen_reg_rtx (mode); | |
6135 | if (TARGET_ARCH32) | |
6136 | emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); | |
6137 | else | |
6138 | emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); | |
3b2d1507 AT |
6139 | emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE, |
6140 | NULL_RTX, mode, 0); | |
5c5c34a4 JJ |
6141 | break; |
6142 | } | |
47ac041c | 6143 | } |
5c5c34a4 | 6144 | |
d88e57d1 RH |
6145 | /* Generate an unsigned DImode to FP conversion. This is the same code |
6146 | optabs would emit if we didn't have TFmode patterns. */ | |
6147 | ||
6148 | void | |
fc27d102 | 6149 | sparc_emit_floatunsdi (rtx *operands) |
d88e57d1 RH |
6150 | { |
6151 | rtx neglab, donelab, i0, i1, f0, in, out; | |
6152 | enum machine_mode mode; | |
6153 | ||
6154 | out = operands[0]; | |
6155 | in = force_reg (DImode, operands[1]); | |
6156 | mode = GET_MODE (out); | |
6157 | neglab = gen_label_rtx (); | |
6158 | donelab = gen_label_rtx (); | |
6159 | i0 = gen_reg_rtx (DImode); | |
6160 | i1 = gen_reg_rtx (DImode); | |
6161 | f0 = gen_reg_rtx (mode); | |
6162 | ||
6163 | emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); | |
6164 | ||
6165 | emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in))); | |
6166 | emit_jump_insn (gen_jump (donelab)); | |
6167 | emit_barrier (); | |
6168 | ||
6169 | emit_label (neglab); | |
6170 | ||
6171 | emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); | |
6172 | emit_insn (gen_anddi3 (i1, in, const1_rtx)); | |
6173 | emit_insn (gen_iordi3 (i0, i0, i1)); | |
6174 | emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0))); | |
6175 | emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0))); | |
6176 | ||
6177 | emit_label (donelab); | |
6178 | } | |
6179 | ||
61a55e8b DE |
6180 | /* Return the string to output a conditional branch to LABEL, testing |
6181 | register REG. LABEL is the operand number of the label; REG is the | |
6182 | operand number of the reg. OP is the conditional expression. The mode | |
6183 | of REG says what kind of comparison we made. | |
6184 | ||
5e7a8ee0 | 6185 | REVERSED is nonzero if we should reverse the sense of the comparison. |
61a55e8b | 6186 | |
5e7a8ee0 | 6187 | ANNUL is nonzero if we should generate an annulling branch. |
61a55e8b | 6188 | |
5e7a8ee0 | 6189 | NOOP is nonzero if we have to follow this branch by a noop. */ |
61a55e8b DE |
6190 | |
6191 | char * | |
fc27d102 KG |
6192 | output_v9branch (rtx op, rtx dest, int reg, int label, int reversed, |
6193 | int annul, int noop, rtx insn) | |
61a55e8b | 6194 | { |
0b82d204 | 6195 | static char string[50]; |
61a55e8b DE |
6196 | enum rtx_code code = GET_CODE (op); |
6197 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
e0d80184 | 6198 | rtx note; |
0b82d204 JJ |
6199 | int far; |
6200 | char *p; | |
6201 | ||
6202 | /* branch on register are limited to +-128KB. If it is too far away, | |
6203 | change | |
6204 | ||
6205 | brnz,pt %g1, .LC30 | |
6206 | ||
6207 | to | |
6208 | ||
6209 | brz,pn %g1, .+12 | |
6210 | nop | |
6211 | ba,pt %xcc, .LC30 | |
6212 | ||
6213 | and | |
6214 | ||
6215 | brgez,a,pn %o1, .LC29 | |
6216 | ||
6217 | to | |
6218 | ||
6219 | brlz,pt %o1, .+16 | |
6220 | nop | |
6221 | ba,pt %xcc, .LC29 */ | |
6222 | ||
6223 | far = get_attr_length (insn) >= 3; | |
61a55e8b DE |
6224 | |
6225 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
0b82d204 JJ |
6226 | if (reversed ^ far) |
6227 | code = reverse_condition (code); | |
61a55e8b DE |
6228 | |
6229 | /* Only 64 bit versions of these instructions exist. */ | |
6230 | if (mode != DImode) | |
6231 | abort (); | |
6232 | ||
6233 | /* Start by writing the branch condition. */ | |
6234 | ||
6235 | switch (code) | |
6236 | { | |
6237 | case NE: | |
6238 | strcpy (string, "brnz"); | |
6239 | break; | |
6240 | ||
6241 | case EQ: | |
6242 | strcpy (string, "brz"); | |
6243 | break; | |
6244 | ||
6245 | case GE: | |
6246 | strcpy (string, "brgez"); | |
6247 | break; | |
6248 | ||
6249 | case LT: | |
6250 | strcpy (string, "brlz"); | |
6251 | break; | |
6252 | ||
6253 | case LE: | |
6254 | strcpy (string, "brlez"); | |
6255 | break; | |
6256 | ||
6257 | case GT: | |
6258 | strcpy (string, "brgz"); | |
6259 | break; | |
6260 | ||
6261 | default: | |
6262 | abort (); | |
6263 | } | |
6264 | ||
0b82d204 JJ |
6265 | p = strchr (string, '\0'); |
6266 | ||
61a55e8b | 6267 | /* Now add the annulling, reg, label, and nop. */ |
0b82d204 | 6268 | if (annul && ! far) |
e0d80184 | 6269 | { |
0b82d204 JJ |
6270 | strcpy (p, ",a"); |
6271 | p += 2; | |
e0d80184 | 6272 | } |
61a55e8b | 6273 | |
4f31cce8 | 6274 | if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) |
e0d80184 | 6275 | { |
0b82d204 | 6276 | strcpy (p, |
4f31cce8 | 6277 | ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) |
0b82d204 JJ |
6278 | ? ",pt" : ",pn"); |
6279 | p += 3; | |
e0d80184 | 6280 | } |
61a55e8b | 6281 | |
0b82d204 JJ |
6282 | *p = p < string + 8 ? '\t' : ' '; |
6283 | p++; | |
6284 | *p++ = '%'; | |
6285 | *p++ = '0' + reg; | |
6286 | *p++ = ','; | |
6287 | *p++ = ' '; | |
6288 | if (far) | |
6289 | { | |
6290 | int veryfar = 1, delta; | |
6291 | ||
6292 | if (INSN_ADDRESSES_SET_P ()) | |
6293 | { | |
6294 | delta = (INSN_ADDRESSES (INSN_UID (dest)) | |
6295 | - INSN_ADDRESSES (INSN_UID (insn))); | |
6296 | /* Leave some instructions for "slop". */ | |
6297 | if (delta >= -260000 && delta < 260000) | |
6298 | veryfar = 0; | |
6299 | } | |
6300 | ||
6301 | strcpy (p, ".+12\n\tnop\n\t"); | |
6302 | if (annul || noop) | |
6303 | p[3] = '6'; | |
6304 | p += 11; | |
6305 | if (veryfar) | |
6306 | { | |
6307 | strcpy (p, "b\t"); | |
6308 | p += 2; | |
6309 | } | |
6310 | else | |
6311 | { | |
6312 | strcpy (p, "ba,pt\t%%xcc, "); | |
6313 | p += 13; | |
6314 | } | |
6315 | } | |
6316 | *p++ = '%'; | |
6317 | *p++ = 'l'; | |
6318 | *p++ = '0' + label; | |
6319 | *p = '\0'; | |
ab835497 RK |
6320 | |
6321 | if (noop) | |
0b82d204 | 6322 | strcpy (p, "\n\tnop"); |
ab835497 RK |
6323 | |
6324 | return string; | |
6325 | } | |
6326 | ||
e48addee JJ |
6327 | /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. |
6328 | Such instructions cannot be used in the delay slot of return insn on v9. | |
6329 | If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. | |
6330 | */ | |
284d86e9 | 6331 | |
e48addee | 6332 | static int |
fc27d102 | 6333 | epilogue_renumber (register rtx *where, int test) |
284d86e9 | 6334 | { |
e48addee JJ |
6335 | register const char *fmt; |
6336 | register int i; | |
6337 | register enum rtx_code code; | |
6338 | ||
6339 | if (*where == 0) | |
6340 | return 0; | |
6341 | ||
6342 | code = GET_CODE (*where); | |
284d86e9 JC |
6343 | |
6344 | switch (code) | |
6345 | { | |
284d86e9 | 6346 | case REG: |
e48addee JJ |
6347 | if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ |
6348 | return 1; | |
6349 | if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) | |
6350 | *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); | |
6351 | case SCRATCH: | |
6352 | case CC0: | |
6353 | case PC: | |
284d86e9 JC |
6354 | case CONST_INT: |
6355 | case CONST_DOUBLE: | |
e48addee | 6356 | return 0; |
76a7c776 | 6357 | |
09ebda1b SC |
6358 | /* Do not replace the frame pointer with the stack pointer because |
6359 | it can cause the delayed instruction to load below the stack. | |
6360 | This occurs when instructions like: | |
6361 | ||
6362 | (set (reg/i:SI 24 %i0) | |
6363 | (mem/f:SI (plus:SI (reg/f:SI 30 %fp) | |
6364 | (const_int -20 [0xffffffec])) 0)) | |
6365 | ||
6366 | are in the return delayed slot. */ | |
6367 | case PLUS: | |
6368 | if (GET_CODE (XEXP (*where, 0)) == REG | |
563c12b0 | 6369 | && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM |
09ebda1b SC |
6370 | && (GET_CODE (XEXP (*where, 1)) != CONST_INT |
6371 | || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS)) | |
6372 | return 1; | |
6373 | break; | |
6374 | ||
6375 | case MEM: | |
6376 | if (SPARC_STACK_BIAS | |
6377 | && GET_CODE (XEXP (*where, 0)) == REG | |
563c12b0 | 6378 | && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM) |
09ebda1b SC |
6379 | return 1; |
6380 | break; | |
6381 | ||
76a7c776 DM |
6382 | default: |
6383 | break; | |
e48addee | 6384 | } |
284d86e9 | 6385 | |
e48addee | 6386 | fmt = GET_RTX_FORMAT (code); |
284d86e9 | 6387 | |
e48addee JJ |
6388 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
6389 | { | |
6390 | if (fmt[i] == 'E') | |
6391 | { | |
6392 | register int j; | |
6393 | for (j = XVECLEN (*where, i) - 1; j >= 0; j--) | |
6394 | if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) | |
6395 | return 1; | |
6396 | } | |
6397 | else if (fmt[i] == 'e' | |
6398 | && epilogue_renumber (&(XEXP (*where, i)), test)) | |
6399 | return 1; | |
284d86e9 | 6400 | } |
e48addee | 6401 | return 0; |
284d86e9 | 6402 | } |
ab835497 RK |
6403 | \f |
6404 | /* Leaf functions and non-leaf functions have different needs. */ | |
6405 | ||
8b60264b | 6406 | static const int |
ab835497 RK |
6407 | reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; |
6408 | ||
8b60264b | 6409 | static const int |
ab835497 RK |
6410 | reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; |
6411 | ||
8b60264b | 6412 | static const int *const reg_alloc_orders[] = { |
ab835497 RK |
6413 | reg_leaf_alloc_order, |
6414 | reg_nonleaf_alloc_order}; | |
6415 | ||
6416 | void | |
fc27d102 | 6417 | order_regs_for_local_alloc (void) |
ab835497 RK |
6418 | { |
6419 | static int last_order_nonleaf = 1; | |
6420 | ||
6421 | if (regs_ever_live[15] != last_order_nonleaf) | |
6422 | { | |
6423 | last_order_nonleaf = !last_order_nonleaf; | |
2e09e75a | 6424 | memcpy ((char *) reg_alloc_order, |
8b60264b | 6425 | (const char *) reg_alloc_orders[last_order_nonleaf], |
2e09e75a | 6426 | FIRST_PSEUDO_REGISTER * sizeof (int)); |
ab835497 RK |
6427 | } |
6428 | } | |
6429 | \f | |
e0d80184 DM |
6430 | /* Return 1 if REG and MEM are legitimate enough to allow the various |
6431 | mem<-->reg splits to be run. */ | |
6432 | ||
6433 | int | |
fc27d102 | 6434 | sparc_splitdi_legitimate (rtx reg, rtx mem) |
e0d80184 | 6435 | { |
e0d80184 DM |
6436 | /* Punt if we are here by mistake. */ |
6437 | if (! reload_completed) | |
9208e4b2 | 6438 | abort (); |
e0d80184 DM |
6439 | |
6440 | /* We must have an offsettable memory reference. */ | |
6441 | if (! offsettable_memref_p (mem)) | |
6442 | return 0; | |
6443 | ||
6444 | /* If we have legitimate args for ldd/std, we do not want | |
6445 | the split to happen. */ | |
6446 | if ((REGNO (reg) % 2) == 0 | |
6447 | && mem_min_alignment (mem, 8)) | |
6448 | return 0; | |
6449 | ||
6450 | /* Success. */ | |
6451 | return 1; | |
6452 | } | |
6453 | ||
e61c29e9 | 6454 | /* Return 1 if x and y are some kind of REG and they refer to |
fae778eb | 6455 | different hard registers. This test is guaranteed to be |
e61c29e9 DM |
6456 | run after reload. */ |
6457 | ||
6458 | int | |
fc27d102 | 6459 | sparc_absnegfloat_split_legitimate (rtx x, rtx y) |
e61c29e9 | 6460 | { |
e61c29e9 DM |
6461 | if (GET_CODE (x) != REG) |
6462 | return 0; | |
e61c29e9 DM |
6463 | if (GET_CODE (y) != REG) |
6464 | return 0; | |
6465 | if (REGNO (x) == REGNO (y)) | |
6466 | return 0; | |
6467 | return 1; | |
6468 | } | |
6469 | ||
35016322 JW |
6470 | /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. |
6471 | This makes them candidates for using ldd and std insns. | |
6472 | ||
bfd6bc60 | 6473 | Note reg1 and reg2 *must* be hard registers. */ |
35016322 JW |
6474 | |
6475 | int | |
fc27d102 | 6476 | registers_ok_for_ldd_peep (rtx reg1, rtx reg2) |
35016322 | 6477 | { |
35016322 JW |
6478 | /* We might have been passed a SUBREG. */ |
6479 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
6480 | return 0; | |
6481 | ||
35016322 JW |
6482 | if (REGNO (reg1) % 2 != 0) |
6483 | return 0; | |
6484 | ||
bfd6bc60 JC |
6485 | /* Integer ldd is deprecated in SPARC V9 */ |
6486 | if (TARGET_V9 && REGNO (reg1) < 32) | |
6487 | return 0; | |
6488 | ||
35016322 | 6489 | return (REGNO (reg1) == REGNO (reg2) - 1); |
35016322 JW |
6490 | } |
6491 | ||
2aad5d68 | 6492 | /* Return 1 if the addresses in mem1 and mem2 are suitable for use in |
303f8933 DN |
6493 | an ldd or std insn. |
6494 | ||
2aad5d68 DN |
6495 | This can only happen when addr1 and addr2, the addresses in mem1 |
6496 | and mem2, are consecutive memory locations (addr1 + 4 == addr2). | |
303f8933 DN |
6497 | addr1 must also be aligned on a 64-bit boundary. |
6498 | ||
6499 | Also iff dependent_reg_rtx is not null it should not be used to | |
6500 | compute the address for mem1, i.e. we cannot optimize a sequence | |
6501 | like: | |
6502 | ld [%o0], %o0 | |
6503 | ld [%o0 + 4], %o1 | |
6504 | to | |
bcdd764b | 6505 | ldd [%o0], %o0 |
0acf409f DM |
6506 | nor: |
6507 | ld [%g3 + 4], %g3 | |
6508 | ld [%g3], %g2 | |
6509 | to | |
6510 | ldd [%g3], %g2 | |
6511 | ||
6512 | But, note that the transformation from: | |
6513 | ld [%g2 + 4], %g3 | |
6514 | ld [%g2], %g2 | |
6515 | to | |
6516 | ldd [%g2], %g2 | |
6517 | is perfectly fine. Thus, the peephole2 patterns always pass us | |
6518 | the destination register of the first load, never the second one. | |
6519 | ||
303f8933 DN |
6520 | For stores we don't have a similar problem, so dependent_reg_rtx is |
6521 | NULL_RTX. */ | |
35016322 JW |
6522 | |
6523 | int | |
fc27d102 | 6524 | mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx) |
35016322 | 6525 | { |
2aad5d68 | 6526 | rtx addr1, addr2; |
0d587737 KG |
6527 | unsigned int reg1; |
6528 | int offset1; | |
35016322 | 6529 | |
303f8933 DN |
6530 | /* The mems cannot be volatile. */ |
6531 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
6532 | return 0; | |
2aad5d68 | 6533 | |
303f8933 | 6534 | /* MEM1 should be aligned on a 64-bit boundary. */ |
2aad5d68 DN |
6535 | if (MEM_ALIGN (mem1) < 64) |
6536 | return 0; | |
6537 | ||
303f8933 DN |
6538 | addr1 = XEXP (mem1, 0); |
6539 | addr2 = XEXP (mem2, 0); | |
6540 | ||
35016322 JW |
6541 | /* Extract a register number and offset (if used) from the first addr. */ |
6542 | if (GET_CODE (addr1) == PLUS) | |
6543 | { | |
6544 | /* If not a REG, return zero. */ | |
6545 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
6546 | return 0; | |
6547 | else | |
6548 | { | |
6549 | reg1 = REGNO (XEXP (addr1, 0)); | |
6550 | /* The offset must be constant! */ | |
6551 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
6552 | return 0; | |
6553 | offset1 = INTVAL (XEXP (addr1, 1)); | |
6554 | } | |
6555 | } | |
6556 | else if (GET_CODE (addr1) != REG) | |
6557 | return 0; | |
6558 | else | |
6559 | { | |
6560 | reg1 = REGNO (addr1); | |
6561 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
6562 | offset1 = 0; | |
6563 | } | |
6564 | ||
6565 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
6566 | if (GET_CODE (addr2) != PLUS) | |
6567 | return 0; | |
6568 | ||
6569 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
6570 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
6571 | return 0; | |
6572 | ||
35016322 JW |
6573 | if (reg1 != REGNO (XEXP (addr2, 0))) |
6574 | return 0; | |
6575 | ||
303f8933 DN |
6576 | if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx)) |
6577 | return 0; | |
6578 | ||
2296cba3 | 6579 | /* The first offset must be evenly divisible by 8 to ensure the |
35016322 JW |
6580 | address is 64 bit aligned. */ |
6581 | if (offset1 % 8 != 0) | |
6582 | return 0; | |
6583 | ||
6584 | /* The offset for the second addr must be 4 more than the first addr. */ | |
6585 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) | |
6586 | return 0; | |
6587 | ||
6588 | /* All the tests passed. addr1 and addr2 are valid for ldd and std | |
6589 | instructions. */ | |
6590 | return 1; | |
6591 | } | |
7c56249d JL |
6592 | |
6593 | /* Return 1 if reg is a pseudo, or is the first register in | |
6594 | a hard register pair. This makes it a candidate for use in | |
6595 | ldd and std insns. */ | |
6596 | ||
6597 | int | |
fc27d102 | 6598 | register_ok_for_ldd (rtx reg) |
7c56249d | 6599 | { |
7c56249d JL |
6600 | /* We might have been passed a SUBREG. */ |
6601 | if (GET_CODE (reg) != REG) | |
6602 | return 0; | |
6603 | ||
6604 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
6605 | return (REGNO (reg) % 2 == 0); | |
6606 | else | |
6607 | return 1; | |
7c56249d | 6608 | } |
ab835497 | 6609 | \f |
ab835497 RK |
6610 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
6611 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
6612 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
6613 | ||
6614 | void | |
fc27d102 | 6615 | print_operand (FILE *file, rtx x, int code) |
ab835497 RK |
6616 | { |
6617 | switch (code) | |
6618 | { | |
6619 | case '#': | |
6620 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
6621 | if (dbr_sequence_length () == 0) | |
e0d80184 | 6622 | fputs ("\n\t nop", file); |
ab835497 RK |
6623 | return; |
6624 | case '*': | |
c6ce0969 JW |
6625 | /* Output an annul flag if there's nothing for the delay slot and we |
6626 | are optimizing. This is always used with '(' below. */ | |
6627 | /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; | |
6628 | this is a dbx bug. So, we only do this when optimizing. */ | |
bfd6bc60 JC |
6629 | /* On UltraSPARC, a branch in a delay slot causes a pipeline flush. |
6630 | Always emit a nop in case the next instruction is a branch. */ | |
6631 | if (dbr_sequence_length () == 0 | |
284d86e9 | 6632 | && (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
c6ce0969 JW |
6633 | fputs (",a", file); |
6634 | return; | |
6635 | case '(': | |
6636 | /* Output a 'nop' if there's nothing for the delay slot and we are | |
6637 | not optimizing. This is always used with '*' above. */ | |
bfd6bc60 | 6638 | if (dbr_sequence_length () == 0 |
284d86e9 | 6639 | && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
e0d80184 | 6640 | fputs ("\n\t nop", file); |
ab835497 | 6641 | return; |
61a55e8b | 6642 | case '_': |
a0a301fc DE |
6643 | /* Output the Embedded Medium/Anywhere code model base register. */ |
6644 | fputs (EMBMEDANY_BASE_REG, file); | |
61a55e8b DE |
6645 | return; |
6646 | case '@': | |
6647 | /* Print out what we are using as the frame pointer. This might | |
6648 | be %fp, or might be %sp+offset. */ | |
6649 | /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ | |
6650 | fprintf (file, "%s+%d", frame_base_name, frame_base_offset); | |
6651 | return; | |
5751a10b JJ |
6652 | case '&': |
6653 | /* Print some local dynamic TLS name. */ | |
6654 | assemble_name (file, get_some_local_dynamic_name ()); | |
6655 | return; | |
ab835497 RK |
6656 | case 'Y': |
6657 | /* Adjust the operand to take into account a RESTORE operation. */ | |
bfd6bc60 JC |
6658 | if (GET_CODE (x) == CONST_INT) |
6659 | break; | |
6660 | else if (GET_CODE (x) != REG) | |
c725bd79 | 6661 | output_operand_lossage ("invalid %%Y operand"); |
b3b1e8bd | 6662 | else if (REGNO (x) < 8) |
ab835497 RK |
6663 | fputs (reg_names[REGNO (x)], file); |
6664 | else if (REGNO (x) >= 24 && REGNO (x) < 32) | |
6665 | fputs (reg_names[REGNO (x)-16], file); | |
6666 | else | |
c725bd79 | 6667 | output_operand_lossage ("invalid %%Y operand"); |
ab835497 | 6668 | return; |
0f39a9aa DE |
6669 | case 'L': |
6670 | /* Print out the low order register name of a register pair. */ | |
6671 | if (WORDS_BIG_ENDIAN) | |
6672 | fputs (reg_names[REGNO (x)+1], file); | |
6673 | else | |
6674 | fputs (reg_names[REGNO (x)], file); | |
6675 | return; | |
6676 | case 'H': | |
6677 | /* Print out the high order register name of a register pair. */ | |
6678 | if (WORDS_BIG_ENDIAN) | |
6679 | fputs (reg_names[REGNO (x)], file); | |
6680 | else | |
6681 | fputs (reg_names[REGNO (x)+1], file); | |
6682 | return; | |
ab835497 | 6683 | case 'R': |
795068a4 | 6684 | /* Print out the second register name of a register pair or quad. |
ab835497 RK |
6685 | I.e., R (%o0) => %o1. */ |
6686 | fputs (reg_names[REGNO (x)+1], file); | |
6687 | return; | |
795068a4 JW |
6688 | case 'S': |
6689 | /* Print out the third register name of a register quad. | |
6690 | I.e., S (%o0) => %o2. */ | |
6691 | fputs (reg_names[REGNO (x)+2], file); | |
6692 | return; | |
6693 | case 'T': | |
6694 | /* Print out the fourth register name of a register quad. | |
6695 | I.e., T (%o0) => %o3. */ | |
6696 | fputs (reg_names[REGNO (x)+3], file); | |
6697 | return; | |
304b7a23 DE |
6698 | case 'x': |
6699 | /* Print a condition code register. */ | |
6700 | if (REGNO (x) == SPARC_ICC_REG) | |
6701 | { | |
6702 | /* We don't handle CC[X]_NOOVmode because they're not supposed | |
6703 | to occur here. */ | |
6704 | if (GET_MODE (x) == CCmode) | |
6705 | fputs ("%icc", file); | |
6706 | else if (GET_MODE (x) == CCXmode) | |
6707 | fputs ("%xcc", file); | |
6708 | else | |
6709 | abort (); | |
6710 | } | |
6711 | else | |
6712 | /* %fccN register */ | |
6713 | fputs (reg_names[REGNO (x)], file); | |
6714 | return; | |
ab835497 RK |
6715 | case 'm': |
6716 | /* Print the operand's address only. */ | |
6717 | output_address (XEXP (x, 0)); | |
6718 | return; | |
6719 | case 'r': | |
6720 | /* In this case we need a register. Use %g0 if the | |
77a02b01 | 6721 | operand is const0_rtx. */ |
76052e74 RS |
6722 | if (x == const0_rtx |
6723 | || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) | |
ab835497 RK |
6724 | { |
6725 | fputs ("%g0", file); | |
6726 | return; | |
6727 | } | |
6728 | else | |
6729 | break; | |
6730 | ||
61a55e8b | 6731 | case 'A': |
ab835497 RK |
6732 | switch (GET_CODE (x)) |
6733 | { | |
6734 | case IOR: fputs ("or", file); break; | |
6735 | case AND: fputs ("and", file); break; | |
6736 | case XOR: fputs ("xor", file); break; | |
c725bd79 | 6737 | default: output_operand_lossage ("invalid %%A operand"); |
ab835497 RK |
6738 | } |
6739 | return; | |
6740 | ||
6741 | case 'B': | |
6742 | switch (GET_CODE (x)) | |
6743 | { | |
6744 | case IOR: fputs ("orn", file); break; | |
6745 | case AND: fputs ("andn", file); break; | |
6746 | case XOR: fputs ("xnor", file); break; | |
c725bd79 | 6747 | default: output_operand_lossage ("invalid %%B operand"); |
ab835497 RK |
6748 | } |
6749 | return; | |
6750 | ||
304b7a23 DE |
6751 | /* These are used by the conditional move instructions. */ |
6752 | case 'c' : | |
61a55e8b | 6753 | case 'C': |
304b7a23 | 6754 | { |
5c5c34a4 JJ |
6755 | enum rtx_code rc = GET_CODE (x); |
6756 | ||
6757 | if (code == 'c') | |
6758 | { | |
6759 | enum machine_mode mode = GET_MODE (XEXP (x, 0)); | |
6760 | if (mode == CCFPmode || mode == CCFPEmode) | |
6761 | rc = reverse_condition_maybe_unordered (GET_CODE (x)); | |
6762 | else | |
6763 | rc = reverse_condition (GET_CODE (x)); | |
6764 | } | |
304b7a23 DE |
6765 | switch (rc) |
6766 | { | |
6767 | case NE: fputs ("ne", file); break; | |
6768 | case EQ: fputs ("e", file); break; | |
6769 | case GE: fputs ("ge", file); break; | |
6770 | case GT: fputs ("g", file); break; | |
6771 | case LE: fputs ("le", file); break; | |
6772 | case LT: fputs ("l", file); break; | |
6773 | case GEU: fputs ("geu", file); break; | |
6774 | case GTU: fputs ("gu", file); break; | |
6775 | case LEU: fputs ("leu", file); break; | |
6776 | case LTU: fputs ("lu", file); break; | |
5c5c34a4 JJ |
6777 | case LTGT: fputs ("lg", file); break; |
6778 | case UNORDERED: fputs ("u", file); break; | |
6779 | case ORDERED: fputs ("o", file); break; | |
6780 | case UNLT: fputs ("ul", file); break; | |
6781 | case UNLE: fputs ("ule", file); break; | |
6782 | case UNGT: fputs ("ug", file); break; | |
6783 | case UNGE: fputs ("uge", file); break; | |
6784 | case UNEQ: fputs ("ue", file); break; | |
304b7a23 | 6785 | default: output_operand_lossage (code == 'c' |
c725bd79 NB |
6786 | ? "invalid %%c operand" |
6787 | : "invalid %%C operand"); | |
304b7a23 DE |
6788 | } |
6789 | return; | |
6790 | } | |
6791 | ||
6792 | /* These are used by the movr instruction pattern. */ | |
6793 | case 'd': | |
61a55e8b | 6794 | case 'D': |
304b7a23 DE |
6795 | { |
6796 | enum rtx_code rc = (code == 'd' | |
6797 | ? reverse_condition (GET_CODE (x)) | |
6798 | : GET_CODE (x)); | |
6799 | switch (rc) | |
6800 | { | |
6801 | case NE: fputs ("ne", file); break; | |
6802 | case EQ: fputs ("e", file); break; | |
6803 | case GE: fputs ("gez", file); break; | |
6804 | case LT: fputs ("lz", file); break; | |
6805 | case LE: fputs ("lez", file); break; | |
6806 | case GT: fputs ("gz", file); break; | |
6807 | default: output_operand_lossage (code == 'd' | |
c725bd79 NB |
6808 | ? "invalid %%d operand" |
6809 | : "invalid %%D operand"); | |
304b7a23 DE |
6810 | } |
6811 | return; | |
6812 | } | |
61a55e8b | 6813 | |
ab835497 RK |
6814 | case 'b': |
6815 | { | |
6816 | /* Print a sign-extended character. */ | |
9e0625a3 | 6817 | int i = trunc_int_for_mode (INTVAL (x), QImode); |
ab835497 RK |
6818 | fprintf (file, "%d", i); |
6819 | return; | |
6820 | } | |
6821 | ||
d2889939 RK |
6822 | case 'f': |
6823 | /* Operand must be a MEM; write its address. */ | |
6824 | if (GET_CODE (x) != MEM) | |
c725bd79 | 6825 | output_operand_lossage ("invalid %%f operand"); |
d2889939 RK |
6826 | output_address (XEXP (x, 0)); |
6827 | return; | |
6828 | ||
8707fe93 RH |
6829 | case 's': |
6830 | { | |
6831 | /* Print a sign-extended 32-bit value. */ | |
6832 | HOST_WIDE_INT i; | |
6833 | if (GET_CODE(x) == CONST_INT) | |
6834 | i = INTVAL (x); | |
6835 | else if (GET_CODE(x) == CONST_DOUBLE) | |
6836 | i = CONST_DOUBLE_LOW (x); | |
6837 | else | |
ffa916ba KG |
6838 | { |
6839 | output_operand_lossage ("invalid %%s operand"); | |
6840 | return; | |
6841 | } | |
8707fe93 RH |
6842 | i = trunc_int_for_mode (i, SImode); |
6843 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, i); | |
6844 | return; | |
6845 | } | |
6846 | ||
ab835497 RK |
6847 | case 0: |
6848 | /* Do nothing special. */ | |
6849 | break; | |
6850 | ||
6851 | default: | |
6852 | /* Undocumented flag. */ | |
415f583e | 6853 | output_operand_lossage ("invalid operand output code"); |
ab835497 RK |
6854 | } |
6855 | ||
6856 | if (GET_CODE (x) == REG) | |
6857 | fputs (reg_names[REGNO (x)], file); | |
6858 | else if (GET_CODE (x) == MEM) | |
6859 | { | |
6860 | fputc ('[', file); | |
ab835497 | 6861 | /* Poor Sun assembler doesn't understand absolute addressing. */ |
e6c1be7e | 6862 | if (CONSTANT_P (XEXP (x, 0))) |
ab835497 RK |
6863 | fputs ("%g0+", file); |
6864 | output_address (XEXP (x, 0)); | |
6865 | fputc (']', file); | |
6866 | } | |
6867 | else if (GET_CODE (x) == HIGH) | |
6868 | { | |
6869 | fputs ("%hi(", file); | |
6870 | output_addr_const (file, XEXP (x, 0)); | |
6871 | fputc (')', file); | |
6872 | } | |
6873 | else if (GET_CODE (x) == LO_SUM) | |
6874 | { | |
6875 | print_operand (file, XEXP (x, 0), 0); | |
e0d80184 DM |
6876 | if (TARGET_CM_MEDMID) |
6877 | fputs ("+%l44(", file); | |
6878 | else | |
6879 | fputs ("+%lo(", file); | |
ab835497 RK |
6880 | output_addr_const (file, XEXP (x, 1)); |
6881 | fputc (')', file); | |
6882 | } | |
e601abce JW |
6883 | else if (GET_CODE (x) == CONST_DOUBLE |
6884 | && (GET_MODE (x) == VOIDmode | |
6885 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) | |
ab835497 RK |
6886 | { |
6887 | if (CONST_DOUBLE_HIGH (x) == 0) | |
0d9484c5 | 6888 | fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x)); |
ab835497 RK |
6889 | else if (CONST_DOUBLE_HIGH (x) == -1 |
6890 | && CONST_DOUBLE_LOW (x) < 0) | |
0d9484c5 | 6891 | fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x)); |
ab835497 | 6892 | else |
e601abce | 6893 | output_operand_lossage ("long long constant not a valid immediate operand"); |
ab835497 | 6894 | } |
e601abce JW |
6895 | else if (GET_CODE (x) == CONST_DOUBLE) |
6896 | output_operand_lossage ("floating point constant not a valid immediate operand"); | |
ab835497 RK |
6897 | else { output_addr_const (file, x); } |
6898 | } | |
6899 | \f | |
301d03af RS |
6900 | /* Target hook for assembling integer objects. The sparc version has |
6901 | special handling for aligned DI-mode objects. */ | |
ab835497 | 6902 | |
301d03af | 6903 | static bool |
fc27d102 | 6904 | sparc_assemble_integer (rtx x, unsigned int size, int aligned_p) |
ab835497 | 6905 | { |
301d03af RS |
6906 | /* ??? We only output .xword's for symbols and only then in environments |
6907 | where the assembler can handle them. */ | |
6908 | if (aligned_p && size == 8 | |
6909 | && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE)) | |
ab835497 | 6910 | { |
301d03af | 6911 | if (TARGET_V9) |
61a55e8b | 6912 | { |
301d03af RS |
6913 | assemble_integer_with_op ("\t.xword\t", x); |
6914 | return true; | |
61a55e8b DE |
6915 | } |
6916 | else | |
6917 | { | |
301d03af RS |
6918 | assemble_aligned_integer (4, const0_rtx); |
6919 | assemble_aligned_integer (4, x); | |
6920 | return true; | |
61a55e8b | 6921 | } |
ab835497 | 6922 | } |
301d03af | 6923 | return default_assemble_integer (x, size, aligned_p); |
ab835497 | 6924 | } |
210aa14a | 6925 | \f |
b0468b84 RK |
6926 | /* Return the value of a code used in the .proc pseudo-op that says |
6927 | what kind of result this function returns. For non-C types, we pick | |
6928 | the closest C type. */ | |
6929 | ||
77a02b01 JW |
6930 | #ifndef SHORT_TYPE_SIZE |
6931 | #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) | |
6932 | #endif | |
6933 | ||
6934 | #ifndef INT_TYPE_SIZE | |
6935 | #define INT_TYPE_SIZE BITS_PER_WORD | |
6936 | #endif | |
6937 | ||
6938 | #ifndef LONG_TYPE_SIZE | |
6939 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
6940 | #endif | |
6941 | ||
6942 | #ifndef LONG_LONG_TYPE_SIZE | |
6943 | #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) | |
6944 | #endif | |
6945 | ||
6946 | #ifndef FLOAT_TYPE_SIZE | |
6947 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
6948 | #endif | |
6949 | ||
6950 | #ifndef DOUBLE_TYPE_SIZE | |
6951 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
6952 | #endif | |
6953 | ||
6954 | #ifndef LONG_DOUBLE_TYPE_SIZE | |
6955 | #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
6956 | #endif | |
210aa14a RS |
6957 | |
6958 | unsigned long | |
fc27d102 | 6959 | sparc_type_code (register tree type) |
210aa14a RS |
6960 | { |
6961 | register unsigned long qualifiers = 0; | |
e5e809f4 | 6962 | register unsigned shift; |
210aa14a | 6963 | |
abc95ed3 | 6964 | /* Only the first 30 bits of the qualifier are valid. We must refrain from |
aee2c3c5 JW |
6965 | setting more, since some assemblers will give an error for this. Also, |
6966 | we must be careful to avoid shifts of 32 bits or more to avoid getting | |
6967 | unpredictable results. */ | |
6968 | ||
e5e809f4 | 6969 | for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) |
210aa14a RS |
6970 | { |
6971 | switch (TREE_CODE (type)) | |
6972 | { | |
6973 | case ERROR_MARK: | |
6974 | return qualifiers; | |
6975 | ||
6976 | case ARRAY_TYPE: | |
e5e809f4 | 6977 | qualifiers |= (3 << shift); |
210aa14a RS |
6978 | break; |
6979 | ||
6980 | case FUNCTION_TYPE: | |
6981 | case METHOD_TYPE: | |
e5e809f4 | 6982 | qualifiers |= (2 << shift); |
210aa14a RS |
6983 | break; |
6984 | ||
6985 | case POINTER_TYPE: | |
6986 | case REFERENCE_TYPE: | |
6987 | case OFFSET_TYPE: | |
e5e809f4 | 6988 | qualifiers |= (1 << shift); |
210aa14a | 6989 | break; |
ab835497 | 6990 | |
210aa14a RS |
6991 | case RECORD_TYPE: |
6992 | return (qualifiers | 8); | |
6993 | ||
6994 | case UNION_TYPE: | |
b0468b84 | 6995 | case QUAL_UNION_TYPE: |
210aa14a RS |
6996 | return (qualifiers | 9); |
6997 | ||
6998 | case ENUMERAL_TYPE: | |
6999 | return (qualifiers | 10); | |
7000 | ||
7001 | case VOID_TYPE: | |
7002 | return (qualifiers | 16); | |
7003 | ||
7004 | case INTEGER_TYPE: | |
654209e6 JW |
7005 | /* If this is a range type, consider it to be the underlying |
7006 | type. */ | |
7007 | if (TREE_TYPE (type) != 0) | |
e5e809f4 | 7008 | break; |
654209e6 | 7009 | |
77a02b01 | 7010 | /* Carefully distinguish all the standard types of C, |
b0468b84 RK |
7011 | without messing up if the language is not C. We do this by |
7012 | testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to | |
7013 | look at both the names and the above fields, but that's redundant. | |
7014 | Any type whose size is between two C types will be considered | |
7015 | to be the wider of the two types. Also, we do not have a | |
7016 | special code to use for "long long", so anything wider than | |
7017 | long is treated the same. Note that we can't distinguish | |
7018 | between "int" and "long" in this code if they are the same | |
7019 | size, but that's fine, since neither can the assembler. */ | |
7020 | ||
7021 | if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) | |
7022 | return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); | |
77a02b01 | 7023 | |
b0468b84 RK |
7024 | else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) |
7025 | return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); | |
77a02b01 | 7026 | |
b0468b84 | 7027 | else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) |
77a02b01 JW |
7028 | return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); |
7029 | ||
b0468b84 | 7030 | else |
77a02b01 JW |
7031 | return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); |
7032 | ||
210aa14a | 7033 | case REAL_TYPE: |
e5e809f4 JL |
7034 | /* If this is a range type, consider it to be the underlying |
7035 | type. */ | |
7036 | if (TREE_TYPE (type) != 0) | |
7037 | break; | |
7038 | ||
77a02b01 JW |
7039 | /* Carefully distinguish all the standard types of C, |
7040 | without messing up if the language is not C. */ | |
b0468b84 | 7041 | |
77a02b01 | 7042 | if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) |
210aa14a | 7043 | return (qualifiers | 6); |
b0468b84 RK |
7044 | |
7045 | else | |
7046 | return (qualifiers | 7); | |
210aa14a RS |
7047 | |
7048 | case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ | |
13d39dbc | 7049 | /* ??? We need to distinguish between double and float complex types, |
c82aa69a JW |
7050 | but I don't know how yet because I can't reach this code from |
7051 | existing front-ends. */ | |
7052 | return (qualifiers | 7); /* Who knows? */ | |
7053 | ||
210aa14a RS |
7054 | case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ |
7055 | case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ | |
7056 | case FILE_TYPE: /* GNU Pascal FILE type. */ | |
26902ae0 | 7057 | case SET_TYPE: /* GNU Pascal SET type. */ |
210aa14a | 7058 | case LANG_TYPE: /* ? */ |
26902ae0 | 7059 | return qualifiers; |
210aa14a RS |
7060 | |
7061 | default: | |
7062 | abort (); /* Not a type! */ | |
7063 | } | |
7064 | } | |
e5e809f4 JL |
7065 | |
7066 | return qualifiers; | |
210aa14a | 7067 | } |
ead69aea | 7068 | \f |
61a55e8b DE |
7069 | /* Nested function support. */ |
7070 | ||
7071 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
7072 | FNADDR is an RTX for the address of the function's pure code. | |
7073 | CXT is an RTX for the static chain value for the function. | |
7074 | ||
7075 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
7076 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
7077 | (to store insns). This is a bit excessive. Perhaps a different | |
7078 | mechanism would be better here. | |
7079 | ||
849a528d | 7080 | Emit enough FLUSH insns to synchronize the data and instruction caches. */ |
61a55e8b DE |
7081 | |
7082 | void | |
fc27d102 | 7083 | sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt) |
61a55e8b | 7084 | { |
c6b0465b JC |
7085 | /* SPARC 32 bit trampoline: |
7086 | ||
e0d80184 DM |
7087 | sethi %hi(fn), %g1 |
7088 | sethi %hi(static), %g2 | |
7089 | jmp %g1+%lo(fn) | |
7090 | or %g2, %lo(static), %g2 | |
c6b0465b JC |
7091 | |
7092 | SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii | |
7093 | JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii | |
7094 | */ | |
959eb758 DM |
7095 | #ifdef TRANSFER_FROM_TRAMPOLINE |
7096 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
eb29ddb6 | 7097 | LCT_NORMAL, VOIDmode, 1, tramp, Pmode); |
959eb758 | 7098 | #endif |
c6b0465b | 7099 | |
35aa3c1c RK |
7100 | emit_move_insn |
7101 | (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), | |
7102 | expand_binop (SImode, ior_optab, | |
7103 | expand_shift (RSHIFT_EXPR, SImode, fnaddr, | |
7104 | size_int (10), 0, 1), | |
7105 | GEN_INT (trunc_int_for_mode (0x03000000, SImode)), | |
7106 | NULL_RTX, 1, OPTAB_DIRECT)); | |
7107 | ||
7108 | emit_move_insn | |
7109 | (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), | |
7110 | expand_binop (SImode, ior_optab, | |
7111 | expand_shift (RSHIFT_EXPR, SImode, cxt, | |
7112 | size_int (10), 0, 1), | |
7113 | GEN_INT (trunc_int_for_mode (0x05000000, SImode)), | |
7114 | NULL_RTX, 1, OPTAB_DIRECT)); | |
7115 | ||
7116 | emit_move_insn | |
7117 | (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), | |
7118 | expand_binop (SImode, ior_optab, | |
7119 | expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX), | |
7120 | GEN_INT (trunc_int_for_mode (0x81c06000, SImode)), | |
7121 | NULL_RTX, 1, OPTAB_DIRECT)); | |
7122 | ||
7123 | emit_move_insn | |
7124 | (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), | |
7125 | expand_binop (SImode, ior_optab, | |
7126 | expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX), | |
7127 | GEN_INT (trunc_int_for_mode (0x8410a000, SImode)), | |
7128 | NULL_RTX, 1, OPTAB_DIRECT)); | |
c6b0465b | 7129 | |
c6b0465b JC |
7130 | /* On UltraSPARC a flush flushes an entire cache line. The trampoline is |
7131 | aligned on a 16 byte boundary so one flush clears it all. */ | |
35aa3c1c | 7132 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); |
84643cbf DM |
7133 | if (sparc_cpu != PROCESSOR_ULTRASPARC |
7134 | && sparc_cpu != PROCESSOR_ULTRASPARC3) | |
c6b0465b JC |
7135 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, |
7136 | plus_constant (tramp, 8))))); | |
61a55e8b DE |
7137 | } |
7138 | ||
849a528d RK |
7139 | /* The 64 bit version is simpler because it makes more sense to load the |
7140 | values as "immediate" data out of the trampoline. It's also easier since | |
7141 | we can read the PC without clobbering a register. */ | |
7142 | ||
61a55e8b | 7143 | void |
fc27d102 | 7144 | sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt) |
61a55e8b | 7145 | { |
345a6161 DM |
7146 | #ifdef TRANSFER_FROM_TRAMPOLINE |
7147 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
eb29ddb6 | 7148 | LCT_NORMAL, VOIDmode, 1, tramp, Pmode); |
345a6161 DM |
7149 | #endif |
7150 | ||
c6b0465b | 7151 | /* |
e0d80184 DM |
7152 | rd %pc, %g1 |
7153 | ldx [%g1+24], %g5 | |
7154 | jmp %g5 | |
7155 | ldx [%g1+16], %g5 | |
c6b0465b JC |
7156 | +16 bytes data |
7157 | */ | |
7158 | ||
7159 | emit_move_insn (gen_rtx_MEM (SImode, tramp), | |
e3aaacf4 | 7160 | GEN_INT (trunc_int_for_mode (0x83414000, SImode))); |
c6b0465b | 7161 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), |
e3aaacf4 | 7162 | GEN_INT (trunc_int_for_mode (0xca586018, SImode))); |
c6b0465b | 7163 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), |
e3aaacf4 | 7164 | GEN_INT (trunc_int_for_mode (0x81c14000, SImode))); |
c6b0465b | 7165 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), |
e3aaacf4 | 7166 | GEN_INT (trunc_int_for_mode (0xca586010, SImode))); |
c6b0465b | 7167 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); |
345a6161 | 7168 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); |
d4203cb4 | 7169 | emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp)))); |
345a6161 | 7170 | |
fae15c93 VM |
7171 | if (sparc_cpu != PROCESSOR_ULTRASPARC |
7172 | && sparc_cpu != PROCESSOR_ULTRASPARC3) | |
d4203cb4 | 7173 | emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); |
61a55e8b DE |
7174 | } |
7175 | \f | |
c819be5b JW |
7176 | /* Subroutines to support a flat (single) register window calling |
7177 | convention. */ | |
7178 | ||
7179 | /* Single-register window sparc stack frames look like: | |
7180 | ||
7181 | Before call After call | |
7182 | +-----------------------+ +-----------------------+ | |
86735b02 DE |
7183 | high | | | | |
7184 | mem | caller's temps. | | caller's temps. | | |
c819be5b JW |
7185 | | | | | |
7186 | +-----------------------+ +-----------------------+ | |
7187 | | | | | | |
7188 | | arguments on stack. | | arguments on stack. | | |
86735b02 DE |
7189 | | | | | |
7190 | +-----------------------+FP+92->+-----------------------+ | |
c819be5b JW |
7191 | | 6 words to save | | 6 words to save | |
7192 | | arguments passed | | arguments passed | | |
7193 | | in registers, even | | in registers, even | | |
86735b02 DE |
7194 | | if not passed. | | if not passed. | |
7195 | SP+68->+-----------------------+FP+68->+-----------------------+ | |
7196 | | 1 word struct addr | | 1 word struct addr | | |
7197 | +-----------------------+FP+64->+-----------------------+ | |
7198 | | | | | | |
7199 | | 16 word reg save area | | 16 word reg save area | | |
7200 | | | | | | |
7201 | SP->+-----------------------+ FP->+-----------------------+ | |
7202 | | 4 word area for | | |
7203 | | fp/alu reg moves | | |
7204 | FP-16->+-----------------------+ | |
7205 | | | | |
7206 | | local variables | | |
7207 | | | | |
7208 | +-----------------------+ | |
7209 | | | | |
c819be5b | 7210 | | fp register save | |
86735b02 DE |
7211 | | | |
7212 | +-----------------------+ | |
7213 | | | | |
c819be5b JW |
7214 | | gp register save | |
7215 | | | | |
86735b02 DE |
7216 | +-----------------------+ |
7217 | | | | |
c819be5b | 7218 | | alloca allocations | |
86735b02 DE |
7219 | | | |
7220 | +-----------------------+ | |
7221 | | | | |
c819be5b | 7222 | | arguments on stack | |
86735b02 DE |
7223 | | | |
7224 | SP+92->+-----------------------+ | |
c819be5b | 7225 | | 6 words to save | |
86735b02 | 7226 | | arguments passed | |
c819be5b | 7227 | | in registers, even | |
86735b02 DE |
7228 | low | if not passed. | |
7229 | memory SP+68->+-----------------------+ | |
7230 | | 1 word struct addr | | |
7231 | SP+64->+-----------------------+ | |
7232 | | | | |
7233 | I 16 word reg save area | | |
7234 | | | | |
7235 | SP->+-----------------------+ */ | |
c819be5b | 7236 | |
c6aa9ce1 | 7237 | /* Structure to be filled in by sparc_flat_compute_frame_size with register |
c819be5b JW |
7238 | save masks, and offsets for the current function. */ |
7239 | ||
7240 | struct sparc_frame_info | |
7241 | { | |
7242 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
7243 | unsigned long var_size; /* # bytes that variables take up. */ | |
7244 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
7245 | unsigned long extra_size; /* # bytes of extra gunk. */ | |
7246 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
7247 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 7248 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 7249 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 | 7250 | unsigned long reg_offset; /* Offset from new sp to store regs. */ |
c819be5b JW |
7251 | int initialized; /* Nonzero if frame size already calculated. */ |
7252 | }; | |
7253 | ||
c6aa9ce1 | 7254 | /* Current frame information calculated by sparc_flat_compute_frame_size. */ |
c819be5b JW |
7255 | struct sparc_frame_info current_frame_info; |
7256 | ||
7257 | /* Zero structure to initialize current_frame_info. */ | |
7258 | struct sparc_frame_info zero_frame_info; | |
7259 | ||
7260 | /* Tell prologue and epilogue if register REGNO should be saved / restored. */ | |
7261 | ||
86735b02 | 7262 | #define RETURN_ADDR_REGNUM 15 |
563c12b0 | 7263 | #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM)) |
86735b02 DE |
7264 | #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) |
7265 | ||
c819be5b | 7266 | #define MUST_SAVE_REGISTER(regno) \ |
563c12b0 RH |
7267 | ((regs_ever_live[regno] && !call_used_regs[regno]) \ |
7268 | || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \ | |
86735b02 | 7269 | || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM])) |
c819be5b JW |
7270 | |
7271 | /* Return the bytes needed to compute the frame pointer from the current | |
7272 | stack pointer. */ | |
7273 | ||
7274 | unsigned long | |
fc27d102 KG |
7275 | sparc_flat_compute_frame_size (int size) |
7276 | /* # of var. bytes allocated. */ | |
c819be5b JW |
7277 | { |
7278 | int regno; | |
7279 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
7280 | unsigned long var_size; /* # bytes that variables take up. */ | |
7281 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
7282 | unsigned long extra_size; /* # extra bytes. */ | |
7283 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
7284 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 7285 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 7286 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 DE |
7287 | unsigned long reg_offset; /* Offset to register save area. */ |
7288 | int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ | |
c819be5b JW |
7289 | |
7290 | /* This is the size of the 16 word reg save area, 1 word struct addr | |
7291 | area, and 4 word fp/alu register copy area. */ | |
8c64be75 SC |
7292 | extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); |
7293 | var_size = size; | |
7294 | gp_reg_size = 0; | |
7295 | fp_reg_size = 0; | |
7296 | gmask = 0; | |
7297 | fmask = 0; | |
7298 | reg_offset = 0; | |
86735b02 | 7299 | need_aligned_p = 0; |
c819be5b | 7300 | |
8c64be75 SC |
7301 | args_size = 0; |
7302 | if (!leaf_function_p ()) | |
7303 | { | |
7304 | /* Also include the size needed for the 6 parameter registers. */ | |
7305 | args_size = current_function_outgoing_args_size + 24; | |
7306 | } | |
7307 | total_size = var_size + args_size; | |
7308 | ||
c819be5b JW |
7309 | /* Calculate space needed for gp registers. */ |
7310 | for (regno = 1; regno <= 31; regno++) | |
7311 | { | |
7312 | if (MUST_SAVE_REGISTER (regno)) | |
7313 | { | |
86735b02 DE |
7314 | /* If we need to save two regs in a row, ensure there's room to bump |
7315 | up the address to align it to a doubleword boundary. */ | |
c819be5b JW |
7316 | if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) |
7317 | { | |
7318 | if (gp_reg_size % 8 != 0) | |
86735b02 | 7319 | gp_reg_size += 4; |
c819be5b | 7320 | gp_reg_size += 2 * UNITS_PER_WORD; |
86735b02 | 7321 | gmask |= 3 << regno; |
c819be5b | 7322 | regno++; |
86735b02 | 7323 | need_aligned_p = 1; |
c819be5b JW |
7324 | } |
7325 | else | |
7326 | { | |
7327 | gp_reg_size += UNITS_PER_WORD; | |
86735b02 | 7328 | gmask |= 1 << regno; |
c819be5b JW |
7329 | } |
7330 | } | |
7331 | } | |
c819be5b JW |
7332 | |
7333 | /* Calculate space needed for fp registers. */ | |
7334 | for (regno = 32; regno <= 63; regno++) | |
7335 | { | |
7336 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
7337 | { | |
7338 | fp_reg_size += UNITS_PER_WORD; | |
7339 | fmask |= 1 << (regno - 32); | |
7340 | } | |
7341 | } | |
7342 | ||
86735b02 DE |
7343 | if (gmask || fmask) |
7344 | { | |
7345 | int n; | |
7346 | reg_offset = FIRST_PARM_OFFSET(0) + args_size; | |
7347 | /* Ensure save area is 8 byte aligned if we need it. */ | |
7348 | n = reg_offset % 8; | |
7349 | if (need_aligned_p && n != 0) | |
7350 | { | |
7351 | total_size += 8 - n; | |
7352 | reg_offset += 8 - n; | |
7353 | } | |
7354 | total_size += gp_reg_size + fp_reg_size; | |
7355 | } | |
c819be5b | 7356 | |
8c64be75 SC |
7357 | /* If we must allocate a stack frame at all, we must also allocate |
7358 | room for register window spillage, so as to be binary compatible | |
7359 | with libraries and operating systems that do not use -mflat. */ | |
7360 | if (total_size > 0) | |
7361 | total_size += extra_size; | |
7362 | else | |
7363 | extra_size = 0; | |
c819be5b JW |
7364 | |
7365 | total_size = SPARC_STACK_ALIGN (total_size); | |
7366 | ||
7367 | /* Save other computed information. */ | |
7368 | current_frame_info.total_size = total_size; | |
7369 | current_frame_info.var_size = var_size; | |
7370 | current_frame_info.args_size = args_size; | |
7371 | current_frame_info.extra_size = extra_size; | |
7372 | current_frame_info.gp_reg_size = gp_reg_size; | |
7373 | current_frame_info.fp_reg_size = fp_reg_size; | |
86735b02 | 7374 | current_frame_info.gmask = gmask; |
c819be5b | 7375 | current_frame_info.fmask = fmask; |
86735b02 | 7376 | current_frame_info.reg_offset = reg_offset; |
c819be5b JW |
7377 | current_frame_info.initialized = reload_completed; |
7378 | ||
c819be5b JW |
7379 | /* Ok, we're done. */ |
7380 | return total_size; | |
7381 | } | |
7382 | \f | |
86735b02 DE |
7383 | /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset |
7384 | OFFSET. | |
7385 | ||
7386 | BASE_REG must be 8 byte aligned. This allows us to test OFFSET for | |
7387 | appropriate alignment and use DOUBLEWORD_OP when we can. We assume | |
7388 | [BASE_REG+OFFSET] will always be a valid address. | |
7389 | ||
7390 | WORD_OP is either "st" for save, "ld" for restore. | |
7391 | DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ | |
c819be5b JW |
7392 | |
7393 | void | |
fc27d102 KG |
7394 | sparc_flat_save_restore (FILE *file, const char *base_reg, |
7395 | unsigned int offset, long unsigned int gmask, | |
7396 | long unsigned int fmask, const char *word_op, | |
7397 | const char *doubleword_op, | |
7398 | long unsigned int base_offset) | |
c819be5b JW |
7399 | { |
7400 | int regno; | |
c819be5b | 7401 | |
86735b02 DE |
7402 | if (gmask == 0 && fmask == 0) |
7403 | return; | |
c819be5b | 7404 | |
86735b02 DE |
7405 | /* Save registers starting from high to low. We've already saved the |
7406 | previous frame pointer and previous return address for the debugger's | |
7407 | sake. The debugger allows us to not need a nop in the epilog if at least | |
7408 | one register is reloaded in addition to return address. */ | |
c819be5b | 7409 | |
86735b02 | 7410 | if (gmask) |
c819be5b JW |
7411 | { |
7412 | for (regno = 1; regno <= 31; regno++) | |
7413 | { | |
86735b02 | 7414 | if ((gmask & (1L << regno)) != 0) |
c819be5b | 7415 | { |
86735b02 | 7416 | if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) |
c819be5b | 7417 | { |
86735b02 DE |
7418 | /* We can save two registers in a row. If we're not at a |
7419 | double word boundary, move to one. | |
7420 | sparc_flat_compute_frame_size ensures there's room to do | |
7421 | this. */ | |
7422 | if (offset % 8 != 0) | |
7423 | offset += UNITS_PER_WORD; | |
7424 | ||
c819be5b | 7425 | if (word_op[0] == 's') |
c53aa195 | 7426 | { |
e0d80184 | 7427 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
7428 | doubleword_op, reg_names[regno], |
7429 | base_reg, offset); | |
0021b564 | 7430 | if (dwarf2out_do_frame ()) |
c53aa195 | 7431 | { |
96987e96 | 7432 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
7433 | dwarf2out_reg_save (l, regno, offset + base_offset); |
7434 | dwarf2out_reg_save | |
7435 | (l, regno+1, offset+base_offset + UNITS_PER_WORD); | |
7436 | } | |
c53aa195 | 7437 | } |
c819be5b | 7438 | else |
e0d80184 | 7439 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 7440 | doubleword_op, base_reg, offset, |
c819be5b JW |
7441 | reg_names[regno]); |
7442 | ||
86735b02 | 7443 | offset += 2 * UNITS_PER_WORD; |
c819be5b JW |
7444 | regno++; |
7445 | } | |
7446 | else | |
7447 | { | |
7448 | if (word_op[0] == 's') | |
c53aa195 | 7449 | { |
e0d80184 | 7450 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
7451 | word_op, reg_names[regno], |
7452 | base_reg, offset); | |
0021b564 | 7453 | if (dwarf2out_do_frame ()) |
c53aa195 | 7454 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 7455 | } |
c819be5b | 7456 | else |
e0d80184 | 7457 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 7458 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 7459 | |
86735b02 | 7460 | offset += UNITS_PER_WORD; |
c819be5b JW |
7461 | } |
7462 | } | |
7463 | } | |
7464 | } | |
7465 | ||
7466 | if (fmask) | |
7467 | { | |
7468 | for (regno = 32; regno <= 63; regno++) | |
7469 | { | |
7470 | if ((fmask & (1L << (regno - 32))) != 0) | |
7471 | { | |
7472 | if (word_op[0] == 's') | |
c53aa195 | 7473 | { |
e0d80184 | 7474 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
7475 | word_op, reg_names[regno], |
7476 | base_reg, offset); | |
0021b564 | 7477 | if (dwarf2out_do_frame ()) |
c53aa195 | 7478 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 7479 | } |
c819be5b | 7480 | else |
e0d80184 | 7481 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 7482 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 7483 | |
86735b02 | 7484 | offset += UNITS_PER_WORD; |
c819be5b JW |
7485 | } |
7486 | } | |
7487 | } | |
7488 | } | |
7489 | \f | |
7490 | /* Set up the stack and frame (if desired) for the function. */ | |
7491 | ||
08c148a8 | 7492 | static void |
fc27d102 | 7493 | sparc_flat_function_prologue (FILE *file, HOST_WIDE_INT size) |
c819be5b | 7494 | { |
99f44eba | 7495 | const char *sp_str = reg_names[STACK_POINTER_REGNUM]; |
86735b02 | 7496 | unsigned long gmask = current_frame_info.gmask; |
a07c1915 | 7497 | |
1cb36a98 RH |
7498 | sparc_output_scratch_registers (file); |
7499 | ||
c6aa9ce1 | 7500 | /* This is only for the human reader. */ |
bf62bbf1 | 7501 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
5e9defae | 7502 | fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n", |
bf62bbf1 | 7503 | ASM_COMMENT_START, |
86735b02 DE |
7504 | current_frame_info.var_size, |
7505 | current_frame_info.gp_reg_size / 4, | |
9f8b85b8 | 7506 | current_frame_info.fp_reg_size / 4, |
86735b02 DE |
7507 | current_function_outgoing_args_size, |
7508 | current_frame_info.extra_size); | |
c819be5b JW |
7509 | |
7510 | size = SPARC_STACK_ALIGN (size); | |
86735b02 DE |
7511 | size = (! current_frame_info.initialized |
7512 | ? sparc_flat_compute_frame_size (size) | |
7513 | : current_frame_info.total_size); | |
c819be5b | 7514 | |
86735b02 DE |
7515 | /* These cases shouldn't happen. Catch them now. */ |
7516 | if (size == 0 && (gmask || current_frame_info.fmask)) | |
7517 | abort (); | |
c819be5b | 7518 | |
86735b02 DE |
7519 | /* Allocate our stack frame by decrementing %sp. |
7520 | At present, the only algorithm gdb can use to determine if this is a | |
7521 | flat frame is if we always set %i7 if we set %sp. This can be optimized | |
7522 | in the future by putting in some sort of debugging information that says | |
7523 | this is a `flat' function. However, there is still the case of debugging | |
7524 | code without such debugging information (including cases where most fns | |
7525 | have such info, but there is one that doesn't). So, always do this now | |
7526 | so we don't get a lot of code out there that gdb can't handle. | |
7527 | If the frame pointer isn't needn't then that's ok - gdb won't be able to | |
7528 | distinguish us from a non-flat function but there won't (and shouldn't) | |
7529 | be any differences anyway. The return pc is saved (if necessary) right | |
7530 | after %i7 so gdb won't have to look too far to find it. */ | |
7531 | if (size > 0) | |
c819be5b | 7532 | { |
86735b02 | 7533 | unsigned int reg_offset = current_frame_info.reg_offset; |
563c12b0 | 7534 | const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; |
83182544 | 7535 | static const char *const t1_str = "%g1"; |
86735b02 DE |
7536 | |
7537 | /* Things get a little tricky if local variables take up more than ~4096 | |
7538 | bytes and outgoing arguments take up more than ~4096 bytes. When that | |
7539 | happens, the register save area can't be accessed from either end of | |
7540 | the frame. Handle this by decrementing %sp to the start of the gp | |
7541 | register save area, save the regs, update %i7, and then set %sp to its | |
7542 | final value. Given that we only have one scratch register to play | |
7543 | with it is the cheapest solution, and it helps gdb out as it won't | |
7544 | slow down recognition of flat functions. | |
7545 | Don't change the order of insns emitted here without checking with | |
7546 | the gdb folk first. */ | |
7547 | ||
ddd5a7c1 | 7548 | /* Is the entire register save area offsettable from %sp? */ |
fbd039b2 | 7549 | if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) |
86735b02 DE |
7550 | { |
7551 | if (size <= 4096) | |
7552 | { | |
e0d80184 | 7553 | fprintf (file, "\tadd\t%s, %d, %s\n", |
0d587737 | 7554 | sp_str, (int) -size, sp_str); |
563c12b0 | 7555 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7556 | { |
e0d80184 | 7557 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 7558 | fp_str, sp_str, reg_offset); |
e0d80184 | 7559 | fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n", |
0d587737 | 7560 | sp_str, (int) -size, fp_str, ASM_COMMENT_START); |
86735b02 DE |
7561 | reg_offset += 4; |
7562 | } | |
7563 | } | |
7564 | else | |
7565 | { | |
4a0a75dd KG |
7566 | fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC |
7567 | ", %s\n\tsub\t%s, %s, %s\n", | |
7568 | size, t1_str, sp_str, t1_str, sp_str); | |
563c12b0 | 7569 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7570 | { |
e0d80184 | 7571 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 7572 | fp_str, sp_str, reg_offset); |
e0d80184 | 7573 | fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
bf62bbf1 | 7574 | sp_str, t1_str, fp_str, ASM_COMMENT_START); |
86735b02 DE |
7575 | reg_offset += 4; |
7576 | } | |
7577 | } | |
0021b564 | 7578 | if (dwarf2out_do_frame ()) |
c53aa195 | 7579 | { |
96987e96 | 7580 | char *l = dwarf2out_cfi_label (); |
563c12b0 | 7581 | if (gmask & HARD_FRAME_POINTER_MASK) |
c53aa195 | 7582 | { |
563c12b0 | 7583 | dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, |
c53aa195 | 7584 | reg_offset - 4 - size); |
563c12b0 | 7585 | dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); |
c53aa195 JM |
7586 | } |
7587 | else | |
7588 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size); | |
7589 | } | |
86735b02 DE |
7590 | if (gmask & RETURN_ADDR_MASK) |
7591 | { | |
e0d80184 | 7592 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 7593 | reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); |
0021b564 | 7594 | if (dwarf2out_do_frame ()) |
c53aa195 | 7595 | dwarf2out_return_save ("", reg_offset - size); |
86735b02 DE |
7596 | reg_offset += 4; |
7597 | } | |
7598 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
563c12b0 | 7599 | gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), |
86735b02 | 7600 | current_frame_info.fmask, |
84e884e9 | 7601 | "st", "std", -size); |
86735b02 | 7602 | } |
c819be5b | 7603 | else |
86735b02 DE |
7604 | { |
7605 | /* Subtract %sp in two steps, but make sure there is always a | |
7606 | 64 byte register save area, and %sp is properly aligned. */ | |
7607 | /* Amount to decrement %sp by, the first time. */ | |
08c148a8 | 7608 | unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16; |
86735b02 | 7609 | /* Offset to register save area from %sp. */ |
08c148a8 | 7610 | unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset); |
86735b02 DE |
7611 | |
7612 | if (size1 <= 4096) | |
7613 | { | |
e0d80184 | 7614 | fprintf (file, "\tadd\t%s, %d, %s\n", |
0d587737 | 7615 | sp_str, (int) -size1, sp_str); |
563c12b0 | 7616 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7617 | { |
e0d80184 | 7618 | fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n", |
0d587737 KG |
7619 | fp_str, sp_str, (int) offset, sp_str, (int) -size1, |
7620 | fp_str, ASM_COMMENT_START); | |
86735b02 DE |
7621 | offset += 4; |
7622 | } | |
7623 | } | |
7624 | else | |
7625 | { | |
4a0a75dd KG |
7626 | fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC |
7627 | ", %s\n\tsub\t%s, %s, %s\n", | |
7628 | size1, t1_str, sp_str, t1_str, sp_str); | |
563c12b0 | 7629 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7630 | { |
e0d80184 | 7631 | fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
0d587737 KG |
7632 | fp_str, sp_str, (int) offset, sp_str, t1_str, |
7633 | fp_str, ASM_COMMENT_START); | |
86735b02 DE |
7634 | offset += 4; |
7635 | } | |
7636 | } | |
0021b564 | 7637 | if (dwarf2out_do_frame ()) |
c53aa195 | 7638 | { |
96987e96 | 7639 | char *l = dwarf2out_cfi_label (); |
563c12b0 | 7640 | if (gmask & HARD_FRAME_POINTER_MASK) |
c53aa195 | 7641 | { |
563c12b0 | 7642 | dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, |
c53aa195 | 7643 | offset - 4 - size1); |
563c12b0 | 7644 | dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); |
c53aa195 JM |
7645 | } |
7646 | else | |
7647 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1); | |
7648 | } | |
86735b02 DE |
7649 | if (gmask & RETURN_ADDR_MASK) |
7650 | { | |
e0d80184 | 7651 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
0d587737 | 7652 | reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset); |
0021b564 | 7653 | if (dwarf2out_do_frame ()) |
c53aa195 JM |
7654 | /* offset - size1 == reg_offset - size |
7655 | if reg_offset were updated above like offset. */ | |
7656 | dwarf2out_return_save ("", offset - size1); | |
86735b02 DE |
7657 | offset += 4; |
7658 | } | |
7659 | sparc_flat_save_restore (file, sp_str, offset, | |
563c12b0 | 7660 | gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), |
86735b02 | 7661 | current_frame_info.fmask, |
84e884e9 | 7662 | "st", "std", -size1); |
4a0a75dd KG |
7663 | fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC |
7664 | ", %s\n\tsub\t%s, %s, %s\n", | |
7665 | size - size1, t1_str, sp_str, t1_str, sp_str); | |
0021b564 | 7666 | if (dwarf2out_do_frame ()) |
563c12b0 | 7667 | if (! (gmask & HARD_FRAME_POINTER_MASK)) |
c53aa195 | 7668 | dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size); |
86735b02 | 7669 | } |
c819be5b | 7670 | } |
c6aa9ce1 | 7671 | |
bf62bbf1 | 7672 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
c819be5b JW |
7673 | } |
7674 | \f | |
7675 | /* Do any necessary cleanup after a function to restore stack, frame, | |
80ffc95e | 7676 | and regs. */ |
c819be5b | 7677 | |
08c148a8 | 7678 | static void |
fc27d102 | 7679 | sparc_flat_function_epilogue (FILE *file, HOST_WIDE_INT size) |
c819be5b | 7680 | { |
c819be5b JW |
7681 | rtx epilogue_delay = current_function_epilogue_delay_list; |
7682 | int noepilogue = FALSE; | |
c819be5b | 7683 | |
c6aa9ce1 | 7684 | /* This is only for the human reader. */ |
bf62bbf1 | 7685 | fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START); |
c6aa9ce1 | 7686 | |
c819be5b JW |
7687 | /* The epilogue does not depend on any registers, but the stack |
7688 | registers, so we assume that if we have 1 pending nop, it can be | |
7689 | ignored, and 2 it must be filled (2 nops occur for integer | |
7690 | multiply and divide). */ | |
7691 | ||
7692 | size = SPARC_STACK_ALIGN (size); | |
86735b02 | 7693 | size = (!current_frame_info.initialized |
c6aa9ce1 | 7694 | ? sparc_flat_compute_frame_size (size) |
c819be5b JW |
7695 | : current_frame_info.total_size); |
7696 | ||
86735b02 | 7697 | if (size == 0 && epilogue_delay == 0) |
c819be5b JW |
7698 | { |
7699 | rtx insn = get_last_insn (); | |
7700 | ||
7701 | /* If the last insn was a BARRIER, we don't have to write any code | |
7702 | because a jump (aka return) was put there. */ | |
7703 | if (GET_CODE (insn) == NOTE) | |
7704 | insn = prev_nonnote_insn (insn); | |
7705 | if (insn && GET_CODE (insn) == BARRIER) | |
7706 | noepilogue = TRUE; | |
7707 | } | |
7708 | ||
7709 | if (!noepilogue) | |
7710 | { | |
08c148a8 NB |
7711 | unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset; |
7712 | unsigned HOST_WIDE_INT size1; | |
27c38fbe | 7713 | const char *const sp_str = reg_names[STACK_POINTER_REGNUM]; |
563c12b0 | 7714 | const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; |
83182544 | 7715 | static const char *const t1_str = "%g1"; |
86735b02 | 7716 | |
c819be5b JW |
7717 | /* In the reload sequence, we don't need to fill the load delay |
7718 | slots for most of the loads, also see if we can fill the final | |
7719 | delay slot if not otherwise filled by the reload sequence. */ | |
7720 | ||
86735b02 | 7721 | if (size > 4095) |
4a0a75dd KG |
7722 | fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC ", %s\n", |
7723 | size, t1_str); | |
c819be5b JW |
7724 | |
7725 | if (frame_pointer_needed) | |
7726 | { | |
86735b02 | 7727 | if (size > 4095) |
e0d80184 | 7728 | fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n", |
bf62bbf1 | 7729 | fp_str, t1_str, sp_str, ASM_COMMENT_START); |
c819be5b | 7730 | else |
e0d80184 | 7731 | fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n", |
0d587737 | 7732 | fp_str, (int) size, sp_str, ASM_COMMENT_START); |
c819be5b JW |
7733 | } |
7734 | ||
ddd5a7c1 | 7735 | /* Is the entire register save area offsettable from %sp? */ |
fbd039b2 | 7736 | if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) |
86735b02 DE |
7737 | { |
7738 | size1 = 0; | |
7739 | } | |
7740 | else | |
7741 | { | |
7742 | /* Restore %sp in two steps, but make sure there is always a | |
7743 | 64 byte register save area, and %sp is properly aligned. */ | |
7744 | /* Amount to increment %sp by, the first time. */ | |
7745 | size1 = ((reg_offset - 64 - 16) + 15) & -16; | |
7746 | /* Offset to register save area from %sp. */ | |
7747 | reg_offset = size1 - reg_offset; | |
7748 | ||
4a0a75dd KG |
7749 | fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC |
7750 | ", %s\n\tadd\t%s, %s, %s\n", | |
7751 | size1, t1_str, sp_str, t1_str, sp_str); | |
86735b02 DE |
7752 | } |
7753 | ||
7754 | /* We must restore the frame pointer and return address reg first | |
7755 | because they are treated specially by the prologue output code. */ | |
563c12b0 | 7756 | if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7757 | { |
e0d80184 | 7758 | fprintf (file, "\tld\t[%s+%d], %s\n", |
0d587737 | 7759 | sp_str, (int) reg_offset, fp_str); |
86735b02 DE |
7760 | reg_offset += 4; |
7761 | } | |
7762 | if (current_frame_info.gmask & RETURN_ADDR_MASK) | |
7763 | { | |
e0d80184 | 7764 | fprintf (file, "\tld\t[%s+%d], %s\n", |
0d587737 | 7765 | sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]); |
86735b02 DE |
7766 | reg_offset += 4; |
7767 | } | |
7768 | ||
7769 | /* Restore any remaining saved registers. */ | |
7770 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
563c12b0 | 7771 | current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), |
86735b02 | 7772 | current_frame_info.fmask, |
c53aa195 | 7773 | "ld", "ldd", 0); |
86735b02 DE |
7774 | |
7775 | /* If we had to increment %sp in two steps, record it so the second | |
7776 | restoration in the epilogue finishes up. */ | |
7777 | if (size1 > 0) | |
7778 | { | |
7779 | size -= size1; | |
7780 | if (size > 4095) | |
4a0a75dd KG |
7781 | fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC ", %s\n", |
7782 | size, t1_str); | |
86735b02 | 7783 | } |
c819be5b | 7784 | |
c819be5b | 7785 | if (current_function_returns_struct) |
e0d80184 | 7786 | fprintf (file, "\tjmp\t%%o7+12\n"); |
c819be5b JW |
7787 | else |
7788 | fprintf (file, "\tretl\n"); | |
7789 | ||
7790 | /* If the only register saved is the return address, we need a | |
7791 | nop, unless we have an instruction to put into it. Otherwise | |
7792 | we don't since reloading multiple registers doesn't reference | |
7793 | the register being loaded. */ | |
7794 | ||
7795 | if (epilogue_delay) | |
7796 | { | |
86735b02 | 7797 | if (size) |
c819be5b JW |
7798 | abort (); |
7799 | final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); | |
7800 | } | |
7801 | ||
86735b02 | 7802 | else if (size > 4095) |
e0d80184 | 7803 | fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); |
c819be5b | 7804 | |
86735b02 | 7805 | else if (size > 0) |
0d587737 | 7806 | fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str); |
c819be5b JW |
7807 | |
7808 | else | |
7809 | fprintf (file, "\tnop\n"); | |
7810 | } | |
7811 | ||
7812 | /* Reset state info for each function. */ | |
7813 | current_frame_info = zero_frame_info; | |
e0d80184 DM |
7814 | |
7815 | sparc_output_deferred_case_vectors (); | |
c819be5b JW |
7816 | } |
7817 | \f | |
7818 | /* Define the number of delay slots needed for the function epilogue. | |
7819 | ||
7820 | On the sparc, we need a slot if either no stack has been allocated, | |
7821 | or the only register saved is the return register. */ | |
7822 | ||
7823 | int | |
fc27d102 | 7824 | sparc_flat_epilogue_delay_slots (void) |
c819be5b JW |
7825 | { |
7826 | if (!current_frame_info.initialized) | |
c6aa9ce1 | 7827 | (void) sparc_flat_compute_frame_size (get_frame_size ()); |
c819be5b JW |
7828 | |
7829 | if (current_frame_info.total_size == 0) | |
7830 | return 1; | |
7831 | ||
c819be5b JW |
7832 | return 0; |
7833 | } | |
7834 | ||
51f26c45 | 7835 | /* Return true if TRIAL is a valid insn for the epilogue delay slot. |
c819be5b JW |
7836 | Any single length instruction which doesn't reference the stack or frame |
7837 | pointer is OK. */ | |
7838 | ||
7839 | int | |
fc27d102 | 7840 | sparc_flat_eligible_for_epilogue_delay (rtx trial, int slot ATTRIBUTE_UNUSED) |
c819be5b | 7841 | { |
c4ce6853 DE |
7842 | rtx pat = PATTERN (trial); |
7843 | ||
7844 | if (get_attr_length (trial) != 1) | |
7845 | return 0; | |
7846 | ||
c4ce6853 DE |
7847 | if (! reg_mentioned_p (stack_pointer_rtx, pat) |
7848 | && ! reg_mentioned_p (frame_pointer_rtx, pat)) | |
c819be5b | 7849 | return 1; |
c4ce6853 | 7850 | |
c819be5b JW |
7851 | return 0; |
7852 | } | |
dbb54862 JW |
7853 | \f |
7854 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
7855 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
7856 | ||
8947065c | 7857 | static int |
fc27d102 | 7858 | supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
dbb54862 JW |
7859 | { |
7860 | enum attr_type insn_type; | |
7861 | ||
7862 | if (! recog_memoized (insn)) | |
7863 | return 0; | |
7864 | ||
7865 | insn_type = get_attr_type (insn); | |
7866 | ||
7867 | if (REG_NOTE_KIND (link) == 0) | |
7868 | { | |
7869 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7870 | cycles later. */ | |
7871 | ||
7872 | /* if a load, then the dependence must be on the memory address; | |
3bc8b61e DM |
7873 | add an extra "cycle". Note that the cost could be two cycles |
7874 | if the reg was written late in an instruction group; we ca not tell | |
dbb54862 JW |
7875 | here. */ |
7876 | if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) | |
7877 | return cost + 3; | |
7878 | ||
7879 | /* Get the delay only if the address of the store is the dependence. */ | |
7880 | if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) | |
7881 | { | |
7882 | rtx pat = PATTERN(insn); | |
7883 | rtx dep_pat = PATTERN (dep_insn); | |
7884 | ||
7885 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
3bc8b61e | 7886 | return cost; /* This should not happen! */ |
dbb54862 JW |
7887 | |
7888 | /* The dependency between the two instructions was on the data that | |
7889 | is being stored. Assume that this implies that the address of the | |
7890 | store is not dependent. */ | |
7891 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
7892 | return cost; | |
7893 | ||
7894 | return cost + 3; /* An approximation. */ | |
7895 | } | |
7896 | ||
7897 | /* A shift instruction cannot receive its data from an instruction | |
7898 | in the same cycle; add a one cycle penalty. */ | |
7899 | if (insn_type == TYPE_SHIFT) | |
7900 | return cost + 3; /* Split before cascade into shift. */ | |
7901 | } | |
7902 | else | |
7903 | { | |
7904 | /* Anti- or output- dependency; DEP_INSN reads/writes a register that | |
7905 | INSN writes some cycles later. */ | |
7906 | ||
7907 | /* These are only significant for the fpu unit; writing a fp reg before | |
7908 | the fpu has finished with it stalls the processor. */ | |
7909 | ||
7910 | /* Reusing an integer register causes no problems. */ | |
7911 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
7912 | return 0; | |
7913 | } | |
7914 | ||
7915 | return cost; | |
7916 | } | |
bfd6bc60 | 7917 | |
8947065c | 7918 | static int |
fc27d102 | 7919 | hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
8947065c RH |
7920 | { |
7921 | enum attr_type insn_type, dep_type; | |
7922 | rtx pat = PATTERN(insn); | |
7923 | rtx dep_pat = PATTERN (dep_insn); | |
7924 | ||
7925 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) | |
7926 | return cost; | |
7927 | ||
7928 | insn_type = get_attr_type (insn); | |
7929 | dep_type = get_attr_type (dep_insn); | |
7930 | ||
7931 | switch (REG_NOTE_KIND (link)) | |
7932 | { | |
7933 | case 0: | |
7934 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7935 | cycles later. */ | |
7936 | ||
7937 | switch (insn_type) | |
7938 | { | |
7939 | case TYPE_STORE: | |
7940 | case TYPE_FPSTORE: | |
80ffc95e | 7941 | /* Get the delay iff the address of the store is the dependence. */ |
8947065c RH |
7942 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) |
7943 | return cost; | |
7944 | ||
7945 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
7946 | return cost; | |
7947 | return cost + 3; | |
7948 | ||
7949 | case TYPE_LOAD: | |
7950 | case TYPE_SLOAD: | |
7951 | case TYPE_FPLOAD: | |
7952 | /* If a load, then the dependence must be on the memory address. If | |
7953 | the addresses aren't equal, then it might be a false dependency */ | |
7954 | if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) | |
7955 | { | |
7956 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET | |
7957 | || GET_CODE (SET_DEST (dep_pat)) != MEM | |
7958 | || GET_CODE (SET_SRC (pat)) != MEM | |
7959 | || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), | |
7960 | XEXP (SET_SRC (pat), 0))) | |
7961 | return cost + 2; | |
7962 | ||
7963 | return cost + 8; | |
7964 | } | |
7965 | break; | |
7966 | ||
7967 | case TYPE_BRANCH: | |
7968 | /* Compare to branch latency is 0. There is no benefit from | |
7969 | separating compare and branch. */ | |
7970 | if (dep_type == TYPE_COMPARE) | |
7971 | return 0; | |
7972 | /* Floating point compare to branch latency is less than | |
7973 | compare to conditional move. */ | |
7974 | if (dep_type == TYPE_FPCMP) | |
7975 | return cost - 1; | |
7976 | break; | |
3bb5de61 KG |
7977 | default: |
7978 | break; | |
8947065c RH |
7979 | } |
7980 | break; | |
7981 | ||
7982 | case REG_DEP_ANTI: | |
80ffc95e | 7983 | /* Anti-dependencies only penalize the fpu unit. */ |
8947065c RH |
7984 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) |
7985 | return 0; | |
7986 | break; | |
7987 | ||
7988 | default: | |
7989 | break; | |
7990 | } | |
7991 | ||
7992 | return cost; | |
7993 | } | |
7994 | ||
c237e94a | 7995 | static int |
fc27d102 | 7996 | sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost) |
8947065c RH |
7997 | { |
7998 | switch (sparc_cpu) | |
7999 | { | |
8000 | case PROCESSOR_SUPERSPARC: | |
8001 | cost = supersparc_adjust_cost (insn, link, dep, cost); | |
8002 | break; | |
8003 | case PROCESSOR_HYPERSPARC: | |
8004 | case PROCESSOR_SPARCLITE86X: | |
8005 | cost = hypersparc_adjust_cost (insn, link, dep, cost); | |
8006 | break; | |
8947065c RH |
8007 | default: |
8008 | break; | |
8009 | } | |
8010 | return cost; | |
8011 | } | |
8012 | ||
fae15c93 | 8013 | static void |
fc27d102 KG |
8014 | sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED, |
8015 | int sched_verbose ATTRIBUTE_UNUSED, | |
8016 | int max_ready ATTRIBUTE_UNUSED) | |
3bc8b61e | 8017 | { |
3bc8b61e | 8018 | } |
fae15c93 | 8019 | |
3bc8b61e | 8020 | static int |
fc27d102 | 8021 | sparc_use_dfa_pipeline_interface (void) |
3bc8b61e | 8022 | { |
fae15c93 VM |
8023 | if ((1 << sparc_cpu) & |
8024 | ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) | | |
8025 | (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | | |
8026 | (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) | | |
8027 | (1 << PROCESSOR_ULTRASPARC3))) | |
8028 | return 1; | |
3bc8b61e DM |
8029 | return 0; |
8030 | } | |
8031 | ||
fae15c93 | 8032 | static int |
fc27d102 | 8033 | sparc_use_sched_lookahead (void) |
fae15c93 VM |
8034 | { |
8035 | if (sparc_cpu == PROCESSOR_ULTRASPARC | |
8036 | || sparc_cpu == PROCESSOR_ULTRASPARC3) | |
8037 | return 4; | |
8038 | if ((1 << sparc_cpu) & | |
8039 | ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | | |
8040 | (1 << PROCESSOR_SPARCLITE86X))) | |
8041 | return 3; | |
3bc8b61e DM |
8042 | return 0; |
8043 | } | |
8044 | ||
fae15c93 | 8045 | static int |
fc27d102 | 8046 | sparc_issue_rate (void) |
bfd6bc60 JC |
8047 | { |
8048 | switch (sparc_cpu) | |
8049 | { | |
fae15c93 VM |
8050 | default: |
8051 | return 1; | |
8052 | case PROCESSOR_V9: | |
284d86e9 | 8053 | /* Assume V9 processors are capable of at least dual-issue. */ |
bfd6bc60 | 8054 | return 2; |
fae15c93 VM |
8055 | case PROCESSOR_SUPERSPARC: |
8056 | return 3; | |
393049a9 RH |
8057 | case PROCESSOR_HYPERSPARC: |
8058 | case PROCESSOR_SPARCLITE86X: | |
8059 | return 2; | |
fae15c93 VM |
8060 | case PROCESSOR_ULTRASPARC: |
8061 | case PROCESSOR_ULTRASPARC3: | |
8062 | return 4; | |
bfd6bc60 JC |
8063 | } |
8064 | } | |
284d86e9 JC |
8065 | |
8066 | static int | |
fc27d102 | 8067 | set_extends (rtx insn) |
284d86e9 JC |
8068 | { |
8069 | register rtx pat = PATTERN (insn); | |
8070 | ||
8071 | switch (GET_CODE (SET_SRC (pat))) | |
8072 | { | |
80ffc95e | 8073 | /* Load and some shift instructions zero extend. */ |
284d86e9 JC |
8074 | case MEM: |
8075 | case ZERO_EXTEND: | |
8076 | /* sethi clears the high bits */ | |
8077 | case HIGH: | |
8078 | /* LO_SUM is used with sethi. sethi cleared the high | |
8079 | bits and the values used with lo_sum are positive */ | |
8080 | case LO_SUM: | |
284d86e9 JC |
8081 | /* Store flag stores 0 or 1 */ |
8082 | case LT: case LTU: | |
8083 | case GT: case GTU: | |
8084 | case LE: case LEU: | |
8085 | case GE: case GEU: | |
8086 | case EQ: | |
8087 | case NE: | |
8088 | return 1; | |
8089 | case AND: | |
8090 | { | |
4df1190a | 8091 | rtx op0 = XEXP (SET_SRC (pat), 0); |
284d86e9 JC |
8092 | rtx op1 = XEXP (SET_SRC (pat), 1); |
8093 | if (GET_CODE (op1) == CONST_INT) | |
8094 | return INTVAL (op1) >= 0; | |
4df1190a JJ |
8095 | if (GET_CODE (op0) != REG) |
8096 | return 0; | |
8097 | if (sparc_check_64 (op0, insn) == 1) | |
284d86e9 | 8098 | return 1; |
4df1190a JJ |
8099 | return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); |
8100 | } | |
8101 | case IOR: | |
8102 | case XOR: | |
8103 | { | |
8104 | rtx op0 = XEXP (SET_SRC (pat), 0); | |
8105 | rtx op1 = XEXP (SET_SRC (pat), 1); | |
8106 | if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) | |
8107 | return 0; | |
8108 | if (GET_CODE (op1) == CONST_INT) | |
8109 | return INTVAL (op1) >= 0; | |
8110 | return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); | |
284d86e9 | 8111 | } |
284d86e9 JC |
8112 | case LSHIFTRT: |
8113 | return GET_MODE (SET_SRC (pat)) == SImode; | |
80ffc95e | 8114 | /* Positive integers leave the high bits zero. */ |
284d86e9 | 8115 | case CONST_DOUBLE: |
4df1190a | 8116 | return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000); |
284d86e9 | 8117 | case CONST_INT: |
4df1190a | 8118 | return ! (INTVAL (SET_SRC (pat)) & 0x80000000); |
284d86e9 JC |
8119 | case ASHIFTRT: |
8120 | case SIGN_EXTEND: | |
8121 | return - (GET_MODE (SET_SRC (pat)) == SImode); | |
4df1190a JJ |
8122 | case REG: |
8123 | return sparc_check_64 (SET_SRC (pat), insn); | |
284d86e9 JC |
8124 | default: |
8125 | return 0; | |
8126 | } | |
8127 | } | |
8128 | ||
80ffc95e | 8129 | /* We _ought_ to have only one kind per function, but... */ |
e2500fed GK |
8130 | static GTY(()) rtx sparc_addr_diff_list; |
8131 | static GTY(()) rtx sparc_addr_list; | |
e0d80184 DM |
8132 | |
8133 | void | |
fc27d102 | 8134 | sparc_defer_case_vector (rtx lab, rtx vec, int diff) |
e0d80184 DM |
8135 | { |
8136 | vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); | |
8137 | if (diff) | |
8138 | sparc_addr_diff_list | |
8139 | = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); | |
8140 | else | |
8141 | sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); | |
8142 | } | |
8143 | ||
8144 | static void | |
fc27d102 | 8145 | sparc_output_addr_vec (rtx vec) |
e0d80184 DM |
8146 | { |
8147 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
8148 | int idx, vlen = XVECLEN (body, 0); | |
8149 | ||
d1accaa3 JJ |
8150 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
8151 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
8152 | #endif | |
8153 | ||
e0d80184 DM |
8154 | #ifdef ASM_OUTPUT_CASE_LABEL |
8155 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
8156 | NEXT_INSN (lab)); | |
8157 | #else | |
4977bab6 | 8158 | (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); |
e0d80184 DM |
8159 | #endif |
8160 | ||
8161 | for (idx = 0; idx < vlen; idx++) | |
8162 | { | |
8163 | ASM_OUTPUT_ADDR_VEC_ELT | |
8164 | (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); | |
8165 | } | |
d1accaa3 JJ |
8166 | |
8167 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
8168 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
8169 | #endif | |
e0d80184 DM |
8170 | } |
8171 | ||
8172 | static void | |
fc27d102 | 8173 | sparc_output_addr_diff_vec (rtx vec) |
e0d80184 DM |
8174 | { |
8175 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
8176 | rtx base = XEXP (XEXP (body, 0), 0); | |
8177 | int idx, vlen = XVECLEN (body, 1); | |
8178 | ||
d1accaa3 JJ |
8179 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
8180 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
8181 | #endif | |
8182 | ||
e0d80184 DM |
8183 | #ifdef ASM_OUTPUT_CASE_LABEL |
8184 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
8185 | NEXT_INSN (lab)); | |
8186 | #else | |
4977bab6 | 8187 | (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); |
e0d80184 DM |
8188 | #endif |
8189 | ||
8190 | for (idx = 0; idx < vlen; idx++) | |
8191 | { | |
8192 | ASM_OUTPUT_ADDR_DIFF_ELT | |
8193 | (asm_out_file, | |
8194 | body, | |
8195 | CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), | |
8196 | CODE_LABEL_NUMBER (base)); | |
8197 | } | |
d1accaa3 JJ |
8198 | |
8199 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
8200 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
8201 | #endif | |
e0d80184 DM |
8202 | } |
8203 | ||
8204 | static void | |
fc27d102 | 8205 | sparc_output_deferred_case_vectors (void) |
e0d80184 DM |
8206 | { |
8207 | rtx t; | |
d676da68 | 8208 | int align; |
e0d80184 | 8209 | |
f3b8847b DM |
8210 | if (sparc_addr_list == NULL_RTX |
8211 | && sparc_addr_diff_list == NULL_RTX) | |
8212 | return; | |
8213 | ||
e0d80184 DM |
8214 | /* Align to cache line in the function's code section. */ |
8215 | function_section (current_function_decl); | |
d676da68 DM |
8216 | |
8217 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
8218 | if (align > 0) | |
f3b8847b | 8219 | ASM_OUTPUT_ALIGN (asm_out_file, align); |
e0d80184 DM |
8220 | |
8221 | for (t = sparc_addr_list; t ; t = XEXP (t, 1)) | |
8222 | sparc_output_addr_vec (XEXP (t, 0)); | |
8223 | for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) | |
8224 | sparc_output_addr_diff_vec (XEXP (t, 0)); | |
8225 | ||
8226 | sparc_addr_list = sparc_addr_diff_list = NULL_RTX; | |
8227 | } | |
8228 | ||
284d86e9 JC |
8229 | /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are |
8230 | unknown. Return 1 if the high bits are zero, -1 if the register is | |
8231 | sign extended. */ | |
8232 | int | |
fc27d102 | 8233 | sparc_check_64 (rtx x, rtx insn) |
284d86e9 JC |
8234 | { |
8235 | /* If a register is set only once it is safe to ignore insns this | |
8236 | code does not know how to handle. The loop will either recognize | |
8237 | the single set and return the correct value or fail to recognize | |
8238 | it and return 0. */ | |
8239 | int set_once = 0; | |
4df1190a JJ |
8240 | rtx y = x; |
8241 | ||
8242 | if (GET_CODE (x) != REG) | |
8243 | abort (); | |
8244 | ||
8245 | if (GET_MODE (x) == DImode) | |
8246 | y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN); | |
284d86e9 | 8247 | |
4df1190a JJ |
8248 | if (flag_expensive_optimizations |
8249 | && REG_N_SETS (REGNO (y)) == 1) | |
284d86e9 JC |
8250 | set_once = 1; |
8251 | ||
8252 | if (insn == 0) | |
d6f4ec51 KG |
8253 | { |
8254 | if (set_once) | |
8255 | insn = get_last_insn_anywhere (); | |
8256 | else | |
8257 | return 0; | |
8258 | } | |
284d86e9 | 8259 | |
d6f4ec51 | 8260 | while ((insn = PREV_INSN (insn))) |
284d86e9 JC |
8261 | { |
8262 | switch (GET_CODE (insn)) | |
8263 | { | |
8264 | case JUMP_INSN: | |
8265 | case NOTE: | |
8266 | break; | |
8267 | case CODE_LABEL: | |
8268 | case CALL_INSN: | |
8269 | default: | |
8270 | if (! set_once) | |
8271 | return 0; | |
8272 | break; | |
8273 | case INSN: | |
8274 | { | |
8275 | rtx pat = PATTERN (insn); | |
8276 | if (GET_CODE (pat) != SET) | |
8277 | return 0; | |
8278 | if (rtx_equal_p (x, SET_DEST (pat))) | |
4df1190a JJ |
8279 | return set_extends (insn); |
8280 | if (y && rtx_equal_p (y, SET_DEST (pat))) | |
8281 | return set_extends (insn); | |
8282 | if (reg_overlap_mentioned_p (SET_DEST (pat), y)) | |
284d86e9 JC |
8283 | return 0; |
8284 | } | |
8285 | } | |
8286 | } | |
8287 | return 0; | |
8288 | } | |
8289 | ||
01d3224a EB |
8290 | /* Returns assembly code to perform a DImode shift using |
8291 | a 64-bit global or out register on SPARC-V8+. */ | |
284d86e9 | 8292 | char * |
fc27d102 | 8293 | sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode) |
284d86e9 JC |
8294 | { |
8295 | static char asm_code[60]; | |
8296 | ||
01d3224a EB |
8297 | /* The scratch register is only required when the destination |
8298 | register is not a 64-bit global or out register. */ | |
8299 | if (which_alternative != 2) | |
284d86e9 | 8300 | operands[3] = operands[0]; |
01d3224a | 8301 | |
1c8b4e29 EB |
8302 | /* We can only shift by constants <= 63. */ |
8303 | if (GET_CODE (operands[2]) == CONST_INT) | |
8304 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); | |
8305 | ||
c6b0465b JC |
8306 | if (GET_CODE (operands[1]) == CONST_INT) |
8307 | { | |
4df1190a | 8308 | output_asm_insn ("mov\t%1, %3", operands); |
c6b0465b JC |
8309 | } |
8310 | else | |
8311 | { | |
4df1190a | 8312 | output_asm_insn ("sllx\t%H1, 32, %3", operands); |
c6b0465b | 8313 | if (sparc_check_64 (operands[1], insn) <= 0) |
4df1190a JJ |
8314 | output_asm_insn ("srl\t%L1, 0, %L1", operands); |
8315 | output_asm_insn ("or\t%L1, %3, %3", operands); | |
c6b0465b | 8316 | } |
284d86e9 JC |
8317 | |
8318 | strcpy(asm_code, opcode); | |
01d3224a | 8319 | |
284d86e9 | 8320 | if (which_alternative != 2) |
4df1190a | 8321 | return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); |
284d86e9 | 8322 | else |
4df1190a | 8323 | return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"); |
284d86e9 | 8324 | } |
2be15d0f | 8325 | \f |
89a8b315 RH |
8326 | /* Output rtl to increment the profiler label LABELNO |
8327 | for profiling a function entry. */ | |
2be15d0f RH |
8328 | |
8329 | void | |
fc27d102 | 8330 | sparc_profile_hook (int labelno) |
2be15d0f RH |
8331 | { |
8332 | char buf[32]; | |
89a8b315 | 8333 | rtx lab, fun; |
2be15d0f | 8334 | |
89a8b315 RH |
8335 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
8336 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
8337 | fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION); | |
2be15d0f | 8338 | |
eb29ddb6 | 8339 | emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode); |
2be15d0f | 8340 | } |
89a8b315 | 8341 | \f |
ede75ee8 | 8342 | #ifdef OBJECT_FORMAT_ELF |
7c262518 | 8343 | static void |
fc27d102 | 8344 | sparc_elf_asm_named_section (const char *name, unsigned int flags) |
7c262518 | 8345 | { |
201556f0 JJ |
8346 | if (flags & SECTION_MERGE) |
8347 | { | |
8348 | /* entsize cannot be expressed in this section attributes | |
8349 | encoding style. */ | |
8350 | default_elf_asm_named_section (name, flags); | |
8351 | return; | |
8352 | } | |
8353 | ||
7c262518 RH |
8354 | fprintf (asm_out_file, "\t.section\t\"%s\"", name); |
8355 | ||
8356 | if (!(flags & SECTION_DEBUG)) | |
8357 | fputs (",#alloc", asm_out_file); | |
8358 | if (flags & SECTION_WRITE) | |
8359 | fputs (",#write", asm_out_file); | |
8360 | if (flags & SECTION_CODE) | |
8361 | fputs (",#execinstr", asm_out_file); | |
8362 | ||
8363 | /* ??? Handle SECTION_BSS. */ | |
8364 | ||
8365 | fputc ('\n', asm_out_file); | |
8366 | } | |
ede75ee8 | 8367 | #endif /* OBJECT_FORMAT_ELF */ |
f451b552 | 8368 | |
4977bab6 ZW |
8369 | /* We do not allow sibling calls if -mflat, nor |
8370 | we do not allow indirect calls to be optimized into sibling calls. | |
8371 | ||
8372 | Also, on sparc 32-bit we cannot emit a sibling call when the | |
8373 | current function returns a structure. This is because the "unimp | |
8374 | after call" convention would cause the callee to return to the | |
8375 | wrong place. The generic code already disallows cases where the | |
8376 | function being called returns a structure. | |
8377 | ||
8378 | It may seem strange how this last case could occur. Usually there | |
8379 | is code after the call which jumps to epilogue code which dumps the | |
8380 | return value into the struct return area. That ought to invalidate | |
8381 | the sibling call right? Well, in the c++ case we can end up passing | |
8382 | the pointer to the struct return area to a constructor (which returns | |
8383 | void) and then nothing else happens. Such a sibling call would look | |
8384 | valid without the added check here. */ | |
8385 | static bool | |
fc27d102 | 8386 | sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
4977bab6 ZW |
8387 | { |
8388 | return (decl | |
8389 | && ! TARGET_FLAT | |
8390 | && (TARGET_ARCH64 || ! current_function_returns_struct)); | |
8391 | } | |
c15c90bb ZW |
8392 | \f |
8393 | /* libfunc renaming. */ | |
8394 | #include "config/gofast.h" | |
8395 | ||
8396 | static void | |
8397 | sparc_init_libfuncs (void) | |
8398 | { | |
8399 | if (TARGET_ARCH32) | |
8400 | { | |
8401 | /* Use the subroutines that Sun's library provides for integer | |
8402 | multiply and divide. The `*' prevents an underscore from | |
8403 | being prepended by the compiler. .umul is a little faster | |
8404 | than .mul. */ | |
8405 | set_optab_libfunc (smul_optab, SImode, "*.umul"); | |
8406 | set_optab_libfunc (sdiv_optab, SImode, "*.div"); | |
8407 | set_optab_libfunc (udiv_optab, SImode, "*.udiv"); | |
8408 | set_optab_libfunc (smod_optab, SImode, "*.rem"); | |
8409 | set_optab_libfunc (umod_optab, SImode, "*.urem"); | |
8410 | ||
8411 | /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */ | |
8412 | set_optab_libfunc (add_optab, TFmode, "_Q_add"); | |
8413 | set_optab_libfunc (sub_optab, TFmode, "_Q_sub"); | |
8414 | set_optab_libfunc (neg_optab, TFmode, "_Q_neg"); | |
8415 | set_optab_libfunc (smul_optab, TFmode, "_Q_mul"); | |
8416 | set_optab_libfunc (sdiv_optab, TFmode, "_Q_div"); | |
8417 | ||
8418 | /* We can define the TFmode sqrt optab only if TARGET_FPU. This | |
8419 | is because with soft-float, the SFmode and DFmode sqrt | |
8420 | instructions will be absent, and the compiler will notice and | |
8421 | try to use the TFmode sqrt instruction for calls to the | |
8422 | builtin function sqrt, but this fails. */ | |
8423 | if (TARGET_FPU) | |
8424 | set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt"); | |
8425 | ||
c9034561 ZW |
8426 | set_optab_libfunc (eq_optab, TFmode, "_Q_feq"); |
8427 | set_optab_libfunc (ne_optab, TFmode, "_Q_fne"); | |
8428 | set_optab_libfunc (gt_optab, TFmode, "_Q_fgt"); | |
8429 | set_optab_libfunc (ge_optab, TFmode, "_Q_fge"); | |
8430 | set_optab_libfunc (lt_optab, TFmode, "_Q_flt"); | |
8431 | set_optab_libfunc (le_optab, TFmode, "_Q_fle"); | |
c15c90bb | 8432 | |
85363ca0 ZW |
8433 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq"); |
8434 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq"); | |
8435 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos"); | |
8436 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod"); | |
8437 | ||
8438 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi"); | |
8439 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou"); | |
8440 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq"); | |
c15c90bb ZW |
8441 | |
8442 | if (SUN_CONVERSION_LIBFUNCS) | |
8443 | { | |
85363ca0 ZW |
8444 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); |
8445 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); | |
8446 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); | |
8447 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); | |
c15c90bb ZW |
8448 | } |
8449 | } | |
8450 | if (TARGET_ARCH64) | |
8451 | { | |
8452 | /* In the SPARC 64bit ABI, SImode multiply and divide functions | |
8453 | do not exist in the library. Make sure the compiler does not | |
8454 | emit calls to them by accident. (It should always use the | |
8455 | hardware instructions.) */ | |
8456 | set_optab_libfunc (smul_optab, SImode, 0); | |
8457 | set_optab_libfunc (sdiv_optab, SImode, 0); | |
8458 | set_optab_libfunc (udiv_optab, SImode, 0); | |
8459 | set_optab_libfunc (smod_optab, SImode, 0); | |
8460 | set_optab_libfunc (umod_optab, SImode, 0); | |
8461 | ||
8462 | if (SUN_INTEGER_MULTIPLY_64) | |
8463 | { | |
8464 | set_optab_libfunc (smul_optab, DImode, "__mul64"); | |
8465 | set_optab_libfunc (sdiv_optab, DImode, "__div64"); | |
8466 | set_optab_libfunc (udiv_optab, DImode, "__udiv64"); | |
8467 | set_optab_libfunc (smod_optab, DImode, "__rem64"); | |
8468 | set_optab_libfunc (umod_optab, DImode, "__urem64"); | |
8469 | } | |
8470 | ||
8471 | if (SUN_CONVERSION_LIBFUNCS) | |
8472 | { | |
85363ca0 ZW |
8473 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol"); |
8474 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul"); | |
8475 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol"); | |
8476 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul"); | |
c15c90bb ZW |
8477 | } |
8478 | } | |
4977bab6 | 8479 | |
c15c90bb ZW |
8480 | gofast_maybe_init_libfuncs (); |
8481 | } | |
8482 | \f | |
ae46c4e0 RH |
8483 | /* ??? Similar to the standard section selection, but force reloc-y-ness |
8484 | if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to | |
8485 | pretending PIC always on), but that's what the old code did. */ | |
8486 | ||
8487 | static void | |
fc27d102 | 8488 | sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align) |
ae46c4e0 | 8489 | { |
508bc172 | 8490 | default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align); |
ae46c4e0 RH |
8491 | } |
8492 | ||
b64a1b53 RH |
8493 | /* Use text section for a constant unless we need more alignment than |
8494 | that offers. */ | |
8495 | ||
8496 | static void | |
fc27d102 KG |
8497 | sparc_aout_select_rtx_section (enum machine_mode mode, rtx x, |
8498 | unsigned HOST_WIDE_INT align) | |
b64a1b53 RH |
8499 | { |
8500 | if (align <= MAX_TEXT_ALIGN | |
8501 | && ! (flag_pic && (symbolic_operand (x, mode) | |
8502 | || SUNOS4_SHARED_LIBRARIES))) | |
8503 | readonly_data_section (); | |
8504 | else | |
8505 | data_section (); | |
8506 | } | |
8507 | ||
f451b552 | 8508 | int |
fc27d102 | 8509 | sparc_extra_constraint_check (rtx op, int c, int strict) |
f451b552 DM |
8510 | { |
8511 | int reload_ok_mem; | |
8512 | ||
8513 | if (TARGET_ARCH64 | |
8514 | && (c == 'T' || c == 'U')) | |
8515 | return 0; | |
8516 | ||
8517 | switch (c) | |
8518 | { | |
8519 | case 'Q': | |
8520 | return fp_sethi_p (op); | |
8521 | ||
8522 | case 'R': | |
8523 | return fp_mov_p (op); | |
8524 | ||
8525 | case 'S': | |
8526 | return fp_high_losum_p (op); | |
8527 | ||
8528 | case 'U': | |
8529 | if (! strict | |
8530 | || (GET_CODE (op) == REG | |
8531 | && (REGNO (op) < FIRST_PSEUDO_REGISTER | |
8532 | || reg_renumber[REGNO (op)] >= 0))) | |
8533 | return register_ok_for_ldd (op); | |
8534 | ||
8535 | return 0; | |
8536 | ||
8537 | case 'W': | |
8538 | case 'T': | |
8539 | break; | |
8540 | ||
8541 | default: | |
8542 | return 0; | |
8543 | } | |
8544 | ||
8545 | /* Our memory extra constraints have to emulate the | |
8546 | behavior of 'm' and 'o' in order for reload to work | |
8547 | correctly. */ | |
8548 | if (GET_CODE (op) == MEM) | |
8549 | { | |
8550 | reload_ok_mem = 0; | |
8551 | if ((TARGET_ARCH64 || mem_min_alignment (op, 8)) | |
8552 | && (! strict | |
8553 | || strict_memory_address_p (Pmode, XEXP (op, 0)))) | |
8554 | reload_ok_mem = 1; | |
8555 | } | |
8556 | else | |
8557 | { | |
8558 | reload_ok_mem = (reload_in_progress | |
8559 | && GET_CODE (op) == REG | |
8560 | && REGNO (op) >= FIRST_PSEUDO_REGISTER | |
8561 | && reg_renumber [REGNO (op)] < 0); | |
8562 | } | |
8563 | ||
8564 | return reload_ok_mem; | |
8565 | } | |
2ce04b6b | 8566 | |
214c6394 DM |
8567 | /* ??? This duplicates information provided to the compiler by the |
8568 | ??? scheduler description. Some day, teach genautomata to output | |
8569 | ??? the latencies and then CSE will just use that. */ | |
8570 | ||
3c50106f | 8571 | static bool |
fc27d102 | 8572 | sparc_rtx_costs (rtx x, int code, int outer_code, int *total) |
2ce04b6b DM |
8573 | { |
8574 | switch (code) | |
8575 | { | |
214c6394 DM |
8576 | case PLUS: case MINUS: case ABS: case NEG: |
8577 | case FLOAT: case UNSIGNED_FLOAT: | |
8578 | case FIX: case UNSIGNED_FIX: | |
8579 | case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
8580 | if (FLOAT_MODE_P (GET_MODE (x))) | |
8581 | { | |
8582 | switch (sparc_cpu) | |
8583 | { | |
8584 | case PROCESSOR_ULTRASPARC: | |
8585 | case PROCESSOR_ULTRASPARC3: | |
3c50106f RH |
8586 | *total = COSTS_N_INSNS (4); |
8587 | return true; | |
214c6394 DM |
8588 | |
8589 | case PROCESSOR_SUPERSPARC: | |
3c50106f RH |
8590 | *total = COSTS_N_INSNS (3); |
8591 | return true; | |
214c6394 DM |
8592 | |
8593 | case PROCESSOR_CYPRESS: | |
3c50106f RH |
8594 | *total = COSTS_N_INSNS (5); |
8595 | return true; | |
214c6394 DM |
8596 | |
8597 | case PROCESSOR_HYPERSPARC: | |
8598 | case PROCESSOR_SPARCLITE86X: | |
8599 | default: | |
3c50106f RH |
8600 | *total = COSTS_N_INSNS (1); |
8601 | return true; | |
214c6394 DM |
8602 | } |
8603 | } | |
8604 | ||
3c50106f RH |
8605 | *total = COSTS_N_INSNS (1); |
8606 | return true; | |
214c6394 DM |
8607 | |
8608 | case SQRT: | |
8609 | switch (sparc_cpu) | |
8610 | { | |
8611 | case PROCESSOR_ULTRASPARC: | |
8612 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8613 | *total = COSTS_N_INSNS (13); |
214c6394 | 8614 | else |
3c50106f RH |
8615 | *total = COSTS_N_INSNS (23); |
8616 | return true; | |
214c6394 DM |
8617 | |
8618 | case PROCESSOR_ULTRASPARC3: | |
8619 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8620 | *total = COSTS_N_INSNS (20); |
214c6394 | 8621 | else |
3c50106f RH |
8622 | *total = COSTS_N_INSNS (29); |
8623 | return true; | |
214c6394 DM |
8624 | |
8625 | case PROCESSOR_SUPERSPARC: | |
3c50106f RH |
8626 | *total = COSTS_N_INSNS (12); |
8627 | return true; | |
214c6394 DM |
8628 | |
8629 | case PROCESSOR_CYPRESS: | |
3c50106f RH |
8630 | *total = COSTS_N_INSNS (63); |
8631 | return true; | |
214c6394 DM |
8632 | |
8633 | case PROCESSOR_HYPERSPARC: | |
8634 | case PROCESSOR_SPARCLITE86X: | |
3c50106f RH |
8635 | *total = COSTS_N_INSNS (17); |
8636 | return true; | |
214c6394 DM |
8637 | |
8638 | default: | |
3c50106f RH |
8639 | *total = COSTS_N_INSNS (30); |
8640 | return true; | |
214c6394 DM |
8641 | } |
8642 | ||
8643 | case COMPARE: | |
8644 | if (FLOAT_MODE_P (GET_MODE (x))) | |
8645 | { | |
8646 | switch (sparc_cpu) | |
8647 | { | |
8648 | case PROCESSOR_ULTRASPARC: | |
8649 | case PROCESSOR_ULTRASPARC3: | |
3c50106f RH |
8650 | *total = COSTS_N_INSNS (1); |
8651 | return true; | |
214c6394 DM |
8652 | |
8653 | case PROCESSOR_SUPERSPARC: | |
3c50106f RH |
8654 | *total = COSTS_N_INSNS (3); |
8655 | return true; | |
214c6394 DM |
8656 | |
8657 | case PROCESSOR_CYPRESS: | |
3c50106f RH |
8658 | *total = COSTS_N_INSNS (5); |
8659 | return true; | |
214c6394 DM |
8660 | |
8661 | case PROCESSOR_HYPERSPARC: | |
8662 | case PROCESSOR_SPARCLITE86X: | |
8663 | default: | |
3c50106f RH |
8664 | *total = COSTS_N_INSNS (1); |
8665 | return true; | |
214c6394 DM |
8666 | } |
8667 | } | |
8668 | ||
8669 | /* ??? Maybe mark integer compares as zero cost on | |
8670 | ??? all UltraSPARC processors because the result | |
8671 | ??? can be bypassed to a branch in the same group. */ | |
8672 | ||
3c50106f RH |
8673 | *total = COSTS_N_INSNS (1); |
8674 | return true; | |
214c6394 | 8675 | |
2ce04b6b | 8676 | case MULT: |
214c6394 DM |
8677 | if (FLOAT_MODE_P (GET_MODE (x))) |
8678 | { | |
8679 | switch (sparc_cpu) | |
8680 | { | |
8681 | case PROCESSOR_ULTRASPARC: | |
8682 | case PROCESSOR_ULTRASPARC3: | |
3c50106f RH |
8683 | *total = COSTS_N_INSNS (4); |
8684 | return true; | |
214c6394 DM |
8685 | |
8686 | case PROCESSOR_SUPERSPARC: | |
3c50106f RH |
8687 | *total = COSTS_N_INSNS (3); |
8688 | return true; | |
214c6394 DM |
8689 | |
8690 | case PROCESSOR_CYPRESS: | |
3c50106f RH |
8691 | *total = COSTS_N_INSNS (7); |
8692 | return true; | |
214c6394 DM |
8693 | |
8694 | case PROCESSOR_HYPERSPARC: | |
8695 | case PROCESSOR_SPARCLITE86X: | |
3c50106f RH |
8696 | *total = COSTS_N_INSNS (1); |
8697 | return true; | |
214c6394 DM |
8698 | |
8699 | default: | |
3c50106f RH |
8700 | *total = COSTS_N_INSNS (5); |
8701 | return true; | |
214c6394 DM |
8702 | } |
8703 | } | |
8704 | ||
8705 | /* The latency is actually variable for Ultra-I/II | |
8706 | And if one of the inputs have a known constant | |
8707 | value, we could calculate this precisely. | |
8708 | ||
8709 | However, for that to be useful we would need to | |
8710 | add some machine description changes which would | |
8711 | make sure small constants ended up in rs1 of the | |
8712 | multiply instruction. This is because the multiply | |
8713 | latency is determined by the number of clear (or | |
8714 | set if the value is negative) bits starting from | |
8715 | the most significant bit of the first input. | |
8716 | ||
8717 | The algorithm for computing num_cycles of a multiply | |
8718 | on Ultra-I/II is: | |
8719 | ||
8720 | if (rs1 < 0) | |
8721 | highest_bit = highest_clear_bit(rs1); | |
8722 | else | |
8723 | highest_bit = highest_set_bit(rs1); | |
8724 | if (num_bits < 3) | |
8725 | highest_bit = 3; | |
8726 | num_cycles = 4 + ((highest_bit - 3) / 2); | |
8727 | ||
8728 | If we did that we would have to also consider register | |
8729 | allocation issues that would result from forcing such | |
8730 | a value into a register. | |
8731 | ||
8732 | There are other similar tricks we could play if we | |
8733 | knew, for example, that one input was an array index. | |
8734 | ||
8735 | Since we do not play any such tricks currently the | |
8736 | safest thing to do is report the worst case latency. */ | |
2ce04b6b | 8737 | if (sparc_cpu == PROCESSOR_ULTRASPARC) |
3c50106f RH |
8738 | { |
8739 | *total = (GET_MODE (x) == DImode | |
8740 | ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); | |
8741 | return true; | |
8742 | } | |
2ce04b6b | 8743 | |
214c6394 | 8744 | /* Multiply latency on Ultra-III, fortunately, is constant. */ |
2ce04b6b | 8745 | if (sparc_cpu == PROCESSOR_ULTRASPARC3) |
3c50106f RH |
8746 | { |
8747 | *total = COSTS_N_INSNS (6); | |
8748 | return true; | |
8749 | } | |
2ce04b6b | 8750 | |
214c6394 DM |
8751 | if (sparc_cpu == PROCESSOR_HYPERSPARC |
8752 | || sparc_cpu == PROCESSOR_SPARCLITE86X) | |
3c50106f RH |
8753 | { |
8754 | *total = COSTS_N_INSNS (17); | |
8755 | return true; | |
8756 | } | |
214c6394 | 8757 | |
3c50106f RH |
8758 | *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25)); |
8759 | return true; | |
2ce04b6b DM |
8760 | |
8761 | case DIV: | |
8762 | case UDIV: | |
8763 | case MOD: | |
8764 | case UMOD: | |
214c6394 DM |
8765 | if (FLOAT_MODE_P (GET_MODE (x))) |
8766 | { | |
8767 | switch (sparc_cpu) | |
8768 | { | |
8769 | case PROCESSOR_ULTRASPARC: | |
8770 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8771 | *total = COSTS_N_INSNS (13); |
214c6394 | 8772 | else |
3c50106f RH |
8773 | *total = COSTS_N_INSNS (23); |
8774 | return true; | |
214c6394 DM |
8775 | |
8776 | case PROCESSOR_ULTRASPARC3: | |
8777 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8778 | *total = COSTS_N_INSNS (17); |
214c6394 | 8779 | else |
3c50106f RH |
8780 | *total = COSTS_N_INSNS (20); |
8781 | return true; | |
214c6394 DM |
8782 | |
8783 | case PROCESSOR_SUPERSPARC: | |
8784 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8785 | *total = COSTS_N_INSNS (6); |
214c6394 | 8786 | else |
3c50106f RH |
8787 | *total = COSTS_N_INSNS (9); |
8788 | return true; | |
214c6394 DM |
8789 | |
8790 | case PROCESSOR_HYPERSPARC: | |
8791 | case PROCESSOR_SPARCLITE86X: | |
8792 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8793 | *total = COSTS_N_INSNS (8); |
214c6394 | 8794 | else |
3c50106f RH |
8795 | *total = COSTS_N_INSNS (12); |
8796 | return true; | |
214c6394 DM |
8797 | |
8798 | default: | |
3c50106f RH |
8799 | *total = COSTS_N_INSNS (7); |
8800 | return true; | |
214c6394 DM |
8801 | } |
8802 | } | |
8803 | ||
2ce04b6b | 8804 | if (sparc_cpu == PROCESSOR_ULTRASPARC) |
3c50106f RH |
8805 | *total = (GET_MODE (x) == DImode |
8806 | ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); | |
8807 | else if (sparc_cpu == PROCESSOR_ULTRASPARC3) | |
8808 | *total = (GET_MODE (x) == DImode | |
8809 | ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40)); | |
8810 | else | |
8811 | *total = COSTS_N_INSNS (25); | |
8812 | return true; | |
2ce04b6b | 8813 | |
214c6394 DM |
8814 | case IF_THEN_ELSE: |
8815 | /* Conditional moves. */ | |
8816 | switch (sparc_cpu) | |
8817 | { | |
8818 | case PROCESSOR_ULTRASPARC: | |
3c50106f RH |
8819 | *total = COSTS_N_INSNS (2); |
8820 | return true; | |
214c6394 DM |
8821 | |
8822 | case PROCESSOR_ULTRASPARC3: | |
8823 | if (FLOAT_MODE_P (GET_MODE (x))) | |
3c50106f | 8824 | *total = COSTS_N_INSNS (3); |
214c6394 | 8825 | else |
3c50106f RH |
8826 | *total = COSTS_N_INSNS (2); |
8827 | return true; | |
214c6394 DM |
8828 | |
8829 | default: | |
3c50106f RH |
8830 | *total = COSTS_N_INSNS (1); |
8831 | return true; | |
214c6394 DM |
8832 | } |
8833 | ||
8834 | case MEM: | |
8835 | /* If outer-code is SIGN/ZERO extension we have to subtract | |
8836 | out COSTS_N_INSNS (1) from whatever we return in determining | |
8837 | the cost. */ | |
8838 | switch (sparc_cpu) | |
8839 | { | |
8840 | case PROCESSOR_ULTRASPARC: | |
8841 | if (outer_code == ZERO_EXTEND) | |
3c50106f | 8842 | *total = COSTS_N_INSNS (1); |
214c6394 | 8843 | else |
3c50106f RH |
8844 | *total = COSTS_N_INSNS (2); |
8845 | return true; | |
214c6394 DM |
8846 | |
8847 | case PROCESSOR_ULTRASPARC3: | |
8848 | if (outer_code == ZERO_EXTEND) | |
8849 | { | |
8850 | if (GET_MODE (x) == QImode | |
8851 | || GET_MODE (x) == HImode | |
8852 | || outer_code == SIGN_EXTEND) | |
3c50106f | 8853 | *total = COSTS_N_INSNS (2); |
214c6394 | 8854 | else |
3c50106f | 8855 | *total = COSTS_N_INSNS (1); |
214c6394 DM |
8856 | } |
8857 | else | |
8858 | { | |
8859 | /* This handles sign extension (3 cycles) | |
8860 | and everything else (2 cycles). */ | |
3c50106f | 8861 | *total = COSTS_N_INSNS (2); |
214c6394 | 8862 | } |
3c50106f | 8863 | return true; |
214c6394 DM |
8864 | |
8865 | case PROCESSOR_SUPERSPARC: | |
8866 | if (FLOAT_MODE_P (GET_MODE (x)) | |
8867 | || outer_code == ZERO_EXTEND | |
8868 | || outer_code == SIGN_EXTEND) | |
3c50106f | 8869 | *total = COSTS_N_INSNS (0); |
214c6394 | 8870 | else |
3c50106f RH |
8871 | *total = COSTS_N_INSNS (1); |
8872 | return true; | |
214c6394 DM |
8873 | |
8874 | case PROCESSOR_TSC701: | |
8875 | if (outer_code == ZERO_EXTEND | |
8876 | || outer_code == SIGN_EXTEND) | |
3c50106f | 8877 | *total = COSTS_N_INSNS (2); |
214c6394 | 8878 | else |
3c50106f RH |
8879 | *total = COSTS_N_INSNS (3); |
8880 | return true; | |
214c6394 DM |
8881 | |
8882 | case PROCESSOR_CYPRESS: | |
8883 | if (outer_code == ZERO_EXTEND | |
8884 | || outer_code == SIGN_EXTEND) | |
3c50106f | 8885 | *total = COSTS_N_INSNS (1); |
214c6394 | 8886 | else |
3c50106f RH |
8887 | *total = COSTS_N_INSNS (2); |
8888 | return true; | |
214c6394 DM |
8889 | |
8890 | case PROCESSOR_HYPERSPARC: | |
8891 | case PROCESSOR_SPARCLITE86X: | |
8892 | default: | |
8893 | if (outer_code == ZERO_EXTEND | |
8894 | || outer_code == SIGN_EXTEND) | |
3c50106f | 8895 | *total = COSTS_N_INSNS (0); |
214c6394 | 8896 | else |
3c50106f RH |
8897 | *total = COSTS_N_INSNS (1); |
8898 | return true; | |
214c6394 | 8899 | } |
2ce04b6b DM |
8900 | |
8901 | case CONST_INT: | |
8902 | if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000) | |
3c50106f RH |
8903 | { |
8904 | *total = 0; | |
8905 | return true; | |
8906 | } | |
8907 | /* FALLTHRU */ | |
2ce04b6b | 8908 | |
2ce04b6b | 8909 | case HIGH: |
3c50106f RH |
8910 | *total = 2; |
8911 | return true; | |
2ce04b6b DM |
8912 | |
8913 | case CONST: | |
8914 | case LABEL_REF: | |
8915 | case SYMBOL_REF: | |
3c50106f RH |
8916 | *total = 4; |
8917 | return true; | |
2ce04b6b DM |
8918 | |
8919 | case CONST_DOUBLE: | |
3c50106f RH |
8920 | if (GET_MODE (x) == DImode |
8921 | && ((XINT (x, 3) == 0 | |
8922 | && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000) | |
8923 | || (XINT (x, 3) == -1 | |
8924 | && XINT (x, 2) < 0 | |
8925 | && XINT (x, 2) >= -0x1000))) | |
8926 | *total = 0; | |
8927 | else | |
8928 | *total = 8; | |
8929 | return true; | |
2ce04b6b DM |
8930 | |
8931 | default: | |
3c50106f RH |
8932 | return false; |
8933 | } | |
2ce04b6b | 8934 | } |
fb49053f | 8935 | |
e133041b RH |
8936 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. |
8937 | Used for C++ multiple inheritance. */ | |
8938 | ||
c590b625 | 8939 | static void |
fc27d102 KG |
8940 | sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
8941 | HOST_WIDE_INT delta, | |
8942 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
8943 | tree function) | |
e133041b RH |
8944 | { |
8945 | rtx this, insn, funexp, delta_rtx, tmp; | |
8946 | ||
8947 | reload_completed = 1; | |
fe3ad572 | 8948 | epilogue_completed = 1; |
e133041b RH |
8949 | no_new_pseudos = 1; |
8950 | current_function_uses_only_leaf_regs = 1; | |
8951 | ||
2e040219 | 8952 | emit_note (NOTE_INSN_PROLOGUE_END); |
e133041b RH |
8953 | |
8954 | /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function | |
8955 | returns a structure, the structure return pointer is there instead. */ | |
61f71b34 | 8956 | if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
e133041b RH |
8957 | this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1); |
8958 | else | |
8959 | this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST); | |
8960 | ||
8961 | /* Add DELTA. When possible use a plain add, otherwise load it into | |
8962 | a register first. */ | |
8963 | delta_rtx = GEN_INT (delta); | |
8964 | if (!SPARC_SIMM13_P (delta)) | |
8965 | { | |
8966 | rtx scratch = gen_rtx_REG (Pmode, 1); | |
8967 | if (TARGET_ARCH64) | |
8968 | sparc_emit_set_const64 (scratch, delta_rtx); | |
8969 | else | |
8970 | sparc_emit_set_const32 (scratch, delta_rtx); | |
8971 | delta_rtx = scratch; | |
8972 | } | |
8973 | ||
8974 | tmp = gen_rtx_PLUS (Pmode, this, delta_rtx); | |
8975 | emit_insn (gen_rtx_SET (VOIDmode, this, tmp)); | |
8976 | ||
8977 | /* Generate a tail call to the target function. */ | |
8978 | if (! TREE_USED (function)) | |
8979 | { | |
8980 | assemble_external (function); | |
8981 | TREE_USED (function) = 1; | |
8982 | } | |
8983 | funexp = XEXP (DECL_RTL (function), 0); | |
8984 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); | |
8985 | insn = emit_call_insn (gen_sibcall (funexp)); | |
8986 | SIBLING_CALL_P (insn) = 1; | |
8987 | emit_barrier (); | |
8988 | ||
8989 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
8990 | There's not really enough bulk here to make other passes such as | |
8991 | instruction scheduling worth while. Note that use_thunk calls | |
8992 | assemble_start_function and assemble_end_function. */ | |
8993 | insn = get_insns (); | |
a2855205 | 8994 | insn_locators_initialize (); |
e133041b RH |
8995 | shorten_branches (insn); |
8996 | final_start_function (insn, file, 1); | |
8997 | final (insn, file, 1, 0); | |
8998 | final_end_function (); | |
8999 | ||
9000 | reload_completed = 0; | |
fe3ad572 | 9001 | epilogue_completed = 0; |
e133041b RH |
9002 | no_new_pseudos = 0; |
9003 | } | |
e2500fed | 9004 | |
5751a10b JJ |
9005 | /* How to allocate a 'struct machine_function'. */ |
9006 | ||
9007 | static struct machine_function * | |
9008 | sparc_init_machine_status (void) | |
9009 | { | |
9010 | return ggc_alloc_cleared (sizeof (struct machine_function)); | |
9011 | } | |
9012 | ||
9013 | /* Locate some local-dynamic symbol still in use by this function | |
9014 | so that we can print its name in local-dynamic base patterns. */ | |
9015 | ||
9016 | static const char * | |
9017 | get_some_local_dynamic_name (void) | |
9018 | { | |
9019 | rtx insn; | |
9020 | ||
9021 | if (cfun->machine->some_ld_name) | |
9022 | return cfun->machine->some_ld_name; | |
9023 | ||
9024 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
9025 | if (INSN_P (insn) | |
9026 | && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0)) | |
9027 | return cfun->machine->some_ld_name; | |
9028 | ||
9029 | abort (); | |
9030 | } | |
9031 | ||
9032 | static int | |
9033 | get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) | |
9034 | { | |
9035 | rtx x = *px; | |
9036 | ||
9037 | if (x | |
9038 | && GET_CODE (x) == SYMBOL_REF | |
9039 | && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
9040 | { | |
9041 | cfun->machine->some_ld_name = XSTR (x, 0); | |
9042 | return 1; | |
9043 | } | |
9044 | ||
9045 | return 0; | |
9046 | } | |
9047 | ||
9048 | /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL. | |
9049 | We need to emit DTP-relative relocations. */ | |
9050 | ||
9051 | void | |
9052 | sparc_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
9053 | { | |
9054 | switch (size) | |
9055 | { | |
9056 | case 4: | |
9057 | fputs ("\t.word\t%r_tls_dtpoff32(", file); | |
9058 | break; | |
9059 | case 8: | |
9060 | fputs ("\t.xword\t%r_tls_dtpoff64(", file); | |
9061 | break; | |
9062 | default: | |
9063 | abort (); | |
9064 | } | |
9065 | output_addr_const (file, x); | |
9066 | fputs (")", file); | |
9067 | } | |
9068 | ||
e2500fed | 9069 | #include "gt-sparc.h" |