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c3427c7d | 1 | /* Subroutines for insn-output.c for SPARC. |
4592bdcb | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
4900aa61 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
62de55f7 | 4 | Free Software Foundation, Inc. |
ab835497 | 5 | Contributed by Michael Tiemann (tiemann@cygnus.com) |
c3427c7d | 6 | 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
61a55e8b | 7 | at Cygnus Support. |
ab835497 | 8 | |
4d8af13f | 9 | This file is part of GCC. |
ab835497 | 10 | |
4d8af13f | 11 | GCC is free software; you can redistribute it and/or modify |
ab835497 | 12 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
ab835497 RK |
14 | any later version. |
15 | ||
4d8af13f | 16 | GCC is distributed in the hope that it will be useful, |
ab835497 RK |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
22 | along with GCC; see the file COPYING3. If not see |
23 | <http://www.gnu.org/licenses/>. */ | |
ab835497 | 24 | |
ab835497 | 25 | #include "config.h" |
284d86e9 | 26 | #include "system.h" |
4977bab6 ZW |
27 | #include "coretypes.h" |
28 | #include "tm.h" | |
210aa14a | 29 | #include "tree.h" |
ab835497 RK |
30 | #include "rtl.h" |
31 | #include "regs.h" | |
32 | #include "hard-reg-set.h" | |
ab835497 | 33 | #include "insn-config.h" |
16f59241 | 34 | #include "insn-codes.h" |
ab835497 | 35 | #include "conditions.h" |
ab835497 RK |
36 | #include "output.h" |
37 | #include "insn-attr.h" | |
38 | #include "flags.h" | |
49ad7cfa | 39 | #include "function.h" |
ab835497 | 40 | #include "expr.h" |
e78d8e51 | 41 | #include "optabs.h" |
ab835497 | 42 | #include "recog.h" |
487a6e06 | 43 | #include "toplev.h" |
d07d525a | 44 | #include "ggc.h" |
b1474bb7 | 45 | #include "tm_p.h" |
e78d8e51 | 46 | #include "debug.h" |
672a6f42 NB |
47 | #include "target.h" |
48 | #include "target-def.h" | |
117dca74 | 49 | #include "cfglayout.h" |
726a989a | 50 | #include "gimple.h" |
16f59241 | 51 | #include "langhooks.h" |
47eb5b32 | 52 | #include "params.h" |
6fb5fa3c | 53 | #include "df.h" |
9fd52c6c | 54 | #include "dwarf2out.h" |
ab835497 | 55 | |
18df6de9 DM |
56 | /* Processor costs */ |
57 | static const | |
58 | struct processor_costs cypress_costs = { | |
ffe384ff DM |
59 | COSTS_N_INSNS (2), /* int load */ |
60 | COSTS_N_INSNS (2), /* int signed load */ | |
61 | COSTS_N_INSNS (2), /* int zeroed load */ | |
62 | COSTS_N_INSNS (2), /* float load */ | |
63 | COSTS_N_INSNS (5), /* fmov, fneg, fabs */ | |
64 | COSTS_N_INSNS (5), /* fadd, fsub */ | |
65 | COSTS_N_INSNS (1), /* fcmp */ | |
66 | COSTS_N_INSNS (1), /* fmov, fmovr */ | |
67 | COSTS_N_INSNS (7), /* fmul */ | |
68 | COSTS_N_INSNS (37), /* fdivs */ | |
69 | COSTS_N_INSNS (37), /* fdivd */ | |
70 | COSTS_N_INSNS (63), /* fsqrts */ | |
71 | COSTS_N_INSNS (63), /* fsqrtd */ | |
72 | COSTS_N_INSNS (1), /* imul */ | |
73 | COSTS_N_INSNS (1), /* imulX */ | |
18df6de9 | 74 | 0, /* imul bit factor */ |
ffe384ff DM |
75 | COSTS_N_INSNS (1), /* idiv */ |
76 | COSTS_N_INSNS (1), /* idivX */ | |
77 | COSTS_N_INSNS (1), /* movcc/movr */ | |
18df6de9 DM |
78 | 0, /* shift penalty */ |
79 | }; | |
80 | ||
81 | static const | |
82 | struct processor_costs supersparc_costs = { | |
ffe384ff DM |
83 | COSTS_N_INSNS (1), /* int load */ |
84 | COSTS_N_INSNS (1), /* int signed load */ | |
85 | COSTS_N_INSNS (1), /* int zeroed load */ | |
86 | COSTS_N_INSNS (0), /* float load */ | |
87 | COSTS_N_INSNS (3), /* fmov, fneg, fabs */ | |
88 | COSTS_N_INSNS (3), /* fadd, fsub */ | |
89 | COSTS_N_INSNS (3), /* fcmp */ | |
90 | COSTS_N_INSNS (1), /* fmov, fmovr */ | |
91 | COSTS_N_INSNS (3), /* fmul */ | |
92 | COSTS_N_INSNS (6), /* fdivs */ | |
93 | COSTS_N_INSNS (9), /* fdivd */ | |
94 | COSTS_N_INSNS (12), /* fsqrts */ | |
95 | COSTS_N_INSNS (12), /* fsqrtd */ | |
96 | COSTS_N_INSNS (4), /* imul */ | |
97 | COSTS_N_INSNS (4), /* imulX */ | |
18df6de9 | 98 | 0, /* imul bit factor */ |
ffe384ff DM |
99 | COSTS_N_INSNS (4), /* idiv */ |
100 | COSTS_N_INSNS (4), /* idivX */ | |
101 | COSTS_N_INSNS (1), /* movcc/movr */ | |
18df6de9 DM |
102 | 1, /* shift penalty */ |
103 | }; | |
104 | ||
105 | static const | |
106 | struct processor_costs hypersparc_costs = { | |
ffe384ff DM |
107 | COSTS_N_INSNS (1), /* int load */ |
108 | COSTS_N_INSNS (1), /* int signed load */ | |
109 | COSTS_N_INSNS (1), /* int zeroed load */ | |
110 | COSTS_N_INSNS (1), /* float load */ | |
111 | COSTS_N_INSNS (1), /* fmov, fneg, fabs */ | |
112 | COSTS_N_INSNS (1), /* fadd, fsub */ | |
113 | COSTS_N_INSNS (1), /* fcmp */ | |
114 | COSTS_N_INSNS (1), /* fmov, fmovr */ | |
115 | COSTS_N_INSNS (1), /* fmul */ | |
116 | COSTS_N_INSNS (8), /* fdivs */ | |
117 | COSTS_N_INSNS (12), /* fdivd */ | |
118 | COSTS_N_INSNS (17), /* fsqrts */ | |
119 | COSTS_N_INSNS (17), /* fsqrtd */ | |
120 | COSTS_N_INSNS (17), /* imul */ | |
121 | COSTS_N_INSNS (17), /* imulX */ | |
18df6de9 | 122 | 0, /* imul bit factor */ |
ffe384ff DM |
123 | COSTS_N_INSNS (17), /* idiv */ |
124 | COSTS_N_INSNS (17), /* idivX */ | |
125 | COSTS_N_INSNS (1), /* movcc/movr */ | |
18df6de9 DM |
126 | 0, /* shift penalty */ |
127 | }; | |
128 | ||
129 | static const | |
130 | struct processor_costs sparclet_costs = { | |
ffe384ff DM |
131 | COSTS_N_INSNS (3), /* int load */ |
132 | COSTS_N_INSNS (3), /* int signed load */ | |
133 | COSTS_N_INSNS (1), /* int zeroed load */ | |
134 | COSTS_N_INSNS (1), /* float load */ | |
135 | COSTS_N_INSNS (1), /* fmov, fneg, fabs */ | |
136 | COSTS_N_INSNS (1), /* fadd, fsub */ | |
137 | COSTS_N_INSNS (1), /* fcmp */ | |
138 | COSTS_N_INSNS (1), /* fmov, fmovr */ | |
139 | COSTS_N_INSNS (1), /* fmul */ | |
140 | COSTS_N_INSNS (1), /* fdivs */ | |
141 | COSTS_N_INSNS (1), /* fdivd */ | |
142 | COSTS_N_INSNS (1), /* fsqrts */ | |
143 | COSTS_N_INSNS (1), /* fsqrtd */ | |
144 | COSTS_N_INSNS (5), /* imul */ | |
145 | COSTS_N_INSNS (5), /* imulX */ | |
18df6de9 | 146 | 0, /* imul bit factor */ |
ffe384ff DM |
147 | COSTS_N_INSNS (5), /* idiv */ |
148 | COSTS_N_INSNS (5), /* idivX */ | |
149 | COSTS_N_INSNS (1), /* movcc/movr */ | |
18df6de9 DM |
150 | 0, /* shift penalty */ |
151 | }; | |
152 | ||
153 | static const | |
154 | struct processor_costs ultrasparc_costs = { | |
ffe384ff DM |
155 | COSTS_N_INSNS (2), /* int load */ |
156 | COSTS_N_INSNS (3), /* int signed load */ | |
157 | COSTS_N_INSNS (2), /* int zeroed load */ | |
158 | COSTS_N_INSNS (2), /* float load */ | |
159 | COSTS_N_INSNS (1), /* fmov, fneg, fabs */ | |
160 | COSTS_N_INSNS (4), /* fadd, fsub */ | |
161 | COSTS_N_INSNS (1), /* fcmp */ | |
162 | COSTS_N_INSNS (2), /* fmov, fmovr */ | |
163 | COSTS_N_INSNS (4), /* fmul */ | |
164 | COSTS_N_INSNS (13), /* fdivs */ | |
165 | COSTS_N_INSNS (23), /* fdivd */ | |
166 | COSTS_N_INSNS (13), /* fsqrts */ | |
167 | COSTS_N_INSNS (23), /* fsqrtd */ | |
168 | COSTS_N_INSNS (4), /* imul */ | |
169 | COSTS_N_INSNS (4), /* imulX */ | |
18df6de9 | 170 | 2, /* imul bit factor */ |
ffe384ff DM |
171 | COSTS_N_INSNS (37), /* idiv */ |
172 | COSTS_N_INSNS (68), /* idivX */ | |
173 | COSTS_N_INSNS (2), /* movcc/movr */ | |
18df6de9 DM |
174 | 2, /* shift penalty */ |
175 | }; | |
176 | ||
177 | static const | |
178 | struct processor_costs ultrasparc3_costs = { | |
ffe384ff DM |
179 | COSTS_N_INSNS (2), /* int load */ |
180 | COSTS_N_INSNS (3), /* int signed load */ | |
181 | COSTS_N_INSNS (3), /* int zeroed load */ | |
182 | COSTS_N_INSNS (2), /* float load */ | |
183 | COSTS_N_INSNS (3), /* fmov, fneg, fabs */ | |
184 | COSTS_N_INSNS (4), /* fadd, fsub */ | |
185 | COSTS_N_INSNS (5), /* fcmp */ | |
186 | COSTS_N_INSNS (3), /* fmov, fmovr */ | |
187 | COSTS_N_INSNS (4), /* fmul */ | |
188 | COSTS_N_INSNS (17), /* fdivs */ | |
189 | COSTS_N_INSNS (20), /* fdivd */ | |
190 | COSTS_N_INSNS (20), /* fsqrts */ | |
191 | COSTS_N_INSNS (29), /* fsqrtd */ | |
192 | COSTS_N_INSNS (6), /* imul */ | |
193 | COSTS_N_INSNS (6), /* imulX */ | |
18df6de9 | 194 | 0, /* imul bit factor */ |
ffe384ff DM |
195 | COSTS_N_INSNS (40), /* idiv */ |
196 | COSTS_N_INSNS (71), /* idivX */ | |
197 | COSTS_N_INSNS (2), /* movcc/movr */ | |
18df6de9 DM |
198 | 0, /* shift penalty */ |
199 | }; | |
200 | ||
4c837a1e DM |
201 | static const |
202 | struct processor_costs niagara_costs = { | |
203 | COSTS_N_INSNS (3), /* int load */ | |
204 | COSTS_N_INSNS (3), /* int signed load */ | |
205 | COSTS_N_INSNS (3), /* int zeroed load */ | |
206 | COSTS_N_INSNS (9), /* float load */ | |
207 | COSTS_N_INSNS (8), /* fmov, fneg, fabs */ | |
208 | COSTS_N_INSNS (8), /* fadd, fsub */ | |
209 | COSTS_N_INSNS (26), /* fcmp */ | |
210 | COSTS_N_INSNS (8), /* fmov, fmovr */ | |
211 | COSTS_N_INSNS (29), /* fmul */ | |
212 | COSTS_N_INSNS (54), /* fdivs */ | |
213 | COSTS_N_INSNS (83), /* fdivd */ | |
214 | COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */ | |
215 | COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */ | |
216 | COSTS_N_INSNS (11), /* imul */ | |
217 | COSTS_N_INSNS (11), /* imulX */ | |
218 | 0, /* imul bit factor */ | |
219 | COSTS_N_INSNS (72), /* idiv */ | |
220 | COSTS_N_INSNS (72), /* idivX */ | |
221 | COSTS_N_INSNS (1), /* movcc/movr */ | |
222 | 0, /* shift penalty */ | |
223 | }; | |
224 | ||
9eeaed6e DM |
225 | static const |
226 | struct processor_costs niagara2_costs = { | |
227 | COSTS_N_INSNS (3), /* int load */ | |
228 | COSTS_N_INSNS (3), /* int signed load */ | |
229 | COSTS_N_INSNS (3), /* int zeroed load */ | |
230 | COSTS_N_INSNS (3), /* float load */ | |
231 | COSTS_N_INSNS (6), /* fmov, fneg, fabs */ | |
232 | COSTS_N_INSNS (6), /* fadd, fsub */ | |
233 | COSTS_N_INSNS (6), /* fcmp */ | |
234 | COSTS_N_INSNS (6), /* fmov, fmovr */ | |
235 | COSTS_N_INSNS (6), /* fmul */ | |
236 | COSTS_N_INSNS (19), /* fdivs */ | |
237 | COSTS_N_INSNS (33), /* fdivd */ | |
238 | COSTS_N_INSNS (19), /* fsqrts */ | |
239 | COSTS_N_INSNS (33), /* fsqrtd */ | |
240 | COSTS_N_INSNS (5), /* imul */ | |
241 | COSTS_N_INSNS (5), /* imulX */ | |
242 | 0, /* imul bit factor */ | |
243 | COSTS_N_INSNS (31), /* idiv, average of 12 - 41 cycle range */ | |
244 | COSTS_N_INSNS (31), /* idivX, average of 12 - 41 cycle range */ | |
245 | COSTS_N_INSNS (1), /* movcc/movr */ | |
246 | 0, /* shift penalty */ | |
247 | }; | |
248 | ||
18df6de9 DM |
249 | const struct processor_costs *sparc_costs = &cypress_costs; |
250 | ||
9ac617d4 EB |
251 | #ifdef HAVE_AS_RELAX_OPTION |
252 | /* If 'as' and 'ld' are relaxing tail call insns into branch always, use | |
253 | "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized. | |
254 | With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if | |
255 | somebody does not branch between the sethi and jmp. */ | |
6244b14e | 256 | #define LEAF_SIBCALL_SLOT_RESERVED_P 1 |
9ac617d4 | 257 | #else |
6244b14e EB |
258 | #define LEAF_SIBCALL_SLOT_RESERVED_P \ |
259 | ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic) | |
9ac617d4 EB |
260 | #endif |
261 | ||
ab835497 RK |
262 | /* Global variables for machine-dependent things. */ |
263 | ||
61a55e8b | 264 | /* Size of frame. Need to know this to emit return insns from leaf procedures. |
9ac617d4 EB |
265 | ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the |
266 | reload pass. This is important as the value is later used for scheduling | |
267 | (to see what can go in a delay slot). | |
61a55e8b DE |
268 | APPARENT_FSIZE is the size of the stack less the register save area and less |
269 | the outgoing argument area. It is used when saving call preserved regs. */ | |
6a151f87 EB |
270 | static HOST_WIDE_INT apparent_fsize; |
271 | static HOST_WIDE_INT actual_fsize; | |
61a55e8b | 272 | |
33074e5f RH |
273 | /* Number of live general or floating point registers needed to be |
274 | saved (as 4-byte quantities). */ | |
e48addee JJ |
275 | static int num_gfregs; |
276 | ||
9ac617d4 | 277 | /* The alias set for prologue/epilogue register save/restore. */ |
4862826d | 278 | static GTY(()) alias_set_type sparc_sr_alias_set; |
9ac617d4 | 279 | |
1da4c3a7 | 280 | /* The alias set for the structure return value. */ |
4862826d | 281 | static GTY(()) alias_set_type struct_value_alias_set; |
1da4c3a7 | 282 | |
563c12b0 RH |
283 | /* Vector to say how input registers are mapped to output registers. |
284 | HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to | |
285 | eliminate it. You must use -fomit-frame-pointer to get that. */ | |
d70e94ec | 286 | char leaf_reg_remap[] = |
ab835497 RK |
287 | { 0, 1, 2, 3, 4, 5, 6, 7, |
288 | -1, -1, -1, -1, -1, -1, 14, -1, | |
289 | -1, -1, -1, -1, -1, -1, -1, -1, | |
290 | 8, 9, 10, 11, 12, 13, -1, 15, | |
291 | ||
292 | 32, 33, 34, 35, 36, 37, 38, 39, | |
293 | 40, 41, 42, 43, 44, 45, 46, 47, | |
294 | 48, 49, 50, 51, 52, 53, 54, 55, | |
61a55e8b DE |
295 | 56, 57, 58, 59, 60, 61, 62, 63, |
296 | 64, 65, 66, 67, 68, 69, 70, 71, | |
297 | 72, 73, 74, 75, 76, 77, 78, 79, | |
298 | 80, 81, 82, 83, 84, 85, 86, 87, | |
299 | 88, 89, 90, 91, 92, 93, 94, 95, | |
c4ce6853 | 300 | 96, 97, 98, 99, 100}; |
ab835497 | 301 | |
7d167afd JJ |
302 | /* Vector, indexed by hard register number, which contains 1 |
303 | for a register that is allowable in a candidate for leaf | |
304 | function treatment. */ | |
305 | char sparc_leaf_regs[] = | |
306 | { 1, 1, 1, 1, 1, 1, 1, 1, | |
307 | 0, 0, 0, 0, 0, 0, 1, 0, | |
308 | 0, 0, 0, 0, 0, 0, 0, 0, | |
309 | 1, 1, 1, 1, 1, 1, 0, 1, | |
310 | 1, 1, 1, 1, 1, 1, 1, 1, | |
311 | 1, 1, 1, 1, 1, 1, 1, 1, | |
312 | 1, 1, 1, 1, 1, 1, 1, 1, | |
313 | 1, 1, 1, 1, 1, 1, 1, 1, | |
314 | 1, 1, 1, 1, 1, 1, 1, 1, | |
315 | 1, 1, 1, 1, 1, 1, 1, 1, | |
316 | 1, 1, 1, 1, 1, 1, 1, 1, | |
317 | 1, 1, 1, 1, 1, 1, 1, 1, | |
318 | 1, 1, 1, 1, 1}; | |
319 | ||
d1b38208 | 320 | struct GTY(()) machine_function |
5751a10b JJ |
321 | { |
322 | /* Some local-dynamic TLS symbol name. */ | |
323 | const char *some_ld_name; | |
5be9b7a1 EB |
324 | |
325 | /* True if the current function is leaf and uses only leaf regs, | |
326 | so that the SPARC leaf function optimization can be applied. | |
327 | Private version of current_function_uses_only_leaf_regs, see | |
328 | sparc_expand_prologue for the rationale. */ | |
329 | int leaf_function_p; | |
330 | ||
331 | /* True if the data calculated by sparc_expand_prologue are valid. */ | |
332 | bool prologue_data_valid_p; | |
5751a10b JJ |
333 | }; |
334 | ||
5be9b7a1 EB |
335 | #define sparc_leaf_function_p cfun->machine->leaf_function_p |
336 | #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p | |
337 | ||
9ac617d4 EB |
338 | /* Register we pretend to think the frame pointer is allocated to. |
339 | Normally, this is %fp, but if we are in a leaf procedure, this | |
340 | is %sp+"something". We record "something" separately as it may | |
341 | be too big for reg+constant addressing. */ | |
9ac617d4 | 342 | static rtx frame_base_reg; |
6a151f87 | 343 | static HOST_WIDE_INT frame_base_offset; |
ab835497 | 344 | |
4e5b002b EB |
345 | /* 1 if the next opcode is to be specially indented. */ |
346 | int sparc_indent_opcode = 0; | |
347 | ||
fe609b0f | 348 | static bool sparc_handle_option (size_t, const char *, int); |
e80d5f80 | 349 | static void sparc_init_modes (void); |
5c4f4b18 | 350 | static void scan_record_type (tree, int *, int *, int *); |
e80d5f80 KG |
351 | static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode, |
352 | tree, int, int, int *, int *); | |
353 | ||
354 | static int supersparc_adjust_cost (rtx, rtx, rtx, int); | |
355 | static int hypersparc_adjust_cost (rtx, rtx, rtx, int); | |
356 | ||
357 | static void sparc_output_addr_vec (rtx); | |
358 | static void sparc_output_addr_diff_vec (rtx); | |
359 | static void sparc_output_deferred_case_vectors (void); | |
c6c3dba9 | 360 | static bool sparc_legitimate_address_p (enum machine_mode, rtx, bool); |
3e2cc1d1 | 361 | static rtx sparc_builtin_saveregs (void); |
e80d5f80 KG |
362 | static int epilogue_renumber (rtx *, int); |
363 | static bool sparc_assemble_integer (rtx, unsigned int, int); | |
364 | static int set_extends (rtx); | |
9fd52c6c | 365 | static void load_pic_register (void); |
9ac617d4 | 366 | static int save_or_restore_regs (int, int, rtx, int, int); |
f8ece000 | 367 | static void emit_save_or_restore_regs (int); |
9ac617d4 EB |
368 | static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT); |
369 | static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT); | |
d1ced155 EB |
370 | static void sparc_solaris_elf_asm_named_section (const char *, unsigned int, |
371 | tree) ATTRIBUTE_UNUSED; | |
e80d5f80 KG |
372 | static int sparc_adjust_cost (rtx, rtx, rtx, int); |
373 | static int sparc_issue_rate (void); | |
374 | static void sparc_sched_init (FILE *, int, int); | |
e80d5f80 KG |
375 | static int sparc_use_sched_lookahead (void); |
376 | ||
377 | static void emit_soft_tfmode_libcall (const char *, int, rtx *); | |
378 | static void emit_soft_tfmode_binop (enum rtx_code, rtx *); | |
379 | static void emit_soft_tfmode_unop (enum rtx_code, rtx *); | |
380 | static void emit_soft_tfmode_cvt (enum rtx_code, rtx *); | |
381 | static void emit_hard_tfmode_operation (enum rtx_code, rtx *); | |
382 | ||
383 | static bool sparc_function_ok_for_sibcall (tree, tree); | |
c15c90bb | 384 | static void sparc_init_libfuncs (void); |
16f59241 JM |
385 | static void sparc_init_builtins (void); |
386 | static void sparc_vis_init_builtins (void); | |
387 | static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
f311c3b4 | 388 | static tree sparc_fold_builtin (tree, int, tree *, bool); |
8b0096b4 JM |
389 | static int sparc_vis_mul8x16 (int, int); |
390 | static tree sparc_handle_vis_mul8x16 (int, tree, tree, tree); | |
e80d5f80 KG |
391 | static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
392 | HOST_WIDE_INT, tree); | |
3101faab KG |
393 | static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT, |
394 | HOST_WIDE_INT, const_tree); | |
5751a10b JJ |
395 | static struct machine_function * sparc_init_machine_status (void); |
396 | static bool sparc_cannot_force_const_mem (rtx); | |
397 | static rtx sparc_tls_get_addr (void); | |
398 | static rtx sparc_tls_got (void); | |
399 | static const char *get_some_local_dynamic_name (void); | |
400 | static int get_some_local_dynamic_name_1 (rtx *, void *); | |
f40751dd | 401 | static bool sparc_rtx_costs (rtx, int, int, int *, bool); |
586de218 | 402 | static bool sparc_promote_prototypes (const_tree); |
bf44d792 AS |
403 | static rtx sparc_function_value (const_tree, const_tree, bool); |
404 | static rtx sparc_libcall_value (enum machine_mode, const_rtx); | |
405 | static bool sparc_function_value_regno_p (const unsigned int); | |
3e2cc1d1 | 406 | static rtx sparc_struct_value_rtx (tree, int); |
cde0f3fd PB |
407 | static enum machine_mode sparc_promote_function_mode (const_tree, enum machine_mode, |
408 | int *, const_tree, int); | |
586de218 | 409 | static bool sparc_return_in_memory (const_tree, const_tree); |
3e2cc1d1 | 410 | static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *); |
d7bd8aeb | 411 | static void sparc_va_start (tree, rtx); |
726a989a | 412 | static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *); |
c75d6010 | 413 | static bool sparc_vector_mode_supported_p (enum machine_mode); |
208384fd EB |
414 | static bool sparc_tls_referenced_p (rtx); |
415 | static rtx legitimize_tls_address (rtx); | |
416 | static rtx legitimize_pic_address (rtx, rtx); | |
506d7b68 | 417 | static rtx sparc_legitimize_address (rtx, rtx, enum machine_mode); |
277e2873 | 418 | static bool sparc_mode_dependent_address_p (const_rtx); |
8cd5a4e0 | 419 | static bool sparc_pass_by_reference (CUMULATIVE_ARGS *, |
586de218 | 420 | enum machine_mode, const_tree, bool); |
78a52f11 RH |
421 | static int sparc_arg_partial_bytes (CUMULATIVE_ARGS *, |
422 | enum machine_mode, tree, bool); | |
e54c7471 | 423 | static void sparc_dwarf_handle_frame_unspec (const char *, rtx, int); |
fdbe66f2 | 424 | static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
5e77eb53 | 425 | static void sparc_file_end (void); |
b52b1749 | 426 | static bool sparc_frame_pointer_required (void); |
7b5cbb57 | 427 | static bool sparc_can_eliminate (const int, const int); |
7269aee7 | 428 | #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING |
3101faab | 429 | static const char *sparc_mangle_type (const_tree); |
7269aee7 | 430 | #endif |
809e78cc | 431 | static void sparc_trampoline_init (rtx, tree, rtx); |
5a82ecd9 | 432 | \f |
07a43492 | 433 | #ifdef SUBTARGET_ATTRIBUTE_TABLE |
5a82ecd9 ILT |
434 | /* Table of valid machine attributes. */ |
435 | static const struct attribute_spec sparc_attribute_table[] = | |
436 | { | |
437 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ | |
438 | SUBTARGET_ATTRIBUTE_TABLE, | |
439 | { NULL, 0, 0, false, false, false, NULL } | |
440 | }; | |
07a43492 | 441 | #endif |
61a55e8b DE |
442 | \f |
443 | /* Option handling. */ | |
444 | ||
a0a301fc DE |
445 | /* Parsed value. */ |
446 | enum cmodel sparc_cmodel; | |
447 | ||
1cb36a98 RH |
448 | char sparc_hard_reg_printed[8]; |
449 | ||
16956f6e DE |
450 | struct sparc_cpu_select sparc_select[] = |
451 | { | |
452 | /* switch name, tune arch */ | |
453 | { (char *)0, "default", 1, 1 }, | |
454 | { (char *)0, "-mcpu=", 1, 1 }, | |
455 | { (char *)0, "-mtune=", 1, 0 }, | |
db3d4438 | 456 | { 0, 0, 0, 0 } |
16956f6e | 457 | }; |
733f53f5 | 458 | |
16956f6e DE |
459 | /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ |
460 | enum processor_type sparc_cpu; | |
fe609b0f EB |
461 | |
462 | /* Whether\fan FPU option was specified. */ | |
463 | static bool fpu_option_set = false; | |
464 | ||
672a6f42 | 465 | /* Initialize the GCC target structure. */ |
301d03af | 466 | |
d1ced155 | 467 | /* The default is to use .half rather than .short for aligned HI objects. */ |
301d03af RS |
468 | #undef TARGET_ASM_ALIGNED_HI_OP |
469 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
301d03af RS |
470 | |
471 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
472 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t" | |
473 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
474 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t" | |
475 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
476 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t" | |
477 | ||
478 | /* The target hook has to handle DI-mode values. */ | |
479 | #undef TARGET_ASM_INTEGER | |
480 | #define TARGET_ASM_INTEGER sparc_assemble_integer | |
481 | ||
08c148a8 | 482 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
9ac617d4 | 483 | #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue |
08c148a8 | 484 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
9ac617d4 | 485 | #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue |
733f53f5 | 486 | |
c237e94a ZW |
487 | #undef TARGET_SCHED_ADJUST_COST |
488 | #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost | |
489 | #undef TARGET_SCHED_ISSUE_RATE | |
490 | #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate | |
c237e94a ZW |
491 | #undef TARGET_SCHED_INIT |
492 | #define TARGET_SCHED_INIT sparc_sched_init | |
fae15c93 VM |
493 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
494 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead | |
c237e94a | 495 | |
4977bab6 ZW |
496 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
497 | #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall | |
498 | ||
c15c90bb ZW |
499 | #undef TARGET_INIT_LIBFUNCS |
500 | #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs | |
16f59241 JM |
501 | #undef TARGET_INIT_BUILTINS |
502 | #define TARGET_INIT_BUILTINS sparc_init_builtins | |
503 | ||
506d7b68 PB |
504 | #undef TARGET_LEGITIMIZE_ADDRESS |
505 | #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address | |
277e2873 AS |
506 | #undef TARGET_MODE_DEPENDENT_ADDRESS_P |
507 | #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p | |
506d7b68 | 508 | |
16f59241 JM |
509 | #undef TARGET_EXPAND_BUILTIN |
510 | #define TARGET_EXPAND_BUILTIN sparc_expand_builtin | |
8b0096b4 JM |
511 | #undef TARGET_FOLD_BUILTIN |
512 | #define TARGET_FOLD_BUILTIN sparc_fold_builtin | |
c15c90bb | 513 | |
fdbe66f2 | 514 | #if TARGET_TLS |
5751a10b JJ |
515 | #undef TARGET_HAVE_TLS |
516 | #define TARGET_HAVE_TLS true | |
517 | #endif | |
fdbe66f2 | 518 | |
5751a10b JJ |
519 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
520 | #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem | |
521 | ||
c590b625 RH |
522 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
523 | #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk | |
3961e8fe | 524 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
b9bf58e5 | 525 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk |
c590b625 | 526 | |
3c50106f RH |
527 | #undef TARGET_RTX_COSTS |
528 | #define TARGET_RTX_COSTS sparc_rtx_costs | |
dcefdf67 | 529 | #undef TARGET_ADDRESS_COST |
f40751dd | 530 | #define TARGET_ADDRESS_COST hook_int_rtx_bool_0 |
3c50106f | 531 | |
cde0f3fd PB |
532 | #undef TARGET_PROMOTE_FUNCTION_MODE |
533 | #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode | |
3e2cc1d1 KH |
534 | |
535 | #undef TARGET_PROMOTE_PROTOTYPES | |
536 | #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes | |
537 | ||
bf44d792 AS |
538 | #undef TARGET_FUNCTION_VALUE |
539 | #define TARGET_FUNCTION_VALUE sparc_function_value | |
540 | #undef TARGET_LIBCALL_VALUE | |
541 | #define TARGET_LIBCALL_VALUE sparc_libcall_value | |
542 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
543 | #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p | |
544 | ||
3e2cc1d1 KH |
545 | #undef TARGET_STRUCT_VALUE_RTX |
546 | #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx | |
547 | #undef TARGET_RETURN_IN_MEMORY | |
548 | #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory | |
fe984136 RH |
549 | #undef TARGET_MUST_PASS_IN_STACK |
550 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
8cd5a4e0 RH |
551 | #undef TARGET_PASS_BY_REFERENCE |
552 | #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference | |
78a52f11 RH |
553 | #undef TARGET_ARG_PARTIAL_BYTES |
554 | #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes | |
3e2cc1d1 KH |
555 | |
556 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
557 | #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs | |
558 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
559 | #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming | |
560 | ||
d7bd8aeb JJ |
561 | #undef TARGET_EXPAND_BUILTIN_VA_START |
562 | #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start | |
5f393b25 JM |
563 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
564 | #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg | |
565 | ||
c75d6010 JM |
566 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
567 | #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p | |
568 | ||
e54c7471 EB |
569 | #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC |
570 | #define TARGET_DWARF_HANDLE_FRAME_UNSPEC sparc_dwarf_handle_frame_unspec | |
571 | ||
07a43492 DJ |
572 | #ifdef SUBTARGET_INSERT_ATTRIBUTES |
573 | #undef TARGET_INSERT_ATTRIBUTES | |
574 | #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES | |
575 | #endif | |
576 | ||
577 | #ifdef SUBTARGET_ATTRIBUTE_TABLE | |
578 | #undef TARGET_ATTRIBUTE_TABLE | |
579 | #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table | |
580 | #endif | |
581 | ||
0e4e8dab | 582 | #undef TARGET_RELAXED_ORDERING |
548a6c4f | 583 | #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING |
445cf5eb | 584 | |
fe609b0f EB |
585 | #undef TARGET_DEFAULT_TARGET_FLAGS |
586 | #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT | |
587 | #undef TARGET_HANDLE_OPTION | |
588 | #define TARGET_HANDLE_OPTION sparc_handle_option | |
589 | ||
f06fb22b | 590 | #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL) |
fdbe66f2 EB |
591 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL |
592 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel | |
593 | #endif | |
594 | ||
c81739f7 | 595 | #undef TARGET_ASM_FILE_END |
5e77eb53 EB |
596 | #define TARGET_ASM_FILE_END sparc_file_end |
597 | ||
b52b1749 AS |
598 | #undef TARGET_FRAME_POINTER_REQUIRED |
599 | #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required | |
600 | ||
7b5cbb57 AS |
601 | #undef TARGET_CAN_ELIMINATE |
602 | #define TARGET_CAN_ELIMINATE sparc_can_eliminate | |
603 | ||
7269aee7 | 604 | #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING |
608063c3 JB |
605 | #undef TARGET_MANGLE_TYPE |
606 | #define TARGET_MANGLE_TYPE sparc_mangle_type | |
7269aee7 AH |
607 | #endif |
608 | ||
c6c3dba9 PB |
609 | #undef TARGET_LEGITIMATE_ADDRESS_P |
610 | #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p | |
611 | ||
809e78cc RH |
612 | #undef TARGET_TRAMPOLINE_INIT |
613 | #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init | |
614 | ||
f6897b10 | 615 | struct gcc_target targetm = TARGET_INITIALIZER; |
fe609b0f EB |
616 | |
617 | /* Implement TARGET_HANDLE_OPTION. */ | |
618 | ||
619 | static bool | |
620 | sparc_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) | |
621 | { | |
622 | switch (code) | |
623 | { | |
624 | case OPT_mfpu: | |
625 | case OPT_mhard_float: | |
626 | case OPT_msoft_float: | |
627 | fpu_option_set = true; | |
628 | break; | |
629 | ||
630 | case OPT_mcpu_: | |
631 | sparc_select[1].string = arg; | |
632 | break; | |
633 | ||
634 | case OPT_mtune_: | |
635 | sparc_select[2].string = arg; | |
636 | break; | |
fe609b0f EB |
637 | } |
638 | ||
639 | return true; | |
640 | } | |
641 | ||
61a55e8b DE |
642 | /* Validate and override various options, and do some machine dependent |
643 | initialization. */ | |
644 | ||
645 | void | |
fc27d102 | 646 | sparc_override_options (void) |
61a55e8b | 647 | { |
a0a301fc | 648 | static struct code_model { |
8b60264b | 649 | const char *const name; |
32e8bb8e | 650 | const enum cmodel value; |
8b60264b | 651 | } const cmodels[] = { |
a0a301fc DE |
652 | { "32", CM_32 }, |
653 | { "medlow", CM_MEDLOW }, | |
654 | { "medmid", CM_MEDMID }, | |
655 | { "medany", CM_MEDANY }, | |
656 | { "embmedany", CM_EMBMEDANY }, | |
32e8bb8e | 657 | { NULL, (enum cmodel) 0 } |
a0a301fc | 658 | }; |
8b60264b | 659 | const struct code_model *cmodel; |
16956f6e | 660 | /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ |
733f53f5 | 661 | static struct cpu_default { |
8b60264b KG |
662 | const int cpu; |
663 | const char *const name; | |
664 | } const cpu_default[] = { | |
a0a301fc | 665 | /* There must be one entry here for each TARGET_CPU value. */ |
16956f6e | 666 | { TARGET_CPU_sparc, "cypress" }, |
3592ea0d | 667 | { TARGET_CPU_sparclet, "tsc701" }, |
16956f6e | 668 | { TARGET_CPU_sparclite, "f930" }, |
a0a301fc | 669 | { TARGET_CPU_v8, "v8" }, |
8947065c RH |
670 | { TARGET_CPU_hypersparc, "hypersparc" }, |
671 | { TARGET_CPU_sparclite86x, "sparclite86x" }, | |
a0a301fc DE |
672 | { TARGET_CPU_supersparc, "supersparc" }, |
673 | { TARGET_CPU_v9, "v9" }, | |
ba542005 | 674 | { TARGET_CPU_ultrasparc, "ultrasparc" }, |
fae15c93 | 675 | { TARGET_CPU_ultrasparc3, "ultrasparc3" }, |
4c837a1e | 676 | { TARGET_CPU_niagara, "niagara" }, |
9eeaed6e | 677 | { TARGET_CPU_niagara2, "niagara2" }, |
db3d4438 | 678 | { 0, 0 } |
733f53f5 | 679 | }; |
8b60264b | 680 | const struct cpu_default *def; |
16956f6e | 681 | /* Table of values for -m{cpu,tune}=. */ |
733f53f5 | 682 | static struct cpu_table { |
8b60264b KG |
683 | const char *const name; |
684 | const enum processor_type processor; | |
685 | const int disable; | |
686 | const int enable; | |
687 | } const cpu_table[] = { | |
16956f6e DE |
688 | { "v7", PROCESSOR_V7, MASK_ISA, 0 }, |
689 | { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, | |
690 | { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, | |
733f53f5 | 691 | /* TI TMS390Z55 supersparc */ |
16956f6e DE |
692 | { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, |
693 | { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, | |
733f53f5 DE |
694 | /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. |
695 | The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ | |
16956f6e DE |
696 | { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, |
697 | { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, | |
8947065c | 698 | { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, |
d3ec6b06 VM |
699 | { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, |
700 | MASK_SPARCLITE }, | |
16956f6e | 701 | { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, |
733f53f5 | 702 | /* TEMIC sparclet */ |
3592ea0d | 703 | { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, |
16956f6e | 704 | { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, |
5cb01b65 JJ |
705 | /* TI ultrasparc I, II, IIi */ |
706 | { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 | |
707 | /* Although insns using %y are deprecated, it is a clear win on current | |
80ffc95e | 708 | ultrasparcs. */ |
3276910d | 709 | |MASK_DEPRECATED_V8_INSNS}, |
fae15c93 VM |
710 | /* TI ultrasparc III */ |
711 | /* ??? Check if %y issue still holds true in ultra3. */ | |
712 | { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, | |
4c837a1e DM |
713 | /* UltraSPARC T1 */ |
714 | { "niagara", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, | |
9eeaed6e | 715 | { "niagara2", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9}, |
81f40b79 | 716 | { 0, (enum processor_type) 0, 0, 0 } |
733f53f5 | 717 | }; |
8b60264b KG |
718 | const struct cpu_table *cpu; |
719 | const struct sparc_cpu_select *sel; | |
a0a301fc | 720 | int fpu; |
4900aa61 | 721 | |
a0a301fc DE |
722 | #ifndef SPARC_BI_ARCH |
723 | /* Check for unsupported architecture size. */ | |
724 | if (! TARGET_64BIT != DEFAULT_ARCH32_P) | |
3276910d RK |
725 | error ("%s is not supported by this configuration", |
726 | DEFAULT_ARCH32_P ? "-m64" : "-m32"); | |
a0a301fc DE |
727 | #endif |
728 | ||
4710d3eb JJ |
729 | /* We force all 64bit archs to use 128 bit long double */ |
730 | if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128) | |
731 | { | |
732 | error ("-mlong-double-64 not allowed with -m64"); | |
733 | target_flags |= MASK_LONG_DOUBLE_128; | |
734 | } | |
735 | ||
a0a301fc DE |
736 | /* Code model selection. */ |
737 | sparc_cmodel = SPARC_DEFAULT_CMODEL; | |
4900aa61 | 738 | |
345a6161 DM |
739 | #ifdef SPARC_BI_ARCH |
740 | if (TARGET_ARCH32) | |
741 | sparc_cmodel = CM_32; | |
742 | #endif | |
743 | ||
a0a301fc DE |
744 | if (sparc_cmodel_string != NULL) |
745 | { | |
746 | if (TARGET_ARCH64) | |
747 | { | |
748 | for (cmodel = &cmodels[0]; cmodel->name; cmodel++) | |
749 | if (strcmp (sparc_cmodel_string, cmodel->name) == 0) | |
750 | break; | |
751 | if (cmodel->name == NULL) | |
752 | error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); | |
753 | else | |
754 | sparc_cmodel = cmodel->value; | |
755 | } | |
756 | else | |
757 | error ("-mcmodel= is not supported on 32 bit systems"); | |
758 | } | |
16956f6e | 759 | |
06063fa2 | 760 | fpu = target_flags & MASK_FPU; /* save current -mfpu status */ |
1f1406b4 | 761 | |
a0a301fc | 762 | /* Set the default CPU. */ |
16956f6e DE |
763 | for (def = &cpu_default[0]; def->name; ++def) |
764 | if (def->cpu == TARGET_CPU_DEFAULT) | |
765 | break; | |
f5f7d171 | 766 | gcc_assert (def->name); |
16956f6e DE |
767 | sparc_select[0].string = def->name; |
768 | ||
769 | for (sel = &sparc_select[0]; sel->name; ++sel) | |
61a55e8b | 770 | { |
16956f6e | 771 | if (sel->string) |
733f53f5 | 772 | { |
16956f6e DE |
773 | for (cpu = &cpu_table[0]; cpu->name; ++cpu) |
774 | if (! strcmp (sel->string, cpu->name)) | |
775 | { | |
776 | if (sel->set_tune_p) | |
777 | sparc_cpu = cpu->processor; | |
778 | ||
779 | if (sel->set_arch_p) | |
780 | { | |
781 | target_flags &= ~cpu->disable; | |
782 | target_flags |= cpu->enable; | |
783 | } | |
784 | break; | |
785 | } | |
786 | ||
787 | if (! cpu->name) | |
788 | error ("bad value (%s) for %s switch", sel->string, sel->name); | |
733f53f5 | 789 | } |
61a55e8b | 790 | } |
97da85b7 | 791 | |
1f1406b4 | 792 | /* If -mfpu or -mno-fpu was explicitly used, don't override with |
fe609b0f EB |
793 | the processor default. */ |
794 | if (fpu_option_set) | |
795 | target_flags = (target_flags & ~MASK_FPU) | fpu; | |
1f1406b4 | 796 | |
a5774a7d JJ |
797 | /* Don't allow -mvis if FPU is disabled. */ |
798 | if (! TARGET_FPU) | |
799 | target_flags &= ~MASK_VIS; | |
800 | ||
801 | /* -mvis assumes UltraSPARC+, so we are sure v9 instructions | |
802 | are available. | |
803 | -m64 also implies v9. */ | |
804 | if (TARGET_VIS || TARGET_ARCH64) | |
c4031a04 JJ |
805 | { |
806 | target_flags |= MASK_V9; | |
807 | target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); | |
808 | } | |
a5774a7d | 809 | |
16956f6e DE |
810 | /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ |
811 | if (TARGET_V9 && TARGET_ARCH32) | |
733f53f5 | 812 | target_flags |= MASK_DEPRECATED_V8_INSNS; |
61a55e8b | 813 | |
345a6161 DM |
814 | /* V8PLUS requires V9, makes no sense in 64 bit mode. */ |
815 | if (! TARGET_V9 || TARGET_ARCH64) | |
284d86e9 JC |
816 | target_flags &= ~MASK_V8PLUS; |
817 | ||
82d6b402 RH |
818 | /* Don't use stack biasing in 32 bit mode. */ |
819 | if (TARGET_ARCH32) | |
820 | target_flags &= ~MASK_STACK_BIAS; | |
4900aa61 | 821 | |
efa3896a | 822 | /* Supply a default value for align_functions. */ |
fae15c93 VM |
823 | if (align_functions == 0 |
824 | && (sparc_cpu == PROCESSOR_ULTRASPARC | |
4c837a1e | 825 | || sparc_cpu == PROCESSOR_ULTRASPARC3 |
9eeaed6e DM |
826 | || sparc_cpu == PROCESSOR_NIAGARA |
827 | || sparc_cpu == PROCESSOR_NIAGARA2)) | |
efa3896a | 828 | align_functions = 32; |
bf62bbf1 | 829 | |
82d6b402 RH |
830 | /* Validate PCC_STRUCT_RETURN. */ |
831 | if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) | |
832 | flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); | |
833 | ||
301d03af RS |
834 | /* Only use .uaxword when compiling for a 64-bit target. */ |
835 | if (!TARGET_ARCH64) | |
836 | targetm.asm_out.unaligned_op.di = NULL; | |
837 | ||
61a55e8b DE |
838 | /* Do various machine dependent initializations. */ |
839 | sparc_init_modes (); | |
5751a10b | 840 | |
1da4c3a7 | 841 | /* Acquire unique alias sets for our private stuff. */ |
9ac617d4 | 842 | sparc_sr_alias_set = new_alias_set (); |
1da4c3a7 | 843 | struct_value_alias_set = new_alias_set (); |
9ac617d4 | 844 | |
5751a10b JJ |
845 | /* Set up function hooks. */ |
846 | init_machine_status = sparc_init_machine_status; | |
18df6de9 DM |
847 | |
848 | switch (sparc_cpu) | |
849 | { | |
850 | case PROCESSOR_V7: | |
851 | case PROCESSOR_CYPRESS: | |
852 | sparc_costs = &cypress_costs; | |
853 | break; | |
854 | case PROCESSOR_V8: | |
855 | case PROCESSOR_SPARCLITE: | |
856 | case PROCESSOR_SUPERSPARC: | |
857 | sparc_costs = &supersparc_costs; | |
858 | break; | |
859 | case PROCESSOR_F930: | |
860 | case PROCESSOR_F934: | |
861 | case PROCESSOR_HYPERSPARC: | |
862 | case PROCESSOR_SPARCLITE86X: | |
863 | sparc_costs = &hypersparc_costs; | |
864 | break; | |
865 | case PROCESSOR_SPARCLET: | |
866 | case PROCESSOR_TSC701: | |
867 | sparc_costs = &sparclet_costs; | |
868 | break; | |
869 | case PROCESSOR_V9: | |
870 | case PROCESSOR_ULTRASPARC: | |
871 | sparc_costs = &ultrasparc_costs; | |
872 | break; | |
873 | case PROCESSOR_ULTRASPARC3: | |
874 | sparc_costs = &ultrasparc3_costs; | |
875 | break; | |
4c837a1e DM |
876 | case PROCESSOR_NIAGARA: |
877 | sparc_costs = &niagara_costs; | |
878 | break; | |
9eeaed6e DM |
879 | case PROCESSOR_NIAGARA2: |
880 | sparc_costs = &niagara2_costs; | |
881 | break; | |
18df6de9 | 882 | }; |
ed965309 JJ |
883 | |
884 | #ifdef TARGET_DEFAULT_LONG_DOUBLE_128 | |
885 | if (!(target_flags_explicit & MASK_LONG_DOUBLE_128)) | |
886 | target_flags |= MASK_LONG_DOUBLE_128; | |
887 | #endif | |
47eb5b32 ZD |
888 | |
889 | if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES)) | |
890 | set_param_value ("simultaneous-prefetches", | |
891 | ((sparc_cpu == PROCESSOR_ULTRASPARC | |
9eeaed6e DM |
892 | || sparc_cpu == PROCESSOR_NIAGARA |
893 | || sparc_cpu == PROCESSOR_NIAGARA2) | |
47eb5b32 ZD |
894 | ? 2 |
895 | : (sparc_cpu == PROCESSOR_ULTRASPARC3 | |
896 | ? 8 : 3))); | |
897 | if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE)) | |
4900aa61 | 898 | set_param_value ("l1-cache-line-size", |
47eb5b32 ZD |
899 | ((sparc_cpu == PROCESSOR_ULTRASPARC |
900 | || sparc_cpu == PROCESSOR_ULTRASPARC3 | |
9eeaed6e DM |
901 | || sparc_cpu == PROCESSOR_NIAGARA |
902 | || sparc_cpu == PROCESSOR_NIAGARA2) | |
47eb5b32 | 903 | ? 64 : 32)); |
61a55e8b DE |
904 | } |
905 | \f | |
cd5fb1ee DE |
906 | /* Miscellaneous utilities. */ |
907 | ||
908 | /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move | |
909 | or branch on register contents instructions. */ | |
910 | ||
911 | int | |
fc27d102 | 912 | v9_regcmp_p (enum rtx_code code) |
cd5fb1ee DE |
913 | { |
914 | return (code == EQ || code == NE || code == GE || code == LT | |
915 | || code == LE || code == GT); | |
916 | } | |
bfd6bc60 | 917 | |
62190128 DM |
918 | /* Nonzero if OP is a floating point constant which can |
919 | be loaded into an integer register using a single | |
920 | sethi instruction. */ | |
921 | ||
922 | int | |
fc27d102 | 923 | fp_sethi_p (rtx op) |
62190128 DM |
924 | { |
925 | if (GET_CODE (op) == CONST_DOUBLE) | |
926 | { | |
927 | REAL_VALUE_TYPE r; | |
928 | long i; | |
929 | ||
930 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
62190128 | 931 | REAL_VALUE_TO_TARGET_SINGLE (r, i); |
9a9e266b | 932 | return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i); |
62190128 DM |
933 | } |
934 | ||
935 | return 0; | |
936 | } | |
937 | ||
938 | /* Nonzero if OP is a floating point constant which can | |
939 | be loaded into an integer register using a single | |
940 | mov instruction. */ | |
941 | ||
942 | int | |
fc27d102 | 943 | fp_mov_p (rtx op) |
62190128 DM |
944 | { |
945 | if (GET_CODE (op) == CONST_DOUBLE) | |
946 | { | |
947 | REAL_VALUE_TYPE r; | |
948 | long i; | |
949 | ||
950 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
62190128 | 951 | REAL_VALUE_TO_TARGET_SINGLE (r, i); |
9a9e266b | 952 | return SPARC_SIMM13_P (i); |
62190128 DM |
953 | } |
954 | ||
955 | return 0; | |
956 | } | |
957 | ||
958 | /* Nonzero if OP is a floating point constant which can | |
959 | be loaded into an integer register using a high/losum | |
960 | instruction sequence. */ | |
961 | ||
962 | int | |
fc27d102 | 963 | fp_high_losum_p (rtx op) |
62190128 DM |
964 | { |
965 | /* The constraints calling this should only be in | |
966 | SFmode move insns, so any constant which cannot | |
967 | be moved using a single insn will do. */ | |
968 | if (GET_CODE (op) == CONST_DOUBLE) | |
969 | { | |
970 | REAL_VALUE_TYPE r; | |
971 | long i; | |
972 | ||
973 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
62190128 | 974 | REAL_VALUE_TO_TARGET_SINGLE (r, i); |
9a9e266b | 975 | return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i); |
62190128 DM |
976 | } |
977 | ||
978 | return 0; | |
979 | } | |
980 | ||
bea5071f EB |
981 | /* Expand a move instruction. Return true if all work is done. */ |
982 | ||
983 | bool | |
984 | sparc_expand_move (enum machine_mode mode, rtx *operands) | |
985 | { | |
986 | /* Handle sets of MEM first. */ | |
987 | if (GET_CODE (operands[0]) == MEM) | |
988 | { | |
989 | /* 0 is a register (or a pair of registers) on SPARC. */ | |
990 | if (register_or_zero_operand (operands[1], mode)) | |
991 | return false; | |
992 | ||
993 | if (!reload_in_progress) | |
994 | { | |
995 | operands[0] = validize_mem (operands[0]); | |
996 | operands[1] = force_reg (mode, operands[1]); | |
997 | } | |
998 | } | |
999 | ||
1000 | /* Fixup TLS cases. */ | |
38fc66ba EB |
1001 | if (TARGET_HAVE_TLS |
1002 | && CONSTANT_P (operands[1]) | |
38fc66ba EB |
1003 | && sparc_tls_referenced_p (operands [1])) |
1004 | { | |
208384fd EB |
1005 | operands[1] = legitimize_tls_address (operands[1]); |
1006 | return false; | |
38fc66ba | 1007 | } |
4900aa61 | 1008 | |
bea5071f EB |
1009 | /* Fixup PIC cases. */ |
1010 | if (flag_pic && CONSTANT_P (operands[1])) | |
1011 | { | |
1012 | if (pic_address_needs_scratch (operands[1])) | |
208384fd | 1013 | operands[1] = legitimize_pic_address (operands[1], NULL_RTX); |
bea5071f | 1014 | |
1910440e RS |
1015 | /* VxWorks does not impose a fixed gap between segments; the run-time |
1016 | gap can be different from the object-file gap. We therefore can't | |
1017 | assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we | |
1018 | are absolutely sure that X is in the same segment as the GOT. | |
1019 | Unfortunately, the flexibility of linker scripts means that we | |
1020 | can't be sure of that in general, so assume that _G_O_T_-relative | |
1021 | accesses are never valid on VxWorks. */ | |
1022 | if (GET_CODE (operands[1]) == LABEL_REF && !TARGET_VXWORKS_RTP) | |
bea5071f | 1023 | { |
1910440e RS |
1024 | if (mode == SImode) |
1025 | { | |
1026 | emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1])); | |
1027 | return true; | |
1028 | } | |
bea5071f | 1029 | |
1910440e RS |
1030 | if (mode == DImode) |
1031 | { | |
1032 | gcc_assert (TARGET_ARCH64); | |
1033 | emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1])); | |
1034 | return true; | |
1035 | } | |
bea5071f EB |
1036 | } |
1037 | ||
1038 | if (symbolic_operand (operands[1], mode)) | |
1039 | { | |
1040 | operands[1] = legitimize_pic_address (operands[1], | |
208384fd EB |
1041 | reload_in_progress |
1042 | ? operands[0] : NULL_RTX); | |
bea5071f EB |
1043 | return false; |
1044 | } | |
1045 | } | |
1046 | ||
1047 | /* If we are trying to toss an integer constant into FP registers, | |
1048 | or loading a FP or vector constant, force it into memory. */ | |
1049 | if (CONSTANT_P (operands[1]) | |
1050 | && REG_P (operands[0]) | |
1051 | && (SPARC_FP_REG_P (REGNO (operands[0])) | |
1052 | || SCALAR_FLOAT_MODE_P (mode) | |
1053 | || VECTOR_MODE_P (mode))) | |
1054 | { | |
1055 | /* emit_group_store will send such bogosity to us when it is | |
1056 | not storing directly into memory. So fix this up to avoid | |
1057 | crashes in output_constant_pool. */ | |
1058 | if (operands [1] == const0_rtx) | |
1059 | operands[1] = CONST0_RTX (mode); | |
1060 | ||
1061 | /* We can clear FP registers if TARGET_VIS, and always other regs. */ | |
1062 | if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG) | |
1063 | && const_zero_operand (operands[1], mode)) | |
1064 | return false; | |
1065 | ||
1066 | if (REGNO (operands[0]) < SPARC_FIRST_FP_REG | |
1067 | /* We are able to build any SF constant in integer registers | |
1068 | with at most 2 instructions. */ | |
1069 | && (mode == SFmode | |
1070 | /* And any DF constant in integer registers. */ | |
1071 | || (mode == DFmode | |
1072 | && (reload_completed || reload_in_progress)))) | |
1073 | return false; | |
1074 | ||
1075 | operands[1] = force_const_mem (mode, operands[1]); | |
1076 | if (!reload_in_progress) | |
1077 | operands[1] = validize_mem (operands[1]); | |
1078 | return false; | |
1079 | } | |
1080 | ||
1081 | /* Accept non-constants and valid constants unmodified. */ | |
1082 | if (!CONSTANT_P (operands[1]) | |
1083 | || GET_CODE (operands[1]) == HIGH | |
1084 | || input_operand (operands[1], mode)) | |
1085 | return false; | |
1086 | ||
1087 | switch (mode) | |
1088 | { | |
1089 | case QImode: | |
1090 | /* All QImode constants require only one insn, so proceed. */ | |
1091 | break; | |
1092 | ||
1093 | case HImode: | |
1094 | case SImode: | |
1095 | sparc_emit_set_const32 (operands[0], operands[1]); | |
1096 | return true; | |
1097 | ||
1098 | case DImode: | |
1099 | /* input_operand should have filtered out 32-bit mode. */ | |
1100 | sparc_emit_set_const64 (operands[0], operands[1]); | |
1101 | return true; | |
4900aa61 | 1102 | |
bea5071f EB |
1103 | default: |
1104 | gcc_unreachable (); | |
1105 | } | |
1106 | ||
1107 | return false; | |
1108 | } | |
1109 | ||
1110 | /* Load OP1, a 32-bit constant, into OP0, a register. | |
1111 | We know it can't be done in one insn when we get | |
1112 | here, the move expander guarantees this. */ | |
1113 | ||
e0d80184 | 1114 | void |
fc27d102 | 1115 | sparc_emit_set_const32 (rtx op0, rtx op1) |
e0d80184 DM |
1116 | { |
1117 | enum machine_mode mode = GET_MODE (op0); | |
1118 | rtx temp; | |
1119 | ||
e0d80184 DM |
1120 | if (reload_in_progress || reload_completed) |
1121 | temp = op0; | |
284d86e9 | 1122 | else |
e0d80184 DM |
1123 | temp = gen_reg_rtx (mode); |
1124 | ||
71648202 DM |
1125 | if (GET_CODE (op1) == CONST_INT) |
1126 | { | |
0e5d569c EB |
1127 | gcc_assert (!small_int_operand (op1, mode) |
1128 | && !const_high_operand (op1, mode)); | |
1129 | ||
71648202 DM |
1130 | /* Emit them as real moves instead of a HIGH/LO_SUM, |
1131 | this way CSE can see everything and reuse intermediate | |
1132 | values if it wants. */ | |
0e5d569c EB |
1133 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
1134 | GEN_INT (INTVAL (op1) | |
1135 | & ~(HOST_WIDE_INT)0x3ff))); | |
f2827474 | 1136 | |
71648202 DM |
1137 | emit_insn (gen_rtx_SET (VOIDmode, |
1138 | op0, | |
f2827474 | 1139 | gen_rtx_IOR (mode, temp, |
71648202 DM |
1140 | GEN_INT (INTVAL (op1) & 0x3ff)))); |
1141 | } | |
1142 | else | |
1143 | { | |
1144 | /* A symbol, emit in the traditional way. */ | |
f2827474 RK |
1145 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
1146 | gen_rtx_HIGH (mode, op1))); | |
71648202 | 1147 | emit_insn (gen_rtx_SET (VOIDmode, |
f2827474 | 1148 | op0, gen_rtx_LO_SUM (mode, temp, op1))); |
71648202 | 1149 | } |
e0d80184 DM |
1150 | } |
1151 | ||
1d511ed5 | 1152 | /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register. |
0e40b5f2 | 1153 | If TEMP is nonzero, we are forbidden to use any other scratch |
1d511ed5 EB |
1154 | registers. Otherwise, we are allowed to generate them as needed. |
1155 | ||
1156 | Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY | |
1157 | or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */ | |
bea5071f | 1158 | |
e0d80184 | 1159 | void |
1d511ed5 | 1160 | sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp) |
e0d80184 | 1161 | { |
1d511ed5 EB |
1162 | rtx temp1, temp2, temp3, temp4, temp5; |
1163 | rtx ti_temp = 0; | |
3968de80 | 1164 | |
1d511ed5 | 1165 | if (temp && GET_MODE (temp) == TImode) |
3968de80 | 1166 | { |
1d511ed5 EB |
1167 | ti_temp = temp; |
1168 | temp = gen_rtx_REG (DImode, REGNO (temp)); | |
3968de80 DD |
1169 | } |
1170 | ||
1d511ed5 | 1171 | /* SPARC-V9 code-model support. */ |
e0d80184 | 1172 | switch (sparc_cmodel) |
284d86e9 | 1173 | { |
e0d80184 DM |
1174 | case CM_MEDLOW: |
1175 | /* The range spanned by all instructions in the object is less | |
1176 | than 2^31 bytes (2GB) and the distance from any instruction | |
1177 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1178 | than 2^31 bytes (2GB). | |
ab835497 | 1179 | |
e0d80184 DM |
1180 | The executable must be in the low 4TB of the virtual address |
1181 | space. | |
61a55e8b | 1182 | |
1d511ed5 EB |
1183 | sethi %hi(symbol), %temp1 |
1184 | or %temp1, %lo(symbol), %reg */ | |
1185 | if (temp) | |
1186 | temp1 = temp; /* op0 is allowed. */ | |
1187 | else | |
1188 | temp1 = gen_reg_rtx (DImode); | |
1189 | ||
9208e4b2 DM |
1190 | emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); |
1191 | emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); | |
e0d80184 | 1192 | break; |
61a55e8b | 1193 | |
e0d80184 DM |
1194 | case CM_MEDMID: |
1195 | /* The range spanned by all instructions in the object is less | |
1196 | than 2^31 bytes (2GB) and the distance from any instruction | |
1197 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1198 | than 2^31 bytes (2GB). | |
1199 | ||
1200 | The executable must be in the low 16TB of the virtual address | |
1201 | space. | |
1202 | ||
1203 | sethi %h44(symbol), %temp1 | |
1204 | or %temp1, %m44(symbol), %temp2 | |
1205 | sllx %temp2, 12, %temp3 | |
1206 | or %temp3, %l44(symbol), %reg */ | |
1d511ed5 EB |
1207 | if (temp) |
1208 | { | |
1209 | temp1 = op0; | |
1210 | temp2 = op0; | |
1211 | temp3 = temp; /* op0 is allowed. */ | |
1212 | } | |
1213 | else | |
1214 | { | |
1215 | temp1 = gen_reg_rtx (DImode); | |
1216 | temp2 = gen_reg_rtx (DImode); | |
1217 | temp3 = gen_reg_rtx (DImode); | |
1218 | } | |
1219 | ||
1220 | emit_insn (gen_seth44 (temp1, op1)); | |
1221 | emit_insn (gen_setm44 (temp2, temp1, op1)); | |
1222 | emit_insn (gen_rtx_SET (VOIDmode, temp3, | |
1223 | gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12)))); | |
1224 | emit_insn (gen_setl44 (op0, temp3, op1)); | |
e0d80184 | 1225 | break; |
61a55e8b | 1226 | |
e0d80184 DM |
1227 | case CM_MEDANY: |
1228 | /* The range spanned by all instructions in the object is less | |
1229 | than 2^31 bytes (2GB) and the distance from any instruction | |
1230 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1231 | than 2^31 bytes (2GB). | |
1232 | ||
1233 | The executable can be placed anywhere in the virtual address | |
1234 | space. | |
1235 | ||
1236 | sethi %hh(symbol), %temp1 | |
1237 | sethi %lm(symbol), %temp2 | |
1238 | or %temp1, %hm(symbol), %temp3 | |
1d511ed5 EB |
1239 | sllx %temp3, 32, %temp4 |
1240 | or %temp4, %temp2, %temp5 | |
1241 | or %temp5, %lo(symbol), %reg */ | |
1242 | if (temp) | |
3968de80 | 1243 | { |
1d511ed5 EB |
1244 | /* It is possible that one of the registers we got for operands[2] |
1245 | might coincide with that of operands[0] (which is why we made | |
1246 | it TImode). Pick the other one to use as our scratch. */ | |
1247 | if (rtx_equal_p (temp, op0)) | |
1248 | { | |
f5f7d171 JM |
1249 | gcc_assert (ti_temp); |
1250 | temp = gen_rtx_REG (DImode, REGNO (temp) + 1); | |
1d511ed5 EB |
1251 | } |
1252 | temp1 = op0; | |
1253 | temp2 = temp; /* op0 is _not_ allowed, see above. */ | |
1254 | temp3 = op0; | |
1255 | temp4 = op0; | |
1256 | temp5 = op0; | |
1257 | } | |
1258 | else | |
1259 | { | |
1260 | temp1 = gen_reg_rtx (DImode); | |
1261 | temp2 = gen_reg_rtx (DImode); | |
1262 | temp3 = gen_reg_rtx (DImode); | |
1263 | temp4 = gen_reg_rtx (DImode); | |
1264 | temp5 = gen_reg_rtx (DImode); | |
3968de80 | 1265 | } |
61a55e8b | 1266 | |
1d511ed5 EB |
1267 | emit_insn (gen_sethh (temp1, op1)); |
1268 | emit_insn (gen_setlm (temp2, op1)); | |
1269 | emit_insn (gen_sethm (temp3, temp1, op1)); | |
1270 | emit_insn (gen_rtx_SET (VOIDmode, temp4, | |
1271 | gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32)))); | |
1272 | emit_insn (gen_rtx_SET (VOIDmode, temp5, | |
1273 | gen_rtx_PLUS (DImode, temp4, temp2))); | |
1274 | emit_insn (gen_setlo (op0, temp5, op1)); | |
e0d80184 | 1275 | break; |
61a55e8b | 1276 | |
e0d80184 DM |
1277 | case CM_EMBMEDANY: |
1278 | /* Old old old backwards compatibility kruft here. | |
1279 | Essentially it is MEDLOW with a fixed 64-bit | |
1280 | virtual base added to all data segment addresses. | |
1281 | Text-segment stuff is computed like MEDANY, we can't | |
1282 | reuse the code above because the relocation knobs | |
1283 | look different. | |
1284 | ||
1285 | Data segment: sethi %hi(symbol), %temp1 | |
1d511ed5 EB |
1286 | add %temp1, EMBMEDANY_BASE_REG, %temp2 |
1287 | or %temp2, %lo(symbol), %reg */ | |
e0d80184 DM |
1288 | if (data_segment_operand (op1, GET_MODE (op1))) |
1289 | { | |
1d511ed5 EB |
1290 | if (temp) |
1291 | { | |
1292 | temp1 = temp; /* op0 is allowed. */ | |
1293 | temp2 = op0; | |
1294 | } | |
1295 | else | |
1296 | { | |
1297 | temp1 = gen_reg_rtx (DImode); | |
1298 | temp2 = gen_reg_rtx (DImode); | |
1299 | } | |
1300 | ||
e0d80184 | 1301 | emit_insn (gen_embmedany_sethi (temp1, op1)); |
1d511ed5 EB |
1302 | emit_insn (gen_embmedany_brsum (temp2, temp1)); |
1303 | emit_insn (gen_embmedany_losum (op0, temp2, op1)); | |
e0d80184 | 1304 | } |
1d511ed5 EB |
1305 | |
1306 | /* Text segment: sethi %uhi(symbol), %temp1 | |
1307 | sethi %hi(symbol), %temp2 | |
1308 | or %temp1, %ulo(symbol), %temp3 | |
1309 | sllx %temp3, 32, %temp4 | |
1310 | or %temp4, %temp2, %temp5 | |
1311 | or %temp5, %lo(symbol), %reg */ | |
e0d80184 DM |
1312 | else |
1313 | { | |
1d511ed5 | 1314 | if (temp) |
3968de80 | 1315 | { |
1d511ed5 EB |
1316 | /* It is possible that one of the registers we got for operands[2] |
1317 | might coincide with that of operands[0] (which is why we made | |
1318 | it TImode). Pick the other one to use as our scratch. */ | |
1319 | if (rtx_equal_p (temp, op0)) | |
1320 | { | |
f5f7d171 JM |
1321 | gcc_assert (ti_temp); |
1322 | temp = gen_rtx_REG (DImode, REGNO (temp) + 1); | |
1d511ed5 EB |
1323 | } |
1324 | temp1 = op0; | |
1325 | temp2 = temp; /* op0 is _not_ allowed, see above. */ | |
1326 | temp3 = op0; | |
1327 | temp4 = op0; | |
1328 | temp5 = op0; | |
1329 | } | |
1330 | else | |
1331 | { | |
1332 | temp1 = gen_reg_rtx (DImode); | |
1333 | temp2 = gen_reg_rtx (DImode); | |
1334 | temp3 = gen_reg_rtx (DImode); | |
1335 | temp4 = gen_reg_rtx (DImode); | |
1336 | temp5 = gen_reg_rtx (DImode); | |
3968de80 | 1337 | } |
61a55e8b | 1338 | |
1d511ed5 EB |
1339 | emit_insn (gen_embmedany_textuhi (temp1, op1)); |
1340 | emit_insn (gen_embmedany_texthi (temp2, op1)); | |
1341 | emit_insn (gen_embmedany_textulo (temp3, temp1, op1)); | |
1342 | emit_insn (gen_rtx_SET (VOIDmode, temp4, | |
1343 | gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32)))); | |
1344 | emit_insn (gen_rtx_SET (VOIDmode, temp5, | |
1345 | gen_rtx_PLUS (DImode, temp4, temp2))); | |
1346 | emit_insn (gen_embmedany_textlo (op0, temp5, op1)); | |
e0d80184 DM |
1347 | } |
1348 | break; | |
1349 | ||
1350 | default: | |
f5f7d171 | 1351 | gcc_unreachable (); |
e0d80184 DM |
1352 | } |
1353 | } | |
1354 | ||
0e5d569c EB |
1355 | #if HOST_BITS_PER_WIDE_INT == 32 |
1356 | void | |
1357 | sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED) | |
1358 | { | |
1359 | gcc_unreachable (); | |
1360 | } | |
1361 | #else | |
9208e4b2 DM |
1362 | /* These avoid problems when cross compiling. If we do not |
1363 | go through all this hair then the optimizer will see | |
1364 | invalid REG_EQUAL notes or in some cases none at all. */ | |
9bb3323d | 1365 | static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT); |
e80d5f80 KG |
1366 | static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT); |
1367 | static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT); | |
1368 | static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT); | |
9208e4b2 | 1369 | |
9208e4b2 DM |
1370 | /* The optimizer is not to assume anything about exactly |
1371 | which bits are set for a HIGH, they are unspecified. | |
1372 | Unfortunately this leads to many missed optimizations | |
1373 | during CSE. We mask out the non-HIGH bits, and matches | |
1374 | a plain movdi, to alleviate this problem. */ | |
9bb3323d EB |
1375 | static rtx |
1376 | gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val) | |
9208e4b2 | 1377 | { |
9bb3323d | 1378 | return gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff)); |
9208e4b2 | 1379 | } |
2a01c939 | 1380 | |
e0d80184 | 1381 | static rtx |
fc27d102 | 1382 | gen_safe_SET64 (rtx dest, HOST_WIDE_INT val) |
61a55e8b | 1383 | { |
0e5d569c | 1384 | return gen_rtx_SET (VOIDmode, dest, GEN_INT (val)); |
9208e4b2 DM |
1385 | } |
1386 | ||
1387 | static rtx | |
fc27d102 | 1388 | gen_safe_OR64 (rtx src, HOST_WIDE_INT val) |
9208e4b2 | 1389 | { |
0e5d569c | 1390 | return gen_rtx_IOR (DImode, src, GEN_INT (val)); |
9208e4b2 DM |
1391 | } |
1392 | ||
1393 | static rtx | |
fc27d102 | 1394 | gen_safe_XOR64 (rtx src, HOST_WIDE_INT val) |
9208e4b2 | 1395 | { |
0e5d569c | 1396 | return gen_rtx_XOR (DImode, src, GEN_INT (val)); |
e0d80184 | 1397 | } |
61a55e8b | 1398 | |
e0d80184 DM |
1399 | /* Worker routines for 64-bit constant formation on arch64. |
1400 | One of the key things to be doing in these emissions is | |
1401 | to create as many temp REGs as possible. This makes it | |
1402 | possible for half-built constants to be used later when | |
1403 | such values are similar to something required later on. | |
1404 | Without doing this, the optimizer cannot see such | |
1405 | opportunities. */ | |
2a01c939 | 1406 | |
e80d5f80 KG |
1407 | static void sparc_emit_set_const64_quick1 (rtx, rtx, |
1408 | unsigned HOST_WIDE_INT, int); | |
2a01c939 | 1409 | |
e0d80184 | 1410 | static void |
fc27d102 KG |
1411 | sparc_emit_set_const64_quick1 (rtx op0, rtx temp, |
1412 | unsigned HOST_WIDE_INT low_bits, int is_neg) | |
e0d80184 | 1413 | { |
2a01c939 | 1414 | unsigned HOST_WIDE_INT high_bits; |
a9e27770 | 1415 | |
e0d80184 | 1416 | if (is_neg) |
2a01c939 | 1417 | high_bits = (~low_bits) & 0xffffffff; |
31bc9eba | 1418 | else |
e0d80184 | 1419 | high_bits = low_bits; |
31bc9eba | 1420 | |
9bb3323d | 1421 | emit_insn (gen_safe_HIGH64 (temp, high_bits)); |
e0d80184 | 1422 | if (!is_neg) |
5108f3e5 DM |
1423 | { |
1424 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1425 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
1426 | } | |
e0d80184 | 1427 | else |
5108f3e5 DM |
1428 | { |
1429 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
1430 | instead. This way the combiner will notice logical operations | |
1431 | such as ANDN later on and substitute. */ | |
1432 | if ((low_bits & 0x3ff) == 0x3ff) | |
1433 | { | |
1434 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1435 | gen_rtx_NOT (DImode, temp))); | |
1436 | } | |
1437 | else | |
1438 | { | |
1439 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1440 | gen_safe_XOR64 (temp, | |
9e0625a3 AO |
1441 | (-(HOST_WIDE_INT)0x400 |
1442 | | (low_bits & 0x3ff))))); | |
5108f3e5 DM |
1443 | } |
1444 | } | |
e0d80184 | 1445 | } |
61a55e8b | 1446 | |
e80d5f80 KG |
1447 | static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT, |
1448 | unsigned HOST_WIDE_INT, int); | |
2a01c939 | 1449 | |
e0d80184 | 1450 | static void |
fc27d102 KG |
1451 | sparc_emit_set_const64_quick2 (rtx op0, rtx temp, |
1452 | unsigned HOST_WIDE_INT high_bits, | |
1453 | unsigned HOST_WIDE_INT low_immediate, | |
1454 | int shift_count) | |
e0d80184 DM |
1455 | { |
1456 | rtx temp2 = op0; | |
61a55e8b | 1457 | |
e0d80184 DM |
1458 | if ((high_bits & 0xfffffc00) != 0) |
1459 | { | |
9bb3323d | 1460 | emit_insn (gen_safe_HIGH64 (temp, high_bits)); |
e0d80184 | 1461 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 DM |
1462 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1463 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
61a55e8b | 1464 | else |
e0d80184 | 1465 | temp2 = temp; |
61a55e8b DE |
1466 | } |
1467 | else | |
1468 | { | |
f710f868 | 1469 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 DM |
1470 | temp2 = temp; |
1471 | } | |
61a55e8b | 1472 | |
80ffc95e | 1473 | /* Now shift it up into place. */ |
9208e4b2 | 1474 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1475 | gen_rtx_ASHIFT (DImode, temp2, |
1476 | GEN_INT (shift_count)))); | |
61a55e8b | 1477 | |
e0d80184 DM |
1478 | /* If there is a low immediate part piece, finish up by |
1479 | putting that in as well. */ | |
1480 | if (low_immediate != 0) | |
9208e4b2 DM |
1481 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1482 | gen_safe_OR64 (op0, low_immediate))); | |
ab835497 RK |
1483 | } |
1484 | ||
e80d5f80 KG |
1485 | static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT, |
1486 | unsigned HOST_WIDE_INT); | |
2a01c939 | 1487 | |
e0d80184 DM |
1488 | /* Full 64-bit constant decomposition. Even though this is the |
1489 | 'worst' case, we still optimize a few things away. */ | |
1490 | static void | |
fc27d102 KG |
1491 | sparc_emit_set_const64_longway (rtx op0, rtx temp, |
1492 | unsigned HOST_WIDE_INT high_bits, | |
1493 | unsigned HOST_WIDE_INT low_bits) | |
ab835497 | 1494 | { |
e0d80184 | 1495 | rtx sub_temp; |
4bf7135b | 1496 | |
e0d80184 DM |
1497 | if (reload_in_progress || reload_completed) |
1498 | sub_temp = op0; | |
1499 | else | |
1500 | sub_temp = gen_reg_rtx (DImode); | |
1501 | ||
1502 | if ((high_bits & 0xfffffc00) != 0) | |
1503 | { | |
9bb3323d | 1504 | emit_insn (gen_safe_HIGH64 (temp, high_bits)); |
e0d80184 | 1505 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 | 1506 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1507 | sub_temp, |
9208e4b2 | 1508 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); |
e0d80184 DM |
1509 | else |
1510 | sub_temp = temp; | |
1511 | } | |
1512 | else | |
ab835497 | 1513 | { |
f710f868 | 1514 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 | 1515 | sub_temp = temp; |
ab835497 | 1516 | } |
4bf7135b | 1517 | |
e0d80184 | 1518 | if (!reload_in_progress && !reload_completed) |
284d86e9 | 1519 | { |
e0d80184 DM |
1520 | rtx temp2 = gen_reg_rtx (DImode); |
1521 | rtx temp3 = gen_reg_rtx (DImode); | |
1522 | rtx temp4 = gen_reg_rtx (DImode); | |
284d86e9 | 1523 | |
9208e4b2 | 1524 | emit_insn (gen_rtx_SET (VOIDmode, temp4, |
e0d80184 DM |
1525 | gen_rtx_ASHIFT (DImode, sub_temp, |
1526 | GEN_INT (32)))); | |
4bf7135b | 1527 | |
9bb3323d | 1528 | emit_insn (gen_safe_HIGH64 (temp2, low_bits)); |
e0d80184 | 1529 | if ((low_bits & ~0xfffffc00) != 0) |
f710f868 DM |
1530 | { |
1531 | emit_insn (gen_rtx_SET (VOIDmode, temp3, | |
1532 | gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); | |
1533 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1534 | gen_rtx_PLUS (DImode, temp4, temp3))); | |
1535 | } | |
1536 | else | |
1537 | { | |
1538 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1539 | gen_rtx_PLUS (DImode, temp4, temp2))); | |
1540 | } | |
284d86e9 | 1541 | } |
e0d80184 DM |
1542 | else |
1543 | { | |
9208e4b2 DM |
1544 | rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); |
1545 | rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); | |
1546 | rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); | |
e0d80184 | 1547 | int to_shift = 12; |
284d86e9 | 1548 | |
e0d80184 DM |
1549 | /* We are in the middle of reload, so this is really |
1550 | painful. However we do still make an attempt to | |
5108f3e5 | 1551 | avoid emitting truly stupid code. */ |
e0d80184 DM |
1552 | if (low1 != const0_rtx) |
1553 | { | |
9208e4b2 | 1554 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1555 | gen_rtx_ASHIFT (DImode, sub_temp, |
2a01c939 | 1556 | GEN_INT (to_shift)))); |
9208e4b2 | 1557 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1558 | gen_rtx_IOR (DImode, op0, low1))); |
1559 | sub_temp = op0; | |
1560 | to_shift = 12; | |
1561 | } | |
1562 | else | |
1563 | { | |
1564 | to_shift += 12; | |
1565 | } | |
1566 | if (low2 != const0_rtx) | |
1567 | { | |
9208e4b2 | 1568 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1569 | gen_rtx_ASHIFT (DImode, sub_temp, |
1570 | GEN_INT (to_shift)))); | |
9208e4b2 | 1571 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1572 | gen_rtx_IOR (DImode, op0, low2))); |
1573 | sub_temp = op0; | |
1574 | to_shift = 8; | |
1575 | } | |
1576 | else | |
1577 | { | |
1578 | to_shift += 8; | |
1579 | } | |
9208e4b2 | 1580 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1581 | gen_rtx_ASHIFT (DImode, sub_temp, |
1582 | GEN_INT (to_shift)))); | |
1583 | if (low3 != const0_rtx) | |
9208e4b2 | 1584 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1585 | gen_rtx_IOR (DImode, op0, low3))); |
80ffc95e | 1586 | /* phew... */ |
e0d80184 | 1587 | } |
284d86e9 JC |
1588 | } |
1589 | ||
80ffc95e | 1590 | /* Analyze a 64-bit constant for certain properties. */ |
e80d5f80 KG |
1591 | static void analyze_64bit_constant (unsigned HOST_WIDE_INT, |
1592 | unsigned HOST_WIDE_INT, | |
1593 | int *, int *, int *); | |
2a01c939 | 1594 | |
e0d80184 | 1595 | static void |
fc27d102 KG |
1596 | analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits, |
1597 | unsigned HOST_WIDE_INT low_bits, | |
1598 | int *hbsp, int *lbsp, int *abbasp) | |
ab835497 | 1599 | { |
e0d80184 DM |
1600 | int lowest_bit_set, highest_bit_set, all_bits_between_are_set; |
1601 | int i; | |
ab835497 | 1602 | |
e0d80184 DM |
1603 | lowest_bit_set = highest_bit_set = -1; |
1604 | i = 0; | |
1605 | do | |
ab835497 | 1606 | { |
e0d80184 DM |
1607 | if ((lowest_bit_set == -1) |
1608 | && ((low_bits >> i) & 1)) | |
1609 | lowest_bit_set = i; | |
1610 | if ((highest_bit_set == -1) | |
1611 | && ((high_bits >> (32 - i - 1)) & 1)) | |
1612 | highest_bit_set = (64 - i - 1); | |
1613 | } | |
1614 | while (++i < 32 | |
1615 | && ((highest_bit_set == -1) | |
1616 | || (lowest_bit_set == -1))); | |
1617 | if (i == 32) | |
1618 | { | |
1619 | i = 0; | |
1620 | do | |
ab835497 | 1621 | { |
e0d80184 DM |
1622 | if ((lowest_bit_set == -1) |
1623 | && ((high_bits >> i) & 1)) | |
1624 | lowest_bit_set = i + 32; | |
1625 | if ((highest_bit_set == -1) | |
1626 | && ((low_bits >> (32 - i - 1)) & 1)) | |
1627 | highest_bit_set = 32 - i - 1; | |
ab835497 | 1628 | } |
e0d80184 DM |
1629 | while (++i < 32 |
1630 | && ((highest_bit_set == -1) | |
1631 | || (lowest_bit_set == -1))); | |
1632 | } | |
1633 | /* If there are no bits set this should have gone out | |
1634 | as one instruction! */ | |
f5f7d171 | 1635 | gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1); |
e0d80184 DM |
1636 | all_bits_between_are_set = 1; |
1637 | for (i = lowest_bit_set; i <= highest_bit_set; i++) | |
1638 | { | |
1639 | if (i < 32) | |
1640 | { | |
1641 | if ((low_bits & (1 << i)) != 0) | |
1642 | continue; | |
1643 | } | |
1644 | else | |
1645 | { | |
1646 | if ((high_bits & (1 << (i - 32))) != 0) | |
1647 | continue; | |
1648 | } | |
1649 | all_bits_between_are_set = 0; | |
1650 | break; | |
ab835497 | 1651 | } |
e0d80184 DM |
1652 | *hbsp = highest_bit_set; |
1653 | *lbsp = lowest_bit_set; | |
1654 | *abbasp = all_bits_between_are_set; | |
ab835497 | 1655 | } |
6a4bb1fa | 1656 | |
e80d5f80 | 1657 | static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT); |
2a01c939 | 1658 | |
e0d80184 | 1659 | static int |
fc27d102 KG |
1660 | const64_is_2insns (unsigned HOST_WIDE_INT high_bits, |
1661 | unsigned HOST_WIDE_INT low_bits) | |
e0d80184 DM |
1662 | { |
1663 | int highest_bit_set, lowest_bit_set, all_bits_between_are_set; | |
284d86e9 | 1664 | |
e0d80184 | 1665 | if (high_bits == 0 |
f451b552 | 1666 | || high_bits == 0xffffffff) |
e0d80184 | 1667 | return 1; |
6a4bb1fa | 1668 | |
e0d80184 DM |
1669 | analyze_64bit_constant (high_bits, low_bits, |
1670 | &highest_bit_set, &lowest_bit_set, | |
1671 | &all_bits_between_are_set); | |
6a4bb1fa | 1672 | |
f710f868 DM |
1673 | if ((highest_bit_set == 63 |
1674 | || lowest_bit_set == 0) | |
e0d80184 DM |
1675 | && all_bits_between_are_set != 0) |
1676 | return 1; | |
6a4bb1fa | 1677 | |
9208e4b2 DM |
1678 | if ((highest_bit_set - lowest_bit_set) < 21) |
1679 | return 1; | |
1680 | ||
6a4bb1fa DE |
1681 | return 0; |
1682 | } | |
1683 | ||
e80d5f80 KG |
1684 | static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT, |
1685 | unsigned HOST_WIDE_INT, | |
1686 | int, int); | |
2a01c939 DM |
1687 | |
1688 | static unsigned HOST_WIDE_INT | |
fc27d102 KG |
1689 | create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits, |
1690 | unsigned HOST_WIDE_INT low_bits, | |
1691 | int lowest_bit_set, int shift) | |
ab835497 | 1692 | { |
f710f868 | 1693 | HOST_WIDE_INT hi, lo; |
ab835497 | 1694 | |
e0d80184 DM |
1695 | if (lowest_bit_set < 32) |
1696 | { | |
1697 | lo = (low_bits >> lowest_bit_set) << shift; | |
1698 | hi = ((high_bits << (32 - lowest_bit_set)) << shift); | |
1699 | } | |
1700 | else | |
1701 | { | |
1702 | lo = 0; | |
1703 | hi = ((high_bits >> (lowest_bit_set - 32)) << shift); | |
1704 | } | |
f5f7d171 | 1705 | gcc_assert (! (hi & lo)); |
e0d80184 DM |
1706 | return (hi | lo); |
1707 | } | |
ab835497 | 1708 | |
e0d80184 DM |
1709 | /* Here we are sure to be arch64 and this is an integer constant |
1710 | being loaded into a register. Emit the most efficient | |
1711 | insn sequence possible. Detection of all the 1-insn cases | |
1712 | has been done already. */ | |
1713 | void | |
fc27d102 | 1714 | sparc_emit_set_const64 (rtx op0, rtx op1) |
e0d80184 | 1715 | { |
2a01c939 | 1716 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1717 | int lowest_bit_set, highest_bit_set; |
1718 | int all_bits_between_are_set; | |
1d511ed5 | 1719 | rtx temp = 0; |
ab835497 | 1720 | |
e0d80184 | 1721 | /* Sanity check that we know what we are working with. */ |
bea5071f EB |
1722 | gcc_assert (TARGET_ARCH64 |
1723 | && (GET_CODE (op0) == SUBREG | |
1724 | || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0))))); | |
380f6ad3 | 1725 | |
f710f868 DM |
1726 | if (reload_in_progress || reload_completed) |
1727 | temp = op0; | |
f710f868 | 1728 | |
0e5d569c | 1729 | if (GET_CODE (op1) != CONST_INT) |
e0d80184 | 1730 | { |
5f78aa30 JC |
1731 | sparc_emit_set_symbolic_const64 (op0, op1, temp); |
1732 | return; | |
e0d80184 | 1733 | } |
ab835497 | 1734 | |
1d511ed5 EB |
1735 | if (! temp) |
1736 | temp = gen_reg_rtx (DImode); | |
1737 | ||
0e5d569c EB |
1738 | high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); |
1739 | low_bits = (INTVAL (op1) & 0xffffffff); | |
ab835497 | 1740 | |
e0d80184 DM |
1741 | /* low_bits bits 0 --> 31 |
1742 | high_bits bits 32 --> 63 */ | |
ab835497 | 1743 | |
e0d80184 DM |
1744 | analyze_64bit_constant (high_bits, low_bits, |
1745 | &highest_bit_set, &lowest_bit_set, | |
1746 | &all_bits_between_are_set); | |
1747 | ||
1748 | /* First try for a 2-insn sequence. */ | |
1749 | ||
1750 | /* These situations are preferred because the optimizer can | |
1751 | * do more things with them: | |
1752 | * 1) mov -1, %reg | |
1753 | * sllx %reg, shift, %reg | |
1754 | * 2) mov -1, %reg | |
1755 | * srlx %reg, shift, %reg | |
1756 | * 3) mov some_small_const, %reg | |
1757 | * sllx %reg, shift, %reg | |
1758 | */ | |
1759 | if (((highest_bit_set == 63 | |
1760 | || lowest_bit_set == 0) | |
1761 | && all_bits_between_are_set != 0) | |
2a01c939 | 1762 | || ((highest_bit_set - lowest_bit_set) < 12)) |
e0d80184 | 1763 | { |
9208e4b2 | 1764 | HOST_WIDE_INT the_const = -1; |
e0d80184 DM |
1765 | int shift = lowest_bit_set; |
1766 | ||
f710f868 DM |
1767 | if ((highest_bit_set != 63 |
1768 | && lowest_bit_set != 0) | |
1769 | || all_bits_between_are_set == 0) | |
ab835497 | 1770 | { |
e0d80184 | 1771 | the_const = |
9208e4b2 | 1772 | create_simple_focus_bits (high_bits, low_bits, |
9208e4b2 | 1773 | lowest_bit_set, 0); |
ab835497 | 1774 | } |
e0d80184 | 1775 | else if (lowest_bit_set == 0) |
9208e4b2 | 1776 | shift = -(63 - highest_bit_set); |
e0d80184 | 1777 | |
f5f7d171 JM |
1778 | gcc_assert (SPARC_SIMM13_P (the_const)); |
1779 | gcc_assert (shift != 0); | |
f710f868 | 1780 | |
9208e4b2 | 1781 | emit_insn (gen_safe_SET64 (temp, the_const)); |
e0d80184 | 1782 | if (shift > 0) |
9208e4b2 | 1783 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 DM |
1784 | op0, |
1785 | gen_rtx_ASHIFT (DImode, | |
1786 | temp, | |
1787 | GEN_INT (shift)))); | |
1788 | else if (shift < 0) | |
9208e4b2 | 1789 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1790 | op0, |
9208e4b2 | 1791 | gen_rtx_LSHIFTRT (DImode, |
e0d80184 DM |
1792 | temp, |
1793 | GEN_INT (-shift)))); | |
e0d80184 DM |
1794 | return; |
1795 | } | |
ab835497 | 1796 | |
e0d80184 DM |
1797 | /* Now a range of 22 or less bits set somewhere. |
1798 | * 1) sethi %hi(focus_bits), %reg | |
1799 | * sllx %reg, shift, %reg | |
1800 | * 2) sethi %hi(focus_bits), %reg | |
1801 | * srlx %reg, shift, %reg | |
1802 | */ | |
2a01c939 | 1803 | if ((highest_bit_set - lowest_bit_set) < 21) |
e0d80184 | 1804 | { |
2a01c939 | 1805 | unsigned HOST_WIDE_INT focus_bits = |
e0d80184 | 1806 | create_simple_focus_bits (high_bits, low_bits, |
ddf80874 | 1807 | lowest_bit_set, 10); |
f710f868 | 1808 | |
f5f7d171 JM |
1809 | gcc_assert (SPARC_SETHI_P (focus_bits)); |
1810 | gcc_assert (lowest_bit_set != 10); | |
f710f868 | 1811 | |
9bb3323d | 1812 | emit_insn (gen_safe_HIGH64 (temp, focus_bits)); |
e0d80184 | 1813 | |
9208e4b2 | 1814 | /* If lowest_bit_set == 10 then a sethi alone could have done it. */ |
e0d80184 | 1815 | if (lowest_bit_set < 10) |
9208e4b2 | 1816 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1817 | op0, |
9208e4b2 | 1818 | gen_rtx_LSHIFTRT (DImode, temp, |
e0d80184 | 1819 | GEN_INT (10 - lowest_bit_set)))); |
9208e4b2 DM |
1820 | else if (lowest_bit_set > 10) |
1821 | emit_insn (gen_rtx_SET (VOIDmode, | |
e0d80184 DM |
1822 | op0, |
1823 | gen_rtx_ASHIFT (DImode, temp, | |
1824 | GEN_INT (lowest_bit_set - 10)))); | |
e0d80184 DM |
1825 | return; |
1826 | } | |
1827 | ||
1828 | /* 1) sethi %hi(low_bits), %reg | |
1829 | * or %reg, %lo(low_bits), %reg | |
1830 | * 2) sethi %hi(~low_bits), %reg | |
1831 | * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg | |
1832 | */ | |
1833 | if (high_bits == 0 | |
2a01c939 | 1834 | || high_bits == 0xffffffff) |
5f78aa30 JC |
1835 | { |
1836 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, | |
1837 | (high_bits == 0xffffffff)); | |
1838 | return; | |
1839 | } | |
e0d80184 | 1840 | |
f710f868 DM |
1841 | /* Now, try 3-insn sequences. */ |
1842 | ||
e0d80184 DM |
1843 | /* 1) sethi %hi(high_bits), %reg |
1844 | * or %reg, %lo(high_bits), %reg | |
1845 | * sllx %reg, 32, %reg | |
1846 | */ | |
f710f868 | 1847 | if (low_bits == 0) |
5f78aa30 | 1848 | { |
f710f868 | 1849 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); |
5f78aa30 JC |
1850 | return; |
1851 | } | |
e0d80184 | 1852 | |
f710f868 DM |
1853 | /* We may be able to do something quick |
1854 | when the constant is negated, so try that. */ | |
e0d80184 DM |
1855 | if (const64_is_2insns ((~high_bits) & 0xffffffff, |
1856 | (~low_bits) & 0xfffffc00)) | |
1857 | { | |
5108f3e5 DM |
1858 | /* NOTE: The trailing bits get XOR'd so we need the |
1859 | non-negated bits, not the negated ones. */ | |
1860 | unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; | |
e0d80184 DM |
1861 | |
1862 | if ((((~high_bits) & 0xffffffff) == 0 | |
1863 | && ((~low_bits) & 0x80000000) == 0) | |
1864 | || (((~high_bits) & 0xffffffff) == 0xffffffff | |
1865 | && ((~low_bits) & 0x80000000) != 0)) | |
ab835497 | 1866 | { |
0e5d569c | 1867 | unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff); |
e0d80184 | 1868 | |
5108f3e5 DM |
1869 | if ((SPARC_SETHI_P (fast_int) |
1870 | && (~high_bits & 0xffffffff) == 0) | |
1871 | || SPARC_SIMM13_P (fast_int)) | |
9208e4b2 | 1872 | emit_insn (gen_safe_SET64 (temp, fast_int)); |
ab835497 | 1873 | else |
0e5d569c | 1874 | sparc_emit_set_const64 (temp, GEN_INT (fast_int)); |
ab835497 | 1875 | } |
e0d80184 DM |
1876 | else |
1877 | { | |
1878 | rtx negated_const; | |
e0d80184 DM |
1879 | negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | |
1880 | (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); | |
e0d80184 DM |
1881 | sparc_emit_set_const64 (temp, negated_const); |
1882 | } | |
5108f3e5 DM |
1883 | |
1884 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
1885 | instead. This way the combiner will notice logical operations | |
1886 | such as ANDN later on and substitute. */ | |
1887 | if (trailing_bits == 0x3ff) | |
1888 | { | |
1889 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1890 | gen_rtx_NOT (DImode, temp))); | |
1891 | } | |
1892 | else | |
1893 | { | |
1894 | emit_insn (gen_rtx_SET (VOIDmode, | |
1895 | op0, | |
1896 | gen_safe_XOR64 (temp, | |
1897 | (-0x400 | trailing_bits)))); | |
1898 | } | |
e0d80184 | 1899 | return; |
ab835497 | 1900 | } |
ab835497 | 1901 | |
e0d80184 DM |
1902 | /* 1) sethi %hi(xxx), %reg |
1903 | * or %reg, %lo(xxx), %reg | |
1904 | * sllx %reg, yyy, %reg | |
f710f868 DM |
1905 | * |
1906 | * ??? This is just a generalized version of the low_bits==0 | |
1907 | * thing above, FIXME... | |
e0d80184 DM |
1908 | */ |
1909 | if ((highest_bit_set - lowest_bit_set) < 32) | |
1910 | { | |
f710f868 DM |
1911 | unsigned HOST_WIDE_INT focus_bits = |
1912 | create_simple_focus_bits (high_bits, low_bits, | |
ddf80874 | 1913 | lowest_bit_set, 0); |
ab835497 | 1914 | |
e0d80184 | 1915 | /* We can't get here in this state. */ |
f5f7d171 | 1916 | gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32); |
95726648 | 1917 | |
e0d80184 DM |
1918 | /* So what we know is that the set bits straddle the |
1919 | middle of the 64-bit word. */ | |
5f78aa30 JC |
1920 | sparc_emit_set_const64_quick2 (op0, temp, |
1921 | focus_bits, 0, | |
1922 | lowest_bit_set); | |
1923 | return; | |
e0d80184 | 1924 | } |
c85f7c16 | 1925 | |
f710f868 DM |
1926 | /* 1) sethi %hi(high_bits), %reg |
1927 | * or %reg, %lo(high_bits), %reg | |
1928 | * sllx %reg, 32, %reg | |
1929 | * or %reg, low_bits, %reg | |
1930 | */ | |
1931 | if (SPARC_SIMM13_P(low_bits) | |
1932 | && ((int)low_bits > 0)) | |
1933 | { | |
1934 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); | |
1935 | return; | |
1936 | } | |
1937 | ||
80ffc95e | 1938 | /* The easiest way when all else fails, is full decomposition. */ |
e0d80184 DM |
1939 | #if 0 |
1940 | printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", | |
1941 | high_bits, low_bits, ~high_bits, ~low_bits); | |
1942 | #endif | |
1943 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); | |
c85f7c16 | 1944 | } |
0e5d569c | 1945 | #endif /* HOST_BITS_PER_WIDE_INT == 32 */ |
c85f7c16 | 1946 | |
e267e177 RH |
1947 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
1948 | return the mode to be used for the comparison. For floating-point, | |
1949 | CCFP[E]mode is used. CC_NOOVmode should be used when the first operand | |
1950 | is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special | |
1951 | processing is needed. */ | |
1952 | ||
1953 | enum machine_mode | |
fc27d102 | 1954 | select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED) |
e267e177 RH |
1955 | { |
1956 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1957 | { | |
1958 | switch (op) | |
1959 | { | |
1960 | case EQ: | |
1961 | case NE: | |
1962 | case UNORDERED: | |
1963 | case ORDERED: | |
1964 | case UNLT: | |
1965 | case UNLE: | |
1966 | case UNGT: | |
1967 | case UNGE: | |
1968 | case UNEQ: | |
7913f3d0 | 1969 | case LTGT: |
e267e177 RH |
1970 | return CCFPmode; |
1971 | ||
1972 | case LT: | |
1973 | case LE: | |
1974 | case GT: | |
1975 | case GE: | |
1976 | return CCFPEmode; | |
1977 | ||
1978 | default: | |
f5f7d171 | 1979 | gcc_unreachable (); |
e267e177 RH |
1980 | } |
1981 | } | |
1982 | else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
1983 | || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) | |
1984 | { | |
1985 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
1986 | return CCX_NOOVmode; | |
1987 | else | |
1988 | return CC_NOOVmode; | |
1989 | } | |
1990 | else | |
1991 | { | |
1992 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
1993 | return CCXmode; | |
1994 | else | |
1995 | return CCmode; | |
1996 | } | |
1997 | } | |
1998 | ||
f90b7a5a PB |
1999 | /* Emit the compare insn and return the CC reg for a CODE comparison |
2000 | with operands X and Y. */ | |
c85f7c16 | 2001 | |
f90b7a5a PB |
2002 | static rtx |
2003 | gen_compare_reg_1 (enum rtx_code code, rtx x, rtx y) | |
c85f7c16 | 2004 | { |
65c5ae8b | 2005 | enum machine_mode mode; |
f90b7a5a | 2006 | rtx cc_reg; |
c85f7c16 | 2007 | |
f90b7a5a PB |
2008 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) |
2009 | return x; | |
65c5ae8b | 2010 | |
65c5ae8b | 2011 | mode = SELECT_CC_MODE (code, x, y); |
8ec11fe9 | 2012 | |
e0d80184 DM |
2013 | /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the |
2014 | fcc regs (cse can't tell they're really call clobbered regs and will | |
2015 | remove a duplicate comparison even if there is an intervening function | |
2016 | call - it will then try to reload the cc reg via an int reg which is why | |
2017 | we need the movcc patterns). It is possible to provide the movcc | |
2018 | patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two | |
2019 | registers (say %g1,%g5) and it takes about 6 insns. A better fix would be | |
2020 | to tell cse that CCFPE mode registers (even pseudos) are call | |
2021 | clobbered. */ | |
c85f7c16 | 2022 | |
e0d80184 DM |
2023 | /* ??? This is an experiment. Rather than making changes to cse which may |
2024 | or may not be easy/clean, we do our own cse. This is possible because | |
2025 | we will generate hard registers. Cse knows they're call clobbered (it | |
2026 | doesn't know the same thing about pseudos). If we guess wrong, no big | |
2027 | deal, but if we win, great! */ | |
c85f7c16 | 2028 | |
e0d80184 DM |
2029 | if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) |
2030 | #if 1 /* experiment */ | |
284d86e9 | 2031 | { |
e0d80184 DM |
2032 | int reg; |
2033 | /* We cycle through the registers to ensure they're all exercised. */ | |
2034 | static int next_fcc_reg = 0; | |
2035 | /* Previous x,y for each fcc reg. */ | |
2036 | static rtx prev_args[4][2]; | |
284d86e9 | 2037 | |
e0d80184 DM |
2038 | /* Scan prev_args for x,y. */ |
2039 | for (reg = 0; reg < 4; reg++) | |
2040 | if (prev_args[reg][0] == x && prev_args[reg][1] == y) | |
2041 | break; | |
2042 | if (reg == 4) | |
2043 | { | |
2044 | reg = next_fcc_reg; | |
2045 | prev_args[reg][0] = x; | |
2046 | prev_args[reg][1] = y; | |
2047 | next_fcc_reg = (next_fcc_reg + 1) & 3; | |
2048 | } | |
2049 | cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); | |
284d86e9 | 2050 | } |
e0d80184 DM |
2051 | #else |
2052 | cc_reg = gen_reg_rtx (mode); | |
2053 | #endif /* ! experiment */ | |
2054 | else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2055 | cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); | |
2056 | else | |
2057 | cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); | |
284d86e9 | 2058 | |
19047e4a EB |
2059 | /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this |
2060 | will only result in an unrecognizable insn so no point in asserting. */ | |
2061 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y))); | |
c85f7c16 | 2062 | |
e0d80184 DM |
2063 | return cc_reg; |
2064 | } | |
c85f7c16 | 2065 | |
f90b7a5a PB |
2066 | |
2067 | /* Emit the compare insn and return the CC reg for the comparison in CMP. */ | |
19047e4a EB |
2068 | |
2069 | rtx | |
f90b7a5a | 2070 | gen_compare_reg (rtx cmp) |
19047e4a | 2071 | { |
f90b7a5a | 2072 | return gen_compare_reg_1 (GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1)); |
19047e4a EB |
2073 | } |
2074 | ||
e0d80184 | 2075 | /* This function is used for v9 only. |
f90b7a5a | 2076 | DEST is the target of the Scc insn. |
e0d80184 | 2077 | CODE is the code for an Scc's comparison. |
f90b7a5a | 2078 | X and Y are the values we compare. |
c85f7c16 | 2079 | |
e0d80184 | 2080 | This function is needed to turn |
ab835497 | 2081 | |
e0d80184 DM |
2082 | (set (reg:SI 110) |
2083 | (gt (reg:CCX 100 %icc) | |
2084 | (const_int 0))) | |
2085 | into | |
2086 | (set (reg:SI 110) | |
2087 | (gt:DI (reg:CCX 100 %icc) | |
2088 | (const_int 0))) | |
2089 | ||
2090 | IE: The instruction recognizer needs to see the mode of the comparison to | |
2091 | find the right instruction. We could use "gt:DI" right in the | |
f90b7a5a | 2092 | define_expand, but leaving it out allows us to handle DI, SI, etc. */ |
ab835497 | 2093 | |
f90b7a5a PB |
2094 | static int |
2095 | gen_v9_scc (rtx dest, enum rtx_code compare_code, rtx x, rtx y) | |
ab835497 | 2096 | { |
e0d80184 | 2097 | if (! TARGET_ARCH64 |
f90b7a5a PB |
2098 | && (GET_MODE (x) == DImode |
2099 | || GET_MODE (dest) == DImode)) | |
e0d80184 | 2100 | return 0; |
7e2feebf | 2101 | |
e0d80184 DM |
2102 | /* Try to use the movrCC insns. */ |
2103 | if (TARGET_ARCH64 | |
f90b7a5a PB |
2104 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT |
2105 | && y == const0_rtx | |
e0d80184 | 2106 | && v9_regcmp_p (compare_code)) |
ab835497 | 2107 | { |
f90b7a5a | 2108 | rtx op0 = x; |
7e04157d DM |
2109 | rtx temp; |
2110 | ||
e0d80184 | 2111 | /* Special case for op0 != 0. This can be done with one instruction if |
f90b7a5a | 2112 | dest == x. */ |
e0d80184 DM |
2113 | |
2114 | if (compare_code == NE | |
f90b7a5a PB |
2115 | && GET_MODE (dest) == DImode |
2116 | && rtx_equal_p (op0, dest)) | |
ab835497 | 2117 | { |
f90b7a5a | 2118 | emit_insn (gen_rtx_SET (VOIDmode, dest, |
e0d80184 DM |
2119 | gen_rtx_IF_THEN_ELSE (DImode, |
2120 | gen_rtx_fmt_ee (compare_code, DImode, | |
2121 | op0, const0_rtx), | |
2122 | const1_rtx, | |
f90b7a5a | 2123 | dest))); |
ab835497 RK |
2124 | return 1; |
2125 | } | |
e0d80184 | 2126 | |
f90b7a5a | 2127 | if (reg_overlap_mentioned_p (dest, op0)) |
a42519be | 2128 | { |
f90b7a5a | 2129 | /* Handle the case where dest == x. |
a42519be | 2130 | We "early clobber" the result. */ |
f90b7a5a PB |
2131 | op0 = gen_reg_rtx (GET_MODE (x)); |
2132 | emit_move_insn (op0, x); | |
a42519be JJ |
2133 | } |
2134 | ||
f90b7a5a | 2135 | emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx)); |
e0d80184 | 2136 | if (GET_MODE (op0) != DImode) |
ab835497 | 2137 | { |
e0d80184 DM |
2138 | temp = gen_reg_rtx (DImode); |
2139 | convert_move (temp, op0, 0); | |
ab835497 | 2140 | } |
e0d80184 DM |
2141 | else |
2142 | temp = op0; | |
f90b7a5a PB |
2143 | emit_insn (gen_rtx_SET (VOIDmode, dest, |
2144 | gen_rtx_IF_THEN_ELSE (GET_MODE (dest), | |
e0d80184 DM |
2145 | gen_rtx_fmt_ee (compare_code, DImode, |
2146 | temp, const0_rtx), | |
2147 | const1_rtx, | |
f90b7a5a | 2148 | dest))); |
95726648 DE |
2149 | return 1; |
2150 | } | |
e0d80184 | 2151 | else |
ab835497 | 2152 | { |
f90b7a5a PB |
2153 | x = gen_compare_reg_1 (compare_code, x, y); |
2154 | y = const0_rtx; | |
ab835497 | 2155 | |
f90b7a5a PB |
2156 | gcc_assert (GET_MODE (x) != CC_NOOVmode |
2157 | && GET_MODE (x) != CCX_NOOVmode); | |
2158 | ||
2159 | emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx)); | |
2160 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
2161 | gen_rtx_IF_THEN_ELSE (GET_MODE (dest), | |
e0d80184 | 2162 | gen_rtx_fmt_ee (compare_code, |
f90b7a5a PB |
2163 | GET_MODE (x), x, y), |
2164 | const1_rtx, dest))); | |
e0d80184 | 2165 | return 1; |
ab835497 | 2166 | } |
ab835497 | 2167 | } |
4fb4e4b8 | 2168 | |
f90b7a5a PB |
2169 | |
2170 | /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this | |
2171 | without jumps using the addx/subx instructions. */ | |
2172 | ||
2173 | bool | |
2174 | emit_scc_insn (rtx operands[]) | |
2175 | { | |
2176 | rtx tem; | |
2177 | rtx x; | |
2178 | rtx y; | |
2179 | enum rtx_code code; | |
2180 | ||
2181 | /* The quad-word fp compare library routines all return nonzero to indicate | |
2182 | true, which is different from the equivalent libgcc routines, so we must | |
2183 | handle them specially here. */ | |
2184 | if (GET_MODE (operands[2]) == TFmode && ! TARGET_HARD_QUAD) | |
2185 | { | |
2186 | operands[1] = sparc_emit_float_lib_cmp (operands[2], operands[3], | |
2187 | GET_CODE (operands[1])); | |
2188 | operands[2] = XEXP (operands[1], 0); | |
2189 | operands[3] = XEXP (operands[1], 1); | |
2190 | } | |
2191 | ||
2192 | code = GET_CODE (operands[1]); | |
2193 | x = operands[2]; | |
2194 | y = operands[3]; | |
2195 | ||
2196 | /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has | |
2197 | more applications). The exception to this is "reg != 0" which can | |
2198 | be done in one instruction on v9 (so we do it). */ | |
2199 | if (code == EQ) | |
2200 | { | |
2201 | if (GET_MODE (x) == SImode) | |
2202 | { | |
2203 | rtx pat = gen_seqsi_special (operands[0], x, y); | |
2204 | emit_insn (pat); | |
2205 | return true; | |
2206 | } | |
2207 | else if (GET_MODE (x) == DImode) | |
2208 | { | |
2209 | rtx pat = gen_seqdi_special (operands[0], x, y); | |
2210 | emit_insn (pat); | |
2211 | return true; | |
2212 | } | |
2213 | } | |
2214 | ||
2215 | if (code == NE) | |
2216 | { | |
2217 | if (GET_MODE (x) == SImode) | |
2218 | { | |
2219 | rtx pat = gen_snesi_special (operands[0], x, y); | |
2220 | emit_insn (pat); | |
2221 | return true; | |
2222 | } | |
2223 | else if (GET_MODE (x) == DImode) | |
2224 | { | |
2225 | rtx pat = gen_snedi_special (operands[0], x, y); | |
2226 | emit_insn (pat); | |
2227 | return true; | |
2228 | } | |
2229 | } | |
2230 | ||
2231 | /* For the rest, on v9 we can use conditional moves. */ | |
2232 | ||
2233 | if (TARGET_V9) | |
2234 | { | |
2235 | if (gen_v9_scc (operands[0], code, x, y)) | |
2236 | return true; | |
2237 | } | |
2238 | ||
2239 | /* We can do LTU and GEU using the addx/subx instructions too. And | |
2240 | for GTU/LEU, if both operands are registers swap them and fall | |
2241 | back to the easy case. */ | |
2242 | if (code == GTU || code == LEU) | |
2243 | { | |
2244 | if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG) | |
2245 | && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG)) | |
2246 | { | |
2247 | tem = x; | |
2248 | x = y; | |
2249 | y = tem; | |
2250 | code = swap_condition (code); | |
2251 | } | |
2252 | } | |
2253 | ||
2254 | if (code == LTU || code == GEU) | |
2255 | { | |
2256 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
4900aa61 | 2257 | gen_rtx_fmt_ee (code, SImode, |
f90b7a5a PB |
2258 | gen_compare_reg_1 (code, x, y), |
2259 | const0_rtx))); | |
2260 | return true; | |
2261 | } | |
2262 | ||
2263 | /* Nope, do branches. */ | |
2264 | return false; | |
2265 | } | |
2266 | ||
e0d80184 DM |
2267 | /* Emit a conditional jump insn for the v9 architecture using comparison code |
2268 | CODE and jump target LABEL. | |
2269 | This function exists to take advantage of the v9 brxx insns. */ | |
ab835497 | 2270 | |
f90b7a5a | 2271 | static void |
fc27d102 | 2272 | emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label) |
ab835497 | 2273 | { |
e0d80184 DM |
2274 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
2275 | pc_rtx, | |
2276 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
2277 | gen_rtx_fmt_ee (code, GET_MODE (op0), | |
2278 | op0, const0_rtx), | |
2279 | gen_rtx_LABEL_REF (VOIDmode, label), | |
2280 | pc_rtx))); | |
2281 | } | |
7b1ac798 | 2282 | |
f90b7a5a PB |
2283 | void |
2284 | emit_conditional_branch_insn (rtx operands[]) | |
2285 | { | |
2286 | /* The quad-word fp compare library routines all return nonzero to indicate | |
2287 | true, which is different from the equivalent libgcc routines, so we must | |
2288 | handle them specially here. */ | |
2289 | if (GET_MODE (operands[1]) == TFmode && ! TARGET_HARD_QUAD) | |
2290 | { | |
2291 | operands[0] = sparc_emit_float_lib_cmp (operands[1], operands[2], | |
2292 | GET_CODE (operands[0])); | |
2293 | operands[1] = XEXP (operands[0], 0); | |
2294 | operands[2] = XEXP (operands[0], 1); | |
2295 | } | |
2296 | ||
2297 | if (TARGET_ARCH64 && operands[2] == const0_rtx | |
2298 | && GET_CODE (operands[1]) == REG | |
2299 | && GET_MODE (operands[1]) == DImode) | |
2300 | { | |
2301 | emit_v9_brxx_insn (GET_CODE (operands[0]), operands[1], operands[3]); | |
2302 | return; | |
2303 | } | |
2304 | ||
2305 | operands[1] = gen_compare_reg (operands[0]); | |
2306 | operands[2] = const0_rtx; | |
2307 | operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]), VOIDmode, | |
2308 | operands[1], operands[2]); | |
2309 | emit_jump_insn (gen_cbranchcc4 (operands[0], operands[1], operands[2], | |
2310 | operands[3])); | |
2311 | } | |
2312 | ||
2313 | ||
7b1ac798 JJ |
2314 | /* Generate a DFmode part of a hard TFmode register. |
2315 | REG is the TFmode hard register, LOW is 1 for the | |
2316 | low 64bit of the register and 0 otherwise. | |
2317 | */ | |
2318 | rtx | |
fc27d102 | 2319 | gen_df_reg (rtx reg, int low) |
7b1ac798 JJ |
2320 | { |
2321 | int regno = REGNO (reg); | |
2322 | ||
2323 | if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) | |
2aac41d6 | 2324 | regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2; |
7b1ac798 JJ |
2325 | return gen_rtx_REG (DFmode, regno); |
2326 | } | |
e0d80184 | 2327 | \f |
73985940 RH |
2328 | /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value. |
2329 | Unlike normal calls, TFmode operands are passed by reference. It is | |
2330 | assumed that no more than 3 operands are required. */ | |
2331 | ||
2332 | static void | |
fc27d102 | 2333 | emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands) |
73985940 RH |
2334 | { |
2335 | rtx ret_slot = NULL, arg[3], func_sym; | |
4e7d5d27 | 2336 | int i; |
73985940 RH |
2337 | |
2338 | /* We only expect to be called for conversions, unary, and binary ops. */ | |
f5f7d171 | 2339 | gcc_assert (nargs == 2 || nargs == 3); |
73985940 RH |
2340 | |
2341 | for (i = 0; i < nargs; ++i) | |
2342 | { | |
2343 | rtx this_arg = operands[i]; | |
2344 | rtx this_slot; | |
2345 | ||
2346 | /* TFmode arguments and return values are passed by reference. */ | |
2347 | if (GET_MODE (this_arg) == TFmode) | |
2348 | { | |
4e7d5d27 DM |
2349 | int force_stack_temp; |
2350 | ||
2351 | force_stack_temp = 0; | |
2352 | if (TARGET_BUGGY_QP_LIB && i == 0) | |
2353 | force_stack_temp = 1; | |
2354 | ||
2355 | if (GET_CODE (this_arg) == MEM | |
2356 | && ! force_stack_temp) | |
2357 | this_arg = XEXP (this_arg, 0); | |
2358 | else if (CONSTANT_P (this_arg) | |
2359 | && ! force_stack_temp) | |
73985940 RH |
2360 | { |
2361 | this_slot = force_const_mem (TFmode, this_arg); | |
2362 | this_arg = XEXP (this_slot, 0); | |
2363 | } | |
2364 | else | |
2365 | { | |
2366 | this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0); | |
2367 | ||
2368 | /* Operand 0 is the return value. We'll copy it out later. */ | |
2369 | if (i > 0) | |
2370 | emit_move_insn (this_slot, this_arg); | |
2371 | else | |
2372 | ret_slot = this_slot; | |
2373 | ||
2374 | this_arg = XEXP (this_slot, 0); | |
2375 | } | |
2376 | } | |
2377 | ||
2378 | arg[i] = this_arg; | |
2379 | } | |
2380 | ||
2381 | func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name); | |
2382 | ||
2383 | if (GET_MODE (operands[0]) == TFmode) | |
2384 | { | |
2385 | if (nargs == 2) | |
2386 | emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2, | |
2387 | arg[0], GET_MODE (arg[0]), | |
2388 | arg[1], GET_MODE (arg[1])); | |
2389 | else | |
2390 | emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3, | |
2391 | arg[0], GET_MODE (arg[0]), | |
2392 | arg[1], GET_MODE (arg[1]), | |
2393 | arg[2], GET_MODE (arg[2])); | |
2394 | ||
2395 | if (ret_slot) | |
2396 | emit_move_insn (operands[0], ret_slot); | |
2397 | } | |
2398 | else | |
2399 | { | |
2400 | rtx ret; | |
2401 | ||
f5f7d171 | 2402 | gcc_assert (nargs == 2); |
73985940 RH |
2403 | |
2404 | ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL, | |
2405 | GET_MODE (operands[0]), 1, | |
2406 | arg[1], GET_MODE (arg[1])); | |
2407 | ||
2408 | if (ret != operands[0]) | |
2409 | emit_move_insn (operands[0], ret); | |
2410 | } | |
2411 | } | |
2412 | ||
2413 | /* Expand soft-float TFmode calls to sparc abi routines. */ | |
2414 | ||
2415 | static void | |
fc27d102 | 2416 | emit_soft_tfmode_binop (enum rtx_code code, rtx *operands) |
73985940 RH |
2417 | { |
2418 | const char *func; | |
2419 | ||
2420 | switch (code) | |
2421 | { | |
2422 | case PLUS: | |
2423 | func = "_Qp_add"; | |
2424 | break; | |
2425 | case MINUS: | |
2426 | func = "_Qp_sub"; | |
2427 | break; | |
2428 | case MULT: | |
2429 | func = "_Qp_mul"; | |
2430 | break; | |
2431 | case DIV: | |
2432 | func = "_Qp_div"; | |
2433 | break; | |
2434 | default: | |
f5f7d171 | 2435 | gcc_unreachable (); |
73985940 RH |
2436 | } |
2437 | ||
2438 | emit_soft_tfmode_libcall (func, 3, operands); | |
2439 | } | |
2440 | ||
2441 | static void | |
fc27d102 | 2442 | emit_soft_tfmode_unop (enum rtx_code code, rtx *operands) |
73985940 RH |
2443 | { |
2444 | const char *func; | |
2445 | ||
f5f7d171 JM |
2446 | gcc_assert (code == SQRT); |
2447 | func = "_Qp_sqrt"; | |
73985940 RH |
2448 | |
2449 | emit_soft_tfmode_libcall (func, 2, operands); | |
2450 | } | |
2451 | ||
2452 | static void | |
fc27d102 | 2453 | emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands) |
73985940 RH |
2454 | { |
2455 | const char *func; | |
2456 | ||
2457 | switch (code) | |
2458 | { | |
2459 | case FLOAT_EXTEND: | |
2460 | switch (GET_MODE (operands[1])) | |
2461 | { | |
2462 | case SFmode: | |
2463 | func = "_Qp_stoq"; | |
2464 | break; | |
2465 | case DFmode: | |
2466 | func = "_Qp_dtoq"; | |
2467 | break; | |
2468 | default: | |
f5f7d171 | 2469 | gcc_unreachable (); |
73985940 RH |
2470 | } |
2471 | break; | |
2472 | ||
2473 | case FLOAT_TRUNCATE: | |
2474 | switch (GET_MODE (operands[0])) | |
2475 | { | |
2476 | case SFmode: | |
2477 | func = "_Qp_qtos"; | |
2478 | break; | |
2479 | case DFmode: | |
2480 | func = "_Qp_qtod"; | |
2481 | break; | |
2482 | default: | |
f5f7d171 | 2483 | gcc_unreachable (); |
73985940 RH |
2484 | } |
2485 | break; | |
2486 | ||
2487 | case FLOAT: | |
2488 | switch (GET_MODE (operands[1])) | |
2489 | { | |
2490 | case SImode: | |
2491 | func = "_Qp_itoq"; | |
92693034 JM |
2492 | if (TARGET_ARCH64) |
2493 | operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]); | |
73985940 RH |
2494 | break; |
2495 | case DImode: | |
2496 | func = "_Qp_xtoq"; | |
2497 | break; | |
2498 | default: | |
f5f7d171 | 2499 | gcc_unreachable (); |
73985940 RH |
2500 | } |
2501 | break; | |
2502 | ||
2503 | case UNSIGNED_FLOAT: | |
2504 | switch (GET_MODE (operands[1])) | |
2505 | { | |
2506 | case SImode: | |
2507 | func = "_Qp_uitoq"; | |
92693034 JM |
2508 | if (TARGET_ARCH64) |
2509 | operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
73985940 RH |
2510 | break; |
2511 | case DImode: | |
2512 | func = "_Qp_uxtoq"; | |
2513 | break; | |
2514 | default: | |
f5f7d171 | 2515 | gcc_unreachable (); |
73985940 RH |
2516 | } |
2517 | break; | |
2518 | ||
2519 | case FIX: | |
2520 | switch (GET_MODE (operands[0])) | |
2521 | { | |
2522 | case SImode: | |
2523 | func = "_Qp_qtoi"; | |
2524 | break; | |
2525 | case DImode: | |
2526 | func = "_Qp_qtox"; | |
2527 | break; | |
2528 | default: | |
f5f7d171 | 2529 | gcc_unreachable (); |
73985940 RH |
2530 | } |
2531 | break; | |
2532 | ||
2533 | case UNSIGNED_FIX: | |
2534 | switch (GET_MODE (operands[0])) | |
2535 | { | |
2536 | case SImode: | |
2537 | func = "_Qp_qtoui"; | |
2538 | break; | |
2539 | case DImode: | |
2540 | func = "_Qp_qtoux"; | |
2541 | break; | |
2542 | default: | |
f5f7d171 | 2543 | gcc_unreachable (); |
73985940 RH |
2544 | } |
2545 | break; | |
2546 | ||
2547 | default: | |
f5f7d171 | 2548 | gcc_unreachable (); |
73985940 RH |
2549 | } |
2550 | ||
2551 | emit_soft_tfmode_libcall (func, 2, operands); | |
2552 | } | |
2553 | ||
2554 | /* Expand a hard-float tfmode operation. All arguments must be in | |
2555 | registers. */ | |
2556 | ||
2557 | static void | |
fc27d102 | 2558 | emit_hard_tfmode_operation (enum rtx_code code, rtx *operands) |
73985940 RH |
2559 | { |
2560 | rtx op, dest; | |
2561 | ||
ec8e098d | 2562 | if (GET_RTX_CLASS (code) == RTX_UNARY) |
73985940 RH |
2563 | { |
2564 | operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); | |
2565 | op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]); | |
2566 | } | |
2567 | else | |
2568 | { | |
2569 | operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); | |
2570 | operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); | |
2571 | op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]), | |
2572 | operands[1], operands[2]); | |
2573 | } | |
2574 | ||
2575 | if (register_operand (operands[0], VOIDmode)) | |
2576 | dest = operands[0]; | |
2577 | else | |
2578 | dest = gen_reg_rtx (GET_MODE (operands[0])); | |
2579 | ||
2580 | emit_insn (gen_rtx_SET (VOIDmode, dest, op)); | |
2581 | ||
2582 | if (dest != operands[0]) | |
2583 | emit_move_insn (operands[0], dest); | |
2584 | } | |
2585 | ||
2586 | void | |
fc27d102 | 2587 | emit_tfmode_binop (enum rtx_code code, rtx *operands) |
73985940 RH |
2588 | { |
2589 | if (TARGET_HARD_QUAD) | |
2590 | emit_hard_tfmode_operation (code, operands); | |
2591 | else | |
2592 | emit_soft_tfmode_binop (code, operands); | |
2593 | } | |
2594 | ||
2595 | void | |
fc27d102 | 2596 | emit_tfmode_unop (enum rtx_code code, rtx *operands) |
73985940 RH |
2597 | { |
2598 | if (TARGET_HARD_QUAD) | |
2599 | emit_hard_tfmode_operation (code, operands); | |
2600 | else | |
2601 | emit_soft_tfmode_unop (code, operands); | |
2602 | } | |
2603 | ||
2604 | void | |
fc27d102 | 2605 | emit_tfmode_cvt (enum rtx_code code, rtx *operands) |
73985940 RH |
2606 | { |
2607 | if (TARGET_HARD_QUAD) | |
2608 | emit_hard_tfmode_operation (code, operands); | |
2609 | else | |
2610 | emit_soft_tfmode_cvt (code, operands); | |
2611 | } | |
2612 | \f | |
f17f9332 JJ |
2613 | /* Return nonzero if a branch/jump/call instruction will be emitting |
2614 | nop into its delay slot. */ | |
2615 | ||
2616 | int | |
fc27d102 | 2617 | empty_delay_slot (rtx insn) |
f17f9332 JJ |
2618 | { |
2619 | rtx seq; | |
2620 | ||
2621 | /* If no previous instruction (should not happen), return true. */ | |
2622 | if (PREV_INSN (insn) == NULL) | |
2623 | return 1; | |
2624 | ||
2625 | seq = NEXT_INSN (PREV_INSN (insn)); | |
2626 | if (GET_CODE (PATTERN (seq)) == SEQUENCE) | |
2627 | return 0; | |
2628 | ||
2629 | return 1; | |
2630 | } | |
2631 | ||
9ac617d4 | 2632 | /* Return nonzero if TRIAL can go into the call delay slot. */ |
ab835497 | 2633 | |
e0d80184 | 2634 | int |
9ac617d4 | 2635 | tls_call_delay (rtx trial) |
e0d80184 | 2636 | { |
e10fbf96 | 2637 | rtx pat; |
1150a841 | 2638 | |
9ac617d4 | 2639 | /* Binutils allows |
e10fbf96 EB |
2640 | call __tls_get_addr, %tgd_call (foo) |
2641 | add %l7, %o0, %o0, %tgd_add (foo) | |
9ac617d4 EB |
2642 | while Sun as/ld does not. */ |
2643 | if (TARGET_GNU_TLS || !TARGET_TLS) | |
2644 | return 1; | |
4fb4e4b8 | 2645 | |
e0d80184 | 2646 | pat = PATTERN (trial); |
795068a4 | 2647 | |
e10fbf96 EB |
2648 | /* We must reject tgd_add{32|64}, i.e. |
2649 | (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD))) | |
2650 | and tldm_add{32|64}, i.e. | |
2651 | (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM))) | |
2652 | for Sun as/ld. */ | |
2653 | if (GET_CODE (pat) == SET | |
2654 | && GET_CODE (SET_SRC (pat)) == PLUS) | |
2655 | { | |
2656 | rtx unspec = XEXP (SET_SRC (pat), 1); | |
795068a4 | 2657 | |
e10fbf96 EB |
2658 | if (GET_CODE (unspec) == UNSPEC |
2659 | && (XINT (unspec, 1) == UNSPEC_TLSGD | |
2660 | || XINT (unspec, 1) == UNSPEC_TLSLDM)) | |
2661 | return 0; | |
2662 | } | |
2663 | ||
2664 | return 1; | |
9ac617d4 EB |
2665 | } |
2666 | ||
2667 | /* Return nonzero if TRIAL, an insn, can be combined with a 'restore' | |
2668 | instruction. RETURN_P is true if the v9 variant 'return' is to be | |
2669 | considered in the test too. | |
c137830f | 2670 | |
9ac617d4 EB |
2671 | TRIAL must be a SET whose destination is a REG appropriate for the |
2672 | 'restore' instruction or, if RETURN_P is true, for the 'return' | |
2673 | instruction. */ | |
795068a4 | 2674 | |
9ac617d4 EB |
2675 | static int |
2676 | eligible_for_restore_insn (rtx trial, bool return_p) | |
2677 | { | |
2678 | rtx pat = PATTERN (trial); | |
2679 | rtx src = SET_SRC (pat); | |
795068a4 | 2680 | |
9ac617d4 | 2681 | /* The 'restore src,%g0,dest' pattern for word mode and below. */ |
3ec6f1a9 RK |
2682 | if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2683 | && arith_operand (src, GET_MODE (src))) | |
3c6088d2 JJ |
2684 | { |
2685 | if (TARGET_ARCH64) | |
2686 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2687 | else | |
2688 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
2689 | } | |
e48addee | 2690 | |
9ac617d4 | 2691 | /* The 'restore src,%g0,dest' pattern for double-word mode. */ |
3ec6f1a9 RK |
2692 | else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2693 | && arith_double_operand (src, GET_MODE (src))) | |
e0d80184 | 2694 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); |
795068a4 | 2695 | |
9ac617d4 EB |
2696 | /* The 'restore src,%g0,dest' pattern for float if no FPU. */ |
2697 | else if (! TARGET_FPU && register_operand (src, SFmode)) | |
2698 | return 1; | |
2699 | ||
2700 | /* The 'restore src,%g0,dest' pattern for double if no FPU. */ | |
2701 | else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode)) | |
e0d80184 | 2702 | return 1; |
f5da225e | 2703 | |
9ac617d4 | 2704 | /* If we have the 'return' instruction, anything that does not use |
e48addee | 2705 | local or output registers and can go into a delay slot wins. */ |
9ac617d4 EB |
2706 | else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1) |
2707 | && (get_attr_in_uncond_branch_delay (trial) | |
2708 | == IN_UNCOND_BRANCH_DELAY_TRUE)) | |
e48addee JJ |
2709 | return 1; |
2710 | ||
9ac617d4 | 2711 | /* The 'restore src1,src2,dest' pattern for SImode. */ |
e0d80184 | 2712 | else if (GET_CODE (src) == PLUS |
9ac617d4 EB |
2713 | && register_operand (XEXP (src, 0), SImode) |
2714 | && arith_operand (XEXP (src, 1), SImode)) | |
e0d80184 DM |
2715 | return 1; |
2716 | ||
9ac617d4 | 2717 | /* The 'restore src1,src2,dest' pattern for DImode. */ |
e0d80184 | 2718 | else if (GET_CODE (src) == PLUS |
9ac617d4 EB |
2719 | && register_operand (XEXP (src, 0), DImode) |
2720 | && arith_double_operand (XEXP (src, 1), DImode)) | |
795068a4 | 2721 | return 1; |
795068a4 | 2722 | |
9ac617d4 | 2723 | /* The 'restore src1,%lo(src2),dest' pattern. */ |
e48addee JJ |
2724 | else if (GET_CODE (src) == LO_SUM |
2725 | && ! TARGET_CM_MEDMID | |
2726 | && ((register_operand (XEXP (src, 0), SImode) | |
2727 | && immediate_operand (XEXP (src, 1), SImode)) | |
2728 | || (TARGET_ARCH64 | |
2729 | && register_operand (XEXP (src, 0), DImode) | |
2730 | && immediate_operand (XEXP (src, 1), DImode)))) | |
2731 | return 1; | |
2732 | ||
9ac617d4 | 2733 | /* The 'restore src,src,dest' pattern. */ |
e48addee JJ |
2734 | else if (GET_CODE (src) == ASHIFT |
2735 | && (register_operand (XEXP (src, 0), SImode) | |
2736 | || register_operand (XEXP (src, 0), DImode)) | |
2737 | && XEXP (src, 1) == const1_rtx) | |
2738 | return 1; | |
2739 | ||
795068a4 JW |
2740 | return 0; |
2741 | } | |
2742 | ||
9ac617d4 EB |
2743 | /* Return nonzero if TRIAL can go into the function return's |
2744 | delay slot. */ | |
2745 | ||
5751a10b | 2746 | int |
9ac617d4 | 2747 | eligible_for_return_delay (rtx trial) |
5751a10b | 2748 | { |
9ac617d4 | 2749 | rtx pat; |
5751a10b | 2750 | |
9ac617d4 EB |
2751 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) |
2752 | return 0; | |
2753 | ||
2754 | if (get_attr_length (trial) != 1) | |
2755 | return 0; | |
2756 | ||
2757 | /* If there are any call-saved registers, we should scan TRIAL if it | |
2758 | does not reference them. For now just make it easy. */ | |
2759 | if (num_gfregs) | |
2760 | return 0; | |
2761 | ||
2762 | /* If the function uses __builtin_eh_return, the eh_return machinery | |
2763 | occupies the delay slot. */ | |
e3b5732b | 2764 | if (crtl->calls_eh_return) |
9ac617d4 EB |
2765 | return 0; |
2766 | ||
2767 | /* In the case of a true leaf function, anything can go into the slot. */ | |
5be9b7a1 | 2768 | if (sparc_leaf_function_p) |
9ac617d4 EB |
2769 | return get_attr_in_uncond_branch_delay (trial) |
2770 | == IN_UNCOND_BRANCH_DELAY_TRUE; | |
5751a10b JJ |
2771 | |
2772 | pat = PATTERN (trial); | |
5751a10b | 2773 | |
9ac617d4 EB |
2774 | /* Otherwise, only operations which can be done in tandem with |
2775 | a `restore' or `return' insn can go into the delay slot. */ | |
2776 | if (GET_CODE (SET_DEST (pat)) != REG | |
2777 | || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)) | |
2778 | return 0; | |
5751a10b | 2779 | |
9ac617d4 EB |
2780 | /* If this instruction sets up floating point register and we have a return |
2781 | instruction, it can probably go in. But restore will not work | |
2782 | with FP_REGS. */ | |
2783 | if (REGNO (SET_DEST (pat)) >= 32) | |
2784 | return (TARGET_V9 | |
2785 | && ! epilogue_renumber (&pat, 1) | |
2786 | && (get_attr_in_uncond_branch_delay (trial) | |
2787 | == IN_UNCOND_BRANCH_DELAY_TRUE)); | |
2788 | ||
2789 | return eligible_for_restore_insn (trial, true); | |
5751a10b JJ |
2790 | } |
2791 | ||
9ac617d4 | 2792 | /* Return nonzero if TRIAL can go into the sibling call's |
7d167afd JJ |
2793 | delay slot. */ |
2794 | ||
2795 | int | |
fc27d102 | 2796 | eligible_for_sibcall_delay (rtx trial) |
7d167afd | 2797 | { |
9ac617d4 | 2798 | rtx pat; |
7d167afd JJ |
2799 | |
2800 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) | |
2801 | return 0; | |
2802 | ||
8456b95a | 2803 | if (get_attr_length (trial) != 1) |
7d167afd JJ |
2804 | return 0; |
2805 | ||
2806 | pat = PATTERN (trial); | |
2807 | ||
5be9b7a1 | 2808 | if (sparc_leaf_function_p) |
7d167afd JJ |
2809 | { |
2810 | /* If the tail call is done using the call instruction, | |
2811 | we have to restore %o7 in the delay slot. */ | |
6244b14e | 2812 | if (LEAF_SIBCALL_SLOT_RESERVED_P) |
7d167afd JJ |
2813 | return 0; |
2814 | ||
2815 | /* %g1 is used to build the function address */ | |
2816 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) | |
2817 | return 0; | |
2818 | ||
2819 | return 1; | |
2820 | } | |
2821 | ||
2822 | /* Otherwise, only operations which can be done in tandem with | |
2823 | a `restore' insn can go into the delay slot. */ | |
2824 | if (GET_CODE (SET_DEST (pat)) != REG | |
9ac617d4 | 2825 | || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24) |
7d167afd JJ |
2826 | || REGNO (SET_DEST (pat)) >= 32) |
2827 | return 0; | |
2828 | ||
2829 | /* If it mentions %o7, it can't go in, because sibcall will clobber it | |
2830 | in most cases. */ | |
2831 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) | |
2832 | return 0; | |
2833 | ||
9ac617d4 | 2834 | return eligible_for_restore_insn (trial, false); |
e0d80184 | 2835 | } |
ab835497 | 2836 | |
e0d80184 | 2837 | int |
fc27d102 | 2838 | short_branch (int uid1, int uid2) |
e0d80184 | 2839 | { |
9d98a694 | 2840 | int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2); |
77b91512 RK |
2841 | |
2842 | /* Leave a few words of "slop". */ | |
2843 | if (delta >= -1023 && delta <= 1022) | |
e0d80184 | 2844 | return 1; |
77b91512 | 2845 | |
e0d80184 DM |
2846 | return 0; |
2847 | } | |
ab835497 | 2848 | |
5e7a8ee0 | 2849 | /* Return nonzero if REG is not used after INSN. |
e0d80184 DM |
2850 | We assume REG is a reload reg, and therefore does |
2851 | not live past labels or calls or jumps. */ | |
2852 | int | |
fc27d102 | 2853 | reg_unused_after (rtx reg, rtx insn) |
e0d80184 DM |
2854 | { |
2855 | enum rtx_code code, prev_code = UNKNOWN; | |
ab835497 | 2856 | |
e0d80184 | 2857 | while ((insn = NEXT_INSN (insn))) |
61a55e8b | 2858 | { |
e0d80184 DM |
2859 | if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) |
2860 | return 1; | |
ab835497 | 2861 | |
e0d80184 DM |
2862 | code = GET_CODE (insn); |
2863 | if (GET_CODE (insn) == CODE_LABEL) | |
2864 | return 1; | |
bc961ed7 | 2865 | |
ec8e098d | 2866 | if (INSN_P (insn)) |
61a55e8b | 2867 | { |
e0d80184 DM |
2868 | rtx set = single_set (insn); |
2869 | int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); | |
2870 | if (set && in_src) | |
2871 | return 0; | |
2872 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
2873 | return 1; | |
2874 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
2875 | return 0; | |
61a55e8b | 2876 | } |
e0d80184 | 2877 | prev_code = code; |
61a55e8b | 2878 | } |
e0d80184 DM |
2879 | return 1; |
2880 | } | |
2881 | \f | |
5751a10b JJ |
2882 | /* Determine if it's legal to put X into the constant pool. This |
2883 | is not possible if X contains the address of a symbol that is | |
2884 | not constant (TLS) or not known at final link time (PIC). */ | |
2885 | ||
2886 | static bool | |
2887 | sparc_cannot_force_const_mem (rtx x) | |
2888 | { | |
2889 | switch (GET_CODE (x)) | |
2890 | { | |
2891 | case CONST_INT: | |
2892 | case CONST_DOUBLE: | |
c75d6010 | 2893 | case CONST_VECTOR: |
5751a10b JJ |
2894 | /* Accept all non-symbolic constants. */ |
2895 | return false; | |
2896 | ||
2897 | case LABEL_REF: | |
2898 | /* Labels are OK iff we are non-PIC. */ | |
2899 | return flag_pic != 0; | |
2900 | ||
2901 | case SYMBOL_REF: | |
2902 | /* 'Naked' TLS symbol references are never OK, | |
2903 | non-TLS symbols are OK iff we are non-PIC. */ | |
2904 | if (SYMBOL_REF_TLS_MODEL (x)) | |
2905 | return true; | |
2906 | else | |
2907 | return flag_pic != 0; | |
2908 | ||
2909 | case CONST: | |
2910 | return sparc_cannot_force_const_mem (XEXP (x, 0)); | |
2911 | case PLUS: | |
2912 | case MINUS: | |
2913 | return sparc_cannot_force_const_mem (XEXP (x, 0)) | |
2914 | || sparc_cannot_force_const_mem (XEXP (x, 1)); | |
2915 | case UNSPEC: | |
2916 | return true; | |
2917 | default: | |
f5f7d171 | 2918 | gcc_unreachable (); |
5751a10b JJ |
2919 | } |
2920 | } | |
2921 | \f | |
5e77eb53 | 2922 | /* PIC support. */ |
9fd52c6c | 2923 | static GTY(()) bool pic_helper_needed = false; |
5e77eb53 | 2924 | static GTY(()) rtx pic_helper_symbol; |
e2500fed | 2925 | static GTY(()) rtx global_offset_table; |
bc961ed7 | 2926 | |
e0d80184 | 2927 | /* Ensure that we are not using patterns that are not OK with PIC. */ |
795068a4 | 2928 | |
e0d80184 | 2929 | int |
fc27d102 | 2930 | check_pic (int i) |
e0d80184 DM |
2931 | { |
2932 | switch (flag_pic) | |
ab835497 | 2933 | { |
e0d80184 | 2934 | case 1: |
f5f7d171 JM |
2935 | gcc_assert (GET_CODE (recog_data.operand[i]) != SYMBOL_REF |
2936 | && (GET_CODE (recog_data.operand[i]) != CONST | |
2937 | || (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS | |
2938 | && (XEXP (XEXP (recog_data.operand[i], 0), 0) | |
2939 | == global_offset_table) | |
2940 | && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) | |
2941 | == CONST)))); | |
e0d80184 DM |
2942 | case 2: |
2943 | default: | |
2944 | return 1; | |
ab835497 | 2945 | } |
ab835497 | 2946 | } |
795068a4 | 2947 | |
4900aa61 | 2948 | /* Return true if X is an address which needs a temporary register when |
e0d80184 | 2949 | reloaded while generating PIC code. */ |
795068a4 | 2950 | |
e0d80184 | 2951 | int |
fc27d102 | 2952 | pic_address_needs_scratch (rtx x) |
795068a4 | 2953 | { |
e0d80184 DM |
2954 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ |
2955 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
2956 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
2957 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2958 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
2959 | return 1; | |
795068a4 | 2960 | |
e0d80184 DM |
2961 | return 0; |
2962 | } | |
795068a4 | 2963 | |
5751a10b JJ |
2964 | /* Determine if a given RTX is a valid constant. We already know this |
2965 | satisfies CONSTANT_P. */ | |
2966 | ||
2967 | bool | |
2968 | legitimate_constant_p (rtx x) | |
2969 | { | |
5751a10b JJ |
2970 | switch (GET_CODE (x)) |
2971 | { | |
5751a10b | 2972 | case CONST: |
208384fd EB |
2973 | case SYMBOL_REF: |
2974 | if (sparc_tls_referenced_p (x)) | |
5751a10b JJ |
2975 | return false; |
2976 | break; | |
2977 | ||
2978 | case CONST_DOUBLE: | |
2979 | if (GET_MODE (x) == VOIDmode) | |
2980 | return true; | |
2981 | ||
2982 | /* Floating point constants are generally not ok. | |
2983 | The only exception is 0.0 in VIS. */ | |
2984 | if (TARGET_VIS | |
bea5071f EB |
2985 | && SCALAR_FLOAT_MODE_P (GET_MODE (x)) |
2986 | && const_zero_operand (x, GET_MODE (x))) | |
2987 | return true; | |
2988 | ||
2989 | return false; | |
2990 | ||
2991 | case CONST_VECTOR: | |
2992 | /* Vector constants are generally not ok. | |
2993 | The only exception is 0 in VIS. */ | |
2994 | if (TARGET_VIS | |
0e5d569c | 2995 | && const_zero_operand (x, GET_MODE (x))) |
5751a10b JJ |
2996 | return true; |
2997 | ||
2998 | return false; | |
2999 | ||
3000 | default: | |
3001 | break; | |
3002 | } | |
3003 | ||
3004 | return true; | |
3005 | } | |
3006 | ||
3007 | /* Determine if a given RTX is a valid constant address. */ | |
3008 | ||
3009 | bool | |
3010 | constant_address_p (rtx x) | |
3011 | { | |
3012 | switch (GET_CODE (x)) | |
3013 | { | |
3014 | case LABEL_REF: | |
3015 | case CONST_INT: | |
3016 | case HIGH: | |
3017 | return true; | |
3018 | ||
3019 | case CONST: | |
3020 | if (flag_pic && pic_address_needs_scratch (x)) | |
3021 | return false; | |
3022 | return legitimate_constant_p (x); | |
3023 | ||
3024 | case SYMBOL_REF: | |
3025 | return !flag_pic && legitimate_constant_p (x); | |
3026 | ||
3027 | default: | |
3028 | return false; | |
3029 | } | |
3030 | } | |
3031 | ||
3032 | /* Nonzero if the constant value X is a legitimate general operand | |
3033 | when generating PIC code. It is given that flag_pic is on and | |
3034 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
3035 | ||
3036 | bool | |
3037 | legitimate_pic_operand_p (rtx x) | |
3038 | { | |
3039 | if (pic_address_needs_scratch (x)) | |
3040 | return false; | |
208384fd | 3041 | if (sparc_tls_referenced_p (x)) |
5751a10b JJ |
3042 | return false; |
3043 | return true; | |
3044 | } | |
3045 | ||
3046 | /* Return nonzero if ADDR is a valid memory address. | |
3047 | STRICT specifies whether strict register checking applies. */ | |
4900aa61 | 3048 | |
c6c3dba9 PB |
3049 | static bool |
3050 | sparc_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict) | |
5751a10b | 3051 | { |
f1b259d5 | 3052 | rtx rs1 = NULL, rs2 = NULL, imm1 = NULL; |
5751a10b JJ |
3053 | |
3054 | if (REG_P (addr) || GET_CODE (addr) == SUBREG) | |
3055 | rs1 = addr; | |
3056 | else if (GET_CODE (addr) == PLUS) | |
3057 | { | |
3058 | rs1 = XEXP (addr, 0); | |
3059 | rs2 = XEXP (addr, 1); | |
3060 | ||
3061 | /* Canonicalize. REG comes first, if there are no regs, | |
3062 | LO_SUM comes first. */ | |
3063 | if (!REG_P (rs1) | |
3064 | && GET_CODE (rs1) != SUBREG | |
3065 | && (REG_P (rs2) | |
3066 | || GET_CODE (rs2) == SUBREG | |
3067 | || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM))) | |
3068 | { | |
3069 | rs1 = XEXP (addr, 1); | |
3070 | rs2 = XEXP (addr, 0); | |
3071 | } | |
3072 | ||
3073 | if ((flag_pic == 1 | |
3074 | && rs1 == pic_offset_table_rtx | |
3075 | && !REG_P (rs2) | |
3076 | && GET_CODE (rs2) != SUBREG | |
3077 | && GET_CODE (rs2) != LO_SUM | |
3078 | && GET_CODE (rs2) != MEM | |
208384fd | 3079 | && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2)) |
5751a10b JJ |
3080 | && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode) |
3081 | && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2))) | |
3082 | || ((REG_P (rs1) | |
3083 | || GET_CODE (rs1) == SUBREG) | |
3084 | && RTX_OK_FOR_OFFSET_P (rs2))) | |
3085 | { | |
3086 | imm1 = rs2; | |
3087 | rs2 = NULL; | |
3088 | } | |
3089 | else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG) | |
3090 | && (REG_P (rs2) || GET_CODE (rs2) == SUBREG)) | |
3091 | { | |
39ba2f92 EB |
3092 | /* We prohibit REG + REG for TFmode when there are no quad move insns |
3093 | and we consequently need to split. We do this because REG+REG | |
3094 | is not an offsettable address. If we get the situation in reload | |
5751a10b JJ |
3095 | where source and destination of a movtf pattern are both MEMs with |
3096 | REG+REG address, then only one of them gets converted to an | |
39ba2f92 | 3097 | offsettable address. */ |
5751a10b | 3098 | if (mode == TFmode |
39ba2f92 | 3099 | && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD)) |
5751a10b JJ |
3100 | return 0; |
3101 | ||
3102 | /* We prohibit REG + REG on ARCH32 if not optimizing for | |
3103 | DFmode/DImode because then mem_min_alignment is likely to be zero | |
3104 | after reload and the forced split would lack a matching splitter | |
3105 | pattern. */ | |
3106 | if (TARGET_ARCH32 && !optimize | |
3107 | && (mode == DFmode || mode == DImode)) | |
3108 | return 0; | |
3109 | } | |
3110 | else if (USE_AS_OFFSETABLE_LO10 | |
3111 | && GET_CODE (rs1) == LO_SUM | |
3112 | && TARGET_ARCH64 | |
3113 | && ! TARGET_CM_MEDMID | |
3114 | && RTX_OK_FOR_OLO10_P (rs2)) | |
3115 | { | |
5751a10b JJ |
3116 | rs2 = NULL; |
3117 | imm1 = XEXP (rs1, 1); | |
3118 | rs1 = XEXP (rs1, 0); | |
208384fd EB |
3119 | if (!CONSTANT_P (imm1) |
3120 | || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1))) | |
5751a10b JJ |
3121 | return 0; |
3122 | } | |
3123 | } | |
3124 | else if (GET_CODE (addr) == LO_SUM) | |
3125 | { | |
3126 | rs1 = XEXP (addr, 0); | |
3127 | imm1 = XEXP (addr, 1); | |
3128 | ||
208384fd EB |
3129 | if (!CONSTANT_P (imm1) |
3130 | || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1))) | |
5751a10b JJ |
3131 | return 0; |
3132 | ||
f1b259d5 EB |
3133 | /* We can't allow TFmode in 32-bit mode, because an offset greater |
3134 | than the alignment (8) may cause the LO_SUM to overflow. */ | |
d24088cc | 3135 | if (mode == TFmode && TARGET_ARCH32) |
f1b259d5 | 3136 | return 0; |
5751a10b JJ |
3137 | } |
3138 | else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr)) | |
3139 | return 1; | |
3140 | else | |
3141 | return 0; | |
3142 | ||
3143 | if (GET_CODE (rs1) == SUBREG) | |
3144 | rs1 = SUBREG_REG (rs1); | |
3145 | if (!REG_P (rs1)) | |
3146 | return 0; | |
3147 | ||
3148 | if (rs2) | |
3149 | { | |
3150 | if (GET_CODE (rs2) == SUBREG) | |
3151 | rs2 = SUBREG_REG (rs2); | |
3152 | if (!REG_P (rs2)) | |
3153 | return 0; | |
3154 | } | |
3155 | ||
3156 | if (strict) | |
3157 | { | |
3158 | if (!REGNO_OK_FOR_BASE_P (REGNO (rs1)) | |
3159 | || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2)))) | |
3160 | return 0; | |
3161 | } | |
3162 | else | |
3163 | { | |
3164 | if ((REGNO (rs1) >= 32 | |
3165 | && REGNO (rs1) != FRAME_POINTER_REGNUM | |
3166 | && REGNO (rs1) < FIRST_PSEUDO_REGISTER) | |
3167 | || (rs2 | |
3168 | && (REGNO (rs2) >= 32 | |
3169 | && REGNO (rs2) != FRAME_POINTER_REGNUM | |
3170 | && REGNO (rs2) < FIRST_PSEUDO_REGISTER))) | |
3171 | return 0; | |
3172 | } | |
3173 | return 1; | |
3174 | } | |
3175 | ||
3176 | /* Construct the SYMBOL_REF for the tls_get_offset function. */ | |
3177 | ||
3178 | static GTY(()) rtx sparc_tls_symbol; | |
38fc66ba | 3179 | |
5751a10b JJ |
3180 | static rtx |
3181 | sparc_tls_get_addr (void) | |
3182 | { | |
3183 | if (!sparc_tls_symbol) | |
3184 | sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr"); | |
3185 | ||
3186 | return sparc_tls_symbol; | |
3187 | } | |
3188 | ||
3189 | static rtx | |
3190 | sparc_tls_got (void) | |
3191 | { | |
3192 | rtx temp; | |
3193 | if (flag_pic) | |
3194 | { | |
e3b5732b | 3195 | crtl->uses_pic_offset_table = 1; |
5751a10b JJ |
3196 | return pic_offset_table_rtx; |
3197 | } | |
3198 | ||
3199 | if (!global_offset_table) | |
3200 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
3201 | temp = gen_reg_rtx (Pmode); | |
3202 | emit_move_insn (temp, global_offset_table); | |
3203 | return temp; | |
3204 | } | |
3205 | ||
208384fd | 3206 | /* Return true if X contains a thread-local symbol. */ |
38fc66ba | 3207 | |
208384fd | 3208 | static bool |
38fc66ba EB |
3209 | sparc_tls_referenced_p (rtx x) |
3210 | { | |
3211 | if (!TARGET_HAVE_TLS) | |
3212 | return false; | |
3213 | ||
208384fd EB |
3214 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS) |
3215 | x = XEXP (XEXP (x, 0), 0); | |
3216 | ||
3217 | if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x)) | |
3218 | return true; | |
3219 | ||
3220 | /* That's all we handle in legitimize_tls_address for now. */ | |
3221 | return false; | |
38fc66ba | 3222 | } |
5751a10b JJ |
3223 | |
3224 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
3225 | this (thread-local) address. */ | |
3226 | ||
208384fd | 3227 | static rtx |
5751a10b JJ |
3228 | legitimize_tls_address (rtx addr) |
3229 | { | |
3230 | rtx temp1, temp2, temp3, ret, o0, got, insn; | |
3231 | ||
b3a13419 | 3232 | gcc_assert (can_create_pseudo_p ()); |
5751a10b JJ |
3233 | |
3234 | if (GET_CODE (addr) == SYMBOL_REF) | |
3235 | switch (SYMBOL_REF_TLS_MODEL (addr)) | |
3236 | { | |
3237 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
3238 | start_sequence (); | |
3239 | temp1 = gen_reg_rtx (SImode); | |
3240 | temp2 = gen_reg_rtx (SImode); | |
3241 | ret = gen_reg_rtx (Pmode); | |
3242 | o0 = gen_rtx_REG (Pmode, 8); | |
3243 | got = sparc_tls_got (); | |
3244 | emit_insn (gen_tgd_hi22 (temp1, addr)); | |
3245 | emit_insn (gen_tgd_lo10 (temp2, temp1, addr)); | |
3246 | if (TARGET_ARCH32) | |
3247 | { | |
3248 | emit_insn (gen_tgd_add32 (o0, got, temp2, addr)); | |
3249 | insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (), | |
3250 | addr, const1_rtx)); | |
3251 | } | |
3252 | else | |
3253 | { | |
3254 | emit_insn (gen_tgd_add64 (o0, got, temp2, addr)); | |
3255 | insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (), | |
3256 | addr, const1_rtx)); | |
3257 | } | |
3258 | CALL_INSN_FUNCTION_USAGE (insn) | |
3259 | = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0), | |
3260 | CALL_INSN_FUNCTION_USAGE (insn)); | |
3261 | insn = get_insns (); | |
3262 | end_sequence (); | |
3263 | emit_libcall_block (insn, ret, o0, addr); | |
3264 | break; | |
3265 | ||
3266 | case TLS_MODEL_LOCAL_DYNAMIC: | |
3267 | start_sequence (); | |
3268 | temp1 = gen_reg_rtx (SImode); | |
3269 | temp2 = gen_reg_rtx (SImode); | |
3270 | temp3 = gen_reg_rtx (Pmode); | |
3271 | ret = gen_reg_rtx (Pmode); | |
3272 | o0 = gen_rtx_REG (Pmode, 8); | |
3273 | got = sparc_tls_got (); | |
3274 | emit_insn (gen_tldm_hi22 (temp1)); | |
3275 | emit_insn (gen_tldm_lo10 (temp2, temp1)); | |
3276 | if (TARGET_ARCH32) | |
3277 | { | |
3278 | emit_insn (gen_tldm_add32 (o0, got, temp2)); | |
3279 | insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (), | |
3280 | const1_rtx)); | |
3281 | } | |
3282 | else | |
3283 | { | |
3284 | emit_insn (gen_tldm_add64 (o0, got, temp2)); | |
3285 | insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (), | |
3286 | const1_rtx)); | |
3287 | } | |
3288 | CALL_INSN_FUNCTION_USAGE (insn) | |
3289 | = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0), | |
3290 | CALL_INSN_FUNCTION_USAGE (insn)); | |
3291 | insn = get_insns (); | |
3292 | end_sequence (); | |
3293 | emit_libcall_block (insn, temp3, o0, | |
3294 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
3295 | UNSPEC_TLSLD_BASE)); | |
3296 | temp1 = gen_reg_rtx (SImode); | |
3297 | temp2 = gen_reg_rtx (SImode); | |
3298 | emit_insn (gen_tldo_hix22 (temp1, addr)); | |
3299 | emit_insn (gen_tldo_lox10 (temp2, temp1, addr)); | |
3300 | if (TARGET_ARCH32) | |
3301 | emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr)); | |
3302 | else | |
3303 | emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr)); | |
3304 | break; | |
3305 | ||
3306 | case TLS_MODEL_INITIAL_EXEC: | |
3307 | temp1 = gen_reg_rtx (SImode); | |
3308 | temp2 = gen_reg_rtx (SImode); | |
3309 | temp3 = gen_reg_rtx (Pmode); | |
3310 | got = sparc_tls_got (); | |
3311 | emit_insn (gen_tie_hi22 (temp1, addr)); | |
3312 | emit_insn (gen_tie_lo10 (temp2, temp1, addr)); | |
3313 | if (TARGET_ARCH32) | |
3314 | emit_insn (gen_tie_ld32 (temp3, got, temp2, addr)); | |
3315 | else | |
3316 | emit_insn (gen_tie_ld64 (temp3, got, temp2, addr)); | |
3317 | if (TARGET_SUN_TLS) | |
3318 | { | |
3319 | ret = gen_reg_rtx (Pmode); | |
3320 | if (TARGET_ARCH32) | |
3321 | emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7), | |
3322 | temp3, addr)); | |
3323 | else | |
3324 | emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7), | |
3325 | temp3, addr)); | |
3326 | } | |
3327 | else | |
3328 | ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3); | |
3329 | break; | |
3330 | ||
3331 | case TLS_MODEL_LOCAL_EXEC: | |
3332 | temp1 = gen_reg_rtx (Pmode); | |
3333 | temp2 = gen_reg_rtx (Pmode); | |
3334 | if (TARGET_ARCH32) | |
3335 | { | |
3336 | emit_insn (gen_tle_hix22_sp32 (temp1, addr)); | |
3337 | emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr)); | |
3338 | } | |
3339 | else | |
3340 | { | |
3341 | emit_insn (gen_tle_hix22_sp64 (temp1, addr)); | |
3342 | emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr)); | |
3343 | } | |
3344 | ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2); | |
3345 | break; | |
3346 | ||
3347 | default: | |
f5f7d171 | 3348 | gcc_unreachable (); |
5751a10b JJ |
3349 | } |
3350 | ||
208384fd EB |
3351 | else if (GET_CODE (addr) == CONST) |
3352 | { | |
3353 | rtx base, offset; | |
3354 | ||
3355 | gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS); | |
3356 | ||
3357 | base = legitimize_tls_address (XEXP (XEXP (addr, 0), 0)); | |
3358 | offset = XEXP (XEXP (addr, 0), 1); | |
3359 | ||
3360 | base = force_operand (base, NULL_RTX); | |
3361 | if (!(GET_CODE (offset) == CONST_INT && SMALL_INT (offset))) | |
3362 | offset = force_reg (Pmode, offset); | |
3363 | ret = gen_rtx_PLUS (Pmode, base, offset); | |
3364 | } | |
3365 | ||
5751a10b | 3366 | else |
f5f7d171 | 3367 | gcc_unreachable (); /* for now ... */ |
5751a10b JJ |
3368 | |
3369 | return ret; | |
3370 | } | |
3371 | ||
e0d80184 DM |
3372 | /* Legitimize PIC addresses. If the address is already position-independent, |
3373 | we return ORIG. Newly generated position-independent addresses go into a | |
88cad84b | 3374 | reg. This is REG if nonzero, otherwise we allocate register(s) as |
e0d80184 | 3375 | necessary. */ |
795068a4 | 3376 | |
208384fd EB |
3377 | static rtx |
3378 | legitimize_pic_address (rtx orig, rtx reg) | |
e0d80184 | 3379 | { |
878ee0ab DM |
3380 | bool gotdata_op = false; |
3381 | ||
1910440e RS |
3382 | if (GET_CODE (orig) == SYMBOL_REF |
3383 | /* See the comment in sparc_expand_move. */ | |
3384 | || (TARGET_VXWORKS_RTP && GET_CODE (orig) == LABEL_REF)) | |
82d6b402 | 3385 | { |
e0d80184 DM |
3386 | rtx pic_ref, address; |
3387 | rtx insn; | |
82d6b402 | 3388 | |
e0d80184 | 3389 | if (reg == 0) |
82d6b402 | 3390 | { |
f5f7d171 JM |
3391 | gcc_assert (! reload_in_progress && ! reload_completed); |
3392 | reg = gen_reg_rtx (Pmode); | |
82d6b402 | 3393 | } |
795068a4 | 3394 | |
e0d80184 | 3395 | if (flag_pic == 2) |
4fb4e4b8 | 3396 | { |
e0d80184 DM |
3397 | /* If not during reload, allocate another temp reg here for loading |
3398 | in the address, so that these instructions can be optimized | |
3399 | properly. */ | |
3400 | rtx temp_reg = ((reload_in_progress || reload_completed) | |
3401 | ? reg : gen_reg_rtx (Pmode)); | |
3402 | ||
3403 | /* Must put the SYMBOL_REF inside an UNSPEC here so that cse | |
3404 | won't get confused into thinking that these two instructions | |
3405 | are loading in the true address of the symbol. If in the | |
3406 | future a PIC rtx exists, that should be used instead. */ | |
bea5071f | 3407 | if (TARGET_ARCH64) |
be3f1ff5 | 3408 | { |
bea5071f EB |
3409 | emit_insn (gen_movdi_high_pic (temp_reg, orig)); |
3410 | emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
be3f1ff5 DM |
3411 | } |
3412 | else | |
3413 | { | |
bea5071f EB |
3414 | emit_insn (gen_movsi_high_pic (temp_reg, orig)); |
3415 | emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
be3f1ff5 | 3416 | } |
e0d80184 | 3417 | address = temp_reg; |
878ee0ab | 3418 | gotdata_op = true; |
4fb4e4b8 DE |
3419 | } |
3420 | else | |
e0d80184 DM |
3421 | address = orig; |
3422 | ||
e3b5732b | 3423 | crtl->uses_pic_offset_table = 1; |
878ee0ab DM |
3424 | if (gotdata_op) |
3425 | { | |
3426 | if (TARGET_ARCH64) | |
3427 | insn = emit_insn (gen_movdi_pic_gotdata_op (reg, pic_offset_table_rtx, | |
3428 | address, orig)); | |
3429 | else | |
3430 | insn = emit_insn (gen_movsi_pic_gotdata_op (reg, pic_offset_table_rtx, | |
3431 | address, orig)); | |
3432 | } | |
3433 | else | |
3434 | { | |
3435 | pic_ref = gen_const_mem (Pmode, | |
3436 | gen_rtx_PLUS (Pmode, | |
3437 | pic_offset_table_rtx, address)); | |
3438 | insn = emit_move_insn (reg, pic_ref); | |
3439 | } | |
e0d80184 DM |
3440 | /* Put a REG_EQUAL note on this insn, so that it can be optimized |
3441 | by loop. */ | |
bd94cb6e | 3442 | set_unique_reg_note (insn, REG_EQUAL, orig); |
e0d80184 | 3443 | return reg; |
795068a4 | 3444 | } |
e0d80184 | 3445 | else if (GET_CODE (orig) == CONST) |
795068a4 | 3446 | { |
e0d80184 | 3447 | rtx base, offset; |
795068a4 | 3448 | |
e0d80184 DM |
3449 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
3450 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
3451 | return orig; | |
82d6b402 | 3452 | |
e0d80184 | 3453 | if (reg == 0) |
4fb4e4b8 | 3454 | { |
f5f7d171 JM |
3455 | gcc_assert (! reload_in_progress && ! reload_completed); |
3456 | reg = gen_reg_rtx (Pmode); | |
4fb4e4b8 | 3457 | } |
e0d80184 | 3458 | |
f5f7d171 | 3459 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
208384fd EB |
3460 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg); |
3461 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
3462 | base == reg ? NULL_RTX : reg); | |
61a66555 | 3463 | |
e0d80184 DM |
3464 | if (GET_CODE (offset) == CONST_INT) |
3465 | { | |
3466 | if (SMALL_INT (offset)) | |
ed8908e7 | 3467 | return plus_constant (base, INTVAL (offset)); |
e0d80184 DM |
3468 | else if (! reload_in_progress && ! reload_completed) |
3469 | offset = force_reg (Pmode, offset); | |
3470 | else | |
3471 | /* If we reach here, then something is seriously wrong. */ | |
f5f7d171 | 3472 | gcc_unreachable (); |
e0d80184 DM |
3473 | } |
3474 | return gen_rtx_PLUS (Pmode, base, offset); | |
795068a4 | 3475 | } |
e0d80184 DM |
3476 | else if (GET_CODE (orig) == LABEL_REF) |
3477 | /* ??? Why do we do this? */ | |
3478 | /* Now movsi_pic_label_ref uses it, but we ought to be checking that | |
3479 | the register is live instead, in case it is eliminated. */ | |
e3b5732b | 3480 | crtl->uses_pic_offset_table = 1; |
795068a4 | 3481 | |
e0d80184 DM |
3482 | return orig; |
3483 | } | |
795068a4 | 3484 | |
5751a10b JJ |
3485 | /* Try machine-dependent ways of modifying an illegitimate address X |
3486 | to be legitimate. If we find one, return the new, valid address. | |
3487 | ||
3488 | OLDX is the address as it was before break_out_memory_refs was called. | |
3489 | In some cases it is useful to look at this to decide what needs to be done. | |
3490 | ||
506d7b68 PB |
3491 | MODE is the mode of the operand pointed to by X. |
3492 | ||
3493 | On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ | |
5751a10b | 3494 | |
208384fd | 3495 | static rtx |
506d7b68 PB |
3496 | sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
3497 | enum machine_mode mode) | |
5751a10b JJ |
3498 | { |
3499 | rtx orig_x = x; | |
3500 | ||
3501 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT) | |
3502 | x = gen_rtx_PLUS (Pmode, XEXP (x, 1), | |
3503 | force_operand (XEXP (x, 0), NULL_RTX)); | |
3504 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT) | |
3505 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
3506 | force_operand (XEXP (x, 1), NULL_RTX)); | |
3507 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS) | |
3508 | x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX), | |
3509 | XEXP (x, 1)); | |
3510 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS) | |
3511 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
3512 | force_operand (XEXP (x, 1), NULL_RTX)); | |
3513 | ||
c6c3dba9 | 3514 | if (x != orig_x && sparc_legitimate_address_p (mode, x, FALSE)) |
5751a10b JJ |
3515 | return x; |
3516 | ||
208384fd | 3517 | if (sparc_tls_referenced_p (x)) |
5751a10b JJ |
3518 | x = legitimize_tls_address (x); |
3519 | else if (flag_pic) | |
208384fd | 3520 | x = legitimize_pic_address (x, NULL_RTX); |
5751a10b JJ |
3521 | else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1))) |
3522 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
3523 | copy_to_mode_reg (Pmode, XEXP (x, 1))); | |
3524 | else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0))) | |
3525 | x = gen_rtx_PLUS (Pmode, XEXP (x, 1), | |
3526 | copy_to_mode_reg (Pmode, XEXP (x, 0))); | |
3527 | else if (GET_CODE (x) == SYMBOL_REF | |
3528 | || GET_CODE (x) == CONST | |
208384fd | 3529 | || GET_CODE (x) == LABEL_REF) |
5751a10b | 3530 | x = copy_to_suggested_reg (x, NULL_RTX, Pmode); |
208384fd | 3531 | |
5751a10b JJ |
3532 | return x; |
3533 | } | |
3534 | ||
277e2873 AS |
3535 | /* Return true if ADDR (a legitimate address expression) |
3536 | has an effect that depends on the machine mode it is used for. | |
3537 | ||
3538 | In PIC mode, | |
3539 | ||
3540 | (mem:HI [%l7+a]) | |
3541 | ||
3542 | is not equivalent to | |
3543 | ||
3544 | (mem:QI [%l7+a]) (mem:QI [%l7+a+1]) | |
3545 | ||
3546 | because [%l7+a+1] is interpreted as the address of (a+1). */ | |
3547 | ||
3548 | ||
3549 | static bool | |
3550 | sparc_mode_dependent_address_p (const_rtx addr) | |
3551 | { | |
3552 | if (flag_pic && GET_CODE (addr) == PLUS) | |
3553 | { | |
3554 | rtx op0 = XEXP (addr, 0); | |
3555 | rtx op1 = XEXP (addr, 1); | |
3556 | if (op0 == pic_offset_table_rtx | |
3557 | && SYMBOLIC_CONST (op1)) | |
3558 | return true; | |
3559 | } | |
3560 | ||
3561 | return false; | |
3562 | } | |
3563 | ||
9fd52c6c DM |
3564 | #ifdef HAVE_GAS_HIDDEN |
3565 | # define USE_HIDDEN_LINKONCE 1 | |
3566 | #else | |
3567 | # define USE_HIDDEN_LINKONCE 0 | |
3568 | #endif | |
795068a4 | 3569 | |
9ac617d4 | 3570 | static void |
9fd52c6c | 3571 | get_pc_thunk_name (char name[32], unsigned int regno) |
e0d80184 | 3572 | { |
9fd52c6c | 3573 | const char *pic_name = reg_names[regno]; |
4fb4e4b8 | 3574 | |
9fd52c6c DM |
3575 | /* Skip the leading '%' as that cannot be used in a |
3576 | symbol name. */ | |
3577 | pic_name += 1; | |
82d6b402 | 3578 | |
9fd52c6c DM |
3579 | if (USE_HIDDEN_LINKONCE) |
3580 | sprintf (name, "__sparc_get_pc_thunk.%s", pic_name); | |
5e77eb53 | 3581 | else |
9fd52c6c | 3582 | ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno); |
5e77eb53 EB |
3583 | } |
3584 | ||
3585 | /* Emit code to load the PIC register. */ | |
3586 | ||
3587 | static void | |
9fd52c6c | 3588 | load_pic_register (void) |
5e77eb53 EB |
3589 | { |
3590 | int orig_flag_pic = flag_pic; | |
3591 | ||
1910440e RS |
3592 | if (TARGET_VXWORKS_RTP) |
3593 | { | |
3594 | emit_insn (gen_vxworks_load_got ()); | |
c41c1387 | 3595 | emit_use (pic_offset_table_rtx); |
1910440e RS |
3596 | return; |
3597 | } | |
3598 | ||
5e77eb53 | 3599 | /* If we haven't initialized the special PIC symbols, do so now. */ |
9fd52c6c | 3600 | if (!pic_helper_needed) |
5e77eb53 | 3601 | { |
9fd52c6c DM |
3602 | char name[32]; |
3603 | ||
3604 | pic_helper_needed = true; | |
3605 | ||
3606 | get_pc_thunk_name (name, REGNO (pic_offset_table_rtx)); | |
3607 | pic_helper_symbol = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); | |
3608 | ||
5e77eb53 | 3609 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); |
e0d80184 | 3610 | } |
82d6b402 | 3611 | |
ef573211 | 3612 | flag_pic = 0; |
eb7a7903 EB |
3613 | if (TARGET_ARCH64) |
3614 | emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx, global_offset_table, | |
5e77eb53 | 3615 | pic_helper_symbol)); |
eb7a7903 EB |
3616 | else |
3617 | emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx, global_offset_table, | |
5e77eb53 | 3618 | pic_helper_symbol)); |
e0d80184 | 3619 | flag_pic = orig_flag_pic; |
82d6b402 | 3620 | |
e0d80184 DM |
3621 | /* Need to emit this whether or not we obey regdecls, |
3622 | since setjmp/longjmp can cause life info to screw up. | |
3623 | ??? In the case where we don't obey regdecls, this is not sufficient | |
3624 | since we may not fall out the bottom. */ | |
c41c1387 | 3625 | emit_use (pic_offset_table_rtx); |
795068a4 | 3626 | } |
1910440e RS |
3627 | |
3628 | /* Emit a call instruction with the pattern given by PAT. ADDR is the | |
3629 | address of the call target. */ | |
3630 | ||
3631 | void | |
3632 | sparc_emit_call_insn (rtx pat, rtx addr) | |
3633 | { | |
3634 | rtx insn; | |
3635 | ||
3636 | insn = emit_call_insn (pat); | |
3637 | ||
3638 | /* The PIC register is live on entry to VxWorks PIC PLT entries. */ | |
3639 | if (TARGET_VXWORKS_RTP | |
3640 | && flag_pic | |
3641 | && GET_CODE (addr) == SYMBOL_REF | |
3642 | && (SYMBOL_REF_DECL (addr) | |
3643 | ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr)) | |
3644 | : !SYMBOL_REF_LOCAL_P (addr))) | |
3645 | { | |
3646 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); | |
e3b5732b | 3647 | crtl->uses_pic_offset_table = 1; |
1910440e RS |
3648 | } |
3649 | } | |
ab835497 | 3650 | \f |
e0d80184 | 3651 | /* Return 1 if RTX is a MEM which is known to be aligned to at |
7a31a340 | 3652 | least a DESIRED byte boundary. */ |
a3ee5899 | 3653 | |
e0d80184 | 3654 | int |
fc27d102 | 3655 | mem_min_alignment (rtx mem, int desired) |
ab835497 | 3656 | { |
e0d80184 DM |
3657 | rtx addr, base, offset; |
3658 | ||
3659 | /* If it's not a MEM we can't accept it. */ | |
3660 | if (GET_CODE (mem) != MEM) | |
3661 | return 0; | |
3662 | ||
167a1354 | 3663 | /* Obviously... */ |
0f95e914 EB |
3664 | if (!TARGET_UNALIGNED_DOUBLES |
3665 | && MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired) | |
167a1354 EB |
3666 | return 1; |
3667 | ||
3668 | /* ??? The rest of the function predates MEM_ALIGN so | |
3669 | there is probably a bit of redundancy. */ | |
e0d80184 DM |
3670 | addr = XEXP (mem, 0); |
3671 | base = offset = NULL_RTX; | |
3672 | if (GET_CODE (addr) == PLUS) | |
ab835497 | 3673 | { |
e0d80184 | 3674 | if (GET_CODE (XEXP (addr, 0)) == REG) |
61a55e8b | 3675 | { |
e0d80184 DM |
3676 | base = XEXP (addr, 0); |
3677 | ||
3678 | /* What we are saying here is that if the base | |
3679 | REG is aligned properly, the compiler will make | |
3680 | sure any REG based index upon it will be so | |
3681 | as well. */ | |
3682 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3683 | offset = XEXP (addr, 1); | |
61a55e8b | 3684 | else |
e0d80184 | 3685 | offset = const0_rtx; |
61a55e8b | 3686 | } |
ab835497 | 3687 | } |
e0d80184 | 3688 | else if (GET_CODE (addr) == REG) |
ab835497 | 3689 | { |
e0d80184 DM |
3690 | base = addr; |
3691 | offset = const0_rtx; | |
ab835497 | 3692 | } |
82d6b402 | 3693 | |
e0d80184 | 3694 | if (base != NULL_RTX) |
795068a4 | 3695 | { |
e0d80184 DM |
3696 | int regno = REGNO (base); |
3697 | ||
563c12b0 | 3698 | if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM) |
61a55e8b | 3699 | { |
e0d80184 DM |
3700 | /* Check if the compiler has recorded some information |
3701 | about the alignment of the base REG. If reload has | |
021e2ecc JJ |
3702 | completed, we already matched with proper alignments. |
3703 | If not running global_alloc, reload might give us | |
3704 | unaligned pointer to local stack though. */ | |
bdb429a5 RK |
3705 | if (((cfun != 0 |
3706 | && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT) | |
021e2ecc | 3707 | || (optimize && reload_completed)) |
bdb429a5 | 3708 | && (INTVAL (offset) & (desired - 1)) == 0) |
e0d80184 | 3709 | return 1; |
61a55e8b | 3710 | } |
795068a4 | 3711 | else |
e0d80184 DM |
3712 | { |
3713 | if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) | |
3714 | return 1; | |
3715 | } | |
795068a4 | 3716 | } |
e0d80184 DM |
3717 | else if (! TARGET_UNALIGNED_DOUBLES |
3718 | || CONSTANT_P (addr) | |
3719 | || GET_CODE (addr) == LO_SUM) | |
795068a4 | 3720 | { |
e0d80184 DM |
3721 | /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES |
3722 | is true, in which case we can only assume that an access is aligned if | |
3723 | it is to a constant address, or the address involves a LO_SUM. */ | |
3724 | return 1; | |
795068a4 | 3725 | } |
4900aa61 | 3726 | |
e0d80184 DM |
3727 | /* An obviously unaligned address. */ |
3728 | return 0; | |
795068a4 | 3729 | } |
e0d80184 | 3730 | |
ab835497 | 3731 | \f |
61a55e8b | 3732 | /* Vectors to keep interesting information about registers where it can easily |
01d3224a | 3733 | be got. We used to use the actual mode value as the bit number, but there |
61a55e8b DE |
3734 | are more than 32 modes now. Instead we use two tables: one indexed by |
3735 | hard register number, and one indexed by mode. */ | |
3736 | ||
3737 | /* The purpose of sparc_mode_class is to shrink the range of modes so that | |
a7b376ee | 3738 | they all fit (as bit numbers) in a 32-bit word (again). Each real mode is |
61a55e8b DE |
3739 | mapped into one sparc_mode_class mode. */ |
3740 | ||
3741 | enum sparc_mode_class { | |
61a55e8b | 3742 | S_MODE, D_MODE, T_MODE, O_MODE, |
c4ce6853 DE |
3743 | SF_MODE, DF_MODE, TF_MODE, OF_MODE, |
3744 | CC_MODE, CCFP_MODE | |
61a55e8b | 3745 | }; |
ab835497 | 3746 | |
61a55e8b DE |
3747 | /* Modes for single-word and smaller quantities. */ |
3748 | #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
3749 | ||
3750 | /* Modes for double-word and smaller quantities. */ | |
3751 | #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) | |
3752 | ||
3753 | /* Modes for quad-word and smaller quantities. */ | |
3754 | #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
ab835497 | 3755 | |
d0cee9ba JJ |
3756 | /* Modes for 8-word and smaller quantities. */ |
3757 | #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) | |
3758 | ||
1e4eb8d1 JW |
3759 | /* Modes for single-float quantities. We must allow any single word or |
3760 | smaller quantity. This is because the fix/float conversion instructions | |
3761 | take integer inputs/outputs from the float registers. */ | |
3762 | #define SF_MODES (S_MODES) | |
ab835497 | 3763 | |
61a55e8b | 3764 | /* Modes for double-float and smaller quantities. */ |
948bf106 | 3765 | #define DF_MODES (D_MODES) |
61a55e8b DE |
3766 | |
3767 | /* Modes for quad-float and smaller quantities. */ | |
948bf106 | 3768 | #define TF_MODES (DF_MODES | (1 << (int) TF_MODE)) |
61a55e8b | 3769 | |
948bf106 EB |
3770 | /* Modes for quad-float pairs and smaller quantities. */ |
3771 | #define OF_MODES (TF_MODES | (1 << (int) OF_MODE)) | |
d0cee9ba | 3772 | |
948bf106 EB |
3773 | /* Modes for double-float only quantities. */ |
3774 | #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) | |
d0cee9ba | 3775 | |
948bf106 EB |
3776 | /* Modes for quad-float and double-float only quantities. */ |
3777 | #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE)) | |
d0cee9ba | 3778 | |
948bf106 EB |
3779 | /* Modes for quad-float pairs and double-float only quantities. */ |
3780 | #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE)) | |
ab835497 | 3781 | |
c4ce6853 DE |
3782 | /* Modes for condition codes. */ |
3783 | #define CC_MODES (1 << (int) CC_MODE) | |
3784 | #define CCFP_MODES (1 << (int) CCFP_MODE) | |
3785 | ||
ab835497 RK |
3786 | /* Value is 1 if register/mode pair is acceptable on sparc. |
3787 | The funny mixture of D and T modes is because integer operations | |
3788 | do not specially operate on tetra quantities, so non-quad-aligned | |
3789 | registers can hold quadword quantities (except %o4 and %i4 because | |
c4ce6853 | 3790 | they cross fixed registers). */ |
ab835497 | 3791 | |
61a55e8b | 3792 | /* This points to either the 32 bit or the 64 bit version. */ |
0b5826ac | 3793 | const int *hard_regno_mode_classes; |
61a55e8b | 3794 | |
0b5826ac | 3795 | static const int hard_32bit_mode_classes[] = { |
c4ce6853 | 3796 | S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, |
ab835497 RK |
3797 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, |
3798 | T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
3799 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
3800 | ||
d0cee9ba JJ |
3801 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
3802 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3803 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3804 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
a9e27770 DE |
3805 | |
3806 | /* FP regs f32 to f63. Only the even numbered registers actually exist, | |
3807 | and none can hold SFmode/SImode values. */ | |
d0cee9ba JJ |
3808 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
3809 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3810 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3811 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
a9e27770 DE |
3812 | |
3813 | /* %fcc[0123] */ | |
c4ce6853 DE |
3814 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
3815 | ||
3816 | /* %icc */ | |
3817 | CC_MODES | |
61a55e8b DE |
3818 | }; |
3819 | ||
0b5826ac | 3820 | static const int hard_64bit_mode_classes[] = { |
c4ce6853 | 3821 | D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 3822 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 3823 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 3824 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 3825 | |
d0cee9ba JJ |
3826 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
3827 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3828 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3829 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
61a55e8b | 3830 | |
a9e27770 | 3831 | /* FP regs f32 to f63. Only the even numbered registers actually exist, |
61a55e8b | 3832 | and none can hold SFmode/SImode values. */ |
d0cee9ba JJ |
3833 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
3834 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3835 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3836 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
61a55e8b DE |
3837 | |
3838 | /* %fcc[0123] */ | |
c4ce6853 DE |
3839 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
3840 | ||
3841 | /* %icc */ | |
3842 | CC_MODES | |
61a55e8b DE |
3843 | }; |
3844 | ||
3845 | int sparc_mode_class [NUM_MACHINE_MODES]; | |
3846 | ||
c4ce6853 DE |
3847 | enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
3848 | ||
61a55e8b | 3849 | static void |
fc27d102 | 3850 | sparc_init_modes (void) |
61a55e8b DE |
3851 | { |
3852 | int i; | |
3853 | ||
61a55e8b DE |
3854 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
3855 | { | |
3856 | switch (GET_MODE_CLASS (i)) | |
3857 | { | |
3858 | case MODE_INT: | |
3859 | case MODE_PARTIAL_INT: | |
3860 | case MODE_COMPLEX_INT: | |
3861 | if (GET_MODE_SIZE (i) <= 4) | |
3862 | sparc_mode_class[i] = 1 << (int) S_MODE; | |
3863 | else if (GET_MODE_SIZE (i) == 8) | |
3864 | sparc_mode_class[i] = 1 << (int) D_MODE; | |
3865 | else if (GET_MODE_SIZE (i) == 16) | |
3866 | sparc_mode_class[i] = 1 << (int) T_MODE; | |
3867 | else if (GET_MODE_SIZE (i) == 32) | |
3868 | sparc_mode_class[i] = 1 << (int) O_MODE; | |
4900aa61 | 3869 | else |
61a55e8b DE |
3870 | sparc_mode_class[i] = 0; |
3871 | break; | |
c75d6010 JM |
3872 | case MODE_VECTOR_INT: |
3873 | if (GET_MODE_SIZE (i) <= 4) | |
3874 | sparc_mode_class[i] = 1 << (int)SF_MODE; | |
3875 | else if (GET_MODE_SIZE (i) == 8) | |
3876 | sparc_mode_class[i] = 1 << (int)DF_MODE; | |
3877 | break; | |
61a55e8b DE |
3878 | case MODE_FLOAT: |
3879 | case MODE_COMPLEX_FLOAT: | |
3880 | if (GET_MODE_SIZE (i) <= 4) | |
3881 | sparc_mode_class[i] = 1 << (int) SF_MODE; | |
3882 | else if (GET_MODE_SIZE (i) == 8) | |
3883 | sparc_mode_class[i] = 1 << (int) DF_MODE; | |
3884 | else if (GET_MODE_SIZE (i) == 16) | |
3885 | sparc_mode_class[i] = 1 << (int) TF_MODE; | |
3886 | else if (GET_MODE_SIZE (i) == 32) | |
3887 | sparc_mode_class[i] = 1 << (int) OF_MODE; | |
4900aa61 | 3888 | else |
61a55e8b DE |
3889 | sparc_mode_class[i] = 0; |
3890 | break; | |
3891 | case MODE_CC: | |
61a55e8b DE |
3892 | if (i == (int) CCFPmode || i == (int) CCFPEmode) |
3893 | sparc_mode_class[i] = 1 << (int) CCFP_MODE; | |
61a55e8b | 3894 | else |
94134f42 ZW |
3895 | sparc_mode_class[i] = 1 << (int) CC_MODE; |
3896 | break; | |
3897 | default: | |
3898 | sparc_mode_class[i] = 0; | |
61a55e8b DE |
3899 | break; |
3900 | } | |
3901 | } | |
3902 | ||
a9e27770 | 3903 | if (TARGET_ARCH64) |
61a55e8b DE |
3904 | hard_regno_mode_classes = hard_64bit_mode_classes; |
3905 | else | |
3906 | hard_regno_mode_classes = hard_32bit_mode_classes; | |
c4ce6853 DE |
3907 | |
3908 | /* Initialize the array used by REGNO_REG_CLASS. */ | |
3909 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3910 | { | |
284d86e9 JC |
3911 | if (i < 16 && TARGET_V8PLUS) |
3912 | sparc_regno_reg_class[i] = I64_REGS; | |
563c12b0 | 3913 | else if (i < 32 || i == FRAME_POINTER_REGNUM) |
c4ce6853 DE |
3914 | sparc_regno_reg_class[i] = GENERAL_REGS; |
3915 | else if (i < 64) | |
3916 | sparc_regno_reg_class[i] = FP_REGS; | |
3917 | else if (i < 96) | |
3918 | sparc_regno_reg_class[i] = EXTRA_FP_REGS; | |
3919 | else if (i < 100) | |
3920 | sparc_regno_reg_class[i] = FPCC_REGS; | |
3921 | else | |
3922 | sparc_regno_reg_class[i] = NO_REGS; | |
3923 | } | |
61a55e8b | 3924 | } |
ab835497 | 3925 | \f |
61a55e8b | 3926 | /* Compute the frame size required by the function. This function is called |
9ac617d4 | 3927 | during the reload pass and also by sparc_expand_prologue. */ |
ab835497 | 3928 | |
6a151f87 | 3929 | HOST_WIDE_INT |
9ac617d4 | 3930 | sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p) |
ab835497 | 3931 | { |
38173d38 | 3932 | int outgoing_args_size = (crtl->outgoing_args_size |
4fb4e4b8 | 3933 | + REG_PARM_STACK_SPACE (current_function_decl)); |
9ac617d4 EB |
3934 | int n_regs = 0; /* N_REGS is the number of 4-byte regs saved thus far. */ |
3935 | int i; | |
61a55e8b | 3936 | |
33074e5f RH |
3937 | if (TARGET_ARCH64) |
3938 | { | |
3939 | for (i = 0; i < 8; i++) | |
6fb5fa3c | 3940 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
33074e5f RH |
3941 | n_regs += 2; |
3942 | } | |
3943 | else | |
3944 | { | |
3945 | for (i = 0; i < 8; i += 2) | |
6fb5fa3c DB |
3946 | if ((df_regs_ever_live_p (i) && ! call_used_regs[i]) |
3947 | || (df_regs_ever_live_p (i+1) && ! call_used_regs[i+1])) | |
61a55e8b | 3948 | n_regs += 2; |
ab835497 RK |
3949 | } |
3950 | ||
33074e5f | 3951 | for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) |
6fb5fa3c DB |
3952 | if ((df_regs_ever_live_p (i) && ! call_used_regs[i]) |
3953 | || (df_regs_ever_live_p (i+1) && ! call_used_regs[i+1])) | |
33074e5f RH |
3954 | n_regs += 2; |
3955 | ||
9ac617d4 | 3956 | /* Set up values for use in prologue and epilogue. */ |
61a55e8b | 3957 | num_gfregs = n_regs; |
ab835497 | 3958 | |
9ac617d4 EB |
3959 | if (leaf_function_p |
3960 | && n_regs == 0 | |
3961 | && size == 0 | |
38173d38 | 3962 | && crtl->outgoing_args_size == 0) |
9ac617d4 | 3963 | actual_fsize = apparent_fsize = 0; |
61a55e8b DE |
3964 | else |
3965 | { | |
225909c3 JS |
3966 | /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */ |
3967 | apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8; | |
61a55e8b DE |
3968 | apparent_fsize += n_regs * 4; |
3969 | actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); | |
3970 | } | |
ab835497 RK |
3971 | |
3972 | /* Make sure nothing can clobber our register windows. | |
3973 | If a SAVE must be done, or there is a stack-local variable, | |
f8ece000 | 3974 | the register window area must be allocated. */ |
9ac617d4 | 3975 | if (! leaf_function_p || size > 0) |
f8ece000 | 3976 | actual_fsize += FIRST_PARM_OFFSET (current_function_decl); |
ab835497 | 3977 | |
61a55e8b DE |
3978 | return SPARC_STACK_ALIGN (actual_fsize); |
3979 | } | |
3980 | ||
9ac617d4 | 3981 | /* Output any necessary .register pseudo-ops. */ |
61a55e8b | 3982 | |
9ac617d4 EB |
3983 | void |
3984 | sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED) | |
61a55e8b | 3985 | { |
9ac617d4 EB |
3986 | #ifdef HAVE_AS_REGISTER_PSEUDO_OP |
3987 | int i; | |
6a151f87 | 3988 | |
9ac617d4 EB |
3989 | if (TARGET_ARCH32) |
3990 | return; | |
3991 | ||
3992 | /* Check if %g[2367] were used without | |
3993 | .register being printed for them already. */ | |
3994 | for (i = 2; i < 8; i++) | |
61a55e8b | 3995 | { |
6fb5fa3c | 3996 | if (df_regs_ever_live_p (i) |
9ac617d4 EB |
3997 | && ! sparc_hard_reg_printed [i]) |
3998 | { | |
3999 | sparc_hard_reg_printed [i] = 1; | |
392e5756 JJ |
4000 | /* %g7 is used as TLS base register, use #ignore |
4001 | for it instead of #scratch. */ | |
4002 | fprintf (file, "\t.register\t%%g%d, #%s\n", i, | |
4003 | i == 7 ? "ignore" : "scratch"); | |
9ac617d4 EB |
4004 | } |
4005 | if (i == 3) i = 5; | |
61a55e8b | 4006 | } |
6a151f87 | 4007 | #endif |
9ac617d4 | 4008 | } |
6a151f87 | 4009 | |
9ac617d4 EB |
4010 | /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET |
4011 | as needed. LOW should be double-word aligned for 32-bit registers. | |
4012 | Return the new OFFSET. */ | |
6a151f87 | 4013 | |
9ac617d4 EB |
4014 | #define SORR_SAVE 0 |
4015 | #define SORR_RESTORE 1 | |
4016 | ||
4017 | static int | |
4018 | save_or_restore_regs (int low, int high, rtx base, int offset, int action) | |
4019 | { | |
4020 | rtx mem, insn; | |
4021 | int i; | |
4022 | ||
4023 | if (TARGET_ARCH64 && high <= 32) | |
4024 | { | |
4025 | for (i = low; i < high; i++) | |
6a151f87 | 4026 | { |
6fb5fa3c | 4027 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
9ac617d4 EB |
4028 | { |
4029 | mem = gen_rtx_MEM (DImode, plus_constant (base, offset)); | |
4030 | set_mem_alias_set (mem, sparc_sr_alias_set); | |
4031 | if (action == SORR_SAVE) | |
4032 | { | |
4033 | insn = emit_move_insn (mem, gen_rtx_REG (DImode, i)); | |
4034 | RTX_FRAME_RELATED_P (insn) = 1; | |
4035 | } | |
4036 | else /* action == SORR_RESTORE */ | |
4037 | emit_move_insn (gen_rtx_REG (DImode, i), mem); | |
4038 | offset += 8; | |
4039 | } | |
6a151f87 | 4040 | } |
9ac617d4 EB |
4041 | } |
4042 | else | |
4043 | { | |
4044 | for (i = low; i < high; i += 2) | |
6a151f87 | 4045 | { |
6fb5fa3c DB |
4046 | bool reg0 = df_regs_ever_live_p (i) && ! call_used_regs[i]; |
4047 | bool reg1 = df_regs_ever_live_p (i+1) && ! call_used_regs[i+1]; | |
9ac617d4 EB |
4048 | enum machine_mode mode; |
4049 | int regno; | |
4050 | ||
4051 | if (reg0 && reg1) | |
4052 | { | |
4053 | mode = i < 32 ? DImode : DFmode; | |
4054 | regno = i; | |
4055 | } | |
4056 | else if (reg0) | |
4057 | { | |
4058 | mode = i < 32 ? SImode : SFmode; | |
4059 | regno = i; | |
4060 | } | |
4061 | else if (reg1) | |
4062 | { | |
4063 | mode = i < 32 ? SImode : SFmode; | |
4064 | regno = i + 1; | |
4065 | offset += 4; | |
4066 | } | |
4067 | else | |
4068 | continue; | |
4069 | ||
4070 | mem = gen_rtx_MEM (mode, plus_constant (base, offset)); | |
4071 | set_mem_alias_set (mem, sparc_sr_alias_set); | |
4072 | if (action == SORR_SAVE) | |
4073 | { | |
4074 | insn = emit_move_insn (mem, gen_rtx_REG (mode, regno)); | |
4075 | RTX_FRAME_RELATED_P (insn) = 1; | |
4076 | } | |
4077 | else /* action == SORR_RESTORE */ | |
4078 | emit_move_insn (gen_rtx_REG (mode, regno), mem); | |
4079 | ||
4080 | /* Always preserve double-word alignment. */ | |
4081 | offset = (offset + 7) & -8; | |
6a151f87 | 4082 | } |
6a151f87 | 4083 | } |
9ac617d4 EB |
4084 | |
4085 | return offset; | |
ab835497 RK |
4086 | } |
4087 | ||
9ac617d4 EB |
4088 | /* Emit code to save call-saved registers. */ |
4089 | ||
4090 | static void | |
f8ece000 | 4091 | emit_save_or_restore_regs (int action) |
1cb36a98 | 4092 | { |
9ac617d4 EB |
4093 | HOST_WIDE_INT offset; |
4094 | rtx base; | |
1cb36a98 | 4095 | |
9ac617d4 | 4096 | offset = frame_base_offset - apparent_fsize; |
1cb36a98 | 4097 | |
f8ece000 | 4098 | if (offset < -4096 || offset + num_gfregs * 4 > 4095) |
1cb36a98 | 4099 | { |
9ac617d4 EB |
4100 | /* ??? This might be optimized a little as %g1 might already have a |
4101 | value close enough that a single add insn will do. */ | |
4102 | /* ??? Although, all of this is probably only a temporary fix | |
4103 | because if %g1 can hold a function result, then | |
4104 | sparc_expand_epilogue will lose (the result will be | |
4105 | clobbered). */ | |
4106 | base = gen_rtx_REG (Pmode, 1); | |
4107 | emit_move_insn (base, GEN_INT (offset)); | |
4108 | emit_insn (gen_rtx_SET (VOIDmode, | |
4109 | base, | |
4110 | gen_rtx_PLUS (Pmode, frame_base_reg, base))); | |
4111 | offset = 0; | |
1cb36a98 | 4112 | } |
9ac617d4 EB |
4113 | else |
4114 | base = frame_base_reg; | |
4115 | ||
f8ece000 EB |
4116 | offset = save_or_restore_regs (0, 8, base, offset, action); |
4117 | save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, action); | |
9ac617d4 | 4118 | } |
08c148a8 | 4119 | |
e54c7471 | 4120 | /* Generate a save_register_window insn. */ |
08c148a8 | 4121 | |
e54c7471 EB |
4122 | static rtx |
4123 | gen_save_register_window (rtx increment) | |
08c148a8 | 4124 | { |
9ac617d4 | 4125 | if (TARGET_ARCH64) |
e54c7471 | 4126 | return gen_save_register_windowdi (increment); |
9ac617d4 | 4127 | else |
e54c7471 | 4128 | return gen_save_register_windowsi (increment); |
08c148a8 NB |
4129 | } |
4130 | ||
e54c7471 | 4131 | /* Generate an increment for the stack pointer. */ |
915f619f | 4132 | |
e54c7471 EB |
4133 | static rtx |
4134 | gen_stack_pointer_inc (rtx increment) | |
ab835497 | 4135 | { |
6deb0339 EB |
4136 | return gen_rtx_SET (VOIDmode, |
4137 | stack_pointer_rtx, | |
4138 | gen_rtx_PLUS (Pmode, | |
4139 | stack_pointer_rtx, | |
4140 | increment)); | |
e54c7471 EB |
4141 | } |
4142 | ||
4143 | /* Generate a decrement for the stack pointer. */ | |
4144 | ||
4145 | static rtx | |
4146 | gen_stack_pointer_dec (rtx decrement) | |
4147 | { | |
6deb0339 EB |
4148 | return gen_rtx_SET (VOIDmode, |
4149 | stack_pointer_rtx, | |
4150 | gen_rtx_MINUS (Pmode, | |
4151 | stack_pointer_rtx, | |
4152 | decrement)); | |
9ac617d4 EB |
4153 | } |
4154 | ||
4155 | /* Expand the function prologue. The prologue is responsible for reserving | |
4156 | storage for the frame, saving the call-saved registers and loading the | |
4157 | PIC register if needed. */ | |
4158 | ||
4159 | void | |
4160 | sparc_expand_prologue (void) | |
4161 | { | |
e54c7471 EB |
4162 | rtx insn; |
4163 | int i; | |
4164 | ||
5be9b7a1 EB |
4165 | /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying |
4166 | on the final value of the flag means deferring the prologue/epilogue | |
4167 | expansion until just before the second scheduling pass, which is too | |
4168 | late to emit multiple epilogues or return insns. | |
4169 | ||
4170 | Of course we are making the assumption that the value of the flag | |
4171 | will not change between now and its final value. Of the three parts | |
4172 | of the formula, only the last one can reasonably vary. Let's take a | |
4173 | closer look, after assuming that the first two ones are set to true | |
4174 | (otherwise the last value is effectively silenced). | |
4175 | ||
4176 | If only_leaf_regs_used returns false, the global predicate will also | |
4177 | be false so the actual frame size calculated below will be positive. | |
4178 | As a consequence, the save_register_window insn will be emitted in | |
4179 | the instruction stream; now this insn explicitly references %fp | |
4180 | which is not a leaf register so only_leaf_regs_used will always | |
4181 | return false subsequently. | |
4182 | ||
4183 | If only_leaf_regs_used returns true, we hope that the subsequent | |
4184 | optimization passes won't cause non-leaf registers to pop up. For | |
4185 | example, the regrename pass has special provisions to not rename to | |
4186 | non-leaf registers in a leaf function. */ | |
4187 | sparc_leaf_function_p | |
4188 | = optimize > 0 && leaf_function_p () && only_leaf_regs_used (); | |
1cb36a98 | 4189 | |
915f619f JW |
4190 | /* Need to use actual_fsize, since we are also allocating |
4191 | space for our callee (and our own register save area). */ | |
5be9b7a1 EB |
4192 | actual_fsize |
4193 | = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p); | |
4194 | ||
4195 | /* Advertise that the data calculated just above are now valid. */ | |
4196 | sparc_prologue_data_valid_p = true; | |
ab835497 | 4197 | |
5be9b7a1 | 4198 | if (sparc_leaf_function_p) |
61a55e8b | 4199 | { |
9ac617d4 | 4200 | frame_base_reg = stack_pointer_rtx; |
61a55e8b DE |
4201 | frame_base_offset = actual_fsize + SPARC_STACK_BIAS; |
4202 | } | |
4203 | else | |
4204 | { | |
9ac617d4 | 4205 | frame_base_reg = hard_frame_pointer_rtx; |
61a55e8b DE |
4206 | frame_base_offset = SPARC_STACK_BIAS; |
4207 | } | |
4208 | ||
915f619f JW |
4209 | if (actual_fsize == 0) |
4210 | /* do nothing. */ ; | |
5be9b7a1 | 4211 | else if (sparc_leaf_function_p) |
ab835497 | 4212 | { |
3592ea0d | 4213 | if (actual_fsize <= 4096) |
e54c7471 | 4214 | insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-actual_fsize))); |
3592ea0d | 4215 | else if (actual_fsize <= 8192) |
915f619f | 4216 | { |
e54c7471 EB |
4217 | insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096))); |
4218 | /* %sp is still the CFA register. */ | |
4219 | RTX_FRAME_RELATED_P (insn) = 1; | |
4220 | insn | |
4221 | = emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize))); | |
915f619f JW |
4222 | } |
4223 | else | |
4224 | { | |
9ac617d4 EB |
4225 | rtx reg = gen_rtx_REG (Pmode, 1); |
4226 | emit_move_insn (reg, GEN_INT (-actual_fsize)); | |
e54c7471 | 4227 | insn = emit_insn (gen_stack_pointer_inc (reg)); |
bbbbb16a ILT |
4228 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
4229 | gen_stack_pointer_inc (GEN_INT (-actual_fsize))); | |
915f619f | 4230 | } |
e54c7471 EB |
4231 | |
4232 | RTX_FRAME_RELATED_P (insn) = 1; | |
ab835497 | 4233 | } |
9ac617d4 | 4234 | else |
5f4241d5 | 4235 | { |
3592ea0d | 4236 | if (actual_fsize <= 4096) |
e54c7471 | 4237 | insn = emit_insn (gen_save_register_window (GEN_INT (-actual_fsize))); |
3592ea0d DE |
4238 | else if (actual_fsize <= 8192) |
4239 | { | |
e54c7471 EB |
4240 | insn = emit_insn (gen_save_register_window (GEN_INT (-4096))); |
4241 | /* %sp is not the CFA register anymore. */ | |
4242 | emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize))); | |
3592ea0d | 4243 | } |
915f619f | 4244 | else |
3592ea0d | 4245 | { |
9ac617d4 EB |
4246 | rtx reg = gen_rtx_REG (Pmode, 1); |
4247 | emit_move_insn (reg, GEN_INT (-actual_fsize)); | |
e54c7471 | 4248 | insn = emit_insn (gen_save_register_window (reg)); |
3592ea0d | 4249 | } |
e54c7471 EB |
4250 | |
4251 | RTX_FRAME_RELATED_P (insn) = 1; | |
4252 | for (i=0; i < XVECLEN (PATTERN (insn), 0); i++) | |
4253 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, i)) = 1; | |
ab835497 RK |
4254 | } |
4255 | ||
9ac617d4 | 4256 | if (num_gfregs) |
f8ece000 | 4257 | emit_save_or_restore_regs (SORR_SAVE); |
9ac617d4 EB |
4258 | |
4259 | /* Load the PIC register if needed. */ | |
e3b5732b | 4260 | if (flag_pic && crtl->uses_pic_offset_table) |
9fd52c6c | 4261 | load_pic_register (); |
9ac617d4 | 4262 | } |
4900aa61 | 4263 | |
9ac617d4 | 4264 | /* This function generates the assembly code for function entry, which boils |
f8ece000 | 4265 | down to emitting the necessary .register directives. */ |
9ac617d4 EB |
4266 | |
4267 | static void | |
4268 | sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
4269 | { | |
5be9b7a1 | 4270 | /* Check that the assumption we made in sparc_expand_prologue is valid. */ |
f5f7d171 | 4271 | gcc_assert (sparc_leaf_function_p == current_function_uses_only_leaf_regs); |
9ac617d4 EB |
4272 | |
4273 | sparc_output_scratch_registers (file); | |
9ac617d4 EB |
4274 | } |
4275 | ||
4276 | /* Expand the function epilogue, either normal or part of a sibcall. | |
4277 | We emit all the instructions except the return or the call. */ | |
c53aa195 | 4278 | |
9ac617d4 EB |
4279 | void |
4280 | sparc_expand_epilogue (void) | |
4281 | { | |
61a55e8b | 4282 | if (num_gfregs) |
f8ece000 | 4283 | emit_save_or_restore_regs (SORR_RESTORE); |
ab835497 | 4284 | |
9ac617d4 EB |
4285 | if (actual_fsize == 0) |
4286 | /* do nothing. */ ; | |
5be9b7a1 | 4287 | else if (sparc_leaf_function_p) |
9ac617d4 EB |
4288 | { |
4289 | if (actual_fsize <= 4096) | |
e54c7471 | 4290 | emit_insn (gen_stack_pointer_dec (GEN_INT (- actual_fsize))); |
9ac617d4 | 4291 | else if (actual_fsize <= 8192) |
61a55e8b | 4292 | { |
e54c7471 EB |
4293 | emit_insn (gen_stack_pointer_dec (GEN_INT (-4096))); |
4294 | emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - actual_fsize))); | |
61a55e8b | 4295 | } |
ab835497 | 4296 | else |
61a55e8b | 4297 | { |
9ac617d4 EB |
4298 | rtx reg = gen_rtx_REG (Pmode, 1); |
4299 | emit_move_insn (reg, GEN_INT (-actual_fsize)); | |
e54c7471 | 4300 | emit_insn (gen_stack_pointer_dec (reg)); |
61a55e8b | 4301 | } |
ab835497 RK |
4302 | } |
4303 | } | |
5be9b7a1 EB |
4304 | |
4305 | /* Return true if it is appropriate to emit `return' instructions in the | |
4306 | body of a function. */ | |
4307 | ||
4308 | bool | |
4309 | sparc_can_use_return_insn_p (void) | |
4310 | { | |
4311 | return sparc_prologue_data_valid_p | |
4312 | && (actual_fsize == 0 || !sparc_leaf_function_p); | |
4313 | } | |
4900aa61 | 4314 | |
9ac617d4 | 4315 | /* This function generates the assembly code for function exit. */ |
4900aa61 | 4316 | |
9ac617d4 EB |
4317 | static void |
4318 | sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
4319 | { | |
4320 | /* If code does not drop into the epilogue, we have to still output | |
4321 | a dummy nop for the sake of sane backtraces. Otherwise, if the | |
4322 | last two instructions of a function were "call foo; dslot;" this | |
19525b57 | 4323 | can make the return PC of foo (i.e. address of call instruction |
9ac617d4 | 4324 | plus 8) point to the first instruction in the next function. */ |
ab835497 | 4325 | |
9ac617d4 | 4326 | rtx insn, last_real_insn; |
7d167afd | 4327 | |
9ac617d4 EB |
4328 | insn = get_last_insn (); |
4329 | ||
4330 | last_real_insn = prev_real_insn (insn); | |
4331 | if (last_real_insn | |
4332 | && GET_CODE (last_real_insn) == INSN | |
4333 | && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE) | |
4334 | last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0); | |
4335 | ||
4336 | if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN) | |
4337 | fputs("\tnop\n", file); | |
4338 | ||
4339 | sparc_output_deferred_case_vectors (); | |
4340 | } | |
4900aa61 | 4341 | |
9ac617d4 | 4342 | /* Output a 'restore' instruction. */ |
4900aa61 | 4343 | |
7d167afd | 4344 | static void |
6244b14e | 4345 | output_restore (rtx pat) |
7d167afd | 4346 | { |
6244b14e | 4347 | rtx operands[3]; |
7d167afd | 4348 | |
6244b14e | 4349 | if (! pat) |
7d167afd | 4350 | { |
9ac617d4 EB |
4351 | fputs ("\t restore\n", asm_out_file); |
4352 | return; | |
7d167afd JJ |
4353 | } |
4354 | ||
f5f7d171 | 4355 | gcc_assert (GET_CODE (pat) == SET); |
08c148a8 | 4356 | |
9ac617d4 EB |
4357 | operands[0] = SET_DEST (pat); |
4358 | pat = SET_SRC (pat); | |
08c148a8 | 4359 | |
9ac617d4 EB |
4360 | switch (GET_CODE (pat)) |
4361 | { | |
4362 | case PLUS: | |
4363 | operands[1] = XEXP (pat, 0); | |
4364 | operands[2] = XEXP (pat, 1); | |
4365 | output_asm_insn (" restore %r1, %2, %Y0", operands); | |
4366 | break; | |
4367 | case LO_SUM: | |
4368 | operands[1] = XEXP (pat, 0); | |
4369 | operands[2] = XEXP (pat, 1); | |
4370 | output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); | |
4371 | break; | |
4372 | case ASHIFT: | |
4373 | operands[1] = XEXP (pat, 0); | |
f5f7d171 | 4374 | gcc_assert (XEXP (pat, 1) == const1_rtx); |
9ac617d4 EB |
4375 | output_asm_insn (" restore %r1, %r1, %Y0", operands); |
4376 | break; | |
4377 | default: | |
4378 | operands[1] = pat; | |
4379 | output_asm_insn (" restore %%g0, %1, %Y0", operands); | |
4380 | break; | |
4381 | } | |
08c148a8 | 4382 | } |
4900aa61 | 4383 | |
9ac617d4 | 4384 | /* Output a return. */ |
08c148a8 | 4385 | |
9ac617d4 EB |
4386 | const char * |
4387 | output_return (rtx insn) | |
ab835497 | 4388 | { |
5be9b7a1 | 4389 | if (sparc_leaf_function_p) |
e48addee | 4390 | { |
9ac617d4 EB |
4391 | /* This is a leaf function so we don't have to bother restoring the |
4392 | register window, which frees us from dealing with the convoluted | |
4393 | semantics of restore/return. We simply output the jump to the | |
4e5b002b | 4394 | return address and the insn in the delay slot (if any). */ |
7a31a340 | 4395 | |
e3b5732b | 4396 | gcc_assert (! crtl->calls_eh_return); |
ac59ed37 | 4397 | |
4e5b002b | 4398 | return "jmp\t%%o7+%)%#"; |
bfd6bc60 | 4399 | } |
ab835497 | 4400 | else |
ab835497 | 4401 | { |
9ac617d4 EB |
4402 | /* This is a regular function so we have to restore the register window. |
4403 | We may have a pending insn for the delay slot, which will be either | |
4404 | combined with the 'restore' instruction or put in the delay slot of | |
4405 | the 'return' instruction. */ | |
4406 | ||
e3b5732b | 4407 | if (crtl->calls_eh_return) |
33074e5f | 4408 | { |
9ac617d4 EB |
4409 | /* If the function uses __builtin_eh_return, the eh_return |
4410 | machinery occupies the delay slot. */ | |
f5f7d171 | 4411 | gcc_assert (! final_sequence); |
ab835497 | 4412 | |
951661a1 EB |
4413 | if (! flag_delayed_branch) |
4414 | fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file); | |
4415 | ||
9ac617d4 EB |
4416 | if (TARGET_V9) |
4417 | fputs ("\treturn\t%i7+8\n", asm_out_file); | |
4418 | else | |
4419 | fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file); | |
4420 | ||
951661a1 EB |
4421 | if (flag_delayed_branch) |
4422 | fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file); | |
4423 | else | |
4424 | fputs ("\t nop\n", asm_out_file); | |
33074e5f | 4425 | } |
4e5b002b | 4426 | else if (final_sequence) |
ef8200df | 4427 | { |
9ac617d4 EB |
4428 | rtx delay, pat; |
4429 | ||
4430 | delay = NEXT_INSN (insn); | |
f5f7d171 | 4431 | gcc_assert (delay); |
1150a841 | 4432 | |
9ac617d4 EB |
4433 | pat = PATTERN (delay); |
4434 | ||
4435 | if (TARGET_V9 && ! epilogue_renumber (&pat, 1)) | |
33074e5f | 4436 | { |
9ac617d4 | 4437 | epilogue_renumber (&pat, 0); |
4e5b002b | 4438 | return "return\t%%i7+%)%#"; |
1150a841 | 4439 | } |
33074e5f | 4440 | else |
ab835497 | 4441 | { |
4e5b002b | 4442 | output_asm_insn ("jmp\t%%i7+%)", NULL); |
6244b14e | 4443 | output_restore (pat); |
4e5b002b EB |
4444 | PATTERN (delay) = gen_blockage (); |
4445 | INSN_CODE (delay) = -1; | |
ab835497 | 4446 | } |
ef8200df | 4447 | } |
33074e5f | 4448 | else |
9ac617d4 EB |
4449 | { |
4450 | /* The delay slot is empty. */ | |
4451 | if (TARGET_V9) | |
4e5b002b | 4452 | return "return\t%%i7+%)\n\t nop"; |
951661a1 | 4453 | else if (flag_delayed_branch) |
4e5b002b | 4454 | return "jmp\t%%i7+%)\n\t restore"; |
951661a1 | 4455 | else |
4e5b002b | 4456 | return "restore\n\tjmp\t%%o7+%)\n\t nop"; |
9ac617d4 | 4457 | } |
6a151f87 | 4458 | } |
e0d80184 | 4459 | |
9ac617d4 | 4460 | return ""; |
ab835497 | 4461 | } |
7d167afd JJ |
4462 | |
4463 | /* Output a sibling call. */ | |
4464 | ||
4465 | const char * | |
fc27d102 | 4466 | output_sibcall (rtx insn, rtx call_operand) |
7d167afd | 4467 | { |
9ac617d4 | 4468 | rtx operands[1]; |
7d167afd | 4469 | |
f5f7d171 | 4470 | gcc_assert (flag_delayed_branch); |
951661a1 | 4471 | |
7d167afd JJ |
4472 | operands[0] = call_operand; |
4473 | ||
5be9b7a1 | 4474 | if (sparc_leaf_function_p) |
7d167afd | 4475 | { |
9ac617d4 EB |
4476 | /* This is a leaf function so we don't have to bother restoring the |
4477 | register window. We simply output the jump to the function and | |
4478 | the insn in the delay slot (if any). */ | |
7d167afd | 4479 | |
f5f7d171 | 4480 | gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence)); |
9ac617d4 | 4481 | |
4e5b002b EB |
4482 | if (final_sequence) |
4483 | output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#", | |
4484 | operands); | |
7d167afd | 4485 | else |
4e5b002b EB |
4486 | /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize |
4487 | it into branch if possible. */ | |
4488 | output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7", | |
4489 | operands); | |
7d167afd | 4490 | } |
9ac617d4 | 4491 | else |
7d167afd | 4492 | { |
9ac617d4 EB |
4493 | /* This is a regular function so we have to restore the register window. |
4494 | We may have a pending insn for the delay slot, which will be combined | |
4495 | with the 'restore' instruction. */ | |
7d167afd | 4496 | |
9ac617d4 | 4497 | output_asm_insn ("call\t%a0, 0", operands); |
7d167afd | 4498 | |
4e5b002b | 4499 | if (final_sequence) |
7d167afd | 4500 | { |
9ac617d4 | 4501 | rtx delay = NEXT_INSN (insn); |
f5f7d171 | 4502 | gcc_assert (delay); |
9ac617d4 | 4503 | |
6244b14e | 4504 | output_restore (PATTERN (delay)); |
9ac617d4 EB |
4505 | |
4506 | PATTERN (delay) = gen_blockage (); | |
4507 | INSN_CODE (delay) = -1; | |
7d167afd | 4508 | } |
9ac617d4 | 4509 | else |
6244b14e | 4510 | output_restore (NULL_RTX); |
7d167afd | 4511 | } |
9ac617d4 | 4512 | |
7d167afd JJ |
4513 | return ""; |
4514 | } | |
4fb4e4b8 DE |
4515 | \f |
4516 | /* Functions for handling argument passing. | |
4517 | ||
1b5963f7 | 4518 | For 32-bit, the first 6 args are normally in registers and the rest are |
4fb4e4b8 DE |
4519 | pushed. Any arg that starts within the first 6 words is at least |
4520 | partially passed in a register unless its data type forbids. | |
4521 | ||
1b5963f7 | 4522 | For 64-bit, the argument registers are laid out as an array of 16 elements |
4fb4e4b8 DE |
4523 | and arguments are added sequentially. The first 6 int args and up to the |
4524 | first 16 fp args (depending on size) are passed in regs. | |
4525 | ||
4526 | Slot Stack Integral Float Float in structure Double Long Double | |
4527 | ---- ----- -------- ----- ------------------ ------ ----------- | |
4528 | 15 [SP+248] %f31 %f30,%f31 %d30 | |
4529 | 14 [SP+240] %f29 %f28,%f29 %d28 %q28 | |
4530 | 13 [SP+232] %f27 %f26,%f27 %d26 | |
4531 | 12 [SP+224] %f25 %f24,%f25 %d24 %q24 | |
4532 | 11 [SP+216] %f23 %f22,%f23 %d22 | |
4533 | 10 [SP+208] %f21 %f20,%f21 %d20 %q20 | |
4534 | 9 [SP+200] %f19 %f18,%f19 %d18 | |
4535 | 8 [SP+192] %f17 %f16,%f17 %d16 %q16 | |
4536 | 7 [SP+184] %f15 %f14,%f15 %d14 | |
4537 | 6 [SP+176] %f13 %f12,%f13 %d12 %q12 | |
4538 | 5 [SP+168] %o5 %f11 %f10,%f11 %d10 | |
4539 | 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 | |
4540 | 3 [SP+152] %o3 %f7 %f6,%f7 %d6 | |
4541 | 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 | |
4542 | 1 [SP+136] %o1 %f3 %f2,%f3 %d2 | |
4543 | 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 | |
4544 | ||
4545 | Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. | |
4546 | ||
1b5963f7 | 4547 | Integral arguments are always passed as 64-bit quantities appropriately |
4fb4e4b8 DE |
4548 | extended. |
4549 | ||
4550 | Passing of floating point values is handled as follows. | |
4551 | If a prototype is in scope: | |
4552 | If the value is in a named argument (i.e. not a stdarg function or a | |
4553 | value not part of the `...') then the value is passed in the appropriate | |
4554 | fp reg. | |
4555 | If the value is part of the `...' and is passed in one of the first 6 | |
4556 | slots then the value is passed in the appropriate int reg. | |
4557 | If the value is part of the `...' and is not passed in one of the first 6 | |
4558 | slots then the value is passed in memory. | |
4559 | If a prototype is not in scope: | |
4560 | If the value is one of the first 6 arguments the value is passed in the | |
4561 | appropriate integer reg and the appropriate fp reg. | |
4562 | If the value is not one of the first 6 arguments the value is passed in | |
4563 | the appropriate fp reg and in memory. | |
1b5963f7 EB |
4564 | |
4565 | ||
4900aa61 | 4566 | Summary of the calling conventions implemented by GCC on the SPARC: |
1b5963f7 EB |
4567 | |
4568 | 32-bit ABI: | |
4569 | size argument return value | |
4570 | ||
4571 | small integer <4 int. reg. int. reg. | |
4572 | word 4 int. reg. int. reg. | |
4573 | double word 8 int. reg. int. reg. | |
4574 | ||
4575 | _Complex small integer <8 int. reg. int. reg. | |
4576 | _Complex word 8 int. reg. int. reg. | |
4577 | _Complex double word 16 memory int. reg. | |
4578 | ||
4579 | vector integer <=8 int. reg. FP reg. | |
4580 | vector integer >8 memory memory | |
4581 | ||
4582 | float 4 int. reg. FP reg. | |
4583 | double 8 int. reg. FP reg. | |
4584 | long double 16 memory memory | |
4585 | ||
4586 | _Complex float 8 memory FP reg. | |
4587 | _Complex double 16 memory FP reg. | |
4588 | _Complex long double 32 memory FP reg. | |
4589 | ||
45261626 | 4590 | vector float any memory memory |
1b5963f7 EB |
4591 | |
4592 | aggregate any memory memory | |
4593 | ||
4594 | ||
4595 | ||
4596 | 64-bit ABI: | |
4597 | size argument return value | |
4598 | ||
4599 | small integer <8 int. reg. int. reg. | |
4600 | word 8 int. reg. int. reg. | |
4601 | double word 16 int. reg. int. reg. | |
4602 | ||
4603 | _Complex small integer <16 int. reg. int. reg. | |
4604 | _Complex word 16 int. reg. int. reg. | |
4605 | _Complex double word 32 memory int. reg. | |
4606 | ||
4607 | vector integer <=16 FP reg. FP reg. | |
4608 | vector integer 16<s<=32 memory FP reg. | |
4609 | vector integer >32 memory memory | |
4610 | ||
4611 | float 4 FP reg. FP reg. | |
4612 | double 8 FP reg. FP reg. | |
4613 | long double 16 FP reg. FP reg. | |
4614 | ||
4615 | _Complex float 8 FP reg. FP reg. | |
4616 | _Complex double 16 FP reg. FP reg. | |
4617 | _Complex long double 32 memory FP reg. | |
4618 | ||
4619 | vector float <=16 FP reg. FP reg. | |
4620 | vector float 16<s<=32 memory FP reg. | |
4621 | vector float >32 memory memory | |
4622 | ||
4623 | aggregate <=16 reg. reg. | |
4624 | aggregate 16<s<=32 memory reg. | |
4625 | aggregate >32 memory memory | |
4626 | ||
4627 | ||
4628 | ||
4629 | Note #1: complex floating-point types follow the extended SPARC ABIs as | |
4630 | implemented by the Sun compiler. | |
4631 | ||
4632 | Note #2: integral vector types follow the scalar floating-point types | |
4633 | conventions to match what is implemented by the Sun VIS SDK. | |
4634 | ||
4900aa61 | 4635 | Note #3: floating-point vector types follow the aggregate types |
45261626 | 4636 | conventions. */ |
1b5963f7 | 4637 | |
4fb4e4b8 DE |
4638 | |
4639 | /* Maximum number of int regs for args. */ | |
4640 | #define SPARC_INT_ARG_MAX 6 | |
4641 | /* Maximum number of fp regs for args. */ | |
4642 | #define SPARC_FP_ARG_MAX 16 | |
4643 | ||
4644 | #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
4645 | ||
4646 | /* Handle the INIT_CUMULATIVE_ARGS macro. | |
4647 | Initialize a variable CUM of type CUMULATIVE_ARGS | |
4648 | for a call to a function whose data type is FNTYPE. | |
4649 | For a library call, FNTYPE is 0. */ | |
3ea1fdd3 | 4650 | |
4fb4e4b8 | 4651 | void |
fc27d102 KG |
4652 | init_cumulative_args (struct sparc_args *cum, tree fntype, |
4653 | rtx libname ATTRIBUTE_UNUSED, | |
4654 | tree fndecl ATTRIBUTE_UNUSED) | |
4fb4e4b8 DE |
4655 | { |
4656 | cum->words = 0; | |
4657 | cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); | |
4658 | cum->libcall_p = fntype == 0; | |
4659 | } | |
61a55e8b | 4660 | |
bd5bd7ac | 4661 | /* Handle the TARGET_PROMOTE_PROTOTYPES target hook. |
3e2cc1d1 KH |
4662 | When a prototype says `char' or `short', really pass an `int'. */ |
4663 | ||
4664 | static bool | |
586de218 | 4665 | sparc_promote_prototypes (const_tree fntype ATTRIBUTE_UNUSED) |
3e2cc1d1 KH |
4666 | { |
4667 | return TARGET_ARCH32 ? true : false; | |
4668 | } | |
4669 | ||
cde0f3fd PB |
4670 | /* Handle promotion of pointer and integer arguments. */ |
4671 | ||
4672 | static enum machine_mode | |
4673 | sparc_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, | |
4674 | enum machine_mode mode, | |
4675 | int *punsignedp ATTRIBUTE_UNUSED, | |
4676 | const_tree fntype ATTRIBUTE_UNUSED, | |
4677 | int for_return ATTRIBUTE_UNUSED) | |
4678 | { | |
4679 | if (POINTER_TYPE_P (type)) | |
4680 | { | |
4681 | *punsignedp = POINTERS_EXTEND_UNSIGNED; | |
4682 | return Pmode; | |
4683 | } | |
4684 | ||
4685 | /* For TARGET_ARCH64 we need this, as we don't have instructions | |
4686 | for arithmetic operations which do zero/sign extension at the same time, | |
4687 | so without this we end up with a srl/sra after every assignment to an | |
4688 | user variable, which means very very bad code. */ | |
cde0f3fd PB |
4689 | if (TARGET_ARCH64 |
4690 | && GET_MODE_CLASS (mode) == MODE_INT | |
4691 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
4692 | return word_mode; | |
4693 | ||
4694 | return mode; | |
4695 | } | |
4696 | ||
bd5bd7ac | 4697 | /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */ |
3e2cc1d1 KH |
4698 | |
4699 | static bool | |
4700 | sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED) | |
4701 | { | |
1b5963f7 | 4702 | return TARGET_ARCH64 ? true : false; |
3e2cc1d1 KH |
4703 | } |
4704 | ||
5c4f4b18 EB |
4705 | /* Scan the record type TYPE and return the following predicates: |
4706 | - INTREGS_P: the record contains at least one field or sub-field | |
4707 | that is eligible for promotion in integer registers. | |
4708 | - FP_REGS_P: the record contains at least one field or sub-field | |
4709 | that is eligible for promotion in floating-point registers. | |
4710 | - PACKED_P: the record contains at least one field that is packed. | |
4711 | ||
4712 | Sub-fields are not taken into account for the PACKED_P predicate. */ | |
4713 | ||
4714 | static void | |
a7bba6ca | 4715 | scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p) |
5c4f4b18 EB |
4716 | { |
4717 | tree field; | |
4718 | ||
4719 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4720 | { | |
4721 | if (TREE_CODE (field) == FIELD_DECL) | |
4722 | { | |
4723 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
4724 | scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0); | |
45261626 EB |
4725 | else if ((FLOAT_TYPE_P (TREE_TYPE (field)) |
4726 | || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE) | |
4727 | && TARGET_FPU) | |
5c4f4b18 EB |
4728 | *fpregs_p = 1; |
4729 | else | |
4730 | *intregs_p = 1; | |
4731 | ||
4732 | if (packed_p && DECL_PACKED (field)) | |
4733 | *packed_p = 1; | |
4734 | } | |
4735 | } | |
4736 | } | |
4737 | ||
4fb4e4b8 | 4738 | /* Compute the slot number to pass an argument in. |
5c4f4b18 | 4739 | Return the slot number or -1 if passing on the stack. |
4fb4e4b8 DE |
4740 | |
4741 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4742 | the preceding args and about the function being called. | |
4743 | MODE is the argument's machine mode. | |
4744 | TYPE is the data type of the argument (as a tree). | |
4745 | This is null for libcalls where that information may | |
4746 | not be available. | |
4747 | NAMED is nonzero if this argument is a named parameter | |
4748 | (otherwise it is an extra parameter matching an ellipsis). | |
4749 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. | |
4750 | *PREGNO records the register number to use if scalar type. | |
4751 | *PPADDING records the amount of padding needed in words. */ | |
4752 | ||
4753 | static int | |
fc27d102 KG |
4754 | function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode, |
4755 | tree type, int named, int incoming_p, | |
4756 | int *pregno, int *ppadding) | |
4fb4e4b8 DE |
4757 | { |
4758 | int regbase = (incoming_p | |
4759 | ? SPARC_INCOMING_INT_ARG_FIRST | |
4760 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
4761 | int slotno = cum->words; | |
45261626 | 4762 | enum mode_class mclass; |
4fb4e4b8 DE |
4763 | int regno; |
4764 | ||
4765 | *ppadding = 0; | |
4766 | ||
1b5963f7 | 4767 | if (type && TREE_ADDRESSABLE (type)) |
4fb4e4b8 | 4768 | return -1; |
1b5963f7 | 4769 | |
4fb4e4b8 | 4770 | if (TARGET_ARCH32 |
1b5963f7 EB |
4771 | && mode == BLKmode |
4772 | && type | |
4fb4e4b8 DE |
4773 | && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) |
4774 | return -1; | |
4775 | ||
1b5963f7 EB |
4776 | /* For SPARC64, objects requiring 16-byte alignment get it. */ |
4777 | if (TARGET_ARCH64 | |
7617ec02 | 4778 | && (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128 |
1b5963f7 EB |
4779 | && (slotno & 1) != 0) |
4780 | slotno++, *ppadding = 1; | |
4fb4e4b8 | 4781 | |
45261626 EB |
4782 | mclass = GET_MODE_CLASS (mode); |
4783 | if (type && TREE_CODE (type) == VECTOR_TYPE) | |
4784 | { | |
4785 | /* Vector types deserve special treatment because they are | |
4786 | polymorphic wrt their mode, depending upon whether VIS | |
4787 | instructions are enabled. */ | |
4788 | if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE) | |
4789 | { | |
4790 | /* The SPARC port defines no floating-point vector modes. */ | |
f5f7d171 | 4791 | gcc_assert (mode == BLKmode); |
45261626 EB |
4792 | } |
4793 | else | |
4794 | { | |
4795 | /* Integral vector types should either have a vector | |
4796 | mode or an integral mode, because we are guaranteed | |
4797 | by pass_by_reference that their size is not greater | |
4798 | than 16 bytes and TImode is 16-byte wide. */ | |
f5f7d171 | 4799 | gcc_assert (mode != BLKmode); |
45261626 EB |
4800 | |
4801 | /* Vector integers are handled like floats according to | |
4802 | the Sun VIS SDK. */ | |
4803 | mclass = MODE_FLOAT; | |
4804 | } | |
4805 | } | |
4806 | ||
4807 | switch (mclass) | |
1b5963f7 EB |
4808 | { |
4809 | case MODE_FLOAT: | |
4810 | case MODE_COMPLEX_FLOAT: | |
0dd8c9bc | 4811 | case MODE_VECTOR_INT: |
1b5963f7 EB |
4812 | if (TARGET_ARCH64 && TARGET_FPU && named) |
4813 | { | |
4814 | if (slotno >= SPARC_FP_ARG_MAX) | |
4815 | return -1; | |
4816 | regno = SPARC_FP_ARG_FIRST + slotno * 2; | |
4817 | /* Arguments filling only one single FP register are | |
4818 | right-justified in the outer double FP register. */ | |
4819 | if (GET_MODE_SIZE (mode) <= 4) | |
4820 | regno++; | |
4821 | break; | |
4822 | } | |
d560b0aa EB |
4823 | /* fallthrough */ |
4824 | ||
1b5963f7 EB |
4825 | case MODE_INT: |
4826 | case MODE_COMPLEX_INT: | |
4fb4e4b8 DE |
4827 | if (slotno >= SPARC_INT_ARG_MAX) |
4828 | return -1; | |
4829 | regno = regbase + slotno; | |
4830 | break; | |
4831 | ||
1b5963f7 EB |
4832 | case MODE_RANDOM: |
4833 | if (mode == VOIDmode) | |
4834 | /* MODE is VOIDmode when generating the actual call. */ | |
4835 | return -1; | |
d560b0aa | 4836 | |
f5f7d171 | 4837 | gcc_assert (mode == BLKmode); |
4fb4e4b8 | 4838 | |
ef6843ed EB |
4839 | if (TARGET_ARCH32 |
4840 | || !type | |
4841 | || (TREE_CODE (type) != VECTOR_TYPE | |
4842 | && TREE_CODE (type) != RECORD_TYPE)) | |
4fb4e4b8 DE |
4843 | { |
4844 | if (slotno >= SPARC_INT_ARG_MAX) | |
4845 | return -1; | |
4846 | regno = regbase + slotno; | |
4847 | } | |
45261626 | 4848 | else /* TARGET_ARCH64 && type */ |
4fb4e4b8 | 4849 | { |
5c4f4b18 EB |
4850 | int intregs_p = 0, fpregs_p = 0, packed_p = 0; |
4851 | ||
4852 | /* First see what kinds of registers we would need. */ | |
45261626 EB |
4853 | if (TREE_CODE (type) == VECTOR_TYPE) |
4854 | fpregs_p = 1; | |
4855 | else | |
4856 | scan_record_type (type, &intregs_p, &fpregs_p, &packed_p); | |
5c4f4b18 EB |
4857 | |
4858 | /* The ABI obviously doesn't specify how packed structures | |
4859 | are passed. These are defined to be passed in int regs | |
4860 | if possible, otherwise memory. */ | |
4fb4e4b8 DE |
4861 | if (packed_p || !named) |
4862 | fpregs_p = 0, intregs_p = 1; | |
4863 | ||
4864 | /* If all arg slots are filled, then must pass on stack. */ | |
4865 | if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) | |
4866 | return -1; | |
1b5963f7 | 4867 | |
4fb4e4b8 DE |
4868 | /* If there are only int args and all int arg slots are filled, |
4869 | then must pass on stack. */ | |
4870 | if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) | |
4871 | return -1; | |
1b5963f7 | 4872 | |
4fb4e4b8 DE |
4873 | /* Note that even if all int arg slots are filled, fp members may |
4874 | still be passed in regs if such regs are available. | |
4875 | *PREGNO isn't set because there may be more than one, it's up | |
4876 | to the caller to compute them. */ | |
4877 | return slotno; | |
4878 | } | |
4879 | break; | |
4880 | ||
4881 | default : | |
f5f7d171 | 4882 | gcc_unreachable (); |
4fb4e4b8 DE |
4883 | } |
4884 | ||
4885 | *pregno = regno; | |
4886 | return slotno; | |
4887 | } | |
4888 | ||
82d6b402 RH |
4889 | /* Handle recursive register counting for structure field layout. */ |
4890 | ||
4891 | struct function_arg_record_value_parms | |
4892 | { | |
48028e21 EB |
4893 | rtx ret; /* return expression being built. */ |
4894 | int slotno; /* slot number of the argument. */ | |
4895 | int named; /* whether the argument is named. */ | |
4896 | int regbase; /* regno of the base register. */ | |
4897 | int stack; /* 1 if part of the argument is on the stack. */ | |
1fd05073 | 4898 | int intoffset; /* offset of the first pending integer field. */ |
48028e21 | 4899 | unsigned int nregs; /* number of words passed in registers. */ |
82d6b402 RH |
4900 | }; |
4901 | ||
2a01c939 | 4902 | static void function_arg_record_value_3 |
e80d5f80 | 4903 | (HOST_WIDE_INT, struct function_arg_record_value_parms *); |
2a01c939 | 4904 | static void function_arg_record_value_2 |
586de218 | 4905 | (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool); |
b1474bb7 | 4906 | static void function_arg_record_value_1 |
586de218 KG |
4907 | (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool); |
4908 | static rtx function_arg_record_value (const_tree, enum machine_mode, int, int, int); | |
22d8d627 | 4909 | static rtx function_arg_union_value (int, enum machine_mode, int, int); |
2a01c939 | 4910 | |
0020b823 | 4911 | /* A subroutine of function_arg_record_value. Traverse the structure |
fae778eb | 4912 | recursively and determine how many registers will be required. */ |
0020b823 | 4913 | |
82d6b402 | 4914 | static void |
586de218 | 4915 | function_arg_record_value_1 (const_tree type, HOST_WIDE_INT startbitpos, |
cde85594 EB |
4916 | struct function_arg_record_value_parms *parms, |
4917 | bool packed_p) | |
82d6b402 RH |
4918 | { |
4919 | tree field; | |
4920 | ||
82d6b402 RH |
4921 | /* We need to compute how many registers are needed so we can |
4922 | allocate the PARALLEL but before we can do that we need to know | |
cde85594 EB |
4923 | whether there are any packed fields. The ABI obviously doesn't |
4924 | specify how structures are passed in this case, so they are | |
4925 | defined to be passed in int regs if possible, otherwise memory, | |
4926 | regardless of whether there are fp values present. */ | |
4927 | ||
4928 | if (! packed_p) | |
4929 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4930 | { | |
4931 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
4932 | { | |
4933 | packed_p = true; | |
4934 | break; | |
4935 | } | |
4936 | } | |
82d6b402 RH |
4937 | |
4938 | /* Compute how many registers we need. */ | |
4939 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4940 | { | |
4941 | if (TREE_CODE (field) == FIELD_DECL) | |
4942 | { | |
75131237 RK |
4943 | HOST_WIDE_INT bitpos = startbitpos; |
4944 | ||
bb05e341 EB |
4945 | if (DECL_SIZE (field) != 0) |
4946 | { | |
4947 | if (integer_zerop (DECL_SIZE (field))) | |
4948 | continue; | |
4949 | ||
4950 | if (host_integerp (bit_position (field), 1)) | |
4951 | bitpos += int_bit_position (field); | |
4952 | } | |
75131237 | 4953 | |
82d6b402 RH |
4954 | /* ??? FIXME: else assume zero offset. */ |
4955 | ||
4956 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
cde85594 EB |
4957 | function_arg_record_value_1 (TREE_TYPE (field), |
4958 | bitpos, | |
4959 | parms, | |
4960 | packed_p); | |
1b5963f7 EB |
4961 | else if ((FLOAT_TYPE_P (TREE_TYPE (field)) |
4962 | || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE) | |
8a98812c EB |
4963 | && TARGET_FPU |
4964 | && parms->named | |
4965 | && ! packed_p) | |
82d6b402 RH |
4966 | { |
4967 | if (parms->intoffset != -1) | |
4968 | { | |
b2f24c85 | 4969 | unsigned int startbit, endbit; |
82d6b402 RH |
4970 | int intslots, this_slotno; |
4971 | ||
b2f24c85 EB |
4972 | startbit = parms->intoffset & -BITS_PER_WORD; |
4973 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4974 | ||
4975 | intslots = (endbit - startbit) / BITS_PER_WORD; | |
82d6b402 RH |
4976 | this_slotno = parms->slotno + parms->intoffset |
4977 | / BITS_PER_WORD; | |
4978 | ||
48028e21 EB |
4979 | if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) |
4980 | { | |
4981 | intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); | |
4982 | /* We need to pass this field on the stack. */ | |
4983 | parms->stack = 1; | |
4984 | } | |
4985 | ||
82d6b402 RH |
4986 | parms->nregs += intslots; |
4987 | parms->intoffset = -1; | |
4988 | } | |
4989 | ||
4990 | /* There's no need to check this_slotno < SPARC_FP_ARG MAX. | |
4991 | If it wasn't true we wouldn't be here. */ | |
45261626 EB |
4992 | if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE |
4993 | && DECL_MODE (field) == BLKmode) | |
4994 | parms->nregs += TYPE_VECTOR_SUBPARTS (TREE_TYPE (field)); | |
4995 | else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) | |
4996 | parms->nregs += 2; | |
4997 | else | |
105b2084 | 4998 | parms->nregs += 1; |
82d6b402 RH |
4999 | } |
5000 | else | |
5001 | { | |
5002 | if (parms->intoffset == -1) | |
5003 | parms->intoffset = bitpos; | |
5004 | } | |
5005 | } | |
5006 | } | |
5007 | } | |
5008 | ||
0020b823 RH |
5009 | /* A subroutine of function_arg_record_value. Assign the bits of the |
5010 | structure between parms->intoffset and bitpos to integer registers. */ | |
82d6b402 | 5011 | |
4900aa61 | 5012 | static void |
fc27d102 KG |
5013 | function_arg_record_value_3 (HOST_WIDE_INT bitpos, |
5014 | struct function_arg_record_value_parms *parms) | |
82d6b402 RH |
5015 | { |
5016 | enum machine_mode mode; | |
75131237 | 5017 | unsigned int regno; |
0020b823 | 5018 | unsigned int startbit, endbit; |
75131237 | 5019 | int this_slotno, intslots, intoffset; |
82d6b402 RH |
5020 | rtx reg; |
5021 | ||
5022 | if (parms->intoffset == -1) | |
5023 | return; | |
75131237 | 5024 | |
82d6b402 RH |
5025 | intoffset = parms->intoffset; |
5026 | parms->intoffset = -1; | |
5027 | ||
0020b823 RH |
5028 | startbit = intoffset & -BITS_PER_WORD; |
5029 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
5030 | intslots = (endbit - startbit) / BITS_PER_WORD; | |
82d6b402 RH |
5031 | this_slotno = parms->slotno + intoffset / BITS_PER_WORD; |
5032 | ||
5033 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
5034 | if (intslots <= 0) | |
5035 | return; | |
5036 | ||
5037 | /* If this is the trailing part of a word, only load that much into | |
5038 | the register. Otherwise load the whole register. Note that in | |
5039 | the latter case we may pick up unwanted bits. It's not a problem | |
5040 | at the moment but may wish to revisit. */ | |
5041 | ||
5042 | if (intoffset % BITS_PER_WORD != 0) | |
bb05e341 EB |
5043 | mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, |
5044 | MODE_INT); | |
82d6b402 RH |
5045 | else |
5046 | mode = word_mode; | |
5047 | ||
5048 | intoffset /= BITS_PER_UNIT; | |
5049 | do | |
5050 | { | |
5051 | regno = parms->regbase + this_slotno; | |
254110c2 | 5052 | reg = gen_rtx_REG (mode, regno); |
48028e21 | 5053 | XVECEXP (parms->ret, 0, parms->stack + parms->nregs) |
254110c2 | 5054 | = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); |
82d6b402 RH |
5055 | |
5056 | this_slotno += 1; | |
5057 | intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; | |
1fd05073 | 5058 | mode = word_mode; |
82d6b402 RH |
5059 | parms->nregs += 1; |
5060 | intslots -= 1; | |
5061 | } | |
5062 | while (intslots > 0); | |
5063 | } | |
5064 | ||
0020b823 RH |
5065 | /* A subroutine of function_arg_record_value. Traverse the structure |
5066 | recursively and assign bits to floating point registers. Track which | |
5067 | bits in between need integer registers; invoke function_arg_record_value_3 | |
5068 | to make that happen. */ | |
5069 | ||
82d6b402 | 5070 | static void |
586de218 | 5071 | function_arg_record_value_2 (const_tree type, HOST_WIDE_INT startbitpos, |
cde85594 EB |
5072 | struct function_arg_record_value_parms *parms, |
5073 | bool packed_p) | |
82d6b402 RH |
5074 | { |
5075 | tree field; | |
82d6b402 | 5076 | |
cde85594 EB |
5077 | if (! packed_p) |
5078 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
5079 | { | |
5080 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
5081 | { | |
5082 | packed_p = true; | |
5083 | break; | |
5084 | } | |
5085 | } | |
82d6b402 RH |
5086 | |
5087 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
5088 | { | |
5089 | if (TREE_CODE (field) == FIELD_DECL) | |
5090 | { | |
75131237 RK |
5091 | HOST_WIDE_INT bitpos = startbitpos; |
5092 | ||
bb05e341 EB |
5093 | if (DECL_SIZE (field) != 0) |
5094 | { | |
5095 | if (integer_zerop (DECL_SIZE (field))) | |
5096 | continue; | |
5097 | ||
5098 | if (host_integerp (bit_position (field), 1)) | |
5099 | bitpos += int_bit_position (field); | |
5100 | } | |
75131237 | 5101 | |
82d6b402 RH |
5102 | /* ??? FIXME: else assume zero offset. */ |
5103 | ||
5104 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
cde85594 EB |
5105 | function_arg_record_value_2 (TREE_TYPE (field), |
5106 | bitpos, | |
5107 | parms, | |
5108 | packed_p); | |
1b5963f7 EB |
5109 | else if ((FLOAT_TYPE_P (TREE_TYPE (field)) |
5110 | || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE) | |
8a98812c EB |
5111 | && TARGET_FPU |
5112 | && parms->named | |
5113 | && ! packed_p) | |
82d6b402 RH |
5114 | { |
5115 | int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; | |
45261626 | 5116 | int regno, nregs, pos; |
105b2084 | 5117 | enum machine_mode mode = DECL_MODE (field); |
82d6b402 RH |
5118 | rtx reg; |
5119 | ||
5120 | function_arg_record_value_3 (bitpos, parms); | |
45261626 EB |
5121 | |
5122 | if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE | |
5123 | && mode == BLKmode) | |
5124 | { | |
5125 | mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field))); | |
5126 | nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field)); | |
105b2084 | 5127 | } |
45261626 EB |
5128 | else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) |
5129 | { | |
5130 | mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field))); | |
5131 | nregs = 2; | |
5132 | } | |
5133 | else | |
5134 | nregs = 1; | |
5135 | ||
1b5963f7 EB |
5136 | regno = SPARC_FP_ARG_FIRST + this_slotno * 2; |
5137 | if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0) | |
5138 | regno++; | |
105b2084 | 5139 | reg = gen_rtx_REG (mode, regno); |
45261626 | 5140 | pos = bitpos / BITS_PER_UNIT; |
48028e21 | 5141 | XVECEXP (parms->ret, 0, parms->stack + parms->nregs) |
45261626 | 5142 | = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos)); |
82d6b402 | 5143 | parms->nregs += 1; |
45261626 | 5144 | while (--nregs > 0) |
105b2084 JJ |
5145 | { |
5146 | regno += GET_MODE_SIZE (mode) / 4; | |
5147 | reg = gen_rtx_REG (mode, regno); | |
45261626 | 5148 | pos += GET_MODE_SIZE (mode); |
48028e21 | 5149 | XVECEXP (parms->ret, 0, parms->stack + parms->nregs) |
45261626 | 5150 | = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos)); |
105b2084 JJ |
5151 | parms->nregs += 1; |
5152 | } | |
82d6b402 RH |
5153 | } |
5154 | else | |
5155 | { | |
5156 | if (parms->intoffset == -1) | |
5157 | parms->intoffset = bitpos; | |
5158 | } | |
5159 | } | |
5160 | } | |
5161 | } | |
5162 | ||
bf44d792 | 5163 | /* Used by function_arg and sparc_function_value_1 to implement the complex |
48028e21 | 5164 | conventions of the 64-bit ABI for passing and returning structures. |
bf44d792 AS |
5165 | Return an expression valid as a return value for the FUNCTION_ARG |
5166 | and TARGET_FUNCTION_VALUE. | |
0020b823 | 5167 | |
48028e21 EB |
5168 | TYPE is the data type of the argument (as a tree). |
5169 | This is null for libcalls where that information may | |
5170 | not be available. | |
5171 | MODE is the argument's machine mode. | |
5172 | SLOTNO is the index number of the argument's slot in the parameter array. | |
5173 | NAMED is nonzero if this argument is a named parameter | |
5174 | (otherwise it is an extra parameter matching an ellipsis). | |
5175 | REGBASE is the regno of the base register for the parameter array. */ | |
4900aa61 | 5176 | |
82d6b402 | 5177 | static rtx |
586de218 | 5178 | function_arg_record_value (const_tree type, enum machine_mode mode, |
fc27d102 | 5179 | int slotno, int named, int regbase) |
82d6b402 RH |
5180 | { |
5181 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
5182 | struct function_arg_record_value_parms parms; | |
75131237 | 5183 | unsigned int nregs; |
82d6b402 RH |
5184 | |
5185 | parms.ret = NULL_RTX; | |
5186 | parms.slotno = slotno; | |
5187 | parms.named = named; | |
5188 | parms.regbase = regbase; | |
48028e21 | 5189 | parms.stack = 0; |
82d6b402 RH |
5190 | |
5191 | /* Compute how many registers we need. */ | |
5192 | parms.nregs = 0; | |
5193 | parms.intoffset = 0; | |
cde85594 | 5194 | function_arg_record_value_1 (type, 0, &parms, false); |
82d6b402 | 5195 | |
1fd05073 | 5196 | /* Take into account pending integer fields. */ |
82d6b402 RH |
5197 | if (parms.intoffset != -1) |
5198 | { | |
0020b823 | 5199 | unsigned int startbit, endbit; |
82d6b402 RH |
5200 | int intslots, this_slotno; |
5201 | ||
0020b823 RH |
5202 | startbit = parms.intoffset & -BITS_PER_WORD; |
5203 | endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
5204 | intslots = (endbit - startbit) / BITS_PER_WORD; | |
82d6b402 RH |
5205 | this_slotno = slotno + parms.intoffset / BITS_PER_WORD; |
5206 | ||
48028e21 EB |
5207 | if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) |
5208 | { | |
5209 | intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); | |
5210 | /* We need to pass this field on the stack. */ | |
5211 | parms.stack = 1; | |
5212 | } | |
82d6b402 RH |
5213 | |
5214 | parms.nregs += intslots; | |
5215 | } | |
5216 | nregs = parms.nregs; | |
5217 | ||
5218 | /* Allocate the vector and handle some annoying special cases. */ | |
5219 | if (nregs == 0) | |
5220 | { | |
5221 | /* ??? Empty structure has no value? Duh? */ | |
5222 | if (typesize <= 0) | |
5223 | { | |
5224 | /* Though there's nothing really to store, return a word register | |
5225 | anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL | |
5226 | leads to breakage due to the fact that there are zero bytes to | |
5227 | load. */ | |
1eac9f59 | 5228 | return gen_rtx_REG (mode, regbase); |
82d6b402 RH |
5229 | } |
5230 | else | |
5231 | { | |
5232 | /* ??? C++ has structures with no fields, and yet a size. Give up | |
5233 | for now and pass everything back in integer registers. */ | |
5234 | nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
5235 | } | |
5236 | if (nregs + slotno > SPARC_INT_ARG_MAX) | |
5237 | nregs = SPARC_INT_ARG_MAX - slotno; | |
5238 | } | |
f5f7d171 | 5239 | gcc_assert (nregs != 0); |
82d6b402 | 5240 | |
48028e21 EB |
5241 | parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs)); |
5242 | ||
5243 | /* If at least one field must be passed on the stack, generate | |
5244 | (parallel [(expr_list (nil) ...) ...]) so that all fields will | |
5245 | also be passed on the stack. We can't do much better because the | |
78a52f11 | 5246 | semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case |
48028e21 EB |
5247 | of structures for which the fields passed exclusively in registers |
5248 | are not at the beginning of the structure. */ | |
5249 | if (parms.stack) | |
5250 | XVECEXP (parms.ret, 0, 0) | |
5251 | = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
82d6b402 RH |
5252 | |
5253 | /* Fill in the entries. */ | |
5254 | parms.nregs = 0; | |
5255 | parms.intoffset = 0; | |
cde85594 | 5256 | function_arg_record_value_2 (type, 0, &parms, false); |
82d6b402 RH |
5257 | function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); |
5258 | ||
f5f7d171 | 5259 | gcc_assert (parms.nregs == nregs); |
82d6b402 RH |
5260 | |
5261 | return parms.ret; | |
5262 | } | |
5263 | ||
bf44d792 | 5264 | /* Used by function_arg and sparc_function_value_1 to implement the conventions |
a7bba6ca | 5265 | of the 64-bit ABI for passing and returning unions. |
bf44d792 AS |
5266 | Return an expression valid as a return value for the FUNCTION_ARG |
5267 | and TARGET_FUNCTION_VALUE. | |
a7bba6ca EB |
5268 | |
5269 | SIZE is the size in bytes of the union. | |
85bbb21f | 5270 | MODE is the argument's machine mode. |
a7bba6ca EB |
5271 | REGNO is the hard register the union will be passed in. */ |
5272 | ||
5273 | static rtx | |
22d8d627 EB |
5274 | function_arg_union_value (int size, enum machine_mode mode, int slotno, |
5275 | int regno) | |
a7bba6ca | 5276 | { |
85bbb21f EB |
5277 | int nwords = ROUND_ADVANCE (size), i; |
5278 | rtx regs; | |
a7bba6ca | 5279 | |
bb05e341 EB |
5280 | /* See comment in previous function for empty structures. */ |
5281 | if (nwords == 0) | |
5282 | return gen_rtx_REG (mode, regno); | |
5283 | ||
22d8d627 EB |
5284 | if (slotno == SPARC_INT_ARG_MAX - 1) |
5285 | nwords = 1; | |
5286 | ||
85bbb21f | 5287 | regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords)); |
a7bba6ca | 5288 | |
85bbb21f | 5289 | for (i = 0; i < nwords; i++) |
45261626 EB |
5290 | { |
5291 | /* Unions are passed left-justified. */ | |
5292 | XVECEXP (regs, 0, i) | |
5293 | = gen_rtx_EXPR_LIST (VOIDmode, | |
5294 | gen_rtx_REG (word_mode, regno), | |
5295 | GEN_INT (UNITS_PER_WORD * i)); | |
5296 | regno++; | |
5297 | } | |
5298 | ||
5299 | return regs; | |
5300 | } | |
5301 | ||
bf44d792 | 5302 | /* Used by function_arg and sparc_function_value_1 to implement the conventions |
45261626 | 5303 | for passing and returning large (BLKmode) vectors. |
bf44d792 AS |
5304 | Return an expression valid as a return value for the FUNCTION_ARG |
5305 | and TARGET_FUNCTION_VALUE. | |
45261626 | 5306 | |
26237a50 | 5307 | SIZE is the size in bytes of the vector (at least 8 bytes). |
45261626 EB |
5308 | REGNO is the FP hard register the vector will be passed in. */ |
5309 | ||
5310 | static rtx | |
26237a50 | 5311 | function_arg_vector_value (int size, int regno) |
45261626 | 5312 | { |
26237a50 | 5313 | int i, nregs = size / 8; |
45261626 EB |
5314 | rtx regs; |
5315 | ||
5316 | regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs)); | |
5317 | ||
5318 | for (i = 0; i < nregs; i++) | |
5319 | { | |
5320 | XVECEXP (regs, 0, i) | |
5321 | = gen_rtx_EXPR_LIST (VOIDmode, | |
26237a50 EB |
5322 | gen_rtx_REG (DImode, regno + 2*i), |
5323 | GEN_INT (i*8)); | |
45261626 | 5324 | } |
a7bba6ca | 5325 | |
85bbb21f | 5326 | return regs; |
a7bba6ca EB |
5327 | } |
5328 | ||
4fb4e4b8 DE |
5329 | /* Handle the FUNCTION_ARG macro. |
5330 | Determine where to put an argument to a function. | |
5331 | Value is zero to push the argument on the stack, | |
5332 | or a hard register in which to store the argument. | |
5333 | ||
5334 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
5335 | the preceding args and about the function being called. | |
5336 | MODE is the argument's machine mode. | |
5337 | TYPE is the data type of the argument (as a tree). | |
5338 | This is null for libcalls where that information may | |
5339 | not be available. | |
5340 | NAMED is nonzero if this argument is a named parameter | |
5341 | (otherwise it is an extra parameter matching an ellipsis). | |
5342 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ | |
61a55e8b DE |
5343 | |
5344 | rtx | |
fc27d102 KG |
5345 | function_arg (const struct sparc_args *cum, enum machine_mode mode, |
5346 | tree type, int named, int incoming_p) | |
61a55e8b | 5347 | { |
4fb4e4b8 DE |
5348 | int regbase = (incoming_p |
5349 | ? SPARC_INCOMING_INT_ARG_FIRST | |
5350 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
5351 | int slotno, regno, padding; | |
45261626 | 5352 | enum mode_class mclass = GET_MODE_CLASS (mode); |
4fb4e4b8 DE |
5353 | |
5354 | slotno = function_arg_slotno (cum, mode, type, named, incoming_p, | |
5355 | ®no, &padding); | |
4fb4e4b8 DE |
5356 | if (slotno == -1) |
5357 | return 0; | |
5358 | ||
ef6843ed EB |
5359 | /* Vector types deserve special treatment because they are polymorphic wrt |
5360 | their mode, depending upon whether VIS instructions are enabled. */ | |
5361 | if (type && TREE_CODE (type) == VECTOR_TYPE) | |
4fb4e4b8 | 5362 | { |
ef6843ed EB |
5363 | HOST_WIDE_INT size = int_size_in_bytes (type); |
5364 | gcc_assert ((TARGET_ARCH32 && size <= 8) | |
5365 | || (TARGET_ARCH64 && size <= 16)); | |
5366 | ||
5367 | if (mode == BLKmode) | |
5368 | return function_arg_vector_value (size, | |
ef6843ed EB |
5369 | SPARC_FP_ARG_FIRST + 2*slotno); |
5370 | else | |
5371 | mclass = MODE_FLOAT; | |
4fb4e4b8 | 5372 | } |
4043d6fb | 5373 | |
ef6843ed EB |
5374 | if (TARGET_ARCH32) |
5375 | return gen_rtx_REG (mode, regno); | |
4043d6fb | 5376 | |
ef6843ed EB |
5377 | /* Structures up to 16 bytes in size are passed in arg slots on the stack |
5378 | and are promoted to registers if possible. */ | |
5379 | if (type && TREE_CODE (type) == RECORD_TYPE) | |
4043d6fb | 5380 | { |
a7bba6ca | 5381 | HOST_WIDE_INT size = int_size_in_bytes (type); |
f5f7d171 | 5382 | gcc_assert (size <= 16); |
4fb4e4b8 | 5383 | |
ef6843ed | 5384 | return function_arg_record_value (type, mode, slotno, named, regbase); |
4043d6fb | 5385 | } |
ef6843ed EB |
5386 | |
5387 | /* Unions up to 16 bytes in size are passed in integer registers. */ | |
5388 | else if (type && TREE_CODE (type) == UNION_TYPE) | |
45261626 | 5389 | { |
45261626 | 5390 | HOST_WIDE_INT size = int_size_in_bytes (type); |
f5f7d171 | 5391 | gcc_assert (size <= 16); |
45261626 | 5392 | |
ef6843ed | 5393 | return function_arg_union_value (size, mode, slotno, regno); |
45261626 EB |
5394 | } |
5395 | ||
4fb4e4b8 DE |
5396 | /* v9 fp args in reg slots beyond the int reg slots get passed in regs |
5397 | but also have the slot allocated for them. | |
5398 | If no prototype is in scope fp values in register slots get passed | |
5399 | in two places, either fp regs and int regs or fp regs and memory. */ | |
ef6843ed EB |
5400 | else if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) |
5401 | && SPARC_FP_REG_P (regno)) | |
4fb4e4b8 | 5402 | { |
ef6843ed | 5403 | rtx reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
5404 | if (cum->prototype_p || cum->libcall_p) |
5405 | { | |
5406 | /* "* 2" because fp reg numbers are recorded in 4 byte | |
5407 | quantities. */ | |
82d6b402 | 5408 | #if 0 |
4fb4e4b8 DE |
5409 | /* ??? This will cause the value to be passed in the fp reg and |
5410 | in the stack. When a prototype exists we want to pass the | |
5411 | value in the reg but reserve space on the stack. That's an | |
956d6950 | 5412 | optimization, and is deferred [for a bit]. */ |
4fb4e4b8 | 5413 | if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) |
254110c2 | 5414 | return gen_rtx_PARALLEL (mode, |
4fb4e4b8 | 5415 | gen_rtvec (2, |
254110c2 | 5416 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 | 5417 | NULL_RTX, const0_rtx), |
254110c2 | 5418 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 DE |
5419 | reg, const0_rtx))); |
5420 | else | |
82d6b402 RH |
5421 | #else |
5422 | /* ??? It seems that passing back a register even when past | |
5423 | the area declared by REG_PARM_STACK_SPACE will allocate | |
5424 | space appropriately, and will not copy the data onto the | |
5425 | stack, exactly as we desire. | |
5426 | ||
5427 | This is due to locate_and_pad_parm being called in | |
5428 | expand_call whenever reg_parm_stack_space > 0, which | |
fae778eb | 5429 | while beneficial to our example here, would seem to be |
82d6b402 RH |
5430 | in error from what had been intended. Ho hum... -- r~ */ |
5431 | #endif | |
4fb4e4b8 DE |
5432 | return reg; |
5433 | } | |
5434 | else | |
5435 | { | |
82d6b402 RH |
5436 | rtx v0, v1; |
5437 | ||
4fb4e4b8 DE |
5438 | if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) |
5439 | { | |
82d6b402 RH |
5440 | int intreg; |
5441 | ||
5442 | /* On incoming, we don't need to know that the value | |
5443 | is passed in %f0 and %i0, and it confuses other parts | |
5444 | causing needless spillage even on the simplest cases. */ | |
5445 | if (incoming_p) | |
5446 | return reg; | |
5447 | ||
5448 | intreg = (SPARC_OUTGOING_INT_ARG_FIRST | |
5449 | + (regno - SPARC_FP_ARG_FIRST) / 2); | |
5450 | ||
5451 | v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
5452 | v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), | |
5453 | const0_rtx); | |
5454 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4fb4e4b8 DE |
5455 | } |
5456 | else | |
82d6b402 RH |
5457 | { |
5458 | v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
5459 | v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
5460 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
5461 | } | |
4fb4e4b8 DE |
5462 | } |
5463 | } | |
ef6843ed EB |
5464 | |
5465 | /* All other aggregate types are passed in an integer register in a mode | |
5466 | corresponding to the size of the type. */ | |
5467 | else if (type && AGGREGATE_TYPE_P (type)) | |
4fb4e4b8 | 5468 | { |
ef6843ed EB |
5469 | HOST_WIDE_INT size = int_size_in_bytes (type); |
5470 | gcc_assert (size <= 16); | |
5471 | ||
5472 | mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); | |
4fb4e4b8 DE |
5473 | } |
5474 | ||
ef6843ed | 5475 | return gen_rtx_REG (mode, regno); |
4fb4e4b8 | 5476 | } |
a7acd911 | 5477 | |
78a52f11 RH |
5478 | /* For an arg passed partly in registers and partly in memory, |
5479 | this is the number of bytes of registers used. | |
4fb4e4b8 | 5480 | For args passed entirely in registers or entirely in memory, zero. |
61a55e8b | 5481 | |
4fb4e4b8 DE |
5482 | Any arg that starts in the first 6 regs but won't entirely fit in them |
5483 | needs partial registers on v8. On v9, structures with integer | |
5484 | values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp | |
5485 | values that begin in the last fp reg [where "last fp reg" varies with the | |
5486 | mode] will be split between that reg and memory. */ | |
61a55e8b | 5487 | |
78a52f11 RH |
5488 | static int |
5489 | sparc_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
5490 | tree type, bool named) | |
4fb4e4b8 DE |
5491 | { |
5492 | int slotno, regno, padding; | |
61a55e8b | 5493 | |
4fb4e4b8 DE |
5494 | /* We pass 0 for incoming_p here, it doesn't matter. */ |
5495 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
5496 | ||
5497 | if (slotno == -1) | |
5498 | return 0; | |
5499 | ||
5500 | if (TARGET_ARCH32) | |
bf62bbf1 | 5501 | { |
4fb4e4b8 DE |
5502 | if ((slotno + (mode == BLKmode |
5503 | ? ROUND_ADVANCE (int_size_in_bytes (type)) | |
5504 | : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) | |
1b5963f7 | 5505 | > SPARC_INT_ARG_MAX) |
78a52f11 | 5506 | return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD; |
4fb4e4b8 DE |
5507 | } |
5508 | else | |
5509 | { | |
8cd5a4e0 | 5510 | /* We are guaranteed by pass_by_reference that the size of the |
78a52f11 RH |
5511 | argument is not greater than 16 bytes, so we only need to return |
5512 | one word if the argument is partially passed in registers. */ | |
1b5963f7 | 5513 | |
4fb4e4b8 DE |
5514 | if (type && AGGREGATE_TYPE_P (type)) |
5515 | { | |
5516 | int size = int_size_in_bytes (type); | |
bf62bbf1 | 5517 | |
1b5963f7 | 5518 | if (size > UNITS_PER_WORD |
4fb4e4b8 | 5519 | && slotno == SPARC_INT_ARG_MAX - 1) |
78a52f11 | 5520 | return UNITS_PER_WORD; |
4fb4e4b8 | 5521 | } |
0a9e65f9 | 5522 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT |
4fb4e4b8 | 5523 | || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT |
c3427c7d | 5524 | && ! (TARGET_FPU && named))) |
4fb4e4b8 | 5525 | { |
0a9e65f9 | 5526 | /* The complex types are passed as packed types. */ |
1b5963f7 EB |
5527 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD |
5528 | && slotno == SPARC_INT_ARG_MAX - 1) | |
78a52f11 | 5529 | return UNITS_PER_WORD; |
4fb4e4b8 DE |
5530 | } |
5531 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5532 | { | |
4fb4e4b8 DE |
5533 | if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) |
5534 | > SPARC_FP_ARG_MAX) | |
78a52f11 | 5535 | return UNITS_PER_WORD; |
4fb4e4b8 | 5536 | } |
bf62bbf1 | 5537 | } |
1b5963f7 EB |
5538 | |
5539 | return 0; | |
4fb4e4b8 | 5540 | } |
61a55e8b | 5541 | |
45261626 EB |
5542 | /* Handle the TARGET_PASS_BY_REFERENCE target hook. |
5543 | Specify whether to pass the argument by reference. */ | |
4fb4e4b8 | 5544 | |
8cd5a4e0 RH |
5545 | static bool |
5546 | sparc_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
586de218 | 5547 | enum machine_mode mode, const_tree type, |
8cd5a4e0 | 5548 | bool named ATTRIBUTE_UNUSED) |
4fb4e4b8 DE |
5549 | { |
5550 | if (TARGET_ARCH32) | |
45261626 EB |
5551 | /* Original SPARC 32-bit ABI says that structures and unions, |
5552 | and quad-precision floats are passed by reference. For Pascal, | |
5553 | also pass arrays by reference. All other base types are passed | |
5554 | in registers. | |
5555 | ||
5556 | Extended ABI (as implemented by the Sun compiler) says that all | |
5557 | complex floats are passed by reference. Pass complex integers | |
5558 | in registers up to 8 bytes. More generally, enforce the 2-word | |
5559 | cap for passing arguments in registers. | |
5560 | ||
5561 | Vector ABI (as implemented by the Sun VIS SDK) says that vector | |
5562 | integers are passed like floats of the same size, that is in | |
5563 | registers up to 8 bytes. Pass all vector floats by reference | |
5564 | like structure and unions. */ | |
ef6843ed EB |
5565 | return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type))) |
5566 | || mode == SCmode | |
5567 | /* Catch CDImode, TFmode, DCmode and TCmode. */ | |
5568 | || GET_MODE_SIZE (mode) > 8 | |
5569 | || (type | |
5570 | && TREE_CODE (type) == VECTOR_TYPE | |
5571 | && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)); | |
4fb4e4b8 | 5572 | else |
45261626 EB |
5573 | /* Original SPARC 64-bit ABI says that structures and unions |
5574 | smaller than 16 bytes are passed in registers, as well as | |
ef6843ed | 5575 | all other base types. |
4900aa61 | 5576 | |
45261626 EB |
5577 | Extended ABI (as implemented by the Sun compiler) says that |
5578 | complex floats are passed in registers up to 16 bytes. Pass | |
5579 | all complex integers in registers up to 16 bytes. More generally, | |
5580 | enforce the 2-word cap for passing arguments in registers. | |
5581 | ||
5582 | Vector ABI (as implemented by the Sun VIS SDK) says that vector | |
5583 | integers are passed like floats of the same size, that is in | |
5584 | registers (up to 16 bytes). Pass all vector floats like structure | |
5585 | and unions. */ | |
ef6843ed EB |
5586 | return ((type |
5587 | && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE) | |
5588 | && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16) | |
5589 | /* Catch CTImode and TCmode. */ | |
5590 | || GET_MODE_SIZE (mode) > 16); | |
4fb4e4b8 DE |
5591 | } |
5592 | ||
5593 | /* Handle the FUNCTION_ARG_ADVANCE macro. | |
5594 | Update the data in CUM to advance over an argument | |
5595 | of mode MODE and data type TYPE. | |
5596 | TYPE is null for libcalls where that information may not be available. */ | |
5597 | ||
5598 | void | |
fc27d102 KG |
5599 | function_arg_advance (struct sparc_args *cum, enum machine_mode mode, |
5600 | tree type, int named) | |
4fb4e4b8 DE |
5601 | { |
5602 | int slotno, regno, padding; | |
5603 | ||
5604 | /* We pass 0 for incoming_p here, it doesn't matter. */ | |
5605 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
5606 | ||
5607 | /* If register required leading padding, add it. */ | |
5608 | if (slotno != -1) | |
5609 | cum->words += padding; | |
eadceb59 | 5610 | |
4fb4e4b8 DE |
5611 | if (TARGET_ARCH32) |
5612 | { | |
5613 | cum->words += (mode != BLKmode | |
5614 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
5615 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
5616 | } | |
5617 | else | |
5618 | { | |
5619 | if (type && AGGREGATE_TYPE_P (type)) | |
5620 | { | |
5621 | int size = int_size_in_bytes (type); | |
5622 | ||
5623 | if (size <= 8) | |
5624 | ++cum->words; | |
5625 | else if (size <= 16) | |
5626 | cum->words += 2; | |
5627 | else /* passed by reference */ | |
5628 | ++cum->words; | |
5629 | } | |
4fb4e4b8 DE |
5630 | else |
5631 | { | |
5632 | cum->words += (mode != BLKmode | |
5633 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
5634 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
5635 | } | |
eadceb59 | 5636 | } |
4fb4e4b8 | 5637 | } |
eadceb59 | 5638 | |
4fb4e4b8 DE |
5639 | /* Handle the FUNCTION_ARG_PADDING macro. |
5640 | For the 64 bit ABI structs are always stored left shifted in their | |
5641 | argument slot. */ | |
5642 | ||
5643 | enum direction | |
586de218 | 5644 | function_arg_padding (enum machine_mode mode, const_tree type) |
4fb4e4b8 | 5645 | { |
c85f7c16 JL |
5646 | if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) |
5647 | return upward; | |
61a55e8b | 5648 | |
d3704c46 KH |
5649 | /* Fall back to the default. */ |
5650 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
61a55e8b | 5651 | } |
82d6b402 | 5652 | |
1b5963f7 EB |
5653 | /* Handle the TARGET_RETURN_IN_MEMORY target hook. |
5654 | Specify whether to return the return value in memory. */ | |
5655 | ||
5656 | static bool | |
586de218 | 5657 | sparc_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
1b5963f7 EB |
5658 | { |
5659 | if (TARGET_ARCH32) | |
45261626 EB |
5660 | /* Original SPARC 32-bit ABI says that structures and unions, |
5661 | and quad-precision floats are returned in memory. All other | |
5662 | base types are returned in registers. | |
5663 | ||
5664 | Extended ABI (as implemented by the Sun compiler) says that | |
5665 | all complex floats are returned in registers (8 FP registers | |
5666 | at most for '_Complex long double'). Return all complex integers | |
5667 | in registers (4 at most for '_Complex long long'). | |
5668 | ||
5669 | Vector ABI (as implemented by the Sun VIS SDK) says that vector | |
5670 | integers are returned like floats of the same size, that is in | |
5671 | registers up to 8 bytes and in memory otherwise. Return all | |
5672 | vector floats in memory like structure and unions; note that | |
5673 | they always have BLKmode like the latter. */ | |
1b5963f7 EB |
5674 | return (TYPE_MODE (type) == BLKmode |
5675 | || TYPE_MODE (type) == TFmode | |
45261626 EB |
5676 | || (TREE_CODE (type) == VECTOR_TYPE |
5677 | && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)); | |
1b5963f7 EB |
5678 | else |
5679 | /* Original SPARC 64-bit ABI says that structures and unions | |
45261626 EB |
5680 | smaller than 32 bytes are returned in registers, as well as |
5681 | all other base types. | |
4900aa61 | 5682 | |
45261626 EB |
5683 | Extended ABI (as implemented by the Sun compiler) says that all |
5684 | complex floats are returned in registers (8 FP registers at most | |
5685 | for '_Complex long double'). Return all complex integers in | |
5686 | registers (4 at most for '_Complex TItype'). | |
5687 | ||
5688 | Vector ABI (as implemented by the Sun VIS SDK) says that vector | |
5689 | integers are returned like floats of the same size, that is in | |
5690 | registers. Return all vector floats like structure and unions; | |
5691 | note that they always have BLKmode like the latter. */ | |
1b5963f7 | 5692 | return ((TYPE_MODE (type) == BLKmode |
45261626 | 5693 | && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32)); |
1b5963f7 EB |
5694 | } |
5695 | ||
5696 | /* Handle the TARGET_STRUCT_VALUE target hook. | |
5697 | Return where to find the structure return value address. */ | |
5698 | ||
5699 | static rtx | |
2225b57c | 5700 | sparc_struct_value_rtx (tree fndecl, int incoming) |
1b5963f7 EB |
5701 | { |
5702 | if (TARGET_ARCH64) | |
5703 | return 0; | |
5704 | else | |
5705 | { | |
1da4c3a7 EB |
5706 | rtx mem; |
5707 | ||
1b5963f7 | 5708 | if (incoming) |
1da4c3a7 EB |
5709 | mem = gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, |
5710 | STRUCT_VALUE_OFFSET)); | |
1b5963f7 | 5711 | else |
1da4c3a7 EB |
5712 | mem = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, |
5713 | STRUCT_VALUE_OFFSET)); | |
5714 | ||
4900aa61 EB |
5715 | /* Only follow the SPARC ABI for fixed-size structure returns. |
5716 | Variable size structure returns are handled per the normal | |
2225b57c | 5717 | procedures in GCC. This is enabled by -mstd-struct-return */ |
4900aa61 | 5718 | if (incoming == 2 |
2225b57c CD |
5719 | && sparc_std_struct_return |
5720 | && TYPE_SIZE_UNIT (TREE_TYPE (fndecl)) | |
5721 | && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl))) == INTEGER_CST) | |
5722 | { | |
5723 | /* We must check and adjust the return address, as it is | |
5724 | optional as to whether the return object is really | |
5725 | provided. */ | |
5726 | rtx ret_rtx = gen_rtx_REG (Pmode, 31); | |
5727 | rtx scratch = gen_reg_rtx (SImode); | |
4900aa61 | 5728 | rtx endlab = gen_label_rtx (); |
2225b57c CD |
5729 | |
5730 | /* Calculate the return object size */ | |
5731 | tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl)); | |
5732 | rtx size_rtx = GEN_INT (TREE_INT_CST_LOW (size) & 0xfff); | |
5733 | /* Construct a temporary return value */ | |
5734 | rtx temp_val = assign_stack_local (Pmode, TREE_INT_CST_LOW (size), 0); | |
5735 | ||
5736 | /* Implement SPARC 32-bit psABI callee returns struck checking | |
4900aa61 EB |
5737 | requirements: |
5738 | ||
2225b57c CD |
5739 | Fetch the instruction where we will return to and see if |
5740 | it's an unimp instruction (the most significant 10 bits | |
5741 | will be zero). */ | |
5742 | emit_move_insn (scratch, gen_rtx_MEM (SImode, | |
5743 | plus_constant (ret_rtx, 8))); | |
5744 | /* Assume the size is valid and pre-adjust */ | |
5745 | emit_insn (gen_add3_insn (ret_rtx, ret_rtx, GEN_INT (4))); | |
5746 | emit_cmp_and_jump_insns (scratch, size_rtx, EQ, const0_rtx, SImode, 0, endlab); | |
5747 | emit_insn (gen_sub3_insn (ret_rtx, ret_rtx, GEN_INT (4))); | |
4900aa61 | 5748 | /* Assign stack temp: |
2225b57c CD |
5749 | Write the address of the memory pointed to by temp_val into |
5750 | the memory pointed to by mem */ | |
5751 | emit_move_insn (mem, XEXP (temp_val, 0)); | |
5752 | emit_label (endlab); | |
5753 | } | |
5754 | ||
1da4c3a7 EB |
5755 | set_mem_alias_set (mem, struct_value_alias_set); |
5756 | return mem; | |
1b5963f7 EB |
5757 | } |
5758 | } | |
5759 | ||
bf44d792 | 5760 | /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook. |
82d6b402 | 5761 | For v9, function return values are subject to the same rules as arguments, |
1b5963f7 | 5762 | except that up to 32 bytes may be returned in registers. */ |
82d6b402 | 5763 | |
bf44d792 AS |
5764 | static rtx |
5765 | sparc_function_value_1 (const_tree type, enum machine_mode mode, | |
5766 | bool outgoing) | |
82d6b402 | 5767 | { |
1b5963f7 | 5768 | /* Beware that the two values are swapped here wrt function_arg. */ |
bf44d792 AS |
5769 | int regbase = (outgoing |
5770 | ? SPARC_INCOMING_INT_ARG_FIRST | |
5771 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
45261626 | 5772 | enum mode_class mclass = GET_MODE_CLASS (mode); |
82d6b402 | 5773 | int regno; |
82d6b402 | 5774 | |
ef6843ed EB |
5775 | /* Vector types deserve special treatment because they are polymorphic wrt |
5776 | their mode, depending upon whether VIS instructions are enabled. */ | |
45261626 EB |
5777 | if (type && TREE_CODE (type) == VECTOR_TYPE) |
5778 | { | |
45261626 | 5779 | HOST_WIDE_INT size = int_size_in_bytes (type); |
f5f7d171 JM |
5780 | gcc_assert ((TARGET_ARCH32 && size <= 8) |
5781 | || (TARGET_ARCH64 && size <= 32)); | |
45261626 EB |
5782 | |
5783 | if (mode == BLKmode) | |
5784 | return function_arg_vector_value (size, | |
45261626 EB |
5785 | SPARC_FP_ARG_FIRST); |
5786 | else | |
5787 | mclass = MODE_FLOAT; | |
5788 | } | |
ef6843ed EB |
5789 | |
5790 | if (TARGET_ARCH64 && type) | |
82d6b402 | 5791 | { |
ef6843ed | 5792 | /* Structures up to 32 bytes in size are returned in registers. */ |
82d6b402 RH |
5793 | if (TREE_CODE (type) == RECORD_TYPE) |
5794 | { | |
ef6843ed EB |
5795 | HOST_WIDE_INT size = int_size_in_bytes (type); |
5796 | gcc_assert (size <= 32); | |
82d6b402 | 5797 | |
1eac9f59 | 5798 | return function_arg_record_value (type, mode, 0, 1, regbase); |
82d6b402 | 5799 | } |
ef6843ed EB |
5800 | |
5801 | /* Unions up to 32 bytes in size are returned in integer registers. */ | |
a7bba6ca EB |
5802 | else if (TREE_CODE (type) == UNION_TYPE) |
5803 | { | |
5804 | HOST_WIDE_INT size = int_size_in_bytes (type); | |
f5f7d171 | 5805 | gcc_assert (size <= 32); |
a7bba6ca | 5806 | |
22d8d627 | 5807 | return function_arg_union_value (size, mode, 0, regbase); |
a7bba6ca | 5808 | } |
ef6843ed EB |
5809 | |
5810 | /* Objects that require it are returned in FP registers. */ | |
5811 | else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) | |
5812 | ; | |
5813 | ||
5814 | /* All other aggregate types are returned in an integer register in a | |
5815 | mode corresponding to the size of the type. */ | |
8a7199ad | 5816 | else if (AGGREGATE_TYPE_P (type)) |
82d6b402 | 5817 | { |
8a7199ad RK |
5818 | /* All other aggregate types are passed in an integer register |
5819 | in a mode corresponding to the size of the type. */ | |
ef6843ed EB |
5820 | HOST_WIDE_INT size = int_size_in_bytes (type); |
5821 | gcc_assert (size <= 32); | |
82d6b402 | 5822 | |
ef6843ed | 5823 | mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); |
c74fd3f1 EB |
5824 | |
5825 | /* ??? We probably should have made the same ABI change in | |
5826 | 3.4.0 as the one we made for unions. The latter was | |
5827 | required by the SCD though, while the former is not | |
5828 | specified, so we favored compatibility and efficiency. | |
5829 | ||
5830 | Now we're stuck for aggregates larger than 16 bytes, | |
5831 | because OImode vanished in the meantime. Let's not | |
5832 | try to be unduly clever, and simply follow the ABI | |
5833 | for unions in that case. */ | |
5834 | if (mode == BLKmode) | |
ef6843ed | 5835 | return function_arg_union_value (size, mode, 0, regbase); |
45261626 EB |
5836 | else |
5837 | mclass = MODE_INT; | |
82d6b402 | 5838 | } |
ef6843ed | 5839 | |
cde0f3fd PB |
5840 | /* This must match sparc_promote_function_mode. |
5841 | ??? Maybe 32-bit pointers should actually remain in Pmode? */ | |
ef6843ed | 5842 | else if (mclass == MODE_INT && GET_MODE_SIZE (mode) < UNITS_PER_WORD) |
a7bba6ca | 5843 | mode = word_mode; |
82d6b402 RH |
5844 | } |
5845 | ||
ef6843ed | 5846 | if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) && TARGET_FPU) |
1b5963f7 | 5847 | regno = SPARC_FP_ARG_FIRST; |
82d6b402 | 5848 | else |
1b5963f7 | 5849 | regno = regbase; |
82d6b402 | 5850 | |
254110c2 | 5851 | return gen_rtx_REG (mode, regno); |
82d6b402 RH |
5852 | } |
5853 | ||
bf44d792 AS |
5854 | /* Handle TARGET_FUNCTION_VALUE. |
5855 | ||
5856 | On SPARC the value is found in the first "output" register, but the called | |
5857 | function leaves it in the first "input" register. */ | |
5858 | ||
5859 | static rtx | |
5860 | sparc_function_value (const_tree valtype, | |
5861 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
5862 | bool outgoing) | |
5863 | { | |
5864 | return sparc_function_value_1 (valtype, TYPE_MODE (valtype), outgoing); | |
5865 | } | |
5866 | ||
5867 | /* Handle TARGET_LIBCALL_VALUE. */ | |
5868 | ||
5869 | static rtx | |
5870 | sparc_libcall_value (enum machine_mode mode, | |
5871 | const_rtx fun ATTRIBUTE_UNUSED) | |
5872 | { | |
5873 | return sparc_function_value_1 (NULL_TREE, mode, false); | |
5874 | } | |
5875 | ||
5876 | /* Handle FUNCTION_VALUE_REGNO_P. | |
5877 | On SPARC, the first "output" reg is used for integer values, and | |
5878 | the first floating point register is used for floating point values. */ | |
5879 | ||
5880 | static bool | |
5881 | sparc_function_value_regno_p (const unsigned int regno) | |
5882 | { | |
5883 | return (regno == 8 || regno == 32); | |
5884 | } | |
5885 | ||
648d2ffc RH |
5886 | /* Do what is necessary for `va_start'. We look at the current function |
5887 | to determine if stdarg or varargs is used and return the address of | |
5888 | the first unnamed parameter. */ | |
3ea1fdd3 | 5889 | |
3e2cc1d1 | 5890 | static rtx |
fc27d102 | 5891 | sparc_builtin_saveregs (void) |
3ea1fdd3 | 5892 | { |
38173d38 | 5893 | int first_reg = crtl->args.info.words; |
3ea1fdd3 JW |
5894 | rtx address; |
5895 | int regno; | |
5896 | ||
1b5963f7 | 5897 | for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++) |
254110c2 | 5898 | emit_move_insn (gen_rtx_MEM (word_mode, |
8ac61af7 RK |
5899 | gen_rtx_PLUS (Pmode, |
5900 | frame_pointer_rtx, | |
563c12b0 | 5901 | GEN_INT (FIRST_PARM_OFFSET (0) |
8ac61af7 RK |
5902 | + (UNITS_PER_WORD |
5903 | * regno)))), | |
254110c2 | 5904 | gen_rtx_REG (word_mode, |
1b5963f7 | 5905 | SPARC_INCOMING_INT_ARG_FIRST + regno)); |
3ea1fdd3 | 5906 | |
254110c2 | 5907 | address = gen_rtx_PLUS (Pmode, |
8ac61af7 | 5908 | frame_pointer_rtx, |
563c12b0 | 5909 | GEN_INT (FIRST_PARM_OFFSET (0) |
8ac61af7 | 5910 | + UNITS_PER_WORD * first_reg)); |
3ea1fdd3 JW |
5911 | |
5912 | return address; | |
5913 | } | |
a8b2c8a1 | 5914 | |
1b5963f7 | 5915 | /* Implement `va_start' for stdarg. */ |
a8b2c8a1 | 5916 | |
d7bd8aeb | 5917 | static void |
fc27d102 | 5918 | sparc_va_start (tree valist, rtx nextarg) |
a8b2c8a1 RH |
5919 | { |
5920 | nextarg = expand_builtin_saveregs (); | |
e5faf155 | 5921 | std_expand_builtin_va_start (valist, nextarg); |
a8b2c8a1 RH |
5922 | } |
5923 | ||
1b5963f7 | 5924 | /* Implement `va_arg' for stdarg. */ |
a8b2c8a1 | 5925 | |
35652573 | 5926 | static tree |
726a989a RB |
5927 | sparc_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, |
5928 | gimple_seq *post_p) | |
5f393b25 JM |
5929 | { |
5930 | HOST_WIDE_INT size, rsize, align; | |
5931 | tree addr, incr; | |
5932 | bool indirect; | |
5933 | tree ptrtype = build_pointer_type (type); | |
5934 | ||
22d66adf | 5935 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
5f393b25 JM |
5936 | { |
5937 | indirect = true; | |
5938 | size = rsize = UNITS_PER_WORD; | |
5939 | align = 0; | |
5940 | } | |
5941 | else | |
5942 | { | |
5943 | indirect = false; | |
5944 | size = int_size_in_bytes (type); | |
5945 | rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; | |
5946 | align = 0; | |
3764d512 | 5947 | |
5f393b25 JM |
5948 | if (TARGET_ARCH64) |
5949 | { | |
5950 | /* For SPARC64, objects requiring 16-byte alignment get it. */ | |
5951 | if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) | |
5952 | align = 2 * UNITS_PER_WORD; | |
5953 | ||
5954 | /* SPARC-V9 ABI states that structures up to 16 bytes in size | |
22d66adf | 5955 | are left-justified in their slots. */ |
5f393b25 JM |
5956 | if (AGGREGATE_TYPE_P (type)) |
5957 | { | |
5958 | if (size == 0) | |
5959 | size = rsize = UNITS_PER_WORD; | |
5960 | else | |
5961 | size = rsize; | |
5962 | } | |
5963 | } | |
5964 | } | |
5965 | ||
5966 | incr = valist; | |
5967 | if (align) | |
5968 | { | |
5be014d5 AP |
5969 | incr = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr, |
5970 | size_int (align - 1)); | |
5971 | incr = fold_convert (sizetype, incr); | |
5972 | incr = fold_build2 (BIT_AND_EXPR, sizetype, incr, | |
5973 | size_int (-align)); | |
5974 | incr = fold_convert (ptr_type_node, incr); | |
5f393b25 JM |
5975 | } |
5976 | ||
5977 | gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue); | |
5978 | addr = incr; | |
5979 | ||
5980 | if (BYTES_BIG_ENDIAN && size < rsize) | |
5be014d5 AP |
5981 | addr = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr, |
5982 | size_int (rsize - size)); | |
5f393b25 JM |
5983 | |
5984 | if (indirect) | |
5985 | { | |
5986 | addr = fold_convert (build_pointer_type (ptrtype), addr); | |
22d66adf | 5987 | addr = build_va_arg_indirect_ref (addr); |
5f393b25 | 5988 | } |
3764d512 EB |
5989 | |
5990 | /* If the address isn't aligned properly for the type, we need a temporary. | |
5991 | FIXME: This is inefficient, usually we can do this in registers. */ | |
5992 | else if (align == 0 && TYPE_ALIGN (type) > BITS_PER_WORD) | |
5f393b25 JM |
5993 | { |
5994 | tree tmp = create_tmp_var (type, "va_arg_tmp"); | |
5995 | tree dest_addr = build_fold_addr_expr (tmp); | |
3764d512 EB |
5996 | tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY], |
5997 | 3, dest_addr, addr, size_int (rsize)); | |
5998 | TREE_ADDRESSABLE (tmp) = 1; | |
5f393b25 JM |
5999 | gimplify_and_add (copy, pre_p); |
6000 | addr = dest_addr; | |
6001 | } | |
3764d512 | 6002 | |
5f393b25 JM |
6003 | else |
6004 | addr = fold_convert (ptrtype, addr); | |
6005 | ||
3764d512 EB |
6006 | incr |
6007 | = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr, size_int (rsize)); | |
726a989a | 6008 | gimplify_assign (valist, incr, post_p); |
5f393b25 | 6009 | |
22d66adf | 6010 | return build_va_arg_indirect_ref (addr); |
5f393b25 | 6011 | } |
ab835497 | 6012 | \f |
c75d6010 JM |
6013 | /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook. |
6014 | Specify whether the vector mode is supported by the hardware. */ | |
6015 | ||
6016 | static bool | |
6017 | sparc_vector_mode_supported_p (enum machine_mode mode) | |
6018 | { | |
6019 | return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false; | |
6020 | } | |
6021 | \f | |
1b3c2c2d EB |
6022 | /* Return the string to output an unconditional branch to LABEL, which is |
6023 | the operand number of the label. | |
6024 | ||
6025 | DEST is the destination insn (i.e. the label), INSN is the source. */ | |
6026 | ||
6027 | const char * | |
6028 | output_ubranch (rtx dest, int label, rtx insn) | |
6029 | { | |
6030 | static char string[64]; | |
4e5b002b | 6031 | bool v9_form = false; |
1b3c2c2d EB |
6032 | char *p; |
6033 | ||
4e5b002b | 6034 | if (TARGET_V9 && INSN_ADDRESSES_SET_P ()) |
1b3c2c2d | 6035 | { |
4e5b002b EB |
6036 | int delta = (INSN_ADDRESSES (INSN_UID (dest)) |
6037 | - INSN_ADDRESSES (INSN_UID (insn))); | |
6038 | /* Leave some instructions for "slop". */ | |
6039 | if (delta >= -260000 && delta < 260000) | |
6040 | v9_form = true; | |
1b3c2c2d | 6041 | } |
1b3c2c2d | 6042 | |
4e5b002b EB |
6043 | if (v9_form) |
6044 | strcpy (string, "ba%*,pt\t%%xcc, "); | |
6045 | else | |
6046 | strcpy (string, "b%*\t"); | |
1b3c2c2d EB |
6047 | |
6048 | p = strchr (string, '\0'); | |
6049 | *p++ = '%'; | |
6050 | *p++ = 'l'; | |
6051 | *p++ = '0' + label; | |
6052 | *p++ = '%'; | |
4e5b002b | 6053 | *p++ = '('; |
1b3c2c2d EB |
6054 | *p = '\0'; |
6055 | ||
6056 | return string; | |
6057 | } | |
6058 | ||
ab835497 | 6059 | /* Return the string to output a conditional branch to LABEL, which is |
c4ce6853 DE |
6060 | the operand number of the label. OP is the conditional expression. |
6061 | XEXP (OP, 0) is assumed to be a condition code register (integer or | |
6062 | floating point) and its mode specifies what kind of comparison we made. | |
61a55e8b | 6063 | |
1b3c2c2d EB |
6064 | DEST is the destination insn (i.e. the label), INSN is the source. |
6065 | ||
5e7a8ee0 | 6066 | REVERSED is nonzero if we should reverse the sense of the comparison. |
ab835497 | 6067 | |
4e5b002b | 6068 | ANNUL is nonzero if we should generate an annulling branch. */ |
ab835497 | 6069 | |
a6163c22 | 6070 | const char * |
fc27d102 | 6071 | output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, |
4e5b002b | 6072 | rtx insn) |
ab835497 | 6073 | { |
a6163c22 | 6074 | static char string[64]; |
ab835497 | 6075 | enum rtx_code code = GET_CODE (op); |
c4ce6853 DE |
6076 | rtx cc_reg = XEXP (op, 0); |
6077 | enum machine_mode mode = GET_MODE (cc_reg); | |
0b82d204 JJ |
6078 | const char *labelno, *branch; |
6079 | int spaces = 8, far; | |
6080 | char *p; | |
6081 | ||
6082 | /* v9 branches are limited to +-1MB. If it is too far away, | |
6083 | change | |
6084 | ||
6085 | bne,pt %xcc, .LC30 | |
6086 | ||
6087 | to | |
6088 | ||
6089 | be,pn %xcc, .+12 | |
a6163c22 | 6090 | nop |
0b82d204 JJ |
6091 | ba .LC30 |
6092 | ||
6093 | and | |
6094 | ||
6095 | fbne,a,pn %fcc2, .LC29 | |
61a55e8b | 6096 | |
0b82d204 JJ |
6097 | to |
6098 | ||
6099 | fbe,pt %fcc2, .+16 | |
a6163c22 | 6100 | nop |
0b82d204 JJ |
6101 | ba .LC29 */ |
6102 | ||
883d9e0c | 6103 | far = TARGET_V9 && (get_attr_length (insn) >= 3); |
0b82d204 | 6104 | if (reversed ^ far) |
ab835497 | 6105 | { |
e267e177 RH |
6106 | /* Reversal of FP compares takes care -- an ordered compare |
6107 | becomes an unordered compare and vice versa. */ | |
4d449554 | 6108 | if (mode == CCFPmode || mode == CCFPEmode) |
7913f3d0 | 6109 | code = reverse_condition_maybe_unordered (code); |
ab835497 | 6110 | else |
e267e177 | 6111 | code = reverse_condition (code); |
ab835497 RK |
6112 | } |
6113 | ||
e267e177 RH |
6114 | /* Start by writing the branch condition. */ |
6115 | if (mode == CCFPmode || mode == CCFPEmode) | |
5850dc00 RH |
6116 | { |
6117 | switch (code) | |
6118 | { | |
6119 | case NE: | |
6120 | branch = "fbne"; | |
6121 | break; | |
6122 | case EQ: | |
6123 | branch = "fbe"; | |
6124 | break; | |
6125 | case GE: | |
6126 | branch = "fbge"; | |
6127 | break; | |
6128 | case GT: | |
6129 | branch = "fbg"; | |
6130 | break; | |
6131 | case LE: | |
6132 | branch = "fble"; | |
6133 | break; | |
6134 | case LT: | |
6135 | branch = "fbl"; | |
6136 | break; | |
6137 | case UNORDERED: | |
6138 | branch = "fbu"; | |
6139 | break; | |
6140 | case ORDERED: | |
6141 | branch = "fbo"; | |
6142 | break; | |
6143 | case UNGT: | |
6144 | branch = "fbug"; | |
6145 | break; | |
6146 | case UNLT: | |
6147 | branch = "fbul"; | |
6148 | break; | |
6149 | case UNEQ: | |
6150 | branch = "fbue"; | |
6151 | break; | |
6152 | case UNGE: | |
6153 | branch = "fbuge"; | |
6154 | break; | |
6155 | case UNLE: | |
6156 | branch = "fbule"; | |
6157 | break; | |
6158 | case LTGT: | |
6159 | branch = "fblg"; | |
6160 | break; | |
6161 | ||
6162 | default: | |
f5f7d171 | 6163 | gcc_unreachable (); |
5850dc00 RH |
6164 | } |
6165 | ||
6166 | /* ??? !v9: FP branches cannot be preceded by another floating point | |
6167 | insn. Because there is currently no concept of pre-delay slots, | |
6168 | we can fix this only by always emitting a nop before a floating | |
6169 | point branch. */ | |
6170 | ||
6171 | string[0] = '\0'; | |
6172 | if (! TARGET_V9) | |
6173 | strcpy (string, "nop\n\t"); | |
6174 | strcat (string, branch); | |
6175 | } | |
e267e177 | 6176 | else |
5850dc00 RH |
6177 | { |
6178 | switch (code) | |
6179 | { | |
6180 | case NE: | |
6181 | branch = "bne"; | |
6182 | break; | |
6183 | case EQ: | |
6184 | branch = "be"; | |
6185 | break; | |
6186 | case GE: | |
0b82d204 | 6187 | if (mode == CC_NOOVmode || mode == CCX_NOOVmode) |
5850dc00 RH |
6188 | branch = "bpos"; |
6189 | else | |
6190 | branch = "bge"; | |
6191 | break; | |
6192 | case GT: | |
6193 | branch = "bg"; | |
6194 | break; | |
6195 | case LE: | |
6196 | branch = "ble"; | |
6197 | break; | |
6198 | case LT: | |
0b82d204 | 6199 | if (mode == CC_NOOVmode || mode == CCX_NOOVmode) |
5850dc00 RH |
6200 | branch = "bneg"; |
6201 | else | |
6202 | branch = "bl"; | |
6203 | break; | |
6204 | case GEU: | |
6205 | branch = "bgeu"; | |
6206 | break; | |
6207 | case GTU: | |
6208 | branch = "bgu"; | |
6209 | break; | |
6210 | case LEU: | |
6211 | branch = "bleu"; | |
6212 | break; | |
6213 | case LTU: | |
6214 | branch = "blu"; | |
6215 | break; | |
6216 | ||
6217 | default: | |
f5f7d171 | 6218 | gcc_unreachable (); |
5850dc00 RH |
6219 | } |
6220 | strcpy (string, branch); | |
6221 | } | |
e267e177 | 6222 | spaces -= strlen (branch); |
0b82d204 | 6223 | p = strchr (string, '\0'); |
e267e177 | 6224 | |
ab835497 | 6225 | /* Now add the annulling, the label, and a possible noop. */ |
0b82d204 | 6226 | if (annul && ! far) |
e0d80184 | 6227 | { |
0b82d204 JJ |
6228 | strcpy (p, ",a"); |
6229 | p += 2; | |
e0d80184 DM |
6230 | spaces -= 2; |
6231 | } | |
ab835497 | 6232 | |
883d9e0c | 6233 | if (TARGET_V9) |
61a55e8b | 6234 | { |
c6b0465b | 6235 | rtx note; |
0b82d204 | 6236 | int v8 = 0; |
c6b0465b | 6237 | |
0b82d204 | 6238 | if (! far && insn && INSN_ADDRESSES_SET_P ()) |
e0d80184 | 6239 | { |
0b82d204 JJ |
6240 | int delta = (INSN_ADDRESSES (INSN_UID (dest)) |
6241 | - INSN_ADDRESSES (INSN_UID (insn))); | |
6242 | /* Leave some instructions for "slop". */ | |
6243 | if (delta < -260000 || delta >= 260000) | |
6244 | v8 = 1; | |
e0d80184 | 6245 | } |
c6b0465b | 6246 | |
61a55e8b DE |
6247 | if (mode == CCFPmode || mode == CCFPEmode) |
6248 | { | |
0b82d204 | 6249 | static char v9_fcc_labelno[] = "%%fccX, "; |
61a55e8b | 6250 | /* Set the char indicating the number of the fcc reg to use. */ |
0b82d204 JJ |
6251 | v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; |
6252 | labelno = v9_fcc_labelno; | |
6253 | if (v8) | |
6254 | { | |
f5f7d171 JM |
6255 | gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG); |
6256 | labelno = ""; | |
0b82d204 | 6257 | } |
61a55e8b DE |
6258 | } |
6259 | else if (mode == CCXmode || mode == CCX_NOOVmode) | |
0b82d204 JJ |
6260 | { |
6261 | labelno = "%%xcc, "; | |
f5f7d171 | 6262 | gcc_assert (! v8); |
0b82d204 | 6263 | } |
61a55e8b | 6264 | else |
0b82d204 JJ |
6265 | { |
6266 | labelno = "%%icc, "; | |
6267 | if (v8) | |
6268 | labelno = ""; | |
6269 | } | |
6270 | ||
4f31cce8 | 6271 | if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) |
0b82d204 JJ |
6272 | { |
6273 | strcpy (p, | |
4f31cce8 | 6274 | ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) |
0b82d204 JJ |
6275 | ? ",pt" : ",pn"); |
6276 | p += 3; | |
6277 | spaces -= 3; | |
6278 | } | |
61a55e8b | 6279 | } |
883d9e0c EB |
6280 | else |
6281 | labelno = ""; | |
6282 | ||
e0d80184 | 6283 | if (spaces > 0) |
0b82d204 | 6284 | *p++ = '\t'; |
e0d80184 | 6285 | else |
0b82d204 JJ |
6286 | *p++ = ' '; |
6287 | strcpy (p, labelno); | |
6288 | p = strchr (p, '\0'); | |
6289 | if (far) | |
6290 | { | |
a6163c22 | 6291 | strcpy (p, ".+12\n\t nop\n\tb\t"); |
4e5b002b EB |
6292 | /* Skip the next insn if requested or |
6293 | if we know that it will be a nop. */ | |
6294 | if (annul || ! final_sequence) | |
0b82d204 | 6295 | p[3] = '6'; |
a6163c22 | 6296 | p += 14; |
0b82d204 JJ |
6297 | } |
6298 | *p++ = '%'; | |
6299 | *p++ = 'l'; | |
0b82d204 | 6300 | *p++ = label + '0'; |
4e5b002b EB |
6301 | *p++ = '%'; |
6302 | *p++ = '#'; | |
0b82d204 | 6303 | *p = '\0'; |
61a55e8b DE |
6304 | |
6305 | return string; | |
6306 | } | |
6307 | ||
47ac041c | 6308 | /* Emit a library call comparison between floating point X and Y. |
19047e4a EB |
6309 | COMPARISON is the operator to compare with (EQ, NE, GT, etc). |
6310 | Return the new operator to be used in the comparison sequence. | |
6311 | ||
47ac041c JJ |
6312 | TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode |
6313 | values as arguments instead of the TFmode registers themselves, | |
6314 | that's why we cannot call emit_float_lib_cmp. */ | |
19047e4a | 6315 | |
f90b7a5a | 6316 | rtx |
fc27d102 | 6317 | sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison) |
47ac041c | 6318 | { |
e77d72cb | 6319 | const char *qpfunc; |
390b17c2 | 6320 | rtx slot0, slot1, result, tem, tem2, libfunc; |
5c5c34a4 | 6321 | enum machine_mode mode; |
19047e4a | 6322 | enum rtx_code new_comparison; |
47ac041c JJ |
6323 | |
6324 | switch (comparison) | |
6325 | { | |
6326 | case EQ: | |
19047e4a | 6327 | qpfunc = (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq"); |
47ac041c JJ |
6328 | break; |
6329 | ||
6330 | case NE: | |
19047e4a | 6331 | qpfunc = (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne"); |
47ac041c JJ |
6332 | break; |
6333 | ||
6334 | case GT: | |
19047e4a | 6335 | qpfunc = (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt"); |
47ac041c JJ |
6336 | break; |
6337 | ||
6338 | case GE: | |
19047e4a | 6339 | qpfunc = (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge"); |
47ac041c JJ |
6340 | break; |
6341 | ||
6342 | case LT: | |
19047e4a | 6343 | qpfunc = (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt"); |
47ac041c JJ |
6344 | break; |
6345 | ||
6346 | case LE: | |
19047e4a | 6347 | qpfunc = (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle"); |
5c5c34a4 JJ |
6348 | break; |
6349 | ||
6350 | case ORDERED: | |
6351 | case UNORDERED: | |
6352 | case UNGT: | |
6353 | case UNLT: | |
6354 | case UNEQ: | |
6355 | case UNGE: | |
6356 | case UNLE: | |
6357 | case LTGT: | |
19047e4a | 6358 | qpfunc = (TARGET_ARCH64 ? "_Qp_cmp" : "_Q_cmp"); |
47ac041c JJ |
6359 | break; |
6360 | ||
6361 | default: | |
f5f7d171 | 6362 | gcc_unreachable (); |
47ac041c JJ |
6363 | } |
6364 | ||
5c5c34a4 | 6365 | if (TARGET_ARCH64) |
47ac041c | 6366 | { |
19047e4a EB |
6367 | if (MEM_P (x)) |
6368 | slot0 = x; | |
6369 | else | |
5c5c34a4 JJ |
6370 | { |
6371 | slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); | |
c5d74498 | 6372 | emit_move_insn (slot0, x); |
5c5c34a4 | 6373 | } |
5c5c34a4 | 6374 | |
19047e4a EB |
6375 | if (MEM_P (y)) |
6376 | slot1 = y; | |
6377 | else | |
5c5c34a4 JJ |
6378 | { |
6379 | slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); | |
c5d74498 | 6380 | emit_move_insn (slot1, y); |
5c5c34a4 | 6381 | } |
47ac041c | 6382 | |
390b17c2 RE |
6383 | libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc); |
6384 | emit_library_call (libfunc, LCT_NORMAL, | |
5c5c34a4 JJ |
6385 | DImode, 2, |
6386 | XEXP (slot0, 0), Pmode, | |
6387 | XEXP (slot1, 0), Pmode); | |
5c5c34a4 JJ |
6388 | mode = DImode; |
6389 | } | |
6390 | else | |
47ac041c | 6391 | { |
390b17c2 RE |
6392 | libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc); |
6393 | emit_library_call (libfunc, LCT_NORMAL, | |
5c5c34a4 JJ |
6394 | SImode, 2, |
6395 | x, TFmode, y, TFmode); | |
5c5c34a4 | 6396 | mode = SImode; |
47ac041c JJ |
6397 | } |
6398 | ||
47ac041c JJ |
6399 | |
6400 | /* Immediately move the result of the libcall into a pseudo | |
6401 | register so reload doesn't clobber the value if it needs | |
6402 | the return register for a spill reg. */ | |
5c5c34a4 | 6403 | result = gen_reg_rtx (mode); |
390b17c2 | 6404 | emit_move_insn (result, hard_libcall_value (mode, libfunc)); |
47ac041c | 6405 | |
5c5c34a4 JJ |
6406 | switch (comparison) |
6407 | { | |
6408 | default: | |
f90b7a5a | 6409 | return gen_rtx_NE (VOIDmode, result, const0_rtx); |
5c5c34a4 JJ |
6410 | case ORDERED: |
6411 | case UNORDERED: | |
19047e4a | 6412 | new_comparison = (comparison == UNORDERED ? EQ : NE); |
f90b7a5a | 6413 | return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, GEN_INT(3)); |
5c5c34a4 JJ |
6414 | case UNGT: |
6415 | case UNGE: | |
19047e4a | 6416 | new_comparison = (comparison == UNGT ? GT : NE); |
f90b7a5a | 6417 | return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, const1_rtx); |
5c5c34a4 | 6418 | case UNLE: |
f90b7a5a | 6419 | return gen_rtx_NE (VOIDmode, result, const2_rtx); |
5c5c34a4 JJ |
6420 | case UNLT: |
6421 | tem = gen_reg_rtx (mode); | |
6422 | if (TARGET_ARCH32) | |
6423 | emit_insn (gen_andsi3 (tem, result, const1_rtx)); | |
6424 | else | |
6425 | emit_insn (gen_anddi3 (tem, result, const1_rtx)); | |
f90b7a5a | 6426 | return gen_rtx_NE (VOIDmode, tem, const0_rtx); |
5c5c34a4 JJ |
6427 | case UNEQ: |
6428 | case LTGT: | |
6429 | tem = gen_reg_rtx (mode); | |
6430 | if (TARGET_ARCH32) | |
6431 | emit_insn (gen_addsi3 (tem, result, const1_rtx)); | |
6432 | else | |
6433 | emit_insn (gen_adddi3 (tem, result, const1_rtx)); | |
6434 | tem2 = gen_reg_rtx (mode); | |
6435 | if (TARGET_ARCH32) | |
6436 | emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); | |
6437 | else | |
6438 | emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); | |
19047e4a | 6439 | new_comparison = (comparison == UNEQ ? EQ : NE); |
f90b7a5a | 6440 | return gen_rtx_fmt_ee (new_comparison, VOIDmode, tem2, const0_rtx); |
5c5c34a4 | 6441 | } |
19047e4a | 6442 | |
f90b7a5a | 6443 | gcc_unreachable (); |
47ac041c | 6444 | } |
5c5c34a4 | 6445 | |
d88e57d1 RH |
6446 | /* Generate an unsigned DImode to FP conversion. This is the same code |
6447 | optabs would emit if we didn't have TFmode patterns. */ | |
6448 | ||
6449 | void | |
b178305d | 6450 | sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode) |
d88e57d1 RH |
6451 | { |
6452 | rtx neglab, donelab, i0, i1, f0, in, out; | |
d88e57d1 RH |
6453 | |
6454 | out = operands[0]; | |
6455 | in = force_reg (DImode, operands[1]); | |
d88e57d1 RH |
6456 | neglab = gen_label_rtx (); |
6457 | donelab = gen_label_rtx (); | |
6458 | i0 = gen_reg_rtx (DImode); | |
6459 | i1 = gen_reg_rtx (DImode); | |
6460 | f0 = gen_reg_rtx (mode); | |
6461 | ||
6462 | emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); | |
6463 | ||
6464 | emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in))); | |
6465 | emit_jump_insn (gen_jump (donelab)); | |
6466 | emit_barrier (); | |
6467 | ||
6468 | emit_label (neglab); | |
6469 | ||
6470 | emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); | |
6471 | emit_insn (gen_anddi3 (i1, in, const1_rtx)); | |
6472 | emit_insn (gen_iordi3 (i0, i0, i1)); | |
6473 | emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0))); | |
6474 | emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0))); | |
6475 | ||
6476 | emit_label (donelab); | |
6477 | } | |
6478 | ||
b178305d EB |
6479 | /* Generate an FP to unsigned DImode conversion. This is the same code |
6480 | optabs would emit if we didn't have TFmode patterns. */ | |
6481 | ||
6482 | void | |
6483 | sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode) | |
6484 | { | |
6485 | rtx neglab, donelab, i0, i1, f0, in, out, limit; | |
6486 | ||
6487 | out = operands[0]; | |
6488 | in = force_reg (mode, operands[1]); | |
6489 | neglab = gen_label_rtx (); | |
6490 | donelab = gen_label_rtx (); | |
6491 | i0 = gen_reg_rtx (DImode); | |
6492 | i1 = gen_reg_rtx (DImode); | |
6493 | limit = gen_reg_rtx (mode); | |
6494 | f0 = gen_reg_rtx (mode); | |
6495 | ||
6496 | emit_move_insn (limit, | |
6497 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
6498 | REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode)); | |
6499 | emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab); | |
6500 | ||
6501 | emit_insn (gen_rtx_SET (VOIDmode, | |
6502 | out, | |
6503 | gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in)))); | |
6504 | emit_jump_insn (gen_jump (donelab)); | |
6505 | emit_barrier (); | |
6506 | ||
6507 | emit_label (neglab); | |
6508 | ||
6509 | emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit))); | |
6510 | emit_insn (gen_rtx_SET (VOIDmode, | |
6511 | i0, | |
6512 | gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0)))); | |
6513 | emit_insn (gen_movdi (i1, const1_rtx)); | |
6514 | emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63))); | |
6515 | emit_insn (gen_xordi3 (out, i0, i1)); | |
6516 | ||
6517 | emit_label (donelab); | |
6518 | } | |
6519 | ||
61a55e8b DE |
6520 | /* Return the string to output a conditional branch to LABEL, testing |
6521 | register REG. LABEL is the operand number of the label; REG is the | |
6522 | operand number of the reg. OP is the conditional expression. The mode | |
6523 | of REG says what kind of comparison we made. | |
6524 | ||
1b3c2c2d EB |
6525 | DEST is the destination insn (i.e. the label), INSN is the source. |
6526 | ||
5e7a8ee0 | 6527 | REVERSED is nonzero if we should reverse the sense of the comparison. |
61a55e8b | 6528 | |
4e5b002b | 6529 | ANNUL is nonzero if we should generate an annulling branch. */ |
61a55e8b | 6530 | |
a6163c22 | 6531 | const char * |
fc27d102 | 6532 | output_v9branch (rtx op, rtx dest, int reg, int label, int reversed, |
4e5b002b | 6533 | int annul, rtx insn) |
61a55e8b | 6534 | { |
a6163c22 | 6535 | static char string[64]; |
61a55e8b DE |
6536 | enum rtx_code code = GET_CODE (op); |
6537 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
e0d80184 | 6538 | rtx note; |
0b82d204 JJ |
6539 | int far; |
6540 | char *p; | |
6541 | ||
6542 | /* branch on register are limited to +-128KB. If it is too far away, | |
6543 | change | |
4900aa61 | 6544 | |
0b82d204 | 6545 | brnz,pt %g1, .LC30 |
4900aa61 | 6546 | |
0b82d204 | 6547 | to |
4900aa61 | 6548 | |
0b82d204 | 6549 | brz,pn %g1, .+12 |
a6163c22 | 6550 | nop |
0b82d204 | 6551 | ba,pt %xcc, .LC30 |
4900aa61 | 6552 | |
0b82d204 | 6553 | and |
4900aa61 | 6554 | |
0b82d204 | 6555 | brgez,a,pn %o1, .LC29 |
4900aa61 | 6556 | |
0b82d204 | 6557 | to |
4900aa61 | 6558 | |
0b82d204 | 6559 | brlz,pt %o1, .+16 |
a6163c22 | 6560 | nop |
0b82d204 JJ |
6561 | ba,pt %xcc, .LC29 */ |
6562 | ||
6563 | far = get_attr_length (insn) >= 3; | |
61a55e8b DE |
6564 | |
6565 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
0b82d204 JJ |
6566 | if (reversed ^ far) |
6567 | code = reverse_condition (code); | |
61a55e8b DE |
6568 | |
6569 | /* Only 64 bit versions of these instructions exist. */ | |
f5f7d171 | 6570 | gcc_assert (mode == DImode); |
61a55e8b DE |
6571 | |
6572 | /* Start by writing the branch condition. */ | |
6573 | ||
6574 | switch (code) | |
6575 | { | |
6576 | case NE: | |
6577 | strcpy (string, "brnz"); | |
6578 | break; | |
6579 | ||
6580 | case EQ: | |
6581 | strcpy (string, "brz"); | |
6582 | break; | |
6583 | ||
6584 | case GE: | |
6585 | strcpy (string, "brgez"); | |
6586 | break; | |
6587 | ||
6588 | case LT: | |
6589 | strcpy (string, "brlz"); | |
6590 | break; | |
6591 | ||
6592 | case LE: | |
6593 | strcpy (string, "brlez"); | |
6594 | break; | |
6595 | ||
6596 | case GT: | |
6597 | strcpy (string, "brgz"); | |
6598 | break; | |
6599 | ||
6600 | default: | |
f5f7d171 | 6601 | gcc_unreachable (); |
61a55e8b DE |
6602 | } |
6603 | ||
0b82d204 JJ |
6604 | p = strchr (string, '\0'); |
6605 | ||
61a55e8b | 6606 | /* Now add the annulling, reg, label, and nop. */ |
0b82d204 | 6607 | if (annul && ! far) |
e0d80184 | 6608 | { |
0b82d204 JJ |
6609 | strcpy (p, ",a"); |
6610 | p += 2; | |
e0d80184 | 6611 | } |
61a55e8b | 6612 | |
4f31cce8 | 6613 | if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) |
e0d80184 | 6614 | { |
0b82d204 | 6615 | strcpy (p, |
4f31cce8 | 6616 | ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) |
0b82d204 JJ |
6617 | ? ",pt" : ",pn"); |
6618 | p += 3; | |
e0d80184 | 6619 | } |
61a55e8b | 6620 | |
0b82d204 JJ |
6621 | *p = p < string + 8 ? '\t' : ' '; |
6622 | p++; | |
6623 | *p++ = '%'; | |
6624 | *p++ = '0' + reg; | |
6625 | *p++ = ','; | |
6626 | *p++ = ' '; | |
6627 | if (far) | |
6628 | { | |
6629 | int veryfar = 1, delta; | |
6630 | ||
6631 | if (INSN_ADDRESSES_SET_P ()) | |
6632 | { | |
6633 | delta = (INSN_ADDRESSES (INSN_UID (dest)) | |
6634 | - INSN_ADDRESSES (INSN_UID (insn))); | |
6635 | /* Leave some instructions for "slop". */ | |
6636 | if (delta >= -260000 && delta < 260000) | |
6637 | veryfar = 0; | |
6638 | } | |
6639 | ||
a6163c22 | 6640 | strcpy (p, ".+12\n\t nop\n\t"); |
4e5b002b EB |
6641 | /* Skip the next insn if requested or |
6642 | if we know that it will be a nop. */ | |
6643 | if (annul || ! final_sequence) | |
0b82d204 | 6644 | p[3] = '6'; |
a6163c22 | 6645 | p += 12; |
0b82d204 JJ |
6646 | if (veryfar) |
6647 | { | |
6648 | strcpy (p, "b\t"); | |
6649 | p += 2; | |
6650 | } | |
6651 | else | |
6652 | { | |
6653 | strcpy (p, "ba,pt\t%%xcc, "); | |
6654 | p += 13; | |
6655 | } | |
6656 | } | |
6657 | *p++ = '%'; | |
6658 | *p++ = 'l'; | |
6659 | *p++ = '0' + label; | |
4e5b002b EB |
6660 | *p++ = '%'; |
6661 | *p++ = '#'; | |
0b82d204 | 6662 | *p = '\0'; |
ab835497 | 6663 | |
ab835497 RK |
6664 | return string; |
6665 | } | |
6666 | ||
e48addee JJ |
6667 | /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. |
6668 | Such instructions cannot be used in the delay slot of return insn on v9. | |
6669 | If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. | |
6670 | */ | |
284d86e9 | 6671 | |
e48addee | 6672 | static int |
fc27d102 | 6673 | epilogue_renumber (register rtx *where, int test) |
284d86e9 | 6674 | { |
e48addee JJ |
6675 | register const char *fmt; |
6676 | register int i; | |
6677 | register enum rtx_code code; | |
6678 | ||
6679 | if (*where == 0) | |
6680 | return 0; | |
6681 | ||
6682 | code = GET_CODE (*where); | |
284d86e9 JC |
6683 | |
6684 | switch (code) | |
6685 | { | |
284d86e9 | 6686 | case REG: |
e48addee JJ |
6687 | if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ |
6688 | return 1; | |
6689 | if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) | |
f1c25d3b | 6690 | *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); |
e48addee JJ |
6691 | case SCRATCH: |
6692 | case CC0: | |
6693 | case PC: | |
284d86e9 JC |
6694 | case CONST_INT: |
6695 | case CONST_DOUBLE: | |
e48addee | 6696 | return 0; |
76a7c776 | 6697 | |
09ebda1b SC |
6698 | /* Do not replace the frame pointer with the stack pointer because |
6699 | it can cause the delayed instruction to load below the stack. | |
6700 | This occurs when instructions like: | |
6701 | ||
6702 | (set (reg/i:SI 24 %i0) | |
6703 | (mem/f:SI (plus:SI (reg/f:SI 30 %fp) | |
6704 | (const_int -20 [0xffffffec])) 0)) | |
6705 | ||
6706 | are in the return delayed slot. */ | |
6707 | case PLUS: | |
6708 | if (GET_CODE (XEXP (*where, 0)) == REG | |
563c12b0 | 6709 | && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM |
09ebda1b SC |
6710 | && (GET_CODE (XEXP (*where, 1)) != CONST_INT |
6711 | || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS)) | |
6712 | return 1; | |
6713 | break; | |
6714 | ||
6715 | case MEM: | |
6716 | if (SPARC_STACK_BIAS | |
6717 | && GET_CODE (XEXP (*where, 0)) == REG | |
563c12b0 | 6718 | && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM) |
09ebda1b SC |
6719 | return 1; |
6720 | break; | |
6721 | ||
76a7c776 DM |
6722 | default: |
6723 | break; | |
e48addee | 6724 | } |
284d86e9 | 6725 | |
e48addee | 6726 | fmt = GET_RTX_FORMAT (code); |
284d86e9 | 6727 | |
e48addee JJ |
6728 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
6729 | { | |
6730 | if (fmt[i] == 'E') | |
6731 | { | |
6732 | register int j; | |
6733 | for (j = XVECLEN (*where, i) - 1; j >= 0; j--) | |
6734 | if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) | |
6735 | return 1; | |
6736 | } | |
6737 | else if (fmt[i] == 'e' | |
6738 | && epilogue_renumber (&(XEXP (*where, i)), test)) | |
6739 | return 1; | |
284d86e9 | 6740 | } |
e48addee | 6741 | return 0; |
284d86e9 | 6742 | } |
ab835497 RK |
6743 | \f |
6744 | /* Leaf functions and non-leaf functions have different needs. */ | |
6745 | ||
8b60264b | 6746 | static const int |
ab835497 RK |
6747 | reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; |
6748 | ||
8b60264b | 6749 | static const int |
ab835497 RK |
6750 | reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; |
6751 | ||
8b60264b | 6752 | static const int *const reg_alloc_orders[] = { |
ab835497 RK |
6753 | reg_leaf_alloc_order, |
6754 | reg_nonleaf_alloc_order}; | |
6755 | ||
6756 | void | |
fc27d102 | 6757 | order_regs_for_local_alloc (void) |
ab835497 RK |
6758 | { |
6759 | static int last_order_nonleaf = 1; | |
6760 | ||
6fb5fa3c | 6761 | if (df_regs_ever_live_p (15) != last_order_nonleaf) |
ab835497 RK |
6762 | { |
6763 | last_order_nonleaf = !last_order_nonleaf; | |
2e09e75a | 6764 | memcpy ((char *) reg_alloc_order, |
8b60264b | 6765 | (const char *) reg_alloc_orders[last_order_nonleaf], |
2e09e75a | 6766 | FIRST_PSEUDO_REGISTER * sizeof (int)); |
ab835497 RK |
6767 | } |
6768 | } | |
6769 | \f | |
e0d80184 DM |
6770 | /* Return 1 if REG and MEM are legitimate enough to allow the various |
6771 | mem<-->reg splits to be run. */ | |
6772 | ||
6773 | int | |
fc27d102 | 6774 | sparc_splitdi_legitimate (rtx reg, rtx mem) |
e0d80184 | 6775 | { |
e0d80184 | 6776 | /* Punt if we are here by mistake. */ |
f5f7d171 | 6777 | gcc_assert (reload_completed); |
e0d80184 DM |
6778 | |
6779 | /* We must have an offsettable memory reference. */ | |
6780 | if (! offsettable_memref_p (mem)) | |
6781 | return 0; | |
6782 | ||
6783 | /* If we have legitimate args for ldd/std, we do not want | |
6784 | the split to happen. */ | |
6785 | if ((REGNO (reg) % 2) == 0 | |
6786 | && mem_min_alignment (mem, 8)) | |
6787 | return 0; | |
6788 | ||
6789 | /* Success. */ | |
6790 | return 1; | |
6791 | } | |
6792 | ||
e61c29e9 | 6793 | /* Return 1 if x and y are some kind of REG and they refer to |
fae778eb | 6794 | different hard registers. This test is guaranteed to be |
e61c29e9 DM |
6795 | run after reload. */ |
6796 | ||
6797 | int | |
fc27d102 | 6798 | sparc_absnegfloat_split_legitimate (rtx x, rtx y) |
e61c29e9 | 6799 | { |
e61c29e9 DM |
6800 | if (GET_CODE (x) != REG) |
6801 | return 0; | |
e61c29e9 DM |
6802 | if (GET_CODE (y) != REG) |
6803 | return 0; | |
6804 | if (REGNO (x) == REGNO (y)) | |
6805 | return 0; | |
6806 | return 1; | |
6807 | } | |
6808 | ||
35016322 | 6809 | /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. |
4900aa61 | 6810 | This makes them candidates for using ldd and std insns. |
35016322 | 6811 | |
bfd6bc60 | 6812 | Note reg1 and reg2 *must* be hard registers. */ |
35016322 JW |
6813 | |
6814 | int | |
fc27d102 | 6815 | registers_ok_for_ldd_peep (rtx reg1, rtx reg2) |
35016322 | 6816 | { |
35016322 | 6817 | /* We might have been passed a SUBREG. */ |
4900aa61 | 6818 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) |
35016322 JW |
6819 | return 0; |
6820 | ||
35016322 JW |
6821 | if (REGNO (reg1) % 2 != 0) |
6822 | return 0; | |
6823 | ||
4900aa61 EB |
6824 | /* Integer ldd is deprecated in SPARC V9 */ |
6825 | if (TARGET_V9 && REGNO (reg1) < 32) | |
6826 | return 0; | |
bfd6bc60 | 6827 | |
35016322 | 6828 | return (REGNO (reg1) == REGNO (reg2) - 1); |
35016322 JW |
6829 | } |
6830 | ||
2aad5d68 | 6831 | /* Return 1 if the addresses in mem1 and mem2 are suitable for use in |
303f8933 | 6832 | an ldd or std insn. |
4900aa61 | 6833 | |
2aad5d68 DN |
6834 | This can only happen when addr1 and addr2, the addresses in mem1 |
6835 | and mem2, are consecutive memory locations (addr1 + 4 == addr2). | |
303f8933 DN |
6836 | addr1 must also be aligned on a 64-bit boundary. |
6837 | ||
6838 | Also iff dependent_reg_rtx is not null it should not be used to | |
6839 | compute the address for mem1, i.e. we cannot optimize a sequence | |
6840 | like: | |
6841 | ld [%o0], %o0 | |
6842 | ld [%o0 + 4], %o1 | |
6843 | to | |
bcdd764b | 6844 | ldd [%o0], %o0 |
0acf409f DM |
6845 | nor: |
6846 | ld [%g3 + 4], %g3 | |
6847 | ld [%g3], %g2 | |
6848 | to | |
6849 | ldd [%g3], %g2 | |
6850 | ||
6851 | But, note that the transformation from: | |
6852 | ld [%g2 + 4], %g3 | |
6853 | ld [%g2], %g2 | |
6854 | to | |
6855 | ldd [%g2], %g2 | |
6856 | is perfectly fine. Thus, the peephole2 patterns always pass us | |
6857 | the destination register of the first load, never the second one. | |
6858 | ||
303f8933 DN |
6859 | For stores we don't have a similar problem, so dependent_reg_rtx is |
6860 | NULL_RTX. */ | |
35016322 JW |
6861 | |
6862 | int | |
fc27d102 | 6863 | mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx) |
35016322 | 6864 | { |
2aad5d68 | 6865 | rtx addr1, addr2; |
0d587737 | 6866 | unsigned int reg1; |
6a151f87 | 6867 | HOST_WIDE_INT offset1; |
35016322 | 6868 | |
303f8933 DN |
6869 | /* The mems cannot be volatile. */ |
6870 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
6871 | return 0; | |
2aad5d68 | 6872 | |
303f8933 | 6873 | /* MEM1 should be aligned on a 64-bit boundary. */ |
2aad5d68 DN |
6874 | if (MEM_ALIGN (mem1) < 64) |
6875 | return 0; | |
4900aa61 | 6876 | |
303f8933 DN |
6877 | addr1 = XEXP (mem1, 0); |
6878 | addr2 = XEXP (mem2, 0); | |
4900aa61 | 6879 | |
35016322 JW |
6880 | /* Extract a register number and offset (if used) from the first addr. */ |
6881 | if (GET_CODE (addr1) == PLUS) | |
6882 | { | |
6883 | /* If not a REG, return zero. */ | |
6884 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
6885 | return 0; | |
6886 | else | |
6887 | { | |
6888 | reg1 = REGNO (XEXP (addr1, 0)); | |
6889 | /* The offset must be constant! */ | |
6890 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
6891 | return 0; | |
6892 | offset1 = INTVAL (XEXP (addr1, 1)); | |
6893 | } | |
6894 | } | |
6895 | else if (GET_CODE (addr1) != REG) | |
6896 | return 0; | |
6897 | else | |
6898 | { | |
6899 | reg1 = REGNO (addr1); | |
6900 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
6901 | offset1 = 0; | |
6902 | } | |
6903 | ||
6904 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
6905 | if (GET_CODE (addr2) != PLUS) | |
6906 | return 0; | |
6907 | ||
6908 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
6909 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
6910 | return 0; | |
6911 | ||
35016322 JW |
6912 | if (reg1 != REGNO (XEXP (addr2, 0))) |
6913 | return 0; | |
6914 | ||
303f8933 DN |
6915 | if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx)) |
6916 | return 0; | |
4900aa61 EB |
6917 | |
6918 | /* The first offset must be evenly divisible by 8 to ensure the | |
35016322 JW |
6919 | address is 64 bit aligned. */ |
6920 | if (offset1 % 8 != 0) | |
6921 | return 0; | |
6922 | ||
6923 | /* The offset for the second addr must be 4 more than the first addr. */ | |
6924 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) | |
6925 | return 0; | |
6926 | ||
6927 | /* All the tests passed. addr1 and addr2 are valid for ldd and std | |
6928 | instructions. */ | |
6929 | return 1; | |
6930 | } | |
7c56249d | 6931 | |
157891a3 EB |
6932 | /* Return 1 if reg is a pseudo, or is the first register in |
6933 | a hard register pair. This makes it suitable for use in | |
7c56249d JL |
6934 | ldd and std insns. */ |
6935 | ||
6936 | int | |
fc27d102 | 6937 | register_ok_for_ldd (rtx reg) |
7c56249d | 6938 | { |
7c56249d | 6939 | /* We might have been passed a SUBREG. */ |
157891a3 | 6940 | if (!REG_P (reg)) |
7c56249d JL |
6941 | return 0; |
6942 | ||
6943 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
6944 | return (REGNO (reg) % 2 == 0); | |
157891a3 EB |
6945 | |
6946 | return 1; | |
6947 | } | |
6948 | ||
6949 | /* Return 1 if OP is a memory whose address is known to be | |
6950 | aligned to 8-byte boundary, or a pseudo during reload. | |
6951 | This makes it suitable for use in ldd and std insns. */ | |
6952 | ||
6953 | int | |
6954 | memory_ok_for_ldd (rtx op) | |
6955 | { | |
6956 | if (MEM_P (op)) | |
6957 | { | |
6958 | /* In 64-bit mode, we assume that the address is word-aligned. */ | |
6959 | if (TARGET_ARCH32 && !mem_min_alignment (op, 8)) | |
6960 | return 0; | |
6961 | ||
6962 | if ((reload_in_progress || reload_completed) | |
6963 | && !strict_memory_address_p (Pmode, XEXP (op, 0))) | |
6964 | return 0; | |
6965 | } | |
6966 | else if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
6967 | { | |
6968 | if (!(reload_in_progress && reg_renumber [REGNO (op)] < 0)) | |
6969 | return 0; | |
6970 | } | |
6971 | else | |
6972 | return 0; | |
6973 | ||
6974 | return 1; | |
7c56249d | 6975 | } |
ab835497 | 6976 | \f |
ab835497 RK |
6977 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
6978 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
6979 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
6980 | ||
6981 | void | |
fc27d102 | 6982 | print_operand (FILE *file, rtx x, int code) |
ab835497 RK |
6983 | { |
6984 | switch (code) | |
6985 | { | |
6986 | case '#': | |
4e5b002b EB |
6987 | /* Output an insn in a delay slot. */ |
6988 | if (final_sequence) | |
6989 | sparc_indent_opcode = 1; | |
6990 | else | |
e0d80184 | 6991 | fputs ("\n\t nop", file); |
ab835497 RK |
6992 | return; |
6993 | case '*': | |
c6ce0969 | 6994 | /* Output an annul flag if there's nothing for the delay slot and we |
4e5b002b EB |
6995 | are optimizing. This is always used with '(' below. |
6996 | Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; | |
6997 | this is a dbx bug. So, we only do this when optimizing. | |
6998 | On UltraSPARC, a branch in a delay slot causes a pipeline flush. | |
bfd6bc60 | 6999 | Always emit a nop in case the next instruction is a branch. */ |
4e5b002b | 7000 | if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
c6ce0969 JW |
7001 | fputs (",a", file); |
7002 | return; | |
7003 | case '(': | |
7004 | /* Output a 'nop' if there's nothing for the delay slot and we are | |
7005 | not optimizing. This is always used with '*' above. */ | |
4e5b002b | 7006 | if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
e0d80184 | 7007 | fputs ("\n\t nop", file); |
4e5b002b EB |
7008 | else if (final_sequence) |
7009 | sparc_indent_opcode = 1; | |
7010 | return; | |
7011 | case ')': | |
7012 | /* Output the right displacement from the saved PC on function return. | |
7013 | The caller may have placed an "unimp" insn immediately after the call | |
7014 | so we have to account for it. This insn is used in the 32-bit ABI | |
66695571 | 7015 | when calling a function that returns a non zero-sized structure. The |
4e5b002b | 7016 | 64-bit ABI doesn't have it. Be careful to have this test be the same |
66695571 EB |
7017 | as that for the call. The exception is when sparc_std_struct_return |
7018 | is enabled, the psABI is followed exactly and the adjustment is made | |
7019 | by the code in sparc_struct_value_rtx. The call emitted is the same | |
7020 | when sparc_std_struct_return is enabled. */ | |
7021 | if (!TARGET_ARCH64 | |
e3b5732b | 7022 | && cfun->returns_struct |
66695571 EB |
7023 | && !sparc_std_struct_return |
7024 | && DECL_SIZE (DECL_RESULT (current_function_decl)) | |
7025 | && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) | |
7026 | == INTEGER_CST | |
7027 | && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl)))) | |
4e5b002b EB |
7028 | fputs ("12", file); |
7029 | else | |
7030 | fputc ('8', file); | |
ab835497 | 7031 | return; |
61a55e8b | 7032 | case '_': |
a0a301fc DE |
7033 | /* Output the Embedded Medium/Anywhere code model base register. */ |
7034 | fputs (EMBMEDANY_BASE_REG, file); | |
61a55e8b | 7035 | return; |
5751a10b JJ |
7036 | case '&': |
7037 | /* Print some local dynamic TLS name. */ | |
7038 | assemble_name (file, get_some_local_dynamic_name ()); | |
7039 | return; | |
4e5b002b | 7040 | |
ab835497 RK |
7041 | case 'Y': |
7042 | /* Adjust the operand to take into account a RESTORE operation. */ | |
bfd6bc60 JC |
7043 | if (GET_CODE (x) == CONST_INT) |
7044 | break; | |
7045 | else if (GET_CODE (x) != REG) | |
c725bd79 | 7046 | output_operand_lossage ("invalid %%Y operand"); |
b3b1e8bd | 7047 | else if (REGNO (x) < 8) |
ab835497 RK |
7048 | fputs (reg_names[REGNO (x)], file); |
7049 | else if (REGNO (x) >= 24 && REGNO (x) < 32) | |
7050 | fputs (reg_names[REGNO (x)-16], file); | |
7051 | else | |
c725bd79 | 7052 | output_operand_lossage ("invalid %%Y operand"); |
ab835497 | 7053 | return; |
0f39a9aa DE |
7054 | case 'L': |
7055 | /* Print out the low order register name of a register pair. */ | |
7056 | if (WORDS_BIG_ENDIAN) | |
7057 | fputs (reg_names[REGNO (x)+1], file); | |
7058 | else | |
7059 | fputs (reg_names[REGNO (x)], file); | |
7060 | return; | |
7061 | case 'H': | |
7062 | /* Print out the high order register name of a register pair. */ | |
7063 | if (WORDS_BIG_ENDIAN) | |
7064 | fputs (reg_names[REGNO (x)], file); | |
7065 | else | |
7066 | fputs (reg_names[REGNO (x)+1], file); | |
7067 | return; | |
ab835497 | 7068 | case 'R': |
795068a4 | 7069 | /* Print out the second register name of a register pair or quad. |
ab835497 RK |
7070 | I.e., R (%o0) => %o1. */ |
7071 | fputs (reg_names[REGNO (x)+1], file); | |
7072 | return; | |
795068a4 JW |
7073 | case 'S': |
7074 | /* Print out the third register name of a register quad. | |
7075 | I.e., S (%o0) => %o2. */ | |
7076 | fputs (reg_names[REGNO (x)+2], file); | |
7077 | return; | |
7078 | case 'T': | |
7079 | /* Print out the fourth register name of a register quad. | |
7080 | I.e., T (%o0) => %o3. */ | |
7081 | fputs (reg_names[REGNO (x)+3], file); | |
7082 | return; | |
304b7a23 DE |
7083 | case 'x': |
7084 | /* Print a condition code register. */ | |
7085 | if (REGNO (x) == SPARC_ICC_REG) | |
7086 | { | |
7087 | /* We don't handle CC[X]_NOOVmode because they're not supposed | |
7088 | to occur here. */ | |
7089 | if (GET_MODE (x) == CCmode) | |
7090 | fputs ("%icc", file); | |
7091 | else if (GET_MODE (x) == CCXmode) | |
7092 | fputs ("%xcc", file); | |
7093 | else | |
f5f7d171 | 7094 | gcc_unreachable (); |
304b7a23 DE |
7095 | } |
7096 | else | |
7097 | /* %fccN register */ | |
7098 | fputs (reg_names[REGNO (x)], file); | |
7099 | return; | |
ab835497 RK |
7100 | case 'm': |
7101 | /* Print the operand's address only. */ | |
7102 | output_address (XEXP (x, 0)); | |
7103 | return; | |
7104 | case 'r': | |
7105 | /* In this case we need a register. Use %g0 if the | |
77a02b01 | 7106 | operand is const0_rtx. */ |
76052e74 RS |
7107 | if (x == const0_rtx |
7108 | || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) | |
ab835497 RK |
7109 | { |
7110 | fputs ("%g0", file); | |
7111 | return; | |
7112 | } | |
7113 | else | |
7114 | break; | |
7115 | ||
61a55e8b | 7116 | case 'A': |
ab835497 RK |
7117 | switch (GET_CODE (x)) |
7118 | { | |
7119 | case IOR: fputs ("or", file); break; | |
7120 | case AND: fputs ("and", file); break; | |
7121 | case XOR: fputs ("xor", file); break; | |
c725bd79 | 7122 | default: output_operand_lossage ("invalid %%A operand"); |
ab835497 RK |
7123 | } |
7124 | return; | |
7125 | ||
7126 | case 'B': | |
7127 | switch (GET_CODE (x)) | |
7128 | { | |
7129 | case IOR: fputs ("orn", file); break; | |
7130 | case AND: fputs ("andn", file); break; | |
7131 | case XOR: fputs ("xnor", file); break; | |
c725bd79 | 7132 | default: output_operand_lossage ("invalid %%B operand"); |
ab835497 RK |
7133 | } |
7134 | return; | |
7135 | ||
304b7a23 DE |
7136 | /* These are used by the conditional move instructions. */ |
7137 | case 'c' : | |
61a55e8b | 7138 | case 'C': |
304b7a23 | 7139 | { |
5c5c34a4 JJ |
7140 | enum rtx_code rc = GET_CODE (x); |
7141 | ||
7142 | if (code == 'c') | |
7143 | { | |
7144 | enum machine_mode mode = GET_MODE (XEXP (x, 0)); | |
7145 | if (mode == CCFPmode || mode == CCFPEmode) | |
7146 | rc = reverse_condition_maybe_unordered (GET_CODE (x)); | |
7147 | else | |
7148 | rc = reverse_condition (GET_CODE (x)); | |
7149 | } | |
304b7a23 DE |
7150 | switch (rc) |
7151 | { | |
7152 | case NE: fputs ("ne", file); break; | |
7153 | case EQ: fputs ("e", file); break; | |
7154 | case GE: fputs ("ge", file); break; | |
7155 | case GT: fputs ("g", file); break; | |
7156 | case LE: fputs ("le", file); break; | |
7157 | case LT: fputs ("l", file); break; | |
7158 | case GEU: fputs ("geu", file); break; | |
7159 | case GTU: fputs ("gu", file); break; | |
7160 | case LEU: fputs ("leu", file); break; | |
7161 | case LTU: fputs ("lu", file); break; | |
5c5c34a4 JJ |
7162 | case LTGT: fputs ("lg", file); break; |
7163 | case UNORDERED: fputs ("u", file); break; | |
7164 | case ORDERED: fputs ("o", file); break; | |
7165 | case UNLT: fputs ("ul", file); break; | |
7166 | case UNLE: fputs ("ule", file); break; | |
7167 | case UNGT: fputs ("ug", file); break; | |
7168 | case UNGE: fputs ("uge", file); break; | |
7169 | case UNEQ: fputs ("ue", file); break; | |
304b7a23 | 7170 | default: output_operand_lossage (code == 'c' |
c725bd79 NB |
7171 | ? "invalid %%c operand" |
7172 | : "invalid %%C operand"); | |
304b7a23 DE |
7173 | } |
7174 | return; | |
7175 | } | |
7176 | ||
7177 | /* These are used by the movr instruction pattern. */ | |
7178 | case 'd': | |
61a55e8b | 7179 | case 'D': |
304b7a23 DE |
7180 | { |
7181 | enum rtx_code rc = (code == 'd' | |
7182 | ? reverse_condition (GET_CODE (x)) | |
7183 | : GET_CODE (x)); | |
7184 | switch (rc) | |
7185 | { | |
7186 | case NE: fputs ("ne", file); break; | |
7187 | case EQ: fputs ("e", file); break; | |
7188 | case GE: fputs ("gez", file); break; | |
7189 | case LT: fputs ("lz", file); break; | |
7190 | case LE: fputs ("lez", file); break; | |
7191 | case GT: fputs ("gz", file); break; | |
7192 | default: output_operand_lossage (code == 'd' | |
c725bd79 NB |
7193 | ? "invalid %%d operand" |
7194 | : "invalid %%D operand"); | |
304b7a23 DE |
7195 | } |
7196 | return; | |
7197 | } | |
61a55e8b | 7198 | |
ab835497 RK |
7199 | case 'b': |
7200 | { | |
7201 | /* Print a sign-extended character. */ | |
9e0625a3 | 7202 | int i = trunc_int_for_mode (INTVAL (x), QImode); |
ab835497 RK |
7203 | fprintf (file, "%d", i); |
7204 | return; | |
7205 | } | |
7206 | ||
d2889939 RK |
7207 | case 'f': |
7208 | /* Operand must be a MEM; write its address. */ | |
7209 | if (GET_CODE (x) != MEM) | |
c725bd79 | 7210 | output_operand_lossage ("invalid %%f operand"); |
d2889939 RK |
7211 | output_address (XEXP (x, 0)); |
7212 | return; | |
7213 | ||
8707fe93 RH |
7214 | case 's': |
7215 | { | |
7216 | /* Print a sign-extended 32-bit value. */ | |
7217 | HOST_WIDE_INT i; | |
7218 | if (GET_CODE(x) == CONST_INT) | |
7219 | i = INTVAL (x); | |
7220 | else if (GET_CODE(x) == CONST_DOUBLE) | |
7221 | i = CONST_DOUBLE_LOW (x); | |
7222 | else | |
ffa916ba KG |
7223 | { |
7224 | output_operand_lossage ("invalid %%s operand"); | |
7225 | return; | |
7226 | } | |
8707fe93 RH |
7227 | i = trunc_int_for_mode (i, SImode); |
7228 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, i); | |
7229 | return; | |
7230 | } | |
7231 | ||
ab835497 RK |
7232 | case 0: |
7233 | /* Do nothing special. */ | |
7234 | break; | |
7235 | ||
7236 | default: | |
7237 | /* Undocumented flag. */ | |
415f583e | 7238 | output_operand_lossage ("invalid operand output code"); |
ab835497 RK |
7239 | } |
7240 | ||
7241 | if (GET_CODE (x) == REG) | |
7242 | fputs (reg_names[REGNO (x)], file); | |
7243 | else if (GET_CODE (x) == MEM) | |
7244 | { | |
7245 | fputc ('[', file); | |
ab835497 | 7246 | /* Poor Sun assembler doesn't understand absolute addressing. */ |
e6c1be7e | 7247 | if (CONSTANT_P (XEXP (x, 0))) |
ab835497 RK |
7248 | fputs ("%g0+", file); |
7249 | output_address (XEXP (x, 0)); | |
7250 | fputc (']', file); | |
7251 | } | |
7252 | else if (GET_CODE (x) == HIGH) | |
7253 | { | |
7254 | fputs ("%hi(", file); | |
7255 | output_addr_const (file, XEXP (x, 0)); | |
7256 | fputc (')', file); | |
7257 | } | |
7258 | else if (GET_CODE (x) == LO_SUM) | |
7259 | { | |
7260 | print_operand (file, XEXP (x, 0), 0); | |
e0d80184 DM |
7261 | if (TARGET_CM_MEDMID) |
7262 | fputs ("+%l44(", file); | |
7263 | else | |
7264 | fputs ("+%lo(", file); | |
ab835497 RK |
7265 | output_addr_const (file, XEXP (x, 1)); |
7266 | fputc (')', file); | |
7267 | } | |
e601abce JW |
7268 | else if (GET_CODE (x) == CONST_DOUBLE |
7269 | && (GET_MODE (x) == VOIDmode | |
7270 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) | |
ab835497 RK |
7271 | { |
7272 | if (CONST_DOUBLE_HIGH (x) == 0) | |
0d9484c5 | 7273 | fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x)); |
ab835497 RK |
7274 | else if (CONST_DOUBLE_HIGH (x) == -1 |
7275 | && CONST_DOUBLE_LOW (x) < 0) | |
0d9484c5 | 7276 | fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x)); |
ab835497 | 7277 | else |
e601abce | 7278 | output_operand_lossage ("long long constant not a valid immediate operand"); |
ab835497 | 7279 | } |
e601abce JW |
7280 | else if (GET_CODE (x) == CONST_DOUBLE) |
7281 | output_operand_lossage ("floating point constant not a valid immediate operand"); | |
ab835497 RK |
7282 | else { output_addr_const (file, x); } |
7283 | } | |
7284 | \f | |
301d03af RS |
7285 | /* Target hook for assembling integer objects. The sparc version has |
7286 | special handling for aligned DI-mode objects. */ | |
ab835497 | 7287 | |
301d03af | 7288 | static bool |
fc27d102 | 7289 | sparc_assemble_integer (rtx x, unsigned int size, int aligned_p) |
ab835497 | 7290 | { |
301d03af RS |
7291 | /* ??? We only output .xword's for symbols and only then in environments |
7292 | where the assembler can handle them. */ | |
7293 | if (aligned_p && size == 8 | |
7294 | && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE)) | |
ab835497 | 7295 | { |
301d03af | 7296 | if (TARGET_V9) |
61a55e8b | 7297 | { |
301d03af RS |
7298 | assemble_integer_with_op ("\t.xword\t", x); |
7299 | return true; | |
61a55e8b DE |
7300 | } |
7301 | else | |
7302 | { | |
301d03af RS |
7303 | assemble_aligned_integer (4, const0_rtx); |
7304 | assemble_aligned_integer (4, x); | |
7305 | return true; | |
61a55e8b | 7306 | } |
ab835497 | 7307 | } |
301d03af | 7308 | return default_assemble_integer (x, size, aligned_p); |
ab835497 | 7309 | } |
210aa14a | 7310 | \f |
b0468b84 RK |
7311 | /* Return the value of a code used in the .proc pseudo-op that says |
7312 | what kind of result this function returns. For non-C types, we pick | |
7313 | the closest C type. */ | |
7314 | ||
77a02b01 JW |
7315 | #ifndef SHORT_TYPE_SIZE |
7316 | #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) | |
7317 | #endif | |
7318 | ||
7319 | #ifndef INT_TYPE_SIZE | |
7320 | #define INT_TYPE_SIZE BITS_PER_WORD | |
7321 | #endif | |
7322 | ||
7323 | #ifndef LONG_TYPE_SIZE | |
7324 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
7325 | #endif | |
7326 | ||
7327 | #ifndef LONG_LONG_TYPE_SIZE | |
7328 | #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) | |
7329 | #endif | |
7330 | ||
7331 | #ifndef FLOAT_TYPE_SIZE | |
7332 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
7333 | #endif | |
7334 | ||
7335 | #ifndef DOUBLE_TYPE_SIZE | |
7336 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
7337 | #endif | |
7338 | ||
7339 | #ifndef LONG_DOUBLE_TYPE_SIZE | |
7340 | #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
7341 | #endif | |
210aa14a RS |
7342 | |
7343 | unsigned long | |
fc27d102 | 7344 | sparc_type_code (register tree type) |
210aa14a RS |
7345 | { |
7346 | register unsigned long qualifiers = 0; | |
e5e809f4 | 7347 | register unsigned shift; |
210aa14a | 7348 | |
abc95ed3 | 7349 | /* Only the first 30 bits of the qualifier are valid. We must refrain from |
aee2c3c5 JW |
7350 | setting more, since some assemblers will give an error for this. Also, |
7351 | we must be careful to avoid shifts of 32 bits or more to avoid getting | |
7352 | unpredictable results. */ | |
7353 | ||
e5e809f4 | 7354 | for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) |
210aa14a RS |
7355 | { |
7356 | switch (TREE_CODE (type)) | |
7357 | { | |
7358 | case ERROR_MARK: | |
7359 | return qualifiers; | |
4900aa61 | 7360 | |
210aa14a | 7361 | case ARRAY_TYPE: |
e5e809f4 | 7362 | qualifiers |= (3 << shift); |
210aa14a RS |
7363 | break; |
7364 | ||
7365 | case FUNCTION_TYPE: | |
7366 | case METHOD_TYPE: | |
e5e809f4 | 7367 | qualifiers |= (2 << shift); |
210aa14a RS |
7368 | break; |
7369 | ||
7370 | case POINTER_TYPE: | |
7371 | case REFERENCE_TYPE: | |
7372 | case OFFSET_TYPE: | |
e5e809f4 | 7373 | qualifiers |= (1 << shift); |
210aa14a | 7374 | break; |
ab835497 | 7375 | |
210aa14a RS |
7376 | case RECORD_TYPE: |
7377 | return (qualifiers | 8); | |
7378 | ||
7379 | case UNION_TYPE: | |
b0468b84 | 7380 | case QUAL_UNION_TYPE: |
210aa14a RS |
7381 | return (qualifiers | 9); |
7382 | ||
7383 | case ENUMERAL_TYPE: | |
7384 | return (qualifiers | 10); | |
7385 | ||
7386 | case VOID_TYPE: | |
7387 | return (qualifiers | 16); | |
7388 | ||
7389 | case INTEGER_TYPE: | |
654209e6 JW |
7390 | /* If this is a range type, consider it to be the underlying |
7391 | type. */ | |
7392 | if (TREE_TYPE (type) != 0) | |
e5e809f4 | 7393 | break; |
654209e6 | 7394 | |
77a02b01 | 7395 | /* Carefully distinguish all the standard types of C, |
b0468b84 | 7396 | without messing up if the language is not C. We do this by |
8df83eae | 7397 | testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to |
b0468b84 RK |
7398 | look at both the names and the above fields, but that's redundant. |
7399 | Any type whose size is between two C types will be considered | |
7400 | to be the wider of the two types. Also, we do not have a | |
7401 | special code to use for "long long", so anything wider than | |
7402 | long is treated the same. Note that we can't distinguish | |
7403 | between "int" and "long" in this code if they are the same | |
7404 | size, but that's fine, since neither can the assembler. */ | |
7405 | ||
7406 | if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) | |
8df83eae | 7407 | return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2)); |
4900aa61 | 7408 | |
b0468b84 | 7409 | else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) |
8df83eae | 7410 | return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3)); |
4900aa61 | 7411 | |
b0468b84 | 7412 | else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) |
8df83eae | 7413 | return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4)); |
4900aa61 | 7414 | |
b0468b84 | 7415 | else |
8df83eae | 7416 | return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5)); |
4900aa61 | 7417 | |
210aa14a | 7418 | case REAL_TYPE: |
e5e809f4 JL |
7419 | /* If this is a range type, consider it to be the underlying |
7420 | type. */ | |
7421 | if (TREE_TYPE (type) != 0) | |
7422 | break; | |
7423 | ||
77a02b01 JW |
7424 | /* Carefully distinguish all the standard types of C, |
7425 | without messing up if the language is not C. */ | |
b0468b84 | 7426 | |
77a02b01 | 7427 | if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) |
210aa14a | 7428 | return (qualifiers | 6); |
b0468b84 | 7429 | |
4900aa61 | 7430 | else |
b0468b84 | 7431 | return (qualifiers | 7); |
4900aa61 | 7432 | |
210aa14a | 7433 | case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ |
13d39dbc | 7434 | /* ??? We need to distinguish between double and float complex types, |
c82aa69a JW |
7435 | but I don't know how yet because I can't reach this code from |
7436 | existing front-ends. */ | |
7437 | return (qualifiers | 7); /* Who knows? */ | |
7438 | ||
1b5963f7 | 7439 | case VECTOR_TYPE: |
62de55f7 | 7440 | case BOOLEAN_TYPE: /* Boolean truth value type. */ |
210aa14a | 7441 | case LANG_TYPE: /* ? */ |
26902ae0 | 7442 | return qualifiers; |
4900aa61 | 7443 | |
210aa14a | 7444 | default: |
f5f7d171 | 7445 | gcc_unreachable (); /* Not a type! */ |
210aa14a RS |
7446 | } |
7447 | } | |
e5e809f4 JL |
7448 | |
7449 | return qualifiers; | |
210aa14a | 7450 | } |
ead69aea | 7451 | \f |
61a55e8b DE |
7452 | /* Nested function support. */ |
7453 | ||
7454 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
7455 | FNADDR is an RTX for the address of the function's pure code. | |
7456 | CXT is an RTX for the static chain value for the function. | |
7457 | ||
7458 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
7459 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
7460 | (to store insns). This is a bit excessive. Perhaps a different | |
7461 | mechanism would be better here. | |
7462 | ||
849a528d | 7463 | Emit enough FLUSH insns to synchronize the data and instruction caches. */ |
61a55e8b | 7464 | |
809e78cc RH |
7465 | static void |
7466 | sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt) | |
61a55e8b | 7467 | { |
1ec0c607 | 7468 | /* SPARC 32-bit trampoline: |
c6b0465b | 7469 | |
e0d80184 DM |
7470 | sethi %hi(fn), %g1 |
7471 | sethi %hi(static), %g2 | |
7472 | jmp %g1+%lo(fn) | |
7473 | or %g2, %lo(static), %g2 | |
c6b0465b JC |
7474 | |
7475 | SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii | |
7476 | JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii | |
7477 | */ | |
7478 | ||
35aa3c1c | 7479 | emit_move_insn |
809e78cc | 7480 | (adjust_address (m_tramp, SImode, 0), |
35aa3c1c RK |
7481 | expand_binop (SImode, ior_optab, |
7482 | expand_shift (RSHIFT_EXPR, SImode, fnaddr, | |
7483 | size_int (10), 0, 1), | |
7484 | GEN_INT (trunc_int_for_mode (0x03000000, SImode)), | |
7485 | NULL_RTX, 1, OPTAB_DIRECT)); | |
7486 | ||
7487 | emit_move_insn | |
809e78cc | 7488 | (adjust_address (m_tramp, SImode, 4), |
35aa3c1c RK |
7489 | expand_binop (SImode, ior_optab, |
7490 | expand_shift (RSHIFT_EXPR, SImode, cxt, | |
7491 | size_int (10), 0, 1), | |
7492 | GEN_INT (trunc_int_for_mode (0x05000000, SImode)), | |
7493 | NULL_RTX, 1, OPTAB_DIRECT)); | |
7494 | ||
7495 | emit_move_insn | |
809e78cc | 7496 | (adjust_address (m_tramp, SImode, 8), |
35aa3c1c RK |
7497 | expand_binop (SImode, ior_optab, |
7498 | expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX), | |
7499 | GEN_INT (trunc_int_for_mode (0x81c06000, SImode)), | |
7500 | NULL_RTX, 1, OPTAB_DIRECT)); | |
7501 | ||
7502 | emit_move_insn | |
809e78cc | 7503 | (adjust_address (m_tramp, SImode, 12), |
35aa3c1c RK |
7504 | expand_binop (SImode, ior_optab, |
7505 | expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX), | |
7506 | GEN_INT (trunc_int_for_mode (0x8410a000, SImode)), | |
7507 | NULL_RTX, 1, OPTAB_DIRECT)); | |
c6b0465b | 7508 | |
c6b0465b JC |
7509 | /* On UltraSPARC a flush flushes an entire cache line. The trampoline is |
7510 | aligned on a 16 byte boundary so one flush clears it all. */ | |
809e78cc | 7511 | emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 0)))); |
84643cbf | 7512 | if (sparc_cpu != PROCESSOR_ULTRASPARC |
4c837a1e | 7513 | && sparc_cpu != PROCESSOR_ULTRASPARC3 |
9eeaed6e DM |
7514 | && sparc_cpu != PROCESSOR_NIAGARA |
7515 | && sparc_cpu != PROCESSOR_NIAGARA2) | |
809e78cc | 7516 | emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 8)))); |
1ec0c607 WH |
7517 | |
7518 | /* Call __enable_execute_stack after writing onto the stack to make sure | |
7519 | the stack address is accessible. */ | |
e7a742ec | 7520 | #ifdef ENABLE_EXECUTE_STACK |
f1c25d3b | 7521 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"), |
809e78cc | 7522 | LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode); |
1ec0c607 WH |
7523 | #endif |
7524 | ||
61a55e8b DE |
7525 | } |
7526 | ||
1ec0c607 | 7527 | /* The 64-bit version is simpler because it makes more sense to load the |
849a528d RK |
7528 | values as "immediate" data out of the trampoline. It's also easier since |
7529 | we can read the PC without clobbering a register. */ | |
7530 | ||
809e78cc RH |
7531 | static void |
7532 | sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt) | |
61a55e8b | 7533 | { |
1ec0c607 | 7534 | /* SPARC 64-bit trampoline: |
345a6161 | 7535 | |
e0d80184 DM |
7536 | rd %pc, %g1 |
7537 | ldx [%g1+24], %g5 | |
7538 | jmp %g5 | |
7539 | ldx [%g1+16], %g5 | |
c6b0465b JC |
7540 | +16 bytes data |
7541 | */ | |
7542 | ||
809e78cc | 7543 | emit_move_insn (adjust_address (m_tramp, SImode, 0), |
e3aaacf4 | 7544 | GEN_INT (trunc_int_for_mode (0x83414000, SImode))); |
809e78cc | 7545 | emit_move_insn (adjust_address (m_tramp, SImode, 4), |
e3aaacf4 | 7546 | GEN_INT (trunc_int_for_mode (0xca586018, SImode))); |
809e78cc | 7547 | emit_move_insn (adjust_address (m_tramp, SImode, 8), |
e3aaacf4 | 7548 | GEN_INT (trunc_int_for_mode (0x81c14000, SImode))); |
809e78cc | 7549 | emit_move_insn (adjust_address (m_tramp, SImode, 12), |
e3aaacf4 | 7550 | GEN_INT (trunc_int_for_mode (0xca586010, SImode))); |
809e78cc RH |
7551 | emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt); |
7552 | emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr); | |
7553 | emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0)))); | |
345a6161 | 7554 | |
fae15c93 | 7555 | if (sparc_cpu != PROCESSOR_ULTRASPARC |
4c837a1e | 7556 | && sparc_cpu != PROCESSOR_ULTRASPARC3 |
9eeaed6e DM |
7557 | && sparc_cpu != PROCESSOR_NIAGARA |
7558 | && sparc_cpu != PROCESSOR_NIAGARA2) | |
809e78cc | 7559 | emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8)))); |
1ec0c607 WH |
7560 | |
7561 | /* Call __enable_execute_stack after writing onto the stack to make sure | |
7562 | the stack address is accessible. */ | |
e7a742ec | 7563 | #ifdef ENABLE_EXECUTE_STACK |
f1c25d3b | 7564 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"), |
809e78cc | 7565 | LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode); |
1ec0c607 | 7566 | #endif |
61a55e8b | 7567 | } |
809e78cc RH |
7568 | |
7569 | /* Worker for TARGET_TRAMPOLINE_INIT. */ | |
7570 | ||
7571 | static void | |
7572 | sparc_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) | |
7573 | { | |
7574 | rtx fnaddr = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0)); | |
7575 | cxt = force_reg (Pmode, cxt); | |
7576 | if (TARGET_ARCH64) | |
7577 | sparc64_initialize_trampoline (m_tramp, fnaddr, cxt); | |
7578 | else | |
7579 | sparc32_initialize_trampoline (m_tramp, fnaddr, cxt); | |
7580 | } | |
61a55e8b | 7581 | \f |
dbb54862 JW |
7582 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
7583 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
7584 | ||
8947065c | 7585 | static int |
fc27d102 | 7586 | supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
dbb54862 JW |
7587 | { |
7588 | enum attr_type insn_type; | |
7589 | ||
7590 | if (! recog_memoized (insn)) | |
7591 | return 0; | |
7592 | ||
7593 | insn_type = get_attr_type (insn); | |
7594 | ||
7595 | if (REG_NOTE_KIND (link) == 0) | |
7596 | { | |
7597 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7598 | cycles later. */ | |
7599 | ||
7600 | /* if a load, then the dependence must be on the memory address; | |
3bc8b61e DM |
7601 | add an extra "cycle". Note that the cost could be two cycles |
7602 | if the reg was written late in an instruction group; we ca not tell | |
dbb54862 JW |
7603 | here. */ |
7604 | if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) | |
7605 | return cost + 3; | |
7606 | ||
7607 | /* Get the delay only if the address of the store is the dependence. */ | |
7608 | if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) | |
7609 | { | |
7610 | rtx pat = PATTERN(insn); | |
7611 | rtx dep_pat = PATTERN (dep_insn); | |
7612 | ||
7613 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
3bc8b61e | 7614 | return cost; /* This should not happen! */ |
dbb54862 JW |
7615 | |
7616 | /* The dependency between the two instructions was on the data that | |
7617 | is being stored. Assume that this implies that the address of the | |
7618 | store is not dependent. */ | |
7619 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
7620 | return cost; | |
7621 | ||
7622 | return cost + 3; /* An approximation. */ | |
7623 | } | |
7624 | ||
7625 | /* A shift instruction cannot receive its data from an instruction | |
7626 | in the same cycle; add a one cycle penalty. */ | |
7627 | if (insn_type == TYPE_SHIFT) | |
7628 | return cost + 3; /* Split before cascade into shift. */ | |
7629 | } | |
7630 | else | |
7631 | { | |
7632 | /* Anti- or output- dependency; DEP_INSN reads/writes a register that | |
7633 | INSN writes some cycles later. */ | |
7634 | ||
7635 | /* These are only significant for the fpu unit; writing a fp reg before | |
7636 | the fpu has finished with it stalls the processor. */ | |
7637 | ||
7638 | /* Reusing an integer register causes no problems. */ | |
7639 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
7640 | return 0; | |
7641 | } | |
7642 | ||
7643 | return cost; | |
7644 | } | |
bfd6bc60 | 7645 | |
8947065c | 7646 | static int |
fc27d102 | 7647 | hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
8947065c RH |
7648 | { |
7649 | enum attr_type insn_type, dep_type; | |
7650 | rtx pat = PATTERN(insn); | |
7651 | rtx dep_pat = PATTERN (dep_insn); | |
7652 | ||
7653 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) | |
7654 | return cost; | |
7655 | ||
7656 | insn_type = get_attr_type (insn); | |
7657 | dep_type = get_attr_type (dep_insn); | |
7658 | ||
7659 | switch (REG_NOTE_KIND (link)) | |
7660 | { | |
7661 | case 0: | |
7662 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7663 | cycles later. */ | |
7664 | ||
7665 | switch (insn_type) | |
7666 | { | |
7667 | case TYPE_STORE: | |
7668 | case TYPE_FPSTORE: | |
80ffc95e | 7669 | /* Get the delay iff the address of the store is the dependence. */ |
8947065c RH |
7670 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) |
7671 | return cost; | |
7672 | ||
7673 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
7674 | return cost; | |
7675 | return cost + 3; | |
7676 | ||
7677 | case TYPE_LOAD: | |
7678 | case TYPE_SLOAD: | |
7679 | case TYPE_FPLOAD: | |
7680 | /* If a load, then the dependence must be on the memory address. If | |
7681 | the addresses aren't equal, then it might be a false dependency */ | |
7682 | if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) | |
7683 | { | |
7684 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET | |
4900aa61 | 7685 | || GET_CODE (SET_DEST (dep_pat)) != MEM |
8947065c RH |
7686 | || GET_CODE (SET_SRC (pat)) != MEM |
7687 | || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), | |
7688 | XEXP (SET_SRC (pat), 0))) | |
7689 | return cost + 2; | |
7690 | ||
4900aa61 | 7691 | return cost + 8; |
8947065c RH |
7692 | } |
7693 | break; | |
7694 | ||
7695 | case TYPE_BRANCH: | |
7696 | /* Compare to branch latency is 0. There is no benefit from | |
7697 | separating compare and branch. */ | |
7698 | if (dep_type == TYPE_COMPARE) | |
7699 | return 0; | |
7700 | /* Floating point compare to branch latency is less than | |
7701 | compare to conditional move. */ | |
7702 | if (dep_type == TYPE_FPCMP) | |
7703 | return cost - 1; | |
7704 | break; | |
3bb5de61 KG |
7705 | default: |
7706 | break; | |
8947065c RH |
7707 | } |
7708 | break; | |
7709 | ||
7710 | case REG_DEP_ANTI: | |
80ffc95e | 7711 | /* Anti-dependencies only penalize the fpu unit. */ |
8947065c RH |
7712 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) |
7713 | return 0; | |
7714 | break; | |
7715 | ||
7716 | default: | |
7717 | break; | |
4900aa61 | 7718 | } |
8947065c RH |
7719 | |
7720 | return cost; | |
7721 | } | |
7722 | ||
c237e94a | 7723 | static int |
fc27d102 | 7724 | sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost) |
8947065c RH |
7725 | { |
7726 | switch (sparc_cpu) | |
7727 | { | |
7728 | case PROCESSOR_SUPERSPARC: | |
7729 | cost = supersparc_adjust_cost (insn, link, dep, cost); | |
7730 | break; | |
7731 | case PROCESSOR_HYPERSPARC: | |
7732 | case PROCESSOR_SPARCLITE86X: | |
7733 | cost = hypersparc_adjust_cost (insn, link, dep, cost); | |
7734 | break; | |
8947065c RH |
7735 | default: |
7736 | break; | |
7737 | } | |
7738 | return cost; | |
7739 | } | |
7740 | ||
fae15c93 | 7741 | static void |
fc27d102 KG |
7742 | sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED, |
7743 | int sched_verbose ATTRIBUTE_UNUSED, | |
7744 | int max_ready ATTRIBUTE_UNUSED) | |
4900aa61 EB |
7745 | {} |
7746 | ||
fae15c93 | 7747 | static int |
fc27d102 | 7748 | sparc_use_sched_lookahead (void) |
fae15c93 | 7749 | { |
9eeaed6e DM |
7750 | if (sparc_cpu == PROCESSOR_NIAGARA |
7751 | || sparc_cpu == PROCESSOR_NIAGARA2) | |
4c837a1e | 7752 | return 0; |
fae15c93 VM |
7753 | if (sparc_cpu == PROCESSOR_ULTRASPARC |
7754 | || sparc_cpu == PROCESSOR_ULTRASPARC3) | |
7755 | return 4; | |
7756 | if ((1 << sparc_cpu) & | |
7757 | ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | | |
7758 | (1 << PROCESSOR_SPARCLITE86X))) | |
7759 | return 3; | |
3bc8b61e DM |
7760 | return 0; |
7761 | } | |
7762 | ||
fae15c93 | 7763 | static int |
fc27d102 | 7764 | sparc_issue_rate (void) |
bfd6bc60 JC |
7765 | { |
7766 | switch (sparc_cpu) | |
7767 | { | |
4c837a1e | 7768 | case PROCESSOR_NIAGARA: |
9eeaed6e | 7769 | case PROCESSOR_NIAGARA2: |
fae15c93 VM |
7770 | default: |
7771 | return 1; | |
7772 | case PROCESSOR_V9: | |
284d86e9 | 7773 | /* Assume V9 processors are capable of at least dual-issue. */ |
bfd6bc60 | 7774 | return 2; |
fae15c93 VM |
7775 | case PROCESSOR_SUPERSPARC: |
7776 | return 3; | |
393049a9 RH |
7777 | case PROCESSOR_HYPERSPARC: |
7778 | case PROCESSOR_SPARCLITE86X: | |
7779 | return 2; | |
fae15c93 VM |
7780 | case PROCESSOR_ULTRASPARC: |
7781 | case PROCESSOR_ULTRASPARC3: | |
7782 | return 4; | |
bfd6bc60 JC |
7783 | } |
7784 | } | |
284d86e9 JC |
7785 | |
7786 | static int | |
fc27d102 | 7787 | set_extends (rtx insn) |
284d86e9 JC |
7788 | { |
7789 | register rtx pat = PATTERN (insn); | |
7790 | ||
7791 | switch (GET_CODE (SET_SRC (pat))) | |
7792 | { | |
80ffc95e | 7793 | /* Load and some shift instructions zero extend. */ |
284d86e9 JC |
7794 | case MEM: |
7795 | case ZERO_EXTEND: | |
7796 | /* sethi clears the high bits */ | |
7797 | case HIGH: | |
7798 | /* LO_SUM is used with sethi. sethi cleared the high | |
7799 | bits and the values used with lo_sum are positive */ | |
7800 | case LO_SUM: | |
284d86e9 JC |
7801 | /* Store flag stores 0 or 1 */ |
7802 | case LT: case LTU: | |
7803 | case GT: case GTU: | |
7804 | case LE: case LEU: | |
7805 | case GE: case GEU: | |
7806 | case EQ: | |
7807 | case NE: | |
7808 | return 1; | |
7809 | case AND: | |
7810 | { | |
4df1190a | 7811 | rtx op0 = XEXP (SET_SRC (pat), 0); |
284d86e9 JC |
7812 | rtx op1 = XEXP (SET_SRC (pat), 1); |
7813 | if (GET_CODE (op1) == CONST_INT) | |
7814 | return INTVAL (op1) >= 0; | |
4df1190a JJ |
7815 | if (GET_CODE (op0) != REG) |
7816 | return 0; | |
7817 | if (sparc_check_64 (op0, insn) == 1) | |
284d86e9 | 7818 | return 1; |
4df1190a JJ |
7819 | return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); |
7820 | } | |
7821 | case IOR: | |
7822 | case XOR: | |
7823 | { | |
7824 | rtx op0 = XEXP (SET_SRC (pat), 0); | |
7825 | rtx op1 = XEXP (SET_SRC (pat), 1); | |
7826 | if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) | |
7827 | return 0; | |
7828 | if (GET_CODE (op1) == CONST_INT) | |
7829 | return INTVAL (op1) >= 0; | |
7830 | return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); | |
284d86e9 | 7831 | } |
284d86e9 JC |
7832 | case LSHIFTRT: |
7833 | return GET_MODE (SET_SRC (pat)) == SImode; | |
80ffc95e | 7834 | /* Positive integers leave the high bits zero. */ |
284d86e9 | 7835 | case CONST_DOUBLE: |
4df1190a | 7836 | return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000); |
284d86e9 | 7837 | case CONST_INT: |
4df1190a | 7838 | return ! (INTVAL (SET_SRC (pat)) & 0x80000000); |
284d86e9 JC |
7839 | case ASHIFTRT: |
7840 | case SIGN_EXTEND: | |
7841 | return - (GET_MODE (SET_SRC (pat)) == SImode); | |
4df1190a JJ |
7842 | case REG: |
7843 | return sparc_check_64 (SET_SRC (pat), insn); | |
284d86e9 JC |
7844 | default: |
7845 | return 0; | |
7846 | } | |
7847 | } | |
7848 | ||
80ffc95e | 7849 | /* We _ought_ to have only one kind per function, but... */ |
e2500fed GK |
7850 | static GTY(()) rtx sparc_addr_diff_list; |
7851 | static GTY(()) rtx sparc_addr_list; | |
e0d80184 DM |
7852 | |
7853 | void | |
fc27d102 | 7854 | sparc_defer_case_vector (rtx lab, rtx vec, int diff) |
e0d80184 DM |
7855 | { |
7856 | vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); | |
7857 | if (diff) | |
7858 | sparc_addr_diff_list | |
7859 | = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); | |
7860 | else | |
7861 | sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); | |
7862 | } | |
7863 | ||
4900aa61 | 7864 | static void |
fc27d102 | 7865 | sparc_output_addr_vec (rtx vec) |
e0d80184 DM |
7866 | { |
7867 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
7868 | int idx, vlen = XVECLEN (body, 0); | |
7869 | ||
4900aa61 | 7870 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
d1accaa3 JJ |
7871 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); |
7872 | #endif | |
7873 | ||
e0d80184 DM |
7874 | #ifdef ASM_OUTPUT_CASE_LABEL |
7875 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
7876 | NEXT_INSN (lab)); | |
7877 | #else | |
4977bab6 | 7878 | (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); |
e0d80184 DM |
7879 | #endif |
7880 | ||
7881 | for (idx = 0; idx < vlen; idx++) | |
7882 | { | |
7883 | ASM_OUTPUT_ADDR_VEC_ELT | |
7884 | (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); | |
7885 | } | |
4900aa61 | 7886 | |
d1accaa3 JJ |
7887 | #ifdef ASM_OUTPUT_ADDR_VEC_END |
7888 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
7889 | #endif | |
e0d80184 DM |
7890 | } |
7891 | ||
4900aa61 | 7892 | static void |
fc27d102 | 7893 | sparc_output_addr_diff_vec (rtx vec) |
e0d80184 DM |
7894 | { |
7895 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
7896 | rtx base = XEXP (XEXP (body, 0), 0); | |
7897 | int idx, vlen = XVECLEN (body, 1); | |
7898 | ||
4900aa61 | 7899 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
d1accaa3 JJ |
7900 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); |
7901 | #endif | |
7902 | ||
e0d80184 DM |
7903 | #ifdef ASM_OUTPUT_CASE_LABEL |
7904 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
7905 | NEXT_INSN (lab)); | |
7906 | #else | |
4977bab6 | 7907 | (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); |
e0d80184 DM |
7908 | #endif |
7909 | ||
7910 | for (idx = 0; idx < vlen; idx++) | |
7911 | { | |
7912 | ASM_OUTPUT_ADDR_DIFF_ELT | |
7913 | (asm_out_file, | |
7914 | body, | |
7915 | CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), | |
7916 | CODE_LABEL_NUMBER (base)); | |
7917 | } | |
4900aa61 | 7918 | |
d1accaa3 JJ |
7919 | #ifdef ASM_OUTPUT_ADDR_VEC_END |
7920 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
7921 | #endif | |
e0d80184 DM |
7922 | } |
7923 | ||
7924 | static void | |
fc27d102 | 7925 | sparc_output_deferred_case_vectors (void) |
e0d80184 DM |
7926 | { |
7927 | rtx t; | |
d676da68 | 7928 | int align; |
e0d80184 | 7929 | |
f3b8847b DM |
7930 | if (sparc_addr_list == NULL_RTX |
7931 | && sparc_addr_diff_list == NULL_RTX) | |
7932 | return; | |
7933 | ||
e0d80184 | 7934 | /* Align to cache line in the function's code section. */ |
d6b5193b | 7935 | switch_to_section (current_function_section ()); |
d676da68 DM |
7936 | |
7937 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
7938 | if (align > 0) | |
f3b8847b | 7939 | ASM_OUTPUT_ALIGN (asm_out_file, align); |
4900aa61 | 7940 | |
e0d80184 DM |
7941 | for (t = sparc_addr_list; t ; t = XEXP (t, 1)) |
7942 | sparc_output_addr_vec (XEXP (t, 0)); | |
7943 | for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) | |
7944 | sparc_output_addr_diff_vec (XEXP (t, 0)); | |
7945 | ||
7946 | sparc_addr_list = sparc_addr_diff_list = NULL_RTX; | |
7947 | } | |
7948 | ||
284d86e9 JC |
7949 | /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are |
7950 | unknown. Return 1 if the high bits are zero, -1 if the register is | |
7951 | sign extended. */ | |
7952 | int | |
fc27d102 | 7953 | sparc_check_64 (rtx x, rtx insn) |
284d86e9 JC |
7954 | { |
7955 | /* If a register is set only once it is safe to ignore insns this | |
7956 | code does not know how to handle. The loop will either recognize | |
7957 | the single set and return the correct value or fail to recognize | |
7958 | it and return 0. */ | |
7959 | int set_once = 0; | |
4df1190a JJ |
7960 | rtx y = x; |
7961 | ||
f5f7d171 | 7962 | gcc_assert (GET_CODE (x) == REG); |
4df1190a JJ |
7963 | |
7964 | if (GET_MODE (x) == DImode) | |
7965 | y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN); | |
284d86e9 | 7966 | |
4df1190a | 7967 | if (flag_expensive_optimizations |
b718216c | 7968 | && df && DF_REG_DEF_COUNT (REGNO (y)) == 1) |
284d86e9 JC |
7969 | set_once = 1; |
7970 | ||
7971 | if (insn == 0) | |
d6f4ec51 KG |
7972 | { |
7973 | if (set_once) | |
7974 | insn = get_last_insn_anywhere (); | |
7975 | else | |
7976 | return 0; | |
7977 | } | |
284d86e9 | 7978 | |
d6f4ec51 | 7979 | while ((insn = PREV_INSN (insn))) |
284d86e9 JC |
7980 | { |
7981 | switch (GET_CODE (insn)) | |
7982 | { | |
7983 | case JUMP_INSN: | |
7984 | case NOTE: | |
7985 | break; | |
7986 | case CODE_LABEL: | |
7987 | case CALL_INSN: | |
7988 | default: | |
7989 | if (! set_once) | |
7990 | return 0; | |
7991 | break; | |
7992 | case INSN: | |
7993 | { | |
7994 | rtx pat = PATTERN (insn); | |
7995 | if (GET_CODE (pat) != SET) | |
7996 | return 0; | |
7997 | if (rtx_equal_p (x, SET_DEST (pat))) | |
4df1190a JJ |
7998 | return set_extends (insn); |
7999 | if (y && rtx_equal_p (y, SET_DEST (pat))) | |
8000 | return set_extends (insn); | |
8001 | if (reg_overlap_mentioned_p (SET_DEST (pat), y)) | |
284d86e9 JC |
8002 | return 0; |
8003 | } | |
8004 | } | |
8005 | } | |
8006 | return 0; | |
8007 | } | |
8008 | ||
01d3224a EB |
8009 | /* Returns assembly code to perform a DImode shift using |
8010 | a 64-bit global or out register on SPARC-V8+. */ | |
a6163c22 EB |
8011 | const char * |
8012 | output_v8plus_shift (rtx *operands, rtx insn, const char *opcode) | |
284d86e9 JC |
8013 | { |
8014 | static char asm_code[60]; | |
8015 | ||
01d3224a EB |
8016 | /* The scratch register is only required when the destination |
8017 | register is not a 64-bit global or out register. */ | |
8018 | if (which_alternative != 2) | |
284d86e9 | 8019 | operands[3] = operands[0]; |
01d3224a | 8020 | |
1c8b4e29 EB |
8021 | /* We can only shift by constants <= 63. */ |
8022 | if (GET_CODE (operands[2]) == CONST_INT) | |
8023 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); | |
8024 | ||
c6b0465b JC |
8025 | if (GET_CODE (operands[1]) == CONST_INT) |
8026 | { | |
4df1190a | 8027 | output_asm_insn ("mov\t%1, %3", operands); |
c6b0465b JC |
8028 | } |
8029 | else | |
8030 | { | |
4df1190a | 8031 | output_asm_insn ("sllx\t%H1, 32, %3", operands); |
c6b0465b | 8032 | if (sparc_check_64 (operands[1], insn) <= 0) |
4df1190a JJ |
8033 | output_asm_insn ("srl\t%L1, 0, %L1", operands); |
8034 | output_asm_insn ("or\t%L1, %3, %3", operands); | |
c6b0465b | 8035 | } |
284d86e9 JC |
8036 | |
8037 | strcpy(asm_code, opcode); | |
01d3224a | 8038 | |
284d86e9 | 8039 | if (which_alternative != 2) |
4df1190a | 8040 | return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); |
284d86e9 | 8041 | else |
4df1190a | 8042 | return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"); |
284d86e9 | 8043 | } |
2be15d0f | 8044 | \f |
89a8b315 RH |
8045 | /* Output rtl to increment the profiler label LABELNO |
8046 | for profiling a function entry. */ | |
2be15d0f RH |
8047 | |
8048 | void | |
fc27d102 | 8049 | sparc_profile_hook (int labelno) |
2be15d0f RH |
8050 | { |
8051 | char buf[32]; | |
89a8b315 | 8052 | rtx lab, fun; |
2be15d0f | 8053 | |
89a8b315 | 8054 | fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION); |
cc44abe6 DM |
8055 | if (NO_PROFILE_COUNTERS) |
8056 | { | |
8057 | emit_library_call (fun, LCT_NORMAL, VOIDmode, 0); | |
8058 | } | |
8059 | else | |
8060 | { | |
8061 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
8062 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
8063 | emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode); | |
8064 | } | |
2be15d0f | 8065 | } |
89a8b315 | 8066 | \f |
d1ced155 EB |
8067 | /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */ |
8068 | ||
7c262518 | 8069 | static void |
d1ced155 EB |
8070 | sparc_solaris_elf_asm_named_section (const char *name, unsigned int flags, |
8071 | tree decl ATTRIBUTE_UNUSED) | |
7c262518 RH |
8072 | { |
8073 | fprintf (asm_out_file, "\t.section\t\"%s\"", name); | |
8074 | ||
8075 | if (!(flags & SECTION_DEBUG)) | |
8076 | fputs (",#alloc", asm_out_file); | |
8077 | if (flags & SECTION_WRITE) | |
8078 | fputs (",#write", asm_out_file); | |
2f3321ca EB |
8079 | if (flags & SECTION_TLS) |
8080 | fputs (",#tls", asm_out_file); | |
7c262518 RH |
8081 | if (flags & SECTION_CODE) |
8082 | fputs (",#execinstr", asm_out_file); | |
8083 | ||
8084 | /* ??? Handle SECTION_BSS. */ | |
8085 | ||
8086 | fputc ('\n', asm_out_file); | |
8087 | } | |
f451b552 | 8088 | |
60b85c4c | 8089 | /* We do not allow indirect calls to be optimized into sibling calls. |
951661a1 EB |
8090 | |
8091 | We cannot use sibling calls when delayed branches are disabled | |
8092 | because they will likely require the call delay slot to be filled. | |
8093 | ||
60b85c4c | 8094 | Also, on SPARC 32-bit we cannot emit a sibling call when the |
4977bab6 ZW |
8095 | current function returns a structure. This is because the "unimp |
8096 | after call" convention would cause the callee to return to the | |
8097 | wrong place. The generic code already disallows cases where the | |
8098 | function being called returns a structure. | |
8099 | ||
8100 | It may seem strange how this last case could occur. Usually there | |
8101 | is code after the call which jumps to epilogue code which dumps the | |
8102 | return value into the struct return area. That ought to invalidate | |
951661a1 | 8103 | the sibling call right? Well, in the C++ case we can end up passing |
4977bab6 ZW |
8104 | the pointer to the struct return area to a constructor (which returns |
8105 | void) and then nothing else happens. Such a sibling call would look | |
1910440e RS |
8106 | valid without the added check here. |
8107 | ||
8108 | VxWorks PIC PLT entries require the global pointer to be initialized | |
8109 | on entry. We therefore can't emit sibling calls to them. */ | |
4977bab6 | 8110 | static bool |
fc27d102 | 8111 | sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
4977bab6 | 8112 | { |
951661a1 EB |
8113 | return (decl |
8114 | && flag_delayed_branch | |
e3b5732b | 8115 | && (TARGET_ARCH64 || ! cfun->returns_struct) |
1910440e RS |
8116 | && !(TARGET_VXWORKS_RTP |
8117 | && flag_pic | |
8118 | && !targetm.binds_local_p (decl))); | |
4977bab6 | 8119 | } |
c15c90bb ZW |
8120 | \f |
8121 | /* libfunc renaming. */ | |
8122 | #include "config/gofast.h" | |
8123 | ||
8124 | static void | |
8125 | sparc_init_libfuncs (void) | |
8126 | { | |
8127 | if (TARGET_ARCH32) | |
8128 | { | |
8129 | /* Use the subroutines that Sun's library provides for integer | |
8130 | multiply and divide. The `*' prevents an underscore from | |
8131 | being prepended by the compiler. .umul is a little faster | |
ff482c8d | 8132 | than .mul. */ |
c15c90bb ZW |
8133 | set_optab_libfunc (smul_optab, SImode, "*.umul"); |
8134 | set_optab_libfunc (sdiv_optab, SImode, "*.div"); | |
8135 | set_optab_libfunc (udiv_optab, SImode, "*.udiv"); | |
8136 | set_optab_libfunc (smod_optab, SImode, "*.rem"); | |
8137 | set_optab_libfunc (umod_optab, SImode, "*.urem"); | |
8138 | ||
8139 | /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */ | |
8140 | set_optab_libfunc (add_optab, TFmode, "_Q_add"); | |
8141 | set_optab_libfunc (sub_optab, TFmode, "_Q_sub"); | |
8142 | set_optab_libfunc (neg_optab, TFmode, "_Q_neg"); | |
8143 | set_optab_libfunc (smul_optab, TFmode, "_Q_mul"); | |
8144 | set_optab_libfunc (sdiv_optab, TFmode, "_Q_div"); | |
8145 | ||
8146 | /* We can define the TFmode sqrt optab only if TARGET_FPU. This | |
8147 | is because with soft-float, the SFmode and DFmode sqrt | |
8148 | instructions will be absent, and the compiler will notice and | |
8149 | try to use the TFmode sqrt instruction for calls to the | |
8150 | builtin function sqrt, but this fails. */ | |
8151 | if (TARGET_FPU) | |
8152 | set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt"); | |
8153 | ||
c9034561 ZW |
8154 | set_optab_libfunc (eq_optab, TFmode, "_Q_feq"); |
8155 | set_optab_libfunc (ne_optab, TFmode, "_Q_fne"); | |
8156 | set_optab_libfunc (gt_optab, TFmode, "_Q_fgt"); | |
8157 | set_optab_libfunc (ge_optab, TFmode, "_Q_fge"); | |
8158 | set_optab_libfunc (lt_optab, TFmode, "_Q_flt"); | |
8159 | set_optab_libfunc (le_optab, TFmode, "_Q_fle"); | |
c15c90bb | 8160 | |
85363ca0 ZW |
8161 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq"); |
8162 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq"); | |
8163 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos"); | |
8164 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod"); | |
8165 | ||
8166 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi"); | |
8167 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou"); | |
8168 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq"); | |
9b336fa4 | 8169 | set_conv_libfunc (ufloat_optab, TFmode, SImode, "_Q_utoq"); |
c15c90bb | 8170 | |
45dcc026 JJ |
8171 | if (DITF_CONVERSION_LIBFUNCS) |
8172 | { | |
8173 | set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll"); | |
8174 | set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull"); | |
8175 | set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq"); | |
9b336fa4 | 8176 | set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq"); |
45dcc026 JJ |
8177 | } |
8178 | ||
c15c90bb ZW |
8179 | if (SUN_CONVERSION_LIBFUNCS) |
8180 | { | |
85363ca0 ZW |
8181 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); |
8182 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); | |
8183 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); | |
8184 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); | |
c15c90bb ZW |
8185 | } |
8186 | } | |
8187 | if (TARGET_ARCH64) | |
8188 | { | |
8189 | /* In the SPARC 64bit ABI, SImode multiply and divide functions | |
8190 | do not exist in the library. Make sure the compiler does not | |
8191 | emit calls to them by accident. (It should always use the | |
8192 | hardware instructions.) */ | |
8193 | set_optab_libfunc (smul_optab, SImode, 0); | |
8194 | set_optab_libfunc (sdiv_optab, SImode, 0); | |
8195 | set_optab_libfunc (udiv_optab, SImode, 0); | |
8196 | set_optab_libfunc (smod_optab, SImode, 0); | |
8197 | set_optab_libfunc (umod_optab, SImode, 0); | |
8198 | ||
8199 | if (SUN_INTEGER_MULTIPLY_64) | |
8200 | { | |
8201 | set_optab_libfunc (smul_optab, DImode, "__mul64"); | |
8202 | set_optab_libfunc (sdiv_optab, DImode, "__div64"); | |
8203 | set_optab_libfunc (udiv_optab, DImode, "__udiv64"); | |
8204 | set_optab_libfunc (smod_optab, DImode, "__rem64"); | |
8205 | set_optab_libfunc (umod_optab, DImode, "__urem64"); | |
8206 | } | |
8207 | ||
8208 | if (SUN_CONVERSION_LIBFUNCS) | |
8209 | { | |
85363ca0 ZW |
8210 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol"); |
8211 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul"); | |
8212 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol"); | |
8213 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul"); | |
c15c90bb ZW |
8214 | } |
8215 | } | |
4977bab6 | 8216 | |
c15c90bb ZW |
8217 | gofast_maybe_init_libfuncs (); |
8218 | } | |
8219 | \f | |
16f59241 | 8220 | #define def_builtin(NAME, CODE, TYPE) \ |
c79efc4d RÁE |
8221 | add_builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \ |
8222 | NULL_TREE) | |
16f59241 JM |
8223 | |
8224 | /* Implement the TARGET_INIT_BUILTINS target hook. | |
8225 | Create builtin functions for special SPARC instructions. */ | |
8226 | ||
8227 | static void | |
8228 | sparc_init_builtins (void) | |
8229 | { | |
8230 | if (TARGET_VIS) | |
8231 | sparc_vis_init_builtins (); | |
8232 | } | |
8233 | ||
8234 | /* Create builtin functions for VIS 1.0 instructions. */ | |
8235 | ||
8236 | static void | |
8237 | sparc_vis_init_builtins (void) | |
8238 | { | |
8239 | tree v4qi = build_vector_type (unsigned_intQI_type_node, 4); | |
8240 | tree v8qi = build_vector_type (unsigned_intQI_type_node, 8); | |
8241 | tree v4hi = build_vector_type (intHI_type_node, 4); | |
8242 | tree v2hi = build_vector_type (intHI_type_node, 2); | |
8243 | tree v2si = build_vector_type (intSI_type_node, 2); | |
8244 | ||
8245 | tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0); | |
8246 | tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0); | |
8247 | tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0); | |
8248 | tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0); | |
8249 | tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0); | |
8250 | tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0); | |
8251 | tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0); | |
8252 | tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0); | |
8253 | tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0); | |
8254 | tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0); | |
8255 | tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0); | |
8256 | tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0); | |
8257 | tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node, | |
8258 | v8qi, v8qi, | |
8259 | intDI_type_node, 0); | |
8260 | tree di_ftype_di_di = build_function_type_list (intDI_type_node, | |
8261 | intDI_type_node, | |
8262 | intDI_type_node, 0); | |
8263 | tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node, | |
8264 | ptr_type_node, | |
8265 | intSI_type_node, 0); | |
8266 | tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node, | |
8267 | ptr_type_node, | |
8268 | intDI_type_node, 0); | |
8269 | ||
8270 | /* Packing and expanding vectors. */ | |
8271 | def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis, v4qi_ftype_v4hi); | |
8272 | def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis, | |
8273 | v8qi_ftype_v2si_v8qi); | |
8274 | def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis, | |
8275 | v2hi_ftype_v2si); | |
8276 | def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis, v4hi_ftype_v4qi); | |
8277 | def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis, | |
8278 | v8qi_ftype_v4qi_v4qi); | |
8279 | ||
8280 | /* Multiplications. */ | |
8281 | def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis, | |
8282 | v4hi_ftype_v4qi_v4hi); | |
8283 | def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis, | |
8284 | v4hi_ftype_v4qi_v2hi); | |
8285 | def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis, | |
8286 | v4hi_ftype_v4qi_v2hi); | |
8287 | def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis, | |
8288 | v4hi_ftype_v8qi_v4hi); | |
8289 | def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis, | |
8290 | v4hi_ftype_v8qi_v4hi); | |
8291 | def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis, | |
8292 | v2si_ftype_v4qi_v2hi); | |
8293 | def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis, | |
8294 | v2si_ftype_v4qi_v2hi); | |
8295 | ||
8296 | /* Data aligning. */ | |
8297 | def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis, | |
8298 | v4hi_ftype_v4hi_v4hi); | |
8299 | def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis, | |
8300 | v8qi_ftype_v8qi_v8qi); | |
8301 | def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis, | |
8302 | v2si_ftype_v2si_v2si); | |
8303 | def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis, | |
8304 | di_ftype_di_di); | |
8305 | if (TARGET_ARCH64) | |
8306 | def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis, | |
8307 | ptr_ftype_ptr_di); | |
8308 | else | |
8309 | def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis, | |
8310 | ptr_ftype_ptr_si); | |
8311 | ||
8312 | /* Pixel distance. */ | |
8313 | def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis, | |
8314 | di_ftype_v8qi_v8qi_di); | |
8315 | } | |
8316 | ||
8317 | /* Handle TARGET_EXPAND_BUILTIN target hook. | |
0fa2e4df | 8318 | Expand builtin functions for sparc intrinsics. */ |
16f59241 JM |
8319 | |
8320 | static rtx | |
724d7c55 EB |
8321 | sparc_expand_builtin (tree exp, rtx target, |
8322 | rtx subtarget ATTRIBUTE_UNUSED, | |
8323 | enum machine_mode tmode ATTRIBUTE_UNUSED, | |
8324 | int ignore ATTRIBUTE_UNUSED) | |
16f59241 | 8325 | { |
5039610b SL |
8326 | tree arg; |
8327 | call_expr_arg_iterator iter; | |
8328 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); | |
16f59241 JM |
8329 | unsigned int icode = DECL_FUNCTION_CODE (fndecl); |
8330 | rtx pat, op[4]; | |
8331 | enum machine_mode mode[4]; | |
8332 | int arg_count = 0; | |
8333 | ||
724d7c55 EB |
8334 | mode[0] = insn_data[icode].operand[0].mode; |
8335 | if (!target | |
8336 | || GET_MODE (target) != mode[0] | |
8337 | || ! (*insn_data[icode].operand[0].predicate) (target, mode[0])) | |
8338 | op[0] = gen_reg_rtx (mode[0]); | |
16f59241 | 8339 | else |
724d7c55 | 8340 | op[0] = target; |
16f59241 | 8341 | |
5039610b | 8342 | FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) |
16f59241 | 8343 | { |
16f59241 JM |
8344 | arg_count++; |
8345 | mode[arg_count] = insn_data[icode].operand[arg_count].mode; | |
84217346 | 8346 | op[arg_count] = expand_normal (arg); |
16f59241 JM |
8347 | |
8348 | if (! (*insn_data[icode].operand[arg_count].predicate) (op[arg_count], | |
8349 | mode[arg_count])) | |
8350 | op[arg_count] = copy_to_mode_reg (mode[arg_count], op[arg_count]); | |
8351 | } | |
8352 | ||
8353 | switch (arg_count) | |
8354 | { | |
8355 | case 1: | |
8356 | pat = GEN_FCN (icode) (op[0], op[1]); | |
8357 | break; | |
8358 | case 2: | |
8359 | pat = GEN_FCN (icode) (op[0], op[1], op[2]); | |
8360 | break; | |
8361 | case 3: | |
8362 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); | |
8363 | break; | |
8364 | default: | |
8365 | gcc_unreachable (); | |
8366 | } | |
8367 | ||
8368 | if (!pat) | |
8369 | return NULL_RTX; | |
8370 | ||
8371 | emit_insn (pat); | |
8372 | ||
8373 | return op[0]; | |
8374 | } | |
8b0096b4 JM |
8375 | |
8376 | static int | |
8377 | sparc_vis_mul8x16 (int e8, int e16) | |
8378 | { | |
8379 | return (e8 * e16 + 128) / 256; | |
8380 | } | |
8381 | ||
8382 | /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified | |
8383 | by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer | |
8384 | constants. A tree list with the results of the multiplications is returned, | |
8385 | and each element in the list is of INNER_TYPE. */ | |
8386 | ||
8387 | static tree | |
8388 | sparc_handle_vis_mul8x16 (int fncode, tree inner_type, tree elts0, tree elts1) | |
8389 | { | |
8390 | tree n_elts = NULL_TREE; | |
8391 | int scale; | |
8392 | ||
8393 | switch (fncode) | |
8394 | { | |
8395 | case CODE_FOR_fmul8x16_vis: | |
8396 | for (; elts0 && elts1; | |
8397 | elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1)) | |
8398 | { | |
8399 | int val | |
8400 | = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)), | |
8401 | TREE_INT_CST_LOW (TREE_VALUE (elts1))); | |
8402 | n_elts = tree_cons (NULL_TREE, | |
8403 | build_int_cst (inner_type, val), | |
8404 | n_elts); | |
8405 | } | |
8406 | break; | |
8407 | ||
8408 | case CODE_FOR_fmul8x16au_vis: | |
8409 | scale = TREE_INT_CST_LOW (TREE_VALUE (elts1)); | |
8410 | ||
8411 | for (; elts0; elts0 = TREE_CHAIN (elts0)) | |
8412 | { | |
8413 | int val | |
8414 | = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)), | |
8415 | scale); | |
8416 | n_elts = tree_cons (NULL_TREE, | |
8417 | build_int_cst (inner_type, val), | |
8418 | n_elts); | |
8419 | } | |
8420 | break; | |
8421 | ||
8422 | case CODE_FOR_fmul8x16al_vis: | |
8423 | scale = TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1))); | |
8424 | ||
8425 | for (; elts0; elts0 = TREE_CHAIN (elts0)) | |
8426 | { | |
8427 | int val | |
8428 | = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)), | |
8429 | scale); | |
8430 | n_elts = tree_cons (NULL_TREE, | |
8431 | build_int_cst (inner_type, val), | |
8432 | n_elts); | |
8433 | } | |
8434 | break; | |
8435 | ||
8436 | default: | |
8437 | gcc_unreachable (); | |
8438 | } | |
8439 | ||
8440 | return nreverse (n_elts); | |
8441 | ||
8442 | } | |
8443 | /* Handle TARGET_FOLD_BUILTIN target hook. | |
607fb860 | 8444 | Fold builtin functions for SPARC intrinsics. If IGNORE is true the |
8b0096b4 JM |
8445 | result of the function call is ignored. NULL_TREE is returned if the |
8446 | function could not be folded. */ | |
8447 | ||
8448 | static tree | |
f311c3b4 NF |
8449 | sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, |
8450 | tree *args, bool ignore) | |
8b0096b4 JM |
8451 | { |
8452 | tree arg0, arg1, arg2; | |
8453 | tree rtype = TREE_TYPE (TREE_TYPE (fndecl)); | |
bbbbb16a | 8454 | enum insn_code icode = (enum insn_code) DECL_FUNCTION_CODE (fndecl); |
8b0096b4 | 8455 | |
724d7c55 | 8456 | if (ignore |
bbbbb16a ILT |
8457 | && icode != CODE_FOR_alignaddrsi_vis |
8458 | && icode != CODE_FOR_alignaddrdi_vis) | |
724d7c55 | 8459 | return fold_convert (rtype, integer_zero_node); |
8b0096b4 | 8460 | |
bbbbb16a | 8461 | switch (icode) |
8b0096b4 JM |
8462 | { |
8463 | case CODE_FOR_fexpand_vis: | |
f311c3b4 | 8464 | arg0 = args[0]; |
8b0096b4 JM |
8465 | STRIP_NOPS (arg0); |
8466 | ||
8467 | if (TREE_CODE (arg0) == VECTOR_CST) | |
8468 | { | |
8469 | tree inner_type = TREE_TYPE (rtype); | |
8470 | tree elts = TREE_VECTOR_CST_ELTS (arg0); | |
8471 | tree n_elts = NULL_TREE; | |
8472 | ||
8473 | for (; elts; elts = TREE_CHAIN (elts)) | |
8474 | { | |
8475 | unsigned int val = TREE_INT_CST_LOW (TREE_VALUE (elts)) << 4; | |
8476 | n_elts = tree_cons (NULL_TREE, | |
8477 | build_int_cst (inner_type, val), | |
8478 | n_elts); | |
8479 | } | |
8480 | return build_vector (rtype, nreverse (n_elts)); | |
8481 | } | |
8482 | break; | |
8483 | ||
8484 | case CODE_FOR_fmul8x16_vis: | |
8485 | case CODE_FOR_fmul8x16au_vis: | |
8486 | case CODE_FOR_fmul8x16al_vis: | |
f311c3b4 NF |
8487 | arg0 = args[0]; |
8488 | arg1 = args[1]; | |
8b0096b4 JM |
8489 | STRIP_NOPS (arg0); |
8490 | STRIP_NOPS (arg1); | |
8491 | ||
8492 | if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST) | |
8493 | { | |
8494 | tree inner_type = TREE_TYPE (rtype); | |
8495 | tree elts0 = TREE_VECTOR_CST_ELTS (arg0); | |
8496 | tree elts1 = TREE_VECTOR_CST_ELTS (arg1); | |
bbbbb16a ILT |
8497 | tree n_elts = sparc_handle_vis_mul8x16 (icode, inner_type, elts0, |
8498 | elts1); | |
8b0096b4 JM |
8499 | |
8500 | return build_vector (rtype, n_elts); | |
8501 | } | |
8502 | break; | |
8503 | ||
8504 | case CODE_FOR_fpmerge_vis: | |
f311c3b4 NF |
8505 | arg0 = args[0]; |
8506 | arg1 = args[1]; | |
8b0096b4 JM |
8507 | STRIP_NOPS (arg0); |
8508 | STRIP_NOPS (arg1); | |
8509 | ||
8510 | if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST) | |
8511 | { | |
8512 | tree elts0 = TREE_VECTOR_CST_ELTS (arg0); | |
8513 | tree elts1 = TREE_VECTOR_CST_ELTS (arg1); | |
8514 | tree n_elts = NULL_TREE; | |
8515 | ||
8516 | for (; elts0 && elts1; | |
8517 | elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1)) | |
8518 | { | |
8519 | n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts0), n_elts); | |
8520 | n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts1), n_elts); | |
8521 | } | |
8522 | ||
8523 | return build_vector (rtype, nreverse (n_elts)); | |
8524 | } | |
8525 | break; | |
8526 | ||
8527 | case CODE_FOR_pdist_vis: | |
f311c3b4 NF |
8528 | arg0 = args[0]; |
8529 | arg1 = args[1]; | |
8530 | arg2 = args[2]; | |
8b0096b4 JM |
8531 | STRIP_NOPS (arg0); |
8532 | STRIP_NOPS (arg1); | |
8533 | STRIP_NOPS (arg2); | |
8534 | ||
8535 | if (TREE_CODE (arg0) == VECTOR_CST | |
8536 | && TREE_CODE (arg1) == VECTOR_CST | |
8537 | && TREE_CODE (arg2) == INTEGER_CST) | |
8538 | { | |
8539 | int overflow = 0; | |
8540 | unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (arg2); | |
8541 | HOST_WIDE_INT high = TREE_INT_CST_HIGH (arg2); | |
8542 | tree elts0 = TREE_VECTOR_CST_ELTS (arg0); | |
8543 | tree elts1 = TREE_VECTOR_CST_ELTS (arg1); | |
8544 | ||
8545 | for (; elts0 && elts1; | |
8546 | elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1)) | |
8547 | { | |
8548 | unsigned HOST_WIDE_INT | |
8549 | low0 = TREE_INT_CST_LOW (TREE_VALUE (elts0)), | |
8550 | low1 = TREE_INT_CST_LOW (TREE_VALUE (elts1)); | |
8551 | HOST_WIDE_INT high0 = TREE_INT_CST_HIGH (TREE_VALUE (elts0)); | |
8552 | HOST_WIDE_INT high1 = TREE_INT_CST_HIGH (TREE_VALUE (elts1)); | |
8553 | ||
8554 | unsigned HOST_WIDE_INT l; | |
8555 | HOST_WIDE_INT h; | |
8556 | ||
8557 | overflow |= neg_double (low1, high1, &l, &h); | |
8558 | overflow |= add_double (low0, high0, l, h, &l, &h); | |
8559 | if (h < 0) | |
8560 | overflow |= neg_double (l, h, &l, &h); | |
8561 | ||
8562 | overflow |= add_double (low, high, l, h, &low, &high); | |
8563 | } | |
8564 | ||
8565 | gcc_assert (overflow == 0); | |
8566 | ||
8567 | return build_int_cst_wide (rtype, low, high); | |
8568 | } | |
8569 | ||
8570 | default: | |
8571 | break; | |
8572 | } | |
724d7c55 | 8573 | |
8b0096b4 JM |
8574 | return NULL_TREE; |
8575 | } | |
16f59241 | 8576 | \f |
214c6394 DM |
8577 | /* ??? This duplicates information provided to the compiler by the |
8578 | ??? scheduler description. Some day, teach genautomata to output | |
8579 | ??? the latencies and then CSE will just use that. */ | |
8580 | ||
3c50106f | 8581 | static bool |
f40751dd JH |
8582 | sparc_rtx_costs (rtx x, int code, int outer_code, int *total, |
8583 | bool speed ATTRIBUTE_UNUSED) | |
2ce04b6b | 8584 | { |
18df6de9 DM |
8585 | enum machine_mode mode = GET_MODE (x); |
8586 | bool float_mode_p = FLOAT_MODE_P (mode); | |
8587 | ||
2ce04b6b DM |
8588 | switch (code) |
8589 | { | |
18df6de9 DM |
8590 | case CONST_INT: |
8591 | if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000) | |
214c6394 | 8592 | { |
18df6de9 | 8593 | *total = 0; |
3c50106f | 8594 | return true; |
214c6394 | 8595 | } |
18df6de9 | 8596 | /* FALLTHRU */ |
214c6394 | 8597 | |
18df6de9 DM |
8598 | case HIGH: |
8599 | *total = 2; | |
8600 | return true; | |
214c6394 | 8601 | |
18df6de9 DM |
8602 | case CONST: |
8603 | case LABEL_REF: | |
8604 | case SYMBOL_REF: | |
8605 | *total = 4; | |
8606 | return true; | |
214c6394 | 8607 | |
18df6de9 | 8608 | case CONST_DOUBLE: |
ca075703 DM |
8609 | if (GET_MODE (x) == VOIDmode |
8610 | && ((CONST_DOUBLE_HIGH (x) == 0 | |
8611 | && CONST_DOUBLE_LOW (x) < 0x1000) | |
8612 | || (CONST_DOUBLE_HIGH (x) == -1 | |
8613 | && CONST_DOUBLE_LOW (x) < 0 | |
8614 | && CONST_DOUBLE_LOW (x) >= -0x1000))) | |
18df6de9 DM |
8615 | *total = 0; |
8616 | else | |
8617 | *total = 8; | |
3c50106f | 8618 | return true; |
214c6394 | 8619 | |
18df6de9 DM |
8620 | case MEM: |
8621 | /* If outer-code was a sign or zero extension, a cost | |
8622 | of COSTS_N_INSNS (1) was already added in. This is | |
8623 | why we are subtracting it back out. */ | |
8624 | if (outer_code == ZERO_EXTEND) | |
214c6394 | 8625 | { |
18df6de9 | 8626 | *total = sparc_costs->int_zload - COSTS_N_INSNS (1); |
214c6394 | 8627 | } |
18df6de9 | 8628 | else if (outer_code == SIGN_EXTEND) |
3c50106f | 8629 | { |
18df6de9 | 8630 | *total = sparc_costs->int_sload - COSTS_N_INSNS (1); |
3c50106f | 8631 | } |
18df6de9 | 8632 | else if (float_mode_p) |
3c50106f | 8633 | { |
18df6de9 | 8634 | *total = sparc_costs->float_load; |
3c50106f | 8635 | } |
18df6de9 | 8636 | else |
3c50106f | 8637 | { |
18df6de9 | 8638 | *total = sparc_costs->int_load; |
3c50106f | 8639 | } |
214c6394 | 8640 | |
3c50106f | 8641 | return true; |
2ce04b6b | 8642 | |
18df6de9 DM |
8643 | case PLUS: |
8644 | case MINUS: | |
8645 | if (float_mode_p) | |
8646 | *total = sparc_costs->float_plusminus; | |
8647 | else | |
8648 | *total = COSTS_N_INSNS (1); | |
8649 | return false; | |
214c6394 | 8650 | |
18df6de9 DM |
8651 | case MULT: |
8652 | if (float_mode_p) | |
8653 | *total = sparc_costs->float_mul; | |
e08eb33c | 8654 | else if (! TARGET_HARD_MUL) |
bf6c40e9 | 8655 | *total = COSTS_N_INSNS (25); |
18df6de9 DM |
8656 | else |
8657 | { | |
8658 | int bit_cost; | |
214c6394 | 8659 | |
18df6de9 DM |
8660 | bit_cost = 0; |
8661 | if (sparc_costs->int_mul_bit_factor) | |
8662 | { | |
8663 | int nbits; | |
214c6394 | 8664 | |
18df6de9 DM |
8665 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) |
8666 | { | |
8667 | unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1)); | |
8668 | for (nbits = 0; value != 0; value &= value - 1) | |
8669 | nbits++; | |
8670 | } | |
8671 | else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
ca075703 | 8672 | && GET_MODE (XEXP (x, 1)) == VOIDmode) |
18df6de9 DM |
8673 | { |
8674 | rtx x1 = XEXP (x, 1); | |
ca075703 DM |
8675 | unsigned HOST_WIDE_INT value1 = CONST_DOUBLE_LOW (x1); |
8676 | unsigned HOST_WIDE_INT value2 = CONST_DOUBLE_HIGH (x1); | |
18df6de9 DM |
8677 | |
8678 | for (nbits = 0; value1 != 0; value1 &= value1 - 1) | |
8679 | nbits++; | |
8680 | for (; value2 != 0; value2 &= value2 - 1) | |
8681 | nbits++; | |
8682 | } | |
214c6394 | 8683 | else |
18df6de9 | 8684 | nbits = 7; |
214c6394 | 8685 | |
18df6de9 DM |
8686 | if (nbits < 3) |
8687 | nbits = 3; | |
8688 | bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor; | |
ffe384ff | 8689 | bit_cost = COSTS_N_INSNS (bit_cost); |
214c6394 | 8690 | } |
18df6de9 DM |
8691 | |
8692 | if (mode == DImode) | |
ffe384ff | 8693 | *total = sparc_costs->int_mulX + bit_cost; |
18df6de9 | 8694 | else |
ffe384ff | 8695 | *total = sparc_costs->int_mul + bit_cost; |
214c6394 | 8696 | } |
18df6de9 | 8697 | return false; |
214c6394 | 8698 | |
18df6de9 DM |
8699 | case ASHIFT: |
8700 | case ASHIFTRT: | |
8701 | case LSHIFTRT: | |
8702 | *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty; | |
8703 | return false; | |
2ce04b6b | 8704 | |
18df6de9 DM |
8705 | case DIV: |
8706 | case UDIV: | |
8707 | case MOD: | |
8708 | case UMOD: | |
8709 | if (float_mode_p) | |
214c6394 | 8710 | { |
18df6de9 DM |
8711 | if (mode == DFmode) |
8712 | *total = sparc_costs->float_div_df; | |
214c6394 | 8713 | else |
18df6de9 | 8714 | *total = sparc_costs->float_div_sf; |
214c6394 | 8715 | } |
18df6de9 | 8716 | else |
214c6394 | 8717 | { |
18df6de9 DM |
8718 | if (mode == DImode) |
8719 | *total = sparc_costs->int_divX; | |
214c6394 | 8720 | else |
18df6de9 | 8721 | *total = sparc_costs->int_div; |
214c6394 | 8722 | } |
18df6de9 | 8723 | return false; |
2ce04b6b | 8724 | |
18df6de9 DM |
8725 | case NEG: |
8726 | if (! float_mode_p) | |
3c50106f | 8727 | { |
18df6de9 DM |
8728 | *total = COSTS_N_INSNS (1); |
8729 | return false; | |
3c50106f | 8730 | } |
5efb1046 | 8731 | /* FALLTHRU */ |
2ce04b6b | 8732 | |
18df6de9 DM |
8733 | case ABS: |
8734 | case FLOAT: | |
8735 | case UNSIGNED_FLOAT: | |
8736 | case FIX: | |
8737 | case UNSIGNED_FIX: | |
8738 | case FLOAT_EXTEND: | |
8739 | case FLOAT_TRUNCATE: | |
8740 | *total = sparc_costs->float_move; | |
8741 | return false; | |
2ce04b6b | 8742 | |
18df6de9 DM |
8743 | case SQRT: |
8744 | if (mode == DFmode) | |
8745 | *total = sparc_costs->float_sqrt_df; | |
8746 | else | |
8747 | *total = sparc_costs->float_sqrt_sf; | |
8748 | return false; | |
2ce04b6b | 8749 | |
18df6de9 DM |
8750 | case COMPARE: |
8751 | if (float_mode_p) | |
8752 | *total = sparc_costs->float_cmp; | |
3c50106f | 8753 | else |
18df6de9 DM |
8754 | *total = COSTS_N_INSNS (1); |
8755 | return false; | |
8756 | ||
8757 | case IF_THEN_ELSE: | |
8758 | if (float_mode_p) | |
8759 | *total = sparc_costs->float_cmove; | |
8760 | else | |
8761 | *total = sparc_costs->int_cmove; | |
8762 | return false; | |
2ce04b6b | 8763 | |
893e18a5 JM |
8764 | case IOR: |
8765 | /* Handle the NAND vector patterns. */ | |
8766 | if (sparc_vector_mode_supported_p (GET_MODE (x)) | |
8767 | && GET_CODE (XEXP (x, 0)) == NOT | |
8768 | && GET_CODE (XEXP (x, 1)) == NOT) | |
8769 | { | |
8770 | *total = COSTS_N_INSNS (1); | |
8771 | return true; | |
8772 | } | |
8773 | else | |
8774 | return false; | |
8775 | ||
2ce04b6b | 8776 | default: |
3c50106f RH |
8777 | return false; |
8778 | } | |
2ce04b6b | 8779 | } |
fb49053f | 8780 | |
68ba34f3 AS |
8781 | /* Emit the sequence of insns SEQ while preserving the registers REG and REG2. |
8782 | This is achieved by means of a manual dynamic stack space allocation in | |
8783 | the current frame. We make the assumption that SEQ doesn't contain any | |
8784 | function calls, with the possible exception of calls to the PIC helper. */ | |
951661a1 EB |
8785 | |
8786 | static void | |
1b970c28 | 8787 | emit_and_preserve (rtx seq, rtx reg, rtx reg2) |
951661a1 | 8788 | { |
68ba34f3 AS |
8789 | /* We must preserve the lowest 16 words for the register save area. */ |
8790 | HOST_WIDE_INT offset = 16*UNITS_PER_WORD; | |
8791 | /* We really need only 2 words of fresh stack space. */ | |
8792 | HOST_WIDE_INT size = SPARC_STACK_ALIGN (offset + 2*UNITS_PER_WORD); | |
951661a1 | 8793 | |
68ba34f3 AS |
8794 | rtx slot |
8795 | = gen_rtx_MEM (word_mode, plus_constant (stack_pointer_rtx, | |
8796 | SPARC_STACK_BIAS + offset)); | |
8797 | ||
8798 | emit_insn (gen_stack_pointer_dec (GEN_INT (size))); | |
951661a1 | 8799 | emit_insn (gen_rtx_SET (VOIDmode, slot, reg)); |
1b970c28 EB |
8800 | if (reg2) |
8801 | emit_insn (gen_rtx_SET (VOIDmode, | |
8802 | adjust_address (slot, word_mode, UNITS_PER_WORD), | |
8803 | reg2)); | |
951661a1 | 8804 | emit_insn (seq); |
1b970c28 EB |
8805 | if (reg2) |
8806 | emit_insn (gen_rtx_SET (VOIDmode, | |
8807 | reg2, | |
8808 | adjust_address (slot, word_mode, UNITS_PER_WORD))); | |
951661a1 | 8809 | emit_insn (gen_rtx_SET (VOIDmode, reg, slot)); |
68ba34f3 | 8810 | emit_insn (gen_stack_pointer_inc (GEN_INT (size))); |
951661a1 EB |
8811 | } |
8812 | ||
b9bf58e5 EB |
8813 | /* Output the assembler code for a thunk function. THUNK_DECL is the |
8814 | declaration for the thunk function itself, FUNCTION is the decl for | |
8815 | the target function. DELTA is an immediate constant offset to be | |
8816 | added to THIS. If VCALL_OFFSET is nonzero, the word at address | |
8817 | (*THIS + VCALL_OFFSET) should be additionally added to THIS. */ | |
e133041b | 8818 | |
c590b625 | 8819 | static void |
fc27d102 | 8820 | sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
b9bf58e5 | 8821 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, |
fc27d102 | 8822 | tree function) |
e133041b | 8823 | { |
0a2aaacc | 8824 | rtx this_rtx, insn, funexp; |
951661a1 | 8825 | unsigned int int_arg_first; |
e133041b RH |
8826 | |
8827 | reload_completed = 1; | |
fe3ad572 | 8828 | epilogue_completed = 1; |
e133041b | 8829 | |
2e040219 | 8830 | emit_note (NOTE_INSN_PROLOGUE_END); |
e133041b | 8831 | |
951661a1 EB |
8832 | if (flag_delayed_branch) |
8833 | { | |
8834 | /* We will emit a regular sibcall below, so we need to instruct | |
8835 | output_sibcall that we are in a leaf function. */ | |
22d66adf | 8836 | sparc_leaf_function_p = current_function_uses_only_leaf_regs = 1; |
951661a1 EB |
8837 | |
8838 | /* This will cause final.c to invoke leaf_renumber_regs so we | |
8839 | must behave as if we were in a not-yet-leafified function. */ | |
8840 | int_arg_first = SPARC_INCOMING_INT_ARG_FIRST; | |
8841 | } | |
8842 | else | |
8843 | { | |
8844 | /* We will emit the sibcall manually below, so we will need to | |
8845 | manually spill non-leaf registers. */ | |
22d66adf | 8846 | sparc_leaf_function_p = current_function_uses_only_leaf_regs = 0; |
951661a1 EB |
8847 | |
8848 | /* We really are in a leaf function. */ | |
8849 | int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST; | |
8850 | } | |
8851 | ||
e133041b RH |
8852 | /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function |
8853 | returns a structure, the structure return pointer is there instead. */ | |
4900aa61 EB |
8854 | if (TARGET_ARCH64 |
8855 | && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
0a2aaacc | 8856 | this_rtx = gen_rtx_REG (Pmode, int_arg_first + 1); |
e133041b | 8857 | else |
0a2aaacc | 8858 | this_rtx = gen_rtx_REG (Pmode, int_arg_first); |
e133041b RH |
8859 | |
8860 | /* Add DELTA. When possible use a plain add, otherwise load it into | |
8861 | a register first. */ | |
b9bf58e5 | 8862 | if (delta) |
e133041b | 8863 | { |
b9bf58e5 EB |
8864 | rtx delta_rtx = GEN_INT (delta); |
8865 | ||
8866 | if (! SPARC_SIMM13_P (delta)) | |
8867 | { | |
8868 | rtx scratch = gen_rtx_REG (Pmode, 1); | |
8869 | emit_move_insn (scratch, delta_rtx); | |
8870 | delta_rtx = scratch; | |
8871 | } | |
8872 | ||
0a2aaacc KG |
8873 | /* THIS_RTX += DELTA. */ |
8874 | emit_insn (gen_add2_insn (this_rtx, delta_rtx)); | |
b9bf58e5 EB |
8875 | } |
8876 | ||
0a2aaacc | 8877 | /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */ |
b9bf58e5 EB |
8878 | if (vcall_offset) |
8879 | { | |
8880 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); | |
e133041b | 8881 | rtx scratch = gen_rtx_REG (Pmode, 1); |
ed1fe829 | 8882 | |
f5f7d171 | 8883 | gcc_assert (vcall_offset < 0); |
b9bf58e5 | 8884 | |
0a2aaacc KG |
8885 | /* SCRATCH = *THIS_RTX. */ |
8886 | emit_move_insn (scratch, gen_rtx_MEM (Pmode, this_rtx)); | |
b9bf58e5 EB |
8887 | |
8888 | /* Prepare for adding VCALL_OFFSET. The difficulty is that we | |
8889 | may not have any available scratch register at this point. */ | |
8890 | if (SPARC_SIMM13_P (vcall_offset)) | |
8891 | ; | |
8892 | /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */ | |
8893 | else if (! fixed_regs[5] | |
8894 | /* The below sequence is made up of at least 2 insns, | |
8895 | while the default method may need only one. */ | |
8896 | && vcall_offset < -8192) | |
8897 | { | |
8898 | rtx scratch2 = gen_rtx_REG (Pmode, 5); | |
8899 | emit_move_insn (scratch2, vcall_offset_rtx); | |
8900 | vcall_offset_rtx = scratch2; | |
8901 | } | |
e133041b | 8902 | else |
ed1fe829 | 8903 | { |
b9bf58e5 EB |
8904 | rtx increment = GEN_INT (-4096); |
8905 | ||
8906 | /* VCALL_OFFSET is a negative number whose typical range can be | |
8907 | estimated as -32768..0 in 32-bit mode. In almost all cases | |
8908 | it is therefore cheaper to emit multiple add insns than | |
8909 | spilling and loading the constant into a register (at least | |
8910 | 6 insns). */ | |
8911 | while (! SPARC_SIMM13_P (vcall_offset)) | |
8912 | { | |
8913 | emit_insn (gen_add2_insn (scratch, increment)); | |
8914 | vcall_offset += 4096; | |
8915 | } | |
8916 | vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */ | |
ed1fe829 EB |
8917 | } |
8918 | ||
0a2aaacc | 8919 | /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */ |
b9bf58e5 EB |
8920 | emit_move_insn (scratch, gen_rtx_MEM (Pmode, |
8921 | gen_rtx_PLUS (Pmode, | |
8922 | scratch, | |
8923 | vcall_offset_rtx))); | |
e133041b | 8924 | |
0a2aaacc KG |
8925 | /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */ |
8926 | emit_insn (gen_add2_insn (this_rtx, scratch)); | |
b9bf58e5 | 8927 | } |
e133041b RH |
8928 | |
8929 | /* Generate a tail call to the target function. */ | |
8930 | if (! TREE_USED (function)) | |
8931 | { | |
8932 | assemble_external (function); | |
8933 | TREE_USED (function) = 1; | |
8934 | } | |
8935 | funexp = XEXP (DECL_RTL (function), 0); | |
951661a1 EB |
8936 | |
8937 | if (flag_delayed_branch) | |
8938 | { | |
8939 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); | |
8940 | insn = emit_call_insn (gen_sibcall (funexp)); | |
8941 | SIBLING_CALL_P (insn) = 1; | |
8942 | } | |
8943 | else | |
8944 | { | |
8945 | /* The hoops we have to jump through in order to generate a sibcall | |
8946 | without using delay slots... */ | |
1b970c28 | 8947 | rtx spill_reg, spill_reg2, seq, scratch = gen_rtx_REG (Pmode, 1); |
951661a1 EB |
8948 | |
8949 | if (flag_pic) | |
8950 | { | |
8951 | spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */ | |
1b970c28 | 8952 | spill_reg2 = gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM); |
951661a1 | 8953 | start_sequence (); |
5e77eb53 EB |
8954 | /* Delay emitting the PIC helper function because it needs to |
8955 | change the section and we are emitting assembly code. */ | |
9fd52c6c | 8956 | load_pic_register (); /* clobbers %o7 */ |
208384fd | 8957 | scratch = legitimize_pic_address (funexp, scratch); |
951661a1 EB |
8958 | seq = get_insns (); |
8959 | end_sequence (); | |
1b970c28 | 8960 | emit_and_preserve (seq, spill_reg, spill_reg2); |
951661a1 EB |
8961 | } |
8962 | else if (TARGET_ARCH32) | |
8963 | { | |
8964 | emit_insn (gen_rtx_SET (VOIDmode, | |
8965 | scratch, | |
8966 | gen_rtx_HIGH (SImode, funexp))); | |
8967 | emit_insn (gen_rtx_SET (VOIDmode, | |
8968 | scratch, | |
8969 | gen_rtx_LO_SUM (SImode, scratch, funexp))); | |
8970 | } | |
8971 | else /* TARGET_ARCH64 */ | |
8972 | { | |
8973 | switch (sparc_cmodel) | |
8974 | { | |
8975 | case CM_MEDLOW: | |
8976 | case CM_MEDMID: | |
8977 | /* The destination can serve as a temporary. */ | |
8978 | sparc_emit_set_symbolic_const64 (scratch, funexp, scratch); | |
8979 | break; | |
8980 | ||
8981 | case CM_MEDANY: | |
8982 | case CM_EMBMEDANY: | |
8983 | /* The destination cannot serve as a temporary. */ | |
8984 | spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */ | |
8985 | start_sequence (); | |
8986 | sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg); | |
8987 | seq = get_insns (); | |
8988 | end_sequence (); | |
1b970c28 | 8989 | emit_and_preserve (seq, spill_reg, 0); |
951661a1 EB |
8990 | break; |
8991 | ||
8992 | default: | |
f5f7d171 | 8993 | gcc_unreachable (); |
951661a1 EB |
8994 | } |
8995 | } | |
8996 | ||
8997 | emit_jump_insn (gen_indirect_jump (scratch)); | |
8998 | } | |
8999 | ||
e133041b RH |
9000 | emit_barrier (); |
9001 | ||
9002 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
9003 | There's not really enough bulk here to make other passes such as | |
9004 | instruction scheduling worth while. Note that use_thunk calls | |
9005 | assemble_start_function and assemble_end_function. */ | |
9006 | insn = get_insns (); | |
55e092c4 | 9007 | insn_locators_alloc (); |
e133041b RH |
9008 | shorten_branches (insn); |
9009 | final_start_function (insn, file, 1); | |
c9d691e9 | 9010 | final (insn, file, 1); |
e133041b RH |
9011 | final_end_function (); |
9012 | ||
9013 | reload_completed = 0; | |
fe3ad572 | 9014 | epilogue_completed = 0; |
e133041b | 9015 | } |
e2500fed | 9016 | |
b9bf58e5 EB |
9017 | /* Return true if sparc_output_mi_thunk would be able to output the |
9018 | assembler code for the thunk function specified by the arguments | |
9019 | it is passed, and false otherwise. */ | |
9020 | static bool | |
3101faab | 9021 | sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED, |
b9bf58e5 EB |
9022 | HOST_WIDE_INT delta ATTRIBUTE_UNUSED, |
9023 | HOST_WIDE_INT vcall_offset, | |
3101faab | 9024 | const_tree function ATTRIBUTE_UNUSED) |
b9bf58e5 EB |
9025 | { |
9026 | /* Bound the loop used in the default method above. */ | |
9027 | return (vcall_offset >= -32768 || ! fixed_regs[5]); | |
9028 | } | |
9029 | ||
5751a10b JJ |
9030 | /* How to allocate a 'struct machine_function'. */ |
9031 | ||
9032 | static struct machine_function * | |
9033 | sparc_init_machine_status (void) | |
9034 | { | |
a9429e29 | 9035 | return ggc_alloc_cleared_machine_function (); |
5751a10b JJ |
9036 | } |
9037 | ||
9038 | /* Locate some local-dynamic symbol still in use by this function | |
9039 | so that we can print its name in local-dynamic base patterns. */ | |
9040 | ||
9041 | static const char * | |
9042 | get_some_local_dynamic_name (void) | |
9043 | { | |
9044 | rtx insn; | |
9045 | ||
9046 | if (cfun->machine->some_ld_name) | |
9047 | return cfun->machine->some_ld_name; | |
9048 | ||
9049 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
9050 | if (INSN_P (insn) | |
9051 | && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0)) | |
9052 | return cfun->machine->some_ld_name; | |
9053 | ||
f5f7d171 | 9054 | gcc_unreachable (); |
5751a10b JJ |
9055 | } |
9056 | ||
9057 | static int | |
9058 | get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) | |
9059 | { | |
9060 | rtx x = *px; | |
9061 | ||
9062 | if (x | |
9063 | && GET_CODE (x) == SYMBOL_REF | |
9064 | && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
9065 | { | |
9066 | cfun->machine->some_ld_name = XSTR (x, 0); | |
9067 | return 1; | |
9068 | } | |
9069 | ||
9070 | return 0; | |
9071 | } | |
9072 | ||
e54c7471 EB |
9073 | /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook. |
9074 | This is called from dwarf2out.c to emit call frame instructions | |
9075 | for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */ | |
9076 | static void | |
9077 | sparc_dwarf_handle_frame_unspec (const char *label, | |
9078 | rtx pattern ATTRIBUTE_UNUSED, | |
9079 | int index ATTRIBUTE_UNUSED) | |
9080 | { | |
9081 | gcc_assert (index == UNSPECV_SAVEW); | |
9082 | dwarf2out_window_save (label); | |
9083 | } | |
9084 | ||
fdbe66f2 | 9085 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
5751a10b JJ |
9086 | We need to emit DTP-relative relocations. */ |
9087 | ||
fdbe66f2 | 9088 | static void |
5751a10b JJ |
9089 | sparc_output_dwarf_dtprel (FILE *file, int size, rtx x) |
9090 | { | |
9091 | switch (size) | |
9092 | { | |
9093 | case 4: | |
9094 | fputs ("\t.word\t%r_tls_dtpoff32(", file); | |
9095 | break; | |
9096 | case 8: | |
9097 | fputs ("\t.xword\t%r_tls_dtpoff64(", file); | |
9098 | break; | |
9099 | default: | |
f5f7d171 | 9100 | gcc_unreachable (); |
5751a10b JJ |
9101 | } |
9102 | output_addr_const (file, x); | |
9103 | fputs (")", file); | |
9104 | } | |
9105 | ||
fdbe66f2 EB |
9106 | /* Do whatever processing is required at the end of a file. */ |
9107 | ||
9108 | static void | |
9109 | sparc_file_end (void) | |
5e77eb53 | 9110 | { |
9fd52c6c DM |
9111 | /* If need to emit the special PIC helper function, do so now. */ |
9112 | if (pic_helper_needed) | |
9113 | { | |
9114 | unsigned int regno = REGNO (pic_offset_table_rtx); | |
9115 | const char *pic_name = reg_names[regno]; | |
9116 | char name[32]; | |
9117 | #ifdef DWARF2_UNWIND_INFO | |
9118 | bool do_cfi; | |
9119 | #endif | |
9120 | ||
9121 | get_pc_thunk_name (name, regno); | |
9122 | if (USE_HIDDEN_LINKONCE) | |
9123 | { | |
9124 | tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, | |
9125 | get_identifier (name), | |
9126 | build_function_type (void_type_node, | |
9127 | void_list_node)); | |
9128 | DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL, | |
9129 | NULL_TREE, void_type_node); | |
9130 | TREE_STATIC (decl) = 1; | |
9131 | make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl)); | |
9132 | DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; | |
9133 | DECL_VISIBILITY_SPECIFIED (decl) = 1; | |
9134 | allocate_struct_function (decl, true); | |
9135 | current_function_decl = decl; | |
9136 | init_varasm_status (); | |
9137 | assemble_start_function (decl, name); | |
9138 | } | |
9139 | else | |
9140 | { | |
9141 | const int align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
9142 | switch_to_section (text_section); | |
9143 | if (align > 0) | |
9144 | ASM_OUTPUT_ALIGN (asm_out_file, align); | |
9145 | ASM_OUTPUT_LABEL (asm_out_file, name); | |
9146 | } | |
9147 | ||
9148 | #ifdef DWARF2_UNWIND_INFO | |
9149 | do_cfi = dwarf2out_do_cfi_asm (); | |
9150 | if (do_cfi) | |
9151 | fprintf (asm_out_file, "\t.cfi_startproc\n"); | |
9152 | #endif | |
9153 | if (flag_delayed_branch) | |
9154 | fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n", | |
9155 | pic_name, pic_name); | |
9156 | else | |
9157 | fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n", | |
9158 | pic_name, pic_name); | |
9159 | #ifdef DWARF2_UNWIND_INFO | |
9160 | if (do_cfi) | |
9161 | fprintf (asm_out_file, "\t.cfi_endproc\n"); | |
9162 | #endif | |
9163 | } | |
5e77eb53 EB |
9164 | |
9165 | if (NEED_INDICATE_EXEC_STACK) | |
9166 | file_end_indicate_exec_stack (); | |
9167 | } | |
9168 | ||
7269aee7 | 9169 | #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING |
608063c3 | 9170 | /* Implement TARGET_MANGLE_TYPE. */ |
7269aee7 AH |
9171 | |
9172 | static const char * | |
3101faab | 9173 | sparc_mangle_type (const_tree type) |
7269aee7 AH |
9174 | { |
9175 | if (!TARGET_64BIT | |
9176 | && TYPE_MAIN_VARIANT (type) == long_double_type_node | |
9177 | && TARGET_LONG_DOUBLE_128) | |
9178 | return "g"; | |
9179 | ||
9180 | /* For all other types, use normal C++ mangling. */ | |
9181 | return NULL; | |
9182 | } | |
9183 | #endif | |
9184 | ||
396b535a JJ |
9185 | /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit |
9186 | compare and swap on the word containing the byte or half-word. */ | |
9187 | ||
9188 | void | |
9189 | sparc_expand_compare_and_swap_12 (rtx result, rtx mem, rtx oldval, rtx newval) | |
9190 | { | |
9191 | rtx addr1 = force_reg (Pmode, XEXP (mem, 0)); | |
9192 | rtx addr = gen_reg_rtx (Pmode); | |
9193 | rtx off = gen_reg_rtx (SImode); | |
9194 | rtx oldv = gen_reg_rtx (SImode); | |
9195 | rtx newv = gen_reg_rtx (SImode); | |
9196 | rtx oldvalue = gen_reg_rtx (SImode); | |
9197 | rtx newvalue = gen_reg_rtx (SImode); | |
9198 | rtx res = gen_reg_rtx (SImode); | |
9199 | rtx resv = gen_reg_rtx (SImode); | |
9200 | rtx memsi, val, mask, end_label, loop_label, cc; | |
9201 | ||
9202 | emit_insn (gen_rtx_SET (VOIDmode, addr, | |
9203 | gen_rtx_AND (Pmode, addr1, GEN_INT (-4)))); | |
9204 | ||
9205 | if (Pmode != SImode) | |
9206 | addr1 = gen_lowpart (SImode, addr1); | |
9207 | emit_insn (gen_rtx_SET (VOIDmode, off, | |
9208 | gen_rtx_AND (SImode, addr1, GEN_INT (3)))); | |
9209 | ||
9210 | memsi = gen_rtx_MEM (SImode, addr); | |
44d64274 | 9211 | set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER); |
396b535a JJ |
9212 | MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem); |
9213 | ||
9214 | val = force_reg (SImode, memsi); | |
9215 | ||
9216 | emit_insn (gen_rtx_SET (VOIDmode, off, | |
9217 | gen_rtx_XOR (SImode, off, | |
9218 | GEN_INT (GET_MODE (mem) == QImode | |
9219 | ? 3 : 2)))); | |
9220 | ||
9221 | emit_insn (gen_rtx_SET (VOIDmode, off, | |
9222 | gen_rtx_ASHIFT (SImode, off, GEN_INT (3)))); | |
9223 | ||
9224 | if (GET_MODE (mem) == QImode) | |
9225 | mask = force_reg (SImode, GEN_INT (0xff)); | |
9226 | else | |
9227 | mask = force_reg (SImode, GEN_INT (0xffff)); | |
9228 | ||
9229 | emit_insn (gen_rtx_SET (VOIDmode, mask, | |
9230 | gen_rtx_ASHIFT (SImode, mask, off))); | |
9231 | ||
9232 | emit_insn (gen_rtx_SET (VOIDmode, val, | |
9233 | gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask), | |
9234 | val))); | |
9235 | ||
9236 | oldval = gen_lowpart (SImode, oldval); | |
9237 | emit_insn (gen_rtx_SET (VOIDmode, oldv, | |
9238 | gen_rtx_ASHIFT (SImode, oldval, off))); | |
9239 | ||
9240 | newval = gen_lowpart_common (SImode, newval); | |
9241 | emit_insn (gen_rtx_SET (VOIDmode, newv, | |
9242 | gen_rtx_ASHIFT (SImode, newval, off))); | |
9243 | ||
9244 | emit_insn (gen_rtx_SET (VOIDmode, oldv, | |
9245 | gen_rtx_AND (SImode, oldv, mask))); | |
9246 | ||
9247 | emit_insn (gen_rtx_SET (VOIDmode, newv, | |
9248 | gen_rtx_AND (SImode, newv, mask))); | |
9249 | ||
9250 | end_label = gen_label_rtx (); | |
9251 | loop_label = gen_label_rtx (); | |
9252 | emit_label (loop_label); | |
9253 | ||
9254 | emit_insn (gen_rtx_SET (VOIDmode, oldvalue, | |
9255 | gen_rtx_IOR (SImode, oldv, val))); | |
9256 | ||
9257 | emit_insn (gen_rtx_SET (VOIDmode, newvalue, | |
9258 | gen_rtx_IOR (SImode, newv, val))); | |
9259 | ||
9260 | emit_insn (gen_sync_compare_and_swapsi (res, memsi, oldvalue, newvalue)); | |
9261 | ||
9262 | emit_cmp_and_jump_insns (res, oldvalue, EQ, NULL, SImode, 0, end_label); | |
9263 | ||
9264 | emit_insn (gen_rtx_SET (VOIDmode, resv, | |
9265 | gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask), | |
9266 | res))); | |
9267 | ||
f90b7a5a | 9268 | cc = gen_compare_reg_1 (NE, resv, val); |
396b535a JJ |
9269 | emit_insn (gen_rtx_SET (VOIDmode, val, resv)); |
9270 | ||
f90b7a5a PB |
9271 | /* Use cbranchcc4 to separate the compare and branch! */ |
9272 | emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode, cc, const0_rtx), | |
9273 | cc, const0_rtx, loop_label)); | |
396b535a JJ |
9274 | |
9275 | emit_label (end_label); | |
9276 | ||
9277 | emit_insn (gen_rtx_SET (VOIDmode, res, | |
9278 | gen_rtx_AND (SImode, res, mask))); | |
9279 | ||
9280 | emit_insn (gen_rtx_SET (VOIDmode, res, | |
9281 | gen_rtx_LSHIFTRT (SImode, res, off))); | |
9282 | ||
9283 | emit_move_insn (result, gen_lowpart (GET_MODE (result), res)); | |
9284 | } | |
9285 | ||
b52b1749 AS |
9286 | /* Implement TARGET_FRAME_POINTER_REQUIRED. */ |
9287 | ||
9288 | bool | |
9289 | sparc_frame_pointer_required (void) | |
9290 | { | |
9291 | return !(leaf_function_p () && only_leaf_regs_used ()); | |
9292 | } | |
9293 | ||
9294 | /* The way this is structured, we can't eliminate SFP in favor of SP | |
9295 | if the frame pointer is required: we want to use the SFP->HFP elimination | |
9296 | in that case. But the test in update_eliminables doesn't know we are | |
9297 | assuming below that we only do the former elimination. */ | |
9298 | ||
9299 | bool | |
9300 | sparc_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
9301 | { | |
4900aa61 | 9302 | return (to == HARD_FRAME_POINTER_REGNUM |
b52b1749 AS |
9303 | || !targetm.frame_pointer_required ()); |
9304 | } | |
9305 | ||
e2500fed | 9306 | #include "gt-sparc.h" |