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ab835497 | 1 | /* Subroutines for insn-output.c for Sun SPARC. |
4592bdcb | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
ae46c4e0 | 3 | 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
ab835497 | 4 | Contributed by Michael Tiemann (tiemann@cygnus.com) |
61a55e8b DE |
5 | 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
6 | at Cygnus Support. | |
ab835497 RK |
7 | |
8 | This file is part of GNU CC. | |
9 | ||
10 | GNU CC is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GNU CC is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, |
23 | Boston, MA 02111-1307, USA. */ | |
ab835497 | 24 | |
ab835497 | 25 | #include "config.h" |
284d86e9 | 26 | #include "system.h" |
210aa14a | 27 | #include "tree.h" |
ab835497 RK |
28 | #include "rtl.h" |
29 | #include "regs.h" | |
30 | #include "hard-reg-set.h" | |
31 | #include "real.h" | |
32 | #include "insn-config.h" | |
33 | #include "conditions.h" | |
ab835497 RK |
34 | #include "output.h" |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
49ad7cfa | 37 | #include "function.h" |
ab835497 | 38 | #include "expr.h" |
e78d8e51 ZW |
39 | #include "optabs.h" |
40 | #include "libfuncs.h" | |
ab835497 | 41 | #include "recog.h" |
487a6e06 | 42 | #include "toplev.h" |
d07d525a | 43 | #include "ggc.h" |
b1474bb7 | 44 | #include "tm_p.h" |
e78d8e51 | 45 | #include "debug.h" |
672a6f42 NB |
46 | #include "target.h" |
47 | #include "target-def.h" | |
ab835497 | 48 | |
61a55e8b DE |
49 | /* 1 if the caller has placed an "unimp" insn immediately after the call. |
50 | This is used in v8 code when calling a function that returns a structure. | |
06b967f9 RK |
51 | v9 doesn't have this. Be careful to have this test be the same as that |
52 | used on the call. */ | |
53 | ||
54 | #define SKIP_CALLERS_UNIMP_P \ | |
55 | (!TARGET_ARCH64 && current_function_returns_struct \ | |
56 | && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
57 | && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
58 | == INTEGER_CST)) | |
61a55e8b | 59 | |
ab835497 RK |
60 | /* Global variables for machine-dependent things. */ |
61 | ||
61a55e8b DE |
62 | /* Size of frame. Need to know this to emit return insns from leaf procedures. |
63 | ACTUAL_FSIZE is set by compute_frame_size() which is called during the | |
64 | reload pass. This is important as the value is later used in insn | |
65 | scheduling (to see what can go in a delay slot). | |
66 | APPARENT_FSIZE is the size of the stack less the register save area and less | |
67 | the outgoing argument area. It is used when saving call preserved regs. */ | |
68 | static int apparent_fsize; | |
69 | static int actual_fsize; | |
70 | ||
33074e5f RH |
71 | /* Number of live general or floating point registers needed to be |
72 | saved (as 4-byte quantities). */ | |
e48addee JJ |
73 | static int num_gfregs; |
74 | ||
ab835497 RK |
75 | /* Save the operands last given to a compare for use when we |
76 | generate a scc or bcc insn. */ | |
ab835497 RK |
77 | rtx sparc_compare_op0, sparc_compare_op1; |
78 | ||
33074e5f RH |
79 | /* Coordinate with the md file wrt special insns created by |
80 | sparc_nonflat_function_epilogue. */ | |
81 | bool sparc_emitting_epilogue; | |
ab835497 | 82 | |
563c12b0 RH |
83 | /* Vector to say how input registers are mapped to output registers. |
84 | HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to | |
85 | eliminate it. You must use -fomit-frame-pointer to get that. */ | |
d70e94ec | 86 | char leaf_reg_remap[] = |
ab835497 RK |
87 | { 0, 1, 2, 3, 4, 5, 6, 7, |
88 | -1, -1, -1, -1, -1, -1, 14, -1, | |
89 | -1, -1, -1, -1, -1, -1, -1, -1, | |
90 | 8, 9, 10, 11, 12, 13, -1, 15, | |
91 | ||
92 | 32, 33, 34, 35, 36, 37, 38, 39, | |
93 | 40, 41, 42, 43, 44, 45, 46, 47, | |
94 | 48, 49, 50, 51, 52, 53, 54, 55, | |
61a55e8b DE |
95 | 56, 57, 58, 59, 60, 61, 62, 63, |
96 | 64, 65, 66, 67, 68, 69, 70, 71, | |
97 | 72, 73, 74, 75, 76, 77, 78, 79, | |
98 | 80, 81, 82, 83, 84, 85, 86, 87, | |
99 | 88, 89, 90, 91, 92, 93, 94, 95, | |
c4ce6853 | 100 | 96, 97, 98, 99, 100}; |
ab835497 | 101 | |
7d167afd JJ |
102 | /* Vector, indexed by hard register number, which contains 1 |
103 | for a register that is allowable in a candidate for leaf | |
104 | function treatment. */ | |
105 | char sparc_leaf_regs[] = | |
106 | { 1, 1, 1, 1, 1, 1, 1, 1, | |
107 | 0, 0, 0, 0, 0, 0, 1, 0, | |
108 | 0, 0, 0, 0, 0, 0, 0, 0, | |
109 | 1, 1, 1, 1, 1, 1, 0, 1, | |
110 | 1, 1, 1, 1, 1, 1, 1, 1, | |
111 | 1, 1, 1, 1, 1, 1, 1, 1, | |
112 | 1, 1, 1, 1, 1, 1, 1, 1, | |
113 | 1, 1, 1, 1, 1, 1, 1, 1, | |
114 | 1, 1, 1, 1, 1, 1, 1, 1, | |
115 | 1, 1, 1, 1, 1, 1, 1, 1, | |
116 | 1, 1, 1, 1, 1, 1, 1, 1, | |
117 | 1, 1, 1, 1, 1, 1, 1, 1, | |
118 | 1, 1, 1, 1, 1}; | |
119 | ||
ab835497 RK |
120 | /* Name of where we pretend to think the frame pointer points. |
121 | Normally, this is "%fp", but if we are in a leaf procedure, | |
61a55e8b DE |
122 | this is "%sp+something". We record "something" separately as it may be |
123 | too big for reg+constant addressing. */ | |
124 | ||
3bb5de61 | 125 | static const char *frame_base_name; |
61a55e8b | 126 | static int frame_base_offset; |
ab835497 | 127 | |
f6da8bc3 KG |
128 | static void sparc_init_modes PARAMS ((void)); |
129 | static int save_regs PARAMS ((FILE *, int, int, const char *, | |
c85f7c16 | 130 | int, int, int)); |
f6da8bc3 KG |
131 | static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int)); |
132 | static void build_big_number PARAMS ((FILE *, int, const char *)); | |
133 | static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *, | |
c85f7c16 JL |
134 | enum machine_mode, tree, int, int, |
135 | int *, int *)); | |
8947065c | 136 | |
f6da8bc3 KG |
137 | static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
138 | static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); | |
f6da8bc3 KG |
139 | |
140 | static void sparc_output_addr_vec PARAMS ((rtx)); | |
141 | static void sparc_output_addr_diff_vec PARAMS ((rtx)); | |
142 | static void sparc_output_deferred_case_vectors PARAMS ((void)); | |
143 | static void sparc_add_gc_roots PARAMS ((void)); | |
f6da8bc3 KG |
144 | static int check_return_regs PARAMS ((rtx)); |
145 | static int epilogue_renumber PARAMS ((rtx *, int)); | |
301d03af | 146 | static bool sparc_assemble_integer PARAMS ((rtx, unsigned int, int)); |
4df1190a | 147 | static int set_extends PARAMS ((rtx)); |
e77d72cb | 148 | static void output_restore_regs PARAMS ((FILE *, int)); |
08c148a8 NB |
149 | static void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
150 | static void sparc_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
151 | static void sparc_flat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
152 | static void sparc_flat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); | |
153 | static void sparc_nonflat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT, | |
154 | int)); | |
155 | static void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT, | |
156 | int)); | |
ede75ee8 | 157 | #ifdef OBJECT_FORMAT_ELF |
715bdd29 | 158 | static void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int)); |
ede75ee8 | 159 | #endif |
ae46c4e0 RH |
160 | static void sparc_aout_select_section PARAMS ((tree, int, |
161 | unsigned HOST_WIDE_INT)) | |
162 | ATTRIBUTE_UNUSED; | |
c237e94a ZW |
163 | |
164 | static int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); | |
165 | static int sparc_issue_rate PARAMS ((void)); | |
c237e94a | 166 | static void sparc_sched_init PARAMS ((FILE *, int, int)); |
fae15c93 VM |
167 | static int sparc_use_dfa_pipeline_interface PARAMS ((void)); |
168 | static int sparc_use_sched_lookahead PARAMS ((void)); | |
73985940 RH |
169 | |
170 | static void emit_soft_tfmode_libcall PARAMS ((const char *, int, rtx *)); | |
171 | static void emit_soft_tfmode_binop PARAMS ((enum rtx_code, rtx *)); | |
172 | static void emit_soft_tfmode_unop PARAMS ((enum rtx_code, rtx *)); | |
173 | static void emit_soft_tfmode_cvt PARAMS ((enum rtx_code, rtx *)); | |
174 | static void emit_hard_tfmode_operation PARAMS ((enum rtx_code, rtx *)); | |
61a55e8b DE |
175 | \f |
176 | /* Option handling. */ | |
177 | ||
a0a301fc | 178 | /* Code model option as passed by user. */ |
3bb5de61 | 179 | const char *sparc_cmodel_string; |
a0a301fc DE |
180 | /* Parsed value. */ |
181 | enum cmodel sparc_cmodel; | |
182 | ||
1cb36a98 RH |
183 | char sparc_hard_reg_printed[8]; |
184 | ||
16956f6e DE |
185 | struct sparc_cpu_select sparc_select[] = |
186 | { | |
187 | /* switch name, tune arch */ | |
188 | { (char *)0, "default", 1, 1 }, | |
189 | { (char *)0, "-mcpu=", 1, 1 }, | |
190 | { (char *)0, "-mtune=", 1, 0 }, | |
db3d4438 | 191 | { 0, 0, 0, 0 } |
16956f6e | 192 | }; |
733f53f5 | 193 | |
16956f6e DE |
194 | /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ |
195 | enum processor_type sparc_cpu; | |
672a6f42 NB |
196 | \f |
197 | /* Initialize the GCC target structure. */ | |
301d03af RS |
198 | |
199 | /* The sparc default is to use .half rather than .short for aligned | |
200 | HI objects. Use .word instead of .long on non-ELF systems. */ | |
201 | #undef TARGET_ASM_ALIGNED_HI_OP | |
202 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
203 | #ifndef OBJECT_FORMAT_ELF | |
204 | #undef TARGET_ASM_ALIGNED_SI_OP | |
205 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
206 | #endif | |
207 | ||
208 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
209 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t" | |
210 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
211 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t" | |
212 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
213 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t" | |
214 | ||
215 | /* The target hook has to handle DI-mode values. */ | |
216 | #undef TARGET_ASM_INTEGER | |
217 | #define TARGET_ASM_INTEGER sparc_assemble_integer | |
218 | ||
08c148a8 NB |
219 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
220 | #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue | |
221 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
222 | #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue | |
733f53f5 | 223 | |
c237e94a ZW |
224 | #undef TARGET_SCHED_ADJUST_COST |
225 | #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost | |
226 | #undef TARGET_SCHED_ISSUE_RATE | |
227 | #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate | |
c237e94a ZW |
228 | #undef TARGET_SCHED_INIT |
229 | #define TARGET_SCHED_INIT sparc_sched_init | |
fae15c93 VM |
230 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE |
231 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface | |
232 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD | |
233 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead | |
c237e94a | 234 | |
f6897b10 | 235 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 236 | \f |
61a55e8b DE |
237 | /* Validate and override various options, and do some machine dependent |
238 | initialization. */ | |
239 | ||
240 | void | |
241 | sparc_override_options () | |
242 | { | |
a0a301fc | 243 | static struct code_model { |
8b60264b KG |
244 | const char *const name; |
245 | const int value; | |
246 | } const cmodels[] = { | |
a0a301fc DE |
247 | { "32", CM_32 }, |
248 | { "medlow", CM_MEDLOW }, | |
249 | { "medmid", CM_MEDMID }, | |
250 | { "medany", CM_MEDANY }, | |
251 | { "embmedany", CM_EMBMEDANY }, | |
252 | { 0, 0 } | |
253 | }; | |
8b60264b | 254 | const struct code_model *cmodel; |
16956f6e | 255 | /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ |
733f53f5 | 256 | static struct cpu_default { |
8b60264b KG |
257 | const int cpu; |
258 | const char *const name; | |
259 | } const cpu_default[] = { | |
a0a301fc | 260 | /* There must be one entry here for each TARGET_CPU value. */ |
16956f6e | 261 | { TARGET_CPU_sparc, "cypress" }, |
3592ea0d | 262 | { TARGET_CPU_sparclet, "tsc701" }, |
16956f6e | 263 | { TARGET_CPU_sparclite, "f930" }, |
a0a301fc | 264 | { TARGET_CPU_v8, "v8" }, |
8947065c RH |
265 | { TARGET_CPU_hypersparc, "hypersparc" }, |
266 | { TARGET_CPU_sparclite86x, "sparclite86x" }, | |
a0a301fc DE |
267 | { TARGET_CPU_supersparc, "supersparc" }, |
268 | { TARGET_CPU_v9, "v9" }, | |
ba542005 | 269 | { TARGET_CPU_ultrasparc, "ultrasparc" }, |
fae15c93 | 270 | { TARGET_CPU_ultrasparc3, "ultrasparc3" }, |
db3d4438 | 271 | { 0, 0 } |
733f53f5 | 272 | }; |
8b60264b | 273 | const struct cpu_default *def; |
16956f6e | 274 | /* Table of values for -m{cpu,tune}=. */ |
733f53f5 | 275 | static struct cpu_table { |
8b60264b KG |
276 | const char *const name; |
277 | const enum processor_type processor; | |
278 | const int disable; | |
279 | const int enable; | |
280 | } const cpu_table[] = { | |
16956f6e DE |
281 | { "v7", PROCESSOR_V7, MASK_ISA, 0 }, |
282 | { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, | |
283 | { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, | |
733f53f5 | 284 | /* TI TMS390Z55 supersparc */ |
16956f6e DE |
285 | { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, |
286 | { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, | |
733f53f5 DE |
287 | /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. |
288 | The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ | |
16956f6e DE |
289 | { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, |
290 | { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, | |
8947065c | 291 | { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, |
d3ec6b06 VM |
292 | { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, |
293 | MASK_SPARCLITE }, | |
16956f6e | 294 | { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, |
733f53f5 | 295 | /* TEMIC sparclet */ |
3592ea0d | 296 | { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, |
16956f6e | 297 | { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, |
5cb01b65 JJ |
298 | /* TI ultrasparc I, II, IIi */ |
299 | { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 | |
300 | /* Although insns using %y are deprecated, it is a clear win on current | |
80ffc95e | 301 | ultrasparcs. */ |
3276910d | 302 | |MASK_DEPRECATED_V8_INSNS}, |
fae15c93 VM |
303 | /* TI ultrasparc III */ |
304 | /* ??? Check if %y issue still holds true in ultra3. */ | |
305 | { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, | |
db3d4438 | 306 | { 0, 0, 0, 0 } |
733f53f5 | 307 | }; |
8b60264b KG |
308 | const struct cpu_table *cpu; |
309 | const struct sparc_cpu_select *sel; | |
a0a301fc | 310 | int fpu; |
345a6161 | 311 | |
a0a301fc DE |
312 | #ifndef SPARC_BI_ARCH |
313 | /* Check for unsupported architecture size. */ | |
314 | if (! TARGET_64BIT != DEFAULT_ARCH32_P) | |
3276910d RK |
315 | error ("%s is not supported by this configuration", |
316 | DEFAULT_ARCH32_P ? "-m64" : "-m32"); | |
a0a301fc DE |
317 | #endif |
318 | ||
4710d3eb JJ |
319 | /* We force all 64bit archs to use 128 bit long double */ |
320 | if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128) | |
321 | { | |
322 | error ("-mlong-double-64 not allowed with -m64"); | |
323 | target_flags |= MASK_LONG_DOUBLE_128; | |
324 | } | |
325 | ||
a0a301fc DE |
326 | /* Code model selection. */ |
327 | sparc_cmodel = SPARC_DEFAULT_CMODEL; | |
345a6161 DM |
328 | |
329 | #ifdef SPARC_BI_ARCH | |
330 | if (TARGET_ARCH32) | |
331 | sparc_cmodel = CM_32; | |
332 | #endif | |
333 | ||
a0a301fc DE |
334 | if (sparc_cmodel_string != NULL) |
335 | { | |
336 | if (TARGET_ARCH64) | |
337 | { | |
338 | for (cmodel = &cmodels[0]; cmodel->name; cmodel++) | |
339 | if (strcmp (sparc_cmodel_string, cmodel->name) == 0) | |
340 | break; | |
341 | if (cmodel->name == NULL) | |
342 | error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); | |
343 | else | |
344 | sparc_cmodel = cmodel->value; | |
345 | } | |
346 | else | |
347 | error ("-mcmodel= is not supported on 32 bit systems"); | |
348 | } | |
16956f6e | 349 | |
a0a301fc | 350 | fpu = TARGET_FPU; /* save current -mfpu status */ |
1f1406b4 | 351 | |
a0a301fc | 352 | /* Set the default CPU. */ |
16956f6e DE |
353 | for (def = &cpu_default[0]; def->name; ++def) |
354 | if (def->cpu == TARGET_CPU_DEFAULT) | |
355 | break; | |
356 | if (! def->name) | |
357 | abort (); | |
358 | sparc_select[0].string = def->name; | |
359 | ||
360 | for (sel = &sparc_select[0]; sel->name; ++sel) | |
61a55e8b | 361 | { |
16956f6e | 362 | if (sel->string) |
733f53f5 | 363 | { |
16956f6e DE |
364 | for (cpu = &cpu_table[0]; cpu->name; ++cpu) |
365 | if (! strcmp (sel->string, cpu->name)) | |
366 | { | |
367 | if (sel->set_tune_p) | |
368 | sparc_cpu = cpu->processor; | |
369 | ||
370 | if (sel->set_arch_p) | |
371 | { | |
372 | target_flags &= ~cpu->disable; | |
373 | target_flags |= cpu->enable; | |
374 | } | |
375 | break; | |
376 | } | |
377 | ||
378 | if (! cpu->name) | |
379 | error ("bad value (%s) for %s switch", sel->string, sel->name); | |
733f53f5 | 380 | } |
61a55e8b | 381 | } |
97da85b7 | 382 | |
1f1406b4 | 383 | /* If -mfpu or -mno-fpu was explicitly used, don't override with |
46cc13b3 RO |
384 | the processor default. Clear MASK_FPU_SET to avoid confusing |
385 | the reverse mapping from switch values to names. */ | |
1f1406b4 | 386 | if (TARGET_FPU_SET) |
46cc13b3 RO |
387 | { |
388 | target_flags = (target_flags & ~MASK_FPU) | fpu; | |
389 | target_flags &= ~MASK_FPU_SET; | |
390 | } | |
1f1406b4 | 391 | |
a5774a7d JJ |
392 | /* Don't allow -mvis if FPU is disabled. */ |
393 | if (! TARGET_FPU) | |
394 | target_flags &= ~MASK_VIS; | |
395 | ||
396 | /* -mvis assumes UltraSPARC+, so we are sure v9 instructions | |
397 | are available. | |
398 | -m64 also implies v9. */ | |
399 | if (TARGET_VIS || TARGET_ARCH64) | |
c4031a04 JJ |
400 | { |
401 | target_flags |= MASK_V9; | |
402 | target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); | |
403 | } | |
a5774a7d | 404 | |
16956f6e DE |
405 | /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ |
406 | if (TARGET_V9 && TARGET_ARCH32) | |
733f53f5 | 407 | target_flags |= MASK_DEPRECATED_V8_INSNS; |
61a55e8b | 408 | |
345a6161 DM |
409 | /* V8PLUS requires V9, makes no sense in 64 bit mode. */ |
410 | if (! TARGET_V9 || TARGET_ARCH64) | |
284d86e9 JC |
411 | target_flags &= ~MASK_V8PLUS; |
412 | ||
82d6b402 RH |
413 | /* Don't use stack biasing in 32 bit mode. */ |
414 | if (TARGET_ARCH32) | |
415 | target_flags &= ~MASK_STACK_BIAS; | |
f952a238 | 416 | |
efa3896a | 417 | /* Supply a default value for align_functions. */ |
fae15c93 VM |
418 | if (align_functions == 0 |
419 | && (sparc_cpu == PROCESSOR_ULTRASPARC | |
420 | || sparc_cpu == PROCESSOR_ULTRASPARC3)) | |
efa3896a | 421 | align_functions = 32; |
bf62bbf1 | 422 | |
82d6b402 RH |
423 | /* Validate PCC_STRUCT_RETURN. */ |
424 | if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) | |
425 | flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); | |
426 | ||
301d03af RS |
427 | /* Only use .uaxword when compiling for a 64-bit target. */ |
428 | if (!TARGET_ARCH64) | |
429 | targetm.asm_out.unaligned_op.di = NULL; | |
430 | ||
61a55e8b DE |
431 | /* Do various machine dependent initializations. */ |
432 | sparc_init_modes (); | |
2be15d0f | 433 | |
d07d525a MM |
434 | /* Register global variables with the garbage collector. */ |
435 | sparc_add_gc_roots (); | |
61a55e8b DE |
436 | } |
437 | \f | |
cd5fb1ee DE |
438 | /* Miscellaneous utilities. */ |
439 | ||
440 | /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move | |
441 | or branch on register contents instructions. */ | |
442 | ||
443 | int | |
444 | v9_regcmp_p (code) | |
445 | enum rtx_code code; | |
446 | { | |
447 | return (code == EQ || code == NE || code == GE || code == LT | |
448 | || code == LE || code == GT); | |
449 | } | |
bfd6bc60 | 450 | |
cd5fb1ee DE |
451 | \f |
452 | /* Operand constraints. */ | |
453 | ||
ab835497 | 454 | /* Return non-zero only if OP is a register of mode MODE, |
e6c1be7e | 455 | or const0_rtx. */ |
c4ce6853 | 456 | |
ab835497 RK |
457 | int |
458 | reg_or_0_operand (op, mode) | |
459 | rtx op; | |
460 | enum machine_mode mode; | |
461 | { | |
c4ce6853 DE |
462 | if (register_operand (op, mode)) |
463 | return 1; | |
c4ce6853 | 464 | if (op == const0_rtx) |
ab835497 | 465 | return 1; |
5b486ce0 | 466 | if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE |
ab835497 RK |
467 | && CONST_DOUBLE_HIGH (op) == 0 |
468 | && CONST_DOUBLE_LOW (op) == 0) | |
469 | return 1; | |
7ce86678 | 470 | if (fp_zero_operand (op, mode)) |
302484ff | 471 | return 1; |
ab835497 RK |
472 | return 0; |
473 | } | |
474 | ||
84ea5bc1 JJ |
475 | /* Return non-zero only if OP is const1_rtx. */ |
476 | ||
477 | int | |
478 | const1_operand (op, mode) | |
479 | rtx op; | |
480 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
481 | { | |
482 | return op == const1_rtx; | |
483 | } | |
484 | ||
302484ff | 485 | /* Nonzero if OP is a floating point value with value 0.0. */ |
c4ce6853 | 486 | |
302484ff | 487 | int |
7ce86678 | 488 | fp_zero_operand (op, mode) |
302484ff | 489 | rtx op; |
7ce86678 | 490 | enum machine_mode mode; |
302484ff | 491 | { |
7ce86678 RH |
492 | if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT) |
493 | return 0; | |
494 | return op == CONST0_RTX (mode); | |
302484ff JW |
495 | } |
496 | ||
2a732575 JJ |
497 | /* Nonzero if OP is a register operand in floating point register. */ |
498 | ||
499 | int | |
500 | fp_register_operand (op, mode) | |
501 | rtx op; | |
502 | enum machine_mode mode; | |
503 | { | |
504 | if (! register_operand (op, mode)) | |
505 | return 0; | |
506 | if (GET_CODE (op) == SUBREG) | |
507 | op = SUBREG_REG (op); | |
508 | return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op)); | |
509 | } | |
510 | ||
62190128 DM |
511 | /* Nonzero if OP is a floating point constant which can |
512 | be loaded into an integer register using a single | |
513 | sethi instruction. */ | |
514 | ||
515 | int | |
516 | fp_sethi_p (op) | |
517 | rtx op; | |
518 | { | |
519 | if (GET_CODE (op) == CONST_DOUBLE) | |
520 | { | |
521 | REAL_VALUE_TYPE r; | |
522 | long i; | |
523 | ||
524 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
525 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
526 | ! REAL_VALUE_MINUS_ZERO (r)) | |
527 | return 0; | |
528 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
529 | if (SPARC_SETHI_P (i)) | |
530 | return 1; | |
531 | } | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
536 | /* Nonzero if OP is a floating point constant which can | |
537 | be loaded into an integer register using a single | |
538 | mov instruction. */ | |
539 | ||
540 | int | |
541 | fp_mov_p (op) | |
542 | rtx op; | |
543 | { | |
544 | if (GET_CODE (op) == CONST_DOUBLE) | |
545 | { | |
546 | REAL_VALUE_TYPE r; | |
547 | long i; | |
548 | ||
549 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
550 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
551 | ! REAL_VALUE_MINUS_ZERO (r)) | |
552 | return 0; | |
553 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
554 | if (SPARC_SIMM13_P (i)) | |
555 | return 1; | |
556 | } | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
561 | /* Nonzero if OP is a floating point constant which can | |
562 | be loaded into an integer register using a high/losum | |
563 | instruction sequence. */ | |
564 | ||
565 | int | |
566 | fp_high_losum_p (op) | |
567 | rtx op; | |
568 | { | |
569 | /* The constraints calling this should only be in | |
570 | SFmode move insns, so any constant which cannot | |
571 | be moved using a single insn will do. */ | |
572 | if (GET_CODE (op) == CONST_DOUBLE) | |
573 | { | |
574 | REAL_VALUE_TYPE r; | |
575 | long i; | |
576 | ||
577 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
578 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
579 | ! REAL_VALUE_MINUS_ZERO (r)) | |
580 | return 0; | |
581 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
582 | if (! SPARC_SETHI_P (i) | |
583 | && ! SPARC_SIMM13_P (i)) | |
584 | return 1; | |
585 | } | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
61a55e8b DE |
590 | /* Nonzero if OP is an integer register. */ |
591 | ||
592 | int | |
593 | intreg_operand (op, mode) | |
594 | rtx op; | |
487a6e06 | 595 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
596 | { |
597 | return (register_operand (op, SImode) | |
a9e27770 | 598 | || (TARGET_ARCH64 && register_operand (op, DImode))); |
61a55e8b DE |
599 | } |
600 | ||
601 | /* Nonzero if OP is a floating point condition code register. */ | |
602 | ||
603 | int | |
c4ce6853 | 604 | fcc_reg_operand (op, mode) |
61a55e8b DE |
605 | rtx op; |
606 | enum machine_mode mode; | |
607 | { | |
608 | /* This can happen when recog is called from combine. Op may be a MEM. | |
609 | Fail instead of calling abort in this case. */ | |
c4ce6853 | 610 | if (GET_CODE (op) != REG) |
61a55e8b | 611 | return 0; |
304b7a23 | 612 | |
c4ce6853 | 613 | if (mode != VOIDmode && mode != GET_MODE (op)) |
61a55e8b | 614 | return 0; |
304b7a23 DE |
615 | if (mode == VOIDmode |
616 | && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) | |
617 | return 0; | |
61a55e8b | 618 | |
c4ce6853 | 619 | #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ |
61a55e8b DE |
620 | if (reg_renumber == 0) |
621 | return REGNO (op) >= FIRST_PSEUDO_REGISTER; | |
622 | return REGNO_OK_FOR_CCFP_P (REGNO (op)); | |
623 | #else | |
c4ce6853 | 624 | return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; |
61a55e8b DE |
625 | #endif |
626 | } | |
627 | ||
0b82d204 JJ |
628 | /* Nonzero if OP is a floating point condition code fcc0 register. */ |
629 | ||
630 | int | |
631 | fcc0_reg_operand (op, mode) | |
632 | rtx op; | |
633 | enum machine_mode mode; | |
634 | { | |
635 | /* This can happen when recog is called from combine. Op may be a MEM. | |
636 | Fail instead of calling abort in this case. */ | |
637 | if (GET_CODE (op) != REG) | |
638 | return 0; | |
639 | ||
640 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
641 | return 0; | |
642 | if (mode == VOIDmode | |
643 | && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) | |
644 | return 0; | |
645 | ||
646 | return REGNO (op) == SPARC_FCC_REG; | |
647 | } | |
648 | ||
c4ce6853 DE |
649 | /* Nonzero if OP is an integer or floating point condition code register. */ |
650 | ||
651 | int | |
652 | icc_or_fcc_reg_operand (op, mode) | |
653 | rtx op; | |
654 | enum machine_mode mode; | |
655 | { | |
656 | if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) | |
304b7a23 DE |
657 | { |
658 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
659 | return 0; | |
660 | if (mode == VOIDmode | |
661 | && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) | |
662 | return 0; | |
663 | return 1; | |
664 | } | |
665 | ||
c4ce6853 DE |
666 | return fcc_reg_operand (op, mode); |
667 | } | |
668 | ||
ab835497 RK |
669 | /* Nonzero if OP can appear as the dest of a RESTORE insn. */ |
670 | int | |
671 | restore_operand (op, mode) | |
672 | rtx op; | |
673 | enum machine_mode mode; | |
674 | { | |
675 | return (GET_CODE (op) == REG && GET_MODE (op) == mode | |
676 | && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); | |
677 | } | |
678 | ||
401cec23 JW |
679 | /* Call insn on SPARC can take a PC-relative constant address, or any regular |
680 | memory address. */ | |
ab835497 RK |
681 | |
682 | int | |
683 | call_operand (op, mode) | |
684 | rtx op; | |
685 | enum machine_mode mode; | |
686 | { | |
687 | if (GET_CODE (op) != MEM) | |
688 | abort (); | |
689 | op = XEXP (op, 0); | |
2445f289 | 690 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
691 | } |
692 | ||
693 | int | |
694 | call_operand_address (op, mode) | |
695 | rtx op; | |
696 | enum machine_mode mode; | |
697 | { | |
2445f289 | 698 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
699 | } |
700 | ||
701 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
702 | reference and a constant. */ | |
703 | ||
704 | int | |
705 | symbolic_operand (op, mode) | |
706 | register rtx op; | |
707 | enum machine_mode mode; | |
708 | { | |
6871dd65 RH |
709 | enum machine_mode omode = GET_MODE (op); |
710 | ||
711 | if (omode != mode && omode != VOIDmode && mode != VOIDmode) | |
712 | return 0; | |
713 | ||
ab835497 RK |
714 | switch (GET_CODE (op)) |
715 | { | |
716 | case SYMBOL_REF: | |
717 | case LABEL_REF: | |
718 | return 1; | |
719 | ||
720 | case CONST: | |
721 | op = XEXP (op, 0); | |
722 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
723 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
724 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
725 | ||
ab835497 RK |
726 | default: |
727 | return 0; | |
728 | } | |
729 | } | |
730 | ||
731 | /* Return truth value of statement that OP is a symbolic memory | |
732 | operand of mode MODE. */ | |
733 | ||
734 | int | |
735 | symbolic_memory_operand (op, mode) | |
736 | rtx op; | |
487a6e06 | 737 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
738 | { |
739 | if (GET_CODE (op) == SUBREG) | |
740 | op = SUBREG_REG (op); | |
741 | if (GET_CODE (op) != MEM) | |
742 | return 0; | |
743 | op = XEXP (op, 0); | |
744 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST | |
745 | || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); | |
746 | } | |
747 | ||
5ab7138b DE |
748 | /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ |
749 | ||
750 | int | |
751 | label_ref_operand (op, mode) | |
752 | rtx op; | |
753 | enum machine_mode mode; | |
754 | { | |
755 | if (GET_CODE (op) != LABEL_REF) | |
756 | return 0; | |
757 | if (GET_MODE (op) != mode) | |
758 | return 0; | |
759 | return 1; | |
760 | } | |
761 | ||
95726648 DE |
762 | /* Return 1 if the operand is an argument used in generating pic references |
763 | in either the medium/low or medium/anywhere code models of sparc64. */ | |
764 | ||
765 | int | |
766 | sp64_medium_pic_operand (op, mode) | |
767 | rtx op; | |
487a6e06 | 768 | enum machine_mode mode ATTRIBUTE_UNUSED; |
95726648 DE |
769 | { |
770 | /* Check for (const (minus (symbol_ref:GOT) | |
771 | (const (minus (label) (pc))))). */ | |
772 | if (GET_CODE (op) != CONST) | |
773 | return 0; | |
774 | op = XEXP (op, 0); | |
775 | if (GET_CODE (op) != MINUS) | |
776 | return 0; | |
777 | if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) | |
778 | return 0; | |
779 | /* ??? Ensure symbol is GOT. */ | |
780 | if (GET_CODE (XEXP (op, 1)) != CONST) | |
781 | return 0; | |
782 | if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) | |
783 | return 0; | |
784 | return 1; | |
785 | } | |
786 | ||
61a55e8b DE |
787 | /* Return 1 if the operand is a data segment reference. This includes |
788 | the readonly data segment, or in other words anything but the text segment. | |
789 | This is needed in the medium/anywhere code model on v9. These values | |
a0a301fc | 790 | are accessed with EMBMEDANY_BASE_REG. */ |
61a55e8b DE |
791 | |
792 | int | |
793 | data_segment_operand (op, mode) | |
794 | rtx op; | |
487a6e06 | 795 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
796 | { |
797 | switch (GET_CODE (op)) | |
798 | { | |
799 | case SYMBOL_REF : | |
800 | return ! SYMBOL_REF_FLAG (op); | |
801 | case PLUS : | |
95726648 DE |
802 | /* Assume canonical format of symbol + constant. |
803 | Fall through. */ | |
61a55e8b | 804 | case CONST : |
b1474bb7 | 805 | return data_segment_operand (XEXP (op, 0), VOIDmode); |
61a55e8b DE |
806 | default : |
807 | return 0; | |
808 | } | |
809 | } | |
810 | ||
811 | /* Return 1 if the operand is a text segment reference. | |
812 | This is needed in the medium/anywhere code model on v9. */ | |
813 | ||
814 | int | |
815 | text_segment_operand (op, mode) | |
816 | rtx op; | |
487a6e06 | 817 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
818 | { |
819 | switch (GET_CODE (op)) | |
820 | { | |
821 | case LABEL_REF : | |
822 | return 1; | |
823 | case SYMBOL_REF : | |
824 | return SYMBOL_REF_FLAG (op); | |
825 | case PLUS : | |
95726648 DE |
826 | /* Assume canonical format of symbol + constant. |
827 | Fall through. */ | |
61a55e8b | 828 | case CONST : |
b1474bb7 | 829 | return text_segment_operand (XEXP (op, 0), VOIDmode); |
61a55e8b DE |
830 | default : |
831 | return 0; | |
832 | } | |
833 | } | |
834 | ||
ab835497 RK |
835 | /* Return 1 if the operand is either a register or a memory operand that is |
836 | not symbolic. */ | |
837 | ||
838 | int | |
839 | reg_or_nonsymb_mem_operand (op, mode) | |
840 | register rtx op; | |
841 | enum machine_mode mode; | |
842 | { | |
843 | if (register_operand (op, mode)) | |
844 | return 1; | |
845 | ||
846 | if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) | |
847 | return 1; | |
848 | ||
849 | return 0; | |
850 | } | |
851 | ||
ab835497 | 852 | int |
6ac34277 | 853 | splittable_symbolic_memory_operand (op, mode) |
ab835497 | 854 | rtx op; |
487a6e06 | 855 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 | 856 | { |
6ac34277 DE |
857 | if (GET_CODE (op) != MEM) |
858 | return 0; | |
859 | if (! symbolic_operand (XEXP (op, 0), Pmode)) | |
860 | return 0; | |
861 | return 1; | |
862 | } | |
863 | ||
864 | int | |
865 | splittable_immediate_memory_operand (op, mode) | |
866 | rtx op; | |
487a6e06 | 867 | enum machine_mode mode ATTRIBUTE_UNUSED; |
6ac34277 DE |
868 | { |
869 | if (GET_CODE (op) != MEM) | |
870 | return 0; | |
871 | if (! immediate_operand (XEXP (op, 0), Pmode)) | |
872 | return 0; | |
873 | return 1; | |
ab835497 RK |
874 | } |
875 | ||
876 | /* Return truth value of whether OP is EQ or NE. */ | |
877 | ||
878 | int | |
879 | eq_or_neq (op, mode) | |
880 | rtx op; | |
487a6e06 | 881 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
882 | { |
883 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
884 | } | |
885 | ||
886 | /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, | |
887 | or LTU for non-floating-point. We handle those specially. */ | |
888 | ||
889 | int | |
890 | normal_comp_operator (op, mode) | |
891 | rtx op; | |
487a6e06 | 892 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
893 | { |
894 | enum rtx_code code = GET_CODE (op); | |
895 | ||
896 | if (GET_RTX_CLASS (code) != '<') | |
897 | return 0; | |
898 | ||
4d449554 JW |
899 | if (GET_MODE (XEXP (op, 0)) == CCFPmode |
900 | || GET_MODE (XEXP (op, 0)) == CCFPEmode) | |
ab835497 RK |
901 | return 1; |
902 | ||
903 | return (code != NE && code != EQ && code != GEU && code != LTU); | |
904 | } | |
905 | ||
906 | /* Return 1 if this is a comparison operator. This allows the use of | |
907 | MATCH_OPERATOR to recognize all the branch insns. */ | |
908 | ||
909 | int | |
910 | noov_compare_op (op, mode) | |
911 | register rtx op; | |
487a6e06 | 912 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
913 | { |
914 | enum rtx_code code = GET_CODE (op); | |
915 | ||
916 | if (GET_RTX_CLASS (code) != '<') | |
917 | return 0; | |
918 | ||
0b82d204 JJ |
919 | if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode |
920 | || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) | |
ab835497 RK |
921 | /* These are the only branches which work with CC_NOOVmode. */ |
922 | return (code == EQ || code == NE || code == GE || code == LT); | |
923 | return 1; | |
924 | } | |
925 | ||
0b82d204 JJ |
926 | /* Return 1 if this is a 64-bit comparison operator. This allows the use of |
927 | MATCH_OPERATOR to recognize all the branch insns. */ | |
928 | ||
929 | int | |
930 | noov_compare64_op (op, mode) | |
931 | register rtx op; | |
932 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
933 | { | |
934 | enum rtx_code code = GET_CODE (op); | |
935 | ||
936 | if (! TARGET_V9) | |
937 | return 0; | |
938 | ||
939 | if (GET_RTX_CLASS (code) != '<') | |
940 | return 0; | |
941 | ||
942 | if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) | |
943 | /* These are the only branches which work with CCX_NOOVmode. */ | |
944 | return (code == EQ || code == NE || code == GE || code == LT); | |
945 | return (GET_MODE (XEXP (op, 0)) == CCXmode); | |
946 | } | |
947 | ||
61a55e8b DE |
948 | /* Nonzero if OP is a comparison operator suitable for use in v9 |
949 | conditional move or branch on register contents instructions. */ | |
950 | ||
951 | int | |
952 | v9_regcmp_op (op, mode) | |
953 | register rtx op; | |
487a6e06 | 954 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
955 | { |
956 | enum rtx_code code = GET_CODE (op); | |
957 | ||
958 | if (GET_RTX_CLASS (code) != '<') | |
959 | return 0; | |
960 | ||
cd5fb1ee | 961 | return v9_regcmp_p (code); |
61a55e8b DE |
962 | } |
963 | ||
ab835497 RK |
964 | /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ |
965 | ||
966 | int | |
967 | extend_op (op, mode) | |
968 | rtx op; | |
487a6e06 | 969 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
970 | { |
971 | return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; | |
972 | } | |
973 | ||
974 | /* Return nonzero if OP is an operator of mode MODE which can set | |
975 | the condition codes explicitly. We do not include PLUS and MINUS | |
976 | because these require CC_NOOVmode, which we handle explicitly. */ | |
977 | ||
978 | int | |
979 | cc_arithop (op, mode) | |
980 | rtx op; | |
487a6e06 | 981 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
982 | { |
983 | if (GET_CODE (op) == AND | |
984 | || GET_CODE (op) == IOR | |
985 | || GET_CODE (op) == XOR) | |
986 | return 1; | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
991 | /* Return nonzero if OP is an operator of mode MODE which can bitwise | |
992 | complement its second operand and set the condition codes explicitly. */ | |
993 | ||
994 | int | |
995 | cc_arithopn (op, mode) | |
996 | rtx op; | |
487a6e06 | 997 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
998 | { |
999 | /* XOR is not here because combine canonicalizes (xor (not ...) ...) | |
80ffc95e | 1000 | and (xor ... (not ...)) to (not (xor ...)). */ |
ab835497 RK |
1001 | return (GET_CODE (op) == AND |
1002 | || GET_CODE (op) == IOR); | |
1003 | } | |
1004 | \f | |
58cbf20e DE |
1005 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
1006 | signed 13 bit immediate field. This is an acceptable SImode operand for | |
1007 | most 3 address instructions. */ | |
ab835497 RK |
1008 | |
1009 | int | |
1010 | arith_operand (op, mode) | |
1011 | rtx op; | |
1012 | enum machine_mode mode; | |
1013 | { | |
11301057 | 1014 | if (register_operand (op, mode)) |
284d86e9 JC |
1015 | return 1; |
1016 | if (GET_CODE (op) != CONST_INT) | |
1017 | return 0; | |
9e0625a3 | 1018 | return SMALL_INT32 (op); |
ab835497 RK |
1019 | } |
1020 | ||
5d6d3339 JJ |
1021 | /* Return true if OP is a constant 4096 */ |
1022 | ||
1023 | int | |
1024 | arith_4096_operand (op, mode) | |
1025 | rtx op; | |
ddf80874 | 1026 | enum machine_mode mode ATTRIBUTE_UNUSED; |
5d6d3339 | 1027 | { |
5d6d3339 JJ |
1028 | if (GET_CODE (op) != CONST_INT) |
1029 | return 0; | |
3070dd00 KG |
1030 | else |
1031 | return INTVAL (op) == 4096; | |
5d6d3339 JJ |
1032 | } |
1033 | ||
1034 | /* Return true if OP is suitable as second operand for add/sub */ | |
1035 | ||
1036 | int | |
1037 | arith_add_operand (op, mode) | |
1038 | rtx op; | |
1039 | enum machine_mode mode; | |
1040 | { | |
1041 | return arith_operand (op, mode) || arith_4096_operand (op, mode); | |
1042 | } | |
1043 | ||
89e65674 DM |
1044 | /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the |
1045 | immediate field of OR and XOR instructions. Used for 64-bit | |
1046 | constant formation patterns. */ | |
1047 | int | |
1048 | const64_operand (op, mode) | |
1049 | rtx op; | |
ddf80874 | 1050 | enum machine_mode mode ATTRIBUTE_UNUSED; |
89e65674 DM |
1051 | { |
1052 | return ((GET_CODE (op) == CONST_INT | |
1053 | && SPARC_SIMM13_P (INTVAL (op))) | |
9208e4b2 | 1054 | #if HOST_BITS_PER_WIDE_INT != 64 |
89e65674 | 1055 | || (GET_CODE (op) == CONST_DOUBLE |
9208e4b2 DM |
1056 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) |
1057 | && (CONST_DOUBLE_HIGH (op) == | |
1058 | ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? | |
9e0625a3 | 1059 | (HOST_WIDE_INT)-1 : 0))) |
9208e4b2 | 1060 | #endif |
11301057 | 1061 | ); |
89e65674 DM |
1062 | } |
1063 | ||
9208e4b2 | 1064 | /* The same, but only for sethi instructions. */ |
89e65674 DM |
1065 | int |
1066 | const64_high_operand (op, mode) | |
1067 | rtx op; | |
7d6040e8 | 1068 | enum machine_mode mode; |
89e65674 DM |
1069 | { |
1070 | return ((GET_CODE (op) == CONST_INT | |
9e0625a3 | 1071 | && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0 |
7d6040e8 | 1072 | && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) |
9208e4b2 | 1073 | ) |
89e65674 DM |
1074 | || (GET_CODE (op) == CONST_DOUBLE |
1075 | && CONST_DOUBLE_HIGH (op) == 0 | |
9e0625a3 | 1076 | && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0 |
11301057 | 1077 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))); |
89e65674 DM |
1078 | } |
1079 | ||
58cbf20e DE |
1080 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
1081 | signed 11 bit immediate field. This is an acceptable SImode operand for | |
1082 | the movcc instructions. */ | |
61a55e8b DE |
1083 | |
1084 | int | |
1085 | arith11_operand (op, mode) | |
1086 | rtx op; | |
1087 | enum machine_mode mode; | |
1088 | { | |
1089 | return (register_operand (op, mode) | |
58cbf20e | 1090 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); |
61a55e8b DE |
1091 | } |
1092 | ||
58cbf20e DE |
1093 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
1094 | signed 10 bit immediate field. This is an acceptable SImode operand for | |
1095 | the movrcc instructions. */ | |
61a55e8b DE |
1096 | |
1097 | int | |
1098 | arith10_operand (op, mode) | |
1099 | rtx op; | |
1100 | enum machine_mode mode; | |
1101 | { | |
1102 | return (register_operand (op, mode) | |
58cbf20e | 1103 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); |
61a55e8b DE |
1104 | } |
1105 | ||
23b8a89f JW |
1106 | /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit |
1107 | immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit | |
61a55e8b DE |
1108 | immediate field. |
1109 | v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
1110 | can fit in a 13 bit immediate field. This is an acceptable DImode operand | |
1111 | for most 3 address instructions. */ | |
ab835497 RK |
1112 | |
1113 | int | |
1114 | arith_double_operand (op, mode) | |
1115 | rtx op; | |
1116 | enum machine_mode mode; | |
1117 | { | |
1118 | return (register_operand (op, mode) | |
23b8a89f | 1119 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) |
a9e27770 | 1120 | || (! TARGET_ARCH64 |
61a55e8b | 1121 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 DE |
1122 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
1123 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) | |
a9e27770 | 1124 | || (TARGET_ARCH64 |
61a55e8b | 1125 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 | 1126 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
61a55e8b DE |
1127 | && ((CONST_DOUBLE_HIGH (op) == -1 |
1128 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) | |
1129 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1130 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); | |
1131 | } | |
1132 | ||
5d6d3339 JJ |
1133 | /* Return true if OP is a constant 4096 for DImode on ARCH64 */ |
1134 | ||
1135 | int | |
1136 | arith_double_4096_operand (op, mode) | |
1137 | rtx op; | |
ddf80874 | 1138 | enum machine_mode mode ATTRIBUTE_UNUSED; |
5d6d3339 JJ |
1139 | { |
1140 | return (TARGET_ARCH64 && | |
1141 | ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || | |
1142 | (GET_CODE (op) == CONST_DOUBLE && | |
1143 | CONST_DOUBLE_LOW (op) == 4096 && | |
1144 | CONST_DOUBLE_HIGH (op) == 0))); | |
1145 | } | |
1146 | ||
1147 | /* Return true if OP is suitable as second operand for add/sub in DImode */ | |
1148 | ||
1149 | int | |
1150 | arith_double_add_operand (op, mode) | |
1151 | rtx op; | |
1152 | enum machine_mode mode; | |
1153 | { | |
1154 | return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode); | |
1155 | } | |
1156 | ||
61a55e8b DE |
1157 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that |
1158 | can fit in an 11 bit immediate field. This is an acceptable DImode | |
1159 | operand for the movcc instructions. */ | |
1160 | /* ??? Replace with arith11_operand? */ | |
1161 | ||
1162 | int | |
1163 | arith11_double_operand (op, mode) | |
1164 | rtx op; | |
1165 | enum machine_mode mode; | |
1166 | { | |
1167 | return (register_operand (op, mode) | |
1168 | || (GET_CODE (op) == CONST_DOUBLE | |
1169 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1170 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 |
61a55e8b DE |
1171 | && ((CONST_DOUBLE_HIGH (op) == -1 |
1172 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) | |
1173 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1174 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) | |
1175 | || (GET_CODE (op) == CONST_INT | |
1176 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1177 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800)); |
61a55e8b DE |
1178 | } |
1179 | ||
1180 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
1181 | can fit in an 10 bit immediate field. This is an acceptable DImode | |
1182 | operand for the movrcc instructions. */ | |
1183 | /* ??? Replace with arith10_operand? */ | |
1184 | ||
1185 | int | |
1186 | arith10_double_operand (op, mode) | |
1187 | rtx op; | |
1188 | enum machine_mode mode; | |
1189 | { | |
1190 | return (register_operand (op, mode) | |
1191 | || (GET_CODE (op) == CONST_DOUBLE | |
1192 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
1193 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 | |
1194 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
1195 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) | |
1196 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1197 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) | |
1198 | || (GET_CODE (op) == CONST_INT | |
1199 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1200 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400)); |
ab835497 RK |
1201 | } |
1202 | ||
5519a4f9 | 1203 | /* Return truth value of whether OP is an integer which fits the |
228b4037 JW |
1204 | range constraining immediate operands in most three-address insns, |
1205 | which have a 13 bit immediate field. */ | |
ab835497 RK |
1206 | |
1207 | int | |
1208 | small_int (op, mode) | |
1209 | rtx op; | |
487a6e06 | 1210 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 | 1211 | { |
11301057 | 1212 | return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); |
ab835497 RK |
1213 | } |
1214 | ||
e0d80184 DM |
1215 | int |
1216 | small_int_or_double (op, mode) | |
1217 | rtx op; | |
1218 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1219 | { | |
1220 | return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) | |
1221 | || (GET_CODE (op) == CONST_DOUBLE | |
1222 | && CONST_DOUBLE_HIGH (op) == 0 | |
11301057 | 1223 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))); |
e0d80184 DM |
1224 | } |
1225 | ||
9b3fad96 JW |
1226 | /* Recognize operand values for the umul instruction. That instruction sign |
1227 | extends immediate values just like all other sparc instructions, but | |
1228 | interprets the extended result as an unsigned number. */ | |
1229 | ||
1230 | int | |
1231 | uns_small_int (op, mode) | |
1232 | rtx op; | |
487a6e06 | 1233 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9b3fad96 JW |
1234 | { |
1235 | #if HOST_BITS_PER_WIDE_INT > 32 | |
1236 | /* All allowed constants will fit a CONST_INT. */ | |
11301057 RH |
1237 | return (GET_CODE (op) == CONST_INT |
1238 | && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) | |
1239 | || (INTVAL (op) >= 0xFFFFF000 | |
0d587737 | 1240 | && INTVAL (op) <= 0xFFFFFFFF))); |
9b3fad96 | 1241 | #else |
11301057 RH |
1242 | return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) |
1243 | || (GET_CODE (op) == CONST_DOUBLE | |
1244 | && CONST_DOUBLE_HIGH (op) == 0 | |
1245 | && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); | |
9b3fad96 JW |
1246 | #endif |
1247 | } | |
1248 | ||
1249 | int | |
1250 | uns_arith_operand (op, mode) | |
1251 | rtx op; | |
1252 | enum machine_mode mode; | |
1253 | { | |
1254 | return register_operand (op, mode) || uns_small_int (op, mode); | |
1255 | } | |
1256 | ||
ab835497 RK |
1257 | /* Return truth value of statement that OP is a call-clobbered register. */ |
1258 | int | |
1259 | clobbered_register (op, mode) | |
1260 | rtx op; | |
487a6e06 | 1261 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
1262 | { |
1263 | return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); | |
1264 | } | |
ab835497 | 1265 | |
e0d80184 | 1266 | /* Return 1 if OP is a valid operand for the source of a move insn. */ |
61a55e8b | 1267 | |
e0d80184 DM |
1268 | int |
1269 | input_operand (op, mode) | |
1270 | rtx op; | |
1271 | enum machine_mode mode; | |
1272 | { | |
1273 | /* If both modes are non-void they must be the same. */ | |
1274 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) | |
1275 | return 0; | |
61a55e8b | 1276 | |
11301057 RH |
1277 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
1278 | if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX) | |
1279 | return 1; | |
1280 | ||
e0d80184 DM |
1281 | /* Allow any one instruction integer constant, and all CONST_INT |
1282 | variants when we are working in DImode and !arch64. */ | |
1283 | if (GET_MODE_CLASS (mode) == MODE_INT | |
9208e4b2 | 1284 | && ((GET_CODE (op) == CONST_INT |
7d6040e8 | 1285 | && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) |
9208e4b2 DM |
1286 | || SPARC_SIMM13_P (INTVAL (op)) |
1287 | || (mode == DImode | |
1288 | && ! TARGET_ARCH64))) | |
1289 | || (TARGET_ARCH64 | |
1290 | && GET_CODE (op) == CONST_DOUBLE | |
1291 | && ((CONST_DOUBLE_HIGH (op) == 0 | |
1292 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) | |
1293 | || | |
1294 | #if HOST_BITS_PER_WIDE_INT == 64 | |
1295 | (CONST_DOUBLE_HIGH (op) == 0 | |
1296 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) | |
1297 | #else | |
1298 | (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) | |
1299 | && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0 | |
1300 | && CONST_DOUBLE_HIGH (op) == 0) | |
4746e0fe RK |
1301 | || (CONST_DOUBLE_HIGH (op) == -1 |
1302 | && CONST_DOUBLE_LOW (op) & 0x80000000) != 0)) | |
9208e4b2 DM |
1303 | #endif |
1304 | )))) | |
e0d80184 DM |
1305 | return 1; |
1306 | ||
e0d80184 DM |
1307 | /* If !arch64 and this is a DImode const, allow it so that |
1308 | the splits can be generated. */ | |
1309 | if (! TARGET_ARCH64 | |
1310 | && mode == DImode | |
1311 | && GET_CODE (op) == CONST_DOUBLE) | |
1312 | return 1; | |
1313 | ||
1314 | if (register_operand (op, mode)) | |
1315 | return 1; | |
1316 | ||
62190128 DM |
1317 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1318 | && GET_CODE (op) == CONST_DOUBLE) | |
1319 | return 1; | |
1320 | ||
e0d80184 DM |
1321 | /* If this is a SUBREG, look inside so that we handle |
1322 | paradoxical ones. */ | |
1323 | if (GET_CODE (op) == SUBREG) | |
1324 | op = SUBREG_REG (op); | |
1325 | ||
1326 | /* Check for valid MEM forms. */ | |
1327 | if (GET_CODE (op) == MEM) | |
61a55e8b | 1328 | { |
e0d80184 | 1329 | rtx inside = XEXP (op, 0); |
61a55e8b | 1330 | |
e0d80184 | 1331 | if (GET_CODE (inside) == LO_SUM) |
03ad6f4d DM |
1332 | { |
1333 | /* We can't allow these because all of the splits | |
1334 | (eventually as they trickle down into DFmode | |
1335 | splits) require offsettable memory references. */ | |
1336 | if (! TARGET_V9 | |
1337 | && GET_MODE (op) == TFmode) | |
1338 | return 0; | |
1339 | ||
1340 | return (register_operand (XEXP (inside, 0), Pmode) | |
1341 | && CONSTANT_P (XEXP (inside, 1))); | |
1342 | } | |
e0d80184 | 1343 | return memory_address_p (mode, inside); |
61a55e8b | 1344 | } |
ab835497 | 1345 | |
e0d80184 DM |
1346 | return 0; |
1347 | } | |
1348 | ||
1349 | \f | |
1350 | /* We know it can't be done in one insn when we get here, | |
1351 | the movsi expander guarentees this. */ | |
1352 | void | |
1353 | sparc_emit_set_const32 (op0, op1) | |
1354 | rtx op0; | |
1355 | rtx op1; | |
1356 | { | |
1357 | enum machine_mode mode = GET_MODE (op0); | |
1358 | rtx temp; | |
1359 | ||
1360 | if (GET_CODE (op1) == CONST_INT) | |
284d86e9 | 1361 | { |
2a01c939 | 1362 | HOST_WIDE_INT value = INTVAL (op1); |
e0d80184 | 1363 | |
7d6040e8 | 1364 | if (SPARC_SETHI_P (value & GET_MODE_MASK (mode)) |
e0d80184 DM |
1365 | || SPARC_SIMM13_P (value)) |
1366 | abort (); | |
284d86e9 | 1367 | } |
e0d80184 DM |
1368 | |
1369 | /* Full 2-insn decomposition is needed. */ | |
1370 | if (reload_in_progress || reload_completed) | |
1371 | temp = op0; | |
284d86e9 | 1372 | else |
e0d80184 DM |
1373 | temp = gen_reg_rtx (mode); |
1374 | ||
71648202 DM |
1375 | if (GET_CODE (op1) == CONST_INT) |
1376 | { | |
1377 | /* Emit them as real moves instead of a HIGH/LO_SUM, | |
1378 | this way CSE can see everything and reuse intermediate | |
1379 | values if it wants. */ | |
1380 | if (TARGET_ARCH64 | |
1381 | && HOST_BITS_PER_WIDE_INT != 64 | |
1382 | && (INTVAL (op1) & 0x80000000) != 0) | |
f2827474 RK |
1383 | emit_insn (gen_rtx_SET |
1384 | (VOIDmode, temp, | |
5692c7bc ZW |
1385 | immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff, |
1386 | 0, DImode))); | |
71648202 | 1387 | else |
f2827474 | 1388 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
9e0625a3 AO |
1389 | GEN_INT (INTVAL (op1) |
1390 | & ~(HOST_WIDE_INT)0x3ff))); | |
f2827474 | 1391 | |
71648202 DM |
1392 | emit_insn (gen_rtx_SET (VOIDmode, |
1393 | op0, | |
f2827474 | 1394 | gen_rtx_IOR (mode, temp, |
71648202 DM |
1395 | GEN_INT (INTVAL (op1) & 0x3ff)))); |
1396 | } | |
1397 | else | |
1398 | { | |
1399 | /* A symbol, emit in the traditional way. */ | |
f2827474 RK |
1400 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
1401 | gen_rtx_HIGH (mode, op1))); | |
71648202 | 1402 | emit_insn (gen_rtx_SET (VOIDmode, |
f2827474 | 1403 | op0, gen_rtx_LO_SUM (mode, temp, op1))); |
71648202 DM |
1404 | |
1405 | } | |
e0d80184 DM |
1406 | } |
1407 | ||
1408 | \f | |
80ffc95e | 1409 | /* Sparc-v9 code-model support. */ |
e0d80184 DM |
1410 | void |
1411 | sparc_emit_set_symbolic_const64 (op0, op1, temp1) | |
1412 | rtx op0; | |
1413 | rtx op1; | |
1414 | rtx temp1; | |
1415 | { | |
3968de80 DD |
1416 | rtx ti_temp1 = 0; |
1417 | ||
1418 | if (temp1 && GET_MODE (temp1) == TImode) | |
1419 | { | |
1420 | ti_temp1 = temp1; | |
1421 | temp1 = gen_rtx_REG (DImode, REGNO (temp1)); | |
1422 | } | |
1423 | ||
e0d80184 | 1424 | switch (sparc_cmodel) |
284d86e9 | 1425 | { |
e0d80184 DM |
1426 | case CM_MEDLOW: |
1427 | /* The range spanned by all instructions in the object is less | |
1428 | than 2^31 bytes (2GB) and the distance from any instruction | |
1429 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1430 | than 2^31 bytes (2GB). | |
ab835497 | 1431 | |
e0d80184 DM |
1432 | The executable must be in the low 4TB of the virtual address |
1433 | space. | |
61a55e8b | 1434 | |
e0d80184 DM |
1435 | sethi %hi(symbol), %temp |
1436 | or %temp, %lo(symbol), %reg */ | |
9208e4b2 DM |
1437 | emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); |
1438 | emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); | |
e0d80184 | 1439 | break; |
61a55e8b | 1440 | |
e0d80184 DM |
1441 | case CM_MEDMID: |
1442 | /* The range spanned by all instructions in the object is less | |
1443 | than 2^31 bytes (2GB) and the distance from any instruction | |
1444 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1445 | than 2^31 bytes (2GB). | |
1446 | ||
1447 | The executable must be in the low 16TB of the virtual address | |
1448 | space. | |
1449 | ||
1450 | sethi %h44(symbol), %temp1 | |
1451 | or %temp1, %m44(symbol), %temp2 | |
1452 | sllx %temp2, 12, %temp3 | |
1453 | or %temp3, %l44(symbol), %reg */ | |
1454 | emit_insn (gen_seth44 (op0, op1)); | |
1455 | emit_insn (gen_setm44 (op0, op0, op1)); | |
9208e4b2 | 1456 | emit_insn (gen_rtx_SET (VOIDmode, temp1, |
e0d80184 DM |
1457 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (12)))); |
1458 | emit_insn (gen_setl44 (op0, temp1, op1)); | |
1459 | break; | |
61a55e8b | 1460 | |
e0d80184 DM |
1461 | case CM_MEDANY: |
1462 | /* The range spanned by all instructions in the object is less | |
1463 | than 2^31 bytes (2GB) and the distance from any instruction | |
1464 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1465 | than 2^31 bytes (2GB). | |
1466 | ||
1467 | The executable can be placed anywhere in the virtual address | |
1468 | space. | |
1469 | ||
1470 | sethi %hh(symbol), %temp1 | |
1471 | sethi %lm(symbol), %temp2 | |
1472 | or %temp1, %hm(symbol), %temp3 | |
1473 | or %temp2, %lo(symbol), %temp4 | |
1474 | sllx %temp3, 32, %temp5 | |
1475 | or %temp4, %temp5, %reg */ | |
1476 | ||
3968de80 DD |
1477 | /* It is possible that one of the registers we got for operands[2] |
1478 | might coincide with that of operands[0] (which is why we made | |
1479 | it TImode). Pick the other one to use as our scratch. */ | |
6cd444b4 | 1480 | if (rtx_equal_p (temp1, op0)) |
3968de80 DD |
1481 | { |
1482 | if (ti_temp1) | |
1483 | temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1); | |
1484 | else | |
1485 | abort(); | |
1486 | } | |
61a55e8b | 1487 | |
e0d80184 DM |
1488 | emit_insn (gen_sethh (op0, op1)); |
1489 | emit_insn (gen_setlm (temp1, op1)); | |
1490 | emit_insn (gen_sethm (op0, op0, op1)); | |
9208e4b2 | 1491 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1492 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1493 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1494 | gen_rtx_PLUS (DImode, op0, temp1))); |
1495 | emit_insn (gen_setlo (op0, op0, op1)); | |
1496 | break; | |
61a55e8b | 1497 | |
e0d80184 DM |
1498 | case CM_EMBMEDANY: |
1499 | /* Old old old backwards compatibility kruft here. | |
1500 | Essentially it is MEDLOW with a fixed 64-bit | |
1501 | virtual base added to all data segment addresses. | |
1502 | Text-segment stuff is computed like MEDANY, we can't | |
1503 | reuse the code above because the relocation knobs | |
1504 | look different. | |
1505 | ||
1506 | Data segment: sethi %hi(symbol), %temp1 | |
1507 | or %temp1, %lo(symbol), %temp2 | |
1508 | add %temp2, EMBMEDANY_BASE_REG, %reg | |
1509 | ||
1510 | Text segment: sethi %uhi(symbol), %temp1 | |
1511 | sethi %hi(symbol), %temp2 | |
1512 | or %temp1, %ulo(symbol), %temp3 | |
1513 | or %temp2, %lo(symbol), %temp4 | |
1514 | sllx %temp3, 32, %temp5 | |
1515 | or %temp4, %temp5, %reg */ | |
1516 | if (data_segment_operand (op1, GET_MODE (op1))) | |
1517 | { | |
1518 | emit_insn (gen_embmedany_sethi (temp1, op1)); | |
1519 | emit_insn (gen_embmedany_brsum (op0, temp1)); | |
1520 | emit_insn (gen_embmedany_losum (op0, op0, op1)); | |
1521 | } | |
1522 | else | |
1523 | { | |
3968de80 DD |
1524 | /* It is possible that one of the registers we got for operands[2] |
1525 | might coincide with that of operands[0] (which is why we made | |
1526 | it TImode). Pick the other one to use as our scratch. */ | |
1527 | if (rtx_equal_p (temp1, op0)) | |
1528 | { | |
1529 | if (ti_temp1) | |
1530 | temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1); | |
1531 | else | |
1532 | abort(); | |
1533 | } | |
61a55e8b | 1534 | |
e0d80184 DM |
1535 | emit_insn (gen_embmedany_textuhi (op0, op1)); |
1536 | emit_insn (gen_embmedany_texthi (temp1, op1)); | |
1537 | emit_insn (gen_embmedany_textulo (op0, op0, op1)); | |
9208e4b2 | 1538 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1539 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1540 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1541 | gen_rtx_PLUS (DImode, op0, temp1))); |
1542 | emit_insn (gen_embmedany_textlo (op0, op0, op1)); | |
1543 | } | |
1544 | break; | |
1545 | ||
1546 | default: | |
1547 | abort(); | |
1548 | } | |
1549 | } | |
1550 | ||
9208e4b2 DM |
1551 | /* These avoid problems when cross compiling. If we do not |
1552 | go through all this hair then the optimizer will see | |
1553 | invalid REG_EQUAL notes or in some cases none at all. */ | |
f6da8bc3 KG |
1554 | static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT)); |
1555 | static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT)); | |
1556 | static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT)); | |
1557 | static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT)); | |
9208e4b2 DM |
1558 | |
1559 | #if HOST_BITS_PER_WIDE_INT == 64 | |
9e0625a3 | 1560 | #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff) |
9208e4b2 DM |
1561 | #define GEN_INT64(__x) GEN_INT (__x) |
1562 | #else | |
1563 | #define GEN_HIGHINT64(__x) \ | |
5692c7bc | 1564 | immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode) |
9208e4b2 | 1565 | #define GEN_INT64(__x) \ |
5692c7bc ZW |
1566 | immed_double_const ((__x) & 0xffffffff, \ |
1567 | ((__x) & 0x80000000 ? -1 : 0), DImode) | |
9208e4b2 DM |
1568 | #endif |
1569 | ||
1570 | /* The optimizer is not to assume anything about exactly | |
1571 | which bits are set for a HIGH, they are unspecified. | |
1572 | Unfortunately this leads to many missed optimizations | |
1573 | during CSE. We mask out the non-HIGH bits, and matches | |
1574 | a plain movdi, to alleviate this problem. */ | |
1575 | static void | |
1576 | sparc_emit_set_safe_HIGH64 (dest, val) | |
1577 | rtx dest; | |
1578 | HOST_WIDE_INT val; | |
1579 | { | |
1580 | emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val))); | |
1581 | } | |
2a01c939 | 1582 | |
e0d80184 | 1583 | static rtx |
9208e4b2 DM |
1584 | gen_safe_SET64 (dest, val) |
1585 | rtx dest; | |
e0d80184 | 1586 | HOST_WIDE_INT val; |
61a55e8b | 1587 | { |
9208e4b2 DM |
1588 | return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val)); |
1589 | } | |
1590 | ||
1591 | static rtx | |
1592 | gen_safe_OR64 (src, val) | |
1593 | rtx src; | |
1594 | HOST_WIDE_INT val; | |
1595 | { | |
1596 | return gen_rtx_IOR (DImode, src, GEN_INT64 (val)); | |
1597 | } | |
1598 | ||
1599 | static rtx | |
1600 | gen_safe_XOR64 (src, val) | |
1601 | rtx src; | |
1602 | HOST_WIDE_INT val; | |
1603 | { | |
1604 | return gen_rtx_XOR (DImode, src, GEN_INT64 (val)); | |
e0d80184 | 1605 | } |
61a55e8b | 1606 | |
e0d80184 DM |
1607 | /* Worker routines for 64-bit constant formation on arch64. |
1608 | One of the key things to be doing in these emissions is | |
1609 | to create as many temp REGs as possible. This makes it | |
1610 | possible for half-built constants to be used later when | |
1611 | such values are similar to something required later on. | |
1612 | Without doing this, the optimizer cannot see such | |
1613 | opportunities. */ | |
2a01c939 DM |
1614 | |
1615 | static void sparc_emit_set_const64_quick1 | |
f6da8bc3 | 1616 | PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int)); |
2a01c939 | 1617 | |
e0d80184 DM |
1618 | static void |
1619 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg) | |
1620 | rtx op0; | |
1621 | rtx temp; | |
2a01c939 | 1622 | unsigned HOST_WIDE_INT low_bits; |
e0d80184 DM |
1623 | int is_neg; |
1624 | { | |
2a01c939 | 1625 | unsigned HOST_WIDE_INT high_bits; |
a9e27770 | 1626 | |
e0d80184 | 1627 | if (is_neg) |
2a01c939 | 1628 | high_bits = (~low_bits) & 0xffffffff; |
31bc9eba | 1629 | else |
e0d80184 | 1630 | high_bits = low_bits; |
31bc9eba | 1631 | |
9208e4b2 | 1632 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1633 | if (!is_neg) |
5108f3e5 DM |
1634 | { |
1635 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1636 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
1637 | } | |
e0d80184 | 1638 | else |
5108f3e5 DM |
1639 | { |
1640 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
1641 | instead. This way the combiner will notice logical operations | |
1642 | such as ANDN later on and substitute. */ | |
1643 | if ((low_bits & 0x3ff) == 0x3ff) | |
1644 | { | |
1645 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1646 | gen_rtx_NOT (DImode, temp))); | |
1647 | } | |
1648 | else | |
1649 | { | |
1650 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1651 | gen_safe_XOR64 (temp, | |
9e0625a3 AO |
1652 | (-(HOST_WIDE_INT)0x400 |
1653 | | (low_bits & 0x3ff))))); | |
5108f3e5 DM |
1654 | } |
1655 | } | |
e0d80184 | 1656 | } |
61a55e8b | 1657 | |
2a01c939 | 1658 | static void sparc_emit_set_const64_quick2 |
f6da8bc3 | 1659 | PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, |
2a01c939 DM |
1660 | unsigned HOST_WIDE_INT, int)); |
1661 | ||
e0d80184 DM |
1662 | static void |
1663 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count) | |
1664 | rtx op0; | |
1665 | rtx temp; | |
2a01c939 DM |
1666 | unsigned HOST_WIDE_INT high_bits; |
1667 | unsigned HOST_WIDE_INT low_immediate; | |
e0d80184 DM |
1668 | int shift_count; |
1669 | { | |
1670 | rtx temp2 = op0; | |
61a55e8b | 1671 | |
e0d80184 DM |
1672 | if ((high_bits & 0xfffffc00) != 0) |
1673 | { | |
9208e4b2 | 1674 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1675 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 DM |
1676 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1677 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
61a55e8b | 1678 | else |
e0d80184 | 1679 | temp2 = temp; |
61a55e8b DE |
1680 | } |
1681 | else | |
1682 | { | |
f710f868 | 1683 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 DM |
1684 | temp2 = temp; |
1685 | } | |
61a55e8b | 1686 | |
80ffc95e | 1687 | /* Now shift it up into place. */ |
9208e4b2 | 1688 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1689 | gen_rtx_ASHIFT (DImode, temp2, |
1690 | GEN_INT (shift_count)))); | |
61a55e8b | 1691 | |
e0d80184 DM |
1692 | /* If there is a low immediate part piece, finish up by |
1693 | putting that in as well. */ | |
1694 | if (low_immediate != 0) | |
9208e4b2 DM |
1695 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1696 | gen_safe_OR64 (op0, low_immediate))); | |
ab835497 RK |
1697 | } |
1698 | ||
2a01c939 | 1699 | static void sparc_emit_set_const64_longway |
f6da8bc3 | 1700 | PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); |
2a01c939 | 1701 | |
e0d80184 DM |
1702 | /* Full 64-bit constant decomposition. Even though this is the |
1703 | 'worst' case, we still optimize a few things away. */ | |
1704 | static void | |
1705 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits) | |
1706 | rtx op0; | |
1707 | rtx temp; | |
2a01c939 DM |
1708 | unsigned HOST_WIDE_INT high_bits; |
1709 | unsigned HOST_WIDE_INT low_bits; | |
ab835497 | 1710 | { |
e0d80184 | 1711 | rtx sub_temp; |
4bf7135b | 1712 | |
e0d80184 DM |
1713 | if (reload_in_progress || reload_completed) |
1714 | sub_temp = op0; | |
1715 | else | |
1716 | sub_temp = gen_reg_rtx (DImode); | |
1717 | ||
1718 | if ((high_bits & 0xfffffc00) != 0) | |
1719 | { | |
9208e4b2 | 1720 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1721 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 | 1722 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1723 | sub_temp, |
9208e4b2 | 1724 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); |
e0d80184 DM |
1725 | else |
1726 | sub_temp = temp; | |
1727 | } | |
1728 | else | |
ab835497 | 1729 | { |
f710f868 | 1730 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 | 1731 | sub_temp = temp; |
ab835497 | 1732 | } |
4bf7135b | 1733 | |
e0d80184 | 1734 | if (!reload_in_progress && !reload_completed) |
284d86e9 | 1735 | { |
e0d80184 DM |
1736 | rtx temp2 = gen_reg_rtx (DImode); |
1737 | rtx temp3 = gen_reg_rtx (DImode); | |
1738 | rtx temp4 = gen_reg_rtx (DImode); | |
284d86e9 | 1739 | |
9208e4b2 | 1740 | emit_insn (gen_rtx_SET (VOIDmode, temp4, |
e0d80184 DM |
1741 | gen_rtx_ASHIFT (DImode, sub_temp, |
1742 | GEN_INT (32)))); | |
4bf7135b | 1743 | |
9208e4b2 | 1744 | sparc_emit_set_safe_HIGH64 (temp2, low_bits); |
e0d80184 | 1745 | if ((low_bits & ~0xfffffc00) != 0) |
f710f868 DM |
1746 | { |
1747 | emit_insn (gen_rtx_SET (VOIDmode, temp3, | |
1748 | gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); | |
1749 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1750 | gen_rtx_PLUS (DImode, temp4, temp3))); | |
1751 | } | |
1752 | else | |
1753 | { | |
1754 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1755 | gen_rtx_PLUS (DImode, temp4, temp2))); | |
1756 | } | |
284d86e9 | 1757 | } |
e0d80184 DM |
1758 | else |
1759 | { | |
9208e4b2 DM |
1760 | rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); |
1761 | rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); | |
1762 | rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); | |
e0d80184 | 1763 | int to_shift = 12; |
284d86e9 | 1764 | |
e0d80184 DM |
1765 | /* We are in the middle of reload, so this is really |
1766 | painful. However we do still make an attempt to | |
5108f3e5 | 1767 | avoid emitting truly stupid code. */ |
e0d80184 DM |
1768 | if (low1 != const0_rtx) |
1769 | { | |
9208e4b2 | 1770 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1771 | gen_rtx_ASHIFT (DImode, sub_temp, |
2a01c939 | 1772 | GEN_INT (to_shift)))); |
9208e4b2 | 1773 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1774 | gen_rtx_IOR (DImode, op0, low1))); |
1775 | sub_temp = op0; | |
1776 | to_shift = 12; | |
1777 | } | |
1778 | else | |
1779 | { | |
1780 | to_shift += 12; | |
1781 | } | |
1782 | if (low2 != const0_rtx) | |
1783 | { | |
9208e4b2 | 1784 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1785 | gen_rtx_ASHIFT (DImode, sub_temp, |
1786 | GEN_INT (to_shift)))); | |
9208e4b2 | 1787 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1788 | gen_rtx_IOR (DImode, op0, low2))); |
1789 | sub_temp = op0; | |
1790 | to_shift = 8; | |
1791 | } | |
1792 | else | |
1793 | { | |
1794 | to_shift += 8; | |
1795 | } | |
9208e4b2 | 1796 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1797 | gen_rtx_ASHIFT (DImode, sub_temp, |
1798 | GEN_INT (to_shift)))); | |
1799 | if (low3 != const0_rtx) | |
9208e4b2 | 1800 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1801 | gen_rtx_IOR (DImode, op0, low3))); |
80ffc95e | 1802 | /* phew... */ |
e0d80184 | 1803 | } |
284d86e9 JC |
1804 | } |
1805 | ||
80ffc95e | 1806 | /* Analyze a 64-bit constant for certain properties. */ |
2a01c939 | 1807 | static void analyze_64bit_constant |
f6da8bc3 | 1808 | PARAMS ((unsigned HOST_WIDE_INT, |
2a01c939 DM |
1809 | unsigned HOST_WIDE_INT, |
1810 | int *, int *, int *)); | |
1811 | ||
e0d80184 DM |
1812 | static void |
1813 | analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp) | |
2a01c939 | 1814 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 | 1815 | int *hbsp, *lbsp, *abbasp; |
ab835497 | 1816 | { |
e0d80184 DM |
1817 | int lowest_bit_set, highest_bit_set, all_bits_between_are_set; |
1818 | int i; | |
ab835497 | 1819 | |
e0d80184 DM |
1820 | lowest_bit_set = highest_bit_set = -1; |
1821 | i = 0; | |
1822 | do | |
ab835497 | 1823 | { |
e0d80184 DM |
1824 | if ((lowest_bit_set == -1) |
1825 | && ((low_bits >> i) & 1)) | |
1826 | lowest_bit_set = i; | |
1827 | if ((highest_bit_set == -1) | |
1828 | && ((high_bits >> (32 - i - 1)) & 1)) | |
1829 | highest_bit_set = (64 - i - 1); | |
1830 | } | |
1831 | while (++i < 32 | |
1832 | && ((highest_bit_set == -1) | |
1833 | || (lowest_bit_set == -1))); | |
1834 | if (i == 32) | |
1835 | { | |
1836 | i = 0; | |
1837 | do | |
ab835497 | 1838 | { |
e0d80184 DM |
1839 | if ((lowest_bit_set == -1) |
1840 | && ((high_bits >> i) & 1)) | |
1841 | lowest_bit_set = i + 32; | |
1842 | if ((highest_bit_set == -1) | |
1843 | && ((low_bits >> (32 - i - 1)) & 1)) | |
1844 | highest_bit_set = 32 - i - 1; | |
ab835497 | 1845 | } |
e0d80184 DM |
1846 | while (++i < 32 |
1847 | && ((highest_bit_set == -1) | |
1848 | || (lowest_bit_set == -1))); | |
1849 | } | |
1850 | /* If there are no bits set this should have gone out | |
1851 | as one instruction! */ | |
1852 | if (lowest_bit_set == -1 | |
1853 | || highest_bit_set == -1) | |
9208e4b2 | 1854 | abort (); |
e0d80184 DM |
1855 | all_bits_between_are_set = 1; |
1856 | for (i = lowest_bit_set; i <= highest_bit_set; i++) | |
1857 | { | |
1858 | if (i < 32) | |
1859 | { | |
1860 | if ((low_bits & (1 << i)) != 0) | |
1861 | continue; | |
1862 | } | |
1863 | else | |
1864 | { | |
1865 | if ((high_bits & (1 << (i - 32))) != 0) | |
1866 | continue; | |
1867 | } | |
1868 | all_bits_between_are_set = 0; | |
1869 | break; | |
ab835497 | 1870 | } |
e0d80184 DM |
1871 | *hbsp = highest_bit_set; |
1872 | *lbsp = lowest_bit_set; | |
1873 | *abbasp = all_bits_between_are_set; | |
ab835497 | 1874 | } |
6a4bb1fa | 1875 | |
2a01c939 | 1876 | static int const64_is_2insns |
f6da8bc3 | 1877 | PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); |
2a01c939 | 1878 | |
e0d80184 DM |
1879 | static int |
1880 | const64_is_2insns (high_bits, low_bits) | |
2a01c939 | 1881 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1882 | { |
1883 | int highest_bit_set, lowest_bit_set, all_bits_between_are_set; | |
284d86e9 | 1884 | |
e0d80184 | 1885 | if (high_bits == 0 |
f451b552 | 1886 | || high_bits == 0xffffffff) |
e0d80184 | 1887 | return 1; |
6a4bb1fa | 1888 | |
e0d80184 DM |
1889 | analyze_64bit_constant (high_bits, low_bits, |
1890 | &highest_bit_set, &lowest_bit_set, | |
1891 | &all_bits_between_are_set); | |
6a4bb1fa | 1892 | |
f710f868 DM |
1893 | if ((highest_bit_set == 63 |
1894 | || lowest_bit_set == 0) | |
e0d80184 DM |
1895 | && all_bits_between_are_set != 0) |
1896 | return 1; | |
6a4bb1fa | 1897 | |
9208e4b2 DM |
1898 | if ((highest_bit_set - lowest_bit_set) < 21) |
1899 | return 1; | |
1900 | ||
6a4bb1fa DE |
1901 | return 0; |
1902 | } | |
1903 | ||
2a01c939 | 1904 | static unsigned HOST_WIDE_INT create_simple_focus_bits |
f6da8bc3 | 1905 | PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, |
ddf80874 | 1906 | int, int)); |
2a01c939 DM |
1907 | |
1908 | static unsigned HOST_WIDE_INT | |
ddf80874 | 1909 | create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift) |
2a01c939 | 1910 | unsigned HOST_WIDE_INT high_bits, low_bits; |
ddf80874 | 1911 | int lowest_bit_set, shift; |
ab835497 | 1912 | { |
f710f868 | 1913 | HOST_WIDE_INT hi, lo; |
ab835497 | 1914 | |
e0d80184 DM |
1915 | if (lowest_bit_set < 32) |
1916 | { | |
1917 | lo = (low_bits >> lowest_bit_set) << shift; | |
1918 | hi = ((high_bits << (32 - lowest_bit_set)) << shift); | |
1919 | } | |
1920 | else | |
1921 | { | |
1922 | lo = 0; | |
1923 | hi = ((high_bits >> (lowest_bit_set - 32)) << shift); | |
1924 | } | |
1925 | if (hi & lo) | |
9208e4b2 | 1926 | abort (); |
e0d80184 DM |
1927 | return (hi | lo); |
1928 | } | |
ab835497 | 1929 | |
e0d80184 DM |
1930 | /* Here we are sure to be arch64 and this is an integer constant |
1931 | being loaded into a register. Emit the most efficient | |
1932 | insn sequence possible. Detection of all the 1-insn cases | |
1933 | has been done already. */ | |
1934 | void | |
1935 | sparc_emit_set_const64 (op0, op1) | |
1936 | rtx op0; | |
1937 | rtx op1; | |
1938 | { | |
2a01c939 | 1939 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1940 | int lowest_bit_set, highest_bit_set; |
1941 | int all_bits_between_are_set; | |
e0d80184 | 1942 | rtx temp; |
ab835497 | 1943 | |
e0d80184 | 1944 | /* Sanity check that we know what we are working with. */ |
380f6ad3 | 1945 | if (! TARGET_ARCH64) |
9208e4b2 | 1946 | abort (); |
95726648 | 1947 | |
380f6ad3 JJ |
1948 | if (GET_CODE (op0) != SUBREG) |
1949 | { | |
1950 | if (GET_CODE (op0) != REG | |
1951 | || (REGNO (op0) >= SPARC_FIRST_FP_REG | |
1952 | && REGNO (op0) <= SPARC_LAST_V9_FP_REG)) | |
1953 | abort (); | |
1954 | } | |
1955 | ||
f710f868 DM |
1956 | if (reload_in_progress || reload_completed) |
1957 | temp = op0; | |
1958 | else | |
1959 | temp = gen_reg_rtx (DImode); | |
1960 | ||
e0d80184 DM |
1961 | if (GET_CODE (op1) != CONST_DOUBLE |
1962 | && GET_CODE (op1) != CONST_INT) | |
1963 | { | |
5f78aa30 JC |
1964 | sparc_emit_set_symbolic_const64 (op0, op1, temp); |
1965 | return; | |
e0d80184 | 1966 | } |
ab835497 | 1967 | |
e0d80184 DM |
1968 | if (GET_CODE (op1) == CONST_DOUBLE) |
1969 | { | |
1970 | #if HOST_BITS_PER_WIDE_INT == 64 | |
2a01c939 | 1971 | high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff; |
e0d80184 DM |
1972 | low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff; |
1973 | #else | |
1974 | high_bits = CONST_DOUBLE_HIGH (op1); | |
1975 | low_bits = CONST_DOUBLE_LOW (op1); | |
1976 | #endif | |
ab835497 | 1977 | } |
e0d80184 | 1978 | else |
ab835497 | 1979 | { |
e0d80184 | 1980 | #if HOST_BITS_PER_WIDE_INT == 64 |
2a01c939 | 1981 | high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); |
e0d80184 DM |
1982 | low_bits = (INTVAL (op1) & 0xffffffff); |
1983 | #else | |
1984 | high_bits = ((INTVAL (op1) < 0) ? | |
1985 | 0xffffffff : | |
1986 | 0x00000000); | |
1987 | low_bits = INTVAL (op1); | |
1988 | #endif | |
1989 | } | |
ab835497 | 1990 | |
e0d80184 DM |
1991 | /* low_bits bits 0 --> 31 |
1992 | high_bits bits 32 --> 63 */ | |
ab835497 | 1993 | |
e0d80184 DM |
1994 | analyze_64bit_constant (high_bits, low_bits, |
1995 | &highest_bit_set, &lowest_bit_set, | |
1996 | &all_bits_between_are_set); | |
1997 | ||
1998 | /* First try for a 2-insn sequence. */ | |
1999 | ||
2000 | /* These situations are preferred because the optimizer can | |
2001 | * do more things with them: | |
2002 | * 1) mov -1, %reg | |
2003 | * sllx %reg, shift, %reg | |
2004 | * 2) mov -1, %reg | |
2005 | * srlx %reg, shift, %reg | |
2006 | * 3) mov some_small_const, %reg | |
2007 | * sllx %reg, shift, %reg | |
2008 | */ | |
2009 | if (((highest_bit_set == 63 | |
2010 | || lowest_bit_set == 0) | |
2011 | && all_bits_between_are_set != 0) | |
2a01c939 | 2012 | || ((highest_bit_set - lowest_bit_set) < 12)) |
e0d80184 | 2013 | { |
9208e4b2 | 2014 | HOST_WIDE_INT the_const = -1; |
e0d80184 DM |
2015 | int shift = lowest_bit_set; |
2016 | ||
f710f868 DM |
2017 | if ((highest_bit_set != 63 |
2018 | && lowest_bit_set != 0) | |
2019 | || all_bits_between_are_set == 0) | |
ab835497 | 2020 | { |
e0d80184 | 2021 | the_const = |
9208e4b2 | 2022 | create_simple_focus_bits (high_bits, low_bits, |
9208e4b2 | 2023 | lowest_bit_set, 0); |
ab835497 | 2024 | } |
e0d80184 | 2025 | else if (lowest_bit_set == 0) |
9208e4b2 | 2026 | shift = -(63 - highest_bit_set); |
e0d80184 | 2027 | |
f710f868 DM |
2028 | if (! SPARC_SIMM13_P (the_const)) |
2029 | abort (); | |
2030 | ||
9208e4b2 | 2031 | emit_insn (gen_safe_SET64 (temp, the_const)); |
e0d80184 | 2032 | if (shift > 0) |
9208e4b2 | 2033 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 DM |
2034 | op0, |
2035 | gen_rtx_ASHIFT (DImode, | |
2036 | temp, | |
2037 | GEN_INT (shift)))); | |
2038 | else if (shift < 0) | |
9208e4b2 | 2039 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 2040 | op0, |
9208e4b2 | 2041 | gen_rtx_LSHIFTRT (DImode, |
e0d80184 DM |
2042 | temp, |
2043 | GEN_INT (-shift)))); | |
ab835497 RK |
2044 | else |
2045 | abort (); | |
e0d80184 DM |
2046 | return; |
2047 | } | |
ab835497 | 2048 | |
e0d80184 DM |
2049 | /* Now a range of 22 or less bits set somewhere. |
2050 | * 1) sethi %hi(focus_bits), %reg | |
2051 | * sllx %reg, shift, %reg | |
2052 | * 2) sethi %hi(focus_bits), %reg | |
2053 | * srlx %reg, shift, %reg | |
2054 | */ | |
2a01c939 | 2055 | if ((highest_bit_set - lowest_bit_set) < 21) |
e0d80184 | 2056 | { |
2a01c939 | 2057 | unsigned HOST_WIDE_INT focus_bits = |
e0d80184 | 2058 | create_simple_focus_bits (high_bits, low_bits, |
ddf80874 | 2059 | lowest_bit_set, 10); |
f710f868 DM |
2060 | |
2061 | if (! SPARC_SETHI_P (focus_bits)) | |
2062 | abort (); | |
2063 | ||
9208e4b2 | 2064 | sparc_emit_set_safe_HIGH64 (temp, focus_bits); |
e0d80184 | 2065 | |
9208e4b2 | 2066 | /* If lowest_bit_set == 10 then a sethi alone could have done it. */ |
e0d80184 | 2067 | if (lowest_bit_set < 10) |
9208e4b2 | 2068 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 2069 | op0, |
9208e4b2 | 2070 | gen_rtx_LSHIFTRT (DImode, temp, |
e0d80184 | 2071 | GEN_INT (10 - lowest_bit_set)))); |
9208e4b2 DM |
2072 | else if (lowest_bit_set > 10) |
2073 | emit_insn (gen_rtx_SET (VOIDmode, | |
e0d80184 DM |
2074 | op0, |
2075 | gen_rtx_ASHIFT (DImode, temp, | |
2076 | GEN_INT (lowest_bit_set - 10)))); | |
2077 | else | |
9208e4b2 | 2078 | abort (); |
e0d80184 DM |
2079 | return; |
2080 | } | |
2081 | ||
2082 | /* 1) sethi %hi(low_bits), %reg | |
2083 | * or %reg, %lo(low_bits), %reg | |
2084 | * 2) sethi %hi(~low_bits), %reg | |
2085 | * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg | |
2086 | */ | |
2087 | if (high_bits == 0 | |
2a01c939 | 2088 | || high_bits == 0xffffffff) |
5f78aa30 JC |
2089 | { |
2090 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, | |
2091 | (high_bits == 0xffffffff)); | |
2092 | return; | |
2093 | } | |
e0d80184 | 2094 | |
f710f868 DM |
2095 | /* Now, try 3-insn sequences. */ |
2096 | ||
e0d80184 DM |
2097 | /* 1) sethi %hi(high_bits), %reg |
2098 | * or %reg, %lo(high_bits), %reg | |
2099 | * sllx %reg, 32, %reg | |
2100 | */ | |
f710f868 | 2101 | if (low_bits == 0) |
5f78aa30 | 2102 | { |
f710f868 | 2103 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); |
5f78aa30 JC |
2104 | return; |
2105 | } | |
e0d80184 | 2106 | |
f710f868 DM |
2107 | /* We may be able to do something quick |
2108 | when the constant is negated, so try that. */ | |
e0d80184 DM |
2109 | if (const64_is_2insns ((~high_bits) & 0xffffffff, |
2110 | (~low_bits) & 0xfffffc00)) | |
2111 | { | |
5108f3e5 DM |
2112 | /* NOTE: The trailing bits get XOR'd so we need the |
2113 | non-negated bits, not the negated ones. */ | |
2114 | unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; | |
e0d80184 DM |
2115 | |
2116 | if ((((~high_bits) & 0xffffffff) == 0 | |
2117 | && ((~low_bits) & 0x80000000) == 0) | |
2118 | || (((~high_bits) & 0xffffffff) == 0xffffffff | |
2119 | && ((~low_bits) & 0x80000000) != 0)) | |
ab835497 | 2120 | { |
5108f3e5 | 2121 | int fast_int = (~low_bits & 0xffffffff); |
e0d80184 | 2122 | |
5108f3e5 DM |
2123 | if ((SPARC_SETHI_P (fast_int) |
2124 | && (~high_bits & 0xffffffff) == 0) | |
2125 | || SPARC_SIMM13_P (fast_int)) | |
9208e4b2 | 2126 | emit_insn (gen_safe_SET64 (temp, fast_int)); |
ab835497 | 2127 | else |
9208e4b2 | 2128 | sparc_emit_set_const64 (temp, GEN_INT64 (fast_int)); |
ab835497 | 2129 | } |
e0d80184 DM |
2130 | else |
2131 | { | |
2132 | rtx negated_const; | |
2133 | #if HOST_BITS_PER_WIDE_INT == 64 | |
2134 | negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | | |
2135 | (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); | |
2136 | #else | |
5692c7bc ZW |
2137 | negated_const = immed_double_const ((~low_bits) & 0xfffffc00, |
2138 | (~high_bits) & 0xffffffff, | |
2139 | DImode); | |
e0d80184 DM |
2140 | #endif |
2141 | sparc_emit_set_const64 (temp, negated_const); | |
2142 | } | |
5108f3e5 DM |
2143 | |
2144 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
2145 | instead. This way the combiner will notice logical operations | |
2146 | such as ANDN later on and substitute. */ | |
2147 | if (trailing_bits == 0x3ff) | |
2148 | { | |
2149 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
2150 | gen_rtx_NOT (DImode, temp))); | |
2151 | } | |
2152 | else | |
2153 | { | |
2154 | emit_insn (gen_rtx_SET (VOIDmode, | |
2155 | op0, | |
2156 | gen_safe_XOR64 (temp, | |
2157 | (-0x400 | trailing_bits)))); | |
2158 | } | |
e0d80184 | 2159 | return; |
ab835497 | 2160 | } |
ab835497 | 2161 | |
e0d80184 DM |
2162 | /* 1) sethi %hi(xxx), %reg |
2163 | * or %reg, %lo(xxx), %reg | |
2164 | * sllx %reg, yyy, %reg | |
f710f868 DM |
2165 | * |
2166 | * ??? This is just a generalized version of the low_bits==0 | |
2167 | * thing above, FIXME... | |
e0d80184 DM |
2168 | */ |
2169 | if ((highest_bit_set - lowest_bit_set) < 32) | |
2170 | { | |
f710f868 DM |
2171 | unsigned HOST_WIDE_INT focus_bits = |
2172 | create_simple_focus_bits (high_bits, low_bits, | |
ddf80874 | 2173 | lowest_bit_set, 0); |
ab835497 | 2174 | |
e0d80184 DM |
2175 | /* We can't get here in this state. */ |
2176 | if (highest_bit_set < 32 | |
2177 | || lowest_bit_set >= 32) | |
9208e4b2 | 2178 | abort (); |
95726648 | 2179 | |
e0d80184 DM |
2180 | /* So what we know is that the set bits straddle the |
2181 | middle of the 64-bit word. */ | |
5f78aa30 JC |
2182 | sparc_emit_set_const64_quick2 (op0, temp, |
2183 | focus_bits, 0, | |
2184 | lowest_bit_set); | |
2185 | return; | |
e0d80184 | 2186 | } |
c85f7c16 | 2187 | |
f710f868 DM |
2188 | /* 1) sethi %hi(high_bits), %reg |
2189 | * or %reg, %lo(high_bits), %reg | |
2190 | * sllx %reg, 32, %reg | |
2191 | * or %reg, low_bits, %reg | |
2192 | */ | |
2193 | if (SPARC_SIMM13_P(low_bits) | |
2194 | && ((int)low_bits > 0)) | |
2195 | { | |
2196 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); | |
2197 | return; | |
2198 | } | |
2199 | ||
80ffc95e | 2200 | /* The easiest way when all else fails, is full decomposition. */ |
e0d80184 DM |
2201 | #if 0 |
2202 | printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", | |
2203 | high_bits, low_bits, ~high_bits, ~low_bits); | |
2204 | #endif | |
2205 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); | |
c85f7c16 JL |
2206 | } |
2207 | ||
e267e177 RH |
2208 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
2209 | return the mode to be used for the comparison. For floating-point, | |
2210 | CCFP[E]mode is used. CC_NOOVmode should be used when the first operand | |
2211 | is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special | |
2212 | processing is needed. */ | |
2213 | ||
2214 | enum machine_mode | |
2215 | select_cc_mode (op, x, y) | |
2216 | enum rtx_code op; | |
2217 | rtx x; | |
2218 | rtx y ATTRIBUTE_UNUSED; | |
2219 | { | |
2220 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2221 | { | |
2222 | switch (op) | |
2223 | { | |
2224 | case EQ: | |
2225 | case NE: | |
2226 | case UNORDERED: | |
2227 | case ORDERED: | |
2228 | case UNLT: | |
2229 | case UNLE: | |
2230 | case UNGT: | |
2231 | case UNGE: | |
2232 | case UNEQ: | |
7913f3d0 | 2233 | case LTGT: |
e267e177 RH |
2234 | return CCFPmode; |
2235 | ||
2236 | case LT: | |
2237 | case LE: | |
2238 | case GT: | |
2239 | case GE: | |
2240 | return CCFPEmode; | |
2241 | ||
2242 | default: | |
2243 | abort (); | |
2244 | } | |
2245 | } | |
2246 | else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
2247 | || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) | |
2248 | { | |
2249 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
2250 | return CCX_NOOVmode; | |
2251 | else | |
2252 | return CC_NOOVmode; | |
2253 | } | |
2254 | else | |
2255 | { | |
2256 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
2257 | return CCXmode; | |
2258 | else | |
2259 | return CCmode; | |
2260 | } | |
2261 | } | |
2262 | ||
e0d80184 DM |
2263 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
2264 | return the rtx for the cc reg in the proper mode. */ | |
c85f7c16 | 2265 | |
e0d80184 DM |
2266 | rtx |
2267 | gen_compare_reg (code, x, y) | |
2268 | enum rtx_code code; | |
2269 | rtx x, y; | |
c85f7c16 | 2270 | { |
e0d80184 DM |
2271 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); |
2272 | rtx cc_reg; | |
c85f7c16 | 2273 | |
e0d80184 DM |
2274 | /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the |
2275 | fcc regs (cse can't tell they're really call clobbered regs and will | |
2276 | remove a duplicate comparison even if there is an intervening function | |
2277 | call - it will then try to reload the cc reg via an int reg which is why | |
2278 | we need the movcc patterns). It is possible to provide the movcc | |
2279 | patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two | |
2280 | registers (say %g1,%g5) and it takes about 6 insns. A better fix would be | |
2281 | to tell cse that CCFPE mode registers (even pseudos) are call | |
2282 | clobbered. */ | |
c85f7c16 | 2283 | |
e0d80184 DM |
2284 | /* ??? This is an experiment. Rather than making changes to cse which may |
2285 | or may not be easy/clean, we do our own cse. This is possible because | |
2286 | we will generate hard registers. Cse knows they're call clobbered (it | |
2287 | doesn't know the same thing about pseudos). If we guess wrong, no big | |
2288 | deal, but if we win, great! */ | |
c85f7c16 | 2289 | |
e0d80184 DM |
2290 | if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) |
2291 | #if 1 /* experiment */ | |
284d86e9 | 2292 | { |
e0d80184 DM |
2293 | int reg; |
2294 | /* We cycle through the registers to ensure they're all exercised. */ | |
2295 | static int next_fcc_reg = 0; | |
2296 | /* Previous x,y for each fcc reg. */ | |
2297 | static rtx prev_args[4][2]; | |
284d86e9 | 2298 | |
e0d80184 DM |
2299 | /* Scan prev_args for x,y. */ |
2300 | for (reg = 0; reg < 4; reg++) | |
2301 | if (prev_args[reg][0] == x && prev_args[reg][1] == y) | |
2302 | break; | |
2303 | if (reg == 4) | |
2304 | { | |
2305 | reg = next_fcc_reg; | |
2306 | prev_args[reg][0] = x; | |
2307 | prev_args[reg][1] = y; | |
2308 | next_fcc_reg = (next_fcc_reg + 1) & 3; | |
2309 | } | |
2310 | cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); | |
284d86e9 | 2311 | } |
e0d80184 DM |
2312 | #else |
2313 | cc_reg = gen_reg_rtx (mode); | |
2314 | #endif /* ! experiment */ | |
2315 | else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2316 | cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); | |
2317 | else | |
2318 | cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); | |
284d86e9 | 2319 | |
e0d80184 DM |
2320 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, |
2321 | gen_rtx_COMPARE (mode, x, y))); | |
c85f7c16 | 2322 | |
e0d80184 DM |
2323 | return cc_reg; |
2324 | } | |
c85f7c16 | 2325 | |
e0d80184 DM |
2326 | /* This function is used for v9 only. |
2327 | CODE is the code for an Scc's comparison. | |
2328 | OPERANDS[0] is the target of the Scc insn. | |
2329 | OPERANDS[1] is the value we compare against const0_rtx (which hasn't | |
2330 | been generated yet). | |
c85f7c16 | 2331 | |
e0d80184 | 2332 | This function is needed to turn |
ab835497 | 2333 | |
e0d80184 DM |
2334 | (set (reg:SI 110) |
2335 | (gt (reg:CCX 100 %icc) | |
2336 | (const_int 0))) | |
2337 | into | |
2338 | (set (reg:SI 110) | |
2339 | (gt:DI (reg:CCX 100 %icc) | |
2340 | (const_int 0))) | |
2341 | ||
2342 | IE: The instruction recognizer needs to see the mode of the comparison to | |
2343 | find the right instruction. We could use "gt:DI" right in the | |
2344 | define_expand, but leaving it out allows us to handle DI, SI, etc. | |
ab835497 | 2345 | |
e0d80184 DM |
2346 | We refer to the global sparc compare operands sparc_compare_op0 and |
2347 | sparc_compare_op1. */ | |
ab835497 RK |
2348 | |
2349 | int | |
e0d80184 DM |
2350 | gen_v9_scc (compare_code, operands) |
2351 | enum rtx_code compare_code; | |
2352 | register rtx *operands; | |
ab835497 | 2353 | { |
e0d80184 | 2354 | rtx temp, op0, op1; |
ab835497 | 2355 | |
e0d80184 DM |
2356 | if (! TARGET_ARCH64 |
2357 | && (GET_MODE (sparc_compare_op0) == DImode | |
2358 | || GET_MODE (operands[0]) == DImode)) | |
2359 | return 0; | |
7e2feebf | 2360 | |
a42519be | 2361 | op0 = sparc_compare_op0; |
e0d80184 DM |
2362 | op1 = sparc_compare_op1; |
2363 | ||
2364 | /* Try to use the movrCC insns. */ | |
2365 | if (TARGET_ARCH64 | |
2366 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
2367 | && op1 == const0_rtx | |
2368 | && v9_regcmp_p (compare_code)) | |
ab835497 | 2369 | { |
e0d80184 | 2370 | /* Special case for op0 != 0. This can be done with one instruction if |
a42519be | 2371 | operands[0] == sparc_compare_op0. */ |
e0d80184 DM |
2372 | |
2373 | if (compare_code == NE | |
2374 | && GET_MODE (operands[0]) == DImode | |
a42519be | 2375 | && rtx_equal_p (op0, operands[0])) |
ab835497 | 2376 | { |
e0d80184 DM |
2377 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], |
2378 | gen_rtx_IF_THEN_ELSE (DImode, | |
2379 | gen_rtx_fmt_ee (compare_code, DImode, | |
2380 | op0, const0_rtx), | |
2381 | const1_rtx, | |
2382 | operands[0]))); | |
ab835497 RK |
2383 | return 1; |
2384 | } | |
e0d80184 | 2385 | |
a42519be JJ |
2386 | if (reg_overlap_mentioned_p (operands[0], op0)) |
2387 | { | |
2388 | /* Handle the case where operands[0] == sparc_compare_op0. | |
2389 | We "early clobber" the result. */ | |
2390 | op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); | |
2391 | emit_move_insn (op0, sparc_compare_op0); | |
2392 | } | |
2393 | ||
e0d80184 DM |
2394 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); |
2395 | if (GET_MODE (op0) != DImode) | |
ab835497 | 2396 | { |
e0d80184 DM |
2397 | temp = gen_reg_rtx (DImode); |
2398 | convert_move (temp, op0, 0); | |
ab835497 | 2399 | } |
e0d80184 DM |
2400 | else |
2401 | temp = op0; | |
2402 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2403 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2404 | gen_rtx_fmt_ee (compare_code, DImode, | |
2405 | temp, const0_rtx), | |
2406 | const1_rtx, | |
2407 | operands[0]))); | |
95726648 DE |
2408 | return 1; |
2409 | } | |
e0d80184 | 2410 | else |
ab835497 | 2411 | { |
e0d80184 | 2412 | operands[1] = gen_compare_reg (compare_code, op0, op1); |
ab835497 | 2413 | |
e0d80184 | 2414 | switch (GET_MODE (operands[1])) |
ab835497 | 2415 | { |
e0d80184 DM |
2416 | case CCmode : |
2417 | case CCXmode : | |
2418 | case CCFPEmode : | |
2419 | case CCFPmode : | |
2420 | break; | |
2421 | default : | |
2422 | abort (); | |
ab835497 | 2423 | } |
e0d80184 DM |
2424 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); |
2425 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2426 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2427 | gen_rtx_fmt_ee (compare_code, | |
2428 | GET_MODE (operands[1]), | |
2429 | operands[1], const0_rtx), | |
2430 | const1_rtx, operands[0]))); | |
2431 | return 1; | |
ab835497 | 2432 | } |
ab835497 | 2433 | } |
4fb4e4b8 | 2434 | |
e0d80184 DM |
2435 | /* Emit a conditional jump insn for the v9 architecture using comparison code |
2436 | CODE and jump target LABEL. | |
2437 | This function exists to take advantage of the v9 brxx insns. */ | |
ab835497 | 2438 | |
e0d80184 DM |
2439 | void |
2440 | emit_v9_brxx_insn (code, op0, label) | |
2441 | enum rtx_code code; | |
2442 | rtx op0, label; | |
ab835497 | 2443 | { |
e0d80184 DM |
2444 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
2445 | pc_rtx, | |
2446 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
2447 | gen_rtx_fmt_ee (code, GET_MODE (op0), | |
2448 | op0, const0_rtx), | |
2449 | gen_rtx_LABEL_REF (VOIDmode, label), | |
2450 | pc_rtx))); | |
2451 | } | |
7b1ac798 JJ |
2452 | |
2453 | /* Generate a DFmode part of a hard TFmode register. | |
2454 | REG is the TFmode hard register, LOW is 1 for the | |
2455 | low 64bit of the register and 0 otherwise. | |
2456 | */ | |
2457 | rtx | |
2458 | gen_df_reg (reg, low) | |
2459 | rtx reg; | |
2460 | int low; | |
2461 | { | |
2462 | int regno = REGNO (reg); | |
2463 | ||
2464 | if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) | |
2aac41d6 | 2465 | regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2; |
7b1ac798 JJ |
2466 | return gen_rtx_REG (DFmode, regno); |
2467 | } | |
e0d80184 | 2468 | \f |
73985940 RH |
2469 | /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value. |
2470 | Unlike normal calls, TFmode operands are passed by reference. It is | |
2471 | assumed that no more than 3 operands are required. */ | |
2472 | ||
2473 | static void | |
2474 | emit_soft_tfmode_libcall (func_name, nargs, operands) | |
2475 | const char *func_name; | |
2476 | int nargs; | |
2477 | rtx *operands; | |
2478 | { | |
2479 | rtx ret_slot = NULL, arg[3], func_sym; | |
4e7d5d27 | 2480 | int i; |
73985940 RH |
2481 | |
2482 | /* We only expect to be called for conversions, unary, and binary ops. */ | |
2483 | if (nargs < 2 || nargs > 3) | |
2484 | abort (); | |
2485 | ||
2486 | for (i = 0; i < nargs; ++i) | |
2487 | { | |
2488 | rtx this_arg = operands[i]; | |
2489 | rtx this_slot; | |
2490 | ||
2491 | /* TFmode arguments and return values are passed by reference. */ | |
2492 | if (GET_MODE (this_arg) == TFmode) | |
2493 | { | |
4e7d5d27 DM |
2494 | int force_stack_temp; |
2495 | ||
2496 | force_stack_temp = 0; | |
2497 | if (TARGET_BUGGY_QP_LIB && i == 0) | |
2498 | force_stack_temp = 1; | |
2499 | ||
2500 | if (GET_CODE (this_arg) == MEM | |
2501 | && ! force_stack_temp) | |
2502 | this_arg = XEXP (this_arg, 0); | |
2503 | else if (CONSTANT_P (this_arg) | |
2504 | && ! force_stack_temp) | |
73985940 RH |
2505 | { |
2506 | this_slot = force_const_mem (TFmode, this_arg); | |
2507 | this_arg = XEXP (this_slot, 0); | |
2508 | } | |
2509 | else | |
2510 | { | |
2511 | this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0); | |
2512 | ||
2513 | /* Operand 0 is the return value. We'll copy it out later. */ | |
2514 | if (i > 0) | |
2515 | emit_move_insn (this_slot, this_arg); | |
2516 | else | |
2517 | ret_slot = this_slot; | |
2518 | ||
2519 | this_arg = XEXP (this_slot, 0); | |
2520 | } | |
2521 | } | |
2522 | ||
2523 | arg[i] = this_arg; | |
2524 | } | |
2525 | ||
2526 | func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name); | |
2527 | ||
2528 | if (GET_MODE (operands[0]) == TFmode) | |
2529 | { | |
2530 | if (nargs == 2) | |
2531 | emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2, | |
2532 | arg[0], GET_MODE (arg[0]), | |
2533 | arg[1], GET_MODE (arg[1])); | |
2534 | else | |
2535 | emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3, | |
2536 | arg[0], GET_MODE (arg[0]), | |
2537 | arg[1], GET_MODE (arg[1]), | |
2538 | arg[2], GET_MODE (arg[2])); | |
2539 | ||
2540 | if (ret_slot) | |
2541 | emit_move_insn (operands[0], ret_slot); | |
2542 | } | |
2543 | else | |
2544 | { | |
2545 | rtx ret; | |
2546 | ||
2547 | if (nargs != 2) | |
2548 | abort (); | |
2549 | ||
2550 | ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL, | |
2551 | GET_MODE (operands[0]), 1, | |
2552 | arg[1], GET_MODE (arg[1])); | |
2553 | ||
2554 | if (ret != operands[0]) | |
2555 | emit_move_insn (operands[0], ret); | |
2556 | } | |
2557 | } | |
2558 | ||
2559 | /* Expand soft-float TFmode calls to sparc abi routines. */ | |
2560 | ||
2561 | static void | |
2562 | emit_soft_tfmode_binop (code, operands) | |
2563 | enum rtx_code code; | |
2564 | rtx *operands; | |
2565 | { | |
2566 | const char *func; | |
2567 | ||
2568 | switch (code) | |
2569 | { | |
2570 | case PLUS: | |
2571 | func = "_Qp_add"; | |
2572 | break; | |
2573 | case MINUS: | |
2574 | func = "_Qp_sub"; | |
2575 | break; | |
2576 | case MULT: | |
2577 | func = "_Qp_mul"; | |
2578 | break; | |
2579 | case DIV: | |
2580 | func = "_Qp_div"; | |
2581 | break; | |
2582 | default: | |
2583 | abort (); | |
2584 | } | |
2585 | ||
2586 | emit_soft_tfmode_libcall (func, 3, operands); | |
2587 | } | |
2588 | ||
2589 | static void | |
2590 | emit_soft_tfmode_unop (code, operands) | |
2591 | enum rtx_code code; | |
2592 | rtx *operands; | |
2593 | { | |
2594 | const char *func; | |
2595 | ||
2596 | switch (code) | |
2597 | { | |
2598 | case SQRT: | |
2599 | func = "_Qp_sqrt"; | |
2600 | break; | |
2601 | default: | |
2602 | abort (); | |
2603 | } | |
2604 | ||
2605 | emit_soft_tfmode_libcall (func, 2, operands); | |
2606 | } | |
2607 | ||
2608 | static void | |
2609 | emit_soft_tfmode_cvt (code, operands) | |
2610 | enum rtx_code code; | |
2611 | rtx *operands; | |
2612 | { | |
2613 | const char *func; | |
2614 | ||
2615 | switch (code) | |
2616 | { | |
2617 | case FLOAT_EXTEND: | |
2618 | switch (GET_MODE (operands[1])) | |
2619 | { | |
2620 | case SFmode: | |
2621 | func = "_Qp_stoq"; | |
2622 | break; | |
2623 | case DFmode: | |
2624 | func = "_Qp_dtoq"; | |
2625 | break; | |
2626 | default: | |
2627 | abort (); | |
2628 | } | |
2629 | break; | |
2630 | ||
2631 | case FLOAT_TRUNCATE: | |
2632 | switch (GET_MODE (operands[0])) | |
2633 | { | |
2634 | case SFmode: | |
2635 | func = "_Qp_qtos"; | |
2636 | break; | |
2637 | case DFmode: | |
2638 | func = "_Qp_qtod"; | |
2639 | break; | |
2640 | default: | |
2641 | abort (); | |
2642 | } | |
2643 | break; | |
2644 | ||
2645 | case FLOAT: | |
2646 | switch (GET_MODE (operands[1])) | |
2647 | { | |
2648 | case SImode: | |
2649 | func = "_Qp_itoq"; | |
2650 | break; | |
2651 | case DImode: | |
2652 | func = "_Qp_xtoq"; | |
2653 | break; | |
2654 | default: | |
2655 | abort (); | |
2656 | } | |
2657 | break; | |
2658 | ||
2659 | case UNSIGNED_FLOAT: | |
2660 | switch (GET_MODE (operands[1])) | |
2661 | { | |
2662 | case SImode: | |
2663 | func = "_Qp_uitoq"; | |
2664 | break; | |
2665 | case DImode: | |
2666 | func = "_Qp_uxtoq"; | |
2667 | break; | |
2668 | default: | |
2669 | abort (); | |
2670 | } | |
2671 | break; | |
2672 | ||
2673 | case FIX: | |
2674 | switch (GET_MODE (operands[0])) | |
2675 | { | |
2676 | case SImode: | |
2677 | func = "_Qp_qtoi"; | |
2678 | break; | |
2679 | case DImode: | |
2680 | func = "_Qp_qtox"; | |
2681 | break; | |
2682 | default: | |
2683 | abort (); | |
2684 | } | |
2685 | break; | |
2686 | ||
2687 | case UNSIGNED_FIX: | |
2688 | switch (GET_MODE (operands[0])) | |
2689 | { | |
2690 | case SImode: | |
2691 | func = "_Qp_qtoui"; | |
2692 | break; | |
2693 | case DImode: | |
2694 | func = "_Qp_qtoux"; | |
2695 | break; | |
2696 | default: | |
2697 | abort (); | |
2698 | } | |
2699 | break; | |
2700 | ||
2701 | default: | |
2702 | abort (); | |
2703 | } | |
2704 | ||
2705 | emit_soft_tfmode_libcall (func, 2, operands); | |
2706 | } | |
2707 | ||
2708 | /* Expand a hard-float tfmode operation. All arguments must be in | |
2709 | registers. */ | |
2710 | ||
2711 | static void | |
2712 | emit_hard_tfmode_operation (code, operands) | |
2713 | enum rtx_code code; | |
2714 | rtx *operands; | |
2715 | { | |
2716 | rtx op, dest; | |
2717 | ||
2718 | if (GET_RTX_CLASS (code) == '1') | |
2719 | { | |
2720 | operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); | |
2721 | op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]); | |
2722 | } | |
2723 | else | |
2724 | { | |
2725 | operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); | |
2726 | operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); | |
2727 | op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]), | |
2728 | operands[1], operands[2]); | |
2729 | } | |
2730 | ||
2731 | if (register_operand (operands[0], VOIDmode)) | |
2732 | dest = operands[0]; | |
2733 | else | |
2734 | dest = gen_reg_rtx (GET_MODE (operands[0])); | |
2735 | ||
2736 | emit_insn (gen_rtx_SET (VOIDmode, dest, op)); | |
2737 | ||
2738 | if (dest != operands[0]) | |
2739 | emit_move_insn (operands[0], dest); | |
2740 | } | |
2741 | ||
2742 | void | |
2743 | emit_tfmode_binop (code, operands) | |
2744 | enum rtx_code code; | |
2745 | rtx *operands; | |
2746 | { | |
2747 | if (TARGET_HARD_QUAD) | |
2748 | emit_hard_tfmode_operation (code, operands); | |
2749 | else | |
2750 | emit_soft_tfmode_binop (code, operands); | |
2751 | } | |
2752 | ||
2753 | void | |
2754 | emit_tfmode_unop (code, operands) | |
2755 | enum rtx_code code; | |
2756 | rtx *operands; | |
2757 | { | |
2758 | if (TARGET_HARD_QUAD) | |
2759 | emit_hard_tfmode_operation (code, operands); | |
2760 | else | |
2761 | emit_soft_tfmode_unop (code, operands); | |
2762 | } | |
2763 | ||
2764 | void | |
2765 | emit_tfmode_cvt (code, operands) | |
2766 | enum rtx_code code; | |
2767 | rtx *operands; | |
2768 | { | |
2769 | if (TARGET_HARD_QUAD) | |
2770 | emit_hard_tfmode_operation (code, operands); | |
2771 | else | |
2772 | emit_soft_tfmode_cvt (code, operands); | |
2773 | } | |
2774 | \f | |
e0d80184 DM |
2775 | /* Return nonzero if a return peephole merging return with |
2776 | setting of output register is ok. */ | |
2777 | int | |
2778 | leaf_return_peephole_ok () | |
2779 | { | |
2780 | return (actual_fsize == 0); | |
2781 | } | |
284d86e9 | 2782 | |
f17f9332 JJ |
2783 | /* Return nonzero if a branch/jump/call instruction will be emitting |
2784 | nop into its delay slot. */ | |
2785 | ||
2786 | int | |
2787 | empty_delay_slot (insn) | |
2788 | rtx insn; | |
2789 | { | |
2790 | rtx seq; | |
2791 | ||
2792 | /* If no previous instruction (should not happen), return true. */ | |
2793 | if (PREV_INSN (insn) == NULL) | |
2794 | return 1; | |
2795 | ||
2796 | seq = NEXT_INSN (PREV_INSN (insn)); | |
2797 | if (GET_CODE (PATTERN (seq)) == SEQUENCE) | |
2798 | return 0; | |
2799 | ||
2800 | return 1; | |
2801 | } | |
2802 | ||
e0d80184 DM |
2803 | /* Return nonzero if TRIAL can go into the function epilogue's |
2804 | delay slot. SLOT is the slot we are trying to fill. */ | |
ab835497 | 2805 | |
e0d80184 DM |
2806 | int |
2807 | eligible_for_epilogue_delay (trial, slot) | |
2808 | rtx trial; | |
2809 | int slot; | |
2810 | { | |
2811 | rtx pat, src; | |
4fb4e4b8 | 2812 | |
e0d80184 DM |
2813 | if (slot >= 1) |
2814 | return 0; | |
4fb4e4b8 | 2815 | |
e0d80184 DM |
2816 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) |
2817 | return 0; | |
4fb4e4b8 | 2818 | |
e0d80184 DM |
2819 | if (get_attr_length (trial) != 1) |
2820 | return 0; | |
4fb4e4b8 | 2821 | |
e48addee JJ |
2822 | /* If there are any call-saved registers, we should scan TRIAL if it |
2823 | does not reference them. For now just make it easy. */ | |
2824 | if (num_gfregs) | |
2825 | return 0; | |
4fb4e4b8 | 2826 | |
1150a841 RH |
2827 | /* If the function uses __builtin_eh_return, the eh_return machinery |
2828 | occupies the delay slot. */ | |
2829 | if (current_function_calls_eh_return) | |
2830 | return 0; | |
2831 | ||
e0d80184 DM |
2832 | /* In the case of a true leaf function, anything can go into the delay slot. |
2833 | A delay slot only exists however if the frame size is zero, otherwise | |
2834 | we will put an insn to adjust the stack after the return. */ | |
54ff41b7 | 2835 | if (current_function_uses_only_leaf_regs) |
4fb4e4b8 | 2836 | { |
e0d80184 DM |
2837 | if (leaf_return_peephole_ok ()) |
2838 | return ((get_attr_in_uncond_branch_delay (trial) | |
2839 | == IN_BRANCH_DELAY_TRUE)); | |
2840 | return 0; | |
4fb4e4b8 | 2841 | } |
4fb4e4b8 | 2842 | |
e0d80184 | 2843 | pat = PATTERN (trial); |
795068a4 | 2844 | |
e0d80184 | 2845 | /* Otherwise, only operations which can be done in tandem with |
e48addee | 2846 | a `restore' or `return' insn can go into the delay slot. */ |
e0d80184 | 2847 | if (GET_CODE (SET_DEST (pat)) != REG |
e0d80184 DM |
2848 | || REGNO (SET_DEST (pat)) < 24) |
2849 | return 0; | |
795068a4 | 2850 | |
c137830f JJ |
2851 | /* If this instruction sets up floating point register and we have a return |
2852 | instruction, it can probably go in. But restore will not work | |
2853 | with FP_REGS. */ | |
2854 | if (REGNO (SET_DEST (pat)) >= 32) | |
2855 | { | |
2856 | if (TARGET_V9 && ! epilogue_renumber (&pat, 1) | |
2857 | && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) | |
2858 | return 1; | |
2859 | return 0; | |
2860 | } | |
2861 | ||
e0d80184 DM |
2862 | /* The set of insns matched here must agree precisely with the set of |
2863 | patterns paired with a RETURN in sparc.md. */ | |
795068a4 | 2864 | |
e0d80184 | 2865 | src = SET_SRC (pat); |
795068a4 | 2866 | |
3c6088d2 | 2867 | /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */ |
3ec6f1a9 RK |
2868 | if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2869 | && arith_operand (src, GET_MODE (src))) | |
3c6088d2 JJ |
2870 | { |
2871 | if (TARGET_ARCH64) | |
2872 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2873 | else | |
2874 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
2875 | } | |
e48addee | 2876 | |
e0d80184 | 2877 | /* This matches "*return_di". */ |
3ec6f1a9 RK |
2878 | else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2879 | && arith_double_operand (src, GET_MODE (src))) | |
e0d80184 | 2880 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); |
795068a4 | 2881 | |
e0d80184 DM |
2882 | /* This matches "*return_sf_no_fpu". */ |
2883 | else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) | |
2884 | && register_operand (src, SFmode)) | |
2885 | return 1; | |
f5da225e | 2886 | |
e48addee JJ |
2887 | /* If we have return instruction, anything that does not use |
2888 | local or output registers and can go into a delay slot wins. */ | |
2889 | else if (TARGET_V9 && ! epilogue_renumber (&pat, 1) | |
2890 | && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) | |
2891 | return 1; | |
2892 | ||
e0d80184 DM |
2893 | /* This matches "*return_addsi". */ |
2894 | else if (GET_CODE (src) == PLUS | |
2895 | && arith_operand (XEXP (src, 0), SImode) | |
2896 | && arith_operand (XEXP (src, 1), SImode) | |
2897 | && (register_operand (XEXP (src, 0), SImode) | |
2898 | || register_operand (XEXP (src, 1), SImode))) | |
2899 | return 1; | |
2900 | ||
2901 | /* This matches "*return_adddi". */ | |
2902 | else if (GET_CODE (src) == PLUS | |
2903 | && arith_double_operand (XEXP (src, 0), DImode) | |
2904 | && arith_double_operand (XEXP (src, 1), DImode) | |
2905 | && (register_operand (XEXP (src, 0), DImode) | |
2906 | || register_operand (XEXP (src, 1), DImode))) | |
795068a4 | 2907 | return 1; |
795068a4 | 2908 | |
e48addee JJ |
2909 | /* This can match "*return_losum_[sd]i". |
2910 | Catch only some cases, so that return_losum* don't have | |
2911 | to be too big. */ | |
2912 | else if (GET_CODE (src) == LO_SUM | |
2913 | && ! TARGET_CM_MEDMID | |
2914 | && ((register_operand (XEXP (src, 0), SImode) | |
2915 | && immediate_operand (XEXP (src, 1), SImode)) | |
2916 | || (TARGET_ARCH64 | |
2917 | && register_operand (XEXP (src, 0), DImode) | |
2918 | && immediate_operand (XEXP (src, 1), DImode)))) | |
2919 | return 1; | |
2920 | ||
2921 | /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */ | |
2922 | else if (GET_CODE (src) == ASHIFT | |
2923 | && (register_operand (XEXP (src, 0), SImode) | |
2924 | || register_operand (XEXP (src, 0), DImode)) | |
2925 | && XEXP (src, 1) == const1_rtx) | |
2926 | return 1; | |
2927 | ||
795068a4 JW |
2928 | return 0; |
2929 | } | |
2930 | ||
7d167afd JJ |
2931 | /* Return nonzero if TRIAL can go into the sibling call |
2932 | delay slot. */ | |
2933 | ||
2934 | int | |
2935 | eligible_for_sibcall_delay (trial) | |
2936 | rtx trial; | |
2937 | { | |
2938 | rtx pat, src; | |
2939 | ||
2940 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) | |
2941 | return 0; | |
2942 | ||
8456b95a | 2943 | if (get_attr_length (trial) != 1) |
7d167afd JJ |
2944 | return 0; |
2945 | ||
2946 | pat = PATTERN (trial); | |
2947 | ||
2948 | if (current_function_uses_only_leaf_regs) | |
2949 | { | |
2950 | /* If the tail call is done using the call instruction, | |
2951 | we have to restore %o7 in the delay slot. */ | |
2be5e524 | 2952 | if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic) |
7d167afd JJ |
2953 | return 0; |
2954 | ||
2955 | /* %g1 is used to build the function address */ | |
2956 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) | |
2957 | return 0; | |
2958 | ||
2959 | return 1; | |
2960 | } | |
2961 | ||
2962 | /* Otherwise, only operations which can be done in tandem with | |
2963 | a `restore' insn can go into the delay slot. */ | |
2964 | if (GET_CODE (SET_DEST (pat)) != REG | |
2965 | || REGNO (SET_DEST (pat)) < 24 | |
2966 | || REGNO (SET_DEST (pat)) >= 32) | |
2967 | return 0; | |
2968 | ||
2969 | /* If it mentions %o7, it can't go in, because sibcall will clobber it | |
2970 | in most cases. */ | |
2971 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) | |
2972 | return 0; | |
2973 | ||
2974 | src = SET_SRC (pat); | |
2975 | ||
3ec6f1a9 RK |
2976 | if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2977 | && arith_operand (src, GET_MODE (src))) | |
7d167afd JJ |
2978 | { |
2979 | if (TARGET_ARCH64) | |
2980 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2981 | else | |
2982 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
2983 | } | |
2984 | ||
3ec6f1a9 RK |
2985 | else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2986 | && arith_double_operand (src, GET_MODE (src))) | |
7d167afd JJ |
2987 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); |
2988 | ||
2989 | else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) | |
2990 | && register_operand (src, SFmode)) | |
2991 | return 1; | |
2992 | ||
2993 | else if (GET_CODE (src) == PLUS | |
2994 | && arith_operand (XEXP (src, 0), SImode) | |
2995 | && arith_operand (XEXP (src, 1), SImode) | |
2996 | && (register_operand (XEXP (src, 0), SImode) | |
2997 | || register_operand (XEXP (src, 1), SImode))) | |
2998 | return 1; | |
2999 | ||
3000 | else if (GET_CODE (src) == PLUS | |
3001 | && arith_double_operand (XEXP (src, 0), DImode) | |
3002 | && arith_double_operand (XEXP (src, 1), DImode) | |
3003 | && (register_operand (XEXP (src, 0), DImode) | |
3004 | || register_operand (XEXP (src, 1), DImode))) | |
3005 | return 1; | |
3006 | ||
3007 | else if (GET_CODE (src) == LO_SUM | |
3008 | && ! TARGET_CM_MEDMID | |
3009 | && ((register_operand (XEXP (src, 0), SImode) | |
3010 | && immediate_operand (XEXP (src, 1), SImode)) | |
3011 | || (TARGET_ARCH64 | |
3012 | && register_operand (XEXP (src, 0), DImode) | |
3013 | && immediate_operand (XEXP (src, 1), DImode)))) | |
3014 | return 1; | |
3015 | ||
3016 | else if (GET_CODE (src) == ASHIFT | |
3017 | && (register_operand (XEXP (src, 0), SImode) | |
3018 | || register_operand (XEXP (src, 0), DImode)) | |
3019 | && XEXP (src, 1) == const1_rtx) | |
3020 | return 1; | |
3021 | ||
3022 | return 0; | |
3023 | } | |
3024 | ||
e0d80184 DM |
3025 | static int |
3026 | check_return_regs (x) | |
3027 | rtx x; | |
ab835497 | 3028 | { |
e0d80184 DM |
3029 | switch (GET_CODE (x)) |
3030 | { | |
3031 | case REG: | |
3032 | return IN_OR_GLOBAL_P (x); | |
ab835497 | 3033 | |
e0d80184 DM |
3034 | case CONST_INT: |
3035 | case CONST_DOUBLE: | |
3036 | case CONST: | |
3037 | case SYMBOL_REF: | |
3038 | case LABEL_REF: | |
3039 | return 1; | |
ab835497 | 3040 | |
e0d80184 DM |
3041 | case SET: |
3042 | case IOR: | |
3043 | case AND: | |
3044 | case XOR: | |
3045 | case PLUS: | |
3046 | case MINUS: | |
3047 | if (check_return_regs (XEXP (x, 1)) == 0) | |
3048 | return 0; | |
3049 | case NOT: | |
3050 | case NEG: | |
3051 | case MEM: | |
3052 | return check_return_regs (XEXP (x, 0)); | |
3053 | ||
3054 | default: | |
3055 | return 0; | |
3056 | } | |
ab835497 | 3057 | |
e0d80184 | 3058 | } |
ab835497 | 3059 | |
e0d80184 DM |
3060 | /* Return 1 if TRIAL references only in and global registers. */ |
3061 | int | |
3062 | eligible_for_return_delay (trial) | |
3063 | rtx trial; | |
3064 | { | |
3065 | if (GET_CODE (PATTERN (trial)) != SET) | |
3066 | return 0; | |
ab835497 | 3067 | |
e0d80184 DM |
3068 | return check_return_regs (PATTERN (trial)); |
3069 | } | |
ab835497 | 3070 | |
e0d80184 DM |
3071 | int |
3072 | short_branch (uid1, uid2) | |
3073 | int uid1, uid2; | |
3074 | { | |
9d98a694 | 3075 | int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2); |
77b91512 RK |
3076 | |
3077 | /* Leave a few words of "slop". */ | |
3078 | if (delta >= -1023 && delta <= 1022) | |
e0d80184 | 3079 | return 1; |
77b91512 | 3080 | |
e0d80184 DM |
3081 | return 0; |
3082 | } | |
ab835497 | 3083 | |
e0d80184 DM |
3084 | /* Return non-zero if REG is not used after INSN. |
3085 | We assume REG is a reload reg, and therefore does | |
3086 | not live past labels or calls or jumps. */ | |
3087 | int | |
3088 | reg_unused_after (reg, insn) | |
3089 | rtx reg; | |
3090 | rtx insn; | |
3091 | { | |
3092 | enum rtx_code code, prev_code = UNKNOWN; | |
ab835497 | 3093 | |
e0d80184 | 3094 | while ((insn = NEXT_INSN (insn))) |
61a55e8b | 3095 | { |
e0d80184 DM |
3096 | if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) |
3097 | return 1; | |
ab835497 | 3098 | |
e0d80184 DM |
3099 | code = GET_CODE (insn); |
3100 | if (GET_CODE (insn) == CODE_LABEL) | |
3101 | return 1; | |
bc961ed7 | 3102 | |
e0d80184 | 3103 | if (GET_RTX_CLASS (code) == 'i') |
61a55e8b | 3104 | { |
e0d80184 DM |
3105 | rtx set = single_set (insn); |
3106 | int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); | |
3107 | if (set && in_src) | |
3108 | return 0; | |
3109 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
3110 | return 1; | |
3111 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
3112 | return 0; | |
61a55e8b | 3113 | } |
e0d80184 | 3114 | prev_code = code; |
61a55e8b | 3115 | } |
e0d80184 DM |
3116 | return 1; |
3117 | } | |
3118 | \f | |
3119 | /* The table we use to reference PIC data. */ | |
3120 | static rtx global_offset_table; | |
bc961ed7 | 3121 | |
e0d80184 DM |
3122 | /* The function we use to get at it. */ |
3123 | static rtx get_pc_symbol; | |
3124 | static char get_pc_symbol_name[256]; | |
ab835497 | 3125 | |
e0d80184 | 3126 | /* Ensure that we are not using patterns that are not OK with PIC. */ |
795068a4 | 3127 | |
e0d80184 DM |
3128 | int |
3129 | check_pic (i) | |
3130 | int i; | |
3131 | { | |
3132 | switch (flag_pic) | |
ab835497 | 3133 | { |
e0d80184 | 3134 | case 1: |
1ccbefce RH |
3135 | if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF |
3136 | || (GET_CODE (recog_data.operand[i]) == CONST | |
3137 | && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS | |
3138 | && (XEXP (XEXP (recog_data.operand[i], 0), 0) | |
e0d80184 | 3139 | == global_offset_table) |
1ccbefce | 3140 | && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) |
e0d80184 DM |
3141 | == CONST)))) |
3142 | abort (); | |
3143 | case 2: | |
3144 | default: | |
3145 | return 1; | |
ab835497 | 3146 | } |
ab835497 | 3147 | } |
795068a4 | 3148 | |
e0d80184 DM |
3149 | /* Return true if X is an address which needs a temporary register when |
3150 | reloaded while generating PIC code. */ | |
795068a4 | 3151 | |
e0d80184 DM |
3152 | int |
3153 | pic_address_needs_scratch (x) | |
3154 | rtx x; | |
795068a4 | 3155 | { |
e0d80184 DM |
3156 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ |
3157 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
3158 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
3159 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3160 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
3161 | return 1; | |
795068a4 | 3162 | |
e0d80184 DM |
3163 | return 0; |
3164 | } | |
795068a4 | 3165 | |
e0d80184 DM |
3166 | /* Legitimize PIC addresses. If the address is already position-independent, |
3167 | we return ORIG. Newly generated position-independent addresses go into a | |
3168 | reg. This is REG if non zero, otherwise we allocate register(s) as | |
3169 | necessary. */ | |
795068a4 | 3170 | |
e0d80184 DM |
3171 | rtx |
3172 | legitimize_pic_address (orig, mode, reg) | |
3173 | rtx orig; | |
3174 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3175 | rtx reg; | |
3176 | { | |
3177 | if (GET_CODE (orig) == SYMBOL_REF) | |
82d6b402 | 3178 | { |
e0d80184 DM |
3179 | rtx pic_ref, address; |
3180 | rtx insn; | |
82d6b402 | 3181 | |
e0d80184 | 3182 | if (reg == 0) |
82d6b402 | 3183 | { |
e0d80184 DM |
3184 | if (reload_in_progress || reload_completed) |
3185 | abort (); | |
3186 | else | |
3187 | reg = gen_reg_rtx (Pmode); | |
82d6b402 | 3188 | } |
795068a4 | 3189 | |
e0d80184 | 3190 | if (flag_pic == 2) |
4fb4e4b8 | 3191 | { |
e0d80184 DM |
3192 | /* If not during reload, allocate another temp reg here for loading |
3193 | in the address, so that these instructions can be optimized | |
3194 | properly. */ | |
3195 | rtx temp_reg = ((reload_in_progress || reload_completed) | |
3196 | ? reg : gen_reg_rtx (Pmode)); | |
3197 | ||
3198 | /* Must put the SYMBOL_REF inside an UNSPEC here so that cse | |
3199 | won't get confused into thinking that these two instructions | |
3200 | are loading in the true address of the symbol. If in the | |
3201 | future a PIC rtx exists, that should be used instead. */ | |
be3f1ff5 DM |
3202 | if (Pmode == SImode) |
3203 | { | |
3204 | emit_insn (gen_movsi_high_pic (temp_reg, orig)); | |
3205 | emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
3206 | } | |
3207 | else | |
3208 | { | |
3209 | emit_insn (gen_movdi_high_pic (temp_reg, orig)); | |
3210 | emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
3211 | } | |
e0d80184 | 3212 | address = temp_reg; |
4fb4e4b8 DE |
3213 | } |
3214 | else | |
e0d80184 DM |
3215 | address = orig; |
3216 | ||
3217 | pic_ref = gen_rtx_MEM (Pmode, | |
8ac61af7 RK |
3218 | gen_rtx_PLUS (Pmode, |
3219 | pic_offset_table_rtx, address)); | |
e0d80184 DM |
3220 | current_function_uses_pic_offset_table = 1; |
3221 | RTX_UNCHANGING_P (pic_ref) = 1; | |
3222 | insn = emit_move_insn (reg, pic_ref); | |
3223 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
3224 | by loop. */ | |
3225 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, | |
3226 | REG_NOTES (insn)); | |
3227 | return reg; | |
795068a4 | 3228 | } |
e0d80184 | 3229 | else if (GET_CODE (orig) == CONST) |
795068a4 | 3230 | { |
e0d80184 | 3231 | rtx base, offset; |
795068a4 | 3232 | |
e0d80184 DM |
3233 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
3234 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
3235 | return orig; | |
82d6b402 | 3236 | |
e0d80184 | 3237 | if (reg == 0) |
4fb4e4b8 | 3238 | { |
e0d80184 DM |
3239 | if (reload_in_progress || reload_completed) |
3240 | abort (); | |
3241 | else | |
3242 | reg = gen_reg_rtx (Pmode); | |
4fb4e4b8 | 3243 | } |
e0d80184 DM |
3244 | |
3245 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
4fb4e4b8 | 3246 | { |
e0d80184 DM |
3247 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
3248 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
3249 | base == reg ? 0 : reg); | |
4fb4e4b8 DE |
3250 | } |
3251 | else | |
61a66555 JW |
3252 | abort (); |
3253 | ||
e0d80184 DM |
3254 | if (GET_CODE (offset) == CONST_INT) |
3255 | { | |
3256 | if (SMALL_INT (offset)) | |
ed8908e7 | 3257 | return plus_constant (base, INTVAL (offset)); |
e0d80184 DM |
3258 | else if (! reload_in_progress && ! reload_completed) |
3259 | offset = force_reg (Pmode, offset); | |
3260 | else | |
3261 | /* If we reach here, then something is seriously wrong. */ | |
3262 | abort (); | |
3263 | } | |
3264 | return gen_rtx_PLUS (Pmode, base, offset); | |
795068a4 | 3265 | } |
e0d80184 DM |
3266 | else if (GET_CODE (orig) == LABEL_REF) |
3267 | /* ??? Why do we do this? */ | |
3268 | /* Now movsi_pic_label_ref uses it, but we ought to be checking that | |
3269 | the register is live instead, in case it is eliminated. */ | |
3270 | current_function_uses_pic_offset_table = 1; | |
795068a4 | 3271 | |
e0d80184 DM |
3272 | return orig; |
3273 | } | |
795068a4 | 3274 | |
fccf9848 | 3275 | /* Emit special PIC prologues. */ |
795068a4 | 3276 | |
e0d80184 | 3277 | void |
fccf9848 | 3278 | load_pic_register () |
e0d80184 DM |
3279 | { |
3280 | /* Labels to get the PC in the prologue of this function. */ | |
3281 | int orig_flag_pic = flag_pic; | |
4fb4e4b8 | 3282 | |
e0d80184 DM |
3283 | if (! flag_pic) |
3284 | abort (); | |
3285 | ||
d6a7951f | 3286 | /* If we haven't emitted the special get_pc helper function, do so now. */ |
e0d80184 | 3287 | if (get_pc_symbol_name[0] == 0) |
4fb4e4b8 | 3288 | { |
d676da68 | 3289 | int align; |
82d6b402 | 3290 | |
d676da68 | 3291 | ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0); |
e0d80184 | 3292 | text_section (); |
d676da68 DM |
3293 | |
3294 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
3295 | if (align > 0) | |
3296 | ASM_OUTPUT_ALIGN (asm_out_file, align); | |
e0d80184 | 3297 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0); |
4df1190a | 3298 | fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file); |
e0d80184 | 3299 | } |
82d6b402 | 3300 | |
e0d80184 DM |
3301 | /* Initialize every time through, since we can't easily |
3302 | know this to be permanent. */ | |
3303 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
3304 | get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name); | |
3305 | flag_pic = 0; | |
82d6b402 | 3306 | |
fccf9848 JJ |
3307 | emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, |
3308 | get_pc_symbol)); | |
82d6b402 | 3309 | |
e0d80184 | 3310 | flag_pic = orig_flag_pic; |
82d6b402 | 3311 | |
e0d80184 DM |
3312 | /* Need to emit this whether or not we obey regdecls, |
3313 | since setjmp/longjmp can cause life info to screw up. | |
3314 | ??? In the case where we don't obey regdecls, this is not sufficient | |
3315 | since we may not fall out the bottom. */ | |
3316 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); | |
795068a4 | 3317 | } |
ab835497 | 3318 | \f |
e0d80184 | 3319 | /* Return 1 if RTX is a MEM which is known to be aligned to at |
7a31a340 | 3320 | least a DESIRED byte boundary. */ |
a3ee5899 | 3321 | |
e0d80184 DM |
3322 | int |
3323 | mem_min_alignment (mem, desired) | |
3324 | rtx mem; | |
3325 | int desired; | |
ab835497 | 3326 | { |
e0d80184 DM |
3327 | rtx addr, base, offset; |
3328 | ||
3329 | /* If it's not a MEM we can't accept it. */ | |
3330 | if (GET_CODE (mem) != MEM) | |
3331 | return 0; | |
3332 | ||
3333 | addr = XEXP (mem, 0); | |
3334 | base = offset = NULL_RTX; | |
3335 | if (GET_CODE (addr) == PLUS) | |
ab835497 | 3336 | { |
e0d80184 | 3337 | if (GET_CODE (XEXP (addr, 0)) == REG) |
61a55e8b | 3338 | { |
e0d80184 DM |
3339 | base = XEXP (addr, 0); |
3340 | ||
3341 | /* What we are saying here is that if the base | |
3342 | REG is aligned properly, the compiler will make | |
3343 | sure any REG based index upon it will be so | |
3344 | as well. */ | |
3345 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3346 | offset = XEXP (addr, 1); | |
61a55e8b | 3347 | else |
e0d80184 | 3348 | offset = const0_rtx; |
61a55e8b | 3349 | } |
ab835497 | 3350 | } |
e0d80184 | 3351 | else if (GET_CODE (addr) == REG) |
ab835497 | 3352 | { |
e0d80184 DM |
3353 | base = addr; |
3354 | offset = const0_rtx; | |
ab835497 | 3355 | } |
82d6b402 | 3356 | |
e0d80184 | 3357 | if (base != NULL_RTX) |
795068a4 | 3358 | { |
e0d80184 DM |
3359 | int regno = REGNO (base); |
3360 | ||
563c12b0 | 3361 | if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM) |
61a55e8b | 3362 | { |
e0d80184 DM |
3363 | /* Check if the compiler has recorded some information |
3364 | about the alignment of the base REG. If reload has | |
021e2ecc JJ |
3365 | completed, we already matched with proper alignments. |
3366 | If not running global_alloc, reload might give us | |
3367 | unaligned pointer to local stack though. */ | |
bdb429a5 RK |
3368 | if (((cfun != 0 |
3369 | && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT) | |
021e2ecc | 3370 | || (optimize && reload_completed)) |
bdb429a5 | 3371 | && (INTVAL (offset) & (desired - 1)) == 0) |
e0d80184 | 3372 | return 1; |
61a55e8b | 3373 | } |
795068a4 | 3374 | else |
e0d80184 DM |
3375 | { |
3376 | if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) | |
3377 | return 1; | |
3378 | } | |
795068a4 | 3379 | } |
e0d80184 DM |
3380 | else if (! TARGET_UNALIGNED_DOUBLES |
3381 | || CONSTANT_P (addr) | |
3382 | || GET_CODE (addr) == LO_SUM) | |
795068a4 | 3383 | { |
e0d80184 DM |
3384 | /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES |
3385 | is true, in which case we can only assume that an access is aligned if | |
3386 | it is to a constant address, or the address involves a LO_SUM. */ | |
3387 | return 1; | |
795068a4 | 3388 | } |
e0d80184 DM |
3389 | |
3390 | /* An obviously unaligned address. */ | |
3391 | return 0; | |
795068a4 | 3392 | } |
e0d80184 | 3393 | |
ab835497 | 3394 | \f |
61a55e8b DE |
3395 | /* Vectors to keep interesting information about registers where it can easily |
3396 | be got. We use to use the actual mode value as the bit number, but there | |
3397 | are more than 32 modes now. Instead we use two tables: one indexed by | |
3398 | hard register number, and one indexed by mode. */ | |
3399 | ||
3400 | /* The purpose of sparc_mode_class is to shrink the range of modes so that | |
3401 | they all fit (as bit numbers) in a 32 bit word (again). Each real mode is | |
3402 | mapped into one sparc_mode_class mode. */ | |
3403 | ||
3404 | enum sparc_mode_class { | |
61a55e8b | 3405 | S_MODE, D_MODE, T_MODE, O_MODE, |
c4ce6853 DE |
3406 | SF_MODE, DF_MODE, TF_MODE, OF_MODE, |
3407 | CC_MODE, CCFP_MODE | |
61a55e8b | 3408 | }; |
ab835497 | 3409 | |
61a55e8b DE |
3410 | /* Modes for single-word and smaller quantities. */ |
3411 | #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
3412 | ||
3413 | /* Modes for double-word and smaller quantities. */ | |
3414 | #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) | |
3415 | ||
3416 | /* Modes for quad-word and smaller quantities. */ | |
3417 | #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
ab835497 | 3418 | |
d0cee9ba JJ |
3419 | /* Modes for 8-word and smaller quantities. */ |
3420 | #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) | |
3421 | ||
1e4eb8d1 JW |
3422 | /* Modes for single-float quantities. We must allow any single word or |
3423 | smaller quantity. This is because the fix/float conversion instructions | |
3424 | take integer inputs/outputs from the float registers. */ | |
3425 | #define SF_MODES (S_MODES) | |
ab835497 | 3426 | |
61a55e8b DE |
3427 | /* Modes for double-float and smaller quantities. */ |
3428 | #define DF_MODES (S_MODES | D_MODES) | |
3429 | ||
61a55e8b | 3430 | /* Modes for double-float only quantities. */ |
38875aba | 3431 | #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) |
ab835497 | 3432 | |
61a55e8b DE |
3433 | /* Modes for quad-float only quantities. */ |
3434 | #define TF_ONLY_MODES (1 << (int) TF_MODE) | |
3435 | ||
3436 | /* Modes for quad-float and smaller quantities. */ | |
3437 | #define TF_MODES (DF_MODES | TF_ONLY_MODES) | |
3438 | ||
d0cee9ba JJ |
3439 | /* Modes for quad-float and double-float quantities. */ |
3440 | #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES) | |
3441 | ||
3442 | /* Modes for quad-float pair only quantities. */ | |
3443 | #define OF_ONLY_MODES (1 << (int) OF_MODE) | |
3444 | ||
3445 | /* Modes for quad-float pairs and smaller quantities. */ | |
3446 | #define OF_MODES (TF_MODES | OF_ONLY_MODES) | |
3447 | ||
3448 | #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES) | |
ab835497 | 3449 | |
c4ce6853 DE |
3450 | /* Modes for condition codes. */ |
3451 | #define CC_MODES (1 << (int) CC_MODE) | |
3452 | #define CCFP_MODES (1 << (int) CCFP_MODE) | |
3453 | ||
ab835497 RK |
3454 | /* Value is 1 if register/mode pair is acceptable on sparc. |
3455 | The funny mixture of D and T modes is because integer operations | |
3456 | do not specially operate on tetra quantities, so non-quad-aligned | |
3457 | registers can hold quadword quantities (except %o4 and %i4 because | |
c4ce6853 | 3458 | they cross fixed registers). */ |
ab835497 | 3459 | |
61a55e8b | 3460 | /* This points to either the 32 bit or the 64 bit version. */ |
0b5826ac | 3461 | const int *hard_regno_mode_classes; |
61a55e8b | 3462 | |
0b5826ac | 3463 | static const int hard_32bit_mode_classes[] = { |
c4ce6853 | 3464 | S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, |
ab835497 RK |
3465 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, |
3466 | T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
3467 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
3468 | ||
d0cee9ba JJ |
3469 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
3470 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3471 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3472 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
a9e27770 DE |
3473 | |
3474 | /* FP regs f32 to f63. Only the even numbered registers actually exist, | |
3475 | and none can hold SFmode/SImode values. */ | |
d0cee9ba JJ |
3476 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
3477 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3478 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3479 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
a9e27770 DE |
3480 | |
3481 | /* %fcc[0123] */ | |
c4ce6853 DE |
3482 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
3483 | ||
3484 | /* %icc */ | |
3485 | CC_MODES | |
61a55e8b DE |
3486 | }; |
3487 | ||
0b5826ac | 3488 | static const int hard_64bit_mode_classes[] = { |
c4ce6853 | 3489 | D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 3490 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 3491 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 3492 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 3493 | |
d0cee9ba JJ |
3494 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
3495 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3496 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3497 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
61a55e8b | 3498 | |
a9e27770 | 3499 | /* FP regs f32 to f63. Only the even numbered registers actually exist, |
61a55e8b | 3500 | and none can hold SFmode/SImode values. */ |
d0cee9ba JJ |
3501 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
3502 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3503 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3504 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
61a55e8b DE |
3505 | |
3506 | /* %fcc[0123] */ | |
c4ce6853 DE |
3507 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
3508 | ||
3509 | /* %icc */ | |
3510 | CC_MODES | |
61a55e8b DE |
3511 | }; |
3512 | ||
3513 | int sparc_mode_class [NUM_MACHINE_MODES]; | |
3514 | ||
c4ce6853 DE |
3515 | enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
3516 | ||
61a55e8b DE |
3517 | static void |
3518 | sparc_init_modes () | |
3519 | { | |
3520 | int i; | |
3521 | ||
61a55e8b DE |
3522 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
3523 | { | |
3524 | switch (GET_MODE_CLASS (i)) | |
3525 | { | |
3526 | case MODE_INT: | |
3527 | case MODE_PARTIAL_INT: | |
3528 | case MODE_COMPLEX_INT: | |
3529 | if (GET_MODE_SIZE (i) <= 4) | |
3530 | sparc_mode_class[i] = 1 << (int) S_MODE; | |
3531 | else if (GET_MODE_SIZE (i) == 8) | |
3532 | sparc_mode_class[i] = 1 << (int) D_MODE; | |
3533 | else if (GET_MODE_SIZE (i) == 16) | |
3534 | sparc_mode_class[i] = 1 << (int) T_MODE; | |
3535 | else if (GET_MODE_SIZE (i) == 32) | |
3536 | sparc_mode_class[i] = 1 << (int) O_MODE; | |
3537 | else | |
3538 | sparc_mode_class[i] = 0; | |
3539 | break; | |
3540 | case MODE_FLOAT: | |
3541 | case MODE_COMPLEX_FLOAT: | |
3542 | if (GET_MODE_SIZE (i) <= 4) | |
3543 | sparc_mode_class[i] = 1 << (int) SF_MODE; | |
3544 | else if (GET_MODE_SIZE (i) == 8) | |
3545 | sparc_mode_class[i] = 1 << (int) DF_MODE; | |
3546 | else if (GET_MODE_SIZE (i) == 16) | |
3547 | sparc_mode_class[i] = 1 << (int) TF_MODE; | |
3548 | else if (GET_MODE_SIZE (i) == 32) | |
3549 | sparc_mode_class[i] = 1 << (int) OF_MODE; | |
3550 | else | |
3551 | sparc_mode_class[i] = 0; | |
3552 | break; | |
3553 | case MODE_CC: | |
3554 | default: | |
3555 | /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so | |
3556 | we must explicitly check for them here. */ | |
3557 | if (i == (int) CCFPmode || i == (int) CCFPEmode) | |
3558 | sparc_mode_class[i] = 1 << (int) CCFP_MODE; | |
3559 | else if (i == (int) CCmode || i == (int) CC_NOOVmode | |
a9e27770 | 3560 | || i == (int) CCXmode || i == (int) CCX_NOOVmode) |
c4ce6853 | 3561 | sparc_mode_class[i] = 1 << (int) CC_MODE; |
61a55e8b DE |
3562 | else |
3563 | sparc_mode_class[i] = 0; | |
3564 | break; | |
3565 | } | |
3566 | } | |
3567 | ||
a9e27770 | 3568 | if (TARGET_ARCH64) |
61a55e8b DE |
3569 | hard_regno_mode_classes = hard_64bit_mode_classes; |
3570 | else | |
3571 | hard_regno_mode_classes = hard_32bit_mode_classes; | |
c4ce6853 DE |
3572 | |
3573 | /* Initialize the array used by REGNO_REG_CLASS. */ | |
3574 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3575 | { | |
284d86e9 JC |
3576 | if (i < 16 && TARGET_V8PLUS) |
3577 | sparc_regno_reg_class[i] = I64_REGS; | |
563c12b0 | 3578 | else if (i < 32 || i == FRAME_POINTER_REGNUM) |
c4ce6853 DE |
3579 | sparc_regno_reg_class[i] = GENERAL_REGS; |
3580 | else if (i < 64) | |
3581 | sparc_regno_reg_class[i] = FP_REGS; | |
3582 | else if (i < 96) | |
3583 | sparc_regno_reg_class[i] = EXTRA_FP_REGS; | |
3584 | else if (i < 100) | |
3585 | sparc_regno_reg_class[i] = FPCC_REGS; | |
3586 | else | |
3587 | sparc_regno_reg_class[i] = NO_REGS; | |
3588 | } | |
61a55e8b | 3589 | } |
ab835497 | 3590 | \f |
61a55e8b DE |
3591 | /* Save non call used registers from LOW to HIGH at BASE+OFFSET. |
3592 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
3593 | v9 int regs as it simplifies the code. */ | |
3594 | ||
ab835497 | 3595 | static int |
c53aa195 | 3596 | save_regs (file, low, high, base, offset, n_regs, real_offset) |
ab835497 RK |
3597 | FILE *file; |
3598 | int low, high; | |
3bb5de61 | 3599 | const char *base; |
ab835497 | 3600 | int offset; |
61a55e8b | 3601 | int n_regs; |
c53aa195 | 3602 | int real_offset; |
ab835497 RK |
3603 | { |
3604 | int i; | |
3605 | ||
a9e27770 | 3606 | if (TARGET_ARCH64 && high <= 32) |
ab835497 | 3607 | { |
61a55e8b DE |
3608 | for (i = low; i < high; i++) |
3609 | { | |
3610 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 3611 | { |
e0d80184 | 3612 | fprintf (file, "\tstx\t%s, [%s+%d]\n", |
c53aa195 | 3613 | reg_names[i], base, offset + 4 * n_regs); |
0021b564 | 3614 | if (dwarf2out_do_frame ()) |
c53aa195 | 3615 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); |
c53aa195 JM |
3616 | n_regs += 2; |
3617 | } | |
61a55e8b | 3618 | } |
ab835497 | 3619 | } |
61a55e8b DE |
3620 | else |
3621 | { | |
3622 | for (i = low; i < high; i += 2) | |
3623 | { | |
3624 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 3625 | { |
5e9defae KG |
3626 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) |
3627 | { | |
e0d80184 | 3628 | fprintf (file, "\tstd\t%s, [%s+%d]\n", |
5e9defae KG |
3629 | reg_names[i], base, offset + 4 * n_regs); |
3630 | if (dwarf2out_do_frame ()) | |
3631 | { | |
3632 | char *l = dwarf2out_cfi_label (); | |
3633 | dwarf2out_reg_save (l, i, real_offset + 4 * n_regs); | |
3634 | dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4); | |
3635 | } | |
3636 | n_regs += 2; | |
3637 | } | |
3638 | else | |
3639 | { | |
e0d80184 | 3640 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
3641 | reg_names[i], base, offset + 4 * n_regs); |
3642 | if (dwarf2out_do_frame ()) | |
3643 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); | |
3644 | n_regs += 2; | |
3645 | } | |
3646 | } | |
3647 | else | |
3648 | { | |
3649 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
3650 | { | |
e0d80184 | 3651 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
3652 | reg_names[i+1], base, offset + 4 * n_regs + 4); |
3653 | if (dwarf2out_do_frame ()) | |
3654 | dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4); | |
3655 | n_regs += 2; | |
3656 | } | |
c53aa195 | 3657 | } |
61a55e8b DE |
3658 | } |
3659 | } | |
3660 | return n_regs; | |
ab835497 RK |
3661 | } |
3662 | ||
61a55e8b DE |
3663 | /* Restore non call used registers from LOW to HIGH at BASE+OFFSET. |
3664 | ||
3665 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
3666 | v9 int regs as it simplifies the code. */ | |
3667 | ||
ab835497 | 3668 | static int |
61a55e8b | 3669 | restore_regs (file, low, high, base, offset, n_regs) |
ab835497 RK |
3670 | FILE *file; |
3671 | int low, high; | |
3bb5de61 | 3672 | const char *base; |
ab835497 | 3673 | int offset; |
61a55e8b | 3674 | int n_regs; |
ab835497 RK |
3675 | { |
3676 | int i; | |
3677 | ||
a9e27770 | 3678 | if (TARGET_ARCH64 && high <= 32) |
61a55e8b DE |
3679 | { |
3680 | for (i = low; i < high; i++) | |
3681 | { | |
3682 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
e0d80184 | 3683 | fprintf (file, "\tldx\t[%s+%d], %s\n", |
61a55e8b DE |
3684 | base, offset + 4 * n_regs, reg_names[i]), |
3685 | n_regs += 2; | |
3686 | } | |
3687 | } | |
3688 | else | |
ab835497 | 3689 | { |
61a55e8b DE |
3690 | for (i = low; i < high; i += 2) |
3691 | { | |
3692 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
3693 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
e0d80184 | 3694 | fprintf (file, "\tldd\t[%s+%d], %s\n", |
61a55e8b DE |
3695 | base, offset + 4 * n_regs, reg_names[i]), |
3696 | n_regs += 2; | |
3697 | else | |
4df1190a | 3698 | fprintf (file, "\tld\t[%s+%d], %s\n", |
61a55e8b DE |
3699 | base, offset + 4 * n_regs, reg_names[i]), |
3700 | n_regs += 2; | |
3701 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
4df1190a | 3702 | fprintf (file, "\tld\t[%s+%d], %s\n", |
61a55e8b DE |
3703 | base, offset + 4 * n_regs + 4, reg_names[i+1]), |
3704 | n_regs += 2; | |
3705 | } | |
ab835497 | 3706 | } |
61a55e8b | 3707 | return n_regs; |
ab835497 RK |
3708 | } |
3709 | ||
61a55e8b DE |
3710 | /* Compute the frame size required by the function. This function is called |
3711 | during the reload pass and also by output_function_prologue(). */ | |
ab835497 | 3712 | |
ab835497 RK |
3713 | int |
3714 | compute_frame_size (size, leaf_function) | |
3715 | int size; | |
3716 | int leaf_function; | |
3717 | { | |
61a55e8b | 3718 | int n_regs = 0, i; |
ab835497 | 3719 | int outgoing_args_size = (current_function_outgoing_args_size |
4fb4e4b8 | 3720 | + REG_PARM_STACK_SPACE (current_function_decl)); |
ab835497 | 3721 | |
33074e5f RH |
3722 | /* N_REGS is the number of 4-byte regs saved thus far. This applies |
3723 | even to v9 int regs to be consistent with save_regs/restore_regs. */ | |
61a55e8b | 3724 | |
33074e5f RH |
3725 | if (TARGET_ARCH64) |
3726 | { | |
3727 | for (i = 0; i < 8; i++) | |
3728 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
3729 | n_regs += 2; | |
3730 | } | |
3731 | else | |
3732 | { | |
3733 | for (i = 0; i < 8; i += 2) | |
ab835497 RK |
3734 | if ((regs_ever_live[i] && ! call_used_regs[i]) |
3735 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
61a55e8b | 3736 | n_regs += 2; |
ab835497 RK |
3737 | } |
3738 | ||
33074e5f RH |
3739 | for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) |
3740 | if ((regs_ever_live[i] && ! call_used_regs[i]) | |
3741 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
3742 | n_regs += 2; | |
3743 | ||
ab835497 | 3744 | /* Set up values for use in `function_epilogue'. */ |
61a55e8b | 3745 | num_gfregs = n_regs; |
ab835497 | 3746 | |
61a55e8b DE |
3747 | if (leaf_function && n_regs == 0 |
3748 | && size == 0 && current_function_outgoing_args_size == 0) | |
3749 | { | |
3750 | actual_fsize = apparent_fsize = 0; | |
3751 | } | |
3752 | else | |
3753 | { | |
225909c3 JS |
3754 | /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */ |
3755 | apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8; | |
61a55e8b DE |
3756 | apparent_fsize += n_regs * 4; |
3757 | actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); | |
3758 | } | |
ab835497 RK |
3759 | |
3760 | /* Make sure nothing can clobber our register windows. | |
3761 | If a SAVE must be done, or there is a stack-local variable, | |
61a55e8b | 3762 | the register window area must be allocated. |
4fb4e4b8 | 3763 | ??? For v8 we apparently need an additional 8 bytes of reserved space. */ |
ab835497 | 3764 | if (leaf_function == 0 || size > 0) |
4fb4e4b8 | 3765 | actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8); |
ab835497 | 3766 | |
61a55e8b DE |
3767 | return SPARC_STACK_ALIGN (actual_fsize); |
3768 | } | |
3769 | ||
3770 | /* Build a (32 bit) big number in a register. */ | |
86735b02 | 3771 | /* ??? We may be able to use the set macro here too. */ |
61a55e8b DE |
3772 | |
3773 | static void | |
3774 | build_big_number (file, num, reg) | |
3775 | FILE *file; | |
3776 | int num; | |
3bb5de61 | 3777 | const char *reg; |
61a55e8b | 3778 | { |
a9e27770 | 3779 | if (num >= 0 || ! TARGET_ARCH64) |
61a55e8b | 3780 | { |
e0d80184 | 3781 | fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg); |
61a55e8b | 3782 | if ((num & 0x3ff) != 0) |
e0d80184 | 3783 | fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg); |
61a55e8b | 3784 | } |
a9e27770 | 3785 | else /* num < 0 && TARGET_ARCH64 */ |
61a55e8b DE |
3786 | { |
3787 | /* Sethi does not sign extend, so we must use a little trickery | |
3788 | to use it for negative numbers. Invert the constant before | |
3789 | loading it in, then use xor immediate to invert the loaded bits | |
3790 | (along with the upper 32 bits) to the desired constant. This | |
3791 | works because the sethi and immediate fields overlap. */ | |
3792 | int asize = num; | |
3793 | int inv = ~asize; | |
3794 | int low = -0x400 + (asize & 0x3FF); | |
3795 | ||
e0d80184 | 3796 | fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n", |
61a55e8b DE |
3797 | inv, reg, reg, low, reg); |
3798 | } | |
ab835497 RK |
3799 | } |
3800 | ||
1cb36a98 RH |
3801 | /* Output any necessary .register pseudo-ops. */ |
3802 | void | |
3803 | sparc_output_scratch_registers (file) | |
fbd039b2 | 3804 | FILE *file ATTRIBUTE_UNUSED; |
1cb36a98 RH |
3805 | { |
3806 | #ifdef HAVE_AS_REGISTER_PSEUDO_OP | |
3807 | int i; | |
3808 | ||
3809 | if (TARGET_ARCH32) | |
3810 | return; | |
3811 | ||
3812 | /* Check if %g[2367] were used without | |
3813 | .register being printed for them already. */ | |
3814 | for (i = 2; i < 8; i++) | |
3815 | { | |
3816 | if (regs_ever_live [i] | |
3817 | && ! sparc_hard_reg_printed [i]) | |
3818 | { | |
3819 | sparc_hard_reg_printed [i] = 1; | |
3820 | fprintf (file, "\t.register\t%%g%d, #scratch\n", i); | |
3821 | } | |
3822 | if (i == 3) i = 5; | |
3823 | } | |
3824 | #endif | |
3825 | } | |
3826 | ||
08c148a8 NB |
3827 | /* This function generates the assembly code for function entry. |
3828 | FILE is a stdio stream to output the code to. | |
3829 | SIZE is an int: how many units of temporary storage to allocate. | |
3830 | Refer to the array `regs_ever_live' to determine which registers | |
3831 | to save; `regs_ever_live[I]' is nonzero if register number I | |
3832 | is ever used in the function. This macro is responsible for | |
3833 | knowing which registers should not be saved even if used. */ | |
3834 | ||
3835 | /* On SPARC, move-double insns between fpu and cpu need an 8-byte block | |
3836 | of memory. If any fpu reg is used in the function, we allocate | |
3837 | such a block here, at the bottom of the frame, just in case it's needed. | |
3838 | ||
3839 | If this function is a leaf procedure, then we may choose not | |
3840 | to do a "save" insn. The decision about whether or not | |
3841 | to do this is made in regclass.c. */ | |
3842 | ||
3843 | static void | |
3844 | sparc_output_function_prologue (file, size) | |
3845 | FILE *file; | |
3846 | HOST_WIDE_INT size; | |
3847 | { | |
3848 | if (TARGET_FLAT) | |
3849 | sparc_flat_function_prologue (file, size); | |
3850 | else | |
3851 | sparc_nonflat_function_prologue (file, size, | |
3852 | current_function_uses_only_leaf_regs); | |
3853 | } | |
3854 | ||
915f619f JW |
3855 | /* Output code for the function prologue. */ |
3856 | ||
08c148a8 NB |
3857 | static void |
3858 | sparc_nonflat_function_prologue (file, size, leaf_function) | |
ab835497 | 3859 | FILE *file; |
08c148a8 | 3860 | HOST_WIDE_INT size; |
915f619f | 3861 | int leaf_function; |
ab835497 | 3862 | { |
1cb36a98 RH |
3863 | sparc_output_scratch_registers (file); |
3864 | ||
915f619f JW |
3865 | /* Need to use actual_fsize, since we are also allocating |
3866 | space for our callee (and our own register save area). */ | |
ab835497 RK |
3867 | actual_fsize = compute_frame_size (size, leaf_function); |
3868 | ||
61a55e8b DE |
3869 | if (leaf_function) |
3870 | { | |
3871 | frame_base_name = "%sp"; | |
3872 | frame_base_offset = actual_fsize + SPARC_STACK_BIAS; | |
3873 | } | |
3874 | else | |
3875 | { | |
3876 | frame_base_name = "%fp"; | |
3877 | frame_base_offset = SPARC_STACK_BIAS; | |
3878 | } | |
3879 | ||
c6aa9ce1 | 3880 | /* This is only for the human reader. */ |
bf62bbf1 | 3881 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
c6aa9ce1 | 3882 | |
915f619f JW |
3883 | if (actual_fsize == 0) |
3884 | /* do nothing. */ ; | |
e6c1be7e | 3885 | else if (! leaf_function) |
ab835497 | 3886 | { |
3592ea0d | 3887 | if (actual_fsize <= 4096) |
e0d80184 | 3888 | fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize); |
3592ea0d | 3889 | else if (actual_fsize <= 8192) |
915f619f | 3890 | { |
e0d80184 DM |
3891 | fprintf (file, "\tsave\t%%sp, -4096, %%sp\n"); |
3892 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); | |
915f619f JW |
3893 | } |
3894 | else | |
3895 | { | |
3592ea0d | 3896 | build_big_number (file, -actual_fsize, "%g1"); |
e0d80184 | 3897 | fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); |
915f619f | 3898 | } |
ab835497 | 3899 | } |
5f4241d5 DE |
3900 | else /* leaf function */ |
3901 | { | |
3592ea0d | 3902 | if (actual_fsize <= 4096) |
e0d80184 | 3903 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize); |
3592ea0d DE |
3904 | else if (actual_fsize <= 8192) |
3905 | { | |
e0d80184 DM |
3906 | fprintf (file, "\tadd\t%%sp, -4096, %%sp\n"); |
3907 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); | |
3592ea0d | 3908 | } |
915f619f | 3909 | else |
3592ea0d DE |
3910 | { |
3911 | build_big_number (file, -actual_fsize, "%g1"); | |
e0d80184 | 3912 | fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n"); |
3592ea0d | 3913 | } |
ab835497 RK |
3914 | } |
3915 | ||
0021b564 | 3916 | if (dwarf2out_do_frame () && actual_fsize) |
c53aa195 | 3917 | { |
96987e96 | 3918 | char *label = dwarf2out_cfi_label (); |
c53aa195 JM |
3919 | |
3920 | /* The canonical frame address refers to the top of the frame. */ | |
3921 | dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM | |
563c12b0 | 3922 | : HARD_FRAME_POINTER_REGNUM), |
c53aa195 JM |
3923 | frame_base_offset); |
3924 | ||
3925 | if (! leaf_function) | |
3926 | { | |
3927 | /* Note the register window save. This tells the unwinder that | |
3928 | it needs to restore the window registers from the previous | |
3929 | frame's window save area at 0(cfa). */ | |
3930 | dwarf2out_window_save (label); | |
3931 | ||
3932 | /* The return address (-8) is now in %i7. */ | |
3933 | dwarf2out_return_reg (label, 31); | |
3934 | } | |
3935 | } | |
c53aa195 | 3936 | |
ab835497 RK |
3937 | /* If doing anything with PIC, do it now. */ |
3938 | if (! flag_pic) | |
bf62bbf1 | 3939 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
ab835497 | 3940 | |
61a55e8b DE |
3941 | /* Call saved registers are saved just above the outgoing argument area. */ |
3942 | if (num_gfregs) | |
ab835497 | 3943 | { |
c53aa195 | 3944 | int offset, real_offset, n_regs; |
3bb5de61 | 3945 | const char *base; |
ab835497 | 3946 | |
84e884e9 JM |
3947 | real_offset = -apparent_fsize; |
3948 | offset = -apparent_fsize + frame_base_offset; | |
61a55e8b DE |
3949 | if (offset < -4096 || offset + num_gfregs * 4 > 4096) |
3950 | { | |
3951 | /* ??? This might be optimized a little as %g1 might already have a | |
3952 | value close enough that a single add insn will do. */ | |
3953 | /* ??? Although, all of this is probably only a temporary fix | |
3954 | because if %g1 can hold a function result, then | |
3955 | output_function_epilogue will lose (the result will get | |
3956 | clobbered). */ | |
3957 | build_big_number (file, offset, "%g1"); | |
e0d80184 | 3958 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); |
61a55e8b DE |
3959 | base = "%g1"; |
3960 | offset = 0; | |
3961 | } | |
ab835497 | 3962 | else |
61a55e8b DE |
3963 | { |
3964 | base = frame_base_name; | |
3965 | } | |
ab835497 | 3966 | |
33074e5f RH |
3967 | n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); |
3968 | save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs, | |
3969 | real_offset); | |
ab835497 RK |
3970 | } |
3971 | } | |
3972 | ||
7d167afd JJ |
3973 | /* Output code to restore any call saved registers. */ |
3974 | ||
3975 | static void | |
3976 | output_restore_regs (file, leaf_function) | |
3977 | FILE *file; | |
f451b552 | 3978 | int leaf_function ATTRIBUTE_UNUSED; |
7d167afd JJ |
3979 | { |
3980 | int offset, n_regs; | |
3981 | const char *base; | |
3982 | ||
3983 | offset = -apparent_fsize + frame_base_offset; | |
3984 | if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) | |
3985 | { | |
3986 | build_big_number (file, offset, "%g1"); | |
3987 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); | |
3988 | base = "%g1"; | |
3989 | offset = 0; | |
3990 | } | |
3991 | else | |
3992 | { | |
3993 | base = frame_base_name; | |
3994 | } | |
3995 | ||
33074e5f RH |
3996 | n_regs = restore_regs (file, 0, 8, base, offset, 0); |
3997 | restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); | |
7d167afd JJ |
3998 | } |
3999 | ||
08c148a8 NB |
4000 | /* This function generates the assembly code for function exit, |
4001 | on machines that need it. | |
4002 | ||
4003 | The function epilogue should not depend on the current stack pointer! | |
4004 | It should use the frame pointer only. This is mandatory because | |
4005 | of alloca; we also take advantage of it to omit stack adjustments | |
4006 | before returning. */ | |
4007 | ||
4008 | static void | |
4009 | sparc_output_function_epilogue (file, size) | |
4010 | FILE *file; | |
4011 | HOST_WIDE_INT size; | |
4012 | { | |
4013 | if (TARGET_FLAT) | |
4014 | sparc_flat_function_epilogue (file, size); | |
4015 | else | |
4016 | sparc_nonflat_function_epilogue (file, size, | |
4017 | current_function_uses_only_leaf_regs); | |
4018 | } | |
4019 | ||
915f619f JW |
4020 | /* Output code for the function epilogue. */ |
4021 | ||
08c148a8 NB |
4022 | static void |
4023 | sparc_nonflat_function_epilogue (file, size, leaf_function) | |
ab835497 | 4024 | FILE *file; |
08c148a8 | 4025 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
ef8200df | 4026 | int leaf_function; |
ab835497 | 4027 | { |
3bb5de61 | 4028 | const char *ret; |
ab835497 | 4029 | |
8456b95a | 4030 | if (current_function_epilogue_delay_list == 0) |
e48addee | 4031 | { |
e0d80184 | 4032 | /* If code does not drop into the epilogue, we need |
7a31a340 DM |
4033 | do nothing except output pending case vectors. |
4034 | ||
4035 | We have to still output a dummy nop for the sake of | |
4036 | sane backtraces. Otherwise, if the last two instructions | |
4037 | of a function were call foo; dslot; this can make the return | |
4038 | PC of foo (ie. address of call instruction plus 8) point to | |
4039 | the first instruction in the next function. */ | |
4040 | rtx insn; | |
4041 | ||
4042 | fputs("\tnop\n", file); | |
4043 | ||
4044 | insn = get_last_insn (); | |
4045 | if (GET_CODE (insn) == NOTE) | |
4046 | insn = prev_nonnote_insn (insn); | |
4047 | if (insn && GET_CODE (insn) == BARRIER) | |
4048 | goto output_vectors; | |
bfd6bc60 JC |
4049 | } |
4050 | ||
61a55e8b | 4051 | if (num_gfregs) |
7d167afd | 4052 | output_restore_regs (file, leaf_function); |
ab835497 RK |
4053 | |
4054 | /* Work out how to skip the caller's unimp instruction if required. */ | |
4055 | if (leaf_function) | |
e0d80184 | 4056 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl"); |
ab835497 | 4057 | else |
e0d80184 | 4058 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret"); |
ab835497 | 4059 | |
33074e5f | 4060 | if (! leaf_function) |
ab835497 | 4061 | { |
33074e5f RH |
4062 | if (current_function_calls_eh_return) |
4063 | { | |
4064 | if (current_function_epilogue_delay_list) | |
4065 | abort (); | |
4066 | if (SKIP_CALLERS_UNIMP_P) | |
4067 | abort (); | |
ab835497 | 4068 | |
33074e5f RH |
4069 | fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file); |
4070 | } | |
4071 | /* If we wound up with things in our delay slot, flush them here. */ | |
4072 | else if (current_function_epilogue_delay_list) | |
ef8200df | 4073 | { |
33074e5f | 4074 | rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0)); |
1150a841 | 4075 | |
33074e5f RH |
4076 | if (TARGET_V9 && ! epilogue_renumber (&delay, 1)) |
4077 | { | |
4078 | epilogue_renumber (&delay, 0); | |
4079 | fputs (SKIP_CALLERS_UNIMP_P | |
4080 | ? "\treturn\t%i7+12\n" | |
4081 | : "\treturn\t%i7+8\n", file); | |
4082 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
4083 | file, 1, 0, 0); | |
1150a841 | 4084 | } |
33074e5f | 4085 | else |
ab835497 | 4086 | { |
33074e5f | 4087 | rtx insn, src; |
e48addee | 4088 | |
33074e5f RH |
4089 | if (GET_CODE (delay) != SET) |
4090 | abort(); | |
e48addee | 4091 | |
33074e5f RH |
4092 | src = SET_SRC (delay); |
4093 | if (GET_CODE (src) == ASHIFT) | |
4094 | { | |
4095 | if (XEXP (src, 1) != const1_rtx) | |
e48addee | 4096 | abort(); |
33074e5f RH |
4097 | SET_SRC (delay) |
4098 | = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0), | |
4099 | XEXP (src, 0)); | |
4100 | } | |
e48addee | 4101 | |
33074e5f RH |
4102 | insn = gen_rtx_PARALLEL (VOIDmode, |
4103 | gen_rtvec (2, delay, | |
4104 | gen_rtx_RETURN (VOIDmode))); | |
4105 | insn = emit_jump_insn (insn); | |
e48addee | 4106 | |
33074e5f RH |
4107 | sparc_emitting_epilogue = true; |
4108 | final_scan_insn (insn, file, 1, 0, 1); | |
4109 | sparc_emitting_epilogue = false; | |
ab835497 | 4110 | } |
ef8200df | 4111 | } |
33074e5f RH |
4112 | else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P) |
4113 | fputs ("\treturn\t%i7+8\n\tnop\n", file); | |
4114 | else | |
4115 | fprintf (file, "\t%s\n\trestore\n", ret); | |
4116 | } | |
4117 | /* All of the following cases are for leaf functions. */ | |
4118 | else if (current_function_calls_eh_return) | |
4119 | abort (); | |
4120 | else if (current_function_epilogue_delay_list) | |
4121 | { | |
4122 | /* eligible_for_epilogue_delay_slot ensures that if this is a | |
4123 | leaf function, then we will only have insn in the delay slot | |
4124 | if the frame size is zero, thus no adjust for the stack is | |
4125 | needed here. */ | |
4126 | if (actual_fsize != 0) | |
1150a841 | 4127 | abort (); |
33074e5f RH |
4128 | fprintf (file, "\t%s\n", ret); |
4129 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
4130 | file, 1, 0, 1); | |
ab835497 | 4131 | } |
33074e5f RH |
4132 | /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to |
4133 | avoid generating confusing assembly language output. */ | |
4134 | else if (actual_fsize == 0) | |
4135 | fprintf (file, "\t%s\n\tnop\n", ret); | |
4136 | else if (actual_fsize <= 4096) | |
4137 | fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize); | |
4138 | else if (actual_fsize <= 8192) | |
4139 | fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n", | |
4140 | ret, actual_fsize - 4096); | |
4141 | else if ((actual_fsize & 0x3ff) == 0) | |
4142 | fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", | |
4143 | actual_fsize, ret); | |
4144 | else | |
4145 | fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", | |
4146 | actual_fsize, actual_fsize, ret); | |
e0d80184 DM |
4147 | |
4148 | output_vectors: | |
4149 | sparc_output_deferred_case_vectors (); | |
ab835497 | 4150 | } |
7d167afd JJ |
4151 | |
4152 | /* Output a sibling call. */ | |
4153 | ||
4154 | const char * | |
4155 | output_sibcall (insn, call_operand) | |
4156 | rtx insn, call_operand; | |
4157 | { | |
4158 | int leaf_regs = current_function_uses_only_leaf_regs; | |
4159 | rtx operands[3]; | |
4160 | int delay_slot = dbr_sequence_length () > 0; | |
4161 | ||
4162 | if (num_gfregs) | |
4163 | { | |
4164 | /* Call to restore global regs might clobber | |
4165 | the delay slot. Instead of checking for this | |
4166 | output the delay slot now. */ | |
4167 | if (delay_slot) | |
4168 | { | |
4169 | rtx delay = NEXT_INSN (insn); | |
4170 | ||
4171 | if (! delay) | |
4172 | abort (); | |
4173 | ||
4174 | final_scan_insn (delay, asm_out_file, 1, 0, 1); | |
4175 | PATTERN (delay) = gen_blockage (); | |
4176 | INSN_CODE (delay) = -1; | |
4177 | delay_slot = 0; | |
4178 | } | |
4179 | output_restore_regs (asm_out_file, leaf_regs); | |
4180 | } | |
4181 | ||
4182 | operands[0] = call_operand; | |
4183 | ||
4184 | if (leaf_regs) | |
4185 | { | |
e95b1e6a JJ |
4186 | #ifdef HAVE_AS_RELAX_OPTION |
4187 | /* If as and ld are relaxing tail call insns into branch always, | |
4188 | use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can | |
4189 | be optimized. With sethi/jmpl as nor ld has no easy way how to | |
4190 | find out if somebody does not branch between the sethi and jmpl. */ | |
4191 | int spare_slot = 0; | |
4192 | #else | |
2be5e524 | 4193 | int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic); |
e95b1e6a | 4194 | #endif |
7d167afd JJ |
4195 | int size = 0; |
4196 | ||
4197 | if ((actual_fsize || ! spare_slot) && delay_slot) | |
4198 | { | |
4199 | rtx delay = NEXT_INSN (insn); | |
4200 | ||
4201 | if (! delay) | |
4202 | abort (); | |
4203 | ||
4204 | final_scan_insn (delay, asm_out_file, 1, 0, 1); | |
4205 | PATTERN (delay) = gen_blockage (); | |
4206 | INSN_CODE (delay) = -1; | |
4207 | delay_slot = 0; | |
4208 | } | |
4209 | if (actual_fsize) | |
4210 | { | |
4211 | if (actual_fsize <= 4096) | |
4212 | size = actual_fsize; | |
4213 | else if (actual_fsize <= 8192) | |
4214 | { | |
4215 | fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file); | |
4216 | size = actual_fsize - 4096; | |
4217 | } | |
4218 | else if ((actual_fsize & 0x3ff) == 0) | |
4219 | fprintf (asm_out_file, | |
4220 | "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n", | |
4221 | actual_fsize); | |
4222 | else | |
4223 | { | |
4224 | fprintf (asm_out_file, | |
4225 | "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n", | |
4226 | actual_fsize, actual_fsize); | |
4227 | fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file); | |
4228 | } | |
4229 | } | |
4230 | if (spare_slot) | |
4231 | { | |
4232 | output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands); | |
4233 | output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands); | |
4234 | if (size) | |
4235 | fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size); | |
4236 | else if (! delay_slot) | |
4237 | fputs ("\t nop\n", asm_out_file); | |
4238 | } | |
4239 | else | |
4240 | { | |
4241 | if (size) | |
4242 | fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size); | |
e95b1e6a JJ |
4243 | /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize |
4244 | it into branch if possible. */ | |
4245 | output_asm_insn ("or\t%%o7, %%g0, %%g1", operands); | |
7d167afd | 4246 | output_asm_insn ("call\t%a0, 0", operands); |
e95b1e6a | 4247 | output_asm_insn (" or\t%%g1, %%g0, %%o7", operands); |
7d167afd JJ |
4248 | } |
4249 | return ""; | |
4250 | } | |
4251 | ||
4252 | output_asm_insn ("call\t%a0, 0", operands); | |
4253 | if (delay_slot) | |
4254 | { | |
4255 | rtx delay = NEXT_INSN (insn), pat; | |
4256 | ||
4257 | if (! delay) | |
4258 | abort (); | |
4259 | ||
4260 | pat = PATTERN (delay); | |
4261 | if (GET_CODE (pat) != SET) | |
4262 | abort (); | |
4263 | ||
4264 | operands[0] = SET_DEST (pat); | |
4265 | pat = SET_SRC (pat); | |
4266 | switch (GET_CODE (pat)) | |
4267 | { | |
4268 | case PLUS: | |
4269 | operands[1] = XEXP (pat, 0); | |
4270 | operands[2] = XEXP (pat, 1); | |
4271 | output_asm_insn (" restore %r1, %2, %Y0", operands); | |
4272 | break; | |
4273 | case LO_SUM: | |
4274 | operands[1] = XEXP (pat, 0); | |
4275 | operands[2] = XEXP (pat, 1); | |
4276 | output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); | |
4277 | break; | |
4278 | case ASHIFT: | |
4279 | operands[1] = XEXP (pat, 0); | |
4280 | output_asm_insn (" restore %r1, %r1, %Y0", operands); | |
4281 | break; | |
4282 | default: | |
4283 | operands[1] = pat; | |
4284 | output_asm_insn (" restore %%g0, %1, %Y0", operands); | |
4285 | break; | |
4286 | } | |
4287 | PATTERN (delay) = gen_blockage (); | |
4288 | INSN_CODE (delay) = -1; | |
4289 | } | |
4290 | else | |
4291 | fputs ("\t restore\n", asm_out_file); | |
4292 | return ""; | |
4293 | } | |
4fb4e4b8 DE |
4294 | \f |
4295 | /* Functions for handling argument passing. | |
4296 | ||
4297 | For v8 the first six args are normally in registers and the rest are | |
4298 | pushed. Any arg that starts within the first 6 words is at least | |
4299 | partially passed in a register unless its data type forbids. | |
4300 | ||
4301 | For v9, the argument registers are laid out as an array of 16 elements | |
4302 | and arguments are added sequentially. The first 6 int args and up to the | |
4303 | first 16 fp args (depending on size) are passed in regs. | |
4304 | ||
4305 | Slot Stack Integral Float Float in structure Double Long Double | |
4306 | ---- ----- -------- ----- ------------------ ------ ----------- | |
4307 | 15 [SP+248] %f31 %f30,%f31 %d30 | |
4308 | 14 [SP+240] %f29 %f28,%f29 %d28 %q28 | |
4309 | 13 [SP+232] %f27 %f26,%f27 %d26 | |
4310 | 12 [SP+224] %f25 %f24,%f25 %d24 %q24 | |
4311 | 11 [SP+216] %f23 %f22,%f23 %d22 | |
4312 | 10 [SP+208] %f21 %f20,%f21 %d20 %q20 | |
4313 | 9 [SP+200] %f19 %f18,%f19 %d18 | |
4314 | 8 [SP+192] %f17 %f16,%f17 %d16 %q16 | |
4315 | 7 [SP+184] %f15 %f14,%f15 %d14 | |
4316 | 6 [SP+176] %f13 %f12,%f13 %d12 %q12 | |
4317 | 5 [SP+168] %o5 %f11 %f10,%f11 %d10 | |
4318 | 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 | |
4319 | 3 [SP+152] %o3 %f7 %f6,%f7 %d6 | |
4320 | 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 | |
4321 | 1 [SP+136] %o1 %f3 %f2,%f3 %d2 | |
4322 | 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 | |
4323 | ||
4324 | Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. | |
4325 | ||
4326 | Integral arguments are always passed as 64 bit quantities appropriately | |
4327 | extended. | |
4328 | ||
4329 | Passing of floating point values is handled as follows. | |
4330 | If a prototype is in scope: | |
4331 | If the value is in a named argument (i.e. not a stdarg function or a | |
4332 | value not part of the `...') then the value is passed in the appropriate | |
4333 | fp reg. | |
4334 | If the value is part of the `...' and is passed in one of the first 6 | |
4335 | slots then the value is passed in the appropriate int reg. | |
4336 | If the value is part of the `...' and is not passed in one of the first 6 | |
4337 | slots then the value is passed in memory. | |
4338 | If a prototype is not in scope: | |
4339 | If the value is one of the first 6 arguments the value is passed in the | |
4340 | appropriate integer reg and the appropriate fp reg. | |
4341 | If the value is not one of the first 6 arguments the value is passed in | |
4342 | the appropriate fp reg and in memory. | |
4343 | */ | |
4344 | ||
4345 | /* Maximum number of int regs for args. */ | |
4346 | #define SPARC_INT_ARG_MAX 6 | |
4347 | /* Maximum number of fp regs for args. */ | |
4348 | #define SPARC_FP_ARG_MAX 16 | |
4349 | ||
4350 | #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
4351 | ||
4352 | /* Handle the INIT_CUMULATIVE_ARGS macro. | |
4353 | Initialize a variable CUM of type CUMULATIVE_ARGS | |
4354 | for a call to a function whose data type is FNTYPE. | |
4355 | For a library call, FNTYPE is 0. */ | |
3ea1fdd3 | 4356 | |
4fb4e4b8 DE |
4357 | void |
4358 | init_cumulative_args (cum, fntype, libname, indirect) | |
4359 | CUMULATIVE_ARGS *cum; | |
db3d4438 | 4360 | tree fntype; |
88430453 | 4361 | rtx libname ATTRIBUTE_UNUSED; |
db3d4438 | 4362 | int indirect ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
4363 | { |
4364 | cum->words = 0; | |
4365 | cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); | |
4366 | cum->libcall_p = fntype == 0; | |
4367 | } | |
61a55e8b | 4368 | |
4fb4e4b8 DE |
4369 | /* Compute the slot number to pass an argument in. |
4370 | Returns the slot number or -1 if passing on the stack. | |
4371 | ||
4372 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4373 | the preceding args and about the function being called. | |
4374 | MODE is the argument's machine mode. | |
4375 | TYPE is the data type of the argument (as a tree). | |
4376 | This is null for libcalls where that information may | |
4377 | not be available. | |
4378 | NAMED is nonzero if this argument is a named parameter | |
4379 | (otherwise it is an extra parameter matching an ellipsis). | |
4380 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. | |
4381 | *PREGNO records the register number to use if scalar type. | |
4382 | *PPADDING records the amount of padding needed in words. */ | |
4383 | ||
4384 | static int | |
4385 | function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding) | |
4386 | const CUMULATIVE_ARGS *cum; | |
4387 | enum machine_mode mode; | |
4388 | tree type; | |
4389 | int named; | |
4390 | int incoming_p; | |
4391 | int *pregno; | |
4392 | int *ppadding; | |
4393 | { | |
4394 | int regbase = (incoming_p | |
4395 | ? SPARC_INCOMING_INT_ARG_FIRST | |
4396 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
4397 | int slotno = cum->words; | |
4398 | int regno; | |
4399 | ||
4400 | *ppadding = 0; | |
4401 | ||
4402 | if (type != 0 && TREE_ADDRESSABLE (type)) | |
4403 | return -1; | |
4404 | if (TARGET_ARCH32 | |
4405 | && type != 0 && mode == BLKmode | |
4406 | && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) | |
4407 | return -1; | |
4408 | ||
4409 | switch (mode) | |
4410 | { | |
4411 | case VOIDmode : | |
4412 | /* MODE is VOIDmode when generating the actual call. | |
4413 | See emit_call_1. */ | |
4414 | return -1; | |
4415 | ||
4416 | case QImode : case CQImode : | |
4417 | case HImode : case CHImode : | |
4418 | case SImode : case CSImode : | |
4419 | case DImode : case CDImode : | |
380f6ad3 | 4420 | case TImode : case CTImode : |
4fb4e4b8 DE |
4421 | if (slotno >= SPARC_INT_ARG_MAX) |
4422 | return -1; | |
4423 | regno = regbase + slotno; | |
4424 | break; | |
4425 | ||
4426 | case SFmode : case SCmode : | |
4427 | case DFmode : case DCmode : | |
4428 | case TFmode : case TCmode : | |
4429 | if (TARGET_ARCH32) | |
4430 | { | |
4431 | if (slotno >= SPARC_INT_ARG_MAX) | |
4432 | return -1; | |
4433 | regno = regbase + slotno; | |
4434 | } | |
4435 | else | |
4436 | { | |
4437 | if ((mode == TFmode || mode == TCmode) | |
4438 | && (slotno & 1) != 0) | |
4439 | slotno++, *ppadding = 1; | |
4440 | if (TARGET_FPU && named) | |
4441 | { | |
4442 | if (slotno >= SPARC_FP_ARG_MAX) | |
82d6b402 | 4443 | return -1; |
4fb4e4b8 DE |
4444 | regno = SPARC_FP_ARG_FIRST + slotno * 2; |
4445 | if (mode == SFmode) | |
4446 | regno++; | |
4447 | } | |
4448 | else | |
4449 | { | |
4450 | if (slotno >= SPARC_INT_ARG_MAX) | |
4451 | return -1; | |
4452 | regno = regbase + slotno; | |
4453 | } | |
4454 | } | |
4455 | break; | |
4456 | ||
4457 | case BLKmode : | |
4458 | /* For sparc64, objects requiring 16 byte alignment get it. */ | |
4459 | if (TARGET_ARCH64) | |
4460 | { | |
4461 | if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0) | |
4462 | slotno++, *ppadding = 1; | |
4463 | } | |
4464 | ||
4465 | if (TARGET_ARCH32 | |
5e9defae | 4466 | || (type && TREE_CODE (type) == UNION_TYPE)) |
4fb4e4b8 DE |
4467 | { |
4468 | if (slotno >= SPARC_INT_ARG_MAX) | |
4469 | return -1; | |
4470 | regno = regbase + slotno; | |
4471 | } | |
4472 | else | |
4473 | { | |
4474 | tree field; | |
4475 | int intregs_p = 0, fpregs_p = 0; | |
4476 | /* The ABI obviously doesn't specify how packed | |
4477 | structures are passed. These are defined to be passed | |
4478 | in int regs if possible, otherwise memory. */ | |
4479 | int packed_p = 0; | |
4480 | ||
4481 | /* First see what kinds of registers we need. */ | |
4482 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4483 | { | |
4484 | if (TREE_CODE (field) == FIELD_DECL) | |
4485 | { | |
4486 | if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
4487 | && TARGET_FPU) | |
4488 | fpregs_p = 1; | |
4489 | else | |
4490 | intregs_p = 1; | |
4491 | if (DECL_PACKED (field)) | |
4492 | packed_p = 1; | |
4493 | } | |
4494 | } | |
4495 | if (packed_p || !named) | |
4496 | fpregs_p = 0, intregs_p = 1; | |
4497 | ||
4498 | /* If all arg slots are filled, then must pass on stack. */ | |
4499 | if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) | |
4500 | return -1; | |
4501 | /* If there are only int args and all int arg slots are filled, | |
4502 | then must pass on stack. */ | |
4503 | if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) | |
4504 | return -1; | |
4505 | /* Note that even if all int arg slots are filled, fp members may | |
4506 | still be passed in regs if such regs are available. | |
4507 | *PREGNO isn't set because there may be more than one, it's up | |
4508 | to the caller to compute them. */ | |
4509 | return slotno; | |
4510 | } | |
4511 | break; | |
4512 | ||
4513 | default : | |
4514 | abort (); | |
4515 | } | |
4516 | ||
4517 | *pregno = regno; | |
4518 | return slotno; | |
4519 | } | |
4520 | ||
82d6b402 RH |
4521 | /* Handle recursive register counting for structure field layout. */ |
4522 | ||
4523 | struct function_arg_record_value_parms | |
4524 | { | |
4525 | rtx ret; | |
4526 | int slotno, named, regbase; | |
75131237 RK |
4527 | unsigned int nregs; |
4528 | int intoffset; | |
82d6b402 RH |
4529 | }; |
4530 | ||
2a01c939 | 4531 | static void function_arg_record_value_3 |
75131237 | 4532 | PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *)); |
2a01c939 | 4533 | static void function_arg_record_value_2 |
75131237 RK |
4534 | PARAMS ((tree, HOST_WIDE_INT, |
4535 | struct function_arg_record_value_parms *)); | |
b1474bb7 | 4536 | static void function_arg_record_value_1 |
75131237 RK |
4537 | PARAMS ((tree, HOST_WIDE_INT, |
4538 | struct function_arg_record_value_parms *)); | |
2a01c939 | 4539 | static rtx function_arg_record_value |
f6da8bc3 | 4540 | PARAMS ((tree, enum machine_mode, int, int, int)); |
2a01c939 | 4541 | |
0020b823 RH |
4542 | /* A subroutine of function_arg_record_value. Traverse the structure |
4543 | recusively and determine how many registers will be required. */ | |
4544 | ||
82d6b402 RH |
4545 | static void |
4546 | function_arg_record_value_1 (type, startbitpos, parms) | |
4547 | tree type; | |
75131237 | 4548 | HOST_WIDE_INT startbitpos; |
82d6b402 RH |
4549 | struct function_arg_record_value_parms *parms; |
4550 | { | |
4551 | tree field; | |
4552 | ||
4553 | /* The ABI obviously doesn't specify how packed structures are | |
4554 | passed. These are defined to be passed in int regs if possible, | |
4555 | otherwise memory. */ | |
4556 | int packed_p = 0; | |
4557 | ||
4558 | /* We need to compute how many registers are needed so we can | |
4559 | allocate the PARALLEL but before we can do that we need to know | |
4560 | whether there are any packed fields. If there are, int regs are | |
4561 | used regardless of whether there are fp values present. */ | |
4562 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4563 | { | |
4564 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
4565 | { | |
4566 | packed_p = 1; | |
4567 | break; | |
4568 | } | |
4569 | } | |
4570 | ||
4571 | /* Compute how many registers we need. */ | |
4572 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4573 | { | |
4574 | if (TREE_CODE (field) == FIELD_DECL) | |
4575 | { | |
75131237 RK |
4576 | HOST_WIDE_INT bitpos = startbitpos; |
4577 | ||
4578 | if (DECL_SIZE (field) != 0 | |
4579 | && host_integerp (bit_position (field), 1)) | |
4580 | bitpos += int_bit_position (field); | |
4581 | ||
82d6b402 RH |
4582 | /* ??? FIXME: else assume zero offset. */ |
4583 | ||
4584 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
75131237 | 4585 | function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms); |
105b2084 JJ |
4586 | else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE |
4587 | || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE | |
4588 | && (TREE_CODE (TREE_TYPE (TREE_TYPE (field))) | |
4589 | == REAL_TYPE))) | |
82d6b402 RH |
4590 | && TARGET_FPU |
4591 | && ! packed_p | |
4592 | && parms->named) | |
4593 | { | |
4594 | if (parms->intoffset != -1) | |
4595 | { | |
4596 | int intslots, this_slotno; | |
4597 | ||
4598 | intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1) | |
4599 | / BITS_PER_WORD; | |
4600 | this_slotno = parms->slotno + parms->intoffset | |
4601 | / BITS_PER_WORD; | |
4602 | ||
4603 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
4604 | intslots = MAX (intslots, 0); | |
4605 | parms->nregs += intslots; | |
4606 | parms->intoffset = -1; | |
4607 | } | |
4608 | ||
4609 | /* There's no need to check this_slotno < SPARC_FP_ARG MAX. | |
4610 | If it wasn't true we wouldn't be here. */ | |
4611 | parms->nregs += 1; | |
105b2084 JJ |
4612 | if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) |
4613 | parms->nregs += 1; | |
82d6b402 RH |
4614 | } |
4615 | else | |
4616 | { | |
4617 | if (parms->intoffset == -1) | |
4618 | parms->intoffset = bitpos; | |
4619 | } | |
4620 | } | |
4621 | } | |
4622 | } | |
4623 | ||
0020b823 RH |
4624 | /* A subroutine of function_arg_record_value. Assign the bits of the |
4625 | structure between parms->intoffset and bitpos to integer registers. */ | |
82d6b402 RH |
4626 | |
4627 | static void | |
4628 | function_arg_record_value_3 (bitpos, parms) | |
75131237 | 4629 | HOST_WIDE_INT bitpos; |
82d6b402 RH |
4630 | struct function_arg_record_value_parms *parms; |
4631 | { | |
4632 | enum machine_mode mode; | |
75131237 | 4633 | unsigned int regno; |
0020b823 | 4634 | unsigned int startbit, endbit; |
75131237 | 4635 | int this_slotno, intslots, intoffset; |
82d6b402 RH |
4636 | rtx reg; |
4637 | ||
4638 | if (parms->intoffset == -1) | |
4639 | return; | |
75131237 | 4640 | |
82d6b402 RH |
4641 | intoffset = parms->intoffset; |
4642 | parms->intoffset = -1; | |
4643 | ||
0020b823 RH |
4644 | startbit = intoffset & -BITS_PER_WORD; |
4645 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4646 | intslots = (endbit - startbit) / BITS_PER_WORD; | |
82d6b402 RH |
4647 | this_slotno = parms->slotno + intoffset / BITS_PER_WORD; |
4648 | ||
4649 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
4650 | if (intslots <= 0) | |
4651 | return; | |
4652 | ||
4653 | /* If this is the trailing part of a word, only load that much into | |
4654 | the register. Otherwise load the whole register. Note that in | |
4655 | the latter case we may pick up unwanted bits. It's not a problem | |
4656 | at the moment but may wish to revisit. */ | |
4657 | ||
4658 | if (intoffset % BITS_PER_WORD != 0) | |
75131237 RK |
4659 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, |
4660 | MODE_INT, 0); | |
82d6b402 RH |
4661 | else |
4662 | mode = word_mode; | |
4663 | ||
4664 | intoffset /= BITS_PER_UNIT; | |
4665 | do | |
4666 | { | |
4667 | regno = parms->regbase + this_slotno; | |
254110c2 | 4668 | reg = gen_rtx_REG (mode, regno); |
82d6b402 | 4669 | XVECEXP (parms->ret, 0, parms->nregs) |
254110c2 | 4670 | = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); |
82d6b402 RH |
4671 | |
4672 | this_slotno += 1; | |
4673 | intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; | |
4674 | parms->nregs += 1; | |
4675 | intslots -= 1; | |
4676 | } | |
4677 | while (intslots > 0); | |
4678 | } | |
4679 | ||
0020b823 RH |
4680 | /* A subroutine of function_arg_record_value. Traverse the structure |
4681 | recursively and assign bits to floating point registers. Track which | |
4682 | bits in between need integer registers; invoke function_arg_record_value_3 | |
4683 | to make that happen. */ | |
4684 | ||
82d6b402 RH |
4685 | static void |
4686 | function_arg_record_value_2 (type, startbitpos, parms) | |
4687 | tree type; | |
75131237 | 4688 | HOST_WIDE_INT startbitpos; |
82d6b402 RH |
4689 | struct function_arg_record_value_parms *parms; |
4690 | { | |
4691 | tree field; | |
4692 | int packed_p = 0; | |
4693 | ||
4694 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4695 | { | |
4696 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
4697 | { | |
4698 | packed_p = 1; | |
4699 | break; | |
4700 | } | |
4701 | } | |
4702 | ||
4703 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4704 | { | |
4705 | if (TREE_CODE (field) == FIELD_DECL) | |
4706 | { | |
75131237 RK |
4707 | HOST_WIDE_INT bitpos = startbitpos; |
4708 | ||
4709 | if (DECL_SIZE (field) != 0 | |
4710 | && host_integerp (bit_position (field), 1)) | |
4711 | bitpos += int_bit_position (field); | |
4712 | ||
82d6b402 RH |
4713 | /* ??? FIXME: else assume zero offset. */ |
4714 | ||
4715 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
75131237 | 4716 | function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms); |
105b2084 JJ |
4717 | else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE |
4718 | || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE | |
4719 | && (TREE_CODE (TREE_TYPE (TREE_TYPE (field))) | |
4720 | == REAL_TYPE))) | |
82d6b402 RH |
4721 | && TARGET_FPU |
4722 | && ! packed_p | |
4723 | && parms->named) | |
4724 | { | |
4725 | int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; | |
105b2084 JJ |
4726 | int regno; |
4727 | enum machine_mode mode = DECL_MODE (field); | |
82d6b402 RH |
4728 | rtx reg; |
4729 | ||
4730 | function_arg_record_value_3 (bitpos, parms); | |
105b2084 JJ |
4731 | regno = SPARC_FP_ARG_FIRST + this_slotno * 2 |
4732 | + ((mode == SFmode || mode == SCmode) | |
4733 | && (bitpos & 32) != 0); | |
4734 | switch (mode) | |
4735 | { | |
4736 | case SCmode: mode = SFmode; break; | |
4737 | case DCmode: mode = DFmode; break; | |
4738 | case TCmode: mode = TFmode; break; | |
4739 | default: break; | |
4740 | } | |
4741 | reg = gen_rtx_REG (mode, regno); | |
82d6b402 | 4742 | XVECEXP (parms->ret, 0, parms->nregs) |
254110c2 | 4743 | = gen_rtx_EXPR_LIST (VOIDmode, reg, |
82d6b402 RH |
4744 | GEN_INT (bitpos / BITS_PER_UNIT)); |
4745 | parms->nregs += 1; | |
105b2084 JJ |
4746 | if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) |
4747 | { | |
4748 | regno += GET_MODE_SIZE (mode) / 4; | |
4749 | reg = gen_rtx_REG (mode, regno); | |
4750 | XVECEXP (parms->ret, 0, parms->nregs) | |
4751 | = gen_rtx_EXPR_LIST (VOIDmode, reg, | |
4752 | GEN_INT ((bitpos + GET_MODE_BITSIZE (mode)) | |
4753 | / BITS_PER_UNIT)); | |
4754 | parms->nregs += 1; | |
4755 | } | |
82d6b402 RH |
4756 | } |
4757 | else | |
4758 | { | |
4759 | if (parms->intoffset == -1) | |
4760 | parms->intoffset = bitpos; | |
4761 | } | |
4762 | } | |
4763 | } | |
4764 | } | |
4765 | ||
0020b823 RH |
4766 | /* Used by function_arg and function_value to implement the complex |
4767 | Sparc64 structure calling conventions. */ | |
4768 | ||
82d6b402 | 4769 | static rtx |
1eac9f59 | 4770 | function_arg_record_value (type, mode, slotno, named, regbase) |
82d6b402 | 4771 | tree type; |
1eac9f59 | 4772 | enum machine_mode mode; |
82d6b402 RH |
4773 | int slotno, named, regbase; |
4774 | { | |
4775 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
4776 | struct function_arg_record_value_parms parms; | |
75131237 | 4777 | unsigned int nregs; |
82d6b402 RH |
4778 | |
4779 | parms.ret = NULL_RTX; | |
4780 | parms.slotno = slotno; | |
4781 | parms.named = named; | |
4782 | parms.regbase = regbase; | |
4783 | ||
4784 | /* Compute how many registers we need. */ | |
4785 | parms.nregs = 0; | |
4786 | parms.intoffset = 0; | |
4787 | function_arg_record_value_1 (type, 0, &parms); | |
4788 | ||
4789 | if (parms.intoffset != -1) | |
4790 | { | |
0020b823 | 4791 | unsigned int startbit, endbit; |
82d6b402 RH |
4792 | int intslots, this_slotno; |
4793 | ||
0020b823 RH |
4794 | startbit = parms.intoffset & -BITS_PER_WORD; |
4795 | endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4796 | intslots = (endbit - startbit) / BITS_PER_WORD; | |
82d6b402 RH |
4797 | this_slotno = slotno + parms.intoffset / BITS_PER_WORD; |
4798 | ||
4799 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
4800 | intslots = MAX (intslots, 0); | |
4801 | ||
4802 | parms.nregs += intslots; | |
4803 | } | |
4804 | nregs = parms.nregs; | |
4805 | ||
4806 | /* Allocate the vector and handle some annoying special cases. */ | |
4807 | if (nregs == 0) | |
4808 | { | |
4809 | /* ??? Empty structure has no value? Duh? */ | |
4810 | if (typesize <= 0) | |
4811 | { | |
4812 | /* Though there's nothing really to store, return a word register | |
4813 | anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL | |
4814 | leads to breakage due to the fact that there are zero bytes to | |
4815 | load. */ | |
1eac9f59 | 4816 | return gen_rtx_REG (mode, regbase); |
82d6b402 RH |
4817 | } |
4818 | else | |
4819 | { | |
4820 | /* ??? C++ has structures with no fields, and yet a size. Give up | |
4821 | for now and pass everything back in integer registers. */ | |
4822 | nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4823 | } | |
4824 | if (nregs + slotno > SPARC_INT_ARG_MAX) | |
4825 | nregs = SPARC_INT_ARG_MAX - slotno; | |
4826 | } | |
4827 | if (nregs == 0) | |
9208e4b2 | 4828 | abort (); |
82d6b402 | 4829 | |
1eac9f59 | 4830 | parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs)); |
82d6b402 RH |
4831 | |
4832 | /* Fill in the entries. */ | |
4833 | parms.nregs = 0; | |
4834 | parms.intoffset = 0; | |
4835 | function_arg_record_value_2 (type, 0, &parms); | |
4836 | function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); | |
4837 | ||
4838 | if (parms.nregs != nregs) | |
4839 | abort (); | |
4840 | ||
4841 | return parms.ret; | |
4842 | } | |
4843 | ||
4fb4e4b8 DE |
4844 | /* Handle the FUNCTION_ARG macro. |
4845 | Determine where to put an argument to a function. | |
4846 | Value is zero to push the argument on the stack, | |
4847 | or a hard register in which to store the argument. | |
4848 | ||
4849 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4850 | the preceding args and about the function being called. | |
4851 | MODE is the argument's machine mode. | |
4852 | TYPE is the data type of the argument (as a tree). | |
4853 | This is null for libcalls where that information may | |
4854 | not be available. | |
4855 | NAMED is nonzero if this argument is a named parameter | |
4856 | (otherwise it is an extra parameter matching an ellipsis). | |
4857 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ | |
61a55e8b DE |
4858 | |
4859 | rtx | |
4fb4e4b8 DE |
4860 | function_arg (cum, mode, type, named, incoming_p) |
4861 | const CUMULATIVE_ARGS *cum; | |
4862 | enum machine_mode mode; | |
4863 | tree type; | |
4864 | int named; | |
4865 | int incoming_p; | |
61a55e8b | 4866 | { |
4fb4e4b8 DE |
4867 | int regbase = (incoming_p |
4868 | ? SPARC_INCOMING_INT_ARG_FIRST | |
4869 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
4870 | int slotno, regno, padding; | |
4871 | rtx reg; | |
4872 | ||
4873 | slotno = function_arg_slotno (cum, mode, type, named, incoming_p, | |
4874 | ®no, &padding); | |
4875 | ||
4876 | if (slotno == -1) | |
4877 | return 0; | |
4878 | ||
4879 | if (TARGET_ARCH32) | |
4880 | { | |
254110c2 | 4881 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
4882 | return reg; |
4883 | } | |
4884 | ||
4885 | /* v9 fp args in reg slots beyond the int reg slots get passed in regs | |
4886 | but also have the slot allocated for them. | |
4887 | If no prototype is in scope fp values in register slots get passed | |
4888 | in two places, either fp regs and int regs or fp regs and memory. */ | |
4889 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
4890 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
4891 | && SPARC_FP_REG_P (regno)) | |
4892 | { | |
254110c2 | 4893 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
4894 | if (cum->prototype_p || cum->libcall_p) |
4895 | { | |
4896 | /* "* 2" because fp reg numbers are recorded in 4 byte | |
4897 | quantities. */ | |
82d6b402 | 4898 | #if 0 |
4fb4e4b8 DE |
4899 | /* ??? This will cause the value to be passed in the fp reg and |
4900 | in the stack. When a prototype exists we want to pass the | |
4901 | value in the reg but reserve space on the stack. That's an | |
956d6950 | 4902 | optimization, and is deferred [for a bit]. */ |
4fb4e4b8 | 4903 | if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) |
254110c2 | 4904 | return gen_rtx_PARALLEL (mode, |
4fb4e4b8 | 4905 | gen_rtvec (2, |
254110c2 | 4906 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 | 4907 | NULL_RTX, const0_rtx), |
254110c2 | 4908 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 DE |
4909 | reg, const0_rtx))); |
4910 | else | |
82d6b402 RH |
4911 | #else |
4912 | /* ??? It seems that passing back a register even when past | |
4913 | the area declared by REG_PARM_STACK_SPACE will allocate | |
4914 | space appropriately, and will not copy the data onto the | |
4915 | stack, exactly as we desire. | |
4916 | ||
4917 | This is due to locate_and_pad_parm being called in | |
4918 | expand_call whenever reg_parm_stack_space > 0, which | |
4919 | while benefical to our example here, would seem to be | |
4920 | in error from what had been intended. Ho hum... -- r~ */ | |
4921 | #endif | |
4fb4e4b8 DE |
4922 | return reg; |
4923 | } | |
4924 | else | |
4925 | { | |
82d6b402 RH |
4926 | rtx v0, v1; |
4927 | ||
4fb4e4b8 DE |
4928 | if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) |
4929 | { | |
82d6b402 RH |
4930 | int intreg; |
4931 | ||
4932 | /* On incoming, we don't need to know that the value | |
4933 | is passed in %f0 and %i0, and it confuses other parts | |
4934 | causing needless spillage even on the simplest cases. */ | |
4935 | if (incoming_p) | |
4936 | return reg; | |
4937 | ||
4938 | intreg = (SPARC_OUTGOING_INT_ARG_FIRST | |
4939 | + (regno - SPARC_FP_ARG_FIRST) / 2); | |
4940 | ||
4941 | v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
4942 | v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), | |
4943 | const0_rtx); | |
4944 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4fb4e4b8 DE |
4945 | } |
4946 | else | |
82d6b402 RH |
4947 | { |
4948 | v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
4949 | v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
4950 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4951 | } | |
4fb4e4b8 DE |
4952 | } |
4953 | } | |
4954 | else if (type && TREE_CODE (type) == RECORD_TYPE) | |
4955 | { | |
4956 | /* Structures up to 16 bytes in size are passed in arg slots on the | |
4957 | stack and are promoted to registers where possible. */ | |
4fb4e4b8 DE |
4958 | |
4959 | if (int_size_in_bytes (type) > 16) | |
4960 | abort (); /* shouldn't get here */ | |
4961 | ||
1eac9f59 | 4962 | return function_arg_record_value (type, mode, slotno, named, regbase); |
4fb4e4b8 DE |
4963 | } |
4964 | else if (type && TREE_CODE (type) == UNION_TYPE) | |
4965 | { | |
4966 | enum machine_mode mode; | |
4967 | int bytes = int_size_in_bytes (type); | |
4968 | ||
4969 | if (bytes > 16) | |
4970 | abort (); | |
4971 | ||
4972 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
254110c2 | 4973 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 | 4974 | } |
a7acd911 | 4975 | else |
4fb4e4b8 DE |
4976 | { |
4977 | /* Scalar or complex int. */ | |
254110c2 | 4978 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
4979 | } |
4980 | ||
4981 | return reg; | |
4982 | } | |
a7acd911 | 4983 | |
4fb4e4b8 DE |
4984 | /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro. |
4985 | For an arg passed partly in registers and partly in memory, | |
4986 | this is the number of registers used. | |
4987 | For args passed entirely in registers or entirely in memory, zero. | |
61a55e8b | 4988 | |
4fb4e4b8 DE |
4989 | Any arg that starts in the first 6 regs but won't entirely fit in them |
4990 | needs partial registers on v8. On v9, structures with integer | |
4991 | values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp | |
4992 | values that begin in the last fp reg [where "last fp reg" varies with the | |
4993 | mode] will be split between that reg and memory. */ | |
61a55e8b | 4994 | |
4fb4e4b8 DE |
4995 | int |
4996 | function_arg_partial_nregs (cum, mode, type, named) | |
4997 | const CUMULATIVE_ARGS *cum; | |
4998 | enum machine_mode mode; | |
4999 | tree type; | |
5000 | int named; | |
5001 | { | |
5002 | int slotno, regno, padding; | |
61a55e8b | 5003 | |
4fb4e4b8 DE |
5004 | /* We pass 0 for incoming_p here, it doesn't matter. */ |
5005 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
5006 | ||
5007 | if (slotno == -1) | |
5008 | return 0; | |
5009 | ||
5010 | if (TARGET_ARCH32) | |
bf62bbf1 | 5011 | { |
4fb4e4b8 DE |
5012 | if ((slotno + (mode == BLKmode |
5013 | ? ROUND_ADVANCE (int_size_in_bytes (type)) | |
5014 | : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) | |
5015 | > NPARM_REGS (SImode)) | |
5016 | return NPARM_REGS (SImode) - slotno; | |
5017 | return 0; | |
5018 | } | |
5019 | else | |
5020 | { | |
5021 | if (type && AGGREGATE_TYPE_P (type)) | |
5022 | { | |
5023 | int size = int_size_in_bytes (type); | |
5024 | int align = TYPE_ALIGN (type); | |
bf62bbf1 | 5025 | |
4fb4e4b8 DE |
5026 | if (align == 16) |
5027 | slotno += slotno & 1; | |
5028 | if (size > 8 && size <= 16 | |
5029 | && slotno == SPARC_INT_ARG_MAX - 1) | |
5030 | return 1; | |
5031 | } | |
5032 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT | |
5033 | || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
5034 | && ! TARGET_FPU)) | |
5035 | { | |
5036 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
5037 | { | |
5038 | slotno += slotno & 1; | |
5039 | if (slotno == SPARC_INT_ARG_MAX - 2) | |
5040 | return 1; | |
5041 | } | |
5042 | else | |
5043 | { | |
5044 | if (slotno == SPARC_INT_ARG_MAX - 1) | |
5045 | return 1; | |
5046 | } | |
5047 | } | |
5048 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5049 | { | |
5050 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
5051 | slotno += slotno & 1; | |
5052 | if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) | |
5053 | > SPARC_FP_ARG_MAX) | |
5054 | return 1; | |
5055 | } | |
5056 | return 0; | |
bf62bbf1 | 5057 | } |
4fb4e4b8 | 5058 | } |
61a55e8b | 5059 | |
4fb4e4b8 DE |
5060 | /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro. |
5061 | !v9: The SPARC ABI stipulates passing struct arguments (of any size) and | |
5062 | quad-precision floats by invisible reference. | |
82d6b402 | 5063 | v9: Aggregates greater than 16 bytes are passed by reference. |
4fb4e4b8 DE |
5064 | For Pascal, also pass arrays by reference. */ |
5065 | ||
5066 | int | |
5067 | function_arg_pass_by_reference (cum, mode, type, named) | |
db3d4438 | 5068 | const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
5069 | enum machine_mode mode; |
5070 | tree type; | |
db3d4438 | 5071 | int named ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
5072 | { |
5073 | if (TARGET_ARCH32) | |
eadceb59 | 5074 | { |
5e9defae | 5075 | return ((type && AGGREGATE_TYPE_P (type)) |
4fb4e4b8 DE |
5076 | || mode == TFmode || mode == TCmode); |
5077 | } | |
5078 | else | |
5079 | { | |
5080 | return ((type && TREE_CODE (type) == ARRAY_TYPE) | |
80ffc95e | 5081 | /* Consider complex values as aggregates, so care for TCmode. */ |
82d6b402 | 5082 | || GET_MODE_SIZE (mode) > 16 |
f36dea3c RH |
5083 | || (type |
5084 | && AGGREGATE_TYPE_P (type) | |
5085 | && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)); | |
4fb4e4b8 DE |
5086 | } |
5087 | } | |
5088 | ||
5089 | /* Handle the FUNCTION_ARG_ADVANCE macro. | |
5090 | Update the data in CUM to advance over an argument | |
5091 | of mode MODE and data type TYPE. | |
5092 | TYPE is null for libcalls where that information may not be available. */ | |
5093 | ||
5094 | void | |
5095 | function_arg_advance (cum, mode, type, named) | |
5096 | CUMULATIVE_ARGS *cum; | |
5097 | enum machine_mode mode; | |
5098 | tree type; | |
5099 | int named; | |
5100 | { | |
5101 | int slotno, regno, padding; | |
5102 | ||
5103 | /* We pass 0 for incoming_p here, it doesn't matter. */ | |
5104 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
5105 | ||
5106 | /* If register required leading padding, add it. */ | |
5107 | if (slotno != -1) | |
5108 | cum->words += padding; | |
eadceb59 | 5109 | |
4fb4e4b8 DE |
5110 | if (TARGET_ARCH32) |
5111 | { | |
5112 | cum->words += (mode != BLKmode | |
5113 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
5114 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
5115 | } | |
5116 | else | |
5117 | { | |
5118 | if (type && AGGREGATE_TYPE_P (type)) | |
5119 | { | |
5120 | int size = int_size_in_bytes (type); | |
5121 | ||
5122 | if (size <= 8) | |
5123 | ++cum->words; | |
5124 | else if (size <= 16) | |
5125 | cum->words += 2; | |
5126 | else /* passed by reference */ | |
5127 | ++cum->words; | |
5128 | } | |
5129 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) | |
5130 | { | |
5131 | cum->words += 2; | |
5132 | } | |
5133 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5134 | { | |
5135 | cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD; | |
5136 | } | |
5137 | else | |
5138 | { | |
5139 | cum->words += (mode != BLKmode | |
5140 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
5141 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
5142 | } | |
eadceb59 | 5143 | } |
4fb4e4b8 | 5144 | } |
eadceb59 | 5145 | |
4fb4e4b8 DE |
5146 | /* Handle the FUNCTION_ARG_PADDING macro. |
5147 | For the 64 bit ABI structs are always stored left shifted in their | |
5148 | argument slot. */ | |
5149 | ||
5150 | enum direction | |
5151 | function_arg_padding (mode, type) | |
5152 | enum machine_mode mode; | |
5153 | tree type; | |
5154 | { | |
c85f7c16 JL |
5155 | if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) |
5156 | return upward; | |
61a55e8b | 5157 | |
4fb4e4b8 DE |
5158 | /* This is the default definition. */ |
5159 | return (! BYTES_BIG_ENDIAN | |
5160 | ? upward | |
5161 | : ((mode == BLKmode | |
5162 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
5163 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
5164 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
5165 | ? downward : upward)); | |
61a55e8b | 5166 | } |
82d6b402 RH |
5167 | |
5168 | /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. | |
5169 | For v9, function return values are subject to the same rules as arguments, | |
5170 | except that up to 32-bytes may be returned in registers. */ | |
5171 | ||
5172 | rtx | |
5173 | function_value (type, mode, incoming_p) | |
5174 | tree type; | |
5175 | enum machine_mode mode; | |
5176 | int incoming_p; | |
5177 | { | |
5178 | int regno; | |
5179 | int regbase = (incoming_p | |
5180 | ? SPARC_OUTGOING_INT_ARG_FIRST | |
5181 | : SPARC_INCOMING_INT_ARG_FIRST); | |
5182 | ||
5183 | if (TARGET_ARCH64 && type) | |
5184 | { | |
5185 | if (TREE_CODE (type) == RECORD_TYPE) | |
5186 | { | |
5187 | /* Structures up to 32 bytes in size are passed in registers, | |
5188 | promoted to fp registers where possible. */ | |
5189 | ||
5190 | if (int_size_in_bytes (type) > 32) | |
5191 | abort (); /* shouldn't get here */ | |
5192 | ||
1eac9f59 | 5193 | return function_arg_record_value (type, mode, 0, 1, regbase); |
82d6b402 | 5194 | } |
8a7199ad | 5195 | else if (AGGREGATE_TYPE_P (type)) |
82d6b402 | 5196 | { |
8a7199ad RK |
5197 | /* All other aggregate types are passed in an integer register |
5198 | in a mode corresponding to the size of the type. */ | |
5199 | HOST_WIDE_INT bytes = int_size_in_bytes (type); | |
82d6b402 RH |
5200 | |
5201 | if (bytes > 32) | |
5202 | abort (); | |
5203 | ||
5204 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
5205 | } | |
5206 | } | |
3c6088d2 JJ |
5207 | |
5208 | if (TARGET_ARCH64 | |
5209 | && GET_MODE_CLASS (mode) == MODE_INT | |
5210 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
8a7199ad | 5211 | && type && ! AGGREGATE_TYPE_P (type)) |
3c6088d2 | 5212 | mode = DImode; |
82d6b402 RH |
5213 | |
5214 | if (incoming_p) | |
5215 | regno = BASE_RETURN_VALUE_REG (mode); | |
5216 | else | |
5217 | regno = BASE_OUTGOING_VALUE_REG (mode); | |
5218 | ||
254110c2 | 5219 | return gen_rtx_REG (mode, regno); |
82d6b402 RH |
5220 | } |
5221 | ||
648d2ffc RH |
5222 | /* Do what is necessary for `va_start'. We look at the current function |
5223 | to determine if stdarg or varargs is used and return the address of | |
5224 | the first unnamed parameter. */ | |
3ea1fdd3 JW |
5225 | |
5226 | rtx | |
648d2ffc | 5227 | sparc_builtin_saveregs () |
3ea1fdd3 | 5228 | { |
4fb4e4b8 | 5229 | int first_reg = current_function_args_info.words; |
3ea1fdd3 JW |
5230 | rtx address; |
5231 | int regno; | |
5232 | ||
4fb4e4b8 | 5233 | for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++) |
254110c2 | 5234 | emit_move_insn (gen_rtx_MEM (word_mode, |
8ac61af7 RK |
5235 | gen_rtx_PLUS (Pmode, |
5236 | frame_pointer_rtx, | |
563c12b0 | 5237 | GEN_INT (FIRST_PARM_OFFSET (0) |
8ac61af7 RK |
5238 | + (UNITS_PER_WORD |
5239 | * regno)))), | |
254110c2 | 5240 | gen_rtx_REG (word_mode, |
8ac61af7 | 5241 | BASE_INCOMING_ARG_REG (word_mode) + regno)); |
3ea1fdd3 | 5242 | |
254110c2 | 5243 | address = gen_rtx_PLUS (Pmode, |
8ac61af7 | 5244 | frame_pointer_rtx, |
563c12b0 | 5245 | GEN_INT (FIRST_PARM_OFFSET (0) |
8ac61af7 | 5246 | + UNITS_PER_WORD * first_reg)); |
3ea1fdd3 JW |
5247 | |
5248 | return address; | |
5249 | } | |
a8b2c8a1 RH |
5250 | |
5251 | /* Implement `va_start' for varargs and stdarg. */ | |
5252 | ||
5253 | void | |
5254 | sparc_va_start (stdarg_p, valist, nextarg) | |
5255 | int stdarg_p ATTRIBUTE_UNUSED; | |
5256 | tree valist; | |
5257 | rtx nextarg; | |
5258 | { | |
5259 | nextarg = expand_builtin_saveregs (); | |
5260 | std_expand_builtin_va_start (1, valist, nextarg); | |
5261 | } | |
5262 | ||
5263 | /* Implement `va_arg'. */ | |
5264 | ||
5265 | rtx | |
5266 | sparc_va_arg (valist, type) | |
5267 | tree valist, type; | |
5268 | { | |
5269 | HOST_WIDE_INT size, rsize, align; | |
da09e317 | 5270 | tree addr, incr; |
a8b2c8a1 RH |
5271 | rtx addr_rtx; |
5272 | int indirect = 0; | |
5273 | ||
5274 | /* Round up sizeof(type) to a word. */ | |
5275 | size = int_size_in_bytes (type); | |
5276 | rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; | |
5277 | align = 0; | |
5278 | ||
5279 | if (TARGET_ARCH64) | |
5280 | { | |
fbd039b2 | 5281 | if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) |
a8b2c8a1 RH |
5282 | align = 2 * UNITS_PER_WORD; |
5283 | ||
f34e52f7 | 5284 | if (AGGREGATE_TYPE_P (type)) |
a8b2c8a1 | 5285 | { |
f36dea3c | 5286 | if ((unsigned HOST_WIDE_INT) size > 16) |
f34e52f7 JJ |
5287 | { |
5288 | indirect = 1; | |
5289 | size = rsize = UNITS_PER_WORD; | |
5290 | } | |
014c0998 JJ |
5291 | /* SPARC v9 ABI states that structures up to 8 bytes in size are |
5292 | given one 8 byte slot. */ | |
5293 | else if (size == 0) | |
5294 | size = rsize = UNITS_PER_WORD; | |
f34e52f7 JJ |
5295 | else |
5296 | size = rsize; | |
a8b2c8a1 RH |
5297 | } |
5298 | } | |
5299 | else | |
5300 | { | |
5301 | if (AGGREGATE_TYPE_P (type) | |
5302 | || TYPE_MODE (type) == TFmode | |
5303 | || TYPE_MODE (type) == TCmode) | |
5304 | { | |
5305 | indirect = 1; | |
5306 | size = rsize = UNITS_PER_WORD; | |
5307 | } | |
a8b2c8a1 RH |
5308 | } |
5309 | ||
5310 | incr = valist; | |
5311 | if (align) | |
5312 | { | |
5313 | incr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
5314 | build_int_2 (align - 1, 0))); | |
5315 | incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr, | |
5316 | build_int_2 (-align, -1))); | |
5317 | } | |
5318 | ||
5319 | addr = incr = save_expr (incr); | |
5320 | if (BYTES_BIG_ENDIAN && size < rsize) | |
5321 | { | |
5322 | addr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
5323 | build_int_2 (rsize - size, 0))); | |
5324 | } | |
5325 | incr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
5326 | build_int_2 (rsize, 0))); | |
5327 | ||
5328 | incr = build (MODIFY_EXPR, ptr_type_node, valist, incr); | |
5329 | TREE_SIDE_EFFECTS (incr) = 1; | |
5330 | expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5331 | ||
5332 | addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); | |
5333 | ||
9a0662b4 GK |
5334 | /* If the address isn't aligned properly for the type, |
5335 | we may need to copy to a temporary. | |
5336 | FIXME: This is inefficient. Usually we can do this | |
5337 | in registers. */ | |
5338 | if (align == 0 | |
5339 | && TYPE_ALIGN (type) > BITS_PER_WORD | |
5340 | && !indirect) | |
5341 | { | |
5342 | /* FIXME: We really need to specify that the temporary is live | |
5343 | for the whole function because expand_builtin_va_arg wants | |
5344 | the alias set to be get_varargs_alias_set (), but in this | |
5345 | case the alias set is that for TYPE and if the memory gets | |
5346 | reused it will be reused with alias set TYPE. */ | |
5347 | rtx tmp = assign_temp (type, 0, 1, 0); | |
5348 | rtx dest_addr; | |
5349 | ||
5350 | addr_rtx = force_reg (Pmode, addr_rtx); | |
5351 | addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx); | |
ba4828e0 | 5352 | set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); |
8ac61af7 | 5353 | set_mem_align (addr_rtx, BITS_PER_WORD); |
9a0662b4 GK |
5354 | tmp = shallow_copy_rtx (tmp); |
5355 | PUT_MODE (tmp, BLKmode); | |
ba4828e0 | 5356 | set_mem_alias_set (tmp, 0); |
9a0662b4 | 5357 | |
8ac61af7 | 5358 | dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize)); |
9a0662b4 GK |
5359 | if (dest_addr != NULL_RTX) |
5360 | addr_rtx = dest_addr; | |
5361 | else | |
5362 | addr_rtx = XCEXP (tmp, 0, MEM); | |
5363 | } | |
5364 | ||
a8b2c8a1 RH |
5365 | if (indirect) |
5366 | { | |
5367 | addr_rtx = force_reg (Pmode, addr_rtx); | |
5368 | addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 5369 | set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); |
a8b2c8a1 RH |
5370 | } |
5371 | ||
5372 | return addr_rtx; | |
5373 | } | |
ab835497 RK |
5374 | \f |
5375 | /* Return the string to output a conditional branch to LABEL, which is | |
c4ce6853 DE |
5376 | the operand number of the label. OP is the conditional expression. |
5377 | XEXP (OP, 0) is assumed to be a condition code register (integer or | |
5378 | floating point) and its mode specifies what kind of comparison we made. | |
61a55e8b | 5379 | |
ab835497 RK |
5380 | REVERSED is non-zero if we should reverse the sense of the comparison. |
5381 | ||
5382 | ANNUL is non-zero if we should generate an annulling branch. | |
5383 | ||
c6b0465b JC |
5384 | NOOP is non-zero if we have to follow this branch by a noop. |
5385 | ||
5386 | INSN, if set, is the insn. */ | |
ab835497 RK |
5387 | |
5388 | char * | |
0b82d204 JJ |
5389 | output_cbranch (op, dest, label, reversed, annul, noop, insn) |
5390 | rtx op, dest; | |
ab835497 RK |
5391 | int label; |
5392 | int reversed, annul, noop; | |
c6b0465b | 5393 | rtx insn; |
ab835497 | 5394 | { |
0b82d204 | 5395 | static char string[50]; |
ab835497 | 5396 | enum rtx_code code = GET_CODE (op); |
c4ce6853 DE |
5397 | rtx cc_reg = XEXP (op, 0); |
5398 | enum machine_mode mode = GET_MODE (cc_reg); | |
0b82d204 JJ |
5399 | const char *labelno, *branch; |
5400 | int spaces = 8, far; | |
5401 | char *p; | |
5402 | ||
5403 | /* v9 branches are limited to +-1MB. If it is too far away, | |
5404 | change | |
5405 | ||
5406 | bne,pt %xcc, .LC30 | |
5407 | ||
5408 | to | |
5409 | ||
5410 | be,pn %xcc, .+12 | |
5411 | nop | |
5412 | ba .LC30 | |
5413 | ||
5414 | and | |
5415 | ||
5416 | fbne,a,pn %fcc2, .LC29 | |
61a55e8b | 5417 | |
0b82d204 JJ |
5418 | to |
5419 | ||
5420 | fbe,pt %fcc2, .+16 | |
5421 | nop | |
5422 | ba .LC29 */ | |
5423 | ||
5424 | far = get_attr_length (insn) >= 3; | |
5425 | if (reversed ^ far) | |
ab835497 | 5426 | { |
e267e177 RH |
5427 | /* Reversal of FP compares takes care -- an ordered compare |
5428 | becomes an unordered compare and vice versa. */ | |
4d449554 | 5429 | if (mode == CCFPmode || mode == CCFPEmode) |
7913f3d0 | 5430 | code = reverse_condition_maybe_unordered (code); |
ab835497 | 5431 | else |
e267e177 | 5432 | code = reverse_condition (code); |
ab835497 RK |
5433 | } |
5434 | ||
e267e177 RH |
5435 | /* Start by writing the branch condition. */ |
5436 | if (mode == CCFPmode || mode == CCFPEmode) | |
5850dc00 RH |
5437 | { |
5438 | switch (code) | |
5439 | { | |
5440 | case NE: | |
5441 | branch = "fbne"; | |
5442 | break; | |
5443 | case EQ: | |
5444 | branch = "fbe"; | |
5445 | break; | |
5446 | case GE: | |
5447 | branch = "fbge"; | |
5448 | break; | |
5449 | case GT: | |
5450 | branch = "fbg"; | |
5451 | break; | |
5452 | case LE: | |
5453 | branch = "fble"; | |
5454 | break; | |
5455 | case LT: | |
5456 | branch = "fbl"; | |
5457 | break; | |
5458 | case UNORDERED: | |
5459 | branch = "fbu"; | |
5460 | break; | |
5461 | case ORDERED: | |
5462 | branch = "fbo"; | |
5463 | break; | |
5464 | case UNGT: | |
5465 | branch = "fbug"; | |
5466 | break; | |
5467 | case UNLT: | |
5468 | branch = "fbul"; | |
5469 | break; | |
5470 | case UNEQ: | |
5471 | branch = "fbue"; | |
5472 | break; | |
5473 | case UNGE: | |
5474 | branch = "fbuge"; | |
5475 | break; | |
5476 | case UNLE: | |
5477 | branch = "fbule"; | |
5478 | break; | |
5479 | case LTGT: | |
5480 | branch = "fblg"; | |
5481 | break; | |
5482 | ||
5483 | default: | |
5484 | abort (); | |
5485 | } | |
5486 | ||
5487 | /* ??? !v9: FP branches cannot be preceded by another floating point | |
5488 | insn. Because there is currently no concept of pre-delay slots, | |
5489 | we can fix this only by always emitting a nop before a floating | |
5490 | point branch. */ | |
5491 | ||
5492 | string[0] = '\0'; | |
5493 | if (! TARGET_V9) | |
5494 | strcpy (string, "nop\n\t"); | |
5495 | strcat (string, branch); | |
5496 | } | |
e267e177 | 5497 | else |
5850dc00 RH |
5498 | { |
5499 | switch (code) | |
5500 | { | |
5501 | case NE: | |
5502 | branch = "bne"; | |
5503 | break; | |
5504 | case EQ: | |
5505 | branch = "be"; | |
5506 | break; | |
5507 | case GE: | |
0b82d204 | 5508 | if (mode == CC_NOOVmode || mode == CCX_NOOVmode) |
5850dc00 RH |
5509 | branch = "bpos"; |
5510 | else | |
5511 | branch = "bge"; | |
5512 | break; | |
5513 | case GT: | |
5514 | branch = "bg"; | |
5515 | break; | |
5516 | case LE: | |
5517 | branch = "ble"; | |
5518 | break; | |
5519 | case LT: | |
0b82d204 | 5520 | if (mode == CC_NOOVmode || mode == CCX_NOOVmode) |
5850dc00 RH |
5521 | branch = "bneg"; |
5522 | else | |
5523 | branch = "bl"; | |
5524 | break; | |
5525 | case GEU: | |
5526 | branch = "bgeu"; | |
5527 | break; | |
5528 | case GTU: | |
5529 | branch = "bgu"; | |
5530 | break; | |
5531 | case LEU: | |
5532 | branch = "bleu"; | |
5533 | break; | |
5534 | case LTU: | |
5535 | branch = "blu"; | |
5536 | break; | |
5537 | ||
5538 | default: | |
5539 | abort (); | |
5540 | } | |
5541 | strcpy (string, branch); | |
5542 | } | |
e267e177 | 5543 | spaces -= strlen (branch); |
0b82d204 | 5544 | p = strchr (string, '\0'); |
e267e177 | 5545 | |
ab835497 | 5546 | /* Now add the annulling, the label, and a possible noop. */ |
0b82d204 | 5547 | if (annul && ! far) |
e0d80184 | 5548 | { |
0b82d204 JJ |
5549 | strcpy (p, ",a"); |
5550 | p += 2; | |
e0d80184 DM |
5551 | spaces -= 2; |
5552 | } | |
ab835497 | 5553 | |
61a55e8b | 5554 | if (! TARGET_V9) |
0b82d204 | 5555 | labelno = ""; |
61a55e8b DE |
5556 | else |
5557 | { | |
c6b0465b | 5558 | rtx note; |
0b82d204 | 5559 | int v8 = 0; |
c6b0465b | 5560 | |
0b82d204 | 5561 | if (! far && insn && INSN_ADDRESSES_SET_P ()) |
e0d80184 | 5562 | { |
0b82d204 JJ |
5563 | int delta = (INSN_ADDRESSES (INSN_UID (dest)) |
5564 | - INSN_ADDRESSES (INSN_UID (insn))); | |
5565 | /* Leave some instructions for "slop". */ | |
5566 | if (delta < -260000 || delta >= 260000) | |
5567 | v8 = 1; | |
e0d80184 | 5568 | } |
c6b0465b | 5569 | |
61a55e8b DE |
5570 | if (mode == CCFPmode || mode == CCFPEmode) |
5571 | { | |
0b82d204 | 5572 | static char v9_fcc_labelno[] = "%%fccX, "; |
61a55e8b | 5573 | /* Set the char indicating the number of the fcc reg to use. */ |
0b82d204 JJ |
5574 | v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; |
5575 | labelno = v9_fcc_labelno; | |
5576 | if (v8) | |
5577 | { | |
5578 | if (REGNO (cc_reg) == SPARC_FCC_REG) | |
5579 | labelno = ""; | |
5580 | else | |
5581 | abort (); | |
5582 | } | |
61a55e8b DE |
5583 | } |
5584 | else if (mode == CCXmode || mode == CCX_NOOVmode) | |
0b82d204 JJ |
5585 | { |
5586 | labelno = "%%xcc, "; | |
5587 | if (v8) | |
5588 | abort (); | |
5589 | } | |
61a55e8b | 5590 | else |
0b82d204 JJ |
5591 | { |
5592 | labelno = "%%icc, "; | |
5593 | if (v8) | |
5594 | labelno = ""; | |
5595 | } | |
5596 | ||
4f31cce8 | 5597 | if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) |
0b82d204 JJ |
5598 | { |
5599 | strcpy (p, | |
4f31cce8 | 5600 | ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) |
0b82d204 JJ |
5601 | ? ",pt" : ",pn"); |
5602 | p += 3; | |
5603 | spaces -= 3; | |
5604 | } | |
61a55e8b | 5605 | } |
e0d80184 | 5606 | if (spaces > 0) |
0b82d204 | 5607 | *p++ = '\t'; |
e0d80184 | 5608 | else |
0b82d204 JJ |
5609 | *p++ = ' '; |
5610 | strcpy (p, labelno); | |
5611 | p = strchr (p, '\0'); | |
5612 | if (far) | |
5613 | { | |
5614 | strcpy (p, ".+12\n\tnop\n\tb\t"); | |
5615 | if (annul || noop) | |
5616 | p[3] = '6'; | |
5617 | p += 13; | |
5618 | } | |
5619 | *p++ = '%'; | |
5620 | *p++ = 'l'; | |
5621 | /* Set the char indicating the number of the operand containing the | |
5622 | label_ref. */ | |
5623 | *p++ = label + '0'; | |
5624 | *p = '\0'; | |
61a55e8b | 5625 | if (noop) |
0b82d204 | 5626 | strcpy (p, "\n\tnop"); |
61a55e8b DE |
5627 | |
5628 | return string; | |
5629 | } | |
5630 | ||
47ac041c JJ |
5631 | /* Emit a library call comparison between floating point X and Y. |
5632 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). | |
5633 | TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode | |
5634 | values as arguments instead of the TFmode registers themselves, | |
5635 | that's why we cannot call emit_float_lib_cmp. */ | |
5636 | void | |
5637 | sparc_emit_float_lib_cmp (x, y, comparison) | |
5638 | rtx x, y; | |
5639 | enum rtx_code comparison; | |
5640 | { | |
e77d72cb | 5641 | const char *qpfunc; |
5c5c34a4 JJ |
5642 | rtx slot0, slot1, result, tem, tem2; |
5643 | enum machine_mode mode; | |
47ac041c JJ |
5644 | |
5645 | switch (comparison) | |
5646 | { | |
5647 | case EQ: | |
5c5c34a4 | 5648 | qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq"; |
47ac041c JJ |
5649 | break; |
5650 | ||
5651 | case NE: | |
5c5c34a4 | 5652 | qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne"; |
47ac041c JJ |
5653 | break; |
5654 | ||
5655 | case GT: | |
5c5c34a4 | 5656 | qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt"; |
47ac041c JJ |
5657 | break; |
5658 | ||
5659 | case GE: | |
5c5c34a4 | 5660 | qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge"; |
47ac041c JJ |
5661 | break; |
5662 | ||
5663 | case LT: | |
5c5c34a4 | 5664 | qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt"; |
47ac041c JJ |
5665 | break; |
5666 | ||
5667 | case LE: | |
5c5c34a4 JJ |
5668 | qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle"; |
5669 | break; | |
5670 | ||
5671 | case ORDERED: | |
5672 | case UNORDERED: | |
5673 | case UNGT: | |
5674 | case UNLT: | |
5675 | case UNEQ: | |
5676 | case UNGE: | |
5677 | case UNLE: | |
5678 | case LTGT: | |
5679 | qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp"; | |
47ac041c JJ |
5680 | break; |
5681 | ||
5682 | default: | |
5683 | abort(); | |
5684 | break; | |
5685 | } | |
5686 | ||
5c5c34a4 | 5687 | if (TARGET_ARCH64) |
47ac041c | 5688 | { |
5c5c34a4 JJ |
5689 | if (GET_CODE (x) != MEM) |
5690 | { | |
5691 | slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); | |
5692 | emit_insn (gen_rtx_SET (VOIDmode, slot0, x)); | |
5693 | } | |
5694 | else | |
5695 | slot0 = x; | |
5696 | ||
5697 | if (GET_CODE (y) != MEM) | |
5698 | { | |
5699 | slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); | |
5700 | emit_insn (gen_rtx_SET (VOIDmode, slot1, y)); | |
5701 | } | |
5702 | else | |
5703 | slot1 = y; | |
47ac041c | 5704 | |
eb29ddb6 | 5705 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, |
5c5c34a4 JJ |
5706 | DImode, 2, |
5707 | XEXP (slot0, 0), Pmode, | |
5708 | XEXP (slot1, 0), Pmode); | |
5709 | ||
5710 | mode = DImode; | |
5711 | } | |
5712 | else | |
47ac041c | 5713 | { |
eb29ddb6 | 5714 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, |
5c5c34a4 JJ |
5715 | SImode, 2, |
5716 | x, TFmode, y, TFmode); | |
5717 | ||
5718 | mode = SImode; | |
47ac041c JJ |
5719 | } |
5720 | ||
47ac041c JJ |
5721 | |
5722 | /* Immediately move the result of the libcall into a pseudo | |
5723 | register so reload doesn't clobber the value if it needs | |
5724 | the return register for a spill reg. */ | |
5c5c34a4 JJ |
5725 | result = gen_reg_rtx (mode); |
5726 | emit_move_insn (result, hard_libcall_value (mode)); | |
47ac041c | 5727 | |
5c5c34a4 JJ |
5728 | switch (comparison) |
5729 | { | |
5730 | default: | |
3b2d1507 | 5731 | emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
5732 | break; |
5733 | case ORDERED: | |
5734 | case UNORDERED: | |
3b2d1507 AT |
5735 | emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE, |
5736 | NULL_RTX, mode, 0); | |
5c5c34a4 JJ |
5737 | break; |
5738 | case UNGT: | |
5739 | case UNGE: | |
5740 | emit_cmp_insn (result, const1_rtx, | |
3b2d1507 | 5741 | comparison == UNGT ? GT : NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
5742 | break; |
5743 | case UNLE: | |
3b2d1507 | 5744 | emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
5745 | break; |
5746 | case UNLT: | |
5747 | tem = gen_reg_rtx (mode); | |
5748 | if (TARGET_ARCH32) | |
5749 | emit_insn (gen_andsi3 (tem, result, const1_rtx)); | |
5750 | else | |
5751 | emit_insn (gen_anddi3 (tem, result, const1_rtx)); | |
3b2d1507 | 5752 | emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
5753 | break; |
5754 | case UNEQ: | |
5755 | case LTGT: | |
5756 | tem = gen_reg_rtx (mode); | |
5757 | if (TARGET_ARCH32) | |
5758 | emit_insn (gen_addsi3 (tem, result, const1_rtx)); | |
5759 | else | |
5760 | emit_insn (gen_adddi3 (tem, result, const1_rtx)); | |
5761 | tem2 = gen_reg_rtx (mode); | |
5762 | if (TARGET_ARCH32) | |
5763 | emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); | |
5764 | else | |
5765 | emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); | |
3b2d1507 AT |
5766 | emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE, |
5767 | NULL_RTX, mode, 0); | |
5c5c34a4 JJ |
5768 | break; |
5769 | } | |
47ac041c | 5770 | } |
5c5c34a4 | 5771 | |
d88e57d1 RH |
5772 | /* Generate an unsigned DImode to FP conversion. This is the same code |
5773 | optabs would emit if we didn't have TFmode patterns. */ | |
5774 | ||
5775 | void | |
5776 | sparc_emit_floatunsdi (operands) | |
5777 | rtx operands[2]; | |
5778 | { | |
5779 | rtx neglab, donelab, i0, i1, f0, in, out; | |
5780 | enum machine_mode mode; | |
5781 | ||
5782 | out = operands[0]; | |
5783 | in = force_reg (DImode, operands[1]); | |
5784 | mode = GET_MODE (out); | |
5785 | neglab = gen_label_rtx (); | |
5786 | donelab = gen_label_rtx (); | |
5787 | i0 = gen_reg_rtx (DImode); | |
5788 | i1 = gen_reg_rtx (DImode); | |
5789 | f0 = gen_reg_rtx (mode); | |
5790 | ||
5791 | emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); | |
5792 | ||
5793 | emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in))); | |
5794 | emit_jump_insn (gen_jump (donelab)); | |
5795 | emit_barrier (); | |
5796 | ||
5797 | emit_label (neglab); | |
5798 | ||
5799 | emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); | |
5800 | emit_insn (gen_anddi3 (i1, in, const1_rtx)); | |
5801 | emit_insn (gen_iordi3 (i0, i0, i1)); | |
5802 | emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0))); | |
5803 | emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0))); | |
5804 | ||
5805 | emit_label (donelab); | |
5806 | } | |
5807 | ||
61a55e8b DE |
5808 | /* Return the string to output a conditional branch to LABEL, testing |
5809 | register REG. LABEL is the operand number of the label; REG is the | |
5810 | operand number of the reg. OP is the conditional expression. The mode | |
5811 | of REG says what kind of comparison we made. | |
5812 | ||
5813 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
5814 | ||
5815 | ANNUL is non-zero if we should generate an annulling branch. | |
5816 | ||
5817 | NOOP is non-zero if we have to follow this branch by a noop. */ | |
5818 | ||
5819 | char * | |
0b82d204 JJ |
5820 | output_v9branch (op, dest, reg, label, reversed, annul, noop, insn) |
5821 | rtx op, dest; | |
61a55e8b DE |
5822 | int reg, label; |
5823 | int reversed, annul, noop; | |
e0d80184 | 5824 | rtx insn; |
61a55e8b | 5825 | { |
0b82d204 | 5826 | static char string[50]; |
61a55e8b DE |
5827 | enum rtx_code code = GET_CODE (op); |
5828 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
e0d80184 | 5829 | rtx note; |
0b82d204 JJ |
5830 | int far; |
5831 | char *p; | |
5832 | ||
5833 | /* branch on register are limited to +-128KB. If it is too far away, | |
5834 | change | |
5835 | ||
5836 | brnz,pt %g1, .LC30 | |
5837 | ||
5838 | to | |
5839 | ||
5840 | brz,pn %g1, .+12 | |
5841 | nop | |
5842 | ba,pt %xcc, .LC30 | |
5843 | ||
5844 | and | |
5845 | ||
5846 | brgez,a,pn %o1, .LC29 | |
5847 | ||
5848 | to | |
5849 | ||
5850 | brlz,pt %o1, .+16 | |
5851 | nop | |
5852 | ba,pt %xcc, .LC29 */ | |
5853 | ||
5854 | far = get_attr_length (insn) >= 3; | |
61a55e8b DE |
5855 | |
5856 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
0b82d204 JJ |
5857 | if (reversed ^ far) |
5858 | code = reverse_condition (code); | |
61a55e8b DE |
5859 | |
5860 | /* Only 64 bit versions of these instructions exist. */ | |
5861 | if (mode != DImode) | |
5862 | abort (); | |
5863 | ||
5864 | /* Start by writing the branch condition. */ | |
5865 | ||
5866 | switch (code) | |
5867 | { | |
5868 | case NE: | |
5869 | strcpy (string, "brnz"); | |
5870 | break; | |
5871 | ||
5872 | case EQ: | |
5873 | strcpy (string, "brz"); | |
5874 | break; | |
5875 | ||
5876 | case GE: | |
5877 | strcpy (string, "brgez"); | |
5878 | break; | |
5879 | ||
5880 | case LT: | |
5881 | strcpy (string, "brlz"); | |
5882 | break; | |
5883 | ||
5884 | case LE: | |
5885 | strcpy (string, "brlez"); | |
5886 | break; | |
5887 | ||
5888 | case GT: | |
5889 | strcpy (string, "brgz"); | |
5890 | break; | |
5891 | ||
5892 | default: | |
5893 | abort (); | |
5894 | } | |
5895 | ||
0b82d204 JJ |
5896 | p = strchr (string, '\0'); |
5897 | ||
61a55e8b | 5898 | /* Now add the annulling, reg, label, and nop. */ |
0b82d204 | 5899 | if (annul && ! far) |
e0d80184 | 5900 | { |
0b82d204 JJ |
5901 | strcpy (p, ",a"); |
5902 | p += 2; | |
e0d80184 | 5903 | } |
61a55e8b | 5904 | |
4f31cce8 | 5905 | if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) |
e0d80184 | 5906 | { |
0b82d204 | 5907 | strcpy (p, |
4f31cce8 | 5908 | ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) |
0b82d204 JJ |
5909 | ? ",pt" : ",pn"); |
5910 | p += 3; | |
e0d80184 | 5911 | } |
61a55e8b | 5912 | |
0b82d204 JJ |
5913 | *p = p < string + 8 ? '\t' : ' '; |
5914 | p++; | |
5915 | *p++ = '%'; | |
5916 | *p++ = '0' + reg; | |
5917 | *p++ = ','; | |
5918 | *p++ = ' '; | |
5919 | if (far) | |
5920 | { | |
5921 | int veryfar = 1, delta; | |
5922 | ||
5923 | if (INSN_ADDRESSES_SET_P ()) | |
5924 | { | |
5925 | delta = (INSN_ADDRESSES (INSN_UID (dest)) | |
5926 | - INSN_ADDRESSES (INSN_UID (insn))); | |
5927 | /* Leave some instructions for "slop". */ | |
5928 | if (delta >= -260000 && delta < 260000) | |
5929 | veryfar = 0; | |
5930 | } | |
5931 | ||
5932 | strcpy (p, ".+12\n\tnop\n\t"); | |
5933 | if (annul || noop) | |
5934 | p[3] = '6'; | |
5935 | p += 11; | |
5936 | if (veryfar) | |
5937 | { | |
5938 | strcpy (p, "b\t"); | |
5939 | p += 2; | |
5940 | } | |
5941 | else | |
5942 | { | |
5943 | strcpy (p, "ba,pt\t%%xcc, "); | |
5944 | p += 13; | |
5945 | } | |
5946 | } | |
5947 | *p++ = '%'; | |
5948 | *p++ = 'l'; | |
5949 | *p++ = '0' + label; | |
5950 | *p = '\0'; | |
ab835497 RK |
5951 | |
5952 | if (noop) | |
0b82d204 | 5953 | strcpy (p, "\n\tnop"); |
ab835497 RK |
5954 | |
5955 | return string; | |
5956 | } | |
5957 | ||
e48addee JJ |
5958 | /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. |
5959 | Such instructions cannot be used in the delay slot of return insn on v9. | |
5960 | If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. | |
5961 | */ | |
284d86e9 | 5962 | |
e48addee JJ |
5963 | static int |
5964 | epilogue_renumber (where, test) | |
5965 | register rtx *where; | |
5966 | int test; | |
284d86e9 | 5967 | { |
e48addee JJ |
5968 | register const char *fmt; |
5969 | register int i; | |
5970 | register enum rtx_code code; | |
5971 | ||
5972 | if (*where == 0) | |
5973 | return 0; | |
5974 | ||
5975 | code = GET_CODE (*where); | |
284d86e9 JC |
5976 | |
5977 | switch (code) | |
5978 | { | |
284d86e9 | 5979 | case REG: |
e48addee JJ |
5980 | if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ |
5981 | return 1; | |
5982 | if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) | |
5983 | *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); | |
5984 | case SCRATCH: | |
5985 | case CC0: | |
5986 | case PC: | |
284d86e9 JC |
5987 | case CONST_INT: |
5988 | case CONST_DOUBLE: | |
e48addee | 5989 | return 0; |
76a7c776 | 5990 | |
09ebda1b SC |
5991 | /* Do not replace the frame pointer with the stack pointer because |
5992 | it can cause the delayed instruction to load below the stack. | |
5993 | This occurs when instructions like: | |
5994 | ||
5995 | (set (reg/i:SI 24 %i0) | |
5996 | (mem/f:SI (plus:SI (reg/f:SI 30 %fp) | |
5997 | (const_int -20 [0xffffffec])) 0)) | |
5998 | ||
5999 | are in the return delayed slot. */ | |
6000 | case PLUS: | |
6001 | if (GET_CODE (XEXP (*where, 0)) == REG | |
563c12b0 | 6002 | && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM |
09ebda1b SC |
6003 | && (GET_CODE (XEXP (*where, 1)) != CONST_INT |
6004 | || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS)) | |
6005 | return 1; | |
6006 | break; | |
6007 | ||
6008 | case MEM: | |
6009 | if (SPARC_STACK_BIAS | |
6010 | && GET_CODE (XEXP (*where, 0)) == REG | |
563c12b0 | 6011 | && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM) |
09ebda1b SC |
6012 | return 1; |
6013 | break; | |
6014 | ||
76a7c776 DM |
6015 | default: |
6016 | break; | |
e48addee | 6017 | } |
284d86e9 | 6018 | |
e48addee | 6019 | fmt = GET_RTX_FORMAT (code); |
284d86e9 | 6020 | |
e48addee JJ |
6021 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
6022 | { | |
6023 | if (fmt[i] == 'E') | |
6024 | { | |
6025 | register int j; | |
6026 | for (j = XVECLEN (*where, i) - 1; j >= 0; j--) | |
6027 | if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) | |
6028 | return 1; | |
6029 | } | |
6030 | else if (fmt[i] == 'e' | |
6031 | && epilogue_renumber (&(XEXP (*where, i)), test)) | |
6032 | return 1; | |
284d86e9 | 6033 | } |
e48addee | 6034 | return 0; |
284d86e9 | 6035 | } |
ab835497 RK |
6036 | \f |
6037 | /* Leaf functions and non-leaf functions have different needs. */ | |
6038 | ||
8b60264b | 6039 | static const int |
ab835497 RK |
6040 | reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; |
6041 | ||
8b60264b | 6042 | static const int |
ab835497 RK |
6043 | reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; |
6044 | ||
8b60264b | 6045 | static const int *const reg_alloc_orders[] = { |
ab835497 RK |
6046 | reg_leaf_alloc_order, |
6047 | reg_nonleaf_alloc_order}; | |
6048 | ||
6049 | void | |
6050 | order_regs_for_local_alloc () | |
6051 | { | |
6052 | static int last_order_nonleaf = 1; | |
6053 | ||
6054 | if (regs_ever_live[15] != last_order_nonleaf) | |
6055 | { | |
6056 | last_order_nonleaf = !last_order_nonleaf; | |
2e09e75a | 6057 | memcpy ((char *) reg_alloc_order, |
8b60264b | 6058 | (const char *) reg_alloc_orders[last_order_nonleaf], |
2e09e75a | 6059 | FIRST_PSEUDO_REGISTER * sizeof (int)); |
ab835497 RK |
6060 | } |
6061 | } | |
6062 | \f | |
e0d80184 DM |
6063 | /* Return 1 if REG and MEM are legitimate enough to allow the various |
6064 | mem<-->reg splits to be run. */ | |
6065 | ||
6066 | int | |
e61c29e9 | 6067 | sparc_splitdi_legitimate (reg, mem) |
e0d80184 DM |
6068 | rtx reg; |
6069 | rtx mem; | |
6070 | { | |
e0d80184 DM |
6071 | /* Punt if we are here by mistake. */ |
6072 | if (! reload_completed) | |
9208e4b2 | 6073 | abort (); |
e0d80184 DM |
6074 | |
6075 | /* We must have an offsettable memory reference. */ | |
6076 | if (! offsettable_memref_p (mem)) | |
6077 | return 0; | |
6078 | ||
6079 | /* If we have legitimate args for ldd/std, we do not want | |
6080 | the split to happen. */ | |
6081 | if ((REGNO (reg) % 2) == 0 | |
6082 | && mem_min_alignment (mem, 8)) | |
6083 | return 0; | |
6084 | ||
6085 | /* Success. */ | |
6086 | return 1; | |
6087 | } | |
6088 | ||
e61c29e9 DM |
6089 | /* Return 1 if x and y are some kind of REG and they refer to |
6090 | different hard registers. This test is guarenteed to be | |
6091 | run after reload. */ | |
6092 | ||
6093 | int | |
6094 | sparc_absnegfloat_split_legitimate (x, y) | |
6095 | rtx x, y; | |
6096 | { | |
e61c29e9 DM |
6097 | if (GET_CODE (x) != REG) |
6098 | return 0; | |
e61c29e9 DM |
6099 | if (GET_CODE (y) != REG) |
6100 | return 0; | |
6101 | if (REGNO (x) == REGNO (y)) | |
6102 | return 0; | |
6103 | return 1; | |
6104 | } | |
6105 | ||
35016322 JW |
6106 | /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. |
6107 | This makes them candidates for using ldd and std insns. | |
6108 | ||
bfd6bc60 | 6109 | Note reg1 and reg2 *must* be hard registers. */ |
35016322 JW |
6110 | |
6111 | int | |
7c56249d | 6112 | registers_ok_for_ldd_peep (reg1, reg2) |
35016322 JW |
6113 | rtx reg1, reg2; |
6114 | { | |
35016322 JW |
6115 | /* We might have been passed a SUBREG. */ |
6116 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
6117 | return 0; | |
6118 | ||
35016322 JW |
6119 | if (REGNO (reg1) % 2 != 0) |
6120 | return 0; | |
6121 | ||
bfd6bc60 JC |
6122 | /* Integer ldd is deprecated in SPARC V9 */ |
6123 | if (TARGET_V9 && REGNO (reg1) < 32) | |
6124 | return 0; | |
6125 | ||
35016322 | 6126 | return (REGNO (reg1) == REGNO (reg2) - 1); |
35016322 JW |
6127 | } |
6128 | ||
2aad5d68 | 6129 | /* Return 1 if the addresses in mem1 and mem2 are suitable for use in |
303f8933 DN |
6130 | an ldd or std insn. |
6131 | ||
2aad5d68 DN |
6132 | This can only happen when addr1 and addr2, the addresses in mem1 |
6133 | and mem2, are consecutive memory locations (addr1 + 4 == addr2). | |
303f8933 DN |
6134 | addr1 must also be aligned on a 64-bit boundary. |
6135 | ||
6136 | Also iff dependent_reg_rtx is not null it should not be used to | |
6137 | compute the address for mem1, i.e. we cannot optimize a sequence | |
6138 | like: | |
6139 | ld [%o0], %o0 | |
6140 | ld [%o0 + 4], %o1 | |
6141 | to | |
bcdd764b | 6142 | ldd [%o0], %o0 |
0acf409f DM |
6143 | nor: |
6144 | ld [%g3 + 4], %g3 | |
6145 | ld [%g3], %g2 | |
6146 | to | |
6147 | ldd [%g3], %g2 | |
6148 | ||
6149 | But, note that the transformation from: | |
6150 | ld [%g2 + 4], %g3 | |
6151 | ld [%g2], %g2 | |
6152 | to | |
6153 | ldd [%g2], %g2 | |
6154 | is perfectly fine. Thus, the peephole2 patterns always pass us | |
6155 | the destination register of the first load, never the second one. | |
6156 | ||
303f8933 DN |
6157 | For stores we don't have a similar problem, so dependent_reg_rtx is |
6158 | NULL_RTX. */ | |
35016322 JW |
6159 | |
6160 | int | |
303f8933 DN |
6161 | mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx) |
6162 | rtx mem1, mem2, dependent_reg_rtx; | |
35016322 | 6163 | { |
2aad5d68 | 6164 | rtx addr1, addr2; |
0d587737 KG |
6165 | unsigned int reg1; |
6166 | int offset1; | |
35016322 | 6167 | |
303f8933 DN |
6168 | /* The mems cannot be volatile. */ |
6169 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
6170 | return 0; | |
2aad5d68 | 6171 | |
303f8933 | 6172 | /* MEM1 should be aligned on a 64-bit boundary. */ |
2aad5d68 DN |
6173 | if (MEM_ALIGN (mem1) < 64) |
6174 | return 0; | |
6175 | ||
303f8933 DN |
6176 | addr1 = XEXP (mem1, 0); |
6177 | addr2 = XEXP (mem2, 0); | |
6178 | ||
35016322 JW |
6179 | /* Extract a register number and offset (if used) from the first addr. */ |
6180 | if (GET_CODE (addr1) == PLUS) | |
6181 | { | |
6182 | /* If not a REG, return zero. */ | |
6183 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
6184 | return 0; | |
6185 | else | |
6186 | { | |
6187 | reg1 = REGNO (XEXP (addr1, 0)); | |
6188 | /* The offset must be constant! */ | |
6189 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
6190 | return 0; | |
6191 | offset1 = INTVAL (XEXP (addr1, 1)); | |
6192 | } | |
6193 | } | |
6194 | else if (GET_CODE (addr1) != REG) | |
6195 | return 0; | |
6196 | else | |
6197 | { | |
6198 | reg1 = REGNO (addr1); | |
6199 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
6200 | offset1 = 0; | |
6201 | } | |
6202 | ||
6203 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
6204 | if (GET_CODE (addr2) != PLUS) | |
6205 | return 0; | |
6206 | ||
6207 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
6208 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
6209 | return 0; | |
6210 | ||
35016322 JW |
6211 | if (reg1 != REGNO (XEXP (addr2, 0))) |
6212 | return 0; | |
6213 | ||
303f8933 DN |
6214 | if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx)) |
6215 | return 0; | |
6216 | ||
2296cba3 | 6217 | /* The first offset must be evenly divisible by 8 to ensure the |
35016322 JW |
6218 | address is 64 bit aligned. */ |
6219 | if (offset1 % 8 != 0) | |
6220 | return 0; | |
6221 | ||
6222 | /* The offset for the second addr must be 4 more than the first addr. */ | |
6223 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) | |
6224 | return 0; | |
6225 | ||
6226 | /* All the tests passed. addr1 and addr2 are valid for ldd and std | |
6227 | instructions. */ | |
6228 | return 1; | |
6229 | } | |
7c56249d JL |
6230 | |
6231 | /* Return 1 if reg is a pseudo, or is the first register in | |
6232 | a hard register pair. This makes it a candidate for use in | |
6233 | ldd and std insns. */ | |
6234 | ||
6235 | int | |
6236 | register_ok_for_ldd (reg) | |
6237 | rtx reg; | |
6238 | { | |
7c56249d JL |
6239 | /* We might have been passed a SUBREG. */ |
6240 | if (GET_CODE (reg) != REG) | |
6241 | return 0; | |
6242 | ||
6243 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
6244 | return (REGNO (reg) % 2 == 0); | |
6245 | else | |
6246 | return 1; | |
7c56249d | 6247 | } |
ab835497 | 6248 | \f |
ab835497 RK |
6249 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
6250 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
6251 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
6252 | ||
6253 | void | |
6254 | print_operand (file, x, code) | |
6255 | FILE *file; | |
6256 | rtx x; | |
6257 | int code; | |
6258 | { | |
6259 | switch (code) | |
6260 | { | |
6261 | case '#': | |
6262 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
6263 | if (dbr_sequence_length () == 0) | |
e0d80184 | 6264 | fputs ("\n\t nop", file); |
ab835497 RK |
6265 | return; |
6266 | case '*': | |
c6ce0969 JW |
6267 | /* Output an annul flag if there's nothing for the delay slot and we |
6268 | are optimizing. This is always used with '(' below. */ | |
6269 | /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; | |
6270 | this is a dbx bug. So, we only do this when optimizing. */ | |
bfd6bc60 JC |
6271 | /* On UltraSPARC, a branch in a delay slot causes a pipeline flush. |
6272 | Always emit a nop in case the next instruction is a branch. */ | |
6273 | if (dbr_sequence_length () == 0 | |
284d86e9 | 6274 | && (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
c6ce0969 JW |
6275 | fputs (",a", file); |
6276 | return; | |
6277 | case '(': | |
6278 | /* Output a 'nop' if there's nothing for the delay slot and we are | |
6279 | not optimizing. This is always used with '*' above. */ | |
bfd6bc60 | 6280 | if (dbr_sequence_length () == 0 |
284d86e9 | 6281 | && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
e0d80184 | 6282 | fputs ("\n\t nop", file); |
ab835497 | 6283 | return; |
61a55e8b | 6284 | case '_': |
a0a301fc DE |
6285 | /* Output the Embedded Medium/Anywhere code model base register. */ |
6286 | fputs (EMBMEDANY_BASE_REG, file); | |
61a55e8b DE |
6287 | return; |
6288 | case '@': | |
6289 | /* Print out what we are using as the frame pointer. This might | |
6290 | be %fp, or might be %sp+offset. */ | |
6291 | /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ | |
6292 | fprintf (file, "%s+%d", frame_base_name, frame_base_offset); | |
6293 | return; | |
ab835497 RK |
6294 | case 'Y': |
6295 | /* Adjust the operand to take into account a RESTORE operation. */ | |
bfd6bc60 JC |
6296 | if (GET_CODE (x) == CONST_INT) |
6297 | break; | |
6298 | else if (GET_CODE (x) != REG) | |
c725bd79 | 6299 | output_operand_lossage ("invalid %%Y operand"); |
b3b1e8bd | 6300 | else if (REGNO (x) < 8) |
ab835497 RK |
6301 | fputs (reg_names[REGNO (x)], file); |
6302 | else if (REGNO (x) >= 24 && REGNO (x) < 32) | |
6303 | fputs (reg_names[REGNO (x)-16], file); | |
6304 | else | |
c725bd79 | 6305 | output_operand_lossage ("invalid %%Y operand"); |
ab835497 | 6306 | return; |
0f39a9aa DE |
6307 | case 'L': |
6308 | /* Print out the low order register name of a register pair. */ | |
6309 | if (WORDS_BIG_ENDIAN) | |
6310 | fputs (reg_names[REGNO (x)+1], file); | |
6311 | else | |
6312 | fputs (reg_names[REGNO (x)], file); | |
6313 | return; | |
6314 | case 'H': | |
6315 | /* Print out the high order register name of a register pair. */ | |
6316 | if (WORDS_BIG_ENDIAN) | |
6317 | fputs (reg_names[REGNO (x)], file); | |
6318 | else | |
6319 | fputs (reg_names[REGNO (x)+1], file); | |
6320 | return; | |
ab835497 | 6321 | case 'R': |
795068a4 | 6322 | /* Print out the second register name of a register pair or quad. |
ab835497 RK |
6323 | I.e., R (%o0) => %o1. */ |
6324 | fputs (reg_names[REGNO (x)+1], file); | |
6325 | return; | |
795068a4 JW |
6326 | case 'S': |
6327 | /* Print out the third register name of a register quad. | |
6328 | I.e., S (%o0) => %o2. */ | |
6329 | fputs (reg_names[REGNO (x)+2], file); | |
6330 | return; | |
6331 | case 'T': | |
6332 | /* Print out the fourth register name of a register quad. | |
6333 | I.e., T (%o0) => %o3. */ | |
6334 | fputs (reg_names[REGNO (x)+3], file); | |
6335 | return; | |
304b7a23 DE |
6336 | case 'x': |
6337 | /* Print a condition code register. */ | |
6338 | if (REGNO (x) == SPARC_ICC_REG) | |
6339 | { | |
6340 | /* We don't handle CC[X]_NOOVmode because they're not supposed | |
6341 | to occur here. */ | |
6342 | if (GET_MODE (x) == CCmode) | |
6343 | fputs ("%icc", file); | |
6344 | else if (GET_MODE (x) == CCXmode) | |
6345 | fputs ("%xcc", file); | |
6346 | else | |
6347 | abort (); | |
6348 | } | |
6349 | else | |
6350 | /* %fccN register */ | |
6351 | fputs (reg_names[REGNO (x)], file); | |
6352 | return; | |
ab835497 RK |
6353 | case 'm': |
6354 | /* Print the operand's address only. */ | |
6355 | output_address (XEXP (x, 0)); | |
6356 | return; | |
6357 | case 'r': | |
6358 | /* In this case we need a register. Use %g0 if the | |
77a02b01 | 6359 | operand is const0_rtx. */ |
76052e74 RS |
6360 | if (x == const0_rtx |
6361 | || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) | |
ab835497 RK |
6362 | { |
6363 | fputs ("%g0", file); | |
6364 | return; | |
6365 | } | |
6366 | else | |
6367 | break; | |
6368 | ||
61a55e8b | 6369 | case 'A': |
ab835497 RK |
6370 | switch (GET_CODE (x)) |
6371 | { | |
6372 | case IOR: fputs ("or", file); break; | |
6373 | case AND: fputs ("and", file); break; | |
6374 | case XOR: fputs ("xor", file); break; | |
c725bd79 | 6375 | default: output_operand_lossage ("invalid %%A operand"); |
ab835497 RK |
6376 | } |
6377 | return; | |
6378 | ||
6379 | case 'B': | |
6380 | switch (GET_CODE (x)) | |
6381 | { | |
6382 | case IOR: fputs ("orn", file); break; | |
6383 | case AND: fputs ("andn", file); break; | |
6384 | case XOR: fputs ("xnor", file); break; | |
c725bd79 | 6385 | default: output_operand_lossage ("invalid %%B operand"); |
ab835497 RK |
6386 | } |
6387 | return; | |
6388 | ||
304b7a23 DE |
6389 | /* These are used by the conditional move instructions. */ |
6390 | case 'c' : | |
61a55e8b | 6391 | case 'C': |
304b7a23 | 6392 | { |
5c5c34a4 JJ |
6393 | enum rtx_code rc = GET_CODE (x); |
6394 | ||
6395 | if (code == 'c') | |
6396 | { | |
6397 | enum machine_mode mode = GET_MODE (XEXP (x, 0)); | |
6398 | if (mode == CCFPmode || mode == CCFPEmode) | |
6399 | rc = reverse_condition_maybe_unordered (GET_CODE (x)); | |
6400 | else | |
6401 | rc = reverse_condition (GET_CODE (x)); | |
6402 | } | |
304b7a23 DE |
6403 | switch (rc) |
6404 | { | |
6405 | case NE: fputs ("ne", file); break; | |
6406 | case EQ: fputs ("e", file); break; | |
6407 | case GE: fputs ("ge", file); break; | |
6408 | case GT: fputs ("g", file); break; | |
6409 | case LE: fputs ("le", file); break; | |
6410 | case LT: fputs ("l", file); break; | |
6411 | case GEU: fputs ("geu", file); break; | |
6412 | case GTU: fputs ("gu", file); break; | |
6413 | case LEU: fputs ("leu", file); break; | |
6414 | case LTU: fputs ("lu", file); break; | |
5c5c34a4 JJ |
6415 | case LTGT: fputs ("lg", file); break; |
6416 | case UNORDERED: fputs ("u", file); break; | |
6417 | case ORDERED: fputs ("o", file); break; | |
6418 | case UNLT: fputs ("ul", file); break; | |
6419 | case UNLE: fputs ("ule", file); break; | |
6420 | case UNGT: fputs ("ug", file); break; | |
6421 | case UNGE: fputs ("uge", file); break; | |
6422 | case UNEQ: fputs ("ue", file); break; | |
304b7a23 | 6423 | default: output_operand_lossage (code == 'c' |
c725bd79 NB |
6424 | ? "invalid %%c operand" |
6425 | : "invalid %%C operand"); | |
304b7a23 DE |
6426 | } |
6427 | return; | |
6428 | } | |
6429 | ||
6430 | /* These are used by the movr instruction pattern. */ | |
6431 | case 'd': | |
61a55e8b | 6432 | case 'D': |
304b7a23 DE |
6433 | { |
6434 | enum rtx_code rc = (code == 'd' | |
6435 | ? reverse_condition (GET_CODE (x)) | |
6436 | : GET_CODE (x)); | |
6437 | switch (rc) | |
6438 | { | |
6439 | case NE: fputs ("ne", file); break; | |
6440 | case EQ: fputs ("e", file); break; | |
6441 | case GE: fputs ("gez", file); break; | |
6442 | case LT: fputs ("lz", file); break; | |
6443 | case LE: fputs ("lez", file); break; | |
6444 | case GT: fputs ("gz", file); break; | |
6445 | default: output_operand_lossage (code == 'd' | |
c725bd79 NB |
6446 | ? "invalid %%d operand" |
6447 | : "invalid %%D operand"); | |
304b7a23 DE |
6448 | } |
6449 | return; | |
6450 | } | |
61a55e8b | 6451 | |
ab835497 RK |
6452 | case 'b': |
6453 | { | |
6454 | /* Print a sign-extended character. */ | |
9e0625a3 | 6455 | int i = trunc_int_for_mode (INTVAL (x), QImode); |
ab835497 RK |
6456 | fprintf (file, "%d", i); |
6457 | return; | |
6458 | } | |
6459 | ||
d2889939 RK |
6460 | case 'f': |
6461 | /* Operand must be a MEM; write its address. */ | |
6462 | if (GET_CODE (x) != MEM) | |
c725bd79 | 6463 | output_operand_lossage ("invalid %%f operand"); |
d2889939 RK |
6464 | output_address (XEXP (x, 0)); |
6465 | return; | |
6466 | ||
ab835497 RK |
6467 | case 0: |
6468 | /* Do nothing special. */ | |
6469 | break; | |
6470 | ||
6471 | default: | |
6472 | /* Undocumented flag. */ | |
415f583e | 6473 | output_operand_lossage ("invalid operand output code"); |
ab835497 RK |
6474 | } |
6475 | ||
6476 | if (GET_CODE (x) == REG) | |
6477 | fputs (reg_names[REGNO (x)], file); | |
6478 | else if (GET_CODE (x) == MEM) | |
6479 | { | |
6480 | fputc ('[', file); | |
ab835497 | 6481 | /* Poor Sun assembler doesn't understand absolute addressing. */ |
e6c1be7e | 6482 | if (CONSTANT_P (XEXP (x, 0))) |
ab835497 RK |
6483 | fputs ("%g0+", file); |
6484 | output_address (XEXP (x, 0)); | |
6485 | fputc (']', file); | |
6486 | } | |
6487 | else if (GET_CODE (x) == HIGH) | |
6488 | { | |
6489 | fputs ("%hi(", file); | |
6490 | output_addr_const (file, XEXP (x, 0)); | |
6491 | fputc (')', file); | |
6492 | } | |
6493 | else if (GET_CODE (x) == LO_SUM) | |
6494 | { | |
6495 | print_operand (file, XEXP (x, 0), 0); | |
e0d80184 DM |
6496 | if (TARGET_CM_MEDMID) |
6497 | fputs ("+%l44(", file); | |
6498 | else | |
6499 | fputs ("+%lo(", file); | |
ab835497 RK |
6500 | output_addr_const (file, XEXP (x, 1)); |
6501 | fputc (')', file); | |
6502 | } | |
e601abce JW |
6503 | else if (GET_CODE (x) == CONST_DOUBLE |
6504 | && (GET_MODE (x) == VOIDmode | |
6505 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) | |
ab835497 RK |
6506 | { |
6507 | if (CONST_DOUBLE_HIGH (x) == 0) | |
0d9484c5 | 6508 | fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x)); |
ab835497 RK |
6509 | else if (CONST_DOUBLE_HIGH (x) == -1 |
6510 | && CONST_DOUBLE_LOW (x) < 0) | |
0d9484c5 | 6511 | fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x)); |
ab835497 | 6512 | else |
e601abce | 6513 | output_operand_lossage ("long long constant not a valid immediate operand"); |
ab835497 | 6514 | } |
e601abce JW |
6515 | else if (GET_CODE (x) == CONST_DOUBLE) |
6516 | output_operand_lossage ("floating point constant not a valid immediate operand"); | |
ab835497 RK |
6517 | else { output_addr_const (file, x); } |
6518 | } | |
6519 | \f | |
301d03af RS |
6520 | /* Target hook for assembling integer objects. The sparc version has |
6521 | special handling for aligned DI-mode objects. */ | |
ab835497 | 6522 | |
301d03af RS |
6523 | static bool |
6524 | sparc_assemble_integer (x, size, aligned_p) | |
6525 | rtx x; | |
6526 | unsigned int size; | |
6527 | int aligned_p; | |
ab835497 | 6528 | { |
301d03af RS |
6529 | /* ??? We only output .xword's for symbols and only then in environments |
6530 | where the assembler can handle them. */ | |
6531 | if (aligned_p && size == 8 | |
6532 | && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE)) | |
ab835497 | 6533 | { |
301d03af | 6534 | if (TARGET_V9) |
61a55e8b | 6535 | { |
301d03af RS |
6536 | assemble_integer_with_op ("\t.xword\t", x); |
6537 | return true; | |
61a55e8b DE |
6538 | } |
6539 | else | |
6540 | { | |
301d03af RS |
6541 | assemble_aligned_integer (4, const0_rtx); |
6542 | assemble_aligned_integer (4, x); | |
6543 | return true; | |
61a55e8b | 6544 | } |
ab835497 | 6545 | } |
301d03af | 6546 | return default_assemble_integer (x, size, aligned_p); |
ab835497 | 6547 | } |
210aa14a | 6548 | \f |
b0468b84 RK |
6549 | /* Return the value of a code used in the .proc pseudo-op that says |
6550 | what kind of result this function returns. For non-C types, we pick | |
6551 | the closest C type. */ | |
6552 | ||
77a02b01 JW |
6553 | #ifndef SHORT_TYPE_SIZE |
6554 | #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) | |
6555 | #endif | |
6556 | ||
6557 | #ifndef INT_TYPE_SIZE | |
6558 | #define INT_TYPE_SIZE BITS_PER_WORD | |
6559 | #endif | |
6560 | ||
6561 | #ifndef LONG_TYPE_SIZE | |
6562 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
6563 | #endif | |
6564 | ||
6565 | #ifndef LONG_LONG_TYPE_SIZE | |
6566 | #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) | |
6567 | #endif | |
6568 | ||
6569 | #ifndef FLOAT_TYPE_SIZE | |
6570 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
6571 | #endif | |
6572 | ||
6573 | #ifndef DOUBLE_TYPE_SIZE | |
6574 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
6575 | #endif | |
6576 | ||
6577 | #ifndef LONG_DOUBLE_TYPE_SIZE | |
6578 | #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
6579 | #endif | |
210aa14a RS |
6580 | |
6581 | unsigned long | |
6582 | sparc_type_code (type) | |
6583 | register tree type; | |
6584 | { | |
6585 | register unsigned long qualifiers = 0; | |
e5e809f4 | 6586 | register unsigned shift; |
210aa14a | 6587 | |
abc95ed3 | 6588 | /* Only the first 30 bits of the qualifier are valid. We must refrain from |
aee2c3c5 JW |
6589 | setting more, since some assemblers will give an error for this. Also, |
6590 | we must be careful to avoid shifts of 32 bits or more to avoid getting | |
6591 | unpredictable results. */ | |
6592 | ||
e5e809f4 | 6593 | for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) |
210aa14a RS |
6594 | { |
6595 | switch (TREE_CODE (type)) | |
6596 | { | |
6597 | case ERROR_MARK: | |
6598 | return qualifiers; | |
6599 | ||
6600 | case ARRAY_TYPE: | |
e5e809f4 | 6601 | qualifiers |= (3 << shift); |
210aa14a RS |
6602 | break; |
6603 | ||
6604 | case FUNCTION_TYPE: | |
6605 | case METHOD_TYPE: | |
e5e809f4 | 6606 | qualifiers |= (2 << shift); |
210aa14a RS |
6607 | break; |
6608 | ||
6609 | case POINTER_TYPE: | |
6610 | case REFERENCE_TYPE: | |
6611 | case OFFSET_TYPE: | |
e5e809f4 | 6612 | qualifiers |= (1 << shift); |
210aa14a | 6613 | break; |
ab835497 | 6614 | |
210aa14a RS |
6615 | case RECORD_TYPE: |
6616 | return (qualifiers | 8); | |
6617 | ||
6618 | case UNION_TYPE: | |
b0468b84 | 6619 | case QUAL_UNION_TYPE: |
210aa14a RS |
6620 | return (qualifiers | 9); |
6621 | ||
6622 | case ENUMERAL_TYPE: | |
6623 | return (qualifiers | 10); | |
6624 | ||
6625 | case VOID_TYPE: | |
6626 | return (qualifiers | 16); | |
6627 | ||
6628 | case INTEGER_TYPE: | |
654209e6 JW |
6629 | /* If this is a range type, consider it to be the underlying |
6630 | type. */ | |
6631 | if (TREE_TYPE (type) != 0) | |
e5e809f4 | 6632 | break; |
654209e6 | 6633 | |
77a02b01 | 6634 | /* Carefully distinguish all the standard types of C, |
b0468b84 RK |
6635 | without messing up if the language is not C. We do this by |
6636 | testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to | |
6637 | look at both the names and the above fields, but that's redundant. | |
6638 | Any type whose size is between two C types will be considered | |
6639 | to be the wider of the two types. Also, we do not have a | |
6640 | special code to use for "long long", so anything wider than | |
6641 | long is treated the same. Note that we can't distinguish | |
6642 | between "int" and "long" in this code if they are the same | |
6643 | size, but that's fine, since neither can the assembler. */ | |
6644 | ||
6645 | if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) | |
6646 | return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); | |
77a02b01 | 6647 | |
b0468b84 RK |
6648 | else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) |
6649 | return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); | |
77a02b01 | 6650 | |
b0468b84 | 6651 | else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) |
77a02b01 JW |
6652 | return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); |
6653 | ||
b0468b84 | 6654 | else |
77a02b01 JW |
6655 | return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); |
6656 | ||
210aa14a | 6657 | case REAL_TYPE: |
e5e809f4 JL |
6658 | /* If this is a range type, consider it to be the underlying |
6659 | type. */ | |
6660 | if (TREE_TYPE (type) != 0) | |
6661 | break; | |
6662 | ||
77a02b01 JW |
6663 | /* Carefully distinguish all the standard types of C, |
6664 | without messing up if the language is not C. */ | |
b0468b84 | 6665 | |
77a02b01 | 6666 | if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) |
210aa14a | 6667 | return (qualifiers | 6); |
b0468b84 RK |
6668 | |
6669 | else | |
6670 | return (qualifiers | 7); | |
210aa14a RS |
6671 | |
6672 | case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ | |
13d39dbc | 6673 | /* ??? We need to distinguish between double and float complex types, |
c82aa69a JW |
6674 | but I don't know how yet because I can't reach this code from |
6675 | existing front-ends. */ | |
6676 | return (qualifiers | 7); /* Who knows? */ | |
6677 | ||
210aa14a RS |
6678 | case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ |
6679 | case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ | |
6680 | case FILE_TYPE: /* GNU Pascal FILE type. */ | |
26902ae0 | 6681 | case SET_TYPE: /* GNU Pascal SET type. */ |
210aa14a | 6682 | case LANG_TYPE: /* ? */ |
26902ae0 | 6683 | return qualifiers; |
210aa14a RS |
6684 | |
6685 | default: | |
6686 | abort (); /* Not a type! */ | |
6687 | } | |
6688 | } | |
e5e809f4 JL |
6689 | |
6690 | return qualifiers; | |
210aa14a | 6691 | } |
ead69aea | 6692 | \f |
61a55e8b DE |
6693 | /* Nested function support. */ |
6694 | ||
6695 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
6696 | FNADDR is an RTX for the address of the function's pure code. | |
6697 | CXT is an RTX for the static chain value for the function. | |
6698 | ||
6699 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
6700 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
6701 | (to store insns). This is a bit excessive. Perhaps a different | |
6702 | mechanism would be better here. | |
6703 | ||
849a528d | 6704 | Emit enough FLUSH insns to synchronize the data and instruction caches. */ |
61a55e8b DE |
6705 | |
6706 | void | |
6707 | sparc_initialize_trampoline (tramp, fnaddr, cxt) | |
6708 | rtx tramp, fnaddr, cxt; | |
6709 | { | |
c6b0465b JC |
6710 | /* SPARC 32 bit trampoline: |
6711 | ||
e0d80184 DM |
6712 | sethi %hi(fn), %g1 |
6713 | sethi %hi(static), %g2 | |
6714 | jmp %g1+%lo(fn) | |
6715 | or %g2, %lo(static), %g2 | |
c6b0465b JC |
6716 | |
6717 | SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii | |
6718 | JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii | |
6719 | */ | |
959eb758 DM |
6720 | #ifdef TRANSFER_FROM_TRAMPOLINE |
6721 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
eb29ddb6 | 6722 | LCT_NORMAL, VOIDmode, 1, tramp, Pmode); |
959eb758 | 6723 | #endif |
c6b0465b | 6724 | |
35aa3c1c RK |
6725 | emit_move_insn |
6726 | (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), | |
6727 | expand_binop (SImode, ior_optab, | |
6728 | expand_shift (RSHIFT_EXPR, SImode, fnaddr, | |
6729 | size_int (10), 0, 1), | |
6730 | GEN_INT (trunc_int_for_mode (0x03000000, SImode)), | |
6731 | NULL_RTX, 1, OPTAB_DIRECT)); | |
6732 | ||
6733 | emit_move_insn | |
6734 | (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), | |
6735 | expand_binop (SImode, ior_optab, | |
6736 | expand_shift (RSHIFT_EXPR, SImode, cxt, | |
6737 | size_int (10), 0, 1), | |
6738 | GEN_INT (trunc_int_for_mode (0x05000000, SImode)), | |
6739 | NULL_RTX, 1, OPTAB_DIRECT)); | |
6740 | ||
6741 | emit_move_insn | |
6742 | (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), | |
6743 | expand_binop (SImode, ior_optab, | |
6744 | expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX), | |
6745 | GEN_INT (trunc_int_for_mode (0x81c06000, SImode)), | |
6746 | NULL_RTX, 1, OPTAB_DIRECT)); | |
6747 | ||
6748 | emit_move_insn | |
6749 | (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), | |
6750 | expand_binop (SImode, ior_optab, | |
6751 | expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX), | |
6752 | GEN_INT (trunc_int_for_mode (0x8410a000, SImode)), | |
6753 | NULL_RTX, 1, OPTAB_DIRECT)); | |
c6b0465b | 6754 | |
c6b0465b JC |
6755 | /* On UltraSPARC a flush flushes an entire cache line. The trampoline is |
6756 | aligned on a 16 byte boundary so one flush clears it all. */ | |
35aa3c1c | 6757 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); |
84643cbf DM |
6758 | if (sparc_cpu != PROCESSOR_ULTRASPARC |
6759 | && sparc_cpu != PROCESSOR_ULTRASPARC3) | |
c6b0465b JC |
6760 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, |
6761 | plus_constant (tramp, 8))))); | |
61a55e8b DE |
6762 | } |
6763 | ||
849a528d RK |
6764 | /* The 64 bit version is simpler because it makes more sense to load the |
6765 | values as "immediate" data out of the trampoline. It's also easier since | |
6766 | we can read the PC without clobbering a register. */ | |
6767 | ||
61a55e8b DE |
6768 | void |
6769 | sparc64_initialize_trampoline (tramp, fnaddr, cxt) | |
6770 | rtx tramp, fnaddr, cxt; | |
6771 | { | |
345a6161 DM |
6772 | #ifdef TRANSFER_FROM_TRAMPOLINE |
6773 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
eb29ddb6 | 6774 | LCT_NORMAL, VOIDmode, 1, tramp, Pmode); |
345a6161 DM |
6775 | #endif |
6776 | ||
c6b0465b | 6777 | /* |
e0d80184 DM |
6778 | rd %pc, %g1 |
6779 | ldx [%g1+24], %g5 | |
6780 | jmp %g5 | |
6781 | ldx [%g1+16], %g5 | |
c6b0465b JC |
6782 | +16 bytes data |
6783 | */ | |
6784 | ||
6785 | emit_move_insn (gen_rtx_MEM (SImode, tramp), | |
e3aaacf4 | 6786 | GEN_INT (trunc_int_for_mode (0x83414000, SImode))); |
c6b0465b | 6787 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), |
e3aaacf4 | 6788 | GEN_INT (trunc_int_for_mode (0xca586018, SImode))); |
c6b0465b | 6789 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), |
e3aaacf4 | 6790 | GEN_INT (trunc_int_for_mode (0x81c14000, SImode))); |
c6b0465b | 6791 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), |
e3aaacf4 | 6792 | GEN_INT (trunc_int_for_mode (0xca586010, SImode))); |
c6b0465b | 6793 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); |
345a6161 | 6794 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); |
d4203cb4 | 6795 | emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp)))); |
345a6161 | 6796 | |
fae15c93 VM |
6797 | if (sparc_cpu != PROCESSOR_ULTRASPARC |
6798 | && sparc_cpu != PROCESSOR_ULTRASPARC3) | |
d4203cb4 | 6799 | emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); |
61a55e8b DE |
6800 | } |
6801 | \f | |
c819be5b JW |
6802 | /* Subroutines to support a flat (single) register window calling |
6803 | convention. */ | |
6804 | ||
6805 | /* Single-register window sparc stack frames look like: | |
6806 | ||
6807 | Before call After call | |
6808 | +-----------------------+ +-----------------------+ | |
86735b02 DE |
6809 | high | | | | |
6810 | mem | caller's temps. | | caller's temps. | | |
c819be5b JW |
6811 | | | | | |
6812 | +-----------------------+ +-----------------------+ | |
6813 | | | | | | |
6814 | | arguments on stack. | | arguments on stack. | | |
86735b02 DE |
6815 | | | | | |
6816 | +-----------------------+FP+92->+-----------------------+ | |
c819be5b JW |
6817 | | 6 words to save | | 6 words to save | |
6818 | | arguments passed | | arguments passed | | |
6819 | | in registers, even | | in registers, even | | |
86735b02 DE |
6820 | | if not passed. | | if not passed. | |
6821 | SP+68->+-----------------------+FP+68->+-----------------------+ | |
6822 | | 1 word struct addr | | 1 word struct addr | | |
6823 | +-----------------------+FP+64->+-----------------------+ | |
6824 | | | | | | |
6825 | | 16 word reg save area | | 16 word reg save area | | |
6826 | | | | | | |
6827 | SP->+-----------------------+ FP->+-----------------------+ | |
6828 | | 4 word area for | | |
6829 | | fp/alu reg moves | | |
6830 | FP-16->+-----------------------+ | |
6831 | | | | |
6832 | | local variables | | |
6833 | | | | |
6834 | +-----------------------+ | |
6835 | | | | |
c819be5b | 6836 | | fp register save | |
86735b02 DE |
6837 | | | |
6838 | +-----------------------+ | |
6839 | | | | |
c819be5b JW |
6840 | | gp register save | |
6841 | | | | |
86735b02 DE |
6842 | +-----------------------+ |
6843 | | | | |
c819be5b | 6844 | | alloca allocations | |
86735b02 DE |
6845 | | | |
6846 | +-----------------------+ | |
6847 | | | | |
c819be5b | 6848 | | arguments on stack | |
86735b02 DE |
6849 | | | |
6850 | SP+92->+-----------------------+ | |
c819be5b | 6851 | | 6 words to save | |
86735b02 | 6852 | | arguments passed | |
c819be5b | 6853 | | in registers, even | |
86735b02 DE |
6854 | low | if not passed. | |
6855 | memory SP+68->+-----------------------+ | |
6856 | | 1 word struct addr | | |
6857 | SP+64->+-----------------------+ | |
6858 | | | | |
6859 | I 16 word reg save area | | |
6860 | | | | |
6861 | SP->+-----------------------+ */ | |
c819be5b | 6862 | |
c6aa9ce1 | 6863 | /* Structure to be filled in by sparc_flat_compute_frame_size with register |
c819be5b JW |
6864 | save masks, and offsets for the current function. */ |
6865 | ||
6866 | struct sparc_frame_info | |
6867 | { | |
6868 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
6869 | unsigned long var_size; /* # bytes that variables take up. */ | |
6870 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
6871 | unsigned long extra_size; /* # bytes of extra gunk. */ | |
6872 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
6873 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 6874 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 6875 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 | 6876 | unsigned long reg_offset; /* Offset from new sp to store regs. */ |
c819be5b JW |
6877 | int initialized; /* Nonzero if frame size already calculated. */ |
6878 | }; | |
6879 | ||
c6aa9ce1 | 6880 | /* Current frame information calculated by sparc_flat_compute_frame_size. */ |
c819be5b JW |
6881 | struct sparc_frame_info current_frame_info; |
6882 | ||
6883 | /* Zero structure to initialize current_frame_info. */ | |
6884 | struct sparc_frame_info zero_frame_info; | |
6885 | ||
6886 | /* Tell prologue and epilogue if register REGNO should be saved / restored. */ | |
6887 | ||
86735b02 | 6888 | #define RETURN_ADDR_REGNUM 15 |
563c12b0 | 6889 | #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM)) |
86735b02 DE |
6890 | #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) |
6891 | ||
c819be5b | 6892 | #define MUST_SAVE_REGISTER(regno) \ |
563c12b0 RH |
6893 | ((regs_ever_live[regno] && !call_used_regs[regno]) \ |
6894 | || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \ | |
86735b02 | 6895 | || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM])) |
c819be5b JW |
6896 | |
6897 | /* Return the bytes needed to compute the frame pointer from the current | |
6898 | stack pointer. */ | |
6899 | ||
6900 | unsigned long | |
c6aa9ce1 | 6901 | sparc_flat_compute_frame_size (size) |
c819be5b JW |
6902 | int size; /* # of var. bytes allocated. */ |
6903 | { | |
6904 | int regno; | |
6905 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
6906 | unsigned long var_size; /* # bytes that variables take up. */ | |
6907 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
6908 | unsigned long extra_size; /* # extra bytes. */ | |
6909 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
6910 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 6911 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 6912 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 DE |
6913 | unsigned long reg_offset; /* Offset to register save area. */ |
6914 | int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ | |
c819be5b JW |
6915 | |
6916 | /* This is the size of the 16 word reg save area, 1 word struct addr | |
6917 | area, and 4 word fp/alu register copy area. */ | |
8c64be75 SC |
6918 | extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); |
6919 | var_size = size; | |
6920 | gp_reg_size = 0; | |
6921 | fp_reg_size = 0; | |
6922 | gmask = 0; | |
6923 | fmask = 0; | |
6924 | reg_offset = 0; | |
86735b02 | 6925 | need_aligned_p = 0; |
c819be5b | 6926 | |
8c64be75 SC |
6927 | args_size = 0; |
6928 | if (!leaf_function_p ()) | |
6929 | { | |
6930 | /* Also include the size needed for the 6 parameter registers. */ | |
6931 | args_size = current_function_outgoing_args_size + 24; | |
6932 | } | |
6933 | total_size = var_size + args_size; | |
6934 | ||
c819be5b JW |
6935 | /* Calculate space needed for gp registers. */ |
6936 | for (regno = 1; regno <= 31; regno++) | |
6937 | { | |
6938 | if (MUST_SAVE_REGISTER (regno)) | |
6939 | { | |
86735b02 DE |
6940 | /* If we need to save two regs in a row, ensure there's room to bump |
6941 | up the address to align it to a doubleword boundary. */ | |
c819be5b JW |
6942 | if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) |
6943 | { | |
6944 | if (gp_reg_size % 8 != 0) | |
86735b02 | 6945 | gp_reg_size += 4; |
c819be5b | 6946 | gp_reg_size += 2 * UNITS_PER_WORD; |
86735b02 | 6947 | gmask |= 3 << regno; |
c819be5b | 6948 | regno++; |
86735b02 | 6949 | need_aligned_p = 1; |
c819be5b JW |
6950 | } |
6951 | else | |
6952 | { | |
6953 | gp_reg_size += UNITS_PER_WORD; | |
86735b02 | 6954 | gmask |= 1 << regno; |
c819be5b JW |
6955 | } |
6956 | } | |
6957 | } | |
c819be5b JW |
6958 | |
6959 | /* Calculate space needed for fp registers. */ | |
6960 | for (regno = 32; regno <= 63; regno++) | |
6961 | { | |
6962 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
6963 | { | |
6964 | fp_reg_size += UNITS_PER_WORD; | |
6965 | fmask |= 1 << (regno - 32); | |
6966 | } | |
6967 | } | |
6968 | ||
86735b02 DE |
6969 | if (gmask || fmask) |
6970 | { | |
6971 | int n; | |
6972 | reg_offset = FIRST_PARM_OFFSET(0) + args_size; | |
6973 | /* Ensure save area is 8 byte aligned if we need it. */ | |
6974 | n = reg_offset % 8; | |
6975 | if (need_aligned_p && n != 0) | |
6976 | { | |
6977 | total_size += 8 - n; | |
6978 | reg_offset += 8 - n; | |
6979 | } | |
6980 | total_size += gp_reg_size + fp_reg_size; | |
6981 | } | |
c819be5b | 6982 | |
8c64be75 SC |
6983 | /* If we must allocate a stack frame at all, we must also allocate |
6984 | room for register window spillage, so as to be binary compatible | |
6985 | with libraries and operating systems that do not use -mflat. */ | |
6986 | if (total_size > 0) | |
6987 | total_size += extra_size; | |
6988 | else | |
6989 | extra_size = 0; | |
c819be5b JW |
6990 | |
6991 | total_size = SPARC_STACK_ALIGN (total_size); | |
6992 | ||
6993 | /* Save other computed information. */ | |
6994 | current_frame_info.total_size = total_size; | |
6995 | current_frame_info.var_size = var_size; | |
6996 | current_frame_info.args_size = args_size; | |
6997 | current_frame_info.extra_size = extra_size; | |
6998 | current_frame_info.gp_reg_size = gp_reg_size; | |
6999 | current_frame_info.fp_reg_size = fp_reg_size; | |
86735b02 | 7000 | current_frame_info.gmask = gmask; |
c819be5b | 7001 | current_frame_info.fmask = fmask; |
86735b02 | 7002 | current_frame_info.reg_offset = reg_offset; |
c819be5b JW |
7003 | current_frame_info.initialized = reload_completed; |
7004 | ||
c819be5b JW |
7005 | /* Ok, we're done. */ |
7006 | return total_size; | |
7007 | } | |
7008 | \f | |
86735b02 DE |
7009 | /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset |
7010 | OFFSET. | |
7011 | ||
7012 | BASE_REG must be 8 byte aligned. This allows us to test OFFSET for | |
7013 | appropriate alignment and use DOUBLEWORD_OP when we can. We assume | |
7014 | [BASE_REG+OFFSET] will always be a valid address. | |
7015 | ||
7016 | WORD_OP is either "st" for save, "ld" for restore. | |
7017 | DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ | |
c819be5b JW |
7018 | |
7019 | void | |
96987e96 DE |
7020 | sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op, |
7021 | doubleword_op, base_offset) | |
86735b02 | 7022 | FILE *file; |
b1474bb7 | 7023 | const char *base_reg; |
86735b02 DE |
7024 | unsigned int offset; |
7025 | unsigned long gmask; | |
7026 | unsigned long fmask; | |
b1474bb7 KG |
7027 | const char *word_op; |
7028 | const char *doubleword_op; | |
c53aa195 | 7029 | unsigned long base_offset; |
c819be5b JW |
7030 | { |
7031 | int regno; | |
c819be5b | 7032 | |
86735b02 DE |
7033 | if (gmask == 0 && fmask == 0) |
7034 | return; | |
c819be5b | 7035 | |
86735b02 DE |
7036 | /* Save registers starting from high to low. We've already saved the |
7037 | previous frame pointer and previous return address for the debugger's | |
7038 | sake. The debugger allows us to not need a nop in the epilog if at least | |
7039 | one register is reloaded in addition to return address. */ | |
c819be5b | 7040 | |
86735b02 | 7041 | if (gmask) |
c819be5b JW |
7042 | { |
7043 | for (regno = 1; regno <= 31; regno++) | |
7044 | { | |
86735b02 | 7045 | if ((gmask & (1L << regno)) != 0) |
c819be5b | 7046 | { |
86735b02 | 7047 | if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) |
c819be5b | 7048 | { |
86735b02 DE |
7049 | /* We can save two registers in a row. If we're not at a |
7050 | double word boundary, move to one. | |
7051 | sparc_flat_compute_frame_size ensures there's room to do | |
7052 | this. */ | |
7053 | if (offset % 8 != 0) | |
7054 | offset += UNITS_PER_WORD; | |
7055 | ||
c819be5b | 7056 | if (word_op[0] == 's') |
c53aa195 | 7057 | { |
e0d80184 | 7058 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
7059 | doubleword_op, reg_names[regno], |
7060 | base_reg, offset); | |
0021b564 | 7061 | if (dwarf2out_do_frame ()) |
c53aa195 | 7062 | { |
96987e96 | 7063 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
7064 | dwarf2out_reg_save (l, regno, offset + base_offset); |
7065 | dwarf2out_reg_save | |
7066 | (l, regno+1, offset+base_offset + UNITS_PER_WORD); | |
7067 | } | |
c53aa195 | 7068 | } |
c819be5b | 7069 | else |
e0d80184 | 7070 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 7071 | doubleword_op, base_reg, offset, |
c819be5b JW |
7072 | reg_names[regno]); |
7073 | ||
86735b02 | 7074 | offset += 2 * UNITS_PER_WORD; |
c819be5b JW |
7075 | regno++; |
7076 | } | |
7077 | else | |
7078 | { | |
7079 | if (word_op[0] == 's') | |
c53aa195 | 7080 | { |
e0d80184 | 7081 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
7082 | word_op, reg_names[regno], |
7083 | base_reg, offset); | |
0021b564 | 7084 | if (dwarf2out_do_frame ()) |
c53aa195 | 7085 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 7086 | } |
c819be5b | 7087 | else |
e0d80184 | 7088 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 7089 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 7090 | |
86735b02 | 7091 | offset += UNITS_PER_WORD; |
c819be5b JW |
7092 | } |
7093 | } | |
7094 | } | |
7095 | } | |
7096 | ||
7097 | if (fmask) | |
7098 | { | |
7099 | for (regno = 32; regno <= 63; regno++) | |
7100 | { | |
7101 | if ((fmask & (1L << (regno - 32))) != 0) | |
7102 | { | |
7103 | if (word_op[0] == 's') | |
c53aa195 | 7104 | { |
e0d80184 | 7105 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
7106 | word_op, reg_names[regno], |
7107 | base_reg, offset); | |
0021b564 | 7108 | if (dwarf2out_do_frame ()) |
c53aa195 | 7109 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 7110 | } |
c819be5b | 7111 | else |
e0d80184 | 7112 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 7113 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 7114 | |
86735b02 | 7115 | offset += UNITS_PER_WORD; |
c819be5b JW |
7116 | } |
7117 | } | |
7118 | } | |
7119 | } | |
7120 | \f | |
7121 | /* Set up the stack and frame (if desired) for the function. */ | |
7122 | ||
08c148a8 NB |
7123 | static void |
7124 | sparc_flat_function_prologue (file, size) | |
c819be5b | 7125 | FILE *file; |
08c148a8 | 7126 | HOST_WIDE_INT size; |
c819be5b | 7127 | { |
99f44eba | 7128 | const char *sp_str = reg_names[STACK_POINTER_REGNUM]; |
86735b02 | 7129 | unsigned long gmask = current_frame_info.gmask; |
a07c1915 | 7130 | |
1cb36a98 RH |
7131 | sparc_output_scratch_registers (file); |
7132 | ||
c6aa9ce1 | 7133 | /* This is only for the human reader. */ |
bf62bbf1 | 7134 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
5e9defae | 7135 | fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n", |
bf62bbf1 | 7136 | ASM_COMMENT_START, |
86735b02 DE |
7137 | current_frame_info.var_size, |
7138 | current_frame_info.gp_reg_size / 4, | |
9f8b85b8 | 7139 | current_frame_info.fp_reg_size / 4, |
86735b02 DE |
7140 | current_function_outgoing_args_size, |
7141 | current_frame_info.extra_size); | |
c819be5b JW |
7142 | |
7143 | size = SPARC_STACK_ALIGN (size); | |
86735b02 DE |
7144 | size = (! current_frame_info.initialized |
7145 | ? sparc_flat_compute_frame_size (size) | |
7146 | : current_frame_info.total_size); | |
c819be5b | 7147 | |
86735b02 DE |
7148 | /* These cases shouldn't happen. Catch them now. */ |
7149 | if (size == 0 && (gmask || current_frame_info.fmask)) | |
7150 | abort (); | |
c819be5b | 7151 | |
86735b02 DE |
7152 | /* Allocate our stack frame by decrementing %sp. |
7153 | At present, the only algorithm gdb can use to determine if this is a | |
7154 | flat frame is if we always set %i7 if we set %sp. This can be optimized | |
7155 | in the future by putting in some sort of debugging information that says | |
7156 | this is a `flat' function. However, there is still the case of debugging | |
7157 | code without such debugging information (including cases where most fns | |
7158 | have such info, but there is one that doesn't). So, always do this now | |
7159 | so we don't get a lot of code out there that gdb can't handle. | |
7160 | If the frame pointer isn't needn't then that's ok - gdb won't be able to | |
7161 | distinguish us from a non-flat function but there won't (and shouldn't) | |
7162 | be any differences anyway. The return pc is saved (if necessary) right | |
7163 | after %i7 so gdb won't have to look too far to find it. */ | |
7164 | if (size > 0) | |
c819be5b | 7165 | { |
86735b02 | 7166 | unsigned int reg_offset = current_frame_info.reg_offset; |
563c12b0 | 7167 | const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; |
83182544 | 7168 | static const char *const t1_str = "%g1"; |
86735b02 DE |
7169 | |
7170 | /* Things get a little tricky if local variables take up more than ~4096 | |
7171 | bytes and outgoing arguments take up more than ~4096 bytes. When that | |
7172 | happens, the register save area can't be accessed from either end of | |
7173 | the frame. Handle this by decrementing %sp to the start of the gp | |
7174 | register save area, save the regs, update %i7, and then set %sp to its | |
7175 | final value. Given that we only have one scratch register to play | |
7176 | with it is the cheapest solution, and it helps gdb out as it won't | |
7177 | slow down recognition of flat functions. | |
7178 | Don't change the order of insns emitted here without checking with | |
7179 | the gdb folk first. */ | |
7180 | ||
ddd5a7c1 | 7181 | /* Is the entire register save area offsettable from %sp? */ |
fbd039b2 | 7182 | if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) |
86735b02 DE |
7183 | { |
7184 | if (size <= 4096) | |
7185 | { | |
e0d80184 | 7186 | fprintf (file, "\tadd\t%s, %d, %s\n", |
0d587737 | 7187 | sp_str, (int) -size, sp_str); |
563c12b0 | 7188 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7189 | { |
e0d80184 | 7190 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 7191 | fp_str, sp_str, reg_offset); |
e0d80184 | 7192 | fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n", |
0d587737 | 7193 | sp_str, (int) -size, fp_str, ASM_COMMENT_START); |
86735b02 DE |
7194 | reg_offset += 4; |
7195 | } | |
7196 | } | |
7197 | else | |
7198 | { | |
0d587737 KG |
7199 | fprintf (file, "\tset\t"); |
7200 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); | |
7201 | fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", | |
7202 | t1_str, sp_str, t1_str, sp_str); | |
563c12b0 | 7203 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7204 | { |
e0d80184 | 7205 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 7206 | fp_str, sp_str, reg_offset); |
e0d80184 | 7207 | fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
bf62bbf1 | 7208 | sp_str, t1_str, fp_str, ASM_COMMENT_START); |
86735b02 DE |
7209 | reg_offset += 4; |
7210 | } | |
7211 | } | |
0021b564 | 7212 | if (dwarf2out_do_frame ()) |
c53aa195 | 7213 | { |
96987e96 | 7214 | char *l = dwarf2out_cfi_label (); |
563c12b0 | 7215 | if (gmask & HARD_FRAME_POINTER_MASK) |
c53aa195 | 7216 | { |
563c12b0 | 7217 | dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, |
c53aa195 | 7218 | reg_offset - 4 - size); |
563c12b0 | 7219 | dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); |
c53aa195 JM |
7220 | } |
7221 | else | |
7222 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size); | |
7223 | } | |
86735b02 DE |
7224 | if (gmask & RETURN_ADDR_MASK) |
7225 | { | |
e0d80184 | 7226 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 7227 | reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); |
0021b564 | 7228 | if (dwarf2out_do_frame ()) |
c53aa195 | 7229 | dwarf2out_return_save ("", reg_offset - size); |
86735b02 DE |
7230 | reg_offset += 4; |
7231 | } | |
7232 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
563c12b0 | 7233 | gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), |
86735b02 | 7234 | current_frame_info.fmask, |
84e884e9 | 7235 | "st", "std", -size); |
86735b02 | 7236 | } |
c819be5b | 7237 | else |
86735b02 DE |
7238 | { |
7239 | /* Subtract %sp in two steps, but make sure there is always a | |
7240 | 64 byte register save area, and %sp is properly aligned. */ | |
7241 | /* Amount to decrement %sp by, the first time. */ | |
08c148a8 | 7242 | unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16; |
86735b02 | 7243 | /* Offset to register save area from %sp. */ |
08c148a8 | 7244 | unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset); |
86735b02 DE |
7245 | |
7246 | if (size1 <= 4096) | |
7247 | { | |
e0d80184 | 7248 | fprintf (file, "\tadd\t%s, %d, %s\n", |
0d587737 | 7249 | sp_str, (int) -size1, sp_str); |
563c12b0 | 7250 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7251 | { |
e0d80184 | 7252 | fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n", |
0d587737 KG |
7253 | fp_str, sp_str, (int) offset, sp_str, (int) -size1, |
7254 | fp_str, ASM_COMMENT_START); | |
86735b02 DE |
7255 | offset += 4; |
7256 | } | |
7257 | } | |
7258 | else | |
7259 | { | |
0d587737 KG |
7260 | fprintf (file, "\tset\t"); |
7261 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1); | |
7262 | fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", | |
7263 | t1_str, sp_str, t1_str, sp_str); | |
563c12b0 | 7264 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7265 | { |
e0d80184 | 7266 | fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
0d587737 KG |
7267 | fp_str, sp_str, (int) offset, sp_str, t1_str, |
7268 | fp_str, ASM_COMMENT_START); | |
86735b02 DE |
7269 | offset += 4; |
7270 | } | |
7271 | } | |
0021b564 | 7272 | if (dwarf2out_do_frame ()) |
c53aa195 | 7273 | { |
96987e96 | 7274 | char *l = dwarf2out_cfi_label (); |
563c12b0 | 7275 | if (gmask & HARD_FRAME_POINTER_MASK) |
c53aa195 | 7276 | { |
563c12b0 | 7277 | dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, |
c53aa195 | 7278 | offset - 4 - size1); |
563c12b0 | 7279 | dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); |
c53aa195 JM |
7280 | } |
7281 | else | |
7282 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1); | |
7283 | } | |
86735b02 DE |
7284 | if (gmask & RETURN_ADDR_MASK) |
7285 | { | |
e0d80184 | 7286 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
0d587737 | 7287 | reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset); |
0021b564 | 7288 | if (dwarf2out_do_frame ()) |
c53aa195 JM |
7289 | /* offset - size1 == reg_offset - size |
7290 | if reg_offset were updated above like offset. */ | |
7291 | dwarf2out_return_save ("", offset - size1); | |
86735b02 DE |
7292 | offset += 4; |
7293 | } | |
7294 | sparc_flat_save_restore (file, sp_str, offset, | |
563c12b0 | 7295 | gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), |
86735b02 | 7296 | current_frame_info.fmask, |
84e884e9 | 7297 | "st", "std", -size1); |
0d587737 KG |
7298 | fprintf (file, "\tset\t"); |
7299 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, size - size1); | |
7300 | fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", | |
7301 | t1_str, sp_str, t1_str, sp_str); | |
0021b564 | 7302 | if (dwarf2out_do_frame ()) |
563c12b0 | 7303 | if (! (gmask & HARD_FRAME_POINTER_MASK)) |
c53aa195 | 7304 | dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size); |
86735b02 | 7305 | } |
c819be5b | 7306 | } |
c6aa9ce1 | 7307 | |
bf62bbf1 | 7308 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
c819be5b JW |
7309 | } |
7310 | \f | |
7311 | /* Do any necessary cleanup after a function to restore stack, frame, | |
80ffc95e | 7312 | and regs. */ |
c819be5b | 7313 | |
08c148a8 NB |
7314 | static void |
7315 | sparc_flat_function_epilogue (file, size) | |
c819be5b | 7316 | FILE *file; |
08c148a8 | 7317 | HOST_WIDE_INT size; |
c819be5b | 7318 | { |
c819be5b JW |
7319 | rtx epilogue_delay = current_function_epilogue_delay_list; |
7320 | int noepilogue = FALSE; | |
c819be5b | 7321 | |
c6aa9ce1 | 7322 | /* This is only for the human reader. */ |
bf62bbf1 | 7323 | fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START); |
c6aa9ce1 | 7324 | |
c819be5b JW |
7325 | /* The epilogue does not depend on any registers, but the stack |
7326 | registers, so we assume that if we have 1 pending nop, it can be | |
7327 | ignored, and 2 it must be filled (2 nops occur for integer | |
7328 | multiply and divide). */ | |
7329 | ||
7330 | size = SPARC_STACK_ALIGN (size); | |
86735b02 | 7331 | size = (!current_frame_info.initialized |
c6aa9ce1 | 7332 | ? sparc_flat_compute_frame_size (size) |
c819be5b JW |
7333 | : current_frame_info.total_size); |
7334 | ||
86735b02 | 7335 | if (size == 0 && epilogue_delay == 0) |
c819be5b JW |
7336 | { |
7337 | rtx insn = get_last_insn (); | |
7338 | ||
7339 | /* If the last insn was a BARRIER, we don't have to write any code | |
7340 | because a jump (aka return) was put there. */ | |
7341 | if (GET_CODE (insn) == NOTE) | |
7342 | insn = prev_nonnote_insn (insn); | |
7343 | if (insn && GET_CODE (insn) == BARRIER) | |
7344 | noepilogue = TRUE; | |
7345 | } | |
7346 | ||
7347 | if (!noepilogue) | |
7348 | { | |
08c148a8 NB |
7349 | unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset; |
7350 | unsigned HOST_WIDE_INT size1; | |
27c38fbe | 7351 | const char *const sp_str = reg_names[STACK_POINTER_REGNUM]; |
563c12b0 | 7352 | const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; |
83182544 | 7353 | static const char *const t1_str = "%g1"; |
86735b02 | 7354 | |
c819be5b JW |
7355 | /* In the reload sequence, we don't need to fill the load delay |
7356 | slots for most of the loads, also see if we can fill the final | |
7357 | delay slot if not otherwise filled by the reload sequence. */ | |
7358 | ||
86735b02 | 7359 | if (size > 4095) |
0d587737 KG |
7360 | { |
7361 | fprintf (file, "\tset\t"); | |
7362 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); | |
7363 | fprintf (file, ", %s\n", t1_str); | |
7364 | } | |
c819be5b JW |
7365 | |
7366 | if (frame_pointer_needed) | |
7367 | { | |
86735b02 | 7368 | if (size > 4095) |
e0d80184 | 7369 | fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n", |
bf62bbf1 | 7370 | fp_str, t1_str, sp_str, ASM_COMMENT_START); |
c819be5b | 7371 | else |
e0d80184 | 7372 | fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n", |
0d587737 | 7373 | fp_str, (int) size, sp_str, ASM_COMMENT_START); |
c819be5b JW |
7374 | } |
7375 | ||
ddd5a7c1 | 7376 | /* Is the entire register save area offsettable from %sp? */ |
fbd039b2 | 7377 | if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) |
86735b02 DE |
7378 | { |
7379 | size1 = 0; | |
7380 | } | |
7381 | else | |
7382 | { | |
7383 | /* Restore %sp in two steps, but make sure there is always a | |
7384 | 64 byte register save area, and %sp is properly aligned. */ | |
7385 | /* Amount to increment %sp by, the first time. */ | |
7386 | size1 = ((reg_offset - 64 - 16) + 15) & -16; | |
7387 | /* Offset to register save area from %sp. */ | |
7388 | reg_offset = size1 - reg_offset; | |
7389 | ||
0d587737 KG |
7390 | fprintf (file, "\tset\t"); |
7391 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1); | |
7392 | fprintf (file, ", %s\n\tadd\t%s, %s, %s\n", | |
7393 | t1_str, sp_str, t1_str, sp_str); | |
86735b02 DE |
7394 | } |
7395 | ||
7396 | /* We must restore the frame pointer and return address reg first | |
7397 | because they are treated specially by the prologue output code. */ | |
563c12b0 | 7398 | if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7399 | { |
e0d80184 | 7400 | fprintf (file, "\tld\t[%s+%d], %s\n", |
0d587737 | 7401 | sp_str, (int) reg_offset, fp_str); |
86735b02 DE |
7402 | reg_offset += 4; |
7403 | } | |
7404 | if (current_frame_info.gmask & RETURN_ADDR_MASK) | |
7405 | { | |
e0d80184 | 7406 | fprintf (file, "\tld\t[%s+%d], %s\n", |
0d587737 | 7407 | sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]); |
86735b02 DE |
7408 | reg_offset += 4; |
7409 | } | |
7410 | ||
7411 | /* Restore any remaining saved registers. */ | |
7412 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
563c12b0 | 7413 | current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), |
86735b02 | 7414 | current_frame_info.fmask, |
c53aa195 | 7415 | "ld", "ldd", 0); |
86735b02 DE |
7416 | |
7417 | /* If we had to increment %sp in two steps, record it so the second | |
7418 | restoration in the epilogue finishes up. */ | |
7419 | if (size1 > 0) | |
7420 | { | |
7421 | size -= size1; | |
7422 | if (size > 4095) | |
0d587737 KG |
7423 | { |
7424 | fprintf (file, "\tset\t"); | |
7425 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); | |
7426 | fprintf (file, ", %s\n", t1_str); | |
7427 | } | |
86735b02 | 7428 | } |
c819be5b | 7429 | |
c819be5b | 7430 | if (current_function_returns_struct) |
e0d80184 | 7431 | fprintf (file, "\tjmp\t%%o7+12\n"); |
c819be5b JW |
7432 | else |
7433 | fprintf (file, "\tretl\n"); | |
7434 | ||
7435 | /* If the only register saved is the return address, we need a | |
7436 | nop, unless we have an instruction to put into it. Otherwise | |
7437 | we don't since reloading multiple registers doesn't reference | |
7438 | the register being loaded. */ | |
7439 | ||
7440 | if (epilogue_delay) | |
7441 | { | |
86735b02 | 7442 | if (size) |
c819be5b JW |
7443 | abort (); |
7444 | final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); | |
7445 | } | |
7446 | ||
86735b02 | 7447 | else if (size > 4095) |
e0d80184 | 7448 | fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); |
c819be5b | 7449 | |
86735b02 | 7450 | else if (size > 0) |
0d587737 | 7451 | fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str); |
c819be5b JW |
7452 | |
7453 | else | |
7454 | fprintf (file, "\tnop\n"); | |
7455 | } | |
7456 | ||
7457 | /* Reset state info for each function. */ | |
7458 | current_frame_info = zero_frame_info; | |
e0d80184 DM |
7459 | |
7460 | sparc_output_deferred_case_vectors (); | |
c819be5b JW |
7461 | } |
7462 | \f | |
7463 | /* Define the number of delay slots needed for the function epilogue. | |
7464 | ||
7465 | On the sparc, we need a slot if either no stack has been allocated, | |
7466 | or the only register saved is the return register. */ | |
7467 | ||
7468 | int | |
c6aa9ce1 | 7469 | sparc_flat_epilogue_delay_slots () |
c819be5b JW |
7470 | { |
7471 | if (!current_frame_info.initialized) | |
c6aa9ce1 | 7472 | (void) sparc_flat_compute_frame_size (get_frame_size ()); |
c819be5b JW |
7473 | |
7474 | if (current_frame_info.total_size == 0) | |
7475 | return 1; | |
7476 | ||
c819be5b JW |
7477 | return 0; |
7478 | } | |
7479 | ||
51f26c45 | 7480 | /* Return true if TRIAL is a valid insn for the epilogue delay slot. |
c819be5b JW |
7481 | Any single length instruction which doesn't reference the stack or frame |
7482 | pointer is OK. */ | |
7483 | ||
7484 | int | |
c6aa9ce1 | 7485 | sparc_flat_eligible_for_epilogue_delay (trial, slot) |
c819be5b | 7486 | rtx trial; |
db3d4438 | 7487 | int slot ATTRIBUTE_UNUSED; |
c819be5b | 7488 | { |
c4ce6853 DE |
7489 | rtx pat = PATTERN (trial); |
7490 | ||
7491 | if (get_attr_length (trial) != 1) | |
7492 | return 0; | |
7493 | ||
c4ce6853 DE |
7494 | if (! reg_mentioned_p (stack_pointer_rtx, pat) |
7495 | && ! reg_mentioned_p (frame_pointer_rtx, pat)) | |
c819be5b | 7496 | return 1; |
c4ce6853 | 7497 | |
c819be5b JW |
7498 | return 0; |
7499 | } | |
dbb54862 JW |
7500 | \f |
7501 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
7502 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
7503 | ||
8947065c | 7504 | static int |
dbb54862 JW |
7505 | supersparc_adjust_cost (insn, link, dep_insn, cost) |
7506 | rtx insn; | |
7507 | rtx link; | |
7508 | rtx dep_insn; | |
7509 | int cost; | |
7510 | { | |
7511 | enum attr_type insn_type; | |
7512 | ||
7513 | if (! recog_memoized (insn)) | |
7514 | return 0; | |
7515 | ||
7516 | insn_type = get_attr_type (insn); | |
7517 | ||
7518 | if (REG_NOTE_KIND (link) == 0) | |
7519 | { | |
7520 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7521 | cycles later. */ | |
7522 | ||
7523 | /* if a load, then the dependence must be on the memory address; | |
3bc8b61e DM |
7524 | add an extra "cycle". Note that the cost could be two cycles |
7525 | if the reg was written late in an instruction group; we ca not tell | |
dbb54862 JW |
7526 | here. */ |
7527 | if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) | |
7528 | return cost + 3; | |
7529 | ||
7530 | /* Get the delay only if the address of the store is the dependence. */ | |
7531 | if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) | |
7532 | { | |
7533 | rtx pat = PATTERN(insn); | |
7534 | rtx dep_pat = PATTERN (dep_insn); | |
7535 | ||
7536 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
3bc8b61e | 7537 | return cost; /* This should not happen! */ |
dbb54862 JW |
7538 | |
7539 | /* The dependency between the two instructions was on the data that | |
7540 | is being stored. Assume that this implies that the address of the | |
7541 | store is not dependent. */ | |
7542 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
7543 | return cost; | |
7544 | ||
7545 | return cost + 3; /* An approximation. */ | |
7546 | } | |
7547 | ||
7548 | /* A shift instruction cannot receive its data from an instruction | |
7549 | in the same cycle; add a one cycle penalty. */ | |
7550 | if (insn_type == TYPE_SHIFT) | |
7551 | return cost + 3; /* Split before cascade into shift. */ | |
7552 | } | |
7553 | else | |
7554 | { | |
7555 | /* Anti- or output- dependency; DEP_INSN reads/writes a register that | |
7556 | INSN writes some cycles later. */ | |
7557 | ||
7558 | /* These are only significant for the fpu unit; writing a fp reg before | |
7559 | the fpu has finished with it stalls the processor. */ | |
7560 | ||
7561 | /* Reusing an integer register causes no problems. */ | |
7562 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
7563 | return 0; | |
7564 | } | |
7565 | ||
7566 | return cost; | |
7567 | } | |
bfd6bc60 | 7568 | |
8947065c RH |
7569 | static int |
7570 | hypersparc_adjust_cost (insn, link, dep_insn, cost) | |
7571 | rtx insn; | |
7572 | rtx link; | |
7573 | rtx dep_insn; | |
7574 | int cost; | |
7575 | { | |
7576 | enum attr_type insn_type, dep_type; | |
7577 | rtx pat = PATTERN(insn); | |
7578 | rtx dep_pat = PATTERN (dep_insn); | |
7579 | ||
7580 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) | |
7581 | return cost; | |
7582 | ||
7583 | insn_type = get_attr_type (insn); | |
7584 | dep_type = get_attr_type (dep_insn); | |
7585 | ||
7586 | switch (REG_NOTE_KIND (link)) | |
7587 | { | |
7588 | case 0: | |
7589 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7590 | cycles later. */ | |
7591 | ||
7592 | switch (insn_type) | |
7593 | { | |
7594 | case TYPE_STORE: | |
7595 | case TYPE_FPSTORE: | |
80ffc95e | 7596 | /* Get the delay iff the address of the store is the dependence. */ |
8947065c RH |
7597 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) |
7598 | return cost; | |
7599 | ||
7600 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
7601 | return cost; | |
7602 | return cost + 3; | |
7603 | ||
7604 | case TYPE_LOAD: | |
7605 | case TYPE_SLOAD: | |
7606 | case TYPE_FPLOAD: | |
7607 | /* If a load, then the dependence must be on the memory address. If | |
7608 | the addresses aren't equal, then it might be a false dependency */ | |
7609 | if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) | |
7610 | { | |
7611 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET | |
7612 | || GET_CODE (SET_DEST (dep_pat)) != MEM | |
7613 | || GET_CODE (SET_SRC (pat)) != MEM | |
7614 | || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), | |
7615 | XEXP (SET_SRC (pat), 0))) | |
7616 | return cost + 2; | |
7617 | ||
7618 | return cost + 8; | |
7619 | } | |
7620 | break; | |
7621 | ||
7622 | case TYPE_BRANCH: | |
7623 | /* Compare to branch latency is 0. There is no benefit from | |
7624 | separating compare and branch. */ | |
7625 | if (dep_type == TYPE_COMPARE) | |
7626 | return 0; | |
7627 | /* Floating point compare to branch latency is less than | |
7628 | compare to conditional move. */ | |
7629 | if (dep_type == TYPE_FPCMP) | |
7630 | return cost - 1; | |
7631 | break; | |
3bb5de61 KG |
7632 | default: |
7633 | break; | |
8947065c RH |
7634 | } |
7635 | break; | |
7636 | ||
7637 | case REG_DEP_ANTI: | |
80ffc95e | 7638 | /* Anti-dependencies only penalize the fpu unit. */ |
8947065c RH |
7639 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) |
7640 | return 0; | |
7641 | break; | |
7642 | ||
7643 | default: | |
7644 | break; | |
7645 | } | |
7646 | ||
7647 | return cost; | |
7648 | } | |
7649 | ||
c237e94a | 7650 | static int |
8947065c RH |
7651 | sparc_adjust_cost(insn, link, dep, cost) |
7652 | rtx insn; | |
7653 | rtx link; | |
7654 | rtx dep; | |
7655 | int cost; | |
7656 | { | |
7657 | switch (sparc_cpu) | |
7658 | { | |
7659 | case PROCESSOR_SUPERSPARC: | |
7660 | cost = supersparc_adjust_cost (insn, link, dep, cost); | |
7661 | break; | |
7662 | case PROCESSOR_HYPERSPARC: | |
7663 | case PROCESSOR_SPARCLITE86X: | |
7664 | cost = hypersparc_adjust_cost (insn, link, dep, cost); | |
7665 | break; | |
8947065c RH |
7666 | default: |
7667 | break; | |
7668 | } | |
7669 | return cost; | |
7670 | } | |
7671 | ||
fae15c93 VM |
7672 | static void |
7673 | sparc_sched_init (dump, sched_verbose, max_ready) | |
7674 | FILE *dump ATTRIBUTE_UNUSED; | |
7675 | int sched_verbose ATTRIBUTE_UNUSED; | |
7676 | int max_ready ATTRIBUTE_UNUSED; | |
3bc8b61e | 7677 | { |
3bc8b61e | 7678 | } |
fae15c93 | 7679 | |
3bc8b61e | 7680 | static int |
fae15c93 | 7681 | sparc_use_dfa_pipeline_interface () |
3bc8b61e | 7682 | { |
fae15c93 VM |
7683 | if ((1 << sparc_cpu) & |
7684 | ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) | | |
7685 | (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | | |
7686 | (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) | | |
7687 | (1 << PROCESSOR_ULTRASPARC3))) | |
7688 | return 1; | |
3bc8b61e DM |
7689 | return 0; |
7690 | } | |
7691 | ||
fae15c93 VM |
7692 | static int |
7693 | sparc_use_sched_lookahead () | |
7694 | { | |
7695 | if (sparc_cpu == PROCESSOR_ULTRASPARC | |
7696 | || sparc_cpu == PROCESSOR_ULTRASPARC3) | |
7697 | return 4; | |
7698 | if ((1 << sparc_cpu) & | |
7699 | ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | | |
7700 | (1 << PROCESSOR_SPARCLITE86X))) | |
7701 | return 3; | |
3bc8b61e DM |
7702 | return 0; |
7703 | } | |
7704 | ||
fae15c93 | 7705 | static int |
bfd6bc60 JC |
7706 | sparc_issue_rate () |
7707 | { | |
7708 | switch (sparc_cpu) | |
7709 | { | |
fae15c93 VM |
7710 | default: |
7711 | return 1; | |
7712 | case PROCESSOR_V9: | |
284d86e9 | 7713 | /* Assume V9 processors are capable of at least dual-issue. */ |
bfd6bc60 | 7714 | return 2; |
fae15c93 VM |
7715 | case PROCESSOR_SUPERSPARC: |
7716 | return 3; | |
393049a9 RH |
7717 | case PROCESSOR_HYPERSPARC: |
7718 | case PROCESSOR_SPARCLITE86X: | |
7719 | return 2; | |
fae15c93 VM |
7720 | case PROCESSOR_ULTRASPARC: |
7721 | case PROCESSOR_ULTRASPARC3: | |
7722 | return 4; | |
bfd6bc60 JC |
7723 | } |
7724 | } | |
284d86e9 JC |
7725 | |
7726 | static int | |
4df1190a JJ |
7727 | set_extends (insn) |
7728 | rtx insn; | |
284d86e9 JC |
7729 | { |
7730 | register rtx pat = PATTERN (insn); | |
7731 | ||
7732 | switch (GET_CODE (SET_SRC (pat))) | |
7733 | { | |
80ffc95e | 7734 | /* Load and some shift instructions zero extend. */ |
284d86e9 JC |
7735 | case MEM: |
7736 | case ZERO_EXTEND: | |
7737 | /* sethi clears the high bits */ | |
7738 | case HIGH: | |
7739 | /* LO_SUM is used with sethi. sethi cleared the high | |
7740 | bits and the values used with lo_sum are positive */ | |
7741 | case LO_SUM: | |
284d86e9 JC |
7742 | /* Store flag stores 0 or 1 */ |
7743 | case LT: case LTU: | |
7744 | case GT: case GTU: | |
7745 | case LE: case LEU: | |
7746 | case GE: case GEU: | |
7747 | case EQ: | |
7748 | case NE: | |
7749 | return 1; | |
7750 | case AND: | |
7751 | { | |
4df1190a | 7752 | rtx op0 = XEXP (SET_SRC (pat), 0); |
284d86e9 JC |
7753 | rtx op1 = XEXP (SET_SRC (pat), 1); |
7754 | if (GET_CODE (op1) == CONST_INT) | |
7755 | return INTVAL (op1) >= 0; | |
4df1190a JJ |
7756 | if (GET_CODE (op0) != REG) |
7757 | return 0; | |
7758 | if (sparc_check_64 (op0, insn) == 1) | |
284d86e9 | 7759 | return 1; |
4df1190a JJ |
7760 | return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); |
7761 | } | |
7762 | case IOR: | |
7763 | case XOR: | |
7764 | { | |
7765 | rtx op0 = XEXP (SET_SRC (pat), 0); | |
7766 | rtx op1 = XEXP (SET_SRC (pat), 1); | |
7767 | if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) | |
7768 | return 0; | |
7769 | if (GET_CODE (op1) == CONST_INT) | |
7770 | return INTVAL (op1) >= 0; | |
7771 | return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); | |
284d86e9 JC |
7772 | } |
7773 | case ASHIFT: | |
7774 | case LSHIFTRT: | |
7775 | return GET_MODE (SET_SRC (pat)) == SImode; | |
80ffc95e | 7776 | /* Positive integers leave the high bits zero. */ |
284d86e9 | 7777 | case CONST_DOUBLE: |
4df1190a | 7778 | return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000); |
284d86e9 | 7779 | case CONST_INT: |
4df1190a | 7780 | return ! (INTVAL (SET_SRC (pat)) & 0x80000000); |
284d86e9 JC |
7781 | case ASHIFTRT: |
7782 | case SIGN_EXTEND: | |
7783 | return - (GET_MODE (SET_SRC (pat)) == SImode); | |
4df1190a JJ |
7784 | case REG: |
7785 | return sparc_check_64 (SET_SRC (pat), insn); | |
284d86e9 JC |
7786 | default: |
7787 | return 0; | |
7788 | } | |
7789 | } | |
7790 | ||
80ffc95e | 7791 | /* We _ought_ to have only one kind per function, but... */ |
e0d80184 DM |
7792 | static rtx sparc_addr_diff_list; |
7793 | static rtx sparc_addr_list; | |
7794 | ||
7795 | void | |
7796 | sparc_defer_case_vector (lab, vec, diff) | |
7797 | rtx lab, vec; | |
7798 | int diff; | |
7799 | { | |
7800 | vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); | |
7801 | if (diff) | |
7802 | sparc_addr_diff_list | |
7803 | = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); | |
7804 | else | |
7805 | sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); | |
7806 | } | |
7807 | ||
7808 | static void | |
7809 | sparc_output_addr_vec (vec) | |
7810 | rtx vec; | |
7811 | { | |
7812 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
7813 | int idx, vlen = XVECLEN (body, 0); | |
7814 | ||
d1accaa3 JJ |
7815 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
7816 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
7817 | #endif | |
7818 | ||
e0d80184 DM |
7819 | #ifdef ASM_OUTPUT_CASE_LABEL |
7820 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
7821 | NEXT_INSN (lab)); | |
7822 | #else | |
7823 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); | |
7824 | #endif | |
7825 | ||
7826 | for (idx = 0; idx < vlen; idx++) | |
7827 | { | |
7828 | ASM_OUTPUT_ADDR_VEC_ELT | |
7829 | (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); | |
7830 | } | |
d1accaa3 JJ |
7831 | |
7832 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
7833 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
7834 | #endif | |
e0d80184 DM |
7835 | } |
7836 | ||
7837 | static void | |
7838 | sparc_output_addr_diff_vec (vec) | |
7839 | rtx vec; | |
7840 | { | |
7841 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
7842 | rtx base = XEXP (XEXP (body, 0), 0); | |
7843 | int idx, vlen = XVECLEN (body, 1); | |
7844 | ||
d1accaa3 JJ |
7845 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
7846 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
7847 | #endif | |
7848 | ||
e0d80184 DM |
7849 | #ifdef ASM_OUTPUT_CASE_LABEL |
7850 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
7851 | NEXT_INSN (lab)); | |
7852 | #else | |
7853 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); | |
7854 | #endif | |
7855 | ||
7856 | for (idx = 0; idx < vlen; idx++) | |
7857 | { | |
7858 | ASM_OUTPUT_ADDR_DIFF_ELT | |
7859 | (asm_out_file, | |
7860 | body, | |
7861 | CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), | |
7862 | CODE_LABEL_NUMBER (base)); | |
7863 | } | |
d1accaa3 JJ |
7864 | |
7865 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
7866 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
7867 | #endif | |
e0d80184 DM |
7868 | } |
7869 | ||
7870 | static void | |
7871 | sparc_output_deferred_case_vectors () | |
7872 | { | |
7873 | rtx t; | |
d676da68 | 7874 | int align; |
e0d80184 | 7875 | |
f3b8847b DM |
7876 | if (sparc_addr_list == NULL_RTX |
7877 | && sparc_addr_diff_list == NULL_RTX) | |
7878 | return; | |
7879 | ||
e0d80184 DM |
7880 | /* Align to cache line in the function's code section. */ |
7881 | function_section (current_function_decl); | |
d676da68 DM |
7882 | |
7883 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
7884 | if (align > 0) | |
f3b8847b | 7885 | ASM_OUTPUT_ALIGN (asm_out_file, align); |
e0d80184 DM |
7886 | |
7887 | for (t = sparc_addr_list; t ; t = XEXP (t, 1)) | |
7888 | sparc_output_addr_vec (XEXP (t, 0)); | |
7889 | for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) | |
7890 | sparc_output_addr_diff_vec (XEXP (t, 0)); | |
7891 | ||
7892 | sparc_addr_list = sparc_addr_diff_list = NULL_RTX; | |
7893 | } | |
7894 | ||
284d86e9 JC |
7895 | /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are |
7896 | unknown. Return 1 if the high bits are zero, -1 if the register is | |
7897 | sign extended. */ | |
7898 | int | |
7899 | sparc_check_64 (x, insn) | |
7900 | rtx x, insn; | |
7901 | { | |
7902 | /* If a register is set only once it is safe to ignore insns this | |
7903 | code does not know how to handle. The loop will either recognize | |
7904 | the single set and return the correct value or fail to recognize | |
7905 | it and return 0. */ | |
7906 | int set_once = 0; | |
4df1190a JJ |
7907 | rtx y = x; |
7908 | ||
7909 | if (GET_CODE (x) != REG) | |
7910 | abort (); | |
7911 | ||
7912 | if (GET_MODE (x) == DImode) | |
7913 | y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN); | |
284d86e9 | 7914 | |
4df1190a JJ |
7915 | if (flag_expensive_optimizations |
7916 | && REG_N_SETS (REGNO (y)) == 1) | |
284d86e9 JC |
7917 | set_once = 1; |
7918 | ||
7919 | if (insn == 0) | |
d6f4ec51 KG |
7920 | { |
7921 | if (set_once) | |
7922 | insn = get_last_insn_anywhere (); | |
7923 | else | |
7924 | return 0; | |
7925 | } | |
284d86e9 | 7926 | |
d6f4ec51 | 7927 | while ((insn = PREV_INSN (insn))) |
284d86e9 JC |
7928 | { |
7929 | switch (GET_CODE (insn)) | |
7930 | { | |
7931 | case JUMP_INSN: | |
7932 | case NOTE: | |
7933 | break; | |
7934 | case CODE_LABEL: | |
7935 | case CALL_INSN: | |
7936 | default: | |
7937 | if (! set_once) | |
7938 | return 0; | |
7939 | break; | |
7940 | case INSN: | |
7941 | { | |
7942 | rtx pat = PATTERN (insn); | |
7943 | if (GET_CODE (pat) != SET) | |
7944 | return 0; | |
7945 | if (rtx_equal_p (x, SET_DEST (pat))) | |
4df1190a JJ |
7946 | return set_extends (insn); |
7947 | if (y && rtx_equal_p (y, SET_DEST (pat))) | |
7948 | return set_extends (insn); | |
7949 | if (reg_overlap_mentioned_p (SET_DEST (pat), y)) | |
284d86e9 JC |
7950 | return 0; |
7951 | } | |
7952 | } | |
7953 | } | |
7954 | return 0; | |
7955 | } | |
7956 | ||
7957 | char * | |
7958 | sparc_v8plus_shift (operands, insn, opcode) | |
7959 | rtx *operands; | |
7960 | rtx insn; | |
b1474bb7 | 7961 | const char *opcode; |
284d86e9 JC |
7962 | { |
7963 | static char asm_code[60]; | |
7964 | ||
7965 | if (GET_CODE (operands[3]) == SCRATCH) | |
7966 | operands[3] = operands[0]; | |
c6b0465b JC |
7967 | if (GET_CODE (operands[1]) == CONST_INT) |
7968 | { | |
4df1190a | 7969 | output_asm_insn ("mov\t%1, %3", operands); |
c6b0465b JC |
7970 | } |
7971 | else | |
7972 | { | |
4df1190a | 7973 | output_asm_insn ("sllx\t%H1, 32, %3", operands); |
c6b0465b | 7974 | if (sparc_check_64 (operands[1], insn) <= 0) |
4df1190a JJ |
7975 | output_asm_insn ("srl\t%L1, 0, %L1", operands); |
7976 | output_asm_insn ("or\t%L1, %3, %3", operands); | |
c6b0465b | 7977 | } |
284d86e9 JC |
7978 | |
7979 | strcpy(asm_code, opcode); | |
7980 | if (which_alternative != 2) | |
4df1190a | 7981 | return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); |
284d86e9 | 7982 | else |
4df1190a | 7983 | return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"); |
284d86e9 | 7984 | } |
2be15d0f | 7985 | \f |
89a8b315 RH |
7986 | /* Output rtl to increment the profiler label LABELNO |
7987 | for profiling a function entry. */ | |
2be15d0f RH |
7988 | |
7989 | void | |
89a8b315 | 7990 | sparc_profile_hook (labelno) |
2be15d0f RH |
7991 | int labelno; |
7992 | { | |
7993 | char buf[32]; | |
89a8b315 | 7994 | rtx lab, fun; |
2be15d0f | 7995 | |
89a8b315 RH |
7996 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
7997 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
7998 | fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION); | |
2be15d0f | 7999 | |
eb29ddb6 | 8000 | emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode); |
2be15d0f | 8001 | } |
89a8b315 | 8002 | \f |
d07d525a MM |
8003 | /* Called to register all of our global variables with the garbage |
8004 | collector. */ | |
8005 | ||
8006 | static void | |
8007 | sparc_add_gc_roots () | |
8008 | { | |
8009 | ggc_add_rtx_root (&sparc_compare_op0, 1); | |
8010 | ggc_add_rtx_root (&sparc_compare_op1, 1); | |
d07d525a MM |
8011 | ggc_add_rtx_root (&global_offset_table, 1); |
8012 | ggc_add_rtx_root (&get_pc_symbol, 1); | |
8013 | ggc_add_rtx_root (&sparc_addr_diff_list, 1); | |
8014 | ggc_add_rtx_root (&sparc_addr_list, 1); | |
d07d525a | 8015 | } |
7c262518 | 8016 | |
ede75ee8 | 8017 | #ifdef OBJECT_FORMAT_ELF |
7c262518 | 8018 | static void |
715bdd29 | 8019 | sparc_elf_asm_named_section (name, flags) |
7c262518 RH |
8020 | const char *name; |
8021 | unsigned int flags; | |
7c262518 | 8022 | { |
201556f0 JJ |
8023 | if (flags & SECTION_MERGE) |
8024 | { | |
8025 | /* entsize cannot be expressed in this section attributes | |
8026 | encoding style. */ | |
8027 | default_elf_asm_named_section (name, flags); | |
8028 | return; | |
8029 | } | |
8030 | ||
7c262518 RH |
8031 | fprintf (asm_out_file, "\t.section\t\"%s\"", name); |
8032 | ||
8033 | if (!(flags & SECTION_DEBUG)) | |
8034 | fputs (",#alloc", asm_out_file); | |
8035 | if (flags & SECTION_WRITE) | |
8036 | fputs (",#write", asm_out_file); | |
8037 | if (flags & SECTION_CODE) | |
8038 | fputs (",#execinstr", asm_out_file); | |
8039 | ||
8040 | /* ??? Handle SECTION_BSS. */ | |
8041 | ||
8042 | fputc ('\n', asm_out_file); | |
8043 | } | |
ede75ee8 | 8044 | #endif /* OBJECT_FORMAT_ELF */ |
f451b552 | 8045 | |
ae46c4e0 RH |
8046 | /* ??? Similar to the standard section selection, but force reloc-y-ness |
8047 | if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to | |
8048 | pretending PIC always on), but that's what the old code did. */ | |
8049 | ||
8050 | static void | |
8051 | sparc_aout_select_section (t, reloc, align) | |
8052 | tree t; | |
8053 | int reloc; | |
8054 | unsigned HOST_WIDE_INT align; | |
8055 | { | |
8056 | default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align) | |
8057 | } | |
8058 | ||
f451b552 DM |
8059 | int |
8060 | sparc_extra_constraint_check (op, c, strict) | |
8061 | rtx op; | |
eb29ddb6 | 8062 | int c; |
f451b552 DM |
8063 | int strict; |
8064 | { | |
8065 | int reload_ok_mem; | |
8066 | ||
8067 | if (TARGET_ARCH64 | |
8068 | && (c == 'T' || c == 'U')) | |
8069 | return 0; | |
8070 | ||
8071 | switch (c) | |
8072 | { | |
8073 | case 'Q': | |
8074 | return fp_sethi_p (op); | |
8075 | ||
8076 | case 'R': | |
8077 | return fp_mov_p (op); | |
8078 | ||
8079 | case 'S': | |
8080 | return fp_high_losum_p (op); | |
8081 | ||
8082 | case 'U': | |
8083 | if (! strict | |
8084 | || (GET_CODE (op) == REG | |
8085 | && (REGNO (op) < FIRST_PSEUDO_REGISTER | |
8086 | || reg_renumber[REGNO (op)] >= 0))) | |
8087 | return register_ok_for_ldd (op); | |
8088 | ||
8089 | return 0; | |
8090 | ||
8091 | case 'W': | |
8092 | case 'T': | |
8093 | break; | |
8094 | ||
8095 | default: | |
8096 | return 0; | |
8097 | } | |
8098 | ||
8099 | /* Our memory extra constraints have to emulate the | |
8100 | behavior of 'm' and 'o' in order for reload to work | |
8101 | correctly. */ | |
8102 | if (GET_CODE (op) == MEM) | |
8103 | { | |
8104 | reload_ok_mem = 0; | |
8105 | if ((TARGET_ARCH64 || mem_min_alignment (op, 8)) | |
8106 | && (! strict | |
8107 | || strict_memory_address_p (Pmode, XEXP (op, 0)))) | |
8108 | reload_ok_mem = 1; | |
8109 | } | |
8110 | else | |
8111 | { | |
8112 | reload_ok_mem = (reload_in_progress | |
8113 | && GET_CODE (op) == REG | |
8114 | && REGNO (op) >= FIRST_PSEUDO_REGISTER | |
8115 | && reg_renumber [REGNO (op)] < 0); | |
8116 | } | |
8117 | ||
8118 | return reload_ok_mem; | |
8119 | } | |
2ce04b6b | 8120 | |
214c6394 DM |
8121 | /* ??? This duplicates information provided to the compiler by the |
8122 | ??? scheduler description. Some day, teach genautomata to output | |
8123 | ??? the latencies and then CSE will just use that. */ | |
8124 | ||
2ce04b6b DM |
8125 | int |
8126 | sparc_rtx_costs (x, code, outer_code) | |
8127 | rtx x; | |
8128 | enum rtx_code code, outer_code; | |
8129 | { | |
8130 | switch (code) | |
8131 | { | |
214c6394 DM |
8132 | case PLUS: case MINUS: case ABS: case NEG: |
8133 | case FLOAT: case UNSIGNED_FLOAT: | |
8134 | case FIX: case UNSIGNED_FIX: | |
8135 | case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
8136 | if (FLOAT_MODE_P (GET_MODE (x))) | |
8137 | { | |
8138 | switch (sparc_cpu) | |
8139 | { | |
8140 | case PROCESSOR_ULTRASPARC: | |
8141 | case PROCESSOR_ULTRASPARC3: | |
8142 | return COSTS_N_INSNS (4); | |
8143 | ||
8144 | case PROCESSOR_SUPERSPARC: | |
8145 | return COSTS_N_INSNS (3); | |
8146 | ||
8147 | case PROCESSOR_CYPRESS: | |
8148 | return COSTS_N_INSNS (5); | |
8149 | ||
8150 | case PROCESSOR_HYPERSPARC: | |
8151 | case PROCESSOR_SPARCLITE86X: | |
8152 | default: | |
8153 | return COSTS_N_INSNS (1); | |
8154 | } | |
8155 | } | |
8156 | ||
8157 | return COSTS_N_INSNS (1); | |
8158 | ||
8159 | case SQRT: | |
8160 | switch (sparc_cpu) | |
8161 | { | |
8162 | case PROCESSOR_ULTRASPARC: | |
8163 | if (GET_MODE (x) == SFmode) | |
8164 | return COSTS_N_INSNS (13); | |
8165 | else | |
8166 | return COSTS_N_INSNS (23); | |
8167 | ||
8168 | case PROCESSOR_ULTRASPARC3: | |
8169 | if (GET_MODE (x) == SFmode) | |
8170 | return COSTS_N_INSNS (20); | |
8171 | else | |
8172 | return COSTS_N_INSNS (29); | |
8173 | ||
8174 | case PROCESSOR_SUPERSPARC: | |
8175 | return COSTS_N_INSNS (12); | |
8176 | ||
8177 | case PROCESSOR_CYPRESS: | |
8178 | return COSTS_N_INSNS (63); | |
8179 | ||
8180 | case PROCESSOR_HYPERSPARC: | |
8181 | case PROCESSOR_SPARCLITE86X: | |
8182 | return COSTS_N_INSNS (17); | |
8183 | ||
8184 | default: | |
8185 | return COSTS_N_INSNS (30); | |
8186 | } | |
8187 | ||
8188 | case COMPARE: | |
8189 | if (FLOAT_MODE_P (GET_MODE (x))) | |
8190 | { | |
8191 | switch (sparc_cpu) | |
8192 | { | |
8193 | case PROCESSOR_ULTRASPARC: | |
8194 | case PROCESSOR_ULTRASPARC3: | |
8195 | return COSTS_N_INSNS (1); | |
8196 | ||
8197 | case PROCESSOR_SUPERSPARC: | |
8198 | return COSTS_N_INSNS (3); | |
8199 | ||
8200 | case PROCESSOR_CYPRESS: | |
8201 | return COSTS_N_INSNS (5); | |
8202 | ||
8203 | case PROCESSOR_HYPERSPARC: | |
8204 | case PROCESSOR_SPARCLITE86X: | |
8205 | default: | |
8206 | return COSTS_N_INSNS (1); | |
8207 | } | |
8208 | } | |
8209 | ||
8210 | /* ??? Maybe mark integer compares as zero cost on | |
8211 | ??? all UltraSPARC processors because the result | |
8212 | ??? can be bypassed to a branch in the same group. */ | |
8213 | ||
8214 | return COSTS_N_INSNS (1); | |
8215 | ||
2ce04b6b | 8216 | case MULT: |
214c6394 DM |
8217 | if (FLOAT_MODE_P (GET_MODE (x))) |
8218 | { | |
8219 | switch (sparc_cpu) | |
8220 | { | |
8221 | case PROCESSOR_ULTRASPARC: | |
8222 | case PROCESSOR_ULTRASPARC3: | |
8223 | return COSTS_N_INSNS (4); | |
8224 | ||
8225 | case PROCESSOR_SUPERSPARC: | |
8226 | return COSTS_N_INSNS (3); | |
8227 | ||
8228 | case PROCESSOR_CYPRESS: | |
8229 | return COSTS_N_INSNS (7); | |
8230 | ||
8231 | case PROCESSOR_HYPERSPARC: | |
8232 | case PROCESSOR_SPARCLITE86X: | |
8233 | return COSTS_N_INSNS (1); | |
8234 | ||
8235 | default: | |
8236 | return COSTS_N_INSNS (5); | |
8237 | } | |
8238 | } | |
8239 | ||
8240 | /* The latency is actually variable for Ultra-I/II | |
8241 | And if one of the inputs have a known constant | |
8242 | value, we could calculate this precisely. | |
8243 | ||
8244 | However, for that to be useful we would need to | |
8245 | add some machine description changes which would | |
8246 | make sure small constants ended up in rs1 of the | |
8247 | multiply instruction. This is because the multiply | |
8248 | latency is determined by the number of clear (or | |
8249 | set if the value is negative) bits starting from | |
8250 | the most significant bit of the first input. | |
8251 | ||
8252 | The algorithm for computing num_cycles of a multiply | |
8253 | on Ultra-I/II is: | |
8254 | ||
8255 | if (rs1 < 0) | |
8256 | highest_bit = highest_clear_bit(rs1); | |
8257 | else | |
8258 | highest_bit = highest_set_bit(rs1); | |
8259 | if (num_bits < 3) | |
8260 | highest_bit = 3; | |
8261 | num_cycles = 4 + ((highest_bit - 3) / 2); | |
8262 | ||
8263 | If we did that we would have to also consider register | |
8264 | allocation issues that would result from forcing such | |
8265 | a value into a register. | |
8266 | ||
8267 | There are other similar tricks we could play if we | |
8268 | knew, for example, that one input was an array index. | |
8269 | ||
8270 | Since we do not play any such tricks currently the | |
8271 | safest thing to do is report the worst case latency. */ | |
2ce04b6b DM |
8272 | if (sparc_cpu == PROCESSOR_ULTRASPARC) |
8273 | return (GET_MODE (x) == DImode ? | |
8274 | COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); | |
8275 | ||
214c6394 | 8276 | /* Multiply latency on Ultra-III, fortunately, is constant. */ |
2ce04b6b DM |
8277 | if (sparc_cpu == PROCESSOR_ULTRASPARC3) |
8278 | return COSTS_N_INSNS (6); | |
8279 | ||
214c6394 DM |
8280 | if (sparc_cpu == PROCESSOR_HYPERSPARC |
8281 | || sparc_cpu == PROCESSOR_SPARCLITE86X) | |
8282 | return COSTS_N_INSNS (17); | |
8283 | ||
2ce04b6b DM |
8284 | return (TARGET_HARD_MUL |
8285 | ? COSTS_N_INSNS (5) | |
8286 | : COSTS_N_INSNS (25)); | |
8287 | ||
8288 | case DIV: | |
8289 | case UDIV: | |
8290 | case MOD: | |
8291 | case UMOD: | |
214c6394 DM |
8292 | if (FLOAT_MODE_P (GET_MODE (x))) |
8293 | { | |
8294 | switch (sparc_cpu) | |
8295 | { | |
8296 | case PROCESSOR_ULTRASPARC: | |
8297 | if (GET_MODE (x) == SFmode) | |
8298 | return COSTS_N_INSNS (13); | |
8299 | else | |
8300 | return COSTS_N_INSNS (23); | |
8301 | ||
8302 | case PROCESSOR_ULTRASPARC3: | |
8303 | if (GET_MODE (x) == SFmode) | |
8304 | return COSTS_N_INSNS (17); | |
8305 | else | |
8306 | return COSTS_N_INSNS (20); | |
8307 | ||
8308 | case PROCESSOR_SUPERSPARC: | |
8309 | if (GET_MODE (x) == SFmode) | |
8310 | return COSTS_N_INSNS (6); | |
8311 | else | |
8312 | return COSTS_N_INSNS (9); | |
8313 | ||
8314 | case PROCESSOR_HYPERSPARC: | |
8315 | case PROCESSOR_SPARCLITE86X: | |
8316 | if (GET_MODE (x) == SFmode) | |
8317 | return COSTS_N_INSNS (8); | |
8318 | else | |
8319 | return COSTS_N_INSNS (12); | |
8320 | ||
8321 | default: | |
8322 | return COSTS_N_INSNS (7); | |
8323 | } | |
8324 | } | |
8325 | ||
2ce04b6b DM |
8326 | if (sparc_cpu == PROCESSOR_ULTRASPARC) |
8327 | return (GET_MODE (x) == DImode ? | |
8328 | COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); | |
8329 | if (sparc_cpu == PROCESSOR_ULTRASPARC3) | |
8330 | return (GET_MODE (x) == DImode ? | |
8331 | COSTS_N_INSNS (71) : COSTS_N_INSNS (40)); | |
8332 | return COSTS_N_INSNS (25); | |
8333 | ||
214c6394 DM |
8334 | case IF_THEN_ELSE: |
8335 | /* Conditional moves. */ | |
8336 | switch (sparc_cpu) | |
8337 | { | |
8338 | case PROCESSOR_ULTRASPARC: | |
8339 | return COSTS_N_INSNS (2); | |
8340 | ||
8341 | case PROCESSOR_ULTRASPARC3: | |
8342 | if (FLOAT_MODE_P (GET_MODE (x))) | |
8343 | return COSTS_N_INSNS (3); | |
8344 | else | |
8345 | return COSTS_N_INSNS (2); | |
8346 | ||
8347 | default: | |
8348 | return COSTS_N_INSNS (1); | |
8349 | } | |
8350 | ||
8351 | case MEM: | |
8352 | /* If outer-code is SIGN/ZERO extension we have to subtract | |
8353 | out COSTS_N_INSNS (1) from whatever we return in determining | |
8354 | the cost. */ | |
8355 | switch (sparc_cpu) | |
8356 | { | |
8357 | case PROCESSOR_ULTRASPARC: | |
8358 | if (outer_code == ZERO_EXTEND) | |
8359 | return COSTS_N_INSNS (1); | |
8360 | else | |
8361 | return COSTS_N_INSNS (2); | |
8362 | ||
8363 | case PROCESSOR_ULTRASPARC3: | |
8364 | if (outer_code == ZERO_EXTEND) | |
8365 | { | |
8366 | if (GET_MODE (x) == QImode | |
8367 | || GET_MODE (x) == HImode | |
8368 | || outer_code == SIGN_EXTEND) | |
8369 | return COSTS_N_INSNS (2); | |
8370 | else | |
8371 | return COSTS_N_INSNS (1); | |
8372 | } | |
8373 | else | |
8374 | { | |
8375 | /* This handles sign extension (3 cycles) | |
8376 | and everything else (2 cycles). */ | |
8377 | return COSTS_N_INSNS (2); | |
8378 | } | |
8379 | ||
8380 | case PROCESSOR_SUPERSPARC: | |
8381 | if (FLOAT_MODE_P (GET_MODE (x)) | |
8382 | || outer_code == ZERO_EXTEND | |
8383 | || outer_code == SIGN_EXTEND) | |
8384 | return COSTS_N_INSNS (0); | |
8385 | else | |
8386 | return COSTS_N_INSNS (1); | |
8387 | ||
8388 | case PROCESSOR_TSC701: | |
8389 | if (outer_code == ZERO_EXTEND | |
8390 | || outer_code == SIGN_EXTEND) | |
8391 | return COSTS_N_INSNS (2); | |
8392 | else | |
8393 | return COSTS_N_INSNS (3); | |
8394 | ||
8395 | case PROCESSOR_CYPRESS: | |
8396 | if (outer_code == ZERO_EXTEND | |
8397 | || outer_code == SIGN_EXTEND) | |
8398 | return COSTS_N_INSNS (1); | |
8399 | else | |
8400 | return COSTS_N_INSNS (2); | |
8401 | ||
8402 | case PROCESSOR_HYPERSPARC: | |
8403 | case PROCESSOR_SPARCLITE86X: | |
8404 | default: | |
8405 | if (outer_code == ZERO_EXTEND | |
8406 | || outer_code == SIGN_EXTEND) | |
8407 | return COSTS_N_INSNS (0); | |
8408 | else | |
8409 | return COSTS_N_INSNS (1); | |
8410 | } | |
2ce04b6b DM |
8411 | |
8412 | case CONST_INT: | |
8413 | if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000) | |
8414 | return 0; | |
8415 | ||
8416 | /* fallthru */ | |
8417 | case HIGH: | |
8418 | return 2; | |
8419 | ||
8420 | case CONST: | |
8421 | case LABEL_REF: | |
8422 | case SYMBOL_REF: | |
8423 | return 4; | |
8424 | ||
8425 | case CONST_DOUBLE: | |
8426 | if (GET_MODE (x) == DImode) | |
8427 | if ((XINT (x, 3) == 0 | |
8428 | && (unsigned) XINT (x, 2) < 0x1000) | |
8429 | || (XINT (x, 3) == -1 | |
8430 | && XINT (x, 2) < 0 | |
8431 | && XINT (x, 2) >= -0x1000)) | |
8432 | return 0; | |
8433 | return 8; | |
8434 | ||
8435 | default: | |
8436 | abort(); | |
8437 | }; | |
8438 | } |