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c3427c7d | 1 | /* Subroutines for insn-output.c for SPARC. |
cbe34bb5 | 2 | Copyright (C) 1987-2017 Free Software Foundation, Inc. |
ab835497 | 3 | Contributed by Michael Tiemann (tiemann@cygnus.com) |
c3427c7d | 4 | 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
61a55e8b | 5 | at Cygnus Support. |
ab835497 | 6 | |
4d8af13f | 7 | This file is part of GCC. |
ab835497 | 8 | |
4d8af13f | 9 | GCC is free software; you can redistribute it and/or modify |
ab835497 | 10 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 11 | the Free Software Foundation; either version 3, or (at your option) |
ab835497 RK |
12 | any later version. |
13 | ||
4d8af13f | 14 | GCC is distributed in the hope that it will be useful, |
ab835497 RK |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
ab835497 | 22 | |
ab835497 | 23 | #include "config.h" |
284d86e9 | 24 | #include "system.h" |
4977bab6 | 25 | #include "coretypes.h" |
c7131fb2 | 26 | #include "backend.h" |
e11c4407 AM |
27 | #include "target.h" |
28 | #include "rtl.h" | |
210aa14a | 29 | #include "tree.h" |
e73cf9a2 | 30 | #include "memmodel.h" |
c7131fb2 | 31 | #include "gimple.h" |
c7131fb2 | 32 | #include "df.h" |
e11c4407 AM |
33 | #include "tm_p.h" |
34 | #include "stringpool.h" | |
314e6352 | 35 | #include "attribs.h" |
e11c4407 AM |
36 | #include "expmed.h" |
37 | #include "optabs.h" | |
38 | #include "regs.h" | |
39 | #include "emit-rtl.h" | |
40 | #include "recog.h" | |
41 | #include "diagnostic-core.h" | |
c7131fb2 | 42 | #include "alias.h" |
40e23961 | 43 | #include "fold-const.h" |
d8a2d370 DN |
44 | #include "stor-layout.h" |
45 | #include "calls.h" | |
46 | #include "varasm.h" | |
ab835497 RK |
47 | #include "output.h" |
48 | #include "insn-attr.h" | |
36566b39 | 49 | #include "explow.h" |
ab835497 | 50 | #include "expr.h" |
e78d8e51 | 51 | #include "debug.h" |
677f3fa8 | 52 | #include "common/common-target.h" |
45b0be94 | 53 | #include "gimplify.h" |
16f59241 | 54 | #include "langhooks.h" |
58e6223e | 55 | #include "reload.h" |
47eb5b32 | 56 | #include "params.h" |
0ea8a6f9 | 57 | #include "tree-pass.h" |
5ee5b32c | 58 | #include "context.h" |
9b2b7279 | 59 | #include "builtins.h" |
ab835497 | 60 | |
994c5d85 | 61 | /* This file should be included last. */ |
d58627a0 RS |
62 | #include "target-def.h" |
63 | ||
18df6de9 | 64 | /* Processor costs */ |
f0237267 DM |
65 | |
66 | struct processor_costs { | |
67 | /* Integer load */ | |
68 | const int int_load; | |
69 | ||
70 | /* Integer signed load */ | |
71 | const int int_sload; | |
72 | ||
73 | /* Integer zeroed load */ | |
74 | const int int_zload; | |
75 | ||
76 | /* Float load */ | |
77 | const int float_load; | |
78 | ||
79 | /* fmov, fneg, fabs */ | |
80 | const int float_move; | |
81 | ||
82 | /* fadd, fsub */ | |
83 | const int float_plusminus; | |
84 | ||
85 | /* fcmp */ | |
86 | const int float_cmp; | |
87 | ||
88 | /* fmov, fmovr */ | |
89 | const int float_cmove; | |
90 | ||
91 | /* fmul */ | |
92 | const int float_mul; | |
93 | ||
94 | /* fdivs */ | |
95 | const int float_div_sf; | |
96 | ||
97 | /* fdivd */ | |
98 | const int float_div_df; | |
99 | ||
100 | /* fsqrts */ | |
101 | const int float_sqrt_sf; | |
102 | ||
103 | /* fsqrtd */ | |
104 | const int float_sqrt_df; | |
105 | ||
106 | /* umul/smul */ | |
107 | const int int_mul; | |
108 | ||
109 | /* mulX */ | |
110 | const int int_mulX; | |
111 | ||
112 | /* integer multiply cost for each bit set past the most | |
113 | significant 3, so the formula for multiply cost becomes: | |
114 | ||
115 | if (rs1 < 0) | |
116 | highest_bit = highest_clear_bit(rs1); | |
117 | else | |
118 | highest_bit = highest_set_bit(rs1); | |
119 | if (highest_bit < 3) | |
120 | highest_bit = 3; | |
121 | cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor); | |
122 | ||
123 | A value of zero indicates that the multiply costs is fixed, | |
124 | and not variable. */ | |
125 | const int int_mul_bit_factor; | |
126 | ||
127 | /* udiv/sdiv */ | |
128 | const int int_div; | |
129 | ||
130 | /* divX */ | |
131 | const int int_divX; | |
132 | ||
133 | /* movcc, movr */ | |
134 | const int int_cmove; | |
135 | ||
136 | /* penalty for shifts, due to scheduling rules etc. */ | |
137 | const int shift_penalty; | |
138 | }; | |
139 | ||
18df6de9 DM |
140 | static const |
141 | struct processor_costs cypress_costs = { | |
ffe384ff DM |
142 | COSTS_N_INSNS (2), /* int load */ |
143 | COSTS_N_INSNS (2), /* int signed load */ | |
144 | COSTS_N_INSNS (2), /* int zeroed load */ | |
145 | COSTS_N_INSNS (2), /* float load */ | |
146 | COSTS_N_INSNS (5), /* fmov, fneg, fabs */ | |
147 | COSTS_N_INSNS (5), /* fadd, fsub */ | |
148 | COSTS_N_INSNS (1), /* fcmp */ | |
149 | COSTS_N_INSNS (1), /* fmov, fmovr */ | |
150 | COSTS_N_INSNS (7), /* fmul */ | |
151 | COSTS_N_INSNS (37), /* fdivs */ | |
152 | COSTS_N_INSNS (37), /* fdivd */ | |
153 | COSTS_N_INSNS (63), /* fsqrts */ | |
154 | COSTS_N_INSNS (63), /* fsqrtd */ | |
155 | COSTS_N_INSNS (1), /* imul */ | |
156 | COSTS_N_INSNS (1), /* imulX */ | |
18df6de9 | 157 | 0, /* imul bit factor */ |
ffe384ff DM |
158 | COSTS_N_INSNS (1), /* idiv */ |
159 | COSTS_N_INSNS (1), /* idivX */ | |
160 | COSTS_N_INSNS (1), /* movcc/movr */ | |
18df6de9 DM |
161 | 0, /* shift penalty */ |
162 | }; | |
163 | ||
164 | static const | |
165 | struct processor_costs supersparc_costs = { | |
ffe384ff DM |
166 | COSTS_N_INSNS (1), /* int load */ |
167 | COSTS_N_INSNS (1), /* int signed load */ | |
168 | COSTS_N_INSNS (1), /* int zeroed load */ | |
169 | COSTS_N_INSNS (0), /* float load */ | |
170 | COSTS_N_INSNS (3), /* fmov, fneg, fabs */ | |
171 | COSTS_N_INSNS (3), /* fadd, fsub */ | |
172 | COSTS_N_INSNS (3), /* fcmp */ | |
173 | COSTS_N_INSNS (1), /* fmov, fmovr */ | |
174 | COSTS_N_INSNS (3), /* fmul */ | |
175 | COSTS_N_INSNS (6), /* fdivs */ | |
176 | COSTS_N_INSNS (9), /* fdivd */ | |
177 | COSTS_N_INSNS (12), /* fsqrts */ | |
178 | COSTS_N_INSNS (12), /* fsqrtd */ | |
179 | COSTS_N_INSNS (4), /* imul */ | |
180 | COSTS_N_INSNS (4), /* imulX */ | |
18df6de9 | 181 | 0, /* imul bit factor */ |
ffe384ff DM |
182 | COSTS_N_INSNS (4), /* idiv */ |
183 | COSTS_N_INSNS (4), /* idivX */ | |
184 | COSTS_N_INSNS (1), /* movcc/movr */ | |
18df6de9 DM |
185 | 1, /* shift penalty */ |
186 | }; | |
187 | ||
188 | static const | |
189 | struct processor_costs hypersparc_costs = { | |
ffe384ff DM |
190 | COSTS_N_INSNS (1), /* int load */ |
191 | COSTS_N_INSNS (1), /* int signed load */ | |
192 | COSTS_N_INSNS (1), /* int zeroed load */ | |
193 | COSTS_N_INSNS (1), /* float load */ | |
194 | COSTS_N_INSNS (1), /* fmov, fneg, fabs */ | |
195 | COSTS_N_INSNS (1), /* fadd, fsub */ | |
196 | COSTS_N_INSNS (1), /* fcmp */ | |
197 | COSTS_N_INSNS (1), /* fmov, fmovr */ | |
198 | COSTS_N_INSNS (1), /* fmul */ | |
199 | COSTS_N_INSNS (8), /* fdivs */ | |
200 | COSTS_N_INSNS (12), /* fdivd */ | |
201 | COSTS_N_INSNS (17), /* fsqrts */ | |
202 | COSTS_N_INSNS (17), /* fsqrtd */ | |
203 | COSTS_N_INSNS (17), /* imul */ | |
204 | COSTS_N_INSNS (17), /* imulX */ | |
18df6de9 | 205 | 0, /* imul bit factor */ |
ffe384ff DM |
206 | COSTS_N_INSNS (17), /* idiv */ |
207 | COSTS_N_INSNS (17), /* idivX */ | |
208 | COSTS_N_INSNS (1), /* movcc/movr */ | |
18df6de9 DM |
209 | 0, /* shift penalty */ |
210 | }; | |
211 | ||
07981468 KE |
212 | static const |
213 | struct processor_costs leon_costs = { | |
214 | COSTS_N_INSNS (1), /* int load */ | |
215 | COSTS_N_INSNS (1), /* int signed load */ | |
216 | COSTS_N_INSNS (1), /* int zeroed load */ | |
217 | COSTS_N_INSNS (1), /* float load */ | |
218 | COSTS_N_INSNS (1), /* fmov, fneg, fabs */ | |
219 | COSTS_N_INSNS (1), /* fadd, fsub */ | |
220 | COSTS_N_INSNS (1), /* fcmp */ | |
221 | COSTS_N_INSNS (1), /* fmov, fmovr */ | |
222 | COSTS_N_INSNS (1), /* fmul */ | |
223 | COSTS_N_INSNS (15), /* fdivs */ | |
224 | COSTS_N_INSNS (15), /* fdivd */ | |
225 | COSTS_N_INSNS (23), /* fsqrts */ | |
226 | COSTS_N_INSNS (23), /* fsqrtd */ | |
227 | COSTS_N_INSNS (5), /* imul */ | |
228 | COSTS_N_INSNS (5), /* imulX */ | |
229 | 0, /* imul bit factor */ | |
230 | COSTS_N_INSNS (5), /* idiv */ | |
231 | COSTS_N_INSNS (5), /* idivX */ | |
232 | COSTS_N_INSNS (1), /* movcc/movr */ | |
233 | 0, /* shift penalty */ | |
234 | }; | |
235 | ||
38ae58ca EB |
236 | static const |
237 | struct processor_costs leon3_costs = { | |
238 | COSTS_N_INSNS (1), /* int load */ | |
239 | COSTS_N_INSNS (1), /* int signed load */ | |
240 | COSTS_N_INSNS (1), /* int zeroed load */ | |
241 | COSTS_N_INSNS (1), /* float load */ | |
242 | COSTS_N_INSNS (1), /* fmov, fneg, fabs */ | |
243 | COSTS_N_INSNS (1), /* fadd, fsub */ | |
244 | COSTS_N_INSNS (1), /* fcmp */ | |
245 | COSTS_N_INSNS (1), /* fmov, fmovr */ | |
246 | COSTS_N_INSNS (1), /* fmul */ | |
247 | COSTS_N_INSNS (14), /* fdivs */ | |
248 | COSTS_N_INSNS (15), /* fdivd */ | |
249 | COSTS_N_INSNS (22), /* fsqrts */ | |
250 | COSTS_N_INSNS (23), /* fsqrtd */ | |
251 | COSTS_N_INSNS (5), /* imul */ | |
252 | COSTS_N_INSNS (5), /* imulX */ | |
253 | 0, /* imul bit factor */ | |
254 | COSTS_N_INSNS (35), /* idiv */ | |
255 | COSTS_N_INSNS (35), /* idivX */ | |
256 | COSTS_N_INSNS (1), /* movcc/movr */ | |
257 | 0, /* shift penalty */ | |
258 | }; | |
259 | ||
18df6de9 DM |
260 | static const |
261 | struct processor_costs sparclet_costs = { | |
ffe384ff DM |
262 | COSTS_N_INSNS (3), /* int load */ |
263 | COSTS_N_INSNS (3), /* int signed load */ | |
264 | COSTS_N_INSNS (1), /* int zeroed load */ | |
265 | COSTS_N_INSNS (1), /* float load */ | |
266 | COSTS_N_INSNS (1), /* fmov, fneg, fabs */ | |
267 | COSTS_N_INSNS (1), /* fadd, fsub */ | |
268 | COSTS_N_INSNS (1), /* fcmp */ | |
269 | COSTS_N_INSNS (1), /* fmov, fmovr */ | |
270 | COSTS_N_INSNS (1), /* fmul */ | |
271 | COSTS_N_INSNS (1), /* fdivs */ | |
272 | COSTS_N_INSNS (1), /* fdivd */ | |
273 | COSTS_N_INSNS (1), /* fsqrts */ | |
274 | COSTS_N_INSNS (1), /* fsqrtd */ | |
275 | COSTS_N_INSNS (5), /* imul */ | |
276 | COSTS_N_INSNS (5), /* imulX */ | |
18df6de9 | 277 | 0, /* imul bit factor */ |
ffe384ff DM |
278 | COSTS_N_INSNS (5), /* idiv */ |
279 | COSTS_N_INSNS (5), /* idivX */ | |
280 | COSTS_N_INSNS (1), /* movcc/movr */ | |
18df6de9 DM |
281 | 0, /* shift penalty */ |
282 | }; | |
283 | ||
284 | static const | |
285 | struct processor_costs ultrasparc_costs = { | |
ffe384ff DM |
286 | COSTS_N_INSNS (2), /* int load */ |
287 | COSTS_N_INSNS (3), /* int signed load */ | |
288 | COSTS_N_INSNS (2), /* int zeroed load */ | |
289 | COSTS_N_INSNS (2), /* float load */ | |
290 | COSTS_N_INSNS (1), /* fmov, fneg, fabs */ | |
291 | COSTS_N_INSNS (4), /* fadd, fsub */ | |
292 | COSTS_N_INSNS (1), /* fcmp */ | |
293 | COSTS_N_INSNS (2), /* fmov, fmovr */ | |
294 | COSTS_N_INSNS (4), /* fmul */ | |
295 | COSTS_N_INSNS (13), /* fdivs */ | |
296 | COSTS_N_INSNS (23), /* fdivd */ | |
297 | COSTS_N_INSNS (13), /* fsqrts */ | |
298 | COSTS_N_INSNS (23), /* fsqrtd */ | |
299 | COSTS_N_INSNS (4), /* imul */ | |
300 | COSTS_N_INSNS (4), /* imulX */ | |
18df6de9 | 301 | 2, /* imul bit factor */ |
ffe384ff DM |
302 | COSTS_N_INSNS (37), /* idiv */ |
303 | COSTS_N_INSNS (68), /* idivX */ | |
304 | COSTS_N_INSNS (2), /* movcc/movr */ | |
18df6de9 DM |
305 | 2, /* shift penalty */ |
306 | }; | |
307 | ||
308 | static const | |
309 | struct processor_costs ultrasparc3_costs = { | |
ffe384ff DM |
310 | COSTS_N_INSNS (2), /* int load */ |
311 | COSTS_N_INSNS (3), /* int signed load */ | |
312 | COSTS_N_INSNS (3), /* int zeroed load */ | |
313 | COSTS_N_INSNS (2), /* float load */ | |
314 | COSTS_N_INSNS (3), /* fmov, fneg, fabs */ | |
315 | COSTS_N_INSNS (4), /* fadd, fsub */ | |
316 | COSTS_N_INSNS (5), /* fcmp */ | |
317 | COSTS_N_INSNS (3), /* fmov, fmovr */ | |
318 | COSTS_N_INSNS (4), /* fmul */ | |
319 | COSTS_N_INSNS (17), /* fdivs */ | |
320 | COSTS_N_INSNS (20), /* fdivd */ | |
321 | COSTS_N_INSNS (20), /* fsqrts */ | |
322 | COSTS_N_INSNS (29), /* fsqrtd */ | |
323 | COSTS_N_INSNS (6), /* imul */ | |
324 | COSTS_N_INSNS (6), /* imulX */ | |
18df6de9 | 325 | 0, /* imul bit factor */ |
ffe384ff DM |
326 | COSTS_N_INSNS (40), /* idiv */ |
327 | COSTS_N_INSNS (71), /* idivX */ | |
328 | COSTS_N_INSNS (2), /* movcc/movr */ | |
18df6de9 DM |
329 | 0, /* shift penalty */ |
330 | }; | |
331 | ||
4c837a1e DM |
332 | static const |
333 | struct processor_costs niagara_costs = { | |
334 | COSTS_N_INSNS (3), /* int load */ | |
335 | COSTS_N_INSNS (3), /* int signed load */ | |
336 | COSTS_N_INSNS (3), /* int zeroed load */ | |
337 | COSTS_N_INSNS (9), /* float load */ | |
338 | COSTS_N_INSNS (8), /* fmov, fneg, fabs */ | |
339 | COSTS_N_INSNS (8), /* fadd, fsub */ | |
340 | COSTS_N_INSNS (26), /* fcmp */ | |
341 | COSTS_N_INSNS (8), /* fmov, fmovr */ | |
342 | COSTS_N_INSNS (29), /* fmul */ | |
343 | COSTS_N_INSNS (54), /* fdivs */ | |
344 | COSTS_N_INSNS (83), /* fdivd */ | |
345 | COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */ | |
346 | COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */ | |
347 | COSTS_N_INSNS (11), /* imul */ | |
348 | COSTS_N_INSNS (11), /* imulX */ | |
349 | 0, /* imul bit factor */ | |
350 | COSTS_N_INSNS (72), /* idiv */ | |
351 | COSTS_N_INSNS (72), /* idivX */ | |
352 | COSTS_N_INSNS (1), /* movcc/movr */ | |
353 | 0, /* shift penalty */ | |
354 | }; | |
355 | ||
9eeaed6e DM |
356 | static const |
357 | struct processor_costs niagara2_costs = { | |
358 | COSTS_N_INSNS (3), /* int load */ | |
359 | COSTS_N_INSNS (3), /* int signed load */ | |
360 | COSTS_N_INSNS (3), /* int zeroed load */ | |
361 | COSTS_N_INSNS (3), /* float load */ | |
362 | COSTS_N_INSNS (6), /* fmov, fneg, fabs */ | |
363 | COSTS_N_INSNS (6), /* fadd, fsub */ | |
364 | COSTS_N_INSNS (6), /* fcmp */ | |
365 | COSTS_N_INSNS (6), /* fmov, fmovr */ | |
366 | COSTS_N_INSNS (6), /* fmul */ | |
367 | COSTS_N_INSNS (19), /* fdivs */ | |
368 | COSTS_N_INSNS (33), /* fdivd */ | |
369 | COSTS_N_INSNS (19), /* fsqrts */ | |
370 | COSTS_N_INSNS (33), /* fsqrtd */ | |
371 | COSTS_N_INSNS (5), /* imul */ | |
372 | COSTS_N_INSNS (5), /* imulX */ | |
373 | 0, /* imul bit factor */ | |
ab0ca06f DM |
374 | COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */ |
375 | COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */ | |
376 | COSTS_N_INSNS (1), /* movcc/movr */ | |
377 | 0, /* shift penalty */ | |
378 | }; | |
379 | ||
380 | static const | |
381 | struct processor_costs niagara3_costs = { | |
382 | COSTS_N_INSNS (3), /* int load */ | |
383 | COSTS_N_INSNS (3), /* int signed load */ | |
384 | COSTS_N_INSNS (3), /* int zeroed load */ | |
385 | COSTS_N_INSNS (3), /* float load */ | |
386 | COSTS_N_INSNS (9), /* fmov, fneg, fabs */ | |
387 | COSTS_N_INSNS (9), /* fadd, fsub */ | |
388 | COSTS_N_INSNS (9), /* fcmp */ | |
389 | COSTS_N_INSNS (9), /* fmov, fmovr */ | |
390 | COSTS_N_INSNS (9), /* fmul */ | |
391 | COSTS_N_INSNS (23), /* fdivs */ | |
392 | COSTS_N_INSNS (37), /* fdivd */ | |
393 | COSTS_N_INSNS (23), /* fsqrts */ | |
394 | COSTS_N_INSNS (37), /* fsqrtd */ | |
395 | COSTS_N_INSNS (9), /* imul */ | |
396 | COSTS_N_INSNS (9), /* imulX */ | |
397 | 0, /* imul bit factor */ | |
398 | COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */ | |
399 | COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */ | |
9eeaed6e DM |
400 | COSTS_N_INSNS (1), /* movcc/movr */ |
401 | 0, /* shift penalty */ | |
402 | }; | |
403 | ||
851634c7 DM |
404 | static const |
405 | struct processor_costs niagara4_costs = { | |
406 | COSTS_N_INSNS (5), /* int load */ | |
407 | COSTS_N_INSNS (5), /* int signed load */ | |
408 | COSTS_N_INSNS (5), /* int zeroed load */ | |
409 | COSTS_N_INSNS (5), /* float load */ | |
410 | COSTS_N_INSNS (11), /* fmov, fneg, fabs */ | |
411 | COSTS_N_INSNS (11), /* fadd, fsub */ | |
412 | COSTS_N_INSNS (11), /* fcmp */ | |
413 | COSTS_N_INSNS (11), /* fmov, fmovr */ | |
414 | COSTS_N_INSNS (11), /* fmul */ | |
415 | COSTS_N_INSNS (24), /* fdivs */ | |
416 | COSTS_N_INSNS (37), /* fdivd */ | |
417 | COSTS_N_INSNS (24), /* fsqrts */ | |
418 | COSTS_N_INSNS (37), /* fsqrtd */ | |
419 | COSTS_N_INSNS (12), /* imul */ | |
420 | COSTS_N_INSNS (12), /* imulX */ | |
421 | 0, /* imul bit factor */ | |
422 | COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */ | |
423 | COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */ | |
424 | COSTS_N_INSNS (1), /* movcc/movr */ | |
425 | 0, /* shift penalty */ | |
426 | }; | |
427 | ||
690f24b7 JM |
428 | static const |
429 | struct processor_costs niagara7_costs = { | |
430 | COSTS_N_INSNS (5), /* int load */ | |
431 | COSTS_N_INSNS (5), /* int signed load */ | |
432 | COSTS_N_INSNS (5), /* int zeroed load */ | |
433 | COSTS_N_INSNS (5), /* float load */ | |
434 | COSTS_N_INSNS (11), /* fmov, fneg, fabs */ | |
435 | COSTS_N_INSNS (11), /* fadd, fsub */ | |
436 | COSTS_N_INSNS (11), /* fcmp */ | |
437 | COSTS_N_INSNS (11), /* fmov, fmovr */ | |
438 | COSTS_N_INSNS (11), /* fmul */ | |
439 | COSTS_N_INSNS (24), /* fdivs */ | |
440 | COSTS_N_INSNS (37), /* fdivd */ | |
441 | COSTS_N_INSNS (24), /* fsqrts */ | |
442 | COSTS_N_INSNS (37), /* fsqrtd */ | |
443 | COSTS_N_INSNS (12), /* imul */ | |
444 | COSTS_N_INSNS (12), /* imulX */ | |
445 | 0, /* imul bit factor */ | |
446 | COSTS_N_INSNS (51), /* idiv, average of 42 - 61 cycle range */ | |
447 | COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */ | |
448 | COSTS_N_INSNS (1), /* movcc/movr */ | |
449 | 0, /* shift penalty */ | |
450 | }; | |
451 | ||
bcc3c3f1 JM |
452 | static const |
453 | struct processor_costs m8_costs = { | |
454 | COSTS_N_INSNS (3), /* int load */ | |
455 | COSTS_N_INSNS (3), /* int signed load */ | |
456 | COSTS_N_INSNS (3), /* int zeroed load */ | |
457 | COSTS_N_INSNS (3), /* float load */ | |
458 | COSTS_N_INSNS (9), /* fmov, fneg, fabs */ | |
459 | COSTS_N_INSNS (9), /* fadd, fsub */ | |
460 | COSTS_N_INSNS (9), /* fcmp */ | |
461 | COSTS_N_INSNS (9), /* fmov, fmovr */ | |
462 | COSTS_N_INSNS (9), /* fmul */ | |
463 | COSTS_N_INSNS (26), /* fdivs */ | |
464 | COSTS_N_INSNS (30), /* fdivd */ | |
465 | COSTS_N_INSNS (33), /* fsqrts */ | |
466 | COSTS_N_INSNS (41), /* fsqrtd */ | |
467 | COSTS_N_INSNS (12), /* imul */ | |
468 | COSTS_N_INSNS (10), /* imulX */ | |
469 | 0, /* imul bit factor */ | |
470 | COSTS_N_INSNS (57), /* udiv/sdiv */ | |
471 | COSTS_N_INSNS (30), /* udivx/sdivx */ | |
472 | COSTS_N_INSNS (1), /* movcc/movr */ | |
473 | 0, /* shift penalty */ | |
474 | }; | |
475 | ||
f0237267 | 476 | static const struct processor_costs *sparc_costs = &cypress_costs; |
18df6de9 | 477 | |
9ac617d4 EB |
478 | #ifdef HAVE_AS_RELAX_OPTION |
479 | /* If 'as' and 'ld' are relaxing tail call insns into branch always, use | |
480 | "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized. | |
481 | With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if | |
482 | somebody does not branch between the sethi and jmp. */ | |
6244b14e | 483 | #define LEAF_SIBCALL_SLOT_RESERVED_P 1 |
9ac617d4 | 484 | #else |
6244b14e EB |
485 | #define LEAF_SIBCALL_SLOT_RESERVED_P \ |
486 | ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic) | |
9ac617d4 EB |
487 | #endif |
488 | ||
563c12b0 RH |
489 | /* Vector to say how input registers are mapped to output registers. |
490 | HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to | |
491 | eliminate it. You must use -fomit-frame-pointer to get that. */ | |
d70e94ec | 492 | char leaf_reg_remap[] = |
ab835497 RK |
493 | { 0, 1, 2, 3, 4, 5, 6, 7, |
494 | -1, -1, -1, -1, -1, -1, 14, -1, | |
495 | -1, -1, -1, -1, -1, -1, -1, -1, | |
496 | 8, 9, 10, 11, 12, 13, -1, 15, | |
497 | ||
498 | 32, 33, 34, 35, 36, 37, 38, 39, | |
499 | 40, 41, 42, 43, 44, 45, 46, 47, | |
500 | 48, 49, 50, 51, 52, 53, 54, 55, | |
61a55e8b DE |
501 | 56, 57, 58, 59, 60, 61, 62, 63, |
502 | 64, 65, 66, 67, 68, 69, 70, 71, | |
503 | 72, 73, 74, 75, 76, 77, 78, 79, | |
504 | 80, 81, 82, 83, 84, 85, 86, 87, | |
505 | 88, 89, 90, 91, 92, 93, 94, 95, | |
10b859c0 | 506 | 96, 97, 98, 99, 100, 101, 102}; |
ab835497 | 507 | |
7d167afd JJ |
508 | /* Vector, indexed by hard register number, which contains 1 |
509 | for a register that is allowable in a candidate for leaf | |
510 | function treatment. */ | |
511 | char sparc_leaf_regs[] = | |
512 | { 1, 1, 1, 1, 1, 1, 1, 1, | |
513 | 0, 0, 0, 0, 0, 0, 1, 0, | |
514 | 0, 0, 0, 0, 0, 0, 0, 0, | |
515 | 1, 1, 1, 1, 1, 1, 0, 1, | |
516 | 1, 1, 1, 1, 1, 1, 1, 1, | |
517 | 1, 1, 1, 1, 1, 1, 1, 1, | |
518 | 1, 1, 1, 1, 1, 1, 1, 1, | |
519 | 1, 1, 1, 1, 1, 1, 1, 1, | |
520 | 1, 1, 1, 1, 1, 1, 1, 1, | |
521 | 1, 1, 1, 1, 1, 1, 1, 1, | |
522 | 1, 1, 1, 1, 1, 1, 1, 1, | |
523 | 1, 1, 1, 1, 1, 1, 1, 1, | |
10b859c0 | 524 | 1, 1, 1, 1, 1, 1, 1}; |
7d167afd | 525 | |
d1b38208 | 526 | struct GTY(()) machine_function |
5751a10b | 527 | { |
b11b0904 EB |
528 | /* Size of the frame of the function. */ |
529 | HOST_WIDE_INT frame_size; | |
530 | ||
531 | /* Size of the frame of the function minus the register window save area | |
532 | and the outgoing argument area. */ | |
533 | HOST_WIDE_INT apparent_frame_size; | |
534 | ||
535 | /* Register we pretend the frame pointer is allocated to. Normally, this | |
536 | is %fp, but if we are in a leaf procedure, this is (%sp + offset). We | |
537 | record "offset" separately as it may be too big for (reg + disp). */ | |
538 | rtx frame_base_reg; | |
539 | HOST_WIDE_INT frame_base_offset; | |
540 | ||
b11b0904 EB |
541 | /* Number of global or FP registers to be saved (as 4-byte quantities). */ |
542 | int n_global_fp_regs; | |
543 | ||
5be9b7a1 EB |
544 | /* True if the current function is leaf and uses only leaf regs, |
545 | so that the SPARC leaf function optimization can be applied. | |
416ff32e | 546 | Private version of crtl->uses_only_leaf_regs, see |
5be9b7a1 EB |
547 | sparc_expand_prologue for the rationale. */ |
548 | int leaf_function_p; | |
549 | ||
b11b0904 EB |
550 | /* True if the prologue saves local or in registers. */ |
551 | bool save_local_in_regs_p; | |
552 | ||
5be9b7a1 EB |
553 | /* True if the data calculated by sparc_expand_prologue are valid. */ |
554 | bool prologue_data_valid_p; | |
5751a10b JJ |
555 | }; |
556 | ||
b11b0904 EB |
557 | #define sparc_frame_size cfun->machine->frame_size |
558 | #define sparc_apparent_frame_size cfun->machine->apparent_frame_size | |
559 | #define sparc_frame_base_reg cfun->machine->frame_base_reg | |
560 | #define sparc_frame_base_offset cfun->machine->frame_base_offset | |
561 | #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs | |
562 | #define sparc_leaf_function_p cfun->machine->leaf_function_p | |
563 | #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p | |
564 | #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p | |
ab835497 | 565 | |
4e5b002b EB |
566 | /* 1 if the next opcode is to be specially indented. */ |
567 | int sparc_indent_opcode = 0; | |
568 | ||
c5387660 | 569 | static void sparc_option_override (void); |
e80d5f80 | 570 | static void sparc_init_modes (void); |
ef4bddc2 | 571 | static int function_arg_slotno (const CUMULATIVE_ARGS *, machine_mode, |
9adafb9f | 572 | const_tree, bool, bool, int *, int *); |
e80d5f80 | 573 | |
b505225b TS |
574 | static int supersparc_adjust_cost (rtx_insn *, int, rtx_insn *, int); |
575 | static int hypersparc_adjust_cost (rtx_insn *, int, rtx_insn *, int); | |
e80d5f80 | 576 | |
d9816849 EB |
577 | static void sparc_emit_set_const32 (rtx, rtx); |
578 | static void sparc_emit_set_const64 (rtx, rtx); | |
e80d5f80 KG |
579 | static void sparc_output_addr_vec (rtx); |
580 | static void sparc_output_addr_diff_vec (rtx); | |
581 | static void sparc_output_deferred_case_vectors (void); | |
ef4bddc2 RS |
582 | static bool sparc_legitimate_address_p (machine_mode, rtx, bool); |
583 | static bool sparc_legitimate_constant_p (machine_mode, rtx); | |
3e2cc1d1 | 584 | static rtx sparc_builtin_saveregs (void); |
e80d5f80 KG |
585 | static int epilogue_renumber (rtx *, int); |
586 | static bool sparc_assemble_integer (rtx, unsigned int, int); | |
b32d5189 | 587 | static int set_extends (rtx_insn *); |
42776416 RS |
588 | static void sparc_asm_function_prologue (FILE *); |
589 | static void sparc_asm_function_epilogue (FILE *); | |
7e32e652 | 590 | #ifdef TARGET_SOLARIS |
d1ced155 EB |
591 | static void sparc_solaris_elf_asm_named_section (const char *, unsigned int, |
592 | tree) ATTRIBUTE_UNUSED; | |
7e32e652 | 593 | #endif |
b505225b | 594 | static int sparc_adjust_cost (rtx_insn *, int, rtx_insn *, int, unsigned int); |
e80d5f80 KG |
595 | static int sparc_issue_rate (void); |
596 | static void sparc_sched_init (FILE *, int, int); | |
e80d5f80 KG |
597 | static int sparc_use_sched_lookahead (void); |
598 | ||
599 | static void emit_soft_tfmode_libcall (const char *, int, rtx *); | |
600 | static void emit_soft_tfmode_binop (enum rtx_code, rtx *); | |
601 | static void emit_soft_tfmode_unop (enum rtx_code, rtx *); | |
602 | static void emit_soft_tfmode_cvt (enum rtx_code, rtx *); | |
603 | static void emit_hard_tfmode_operation (enum rtx_code, rtx *); | |
604 | ||
605 | static bool sparc_function_ok_for_sibcall (tree, tree); | |
c15c90bb | 606 | static void sparc_init_libfuncs (void); |
16f59241 | 607 | static void sparc_init_builtins (void); |
fde66fde | 608 | static void sparc_fpu_init_builtins (void); |
16f59241 | 609 | static void sparc_vis_init_builtins (void); |
fde66fde | 610 | static tree sparc_builtin_decl (unsigned, bool); |
ef4bddc2 | 611 | static rtx sparc_expand_builtin (tree, rtx, rtx, machine_mode, int); |
f311c3b4 | 612 | static tree sparc_fold_builtin (tree, int, tree *, bool); |
e80d5f80 KG |
613 | static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
614 | HOST_WIDE_INT, tree); | |
3101faab KG |
615 | static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT, |
616 | HOST_WIDE_INT, const_tree); | |
5751a10b | 617 | static struct machine_function * sparc_init_machine_status (void); |
ef4bddc2 | 618 | static bool sparc_cannot_force_const_mem (machine_mode, rtx); |
5751a10b JJ |
619 | static rtx sparc_tls_get_addr (void); |
620 | static rtx sparc_tls_got (void); | |
ef4bddc2 | 621 | static int sparc_register_move_cost (machine_mode, |
32257ddc | 622 | reg_class_t, reg_class_t); |
e548c9df | 623 | static bool sparc_rtx_costs (rtx, machine_mode, int, int, int *, bool); |
bf44d792 | 624 | static rtx sparc_function_value (const_tree, const_tree, bool); |
ef4bddc2 | 625 | static rtx sparc_libcall_value (machine_mode, const_rtx); |
bf44d792 | 626 | static bool sparc_function_value_regno_p (const unsigned int); |
3e2cc1d1 | 627 | static rtx sparc_struct_value_rtx (tree, int); |
ef4bddc2 | 628 | static machine_mode sparc_promote_function_mode (const_tree, machine_mode, |
cde0f3fd | 629 | int *, const_tree, int); |
586de218 | 630 | static bool sparc_return_in_memory (const_tree, const_tree); |
d5cc9181 | 631 | static bool sparc_strict_argument_naming (cumulative_args_t); |
d7bd8aeb | 632 | static void sparc_va_start (tree, rtx); |
726a989a | 633 | static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *); |
ef4bddc2 | 634 | static bool sparc_vector_mode_supported_p (machine_mode); |
208384fd | 635 | static bool sparc_tls_referenced_p (rtx); |
58e6223e EB |
636 | static rtx sparc_legitimize_tls_address (rtx); |
637 | static rtx sparc_legitimize_pic_address (rtx, rtx); | |
ef4bddc2 | 638 | static rtx sparc_legitimize_address (rtx, rtx, machine_mode); |
8e7a6ed6 | 639 | static rtx sparc_delegitimize_address (rtx); |
5bfed9a9 | 640 | static bool sparc_mode_dependent_address_p (const_rtx, addr_space_t); |
d5cc9181 | 641 | static bool sparc_pass_by_reference (cumulative_args_t, |
ef4bddc2 | 642 | machine_mode, const_tree, bool); |
d5cc9181 | 643 | static void sparc_function_arg_advance (cumulative_args_t, |
ef4bddc2 | 644 | machine_mode, const_tree, bool); |
d5cc9181 | 645 | static rtx sparc_function_arg_1 (cumulative_args_t, |
ef4bddc2 | 646 | machine_mode, const_tree, bool, bool); |
d5cc9181 | 647 | static rtx sparc_function_arg (cumulative_args_t, |
ef4bddc2 | 648 | machine_mode, const_tree, bool); |
d5cc9181 | 649 | static rtx sparc_function_incoming_arg (cumulative_args_t, |
ef4bddc2 | 650 | machine_mode, const_tree, bool); |
76b0cbf8 | 651 | static pad_direction sparc_function_arg_padding (machine_mode, const_tree); |
ef4bddc2 | 652 | static unsigned int sparc_function_arg_boundary (machine_mode, |
c2ed6cf8 | 653 | const_tree); |
d5cc9181 | 654 | static int sparc_arg_partial_bytes (cumulative_args_t, |
ef4bddc2 | 655 | machine_mode, tree, bool); |
fdbe66f2 | 656 | static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
5e77eb53 | 657 | static void sparc_file_end (void); |
b52b1749 | 658 | static bool sparc_frame_pointer_required (void); |
7b5cbb57 | 659 | static bool sparc_can_eliminate (const int, const int); |
bc6d3f91 | 660 | static rtx sparc_builtin_setjmp_frame_value (void); |
5efd84c5 | 661 | static void sparc_conditional_register_usage (void); |
7269aee7 | 662 | #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING |
3101faab | 663 | static const char *sparc_mangle_type (const_tree); |
7269aee7 | 664 | #endif |
809e78cc | 665 | static void sparc_trampoline_init (rtx, tree, rtx); |
005ba29c | 666 | static machine_mode sparc_preferred_simd_mode (scalar_mode); |
112a861d | 667 | static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass); |
f99bd883 | 668 | static bool sparc_lra_p (void); |
46e43d2b AS |
669 | static bool sparc_print_operand_punct_valid_p (unsigned char); |
670 | static void sparc_print_operand (FILE *, rtx, int); | |
cc8ca59e | 671 | static void sparc_print_operand_address (FILE *, machine_mode, rtx); |
9dc98917 | 672 | static reg_class_t sparc_secondary_reload (bool, rtx, reg_class_t, |
ef4bddc2 | 673 | machine_mode, |
68126bad | 674 | secondary_reload_info *); |
7cc237a6 | 675 | static scalar_int_mode sparc_cstore_mode (enum insn_code icode); |
fde66fde | 676 | static void sparc_atomic_assign_expand_fenv (tree *, tree *, tree *); |
ff7e7ee0 | 677 | static bool sparc_fixed_condition_code_regs (unsigned int *, unsigned int *); |
894d8b41 | 678 | static unsigned int sparc_min_arithmetic_precision (void); |
c43f4279 | 679 | static unsigned int sparc_hard_regno_nregs (unsigned int, machine_mode); |
f939c3e6 | 680 | static bool sparc_hard_regno_mode_ok (unsigned int, machine_mode); |
99e1629f | 681 | static bool sparc_modes_tieable_p (machine_mode, machine_mode); |
f939c3e6 | 682 | |
5a82ecd9 | 683 | \f |
07a43492 | 684 | #ifdef SUBTARGET_ATTRIBUTE_TABLE |
5a82ecd9 ILT |
685 | /* Table of valid machine attributes. */ |
686 | static const struct attribute_spec sparc_attribute_table[] = | |
687 | { | |
62d784f7 KT |
688 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
689 | do_diagnostic } */ | |
5a82ecd9 | 690 | SUBTARGET_ATTRIBUTE_TABLE, |
62d784f7 | 691 | { NULL, 0, 0, false, false, false, NULL, false } |
5a82ecd9 | 692 | }; |
07a43492 | 693 | #endif |
61a55e8b DE |
694 | \f |
695 | /* Option handling. */ | |
696 | ||
a0a301fc DE |
697 | /* Parsed value. */ |
698 | enum cmodel sparc_cmodel; | |
699 | ||
1cb36a98 RH |
700 | char sparc_hard_reg_printed[8]; |
701 | ||
672a6f42 | 702 | /* Initialize the GCC target structure. */ |
301d03af | 703 | |
d1ced155 | 704 | /* The default is to use .half rather than .short for aligned HI objects. */ |
301d03af RS |
705 | #undef TARGET_ASM_ALIGNED_HI_OP |
706 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
301d03af RS |
707 | |
708 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
709 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t" | |
710 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
711 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t" | |
712 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
713 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t" | |
714 | ||
715 | /* The target hook has to handle DI-mode values. */ | |
716 | #undef TARGET_ASM_INTEGER | |
717 | #define TARGET_ASM_INTEGER sparc_assemble_integer | |
718 | ||
08c148a8 | 719 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
9ac617d4 | 720 | #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue |
08c148a8 | 721 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
9ac617d4 | 722 | #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue |
733f53f5 | 723 | |
c237e94a ZW |
724 | #undef TARGET_SCHED_ADJUST_COST |
725 | #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost | |
726 | #undef TARGET_SCHED_ISSUE_RATE | |
727 | #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate | |
c237e94a ZW |
728 | #undef TARGET_SCHED_INIT |
729 | #define TARGET_SCHED_INIT sparc_sched_init | |
fae15c93 VM |
730 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
731 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead | |
c237e94a | 732 | |
4977bab6 ZW |
733 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
734 | #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall | |
735 | ||
c15c90bb ZW |
736 | #undef TARGET_INIT_LIBFUNCS |
737 | #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs | |
16f59241 | 738 | |
506d7b68 PB |
739 | #undef TARGET_LEGITIMIZE_ADDRESS |
740 | #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address | |
8e7a6ed6 EB |
741 | #undef TARGET_DELEGITIMIZE_ADDRESS |
742 | #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address | |
277e2873 AS |
743 | #undef TARGET_MODE_DEPENDENT_ADDRESS_P |
744 | #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p | |
506d7b68 | 745 | |
fde66fde EB |
746 | #undef TARGET_INIT_BUILTINS |
747 | #define TARGET_INIT_BUILTINS sparc_init_builtins | |
748 | #undef TARGET_BUILTIN_DECL | |
749 | #define TARGET_BUILTIN_DECL sparc_builtin_decl | |
16f59241 JM |
750 | #undef TARGET_EXPAND_BUILTIN |
751 | #define TARGET_EXPAND_BUILTIN sparc_expand_builtin | |
8b0096b4 JM |
752 | #undef TARGET_FOLD_BUILTIN |
753 | #define TARGET_FOLD_BUILTIN sparc_fold_builtin | |
c15c90bb | 754 | |
fdbe66f2 | 755 | #if TARGET_TLS |
5751a10b JJ |
756 | #undef TARGET_HAVE_TLS |
757 | #define TARGET_HAVE_TLS true | |
758 | #endif | |
fdbe66f2 | 759 | |
5751a10b JJ |
760 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
761 | #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem | |
762 | ||
c590b625 RH |
763 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
764 | #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk | |
3961e8fe | 765 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
b9bf58e5 | 766 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk |
c590b625 | 767 | |
3c50106f RH |
768 | #undef TARGET_RTX_COSTS |
769 | #define TARGET_RTX_COSTS sparc_rtx_costs | |
dcefdf67 | 770 | #undef TARGET_ADDRESS_COST |
b413068c | 771 | #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0 |
32257ddc AS |
772 | #undef TARGET_REGISTER_MOVE_COST |
773 | #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost | |
3c50106f | 774 | |
cde0f3fd PB |
775 | #undef TARGET_PROMOTE_FUNCTION_MODE |
776 | #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode | |
3e2cc1d1 | 777 | |
bf44d792 AS |
778 | #undef TARGET_FUNCTION_VALUE |
779 | #define TARGET_FUNCTION_VALUE sparc_function_value | |
780 | #undef TARGET_LIBCALL_VALUE | |
781 | #define TARGET_LIBCALL_VALUE sparc_libcall_value | |
782 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
783 | #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p | |
784 | ||
3e2cc1d1 KH |
785 | #undef TARGET_STRUCT_VALUE_RTX |
786 | #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx | |
787 | #undef TARGET_RETURN_IN_MEMORY | |
788 | #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory | |
fe984136 RH |
789 | #undef TARGET_MUST_PASS_IN_STACK |
790 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
8cd5a4e0 RH |
791 | #undef TARGET_PASS_BY_REFERENCE |
792 | #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference | |
78a52f11 RH |
793 | #undef TARGET_ARG_PARTIAL_BYTES |
794 | #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes | |
9adafb9f NF |
795 | #undef TARGET_FUNCTION_ARG_ADVANCE |
796 | #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance | |
797 | #undef TARGET_FUNCTION_ARG | |
798 | #define TARGET_FUNCTION_ARG sparc_function_arg | |
799 | #undef TARGET_FUNCTION_INCOMING_ARG | |
800 | #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg | |
76b0cbf8 RS |
801 | #undef TARGET_FUNCTION_ARG_PADDING |
802 | #define TARGET_FUNCTION_ARG_PADDING sparc_function_arg_padding | |
c2ed6cf8 NF |
803 | #undef TARGET_FUNCTION_ARG_BOUNDARY |
804 | #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary | |
3e2cc1d1 KH |
805 | |
806 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
807 | #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs | |
808 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
809 | #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming | |
810 | ||
d7bd8aeb JJ |
811 | #undef TARGET_EXPAND_BUILTIN_VA_START |
812 | #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start | |
5f393b25 JM |
813 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
814 | #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg | |
815 | ||
c75d6010 JM |
816 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
817 | #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p | |
818 | ||
cc4b5170 RG |
819 | #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE |
820 | #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode | |
26983c22 | 821 | |
07a43492 DJ |
822 | #ifdef SUBTARGET_INSERT_ATTRIBUTES |
823 | #undef TARGET_INSERT_ATTRIBUTES | |
824 | #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES | |
825 | #endif | |
826 | ||
827 | #ifdef SUBTARGET_ATTRIBUTE_TABLE | |
828 | #undef TARGET_ATTRIBUTE_TABLE | |
829 | #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table | |
830 | #endif | |
831 | ||
c5387660 JM |
832 | #undef TARGET_OPTION_OVERRIDE |
833 | #define TARGET_OPTION_OVERRIDE sparc_option_override | |
fe609b0f | 834 | |
1202f33e JJ |
835 | #ifdef TARGET_THREAD_SSP_OFFSET |
836 | #undef TARGET_STACK_PROTECT_GUARD | |
837 | #define TARGET_STACK_PROTECT_GUARD hook_tree_void_null | |
838 | #endif | |
839 | ||
f06fb22b | 840 | #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL) |
fdbe66f2 EB |
841 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL |
842 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel | |
843 | #endif | |
844 | ||
c81739f7 | 845 | #undef TARGET_ASM_FILE_END |
5e77eb53 EB |
846 | #define TARGET_ASM_FILE_END sparc_file_end |
847 | ||
b52b1749 AS |
848 | #undef TARGET_FRAME_POINTER_REQUIRED |
849 | #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required | |
850 | ||
bc6d3f91 EB |
851 | #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE |
852 | #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value | |
853 | ||
7b5cbb57 AS |
854 | #undef TARGET_CAN_ELIMINATE |
855 | #define TARGET_CAN_ELIMINATE sparc_can_eliminate | |
bc6d3f91 | 856 | |
112a861d AS |
857 | #undef TARGET_PREFERRED_RELOAD_CLASS |
858 | #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class | |
7b5cbb57 | 859 | |
9dc98917 DM |
860 | #undef TARGET_SECONDARY_RELOAD |
861 | #define TARGET_SECONDARY_RELOAD sparc_secondary_reload | |
862 | ||
5efd84c5 NF |
863 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
864 | #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage | |
865 | ||
7269aee7 | 866 | #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING |
608063c3 JB |
867 | #undef TARGET_MANGLE_TYPE |
868 | #define TARGET_MANGLE_TYPE sparc_mangle_type | |
7269aee7 AH |
869 | #endif |
870 | ||
d81db636 | 871 | #undef TARGET_LRA_P |
f99bd883 | 872 | #define TARGET_LRA_P sparc_lra_p |
d81db636 | 873 | |
c6c3dba9 PB |
874 | #undef TARGET_LEGITIMATE_ADDRESS_P |
875 | #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p | |
876 | ||
1a627b35 RS |
877 | #undef TARGET_LEGITIMATE_CONSTANT_P |
878 | #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p | |
879 | ||
809e78cc RH |
880 | #undef TARGET_TRAMPOLINE_INIT |
881 | #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init | |
882 | ||
46e43d2b AS |
883 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P |
884 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p | |
885 | #undef TARGET_PRINT_OPERAND | |
886 | #define TARGET_PRINT_OPERAND sparc_print_operand | |
887 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
888 | #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address | |
889 | ||
5a843a13 RH |
890 | /* The value stored by LDSTUB. */ |
891 | #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL | |
892 | #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff | |
893 | ||
42e37616 DM |
894 | #undef TARGET_CSTORE_MODE |
895 | #define TARGET_CSTORE_MODE sparc_cstore_mode | |
896 | ||
fde66fde EB |
897 | #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV |
898 | #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv | |
899 | ||
ff7e7ee0 EB |
900 | #undef TARGET_FIXED_CONDITION_CODE_REGS |
901 | #define TARGET_FIXED_CONDITION_CODE_REGS sparc_fixed_condition_code_regs | |
902 | ||
894d8b41 EB |
903 | #undef TARGET_MIN_ARITHMETIC_PRECISION |
904 | #define TARGET_MIN_ARITHMETIC_PRECISION sparc_min_arithmetic_precision | |
905 | ||
86f98087 EB |
906 | #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS |
907 | #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1 | |
908 | ||
c43f4279 RS |
909 | #undef TARGET_HARD_REGNO_NREGS |
910 | #define TARGET_HARD_REGNO_NREGS sparc_hard_regno_nregs | |
f939c3e6 RS |
911 | #undef TARGET_HARD_REGNO_MODE_OK |
912 | #define TARGET_HARD_REGNO_MODE_OK sparc_hard_regno_mode_ok | |
913 | ||
99e1629f RS |
914 | #undef TARGET_MODES_TIEABLE_P |
915 | #define TARGET_MODES_TIEABLE_P sparc_modes_tieable_p | |
916 | ||
f6897b10 | 917 | struct gcc_target targetm = TARGET_INITIALIZER; |
fe609b0f | 918 | |
38ae58ca EB |
919 | /* Return the memory reference contained in X if any, zero otherwise. */ |
920 | ||
921 | static rtx | |
922 | mem_ref (rtx x) | |
923 | { | |
924 | if (GET_CODE (x) == SIGN_EXTEND || GET_CODE (x) == ZERO_EXTEND) | |
925 | x = XEXP (x, 0); | |
926 | ||
927 | if (MEM_P (x)) | |
928 | return x; | |
929 | ||
930 | return NULL_RTX; | |
931 | } | |
932 | ||
0ea8a6f9 | 933 | /* We use a machine specific pass to enable workarounds for errata. |
6af11d2b | 934 | |
0ea8a6f9 SB |
935 | We need to have the (essentially) final form of the insn stream in order |
936 | to properly detect the various hazards. Therefore, this machine specific | |
6af11d2b | 937 | pass runs as late as possible. */ |
0ea8a6f9 | 938 | |
67091cb4 DC |
939 | /* True if INSN is a md pattern or asm statement. */ |
940 | #define USEFUL_INSN_P(INSN) \ | |
941 | (NONDEBUG_INSN_P (INSN) \ | |
942 | && GET_CODE (PATTERN (INSN)) != USE \ | |
943 | && GET_CODE (PATTERN (INSN)) != CLOBBER) | |
944 | ||
0ea8a6f9 SB |
945 | static unsigned int |
946 | sparc_do_work_around_errata (void) | |
947 | { | |
b32d5189 | 948 | rtx_insn *insn, *next; |
0ea8a6f9 | 949 | |
38ae58ca EB |
950 | /* Force all instructions to be split into their final form. */ |
951 | split_all_insns_noflow (); | |
952 | ||
0ea8a6f9 SB |
953 | /* Now look for specific patterns in the insn stream. */ |
954 | for (insn = get_insns (); insn; insn = next) | |
955 | { | |
956 | bool insert_nop = false; | |
957 | rtx set; | |
958 | ||
38ae58ca | 959 | /* Look into the instruction in a delay slot. */ |
b32d5189 DM |
960 | if (NONJUMP_INSN_P (insn)) |
961 | if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) | |
962 | insn = seq->insn (1); | |
38ae58ca | 963 | |
67091cb4 DC |
964 | /* Look for either of these two sequences: |
965 | ||
966 | Sequence A: | |
967 | 1. store of word size or less (e.g. st / stb / sth / stf) | |
968 | 2. any single instruction that is not a load or store | |
969 | 3. any store instruction (e.g. st / stb / sth / stf / std / stdf) | |
970 | ||
971 | Sequence B: | |
972 | 1. store of double word size (e.g. std / stdf) | |
973 | 2. any store instruction (e.g. st / stb / sth / stf / std / stdf) */ | |
974 | if (sparc_fix_b2bst | |
975 | && NONJUMP_INSN_P (insn) | |
976 | && (set = single_set (insn)) != NULL_RTX | |
977 | && MEM_P (SET_DEST (set))) | |
978 | { | |
979 | /* Sequence B begins with a double-word store. */ | |
980 | bool seq_b = GET_MODE_SIZE (GET_MODE (SET_DEST (set))) == 8; | |
981 | rtx_insn *after; | |
982 | int i; | |
983 | ||
984 | next = next_active_insn (insn); | |
985 | if (!next) | |
986 | break; | |
987 | ||
988 | for (after = next, i = 0; i < 2; i++) | |
989 | { | |
990 | /* Skip empty assembly statements. */ | |
991 | if ((GET_CODE (PATTERN (after)) == UNSPEC_VOLATILE) | |
992 | || (USEFUL_INSN_P (after) | |
993 | && (asm_noperands (PATTERN (after))>=0) | |
994 | && !strcmp (decode_asm_operands (PATTERN (after), | |
995 | NULL, NULL, NULL, | |
996 | NULL, NULL), ""))) | |
997 | after = next_active_insn (after); | |
998 | if (!after) | |
999 | break; | |
1000 | ||
1001 | /* If the insn is a branch, then it cannot be problematic. */ | |
1002 | if (!NONJUMP_INSN_P (after) | |
1003 | || GET_CODE (PATTERN (after)) == SEQUENCE) | |
1004 | break; | |
1005 | ||
1006 | /* Sequence B is only two instructions long. */ | |
1007 | if (seq_b) | |
1008 | { | |
1009 | /* Add NOP if followed by a store. */ | |
1010 | if ((set = single_set (after)) != NULL_RTX | |
1011 | && MEM_P (SET_DEST (set))) | |
1012 | insert_nop = true; | |
1013 | ||
1014 | /* Otherwise it is ok. */ | |
1015 | break; | |
1016 | } | |
1017 | ||
1018 | /* If the second instruction is a load or a store, | |
1019 | then the sequence cannot be problematic. */ | |
1020 | if (i == 0) | |
1021 | { | |
1022 | if (((set = single_set (after)) != NULL_RTX) | |
1023 | && (MEM_P (SET_DEST (set)) || MEM_P (SET_SRC (set)))) | |
1024 | break; | |
1025 | ||
1026 | after = next_active_insn (after); | |
1027 | if (!after) | |
1028 | break; | |
1029 | } | |
1030 | ||
1031 | /* Add NOP if third instruction is a store. */ | |
1032 | if (i == 1 | |
1033 | && ((set = single_set (after)) != NULL_RTX) | |
1034 | && MEM_P (SET_DEST (set))) | |
1035 | insert_nop = true; | |
1036 | } | |
1037 | } | |
1038 | else | |
0ea8a6f9 | 1039 | /* Look for a single-word load into an odd-numbered FP register. */ |
38ae58ca EB |
1040 | if (sparc_fix_at697f |
1041 | && NONJUMP_INSN_P (insn) | |
0ea8a6f9 SB |
1042 | && (set = single_set (insn)) != NULL_RTX |
1043 | && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4 | |
1044 | && MEM_P (SET_SRC (set)) | |
1045 | && REG_P (SET_DEST (set)) | |
1046 | && REGNO (SET_DEST (set)) > 31 | |
1047 | && REGNO (SET_DEST (set)) % 2 != 0) | |
1048 | { | |
1049 | /* The wrong dependency is on the enclosing double register. */ | |
e33da4a1 | 1050 | const unsigned int x = REGNO (SET_DEST (set)) - 1; |
0ea8a6f9 SB |
1051 | unsigned int src1, src2, dest; |
1052 | int code; | |
1053 | ||
0ea8a6f9 | 1054 | next = next_active_insn (insn); |
38ae58ca EB |
1055 | if (!next) |
1056 | break; | |
e33da4a1 EB |
1057 | /* If the insn is a branch, then it cannot be problematic. */ |
1058 | if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE) | |
38ae58ca EB |
1059 | continue; |
1060 | ||
1061 | extract_insn (next); | |
1062 | code = INSN_CODE (next); | |
0ea8a6f9 SB |
1063 | |
1064 | switch (code) | |
1065 | { | |
1066 | case CODE_FOR_adddf3: | |
1067 | case CODE_FOR_subdf3: | |
1068 | case CODE_FOR_muldf3: | |
1069 | case CODE_FOR_divdf3: | |
1070 | dest = REGNO (recog_data.operand[0]); | |
1071 | src1 = REGNO (recog_data.operand[1]); | |
1072 | src2 = REGNO (recog_data.operand[2]); | |
1073 | if (src1 != src2) | |
1074 | { | |
1075 | /* Case [1-4]: | |
1076 | ld [address], %fx+1 | |
1077 | FPOPd %f{x,y}, %f{y,x}, %f{x,y} */ | |
1078 | if ((src1 == x || src2 == x) | |
1079 | && (dest == src1 || dest == src2)) | |
1080 | insert_nop = true; | |
1081 | } | |
1082 | else | |
1083 | { | |
1084 | /* Case 5: | |
1085 | ld [address], %fx+1 | |
1086 | FPOPd %fx, %fx, %fx */ | |
1087 | if (src1 == x | |
1088 | && dest == src1 | |
1089 | && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3)) | |
1090 | insert_nop = true; | |
1091 | } | |
1092 | break; | |
1093 | ||
1094 | case CODE_FOR_sqrtdf2: | |
1095 | dest = REGNO (recog_data.operand[0]); | |
1096 | src1 = REGNO (recog_data.operand[1]); | |
1097 | /* Case 6: | |
1098 | ld [address], %fx+1 | |
1099 | fsqrtd %fx, %fx */ | |
1100 | if (src1 == x && dest == src1) | |
1101 | insert_nop = true; | |
1102 | break; | |
1103 | ||
1104 | default: | |
1105 | break; | |
1106 | } | |
1107 | } | |
38ae58ca EB |
1108 | |
1109 | /* Look for a single-word load into an integer register. */ | |
1110 | else if (sparc_fix_ut699 | |
1111 | && NONJUMP_INSN_P (insn) | |
1112 | && (set = single_set (insn)) != NULL_RTX | |
1113 | && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) <= 4 | |
1114 | && mem_ref (SET_SRC (set)) != NULL_RTX | |
1115 | && REG_P (SET_DEST (set)) | |
1116 | && REGNO (SET_DEST (set)) < 32) | |
1117 | { | |
1118 | /* There is no problem if the second memory access has a data | |
1119 | dependency on the first single-cycle load. */ | |
1120 | rtx x = SET_DEST (set); | |
1121 | ||
38ae58ca EB |
1122 | next = next_active_insn (insn); |
1123 | if (!next) | |
1124 | break; | |
e33da4a1 EB |
1125 | /* If the insn is a branch, then it cannot be problematic. */ |
1126 | if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE) | |
38ae58ca EB |
1127 | continue; |
1128 | ||
1129 | /* Look for a second memory access to/from an integer register. */ | |
1130 | if ((set = single_set (next)) != NULL_RTX) | |
1131 | { | |
1132 | rtx src = SET_SRC (set); | |
1133 | rtx dest = SET_DEST (set); | |
1134 | rtx mem; | |
1135 | ||
1136 | /* LDD is affected. */ | |
1137 | if ((mem = mem_ref (src)) != NULL_RTX | |
1138 | && REG_P (dest) | |
1139 | && REGNO (dest) < 32 | |
1140 | && !reg_mentioned_p (x, XEXP (mem, 0))) | |
1141 | insert_nop = true; | |
1142 | ||
1143 | /* STD is *not* affected. */ | |
e33da4a1 EB |
1144 | else if (MEM_P (dest) |
1145 | && GET_MODE_SIZE (GET_MODE (dest)) <= 4 | |
1146 | && (src == CONST0_RTX (GET_MODE (dest)) | |
38ae58ca EB |
1147 | || (REG_P (src) |
1148 | && REGNO (src) < 32 | |
1149 | && REGNO (src) != REGNO (x))) | |
e33da4a1 | 1150 | && !reg_mentioned_p (x, XEXP (dest, 0))) |
38ae58ca EB |
1151 | insert_nop = true; |
1152 | } | |
1153 | } | |
1154 | ||
7075c792 EB |
1155 | /* Look for a single-word load/operation into an FP register. */ |
1156 | else if (sparc_fix_ut699 | |
1157 | && NONJUMP_INSN_P (insn) | |
1158 | && (set = single_set (insn)) != NULL_RTX | |
1159 | && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4 | |
1160 | && REG_P (SET_DEST (set)) | |
1161 | && REGNO (SET_DEST (set)) > 31) | |
1162 | { | |
1163 | /* Number of instructions in the problematic window. */ | |
1164 | const int n_insns = 4; | |
1165 | /* The problematic combination is with the sibling FP register. */ | |
1166 | const unsigned int x = REGNO (SET_DEST (set)); | |
1167 | const unsigned int y = x ^ 1; | |
e8a54173 | 1168 | rtx_insn *after; |
7075c792 EB |
1169 | int i; |
1170 | ||
1171 | next = next_active_insn (insn); | |
1172 | if (!next) | |
1173 | break; | |
1174 | /* If the insn is a branch, then it cannot be problematic. */ | |
1175 | if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE) | |
1176 | continue; | |
1177 | ||
1178 | /* Look for a second load/operation into the sibling FP register. */ | |
1179 | if (!((set = single_set (next)) != NULL_RTX | |
1180 | && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4 | |
1181 | && REG_P (SET_DEST (set)) | |
1182 | && REGNO (SET_DEST (set)) == y)) | |
1183 | continue; | |
1184 | ||
1185 | /* Look for a (possible) store from the FP register in the next N | |
1186 | instructions, but bail out if it is again modified or if there | |
1187 | is a store from the sibling FP register before this store. */ | |
1188 | for (after = next, i = 0; i < n_insns; i++) | |
1189 | { | |
1190 | bool branch_p; | |
1191 | ||
1192 | after = next_active_insn (after); | |
1193 | if (!after) | |
1194 | break; | |
1195 | ||
1196 | /* This is a branch with an empty delay slot. */ | |
1197 | if (!NONJUMP_INSN_P (after)) | |
1198 | { | |
1199 | if (++i == n_insns) | |
1200 | break; | |
1201 | branch_p = true; | |
e8a54173 | 1202 | after = NULL; |
7075c792 EB |
1203 | } |
1204 | /* This is a branch with a filled delay slot. */ | |
e8a54173 DM |
1205 | else if (rtx_sequence *seq = |
1206 | dyn_cast <rtx_sequence *> (PATTERN (after))) | |
7075c792 EB |
1207 | { |
1208 | if (++i == n_insns) | |
1209 | break; | |
1210 | branch_p = true; | |
e8a54173 | 1211 | after = seq->insn (1); |
7075c792 EB |
1212 | } |
1213 | /* This is a regular instruction. */ | |
1214 | else | |
1215 | branch_p = false; | |
1216 | ||
1217 | if (after && (set = single_set (after)) != NULL_RTX) | |
1218 | { | |
1219 | const rtx src = SET_SRC (set); | |
1220 | const rtx dest = SET_DEST (set); | |
1221 | const unsigned int size = GET_MODE_SIZE (GET_MODE (dest)); | |
1222 | ||
1223 | /* If the FP register is again modified before the store, | |
1224 | then the store isn't affected. */ | |
1225 | if (REG_P (dest) | |
1226 | && (REGNO (dest) == x | |
1227 | || (REGNO (dest) == y && size == 8))) | |
1228 | break; | |
1229 | ||
1230 | if (MEM_P (dest) && REG_P (src)) | |
1231 | { | |
1232 | /* If there is a store from the sibling FP register | |
1233 | before the store, then the store is not affected. */ | |
1234 | if (REGNO (src) == y || (REGNO (src) == x && size == 8)) | |
1235 | break; | |
1236 | ||
1237 | /* Otherwise, the store is affected. */ | |
1238 | if (REGNO (src) == x && size == 4) | |
1239 | { | |
1240 | insert_nop = true; | |
1241 | break; | |
1242 | } | |
1243 | } | |
1244 | } | |
1245 | ||
1246 | /* If we have a branch in the first M instructions, then we | |
1247 | cannot see the (M+2)th instruction so we play safe. */ | |
1248 | if (branch_p && i <= (n_insns - 2)) | |
1249 | { | |
1250 | insert_nop = true; | |
1251 | break; | |
1252 | } | |
1253 | } | |
1254 | } | |
1255 | ||
0ea8a6f9 SB |
1256 | else |
1257 | next = NEXT_INSN (insn); | |
1258 | ||
1259 | if (insert_nop) | |
38ae58ca | 1260 | emit_insn_before (gen_nop (), next); |
0ea8a6f9 | 1261 | } |
38ae58ca | 1262 | |
0ea8a6f9 SB |
1263 | return 0; |
1264 | } | |
1265 | ||
27a4cd48 DM |
1266 | namespace { |
1267 | ||
1268 | const pass_data pass_data_work_around_errata = | |
0ea8a6f9 | 1269 | { |
27a4cd48 DM |
1270 | RTL_PASS, /* type */ |
1271 | "errata", /* name */ | |
1272 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
1273 | TV_MACH_DEP, /* tv_id */ |
1274 | 0, /* properties_required */ | |
1275 | 0, /* properties_provided */ | |
1276 | 0, /* properties_destroyed */ | |
1277 | 0, /* todo_flags_start */ | |
3bea341f | 1278 | 0, /* todo_flags_finish */ |
0ea8a6f9 SB |
1279 | }; |
1280 | ||
27a4cd48 DM |
1281 | class pass_work_around_errata : public rtl_opt_pass |
1282 | { | |
1283 | public: | |
1284 | pass_work_around_errata(gcc::context *ctxt) | |
1285 | : rtl_opt_pass(pass_data_work_around_errata, ctxt) | |
1286 | {} | |
1287 | ||
1288 | /* opt_pass methods: */ | |
1a3d085c TS |
1289 | virtual bool gate (function *) |
1290 | { | |
67091cb4 | 1291 | return sparc_fix_at697f || sparc_fix_ut699 || sparc_fix_b2bst; |
1a3d085c TS |
1292 | } |
1293 | ||
be55bfe6 TS |
1294 | virtual unsigned int execute (function *) |
1295 | { | |
1296 | return sparc_do_work_around_errata (); | |
1297 | } | |
27a4cd48 DM |
1298 | |
1299 | }; // class pass_work_around_errata | |
1300 | ||
1301 | } // anon namespace | |
1302 | ||
1303 | rtl_opt_pass * | |
1304 | make_pass_work_around_errata (gcc::context *ctxt) | |
1305 | { | |
1306 | return new pass_work_around_errata (ctxt); | |
1307 | } | |
1308 | ||
0ea8a6f9 | 1309 | /* Helpers for TARGET_DEBUG_OPTIONS. */ |
a0bd60d1 DM |
1310 | static void |
1311 | dump_target_flag_bits (const int flags) | |
1312 | { | |
1313 | if (flags & MASK_64BIT) | |
1314 | fprintf (stderr, "64BIT "); | |
1315 | if (flags & MASK_APP_REGS) | |
1316 | fprintf (stderr, "APP_REGS "); | |
1317 | if (flags & MASK_FASTER_STRUCTS) | |
1318 | fprintf (stderr, "FASTER_STRUCTS "); | |
1319 | if (flags & MASK_FLAT) | |
1320 | fprintf (stderr, "FLAT "); | |
1321 | if (flags & MASK_FMAF) | |
1322 | fprintf (stderr, "FMAF "); | |
867ba4b9 SH |
1323 | if (flags & MASK_FSMULD) |
1324 | fprintf (stderr, "FSMULD "); | |
a0bd60d1 DM |
1325 | if (flags & MASK_FPU) |
1326 | fprintf (stderr, "FPU "); | |
1327 | if (flags & MASK_HARD_QUAD) | |
1328 | fprintf (stderr, "HARD_QUAD "); | |
1329 | if (flags & MASK_POPC) | |
1330 | fprintf (stderr, "POPC "); | |
1331 | if (flags & MASK_PTR64) | |
1332 | fprintf (stderr, "PTR64 "); | |
1333 | if (flags & MASK_STACK_BIAS) | |
1334 | fprintf (stderr, "STACK_BIAS "); | |
1335 | if (flags & MASK_UNALIGNED_DOUBLES) | |
1336 | fprintf (stderr, "UNALIGNED_DOUBLES "); | |
1337 | if (flags & MASK_V8PLUS) | |
1338 | fprintf (stderr, "V8PLUS "); | |
1339 | if (flags & MASK_VIS) | |
1340 | fprintf (stderr, "VIS "); | |
1341 | if (flags & MASK_VIS2) | |
1342 | fprintf (stderr, "VIS2 "); | |
1343 | if (flags & MASK_VIS3) | |
1344 | fprintf (stderr, "VIS3 "); | |
690f24b7 JM |
1345 | if (flags & MASK_VIS4) |
1346 | fprintf (stderr, "VIS4 "); | |
bcc3c3f1 JM |
1347 | if (flags & MASK_VIS4B) |
1348 | fprintf (stderr, "VIS4B "); | |
8b98b5fd DM |
1349 | if (flags & MASK_CBCOND) |
1350 | fprintf (stderr, "CBCOND "); | |
a0bd60d1 DM |
1351 | if (flags & MASK_DEPRECATED_V8_INSNS) |
1352 | fprintf (stderr, "DEPRECATED_V8_INSNS "); | |
a0bd60d1 DM |
1353 | if (flags & MASK_SPARCLET) |
1354 | fprintf (stderr, "SPARCLET "); | |
1355 | if (flags & MASK_SPARCLITE) | |
1356 | fprintf (stderr, "SPARCLITE "); | |
1357 | if (flags & MASK_V8) | |
1358 | fprintf (stderr, "V8 "); | |
1359 | if (flags & MASK_V9) | |
1360 | fprintf (stderr, "V9 "); | |
1361 | } | |
1362 | ||
1363 | static void | |
1364 | dump_target_flags (const char *prefix, const int flags) | |
1365 | { | |
1366 | fprintf (stderr, "%s: (%08x) [ ", prefix, flags); | |
1367 | dump_target_flag_bits (flags); | |
1368 | fprintf(stderr, "]\n"); | |
1369 | } | |
1370 | ||
61a55e8b DE |
1371 | /* Validate and override various options, and do some machine dependent |
1372 | initialization. */ | |
1373 | ||
c5387660 JM |
1374 | static void |
1375 | sparc_option_override (void) | |
61a55e8b | 1376 | { |
a0a301fc | 1377 | static struct code_model { |
8b60264b | 1378 | const char *const name; |
32e8bb8e | 1379 | const enum cmodel value; |
8b60264b | 1380 | } const cmodels[] = { |
a0a301fc DE |
1381 | { "32", CM_32 }, |
1382 | { "medlow", CM_MEDLOW }, | |
1383 | { "medmid", CM_MEDMID }, | |
1384 | { "medany", CM_MEDANY }, | |
1385 | { "embmedany", CM_EMBMEDANY }, | |
32e8bb8e | 1386 | { NULL, (enum cmodel) 0 } |
a0a301fc | 1387 | }; |
8b60264b | 1388 | const struct code_model *cmodel; |
07981468 | 1389 | /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */ |
733f53f5 | 1390 | static struct cpu_default { |
8b60264b | 1391 | const int cpu; |
aa53e58b | 1392 | const enum processor_type processor; |
8b60264b | 1393 | } const cpu_default[] = { |
a0a301fc | 1394 | /* There must be one entry here for each TARGET_CPU value. */ |
aa53e58b JM |
1395 | { TARGET_CPU_sparc, PROCESSOR_CYPRESS }, |
1396 | { TARGET_CPU_v8, PROCESSOR_V8 }, | |
1397 | { TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC }, | |
1398 | { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC }, | |
1399 | { TARGET_CPU_leon, PROCESSOR_LEON }, | |
38ae58ca | 1400 | { TARGET_CPU_leon3, PROCESSOR_LEON3 }, |
d81230b5 | 1401 | { TARGET_CPU_leon3v7, PROCESSOR_LEON3V7 }, |
aa53e58b JM |
1402 | { TARGET_CPU_sparclite, PROCESSOR_F930 }, |
1403 | { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X }, | |
1404 | { TARGET_CPU_sparclet, PROCESSOR_TSC701 }, | |
1405 | { TARGET_CPU_v9, PROCESSOR_V9 }, | |
1406 | { TARGET_CPU_ultrasparc, PROCESSOR_ULTRASPARC }, | |
1407 | { TARGET_CPU_ultrasparc3, PROCESSOR_ULTRASPARC3 }, | |
1408 | { TARGET_CPU_niagara, PROCESSOR_NIAGARA }, | |
1409 | { TARGET_CPU_niagara2, PROCESSOR_NIAGARA2 }, | |
3e64c239 DM |
1410 | { TARGET_CPU_niagara3, PROCESSOR_NIAGARA3 }, |
1411 | { TARGET_CPU_niagara4, PROCESSOR_NIAGARA4 }, | |
690f24b7 | 1412 | { TARGET_CPU_niagara7, PROCESSOR_NIAGARA7 }, |
bcc3c3f1 | 1413 | { TARGET_CPU_m8, PROCESSOR_M8 }, |
023592aa | 1414 | { -1, PROCESSOR_V7 } |
733f53f5 | 1415 | }; |
8b60264b | 1416 | const struct cpu_default *def; |
aa53e58b | 1417 | /* Table of values for -m{cpu,tune}=. This must match the order of |
38ae58ca | 1418 | the enum processor_type in sparc-opts.h. */ |
733f53f5 | 1419 | static struct cpu_table { |
a0bd60d1 | 1420 | const char *const name; |
8b60264b KG |
1421 | const int disable; |
1422 | const int enable; | |
1423 | } const cpu_table[] = { | |
867ba4b9 SH |
1424 | { "v7", MASK_ISA|MASK_FSMULD, 0 }, |
1425 | { "cypress", MASK_ISA|MASK_FSMULD, 0 }, | |
a0bd60d1 | 1426 | { "v8", MASK_ISA, MASK_V8 }, |
733f53f5 | 1427 | /* TI TMS390Z55 supersparc */ |
a0bd60d1 | 1428 | { "supersparc", MASK_ISA, MASK_V8 }, |
9cda17b5 | 1429 | { "hypersparc", MASK_ISA, MASK_V8 }, |
867ba4b9 | 1430 | { "leon", MASK_ISA|MASK_FSMULD, MASK_V8|MASK_LEON }, |
9cda17b5 | 1431 | { "leon3", MASK_ISA, MASK_V8|MASK_LEON3 }, |
867ba4b9 SH |
1432 | { "leon3v7", MASK_ISA|MASK_FSMULD, MASK_LEON3 }, |
1433 | { "sparclite", MASK_ISA|MASK_FSMULD, MASK_SPARCLITE }, | |
07981468 | 1434 | /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */ |
a0bd60d1 | 1435 | { "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE }, |
07981468 | 1436 | /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */ |
867ba4b9 | 1437 | { "f934", MASK_ISA|MASK_FSMULD, MASK_SPARCLITE }, |
a0bd60d1 | 1438 | { "sparclite86x", MASK_ISA|MASK_FPU, MASK_SPARCLITE }, |
867ba4b9 | 1439 | { "sparclet", MASK_ISA|MASK_FSMULD, MASK_SPARCLET }, |
733f53f5 | 1440 | /* TEMIC sparclet */ |
867ba4b9 | 1441 | { "tsc701", MASK_ISA|MASK_FSMULD, MASK_SPARCLET }, |
a0bd60d1 | 1442 | { "v9", MASK_ISA, MASK_V9 }, |
07981468 | 1443 | /* UltraSPARC I, II, IIi */ |
a0bd60d1 | 1444 | { "ultrasparc", MASK_ISA, |
07981468 | 1445 | /* Although insns using %y are deprecated, it is a clear win. */ |
a0bd60d1 | 1446 | MASK_V9|MASK_DEPRECATED_V8_INSNS }, |
07981468 KE |
1447 | /* UltraSPARC III */ |
1448 | /* ??? Check if %y issue still holds true. */ | |
a0bd60d1 DM |
1449 | { "ultrasparc3", MASK_ISA, |
1450 | MASK_V9|MASK_DEPRECATED_V8_INSNS|MASK_VIS2 }, | |
4c837a1e | 1451 | /* UltraSPARC T1 */ |
a0bd60d1 DM |
1452 | { "niagara", MASK_ISA, |
1453 | MASK_V9|MASK_DEPRECATED_V8_INSNS }, | |
07981468 | 1454 | /* UltraSPARC T2 */ |
a0bd60d1 DM |
1455 | { "niagara2", MASK_ISA, |
1456 | MASK_V9|MASK_POPC|MASK_VIS2 }, | |
3e64c239 | 1457 | /* UltraSPARC T3 */ |
a0bd60d1 | 1458 | { "niagara3", MASK_ISA, |
ff7e7ee0 | 1459 | MASK_V9|MASK_POPC|MASK_VIS3|MASK_FMAF }, |
3e64c239 | 1460 | /* UltraSPARC T4 */ |
a0bd60d1 | 1461 | { "niagara4", MASK_ISA, |
ff7e7ee0 | 1462 | MASK_V9|MASK_POPC|MASK_VIS3|MASK_FMAF|MASK_CBCOND }, |
690f24b7 JM |
1463 | /* UltraSPARC M7 */ |
1464 | { "niagara7", MASK_ISA, | |
bcc3c3f1 JM |
1465 | MASK_V9|MASK_POPC|MASK_VIS4|MASK_FMAF|MASK_CBCOND|MASK_SUBXC }, |
1466 | /* UltraSPARC M8 */ | |
1467 | { "m8", MASK_ISA, | |
a7faf57b | 1468 | MASK_V9|MASK_POPC|MASK_VIS4|MASK_FMAF|MASK_CBCOND|MASK_SUBXC|MASK_VIS4B } |
733f53f5 | 1469 | }; |
8b60264b | 1470 | const struct cpu_table *cpu; |
b11b0904 | 1471 | unsigned int i; |
4900aa61 | 1472 | |
a0bd60d1 DM |
1473 | if (sparc_debug_string != NULL) |
1474 | { | |
1475 | const char *q; | |
1476 | char *p; | |
1477 | ||
1478 | p = ASTRDUP (sparc_debug_string); | |
1479 | while ((q = strtok (p, ",")) != NULL) | |
1480 | { | |
1481 | bool invert; | |
1482 | int mask; | |
1483 | ||
1484 | p = NULL; | |
1485 | if (*q == '!') | |
1486 | { | |
1487 | invert = true; | |
1488 | q++; | |
1489 | } | |
1490 | else | |
1491 | invert = false; | |
1492 | ||
1493 | if (! strcmp (q, "all")) | |
1494 | mask = MASK_DEBUG_ALL; | |
1495 | else if (! strcmp (q, "options")) | |
1496 | mask = MASK_DEBUG_OPTIONS; | |
1497 | else | |
1498 | error ("unknown -mdebug-%s switch", q); | |
1499 | ||
1500 | if (invert) | |
1501 | sparc_debug &= ~mask; | |
1502 | else | |
1503 | sparc_debug |= mask; | |
1504 | } | |
1505 | } | |
1506 | ||
a7faf57b EB |
1507 | /* Enable the FsMULd instruction by default if not explicitly specified by |
1508 | the user. It may be later disabled by the CPU (explicitly or not). */ | |
1509 | if (TARGET_FPU && !(target_flags_explicit & MASK_FSMULD)) | |
1510 | target_flags |= MASK_FSMULD; | |
1511 | ||
a0bd60d1 DM |
1512 | if (TARGET_DEBUG_OPTIONS) |
1513 | { | |
1514 | dump_target_flags("Initial target_flags", target_flags); | |
1515 | dump_target_flags("target_flags_explicit", target_flags_explicit); | |
1516 | } | |
1517 | ||
c5387660 JM |
1518 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
1519 | SUBTARGET_OVERRIDE_OPTIONS; | |
1520 | #endif | |
1521 | ||
a0a301fc DE |
1522 | #ifndef SPARC_BI_ARCH |
1523 | /* Check for unsupported architecture size. */ | |
7c7dae65 | 1524 | if (!TARGET_64BIT != DEFAULT_ARCH32_P) |
3276910d RK |
1525 | error ("%s is not supported by this configuration", |
1526 | DEFAULT_ARCH32_P ? "-m64" : "-m32"); | |
a0a301fc DE |
1527 | #endif |
1528 | ||
4710d3eb | 1529 | /* We force all 64bit archs to use 128 bit long double */ |
7c7dae65 | 1530 | if (TARGET_ARCH64 && !TARGET_LONG_DOUBLE_128) |
4710d3eb JJ |
1531 | { |
1532 | error ("-mlong-double-64 not allowed with -m64"); | |
1533 | target_flags |= MASK_LONG_DOUBLE_128; | |
1534 | } | |
1535 | ||
a0a301fc DE |
1536 | /* Code model selection. */ |
1537 | sparc_cmodel = SPARC_DEFAULT_CMODEL; | |
4900aa61 | 1538 | |
345a6161 DM |
1539 | #ifdef SPARC_BI_ARCH |
1540 | if (TARGET_ARCH32) | |
1541 | sparc_cmodel = CM_32; | |
1542 | #endif | |
1543 | ||
a0a301fc DE |
1544 | if (sparc_cmodel_string != NULL) |
1545 | { | |
1546 | if (TARGET_ARCH64) | |
1547 | { | |
1548 | for (cmodel = &cmodels[0]; cmodel->name; cmodel++) | |
1549 | if (strcmp (sparc_cmodel_string, cmodel->name) == 0) | |
1550 | break; | |
1551 | if (cmodel->name == NULL) | |
1552 | error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); | |
1553 | else | |
1554 | sparc_cmodel = cmodel->value; | |
1555 | } | |
1556 | else | |
a7faf57b | 1557 | error ("-mcmodel= is not supported on 32-bit systems"); |
a0a301fc | 1558 | } |
16956f6e | 1559 | |
b11b0904 EB |
1560 | /* Check that -fcall-saved-REG wasn't specified for out registers. */ |
1561 | for (i = 8; i < 16; i++) | |
1562 | if (!call_used_regs [i]) | |
1563 | { | |
1564 | error ("-fcall-saved-REG is not supported for out registers"); | |
1565 | call_used_regs [i] = 1; | |
1566 | } | |
1567 | ||
a7faf57b | 1568 | /* Set the default CPU if no -mcpu option was specified. */ |
aa53e58b | 1569 | if (!global_options_set.x_sparc_cpu_and_features) |
61a55e8b | 1570 | { |
aa53e58b JM |
1571 | for (def = &cpu_default[0]; def->cpu != -1; ++def) |
1572 | if (def->cpu == TARGET_CPU_DEFAULT) | |
1573 | break; | |
1574 | gcc_assert (def->cpu != -1); | |
1575 | sparc_cpu_and_features = def->processor; | |
61a55e8b | 1576 | } |
a0bd60d1 | 1577 | |
a7faf57b | 1578 | /* Set the default CPU if no -mtune option was specified. */ |
aa53e58b JM |
1579 | if (!global_options_set.x_sparc_cpu) |
1580 | sparc_cpu = sparc_cpu_and_features; | |
1581 | ||
1582 | cpu = &cpu_table[(int) sparc_cpu_and_features]; | |
a0bd60d1 DM |
1583 | |
1584 | if (TARGET_DEBUG_OPTIONS) | |
1585 | { | |
1586 | fprintf (stderr, "sparc_cpu_and_features: %s\n", cpu->name); | |
a0bd60d1 DM |
1587 | dump_target_flags ("cpu->disable", cpu->disable); |
1588 | dump_target_flags ("cpu->enable", cpu->enable); | |
1589 | } | |
1590 | ||
aa53e58b | 1591 | target_flags &= ~cpu->disable; |
fad034a7 DM |
1592 | target_flags |= (cpu->enable |
1593 | #ifndef HAVE_AS_FMAF_HPC_VIS3 | |
1594 | & ~(MASK_FMAF | MASK_VIS3) | |
8b98b5fd DM |
1595 | #endif |
1596 | #ifndef HAVE_AS_SPARC4 | |
1597 | & ~MASK_CBCOND | |
1f65ae7a | 1598 | #endif |
690f24b7 | 1599 | #ifndef HAVE_AS_SPARC5_VIS4 |
ff7e7ee0 | 1600 | & ~(MASK_VIS4 | MASK_SUBXC) |
690f24b7 | 1601 | #endif |
bcc3c3f1 JM |
1602 | #ifndef HAVE_AS_SPARC6 |
1603 | & ~(MASK_VIS4B) | |
1604 | #endif | |
1f65ae7a EB |
1605 | #ifndef HAVE_AS_LEON |
1606 | & ~(MASK_LEON | MASK_LEON3) | |
fad034a7 | 1607 | #endif |
938a807a | 1608 | & ~(target_flags_explicit & MASK_FEATURES) |
fad034a7 | 1609 | ); |
97da85b7 | 1610 | |
938a807a | 1611 | /* -mvis2 implies -mvis. */ |
c4728c6b DM |
1612 | if (TARGET_VIS2) |
1613 | target_flags |= MASK_VIS; | |
1614 | ||
938a807a | 1615 | /* -mvis3 implies -mvis2 and -mvis. */ |
96d7b15f DM |
1616 | if (TARGET_VIS3) |
1617 | target_flags |= MASK_VIS2 | MASK_VIS; | |
1618 | ||
938a807a | 1619 | /* -mvis4 implies -mvis3, -mvis2 and -mvis. */ |
690f24b7 JM |
1620 | if (TARGET_VIS4) |
1621 | target_flags |= MASK_VIS3 | MASK_VIS2 | MASK_VIS; | |
1622 | ||
bcc3c3f1 JM |
1623 | /* -mvis4b implies -mvis4, -mvis3, -mvis2 and -mvis */ |
1624 | if (TARGET_VIS4B) | |
1625 | target_flags |= MASK_VIS4 | MASK_VIS3 | MASK_VIS2 | MASK_VIS; | |
1626 | ||
867ba4b9 | 1627 | /* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b, -mfmaf and -mfsmuld if |
bcc3c3f1 | 1628 | FPU is disabled. */ |
a7faf57b | 1629 | if (!TARGET_FPU) |
690f24b7 | 1630 | target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_VIS4 |
867ba4b9 | 1631 | | MASK_VIS4B | MASK_FMAF | MASK_FSMULD); |
a5774a7d JJ |
1632 | |
1633 | /* -mvis assumes UltraSPARC+, so we are sure v9 instructions | |
938a807a | 1634 | are available; -m64 also implies v9. */ |
a5774a7d | 1635 | if (TARGET_VIS || TARGET_ARCH64) |
c4031a04 JJ |
1636 | { |
1637 | target_flags |= MASK_V9; | |
1638 | target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); | |
1639 | } | |
a5774a7d | 1640 | |
938a807a | 1641 | /* -mvis also implies -mv8plus on 32-bit. */ |
a7faf57b | 1642 | if (TARGET_VIS && !TARGET_ARCH64) |
10b859c0 DM |
1643 | target_flags |= MASK_V8PLUS; |
1644 | ||
a7faf57b | 1645 | /* Use the deprecated v8 insns for sparc64 in 32-bit mode. */ |
16956f6e | 1646 | if (TARGET_V9 && TARGET_ARCH32) |
733f53f5 | 1647 | target_flags |= MASK_DEPRECATED_V8_INSNS; |
61a55e8b | 1648 | |
a7faf57b EB |
1649 | /* V8PLUS requires V9 and makes no sense in 64-bit mode. */ |
1650 | if (!TARGET_V9 || TARGET_ARCH64) | |
284d86e9 JC |
1651 | target_flags &= ~MASK_V8PLUS; |
1652 | ||
a7faf57b | 1653 | /* Don't use stack biasing in 32-bit mode. */ |
82d6b402 RH |
1654 | if (TARGET_ARCH32) |
1655 | target_flags &= ~MASK_STACK_BIAS; | |
4900aa61 | 1656 | |
70a6dbe7 EB |
1657 | /* Use LRA instead of reload, unless otherwise instructed. */ |
1658 | if (!(target_flags_explicit & MASK_LRA)) | |
1659 | target_flags |= MASK_LRA; | |
1660 | ||
67091cb4 DC |
1661 | /* Enable the back-to-back store errata workaround for LEON3FT. */ |
1662 | if (sparc_fix_ut699 || sparc_fix_ut700 || sparc_fix_gr712rc) | |
1663 | sparc_fix_b2bst = 1; | |
1664 | ||
867ba4b9 SH |
1665 | /* Disable FsMULd for the UT699 since it doesn't work correctly. */ |
1666 | if (sparc_fix_ut699) | |
1667 | target_flags &= ~MASK_FSMULD; | |
1668 | ||
efa3896a | 1669 | /* Supply a default value for align_functions. */ |
00a84d0e SL |
1670 | if (align_functions == 0) |
1671 | { | |
1672 | if (sparc_cpu == PROCESSOR_ULTRASPARC | |
4c837a1e | 1673 | || sparc_cpu == PROCESSOR_ULTRASPARC3 |
9eeaed6e | 1674 | || sparc_cpu == PROCESSOR_NIAGARA |
3e64c239 DM |
1675 | || sparc_cpu == PROCESSOR_NIAGARA2 |
1676 | || sparc_cpu == PROCESSOR_NIAGARA3 | |
00a84d0e SL |
1677 | || sparc_cpu == PROCESSOR_NIAGARA4) |
1678 | align_functions = 32; | |
bcc3c3f1 JM |
1679 | else if (sparc_cpu == PROCESSOR_NIAGARA7 |
1680 | || sparc_cpu == PROCESSOR_M8) | |
00a84d0e SL |
1681 | align_functions = 64; |
1682 | } | |
bf62bbf1 | 1683 | |
82d6b402 RH |
1684 | /* Validate PCC_STRUCT_RETURN. */ |
1685 | if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) | |
1686 | flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); | |
1687 | ||
301d03af RS |
1688 | /* Only use .uaxword when compiling for a 64-bit target. */ |
1689 | if (!TARGET_ARCH64) | |
1690 | targetm.asm_out.unaligned_op.di = NULL; | |
1691 | ||
61a55e8b DE |
1692 | /* Do various machine dependent initializations. */ |
1693 | sparc_init_modes (); | |
5751a10b JJ |
1694 | |
1695 | /* Set up function hooks. */ | |
1696 | init_machine_status = sparc_init_machine_status; | |
18df6de9 DM |
1697 | |
1698 | switch (sparc_cpu) | |
1699 | { | |
1700 | case PROCESSOR_V7: | |
1701 | case PROCESSOR_CYPRESS: | |
1702 | sparc_costs = &cypress_costs; | |
1703 | break; | |
1704 | case PROCESSOR_V8: | |
1705 | case PROCESSOR_SPARCLITE: | |
1706 | case PROCESSOR_SUPERSPARC: | |
1707 | sparc_costs = &supersparc_costs; | |
1708 | break; | |
1709 | case PROCESSOR_F930: | |
1710 | case PROCESSOR_F934: | |
1711 | case PROCESSOR_HYPERSPARC: | |
1712 | case PROCESSOR_SPARCLITE86X: | |
1713 | sparc_costs = &hypersparc_costs; | |
1714 | break; | |
07981468 KE |
1715 | case PROCESSOR_LEON: |
1716 | sparc_costs = &leon_costs; | |
1717 | break; | |
38ae58ca | 1718 | case PROCESSOR_LEON3: |
d81230b5 | 1719 | case PROCESSOR_LEON3V7: |
38ae58ca EB |
1720 | sparc_costs = &leon3_costs; |
1721 | break; | |
18df6de9 DM |
1722 | case PROCESSOR_SPARCLET: |
1723 | case PROCESSOR_TSC701: | |
1724 | sparc_costs = &sparclet_costs; | |
1725 | break; | |
1726 | case PROCESSOR_V9: | |
1727 | case PROCESSOR_ULTRASPARC: | |
1728 | sparc_costs = &ultrasparc_costs; | |
1729 | break; | |
1730 | case PROCESSOR_ULTRASPARC3: | |
1731 | sparc_costs = &ultrasparc3_costs; | |
1732 | break; | |
4c837a1e DM |
1733 | case PROCESSOR_NIAGARA: |
1734 | sparc_costs = &niagara_costs; | |
1735 | break; | |
9eeaed6e | 1736 | case PROCESSOR_NIAGARA2: |
ab0ca06f DM |
1737 | sparc_costs = &niagara2_costs; |
1738 | break; | |
3e64c239 | 1739 | case PROCESSOR_NIAGARA3: |
ab0ca06f | 1740 | sparc_costs = &niagara3_costs; |
9eeaed6e | 1741 | break; |
851634c7 DM |
1742 | case PROCESSOR_NIAGARA4: |
1743 | sparc_costs = &niagara4_costs; | |
1744 | break; | |
690f24b7 JM |
1745 | case PROCESSOR_NIAGARA7: |
1746 | sparc_costs = &niagara7_costs; | |
1747 | break; | |
bcc3c3f1 JM |
1748 | case PROCESSOR_M8: |
1749 | sparc_costs = &m8_costs; | |
1750 | break; | |
e3b3fa45 RO |
1751 | case PROCESSOR_NATIVE: |
1752 | gcc_unreachable (); | |
18df6de9 | 1753 | }; |
ed965309 | 1754 | |
2e65f38f RH |
1755 | if (sparc_memory_model == SMM_DEFAULT) |
1756 | { | |
6cc7fb90 RH |
1757 | /* Choose the memory model for the operating system. */ |
1758 | enum sparc_memory_model_type os_default = SUBTARGET_DEFAULT_MEMORY_MODEL; | |
1759 | if (os_default != SMM_DEFAULT) | |
1760 | sparc_memory_model = os_default; | |
2e65f38f | 1761 | /* Choose the most relaxed model for the processor. */ |
6cc7fb90 | 1762 | else if (TARGET_V9) |
2e65f38f | 1763 | sparc_memory_model = SMM_RMO; |
1f65ae7a EB |
1764 | else if (TARGET_LEON3) |
1765 | sparc_memory_model = SMM_TSO; | |
1766 | else if (TARGET_LEON) | |
1767 | sparc_memory_model = SMM_SC; | |
2e65f38f RH |
1768 | else if (TARGET_V8) |
1769 | sparc_memory_model = SMM_PSO; | |
1770 | else | |
1771 | sparc_memory_model = SMM_SC; | |
1772 | } | |
1773 | ||
ed965309 JJ |
1774 | #ifdef TARGET_DEFAULT_LONG_DOUBLE_128 |
1775 | if (!(target_flags_explicit & MASK_LONG_DOUBLE_128)) | |
1776 | target_flags |= MASK_LONG_DOUBLE_128; | |
1777 | #endif | |
47eb5b32 | 1778 | |
a0bd60d1 DM |
1779 | if (TARGET_DEBUG_OPTIONS) |
1780 | dump_target_flags ("Final target_flags", target_flags); | |
1781 | ||
690f24b7 JM |
1782 | /* PARAM_SIMULTANEOUS_PREFETCHES is the number of prefetches that |
1783 | can run at the same time. More important, it is the threshold | |
1784 | defining when additional prefetches will be dropped by the | |
1785 | hardware. | |
1786 | ||
1787 | The UltraSPARC-III features a documented prefetch queue with a | |
1788 | size of 8. Additional prefetches issued in the cpu are | |
1789 | dropped. | |
1790 | ||
1791 | Niagara processors are different. In these processors prefetches | |
1792 | are handled much like regular loads. The L1 miss buffer is 32 | |
1793 | entries, but prefetches start getting affected when 30 entries | |
1794 | become occupied. That occupation could be a mix of regular loads | |
1795 | and prefetches though. And that buffer is shared by all threads. | |
1796 | Once the threshold is reached, if the core is running a single | |
1797 | thread the prefetch will retry. If more than one thread is | |
1798 | running, the prefetch will be dropped. | |
1799 | ||
1800 | All this makes it very difficult to determine how many | |
1801 | simultaneous prefetches can be issued simultaneously, even in a | |
1802 | single-threaded program. Experimental results show that setting | |
1803 | this parameter to 32 works well when the number of threads is not | |
1804 | high. */ | |
128dc8e2 JM |
1805 | maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, |
1806 | ((sparc_cpu == PROCESSOR_ULTRASPARC | |
1807 | || sparc_cpu == PROCESSOR_NIAGARA | |
3e64c239 DM |
1808 | || sparc_cpu == PROCESSOR_NIAGARA2 |
1809 | || sparc_cpu == PROCESSOR_NIAGARA3 | |
1810 | || sparc_cpu == PROCESSOR_NIAGARA4) | |
128dc8e2 JM |
1811 | ? 2 |
1812 | : (sparc_cpu == PROCESSOR_ULTRASPARC3 | |
bcc3c3f1 JM |
1813 | ? 8 : ((sparc_cpu == PROCESSOR_NIAGARA7 |
1814 | || sparc_cpu == PROCESSOR_M8) | |
690f24b7 | 1815 | ? 32 : 3))), |
48476d13 JM |
1816 | global_options.x_param_values, |
1817 | global_options_set.x_param_values); | |
690f24b7 | 1818 | |
bcc3c3f1 JM |
1819 | /* PARAM_L1_CACHE_LINE_SIZE is the size of the L1 cache line, in |
1820 | bytes. | |
690f24b7 JM |
1821 | |
1822 | The Oracle SPARC Architecture (previously the UltraSPARC | |
1823 | Architecture) specification states that when a PREFETCH[A] | |
1824 | instruction is executed an implementation-specific amount of data | |
1825 | is prefetched, and that it is at least 64 bytes long (aligned to | |
1826 | at least 64 bytes). | |
1827 | ||
1828 | However, this is not correct. The M7 (and implementations prior | |
1829 | to that) does not guarantee a 64B prefetch into a cache if the | |
1830 | line size is smaller. A single cache line is all that is ever | |
1831 | prefetched. So for the M7, where the L1D$ has 32B lines and the | |
1832 | L2D$ and L3 have 64B lines, a prefetch will prefetch 64B into the | |
1833 | L2 and L3, but only 32B are brought into the L1D$. (Assuming it | |
1834 | is a read_n prefetch, which is the only type which allocates to | |
1835 | the L1.) */ | |
bcc3c3f1 JM |
1836 | maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, |
1837 | (sparc_cpu == PROCESSOR_M8 | |
1838 | ? 64 : 32), | |
1839 | global_options.x_param_values, | |
1840 | global_options_set.x_param_values); | |
690f24b7 JM |
1841 | |
1842 | /* PARAM_L1_CACHE_SIZE is the size of the L1D$ (most SPARC chips use | |
1843 | Hardvard level-1 caches) in kilobytes. Both UltraSPARC and | |
1844 | Niagara processors feature a L1D$ of 16KB. */ | |
1845 | maybe_set_param_value (PARAM_L1_CACHE_SIZE, | |
128dc8e2 JM |
1846 | ((sparc_cpu == PROCESSOR_ULTRASPARC |
1847 | || sparc_cpu == PROCESSOR_ULTRASPARC3 | |
1848 | || sparc_cpu == PROCESSOR_NIAGARA | |
3e64c239 DM |
1849 | || sparc_cpu == PROCESSOR_NIAGARA2 |
1850 | || sparc_cpu == PROCESSOR_NIAGARA3 | |
690f24b7 | 1851 | || sparc_cpu == PROCESSOR_NIAGARA4 |
bcc3c3f1 JM |
1852 | || sparc_cpu == PROCESSOR_NIAGARA7 |
1853 | || sparc_cpu == PROCESSOR_M8) | |
690f24b7 JM |
1854 | ? 16 : 64), |
1855 | global_options.x_param_values, | |
1856 | global_options_set.x_param_values); | |
1857 | ||
1858 | ||
1859 | /* PARAM_L2_CACHE_SIZE is the size fo the L2 in kilobytes. Note | |
1860 | that 512 is the default in params.def. */ | |
1861 | maybe_set_param_value (PARAM_L2_CACHE_SIZE, | |
bcc3c3f1 JM |
1862 | ((sparc_cpu == PROCESSOR_NIAGARA4 |
1863 | || sparc_cpu == PROCESSOR_M8) | |
690f24b7 JM |
1864 | ? 128 : (sparc_cpu == PROCESSOR_NIAGARA7 |
1865 | ? 256 : 512)), | |
48476d13 JM |
1866 | global_options.x_param_values, |
1867 | global_options_set.x_param_values); | |
690f24b7 | 1868 | |
24d1bbc7 EB |
1869 | |
1870 | /* Disable save slot sharing for call-clobbered registers by default. | |
1871 | The IRA sharing algorithm works on single registers only and this | |
1872 | pessimizes for double floating-point registers. */ | |
1873 | if (!global_options_set.x_flag_ira_share_save_slots) | |
1874 | flag_ira_share_save_slots = 0; | |
94331892 EB |
1875 | |
1876 | /* Only enable REE by default in 64-bit mode where it helps to eliminate | |
1877 | redundant 32-to-64-bit extensions. */ | |
1878 | if (!global_options_set.x_flag_ree && TARGET_ARCH32) | |
1879 | flag_ree = 0; | |
61a55e8b DE |
1880 | } |
1881 | \f | |
cd5fb1ee DE |
1882 | /* Miscellaneous utilities. */ |
1883 | ||
1884 | /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move | |
1885 | or branch on register contents instructions. */ | |
1886 | ||
1887 | int | |
fc27d102 | 1888 | v9_regcmp_p (enum rtx_code code) |
cd5fb1ee DE |
1889 | { |
1890 | return (code == EQ || code == NE || code == GE || code == LT | |
1891 | || code == LE || code == GT); | |
1892 | } | |
bfd6bc60 | 1893 | |
62190128 DM |
1894 | /* Nonzero if OP is a floating point constant which can |
1895 | be loaded into an integer register using a single | |
1896 | sethi instruction. */ | |
1897 | ||
1898 | int | |
fc27d102 | 1899 | fp_sethi_p (rtx op) |
62190128 DM |
1900 | { |
1901 | if (GET_CODE (op) == CONST_DOUBLE) | |
1902 | { | |
62190128 DM |
1903 | long i; |
1904 | ||
34a72c33 | 1905 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), i); |
9a9e266b | 1906 | return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i); |
62190128 DM |
1907 | } |
1908 | ||
1909 | return 0; | |
1910 | } | |
1911 | ||
1912 | /* Nonzero if OP is a floating point constant which can | |
1913 | be loaded into an integer register using a single | |
1914 | mov instruction. */ | |
1915 | ||
1916 | int | |
fc27d102 | 1917 | fp_mov_p (rtx op) |
62190128 DM |
1918 | { |
1919 | if (GET_CODE (op) == CONST_DOUBLE) | |
1920 | { | |
62190128 DM |
1921 | long i; |
1922 | ||
34a72c33 | 1923 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), i); |
9a9e266b | 1924 | return SPARC_SIMM13_P (i); |
62190128 DM |
1925 | } |
1926 | ||
1927 | return 0; | |
1928 | } | |
1929 | ||
1930 | /* Nonzero if OP is a floating point constant which can | |
1931 | be loaded into an integer register using a high/losum | |
1932 | instruction sequence. */ | |
1933 | ||
1934 | int | |
fc27d102 | 1935 | fp_high_losum_p (rtx op) |
62190128 DM |
1936 | { |
1937 | /* The constraints calling this should only be in | |
1938 | SFmode move insns, so any constant which cannot | |
1939 | be moved using a single insn will do. */ | |
1940 | if (GET_CODE (op) == CONST_DOUBLE) | |
1941 | { | |
62190128 DM |
1942 | long i; |
1943 | ||
34a72c33 | 1944 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), i); |
9a9e266b | 1945 | return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i); |
62190128 DM |
1946 | } |
1947 | ||
1948 | return 0; | |
1949 | } | |
1950 | ||
205e4c6a EB |
1951 | /* Return true if the address of LABEL can be loaded by means of the |
1952 | mov{si,di}_pic_label_ref patterns in PIC mode. */ | |
1953 | ||
1954 | static bool | |
1955 | can_use_mov_pic_label_ref (rtx label) | |
1956 | { | |
1957 | /* VxWorks does not impose a fixed gap between segments; the run-time | |
1958 | gap can be different from the object-file gap. We therefore can't | |
1959 | assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we | |
1960 | are absolutely sure that X is in the same segment as the GOT. | |
1961 | Unfortunately, the flexibility of linker scripts means that we | |
1962 | can't be sure of that in general, so assume that GOT-relative | |
1963 | accesses are never valid on VxWorks. */ | |
1964 | if (TARGET_VXWORKS_RTP) | |
1965 | return false; | |
1966 | ||
1967 | /* Similarly, if the label is non-local, it might end up being placed | |
1968 | in a different section than the current one; now mov_pic_label_ref | |
1969 | requires the label and the code to be in the same section. */ | |
1970 | if (LABEL_REF_NONLOCAL_P (label)) | |
1971 | return false; | |
1972 | ||
1973 | /* Finally, if we are reordering basic blocks and partition into hot | |
1974 | and cold sections, this might happen for any label. */ | |
1975 | if (flag_reorder_blocks_and_partition) | |
1976 | return false; | |
1977 | ||
1978 | return true; | |
1979 | } | |
1980 | ||
bea5071f EB |
1981 | /* Expand a move instruction. Return true if all work is done. */ |
1982 | ||
1983 | bool | |
ef4bddc2 | 1984 | sparc_expand_move (machine_mode mode, rtx *operands) |
bea5071f EB |
1985 | { |
1986 | /* Handle sets of MEM first. */ | |
1987 | if (GET_CODE (operands[0]) == MEM) | |
1988 | { | |
1989 | /* 0 is a register (or a pair of registers) on SPARC. */ | |
1990 | if (register_or_zero_operand (operands[1], mode)) | |
1991 | return false; | |
1992 | ||
1993 | if (!reload_in_progress) | |
1994 | { | |
1995 | operands[0] = validize_mem (operands[0]); | |
1996 | operands[1] = force_reg (mode, operands[1]); | |
1997 | } | |
1998 | } | |
1999 | ||
2000 | /* Fixup TLS cases. */ | |
38fc66ba EB |
2001 | if (TARGET_HAVE_TLS |
2002 | && CONSTANT_P (operands[1]) | |
38fc66ba EB |
2003 | && sparc_tls_referenced_p (operands [1])) |
2004 | { | |
58e6223e | 2005 | operands[1] = sparc_legitimize_tls_address (operands[1]); |
208384fd | 2006 | return false; |
38fc66ba | 2007 | } |
4900aa61 | 2008 | |
bea5071f EB |
2009 | /* Fixup PIC cases. */ |
2010 | if (flag_pic && CONSTANT_P (operands[1])) | |
2011 | { | |
2012 | if (pic_address_needs_scratch (operands[1])) | |
58e6223e | 2013 | operands[1] = sparc_legitimize_pic_address (operands[1], NULL_RTX); |
bea5071f | 2014 | |
205e4c6a EB |
2015 | /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */ |
2016 | if (GET_CODE (operands[1]) == LABEL_REF | |
2017 | && can_use_mov_pic_label_ref (operands[1])) | |
bea5071f | 2018 | { |
1910440e RS |
2019 | if (mode == SImode) |
2020 | { | |
2021 | emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1])); | |
2022 | return true; | |
2023 | } | |
bea5071f | 2024 | |
1910440e RS |
2025 | if (mode == DImode) |
2026 | { | |
2027 | gcc_assert (TARGET_ARCH64); | |
2028 | emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1])); | |
2029 | return true; | |
2030 | } | |
bea5071f EB |
2031 | } |
2032 | ||
2033 | if (symbolic_operand (operands[1], mode)) | |
2034 | { | |
58e6223e EB |
2035 | operands[1] |
2036 | = sparc_legitimize_pic_address (operands[1], | |
2037 | reload_in_progress | |
2038 | ? operands[0] : NULL_RTX); | |
bea5071f EB |
2039 | return false; |
2040 | } | |
2041 | } | |
2042 | ||
2043 | /* If we are trying to toss an integer constant into FP registers, | |
2044 | or loading a FP or vector constant, force it into memory. */ | |
2045 | if (CONSTANT_P (operands[1]) | |
2046 | && REG_P (operands[0]) | |
2047 | && (SPARC_FP_REG_P (REGNO (operands[0])) | |
2048 | || SCALAR_FLOAT_MODE_P (mode) | |
2049 | || VECTOR_MODE_P (mode))) | |
2050 | { | |
2051 | /* emit_group_store will send such bogosity to us when it is | |
2052 | not storing directly into memory. So fix this up to avoid | |
2053 | crashes in output_constant_pool. */ | |
2054 | if (operands [1] == const0_rtx) | |
2055 | operands[1] = CONST0_RTX (mode); | |
2056 | ||
7cbcf85b DM |
2057 | /* We can clear or set to all-ones FP registers if TARGET_VIS, and |
2058 | always other regs. */ | |
bea5071f | 2059 | if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG) |
7cbcf85b DM |
2060 | && (const_zero_operand (operands[1], mode) |
2061 | || const_all_ones_operand (operands[1], mode))) | |
bea5071f EB |
2062 | return false; |
2063 | ||
2064 | if (REGNO (operands[0]) < SPARC_FIRST_FP_REG | |
2065 | /* We are able to build any SF constant in integer registers | |
2066 | with at most 2 instructions. */ | |
2067 | && (mode == SFmode | |
a16c8d8b EB |
2068 | /* And any DF constant in integer registers if needed. */ |
2069 | || (mode == DFmode && !can_create_pseudo_p ()))) | |
bea5071f EB |
2070 | return false; |
2071 | ||
2072 | operands[1] = force_const_mem (mode, operands[1]); | |
2073 | if (!reload_in_progress) | |
2074 | operands[1] = validize_mem (operands[1]); | |
2075 | return false; | |
2076 | } | |
2077 | ||
2078 | /* Accept non-constants and valid constants unmodified. */ | |
2079 | if (!CONSTANT_P (operands[1]) | |
2080 | || GET_CODE (operands[1]) == HIGH | |
2081 | || input_operand (operands[1], mode)) | |
2082 | return false; | |
2083 | ||
2084 | switch (mode) | |
2085 | { | |
4e10a5a7 | 2086 | case E_QImode: |
bea5071f EB |
2087 | /* All QImode constants require only one insn, so proceed. */ |
2088 | break; | |
2089 | ||
4e10a5a7 RS |
2090 | case E_HImode: |
2091 | case E_SImode: | |
bea5071f EB |
2092 | sparc_emit_set_const32 (operands[0], operands[1]); |
2093 | return true; | |
2094 | ||
4e10a5a7 | 2095 | case E_DImode: |
bea5071f EB |
2096 | /* input_operand should have filtered out 32-bit mode. */ |
2097 | sparc_emit_set_const64 (operands[0], operands[1]); | |
2098 | return true; | |
4900aa61 | 2099 | |
4e10a5a7 | 2100 | case E_TImode: |
03c432bd EB |
2101 | { |
2102 | rtx high, low; | |
2103 | /* TImode isn't available in 32-bit mode. */ | |
2104 | split_double (operands[1], &high, &low); | |
2105 | emit_insn (gen_movdi (operand_subword (operands[0], 0, 0, TImode), | |
2106 | high)); | |
2107 | emit_insn (gen_movdi (operand_subword (operands[0], 1, 0, TImode), | |
2108 | low)); | |
2109 | } | |
2110 | return true; | |
2111 | ||
bea5071f EB |
2112 | default: |
2113 | gcc_unreachable (); | |
2114 | } | |
2115 | ||
2116 | return false; | |
2117 | } | |
2118 | ||
2119 | /* Load OP1, a 32-bit constant, into OP0, a register. | |
2120 | We know it can't be done in one insn when we get | |
2121 | here, the move expander guarantees this. */ | |
2122 | ||
d9816849 | 2123 | static void |
fc27d102 | 2124 | sparc_emit_set_const32 (rtx op0, rtx op1) |
e0d80184 | 2125 | { |
ef4bddc2 | 2126 | machine_mode mode = GET_MODE (op0); |
cedced65 | 2127 | rtx temp = op0; |
e0d80184 | 2128 | |
cedced65 | 2129 | if (can_create_pseudo_p ()) |
e0d80184 DM |
2130 | temp = gen_reg_rtx (mode); |
2131 | ||
71648202 DM |
2132 | if (GET_CODE (op1) == CONST_INT) |
2133 | { | |
0e5d569c EB |
2134 | gcc_assert (!small_int_operand (op1, mode) |
2135 | && !const_high_operand (op1, mode)); | |
2136 | ||
71648202 DM |
2137 | /* Emit them as real moves instead of a HIGH/LO_SUM, |
2138 | this way CSE can see everything and reuse intermediate | |
2139 | values if it wants. */ | |
f7df4a84 RS |
2140 | emit_insn (gen_rtx_SET (temp, GEN_INT (INTVAL (op1) |
2141 | & ~(HOST_WIDE_INT) 0x3ff))); | |
f2827474 | 2142 | |
f7df4a84 | 2143 | emit_insn (gen_rtx_SET (op0, |
f2827474 | 2144 | gen_rtx_IOR (mode, temp, |
71648202 DM |
2145 | GEN_INT (INTVAL (op1) & 0x3ff)))); |
2146 | } | |
2147 | else | |
2148 | { | |
2149 | /* A symbol, emit in the traditional way. */ | |
f7df4a84 RS |
2150 | emit_insn (gen_rtx_SET (temp, gen_rtx_HIGH (mode, op1))); |
2151 | emit_insn (gen_rtx_SET (op0, gen_rtx_LO_SUM (mode, temp, op1))); | |
71648202 | 2152 | } |
e0d80184 DM |
2153 | } |
2154 | ||
1d511ed5 | 2155 | /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register. |
0e40b5f2 | 2156 | If TEMP is nonzero, we are forbidden to use any other scratch |
1d511ed5 EB |
2157 | registers. Otherwise, we are allowed to generate them as needed. |
2158 | ||
2159 | Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY | |
2160 | or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */ | |
bea5071f | 2161 | |
e0d80184 | 2162 | void |
1d511ed5 | 2163 | sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp) |
e0d80184 | 2164 | { |
1c49a3ed | 2165 | rtx cst, temp1, temp2, temp3, temp4, temp5; |
1d511ed5 | 2166 | rtx ti_temp = 0; |
3968de80 | 2167 | |
1c49a3ed EB |
2168 | /* Deal with too large offsets. */ |
2169 | if (GET_CODE (op1) == CONST | |
2170 | && GET_CODE (XEXP (op1, 0)) == PLUS | |
2171 | && CONST_INT_P (cst = XEXP (XEXP (op1, 0), 1)) | |
2172 | && trunc_int_for_mode (INTVAL (cst), SImode) != INTVAL (cst)) | |
2173 | { | |
2174 | gcc_assert (!temp); | |
2175 | temp1 = gen_reg_rtx (DImode); | |
2176 | temp2 = gen_reg_rtx (DImode); | |
2177 | sparc_emit_set_const64 (temp2, cst); | |
2178 | sparc_emit_set_symbolic_const64 (temp1, XEXP (XEXP (op1, 0), 0), | |
2179 | NULL_RTX); | |
2180 | emit_insn (gen_rtx_SET (op0, gen_rtx_PLUS (DImode, temp1, temp2))); | |
2181 | return; | |
2182 | } | |
2183 | ||
1d511ed5 | 2184 | if (temp && GET_MODE (temp) == TImode) |
3968de80 | 2185 | { |
1d511ed5 EB |
2186 | ti_temp = temp; |
2187 | temp = gen_rtx_REG (DImode, REGNO (temp)); | |
3968de80 DD |
2188 | } |
2189 | ||
1d511ed5 | 2190 | /* SPARC-V9 code-model support. */ |
e0d80184 | 2191 | switch (sparc_cmodel) |
284d86e9 | 2192 | { |
e0d80184 DM |
2193 | case CM_MEDLOW: |
2194 | /* The range spanned by all instructions in the object is less | |
2195 | than 2^31 bytes (2GB) and the distance from any instruction | |
2196 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
2197 | than 2^31 bytes (2GB). | |
ab835497 | 2198 | |
e0d80184 DM |
2199 | The executable must be in the low 4TB of the virtual address |
2200 | space. | |
61a55e8b | 2201 | |
1d511ed5 EB |
2202 | sethi %hi(symbol), %temp1 |
2203 | or %temp1, %lo(symbol), %reg */ | |
2204 | if (temp) | |
2205 | temp1 = temp; /* op0 is allowed. */ | |
2206 | else | |
2207 | temp1 = gen_reg_rtx (DImode); | |
2208 | ||
f7df4a84 RS |
2209 | emit_insn (gen_rtx_SET (temp1, gen_rtx_HIGH (DImode, op1))); |
2210 | emit_insn (gen_rtx_SET (op0, gen_rtx_LO_SUM (DImode, temp1, op1))); | |
e0d80184 | 2211 | break; |
61a55e8b | 2212 | |
e0d80184 DM |
2213 | case CM_MEDMID: |
2214 | /* The range spanned by all instructions in the object is less | |
2215 | than 2^31 bytes (2GB) and the distance from any instruction | |
2216 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
2217 | than 2^31 bytes (2GB). | |
2218 | ||
2219 | The executable must be in the low 16TB of the virtual address | |
2220 | space. | |
2221 | ||
2222 | sethi %h44(symbol), %temp1 | |
2223 | or %temp1, %m44(symbol), %temp2 | |
2224 | sllx %temp2, 12, %temp3 | |
2225 | or %temp3, %l44(symbol), %reg */ | |
1d511ed5 EB |
2226 | if (temp) |
2227 | { | |
2228 | temp1 = op0; | |
2229 | temp2 = op0; | |
2230 | temp3 = temp; /* op0 is allowed. */ | |
2231 | } | |
2232 | else | |
2233 | { | |
2234 | temp1 = gen_reg_rtx (DImode); | |
2235 | temp2 = gen_reg_rtx (DImode); | |
2236 | temp3 = gen_reg_rtx (DImode); | |
2237 | } | |
2238 | ||
2239 | emit_insn (gen_seth44 (temp1, op1)); | |
2240 | emit_insn (gen_setm44 (temp2, temp1, op1)); | |
f7df4a84 | 2241 | emit_insn (gen_rtx_SET (temp3, |
1d511ed5 EB |
2242 | gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12)))); |
2243 | emit_insn (gen_setl44 (op0, temp3, op1)); | |
e0d80184 | 2244 | break; |
61a55e8b | 2245 | |
e0d80184 DM |
2246 | case CM_MEDANY: |
2247 | /* The range spanned by all instructions in the object is less | |
2248 | than 2^31 bytes (2GB) and the distance from any instruction | |
2249 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
2250 | than 2^31 bytes (2GB). | |
2251 | ||
2252 | The executable can be placed anywhere in the virtual address | |
2253 | space. | |
2254 | ||
2255 | sethi %hh(symbol), %temp1 | |
2256 | sethi %lm(symbol), %temp2 | |
2257 | or %temp1, %hm(symbol), %temp3 | |
1d511ed5 EB |
2258 | sllx %temp3, 32, %temp4 |
2259 | or %temp4, %temp2, %temp5 | |
2260 | or %temp5, %lo(symbol), %reg */ | |
2261 | if (temp) | |
3968de80 | 2262 | { |
1d511ed5 EB |
2263 | /* It is possible that one of the registers we got for operands[2] |
2264 | might coincide with that of operands[0] (which is why we made | |
2265 | it TImode). Pick the other one to use as our scratch. */ | |
2266 | if (rtx_equal_p (temp, op0)) | |
2267 | { | |
f5f7d171 JM |
2268 | gcc_assert (ti_temp); |
2269 | temp = gen_rtx_REG (DImode, REGNO (temp) + 1); | |
1d511ed5 EB |
2270 | } |
2271 | temp1 = op0; | |
2272 | temp2 = temp; /* op0 is _not_ allowed, see above. */ | |
2273 | temp3 = op0; | |
2274 | temp4 = op0; | |
2275 | temp5 = op0; | |
2276 | } | |
2277 | else | |
2278 | { | |
2279 | temp1 = gen_reg_rtx (DImode); | |
2280 | temp2 = gen_reg_rtx (DImode); | |
2281 | temp3 = gen_reg_rtx (DImode); | |
2282 | temp4 = gen_reg_rtx (DImode); | |
2283 | temp5 = gen_reg_rtx (DImode); | |
3968de80 | 2284 | } |
61a55e8b | 2285 | |
1d511ed5 EB |
2286 | emit_insn (gen_sethh (temp1, op1)); |
2287 | emit_insn (gen_setlm (temp2, op1)); | |
2288 | emit_insn (gen_sethm (temp3, temp1, op1)); | |
f7df4a84 | 2289 | emit_insn (gen_rtx_SET (temp4, |
1d511ed5 | 2290 | gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32)))); |
f7df4a84 | 2291 | emit_insn (gen_rtx_SET (temp5, gen_rtx_PLUS (DImode, temp4, temp2))); |
1d511ed5 | 2292 | emit_insn (gen_setlo (op0, temp5, op1)); |
e0d80184 | 2293 | break; |
61a55e8b | 2294 | |
e0d80184 DM |
2295 | case CM_EMBMEDANY: |
2296 | /* Old old old backwards compatibility kruft here. | |
2297 | Essentially it is MEDLOW with a fixed 64-bit | |
2298 | virtual base added to all data segment addresses. | |
2299 | Text-segment stuff is computed like MEDANY, we can't | |
2300 | reuse the code above because the relocation knobs | |
2301 | look different. | |
2302 | ||
2303 | Data segment: sethi %hi(symbol), %temp1 | |
1d511ed5 EB |
2304 | add %temp1, EMBMEDANY_BASE_REG, %temp2 |
2305 | or %temp2, %lo(symbol), %reg */ | |
e0d80184 DM |
2306 | if (data_segment_operand (op1, GET_MODE (op1))) |
2307 | { | |
1d511ed5 EB |
2308 | if (temp) |
2309 | { | |
2310 | temp1 = temp; /* op0 is allowed. */ | |
2311 | temp2 = op0; | |
2312 | } | |
2313 | else | |
2314 | { | |
2315 | temp1 = gen_reg_rtx (DImode); | |
2316 | temp2 = gen_reg_rtx (DImode); | |
2317 | } | |
2318 | ||
e0d80184 | 2319 | emit_insn (gen_embmedany_sethi (temp1, op1)); |
1d511ed5 EB |
2320 | emit_insn (gen_embmedany_brsum (temp2, temp1)); |
2321 | emit_insn (gen_embmedany_losum (op0, temp2, op1)); | |
e0d80184 | 2322 | } |
1d511ed5 EB |
2323 | |
2324 | /* Text segment: sethi %uhi(symbol), %temp1 | |
2325 | sethi %hi(symbol), %temp2 | |
2326 | or %temp1, %ulo(symbol), %temp3 | |
2327 | sllx %temp3, 32, %temp4 | |
2328 | or %temp4, %temp2, %temp5 | |
2329 | or %temp5, %lo(symbol), %reg */ | |
e0d80184 DM |
2330 | else |
2331 | { | |
1d511ed5 | 2332 | if (temp) |
3968de80 | 2333 | { |
1d511ed5 EB |
2334 | /* It is possible that one of the registers we got for operands[2] |
2335 | might coincide with that of operands[0] (which is why we made | |
2336 | it TImode). Pick the other one to use as our scratch. */ | |
2337 | if (rtx_equal_p (temp, op0)) | |
2338 | { | |
f5f7d171 JM |
2339 | gcc_assert (ti_temp); |
2340 | temp = gen_rtx_REG (DImode, REGNO (temp) + 1); | |
1d511ed5 EB |
2341 | } |
2342 | temp1 = op0; | |
2343 | temp2 = temp; /* op0 is _not_ allowed, see above. */ | |
2344 | temp3 = op0; | |
2345 | temp4 = op0; | |
2346 | temp5 = op0; | |
2347 | } | |
2348 | else | |
2349 | { | |
2350 | temp1 = gen_reg_rtx (DImode); | |
2351 | temp2 = gen_reg_rtx (DImode); | |
2352 | temp3 = gen_reg_rtx (DImode); | |
2353 | temp4 = gen_reg_rtx (DImode); | |
2354 | temp5 = gen_reg_rtx (DImode); | |
3968de80 | 2355 | } |
61a55e8b | 2356 | |
1d511ed5 EB |
2357 | emit_insn (gen_embmedany_textuhi (temp1, op1)); |
2358 | emit_insn (gen_embmedany_texthi (temp2, op1)); | |
2359 | emit_insn (gen_embmedany_textulo (temp3, temp1, op1)); | |
f7df4a84 | 2360 | emit_insn (gen_rtx_SET (temp4, |
1d511ed5 | 2361 | gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32)))); |
f7df4a84 | 2362 | emit_insn (gen_rtx_SET (temp5, gen_rtx_PLUS (DImode, temp4, temp2))); |
1d511ed5 | 2363 | emit_insn (gen_embmedany_textlo (op0, temp5, op1)); |
e0d80184 DM |
2364 | } |
2365 | break; | |
2366 | ||
2367 | default: | |
f5f7d171 | 2368 | gcc_unreachable (); |
e0d80184 DM |
2369 | } |
2370 | } | |
2371 | ||
9208e4b2 DM |
2372 | /* These avoid problems when cross compiling. If we do not |
2373 | go through all this hair then the optimizer will see | |
2374 | invalid REG_EQUAL notes or in some cases none at all. */ | |
9bb3323d | 2375 | static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT); |
e80d5f80 KG |
2376 | static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT); |
2377 | static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT); | |
2378 | static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT); | |
9208e4b2 | 2379 | |
9208e4b2 DM |
2380 | /* The optimizer is not to assume anything about exactly |
2381 | which bits are set for a HIGH, they are unspecified. | |
2382 | Unfortunately this leads to many missed optimizations | |
2383 | during CSE. We mask out the non-HIGH bits, and matches | |
2384 | a plain movdi, to alleviate this problem. */ | |
9bb3323d EB |
2385 | static rtx |
2386 | gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val) | |
9208e4b2 | 2387 | { |
f7df4a84 | 2388 | return gen_rtx_SET (dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff)); |
9208e4b2 | 2389 | } |
2a01c939 | 2390 | |
e0d80184 | 2391 | static rtx |
fc27d102 | 2392 | gen_safe_SET64 (rtx dest, HOST_WIDE_INT val) |
61a55e8b | 2393 | { |
f7df4a84 | 2394 | return gen_rtx_SET (dest, GEN_INT (val)); |
9208e4b2 DM |
2395 | } |
2396 | ||
2397 | static rtx | |
fc27d102 | 2398 | gen_safe_OR64 (rtx src, HOST_WIDE_INT val) |
9208e4b2 | 2399 | { |
0e5d569c | 2400 | return gen_rtx_IOR (DImode, src, GEN_INT (val)); |
9208e4b2 DM |
2401 | } |
2402 | ||
2403 | static rtx | |
fc27d102 | 2404 | gen_safe_XOR64 (rtx src, HOST_WIDE_INT val) |
9208e4b2 | 2405 | { |
0e5d569c | 2406 | return gen_rtx_XOR (DImode, src, GEN_INT (val)); |
e0d80184 | 2407 | } |
61a55e8b | 2408 | |
e0d80184 DM |
2409 | /* Worker routines for 64-bit constant formation on arch64. |
2410 | One of the key things to be doing in these emissions is | |
2411 | to create as many temp REGs as possible. This makes it | |
2412 | possible for half-built constants to be used later when | |
2413 | such values are similar to something required later on. | |
2414 | Without doing this, the optimizer cannot see such | |
2415 | opportunities. */ | |
2a01c939 | 2416 | |
e80d5f80 KG |
2417 | static void sparc_emit_set_const64_quick1 (rtx, rtx, |
2418 | unsigned HOST_WIDE_INT, int); | |
2a01c939 | 2419 | |
e0d80184 | 2420 | static void |
fc27d102 KG |
2421 | sparc_emit_set_const64_quick1 (rtx op0, rtx temp, |
2422 | unsigned HOST_WIDE_INT low_bits, int is_neg) | |
e0d80184 | 2423 | { |
2a01c939 | 2424 | unsigned HOST_WIDE_INT high_bits; |
a9e27770 | 2425 | |
e0d80184 | 2426 | if (is_neg) |
2a01c939 | 2427 | high_bits = (~low_bits) & 0xffffffff; |
31bc9eba | 2428 | else |
e0d80184 | 2429 | high_bits = low_bits; |
31bc9eba | 2430 | |
9bb3323d | 2431 | emit_insn (gen_safe_HIGH64 (temp, high_bits)); |
e0d80184 | 2432 | if (!is_neg) |
5108f3e5 | 2433 | { |
f7df4a84 | 2434 | emit_insn (gen_rtx_SET (op0, gen_safe_OR64 (temp, (high_bits & 0x3ff)))); |
5108f3e5 | 2435 | } |
e0d80184 | 2436 | else |
5108f3e5 DM |
2437 | { |
2438 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
2439 | instead. This way the combiner will notice logical operations | |
2440 | such as ANDN later on and substitute. */ | |
2441 | if ((low_bits & 0x3ff) == 0x3ff) | |
2442 | { | |
f7df4a84 | 2443 | emit_insn (gen_rtx_SET (op0, gen_rtx_NOT (DImode, temp))); |
5108f3e5 DM |
2444 | } |
2445 | else | |
2446 | { | |
f7df4a84 | 2447 | emit_insn (gen_rtx_SET (op0, |
5108f3e5 | 2448 | gen_safe_XOR64 (temp, |
9e0625a3 AO |
2449 | (-(HOST_WIDE_INT)0x400 |
2450 | | (low_bits & 0x3ff))))); | |
5108f3e5 DM |
2451 | } |
2452 | } | |
e0d80184 | 2453 | } |
61a55e8b | 2454 | |
e80d5f80 KG |
2455 | static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT, |
2456 | unsigned HOST_WIDE_INT, int); | |
2a01c939 | 2457 | |
e0d80184 | 2458 | static void |
fc27d102 KG |
2459 | sparc_emit_set_const64_quick2 (rtx op0, rtx temp, |
2460 | unsigned HOST_WIDE_INT high_bits, | |
2461 | unsigned HOST_WIDE_INT low_immediate, | |
2462 | int shift_count) | |
e0d80184 DM |
2463 | { |
2464 | rtx temp2 = op0; | |
61a55e8b | 2465 | |
e0d80184 DM |
2466 | if ((high_bits & 0xfffffc00) != 0) |
2467 | { | |
9bb3323d | 2468 | emit_insn (gen_safe_HIGH64 (temp, high_bits)); |
e0d80184 | 2469 | if ((high_bits & ~0xfffffc00) != 0) |
f7df4a84 | 2470 | emit_insn (gen_rtx_SET (op0, |
9208e4b2 | 2471 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); |
61a55e8b | 2472 | else |
e0d80184 | 2473 | temp2 = temp; |
61a55e8b DE |
2474 | } |
2475 | else | |
2476 | { | |
f710f868 | 2477 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 DM |
2478 | temp2 = temp; |
2479 | } | |
61a55e8b | 2480 | |
80ffc95e | 2481 | /* Now shift it up into place. */ |
f7df4a84 RS |
2482 | emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, temp2, |
2483 | GEN_INT (shift_count)))); | |
61a55e8b | 2484 | |
e0d80184 DM |
2485 | /* If there is a low immediate part piece, finish up by |
2486 | putting that in as well. */ | |
2487 | if (low_immediate != 0) | |
f7df4a84 | 2488 | emit_insn (gen_rtx_SET (op0, gen_safe_OR64 (op0, low_immediate))); |
ab835497 RK |
2489 | } |
2490 | ||
e80d5f80 KG |
2491 | static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT, |
2492 | unsigned HOST_WIDE_INT); | |
2a01c939 | 2493 | |
e0d80184 DM |
2494 | /* Full 64-bit constant decomposition. Even though this is the |
2495 | 'worst' case, we still optimize a few things away. */ | |
2496 | static void | |
fc27d102 KG |
2497 | sparc_emit_set_const64_longway (rtx op0, rtx temp, |
2498 | unsigned HOST_WIDE_INT high_bits, | |
2499 | unsigned HOST_WIDE_INT low_bits) | |
ab835497 | 2500 | { |
cedced65 | 2501 | rtx sub_temp = op0; |
4bf7135b | 2502 | |
cedced65 | 2503 | if (can_create_pseudo_p ()) |
e0d80184 DM |
2504 | sub_temp = gen_reg_rtx (DImode); |
2505 | ||
2506 | if ((high_bits & 0xfffffc00) != 0) | |
2507 | { | |
9bb3323d | 2508 | emit_insn (gen_safe_HIGH64 (temp, high_bits)); |
e0d80184 | 2509 | if ((high_bits & ~0xfffffc00) != 0) |
f7df4a84 | 2510 | emit_insn (gen_rtx_SET (sub_temp, |
9208e4b2 | 2511 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); |
e0d80184 DM |
2512 | else |
2513 | sub_temp = temp; | |
2514 | } | |
2515 | else | |
ab835497 | 2516 | { |
f710f868 | 2517 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 | 2518 | sub_temp = temp; |
ab835497 | 2519 | } |
4bf7135b | 2520 | |
cedced65 | 2521 | if (can_create_pseudo_p ()) |
284d86e9 | 2522 | { |
e0d80184 DM |
2523 | rtx temp2 = gen_reg_rtx (DImode); |
2524 | rtx temp3 = gen_reg_rtx (DImode); | |
2525 | rtx temp4 = gen_reg_rtx (DImode); | |
284d86e9 | 2526 | |
f7df4a84 RS |
2527 | emit_insn (gen_rtx_SET (temp4, gen_rtx_ASHIFT (DImode, sub_temp, |
2528 | GEN_INT (32)))); | |
4bf7135b | 2529 | |
9bb3323d | 2530 | emit_insn (gen_safe_HIGH64 (temp2, low_bits)); |
e0d80184 | 2531 | if ((low_bits & ~0xfffffc00) != 0) |
f710f868 | 2532 | { |
f7df4a84 | 2533 | emit_insn (gen_rtx_SET (temp3, |
f710f868 | 2534 | gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); |
f7df4a84 | 2535 | emit_insn (gen_rtx_SET (op0, gen_rtx_PLUS (DImode, temp4, temp3))); |
f710f868 DM |
2536 | } |
2537 | else | |
2538 | { | |
f7df4a84 | 2539 | emit_insn (gen_rtx_SET (op0, gen_rtx_PLUS (DImode, temp4, temp2))); |
f710f868 | 2540 | } |
284d86e9 | 2541 | } |
e0d80184 DM |
2542 | else |
2543 | { | |
9208e4b2 DM |
2544 | rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); |
2545 | rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); | |
2546 | rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); | |
e0d80184 | 2547 | int to_shift = 12; |
284d86e9 | 2548 | |
e0d80184 DM |
2549 | /* We are in the middle of reload, so this is really |
2550 | painful. However we do still make an attempt to | |
5108f3e5 | 2551 | avoid emitting truly stupid code. */ |
e0d80184 DM |
2552 | if (low1 != const0_rtx) |
2553 | { | |
f7df4a84 RS |
2554 | emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, sub_temp, |
2555 | GEN_INT (to_shift)))); | |
2556 | emit_insn (gen_rtx_SET (op0, gen_rtx_IOR (DImode, op0, low1))); | |
e0d80184 DM |
2557 | sub_temp = op0; |
2558 | to_shift = 12; | |
2559 | } | |
2560 | else | |
2561 | { | |
2562 | to_shift += 12; | |
2563 | } | |
2564 | if (low2 != const0_rtx) | |
2565 | { | |
f7df4a84 RS |
2566 | emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, sub_temp, |
2567 | GEN_INT (to_shift)))); | |
2568 | emit_insn (gen_rtx_SET (op0, gen_rtx_IOR (DImode, op0, low2))); | |
e0d80184 DM |
2569 | sub_temp = op0; |
2570 | to_shift = 8; | |
2571 | } | |
2572 | else | |
2573 | { | |
2574 | to_shift += 8; | |
2575 | } | |
f7df4a84 RS |
2576 | emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, sub_temp, |
2577 | GEN_INT (to_shift)))); | |
e0d80184 | 2578 | if (low3 != const0_rtx) |
f7df4a84 | 2579 | emit_insn (gen_rtx_SET (op0, gen_rtx_IOR (DImode, op0, low3))); |
80ffc95e | 2580 | /* phew... */ |
e0d80184 | 2581 | } |
284d86e9 JC |
2582 | } |
2583 | ||
80ffc95e | 2584 | /* Analyze a 64-bit constant for certain properties. */ |
e80d5f80 KG |
2585 | static void analyze_64bit_constant (unsigned HOST_WIDE_INT, |
2586 | unsigned HOST_WIDE_INT, | |
2587 | int *, int *, int *); | |
2a01c939 | 2588 | |
e0d80184 | 2589 | static void |
fc27d102 KG |
2590 | analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits, |
2591 | unsigned HOST_WIDE_INT low_bits, | |
2592 | int *hbsp, int *lbsp, int *abbasp) | |
ab835497 | 2593 | { |
e0d80184 DM |
2594 | int lowest_bit_set, highest_bit_set, all_bits_between_are_set; |
2595 | int i; | |
ab835497 | 2596 | |
e0d80184 DM |
2597 | lowest_bit_set = highest_bit_set = -1; |
2598 | i = 0; | |
2599 | do | |
ab835497 | 2600 | { |
e0d80184 DM |
2601 | if ((lowest_bit_set == -1) |
2602 | && ((low_bits >> i) & 1)) | |
2603 | lowest_bit_set = i; | |
2604 | if ((highest_bit_set == -1) | |
2605 | && ((high_bits >> (32 - i - 1)) & 1)) | |
2606 | highest_bit_set = (64 - i - 1); | |
2607 | } | |
2608 | while (++i < 32 | |
2609 | && ((highest_bit_set == -1) | |
2610 | || (lowest_bit_set == -1))); | |
2611 | if (i == 32) | |
2612 | { | |
2613 | i = 0; | |
2614 | do | |
ab835497 | 2615 | { |
e0d80184 DM |
2616 | if ((lowest_bit_set == -1) |
2617 | && ((high_bits >> i) & 1)) | |
2618 | lowest_bit_set = i + 32; | |
2619 | if ((highest_bit_set == -1) | |
2620 | && ((low_bits >> (32 - i - 1)) & 1)) | |
2621 | highest_bit_set = 32 - i - 1; | |
ab835497 | 2622 | } |
e0d80184 DM |
2623 | while (++i < 32 |
2624 | && ((highest_bit_set == -1) | |
2625 | || (lowest_bit_set == -1))); | |
2626 | } | |
2627 | /* If there are no bits set this should have gone out | |
2628 | as one instruction! */ | |
f5f7d171 | 2629 | gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1); |
e0d80184 DM |
2630 | all_bits_between_are_set = 1; |
2631 | for (i = lowest_bit_set; i <= highest_bit_set; i++) | |
2632 | { | |
2633 | if (i < 32) | |
2634 | { | |
2635 | if ((low_bits & (1 << i)) != 0) | |
2636 | continue; | |
2637 | } | |
2638 | else | |
2639 | { | |
2640 | if ((high_bits & (1 << (i - 32))) != 0) | |
2641 | continue; | |
2642 | } | |
2643 | all_bits_between_are_set = 0; | |
2644 | break; | |
ab835497 | 2645 | } |
e0d80184 DM |
2646 | *hbsp = highest_bit_set; |
2647 | *lbsp = lowest_bit_set; | |
2648 | *abbasp = all_bits_between_are_set; | |
ab835497 | 2649 | } |
6a4bb1fa | 2650 | |
e80d5f80 | 2651 | static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT); |
2a01c939 | 2652 | |
e0d80184 | 2653 | static int |
fc27d102 KG |
2654 | const64_is_2insns (unsigned HOST_WIDE_INT high_bits, |
2655 | unsigned HOST_WIDE_INT low_bits) | |
e0d80184 DM |
2656 | { |
2657 | int highest_bit_set, lowest_bit_set, all_bits_between_are_set; | |
284d86e9 | 2658 | |
e0d80184 | 2659 | if (high_bits == 0 |
f451b552 | 2660 | || high_bits == 0xffffffff) |
e0d80184 | 2661 | return 1; |
6a4bb1fa | 2662 | |
e0d80184 DM |
2663 | analyze_64bit_constant (high_bits, low_bits, |
2664 | &highest_bit_set, &lowest_bit_set, | |
2665 | &all_bits_between_are_set); | |
6a4bb1fa | 2666 | |
f710f868 DM |
2667 | if ((highest_bit_set == 63 |
2668 | || lowest_bit_set == 0) | |
e0d80184 DM |
2669 | && all_bits_between_are_set != 0) |
2670 | return 1; | |
6a4bb1fa | 2671 | |
9208e4b2 DM |
2672 | if ((highest_bit_set - lowest_bit_set) < 21) |
2673 | return 1; | |
2674 | ||
6a4bb1fa DE |
2675 | return 0; |
2676 | } | |
2677 | ||
e80d5f80 KG |
2678 | static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT, |
2679 | unsigned HOST_WIDE_INT, | |
2680 | int, int); | |
2a01c939 DM |
2681 | |
2682 | static unsigned HOST_WIDE_INT | |
fc27d102 KG |
2683 | create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits, |
2684 | unsigned HOST_WIDE_INT low_bits, | |
2685 | int lowest_bit_set, int shift) | |
ab835497 | 2686 | { |
f710f868 | 2687 | HOST_WIDE_INT hi, lo; |
ab835497 | 2688 | |
e0d80184 DM |
2689 | if (lowest_bit_set < 32) |
2690 | { | |
2691 | lo = (low_bits >> lowest_bit_set) << shift; | |
2692 | hi = ((high_bits << (32 - lowest_bit_set)) << shift); | |
2693 | } | |
2694 | else | |
2695 | { | |
2696 | lo = 0; | |
2697 | hi = ((high_bits >> (lowest_bit_set - 32)) << shift); | |
2698 | } | |
f5f7d171 | 2699 | gcc_assert (! (hi & lo)); |
e0d80184 DM |
2700 | return (hi | lo); |
2701 | } | |
ab835497 | 2702 | |
e0d80184 DM |
2703 | /* Here we are sure to be arch64 and this is an integer constant |
2704 | being loaded into a register. Emit the most efficient | |
2705 | insn sequence possible. Detection of all the 1-insn cases | |
2706 | has been done already. */ | |
d9816849 | 2707 | static void |
fc27d102 | 2708 | sparc_emit_set_const64 (rtx op0, rtx op1) |
e0d80184 | 2709 | { |
2a01c939 | 2710 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
2711 | int lowest_bit_set, highest_bit_set; |
2712 | int all_bits_between_are_set; | |
1d511ed5 | 2713 | rtx temp = 0; |
ab835497 | 2714 | |
e0d80184 | 2715 | /* Sanity check that we know what we are working with. */ |
bea5071f EB |
2716 | gcc_assert (TARGET_ARCH64 |
2717 | && (GET_CODE (op0) == SUBREG | |
2718 | || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0))))); | |
380f6ad3 | 2719 | |
cedced65 | 2720 | if (! can_create_pseudo_p ()) |
f710f868 | 2721 | temp = op0; |
f710f868 | 2722 | |
0e5d569c | 2723 | if (GET_CODE (op1) != CONST_INT) |
e0d80184 | 2724 | { |
5f78aa30 JC |
2725 | sparc_emit_set_symbolic_const64 (op0, op1, temp); |
2726 | return; | |
e0d80184 | 2727 | } |
ab835497 | 2728 | |
1d511ed5 EB |
2729 | if (! temp) |
2730 | temp = gen_reg_rtx (DImode); | |
2731 | ||
0e5d569c EB |
2732 | high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); |
2733 | low_bits = (INTVAL (op1) & 0xffffffff); | |
ab835497 | 2734 | |
e0d80184 DM |
2735 | /* low_bits bits 0 --> 31 |
2736 | high_bits bits 32 --> 63 */ | |
ab835497 | 2737 | |
e0d80184 DM |
2738 | analyze_64bit_constant (high_bits, low_bits, |
2739 | &highest_bit_set, &lowest_bit_set, | |
2740 | &all_bits_between_are_set); | |
2741 | ||
2742 | /* First try for a 2-insn sequence. */ | |
2743 | ||
2744 | /* These situations are preferred because the optimizer can | |
2745 | * do more things with them: | |
2746 | * 1) mov -1, %reg | |
2747 | * sllx %reg, shift, %reg | |
2748 | * 2) mov -1, %reg | |
2749 | * srlx %reg, shift, %reg | |
2750 | * 3) mov some_small_const, %reg | |
2751 | * sllx %reg, shift, %reg | |
2752 | */ | |
2753 | if (((highest_bit_set == 63 | |
2754 | || lowest_bit_set == 0) | |
2755 | && all_bits_between_are_set != 0) | |
2a01c939 | 2756 | || ((highest_bit_set - lowest_bit_set) < 12)) |
e0d80184 | 2757 | { |
9208e4b2 | 2758 | HOST_WIDE_INT the_const = -1; |
e0d80184 DM |
2759 | int shift = lowest_bit_set; |
2760 | ||
f710f868 DM |
2761 | if ((highest_bit_set != 63 |
2762 | && lowest_bit_set != 0) | |
2763 | || all_bits_between_are_set == 0) | |
ab835497 | 2764 | { |
e0d80184 | 2765 | the_const = |
9208e4b2 | 2766 | create_simple_focus_bits (high_bits, low_bits, |
9208e4b2 | 2767 | lowest_bit_set, 0); |
ab835497 | 2768 | } |
e0d80184 | 2769 | else if (lowest_bit_set == 0) |
9208e4b2 | 2770 | shift = -(63 - highest_bit_set); |
e0d80184 | 2771 | |
f5f7d171 JM |
2772 | gcc_assert (SPARC_SIMM13_P (the_const)); |
2773 | gcc_assert (shift != 0); | |
f710f868 | 2774 | |
9208e4b2 | 2775 | emit_insn (gen_safe_SET64 (temp, the_const)); |
e0d80184 | 2776 | if (shift > 0) |
f7df4a84 RS |
2777 | emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, temp, |
2778 | GEN_INT (shift)))); | |
e0d80184 | 2779 | else if (shift < 0) |
f7df4a84 RS |
2780 | emit_insn (gen_rtx_SET (op0, gen_rtx_LSHIFTRT (DImode, temp, |
2781 | GEN_INT (-shift)))); | |
e0d80184 DM |
2782 | return; |
2783 | } | |
ab835497 | 2784 | |
e0d80184 DM |
2785 | /* Now a range of 22 or less bits set somewhere. |
2786 | * 1) sethi %hi(focus_bits), %reg | |
2787 | * sllx %reg, shift, %reg | |
2788 | * 2) sethi %hi(focus_bits), %reg | |
2789 | * srlx %reg, shift, %reg | |
2790 | */ | |
2a01c939 | 2791 | if ((highest_bit_set - lowest_bit_set) < 21) |
e0d80184 | 2792 | { |
2a01c939 | 2793 | unsigned HOST_WIDE_INT focus_bits = |
e0d80184 | 2794 | create_simple_focus_bits (high_bits, low_bits, |
ddf80874 | 2795 | lowest_bit_set, 10); |
f710f868 | 2796 | |
f5f7d171 JM |
2797 | gcc_assert (SPARC_SETHI_P (focus_bits)); |
2798 | gcc_assert (lowest_bit_set != 10); | |
f710f868 | 2799 | |
9bb3323d | 2800 | emit_insn (gen_safe_HIGH64 (temp, focus_bits)); |
e0d80184 | 2801 | |
9208e4b2 | 2802 | /* If lowest_bit_set == 10 then a sethi alone could have done it. */ |
e0d80184 | 2803 | if (lowest_bit_set < 10) |
f7df4a84 | 2804 | emit_insn (gen_rtx_SET (op0, |
9208e4b2 | 2805 | gen_rtx_LSHIFTRT (DImode, temp, |
e0d80184 | 2806 | GEN_INT (10 - lowest_bit_set)))); |
9208e4b2 | 2807 | else if (lowest_bit_set > 10) |
f7df4a84 | 2808 | emit_insn (gen_rtx_SET (op0, |
e0d80184 DM |
2809 | gen_rtx_ASHIFT (DImode, temp, |
2810 | GEN_INT (lowest_bit_set - 10)))); | |
e0d80184 DM |
2811 | return; |
2812 | } | |
2813 | ||
2814 | /* 1) sethi %hi(low_bits), %reg | |
2815 | * or %reg, %lo(low_bits), %reg | |
2816 | * 2) sethi %hi(~low_bits), %reg | |
2817 | * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg | |
2818 | */ | |
2819 | if (high_bits == 0 | |
2a01c939 | 2820 | || high_bits == 0xffffffff) |
5f78aa30 JC |
2821 | { |
2822 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, | |
2823 | (high_bits == 0xffffffff)); | |
2824 | return; | |
2825 | } | |
e0d80184 | 2826 | |
f710f868 DM |
2827 | /* Now, try 3-insn sequences. */ |
2828 | ||
e0d80184 DM |
2829 | /* 1) sethi %hi(high_bits), %reg |
2830 | * or %reg, %lo(high_bits), %reg | |
2831 | * sllx %reg, 32, %reg | |
2832 | */ | |
f710f868 | 2833 | if (low_bits == 0) |
5f78aa30 | 2834 | { |
f710f868 | 2835 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); |
5f78aa30 JC |
2836 | return; |
2837 | } | |
e0d80184 | 2838 | |
f710f868 DM |
2839 | /* We may be able to do something quick |
2840 | when the constant is negated, so try that. */ | |
e0d80184 DM |
2841 | if (const64_is_2insns ((~high_bits) & 0xffffffff, |
2842 | (~low_bits) & 0xfffffc00)) | |
2843 | { | |
5108f3e5 DM |
2844 | /* NOTE: The trailing bits get XOR'd so we need the |
2845 | non-negated bits, not the negated ones. */ | |
2846 | unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; | |
e0d80184 DM |
2847 | |
2848 | if ((((~high_bits) & 0xffffffff) == 0 | |
2849 | && ((~low_bits) & 0x80000000) == 0) | |
2850 | || (((~high_bits) & 0xffffffff) == 0xffffffff | |
2851 | && ((~low_bits) & 0x80000000) != 0)) | |
ab835497 | 2852 | { |
0e5d569c | 2853 | unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff); |
e0d80184 | 2854 | |
5108f3e5 DM |
2855 | if ((SPARC_SETHI_P (fast_int) |
2856 | && (~high_bits & 0xffffffff) == 0) | |
2857 | || SPARC_SIMM13_P (fast_int)) | |
9208e4b2 | 2858 | emit_insn (gen_safe_SET64 (temp, fast_int)); |
ab835497 | 2859 | else |
0e5d569c | 2860 | sparc_emit_set_const64 (temp, GEN_INT (fast_int)); |
ab835497 | 2861 | } |
e0d80184 DM |
2862 | else |
2863 | { | |
2864 | rtx negated_const; | |
e0d80184 DM |
2865 | negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | |
2866 | (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); | |
e0d80184 DM |
2867 | sparc_emit_set_const64 (temp, negated_const); |
2868 | } | |
5108f3e5 DM |
2869 | |
2870 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
2871 | instead. This way the combiner will notice logical operations | |
2872 | such as ANDN later on and substitute. */ | |
2873 | if (trailing_bits == 0x3ff) | |
2874 | { | |
f7df4a84 | 2875 | emit_insn (gen_rtx_SET (op0, gen_rtx_NOT (DImode, temp))); |
5108f3e5 DM |
2876 | } |
2877 | else | |
2878 | { | |
f7df4a84 | 2879 | emit_insn (gen_rtx_SET (op0, |
5108f3e5 DM |
2880 | gen_safe_XOR64 (temp, |
2881 | (-0x400 | trailing_bits)))); | |
2882 | } | |
e0d80184 | 2883 | return; |
ab835497 | 2884 | } |
ab835497 | 2885 | |
e0d80184 DM |
2886 | /* 1) sethi %hi(xxx), %reg |
2887 | * or %reg, %lo(xxx), %reg | |
2888 | * sllx %reg, yyy, %reg | |
f710f868 DM |
2889 | * |
2890 | * ??? This is just a generalized version of the low_bits==0 | |
2891 | * thing above, FIXME... | |
e0d80184 DM |
2892 | */ |
2893 | if ((highest_bit_set - lowest_bit_set) < 32) | |
2894 | { | |
f710f868 DM |
2895 | unsigned HOST_WIDE_INT focus_bits = |
2896 | create_simple_focus_bits (high_bits, low_bits, | |
ddf80874 | 2897 | lowest_bit_set, 0); |
ab835497 | 2898 | |
e0d80184 | 2899 | /* We can't get here in this state. */ |
f5f7d171 | 2900 | gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32); |
95726648 | 2901 | |
e0d80184 DM |
2902 | /* So what we know is that the set bits straddle the |
2903 | middle of the 64-bit word. */ | |
5f78aa30 JC |
2904 | sparc_emit_set_const64_quick2 (op0, temp, |
2905 | focus_bits, 0, | |
2906 | lowest_bit_set); | |
2907 | return; | |
e0d80184 | 2908 | } |
c85f7c16 | 2909 | |
f710f868 DM |
2910 | /* 1) sethi %hi(high_bits), %reg |
2911 | * or %reg, %lo(high_bits), %reg | |
2912 | * sllx %reg, 32, %reg | |
2913 | * or %reg, low_bits, %reg | |
2914 | */ | |
eaac029f | 2915 | if (SPARC_SIMM13_P (low_bits) && ((int)low_bits > 0)) |
f710f868 DM |
2916 | { |
2917 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); | |
2918 | return; | |
2919 | } | |
2920 | ||
80ffc95e | 2921 | /* The easiest way when all else fails, is full decomposition. */ |
e0d80184 | 2922 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); |
c85f7c16 JL |
2923 | } |
2924 | ||
ff7e7ee0 EB |
2925 | /* Implement TARGET_FIXED_CONDITION_CODE_REGS. */ |
2926 | ||
2927 | static bool | |
2928 | sparc_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) | |
2929 | { | |
2930 | *p1 = SPARC_ICC_REG; | |
2931 | *p2 = SPARC_FCC_REG; | |
2932 | return true; | |
2933 | } | |
2934 | ||
894d8b41 EB |
2935 | /* Implement TARGET_MIN_ARITHMETIC_PRECISION. */ |
2936 | ||
2937 | static unsigned int | |
2938 | sparc_min_arithmetic_precision (void) | |
2939 | { | |
2940 | return 32; | |
2941 | } | |
2942 | ||
e267e177 RH |
2943 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
2944 | return the mode to be used for the comparison. For floating-point, | |
ff7e7ee0 | 2945 | CCFP[E]mode is used. CCNZmode should be used when the first operand |
e267e177 RH |
2946 | is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special |
2947 | processing is needed. */ | |
2948 | ||
ef4bddc2 | 2949 | machine_mode |
ff7e7ee0 | 2950 | select_cc_mode (enum rtx_code op, rtx x, rtx y) |
e267e177 RH |
2951 | { |
2952 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2953 | { | |
2954 | switch (op) | |
2955 | { | |
2956 | case EQ: | |
2957 | case NE: | |
2958 | case UNORDERED: | |
2959 | case ORDERED: | |
2960 | case UNLT: | |
2961 | case UNLE: | |
2962 | case UNGT: | |
2963 | case UNGE: | |
2964 | case UNEQ: | |
7913f3d0 | 2965 | case LTGT: |
e267e177 RH |
2966 | return CCFPmode; |
2967 | ||
2968 | case LT: | |
2969 | case LE: | |
2970 | case GT: | |
2971 | case GE: | |
2972 | return CCFPEmode; | |
2973 | ||
2974 | default: | |
f5f7d171 | 2975 | gcc_unreachable (); |
e267e177 RH |
2976 | } |
2977 | } | |
85729229 EB |
2978 | else if ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS |
2979 | || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) | |
2980 | && y == const0_rtx) | |
e267e177 RH |
2981 | { |
2982 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
ff7e7ee0 | 2983 | return CCXNZmode; |
e267e177 | 2984 | else |
ff7e7ee0 | 2985 | return CCNZmode; |
e267e177 RH |
2986 | } |
2987 | else | |
2988 | { | |
ff7e7ee0 EB |
2989 | /* This is for the cmp<mode>_sne pattern. */ |
2990 | if (GET_CODE (x) == NOT && y == constm1_rtx) | |
2991 | { | |
2992 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
2993 | return CCXCmode; | |
2994 | else | |
2995 | return CCCmode; | |
2996 | } | |
2997 | ||
85729229 EB |
2998 | /* This is for the [u]addvdi4_sp32 and [u]subvdi4_sp32 patterns. */ |
2999 | if (!TARGET_ARCH64 && GET_MODE (x) == DImode) | |
3000 | { | |
3001 | if (GET_CODE (y) == UNSPEC | |
3002 | && (XINT (y, 1) == UNSPEC_ADDV | |
3003 | || XINT (y, 1) == UNSPEC_SUBV | |
3004 | || XINT (y, 1) == UNSPEC_NEGV)) | |
3005 | return CCVmode; | |
3006 | else | |
3007 | return CCCmode; | |
3008 | } | |
3009 | ||
e267e177 RH |
3010 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) |
3011 | return CCXmode; | |
3012 | else | |
3013 | return CCmode; | |
3014 | } | |
3015 | } | |
3016 | ||
f90b7a5a PB |
3017 | /* Emit the compare insn and return the CC reg for a CODE comparison |
3018 | with operands X and Y. */ | |
c85f7c16 | 3019 | |
f90b7a5a PB |
3020 | static rtx |
3021 | gen_compare_reg_1 (enum rtx_code code, rtx x, rtx y) | |
c85f7c16 | 3022 | { |
ef4bddc2 | 3023 | machine_mode mode; |
f90b7a5a | 3024 | rtx cc_reg; |
c85f7c16 | 3025 | |
f90b7a5a PB |
3026 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) |
3027 | return x; | |
65c5ae8b | 3028 | |
65c5ae8b | 3029 | mode = SELECT_CC_MODE (code, x, y); |
8ec11fe9 | 3030 | |
e0d80184 DM |
3031 | /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the |
3032 | fcc regs (cse can't tell they're really call clobbered regs and will | |
3033 | remove a duplicate comparison even if there is an intervening function | |
3034 | call - it will then try to reload the cc reg via an int reg which is why | |
3035 | we need the movcc patterns). It is possible to provide the movcc | |
3036 | patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two | |
3037 | registers (say %g1,%g5) and it takes about 6 insns. A better fix would be | |
3038 | to tell cse that CCFPE mode registers (even pseudos) are call | |
3039 | clobbered. */ | |
c85f7c16 | 3040 | |
e0d80184 DM |
3041 | /* ??? This is an experiment. Rather than making changes to cse which may |
3042 | or may not be easy/clean, we do our own cse. This is possible because | |
3043 | we will generate hard registers. Cse knows they're call clobbered (it | |
3044 | doesn't know the same thing about pseudos). If we guess wrong, no big | |
3045 | deal, but if we win, great! */ | |
c85f7c16 | 3046 | |
e0d80184 DM |
3047 | if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) |
3048 | #if 1 /* experiment */ | |
284d86e9 | 3049 | { |
e0d80184 DM |
3050 | int reg; |
3051 | /* We cycle through the registers to ensure they're all exercised. */ | |
3052 | static int next_fcc_reg = 0; | |
3053 | /* Previous x,y for each fcc reg. */ | |
3054 | static rtx prev_args[4][2]; | |
284d86e9 | 3055 | |
e0d80184 DM |
3056 | /* Scan prev_args for x,y. */ |
3057 | for (reg = 0; reg < 4; reg++) | |
3058 | if (prev_args[reg][0] == x && prev_args[reg][1] == y) | |
3059 | break; | |
3060 | if (reg == 4) | |
3061 | { | |
3062 | reg = next_fcc_reg; | |
3063 | prev_args[reg][0] = x; | |
3064 | prev_args[reg][1] = y; | |
3065 | next_fcc_reg = (next_fcc_reg + 1) & 3; | |
3066 | } | |
3067 | cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); | |
284d86e9 | 3068 | } |
e0d80184 DM |
3069 | #else |
3070 | cc_reg = gen_reg_rtx (mode); | |
3071 | #endif /* ! experiment */ | |
3072 | else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
3073 | cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); | |
3074 | else | |
3075 | cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); | |
284d86e9 | 3076 | |
19047e4a EB |
3077 | /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this |
3078 | will only result in an unrecognizable insn so no point in asserting. */ | |
f7df4a84 | 3079 | emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (mode, x, y))); |
c85f7c16 | 3080 | |
e0d80184 DM |
3081 | return cc_reg; |
3082 | } | |
c85f7c16 | 3083 | |
f90b7a5a PB |
3084 | |
3085 | /* Emit the compare insn and return the CC reg for the comparison in CMP. */ | |
19047e4a EB |
3086 | |
3087 | rtx | |
f90b7a5a | 3088 | gen_compare_reg (rtx cmp) |
19047e4a | 3089 | { |
f90b7a5a | 3090 | return gen_compare_reg_1 (GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1)); |
19047e4a EB |
3091 | } |
3092 | ||
e0d80184 | 3093 | /* This function is used for v9 only. |
f90b7a5a | 3094 | DEST is the target of the Scc insn. |
e0d80184 | 3095 | CODE is the code for an Scc's comparison. |
f90b7a5a | 3096 | X and Y are the values we compare. |
c85f7c16 | 3097 | |
e0d80184 | 3098 | This function is needed to turn |
ab835497 | 3099 | |
e0d80184 DM |
3100 | (set (reg:SI 110) |
3101 | (gt (reg:CCX 100 %icc) | |
3102 | (const_int 0))) | |
3103 | into | |
3104 | (set (reg:SI 110) | |
3105 | (gt:DI (reg:CCX 100 %icc) | |
3106 | (const_int 0))) | |
3107 | ||
3108 | IE: The instruction recognizer needs to see the mode of the comparison to | |
3109 | find the right instruction. We could use "gt:DI" right in the | |
f90b7a5a | 3110 | define_expand, but leaving it out allows us to handle DI, SI, etc. */ |
ab835497 | 3111 | |
f90b7a5a PB |
3112 | static int |
3113 | gen_v9_scc (rtx dest, enum rtx_code compare_code, rtx x, rtx y) | |
ab835497 | 3114 | { |
e0d80184 | 3115 | if (! TARGET_ARCH64 |
f90b7a5a PB |
3116 | && (GET_MODE (x) == DImode |
3117 | || GET_MODE (dest) == DImode)) | |
e0d80184 | 3118 | return 0; |
7e2feebf | 3119 | |
e0d80184 DM |
3120 | /* Try to use the movrCC insns. */ |
3121 | if (TARGET_ARCH64 | |
f90b7a5a PB |
3122 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT |
3123 | && y == const0_rtx | |
e0d80184 | 3124 | && v9_regcmp_p (compare_code)) |
ab835497 | 3125 | { |
f90b7a5a | 3126 | rtx op0 = x; |
7e04157d DM |
3127 | rtx temp; |
3128 | ||
e0d80184 | 3129 | /* Special case for op0 != 0. This can be done with one instruction if |
f90b7a5a | 3130 | dest == x. */ |
e0d80184 DM |
3131 | |
3132 | if (compare_code == NE | |
f90b7a5a PB |
3133 | && GET_MODE (dest) == DImode |
3134 | && rtx_equal_p (op0, dest)) | |
ab835497 | 3135 | { |
f7df4a84 | 3136 | emit_insn (gen_rtx_SET (dest, |
e0d80184 DM |
3137 | gen_rtx_IF_THEN_ELSE (DImode, |
3138 | gen_rtx_fmt_ee (compare_code, DImode, | |
3139 | op0, const0_rtx), | |
3140 | const1_rtx, | |
f90b7a5a | 3141 | dest))); |
ab835497 RK |
3142 | return 1; |
3143 | } | |
e0d80184 | 3144 | |
f90b7a5a | 3145 | if (reg_overlap_mentioned_p (dest, op0)) |
a42519be | 3146 | { |
f90b7a5a | 3147 | /* Handle the case where dest == x. |
a42519be | 3148 | We "early clobber" the result. */ |
f90b7a5a PB |
3149 | op0 = gen_reg_rtx (GET_MODE (x)); |
3150 | emit_move_insn (op0, x); | |
a42519be JJ |
3151 | } |
3152 | ||
f7df4a84 | 3153 | emit_insn (gen_rtx_SET (dest, const0_rtx)); |
e0d80184 | 3154 | if (GET_MODE (op0) != DImode) |
ab835497 | 3155 | { |
e0d80184 DM |
3156 | temp = gen_reg_rtx (DImode); |
3157 | convert_move (temp, op0, 0); | |
ab835497 | 3158 | } |
e0d80184 DM |
3159 | else |
3160 | temp = op0; | |
f7df4a84 | 3161 | emit_insn (gen_rtx_SET (dest, |
f90b7a5a | 3162 | gen_rtx_IF_THEN_ELSE (GET_MODE (dest), |
e0d80184 DM |
3163 | gen_rtx_fmt_ee (compare_code, DImode, |
3164 | temp, const0_rtx), | |
3165 | const1_rtx, | |
f90b7a5a | 3166 | dest))); |
95726648 DE |
3167 | return 1; |
3168 | } | |
e0d80184 | 3169 | else |
ab835497 | 3170 | { |
f90b7a5a PB |
3171 | x = gen_compare_reg_1 (compare_code, x, y); |
3172 | y = const0_rtx; | |
ab835497 | 3173 | |
f7df4a84 RS |
3174 | emit_insn (gen_rtx_SET (dest, const0_rtx)); |
3175 | emit_insn (gen_rtx_SET (dest, | |
f90b7a5a | 3176 | gen_rtx_IF_THEN_ELSE (GET_MODE (dest), |
e0d80184 | 3177 | gen_rtx_fmt_ee (compare_code, |
f90b7a5a PB |
3178 | GET_MODE (x), x, y), |
3179 | const1_rtx, dest))); | |
e0d80184 | 3180 | return 1; |
ab835497 | 3181 | } |
ab835497 | 3182 | } |
4fb4e4b8 | 3183 | |
f90b7a5a PB |
3184 | |
3185 | /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this | |
3186 | without jumps using the addx/subx instructions. */ | |
3187 | ||
3188 | bool | |
3189 | emit_scc_insn (rtx operands[]) | |
3190 | { | |
ff7e7ee0 | 3191 | rtx tem, x, y; |
f90b7a5a | 3192 | enum rtx_code code; |
ff7e7ee0 | 3193 | machine_mode mode; |
f90b7a5a PB |
3194 | |
3195 | /* The quad-word fp compare library routines all return nonzero to indicate | |
3196 | true, which is different from the equivalent libgcc routines, so we must | |
3197 | handle them specially here. */ | |
3198 | if (GET_MODE (operands[2]) == TFmode && ! TARGET_HARD_QUAD) | |
3199 | { | |
3200 | operands[1] = sparc_emit_float_lib_cmp (operands[2], operands[3], | |
3201 | GET_CODE (operands[1])); | |
3202 | operands[2] = XEXP (operands[1], 0); | |
3203 | operands[3] = XEXP (operands[1], 1); | |
3204 | } | |
3205 | ||
3206 | code = GET_CODE (operands[1]); | |
3207 | x = operands[2]; | |
3208 | y = operands[3]; | |
ff7e7ee0 | 3209 | mode = GET_MODE (x); |
f90b7a5a PB |
3210 | |
3211 | /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has | |
3212 | more applications). The exception to this is "reg != 0" which can | |
3213 | be done in one instruction on v9 (so we do it). */ | |
ff7e7ee0 | 3214 | if ((code == EQ || code == NE) && (mode == SImode || mode == DImode)) |
f90b7a5a | 3215 | { |
ff7e7ee0 EB |
3216 | if (y != const0_rtx) |
3217 | x = force_reg (mode, gen_rtx_XOR (mode, x, y)); | |
f90b7a5a | 3218 | |
ff7e7ee0 EB |
3219 | rtx pat = gen_rtx_SET (operands[0], |
3220 | gen_rtx_fmt_ee (code, GET_MODE (operands[0]), | |
3221 | x, const0_rtx)); | |
3222 | ||
4803de58 EB |
3223 | /* If we can use addx/subx or addxc, add a clobber for CC. */ |
3224 | if (mode == SImode || (code == NE && TARGET_VIS3)) | |
ff7e7ee0 EB |
3225 | { |
3226 | rtx clobber | |
3227 | = gen_rtx_CLOBBER (VOIDmode, | |
3228 | gen_rtx_REG (mode == SImode ? CCmode : CCXmode, | |
3229 | SPARC_ICC_REG)); | |
3230 | pat = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clobber)); | |
3231 | } | |
3232 | ||
3233 | emit_insn (pat); | |
3234 | return true; | |
f90b7a5a PB |
3235 | } |
3236 | ||
4803de58 | 3237 | /* We can do LTU in DImode using the addxc instruction with VIS3. */ |
ff7e7ee0 EB |
3238 | if (TARGET_ARCH64 |
3239 | && mode == DImode | |
3240 | && !((code == LTU || code == GTU) && TARGET_VIS3) | |
78968b76 DM |
3241 | && gen_v9_scc (operands[0], code, x, y)) |
3242 | return true; | |
3243 | ||
f90b7a5a PB |
3244 | /* We can do LTU and GEU using the addx/subx instructions too. And |
3245 | for GTU/LEU, if both operands are registers swap them and fall | |
3246 | back to the easy case. */ | |
3247 | if (code == GTU || code == LEU) | |
3248 | { | |
3249 | if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG) | |
3250 | && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG)) | |
3251 | { | |
3252 | tem = x; | |
3253 | x = y; | |
3254 | y = tem; | |
3255 | code = swap_condition (code); | |
3256 | } | |
3257 | } | |
3258 | ||
ff7e7ee0 | 3259 | if (code == LTU || code == GEU) |
f90b7a5a | 3260 | { |
f7df4a84 | 3261 | emit_insn (gen_rtx_SET (operands[0], |
42e37616 | 3262 | gen_rtx_fmt_ee (code, GET_MODE (operands[0]), |
f90b7a5a PB |
3263 | gen_compare_reg_1 (code, x, y), |
3264 | const0_rtx))); | |
3265 | return true; | |
3266 | } | |
3267 | ||
9aa6a9b5 DM |
3268 | /* All the posibilities to use addx/subx based sequences has been |
3269 | exhausted, try for a 3 instruction sequence using v9 conditional | |
3270 | moves. */ | |
3271 | if (TARGET_V9 && gen_v9_scc (operands[0], code, x, y)) | |
3272 | return true; | |
3273 | ||
f90b7a5a PB |
3274 | /* Nope, do branches. */ |
3275 | return false; | |
3276 | } | |
3277 | ||
e0d80184 DM |
3278 | /* Emit a conditional jump insn for the v9 architecture using comparison code |
3279 | CODE and jump target LABEL. | |
3280 | This function exists to take advantage of the v9 brxx insns. */ | |
ab835497 | 3281 | |
f90b7a5a | 3282 | static void |
fc27d102 | 3283 | emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label) |
ab835497 | 3284 | { |
f7df4a84 | 3285 | emit_jump_insn (gen_rtx_SET (pc_rtx, |
e0d80184 DM |
3286 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
3287 | gen_rtx_fmt_ee (code, GET_MODE (op0), | |
3288 | op0, const0_rtx), | |
3289 | gen_rtx_LABEL_REF (VOIDmode, label), | |
3290 | pc_rtx))); | |
3291 | } | |
7b1ac798 | 3292 | |
8b98b5fd DM |
3293 | /* Emit a conditional jump insn for the UA2011 architecture using |
3294 | comparison code CODE and jump target LABEL. This function exists | |
3295 | to take advantage of the UA2011 Compare and Branch insns. */ | |
3296 | ||
3297 | static void | |
3298 | emit_cbcond_insn (enum rtx_code code, rtx op0, rtx op1, rtx label) | |
3299 | { | |
3300 | rtx if_then_else; | |
3301 | ||
3302 | if_then_else = gen_rtx_IF_THEN_ELSE (VOIDmode, | |
3303 | gen_rtx_fmt_ee(code, GET_MODE(op0), | |
3304 | op0, op1), | |
3305 | gen_rtx_LABEL_REF (VOIDmode, label), | |
3306 | pc_rtx); | |
3307 | ||
f7df4a84 | 3308 | emit_jump_insn (gen_rtx_SET (pc_rtx, if_then_else)); |
8b98b5fd DM |
3309 | } |
3310 | ||
f90b7a5a PB |
3311 | void |
3312 | emit_conditional_branch_insn (rtx operands[]) | |
3313 | { | |
3314 | /* The quad-word fp compare library routines all return nonzero to indicate | |
3315 | true, which is different from the equivalent libgcc routines, so we must | |
3316 | handle them specially here. */ | |
3317 | if (GET_MODE (operands[1]) == TFmode && ! TARGET_HARD_QUAD) | |
3318 | { | |
3319 | operands[0] = sparc_emit_float_lib_cmp (operands[1], operands[2], | |
3320 | GET_CODE (operands[0])); | |
3321 | operands[1] = XEXP (operands[0], 0); | |
3322 | operands[2] = XEXP (operands[0], 1); | |
3323 | } | |
3324 | ||
8b98b5fd DM |
3325 | /* If we can tell early on that the comparison is against a constant |
3326 | that won't fit in the 5-bit signed immediate field of a cbcond, | |
3327 | use one of the other v9 conditional branch sequences. */ | |
3328 | if (TARGET_CBCOND | |
3329 | && GET_CODE (operands[1]) == REG | |
3330 | && (GET_MODE (operands[1]) == SImode | |
3331 | || (TARGET_ARCH64 && GET_MODE (operands[1]) == DImode)) | |
3332 | && (GET_CODE (operands[2]) != CONST_INT | |
3333 | || SPARC_SIMM5_P (INTVAL (operands[2])))) | |
3334 | { | |
3335 | emit_cbcond_insn (GET_CODE (operands[0]), operands[1], operands[2], operands[3]); | |
3336 | return; | |
3337 | } | |
3338 | ||
f90b7a5a PB |
3339 | if (TARGET_ARCH64 && operands[2] == const0_rtx |
3340 | && GET_CODE (operands[1]) == REG | |
3341 | && GET_MODE (operands[1]) == DImode) | |
3342 | { | |
3343 | emit_v9_brxx_insn (GET_CODE (operands[0]), operands[1], operands[3]); | |
3344 | return; | |
3345 | } | |
3346 | ||
3347 | operands[1] = gen_compare_reg (operands[0]); | |
3348 | operands[2] = const0_rtx; | |
3349 | operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]), VOIDmode, | |
3350 | operands[1], operands[2]); | |
3351 | emit_jump_insn (gen_cbranchcc4 (operands[0], operands[1], operands[2], | |
3352 | operands[3])); | |
3353 | } | |
3354 | ||
3355 | ||
7b1ac798 JJ |
3356 | /* Generate a DFmode part of a hard TFmode register. |
3357 | REG is the TFmode hard register, LOW is 1 for the | |
3358 | low 64bit of the register and 0 otherwise. | |
3359 | */ | |
3360 | rtx | |
fc27d102 | 3361 | gen_df_reg (rtx reg, int low) |
7b1ac798 JJ |
3362 | { |
3363 | int regno = REGNO (reg); | |
3364 | ||
3365 | if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) | |
5a53588f | 3366 | regno += (TARGET_ARCH64 && SPARC_INT_REG_P (regno)) ? 1 : 2; |
7b1ac798 JJ |
3367 | return gen_rtx_REG (DFmode, regno); |
3368 | } | |
e0d80184 | 3369 | \f |
73985940 RH |
3370 | /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value. |
3371 | Unlike normal calls, TFmode operands are passed by reference. It is | |
3372 | assumed that no more than 3 operands are required. */ | |
3373 | ||
3374 | static void | |
fc27d102 | 3375 | emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands) |
73985940 RH |
3376 | { |
3377 | rtx ret_slot = NULL, arg[3], func_sym; | |
4e7d5d27 | 3378 | int i; |
73985940 RH |
3379 | |
3380 | /* We only expect to be called for conversions, unary, and binary ops. */ | |
f5f7d171 | 3381 | gcc_assert (nargs == 2 || nargs == 3); |
73985940 RH |
3382 | |
3383 | for (i = 0; i < nargs; ++i) | |
3384 | { | |
3385 | rtx this_arg = operands[i]; | |
3386 | rtx this_slot; | |
3387 | ||
3388 | /* TFmode arguments and return values are passed by reference. */ | |
3389 | if (GET_MODE (this_arg) == TFmode) | |
3390 | { | |
4e7d5d27 DM |
3391 | int force_stack_temp; |
3392 | ||
3393 | force_stack_temp = 0; | |
3394 | if (TARGET_BUGGY_QP_LIB && i == 0) | |
3395 | force_stack_temp = 1; | |
3396 | ||
3397 | if (GET_CODE (this_arg) == MEM | |
3398 | && ! force_stack_temp) | |
d333c3eb DM |
3399 | { |
3400 | tree expr = MEM_EXPR (this_arg); | |
3401 | if (expr) | |
3402 | mark_addressable (expr); | |
3403 | this_arg = XEXP (this_arg, 0); | |
3404 | } | |
4e7d5d27 DM |
3405 | else if (CONSTANT_P (this_arg) |
3406 | && ! force_stack_temp) | |
73985940 RH |
3407 | { |
3408 | this_slot = force_const_mem (TFmode, this_arg); | |
3409 | this_arg = XEXP (this_slot, 0); | |
3410 | } | |
3411 | else | |
3412 | { | |
9474e8ab | 3413 | this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode)); |
73985940 RH |
3414 | |
3415 | /* Operand 0 is the return value. We'll copy it out later. */ | |
3416 | if (i > 0) | |
3417 | emit_move_insn (this_slot, this_arg); | |
3418 | else | |
3419 | ret_slot = this_slot; | |
3420 | ||
3421 | this_arg = XEXP (this_slot, 0); | |
3422 | } | |
3423 | } | |
3424 | ||
3425 | arg[i] = this_arg; | |
3426 | } | |
3427 | ||
3428 | func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name); | |
3429 | ||
3430 | if (GET_MODE (operands[0]) == TFmode) | |
3431 | { | |
3432 | if (nargs == 2) | |
db69559b | 3433 | emit_library_call (func_sym, LCT_NORMAL, VOIDmode, |
73985940 RH |
3434 | arg[0], GET_MODE (arg[0]), |
3435 | arg[1], GET_MODE (arg[1])); | |
3436 | else | |
db69559b | 3437 | emit_library_call (func_sym, LCT_NORMAL, VOIDmode, |
73985940 RH |
3438 | arg[0], GET_MODE (arg[0]), |
3439 | arg[1], GET_MODE (arg[1]), | |
3440 | arg[2], GET_MODE (arg[2])); | |
3441 | ||
3442 | if (ret_slot) | |
3443 | emit_move_insn (operands[0], ret_slot); | |
3444 | } | |
3445 | else | |
3446 | { | |
3447 | rtx ret; | |
3448 | ||
f5f7d171 | 3449 | gcc_assert (nargs == 2); |
73985940 RH |
3450 | |
3451 | ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL, | |
db69559b | 3452 | GET_MODE (operands[0]), |
73985940 RH |
3453 | arg[1], GET_MODE (arg[1])); |
3454 | ||
3455 | if (ret != operands[0]) | |
3456 | emit_move_insn (operands[0], ret); | |
3457 | } | |
3458 | } | |
3459 | ||
3460 | /* Expand soft-float TFmode calls to sparc abi routines. */ | |
3461 | ||
3462 | static void | |
fc27d102 | 3463 | emit_soft_tfmode_binop (enum rtx_code code, rtx *operands) |
73985940 RH |
3464 | { |
3465 | const char *func; | |
3466 | ||
3467 | switch (code) | |
3468 | { | |
3469 | case PLUS: | |
3470 | func = "_Qp_add"; | |
3471 | break; | |
3472 | case MINUS: | |
3473 | func = "_Qp_sub"; | |
3474 | break; | |
3475 | case MULT: | |
3476 | func = "_Qp_mul"; | |
3477 | break; | |
3478 | case DIV: | |
3479 | func = "_Qp_div"; | |
3480 | break; | |
3481 | default: | |
f5f7d171 | 3482 | gcc_unreachable (); |
73985940 RH |
3483 | } |
3484 | ||
3485 | emit_soft_tfmode_libcall (func, 3, operands); | |
3486 | } | |
3487 | ||
3488 | static void | |
fc27d102 | 3489 | emit_soft_tfmode_unop (enum rtx_code code, rtx *operands) |
73985940 RH |
3490 | { |
3491 | const char *func; | |
3492 | ||
f5f7d171 JM |
3493 | gcc_assert (code == SQRT); |
3494 | func = "_Qp_sqrt"; | |
73985940 RH |
3495 | |
3496 | emit_soft_tfmode_libcall (func, 2, operands); | |
3497 | } | |
3498 | ||
3499 | static void | |
fc27d102 | 3500 | emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands) |
73985940 RH |
3501 | { |
3502 | const char *func; | |
3503 | ||
3504 | switch (code) | |
3505 | { | |
3506 | case FLOAT_EXTEND: | |
3507 | switch (GET_MODE (operands[1])) | |
3508 | { | |
4e10a5a7 | 3509 | case E_SFmode: |
73985940 RH |
3510 | func = "_Qp_stoq"; |
3511 | break; | |
4e10a5a7 | 3512 | case E_DFmode: |
73985940 RH |
3513 | func = "_Qp_dtoq"; |
3514 | break; | |
3515 | default: | |
f5f7d171 | 3516 | gcc_unreachable (); |
73985940 RH |
3517 | } |
3518 | break; | |
3519 | ||
3520 | case FLOAT_TRUNCATE: | |
3521 | switch (GET_MODE (operands[0])) | |
3522 | { | |
4e10a5a7 | 3523 | case E_SFmode: |
73985940 RH |
3524 | func = "_Qp_qtos"; |
3525 | break; | |
4e10a5a7 | 3526 | case E_DFmode: |
73985940 RH |
3527 | func = "_Qp_qtod"; |
3528 | break; | |
3529 | default: | |
f5f7d171 | 3530 | gcc_unreachable (); |
73985940 RH |
3531 | } |
3532 | break; | |
3533 | ||
3534 | case FLOAT: | |
3535 | switch (GET_MODE (operands[1])) | |
3536 | { | |
4e10a5a7 | 3537 | case E_SImode: |
73985940 | 3538 | func = "_Qp_itoq"; |
92693034 JM |
3539 | if (TARGET_ARCH64) |
3540 | operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]); | |
73985940 | 3541 | break; |
4e10a5a7 | 3542 | case E_DImode: |
73985940 RH |
3543 | func = "_Qp_xtoq"; |
3544 | break; | |
3545 | default: | |
f5f7d171 | 3546 | gcc_unreachable (); |
73985940 RH |
3547 | } |
3548 | break; | |
3549 | ||
3550 | case UNSIGNED_FLOAT: | |
3551 | switch (GET_MODE (operands[1])) | |
3552 | { | |
4e10a5a7 | 3553 | case E_SImode: |
73985940 | 3554 | func = "_Qp_uitoq"; |
92693034 JM |
3555 | if (TARGET_ARCH64) |
3556 | operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
73985940 | 3557 | break; |
4e10a5a7 | 3558 | case E_DImode: |
73985940 RH |
3559 | func = "_Qp_uxtoq"; |
3560 | break; | |
3561 | default: | |
f5f7d171 | 3562 | gcc_unreachable (); |
73985940 RH |
3563 | } |
3564 | break; | |
3565 | ||
3566 | case FIX: | |
3567 | switch (GET_MODE (operands[0])) | |
3568 | { | |
4e10a5a7 | 3569 | case E_SImode: |
73985940 RH |
3570 | func = "_Qp_qtoi"; |
3571 | break; | |
4e10a5a7 | 3572 | case E_DImode: |
73985940 RH |
3573 | func = "_Qp_qtox"; |
3574 | break; | |
3575 | default: | |
f5f7d171 | 3576 | gcc_unreachable (); |
73985940 RH |
3577 | } |
3578 | break; | |
3579 | ||
3580 | case UNSIGNED_FIX: | |
3581 | switch (GET_MODE (operands[0])) | |
3582 | { | |
4e10a5a7 | 3583 | case E_SImode: |
73985940 RH |
3584 | func = "_Qp_qtoui"; |
3585 | break; | |
4e10a5a7 | 3586 | case E_DImode: |
73985940 RH |
3587 | func = "_Qp_qtoux"; |
3588 | break; | |
3589 | default: | |
f5f7d171 | 3590 | gcc_unreachable (); |
73985940 RH |
3591 | } |
3592 | break; | |
3593 | ||
3594 | default: | |
f5f7d171 | 3595 | gcc_unreachable (); |
73985940 RH |
3596 | } |
3597 | ||
3598 | emit_soft_tfmode_libcall (func, 2, operands); | |
3599 | } | |
3600 | ||
3601 | /* Expand a hard-float tfmode operation. All arguments must be in | |
3602 | registers. */ | |
3603 | ||
3604 | static void | |
fc27d102 | 3605 | emit_hard_tfmode_operation (enum rtx_code code, rtx *operands) |
73985940 RH |
3606 | { |
3607 | rtx op, dest; | |
3608 | ||
ec8e098d | 3609 | if (GET_RTX_CLASS (code) == RTX_UNARY) |
73985940 RH |
3610 | { |
3611 | operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); | |
3612 | op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]); | |
3613 | } | |
3614 | else | |
3615 | { | |
3616 | operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); | |
3617 | operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); | |
3618 | op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]), | |
3619 | operands[1], operands[2]); | |
3620 | } | |
3621 | ||
3622 | if (register_operand (operands[0], VOIDmode)) | |
3623 | dest = operands[0]; | |
3624 | else | |
3625 | dest = gen_reg_rtx (GET_MODE (operands[0])); | |
3626 | ||
f7df4a84 | 3627 | emit_insn (gen_rtx_SET (dest, op)); |
73985940 RH |
3628 | |
3629 | if (dest != operands[0]) | |
3630 | emit_move_insn (operands[0], dest); | |
3631 | } | |
3632 | ||
3633 | void | |
fc27d102 | 3634 | emit_tfmode_binop (enum rtx_code code, rtx *operands) |
73985940 RH |
3635 | { |
3636 | if (TARGET_HARD_QUAD) | |
3637 | emit_hard_tfmode_operation (code, operands); | |
3638 | else | |
3639 | emit_soft_tfmode_binop (code, operands); | |
3640 | } | |
3641 | ||
3642 | void | |
fc27d102 | 3643 | emit_tfmode_unop (enum rtx_code code, rtx *operands) |
73985940 RH |
3644 | { |
3645 | if (TARGET_HARD_QUAD) | |
3646 | emit_hard_tfmode_operation (code, operands); | |
3647 | else | |
3648 | emit_soft_tfmode_unop (code, operands); | |
3649 | } | |
3650 | ||
3651 | void | |
fc27d102 | 3652 | emit_tfmode_cvt (enum rtx_code code, rtx *operands) |
73985940 RH |
3653 | { |
3654 | if (TARGET_HARD_QUAD) | |
3655 | emit_hard_tfmode_operation (code, operands); | |
3656 | else | |
3657 | emit_soft_tfmode_cvt (code, operands); | |
3658 | } | |
3659 | \f | |
f17f9332 JJ |
3660 | /* Return nonzero if a branch/jump/call instruction will be emitting |
3661 | nop into its delay slot. */ | |
3662 | ||
3663 | int | |
b32d5189 | 3664 | empty_delay_slot (rtx_insn *insn) |
f17f9332 JJ |
3665 | { |
3666 | rtx seq; | |
3667 | ||
3668 | /* If no previous instruction (should not happen), return true. */ | |
3669 | if (PREV_INSN (insn) == NULL) | |
3670 | return 1; | |
3671 | ||
3672 | seq = NEXT_INSN (PREV_INSN (insn)); | |
3673 | if (GET_CODE (PATTERN (seq)) == SEQUENCE) | |
3674 | return 0; | |
3675 | ||
3676 | return 1; | |
3677 | } | |
3678 | ||
8b98b5fd DM |
3679 | /* Return nonzero if we should emit a nop after a cbcond instruction. |
3680 | The cbcond instruction does not have a delay slot, however there is | |
3681 | a severe performance penalty if a control transfer appears right | |
3682 | after a cbcond. Therefore we emit a nop when we detect this | |
3683 | situation. */ | |
3684 | ||
3685 | int | |
82082f65 | 3686 | emit_cbcond_nop (rtx_insn *insn) |
8b98b5fd DM |
3687 | { |
3688 | rtx next = next_active_insn (insn); | |
3689 | ||
3690 | if (!next) | |
3691 | return 1; | |
3692 | ||
b64925dc | 3693 | if (NONJUMP_INSN_P (next) |
8b98b5fd DM |
3694 | && GET_CODE (PATTERN (next)) == SEQUENCE) |
3695 | next = XVECEXP (PATTERN (next), 0, 0); | |
b64925dc | 3696 | else if (CALL_P (next) |
8b98b5fd DM |
3697 | && GET_CODE (PATTERN (next)) == PARALLEL) |
3698 | { | |
3699 | rtx delay = XVECEXP (PATTERN (next), 0, 1); | |
3700 | ||
3701 | if (GET_CODE (delay) == RETURN) | |
3702 | { | |
3703 | /* It's a sibling call. Do not emit the nop if we're going | |
3704 | to emit something other than the jump itself as the first | |
3705 | instruction of the sibcall sequence. */ | |
3706 | if (sparc_leaf_function_p || TARGET_FLAT) | |
3707 | return 0; | |
3708 | } | |
3709 | } | |
3710 | ||
3711 | if (NONJUMP_INSN_P (next)) | |
3712 | return 0; | |
3713 | ||
3714 | return 1; | |
3715 | } | |
3716 | ||
9ac617d4 | 3717 | /* Return nonzero if TRIAL can go into the call delay slot. */ |
ab835497 | 3718 | |
e0d80184 | 3719 | int |
84034c69 | 3720 | eligible_for_call_delay (rtx_insn *trial) |
e0d80184 | 3721 | { |
e10fbf96 | 3722 | rtx pat; |
1150a841 | 3723 | |
890fa568 EB |
3724 | if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE) |
3725 | return 0; | |
3726 | ||
9ac617d4 | 3727 | /* Binutils allows |
e10fbf96 EB |
3728 | call __tls_get_addr, %tgd_call (foo) |
3729 | add %l7, %o0, %o0, %tgd_add (foo) | |
9ac617d4 EB |
3730 | while Sun as/ld does not. */ |
3731 | if (TARGET_GNU_TLS || !TARGET_TLS) | |
3732 | return 1; | |
4fb4e4b8 | 3733 | |
e0d80184 | 3734 | pat = PATTERN (trial); |
795068a4 | 3735 | |
e10fbf96 EB |
3736 | /* We must reject tgd_add{32|64}, i.e. |
3737 | (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD))) | |
3738 | and tldm_add{32|64}, i.e. | |
3739 | (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM))) | |
3740 | for Sun as/ld. */ | |
3741 | if (GET_CODE (pat) == SET | |
3742 | && GET_CODE (SET_SRC (pat)) == PLUS) | |
3743 | { | |
3744 | rtx unspec = XEXP (SET_SRC (pat), 1); | |
795068a4 | 3745 | |
e10fbf96 EB |
3746 | if (GET_CODE (unspec) == UNSPEC |
3747 | && (XINT (unspec, 1) == UNSPEC_TLSGD | |
3748 | || XINT (unspec, 1) == UNSPEC_TLSLDM)) | |
3749 | return 0; | |
3750 | } | |
3751 | ||
3752 | return 1; | |
9ac617d4 EB |
3753 | } |
3754 | ||
3755 | /* Return nonzero if TRIAL, an insn, can be combined with a 'restore' | |
3756 | instruction. RETURN_P is true if the v9 variant 'return' is to be | |
3757 | considered in the test too. | |
c137830f | 3758 | |
9ac617d4 EB |
3759 | TRIAL must be a SET whose destination is a REG appropriate for the |
3760 | 'restore' instruction or, if RETURN_P is true, for the 'return' | |
3761 | instruction. */ | |
795068a4 | 3762 | |
9ac617d4 EB |
3763 | static int |
3764 | eligible_for_restore_insn (rtx trial, bool return_p) | |
3765 | { | |
3766 | rtx pat = PATTERN (trial); | |
3767 | rtx src = SET_SRC (pat); | |
bb12a72a DM |
3768 | bool src_is_freg = false; |
3769 | rtx src_reg; | |
3770 | ||
3771 | /* Since we now can do moves between float and integer registers when | |
3772 | VIS3 is enabled, we have to catch this case. We can allow such | |
3773 | moves when doing a 'return' however. */ | |
3774 | src_reg = src; | |
3775 | if (GET_CODE (src_reg) == SUBREG) | |
3776 | src_reg = SUBREG_REG (src_reg); | |
3777 | if (GET_CODE (src_reg) == REG | |
3778 | && SPARC_FP_REG_P (REGNO (src_reg))) | |
3779 | src_is_freg = true; | |
795068a4 | 3780 | |
9ac617d4 | 3781 | /* The 'restore src,%g0,dest' pattern for word mode and below. */ |
3ec6f1a9 | 3782 | if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
bb12a72a DM |
3783 | && arith_operand (src, GET_MODE (src)) |
3784 | && ! src_is_freg) | |
3c6088d2 JJ |
3785 | { |
3786 | if (TARGET_ARCH64) | |
3787 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
3788 | else | |
3789 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
3790 | } | |
e48addee | 3791 | |
9ac617d4 | 3792 | /* The 'restore src,%g0,dest' pattern for double-word mode. */ |
3ec6f1a9 | 3793 | else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
bb12a72a DM |
3794 | && arith_double_operand (src, GET_MODE (src)) |
3795 | && ! src_is_freg) | |
e0d80184 | 3796 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); |
795068a4 | 3797 | |
9ac617d4 EB |
3798 | /* The 'restore src,%g0,dest' pattern for float if no FPU. */ |
3799 | else if (! TARGET_FPU && register_operand (src, SFmode)) | |
3800 | return 1; | |
3801 | ||
3802 | /* The 'restore src,%g0,dest' pattern for double if no FPU. */ | |
3803 | else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode)) | |
e0d80184 | 3804 | return 1; |
f5da225e | 3805 | |
9ac617d4 | 3806 | /* If we have the 'return' instruction, anything that does not use |
e48addee | 3807 | local or output registers and can go into a delay slot wins. */ |
890fa568 | 3808 | else if (return_p && TARGET_V9 && !epilogue_renumber (&pat, 1)) |
e48addee JJ |
3809 | return 1; |
3810 | ||
9ac617d4 | 3811 | /* The 'restore src1,src2,dest' pattern for SImode. */ |
e0d80184 | 3812 | else if (GET_CODE (src) == PLUS |
9ac617d4 EB |
3813 | && register_operand (XEXP (src, 0), SImode) |
3814 | && arith_operand (XEXP (src, 1), SImode)) | |
e0d80184 DM |
3815 | return 1; |
3816 | ||
9ac617d4 | 3817 | /* The 'restore src1,src2,dest' pattern for DImode. */ |
e0d80184 | 3818 | else if (GET_CODE (src) == PLUS |
9ac617d4 EB |
3819 | && register_operand (XEXP (src, 0), DImode) |
3820 | && arith_double_operand (XEXP (src, 1), DImode)) | |
795068a4 | 3821 | return 1; |
795068a4 | 3822 | |
9ac617d4 | 3823 | /* The 'restore src1,%lo(src2),dest' pattern. */ |
e48addee JJ |
3824 | else if (GET_CODE (src) == LO_SUM |
3825 | && ! TARGET_CM_MEDMID | |
3826 | && ((register_operand (XEXP (src, 0), SImode) | |
3827 | && immediate_operand (XEXP (src, 1), SImode)) | |
3828 | || (TARGET_ARCH64 | |
3829 | && register_operand (XEXP (src, 0), DImode) | |
3830 | && immediate_operand (XEXP (src, 1), DImode)))) | |
3831 | return 1; | |
3832 | ||
9ac617d4 | 3833 | /* The 'restore src,src,dest' pattern. */ |
e48addee JJ |
3834 | else if (GET_CODE (src) == ASHIFT |
3835 | && (register_operand (XEXP (src, 0), SImode) | |
3836 | || register_operand (XEXP (src, 0), DImode)) | |
3837 | && XEXP (src, 1) == const1_rtx) | |
3838 | return 1; | |
3839 | ||
795068a4 JW |
3840 | return 0; |
3841 | } | |
3842 | ||
b11b0904 | 3843 | /* Return nonzero if TRIAL can go into the function return's delay slot. */ |
9ac617d4 | 3844 | |
5751a10b | 3845 | int |
84034c69 | 3846 | eligible_for_return_delay (rtx_insn *trial) |
5751a10b | 3847 | { |
cb8bbba8 | 3848 | int regno; |
9ac617d4 | 3849 | rtx pat; |
5751a10b | 3850 | |
9ac617d4 EB |
3851 | /* If the function uses __builtin_eh_return, the eh_return machinery |
3852 | occupies the delay slot. */ | |
e3b5732b | 3853 | if (crtl->calls_eh_return) |
9ac617d4 EB |
3854 | return 0; |
3855 | ||
890fa568 EB |
3856 | if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE) |
3857 | return 0; | |
3858 | ||
b11b0904 EB |
3859 | /* In the case of a leaf or flat function, anything can go into the slot. */ |
3860 | if (sparc_leaf_function_p || TARGET_FLAT) | |
890fa568 EB |
3861 | return 1; |
3862 | ||
3863 | if (!NONJUMP_INSN_P (trial)) | |
3864 | return 0; | |
5751a10b JJ |
3865 | |
3866 | pat = PATTERN (trial); | |
cb8bbba8 DM |
3867 | if (GET_CODE (pat) == PARALLEL) |
3868 | { | |
3869 | int i; | |
3870 | ||
3871 | if (! TARGET_V9) | |
3872 | return 0; | |
3873 | for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) | |
3874 | { | |
3875 | rtx expr = XVECEXP (pat, 0, i); | |
3876 | if (GET_CODE (expr) != SET) | |
3877 | return 0; | |
3878 | if (GET_CODE (SET_DEST (expr)) != REG) | |
3879 | return 0; | |
3880 | regno = REGNO (SET_DEST (expr)); | |
3881 | if (regno >= 8 && regno < 24) | |
3882 | return 0; | |
3883 | } | |
890fa568 | 3884 | return !epilogue_renumber (&pat, 1); |
cb8bbba8 DM |
3885 | } |
3886 | ||
3887 | if (GET_CODE (pat) != SET) | |
3888 | return 0; | |
3889 | ||
3890 | if (GET_CODE (SET_DEST (pat)) != REG) | |
3891 | return 0; | |
3892 | ||
3893 | regno = REGNO (SET_DEST (pat)); | |
5751a10b | 3894 | |
9ac617d4 EB |
3895 | /* Otherwise, only operations which can be done in tandem with |
3896 | a `restore' or `return' insn can go into the delay slot. */ | |
cb8bbba8 | 3897 | if (regno >= 8 && regno < 24) |
9ac617d4 | 3898 | return 0; |
5751a10b | 3899 | |
9ac617d4 EB |
3900 | /* If this instruction sets up floating point register and we have a return |
3901 | instruction, it can probably go in. But restore will not work | |
3902 | with FP_REGS. */ | |
5a53588f | 3903 | if (! SPARC_INT_REG_P (regno)) |
890fa568 | 3904 | return TARGET_V9 && !epilogue_renumber (&pat, 1); |
9ac617d4 EB |
3905 | |
3906 | return eligible_for_restore_insn (trial, true); | |
5751a10b JJ |
3907 | } |
3908 | ||
b11b0904 | 3909 | /* Return nonzero if TRIAL can go into the sibling call's delay slot. */ |
7d167afd JJ |
3910 | |
3911 | int | |
84034c69 | 3912 | eligible_for_sibcall_delay (rtx_insn *trial) |
7d167afd | 3913 | { |
9ac617d4 | 3914 | rtx pat; |
7d167afd | 3915 | |
890fa568 | 3916 | if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE) |
7d167afd JJ |
3917 | return 0; |
3918 | ||
890fa568 | 3919 | if (!NONJUMP_INSN_P (trial)) |
7d167afd JJ |
3920 | return 0; |
3921 | ||
3922 | pat = PATTERN (trial); | |
3923 | ||
b11b0904 | 3924 | if (sparc_leaf_function_p || TARGET_FLAT) |
7d167afd JJ |
3925 | { |
3926 | /* If the tail call is done using the call instruction, | |
3927 | we have to restore %o7 in the delay slot. */ | |
6244b14e | 3928 | if (LEAF_SIBCALL_SLOT_RESERVED_P) |
7d167afd JJ |
3929 | return 0; |
3930 | ||
3931 | /* %g1 is used to build the function address */ | |
3932 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) | |
3933 | return 0; | |
3934 | ||
3935 | return 1; | |
3936 | } | |
3937 | ||
890fa568 EB |
3938 | if (GET_CODE (pat) != SET) |
3939 | return 0; | |
3940 | ||
7d167afd JJ |
3941 | /* Otherwise, only operations which can be done in tandem with |
3942 | a `restore' insn can go into the delay slot. */ | |
3943 | if (GET_CODE (SET_DEST (pat)) != REG | |
9ac617d4 | 3944 | || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24) |
5a53588f | 3945 | || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat)))) |
7d167afd JJ |
3946 | return 0; |
3947 | ||
3948 | /* If it mentions %o7, it can't go in, because sibcall will clobber it | |
3949 | in most cases. */ | |
3950 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) | |
3951 | return 0; | |
3952 | ||
9ac617d4 | 3953 | return eligible_for_restore_insn (trial, false); |
e0d80184 | 3954 | } |
e0d80184 | 3955 | \f |
5751a10b JJ |
3956 | /* Determine if it's legal to put X into the constant pool. This |
3957 | is not possible if X contains the address of a symbol that is | |
3958 | not constant (TLS) or not known at final link time (PIC). */ | |
3959 | ||
3960 | static bool | |
ef4bddc2 | 3961 | sparc_cannot_force_const_mem (machine_mode mode, rtx x) |
5751a10b JJ |
3962 | { |
3963 | switch (GET_CODE (x)) | |
3964 | { | |
3965 | case CONST_INT: | |
eaac029f | 3966 | case CONST_WIDE_INT: |
5751a10b | 3967 | case CONST_DOUBLE: |
c75d6010 | 3968 | case CONST_VECTOR: |
5751a10b JJ |
3969 | /* Accept all non-symbolic constants. */ |
3970 | return false; | |
3971 | ||
3972 | case LABEL_REF: | |
3973 | /* Labels are OK iff we are non-PIC. */ | |
3974 | return flag_pic != 0; | |
3975 | ||
3976 | case SYMBOL_REF: | |
3977 | /* 'Naked' TLS symbol references are never OK, | |
3978 | non-TLS symbols are OK iff we are non-PIC. */ | |
3979 | if (SYMBOL_REF_TLS_MODEL (x)) | |
3980 | return true; | |
3981 | else | |
3982 | return flag_pic != 0; | |
3983 | ||
3984 | case CONST: | |
fbbf66e7 | 3985 | return sparc_cannot_force_const_mem (mode, XEXP (x, 0)); |
5751a10b JJ |
3986 | case PLUS: |
3987 | case MINUS: | |
fbbf66e7 RS |
3988 | return sparc_cannot_force_const_mem (mode, XEXP (x, 0)) |
3989 | || sparc_cannot_force_const_mem (mode, XEXP (x, 1)); | |
5751a10b JJ |
3990 | case UNSPEC: |
3991 | return true; | |
3992 | default: | |
f5f7d171 | 3993 | gcc_unreachable (); |
5751a10b JJ |
3994 | } |
3995 | } | |
3996 | \f | |
a6fed83f EB |
3997 | /* Global Offset Table support. */ |
3998 | static GTY(()) rtx got_helper_rtx = NULL_RTX; | |
3999 | static GTY(()) rtx global_offset_table_rtx = NULL_RTX; | |
4000 | ||
4001 | /* Return the SYMBOL_REF for the Global Offset Table. */ | |
4002 | ||
4003 | static GTY(()) rtx sparc_got_symbol = NULL_RTX; | |
4004 | ||
4005 | static rtx | |
4006 | sparc_got (void) | |
4007 | { | |
4008 | if (!sparc_got_symbol) | |
4009 | sparc_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
4010 | ||
4011 | return sparc_got_symbol; | |
4012 | } | |
bc961ed7 | 4013 | |
e0d80184 | 4014 | /* Ensure that we are not using patterns that are not OK with PIC. */ |
795068a4 | 4015 | |
e0d80184 | 4016 | int |
fc27d102 | 4017 | check_pic (int i) |
e0d80184 | 4018 | { |
a6fed83f EB |
4019 | rtx op; |
4020 | ||
e0d80184 | 4021 | switch (flag_pic) |
ab835497 | 4022 | { |
e0d80184 | 4023 | case 1: |
a6fed83f EB |
4024 | op = recog_data.operand[i]; |
4025 | gcc_assert (GET_CODE (op) != SYMBOL_REF | |
4026 | && (GET_CODE (op) != CONST | |
4027 | || (GET_CODE (XEXP (op, 0)) == MINUS | |
4028 | && XEXP (XEXP (op, 0), 0) == sparc_got () | |
4029 | && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST))); | |
fbedd170 | 4030 | /* fallthrough */ |
e0d80184 DM |
4031 | case 2: |
4032 | default: | |
4033 | return 1; | |
ab835497 | 4034 | } |
ab835497 | 4035 | } |
795068a4 | 4036 | |
4900aa61 | 4037 | /* Return true if X is an address which needs a temporary register when |
e0d80184 | 4038 | reloaded while generating PIC code. */ |
795068a4 | 4039 | |
e0d80184 | 4040 | int |
fc27d102 | 4041 | pic_address_needs_scratch (rtx x) |
795068a4 | 4042 | { |
e0d80184 DM |
4043 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ |
4044 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
4045 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
4046 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
4047 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
4048 | return 1; | |
795068a4 | 4049 | |
e0d80184 DM |
4050 | return 0; |
4051 | } | |
795068a4 | 4052 | |
5751a10b JJ |
4053 | /* Determine if a given RTX is a valid constant. We already know this |
4054 | satisfies CONSTANT_P. */ | |
4055 | ||
1a627b35 | 4056 | static bool |
ef4bddc2 | 4057 | sparc_legitimate_constant_p (machine_mode mode, rtx x) |
5751a10b | 4058 | { |
5751a10b JJ |
4059 | switch (GET_CODE (x)) |
4060 | { | |
5751a10b | 4061 | case CONST: |
208384fd EB |
4062 | case SYMBOL_REF: |
4063 | if (sparc_tls_referenced_p (x)) | |
5751a10b JJ |
4064 | return false; |
4065 | break; | |
4066 | ||
4067 | case CONST_DOUBLE: | |
5751a10b | 4068 | /* Floating point constants are generally not ok. |
7cbcf85b | 4069 | The only exception is 0.0 and all-ones in VIS. */ |
5751a10b | 4070 | if (TARGET_VIS |
1a627b35 | 4071 | && SCALAR_FLOAT_MODE_P (mode) |
7cbcf85b DM |
4072 | && (const_zero_operand (x, mode) |
4073 | || const_all_ones_operand (x, mode))) | |
bea5071f EB |
4074 | return true; |
4075 | ||
4076 | return false; | |
4077 | ||
4078 | case CONST_VECTOR: | |
4079 | /* Vector constants are generally not ok. | |
7cbcf85b | 4080 | The only exception is 0 or -1 in VIS. */ |
bea5071f | 4081 | if (TARGET_VIS |
7cbcf85b DM |
4082 | && (const_zero_operand (x, mode) |
4083 | || const_all_ones_operand (x, mode))) | |
5751a10b JJ |
4084 | return true; |
4085 | ||
4086 | return false; | |
4087 | ||
4088 | default: | |
4089 | break; | |
4090 | } | |
4091 | ||
4092 | return true; | |
4093 | } | |
4094 | ||
4095 | /* Determine if a given RTX is a valid constant address. */ | |
4096 | ||
4097 | bool | |
4098 | constant_address_p (rtx x) | |
4099 | { | |
4100 | switch (GET_CODE (x)) | |
4101 | { | |
4102 | case LABEL_REF: | |
4103 | case CONST_INT: | |
4104 | case HIGH: | |
4105 | return true; | |
4106 | ||
4107 | case CONST: | |
4108 | if (flag_pic && pic_address_needs_scratch (x)) | |
4109 | return false; | |
1a627b35 | 4110 | return sparc_legitimate_constant_p (Pmode, x); |
5751a10b JJ |
4111 | |
4112 | case SYMBOL_REF: | |
1a627b35 | 4113 | return !flag_pic && sparc_legitimate_constant_p (Pmode, x); |
5751a10b JJ |
4114 | |
4115 | default: | |
4116 | return false; | |
4117 | } | |
4118 | } | |
4119 | ||
4120 | /* Nonzero if the constant value X is a legitimate general operand | |
4121 | when generating PIC code. It is given that flag_pic is on and | |
eaac029f | 4122 | that X satisfies CONSTANT_P. */ |
5751a10b JJ |
4123 | |
4124 | bool | |
4125 | legitimate_pic_operand_p (rtx x) | |
4126 | { | |
4127 | if (pic_address_needs_scratch (x)) | |
4128 | return false; | |
208384fd | 4129 | if (sparc_tls_referenced_p (x)) |
5751a10b JJ |
4130 | return false; |
4131 | return true; | |
4132 | } | |
4133 | ||
b11b0904 EB |
4134 | #define RTX_OK_FOR_OFFSET_P(X, MODE) \ |
4135 | (CONST_INT_P (X) \ | |
4136 | && INTVAL (X) >= -0x1000 \ | |
a6bc87d3 | 4137 | && INTVAL (X) <= (0x1000 - GET_MODE_SIZE (MODE))) |
8b9a1428 | 4138 | |
b11b0904 EB |
4139 | #define RTX_OK_FOR_OLO10_P(X, MODE) \ |
4140 | (CONST_INT_P (X) \ | |
4141 | && INTVAL (X) >= -0x1000 \ | |
a6bc87d3 | 4142 | && INTVAL (X) <= (0xc00 - GET_MODE_SIZE (MODE))) |
8b9a1428 AS |
4143 | |
4144 | /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook. | |
4145 | ||
4146 | On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT | |
4147 | ordinarily. This changes a bit when generating PIC. */ | |
4900aa61 | 4148 | |
c6c3dba9 | 4149 | static bool |
ef4bddc2 | 4150 | sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict) |
5751a10b | 4151 | { |
f1b259d5 | 4152 | rtx rs1 = NULL, rs2 = NULL, imm1 = NULL; |
5751a10b JJ |
4153 | |
4154 | if (REG_P (addr) || GET_CODE (addr) == SUBREG) | |
4155 | rs1 = addr; | |
4156 | else if (GET_CODE (addr) == PLUS) | |
4157 | { | |
4158 | rs1 = XEXP (addr, 0); | |
4159 | rs2 = XEXP (addr, 1); | |
4160 | ||
4161 | /* Canonicalize. REG comes first, if there are no regs, | |
4162 | LO_SUM comes first. */ | |
4163 | if (!REG_P (rs1) | |
4164 | && GET_CODE (rs1) != SUBREG | |
4165 | && (REG_P (rs2) | |
4166 | || GET_CODE (rs2) == SUBREG | |
4167 | || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM))) | |
4168 | { | |
4169 | rs1 = XEXP (addr, 1); | |
4170 | rs2 = XEXP (addr, 0); | |
4171 | } | |
4172 | ||
4173 | if ((flag_pic == 1 | |
4174 | && rs1 == pic_offset_table_rtx | |
4175 | && !REG_P (rs2) | |
4176 | && GET_CODE (rs2) != SUBREG | |
4177 | && GET_CODE (rs2) != LO_SUM | |
4178 | && GET_CODE (rs2) != MEM | |
208384fd | 4179 | && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2)) |
5751a10b JJ |
4180 | && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode) |
4181 | && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2))) | |
4182 | || ((REG_P (rs1) | |
4183 | || GET_CODE (rs1) == SUBREG) | |
b11b0904 | 4184 | && RTX_OK_FOR_OFFSET_P (rs2, mode))) |
5751a10b JJ |
4185 | { |
4186 | imm1 = rs2; | |
4187 | rs2 = NULL; | |
4188 | } | |
4189 | else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG) | |
4190 | && (REG_P (rs2) || GET_CODE (rs2) == SUBREG)) | |
4191 | { | |
39ba2f92 EB |
4192 | /* We prohibit REG + REG for TFmode when there are no quad move insns |
4193 | and we consequently need to split. We do this because REG+REG | |
4194 | is not an offsettable address. If we get the situation in reload | |
5751a10b JJ |
4195 | where source and destination of a movtf pattern are both MEMs with |
4196 | REG+REG address, then only one of them gets converted to an | |
39ba2f92 | 4197 | offsettable address. */ |
5751a10b | 4198 | if (mode == TFmode |
12e55ac7 | 4199 | && ! (TARGET_ARCH64 && TARGET_HARD_QUAD)) |
5751a10b JJ |
4200 | return 0; |
4201 | ||
03c432bd EB |
4202 | /* Likewise for TImode, but in all cases. */ |
4203 | if (mode == TImode) | |
4204 | return 0; | |
4205 | ||
5751a10b JJ |
4206 | /* We prohibit REG + REG on ARCH32 if not optimizing for |
4207 | DFmode/DImode because then mem_min_alignment is likely to be zero | |
4208 | after reload and the forced split would lack a matching splitter | |
4209 | pattern. */ | |
4210 | if (TARGET_ARCH32 && !optimize | |
4211 | && (mode == DFmode || mode == DImode)) | |
4212 | return 0; | |
4213 | } | |
4214 | else if (USE_AS_OFFSETABLE_LO10 | |
4215 | && GET_CODE (rs1) == LO_SUM | |
4216 | && TARGET_ARCH64 | |
4217 | && ! TARGET_CM_MEDMID | |
b11b0904 | 4218 | && RTX_OK_FOR_OLO10_P (rs2, mode)) |
5751a10b | 4219 | { |
5751a10b JJ |
4220 | rs2 = NULL; |
4221 | imm1 = XEXP (rs1, 1); | |
4222 | rs1 = XEXP (rs1, 0); | |
208384fd EB |
4223 | if (!CONSTANT_P (imm1) |
4224 | || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1))) | |
5751a10b JJ |
4225 | return 0; |
4226 | } | |
4227 | } | |
4228 | else if (GET_CODE (addr) == LO_SUM) | |
4229 | { | |
4230 | rs1 = XEXP (addr, 0); | |
4231 | imm1 = XEXP (addr, 1); | |
4232 | ||
208384fd EB |
4233 | if (!CONSTANT_P (imm1) |
4234 | || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1))) | |
5751a10b JJ |
4235 | return 0; |
4236 | ||
f1b259d5 EB |
4237 | /* We can't allow TFmode in 32-bit mode, because an offset greater |
4238 | than the alignment (8) may cause the LO_SUM to overflow. */ | |
d24088cc | 4239 | if (mode == TFmode && TARGET_ARCH32) |
f1b259d5 | 4240 | return 0; |
710a2e10 EB |
4241 | |
4242 | /* During reload, accept the HIGH+LO_SUM construct generated by | |
4243 | sparc_legitimize_reload_address. */ | |
4244 | if (reload_in_progress | |
4245 | && GET_CODE (rs1) == HIGH | |
4246 | && XEXP (rs1, 0) == imm1) | |
4247 | return 1; | |
5751a10b JJ |
4248 | } |
4249 | else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr)) | |
4250 | return 1; | |
4251 | else | |
4252 | return 0; | |
4253 | ||
4254 | if (GET_CODE (rs1) == SUBREG) | |
4255 | rs1 = SUBREG_REG (rs1); | |
4256 | if (!REG_P (rs1)) | |
4257 | return 0; | |
4258 | ||
4259 | if (rs2) | |
4260 | { | |
4261 | if (GET_CODE (rs2) == SUBREG) | |
4262 | rs2 = SUBREG_REG (rs2); | |
4263 | if (!REG_P (rs2)) | |
4264 | return 0; | |
4265 | } | |
4266 | ||
4267 | if (strict) | |
4268 | { | |
4269 | if (!REGNO_OK_FOR_BASE_P (REGNO (rs1)) | |
4270 | || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2)))) | |
4271 | return 0; | |
4272 | } | |
4273 | else | |
4274 | { | |
5a53588f | 4275 | if ((! SPARC_INT_REG_P (REGNO (rs1)) |
5751a10b JJ |
4276 | && REGNO (rs1) != FRAME_POINTER_REGNUM |
4277 | && REGNO (rs1) < FIRST_PSEUDO_REGISTER) | |
4278 | || (rs2 | |
5a53588f | 4279 | && (! SPARC_INT_REG_P (REGNO (rs2)) |
5751a10b JJ |
4280 | && REGNO (rs2) != FRAME_POINTER_REGNUM |
4281 | && REGNO (rs2) < FIRST_PSEUDO_REGISTER))) | |
4282 | return 0; | |
4283 | } | |
4284 | return 1; | |
4285 | } | |
4286 | ||
a6fed83f | 4287 | /* Return the SYMBOL_REF for the tls_get_addr function. */ |
5751a10b | 4288 | |
a6fed83f | 4289 | static GTY(()) rtx sparc_tls_symbol = NULL_RTX; |
38fc66ba | 4290 | |
5751a10b JJ |
4291 | static rtx |
4292 | sparc_tls_get_addr (void) | |
4293 | { | |
4294 | if (!sparc_tls_symbol) | |
4295 | sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr"); | |
4296 | ||
4297 | return sparc_tls_symbol; | |
4298 | } | |
4299 | ||
a6fed83f EB |
4300 | /* Return the Global Offset Table to be used in TLS mode. */ |
4301 | ||
5751a10b JJ |
4302 | static rtx |
4303 | sparc_tls_got (void) | |
4304 | { | |
a6fed83f | 4305 | /* In PIC mode, this is just the PIC offset table. */ |
5751a10b JJ |
4306 | if (flag_pic) |
4307 | { | |
e3b5732b | 4308 | crtl->uses_pic_offset_table = 1; |
5751a10b JJ |
4309 | return pic_offset_table_rtx; |
4310 | } | |
4311 | ||
a6fed83f EB |
4312 | /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for |
4313 | the GOT symbol with the 32-bit ABI, so we reload the GOT register. */ | |
4314 | if (TARGET_SUN_TLS && TARGET_ARCH32) | |
4315 | { | |
4316 | load_got_register (); | |
4317 | return global_offset_table_rtx; | |
4318 | } | |
4319 | ||
4320 | /* In all other cases, we load a new pseudo with the GOT symbol. */ | |
4321 | return copy_to_reg (sparc_got ()); | |
5751a10b JJ |
4322 | } |
4323 | ||
208384fd | 4324 | /* Return true if X contains a thread-local symbol. */ |
38fc66ba | 4325 | |
208384fd | 4326 | static bool |
38fc66ba EB |
4327 | sparc_tls_referenced_p (rtx x) |
4328 | { | |
4329 | if (!TARGET_HAVE_TLS) | |
4330 | return false; | |
4331 | ||
208384fd EB |
4332 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS) |
4333 | x = XEXP (XEXP (x, 0), 0); | |
4334 | ||
4335 | if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x)) | |
4336 | return true; | |
4337 | ||
58e6223e | 4338 | /* That's all we handle in sparc_legitimize_tls_address for now. */ |
208384fd | 4339 | return false; |
38fc66ba | 4340 | } |
5751a10b JJ |
4341 | |
4342 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
4343 | this (thread-local) address. */ | |
4344 | ||
208384fd | 4345 | static rtx |
58e6223e | 4346 | sparc_legitimize_tls_address (rtx addr) |
5751a10b | 4347 | { |
e1faf324 DM |
4348 | rtx temp1, temp2, temp3, ret, o0, got; |
4349 | rtx_insn *insn; | |
5751a10b | 4350 | |
b3a13419 | 4351 | gcc_assert (can_create_pseudo_p ()); |
5751a10b JJ |
4352 | |
4353 | if (GET_CODE (addr) == SYMBOL_REF) | |
4354 | switch (SYMBOL_REF_TLS_MODEL (addr)) | |
4355 | { | |
4356 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
4357 | start_sequence (); | |
4358 | temp1 = gen_reg_rtx (SImode); | |
4359 | temp2 = gen_reg_rtx (SImode); | |
4360 | ret = gen_reg_rtx (Pmode); | |
4361 | o0 = gen_rtx_REG (Pmode, 8); | |
4362 | got = sparc_tls_got (); | |
4363 | emit_insn (gen_tgd_hi22 (temp1, addr)); | |
4364 | emit_insn (gen_tgd_lo10 (temp2, temp1, addr)); | |
4365 | if (TARGET_ARCH32) | |
4366 | { | |
4367 | emit_insn (gen_tgd_add32 (o0, got, temp2, addr)); | |
4368 | insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (), | |
4369 | addr, const1_rtx)); | |
4370 | } | |
4371 | else | |
4372 | { | |
4373 | emit_insn (gen_tgd_add64 (o0, got, temp2, addr)); | |
4374 | insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (), | |
4375 | addr, const1_rtx)); | |
4376 | } | |
44f370bf | 4377 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0); |
5751a10b JJ |
4378 | insn = get_insns (); |
4379 | end_sequence (); | |
4380 | emit_libcall_block (insn, ret, o0, addr); | |
4381 | break; | |
4382 | ||
4383 | case TLS_MODEL_LOCAL_DYNAMIC: | |
4384 | start_sequence (); | |
4385 | temp1 = gen_reg_rtx (SImode); | |
4386 | temp2 = gen_reg_rtx (SImode); | |
4387 | temp3 = gen_reg_rtx (Pmode); | |
4388 | ret = gen_reg_rtx (Pmode); | |
4389 | o0 = gen_rtx_REG (Pmode, 8); | |
4390 | got = sparc_tls_got (); | |
4391 | emit_insn (gen_tldm_hi22 (temp1)); | |
4392 | emit_insn (gen_tldm_lo10 (temp2, temp1)); | |
4393 | if (TARGET_ARCH32) | |
4394 | { | |
4395 | emit_insn (gen_tldm_add32 (o0, got, temp2)); | |
4396 | insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (), | |
4397 | const1_rtx)); | |
4398 | } | |
4399 | else | |
4400 | { | |
4401 | emit_insn (gen_tldm_add64 (o0, got, temp2)); | |
4402 | insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (), | |
4403 | const1_rtx)); | |
4404 | } | |
44f370bf | 4405 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0); |
5751a10b JJ |
4406 | insn = get_insns (); |
4407 | end_sequence (); | |
4408 | emit_libcall_block (insn, temp3, o0, | |
4409 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
4410 | UNSPEC_TLSLD_BASE)); | |
4411 | temp1 = gen_reg_rtx (SImode); | |
4412 | temp2 = gen_reg_rtx (SImode); | |
4413 | emit_insn (gen_tldo_hix22 (temp1, addr)); | |
4414 | emit_insn (gen_tldo_lox10 (temp2, temp1, addr)); | |
4415 | if (TARGET_ARCH32) | |
4416 | emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr)); | |
4417 | else | |
4418 | emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr)); | |
4419 | break; | |
4420 | ||
4421 | case TLS_MODEL_INITIAL_EXEC: | |
4422 | temp1 = gen_reg_rtx (SImode); | |
4423 | temp2 = gen_reg_rtx (SImode); | |
4424 | temp3 = gen_reg_rtx (Pmode); | |
4425 | got = sparc_tls_got (); | |
4426 | emit_insn (gen_tie_hi22 (temp1, addr)); | |
4427 | emit_insn (gen_tie_lo10 (temp2, temp1, addr)); | |
4428 | if (TARGET_ARCH32) | |
4429 | emit_insn (gen_tie_ld32 (temp3, got, temp2, addr)); | |
4430 | else | |
4431 | emit_insn (gen_tie_ld64 (temp3, got, temp2, addr)); | |
4432 | if (TARGET_SUN_TLS) | |
4433 | { | |
4434 | ret = gen_reg_rtx (Pmode); | |
4435 | if (TARGET_ARCH32) | |
4436 | emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7), | |
4437 | temp3, addr)); | |
4438 | else | |
4439 | emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7), | |
4440 | temp3, addr)); | |
4441 | } | |
4442 | else | |
4443 | ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3); | |
4444 | break; | |
4445 | ||
4446 | case TLS_MODEL_LOCAL_EXEC: | |
4447 | temp1 = gen_reg_rtx (Pmode); | |
4448 | temp2 = gen_reg_rtx (Pmode); | |
4449 | if (TARGET_ARCH32) | |
4450 | { | |
4451 | emit_insn (gen_tle_hix22_sp32 (temp1, addr)); | |
4452 | emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr)); | |
4453 | } | |
4454 | else | |
4455 | { | |
4456 | emit_insn (gen_tle_hix22_sp64 (temp1, addr)); | |
4457 | emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr)); | |
4458 | } | |
4459 | ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2); | |
4460 | break; | |
4461 | ||
4462 | default: | |
f5f7d171 | 4463 | gcc_unreachable (); |
5751a10b JJ |
4464 | } |
4465 | ||
208384fd EB |
4466 | else if (GET_CODE (addr) == CONST) |
4467 | { | |
4468 | rtx base, offset; | |
4469 | ||
4470 | gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS); | |
4471 | ||
58e6223e | 4472 | base = sparc_legitimize_tls_address (XEXP (XEXP (addr, 0), 0)); |
208384fd EB |
4473 | offset = XEXP (XEXP (addr, 0), 1); |
4474 | ||
4475 | base = force_operand (base, NULL_RTX); | |
4476 | if (!(GET_CODE (offset) == CONST_INT && SMALL_INT (offset))) | |
4477 | offset = force_reg (Pmode, offset); | |
4478 | ret = gen_rtx_PLUS (Pmode, base, offset); | |
4479 | } | |
4480 | ||
5751a10b | 4481 | else |
f5f7d171 | 4482 | gcc_unreachable (); /* for now ... */ |
5751a10b JJ |
4483 | |
4484 | return ret; | |
4485 | } | |
4486 | ||
e0d80184 DM |
4487 | /* Legitimize PIC addresses. If the address is already position-independent, |
4488 | we return ORIG. Newly generated position-independent addresses go into a | |
88cad84b | 4489 | reg. This is REG if nonzero, otherwise we allocate register(s) as |
e0d80184 | 4490 | necessary. */ |
795068a4 | 4491 | |
208384fd | 4492 | static rtx |
58e6223e | 4493 | sparc_legitimize_pic_address (rtx orig, rtx reg) |
e0d80184 | 4494 | { |
878ee0ab DM |
4495 | bool gotdata_op = false; |
4496 | ||
1910440e RS |
4497 | if (GET_CODE (orig) == SYMBOL_REF |
4498 | /* See the comment in sparc_expand_move. */ | |
205e4c6a | 4499 | || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig))) |
82d6b402 | 4500 | { |
e0d80184 | 4501 | rtx pic_ref, address; |
e1faf324 | 4502 | rtx_insn *insn; |
82d6b402 | 4503 | |
e0d80184 | 4504 | if (reg == 0) |
82d6b402 | 4505 | { |
cedced65 | 4506 | gcc_assert (can_create_pseudo_p ()); |
f5f7d171 | 4507 | reg = gen_reg_rtx (Pmode); |
82d6b402 | 4508 | } |
795068a4 | 4509 | |
e0d80184 | 4510 | if (flag_pic == 2) |
4fb4e4b8 | 4511 | { |
e0d80184 DM |
4512 | /* If not during reload, allocate another temp reg here for loading |
4513 | in the address, so that these instructions can be optimized | |
4514 | properly. */ | |
cedced65 | 4515 | rtx temp_reg = (! can_create_pseudo_p () |
e0d80184 DM |
4516 | ? reg : gen_reg_rtx (Pmode)); |
4517 | ||
4518 | /* Must put the SYMBOL_REF inside an UNSPEC here so that cse | |
4519 | won't get confused into thinking that these two instructions | |
4520 | are loading in the true address of the symbol. If in the | |
4521 | future a PIC rtx exists, that should be used instead. */ | |
bea5071f | 4522 | if (TARGET_ARCH64) |
be3f1ff5 | 4523 | { |
bea5071f EB |
4524 | emit_insn (gen_movdi_high_pic (temp_reg, orig)); |
4525 | emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
be3f1ff5 DM |
4526 | } |
4527 | else | |
4528 | { | |
bea5071f EB |
4529 | emit_insn (gen_movsi_high_pic (temp_reg, orig)); |
4530 | emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
be3f1ff5 | 4531 | } |
e0d80184 | 4532 | address = temp_reg; |
878ee0ab | 4533 | gotdata_op = true; |
4fb4e4b8 DE |
4534 | } |
4535 | else | |
e0d80184 DM |
4536 | address = orig; |
4537 | ||
e3b5732b | 4538 | crtl->uses_pic_offset_table = 1; |
878ee0ab DM |
4539 | if (gotdata_op) |
4540 | { | |
4541 | if (TARGET_ARCH64) | |
58e6223e EB |
4542 | insn = emit_insn (gen_movdi_pic_gotdata_op (reg, |
4543 | pic_offset_table_rtx, | |
878ee0ab DM |
4544 | address, orig)); |
4545 | else | |
58e6223e EB |
4546 | insn = emit_insn (gen_movsi_pic_gotdata_op (reg, |
4547 | pic_offset_table_rtx, | |
878ee0ab DM |
4548 | address, orig)); |
4549 | } | |
4550 | else | |
4551 | { | |
205e4c6a EB |
4552 | pic_ref |
4553 | = gen_const_mem (Pmode, | |
4554 | gen_rtx_PLUS (Pmode, | |
4555 | pic_offset_table_rtx, address)); | |
878ee0ab DM |
4556 | insn = emit_move_insn (reg, pic_ref); |
4557 | } | |
205e4c6a | 4558 | |
e0d80184 DM |
4559 | /* Put a REG_EQUAL note on this insn, so that it can be optimized |
4560 | by loop. */ | |
bd94cb6e | 4561 | set_unique_reg_note (insn, REG_EQUAL, orig); |
e0d80184 | 4562 | return reg; |
795068a4 | 4563 | } |
e0d80184 | 4564 | else if (GET_CODE (orig) == CONST) |
795068a4 | 4565 | { |
e0d80184 | 4566 | rtx base, offset; |
795068a4 | 4567 | |
e0d80184 DM |
4568 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
4569 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
4570 | return orig; | |
82d6b402 | 4571 | |
e0d80184 | 4572 | if (reg == 0) |
4fb4e4b8 | 4573 | { |
cedced65 | 4574 | gcc_assert (can_create_pseudo_p ()); |
f5f7d171 | 4575 | reg = gen_reg_rtx (Pmode); |
4fb4e4b8 | 4576 | } |
e0d80184 | 4577 | |
f5f7d171 | 4578 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
58e6223e EB |
4579 | base = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg); |
4580 | offset = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
4581 | base == reg ? NULL_RTX : reg); | |
61a66555 | 4582 | |
e0d80184 DM |
4583 | if (GET_CODE (offset) == CONST_INT) |
4584 | { | |
4585 | if (SMALL_INT (offset)) | |
0a81f074 | 4586 | return plus_constant (Pmode, base, INTVAL (offset)); |
cedced65 | 4587 | else if (can_create_pseudo_p ()) |
e0d80184 DM |
4588 | offset = force_reg (Pmode, offset); |
4589 | else | |
4590 | /* If we reach here, then something is seriously wrong. */ | |
f5f7d171 | 4591 | gcc_unreachable (); |
e0d80184 DM |
4592 | } |
4593 | return gen_rtx_PLUS (Pmode, base, offset); | |
795068a4 | 4594 | } |
e0d80184 | 4595 | else if (GET_CODE (orig) == LABEL_REF) |
205e4c6a EB |
4596 | /* ??? We ought to be checking that the register is live instead, in case |
4597 | it is eliminated. */ | |
e3b5732b | 4598 | crtl->uses_pic_offset_table = 1; |
795068a4 | 4599 | |
e0d80184 DM |
4600 | return orig; |
4601 | } | |
795068a4 | 4602 | |
5751a10b JJ |
4603 | /* Try machine-dependent ways of modifying an illegitimate address X |
4604 | to be legitimate. If we find one, return the new, valid address. | |
4605 | ||
4606 | OLDX is the address as it was before break_out_memory_refs was called. | |
4607 | In some cases it is useful to look at this to decide what needs to be done. | |
4608 | ||
506d7b68 PB |
4609 | MODE is the mode of the operand pointed to by X. |
4610 | ||
4611 | On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ | |
5751a10b | 4612 | |
208384fd | 4613 | static rtx |
506d7b68 | 4614 | sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
ef4bddc2 | 4615 | machine_mode mode) |
5751a10b JJ |
4616 | { |
4617 | rtx orig_x = x; | |
4618 | ||
4619 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT) | |
4620 | x = gen_rtx_PLUS (Pmode, XEXP (x, 1), | |
4621 | force_operand (XEXP (x, 0), NULL_RTX)); | |
4622 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT) | |
4623 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
4624 | force_operand (XEXP (x, 1), NULL_RTX)); | |
4625 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS) | |
4626 | x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX), | |
4627 | XEXP (x, 1)); | |
4628 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS) | |
4629 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
4630 | force_operand (XEXP (x, 1), NULL_RTX)); | |
4631 | ||
c6c3dba9 | 4632 | if (x != orig_x && sparc_legitimate_address_p (mode, x, FALSE)) |
5751a10b JJ |
4633 | return x; |
4634 | ||
208384fd | 4635 | if (sparc_tls_referenced_p (x)) |
58e6223e | 4636 | x = sparc_legitimize_tls_address (x); |
5751a10b | 4637 | else if (flag_pic) |
58e6223e | 4638 | x = sparc_legitimize_pic_address (x, NULL_RTX); |
5751a10b JJ |
4639 | else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1))) |
4640 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
4641 | copy_to_mode_reg (Pmode, XEXP (x, 1))); | |
4642 | else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0))) | |
4643 | x = gen_rtx_PLUS (Pmode, XEXP (x, 1), | |
4644 | copy_to_mode_reg (Pmode, XEXP (x, 0))); | |
4645 | else if (GET_CODE (x) == SYMBOL_REF | |
4646 | || GET_CODE (x) == CONST | |
208384fd | 4647 | || GET_CODE (x) == LABEL_REF) |
5751a10b | 4648 | x = copy_to_suggested_reg (x, NULL_RTX, Pmode); |
208384fd | 4649 | |
5751a10b JJ |
4650 | return x; |
4651 | } | |
4652 | ||
8e7a6ed6 EB |
4653 | /* Delegitimize an address that was legitimized by the above function. */ |
4654 | ||
4655 | static rtx | |
4656 | sparc_delegitimize_address (rtx x) | |
4657 | { | |
4658 | x = delegitimize_mem_from_attrs (x); | |
4659 | ||
145f6c5b EB |
4660 | if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 1)) == UNSPEC) |
4661 | switch (XINT (XEXP (x, 1), 1)) | |
4662 | { | |
4663 | case UNSPEC_MOVE_PIC: | |
4664 | case UNSPEC_TLSLE: | |
4665 | x = XVECEXP (XEXP (x, 1), 0, 0); | |
4666 | gcc_assert (GET_CODE (x) == SYMBOL_REF); | |
4667 | break; | |
4668 | default: | |
4669 | break; | |
4670 | } | |
8e7a6ed6 | 4671 | |
806c3492 EB |
4672 | /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */ |
4673 | if (GET_CODE (x) == MINUS | |
4674 | && REG_P (XEXP (x, 0)) | |
4675 | && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM | |
4676 | && GET_CODE (XEXP (x, 1)) == LO_SUM | |
4677 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == UNSPEC | |
4678 | && XINT (XEXP (XEXP (x, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL) | |
4679 | { | |
4680 | x = XVECEXP (XEXP (XEXP (x, 1), 1), 0, 0); | |
4681 | gcc_assert (GET_CODE (x) == LABEL_REF); | |
4682 | } | |
4683 | ||
8e7a6ed6 EB |
4684 | return x; |
4685 | } | |
4686 | ||
58e6223e EB |
4687 | /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to |
4688 | replace the input X, or the original X if no replacement is called for. | |
4689 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
4690 | 0 if it should not. | |
4691 | ||
4692 | For SPARC, we wish to handle addresses by splitting them into | |
4693 | HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference. | |
4694 | This cuts the number of extra insns by one. | |
4695 | ||
4696 | Do nothing when generating PIC code and the address is a symbolic | |
4697 | operand or requires a scratch register. */ | |
4698 | ||
4699 | rtx | |
ef4bddc2 | 4700 | sparc_legitimize_reload_address (rtx x, machine_mode mode, |
58e6223e EB |
4701 | int opnum, int type, |
4702 | int ind_levels ATTRIBUTE_UNUSED, int *win) | |
4703 | { | |
4704 | /* Decompose SImode constants into HIGH+LO_SUM. */ | |
4705 | if (CONSTANT_P (x) | |
4706 | && (mode != TFmode || TARGET_ARCH64) | |
4707 | && GET_MODE (x) == SImode | |
4708 | && GET_CODE (x) != LO_SUM | |
4709 | && GET_CODE (x) != HIGH | |
4710 | && sparc_cmodel <= CM_MEDLOW | |
4711 | && !(flag_pic | |
4712 | && (symbolic_operand (x, Pmode) || pic_address_needs_scratch (x)))) | |
4713 | { | |
4714 | x = gen_rtx_LO_SUM (GET_MODE (x), gen_rtx_HIGH (GET_MODE (x), x), x); | |
4715 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
4716 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
4717 | opnum, (enum reload_type)type); | |
4718 | *win = 1; | |
4719 | return x; | |
4720 | } | |
4721 | ||
4722 | /* We have to recognize what we have already generated above. */ | |
4723 | if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == HIGH) | |
4724 | { | |
4725 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
4726 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
4727 | opnum, (enum reload_type)type); | |
4728 | *win = 1; | |
4729 | return x; | |
4730 | } | |
4731 | ||
4732 | *win = 0; | |
4733 | return x; | |
4734 | } | |
4735 | ||
277e2873 AS |
4736 | /* Return true if ADDR (a legitimate address expression) |
4737 | has an effect that depends on the machine mode it is used for. | |
4738 | ||
4739 | In PIC mode, | |
4740 | ||
4741 | (mem:HI [%l7+a]) | |
4742 | ||
4743 | is not equivalent to | |
4744 | ||
4745 | (mem:QI [%l7+a]) (mem:QI [%l7+a+1]) | |
4746 | ||
4747 | because [%l7+a+1] is interpreted as the address of (a+1). */ | |
4748 | ||
4749 | ||
4750 | static bool | |
5bfed9a9 GJL |
4751 | sparc_mode_dependent_address_p (const_rtx addr, |
4752 | addr_space_t as ATTRIBUTE_UNUSED) | |
277e2873 AS |
4753 | { |
4754 | if (flag_pic && GET_CODE (addr) == PLUS) | |
4755 | { | |
4756 | rtx op0 = XEXP (addr, 0); | |
4757 | rtx op1 = XEXP (addr, 1); | |
4758 | if (op0 == pic_offset_table_rtx | |
8b9a1428 | 4759 | && symbolic_operand (op1, VOIDmode)) |
277e2873 AS |
4760 | return true; |
4761 | } | |
4762 | ||
4763 | return false; | |
4764 | } | |
4765 | ||
9fd52c6c DM |
4766 | #ifdef HAVE_GAS_HIDDEN |
4767 | # define USE_HIDDEN_LINKONCE 1 | |
4768 | #else | |
4769 | # define USE_HIDDEN_LINKONCE 0 | |
4770 | #endif | |
795068a4 | 4771 | |
9ac617d4 | 4772 | static void |
9fd52c6c | 4773 | get_pc_thunk_name (char name[32], unsigned int regno) |
e0d80184 | 4774 | { |
a6fed83f | 4775 | const char *reg_name = reg_names[regno]; |
4fb4e4b8 | 4776 | |
9fd52c6c DM |
4777 | /* Skip the leading '%' as that cannot be used in a |
4778 | symbol name. */ | |
a6fed83f | 4779 | reg_name += 1; |
82d6b402 | 4780 | |
9fd52c6c | 4781 | if (USE_HIDDEN_LINKONCE) |
a6fed83f | 4782 | sprintf (name, "__sparc_get_pc_thunk.%s", reg_name); |
5e77eb53 | 4783 | else |
9fd52c6c | 4784 | ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno); |
5e77eb53 EB |
4785 | } |
4786 | ||
a6fed83f | 4787 | /* Wrapper around the load_pcrel_sym{si,di} patterns. */ |
5e77eb53 | 4788 | |
a6fed83f EB |
4789 | static rtx |
4790 | gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2, rtx op3) | |
5e77eb53 EB |
4791 | { |
4792 | int orig_flag_pic = flag_pic; | |
a6fed83f | 4793 | rtx insn; |
5e77eb53 | 4794 | |
a6fed83f EB |
4795 | /* The load_pcrel_sym{si,di} patterns require absolute addressing. */ |
4796 | flag_pic = 0; | |
4797 | if (TARGET_ARCH64) | |
4798 | insn = gen_load_pcrel_symdi (op0, op1, op2, op3); | |
4799 | else | |
4800 | insn = gen_load_pcrel_symsi (op0, op1, op2, op3); | |
4801 | flag_pic = orig_flag_pic; | |
9fd52c6c | 4802 | |
a6fed83f EB |
4803 | return insn; |
4804 | } | |
9fd52c6c | 4805 | |
a6fed83f | 4806 | /* Emit code to load the GOT register. */ |
9fd52c6c | 4807 | |
bc6d3f91 | 4808 | void |
a6fed83f EB |
4809 | load_got_register (void) |
4810 | { | |
4811 | /* In PIC mode, this will retrieve pic_offset_table_rtx. */ | |
4812 | if (!global_offset_table_rtx) | |
4813 | global_offset_table_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM); | |
82d6b402 | 4814 | |
a6fed83f EB |
4815 | if (TARGET_VXWORKS_RTP) |
4816 | emit_insn (gen_vxworks_load_got ()); | |
eb7a7903 | 4817 | else |
a6fed83f EB |
4818 | { |
4819 | /* The GOT symbol is subject to a PC-relative relocation so we need a | |
4820 | helper function to add the PC value and thus get the final value. */ | |
4821 | if (!got_helper_rtx) | |
4822 | { | |
4823 | char name[32]; | |
4824 | get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM); | |
4825 | got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); | |
4826 | } | |
4827 | ||
4828 | emit_insn (gen_load_pcrel_sym (global_offset_table_rtx, sparc_got (), | |
4829 | got_helper_rtx, | |
4830 | GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM))); | |
4831 | } | |
82d6b402 | 4832 | |
e0d80184 DM |
4833 | /* Need to emit this whether or not we obey regdecls, |
4834 | since setjmp/longjmp can cause life info to screw up. | |
4835 | ??? In the case where we don't obey regdecls, this is not sufficient | |
4836 | since we may not fall out the bottom. */ | |
a6fed83f | 4837 | emit_use (global_offset_table_rtx); |
795068a4 | 4838 | } |
1910440e RS |
4839 | |
4840 | /* Emit a call instruction with the pattern given by PAT. ADDR is the | |
4841 | address of the call target. */ | |
4842 | ||
4843 | void | |
4844 | sparc_emit_call_insn (rtx pat, rtx addr) | |
4845 | { | |
e1faf324 | 4846 | rtx_insn *insn; |
1910440e RS |
4847 | |
4848 | insn = emit_call_insn (pat); | |
4849 | ||
4850 | /* The PIC register is live on entry to VxWorks PIC PLT entries. */ | |
4851 | if (TARGET_VXWORKS_RTP | |
4852 | && flag_pic | |
4853 | && GET_CODE (addr) == SYMBOL_REF | |
4854 | && (SYMBOL_REF_DECL (addr) | |
4855 | ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr)) | |
4856 | : !SYMBOL_REF_LOCAL_P (addr))) | |
4857 | { | |
4858 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); | |
e3b5732b | 4859 | crtl->uses_pic_offset_table = 1; |
1910440e RS |
4860 | } |
4861 | } | |
ab835497 | 4862 | \f |
e0d80184 | 4863 | /* Return 1 if RTX is a MEM which is known to be aligned to at |
7a31a340 | 4864 | least a DESIRED byte boundary. */ |
a3ee5899 | 4865 | |
e0d80184 | 4866 | int |
fc27d102 | 4867 | mem_min_alignment (rtx mem, int desired) |
ab835497 | 4868 | { |
e0d80184 DM |
4869 | rtx addr, base, offset; |
4870 | ||
4871 | /* If it's not a MEM we can't accept it. */ | |
4872 | if (GET_CODE (mem) != MEM) | |
4873 | return 0; | |
4874 | ||
167a1354 | 4875 | /* Obviously... */ |
0f95e914 EB |
4876 | if (!TARGET_UNALIGNED_DOUBLES |
4877 | && MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired) | |
167a1354 EB |
4878 | return 1; |
4879 | ||
4880 | /* ??? The rest of the function predates MEM_ALIGN so | |
4881 | there is probably a bit of redundancy. */ | |
e0d80184 DM |
4882 | addr = XEXP (mem, 0); |
4883 | base = offset = NULL_RTX; | |
4884 | if (GET_CODE (addr) == PLUS) | |
ab835497 | 4885 | { |
e0d80184 | 4886 | if (GET_CODE (XEXP (addr, 0)) == REG) |
61a55e8b | 4887 | { |
e0d80184 DM |
4888 | base = XEXP (addr, 0); |
4889 | ||
4890 | /* What we are saying here is that if the base | |
4891 | REG is aligned properly, the compiler will make | |
4892 | sure any REG based index upon it will be so | |
4893 | as well. */ | |
4894 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
4895 | offset = XEXP (addr, 1); | |
61a55e8b | 4896 | else |
e0d80184 | 4897 | offset = const0_rtx; |
61a55e8b | 4898 | } |
ab835497 | 4899 | } |
e0d80184 | 4900 | else if (GET_CODE (addr) == REG) |
ab835497 | 4901 | { |
e0d80184 DM |
4902 | base = addr; |
4903 | offset = const0_rtx; | |
ab835497 | 4904 | } |
82d6b402 | 4905 | |
e0d80184 | 4906 | if (base != NULL_RTX) |
795068a4 | 4907 | { |
e0d80184 DM |
4908 | int regno = REGNO (base); |
4909 | ||
563c12b0 | 4910 | if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM) |
61a55e8b | 4911 | { |
e0d80184 DM |
4912 | /* Check if the compiler has recorded some information |
4913 | about the alignment of the base REG. If reload has | |
021e2ecc JJ |
4914 | completed, we already matched with proper alignments. |
4915 | If not running global_alloc, reload might give us | |
4916 | unaligned pointer to local stack though. */ | |
bdb429a5 RK |
4917 | if (((cfun != 0 |
4918 | && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT) | |
021e2ecc | 4919 | || (optimize && reload_completed)) |
bdb429a5 | 4920 | && (INTVAL (offset) & (desired - 1)) == 0) |
e0d80184 | 4921 | return 1; |
61a55e8b | 4922 | } |
795068a4 | 4923 | else |
e0d80184 DM |
4924 | { |
4925 | if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) | |
4926 | return 1; | |
4927 | } | |
795068a4 | 4928 | } |
e0d80184 DM |
4929 | else if (! TARGET_UNALIGNED_DOUBLES |
4930 | || CONSTANT_P (addr) | |
4931 | || GET_CODE (addr) == LO_SUM) | |
795068a4 | 4932 | { |
e0d80184 DM |
4933 | /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES |
4934 | is true, in which case we can only assume that an access is aligned if | |
4935 | it is to a constant address, or the address involves a LO_SUM. */ | |
4936 | return 1; | |
795068a4 | 4937 | } |
4900aa61 | 4938 | |
e0d80184 DM |
4939 | /* An obviously unaligned address. */ |
4940 | return 0; | |
795068a4 | 4941 | } |
e0d80184 | 4942 | |
ab835497 | 4943 | \f |
61a55e8b | 4944 | /* Vectors to keep interesting information about registers where it can easily |
01d3224a | 4945 | be got. We used to use the actual mode value as the bit number, but there |
61a55e8b DE |
4946 | are more than 32 modes now. Instead we use two tables: one indexed by |
4947 | hard register number, and one indexed by mode. */ | |
4948 | ||
4949 | /* The purpose of sparc_mode_class is to shrink the range of modes so that | |
a7b376ee | 4950 | they all fit (as bit numbers) in a 32-bit word (again). Each real mode is |
61a55e8b DE |
4951 | mapped into one sparc_mode_class mode. */ |
4952 | ||
4953 | enum sparc_mode_class { | |
811b72f9 | 4954 | H_MODE, S_MODE, D_MODE, T_MODE, O_MODE, |
c4ce6853 DE |
4955 | SF_MODE, DF_MODE, TF_MODE, OF_MODE, |
4956 | CC_MODE, CCFP_MODE | |
61a55e8b | 4957 | }; |
ab835497 | 4958 | |
61a55e8b | 4959 | /* Modes for single-word and smaller quantities. */ |
811b72f9 EB |
4960 | #define S_MODES \ |
4961 | ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
61a55e8b DE |
4962 | |
4963 | /* Modes for double-word and smaller quantities. */ | |
f99bd883 | 4964 | #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE)) |
61a55e8b DE |
4965 | |
4966 | /* Modes for quad-word and smaller quantities. */ | |
4967 | #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
ab835497 | 4968 | |
d0cee9ba JJ |
4969 | /* Modes for 8-word and smaller quantities. */ |
4970 | #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) | |
4971 | ||
811b72f9 EB |
4972 | /* Modes for single-float quantities. */ |
4973 | #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
ab835497 | 4974 | |
61a55e8b | 4975 | /* Modes for double-float and smaller quantities. */ |
f99bd883 | 4976 | #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE)) |
61a55e8b DE |
4977 | |
4978 | /* Modes for quad-float and smaller quantities. */ | |
dc2a24ed | 4979 | #define TF_MODES (DF_MODES | (1 << (int) TF_MODE)) |
61a55e8b | 4980 | |
948bf106 | 4981 | /* Modes for quad-float pairs and smaller quantities. */ |
dc2a24ed | 4982 | #define OF_MODES (TF_MODES | (1 << (int) OF_MODE)) |
d0cee9ba | 4983 | |
948bf106 EB |
4984 | /* Modes for double-float only quantities. */ |
4985 | #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) | |
d0cee9ba | 4986 | |
948bf106 | 4987 | /* Modes for quad-float and double-float only quantities. */ |
dc2a24ed | 4988 | #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE)) |
d0cee9ba | 4989 | |
948bf106 | 4990 | /* Modes for quad-float pairs and double-float only quantities. */ |
dc2a24ed | 4991 | #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE)) |
ab835497 | 4992 | |
c4ce6853 DE |
4993 | /* Modes for condition codes. */ |
4994 | #define CC_MODES (1 << (int) CC_MODE) | |
4995 | #define CCFP_MODES (1 << (int) CCFP_MODE) | |
4996 | ||
ab835497 | 4997 | /* Value is 1 if register/mode pair is acceptable on sparc. |
ca3e6775 | 4998 | |
ab835497 RK |
4999 | The funny mixture of D and T modes is because integer operations |
5000 | do not specially operate on tetra quantities, so non-quad-aligned | |
5001 | registers can hold quadword quantities (except %o4 and %i4 because | |
ca3e6775 EB |
5002 | they cross fixed registers). |
5003 | ||
5004 | ??? Note that, despite the settings, non-double-aligned parameter | |
5005 | registers can hold double-word quantities in 32-bit mode. */ | |
ab835497 | 5006 | |
a7faf57b | 5007 | /* This points to either the 32-bit or the 64-bit version. */ |
f939c3e6 | 5008 | static const int *hard_regno_mode_classes; |
61a55e8b | 5009 | |
0b5826ac | 5010 | static const int hard_32bit_mode_classes[] = { |
c4ce6853 | 5011 | S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, |
ab835497 RK |
5012 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, |
5013 | T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
5014 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
5015 | ||
d0cee9ba JJ |
5016 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
5017 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
5018 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
5019 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
a9e27770 DE |
5020 | |
5021 | /* FP regs f32 to f63. Only the even numbered registers actually exist, | |
5022 | and none can hold SFmode/SImode values. */ | |
d0cee9ba JJ |
5023 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
5024 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
5025 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
5026 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
a9e27770 DE |
5027 | |
5028 | /* %fcc[0123] */ | |
c4ce6853 DE |
5029 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
5030 | ||
10b859c0 DM |
5031 | /* %icc, %sfp, %gsr */ |
5032 | CC_MODES, 0, D_MODES | |
61a55e8b DE |
5033 | }; |
5034 | ||
0b5826ac | 5035 | static const int hard_64bit_mode_classes[] = { |
c4ce6853 | 5036 | D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 5037 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 5038 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 5039 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 5040 | |
d0cee9ba JJ |
5041 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
5042 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
5043 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
5044 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
61a55e8b | 5045 | |
a9e27770 | 5046 | /* FP regs f32 to f63. Only the even numbered registers actually exist, |
61a55e8b | 5047 | and none can hold SFmode/SImode values. */ |
d0cee9ba JJ |
5048 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
5049 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
5050 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
5051 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
61a55e8b DE |
5052 | |
5053 | /* %fcc[0123] */ | |
c4ce6853 DE |
5054 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
5055 | ||
10b859c0 DM |
5056 | /* %icc, %sfp, %gsr */ |
5057 | CC_MODES, 0, D_MODES | |
61a55e8b DE |
5058 | }; |
5059 | ||
f939c3e6 | 5060 | static int sparc_mode_class [NUM_MACHINE_MODES]; |
61a55e8b | 5061 | |
c4ce6853 DE |
5062 | enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
5063 | ||
61a55e8b | 5064 | static void |
fc27d102 | 5065 | sparc_init_modes (void) |
61a55e8b DE |
5066 | { |
5067 | int i; | |
5068 | ||
61a55e8b DE |
5069 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
5070 | { | |
ef4bddc2 | 5071 | machine_mode m = (machine_mode) i; |
f2a2c4b5 RH |
5072 | unsigned int size = GET_MODE_SIZE (m); |
5073 | ||
4552e70c | 5074 | switch (GET_MODE_CLASS (m)) |
61a55e8b DE |
5075 | { |
5076 | case MODE_INT: | |
5077 | case MODE_PARTIAL_INT: | |
5078 | case MODE_COMPLEX_INT: | |
f2a2c4b5 | 5079 | if (size < 4) |
811b72f9 | 5080 | sparc_mode_class[i] = 1 << (int) H_MODE; |
f2a2c4b5 | 5081 | else if (size == 4) |
61a55e8b | 5082 | sparc_mode_class[i] = 1 << (int) S_MODE; |
f2a2c4b5 | 5083 | else if (size == 8) |
61a55e8b | 5084 | sparc_mode_class[i] = 1 << (int) D_MODE; |
f2a2c4b5 | 5085 | else if (size == 16) |
61a55e8b | 5086 | sparc_mode_class[i] = 1 << (int) T_MODE; |
f2a2c4b5 | 5087 | else if (size == 32) |
61a55e8b | 5088 | sparc_mode_class[i] = 1 << (int) O_MODE; |
4900aa61 | 5089 | else |
61a55e8b DE |
5090 | sparc_mode_class[i] = 0; |
5091 | break; | |
c75d6010 | 5092 | case MODE_VECTOR_INT: |
f2a2c4b5 | 5093 | if (size == 4) |
811b72f9 | 5094 | sparc_mode_class[i] = 1 << (int) SF_MODE; |
f2a2c4b5 | 5095 | else if (size == 8) |
811b72f9 EB |
5096 | sparc_mode_class[i] = 1 << (int) DF_MODE; |
5097 | else | |
5098 | sparc_mode_class[i] = 0; | |
c75d6010 | 5099 | break; |
61a55e8b DE |
5100 | case MODE_FLOAT: |
5101 | case MODE_COMPLEX_FLOAT: | |
f2a2c4b5 | 5102 | if (size == 4) |
61a55e8b | 5103 | sparc_mode_class[i] = 1 << (int) SF_MODE; |
f2a2c4b5 | 5104 | else if (size == 8) |
61a55e8b | 5105 | sparc_mode_class[i] = 1 << (int) DF_MODE; |
f2a2c4b5 | 5106 | else if (size == 16) |
61a55e8b | 5107 | sparc_mode_class[i] = 1 << (int) TF_MODE; |
f2a2c4b5 | 5108 | else if (size == 32) |
61a55e8b | 5109 | sparc_mode_class[i] = 1 << (int) OF_MODE; |
4900aa61 | 5110 | else |
61a55e8b DE |
5111 | sparc_mode_class[i] = 0; |
5112 | break; | |
5113 | case MODE_CC: | |
4552e70c | 5114 | if (m == CCFPmode || m == CCFPEmode) |
61a55e8b | 5115 | sparc_mode_class[i] = 1 << (int) CCFP_MODE; |
61a55e8b | 5116 | else |
94134f42 ZW |
5117 | sparc_mode_class[i] = 1 << (int) CC_MODE; |
5118 | break; | |
5119 | default: | |
5120 | sparc_mode_class[i] = 0; | |
61a55e8b DE |
5121 | break; |
5122 | } | |
5123 | } | |
5124 | ||
a9e27770 | 5125 | if (TARGET_ARCH64) |
61a55e8b DE |
5126 | hard_regno_mode_classes = hard_64bit_mode_classes; |
5127 | else | |
5128 | hard_regno_mode_classes = hard_32bit_mode_classes; | |
c4ce6853 DE |
5129 | |
5130 | /* Initialize the array used by REGNO_REG_CLASS. */ | |
5131 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5132 | { | |
284d86e9 JC |
5133 | if (i < 16 && TARGET_V8PLUS) |
5134 | sparc_regno_reg_class[i] = I64_REGS; | |
563c12b0 | 5135 | else if (i < 32 || i == FRAME_POINTER_REGNUM) |
c4ce6853 DE |
5136 | sparc_regno_reg_class[i] = GENERAL_REGS; |
5137 | else if (i < 64) | |
5138 | sparc_regno_reg_class[i] = FP_REGS; | |
5139 | else if (i < 96) | |
5140 | sparc_regno_reg_class[i] = EXTRA_FP_REGS; | |
5141 | else if (i < 100) | |
5142 | sparc_regno_reg_class[i] = FPCC_REGS; | |
5143 | else | |
5144 | sparc_regno_reg_class[i] = NO_REGS; | |
5145 | } | |
61a55e8b | 5146 | } |
ab835497 | 5147 | \f |
b11b0904 EB |
5148 | /* Return whether REGNO, a global or FP register, must be saved/restored. */ |
5149 | ||
5150 | static inline bool | |
5151 | save_global_or_fp_reg_p (unsigned int regno, | |
5152 | int leaf_function ATTRIBUTE_UNUSED) | |
5153 | { | |
5154 | return !call_used_regs[regno] && df_regs_ever_live_p (regno); | |
5155 | } | |
5156 | ||
5157 | /* Return whether the return address register (%i7) is needed. */ | |
5158 | ||
5159 | static inline bool | |
5160 | return_addr_reg_needed_p (int leaf_function) | |
5161 | { | |
5162 | /* If it is live, for example because of __builtin_return_address (0). */ | |
5163 | if (df_regs_ever_live_p (RETURN_ADDR_REGNUM)) | |
5164 | return true; | |
5165 | ||
5166 | /* Otherwise, it is needed as save register if %o7 is clobbered. */ | |
5167 | if (!leaf_function | |
5168 | /* Loading the GOT register clobbers %o7. */ | |
5169 | || crtl->uses_pic_offset_table | |
5170 | || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM)) | |
5171 | return true; | |
5172 | ||
5173 | return false; | |
5174 | } | |
5175 | ||
5176 | /* Return whether REGNO, a local or in register, must be saved/restored. */ | |
5177 | ||
5178 | static bool | |
5179 | save_local_or_in_reg_p (unsigned int regno, int leaf_function) | |
5180 | { | |
5181 | /* General case: call-saved registers live at some point. */ | |
5182 | if (!call_used_regs[regno] && df_regs_ever_live_p (regno)) | |
5183 | return true; | |
5184 | ||
5185 | /* Frame pointer register (%fp) if needed. */ | |
5186 | if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) | |
5187 | return true; | |
5188 | ||
5189 | /* Return address register (%i7) if needed. */ | |
5190 | if (regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p (leaf_function)) | |
5191 | return true; | |
5192 | ||
605354f3 | 5193 | /* GOT register (%l7) if needed. */ |
b11b0904 EB |
5194 | if (regno == PIC_OFFSET_TABLE_REGNUM && crtl->uses_pic_offset_table) |
5195 | return true; | |
5196 | ||
5197 | /* If the function accesses prior frames, the frame pointer and the return | |
5198 | address of the previous frame must be saved on the stack. */ | |
5199 | if (crtl->accesses_prior_frames | |
5200 | && (regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM)) | |
5201 | return true; | |
5202 | ||
5203 | return false; | |
5204 | } | |
5205 | ||
61a55e8b | 5206 | /* Compute the frame size required by the function. This function is called |
9ac617d4 | 5207 | during the reload pass and also by sparc_expand_prologue. */ |
ab835497 | 5208 | |
6a151f87 | 5209 | HOST_WIDE_INT |
b11b0904 | 5210 | sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function) |
ab835497 | 5211 | { |
b11b0904 EB |
5212 | HOST_WIDE_INT frame_size, apparent_frame_size; |
5213 | int args_size, n_global_fp_regs = 0; | |
5214 | bool save_local_in_regs_p = false; | |
5215 | unsigned int i; | |
61a55e8b | 5216 | |
b11b0904 EB |
5217 | /* If the function allocates dynamic stack space, the dynamic offset is |
5218 | computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */ | |
5219 | if (leaf_function && !cfun->calls_alloca) | |
5220 | args_size = 0; | |
33074e5f | 5221 | else |
b11b0904 | 5222 | args_size = crtl->outgoing_args_size + REG_PARM_STACK_SPACE (cfun->decl); |
ab835497 | 5223 | |
b11b0904 EB |
5224 | /* Calculate space needed for global registers. */ |
5225 | if (TARGET_ARCH64) | |
5445cf2a EB |
5226 | { |
5227 | for (i = 0; i < 8; i++) | |
5228 | if (save_global_or_fp_reg_p (i, 0)) | |
5229 | n_global_fp_regs += 2; | |
5230 | } | |
b11b0904 | 5231 | else |
5445cf2a EB |
5232 | { |
5233 | for (i = 0; i < 8; i += 2) | |
5234 | if (save_global_or_fp_reg_p (i, 0) | |
5235 | || save_global_or_fp_reg_p (i + 1, 0)) | |
5236 | n_global_fp_regs += 2; | |
5237 | } | |
33074e5f | 5238 | |
b11b0904 EB |
5239 | /* In the flat window model, find out which local and in registers need to |
5240 | be saved. We don't reserve space in the current frame for them as they | |
5241 | will be spilled into the register window save area of the caller's frame. | |
5242 | However, as soon as we use this register window save area, we must create | |
5243 | that of the current frame to make it the live one. */ | |
5244 | if (TARGET_FLAT) | |
5245 | for (i = 16; i < 32; i++) | |
5246 | if (save_local_or_in_reg_p (i, leaf_function)) | |
5247 | { | |
5248 | save_local_in_regs_p = true; | |
5249 | break; | |
5250 | } | |
ab835497 | 5251 | |
b11b0904 EB |
5252 | /* Calculate space needed for FP registers. */ |
5253 | for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) | |
5254 | if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0)) | |
5255 | n_global_fp_regs += 2; | |
5256 | ||
5257 | if (size == 0 | |
5258 | && n_global_fp_regs == 0 | |
5259 | && args_size == 0 | |
5260 | && !save_local_in_regs_p) | |
5261 | frame_size = apparent_frame_size = 0; | |
61a55e8b DE |
5262 | else |
5263 | { | |
225909c3 | 5264 | /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */ |
63b8ef40 | 5265 | apparent_frame_size = ROUND_UP (size - STARTING_FRAME_OFFSET, 8); |
b11b0904 EB |
5266 | apparent_frame_size += n_global_fp_regs * 4; |
5267 | ||
5268 | /* We need to add the size of the outgoing argument area. */ | |
63b8ef40 | 5269 | frame_size = apparent_frame_size + ROUND_UP (args_size, 8); |
b11b0904 EB |
5270 | |
5271 | /* And that of the register window save area. */ | |
5272 | frame_size += FIRST_PARM_OFFSET (cfun->decl); | |
5273 | ||
5274 | /* Finally, bump to the appropriate alignment. */ | |
5275 | frame_size = SPARC_STACK_ALIGN (frame_size); | |
61a55e8b | 5276 | } |
ab835497 | 5277 | |
b11b0904 EB |
5278 | /* Set up values for use in prologue and epilogue. */ |
5279 | sparc_frame_size = frame_size; | |
5280 | sparc_apparent_frame_size = apparent_frame_size; | |
5281 | sparc_n_global_fp_regs = n_global_fp_regs; | |
5282 | sparc_save_local_in_regs_p = save_local_in_regs_p; | |
ab835497 | 5283 | |
b11b0904 | 5284 | return frame_size; |
61a55e8b DE |
5285 | } |
5286 | ||
9e6a4b77 SB |
5287 | /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */ |
5288 | ||
5289 | int | |
5290 | sparc_initial_elimination_offset (int to) | |
5291 | { | |
5292 | int offset; | |
5293 | ||
5294 | if (to == STACK_POINTER_REGNUM) | |
416ff32e | 5295 | offset = sparc_compute_frame_size (get_frame_size (), crtl->is_leaf); |
9e6a4b77 SB |
5296 | else |
5297 | offset = 0; | |
5298 | ||
5299 | offset += SPARC_STACK_BIAS; | |
5300 | return offset; | |
5301 | } | |
5302 | ||
9ac617d4 | 5303 | /* Output any necessary .register pseudo-ops. */ |
61a55e8b | 5304 | |
9ac617d4 EB |
5305 | void |
5306 | sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED) | |
61a55e8b | 5307 | { |
9ac617d4 EB |
5308 | #ifdef HAVE_AS_REGISTER_PSEUDO_OP |
5309 | int i; | |
6a151f87 | 5310 | |
9ac617d4 EB |
5311 | if (TARGET_ARCH32) |
5312 | return; | |
5313 | ||
5314 | /* Check if %g[2367] were used without | |
5315 | .register being printed for them already. */ | |
5316 | for (i = 2; i < 8; i++) | |
61a55e8b | 5317 | { |
6fb5fa3c | 5318 | if (df_regs_ever_live_p (i) |
9ac617d4 EB |
5319 | && ! sparc_hard_reg_printed [i]) |
5320 | { | |
5321 | sparc_hard_reg_printed [i] = 1; | |
392e5756 JJ |
5322 | /* %g7 is used as TLS base register, use #ignore |
5323 | for it instead of #scratch. */ | |
5324 | fprintf (file, "\t.register\t%%g%d, #%s\n", i, | |
5325 | i == 7 ? "ignore" : "scratch"); | |
9ac617d4 EB |
5326 | } |
5327 | if (i == 3) i = 5; | |
61a55e8b | 5328 | } |
6a151f87 | 5329 | #endif |
9ac617d4 | 5330 | } |
6a151f87 | 5331 | |
260c8ba3 EB |
5332 | #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP) |
5333 | ||
5334 | #if PROBE_INTERVAL > 4096 | |
5335 | #error Cannot use indexed addressing mode for stack probing | |
5336 | #endif | |
5337 | ||
5338 | /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE, | |
5339 | inclusive. These are offsets from the current stack pointer. | |
5340 | ||
5341 | Note that we don't use the REG+REG addressing mode for the probes because | |
5342 | of the stack bias in 64-bit mode. And it doesn't really buy us anything | |
5343 | so the advantages of having a single code win here. */ | |
5344 | ||
5345 | static void | |
5346 | sparc_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size) | |
5347 | { | |
5348 | rtx g1 = gen_rtx_REG (Pmode, 1); | |
5349 | ||
5350 | /* See if we have a constant small number of probes to generate. If so, | |
5351 | that's the easy case. */ | |
5352 | if (size <= PROBE_INTERVAL) | |
5353 | { | |
5354 | emit_move_insn (g1, GEN_INT (first)); | |
f7df4a84 | 5355 | emit_insn (gen_rtx_SET (g1, |
260c8ba3 | 5356 | gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1))); |
0a81f074 | 5357 | emit_stack_probe (plus_constant (Pmode, g1, -size)); |
260c8ba3 EB |
5358 | } |
5359 | ||
632b0921 | 5360 | /* The run-time loop is made up of 9 insns in the generic case while the |
260c8ba3 | 5361 | compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */ |
632b0921 | 5362 | else if (size <= 4 * PROBE_INTERVAL) |
260c8ba3 EB |
5363 | { |
5364 | HOST_WIDE_INT i; | |
5365 | ||
5366 | emit_move_insn (g1, GEN_INT (first + PROBE_INTERVAL)); | |
f7df4a84 | 5367 | emit_insn (gen_rtx_SET (g1, |
260c8ba3 EB |
5368 | gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1))); |
5369 | emit_stack_probe (g1); | |
5370 | ||
5371 | /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until | |
5372 | it exceeds SIZE. If only two probes are needed, this will not | |
5373 | generate any code. Then probe at FIRST + SIZE. */ | |
5374 | for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL) | |
5375 | { | |
f7df4a84 | 5376 | emit_insn (gen_rtx_SET (g1, |
0a81f074 | 5377 | plus_constant (Pmode, g1, -PROBE_INTERVAL))); |
260c8ba3 EB |
5378 | emit_stack_probe (g1); |
5379 | } | |
5380 | ||
0a81f074 RS |
5381 | emit_stack_probe (plus_constant (Pmode, g1, |
5382 | (i - PROBE_INTERVAL) - size)); | |
260c8ba3 EB |
5383 | } |
5384 | ||
5385 | /* Otherwise, do the same as above, but in a loop. Note that we must be | |
5386 | extra careful with variables wrapping around because we might be at | |
5387 | the very top (or the very bottom) of the address space and we have | |
5388 | to be able to handle this case properly; in particular, we use an | |
5389 | equality test for the loop condition. */ | |
5390 | else | |
5391 | { | |
5392 | HOST_WIDE_INT rounded_size; | |
5393 | rtx g4 = gen_rtx_REG (Pmode, 4); | |
5394 | ||
5395 | emit_move_insn (g1, GEN_INT (first)); | |
5396 | ||
5397 | ||
5398 | /* Step 1: round SIZE to the previous multiple of the interval. */ | |
5399 | ||
63b8ef40 | 5400 | rounded_size = ROUND_DOWN (size, PROBE_INTERVAL); |
260c8ba3 EB |
5401 | emit_move_insn (g4, GEN_INT (rounded_size)); |
5402 | ||
5403 | ||
5404 | /* Step 2: compute initial and final value of the loop counter. */ | |
5405 | ||
5406 | /* TEST_ADDR = SP + FIRST. */ | |
f7df4a84 | 5407 | emit_insn (gen_rtx_SET (g1, |
260c8ba3 EB |
5408 | gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1))); |
5409 | ||
5410 | /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */ | |
f7df4a84 | 5411 | emit_insn (gen_rtx_SET (g4, gen_rtx_MINUS (Pmode, g1, g4))); |
260c8ba3 EB |
5412 | |
5413 | ||
5414 | /* Step 3: the loop | |
5415 | ||
5416 | while (TEST_ADDR != LAST_ADDR) | |
5417 | { | |
5418 | TEST_ADDR = TEST_ADDR + PROBE_INTERVAL | |
5419 | probe at TEST_ADDR | |
5420 | } | |
5421 | ||
5422 | probes at FIRST + N * PROBE_INTERVAL for values of N from 1 | |
5423 | until it is equal to ROUNDED_SIZE. */ | |
5424 | ||
b9aaf52e | 5425 | if (TARGET_ARCH64) |
260c8ba3 EB |
5426 | emit_insn (gen_probe_stack_rangedi (g1, g1, g4)); |
5427 | else | |
5428 | emit_insn (gen_probe_stack_rangesi (g1, g1, g4)); | |
5429 | ||
5430 | ||
5431 | /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time | |
5432 | that SIZE is equal to ROUNDED_SIZE. */ | |
5433 | ||
5434 | if (size != rounded_size) | |
0a81f074 | 5435 | emit_stack_probe (plus_constant (Pmode, g4, rounded_size - size)); |
260c8ba3 EB |
5436 | } |
5437 | ||
5438 | /* Make sure nothing is scheduled before we are done. */ | |
5439 | emit_insn (gen_blockage ()); | |
5440 | } | |
5441 | ||
5442 | /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are | |
5443 | absolute addresses. */ | |
5444 | ||
5445 | const char * | |
5446 | output_probe_stack_range (rtx reg1, rtx reg2) | |
5447 | { | |
5448 | static int labelno = 0; | |
632b0921 | 5449 | char loop_lab[32]; |
260c8ba3 EB |
5450 | rtx xops[2]; |
5451 | ||
632b0921 | 5452 | ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++); |
260c8ba3 | 5453 | |
632b0921 | 5454 | /* Loop. */ |
260c8ba3 EB |
5455 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab); |
5456 | ||
632b0921 | 5457 | /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */ |
260c8ba3 | 5458 | xops[0] = reg1; |
632b0921 EB |
5459 | xops[1] = GEN_INT (-PROBE_INTERVAL); |
5460 | output_asm_insn ("add\t%0, %1, %0", xops); | |
5461 | ||
5462 | /* Test if TEST_ADDR == LAST_ADDR. */ | |
260c8ba3 EB |
5463 | xops[1] = reg2; |
5464 | output_asm_insn ("cmp\t%0, %1", xops); | |
260c8ba3 EB |
5465 | |
5466 | /* Probe at TEST_ADDR and branch. */ | |
5467 | if (TARGET_ARCH64) | |
632b0921 | 5468 | fputs ("\tbne,pt\t%xcc,", asm_out_file); |
260c8ba3 | 5469 | else |
632b0921 | 5470 | fputs ("\tbne\t", asm_out_file); |
260c8ba3 EB |
5471 | assemble_name_raw (asm_out_file, loop_lab); |
5472 | fputc ('\n', asm_out_file); | |
5473 | xops[1] = GEN_INT (SPARC_STACK_BIAS); | |
5474 | output_asm_insn (" st\t%%g0, [%0+%1]", xops); | |
5475 | ||
260c8ba3 EB |
5476 | return ""; |
5477 | } | |
5478 | ||
b11b0904 EB |
5479 | /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as |
5480 | needed. LOW is supposed to be double-word aligned for 32-bit registers. | |
5481 | SAVE_P decides whether a register must be saved/restored. ACTION_TRUE | |
5482 | is the action to be performed if SAVE_P returns true and ACTION_FALSE | |
5483 | the action to be performed if it returns false. Return the new offset. */ | |
6a151f87 | 5484 | |
b11b0904 EB |
5485 | typedef bool (*sorr_pred_t) (unsigned int, int); |
5486 | typedef enum { SORR_NONE, SORR_ADVANCE, SORR_SAVE, SORR_RESTORE } sorr_act_t; | |
9ac617d4 EB |
5487 | |
5488 | static int | |
b11b0904 EB |
5489 | emit_save_or_restore_regs (unsigned int low, unsigned int high, rtx base, |
5490 | int offset, int leaf_function, sorr_pred_t save_p, | |
5491 | sorr_act_t action_true, sorr_act_t action_false) | |
9ac617d4 | 5492 | { |
b11b0904 | 5493 | unsigned int i; |
e1faf324 DM |
5494 | rtx mem; |
5495 | rtx_insn *insn; | |
9ac617d4 EB |
5496 | |
5497 | if (TARGET_ARCH64 && high <= 32) | |
5498 | { | |
b11b0904 EB |
5499 | int fp_offset = -1; |
5500 | ||
9ac617d4 | 5501 | for (i = low; i < high; i++) |
6a151f87 | 5502 | { |
b11b0904 | 5503 | if (save_p (i, leaf_function)) |
9ac617d4 | 5504 | { |
0a81f074 RS |
5505 | mem = gen_frame_mem (DImode, plus_constant (Pmode, |
5506 | base, offset)); | |
b11b0904 | 5507 | if (action_true == SORR_SAVE) |
9ac617d4 EB |
5508 | { |
5509 | insn = emit_move_insn (mem, gen_rtx_REG (DImode, i)); | |
5510 | RTX_FRAME_RELATED_P (insn) = 1; | |
5511 | } | |
b11b0904 EB |
5512 | else /* action_true == SORR_RESTORE */ |
5513 | { | |
5514 | /* The frame pointer must be restored last since its old | |
5515 | value may be used as base address for the frame. This | |
5516 | is problematic in 64-bit mode only because of the lack | |
5517 | of double-word load instruction. */ | |
5518 | if (i == HARD_FRAME_POINTER_REGNUM) | |
5519 | fp_offset = offset; | |
5520 | else | |
5521 | emit_move_insn (gen_rtx_REG (DImode, i), mem); | |
5522 | } | |
9ac617d4 EB |
5523 | offset += 8; |
5524 | } | |
b11b0904 EB |
5525 | else if (action_false == SORR_ADVANCE) |
5526 | offset += 8; | |
5527 | } | |
5528 | ||
5529 | if (fp_offset >= 0) | |
5530 | { | |
0a81f074 | 5531 | mem = gen_frame_mem (DImode, plus_constant (Pmode, base, fp_offset)); |
b11b0904 | 5532 | emit_move_insn (hard_frame_pointer_rtx, mem); |
6a151f87 | 5533 | } |
9ac617d4 EB |
5534 | } |
5535 | else | |
5536 | { | |
5537 | for (i = low; i < high; i += 2) | |
6a151f87 | 5538 | { |
b11b0904 EB |
5539 | bool reg0 = save_p (i, leaf_function); |
5540 | bool reg1 = save_p (i + 1, leaf_function); | |
ef4bddc2 | 5541 | machine_mode mode; |
9ac617d4 EB |
5542 | int regno; |
5543 | ||
5544 | if (reg0 && reg1) | |
5545 | { | |
0d4a1197 | 5546 | mode = SPARC_INT_REG_P (i) ? E_DImode : E_DFmode; |
9ac617d4 EB |
5547 | regno = i; |
5548 | } | |
5549 | else if (reg0) | |
5550 | { | |
0d4a1197 | 5551 | mode = SPARC_INT_REG_P (i) ? E_SImode : E_SFmode; |
9ac617d4 EB |
5552 | regno = i; |
5553 | } | |
5554 | else if (reg1) | |
5555 | { | |
0d4a1197 | 5556 | mode = SPARC_INT_REG_P (i) ? E_SImode : E_SFmode; |
9ac617d4 EB |
5557 | regno = i + 1; |
5558 | offset += 4; | |
5559 | } | |
5560 | else | |
b11b0904 EB |
5561 | { |
5562 | if (action_false == SORR_ADVANCE) | |
5563 | offset += 8; | |
5564 | continue; | |
5565 | } | |
9ac617d4 | 5566 | |
0a81f074 | 5567 | mem = gen_frame_mem (mode, plus_constant (Pmode, base, offset)); |
b11b0904 | 5568 | if (action_true == SORR_SAVE) |
9ac617d4 EB |
5569 | { |
5570 | insn = emit_move_insn (mem, gen_rtx_REG (mode, regno)); | |
5571 | RTX_FRAME_RELATED_P (insn) = 1; | |
b11b0904 EB |
5572 | if (mode == DImode) |
5573 | { | |
5574 | rtx set1, set2; | |
0a81f074 RS |
5575 | mem = gen_frame_mem (SImode, plus_constant (Pmode, base, |
5576 | offset)); | |
f7df4a84 | 5577 | set1 = gen_rtx_SET (mem, gen_rtx_REG (SImode, regno)); |
b11b0904 EB |
5578 | RTX_FRAME_RELATED_P (set1) = 1; |
5579 | mem | |
0a81f074 RS |
5580 | = gen_frame_mem (SImode, plus_constant (Pmode, base, |
5581 | offset + 4)); | |
f7df4a84 | 5582 | set2 = gen_rtx_SET (mem, gen_rtx_REG (SImode, regno + 1)); |
b11b0904 EB |
5583 | RTX_FRAME_RELATED_P (set2) = 1; |
5584 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, | |
5585 | gen_rtx_PARALLEL (VOIDmode, | |
5586 | gen_rtvec (2, set1, set2))); | |
5587 | } | |
9ac617d4 | 5588 | } |
b11b0904 | 5589 | else /* action_true == SORR_RESTORE */ |
9ac617d4 EB |
5590 | emit_move_insn (gen_rtx_REG (mode, regno), mem); |
5591 | ||
63b8ef40 UB |
5592 | /* Bump and round down to double word |
5593 | in case we already bumped by 4. */ | |
5594 | offset = ROUND_DOWN (offset + 8, 8); | |
6a151f87 | 5595 | } |
6a151f87 | 5596 | } |
9ac617d4 EB |
5597 | |
5598 | return offset; | |
ab835497 RK |
5599 | } |
5600 | ||
b11b0904 EB |
5601 | /* Emit code to adjust BASE to OFFSET. Return the new base. */ |
5602 | ||
5603 | static rtx | |
5604 | emit_adjust_base_to_offset (rtx base, int offset) | |
5605 | { | |
5606 | /* ??? This might be optimized a little as %g1 might already have a | |
5607 | value close enough that a single add insn will do. */ | |
5608 | /* ??? Although, all of this is probably only a temporary fix because | |
5609 | if %g1 can hold a function result, then sparc_expand_epilogue will | |
5610 | lose (the result will be clobbered). */ | |
5611 | rtx new_base = gen_rtx_REG (Pmode, 1); | |
5612 | emit_move_insn (new_base, GEN_INT (offset)); | |
f7df4a84 | 5613 | emit_insn (gen_rtx_SET (new_base, gen_rtx_PLUS (Pmode, base, new_base))); |
b11b0904 EB |
5614 | return new_base; |
5615 | } | |
5616 | ||
5617 | /* Emit code to save/restore call-saved global and FP registers. */ | |
9ac617d4 EB |
5618 | |
5619 | static void | |
b11b0904 | 5620 | emit_save_or_restore_global_fp_regs (rtx base, int offset, sorr_act_t action) |
1cb36a98 | 5621 | { |
b11b0904 EB |
5622 | if (offset < -4096 || offset + sparc_n_global_fp_regs * 4 > 4095) |
5623 | { | |
5624 | base = emit_adjust_base_to_offset (base, offset); | |
5625 | offset = 0; | |
5626 | } | |
1cb36a98 | 5627 | |
b11b0904 EB |
5628 | offset |
5629 | = emit_save_or_restore_regs (0, 8, base, offset, 0, | |
5630 | save_global_or_fp_reg_p, action, SORR_NONE); | |
5631 | emit_save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, 0, | |
5632 | save_global_or_fp_reg_p, action, SORR_NONE); | |
5633 | } | |
1cb36a98 | 5634 | |
b11b0904 EB |
5635 | /* Emit code to save/restore call-saved local and in registers. */ |
5636 | ||
5637 | static void | |
5638 | emit_save_or_restore_local_in_regs (rtx base, int offset, sorr_act_t action) | |
5639 | { | |
5640 | if (offset < -4096 || offset + 16 * UNITS_PER_WORD > 4095) | |
1cb36a98 | 5641 | { |
b11b0904 | 5642 | base = emit_adjust_base_to_offset (base, offset); |
9ac617d4 | 5643 | offset = 0; |
1cb36a98 | 5644 | } |
9ac617d4 | 5645 | |
b11b0904 EB |
5646 | emit_save_or_restore_regs (16, 32, base, offset, sparc_leaf_function_p, |
5647 | save_local_or_in_reg_p, action, SORR_ADVANCE); | |
9ac617d4 | 5648 | } |
08c148a8 | 5649 | |
18970372 | 5650 | /* Emit a window_save insn. */ |
08c148a8 | 5651 | |
e1faf324 | 5652 | static rtx_insn * |
18970372 | 5653 | emit_window_save (rtx increment) |
08c148a8 | 5654 | { |
e1faf324 | 5655 | rtx_insn *insn = emit_insn (gen_window_save (increment)); |
78a8eb4e RH |
5656 | RTX_FRAME_RELATED_P (insn) = 1; |
5657 | ||
605354f3 | 5658 | /* The incoming return address (%o7) is saved in %i7. */ |
78a8eb4e | 5659 | add_reg_note (insn, REG_CFA_REGISTER, |
f7df4a84 | 5660 | gen_rtx_SET (gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM), |
605354f3 EB |
5661 | gen_rtx_REG (Pmode, |
5662 | INCOMING_RETURN_ADDR_REGNUM))); | |
78a8eb4e RH |
5663 | |
5664 | /* The window save event. */ | |
5665 | add_reg_note (insn, REG_CFA_WINDOW_SAVE, const0_rtx); | |
5666 | ||
5667 | /* The CFA is %fp, the hard frame pointer. */ | |
5668 | add_reg_note (insn, REG_CFA_DEF_CFA, | |
0a81f074 | 5669 | plus_constant (Pmode, hard_frame_pointer_rtx, |
78a8eb4e RH |
5670 | INCOMING_FRAME_SP_OFFSET)); |
5671 | ||
5672 | return insn; | |
08c148a8 NB |
5673 | } |
5674 | ||
e54c7471 | 5675 | /* Generate an increment for the stack pointer. */ |
915f619f | 5676 | |
e54c7471 EB |
5677 | static rtx |
5678 | gen_stack_pointer_inc (rtx increment) | |
ab835497 | 5679 | { |
f7df4a84 | 5680 | return gen_rtx_SET (stack_pointer_rtx, |
6deb0339 EB |
5681 | gen_rtx_PLUS (Pmode, |
5682 | stack_pointer_rtx, | |
5683 | increment)); | |
e54c7471 EB |
5684 | } |
5685 | ||
9ac617d4 EB |
5686 | /* Expand the function prologue. The prologue is responsible for reserving |
5687 | storage for the frame, saving the call-saved registers and loading the | |
a6fed83f | 5688 | GOT register if needed. */ |
9ac617d4 EB |
5689 | |
5690 | void | |
5691 | sparc_expand_prologue (void) | |
5692 | { | |
b11b0904 | 5693 | HOST_WIDE_INT size; |
e1faf324 | 5694 | rtx_insn *insn; |
e54c7471 | 5695 | |
416ff32e | 5696 | /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying |
5be9b7a1 EB |
5697 | on the final value of the flag means deferring the prologue/epilogue |
5698 | expansion until just before the second scheduling pass, which is too | |
5699 | late to emit multiple epilogues or return insns. | |
5700 | ||
5701 | Of course we are making the assumption that the value of the flag | |
5702 | will not change between now and its final value. Of the three parts | |
5703 | of the formula, only the last one can reasonably vary. Let's take a | |
5704 | closer look, after assuming that the first two ones are set to true | |
5705 | (otherwise the last value is effectively silenced). | |
5706 | ||
5707 | If only_leaf_regs_used returns false, the global predicate will also | |
5708 | be false so the actual frame size calculated below will be positive. | |
5709 | As a consequence, the save_register_window insn will be emitted in | |
5710 | the instruction stream; now this insn explicitly references %fp | |
5711 | which is not a leaf register so only_leaf_regs_used will always | |
5712 | return false subsequently. | |
5713 | ||
5714 | If only_leaf_regs_used returns true, we hope that the subsequent | |
5715 | optimization passes won't cause non-leaf registers to pop up. For | |
5716 | example, the regrename pass has special provisions to not rename to | |
5717 | non-leaf registers in a leaf function. */ | |
5718 | sparc_leaf_function_p | |
416ff32e | 5719 | = optimize > 0 && crtl->is_leaf && only_leaf_regs_used (); |
1cb36a98 | 5720 | |
b11b0904 | 5721 | size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p); |
ab835497 | 5722 | |
a11e0df4 | 5723 | if (flag_stack_usage_info) |
b11b0904 | 5724 | current_function_static_stack_size = size; |
d3c12306 | 5725 | |
0dca9cd8 EB |
5726 | if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK) |
5727 | { | |
5728 | if (crtl->is_leaf && !cfun->calls_alloca) | |
5729 | { | |
5730 | if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT) | |
5731 | sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, | |
5732 | size - STACK_CHECK_PROTECT); | |
5733 | } | |
5734 | else if (size > 0) | |
5735 | sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size); | |
5736 | } | |
260c8ba3 | 5737 | |
b11b0904 EB |
5738 | if (size == 0) |
5739 | ; /* do nothing. */ | |
5be9b7a1 | 5740 | else if (sparc_leaf_function_p) |
ab835497 | 5741 | { |
605354f3 EB |
5742 | rtx size_int_rtx = GEN_INT (-size); |
5743 | ||
b11b0904 | 5744 | if (size <= 4096) |
605354f3 | 5745 | insn = emit_insn (gen_stack_pointer_inc (size_int_rtx)); |
b11b0904 | 5746 | else if (size <= 8192) |
915f619f | 5747 | { |
e54c7471 | 5748 | insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096))); |
e54c7471 | 5749 | RTX_FRAME_RELATED_P (insn) = 1; |
e98b1def EB |
5750 | |
5751 | /* %sp is still the CFA register. */ | |
b11b0904 | 5752 | insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size))); |
915f619f JW |
5753 | } |
5754 | else | |
5755 | { | |
605354f3 EB |
5756 | rtx size_rtx = gen_rtx_REG (Pmode, 1); |
5757 | emit_move_insn (size_rtx, size_int_rtx); | |
5758 | insn = emit_insn (gen_stack_pointer_inc (size_rtx)); | |
bbbbb16a | 5759 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
605354f3 | 5760 | gen_stack_pointer_inc (size_int_rtx)); |
915f619f | 5761 | } |
e54c7471 EB |
5762 | |
5763 | RTX_FRAME_RELATED_P (insn) = 1; | |
ab835497 | 5764 | } |
9ac617d4 | 5765 | else |
5f4241d5 | 5766 | { |
605354f3 EB |
5767 | rtx size_int_rtx = GEN_INT (-size); |
5768 | ||
b11b0904 | 5769 | if (size <= 4096) |
18970372 | 5770 | emit_window_save (size_int_rtx); |
b11b0904 | 5771 | else if (size <= 8192) |
3592ea0d | 5772 | { |
18970372 | 5773 | emit_window_save (GEN_INT (-4096)); |
e98b1def | 5774 | |
e54c7471 | 5775 | /* %sp is not the CFA register anymore. */ |
b11b0904 | 5776 | emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size))); |
e98b1def EB |
5777 | |
5778 | /* Make sure no %fp-based store is issued until after the frame is | |
5779 | established. The offset between the frame pointer and the stack | |
5780 | pointer is calculated relative to the value of the stack pointer | |
5781 | at the end of the function prologue, and moving instructions that | |
5782 | access the stack via the frame pointer between the instructions | |
5783 | that decrement the stack pointer could result in accessing the | |
5784 | register window save area, which is volatile. */ | |
5785 | emit_insn (gen_frame_blockage ()); | |
3592ea0d | 5786 | } |
915f619f | 5787 | else |
3592ea0d | 5788 | { |
605354f3 EB |
5789 | rtx size_rtx = gen_rtx_REG (Pmode, 1); |
5790 | emit_move_insn (size_rtx, size_int_rtx); | |
18970372 | 5791 | emit_window_save (size_rtx); |
3592ea0d | 5792 | } |
ab835497 RK |
5793 | } |
5794 | ||
b11b0904 EB |
5795 | if (sparc_leaf_function_p) |
5796 | { | |
5797 | sparc_frame_base_reg = stack_pointer_rtx; | |
5798 | sparc_frame_base_offset = size + SPARC_STACK_BIAS; | |
5799 | } | |
5800 | else | |
5801 | { | |
5802 | sparc_frame_base_reg = hard_frame_pointer_rtx; | |
5803 | sparc_frame_base_offset = SPARC_STACK_BIAS; | |
5804 | } | |
5805 | ||
5806 | if (sparc_n_global_fp_regs > 0) | |
5807 | emit_save_or_restore_global_fp_regs (sparc_frame_base_reg, | |
5808 | sparc_frame_base_offset | |
5809 | - sparc_apparent_frame_size, | |
5810 | SORR_SAVE); | |
9ac617d4 | 5811 | |
a6fed83f EB |
5812 | /* Load the GOT register if needed. */ |
5813 | if (crtl->uses_pic_offset_table) | |
5814 | load_got_register (); | |
b11b0904 EB |
5815 | |
5816 | /* Advertise that the data calculated just above are now valid. */ | |
5817 | sparc_prologue_data_valid_p = true; | |
5818 | } | |
5819 | ||
5820 | /* Expand the function prologue. The prologue is responsible for reserving | |
5821 | storage for the frame, saving the call-saved registers and loading the | |
5822 | GOT register if needed. */ | |
5823 | ||
5824 | void | |
5825 | sparc_flat_expand_prologue (void) | |
5826 | { | |
5827 | HOST_WIDE_INT size; | |
e1faf324 | 5828 | rtx_insn *insn; |
b11b0904 | 5829 | |
416ff32e | 5830 | sparc_leaf_function_p = optimize > 0 && crtl->is_leaf; |
b11b0904 EB |
5831 | |
5832 | size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p); | |
5833 | ||
5834 | if (flag_stack_usage_info) | |
5835 | current_function_static_stack_size = size; | |
5836 | ||
0dca9cd8 EB |
5837 | if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK) |
5838 | { | |
5839 | if (crtl->is_leaf && !cfun->calls_alloca) | |
5840 | { | |
5841 | if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT) | |
5842 | sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, | |
5843 | size - STACK_CHECK_PROTECT); | |
5844 | } | |
5845 | else if (size > 0) | |
5846 | sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size); | |
5847 | } | |
b11b0904 EB |
5848 | |
5849 | if (sparc_save_local_in_regs_p) | |
5850 | emit_save_or_restore_local_in_regs (stack_pointer_rtx, SPARC_STACK_BIAS, | |
5851 | SORR_SAVE); | |
5852 | ||
5853 | if (size == 0) | |
5854 | ; /* do nothing. */ | |
a7289eaf | 5855 | else |
b11b0904 | 5856 | { |
a7289eaf RH |
5857 | rtx size_int_rtx, size_rtx; |
5858 | ||
5859 | size_rtx = size_int_rtx = GEN_INT (-size); | |
b11b0904 | 5860 | |
605354f3 EB |
5861 | /* We establish the frame (i.e. decrement the stack pointer) first, even |
5862 | if we use a frame pointer, because we cannot clobber any call-saved | |
5863 | registers, including the frame pointer, if we haven't created a new | |
5864 | register save area, for the sake of compatibility with the ABI. */ | |
b11b0904 | 5865 | if (size <= 4096) |
a7289eaf RH |
5866 | insn = emit_insn (gen_stack_pointer_inc (size_int_rtx)); |
5867 | else if (size <= 8192 && !frame_pointer_needed) | |
b11b0904 | 5868 | { |
a7289eaf | 5869 | insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096))); |
b11b0904 | 5870 | RTX_FRAME_RELATED_P (insn) = 1; |
a7289eaf | 5871 | insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size))); |
b11b0904 EB |
5872 | } |
5873 | else | |
5874 | { | |
a7289eaf RH |
5875 | size_rtx = gen_rtx_REG (Pmode, 1); |
5876 | emit_move_insn (size_rtx, size_int_rtx); | |
5877 | insn = emit_insn (gen_stack_pointer_inc (size_rtx)); | |
5878 | add_reg_note (insn, REG_CFA_ADJUST_CFA, | |
5879 | gen_stack_pointer_inc (size_int_rtx)); | |
b11b0904 | 5880 | } |
a7289eaf RH |
5881 | RTX_FRAME_RELATED_P (insn) = 1; |
5882 | ||
605354f3 EB |
5883 | /* Ensure nothing is scheduled until after the frame is established. */ |
5884 | emit_insn (gen_blockage ()); | |
5885 | ||
a7289eaf | 5886 | if (frame_pointer_needed) |
b11b0904 | 5887 | { |
f7df4a84 | 5888 | insn = emit_insn (gen_rtx_SET (hard_frame_pointer_rtx, |
a7289eaf RH |
5889 | gen_rtx_MINUS (Pmode, |
5890 | stack_pointer_rtx, | |
5891 | size_rtx))); | |
b11b0904 | 5892 | RTX_FRAME_RELATED_P (insn) = 1; |
a7289eaf RH |
5893 | |
5894 | add_reg_note (insn, REG_CFA_ADJUST_CFA, | |
f7df4a84 | 5895 | gen_rtx_SET (hard_frame_pointer_rtx, |
0a81f074 | 5896 | plus_constant (Pmode, stack_pointer_rtx, |
a7289eaf | 5897 | size))); |
b11b0904 | 5898 | } |
a7289eaf RH |
5899 | |
5900 | if (return_addr_reg_needed_p (sparc_leaf_function_p)) | |
b11b0904 | 5901 | { |
605354f3 EB |
5902 | rtx o7 = gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM); |
5903 | rtx i7 = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); | |
b11b0904 | 5904 | |
605354f3 | 5905 | insn = emit_move_insn (i7, o7); |
a7289eaf | 5906 | RTX_FRAME_RELATED_P (insn) = 1; |
b11b0904 | 5907 | |
f7df4a84 | 5908 | add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (i7, o7)); |
a7289eaf RH |
5909 | |
5910 | /* Prevent this instruction from ever being considered dead, | |
5911 | even if this function has no epilogue. */ | |
8c92f3e8 | 5912 | emit_use (i7); |
a7289eaf RH |
5913 | } |
5914 | } | |
b11b0904 EB |
5915 | |
5916 | if (frame_pointer_needed) | |
5917 | { | |
5918 | sparc_frame_base_reg = hard_frame_pointer_rtx; | |
5919 | sparc_frame_base_offset = SPARC_STACK_BIAS; | |
5920 | } | |
5921 | else | |
5922 | { | |
5923 | sparc_frame_base_reg = stack_pointer_rtx; | |
5924 | sparc_frame_base_offset = size + SPARC_STACK_BIAS; | |
5925 | } | |
5926 | ||
5927 | if (sparc_n_global_fp_regs > 0) | |
5928 | emit_save_or_restore_global_fp_regs (sparc_frame_base_reg, | |
5929 | sparc_frame_base_offset | |
5930 | - sparc_apparent_frame_size, | |
5931 | SORR_SAVE); | |
5932 | ||
5933 | /* Load the GOT register if needed. */ | |
5934 | if (crtl->uses_pic_offset_table) | |
5935 | load_got_register (); | |
5936 | ||
5937 | /* Advertise that the data calculated just above are now valid. */ | |
5938 | sparc_prologue_data_valid_p = true; | |
9ac617d4 | 5939 | } |
4900aa61 | 5940 | |
9ac617d4 | 5941 | /* This function generates the assembly code for function entry, which boils |
f8ece000 | 5942 | down to emitting the necessary .register directives. */ |
9ac617d4 EB |
5943 | |
5944 | static void | |
42776416 | 5945 | sparc_asm_function_prologue (FILE *file) |
9ac617d4 | 5946 | { |
5be9b7a1 | 5947 | /* Check that the assumption we made in sparc_expand_prologue is valid. */ |
b11b0904 | 5948 | if (!TARGET_FLAT) |
416ff32e | 5949 | gcc_assert (sparc_leaf_function_p == crtl->uses_only_leaf_regs); |
9ac617d4 EB |
5950 | |
5951 | sparc_output_scratch_registers (file); | |
9ac617d4 EB |
5952 | } |
5953 | ||
5954 | /* Expand the function epilogue, either normal or part of a sibcall. | |
5955 | We emit all the instructions except the return or the call. */ | |
c53aa195 | 5956 | |
9ac617d4 | 5957 | void |
b11b0904 | 5958 | sparc_expand_epilogue (bool for_eh) |
9ac617d4 | 5959 | { |
b11b0904 EB |
5960 | HOST_WIDE_INT size = sparc_frame_size; |
5961 | ||
100d0700 DM |
5962 | if (cfun->calls_alloca) |
5963 | emit_insn (gen_frame_blockage ()); | |
5964 | ||
b11b0904 EB |
5965 | if (sparc_n_global_fp_regs > 0) |
5966 | emit_save_or_restore_global_fp_regs (sparc_frame_base_reg, | |
5967 | sparc_frame_base_offset | |
5968 | - sparc_apparent_frame_size, | |
5969 | SORR_RESTORE); | |
ab835497 | 5970 | |
b11b0904 EB |
5971 | if (size == 0 || for_eh) |
5972 | ; /* do nothing. */ | |
5be9b7a1 | 5973 | else if (sparc_leaf_function_p) |
9ac617d4 | 5974 | { |
b11b0904 | 5975 | if (size <= 4096) |
b7dcf38f | 5976 | emit_insn (gen_stack_pointer_inc (GEN_INT (size))); |
b11b0904 | 5977 | else if (size <= 8192) |
61a55e8b | 5978 | { |
b7dcf38f EB |
5979 | emit_insn (gen_stack_pointer_inc (GEN_INT (4096))); |
5980 | emit_insn (gen_stack_pointer_inc (GEN_INT (size - 4096))); | |
61a55e8b | 5981 | } |
ab835497 | 5982 | else |
61a55e8b | 5983 | { |
9ac617d4 | 5984 | rtx reg = gen_rtx_REG (Pmode, 1); |
b7dcf38f EB |
5985 | emit_move_insn (reg, GEN_INT (size)); |
5986 | emit_insn (gen_stack_pointer_inc (reg)); | |
b11b0904 EB |
5987 | } |
5988 | } | |
5989 | } | |
5990 | ||
5991 | /* Expand the function epilogue, either normal or part of a sibcall. | |
5992 | We emit all the instructions except the return or the call. */ | |
5993 | ||
5994 | void | |
5995 | sparc_flat_expand_epilogue (bool for_eh) | |
5996 | { | |
5997 | HOST_WIDE_INT size = sparc_frame_size; | |
5998 | ||
5999 | if (sparc_n_global_fp_regs > 0) | |
6000 | emit_save_or_restore_global_fp_regs (sparc_frame_base_reg, | |
6001 | sparc_frame_base_offset | |
6002 | - sparc_apparent_frame_size, | |
6003 | SORR_RESTORE); | |
6004 | ||
6005 | /* If we have a frame pointer, we'll need both to restore it before the | |
6006 | frame is destroyed and use its current value in destroying the frame. | |
6007 | Since we don't have an atomic way to do that in the flat window model, | |
6008 | we save the current value into a temporary register (%g1). */ | |
6009 | if (frame_pointer_needed && !for_eh) | |
6010 | emit_move_insn (gen_rtx_REG (Pmode, 1), hard_frame_pointer_rtx); | |
6011 | ||
6012 | if (return_addr_reg_needed_p (sparc_leaf_function_p)) | |
6013 | emit_move_insn (gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM), | |
6014 | gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)); | |
6015 | ||
6016 | if (sparc_save_local_in_regs_p) | |
6017 | emit_save_or_restore_local_in_regs (sparc_frame_base_reg, | |
6018 | sparc_frame_base_offset, | |
6019 | SORR_RESTORE); | |
6020 | ||
6021 | if (size == 0 || for_eh) | |
6022 | ; /* do nothing. */ | |
6023 | else if (frame_pointer_needed) | |
6024 | { | |
6025 | /* Make sure the frame is destroyed after everything else is done. */ | |
6026 | emit_insn (gen_blockage ()); | |
6027 | ||
6028 | emit_move_insn (stack_pointer_rtx, gen_rtx_REG (Pmode, 1)); | |
6029 | } | |
6030 | else | |
6031 | { | |
6032 | /* Likewise. */ | |
6033 | emit_insn (gen_blockage ()); | |
6034 | ||
6035 | if (size <= 4096) | |
b7dcf38f | 6036 | emit_insn (gen_stack_pointer_inc (GEN_INT (size))); |
b11b0904 EB |
6037 | else if (size <= 8192) |
6038 | { | |
b7dcf38f EB |
6039 | emit_insn (gen_stack_pointer_inc (GEN_INT (4096))); |
6040 | emit_insn (gen_stack_pointer_inc (GEN_INT (size - 4096))); | |
b11b0904 EB |
6041 | } |
6042 | else | |
6043 | { | |
6044 | rtx reg = gen_rtx_REG (Pmode, 1); | |
b7dcf38f EB |
6045 | emit_move_insn (reg, GEN_INT (size)); |
6046 | emit_insn (gen_stack_pointer_inc (reg)); | |
61a55e8b | 6047 | } |
ab835497 RK |
6048 | } |
6049 | } | |
5be9b7a1 EB |
6050 | |
6051 | /* Return true if it is appropriate to emit `return' instructions in the | |
6052 | body of a function. */ | |
6053 | ||
6054 | bool | |
6055 | sparc_can_use_return_insn_p (void) | |
6056 | { | |
6057 | return sparc_prologue_data_valid_p | |
b11b0904 EB |
6058 | && sparc_n_global_fp_regs == 0 |
6059 | && TARGET_FLAT | |
6060 | ? (sparc_frame_size == 0 && !sparc_save_local_in_regs_p) | |
6061 | : (sparc_frame_size == 0 || !sparc_leaf_function_p); | |
5be9b7a1 | 6062 | } |
4900aa61 | 6063 | |
9ac617d4 | 6064 | /* This function generates the assembly code for function exit. */ |
4900aa61 | 6065 | |
9ac617d4 | 6066 | static void |
42776416 | 6067 | sparc_asm_function_epilogue (FILE *file) |
9ac617d4 | 6068 | { |
891aa2ec OH |
6069 | /* If the last two instructions of a function are "call foo; dslot;" |
6070 | the return address might point to the first instruction in the next | |
6071 | function and we have to output a dummy nop for the sake of sane | |
6072 | backtraces in such cases. This is pointless for sibling calls since | |
6073 | the return address is explicitly adjusted. */ | |
ab835497 | 6074 | |
82082f65 | 6075 | rtx_insn *insn = get_last_insn (); |
7d167afd | 6076 | |
82082f65 | 6077 | rtx last_real_insn = prev_real_insn (insn); |
9ac617d4 | 6078 | if (last_real_insn |
b64925dc | 6079 | && NONJUMP_INSN_P (last_real_insn) |
9ac617d4 EB |
6080 | && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE) |
6081 | last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0); | |
6082 | ||
891aa2ec OH |
6083 | if (last_real_insn |
6084 | && CALL_P (last_real_insn) | |
6085 | && !SIBLING_CALL_P (last_real_insn)) | |
9ac617d4 EB |
6086 | fputs("\tnop\n", file); |
6087 | ||
6088 | sparc_output_deferred_case_vectors (); | |
6089 | } | |
4900aa61 | 6090 | |
9ac617d4 | 6091 | /* Output a 'restore' instruction. */ |
4900aa61 | 6092 | |
7d167afd | 6093 | static void |
6244b14e | 6094 | output_restore (rtx pat) |
7d167afd | 6095 | { |
6244b14e | 6096 | rtx operands[3]; |
7d167afd | 6097 | |
6244b14e | 6098 | if (! pat) |
7d167afd | 6099 | { |
9ac617d4 EB |
6100 | fputs ("\t restore\n", asm_out_file); |
6101 | return; | |
7d167afd JJ |
6102 | } |
6103 | ||
f5f7d171 | 6104 | gcc_assert (GET_CODE (pat) == SET); |
08c148a8 | 6105 | |
9ac617d4 EB |
6106 | operands[0] = SET_DEST (pat); |
6107 | pat = SET_SRC (pat); | |
08c148a8 | 6108 | |
9ac617d4 EB |
6109 | switch (GET_CODE (pat)) |
6110 | { | |
6111 | case PLUS: | |
6112 | operands[1] = XEXP (pat, 0); | |
6113 | operands[2] = XEXP (pat, 1); | |
6114 | output_asm_insn (" restore %r1, %2, %Y0", operands); | |
6115 | break; | |
6116 | case LO_SUM: | |
6117 | operands[1] = XEXP (pat, 0); | |
6118 | operands[2] = XEXP (pat, 1); | |
6119 | output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); | |
6120 | break; | |
6121 | case ASHIFT: | |
6122 | operands[1] = XEXP (pat, 0); | |
f5f7d171 | 6123 | gcc_assert (XEXP (pat, 1) == const1_rtx); |
9ac617d4 EB |
6124 | output_asm_insn (" restore %r1, %r1, %Y0", operands); |
6125 | break; | |
6126 | default: | |
6127 | operands[1] = pat; | |
6128 | output_asm_insn (" restore %%g0, %1, %Y0", operands); | |
6129 | break; | |
6130 | } | |
08c148a8 | 6131 | } |
4900aa61 | 6132 | |
9ac617d4 | 6133 | /* Output a return. */ |
08c148a8 | 6134 | |
9ac617d4 | 6135 | const char * |
e1faf324 | 6136 | output_return (rtx_insn *insn) |
ab835497 | 6137 | { |
b11b0904 EB |
6138 | if (crtl->calls_eh_return) |
6139 | { | |
6140 | /* If the function uses __builtin_eh_return, the eh_return | |
6141 | machinery occupies the delay slot. */ | |
6142 | gcc_assert (!final_sequence); | |
6143 | ||
6144 | if (flag_delayed_branch) | |
6145 | { | |
6146 | if (!TARGET_FLAT && TARGET_V9) | |
6147 | fputs ("\treturn\t%i7+8\n", asm_out_file); | |
6148 | else | |
6149 | { | |
6150 | if (!TARGET_FLAT) | |
6151 | fputs ("\trestore\n", asm_out_file); | |
6152 | ||
6153 | fputs ("\tjmp\t%o7+8\n", asm_out_file); | |
6154 | } | |
6155 | ||
6156 | fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file); | |
6157 | } | |
6158 | else | |
6159 | { | |
6160 | if (!TARGET_FLAT) | |
6161 | fputs ("\trestore\n", asm_out_file); | |
6162 | ||
6163 | fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file); | |
6164 | fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file); | |
6165 | } | |
6166 | } | |
6167 | else if (sparc_leaf_function_p || TARGET_FLAT) | |
e48addee | 6168 | { |
b11b0904 EB |
6169 | /* This is a leaf or flat function so we don't have to bother restoring |
6170 | the register window, which frees us from dealing with the convoluted | |
9ac617d4 | 6171 | semantics of restore/return. We simply output the jump to the |
4e5b002b | 6172 | return address and the insn in the delay slot (if any). */ |
7a31a340 | 6173 | |
4e5b002b | 6174 | return "jmp\t%%o7+%)%#"; |
bfd6bc60 | 6175 | } |
ab835497 | 6176 | else |
ab835497 | 6177 | { |
9ac617d4 EB |
6178 | /* This is a regular function so we have to restore the register window. |
6179 | We may have a pending insn for the delay slot, which will be either | |
6180 | combined with the 'restore' instruction or put in the delay slot of | |
6181 | the 'return' instruction. */ | |
6182 | ||
b11b0904 | 6183 | if (final_sequence) |
ef8200df | 6184 | { |
9ac617d4 EB |
6185 | rtx delay, pat; |
6186 | ||
6187 | delay = NEXT_INSN (insn); | |
f5f7d171 | 6188 | gcc_assert (delay); |
1150a841 | 6189 | |
9ac617d4 EB |
6190 | pat = PATTERN (delay); |
6191 | ||
6192 | if (TARGET_V9 && ! epilogue_renumber (&pat, 1)) | |
33074e5f | 6193 | { |
9ac617d4 | 6194 | epilogue_renumber (&pat, 0); |
4e5b002b | 6195 | return "return\t%%i7+%)%#"; |
1150a841 | 6196 | } |
33074e5f | 6197 | else |
ab835497 | 6198 | { |
4e5b002b | 6199 | output_asm_insn ("jmp\t%%i7+%)", NULL); |
6244b14e | 6200 | output_restore (pat); |
4e5b002b EB |
6201 | PATTERN (delay) = gen_blockage (); |
6202 | INSN_CODE (delay) = -1; | |
ab835497 | 6203 | } |
ef8200df | 6204 | } |
33074e5f | 6205 | else |
9ac617d4 EB |
6206 | { |
6207 | /* The delay slot is empty. */ | |
6208 | if (TARGET_V9) | |
4e5b002b | 6209 | return "return\t%%i7+%)\n\t nop"; |
951661a1 | 6210 | else if (flag_delayed_branch) |
4e5b002b | 6211 | return "jmp\t%%i7+%)\n\t restore"; |
951661a1 | 6212 | else |
4e5b002b | 6213 | return "restore\n\tjmp\t%%o7+%)\n\t nop"; |
9ac617d4 | 6214 | } |
6a151f87 | 6215 | } |
e0d80184 | 6216 | |
9ac617d4 | 6217 | return ""; |
ab835497 | 6218 | } |
7d167afd JJ |
6219 | |
6220 | /* Output a sibling call. */ | |
6221 | ||
6222 | const char * | |
e1faf324 | 6223 | output_sibcall (rtx_insn *insn, rtx call_operand) |
7d167afd | 6224 | { |
9ac617d4 | 6225 | rtx operands[1]; |
7d167afd | 6226 | |
f5f7d171 | 6227 | gcc_assert (flag_delayed_branch); |
951661a1 | 6228 | |
7d167afd JJ |
6229 | operands[0] = call_operand; |
6230 | ||
b11b0904 | 6231 | if (sparc_leaf_function_p || TARGET_FLAT) |
7d167afd | 6232 | { |
b11b0904 EB |
6233 | /* This is a leaf or flat function so we don't have to bother restoring |
6234 | the register window. We simply output the jump to the function and | |
9ac617d4 | 6235 | the insn in the delay slot (if any). */ |
7d167afd | 6236 | |
f5f7d171 | 6237 | gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence)); |
9ac617d4 | 6238 | |
4e5b002b EB |
6239 | if (final_sequence) |
6240 | output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#", | |
6241 | operands); | |
7d167afd | 6242 | else |
4e5b002b EB |
6243 | /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize |
6244 | it into branch if possible. */ | |
6245 | output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7", | |
6246 | operands); | |
7d167afd | 6247 | } |
9ac617d4 | 6248 | else |
7d167afd | 6249 | { |
9ac617d4 EB |
6250 | /* This is a regular function so we have to restore the register window. |
6251 | We may have a pending insn for the delay slot, which will be combined | |
6252 | with the 'restore' instruction. */ | |
7d167afd | 6253 | |
9ac617d4 | 6254 | output_asm_insn ("call\t%a0, 0", operands); |
7d167afd | 6255 | |
4e5b002b | 6256 | if (final_sequence) |
7d167afd | 6257 | { |
e1faf324 | 6258 | rtx_insn *delay = NEXT_INSN (insn); |
f5f7d171 | 6259 | gcc_assert (delay); |
9ac617d4 | 6260 | |
6244b14e | 6261 | output_restore (PATTERN (delay)); |
9ac617d4 EB |
6262 | |
6263 | PATTERN (delay) = gen_blockage (); | |
6264 | INSN_CODE (delay) = -1; | |
7d167afd | 6265 | } |
9ac617d4 | 6266 | else |
6244b14e | 6267 | output_restore (NULL_RTX); |
7d167afd | 6268 | } |
9ac617d4 | 6269 | |
7d167afd JJ |
6270 | return ""; |
6271 | } | |
4fb4e4b8 DE |
6272 | \f |
6273 | /* Functions for handling argument passing. | |
6274 | ||
1b5963f7 | 6275 | For 32-bit, the first 6 args are normally in registers and the rest are |
4fb4e4b8 DE |
6276 | pushed. Any arg that starts within the first 6 words is at least |
6277 | partially passed in a register unless its data type forbids. | |
6278 | ||
1b5963f7 | 6279 | For 64-bit, the argument registers are laid out as an array of 16 elements |
4fb4e4b8 DE |
6280 | and arguments are added sequentially. The first 6 int args and up to the |
6281 | first 16 fp args (depending on size) are passed in regs. | |
6282 | ||
6283 | Slot Stack Integral Float Float in structure Double Long Double | |
6284 | ---- ----- -------- ----- ------------------ ------ ----------- | |
6285 | 15 [SP+248] %f31 %f30,%f31 %d30 | |
6286 | 14 [SP+240] %f29 %f28,%f29 %d28 %q28 | |
6287 | 13 [SP+232] %f27 %f26,%f27 %d26 | |
6288 | 12 [SP+224] %f25 %f24,%f25 %d24 %q24 | |
6289 | 11 [SP+216] %f23 %f22,%f23 %d22 | |
6290 | 10 [SP+208] %f21 %f20,%f21 %d20 %q20 | |
6291 | 9 [SP+200] %f19 %f18,%f19 %d18 | |
6292 | 8 [SP+192] %f17 %f16,%f17 %d16 %q16 | |
6293 | 7 [SP+184] %f15 %f14,%f15 %d14 | |
6294 | 6 [SP+176] %f13 %f12,%f13 %d12 %q12 | |
6295 | 5 [SP+168] %o5 %f11 %f10,%f11 %d10 | |
6296 | 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 | |
6297 | 3 [SP+152] %o3 %f7 %f6,%f7 %d6 | |
6298 | 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 | |
6299 | 1 [SP+136] %o1 %f3 %f2,%f3 %d2 | |
6300 | 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 | |
6301 | ||
6302 | Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. | |
6303 | ||
1b5963f7 | 6304 | Integral arguments are always passed as 64-bit quantities appropriately |
4fb4e4b8 DE |
6305 | extended. |
6306 | ||
6307 | Passing of floating point values is handled as follows. | |
6308 | If a prototype is in scope: | |
6309 | If the value is in a named argument (i.e. not a stdarg function or a | |
6310 | value not part of the `...') then the value is passed in the appropriate | |
6311 | fp reg. | |
6312 | If the value is part of the `...' and is passed in one of the first 6 | |
6313 | slots then the value is passed in the appropriate int reg. | |
6314 | If the value is part of the `...' and is not passed in one of the first 6 | |
6315 | slots then the value is passed in memory. | |
6316 | If a prototype is not in scope: | |
6317 | If the value is one of the first 6 arguments the value is passed in the | |
6318 | appropriate integer reg and the appropriate fp reg. | |
6319 | If the value is not one of the first 6 arguments the value is passed in | |
6320 | the appropriate fp reg and in memory. | |
1b5963f7 EB |
6321 | |
6322 | ||
4900aa61 | 6323 | Summary of the calling conventions implemented by GCC on the SPARC: |
1b5963f7 EB |
6324 | |
6325 | 32-bit ABI: | |
6326 | size argument return value | |
6327 | ||
6328 | small integer <4 int. reg. int. reg. | |
6329 | word 4 int. reg. int. reg. | |
6330 | double word 8 int. reg. int. reg. | |
6331 | ||
6332 | _Complex small integer <8 int. reg. int. reg. | |
6333 | _Complex word 8 int. reg. int. reg. | |
6334 | _Complex double word 16 memory int. reg. | |
6335 | ||
6336 | vector integer <=8 int. reg. FP reg. | |
6337 | vector integer >8 memory memory | |
6338 | ||
6339 | float 4 int. reg. FP reg. | |
6340 | double 8 int. reg. FP reg. | |
6341 | long double 16 memory memory | |
6342 | ||
6343 | _Complex float 8 memory FP reg. | |
6344 | _Complex double 16 memory FP reg. | |
6345 | _Complex long double 32 memory FP reg. | |
6346 | ||
45261626 | 6347 | vector float any memory memory |
1b5963f7 EB |
6348 | |
6349 | aggregate any memory memory | |
6350 | ||
6351 | ||
6352 | ||
6353 | 64-bit ABI: | |
6354 | size argument return value | |
6355 | ||
6356 | small integer <8 int. reg. int. reg. | |
6357 | word 8 int. reg. int. reg. | |
6358 | double word 16 int. reg. int. reg. | |
6359 | ||
6360 | _Complex small integer <16 int. reg. int. reg. | |
6361 | _Complex word 16 int. reg. int. reg. | |
6362 | _Complex double word 32 memory int. reg. | |
6363 | ||
6364 | vector integer <=16 FP reg. FP reg. | |
6365 | vector integer 16<s<=32 memory FP reg. | |
6366 | vector integer >32 memory memory | |
6367 | ||
6368 | float 4 FP reg. FP reg. | |
6369 | double 8 FP reg. FP reg. | |
6370 | long double 16 FP reg. FP reg. | |
6371 | ||
6372 | _Complex float 8 FP reg. FP reg. | |
6373 | _Complex double 16 FP reg. FP reg. | |
6374 | _Complex long double 32 memory FP reg. | |
6375 | ||
6376 | vector float <=16 FP reg. FP reg. | |
6377 | vector float 16<s<=32 memory FP reg. | |
6378 | vector float >32 memory memory | |
6379 | ||
6380 | aggregate <=16 reg. reg. | |
6381 | aggregate 16<s<=32 memory reg. | |
6382 | aggregate >32 memory memory | |
6383 | ||
6384 | ||
6385 | ||
6386 | Note #1: complex floating-point types follow the extended SPARC ABIs as | |
6387 | implemented by the Sun compiler. | |
6388 | ||
6389 | Note #2: integral vector types follow the scalar floating-point types | |
6390 | conventions to match what is implemented by the Sun VIS SDK. | |
6391 | ||
4900aa61 | 6392 | Note #3: floating-point vector types follow the aggregate types |
45261626 | 6393 | conventions. */ |
1b5963f7 | 6394 | |
4fb4e4b8 DE |
6395 | |
6396 | /* Maximum number of int regs for args. */ | |
6397 | #define SPARC_INT_ARG_MAX 6 | |
6398 | /* Maximum number of fp regs for args. */ | |
6399 | #define SPARC_FP_ARG_MAX 16 | |
84ea0f58 | 6400 | /* Number of words (partially) occupied for a given size in units. */ |
f3c7a945 | 6401 | #define CEIL_NWORDS(SIZE) CEIL((SIZE), UNITS_PER_WORD) |
4fb4e4b8 DE |
6402 | |
6403 | /* Handle the INIT_CUMULATIVE_ARGS macro. | |
6404 | Initialize a variable CUM of type CUMULATIVE_ARGS | |
6405 | for a call to a function whose data type is FNTYPE. | |
6406 | For a library call, FNTYPE is 0. */ | |
3ea1fdd3 | 6407 | |
4fb4e4b8 | 6408 | void |
84ea0f58 | 6409 | init_cumulative_args (struct sparc_args *cum, tree fntype, rtx, tree) |
4fb4e4b8 DE |
6410 | { |
6411 | cum->words = 0; | |
f4da8dce | 6412 | cum->prototype_p = fntype && prototype_p (fntype); |
84ea0f58 | 6413 | cum->libcall_p = !fntype; |
4fb4e4b8 | 6414 | } |
61a55e8b | 6415 | |
cde0f3fd PB |
6416 | /* Handle promotion of pointer and integer arguments. */ |
6417 | ||
ef4bddc2 | 6418 | static machine_mode |
84ea0f58 EB |
6419 | sparc_promote_function_mode (const_tree type, machine_mode mode, |
6420 | int *punsignedp, const_tree, int) | |
cde0f3fd | 6421 | { |
84ea0f58 | 6422 | if (type && POINTER_TYPE_P (type)) |
cde0f3fd PB |
6423 | { |
6424 | *punsignedp = POINTERS_EXTEND_UNSIGNED; | |
6425 | return Pmode; | |
6426 | } | |
6427 | ||
f79e1b0f EB |
6428 | /* Integral arguments are passed as full words, as per the ABI. */ |
6429 | if (GET_MODE_CLASS (mode) == MODE_INT | |
cde0f3fd PB |
6430 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD) |
6431 | return word_mode; | |
6432 | ||
6433 | return mode; | |
6434 | } | |
6435 | ||
bd5bd7ac | 6436 | /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */ |
3e2cc1d1 KH |
6437 | |
6438 | static bool | |
d5cc9181 | 6439 | sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) |
3e2cc1d1 | 6440 | { |
1b5963f7 | 6441 | return TARGET_ARCH64 ? true : false; |
3e2cc1d1 KH |
6442 | } |
6443 | ||
84ea0f58 EB |
6444 | /* Traverse the record TYPE recursively and call FUNC on its fields. |
6445 | NAMED is true if this is for a named parameter. DATA is passed | |
6446 | to FUNC for each field. OFFSET is the starting position and | |
6447 | PACKED is true if we are inside a packed record. */ | |
5c4f4b18 | 6448 | |
84ea0f58 | 6449 | template <typename T, void Func (const_tree, HOST_WIDE_INT, bool, T*)> |
5c4f4b18 | 6450 | static void |
84ea0f58 EB |
6451 | traverse_record_type (const_tree type, bool named, T *data, |
6452 | HOST_WIDE_INT offset = 0, bool packed = false) | |
5c4f4b18 | 6453 | { |
84ea0f58 EB |
6454 | /* The ABI obviously doesn't specify how packed structures are passed. |
6455 | These are passed in integer regs if possible, otherwise memory. */ | |
6456 | if (!packed) | |
6457 | for (tree field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) | |
6458 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
5c4f4b18 | 6459 | { |
84ea0f58 EB |
6460 | packed = true; |
6461 | break; | |
5c4f4b18 | 6462 | } |
84ea0f58 EB |
6463 | |
6464 | /* Walk the real fields, but skip those with no size or a zero size. | |
6465 | ??? Fields with variable offset are handled as having zero offset. */ | |
6466 | for (tree field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) | |
6467 | if (TREE_CODE (field) == FIELD_DECL) | |
6468 | { | |
6469 | if (!DECL_SIZE (field) || integer_zerop (DECL_SIZE (field))) | |
6470 | continue; | |
6471 | ||
6472 | HOST_WIDE_INT bitpos = offset; | |
6473 | if (TREE_CODE (DECL_FIELD_OFFSET (field)) == INTEGER_CST) | |
6474 | bitpos += int_bit_position (field); | |
6475 | ||
6476 | tree field_type = TREE_TYPE (field); | |
6477 | if (TREE_CODE (field_type) == RECORD_TYPE) | |
6478 | traverse_record_type<T, Func> (field_type, named, data, bitpos, | |
6479 | packed); | |
6480 | else | |
6481 | { | |
6482 | const bool fp_type | |
6483 | = FLOAT_TYPE_P (field_type) || VECTOR_TYPE_P (field_type); | |
6484 | Func (field, bitpos, fp_type && named && !packed && TARGET_FPU, | |
6485 | data); | |
6486 | } | |
6487 | } | |
6488 | } | |
6489 | ||
6490 | /* Handle recursive register classifying for structure layout. */ | |
6491 | ||
6492 | typedef struct | |
6493 | { | |
84ea0f58 EB |
6494 | bool fp_regs; /* true if field eligible to FP registers. */ |
6495 | bool fp_regs_in_first_word; /* true if such field in first word. */ | |
6496 | } classify_data_t; | |
6497 | ||
6498 | /* A subroutine of function_arg_slotno. Classify the field. */ | |
6499 | ||
6500 | inline void | |
6501 | classify_registers (const_tree, HOST_WIDE_INT bitpos, bool fp, | |
6502 | classify_data_t *data) | |
6503 | { | |
6504 | if (fp) | |
6505 | { | |
6506 | data->fp_regs = true; | |
6507 | if (bitpos < BITS_PER_WORD) | |
6508 | data->fp_regs_in_first_word = true; | |
5c4f4b18 EB |
6509 | } |
6510 | } | |
6511 | ||
4fb4e4b8 | 6512 | /* Compute the slot number to pass an argument in. |
5c4f4b18 | 6513 | Return the slot number or -1 if passing on the stack. |
4fb4e4b8 DE |
6514 | |
6515 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
6516 | the preceding args and about the function being called. | |
6517 | MODE is the argument's machine mode. | |
6518 | TYPE is the data type of the argument (as a tree). | |
6519 | This is null for libcalls where that information may | |
6520 | not be available. | |
6521 | NAMED is nonzero if this argument is a named parameter | |
6522 | (otherwise it is an extra parameter matching an ellipsis). | |
84ea0f58 | 6523 | INCOMING is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. |
4fb4e4b8 DE |
6524 | *PREGNO records the register number to use if scalar type. |
6525 | *PPADDING records the amount of padding needed in words. */ | |
6526 | ||
6527 | static int | |
ef4bddc2 | 6528 | function_arg_slotno (const struct sparc_args *cum, machine_mode mode, |
84ea0f58 | 6529 | const_tree type, bool named, bool incoming, |
fc27d102 | 6530 | int *pregno, int *ppadding) |
4fb4e4b8 | 6531 | { |
84ea0f58 | 6532 | int regbase = (incoming |
4fb4e4b8 DE |
6533 | ? SPARC_INCOMING_INT_ARG_FIRST |
6534 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
6535 | int slotno = cum->words; | |
45261626 | 6536 | enum mode_class mclass; |
4fb4e4b8 DE |
6537 | int regno; |
6538 | ||
6539 | *ppadding = 0; | |
6540 | ||
1b5963f7 | 6541 | if (type && TREE_ADDRESSABLE (type)) |
4fb4e4b8 | 6542 | return -1; |
1b5963f7 | 6543 | |
4fb4e4b8 | 6544 | if (TARGET_ARCH32 |
1b5963f7 EB |
6545 | && mode == BLKmode |
6546 | && type | |
4fb4e4b8 DE |
6547 | && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) |
6548 | return -1; | |
6549 | ||
1b5963f7 EB |
6550 | /* For SPARC64, objects requiring 16-byte alignment get it. */ |
6551 | if (TARGET_ARCH64 | |
7617ec02 | 6552 | && (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128 |
1b5963f7 EB |
6553 | && (slotno & 1) != 0) |
6554 | slotno++, *ppadding = 1; | |
4fb4e4b8 | 6555 | |
45261626 EB |
6556 | mclass = GET_MODE_CLASS (mode); |
6557 | if (type && TREE_CODE (type) == VECTOR_TYPE) | |
6558 | { | |
6559 | /* Vector types deserve special treatment because they are | |
6560 | polymorphic wrt their mode, depending upon whether VIS | |
6561 | instructions are enabled. */ | |
6562 | if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE) | |
6563 | { | |
6564 | /* The SPARC port defines no floating-point vector modes. */ | |
f5f7d171 | 6565 | gcc_assert (mode == BLKmode); |
45261626 EB |
6566 | } |
6567 | else | |
6568 | { | |
6569 | /* Integral vector types should either have a vector | |
6570 | mode or an integral mode, because we are guaranteed | |
6571 | by pass_by_reference that their size is not greater | |
6572 | than 16 bytes and TImode is 16-byte wide. */ | |
f5f7d171 | 6573 | gcc_assert (mode != BLKmode); |
45261626 EB |
6574 | |
6575 | /* Vector integers are handled like floats according to | |
6576 | the Sun VIS SDK. */ | |
6577 | mclass = MODE_FLOAT; | |
6578 | } | |
6579 | } | |
6580 | ||
6581 | switch (mclass) | |
1b5963f7 EB |
6582 | { |
6583 | case MODE_FLOAT: | |
6584 | case MODE_COMPLEX_FLOAT: | |
0dd8c9bc | 6585 | case MODE_VECTOR_INT: |
1b5963f7 EB |
6586 | if (TARGET_ARCH64 && TARGET_FPU && named) |
6587 | { | |
84ea0f58 | 6588 | /* If all arg slots are filled, then must pass on stack. */ |
1b5963f7 EB |
6589 | if (slotno >= SPARC_FP_ARG_MAX) |
6590 | return -1; | |
84ea0f58 | 6591 | |
1b5963f7 EB |
6592 | regno = SPARC_FP_ARG_FIRST + slotno * 2; |
6593 | /* Arguments filling only one single FP register are | |
6594 | right-justified in the outer double FP register. */ | |
6595 | if (GET_MODE_SIZE (mode) <= 4) | |
6596 | regno++; | |
6597 | break; | |
6598 | } | |
d560b0aa EB |
6599 | /* fallthrough */ |
6600 | ||
1b5963f7 EB |
6601 | case MODE_INT: |
6602 | case MODE_COMPLEX_INT: | |
84ea0f58 | 6603 | /* If all arg slots are filled, then must pass on stack. */ |
4fb4e4b8 DE |
6604 | if (slotno >= SPARC_INT_ARG_MAX) |
6605 | return -1; | |
84ea0f58 | 6606 | |
4fb4e4b8 DE |
6607 | regno = regbase + slotno; |
6608 | break; | |
6609 | ||
1b5963f7 EB |
6610 | case MODE_RANDOM: |
6611 | if (mode == VOIDmode) | |
6612 | /* MODE is VOIDmode when generating the actual call. */ | |
6613 | return -1; | |
d560b0aa | 6614 | |
f5f7d171 | 6615 | gcc_assert (mode == BLKmode); |
4fb4e4b8 | 6616 | |
ef6843ed EB |
6617 | if (TARGET_ARCH32 |
6618 | || !type | |
84ea0f58 EB |
6619 | || (TREE_CODE (type) != RECORD_TYPE |
6620 | && TREE_CODE (type) != VECTOR_TYPE)) | |
4fb4e4b8 | 6621 | { |
84ea0f58 | 6622 | /* If all arg slots are filled, then must pass on stack. */ |
4fb4e4b8 DE |
6623 | if (slotno >= SPARC_INT_ARG_MAX) |
6624 | return -1; | |
84ea0f58 | 6625 | |
4fb4e4b8 DE |
6626 | regno = regbase + slotno; |
6627 | } | |
45261626 | 6628 | else /* TARGET_ARCH64 && type */ |
4fb4e4b8 | 6629 | { |
4fb4e4b8 | 6630 | /* If all arg slots are filled, then must pass on stack. */ |
84ea0f58 | 6631 | if (slotno >= SPARC_FP_ARG_MAX) |
4fb4e4b8 | 6632 | return -1; |
1b5963f7 | 6633 | |
84ea0f58 EB |
6634 | if (TREE_CODE (type) == RECORD_TYPE) |
6635 | { | |
139dc3c6 | 6636 | classify_data_t data = { false, false }; |
84ea0f58 EB |
6637 | traverse_record_type<classify_data_t, classify_registers> |
6638 | (type, named, &data); | |
6639 | ||
139dc3c6 JC |
6640 | if (data.fp_regs) |
6641 | { | |
6642 | /* If all FP slots are filled except for the last one and | |
6643 | there is no FP field in the first word, then must pass | |
6644 | on stack. */ | |
6645 | if (slotno >= SPARC_FP_ARG_MAX - 1 | |
6646 | && !data.fp_regs_in_first_word) | |
6647 | return -1; | |
6648 | } | |
6649 | else | |
6650 | { | |
6651 | /* If all int slots are filled, then must pass on stack. */ | |
6652 | if (slotno >= SPARC_INT_ARG_MAX) | |
6653 | return -1; | |
6654 | } | |
84ea0f58 | 6655 | } |
1b5963f7 | 6656 | |
84ea0f58 | 6657 | /* PREGNO isn't set since both int and FP regs can be used. */ |
4fb4e4b8 DE |
6658 | return slotno; |
6659 | } | |
6660 | break; | |
6661 | ||
6662 | default : | |
f5f7d171 | 6663 | gcc_unreachable (); |
4fb4e4b8 DE |
6664 | } |
6665 | ||
6666 | *pregno = regno; | |
6667 | return slotno; | |
6668 | } | |
6669 | ||
84ea0f58 | 6670 | /* Handle recursive register counting/assigning for structure layout. */ |
82d6b402 | 6671 | |
84ea0f58 | 6672 | typedef struct |
82d6b402 | 6673 | { |
48028e21 | 6674 | int slotno; /* slot number of the argument. */ |
48028e21 | 6675 | int regbase; /* regno of the base register. */ |
1fd05073 | 6676 | int intoffset; /* offset of the first pending integer field. */ |
84ea0f58 EB |
6677 | int nregs; /* number of words passed in registers. */ |
6678 | bool stack; /* true if part of the argument is on the stack. */ | |
6679 | rtx ret; /* return expression being built. */ | |
6680 | } assign_data_t; | |
2a01c939 | 6681 | |
84ea0f58 EB |
6682 | /* A subroutine of function_arg_record_value. Compute the number of integer |
6683 | registers to be assigned between PARMS->intoffset and BITPOS. Return | |
6684 | true if at least one integer register is assigned or false otherwise. */ | |
0020b823 | 6685 | |
84ea0f58 EB |
6686 | static bool |
6687 | compute_int_layout (HOST_WIDE_INT bitpos, assign_data_t *data, int *pnregs) | |
82d6b402 | 6688 | { |
84ea0f58 EB |
6689 | if (data->intoffset < 0) |
6690 | return false; | |
82d6b402 | 6691 | |
84ea0f58 EB |
6692 | const int intoffset = data->intoffset; |
6693 | data->intoffset = -1; | |
cde85594 | 6694 | |
84ea0f58 EB |
6695 | const int this_slotno = data->slotno + intoffset / BITS_PER_WORD; |
6696 | const unsigned int startbit = ROUND_DOWN (intoffset, BITS_PER_WORD); | |
6697 | const unsigned int endbit = ROUND_UP (bitpos, BITS_PER_WORD); | |
6698 | int nregs = (endbit - startbit) / BITS_PER_WORD; | |
82d6b402 | 6699 | |
84ea0f58 | 6700 | if (nregs > 0 && nregs > SPARC_INT_ARG_MAX - this_slotno) |
82d6b402 | 6701 | { |
84ea0f58 | 6702 | nregs = SPARC_INT_ARG_MAX - this_slotno; |
75131237 | 6703 | |
84ea0f58 EB |
6704 | /* We need to pass this field (partly) on the stack. */ |
6705 | data->stack = 1; | |
6706 | } | |
bb05e341 | 6707 | |
84ea0f58 EB |
6708 | if (nregs <= 0) |
6709 | return false; | |
75131237 | 6710 | |
84ea0f58 EB |
6711 | *pnregs = nregs; |
6712 | return true; | |
6713 | } | |
82d6b402 | 6714 | |
84ea0f58 EB |
6715 | /* A subroutine of function_arg_record_value. Compute the number and the mode |
6716 | of the FP registers to be assigned for FIELD. Return true if at least one | |
6717 | FP register is assigned or false otherwise. */ | |
b2f24c85 | 6718 | |
84ea0f58 EB |
6719 | static bool |
6720 | compute_fp_layout (const_tree field, HOST_WIDE_INT bitpos, | |
6721 | assign_data_t *data, | |
6722 | int *pnregs, machine_mode *pmode) | |
6723 | { | |
6724 | const int this_slotno = data->slotno + bitpos / BITS_PER_WORD; | |
6725 | machine_mode mode = DECL_MODE (field); | |
6726 | int nregs, nslots; | |
82d6b402 | 6727 | |
84ea0f58 EB |
6728 | /* Slots are counted as words while regs are counted as having the size of |
6729 | the (inner) mode. */ | |
6730 | if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE && mode == BLKmode) | |
6731 | { | |
6732 | mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field))); | |
6733 | nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field)); | |
6734 | } | |
6735 | else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) | |
6736 | { | |
6737 | mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field))); | |
6738 | nregs = 2; | |
6739 | } | |
6740 | else | |
6741 | nregs = 1; | |
48028e21 | 6742 | |
f3c7a945 | 6743 | nslots = CEIL_NWORDS (nregs * GET_MODE_SIZE (mode)); |
82d6b402 | 6744 | |
84ea0f58 EB |
6745 | if (nslots > SPARC_FP_ARG_MAX - this_slotno) |
6746 | { | |
6747 | nslots = SPARC_FP_ARG_MAX - this_slotno; | |
6748 | nregs = (nslots * UNITS_PER_WORD) / GET_MODE_SIZE (mode); | |
6749 | ||
6750 | /* We need to pass this field (partly) on the stack. */ | |
6751 | data->stack = 1; | |
6752 | ||
6753 | if (nregs <= 0) | |
6754 | return false; | |
82d6b402 | 6755 | } |
84ea0f58 EB |
6756 | |
6757 | *pnregs = nregs; | |
6758 | *pmode = mode; | |
6759 | return true; | |
82d6b402 RH |
6760 | } |
6761 | ||
84ea0f58 EB |
6762 | /* A subroutine of function_arg_record_value. Count the number of registers |
6763 | to be assigned for FIELD and between PARMS->intoffset and BITPOS. */ | |
82d6b402 | 6764 | |
84ea0f58 EB |
6765 | inline void |
6766 | count_registers (const_tree field, HOST_WIDE_INT bitpos, bool fp, | |
6767 | assign_data_t *data) | |
82d6b402 | 6768 | { |
84ea0f58 EB |
6769 | if (fp) |
6770 | { | |
6771 | int nregs; | |
6772 | machine_mode mode; | |
82d6b402 | 6773 | |
84ea0f58 EB |
6774 | if (compute_int_layout (bitpos, data, &nregs)) |
6775 | data->nregs += nregs; | |
75131237 | 6776 | |
84ea0f58 EB |
6777 | if (compute_fp_layout (field, bitpos, data, &nregs, &mode)) |
6778 | data->nregs += nregs; | |
6779 | } | |
6780 | else | |
6781 | { | |
6782 | if (data->intoffset < 0) | |
6783 | data->intoffset = bitpos; | |
6784 | } | |
6785 | } | |
82d6b402 | 6786 | |
84ea0f58 EB |
6787 | /* A subroutine of function_arg_record_value. Assign the bits of the |
6788 | structure between PARMS->intoffset and BITPOS to integer registers. */ | |
6789 | ||
6790 | static void | |
6791 | assign_int_registers (HOST_WIDE_INT bitpos, assign_data_t *data) | |
6792 | { | |
6793 | int intoffset = data->intoffset; | |
6794 | machine_mode mode; | |
6795 | int nregs; | |
82d6b402 | 6796 | |
84ea0f58 | 6797 | if (!compute_int_layout (bitpos, data, &nregs)) |
82d6b402 RH |
6798 | return; |
6799 | ||
6800 | /* If this is the trailing part of a word, only load that much into | |
6801 | the register. Otherwise load the whole register. Note that in | |
6802 | the latter case we may pick up unwanted bits. It's not a problem | |
6803 | at the moment but may wish to revisit. */ | |
82d6b402 | 6804 | if (intoffset % BITS_PER_WORD != 0) |
f67f4dff RS |
6805 | mode = smallest_int_mode_for_size (BITS_PER_WORD |
6806 | - intoffset % BITS_PER_WORD); | |
82d6b402 RH |
6807 | else |
6808 | mode = word_mode; | |
6809 | ||
84ea0f58 EB |
6810 | const int this_slotno = data->slotno + intoffset / BITS_PER_WORD; |
6811 | unsigned int regno = data->regbase + this_slotno; | |
82d6b402 | 6812 | intoffset /= BITS_PER_UNIT; |
84ea0f58 | 6813 | |
82d6b402 RH |
6814 | do |
6815 | { | |
84ea0f58 EB |
6816 | rtx reg = gen_rtx_REG (mode, regno); |
6817 | XVECEXP (data->ret, 0, data->stack + data->nregs) | |
254110c2 | 6818 | = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); |
84ea0f58 | 6819 | data->nregs += 1; |
1fd05073 | 6820 | mode = word_mode; |
84ea0f58 EB |
6821 | regno += 1; |
6822 | intoffset = (intoffset | (UNITS_PER_WORD - 1)) + 1; | |
82d6b402 | 6823 | } |
84ea0f58 | 6824 | while (--nregs > 0); |
82d6b402 RH |
6825 | } |
6826 | ||
84ea0f58 EB |
6827 | /* A subroutine of function_arg_record_value. Assign FIELD at position |
6828 | BITPOS to FP registers. */ | |
0020b823 | 6829 | |
82d6b402 | 6830 | static void |
84ea0f58 EB |
6831 | assign_fp_registers (const_tree field, HOST_WIDE_INT bitpos, |
6832 | assign_data_t *data) | |
82d6b402 | 6833 | { |
84ea0f58 EB |
6834 | int nregs; |
6835 | machine_mode mode; | |
82d6b402 | 6836 | |
84ea0f58 EB |
6837 | if (!compute_fp_layout (field, bitpos, data, &nregs, &mode)) |
6838 | return; | |
6839 | ||
6840 | const int this_slotno = data->slotno + bitpos / BITS_PER_WORD; | |
6841 | int regno = SPARC_FP_ARG_FIRST + this_slotno * 2; | |
6842 | if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0) | |
6843 | regno++; | |
6844 | int pos = bitpos / BITS_PER_UNIT; | |
82d6b402 | 6845 | |
84ea0f58 | 6846 | do |
82d6b402 | 6847 | { |
84ea0f58 EB |
6848 | rtx reg = gen_rtx_REG (mode, regno); |
6849 | XVECEXP (data->ret, 0, data->stack + data->nregs) | |
6850 | = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos)); | |
6851 | data->nregs += 1; | |
6852 | regno += GET_MODE_SIZE (mode) / 4; | |
6853 | pos += GET_MODE_SIZE (mode); | |
6854 | } | |
6855 | while (--nregs > 0); | |
6856 | } | |
75131237 | 6857 | |
84ea0f58 EB |
6858 | /* A subroutine of function_arg_record_value. Assign FIELD and the bits of |
6859 | the structure between PARMS->intoffset and BITPOS to registers. */ | |
bb05e341 | 6860 | |
84ea0f58 EB |
6861 | inline void |
6862 | assign_registers (const_tree field, HOST_WIDE_INT bitpos, bool fp, | |
6863 | assign_data_t *data) | |
6864 | { | |
6865 | if (fp) | |
6866 | { | |
6867 | assign_int_registers (bitpos, data); | |
75131237 | 6868 | |
84ea0f58 EB |
6869 | assign_fp_registers (field, bitpos, data); |
6870 | } | |
6871 | else | |
6872 | { | |
6873 | if (data->intoffset < 0) | |
6874 | data->intoffset = bitpos; | |
82d6b402 RH |
6875 | } |
6876 | } | |
6877 | ||
bf44d792 | 6878 | /* Used by function_arg and sparc_function_value_1 to implement the complex |
48028e21 | 6879 | conventions of the 64-bit ABI for passing and returning structures. |
bf44d792 AS |
6880 | Return an expression valid as a return value for the FUNCTION_ARG |
6881 | and TARGET_FUNCTION_VALUE. | |
0020b823 | 6882 | |
48028e21 EB |
6883 | TYPE is the data type of the argument (as a tree). |
6884 | This is null for libcalls where that information may | |
6885 | not be available. | |
6886 | MODE is the argument's machine mode. | |
6887 | SLOTNO is the index number of the argument's slot in the parameter array. | |
84ea0f58 | 6888 | NAMED is true if this argument is a named parameter |
48028e21 EB |
6889 | (otherwise it is an extra parameter matching an ellipsis). |
6890 | REGBASE is the regno of the base register for the parameter array. */ | |
4900aa61 | 6891 | |
82d6b402 | 6892 | static rtx |
ef4bddc2 | 6893 | function_arg_record_value (const_tree type, machine_mode mode, |
84ea0f58 | 6894 | int slotno, bool named, int regbase) |
82d6b402 RH |
6895 | { |
6896 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
84ea0f58 EB |
6897 | assign_data_t data; |
6898 | int nregs; | |
82d6b402 | 6899 | |
84ea0f58 EB |
6900 | data.slotno = slotno; |
6901 | data.regbase = regbase; | |
82d6b402 | 6902 | |
84ea0f58 EB |
6903 | /* Count how many registers we need. */ |
6904 | data.nregs = 0; | |
6905 | data.intoffset = 0; | |
6906 | data.stack = false; | |
6907 | traverse_record_type<assign_data_t, count_registers> (type, named, &data); | |
82d6b402 | 6908 | |
1fd05073 | 6909 | /* Take into account pending integer fields. */ |
84ea0f58 EB |
6910 | if (compute_int_layout (typesize * BITS_PER_UNIT, &data, &nregs)) |
6911 | data.nregs += nregs; | |
82d6b402 RH |
6912 | |
6913 | /* Allocate the vector and handle some annoying special cases. */ | |
84ea0f58 | 6914 | nregs = data.nregs; |
e8d65a35 | 6915 | |
82d6b402 RH |
6916 | if (nregs == 0) |
6917 | { | |
6918 | /* ??? Empty structure has no value? Duh? */ | |
6919 | if (typesize <= 0) | |
6920 | { | |
6921 | /* Though there's nothing really to store, return a word register | |
6922 | anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL | |
6923 | leads to breakage due to the fact that there are zero bytes to | |
6924 | load. */ | |
1eac9f59 | 6925 | return gen_rtx_REG (mode, regbase); |
82d6b402 | 6926 | } |
e8d65a35 EB |
6927 | |
6928 | /* ??? C++ has structures with no fields, and yet a size. Give up | |
6929 | for now and pass everything back in integer registers. */ | |
6930 | nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
82d6b402 RH |
6931 | if (nregs + slotno > SPARC_INT_ARG_MAX) |
6932 | nregs = SPARC_INT_ARG_MAX - slotno; | |
6933 | } | |
e8d65a35 EB |
6934 | |
6935 | gcc_assert (nregs > 0); | |
82d6b402 | 6936 | |
84ea0f58 | 6937 | data.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (data.stack + nregs)); |
48028e21 EB |
6938 | |
6939 | /* If at least one field must be passed on the stack, generate | |
6940 | (parallel [(expr_list (nil) ...) ...]) so that all fields will | |
6941 | also be passed on the stack. We can't do much better because the | |
78a52f11 | 6942 | semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case |
48028e21 EB |
6943 | of structures for which the fields passed exclusively in registers |
6944 | are not at the beginning of the structure. */ | |
84ea0f58 EB |
6945 | if (data.stack) |
6946 | XVECEXP (data.ret, 0, 0) | |
48028e21 | 6947 | = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); |
82d6b402 | 6948 | |
84ea0f58 EB |
6949 | /* Assign the registers. */ |
6950 | data.nregs = 0; | |
6951 | data.intoffset = 0; | |
6952 | traverse_record_type<assign_data_t, assign_registers> (type, named, &data); | |
82d6b402 | 6953 | |
84ea0f58 EB |
6954 | /* Assign pending integer fields. */ |
6955 | assign_int_registers (typesize * BITS_PER_UNIT, &data); | |
82d6b402 | 6956 | |
84ea0f58 EB |
6957 | gcc_assert (data.nregs == nregs); |
6958 | ||
6959 | return data.ret; | |
82d6b402 RH |
6960 | } |
6961 | ||
bf44d792 | 6962 | /* Used by function_arg and sparc_function_value_1 to implement the conventions |
a7bba6ca | 6963 | of the 64-bit ABI for passing and returning unions. |
bf44d792 AS |
6964 | Return an expression valid as a return value for the FUNCTION_ARG |
6965 | and TARGET_FUNCTION_VALUE. | |
a7bba6ca EB |
6966 | |
6967 | SIZE is the size in bytes of the union. | |
85bbb21f | 6968 | MODE is the argument's machine mode. |
a7bba6ca EB |
6969 | REGNO is the hard register the union will be passed in. */ |
6970 | ||
6971 | static rtx | |
ef4bddc2 | 6972 | function_arg_union_value (int size, machine_mode mode, int slotno, |
22d8d627 | 6973 | int regno) |
a7bba6ca | 6974 | { |
f3c7a945 | 6975 | int nwords = CEIL_NWORDS (size), i; |
85bbb21f | 6976 | rtx regs; |
a7bba6ca | 6977 | |
bb05e341 EB |
6978 | /* See comment in previous function for empty structures. */ |
6979 | if (nwords == 0) | |
6980 | return gen_rtx_REG (mode, regno); | |
6981 | ||
22d8d627 EB |
6982 | if (slotno == SPARC_INT_ARG_MAX - 1) |
6983 | nwords = 1; | |
6984 | ||
85bbb21f | 6985 | regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords)); |
a7bba6ca | 6986 | |
85bbb21f | 6987 | for (i = 0; i < nwords; i++) |
45261626 EB |
6988 | { |
6989 | /* Unions are passed left-justified. */ | |
6990 | XVECEXP (regs, 0, i) | |
6991 | = gen_rtx_EXPR_LIST (VOIDmode, | |
6992 | gen_rtx_REG (word_mode, regno), | |
6993 | GEN_INT (UNITS_PER_WORD * i)); | |
6994 | regno++; | |
6995 | } | |
6996 | ||
6997 | return regs; | |
6998 | } | |
6999 | ||
bf44d792 | 7000 | /* Used by function_arg and sparc_function_value_1 to implement the conventions |
58926ad4 | 7001 | for passing and returning BLKmode vectors. |
bf44d792 AS |
7002 | Return an expression valid as a return value for the FUNCTION_ARG |
7003 | and TARGET_FUNCTION_VALUE. | |
45261626 | 7004 | |
58926ad4 | 7005 | SIZE is the size in bytes of the vector. |
45261626 EB |
7006 | REGNO is the FP hard register the vector will be passed in. */ |
7007 | ||
7008 | static rtx | |
26237a50 | 7009 | function_arg_vector_value (int size, int regno) |
45261626 | 7010 | { |
58926ad4 EB |
7011 | const int nregs = MAX (1, size / 8); |
7012 | rtx regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs)); | |
7013 | ||
7014 | if (size < 8) | |
7015 | XVECEXP (regs, 0, 0) | |
7016 | = gen_rtx_EXPR_LIST (VOIDmode, | |
7017 | gen_rtx_REG (SImode, regno), | |
7018 | const0_rtx); | |
7019 | else | |
7020 | for (int i = 0; i < nregs; i++) | |
45261626 EB |
7021 | XVECEXP (regs, 0, i) |
7022 | = gen_rtx_EXPR_LIST (VOIDmode, | |
26237a50 EB |
7023 | gen_rtx_REG (DImode, regno + 2*i), |
7024 | GEN_INT (i*8)); | |
a7bba6ca | 7025 | |
85bbb21f | 7026 | return regs; |
a7bba6ca EB |
7027 | } |
7028 | ||
9adafb9f | 7029 | /* Determine where to put an argument to a function. |
4fb4e4b8 DE |
7030 | Value is zero to push the argument on the stack, |
7031 | or a hard register in which to store the argument. | |
7032 | ||
7033 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
7034 | the preceding args and about the function being called. | |
7035 | MODE is the argument's machine mode. | |
7036 | TYPE is the data type of the argument (as a tree). | |
7037 | This is null for libcalls where that information may | |
7038 | not be available. | |
9adafb9f | 7039 | NAMED is true if this argument is a named parameter |
4fb4e4b8 | 7040 | (otherwise it is an extra parameter matching an ellipsis). |
9adafb9f NF |
7041 | INCOMING_P is false for TARGET_FUNCTION_ARG, true for |
7042 | TARGET_FUNCTION_INCOMING_ARG. */ | |
61a55e8b | 7043 | |
9adafb9f | 7044 | static rtx |
ef4bddc2 | 7045 | sparc_function_arg_1 (cumulative_args_t cum_v, machine_mode mode, |
84ea0f58 | 7046 | const_tree type, bool named, bool incoming) |
61a55e8b | 7047 | { |
d5cc9181 JR |
7048 | const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
7049 | ||
84ea0f58 | 7050 | int regbase = (incoming |
4fb4e4b8 DE |
7051 | ? SPARC_INCOMING_INT_ARG_FIRST |
7052 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
7053 | int slotno, regno, padding; | |
45261626 | 7054 | enum mode_class mclass = GET_MODE_CLASS (mode); |
4fb4e4b8 | 7055 | |
84ea0f58 | 7056 | slotno = function_arg_slotno (cum, mode, type, named, incoming, |
4fb4e4b8 | 7057 | ®no, &padding); |
4fb4e4b8 DE |
7058 | if (slotno == -1) |
7059 | return 0; | |
7060 | ||
ef6843ed EB |
7061 | /* Vector types deserve special treatment because they are polymorphic wrt |
7062 | their mode, depending upon whether VIS instructions are enabled. */ | |
7063 | if (type && TREE_CODE (type) == VECTOR_TYPE) | |
4fb4e4b8 | 7064 | { |
ef6843ed EB |
7065 | HOST_WIDE_INT size = int_size_in_bytes (type); |
7066 | gcc_assert ((TARGET_ARCH32 && size <= 8) | |
7067 | || (TARGET_ARCH64 && size <= 16)); | |
7068 | ||
7069 | if (mode == BLKmode) | |
58926ad4 EB |
7070 | return function_arg_vector_value (size, SPARC_FP_ARG_FIRST + 2*slotno); |
7071 | ||
7072 | mclass = MODE_FLOAT; | |
4fb4e4b8 | 7073 | } |
4043d6fb | 7074 | |
ef6843ed EB |
7075 | if (TARGET_ARCH32) |
7076 | return gen_rtx_REG (mode, regno); | |
4043d6fb | 7077 | |
ef6843ed EB |
7078 | /* Structures up to 16 bytes in size are passed in arg slots on the stack |
7079 | and are promoted to registers if possible. */ | |
7080 | if (type && TREE_CODE (type) == RECORD_TYPE) | |
4043d6fb | 7081 | { |
a7bba6ca | 7082 | HOST_WIDE_INT size = int_size_in_bytes (type); |
f5f7d171 | 7083 | gcc_assert (size <= 16); |
4fb4e4b8 | 7084 | |
ef6843ed | 7085 | return function_arg_record_value (type, mode, slotno, named, regbase); |
4043d6fb | 7086 | } |
ef6843ed EB |
7087 | |
7088 | /* Unions up to 16 bytes in size are passed in integer registers. */ | |
7089 | else if (type && TREE_CODE (type) == UNION_TYPE) | |
45261626 | 7090 | { |
45261626 | 7091 | HOST_WIDE_INT size = int_size_in_bytes (type); |
f5f7d171 | 7092 | gcc_assert (size <= 16); |
45261626 | 7093 | |
ef6843ed | 7094 | return function_arg_union_value (size, mode, slotno, regno); |
45261626 EB |
7095 | } |
7096 | ||
4fb4e4b8 DE |
7097 | /* v9 fp args in reg slots beyond the int reg slots get passed in regs |
7098 | but also have the slot allocated for them. | |
7099 | If no prototype is in scope fp values in register slots get passed | |
7100 | in two places, either fp regs and int regs or fp regs and memory. */ | |
ef6843ed EB |
7101 | else if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) |
7102 | && SPARC_FP_REG_P (regno)) | |
4fb4e4b8 | 7103 | { |
ef6843ed | 7104 | rtx reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 | 7105 | if (cum->prototype_p || cum->libcall_p) |
84ea0f58 | 7106 | return reg; |
4fb4e4b8 DE |
7107 | else |
7108 | { | |
82d6b402 RH |
7109 | rtx v0, v1; |
7110 | ||
4fb4e4b8 DE |
7111 | if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) |
7112 | { | |
82d6b402 RH |
7113 | int intreg; |
7114 | ||
7115 | /* On incoming, we don't need to know that the value | |
7116 | is passed in %f0 and %i0, and it confuses other parts | |
7117 | causing needless spillage even on the simplest cases. */ | |
84ea0f58 | 7118 | if (incoming) |
82d6b402 RH |
7119 | return reg; |
7120 | ||
7121 | intreg = (SPARC_OUTGOING_INT_ARG_FIRST | |
7122 | + (regno - SPARC_FP_ARG_FIRST) / 2); | |
7123 | ||
7124 | v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
7125 | v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), | |
7126 | const0_rtx); | |
7127 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4fb4e4b8 DE |
7128 | } |
7129 | else | |
82d6b402 RH |
7130 | { |
7131 | v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
7132 | v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
7133 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
7134 | } | |
4fb4e4b8 DE |
7135 | } |
7136 | } | |
ef6843ed EB |
7137 | |
7138 | /* All other aggregate types are passed in an integer register in a mode | |
7139 | corresponding to the size of the type. */ | |
7140 | else if (type && AGGREGATE_TYPE_P (type)) | |
4fb4e4b8 | 7141 | { |
ef6843ed EB |
7142 | HOST_WIDE_INT size = int_size_in_bytes (type); |
7143 | gcc_assert (size <= 16); | |
7144 | ||
f4b31647 | 7145 | mode = int_mode_for_size (size * BITS_PER_UNIT, 0).else_blk (); |
4fb4e4b8 DE |
7146 | } |
7147 | ||
ef6843ed | 7148 | return gen_rtx_REG (mode, regno); |
4fb4e4b8 | 7149 | } |
a7acd911 | 7150 | |
9adafb9f NF |
7151 | /* Handle the TARGET_FUNCTION_ARG target hook. */ |
7152 | ||
7153 | static rtx | |
ef4bddc2 | 7154 | sparc_function_arg (cumulative_args_t cum, machine_mode mode, |
9adafb9f NF |
7155 | const_tree type, bool named) |
7156 | { | |
7157 | return sparc_function_arg_1 (cum, mode, type, named, false); | |
7158 | } | |
7159 | ||
7160 | /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */ | |
7161 | ||
7162 | static rtx | |
ef4bddc2 | 7163 | sparc_function_incoming_arg (cumulative_args_t cum, machine_mode mode, |
9adafb9f NF |
7164 | const_tree type, bool named) |
7165 | { | |
7166 | return sparc_function_arg_1 (cum, mode, type, named, true); | |
7167 | } | |
7168 | ||
c2ed6cf8 NF |
7169 | /* For sparc64, objects requiring 16 byte alignment are passed that way. */ |
7170 | ||
7171 | static unsigned int | |
ef4bddc2 | 7172 | sparc_function_arg_boundary (machine_mode mode, const_tree type) |
c2ed6cf8 NF |
7173 | { |
7174 | return ((TARGET_ARCH64 | |
7175 | && (GET_MODE_ALIGNMENT (mode) == 128 | |
7176 | || (type && TYPE_ALIGN (type) == 128))) | |
7177 | ? 128 | |
7178 | : PARM_BOUNDARY); | |
7179 | } | |
7180 | ||
78a52f11 RH |
7181 | /* For an arg passed partly in registers and partly in memory, |
7182 | this is the number of bytes of registers used. | |
4fb4e4b8 | 7183 | For args passed entirely in registers or entirely in memory, zero. |
61a55e8b | 7184 | |
4fb4e4b8 DE |
7185 | Any arg that starts in the first 6 regs but won't entirely fit in them |
7186 | needs partial registers on v8. On v9, structures with integer | |
7187 | values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp | |
7188 | values that begin in the last fp reg [where "last fp reg" varies with the | |
7189 | mode] will be split between that reg and memory. */ | |
61a55e8b | 7190 | |
78a52f11 | 7191 | static int |
ef4bddc2 | 7192 | sparc_arg_partial_bytes (cumulative_args_t cum, machine_mode mode, |
78a52f11 | 7193 | tree type, bool named) |
4fb4e4b8 DE |
7194 | { |
7195 | int slotno, regno, padding; | |
61a55e8b | 7196 | |
84ea0f58 | 7197 | /* We pass false for incoming here, it doesn't matter. */ |
d5cc9181 JR |
7198 | slotno = function_arg_slotno (get_cumulative_args (cum), mode, type, named, |
7199 | false, ®no, &padding); | |
4fb4e4b8 DE |
7200 | |
7201 | if (slotno == -1) | |
7202 | return 0; | |
7203 | ||
7204 | if (TARGET_ARCH32) | |
bf62bbf1 | 7205 | { |
4fb4e4b8 | 7206 | if ((slotno + (mode == BLKmode |
f3c7a945 EB |
7207 | ? CEIL_NWORDS (int_size_in_bytes (type)) |
7208 | : CEIL_NWORDS (GET_MODE_SIZE (mode)))) | |
1b5963f7 | 7209 | > SPARC_INT_ARG_MAX) |
78a52f11 | 7210 | return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD; |
4fb4e4b8 DE |
7211 | } |
7212 | else | |
7213 | { | |
8cd5a4e0 | 7214 | /* We are guaranteed by pass_by_reference that the size of the |
78a52f11 RH |
7215 | argument is not greater than 16 bytes, so we only need to return |
7216 | one word if the argument is partially passed in registers. */ | |
1b5963f7 | 7217 | |
4fb4e4b8 DE |
7218 | if (type && AGGREGATE_TYPE_P (type)) |
7219 | { | |
7220 | int size = int_size_in_bytes (type); | |
bf62bbf1 | 7221 | |
1b5963f7 | 7222 | if (size > UNITS_PER_WORD |
84ea0f58 EB |
7223 | && (slotno == SPARC_INT_ARG_MAX - 1 |
7224 | || slotno == SPARC_FP_ARG_MAX - 1)) | |
78a52f11 | 7225 | return UNITS_PER_WORD; |
4fb4e4b8 | 7226 | } |
0a9e65f9 | 7227 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT |
4fb4e4b8 | 7228 | || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT |
c3427c7d | 7229 | && ! (TARGET_FPU && named))) |
4fb4e4b8 | 7230 | { |
0a9e65f9 | 7231 | /* The complex types are passed as packed types. */ |
1b5963f7 EB |
7232 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD |
7233 | && slotno == SPARC_INT_ARG_MAX - 1) | |
78a52f11 | 7234 | return UNITS_PER_WORD; |
4fb4e4b8 DE |
7235 | } |
7236 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
7237 | { | |
4fb4e4b8 DE |
7238 | if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) |
7239 | > SPARC_FP_ARG_MAX) | |
78a52f11 | 7240 | return UNITS_PER_WORD; |
4fb4e4b8 | 7241 | } |
bf62bbf1 | 7242 | } |
1b5963f7 EB |
7243 | |
7244 | return 0; | |
4fb4e4b8 | 7245 | } |
61a55e8b | 7246 | |
45261626 EB |
7247 | /* Handle the TARGET_PASS_BY_REFERENCE target hook. |
7248 | Specify whether to pass the argument by reference. */ | |
4fb4e4b8 | 7249 | |
8cd5a4e0 | 7250 | static bool |
d5cc9181 | 7251 | sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED, |
ef4bddc2 | 7252 | machine_mode mode, const_tree type, |
8cd5a4e0 | 7253 | bool named ATTRIBUTE_UNUSED) |
4fb4e4b8 DE |
7254 | { |
7255 | if (TARGET_ARCH32) | |
45261626 EB |
7256 | /* Original SPARC 32-bit ABI says that structures and unions, |
7257 | and quad-precision floats are passed by reference. For Pascal, | |
7258 | also pass arrays by reference. All other base types are passed | |
7259 | in registers. | |
7260 | ||
7261 | Extended ABI (as implemented by the Sun compiler) says that all | |
7262 | complex floats are passed by reference. Pass complex integers | |
7263 | in registers up to 8 bytes. More generally, enforce the 2-word | |
7264 | cap for passing arguments in registers. | |
7265 | ||
7266 | Vector ABI (as implemented by the Sun VIS SDK) says that vector | |
7267 | integers are passed like floats of the same size, that is in | |
7268 | registers up to 8 bytes. Pass all vector floats by reference | |
7269 | like structure and unions. */ | |
ef6843ed EB |
7270 | return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type))) |
7271 | || mode == SCmode | |
7272 | /* Catch CDImode, TFmode, DCmode and TCmode. */ | |
7273 | || GET_MODE_SIZE (mode) > 8 | |
7274 | || (type | |
7275 | && TREE_CODE (type) == VECTOR_TYPE | |
7276 | && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)); | |
4fb4e4b8 | 7277 | else |
45261626 EB |
7278 | /* Original SPARC 64-bit ABI says that structures and unions |
7279 | smaller than 16 bytes are passed in registers, as well as | |
ef6843ed | 7280 | all other base types. |
4900aa61 | 7281 | |
45261626 EB |
7282 | Extended ABI (as implemented by the Sun compiler) says that |
7283 | complex floats are passed in registers up to 16 bytes. Pass | |
7284 | all complex integers in registers up to 16 bytes. More generally, | |
7285 | enforce the 2-word cap for passing arguments in registers. | |
7286 | ||
7287 | Vector ABI (as implemented by the Sun VIS SDK) says that vector | |
7288 | integers are passed like floats of the same size, that is in | |
7289 | registers (up to 16 bytes). Pass all vector floats like structure | |
7290 | and unions. */ | |
ef6843ed EB |
7291 | return ((type |
7292 | && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE) | |
7293 | && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16) | |
7294 | /* Catch CTImode and TCmode. */ | |
7295 | || GET_MODE_SIZE (mode) > 16); | |
4fb4e4b8 DE |
7296 | } |
7297 | ||
9adafb9f | 7298 | /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook. |
4fb4e4b8 DE |
7299 | Update the data in CUM to advance over an argument |
7300 | of mode MODE and data type TYPE. | |
7301 | TYPE is null for libcalls where that information may not be available. */ | |
7302 | ||
9adafb9f | 7303 | static void |
ef4bddc2 | 7304 | sparc_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, |
9adafb9f | 7305 | const_tree type, bool named) |
4fb4e4b8 | 7306 | { |
d5cc9181 | 7307 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
e0c7ff23 | 7308 | int regno, padding; |
4fb4e4b8 | 7309 | |
84ea0f58 | 7310 | /* We pass false for incoming here, it doesn't matter. */ |
9adafb9f | 7311 | function_arg_slotno (cum, mode, type, named, false, ®no, &padding); |
4fb4e4b8 | 7312 | |
e0c7ff23 EB |
7313 | /* If argument requires leading padding, add it. */ |
7314 | cum->words += padding; | |
eadceb59 | 7315 | |
4fb4e4b8 | 7316 | if (TARGET_ARCH32) |
84ea0f58 | 7317 | cum->words += (mode == BLKmode |
f3c7a945 EB |
7318 | ? CEIL_NWORDS (int_size_in_bytes (type)) |
7319 | : CEIL_NWORDS (GET_MODE_SIZE (mode))); | |
4fb4e4b8 DE |
7320 | else |
7321 | { | |
7322 | if (type && AGGREGATE_TYPE_P (type)) | |
7323 | { | |
7324 | int size = int_size_in_bytes (type); | |
7325 | ||
7326 | if (size <= 8) | |
7327 | ++cum->words; | |
7328 | else if (size <= 16) | |
7329 | cum->words += 2; | |
7330 | else /* passed by reference */ | |
7331 | ++cum->words; | |
7332 | } | |
4fb4e4b8 | 7333 | else |
84ea0f58 | 7334 | cum->words += (mode == BLKmode |
f3c7a945 EB |
7335 | ? CEIL_NWORDS (int_size_in_bytes (type)) |
7336 | : CEIL_NWORDS (GET_MODE_SIZE (mode))); | |
eadceb59 | 7337 | } |
4fb4e4b8 | 7338 | } |
eadceb59 | 7339 | |
76b0cbf8 RS |
7340 | /* Implement TARGET_FUNCTION_ARG_PADDING. For the 64-bit ABI structs |
7341 | are always stored left shifted in their argument slot. */ | |
4fb4e4b8 | 7342 | |
76b0cbf8 RS |
7343 | static pad_direction |
7344 | sparc_function_arg_padding (machine_mode mode, const_tree type) | |
4fb4e4b8 | 7345 | { |
84ea0f58 | 7346 | if (TARGET_ARCH64 && type && AGGREGATE_TYPE_P (type)) |
76b0cbf8 | 7347 | return PAD_UPWARD; |
61a55e8b | 7348 | |
d3704c46 | 7349 | /* Fall back to the default. */ |
76b0cbf8 | 7350 | return default_function_arg_padding (mode, type); |
61a55e8b | 7351 | } |
82d6b402 | 7352 | |
1b5963f7 EB |
7353 | /* Handle the TARGET_RETURN_IN_MEMORY target hook. |
7354 | Specify whether to return the return value in memory. */ | |
7355 | ||
7356 | static bool | |
586de218 | 7357 | sparc_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
1b5963f7 EB |
7358 | { |
7359 | if (TARGET_ARCH32) | |
45261626 EB |
7360 | /* Original SPARC 32-bit ABI says that structures and unions, |
7361 | and quad-precision floats are returned in memory. All other | |
7362 | base types are returned in registers. | |
7363 | ||
7364 | Extended ABI (as implemented by the Sun compiler) says that | |
7365 | all complex floats are returned in registers (8 FP registers | |
7366 | at most for '_Complex long double'). Return all complex integers | |
7367 | in registers (4 at most for '_Complex long long'). | |
7368 | ||
7369 | Vector ABI (as implemented by the Sun VIS SDK) says that vector | |
7370 | integers are returned like floats of the same size, that is in | |
7371 | registers up to 8 bytes and in memory otherwise. Return all | |
7372 | vector floats in memory like structure and unions; note that | |
7373 | they always have BLKmode like the latter. */ | |
1b5963f7 EB |
7374 | return (TYPE_MODE (type) == BLKmode |
7375 | || TYPE_MODE (type) == TFmode | |
45261626 EB |
7376 | || (TREE_CODE (type) == VECTOR_TYPE |
7377 | && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)); | |
1b5963f7 EB |
7378 | else |
7379 | /* Original SPARC 64-bit ABI says that structures and unions | |
45261626 EB |
7380 | smaller than 32 bytes are returned in registers, as well as |
7381 | all other base types. | |
4900aa61 | 7382 | |
45261626 EB |
7383 | Extended ABI (as implemented by the Sun compiler) says that all |
7384 | complex floats are returned in registers (8 FP registers at most | |
7385 | for '_Complex long double'). Return all complex integers in | |
7386 | registers (4 at most for '_Complex TItype'). | |
7387 | ||
7388 | Vector ABI (as implemented by the Sun VIS SDK) says that vector | |
7389 | integers are returned like floats of the same size, that is in | |
7390 | registers. Return all vector floats like structure and unions; | |
7391 | note that they always have BLKmode like the latter. */ | |
f79e1b0f EB |
7392 | return (TYPE_MODE (type) == BLKmode |
7393 | && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32); | |
1b5963f7 EB |
7394 | } |
7395 | ||
7396 | /* Handle the TARGET_STRUCT_VALUE target hook. | |
7397 | Return where to find the structure return value address. */ | |
7398 | ||
7399 | static rtx | |
2225b57c | 7400 | sparc_struct_value_rtx (tree fndecl, int incoming) |
1b5963f7 EB |
7401 | { |
7402 | if (TARGET_ARCH64) | |
7403 | return 0; | |
7404 | else | |
7405 | { | |
1da4c3a7 EB |
7406 | rtx mem; |
7407 | ||
1b5963f7 | 7408 | if (incoming) |
0a81f074 | 7409 | mem = gen_frame_mem (Pmode, plus_constant (Pmode, frame_pointer_rtx, |
114ce554 | 7410 | STRUCT_VALUE_OFFSET)); |
1b5963f7 | 7411 | else |
0a81f074 | 7412 | mem = gen_frame_mem (Pmode, plus_constant (Pmode, stack_pointer_rtx, |
114ce554 | 7413 | STRUCT_VALUE_OFFSET)); |
1da4c3a7 | 7414 | |
4900aa61 EB |
7415 | /* Only follow the SPARC ABI for fixed-size structure returns. |
7416 | Variable size structure returns are handled per the normal | |
2225b57c | 7417 | procedures in GCC. This is enabled by -mstd-struct-return */ |
4900aa61 | 7418 | if (incoming == 2 |
2225b57c CD |
7419 | && sparc_std_struct_return |
7420 | && TYPE_SIZE_UNIT (TREE_TYPE (fndecl)) | |
7421 | && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl))) == INTEGER_CST) | |
7422 | { | |
9250444b EB |
7423 | /* We must check and adjust the return address, as it is optional |
7424 | as to whether the return object is really provided. */ | |
7425 | rtx ret_reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); | |
2225b57c | 7426 | rtx scratch = gen_reg_rtx (SImode); |
19f8b229 | 7427 | rtx_code_label *endlab = gen_label_rtx (); |
2225b57c | 7428 | |
9250444b | 7429 | /* Calculate the return object size. */ |
2225b57c CD |
7430 | tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl)); |
7431 | rtx size_rtx = GEN_INT (TREE_INT_CST_LOW (size) & 0xfff); | |
9250444b | 7432 | /* Construct a temporary return value. */ |
f79e1b0f EB |
7433 | rtx temp_val |
7434 | = assign_stack_local (Pmode, TREE_INT_CST_LOW (size), 0); | |
2225b57c | 7435 | |
f79e1b0f | 7436 | /* Implement SPARC 32-bit psABI callee return struct checking: |
4900aa61 | 7437 | |
f79e1b0f | 7438 | Fetch the instruction where we will return to and see if |
2225b57c CD |
7439 | it's an unimp instruction (the most significant 10 bits |
7440 | will be zero). */ | |
7441 | emit_move_insn (scratch, gen_rtx_MEM (SImode, | |
0a81f074 RS |
7442 | plus_constant (Pmode, |
7443 | ret_reg, 8))); | |
9250444b | 7444 | /* Assume the size is valid and pre-adjust. */ |
3810076b | 7445 | emit_insn (gen_add3_insn (ret_reg, ret_reg, GEN_INT (4))); |
f79e1b0f EB |
7446 | emit_cmp_and_jump_insns (scratch, size_rtx, EQ, const0_rtx, SImode, |
7447 | 0, endlab); | |
3810076b | 7448 | emit_insn (gen_sub3_insn (ret_reg, ret_reg, GEN_INT (4))); |
f79e1b0f | 7449 | /* Write the address of the memory pointed to by temp_val into |
9250444b | 7450 | the memory pointed to by mem. */ |
2225b57c CD |
7451 | emit_move_insn (mem, XEXP (temp_val, 0)); |
7452 | emit_label (endlab); | |
7453 | } | |
7454 | ||
1da4c3a7 | 7455 | return mem; |
1b5963f7 EB |
7456 | } |
7457 | } | |
7458 | ||
bf44d792 | 7459 | /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook. |
82d6b402 | 7460 | For v9, function return values are subject to the same rules as arguments, |
1b5963f7 | 7461 | except that up to 32 bytes may be returned in registers. */ |
82d6b402 | 7462 | |
bf44d792 | 7463 | static rtx |
ef4bddc2 | 7464 | sparc_function_value_1 (const_tree type, machine_mode mode, |
bf44d792 | 7465 | bool outgoing) |
82d6b402 | 7466 | { |
1b5963f7 | 7467 | /* Beware that the two values are swapped here wrt function_arg. */ |
bf44d792 AS |
7468 | int regbase = (outgoing |
7469 | ? SPARC_INCOMING_INT_ARG_FIRST | |
7470 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
45261626 | 7471 | enum mode_class mclass = GET_MODE_CLASS (mode); |
82d6b402 | 7472 | int regno; |
82d6b402 | 7473 | |
ef6843ed EB |
7474 | /* Vector types deserve special treatment because they are polymorphic wrt |
7475 | their mode, depending upon whether VIS instructions are enabled. */ | |
45261626 EB |
7476 | if (type && TREE_CODE (type) == VECTOR_TYPE) |
7477 | { | |
45261626 | 7478 | HOST_WIDE_INT size = int_size_in_bytes (type); |
f5f7d171 JM |
7479 | gcc_assert ((TARGET_ARCH32 && size <= 8) |
7480 | || (TARGET_ARCH64 && size <= 32)); | |
45261626 EB |
7481 | |
7482 | if (mode == BLKmode) | |
58926ad4 EB |
7483 | return function_arg_vector_value (size, SPARC_FP_ARG_FIRST); |
7484 | ||
7485 | mclass = MODE_FLOAT; | |
45261626 | 7486 | } |
ef6843ed EB |
7487 | |
7488 | if (TARGET_ARCH64 && type) | |
82d6b402 | 7489 | { |
ef6843ed | 7490 | /* Structures up to 32 bytes in size are returned in registers. */ |
82d6b402 RH |
7491 | if (TREE_CODE (type) == RECORD_TYPE) |
7492 | { | |
ef6843ed EB |
7493 | HOST_WIDE_INT size = int_size_in_bytes (type); |
7494 | gcc_assert (size <= 32); | |
82d6b402 | 7495 | |
1eac9f59 | 7496 | return function_arg_record_value (type, mode, 0, 1, regbase); |
82d6b402 | 7497 | } |
ef6843ed EB |
7498 | |
7499 | /* Unions up to 32 bytes in size are returned in integer registers. */ | |
a7bba6ca EB |
7500 | else if (TREE_CODE (type) == UNION_TYPE) |
7501 | { | |
7502 | HOST_WIDE_INT size = int_size_in_bytes (type); | |
f5f7d171 | 7503 | gcc_assert (size <= 32); |
a7bba6ca | 7504 | |
22d8d627 | 7505 | return function_arg_union_value (size, mode, 0, regbase); |
a7bba6ca | 7506 | } |
ef6843ed EB |
7507 | |
7508 | /* Objects that require it are returned in FP registers. */ | |
7509 | else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) | |
7510 | ; | |
7511 | ||
7512 | /* All other aggregate types are returned in an integer register in a | |
7513 | mode corresponding to the size of the type. */ | |
8a7199ad | 7514 | else if (AGGREGATE_TYPE_P (type)) |
82d6b402 | 7515 | { |
8a7199ad RK |
7516 | /* All other aggregate types are passed in an integer register |
7517 | in a mode corresponding to the size of the type. */ | |
ef6843ed EB |
7518 | HOST_WIDE_INT size = int_size_in_bytes (type); |
7519 | gcc_assert (size <= 32); | |
82d6b402 | 7520 | |
f4b31647 | 7521 | mode = int_mode_for_size (size * BITS_PER_UNIT, 0).else_blk (); |
c74fd3f1 EB |
7522 | |
7523 | /* ??? We probably should have made the same ABI change in | |
7524 | 3.4.0 as the one we made for unions. The latter was | |
7525 | required by the SCD though, while the former is not | |
7526 | specified, so we favored compatibility and efficiency. | |
7527 | ||
7528 | Now we're stuck for aggregates larger than 16 bytes, | |
7529 | because OImode vanished in the meantime. Let's not | |
7530 | try to be unduly clever, and simply follow the ABI | |
7531 | for unions in that case. */ | |
7532 | if (mode == BLKmode) | |
ef6843ed | 7533 | return function_arg_union_value (size, mode, 0, regbase); |
45261626 EB |
7534 | else |
7535 | mclass = MODE_INT; | |
82d6b402 | 7536 | } |
ef6843ed | 7537 | |
f79e1b0f EB |
7538 | /* We should only have pointer and integer types at this point. This |
7539 | must match sparc_promote_function_mode. */ | |
ef6843ed | 7540 | else if (mclass == MODE_INT && GET_MODE_SIZE (mode) < UNITS_PER_WORD) |
a7bba6ca | 7541 | mode = word_mode; |
82d6b402 RH |
7542 | } |
7543 | ||
fbae25c0 EB |
7544 | /* We should only have pointer and integer types at this point, except with |
7545 | -freg-struct-return. This must match sparc_promote_function_mode. */ | |
f79e1b0f | 7546 | else if (TARGET_ARCH32 |
fbae25c0 | 7547 | && !(type && AGGREGATE_TYPE_P (type)) |
f79e1b0f EB |
7548 | && mclass == MODE_INT |
7549 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
7550 | mode = word_mode; | |
7551 | ||
ef6843ed | 7552 | if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) && TARGET_FPU) |
1b5963f7 | 7553 | regno = SPARC_FP_ARG_FIRST; |
82d6b402 | 7554 | else |
1b5963f7 | 7555 | regno = regbase; |
82d6b402 | 7556 | |
254110c2 | 7557 | return gen_rtx_REG (mode, regno); |
82d6b402 RH |
7558 | } |
7559 | ||
bf44d792 | 7560 | /* Handle TARGET_FUNCTION_VALUE. |
f79e1b0f EB |
7561 | On the SPARC, the value is found in the first "output" register, but the |
7562 | called function leaves it in the first "input" register. */ | |
bf44d792 AS |
7563 | |
7564 | static rtx | |
7565 | sparc_function_value (const_tree valtype, | |
7566 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
7567 | bool outgoing) | |
7568 | { | |
7569 | return sparc_function_value_1 (valtype, TYPE_MODE (valtype), outgoing); | |
7570 | } | |
7571 | ||
7572 | /* Handle TARGET_LIBCALL_VALUE. */ | |
7573 | ||
7574 | static rtx | |
ef4bddc2 | 7575 | sparc_libcall_value (machine_mode mode, |
bf44d792 AS |
7576 | const_rtx fun ATTRIBUTE_UNUSED) |
7577 | { | |
7578 | return sparc_function_value_1 (NULL_TREE, mode, false); | |
7579 | } | |
7580 | ||
f79e1b0f EB |
7581 | /* Handle FUNCTION_VALUE_REGNO_P. |
7582 | On the SPARC, the first "output" reg is used for integer values, and the | |
7583 | first floating point register is used for floating point values. */ | |
bf44d792 AS |
7584 | |
7585 | static bool | |
7586 | sparc_function_value_regno_p (const unsigned int regno) | |
7587 | { | |
9cb00eb1 | 7588 | return (regno == 8 || (TARGET_FPU && regno == 32)); |
bf44d792 AS |
7589 | } |
7590 | ||
648d2ffc RH |
7591 | /* Do what is necessary for `va_start'. We look at the current function |
7592 | to determine if stdarg or varargs is used and return the address of | |
7593 | the first unnamed parameter. */ | |
3ea1fdd3 | 7594 | |
3e2cc1d1 | 7595 | static rtx |
fc27d102 | 7596 | sparc_builtin_saveregs (void) |
3ea1fdd3 | 7597 | { |
38173d38 | 7598 | int first_reg = crtl->args.info.words; |
3ea1fdd3 JW |
7599 | rtx address; |
7600 | int regno; | |
7601 | ||
1b5963f7 | 7602 | for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++) |
254110c2 | 7603 | emit_move_insn (gen_rtx_MEM (word_mode, |
8ac61af7 RK |
7604 | gen_rtx_PLUS (Pmode, |
7605 | frame_pointer_rtx, | |
563c12b0 | 7606 | GEN_INT (FIRST_PARM_OFFSET (0) |
8ac61af7 RK |
7607 | + (UNITS_PER_WORD |
7608 | * regno)))), | |
254110c2 | 7609 | gen_rtx_REG (word_mode, |
1b5963f7 | 7610 | SPARC_INCOMING_INT_ARG_FIRST + regno)); |
3ea1fdd3 | 7611 | |
254110c2 | 7612 | address = gen_rtx_PLUS (Pmode, |
8ac61af7 | 7613 | frame_pointer_rtx, |
563c12b0 | 7614 | GEN_INT (FIRST_PARM_OFFSET (0) |
8ac61af7 | 7615 | + UNITS_PER_WORD * first_reg)); |
3ea1fdd3 JW |
7616 | |
7617 | return address; | |
7618 | } | |
a8b2c8a1 | 7619 | |
1b5963f7 | 7620 | /* Implement `va_start' for stdarg. */ |
a8b2c8a1 | 7621 | |
d7bd8aeb | 7622 | static void |
fc27d102 | 7623 | sparc_va_start (tree valist, rtx nextarg) |
a8b2c8a1 RH |
7624 | { |
7625 | nextarg = expand_builtin_saveregs (); | |
e5faf155 | 7626 | std_expand_builtin_va_start (valist, nextarg); |
a8b2c8a1 RH |
7627 | } |
7628 | ||
1b5963f7 | 7629 | /* Implement `va_arg' for stdarg. */ |
a8b2c8a1 | 7630 | |
35652573 | 7631 | static tree |
726a989a RB |
7632 | sparc_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, |
7633 | gimple_seq *post_p) | |
5f393b25 JM |
7634 | { |
7635 | HOST_WIDE_INT size, rsize, align; | |
7636 | tree addr, incr; | |
7637 | bool indirect; | |
7638 | tree ptrtype = build_pointer_type (type); | |
7639 | ||
22d66adf | 7640 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
5f393b25 JM |
7641 | { |
7642 | indirect = true; | |
7643 | size = rsize = UNITS_PER_WORD; | |
7644 | align = 0; | |
7645 | } | |
7646 | else | |
7647 | { | |
7648 | indirect = false; | |
7649 | size = int_size_in_bytes (type); | |
63b8ef40 | 7650 | rsize = ROUND_UP (size, UNITS_PER_WORD); |
5f393b25 | 7651 | align = 0; |
3764d512 | 7652 | |
5f393b25 JM |
7653 | if (TARGET_ARCH64) |
7654 | { | |
7655 | /* For SPARC64, objects requiring 16-byte alignment get it. */ | |
7656 | if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) | |
7657 | align = 2 * UNITS_PER_WORD; | |
7658 | ||
7659 | /* SPARC-V9 ABI states that structures up to 16 bytes in size | |
22d66adf | 7660 | are left-justified in their slots. */ |
5f393b25 JM |
7661 | if (AGGREGATE_TYPE_P (type)) |
7662 | { | |
7663 | if (size == 0) | |
7664 | size = rsize = UNITS_PER_WORD; | |
7665 | else | |
7666 | size = rsize; | |
7667 | } | |
7668 | } | |
7669 | } | |
7670 | ||
7671 | incr = valist; | |
7672 | if (align) | |
7673 | { | |
5d49b6a7 | 7674 | incr = fold_build_pointer_plus_hwi (incr, align - 1); |
5be014d5 AP |
7675 | incr = fold_convert (sizetype, incr); |
7676 | incr = fold_build2 (BIT_AND_EXPR, sizetype, incr, | |
7677 | size_int (-align)); | |
7678 | incr = fold_convert (ptr_type_node, incr); | |
5f393b25 JM |
7679 | } |
7680 | ||
7681 | gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue); | |
7682 | addr = incr; | |
7683 | ||
7684 | if (BYTES_BIG_ENDIAN && size < rsize) | |
5d49b6a7 | 7685 | addr = fold_build_pointer_plus_hwi (incr, rsize - size); |
5f393b25 JM |
7686 | |
7687 | if (indirect) | |
7688 | { | |
7689 | addr = fold_convert (build_pointer_type (ptrtype), addr); | |
22d66adf | 7690 | addr = build_va_arg_indirect_ref (addr); |
5f393b25 | 7691 | } |
3764d512 EB |
7692 | |
7693 | /* If the address isn't aligned properly for the type, we need a temporary. | |
7694 | FIXME: This is inefficient, usually we can do this in registers. */ | |
7695 | else if (align == 0 && TYPE_ALIGN (type) > BITS_PER_WORD) | |
5f393b25 JM |
7696 | { |
7697 | tree tmp = create_tmp_var (type, "va_arg_tmp"); | |
7698 | tree dest_addr = build_fold_addr_expr (tmp); | |
e79983f4 | 7699 | tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY), |
3764d512 EB |
7700 | 3, dest_addr, addr, size_int (rsize)); |
7701 | TREE_ADDRESSABLE (tmp) = 1; | |
5f393b25 JM |
7702 | gimplify_and_add (copy, pre_p); |
7703 | addr = dest_addr; | |
7704 | } | |
3764d512 | 7705 | |
5f393b25 JM |
7706 | else |
7707 | addr = fold_convert (ptrtype, addr); | |
7708 | ||
5d49b6a7 | 7709 | incr = fold_build_pointer_plus_hwi (incr, rsize); |
726a989a | 7710 | gimplify_assign (valist, incr, post_p); |
5f393b25 | 7711 | |
22d66adf | 7712 | return build_va_arg_indirect_ref (addr); |
5f393b25 | 7713 | } |
ab835497 | 7714 | \f |
c75d6010 JM |
7715 | /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook. |
7716 | Specify whether the vector mode is supported by the hardware. */ | |
7717 | ||
7718 | static bool | |
ef4bddc2 | 7719 | sparc_vector_mode_supported_p (machine_mode mode) |
c75d6010 JM |
7720 | { |
7721 | return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false; | |
7722 | } | |
7723 | \f | |
cc4b5170 | 7724 | /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */ |
26983c22 | 7725 | |
ef4bddc2 | 7726 | static machine_mode |
005ba29c | 7727 | sparc_preferred_simd_mode (scalar_mode mode) |
26983c22 | 7728 | { |
cc4b5170 RG |
7729 | if (TARGET_VIS) |
7730 | switch (mode) | |
7731 | { | |
4e10a5a7 | 7732 | case E_SImode: |
cc4b5170 | 7733 | return V2SImode; |
4e10a5a7 | 7734 | case E_HImode: |
cc4b5170 | 7735 | return V4HImode; |
4e10a5a7 | 7736 | case E_QImode: |
cc4b5170 RG |
7737 | return V8QImode; |
7738 | ||
7739 | default:; | |
7740 | } | |
7741 | ||
7742 | return word_mode; | |
26983c22 L |
7743 | } |
7744 | \f | |
1b3c2c2d EB |
7745 | /* Return the string to output an unconditional branch to LABEL, which is |
7746 | the operand number of the label. | |
7747 | ||
7748 | DEST is the destination insn (i.e. the label), INSN is the source. */ | |
7749 | ||
7750 | const char * | |
e1faf324 | 7751 | output_ubranch (rtx dest, rtx_insn *insn) |
1b3c2c2d EB |
7752 | { |
7753 | static char string[64]; | |
4e5b002b | 7754 | bool v9_form = false; |
8b98b5fd | 7755 | int delta; |
1b3c2c2d EB |
7756 | char *p; |
7757 | ||
8b98b5fd DM |
7758 | /* Even if we are trying to use cbcond for this, evaluate |
7759 | whether we can use V9 branches as our backup plan. */ | |
7760 | ||
7761 | delta = 5000000; | |
7762 | if (INSN_ADDRESSES_SET_P ()) | |
7763 | delta = (INSN_ADDRESSES (INSN_UID (dest)) | |
7764 | - INSN_ADDRESSES (INSN_UID (insn))); | |
7765 | ||
7766 | /* Leave some instructions for "slop". */ | |
7767 | if (TARGET_V9 && delta >= -260000 && delta < 260000) | |
7768 | v9_form = true; | |
7769 | ||
7770 | if (TARGET_CBCOND) | |
1b3c2c2d | 7771 | { |
8b98b5fd DM |
7772 | bool emit_nop = emit_cbcond_nop (insn); |
7773 | bool far = false; | |
7774 | const char *rval; | |
7775 | ||
7776 | if (delta < -500 || delta > 500) | |
7777 | far = true; | |
7778 | ||
7779 | if (far) | |
7780 | { | |
7781 | if (v9_form) | |
7782 | rval = "ba,a,pt\t%%xcc, %l0"; | |
7783 | else | |
7784 | rval = "b,a\t%l0"; | |
7785 | } | |
7786 | else | |
7787 | { | |
7788 | if (emit_nop) | |
7789 | rval = "cwbe\t%%g0, %%g0, %l0\n\tnop"; | |
7790 | else | |
7791 | rval = "cwbe\t%%g0, %%g0, %l0"; | |
7792 | } | |
7793 | return rval; | |
1b3c2c2d | 7794 | } |
1b3c2c2d | 7795 | |
4e5b002b EB |
7796 | if (v9_form) |
7797 | strcpy (string, "ba%*,pt\t%%xcc, "); | |
7798 | else | |
7799 | strcpy (string, "b%*\t"); | |
1b3c2c2d EB |
7800 | |
7801 | p = strchr (string, '\0'); | |
7802 | *p++ = '%'; | |
7803 | *p++ = 'l'; | |
8b98b5fd | 7804 | *p++ = '0'; |
1b3c2c2d | 7805 | *p++ = '%'; |
4e5b002b | 7806 | *p++ = '('; |
1b3c2c2d EB |
7807 | *p = '\0'; |
7808 | ||
7809 | return string; | |
7810 | } | |
7811 | ||
ab835497 | 7812 | /* Return the string to output a conditional branch to LABEL, which is |
c4ce6853 DE |
7813 | the operand number of the label. OP is the conditional expression. |
7814 | XEXP (OP, 0) is assumed to be a condition code register (integer or | |
7815 | floating point) and its mode specifies what kind of comparison we made. | |
61a55e8b | 7816 | |
1b3c2c2d EB |
7817 | DEST is the destination insn (i.e. the label), INSN is the source. |
7818 | ||
5e7a8ee0 | 7819 | REVERSED is nonzero if we should reverse the sense of the comparison. |
ab835497 | 7820 | |
4e5b002b | 7821 | ANNUL is nonzero if we should generate an annulling branch. */ |
ab835497 | 7822 | |
a6163c22 | 7823 | const char * |
fc27d102 | 7824 | output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, |
e1faf324 | 7825 | rtx_insn *insn) |
ab835497 | 7826 | { |
a6163c22 | 7827 | static char string[64]; |
ab835497 | 7828 | enum rtx_code code = GET_CODE (op); |
c4ce6853 | 7829 | rtx cc_reg = XEXP (op, 0); |
ef4bddc2 | 7830 | machine_mode mode = GET_MODE (cc_reg); |
0b82d204 JJ |
7831 | const char *labelno, *branch; |
7832 | int spaces = 8, far; | |
7833 | char *p; | |
7834 | ||
7835 | /* v9 branches are limited to +-1MB. If it is too far away, | |
7836 | change | |
7837 | ||
7838 | bne,pt %xcc, .LC30 | |
7839 | ||
7840 | to | |
7841 | ||
7842 | be,pn %xcc, .+12 | |
a6163c22 | 7843 | nop |
0b82d204 JJ |
7844 | ba .LC30 |
7845 | ||
7846 | and | |
7847 | ||
7848 | fbne,a,pn %fcc2, .LC29 | |
61a55e8b | 7849 | |
0b82d204 JJ |
7850 | to |
7851 | ||
7852 | fbe,pt %fcc2, .+16 | |
a6163c22 | 7853 | nop |
0b82d204 JJ |
7854 | ba .LC29 */ |
7855 | ||
883d9e0c | 7856 | far = TARGET_V9 && (get_attr_length (insn) >= 3); |
0b82d204 | 7857 | if (reversed ^ far) |
ab835497 | 7858 | { |
e267e177 RH |
7859 | /* Reversal of FP compares takes care -- an ordered compare |
7860 | becomes an unordered compare and vice versa. */ | |
4d449554 | 7861 | if (mode == CCFPmode || mode == CCFPEmode) |
7913f3d0 | 7862 | code = reverse_condition_maybe_unordered (code); |
ab835497 | 7863 | else |
e267e177 | 7864 | code = reverse_condition (code); |
ab835497 RK |
7865 | } |
7866 | ||
e267e177 RH |
7867 | /* Start by writing the branch condition. */ |
7868 | if (mode == CCFPmode || mode == CCFPEmode) | |
5850dc00 RH |
7869 | { |
7870 | switch (code) | |
7871 | { | |
7872 | case NE: | |
7873 | branch = "fbne"; | |
7874 | break; | |
7875 | case EQ: | |
7876 | branch = "fbe"; | |
7877 | break; | |
7878 | case GE: | |
7879 | branch = "fbge"; | |
7880 | break; | |
7881 | case GT: | |
7882 | branch = "fbg"; | |
7883 | break; | |
7884 | case LE: | |
7885 | branch = "fble"; | |
7886 | break; | |
7887 | case LT: | |
7888 | branch = "fbl"; | |
7889 | break; | |
7890 | case UNORDERED: | |
7891 | branch = "fbu"; | |
7892 | break; | |
7893 | case ORDERED: | |
7894 | branch = "fbo"; | |
7895 | break; | |
7896 | case UNGT: | |
7897 | branch = "fbug"; | |
7898 | break; | |
7899 | case UNLT: | |
7900 | branch = "fbul"; | |
7901 | break; | |
7902 | case UNEQ: | |
7903 | branch = "fbue"; | |
7904 | break; | |
7905 | case UNGE: | |
7906 | branch = "fbuge"; | |
7907 | break; | |
7908 | case UNLE: | |
7909 | branch = "fbule"; | |
7910 | break; | |
7911 | case LTGT: | |
7912 | branch = "fblg"; | |
7913 | break; | |
5850dc00 | 7914 | default: |
f5f7d171 | 7915 | gcc_unreachable (); |
5850dc00 RH |
7916 | } |
7917 | ||
7918 | /* ??? !v9: FP branches cannot be preceded by another floating point | |
7919 | insn. Because there is currently no concept of pre-delay slots, | |
7920 | we can fix this only by always emitting a nop before a floating | |
7921 | point branch. */ | |
7922 | ||
7923 | string[0] = '\0'; | |
7924 | if (! TARGET_V9) | |
7925 | strcpy (string, "nop\n\t"); | |
7926 | strcat (string, branch); | |
7927 | } | |
e267e177 | 7928 | else |
5850dc00 RH |
7929 | { |
7930 | switch (code) | |
7931 | { | |
7932 | case NE: | |
85729229 EB |
7933 | if (mode == CCVmode || mode == CCXVmode) |
7934 | branch = "bvs"; | |
7935 | else | |
7936 | branch = "bne"; | |
5850dc00 RH |
7937 | break; |
7938 | case EQ: | |
85729229 EB |
7939 | if (mode == CCVmode || mode == CCXVmode) |
7940 | branch = "bvc"; | |
7941 | else | |
7942 | branch = "be"; | |
5850dc00 RH |
7943 | break; |
7944 | case GE: | |
ff7e7ee0 | 7945 | if (mode == CCNZmode || mode == CCXNZmode) |
5850dc00 RH |
7946 | branch = "bpos"; |
7947 | else | |
7948 | branch = "bge"; | |
7949 | break; | |
7950 | case GT: | |
7951 | branch = "bg"; | |
7952 | break; | |
7953 | case LE: | |
7954 | branch = "ble"; | |
7955 | break; | |
7956 | case LT: | |
ff7e7ee0 | 7957 | if (mode == CCNZmode || mode == CCXNZmode) |
5850dc00 RH |
7958 | branch = "bneg"; |
7959 | else | |
7960 | branch = "bl"; | |
7961 | break; | |
7962 | case GEU: | |
7963 | branch = "bgeu"; | |
7964 | break; | |
7965 | case GTU: | |
7966 | branch = "bgu"; | |
7967 | break; | |
7968 | case LEU: | |
7969 | branch = "bleu"; | |
7970 | break; | |
7971 | case LTU: | |
7972 | branch = "blu"; | |
7973 | break; | |
5850dc00 | 7974 | default: |
f5f7d171 | 7975 | gcc_unreachable (); |
5850dc00 RH |
7976 | } |
7977 | strcpy (string, branch); | |
7978 | } | |
e267e177 | 7979 | spaces -= strlen (branch); |
0b82d204 | 7980 | p = strchr (string, '\0'); |
e267e177 | 7981 | |
ab835497 | 7982 | /* Now add the annulling, the label, and a possible noop. */ |
0b82d204 | 7983 | if (annul && ! far) |
e0d80184 | 7984 | { |
0b82d204 JJ |
7985 | strcpy (p, ",a"); |
7986 | p += 2; | |
e0d80184 DM |
7987 | spaces -= 2; |
7988 | } | |
ab835497 | 7989 | |
883d9e0c | 7990 | if (TARGET_V9) |
61a55e8b | 7991 | { |
c6b0465b | 7992 | rtx note; |
0b82d204 | 7993 | int v8 = 0; |
c6b0465b | 7994 | |
0b82d204 | 7995 | if (! far && insn && INSN_ADDRESSES_SET_P ()) |
e0d80184 | 7996 | { |
0b82d204 JJ |
7997 | int delta = (INSN_ADDRESSES (INSN_UID (dest)) |
7998 | - INSN_ADDRESSES (INSN_UID (insn))); | |
7999 | /* Leave some instructions for "slop". */ | |
8000 | if (delta < -260000 || delta >= 260000) | |
8001 | v8 = 1; | |
e0d80184 | 8002 | } |
c6b0465b | 8003 | |
ff7e7ee0 | 8004 | switch (mode) |
0b82d204 | 8005 | { |
4e10a5a7 RS |
8006 | case E_CCmode: |
8007 | case E_CCNZmode: | |
8008 | case E_CCCmode: | |
8009 | case E_CCVmode: | |
0b82d204 JJ |
8010 | labelno = "%%icc, "; |
8011 | if (v8) | |
8012 | labelno = ""; | |
ff7e7ee0 | 8013 | break; |
4e10a5a7 RS |
8014 | case E_CCXmode: |
8015 | case E_CCXNZmode: | |
8016 | case E_CCXCmode: | |
8017 | case E_CCXVmode: | |
ff7e7ee0 EB |
8018 | labelno = "%%xcc, "; |
8019 | gcc_assert (!v8); | |
8020 | break; | |
4e10a5a7 RS |
8021 | case E_CCFPmode: |
8022 | case E_CCFPEmode: | |
ff7e7ee0 EB |
8023 | { |
8024 | static char v9_fcc_labelno[] = "%%fccX, "; | |
8025 | /* Set the char indicating the number of the fcc reg to use. */ | |
8026 | v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; | |
8027 | labelno = v9_fcc_labelno; | |
8028 | if (v8) | |
8029 | { | |
8030 | gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG); | |
8031 | labelno = ""; | |
8032 | } | |
8033 | } | |
8034 | break; | |
8035 | default: | |
8036 | gcc_unreachable (); | |
0b82d204 JJ |
8037 | } |
8038 | ||
4f31cce8 | 8039 | if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) |
0b82d204 JJ |
8040 | { |
8041 | strcpy (p, | |
5fa396ad JH |
8042 | ((profile_probability::from_reg_br_prob_note (XINT (note, 0)) |
8043 | >= profile_probability::even ()) ^ far) | |
0b82d204 JJ |
8044 | ? ",pt" : ",pn"); |
8045 | p += 3; | |
8046 | spaces -= 3; | |
8047 | } | |
61a55e8b | 8048 | } |
883d9e0c EB |
8049 | else |
8050 | labelno = ""; | |
8051 | ||
e0d80184 | 8052 | if (spaces > 0) |
0b82d204 | 8053 | *p++ = '\t'; |
e0d80184 | 8054 | else |
0b82d204 JJ |
8055 | *p++ = ' '; |
8056 | strcpy (p, labelno); | |
8057 | p = strchr (p, '\0'); | |
8058 | if (far) | |
8059 | { | |
a6163c22 | 8060 | strcpy (p, ".+12\n\t nop\n\tb\t"); |
4e5b002b EB |
8061 | /* Skip the next insn if requested or |
8062 | if we know that it will be a nop. */ | |
8063 | if (annul || ! final_sequence) | |
0b82d204 | 8064 | p[3] = '6'; |
a6163c22 | 8065 | p += 14; |
0b82d204 JJ |
8066 | } |
8067 | *p++ = '%'; | |
8068 | *p++ = 'l'; | |
0b82d204 | 8069 | *p++ = label + '0'; |
4e5b002b EB |
8070 | *p++ = '%'; |
8071 | *p++ = '#'; | |
0b82d204 | 8072 | *p = '\0'; |
61a55e8b DE |
8073 | |
8074 | return string; | |
8075 | } | |
8076 | ||
47ac041c | 8077 | /* Emit a library call comparison between floating point X and Y. |
19047e4a EB |
8078 | COMPARISON is the operator to compare with (EQ, NE, GT, etc). |
8079 | Return the new operator to be used in the comparison sequence. | |
8080 | ||
47ac041c JJ |
8081 | TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode |
8082 | values as arguments instead of the TFmode registers themselves, | |
8083 | that's why we cannot call emit_float_lib_cmp. */ | |
19047e4a | 8084 | |
f90b7a5a | 8085 | rtx |
fc27d102 | 8086 | sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison) |
47ac041c | 8087 | { |
e77d72cb | 8088 | const char *qpfunc; |
390b17c2 | 8089 | rtx slot0, slot1, result, tem, tem2, libfunc; |
ef4bddc2 | 8090 | machine_mode mode; |
19047e4a | 8091 | enum rtx_code new_comparison; |
47ac041c JJ |
8092 | |
8093 | switch (comparison) | |
8094 | { | |
8095 | case EQ: | |
19047e4a | 8096 | qpfunc = (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq"); |
47ac041c JJ |
8097 | break; |
8098 | ||
8099 | case NE: | |
19047e4a | 8100 | qpfunc = (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne"); |
47ac041c JJ |
8101 | break; |
8102 | ||
8103 | case GT: | |
19047e4a | 8104 | qpfunc = (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt"); |
47ac041c JJ |
8105 | break; |
8106 | ||
8107 | case GE: | |
19047e4a | 8108 | qpfunc = (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge"); |
47ac041c JJ |
8109 | break; |
8110 | ||
8111 | case LT: | |
19047e4a | 8112 | qpfunc = (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt"); |
47ac041c JJ |
8113 | break; |
8114 | ||
8115 | case LE: | |
19047e4a | 8116 | qpfunc = (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle"); |
5c5c34a4 JJ |
8117 | break; |
8118 | ||
8119 | case ORDERED: | |
8120 | case UNORDERED: | |
8121 | case UNGT: | |
8122 | case UNLT: | |
8123 | case UNEQ: | |
8124 | case UNGE: | |
8125 | case UNLE: | |
8126 | case LTGT: | |
19047e4a | 8127 | qpfunc = (TARGET_ARCH64 ? "_Qp_cmp" : "_Q_cmp"); |
47ac041c JJ |
8128 | break; |
8129 | ||
8130 | default: | |
f5f7d171 | 8131 | gcc_unreachable (); |
47ac041c JJ |
8132 | } |
8133 | ||
5c5c34a4 | 8134 | if (TARGET_ARCH64) |
47ac041c | 8135 | { |
19047e4a | 8136 | if (MEM_P (x)) |
d333c3eb DM |
8137 | { |
8138 | tree expr = MEM_EXPR (x); | |
8139 | if (expr) | |
8140 | mark_addressable (expr); | |
8141 | slot0 = x; | |
8142 | } | |
19047e4a | 8143 | else |
5c5c34a4 | 8144 | { |
9474e8ab | 8145 | slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode)); |
c5d74498 | 8146 | emit_move_insn (slot0, x); |
5c5c34a4 | 8147 | } |
5c5c34a4 | 8148 | |
19047e4a | 8149 | if (MEM_P (y)) |
d333c3eb DM |
8150 | { |
8151 | tree expr = MEM_EXPR (y); | |
8152 | if (expr) | |
8153 | mark_addressable (expr); | |
8154 | slot1 = y; | |
8155 | } | |
19047e4a | 8156 | else |
5c5c34a4 | 8157 | { |
9474e8ab | 8158 | slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode)); |
c5d74498 | 8159 | emit_move_insn (slot1, y); |
5c5c34a4 | 8160 | } |
47ac041c | 8161 | |
390b17c2 RE |
8162 | libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc); |
8163 | emit_library_call (libfunc, LCT_NORMAL, | |
db69559b | 8164 | DImode, |
5c5c34a4 JJ |
8165 | XEXP (slot0, 0), Pmode, |
8166 | XEXP (slot1, 0), Pmode); | |
5c5c34a4 JJ |
8167 | mode = DImode; |
8168 | } | |
8169 | else | |
47ac041c | 8170 | { |
390b17c2 RE |
8171 | libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc); |
8172 | emit_library_call (libfunc, LCT_NORMAL, | |
db69559b | 8173 | SImode, |
5c5c34a4 | 8174 | x, TFmode, y, TFmode); |
5c5c34a4 | 8175 | mode = SImode; |
47ac041c JJ |
8176 | } |
8177 | ||
47ac041c JJ |
8178 | |
8179 | /* Immediately move the result of the libcall into a pseudo | |
8180 | register so reload doesn't clobber the value if it needs | |
8181 | the return register for a spill reg. */ | |
5c5c34a4 | 8182 | result = gen_reg_rtx (mode); |
390b17c2 | 8183 | emit_move_insn (result, hard_libcall_value (mode, libfunc)); |
47ac041c | 8184 | |
5c5c34a4 JJ |
8185 | switch (comparison) |
8186 | { | |
8187 | default: | |
f90b7a5a | 8188 | return gen_rtx_NE (VOIDmode, result, const0_rtx); |
5c5c34a4 JJ |
8189 | case ORDERED: |
8190 | case UNORDERED: | |
19047e4a | 8191 | new_comparison = (comparison == UNORDERED ? EQ : NE); |
f90b7a5a | 8192 | return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, GEN_INT(3)); |
5c5c34a4 JJ |
8193 | case UNGT: |
8194 | case UNGE: | |
19047e4a | 8195 | new_comparison = (comparison == UNGT ? GT : NE); |
f90b7a5a | 8196 | return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, const1_rtx); |
5c5c34a4 | 8197 | case UNLE: |
f90b7a5a | 8198 | return gen_rtx_NE (VOIDmode, result, const2_rtx); |
5c5c34a4 JJ |
8199 | case UNLT: |
8200 | tem = gen_reg_rtx (mode); | |
8201 | if (TARGET_ARCH32) | |
8202 | emit_insn (gen_andsi3 (tem, result, const1_rtx)); | |
8203 | else | |
8204 | emit_insn (gen_anddi3 (tem, result, const1_rtx)); | |
f90b7a5a | 8205 | return gen_rtx_NE (VOIDmode, tem, const0_rtx); |
5c5c34a4 JJ |
8206 | case UNEQ: |
8207 | case LTGT: | |
8208 | tem = gen_reg_rtx (mode); | |
8209 | if (TARGET_ARCH32) | |
8210 | emit_insn (gen_addsi3 (tem, result, const1_rtx)); | |
8211 | else | |
8212 | emit_insn (gen_adddi3 (tem, result, const1_rtx)); | |
8213 | tem2 = gen_reg_rtx (mode); | |
8214 | if (TARGET_ARCH32) | |
8215 | emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); | |
8216 | else | |
8217 | emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); | |
19047e4a | 8218 | new_comparison = (comparison == UNEQ ? EQ : NE); |
f90b7a5a | 8219 | return gen_rtx_fmt_ee (new_comparison, VOIDmode, tem2, const0_rtx); |
5c5c34a4 | 8220 | } |
19047e4a | 8221 | |
f90b7a5a | 8222 | gcc_unreachable (); |
47ac041c | 8223 | } |
5c5c34a4 | 8224 | |
d88e57d1 RH |
8225 | /* Generate an unsigned DImode to FP conversion. This is the same code |
8226 | optabs would emit if we didn't have TFmode patterns. */ | |
8227 | ||
8228 | void | |
ef4bddc2 | 8229 | sparc_emit_floatunsdi (rtx *operands, machine_mode mode) |
d88e57d1 | 8230 | { |
19f8b229 | 8231 | rtx i0, i1, f0, in, out; |
d88e57d1 RH |
8232 | |
8233 | out = operands[0]; | |
8234 | in = force_reg (DImode, operands[1]); | |
19f8b229 TS |
8235 | rtx_code_label *neglab = gen_label_rtx (); |
8236 | rtx_code_label *donelab = gen_label_rtx (); | |
d88e57d1 RH |
8237 | i0 = gen_reg_rtx (DImode); |
8238 | i1 = gen_reg_rtx (DImode); | |
8239 | f0 = gen_reg_rtx (mode); | |
8240 | ||
8241 | emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); | |
8242 | ||
f7df4a84 | 8243 | emit_insn (gen_rtx_SET (out, gen_rtx_FLOAT (mode, in))); |
d88e57d1 RH |
8244 | emit_jump_insn (gen_jump (donelab)); |
8245 | emit_barrier (); | |
8246 | ||
8247 | emit_label (neglab); | |
8248 | ||
8249 | emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); | |
8250 | emit_insn (gen_anddi3 (i1, in, const1_rtx)); | |
8251 | emit_insn (gen_iordi3 (i0, i0, i1)); | |
f7df4a84 RS |
8252 | emit_insn (gen_rtx_SET (f0, gen_rtx_FLOAT (mode, i0))); |
8253 | emit_insn (gen_rtx_SET (out, gen_rtx_PLUS (mode, f0, f0))); | |
d88e57d1 RH |
8254 | |
8255 | emit_label (donelab); | |
8256 | } | |
8257 | ||
b178305d EB |
8258 | /* Generate an FP to unsigned DImode conversion. This is the same code |
8259 | optabs would emit if we didn't have TFmode patterns. */ | |
8260 | ||
8261 | void | |
ef4bddc2 | 8262 | sparc_emit_fixunsdi (rtx *operands, machine_mode mode) |
b178305d | 8263 | { |
19f8b229 | 8264 | rtx i0, i1, f0, in, out, limit; |
b178305d EB |
8265 | |
8266 | out = operands[0]; | |
8267 | in = force_reg (mode, operands[1]); | |
19f8b229 TS |
8268 | rtx_code_label *neglab = gen_label_rtx (); |
8269 | rtx_code_label *donelab = gen_label_rtx (); | |
b178305d EB |
8270 | i0 = gen_reg_rtx (DImode); |
8271 | i1 = gen_reg_rtx (DImode); | |
8272 | limit = gen_reg_rtx (mode); | |
8273 | f0 = gen_reg_rtx (mode); | |
8274 | ||
8275 | emit_move_insn (limit, | |
555affd7 | 8276 | const_double_from_real_value ( |
b178305d EB |
8277 | REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode)); |
8278 | emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab); | |
8279 | ||
f7df4a84 | 8280 | emit_insn (gen_rtx_SET (out, |
b178305d EB |
8281 | gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in)))); |
8282 | emit_jump_insn (gen_jump (donelab)); | |
8283 | emit_barrier (); | |
8284 | ||
8285 | emit_label (neglab); | |
8286 | ||
f7df4a84 RS |
8287 | emit_insn (gen_rtx_SET (f0, gen_rtx_MINUS (mode, in, limit))); |
8288 | emit_insn (gen_rtx_SET (i0, | |
b178305d EB |
8289 | gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0)))); |
8290 | emit_insn (gen_movdi (i1, const1_rtx)); | |
8291 | emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63))); | |
8292 | emit_insn (gen_xordi3 (out, i0, i1)); | |
8293 | ||
8294 | emit_label (donelab); | |
8295 | } | |
8296 | ||
8b98b5fd DM |
8297 | /* Return the string to output a compare and branch instruction to DEST. |
8298 | DEST is the destination insn (i.e. the label), INSN is the source, | |
8299 | and OP is the conditional expression. */ | |
8300 | ||
8301 | const char * | |
e1faf324 | 8302 | output_cbcond (rtx op, rtx dest, rtx_insn *insn) |
8b98b5fd | 8303 | { |
ef4bddc2 | 8304 | machine_mode mode = GET_MODE (XEXP (op, 0)); |
8b98b5fd DM |
8305 | enum rtx_code code = GET_CODE (op); |
8306 | const char *cond_str, *tmpl; | |
8307 | int far, emit_nop, len; | |
8308 | static char string[64]; | |
8309 | char size_char; | |
8310 | ||
8311 | /* Compare and Branch is limited to +-2KB. If it is too far away, | |
8312 | change | |
8313 | ||
8314 | cxbne X, Y, .LC30 | |
8315 | ||
8316 | to | |
8317 | ||
8318 | cxbe X, Y, .+16 | |
8319 | nop | |
8320 | ba,pt xcc, .LC30 | |
8321 | nop */ | |
8322 | ||
8323 | len = get_attr_length (insn); | |
8324 | ||
8325 | far = len == 4; | |
8326 | emit_nop = len == 2; | |
8327 | ||
8328 | if (far) | |
8329 | code = reverse_condition (code); | |
8330 | ||
8331 | size_char = ((mode == SImode) ? 'w' : 'x'); | |
8332 | ||
8333 | switch (code) | |
8334 | { | |
8335 | case NE: | |
8336 | cond_str = "ne"; | |
8337 | break; | |
8338 | ||
8339 | case EQ: | |
8340 | cond_str = "e"; | |
8341 | break; | |
8342 | ||
8343 | case GE: | |
ff7e7ee0 | 8344 | cond_str = "ge"; |
8b98b5fd DM |
8345 | break; |
8346 | ||
8347 | case GT: | |
8348 | cond_str = "g"; | |
8349 | break; | |
8350 | ||
8351 | case LE: | |
8352 | cond_str = "le"; | |
8353 | break; | |
8354 | ||
8355 | case LT: | |
ff7e7ee0 | 8356 | cond_str = "l"; |
8b98b5fd DM |
8357 | break; |
8358 | ||
8359 | case GEU: | |
8360 | cond_str = "cc"; | |
8361 | break; | |
8362 | ||
8363 | case GTU: | |
8364 | cond_str = "gu"; | |
8365 | break; | |
8366 | ||
8367 | case LEU: | |
8368 | cond_str = "leu"; | |
8369 | break; | |
8370 | ||
8371 | case LTU: | |
8372 | cond_str = "cs"; | |
8373 | break; | |
8374 | ||
8375 | default: | |
8376 | gcc_unreachable (); | |
8377 | } | |
8378 | ||
8379 | if (far) | |
8380 | { | |
8381 | int veryfar = 1, delta; | |
8382 | ||
8383 | if (INSN_ADDRESSES_SET_P ()) | |
8384 | { | |
8385 | delta = (INSN_ADDRESSES (INSN_UID (dest)) | |
8386 | - INSN_ADDRESSES (INSN_UID (insn))); | |
8387 | /* Leave some instructions for "slop". */ | |
8388 | if (delta >= -260000 && delta < 260000) | |
8389 | veryfar = 0; | |
8390 | } | |
8391 | ||
8392 | if (veryfar) | |
8393 | tmpl = "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop"; | |
8394 | else | |
8395 | tmpl = "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop"; | |
8396 | } | |
8397 | else | |
8398 | { | |
8399 | if (emit_nop) | |
8400 | tmpl = "c%cb%s\t%%1, %%2, %%3\n\tnop"; | |
8401 | else | |
8402 | tmpl = "c%cb%s\t%%1, %%2, %%3"; | |
8403 | } | |
8404 | ||
8405 | snprintf (string, sizeof(string), tmpl, size_char, cond_str); | |
8406 | ||
8407 | return string; | |
8408 | } | |
8409 | ||
61a55e8b DE |
8410 | /* Return the string to output a conditional branch to LABEL, testing |
8411 | register REG. LABEL is the operand number of the label; REG is the | |
8412 | operand number of the reg. OP is the conditional expression. The mode | |
8413 | of REG says what kind of comparison we made. | |
8414 | ||
1b3c2c2d EB |
8415 | DEST is the destination insn (i.e. the label), INSN is the source. |
8416 | ||
5e7a8ee0 | 8417 | REVERSED is nonzero if we should reverse the sense of the comparison. |
61a55e8b | 8418 | |
4e5b002b | 8419 | ANNUL is nonzero if we should generate an annulling branch. */ |
61a55e8b | 8420 | |
a6163c22 | 8421 | const char * |
fc27d102 | 8422 | output_v9branch (rtx op, rtx dest, int reg, int label, int reversed, |
e1faf324 | 8423 | int annul, rtx_insn *insn) |
61a55e8b | 8424 | { |
a6163c22 | 8425 | static char string[64]; |
61a55e8b | 8426 | enum rtx_code code = GET_CODE (op); |
ef4bddc2 | 8427 | machine_mode mode = GET_MODE (XEXP (op, 0)); |
e0d80184 | 8428 | rtx note; |
0b82d204 JJ |
8429 | int far; |
8430 | char *p; | |
8431 | ||
8432 | /* branch on register are limited to +-128KB. If it is too far away, | |
8433 | change | |
4900aa61 | 8434 | |
0b82d204 | 8435 | brnz,pt %g1, .LC30 |
4900aa61 | 8436 | |
0b82d204 | 8437 | to |
4900aa61 | 8438 | |
0b82d204 | 8439 | brz,pn %g1, .+12 |
a6163c22 | 8440 | nop |
0b82d204 | 8441 | ba,pt %xcc, .LC30 |
4900aa61 | 8442 | |
0b82d204 | 8443 | and |
4900aa61 | 8444 | |
0b82d204 | 8445 | brgez,a,pn %o1, .LC29 |
4900aa61 | 8446 | |
0b82d204 | 8447 | to |
4900aa61 | 8448 | |
0b82d204 | 8449 | brlz,pt %o1, .+16 |
a6163c22 | 8450 | nop |
0b82d204 JJ |
8451 | ba,pt %xcc, .LC29 */ |
8452 | ||
8453 | far = get_attr_length (insn) >= 3; | |
61a55e8b DE |
8454 | |
8455 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
0b82d204 JJ |
8456 | if (reversed ^ far) |
8457 | code = reverse_condition (code); | |
61a55e8b | 8458 | |
a7faf57b | 8459 | /* Only 64-bit versions of these instructions exist. */ |
f5f7d171 | 8460 | gcc_assert (mode == DImode); |
61a55e8b DE |
8461 | |
8462 | /* Start by writing the branch condition. */ | |
8463 | ||
8464 | switch (code) | |
8465 | { | |
8466 | case NE: | |
8467 | strcpy (string, "brnz"); | |
8468 | break; | |
8469 | ||
8470 | case EQ: | |
8471 | strcpy (string, "brz"); | |
8472 | break; | |
8473 | ||
8474 | case GE: | |
8475 | strcpy (string, "brgez"); | |
8476 | break; | |
8477 | ||
8478 | case LT: | |
8479 | strcpy (string, "brlz"); | |
8480 | break; | |
8481 | ||
8482 | case LE: | |
8483 | strcpy (string, "brlez"); | |
8484 | break; | |
8485 | ||
8486 | case GT: | |
8487 | strcpy (string, "brgz"); | |
8488 | break; | |
8489 | ||
8490 | default: | |
f5f7d171 | 8491 | gcc_unreachable (); |
61a55e8b DE |
8492 | } |
8493 | ||
0b82d204 JJ |
8494 | p = strchr (string, '\0'); |
8495 | ||
61a55e8b | 8496 | /* Now add the annulling, reg, label, and nop. */ |
0b82d204 | 8497 | if (annul && ! far) |
e0d80184 | 8498 | { |
0b82d204 JJ |
8499 | strcpy (p, ",a"); |
8500 | p += 2; | |
e0d80184 | 8501 | } |
61a55e8b | 8502 | |
4f31cce8 | 8503 | if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) |
e0d80184 | 8504 | { |
0b82d204 | 8505 | strcpy (p, |
5fa396ad JH |
8506 | ((profile_probability::from_reg_br_prob_note (XINT (note, 0)) |
8507 | >= profile_probability::even ()) ^ far) | |
0b82d204 JJ |
8508 | ? ",pt" : ",pn"); |
8509 | p += 3; | |
e0d80184 | 8510 | } |
61a55e8b | 8511 | |
0b82d204 JJ |
8512 | *p = p < string + 8 ? '\t' : ' '; |
8513 | p++; | |
8514 | *p++ = '%'; | |
8515 | *p++ = '0' + reg; | |
8516 | *p++ = ','; | |
8517 | *p++ = ' '; | |
8518 | if (far) | |
8519 | { | |
8520 | int veryfar = 1, delta; | |
8521 | ||
8522 | if (INSN_ADDRESSES_SET_P ()) | |
8523 | { | |
8524 | delta = (INSN_ADDRESSES (INSN_UID (dest)) | |
8525 | - INSN_ADDRESSES (INSN_UID (insn))); | |
8526 | /* Leave some instructions for "slop". */ | |
8527 | if (delta >= -260000 && delta < 260000) | |
8528 | veryfar = 0; | |
8529 | } | |
8530 | ||
a6163c22 | 8531 | strcpy (p, ".+12\n\t nop\n\t"); |
4e5b002b EB |
8532 | /* Skip the next insn if requested or |
8533 | if we know that it will be a nop. */ | |
8534 | if (annul || ! final_sequence) | |
0b82d204 | 8535 | p[3] = '6'; |
a6163c22 | 8536 | p += 12; |
0b82d204 JJ |
8537 | if (veryfar) |
8538 | { | |
8539 | strcpy (p, "b\t"); | |
8540 | p += 2; | |
8541 | } | |
8542 | else | |
8543 | { | |
8544 | strcpy (p, "ba,pt\t%%xcc, "); | |
8545 | p += 13; | |
8546 | } | |
8547 | } | |
8548 | *p++ = '%'; | |
8549 | *p++ = 'l'; | |
8550 | *p++ = '0' + label; | |
4e5b002b EB |
8551 | *p++ = '%'; |
8552 | *p++ = '#'; | |
0b82d204 | 8553 | *p = '\0'; |
ab835497 | 8554 | |
ab835497 RK |
8555 | return string; |
8556 | } | |
8557 | ||
e48addee JJ |
8558 | /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. |
8559 | Such instructions cannot be used in the delay slot of return insn on v9. | |
8560 | If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. | |
8561 | */ | |
284d86e9 | 8562 | |
e48addee | 8563 | static int |
fc27d102 | 8564 | epilogue_renumber (register rtx *where, int test) |
284d86e9 | 8565 | { |
e48addee JJ |
8566 | register const char *fmt; |
8567 | register int i; | |
8568 | register enum rtx_code code; | |
8569 | ||
8570 | if (*where == 0) | |
8571 | return 0; | |
8572 | ||
8573 | code = GET_CODE (*where); | |
284d86e9 JC |
8574 | |
8575 | switch (code) | |
8576 | { | |
284d86e9 | 8577 | case REG: |
e48addee JJ |
8578 | if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ |
8579 | return 1; | |
8580 | if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) | |
f1c25d3b | 8581 | *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); |
fbedd170 | 8582 | /* fallthrough */ |
e48addee JJ |
8583 | case SCRATCH: |
8584 | case CC0: | |
8585 | case PC: | |
284d86e9 | 8586 | case CONST_INT: |
eaac029f | 8587 | case CONST_WIDE_INT: |
284d86e9 | 8588 | case CONST_DOUBLE: |
e48addee | 8589 | return 0; |
76a7c776 | 8590 | |
09ebda1b SC |
8591 | /* Do not replace the frame pointer with the stack pointer because |
8592 | it can cause the delayed instruction to load below the stack. | |
8593 | This occurs when instructions like: | |
8594 | ||
8595 | (set (reg/i:SI 24 %i0) | |
8596 | (mem/f:SI (plus:SI (reg/f:SI 30 %fp) | |
8597 | (const_int -20 [0xffffffec])) 0)) | |
8598 | ||
8599 | are in the return delayed slot. */ | |
8600 | case PLUS: | |
8601 | if (GET_CODE (XEXP (*where, 0)) == REG | |
563c12b0 | 8602 | && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM |
09ebda1b SC |
8603 | && (GET_CODE (XEXP (*where, 1)) != CONST_INT |
8604 | || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS)) | |
8605 | return 1; | |
8606 | break; | |
8607 | ||
8608 | case MEM: | |
8609 | if (SPARC_STACK_BIAS | |
8610 | && GET_CODE (XEXP (*where, 0)) == REG | |
563c12b0 | 8611 | && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM) |
09ebda1b SC |
8612 | return 1; |
8613 | break; | |
8614 | ||
76a7c776 DM |
8615 | default: |
8616 | break; | |
e48addee | 8617 | } |
284d86e9 | 8618 | |
e48addee | 8619 | fmt = GET_RTX_FORMAT (code); |
284d86e9 | 8620 | |
e48addee JJ |
8621 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
8622 | { | |
8623 | if (fmt[i] == 'E') | |
8624 | { | |
8625 | register int j; | |
8626 | for (j = XVECLEN (*where, i) - 1; j >= 0; j--) | |
8627 | if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) | |
8628 | return 1; | |
8629 | } | |
8630 | else if (fmt[i] == 'e' | |
8631 | && epilogue_renumber (&(XEXP (*where, i)), test)) | |
8632 | return 1; | |
284d86e9 | 8633 | } |
e48addee | 8634 | return 0; |
284d86e9 | 8635 | } |
ab835497 RK |
8636 | \f |
8637 | /* Leaf functions and non-leaf functions have different needs. */ | |
8638 | ||
8b60264b | 8639 | static const int |
ab835497 RK |
8640 | reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; |
8641 | ||
8b60264b | 8642 | static const int |
ab835497 RK |
8643 | reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; |
8644 | ||
8b60264b | 8645 | static const int *const reg_alloc_orders[] = { |
ab835497 RK |
8646 | reg_leaf_alloc_order, |
8647 | reg_nonleaf_alloc_order}; | |
8648 | ||
8649 | void | |
fc27d102 | 8650 | order_regs_for_local_alloc (void) |
ab835497 RK |
8651 | { |
8652 | static int last_order_nonleaf = 1; | |
8653 | ||
6fb5fa3c | 8654 | if (df_regs_ever_live_p (15) != last_order_nonleaf) |
ab835497 RK |
8655 | { |
8656 | last_order_nonleaf = !last_order_nonleaf; | |
2e09e75a | 8657 | memcpy ((char *) reg_alloc_order, |
8b60264b | 8658 | (const char *) reg_alloc_orders[last_order_nonleaf], |
2e09e75a | 8659 | FIRST_PSEUDO_REGISTER * sizeof (int)); |
ab835497 RK |
8660 | } |
8661 | } | |
8662 | \f | |
e0d80184 | 8663 | /* Return 1 if REG and MEM are legitimate enough to allow the various |
dc7342d2 | 8664 | MEM<-->REG splits to be run. */ |
e0d80184 DM |
8665 | |
8666 | int | |
dc7342d2 | 8667 | sparc_split_reg_mem_legitimate (rtx reg, rtx mem) |
e0d80184 | 8668 | { |
e0d80184 | 8669 | /* Punt if we are here by mistake. */ |
f5f7d171 | 8670 | gcc_assert (reload_completed); |
e0d80184 DM |
8671 | |
8672 | /* We must have an offsettable memory reference. */ | |
dc7342d2 | 8673 | if (!offsettable_memref_p (mem)) |
e0d80184 DM |
8674 | return 0; |
8675 | ||
8676 | /* If we have legitimate args for ldd/std, we do not want | |
8677 | the split to happen. */ | |
dc7342d2 | 8678 | if ((REGNO (reg) % 2) == 0 && mem_min_alignment (mem, 8)) |
e0d80184 DM |
8679 | return 0; |
8680 | ||
8681 | /* Success. */ | |
8682 | return 1; | |
8683 | } | |
8684 | ||
dc7342d2 EB |
8685 | /* Split a REG <-- MEM move into a pair of moves in MODE. */ |
8686 | ||
8687 | void | |
8688 | sparc_split_reg_mem (rtx dest, rtx src, machine_mode mode) | |
8689 | { | |
8690 | rtx high_part = gen_highpart (mode, dest); | |
8691 | rtx low_part = gen_lowpart (mode, dest); | |
8692 | rtx word0 = adjust_address (src, mode, 0); | |
8693 | rtx word1 = adjust_address (src, mode, 4); | |
8694 | ||
8695 | if (reg_overlap_mentioned_p (high_part, word1)) | |
8696 | { | |
8697 | emit_move_insn_1 (low_part, word1); | |
8698 | emit_move_insn_1 (high_part, word0); | |
8699 | } | |
8700 | else | |
8701 | { | |
8702 | emit_move_insn_1 (high_part, word0); | |
8703 | emit_move_insn_1 (low_part, word1); | |
8704 | } | |
8705 | } | |
8706 | ||
8707 | /* Split a MEM <-- REG move into a pair of moves in MODE. */ | |
8708 | ||
8709 | void | |
8710 | sparc_split_mem_reg (rtx dest, rtx src, machine_mode mode) | |
8711 | { | |
8712 | rtx word0 = adjust_address (dest, mode, 0); | |
8713 | rtx word1 = adjust_address (dest, mode, 4); | |
8714 | rtx high_part = gen_highpart (mode, src); | |
8715 | rtx low_part = gen_lowpart (mode, src); | |
8716 | ||
8717 | emit_move_insn_1 (word0, high_part); | |
8718 | emit_move_insn_1 (word1, low_part); | |
8719 | } | |
8720 | ||
8721 | /* Like sparc_split_reg_mem_legitimate but for REG <--> REG moves. */ | |
b1fc9f8b DM |
8722 | |
8723 | int | |
dc7342d2 | 8724 | sparc_split_reg_reg_legitimate (rtx reg1, rtx reg2) |
b1fc9f8b | 8725 | { |
dc7342d2 EB |
8726 | /* Punt if we are here by mistake. */ |
8727 | gcc_assert (reload_completed); | |
b1fc9f8b DM |
8728 | |
8729 | if (GET_CODE (reg1) == SUBREG) | |
8730 | reg1 = SUBREG_REG (reg1); | |
8731 | if (GET_CODE (reg1) != REG) | |
8732 | return 0; | |
dc7342d2 | 8733 | const int regno1 = REGNO (reg1); |
b1fc9f8b DM |
8734 | |
8735 | if (GET_CODE (reg2) == SUBREG) | |
8736 | reg2 = SUBREG_REG (reg2); | |
8737 | if (GET_CODE (reg2) != REG) | |
8738 | return 0; | |
dc7342d2 | 8739 | const int regno2 = REGNO (reg2); |
b1fc9f8b DM |
8740 | |
8741 | if (SPARC_INT_REG_P (regno1) && SPARC_INT_REG_P (regno2)) | |
8742 | return 1; | |
8743 | ||
bb12a72a DM |
8744 | if (TARGET_VIS3) |
8745 | { | |
8746 | if ((SPARC_INT_REG_P (regno1) && SPARC_FP_REG_P (regno2)) | |
8747 | || (SPARC_FP_REG_P (regno1) && SPARC_INT_REG_P (regno2))) | |
8748 | return 1; | |
8749 | } | |
8750 | ||
b1fc9f8b DM |
8751 | return 0; |
8752 | } | |
8753 | ||
dc7342d2 EB |
8754 | /* Split a REG <--> REG move into a pair of moves in MODE. */ |
8755 | ||
8756 | void | |
8757 | sparc_split_reg_reg (rtx dest, rtx src, machine_mode mode) | |
8758 | { | |
8759 | rtx dest1 = gen_highpart (mode, dest); | |
8760 | rtx dest2 = gen_lowpart (mode, dest); | |
8761 | rtx src1 = gen_highpart (mode, src); | |
8762 | rtx src2 = gen_lowpart (mode, src); | |
8763 | ||
8764 | /* Now emit using the real source and destination we found, swapping | |
8765 | the order if we detect overlap. */ | |
8766 | if (reg_overlap_mentioned_p (dest1, src2)) | |
8767 | { | |
8768 | emit_move_insn_1 (dest2, src2); | |
8769 | emit_move_insn_1 (dest1, src1); | |
8770 | } | |
8771 | else | |
8772 | { | |
8773 | emit_move_insn_1 (dest1, src1); | |
8774 | emit_move_insn_1 (dest2, src2); | |
8775 | } | |
8776 | } | |
8777 | ||
35016322 | 8778 | /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. |
4900aa61 | 8779 | This makes them candidates for using ldd and std insns. |
35016322 | 8780 | |
bfd6bc60 | 8781 | Note reg1 and reg2 *must* be hard registers. */ |
35016322 JW |
8782 | |
8783 | int | |
fc27d102 | 8784 | registers_ok_for_ldd_peep (rtx reg1, rtx reg2) |
35016322 | 8785 | { |
35016322 | 8786 | /* We might have been passed a SUBREG. */ |
4900aa61 | 8787 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) |
35016322 JW |
8788 | return 0; |
8789 | ||
35016322 JW |
8790 | if (REGNO (reg1) % 2 != 0) |
8791 | return 0; | |
8792 | ||
4900aa61 | 8793 | /* Integer ldd is deprecated in SPARC V9 */ |
5a53588f | 8794 | if (TARGET_V9 && SPARC_INT_REG_P (REGNO (reg1))) |
4900aa61 | 8795 | return 0; |
bfd6bc60 | 8796 | |
35016322 | 8797 | return (REGNO (reg1) == REGNO (reg2) - 1); |
35016322 JW |
8798 | } |
8799 | ||
2aad5d68 | 8800 | /* Return 1 if the addresses in mem1 and mem2 are suitable for use in |
303f8933 | 8801 | an ldd or std insn. |
4900aa61 | 8802 | |
2aad5d68 DN |
8803 | This can only happen when addr1 and addr2, the addresses in mem1 |
8804 | and mem2, are consecutive memory locations (addr1 + 4 == addr2). | |
303f8933 DN |
8805 | addr1 must also be aligned on a 64-bit boundary. |
8806 | ||
8807 | Also iff dependent_reg_rtx is not null it should not be used to | |
8808 | compute the address for mem1, i.e. we cannot optimize a sequence | |
8809 | like: | |
8810 | ld [%o0], %o0 | |
8811 | ld [%o0 + 4], %o1 | |
8812 | to | |
bcdd764b | 8813 | ldd [%o0], %o0 |
0acf409f DM |
8814 | nor: |
8815 | ld [%g3 + 4], %g3 | |
8816 | ld [%g3], %g2 | |
8817 | to | |
8818 | ldd [%g3], %g2 | |
8819 | ||
8820 | But, note that the transformation from: | |
8821 | ld [%g2 + 4], %g3 | |
8822 | ld [%g2], %g2 | |
8823 | to | |
8824 | ldd [%g2], %g2 | |
8825 | is perfectly fine. Thus, the peephole2 patterns always pass us | |
8826 | the destination register of the first load, never the second one. | |
8827 | ||
303f8933 DN |
8828 | For stores we don't have a similar problem, so dependent_reg_rtx is |
8829 | NULL_RTX. */ | |
35016322 JW |
8830 | |
8831 | int | |
fc27d102 | 8832 | mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx) |
35016322 | 8833 | { |
2aad5d68 | 8834 | rtx addr1, addr2; |
0d587737 | 8835 | unsigned int reg1; |
6a151f87 | 8836 | HOST_WIDE_INT offset1; |
35016322 | 8837 | |
303f8933 DN |
8838 | /* The mems cannot be volatile. */ |
8839 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
8840 | return 0; | |
2aad5d68 | 8841 | |
303f8933 | 8842 | /* MEM1 should be aligned on a 64-bit boundary. */ |
2aad5d68 DN |
8843 | if (MEM_ALIGN (mem1) < 64) |
8844 | return 0; | |
4900aa61 | 8845 | |
303f8933 DN |
8846 | addr1 = XEXP (mem1, 0); |
8847 | addr2 = XEXP (mem2, 0); | |
4900aa61 | 8848 | |
35016322 JW |
8849 | /* Extract a register number and offset (if used) from the first addr. */ |
8850 | if (GET_CODE (addr1) == PLUS) | |
8851 | { | |
8852 | /* If not a REG, return zero. */ | |
8853 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
8854 | return 0; | |
8855 | else | |
8856 | { | |
8857 | reg1 = REGNO (XEXP (addr1, 0)); | |
8858 | /* The offset must be constant! */ | |
8859 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
8860 | return 0; | |
8861 | offset1 = INTVAL (XEXP (addr1, 1)); | |
8862 | } | |
8863 | } | |
8864 | else if (GET_CODE (addr1) != REG) | |
8865 | return 0; | |
8866 | else | |
8867 | { | |
8868 | reg1 = REGNO (addr1); | |
8869 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
8870 | offset1 = 0; | |
8871 | } | |
8872 | ||
8873 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
8874 | if (GET_CODE (addr2) != PLUS) | |
8875 | return 0; | |
8876 | ||
8877 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
8878 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
8879 | return 0; | |
8880 | ||
35016322 JW |
8881 | if (reg1 != REGNO (XEXP (addr2, 0))) |
8882 | return 0; | |
8883 | ||
303f8933 DN |
8884 | if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx)) |
8885 | return 0; | |
4900aa61 EB |
8886 | |
8887 | /* The first offset must be evenly divisible by 8 to ensure the | |
a7faf57b | 8888 | address is 64-bit aligned. */ |
35016322 JW |
8889 | if (offset1 % 8 != 0) |
8890 | return 0; | |
8891 | ||
8892 | /* The offset for the second addr must be 4 more than the first addr. */ | |
8893 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) | |
8894 | return 0; | |
8895 | ||
8896 | /* All the tests passed. addr1 and addr2 are valid for ldd and std | |
8897 | instructions. */ | |
8898 | return 1; | |
8899 | } | |
7c56249d | 8900 | |
b5ccb9ed EB |
8901 | /* Return the widened memory access made of MEM1 and MEM2 in MODE. */ |
8902 | ||
8903 | rtx | |
ef4bddc2 | 8904 | widen_mem_for_ldd_peep (rtx mem1, rtx mem2, machine_mode mode) |
b5ccb9ed EB |
8905 | { |
8906 | rtx x = widen_memory_access (mem1, mode, 0); | |
8907 | MEM_NOTRAP_P (x) = MEM_NOTRAP_P (mem1) && MEM_NOTRAP_P (mem2); | |
8908 | return x; | |
8909 | } | |
8910 | ||
157891a3 EB |
8911 | /* Return 1 if reg is a pseudo, or is the first register in |
8912 | a hard register pair. This makes it suitable for use in | |
7c56249d JL |
8913 | ldd and std insns. */ |
8914 | ||
8915 | int | |
fc27d102 | 8916 | register_ok_for_ldd (rtx reg) |
7c56249d | 8917 | { |
7c56249d | 8918 | /* We might have been passed a SUBREG. */ |
157891a3 | 8919 | if (!REG_P (reg)) |
7c56249d JL |
8920 | return 0; |
8921 | ||
8922 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
8923 | return (REGNO (reg) % 2 == 0); | |
157891a3 EB |
8924 | |
8925 | return 1; | |
8926 | } | |
8927 | ||
9106d8d2 DM |
8928 | /* Return 1 if OP, a MEM, has an address which is known to be |
8929 | aligned to an 8-byte boundary. */ | |
157891a3 EB |
8930 | |
8931 | int | |
8932 | memory_ok_for_ldd (rtx op) | |
8933 | { | |
9106d8d2 DM |
8934 | /* In 64-bit mode, we assume that the address is word-aligned. */ |
8935 | if (TARGET_ARCH32 && !mem_min_alignment (op, 8)) | |
8936 | return 0; | |
157891a3 | 8937 | |
9106d8d2 DM |
8938 | if (! can_create_pseudo_p () |
8939 | && !strict_memory_address_p (Pmode, XEXP (op, 0))) | |
157891a3 EB |
8940 | return 0; |
8941 | ||
8942 | return 1; | |
7c56249d | 8943 | } |
ab835497 | 8944 | \f |
46e43d2b AS |
8945 | /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ |
8946 | ||
8947 | static bool | |
8948 | sparc_print_operand_punct_valid_p (unsigned char code) | |
8949 | { | |
8950 | if (code == '#' | |
8951 | || code == '*' | |
8952 | || code == '(' | |
8953 | || code == ')' | |
8954 | || code == '_' | |
8955 | || code == '&') | |
8956 | return true; | |
8957 | ||
8958 | return false; | |
8959 | } | |
8960 | ||
8961 | /* Implement TARGET_PRINT_OPERAND. | |
8962 | Print operand X (an rtx) in assembler syntax to file FILE. | |
ab835497 RK |
8963 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. |
8964 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
8965 | ||
46e43d2b AS |
8966 | static void |
8967 | sparc_print_operand (FILE *file, rtx x, int code) | |
ab835497 | 8968 | { |
ff7e7ee0 EB |
8969 | const char *s; |
8970 | ||
ab835497 RK |
8971 | switch (code) |
8972 | { | |
8973 | case '#': | |
4e5b002b EB |
8974 | /* Output an insn in a delay slot. */ |
8975 | if (final_sequence) | |
8976 | sparc_indent_opcode = 1; | |
8977 | else | |
e0d80184 | 8978 | fputs ("\n\t nop", file); |
ab835497 RK |
8979 | return; |
8980 | case '*': | |
c6ce0969 | 8981 | /* Output an annul flag if there's nothing for the delay slot and we |
4e5b002b EB |
8982 | are optimizing. This is always used with '(' below. |
8983 | Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; | |
8984 | this is a dbx bug. So, we only do this when optimizing. | |
8985 | On UltraSPARC, a branch in a delay slot causes a pipeline flush. | |
bfd6bc60 | 8986 | Always emit a nop in case the next instruction is a branch. */ |
4e5b002b | 8987 | if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
c6ce0969 JW |
8988 | fputs (",a", file); |
8989 | return; | |
8990 | case '(': | |
8991 | /* Output a 'nop' if there's nothing for the delay slot and we are | |
8992 | not optimizing. This is always used with '*' above. */ | |
4e5b002b | 8993 | if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
e0d80184 | 8994 | fputs ("\n\t nop", file); |
4e5b002b EB |
8995 | else if (final_sequence) |
8996 | sparc_indent_opcode = 1; | |
8997 | return; | |
8998 | case ')': | |
8999 | /* Output the right displacement from the saved PC on function return. | |
9000 | The caller may have placed an "unimp" insn immediately after the call | |
9001 | so we have to account for it. This insn is used in the 32-bit ABI | |
66695571 | 9002 | when calling a function that returns a non zero-sized structure. The |
4e5b002b | 9003 | 64-bit ABI doesn't have it. Be careful to have this test be the same |
66695571 EB |
9004 | as that for the call. The exception is when sparc_std_struct_return |
9005 | is enabled, the psABI is followed exactly and the adjustment is made | |
9006 | by the code in sparc_struct_value_rtx. The call emitted is the same | |
9007 | when sparc_std_struct_return is enabled. */ | |
9008 | if (!TARGET_ARCH64 | |
e3b5732b | 9009 | && cfun->returns_struct |
66695571 EB |
9010 | && !sparc_std_struct_return |
9011 | && DECL_SIZE (DECL_RESULT (current_function_decl)) | |
9012 | && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) | |
9013 | == INTEGER_CST | |
9014 | && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl)))) | |
4e5b002b EB |
9015 | fputs ("12", file); |
9016 | else | |
9017 | fputc ('8', file); | |
ab835497 | 9018 | return; |
61a55e8b | 9019 | case '_': |
a0a301fc DE |
9020 | /* Output the Embedded Medium/Anywhere code model base register. */ |
9021 | fputs (EMBMEDANY_BASE_REG, file); | |
61a55e8b | 9022 | return; |
5751a10b JJ |
9023 | case '&': |
9024 | /* Print some local dynamic TLS name. */ | |
4fbca4ba RS |
9025 | if (const char *name = get_some_local_dynamic_name ()) |
9026 | assemble_name (file, name); | |
9027 | else | |
9028 | output_operand_lossage ("'%%&' used without any " | |
9029 | "local dynamic TLS references"); | |
5751a10b | 9030 | return; |
4e5b002b | 9031 | |
ab835497 RK |
9032 | case 'Y': |
9033 | /* Adjust the operand to take into account a RESTORE operation. */ | |
bfd6bc60 JC |
9034 | if (GET_CODE (x) == CONST_INT) |
9035 | break; | |
9036 | else if (GET_CODE (x) != REG) | |
c725bd79 | 9037 | output_operand_lossage ("invalid %%Y operand"); |
b3b1e8bd | 9038 | else if (REGNO (x) < 8) |
ab835497 RK |
9039 | fputs (reg_names[REGNO (x)], file); |
9040 | else if (REGNO (x) >= 24 && REGNO (x) < 32) | |
9041 | fputs (reg_names[REGNO (x)-16], file); | |
9042 | else | |
c725bd79 | 9043 | output_operand_lossage ("invalid %%Y operand"); |
ab835497 | 9044 | return; |
0f39a9aa DE |
9045 | case 'L': |
9046 | /* Print out the low order register name of a register pair. */ | |
9047 | if (WORDS_BIG_ENDIAN) | |
9048 | fputs (reg_names[REGNO (x)+1], file); | |
9049 | else | |
9050 | fputs (reg_names[REGNO (x)], file); | |
9051 | return; | |
9052 | case 'H': | |
9053 | /* Print out the high order register name of a register pair. */ | |
9054 | if (WORDS_BIG_ENDIAN) | |
9055 | fputs (reg_names[REGNO (x)], file); | |
9056 | else | |
9057 | fputs (reg_names[REGNO (x)+1], file); | |
9058 | return; | |
ab835497 | 9059 | case 'R': |
795068a4 | 9060 | /* Print out the second register name of a register pair or quad. |
ab835497 RK |
9061 | I.e., R (%o0) => %o1. */ |
9062 | fputs (reg_names[REGNO (x)+1], file); | |
9063 | return; | |
795068a4 JW |
9064 | case 'S': |
9065 | /* Print out the third register name of a register quad. | |
9066 | I.e., S (%o0) => %o2. */ | |
9067 | fputs (reg_names[REGNO (x)+2], file); | |
9068 | return; | |
9069 | case 'T': | |
9070 | /* Print out the fourth register name of a register quad. | |
9071 | I.e., T (%o0) => %o3. */ | |
9072 | fputs (reg_names[REGNO (x)+3], file); | |
9073 | return; | |
304b7a23 DE |
9074 | case 'x': |
9075 | /* Print a condition code register. */ | |
9076 | if (REGNO (x) == SPARC_ICC_REG) | |
9077 | { | |
ff7e7ee0 EB |
9078 | switch (GET_MODE (x)) |
9079 | { | |
4e10a5a7 RS |
9080 | case E_CCmode: |
9081 | case E_CCNZmode: | |
9082 | case E_CCCmode: | |
9083 | case E_CCVmode: | |
ff7e7ee0 EB |
9084 | s = "%icc"; |
9085 | break; | |
4e10a5a7 RS |
9086 | case E_CCXmode: |
9087 | case E_CCXNZmode: | |
9088 | case E_CCXCmode: | |
9089 | case E_CCXVmode: | |
ff7e7ee0 EB |
9090 | s = "%xcc"; |
9091 | break; | |
9092 | default: | |
9093 | gcc_unreachable (); | |
9094 | } | |
9095 | fputs (s, file); | |
304b7a23 DE |
9096 | } |
9097 | else | |
9098 | /* %fccN register */ | |
9099 | fputs (reg_names[REGNO (x)], file); | |
9100 | return; | |
ab835497 RK |
9101 | case 'm': |
9102 | /* Print the operand's address only. */ | |
cc8ca59e | 9103 | output_address (GET_MODE (x), XEXP (x, 0)); |
ab835497 RK |
9104 | return; |
9105 | case 'r': | |
9106 | /* In this case we need a register. Use %g0 if the | |
77a02b01 | 9107 | operand is const0_rtx. */ |
76052e74 RS |
9108 | if (x == const0_rtx |
9109 | || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) | |
ab835497 RK |
9110 | { |
9111 | fputs ("%g0", file); | |
9112 | return; | |
9113 | } | |
9114 | else | |
9115 | break; | |
9116 | ||
61a55e8b | 9117 | case 'A': |
ab835497 RK |
9118 | switch (GET_CODE (x)) |
9119 | { | |
ff7e7ee0 EB |
9120 | case IOR: |
9121 | s = "or"; | |
9122 | break; | |
9123 | case AND: | |
9124 | s = "and"; | |
9125 | break; | |
9126 | case XOR: | |
9127 | s = "xor"; | |
9128 | break; | |
9129 | default: | |
9130 | output_operand_lossage ("invalid %%A operand"); | |
9131 | s = ""; | |
9132 | break; | |
ab835497 | 9133 | } |
ff7e7ee0 | 9134 | fputs (s, file); |
ab835497 RK |
9135 | return; |
9136 | ||
9137 | case 'B': | |
9138 | switch (GET_CODE (x)) | |
9139 | { | |
ff7e7ee0 EB |
9140 | case IOR: |
9141 | s = "orn"; | |
9142 | break; | |
9143 | case AND: | |
9144 | s = "andn"; | |
9145 | break; | |
9146 | case XOR: | |
9147 | s = "xnor"; | |
9148 | break; | |
9149 | default: | |
9150 | output_operand_lossage ("invalid %%B operand"); | |
9151 | s = ""; | |
9152 | break; | |
ab835497 | 9153 | } |
ff7e7ee0 | 9154 | fputs (s, file); |
ab835497 RK |
9155 | return; |
9156 | ||
bf84f42d | 9157 | /* This is used by the conditional move instructions. */ |
61a55e8b | 9158 | case 'C': |
304b7a23 | 9159 | { |
ff7e7ee0 EB |
9160 | machine_mode mode = GET_MODE (XEXP (x, 0)); |
9161 | switch (GET_CODE (x)) | |
304b7a23 | 9162 | { |
ff7e7ee0 | 9163 | case NE: |
85729229 EB |
9164 | if (mode == CCVmode || mode == CCXVmode) |
9165 | s = "vs"; | |
9166 | else | |
9167 | s = "ne"; | |
ff7e7ee0 EB |
9168 | break; |
9169 | case EQ: | |
85729229 EB |
9170 | if (mode == CCVmode || mode == CCXVmode) |
9171 | s = "vc"; | |
9172 | else | |
9173 | s = "e"; | |
ff7e7ee0 EB |
9174 | break; |
9175 | case GE: | |
9176 | if (mode == CCNZmode || mode == CCXNZmode) | |
9177 | s = "pos"; | |
9178 | else | |
9179 | s = "ge"; | |
9180 | break; | |
9181 | case GT: | |
9182 | s = "g"; | |
9183 | break; | |
9184 | case LE: | |
9185 | s = "le"; | |
9186 | break; | |
9187 | case LT: | |
9188 | if (mode == CCNZmode || mode == CCXNZmode) | |
9189 | s = "neg"; | |
9190 | else | |
9191 | s = "l"; | |
9192 | break; | |
9193 | case GEU: | |
9194 | s = "geu"; | |
9195 | break; | |
9196 | case GTU: | |
9197 | s = "gu"; | |
9198 | break; | |
9199 | case LEU: | |
9200 | s = "leu"; | |
9201 | break; | |
9202 | case LTU: | |
9203 | s = "lu"; | |
9204 | break; | |
9205 | case LTGT: | |
9206 | s = "lg"; | |
9207 | break; | |
9208 | case UNORDERED: | |
9209 | s = "u"; | |
9210 | break; | |
9211 | case ORDERED: | |
9212 | s = "o"; | |
9213 | break; | |
9214 | case UNLT: | |
9215 | s = "ul"; | |
9216 | break; | |
9217 | case UNLE: | |
9218 | s = "ule"; | |
9219 | break; | |
9220 | case UNGT: | |
9221 | s = "ug"; | |
9222 | break; | |
9223 | case UNGE: | |
9224 | s = "uge" | |
9225 | ; break; | |
9226 | case UNEQ: | |
9227 | s = "ue"; | |
9228 | break; | |
9229 | default: | |
9230 | output_operand_lossage ("invalid %%C operand"); | |
9231 | s = ""; | |
9232 | break; | |
304b7a23 | 9233 | } |
ff7e7ee0 | 9234 | fputs (s, file); |
304b7a23 DE |
9235 | return; |
9236 | } | |
9237 | ||
bf84f42d | 9238 | /* This are used by the movr instruction pattern. */ |
61a55e8b | 9239 | case 'D': |
304b7a23 | 9240 | { |
ff7e7ee0 | 9241 | switch (GET_CODE (x)) |
304b7a23 | 9242 | { |
ff7e7ee0 EB |
9243 | case NE: |
9244 | s = "ne"; | |
9245 | break; | |
9246 | case EQ: | |
9247 | s = "e"; | |
9248 | break; | |
9249 | case GE: | |
9250 | s = "gez"; | |
9251 | break; | |
9252 | case LT: | |
9253 | s = "lz"; | |
9254 | break; | |
9255 | case LE: | |
9256 | s = "lez"; | |
9257 | break; | |
9258 | case GT: | |
9259 | s = "gz"; | |
9260 | break; | |
9261 | default: | |
9262 | output_operand_lossage ("invalid %%D operand"); | |
9263 | s = ""; | |
9264 | break; | |
304b7a23 | 9265 | } |
ff7e7ee0 | 9266 | fputs (s, file); |
304b7a23 DE |
9267 | return; |
9268 | } | |
61a55e8b | 9269 | |
ab835497 RK |
9270 | case 'b': |
9271 | { | |
9272 | /* Print a sign-extended character. */ | |
9e0625a3 | 9273 | int i = trunc_int_for_mode (INTVAL (x), QImode); |
ab835497 RK |
9274 | fprintf (file, "%d", i); |
9275 | return; | |
9276 | } | |
9277 | ||
d2889939 RK |
9278 | case 'f': |
9279 | /* Operand must be a MEM; write its address. */ | |
9280 | if (GET_CODE (x) != MEM) | |
c725bd79 | 9281 | output_operand_lossage ("invalid %%f operand"); |
cc8ca59e | 9282 | output_address (GET_MODE (x), XEXP (x, 0)); |
d2889939 RK |
9283 | return; |
9284 | ||
8707fe93 RH |
9285 | case 's': |
9286 | { | |
9287 | /* Print a sign-extended 32-bit value. */ | |
9288 | HOST_WIDE_INT i; | |
9289 | if (GET_CODE(x) == CONST_INT) | |
9290 | i = INTVAL (x); | |
8707fe93 | 9291 | else |
ffa916ba KG |
9292 | { |
9293 | output_operand_lossage ("invalid %%s operand"); | |
9294 | return; | |
9295 | } | |
8707fe93 RH |
9296 | i = trunc_int_for_mode (i, SImode); |
9297 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, i); | |
9298 | return; | |
9299 | } | |
9300 | ||
ab835497 RK |
9301 | case 0: |
9302 | /* Do nothing special. */ | |
9303 | break; | |
9304 | ||
9305 | default: | |
9306 | /* Undocumented flag. */ | |
415f583e | 9307 | output_operand_lossage ("invalid operand output code"); |
ab835497 RK |
9308 | } |
9309 | ||
9310 | if (GET_CODE (x) == REG) | |
9311 | fputs (reg_names[REGNO (x)], file); | |
9312 | else if (GET_CODE (x) == MEM) | |
9313 | { | |
9314 | fputc ('[', file); | |
ab835497 | 9315 | /* Poor Sun assembler doesn't understand absolute addressing. */ |
e6c1be7e | 9316 | if (CONSTANT_P (XEXP (x, 0))) |
ab835497 | 9317 | fputs ("%g0+", file); |
cc8ca59e | 9318 | output_address (GET_MODE (x), XEXP (x, 0)); |
ab835497 RK |
9319 | fputc (']', file); |
9320 | } | |
9321 | else if (GET_CODE (x) == HIGH) | |
9322 | { | |
9323 | fputs ("%hi(", file); | |
9324 | output_addr_const (file, XEXP (x, 0)); | |
9325 | fputc (')', file); | |
9326 | } | |
9327 | else if (GET_CODE (x) == LO_SUM) | |
9328 | { | |
46e43d2b | 9329 | sparc_print_operand (file, XEXP (x, 0), 0); |
e0d80184 DM |
9330 | if (TARGET_CM_MEDMID) |
9331 | fputs ("+%l44(", file); | |
9332 | else | |
9333 | fputs ("+%lo(", file); | |
ab835497 RK |
9334 | output_addr_const (file, XEXP (x, 1)); |
9335 | fputc (')', file); | |
9336 | } | |
e601abce | 9337 | else if (GET_CODE (x) == CONST_DOUBLE) |
eaac029f EB |
9338 | output_operand_lossage ("floating-point constant not a valid immediate operand"); |
9339 | else | |
9340 | output_addr_const (file, x); | |
ab835497 | 9341 | } |
46e43d2b AS |
9342 | |
9343 | /* Implement TARGET_PRINT_OPERAND_ADDRESS. */ | |
9344 | ||
9345 | static void | |
cc8ca59e | 9346 | sparc_print_operand_address (FILE *file, machine_mode /*mode*/, rtx x) |
46e43d2b AS |
9347 | { |
9348 | register rtx base, index = 0; | |
9349 | int offset = 0; | |
9350 | register rtx addr = x; | |
9351 | ||
9352 | if (REG_P (addr)) | |
9353 | fputs (reg_names[REGNO (addr)], file); | |
9354 | else if (GET_CODE (addr) == PLUS) | |
9355 | { | |
9356 | if (CONST_INT_P (XEXP (addr, 0))) | |
9357 | offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1); | |
9358 | else if (CONST_INT_P (XEXP (addr, 1))) | |
9359 | offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0); | |
9360 | else | |
9361 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
9362 | if (GET_CODE (base) == LO_SUM) | |
9363 | { | |
9364 | gcc_assert (USE_AS_OFFSETABLE_LO10 | |
9365 | && TARGET_ARCH64 | |
9366 | && ! TARGET_CM_MEDMID); | |
9367 | output_operand (XEXP (base, 0), 0); | |
9368 | fputs ("+%lo(", file); | |
cc8ca59e | 9369 | output_address (VOIDmode, XEXP (base, 1)); |
46e43d2b AS |
9370 | fprintf (file, ")+%d", offset); |
9371 | } | |
9372 | else | |
9373 | { | |
9374 | fputs (reg_names[REGNO (base)], file); | |
9375 | if (index == 0) | |
9376 | fprintf (file, "%+d", offset); | |
9377 | else if (REG_P (index)) | |
9378 | fprintf (file, "+%s", reg_names[REGNO (index)]); | |
9379 | else if (GET_CODE (index) == SYMBOL_REF | |
9380 | || GET_CODE (index) == LABEL_REF | |
9381 | || GET_CODE (index) == CONST) | |
9382 | fputc ('+', file), output_addr_const (file, index); | |
9383 | else gcc_unreachable (); | |
9384 | } | |
9385 | } | |
9386 | else if (GET_CODE (addr) == MINUS | |
9387 | && GET_CODE (XEXP (addr, 1)) == LABEL_REF) | |
9388 | { | |
9389 | output_addr_const (file, XEXP (addr, 0)); | |
9390 | fputs ("-(", file); | |
9391 | output_addr_const (file, XEXP (addr, 1)); | |
9392 | fputs ("-.)", file); | |
9393 | } | |
9394 | else if (GET_CODE (addr) == LO_SUM) | |
9395 | { | |
9396 | output_operand (XEXP (addr, 0), 0); | |
9397 | if (TARGET_CM_MEDMID) | |
9398 | fputs ("+%l44(", file); | |
9399 | else | |
9400 | fputs ("+%lo(", file); | |
cc8ca59e | 9401 | output_address (VOIDmode, XEXP (addr, 1)); |
46e43d2b AS |
9402 | fputc (')', file); |
9403 | } | |
9404 | else if (flag_pic | |
9405 | && GET_CODE (addr) == CONST | |
9406 | && GET_CODE (XEXP (addr, 0)) == MINUS | |
9407 | && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST | |
9408 | && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS | |
9409 | && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) | |
9410 | { | |
9411 | addr = XEXP (addr, 0); | |
9412 | output_addr_const (file, XEXP (addr, 0)); | |
9413 | /* Group the args of the second CONST in parenthesis. */ | |
9414 | fputs ("-(", file); | |
9415 | /* Skip past the second CONST--it does nothing for us. */ | |
9416 | output_addr_const (file, XEXP (XEXP (addr, 1), 0)); | |
9417 | /* Close the parenthesis. */ | |
9418 | fputc (')', file); | |
9419 | } | |
9420 | else | |
9421 | { | |
9422 | output_addr_const (file, addr); | |
9423 | } | |
9424 | } | |
ab835497 | 9425 | \f |
301d03af RS |
9426 | /* Target hook for assembling integer objects. The sparc version has |
9427 | special handling for aligned DI-mode objects. */ | |
ab835497 | 9428 | |
301d03af | 9429 | static bool |
fc27d102 | 9430 | sparc_assemble_integer (rtx x, unsigned int size, int aligned_p) |
ab835497 | 9431 | { |
301d03af RS |
9432 | /* ??? We only output .xword's for symbols and only then in environments |
9433 | where the assembler can handle them. */ | |
eaac029f | 9434 | if (aligned_p && size == 8 && GET_CODE (x) != CONST_INT) |
ab835497 | 9435 | { |
301d03af | 9436 | if (TARGET_V9) |
61a55e8b | 9437 | { |
301d03af RS |
9438 | assemble_integer_with_op ("\t.xword\t", x); |
9439 | return true; | |
61a55e8b DE |
9440 | } |
9441 | else | |
9442 | { | |
301d03af RS |
9443 | assemble_aligned_integer (4, const0_rtx); |
9444 | assemble_aligned_integer (4, x); | |
9445 | return true; | |
61a55e8b | 9446 | } |
ab835497 | 9447 | } |
301d03af | 9448 | return default_assemble_integer (x, size, aligned_p); |
ab835497 | 9449 | } |
210aa14a | 9450 | \f |
b0468b84 RK |
9451 | /* Return the value of a code used in the .proc pseudo-op that says |
9452 | what kind of result this function returns. For non-C types, we pick | |
9453 | the closest C type. */ | |
9454 | ||
77a02b01 JW |
9455 | #ifndef SHORT_TYPE_SIZE |
9456 | #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) | |
9457 | #endif | |
9458 | ||
9459 | #ifndef INT_TYPE_SIZE | |
9460 | #define INT_TYPE_SIZE BITS_PER_WORD | |
9461 | #endif | |
9462 | ||
9463 | #ifndef LONG_TYPE_SIZE | |
9464 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
9465 | #endif | |
9466 | ||
9467 | #ifndef LONG_LONG_TYPE_SIZE | |
9468 | #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) | |
9469 | #endif | |
9470 | ||
9471 | #ifndef FLOAT_TYPE_SIZE | |
9472 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
9473 | #endif | |
9474 | ||
9475 | #ifndef DOUBLE_TYPE_SIZE | |
9476 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
9477 | #endif | |
9478 | ||
9479 | #ifndef LONG_DOUBLE_TYPE_SIZE | |
9480 | #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
9481 | #endif | |
210aa14a RS |
9482 | |
9483 | unsigned long | |
fc27d102 | 9484 | sparc_type_code (register tree type) |
210aa14a RS |
9485 | { |
9486 | register unsigned long qualifiers = 0; | |
e5e809f4 | 9487 | register unsigned shift; |
210aa14a | 9488 | |
abc95ed3 | 9489 | /* Only the first 30 bits of the qualifier are valid. We must refrain from |
aee2c3c5 JW |
9490 | setting more, since some assemblers will give an error for this. Also, |
9491 | we must be careful to avoid shifts of 32 bits or more to avoid getting | |
9492 | unpredictable results. */ | |
9493 | ||
e5e809f4 | 9494 | for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) |
210aa14a RS |
9495 | { |
9496 | switch (TREE_CODE (type)) | |
9497 | { | |
9498 | case ERROR_MARK: | |
9499 | return qualifiers; | |
4900aa61 | 9500 | |
210aa14a | 9501 | case ARRAY_TYPE: |
e5e809f4 | 9502 | qualifiers |= (3 << shift); |
210aa14a RS |
9503 | break; |
9504 | ||
9505 | case FUNCTION_TYPE: | |
9506 | case METHOD_TYPE: | |
e5e809f4 | 9507 | qualifiers |= (2 << shift); |
210aa14a RS |
9508 | break; |
9509 | ||
9510 | case POINTER_TYPE: | |
9511 | case REFERENCE_TYPE: | |
9512 | case OFFSET_TYPE: | |
e5e809f4 | 9513 | qualifiers |= (1 << shift); |
210aa14a | 9514 | break; |
ab835497 | 9515 | |
210aa14a RS |
9516 | case RECORD_TYPE: |
9517 | return (qualifiers | 8); | |
9518 | ||
9519 | case UNION_TYPE: | |
b0468b84 | 9520 | case QUAL_UNION_TYPE: |
210aa14a RS |
9521 | return (qualifiers | 9); |
9522 | ||
9523 | case ENUMERAL_TYPE: | |
9524 | return (qualifiers | 10); | |
9525 | ||
9526 | case VOID_TYPE: | |
9527 | return (qualifiers | 16); | |
9528 | ||
9529 | case INTEGER_TYPE: | |
654209e6 JW |
9530 | /* If this is a range type, consider it to be the underlying |
9531 | type. */ | |
9532 | if (TREE_TYPE (type) != 0) | |
e5e809f4 | 9533 | break; |
654209e6 | 9534 | |
77a02b01 | 9535 | /* Carefully distinguish all the standard types of C, |
b0468b84 | 9536 | without messing up if the language is not C. We do this by |
8df83eae | 9537 | testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to |
b0468b84 RK |
9538 | look at both the names and the above fields, but that's redundant. |
9539 | Any type whose size is between two C types will be considered | |
9540 | to be the wider of the two types. Also, we do not have a | |
9541 | special code to use for "long long", so anything wider than | |
9542 | long is treated the same. Note that we can't distinguish | |
9543 | between "int" and "long" in this code if they are the same | |
9544 | size, but that's fine, since neither can the assembler. */ | |
9545 | ||
9546 | if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) | |
8df83eae | 9547 | return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2)); |
4900aa61 | 9548 | |
b0468b84 | 9549 | else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) |
8df83eae | 9550 | return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3)); |
4900aa61 | 9551 | |
b0468b84 | 9552 | else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) |
8df83eae | 9553 | return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4)); |
4900aa61 | 9554 | |
b0468b84 | 9555 | else |
8df83eae | 9556 | return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5)); |
4900aa61 | 9557 | |
210aa14a | 9558 | case REAL_TYPE: |
e5e809f4 JL |
9559 | /* If this is a range type, consider it to be the underlying |
9560 | type. */ | |
9561 | if (TREE_TYPE (type) != 0) | |
9562 | break; | |
9563 | ||
77a02b01 JW |
9564 | /* Carefully distinguish all the standard types of C, |
9565 | without messing up if the language is not C. */ | |
b0468b84 | 9566 | |
77a02b01 | 9567 | if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) |
210aa14a | 9568 | return (qualifiers | 6); |
b0468b84 | 9569 | |
4900aa61 | 9570 | else |
b0468b84 | 9571 | return (qualifiers | 7); |
4900aa61 | 9572 | |
210aa14a | 9573 | case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ |
13d39dbc | 9574 | /* ??? We need to distinguish between double and float complex types, |
c82aa69a JW |
9575 | but I don't know how yet because I can't reach this code from |
9576 | existing front-ends. */ | |
9577 | return (qualifiers | 7); /* Who knows? */ | |
9578 | ||
1b5963f7 | 9579 | case VECTOR_TYPE: |
62de55f7 | 9580 | case BOOLEAN_TYPE: /* Boolean truth value type. */ |
0e7e1527 EB |
9581 | case LANG_TYPE: |
9582 | case NULLPTR_TYPE: | |
26902ae0 | 9583 | return qualifiers; |
4900aa61 | 9584 | |
210aa14a | 9585 | default: |
f5f7d171 | 9586 | gcc_unreachable (); /* Not a type! */ |
210aa14a RS |
9587 | } |
9588 | } | |
e5e809f4 JL |
9589 | |
9590 | return qualifiers; | |
210aa14a | 9591 | } |
ead69aea | 9592 | \f |
61a55e8b DE |
9593 | /* Nested function support. */ |
9594 | ||
9595 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
9596 | FNADDR is an RTX for the address of the function's pure code. | |
9597 | CXT is an RTX for the static chain value for the function. | |
9598 | ||
9599 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
9600 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
9601 | (to store insns). This is a bit excessive. Perhaps a different | |
9602 | mechanism would be better here. | |
9603 | ||
849a528d | 9604 | Emit enough FLUSH insns to synchronize the data and instruction caches. */ |
61a55e8b | 9605 | |
809e78cc RH |
9606 | static void |
9607 | sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt) | |
61a55e8b | 9608 | { |
1ec0c607 | 9609 | /* SPARC 32-bit trampoline: |
c6b0465b | 9610 | |
e0d80184 DM |
9611 | sethi %hi(fn), %g1 |
9612 | sethi %hi(static), %g2 | |
9613 | jmp %g1+%lo(fn) | |
9614 | or %g2, %lo(static), %g2 | |
c6b0465b JC |
9615 | |
9616 | SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii | |
9617 | JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii | |
9618 | */ | |
9619 | ||
35aa3c1c | 9620 | emit_move_insn |
809e78cc | 9621 | (adjust_address (m_tramp, SImode, 0), |
35aa3c1c | 9622 | expand_binop (SImode, ior_optab, |
eb6c3df1 | 9623 | expand_shift (RSHIFT_EXPR, SImode, fnaddr, 10, 0, 1), |
35aa3c1c RK |
9624 | GEN_INT (trunc_int_for_mode (0x03000000, SImode)), |
9625 | NULL_RTX, 1, OPTAB_DIRECT)); | |
9626 | ||
9627 | emit_move_insn | |
809e78cc | 9628 | (adjust_address (m_tramp, SImode, 4), |
35aa3c1c | 9629 | expand_binop (SImode, ior_optab, |
eb6c3df1 | 9630 | expand_shift (RSHIFT_EXPR, SImode, cxt, 10, 0, 1), |
35aa3c1c RK |
9631 | GEN_INT (trunc_int_for_mode (0x05000000, SImode)), |
9632 | NULL_RTX, 1, OPTAB_DIRECT)); | |
9633 | ||
9634 | emit_move_insn | |
809e78cc | 9635 | (adjust_address (m_tramp, SImode, 8), |
35aa3c1c RK |
9636 | expand_binop (SImode, ior_optab, |
9637 | expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX), | |
9638 | GEN_INT (trunc_int_for_mode (0x81c06000, SImode)), | |
9639 | NULL_RTX, 1, OPTAB_DIRECT)); | |
9640 | ||
9641 | emit_move_insn | |
809e78cc | 9642 | (adjust_address (m_tramp, SImode, 12), |
35aa3c1c RK |
9643 | expand_binop (SImode, ior_optab, |
9644 | expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX), | |
9645 | GEN_INT (trunc_int_for_mode (0x8410a000, SImode)), | |
9646 | NULL_RTX, 1, OPTAB_DIRECT)); | |
c6b0465b | 9647 | |
c6b0465b JC |
9648 | /* On UltraSPARC a flush flushes an entire cache line. The trampoline is |
9649 | aligned on a 16 byte boundary so one flush clears it all. */ | |
fde66fde | 9650 | emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 0)))); |
84643cbf | 9651 | if (sparc_cpu != PROCESSOR_ULTRASPARC |
4c837a1e | 9652 | && sparc_cpu != PROCESSOR_ULTRASPARC3 |
9eeaed6e | 9653 | && sparc_cpu != PROCESSOR_NIAGARA |
3e64c239 DM |
9654 | && sparc_cpu != PROCESSOR_NIAGARA2 |
9655 | && sparc_cpu != PROCESSOR_NIAGARA3 | |
690f24b7 | 9656 | && sparc_cpu != PROCESSOR_NIAGARA4 |
bcc3c3f1 JM |
9657 | && sparc_cpu != PROCESSOR_NIAGARA7 |
9658 | && sparc_cpu != PROCESSOR_M8) | |
fde66fde | 9659 | emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 8)))); |
1ec0c607 WH |
9660 | |
9661 | /* Call __enable_execute_stack after writing onto the stack to make sure | |
9662 | the stack address is accessible. */ | |
10e48e39 | 9663 | #ifdef HAVE_ENABLE_EXECUTE_STACK |
f1c25d3b | 9664 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"), |
db69559b | 9665 | LCT_NORMAL, VOIDmode, XEXP (m_tramp, 0), Pmode); |
1ec0c607 WH |
9666 | #endif |
9667 | ||
61a55e8b DE |
9668 | } |
9669 | ||
1ec0c607 | 9670 | /* The 64-bit version is simpler because it makes more sense to load the |
849a528d RK |
9671 | values as "immediate" data out of the trampoline. It's also easier since |
9672 | we can read the PC without clobbering a register. */ | |
9673 | ||
809e78cc RH |
9674 | static void |
9675 | sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt) | |
61a55e8b | 9676 | { |
1ec0c607 | 9677 | /* SPARC 64-bit trampoline: |
345a6161 | 9678 | |
e0d80184 DM |
9679 | rd %pc, %g1 |
9680 | ldx [%g1+24], %g5 | |
9681 | jmp %g5 | |
9682 | ldx [%g1+16], %g5 | |
c6b0465b JC |
9683 | +16 bytes data |
9684 | */ | |
9685 | ||
809e78cc | 9686 | emit_move_insn (adjust_address (m_tramp, SImode, 0), |
e3aaacf4 | 9687 | GEN_INT (trunc_int_for_mode (0x83414000, SImode))); |
809e78cc | 9688 | emit_move_insn (adjust_address (m_tramp, SImode, 4), |
e3aaacf4 | 9689 | GEN_INT (trunc_int_for_mode (0xca586018, SImode))); |
809e78cc | 9690 | emit_move_insn (adjust_address (m_tramp, SImode, 8), |
e3aaacf4 | 9691 | GEN_INT (trunc_int_for_mode (0x81c14000, SImode))); |
809e78cc | 9692 | emit_move_insn (adjust_address (m_tramp, SImode, 12), |
e3aaacf4 | 9693 | GEN_INT (trunc_int_for_mode (0xca586010, SImode))); |
809e78cc RH |
9694 | emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt); |
9695 | emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr); | |
9696 | emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0)))); | |
345a6161 | 9697 | |
fae15c93 | 9698 | if (sparc_cpu != PROCESSOR_ULTRASPARC |
4c837a1e | 9699 | && sparc_cpu != PROCESSOR_ULTRASPARC3 |
9eeaed6e | 9700 | && sparc_cpu != PROCESSOR_NIAGARA |
3e64c239 DM |
9701 | && sparc_cpu != PROCESSOR_NIAGARA2 |
9702 | && sparc_cpu != PROCESSOR_NIAGARA3 | |
690f24b7 | 9703 | && sparc_cpu != PROCESSOR_NIAGARA4 |
bcc3c3f1 JM |
9704 | && sparc_cpu != PROCESSOR_NIAGARA7 |
9705 | && sparc_cpu != PROCESSOR_M8) | |
809e78cc | 9706 | emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8)))); |
1ec0c607 WH |
9707 | |
9708 | /* Call __enable_execute_stack after writing onto the stack to make sure | |
9709 | the stack address is accessible. */ | |
10e48e39 | 9710 | #ifdef HAVE_ENABLE_EXECUTE_STACK |
f1c25d3b | 9711 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"), |
db69559b | 9712 | LCT_NORMAL, VOIDmode, XEXP (m_tramp, 0), Pmode); |
1ec0c607 | 9713 | #endif |
61a55e8b | 9714 | } |
809e78cc RH |
9715 | |
9716 | /* Worker for TARGET_TRAMPOLINE_INIT. */ | |
9717 | ||
9718 | static void | |
9719 | sparc_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) | |
9720 | { | |
9721 | rtx fnaddr = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0)); | |
9722 | cxt = force_reg (Pmode, cxt); | |
9723 | if (TARGET_ARCH64) | |
9724 | sparc64_initialize_trampoline (m_tramp, fnaddr, cxt); | |
9725 | else | |
9726 | sparc32_initialize_trampoline (m_tramp, fnaddr, cxt); | |
9727 | } | |
61a55e8b | 9728 | \f |
dbb54862 JW |
9729 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
9730 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
9731 | ||
8947065c | 9732 | static int |
b505225b TS |
9733 | supersparc_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, |
9734 | int cost) | |
dbb54862 JW |
9735 | { |
9736 | enum attr_type insn_type; | |
9737 | ||
eadb344f EB |
9738 | if (recog_memoized (insn) < 0) |
9739 | return cost; | |
dbb54862 JW |
9740 | |
9741 | insn_type = get_attr_type (insn); | |
9742 | ||
b505225b | 9743 | if (dep_type == 0) |
dbb54862 JW |
9744 | { |
9745 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
9746 | cycles later. */ | |
9747 | ||
9748 | /* if a load, then the dependence must be on the memory address; | |
3bc8b61e DM |
9749 | add an extra "cycle". Note that the cost could be two cycles |
9750 | if the reg was written late in an instruction group; we ca not tell | |
dbb54862 JW |
9751 | here. */ |
9752 | if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) | |
9753 | return cost + 3; | |
9754 | ||
9755 | /* Get the delay only if the address of the store is the dependence. */ | |
9756 | if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) | |
9757 | { | |
9758 | rtx pat = PATTERN(insn); | |
9759 | rtx dep_pat = PATTERN (dep_insn); | |
9760 | ||
9761 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
3bc8b61e | 9762 | return cost; /* This should not happen! */ |
dbb54862 JW |
9763 | |
9764 | /* The dependency between the two instructions was on the data that | |
9765 | is being stored. Assume that this implies that the address of the | |
9766 | store is not dependent. */ | |
9767 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
9768 | return cost; | |
9769 | ||
9770 | return cost + 3; /* An approximation. */ | |
9771 | } | |
9772 | ||
9773 | /* A shift instruction cannot receive its data from an instruction | |
9774 | in the same cycle; add a one cycle penalty. */ | |
9775 | if (insn_type == TYPE_SHIFT) | |
9776 | return cost + 3; /* Split before cascade into shift. */ | |
9777 | } | |
9778 | else | |
9779 | { | |
9780 | /* Anti- or output- dependency; DEP_INSN reads/writes a register that | |
9781 | INSN writes some cycles later. */ | |
9782 | ||
9783 | /* These are only significant for the fpu unit; writing a fp reg before | |
9784 | the fpu has finished with it stalls the processor. */ | |
9785 | ||
9786 | /* Reusing an integer register causes no problems. */ | |
9787 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
9788 | return 0; | |
9789 | } | |
9790 | ||
9791 | return cost; | |
9792 | } | |
bfd6bc60 | 9793 | |
8947065c | 9794 | static int |
b505225b TS |
9795 | hypersparc_adjust_cost (rtx_insn *insn, int dtype, rtx_insn *dep_insn, |
9796 | int cost) | |
8947065c RH |
9797 | { |
9798 | enum attr_type insn_type, dep_type; | |
9799 | rtx pat = PATTERN(insn); | |
9800 | rtx dep_pat = PATTERN (dep_insn); | |
9801 | ||
9802 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) | |
9803 | return cost; | |
9804 | ||
9805 | insn_type = get_attr_type (insn); | |
9806 | dep_type = get_attr_type (dep_insn); | |
9807 | ||
b505225b | 9808 | switch (dtype) |
8947065c RH |
9809 | { |
9810 | case 0: | |
9811 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
9812 | cycles later. */ | |
9813 | ||
9814 | switch (insn_type) | |
9815 | { | |
9816 | case TYPE_STORE: | |
9817 | case TYPE_FPSTORE: | |
80ffc95e | 9818 | /* Get the delay iff the address of the store is the dependence. */ |
8947065c RH |
9819 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) |
9820 | return cost; | |
9821 | ||
9822 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
9823 | return cost; | |
9824 | return cost + 3; | |
9825 | ||
9826 | case TYPE_LOAD: | |
9827 | case TYPE_SLOAD: | |
9828 | case TYPE_FPLOAD: | |
9829 | /* If a load, then the dependence must be on the memory address. If | |
9830 | the addresses aren't equal, then it might be a false dependency */ | |
9831 | if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) | |
9832 | { | |
9833 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET | |
4900aa61 | 9834 | || GET_CODE (SET_DEST (dep_pat)) != MEM |
8947065c RH |
9835 | || GET_CODE (SET_SRC (pat)) != MEM |
9836 | || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), | |
9837 | XEXP (SET_SRC (pat), 0))) | |
9838 | return cost + 2; | |
9839 | ||
4900aa61 | 9840 | return cost + 8; |
8947065c RH |
9841 | } |
9842 | break; | |
9843 | ||
9844 | case TYPE_BRANCH: | |
9845 | /* Compare to branch latency is 0. There is no benefit from | |
9846 | separating compare and branch. */ | |
9847 | if (dep_type == TYPE_COMPARE) | |
9848 | return 0; | |
9849 | /* Floating point compare to branch latency is less than | |
9850 | compare to conditional move. */ | |
9851 | if (dep_type == TYPE_FPCMP) | |
9852 | return cost - 1; | |
9853 | break; | |
3bb5de61 KG |
9854 | default: |
9855 | break; | |
8947065c RH |
9856 | } |
9857 | break; | |
9858 | ||
9859 | case REG_DEP_ANTI: | |
80ffc95e | 9860 | /* Anti-dependencies only penalize the fpu unit. */ |
8947065c RH |
9861 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) |
9862 | return 0; | |
9863 | break; | |
9864 | ||
9865 | default: | |
9866 | break; | |
4900aa61 | 9867 | } |
8947065c RH |
9868 | |
9869 | return cost; | |
9870 | } | |
9871 | ||
c237e94a | 9872 | static int |
b505225b TS |
9873 | sparc_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep, int cost, |
9874 | unsigned int) | |
8947065c RH |
9875 | { |
9876 | switch (sparc_cpu) | |
9877 | { | |
9878 | case PROCESSOR_SUPERSPARC: | |
b505225b | 9879 | cost = supersparc_adjust_cost (insn, dep_type, dep, cost); |
8947065c RH |
9880 | break; |
9881 | case PROCESSOR_HYPERSPARC: | |
9882 | case PROCESSOR_SPARCLITE86X: | |
b505225b | 9883 | cost = hypersparc_adjust_cost (insn, dep_type, dep, cost); |
8947065c | 9884 | break; |
8947065c RH |
9885 | default: |
9886 | break; | |
9887 | } | |
9888 | return cost; | |
9889 | } | |
9890 | ||
fae15c93 | 9891 | static void |
fc27d102 KG |
9892 | sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED, |
9893 | int sched_verbose ATTRIBUTE_UNUSED, | |
9894 | int max_ready ATTRIBUTE_UNUSED) | |
4900aa61 EB |
9895 | {} |
9896 | ||
fae15c93 | 9897 | static int |
fc27d102 | 9898 | sparc_use_sched_lookahead (void) |
fae15c93 | 9899 | { |
9eeaed6e | 9900 | if (sparc_cpu == PROCESSOR_NIAGARA |
3e64c239 | 9901 | || sparc_cpu == PROCESSOR_NIAGARA2 |
851634c7 | 9902 | || sparc_cpu == PROCESSOR_NIAGARA3) |
4c837a1e | 9903 | return 0; |
690f24b7 | 9904 | if (sparc_cpu == PROCESSOR_NIAGARA4 |
bcc3c3f1 JM |
9905 | || sparc_cpu == PROCESSOR_NIAGARA7 |
9906 | || sparc_cpu == PROCESSOR_M8) | |
851634c7 | 9907 | return 2; |
fae15c93 VM |
9908 | if (sparc_cpu == PROCESSOR_ULTRASPARC |
9909 | || sparc_cpu == PROCESSOR_ULTRASPARC3) | |
9910 | return 4; | |
9911 | if ((1 << sparc_cpu) & | |
9912 | ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | | |
9913 | (1 << PROCESSOR_SPARCLITE86X))) | |
9914 | return 3; | |
3bc8b61e DM |
9915 | return 0; |
9916 | } | |
9917 | ||
fae15c93 | 9918 | static int |
fc27d102 | 9919 | sparc_issue_rate (void) |
bfd6bc60 JC |
9920 | { |
9921 | switch (sparc_cpu) | |
9922 | { | |
4c837a1e | 9923 | case PROCESSOR_NIAGARA: |
9eeaed6e | 9924 | case PROCESSOR_NIAGARA2: |
3e64c239 | 9925 | case PROCESSOR_NIAGARA3: |
fae15c93 VM |
9926 | default: |
9927 | return 1; | |
851634c7 | 9928 | case PROCESSOR_NIAGARA4: |
690f24b7 | 9929 | case PROCESSOR_NIAGARA7: |
fae15c93 | 9930 | case PROCESSOR_V9: |
284d86e9 | 9931 | /* Assume V9 processors are capable of at least dual-issue. */ |
bfd6bc60 | 9932 | return 2; |
fae15c93 VM |
9933 | case PROCESSOR_SUPERSPARC: |
9934 | return 3; | |
393049a9 RH |
9935 | case PROCESSOR_HYPERSPARC: |
9936 | case PROCESSOR_SPARCLITE86X: | |
9937 | return 2; | |
fae15c93 VM |
9938 | case PROCESSOR_ULTRASPARC: |
9939 | case PROCESSOR_ULTRASPARC3: | |
bcc3c3f1 | 9940 | case PROCESSOR_M8: |
fae15c93 | 9941 | return 4; |
bfd6bc60 JC |
9942 | } |
9943 | } | |
284d86e9 JC |
9944 | |
9945 | static int | |
b32d5189 | 9946 | set_extends (rtx_insn *insn) |
284d86e9 JC |
9947 | { |
9948 | register rtx pat = PATTERN (insn); | |
9949 | ||
9950 | switch (GET_CODE (SET_SRC (pat))) | |
9951 | { | |
80ffc95e | 9952 | /* Load and some shift instructions zero extend. */ |
284d86e9 JC |
9953 | case MEM: |
9954 | case ZERO_EXTEND: | |
9955 | /* sethi clears the high bits */ | |
9956 | case HIGH: | |
9957 | /* LO_SUM is used with sethi. sethi cleared the high | |
9958 | bits and the values used with lo_sum are positive */ | |
9959 | case LO_SUM: | |
284d86e9 JC |
9960 | /* Store flag stores 0 or 1 */ |
9961 | case LT: case LTU: | |
9962 | case GT: case GTU: | |
9963 | case LE: case LEU: | |
9964 | case GE: case GEU: | |
9965 | case EQ: | |
9966 | case NE: | |
9967 | return 1; | |
9968 | case AND: | |
9969 | { | |
4df1190a | 9970 | rtx op0 = XEXP (SET_SRC (pat), 0); |
284d86e9 JC |
9971 | rtx op1 = XEXP (SET_SRC (pat), 1); |
9972 | if (GET_CODE (op1) == CONST_INT) | |
9973 | return INTVAL (op1) >= 0; | |
4df1190a JJ |
9974 | if (GET_CODE (op0) != REG) |
9975 | return 0; | |
9976 | if (sparc_check_64 (op0, insn) == 1) | |
284d86e9 | 9977 | return 1; |
4df1190a JJ |
9978 | return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); |
9979 | } | |
9980 | case IOR: | |
9981 | case XOR: | |
9982 | { | |
9983 | rtx op0 = XEXP (SET_SRC (pat), 0); | |
9984 | rtx op1 = XEXP (SET_SRC (pat), 1); | |
9985 | if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) | |
9986 | return 0; | |
9987 | if (GET_CODE (op1) == CONST_INT) | |
9988 | return INTVAL (op1) >= 0; | |
9989 | return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); | |
284d86e9 | 9990 | } |
284d86e9 JC |
9991 | case LSHIFTRT: |
9992 | return GET_MODE (SET_SRC (pat)) == SImode; | |
80ffc95e | 9993 | /* Positive integers leave the high bits zero. */ |
284d86e9 | 9994 | case CONST_INT: |
eaac029f | 9995 | return !(INTVAL (SET_SRC (pat)) & 0x80000000); |
284d86e9 JC |
9996 | case ASHIFTRT: |
9997 | case SIGN_EXTEND: | |
9998 | return - (GET_MODE (SET_SRC (pat)) == SImode); | |
4df1190a JJ |
9999 | case REG: |
10000 | return sparc_check_64 (SET_SRC (pat), insn); | |
284d86e9 JC |
10001 | default: |
10002 | return 0; | |
10003 | } | |
10004 | } | |
10005 | ||
80ffc95e | 10006 | /* We _ought_ to have only one kind per function, but... */ |
e2500fed GK |
10007 | static GTY(()) rtx sparc_addr_diff_list; |
10008 | static GTY(()) rtx sparc_addr_list; | |
e0d80184 DM |
10009 | |
10010 | void | |
fc27d102 | 10011 | sparc_defer_case_vector (rtx lab, rtx vec, int diff) |
e0d80184 DM |
10012 | { |
10013 | vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); | |
10014 | if (diff) | |
10015 | sparc_addr_diff_list | |
10016 | = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); | |
10017 | else | |
10018 | sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); | |
10019 | } | |
10020 | ||
4900aa61 | 10021 | static void |
fc27d102 | 10022 | sparc_output_addr_vec (rtx vec) |
e0d80184 DM |
10023 | { |
10024 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
10025 | int idx, vlen = XVECLEN (body, 0); | |
10026 | ||
4900aa61 | 10027 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
d1accaa3 JJ |
10028 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); |
10029 | #endif | |
10030 | ||
e0d80184 DM |
10031 | #ifdef ASM_OUTPUT_CASE_LABEL |
10032 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
10033 | NEXT_INSN (lab)); | |
10034 | #else | |
4977bab6 | 10035 | (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); |
e0d80184 DM |
10036 | #endif |
10037 | ||
10038 | for (idx = 0; idx < vlen; idx++) | |
10039 | { | |
10040 | ASM_OUTPUT_ADDR_VEC_ELT | |
10041 | (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); | |
10042 | } | |
4900aa61 | 10043 | |
d1accaa3 JJ |
10044 | #ifdef ASM_OUTPUT_ADDR_VEC_END |
10045 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
10046 | #endif | |
e0d80184 DM |
10047 | } |
10048 | ||
4900aa61 | 10049 | static void |
fc27d102 | 10050 | sparc_output_addr_diff_vec (rtx vec) |
e0d80184 DM |
10051 | { |
10052 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
10053 | rtx base = XEXP (XEXP (body, 0), 0); | |
10054 | int idx, vlen = XVECLEN (body, 1); | |
10055 | ||
4900aa61 | 10056 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
d1accaa3 JJ |
10057 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); |
10058 | #endif | |
10059 | ||
e0d80184 DM |
10060 | #ifdef ASM_OUTPUT_CASE_LABEL |
10061 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
10062 | NEXT_INSN (lab)); | |
10063 | #else | |
4977bab6 | 10064 | (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); |
e0d80184 DM |
10065 | #endif |
10066 | ||
10067 | for (idx = 0; idx < vlen; idx++) | |
10068 | { | |
10069 | ASM_OUTPUT_ADDR_DIFF_ELT | |
10070 | (asm_out_file, | |
10071 | body, | |
10072 | CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), | |
10073 | CODE_LABEL_NUMBER (base)); | |
10074 | } | |
4900aa61 | 10075 | |
d1accaa3 JJ |
10076 | #ifdef ASM_OUTPUT_ADDR_VEC_END |
10077 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
10078 | #endif | |
e0d80184 DM |
10079 | } |
10080 | ||
10081 | static void | |
fc27d102 | 10082 | sparc_output_deferred_case_vectors (void) |
e0d80184 DM |
10083 | { |
10084 | rtx t; | |
d676da68 | 10085 | int align; |
e0d80184 | 10086 | |
f3b8847b DM |
10087 | if (sparc_addr_list == NULL_RTX |
10088 | && sparc_addr_diff_list == NULL_RTX) | |
10089 | return; | |
10090 | ||
e0d80184 | 10091 | /* Align to cache line in the function's code section. */ |
d6b5193b | 10092 | switch_to_section (current_function_section ()); |
d676da68 DM |
10093 | |
10094 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
10095 | if (align > 0) | |
f3b8847b | 10096 | ASM_OUTPUT_ALIGN (asm_out_file, align); |
4900aa61 | 10097 | |
e0d80184 DM |
10098 | for (t = sparc_addr_list; t ; t = XEXP (t, 1)) |
10099 | sparc_output_addr_vec (XEXP (t, 0)); | |
10100 | for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) | |
10101 | sparc_output_addr_diff_vec (XEXP (t, 0)); | |
10102 | ||
10103 | sparc_addr_list = sparc_addr_diff_list = NULL_RTX; | |
10104 | } | |
10105 | ||
284d86e9 JC |
10106 | /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are |
10107 | unknown. Return 1 if the high bits are zero, -1 if the register is | |
10108 | sign extended. */ | |
10109 | int | |
b32d5189 | 10110 | sparc_check_64 (rtx x, rtx_insn *insn) |
284d86e9 JC |
10111 | { |
10112 | /* If a register is set only once it is safe to ignore insns this | |
10113 | code does not know how to handle. The loop will either recognize | |
10114 | the single set and return the correct value or fail to recognize | |
10115 | it and return 0. */ | |
10116 | int set_once = 0; | |
4df1190a JJ |
10117 | rtx y = x; |
10118 | ||
f5f7d171 | 10119 | gcc_assert (GET_CODE (x) == REG); |
4df1190a JJ |
10120 | |
10121 | if (GET_MODE (x) == DImode) | |
10122 | y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN); | |
284d86e9 | 10123 | |
4df1190a | 10124 | if (flag_expensive_optimizations |
b718216c | 10125 | && df && DF_REG_DEF_COUNT (REGNO (y)) == 1) |
284d86e9 JC |
10126 | set_once = 1; |
10127 | ||
10128 | if (insn == 0) | |
d6f4ec51 KG |
10129 | { |
10130 | if (set_once) | |
10131 | insn = get_last_insn_anywhere (); | |
10132 | else | |
10133 | return 0; | |
10134 | } | |
284d86e9 | 10135 | |
d6f4ec51 | 10136 | while ((insn = PREV_INSN (insn))) |
284d86e9 JC |
10137 | { |
10138 | switch (GET_CODE (insn)) | |
10139 | { | |
10140 | case JUMP_INSN: | |
10141 | case NOTE: | |
10142 | break; | |
10143 | case CODE_LABEL: | |
10144 | case CALL_INSN: | |
10145 | default: | |
10146 | if (! set_once) | |
10147 | return 0; | |
10148 | break; | |
10149 | case INSN: | |
10150 | { | |
10151 | rtx pat = PATTERN (insn); | |
10152 | if (GET_CODE (pat) != SET) | |
10153 | return 0; | |
10154 | if (rtx_equal_p (x, SET_DEST (pat))) | |
4df1190a JJ |
10155 | return set_extends (insn); |
10156 | if (y && rtx_equal_p (y, SET_DEST (pat))) | |
10157 | return set_extends (insn); | |
10158 | if (reg_overlap_mentioned_p (SET_DEST (pat), y)) | |
284d86e9 JC |
10159 | return 0; |
10160 | } | |
10161 | } | |
10162 | } | |
10163 | return 0; | |
10164 | } | |
10165 | ||
68126bad EB |
10166 | /* Output a wide shift instruction in V8+ mode. INSN is the instruction, |
10167 | OPERANDS are its operands and OPCODE is the mnemonic to be used. */ | |
10168 | ||
a6163c22 | 10169 | const char * |
e1faf324 | 10170 | output_v8plus_shift (rtx_insn *insn, rtx *operands, const char *opcode) |
284d86e9 JC |
10171 | { |
10172 | static char asm_code[60]; | |
10173 | ||
01d3224a EB |
10174 | /* The scratch register is only required when the destination |
10175 | register is not a 64-bit global or out register. */ | |
10176 | if (which_alternative != 2) | |
284d86e9 | 10177 | operands[3] = operands[0]; |
01d3224a | 10178 | |
1c8b4e29 EB |
10179 | /* We can only shift by constants <= 63. */ |
10180 | if (GET_CODE (operands[2]) == CONST_INT) | |
10181 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); | |
10182 | ||
c6b0465b JC |
10183 | if (GET_CODE (operands[1]) == CONST_INT) |
10184 | { | |
4df1190a | 10185 | output_asm_insn ("mov\t%1, %3", operands); |
c6b0465b JC |
10186 | } |
10187 | else | |
10188 | { | |
4df1190a | 10189 | output_asm_insn ("sllx\t%H1, 32, %3", operands); |
c6b0465b | 10190 | if (sparc_check_64 (operands[1], insn) <= 0) |
4df1190a JJ |
10191 | output_asm_insn ("srl\t%L1, 0, %L1", operands); |
10192 | output_asm_insn ("or\t%L1, %3, %3", operands); | |
c6b0465b | 10193 | } |
284d86e9 | 10194 | |
68126bad | 10195 | strcpy (asm_code, opcode); |
01d3224a | 10196 | |
284d86e9 | 10197 | if (which_alternative != 2) |
4df1190a | 10198 | return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); |
284d86e9 | 10199 | else |
68126bad EB |
10200 | return |
10201 | strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"); | |
284d86e9 | 10202 | } |
2be15d0f | 10203 | \f |
89a8b315 RH |
10204 | /* Output rtl to increment the profiler label LABELNO |
10205 | for profiling a function entry. */ | |
2be15d0f RH |
10206 | |
10207 | void | |
fc27d102 | 10208 | sparc_profile_hook (int labelno) |
2be15d0f RH |
10209 | { |
10210 | char buf[32]; | |
89a8b315 | 10211 | rtx lab, fun; |
2be15d0f | 10212 | |
89a8b315 | 10213 | fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION); |
cc44abe6 DM |
10214 | if (NO_PROFILE_COUNTERS) |
10215 | { | |
db69559b | 10216 | emit_library_call (fun, LCT_NORMAL, VOIDmode); |
cc44abe6 DM |
10217 | } |
10218 | else | |
10219 | { | |
10220 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
10221 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
db69559b | 10222 | emit_library_call (fun, LCT_NORMAL, VOIDmode, lab, Pmode); |
cc44abe6 | 10223 | } |
2be15d0f | 10224 | } |
89a8b315 | 10225 | \f |
2ca48caa | 10226 | #ifdef TARGET_SOLARIS |
d1ced155 EB |
10227 | /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */ |
10228 | ||
7c262518 | 10229 | static void |
d1ced155 EB |
10230 | sparc_solaris_elf_asm_named_section (const char *name, unsigned int flags, |
10231 | tree decl ATTRIBUTE_UNUSED) | |
7c262518 | 10232 | { |
2ca48caa RO |
10233 | if (HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE) |
10234 | { | |
10235 | solaris_elf_asm_comdat_section (name, flags, decl); | |
10236 | return; | |
10237 | } | |
10238 | ||
7c262518 RH |
10239 | fprintf (asm_out_file, "\t.section\t\"%s\"", name); |
10240 | ||
10241 | if (!(flags & SECTION_DEBUG)) | |
10242 | fputs (",#alloc", asm_out_file); | |
10243 | if (flags & SECTION_WRITE) | |
10244 | fputs (",#write", asm_out_file); | |
2f3321ca EB |
10245 | if (flags & SECTION_TLS) |
10246 | fputs (",#tls", asm_out_file); | |
7c262518 RH |
10247 | if (flags & SECTION_CODE) |
10248 | fputs (",#execinstr", asm_out_file); | |
10249 | ||
e6b6bf09 RO |
10250 | if (flags & SECTION_NOTYPE) |
10251 | ; | |
10252 | else if (flags & SECTION_BSS) | |
10253 | fputs (",#nobits", asm_out_file); | |
10254 | else | |
10255 | fputs (",#progbits", asm_out_file); | |
7c262518 RH |
10256 | |
10257 | fputc ('\n', asm_out_file); | |
10258 | } | |
2ca48caa | 10259 | #endif /* TARGET_SOLARIS */ |
f451b552 | 10260 | |
60b85c4c | 10261 | /* We do not allow indirect calls to be optimized into sibling calls. |
951661a1 EB |
10262 | |
10263 | We cannot use sibling calls when delayed branches are disabled | |
10264 | because they will likely require the call delay slot to be filled. | |
10265 | ||
60b85c4c | 10266 | Also, on SPARC 32-bit we cannot emit a sibling call when the |
4977bab6 ZW |
10267 | current function returns a structure. This is because the "unimp |
10268 | after call" convention would cause the callee to return to the | |
10269 | wrong place. The generic code already disallows cases where the | |
10270 | function being called returns a structure. | |
10271 | ||
10272 | It may seem strange how this last case could occur. Usually there | |
10273 | is code after the call which jumps to epilogue code which dumps the | |
10274 | return value into the struct return area. That ought to invalidate | |
951661a1 | 10275 | the sibling call right? Well, in the C++ case we can end up passing |
4977bab6 ZW |
10276 | the pointer to the struct return area to a constructor (which returns |
10277 | void) and then nothing else happens. Such a sibling call would look | |
1910440e RS |
10278 | valid without the added check here. |
10279 | ||
10280 | VxWorks PIC PLT entries require the global pointer to be initialized | |
10281 | on entry. We therefore can't emit sibling calls to them. */ | |
4977bab6 | 10282 | static bool |
fc27d102 | 10283 | sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
4977bab6 | 10284 | { |
951661a1 EB |
10285 | return (decl |
10286 | && flag_delayed_branch | |
e3b5732b | 10287 | && (TARGET_ARCH64 || ! cfun->returns_struct) |
1910440e RS |
10288 | && !(TARGET_VXWORKS_RTP |
10289 | && flag_pic | |
10290 | && !targetm.binds_local_p (decl))); | |
4977bab6 | 10291 | } |
c15c90bb ZW |
10292 | \f |
10293 | /* libfunc renaming. */ | |
c15c90bb ZW |
10294 | |
10295 | static void | |
10296 | sparc_init_libfuncs (void) | |
10297 | { | |
10298 | if (TARGET_ARCH32) | |
10299 | { | |
10300 | /* Use the subroutines that Sun's library provides for integer | |
10301 | multiply and divide. The `*' prevents an underscore from | |
10302 | being prepended by the compiler. .umul is a little faster | |
ff482c8d | 10303 | than .mul. */ |
c15c90bb ZW |
10304 | set_optab_libfunc (smul_optab, SImode, "*.umul"); |
10305 | set_optab_libfunc (sdiv_optab, SImode, "*.div"); | |
10306 | set_optab_libfunc (udiv_optab, SImode, "*.udiv"); | |
10307 | set_optab_libfunc (smod_optab, SImode, "*.rem"); | |
10308 | set_optab_libfunc (umod_optab, SImode, "*.urem"); | |
10309 | ||
10310 | /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */ | |
10311 | set_optab_libfunc (add_optab, TFmode, "_Q_add"); | |
10312 | set_optab_libfunc (sub_optab, TFmode, "_Q_sub"); | |
10313 | set_optab_libfunc (neg_optab, TFmode, "_Q_neg"); | |
10314 | set_optab_libfunc (smul_optab, TFmode, "_Q_mul"); | |
10315 | set_optab_libfunc (sdiv_optab, TFmode, "_Q_div"); | |
10316 | ||
10317 | /* We can define the TFmode sqrt optab only if TARGET_FPU. This | |
10318 | is because with soft-float, the SFmode and DFmode sqrt | |
10319 | instructions will be absent, and the compiler will notice and | |
10320 | try to use the TFmode sqrt instruction for calls to the | |
10321 | builtin function sqrt, but this fails. */ | |
10322 | if (TARGET_FPU) | |
10323 | set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt"); | |
10324 | ||
c9034561 ZW |
10325 | set_optab_libfunc (eq_optab, TFmode, "_Q_feq"); |
10326 | set_optab_libfunc (ne_optab, TFmode, "_Q_fne"); | |
10327 | set_optab_libfunc (gt_optab, TFmode, "_Q_fgt"); | |
10328 | set_optab_libfunc (ge_optab, TFmode, "_Q_fge"); | |
10329 | set_optab_libfunc (lt_optab, TFmode, "_Q_flt"); | |
10330 | set_optab_libfunc (le_optab, TFmode, "_Q_fle"); | |
c15c90bb | 10331 | |
85363ca0 ZW |
10332 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq"); |
10333 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq"); | |
10334 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos"); | |
10335 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod"); | |
10336 | ||
10337 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi"); | |
10338 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou"); | |
10339 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq"); | |
9b336fa4 | 10340 | set_conv_libfunc (ufloat_optab, TFmode, SImode, "_Q_utoq"); |
c15c90bb | 10341 | |
45dcc026 JJ |
10342 | if (DITF_CONVERSION_LIBFUNCS) |
10343 | { | |
10344 | set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll"); | |
10345 | set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull"); | |
10346 | set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq"); | |
9b336fa4 | 10347 | set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq"); |
45dcc026 JJ |
10348 | } |
10349 | ||
c15c90bb ZW |
10350 | if (SUN_CONVERSION_LIBFUNCS) |
10351 | { | |
85363ca0 ZW |
10352 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); |
10353 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); | |
10354 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); | |
10355 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); | |
c15c90bb ZW |
10356 | } |
10357 | } | |
10358 | if (TARGET_ARCH64) | |
10359 | { | |
10360 | /* In the SPARC 64bit ABI, SImode multiply and divide functions | |
10361 | do not exist in the library. Make sure the compiler does not | |
10362 | emit calls to them by accident. (It should always use the | |
10363 | hardware instructions.) */ | |
10364 | set_optab_libfunc (smul_optab, SImode, 0); | |
10365 | set_optab_libfunc (sdiv_optab, SImode, 0); | |
10366 | set_optab_libfunc (udiv_optab, SImode, 0); | |
10367 | set_optab_libfunc (smod_optab, SImode, 0); | |
10368 | set_optab_libfunc (umod_optab, SImode, 0); | |
10369 | ||
10370 | if (SUN_INTEGER_MULTIPLY_64) | |
10371 | { | |
10372 | set_optab_libfunc (smul_optab, DImode, "__mul64"); | |
10373 | set_optab_libfunc (sdiv_optab, DImode, "__div64"); | |
10374 | set_optab_libfunc (udiv_optab, DImode, "__udiv64"); | |
10375 | set_optab_libfunc (smod_optab, DImode, "__rem64"); | |
10376 | set_optab_libfunc (umod_optab, DImode, "__urem64"); | |
10377 | } | |
10378 | ||
10379 | if (SUN_CONVERSION_LIBFUNCS) | |
10380 | { | |
85363ca0 ZW |
10381 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol"); |
10382 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul"); | |
10383 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol"); | |
10384 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul"); | |
c15c90bb ZW |
10385 | } |
10386 | } | |
c15c90bb ZW |
10387 | } |
10388 | \f | |
fde66fde EB |
10389 | /* SPARC builtins. */ |
10390 | enum sparc_builtins | |
10391 | { | |
10392 | /* FPU builtins. */ | |
10393 | SPARC_BUILTIN_LDFSR, | |
10394 | SPARC_BUILTIN_STFSR, | |
10395 | ||
10396 | /* VIS 1.0 builtins. */ | |
10397 | SPARC_BUILTIN_FPACK16, | |
10398 | SPARC_BUILTIN_FPACK32, | |
10399 | SPARC_BUILTIN_FPACKFIX, | |
10400 | SPARC_BUILTIN_FEXPAND, | |
10401 | SPARC_BUILTIN_FPMERGE, | |
10402 | SPARC_BUILTIN_FMUL8X16, | |
10403 | SPARC_BUILTIN_FMUL8X16AU, | |
10404 | SPARC_BUILTIN_FMUL8X16AL, | |
10405 | SPARC_BUILTIN_FMUL8SUX16, | |
10406 | SPARC_BUILTIN_FMUL8ULX16, | |
10407 | SPARC_BUILTIN_FMULD8SUX16, | |
10408 | SPARC_BUILTIN_FMULD8ULX16, | |
10409 | SPARC_BUILTIN_FALIGNDATAV4HI, | |
10410 | SPARC_BUILTIN_FALIGNDATAV8QI, | |
10411 | SPARC_BUILTIN_FALIGNDATAV2SI, | |
10412 | SPARC_BUILTIN_FALIGNDATADI, | |
10413 | SPARC_BUILTIN_WRGSR, | |
10414 | SPARC_BUILTIN_RDGSR, | |
10415 | SPARC_BUILTIN_ALIGNADDR, | |
10416 | SPARC_BUILTIN_ALIGNADDRL, | |
10417 | SPARC_BUILTIN_PDIST, | |
10418 | SPARC_BUILTIN_EDGE8, | |
10419 | SPARC_BUILTIN_EDGE8L, | |
10420 | SPARC_BUILTIN_EDGE16, | |
10421 | SPARC_BUILTIN_EDGE16L, | |
10422 | SPARC_BUILTIN_EDGE32, | |
10423 | SPARC_BUILTIN_EDGE32L, | |
10424 | SPARC_BUILTIN_FCMPLE16, | |
10425 | SPARC_BUILTIN_FCMPLE32, | |
10426 | SPARC_BUILTIN_FCMPNE16, | |
10427 | SPARC_BUILTIN_FCMPNE32, | |
10428 | SPARC_BUILTIN_FCMPGT16, | |
10429 | SPARC_BUILTIN_FCMPGT32, | |
10430 | SPARC_BUILTIN_FCMPEQ16, | |
10431 | SPARC_BUILTIN_FCMPEQ32, | |
10432 | SPARC_BUILTIN_FPADD16, | |
10433 | SPARC_BUILTIN_FPADD16S, | |
10434 | SPARC_BUILTIN_FPADD32, | |
10435 | SPARC_BUILTIN_FPADD32S, | |
10436 | SPARC_BUILTIN_FPSUB16, | |
10437 | SPARC_BUILTIN_FPSUB16S, | |
10438 | SPARC_BUILTIN_FPSUB32, | |
10439 | SPARC_BUILTIN_FPSUB32S, | |
10440 | SPARC_BUILTIN_ARRAY8, | |
10441 | SPARC_BUILTIN_ARRAY16, | |
10442 | SPARC_BUILTIN_ARRAY32, | |
10443 | ||
10444 | /* VIS 2.0 builtins. */ | |
10445 | SPARC_BUILTIN_EDGE8N, | |
10446 | SPARC_BUILTIN_EDGE8LN, | |
10447 | SPARC_BUILTIN_EDGE16N, | |
10448 | SPARC_BUILTIN_EDGE16LN, | |
10449 | SPARC_BUILTIN_EDGE32N, | |
10450 | SPARC_BUILTIN_EDGE32LN, | |
10451 | SPARC_BUILTIN_BMASK, | |
10452 | SPARC_BUILTIN_BSHUFFLEV4HI, | |
10453 | SPARC_BUILTIN_BSHUFFLEV8QI, | |
10454 | SPARC_BUILTIN_BSHUFFLEV2SI, | |
10455 | SPARC_BUILTIN_BSHUFFLEDI, | |
10456 | ||
10457 | /* VIS 3.0 builtins. */ | |
10458 | SPARC_BUILTIN_CMASK8, | |
10459 | SPARC_BUILTIN_CMASK16, | |
10460 | SPARC_BUILTIN_CMASK32, | |
10461 | SPARC_BUILTIN_FCHKSM16, | |
10462 | SPARC_BUILTIN_FSLL16, | |
10463 | SPARC_BUILTIN_FSLAS16, | |
10464 | SPARC_BUILTIN_FSRL16, | |
10465 | SPARC_BUILTIN_FSRA16, | |
10466 | SPARC_BUILTIN_FSLL32, | |
10467 | SPARC_BUILTIN_FSLAS32, | |
10468 | SPARC_BUILTIN_FSRL32, | |
10469 | SPARC_BUILTIN_FSRA32, | |
10470 | SPARC_BUILTIN_PDISTN, | |
10471 | SPARC_BUILTIN_FMEAN16, | |
10472 | SPARC_BUILTIN_FPADD64, | |
10473 | SPARC_BUILTIN_FPSUB64, | |
10474 | SPARC_BUILTIN_FPADDS16, | |
10475 | SPARC_BUILTIN_FPADDS16S, | |
10476 | SPARC_BUILTIN_FPSUBS16, | |
10477 | SPARC_BUILTIN_FPSUBS16S, | |
10478 | SPARC_BUILTIN_FPADDS32, | |
10479 | SPARC_BUILTIN_FPADDS32S, | |
10480 | SPARC_BUILTIN_FPSUBS32, | |
10481 | SPARC_BUILTIN_FPSUBS32S, | |
10482 | SPARC_BUILTIN_FUCMPLE8, | |
10483 | SPARC_BUILTIN_FUCMPNE8, | |
10484 | SPARC_BUILTIN_FUCMPGT8, | |
10485 | SPARC_BUILTIN_FUCMPEQ8, | |
10486 | SPARC_BUILTIN_FHADDS, | |
10487 | SPARC_BUILTIN_FHADDD, | |
10488 | SPARC_BUILTIN_FHSUBS, | |
10489 | SPARC_BUILTIN_FHSUBD, | |
10490 | SPARC_BUILTIN_FNHADDS, | |
10491 | SPARC_BUILTIN_FNHADDD, | |
10492 | SPARC_BUILTIN_UMULXHI, | |
10493 | SPARC_BUILTIN_XMULX, | |
10494 | SPARC_BUILTIN_XMULXHI, | |
10495 | ||
690f24b7 JM |
10496 | /* VIS 4.0 builtins. */ |
10497 | SPARC_BUILTIN_FPADD8, | |
10498 | SPARC_BUILTIN_FPADDS8, | |
10499 | SPARC_BUILTIN_FPADDUS8, | |
10500 | SPARC_BUILTIN_FPADDUS16, | |
10501 | SPARC_BUILTIN_FPCMPLE8, | |
10502 | SPARC_BUILTIN_FPCMPGT8, | |
10503 | SPARC_BUILTIN_FPCMPULE16, | |
10504 | SPARC_BUILTIN_FPCMPUGT16, | |
10505 | SPARC_BUILTIN_FPCMPULE32, | |
10506 | SPARC_BUILTIN_FPCMPUGT32, | |
10507 | SPARC_BUILTIN_FPMAX8, | |
10508 | SPARC_BUILTIN_FPMAX16, | |
10509 | SPARC_BUILTIN_FPMAX32, | |
10510 | SPARC_BUILTIN_FPMAXU8, | |
10511 | SPARC_BUILTIN_FPMAXU16, | |
10512 | SPARC_BUILTIN_FPMAXU32, | |
10513 | SPARC_BUILTIN_FPMIN8, | |
10514 | SPARC_BUILTIN_FPMIN16, | |
10515 | SPARC_BUILTIN_FPMIN32, | |
10516 | SPARC_BUILTIN_FPMINU8, | |
10517 | SPARC_BUILTIN_FPMINU16, | |
10518 | SPARC_BUILTIN_FPMINU32, | |
10519 | SPARC_BUILTIN_FPSUB8, | |
10520 | SPARC_BUILTIN_FPSUBS8, | |
10521 | SPARC_BUILTIN_FPSUBUS8, | |
10522 | SPARC_BUILTIN_FPSUBUS16, | |
bcc3c3f1 JM |
10523 | |
10524 | /* VIS 4.0B builtins. */ | |
10525 | ||
10526 | /* Note that all the DICTUNPACK* entries should be kept | |
10527 | contiguous. */ | |
10528 | SPARC_BUILTIN_FIRST_DICTUNPACK, | |
10529 | SPARC_BUILTIN_DICTUNPACK8 = SPARC_BUILTIN_FIRST_DICTUNPACK, | |
10530 | SPARC_BUILTIN_DICTUNPACK16, | |
10531 | SPARC_BUILTIN_DICTUNPACK32, | |
10532 | SPARC_BUILTIN_LAST_DICTUNPACK = SPARC_BUILTIN_DICTUNPACK32, | |
10533 | ||
10534 | /* Note that all the FPCMP*SHL entries should be kept | |
10535 | contiguous. */ | |
10536 | SPARC_BUILTIN_FIRST_FPCMPSHL, | |
10537 | SPARC_BUILTIN_FPCMPLE8SHL = SPARC_BUILTIN_FIRST_FPCMPSHL, | |
10538 | SPARC_BUILTIN_FPCMPGT8SHL, | |
10539 | SPARC_BUILTIN_FPCMPEQ8SHL, | |
10540 | SPARC_BUILTIN_FPCMPNE8SHL, | |
10541 | SPARC_BUILTIN_FPCMPLE16SHL, | |
10542 | SPARC_BUILTIN_FPCMPGT16SHL, | |
10543 | SPARC_BUILTIN_FPCMPEQ16SHL, | |
10544 | SPARC_BUILTIN_FPCMPNE16SHL, | |
10545 | SPARC_BUILTIN_FPCMPLE32SHL, | |
10546 | SPARC_BUILTIN_FPCMPGT32SHL, | |
10547 | SPARC_BUILTIN_FPCMPEQ32SHL, | |
10548 | SPARC_BUILTIN_FPCMPNE32SHL, | |
10549 | SPARC_BUILTIN_FPCMPULE8SHL, | |
10550 | SPARC_BUILTIN_FPCMPUGT8SHL, | |
10551 | SPARC_BUILTIN_FPCMPULE16SHL, | |
10552 | SPARC_BUILTIN_FPCMPUGT16SHL, | |
10553 | SPARC_BUILTIN_FPCMPULE32SHL, | |
10554 | SPARC_BUILTIN_FPCMPUGT32SHL, | |
10555 | SPARC_BUILTIN_FPCMPDE8SHL, | |
10556 | SPARC_BUILTIN_FPCMPDE16SHL, | |
10557 | SPARC_BUILTIN_FPCMPDE32SHL, | |
10558 | SPARC_BUILTIN_FPCMPUR8SHL, | |
10559 | SPARC_BUILTIN_FPCMPUR16SHL, | |
10560 | SPARC_BUILTIN_FPCMPUR32SHL, | |
10561 | SPARC_BUILTIN_LAST_FPCMPSHL = SPARC_BUILTIN_FPCMPUR32SHL, | |
690f24b7 | 10562 | |
fde66fde EB |
10563 | SPARC_BUILTIN_MAX |
10564 | }; | |
10565 | ||
10566 | static GTY (()) tree sparc_builtins[(int) SPARC_BUILTIN_MAX]; | |
10567 | static enum insn_code sparc_builtins_icode[(int) SPARC_BUILTIN_MAX]; | |
10568 | ||
bcc3c3f1 JM |
10569 | /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE. |
10570 | The instruction should require a constant operand of some sort. The | |
10571 | function prints an error if OPVAL is not valid. */ | |
10572 | ||
10573 | static int | |
10574 | check_constant_argument (enum insn_code icode, int opnum, rtx opval) | |
10575 | { | |
10576 | if (GET_CODE (opval) != CONST_INT) | |
10577 | { | |
10578 | error ("%qs expects a constant argument", insn_data[icode].name); | |
10579 | return false; | |
10580 | } | |
10581 | ||
10582 | if (!(*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode)) | |
10583 | { | |
10584 | error ("constant argument out of range for %qs", insn_data[icode].name); | |
10585 | return false; | |
10586 | } | |
10587 | return true; | |
10588 | } | |
10589 | ||
fde66fde EB |
10590 | /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the |
10591 | function decl or NULL_TREE if the builtin was not added. */ | |
10592 | ||
10593 | static tree | |
10594 | def_builtin (const char *name, enum insn_code icode, enum sparc_builtins code, | |
10595 | tree type) | |
3653988e | 10596 | { |
fde66fde EB |
10597 | tree t |
10598 | = add_builtin_function (name, type, code, BUILT_IN_MD, NULL, NULL_TREE); | |
10599 | ||
10600 | if (t) | |
10601 | { | |
10602 | sparc_builtins[code] = t; | |
10603 | sparc_builtins_icode[code] = icode; | |
10604 | } | |
10605 | ||
10606 | return t; | |
3653988e DM |
10607 | } |
10608 | ||
fde66fde EB |
10609 | /* Likewise, but also marks the function as "const". */ |
10610 | ||
10611 | static tree | |
10612 | def_builtin_const (const char *name, enum insn_code icode, | |
10613 | enum sparc_builtins code, tree type) | |
3653988e | 10614 | { |
fde66fde | 10615 | tree t = def_builtin (name, icode, code, type); |
3653988e DM |
10616 | |
10617 | if (t) | |
10618 | TREE_READONLY (t) = 1; | |
10619 | ||
10620 | return t; | |
10621 | } | |
16f59241 JM |
10622 | |
10623 | /* Implement the TARGET_INIT_BUILTINS target hook. | |
10624 | Create builtin functions for special SPARC instructions. */ | |
10625 | ||
10626 | static void | |
10627 | sparc_init_builtins (void) | |
10628 | { | |
fde66fde EB |
10629 | if (TARGET_FPU) |
10630 | sparc_fpu_init_builtins (); | |
10631 | ||
16f59241 JM |
10632 | if (TARGET_VIS) |
10633 | sparc_vis_init_builtins (); | |
10634 | } | |
10635 | ||
fde66fde EB |
10636 | /* Create builtin functions for FPU instructions. */ |
10637 | ||
10638 | static void | |
10639 | sparc_fpu_init_builtins (void) | |
10640 | { | |
10641 | tree ftype | |
10642 | = build_function_type_list (void_type_node, | |
10643 | build_pointer_type (unsigned_type_node), 0); | |
10644 | def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr, | |
10645 | SPARC_BUILTIN_LDFSR, ftype); | |
10646 | def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr, | |
10647 | SPARC_BUILTIN_STFSR, ftype); | |
10648 | } | |
10649 | ||
10650 | /* Create builtin functions for VIS instructions. */ | |
16f59241 JM |
10651 | |
10652 | static void | |
10653 | sparc_vis_init_builtins (void) | |
10654 | { | |
10655 | tree v4qi = build_vector_type (unsigned_intQI_type_node, 4); | |
10656 | tree v8qi = build_vector_type (unsigned_intQI_type_node, 8); | |
10657 | tree v4hi = build_vector_type (intHI_type_node, 4); | |
10658 | tree v2hi = build_vector_type (intHI_type_node, 2); | |
10659 | tree v2si = build_vector_type (intSI_type_node, 2); | |
f14e0262 | 10660 | tree v1si = build_vector_type (intSI_type_node, 1); |
16f59241 JM |
10661 | |
10662 | tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0); | |
10663 | tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0); | |
10664 | tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0); | |
10665 | tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0); | |
10666 | tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0); | |
10667 | tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0); | |
10668 | tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0); | |
10669 | tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0); | |
10670 | tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0); | |
10671 | tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0); | |
10672 | tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0); | |
10673 | tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0); | |
f14e0262 DM |
10674 | tree v2hi_ftype_v2hi_v2hi = build_function_type_list (v2hi, v2hi, v2hi, 0); |
10675 | tree v1si_ftype_v1si_v1si = build_function_type_list (v1si, v1si, v1si, 0); | |
16f59241 JM |
10676 | tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node, |
10677 | v8qi, v8qi, | |
10678 | intDI_type_node, 0); | |
96d7b15f DM |
10679 | tree di_ftype_v8qi_v8qi = build_function_type_list (intDI_type_node, |
10680 | v8qi, v8qi, 0); | |
10681 | tree si_ftype_v8qi_v8qi = build_function_type_list (intSI_type_node, | |
10682 | v8qi, v8qi, 0); | |
bcc3c3f1 JM |
10683 | tree v8qi_ftype_df_si = build_function_type_list (v8qi, double_type_node, |
10684 | intSI_type_node, 0); | |
10685 | tree v4hi_ftype_df_si = build_function_type_list (v4hi, double_type_node, | |
10686 | intSI_type_node, 0); | |
10687 | tree v2si_ftype_df_si = build_function_type_list (v2si, double_type_node, | |
10688 | intDI_type_node, 0); | |
16f59241 JM |
10689 | tree di_ftype_di_di = build_function_type_list (intDI_type_node, |
10690 | intDI_type_node, | |
10691 | intDI_type_node, 0); | |
1ec01ab2 DM |
10692 | tree si_ftype_si_si = build_function_type_list (intSI_type_node, |
10693 | intSI_type_node, | |
10694 | intSI_type_node, 0); | |
16f59241 JM |
10695 | tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node, |
10696 | ptr_type_node, | |
10697 | intSI_type_node, 0); | |
10698 | tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node, | |
10699 | ptr_type_node, | |
10700 | intDI_type_node, 0); | |
47640f40 DM |
10701 | tree si_ftype_ptr_ptr = build_function_type_list (intSI_type_node, |
10702 | ptr_type_node, | |
10703 | ptr_type_node, 0); | |
cb8bbba8 DM |
10704 | tree di_ftype_ptr_ptr = build_function_type_list (intDI_type_node, |
10705 | ptr_type_node, | |
10706 | ptr_type_node, 0); | |
f4d7f828 DM |
10707 | tree si_ftype_v4hi_v4hi = build_function_type_list (intSI_type_node, |
10708 | v4hi, v4hi, 0); | |
10709 | tree si_ftype_v2si_v2si = build_function_type_list (intSI_type_node, | |
10710 | v2si, v2si, 0); | |
cb8bbba8 DM |
10711 | tree di_ftype_v4hi_v4hi = build_function_type_list (intDI_type_node, |
10712 | v4hi, v4hi, 0); | |
10713 | tree di_ftype_v2si_v2si = build_function_type_list (intDI_type_node, | |
10714 | v2si, v2si, 0); | |
10b859c0 DM |
10715 | tree void_ftype_di = build_function_type_list (void_type_node, |
10716 | intDI_type_node, 0); | |
10717 | tree di_ftype_void = build_function_type_list (intDI_type_node, | |
10718 | void_type_node, 0); | |
96d7b15f DM |
10719 | tree void_ftype_si = build_function_type_list (void_type_node, |
10720 | intSI_type_node, 0); | |
facb3fd7 DM |
10721 | tree sf_ftype_sf_sf = build_function_type_list (float_type_node, |
10722 | float_type_node, | |
10723 | float_type_node, 0); | |
10724 | tree df_ftype_df_df = build_function_type_list (double_type_node, | |
10725 | double_type_node, | |
10726 | double_type_node, 0); | |
16f59241 JM |
10727 | |
10728 | /* Packing and expanding vectors. */ | |
f0d07099 | 10729 | def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis, |
fde66fde | 10730 | SPARC_BUILTIN_FPACK16, v4qi_ftype_v4hi); |
f0d07099 | 10731 | def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis, |
fde66fde | 10732 | SPARC_BUILTIN_FPACK32, v8qi_ftype_v2si_v8qi); |
f0d07099 | 10733 | def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis, |
fde66fde | 10734 | SPARC_BUILTIN_FPACKFIX, v2hi_ftype_v2si); |
3653988e | 10735 | def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis, |
fde66fde | 10736 | SPARC_BUILTIN_FEXPAND, v4hi_ftype_v4qi); |
3653988e | 10737 | def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis, |
fde66fde | 10738 | SPARC_BUILTIN_FPMERGE, v8qi_ftype_v4qi_v4qi); |
16f59241 JM |
10739 | |
10740 | /* Multiplications. */ | |
3653988e | 10741 | def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis, |
fde66fde | 10742 | SPARC_BUILTIN_FMUL8X16, v4hi_ftype_v4qi_v4hi); |
3653988e | 10743 | def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis, |
fde66fde | 10744 | SPARC_BUILTIN_FMUL8X16AU, v4hi_ftype_v4qi_v2hi); |
3653988e | 10745 | def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis, |
fde66fde | 10746 | SPARC_BUILTIN_FMUL8X16AL, v4hi_ftype_v4qi_v2hi); |
3653988e | 10747 | def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis, |
fde66fde | 10748 | SPARC_BUILTIN_FMUL8SUX16, v4hi_ftype_v8qi_v4hi); |
3653988e | 10749 | def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis, |
fde66fde | 10750 | SPARC_BUILTIN_FMUL8ULX16, v4hi_ftype_v8qi_v4hi); |
3653988e | 10751 | def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis, |
fde66fde | 10752 | SPARC_BUILTIN_FMULD8SUX16, v2si_ftype_v4qi_v2hi); |
3653988e | 10753 | def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis, |
fde66fde | 10754 | SPARC_BUILTIN_FMULD8ULX16, v2si_ftype_v4qi_v2hi); |
16f59241 JM |
10755 | |
10756 | /* Data aligning. */ | |
10757 | def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis, | |
fde66fde | 10758 | SPARC_BUILTIN_FALIGNDATAV4HI, v4hi_ftype_v4hi_v4hi); |
16f59241 | 10759 | def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis, |
fde66fde | 10760 | SPARC_BUILTIN_FALIGNDATAV8QI, v8qi_ftype_v8qi_v8qi); |
16f59241 | 10761 | def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis, |
fde66fde | 10762 | SPARC_BUILTIN_FALIGNDATAV2SI, v2si_ftype_v2si_v2si); |
e00560c2 | 10763 | def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis, |
fde66fde | 10764 | SPARC_BUILTIN_FALIGNDATADI, di_ftype_di_di); |
10b859c0 DM |
10765 | |
10766 | def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis, | |
fde66fde | 10767 | SPARC_BUILTIN_WRGSR, void_ftype_di); |
10b859c0 | 10768 | def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis, |
fde66fde | 10769 | SPARC_BUILTIN_RDGSR, di_ftype_void); |
10b859c0 | 10770 | |
16f59241 | 10771 | if (TARGET_ARCH64) |
47640f40 DM |
10772 | { |
10773 | def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis, | |
fde66fde | 10774 | SPARC_BUILTIN_ALIGNADDR, ptr_ftype_ptr_di); |
47640f40 | 10775 | def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis, |
fde66fde | 10776 | SPARC_BUILTIN_ALIGNADDRL, ptr_ftype_ptr_di); |
47640f40 | 10777 | } |
16f59241 | 10778 | else |
47640f40 DM |
10779 | { |
10780 | def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis, | |
fde66fde | 10781 | SPARC_BUILTIN_ALIGNADDR, ptr_ftype_ptr_si); |
47640f40 | 10782 | def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis, |
fde66fde | 10783 | SPARC_BUILTIN_ALIGNADDRL, ptr_ftype_ptr_si); |
47640f40 | 10784 | } |
16f59241 JM |
10785 | |
10786 | /* Pixel distance. */ | |
3653988e | 10787 | def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis, |
fde66fde | 10788 | SPARC_BUILTIN_PDIST, di_ftype_v8qi_v8qi_di); |
b1e4f4dd DM |
10789 | |
10790 | /* Edge handling. */ | |
47640f40 DM |
10791 | if (TARGET_ARCH64) |
10792 | { | |
3653988e | 10793 | def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis, |
fde66fde | 10794 | SPARC_BUILTIN_EDGE8, di_ftype_ptr_ptr); |
3653988e | 10795 | def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis, |
fde66fde | 10796 | SPARC_BUILTIN_EDGE8L, di_ftype_ptr_ptr); |
3653988e | 10797 | def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis, |
fde66fde | 10798 | SPARC_BUILTIN_EDGE16, di_ftype_ptr_ptr); |
3653988e | 10799 | def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis, |
fde66fde | 10800 | SPARC_BUILTIN_EDGE16L, di_ftype_ptr_ptr); |
3653988e | 10801 | def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis, |
fde66fde | 10802 | SPARC_BUILTIN_EDGE32, di_ftype_ptr_ptr); |
3653988e | 10803 | def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis, |
fde66fde | 10804 | SPARC_BUILTIN_EDGE32L, di_ftype_ptr_ptr); |
47640f40 DM |
10805 | } |
10806 | else | |
10807 | { | |
3653988e | 10808 | def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis, |
fde66fde | 10809 | SPARC_BUILTIN_EDGE8, si_ftype_ptr_ptr); |
3653988e | 10810 | def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis, |
fde66fde | 10811 | SPARC_BUILTIN_EDGE8L, si_ftype_ptr_ptr); |
3653988e | 10812 | def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis, |
fde66fde | 10813 | SPARC_BUILTIN_EDGE16, si_ftype_ptr_ptr); |
3653988e | 10814 | def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis, |
fde66fde | 10815 | SPARC_BUILTIN_EDGE16L, si_ftype_ptr_ptr); |
3653988e | 10816 | def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis, |
fde66fde | 10817 | SPARC_BUILTIN_EDGE32, si_ftype_ptr_ptr); |
3653988e | 10818 | def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis, |
fde66fde | 10819 | SPARC_BUILTIN_EDGE32L, si_ftype_ptr_ptr); |
47640f40 | 10820 | } |
f4d7f828 | 10821 | |
cb8bbba8 DM |
10822 | /* Pixel compare. */ |
10823 | if (TARGET_ARCH64) | |
10824 | { | |
10825 | def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis, | |
fde66fde | 10826 | SPARC_BUILTIN_FCMPLE16, di_ftype_v4hi_v4hi); |
cb8bbba8 | 10827 | def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis, |
fde66fde | 10828 | SPARC_BUILTIN_FCMPLE32, di_ftype_v2si_v2si); |
cb8bbba8 | 10829 | def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis, |
fde66fde | 10830 | SPARC_BUILTIN_FCMPNE16, di_ftype_v4hi_v4hi); |
cb8bbba8 | 10831 | def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis, |
fde66fde | 10832 | SPARC_BUILTIN_FCMPNE32, di_ftype_v2si_v2si); |
cb8bbba8 | 10833 | def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis, |
fde66fde | 10834 | SPARC_BUILTIN_FCMPGT16, di_ftype_v4hi_v4hi); |
cb8bbba8 | 10835 | def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis, |
fde66fde | 10836 | SPARC_BUILTIN_FCMPGT32, di_ftype_v2si_v2si); |
cb8bbba8 | 10837 | def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis, |
fde66fde | 10838 | SPARC_BUILTIN_FCMPEQ16, di_ftype_v4hi_v4hi); |
cb8bbba8 | 10839 | def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis, |
fde66fde | 10840 | SPARC_BUILTIN_FCMPEQ32, di_ftype_v2si_v2si); |
cb8bbba8 DM |
10841 | } |
10842 | else | |
10843 | { | |
10844 | def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis, | |
fde66fde | 10845 | SPARC_BUILTIN_FCMPLE16, si_ftype_v4hi_v4hi); |
cb8bbba8 | 10846 | def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis, |
fde66fde | 10847 | SPARC_BUILTIN_FCMPLE32, si_ftype_v2si_v2si); |
cb8bbba8 | 10848 | def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis, |
fde66fde | 10849 | SPARC_BUILTIN_FCMPNE16, si_ftype_v4hi_v4hi); |
cb8bbba8 | 10850 | def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis, |
fde66fde | 10851 | SPARC_BUILTIN_FCMPNE32, si_ftype_v2si_v2si); |
cb8bbba8 | 10852 | def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis, |
fde66fde | 10853 | SPARC_BUILTIN_FCMPGT16, si_ftype_v4hi_v4hi); |
cb8bbba8 | 10854 | def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis, |
fde66fde | 10855 | SPARC_BUILTIN_FCMPGT32, si_ftype_v2si_v2si); |
cb8bbba8 | 10856 | def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis, |
fde66fde | 10857 | SPARC_BUILTIN_FCMPEQ16, si_ftype_v4hi_v4hi); |
cb8bbba8 | 10858 | def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis, |
fde66fde | 10859 | SPARC_BUILTIN_FCMPEQ32, si_ftype_v2si_v2si); |
cb8bbba8 | 10860 | } |
f14e0262 DM |
10861 | |
10862 | /* Addition and subtraction. */ | |
10863 | def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3, | |
fde66fde | 10864 | SPARC_BUILTIN_FPADD16, v4hi_ftype_v4hi_v4hi); |
f14e0262 | 10865 | def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3, |
fde66fde | 10866 | SPARC_BUILTIN_FPADD16S, v2hi_ftype_v2hi_v2hi); |
f14e0262 | 10867 | def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3, |
fde66fde | 10868 | SPARC_BUILTIN_FPADD32, v2si_ftype_v2si_v2si); |
e00560c2 | 10869 | def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3, |
fde66fde | 10870 | SPARC_BUILTIN_FPADD32S, v1si_ftype_v1si_v1si); |
f14e0262 | 10871 | def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3, |
fde66fde | 10872 | SPARC_BUILTIN_FPSUB16, v4hi_ftype_v4hi_v4hi); |
f14e0262 | 10873 | def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3, |
fde66fde | 10874 | SPARC_BUILTIN_FPSUB16S, v2hi_ftype_v2hi_v2hi); |
f14e0262 | 10875 | def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3, |
fde66fde | 10876 | SPARC_BUILTIN_FPSUB32, v2si_ftype_v2si_v2si); |
e00560c2 | 10877 | def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3, |
fde66fde | 10878 | SPARC_BUILTIN_FPSUB32S, v1si_ftype_v1si_v1si); |
1ec01ab2 DM |
10879 | |
10880 | /* Three-dimensional array addressing. */ | |
10881 | if (TARGET_ARCH64) | |
10882 | { | |
10883 | def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis, | |
fde66fde | 10884 | SPARC_BUILTIN_ARRAY8, di_ftype_di_di); |
1ec01ab2 | 10885 | def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis, |
fde66fde | 10886 | SPARC_BUILTIN_ARRAY16, di_ftype_di_di); |
1ec01ab2 | 10887 | def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis, |
fde66fde | 10888 | SPARC_BUILTIN_ARRAY32, di_ftype_di_di); |
1ec01ab2 DM |
10889 | } |
10890 | else | |
10891 | { | |
10892 | def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis, | |
fde66fde | 10893 | SPARC_BUILTIN_ARRAY8, si_ftype_si_si); |
1ec01ab2 | 10894 | def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis, |
fde66fde | 10895 | SPARC_BUILTIN_ARRAY16, si_ftype_si_si); |
1ec01ab2 | 10896 | def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis, |
fde66fde EB |
10897 | SPARC_BUILTIN_ARRAY32, si_ftype_si_si); |
10898 | } | |
c4728c6b DM |
10899 | |
10900 | if (TARGET_VIS2) | |
10901 | { | |
fde66fde EB |
10902 | /* Edge handling. */ |
10903 | if (TARGET_ARCH64) | |
10904 | { | |
10905 | def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis, | |
10906 | SPARC_BUILTIN_EDGE8N, di_ftype_ptr_ptr); | |
10907 | def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis, | |
10908 | SPARC_BUILTIN_EDGE8LN, di_ftype_ptr_ptr); | |
10909 | def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis, | |
10910 | SPARC_BUILTIN_EDGE16N, di_ftype_ptr_ptr); | |
10911 | def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis, | |
10912 | SPARC_BUILTIN_EDGE16LN, di_ftype_ptr_ptr); | |
10913 | def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis, | |
10914 | SPARC_BUILTIN_EDGE32N, di_ftype_ptr_ptr); | |
10915 | def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis, | |
10916 | SPARC_BUILTIN_EDGE32LN, di_ftype_ptr_ptr); | |
10917 | } | |
10918 | else | |
10919 | { | |
10920 | def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis, | |
10921 | SPARC_BUILTIN_EDGE8N, si_ftype_ptr_ptr); | |
10922 | def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis, | |
10923 | SPARC_BUILTIN_EDGE8LN, si_ftype_ptr_ptr); | |
10924 | def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis, | |
10925 | SPARC_BUILTIN_EDGE16N, si_ftype_ptr_ptr); | |
10926 | def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis, | |
10927 | SPARC_BUILTIN_EDGE16LN, si_ftype_ptr_ptr); | |
10928 | def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis, | |
10929 | SPARC_BUILTIN_EDGE32N, si_ftype_ptr_ptr); | |
10930 | def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis, | |
10931 | SPARC_BUILTIN_EDGE32LN, si_ftype_ptr_ptr); | |
10932 | } | |
10933 | ||
10934 | /* Byte mask and shuffle. */ | |
c4728c6b DM |
10935 | if (TARGET_ARCH64) |
10936 | def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis, | |
fde66fde | 10937 | SPARC_BUILTIN_BMASK, di_ftype_di_di); |
c4728c6b DM |
10938 | else |
10939 | def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis, | |
fde66fde | 10940 | SPARC_BUILTIN_BMASK, si_ftype_si_si); |
c4728c6b | 10941 | def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis, |
fde66fde | 10942 | SPARC_BUILTIN_BSHUFFLEV4HI, v4hi_ftype_v4hi_v4hi); |
c4728c6b | 10943 | def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis, |
fde66fde | 10944 | SPARC_BUILTIN_BSHUFFLEV8QI, v8qi_ftype_v8qi_v8qi); |
c4728c6b | 10945 | def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis, |
fde66fde | 10946 | SPARC_BUILTIN_BSHUFFLEV2SI, v2si_ftype_v2si_v2si); |
e00560c2 | 10947 | def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis, |
fde66fde | 10948 | SPARC_BUILTIN_BSHUFFLEDI, di_ftype_di_di); |
c4728c6b | 10949 | } |
96d7b15f DM |
10950 | |
10951 | if (TARGET_VIS3) | |
10952 | { | |
10953 | if (TARGET_ARCH64) | |
10954 | { | |
10955 | def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis, | |
fde66fde | 10956 | SPARC_BUILTIN_CMASK8, void_ftype_di); |
96d7b15f | 10957 | def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis, |
fde66fde | 10958 | SPARC_BUILTIN_CMASK16, void_ftype_di); |
96d7b15f | 10959 | def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis, |
fde66fde | 10960 | SPARC_BUILTIN_CMASK32, void_ftype_di); |
96d7b15f DM |
10961 | } |
10962 | else | |
10963 | { | |
10964 | def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis, | |
fde66fde | 10965 | SPARC_BUILTIN_CMASK8, void_ftype_si); |
96d7b15f | 10966 | def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis, |
fde66fde | 10967 | SPARC_BUILTIN_CMASK16, void_ftype_si); |
96d7b15f | 10968 | def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis, |
fde66fde | 10969 | SPARC_BUILTIN_CMASK32, void_ftype_si); |
96d7b15f DM |
10970 | } |
10971 | ||
10972 | def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis, | |
fde66fde | 10973 | SPARC_BUILTIN_FCHKSM16, v4hi_ftype_v4hi_v4hi); |
96d7b15f | 10974 | |
f1c141a7 | 10975 | def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3, |
fde66fde | 10976 | SPARC_BUILTIN_FSLL16, v4hi_ftype_v4hi_v4hi); |
f1c141a7 | 10977 | def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3, |
fde66fde | 10978 | SPARC_BUILTIN_FSLAS16, v4hi_ftype_v4hi_v4hi); |
f1c141a7 | 10979 | def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3, |
fde66fde | 10980 | SPARC_BUILTIN_FSRL16, v4hi_ftype_v4hi_v4hi); |
f1c141a7 | 10981 | def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3, |
fde66fde | 10982 | SPARC_BUILTIN_FSRA16, v4hi_ftype_v4hi_v4hi); |
f1c141a7 | 10983 | def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3, |
fde66fde | 10984 | SPARC_BUILTIN_FSLL32, v2si_ftype_v2si_v2si); |
f1c141a7 | 10985 | def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3, |
fde66fde | 10986 | SPARC_BUILTIN_FSLAS32, v2si_ftype_v2si_v2si); |
f1c141a7 | 10987 | def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3, |
fde66fde | 10988 | SPARC_BUILTIN_FSRL32, v2si_ftype_v2si_v2si); |
f1c141a7 | 10989 | def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3, |
fde66fde | 10990 | SPARC_BUILTIN_FSRA32, v2si_ftype_v2si_v2si); |
96d7b15f DM |
10991 | |
10992 | if (TARGET_ARCH64) | |
10993 | def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis, | |
fde66fde | 10994 | SPARC_BUILTIN_PDISTN, di_ftype_v8qi_v8qi); |
96d7b15f DM |
10995 | else |
10996 | def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis, | |
fde66fde | 10997 | SPARC_BUILTIN_PDISTN, si_ftype_v8qi_v8qi); |
96d7b15f DM |
10998 | |
10999 | def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis, | |
fde66fde | 11000 | SPARC_BUILTIN_FMEAN16, v4hi_ftype_v4hi_v4hi); |
96d7b15f | 11001 | def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis, |
fde66fde | 11002 | SPARC_BUILTIN_FPADD64, di_ftype_di_di); |
96d7b15f | 11003 | def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis, |
fde66fde | 11004 | SPARC_BUILTIN_FPSUB64, di_ftype_di_di); |
96d7b15f | 11005 | |
f1c141a7 | 11006 | def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3, |
fde66fde | 11007 | SPARC_BUILTIN_FPADDS16, v4hi_ftype_v4hi_v4hi); |
f1c141a7 | 11008 | def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3, |
fde66fde | 11009 | SPARC_BUILTIN_FPADDS16S, v2hi_ftype_v2hi_v2hi); |
f1c141a7 | 11010 | def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3, |
fde66fde | 11011 | SPARC_BUILTIN_FPSUBS16, v4hi_ftype_v4hi_v4hi); |
f1c141a7 | 11012 | def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3, |
fde66fde | 11013 | SPARC_BUILTIN_FPSUBS16S, v2hi_ftype_v2hi_v2hi); |
f1c141a7 | 11014 | def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3, |
fde66fde | 11015 | SPARC_BUILTIN_FPADDS32, v2si_ftype_v2si_v2si); |
e00560c2 | 11016 | def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3, |
fde66fde | 11017 | SPARC_BUILTIN_FPADDS32S, v1si_ftype_v1si_v1si); |
f1c141a7 | 11018 | def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3, |
fde66fde | 11019 | SPARC_BUILTIN_FPSUBS32, v2si_ftype_v2si_v2si); |
e00560c2 | 11020 | def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3, |
fde66fde | 11021 | SPARC_BUILTIN_FPSUBS32S, v1si_ftype_v1si_v1si); |
96d7b15f DM |
11022 | |
11023 | if (TARGET_ARCH64) | |
11024 | { | |
11025 | def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis, | |
fde66fde | 11026 | SPARC_BUILTIN_FUCMPLE8, di_ftype_v8qi_v8qi); |
96d7b15f | 11027 | def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis, |
fde66fde | 11028 | SPARC_BUILTIN_FUCMPNE8, di_ftype_v8qi_v8qi); |
96d7b15f | 11029 | def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis, |
fde66fde | 11030 | SPARC_BUILTIN_FUCMPGT8, di_ftype_v8qi_v8qi); |
96d7b15f | 11031 | def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis, |
fde66fde | 11032 | SPARC_BUILTIN_FUCMPEQ8, di_ftype_v8qi_v8qi); |
96d7b15f DM |
11033 | } |
11034 | else | |
11035 | { | |
11036 | def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis, | |
fde66fde | 11037 | SPARC_BUILTIN_FUCMPLE8, si_ftype_v8qi_v8qi); |
96d7b15f | 11038 | def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis, |
fde66fde | 11039 | SPARC_BUILTIN_FUCMPNE8, si_ftype_v8qi_v8qi); |
96d7b15f | 11040 | def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis, |
fde66fde | 11041 | SPARC_BUILTIN_FUCMPGT8, si_ftype_v8qi_v8qi); |
96d7b15f | 11042 | def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis, |
fde66fde | 11043 | SPARC_BUILTIN_FUCMPEQ8, si_ftype_v8qi_v8qi); |
96d7b15f | 11044 | } |
facb3fd7 DM |
11045 | |
11046 | def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis, | |
fde66fde | 11047 | SPARC_BUILTIN_FHADDS, sf_ftype_sf_sf); |
facb3fd7 | 11048 | def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis, |
fde66fde | 11049 | SPARC_BUILTIN_FHADDD, df_ftype_df_df); |
facb3fd7 | 11050 | def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis, |
fde66fde | 11051 | SPARC_BUILTIN_FHSUBS, sf_ftype_sf_sf); |
facb3fd7 | 11052 | def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis, |
fde66fde | 11053 | SPARC_BUILTIN_FHSUBD, df_ftype_df_df); |
facb3fd7 | 11054 | def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis, |
fde66fde | 11055 | SPARC_BUILTIN_FNHADDS, sf_ftype_sf_sf); |
facb3fd7 | 11056 | def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis, |
fde66fde | 11057 | SPARC_BUILTIN_FNHADDD, df_ftype_df_df); |
facb3fd7 DM |
11058 | |
11059 | def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis, | |
fde66fde | 11060 | SPARC_BUILTIN_UMULXHI, di_ftype_di_di); |
facb3fd7 | 11061 | def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis, |
fde66fde | 11062 | SPARC_BUILTIN_XMULX, di_ftype_di_di); |
facb3fd7 | 11063 | def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis, |
fde66fde | 11064 | SPARC_BUILTIN_XMULXHI, di_ftype_di_di); |
96d7b15f | 11065 | } |
690f24b7 JM |
11066 | |
11067 | if (TARGET_VIS4) | |
11068 | { | |
11069 | def_builtin_const ("__builtin_vis_fpadd8", CODE_FOR_addv8qi3, | |
11070 | SPARC_BUILTIN_FPADD8, v8qi_ftype_v8qi_v8qi); | |
11071 | def_builtin_const ("__builtin_vis_fpadds8", CODE_FOR_ssaddv8qi3, | |
11072 | SPARC_BUILTIN_FPADDS8, v8qi_ftype_v8qi_v8qi); | |
11073 | def_builtin_const ("__builtin_vis_fpaddus8", CODE_FOR_usaddv8qi3, | |
11074 | SPARC_BUILTIN_FPADDUS8, v8qi_ftype_v8qi_v8qi); | |
11075 | def_builtin_const ("__builtin_vis_fpaddus16", CODE_FOR_usaddv4hi3, | |
11076 | SPARC_BUILTIN_FPADDUS16, v4hi_ftype_v4hi_v4hi); | |
11077 | ||
11078 | ||
11079 | if (TARGET_ARCH64) | |
11080 | { | |
11081 | def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8di_vis, | |
11082 | SPARC_BUILTIN_FPCMPLE8, di_ftype_v8qi_v8qi); | |
11083 | def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8di_vis, | |
11084 | SPARC_BUILTIN_FPCMPGT8, di_ftype_v8qi_v8qi); | |
11085 | def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16di_vis, | |
11086 | SPARC_BUILTIN_FPCMPULE16, di_ftype_v4hi_v4hi); | |
11087 | def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16di_vis, | |
11088 | SPARC_BUILTIN_FPCMPUGT16, di_ftype_v4hi_v4hi); | |
11089 | def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32di_vis, | |
11090 | SPARC_BUILTIN_FPCMPULE32, di_ftype_v2si_v2si); | |
11091 | def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32di_vis, | |
11092 | SPARC_BUILTIN_FPCMPUGT32, di_ftype_v2si_v2si); | |
11093 | } | |
11094 | else | |
11095 | { | |
11096 | def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8si_vis, | |
11097 | SPARC_BUILTIN_FPCMPLE8, si_ftype_v8qi_v8qi); | |
11098 | def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8si_vis, | |
11099 | SPARC_BUILTIN_FPCMPGT8, si_ftype_v8qi_v8qi); | |
11100 | def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16si_vis, | |
11101 | SPARC_BUILTIN_FPCMPULE16, si_ftype_v4hi_v4hi); | |
11102 | def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16si_vis, | |
11103 | SPARC_BUILTIN_FPCMPUGT16, si_ftype_v4hi_v4hi); | |
11104 | def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32si_vis, | |
11105 | SPARC_BUILTIN_FPCMPULE32, di_ftype_v2si_v2si); | |
11106 | def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32si_vis, | |
11107 | SPARC_BUILTIN_FPCMPUGT32, di_ftype_v2si_v2si); | |
11108 | } | |
11109 | ||
11110 | def_builtin_const ("__builtin_vis_fpmax8", CODE_FOR_maxv8qi3, | |
11111 | SPARC_BUILTIN_FPMAX8, v8qi_ftype_v8qi_v8qi); | |
11112 | def_builtin_const ("__builtin_vis_fpmax16", CODE_FOR_maxv4hi3, | |
11113 | SPARC_BUILTIN_FPMAX16, v4hi_ftype_v4hi_v4hi); | |
11114 | def_builtin_const ("__builtin_vis_fpmax32", CODE_FOR_maxv2si3, | |
11115 | SPARC_BUILTIN_FPMAX32, v2si_ftype_v2si_v2si); | |
11116 | def_builtin_const ("__builtin_vis_fpmaxu8", CODE_FOR_maxuv8qi3, | |
11117 | SPARC_BUILTIN_FPMAXU8, v8qi_ftype_v8qi_v8qi); | |
11118 | def_builtin_const ("__builtin_vis_fpmaxu16", CODE_FOR_maxuv4hi3, | |
11119 | SPARC_BUILTIN_FPMAXU16, v4hi_ftype_v4hi_v4hi); | |
11120 | def_builtin_const ("__builtin_vis_fpmaxu32", CODE_FOR_maxuv2si3, | |
11121 | SPARC_BUILTIN_FPMAXU32, v2si_ftype_v2si_v2si); | |
11122 | def_builtin_const ("__builtin_vis_fpmin8", CODE_FOR_minv8qi3, | |
11123 | SPARC_BUILTIN_FPMIN8, v8qi_ftype_v8qi_v8qi); | |
11124 | def_builtin_const ("__builtin_vis_fpmin16", CODE_FOR_minv4hi3, | |
11125 | SPARC_BUILTIN_FPMIN16, v4hi_ftype_v4hi_v4hi); | |
11126 | def_builtin_const ("__builtin_vis_fpmin32", CODE_FOR_minv2si3, | |
11127 | SPARC_BUILTIN_FPMIN32, v2si_ftype_v2si_v2si); | |
11128 | def_builtin_const ("__builtin_vis_fpminu8", CODE_FOR_minuv8qi3, | |
11129 | SPARC_BUILTIN_FPMINU8, v8qi_ftype_v8qi_v8qi); | |
11130 | def_builtin_const ("__builtin_vis_fpminu16", CODE_FOR_minuv4hi3, | |
11131 | SPARC_BUILTIN_FPMINU16, v4hi_ftype_v4hi_v4hi); | |
11132 | def_builtin_const ("__builtin_vis_fpminu32", CODE_FOR_minuv2si3, | |
11133 | SPARC_BUILTIN_FPMINU32, v2si_ftype_v2si_v2si); | |
11134 | def_builtin_const ("__builtin_vis_fpsub8", CODE_FOR_subv8qi3, | |
11135 | SPARC_BUILTIN_FPSUB8, v8qi_ftype_v8qi_v8qi); | |
11136 | def_builtin_const ("__builtin_vis_fpsubs8", CODE_FOR_sssubv8qi3, | |
11137 | SPARC_BUILTIN_FPSUBS8, v8qi_ftype_v8qi_v8qi); | |
11138 | def_builtin_const ("__builtin_vis_fpsubus8", CODE_FOR_ussubv8qi3, | |
11139 | SPARC_BUILTIN_FPSUBUS8, v8qi_ftype_v8qi_v8qi); | |
11140 | def_builtin_const ("__builtin_vis_fpsubus16", CODE_FOR_ussubv4hi3, | |
11141 | SPARC_BUILTIN_FPSUBUS16, v4hi_ftype_v4hi_v4hi); | |
11142 | } | |
bcc3c3f1 JM |
11143 | |
11144 | if (TARGET_VIS4B) | |
11145 | { | |
11146 | def_builtin_const ("__builtin_vis_dictunpack8", CODE_FOR_dictunpack8, | |
11147 | SPARC_BUILTIN_DICTUNPACK8, v8qi_ftype_df_si); | |
11148 | def_builtin_const ("__builtin_vis_dictunpack16", CODE_FOR_dictunpack16, | |
11149 | SPARC_BUILTIN_DICTUNPACK16, v4hi_ftype_df_si); | |
11150 | def_builtin_const ("__builtin_vis_dictunpack32", CODE_FOR_dictunpack32, | |
11151 | SPARC_BUILTIN_DICTUNPACK32, v2si_ftype_df_si); | |
11152 | ||
11153 | if (TARGET_ARCH64) | |
11154 | { | |
11155 | tree di_ftype_v8qi_v8qi_si = build_function_type_list (intDI_type_node, | |
11156 | v8qi, v8qi, | |
11157 | intSI_type_node, 0); | |
11158 | tree di_ftype_v4hi_v4hi_si = build_function_type_list (intDI_type_node, | |
11159 | v4hi, v4hi, | |
11160 | intSI_type_node, 0); | |
11161 | tree di_ftype_v2si_v2si_si = build_function_type_list (intDI_type_node, | |
11162 | v2si, v2si, | |
11163 | intSI_type_node, 0); | |
11164 | ||
11165 | def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8dishl, | |
11166 | SPARC_BUILTIN_FPCMPLE8SHL, di_ftype_v8qi_v8qi_si); | |
11167 | def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8dishl, | |
11168 | SPARC_BUILTIN_FPCMPGT8SHL, di_ftype_v8qi_v8qi_si); | |
11169 | def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8dishl, | |
11170 | SPARC_BUILTIN_FPCMPEQ8SHL, di_ftype_v8qi_v8qi_si); | |
11171 | def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8dishl, | |
11172 | SPARC_BUILTIN_FPCMPNE8SHL, di_ftype_v8qi_v8qi_si); | |
11173 | ||
11174 | def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16dishl, | |
11175 | SPARC_BUILTIN_FPCMPLE16SHL, di_ftype_v4hi_v4hi_si); | |
11176 | def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16dishl, | |
11177 | SPARC_BUILTIN_FPCMPGT16SHL, di_ftype_v4hi_v4hi_si); | |
11178 | def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16dishl, | |
11179 | SPARC_BUILTIN_FPCMPEQ16SHL, di_ftype_v4hi_v4hi_si); | |
11180 | def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16dishl, | |
11181 | SPARC_BUILTIN_FPCMPNE16SHL, di_ftype_v4hi_v4hi_si); | |
11182 | ||
11183 | def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32dishl, | |
11184 | SPARC_BUILTIN_FPCMPLE32SHL, di_ftype_v2si_v2si_si); | |
11185 | def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32dishl, | |
11186 | SPARC_BUILTIN_FPCMPGT32SHL, di_ftype_v2si_v2si_si); | |
11187 | def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32dishl, | |
11188 | SPARC_BUILTIN_FPCMPEQ32SHL, di_ftype_v2si_v2si_si); | |
11189 | def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32dishl, | |
11190 | SPARC_BUILTIN_FPCMPNE32SHL, di_ftype_v2si_v2si_si); | |
11191 | ||
11192 | ||
11193 | def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8dishl, | |
11194 | SPARC_BUILTIN_FPCMPULE8SHL, di_ftype_v8qi_v8qi_si); | |
11195 | def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8dishl, | |
11196 | SPARC_BUILTIN_FPCMPUGT8SHL, di_ftype_v8qi_v8qi_si); | |
11197 | ||
11198 | def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16dishl, | |
11199 | SPARC_BUILTIN_FPCMPULE16SHL, di_ftype_v4hi_v4hi_si); | |
11200 | def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16dishl, | |
11201 | SPARC_BUILTIN_FPCMPUGT16SHL, di_ftype_v4hi_v4hi_si); | |
11202 | ||
11203 | def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32dishl, | |
11204 | SPARC_BUILTIN_FPCMPULE32SHL, di_ftype_v2si_v2si_si); | |
11205 | def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32dishl, | |
11206 | SPARC_BUILTIN_FPCMPUGT32SHL, di_ftype_v2si_v2si_si); | |
11207 | ||
11208 | def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8dishl, | |
11209 | SPARC_BUILTIN_FPCMPDE8SHL, di_ftype_v8qi_v8qi_si); | |
11210 | def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16dishl, | |
11211 | SPARC_BUILTIN_FPCMPDE16SHL, di_ftype_v4hi_v4hi_si); | |
11212 | def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32dishl, | |
11213 | SPARC_BUILTIN_FPCMPDE32SHL, di_ftype_v2si_v2si_si); | |
11214 | ||
11215 | def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8dishl, | |
11216 | SPARC_BUILTIN_FPCMPUR8SHL, di_ftype_v8qi_v8qi_si); | |
11217 | def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16dishl, | |
11218 | SPARC_BUILTIN_FPCMPUR16SHL, di_ftype_v4hi_v4hi_si); | |
11219 | def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32dishl, | |
11220 | SPARC_BUILTIN_FPCMPUR32SHL, di_ftype_v2si_v2si_si); | |
11221 | ||
11222 | } | |
11223 | else | |
11224 | { | |
11225 | tree si_ftype_v8qi_v8qi_si = build_function_type_list (intSI_type_node, | |
11226 | v8qi, v8qi, | |
11227 | intSI_type_node, 0); | |
11228 | tree si_ftype_v4hi_v4hi_si = build_function_type_list (intSI_type_node, | |
11229 | v4hi, v4hi, | |
11230 | intSI_type_node, 0); | |
11231 | tree si_ftype_v2si_v2si_si = build_function_type_list (intSI_type_node, | |
11232 | v2si, v2si, | |
11233 | intSI_type_node, 0); | |
11234 | ||
11235 | def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8sishl, | |
11236 | SPARC_BUILTIN_FPCMPLE8SHL, si_ftype_v8qi_v8qi_si); | |
11237 | def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8sishl, | |
11238 | SPARC_BUILTIN_FPCMPGT8SHL, si_ftype_v8qi_v8qi_si); | |
11239 | def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8sishl, | |
11240 | SPARC_BUILTIN_FPCMPEQ8SHL, si_ftype_v8qi_v8qi_si); | |
11241 | def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8sishl, | |
11242 | SPARC_BUILTIN_FPCMPNE8SHL, si_ftype_v8qi_v8qi_si); | |
11243 | ||
11244 | def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16sishl, | |
11245 | SPARC_BUILTIN_FPCMPLE16SHL, si_ftype_v4hi_v4hi_si); | |
11246 | def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16sishl, | |
11247 | SPARC_BUILTIN_FPCMPGT16SHL, si_ftype_v4hi_v4hi_si); | |
11248 | def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16sishl, | |
11249 | SPARC_BUILTIN_FPCMPEQ16SHL, si_ftype_v4hi_v4hi_si); | |
11250 | def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16sishl, | |
11251 | SPARC_BUILTIN_FPCMPNE16SHL, si_ftype_v4hi_v4hi_si); | |
11252 | ||
11253 | def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32sishl, | |
11254 | SPARC_BUILTIN_FPCMPLE32SHL, si_ftype_v2si_v2si_si); | |
11255 | def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32sishl, | |
11256 | SPARC_BUILTIN_FPCMPGT32SHL, si_ftype_v2si_v2si_si); | |
11257 | def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32sishl, | |
11258 | SPARC_BUILTIN_FPCMPEQ32SHL, si_ftype_v2si_v2si_si); | |
11259 | def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32sishl, | |
11260 | SPARC_BUILTIN_FPCMPNE32SHL, si_ftype_v2si_v2si_si); | |
11261 | ||
11262 | ||
11263 | def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8sishl, | |
11264 | SPARC_BUILTIN_FPCMPULE8SHL, si_ftype_v8qi_v8qi_si); | |
11265 | def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8sishl, | |
11266 | SPARC_BUILTIN_FPCMPUGT8SHL, si_ftype_v8qi_v8qi_si); | |
11267 | ||
11268 | def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16sishl, | |
11269 | SPARC_BUILTIN_FPCMPULE16SHL, si_ftype_v4hi_v4hi_si); | |
11270 | def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16sishl, | |
11271 | SPARC_BUILTIN_FPCMPUGT16SHL, si_ftype_v4hi_v4hi_si); | |
11272 | ||
11273 | def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32sishl, | |
11274 | SPARC_BUILTIN_FPCMPULE32SHL, si_ftype_v2si_v2si_si); | |
11275 | def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32sishl, | |
11276 | SPARC_BUILTIN_FPCMPUGT32SHL, si_ftype_v2si_v2si_si); | |
11277 | ||
11278 | def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8sishl, | |
11279 | SPARC_BUILTIN_FPCMPDE8SHL, si_ftype_v8qi_v8qi_si); | |
11280 | def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16sishl, | |
11281 | SPARC_BUILTIN_FPCMPDE16SHL, si_ftype_v4hi_v4hi_si); | |
11282 | def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32sishl, | |
11283 | SPARC_BUILTIN_FPCMPDE32SHL, si_ftype_v2si_v2si_si); | |
11284 | ||
11285 | def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8sishl, | |
11286 | SPARC_BUILTIN_FPCMPUR8SHL, si_ftype_v8qi_v8qi_si); | |
11287 | def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16sishl, | |
11288 | SPARC_BUILTIN_FPCMPUR16SHL, si_ftype_v4hi_v4hi_si); | |
11289 | def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32sishl, | |
11290 | SPARC_BUILTIN_FPCMPUR32SHL, si_ftype_v2si_v2si_si); | |
11291 | } | |
11292 | } | |
16f59241 JM |
11293 | } |
11294 | ||
fde66fde EB |
11295 | /* Implement TARGET_BUILTIN_DECL hook. */ |
11296 | ||
11297 | static tree | |
11298 | sparc_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) | |
11299 | { | |
11300 | if (code >= SPARC_BUILTIN_MAX) | |
11301 | return error_mark_node; | |
11302 | ||
11303 | return sparc_builtins[code]; | |
11304 | } | |
11305 | ||
11306 | /* Implemented TARGET_EXPAND_BUILTIN hook. */ | |
16f59241 JM |
11307 | |
11308 | static rtx | |
724d7c55 EB |
11309 | sparc_expand_builtin (tree exp, rtx target, |
11310 | rtx subtarget ATTRIBUTE_UNUSED, | |
ef4bddc2 | 11311 | machine_mode tmode ATTRIBUTE_UNUSED, |
724d7c55 | 11312 | int ignore ATTRIBUTE_UNUSED) |
16f59241 | 11313 | { |
5039610b | 11314 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
fde66fde EB |
11315 | enum sparc_builtins code = (enum sparc_builtins) DECL_FUNCTION_CODE (fndecl); |
11316 | enum insn_code icode = sparc_builtins_icode[code]; | |
11317 | bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; | |
11318 | call_expr_arg_iterator iter; | |
16f59241 | 11319 | int arg_count = 0; |
fde66fde EB |
11320 | rtx pat, op[4]; |
11321 | tree arg; | |
16f59241 | 11322 | |
10b859c0 DM |
11323 | if (nonvoid) |
11324 | { | |
ef4bddc2 | 11325 | machine_mode tmode = insn_data[icode].operand[0].mode; |
10b859c0 DM |
11326 | if (!target |
11327 | || GET_MODE (target) != tmode | |
11328 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
11329 | op[0] = gen_reg_rtx (tmode); | |
11330 | else | |
11331 | op[0] = target; | |
11332 | } | |
fde66fde | 11333 | |
5039610b | 11334 | FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) |
16f59241 | 11335 | { |
10b859c0 | 11336 | const struct insn_operand_data *insn_op; |
c4728c6b | 11337 | int idx; |
10b859c0 DM |
11338 | |
11339 | if (arg == error_mark_node) | |
11340 | return NULL_RTX; | |
11341 | ||
16f59241 | 11342 | arg_count++; |
c4728c6b DM |
11343 | idx = arg_count - !nonvoid; |
11344 | insn_op = &insn_data[icode].operand[idx]; | |
84217346 | 11345 | op[arg_count] = expand_normal (arg); |
16f59241 | 11346 | |
bcc3c3f1 JM |
11347 | /* Some of the builtins require constant arguments. We check |
11348 | for this here. */ | |
11349 | if ((code >= SPARC_BUILTIN_FIRST_FPCMPSHL | |
11350 | && code <= SPARC_BUILTIN_LAST_FPCMPSHL | |
11351 | && arg_count == 3) | |
11352 | || (code >= SPARC_BUILTIN_FIRST_DICTUNPACK | |
11353 | && code <= SPARC_BUILTIN_LAST_DICTUNPACK | |
11354 | && arg_count == 2)) | |
11355 | { | |
11356 | if (!check_constant_argument (icode, idx, op[arg_count])) | |
11357 | return const0_rtx; | |
11358 | } | |
11359 | ||
fde66fde EB |
11360 | if (code == SPARC_BUILTIN_LDFSR || code == SPARC_BUILTIN_STFSR) |
11361 | { | |
11362 | if (!address_operand (op[arg_count], SImode)) | |
11363 | { | |
11364 | op[arg_count] = convert_memory_address (Pmode, op[arg_count]); | |
11365 | op[arg_count] = copy_addr_to_reg (op[arg_count]); | |
11366 | } | |
11367 | op[arg_count] = gen_rtx_MEM (SImode, op[arg_count]); | |
11368 | } | |
11369 | ||
11370 | else if (insn_op->mode == V1DImode | |
11371 | && GET_MODE (op[arg_count]) == DImode) | |
e00560c2 | 11372 | op[arg_count] = gen_lowpart (V1DImode, op[arg_count]); |
fde66fde | 11373 | |
e00560c2 | 11374 | else if (insn_op->mode == V1SImode |
fde66fde | 11375 | && GET_MODE (op[arg_count]) == SImode) |
e00560c2 DM |
11376 | op[arg_count] = gen_lowpart (V1SImode, op[arg_count]); |
11377 | ||
c4728c6b DM |
11378 | if (! (*insn_data[icode].operand[idx].predicate) (op[arg_count], |
11379 | insn_op->mode)) | |
10b859c0 | 11380 | op[arg_count] = copy_to_mode_reg (insn_op->mode, op[arg_count]); |
16f59241 JM |
11381 | } |
11382 | ||
11383 | switch (arg_count) | |
11384 | { | |
10b859c0 DM |
11385 | case 0: |
11386 | pat = GEN_FCN (icode) (op[0]); | |
11387 | break; | |
16f59241 | 11388 | case 1: |
10b859c0 DM |
11389 | if (nonvoid) |
11390 | pat = GEN_FCN (icode) (op[0], op[1]); | |
11391 | else | |
11392 | pat = GEN_FCN (icode) (op[1]); | |
16f59241 JM |
11393 | break; |
11394 | case 2: | |
11395 | pat = GEN_FCN (icode) (op[0], op[1], op[2]); | |
11396 | break; | |
11397 | case 3: | |
11398 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); | |
11399 | break; | |
11400 | default: | |
11401 | gcc_unreachable (); | |
11402 | } | |
11403 | ||
11404 | if (!pat) | |
11405 | return NULL_RTX; | |
11406 | ||
11407 | emit_insn (pat); | |
11408 | ||
fde66fde | 11409 | return (nonvoid ? op[0] : const0_rtx); |
16f59241 | 11410 | } |
8b0096b4 | 11411 | |
fde66fde EB |
11412 | /* Return the upper 16 bits of the 8x16 multiplication. */ |
11413 | ||
8b0096b4 JM |
11414 | static int |
11415 | sparc_vis_mul8x16 (int e8, int e16) | |
11416 | { | |
11417 | return (e8 * e16 + 128) / 256; | |
11418 | } | |
11419 | ||
d2a12ae7 RG |
11420 | /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put |
11421 | the result into the array N_ELTS, whose elements are of INNER_TYPE. */ | |
8b0096b4 | 11422 | |
d2a12ae7 | 11423 | static void |
fde66fde EB |
11424 | sparc_handle_vis_mul8x16 (tree *n_elts, enum sparc_builtins fncode, |
11425 | tree inner_type, tree cst0, tree cst1) | |
8b0096b4 | 11426 | { |
d2a12ae7 | 11427 | unsigned i, num = VECTOR_CST_NELTS (cst0); |
8b0096b4 JM |
11428 | int scale; |
11429 | ||
11430 | switch (fncode) | |
11431 | { | |
fde66fde | 11432 | case SPARC_BUILTIN_FMUL8X16: |
d2a12ae7 | 11433 | for (i = 0; i < num; ++i) |
8b0096b4 JM |
11434 | { |
11435 | int val | |
d2a12ae7 RG |
11436 | = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0, i)), |
11437 | TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1, i))); | |
11438 | n_elts[i] = build_int_cst (inner_type, val); | |
8b0096b4 JM |
11439 | } |
11440 | break; | |
11441 | ||
fde66fde | 11442 | case SPARC_BUILTIN_FMUL8X16AU: |
d2a12ae7 | 11443 | scale = TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1, 0)); |
8b0096b4 | 11444 | |
d2a12ae7 | 11445 | for (i = 0; i < num; ++i) |
8b0096b4 JM |
11446 | { |
11447 | int val | |
d2a12ae7 | 11448 | = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0, i)), |
8b0096b4 | 11449 | scale); |
d2a12ae7 | 11450 | n_elts[i] = build_int_cst (inner_type, val); |
8b0096b4 JM |
11451 | } |
11452 | break; | |
11453 | ||
fde66fde | 11454 | case SPARC_BUILTIN_FMUL8X16AL: |
f26c81d6 | 11455 | scale = TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1, 1)); |
8b0096b4 | 11456 | |
d2a12ae7 | 11457 | for (i = 0; i < num; ++i) |
8b0096b4 JM |
11458 | { |
11459 | int val | |
d2a12ae7 | 11460 | = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0, i)), |
8b0096b4 | 11461 | scale); |
d2a12ae7 | 11462 | n_elts[i] = build_int_cst (inner_type, val); |
8b0096b4 JM |
11463 | } |
11464 | break; | |
11465 | ||
11466 | default: | |
11467 | gcc_unreachable (); | |
11468 | } | |
8b0096b4 | 11469 | } |
d2a12ae7 | 11470 | |
fde66fde EB |
11471 | /* Implement TARGET_FOLD_BUILTIN hook. |
11472 | ||
607fb860 | 11473 | Fold builtin functions for SPARC intrinsics. If IGNORE is true the |
8b0096b4 JM |
11474 | result of the function call is ignored. NULL_TREE is returned if the |
11475 | function could not be folded. */ | |
11476 | ||
11477 | static tree | |
f311c3b4 NF |
11478 | sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, |
11479 | tree *args, bool ignore) | |
8b0096b4 | 11480 | { |
fde66fde | 11481 | enum sparc_builtins code = (enum sparc_builtins) DECL_FUNCTION_CODE (fndecl); |
8b0096b4 | 11482 | tree rtype = TREE_TYPE (TREE_TYPE (fndecl)); |
fde66fde | 11483 | tree arg0, arg1, arg2; |
8b0096b4 | 11484 | |
96d7b15f | 11485 | if (ignore) |
fde66fde EB |
11486 | switch (code) |
11487 | { | |
11488 | case SPARC_BUILTIN_LDFSR: | |
11489 | case SPARC_BUILTIN_STFSR: | |
11490 | case SPARC_BUILTIN_ALIGNADDR: | |
11491 | case SPARC_BUILTIN_WRGSR: | |
11492 | case SPARC_BUILTIN_BMASK: | |
11493 | case SPARC_BUILTIN_CMASK8: | |
11494 | case SPARC_BUILTIN_CMASK16: | |
11495 | case SPARC_BUILTIN_CMASK32: | |
11496 | break; | |
11497 | ||
11498 | default: | |
437bcafa | 11499 | return build_zero_cst (rtype); |
fde66fde | 11500 | } |
8b0096b4 | 11501 | |
fde66fde | 11502 | switch (code) |
8b0096b4 | 11503 | { |
fde66fde | 11504 | case SPARC_BUILTIN_FEXPAND: |
f311c3b4 | 11505 | arg0 = args[0]; |
8b0096b4 JM |
11506 | STRIP_NOPS (arg0); |
11507 | ||
11508 | if (TREE_CODE (arg0) == VECTOR_CST) | |
11509 | { | |
11510 | tree inner_type = TREE_TYPE (rtype); | |
d2a12ae7 RG |
11511 | tree *n_elts; |
11512 | unsigned i; | |
11513 | ||
11514 | n_elts = XALLOCAVEC (tree, VECTOR_CST_NELTS (arg0)); | |
11515 | for (i = 0; i < VECTOR_CST_NELTS (arg0); ++i) | |
11516 | n_elts[i] = build_int_cst (inner_type, | |
11517 | TREE_INT_CST_LOW | |
11518 | (VECTOR_CST_ELT (arg0, i)) << 4); | |
11519 | return build_vector (rtype, n_elts); | |
8b0096b4 JM |
11520 | } |
11521 | break; | |
11522 | ||
fde66fde EB |
11523 | case SPARC_BUILTIN_FMUL8X16: |
11524 | case SPARC_BUILTIN_FMUL8X16AU: | |
11525 | case SPARC_BUILTIN_FMUL8X16AL: | |
f311c3b4 NF |
11526 | arg0 = args[0]; |
11527 | arg1 = args[1]; | |
8b0096b4 JM |
11528 | STRIP_NOPS (arg0); |
11529 | STRIP_NOPS (arg1); | |
11530 | ||
11531 | if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST) | |
11532 | { | |
11533 | tree inner_type = TREE_TYPE (rtype); | |
d2a12ae7 | 11534 | tree *n_elts = XALLOCAVEC (tree, VECTOR_CST_NELTS (arg0)); |
fde66fde | 11535 | sparc_handle_vis_mul8x16 (n_elts, code, inner_type, arg0, arg1); |
8b0096b4 JM |
11536 | return build_vector (rtype, n_elts); |
11537 | } | |
11538 | break; | |
11539 | ||
fde66fde | 11540 | case SPARC_BUILTIN_FPMERGE: |
f311c3b4 NF |
11541 | arg0 = args[0]; |
11542 | arg1 = args[1]; | |
8b0096b4 JM |
11543 | STRIP_NOPS (arg0); |
11544 | STRIP_NOPS (arg1); | |
11545 | ||
11546 | if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST) | |
11547 | { | |
d2a12ae7 RG |
11548 | tree *n_elts = XALLOCAVEC (tree, 2 * VECTOR_CST_NELTS (arg0)); |
11549 | unsigned i; | |
11550 | for (i = 0; i < VECTOR_CST_NELTS (arg0); ++i) | |
8b0096b4 | 11551 | { |
d2a12ae7 RG |
11552 | n_elts[2*i] = VECTOR_CST_ELT (arg0, i); |
11553 | n_elts[2*i+1] = VECTOR_CST_ELT (arg1, i); | |
8b0096b4 JM |
11554 | } |
11555 | ||
d2a12ae7 | 11556 | return build_vector (rtype, n_elts); |
8b0096b4 JM |
11557 | } |
11558 | break; | |
11559 | ||
fde66fde EB |
11560 | case SPARC_BUILTIN_PDIST: |
11561 | case SPARC_BUILTIN_PDISTN: | |
f311c3b4 NF |
11562 | arg0 = args[0]; |
11563 | arg1 = args[1]; | |
8b0096b4 JM |
11564 | STRIP_NOPS (arg0); |
11565 | STRIP_NOPS (arg1); | |
fde66fde EB |
11566 | if (code == SPARC_BUILTIN_PDIST) |
11567 | { | |
11568 | arg2 = args[2]; | |
11569 | STRIP_NOPS (arg2); | |
11570 | } | |
11571 | else | |
11572 | arg2 = integer_zero_node; | |
8b0096b4 JM |
11573 | |
11574 | if (TREE_CODE (arg0) == VECTOR_CST | |
11575 | && TREE_CODE (arg1) == VECTOR_CST | |
11576 | && TREE_CODE (arg2) == INTEGER_CST) | |
11577 | { | |
9be0ac8c | 11578 | bool overflow = false; |
34dbb287 RS |
11579 | widest_int result = wi::to_widest (arg2); |
11580 | widest_int tmp; | |
d2a12ae7 | 11581 | unsigned i; |
8b0096b4 | 11582 | |
d2a12ae7 | 11583 | for (i = 0; i < VECTOR_CST_NELTS (arg0); ++i) |
8b0096b4 | 11584 | { |
807e902e KZ |
11585 | tree e0 = VECTOR_CST_ELT (arg0, i); |
11586 | tree e1 = VECTOR_CST_ELT (arg1, i); | |
9be0ac8c LC |
11587 | |
11588 | bool neg1_ovf, neg2_ovf, add1_ovf, add2_ovf; | |
11589 | ||
34dbb287 RS |
11590 | tmp = wi::neg (wi::to_widest (e1), &neg1_ovf); |
11591 | tmp = wi::add (wi::to_widest (e0), tmp, SIGNED, &add1_ovf); | |
807e902e KZ |
11592 | if (wi::neg_p (tmp)) |
11593 | tmp = wi::neg (tmp, &neg2_ovf); | |
a9a130f5 EB |
11594 | else |
11595 | neg2_ovf = false; | |
807e902e | 11596 | result = wi::add (result, tmp, SIGNED, &add2_ovf); |
9be0ac8c | 11597 | overflow |= neg1_ovf | neg2_ovf | add1_ovf | add2_ovf; |
8b0096b4 JM |
11598 | } |
11599 | ||
9be0ac8c | 11600 | gcc_assert (!overflow); |
8b0096b4 | 11601 | |
807e902e | 11602 | return wide_int_to_tree (rtype, result); |
8b0096b4 JM |
11603 | } |
11604 | ||
11605 | default: | |
11606 | break; | |
11607 | } | |
724d7c55 | 11608 | |
8b0096b4 JM |
11609 | return NULL_TREE; |
11610 | } | |
16f59241 | 11611 | \f |
214c6394 DM |
11612 | /* ??? This duplicates information provided to the compiler by the |
11613 | ??? scheduler description. Some day, teach genautomata to output | |
11614 | ??? the latencies and then CSE will just use that. */ | |
11615 | ||
3c50106f | 11616 | static bool |
e548c9df AM |
11617 | sparc_rtx_costs (rtx x, machine_mode mode, int outer_code, |
11618 | int opno ATTRIBUTE_UNUSED, | |
68f932c4 | 11619 | int *total, bool speed ATTRIBUTE_UNUSED) |
2ce04b6b | 11620 | { |
e548c9df | 11621 | int code = GET_CODE (x); |
18df6de9 DM |
11622 | bool float_mode_p = FLOAT_MODE_P (mode); |
11623 | ||
2ce04b6b DM |
11624 | switch (code) |
11625 | { | |
18df6de9 | 11626 | case CONST_INT: |
eaac029f EB |
11627 | if (SMALL_INT (x)) |
11628 | *total = 0; | |
11629 | else | |
11630 | *total = 2; | |
11631 | return true; | |
11632 | ||
11633 | case CONST_WIDE_INT: | |
11634 | *total = 0; | |
11635 | if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x, 0))) | |
11636 | *total += 2; | |
11637 | if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x, 1))) | |
11638 | *total += 2; | |
11639 | return true; | |
214c6394 | 11640 | |
18df6de9 DM |
11641 | case HIGH: |
11642 | *total = 2; | |
11643 | return true; | |
214c6394 | 11644 | |
18df6de9 DM |
11645 | case CONST: |
11646 | case LABEL_REF: | |
11647 | case SYMBOL_REF: | |
11648 | *total = 4; | |
11649 | return true; | |
214c6394 | 11650 | |
18df6de9 | 11651 | case CONST_DOUBLE: |
eaac029f | 11652 | *total = 8; |
3c50106f | 11653 | return true; |
214c6394 | 11654 | |
18df6de9 DM |
11655 | case MEM: |
11656 | /* If outer-code was a sign or zero extension, a cost | |
11657 | of COSTS_N_INSNS (1) was already added in. This is | |
11658 | why we are subtracting it back out. */ | |
11659 | if (outer_code == ZERO_EXTEND) | |
214c6394 | 11660 | { |
18df6de9 | 11661 | *total = sparc_costs->int_zload - COSTS_N_INSNS (1); |
214c6394 | 11662 | } |
18df6de9 | 11663 | else if (outer_code == SIGN_EXTEND) |
3c50106f | 11664 | { |
18df6de9 | 11665 | *total = sparc_costs->int_sload - COSTS_N_INSNS (1); |
3c50106f | 11666 | } |
18df6de9 | 11667 | else if (float_mode_p) |
3c50106f | 11668 | { |
18df6de9 | 11669 | *total = sparc_costs->float_load; |
3c50106f | 11670 | } |
18df6de9 | 11671 | else |
3c50106f | 11672 | { |
18df6de9 | 11673 | *total = sparc_costs->int_load; |
3c50106f | 11674 | } |
214c6394 | 11675 | |
3c50106f | 11676 | return true; |
2ce04b6b | 11677 | |
18df6de9 DM |
11678 | case PLUS: |
11679 | case MINUS: | |
11680 | if (float_mode_p) | |
11681 | *total = sparc_costs->float_plusminus; | |
11682 | else | |
11683 | *total = COSTS_N_INSNS (1); | |
11684 | return false; | |
214c6394 | 11685 | |
e8b141b5 DM |
11686 | case FMA: |
11687 | { | |
11688 | rtx sub; | |
11689 | ||
11690 | gcc_assert (float_mode_p); | |
11691 | *total = sparc_costs->float_mul; | |
11692 | ||
11693 | sub = XEXP (x, 0); | |
11694 | if (GET_CODE (sub) == NEG) | |
11695 | sub = XEXP (sub, 0); | |
e548c9df | 11696 | *total += rtx_cost (sub, mode, FMA, 0, speed); |
e8b141b5 DM |
11697 | |
11698 | sub = XEXP (x, 2); | |
11699 | if (GET_CODE (sub) == NEG) | |
11700 | sub = XEXP (sub, 0); | |
e548c9df | 11701 | *total += rtx_cost (sub, mode, FMA, 2, speed); |
e8b141b5 DM |
11702 | return true; |
11703 | } | |
11704 | ||
18df6de9 DM |
11705 | case MULT: |
11706 | if (float_mode_p) | |
11707 | *total = sparc_costs->float_mul; | |
aa47faf0 | 11708 | else if (TARGET_ARCH32 && !TARGET_HARD_MUL) |
bf6c40e9 | 11709 | *total = COSTS_N_INSNS (25); |
18df6de9 DM |
11710 | else |
11711 | { | |
11712 | int bit_cost; | |
214c6394 | 11713 | |
18df6de9 DM |
11714 | bit_cost = 0; |
11715 | if (sparc_costs->int_mul_bit_factor) | |
11716 | { | |
11717 | int nbits; | |
214c6394 | 11718 | |
18df6de9 DM |
11719 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) |
11720 | { | |
11721 | unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1)); | |
11722 | for (nbits = 0; value != 0; value &= value - 1) | |
11723 | nbits++; | |
11724 | } | |
214c6394 | 11725 | else |
18df6de9 | 11726 | nbits = 7; |
214c6394 | 11727 | |
18df6de9 DM |
11728 | if (nbits < 3) |
11729 | nbits = 3; | |
11730 | bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor; | |
ffe384ff | 11731 | bit_cost = COSTS_N_INSNS (bit_cost); |
214c6394 | 11732 | } |
18df6de9 | 11733 | |
aa47faf0 | 11734 | if (mode == DImode || !TARGET_HARD_MUL) |
ffe384ff | 11735 | *total = sparc_costs->int_mulX + bit_cost; |
18df6de9 | 11736 | else |
ffe384ff | 11737 | *total = sparc_costs->int_mul + bit_cost; |
214c6394 | 11738 | } |
18df6de9 | 11739 | return false; |
214c6394 | 11740 | |
18df6de9 DM |
11741 | case ASHIFT: |
11742 | case ASHIFTRT: | |
11743 | case LSHIFTRT: | |
11744 | *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty; | |
11745 | return false; | |
2ce04b6b | 11746 | |
18df6de9 DM |
11747 | case DIV: |
11748 | case UDIV: | |
11749 | case MOD: | |
11750 | case UMOD: | |
11751 | if (float_mode_p) | |
214c6394 | 11752 | { |
18df6de9 DM |
11753 | if (mode == DFmode) |
11754 | *total = sparc_costs->float_div_df; | |
214c6394 | 11755 | else |
18df6de9 | 11756 | *total = sparc_costs->float_div_sf; |
214c6394 | 11757 | } |
18df6de9 | 11758 | else |
214c6394 | 11759 | { |
18df6de9 DM |
11760 | if (mode == DImode) |
11761 | *total = sparc_costs->int_divX; | |
214c6394 | 11762 | else |
18df6de9 | 11763 | *total = sparc_costs->int_div; |
214c6394 | 11764 | } |
18df6de9 | 11765 | return false; |
2ce04b6b | 11766 | |
18df6de9 DM |
11767 | case NEG: |
11768 | if (! float_mode_p) | |
3c50106f | 11769 | { |
18df6de9 DM |
11770 | *total = COSTS_N_INSNS (1); |
11771 | return false; | |
3c50106f | 11772 | } |
5efb1046 | 11773 | /* FALLTHRU */ |
2ce04b6b | 11774 | |
18df6de9 DM |
11775 | case ABS: |
11776 | case FLOAT: | |
11777 | case UNSIGNED_FLOAT: | |
11778 | case FIX: | |
11779 | case UNSIGNED_FIX: | |
11780 | case FLOAT_EXTEND: | |
11781 | case FLOAT_TRUNCATE: | |
11782 | *total = sparc_costs->float_move; | |
11783 | return false; | |
2ce04b6b | 11784 | |
18df6de9 DM |
11785 | case SQRT: |
11786 | if (mode == DFmode) | |
11787 | *total = sparc_costs->float_sqrt_df; | |
11788 | else | |
11789 | *total = sparc_costs->float_sqrt_sf; | |
11790 | return false; | |
2ce04b6b | 11791 | |
18df6de9 DM |
11792 | case COMPARE: |
11793 | if (float_mode_p) | |
11794 | *total = sparc_costs->float_cmp; | |
3c50106f | 11795 | else |
18df6de9 DM |
11796 | *total = COSTS_N_INSNS (1); |
11797 | return false; | |
11798 | ||
11799 | case IF_THEN_ELSE: | |
11800 | if (float_mode_p) | |
11801 | *total = sparc_costs->float_cmove; | |
11802 | else | |
11803 | *total = sparc_costs->int_cmove; | |
11804 | return false; | |
2ce04b6b | 11805 | |
893e18a5 JM |
11806 | case IOR: |
11807 | /* Handle the NAND vector patterns. */ | |
e548c9df | 11808 | if (sparc_vector_mode_supported_p (mode) |
893e18a5 JM |
11809 | && GET_CODE (XEXP (x, 0)) == NOT |
11810 | && GET_CODE (XEXP (x, 1)) == NOT) | |
11811 | { | |
11812 | *total = COSTS_N_INSNS (1); | |
11813 | return true; | |
11814 | } | |
11815 | else | |
11816 | return false; | |
11817 | ||
2ce04b6b | 11818 | default: |
3c50106f RH |
11819 | return false; |
11820 | } | |
2ce04b6b | 11821 | } |
fb49053f | 11822 | |
32257ddc AS |
11823 | /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */ |
11824 | ||
11825 | static inline bool | |
11826 | general_or_i64_p (reg_class_t rclass) | |
11827 | { | |
11828 | return (rclass == GENERAL_REGS || rclass == I64_REGS); | |
11829 | } | |
11830 | ||
11831 | /* Implement TARGET_REGISTER_MOVE_COST. */ | |
11832 | ||
11833 | static int | |
ef4bddc2 | 11834 | sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
32257ddc AS |
11835 | reg_class_t from, reg_class_t to) |
11836 | { | |
bb12a72a DM |
11837 | bool need_memory = false; |
11838 | ||
ff7e7ee0 EB |
11839 | /* This helps postreload CSE to eliminate redundant comparisons. */ |
11840 | if (from == NO_REGS || to == NO_REGS) | |
11841 | return 100; | |
11842 | ||
bb12a72a DM |
11843 | if (from == FPCC_REGS || to == FPCC_REGS) |
11844 | need_memory = true; | |
11845 | else if ((FP_REG_CLASS_P (from) && general_or_i64_p (to)) | |
11846 | || (general_or_i64_p (from) && FP_REG_CLASS_P (to))) | |
11847 | { | |
11848 | if (TARGET_VIS3) | |
11849 | { | |
11850 | int size = GET_MODE_SIZE (mode); | |
11851 | if (size == 8 || size == 4) | |
11852 | { | |
11853 | if (! TARGET_ARCH32 || size == 4) | |
11854 | return 4; | |
11855 | else | |
11856 | return 6; | |
11857 | } | |
11858 | } | |
11859 | need_memory = true; | |
11860 | } | |
11861 | ||
11862 | if (need_memory) | |
32257ddc AS |
11863 | { |
11864 | if (sparc_cpu == PROCESSOR_ULTRASPARC | |
11865 | || sparc_cpu == PROCESSOR_ULTRASPARC3 | |
11866 | || sparc_cpu == PROCESSOR_NIAGARA | |
3e64c239 DM |
11867 | || sparc_cpu == PROCESSOR_NIAGARA2 |
11868 | || sparc_cpu == PROCESSOR_NIAGARA3 | |
690f24b7 | 11869 | || sparc_cpu == PROCESSOR_NIAGARA4 |
bcc3c3f1 JM |
11870 | || sparc_cpu == PROCESSOR_NIAGARA7 |
11871 | || sparc_cpu == PROCESSOR_M8) | |
dc2a24ed | 11872 | return 12; |
32257ddc AS |
11873 | |
11874 | return 6; | |
11875 | } | |
11876 | ||
11877 | return 2; | |
11878 | } | |
11879 | ||
68ba34f3 AS |
11880 | /* Emit the sequence of insns SEQ while preserving the registers REG and REG2. |
11881 | This is achieved by means of a manual dynamic stack space allocation in | |
11882 | the current frame. We make the assumption that SEQ doesn't contain any | |
a6fed83f | 11883 | function calls, with the possible exception of calls to the GOT helper. */ |
951661a1 EB |
11884 | |
11885 | static void | |
1b970c28 | 11886 | emit_and_preserve (rtx seq, rtx reg, rtx reg2) |
951661a1 | 11887 | { |
68ba34f3 AS |
11888 | /* We must preserve the lowest 16 words for the register save area. */ |
11889 | HOST_WIDE_INT offset = 16*UNITS_PER_WORD; | |
11890 | /* We really need only 2 words of fresh stack space. */ | |
11891 | HOST_WIDE_INT size = SPARC_STACK_ALIGN (offset + 2*UNITS_PER_WORD); | |
951661a1 | 11892 | |
68ba34f3 | 11893 | rtx slot |
0a81f074 | 11894 | = gen_rtx_MEM (word_mode, plus_constant (Pmode, stack_pointer_rtx, |
68ba34f3 AS |
11895 | SPARC_STACK_BIAS + offset)); |
11896 | ||
b7dcf38f | 11897 | emit_insn (gen_stack_pointer_inc (GEN_INT (-size))); |
f7df4a84 | 11898 | emit_insn (gen_rtx_SET (slot, reg)); |
1b970c28 | 11899 | if (reg2) |
f7df4a84 | 11900 | emit_insn (gen_rtx_SET (adjust_address (slot, word_mode, UNITS_PER_WORD), |
1b970c28 | 11901 | reg2)); |
951661a1 | 11902 | emit_insn (seq); |
1b970c28 | 11903 | if (reg2) |
f7df4a84 | 11904 | emit_insn (gen_rtx_SET (reg2, |
1b970c28 | 11905 | adjust_address (slot, word_mode, UNITS_PER_WORD))); |
f7df4a84 | 11906 | emit_insn (gen_rtx_SET (reg, slot)); |
68ba34f3 | 11907 | emit_insn (gen_stack_pointer_inc (GEN_INT (size))); |
951661a1 EB |
11908 | } |
11909 | ||
b9bf58e5 EB |
11910 | /* Output the assembler code for a thunk function. THUNK_DECL is the |
11911 | declaration for the thunk function itself, FUNCTION is the decl for | |
11912 | the target function. DELTA is an immediate constant offset to be | |
11913 | added to THIS. If VCALL_OFFSET is nonzero, the word at address | |
11914 | (*THIS + VCALL_OFFSET) should be additionally added to THIS. */ | |
e133041b | 11915 | |
c590b625 | 11916 | static void |
fc27d102 | 11917 | sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
b9bf58e5 | 11918 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, |
fc27d102 | 11919 | tree function) |
e133041b | 11920 | { |
e1faf324 DM |
11921 | rtx this_rtx, funexp; |
11922 | rtx_insn *insn; | |
951661a1 | 11923 | unsigned int int_arg_first; |
e133041b RH |
11924 | |
11925 | reload_completed = 1; | |
fe3ad572 | 11926 | epilogue_completed = 1; |
e133041b | 11927 | |
2e040219 | 11928 | emit_note (NOTE_INSN_PROLOGUE_END); |
e133041b | 11929 | |
b11b0904 EB |
11930 | if (TARGET_FLAT) |
11931 | { | |
11932 | sparc_leaf_function_p = 1; | |
11933 | ||
11934 | int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST; | |
11935 | } | |
11936 | else if (flag_delayed_branch) | |
951661a1 EB |
11937 | { |
11938 | /* We will emit a regular sibcall below, so we need to instruct | |
11939 | output_sibcall that we are in a leaf function. */ | |
416ff32e | 11940 | sparc_leaf_function_p = crtl->uses_only_leaf_regs = 1; |
951661a1 EB |
11941 | |
11942 | /* This will cause final.c to invoke leaf_renumber_regs so we | |
11943 | must behave as if we were in a not-yet-leafified function. */ | |
11944 | int_arg_first = SPARC_INCOMING_INT_ARG_FIRST; | |
11945 | } | |
11946 | else | |
11947 | { | |
11948 | /* We will emit the sibcall manually below, so we will need to | |
11949 | manually spill non-leaf registers. */ | |
416ff32e | 11950 | sparc_leaf_function_p = crtl->uses_only_leaf_regs = 0; |
951661a1 EB |
11951 | |
11952 | /* We really are in a leaf function. */ | |
11953 | int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST; | |
11954 | } | |
11955 | ||
e133041b RH |
11956 | /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function |
11957 | returns a structure, the structure return pointer is there instead. */ | |
4900aa61 EB |
11958 | if (TARGET_ARCH64 |
11959 | && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
0a2aaacc | 11960 | this_rtx = gen_rtx_REG (Pmode, int_arg_first + 1); |
e133041b | 11961 | else |
0a2aaacc | 11962 | this_rtx = gen_rtx_REG (Pmode, int_arg_first); |
e133041b RH |
11963 | |
11964 | /* Add DELTA. When possible use a plain add, otherwise load it into | |
11965 | a register first. */ | |
b9bf58e5 | 11966 | if (delta) |
e133041b | 11967 | { |
b9bf58e5 EB |
11968 | rtx delta_rtx = GEN_INT (delta); |
11969 | ||
11970 | if (! SPARC_SIMM13_P (delta)) | |
11971 | { | |
11972 | rtx scratch = gen_rtx_REG (Pmode, 1); | |
11973 | emit_move_insn (scratch, delta_rtx); | |
11974 | delta_rtx = scratch; | |
11975 | } | |
11976 | ||
0a2aaacc KG |
11977 | /* THIS_RTX += DELTA. */ |
11978 | emit_insn (gen_add2_insn (this_rtx, delta_rtx)); | |
b9bf58e5 EB |
11979 | } |
11980 | ||
0a2aaacc | 11981 | /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */ |
b9bf58e5 EB |
11982 | if (vcall_offset) |
11983 | { | |
11984 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); | |
e133041b | 11985 | rtx scratch = gen_rtx_REG (Pmode, 1); |
ed1fe829 | 11986 | |
f5f7d171 | 11987 | gcc_assert (vcall_offset < 0); |
b9bf58e5 | 11988 | |
0a2aaacc KG |
11989 | /* SCRATCH = *THIS_RTX. */ |
11990 | emit_move_insn (scratch, gen_rtx_MEM (Pmode, this_rtx)); | |
b9bf58e5 EB |
11991 | |
11992 | /* Prepare for adding VCALL_OFFSET. The difficulty is that we | |
11993 | may not have any available scratch register at this point. */ | |
11994 | if (SPARC_SIMM13_P (vcall_offset)) | |
11995 | ; | |
11996 | /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */ | |
11997 | else if (! fixed_regs[5] | |
11998 | /* The below sequence is made up of at least 2 insns, | |
11999 | while the default method may need only one. */ | |
12000 | && vcall_offset < -8192) | |
12001 | { | |
12002 | rtx scratch2 = gen_rtx_REG (Pmode, 5); | |
12003 | emit_move_insn (scratch2, vcall_offset_rtx); | |
12004 | vcall_offset_rtx = scratch2; | |
12005 | } | |
e133041b | 12006 | else |
ed1fe829 | 12007 | { |
b9bf58e5 EB |
12008 | rtx increment = GEN_INT (-4096); |
12009 | ||
12010 | /* VCALL_OFFSET is a negative number whose typical range can be | |
12011 | estimated as -32768..0 in 32-bit mode. In almost all cases | |
12012 | it is therefore cheaper to emit multiple add insns than | |
12013 | spilling and loading the constant into a register (at least | |
12014 | 6 insns). */ | |
12015 | while (! SPARC_SIMM13_P (vcall_offset)) | |
12016 | { | |
12017 | emit_insn (gen_add2_insn (scratch, increment)); | |
12018 | vcall_offset += 4096; | |
12019 | } | |
12020 | vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */ | |
ed1fe829 EB |
12021 | } |
12022 | ||
0a2aaacc | 12023 | /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */ |
b9bf58e5 EB |
12024 | emit_move_insn (scratch, gen_rtx_MEM (Pmode, |
12025 | gen_rtx_PLUS (Pmode, | |
12026 | scratch, | |
12027 | vcall_offset_rtx))); | |
e133041b | 12028 | |
0a2aaacc KG |
12029 | /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */ |
12030 | emit_insn (gen_add2_insn (this_rtx, scratch)); | |
b9bf58e5 | 12031 | } |
e133041b RH |
12032 | |
12033 | /* Generate a tail call to the target function. */ | |
12034 | if (! TREE_USED (function)) | |
12035 | { | |
12036 | assemble_external (function); | |
12037 | TREE_USED (function) = 1; | |
12038 | } | |
12039 | funexp = XEXP (DECL_RTL (function), 0); | |
951661a1 EB |
12040 | |
12041 | if (flag_delayed_branch) | |
12042 | { | |
12043 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); | |
12044 | insn = emit_call_insn (gen_sibcall (funexp)); | |
12045 | SIBLING_CALL_P (insn) = 1; | |
12046 | } | |
12047 | else | |
12048 | { | |
12049 | /* The hoops we have to jump through in order to generate a sibcall | |
12050 | without using delay slots... */ | |
a6fed83f | 12051 | rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1); |
951661a1 EB |
12052 | |
12053 | if (flag_pic) | |
12054 | { | |
12055 | spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */ | |
12056 | start_sequence (); | |
a6fed83f | 12057 | load_got_register (); /* clobbers %o7 */ |
58e6223e | 12058 | scratch = sparc_legitimize_pic_address (funexp, scratch); |
951661a1 EB |
12059 | seq = get_insns (); |
12060 | end_sequence (); | |
a6fed83f | 12061 | emit_and_preserve (seq, spill_reg, pic_offset_table_rtx); |
951661a1 EB |
12062 | } |
12063 | else if (TARGET_ARCH32) | |
12064 | { | |
f7df4a84 | 12065 | emit_insn (gen_rtx_SET (scratch, |
951661a1 | 12066 | gen_rtx_HIGH (SImode, funexp))); |
f7df4a84 | 12067 | emit_insn (gen_rtx_SET (scratch, |
951661a1 EB |
12068 | gen_rtx_LO_SUM (SImode, scratch, funexp))); |
12069 | } | |
12070 | else /* TARGET_ARCH64 */ | |
12071 | { | |
12072 | switch (sparc_cmodel) | |
12073 | { | |
12074 | case CM_MEDLOW: | |
12075 | case CM_MEDMID: | |
12076 | /* The destination can serve as a temporary. */ | |
12077 | sparc_emit_set_symbolic_const64 (scratch, funexp, scratch); | |
12078 | break; | |
12079 | ||
12080 | case CM_MEDANY: | |
12081 | case CM_EMBMEDANY: | |
12082 | /* The destination cannot serve as a temporary. */ | |
12083 | spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */ | |
12084 | start_sequence (); | |
12085 | sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg); | |
12086 | seq = get_insns (); | |
12087 | end_sequence (); | |
1b970c28 | 12088 | emit_and_preserve (seq, spill_reg, 0); |
951661a1 EB |
12089 | break; |
12090 | ||
12091 | default: | |
f5f7d171 | 12092 | gcc_unreachable (); |
951661a1 EB |
12093 | } |
12094 | } | |
12095 | ||
12096 | emit_jump_insn (gen_indirect_jump (scratch)); | |
12097 | } | |
12098 | ||
e133041b RH |
12099 | emit_barrier (); |
12100 | ||
12101 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
12102 | There's not really enough bulk here to make other passes such as | |
12103 | instruction scheduling worth while. Note that use_thunk calls | |
12104 | assemble_start_function and assemble_end_function. */ | |
12105 | insn = get_insns (); | |
12106 | shorten_branches (insn); | |
12107 | final_start_function (insn, file, 1); | |
c9d691e9 | 12108 | final (insn, file, 1); |
e133041b RH |
12109 | final_end_function (); |
12110 | ||
12111 | reload_completed = 0; | |
fe3ad572 | 12112 | epilogue_completed = 0; |
e133041b | 12113 | } |
e2500fed | 12114 | |
b9bf58e5 EB |
12115 | /* Return true if sparc_output_mi_thunk would be able to output the |
12116 | assembler code for the thunk function specified by the arguments | |
12117 | it is passed, and false otherwise. */ | |
12118 | static bool | |
3101faab | 12119 | sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED, |
b9bf58e5 EB |
12120 | HOST_WIDE_INT delta ATTRIBUTE_UNUSED, |
12121 | HOST_WIDE_INT vcall_offset, | |
3101faab | 12122 | const_tree function ATTRIBUTE_UNUSED) |
b9bf58e5 EB |
12123 | { |
12124 | /* Bound the loop used in the default method above. */ | |
12125 | return (vcall_offset >= -32768 || ! fixed_regs[5]); | |
12126 | } | |
12127 | ||
5751a10b JJ |
12128 | /* How to allocate a 'struct machine_function'. */ |
12129 | ||
12130 | static struct machine_function * | |
12131 | sparc_init_machine_status (void) | |
12132 | { | |
766090c2 | 12133 | return ggc_cleared_alloc<machine_function> (); |
5751a10b JJ |
12134 | } |
12135 | ||
fdbe66f2 | 12136 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
5751a10b JJ |
12137 | We need to emit DTP-relative relocations. */ |
12138 | ||
fdbe66f2 | 12139 | static void |
5751a10b JJ |
12140 | sparc_output_dwarf_dtprel (FILE *file, int size, rtx x) |
12141 | { | |
12142 | switch (size) | |
12143 | { | |
12144 | case 4: | |
12145 | fputs ("\t.word\t%r_tls_dtpoff32(", file); | |
12146 | break; | |
12147 | case 8: | |
12148 | fputs ("\t.xword\t%r_tls_dtpoff64(", file); | |
12149 | break; | |
12150 | default: | |
f5f7d171 | 12151 | gcc_unreachable (); |
5751a10b JJ |
12152 | } |
12153 | output_addr_const (file, x); | |
12154 | fputs (")", file); | |
12155 | } | |
12156 | ||
fdbe66f2 EB |
12157 | /* Do whatever processing is required at the end of a file. */ |
12158 | ||
12159 | static void | |
12160 | sparc_file_end (void) | |
5e77eb53 | 12161 | { |
a6fed83f EB |
12162 | /* If we need to emit the special GOT helper function, do so now. */ |
12163 | if (got_helper_rtx) | |
9fd52c6c | 12164 | { |
a6fed83f EB |
12165 | const char *name = XSTR (got_helper_rtx, 0); |
12166 | const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM]; | |
9fd52c6c DM |
12167 | #ifdef DWARF2_UNWIND_INFO |
12168 | bool do_cfi; | |
12169 | #endif | |
12170 | ||
9fd52c6c DM |
12171 | if (USE_HIDDEN_LINKONCE) |
12172 | { | |
12173 | tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, | |
12174 | get_identifier (name), | |
4c203a6a NF |
12175 | build_function_type_list (void_type_node, |
12176 | NULL_TREE)); | |
9fd52c6c DM |
12177 | DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL, |
12178 | NULL_TREE, void_type_node); | |
5ff5b41c | 12179 | TREE_PUBLIC (decl) = 1; |
9fd52c6c DM |
12180 | TREE_STATIC (decl) = 1; |
12181 | make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl)); | |
12182 | DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; | |
12183 | DECL_VISIBILITY_SPECIFIED (decl) = 1; | |
b331ec2b | 12184 | resolve_unique_section (decl, 0, flag_function_sections); |
9fd52c6c | 12185 | allocate_struct_function (decl, true); |
205e4c6a | 12186 | cfun->is_thunk = 1; |
9fd52c6c DM |
12187 | current_function_decl = decl; |
12188 | init_varasm_status (); | |
12189 | assemble_start_function (decl, name); | |
12190 | } | |
12191 | else | |
12192 | { | |
12193 | const int align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
12194 | switch_to_section (text_section); | |
12195 | if (align > 0) | |
12196 | ASM_OUTPUT_ALIGN (asm_out_file, align); | |
12197 | ASM_OUTPUT_LABEL (asm_out_file, name); | |
12198 | } | |
12199 | ||
12200 | #ifdef DWARF2_UNWIND_INFO | |
12201 | do_cfi = dwarf2out_do_cfi_asm (); | |
12202 | if (do_cfi) | |
12203 | fprintf (asm_out_file, "\t.cfi_startproc\n"); | |
12204 | #endif | |
12205 | if (flag_delayed_branch) | |
12206 | fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n", | |
a6fed83f | 12207 | reg_name, reg_name); |
9fd52c6c DM |
12208 | else |
12209 | fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n", | |
a6fed83f | 12210 | reg_name, reg_name); |
9fd52c6c DM |
12211 | #ifdef DWARF2_UNWIND_INFO |
12212 | if (do_cfi) | |
12213 | fprintf (asm_out_file, "\t.cfi_endproc\n"); | |
12214 | #endif | |
12215 | } | |
5e77eb53 EB |
12216 | |
12217 | if (NEED_INDICATE_EXEC_STACK) | |
12218 | file_end_indicate_exec_stack (); | |
b6193c94 RO |
12219 | |
12220 | #ifdef TARGET_SOLARIS | |
12221 | solaris_file_end (); | |
12222 | #endif | |
5e77eb53 EB |
12223 | } |
12224 | ||
7269aee7 | 12225 | #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING |
608063c3 | 12226 | /* Implement TARGET_MANGLE_TYPE. */ |
7269aee7 AH |
12227 | |
12228 | static const char * | |
3101faab | 12229 | sparc_mangle_type (const_tree type) |
7269aee7 | 12230 | { |
7c7dae65 | 12231 | if (TARGET_ARCH32 |
7269aee7 AH |
12232 | && TYPE_MAIN_VARIANT (type) == long_double_type_node |
12233 | && TARGET_LONG_DOUBLE_128) | |
12234 | return "g"; | |
12235 | ||
12236 | /* For all other types, use normal C++ mangling. */ | |
12237 | return NULL; | |
12238 | } | |
12239 | #endif | |
12240 | ||
9a738908 RH |
12241 | /* Expand a membar instruction for various use cases. Both the LOAD_STORE |
12242 | and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where | |
12243 | bit 0 indicates that X is true, and bit 1 indicates Y is true. */ | |
12244 | ||
12245 | void | |
12246 | sparc_emit_membar_for_model (enum memmodel model, | |
12247 | int load_store, int before_after) | |
12248 | { | |
12249 | /* Bits for the MEMBAR mmask field. */ | |
12250 | const int LoadLoad = 1; | |
12251 | const int StoreLoad = 2; | |
12252 | const int LoadStore = 4; | |
12253 | const int StoreStore = 8; | |
12254 | ||
2e65f38f RH |
12255 | int mm = 0, implied = 0; |
12256 | ||
12257 | switch (sparc_memory_model) | |
12258 | { | |
12259 | case SMM_SC: | |
12260 | /* Sequential Consistency. All memory transactions are immediately | |
12261 | visible in sequential execution order. No barriers needed. */ | |
12262 | implied = LoadLoad | StoreLoad | LoadStore | StoreStore; | |
12263 | break; | |
12264 | ||
12265 | case SMM_TSO: | |
12266 | /* Total Store Ordering: all memory transactions with store semantics | |
12267 | are followed by an implied StoreStore. */ | |
12268 | implied |= StoreStore; | |
13ec0527 EB |
12269 | |
12270 | /* If we're not looking for a raw barrer (before+after), then atomic | |
12271 | operations get the benefit of being both load and store. */ | |
12272 | if (load_store == 3 && before_after == 1) | |
12273 | implied |= StoreLoad; | |
2e65f38f RH |
12274 | /* FALLTHRU */ |
12275 | ||
12276 | case SMM_PSO: | |
12277 | /* Partial Store Ordering: all memory transactions with load semantics | |
12278 | are followed by an implied LoadLoad | LoadStore. */ | |
12279 | implied |= LoadLoad | LoadStore; | |
12280 | ||
12281 | /* If we're not looking for a raw barrer (before+after), then atomic | |
12282 | operations get the benefit of being both load and store. */ | |
12283 | if (load_store == 3 && before_after == 2) | |
12284 | implied |= StoreLoad | StoreStore; | |
12285 | /* FALLTHRU */ | |
12286 | ||
12287 | case SMM_RMO: | |
12288 | /* Relaxed Memory Ordering: no implicit bits. */ | |
12289 | break; | |
12290 | ||
12291 | default: | |
12292 | gcc_unreachable (); | |
12293 | } | |
9a738908 RH |
12294 | |
12295 | if (before_after & 1) | |
12296 | { | |
46b35980 AM |
12297 | if (is_mm_release (model) || is_mm_acq_rel (model) |
12298 | || is_mm_seq_cst (model)) | |
9a738908 RH |
12299 | { |
12300 | if (load_store & 1) | |
ba6bdc29 | 12301 | mm |= LoadLoad | StoreLoad; |
9a738908 | 12302 | if (load_store & 2) |
ba6bdc29 | 12303 | mm |= LoadStore | StoreStore; |
9a738908 RH |
12304 | } |
12305 | } | |
12306 | if (before_after & 2) | |
12307 | { | |
46b35980 AM |
12308 | if (is_mm_acquire (model) || is_mm_acq_rel (model) |
12309 | || is_mm_seq_cst (model)) | |
9a738908 RH |
12310 | { |
12311 | if (load_store & 1) | |
ba6bdc29 | 12312 | mm |= LoadLoad | LoadStore; |
9a738908 | 12313 | if (load_store & 2) |
ba6bdc29 | 12314 | mm |= StoreLoad | StoreStore; |
9a738908 RH |
12315 | } |
12316 | } | |
12317 | ||
2e65f38f RH |
12318 | /* Remove the bits implied by the system memory model. */ |
12319 | mm &= ~implied; | |
12320 | ||
9a738908 RH |
12321 | /* For raw barriers (before+after), always emit a barrier. |
12322 | This will become a compile-time barrier if needed. */ | |
12323 | if (mm || before_after == 3) | |
12324 | emit_insn (gen_membar (GEN_INT (mm))); | |
12325 | } | |
12326 | ||
396b535a JJ |
12327 | /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit |
12328 | compare and swap on the word containing the byte or half-word. */ | |
12329 | ||
470b6e51 RH |
12330 | static void |
12331 | sparc_expand_compare_and_swap_12 (rtx bool_result, rtx result, rtx mem, | |
12332 | rtx oldval, rtx newval) | |
396b535a JJ |
12333 | { |
12334 | rtx addr1 = force_reg (Pmode, XEXP (mem, 0)); | |
12335 | rtx addr = gen_reg_rtx (Pmode); | |
12336 | rtx off = gen_reg_rtx (SImode); | |
12337 | rtx oldv = gen_reg_rtx (SImode); | |
12338 | rtx newv = gen_reg_rtx (SImode); | |
12339 | rtx oldvalue = gen_reg_rtx (SImode); | |
12340 | rtx newvalue = gen_reg_rtx (SImode); | |
12341 | rtx res = gen_reg_rtx (SImode); | |
12342 | rtx resv = gen_reg_rtx (SImode); | |
19f8b229 | 12343 | rtx memsi, val, mask, cc; |
396b535a | 12344 | |
f7df4a84 | 12345 | emit_insn (gen_rtx_SET (addr, gen_rtx_AND (Pmode, addr1, GEN_INT (-4)))); |
396b535a JJ |
12346 | |
12347 | if (Pmode != SImode) | |
12348 | addr1 = gen_lowpart (SImode, addr1); | |
f7df4a84 | 12349 | emit_insn (gen_rtx_SET (off, gen_rtx_AND (SImode, addr1, GEN_INT (3)))); |
396b535a JJ |
12350 | |
12351 | memsi = gen_rtx_MEM (SImode, addr); | |
44d64274 | 12352 | set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER); |
396b535a JJ |
12353 | MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem); |
12354 | ||
470b6e51 | 12355 | val = copy_to_reg (memsi); |
396b535a | 12356 | |
f7df4a84 | 12357 | emit_insn (gen_rtx_SET (off, |
396b535a JJ |
12358 | gen_rtx_XOR (SImode, off, |
12359 | GEN_INT (GET_MODE (mem) == QImode | |
12360 | ? 3 : 2)))); | |
12361 | ||
f7df4a84 | 12362 | emit_insn (gen_rtx_SET (off, gen_rtx_ASHIFT (SImode, off, GEN_INT (3)))); |
396b535a JJ |
12363 | |
12364 | if (GET_MODE (mem) == QImode) | |
12365 | mask = force_reg (SImode, GEN_INT (0xff)); | |
12366 | else | |
12367 | mask = force_reg (SImode, GEN_INT (0xffff)); | |
12368 | ||
f7df4a84 | 12369 | emit_insn (gen_rtx_SET (mask, gen_rtx_ASHIFT (SImode, mask, off))); |
396b535a | 12370 | |
f7df4a84 | 12371 | emit_insn (gen_rtx_SET (val, |
396b535a JJ |
12372 | gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask), |
12373 | val))); | |
12374 | ||
12375 | oldval = gen_lowpart (SImode, oldval); | |
f7df4a84 | 12376 | emit_insn (gen_rtx_SET (oldv, gen_rtx_ASHIFT (SImode, oldval, off))); |
396b535a JJ |
12377 | |
12378 | newval = gen_lowpart_common (SImode, newval); | |
f7df4a84 | 12379 | emit_insn (gen_rtx_SET (newv, gen_rtx_ASHIFT (SImode, newval, off))); |
396b535a | 12380 | |
f7df4a84 | 12381 | emit_insn (gen_rtx_SET (oldv, gen_rtx_AND (SImode, oldv, mask))); |
396b535a | 12382 | |
f7df4a84 | 12383 | emit_insn (gen_rtx_SET (newv, gen_rtx_AND (SImode, newv, mask))); |
396b535a | 12384 | |
19f8b229 TS |
12385 | rtx_code_label *end_label = gen_label_rtx (); |
12386 | rtx_code_label *loop_label = gen_label_rtx (); | |
396b535a JJ |
12387 | emit_label (loop_label); |
12388 | ||
f7df4a84 | 12389 | emit_insn (gen_rtx_SET (oldvalue, gen_rtx_IOR (SImode, oldv, val))); |
396b535a | 12390 | |
f7df4a84 | 12391 | emit_insn (gen_rtx_SET (newvalue, gen_rtx_IOR (SImode, newv, val))); |
396b535a | 12392 | |
470b6e51 RH |
12393 | emit_move_insn (bool_result, const1_rtx); |
12394 | ||
12395 | emit_insn (gen_atomic_compare_and_swapsi_1 (res, memsi, oldvalue, newvalue)); | |
396b535a JJ |
12396 | |
12397 | emit_cmp_and_jump_insns (res, oldvalue, EQ, NULL, SImode, 0, end_label); | |
12398 | ||
f7df4a84 | 12399 | emit_insn (gen_rtx_SET (resv, |
396b535a JJ |
12400 | gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask), |
12401 | res))); | |
12402 | ||
470b6e51 RH |
12403 | emit_move_insn (bool_result, const0_rtx); |
12404 | ||
f90b7a5a | 12405 | cc = gen_compare_reg_1 (NE, resv, val); |
f7df4a84 | 12406 | emit_insn (gen_rtx_SET (val, resv)); |
396b535a | 12407 | |
f90b7a5a PB |
12408 | /* Use cbranchcc4 to separate the compare and branch! */ |
12409 | emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode, cc, const0_rtx), | |
12410 | cc, const0_rtx, loop_label)); | |
396b535a JJ |
12411 | |
12412 | emit_label (end_label); | |
12413 | ||
f7df4a84 | 12414 | emit_insn (gen_rtx_SET (res, gen_rtx_AND (SImode, res, mask))); |
396b535a | 12415 | |
f7df4a84 | 12416 | emit_insn (gen_rtx_SET (res, gen_rtx_LSHIFTRT (SImode, res, off))); |
396b535a JJ |
12417 | |
12418 | emit_move_insn (result, gen_lowpart (GET_MODE (result), res)); | |
12419 | } | |
12420 | ||
470b6e51 RH |
12421 | /* Expand code to perform a compare-and-swap. */ |
12422 | ||
12423 | void | |
12424 | sparc_expand_compare_and_swap (rtx operands[]) | |
12425 | { | |
12426 | rtx bval, retval, mem, oldval, newval; | |
ef4bddc2 | 12427 | machine_mode mode; |
470b6e51 RH |
12428 | enum memmodel model; |
12429 | ||
12430 | bval = operands[0]; | |
12431 | retval = operands[1]; | |
12432 | mem = operands[2]; | |
12433 | oldval = operands[3]; | |
12434 | newval = operands[4]; | |
12435 | model = (enum memmodel) INTVAL (operands[6]); | |
12436 | mode = GET_MODE (mem); | |
12437 | ||
12438 | sparc_emit_membar_for_model (model, 3, 1); | |
12439 | ||
12440 | if (reg_overlap_mentioned_p (retval, oldval)) | |
12441 | oldval = copy_to_reg (oldval); | |
12442 | ||
12443 | if (mode == QImode || mode == HImode) | |
12444 | sparc_expand_compare_and_swap_12 (bval, retval, mem, oldval, newval); | |
12445 | else | |
12446 | { | |
12447 | rtx (*gen) (rtx, rtx, rtx, rtx); | |
12448 | rtx x; | |
12449 | ||
12450 | if (mode == SImode) | |
12451 | gen = gen_atomic_compare_and_swapsi_1; | |
12452 | else | |
12453 | gen = gen_atomic_compare_and_swapdi_1; | |
12454 | emit_insn (gen (retval, mem, oldval, newval)); | |
12455 | ||
12456 | x = emit_store_flag (bval, EQ, retval, oldval, mode, 1, 1); | |
12457 | if (x != bval) | |
12458 | convert_move (bval, x, 1); | |
12459 | } | |
12460 | ||
12461 | sparc_emit_membar_for_model (model, 3, 2); | |
12462 | } | |
12463 | ||
9d4dedaa | 12464 | void |
ef4bddc2 | 12465 | sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel) |
9d4dedaa RH |
12466 | { |
12467 | rtx t_1, t_2, t_3; | |
12468 | ||
12469 | sel = gen_lowpart (DImode, sel); | |
12470 | switch (vmode) | |
12471 | { | |
4e10a5a7 | 12472 | case E_V2SImode: |
9d4dedaa RH |
12473 | /* inp = xxxxxxxAxxxxxxxB */ |
12474 | t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16), | |
12475 | NULL_RTX, 1, OPTAB_DIRECT); | |
12476 | /* t_1 = ....xxxxxxxAxxx. */ | |
12477 | sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel), | |
12478 | GEN_INT (3), NULL_RTX, 1, OPTAB_DIRECT); | |
12479 | t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1), | |
12480 | GEN_INT (0x30000), NULL_RTX, 1, OPTAB_DIRECT); | |
12481 | /* sel = .......B */ | |
12482 | /* t_1 = ...A.... */ | |
12483 | sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT); | |
12484 | /* sel = ...A...B */ | |
12485 | sel = expand_mult (SImode, sel, GEN_INT (0x4444), sel, 1); | |
12486 | /* sel = AAAABBBB * 4 */ | |
12487 | t_1 = force_reg (SImode, GEN_INT (0x01230123)); | |
12488 | /* sel = { A*4, A*4+1, A*4+2, ... } */ | |
12489 | break; | |
12490 | ||
4e10a5a7 | 12491 | case E_V4HImode: |
9d4dedaa RH |
12492 | /* inp = xxxAxxxBxxxCxxxD */ |
12493 | t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8), | |
12494 | NULL_RTX, 1, OPTAB_DIRECT); | |
12495 | t_2 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16), | |
12496 | NULL_RTX, 1, OPTAB_DIRECT); | |
12497 | t_3 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (24), | |
12498 | NULL_RTX, 1, OPTAB_DIRECT); | |
12499 | /* t_1 = ..xxxAxxxBxxxCxx */ | |
12500 | /* t_2 = ....xxxAxxxBxxxC */ | |
12501 | /* t_3 = ......xxxAxxxBxx */ | |
12502 | sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel), | |
12503 | GEN_INT (0x07), | |
12504 | NULL_RTX, 1, OPTAB_DIRECT); | |
12505 | t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1), | |
12506 | GEN_INT (0x0700), | |
12507 | NULL_RTX, 1, OPTAB_DIRECT); | |
12508 | t_2 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_2), | |
12509 | GEN_INT (0x070000), | |
12510 | NULL_RTX, 1, OPTAB_DIRECT); | |
12511 | t_3 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_3), | |
12512 | GEN_INT (0x07000000), | |
12513 | NULL_RTX, 1, OPTAB_DIRECT); | |
12514 | /* sel = .......D */ | |
12515 | /* t_1 = .....C.. */ | |
12516 | /* t_2 = ...B.... */ | |
12517 | /* t_3 = .A...... */ | |
12518 | sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT); | |
12519 | t_2 = expand_simple_binop (SImode, IOR, t_2, t_3, t_2, 1, OPTAB_DIRECT); | |
12520 | sel = expand_simple_binop (SImode, IOR, sel, t_2, sel, 1, OPTAB_DIRECT); | |
12521 | /* sel = .A.B.C.D */ | |
12522 | sel = expand_mult (SImode, sel, GEN_INT (0x22), sel, 1); | |
12523 | /* sel = AABBCCDD * 2 */ | |
12524 | t_1 = force_reg (SImode, GEN_INT (0x01010101)); | |
12525 | /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */ | |
12526 | break; | |
12527 | ||
4e10a5a7 | 12528 | case E_V8QImode: |
9d4dedaa RH |
12529 | /* input = xAxBxCxDxExFxGxH */ |
12530 | sel = expand_simple_binop (DImode, AND, sel, | |
12531 | GEN_INT ((HOST_WIDE_INT)0x0f0f0f0f << 32 | |
12532 | | 0x0f0f0f0f), | |
12533 | NULL_RTX, 1, OPTAB_DIRECT); | |
12534 | /* sel = .A.B.C.D.E.F.G.H */ | |
12535 | t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (4), | |
12536 | NULL_RTX, 1, OPTAB_DIRECT); | |
12537 | /* t_1 = ..A.B.C.D.E.F.G. */ | |
12538 | sel = expand_simple_binop (DImode, IOR, sel, t_1, | |
12539 | NULL_RTX, 1, OPTAB_DIRECT); | |
12540 | /* sel = .AABBCCDDEEFFGGH */ | |
12541 | sel = expand_simple_binop (DImode, AND, sel, | |
12542 | GEN_INT ((HOST_WIDE_INT)0xff00ff << 32 | |
12543 | | 0xff00ff), | |
12544 | NULL_RTX, 1, OPTAB_DIRECT); | |
12545 | /* sel = ..AB..CD..EF..GH */ | |
12546 | t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8), | |
12547 | NULL_RTX, 1, OPTAB_DIRECT); | |
12548 | /* t_1 = ....AB..CD..EF.. */ | |
12549 | sel = expand_simple_binop (DImode, IOR, sel, t_1, | |
12550 | NULL_RTX, 1, OPTAB_DIRECT); | |
12551 | /* sel = ..ABABCDCDEFEFGH */ | |
12552 | sel = expand_simple_binop (DImode, AND, sel, | |
12553 | GEN_INT ((HOST_WIDE_INT)0xffff << 32 | 0xffff), | |
12554 | NULL_RTX, 1, OPTAB_DIRECT); | |
12555 | /* sel = ....ABCD....EFGH */ | |
12556 | t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16), | |
12557 | NULL_RTX, 1, OPTAB_DIRECT); | |
12558 | /* t_1 = ........ABCD.... */ | |
12559 | sel = gen_lowpart (SImode, sel); | |
12560 | t_1 = gen_lowpart (SImode, t_1); | |
12561 | break; | |
12562 | ||
12563 | default: | |
12564 | gcc_unreachable (); | |
12565 | } | |
12566 | ||
12567 | /* Always perform the final addition/merge within the bmask insn. */ | |
d0d48a06 | 12568 | emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, t_1)); |
9d4dedaa RH |
12569 | } |
12570 | ||
b52b1749 AS |
12571 | /* Implement TARGET_FRAME_POINTER_REQUIRED. */ |
12572 | ||
bc6d3f91 | 12573 | static bool |
b52b1749 AS |
12574 | sparc_frame_pointer_required (void) |
12575 | { | |
b11b0904 EB |
12576 | /* If the stack pointer is dynamically modified in the function, it cannot |
12577 | serve as the frame pointer. */ | |
12578 | if (cfun->calls_alloca) | |
12579 | return true; | |
12580 | ||
157b9300 EB |
12581 | /* If the function receives nonlocal gotos, it needs to save the frame |
12582 | pointer in the nonlocal_goto_save_area object. */ | |
12583 | if (cfun->has_nonlocal_label) | |
12584 | return true; | |
12585 | ||
b11b0904 EB |
12586 | /* In flat mode, that's it. */ |
12587 | if (TARGET_FLAT) | |
12588 | return false; | |
12589 | ||
7a1ae923 EB |
12590 | /* Otherwise, the frame pointer is required if the function isn't leaf, but |
12591 | we cannot use sparc_leaf_function_p since it hasn't been computed yet. */ | |
12592 | return !(optimize > 0 && crtl->is_leaf && only_leaf_regs_used ()); | |
b52b1749 AS |
12593 | } |
12594 | ||
12595 | /* The way this is structured, we can't eliminate SFP in favor of SP | |
12596 | if the frame pointer is required: we want to use the SFP->HFP elimination | |
12597 | in that case. But the test in update_eliminables doesn't know we are | |
12598 | assuming below that we only do the former elimination. */ | |
12599 | ||
bc6d3f91 | 12600 | static bool |
b52b1749 AS |
12601 | sparc_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) |
12602 | { | |
bc6d3f91 EB |
12603 | return to == HARD_FRAME_POINTER_REGNUM || !sparc_frame_pointer_required (); |
12604 | } | |
12605 | ||
12606 | /* Return the hard frame pointer directly to bypass the stack bias. */ | |
12607 | ||
12608 | static rtx | |
12609 | sparc_builtin_setjmp_frame_value (void) | |
12610 | { | |
12611 | return hard_frame_pointer_rtx; | |
b52b1749 AS |
12612 | } |
12613 | ||
5efd84c5 NF |
12614 | /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that |
12615 | they won't be allocated. */ | |
12616 | ||
12617 | static void | |
12618 | sparc_conditional_register_usage (void) | |
12619 | { | |
12620 | if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) | |
12621 | { | |
12622 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
12623 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
12624 | } | |
12625 | /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ | |
12626 | /* then honor it. */ | |
12627 | if (TARGET_ARCH32 && fixed_regs[5]) | |
12628 | fixed_regs[5] = 1; | |
12629 | else if (TARGET_ARCH64 && fixed_regs[5] == 2) | |
12630 | fixed_regs[5] = 0; | |
12631 | if (! TARGET_V9) | |
12632 | { | |
12633 | int regno; | |
12634 | for (regno = SPARC_FIRST_V9_FP_REG; | |
12635 | regno <= SPARC_LAST_V9_FP_REG; | |
12636 | regno++) | |
12637 | fixed_regs[regno] = 1; | |
12638 | /* %fcc0 is used by v8 and v9. */ | |
12639 | for (regno = SPARC_FIRST_V9_FCC_REG + 1; | |
12640 | regno <= SPARC_LAST_V9_FCC_REG; | |
12641 | regno++) | |
12642 | fixed_regs[regno] = 1; | |
12643 | } | |
12644 | if (! TARGET_FPU) | |
12645 | { | |
12646 | int regno; | |
12647 | for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) | |
12648 | fixed_regs[regno] = 1; | |
12649 | } | |
12650 | /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ | |
12651 | /* then honor it. Likewise with g3 and g4. */ | |
12652 | if (fixed_regs[2] == 2) | |
12653 | fixed_regs[2] = ! TARGET_APP_REGS; | |
12654 | if (fixed_regs[3] == 2) | |
12655 | fixed_regs[3] = ! TARGET_APP_REGS; | |
12656 | if (TARGET_ARCH32 && fixed_regs[4] == 2) | |
12657 | fixed_regs[4] = ! TARGET_APP_REGS; | |
12658 | else if (TARGET_CM_EMBMEDANY) | |
12659 | fixed_regs[4] = 1; | |
12660 | else if (fixed_regs[4] == 2) | |
12661 | fixed_regs[4] = 0; | |
b11b0904 EB |
12662 | if (TARGET_FLAT) |
12663 | { | |
12664 | int regno; | |
12665 | /* Disable leaf functions. */ | |
12666 | memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); | |
12667 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
12668 | leaf_reg_remap [regno] = regno; | |
12669 | } | |
caa06916 DM |
12670 | if (TARGET_VIS) |
12671 | global_regs[SPARC_GSR_REG] = 1; | |
5efd84c5 NF |
12672 | } |
12673 | ||
68126bad | 12674 | /* Implement TARGET_PREFERRED_RELOAD_CLASS: |
112a861d AS |
12675 | |
12676 | - We can't load constants into FP registers. | |
12677 | - We can't load FP constants into integer registers when soft-float, | |
12678 | because there is no soft-float pattern with a r/F constraint. | |
12679 | - We can't load FP constants into integer registers for TFmode unless | |
12680 | it is 0.0L, because there is no movtf pattern with a r/F constraint. | |
12681 | - Try and reload integer constants (symbolic or otherwise) back into | |
12682 | registers directly, rather than having them dumped to memory. */ | |
12683 | ||
12684 | static reg_class_t | |
12685 | sparc_preferred_reload_class (rtx x, reg_class_t rclass) | |
12686 | { | |
ef4bddc2 | 12687 | machine_mode mode = GET_MODE (x); |
112a861d AS |
12688 | if (CONSTANT_P (x)) |
12689 | { | |
12690 | if (FP_REG_CLASS_P (rclass) | |
12691 | || rclass == GENERAL_OR_FP_REGS | |
12692 | || rclass == GENERAL_OR_EXTRA_FP_REGS | |
4d1a8838 DM |
12693 | || (GET_MODE_CLASS (mode) == MODE_FLOAT && ! TARGET_FPU) |
12694 | || (mode == TFmode && ! const_zero_operand (x, mode))) | |
112a861d AS |
12695 | return NO_REGS; |
12696 | ||
4d1a8838 | 12697 | if (GET_MODE_CLASS (mode) == MODE_INT) |
112a861d | 12698 | return GENERAL_REGS; |
4d1a8838 DM |
12699 | |
12700 | if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) | |
12701 | { | |
12702 | if (! FP_REG_CLASS_P (rclass) | |
12703 | || !(const_zero_operand (x, mode) | |
12704 | || const_all_ones_operand (x, mode))) | |
12705 | return NO_REGS; | |
12706 | } | |
112a861d AS |
12707 | } |
12708 | ||
bb12a72a DM |
12709 | if (TARGET_VIS3 |
12710 | && ! TARGET_ARCH64 | |
12711 | && (rclass == EXTRA_FP_REGS | |
12712 | || rclass == GENERAL_OR_EXTRA_FP_REGS)) | |
12713 | { | |
12714 | int regno = true_regnum (x); | |
12715 | ||
12716 | if (SPARC_INT_REG_P (regno)) | |
12717 | return (rclass == EXTRA_FP_REGS | |
12718 | ? FP_REGS : GENERAL_OR_FP_REGS); | |
12719 | } | |
12720 | ||
112a861d AS |
12721 | return rclass; |
12722 | } | |
12723 | ||
f99bd883 EB |
12724 | /* Return true if we use LRA instead of reload pass. */ |
12725 | ||
12726 | static bool | |
12727 | sparc_lra_p (void) | |
12728 | { | |
12729 | return TARGET_LRA; | |
12730 | } | |
12731 | ||
68126bad EB |
12732 | /* Output a wide multiply instruction in V8+ mode. INSN is the instruction, |
12733 | OPERANDS are its operands and OPCODE is the mnemonic to be used. */ | |
12734 | ||
facb3fd7 | 12735 | const char * |
e1faf324 | 12736 | output_v8plus_mult (rtx_insn *insn, rtx *operands, const char *opcode) |
facb3fd7 DM |
12737 | { |
12738 | char mulstr[32]; | |
12739 | ||
12740 | gcc_assert (! TARGET_ARCH64); | |
12741 | ||
12742 | if (sparc_check_64 (operands[1], insn) <= 0) | |
12743 | output_asm_insn ("srl\t%L1, 0, %L1", operands); | |
12744 | if (which_alternative == 1) | |
12745 | output_asm_insn ("sllx\t%H1, 32, %H1", operands); | |
12746 | if (GET_CODE (operands[2]) == CONST_INT) | |
12747 | { | |
12748 | if (which_alternative == 1) | |
12749 | { | |
12750 | output_asm_insn ("or\t%L1, %H1, %H1", operands); | |
68126bad | 12751 | sprintf (mulstr, "%s\t%%H1, %%2, %%L0", opcode); |
facb3fd7 DM |
12752 | output_asm_insn (mulstr, operands); |
12753 | return "srlx\t%L0, 32, %H0"; | |
12754 | } | |
12755 | else | |
12756 | { | |
12757 | output_asm_insn ("sllx\t%H1, 32, %3", operands); | |
12758 | output_asm_insn ("or\t%L1, %3, %3", operands); | |
68126bad | 12759 | sprintf (mulstr, "%s\t%%3, %%2, %%3", opcode); |
facb3fd7 DM |
12760 | output_asm_insn (mulstr, operands); |
12761 | output_asm_insn ("srlx\t%3, 32, %H0", operands); | |
12762 | return "mov\t%3, %L0"; | |
12763 | } | |
12764 | } | |
12765 | else if (rtx_equal_p (operands[1], operands[2])) | |
12766 | { | |
12767 | if (which_alternative == 1) | |
12768 | { | |
12769 | output_asm_insn ("or\t%L1, %H1, %H1", operands); | |
68126bad | 12770 | sprintf (mulstr, "%s\t%%H1, %%H1, %%L0", opcode); |
facb3fd7 DM |
12771 | output_asm_insn (mulstr, operands); |
12772 | return "srlx\t%L0, 32, %H0"; | |
12773 | } | |
12774 | else | |
12775 | { | |
12776 | output_asm_insn ("sllx\t%H1, 32, %3", operands); | |
12777 | output_asm_insn ("or\t%L1, %3, %3", operands); | |
68126bad | 12778 | sprintf (mulstr, "%s\t%%3, %%3, %%3", opcode); |
facb3fd7 DM |
12779 | output_asm_insn (mulstr, operands); |
12780 | output_asm_insn ("srlx\t%3, 32, %H0", operands); | |
12781 | return "mov\t%3, %L0"; | |
12782 | } | |
12783 | } | |
12784 | if (sparc_check_64 (operands[2], insn) <= 0) | |
12785 | output_asm_insn ("srl\t%L2, 0, %L2", operands); | |
12786 | if (which_alternative == 1) | |
12787 | { | |
12788 | output_asm_insn ("or\t%L1, %H1, %H1", operands); | |
12789 | output_asm_insn ("sllx\t%H2, 32, %L1", operands); | |
12790 | output_asm_insn ("or\t%L2, %L1, %L1", operands); | |
68126bad | 12791 | sprintf (mulstr, "%s\t%%H1, %%L1, %%L0", opcode); |
facb3fd7 DM |
12792 | output_asm_insn (mulstr, operands); |
12793 | return "srlx\t%L0, 32, %H0"; | |
12794 | } | |
12795 | else | |
12796 | { | |
12797 | output_asm_insn ("sllx\t%H1, 32, %3", operands); | |
12798 | output_asm_insn ("sllx\t%H2, 32, %4", operands); | |
12799 | output_asm_insn ("or\t%L1, %3, %3", operands); | |
12800 | output_asm_insn ("or\t%L2, %4, %4", operands); | |
68126bad | 12801 | sprintf (mulstr, "%s\t%%3, %%4, %%3", opcode); |
facb3fd7 DM |
12802 | output_asm_insn (mulstr, operands); |
12803 | output_asm_insn ("srlx\t%3, 32, %H0", operands); | |
12804 | return "mov\t%3, %L0"; | |
12805 | } | |
12806 | } | |
12807 | ||
2b38137d DM |
12808 | /* Subroutine of sparc_expand_vector_init. Emit code to initialize |
12809 | all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE | |
12810 | and INNER_MODE are the modes describing TARGET. */ | |
68126bad | 12811 | |
f6b29aeb | 12812 | static void |
ef4bddc2 RS |
12813 | vector_init_bshuffle (rtx target, rtx elt, machine_mode mode, |
12814 | machine_mode inner_mode) | |
f6b29aeb | 12815 | { |
2f56a311 | 12816 | rtx t1, final_insn, sel; |
2b38137d | 12817 | int bmask; |
f6b29aeb | 12818 | |
2b38137d | 12819 | t1 = gen_reg_rtx (mode); |
f6b29aeb | 12820 | |
2b38137d DM |
12821 | elt = convert_modes (SImode, inner_mode, elt, true); |
12822 | emit_move_insn (gen_lowpart(SImode, t1), elt); | |
f6b29aeb | 12823 | |
2b38137d | 12824 | switch (mode) |
79cad86d | 12825 | { |
4e10a5a7 | 12826 | case E_V2SImode: |
2b38137d DM |
12827 | final_insn = gen_bshufflev2si_vis (target, t1, t1); |
12828 | bmask = 0x45674567; | |
12829 | break; | |
4e10a5a7 | 12830 | case E_V4HImode: |
2b38137d DM |
12831 | final_insn = gen_bshufflev4hi_vis (target, t1, t1); |
12832 | bmask = 0x67676767; | |
79cad86d | 12833 | break; |
4e10a5a7 | 12834 | case E_V8QImode: |
2b38137d DM |
12835 | final_insn = gen_bshufflev8qi_vis (target, t1, t1); |
12836 | bmask = 0x77777777; | |
79cad86d DM |
12837 | break; |
12838 | default: | |
12839 | gcc_unreachable (); | |
12840 | } | |
f6b29aeb | 12841 | |
2f56a311 | 12842 | sel = force_reg (SImode, GEN_INT (bmask)); |
d0d48a06 | 12843 | emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, const0_rtx)); |
2b38137d | 12844 | emit_insn (final_insn); |
79cad86d DM |
12845 | } |
12846 | ||
98e4350f EB |
12847 | /* Subroutine of sparc_expand_vector_init. Emit code to initialize |
12848 | all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */ | |
12849 | ||
f6b29aeb | 12850 | static void |
98e4350f | 12851 | vector_init_fpmerge (rtx target, rtx elt) |
f6b29aeb | 12852 | { |
98e4350f | 12853 | rtx t1, t2, t2_low, t3, t3_low; |
f6b29aeb | 12854 | |
2b38137d | 12855 | t1 = gen_reg_rtx (V4QImode); |
98e4350f | 12856 | elt = convert_modes (SImode, QImode, elt, true); |
2b38137d | 12857 | emit_move_insn (gen_lowpart (SImode, t1), elt); |
f6b29aeb | 12858 | |
98e4350f EB |
12859 | t2 = gen_reg_rtx (V8QImode); |
12860 | t2_low = gen_lowpart (V4QImode, t2); | |
12861 | emit_insn (gen_fpmerge_vis (t2, t1, t1)); | |
79cad86d | 12862 | |
2b38137d DM |
12863 | t3 = gen_reg_rtx (V8QImode); |
12864 | t3_low = gen_lowpart (V4QImode, t3); | |
98e4350f | 12865 | emit_insn (gen_fpmerge_vis (t3, t2_low, t2_low)); |
79cad86d | 12866 | |
98e4350f | 12867 | emit_insn (gen_fpmerge_vis (target, t3_low, t3_low)); |
f6b29aeb DM |
12868 | } |
12869 | ||
98e4350f EB |
12870 | /* Subroutine of sparc_expand_vector_init. Emit code to initialize |
12871 | all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */ | |
12872 | ||
0182eb8a | 12873 | static void |
98e4350f | 12874 | vector_init_faligndata (rtx target, rtx elt) |
0182eb8a | 12875 | { |
2b38137d | 12876 | rtx t1 = gen_reg_rtx (V4HImode); |
98e4350f | 12877 | int i; |
0182eb8a | 12878 | |
98e4350f | 12879 | elt = convert_modes (SImode, HImode, elt, true); |
2b38137d | 12880 | emit_move_insn (gen_lowpart (SImode, t1), elt); |
0182eb8a DM |
12881 | |
12882 | emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode), | |
2b38137d | 12883 | force_reg (SImode, GEN_INT (6)), |
98e4350f | 12884 | const0_rtx)); |
0182eb8a | 12885 | |
98e4350f EB |
12886 | for (i = 0; i < 4; i++) |
12887 | emit_insn (gen_faligndatav4hi_vis (target, t1, target)); | |
0182eb8a DM |
12888 | } |
12889 | ||
68126bad EB |
12890 | /* Emit code to initialize TARGET to values for individual fields VALS. */ |
12891 | ||
e00560c2 DM |
12892 | void |
12893 | sparc_expand_vector_init (rtx target, rtx vals) | |
12894 | { | |
ef4bddc2 RS |
12895 | const machine_mode mode = GET_MODE (target); |
12896 | const machine_mode inner_mode = GET_MODE_INNER (mode); | |
98e4350f | 12897 | const int n_elts = GET_MODE_NUNITS (mode); |
2b38137d | 12898 | int i, n_var = 0; |
855db698 | 12899 | bool all_same = true; |
2b38137d | 12900 | rtx mem; |
e00560c2 DM |
12901 | |
12902 | for (i = 0; i < n_elts; i++) | |
12903 | { | |
12904 | rtx x = XVECEXP (vals, 0, i); | |
855db698 | 12905 | if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x))) |
e00560c2 | 12906 | n_var++; |
f6b29aeb | 12907 | |
2b38137d DM |
12908 | if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) |
12909 | all_same = false; | |
e00560c2 DM |
12910 | } |
12911 | ||
12912 | if (n_var == 0) | |
12913 | { | |
12914 | emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0))); | |
12915 | return; | |
12916 | } | |
12917 | ||
2b38137d DM |
12918 | if (GET_MODE_SIZE (inner_mode) == GET_MODE_SIZE (mode)) |
12919 | { | |
12920 | if (GET_MODE_SIZE (inner_mode) == 4) | |
12921 | { | |
12922 | emit_move_insn (gen_lowpart (SImode, target), | |
12923 | gen_lowpart (SImode, XVECEXP (vals, 0, 0))); | |
12924 | return; | |
12925 | } | |
12926 | else if (GET_MODE_SIZE (inner_mode) == 8) | |
12927 | { | |
12928 | emit_move_insn (gen_lowpart (DImode, target), | |
12929 | gen_lowpart (DImode, XVECEXP (vals, 0, 0))); | |
12930 | return; | |
12931 | } | |
12932 | } | |
12933 | else if (GET_MODE_SIZE (inner_mode) == GET_MODE_SIZE (word_mode) | |
12934 | && GET_MODE_SIZE (mode) == 2 * GET_MODE_SIZE (word_mode)) | |
12935 | { | |
12936 | emit_move_insn (gen_highpart (word_mode, target), | |
12937 | gen_lowpart (word_mode, XVECEXP (vals, 0, 0))); | |
12938 | emit_move_insn (gen_lowpart (word_mode, target), | |
12939 | gen_lowpart (word_mode, XVECEXP (vals, 0, 1))); | |
12940 | return; | |
12941 | } | |
f6b29aeb | 12942 | |
2b38137d DM |
12943 | if (all_same && GET_MODE_SIZE (mode) == 8) |
12944 | { | |
12945 | if (TARGET_VIS2) | |
12946 | { | |
12947 | vector_init_bshuffle (target, XVECEXP (vals, 0, 0), mode, inner_mode); | |
12948 | return; | |
12949 | } | |
12950 | if (mode == V8QImode) | |
12951 | { | |
98e4350f | 12952 | vector_init_fpmerge (target, XVECEXP (vals, 0, 0)); |
2b38137d DM |
12953 | return; |
12954 | } | |
12955 | if (mode == V4HImode) | |
12956 | { | |
98e4350f | 12957 | vector_init_faligndata (target, XVECEXP (vals, 0, 0)); |
2b38137d DM |
12958 | return; |
12959 | } | |
12960 | } | |
f6b29aeb | 12961 | |
9474e8ab | 12962 | mem = assign_stack_temp (mode, GET_MODE_SIZE (mode)); |
2b38137d DM |
12963 | for (i = 0; i < n_elts; i++) |
12964 | emit_move_insn (adjust_address_nv (mem, inner_mode, | |
12965 | i * GET_MODE_SIZE (inner_mode)), | |
12966 | XVECEXP (vals, 0, i)); | |
12967 | emit_move_insn (target, mem); | |
e00560c2 DM |
12968 | } |
12969 | ||
68126bad EB |
12970 | /* Implement TARGET_SECONDARY_RELOAD. */ |
12971 | ||
9dc98917 DM |
12972 | static reg_class_t |
12973 | sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, | |
ef4bddc2 | 12974 | machine_mode mode, secondary_reload_info *sri) |
9dc98917 DM |
12975 | { |
12976 | enum reg_class rclass = (enum reg_class) rclass_i; | |
12977 | ||
bb12a72a DM |
12978 | sri->icode = CODE_FOR_nothing; |
12979 | sri->extra_cost = 0; | |
12980 | ||
9dc98917 DM |
12981 | /* We need a temporary when loading/storing a HImode/QImode value |
12982 | between memory and the FPU registers. This can happen when combine puts | |
12983 | a paradoxical subreg in a float/fix conversion insn. */ | |
12984 | if (FP_REG_CLASS_P (rclass) | |
12985 | && (mode == HImode || mode == QImode) | |
12986 | && (GET_CODE (x) == MEM | |
12987 | || ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG) | |
12988 | && true_regnum (x) == -1))) | |
12989 | return GENERAL_REGS; | |
12990 | ||
12991 | /* On 32-bit we need a temporary when loading/storing a DFmode value | |
12992 | between unaligned memory and the upper FPU registers. */ | |
12993 | if (TARGET_ARCH32 | |
12994 | && rclass == EXTRA_FP_REGS | |
12995 | && mode == DFmode | |
12996 | && GET_CODE (x) == MEM | |
12997 | && ! mem_min_alignment (x, 8)) | |
12998 | return FP_REGS; | |
12999 | ||
13000 | if (((TARGET_CM_MEDANY | |
13001 | && symbolic_operand (x, mode)) | |
13002 | || (TARGET_CM_EMBMEDANY | |
13003 | && text_segment_operand (x, mode))) | |
13004 | && ! flag_pic) | |
13005 | { | |
13006 | if (in_p) | |
13007 | sri->icode = direct_optab_handler (reload_in_optab, mode); | |
13008 | else | |
13009 | sri->icode = direct_optab_handler (reload_out_optab, mode); | |
13010 | return NO_REGS; | |
13011 | } | |
13012 | ||
bb12a72a DM |
13013 | if (TARGET_VIS3 && TARGET_ARCH32) |
13014 | { | |
13015 | int regno = true_regnum (x); | |
13016 | ||
13017 | /* When using VIS3 fp<-->int register moves, on 32-bit we have | |
13018 | to move 8-byte values in 4-byte pieces. This only works via | |
13019 | FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to | |
13020 | move between EXTRA_FP_REGS and GENERAL_REGS, we will need | |
13021 | an FP_REGS intermediate move. */ | |
13022 | if ((rclass == EXTRA_FP_REGS && SPARC_INT_REG_P (regno)) | |
13023 | || ((general_or_i64_p (rclass) | |
13024 | || rclass == GENERAL_OR_FP_REGS) | |
13025 | && SPARC_FP_REG_P (regno))) | |
13026 | { | |
13027 | sri->extra_cost = 2; | |
13028 | return FP_REGS; | |
13029 | } | |
13030 | } | |
13031 | ||
9dc98917 DM |
13032 | return NO_REGS; |
13033 | } | |
13034 | ||
68126bad EB |
13035 | /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into |
13036 | OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */ | |
13037 | ||
bf84f42d | 13038 | bool |
ef4bddc2 | 13039 | sparc_expand_conditional_move (machine_mode mode, rtx *operands) |
bf84f42d DM |
13040 | { |
13041 | enum rtx_code rc = GET_CODE (operands[1]); | |
ef4bddc2 | 13042 | machine_mode cmp_mode; |
bf84f42d DM |
13043 | rtx cc_reg, dst, cmp; |
13044 | ||
13045 | cmp = operands[1]; | |
7a83e5bc | 13046 | if (GET_MODE (XEXP (cmp, 0)) == DImode && !TARGET_ARCH64) |
bf84f42d DM |
13047 | return false; |
13048 | ||
7a83e5bc DM |
13049 | if (GET_MODE (XEXP (cmp, 0)) == TFmode && !TARGET_HARD_QUAD) |
13050 | cmp = sparc_emit_float_lib_cmp (XEXP (cmp, 0), XEXP (cmp, 1), rc); | |
13051 | ||
13052 | cmp_mode = GET_MODE (XEXP (cmp, 0)); | |
13053 | rc = GET_CODE (cmp); | |
bf84f42d | 13054 | |
7a83e5bc | 13055 | dst = operands[0]; |
bf84f42d DM |
13056 | if (! rtx_equal_p (operands[2], dst) |
13057 | && ! rtx_equal_p (operands[3], dst)) | |
13058 | { | |
13059 | if (reg_overlap_mentioned_p (dst, cmp)) | |
13060 | dst = gen_reg_rtx (mode); | |
13061 | ||
13062 | emit_move_insn (dst, operands[3]); | |
13063 | } | |
13064 | else if (operands[2] == dst) | |
13065 | { | |
13066 | operands[2] = operands[3]; | |
13067 | ||
13068 | if (GET_MODE_CLASS (cmp_mode) == MODE_FLOAT) | |
13069 | rc = reverse_condition_maybe_unordered (rc); | |
13070 | else | |
13071 | rc = reverse_condition (rc); | |
13072 | } | |
13073 | ||
bf84f42d DM |
13074 | if (XEXP (cmp, 1) == const0_rtx |
13075 | && GET_CODE (XEXP (cmp, 0)) == REG | |
13076 | && cmp_mode == DImode | |
13077 | && v9_regcmp_p (rc)) | |
13078 | cc_reg = XEXP (cmp, 0); | |
13079 | else | |
13080 | cc_reg = gen_compare_reg_1 (rc, XEXP (cmp, 0), XEXP (cmp, 1)); | |
13081 | ||
13082 | cmp = gen_rtx_fmt_ee (rc, GET_MODE (cc_reg), cc_reg, const0_rtx); | |
13083 | ||
f7df4a84 | 13084 | emit_insn (gen_rtx_SET (dst, |
bf84f42d DM |
13085 | gen_rtx_IF_THEN_ELSE (mode, cmp, operands[2], dst))); |
13086 | ||
13087 | if (dst != operands[0]) | |
13088 | emit_move_insn (operands[0], dst); | |
13089 | ||
13090 | return true; | |
13091 | } | |
13092 | ||
68126bad EB |
13093 | /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2] |
13094 | into OPERANDS[0] in MODE, depending on the outcome of the comparison of | |
13095 | OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition. | |
13096 | FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine | |
13097 | code to be used for the condition mask. */ | |
13098 | ||
1f9ed162 | 13099 | void |
ef4bddc2 | 13100 | sparc_expand_vcond (machine_mode mode, rtx *operands, int ccode, int fcode) |
1f9ed162 DM |
13101 | { |
13102 | rtx mask, cop0, cop1, fcmp, cmask, bshuf, gsr; | |
13103 | enum rtx_code code = GET_CODE (operands[3]); | |
13104 | ||
13105 | mask = gen_reg_rtx (Pmode); | |
13106 | cop0 = operands[4]; | |
13107 | cop1 = operands[5]; | |
13108 | if (code == LT || code == GE) | |
13109 | { | |
13110 | rtx t; | |
13111 | ||
13112 | code = swap_condition (code); | |
13113 | t = cop0; cop0 = cop1; cop1 = t; | |
13114 | } | |
13115 | ||
13116 | gsr = gen_rtx_REG (DImode, SPARC_GSR_REG); | |
13117 | ||
13118 | fcmp = gen_rtx_UNSPEC (Pmode, | |
13119 | gen_rtvec (1, gen_rtx_fmt_ee (code, mode, cop0, cop1)), | |
13120 | fcode); | |
13121 | ||
13122 | cmask = gen_rtx_UNSPEC (DImode, | |
13123 | gen_rtvec (2, mask, gsr), | |
13124 | ccode); | |
13125 | ||
13126 | bshuf = gen_rtx_UNSPEC (mode, | |
13127 | gen_rtvec (3, operands[1], operands[2], gsr), | |
13128 | UNSPEC_BSHUFFLE); | |
13129 | ||
f7df4a84 RS |
13130 | emit_insn (gen_rtx_SET (mask, fcmp)); |
13131 | emit_insn (gen_rtx_SET (gsr, cmask)); | |
1f9ed162 | 13132 | |
f7df4a84 | 13133 | emit_insn (gen_rtx_SET (operands[0], bshuf)); |
1f9ed162 DM |
13134 | } |
13135 | ||
98ccb32d DM |
13136 | /* On sparc, any mode which naturally allocates into the float |
13137 | registers should return 4 here. */ | |
13138 | ||
13139 | unsigned int | |
ef4bddc2 | 13140 | sparc_regmode_natural_size (machine_mode mode) |
98ccb32d DM |
13141 | { |
13142 | int size = UNITS_PER_WORD; | |
13143 | ||
13144 | if (TARGET_ARCH64) | |
13145 | { | |
13146 | enum mode_class mclass = GET_MODE_CLASS (mode); | |
13147 | ||
13148 | if (mclass == MODE_FLOAT || mclass == MODE_VECTOR_INT) | |
13149 | size = 4; | |
13150 | } | |
13151 | ||
13152 | return size; | |
13153 | } | |
13154 | ||
c43f4279 RS |
13155 | /* Implement TARGET_HARD_REGNO_NREGS. |
13156 | ||
13157 | On SPARC, ordinary registers hold 32 bits worth; this means both | |
13158 | integer and floating point registers. On v9, integer regs hold 64 | |
13159 | bits worth; floating point regs hold 32 bits worth (this includes the | |
13160 | new fp regs as even the odd ones are included in the hard register | |
13161 | count). */ | |
13162 | ||
13163 | static unsigned int | |
13164 | sparc_hard_regno_nregs (unsigned int regno, machine_mode mode) | |
13165 | { | |
13166 | if (regno == SPARC_GSR_REG) | |
13167 | return 1; | |
13168 | if (TARGET_ARCH64) | |
13169 | { | |
13170 | if (SPARC_INT_REG_P (regno) || regno == FRAME_POINTER_REGNUM) | |
13171 | return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD); | |
13172 | return CEIL (GET_MODE_SIZE (mode), 4); | |
13173 | } | |
13174 | return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD); | |
13175 | } | |
13176 | ||
f939c3e6 RS |
13177 | /* Implement TARGET_HARD_REGNO_MODE_OK. |
13178 | ||
13179 | ??? Because of the funny way we pass parameters we should allow certain | |
13180 | ??? types of float/complex values to be in integer registers during | |
13181 | ??? RTL generation. This only matters on arch32. */ | |
13182 | ||
13183 | static bool | |
13184 | sparc_hard_regno_mode_ok (unsigned int regno, machine_mode mode) | |
13185 | { | |
13186 | return (hard_regno_mode_classes[regno] & sparc_mode_class[mode]) != 0; | |
13187 | } | |
13188 | ||
99e1629f | 13189 | /* Implement TARGET_MODES_TIEABLE_P. |
98ccb32d DM |
13190 | |
13191 | For V9 we have to deal with the fact that only the lower 32 floating | |
13192 | point registers are 32-bit addressable. */ | |
13193 | ||
99e1629f | 13194 | static bool |
ef4bddc2 | 13195 | sparc_modes_tieable_p (machine_mode mode1, machine_mode mode2) |
98ccb32d DM |
13196 | { |
13197 | enum mode_class mclass1, mclass2; | |
13198 | unsigned short size1, size2; | |
13199 | ||
13200 | if (mode1 == mode2) | |
13201 | return true; | |
13202 | ||
13203 | mclass1 = GET_MODE_CLASS (mode1); | |
13204 | mclass2 = GET_MODE_CLASS (mode2); | |
13205 | if (mclass1 != mclass2) | |
13206 | return false; | |
13207 | ||
13208 | if (! TARGET_V9) | |
13209 | return true; | |
13210 | ||
13211 | /* Classes are the same and we are V9 so we have to deal with upper | |
13212 | vs. lower floating point registers. If one of the modes is a | |
13213 | 4-byte mode, and the other is not, we have to mark them as not | |
13214 | tieable because only the lower 32 floating point register are | |
13215 | addressable 32-bits at a time. | |
13216 | ||
13217 | We can't just test explicitly for SFmode, otherwise we won't | |
13218 | cover the vector mode cases properly. */ | |
13219 | ||
13220 | if (mclass1 != MODE_FLOAT && mclass1 != MODE_VECTOR_INT) | |
13221 | return true; | |
13222 | ||
13223 | size1 = GET_MODE_SIZE (mode1); | |
13224 | size2 = GET_MODE_SIZE (mode2); | |
13225 | if ((size1 > 4 && size2 == 4) | |
13226 | || (size2 > 4 && size1 == 4)) | |
13227 | return false; | |
13228 | ||
13229 | return true; | |
13230 | } | |
13231 | ||
fde66fde EB |
13232 | /* Implement TARGET_CSTORE_MODE. */ |
13233 | ||
7cc237a6 | 13234 | static scalar_int_mode |
fde66fde | 13235 | sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED) |
42e37616 DM |
13236 | { |
13237 | return (TARGET_ARCH64 ? DImode : SImode); | |
13238 | } | |
13239 | ||
fde66fde EB |
13240 | /* Return the compound expression made of T1 and T2. */ |
13241 | ||
13242 | static inline tree | |
13243 | compound_expr (tree t1, tree t2) | |
13244 | { | |
13245 | return build2 (COMPOUND_EXPR, void_type_node, t1, t2); | |
13246 | } | |
13247 | ||
13248 | /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */ | |
13249 | ||
13250 | static void | |
13251 | sparc_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) | |
13252 | { | |
13253 | if (!TARGET_FPU) | |
13254 | return; | |
13255 | ||
13256 | const unsigned HOST_WIDE_INT accrued_exception_mask = 0x1f << 5; | |
13257 | const unsigned HOST_WIDE_INT trap_enable_mask = 0x1f << 23; | |
13258 | ||
13259 | /* We generate the equivalent of feholdexcept (&fenv_var): | |
13260 | ||
13261 | unsigned int fenv_var; | |
13262 | __builtin_store_fsr (&fenv_var); | |
13263 | ||
13264 | unsigned int tmp1_var; | |
13265 | tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask); | |
13266 | ||
13267 | __builtin_load_fsr (&tmp1_var); */ | |
13268 | ||
68ea7618 EB |
13269 | tree fenv_var = create_tmp_var_raw (unsigned_type_node); |
13270 | TREE_ADDRESSABLE (fenv_var) = 1; | |
fde66fde EB |
13271 | tree fenv_addr = build_fold_addr_expr (fenv_var); |
13272 | tree stfsr = sparc_builtins[SPARC_BUILTIN_STFSR]; | |
68ea7618 EB |
13273 | tree hold_stfsr |
13274 | = build4 (TARGET_EXPR, unsigned_type_node, fenv_var, | |
13275 | build_call_expr (stfsr, 1, fenv_addr), NULL_TREE, NULL_TREE); | |
fde66fde | 13276 | |
68ea7618 EB |
13277 | tree tmp1_var = create_tmp_var_raw (unsigned_type_node); |
13278 | TREE_ADDRESSABLE (tmp1_var) = 1; | |
fde66fde EB |
13279 | tree masked_fenv_var |
13280 | = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, | |
13281 | build_int_cst (unsigned_type_node, | |
13282 | ~(accrued_exception_mask | trap_enable_mask))); | |
13283 | tree hold_mask | |
68ea7618 EB |
13284 | = build4 (TARGET_EXPR, unsigned_type_node, tmp1_var, masked_fenv_var, |
13285 | NULL_TREE, NULL_TREE); | |
fde66fde EB |
13286 | |
13287 | tree tmp1_addr = build_fold_addr_expr (tmp1_var); | |
13288 | tree ldfsr = sparc_builtins[SPARC_BUILTIN_LDFSR]; | |
13289 | tree hold_ldfsr = build_call_expr (ldfsr, 1, tmp1_addr); | |
13290 | ||
13291 | *hold = compound_expr (compound_expr (hold_stfsr, hold_mask), hold_ldfsr); | |
13292 | ||
13293 | /* We reload the value of tmp1_var to clear the exceptions: | |
13294 | ||
13295 | __builtin_load_fsr (&tmp1_var); */ | |
13296 | ||
13297 | *clear = build_call_expr (ldfsr, 1, tmp1_addr); | |
13298 | ||
13299 | /* We generate the equivalent of feupdateenv (&fenv_var): | |
13300 | ||
13301 | unsigned int tmp2_var; | |
13302 | __builtin_store_fsr (&tmp2_var); | |
13303 | ||
13304 | __builtin_load_fsr (&fenv_var); | |
13305 | ||
13306 | if (SPARC_LOW_FE_EXCEPT_VALUES) | |
13307 | tmp2_var >>= 5; | |
13308 | __atomic_feraiseexcept ((int) tmp2_var); */ | |
13309 | ||
68ea7618 EB |
13310 | tree tmp2_var = create_tmp_var_raw (unsigned_type_node); |
13311 | TREE_ADDRESSABLE (tmp2_var) = 1; | |
13312 | tree tmp2_addr = build_fold_addr_expr (tmp2_var); | |
13313 | tree update_stfsr | |
13314 | = build4 (TARGET_EXPR, unsigned_type_node, tmp2_var, | |
13315 | build_call_expr (stfsr, 1, tmp2_addr), NULL_TREE, NULL_TREE); | |
fde66fde EB |
13316 | |
13317 | tree update_ldfsr = build_call_expr (ldfsr, 1, fenv_addr); | |
13318 | ||
13319 | tree atomic_feraiseexcept | |
13320 | = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT); | |
13321 | tree update_call | |
13322 | = build_call_expr (atomic_feraiseexcept, 1, | |
13323 | fold_convert (integer_type_node, tmp2_var)); | |
13324 | ||
13325 | if (SPARC_LOW_FE_EXCEPT_VALUES) | |
13326 | { | |
13327 | tree shifted_tmp2_var | |
13328 | = build2 (RSHIFT_EXPR, unsigned_type_node, tmp2_var, | |
13329 | build_int_cst (unsigned_type_node, 5)); | |
13330 | tree update_shift | |
13331 | = build2 (MODIFY_EXPR, void_type_node, tmp2_var, shifted_tmp2_var); | |
13332 | update_call = compound_expr (update_shift, update_call); | |
13333 | } | |
13334 | ||
13335 | *update | |
13336 | = compound_expr (compound_expr (update_stfsr, update_ldfsr), update_call); | |
13337 | } | |
13338 | ||
e2500fed | 13339 | #include "gt-sparc.h" |