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c3427c7d 1/* Subroutines for insn-output.c for SPARC.
4592bdcb 2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
bbbbb16a 3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
62de55f7 4 Free Software Foundation, Inc.
ab835497 5 Contributed by Michael Tiemann (tiemann@cygnus.com)
c3427c7d 6 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
61a55e8b 7 at Cygnus Support.
ab835497 8
4d8af13f 9This file is part of GCC.
ab835497 10
4d8af13f 11GCC is free software; you can redistribute it and/or modify
ab835497 12it under the terms of the GNU General Public License as published by
2f83c7d6 13the Free Software Foundation; either version 3, or (at your option)
ab835497
RK		 14any later version.
15
4d8af13f 16GCC is distributed in the hope that it will be useful,
ab835497
RK		 17but WITHOUT ANY WARRANTY; without even the implied warranty of
18MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19GNU General Public License for more details.
20
21You should have received a copy of the GNU General Public License
2f83c7d6
NC		 22along with GCC; see the file COPYING3. If not see
23<http://www.gnu.org/licenses/>. */
ab835497 24
ab835497 25#include "config.h"
284d86e9 26#include "system.h"
4977bab6
ZW		 27#include "coretypes.h"
28#include "tm.h"
210aa14a 29#include "tree.h"
ab835497
RK		 30#include "rtl.h"
31#include "regs.h"
32#include "hard-reg-set.h"
33#include "real.h"
34#include "insn-config.h"
16f59241 35#include "insn-codes.h"
ab835497 36#include "conditions.h"
ab835497
RK		 37#include "output.h"
38#include "insn-attr.h"
39#include "flags.h"
49ad7cfa 40#include "function.h"
ab835497 41#include "expr.h"
e78d8e51 42#include "optabs.h"
ab835497 43#include "recog.h"
487a6e06 44#include "toplev.h"
d07d525a 45#include "ggc.h"
b1474bb7 46#include "tm_p.h"
e78d8e51 47#include "debug.h"
672a6f42
NB		 48#include "target.h"
49#include "target-def.h"
117dca74 50#include "cfglayout.h"
726a989a 51#include "gimple.h"
16f59241 52#include "langhooks.h"
47eb5b32 53#include "params.h"
6fb5fa3c 54#include "df.h"
ab835497 55
18df6de9
DM		 56/* Processor costs */
57static const
58struct processor_costs cypress_costs = {
ffe384ff
DM		 59 COSTS_N_INSNS (2), /* int load */
60 COSTS_N_INSNS (2), /* int signed load */
61 COSTS_N_INSNS (2), /* int zeroed load */
62 COSTS_N_INSNS (2), /* float load */
63 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
64 COSTS_N_INSNS (5), /* fadd, fsub */
65 COSTS_N_INSNS (1), /* fcmp */
66 COSTS_N_INSNS (1), /* fmov, fmovr */
67 COSTS_N_INSNS (7), /* fmul */
68 COSTS_N_INSNS (37), /* fdivs */
69 COSTS_N_INSNS (37), /* fdivd */
70 COSTS_N_INSNS (63), /* fsqrts */
71 COSTS_N_INSNS (63), /* fsqrtd */
72 COSTS_N_INSNS (1), /* imul */
73 COSTS_N_INSNS (1), /* imulX */
18df6de9 74 0, /* imul bit factor */
ffe384ff
DM		 75 COSTS_N_INSNS (1), /* idiv */
76 COSTS_N_INSNS (1), /* idivX */
77 COSTS_N_INSNS (1), /* movcc/movr */
18df6de9
DM		 78 0, /* shift penalty */
79};
80
81static const
82struct processor_costs supersparc_costs = {
ffe384ff
DM		 83 COSTS_N_INSNS (1), /* int load */
84 COSTS_N_INSNS (1), /* int signed load */
85 COSTS_N_INSNS (1), /* int zeroed load */
86 COSTS_N_INSNS (0), /* float load */
87 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
88 COSTS_N_INSNS (3), /* fadd, fsub */
89 COSTS_N_INSNS (3), /* fcmp */
90 COSTS_N_INSNS (1), /* fmov, fmovr */
91 COSTS_N_INSNS (3), /* fmul */
92 COSTS_N_INSNS (6), /* fdivs */
93 COSTS_N_INSNS (9), /* fdivd */
94 COSTS_N_INSNS (12), /* fsqrts */
95 COSTS_N_INSNS (12), /* fsqrtd */
96 COSTS_N_INSNS (4), /* imul */
97 COSTS_N_INSNS (4), /* imulX */
18df6de9 98 0, /* imul bit factor */
ffe384ff
DM		 99 COSTS_N_INSNS (4), /* idiv */
100 COSTS_N_INSNS (4), /* idivX */
101 COSTS_N_INSNS (1), /* movcc/movr */
18df6de9
DM		 102 1, /* shift penalty */
103};
104
105static const
106struct processor_costs hypersparc_costs = {
ffe384ff
DM		 107 COSTS_N_INSNS (1), /* int load */
108 COSTS_N_INSNS (1), /* int signed load */
109 COSTS_N_INSNS (1), /* int zeroed load */
110 COSTS_N_INSNS (1), /* float load */
111 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
112 COSTS_N_INSNS (1), /* fadd, fsub */
113 COSTS_N_INSNS (1), /* fcmp */
114 COSTS_N_INSNS (1), /* fmov, fmovr */
115 COSTS_N_INSNS (1), /* fmul */
116 COSTS_N_INSNS (8), /* fdivs */
117 COSTS_N_INSNS (12), /* fdivd */
118 COSTS_N_INSNS (17), /* fsqrts */
119 COSTS_N_INSNS (17), /* fsqrtd */
120 COSTS_N_INSNS (17), /* imul */
121 COSTS_N_INSNS (17), /* imulX */
18df6de9 122 0, /* imul bit factor */
ffe384ff
DM		 123 COSTS_N_INSNS (17), /* idiv */
124 COSTS_N_INSNS (17), /* idivX */
125 COSTS_N_INSNS (1), /* movcc/movr */
18df6de9
DM		 126 0, /* shift penalty */
127};
128
129static const
130struct processor_costs sparclet_costs = {
ffe384ff
DM		 131 COSTS_N_INSNS (3), /* int load */
132 COSTS_N_INSNS (3), /* int signed load */
133 COSTS_N_INSNS (1), /* int zeroed load */
134 COSTS_N_INSNS (1), /* float load */
135 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
136 COSTS_N_INSNS (1), /* fadd, fsub */
137 COSTS_N_INSNS (1), /* fcmp */
138 COSTS_N_INSNS (1), /* fmov, fmovr */
139 COSTS_N_INSNS (1), /* fmul */
140 COSTS_N_INSNS (1), /* fdivs */
141 COSTS_N_INSNS (1), /* fdivd */
142 COSTS_N_INSNS (1), /* fsqrts */
143 COSTS_N_INSNS (1), /* fsqrtd */
144 COSTS_N_INSNS (5), /* imul */
145 COSTS_N_INSNS (5), /* imulX */
18df6de9 146 0, /* imul bit factor */
ffe384ff
DM		 147 COSTS_N_INSNS (5), /* idiv */
148 COSTS_N_INSNS (5), /* idivX */
149 COSTS_N_INSNS (1), /* movcc/movr */
18df6de9
DM		 150 0, /* shift penalty */
151};
152
153static const
154struct processor_costs ultrasparc_costs = {
ffe384ff
DM		 155 COSTS_N_INSNS (2), /* int load */
156 COSTS_N_INSNS (3), /* int signed load */
157 COSTS_N_INSNS (2), /* int zeroed load */
158 COSTS_N_INSNS (2), /* float load */
159 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
160 COSTS_N_INSNS (4), /* fadd, fsub */
161 COSTS_N_INSNS (1), /* fcmp */
162 COSTS_N_INSNS (2), /* fmov, fmovr */
163 COSTS_N_INSNS (4), /* fmul */
164 COSTS_N_INSNS (13), /* fdivs */
165 COSTS_N_INSNS (23), /* fdivd */
166 COSTS_N_INSNS (13), /* fsqrts */
167 COSTS_N_INSNS (23), /* fsqrtd */
168 COSTS_N_INSNS (4), /* imul */
169 COSTS_N_INSNS (4), /* imulX */
18df6de9 170 2, /* imul bit factor */
ffe384ff
DM		 171 COSTS_N_INSNS (37), /* idiv */
172 COSTS_N_INSNS (68), /* idivX */
173 COSTS_N_INSNS (2), /* movcc/movr */
18df6de9
DM		 174 2, /* shift penalty */
175};
176
177static const
178struct processor_costs ultrasparc3_costs = {
ffe384ff
DM		 179 COSTS_N_INSNS (2), /* int load */
180 COSTS_N_INSNS (3), /* int signed load */
181 COSTS_N_INSNS (3), /* int zeroed load */
182 COSTS_N_INSNS (2), /* float load */
183 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
184 COSTS_N_INSNS (4), /* fadd, fsub */
185 COSTS_N_INSNS (5), /* fcmp */
186 COSTS_N_INSNS (3), /* fmov, fmovr */
187 COSTS_N_INSNS (4), /* fmul */
188 COSTS_N_INSNS (17), /* fdivs */
189 COSTS_N_INSNS (20), /* fdivd */
190 COSTS_N_INSNS (20), /* fsqrts */
191 COSTS_N_INSNS (29), /* fsqrtd */
192 COSTS_N_INSNS (6), /* imul */
193 COSTS_N_INSNS (6), /* imulX */
18df6de9 194 0, /* imul bit factor */
ffe384ff
DM		 195 COSTS_N_INSNS (40), /* idiv */
196 COSTS_N_INSNS (71), /* idivX */
197 COSTS_N_INSNS (2), /* movcc/movr */
18df6de9
DM		 198 0, /* shift penalty */
199};
200
4c837a1e
DM		 201static const
202struct processor_costs niagara_costs = {
203 COSTS_N_INSNS (3), /* int load */
204 COSTS_N_INSNS (3), /* int signed load */
205 COSTS_N_INSNS (3), /* int zeroed load */
206 COSTS_N_INSNS (9), /* float load */
207 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
208 COSTS_N_INSNS (8), /* fadd, fsub */
209 COSTS_N_INSNS (26), /* fcmp */
210 COSTS_N_INSNS (8), /* fmov, fmovr */
211 COSTS_N_INSNS (29), /* fmul */
212 COSTS_N_INSNS (54), /* fdivs */
213 COSTS_N_INSNS (83), /* fdivd */
214 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
215 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
216 COSTS_N_INSNS (11), /* imul */
217 COSTS_N_INSNS (11), /* imulX */
218 0, /* imul bit factor */
219 COSTS_N_INSNS (72), /* idiv */
220 COSTS_N_INSNS (72), /* idivX */
221 COSTS_N_INSNS (1), /* movcc/movr */
222 0, /* shift penalty */
223};
224
9eeaed6e
DM		 225static const
226struct processor_costs niagara2_costs = {
227 COSTS_N_INSNS (3), /* int load */
228 COSTS_N_INSNS (3), /* int signed load */
229 COSTS_N_INSNS (3), /* int zeroed load */
230 COSTS_N_INSNS (3), /* float load */
231 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
232 COSTS_N_INSNS (6), /* fadd, fsub */
233 COSTS_N_INSNS (6), /* fcmp */
234 COSTS_N_INSNS (6), /* fmov, fmovr */
235 COSTS_N_INSNS (6), /* fmul */
236 COSTS_N_INSNS (19), /* fdivs */
237 COSTS_N_INSNS (33), /* fdivd */
238 COSTS_N_INSNS (19), /* fsqrts */
239 COSTS_N_INSNS (33), /* fsqrtd */
240 COSTS_N_INSNS (5), /* imul */
241 COSTS_N_INSNS (5), /* imulX */
242 0, /* imul bit factor */
243 COSTS_N_INSNS (31), /* idiv, average of 12 - 41 cycle range */
244 COSTS_N_INSNS (31), /* idivX, average of 12 - 41 cycle range */
245 COSTS_N_INSNS (1), /* movcc/movr */
246 0, /* shift penalty */
247};
248
18df6de9
DM		 249const struct processor_costs *sparc_costs = &cypress_costs;
250
9ac617d4
EB		 251#ifdef HAVE_AS_RELAX_OPTION
252/* If 'as' and 'ld' are relaxing tail call insns into branch always, use
253 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
254 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
255 somebody does not branch between the sethi and jmp. */
6244b14e 256#define LEAF_SIBCALL_SLOT_RESERVED_P 1
9ac617d4 257#else
6244b14e
EB		 258#define LEAF_SIBCALL_SLOT_RESERVED_P \
259 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
9ac617d4
EB		 260#endif
261
ab835497
RK		 262/* Global variables for machine-dependent things. */
263
61a55e8b 264/* Size of frame. Need to know this to emit return insns from leaf procedures.
9ac617d4
EB		 265 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
266 reload pass. This is important as the value is later used for scheduling
267 (to see what can go in a delay slot).
61a55e8b
DE		 268 APPARENT_FSIZE is the size of the stack less the register save area and less
269 the outgoing argument area. It is used when saving call preserved regs. */
6a151f87
EB		 270static HOST_WIDE_INT apparent_fsize;
271static HOST_WIDE_INT actual_fsize;
61a55e8b 272
33074e5f
RH		 273/* Number of live general or floating point registers needed to be
274 saved (as 4-byte quantities). */
e48addee
JJ		 275static int num_gfregs;
276
9ac617d4 277/* The alias set for prologue/epilogue register save/restore. */
4862826d 278static GTY(()) alias_set_type sparc_sr_alias_set;
9ac617d4 279
1da4c3a7 280/* The alias set for the structure return value. */
4862826d 281static GTY(()) alias_set_type struct_value_alias_set;
1da4c3a7 282
ab835497
RK		 283/* Save the operands last given to a compare for use when we
284 generate a scc or bcc insn. */
65c5ae8b 285rtx sparc_compare_op0, sparc_compare_op1;
ab835497 286
563c12b0
RH		 287/* Vector to say how input registers are mapped to output registers.
288 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
289 eliminate it. You must use -fomit-frame-pointer to get that. */
d70e94ec 290char leaf_reg_remap[] =
ab835497
RK		 291{ 0, 1, 2, 3, 4, 5, 6, 7,
292 -1, -1, -1, -1, -1, -1, 14, -1,
293 -1, -1, -1, -1, -1, -1, -1, -1,
294 8, 9, 10, 11, 12, 13, -1, 15,
295
296 32, 33, 34, 35, 36, 37, 38, 39,
297 40, 41, 42, 43, 44, 45, 46, 47,
298 48, 49, 50, 51, 52, 53, 54, 55,
61a55e8b
DE		 299 56, 57, 58, 59, 60, 61, 62, 63,
300 64, 65, 66, 67, 68, 69, 70, 71,
301 72, 73, 74, 75, 76, 77, 78, 79,
302 80, 81, 82, 83, 84, 85, 86, 87,
303 88, 89, 90, 91, 92, 93, 94, 95,
c4ce6853 304 96, 97, 98, 99, 100};
ab835497 305
7d167afd
JJ		 306/* Vector, indexed by hard register number, which contains 1
307 for a register that is allowable in a candidate for leaf
308 function treatment. */
309char sparc_leaf_regs[] =
310{ 1, 1, 1, 1, 1, 1, 1, 1,
311 0, 0, 0, 0, 0, 0, 1, 0,
312 0, 0, 0, 0, 0, 0, 0, 0,
313 1, 1, 1, 1, 1, 1, 0, 1,
314 1, 1, 1, 1, 1, 1, 1, 1,
315 1, 1, 1, 1, 1, 1, 1, 1,
316 1, 1, 1, 1, 1, 1, 1, 1,
317 1, 1, 1, 1, 1, 1, 1, 1,
318 1, 1, 1, 1, 1, 1, 1, 1,
319 1, 1, 1, 1, 1, 1, 1, 1,
320 1, 1, 1, 1, 1, 1, 1, 1,
321 1, 1, 1, 1, 1, 1, 1, 1,
322 1, 1, 1, 1, 1};
323
d1b38208 324struct GTY(()) machine_function
5751a10b
JJ		 325{
326 /* Some local-dynamic TLS symbol name. */
327 const char *some_ld_name;
5be9b7a1
EB		 328
329 /* True if the current function is leaf and uses only leaf regs,
330 so that the SPARC leaf function optimization can be applied.
331 Private version of current_function_uses_only_leaf_regs, see
332 sparc_expand_prologue for the rationale. */
333 int leaf_function_p;
334
335 /* True if the data calculated by sparc_expand_prologue are valid. */
336 bool prologue_data_valid_p;
5751a10b
JJ		 337};
338
5be9b7a1
EB		 339#define sparc_leaf_function_p cfun->machine->leaf_function_p
340#define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
341
9ac617d4
EB		 342/* Register we pretend to think the frame pointer is allocated to.
343 Normally, this is %fp, but if we are in a leaf procedure, this
344 is %sp+"something". We record "something" separately as it may
345 be too big for reg+constant addressing. */
9ac617d4 346static rtx frame_base_reg;
6a151f87 347static HOST_WIDE_INT frame_base_offset;
ab835497 348
4e5b002b
EB		 349/* 1 if the next opcode is to be specially indented. */
350int sparc_indent_opcode = 0;
351
fe609b0f 352static bool sparc_handle_option (size_t, const char *, int);
e80d5f80 353static void sparc_init_modes (void);
5c4f4b18 354static void scan_record_type (tree, int *, int *, int *);
e80d5f80
KG		 355static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
356 tree, int, int, int *, int *);
357
358static int supersparc_adjust_cost (rtx, rtx, rtx, int);
359static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
360
361static void sparc_output_addr_vec (rtx);
362static void sparc_output_addr_diff_vec (rtx);
363static void sparc_output_deferred_case_vectors (void);
3e2cc1d1 364static rtx sparc_builtin_saveregs (void);
e80d5f80
KG		 365static int epilogue_renumber (rtx *, int);
366static bool sparc_assemble_integer (rtx, unsigned int, int);
367static int set_extends (rtx);
5e77eb53
EB		 368static void emit_pic_helper (void);
369static void load_pic_register (bool);
9ac617d4 370static int save_or_restore_regs (int, int, rtx, int, int);
f8ece000 371static void emit_save_or_restore_regs (int);
9ac617d4
EB		 372static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
373static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
ede75ee8 374#ifdef OBJECT_FORMAT_ELF
c18a5b6c 375static void sparc_elf_asm_named_section (const char *, unsigned int, tree);
ede75ee8 376#endif
c237e94a 377
e80d5f80
KG		 378static int sparc_adjust_cost (rtx, rtx, rtx, int);
379static int sparc_issue_rate (void);
380static void sparc_sched_init (FILE *, int, int);
e80d5f80
KG		 381static int sparc_use_sched_lookahead (void);
382
383static void emit_soft_tfmode_libcall (const char *, int, rtx *);
384static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
385static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
386static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
387static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
388
389static bool sparc_function_ok_for_sibcall (tree, tree);
c15c90bb 390static void sparc_init_libfuncs (void);
16f59241
JM		 391static void sparc_init_builtins (void);
392static void sparc_vis_init_builtins (void);
393static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
8b0096b4
JM		 394static tree sparc_fold_builtin (tree, tree, bool);
395static int sparc_vis_mul8x16 (int, int);
396static tree sparc_handle_vis_mul8x16 (int, tree, tree, tree);
e80d5f80
KG		 397static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
398 HOST_WIDE_INT, tree);
3101faab
KG		 399static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,
400 HOST_WIDE_INT, const_tree);
5751a10b
JJ		 401static struct machine_function * sparc_init_machine_status (void);
402static bool sparc_cannot_force_const_mem (rtx);
403static rtx sparc_tls_get_addr (void);
404static rtx sparc_tls_got (void);
405static const char *get_some_local_dynamic_name (void);
406static int get_some_local_dynamic_name_1 (rtx *, void *);
f40751dd 407static bool sparc_rtx_costs (rtx, int, int, int *, bool);
586de218 408static bool sparc_promote_prototypes (const_tree);
3e2cc1d1 409static rtx sparc_struct_value_rtx (tree, int);
586de218 410static bool sparc_return_in_memory (const_tree, const_tree);
3e2cc1d1 411static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
d7bd8aeb 412static void sparc_va_start (tree, rtx);
726a989a 413static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
c75d6010 414static bool sparc_vector_mode_supported_p (enum machine_mode);
8cd5a4e0 415static bool sparc_pass_by_reference (CUMULATIVE_ARGS *,
586de218 416 enum machine_mode, const_tree, bool);
78a52f11
RH		 417static int sparc_arg_partial_bytes (CUMULATIVE_ARGS *,
418 enum machine_mode, tree, bool);
e54c7471 419static void sparc_dwarf_handle_frame_unspec (const char *, rtx, int);
fdbe66f2 420static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5e77eb53 421static void sparc_file_end (void);
7269aee7 422#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
3101faab 423static const char *sparc_mangle_type (const_tree);
7269aee7 424#endif
07a43492
DJ		 425#ifdef SUBTARGET_ATTRIBUTE_TABLE
426const struct attribute_spec sparc_attribute_table[];
427#endif
61a55e8b
DE		 428\f
429/* Option handling. */
430
a0a301fc
DE		 431/* Parsed value. */
432enum cmodel sparc_cmodel;
433
1cb36a98
RH		 434char sparc_hard_reg_printed[8];
435
16956f6e
DE		 436struct sparc_cpu_select sparc_select[] =
437{
438 /* switch name, tune arch */
439 { (char *)0, "default", 1, 1 },
440 { (char *)0, "-mcpu=", 1, 1 },
441 { (char *)0, "-mtune=", 1, 0 },
db3d4438 442 { 0, 0, 0, 0 }
16956f6e 443};
733f53f5 444
16956f6e
DE		 445/* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
446enum processor_type sparc_cpu;
fe609b0f
EB		 447
448/* Whether\fan FPU option was specified. */
449static bool fpu_option_set = false;
450
672a6f42 451/* Initialize the GCC target structure. */
301d03af
RS		 452
453/* The sparc default is to use .half rather than .short for aligned
454 HI objects. Use .word instead of .long on non-ELF systems. */
455#undef TARGET_ASM_ALIGNED_HI_OP
456#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
457#ifndef OBJECT_FORMAT_ELF
458#undef TARGET_ASM_ALIGNED_SI_OP
459#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
460#endif
461
462#undef TARGET_ASM_UNALIGNED_HI_OP
463#define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
464#undef TARGET_ASM_UNALIGNED_SI_OP
465#define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
466#undef TARGET_ASM_UNALIGNED_DI_OP
467#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
468
469/* The target hook has to handle DI-mode values. */
470#undef TARGET_ASM_INTEGER
471#define TARGET_ASM_INTEGER sparc_assemble_integer
472
08c148a8 473#undef TARGET_ASM_FUNCTION_PROLOGUE
9ac617d4 474#define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
08c148a8 475#undef TARGET_ASM_FUNCTION_EPILOGUE
9ac617d4 476#define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
733f53f5 477
c237e94a
ZW		 478#undef TARGET_SCHED_ADJUST_COST
479#define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
480#undef TARGET_SCHED_ISSUE_RATE
481#define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
c237e94a
ZW		 482#undef TARGET_SCHED_INIT
483#define TARGET_SCHED_INIT sparc_sched_init
fae15c93
VM		 484#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
485#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
c237e94a 486
4977bab6
ZW		 487#undef TARGET_FUNCTION_OK_FOR_SIBCALL
488#define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
489
c15c90bb
ZW		 490#undef TARGET_INIT_LIBFUNCS
491#define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
16f59241
JM		 492#undef TARGET_INIT_BUILTINS
493#define TARGET_INIT_BUILTINS sparc_init_builtins
494
495#undef TARGET_EXPAND_BUILTIN
496#define TARGET_EXPAND_BUILTIN sparc_expand_builtin
8b0096b4
JM		 497#undef TARGET_FOLD_BUILTIN
498#define TARGET_FOLD_BUILTIN sparc_fold_builtin
c15c90bb 499
fdbe66f2 500#if TARGET_TLS
5751a10b
JJ		 501#undef TARGET_HAVE_TLS
502#define TARGET_HAVE_TLS true
503#endif
fdbe66f2 504
5751a10b
JJ		 505#undef TARGET_CANNOT_FORCE_CONST_MEM
506#define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
507
c590b625
RH		 508#undef TARGET_ASM_OUTPUT_MI_THUNK
509#define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
3961e8fe 510#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
b9bf58e5 511#define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
c590b625 512
3c50106f
RH		 513#undef TARGET_RTX_COSTS
514#define TARGET_RTX_COSTS sparc_rtx_costs
dcefdf67 515#undef TARGET_ADDRESS_COST
f40751dd 516#define TARGET_ADDRESS_COST hook_int_rtx_bool_0
3c50106f 517
d4453b7a
PB		 518/* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
519 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
520 test for this value. */
3e2cc1d1 521#undef TARGET_PROMOTE_FUNCTION_ARGS
586de218 522#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
3e2cc1d1 523
d4453b7a
PB		 524/* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
525 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
526 test for this value. */
3e2cc1d1 527#undef TARGET_PROMOTE_FUNCTION_RETURN
586de218 528#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
3e2cc1d1
KH		 529
530#undef TARGET_PROMOTE_PROTOTYPES
531#define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
532
533#undef TARGET_STRUCT_VALUE_RTX
534#define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
535#undef TARGET_RETURN_IN_MEMORY
536#define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
fe984136
RH		 537#undef TARGET_MUST_PASS_IN_STACK
538#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
8cd5a4e0
RH		 539#undef TARGET_PASS_BY_REFERENCE
540#define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
78a52f11
RH		 541#undef TARGET_ARG_PARTIAL_BYTES
542#define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
3e2cc1d1
KH		 543
544#undef TARGET_EXPAND_BUILTIN_SAVEREGS
545#define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
546#undef TARGET_STRICT_ARGUMENT_NAMING
547#define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
548
d7bd8aeb
JJ		 549#undef TARGET_EXPAND_BUILTIN_VA_START
550#define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
5f393b25
JM		 551#undef TARGET_GIMPLIFY_VA_ARG_EXPR
552#define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
553
c75d6010
JM		 554#undef TARGET_VECTOR_MODE_SUPPORTED_P
555#define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
556
e54c7471
EB		 557#undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
558#define TARGET_DWARF_HANDLE_FRAME_UNSPEC sparc_dwarf_handle_frame_unspec
559
07a43492
DJ		 560#ifdef SUBTARGET_INSERT_ATTRIBUTES
561#undef TARGET_INSERT_ATTRIBUTES
562#define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
563#endif
564
565#ifdef SUBTARGET_ATTRIBUTE_TABLE
566#undef TARGET_ATTRIBUTE_TABLE
567#define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
568#endif
569
0e4e8dab 570#undef TARGET_RELAXED_ORDERING
548a6c4f 571#define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
445cf5eb 572
fe609b0f
EB		 573#undef TARGET_DEFAULT_TARGET_FLAGS
574#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
575#undef TARGET_HANDLE_OPTION
576#define TARGET_HANDLE_OPTION sparc_handle_option
577
f06fb22b 578#if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
fdbe66f2
EB		 579#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
580#define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
581#endif
582
c81739f7 583#undef TARGET_ASM_FILE_END
5e77eb53
EB		 584#define TARGET_ASM_FILE_END sparc_file_end
585
7269aee7 586#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
608063c3
JB		 587#undef TARGET_MANGLE_TYPE
588#define TARGET_MANGLE_TYPE sparc_mangle_type
7269aee7
AH		 589#endif
590
f6897b10 591struct gcc_target targetm = TARGET_INITIALIZER;
fe609b0f
EB		 592
593/* Implement TARGET_HANDLE_OPTION. */
594
595static bool
596sparc_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
597{
598 switch (code)
599 {
600 case OPT_mfpu:
601 case OPT_mhard_float:
602 case OPT_msoft_float:
603 fpu_option_set = true;
604 break;
605
606 case OPT_mcpu_:
607 sparc_select[1].string = arg;
608 break;
609
610 case OPT_mtune_:
611 sparc_select[2].string = arg;
612 break;
fe609b0f
EB		 613 }
614
615 return true;
616}
617
61a55e8b
DE		 618/* Validate and override various options, and do some machine dependent
619 initialization. */
620
621void
fc27d102 622sparc_override_options (void)
61a55e8b 623{
a0a301fc 624 static struct code_model {
8b60264b
KG		 625 const char *const name;
626 const int value;
627 } const cmodels[] = {
a0a301fc
DE		 628 { "32", CM_32 },
629 { "medlow", CM_MEDLOW },
630 { "medmid", CM_MEDMID },
631 { "medany", CM_MEDANY },
632 { "embmedany", CM_EMBMEDANY },
633 { 0, 0 }
634 };
8b60264b 635 const struct code_model *cmodel;
16956f6e 636 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
733f53f5 637 static struct cpu_default {
8b60264b
KG		 638 const int cpu;
639 const char *const name;
640 } const cpu_default[] = {
a0a301fc 641 /* There must be one entry here for each TARGET_CPU value. */
16956f6e 642 { TARGET_CPU_sparc, "cypress" },
3592ea0d 643 { TARGET_CPU_sparclet, "tsc701" },
16956f6e 644 { TARGET_CPU_sparclite, "f930" },
a0a301fc 645 { TARGET_CPU_v8, "v8" },
8947065c
RH		 646 { TARGET_CPU_hypersparc, "hypersparc" },
647 { TARGET_CPU_sparclite86x, "sparclite86x" },
a0a301fc
DE		 648 { TARGET_CPU_supersparc, "supersparc" },
649 { TARGET_CPU_v9, "v9" },
ba542005 650 { TARGET_CPU_ultrasparc, "ultrasparc" },
fae15c93 651 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
4c837a1e 652 { TARGET_CPU_niagara, "niagara" },
9eeaed6e 653 { TARGET_CPU_niagara2, "niagara2" },
db3d4438 654 { 0, 0 }
733f53f5 655 };
8b60264b 656 const struct cpu_default *def;
16956f6e 657 /* Table of values for -m{cpu,tune}=. */
733f53f5 658 static struct cpu_table {
8b60264b
KG		 659 const char *const name;
660 const enum processor_type processor;
661 const int disable;
662 const int enable;
663 } const cpu_table[] = {
16956f6e
DE		 664 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
665 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
666 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
733f53f5 667 /* TI TMS390Z55 supersparc */
16956f6e
DE		 668 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
669 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
733f53f5
DE		 670 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
671 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
16956f6e
DE		 672 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
673 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
8947065c 674 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
d3ec6b06
VM		 675 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
676 MASK_SPARCLITE },
16956f6e 677 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
733f53f5 678 /* TEMIC sparclet */
3592ea0d 679 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
16956f6e 680 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
5cb01b65
JJ		 681 /* TI ultrasparc I, II, IIi */
682 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
683 /* Although insns using %y are deprecated, it is a clear win on current
80ffc95e 684 ultrasparcs. */
3276910d 685 |MASK_DEPRECATED_V8_INSNS},
fae15c93
VM		 686 /* TI ultrasparc III */
687 /* ??? Check if %y issue still holds true in ultra3. */
688 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
4c837a1e
DM		 689 /* UltraSPARC T1 */
690 { "niagara", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
9eeaed6e 691 { "niagara2", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9},
db3d4438 692 { 0, 0, 0, 0 }
733f53f5 693 };
8b60264b
KG		 694 const struct cpu_table *cpu;
695 const struct sparc_cpu_select *sel;
a0a301fc 696 int fpu;
345a6161 697
a0a301fc
DE		 698#ifndef SPARC_BI_ARCH
699 /* Check for unsupported architecture size. */
700 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
3276910d
RK		 701 error ("%s is not supported by this configuration",
702 DEFAULT_ARCH32_P ? "-m64" : "-m32");
a0a301fc
DE		 703#endif
704
4710d3eb
JJ		 705 /* We force all 64bit archs to use 128 bit long double */
706 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
707 {
708 error ("-mlong-double-64 not allowed with -m64");
709 target_flags |= MASK_LONG_DOUBLE_128;
710 }
711
a0a301fc
DE		 712 /* Code model selection. */
713 sparc_cmodel = SPARC_DEFAULT_CMODEL;
345a6161
DM		 714
715#ifdef SPARC_BI_ARCH
716 if (TARGET_ARCH32)
717 sparc_cmodel = CM_32;
718#endif
719
a0a301fc
DE		 720 if (sparc_cmodel_string != NULL)
721 {
722 if (TARGET_ARCH64)
723 {
724 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
725 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
726 break;
727 if (cmodel->name == NULL)
728 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
729 else
730 sparc_cmodel = cmodel->value;
731 }
732 else
733 error ("-mcmodel= is not supported on 32 bit systems");
734 }
16956f6e 735
06063fa2 736 fpu = target_flags & MASK_FPU; /* save current -mfpu status */
1f1406b4 737
a0a301fc 738 /* Set the default CPU. */
16956f6e
DE		 739 for (def = &cpu_default[0]; def->name; ++def)
740 if (def->cpu == TARGET_CPU_DEFAULT)
741 break;
f5f7d171 742 gcc_assert (def->name);
16956f6e
DE		 743 sparc_select[0].string = def->name;
744
745 for (sel = &sparc_select[0]; sel->name; ++sel)
61a55e8b 746 {
16956f6e 747 if (sel->string)
733f53f5 748 {
16956f6e
DE		 749 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
750 if (! strcmp (sel->string, cpu->name))
751 {
752 if (sel->set_tune_p)
753 sparc_cpu = cpu->processor;
754
755 if (sel->set_arch_p)
756 {
757 target_flags &= ~cpu->disable;
758 target_flags |= cpu->enable;
759 }
760 break;
761 }
762
763 if (! cpu->name)
764 error ("bad value (%s) for %s switch", sel->string, sel->name);
733f53f5 765 }
61a55e8b 766 }
97da85b7 767
1f1406b4 768 /* If -mfpu or -mno-fpu was explicitly used, don't override with
fe609b0f
EB		 769 the processor default. */
770 if (fpu_option_set)
771 target_flags = (target_flags & ~MASK_FPU) | fpu;
1f1406b4 772
a5774a7d
JJ		 773 /* Don't allow -mvis if FPU is disabled. */
774 if (! TARGET_FPU)
775 target_flags &= ~MASK_VIS;
776
777 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
778 are available.
779 -m64 also implies v9. */
780 if (TARGET_VIS || TARGET_ARCH64)
c4031a04
JJ		 781 {
782 target_flags |= MASK_V9;
783 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
784 }
a5774a7d 785
16956f6e
DE		 786 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
787 if (TARGET_V9 && TARGET_ARCH32)
733f53f5 788 target_flags |= MASK_DEPRECATED_V8_INSNS;
61a55e8b 789
345a6161
DM		 790 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
791 if (! TARGET_V9 || TARGET_ARCH64)
284d86e9
JC		 792 target_flags &= ~MASK_V8PLUS;
793
82d6b402
RH		 794 /* Don't use stack biasing in 32 bit mode. */
795 if (TARGET_ARCH32)
796 target_flags &= ~MASK_STACK_BIAS;
f952a238 797
efa3896a 798 /* Supply a default value for align_functions. */
fae15c93
VM		 799 if (align_functions == 0
800 && (sparc_cpu == PROCESSOR_ULTRASPARC
4c837a1e 801 || sparc_cpu == PROCESSOR_ULTRASPARC3
9eeaed6e
DM		 802 || sparc_cpu == PROCESSOR_NIAGARA
803 || sparc_cpu == PROCESSOR_NIAGARA2))
efa3896a 804 align_functions = 32;
bf62bbf1 805
82d6b402
RH		 806 /* Validate PCC_STRUCT_RETURN. */
807 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
808 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
809
301d03af
RS		 810 /* Only use .uaxword when compiling for a 64-bit target. */
811 if (!TARGET_ARCH64)
812 targetm.asm_out.unaligned_op.di = NULL;
813
61a55e8b
DE		 814 /* Do various machine dependent initializations. */
815 sparc_init_modes ();
5751a10b 816
1da4c3a7 817 /* Acquire unique alias sets for our private stuff. */
9ac617d4 818 sparc_sr_alias_set = new_alias_set ();
1da4c3a7 819 struct_value_alias_set = new_alias_set ();
9ac617d4 820
5751a10b
JJ		 821 /* Set up function hooks. */
822 init_machine_status = sparc_init_machine_status;
18df6de9
DM		 823
824 switch (sparc_cpu)
825 {
826 case PROCESSOR_V7:
827 case PROCESSOR_CYPRESS:
828 sparc_costs = &cypress_costs;
829 break;
830 case PROCESSOR_V8:
831 case PROCESSOR_SPARCLITE:
832 case PROCESSOR_SUPERSPARC:
833 sparc_costs = &supersparc_costs;
834 break;
835 case PROCESSOR_F930:
836 case PROCESSOR_F934:
837 case PROCESSOR_HYPERSPARC:
838 case PROCESSOR_SPARCLITE86X:
839 sparc_costs = &hypersparc_costs;
840 break;
841 case PROCESSOR_SPARCLET:
842 case PROCESSOR_TSC701:
843 sparc_costs = &sparclet_costs;
844 break;
845 case PROCESSOR_V9:
846 case PROCESSOR_ULTRASPARC:
847 sparc_costs = &ultrasparc_costs;
848 break;
849 case PROCESSOR_ULTRASPARC3:
850 sparc_costs = &ultrasparc3_costs;
851 break;
4c837a1e
DM		 852 case PROCESSOR_NIAGARA:
853 sparc_costs = &niagara_costs;
854 break;
9eeaed6e
DM		 855 case PROCESSOR_NIAGARA2:
856 sparc_costs = &niagara2_costs;
857 break;
18df6de9 858 };
ed965309
JJ		 859
860#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
861 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
862 target_flags |= MASK_LONG_DOUBLE_128;
863#endif
47eb5b32
ZD		 864
865 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
866 set_param_value ("simultaneous-prefetches",
867 ((sparc_cpu == PROCESSOR_ULTRASPARC
9eeaed6e
DM		 868 || sparc_cpu == PROCESSOR_NIAGARA
869 || sparc_cpu == PROCESSOR_NIAGARA2)
47eb5b32
ZD		 870 ? 2
871 : (sparc_cpu == PROCESSOR_ULTRASPARC3
872 ? 8 : 3)));
873 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
874 set_param_value ("l1-cache-line-size",
875 ((sparc_cpu == PROCESSOR_ULTRASPARC
876 || sparc_cpu == PROCESSOR_ULTRASPARC3
9eeaed6e
DM		 877 || sparc_cpu == PROCESSOR_NIAGARA
878 || sparc_cpu == PROCESSOR_NIAGARA2)
47eb5b32 879 ? 64 : 32));
61a55e8b
DE		 880}
881\f
07a43492
DJ		 882#ifdef SUBTARGET_ATTRIBUTE_TABLE
883/* Table of valid machine attributes. */
884const struct attribute_spec sparc_attribute_table[] =
885{
886 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
887 SUBTARGET_ATTRIBUTE_TABLE,
888 { NULL, 0, 0, false, false, false, NULL }
889};
890#endif
891\f
cd5fb1ee
DE		 892/* Miscellaneous utilities. */
893
894/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
895 or branch on register contents instructions. */
896
897int
fc27d102 898v9_regcmp_p (enum rtx_code code)
cd5fb1ee
DE		 899{
900 return (code == EQ || code == NE || code == GE || code == LT
901 || code == LE || code == GT);
902}
bfd6bc60 903
62190128
DM		 904/* Nonzero if OP is a floating point constant which can
905 be loaded into an integer register using a single
906 sethi instruction. */
907
908int
fc27d102 909fp_sethi_p (rtx op)
62190128
DM		 910{
911 if (GET_CODE (op) == CONST_DOUBLE)
912 {
913 REAL_VALUE_TYPE r;
914 long i;
915
916 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
62190128 917 REAL_VALUE_TO_TARGET_SINGLE (r, i);
9a9e266b 918 return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i);
62190128
DM		 919 }
920
921 return 0;
922}
923
924/* Nonzero if OP is a floating point constant which can
925 be loaded into an integer register using a single
926 mov instruction. */
927
928int
fc27d102 929fp_mov_p (rtx op)
62190128
DM		 930{
931 if (GET_CODE (op) == CONST_DOUBLE)
932 {
933 REAL_VALUE_TYPE r;
934 long i;
935
936 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
62190128 937 REAL_VALUE_TO_TARGET_SINGLE (r, i);
9a9e266b 938 return SPARC_SIMM13_P (i);
62190128
DM		 939 }
940
941 return 0;
942}
943
944/* Nonzero if OP is a floating point constant which can
945 be loaded into an integer register using a high/losum
946 instruction sequence. */
947
948int
fc27d102 949fp_high_losum_p (rtx op)
62190128
DM		 950{
951 /* The constraints calling this should only be in
952 SFmode move insns, so any constant which cannot
953 be moved using a single insn will do. */
954 if (GET_CODE (op) == CONST_DOUBLE)
955 {
956 REAL_VALUE_TYPE r;
957 long i;
958
959 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
62190128 960 REAL_VALUE_TO_TARGET_SINGLE (r, i);
9a9e266b 961 return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i);
62190128
DM		 962 }
963
964 return 0;
965}
966
bea5071f
EB		 967/* Expand a move instruction. Return true if all work is done. */
968
969bool
970sparc_expand_move (enum machine_mode mode, rtx *operands)
971{
972 /* Handle sets of MEM first. */
973 if (GET_CODE (operands[0]) == MEM)
974 {
975 /* 0 is a register (or a pair of registers) on SPARC. */
976 if (register_or_zero_operand (operands[1], mode))
977 return false;
978
979 if (!reload_in_progress)
980 {
981 operands[0] = validize_mem (operands[0]);
982 operands[1] = force_reg (mode, operands[1]);
983 }
984 }
985
986 /* Fixup TLS cases. */
38fc66ba
EB		 987 if (TARGET_HAVE_TLS
988 && CONSTANT_P (operands[1])
989 && GET_CODE (operands[1]) != HIGH
990 && sparc_tls_referenced_p (operands [1]))
991 {
992 rtx sym = operands[1];
993 rtx addend = NULL;
bea5071f 994
38fc66ba
EB		 995 if (GET_CODE (sym) == CONST && GET_CODE (XEXP (sym, 0)) == PLUS)
996 {
997 addend = XEXP (XEXP (sym, 0), 1);
998 sym = XEXP (XEXP (sym, 0), 0);
999 }
1000
1001 gcc_assert (SPARC_SYMBOL_REF_TLS_P (sym));
1002
1003 sym = legitimize_tls_address (sym);
1004 if (addend)
1005 {
1006 sym = gen_rtx_PLUS (mode, sym, addend);
1007 sym = force_operand (sym, operands[0]);
1008 }
1009 operands[1] = sym;
1010 }
1011
bea5071f
EB		 1012 /* Fixup PIC cases. */
1013 if (flag_pic && CONSTANT_P (operands[1]))
1014 {
1015 if (pic_address_needs_scratch (operands[1]))
1016 operands[1] = legitimize_pic_address (operands[1], mode, 0);
1017
1910440e
RS		 1018 /* VxWorks does not impose a fixed gap between segments; the run-time
1019 gap can be different from the object-file gap. We therefore can't
1020 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1021 are absolutely sure that X is in the same segment as the GOT.
1022 Unfortunately, the flexibility of linker scripts means that we
1023 can't be sure of that in general, so assume that _G_O_T_-relative
1024 accesses are never valid on VxWorks. */
1025 if (GET_CODE (operands[1]) == LABEL_REF && !TARGET_VXWORKS_RTP)
bea5071f 1026 {
1910440e
RS		 1027 if (mode == SImode)
1028 {
1029 emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
1030 return true;
1031 }
bea5071f 1032
1910440e
RS		 1033 if (mode == DImode)
1034 {
1035 gcc_assert (TARGET_ARCH64);
1036 emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
1037 return true;
1038 }
bea5071f
EB		 1039 }
1040
1041 if (symbolic_operand (operands[1], mode))
1042 {
1043 operands[1] = legitimize_pic_address (operands[1],
1044 mode,
1045 (reload_in_progress ?
1046 operands[0] :
1047 NULL_RTX));
1048 return false;
1049 }
1050 }
1051
1052 /* If we are trying to toss an integer constant into FP registers,
1053 or loading a FP or vector constant, force it into memory. */
1054 if (CONSTANT_P (operands[1])
1055 && REG_P (operands[0])
1056 && (SPARC_FP_REG_P (REGNO (operands[0]))
1057 || SCALAR_FLOAT_MODE_P (mode)
1058 || VECTOR_MODE_P (mode)))
1059 {
1060 /* emit_group_store will send such bogosity to us when it is
1061 not storing directly into memory. So fix this up to avoid
1062 crashes in output_constant_pool. */
1063 if (operands [1] == const0_rtx)
1064 operands[1] = CONST0_RTX (mode);
1065
1066 /* We can clear FP registers if TARGET_VIS, and always other regs. */
1067 if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
1068 && const_zero_operand (operands[1], mode))
1069 return false;
1070
1071 if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
1072 /* We are able to build any SF constant in integer registers
1073 with at most 2 instructions. */
1074 && (mode == SFmode
1075 /* And any DF constant in integer registers. */
1076 || (mode == DFmode
1077 && (reload_completed || reload_in_progress))))
1078 return false;
1079
1080 operands[1] = force_const_mem (mode, operands[1]);
1081 if (!reload_in_progress)
1082 operands[1] = validize_mem (operands[1]);
1083 return false;
1084 }
1085
1086 /* Accept non-constants and valid constants unmodified. */
1087 if (!CONSTANT_P (operands[1])
1088 || GET_CODE (operands[1]) == HIGH
1089 || input_operand (operands[1], mode))
1090 return false;
1091
1092 switch (mode)
1093 {
1094 case QImode:
1095 /* All QImode constants require only one insn, so proceed. */
1096 break;
1097
1098 case HImode:
1099 case SImode:
1100 sparc_emit_set_const32 (operands[0], operands[1]);
1101 return true;
1102
1103 case DImode:
1104 /* input_operand should have filtered out 32-bit mode. */
1105 sparc_emit_set_const64 (operands[0], operands[1]);
1106 return true;
1107
1108 default:
1109 gcc_unreachable ();
1110 }
1111
1112 return false;
1113}
1114
1115/* Load OP1, a 32-bit constant, into OP0, a register.
1116 We know it can't be done in one insn when we get
1117 here, the move expander guarantees this. */
1118
e0d80184 1119void
fc27d102 1120sparc_emit_set_const32 (rtx op0, rtx op1)
e0d80184
DM		 1121{
1122 enum machine_mode mode = GET_MODE (op0);
1123 rtx temp;
1124
e0d80184
DM		 1125 if (reload_in_progress || reload_completed)
1126 temp = op0;
284d86e9 1127 else
e0d80184
DM		 1128 temp = gen_reg_rtx (mode);
1129
71648202
DM		 1130 if (GET_CODE (op1) == CONST_INT)
1131 {
0e5d569c
EB		 1132 gcc_assert (!small_int_operand (op1, mode)
1133 && !const_high_operand (op1, mode));
1134
71648202
DM		 1135 /* Emit them as real moves instead of a HIGH/LO_SUM,
1136 this way CSE can see everything and reuse intermediate
1137 values if it wants. */
0e5d569c
EB		 1138 emit_insn (gen_rtx_SET (VOIDmode, temp,
1139 GEN_INT (INTVAL (op1)
1140 & ~(HOST_WIDE_INT)0x3ff)));
f2827474 1141
71648202
DM		 1142 emit_insn (gen_rtx_SET (VOIDmode,
1143 op0,
f2827474 1144 gen_rtx_IOR (mode, temp,
71648202
DM		 1145 GEN_INT (INTVAL (op1) & 0x3ff))));
1146 }
1147 else
1148 {
1149 /* A symbol, emit in the traditional way. */
f2827474
RK		 1150 emit_insn (gen_rtx_SET (VOIDmode, temp,
1151 gen_rtx_HIGH (mode, op1)));
71648202 1152 emit_insn (gen_rtx_SET (VOIDmode,
f2827474 1153 op0, gen_rtx_LO_SUM (mode, temp, op1)));
71648202 1154 }
e0d80184
DM		 1155}
1156
1d511ed5 1157/* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
0e40b5f2 1158 If TEMP is nonzero, we are forbidden to use any other scratch
1d511ed5
EB		 1159 registers. Otherwise, we are allowed to generate them as needed.
1160
1161 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1162 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
bea5071f 1163
e0d80184 1164void
1d511ed5 1165sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
e0d80184 1166{
1d511ed5
EB		 1167 rtx temp1, temp2, temp3, temp4, temp5;
1168 rtx ti_temp = 0;
3968de80 1169
1d511ed5 1170 if (temp && GET_MODE (temp) == TImode)
3968de80 1171 {
1d511ed5
EB		 1172 ti_temp = temp;
1173 temp = gen_rtx_REG (DImode, REGNO (temp));
3968de80
DD		 1174 }
1175
1d511ed5 1176 /* SPARC-V9 code-model support. */
e0d80184 1177 switch (sparc_cmodel)
284d86e9 1178 {
e0d80184
DM		 1179 case CM_MEDLOW:
1180 /* The range spanned by all instructions in the object is less
1181 than 2^31 bytes (2GB) and the distance from any instruction
1182 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1183 than 2^31 bytes (2GB).
ab835497 1184
e0d80184
DM		 1185 The executable must be in the low 4TB of the virtual address
1186 space.
61a55e8b 1187
1d511ed5
EB		 1188 sethi %hi(symbol), %temp1
1189 or %temp1, %lo(symbol), %reg */
1190 if (temp)
1191 temp1 = temp; /* op0 is allowed. */
1192 else
1193 temp1 = gen_reg_rtx (DImode);
1194
9208e4b2
DM		 1195 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1196 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
e0d80184 1197 break;
61a55e8b 1198
e0d80184
DM		 1199 case CM_MEDMID:
1200 /* The range spanned by all instructions in the object is less
1201 than 2^31 bytes (2GB) and the distance from any instruction
1202 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1203 than 2^31 bytes (2GB).
1204
1205 The executable must be in the low 16TB of the virtual address
1206 space.
1207
1208 sethi %h44(symbol), %temp1
1209 or %temp1, %m44(symbol), %temp2
1210 sllx %temp2, 12, %temp3
1211 or %temp3, %l44(symbol), %reg */
1d511ed5
EB		 1212 if (temp)
1213 {
1214 temp1 = op0;
1215 temp2 = op0;
1216 temp3 = temp; /* op0 is allowed. */
1217 }
1218 else
1219 {
1220 temp1 = gen_reg_rtx (DImode);
1221 temp2 = gen_reg_rtx (DImode);
1222 temp3 = gen_reg_rtx (DImode);
1223 }
1224
1225 emit_insn (gen_seth44 (temp1, op1));
1226 emit_insn (gen_setm44 (temp2, temp1, op1));
1227 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1228 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1229 emit_insn (gen_setl44 (op0, temp3, op1));
e0d80184 1230 break;
61a55e8b 1231
e0d80184
DM		 1232 case CM_MEDANY:
1233 /* The range spanned by all instructions in the object is less
1234 than 2^31 bytes (2GB) and the distance from any instruction
1235 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1236 than 2^31 bytes (2GB).
1237
1238 The executable can be placed anywhere in the virtual address
1239 space.
1240
1241 sethi %hh(symbol), %temp1
1242 sethi %lm(symbol), %temp2
1243 or %temp1, %hm(symbol), %temp3
1d511ed5
EB		 1244 sllx %temp3, 32, %temp4
1245 or %temp4, %temp2, %temp5
1246 or %temp5, %lo(symbol), %reg */
1247 if (temp)
3968de80 1248 {
1d511ed5
EB		 1249 /* It is possible that one of the registers we got for operands[2]
1250 might coincide with that of operands[0] (which is why we made
1251 it TImode). Pick the other one to use as our scratch. */
1252 if (rtx_equal_p (temp, op0))
1253 {
f5f7d171
JM		 1254 gcc_assert (ti_temp);
1255 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1d511ed5
EB		 1256 }
1257 temp1 = op0;
1258 temp2 = temp; /* op0 is _not_ allowed, see above. */
1259 temp3 = op0;
1260 temp4 = op0;
1261 temp5 = op0;
1262 }
1263 else
1264 {
1265 temp1 = gen_reg_rtx (DImode);
1266 temp2 = gen_reg_rtx (DImode);
1267 temp3 = gen_reg_rtx (DImode);
1268 temp4 = gen_reg_rtx (DImode);
1269 temp5 = gen_reg_rtx (DImode);
3968de80 1270 }
61a55e8b 1271
1d511ed5
EB		 1272 emit_insn (gen_sethh (temp1, op1));
1273 emit_insn (gen_setlm (temp2, op1));
1274 emit_insn (gen_sethm (temp3, temp1, op1));
1275 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1276 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1277 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1278 gen_rtx_PLUS (DImode, temp4, temp2)));
1279 emit_insn (gen_setlo (op0, temp5, op1));
e0d80184 1280 break;
61a55e8b 1281
e0d80184
DM		 1282 case CM_EMBMEDANY:
1283 /* Old old old backwards compatibility kruft here.
1284 Essentially it is MEDLOW with a fixed 64-bit
1285 virtual base added to all data segment addresses.
1286 Text-segment stuff is computed like MEDANY, we can't
1287 reuse the code above because the relocation knobs
1288 look different.
1289
1290 Data segment: sethi %hi(symbol), %temp1
1d511ed5
EB		 1291 add %temp1, EMBMEDANY_BASE_REG, %temp2
1292 or %temp2, %lo(symbol), %reg */
e0d80184
DM		 1293 if (data_segment_operand (op1, GET_MODE (op1)))
1294 {
1d511ed5
EB		 1295 if (temp)
1296 {
1297 temp1 = temp; /* op0 is allowed. */
1298 temp2 = op0;
1299 }
1300 else
1301 {
1302 temp1 = gen_reg_rtx (DImode);
1303 temp2 = gen_reg_rtx (DImode);
1304 }
1305
e0d80184 1306 emit_insn (gen_embmedany_sethi (temp1, op1));
1d511ed5
EB		 1307 emit_insn (gen_embmedany_brsum (temp2, temp1));
1308 emit_insn (gen_embmedany_losum (op0, temp2, op1));
e0d80184 1309 }
1d511ed5
EB		 1310
1311 /* Text segment: sethi %uhi(symbol), %temp1
1312 sethi %hi(symbol), %temp2
1313 or %temp1, %ulo(symbol), %temp3
1314 sllx %temp3, 32, %temp4
1315 or %temp4, %temp2, %temp5
1316 or %temp5, %lo(symbol), %reg */
e0d80184
DM		 1317 else
1318 {
1d511ed5 1319 if (temp)
3968de80 1320 {
1d511ed5
EB		 1321 /* It is possible that one of the registers we got for operands[2]
1322 might coincide with that of operands[0] (which is why we made
1323 it TImode). Pick the other one to use as our scratch. */
1324 if (rtx_equal_p (temp, op0))
1325 {
f5f7d171
JM		 1326 gcc_assert (ti_temp);
1327 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1d511ed5
EB		 1328 }
1329 temp1 = op0;
1330 temp2 = temp; /* op0 is _not_ allowed, see above. */
1331 temp3 = op0;
1332 temp4 = op0;
1333 temp5 = op0;
1334 }
1335 else
1336 {
1337 temp1 = gen_reg_rtx (DImode);
1338 temp2 = gen_reg_rtx (DImode);
1339 temp3 = gen_reg_rtx (DImode);
1340 temp4 = gen_reg_rtx (DImode);
1341 temp5 = gen_reg_rtx (DImode);
3968de80 1342 }
61a55e8b 1343
1d511ed5
EB		 1344 emit_insn (gen_embmedany_textuhi (temp1, op1));
1345 emit_insn (gen_embmedany_texthi (temp2, op1));
1346 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1347 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1348 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1349 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1350 gen_rtx_PLUS (DImode, temp4, temp2)));
1351 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
e0d80184
DM		 1352 }
1353 break;
1354
1355 default:
f5f7d171 1356 gcc_unreachable ();
e0d80184
DM		 1357 }
1358}
1359
0e5d569c
EB		 1360#if HOST_BITS_PER_WIDE_INT == 32
1361void
1362sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED)
1363{
1364 gcc_unreachable ();
1365}
1366#else
9208e4b2
DM		 1367/* These avoid problems when cross compiling. If we do not
1368 go through all this hair then the optimizer will see
1369 invalid REG_EQUAL notes or in some cases none at all. */
9bb3323d 1370static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT);
e80d5f80
KG		 1371static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1372static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1373static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
9208e4b2 1374
9208e4b2
DM		 1375/* The optimizer is not to assume anything about exactly
1376 which bits are set for a HIGH, they are unspecified.
1377 Unfortunately this leads to many missed optimizations
1378 during CSE. We mask out the non-HIGH bits, and matches
1379 a plain movdi, to alleviate this problem. */
9bb3323d
EB		 1380static rtx
1381gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
9208e4b2 1382{
9bb3323d 1383 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff));
9208e4b2 1384}
2a01c939 1385
e0d80184 1386static rtx
fc27d102 1387gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
61a55e8b 1388{
0e5d569c 1389 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val));
9208e4b2
DM		 1390}
1391
1392static rtx
fc27d102 1393gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
9208e4b2 1394{
0e5d569c 1395 return gen_rtx_IOR (DImode, src, GEN_INT (val));
9208e4b2
DM		 1396}
1397
1398static rtx
fc27d102 1399gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
9208e4b2 1400{
0e5d569c 1401 return gen_rtx_XOR (DImode, src, GEN_INT (val));
e0d80184 1402}
61a55e8b 1403
e0d80184
DM		 1404/* Worker routines for 64-bit constant formation on arch64.
1405 One of the key things to be doing in these emissions is
1406 to create as many temp REGs as possible. This makes it
1407 possible for half-built constants to be used later when
1408 such values are similar to something required later on.
1409 Without doing this, the optimizer cannot see such
1410 opportunities. */
2a01c939 1411
e80d5f80
KG		 1412static void sparc_emit_set_const64_quick1 (rtx, rtx,
1413 unsigned HOST_WIDE_INT, int);
2a01c939 1414
e0d80184 1415static void
fc27d102
KG		 1416sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1417 unsigned HOST_WIDE_INT low_bits, int is_neg)
e0d80184 1418{
2a01c939 1419 unsigned HOST_WIDE_INT high_bits;
a9e27770 1420
e0d80184 1421 if (is_neg)
2a01c939 1422 high_bits = (~low_bits) & 0xffffffff;
31bc9eba 1423 else
e0d80184 1424 high_bits = low_bits;
31bc9eba 1425
9bb3323d 1426 emit_insn (gen_safe_HIGH64 (temp, high_bits));
e0d80184 1427 if (!is_neg)
5108f3e5
DM		 1428 {
1429 emit_insn (gen_rtx_SET (VOIDmode, op0,
1430 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1431 }
e0d80184 1432 else
5108f3e5
DM		 1433 {
1434 /* If we are XOR'ing with -1, then we should emit a one's complement
1435 instead. This way the combiner will notice logical operations
1436 such as ANDN later on and substitute. */
1437 if ((low_bits & 0x3ff) == 0x3ff)
1438 {
1439 emit_insn (gen_rtx_SET (VOIDmode, op0,
1440 gen_rtx_NOT (DImode, temp)));
1441 }
1442 else
1443 {
1444 emit_insn (gen_rtx_SET (VOIDmode, op0,
1445 gen_safe_XOR64 (temp,
9e0625a3
AO		 1446 (-(HOST_WIDE_INT)0x400
1447 | (low_bits & 0x3ff)))));
5108f3e5
DM		 1448 }
1449 }
e0d80184 1450}
61a55e8b 1451
e80d5f80
KG		 1452static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1453 unsigned HOST_WIDE_INT, int);
2a01c939 1454
e0d80184 1455static void
fc27d102
KG		 1456sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1457 unsigned HOST_WIDE_INT high_bits,
1458 unsigned HOST_WIDE_INT low_immediate,
1459 int shift_count)
e0d80184
DM		 1460{
1461 rtx temp2 = op0;
61a55e8b 1462
e0d80184
DM		 1463 if ((high_bits & 0xfffffc00) != 0)
1464 {
9bb3323d 1465 emit_insn (gen_safe_HIGH64 (temp, high_bits));
e0d80184 1466 if ((high_bits & ~0xfffffc00) != 0)
9208e4b2
DM		 1467 emit_insn (gen_rtx_SET (VOIDmode, op0,
1468 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
61a55e8b 1469 else
e0d80184 1470 temp2 = temp;
61a55e8b
DE		 1471 }
1472 else
1473 {
f710f868 1474 emit_insn (gen_safe_SET64 (temp, high_bits));
e0d80184
DM		 1475 temp2 = temp;
1476 }
61a55e8b 1477
80ffc95e 1478 /* Now shift it up into place. */
9208e4b2 1479 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1480 gen_rtx_ASHIFT (DImode, temp2,
1481 GEN_INT (shift_count))));
61a55e8b 1482
e0d80184
DM		 1483 /* If there is a low immediate part piece, finish up by
1484 putting that in as well. */
1485 if (low_immediate != 0)
9208e4b2
DM		 1486 emit_insn (gen_rtx_SET (VOIDmode, op0,
1487 gen_safe_OR64 (op0, low_immediate)));
ab835497
RK		 1488}
1489
e80d5f80
KG		 1490static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1491 unsigned HOST_WIDE_INT);
2a01c939 1492
e0d80184
DM		 1493/* Full 64-bit constant decomposition. Even though this is the
1494 'worst' case, we still optimize a few things away. */
1495static void
fc27d102
KG		 1496sparc_emit_set_const64_longway (rtx op0, rtx temp,
1497 unsigned HOST_WIDE_INT high_bits,
1498 unsigned HOST_WIDE_INT low_bits)
ab835497 1499{
e0d80184 1500 rtx sub_temp;
4bf7135b 1501
e0d80184
DM		 1502 if (reload_in_progress || reload_completed)
1503 sub_temp = op0;
1504 else
1505 sub_temp = gen_reg_rtx (DImode);
1506
1507 if ((high_bits & 0xfffffc00) != 0)
1508 {
9bb3323d 1509 emit_insn (gen_safe_HIGH64 (temp, high_bits));
e0d80184 1510 if ((high_bits & ~0xfffffc00) != 0)
9208e4b2 1511 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1512 sub_temp,
9208e4b2 1513 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
e0d80184
DM		 1514 else
1515 sub_temp = temp;
1516 }
1517 else
ab835497 1518 {
f710f868 1519 emit_insn (gen_safe_SET64 (temp, high_bits));
e0d80184 1520 sub_temp = temp;
ab835497 1521 }
4bf7135b 1522
e0d80184 1523 if (!reload_in_progress && !reload_completed)
284d86e9 1524 {
e0d80184
DM		 1525 rtx temp2 = gen_reg_rtx (DImode);
1526 rtx temp3 = gen_reg_rtx (DImode);
1527 rtx temp4 = gen_reg_rtx (DImode);
284d86e9 1528
9208e4b2 1529 emit_insn (gen_rtx_SET (VOIDmode, temp4,
e0d80184
DM		 1530 gen_rtx_ASHIFT (DImode, sub_temp,
1531 GEN_INT (32))));
4bf7135b 1532
9bb3323d 1533 emit_insn (gen_safe_HIGH64 (temp2, low_bits));
e0d80184 1534 if ((low_bits & ~0xfffffc00) != 0)
f710f868
DM		 1535 {
1536 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1537 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1538 emit_insn (gen_rtx_SET (VOIDmode, op0,
1539 gen_rtx_PLUS (DImode, temp4, temp3)));
1540 }
1541 else
1542 {
1543 emit_insn (gen_rtx_SET (VOIDmode, op0,
1544 gen_rtx_PLUS (DImode, temp4, temp2)));
1545 }
284d86e9 1546 }
e0d80184
DM		 1547 else
1548 {
9208e4b2
DM		 1549 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1550 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1551 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
e0d80184 1552 int to_shift = 12;
284d86e9 1553
e0d80184
DM		 1554 /* We are in the middle of reload, so this is really
1555 painful. However we do still make an attempt to
5108f3e5 1556 avoid emitting truly stupid code. */
e0d80184
DM		 1557 if (low1 != const0_rtx)
1558 {
9208e4b2 1559 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184 1560 gen_rtx_ASHIFT (DImode, sub_temp,
2a01c939 1561 GEN_INT (to_shift))));
9208e4b2 1562 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1563 gen_rtx_IOR (DImode, op0, low1)));
1564 sub_temp = op0;
1565 to_shift = 12;
1566 }
1567 else
1568 {
1569 to_shift += 12;
1570 }
1571 if (low2 != const0_rtx)
1572 {
9208e4b2 1573 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1574 gen_rtx_ASHIFT (DImode, sub_temp,
1575 GEN_INT (to_shift))));
9208e4b2 1576 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1577 gen_rtx_IOR (DImode, op0, low2)));
1578 sub_temp = op0;
1579 to_shift = 8;
1580 }
1581 else
1582 {
1583 to_shift += 8;
1584 }
9208e4b2 1585 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1586 gen_rtx_ASHIFT (DImode, sub_temp,
1587 GEN_INT (to_shift))));
1588 if (low3 != const0_rtx)
9208e4b2 1589 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184 1590 gen_rtx_IOR (DImode, op0, low3)));
80ffc95e 1591 /* phew... */
e0d80184 1592 }
284d86e9
JC		 1593}
1594
80ffc95e 1595/* Analyze a 64-bit constant for certain properties. */
e80d5f80
KG		 1596static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1597 unsigned HOST_WIDE_INT,
1598 int *, int *, int *);
2a01c939 1599
e0d80184 1600static void
fc27d102
KG		 1601analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1602 unsigned HOST_WIDE_INT low_bits,
1603 int *hbsp, int *lbsp, int *abbasp)
ab835497 1604{
e0d80184
DM		 1605 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1606 int i;
ab835497 1607
e0d80184
DM		 1608 lowest_bit_set = highest_bit_set = -1;
1609 i = 0;
1610 do
ab835497 1611 {
e0d80184
DM		 1612 if ((lowest_bit_set == -1)
1613 && ((low_bits >> i) & 1))
1614 lowest_bit_set = i;
1615 if ((highest_bit_set == -1)
1616 && ((high_bits >> (32 - i - 1)) & 1))
1617 highest_bit_set = (64 - i - 1);
1618 }
1619 while (++i < 32
1620 && ((highest_bit_set == -1)
1621 || (lowest_bit_set == -1)));
1622 if (i == 32)
1623 {
1624 i = 0;
1625 do
ab835497 1626 {
e0d80184
DM		 1627 if ((lowest_bit_set == -1)
1628 && ((high_bits >> i) & 1))
1629 lowest_bit_set = i + 32;
1630 if ((highest_bit_set == -1)
1631 && ((low_bits >> (32 - i - 1)) & 1))
1632 highest_bit_set = 32 - i - 1;
ab835497 1633 }
e0d80184
DM		 1634 while (++i < 32
1635 && ((highest_bit_set == -1)
1636 || (lowest_bit_set == -1)));
1637 }
1638 /* If there are no bits set this should have gone out
1639 as one instruction! */
f5f7d171 1640 gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1);
e0d80184
DM		 1641 all_bits_between_are_set = 1;
1642 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1643 {
1644 if (i < 32)
1645 {
1646 if ((low_bits & (1 << i)) != 0)
1647 continue;
1648 }
1649 else
1650 {
1651 if ((high_bits & (1 << (i - 32))) != 0)
1652 continue;
1653 }
1654 all_bits_between_are_set = 0;
1655 break;
ab835497 1656 }
e0d80184
DM		 1657 *hbsp = highest_bit_set;
1658 *lbsp = lowest_bit_set;
1659 *abbasp = all_bits_between_are_set;
ab835497 1660}
6a4bb1fa 1661
e80d5f80 1662static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
2a01c939 1663
e0d80184 1664static int
fc27d102
KG		 1665const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1666 unsigned HOST_WIDE_INT low_bits)
e0d80184
DM		 1667{
1668 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
284d86e9 1669
e0d80184 1670 if (high_bits == 0
f451b552 1671 || high_bits == 0xffffffff)
e0d80184 1672 return 1;
6a4bb1fa 1673
e0d80184
DM		 1674 analyze_64bit_constant (high_bits, low_bits,
1675 &highest_bit_set, &lowest_bit_set,
1676 &all_bits_between_are_set);
6a4bb1fa 1677
f710f868
DM		 1678 if ((highest_bit_set == 63
1679 || lowest_bit_set == 0)
e0d80184
DM		 1680 && all_bits_between_are_set != 0)
1681 return 1;
6a4bb1fa 1682
9208e4b2
DM		 1683 if ((highest_bit_set - lowest_bit_set) < 21)
1684 return 1;
1685
6a4bb1fa
DE		 1686 return 0;
1687}
1688
e80d5f80
KG		 1689static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1690 unsigned HOST_WIDE_INT,
1691 int, int);
2a01c939
DM		 1692
1693static unsigned HOST_WIDE_INT
fc27d102
KG		 1694create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1695 unsigned HOST_WIDE_INT low_bits,
1696 int lowest_bit_set, int shift)
ab835497 1697{
f710f868 1698 HOST_WIDE_INT hi, lo;
ab835497 1699
e0d80184
DM		 1700 if (lowest_bit_set < 32)
1701 {
1702 lo = (low_bits >> lowest_bit_set) << shift;
1703 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1704 }
1705 else
1706 {
1707 lo = 0;
1708 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1709 }
f5f7d171 1710 gcc_assert (! (hi & lo));
e0d80184
DM		 1711 return (hi | lo);
1712}
ab835497 1713
e0d80184
DM		 1714/* Here we are sure to be arch64 and this is an integer constant
1715 being loaded into a register. Emit the most efficient
1716 insn sequence possible. Detection of all the 1-insn cases
1717 has been done already. */
1718void
fc27d102 1719sparc_emit_set_const64 (rtx op0, rtx op1)
e0d80184 1720{
2a01c939 1721 unsigned HOST_WIDE_INT high_bits, low_bits;
e0d80184
DM		 1722 int lowest_bit_set, highest_bit_set;
1723 int all_bits_between_are_set;
1d511ed5 1724 rtx temp = 0;
ab835497 1725
e0d80184 1726 /* Sanity check that we know what we are working with. */
bea5071f
EB		 1727 gcc_assert (TARGET_ARCH64
1728 && (GET_CODE (op0) == SUBREG
1729 || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));
380f6ad3 1730
f710f868
DM		 1731 if (reload_in_progress || reload_completed)
1732 temp = op0;
f710f868 1733
0e5d569c 1734 if (GET_CODE (op1) != CONST_INT)
e0d80184 1735 {
5f78aa30
JC		 1736 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1737 return;
e0d80184 1738 }
ab835497 1739
1d511ed5
EB		 1740 if (! temp)
1741 temp = gen_reg_rtx (DImode);
1742
0e5d569c
EB		 1743 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1744 low_bits = (INTVAL (op1) & 0xffffffff);
ab835497 1745
e0d80184
DM		 1746 /* low_bits bits 0 --> 31
1747 high_bits bits 32 --> 63 */
ab835497 1748
e0d80184
DM		 1749 analyze_64bit_constant (high_bits, low_bits,
1750 &highest_bit_set, &lowest_bit_set,
1751 &all_bits_between_are_set);
1752
1753 /* First try for a 2-insn sequence. */
1754
1755 /* These situations are preferred because the optimizer can
1756 * do more things with them:
1757 * 1) mov -1, %reg
1758 * sllx %reg, shift, %reg
1759 * 2) mov -1, %reg
1760 * srlx %reg, shift, %reg
1761 * 3) mov some_small_const, %reg
1762 * sllx %reg, shift, %reg
1763 */
1764 if (((highest_bit_set == 63
1765 || lowest_bit_set == 0)
1766 && all_bits_between_are_set != 0)
2a01c939 1767 || ((highest_bit_set - lowest_bit_set) < 12))
e0d80184 1768 {
9208e4b2 1769 HOST_WIDE_INT the_const = -1;
e0d80184
DM		 1770 int shift = lowest_bit_set;
1771
f710f868
DM		 1772 if ((highest_bit_set != 63
1773 && lowest_bit_set != 0)
1774 || all_bits_between_are_set == 0)
ab835497 1775 {
e0d80184 1776 the_const =
9208e4b2 1777 create_simple_focus_bits (high_bits, low_bits,
9208e4b2 1778 lowest_bit_set, 0);
ab835497 1779 }
e0d80184 1780 else if (lowest_bit_set == 0)
9208e4b2 1781 shift = -(63 - highest_bit_set);
e0d80184 1782
f5f7d171
JM		 1783 gcc_assert (SPARC_SIMM13_P (the_const));
1784 gcc_assert (shift != 0);
f710f868 1785
9208e4b2 1786 emit_insn (gen_safe_SET64 (temp, the_const));
e0d80184 1787 if (shift > 0)
9208e4b2 1788 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184
DM		 1789 op0,
1790 gen_rtx_ASHIFT (DImode,
1791 temp,
1792 GEN_INT (shift))));
1793 else if (shift < 0)
9208e4b2 1794 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1795 op0,
9208e4b2 1796 gen_rtx_LSHIFTRT (DImode,
e0d80184
DM		 1797 temp,
1798 GEN_INT (-shift))));
e0d80184
DM		 1799 return;
1800 }
ab835497 1801
e0d80184
DM		 1802 /* Now a range of 22 or less bits set somewhere.
1803 * 1) sethi %hi(focus_bits), %reg
1804 * sllx %reg, shift, %reg
1805 * 2) sethi %hi(focus_bits), %reg
1806 * srlx %reg, shift, %reg
1807 */
2a01c939 1808 if ((highest_bit_set - lowest_bit_set) < 21)
e0d80184 1809 {
2a01c939 1810 unsigned HOST_WIDE_INT focus_bits =
e0d80184 1811 create_simple_focus_bits (high_bits, low_bits,
ddf80874 1812 lowest_bit_set, 10);
f710f868 1813
f5f7d171
JM		 1814 gcc_assert (SPARC_SETHI_P (focus_bits));
1815 gcc_assert (lowest_bit_set != 10);
f710f868 1816
9bb3323d 1817 emit_insn (gen_safe_HIGH64 (temp, focus_bits));
e0d80184 1818
9208e4b2 1819 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
e0d80184 1820 if (lowest_bit_set < 10)
9208e4b2 1821 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1822 op0,
9208e4b2 1823 gen_rtx_LSHIFTRT (DImode, temp,
e0d80184 1824 GEN_INT (10 - lowest_bit_set))));
9208e4b2
DM		 1825 else if (lowest_bit_set > 10)
1826 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184
DM		 1827 op0,
1828 gen_rtx_ASHIFT (DImode, temp,
1829 GEN_INT (lowest_bit_set - 10))));
e0d80184
DM		 1830 return;
1831 }
1832
1833 /* 1) sethi %hi(low_bits), %reg
1834 * or %reg, %lo(low_bits), %reg
1835 * 2) sethi %hi(~low_bits), %reg
1836 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1837 */
1838 if (high_bits == 0
2a01c939 1839 || high_bits == 0xffffffff)
5f78aa30
JC		 1840 {
1841 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1842 (high_bits == 0xffffffff));
1843 return;
1844 }
e0d80184 1845
f710f868
DM		 1846 /* Now, try 3-insn sequences. */
1847
e0d80184
DM		 1848 /* 1) sethi %hi(high_bits), %reg
1849 * or %reg, %lo(high_bits), %reg
1850 * sllx %reg, 32, %reg
1851 */
f710f868 1852 if (low_bits == 0)
5f78aa30 1853 {
f710f868 1854 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
5f78aa30
JC		 1855 return;
1856 }
e0d80184 1857
f710f868
DM		 1858 /* We may be able to do something quick
1859 when the constant is negated, so try that. */
e0d80184
DM		 1860 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1861 (~low_bits) & 0xfffffc00))
1862 {
5108f3e5
DM		 1863 /* NOTE: The trailing bits get XOR'd so we need the
1864 non-negated bits, not the negated ones. */
1865 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
e0d80184
DM		 1866
1867 if ((((~high_bits) & 0xffffffff) == 0
1868 && ((~low_bits) & 0x80000000) == 0)
1869 || (((~high_bits) & 0xffffffff) == 0xffffffff
1870 && ((~low_bits) & 0x80000000) != 0))
ab835497 1871 {
0e5d569c 1872 unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff);
e0d80184 1873
5108f3e5
DM		 1874 if ((SPARC_SETHI_P (fast_int)
1875 && (~high_bits & 0xffffffff) == 0)
1876 || SPARC_SIMM13_P (fast_int))
9208e4b2 1877 emit_insn (gen_safe_SET64 (temp, fast_int));
ab835497 1878 else
0e5d569c 1879 sparc_emit_set_const64 (temp, GEN_INT (fast_int));
ab835497 1880 }
e0d80184
DM		 1881 else
1882 {
1883 rtx negated_const;
e0d80184
DM		 1884 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
1885 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
e0d80184
DM		 1886 sparc_emit_set_const64 (temp, negated_const);
1887 }
5108f3e5
DM		 1888
1889 /* If we are XOR'ing with -1, then we should emit a one's complement
1890 instead. This way the combiner will notice logical operations
1891 such as ANDN later on and substitute. */
1892 if (trailing_bits == 0x3ff)
1893 {
1894 emit_insn (gen_rtx_SET (VOIDmode, op0,
1895 gen_rtx_NOT (DImode, temp)));
1896 }
1897 else
1898 {
1899 emit_insn (gen_rtx_SET (VOIDmode,
1900 op0,
1901 gen_safe_XOR64 (temp,
1902 (-0x400 | trailing_bits))));
1903 }
e0d80184 1904 return;
ab835497 1905 }
ab835497 1906
e0d80184
DM		 1907 /* 1) sethi %hi(xxx), %reg
1908 * or %reg, %lo(xxx), %reg
1909 * sllx %reg, yyy, %reg
f710f868
DM		 1910 *
1911 * ??? This is just a generalized version of the low_bits==0
1912 * thing above, FIXME...
e0d80184
DM		 1913 */
1914 if ((highest_bit_set - lowest_bit_set) < 32)
1915 {
f710f868
DM		 1916 unsigned HOST_WIDE_INT focus_bits =
1917 create_simple_focus_bits (high_bits, low_bits,
ddf80874 1918 lowest_bit_set, 0);
ab835497 1919
e0d80184 1920 /* We can't get here in this state. */
f5f7d171 1921 gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32);
95726648 1922
e0d80184
DM		 1923 /* So what we know is that the set bits straddle the
1924 middle of the 64-bit word. */
5f78aa30
JC		 1925 sparc_emit_set_const64_quick2 (op0, temp,
1926 focus_bits, 0,
1927 lowest_bit_set);
1928 return;
e0d80184 1929 }
c85f7c16 1930
f710f868
DM		 1931 /* 1) sethi %hi(high_bits), %reg
1932 * or %reg, %lo(high_bits), %reg
1933 * sllx %reg, 32, %reg
1934 * or %reg, low_bits, %reg
1935 */
1936 if (SPARC_SIMM13_P(low_bits)
1937 && ((int)low_bits > 0))
1938 {
1939 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
1940 return;
1941 }
1942
80ffc95e 1943 /* The easiest way when all else fails, is full decomposition. */
e0d80184
DM		 1944#if 0
1945 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
1946 high_bits, low_bits, ~high_bits, ~low_bits);
1947#endif
1948 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
c85f7c16 1949}
0e5d569c 1950#endif /* HOST_BITS_PER_WIDE_INT == 32 */
c85f7c16 1951
e267e177
RH		 1952/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1953 return the mode to be used for the comparison. For floating-point,
1954 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
1955 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1956 processing is needed. */
1957
1958enum machine_mode
fc27d102 1959select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
e267e177
RH		 1960{
1961 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1962 {
1963 switch (op)
1964 {
1965 case EQ:
1966 case NE:
1967 case UNORDERED:
1968 case ORDERED:
1969 case UNLT:
1970 case UNLE:
1971 case UNGT:
1972 case UNGE:
1973 case UNEQ:
7913f3d0 1974 case LTGT:
e267e177
RH		 1975 return CCFPmode;
1976
1977 case LT:
1978 case LE:
1979 case GT:
1980 case GE:
1981 return CCFPEmode;
1982
1983 default:
f5f7d171 1984 gcc_unreachable ();
e267e177
RH		 1985 }
1986 }
1987 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
1988 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
1989 {
1990 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
1991 return CCX_NOOVmode;
1992 else
1993 return CC_NOOVmode;
1994 }
1995 else
1996 {
1997 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
1998 return CCXmode;
1999 else
2000 return CCmode;
2001 }
2002}
2003
19047e4a 2004/* Emit the compare insn and return the CC reg for a CODE comparison. */
c85f7c16 2005
e0d80184 2006rtx
7e04157d 2007gen_compare_reg (enum rtx_code code)
c85f7c16 2008{
65c5ae8b
PB		 2009 enum machine_mode mode;
2010 rtx x, y, cc_reg;
c85f7c16 2011
65c5ae8b
PB		 2012 if (GET_MODE_CLASS (GET_MODE (sparc_compare_op0)) == MODE_CC)
2013 return sparc_compare_op0;
2014
2015 x = sparc_compare_op0;
2016 y = sparc_compare_op1;
2017 mode = SELECT_CC_MODE (code, x, y);
8ec11fe9 2018
e0d80184
DM		 2019 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2020 fcc regs (cse can't tell they're really call clobbered regs and will
2021 remove a duplicate comparison even if there is an intervening function
2022 call - it will then try to reload the cc reg via an int reg which is why
2023 we need the movcc patterns). It is possible to provide the movcc
2024 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2025 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2026 to tell cse that CCFPE mode registers (even pseudos) are call
2027 clobbered. */
c85f7c16 2028
e0d80184
DM		 2029 /* ??? This is an experiment. Rather than making changes to cse which may
2030 or may not be easy/clean, we do our own cse. This is possible because
2031 we will generate hard registers. Cse knows they're call clobbered (it
2032 doesn't know the same thing about pseudos). If we guess wrong, no big
2033 deal, but if we win, great! */
c85f7c16 2034
e0d80184
DM		 2035 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2036#if 1 /* experiment */
284d86e9 2037 {
e0d80184
DM		 2038 int reg;
2039 /* We cycle through the registers to ensure they're all exercised. */
2040 static int next_fcc_reg = 0;
2041 /* Previous x,y for each fcc reg. */
2042 static rtx prev_args[4][2];
284d86e9 2043
e0d80184
DM		 2044 /* Scan prev_args for x,y. */
2045 for (reg = 0; reg < 4; reg++)
2046 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2047 break;
2048 if (reg == 4)
2049 {
2050 reg = next_fcc_reg;
2051 prev_args[reg][0] = x;
2052 prev_args[reg][1] = y;
2053 next_fcc_reg = (next_fcc_reg + 1) & 3;
2054 }
2055 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
284d86e9 2056 }
e0d80184
DM		 2057#else
2058 cc_reg = gen_reg_rtx (mode);
2059#endif /* ! experiment */
2060 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2061 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2062 else
2063 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
284d86e9 2064
19047e4a
EB		 2065 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2066 will only result in an unrecognizable insn so no point in asserting. */
2067 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y)));
c85f7c16 2068
e0d80184
DM		 2069 return cc_reg;
2070}
c85f7c16 2071
19047e4a
EB		 2072/* Same as above but return the whole compare operator. */
2073
2074rtx
2075gen_compare_operator (enum rtx_code code)
2076{
2077 rtx cc_reg;
2078
2079 if (GET_MODE (sparc_compare_op0) == TFmode && !TARGET_HARD_QUAD)
2080 code
2081 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, code);
2082
2083 cc_reg = gen_compare_reg (code);
2084 return gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
2085}
2086
e0d80184
DM		 2087/* This function is used for v9 only.
2088 CODE is the code for an Scc's comparison.
2089 OPERANDS[0] is the target of the Scc insn.
2090 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2091 been generated yet).
c85f7c16 2092
e0d80184 2093 This function is needed to turn
ab835497 2094
e0d80184
DM		 2095 (set (reg:SI 110)
2096 (gt (reg:CCX 100 %icc)
2097 (const_int 0)))
2098 into
2099 (set (reg:SI 110)
2100 (gt:DI (reg:CCX 100 %icc)
2101 (const_int 0)))
2102
2103 IE: The instruction recognizer needs to see the mode of the comparison to
2104 find the right instruction. We could use "gt:DI" right in the
2105 define_expand, but leaving it out allows us to handle DI, SI, etc.
ab835497 2106
e0d80184
DM		 2107 We refer to the global sparc compare operands sparc_compare_op0 and
2108 sparc_compare_op1. */
ab835497
RK		 2109
2110int
fc27d102 2111gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
ab835497 2112{
e0d80184
DM		 2113 if (! TARGET_ARCH64
2114 && (GET_MODE (sparc_compare_op0) == DImode
2115 || GET_MODE (operands[0]) == DImode))
2116 return 0;
7e2feebf 2117
e0d80184
DM		 2118 /* Try to use the movrCC insns. */
2119 if (TARGET_ARCH64
7e04157d
DM		 2120 && GET_MODE_CLASS (GET_MODE (sparc_compare_op0)) == MODE_INT
2121 && sparc_compare_op1 == const0_rtx
e0d80184 2122 && v9_regcmp_p (compare_code))
ab835497 2123 {
7e04157d
DM		 2124 rtx op0 = sparc_compare_op0;
2125 rtx temp;
2126
e0d80184 2127 /* Special case for op0 != 0. This can be done with one instruction if
a42519be 2128 operands[0] == sparc_compare_op0. */
e0d80184
DM		 2129
2130 if (compare_code == NE
2131 && GET_MODE (operands[0]) == DImode
a42519be 2132 && rtx_equal_p (op0, operands[0]))
ab835497 2133 {
e0d80184
DM		 2134 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2135 gen_rtx_IF_THEN_ELSE (DImode,
2136 gen_rtx_fmt_ee (compare_code, DImode,
2137 op0, const0_rtx),
2138 const1_rtx,
2139 operands[0])));
ab835497
RK		 2140 return 1;
2141 }
e0d80184 2142
a42519be
JJ		 2143 if (reg_overlap_mentioned_p (operands[0], op0))
2144 {
2145 /* Handle the case where operands[0] == sparc_compare_op0.
2146 We "early clobber" the result. */
2147 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2148 emit_move_insn (op0, sparc_compare_op0);
2149 }
2150
e0d80184
DM		 2151 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2152 if (GET_MODE (op0) != DImode)
ab835497 2153 {
e0d80184
DM		 2154 temp = gen_reg_rtx (DImode);
2155 convert_move (temp, op0, 0);
ab835497 2156 }
e0d80184
DM		 2157 else
2158 temp = op0;
2159 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2160 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2161 gen_rtx_fmt_ee (compare_code, DImode,
2162 temp, const0_rtx),
2163 const1_rtx,
2164 operands[0])));
95726648
DE		 2165 return 1;
2166 }
e0d80184 2167 else
ab835497 2168 {
7e04157d 2169 operands[1] = gen_compare_reg (compare_code);
ab835497 2170
e0d80184 2171 switch (GET_MODE (operands[1]))
ab835497 2172 {
e0d80184
DM		 2173 case CCmode :
2174 case CCXmode :
2175 case CCFPEmode :
2176 case CCFPmode :
2177 break;
2178 default :
f5f7d171 2179 gcc_unreachable ();
ab835497 2180 }
e0d80184
DM		 2181 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2182 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2183 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2184 gen_rtx_fmt_ee (compare_code,
2185 GET_MODE (operands[1]),
2186 operands[1], const0_rtx),
2187 const1_rtx, operands[0])));
2188 return 1;
ab835497 2189 }
ab835497 2190}
4fb4e4b8 2191
e0d80184
DM		 2192/* Emit a conditional jump insn for the v9 architecture using comparison code
2193 CODE and jump target LABEL.
2194 This function exists to take advantage of the v9 brxx insns. */
ab835497 2195
e0d80184 2196void
fc27d102 2197emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
ab835497 2198{
65c5ae8b 2199 gcc_assert (GET_MODE_CLASS (GET_MODE (sparc_compare_op0)) != MODE_CC);
e0d80184
DM		 2200 emit_jump_insn (gen_rtx_SET (VOIDmode,
2201 pc_rtx,
2202 gen_rtx_IF_THEN_ELSE (VOIDmode,
2203 gen_rtx_fmt_ee (code, GET_MODE (op0),
2204 op0, const0_rtx),
2205 gen_rtx_LABEL_REF (VOIDmode, label),
2206 pc_rtx)));
2207}
7b1ac798
JJ		 2208
2209/* Generate a DFmode part of a hard TFmode register.
2210 REG is the TFmode hard register, LOW is 1 for the
2211 low 64bit of the register and 0 otherwise.
2212 */
2213rtx
fc27d102 2214gen_df_reg (rtx reg, int low)
7b1ac798
JJ		 2215{
2216 int regno = REGNO (reg);
2217
2218 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2aac41d6 2219 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
7b1ac798
JJ		 2220 return gen_rtx_REG (DFmode, regno);
2221}
e0d80184 2222\f
73985940
RH		 2223/* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2224 Unlike normal calls, TFmode operands are passed by reference. It is
2225 assumed that no more than 3 operands are required. */
2226
2227static void
fc27d102 2228emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
73985940
RH		 2229{
2230 rtx ret_slot = NULL, arg[3], func_sym;
4e7d5d27 2231 int i;
73985940
RH		 2232
2233 /* We only expect to be called for conversions, unary, and binary ops. */
f5f7d171 2234 gcc_assert (nargs == 2 || nargs == 3);
73985940
RH		 2235
2236 for (i = 0; i < nargs; ++i)
2237 {
2238 rtx this_arg = operands[i];
2239 rtx this_slot;
2240
2241 /* TFmode arguments and return values are passed by reference. */
2242 if (GET_MODE (this_arg) == TFmode)
2243 {
4e7d5d27
DM		 2244 int force_stack_temp;
2245
2246 force_stack_temp = 0;
2247 if (TARGET_BUGGY_QP_LIB && i == 0)
2248 force_stack_temp = 1;
2249
2250 if (GET_CODE (this_arg) == MEM
2251 && ! force_stack_temp)
2252 this_arg = XEXP (this_arg, 0);
2253 else if (CONSTANT_P (this_arg)
2254 && ! force_stack_temp)
73985940
RH		 2255 {
2256 this_slot = force_const_mem (TFmode, this_arg);
2257 this_arg = XEXP (this_slot, 0);
2258 }
2259 else
2260 {
2261 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2262
2263 /* Operand 0 is the return value. We'll copy it out later. */
2264 if (i > 0)
2265 emit_move_insn (this_slot, this_arg);
2266 else
2267 ret_slot = this_slot;
2268
2269 this_arg = XEXP (this_slot, 0);
2270 }
2271 }
2272
2273 arg[i] = this_arg;
2274 }
2275
2276 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2277
2278 if (GET_MODE (operands[0]) == TFmode)
2279 {
2280 if (nargs == 2)
2281 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2282 arg[0], GET_MODE (arg[0]),
2283 arg[1], GET_MODE (arg[1]));
2284 else
2285 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2286 arg[0], GET_MODE (arg[0]),
2287 arg[1], GET_MODE (arg[1]),
2288 arg[2], GET_MODE (arg[2]));
2289
2290 if (ret_slot)
2291 emit_move_insn (operands[0], ret_slot);
2292 }
2293 else
2294 {
2295 rtx ret;
2296
f5f7d171 2297 gcc_assert (nargs == 2);
73985940
RH		 2298
2299 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2300 GET_MODE (operands[0]), 1,
2301 arg[1], GET_MODE (arg[1]));
2302
2303 if (ret != operands[0])
2304 emit_move_insn (operands[0], ret);
2305 }
2306}
2307
2308/* Expand soft-float TFmode calls to sparc abi routines. */
2309
2310static void
fc27d102 2311emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
73985940
RH		 2312{
2313 const char *func;
2314
2315 switch (code)
2316 {
2317 case PLUS:
2318 func = "_Qp_add";
2319 break;
2320 case MINUS:
2321 func = "_Qp_sub";
2322 break;
2323 case MULT:
2324 func = "_Qp_mul";
2325 break;
2326 case DIV:
2327 func = "_Qp_div";
2328 break;
2329 default:
f5f7d171 2330 gcc_unreachable ();
73985940
RH		 2331 }
2332
2333 emit_soft_tfmode_libcall (func, 3, operands);
2334}
2335
2336static void
fc27d102 2337emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
73985940
RH		 2338{
2339 const char *func;
2340
f5f7d171
JM		 2341 gcc_assert (code == SQRT);
2342 func = "_Qp_sqrt";
73985940
RH		 2343
2344 emit_soft_tfmode_libcall (func, 2, operands);
2345}
2346
2347static void
fc27d102 2348emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
73985940
RH		 2349{
2350 const char *func;
2351
2352 switch (code)
2353 {
2354 case FLOAT_EXTEND:
2355 switch (GET_MODE (operands[1]))
2356 {
2357 case SFmode:
2358 func = "_Qp_stoq";
2359 break;
2360 case DFmode:
2361 func = "_Qp_dtoq";
2362 break;
2363 default:
f5f7d171 2364 gcc_unreachable ();
73985940
RH		 2365 }
2366 break;
2367
2368 case FLOAT_TRUNCATE:
2369 switch (GET_MODE (operands[0]))
2370 {
2371 case SFmode:
2372 func = "_Qp_qtos";
2373 break;
2374 case DFmode:
2375 func = "_Qp_qtod";
2376 break;
2377 default:
f5f7d171 2378 gcc_unreachable ();
73985940
RH		 2379 }
2380 break;
2381
2382 case FLOAT:
2383 switch (GET_MODE (operands[1]))
2384 {
2385 case SImode:
2386 func = "_Qp_itoq";
92693034
JM		 2387 if (TARGET_ARCH64)
2388 operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]);
73985940
RH		 2389 break;
2390 case DImode:
2391 func = "_Qp_xtoq";
2392 break;
2393 default:
f5f7d171 2394 gcc_unreachable ();
73985940
RH		 2395 }
2396 break;
2397
2398 case UNSIGNED_FLOAT:
2399 switch (GET_MODE (operands[1]))
2400 {
2401 case SImode:
2402 func = "_Qp_uitoq";
92693034
JM		 2403 if (TARGET_ARCH64)
2404 operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
73985940
RH		 2405 break;
2406 case DImode:
2407 func = "_Qp_uxtoq";
2408 break;
2409 default:
f5f7d171 2410 gcc_unreachable ();
73985940
RH		 2411 }
2412 break;
2413
2414 case FIX:
2415 switch (GET_MODE (operands[0]))
2416 {
2417 case SImode:
2418 func = "_Qp_qtoi";
2419 break;
2420 case DImode:
2421 func = "_Qp_qtox";
2422 break;
2423 default:
f5f7d171 2424 gcc_unreachable ();
73985940
RH		 2425 }
2426 break;
2427
2428 case UNSIGNED_FIX:
2429 switch (GET_MODE (operands[0]))
2430 {
2431 case SImode:
2432 func = "_Qp_qtoui";
2433 break;
2434 case DImode:
2435 func = "_Qp_qtoux";
2436 break;
2437 default:
f5f7d171 2438 gcc_unreachable ();
73985940
RH		 2439 }
2440 break;
2441
2442 default:
f5f7d171 2443 gcc_unreachable ();
73985940
RH		 2444 }
2445
2446 emit_soft_tfmode_libcall (func, 2, operands);
2447}
2448
2449/* Expand a hard-float tfmode operation. All arguments must be in
2450 registers. */
2451
2452static void
fc27d102 2453emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
73985940
RH		 2454{
2455 rtx op, dest;
2456
ec8e098d 2457 if (GET_RTX_CLASS (code) == RTX_UNARY)
73985940
RH		 2458 {
2459 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2460 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2461 }
2462 else
2463 {
2464 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2465 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2466 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2467 operands[1], operands[2]);
2468 }
2469
2470 if (register_operand (operands[0], VOIDmode))
2471 dest = operands[0];
2472 else
2473 dest = gen_reg_rtx (GET_MODE (operands[0]));
2474
2475 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2476
2477 if (dest != operands[0])
2478 emit_move_insn (operands[0], dest);
2479}
2480
2481void
fc27d102 2482emit_tfmode_binop (enum rtx_code code, rtx *operands)
73985940
RH		 2483{
2484 if (TARGET_HARD_QUAD)
2485 emit_hard_tfmode_operation (code, operands);
2486 else
2487 emit_soft_tfmode_binop (code, operands);
2488}
2489
2490void
fc27d102 2491emit_tfmode_unop (enum rtx_code code, rtx *operands)
73985940
RH		 2492{
2493 if (TARGET_HARD_QUAD)
2494 emit_hard_tfmode_operation (code, operands);
2495 else
2496 emit_soft_tfmode_unop (code, operands);
2497}
2498
2499void
fc27d102 2500emit_tfmode_cvt (enum rtx_code code, rtx *operands)
73985940
RH		 2501{
2502 if (TARGET_HARD_QUAD)
2503 emit_hard_tfmode_operation (code, operands);
2504 else
2505 emit_soft_tfmode_cvt (code, operands);
2506}
2507\f
f17f9332
JJ		 2508/* Return nonzero if a branch/jump/call instruction will be emitting
2509 nop into its delay slot. */
2510
2511int
fc27d102 2512empty_delay_slot (rtx insn)
f17f9332
JJ		 2513{
2514 rtx seq;
2515
2516 /* If no previous instruction (should not happen), return true. */
2517 if (PREV_INSN (insn) == NULL)
2518 return 1;
2519
2520 seq = NEXT_INSN (PREV_INSN (insn));
2521 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2522 return 0;
2523
2524 return 1;
2525}
2526
9ac617d4 2527/* Return nonzero if TRIAL can go into the call delay slot. */
ab835497 2528
e0d80184 2529int
9ac617d4 2530tls_call_delay (rtx trial)
e0d80184 2531{
e10fbf96 2532 rtx pat;
1150a841 2533
9ac617d4 2534 /* Binutils allows
e10fbf96
EB		 2535 call __tls_get_addr, %tgd_call (foo)
2536 add %l7, %o0, %o0, %tgd_add (foo)
9ac617d4
EB		 2537 while Sun as/ld does not. */
2538 if (TARGET_GNU_TLS || !TARGET_TLS)
2539 return 1;
4fb4e4b8 2540
e0d80184 2541 pat = PATTERN (trial);
795068a4 2542
e10fbf96
EB		 2543 /* We must reject tgd_add{32|64}, i.e.
2544 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2545 and tldm_add{32|64}, i.e.
2546 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2547 for Sun as/ld. */
2548 if (GET_CODE (pat) == SET
2549 && GET_CODE (SET_SRC (pat)) == PLUS)
2550 {
2551 rtx unspec = XEXP (SET_SRC (pat), 1);
795068a4 2552
e10fbf96
EB		 2553 if (GET_CODE (unspec) == UNSPEC
2554 && (XINT (unspec, 1) == UNSPEC_TLSGD
2555 || XINT (unspec, 1) == UNSPEC_TLSLDM))
2556 return 0;
2557 }
2558
2559 return 1;
9ac617d4
EB		 2560}
2561
2562/* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2563 instruction. RETURN_P is true if the v9 variant 'return' is to be
2564 considered in the test too.
c137830f 2565
9ac617d4
EB		 2566 TRIAL must be a SET whose destination is a REG appropriate for the
2567 'restore' instruction or, if RETURN_P is true, for the 'return'
2568 instruction. */
795068a4 2569
9ac617d4
EB		 2570static int
2571eligible_for_restore_insn (rtx trial, bool return_p)
2572{
2573 rtx pat = PATTERN (trial);
2574 rtx src = SET_SRC (pat);
795068a4 2575
9ac617d4 2576 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3ec6f1a9
RK		 2577 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2578 && arith_operand (src, GET_MODE (src)))
3c6088d2
JJ		 2579 {
2580 if (TARGET_ARCH64)
2581 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2582 else
2583 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2584 }
e48addee 2585
9ac617d4 2586 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3ec6f1a9
RK		 2587 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2588 && arith_double_operand (src, GET_MODE (src)))
e0d80184 2589 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
795068a4 2590
9ac617d4
EB		 2591 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2592 else if (! TARGET_FPU && register_operand (src, SFmode))
2593 return 1;
2594
2595 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2596 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
e0d80184 2597 return 1;
f5da225e 2598
9ac617d4 2599 /* If we have the 'return' instruction, anything that does not use
e48addee 2600 local or output registers and can go into a delay slot wins. */
9ac617d4
EB		 2601 else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1)
2602 && (get_attr_in_uncond_branch_delay (trial)
2603 == IN_UNCOND_BRANCH_DELAY_TRUE))
e48addee
JJ		 2604 return 1;
2605
9ac617d4 2606 /* The 'restore src1,src2,dest' pattern for SImode. */
e0d80184 2607 else if (GET_CODE (src) == PLUS
9ac617d4
EB		 2608 && register_operand (XEXP (src, 0), SImode)
2609 && arith_operand (XEXP (src, 1), SImode))
e0d80184
DM		 2610 return 1;
2611
9ac617d4 2612 /* The 'restore src1,src2,dest' pattern for DImode. */
e0d80184 2613 else if (GET_CODE (src) == PLUS
9ac617d4
EB		 2614 && register_operand (XEXP (src, 0), DImode)
2615 && arith_double_operand (XEXP (src, 1), DImode))
795068a4 2616 return 1;
795068a4 2617
9ac617d4 2618 /* The 'restore src1,%lo(src2),dest' pattern. */
e48addee
JJ		 2619 else if (GET_CODE (src) == LO_SUM
2620 && ! TARGET_CM_MEDMID
2621 && ((register_operand (XEXP (src, 0), SImode)
2622 && immediate_operand (XEXP (src, 1), SImode))
2623 || (TARGET_ARCH64
2624 && register_operand (XEXP (src, 0), DImode)
2625 && immediate_operand (XEXP (src, 1), DImode))))
2626 return 1;
2627
9ac617d4 2628 /* The 'restore src,src,dest' pattern. */
e48addee
JJ		 2629 else if (GET_CODE (src) == ASHIFT
2630 && (register_operand (XEXP (src, 0), SImode)
2631 || register_operand (XEXP (src, 0), DImode))
2632 && XEXP (src, 1) == const1_rtx)
2633 return 1;
2634
795068a4
JW		 2635 return 0;
2636}
2637
9ac617d4
EB		 2638/* Return nonzero if TRIAL can go into the function return's
2639 delay slot. */
2640
5751a10b 2641int
9ac617d4 2642eligible_for_return_delay (rtx trial)
5751a10b 2643{
9ac617d4 2644 rtx pat;
5751a10b 2645
9ac617d4
EB		 2646 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2647 return 0;
2648
2649 if (get_attr_length (trial) != 1)
2650 return 0;
2651
2652 /* If there are any call-saved registers, we should scan TRIAL if it
2653 does not reference them. For now just make it easy. */
2654 if (num_gfregs)
2655 return 0;
2656
2657 /* If the function uses __builtin_eh_return, the eh_return machinery
2658 occupies the delay slot. */
e3b5732b 2659 if (crtl->calls_eh_return)
9ac617d4
EB		 2660 return 0;
2661
2662 /* In the case of a true leaf function, anything can go into the slot. */
5be9b7a1 2663 if (sparc_leaf_function_p)
9ac617d4
EB		 2664 return get_attr_in_uncond_branch_delay (trial)
2665 == IN_UNCOND_BRANCH_DELAY_TRUE;
5751a10b
JJ		 2666
2667 pat = PATTERN (trial);
5751a10b 2668
9ac617d4
EB		 2669 /* Otherwise, only operations which can be done in tandem with
2670 a `restore' or `return' insn can go into the delay slot. */
2671 if (GET_CODE (SET_DEST (pat)) != REG
2672 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
2673 return 0;
5751a10b 2674
9ac617d4
EB		 2675 /* If this instruction sets up floating point register and we have a return
2676 instruction, it can probably go in. But restore will not work
2677 with FP_REGS. */
2678 if (REGNO (SET_DEST (pat)) >= 32)
2679 return (TARGET_V9
2680 && ! epilogue_renumber (&pat, 1)
2681 && (get_attr_in_uncond_branch_delay (trial)
2682 == IN_UNCOND_BRANCH_DELAY_TRUE));
2683
2684 return eligible_for_restore_insn (trial, true);
5751a10b
JJ		 2685}
2686
9ac617d4 2687/* Return nonzero if TRIAL can go into the sibling call's
7d167afd
JJ		 2688 delay slot. */
2689
2690int
fc27d102 2691eligible_for_sibcall_delay (rtx trial)
7d167afd 2692{
9ac617d4 2693 rtx pat;
7d167afd
JJ		 2694
2695 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2696 return 0;
2697
8456b95a 2698 if (get_attr_length (trial) != 1)
7d167afd
JJ		 2699 return 0;
2700
2701 pat = PATTERN (trial);
2702
5be9b7a1 2703 if (sparc_leaf_function_p)
7d167afd
JJ		 2704 {
2705 /* If the tail call is done using the call instruction,
2706 we have to restore %o7 in the delay slot. */
6244b14e 2707 if (LEAF_SIBCALL_SLOT_RESERVED_P)
7d167afd
JJ		 2708 return 0;
2709
2710 /* %g1 is used to build the function address */
2711 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2712 return 0;
2713
2714 return 1;
2715 }
2716
2717 /* Otherwise, only operations which can be done in tandem with
2718 a `restore' insn can go into the delay slot. */
2719 if (GET_CODE (SET_DEST (pat)) != REG
9ac617d4 2720 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
7d167afd
JJ		 2721 || REGNO (SET_DEST (pat)) >= 32)
2722 return 0;
2723
2724 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2725 in most cases. */
2726 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2727 return 0;
2728
9ac617d4 2729 return eligible_for_restore_insn (trial, false);
e0d80184 2730}
ab835497 2731
e0d80184 2732int
fc27d102 2733short_branch (int uid1, int uid2)
e0d80184 2734{
9d98a694 2735 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
77b91512
RK		 2736
2737 /* Leave a few words of "slop". */
2738 if (delta >= -1023 && delta <= 1022)
e0d80184 2739 return 1;
77b91512 2740
e0d80184
DM		 2741 return 0;
2742}
ab835497 2743
5e7a8ee0 2744/* Return nonzero if REG is not used after INSN.
e0d80184
DM		 2745 We assume REG is a reload reg, and therefore does
2746 not live past labels or calls or jumps. */
2747int
fc27d102 2748reg_unused_after (rtx reg, rtx insn)
e0d80184
DM		 2749{
2750 enum rtx_code code, prev_code = UNKNOWN;
ab835497 2751
e0d80184 2752 while ((insn = NEXT_INSN (insn)))
61a55e8b 2753 {
e0d80184
DM		 2754 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2755 return 1;
ab835497 2756
e0d80184
DM		 2757 code = GET_CODE (insn);
2758 if (GET_CODE (insn) == CODE_LABEL)
2759 return 1;
bc961ed7 2760
ec8e098d 2761 if (INSN_P (insn))
61a55e8b 2762 {
e0d80184
DM		 2763 rtx set = single_set (insn);
2764 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2765 if (set && in_src)
2766 return 0;
2767 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2768 return 1;
2769 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2770 return 0;
61a55e8b 2771 }
e0d80184 2772 prev_code = code;
61a55e8b 2773 }
e0d80184
DM		 2774 return 1;
2775}
2776\f
5751a10b
JJ		 2777/* Determine if it's legal to put X into the constant pool. This
2778 is not possible if X contains the address of a symbol that is
2779 not constant (TLS) or not known at final link time (PIC). */
2780
2781static bool
2782sparc_cannot_force_const_mem (rtx x)
2783{
2784 switch (GET_CODE (x))
2785 {
2786 case CONST_INT:
2787 case CONST_DOUBLE:
c75d6010 2788 case CONST_VECTOR:
5751a10b
JJ		 2789 /* Accept all non-symbolic constants. */
2790 return false;
2791
2792 case LABEL_REF:
2793 /* Labels are OK iff we are non-PIC. */
2794 return flag_pic != 0;
2795
2796 case SYMBOL_REF:
2797 /* 'Naked' TLS symbol references are never OK,
2798 non-TLS symbols are OK iff we are non-PIC. */
2799 if (SYMBOL_REF_TLS_MODEL (x))
2800 return true;
2801 else
2802 return flag_pic != 0;
2803
2804 case CONST:
2805 return sparc_cannot_force_const_mem (XEXP (x, 0));
2806 case PLUS:
2807 case MINUS:
2808 return sparc_cannot_force_const_mem (XEXP (x, 0))
2809 || sparc_cannot_force_const_mem (XEXP (x, 1));
2810 case UNSPEC:
2811 return true;
2812 default:
f5f7d171 2813 gcc_unreachable ();
5751a10b
JJ		 2814 }
2815}
2816\f
5e77eb53
EB		 2817/* PIC support. */
2818static GTY(()) char pic_helper_symbol_name[256];
2819static GTY(()) rtx pic_helper_symbol;
2820static GTY(()) bool pic_helper_emitted_p = false;
e2500fed 2821static GTY(()) rtx global_offset_table;
bc961ed7 2822
e0d80184 2823/* Ensure that we are not using patterns that are not OK with PIC. */
795068a4 2824
e0d80184 2825int
fc27d102 2826check_pic (int i)
e0d80184
DM		 2827{
2828 switch (flag_pic)
ab835497 2829 {
e0d80184 2830 case 1:
f5f7d171
JM		 2831 gcc_assert (GET_CODE (recog_data.operand[i]) != SYMBOL_REF
2832 && (GET_CODE (recog_data.operand[i]) != CONST
2833 || (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
2834 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
2835 == global_offset_table)
2836 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
2837 == CONST))));
e0d80184
DM		 2838 case 2:
2839 default:
2840 return 1;
ab835497 2841 }
ab835497 2842}
795068a4 2843
e0d80184
DM		 2844/* Return true if X is an address which needs a temporary register when
2845 reloaded while generating PIC code. */
795068a4 2846
e0d80184 2847int
fc27d102 2848pic_address_needs_scratch (rtx x)
795068a4 2849{
e0d80184
DM		 2850 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2851 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2852 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2853 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2854 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2855 return 1;
795068a4 2856
e0d80184
DM		 2857 return 0;
2858}
795068a4 2859
5751a10b
JJ		 2860/* Determine if a given RTX is a valid constant. We already know this
2861 satisfies CONSTANT_P. */
2862
2863bool
2864legitimate_constant_p (rtx x)
2865{
2866 rtx inner;
2867
2868 switch (GET_CODE (x))
2869 {
2870 case SYMBOL_REF:
2871 /* TLS symbols are not constant. */
2872 if (SYMBOL_REF_TLS_MODEL (x))
2873 return false;
2874 break;
2875
2876 case CONST:
2877 inner = XEXP (x, 0);
2878
2879 /* Offsets of TLS symbols are never valid.
2880 Discourage CSE from creating them. */
2881 if (GET_CODE (inner) == PLUS
38fc66ba 2882 && SPARC_SYMBOL_REF_TLS_P (XEXP (inner, 0)))
5751a10b
JJ		 2883 return false;
2884 break;
2885
2886 case CONST_DOUBLE:
2887 if (GET_MODE (x) == VOIDmode)
2888 return true;
2889
2890 /* Floating point constants are generally not ok.
2891 The only exception is 0.0 in VIS. */
2892 if (TARGET_VIS
bea5071f
EB		 2893 && SCALAR_FLOAT_MODE_P (GET_MODE (x))
2894 && const_zero_operand (x, GET_MODE (x)))
2895 return true;
2896
2897 return false;
2898
2899 case CONST_VECTOR:
2900 /* Vector constants are generally not ok.
2901 The only exception is 0 in VIS. */
2902 if (TARGET_VIS
0e5d569c 2903 && const_zero_operand (x, GET_MODE (x)))
5751a10b
JJ		 2904 return true;
2905
2906 return false;
2907
2908 default:
2909 break;
2910 }
2911
2912 return true;
2913}
2914
2915/* Determine if a given RTX is a valid constant address. */
2916
2917bool
2918constant_address_p (rtx x)
2919{
2920 switch (GET_CODE (x))
2921 {
2922 case LABEL_REF:
2923 case CONST_INT:
2924 case HIGH:
2925 return true;
2926
2927 case CONST:
2928 if (flag_pic && pic_address_needs_scratch (x))
2929 return false;
2930 return legitimate_constant_p (x);
2931
2932 case SYMBOL_REF:
2933 return !flag_pic && legitimate_constant_p (x);
2934
2935 default:
2936 return false;
2937 }
2938}
2939
2940/* Nonzero if the constant value X is a legitimate general operand
2941 when generating PIC code. It is given that flag_pic is on and
2942 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
2943
2944bool
2945legitimate_pic_operand_p (rtx x)
2946{
2947 if (pic_address_needs_scratch (x))
2948 return false;
38fc66ba 2949 if (SPARC_SYMBOL_REF_TLS_P (x)
5751a10b
JJ		 2950 || (GET_CODE (x) == CONST
2951 && GET_CODE (XEXP (x, 0)) == PLUS
38fc66ba 2952 && SPARC_SYMBOL_REF_TLS_P (XEXP (XEXP (x, 0), 0))))
5751a10b
JJ		 2953 return false;
2954 return true;
2955}
2956
2957/* Return nonzero if ADDR is a valid memory address.
2958 STRICT specifies whether strict register checking applies. */
2959
2960int
2961legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
2962{
f1b259d5 2963 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
5751a10b
JJ		 2964
2965 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
2966 rs1 = addr;
2967 else if (GET_CODE (addr) == PLUS)
2968 {
2969 rs1 = XEXP (addr, 0);
2970 rs2 = XEXP (addr, 1);
2971
2972 /* Canonicalize. REG comes first, if there are no regs,
2973 LO_SUM comes first. */
2974 if (!REG_P (rs1)
2975 && GET_CODE (rs1) != SUBREG
2976 && (REG_P (rs2)
2977 || GET_CODE (rs2) == SUBREG
2978 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
2979 {
2980 rs1 = XEXP (addr, 1);
2981 rs2 = XEXP (addr, 0);
2982 }
2983
2984 if ((flag_pic == 1
2985 && rs1 == pic_offset_table_rtx
2986 && !REG_P (rs2)
2987 && GET_CODE (rs2) != SUBREG
2988 && GET_CODE (rs2) != LO_SUM
2989 && GET_CODE (rs2) != MEM
38fc66ba 2990 && ! SPARC_SYMBOL_REF_TLS_P (rs2)
5751a10b
JJ		 2991 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
2992 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
2993 || ((REG_P (rs1)
2994 || GET_CODE (rs1) == SUBREG)
2995 && RTX_OK_FOR_OFFSET_P (rs2)))
2996 {
2997 imm1 = rs2;
2998 rs2 = NULL;
2999 }
3000 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3001 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3002 {
39ba2f92
EB		 3003 /* We prohibit REG + REG for TFmode when there are no quad move insns
3004 and we consequently need to split. We do this because REG+REG
3005 is not an offsettable address. If we get the situation in reload
5751a10b
JJ		 3006 where source and destination of a movtf pattern are both MEMs with
3007 REG+REG address, then only one of them gets converted to an
39ba2f92 3008 offsettable address. */
5751a10b 3009 if (mode == TFmode
39ba2f92 3010 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
5751a10b
JJ		 3011 return 0;
3012
3013 /* We prohibit REG + REG on ARCH32 if not optimizing for
3014 DFmode/DImode because then mem_min_alignment is likely to be zero
3015 after reload and the forced split would lack a matching splitter
3016 pattern. */
3017 if (TARGET_ARCH32 && !optimize
3018 && (mode == DFmode || mode == DImode))
3019 return 0;
3020 }
3021 else if (USE_AS_OFFSETABLE_LO10
3022 && GET_CODE (rs1) == LO_SUM
3023 && TARGET_ARCH64
3024 && ! TARGET_CM_MEDMID
3025 && RTX_OK_FOR_OLO10_P (rs2))
3026 {
5751a10b
JJ		 3027 rs2 = NULL;
3028 imm1 = XEXP (rs1, 1);
3029 rs1 = XEXP (rs1, 0);
38fc66ba 3030 if (! CONSTANT_P (imm1) || SPARC_SYMBOL_REF_TLS_P (rs1))
5751a10b
JJ		 3031 return 0;
3032 }
3033 }
3034 else if (GET_CODE (addr) == LO_SUM)
3035 {
3036 rs1 = XEXP (addr, 0);
3037 imm1 = XEXP (addr, 1);
3038
38fc66ba 3039 if (! CONSTANT_P (imm1) || SPARC_SYMBOL_REF_TLS_P (rs1))
5751a10b
JJ		 3040 return 0;
3041
f1b259d5
EB		 3042 /* We can't allow TFmode in 32-bit mode, because an offset greater
3043 than the alignment (8) may cause the LO_SUM to overflow. */
d24088cc 3044 if (mode == TFmode && TARGET_ARCH32)
f1b259d5 3045 return 0;
5751a10b
JJ		 3046 }
3047 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3048 return 1;
3049 else
3050 return 0;
3051
3052 if (GET_CODE (rs1) == SUBREG)
3053 rs1 = SUBREG_REG (rs1);
3054 if (!REG_P (rs1))
3055 return 0;
3056
3057 if (rs2)
3058 {
3059 if (GET_CODE (rs2) == SUBREG)
3060 rs2 = SUBREG_REG (rs2);
3061 if (!REG_P (rs2))
3062 return 0;
3063 }
3064
3065 if (strict)
3066 {
3067 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3068 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3069 return 0;
3070 }
3071 else
3072 {
3073 if ((REGNO (rs1) >= 32
3074 && REGNO (rs1) != FRAME_POINTER_REGNUM
3075 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3076 || (rs2
3077 && (REGNO (rs2) >= 32
3078 && REGNO (rs2) != FRAME_POINTER_REGNUM
3079 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3080 return 0;
3081 }
3082 return 1;
3083}
3084
3085/* Construct the SYMBOL_REF for the tls_get_offset function. */
3086
3087static GTY(()) rtx sparc_tls_symbol;
38fc66ba 3088
5751a10b
JJ		 3089static rtx
3090sparc_tls_get_addr (void)
3091{
3092 if (!sparc_tls_symbol)
3093 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3094
3095 return sparc_tls_symbol;
3096}
3097
3098static rtx
3099sparc_tls_got (void)
3100{
3101 rtx temp;
3102 if (flag_pic)
3103 {
e3b5732b 3104 crtl->uses_pic_offset_table = 1;
5751a10b
JJ		 3105 return pic_offset_table_rtx;
3106 }
3107
3108 if (!global_offset_table)
3109 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3110 temp = gen_reg_rtx (Pmode);
3111 emit_move_insn (temp, global_offset_table);
3112 return temp;
3113}
3114
38fc66ba
EB		 3115/* Return 1 if *X is a thread-local symbol. */
3116
3117static int
3118sparc_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3119{
3120 return SPARC_SYMBOL_REF_TLS_P (*x);
3121}
3122
3123/* Return 1 if X contains a thread-local symbol. */
3124
3125bool
3126sparc_tls_referenced_p (rtx x)
3127{
3128 if (!TARGET_HAVE_TLS)
3129 return false;
3130
3131 return for_each_rtx (&x, &sparc_tls_symbol_ref_1, 0);
3132}
5751a10b
JJ		 3133
3134/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3135 this (thread-local) address. */
3136
3137rtx
3138legitimize_tls_address (rtx addr)
3139{
3140 rtx temp1, temp2, temp3, ret, o0, got, insn;
3141
b3a13419 3142 gcc_assert (can_create_pseudo_p ());
5751a10b
JJ		 3143
3144 if (GET_CODE (addr) == SYMBOL_REF)
3145 switch (SYMBOL_REF_TLS_MODEL (addr))
3146 {
3147 case TLS_MODEL_GLOBAL_DYNAMIC:
3148 start_sequence ();
3149 temp1 = gen_reg_rtx (SImode);
3150 temp2 = gen_reg_rtx (SImode);
3151 ret = gen_reg_rtx (Pmode);
3152 o0 = gen_rtx_REG (Pmode, 8);
3153 got = sparc_tls_got ();
3154 emit_insn (gen_tgd_hi22 (temp1, addr));
3155 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3156 if (TARGET_ARCH32)
3157 {
3158 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3159 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3160 addr, const1_rtx));
3161 }
3162 else
3163 {
3164 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3165 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3166 addr, const1_rtx));
3167 }
3168 CALL_INSN_FUNCTION_USAGE (insn)
3169 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3170 CALL_INSN_FUNCTION_USAGE (insn));
3171 insn = get_insns ();
3172 end_sequence ();
3173 emit_libcall_block (insn, ret, o0, addr);
3174 break;
3175
3176 case TLS_MODEL_LOCAL_DYNAMIC:
3177 start_sequence ();
3178 temp1 = gen_reg_rtx (SImode);
3179 temp2 = gen_reg_rtx (SImode);
3180 temp3 = gen_reg_rtx (Pmode);
3181 ret = gen_reg_rtx (Pmode);
3182 o0 = gen_rtx_REG (Pmode, 8);
3183 got = sparc_tls_got ();
3184 emit_insn (gen_tldm_hi22 (temp1));
3185 emit_insn (gen_tldm_lo10 (temp2, temp1));
3186 if (TARGET_ARCH32)
3187 {
3188 emit_insn (gen_tldm_add32 (o0, got, temp2));
3189 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3190 const1_rtx));
3191 }
3192 else
3193 {
3194 emit_insn (gen_tldm_add64 (o0, got, temp2));
3195 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3196 const1_rtx));
3197 }
3198 CALL_INSN_FUNCTION_USAGE (insn)
3199 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3200 CALL_INSN_FUNCTION_USAGE (insn));
3201 insn = get_insns ();
3202 end_sequence ();
3203 emit_libcall_block (insn, temp3, o0,
3204 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3205 UNSPEC_TLSLD_BASE));
3206 temp1 = gen_reg_rtx (SImode);
3207 temp2 = gen_reg_rtx (SImode);
3208 emit_insn (gen_tldo_hix22 (temp1, addr));
3209 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3210 if (TARGET_ARCH32)
3211 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3212 else
3213 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3214 break;
3215
3216 case TLS_MODEL_INITIAL_EXEC:
3217 temp1 = gen_reg_rtx (SImode);
3218 temp2 = gen_reg_rtx (SImode);
3219 temp3 = gen_reg_rtx (Pmode);
3220 got = sparc_tls_got ();
3221 emit_insn (gen_tie_hi22 (temp1, addr));
3222 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3223 if (TARGET_ARCH32)
3224 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3225 else
3226 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3227 if (TARGET_SUN_TLS)
3228 {
3229 ret = gen_reg_rtx (Pmode);
3230 if (TARGET_ARCH32)
3231 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3232 temp3, addr));
3233 else
3234 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3235 temp3, addr));
3236 }
3237 else
3238 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3239 break;
3240
3241 case TLS_MODEL_LOCAL_EXEC:
3242 temp1 = gen_reg_rtx (Pmode);
3243 temp2 = gen_reg_rtx (Pmode);
3244 if (TARGET_ARCH32)
3245 {
3246 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3247 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3248 }
3249 else
3250 {
3251 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3252 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3253 }
3254 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3255 break;
3256
3257 default:
f5f7d171 3258 gcc_unreachable ();
5751a10b
JJ		 3259 }
3260
3261 else
f5f7d171 3262 gcc_unreachable (); /* for now ... */
5751a10b
JJ		 3263
3264 return ret;
3265}
3266
3267
e0d80184
DM		 3268/* Legitimize PIC addresses. If the address is already position-independent,
3269 we return ORIG. Newly generated position-independent addresses go into a
88cad84b 3270 reg. This is REG if nonzero, otherwise we allocate register(s) as
e0d80184 3271 necessary. */
795068a4 3272
e0d80184 3273rtx
fc27d102
KG		 3274legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3275 rtx reg)
e0d80184 3276{
1910440e
RS		 3277 if (GET_CODE (orig) == SYMBOL_REF
3278 /* See the comment in sparc_expand_move. */
3279 || (TARGET_VXWORKS_RTP && GET_CODE (orig) == LABEL_REF))
82d6b402 3280 {
e0d80184
DM		 3281 rtx pic_ref, address;
3282 rtx insn;
82d6b402 3283
e0d80184 3284 if (reg == 0)
82d6b402 3285 {
f5f7d171
JM		 3286 gcc_assert (! reload_in_progress && ! reload_completed);
3287 reg = gen_reg_rtx (Pmode);
82d6b402 3288 }
795068a4 3289
e0d80184 3290 if (flag_pic == 2)
4fb4e4b8 3291 {
e0d80184
DM		 3292 /* If not during reload, allocate another temp reg here for loading
3293 in the address, so that these instructions can be optimized
3294 properly. */
3295 rtx temp_reg = ((reload_in_progress || reload_completed)
3296 ? reg : gen_reg_rtx (Pmode));
3297
3298 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3299 won't get confused into thinking that these two instructions
3300 are loading in the true address of the symbol. If in the
3301 future a PIC rtx exists, that should be used instead. */
bea5071f 3302 if (TARGET_ARCH64)
be3f1ff5 3303 {
bea5071f
EB		 3304 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3305 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
be3f1ff5
DM		 3306 }
3307 else
3308 {
bea5071f
EB		 3309 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3310 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
be3f1ff5 3311 }
e0d80184 3312 address = temp_reg;
4fb4e4b8
DE		 3313 }
3314 else
e0d80184
DM		 3315 address = orig;
3316
542a8afa
RH		 3317 pic_ref = gen_const_mem (Pmode,
3318 gen_rtx_PLUS (Pmode,
3319 pic_offset_table_rtx, address));
e3b5732b 3320 crtl->uses_pic_offset_table = 1;
e0d80184
DM		 3321 insn = emit_move_insn (reg, pic_ref);
3322 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3323 by loop. */
bd94cb6e 3324 set_unique_reg_note (insn, REG_EQUAL, orig);
e0d80184 3325 return reg;
795068a4 3326 }
e0d80184 3327 else if (GET_CODE (orig) == CONST)
795068a4 3328 {
e0d80184 3329 rtx base, offset;
795068a4 3330
e0d80184
DM		 3331 if (GET_CODE (XEXP (orig, 0)) == PLUS
3332 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3333 return orig;
82d6b402 3334
e0d80184 3335 if (reg == 0)
4fb4e4b8 3336 {
f5f7d171
JM		 3337 gcc_assert (! reload_in_progress && ! reload_completed);
3338 reg = gen_reg_rtx (Pmode);
4fb4e4b8 3339 }
e0d80184 3340
f5f7d171
JM		 3341 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3342 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3343 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3344 base == reg ? 0 : reg);
61a66555 3345
e0d80184
DM		 3346 if (GET_CODE (offset) == CONST_INT)
3347 {
3348 if (SMALL_INT (offset))
ed8908e7 3349 return plus_constant (base, INTVAL (offset));
e0d80184
DM		 3350 else if (! reload_in_progress && ! reload_completed)
3351 offset = force_reg (Pmode, offset);
3352 else
3353 /* If we reach here, then something is seriously wrong. */
f5f7d171 3354 gcc_unreachable ();
e0d80184
DM		 3355 }
3356 return gen_rtx_PLUS (Pmode, base, offset);
795068a4 3357 }
e0d80184
DM		 3358 else if (GET_CODE (orig) == LABEL_REF)
3359 /* ??? Why do we do this? */
3360 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3361 the register is live instead, in case it is eliminated. */
e3b5732b 3362 crtl->uses_pic_offset_table = 1;
795068a4 3363
e0d80184
DM		 3364 return orig;
3365}
795068a4 3366
5751a10b
JJ		 3367/* Try machine-dependent ways of modifying an illegitimate address X
3368 to be legitimate. If we find one, return the new, valid address.
3369
3370 OLDX is the address as it was before break_out_memory_refs was called.
3371 In some cases it is useful to look at this to decide what needs to be done.
3372
3373 MODE is the mode of the operand pointed to by X. */
3374
3375rtx
3376legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3377{
3378 rtx orig_x = x;
3379
3380 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3381 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3382 force_operand (XEXP (x, 0), NULL_RTX));
3383 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3384 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3385 force_operand (XEXP (x, 1), NULL_RTX));
3386 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3387 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3388 XEXP (x, 1));
3389 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3390 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3391 force_operand (XEXP (x, 1), NULL_RTX));
3392
3393 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3394 return x;
3395
38fc66ba 3396 if (SPARC_SYMBOL_REF_TLS_P (x))
5751a10b
JJ		 3397 x = legitimize_tls_address (x);
3398 else if (flag_pic)
3399 x = legitimize_pic_address (x, mode, 0);
3400 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3401 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3402 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3403 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3404 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3405 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3406 else if (GET_CODE (x) == SYMBOL_REF
3407 || GET_CODE (x) == CONST
3408 || GET_CODE (x) == LABEL_REF)
3409 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3410 return x;
3411}
3412
5e77eb53 3413/* Emit the special PIC helper function. */
795068a4 3414
9ac617d4 3415static void
5e77eb53 3416emit_pic_helper (void)
e0d80184 3417{
5e77eb53
EB		 3418 const char *pic_name = reg_names[REGNO (pic_offset_table_rtx)];
3419 int align;
4fb4e4b8 3420
d6b5193b 3421 switch_to_section (text_section);
82d6b402 3422
5e77eb53
EB		 3423 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3424 if (align > 0)
3425 ASM_OUTPUT_ALIGN (asm_out_file, align);
3426 ASM_OUTPUT_LABEL (asm_out_file, pic_helper_symbol_name);
3427 if (flag_delayed_branch)
3428 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
3429 pic_name, pic_name);
3430 else
3431 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
3432 pic_name, pic_name);
d676da68 3433
5e77eb53
EB		 3434 pic_helper_emitted_p = true;
3435}
3436
3437/* Emit code to load the PIC register. */
3438
3439static void
3440load_pic_register (bool delay_pic_helper)
3441{
3442 int orig_flag_pic = flag_pic;
3443
1910440e
RS		 3444 if (TARGET_VXWORKS_RTP)
3445 {
3446 emit_insn (gen_vxworks_load_got ());
c41c1387 3447 emit_use (pic_offset_table_rtx);
1910440e
RS		 3448 return;
3449 }
3450
5e77eb53
EB		 3451 /* If we haven't initialized the special PIC symbols, do so now. */
3452 if (!pic_helper_symbol_name[0])
3453 {
3454 ASM_GENERATE_INTERNAL_LABEL (pic_helper_symbol_name, "LADDPC", 0);
3455 pic_helper_symbol = gen_rtx_SYMBOL_REF (Pmode, pic_helper_symbol_name);
3456 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
e0d80184 3457 }
82d6b402 3458
5e77eb53
EB		 3459 /* If we haven't emitted the special PIC helper function, do so now unless
3460 we are requested to delay it. */
3461 if (!delay_pic_helper && !pic_helper_emitted_p)
3462 emit_pic_helper ();
82d6b402 3463
ef573211 3464 flag_pic = 0;
eb7a7903
EB		 3465 if (TARGET_ARCH64)
3466 emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx, global_offset_table,
5e77eb53 3467 pic_helper_symbol));
eb7a7903
EB		 3468 else
3469 emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx, global_offset_table,
5e77eb53 3470 pic_helper_symbol));
e0d80184 3471 flag_pic = orig_flag_pic;
82d6b402 3472
e0d80184
DM		 3473 /* Need to emit this whether or not we obey regdecls,
3474 since setjmp/longjmp can cause life info to screw up.
3475 ??? In the case where we don't obey regdecls, this is not sufficient
3476 since we may not fall out the bottom. */
c41c1387 3477 emit_use (pic_offset_table_rtx);
795068a4 3478}
1910440e
RS		 3479
3480/* Emit a call instruction with the pattern given by PAT. ADDR is the
3481 address of the call target. */
3482
3483void
3484sparc_emit_call_insn (rtx pat, rtx addr)
3485{
3486 rtx insn;
3487
3488 insn = emit_call_insn (pat);
3489
3490 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
3491 if (TARGET_VXWORKS_RTP
3492 && flag_pic
3493 && GET_CODE (addr) == SYMBOL_REF
3494 && (SYMBOL_REF_DECL (addr)
3495 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
3496 : !SYMBOL_REF_LOCAL_P (addr)))
3497 {
3498 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
e3b5732b 3499 crtl->uses_pic_offset_table = 1;
1910440e
RS		 3500 }
3501}
ab835497 3502\f
e0d80184 3503/* Return 1 if RTX is a MEM which is known to be aligned to at
7a31a340 3504 least a DESIRED byte boundary. */
a3ee5899 3505
e0d80184 3506int
fc27d102 3507mem_min_alignment (rtx mem, int desired)
ab835497 3508{
e0d80184
DM		 3509 rtx addr, base, offset;
3510
3511 /* If it's not a MEM we can't accept it. */
3512 if (GET_CODE (mem) != MEM)
3513 return 0;
3514
167a1354 3515 /* Obviously... */
0f95e914
EB		 3516 if (!TARGET_UNALIGNED_DOUBLES
3517 && MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired)
167a1354
EB		 3518 return 1;
3519
3520 /* ??? The rest of the function predates MEM_ALIGN so
3521 there is probably a bit of redundancy. */
e0d80184
DM		 3522 addr = XEXP (mem, 0);
3523 base = offset = NULL_RTX;
3524 if (GET_CODE (addr) == PLUS)
ab835497 3525 {
e0d80184 3526 if (GET_CODE (XEXP (addr, 0)) == REG)
61a55e8b 3527 {
e0d80184
DM		 3528 base = XEXP (addr, 0);
3529
3530 /* What we are saying here is that if the base
3531 REG is aligned properly, the compiler will make
3532 sure any REG based index upon it will be so
3533 as well. */
3534 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3535 offset = XEXP (addr, 1);
61a55e8b 3536 else
e0d80184 3537 offset = const0_rtx;
61a55e8b 3538 }
ab835497 3539 }
e0d80184 3540 else if (GET_CODE (addr) == REG)
ab835497 3541 {
e0d80184
DM		 3542 base = addr;
3543 offset = const0_rtx;
ab835497 3544 }
82d6b402 3545
e0d80184 3546 if (base != NULL_RTX)
795068a4 3547 {
e0d80184
DM		 3548 int regno = REGNO (base);
3549
563c12b0 3550 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
61a55e8b 3551 {
e0d80184
DM		 3552 /* Check if the compiler has recorded some information
3553 about the alignment of the base REG. If reload has
021e2ecc
JJ		 3554 completed, we already matched with proper alignments.
3555 If not running global_alloc, reload might give us
3556 unaligned pointer to local stack though. */
bdb429a5
RK		 3557 if (((cfun != 0
3558 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
021e2ecc 3559 || (optimize && reload_completed))
bdb429a5 3560 && (INTVAL (offset) & (desired - 1)) == 0)
e0d80184 3561 return 1;
61a55e8b 3562 }
795068a4 3563 else
e0d80184
DM		 3564 {
3565 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3566 return 1;
3567 }
795068a4 3568 }
e0d80184
DM		 3569 else if (! TARGET_UNALIGNED_DOUBLES
3570 || CONSTANT_P (addr)
3571 || GET_CODE (addr) == LO_SUM)
795068a4 3572 {
e0d80184
DM		 3573 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3574 is true, in which case we can only assume that an access is aligned if
3575 it is to a constant address, or the address involves a LO_SUM. */
3576 return 1;
795068a4 3577 }
e0d80184
DM		 3578
3579 /* An obviously unaligned address. */
3580 return 0;
795068a4 3581}
e0d80184 3582
ab835497 3583\f
61a55e8b 3584/* Vectors to keep interesting information about registers where it can easily
01d3224a 3585 be got. We used to use the actual mode value as the bit number, but there
61a55e8b
DE		 3586 are more than 32 modes now. Instead we use two tables: one indexed by
3587 hard register number, and one indexed by mode. */
3588
3589/* The purpose of sparc_mode_class is to shrink the range of modes so that
a7b376ee 3590 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
61a55e8b
DE		 3591 mapped into one sparc_mode_class mode. */
3592
3593enum sparc_mode_class {
61a55e8b 3594 S_MODE, D_MODE, T_MODE, O_MODE,
c4ce6853
DE		 3595 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3596 CC_MODE, CCFP_MODE
61a55e8b 3597};
ab835497 3598
61a55e8b
DE		 3599/* Modes for single-word and smaller quantities. */
3600#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3601
3602/* Modes for double-word and smaller quantities. */
3603#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3604
3605/* Modes for quad-word and smaller quantities. */
3606#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
ab835497 3607
d0cee9ba
JJ		 3608/* Modes for 8-word and smaller quantities. */
3609#define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3610
1e4eb8d1
JW		 3611/* Modes for single-float quantities. We must allow any single word or
3612 smaller quantity. This is because the fix/float conversion instructions
3613 take integer inputs/outputs from the float registers. */
3614#define SF_MODES (S_MODES)
ab835497 3615
61a55e8b
DE		 3616/* Modes for double-float and smaller quantities. */
3617#define DF_MODES (S_MODES | D_MODES)
3618
61a55e8b 3619/* Modes for double-float only quantities. */
38875aba 3620#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
ab835497 3621
61a55e8b
DE		 3622/* Modes for quad-float only quantities. */
3623#define TF_ONLY_MODES (1 << (int) TF_MODE)
3624
3625/* Modes for quad-float and smaller quantities. */
3626#define TF_MODES (DF_MODES | TF_ONLY_MODES)
3627
d0cee9ba
JJ		 3628/* Modes for quad-float and double-float quantities. */
3629#define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3630
3631/* Modes for quad-float pair only quantities. */
3632#define OF_ONLY_MODES (1 << (int) OF_MODE)
3633
3634/* Modes for quad-float pairs and smaller quantities. */
3635#define OF_MODES (TF_MODES | OF_ONLY_MODES)
3636
3637#define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
ab835497 3638
c4ce6853
DE		 3639/* Modes for condition codes. */
3640#define CC_MODES (1 << (int) CC_MODE)
3641#define CCFP_MODES (1 << (int) CCFP_MODE)
3642
ab835497
RK		 3643/* Value is 1 if register/mode pair is acceptable on sparc.
3644 The funny mixture of D and T modes is because integer operations
3645 do not specially operate on tetra quantities, so non-quad-aligned
3646 registers can hold quadword quantities (except %o4 and %i4 because
c4ce6853 3647 they cross fixed registers). */
ab835497 3648
61a55e8b 3649/* This points to either the 32 bit or the 64 bit version. */
0b5826ac 3650const int *hard_regno_mode_classes;
61a55e8b 3651
0b5826ac 3652static const int hard_32bit_mode_classes[] = {
c4ce6853 3653 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
ab835497
RK		 3654 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3655 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3656 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3657
d0cee9ba
JJ		 3658 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3659 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3660 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3661 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
a9e27770
DE		 3662
3663 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3664 and none can hold SFmode/SImode values. */
d0cee9ba
JJ		 3665 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3666 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3667 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3668 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
a9e27770
DE		 3669
3670 /* %fcc[0123] */
c4ce6853
DE		 3671 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3672
3673 /* %icc */
3674 CC_MODES
61a55e8b
DE		 3675};
3676
0b5826ac 3677static const int hard_64bit_mode_classes[] = {
c4ce6853 3678 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
d0cee9ba 3679 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
61a55e8b 3680 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
d0cee9ba 3681 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
61a55e8b 3682
d0cee9ba
JJ		 3683 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3684 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3685 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3686 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
61a55e8b 3687
a9e27770 3688 /* FP regs f32 to f63. Only the even numbered registers actually exist,
61a55e8b 3689 and none can hold SFmode/SImode values. */
d0cee9ba
JJ		 3690 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3691 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3692 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3693 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
61a55e8b
DE		 3694
3695 /* %fcc[0123] */
c4ce6853
DE		 3696 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3697
3698 /* %icc */
3699 CC_MODES
61a55e8b
DE		 3700};
3701
3702int sparc_mode_class [NUM_MACHINE_MODES];
3703
c4ce6853
DE		 3704enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3705
61a55e8b 3706static void
fc27d102 3707sparc_init_modes (void)
61a55e8b
DE		 3708{
3709 int i;
3710
61a55e8b
DE		 3711 for (i = 0; i < NUM_MACHINE_MODES; i++)
3712 {
3713 switch (GET_MODE_CLASS (i))
3714 {
3715 case MODE_INT:
3716 case MODE_PARTIAL_INT:
3717 case MODE_COMPLEX_INT:
3718 if (GET_MODE_SIZE (i) <= 4)
3719 sparc_mode_class[i] = 1 << (int) S_MODE;
3720 else if (GET_MODE_SIZE (i) == 8)
3721 sparc_mode_class[i] = 1 << (int) D_MODE;
3722 else if (GET_MODE_SIZE (i) == 16)
3723 sparc_mode_class[i] = 1 << (int) T_MODE;
3724 else if (GET_MODE_SIZE (i) == 32)
3725 sparc_mode_class[i] = 1 << (int) O_MODE;
3726 else
3727 sparc_mode_class[i] = 0;
3728 break;
c75d6010
JM		 3729 case MODE_VECTOR_INT:
3730 if (GET_MODE_SIZE (i) <= 4)
3731 sparc_mode_class[i] = 1 << (int)SF_MODE;
3732 else if (GET_MODE_SIZE (i) == 8)
3733 sparc_mode_class[i] = 1 << (int)DF_MODE;
3734 break;
61a55e8b
DE		 3735 case MODE_FLOAT:
3736 case MODE_COMPLEX_FLOAT:
3737 if (GET_MODE_SIZE (i) <= 4)
3738 sparc_mode_class[i] = 1 << (int) SF_MODE;
3739 else if (GET_MODE_SIZE (i) == 8)
3740 sparc_mode_class[i] = 1 << (int) DF_MODE;
3741 else if (GET_MODE_SIZE (i) == 16)
3742 sparc_mode_class[i] = 1 << (int) TF_MODE;
3743 else if (GET_MODE_SIZE (i) == 32)
3744 sparc_mode_class[i] = 1 << (int) OF_MODE;
3745 else
3746 sparc_mode_class[i] = 0;
3747 break;
3748 case MODE_CC:
61a55e8b
DE		 3749 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3750 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
61a55e8b 3751 else
94134f42
ZW		 3752 sparc_mode_class[i] = 1 << (int) CC_MODE;
3753 break;
3754 default:
3755 sparc_mode_class[i] = 0;
61a55e8b
DE		 3756 break;
3757 }
3758 }
3759
a9e27770 3760 if (TARGET_ARCH64)
61a55e8b
DE		 3761 hard_regno_mode_classes = hard_64bit_mode_classes;
3762 else
3763 hard_regno_mode_classes = hard_32bit_mode_classes;
c4ce6853
DE		 3764
3765 /* Initialize the array used by REGNO_REG_CLASS. */
3766 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3767 {
284d86e9
JC		 3768 if (i < 16 && TARGET_V8PLUS)
3769 sparc_regno_reg_class[i] = I64_REGS;
563c12b0 3770 else if (i < 32 || i == FRAME_POINTER_REGNUM)
c4ce6853
DE		 3771 sparc_regno_reg_class[i] = GENERAL_REGS;
3772 else if (i < 64)
3773 sparc_regno_reg_class[i] = FP_REGS;
3774 else if (i < 96)
3775 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3776 else if (i < 100)
3777 sparc_regno_reg_class[i] = FPCC_REGS;
3778 else
3779 sparc_regno_reg_class[i] = NO_REGS;
3780 }
61a55e8b 3781}
ab835497 3782\f
61a55e8b 3783/* Compute the frame size required by the function. This function is called
9ac617d4 3784 during the reload pass and also by sparc_expand_prologue. */
ab835497 3785
6a151f87 3786HOST_WIDE_INT
9ac617d4 3787sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p)
ab835497 3788{
38173d38 3789 int outgoing_args_size = (crtl->outgoing_args_size
4fb4e4b8 3790 + REG_PARM_STACK_SPACE (current_function_decl));
9ac617d4
EB		 3791 int n_regs = 0; /* N_REGS is the number of 4-byte regs saved thus far. */
3792 int i;
61a55e8b 3793
33074e5f
RH		 3794 if (TARGET_ARCH64)
3795 {
3796 for (i = 0; i < 8; i++)
6fb5fa3c 3797 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
33074e5f
RH		 3798 n_regs += 2;
3799 }
3800 else
3801 {
3802 for (i = 0; i < 8; i += 2)
6fb5fa3c
DB		 3803 if ((df_regs_ever_live_p (i) && ! call_used_regs[i])
3804 || (df_regs_ever_live_p (i+1) && ! call_used_regs[i+1]))
61a55e8b 3805 n_regs += 2;
ab835497
RK		 3806 }
3807
33074e5f 3808 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
6fb5fa3c
DB		 3809 if ((df_regs_ever_live_p (i) && ! call_used_regs[i])
3810 || (df_regs_ever_live_p (i+1) && ! call_used_regs[i+1]))
33074e5f
RH		 3811 n_regs += 2;
3812
9ac617d4 3813 /* Set up values for use in prologue and epilogue. */
61a55e8b 3814 num_gfregs = n_regs;
ab835497 3815
9ac617d4
EB		 3816 if (leaf_function_p
3817 && n_regs == 0
3818 && size == 0
38173d38 3819 && crtl->outgoing_args_size == 0)
9ac617d4 3820 actual_fsize = apparent_fsize = 0;
61a55e8b
DE		 3821 else
3822 {
225909c3
JS		 3823 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3824 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
61a55e8b
DE		 3825 apparent_fsize += n_regs * 4;
3826 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3827 }
ab835497
RK		 3828
3829 /* Make sure nothing can clobber our register windows.
3830 If a SAVE must be done, or there is a stack-local variable,
f8ece000 3831 the register window area must be allocated. */
9ac617d4 3832 if (! leaf_function_p || size > 0)
f8ece000 3833 actual_fsize += FIRST_PARM_OFFSET (current_function_decl);
ab835497 3834
61a55e8b
DE		 3835 return SPARC_STACK_ALIGN (actual_fsize);
3836}
3837
9ac617d4 3838/* Output any necessary .register pseudo-ops. */
61a55e8b 3839
9ac617d4
EB		 3840void
3841sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
61a55e8b 3842{
9ac617d4
EB		 3843#ifdef HAVE_AS_REGISTER_PSEUDO_OP
3844 int i;
6a151f87 3845
9ac617d4
EB		 3846 if (TARGET_ARCH32)
3847 return;
3848
3849 /* Check if %g[2367] were used without
3850 .register being printed for them already. */
3851 for (i = 2; i < 8; i++)
61a55e8b 3852 {
6fb5fa3c 3853 if (df_regs_ever_live_p (i)
9ac617d4
EB		 3854 && ! sparc_hard_reg_printed [i])
3855 {
3856 sparc_hard_reg_printed [i] = 1;
392e5756
JJ		 3857 /* %g7 is used as TLS base register, use #ignore
3858 for it instead of #scratch. */
3859 fprintf (file, "\t.register\t%%g%d, #%s\n", i,
3860 i == 7 ? "ignore" : "scratch");
9ac617d4
EB		 3861 }
3862 if (i == 3) i = 5;
61a55e8b 3863 }
6a151f87 3864#endif
9ac617d4 3865}
6a151f87 3866
9ac617d4
EB		 3867/* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
3868 as needed. LOW should be double-word aligned for 32-bit registers.
3869 Return the new OFFSET. */
6a151f87 3870
9ac617d4
EB		 3871#define SORR_SAVE 0
3872#define SORR_RESTORE 1
3873
3874static int
3875save_or_restore_regs (int low, int high, rtx base, int offset, int action)
3876{
3877 rtx mem, insn;
3878 int i;
3879
3880 if (TARGET_ARCH64 && high <= 32)
3881 {
3882 for (i = low; i < high; i++)
6a151f87 3883 {
6fb5fa3c 3884 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
9ac617d4
EB		 3885 {
3886 mem = gen_rtx_MEM (DImode, plus_constant (base, offset));
3887 set_mem_alias_set (mem, sparc_sr_alias_set);
3888 if (action == SORR_SAVE)
3889 {
3890 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
3891 RTX_FRAME_RELATED_P (insn) = 1;
3892 }
3893 else /* action == SORR_RESTORE */
3894 emit_move_insn (gen_rtx_REG (DImode, i), mem);
3895 offset += 8;
3896 }
6a151f87 3897 }
9ac617d4
EB		 3898 }
3899 else
3900 {
3901 for (i = low; i < high; i += 2)
6a151f87 3902 {
6fb5fa3c
DB		 3903 bool reg0 = df_regs_ever_live_p (i) && ! call_used_regs[i];
3904 bool reg1 = df_regs_ever_live_p (i+1) && ! call_used_regs[i+1];
9ac617d4
EB		 3905 enum machine_mode mode;
3906 int regno;
3907
3908 if (reg0 && reg1)
3909 {
3910 mode = i < 32 ? DImode : DFmode;
3911 regno = i;
3912 }
3913 else if (reg0)
3914 {
3915 mode = i < 32 ? SImode : SFmode;
3916 regno = i;
3917 }
3918 else if (reg1)
3919 {
3920 mode = i < 32 ? SImode : SFmode;
3921 regno = i + 1;
3922 offset += 4;
3923 }
3924 else
3925 continue;
3926
3927 mem = gen_rtx_MEM (mode, plus_constant (base, offset));
3928 set_mem_alias_set (mem, sparc_sr_alias_set);
3929 if (action == SORR_SAVE)
3930 {
3931 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
3932 RTX_FRAME_RELATED_P (insn) = 1;
3933 }
3934 else /* action == SORR_RESTORE */
3935 emit_move_insn (gen_rtx_REG (mode, regno), mem);
3936
3937 /* Always preserve double-word alignment. */
3938 offset = (offset + 7) & -8;
6a151f87 3939 }
6a151f87 3940 }
9ac617d4
EB		 3941
3942 return offset;
ab835497
RK		 3943}
3944
9ac617d4
EB		 3945/* Emit code to save call-saved registers. */
3946
3947static void
f8ece000 3948emit_save_or_restore_regs (int action)
1cb36a98 3949{
9ac617d4
EB		 3950 HOST_WIDE_INT offset;
3951 rtx base;
1cb36a98 3952
9ac617d4 3953 offset = frame_base_offset - apparent_fsize;
1cb36a98 3954
f8ece000 3955 if (offset < -4096 || offset + num_gfregs * 4 > 4095)
1cb36a98 3956 {
9ac617d4
EB		 3957 /* ??? This might be optimized a little as %g1 might already have a
3958 value close enough that a single add insn will do. */
3959 /* ??? Although, all of this is probably only a temporary fix
3960 because if %g1 can hold a function result, then
3961 sparc_expand_epilogue will lose (the result will be
3962 clobbered). */
3963 base = gen_rtx_REG (Pmode, 1);
3964 emit_move_insn (base, GEN_INT (offset));
3965 emit_insn (gen_rtx_SET (VOIDmode,
3966 base,
3967 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
3968 offset = 0;
1cb36a98 3969 }
9ac617d4
EB		 3970 else
3971 base = frame_base_reg;
3972
f8ece000
EB		 3973 offset = save_or_restore_regs (0, 8, base, offset, action);
3974 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, action);
9ac617d4 3975}
08c148a8 3976
e54c7471 3977/* Generate a save_register_window insn. */
08c148a8 3978
e54c7471
EB		 3979static rtx
3980gen_save_register_window (rtx increment)
08c148a8 3981{
9ac617d4 3982 if (TARGET_ARCH64)
e54c7471 3983 return gen_save_register_windowdi (increment);
9ac617d4 3984 else
e54c7471 3985 return gen_save_register_windowsi (increment);
08c148a8
NB		 3986}
3987
e54c7471 3988/* Generate an increment for the stack pointer. */
915f619f 3989
e54c7471
EB		 3990static rtx
3991gen_stack_pointer_inc (rtx increment)
ab835497 3992{
6deb0339
EB		 3993 return gen_rtx_SET (VOIDmode,
3994 stack_pointer_rtx,
3995 gen_rtx_PLUS (Pmode,
3996 stack_pointer_rtx,
3997 increment));
e54c7471
EB		 3998}
3999
4000/* Generate a decrement for the stack pointer. */
4001
4002static rtx
4003gen_stack_pointer_dec (rtx decrement)
4004{
6deb0339
EB		 4005 return gen_rtx_SET (VOIDmode,
4006 stack_pointer_rtx,
4007 gen_rtx_MINUS (Pmode,
4008 stack_pointer_rtx,
4009 decrement));
9ac617d4
EB		 4010}
4011
4012/* Expand the function prologue. The prologue is responsible for reserving
4013 storage for the frame, saving the call-saved registers and loading the
4014 PIC register if needed. */
4015
4016void
4017sparc_expand_prologue (void)
4018{
e54c7471
EB		 4019 rtx insn;
4020 int i;
4021
5be9b7a1
EB		 4022 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4023 on the final value of the flag means deferring the prologue/epilogue
4024 expansion until just before the second scheduling pass, which is too
4025 late to emit multiple epilogues or return insns.
4026
4027 Of course we are making the assumption that the value of the flag
4028 will not change between now and its final value. Of the three parts
4029 of the formula, only the last one can reasonably vary. Let's take a
4030 closer look, after assuming that the first two ones are set to true
4031 (otherwise the last value is effectively silenced).
4032
4033 If only_leaf_regs_used returns false, the global predicate will also
4034 be false so the actual frame size calculated below will be positive.
4035 As a consequence, the save_register_window insn will be emitted in
4036 the instruction stream; now this insn explicitly references %fp
4037 which is not a leaf register so only_leaf_regs_used will always
4038 return false subsequently.
4039
4040 If only_leaf_regs_used returns true, we hope that the subsequent
4041 optimization passes won't cause non-leaf registers to pop up. For
4042 example, the regrename pass has special provisions to not rename to
4043 non-leaf registers in a leaf function. */
4044 sparc_leaf_function_p
4045 = optimize > 0 && leaf_function_p () && only_leaf_regs_used ();
1cb36a98 4046
915f619f
JW		 4047 /* Need to use actual_fsize, since we are also allocating
4048 space for our callee (and our own register save area). */
5be9b7a1
EB		 4049 actual_fsize
4050 = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
4051
4052 /* Advertise that the data calculated just above are now valid. */
4053 sparc_prologue_data_valid_p = true;
ab835497 4054
5be9b7a1 4055 if (sparc_leaf_function_p)
61a55e8b 4056 {
9ac617d4 4057 frame_base_reg = stack_pointer_rtx;
61a55e8b
DE		 4058 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4059 }
4060 else
4061 {
9ac617d4 4062 frame_base_reg = hard_frame_pointer_rtx;
61a55e8b
DE		 4063 frame_base_offset = SPARC_STACK_BIAS;
4064 }
4065
915f619f
JW		 4066 if (actual_fsize == 0)
4067 /* do nothing. */ ;
5be9b7a1 4068 else if (sparc_leaf_function_p)
ab835497 4069 {
3592ea0d 4070 if (actual_fsize <= 4096)
e54c7471 4071 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-actual_fsize)));
3592ea0d 4072 else if (actual_fsize <= 8192)
915f619f 4073 {
e54c7471
EB		 4074 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4075 /* %sp is still the CFA register. */
4076 RTX_FRAME_RELATED_P (insn) = 1;
4077 insn
4078 = emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize)));
915f619f
JW		 4079 }
4080 else
4081 {
9ac617d4
EB		 4082 rtx reg = gen_rtx_REG (Pmode, 1);
4083 emit_move_insn (reg, GEN_INT (-actual_fsize));
e54c7471 4084 insn = emit_insn (gen_stack_pointer_inc (reg));
bbbbb16a
ILT		 4085 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4086 gen_stack_pointer_inc (GEN_INT (-actual_fsize)));
915f619f 4087 }
e54c7471
EB		 4088
4089 RTX_FRAME_RELATED_P (insn) = 1;
ab835497 4090 }
9ac617d4 4091 else
5f4241d5 4092 {
3592ea0d 4093 if (actual_fsize <= 4096)
e54c7471 4094 insn = emit_insn (gen_save_register_window (GEN_INT (-actual_fsize)));
3592ea0d
DE		 4095 else if (actual_fsize <= 8192)
4096 {
e54c7471
EB		 4097 insn = emit_insn (gen_save_register_window (GEN_INT (-4096)));
4098 /* %sp is not the CFA register anymore. */
4099 emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize)));
3592ea0d 4100 }
915f619f 4101 else
3592ea0d 4102 {
9ac617d4
EB		 4103 rtx reg = gen_rtx_REG (Pmode, 1);
4104 emit_move_insn (reg, GEN_INT (-actual_fsize));
e54c7471 4105 insn = emit_insn (gen_save_register_window (reg));
3592ea0d 4106 }
e54c7471
EB		 4107
4108 RTX_FRAME_RELATED_P (insn) = 1;
4109 for (i=0; i < XVECLEN (PATTERN (insn), 0); i++)
4110 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, i)) = 1;
ab835497
RK		 4111 }
4112
9ac617d4 4113 if (num_gfregs)
f8ece000 4114 emit_save_or_restore_regs (SORR_SAVE);
9ac617d4
EB		 4115
4116 /* Load the PIC register if needed. */
e3b5732b 4117 if (flag_pic && crtl->uses_pic_offset_table)
5e77eb53 4118 load_pic_register (false);
9ac617d4
EB		 4119}
4120
4121/* This function generates the assembly code for function entry, which boils
f8ece000 4122 down to emitting the necessary .register directives. */
9ac617d4
EB		 4123
4124static void
4125sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4126{
5be9b7a1 4127 /* Check that the assumption we made in sparc_expand_prologue is valid. */
f5f7d171 4128 gcc_assert (sparc_leaf_function_p == current_function_uses_only_leaf_regs);
9ac617d4
EB		 4129
4130 sparc_output_scratch_registers (file);
9ac617d4
EB		 4131}
4132
4133/* Expand the function epilogue, either normal or part of a sibcall.
4134 We emit all the instructions except the return or the call. */
c53aa195 4135
9ac617d4
EB		 4136void
4137sparc_expand_epilogue (void)
4138{
61a55e8b 4139 if (num_gfregs)
f8ece000 4140 emit_save_or_restore_regs (SORR_RESTORE);
ab835497 4141
9ac617d4
EB		 4142 if (actual_fsize == 0)
4143 /* do nothing. */ ;
5be9b7a1 4144 else if (sparc_leaf_function_p)
9ac617d4
EB		 4145 {
4146 if (actual_fsize <= 4096)
e54c7471 4147 emit_insn (gen_stack_pointer_dec (GEN_INT (- actual_fsize)));
9ac617d4 4148 else if (actual_fsize <= 8192)
61a55e8b 4149 {
e54c7471
EB		 4150 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4151 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - actual_fsize)));
61a55e8b 4152 }
ab835497 4153 else
61a55e8b 4154 {
9ac617d4
EB		 4155 rtx reg = gen_rtx_REG (Pmode, 1);
4156 emit_move_insn (reg, GEN_INT (-actual_fsize));
e54c7471 4157 emit_insn (gen_stack_pointer_dec (reg));
61a55e8b 4158 }
ab835497
RK		 4159 }
4160}
5be9b7a1
EB		 4161
4162/* Return true if it is appropriate to emit `return' instructions in the
4163 body of a function. */
4164
4165bool
4166sparc_can_use_return_insn_p (void)
4167{
4168 return sparc_prologue_data_valid_p
4169 && (actual_fsize == 0 || !sparc_leaf_function_p);
4170}
9ac617d4
EB		 4171
4172/* This function generates the assembly code for function exit. */
4173
4174static void
4175sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4176{
4177 /* If code does not drop into the epilogue, we have to still output
4178 a dummy nop for the sake of sane backtraces. Otherwise, if the
4179 last two instructions of a function were "call foo; dslot;" this
19525b57 4180 can make the return PC of foo (i.e. address of call instruction
9ac617d4 4181 plus 8) point to the first instruction in the next function. */
ab835497 4182
9ac617d4 4183 rtx insn, last_real_insn;
7d167afd 4184
9ac617d4
EB		 4185 insn = get_last_insn ();
4186
4187 last_real_insn = prev_real_insn (insn);
4188 if (last_real_insn
4189 && GET_CODE (last_real_insn) == INSN
4190 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4191 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4192
4193 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4194 fputs("\tnop\n", file);
4195
4196 sparc_output_deferred_case_vectors ();
4197}
4198
4199/* Output a 'restore' instruction. */
4200
7d167afd 4201static void
6244b14e 4202output_restore (rtx pat)
7d167afd 4203{
6244b14e 4204 rtx operands[3];
7d167afd 4205
6244b14e 4206 if (! pat)
7d167afd 4207 {
9ac617d4
EB		 4208 fputs ("\t restore\n", asm_out_file);
4209 return;
7d167afd
JJ		 4210 }
4211
f5f7d171 4212 gcc_assert (GET_CODE (pat) == SET);
08c148a8 4213
9ac617d4
EB		 4214 operands[0] = SET_DEST (pat);
4215 pat = SET_SRC (pat);
08c148a8 4216
9ac617d4
EB		 4217 switch (GET_CODE (pat))
4218 {
4219 case PLUS:
4220 operands[1] = XEXP (pat, 0);
4221 operands[2] = XEXP (pat, 1);
4222 output_asm_insn (" restore %r1, %2, %Y0", operands);
4223 break;
4224 case LO_SUM:
4225 operands[1] = XEXP (pat, 0);
4226 operands[2] = XEXP (pat, 1);
4227 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4228 break;
4229 case ASHIFT:
4230 operands[1] = XEXP (pat, 0);
f5f7d171 4231 gcc_assert (XEXP (pat, 1) == const1_rtx);
9ac617d4
EB		 4232 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4233 break;
4234 default:
4235 operands[1] = pat;
4236 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4237 break;
4238 }
08c148a8 4239}
9ac617d4
EB		 4240
4241/* Output a return. */
08c148a8 4242
9ac617d4
EB		 4243const char *
4244output_return (rtx insn)
ab835497 4245{
5be9b7a1 4246 if (sparc_leaf_function_p)
e48addee 4247 {
9ac617d4
EB		 4248 /* This is a leaf function so we don't have to bother restoring the
4249 register window, which frees us from dealing with the convoluted
4250 semantics of restore/return. We simply output the jump to the
4e5b002b 4251 return address and the insn in the delay slot (if any). */
7a31a340 4252
e3b5732b 4253 gcc_assert (! crtl->calls_eh_return);
ac59ed37 4254
4e5b002b 4255 return "jmp\t%%o7+%)%#";
bfd6bc60 4256 }
ab835497 4257 else
ab835497 4258 {
9ac617d4
EB		 4259 /* This is a regular function so we have to restore the register window.
4260 We may have a pending insn for the delay slot, which will be either
4261 combined with the 'restore' instruction or put in the delay slot of
4262 the 'return' instruction. */
4263
e3b5732b 4264 if (crtl->calls_eh_return)
33074e5f 4265 {
9ac617d4
EB		 4266 /* If the function uses __builtin_eh_return, the eh_return
4267 machinery occupies the delay slot. */
f5f7d171 4268 gcc_assert (! final_sequence);
ab835497 4269
951661a1
EB		 4270 if (! flag_delayed_branch)
4271 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file);
4272
9ac617d4
EB		 4273 if (TARGET_V9)
4274 fputs ("\treturn\t%i7+8\n", asm_out_file);
4275 else
4276 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file);
4277
951661a1
EB		 4278 if (flag_delayed_branch)
4279 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
4280 else
4281 fputs ("\t nop\n", asm_out_file);
33074e5f 4282 }
4e5b002b 4283 else if (final_sequence)
ef8200df 4284 {
9ac617d4
EB		 4285 rtx delay, pat;
4286
4287 delay = NEXT_INSN (insn);
f5f7d171 4288 gcc_assert (delay);
1150a841 4289
9ac617d4
EB		 4290 pat = PATTERN (delay);
4291
4292 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
33074e5f 4293 {
9ac617d4 4294 epilogue_renumber (&pat, 0);
4e5b002b 4295 return "return\t%%i7+%)%#";
1150a841 4296 }
33074e5f 4297 else
ab835497 4298 {
4e5b002b 4299 output_asm_insn ("jmp\t%%i7+%)", NULL);
6244b14e 4300 output_restore (pat);
4e5b002b
EB		 4301 PATTERN (delay) = gen_blockage ();
4302 INSN_CODE (delay) = -1;
ab835497 4303 }
ef8200df 4304 }
33074e5f 4305 else
9ac617d4
EB		 4306 {
4307 /* The delay slot is empty. */
4308 if (TARGET_V9)
4e5b002b 4309 return "return\t%%i7+%)\n\t nop";
951661a1 4310 else if (flag_delayed_branch)
4e5b002b 4311 return "jmp\t%%i7+%)\n\t restore";
951661a1 4312 else
4e5b002b 4313 return "restore\n\tjmp\t%%o7+%)\n\t nop";
9ac617d4 4314 }
6a151f87 4315 }
e0d80184 4316
9ac617d4 4317 return "";
ab835497 4318}
7d167afd
JJ		 4319
4320/* Output a sibling call. */
4321
4322const char *
fc27d102 4323output_sibcall (rtx insn, rtx call_operand)
7d167afd 4324{
9ac617d4 4325 rtx operands[1];
7d167afd 4326
f5f7d171 4327 gcc_assert (flag_delayed_branch);
951661a1 4328
7d167afd
JJ		 4329 operands[0] = call_operand;
4330
5be9b7a1 4331 if (sparc_leaf_function_p)
7d167afd 4332 {
9ac617d4
EB		 4333 /* This is a leaf function so we don't have to bother restoring the
4334 register window. We simply output the jump to the function and
4335 the insn in the delay slot (if any). */
7d167afd 4336
f5f7d171 4337 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence));
9ac617d4 4338
4e5b002b
EB		 4339 if (final_sequence)
4340 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
4341 operands);
7d167afd 4342 else
4e5b002b
EB		 4343 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4344 it into branch if possible. */
4345 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
4346 operands);
7d167afd 4347 }
9ac617d4 4348 else
7d167afd 4349 {
9ac617d4
EB		 4350 /* This is a regular function so we have to restore the register window.
4351 We may have a pending insn for the delay slot, which will be combined
4352 with the 'restore' instruction. */
7d167afd 4353
9ac617d4 4354 output_asm_insn ("call\t%a0, 0", operands);
7d167afd 4355
4e5b002b 4356 if (final_sequence)
7d167afd 4357 {
9ac617d4 4358 rtx delay = NEXT_INSN (insn);
f5f7d171 4359 gcc_assert (delay);
9ac617d4 4360
6244b14e 4361 output_restore (PATTERN (delay));
9ac617d4
EB		 4362
4363 PATTERN (delay) = gen_blockage ();
4364 INSN_CODE (delay) = -1;
7d167afd 4365 }
9ac617d4 4366 else
6244b14e 4367 output_restore (NULL_RTX);
7d167afd 4368 }
9ac617d4 4369
7d167afd
JJ		 4370 return "";
4371}
4fb4e4b8
DE		 4372\f
4373/* Functions for handling argument passing.
4374
1b5963f7 4375 For 32-bit, the first 6 args are normally in registers and the rest are
4fb4e4b8
DE		 4376 pushed. Any arg that starts within the first 6 words is at least
4377 partially passed in a register unless its data type forbids.
4378
1b5963f7 4379 For 64-bit, the argument registers are laid out as an array of 16 elements
4fb4e4b8
DE		 4380 and arguments are added sequentially. The first 6 int args and up to the
4381 first 16 fp args (depending on size) are passed in regs.
4382
4383 Slot Stack Integral Float Float in structure Double Long Double
4384 ---- ----- -------- ----- ------------------ ------ -----------
4385 15 [SP+248] %f31 %f30,%f31 %d30
4386 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4387 13 [SP+232] %f27 %f26,%f27 %d26
4388 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4389 11 [SP+216] %f23 %f22,%f23 %d22
4390 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4391 9 [SP+200] %f19 %f18,%f19 %d18
4392 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4393 7 [SP+184] %f15 %f14,%f15 %d14
4394 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4395 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4396 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4397 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4398 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4399 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4400 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4401
4402 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4403
1b5963f7 4404 Integral arguments are always passed as 64-bit quantities appropriately
4fb4e4b8
DE		 4405 extended.
4406
4407 Passing of floating point values is handled as follows.
4408 If a prototype is in scope:
4409 If the value is in a named argument (i.e. not a stdarg function or a
4410 value not part of the `...') then the value is passed in the appropriate
4411 fp reg.
4412 If the value is part of the `...' and is passed in one of the first 6
4413 slots then the value is passed in the appropriate int reg.
4414 If the value is part of the `...' and is not passed in one of the first 6
4415 slots then the value is passed in memory.
4416 If a prototype is not in scope:
4417 If the value is one of the first 6 arguments the value is passed in the
4418 appropriate integer reg and the appropriate fp reg.
4419 If the value is not one of the first 6 arguments the value is passed in
4420 the appropriate fp reg and in memory.
1b5963f7
EB		 4421
4422
4423 Summary of the calling conventions implemented by GCC on SPARC:
4424
4425 32-bit ABI:
4426 size argument return value
4427
4428 small integer <4 int. reg. int. reg.
4429 word 4 int. reg. int. reg.
4430 double word 8 int. reg. int. reg.
4431
4432 _Complex small integer <8 int. reg. int. reg.
4433 _Complex word 8 int. reg. int. reg.
4434 _Complex double word 16 memory int. reg.
4435
4436 vector integer <=8 int. reg. FP reg.
4437 vector integer >8 memory memory
4438
4439 float 4 int. reg. FP reg.
4440 double 8 int. reg. FP reg.
4441 long double 16 memory memory
4442
4443 _Complex float 8 memory FP reg.
4444 _Complex double 16 memory FP reg.
4445 _Complex long double 32 memory FP reg.
4446
45261626 4447 vector float any memory memory
1b5963f7
EB		 4448
4449 aggregate any memory memory
4450
4451
4452
4453 64-bit ABI:
4454 size argument return value
4455
4456 small integer <8 int. reg. int. reg.
4457 word 8 int. reg. int. reg.
4458 double word 16 int. reg. int. reg.
4459
4460 _Complex small integer <16 int. reg. int. reg.
4461 _Complex word 16 int. reg. int. reg.
4462 _Complex double word 32 memory int. reg.
4463
4464 vector integer <=16 FP reg. FP reg.
4465 vector integer 16<s<=32 memory FP reg.
4466 vector integer >32 memory memory
4467
4468 float 4 FP reg. FP reg.
4469 double 8 FP reg. FP reg.
4470 long double 16 FP reg. FP reg.
4471
4472 _Complex float 8 FP reg. FP reg.
4473 _Complex double 16 FP reg. FP reg.
4474 _Complex long double 32 memory FP reg.
4475
4476 vector float <=16 FP reg. FP reg.
4477 vector float 16<s<=32 memory FP reg.
4478 vector float >32 memory memory
4479
4480 aggregate <=16 reg. reg.
4481 aggregate 16<s<=32 memory reg.
4482 aggregate >32 memory memory
4483
4484
4485
4486Note #1: complex floating-point types follow the extended SPARC ABIs as
4487implemented by the Sun compiler.
4488
4489Note #2: integral vector types follow the scalar floating-point types
4490conventions to match what is implemented by the Sun VIS SDK.
4491
45261626
EB		 4492Note #3: floating-point vector types follow the aggregate types
4493conventions. */
1b5963f7 4494
4fb4e4b8
DE		 4495
4496/* Maximum number of int regs for args. */
4497#define SPARC_INT_ARG_MAX 6
4498/* Maximum number of fp regs for args. */
4499#define SPARC_FP_ARG_MAX 16
4500
4501#define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4502
4503/* Handle the INIT_CUMULATIVE_ARGS macro.
4504 Initialize a variable CUM of type CUMULATIVE_ARGS
4505 for a call to a function whose data type is FNTYPE.
4506 For a library call, FNTYPE is 0. */
3ea1fdd3 4507
4fb4e4b8 4508void
fc27d102
KG		 4509init_cumulative_args (struct sparc_args *cum, tree fntype,
4510 rtx libname ATTRIBUTE_UNUSED,
4511 tree fndecl ATTRIBUTE_UNUSED)
4fb4e4b8
DE		 4512{
4513 cum->words = 0;
4514 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4515 cum->libcall_p = fntype == 0;
4516}
61a55e8b 4517
bd5bd7ac 4518/* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
3e2cc1d1
KH		 4519 When a prototype says `char' or `short', really pass an `int'. */
4520
4521static bool
586de218 4522sparc_promote_prototypes (const_tree fntype ATTRIBUTE_UNUSED)
3e2cc1d1
KH		 4523{
4524 return TARGET_ARCH32 ? true : false;
4525}
4526
bd5bd7ac 4527/* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
3e2cc1d1
KH		 4528
4529static bool
4530sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4531{
1b5963f7 4532 return TARGET_ARCH64 ? true : false;
3e2cc1d1
KH		 4533}
4534
5c4f4b18
EB		 4535/* Scan the record type TYPE and return the following predicates:
4536 - INTREGS_P: the record contains at least one field or sub-field
4537 that is eligible for promotion in integer registers.
4538 - FP_REGS_P: the record contains at least one field or sub-field
4539 that is eligible for promotion in floating-point registers.
4540 - PACKED_P: the record contains at least one field that is packed.
4541
4542 Sub-fields are not taken into account for the PACKED_P predicate. */
4543
4544static void
a7bba6ca 4545scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
5c4f4b18
EB		 4546{
4547 tree field;
4548
4549 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4550 {
4551 if (TREE_CODE (field) == FIELD_DECL)
4552 {
4553 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4554 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
45261626
EB		 4555 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
4556 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
4557 && TARGET_FPU)
5c4f4b18
EB		 4558 *fpregs_p = 1;
4559 else
4560 *intregs_p = 1;
4561
4562 if (packed_p && DECL_PACKED (field))
4563 *packed_p = 1;
4564 }
4565 }
4566}
4567
4fb4e4b8 4568/* Compute the slot number to pass an argument in.
5c4f4b18 4569 Return the slot number or -1 if passing on the stack.
4fb4e4b8
DE		 4570
4571 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4572 the preceding args and about the function being called.
4573 MODE is the argument's machine mode.
4574 TYPE is the data type of the argument (as a tree).
4575 This is null for libcalls where that information may
4576 not be available.
4577 NAMED is nonzero if this argument is a named parameter
4578 (otherwise it is an extra parameter matching an ellipsis).
4579 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4580 *PREGNO records the register number to use if scalar type.
4581 *PPADDING records the amount of padding needed in words. */
4582
4583static int
fc27d102
KG		 4584function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
4585 tree type, int named, int incoming_p,
4586 int *pregno, int *ppadding)
4fb4e4b8
DE		 4587{
4588 int regbase = (incoming_p
4589 ? SPARC_INCOMING_INT_ARG_FIRST
4590 : SPARC_OUTGOING_INT_ARG_FIRST);
4591 int slotno = cum->words;
45261626 4592 enum mode_class mclass;
4fb4e4b8
DE		 4593 int regno;
4594
4595 *ppadding = 0;
4596
1b5963f7 4597 if (type && TREE_ADDRESSABLE (type))
4fb4e4b8 4598 return -1;
1b5963f7 4599
4fb4e4b8 4600 if (TARGET_ARCH32
1b5963f7
EB		 4601 && mode == BLKmode
4602 && type
4fb4e4b8
DE		 4603 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4604 return -1;
4605
1b5963f7
EB		 4606 /* For SPARC64, objects requiring 16-byte alignment get it. */
4607 if (TARGET_ARCH64
7617ec02 4608 && (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128
1b5963f7
EB		 4609 && (slotno & 1) != 0)
4610 slotno++, *ppadding = 1;
4fb4e4b8 4611
45261626
EB		 4612 mclass = GET_MODE_CLASS (mode);
4613 if (type && TREE_CODE (type) == VECTOR_TYPE)
4614 {
4615 /* Vector types deserve special treatment because they are
4616 polymorphic wrt their mode, depending upon whether VIS
4617 instructions are enabled. */
4618 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4619 {
4620 /* The SPARC port defines no floating-point vector modes. */
f5f7d171 4621 gcc_assert (mode == BLKmode);
45261626
EB		 4622 }
4623 else
4624 {
4625 /* Integral vector types should either have a vector
4626 mode or an integral mode, because we are guaranteed
4627 by pass_by_reference that their size is not greater
4628 than 16 bytes and TImode is 16-byte wide. */
f5f7d171 4629 gcc_assert (mode != BLKmode);
45261626
EB		 4630
4631 /* Vector integers are handled like floats according to
4632 the Sun VIS SDK. */
4633 mclass = MODE_FLOAT;
4634 }
4635 }
4636
4637 switch (mclass)
1b5963f7
EB		 4638 {
4639 case MODE_FLOAT:
4640 case MODE_COMPLEX_FLOAT:
0dd8c9bc 4641 case MODE_VECTOR_INT:
1b5963f7
EB		 4642 if (TARGET_ARCH64 && TARGET_FPU && named)
4643 {
4644 if (slotno >= SPARC_FP_ARG_MAX)
4645 return -1;
4646 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4647 /* Arguments filling only one single FP register are
4648 right-justified in the outer double FP register. */
4649 if (GET_MODE_SIZE (mode) <= 4)
4650 regno++;
4651 break;
4652 }
d560b0aa
EB		 4653 /* fallthrough */
4654
1b5963f7
EB		 4655 case MODE_INT:
4656 case MODE_COMPLEX_INT:
4fb4e4b8
DE		 4657 if (slotno >= SPARC_INT_ARG_MAX)
4658 return -1;
4659 regno = regbase + slotno;
4660 break;
4661
1b5963f7
EB		 4662 case MODE_RANDOM:
4663 if (mode == VOIDmode)
4664 /* MODE is VOIDmode when generating the actual call. */
4665 return -1;
d560b0aa 4666
f5f7d171 4667 gcc_assert (mode == BLKmode);
4fb4e4b8 4668
ef6843ed
EB		 4669 if (TARGET_ARCH32
4670 || !type
4671 || (TREE_CODE (type) != VECTOR_TYPE
4672 && TREE_CODE (type) != RECORD_TYPE))
4fb4e4b8
DE		 4673 {
4674 if (slotno >= SPARC_INT_ARG_MAX)
4675 return -1;
4676 regno = regbase + slotno;
4677 }
45261626 4678 else /* TARGET_ARCH64 && type */
4fb4e4b8 4679 {
5c4f4b18
EB		 4680 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
4681
4682 /* First see what kinds of registers we would need. */
45261626
EB		 4683 if (TREE_CODE (type) == VECTOR_TYPE)
4684 fpregs_p = 1;
4685 else
4686 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5c4f4b18
EB		 4687
4688 /* The ABI obviously doesn't specify how packed structures
4689 are passed. These are defined to be passed in int regs
4690 if possible, otherwise memory. */
4fb4e4b8
DE		 4691 if (packed_p || !named)
4692 fpregs_p = 0, intregs_p = 1;
4693
4694 /* If all arg slots are filled, then must pass on stack. */
4695 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4696 return -1;
1b5963f7 4697
4fb4e4b8
DE		 4698 /* If there are only int args and all int arg slots are filled,
4699 then must pass on stack. */
4700 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4701 return -1;
1b5963f7 4702
4fb4e4b8
DE		 4703 /* Note that even if all int arg slots are filled, fp members may
4704 still be passed in regs if such regs are available.
4705 *PREGNO isn't set because there may be more than one, it's up
4706 to the caller to compute them. */
4707 return slotno;
4708 }
4709 break;
4710
4711 default :
f5f7d171 4712 gcc_unreachable ();
4fb4e4b8
DE		 4713 }
4714
4715 *pregno = regno;
4716 return slotno;
4717}
4718
82d6b402
RH		 4719/* Handle recursive register counting for structure field layout. */
4720
4721struct function_arg_record_value_parms
4722{
48028e21
EB		 4723 rtx ret; /* return expression being built. */
4724 int slotno; /* slot number of the argument. */
4725 int named; /* whether the argument is named. */
4726 int regbase; /* regno of the base register. */
4727 int stack; /* 1 if part of the argument is on the stack. */
1fd05073 4728 int intoffset; /* offset of the first pending integer field. */
48028e21 4729 unsigned int nregs; /* number of words passed in registers. */
82d6b402
RH		 4730};
4731
2a01c939 4732static void function_arg_record_value_3
e80d5f80 4733 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
2a01c939 4734static void function_arg_record_value_2
586de218 4735 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
b1474bb7 4736static void function_arg_record_value_1
586de218
KG		 4737 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
4738static rtx function_arg_record_value (const_tree, enum machine_mode, int, int, int);
22d8d627 4739static rtx function_arg_union_value (int, enum machine_mode, int, int);
2a01c939 4740
0020b823 4741/* A subroutine of function_arg_record_value. Traverse the structure
fae778eb 4742 recursively and determine how many registers will be required. */
0020b823 4743
82d6b402 4744static void
586de218 4745function_arg_record_value_1 (const_tree type, HOST_WIDE_INT startbitpos,
cde85594
EB		 4746 struct function_arg_record_value_parms *parms,
4747 bool packed_p)
82d6b402
RH		 4748{
4749 tree field;
4750
82d6b402
RH		 4751 /* We need to compute how many registers are needed so we can
4752 allocate the PARALLEL but before we can do that we need to know
cde85594
EB		 4753 whether there are any packed fields. The ABI obviously doesn't
4754 specify how structures are passed in this case, so they are
4755 defined to be passed in int regs if possible, otherwise memory,
4756 regardless of whether there are fp values present. */
4757
4758 if (! packed_p)
4759 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4760 {
4761 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4762 {
4763 packed_p = true;
4764 break;
4765 }
4766 }
82d6b402
RH		 4767
4768 /* Compute how many registers we need. */
4769 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4770 {
4771 if (TREE_CODE (field) == FIELD_DECL)
4772 {
75131237
RK		 4773 HOST_WIDE_INT bitpos = startbitpos;
4774
bb05e341
EB		 4775 if (DECL_SIZE (field) != 0)
4776 {
4777 if (integer_zerop (DECL_SIZE (field)))
4778 continue;
4779
4780 if (host_integerp (bit_position (field), 1))
4781 bitpos += int_bit_position (field);
4782 }
75131237 4783
82d6b402
RH		 4784 /* ??? FIXME: else assume zero offset. */
4785
4786 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
cde85594
EB		 4787 function_arg_record_value_1 (TREE_TYPE (field),
4788 bitpos,
4789 parms,
4790 packed_p);
1b5963f7
EB		 4791 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
4792 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
8a98812c
EB		 4793 && TARGET_FPU
4794 && parms->named
4795 && ! packed_p)
82d6b402
RH		 4796 {
4797 if (parms->intoffset != -1)
4798 {
b2f24c85 4799 unsigned int startbit, endbit;
82d6b402
RH		 4800 int intslots, this_slotno;
4801
b2f24c85
EB		 4802 startbit = parms->intoffset & -BITS_PER_WORD;
4803 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4804
4805 intslots = (endbit - startbit) / BITS_PER_WORD;
82d6b402
RH		 4806 this_slotno = parms->slotno + parms->intoffset
4807 / BITS_PER_WORD;
4808
48028e21
EB		 4809 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
4810 {
4811 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
4812 /* We need to pass this field on the stack. */
4813 parms->stack = 1;
4814 }
4815
82d6b402
RH		 4816 parms->nregs += intslots;
4817 parms->intoffset = -1;
4818 }
4819
4820 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4821 If it wasn't true we wouldn't be here. */
45261626
EB		 4822 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
4823 && DECL_MODE (field) == BLKmode)
4824 parms->nregs += TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
4825 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4826 parms->nregs += 2;
4827 else
105b2084 4828 parms->nregs += 1;
82d6b402
RH		 4829 }
4830 else
4831 {
4832 if (parms->intoffset == -1)
4833 parms->intoffset = bitpos;
4834 }
4835 }
4836 }
4837}
4838
0020b823
RH		 4839/* A subroutine of function_arg_record_value. Assign the bits of the
4840 structure between parms->intoffset and bitpos to integer registers. */
82d6b402
RH		 4841
4842static void
fc27d102
KG		 4843function_arg_record_value_3 (HOST_WIDE_INT bitpos,
4844 struct function_arg_record_value_parms *parms)
82d6b402
RH		 4845{
4846 enum machine_mode mode;
75131237 4847 unsigned int regno;
0020b823 4848 unsigned int startbit, endbit;
75131237 4849 int this_slotno, intslots, intoffset;
82d6b402
RH		 4850 rtx reg;
4851
4852 if (parms->intoffset == -1)
4853 return;
75131237 4854
82d6b402
RH		 4855 intoffset = parms->intoffset;
4856 parms->intoffset = -1;
4857
0020b823
RH		 4858 startbit = intoffset & -BITS_PER_WORD;
4859 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4860 intslots = (endbit - startbit) / BITS_PER_WORD;
82d6b402
RH		 4861 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
4862
4863 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4864 if (intslots <= 0)
4865 return;
4866
4867 /* If this is the trailing part of a word, only load that much into
4868 the register. Otherwise load the whole register. Note that in
4869 the latter case we may pick up unwanted bits. It's not a problem
4870 at the moment but may wish to revisit. */
4871
4872 if (intoffset % BITS_PER_WORD != 0)
bb05e341
EB		 4873 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4874 MODE_INT);
82d6b402
RH		 4875 else
4876 mode = word_mode;
4877
4878 intoffset /= BITS_PER_UNIT;
4879 do
4880 {
4881 regno = parms->regbase + this_slotno;
254110c2 4882 reg = gen_rtx_REG (mode, regno);
48028e21 4883 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
254110c2 4884 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
82d6b402
RH		 4885
4886 this_slotno += 1;
4887 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
1fd05073 4888 mode = word_mode;
82d6b402
RH		 4889 parms->nregs += 1;
4890 intslots -= 1;
4891 }
4892 while (intslots > 0);
4893}
4894
0020b823
RH		 4895/* A subroutine of function_arg_record_value. Traverse the structure
4896 recursively and assign bits to floating point registers. Track which
4897 bits in between need integer registers; invoke function_arg_record_value_3
4898 to make that happen. */
4899
82d6b402 4900static void
586de218 4901function_arg_record_value_2 (const_tree type, HOST_WIDE_INT startbitpos,
cde85594
EB		 4902 struct function_arg_record_value_parms *parms,
4903 bool packed_p)
82d6b402
RH		 4904{
4905 tree field;
82d6b402 4906
cde85594
EB		 4907 if (! packed_p)
4908 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4909 {
4910 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4911 {
4912 packed_p = true;
4913 break;
4914 }
4915 }
82d6b402
RH		 4916
4917 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4918 {
4919 if (TREE_CODE (field) == FIELD_DECL)
4920 {
75131237
RK		 4921 HOST_WIDE_INT bitpos = startbitpos;
4922
bb05e341
EB		 4923 if (DECL_SIZE (field) != 0)
4924 {
4925 if (integer_zerop (DECL_SIZE (field)))
4926 continue;
4927
4928 if (host_integerp (bit_position (field), 1))
4929 bitpos += int_bit_position (field);
4930 }
75131237 4931
82d6b402
RH		 4932 /* ??? FIXME: else assume zero offset. */
4933
4934 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
cde85594
EB		 4935 function_arg_record_value_2 (TREE_TYPE (field),
4936 bitpos,
4937 parms,
4938 packed_p);
1b5963f7
EB		 4939 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
4940 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
8a98812c
EB		 4941 && TARGET_FPU
4942 && parms->named
4943 && ! packed_p)
82d6b402
RH		 4944 {
4945 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
45261626 4946 int regno, nregs, pos;
105b2084 4947 enum machine_mode mode = DECL_MODE (field);
82d6b402
RH		 4948 rtx reg;
4949
4950 function_arg_record_value_3 (bitpos, parms);
45261626
EB		 4951
4952 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
4953 && mode == BLKmode)
4954 {
4955 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
4956 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
105b2084 4957 }
45261626
EB		 4958 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4959 {
4960 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
4961 nregs = 2;
4962 }
4963 else
4964 nregs = 1;
4965
1b5963f7
EB		 4966 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
4967 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
4968 regno++;
105b2084 4969 reg = gen_rtx_REG (mode, regno);
45261626 4970 pos = bitpos / BITS_PER_UNIT;
48028e21 4971 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
45261626 4972 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
82d6b402 4973 parms->nregs += 1;
45261626 4974 while (--nregs > 0)
105b2084
JJ		 4975 {
4976 regno += GET_MODE_SIZE (mode) / 4;
4977 reg = gen_rtx_REG (mode, regno);
45261626 4978 pos += GET_MODE_SIZE (mode);
48028e21 4979 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
45261626 4980 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
105b2084
JJ		 4981 parms->nregs += 1;
4982 }
82d6b402
RH		 4983 }
4984 else
4985 {
4986 if (parms->intoffset == -1)
4987 parms->intoffset = bitpos;
4988 }
4989 }
4990 }
4991}
4992
0020b823 4993/* Used by function_arg and function_value to implement the complex
48028e21
EB		 4994 conventions of the 64-bit ABI for passing and returning structures.
4995 Return an expression valid as a return value for the two macros
4996 FUNCTION_ARG and FUNCTION_VALUE.
0020b823 4997
48028e21
EB		 4998 TYPE is the data type of the argument (as a tree).
4999 This is null for libcalls where that information may
5000 not be available.
5001 MODE is the argument's machine mode.
5002 SLOTNO is the index number of the argument's slot in the parameter array.
5003 NAMED is nonzero if this argument is a named parameter
5004 (otherwise it is an extra parameter matching an ellipsis).
5005 REGBASE is the regno of the base register for the parameter array. */
5006
82d6b402 5007static rtx
586de218 5008function_arg_record_value (const_tree type, enum machine_mode mode,
fc27d102 5009 int slotno, int named, int regbase)
82d6b402
RH		 5010{
5011 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5012 struct function_arg_record_value_parms parms;
75131237 5013 unsigned int nregs;
82d6b402
RH		 5014
5015 parms.ret = NULL_RTX;
5016 parms.slotno = slotno;
5017 parms.named = named;
5018 parms.regbase = regbase;
48028e21 5019 parms.stack = 0;
82d6b402
RH		 5020
5021 /* Compute how many registers we need. */
5022 parms.nregs = 0;
5023 parms.intoffset = 0;
cde85594 5024 function_arg_record_value_1 (type, 0, &parms, false);
82d6b402 5025
1fd05073 5026 /* Take into account pending integer fields. */
82d6b402
RH		 5027 if (parms.intoffset != -1)
5028 {
0020b823 5029 unsigned int startbit, endbit;
82d6b402
RH		 5030 int intslots, this_slotno;
5031
0020b823
RH		 5032 startbit = parms.intoffset & -BITS_PER_WORD;
5033 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5034 intslots = (endbit - startbit) / BITS_PER_WORD;
82d6b402
RH		 5035 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5036
48028e21
EB		 5037 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5038 {
5039 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5040 /* We need to pass this field on the stack. */
5041 parms.stack = 1;
5042 }
82d6b402
RH		 5043
5044 parms.nregs += intslots;
5045 }
5046 nregs = parms.nregs;
5047
5048 /* Allocate the vector and handle some annoying special cases. */
5049 if (nregs == 0)
5050 {
5051 /* ??? Empty structure has no value? Duh? */
5052 if (typesize <= 0)
5053 {
5054 /* Though there's nothing really to store, return a word register
5055 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5056 leads to breakage due to the fact that there are zero bytes to
5057 load. */
1eac9f59 5058 return gen_rtx_REG (mode, regbase);
82d6b402
RH		 5059 }
5060 else
5061 {
5062 /* ??? C++ has structures with no fields, and yet a size. Give up
5063 for now and pass everything back in integer registers. */
5064 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5065 }
5066 if (nregs + slotno > SPARC_INT_ARG_MAX)
5067 nregs = SPARC_INT_ARG_MAX - slotno;
5068 }
f5f7d171 5069 gcc_assert (nregs != 0);
82d6b402 5070
48028e21
EB		 5071 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5072
5073 /* If at least one field must be passed on the stack, generate
5074 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5075 also be passed on the stack. We can't do much better because the
78a52f11 5076 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
48028e21
EB		 5077 of structures for which the fields passed exclusively in registers
5078 are not at the beginning of the structure. */
5079 if (parms.stack)
5080 XVECEXP (parms.ret, 0, 0)
5081 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
82d6b402
RH		 5082
5083 /* Fill in the entries. */
5084 parms.nregs = 0;
5085 parms.intoffset = 0;
cde85594 5086 function_arg_record_value_2 (type, 0, &parms, false);
82d6b402
RH		 5087 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5088
f5f7d171 5089 gcc_assert (parms.nregs == nregs);
82d6b402
RH		 5090
5091 return parms.ret;
5092}
5093
a7bba6ca
EB		 5094/* Used by function_arg and function_value to implement the conventions
5095 of the 64-bit ABI for passing and returning unions.
5096 Return an expression valid as a return value for the two macros
5097 FUNCTION_ARG and FUNCTION_VALUE.
5098
5099 SIZE is the size in bytes of the union.
85bbb21f 5100 MODE is the argument's machine mode.
a7bba6ca
EB		 5101 REGNO is the hard register the union will be passed in. */
5102
5103static rtx
22d8d627
EB		 5104function_arg_union_value (int size, enum machine_mode mode, int slotno,
5105 int regno)
a7bba6ca 5106{
85bbb21f
EB		 5107 int nwords = ROUND_ADVANCE (size), i;
5108 rtx regs;
a7bba6ca 5109
bb05e341
EB		 5110 /* See comment in previous function for empty structures. */
5111 if (nwords == 0)
5112 return gen_rtx_REG (mode, regno);
5113
22d8d627
EB		 5114 if (slotno == SPARC_INT_ARG_MAX - 1)
5115 nwords = 1;
5116
85bbb21f 5117 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
a7bba6ca 5118
85bbb21f 5119 for (i = 0; i < nwords; i++)
45261626
EB		 5120 {
5121 /* Unions are passed left-justified. */
5122 XVECEXP (regs, 0, i)
5123 = gen_rtx_EXPR_LIST (VOIDmode,
5124 gen_rtx_REG (word_mode, regno),
5125 GEN_INT (UNITS_PER_WORD * i));
5126 regno++;
5127 }
5128
5129 return regs;
5130}
5131
5132/* Used by function_arg and function_value to implement the conventions
5133 for passing and returning large (BLKmode) vectors.
5134 Return an expression valid as a return value for the two macros
5135 FUNCTION_ARG and FUNCTION_VALUE.
5136
26237a50 5137 SIZE is the size in bytes of the vector (at least 8 bytes).
45261626
EB		 5138 REGNO is the FP hard register the vector will be passed in. */
5139
5140static rtx
26237a50 5141function_arg_vector_value (int size, int regno)
45261626 5142{
26237a50 5143 int i, nregs = size / 8;
45261626
EB		 5144 rtx regs;
5145
5146 regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
5147
5148 for (i = 0; i < nregs; i++)
5149 {
5150 XVECEXP (regs, 0, i)
5151 = gen_rtx_EXPR_LIST (VOIDmode,
26237a50
EB		 5152 gen_rtx_REG (DImode, regno + 2*i),
5153 GEN_INT (i*8));
45261626 5154 }
a7bba6ca 5155
85bbb21f 5156 return regs;
a7bba6ca
EB		 5157}
5158
4fb4e4b8
DE		 5159/* Handle the FUNCTION_ARG macro.
5160 Determine where to put an argument to a function.
5161 Value is zero to push the argument on the stack,
5162 or a hard register in which to store the argument.
5163
5164 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5165 the preceding args and about the function being called.
5166 MODE is the argument's machine mode.
5167 TYPE is the data type of the argument (as a tree).
5168 This is null for libcalls where that information may
5169 not be available.
5170 NAMED is nonzero if this argument is a named parameter
5171 (otherwise it is an extra parameter matching an ellipsis).
5172 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
61a55e8b
DE		 5173
5174rtx
fc27d102
KG		 5175function_arg (const struct sparc_args *cum, enum machine_mode mode,
5176 tree type, int named, int incoming_p)
61a55e8b 5177{
4fb4e4b8
DE		 5178 int regbase = (incoming_p
5179 ? SPARC_INCOMING_INT_ARG_FIRST
5180 : SPARC_OUTGOING_INT_ARG_FIRST);
5181 int slotno, regno, padding;
45261626 5182 enum mode_class mclass = GET_MODE_CLASS (mode);
4fb4e4b8
DE		 5183
5184 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5185 &regno, &padding);
4fb4e4b8
DE		 5186 if (slotno == -1)
5187 return 0;
5188
ef6843ed
EB		 5189 /* Vector types deserve special treatment because they are polymorphic wrt
5190 their mode, depending upon whether VIS instructions are enabled. */
5191 if (type && TREE_CODE (type) == VECTOR_TYPE)
4fb4e4b8 5192 {
ef6843ed
EB		 5193 HOST_WIDE_INT size = int_size_in_bytes (type);
5194 gcc_assert ((TARGET_ARCH32 && size <= 8)
5195 || (TARGET_ARCH64 && size <= 16));
5196
5197 if (mode == BLKmode)
5198 return function_arg_vector_value (size,
ef6843ed
EB		 5199 SPARC_FP_ARG_FIRST + 2*slotno);
5200 else
5201 mclass = MODE_FLOAT;
4fb4e4b8 5202 }
4043d6fb 5203
ef6843ed
EB		 5204 if (TARGET_ARCH32)
5205 return gen_rtx_REG (mode, regno);
4043d6fb 5206
ef6843ed
EB		 5207 /* Structures up to 16 bytes in size are passed in arg slots on the stack
5208 and are promoted to registers if possible. */
5209 if (type && TREE_CODE (type) == RECORD_TYPE)
4043d6fb 5210 {
a7bba6ca 5211 HOST_WIDE_INT size = int_size_in_bytes (type);
f5f7d171 5212 gcc_assert (size <= 16);
4fb4e4b8 5213
ef6843ed 5214 return function_arg_record_value (type, mode, slotno, named, regbase);
4043d6fb 5215 }
ef6843ed
EB		 5216
5217 /* Unions up to 16 bytes in size are passed in integer registers. */
5218 else if (type && TREE_CODE (type) == UNION_TYPE)
45261626 5219 {
45261626 5220 HOST_WIDE_INT size = int_size_in_bytes (type);
f5f7d171 5221 gcc_assert (size <= 16);
45261626 5222
ef6843ed 5223 return function_arg_union_value (size, mode, slotno, regno);
45261626
EB		 5224 }
5225
4fb4e4b8
DE		 5226 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5227 but also have the slot allocated for them.
5228 If no prototype is in scope fp values in register slots get passed
5229 in two places, either fp regs and int regs or fp regs and memory. */
ef6843ed
EB		 5230 else if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
5231 && SPARC_FP_REG_P (regno))
4fb4e4b8 5232 {
ef6843ed 5233 rtx reg = gen_rtx_REG (mode, regno);
4fb4e4b8
DE		 5234 if (cum->prototype_p || cum->libcall_p)
5235 {
5236 /* "* 2" because fp reg numbers are recorded in 4 byte
5237 quantities. */
82d6b402 5238#if 0
4fb4e4b8
DE		 5239 /* ??? This will cause the value to be passed in the fp reg and
5240 in the stack. When a prototype exists we want to pass the
5241 value in the reg but reserve space on the stack. That's an
956d6950 5242 optimization, and is deferred [for a bit]. */
4fb4e4b8 5243 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
254110c2 5244 return gen_rtx_PARALLEL (mode,
4fb4e4b8 5245 gen_rtvec (2,
254110c2 5246 gen_rtx_EXPR_LIST (VOIDmode,
4fb4e4b8 5247 NULL_RTX, const0_rtx),
254110c2 5248 gen_rtx_EXPR_LIST (VOIDmode,
4fb4e4b8
DE		 5249 reg, const0_rtx)));
5250 else
82d6b402
RH		 5251#else
5252 /* ??? It seems that passing back a register even when past
5253 the area declared by REG_PARM_STACK_SPACE will allocate
5254 space appropriately, and will not copy the data onto the
5255 stack, exactly as we desire.
5256
5257 This is due to locate_and_pad_parm being called in
5258 expand_call whenever reg_parm_stack_space > 0, which
fae778eb 5259 while beneficial to our example here, would seem to be
82d6b402
RH		 5260 in error from what had been intended. Ho hum... -- r~ */
5261#endif
4fb4e4b8
DE		 5262 return reg;
5263 }
5264 else
5265 {
82d6b402
RH		 5266 rtx v0, v1;
5267
4fb4e4b8
DE		 5268 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5269 {
82d6b402
RH		 5270 int intreg;
5271
5272 /* On incoming, we don't need to know that the value
5273 is passed in %f0 and %i0, and it confuses other parts
5274 causing needless spillage even on the simplest cases. */
5275 if (incoming_p)
5276 return reg;
5277
5278 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5279 + (regno - SPARC_FP_ARG_FIRST) / 2);
5280
5281 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5282 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5283 const0_rtx);
5284 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4fb4e4b8
DE		 5285 }
5286 else
82d6b402
RH		 5287 {
5288 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5289 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5290 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5291 }
4fb4e4b8
DE		 5292 }
5293 }
ef6843ed
EB		 5294
5295 /* All other aggregate types are passed in an integer register in a mode
5296 corresponding to the size of the type. */
5297 else if (type && AGGREGATE_TYPE_P (type))
4fb4e4b8 5298 {
ef6843ed
EB		 5299 HOST_WIDE_INT size = int_size_in_bytes (type);
5300 gcc_assert (size <= 16);
5301
5302 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
4fb4e4b8
DE		 5303 }
5304
ef6843ed 5305 return gen_rtx_REG (mode, regno);
4fb4e4b8 5306}
a7acd911 5307
78a52f11
RH		 5308/* For an arg passed partly in registers and partly in memory,
5309 this is the number of bytes of registers used.
4fb4e4b8 5310 For args passed entirely in registers or entirely in memory, zero.
61a55e8b 5311
4fb4e4b8
DE		 5312 Any arg that starts in the first 6 regs but won't entirely fit in them
5313 needs partial registers on v8. On v9, structures with integer
5314 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5315 values that begin in the last fp reg [where "last fp reg" varies with the
5316 mode] will be split between that reg and memory. */
61a55e8b 5317
78a52f11
RH		 5318static int
5319sparc_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5320 tree type, bool named)
4fb4e4b8
DE		 5321{
5322 int slotno, regno, padding;
61a55e8b 5323
4fb4e4b8
DE		 5324 /* We pass 0 for incoming_p here, it doesn't matter. */
5325 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5326
5327 if (slotno == -1)
5328 return 0;
5329
5330 if (TARGET_ARCH32)
bf62bbf1 5331 {
4fb4e4b8
DE		 5332 if ((slotno + (mode == BLKmode
5333 ? ROUND_ADVANCE (int_size_in_bytes (type))
5334 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
1b5963f7 5335 > SPARC_INT_ARG_MAX)
78a52f11 5336 return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD;
4fb4e4b8
DE		 5337 }
5338 else
5339 {
8cd5a4e0 5340 /* We are guaranteed by pass_by_reference that the size of the
78a52f11
RH		 5341 argument is not greater than 16 bytes, so we only need to return
5342 one word if the argument is partially passed in registers. */
1b5963f7 5343
4fb4e4b8
DE		 5344 if (type && AGGREGATE_TYPE_P (type))
5345 {
5346 int size = int_size_in_bytes (type);
bf62bbf1 5347
1b5963f7 5348 if (size > UNITS_PER_WORD
4fb4e4b8 5349 && slotno == SPARC_INT_ARG_MAX - 1)
78a52f11 5350 return UNITS_PER_WORD;
4fb4e4b8 5351 }
0a9e65f9 5352 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
4fb4e4b8 5353 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
c3427c7d 5354 && ! (TARGET_FPU && named)))
4fb4e4b8 5355 {
0a9e65f9 5356 /* The complex types are passed as packed types. */
1b5963f7
EB		 5357 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5358 && slotno == SPARC_INT_ARG_MAX - 1)
78a52f11 5359 return UNITS_PER_WORD;
4fb4e4b8
DE		 5360 }
5361 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5362 {
4fb4e4b8
DE		 5363 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5364 > SPARC_FP_ARG_MAX)
78a52f11 5365 return UNITS_PER_WORD;
4fb4e4b8 5366 }
bf62bbf1 5367 }
1b5963f7
EB		 5368
5369 return 0;
4fb4e4b8 5370}
61a55e8b 5371
45261626
EB		 5372/* Handle the TARGET_PASS_BY_REFERENCE target hook.
5373 Specify whether to pass the argument by reference. */
4fb4e4b8 5374
8cd5a4e0
RH		 5375static bool
5376sparc_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
586de218 5377 enum machine_mode mode, const_tree type,
8cd5a4e0 5378 bool named ATTRIBUTE_UNUSED)
4fb4e4b8
DE		 5379{
5380 if (TARGET_ARCH32)
45261626
EB		 5381 /* Original SPARC 32-bit ABI says that structures and unions,
5382 and quad-precision floats are passed by reference. For Pascal,
5383 also pass arrays by reference. All other base types are passed
5384 in registers.
5385
5386 Extended ABI (as implemented by the Sun compiler) says that all
5387 complex floats are passed by reference. Pass complex integers
5388 in registers up to 8 bytes. More generally, enforce the 2-word
5389 cap for passing arguments in registers.
5390
5391 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5392 integers are passed like floats of the same size, that is in
5393 registers up to 8 bytes. Pass all vector floats by reference
5394 like structure and unions. */
ef6843ed
EB		 5395 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
5396 || mode == SCmode
5397 /* Catch CDImode, TFmode, DCmode and TCmode. */
5398 || GET_MODE_SIZE (mode) > 8
5399 || (type
5400 && TREE_CODE (type) == VECTOR_TYPE
5401 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
4fb4e4b8 5402 else
45261626
EB		 5403 /* Original SPARC 64-bit ABI says that structures and unions
5404 smaller than 16 bytes are passed in registers, as well as
ef6843ed 5405 all other base types.
45261626
EB		 5406
5407 Extended ABI (as implemented by the Sun compiler) says that
5408 complex floats are passed in registers up to 16 bytes. Pass
5409 all complex integers in registers up to 16 bytes. More generally,
5410 enforce the 2-word cap for passing arguments in registers.
5411
5412 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5413 integers are passed like floats of the same size, that is in
5414 registers (up to 16 bytes). Pass all vector floats like structure
5415 and unions. */
ef6843ed
EB		 5416 return ((type
5417 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE)
5418 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
5419 /* Catch CTImode and TCmode. */
5420 || GET_MODE_SIZE (mode) > 16);
4fb4e4b8
DE		 5421}
5422
5423/* Handle the FUNCTION_ARG_ADVANCE macro.
5424 Update the data in CUM to advance over an argument
5425 of mode MODE and data type TYPE.
5426 TYPE is null for libcalls where that information may not be available. */
5427
5428void
fc27d102
KG		 5429function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5430 tree type, int named)
4fb4e4b8
DE		 5431{
5432 int slotno, regno, padding;
5433
5434 /* We pass 0 for incoming_p here, it doesn't matter. */
5435 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5436
5437 /* If register required leading padding, add it. */
5438 if (slotno != -1)
5439 cum->words += padding;
eadceb59 5440
4fb4e4b8
DE		 5441 if (TARGET_ARCH32)
5442 {
5443 cum->words += (mode != BLKmode
5444 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5445 : ROUND_ADVANCE (int_size_in_bytes (type)));
5446 }
5447 else
5448 {
5449 if (type && AGGREGATE_TYPE_P (type))
5450 {
5451 int size = int_size_in_bytes (type);
5452
5453 if (size <= 8)
5454 ++cum->words;
5455 else if (size <= 16)
5456 cum->words += 2;
5457 else /* passed by reference */
5458 ++cum->words;
5459 }
4fb4e4b8
DE		 5460 else
5461 {
5462 cum->words += (mode != BLKmode
5463 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5464 : ROUND_ADVANCE (int_size_in_bytes (type)));
5465 }
eadceb59 5466 }
4fb4e4b8 5467}
eadceb59 5468
4fb4e4b8
DE		 5469/* Handle the FUNCTION_ARG_PADDING macro.
5470 For the 64 bit ABI structs are always stored left shifted in their
5471 argument slot. */
5472
5473enum direction
586de218 5474function_arg_padding (enum machine_mode mode, const_tree type)
4fb4e4b8 5475{
c85f7c16
JL		 5476 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5477 return upward;
61a55e8b 5478
d3704c46
KH		 5479 /* Fall back to the default. */
5480 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
61a55e8b 5481}
82d6b402 5482
1b5963f7
EB		 5483/* Handle the TARGET_RETURN_IN_MEMORY target hook.
5484 Specify whether to return the return value in memory. */
5485
5486static bool
586de218 5487sparc_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1b5963f7
EB		 5488{
5489 if (TARGET_ARCH32)
45261626
EB		 5490 /* Original SPARC 32-bit ABI says that structures and unions,
5491 and quad-precision floats are returned in memory. All other
5492 base types are returned in registers.
5493
5494 Extended ABI (as implemented by the Sun compiler) says that
5495 all complex floats are returned in registers (8 FP registers
5496 at most for '_Complex long double'). Return all complex integers
5497 in registers (4 at most for '_Complex long long').
5498
5499 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5500 integers are returned like floats of the same size, that is in
5501 registers up to 8 bytes and in memory otherwise. Return all
5502 vector floats in memory like structure and unions; note that
5503 they always have BLKmode like the latter. */
1b5963f7
EB		 5504 return (TYPE_MODE (type) == BLKmode
5505 || TYPE_MODE (type) == TFmode
45261626
EB		 5506 || (TREE_CODE (type) == VECTOR_TYPE
5507 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
1b5963f7
EB		 5508 else
5509 /* Original SPARC 64-bit ABI says that structures and unions
45261626
EB		 5510 smaller than 32 bytes are returned in registers, as well as
5511 all other base types.
5512
5513 Extended ABI (as implemented by the Sun compiler) says that all
5514 complex floats are returned in registers (8 FP registers at most
5515 for '_Complex long double'). Return all complex integers in
5516 registers (4 at most for '_Complex TItype').
5517
5518 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5519 integers are returned like floats of the same size, that is in
5520 registers. Return all vector floats like structure and unions;
5521 note that they always have BLKmode like the latter. */
1b5963f7 5522 return ((TYPE_MODE (type) == BLKmode
45261626 5523 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32));
1b5963f7
EB		 5524}
5525
5526/* Handle the TARGET_STRUCT_VALUE target hook.
5527 Return where to find the structure return value address. */
5528
5529static rtx
2225b57c 5530sparc_struct_value_rtx (tree fndecl, int incoming)
1b5963f7
EB		 5531{
5532 if (TARGET_ARCH64)
5533 return 0;
5534 else
5535 {
1da4c3a7
EB		 5536 rtx mem;
5537
1b5963f7 5538 if (incoming)
1da4c3a7
EB		 5539 mem = gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx,
5540 STRUCT_VALUE_OFFSET));
1b5963f7 5541 else
1da4c3a7
EB		 5542 mem = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx,
5543 STRUCT_VALUE_OFFSET));
5544
2225b57c
CD		 5545 /* Only follow the SPARC ABI for fixed-size structure returns.
5546 Variable size structure returns are handled per the normal
5547 procedures in GCC. This is enabled by -mstd-struct-return */
5548 if (incoming == 2
5549 && sparc_std_struct_return
5550 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl))
5551 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl))) == INTEGER_CST)
5552 {
5553 /* We must check and adjust the return address, as it is
5554 optional as to whether the return object is really
5555 provided. */
5556 rtx ret_rtx = gen_rtx_REG (Pmode, 31);
5557 rtx scratch = gen_reg_rtx (SImode);
5558 rtx endlab = gen_label_rtx ();
5559
5560 /* Calculate the return object size */
5561 tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl));
5562 rtx size_rtx = GEN_INT (TREE_INT_CST_LOW (size) & 0xfff);
5563 /* Construct a temporary return value */
5564 rtx temp_val = assign_stack_local (Pmode, TREE_INT_CST_LOW (size), 0);
5565
5566 /* Implement SPARC 32-bit psABI callee returns struck checking
5567 requirements:
5568
5569 Fetch the instruction where we will return to and see if
5570 it's an unimp instruction (the most significant 10 bits
5571 will be zero). */
5572 emit_move_insn (scratch, gen_rtx_MEM (SImode,
5573 plus_constant (ret_rtx, 8)));
5574 /* Assume the size is valid and pre-adjust */
5575 emit_insn (gen_add3_insn (ret_rtx, ret_rtx, GEN_INT (4)));
5576 emit_cmp_and_jump_insns (scratch, size_rtx, EQ, const0_rtx, SImode, 0, endlab);
5577 emit_insn (gen_sub3_insn (ret_rtx, ret_rtx, GEN_INT (4)));
5578 /* Assign stack temp:
5579 Write the address of the memory pointed to by temp_val into
5580 the memory pointed to by mem */
5581 emit_move_insn (mem, XEXP (temp_val, 0));
5582 emit_label (endlab);
5583 }
5584
1da4c3a7
EB		 5585 set_mem_alias_set (mem, struct_value_alias_set);
5586 return mem;
1b5963f7
EB		 5587 }
5588}
5589
82d6b402
RH		 5590/* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5591 For v9, function return values are subject to the same rules as arguments,
1b5963f7 5592 except that up to 32 bytes may be returned in registers. */
82d6b402
RH		 5593
5594rtx
586de218 5595function_value (const_tree type, enum machine_mode mode, int incoming_p)
82d6b402 5596{
1b5963f7
EB		 5597 /* Beware that the two values are swapped here wrt function_arg. */
5598 int regbase = (incoming_p
5599 ? SPARC_OUTGOING_INT_ARG_FIRST
5600 : SPARC_INCOMING_INT_ARG_FIRST);
45261626 5601 enum mode_class mclass = GET_MODE_CLASS (mode);
82d6b402 5602 int regno;
82d6b402 5603
ef6843ed
EB		 5604 /* Vector types deserve special treatment because they are polymorphic wrt
5605 their mode, depending upon whether VIS instructions are enabled. */
45261626
EB		 5606 if (type && TREE_CODE (type) == VECTOR_TYPE)
5607 {
45261626 5608 HOST_WIDE_INT size = int_size_in_bytes (type);
f5f7d171
JM		 5609 gcc_assert ((TARGET_ARCH32 && size <= 8)
5610 || (TARGET_ARCH64 && size <= 32));
45261626
EB		 5611
5612 if (mode == BLKmode)
5613 return function_arg_vector_value (size,
45261626
EB		 5614 SPARC_FP_ARG_FIRST);
5615 else
5616 mclass = MODE_FLOAT;
5617 }
ef6843ed
EB		 5618
5619 if (TARGET_ARCH64 && type)
82d6b402 5620 {
ef6843ed 5621 /* Structures up to 32 bytes in size are returned in registers. */
82d6b402
RH		 5622 if (TREE_CODE (type) == RECORD_TYPE)
5623 {
ef6843ed
EB		 5624 HOST_WIDE_INT size = int_size_in_bytes (type);
5625 gcc_assert (size <= 32);
82d6b402 5626
1eac9f59 5627 return function_arg_record_value (type, mode, 0, 1, regbase);
82d6b402 5628 }
ef6843ed
EB		 5629
5630 /* Unions up to 32 bytes in size are returned in integer registers. */
a7bba6ca
EB		 5631 else if (TREE_CODE (type) == UNION_TYPE)
5632 {
5633 HOST_WIDE_INT size = int_size_in_bytes (type);
f5f7d171 5634 gcc_assert (size <= 32);
a7bba6ca 5635
22d8d627 5636 return function_arg_union_value (size, mode, 0, regbase);
a7bba6ca 5637 }
ef6843ed
EB		 5638
5639 /* Objects that require it are returned in FP registers. */
5640 else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
5641 ;
5642
5643 /* All other aggregate types are returned in an integer register in a
5644 mode corresponding to the size of the type. */
8a7199ad 5645 else if (AGGREGATE_TYPE_P (type))
82d6b402 5646 {
8a7199ad
RK		 5647 /* All other aggregate types are passed in an integer register
5648 in a mode corresponding to the size of the type. */
ef6843ed
EB		 5649 HOST_WIDE_INT size = int_size_in_bytes (type);
5650 gcc_assert (size <= 32);
82d6b402 5651
ef6843ed 5652 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
c74fd3f1
EB		 5653
5654 /* ??? We probably should have made the same ABI change in
5655 3.4.0 as the one we made for unions. The latter was
5656 required by the SCD though, while the former is not
5657 specified, so we favored compatibility and efficiency.
5658
5659 Now we're stuck for aggregates larger than 16 bytes,
5660 because OImode vanished in the meantime. Let's not
5661 try to be unduly clever, and simply follow the ABI
5662 for unions in that case. */
5663 if (mode == BLKmode)
ef6843ed 5664 return function_arg_union_value (size, mode, 0, regbase);
45261626
EB		 5665 else
5666 mclass = MODE_INT;
82d6b402 5667 }
ef6843ed
EB		 5668
5669 /* This must match PROMOTE_FUNCTION_MODE. */
5670 else if (mclass == MODE_INT && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
a7bba6ca 5671 mode = word_mode;
82d6b402
RH		 5672 }
5673
ef6843ed 5674 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) && TARGET_FPU)
1b5963f7 5675 regno = SPARC_FP_ARG_FIRST;
82d6b402 5676 else
1b5963f7 5677 regno = regbase;
82d6b402 5678
254110c2 5679 return gen_rtx_REG (mode, regno);
82d6b402
RH		 5680}
5681
648d2ffc
RH		 5682/* Do what is necessary for `va_start'. We look at the current function
5683 to determine if stdarg or varargs is used and return the address of
5684 the first unnamed parameter. */
3ea1fdd3 5685
3e2cc1d1 5686static rtx
fc27d102 5687sparc_builtin_saveregs (void)
3ea1fdd3 5688{
38173d38 5689 int first_reg = crtl->args.info.words;
3ea1fdd3
JW		 5690 rtx address;
5691 int regno;
5692
1b5963f7 5693 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
254110c2 5694 emit_move_insn (gen_rtx_MEM (word_mode,
8ac61af7
RK		 5695 gen_rtx_PLUS (Pmode,
5696 frame_pointer_rtx,
563c12b0 5697 GEN_INT (FIRST_PARM_OFFSET (0)
8ac61af7
RK		 5698 + (UNITS_PER_WORD
5699 * regno)))),
254110c2 5700 gen_rtx_REG (word_mode,
1b5963f7 5701 SPARC_INCOMING_INT_ARG_FIRST + regno));
3ea1fdd3 5702
254110c2 5703 address = gen_rtx_PLUS (Pmode,
8ac61af7 5704 frame_pointer_rtx,
563c12b0 5705 GEN_INT (FIRST_PARM_OFFSET (0)
8ac61af7 5706 + UNITS_PER_WORD * first_reg));
3ea1fdd3
JW		 5707
5708 return address;
5709}
a8b2c8a1 5710
1b5963f7 5711/* Implement `va_start' for stdarg. */
a8b2c8a1 5712
d7bd8aeb 5713static void
fc27d102 5714sparc_va_start (tree valist, rtx nextarg)
a8b2c8a1
RH		 5715{
5716 nextarg = expand_builtin_saveregs ();
e5faf155 5717 std_expand_builtin_va_start (valist, nextarg);
a8b2c8a1
RH		 5718}
5719
1b5963f7 5720/* Implement `va_arg' for stdarg. */
a8b2c8a1 5721
35652573 5722static tree
726a989a
RB		 5723sparc_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
5724 gimple_seq *post_p)
5f393b25
JM		 5725{
5726 HOST_WIDE_INT size, rsize, align;
5727 tree addr, incr;
5728 bool indirect;
5729 tree ptrtype = build_pointer_type (type);
5730
22d66adf 5731 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5f393b25
JM		 5732 {
5733 indirect = true;
5734 size = rsize = UNITS_PER_WORD;
5735 align = 0;
5736 }
5737 else
5738 {
5739 indirect = false;
5740 size = int_size_in_bytes (type);
5741 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5742 align = 0;
5743
5744 if (TARGET_ARCH64)
5745 {
5746 /* For SPARC64, objects requiring 16-byte alignment get it. */
5747 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5748 align = 2 * UNITS_PER_WORD;
5749
5750 /* SPARC-V9 ABI states that structures up to 16 bytes in size
22d66adf 5751 are left-justified in their slots. */
5f393b25
JM		 5752 if (AGGREGATE_TYPE_P (type))
5753 {
5754 if (size == 0)
5755 size = rsize = UNITS_PER_WORD;
5756 else
5757 size = rsize;
5758 }
5759 }
5760 }
5761
5762 incr = valist;
5763 if (align)
5764 {
5be014d5
AP		 5765 incr = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr,
5766 size_int (align - 1));
5767 incr = fold_convert (sizetype, incr);
5768 incr = fold_build2 (BIT_AND_EXPR, sizetype, incr,
5769 size_int (-align));
5770 incr = fold_convert (ptr_type_node, incr);
5f393b25
JM		 5771 }
5772
5773 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
5774 addr = incr;
5775
5776 if (BYTES_BIG_ENDIAN && size < rsize)
5be014d5
AP		 5777 addr = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr,
5778 size_int (rsize - size));
5f393b25
JM		 5779
5780 if (indirect)
5781 {
5782 addr = fold_convert (build_pointer_type (ptrtype), addr);
22d66adf 5783 addr = build_va_arg_indirect_ref (addr);
5f393b25
JM		 5784 }
5785 /* If the address isn't aligned properly for the type,
5786 we may need to copy to a temporary.
5787 FIXME: This is inefficient. Usually we can do this
5788 in registers. */
5789 else if (align == 0
5790 && TYPE_ALIGN (type) > BITS_PER_WORD)
5791 {
5792 tree tmp = create_tmp_var (type, "va_arg_tmp");
5793 tree dest_addr = build_fold_addr_expr (tmp);
5794
5039610b
SL		 5795 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY], 3,
5796 dest_addr,
5797 addr,
5798 size_int (rsize));
5f393b25
JM		 5799
5800 gimplify_and_add (copy, pre_p);
5801 addr = dest_addr;
5802 }
5803 else
5804 addr = fold_convert (ptrtype, addr);
5805
5be014d5 5806 incr = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr, size_int (rsize));
726a989a 5807 gimplify_assign (valist, incr, post_p);
5f393b25 5808
22d66adf 5809 return build_va_arg_indirect_ref (addr);
5f393b25 5810}
ab835497 5811\f
c75d6010
JM		 5812/* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
5813 Specify whether the vector mode is supported by the hardware. */
5814
5815static bool
5816sparc_vector_mode_supported_p (enum machine_mode mode)
5817{
5818 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
5819}
5820\f
1b3c2c2d
EB		 5821/* Return the string to output an unconditional branch to LABEL, which is
5822 the operand number of the label.
5823
5824 DEST is the destination insn (i.e. the label), INSN is the source. */
5825
5826const char *
5827output_ubranch (rtx dest, int label, rtx insn)
5828{
5829 static char string[64];
4e5b002b 5830 bool v9_form = false;
1b3c2c2d
EB		 5831 char *p;
5832
4e5b002b 5833 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
1b3c2c2d 5834 {
4e5b002b
EB		 5835 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5836 - INSN_ADDRESSES (INSN_UID (insn)));
5837 /* Leave some instructions for "slop". */
5838 if (delta >= -260000 && delta < 260000)
5839 v9_form = true;
1b3c2c2d 5840 }
1b3c2c2d 5841
4e5b002b
EB		 5842 if (v9_form)
5843 strcpy (string, "ba%*,pt\t%%xcc, ");
5844 else
5845 strcpy (string, "b%*\t");
1b3c2c2d
EB		 5846
5847 p = strchr (string, '\0');
5848 *p++ = '%';
5849 *p++ = 'l';
5850 *p++ = '0' + label;
5851 *p++ = '%';
4e5b002b 5852 *p++ = '(';
1b3c2c2d
EB		 5853 *p = '\0';
5854
5855 return string;
5856}
5857
ab835497 5858/* Return the string to output a conditional branch to LABEL, which is
c4ce6853
DE		 5859 the operand number of the label. OP is the conditional expression.
5860 XEXP (OP, 0) is assumed to be a condition code register (integer or
5861 floating point) and its mode specifies what kind of comparison we made.
61a55e8b 5862
1b3c2c2d
EB		 5863 DEST is the destination insn (i.e. the label), INSN is the source.
5864
5e7a8ee0 5865 REVERSED is nonzero if we should reverse the sense of the comparison.
ab835497 5866
4e5b002b 5867 ANNUL is nonzero if we should generate an annulling branch. */
ab835497 5868
a6163c22 5869const char *
fc27d102 5870output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
4e5b002b 5871 rtx insn)
ab835497 5872{
a6163c22 5873 static char string[64];
ab835497 5874 enum rtx_code code = GET_CODE (op);
c4ce6853
DE		 5875 rtx cc_reg = XEXP (op, 0);
5876 enum machine_mode mode = GET_MODE (cc_reg);
0b82d204
JJ		 5877 const char *labelno, *branch;
5878 int spaces = 8, far;
5879 char *p;
5880
5881 /* v9 branches are limited to +-1MB. If it is too far away,
5882 change
5883
5884 bne,pt %xcc, .LC30
5885
5886 to
5887
5888 be,pn %xcc, .+12
a6163c22 5889 nop
0b82d204
JJ		 5890 ba .LC30
5891
5892 and
5893
5894 fbne,a,pn %fcc2, .LC29
61a55e8b 5895
0b82d204
JJ		 5896 to
5897
5898 fbe,pt %fcc2, .+16
a6163c22 5899 nop
0b82d204
JJ		 5900 ba .LC29 */
5901
883d9e0c 5902 far = TARGET_V9 && (get_attr_length (insn) >= 3);
0b82d204 5903 if (reversed ^ far)
ab835497 5904 {
e267e177
RH		 5905 /* Reversal of FP compares takes care -- an ordered compare
5906 becomes an unordered compare and vice versa. */
4d449554 5907 if (mode == CCFPmode || mode == CCFPEmode)
7913f3d0 5908 code = reverse_condition_maybe_unordered (code);
ab835497 5909 else
e267e177 5910 code = reverse_condition (code);
ab835497
RK		 5911 }
5912
e267e177
RH		 5913 /* Start by writing the branch condition. */
5914 if (mode == CCFPmode || mode == CCFPEmode)
5850dc00
RH		 5915 {
5916 switch (code)
5917 {
5918 case NE:
5919 branch = "fbne";
5920 break;
5921 case EQ:
5922 branch = "fbe";
5923 break;
5924 case GE:
5925 branch = "fbge";
5926 break;
5927 case GT:
5928 branch = "fbg";
5929 break;
5930 case LE:
5931 branch = "fble";
5932 break;
5933 case LT:
5934 branch = "fbl";
5935 break;
5936 case UNORDERED:
5937 branch = "fbu";
5938 break;
5939 case ORDERED:
5940 branch = "fbo";
5941 break;
5942 case UNGT:
5943 branch = "fbug";
5944 break;
5945 case UNLT:
5946 branch = "fbul";
5947 break;
5948 case UNEQ:
5949 branch = "fbue";
5950 break;
5951 case UNGE:
5952 branch = "fbuge";
5953 break;
5954 case UNLE:
5955 branch = "fbule";
5956 break;
5957 case LTGT:
5958 branch = "fblg";
5959 break;
5960
5961 default:
f5f7d171 5962 gcc_unreachable ();
5850dc00
RH		 5963 }
5964
5965 /* ??? !v9: FP branches cannot be preceded by another floating point
5966 insn. Because there is currently no concept of pre-delay slots,
5967 we can fix this only by always emitting a nop before a floating
5968 point branch. */
5969
5970 string[0] = '\0';
5971 if (! TARGET_V9)
5972 strcpy (string, "nop\n\t");
5973 strcat (string, branch);
5974 }
e267e177 5975 else
5850dc00
RH		 5976 {
5977 switch (code)
5978 {
5979 case NE:
5980 branch = "bne";
5981 break;
5982 case EQ:
5983 branch = "be";
5984 break;
5985 case GE:
0b82d204 5986 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5850dc00
RH		 5987 branch = "bpos";
5988 else
5989 branch = "bge";
5990 break;
5991 case GT:
5992 branch = "bg";
5993 break;
5994 case LE:
5995 branch = "ble";
5996 break;
5997 case LT:
0b82d204 5998 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5850dc00
RH		 5999 branch = "bneg";
6000 else
6001 branch = "bl";
6002 break;
6003 case GEU:
6004 branch = "bgeu";
6005 break;
6006 case GTU:
6007 branch = "bgu";
6008 break;
6009 case LEU:
6010 branch = "bleu";
6011 break;
6012 case LTU:
6013 branch = "blu";
6014 break;
6015
6016 default:
f5f7d171 6017 gcc_unreachable ();
5850dc00
RH		 6018 }
6019 strcpy (string, branch);
6020 }
e267e177 6021 spaces -= strlen (branch);
0b82d204 6022 p = strchr (string, '\0');
e267e177 6023
ab835497 6024 /* Now add the annulling, the label, and a possible noop. */
0b82d204 6025 if (annul && ! far)
e0d80184 6026 {
0b82d204
JJ		 6027 strcpy (p, ",a");
6028 p += 2;
e0d80184
DM		 6029 spaces -= 2;
6030 }
ab835497 6031
883d9e0c 6032 if (TARGET_V9)
61a55e8b 6033 {
c6b0465b 6034 rtx note;
0b82d204 6035 int v8 = 0;
c6b0465b 6036
0b82d204 6037 if (! far && insn && INSN_ADDRESSES_SET_P ())
e0d80184 6038 {
0b82d204
JJ		 6039 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6040 - INSN_ADDRESSES (INSN_UID (insn)));
6041 /* Leave some instructions for "slop". */
6042 if (delta < -260000 || delta >= 260000)
6043 v8 = 1;
e0d80184 6044 }
c6b0465b 6045
61a55e8b
DE		 6046 if (mode == CCFPmode || mode == CCFPEmode)
6047 {
0b82d204 6048 static char v9_fcc_labelno[] = "%%fccX, ";
61a55e8b 6049 /* Set the char indicating the number of the fcc reg to use. */
0b82d204
JJ		 6050 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6051 labelno = v9_fcc_labelno;
6052 if (v8)
6053 {
f5f7d171
JM		 6054 gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG);
6055 labelno = "";
0b82d204 6056 }
61a55e8b
DE		 6057 }
6058 else if (mode == CCXmode || mode == CCX_NOOVmode)
0b82d204
JJ		 6059 {
6060 labelno = "%%xcc, ";
f5f7d171 6061 gcc_assert (! v8);
0b82d204 6062 }
61a55e8b 6063 else
0b82d204
JJ		 6064 {
6065 labelno = "%%icc, ";
6066 if (v8)
6067 labelno = "";
6068 }
6069
4f31cce8 6070 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
0b82d204
JJ		 6071 {
6072 strcpy (p,
4f31cce8 6073 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
0b82d204
JJ		 6074 ? ",pt" : ",pn");
6075 p += 3;
6076 spaces -= 3;
6077 }
61a55e8b 6078 }
883d9e0c
EB		 6079 else
6080 labelno = "";
6081
e0d80184 6082 if (spaces > 0)
0b82d204 6083 *p++ = '\t';
e0d80184 6084 else
0b82d204
JJ		 6085 *p++ = ' ';
6086 strcpy (p, labelno);
6087 p = strchr (p, '\0');
6088 if (far)
6089 {
a6163c22 6090 strcpy (p, ".+12\n\t nop\n\tb\t");
4e5b002b
EB		 6091 /* Skip the next insn if requested or
6092 if we know that it will be a nop. */
6093 if (annul || ! final_sequence)
0b82d204 6094 p[3] = '6';
a6163c22 6095 p += 14;
0b82d204
JJ		 6096 }
6097 *p++ = '%';
6098 *p++ = 'l';
0b82d204 6099 *p++ = label + '0';
4e5b002b
EB		 6100 *p++ = '%';
6101 *p++ = '#';
0b82d204 6102 *p = '\0';
61a55e8b
DE		 6103
6104 return string;
6105}
6106
47ac041c 6107/* Emit a library call comparison between floating point X and Y.
19047e4a
EB		 6108 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
6109 Return the new operator to be used in the comparison sequence.
6110
47ac041c
JJ		 6111 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6112 values as arguments instead of the TFmode registers themselves,
6113 that's why we cannot call emit_float_lib_cmp. */
19047e4a
EB		 6114
6115enum rtx_code
fc27d102 6116sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
47ac041c 6117{
e77d72cb 6118 const char *qpfunc;
5c5c34a4
JJ		 6119 rtx slot0, slot1, result, tem, tem2;
6120 enum machine_mode mode;
19047e4a 6121 enum rtx_code new_comparison;
47ac041c
JJ		 6122
6123 switch (comparison)
6124 {
6125 case EQ:
19047e4a 6126 qpfunc = (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq");
47ac041c
JJ		 6127 break;
6128
6129 case NE:
19047e4a 6130 qpfunc = (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne");
47ac041c
JJ		 6131 break;
6132
6133 case GT:
19047e4a 6134 qpfunc = (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt");
47ac041c
JJ		 6135 break;
6136
6137 case GE:
19047e4a 6138 qpfunc = (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge");
47ac041c
JJ		 6139 break;
6140
6141 case LT:
19047e4a 6142 qpfunc = (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt");
47ac041c
JJ		 6143 break;
6144
6145 case LE:
19047e4a 6146 qpfunc = (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle");
5c5c34a4
JJ		 6147 break;
6148
6149 case ORDERED:
6150 case UNORDERED:
6151 case UNGT:
6152 case UNLT:
6153 case UNEQ:
6154 case UNGE:
6155 case UNLE:
6156 case LTGT:
19047e4a 6157 qpfunc = (TARGET_ARCH64 ? "_Qp_cmp" : "_Q_cmp");
47ac041c
JJ		 6158 break;
6159
6160 default:
f5f7d171 6161 gcc_unreachable ();
47ac041c
JJ		 6162 }
6163
5c5c34a4 6164 if (TARGET_ARCH64)
47ac041c 6165 {
19047e4a
EB		 6166 if (MEM_P (x))
6167 slot0 = x;
6168 else
5c5c34a4
JJ		 6169 {
6170 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
c5d74498 6171 emit_move_insn (slot0, x);
5c5c34a4 6172 }
5c5c34a4 6173
19047e4a
EB		 6174 if (MEM_P (y))
6175 slot1 = y;
6176 else
5c5c34a4
JJ		 6177 {
6178 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
c5d74498 6179 emit_move_insn (slot1, y);
5c5c34a4 6180 }
47ac041c 6181
eb29ddb6 6182 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5c5c34a4
JJ		 6183 DImode, 2,
6184 XEXP (slot0, 0), Pmode,
6185 XEXP (slot1, 0), Pmode);
5c5c34a4
JJ		 6186 mode = DImode;
6187 }
6188 else
47ac041c 6189 {
eb29ddb6 6190 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5c5c34a4
JJ		 6191 SImode, 2,
6192 x, TFmode, y, TFmode);
5c5c34a4 6193 mode = SImode;
47ac041c
JJ		 6194 }
6195
47ac041c
JJ		 6196
6197 /* Immediately move the result of the libcall into a pseudo
6198 register so reload doesn't clobber the value if it needs
6199 the return register for a spill reg. */
5c5c34a4
JJ		 6200 result = gen_reg_rtx (mode);
6201 emit_move_insn (result, hard_libcall_value (mode));
47ac041c 6202
5c5c34a4
JJ		 6203 switch (comparison)
6204 {
6205 default:
19047e4a
EB		 6206 new_comparison = NE;
6207 emit_cmp_insn (result, const0_rtx, new_comparison, NULL_RTX, mode, 0);
5c5c34a4
JJ		 6208 break;
6209 case ORDERED:
6210 case UNORDERED:
19047e4a
EB		 6211 new_comparison = (comparison == UNORDERED ? EQ : NE);
6212 emit_cmp_insn (result, GEN_INT(3), new_comparison, NULL_RTX, mode, 0);
5c5c34a4
JJ		 6213 break;
6214 case UNGT:
6215 case UNGE:
19047e4a
EB		 6216 new_comparison = (comparison == UNGT ? GT : NE);
6217 emit_cmp_insn (result, const1_rtx, new_comparison, NULL_RTX, mode, 0);
5c5c34a4
JJ		 6218 break;
6219 case UNLE:
19047e4a
EB		 6220 new_comparison = NE;
6221 emit_cmp_insn (result, const2_rtx, new_comparison, NULL_RTX, mode, 0);
5c5c34a4
JJ		 6222 break;
6223 case UNLT:
6224 tem = gen_reg_rtx (mode);
6225 if (TARGET_ARCH32)
6226 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6227 else
6228 emit_insn (gen_anddi3 (tem, result, const1_rtx));
19047e4a
EB		 6229 new_comparison = NE;
6230 emit_cmp_insn (tem, const0_rtx, new_comparison, NULL_RTX, mode, 0);
5c5c34a4
JJ		 6231 break;
6232 case UNEQ:
6233 case LTGT:
6234 tem = gen_reg_rtx (mode);
6235 if (TARGET_ARCH32)
6236 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6237 else
6238 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6239 tem2 = gen_reg_rtx (mode);
6240 if (TARGET_ARCH32)
6241 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6242 else
6243 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
19047e4a
EB		 6244 new_comparison = (comparison == UNEQ ? EQ : NE);
6245 emit_cmp_insn (tem2, const0_rtx, new_comparison, NULL_RTX, mode, 0);
5c5c34a4
JJ		 6246 break;
6247 }
19047e4a
EB		 6248
6249 return new_comparison;
47ac041c 6250}
5c5c34a4 6251
d88e57d1
RH		 6252/* Generate an unsigned DImode to FP conversion. This is the same code
6253 optabs would emit if we didn't have TFmode patterns. */
6254
6255void
b178305d 6256sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
d88e57d1
RH		 6257{
6258 rtx neglab, donelab, i0, i1, f0, in, out;
d88e57d1
RH		 6259
6260 out = operands[0];
6261 in = force_reg (DImode, operands[1]);
d88e57d1
RH		 6262 neglab = gen_label_rtx ();
6263 donelab = gen_label_rtx ();
6264 i0 = gen_reg_rtx (DImode);
6265 i1 = gen_reg_rtx (DImode);
6266 f0 = gen_reg_rtx (mode);
6267
6268 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6269
6270 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6271 emit_jump_insn (gen_jump (donelab));
6272 emit_barrier ();
6273
6274 emit_label (neglab);
6275
6276 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6277 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6278 emit_insn (gen_iordi3 (i0, i0, i1));
6279 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6280 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6281
6282 emit_label (donelab);
6283}
6284
b178305d
EB		 6285/* Generate an FP to unsigned DImode conversion. This is the same code
6286 optabs would emit if we didn't have TFmode patterns. */
6287
6288void
6289sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
6290{
6291 rtx neglab, donelab, i0, i1, f0, in, out, limit;
6292
6293 out = operands[0];
6294 in = force_reg (mode, operands[1]);
6295 neglab = gen_label_rtx ();
6296 donelab = gen_label_rtx ();
6297 i0 = gen_reg_rtx (DImode);
6298 i1 = gen_reg_rtx (DImode);
6299 limit = gen_reg_rtx (mode);
6300 f0 = gen_reg_rtx (mode);
6301
6302 emit_move_insn (limit,
6303 CONST_DOUBLE_FROM_REAL_VALUE (
6304 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
6305 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
6306
6307 emit_insn (gen_rtx_SET (VOIDmode,
6308 out,
6309 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
6310 emit_jump_insn (gen_jump (donelab));
6311 emit_barrier ();
6312
6313 emit_label (neglab);
6314
6315 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
6316 emit_insn (gen_rtx_SET (VOIDmode,
6317 i0,
6318 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6319 emit_insn (gen_movdi (i1, const1_rtx));
6320 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6321 emit_insn (gen_xordi3 (out, i0, i1));
6322
6323 emit_label (donelab);
6324}
6325
61a55e8b
DE		 6326/* Return the string to output a conditional branch to LABEL, testing
6327 register REG. LABEL is the operand number of the label; REG is the
6328 operand number of the reg. OP is the conditional expression. The mode
6329 of REG says what kind of comparison we made.
6330
1b3c2c2d
EB		 6331 DEST is the destination insn (i.e. the label), INSN is the source.
6332
5e7a8ee0 6333 REVERSED is nonzero if we should reverse the sense of the comparison.
61a55e8b 6334
4e5b002b 6335 ANNUL is nonzero if we should generate an annulling branch. */
61a55e8b 6336
a6163c22 6337const char *
fc27d102 6338output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
4e5b002b 6339 int annul, rtx insn)
61a55e8b 6340{
a6163c22 6341 static char string[64];
61a55e8b
DE		 6342 enum rtx_code code = GET_CODE (op);
6343 enum machine_mode mode = GET_MODE (XEXP (op, 0));
e0d80184 6344 rtx note;
0b82d204
JJ		 6345 int far;
6346 char *p;
6347
6348 /* branch on register are limited to +-128KB. If it is too far away,
6349 change
6350
6351 brnz,pt %g1, .LC30
6352
6353 to
6354
6355 brz,pn %g1, .+12
a6163c22 6356 nop
0b82d204
JJ		 6357 ba,pt %xcc, .LC30
6358
6359 and
6360
6361 brgez,a,pn %o1, .LC29
6362
6363 to
6364
6365 brlz,pt %o1, .+16
a6163c22 6366 nop
0b82d204
JJ		 6367 ba,pt %xcc, .LC29 */
6368
6369 far = get_attr_length (insn) >= 3;
61a55e8b
DE		 6370
6371 /* If not floating-point or if EQ or NE, we can just reverse the code. */
0b82d204
JJ		 6372 if (reversed ^ far)
6373 code = reverse_condition (code);
61a55e8b
DE		 6374
6375 /* Only 64 bit versions of these instructions exist. */
f5f7d171 6376 gcc_assert (mode == DImode);
61a55e8b
DE		 6377
6378 /* Start by writing the branch condition. */
6379
6380 switch (code)
6381 {
6382 case NE:
6383 strcpy (string, "brnz");
6384 break;
6385
6386 case EQ:
6387 strcpy (string, "brz");
6388 break;
6389
6390 case GE:
6391 strcpy (string, "brgez");
6392 break;
6393
6394 case LT:
6395 strcpy (string, "brlz");
6396 break;
6397
6398 case LE:
6399 strcpy (string, "brlez");
6400 break;
6401
6402 case GT:
6403 strcpy (string, "brgz");
6404 break;
6405
6406 default:
f5f7d171 6407 gcc_unreachable ();
61a55e8b
DE		 6408 }
6409
0b82d204
JJ		 6410 p = strchr (string, '\0');
6411
61a55e8b 6412 /* Now add the annulling, reg, label, and nop. */
0b82d204 6413 if (annul && ! far)
e0d80184 6414 {
0b82d204
JJ		 6415 strcpy (p, ",a");
6416 p += 2;
e0d80184 6417 }
61a55e8b 6418
4f31cce8 6419 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
e0d80184 6420 {
0b82d204 6421 strcpy (p,
4f31cce8 6422 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
0b82d204
JJ		 6423 ? ",pt" : ",pn");
6424 p += 3;
e0d80184 6425 }
61a55e8b 6426
0b82d204
JJ		 6427 *p = p < string + 8 ? '\t' : ' ';
6428 p++;
6429 *p++ = '%';
6430 *p++ = '0' + reg;
6431 *p++ = ',';
6432 *p++ = ' ';
6433 if (far)
6434 {
6435 int veryfar = 1, delta;
6436
6437 if (INSN_ADDRESSES_SET_P ())
6438 {
6439 delta = (INSN_ADDRESSES (INSN_UID (dest))
6440 - INSN_ADDRESSES (INSN_UID (insn)));
6441 /* Leave some instructions for "slop". */
6442 if (delta >= -260000 && delta < 260000)
6443 veryfar = 0;
6444 }
6445
a6163c22 6446 strcpy (p, ".+12\n\t nop\n\t");
4e5b002b
EB		 6447 /* Skip the next insn if requested or
6448 if we know that it will be a nop. */
6449 if (annul || ! final_sequence)
0b82d204 6450 p[3] = '6';
a6163c22 6451 p += 12;
0b82d204
JJ		 6452 if (veryfar)
6453 {
6454 strcpy (p, "b\t");
6455 p += 2;
6456 }
6457 else
6458 {
6459 strcpy (p, "ba,pt\t%%xcc, ");
6460 p += 13;
6461 }
6462 }
6463 *p++ = '%';
6464 *p++ = 'l';
6465 *p++ = '0' + label;
4e5b002b
EB		 6466 *p++ = '%';
6467 *p++ = '#';
0b82d204 6468 *p = '\0';
ab835497 6469
ab835497
RK		 6470 return string;
6471}
6472
e48addee
JJ		 6473/* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6474 Such instructions cannot be used in the delay slot of return insn on v9.
6475 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6476 */
284d86e9 6477
e48addee 6478static int
fc27d102 6479epilogue_renumber (register rtx *where, int test)
284d86e9 6480{
e48addee
JJ		 6481 register const char *fmt;
6482 register int i;
6483 register enum rtx_code code;
6484
6485 if (*where == 0)
6486 return 0;
6487
6488 code = GET_CODE (*where);
284d86e9
JC		 6489
6490 switch (code)
6491 {
284d86e9 6492 case REG:
e48addee
JJ		 6493 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6494 return 1;
6495 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
f1c25d3b 6496 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
e48addee
JJ		 6497 case SCRATCH:
6498 case CC0:
6499 case PC:
284d86e9
JC		 6500 case CONST_INT:
6501 case CONST_DOUBLE:
e48addee 6502 return 0;
76a7c776 6503
09ebda1b
SC		 6504 /* Do not replace the frame pointer with the stack pointer because
6505 it can cause the delayed instruction to load below the stack.
6506 This occurs when instructions like:
6507
6508 (set (reg/i:SI 24 %i0)
6509 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6510 (const_int -20 [0xffffffec])) 0))
6511
6512 are in the return delayed slot. */
6513 case PLUS:
6514 if (GET_CODE (XEXP (*where, 0)) == REG
563c12b0 6515 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
09ebda1b
SC		 6516 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6517 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6518 return 1;
6519 break;
6520
6521 case MEM:
6522 if (SPARC_STACK_BIAS
6523 && GET_CODE (XEXP (*where, 0)) == REG
563c12b0 6524 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
09ebda1b
SC		 6525 return 1;
6526 break;
6527
76a7c776
DM		 6528 default:
6529 break;
e48addee 6530 }
284d86e9 6531
e48addee 6532 fmt = GET_RTX_FORMAT (code);
284d86e9 6533
e48addee
JJ		 6534 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6535 {
6536 if (fmt[i] == 'E')
6537 {
6538 register int j;
6539 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6540 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6541 return 1;
6542 }
6543 else if (fmt[i] == 'e'
6544 && epilogue_renumber (&(XEXP (*where, i)), test))
6545 return 1;
284d86e9 6546 }
e48addee 6547 return 0;
284d86e9 6548}
ab835497
RK		 6549\f
6550/* Leaf functions and non-leaf functions have different needs. */
6551
8b60264b 6552static const int
ab835497
RK		 6553reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6554
8b60264b 6555static const int
ab835497
RK		 6556reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6557
8b60264b 6558static const int *const reg_alloc_orders[] = {
ab835497
RK		 6559 reg_leaf_alloc_order,
6560 reg_nonleaf_alloc_order};
6561
6562void
fc27d102 6563order_regs_for_local_alloc (void)
ab835497
RK		 6564{
6565 static int last_order_nonleaf = 1;
6566
6fb5fa3c 6567 if (df_regs_ever_live_p (15) != last_order_nonleaf)
ab835497
RK		 6568 {
6569 last_order_nonleaf = !last_order_nonleaf;
2e09e75a 6570 memcpy ((char *) reg_alloc_order,
8b60264b 6571 (const char *) reg_alloc_orders[last_order_nonleaf],
2e09e75a 6572 FIRST_PSEUDO_REGISTER * sizeof (int));
ab835497
RK		 6573 }
6574}
6575\f
e0d80184
DM		 6576/* Return 1 if REG and MEM are legitimate enough to allow the various
6577 mem<-->reg splits to be run. */
6578
6579int
fc27d102 6580sparc_splitdi_legitimate (rtx reg, rtx mem)
e0d80184 6581{
e0d80184 6582 /* Punt if we are here by mistake. */
f5f7d171 6583 gcc_assert (reload_completed);
e0d80184
DM		 6584
6585 /* We must have an offsettable memory reference. */
6586 if (! offsettable_memref_p (mem))
6587 return 0;
6588
6589 /* If we have legitimate args for ldd/std, we do not want
6590 the split to happen. */
6591 if ((REGNO (reg) % 2) == 0
6592 && mem_min_alignment (mem, 8))
6593 return 0;
6594
6595 /* Success. */
6596 return 1;
6597}
6598
e61c29e9 6599/* Return 1 if x and y are some kind of REG and they refer to
fae778eb 6600 different hard registers. This test is guaranteed to be
e61c29e9
DM		 6601 run after reload. */
6602
6603int
fc27d102 6604sparc_absnegfloat_split_legitimate (rtx x, rtx y)
e61c29e9 6605{
e61c29e9
DM		 6606 if (GET_CODE (x) != REG)
6607 return 0;
e61c29e9
DM		 6608 if (GET_CODE (y) != REG)
6609 return 0;
6610 if (REGNO (x) == REGNO (y))
6611 return 0;
6612 return 1;
6613}
6614
35016322
JW		 6615/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6616 This makes them candidates for using ldd and std insns.
6617
bfd6bc60 6618 Note reg1 and reg2 *must* be hard registers. */
35016322
JW		 6619
6620int
fc27d102 6621registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
35016322 6622{
35016322
JW		 6623 /* We might have been passed a SUBREG. */
6624 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6625 return 0;
6626
35016322
JW		 6627 if (REGNO (reg1) % 2 != 0)
6628 return 0;
6629
bfd6bc60
JC		 6630 /* Integer ldd is deprecated in SPARC V9 */
6631 if (TARGET_V9 && REGNO (reg1) < 32)
6632 return 0;
6633
35016322 6634 return (REGNO (reg1) == REGNO (reg2) - 1);
35016322
JW		 6635}
6636
2aad5d68 6637/* Return 1 if the addresses in mem1 and mem2 are suitable for use in
303f8933
DN		 6638 an ldd or std insn.
6639
2aad5d68
DN		 6640 This can only happen when addr1 and addr2, the addresses in mem1
6641 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
303f8933
DN		 6642 addr1 must also be aligned on a 64-bit boundary.
6643
6644 Also iff dependent_reg_rtx is not null it should not be used to
6645 compute the address for mem1, i.e. we cannot optimize a sequence
6646 like:
6647 ld [%o0], %o0
6648 ld [%o0 + 4], %o1
6649 to
bcdd764b 6650 ldd [%o0], %o0
0acf409f
DM		 6651 nor:
6652 ld [%g3 + 4], %g3
6653 ld [%g3], %g2
6654 to
6655 ldd [%g3], %g2
6656
6657 But, note that the transformation from:
6658 ld [%g2 + 4], %g3
6659 ld [%g2], %g2
6660 to
6661 ldd [%g2], %g2
6662 is perfectly fine. Thus, the peephole2 patterns always pass us
6663 the destination register of the first load, never the second one.
6664
303f8933
DN		 6665 For stores we don't have a similar problem, so dependent_reg_rtx is
6666 NULL_RTX. */
35016322
JW		 6667
6668int
fc27d102 6669mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
35016322 6670{
2aad5d68 6671 rtx addr1, addr2;
0d587737 6672 unsigned int reg1;
6a151f87 6673 HOST_WIDE_INT offset1;
35016322 6674
303f8933
DN		 6675 /* The mems cannot be volatile. */
6676 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6677 return 0;
2aad5d68 6678
303f8933 6679 /* MEM1 should be aligned on a 64-bit boundary. */
2aad5d68
DN		 6680 if (MEM_ALIGN (mem1) < 64)
6681 return 0;
6682
303f8933
DN		 6683 addr1 = XEXP (mem1, 0);
6684 addr2 = XEXP (mem2, 0);
6685
35016322
JW		 6686 /* Extract a register number and offset (if used) from the first addr. */
6687 if (GET_CODE (addr1) == PLUS)
6688 {
6689 /* If not a REG, return zero. */
6690 if (GET_CODE (XEXP (addr1, 0)) != REG)
6691 return 0;
6692 else
6693 {
6694 reg1 = REGNO (XEXP (addr1, 0));
6695 /* The offset must be constant! */
6696 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6697 return 0;
6698 offset1 = INTVAL (XEXP (addr1, 1));
6699 }
6700 }
6701 else if (GET_CODE (addr1) != REG)
6702 return 0;
6703 else
6704 {
6705 reg1 = REGNO (addr1);
6706 /* This was a simple (mem (reg)) expression. Offset is 0. */
6707 offset1 = 0;
6708 }
6709
6710 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6711 if (GET_CODE (addr2) != PLUS)
6712 return 0;
6713
6714 if (GET_CODE (XEXP (addr2, 0)) != REG
6715 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6716 return 0;
6717
35016322
JW		 6718 if (reg1 != REGNO (XEXP (addr2, 0)))
6719 return 0;
6720
303f8933
DN		 6721 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6722 return 0;
6723
2296cba3 6724 /* The first offset must be evenly divisible by 8 to ensure the
35016322
JW		 6725 address is 64 bit aligned. */
6726 if (offset1 % 8 != 0)
6727 return 0;
6728
6729 /* The offset for the second addr must be 4 more than the first addr. */
6730 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6731 return 0;
6732
6733 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6734 instructions. */
6735 return 1;
6736}
7c56249d 6737
157891a3
EB		 6738/* Return 1 if reg is a pseudo, or is the first register in
6739 a hard register pair. This makes it suitable for use in
7c56249d
JL		 6740 ldd and std insns. */
6741
6742int
fc27d102 6743register_ok_for_ldd (rtx reg)
7c56249d 6744{
7c56249d 6745 /* We might have been passed a SUBREG. */
157891a3 6746 if (!REG_P (reg))
7c56249d
JL		 6747 return 0;
6748
6749 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6750 return (REGNO (reg) % 2 == 0);
157891a3
EB		 6751
6752 return 1;
6753}
6754
6755/* Return 1 if OP is a memory whose address is known to be
6756 aligned to 8-byte boundary, or a pseudo during reload.
6757 This makes it suitable for use in ldd and std insns. */
6758
6759int
6760memory_ok_for_ldd (rtx op)
6761{
6762 if (MEM_P (op))
6763 {
6764 /* In 64-bit mode, we assume that the address is word-aligned. */
6765 if (TARGET_ARCH32 && !mem_min_alignment (op, 8))
6766 return 0;
6767
6768 if ((reload_in_progress || reload_completed)
6769 && !strict_memory_address_p (Pmode, XEXP (op, 0)))
6770 return 0;
6771 }
6772 else if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
6773 {
6774 if (!(reload_in_progress && reg_renumber [REGNO (op)] < 0))
6775 return 0;
6776 }
6777 else
6778 return 0;
6779
6780 return 1;
7c56249d 6781}
ab835497 6782\f
ab835497
RK		 6783/* Print operand X (an rtx) in assembler syntax to file FILE.
6784 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6785 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6786
6787void
fc27d102 6788print_operand (FILE *file, rtx x, int code)
ab835497
RK		 6789{
6790 switch (code)
6791 {
6792 case '#':
4e5b002b
EB		 6793 /* Output an insn in a delay slot. */
6794 if (final_sequence)
6795 sparc_indent_opcode = 1;
6796 else
e0d80184 6797 fputs ("\n\t nop", file);
ab835497
RK		 6798 return;
6799 case '*':
c6ce0969 6800 /* Output an annul flag if there's nothing for the delay slot and we
4e5b002b
EB		 6801 are optimizing. This is always used with '(' below.
6802 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6803 this is a dbx bug. So, we only do this when optimizing.
6804 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
bfd6bc60 6805 Always emit a nop in case the next instruction is a branch. */
4e5b002b 6806 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9))
c6ce0969
JW		 6807 fputs (",a", file);
6808 return;
6809 case '(':
6810 /* Output a 'nop' if there's nothing for the delay slot and we are
6811 not optimizing. This is always used with '*' above. */
4e5b002b 6812 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
e0d80184 6813 fputs ("\n\t nop", file);
4e5b002b
EB		 6814 else if (final_sequence)
6815 sparc_indent_opcode = 1;
6816 return;
6817 case ')':
6818 /* Output the right displacement from the saved PC on function return.
6819 The caller may have placed an "unimp" insn immediately after the call
6820 so we have to account for it. This insn is used in the 32-bit ABI
6821 when calling a function that returns a non zero-sized structure. The
6822 64-bit ABI doesn't have it. Be careful to have this test be the same
2225b57c
CD		 6823 as that used on the call. The exception here is that when
6824 sparc_std_struct_return is enabled, the psABI is followed exactly
6825 and the adjustment is made by the code in sparc_struct_value_rtx.
6826 The call emitted is the same when sparc_std_struct_return is
6827 present. */
4e5b002b 6828 if (! TARGET_ARCH64
e3b5732b 6829 && cfun->returns_struct
2225b57c 6830 && ! sparc_std_struct_return
4e5b002b
EB		 6831 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
6832 == INTEGER_CST)
6833 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))))
6834 fputs ("12", file);
6835 else
6836 fputc ('8', file);
ab835497 6837 return;
61a55e8b 6838 case '_':
a0a301fc
DE		 6839 /* Output the Embedded Medium/Anywhere code model base register. */
6840 fputs (EMBMEDANY_BASE_REG, file);
61a55e8b 6841 return;
5751a10b
JJ		 6842 case '&':
6843 /* Print some local dynamic TLS name. */
6844 assemble_name (file, get_some_local_dynamic_name ());
6845 return;
4e5b002b 6846
ab835497
RK		 6847 case 'Y':
6848 /* Adjust the operand to take into account a RESTORE operation. */
bfd6bc60
JC		 6849 if (GET_CODE (x) == CONST_INT)
6850 break;
6851 else if (GET_CODE (x) != REG)
c725bd79 6852 output_operand_lossage ("invalid %%Y operand");
b3b1e8bd 6853 else if (REGNO (x) < 8)
ab835497
RK		 6854 fputs (reg_names[REGNO (x)], file);
6855 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6856 fputs (reg_names[REGNO (x)-16], file);
6857 else
c725bd79 6858 output_operand_lossage ("invalid %%Y operand");
ab835497 6859 return;
0f39a9aa
DE		 6860 case 'L':
6861 /* Print out the low order register name of a register pair. */
6862 if (WORDS_BIG_ENDIAN)
6863 fputs (reg_names[REGNO (x)+1], file);
6864 else
6865 fputs (reg_names[REGNO (x)], file);
6866 return;
6867 case 'H':
6868 /* Print out the high order register name of a register pair. */
6869 if (WORDS_BIG_ENDIAN)
6870 fputs (reg_names[REGNO (x)], file);
6871 else
6872 fputs (reg_names[REGNO (x)+1], file);
6873 return;
ab835497 6874 case 'R':
795068a4 6875 /* Print out the second register name of a register pair or quad.
ab835497
RK		 6876 I.e., R (%o0) => %o1. */
6877 fputs (reg_names[REGNO (x)+1], file);
6878 return;
795068a4
JW		 6879 case 'S':
6880 /* Print out the third register name of a register quad.
6881 I.e., S (%o0) => %o2. */
6882 fputs (reg_names[REGNO (x)+2], file);
6883 return;
6884 case 'T':
6885 /* Print out the fourth register name of a register quad.
6886 I.e., T (%o0) => %o3. */
6887 fputs (reg_names[REGNO (x)+3], file);
6888 return;
304b7a23
DE		 6889 case 'x':
6890 /* Print a condition code register. */
6891 if (REGNO (x) == SPARC_ICC_REG)
6892 {
6893 /* We don't handle CC[X]_NOOVmode because they're not supposed
6894 to occur here. */
6895 if (GET_MODE (x) == CCmode)
6896 fputs ("%icc", file);
6897 else if (GET_MODE (x) == CCXmode)
6898 fputs ("%xcc", file);
6899 else
f5f7d171 6900 gcc_unreachable ();
304b7a23
DE		 6901 }
6902 else
6903 /* %fccN register */
6904 fputs (reg_names[REGNO (x)], file);
6905 return;
ab835497
RK		 6906 case 'm':
6907 /* Print the operand's address only. */
6908 output_address (XEXP (x, 0));
6909 return;
6910 case 'r':
6911 /* In this case we need a register. Use %g0 if the
77a02b01 6912 operand is const0_rtx. */
76052e74
RS		 6913 if (x == const0_rtx
6914 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
ab835497
RK		 6915 {
6916 fputs ("%g0", file);
6917 return;
6918 }
6919 else
6920 break;
6921
61a55e8b 6922 case 'A':
ab835497
RK		 6923 switch (GET_CODE (x))
6924 {
6925 case IOR: fputs ("or", file); break;
6926 case AND: fputs ("and", file); break;
6927 case XOR: fputs ("xor", file); break;
c725bd79 6928 default: output_operand_lossage ("invalid %%A operand");
ab835497
RK		 6929 }
6930 return;
6931
6932 case 'B':
6933 switch (GET_CODE (x))
6934 {
6935 case IOR: fputs ("orn", file); break;
6936 case AND: fputs ("andn", file); break;
6937 case XOR: fputs ("xnor", file); break;
c725bd79 6938 default: output_operand_lossage ("invalid %%B operand");
ab835497
RK		 6939 }
6940 return;
6941
304b7a23
DE		 6942 /* These are used by the conditional move instructions. */
6943 case 'c' :
61a55e8b 6944 case 'C':
304b7a23 6945 {
5c5c34a4
JJ		 6946 enum rtx_code rc = GET_CODE (x);
6947
6948 if (code == 'c')
6949 {
6950 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6951 if (mode == CCFPmode || mode == CCFPEmode)
6952 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6953 else
6954 rc = reverse_condition (GET_CODE (x));
6955 }
304b7a23
DE		 6956 switch (rc)
6957 {
6958 case NE: fputs ("ne", file); break;
6959 case EQ: fputs ("e", file); break;
6960 case GE: fputs ("ge", file); break;
6961 case GT: fputs ("g", file); break;
6962 case LE: fputs ("le", file); break;
6963 case LT: fputs ("l", file); break;
6964 case GEU: fputs ("geu", file); break;
6965 case GTU: fputs ("gu", file); break;
6966 case LEU: fputs ("leu", file); break;
6967 case LTU: fputs ("lu", file); break;
5c5c34a4
JJ		 6968 case LTGT: fputs ("lg", file); break;
6969 case UNORDERED: fputs ("u", file); break;
6970 case ORDERED: fputs ("o", file); break;
6971 case UNLT: fputs ("ul", file); break;
6972 case UNLE: fputs ("ule", file); break;
6973 case UNGT: fputs ("ug", file); break;
6974 case UNGE: fputs ("uge", file); break;
6975 case UNEQ: fputs ("ue", file); break;
304b7a23 6976 default: output_operand_lossage (code == 'c'
c725bd79
NB		 6977 ? "invalid %%c operand"
6978 : "invalid %%C operand");
304b7a23
DE		 6979 }
6980 return;
6981 }
6982
6983 /* These are used by the movr instruction pattern. */
6984 case 'd':
61a55e8b 6985 case 'D':
304b7a23
DE		 6986 {
6987 enum rtx_code rc = (code == 'd'
6988 ? reverse_condition (GET_CODE (x))
6989 : GET_CODE (x));
6990 switch (rc)
6991 {
6992 case NE: fputs ("ne", file); break;
6993 case EQ: fputs ("e", file); break;
6994 case GE: fputs ("gez", file); break;
6995 case LT: fputs ("lz", file); break;
6996 case LE: fputs ("lez", file); break;
6997 case GT: fputs ("gz", file); break;
6998 default: output_operand_lossage (code == 'd'
c725bd79
NB		 6999 ? "invalid %%d operand"
7000 : "invalid %%D operand");
304b7a23
DE		 7001 }
7002 return;
7003 }
61a55e8b 7004
ab835497
RK		 7005 case 'b':
7006 {
7007 /* Print a sign-extended character. */
9e0625a3 7008 int i = trunc_int_for_mode (INTVAL (x), QImode);
ab835497
RK		 7009 fprintf (file, "%d", i);
7010 return;
7011 }
7012
d2889939
RK		 7013 case 'f':
7014 /* Operand must be a MEM; write its address. */
7015 if (GET_CODE (x) != MEM)
c725bd79 7016 output_operand_lossage ("invalid %%f operand");
d2889939
RK		 7017 output_address (XEXP (x, 0));
7018 return;
7019
8707fe93
RH		 7020 case 's':
7021 {
7022 /* Print a sign-extended 32-bit value. */
7023 HOST_WIDE_INT i;
7024 if (GET_CODE(x) == CONST_INT)
7025 i = INTVAL (x);
7026 else if (GET_CODE(x) == CONST_DOUBLE)
7027 i = CONST_DOUBLE_LOW (x);
7028 else
ffa916ba
KG		 7029 {
7030 output_operand_lossage ("invalid %%s operand");
7031 return;
7032 }
8707fe93
RH		 7033 i = trunc_int_for_mode (i, SImode);
7034 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7035 return;
7036 }
7037
ab835497
RK		 7038 case 0:
7039 /* Do nothing special. */
7040 break;
7041
7042 default:
7043 /* Undocumented flag. */
415f583e 7044 output_operand_lossage ("invalid operand output code");
ab835497
RK		 7045 }
7046
7047 if (GET_CODE (x) == REG)
7048 fputs (reg_names[REGNO (x)], file);
7049 else if (GET_CODE (x) == MEM)
7050 {
7051 fputc ('[', file);
ab835497 7052 /* Poor Sun assembler doesn't understand absolute addressing. */
e6c1be7e 7053 if (CONSTANT_P (XEXP (x, 0)))
ab835497
RK		 7054 fputs ("%g0+", file);
7055 output_address (XEXP (x, 0));
7056 fputc (']', file);
7057 }
7058 else if (GET_CODE (x) == HIGH)
7059 {
7060 fputs ("%hi(", file);
7061 output_addr_const (file, XEXP (x, 0));
7062 fputc (')', file);
7063 }
7064 else if (GET_CODE (x) == LO_SUM)
7065 {
7066 print_operand (file, XEXP (x, 0), 0);
e0d80184
DM		 7067 if (TARGET_CM_MEDMID)
7068 fputs ("+%l44(", file);
7069 else
7070 fputs ("+%lo(", file);
ab835497
RK		 7071 output_addr_const (file, XEXP (x, 1));
7072 fputc (')', file);
7073 }
e601abce
JW		 7074 else if (GET_CODE (x) == CONST_DOUBLE
7075 && (GET_MODE (x) == VOIDmode
7076 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
ab835497
RK		 7077 {
7078 if (CONST_DOUBLE_HIGH (x) == 0)
0d9484c5 7079 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
ab835497
RK		 7080 else if (CONST_DOUBLE_HIGH (x) == -1
7081 && CONST_DOUBLE_LOW (x) < 0)
0d9484c5 7082 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
ab835497 7083 else
e601abce 7084 output_operand_lossage ("long long constant not a valid immediate operand");
ab835497 7085 }
e601abce
JW		 7086 else if (GET_CODE (x) == CONST_DOUBLE)
7087 output_operand_lossage ("floating point constant not a valid immediate operand");
ab835497
RK		 7088 else { output_addr_const (file, x); }
7089}
7090\f
301d03af
RS		 7091/* Target hook for assembling integer objects. The sparc version has
7092 special handling for aligned DI-mode objects. */
ab835497 7093
301d03af 7094static bool
fc27d102 7095sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
ab835497 7096{
301d03af
RS		 7097 /* ??? We only output .xword's for symbols and only then in environments
7098 where the assembler can handle them. */
7099 if (aligned_p && size == 8
7100 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
ab835497 7101 {
301d03af 7102 if (TARGET_V9)
61a55e8b 7103 {
301d03af
RS		 7104 assemble_integer_with_op ("\t.xword\t", x);
7105 return true;
61a55e8b
DE		 7106 }
7107 else
7108 {
301d03af
RS		 7109 assemble_aligned_integer (4, const0_rtx);
7110 assemble_aligned_integer (4, x);
7111 return true;
61a55e8b 7112 }
ab835497 7113 }
301d03af 7114 return default_assemble_integer (x, size, aligned_p);
ab835497 7115}
210aa14a 7116\f
b0468b84
RK		 7117/* Return the value of a code used in the .proc pseudo-op that says
7118 what kind of result this function returns. For non-C types, we pick
7119 the closest C type. */
7120
77a02b01
JW		 7121#ifndef SHORT_TYPE_SIZE
7122#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7123#endif
7124
7125#ifndef INT_TYPE_SIZE
7126#define INT_TYPE_SIZE BITS_PER_WORD
7127#endif
7128
7129#ifndef LONG_TYPE_SIZE
7130#define LONG_TYPE_SIZE BITS_PER_WORD
7131#endif
7132
7133#ifndef LONG_LONG_TYPE_SIZE
7134#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7135#endif
7136
7137#ifndef FLOAT_TYPE_SIZE
7138#define FLOAT_TYPE_SIZE BITS_PER_WORD
7139#endif
7140
7141#ifndef DOUBLE_TYPE_SIZE
7142#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7143#endif
7144
7145#ifndef LONG_DOUBLE_TYPE_SIZE
7146#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7147#endif
210aa14a
RS		 7148
7149unsigned long
fc27d102 7150sparc_type_code (register tree type)
210aa14a
RS		 7151{
7152 register unsigned long qualifiers = 0;
e5e809f4 7153 register unsigned shift;
210aa14a 7154
abc95ed3 7155 /* Only the first 30 bits of the qualifier are valid. We must refrain from
aee2c3c5
JW		 7156 setting more, since some assemblers will give an error for this. Also,
7157 we must be careful to avoid shifts of 32 bits or more to avoid getting
7158 unpredictable results. */
7159
e5e809f4 7160 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
210aa14a
RS		 7161 {
7162 switch (TREE_CODE (type))
7163 {
7164 case ERROR_MARK:
7165 return qualifiers;
7166
7167 case ARRAY_TYPE:
e5e809f4 7168 qualifiers |= (3 << shift);
210aa14a
RS		 7169 break;
7170
7171 case FUNCTION_TYPE:
7172 case METHOD_TYPE:
e5e809f4 7173 qualifiers |= (2 << shift);
210aa14a
RS		 7174 break;
7175
7176 case POINTER_TYPE:
7177 case REFERENCE_TYPE:
7178 case OFFSET_TYPE:
e5e809f4 7179 qualifiers |= (1 << shift);
210aa14a 7180 break;
ab835497 7181
210aa14a
RS		 7182 case RECORD_TYPE:
7183 return (qualifiers | 8);
7184
7185 case UNION_TYPE:
b0468b84 7186 case QUAL_UNION_TYPE:
210aa14a
RS		 7187 return (qualifiers | 9);
7188
7189 case ENUMERAL_TYPE:
7190 return (qualifiers | 10);
7191
7192 case VOID_TYPE:
7193 return (qualifiers | 16);
7194
7195 case INTEGER_TYPE:
654209e6
JW		 7196 /* If this is a range type, consider it to be the underlying
7197 type. */
7198 if (TREE_TYPE (type) != 0)
e5e809f4 7199 break;
654209e6 7200
77a02b01 7201 /* Carefully distinguish all the standard types of C,
b0468b84 7202 without messing up if the language is not C. We do this by
8df83eae 7203 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
b0468b84
RK		 7204 look at both the names and the above fields, but that's redundant.
7205 Any type whose size is between two C types will be considered
7206 to be the wider of the two types. Also, we do not have a
7207 special code to use for "long long", so anything wider than
7208 long is treated the same. Note that we can't distinguish
7209 between "int" and "long" in this code if they are the same
7210 size, but that's fine, since neither can the assembler. */
7211
7212 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
8df83eae 7213 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
77a02b01 7214
b0468b84 7215 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
8df83eae 7216 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
77a02b01 7217
b0468b84 7218 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
8df83eae 7219 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
77a02b01 7220
b0468b84 7221 else
8df83eae 7222 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
77a02b01 7223
210aa14a 7224 case REAL_TYPE:
e5e809f4
JL		 7225 /* If this is a range type, consider it to be the underlying
7226 type. */
7227 if (TREE_TYPE (type) != 0)
7228 break;
7229
77a02b01
JW		 7230 /* Carefully distinguish all the standard types of C,
7231 without messing up if the language is not C. */
b0468b84 7232
77a02b01 7233 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
210aa14a 7234 return (qualifiers | 6);
b0468b84
RK		 7235
7236 else
7237 return (qualifiers | 7);
210aa14a
RS		 7238
7239 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
13d39dbc 7240 /* ??? We need to distinguish between double and float complex types,
c82aa69a
JW		 7241 but I don't know how yet because I can't reach this code from
7242 existing front-ends. */
7243 return (qualifiers | 7); /* Who knows? */
7244
1b5963f7 7245 case VECTOR_TYPE:
62de55f7 7246 case BOOLEAN_TYPE: /* Boolean truth value type. */
210aa14a 7247 case LANG_TYPE: /* ? */
26902ae0 7248 return qualifiers;
210aa14a
RS		 7249
7250 default:
f5f7d171 7251 gcc_unreachable (); /* Not a type! */
210aa14a
RS		 7252 }
7253 }
e5e809f4
JL		 7254
7255 return qualifiers;
210aa14a 7256}
ead69aea 7257\f
61a55e8b
DE		 7258/* Nested function support. */
7259
7260/* Emit RTL insns to initialize the variable parts of a trampoline.
7261 FNADDR is an RTX for the address of the function's pure code.
7262 CXT is an RTX for the static chain value for the function.
7263
7264 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7265 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7266 (to store insns). This is a bit excessive. Perhaps a different
7267 mechanism would be better here.
7268
849a528d 7269 Emit enough FLUSH insns to synchronize the data and instruction caches. */
61a55e8b
DE		 7270
7271void
fc27d102 7272sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
61a55e8b 7273{
1ec0c607 7274 /* SPARC 32-bit trampoline:
c6b0465b 7275
e0d80184
DM		 7276 sethi %hi(fn), %g1
7277 sethi %hi(static), %g2
7278 jmp %g1+%lo(fn)
7279 or %g2, %lo(static), %g2
c6b0465b
JC		 7280
7281 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7282 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7283 */
7284
35aa3c1c
RK		 7285 emit_move_insn
7286 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7287 expand_binop (SImode, ior_optab,
7288 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7289 size_int (10), 0, 1),
7290 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7291 NULL_RTX, 1, OPTAB_DIRECT));
7292
7293 emit_move_insn
7294 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7295 expand_binop (SImode, ior_optab,
7296 expand_shift (RSHIFT_EXPR, SImode, cxt,
7297 size_int (10), 0, 1),
7298 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7299 NULL_RTX, 1, OPTAB_DIRECT));
7300
7301 emit_move_insn
7302 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7303 expand_binop (SImode, ior_optab,
7304 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7305 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7306 NULL_RTX, 1, OPTAB_DIRECT));
7307
7308 emit_move_insn
7309 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7310 expand_binop (SImode, ior_optab,
7311 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7312 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7313 NULL_RTX, 1, OPTAB_DIRECT));
c6b0465b 7314
c6b0465b
JC		 7315 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7316 aligned on a 16 byte boundary so one flush clears it all. */
35aa3c1c 7317 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
84643cbf 7318 if (sparc_cpu != PROCESSOR_ULTRASPARC
4c837a1e 7319 && sparc_cpu != PROCESSOR_ULTRASPARC3
9eeaed6e
DM		 7320 && sparc_cpu != PROCESSOR_NIAGARA
7321 && sparc_cpu != PROCESSOR_NIAGARA2)
c6b0465b
JC		 7322 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7323 plus_constant (tramp, 8)))));
1ec0c607
WH		 7324
7325 /* Call __enable_execute_stack after writing onto the stack to make sure
7326 the stack address is accessible. */
e7a742ec 7327#ifdef ENABLE_EXECUTE_STACK
f1c25d3b 7328 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
1ec0c607
WH		 7329 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7330#endif
7331
61a55e8b
DE		 7332}
7333
1ec0c607 7334/* The 64-bit version is simpler because it makes more sense to load the
849a528d
RK		 7335 values as "immediate" data out of the trampoline. It's also easier since
7336 we can read the PC without clobbering a register. */
7337
61a55e8b 7338void
fc27d102 7339sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
61a55e8b 7340{
1ec0c607 7341 /* SPARC 64-bit trampoline:
345a6161 7342
e0d80184
DM		 7343 rd %pc, %g1
7344 ldx [%g1+24], %g5
7345 jmp %g5
7346 ldx [%g1+16], %g5
c6b0465b
JC		 7347 +16 bytes data
7348 */
7349
7350 emit_move_insn (gen_rtx_MEM (SImode, tramp),
e3aaacf4 7351 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
c6b0465b 7352 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
e3aaacf4 7353 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
c6b0465b 7354 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
e3aaacf4 7355 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
c6b0465b 7356 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
e3aaacf4 7357 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
c6b0465b 7358 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
345a6161 7359 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
d4203cb4 7360 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
345a6161 7361
fae15c93 7362 if (sparc_cpu != PROCESSOR_ULTRASPARC
4c837a1e 7363 && sparc_cpu != PROCESSOR_ULTRASPARC3
9eeaed6e
DM		 7364 && sparc_cpu != PROCESSOR_NIAGARA
7365 && sparc_cpu != PROCESSOR_NIAGARA2)
d4203cb4 7366 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
1ec0c607
WH		 7367
7368 /* Call __enable_execute_stack after writing onto the stack to make sure
7369 the stack address is accessible. */
e7a742ec 7370#ifdef ENABLE_EXECUTE_STACK
f1c25d3b 7371 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
1ec0c607
WH		 7372 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7373#endif
61a55e8b
DE		 7374}
7375\f
dbb54862
JW		 7376/* Adjust the cost of a scheduling dependency. Return the new cost of
7377 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7378
8947065c 7379static int
fc27d102 7380supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
dbb54862
JW		 7381{
7382 enum attr_type insn_type;
7383
7384 if (! recog_memoized (insn))
7385 return 0;
7386
7387 insn_type = get_attr_type (insn);
7388
7389 if (REG_NOTE_KIND (link) == 0)
7390 {
7391 /* Data dependency; DEP_INSN writes a register that INSN reads some
7392 cycles later. */
7393
7394 /* if a load, then the dependence must be on the memory address;
3bc8b61e
DM		 7395 add an extra "cycle". Note that the cost could be two cycles
7396 if the reg was written late in an instruction group; we ca not tell
dbb54862
JW		 7397 here. */
7398 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7399 return cost + 3;
7400
7401 /* Get the delay only if the address of the store is the dependence. */
7402 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7403 {
7404 rtx pat = PATTERN(insn);
7405 rtx dep_pat = PATTERN (dep_insn);
7406
7407 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3bc8b61e 7408 return cost; /* This should not happen! */
dbb54862
JW		 7409
7410 /* The dependency between the two instructions was on the data that
7411 is being stored. Assume that this implies that the address of the
7412 store is not dependent. */
7413 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7414 return cost;
7415
7416 return cost + 3; /* An approximation. */
7417 }
7418
7419 /* A shift instruction cannot receive its data from an instruction
7420 in the same cycle; add a one cycle penalty. */
7421 if (insn_type == TYPE_SHIFT)
7422 return cost + 3; /* Split before cascade into shift. */
7423 }
7424 else
7425 {
7426 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7427 INSN writes some cycles later. */
7428
7429 /* These are only significant for the fpu unit; writing a fp reg before
7430 the fpu has finished with it stalls the processor. */
7431
7432 /* Reusing an integer register causes no problems. */
7433 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7434 return 0;
7435 }
7436
7437 return cost;
7438}
bfd6bc60 7439
8947065c 7440static int
fc27d102 7441hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8947065c
RH		 7442{
7443 enum attr_type insn_type, dep_type;
7444 rtx pat = PATTERN(insn);
7445 rtx dep_pat = PATTERN (dep_insn);
7446
7447 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7448 return cost;
7449
7450 insn_type = get_attr_type (insn);
7451 dep_type = get_attr_type (dep_insn);
7452
7453 switch (REG_NOTE_KIND (link))
7454 {
7455 case 0:
7456 /* Data dependency; DEP_INSN writes a register that INSN reads some
7457 cycles later. */
7458
7459 switch (insn_type)
7460 {
7461 case TYPE_STORE:
7462 case TYPE_FPSTORE:
80ffc95e 7463 /* Get the delay iff the address of the store is the dependence. */
8947065c
RH		 7464 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7465 return cost;
7466
7467 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7468 return cost;
7469 return cost + 3;
7470
7471 case TYPE_LOAD:
7472 case TYPE_SLOAD:
7473 case TYPE_FPLOAD:
7474 /* If a load, then the dependence must be on the memory address. If
7475 the addresses aren't equal, then it might be a false dependency */
7476 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7477 {
7478 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7479 || GET_CODE (SET_DEST (dep_pat)) != MEM
7480 || GET_CODE (SET_SRC (pat)) != MEM
7481 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7482 XEXP (SET_SRC (pat), 0)))
7483 return cost + 2;
7484
7485 return cost + 8;
7486 }
7487 break;
7488
7489 case TYPE_BRANCH:
7490 /* Compare to branch latency is 0. There is no benefit from
7491 separating compare and branch. */
7492 if (dep_type == TYPE_COMPARE)
7493 return 0;
7494 /* Floating point compare to branch latency is less than
7495 compare to conditional move. */
7496 if (dep_type == TYPE_FPCMP)
7497 return cost - 1;
7498 break;
3bb5de61
KG		 7499 default:
7500 break;
8947065c
RH		 7501 }
7502 break;
7503
7504 case REG_DEP_ANTI:
80ffc95e 7505 /* Anti-dependencies only penalize the fpu unit. */
8947065c
RH		 7506 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7507 return 0;
7508 break;
7509
7510 default:
7511 break;
7512 }
7513
7514 return cost;
7515}
7516
c237e94a 7517static int
fc27d102 7518sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8947065c
RH		 7519{
7520 switch (sparc_cpu)
7521 {
7522 case PROCESSOR_SUPERSPARC:
7523 cost = supersparc_adjust_cost (insn, link, dep, cost);
7524 break;
7525 case PROCESSOR_HYPERSPARC:
7526 case PROCESSOR_SPARCLITE86X:
7527 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7528 break;
8947065c
RH		 7529 default:
7530 break;
7531 }
7532 return cost;
7533}
7534
fae15c93 7535static void
fc27d102
KG		 7536sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7537 int sched_verbose ATTRIBUTE_UNUSED,
7538 int max_ready ATTRIBUTE_UNUSED)
3bc8b61e 7539{
3bc8b61e 7540}
fae15c93 7541
fae15c93 7542static int
fc27d102 7543sparc_use_sched_lookahead (void)
fae15c93 7544{
9eeaed6e
DM		 7545 if (sparc_cpu == PROCESSOR_NIAGARA
7546 || sparc_cpu == PROCESSOR_NIAGARA2)
4c837a1e 7547 return 0;
fae15c93
VM		 7548 if (sparc_cpu == PROCESSOR_ULTRASPARC
7549 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7550 return 4;
7551 if ((1 << sparc_cpu) &
7552 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7553 (1 << PROCESSOR_SPARCLITE86X)))
7554 return 3;
3bc8b61e
DM		 7555 return 0;
7556}
7557
fae15c93 7558static int
fc27d102 7559sparc_issue_rate (void)
bfd6bc60
JC		 7560{
7561 switch (sparc_cpu)
7562 {
4c837a1e 7563 case PROCESSOR_NIAGARA:
9eeaed6e 7564 case PROCESSOR_NIAGARA2:
fae15c93
VM		 7565 default:
7566 return 1;
7567 case PROCESSOR_V9:
284d86e9 7568 /* Assume V9 processors are capable of at least dual-issue. */
bfd6bc60 7569 return 2;
fae15c93
VM		 7570 case PROCESSOR_SUPERSPARC:
7571 return 3;
393049a9
RH		 7572 case PROCESSOR_HYPERSPARC:
7573 case PROCESSOR_SPARCLITE86X:
7574 return 2;
fae15c93
VM		 7575 case PROCESSOR_ULTRASPARC:
7576 case PROCESSOR_ULTRASPARC3:
7577 return 4;
bfd6bc60
JC		 7578 }
7579}
284d86e9
JC		 7580
7581static int
fc27d102 7582set_extends (rtx insn)
284d86e9
JC		 7583{
7584 register rtx pat = PATTERN (insn);
7585
7586 switch (GET_CODE (SET_SRC (pat)))
7587 {
80ffc95e 7588 /* Load and some shift instructions zero extend. */
284d86e9
JC		 7589 case MEM:
7590 case ZERO_EXTEND:
7591 /* sethi clears the high bits */
7592 case HIGH:
7593 /* LO_SUM is used with sethi. sethi cleared the high
7594 bits and the values used with lo_sum are positive */
7595 case LO_SUM:
284d86e9
JC		 7596 /* Store flag stores 0 or 1 */
7597 case LT: case LTU:
7598 case GT: case GTU:
7599 case LE: case LEU:
7600 case GE: case GEU:
7601 case EQ:
7602 case NE:
7603 return 1;
7604 case AND:
7605 {
4df1190a 7606 rtx op0 = XEXP (SET_SRC (pat), 0);
284d86e9
JC		 7607 rtx op1 = XEXP (SET_SRC (pat), 1);
7608 if (GET_CODE (op1) == CONST_INT)
7609 return INTVAL (op1) >= 0;
4df1190a
JJ		 7610 if (GET_CODE (op0) != REG)
7611 return 0;
7612 if (sparc_check_64 (op0, insn) == 1)
284d86e9 7613 return 1;
4df1190a
JJ		 7614 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7615 }
7616 case IOR:
7617 case XOR:
7618 {
7619 rtx op0 = XEXP (SET_SRC (pat), 0);
7620 rtx op1 = XEXP (SET_SRC (pat), 1);
7621 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7622 return 0;
7623 if (GET_CODE (op1) == CONST_INT)
7624 return INTVAL (op1) >= 0;
7625 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
284d86e9 7626 }
284d86e9
JC		 7627 case LSHIFTRT:
7628 return GET_MODE (SET_SRC (pat)) == SImode;
80ffc95e 7629 /* Positive integers leave the high bits zero. */
284d86e9 7630 case CONST_DOUBLE:
4df1190a 7631 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
284d86e9 7632 case CONST_INT:
4df1190a 7633 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
284d86e9
JC		 7634 case ASHIFTRT:
7635 case SIGN_EXTEND:
7636 return - (GET_MODE (SET_SRC (pat)) == SImode);
4df1190a
JJ		 7637 case REG:
7638 return sparc_check_64 (SET_SRC (pat), insn);
284d86e9
JC		 7639 default:
7640 return 0;
7641 }
7642}
7643
80ffc95e 7644/* We _ought_ to have only one kind per function, but... */
e2500fed
GK		 7645static GTY(()) rtx sparc_addr_diff_list;
7646static GTY(()) rtx sparc_addr_list;
e0d80184
DM		 7647
7648void
fc27d102 7649sparc_defer_case_vector (rtx lab, rtx vec, int diff)
e0d80184
DM		 7650{
7651 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7652 if (diff)
7653 sparc_addr_diff_list
7654 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7655 else
7656 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7657}
7658
7659static void
fc27d102 7660sparc_output_addr_vec (rtx vec)
e0d80184
DM		 7661{
7662 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7663 int idx, vlen = XVECLEN (body, 0);
7664
d1accaa3
JJ		 7665#ifdef ASM_OUTPUT_ADDR_VEC_START
7666 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7667#endif
7668
e0d80184
DM		 7669#ifdef ASM_OUTPUT_CASE_LABEL
7670 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7671 NEXT_INSN (lab));
7672#else
4977bab6 7673 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
e0d80184
DM		 7674#endif
7675
7676 for (idx = 0; idx < vlen; idx++)
7677 {
7678 ASM_OUTPUT_ADDR_VEC_ELT
7679 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7680 }
d1accaa3
JJ		 7681
7682#ifdef ASM_OUTPUT_ADDR_VEC_END
7683 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7684#endif
e0d80184
DM		 7685}
7686
7687static void
fc27d102 7688sparc_output_addr_diff_vec (rtx vec)
e0d80184
DM		 7689{
7690 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7691 rtx base = XEXP (XEXP (body, 0), 0);
7692 int idx, vlen = XVECLEN (body, 1);
7693
d1accaa3
JJ		 7694#ifdef ASM_OUTPUT_ADDR_VEC_START
7695 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7696#endif
7697
e0d80184
DM		 7698#ifdef ASM_OUTPUT_CASE_LABEL
7699 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7700 NEXT_INSN (lab));
7701#else
4977bab6 7702 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
e0d80184
DM		 7703#endif
7704
7705 for (idx = 0; idx < vlen; idx++)
7706 {
7707 ASM_OUTPUT_ADDR_DIFF_ELT
7708 (asm_out_file,
7709 body,
7710 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7711 CODE_LABEL_NUMBER (base));
7712 }
d1accaa3
JJ		 7713
7714#ifdef ASM_OUTPUT_ADDR_VEC_END
7715 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7716#endif
e0d80184
DM		 7717}
7718
7719static void
fc27d102 7720sparc_output_deferred_case_vectors (void)
e0d80184
DM		 7721{
7722 rtx t;
d676da68 7723 int align;
e0d80184 7724
f3b8847b
DM		 7725 if (sparc_addr_list == NULL_RTX
7726 && sparc_addr_diff_list == NULL_RTX)
7727 return;
7728
e0d80184 7729 /* Align to cache line in the function's code section. */
d6b5193b 7730 switch_to_section (current_function_section ());
d676da68
DM		 7731
7732 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7733 if (align > 0)
f3b8847b 7734 ASM_OUTPUT_ALIGN (asm_out_file, align);
e0d80184
DM		 7735
7736 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7737 sparc_output_addr_vec (XEXP (t, 0));
7738 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7739 sparc_output_addr_diff_vec (XEXP (t, 0));
7740
7741 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7742}
7743
284d86e9
JC		 7744/* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7745 unknown. Return 1 if the high bits are zero, -1 if the register is
7746 sign extended. */
7747int
fc27d102 7748sparc_check_64 (rtx x, rtx insn)
284d86e9
JC		 7749{
7750 /* If a register is set only once it is safe to ignore insns this
7751 code does not know how to handle. The loop will either recognize
7752 the single set and return the correct value or fail to recognize
7753 it and return 0. */
7754 int set_once = 0;
4df1190a
JJ		 7755 rtx y = x;
7756
f5f7d171 7757 gcc_assert (GET_CODE (x) == REG);
4df1190a
JJ		 7758
7759 if (GET_MODE (x) == DImode)
7760 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
284d86e9 7761
4df1190a 7762 if (flag_expensive_optimizations
b718216c 7763 && df && DF_REG_DEF_COUNT (REGNO (y)) == 1)
284d86e9
JC		 7764 set_once = 1;
7765
7766 if (insn == 0)
d6f4ec51
KG		 7767 {
7768 if (set_once)
7769 insn = get_last_insn_anywhere ();
7770 else
7771 return 0;
7772 }
284d86e9 7773
d6f4ec51 7774 while ((insn = PREV_INSN (insn)))
284d86e9
JC		 7775 {
7776 switch (GET_CODE (insn))
7777 {
7778 case JUMP_INSN:
7779 case NOTE:
7780 break;
7781 case CODE_LABEL:
7782 case CALL_INSN:
7783 default:
7784 if (! set_once)
7785 return 0;
7786 break;
7787 case INSN:
7788 {
7789 rtx pat = PATTERN (insn);
7790 if (GET_CODE (pat) != SET)
7791 return 0;
7792 if (rtx_equal_p (x, SET_DEST (pat)))
4df1190a
JJ		 7793 return set_extends (insn);
7794 if (y && rtx_equal_p (y, SET_DEST (pat)))
7795 return set_extends (insn);
7796 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
284d86e9
JC		 7797 return 0;
7798 }
7799 }
7800 }
7801 return 0;
7802}
7803
01d3224a
EB		 7804/* Returns assembly code to perform a DImode shift using
7805 a 64-bit global or out register on SPARC-V8+. */
a6163c22
EB		 7806const char *
7807output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
284d86e9
JC		 7808{
7809 static char asm_code[60];
7810
01d3224a
EB		 7811 /* The scratch register is only required when the destination
7812 register is not a 64-bit global or out register. */
7813 if (which_alternative != 2)
284d86e9 7814 operands[3] = operands[0];
01d3224a 7815
1c8b4e29
EB		 7816 /* We can only shift by constants <= 63. */
7817 if (GET_CODE (operands[2]) == CONST_INT)
7818 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7819
c6b0465b
JC		 7820 if (GET_CODE (operands[1]) == CONST_INT)
7821 {
4df1190a 7822 output_asm_insn ("mov\t%1, %3", operands);
c6b0465b
JC		 7823 }
7824 else
7825 {
4df1190a 7826 output_asm_insn ("sllx\t%H1, 32, %3", operands);
c6b0465b 7827 if (sparc_check_64 (operands[1], insn) <= 0)
4df1190a
JJ		 7828 output_asm_insn ("srl\t%L1, 0, %L1", operands);
7829 output_asm_insn ("or\t%L1, %3, %3", operands);
c6b0465b 7830 }
284d86e9
JC		 7831
7832 strcpy(asm_code, opcode);
01d3224a 7833
284d86e9 7834 if (which_alternative != 2)
4df1190a 7835 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
284d86e9 7836 else
4df1190a 7837 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
284d86e9 7838}
2be15d0f 7839\f
89a8b315
RH		 7840/* Output rtl to increment the profiler label LABELNO
7841 for profiling a function entry. */
2be15d0f
RH		 7842
7843void
fc27d102 7844sparc_profile_hook (int labelno)
2be15d0f
RH		 7845{
7846 char buf[32];
89a8b315 7847 rtx lab, fun;
2be15d0f 7848
89a8b315 7849 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
cc44abe6
DM		 7850 if (NO_PROFILE_COUNTERS)
7851 {
7852 emit_library_call (fun, LCT_NORMAL, VOIDmode, 0);
7853 }
7854 else
7855 {
7856 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
7857 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
7858 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
7859 }
2be15d0f 7860}
89a8b315 7861\f
ede75ee8 7862#ifdef OBJECT_FORMAT_ELF
7c262518 7863static void
c18a5b6c
MM		 7864sparc_elf_asm_named_section (const char *name, unsigned int flags,
7865 tree decl)
7c262518 7866{
201556f0
JJ		 7867 if (flags & SECTION_MERGE)
7868 {
7869 /* entsize cannot be expressed in this section attributes
7870 encoding style. */
c18a5b6c 7871 default_elf_asm_named_section (name, flags, decl);
201556f0
JJ		 7872 return;
7873 }
7874
7c262518
RH		 7875 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
7876
7877 if (!(flags & SECTION_DEBUG))
7878 fputs (",#alloc", asm_out_file);
7879 if (flags & SECTION_WRITE)
7880 fputs (",#write", asm_out_file);
2f3321ca
EB		 7881 if (flags & SECTION_TLS)
7882 fputs (",#tls", asm_out_file);
7c262518
RH		 7883 if (flags & SECTION_CODE)
7884 fputs (",#execinstr", asm_out_file);
7885
7886 /* ??? Handle SECTION_BSS. */
7887
7888 fputc ('\n', asm_out_file);
7889}
ede75ee8 7890#endif /* OBJECT_FORMAT_ELF */
f451b552 7891
60b85c4c 7892/* We do not allow indirect calls to be optimized into sibling calls.
951661a1
EB		 7893
7894 We cannot use sibling calls when delayed branches are disabled
7895 because they will likely require the call delay slot to be filled.
7896
60b85c4c 7897 Also, on SPARC 32-bit we cannot emit a sibling call when the
4977bab6
ZW		 7898 current function returns a structure. This is because the "unimp
7899 after call" convention would cause the callee to return to the
7900 wrong place. The generic code already disallows cases where the
7901 function being called returns a structure.
7902
7903 It may seem strange how this last case could occur. Usually there
7904 is code after the call which jumps to epilogue code which dumps the
7905 return value into the struct return area. That ought to invalidate
951661a1 7906 the sibling call right? Well, in the C++ case we can end up passing
4977bab6
ZW		 7907 the pointer to the struct return area to a constructor (which returns
7908 void) and then nothing else happens. Such a sibling call would look
1910440e
RS		 7909 valid without the added check here.
7910
7911 VxWorks PIC PLT entries require the global pointer to be initialized
7912 on entry. We therefore can't emit sibling calls to them. */
4977bab6 7913static bool
fc27d102 7914sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
4977bab6 7915{
951661a1
EB		 7916 return (decl
7917 && flag_delayed_branch
e3b5732b 7918 && (TARGET_ARCH64 || ! cfun->returns_struct)
1910440e
RS		 7919 && !(TARGET_VXWORKS_RTP
7920 && flag_pic
7921 && !targetm.binds_local_p (decl)));
4977bab6 7922}
c15c90bb
ZW		 7923\f
7924/* libfunc renaming. */
7925#include "config/gofast.h"
7926
7927static void
7928sparc_init_libfuncs (void)
7929{
7930 if (TARGET_ARCH32)
7931 {
7932 /* Use the subroutines that Sun's library provides for integer
7933 multiply and divide. The `*' prevents an underscore from
7934 being prepended by the compiler. .umul is a little faster
ff482c8d 7935 than .mul. */
c15c90bb
ZW		 7936 set_optab_libfunc (smul_optab, SImode, "*.umul");
7937 set_optab_libfunc (sdiv_optab, SImode, "*.div");
7938 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
7939 set_optab_libfunc (smod_optab, SImode, "*.rem");
7940 set_optab_libfunc (umod_optab, SImode, "*.urem");
7941
7942 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
7943 set_optab_libfunc (add_optab, TFmode, "_Q_add");
7944 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
7945 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
7946 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
7947 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
7948
7949 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
7950 is because with soft-float, the SFmode and DFmode sqrt
7951 instructions will be absent, and the compiler will notice and
7952 try to use the TFmode sqrt instruction for calls to the
7953 builtin function sqrt, but this fails. */
7954 if (TARGET_FPU)
7955 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
7956
c9034561
ZW		 7957 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
7958 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
7959 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
7960 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
7961 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
7962 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
c15c90bb 7963
85363ca0
ZW		 7964 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
7965 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
7966 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
7967 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
7968
7969 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
7970 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
7971 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
9b336fa4 7972 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_Q_utoq");
c15c90bb 7973
45dcc026
JJ		 7974 if (DITF_CONVERSION_LIBFUNCS)
7975 {
7976 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
7977 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
7978 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
9b336fa4 7979 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq");
45dcc026
JJ		 7980 }
7981
c15c90bb
ZW		 7982 if (SUN_CONVERSION_LIBFUNCS)
7983 {
85363ca0
ZW		 7984 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
7985 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
7986 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
7987 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
c15c90bb
ZW		 7988 }
7989 }
7990 if (TARGET_ARCH64)
7991 {
7992 /* In the SPARC 64bit ABI, SImode multiply and divide functions
7993 do not exist in the library. Make sure the compiler does not
7994 emit calls to them by accident. (It should always use the
7995 hardware instructions.) */
7996 set_optab_libfunc (smul_optab, SImode, 0);
7997 set_optab_libfunc (sdiv_optab, SImode, 0);
7998 set_optab_libfunc (udiv_optab, SImode, 0);
7999 set_optab_libfunc (smod_optab, SImode, 0);
8000 set_optab_libfunc (umod_optab, SImode, 0);
8001
8002 if (SUN_INTEGER_MULTIPLY_64)
8003 {
8004 set_optab_libfunc (smul_optab, DImode, "__mul64");
8005 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8006 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8007 set_optab_libfunc (smod_optab, DImode, "__rem64");
8008 set_optab_libfunc (umod_optab, DImode, "__urem64");
8009 }
8010
8011 if (SUN_CONVERSION_LIBFUNCS)
8012 {
85363ca0
ZW		 8013 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8014 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8015 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8016 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
c15c90bb
ZW		 8017 }
8018 }
4977bab6 8019
c15c90bb
ZW		 8020 gofast_maybe_init_libfuncs ();
8021}
8022\f
16f59241 8023#define def_builtin(NAME, CODE, TYPE) \
c79efc4d
RÁE		 8024 add_builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \
8025 NULL_TREE)
16f59241
JM		 8026
8027/* Implement the TARGET_INIT_BUILTINS target hook.
8028 Create builtin functions for special SPARC instructions. */
8029
8030static void
8031sparc_init_builtins (void)
8032{
8033 if (TARGET_VIS)
8034 sparc_vis_init_builtins ();
8035}
8036
8037/* Create builtin functions for VIS 1.0 instructions. */
8038
8039static void
8040sparc_vis_init_builtins (void)
8041{
8042 tree v4qi = build_vector_type (unsigned_intQI_type_node, 4);
8043 tree v8qi = build_vector_type (unsigned_intQI_type_node, 8);
8044 tree v4hi = build_vector_type (intHI_type_node, 4);
8045 tree v2hi = build_vector_type (intHI_type_node, 2);
8046 tree v2si = build_vector_type (intSI_type_node, 2);
8047
8048 tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0);
8049 tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0);
8050 tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0);
8051 tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0);
8052 tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0);
8053 tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0);
8054 tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0);
8055 tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0);
8056 tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0);
8057 tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0);
8058 tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0);
8059 tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0);
8060 tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node,
8061 v8qi, v8qi,
8062 intDI_type_node, 0);
8063 tree di_ftype_di_di = build_function_type_list (intDI_type_node,
8064 intDI_type_node,
8065 intDI_type_node, 0);
8066 tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node,
8067 ptr_type_node,
8068 intSI_type_node, 0);
8069 tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node,
8070 ptr_type_node,
8071 intDI_type_node, 0);
8072
8073 /* Packing and expanding vectors. */
8074 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis, v4qi_ftype_v4hi);
8075 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
8076 v8qi_ftype_v2si_v8qi);
8077 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
8078 v2hi_ftype_v2si);
8079 def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis, v4hi_ftype_v4qi);
8080 def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis,
8081 v8qi_ftype_v4qi_v4qi);
8082
8083 /* Multiplications. */
8084 def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis,
8085 v4hi_ftype_v4qi_v4hi);
8086 def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis,
8087 v4hi_ftype_v4qi_v2hi);
8088 def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis,
8089 v4hi_ftype_v4qi_v2hi);
8090 def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis,
8091 v4hi_ftype_v8qi_v4hi);
8092 def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis,
8093 v4hi_ftype_v8qi_v4hi);
8094 def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis,
8095 v2si_ftype_v4qi_v2hi);
8096 def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis,
8097 v2si_ftype_v4qi_v2hi);
8098
8099 /* Data aligning. */
8100 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
8101 v4hi_ftype_v4hi_v4hi);
8102 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
8103 v8qi_ftype_v8qi_v8qi);
8104 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
8105 v2si_ftype_v2si_v2si);
8106 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis,
8107 di_ftype_di_di);
8108 if (TARGET_ARCH64)
8109 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
8110 ptr_ftype_ptr_di);
8111 else
8112 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
8113 ptr_ftype_ptr_si);
8114
8115 /* Pixel distance. */
8116 def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
8117 di_ftype_v8qi_v8qi_di);
8118}
8119
8120/* Handle TARGET_EXPAND_BUILTIN target hook.
0fa2e4df 8121 Expand builtin functions for sparc intrinsics. */
16f59241
JM		 8122
8123static rtx
724d7c55
EB		 8124sparc_expand_builtin (tree exp, rtx target,
8125 rtx subtarget ATTRIBUTE_UNUSED,
8126 enum machine_mode tmode ATTRIBUTE_UNUSED,
8127 int ignore ATTRIBUTE_UNUSED)
16f59241 8128{
5039610b
SL		 8129 tree arg;
8130 call_expr_arg_iterator iter;
8131 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
16f59241
JM		 8132 unsigned int icode = DECL_FUNCTION_CODE (fndecl);
8133 rtx pat, op[4];
8134 enum machine_mode mode[4];
8135 int arg_count = 0;
8136
724d7c55
EB		 8137 mode[0] = insn_data[icode].operand[0].mode;
8138 if (!target
8139 || GET_MODE (target) != mode[0]
8140 || ! (*insn_data[icode].operand[0].predicate) (target, mode[0]))
8141 op[0] = gen_reg_rtx (mode[0]);
16f59241 8142 else
724d7c55 8143 op[0] = target;
16f59241 8144
5039610b 8145 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
16f59241 8146 {
16f59241
JM		 8147 arg_count++;
8148 mode[arg_count] = insn_data[icode].operand[arg_count].mode;
84217346 8149 op[arg_count] = expand_normal (arg);
16f59241
JM		 8150
8151 if (! (*insn_data[icode].operand[arg_count].predicate) (op[arg_count],
8152 mode[arg_count]))
8153 op[arg_count] = copy_to_mode_reg (mode[arg_count], op[arg_count]);
8154 }
8155
8156 switch (arg_count)
8157 {
8158 case 1:
8159 pat = GEN_FCN (icode) (op[0], op[1]);
8160 break;
8161 case 2:
8162 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
8163 break;
8164 case 3:
8165 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
8166 break;
8167 default:
8168 gcc_unreachable ();
8169 }
8170
8171 if (!pat)
8172 return NULL_RTX;
8173
8174 emit_insn (pat);
8175
8176 return op[0];
8177}
8b0096b4
JM		 8178
8179static int
8180sparc_vis_mul8x16 (int e8, int e16)
8181{
8182 return (e8 * e16 + 128) / 256;
8183}
8184
8185/* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
8186 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
8187 constants. A tree list with the results of the multiplications is returned,
8188 and each element in the list is of INNER_TYPE. */
8189
8190static tree
8191sparc_handle_vis_mul8x16 (int fncode, tree inner_type, tree elts0, tree elts1)
8192{
8193 tree n_elts = NULL_TREE;
8194 int scale;
8195
8196 switch (fncode)
8197 {
8198 case CODE_FOR_fmul8x16_vis:
8199 for (; elts0 && elts1;
8200 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
8201 {
8202 int val
8203 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
8204 TREE_INT_CST_LOW (TREE_VALUE (elts1)));
8205 n_elts = tree_cons (NULL_TREE,
8206 build_int_cst (inner_type, val),
8207 n_elts);
8208 }
8209 break;
8210
8211 case CODE_FOR_fmul8x16au_vis:
8212 scale = TREE_INT_CST_LOW (TREE_VALUE (elts1));
8213
8214 for (; elts0; elts0 = TREE_CHAIN (elts0))
8215 {
8216 int val
8217 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
8218 scale);
8219 n_elts = tree_cons (NULL_TREE,
8220 build_int_cst (inner_type, val),
8221 n_elts);
8222 }
8223 break;
8224
8225 case CODE_FOR_fmul8x16al_vis:
8226 scale = TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1)));
8227
8228 for (; elts0; elts0 = TREE_CHAIN (elts0))
8229 {
8230 int val
8231 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
8232 scale);
8233 n_elts = tree_cons (NULL_TREE,
8234 build_int_cst (inner_type, val),
8235 n_elts);
8236 }
8237 break;
8238
8239 default:
8240 gcc_unreachable ();
8241 }
8242
8243 return nreverse (n_elts);
8244
8245}
8246/* Handle TARGET_FOLD_BUILTIN target hook.
607fb860 8247 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
8b0096b4
JM		 8248 result of the function call is ignored. NULL_TREE is returned if the
8249 function could not be folded. */
8250
8251static tree
8252sparc_fold_builtin (tree fndecl, tree arglist, bool ignore)
8253{
8254 tree arg0, arg1, arg2;
8255 tree rtype = TREE_TYPE (TREE_TYPE (fndecl));
bbbbb16a 8256 enum insn_code icode = (enum insn_code) DECL_FUNCTION_CODE (fndecl);
8b0096b4 8257
724d7c55 8258 if (ignore
bbbbb16a
ILT		 8259 && icode != CODE_FOR_alignaddrsi_vis
8260 && icode != CODE_FOR_alignaddrdi_vis)
724d7c55 8261 return fold_convert (rtype, integer_zero_node);
8b0096b4 8262
bbbbb16a 8263 switch (icode)
8b0096b4
JM		 8264 {
8265 case CODE_FOR_fexpand_vis:
8266 arg0 = TREE_VALUE (arglist);
8267 STRIP_NOPS (arg0);
8268
8269 if (TREE_CODE (arg0) == VECTOR_CST)
8270 {
8271 tree inner_type = TREE_TYPE (rtype);
8272 tree elts = TREE_VECTOR_CST_ELTS (arg0);
8273 tree n_elts = NULL_TREE;
8274
8275 for (; elts; elts = TREE_CHAIN (elts))
8276 {
8277 unsigned int val = TREE_INT_CST_LOW (TREE_VALUE (elts)) << 4;
8278 n_elts = tree_cons (NULL_TREE,
8279 build_int_cst (inner_type, val),
8280 n_elts);
8281 }
8282 return build_vector (rtype, nreverse (n_elts));
8283 }
8284 break;
8285
8286 case CODE_FOR_fmul8x16_vis:
8287 case CODE_FOR_fmul8x16au_vis:
8288 case CODE_FOR_fmul8x16al_vis:
8289 arg0 = TREE_VALUE (arglist);
8290 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8291 STRIP_NOPS (arg0);
8292 STRIP_NOPS (arg1);
8293
8294 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
8295 {
8296 tree inner_type = TREE_TYPE (rtype);
8297 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
8298 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
bbbbb16a
ILT		 8299 tree n_elts = sparc_handle_vis_mul8x16 (icode, inner_type, elts0,
8300 elts1);
8b0096b4
JM		 8301
8302 return build_vector (rtype, n_elts);
8303 }
8304 break;
8305
8306 case CODE_FOR_fpmerge_vis:
8307 arg0 = TREE_VALUE (arglist);
8308 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8309 STRIP_NOPS (arg0);
8310 STRIP_NOPS (arg1);
8311
8312 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
8313 {
8314 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
8315 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
8316 tree n_elts = NULL_TREE;
8317
8318 for (; elts0 && elts1;
8319 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
8320 {
8321 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts0), n_elts);
8322 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts1), n_elts);
8323 }
8324
8325 return build_vector (rtype, nreverse (n_elts));
8326 }
8327 break;
8328
8329 case CODE_FOR_pdist_vis:
8330 arg0 = TREE_VALUE (arglist);
8331 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8332 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
8333 STRIP_NOPS (arg0);
8334 STRIP_NOPS (arg1);
8335 STRIP_NOPS (arg2);
8336
8337 if (TREE_CODE (arg0) == VECTOR_CST
8338 && TREE_CODE (arg1) == VECTOR_CST
8339 && TREE_CODE (arg2) == INTEGER_CST)
8340 {
8341 int overflow = 0;
8342 unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (arg2);
8343 HOST_WIDE_INT high = TREE_INT_CST_HIGH (arg2);
8344 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
8345 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
8346
8347 for (; elts0 && elts1;
8348 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
8349 {
8350 unsigned HOST_WIDE_INT
8351 low0 = TREE_INT_CST_LOW (TREE_VALUE (elts0)),
8352 low1 = TREE_INT_CST_LOW (TREE_VALUE (elts1));
8353 HOST_WIDE_INT high0 = TREE_INT_CST_HIGH (TREE_VALUE (elts0));
8354 HOST_WIDE_INT high1 = TREE_INT_CST_HIGH (TREE_VALUE (elts1));
8355
8356 unsigned HOST_WIDE_INT l;
8357 HOST_WIDE_INT h;
8358
8359 overflow |= neg_double (low1, high1, &l, &h);
8360 overflow |= add_double (low0, high0, l, h, &l, &h);
8361 if (h < 0)
8362 overflow |= neg_double (l, h, &l, &h);
8363
8364 overflow |= add_double (low, high, l, h, &low, &high);
8365 }
8366
8367 gcc_assert (overflow == 0);
8368
8369 return build_int_cst_wide (rtype, low, high);
8370 }
8371
8372 default:
8373 break;
8374 }
724d7c55 8375
8b0096b4
JM		 8376 return NULL_TREE;
8377}
16f59241 8378\f
214c6394
DM		 8379/* ??? This duplicates information provided to the compiler by the
8380 ??? scheduler description. Some day, teach genautomata to output
8381 ??? the latencies and then CSE will just use that. */
8382
3c50106f 8383static bool
f40751dd
JH		 8384sparc_rtx_costs (rtx x, int code, int outer_code, int *total,
8385 bool speed ATTRIBUTE_UNUSED)
2ce04b6b 8386{
18df6de9
DM		 8387 enum machine_mode mode = GET_MODE (x);
8388 bool float_mode_p = FLOAT_MODE_P (mode);
8389
2ce04b6b
DM		 8390 switch (code)
8391 {
18df6de9
DM		 8392 case CONST_INT:
8393 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
214c6394 8394 {
18df6de9 8395 *total = 0;
3c50106f 8396 return true;
214c6394 8397 }
18df6de9 8398 /* FALLTHRU */
214c6394 8399
18df6de9
DM		 8400 case HIGH:
8401 *total = 2;
8402 return true;
214c6394 8403
18df6de9
DM		 8404 case CONST:
8405 case LABEL_REF:
8406 case SYMBOL_REF:
8407 *total = 4;
8408 return true;
214c6394 8409
18df6de9 8410 case CONST_DOUBLE:
ca075703
DM		 8411 if (GET_MODE (x) == VOIDmode
8412 && ((CONST_DOUBLE_HIGH (x) == 0
8413 && CONST_DOUBLE_LOW (x) < 0x1000)
8414 || (CONST_DOUBLE_HIGH (x) == -1
8415 && CONST_DOUBLE_LOW (x) < 0
8416 && CONST_DOUBLE_LOW (x) >= -0x1000)))
18df6de9
DM		 8417 *total = 0;
8418 else
8419 *total = 8;
3c50106f 8420 return true;
214c6394 8421
18df6de9
DM		 8422 case MEM:
8423 /* If outer-code was a sign or zero extension, a cost
8424 of COSTS_N_INSNS (1) was already added in. This is
8425 why we are subtracting it back out. */
8426 if (outer_code == ZERO_EXTEND)
214c6394 8427 {
18df6de9 8428 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
214c6394 8429 }
18df6de9 8430 else if (outer_code == SIGN_EXTEND)
3c50106f 8431 {
18df6de9 8432 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
3c50106f 8433 }
18df6de9 8434 else if (float_mode_p)
3c50106f 8435 {
18df6de9 8436 *total = sparc_costs->float_load;
3c50106f 8437 }
18df6de9 8438 else
3c50106f 8439 {
18df6de9 8440 *total = sparc_costs->int_load;
3c50106f 8441 }
214c6394 8442
3c50106f 8443 return true;
2ce04b6b 8444
18df6de9
DM		 8445 case PLUS:
8446 case MINUS:
8447 if (float_mode_p)
8448 *total = sparc_costs->float_plusminus;
8449 else
8450 *total = COSTS_N_INSNS (1);
8451 return false;
214c6394 8452
18df6de9
DM		 8453 case MULT:
8454 if (float_mode_p)
8455 *total = sparc_costs->float_mul;
e08eb33c 8456 else if (! TARGET_HARD_MUL)
bf6c40e9 8457 *total = COSTS_N_INSNS (25);
18df6de9
DM		 8458 else
8459 {
8460 int bit_cost;
214c6394 8461
18df6de9
DM		 8462 bit_cost = 0;
8463 if (sparc_costs->int_mul_bit_factor)
8464 {
8465 int nbits;
214c6394 8466
18df6de9
DM		 8467 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8468 {
8469 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
8470 for (nbits = 0; value != 0; value &= value - 1)
8471 nbits++;
8472 }
8473 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
ca075703 8474 && GET_MODE (XEXP (x, 1)) == VOIDmode)
18df6de9
DM		 8475 {
8476 rtx x1 = XEXP (x, 1);
ca075703
DM		 8477 unsigned HOST_WIDE_INT value1 = CONST_DOUBLE_LOW (x1);
8478 unsigned HOST_WIDE_INT value2 = CONST_DOUBLE_HIGH (x1);
18df6de9
DM		 8479
8480 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
8481 nbits++;
8482 for (; value2 != 0; value2 &= value2 - 1)
8483 nbits++;
8484 }
214c6394 8485 else
18df6de9 8486 nbits = 7;
214c6394 8487
18df6de9
DM		 8488 if (nbits < 3)
8489 nbits = 3;
8490 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
ffe384ff 8491 bit_cost = COSTS_N_INSNS (bit_cost);
214c6394 8492 }
18df6de9
DM		 8493
8494 if (mode == DImode)
ffe384ff 8495 *total = sparc_costs->int_mulX + bit_cost;
18df6de9 8496 else
ffe384ff 8497 *total = sparc_costs->int_mul + bit_cost;
214c6394 8498 }
18df6de9 8499 return false;
214c6394 8500
18df6de9
DM		 8501 case ASHIFT:
8502 case ASHIFTRT:
8503 case LSHIFTRT:
8504 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
8505 return false;
2ce04b6b 8506
18df6de9
DM		 8507 case DIV:
8508 case UDIV:
8509 case MOD:
8510 case UMOD:
8511 if (float_mode_p)
214c6394 8512 {
18df6de9
DM		 8513 if (mode == DFmode)
8514 *total = sparc_costs->float_div_df;
214c6394 8515 else
18df6de9 8516 *total = sparc_costs->float_div_sf;
214c6394 8517 }
18df6de9 8518 else
214c6394 8519 {
18df6de9
DM		 8520 if (mode == DImode)
8521 *total = sparc_costs->int_divX;
214c6394 8522 else
18df6de9 8523 *total = sparc_costs->int_div;
214c6394 8524 }
18df6de9 8525 return false;
2ce04b6b 8526
18df6de9
DM		 8527 case NEG:
8528 if (! float_mode_p)
3c50106f 8529 {
18df6de9
DM		 8530 *total = COSTS_N_INSNS (1);
8531 return false;
3c50106f 8532 }
5efb1046 8533 /* FALLTHRU */
2ce04b6b 8534
18df6de9
DM		 8535 case ABS:
8536 case FLOAT:
8537 case UNSIGNED_FLOAT:
8538 case FIX:
8539 case UNSIGNED_FIX:
8540 case FLOAT_EXTEND:
8541 case FLOAT_TRUNCATE:
8542 *total = sparc_costs->float_move;
8543 return false;
2ce04b6b 8544
18df6de9
DM		 8545 case SQRT:
8546 if (mode == DFmode)
8547 *total = sparc_costs->float_sqrt_df;
8548 else
8549 *total = sparc_costs->float_sqrt_sf;
8550 return false;
2ce04b6b 8551
18df6de9
DM		 8552 case COMPARE:
8553 if (float_mode_p)
8554 *total = sparc_costs->float_cmp;
3c50106f 8555 else
18df6de9
DM		 8556 *total = COSTS_N_INSNS (1);
8557 return false;
8558
8559 case IF_THEN_ELSE:
8560 if (float_mode_p)
8561 *total = sparc_costs->float_cmove;
8562 else
8563 *total = sparc_costs->int_cmove;
8564 return false;
2ce04b6b 8565
893e18a5
JM		 8566 case IOR:
8567 /* Handle the NAND vector patterns. */
8568 if (sparc_vector_mode_supported_p (GET_MODE (x))
8569 && GET_CODE (XEXP (x, 0)) == NOT
8570 && GET_CODE (XEXP (x, 1)) == NOT)
8571 {
8572 *total = COSTS_N_INSNS (1);
8573 return true;
8574 }
8575 else
8576 return false;
8577
2ce04b6b 8578 default:
3c50106f
RH		 8579 return false;
8580 }
2ce04b6b 8581}
fb49053f 8582
68ba34f3
AS		 8583/* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
8584 This is achieved by means of a manual dynamic stack space allocation in
8585 the current frame. We make the assumption that SEQ doesn't contain any
8586 function calls, with the possible exception of calls to the PIC helper. */
951661a1
EB		 8587
8588static void
1b970c28 8589emit_and_preserve (rtx seq, rtx reg, rtx reg2)
951661a1 8590{
68ba34f3
AS		 8591 /* We must preserve the lowest 16 words for the register save area. */
8592 HOST_WIDE_INT offset = 16*UNITS_PER_WORD;
8593 /* We really need only 2 words of fresh stack space. */
8594 HOST_WIDE_INT size = SPARC_STACK_ALIGN (offset + 2*UNITS_PER_WORD);
951661a1 8595
68ba34f3
AS		 8596 rtx slot
8597 = gen_rtx_MEM (word_mode, plus_constant (stack_pointer_rtx,
8598 SPARC_STACK_BIAS + offset));
8599
8600 emit_insn (gen_stack_pointer_dec (GEN_INT (size)));
951661a1 8601 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
1b970c28
EB		 8602 if (reg2)
8603 emit_insn (gen_rtx_SET (VOIDmode,
8604 adjust_address (slot, word_mode, UNITS_PER_WORD),
8605 reg2));
951661a1 8606 emit_insn (seq);
1b970c28
EB		 8607 if (reg2)
8608 emit_insn (gen_rtx_SET (VOIDmode,
8609 reg2,
8610 adjust_address (slot, word_mode, UNITS_PER_WORD)));
951661a1 8611 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
68ba34f3 8612 emit_insn (gen_stack_pointer_inc (GEN_INT (size)));
951661a1
EB		 8613}
8614
b9bf58e5
EB		 8615/* Output the assembler code for a thunk function. THUNK_DECL is the
8616 declaration for the thunk function itself, FUNCTION is the decl for
8617 the target function. DELTA is an immediate constant offset to be
8618 added to THIS. If VCALL_OFFSET is nonzero, the word at address
8619 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
e133041b 8620
c590b625 8621static void
fc27d102 8622sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
b9bf58e5 8623 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
fc27d102 8624 tree function)
e133041b 8625{
0a2aaacc 8626 rtx this_rtx, insn, funexp;
951661a1 8627 unsigned int int_arg_first;
e133041b
RH		 8628
8629 reload_completed = 1;
fe3ad572 8630 epilogue_completed = 1;
e133041b 8631
2e040219 8632 emit_note (NOTE_INSN_PROLOGUE_END);
e133041b 8633
951661a1
EB		 8634 if (flag_delayed_branch)
8635 {
8636 /* We will emit a regular sibcall below, so we need to instruct
8637 output_sibcall that we are in a leaf function. */
22d66adf 8638 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 1;
951661a1
EB		 8639
8640 /* This will cause final.c to invoke leaf_renumber_regs so we
8641 must behave as if we were in a not-yet-leafified function. */
8642 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
8643 }
8644 else
8645 {
8646 /* We will emit the sibcall manually below, so we will need to
8647 manually spill non-leaf registers. */
22d66adf 8648 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 0;
951661a1
EB		 8649
8650 /* We really are in a leaf function. */
8651 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
8652 }
8653
e133041b
RH		 8654 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8655 returns a structure, the structure return pointer is there instead. */
61f71b34 8656 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
0a2aaacc 8657 this_rtx = gen_rtx_REG (Pmode, int_arg_first + 1);
e133041b 8658 else
0a2aaacc 8659 this_rtx = gen_rtx_REG (Pmode, int_arg_first);
e133041b
RH		 8660
8661 /* Add DELTA. When possible use a plain add, otherwise load it into
8662 a register first. */
b9bf58e5 8663 if (delta)
e133041b 8664 {
b9bf58e5
EB		 8665 rtx delta_rtx = GEN_INT (delta);
8666
8667 if (! SPARC_SIMM13_P (delta))
8668 {
8669 rtx scratch = gen_rtx_REG (Pmode, 1);
8670 emit_move_insn (scratch, delta_rtx);
8671 delta_rtx = scratch;
8672 }
8673
0a2aaacc
KG		 8674 /* THIS_RTX += DELTA. */
8675 emit_insn (gen_add2_insn (this_rtx, delta_rtx));
b9bf58e5
EB		 8676 }
8677
0a2aaacc 8678 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
b9bf58e5
EB		 8679 if (vcall_offset)
8680 {
8681 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
e133041b 8682 rtx scratch = gen_rtx_REG (Pmode, 1);
ed1fe829 8683
f5f7d171 8684 gcc_assert (vcall_offset < 0);
b9bf58e5 8685
0a2aaacc
KG		 8686 /* SCRATCH = *THIS_RTX. */
8687 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this_rtx));
b9bf58e5
EB		 8688
8689 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
8690 may not have any available scratch register at this point. */
8691 if (SPARC_SIMM13_P (vcall_offset))
8692 ;
8693 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
8694 else if (! fixed_regs[5]
8695 /* The below sequence is made up of at least 2 insns,
8696 while the default method may need only one. */
8697 && vcall_offset < -8192)
8698 {
8699 rtx scratch2 = gen_rtx_REG (Pmode, 5);
8700 emit_move_insn (scratch2, vcall_offset_rtx);
8701 vcall_offset_rtx = scratch2;
8702 }
e133041b 8703 else
ed1fe829 8704 {
b9bf58e5
EB		 8705 rtx increment = GEN_INT (-4096);
8706
8707 /* VCALL_OFFSET is a negative number whose typical range can be
8708 estimated as -32768..0 in 32-bit mode. In almost all cases
8709 it is therefore cheaper to emit multiple add insns than
8710 spilling and loading the constant into a register (at least
8711 6 insns). */
8712 while (! SPARC_SIMM13_P (vcall_offset))
8713 {
8714 emit_insn (gen_add2_insn (scratch, increment));
8715 vcall_offset += 4096;
8716 }
8717 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
ed1fe829
EB		 8718 }
8719
0a2aaacc 8720 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
b9bf58e5
EB		 8721 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
8722 gen_rtx_PLUS (Pmode,
8723 scratch,
8724 vcall_offset_rtx)));
e133041b 8725
0a2aaacc
KG		 8726 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
8727 emit_insn (gen_add2_insn (this_rtx, scratch));
b9bf58e5 8728 }
e133041b
RH		 8729
8730 /* Generate a tail call to the target function. */
8731 if (! TREE_USED (function))
8732 {
8733 assemble_external (function);
8734 TREE_USED (function) = 1;
8735 }
8736 funexp = XEXP (DECL_RTL (function), 0);
951661a1
EB		 8737
8738 if (flag_delayed_branch)
8739 {
8740 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8741 insn = emit_call_insn (gen_sibcall (funexp));
8742 SIBLING_CALL_P (insn) = 1;
8743 }
8744 else
8745 {
8746 /* The hoops we have to jump through in order to generate a sibcall
8747 without using delay slots... */
1b970c28 8748 rtx spill_reg, spill_reg2, seq, scratch = gen_rtx_REG (Pmode, 1);
951661a1
EB		 8749
8750 if (flag_pic)
8751 {
8752 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
1b970c28 8753 spill_reg2 = gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM);
951661a1 8754 start_sequence ();
5e77eb53
EB		 8755 /* Delay emitting the PIC helper function because it needs to
8756 change the section and we are emitting assembly code. */
8757 load_pic_register (true); /* clobbers %o7 */
951661a1
EB		 8758 scratch = legitimize_pic_address (funexp, Pmode, scratch);
8759 seq = get_insns ();
8760 end_sequence ();
1b970c28 8761 emit_and_preserve (seq, spill_reg, spill_reg2);
951661a1
EB		 8762 }
8763 else if (TARGET_ARCH32)
8764 {
8765 emit_insn (gen_rtx_SET (VOIDmode,
8766 scratch,
8767 gen_rtx_HIGH (SImode, funexp)));
8768 emit_insn (gen_rtx_SET (VOIDmode,
8769 scratch,
8770 gen_rtx_LO_SUM (SImode, scratch, funexp)));
8771 }
8772 else /* TARGET_ARCH64 */
8773 {
8774 switch (sparc_cmodel)
8775 {
8776 case CM_MEDLOW:
8777 case CM_MEDMID:
8778 /* The destination can serve as a temporary. */
8779 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
8780 break;
8781
8782 case CM_MEDANY:
8783 case CM_EMBMEDANY:
8784 /* The destination cannot serve as a temporary. */
8785 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
8786 start_sequence ();
8787 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
8788 seq = get_insns ();
8789 end_sequence ();
1b970c28 8790 emit_and_preserve (seq, spill_reg, 0);
951661a1
EB		 8791 break;
8792
8793 default:
f5f7d171 8794 gcc_unreachable ();
951661a1
EB		 8795 }
8796 }
8797
8798 emit_jump_insn (gen_indirect_jump (scratch));
8799 }
8800
e133041b
RH		 8801 emit_barrier ();
8802
8803 /* Run just enough of rest_of_compilation to get the insns emitted.
8804 There's not really enough bulk here to make other passes such as
8805 instruction scheduling worth while. Note that use_thunk calls
8806 assemble_start_function and assemble_end_function. */
8807 insn = get_insns ();
55e092c4 8808 insn_locators_alloc ();
e133041b
RH		 8809 shorten_branches (insn);
8810 final_start_function (insn, file, 1);
c9d691e9 8811 final (insn, file, 1);
e133041b 8812 final_end_function ();
6b0c2336 8813 free_after_compilation (cfun);
e133041b
RH		 8814
8815 reload_completed = 0;
fe3ad572 8816 epilogue_completed = 0;
e133041b 8817}
e2500fed 8818
b9bf58e5
EB		 8819/* Return true if sparc_output_mi_thunk would be able to output the
8820 assembler code for the thunk function specified by the arguments
8821 it is passed, and false otherwise. */
8822static bool
3101faab 8823sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
b9bf58e5
EB		 8824 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
8825 HOST_WIDE_INT vcall_offset,
3101faab 8826 const_tree function ATTRIBUTE_UNUSED)
b9bf58e5
EB		 8827{
8828 /* Bound the loop used in the default method above. */
8829 return (vcall_offset >= -32768 || ! fixed_regs[5]);
8830}
8831
5751a10b
JJ		 8832/* How to allocate a 'struct machine_function'. */
8833
8834static struct machine_function *
8835sparc_init_machine_status (void)
8836{
5ead67f6 8837 return GGC_CNEW (struct machine_function);
5751a10b
JJ		 8838}
8839
8840/* Locate some local-dynamic symbol still in use by this function
8841 so that we can print its name in local-dynamic base patterns. */
8842
8843static const char *
8844get_some_local_dynamic_name (void)
8845{
8846 rtx insn;
8847
8848 if (cfun->machine->some_ld_name)
8849 return cfun->machine->some_ld_name;
8850
8851 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8852 if (INSN_P (insn)
8853 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8854 return cfun->machine->some_ld_name;
8855
f5f7d171 8856 gcc_unreachable ();
5751a10b
JJ		 8857}
8858
8859static int
8860get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8861{
8862 rtx x = *px;
8863
8864 if (x
8865 && GET_CODE (x) == SYMBOL_REF
8866 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8867 {
8868 cfun->machine->some_ld_name = XSTR (x, 0);
8869 return 1;
8870 }
8871
8872 return 0;
8873}
8874
e54c7471
EB		 8875/* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
8876 This is called from dwarf2out.c to emit call frame instructions
8877 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
8878static void
8879sparc_dwarf_handle_frame_unspec (const char *label,
8880 rtx pattern ATTRIBUTE_UNUSED,
8881 int index ATTRIBUTE_UNUSED)
8882{
8883 gcc_assert (index == UNSPECV_SAVEW);
8884 dwarf2out_window_save (label);
8885}
8886
fdbe66f2 8887/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5751a10b
JJ		 8888 We need to emit DTP-relative relocations. */
8889
fdbe66f2 8890static void
5751a10b
JJ		 8891sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
8892{
8893 switch (size)
8894 {
8895 case 4:
8896 fputs ("\t.word\t%r_tls_dtpoff32(", file);
8897 break;
8898 case 8:
8899 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
8900 break;
8901 default:
f5f7d171 8902 gcc_unreachable ();
5751a10b
JJ		 8903 }
8904 output_addr_const (file, x);
8905 fputs (")", file);
8906}
8907
fdbe66f2
EB		 8908/* Do whatever processing is required at the end of a file. */
8909
8910static void
8911sparc_file_end (void)
5e77eb53
EB		 8912{
8913 /* If we haven't emitted the special PIC helper function, do so now. */
8914 if (pic_helper_symbol_name[0] && !pic_helper_emitted_p)
8915 emit_pic_helper ();
8916
8917 if (NEED_INDICATE_EXEC_STACK)
8918 file_end_indicate_exec_stack ();
8919}
8920
7269aee7 8921#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
608063c3 8922/* Implement TARGET_MANGLE_TYPE. */
7269aee7
AH		 8923
8924static const char *
3101faab 8925sparc_mangle_type (const_tree type)
7269aee7
AH		 8926{
8927 if (!TARGET_64BIT
8928 && TYPE_MAIN_VARIANT (type) == long_double_type_node
8929 && TARGET_LONG_DOUBLE_128)
8930 return "g";
8931
8932 /* For all other types, use normal C++ mangling. */
8933 return NULL;
8934}
8935#endif
8936
396b535a
JJ		 8937/* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
8938 compare and swap on the word containing the byte or half-word. */
8939
8940void
8941sparc_expand_compare_and_swap_12 (rtx result, rtx mem, rtx oldval, rtx newval)
8942{
8943 rtx addr1 = force_reg (Pmode, XEXP (mem, 0));
8944 rtx addr = gen_reg_rtx (Pmode);
8945 rtx off = gen_reg_rtx (SImode);
8946 rtx oldv = gen_reg_rtx (SImode);
8947 rtx newv = gen_reg_rtx (SImode);
8948 rtx oldvalue = gen_reg_rtx (SImode);
8949 rtx newvalue = gen_reg_rtx (SImode);
8950 rtx res = gen_reg_rtx (SImode);
8951 rtx resv = gen_reg_rtx (SImode);
8952 rtx memsi, val, mask, end_label, loop_label, cc;
8953
8954 emit_insn (gen_rtx_SET (VOIDmode, addr,
8955 gen_rtx_AND (Pmode, addr1, GEN_INT (-4))));
8956
8957 if (Pmode != SImode)
8958 addr1 = gen_lowpart (SImode, addr1);
8959 emit_insn (gen_rtx_SET (VOIDmode, off,
8960 gen_rtx_AND (SImode, addr1, GEN_INT (3))));
8961
8962 memsi = gen_rtx_MEM (SImode, addr);
44d64274 8963 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
396b535a
JJ		 8964 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
8965
8966 val = force_reg (SImode, memsi);
8967
8968 emit_insn (gen_rtx_SET (VOIDmode, off,
8969 gen_rtx_XOR (SImode, off,
8970 GEN_INT (GET_MODE (mem) == QImode
8971 ? 3 : 2))));
8972
8973 emit_insn (gen_rtx_SET (VOIDmode, off,
8974 gen_rtx_ASHIFT (SImode, off, GEN_INT (3))));
8975
8976 if (GET_MODE (mem) == QImode)
8977 mask = force_reg (SImode, GEN_INT (0xff));
8978 else
8979 mask = force_reg (SImode, GEN_INT (0xffff));
8980
8981 emit_insn (gen_rtx_SET (VOIDmode, mask,
8982 gen_rtx_ASHIFT (SImode, mask, off)));
8983
8984 emit_insn (gen_rtx_SET (VOIDmode, val,
8985 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
8986 val)));
8987
8988 oldval = gen_lowpart (SImode, oldval);
8989 emit_insn (gen_rtx_SET (VOIDmode, oldv,
8990 gen_rtx_ASHIFT (SImode, oldval, off)));
8991
8992 newval = gen_lowpart_common (SImode, newval);
8993 emit_insn (gen_rtx_SET (VOIDmode, newv,
8994 gen_rtx_ASHIFT (SImode, newval, off)));
8995
8996 emit_insn (gen_rtx_SET (VOIDmode, oldv,
8997 gen_rtx_AND (SImode, oldv, mask)));
8998
8999 emit_insn (gen_rtx_SET (VOIDmode, newv,
9000 gen_rtx_AND (SImode, newv, mask)));
9001
9002 end_label = gen_label_rtx ();
9003 loop_label = gen_label_rtx ();
9004 emit_label (loop_label);
9005
9006 emit_insn (gen_rtx_SET (VOIDmode, oldvalue,
9007 gen_rtx_IOR (SImode, oldv, val)));
9008
9009 emit_insn (gen_rtx_SET (VOIDmode, newvalue,
9010 gen_rtx_IOR (SImode, newv, val)));
9011
9012 emit_insn (gen_sync_compare_and_swapsi (res, memsi, oldvalue, newvalue));
9013
9014 emit_cmp_and_jump_insns (res, oldvalue, EQ, NULL, SImode, 0, end_label);
9015
9016 emit_insn (gen_rtx_SET (VOIDmode, resv,
9017 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
9018 res)));
9019
9020 sparc_compare_op0 = resv;
9021 sparc_compare_op1 = val;
9022 cc = gen_compare_reg (NE);
9023
9024 emit_insn (gen_rtx_SET (VOIDmode, val, resv));
9025
65c5ae8b
PB		 9026 sparc_compare_op0 = cc;
9027 sparc_compare_op1 = const0_rtx;
396b535a
JJ		 9028 emit_jump_insn (gen_bne (loop_label));
9029
9030 emit_label (end_label);
9031
9032 emit_insn (gen_rtx_SET (VOIDmode, res,
9033 gen_rtx_AND (SImode, res, mask)));
9034
9035 emit_insn (gen_rtx_SET (VOIDmode, res,
9036 gen_rtx_LSHIFTRT (SImode, res, off)));
9037
9038 emit_move_insn (result, gen_lowpart (GET_MODE (result), res));
9039}
9040
e2500fed 9041#include "gt-sparc.h"
Mirror of https://gcc.gnu.org/git/gcc.git