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c3427c7d 1/* Subroutines for insn-output.c for SPARC.
4592bdcb 2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
96e45421
JM		 3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011
62de55f7 5 Free Software Foundation, Inc.
ab835497 6 Contributed by Michael Tiemann (tiemann@cygnus.com)
c3427c7d 7 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
61a55e8b 8 at Cygnus Support.
ab835497 9
4d8af13f 10This file is part of GCC.
ab835497 11
4d8af13f 12GCC is free software; you can redistribute it and/or modify
ab835497 13it under the terms of the GNU General Public License as published by
2f83c7d6 14the Free Software Foundation; either version 3, or (at your option)
ab835497
RK		 15any later version.
16
4d8af13f 17GCC is distributed in the hope that it will be useful,
ab835497
RK		 18but WITHOUT ANY WARRANTY; without even the implied warranty of
19MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20GNU General Public License for more details.
21
22You should have received a copy of the GNU General Public License
2f83c7d6
NC		 23along with GCC; see the file COPYING3. If not see
24<http://www.gnu.org/licenses/>. */
ab835497 25
ab835497 26#include "config.h"
284d86e9 27#include "system.h"
4977bab6
ZW		 28#include "coretypes.h"
29#include "tm.h"
210aa14a 30#include "tree.h"
ab835497
RK		 31#include "rtl.h"
32#include "regs.h"
33#include "hard-reg-set.h"
ab835497 34#include "insn-config.h"
16f59241 35#include "insn-codes.h"
ab835497 36#include "conditions.h"
ab835497
RK		 37#include "output.h"
38#include "insn-attr.h"
39#include "flags.h"
49ad7cfa 40#include "function.h"
260c8ba3 41#include "except.h"
ab835497 42#include "expr.h"
e78d8e51 43#include "optabs.h"
ab835497 44#include "recog.h"
718f9c0f 45#include "diagnostic-core.h"
d07d525a 46#include "ggc.h"
b1474bb7 47#include "tm_p.h"
e78d8e51 48#include "debug.h"
672a6f42
NB		 49#include "target.h"
50#include "target-def.h"
677f3fa8 51#include "common/common-target.h"
117dca74 52#include "cfglayout.h"
726a989a 53#include "gimple.h"
16f59241 54#include "langhooks.h"
58e6223e 55#include "reload.h"
47eb5b32 56#include "params.h"
6fb5fa3c 57#include "df.h"
9fd52c6c 58#include "dwarf2out.h"
96e45421 59#include "opts.h"
ab835497 60
18df6de9
DM		 61/* Processor costs */
62static const
63struct processor_costs cypress_costs = {
ffe384ff
DM		 64 COSTS_N_INSNS (2), /* int load */
65 COSTS_N_INSNS (2), /* int signed load */
66 COSTS_N_INSNS (2), /* int zeroed load */
67 COSTS_N_INSNS (2), /* float load */
68 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
69 COSTS_N_INSNS (5), /* fadd, fsub */
70 COSTS_N_INSNS (1), /* fcmp */
71 COSTS_N_INSNS (1), /* fmov, fmovr */
72 COSTS_N_INSNS (7), /* fmul */
73 COSTS_N_INSNS (37), /* fdivs */
74 COSTS_N_INSNS (37), /* fdivd */
75 COSTS_N_INSNS (63), /* fsqrts */
76 COSTS_N_INSNS (63), /* fsqrtd */
77 COSTS_N_INSNS (1), /* imul */
78 COSTS_N_INSNS (1), /* imulX */
18df6de9 79 0, /* imul bit factor */
ffe384ff
DM		 80 COSTS_N_INSNS (1), /* idiv */
81 COSTS_N_INSNS (1), /* idivX */
82 COSTS_N_INSNS (1), /* movcc/movr */
18df6de9
DM		 83 0, /* shift penalty */
84};
85
86static const
87struct processor_costs supersparc_costs = {
ffe384ff
DM		 88 COSTS_N_INSNS (1), /* int load */
89 COSTS_N_INSNS (1), /* int signed load */
90 COSTS_N_INSNS (1), /* int zeroed load */
91 COSTS_N_INSNS (0), /* float load */
92 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
93 COSTS_N_INSNS (3), /* fadd, fsub */
94 COSTS_N_INSNS (3), /* fcmp */
95 COSTS_N_INSNS (1), /* fmov, fmovr */
96 COSTS_N_INSNS (3), /* fmul */
97 COSTS_N_INSNS (6), /* fdivs */
98 COSTS_N_INSNS (9), /* fdivd */
99 COSTS_N_INSNS (12), /* fsqrts */
100 COSTS_N_INSNS (12), /* fsqrtd */
101 COSTS_N_INSNS (4), /* imul */
102 COSTS_N_INSNS (4), /* imulX */
18df6de9 103 0, /* imul bit factor */
ffe384ff
DM		 104 COSTS_N_INSNS (4), /* idiv */
105 COSTS_N_INSNS (4), /* idivX */
106 COSTS_N_INSNS (1), /* movcc/movr */
18df6de9
DM		 107 1, /* shift penalty */
108};
109
110static const
111struct processor_costs hypersparc_costs = {
ffe384ff
DM		 112 COSTS_N_INSNS (1), /* int load */
113 COSTS_N_INSNS (1), /* int signed load */
114 COSTS_N_INSNS (1), /* int zeroed load */
115 COSTS_N_INSNS (1), /* float load */
116 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
117 COSTS_N_INSNS (1), /* fadd, fsub */
118 COSTS_N_INSNS (1), /* fcmp */
119 COSTS_N_INSNS (1), /* fmov, fmovr */
120 COSTS_N_INSNS (1), /* fmul */
121 COSTS_N_INSNS (8), /* fdivs */
122 COSTS_N_INSNS (12), /* fdivd */
123 COSTS_N_INSNS (17), /* fsqrts */
124 COSTS_N_INSNS (17), /* fsqrtd */
125 COSTS_N_INSNS (17), /* imul */
126 COSTS_N_INSNS (17), /* imulX */
18df6de9 127 0, /* imul bit factor */
ffe384ff
DM		 128 COSTS_N_INSNS (17), /* idiv */
129 COSTS_N_INSNS (17), /* idivX */
130 COSTS_N_INSNS (1), /* movcc/movr */
18df6de9
DM		 131 0, /* shift penalty */
132};
133
07981468
KE		 134static const
135struct processor_costs leon_costs = {
136 COSTS_N_INSNS (1), /* int load */
137 COSTS_N_INSNS (1), /* int signed load */
138 COSTS_N_INSNS (1), /* int zeroed load */
139 COSTS_N_INSNS (1), /* float load */
140 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
141 COSTS_N_INSNS (1), /* fadd, fsub */
142 COSTS_N_INSNS (1), /* fcmp */
143 COSTS_N_INSNS (1), /* fmov, fmovr */
144 COSTS_N_INSNS (1), /* fmul */
145 COSTS_N_INSNS (15), /* fdivs */
146 COSTS_N_INSNS (15), /* fdivd */
147 COSTS_N_INSNS (23), /* fsqrts */
148 COSTS_N_INSNS (23), /* fsqrtd */
149 COSTS_N_INSNS (5), /* imul */
150 COSTS_N_INSNS (5), /* imulX */
151 0, /* imul bit factor */
152 COSTS_N_INSNS (5), /* idiv */
153 COSTS_N_INSNS (5), /* idivX */
154 COSTS_N_INSNS (1), /* movcc/movr */
155 0, /* shift penalty */
156};
157
18df6de9
DM		 158static const
159struct processor_costs sparclet_costs = {
ffe384ff
DM		 160 COSTS_N_INSNS (3), /* int load */
161 COSTS_N_INSNS (3), /* int signed load */
162 COSTS_N_INSNS (1), /* int zeroed load */
163 COSTS_N_INSNS (1), /* float load */
164 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
165 COSTS_N_INSNS (1), /* fadd, fsub */
166 COSTS_N_INSNS (1), /* fcmp */
167 COSTS_N_INSNS (1), /* fmov, fmovr */
168 COSTS_N_INSNS (1), /* fmul */
169 COSTS_N_INSNS (1), /* fdivs */
170 COSTS_N_INSNS (1), /* fdivd */
171 COSTS_N_INSNS (1), /* fsqrts */
172 COSTS_N_INSNS (1), /* fsqrtd */
173 COSTS_N_INSNS (5), /* imul */
174 COSTS_N_INSNS (5), /* imulX */
18df6de9 175 0, /* imul bit factor */
ffe384ff
DM		 176 COSTS_N_INSNS (5), /* idiv */
177 COSTS_N_INSNS (5), /* idivX */
178 COSTS_N_INSNS (1), /* movcc/movr */
18df6de9
DM		 179 0, /* shift penalty */
180};
181
182static const
183struct processor_costs ultrasparc_costs = {
ffe384ff
DM		 184 COSTS_N_INSNS (2), /* int load */
185 COSTS_N_INSNS (3), /* int signed load */
186 COSTS_N_INSNS (2), /* int zeroed load */
187 COSTS_N_INSNS (2), /* float load */
188 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
189 COSTS_N_INSNS (4), /* fadd, fsub */
190 COSTS_N_INSNS (1), /* fcmp */
191 COSTS_N_INSNS (2), /* fmov, fmovr */
192 COSTS_N_INSNS (4), /* fmul */
193 COSTS_N_INSNS (13), /* fdivs */
194 COSTS_N_INSNS (23), /* fdivd */
195 COSTS_N_INSNS (13), /* fsqrts */
196 COSTS_N_INSNS (23), /* fsqrtd */
197 COSTS_N_INSNS (4), /* imul */
198 COSTS_N_INSNS (4), /* imulX */
18df6de9 199 2, /* imul bit factor */
ffe384ff
DM		 200 COSTS_N_INSNS (37), /* idiv */
201 COSTS_N_INSNS (68), /* idivX */
202 COSTS_N_INSNS (2), /* movcc/movr */
18df6de9
DM		 203 2, /* shift penalty */
204};
205
206static const
207struct processor_costs ultrasparc3_costs = {
ffe384ff
DM		 208 COSTS_N_INSNS (2), /* int load */
209 COSTS_N_INSNS (3), /* int signed load */
210 COSTS_N_INSNS (3), /* int zeroed load */
211 COSTS_N_INSNS (2), /* float load */
212 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
213 COSTS_N_INSNS (4), /* fadd, fsub */
214 COSTS_N_INSNS (5), /* fcmp */
215 COSTS_N_INSNS (3), /* fmov, fmovr */
216 COSTS_N_INSNS (4), /* fmul */
217 COSTS_N_INSNS (17), /* fdivs */
218 COSTS_N_INSNS (20), /* fdivd */
219 COSTS_N_INSNS (20), /* fsqrts */
220 COSTS_N_INSNS (29), /* fsqrtd */
221 COSTS_N_INSNS (6), /* imul */
222 COSTS_N_INSNS (6), /* imulX */
18df6de9 223 0, /* imul bit factor */
ffe384ff
DM		 224 COSTS_N_INSNS (40), /* idiv */
225 COSTS_N_INSNS (71), /* idivX */
226 COSTS_N_INSNS (2), /* movcc/movr */
18df6de9
DM		 227 0, /* shift penalty */
228};
229
4c837a1e
DM		 230static const
231struct processor_costs niagara_costs = {
232 COSTS_N_INSNS (3), /* int load */
233 COSTS_N_INSNS (3), /* int signed load */
234 COSTS_N_INSNS (3), /* int zeroed load */
235 COSTS_N_INSNS (9), /* float load */
236 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
237 COSTS_N_INSNS (8), /* fadd, fsub */
238 COSTS_N_INSNS (26), /* fcmp */
239 COSTS_N_INSNS (8), /* fmov, fmovr */
240 COSTS_N_INSNS (29), /* fmul */
241 COSTS_N_INSNS (54), /* fdivs */
242 COSTS_N_INSNS (83), /* fdivd */
243 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
244 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
245 COSTS_N_INSNS (11), /* imul */
246 COSTS_N_INSNS (11), /* imulX */
247 0, /* imul bit factor */
248 COSTS_N_INSNS (72), /* idiv */
249 COSTS_N_INSNS (72), /* idivX */
250 COSTS_N_INSNS (1), /* movcc/movr */
251 0, /* shift penalty */
252};
253
9eeaed6e
DM		 254static const
255struct processor_costs niagara2_costs = {
256 COSTS_N_INSNS (3), /* int load */
257 COSTS_N_INSNS (3), /* int signed load */
258 COSTS_N_INSNS (3), /* int zeroed load */
259 COSTS_N_INSNS (3), /* float load */
260 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
261 COSTS_N_INSNS (6), /* fadd, fsub */
262 COSTS_N_INSNS (6), /* fcmp */
263 COSTS_N_INSNS (6), /* fmov, fmovr */
264 COSTS_N_INSNS (6), /* fmul */
265 COSTS_N_INSNS (19), /* fdivs */
266 COSTS_N_INSNS (33), /* fdivd */
267 COSTS_N_INSNS (19), /* fsqrts */
268 COSTS_N_INSNS (33), /* fsqrtd */
269 COSTS_N_INSNS (5), /* imul */
270 COSTS_N_INSNS (5), /* imulX */
271 0, /* imul bit factor */
272 COSTS_N_INSNS (31), /* idiv, average of 12 - 41 cycle range */
273 COSTS_N_INSNS (31), /* idivX, average of 12 - 41 cycle range */
274 COSTS_N_INSNS (1), /* movcc/movr */
275 0, /* shift penalty */
276};
277
18df6de9
DM		 278const struct processor_costs *sparc_costs = &cypress_costs;
279
9ac617d4
EB		 280#ifdef HAVE_AS_RELAX_OPTION
281/* If 'as' and 'ld' are relaxing tail call insns into branch always, use
282 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
283 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
284 somebody does not branch between the sethi and jmp. */
6244b14e 285#define LEAF_SIBCALL_SLOT_RESERVED_P 1
9ac617d4 286#else
6244b14e
EB		 287#define LEAF_SIBCALL_SLOT_RESERVED_P \
288 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
9ac617d4
EB		 289#endif
290
563c12b0
RH		 291/* Vector to say how input registers are mapped to output registers.
292 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
293 eliminate it. You must use -fomit-frame-pointer to get that. */
d70e94ec 294char leaf_reg_remap[] =
ab835497
RK		 295{ 0, 1, 2, 3, 4, 5, 6, 7,
296 -1, -1, -1, -1, -1, -1, 14, -1,
297 -1, -1, -1, -1, -1, -1, -1, -1,
298 8, 9, 10, 11, 12, 13, -1, 15,
299
300 32, 33, 34, 35, 36, 37, 38, 39,
301 40, 41, 42, 43, 44, 45, 46, 47,
302 48, 49, 50, 51, 52, 53, 54, 55,
61a55e8b
DE		 303 56, 57, 58, 59, 60, 61, 62, 63,
304 64, 65, 66, 67, 68, 69, 70, 71,
305 72, 73, 74, 75, 76, 77, 78, 79,
306 80, 81, 82, 83, 84, 85, 86, 87,
307 88, 89, 90, 91, 92, 93, 94, 95,
c4ce6853 308 96, 97, 98, 99, 100};
ab835497 309
7d167afd
JJ		 310/* Vector, indexed by hard register number, which contains 1
311 for a register that is allowable in a candidate for leaf
312 function treatment. */
313char sparc_leaf_regs[] =
314{ 1, 1, 1, 1, 1, 1, 1, 1,
315 0, 0, 0, 0, 0, 0, 1, 0,
316 0, 0, 0, 0, 0, 0, 0, 0,
317 1, 1, 1, 1, 1, 1, 0, 1,
318 1, 1, 1, 1, 1, 1, 1, 1,
319 1, 1, 1, 1, 1, 1, 1, 1,
320 1, 1, 1, 1, 1, 1, 1, 1,
321 1, 1, 1, 1, 1, 1, 1, 1,
322 1, 1, 1, 1, 1, 1, 1, 1,
323 1, 1, 1, 1, 1, 1, 1, 1,
324 1, 1, 1, 1, 1, 1, 1, 1,
325 1, 1, 1, 1, 1, 1, 1, 1,
326 1, 1, 1, 1, 1};
327
d1b38208 328struct GTY(()) machine_function
5751a10b 329{
b11b0904
EB		 330 /* Size of the frame of the function. */
331 HOST_WIDE_INT frame_size;
332
333 /* Size of the frame of the function minus the register window save area
334 and the outgoing argument area. */
335 HOST_WIDE_INT apparent_frame_size;
336
337 /* Register we pretend the frame pointer is allocated to. Normally, this
338 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
339 record "offset" separately as it may be too big for (reg + disp). */
340 rtx frame_base_reg;
341 HOST_WIDE_INT frame_base_offset;
342
5751a10b
JJ		 343 /* Some local-dynamic TLS symbol name. */
344 const char *some_ld_name;
5be9b7a1 345
b11b0904
EB		 346 /* Number of global or FP registers to be saved (as 4-byte quantities). */
347 int n_global_fp_regs;
348
5be9b7a1
EB		 349 /* True if the current function is leaf and uses only leaf regs,
350 so that the SPARC leaf function optimization can be applied.
351 Private version of current_function_uses_only_leaf_regs, see
352 sparc_expand_prologue for the rationale. */
353 int leaf_function_p;
354
b11b0904
EB		 355 /* True if the prologue saves local or in registers. */
356 bool save_local_in_regs_p;
357
5be9b7a1
EB		 358 /* True if the data calculated by sparc_expand_prologue are valid. */
359 bool prologue_data_valid_p;
5751a10b
JJ		 360};
361
b11b0904
EB		 362#define sparc_frame_size cfun->machine->frame_size
363#define sparc_apparent_frame_size cfun->machine->apparent_frame_size
364#define sparc_frame_base_reg cfun->machine->frame_base_reg
365#define sparc_frame_base_offset cfun->machine->frame_base_offset
366#define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
367#define sparc_leaf_function_p cfun->machine->leaf_function_p
368#define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
369#define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
ab835497 370
4e5b002b
EB		 371/* 1 if the next opcode is to be specially indented. */
372int sparc_indent_opcode = 0;
373
c5387660 374static void sparc_option_override (void);
e80d5f80 375static void sparc_init_modes (void);
9adafb9f 376static void scan_record_type (const_tree, int *, int *, int *);
e80d5f80 377static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
9adafb9f 378 const_tree, bool, bool, int *, int *);
e80d5f80
KG		 379
380static int supersparc_adjust_cost (rtx, rtx, rtx, int);
381static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
382
d9816849
EB		 383static void sparc_emit_set_const32 (rtx, rtx);
384static void sparc_emit_set_const64 (rtx, rtx);
e80d5f80
KG		 385static void sparc_output_addr_vec (rtx);
386static void sparc_output_addr_diff_vec (rtx);
387static void sparc_output_deferred_case_vectors (void);
c6c3dba9 388static bool sparc_legitimate_address_p (enum machine_mode, rtx, bool);
1a627b35 389static bool sparc_legitimate_constant_p (enum machine_mode, rtx);
3e2cc1d1 390static rtx sparc_builtin_saveregs (void);
e80d5f80
KG		 391static int epilogue_renumber (rtx *, int);
392static bool sparc_assemble_integer (rtx, unsigned int, int);
393static int set_extends (rtx);
9ac617d4
EB		 394static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
395static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
7e32e652 396#ifdef TARGET_SOLARIS
d1ced155
EB		 397static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
398 tree) ATTRIBUTE_UNUSED;
7e32e652 399#endif
e80d5f80
KG		 400static int sparc_adjust_cost (rtx, rtx, rtx, int);
401static int sparc_issue_rate (void);
402static void sparc_sched_init (FILE *, int, int);
e80d5f80
KG		 403static int sparc_use_sched_lookahead (void);
404
405static void emit_soft_tfmode_libcall (const char *, int, rtx *);
406static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
407static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
408static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
409static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
410
411static bool sparc_function_ok_for_sibcall (tree, tree);
c15c90bb 412static void sparc_init_libfuncs (void);
16f59241
JM		 413static void sparc_init_builtins (void);
414static void sparc_vis_init_builtins (void);
415static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
f311c3b4 416static tree sparc_fold_builtin (tree, int, tree *, bool);
8b0096b4
JM		 417static int sparc_vis_mul8x16 (int, int);
418static tree sparc_handle_vis_mul8x16 (int, tree, tree, tree);
e80d5f80
KG		 419static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
420 HOST_WIDE_INT, tree);
3101faab
KG		 421static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,
422 HOST_WIDE_INT, const_tree);
5751a10b 423static struct machine_function * sparc_init_machine_status (void);
fbbf66e7 424static bool sparc_cannot_force_const_mem (enum machine_mode, rtx);
5751a10b
JJ		 425static rtx sparc_tls_get_addr (void);
426static rtx sparc_tls_got (void);
427static const char *get_some_local_dynamic_name (void);
428static int get_some_local_dynamic_name_1 (rtx *, void *);
32257ddc
AS		 429static int sparc_register_move_cost (enum machine_mode,
430 reg_class_t, reg_class_t);
f40751dd 431static bool sparc_rtx_costs (rtx, int, int, int *, bool);
bf44d792
AS		 432static rtx sparc_function_value (const_tree, const_tree, bool);
433static rtx sparc_libcall_value (enum machine_mode, const_rtx);
434static bool sparc_function_value_regno_p (const unsigned int);
3e2cc1d1 435static rtx sparc_struct_value_rtx (tree, int);
cde0f3fd
PB		 436static enum machine_mode sparc_promote_function_mode (const_tree, enum machine_mode,
437 int *, const_tree, int);
586de218 438static bool sparc_return_in_memory (const_tree, const_tree);
d5cc9181 439static bool sparc_strict_argument_naming (cumulative_args_t);
d7bd8aeb 440static void sparc_va_start (tree, rtx);
726a989a 441static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
c75d6010 442static bool sparc_vector_mode_supported_p (enum machine_mode);
208384fd 443static bool sparc_tls_referenced_p (rtx);
58e6223e
EB		 444static rtx sparc_legitimize_tls_address (rtx);
445static rtx sparc_legitimize_pic_address (rtx, rtx);
506d7b68 446static rtx sparc_legitimize_address (rtx, rtx, enum machine_mode);
8e7a6ed6 447static rtx sparc_delegitimize_address (rtx);
277e2873 448static bool sparc_mode_dependent_address_p (const_rtx);
d5cc9181 449static bool sparc_pass_by_reference (cumulative_args_t,
586de218 450 enum machine_mode, const_tree, bool);
d5cc9181 451static void sparc_function_arg_advance (cumulative_args_t,
9adafb9f 452 enum machine_mode, const_tree, bool);
d5cc9181 453static rtx sparc_function_arg_1 (cumulative_args_t,
9adafb9f 454 enum machine_mode, const_tree, bool, bool);
d5cc9181 455static rtx sparc_function_arg (cumulative_args_t,
9adafb9f 456 enum machine_mode, const_tree, bool);
d5cc9181 457static rtx sparc_function_incoming_arg (cumulative_args_t,
9adafb9f 458 enum machine_mode, const_tree, bool);
c2ed6cf8
NF		 459static unsigned int sparc_function_arg_boundary (enum machine_mode,
460 const_tree);
d5cc9181 461static int sparc_arg_partial_bytes (cumulative_args_t,
78a52f11 462 enum machine_mode, tree, bool);
e54c7471 463static void sparc_dwarf_handle_frame_unspec (const char *, rtx, int);
fdbe66f2 464static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5e77eb53 465static void sparc_file_end (void);
b52b1749 466static bool sparc_frame_pointer_required (void);
7b5cbb57 467static bool sparc_can_eliminate (const int, const int);
bc6d3f91 468static rtx sparc_builtin_setjmp_frame_value (void);
5efd84c5 469static void sparc_conditional_register_usage (void);
7269aee7 470#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
3101faab 471static const char *sparc_mangle_type (const_tree);
7269aee7 472#endif
809e78cc 473static void sparc_trampoline_init (rtx, tree, rtx);
cc4b5170 474static enum machine_mode sparc_preferred_simd_mode (enum machine_mode);
112a861d 475static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass);
46e43d2b
AS		 476static bool sparc_print_operand_punct_valid_p (unsigned char);
477static void sparc_print_operand (FILE *, rtx, int);
478static void sparc_print_operand_address (FILE *, rtx);
5a82ecd9 479\f
07a43492 480#ifdef SUBTARGET_ATTRIBUTE_TABLE
5a82ecd9
ILT		 481/* Table of valid machine attributes. */
482static const struct attribute_spec sparc_attribute_table[] =
483{
62d784f7
KT		 484 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
485 do_diagnostic } */
5a82ecd9 486 SUBTARGET_ATTRIBUTE_TABLE,
62d784f7 487 { NULL, 0, 0, false, false, false, NULL, false }
5a82ecd9 488};
07a43492 489#endif
61a55e8b
DE		 490\f
491/* Option handling. */
492
a0a301fc
DE		 493/* Parsed value. */
494enum cmodel sparc_cmodel;
495
1cb36a98
RH		 496char sparc_hard_reg_printed[8];
497
672a6f42 498/* Initialize the GCC target structure. */
301d03af 499
d1ced155 500/* The default is to use .half rather than .short for aligned HI objects. */
301d03af
RS		 501#undef TARGET_ASM_ALIGNED_HI_OP
502#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
301d03af
RS		 503
504#undef TARGET_ASM_UNALIGNED_HI_OP
505#define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
506#undef TARGET_ASM_UNALIGNED_SI_OP
507#define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
508#undef TARGET_ASM_UNALIGNED_DI_OP
509#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
510
511/* The target hook has to handle DI-mode values. */
512#undef TARGET_ASM_INTEGER
513#define TARGET_ASM_INTEGER sparc_assemble_integer
514
08c148a8 515#undef TARGET_ASM_FUNCTION_PROLOGUE
9ac617d4 516#define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
08c148a8 517#undef TARGET_ASM_FUNCTION_EPILOGUE
9ac617d4 518#define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
733f53f5 519
c237e94a
ZW		 520#undef TARGET_SCHED_ADJUST_COST
521#define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
522#undef TARGET_SCHED_ISSUE_RATE
523#define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
c237e94a
ZW		 524#undef TARGET_SCHED_INIT
525#define TARGET_SCHED_INIT sparc_sched_init
fae15c93
VM		 526#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
527#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
c237e94a 528
4977bab6
ZW		 529#undef TARGET_FUNCTION_OK_FOR_SIBCALL
530#define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
531
c15c90bb
ZW		 532#undef TARGET_INIT_LIBFUNCS
533#define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
16f59241
JM		 534#undef TARGET_INIT_BUILTINS
535#define TARGET_INIT_BUILTINS sparc_init_builtins
536
506d7b68
PB		 537#undef TARGET_LEGITIMIZE_ADDRESS
538#define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
8e7a6ed6
EB		 539#undef TARGET_DELEGITIMIZE_ADDRESS
540#define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
277e2873
AS		 541#undef TARGET_MODE_DEPENDENT_ADDRESS_P
542#define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
506d7b68 543
16f59241
JM		 544#undef TARGET_EXPAND_BUILTIN
545#define TARGET_EXPAND_BUILTIN sparc_expand_builtin
8b0096b4
JM		 546#undef TARGET_FOLD_BUILTIN
547#define TARGET_FOLD_BUILTIN sparc_fold_builtin
c15c90bb 548
fdbe66f2 549#if TARGET_TLS
5751a10b
JJ		 550#undef TARGET_HAVE_TLS
551#define TARGET_HAVE_TLS true
552#endif
fdbe66f2 553
5751a10b
JJ		 554#undef TARGET_CANNOT_FORCE_CONST_MEM
555#define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
556
c590b625
RH		 557#undef TARGET_ASM_OUTPUT_MI_THUNK
558#define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
3961e8fe 559#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
b9bf58e5 560#define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
c590b625 561
3c50106f
RH		 562#undef TARGET_RTX_COSTS
563#define TARGET_RTX_COSTS sparc_rtx_costs
dcefdf67 564#undef TARGET_ADDRESS_COST
f40751dd 565#define TARGET_ADDRESS_COST hook_int_rtx_bool_0
32257ddc
AS		 566#undef TARGET_REGISTER_MOVE_COST
567#define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
3c50106f 568
cde0f3fd
PB		 569#undef TARGET_PROMOTE_FUNCTION_MODE
570#define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
3e2cc1d1 571
bf44d792
AS		 572#undef TARGET_FUNCTION_VALUE
573#define TARGET_FUNCTION_VALUE sparc_function_value
574#undef TARGET_LIBCALL_VALUE
575#define TARGET_LIBCALL_VALUE sparc_libcall_value
576#undef TARGET_FUNCTION_VALUE_REGNO_P
577#define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
578
3e2cc1d1
KH		 579#undef TARGET_STRUCT_VALUE_RTX
580#define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
581#undef TARGET_RETURN_IN_MEMORY
582#define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
fe984136
RH		 583#undef TARGET_MUST_PASS_IN_STACK
584#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
8cd5a4e0
RH		 585#undef TARGET_PASS_BY_REFERENCE
586#define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
78a52f11
RH		 587#undef TARGET_ARG_PARTIAL_BYTES
588#define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
9adafb9f
NF		 589#undef TARGET_FUNCTION_ARG_ADVANCE
590#define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
591#undef TARGET_FUNCTION_ARG
592#define TARGET_FUNCTION_ARG sparc_function_arg
593#undef TARGET_FUNCTION_INCOMING_ARG
594#define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
c2ed6cf8
NF		 595#undef TARGET_FUNCTION_ARG_BOUNDARY
596#define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
3e2cc1d1
KH		 597
598#undef TARGET_EXPAND_BUILTIN_SAVEREGS
599#define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
600#undef TARGET_STRICT_ARGUMENT_NAMING
601#define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
602
d7bd8aeb
JJ		 603#undef TARGET_EXPAND_BUILTIN_VA_START
604#define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
5f393b25
JM		 605#undef TARGET_GIMPLIFY_VA_ARG_EXPR
606#define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
607
c75d6010
JM		 608#undef TARGET_VECTOR_MODE_SUPPORTED_P
609#define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
610
cc4b5170
RG		 611#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
612#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
26983c22 613
e54c7471
EB		 614#undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
615#define TARGET_DWARF_HANDLE_FRAME_UNSPEC sparc_dwarf_handle_frame_unspec
616
07a43492
DJ		 617#ifdef SUBTARGET_INSERT_ATTRIBUTES
618#undef TARGET_INSERT_ATTRIBUTES
619#define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
620#endif
621
622#ifdef SUBTARGET_ATTRIBUTE_TABLE
623#undef TARGET_ATTRIBUTE_TABLE
624#define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
625#endif
626
0e4e8dab 627#undef TARGET_RELAXED_ORDERING
548a6c4f 628#define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
445cf5eb 629
c5387660
JM		 630#undef TARGET_OPTION_OVERRIDE
631#define TARGET_OPTION_OVERRIDE sparc_option_override
fe609b0f 632
f06fb22b 633#if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
fdbe66f2
EB		 634#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
635#define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
636#endif
637
c81739f7 638#undef TARGET_ASM_FILE_END
5e77eb53
EB		 639#define TARGET_ASM_FILE_END sparc_file_end
640
b52b1749
AS		 641#undef TARGET_FRAME_POINTER_REQUIRED
642#define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
643
bc6d3f91
EB		 644#undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
645#define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
646
7b5cbb57
AS		 647#undef TARGET_CAN_ELIMINATE
648#define TARGET_CAN_ELIMINATE sparc_can_eliminate
bc6d3f91 649
112a861d
AS		 650#undef TARGET_PREFERRED_RELOAD_CLASS
651#define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
7b5cbb57 652
5efd84c5
NF		 653#undef TARGET_CONDITIONAL_REGISTER_USAGE
654#define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
655
7269aee7 656#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
608063c3
JB		 657#undef TARGET_MANGLE_TYPE
658#define TARGET_MANGLE_TYPE sparc_mangle_type
7269aee7
AH		 659#endif
660
c6c3dba9
PB		 661#undef TARGET_LEGITIMATE_ADDRESS_P
662#define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
663
1a627b35
RS		 664#undef TARGET_LEGITIMATE_CONSTANT_P
665#define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
666
809e78cc
RH		 667#undef TARGET_TRAMPOLINE_INIT
668#define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
669
46e43d2b
AS		 670#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
671#define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
672#undef TARGET_PRINT_OPERAND
673#define TARGET_PRINT_OPERAND sparc_print_operand
674#undef TARGET_PRINT_OPERAND_ADDRESS
675#define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
676
f6897b10 677struct gcc_target targetm = TARGET_INITIALIZER;
fe609b0f 678
61a55e8b
DE		 679/* Validate and override various options, and do some machine dependent
680 initialization. */
681
c5387660
JM		 682static void
683sparc_option_override (void)
61a55e8b 684{
a0a301fc 685 static struct code_model {
8b60264b 686 const char *const name;
32e8bb8e 687 const enum cmodel value;
8b60264b 688 } const cmodels[] = {
a0a301fc
DE		 689 { "32", CM_32 },
690 { "medlow", CM_MEDLOW },
691 { "medmid", CM_MEDMID },
692 { "medany", CM_MEDANY },
693 { "embmedany", CM_EMBMEDANY },
32e8bb8e 694 { NULL, (enum cmodel) 0 }
a0a301fc 695 };
8b60264b 696 const struct code_model *cmodel;
07981468 697 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
733f53f5 698 static struct cpu_default {
8b60264b 699 const int cpu;
aa53e58b 700 const enum processor_type processor;
8b60264b 701 } const cpu_default[] = {
a0a301fc 702 /* There must be one entry here for each TARGET_CPU value. */
aa53e58b
JM		 703 { TARGET_CPU_sparc, PROCESSOR_CYPRESS },
704 { TARGET_CPU_v8, PROCESSOR_V8 },
705 { TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC },
706 { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },
707 { TARGET_CPU_leon, PROCESSOR_LEON },
708 { TARGET_CPU_sparclite, PROCESSOR_F930 },
709 { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },
710 { TARGET_CPU_sparclet, PROCESSOR_TSC701 },
711 { TARGET_CPU_v9, PROCESSOR_V9 },
712 { TARGET_CPU_ultrasparc, PROCESSOR_ULTRASPARC },
713 { TARGET_CPU_ultrasparc3, PROCESSOR_ULTRASPARC3 },
714 { TARGET_CPU_niagara, PROCESSOR_NIAGARA },
715 { TARGET_CPU_niagara2, PROCESSOR_NIAGARA2 },
023592aa 716 { -1, PROCESSOR_V7 }
733f53f5 717 };
8b60264b 718 const struct cpu_default *def;
aa53e58b
JM		 719 /* Table of values for -m{cpu,tune}=. This must match the order of
720 the PROCESSOR_* enumeration. */
733f53f5 721 static struct cpu_table {
8b60264b
KG		 722 const int disable;
723 const int enable;
724 } const cpu_table[] = {
aa53e58b
JM		 725 { MASK_ISA, 0 },
726 { MASK_ISA, 0 },
727 { MASK_ISA, MASK_V8 },
733f53f5 728 /* TI TMS390Z55 supersparc */
aa53e58b
JM		 729 { MASK_ISA, MASK_V8 },
730 { MASK_ISA, MASK_V8|MASK_FPU },
07981468 731 /* LEON */
aa53e58b
JM		 732 { MASK_ISA, MASK_V8|MASK_FPU },
733 { MASK_ISA, MASK_SPARCLITE },
07981468 734 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
aa53e58b 735 { MASK_ISA|MASK_FPU, MASK_SPARCLITE },
07981468 736 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
aa53e58b
JM		 737 { MASK_ISA, MASK_SPARCLITE|MASK_FPU },
738 { MASK_ISA|MASK_FPU, MASK_SPARCLITE },
739 { MASK_ISA, MASK_SPARCLET },
733f53f5 740 /* TEMIC sparclet */
aa53e58b
JM		 741 { MASK_ISA, MASK_SPARCLET },
742 { MASK_ISA, MASK_V9 },
07981468 743 /* UltraSPARC I, II, IIi */
aa53e58b 744 { MASK_ISA,
07981468
KE		 745 /* Although insns using %y are deprecated, it is a clear win. */
746 MASK_V9|MASK_DEPRECATED_V8_INSNS},
747 /* UltraSPARC III */
748 /* ??? Check if %y issue still holds true. */
aa53e58b 749 { MASK_ISA,
07981468 750 MASK_V9|MASK_DEPRECATED_V8_INSNS},
4c837a1e 751 /* UltraSPARC T1 */
aa53e58b 752 { MASK_ISA,
07981468
KE		 753 MASK_V9|MASK_DEPRECATED_V8_INSNS},
754 /* UltraSPARC T2 */
aa53e58b 755 { MASK_ISA, MASK_V9},
733f53f5 756 };
8b60264b 757 const struct cpu_table *cpu;
b11b0904 758 unsigned int i;
a0a301fc 759 int fpu;
4900aa61 760
c5387660
JM		 761#ifdef SUBTARGET_OVERRIDE_OPTIONS
762 SUBTARGET_OVERRIDE_OPTIONS;
763#endif
764
a0a301fc
DE		 765#ifndef SPARC_BI_ARCH
766 /* Check for unsupported architecture size. */
767 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
3276910d
RK		 768 error ("%s is not supported by this configuration",
769 DEFAULT_ARCH32_P ? "-m64" : "-m32");
a0a301fc
DE		 770#endif
771
4710d3eb
JJ		 772 /* We force all 64bit archs to use 128 bit long double */
773 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
774 {
775 error ("-mlong-double-64 not allowed with -m64");
776 target_flags |= MASK_LONG_DOUBLE_128;
777 }
778
a0a301fc
DE		 779 /* Code model selection. */
780 sparc_cmodel = SPARC_DEFAULT_CMODEL;
4900aa61 781
345a6161
DM		 782#ifdef SPARC_BI_ARCH
783 if (TARGET_ARCH32)
784 sparc_cmodel = CM_32;
785#endif
786
a0a301fc
DE		 787 if (sparc_cmodel_string != NULL)
788 {
789 if (TARGET_ARCH64)
790 {
791 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
792 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
793 break;
794 if (cmodel->name == NULL)
795 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
796 else
797 sparc_cmodel = cmodel->value;
798 }
799 else
800 error ("-mcmodel= is not supported on 32 bit systems");
801 }
16956f6e 802
b11b0904
EB		 803 /* Check that -fcall-saved-REG wasn't specified for out registers. */
804 for (i = 8; i < 16; i++)
805 if (!call_used_regs [i])
806 {
807 error ("-fcall-saved-REG is not supported for out registers");
808 call_used_regs [i] = 1;
809 }
810
06063fa2 811 fpu = target_flags & MASK_FPU; /* save current -mfpu status */
1f1406b4 812
a0a301fc 813 /* Set the default CPU. */
aa53e58b 814 if (!global_options_set.x_sparc_cpu_and_features)
61a55e8b 815 {
aa53e58b
JM		 816 for (def = &cpu_default[0]; def->cpu != -1; ++def)
817 if (def->cpu == TARGET_CPU_DEFAULT)
818 break;
819 gcc_assert (def->cpu != -1);
820 sparc_cpu_and_features = def->processor;
61a55e8b 821 }
aa53e58b
JM		 822 if (!global_options_set.x_sparc_cpu)
823 sparc_cpu = sparc_cpu_and_features;
824
825 cpu = &cpu_table[(int) sparc_cpu_and_features];
826 target_flags &= ~cpu->disable;
827 target_flags |= cpu->enable;
97da85b7 828
1f1406b4 829 /* If -mfpu or -mno-fpu was explicitly used, don't override with
fe609b0f 830 the processor default. */
aa53e58b 831 if (target_flags_explicit & MASK_FPU)
fe609b0f 832 target_flags = (target_flags & ~MASK_FPU) | fpu;
1f1406b4 833
a5774a7d
JJ		 834 /* Don't allow -mvis if FPU is disabled. */
835 if (! TARGET_FPU)
836 target_flags &= ~MASK_VIS;
837
838 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
839 are available.
840 -m64 also implies v9. */
841 if (TARGET_VIS || TARGET_ARCH64)
c4031a04
JJ		 842 {
843 target_flags |= MASK_V9;
844 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
845 }
a5774a7d 846
16956f6e
DE		 847 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
848 if (TARGET_V9 && TARGET_ARCH32)
733f53f5 849 target_flags |= MASK_DEPRECATED_V8_INSNS;
61a55e8b 850
345a6161
DM		 851 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
852 if (! TARGET_V9 || TARGET_ARCH64)
284d86e9
JC		 853 target_flags &= ~MASK_V8PLUS;
854
82d6b402
RH		 855 /* Don't use stack biasing in 32 bit mode. */
856 if (TARGET_ARCH32)
857 target_flags &= ~MASK_STACK_BIAS;
4900aa61 858
efa3896a 859 /* Supply a default value for align_functions. */
fae15c93
VM		 860 if (align_functions == 0
861 && (sparc_cpu == PROCESSOR_ULTRASPARC
4c837a1e 862 || sparc_cpu == PROCESSOR_ULTRASPARC3
9eeaed6e
DM		 863 || sparc_cpu == PROCESSOR_NIAGARA
864 || sparc_cpu == PROCESSOR_NIAGARA2))
efa3896a 865 align_functions = 32;
bf62bbf1 866
82d6b402
RH		 867 /* Validate PCC_STRUCT_RETURN. */
868 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
869 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
870
301d03af
RS		 871 /* Only use .uaxword when compiling for a 64-bit target. */
872 if (!TARGET_ARCH64)
873 targetm.asm_out.unaligned_op.di = NULL;
874
61a55e8b
DE		 875 /* Do various machine dependent initializations. */
876 sparc_init_modes ();
5751a10b
JJ		 877
878 /* Set up function hooks. */
879 init_machine_status = sparc_init_machine_status;
18df6de9
DM		 880
881 switch (sparc_cpu)
882 {
883 case PROCESSOR_V7:
884 case PROCESSOR_CYPRESS:
885 sparc_costs = &cypress_costs;
886 break;
887 case PROCESSOR_V8:
888 case PROCESSOR_SPARCLITE:
889 case PROCESSOR_SUPERSPARC:
890 sparc_costs = &supersparc_costs;
891 break;
892 case PROCESSOR_F930:
893 case PROCESSOR_F934:
894 case PROCESSOR_HYPERSPARC:
895 case PROCESSOR_SPARCLITE86X:
896 sparc_costs = &hypersparc_costs;
897 break;
07981468
KE		 898 case PROCESSOR_LEON:
899 sparc_costs = &leon_costs;
900 break;
18df6de9
DM		 901 case PROCESSOR_SPARCLET:
902 case PROCESSOR_TSC701:
903 sparc_costs = &sparclet_costs;
904 break;
905 case PROCESSOR_V9:
906 case PROCESSOR_ULTRASPARC:
907 sparc_costs = &ultrasparc_costs;
908 break;
909 case PROCESSOR_ULTRASPARC3:
910 sparc_costs = &ultrasparc3_costs;
911 break;
4c837a1e
DM		 912 case PROCESSOR_NIAGARA:
913 sparc_costs = &niagara_costs;
914 break;
9eeaed6e
DM		 915 case PROCESSOR_NIAGARA2:
916 sparc_costs = &niagara2_costs;
917 break;
18df6de9 918 };
ed965309
JJ		 919
920#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
921 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
922 target_flags |= MASK_LONG_DOUBLE_128;
923#endif
47eb5b32 924
128dc8e2
JM		 925 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
926 ((sparc_cpu == PROCESSOR_ULTRASPARC
927 || sparc_cpu == PROCESSOR_NIAGARA
928 || sparc_cpu == PROCESSOR_NIAGARA2)
929 ? 2
930 : (sparc_cpu == PROCESSOR_ULTRASPARC3
48476d13
JM		 931 ? 8 : 3)),
932 global_options.x_param_values,
933 global_options_set.x_param_values);
128dc8e2
JM		 934 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
935 ((sparc_cpu == PROCESSOR_ULTRASPARC
936 || sparc_cpu == PROCESSOR_ULTRASPARC3
937 || sparc_cpu == PROCESSOR_NIAGARA
938 || sparc_cpu == PROCESSOR_NIAGARA2)
48476d13
JM		 939 ? 64 : 32),
940 global_options.x_param_values,
941 global_options_set.x_param_values);
24d1bbc7
EB		 942
943 /* Disable save slot sharing for call-clobbered registers by default.
944 The IRA sharing algorithm works on single registers only and this
945 pessimizes for double floating-point registers. */
946 if (!global_options_set.x_flag_ira_share_save_slots)
947 flag_ira_share_save_slots = 0;
61a55e8b
DE		 948}
949\f
cd5fb1ee
DE		 950/* Miscellaneous utilities. */
951
952/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
953 or branch on register contents instructions. */
954
955int
fc27d102 956v9_regcmp_p (enum rtx_code code)
cd5fb1ee
DE		 957{
958 return (code == EQ || code == NE || code == GE || code == LT
959 || code == LE || code == GT);
960}
bfd6bc60 961
62190128
DM		 962/* Nonzero if OP is a floating point constant which can
963 be loaded into an integer register using a single
964 sethi instruction. */
965
966int
fc27d102 967fp_sethi_p (rtx op)
62190128
DM		 968{
969 if (GET_CODE (op) == CONST_DOUBLE)
970 {
971 REAL_VALUE_TYPE r;
972 long i;
973
974 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
62190128 975 REAL_VALUE_TO_TARGET_SINGLE (r, i);
9a9e266b 976 return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i);
62190128
DM		 977 }
978
979 return 0;
980}
981
982/* Nonzero if OP is a floating point constant which can
983 be loaded into an integer register using a single
984 mov instruction. */
985
986int
fc27d102 987fp_mov_p (rtx op)
62190128
DM		 988{
989 if (GET_CODE (op) == CONST_DOUBLE)
990 {
991 REAL_VALUE_TYPE r;
992 long i;
993
994 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
62190128 995 REAL_VALUE_TO_TARGET_SINGLE (r, i);
9a9e266b 996 return SPARC_SIMM13_P (i);
62190128
DM		 997 }
998
999 return 0;
1000}
1001
1002/* Nonzero if OP is a floating point constant which can
1003 be loaded into an integer register using a high/losum
1004 instruction sequence. */
1005
1006int
fc27d102 1007fp_high_losum_p (rtx op)
62190128
DM		 1008{
1009 /* The constraints calling this should only be in
1010 SFmode move insns, so any constant which cannot
1011 be moved using a single insn will do. */
1012 if (GET_CODE (op) == CONST_DOUBLE)
1013 {
1014 REAL_VALUE_TYPE r;
1015 long i;
1016
1017 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
62190128 1018 REAL_VALUE_TO_TARGET_SINGLE (r, i);
9a9e266b 1019 return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i);
62190128
DM		 1020 }
1021
1022 return 0;
1023}
1024
205e4c6a
EB		 1025/* Return true if the address of LABEL can be loaded by means of the
1026 mov{si,di}_pic_label_ref patterns in PIC mode. */
1027
1028static bool
1029can_use_mov_pic_label_ref (rtx label)
1030{
1031 /* VxWorks does not impose a fixed gap between segments; the run-time
1032 gap can be different from the object-file gap. We therefore can't
1033 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1034 are absolutely sure that X is in the same segment as the GOT.
1035 Unfortunately, the flexibility of linker scripts means that we
1036 can't be sure of that in general, so assume that GOT-relative
1037 accesses are never valid on VxWorks. */
1038 if (TARGET_VXWORKS_RTP)
1039 return false;
1040
1041 /* Similarly, if the label is non-local, it might end up being placed
1042 in a different section than the current one; now mov_pic_label_ref
1043 requires the label and the code to be in the same section. */
1044 if (LABEL_REF_NONLOCAL_P (label))
1045 return false;
1046
1047 /* Finally, if we are reordering basic blocks and partition into hot
1048 and cold sections, this might happen for any label. */
1049 if (flag_reorder_blocks_and_partition)
1050 return false;
1051
1052 return true;
1053}
1054
bea5071f
EB		 1055/* Expand a move instruction. Return true if all work is done. */
1056
1057bool
1058sparc_expand_move (enum machine_mode mode, rtx *operands)
1059{
1060 /* Handle sets of MEM first. */
1061 if (GET_CODE (operands[0]) == MEM)
1062 {
1063 /* 0 is a register (or a pair of registers) on SPARC. */
1064 if (register_or_zero_operand (operands[1], mode))
1065 return false;
1066
1067 if (!reload_in_progress)
1068 {
1069 operands[0] = validize_mem (operands[0]);
1070 operands[1] = force_reg (mode, operands[1]);
1071 }
1072 }
1073
1074 /* Fixup TLS cases. */
38fc66ba
EB		 1075 if (TARGET_HAVE_TLS
1076 && CONSTANT_P (operands[1])
38fc66ba
EB		 1077 && sparc_tls_referenced_p (operands [1]))
1078 {
58e6223e 1079 operands[1] = sparc_legitimize_tls_address (operands[1]);
208384fd 1080 return false;
38fc66ba 1081 }
4900aa61 1082
bea5071f
EB		 1083 /* Fixup PIC cases. */
1084 if (flag_pic && CONSTANT_P (operands[1]))
1085 {
1086 if (pic_address_needs_scratch (operands[1]))
58e6223e 1087 operands[1] = sparc_legitimize_pic_address (operands[1], NULL_RTX);
bea5071f 1088
205e4c6a
EB		 1089 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1090 if (GET_CODE (operands[1]) == LABEL_REF
1091 && can_use_mov_pic_label_ref (operands[1]))
bea5071f 1092 {
1910440e
RS		 1093 if (mode == SImode)
1094 {
1095 emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
1096 return true;
1097 }
bea5071f 1098
1910440e
RS		 1099 if (mode == DImode)
1100 {
1101 gcc_assert (TARGET_ARCH64);
1102 emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
1103 return true;
1104 }
bea5071f
EB		 1105 }
1106
1107 if (symbolic_operand (operands[1], mode))
1108 {
58e6223e
EB		 1109 operands[1]
1110 = sparc_legitimize_pic_address (operands[1],
1111 reload_in_progress
1112 ? operands[0] : NULL_RTX);
bea5071f
EB		 1113 return false;
1114 }
1115 }
1116
1117 /* If we are trying to toss an integer constant into FP registers,
1118 or loading a FP or vector constant, force it into memory. */
1119 if (CONSTANT_P (operands[1])
1120 && REG_P (operands[0])
1121 && (SPARC_FP_REG_P (REGNO (operands[0]))
1122 || SCALAR_FLOAT_MODE_P (mode)
1123 || VECTOR_MODE_P (mode)))
1124 {
1125 /* emit_group_store will send such bogosity to us when it is
1126 not storing directly into memory. So fix this up to avoid
1127 crashes in output_constant_pool. */
1128 if (operands [1] == const0_rtx)
1129 operands[1] = CONST0_RTX (mode);
1130
1131 /* We can clear FP registers if TARGET_VIS, and always other regs. */
1132 if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
1133 && const_zero_operand (operands[1], mode))
1134 return false;
1135
1136 if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
1137 /* We are able to build any SF constant in integer registers
1138 with at most 2 instructions. */
1139 && (mode == SFmode
1140 /* And any DF constant in integer registers. */
1141 || (mode == DFmode
1142 && (reload_completed || reload_in_progress))))
1143 return false;
1144
1145 operands[1] = force_const_mem (mode, operands[1]);
1146 if (!reload_in_progress)
1147 operands[1] = validize_mem (operands[1]);
1148 return false;
1149 }
1150
1151 /* Accept non-constants and valid constants unmodified. */
1152 if (!CONSTANT_P (operands[1])
1153 || GET_CODE (operands[1]) == HIGH
1154 || input_operand (operands[1], mode))
1155 return false;
1156
1157 switch (mode)
1158 {
1159 case QImode:
1160 /* All QImode constants require only one insn, so proceed. */
1161 break;
1162
1163 case HImode:
1164 case SImode:
1165 sparc_emit_set_const32 (operands[0], operands[1]);
1166 return true;
1167
1168 case DImode:
1169 /* input_operand should have filtered out 32-bit mode. */
1170 sparc_emit_set_const64 (operands[0], operands[1]);
1171 return true;
4900aa61 1172
bea5071f
EB		 1173 default:
1174 gcc_unreachable ();
1175 }
1176
1177 return false;
1178}
1179
1180/* Load OP1, a 32-bit constant, into OP0, a register.
1181 We know it can't be done in one insn when we get
1182 here, the move expander guarantees this. */
1183
d9816849 1184static void
fc27d102 1185sparc_emit_set_const32 (rtx op0, rtx op1)
e0d80184
DM		 1186{
1187 enum machine_mode mode = GET_MODE (op0);
1188 rtx temp;
1189
e0d80184
DM		 1190 if (reload_in_progress || reload_completed)
1191 temp = op0;
284d86e9 1192 else
e0d80184
DM		 1193 temp = gen_reg_rtx (mode);
1194
71648202
DM		 1195 if (GET_CODE (op1) == CONST_INT)
1196 {
0e5d569c
EB		 1197 gcc_assert (!small_int_operand (op1, mode)
1198 && !const_high_operand (op1, mode));
1199
71648202
DM		 1200 /* Emit them as real moves instead of a HIGH/LO_SUM,
1201 this way CSE can see everything and reuse intermediate
1202 values if it wants. */
0e5d569c
EB		 1203 emit_insn (gen_rtx_SET (VOIDmode, temp,
1204 GEN_INT (INTVAL (op1)
1205 & ~(HOST_WIDE_INT)0x3ff)));
f2827474 1206
71648202
DM		 1207 emit_insn (gen_rtx_SET (VOIDmode,
1208 op0,
f2827474 1209 gen_rtx_IOR (mode, temp,
71648202
DM		 1210 GEN_INT (INTVAL (op1) & 0x3ff))));
1211 }
1212 else
1213 {
1214 /* A symbol, emit in the traditional way. */
f2827474
RK		 1215 emit_insn (gen_rtx_SET (VOIDmode, temp,
1216 gen_rtx_HIGH (mode, op1)));
71648202 1217 emit_insn (gen_rtx_SET (VOIDmode,
f2827474 1218 op0, gen_rtx_LO_SUM (mode, temp, op1)));
71648202 1219 }
e0d80184
DM		 1220}
1221
1d511ed5 1222/* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
0e40b5f2 1223 If TEMP is nonzero, we are forbidden to use any other scratch
1d511ed5
EB		 1224 registers. Otherwise, we are allowed to generate them as needed.
1225
1226 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1227 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
bea5071f 1228
e0d80184 1229void
1d511ed5 1230sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
e0d80184 1231{
1d511ed5
EB		 1232 rtx temp1, temp2, temp3, temp4, temp5;
1233 rtx ti_temp = 0;
3968de80 1234
1d511ed5 1235 if (temp && GET_MODE (temp) == TImode)
3968de80 1236 {
1d511ed5
EB		 1237 ti_temp = temp;
1238 temp = gen_rtx_REG (DImode, REGNO (temp));
3968de80
DD		 1239 }
1240
1d511ed5 1241 /* SPARC-V9 code-model support. */
e0d80184 1242 switch (sparc_cmodel)
284d86e9 1243 {
e0d80184
DM		 1244 case CM_MEDLOW:
1245 /* The range spanned by all instructions in the object is less
1246 than 2^31 bytes (2GB) and the distance from any instruction
1247 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1248 than 2^31 bytes (2GB).
ab835497 1249
e0d80184
DM		 1250 The executable must be in the low 4TB of the virtual address
1251 space.
61a55e8b 1252
1d511ed5
EB		 1253 sethi %hi(symbol), %temp1
1254 or %temp1, %lo(symbol), %reg */
1255 if (temp)
1256 temp1 = temp; /* op0 is allowed. */
1257 else
1258 temp1 = gen_reg_rtx (DImode);
1259
9208e4b2
DM		 1260 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1261 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
e0d80184 1262 break;
61a55e8b 1263
e0d80184
DM		 1264 case CM_MEDMID:
1265 /* The range spanned by all instructions in the object is less
1266 than 2^31 bytes (2GB) and the distance from any instruction
1267 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1268 than 2^31 bytes (2GB).
1269
1270 The executable must be in the low 16TB of the virtual address
1271 space.
1272
1273 sethi %h44(symbol), %temp1
1274 or %temp1, %m44(symbol), %temp2
1275 sllx %temp2, 12, %temp3
1276 or %temp3, %l44(symbol), %reg */
1d511ed5
EB		 1277 if (temp)
1278 {
1279 temp1 = op0;
1280 temp2 = op0;
1281 temp3 = temp; /* op0 is allowed. */
1282 }
1283 else
1284 {
1285 temp1 = gen_reg_rtx (DImode);
1286 temp2 = gen_reg_rtx (DImode);
1287 temp3 = gen_reg_rtx (DImode);
1288 }
1289
1290 emit_insn (gen_seth44 (temp1, op1));
1291 emit_insn (gen_setm44 (temp2, temp1, op1));
1292 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1293 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1294 emit_insn (gen_setl44 (op0, temp3, op1));
e0d80184 1295 break;
61a55e8b 1296
e0d80184
DM		 1297 case CM_MEDANY:
1298 /* The range spanned by all instructions in the object is less
1299 than 2^31 bytes (2GB) and the distance from any instruction
1300 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1301 than 2^31 bytes (2GB).
1302
1303 The executable can be placed anywhere in the virtual address
1304 space.
1305
1306 sethi %hh(symbol), %temp1
1307 sethi %lm(symbol), %temp2
1308 or %temp1, %hm(symbol), %temp3
1d511ed5
EB		 1309 sllx %temp3, 32, %temp4
1310 or %temp4, %temp2, %temp5
1311 or %temp5, %lo(symbol), %reg */
1312 if (temp)
3968de80 1313 {
1d511ed5
EB		 1314 /* It is possible that one of the registers we got for operands[2]
1315 might coincide with that of operands[0] (which is why we made
1316 it TImode). Pick the other one to use as our scratch. */
1317 if (rtx_equal_p (temp, op0))
1318 {
f5f7d171
JM		 1319 gcc_assert (ti_temp);
1320 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1d511ed5
EB		 1321 }
1322 temp1 = op0;
1323 temp2 = temp; /* op0 is _not_ allowed, see above. */
1324 temp3 = op0;
1325 temp4 = op0;
1326 temp5 = op0;
1327 }
1328 else
1329 {
1330 temp1 = gen_reg_rtx (DImode);
1331 temp2 = gen_reg_rtx (DImode);
1332 temp3 = gen_reg_rtx (DImode);
1333 temp4 = gen_reg_rtx (DImode);
1334 temp5 = gen_reg_rtx (DImode);
3968de80 1335 }
61a55e8b 1336
1d511ed5
EB		 1337 emit_insn (gen_sethh (temp1, op1));
1338 emit_insn (gen_setlm (temp2, op1));
1339 emit_insn (gen_sethm (temp3, temp1, op1));
1340 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1341 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1342 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1343 gen_rtx_PLUS (DImode, temp4, temp2)));
1344 emit_insn (gen_setlo (op0, temp5, op1));
e0d80184 1345 break;
61a55e8b 1346
e0d80184
DM		 1347 case CM_EMBMEDANY:
1348 /* Old old old backwards compatibility kruft here.
1349 Essentially it is MEDLOW with a fixed 64-bit
1350 virtual base added to all data segment addresses.
1351 Text-segment stuff is computed like MEDANY, we can't
1352 reuse the code above because the relocation knobs
1353 look different.
1354
1355 Data segment: sethi %hi(symbol), %temp1
1d511ed5
EB		 1356 add %temp1, EMBMEDANY_BASE_REG, %temp2
1357 or %temp2, %lo(symbol), %reg */
e0d80184
DM		 1358 if (data_segment_operand (op1, GET_MODE (op1)))
1359 {
1d511ed5
EB		 1360 if (temp)
1361 {
1362 temp1 = temp; /* op0 is allowed. */
1363 temp2 = op0;
1364 }
1365 else
1366 {
1367 temp1 = gen_reg_rtx (DImode);
1368 temp2 = gen_reg_rtx (DImode);
1369 }
1370
e0d80184 1371 emit_insn (gen_embmedany_sethi (temp1, op1));
1d511ed5
EB		 1372 emit_insn (gen_embmedany_brsum (temp2, temp1));
1373 emit_insn (gen_embmedany_losum (op0, temp2, op1));
e0d80184 1374 }
1d511ed5
EB		 1375
1376 /* Text segment: sethi %uhi(symbol), %temp1
1377 sethi %hi(symbol), %temp2
1378 or %temp1, %ulo(symbol), %temp3
1379 sllx %temp3, 32, %temp4
1380 or %temp4, %temp2, %temp5
1381 or %temp5, %lo(symbol), %reg */
e0d80184
DM		 1382 else
1383 {
1d511ed5 1384 if (temp)
3968de80 1385 {
1d511ed5
EB		 1386 /* It is possible that one of the registers we got for operands[2]
1387 might coincide with that of operands[0] (which is why we made
1388 it TImode). Pick the other one to use as our scratch. */
1389 if (rtx_equal_p (temp, op0))
1390 {
f5f7d171
JM		 1391 gcc_assert (ti_temp);
1392 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1d511ed5
EB		 1393 }
1394 temp1 = op0;
1395 temp2 = temp; /* op0 is _not_ allowed, see above. */
1396 temp3 = op0;
1397 temp4 = op0;
1398 temp5 = op0;
1399 }
1400 else
1401 {
1402 temp1 = gen_reg_rtx (DImode);
1403 temp2 = gen_reg_rtx (DImode);
1404 temp3 = gen_reg_rtx (DImode);
1405 temp4 = gen_reg_rtx (DImode);
1406 temp5 = gen_reg_rtx (DImode);
3968de80 1407 }
61a55e8b 1408
1d511ed5
EB		 1409 emit_insn (gen_embmedany_textuhi (temp1, op1));
1410 emit_insn (gen_embmedany_texthi (temp2, op1));
1411 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1412 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1413 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1414 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1415 gen_rtx_PLUS (DImode, temp4, temp2)));
1416 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
e0d80184
DM		 1417 }
1418 break;
1419
1420 default:
f5f7d171 1421 gcc_unreachable ();
e0d80184
DM		 1422 }
1423}
1424
0e5d569c 1425#if HOST_BITS_PER_WIDE_INT == 32
d9816849 1426static void
0e5d569c
EB		 1427sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED)
1428{
1429 gcc_unreachable ();
1430}
1431#else
9208e4b2
DM		 1432/* These avoid problems when cross compiling. If we do not
1433 go through all this hair then the optimizer will see
1434 invalid REG_EQUAL notes or in some cases none at all. */
9bb3323d 1435static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT);
e80d5f80
KG		 1436static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1437static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1438static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
9208e4b2 1439
9208e4b2
DM		 1440/* The optimizer is not to assume anything about exactly
1441 which bits are set for a HIGH, they are unspecified.
1442 Unfortunately this leads to many missed optimizations
1443 during CSE. We mask out the non-HIGH bits, and matches
1444 a plain movdi, to alleviate this problem. */
9bb3323d
EB		 1445static rtx
1446gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
9208e4b2 1447{
9bb3323d 1448 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff));
9208e4b2 1449}
2a01c939 1450
e0d80184 1451static rtx
fc27d102 1452gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
61a55e8b 1453{
0e5d569c 1454 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val));
9208e4b2
DM		 1455}
1456
1457static rtx
fc27d102 1458gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
9208e4b2 1459{
0e5d569c 1460 return gen_rtx_IOR (DImode, src, GEN_INT (val));
9208e4b2
DM		 1461}
1462
1463static rtx
fc27d102 1464gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
9208e4b2 1465{
0e5d569c 1466 return gen_rtx_XOR (DImode, src, GEN_INT (val));
e0d80184 1467}
61a55e8b 1468
e0d80184
DM		 1469/* Worker routines for 64-bit constant formation on arch64.
1470 One of the key things to be doing in these emissions is
1471 to create as many temp REGs as possible. This makes it
1472 possible for half-built constants to be used later when
1473 such values are similar to something required later on.
1474 Without doing this, the optimizer cannot see such
1475 opportunities. */
2a01c939 1476
e80d5f80
KG		 1477static void sparc_emit_set_const64_quick1 (rtx, rtx,
1478 unsigned HOST_WIDE_INT, int);
2a01c939 1479
e0d80184 1480static void
fc27d102
KG		 1481sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1482 unsigned HOST_WIDE_INT low_bits, int is_neg)
e0d80184 1483{
2a01c939 1484 unsigned HOST_WIDE_INT high_bits;
a9e27770 1485
e0d80184 1486 if (is_neg)
2a01c939 1487 high_bits = (~low_bits) & 0xffffffff;
31bc9eba 1488 else
e0d80184 1489 high_bits = low_bits;
31bc9eba 1490
9bb3323d 1491 emit_insn (gen_safe_HIGH64 (temp, high_bits));
e0d80184 1492 if (!is_neg)
5108f3e5
DM		 1493 {
1494 emit_insn (gen_rtx_SET (VOIDmode, op0,
1495 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1496 }
e0d80184 1497 else
5108f3e5
DM		 1498 {
1499 /* If we are XOR'ing with -1, then we should emit a one's complement
1500 instead. This way the combiner will notice logical operations
1501 such as ANDN later on and substitute. */
1502 if ((low_bits & 0x3ff) == 0x3ff)
1503 {
1504 emit_insn (gen_rtx_SET (VOIDmode, op0,
1505 gen_rtx_NOT (DImode, temp)));
1506 }
1507 else
1508 {
1509 emit_insn (gen_rtx_SET (VOIDmode, op0,
1510 gen_safe_XOR64 (temp,
9e0625a3
AO		 1511 (-(HOST_WIDE_INT)0x400
1512 | (low_bits & 0x3ff)))));
5108f3e5
DM		 1513 }
1514 }
e0d80184 1515}
61a55e8b 1516
e80d5f80
KG		 1517static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1518 unsigned HOST_WIDE_INT, int);
2a01c939 1519
e0d80184 1520static void
fc27d102
KG		 1521sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1522 unsigned HOST_WIDE_INT high_bits,
1523 unsigned HOST_WIDE_INT low_immediate,
1524 int shift_count)
e0d80184
DM		 1525{
1526 rtx temp2 = op0;
61a55e8b 1527
e0d80184
DM		 1528 if ((high_bits & 0xfffffc00) != 0)
1529 {
9bb3323d 1530 emit_insn (gen_safe_HIGH64 (temp, high_bits));
e0d80184 1531 if ((high_bits & ~0xfffffc00) != 0)
9208e4b2
DM		 1532 emit_insn (gen_rtx_SET (VOIDmode, op0,
1533 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
61a55e8b 1534 else
e0d80184 1535 temp2 = temp;
61a55e8b
DE		 1536 }
1537 else
1538 {
f710f868 1539 emit_insn (gen_safe_SET64 (temp, high_bits));
e0d80184
DM		 1540 temp2 = temp;
1541 }
61a55e8b 1542
80ffc95e 1543 /* Now shift it up into place. */
9208e4b2 1544 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1545 gen_rtx_ASHIFT (DImode, temp2,
1546 GEN_INT (shift_count))));
61a55e8b 1547
e0d80184
DM		 1548 /* If there is a low immediate part piece, finish up by
1549 putting that in as well. */
1550 if (low_immediate != 0)
9208e4b2
DM		 1551 emit_insn (gen_rtx_SET (VOIDmode, op0,
1552 gen_safe_OR64 (op0, low_immediate)));
ab835497
RK		 1553}
1554
e80d5f80
KG		 1555static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1556 unsigned HOST_WIDE_INT);
2a01c939 1557
e0d80184
DM		 1558/* Full 64-bit constant decomposition. Even though this is the
1559 'worst' case, we still optimize a few things away. */
1560static void
fc27d102
KG		 1561sparc_emit_set_const64_longway (rtx op0, rtx temp,
1562 unsigned HOST_WIDE_INT high_bits,
1563 unsigned HOST_WIDE_INT low_bits)
ab835497 1564{
e0d80184 1565 rtx sub_temp;
4bf7135b 1566
e0d80184
DM		 1567 if (reload_in_progress || reload_completed)
1568 sub_temp = op0;
1569 else
1570 sub_temp = gen_reg_rtx (DImode);
1571
1572 if ((high_bits & 0xfffffc00) != 0)
1573 {
9bb3323d 1574 emit_insn (gen_safe_HIGH64 (temp, high_bits));
e0d80184 1575 if ((high_bits & ~0xfffffc00) != 0)
9208e4b2 1576 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1577 sub_temp,
9208e4b2 1578 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
e0d80184
DM		 1579 else
1580 sub_temp = temp;
1581 }
1582 else
ab835497 1583 {
f710f868 1584 emit_insn (gen_safe_SET64 (temp, high_bits));
e0d80184 1585 sub_temp = temp;
ab835497 1586 }
4bf7135b 1587
e0d80184 1588 if (!reload_in_progress && !reload_completed)
284d86e9 1589 {
e0d80184
DM		 1590 rtx temp2 = gen_reg_rtx (DImode);
1591 rtx temp3 = gen_reg_rtx (DImode);
1592 rtx temp4 = gen_reg_rtx (DImode);
284d86e9 1593
9208e4b2 1594 emit_insn (gen_rtx_SET (VOIDmode, temp4,
e0d80184
DM		 1595 gen_rtx_ASHIFT (DImode, sub_temp,
1596 GEN_INT (32))));
4bf7135b 1597
9bb3323d 1598 emit_insn (gen_safe_HIGH64 (temp2, low_bits));
e0d80184 1599 if ((low_bits & ~0xfffffc00) != 0)
f710f868
DM		 1600 {
1601 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1602 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1603 emit_insn (gen_rtx_SET (VOIDmode, op0,
1604 gen_rtx_PLUS (DImode, temp4, temp3)));
1605 }
1606 else
1607 {
1608 emit_insn (gen_rtx_SET (VOIDmode, op0,
1609 gen_rtx_PLUS (DImode, temp4, temp2)));
1610 }
284d86e9 1611 }
e0d80184
DM		 1612 else
1613 {
9208e4b2
DM		 1614 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1615 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1616 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
e0d80184 1617 int to_shift = 12;
284d86e9 1618
e0d80184
DM		 1619 /* We are in the middle of reload, so this is really
1620 painful. However we do still make an attempt to
5108f3e5 1621 avoid emitting truly stupid code. */
e0d80184
DM		 1622 if (low1 != const0_rtx)
1623 {
9208e4b2 1624 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184 1625 gen_rtx_ASHIFT (DImode, sub_temp,
2a01c939 1626 GEN_INT (to_shift))));
9208e4b2 1627 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1628 gen_rtx_IOR (DImode, op0, low1)));
1629 sub_temp = op0;
1630 to_shift = 12;
1631 }
1632 else
1633 {
1634 to_shift += 12;
1635 }
1636 if (low2 != const0_rtx)
1637 {
9208e4b2 1638 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1639 gen_rtx_ASHIFT (DImode, sub_temp,
1640 GEN_INT (to_shift))));
9208e4b2 1641 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1642 gen_rtx_IOR (DImode, op0, low2)));
1643 sub_temp = op0;
1644 to_shift = 8;
1645 }
1646 else
1647 {
1648 to_shift += 8;
1649 }
9208e4b2 1650 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1651 gen_rtx_ASHIFT (DImode, sub_temp,
1652 GEN_INT (to_shift))));
1653 if (low3 != const0_rtx)
9208e4b2 1654 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184 1655 gen_rtx_IOR (DImode, op0, low3)));
80ffc95e 1656 /* phew... */
e0d80184 1657 }
284d86e9
JC		 1658}
1659
80ffc95e 1660/* Analyze a 64-bit constant for certain properties. */
e80d5f80
KG		 1661static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1662 unsigned HOST_WIDE_INT,
1663 int *, int *, int *);
2a01c939 1664
e0d80184 1665static void
fc27d102
KG		 1666analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1667 unsigned HOST_WIDE_INT low_bits,
1668 int *hbsp, int *lbsp, int *abbasp)
ab835497 1669{
e0d80184
DM		 1670 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1671 int i;
ab835497 1672
e0d80184
DM		 1673 lowest_bit_set = highest_bit_set = -1;
1674 i = 0;
1675 do
ab835497 1676 {
e0d80184
DM		 1677 if ((lowest_bit_set == -1)
1678 && ((low_bits >> i) & 1))
1679 lowest_bit_set = i;
1680 if ((highest_bit_set == -1)
1681 && ((high_bits >> (32 - i - 1)) & 1))
1682 highest_bit_set = (64 - i - 1);
1683 }
1684 while (++i < 32
1685 && ((highest_bit_set == -1)
1686 || (lowest_bit_set == -1)));
1687 if (i == 32)
1688 {
1689 i = 0;
1690 do
ab835497 1691 {
e0d80184
DM		 1692 if ((lowest_bit_set == -1)
1693 && ((high_bits >> i) & 1))
1694 lowest_bit_set = i + 32;
1695 if ((highest_bit_set == -1)
1696 && ((low_bits >> (32 - i - 1)) & 1))
1697 highest_bit_set = 32 - i - 1;
ab835497 1698 }
e0d80184
DM		 1699 while (++i < 32
1700 && ((highest_bit_set == -1)
1701 || (lowest_bit_set == -1)));
1702 }
1703 /* If there are no bits set this should have gone out
1704 as one instruction! */
f5f7d171 1705 gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1);
e0d80184
DM		 1706 all_bits_between_are_set = 1;
1707 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1708 {
1709 if (i < 32)
1710 {
1711 if ((low_bits & (1 << i)) != 0)
1712 continue;
1713 }
1714 else
1715 {
1716 if ((high_bits & (1 << (i - 32))) != 0)
1717 continue;
1718 }
1719 all_bits_between_are_set = 0;
1720 break;
ab835497 1721 }
e0d80184
DM		 1722 *hbsp = highest_bit_set;
1723 *lbsp = lowest_bit_set;
1724 *abbasp = all_bits_between_are_set;
ab835497 1725}
6a4bb1fa 1726
e80d5f80 1727static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
2a01c939 1728
e0d80184 1729static int
fc27d102
KG		 1730const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1731 unsigned HOST_WIDE_INT low_bits)
e0d80184
DM		 1732{
1733 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
284d86e9 1734
e0d80184 1735 if (high_bits == 0
f451b552 1736 || high_bits == 0xffffffff)
e0d80184 1737 return 1;
6a4bb1fa 1738
e0d80184
DM		 1739 analyze_64bit_constant (high_bits, low_bits,
1740 &highest_bit_set, &lowest_bit_set,
1741 &all_bits_between_are_set);
6a4bb1fa 1742
f710f868
DM		 1743 if ((highest_bit_set == 63
1744 || lowest_bit_set == 0)
e0d80184
DM		 1745 && all_bits_between_are_set != 0)
1746 return 1;
6a4bb1fa 1747
9208e4b2
DM		 1748 if ((highest_bit_set - lowest_bit_set) < 21)
1749 return 1;
1750
6a4bb1fa
DE		 1751 return 0;
1752}
1753
e80d5f80
KG		 1754static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1755 unsigned HOST_WIDE_INT,
1756 int, int);
2a01c939
DM		 1757
1758static unsigned HOST_WIDE_INT
fc27d102
KG		 1759create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1760 unsigned HOST_WIDE_INT low_bits,
1761 int lowest_bit_set, int shift)
ab835497 1762{
f710f868 1763 HOST_WIDE_INT hi, lo;
ab835497 1764
e0d80184
DM		 1765 if (lowest_bit_set < 32)
1766 {
1767 lo = (low_bits >> lowest_bit_set) << shift;
1768 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1769 }
1770 else
1771 {
1772 lo = 0;
1773 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1774 }
f5f7d171 1775 gcc_assert (! (hi & lo));
e0d80184
DM		 1776 return (hi | lo);
1777}
ab835497 1778
e0d80184
DM		 1779/* Here we are sure to be arch64 and this is an integer constant
1780 being loaded into a register. Emit the most efficient
1781 insn sequence possible. Detection of all the 1-insn cases
1782 has been done already. */
d9816849 1783static void
fc27d102 1784sparc_emit_set_const64 (rtx op0, rtx op1)
e0d80184 1785{
2a01c939 1786 unsigned HOST_WIDE_INT high_bits, low_bits;
e0d80184
DM		 1787 int lowest_bit_set, highest_bit_set;
1788 int all_bits_between_are_set;
1d511ed5 1789 rtx temp = 0;
ab835497 1790
e0d80184 1791 /* Sanity check that we know what we are working with. */
bea5071f
EB		 1792 gcc_assert (TARGET_ARCH64
1793 && (GET_CODE (op0) == SUBREG
1794 || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));
380f6ad3 1795
f710f868
DM		 1796 if (reload_in_progress || reload_completed)
1797 temp = op0;
f710f868 1798
0e5d569c 1799 if (GET_CODE (op1) != CONST_INT)
e0d80184 1800 {
5f78aa30
JC		 1801 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1802 return;
e0d80184 1803 }
ab835497 1804
1d511ed5
EB		 1805 if (! temp)
1806 temp = gen_reg_rtx (DImode);
1807
0e5d569c
EB		 1808 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1809 low_bits = (INTVAL (op1) & 0xffffffff);
ab835497 1810
e0d80184
DM		 1811 /* low_bits bits 0 --> 31
1812 high_bits bits 32 --> 63 */
ab835497 1813
e0d80184
DM		 1814 analyze_64bit_constant (high_bits, low_bits,
1815 &highest_bit_set, &lowest_bit_set,
1816 &all_bits_between_are_set);
1817
1818 /* First try for a 2-insn sequence. */
1819
1820 /* These situations are preferred because the optimizer can
1821 * do more things with them:
1822 * 1) mov -1, %reg
1823 * sllx %reg, shift, %reg
1824 * 2) mov -1, %reg
1825 * srlx %reg, shift, %reg
1826 * 3) mov some_small_const, %reg
1827 * sllx %reg, shift, %reg
1828 */
1829 if (((highest_bit_set == 63
1830 || lowest_bit_set == 0)
1831 && all_bits_between_are_set != 0)
2a01c939 1832 || ((highest_bit_set - lowest_bit_set) < 12))
e0d80184 1833 {
9208e4b2 1834 HOST_WIDE_INT the_const = -1;
e0d80184
DM		 1835 int shift = lowest_bit_set;
1836
f710f868
DM		 1837 if ((highest_bit_set != 63
1838 && lowest_bit_set != 0)
1839 || all_bits_between_are_set == 0)
ab835497 1840 {
e0d80184 1841 the_const =
9208e4b2 1842 create_simple_focus_bits (high_bits, low_bits,
9208e4b2 1843 lowest_bit_set, 0);
ab835497 1844 }
e0d80184 1845 else if (lowest_bit_set == 0)
9208e4b2 1846 shift = -(63 - highest_bit_set);
e0d80184 1847
f5f7d171
JM		 1848 gcc_assert (SPARC_SIMM13_P (the_const));
1849 gcc_assert (shift != 0);
f710f868 1850
9208e4b2 1851 emit_insn (gen_safe_SET64 (temp, the_const));
e0d80184 1852 if (shift > 0)
9208e4b2 1853 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184
DM		 1854 op0,
1855 gen_rtx_ASHIFT (DImode,
1856 temp,
1857 GEN_INT (shift))));
1858 else if (shift < 0)
9208e4b2 1859 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1860 op0,
9208e4b2 1861 gen_rtx_LSHIFTRT (DImode,
e0d80184
DM		 1862 temp,
1863 GEN_INT (-shift))));
e0d80184
DM		 1864 return;
1865 }
ab835497 1866
e0d80184
DM		 1867 /* Now a range of 22 or less bits set somewhere.
1868 * 1) sethi %hi(focus_bits), %reg
1869 * sllx %reg, shift, %reg
1870 * 2) sethi %hi(focus_bits), %reg
1871 * srlx %reg, shift, %reg
1872 */
2a01c939 1873 if ((highest_bit_set - lowest_bit_set) < 21)
e0d80184 1874 {
2a01c939 1875 unsigned HOST_WIDE_INT focus_bits =
e0d80184 1876 create_simple_focus_bits (high_bits, low_bits,
ddf80874 1877 lowest_bit_set, 10);
f710f868 1878
f5f7d171
JM		 1879 gcc_assert (SPARC_SETHI_P (focus_bits));
1880 gcc_assert (lowest_bit_set != 10);
f710f868 1881
9bb3323d 1882 emit_insn (gen_safe_HIGH64 (temp, focus_bits));
e0d80184 1883
9208e4b2 1884 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
e0d80184 1885 if (lowest_bit_set < 10)
9208e4b2 1886 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1887 op0,
9208e4b2 1888 gen_rtx_LSHIFTRT (DImode, temp,
e0d80184 1889 GEN_INT (10 - lowest_bit_set))));
9208e4b2
DM		 1890 else if (lowest_bit_set > 10)
1891 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184
DM		 1892 op0,
1893 gen_rtx_ASHIFT (DImode, temp,
1894 GEN_INT (lowest_bit_set - 10))));
e0d80184
DM		 1895 return;
1896 }
1897
1898 /* 1) sethi %hi(low_bits), %reg
1899 * or %reg, %lo(low_bits), %reg
1900 * 2) sethi %hi(~low_bits), %reg
1901 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1902 */
1903 if (high_bits == 0
2a01c939 1904 || high_bits == 0xffffffff)
5f78aa30
JC		 1905 {
1906 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1907 (high_bits == 0xffffffff));
1908 return;
1909 }
e0d80184 1910
f710f868
DM		 1911 /* Now, try 3-insn sequences. */
1912
e0d80184
DM		 1913 /* 1) sethi %hi(high_bits), %reg
1914 * or %reg, %lo(high_bits), %reg
1915 * sllx %reg, 32, %reg
1916 */
f710f868 1917 if (low_bits == 0)
5f78aa30 1918 {
f710f868 1919 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
5f78aa30
JC		 1920 return;
1921 }
e0d80184 1922
f710f868
DM		 1923 /* We may be able to do something quick
1924 when the constant is negated, so try that. */
e0d80184
DM		 1925 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1926 (~low_bits) & 0xfffffc00))
1927 {
5108f3e5
DM		 1928 /* NOTE: The trailing bits get XOR'd so we need the
1929 non-negated bits, not the negated ones. */
1930 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
e0d80184
DM		 1931
1932 if ((((~high_bits) & 0xffffffff) == 0
1933 && ((~low_bits) & 0x80000000) == 0)
1934 || (((~high_bits) & 0xffffffff) == 0xffffffff
1935 && ((~low_bits) & 0x80000000) != 0))
ab835497 1936 {
0e5d569c 1937 unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff);
e0d80184 1938
5108f3e5
DM		 1939 if ((SPARC_SETHI_P (fast_int)
1940 && (~high_bits & 0xffffffff) == 0)
1941 || SPARC_SIMM13_P (fast_int))
9208e4b2 1942 emit_insn (gen_safe_SET64 (temp, fast_int));
ab835497 1943 else
0e5d569c 1944 sparc_emit_set_const64 (temp, GEN_INT (fast_int));
ab835497 1945 }
e0d80184
DM		 1946 else
1947 {
1948 rtx negated_const;
e0d80184
DM		 1949 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
1950 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
e0d80184
DM		 1951 sparc_emit_set_const64 (temp, negated_const);
1952 }
5108f3e5
DM		 1953
1954 /* If we are XOR'ing with -1, then we should emit a one's complement
1955 instead. This way the combiner will notice logical operations
1956 such as ANDN later on and substitute. */
1957 if (trailing_bits == 0x3ff)
1958 {
1959 emit_insn (gen_rtx_SET (VOIDmode, op0,
1960 gen_rtx_NOT (DImode, temp)));
1961 }
1962 else
1963 {
1964 emit_insn (gen_rtx_SET (VOIDmode,
1965 op0,
1966 gen_safe_XOR64 (temp,
1967 (-0x400 | trailing_bits))));
1968 }
e0d80184 1969 return;
ab835497 1970 }
ab835497 1971
e0d80184
DM		 1972 /* 1) sethi %hi(xxx), %reg
1973 * or %reg, %lo(xxx), %reg
1974 * sllx %reg, yyy, %reg
f710f868
DM		 1975 *
1976 * ??? This is just a generalized version of the low_bits==0
1977 * thing above, FIXME...
e0d80184
DM		 1978 */
1979 if ((highest_bit_set - lowest_bit_set) < 32)
1980 {
f710f868
DM		 1981 unsigned HOST_WIDE_INT focus_bits =
1982 create_simple_focus_bits (high_bits, low_bits,
ddf80874 1983 lowest_bit_set, 0);
ab835497 1984
e0d80184 1985 /* We can't get here in this state. */
f5f7d171 1986 gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32);
95726648 1987
e0d80184
DM		 1988 /* So what we know is that the set bits straddle the
1989 middle of the 64-bit word. */
5f78aa30
JC		 1990 sparc_emit_set_const64_quick2 (op0, temp,
1991 focus_bits, 0,
1992 lowest_bit_set);
1993 return;
e0d80184 1994 }
c85f7c16 1995
f710f868
DM		 1996 /* 1) sethi %hi(high_bits), %reg
1997 * or %reg, %lo(high_bits), %reg
1998 * sllx %reg, 32, %reg
1999 * or %reg, low_bits, %reg
2000 */
2001 if (SPARC_SIMM13_P(low_bits)
2002 && ((int)low_bits > 0))
2003 {
2004 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2005 return;
2006 }
2007
80ffc95e 2008 /* The easiest way when all else fails, is full decomposition. */
e0d80184 2009 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
c85f7c16 2010}
0e5d569c 2011#endif /* HOST_BITS_PER_WIDE_INT == 32 */
c85f7c16 2012
e267e177
RH		 2013/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2014 return the mode to be used for the comparison. For floating-point,
2015 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2016 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2017 processing is needed. */
2018
2019enum machine_mode
fc27d102 2020select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
e267e177
RH		 2021{
2022 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2023 {
2024 switch (op)
2025 {
2026 case EQ:
2027 case NE:
2028 case UNORDERED:
2029 case ORDERED:
2030 case UNLT:
2031 case UNLE:
2032 case UNGT:
2033 case UNGE:
2034 case UNEQ:
7913f3d0 2035 case LTGT:
e267e177
RH		 2036 return CCFPmode;
2037
2038 case LT:
2039 case LE:
2040 case GT:
2041 case GE:
2042 return CCFPEmode;
2043
2044 default:
f5f7d171 2045 gcc_unreachable ();
e267e177
RH		 2046 }
2047 }
2048 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2049 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2050 {
2051 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2052 return CCX_NOOVmode;
2053 else
2054 return CC_NOOVmode;
2055 }
2056 else
2057 {
2058 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2059 return CCXmode;
2060 else
2061 return CCmode;
2062 }
2063}
2064
f90b7a5a
PB		 2065/* Emit the compare insn and return the CC reg for a CODE comparison
2066 with operands X and Y. */
c85f7c16 2067
f90b7a5a
PB		 2068static rtx
2069gen_compare_reg_1 (enum rtx_code code, rtx x, rtx y)
c85f7c16 2070{
65c5ae8b 2071 enum machine_mode mode;
f90b7a5a 2072 rtx cc_reg;
c85f7c16 2073
f90b7a5a
PB		 2074 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
2075 return x;
65c5ae8b 2076
65c5ae8b 2077 mode = SELECT_CC_MODE (code, x, y);
8ec11fe9 2078
e0d80184
DM		 2079 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2080 fcc regs (cse can't tell they're really call clobbered regs and will
2081 remove a duplicate comparison even if there is an intervening function
2082 call - it will then try to reload the cc reg via an int reg which is why
2083 we need the movcc patterns). It is possible to provide the movcc
2084 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2085 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2086 to tell cse that CCFPE mode registers (even pseudos) are call
2087 clobbered. */
c85f7c16 2088
e0d80184
DM		 2089 /* ??? This is an experiment. Rather than making changes to cse which may
2090 or may not be easy/clean, we do our own cse. This is possible because
2091 we will generate hard registers. Cse knows they're call clobbered (it
2092 doesn't know the same thing about pseudos). If we guess wrong, no big
2093 deal, but if we win, great! */
c85f7c16 2094
e0d80184
DM		 2095 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2096#if 1 /* experiment */
284d86e9 2097 {
e0d80184
DM		 2098 int reg;
2099 /* We cycle through the registers to ensure they're all exercised. */
2100 static int next_fcc_reg = 0;
2101 /* Previous x,y for each fcc reg. */
2102 static rtx prev_args[4][2];
284d86e9 2103
e0d80184
DM		 2104 /* Scan prev_args for x,y. */
2105 for (reg = 0; reg < 4; reg++)
2106 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2107 break;
2108 if (reg == 4)
2109 {
2110 reg = next_fcc_reg;
2111 prev_args[reg][0] = x;
2112 prev_args[reg][1] = y;
2113 next_fcc_reg = (next_fcc_reg + 1) & 3;
2114 }
2115 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
284d86e9 2116 }
e0d80184
DM		 2117#else
2118 cc_reg = gen_reg_rtx (mode);
2119#endif /* ! experiment */
2120 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2121 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2122 else
2123 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
284d86e9 2124
19047e4a
EB		 2125 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2126 will only result in an unrecognizable insn so no point in asserting. */
2127 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y)));
c85f7c16 2128
e0d80184
DM		 2129 return cc_reg;
2130}
c85f7c16 2131
f90b7a5a
PB		 2132
2133/* Emit the compare insn and return the CC reg for the comparison in CMP. */
19047e4a
EB		 2134
2135rtx
f90b7a5a 2136gen_compare_reg (rtx cmp)
19047e4a 2137{
f90b7a5a 2138 return gen_compare_reg_1 (GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1));
19047e4a
EB		 2139}
2140
e0d80184 2141/* This function is used for v9 only.
f90b7a5a 2142 DEST is the target of the Scc insn.
e0d80184 2143 CODE is the code for an Scc's comparison.
f90b7a5a 2144 X and Y are the values we compare.
c85f7c16 2145
e0d80184 2146 This function is needed to turn
ab835497 2147
e0d80184
DM		 2148 (set (reg:SI 110)
2149 (gt (reg:CCX 100 %icc)
2150 (const_int 0)))
2151 into
2152 (set (reg:SI 110)
2153 (gt:DI (reg:CCX 100 %icc)
2154 (const_int 0)))
2155
2156 IE: The instruction recognizer needs to see the mode of the comparison to
2157 find the right instruction. We could use "gt:DI" right in the
f90b7a5a 2158 define_expand, but leaving it out allows us to handle DI, SI, etc. */
ab835497 2159
f90b7a5a
PB		 2160static int
2161gen_v9_scc (rtx dest, enum rtx_code compare_code, rtx x, rtx y)
ab835497 2162{
e0d80184 2163 if (! TARGET_ARCH64
f90b7a5a
PB		 2164 && (GET_MODE (x) == DImode
2165 || GET_MODE (dest) == DImode))
e0d80184 2166 return 0;
7e2feebf 2167
e0d80184
DM		 2168 /* Try to use the movrCC insns. */
2169 if (TARGET_ARCH64
f90b7a5a
PB		 2170 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT
2171 && y == const0_rtx
e0d80184 2172 && v9_regcmp_p (compare_code))
ab835497 2173 {
f90b7a5a 2174 rtx op0 = x;
7e04157d
DM		 2175 rtx temp;
2176
e0d80184 2177 /* Special case for op0 != 0. This can be done with one instruction if
f90b7a5a 2178 dest == x. */
e0d80184
DM		 2179
2180 if (compare_code == NE
f90b7a5a
PB		 2181 && GET_MODE (dest) == DImode
2182 && rtx_equal_p (op0, dest))
ab835497 2183 {
f90b7a5a 2184 emit_insn (gen_rtx_SET (VOIDmode, dest,
e0d80184
DM		 2185 gen_rtx_IF_THEN_ELSE (DImode,
2186 gen_rtx_fmt_ee (compare_code, DImode,
2187 op0, const0_rtx),
2188 const1_rtx,
f90b7a5a 2189 dest)));
ab835497
RK		 2190 return 1;
2191 }
e0d80184 2192
f90b7a5a 2193 if (reg_overlap_mentioned_p (dest, op0))
a42519be 2194 {
f90b7a5a 2195 /* Handle the case where dest == x.
a42519be 2196 We "early clobber" the result. */
f90b7a5a
PB		 2197 op0 = gen_reg_rtx (GET_MODE (x));
2198 emit_move_insn (op0, x);
a42519be
JJ		 2199 }
2200
f90b7a5a 2201 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
e0d80184 2202 if (GET_MODE (op0) != DImode)
ab835497 2203 {
e0d80184
DM		 2204 temp = gen_reg_rtx (DImode);
2205 convert_move (temp, op0, 0);
ab835497 2206 }
e0d80184
DM		 2207 else
2208 temp = op0;
f90b7a5a
PB		 2209 emit_insn (gen_rtx_SET (VOIDmode, dest,
2210 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
e0d80184
DM		 2211 gen_rtx_fmt_ee (compare_code, DImode,
2212 temp, const0_rtx),
2213 const1_rtx,
f90b7a5a 2214 dest)));
95726648
DE		 2215 return 1;
2216 }
e0d80184 2217 else
ab835497 2218 {
f90b7a5a
PB		 2219 x = gen_compare_reg_1 (compare_code, x, y);
2220 y = const0_rtx;
ab835497 2221
f90b7a5a
PB		 2222 gcc_assert (GET_MODE (x) != CC_NOOVmode
2223 && GET_MODE (x) != CCX_NOOVmode);
2224
2225 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
2226 emit_insn (gen_rtx_SET (VOIDmode, dest,
2227 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
e0d80184 2228 gen_rtx_fmt_ee (compare_code,
f90b7a5a
PB		 2229 GET_MODE (x), x, y),
2230 const1_rtx, dest)));
e0d80184 2231 return 1;
ab835497 2232 }
ab835497 2233}
4fb4e4b8 2234
f90b7a5a
PB		 2235
2236/* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2237 without jumps using the addx/subx instructions. */
2238
2239bool
2240emit_scc_insn (rtx operands[])
2241{
2242 rtx tem;
2243 rtx x;
2244 rtx y;
2245 enum rtx_code code;
2246
2247 /* The quad-word fp compare library routines all return nonzero to indicate
2248 true, which is different from the equivalent libgcc routines, so we must
2249 handle them specially here. */
2250 if (GET_MODE (operands[2]) == TFmode && ! TARGET_HARD_QUAD)
2251 {
2252 operands[1] = sparc_emit_float_lib_cmp (operands[2], operands[3],
2253 GET_CODE (operands[1]));
2254 operands[2] = XEXP (operands[1], 0);
2255 operands[3] = XEXP (operands[1], 1);
2256 }
2257
2258 code = GET_CODE (operands[1]);
2259 x = operands[2];
2260 y = operands[3];
2261
2262 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2263 more applications). The exception to this is "reg != 0" which can
2264 be done in one instruction on v9 (so we do it). */
2265 if (code == EQ)
2266 {
2267 if (GET_MODE (x) == SImode)
2268 {
2269 rtx pat = gen_seqsi_special (operands[0], x, y);
2270 emit_insn (pat);
2271 return true;
2272 }
2273 else if (GET_MODE (x) == DImode)
2274 {
2275 rtx pat = gen_seqdi_special (operands[0], x, y);
2276 emit_insn (pat);
2277 return true;
2278 }
2279 }
2280
2281 if (code == NE)
2282 {
2283 if (GET_MODE (x) == SImode)
2284 {
2285 rtx pat = gen_snesi_special (operands[0], x, y);
2286 emit_insn (pat);
2287 return true;
2288 }
2289 else if (GET_MODE (x) == DImode)
2290 {
2291 rtx pat = gen_snedi_special (operands[0], x, y);
2292 emit_insn (pat);
2293 return true;
2294 }
2295 }
2296
2297 /* For the rest, on v9 we can use conditional moves. */
2298
2299 if (TARGET_V9)
2300 {
2301 if (gen_v9_scc (operands[0], code, x, y))
2302 return true;
2303 }
2304
2305 /* We can do LTU and GEU using the addx/subx instructions too. And
2306 for GTU/LEU, if both operands are registers swap them and fall
2307 back to the easy case. */
2308 if (code == GTU || code == LEU)
2309 {
2310 if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2311 && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG))
2312 {
2313 tem = x;
2314 x = y;
2315 y = tem;
2316 code = swap_condition (code);
2317 }
2318 }
2319
2320 if (code == LTU || code == GEU)
2321 {
2322 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4900aa61 2323 gen_rtx_fmt_ee (code, SImode,
f90b7a5a
PB		 2324 gen_compare_reg_1 (code, x, y),
2325 const0_rtx)));
2326 return true;
2327 }
2328
2329 /* Nope, do branches. */
2330 return false;
2331}
2332
e0d80184
DM		 2333/* Emit a conditional jump insn for the v9 architecture using comparison code
2334 CODE and jump target LABEL.
2335 This function exists to take advantage of the v9 brxx insns. */
ab835497 2336
f90b7a5a 2337static void
fc27d102 2338emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
ab835497 2339{
e0d80184
DM		 2340 emit_jump_insn (gen_rtx_SET (VOIDmode,
2341 pc_rtx,
2342 gen_rtx_IF_THEN_ELSE (VOIDmode,
2343 gen_rtx_fmt_ee (code, GET_MODE (op0),
2344 op0, const0_rtx),
2345 gen_rtx_LABEL_REF (VOIDmode, label),
2346 pc_rtx)));
2347}
7b1ac798 2348
f90b7a5a
PB		 2349void
2350emit_conditional_branch_insn (rtx operands[])
2351{
2352 /* The quad-word fp compare library routines all return nonzero to indicate
2353 true, which is different from the equivalent libgcc routines, so we must
2354 handle them specially here. */
2355 if (GET_MODE (operands[1]) == TFmode && ! TARGET_HARD_QUAD)
2356 {
2357 operands[0] = sparc_emit_float_lib_cmp (operands[1], operands[2],
2358 GET_CODE (operands[0]));
2359 operands[1] = XEXP (operands[0], 0);
2360 operands[2] = XEXP (operands[0], 1);
2361 }
2362
2363 if (TARGET_ARCH64 && operands[2] == const0_rtx
2364 && GET_CODE (operands[1]) == REG
2365 && GET_MODE (operands[1]) == DImode)
2366 {
2367 emit_v9_brxx_insn (GET_CODE (operands[0]), operands[1], operands[3]);
2368 return;
2369 }
2370
2371 operands[1] = gen_compare_reg (operands[0]);
2372 operands[2] = const0_rtx;
2373 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]), VOIDmode,
2374 operands[1], operands[2]);
2375 emit_jump_insn (gen_cbranchcc4 (operands[0], operands[1], operands[2],
2376 operands[3]));
2377}
2378
2379
7b1ac798
JJ		 2380/* Generate a DFmode part of a hard TFmode register.
2381 REG is the TFmode hard register, LOW is 1 for the
2382 low 64bit of the register and 0 otherwise.
2383 */
2384rtx
fc27d102 2385gen_df_reg (rtx reg, int low)
7b1ac798
JJ		 2386{
2387 int regno = REGNO (reg);
2388
2389 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2aac41d6 2390 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
7b1ac798
JJ		 2391 return gen_rtx_REG (DFmode, regno);
2392}
e0d80184 2393\f
73985940
RH		 2394/* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2395 Unlike normal calls, TFmode operands are passed by reference. It is
2396 assumed that no more than 3 operands are required. */
2397
2398static void
fc27d102 2399emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
73985940
RH		 2400{
2401 rtx ret_slot = NULL, arg[3], func_sym;
4e7d5d27 2402 int i;
73985940
RH		 2403
2404 /* We only expect to be called for conversions, unary, and binary ops. */
f5f7d171 2405 gcc_assert (nargs == 2 || nargs == 3);
73985940
RH		 2406
2407 for (i = 0; i < nargs; ++i)
2408 {
2409 rtx this_arg = operands[i];
2410 rtx this_slot;
2411
2412 /* TFmode arguments and return values are passed by reference. */
2413 if (GET_MODE (this_arg) == TFmode)
2414 {
4e7d5d27
DM		 2415 int force_stack_temp;
2416
2417 force_stack_temp = 0;
2418 if (TARGET_BUGGY_QP_LIB && i == 0)
2419 force_stack_temp = 1;
2420
2421 if (GET_CODE (this_arg) == MEM
2422 && ! force_stack_temp)
2423 this_arg = XEXP (this_arg, 0);
2424 else if (CONSTANT_P (this_arg)
2425 && ! force_stack_temp)
73985940
RH		 2426 {
2427 this_slot = force_const_mem (TFmode, this_arg);
2428 this_arg = XEXP (this_slot, 0);
2429 }
2430 else
2431 {
2432 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2433
2434 /* Operand 0 is the return value. We'll copy it out later. */
2435 if (i > 0)
2436 emit_move_insn (this_slot, this_arg);
2437 else
2438 ret_slot = this_slot;
2439
2440 this_arg = XEXP (this_slot, 0);
2441 }
2442 }
2443
2444 arg[i] = this_arg;
2445 }
2446
2447 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2448
2449 if (GET_MODE (operands[0]) == TFmode)
2450 {
2451 if (nargs == 2)
2452 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2453 arg[0], GET_MODE (arg[0]),
2454 arg[1], GET_MODE (arg[1]));
2455 else
2456 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2457 arg[0], GET_MODE (arg[0]),
2458 arg[1], GET_MODE (arg[1]),
2459 arg[2], GET_MODE (arg[2]));
2460
2461 if (ret_slot)
2462 emit_move_insn (operands[0], ret_slot);
2463 }
2464 else
2465 {
2466 rtx ret;
2467
f5f7d171 2468 gcc_assert (nargs == 2);
73985940
RH		 2469
2470 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2471 GET_MODE (operands[0]), 1,
2472 arg[1], GET_MODE (arg[1]));
2473
2474 if (ret != operands[0])
2475 emit_move_insn (operands[0], ret);
2476 }
2477}
2478
2479/* Expand soft-float TFmode calls to sparc abi routines. */
2480
2481static void
fc27d102 2482emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
73985940
RH		 2483{
2484 const char *func;
2485
2486 switch (code)
2487 {
2488 case PLUS:
2489 func = "_Qp_add";
2490 break;
2491 case MINUS:
2492 func = "_Qp_sub";
2493 break;
2494 case MULT:
2495 func = "_Qp_mul";
2496 break;
2497 case DIV:
2498 func = "_Qp_div";
2499 break;
2500 default:
f5f7d171 2501 gcc_unreachable ();
73985940
RH		 2502 }
2503
2504 emit_soft_tfmode_libcall (func, 3, operands);
2505}
2506
2507static void
fc27d102 2508emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
73985940
RH		 2509{
2510 const char *func;
2511
f5f7d171
JM		 2512 gcc_assert (code == SQRT);
2513 func = "_Qp_sqrt";
73985940
RH		 2514
2515 emit_soft_tfmode_libcall (func, 2, operands);
2516}
2517
2518static void
fc27d102 2519emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
73985940
RH		 2520{
2521 const char *func;
2522
2523 switch (code)
2524 {
2525 case FLOAT_EXTEND:
2526 switch (GET_MODE (operands[1]))
2527 {
2528 case SFmode:
2529 func = "_Qp_stoq";
2530 break;
2531 case DFmode:
2532 func = "_Qp_dtoq";
2533 break;
2534 default:
f5f7d171 2535 gcc_unreachable ();
73985940
RH		 2536 }
2537 break;
2538
2539 case FLOAT_TRUNCATE:
2540 switch (GET_MODE (operands[0]))
2541 {
2542 case SFmode:
2543 func = "_Qp_qtos";
2544 break;
2545 case DFmode:
2546 func = "_Qp_qtod";
2547 break;
2548 default:
f5f7d171 2549 gcc_unreachable ();
73985940
RH		 2550 }
2551 break;
2552
2553 case FLOAT:
2554 switch (GET_MODE (operands[1]))
2555 {
2556 case SImode:
2557 func = "_Qp_itoq";
92693034
JM		 2558 if (TARGET_ARCH64)
2559 operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]);
73985940
RH		 2560 break;
2561 case DImode:
2562 func = "_Qp_xtoq";
2563 break;
2564 default:
f5f7d171 2565 gcc_unreachable ();
73985940
RH		 2566 }
2567 break;
2568
2569 case UNSIGNED_FLOAT:
2570 switch (GET_MODE (operands[1]))
2571 {
2572 case SImode:
2573 func = "_Qp_uitoq";
92693034
JM		 2574 if (TARGET_ARCH64)
2575 operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
73985940
RH		 2576 break;
2577 case DImode:
2578 func = "_Qp_uxtoq";
2579 break;
2580 default:
f5f7d171 2581 gcc_unreachable ();
73985940
RH		 2582 }
2583 break;
2584
2585 case FIX:
2586 switch (GET_MODE (operands[0]))
2587 {
2588 case SImode:
2589 func = "_Qp_qtoi";
2590 break;
2591 case DImode:
2592 func = "_Qp_qtox";
2593 break;
2594 default:
f5f7d171 2595 gcc_unreachable ();
73985940
RH		 2596 }
2597 break;
2598
2599 case UNSIGNED_FIX:
2600 switch (GET_MODE (operands[0]))
2601 {
2602 case SImode:
2603 func = "_Qp_qtoui";
2604 break;
2605 case DImode:
2606 func = "_Qp_qtoux";
2607 break;
2608 default:
f5f7d171 2609 gcc_unreachable ();
73985940
RH		 2610 }
2611 break;
2612
2613 default:
f5f7d171 2614 gcc_unreachable ();
73985940
RH		 2615 }
2616
2617 emit_soft_tfmode_libcall (func, 2, operands);
2618}
2619
2620/* Expand a hard-float tfmode operation. All arguments must be in
2621 registers. */
2622
2623static void
fc27d102 2624emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
73985940
RH		 2625{
2626 rtx op, dest;
2627
ec8e098d 2628 if (GET_RTX_CLASS (code) == RTX_UNARY)
73985940
RH		 2629 {
2630 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2631 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2632 }
2633 else
2634 {
2635 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2636 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2637 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2638 operands[1], operands[2]);
2639 }
2640
2641 if (register_operand (operands[0], VOIDmode))
2642 dest = operands[0];
2643 else
2644 dest = gen_reg_rtx (GET_MODE (operands[0]));
2645
2646 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2647
2648 if (dest != operands[0])
2649 emit_move_insn (operands[0], dest);
2650}
2651
2652void
fc27d102 2653emit_tfmode_binop (enum rtx_code code, rtx *operands)
73985940
RH		 2654{
2655 if (TARGET_HARD_QUAD)
2656 emit_hard_tfmode_operation (code, operands);
2657 else
2658 emit_soft_tfmode_binop (code, operands);
2659}
2660
2661void
fc27d102 2662emit_tfmode_unop (enum rtx_code code, rtx *operands)
73985940
RH		 2663{
2664 if (TARGET_HARD_QUAD)
2665 emit_hard_tfmode_operation (code, operands);
2666 else
2667 emit_soft_tfmode_unop (code, operands);
2668}
2669
2670void
fc27d102 2671emit_tfmode_cvt (enum rtx_code code, rtx *operands)
73985940
RH		 2672{
2673 if (TARGET_HARD_QUAD)
2674 emit_hard_tfmode_operation (code, operands);
2675 else
2676 emit_soft_tfmode_cvt (code, operands);
2677}
2678\f
f17f9332
JJ		 2679/* Return nonzero if a branch/jump/call instruction will be emitting
2680 nop into its delay slot. */
2681
2682int
fc27d102 2683empty_delay_slot (rtx insn)
f17f9332
JJ		 2684{
2685 rtx seq;
2686
2687 /* If no previous instruction (should not happen), return true. */
2688 if (PREV_INSN (insn) == NULL)
2689 return 1;
2690
2691 seq = NEXT_INSN (PREV_INSN (insn));
2692 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2693 return 0;
2694
2695 return 1;
2696}
2697
9ac617d4 2698/* Return nonzero if TRIAL can go into the call delay slot. */
ab835497 2699
e0d80184 2700int
9ac617d4 2701tls_call_delay (rtx trial)
e0d80184 2702{
e10fbf96 2703 rtx pat;
1150a841 2704
9ac617d4 2705 /* Binutils allows
e10fbf96
EB		 2706 call __tls_get_addr, %tgd_call (foo)
2707 add %l7, %o0, %o0, %tgd_add (foo)
9ac617d4
EB		 2708 while Sun as/ld does not. */
2709 if (TARGET_GNU_TLS || !TARGET_TLS)
2710 return 1;
4fb4e4b8 2711
e0d80184 2712 pat = PATTERN (trial);
795068a4 2713
e10fbf96
EB		 2714 /* We must reject tgd_add{32|64}, i.e.
2715 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2716 and tldm_add{32|64}, i.e.
2717 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2718 for Sun as/ld. */
2719 if (GET_CODE (pat) == SET
2720 && GET_CODE (SET_SRC (pat)) == PLUS)
2721 {
2722 rtx unspec = XEXP (SET_SRC (pat), 1);
795068a4 2723
e10fbf96
EB		 2724 if (GET_CODE (unspec) == UNSPEC
2725 && (XINT (unspec, 1) == UNSPEC_TLSGD
2726 || XINT (unspec, 1) == UNSPEC_TLSLDM))
2727 return 0;
2728 }
2729
2730 return 1;
9ac617d4
EB		 2731}
2732
2733/* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2734 instruction. RETURN_P is true if the v9 variant 'return' is to be
2735 considered in the test too.
c137830f 2736
9ac617d4
EB		 2737 TRIAL must be a SET whose destination is a REG appropriate for the
2738 'restore' instruction or, if RETURN_P is true, for the 'return'
2739 instruction. */
795068a4 2740
9ac617d4
EB		 2741static int
2742eligible_for_restore_insn (rtx trial, bool return_p)
2743{
2744 rtx pat = PATTERN (trial);
2745 rtx src = SET_SRC (pat);
795068a4 2746
9ac617d4 2747 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3ec6f1a9
RK		 2748 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2749 && arith_operand (src, GET_MODE (src)))
3c6088d2
JJ		 2750 {
2751 if (TARGET_ARCH64)
2752 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2753 else
2754 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2755 }
e48addee 2756
9ac617d4 2757 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3ec6f1a9
RK		 2758 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2759 && arith_double_operand (src, GET_MODE (src)))
e0d80184 2760 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
795068a4 2761
9ac617d4
EB		 2762 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2763 else if (! TARGET_FPU && register_operand (src, SFmode))
2764 return 1;
2765
2766 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2767 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
e0d80184 2768 return 1;
f5da225e 2769
9ac617d4 2770 /* If we have the 'return' instruction, anything that does not use
e48addee 2771 local or output registers and can go into a delay slot wins. */
b11b0904
EB		 2772 else if (return_p
2773 && TARGET_V9
2774 && !epilogue_renumber (&pat, 1)
2775 && get_attr_in_uncond_branch_delay (trial)
2776 == IN_UNCOND_BRANCH_DELAY_TRUE)
e48addee
JJ		 2777 return 1;
2778
9ac617d4 2779 /* The 'restore src1,src2,dest' pattern for SImode. */
e0d80184 2780 else if (GET_CODE (src) == PLUS
9ac617d4
EB		 2781 && register_operand (XEXP (src, 0), SImode)
2782 && arith_operand (XEXP (src, 1), SImode))
e0d80184
DM		 2783 return 1;
2784
9ac617d4 2785 /* The 'restore src1,src2,dest' pattern for DImode. */
e0d80184 2786 else if (GET_CODE (src) == PLUS
9ac617d4
EB		 2787 && register_operand (XEXP (src, 0), DImode)
2788 && arith_double_operand (XEXP (src, 1), DImode))
795068a4 2789 return 1;
795068a4 2790
9ac617d4 2791 /* The 'restore src1,%lo(src2),dest' pattern. */
e48addee
JJ		 2792 else if (GET_CODE (src) == LO_SUM
2793 && ! TARGET_CM_MEDMID
2794 && ((register_operand (XEXP (src, 0), SImode)
2795 && immediate_operand (XEXP (src, 1), SImode))
2796 || (TARGET_ARCH64
2797 && register_operand (XEXP (src, 0), DImode)
2798 && immediate_operand (XEXP (src, 1), DImode))))
2799 return 1;
2800
9ac617d4 2801 /* The 'restore src,src,dest' pattern. */
e48addee
JJ		 2802 else if (GET_CODE (src) == ASHIFT
2803 && (register_operand (XEXP (src, 0), SImode)
2804 || register_operand (XEXP (src, 0), DImode))
2805 && XEXP (src, 1) == const1_rtx)
2806 return 1;
2807
795068a4
JW		 2808 return 0;
2809}
2810
b11b0904 2811/* Return nonzero if TRIAL can go into the function return's delay slot. */
9ac617d4 2812
5751a10b 2813int
9ac617d4 2814eligible_for_return_delay (rtx trial)
5751a10b 2815{
9ac617d4 2816 rtx pat;
5751a10b 2817
9ac617d4
EB		 2818 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2819 return 0;
2820
2821 if (get_attr_length (trial) != 1)
2822 return 0;
2823
9ac617d4
EB		 2824 /* If the function uses __builtin_eh_return, the eh_return machinery
2825 occupies the delay slot. */
e3b5732b 2826 if (crtl->calls_eh_return)
9ac617d4
EB		 2827 return 0;
2828
b11b0904
EB		 2829 /* In the case of a leaf or flat function, anything can go into the slot. */
2830 if (sparc_leaf_function_p || TARGET_FLAT)
2831 return
2832 get_attr_in_uncond_branch_delay (trial) == IN_UNCOND_BRANCH_DELAY_TRUE;
5751a10b
JJ		 2833
2834 pat = PATTERN (trial);
5751a10b 2835
9ac617d4
EB		 2836 /* Otherwise, only operations which can be done in tandem with
2837 a `restore' or `return' insn can go into the delay slot. */
2838 if (GET_CODE (SET_DEST (pat)) != REG
2839 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
2840 return 0;
5751a10b 2841
9ac617d4
EB		 2842 /* If this instruction sets up floating point register and we have a return
2843 instruction, it can probably go in. But restore will not work
2844 with FP_REGS. */
2845 if (REGNO (SET_DEST (pat)) >= 32)
2846 return (TARGET_V9
b11b0904
EB		 2847 && !epilogue_renumber (&pat, 1)
2848 && get_attr_in_uncond_branch_delay (trial)
2849 == IN_UNCOND_BRANCH_DELAY_TRUE);
9ac617d4
EB		 2850
2851 return eligible_for_restore_insn (trial, true);
5751a10b
JJ		 2852}
2853
b11b0904 2854/* Return nonzero if TRIAL can go into the sibling call's delay slot. */
7d167afd
JJ		 2855
2856int
fc27d102 2857eligible_for_sibcall_delay (rtx trial)
7d167afd 2858{
9ac617d4 2859 rtx pat;
7d167afd
JJ		 2860
2861 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2862 return 0;
2863
8456b95a 2864 if (get_attr_length (trial) != 1)
7d167afd
JJ		 2865 return 0;
2866
2867 pat = PATTERN (trial);
2868
b11b0904 2869 if (sparc_leaf_function_p || TARGET_FLAT)
7d167afd
JJ		 2870 {
2871 /* If the tail call is done using the call instruction,
2872 we have to restore %o7 in the delay slot. */
6244b14e 2873 if (LEAF_SIBCALL_SLOT_RESERVED_P)
7d167afd
JJ		 2874 return 0;
2875
2876 /* %g1 is used to build the function address */
2877 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2878 return 0;
2879
2880 return 1;
2881 }
2882
2883 /* Otherwise, only operations which can be done in tandem with
2884 a `restore' insn can go into the delay slot. */
2885 if (GET_CODE (SET_DEST (pat)) != REG
9ac617d4 2886 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
7d167afd
JJ		 2887 || REGNO (SET_DEST (pat)) >= 32)
2888 return 0;
2889
2890 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2891 in most cases. */
2892 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2893 return 0;
2894
9ac617d4 2895 return eligible_for_restore_insn (trial, false);
e0d80184 2896}
ab835497 2897
e0d80184 2898int
fc27d102 2899short_branch (int uid1, int uid2)
e0d80184 2900{
9d98a694 2901 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
77b91512
RK		 2902
2903 /* Leave a few words of "slop". */
2904 if (delta >= -1023 && delta <= 1022)
e0d80184 2905 return 1;
77b91512 2906
e0d80184
DM		 2907 return 0;
2908}
ab835497 2909
5e7a8ee0 2910/* Return nonzero if REG is not used after INSN.
e0d80184
DM		 2911 We assume REG is a reload reg, and therefore does
2912 not live past labels or calls or jumps. */
2913int
fc27d102 2914reg_unused_after (rtx reg, rtx insn)
e0d80184
DM		 2915{
2916 enum rtx_code code, prev_code = UNKNOWN;
ab835497 2917
e0d80184 2918 while ((insn = NEXT_INSN (insn)))
61a55e8b 2919 {
e0d80184
DM		 2920 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2921 return 1;
ab835497 2922
e0d80184
DM		 2923 code = GET_CODE (insn);
2924 if (GET_CODE (insn) == CODE_LABEL)
2925 return 1;
bc961ed7 2926
ec8e098d 2927 if (INSN_P (insn))
61a55e8b 2928 {
e0d80184
DM		 2929 rtx set = single_set (insn);
2930 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2931 if (set && in_src)
2932 return 0;
2933 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2934 return 1;
2935 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2936 return 0;
61a55e8b 2937 }
e0d80184 2938 prev_code = code;
61a55e8b 2939 }
e0d80184
DM		 2940 return 1;
2941}
2942\f
5751a10b
JJ		 2943/* Determine if it's legal to put X into the constant pool. This
2944 is not possible if X contains the address of a symbol that is
2945 not constant (TLS) or not known at final link time (PIC). */
2946
2947static bool
fbbf66e7 2948sparc_cannot_force_const_mem (enum machine_mode mode, rtx x)
5751a10b
JJ		 2949{
2950 switch (GET_CODE (x))
2951 {
2952 case CONST_INT:
2953 case CONST_DOUBLE:
c75d6010 2954 case CONST_VECTOR:
5751a10b
JJ		 2955 /* Accept all non-symbolic constants. */
2956 return false;
2957
2958 case LABEL_REF:
2959 /* Labels are OK iff we are non-PIC. */
2960 return flag_pic != 0;
2961
2962 case SYMBOL_REF:
2963 /* 'Naked' TLS symbol references are never OK,
2964 non-TLS symbols are OK iff we are non-PIC. */
2965 if (SYMBOL_REF_TLS_MODEL (x))
2966 return true;
2967 else
2968 return flag_pic != 0;
2969
2970 case CONST:
fbbf66e7 2971 return sparc_cannot_force_const_mem (mode, XEXP (x, 0));
5751a10b
JJ		 2972 case PLUS:
2973 case MINUS:
fbbf66e7
RS		 2974 return sparc_cannot_force_const_mem (mode, XEXP (x, 0))
2975 || sparc_cannot_force_const_mem (mode, XEXP (x, 1));
5751a10b
JJ		 2976 case UNSPEC:
2977 return true;
2978 default:
f5f7d171 2979 gcc_unreachable ();
5751a10b
JJ		 2980 }
2981}
2982\f
a6fed83f
EB		 2983/* Global Offset Table support. */
2984static GTY(()) rtx got_helper_rtx = NULL_RTX;
2985static GTY(()) rtx global_offset_table_rtx = NULL_RTX;
2986
2987/* Return the SYMBOL_REF for the Global Offset Table. */
2988
2989static GTY(()) rtx sparc_got_symbol = NULL_RTX;
2990
2991static rtx
2992sparc_got (void)
2993{
2994 if (!sparc_got_symbol)
2995 sparc_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2996
2997 return sparc_got_symbol;
2998}
bc961ed7 2999
e0d80184 3000/* Ensure that we are not using patterns that are not OK with PIC. */
795068a4 3001
e0d80184 3002int
fc27d102 3003check_pic (int i)
e0d80184 3004{
a6fed83f
EB		 3005 rtx op;
3006
e0d80184 3007 switch (flag_pic)
ab835497 3008 {
e0d80184 3009 case 1:
a6fed83f
EB		 3010 op = recog_data.operand[i];
3011 gcc_assert (GET_CODE (op) != SYMBOL_REF
3012 && (GET_CODE (op) != CONST
3013 || (GET_CODE (XEXP (op, 0)) == MINUS
3014 && XEXP (XEXP (op, 0), 0) == sparc_got ()
3015 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST)));
e0d80184
DM		 3016 case 2:
3017 default:
3018 return 1;
ab835497 3019 }
ab835497 3020}
795068a4 3021
4900aa61 3022/* Return true if X is an address which needs a temporary register when
e0d80184 3023 reloaded while generating PIC code. */
795068a4 3024
e0d80184 3025int
fc27d102 3026pic_address_needs_scratch (rtx x)
795068a4 3027{
e0d80184
DM		 3028 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3029 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3030 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3031 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3032 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3033 return 1;
795068a4 3034
e0d80184
DM		 3035 return 0;
3036}
795068a4 3037
5751a10b
JJ		 3038/* Determine if a given RTX is a valid constant. We already know this
3039 satisfies CONSTANT_P. */
3040
1a627b35
RS		 3041static bool
3042sparc_legitimate_constant_p (enum machine_mode mode, rtx x)
5751a10b 3043{
5751a10b
JJ		 3044 switch (GET_CODE (x))
3045 {
5751a10b 3046 case CONST:
208384fd
EB		 3047 case SYMBOL_REF:
3048 if (sparc_tls_referenced_p (x))
5751a10b
JJ		 3049 return false;
3050 break;
3051
3052 case CONST_DOUBLE:
3053 if (GET_MODE (x) == VOIDmode)
3054 return true;
3055
3056 /* Floating point constants are generally not ok.
3057 The only exception is 0.0 in VIS. */
3058 if (TARGET_VIS
1a627b35
RS		 3059 && SCALAR_FLOAT_MODE_P (mode)
3060 && const_zero_operand (x, mode))
bea5071f
EB		 3061 return true;
3062
3063 return false;
3064
3065 case CONST_VECTOR:
3066 /* Vector constants are generally not ok.
3067 The only exception is 0 in VIS. */
3068 if (TARGET_VIS
1a627b35 3069 && const_zero_operand (x, mode))
5751a10b
JJ		 3070 return true;
3071
3072 return false;
3073
3074 default:
3075 break;
3076 }
3077
3078 return true;
3079}
3080
3081/* Determine if a given RTX is a valid constant address. */
3082
3083bool
3084constant_address_p (rtx x)
3085{
3086 switch (GET_CODE (x))
3087 {
3088 case LABEL_REF:
3089 case CONST_INT:
3090 case HIGH:
3091 return true;
3092
3093 case CONST:
3094 if (flag_pic && pic_address_needs_scratch (x))
3095 return false;
1a627b35 3096 return sparc_legitimate_constant_p (Pmode, x);
5751a10b
JJ		 3097
3098 case SYMBOL_REF:
1a627b35 3099 return !flag_pic && sparc_legitimate_constant_p (Pmode, x);
5751a10b
JJ		 3100
3101 default:
3102 return false;
3103 }
3104}
3105
3106/* Nonzero if the constant value X is a legitimate general operand
3107 when generating PIC code. It is given that flag_pic is on and
3108 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3109
3110bool
3111legitimate_pic_operand_p (rtx x)
3112{
3113 if (pic_address_needs_scratch (x))
3114 return false;
208384fd 3115 if (sparc_tls_referenced_p (x))
5751a10b
JJ		 3116 return false;
3117 return true;
3118}
3119
b11b0904
EB		 3120#define RTX_OK_FOR_OFFSET_P(X, MODE) \
3121 (CONST_INT_P (X) \
3122 && INTVAL (X) >= -0x1000 \
3123 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
8b9a1428 3124
b11b0904
EB		 3125#define RTX_OK_FOR_OLO10_P(X, MODE) \
3126 (CONST_INT_P (X) \
3127 && INTVAL (X) >= -0x1000 \
3128 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
8b9a1428
AS		 3129
3130/* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3131
3132 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3133 ordinarily. This changes a bit when generating PIC. */
4900aa61 3134
c6c3dba9
PB		 3135static bool
3136sparc_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
5751a10b 3137{
f1b259d5 3138 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
5751a10b
JJ		 3139
3140 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3141 rs1 = addr;
3142 else if (GET_CODE (addr) == PLUS)
3143 {
3144 rs1 = XEXP (addr, 0);
3145 rs2 = XEXP (addr, 1);
3146
3147 /* Canonicalize. REG comes first, if there are no regs,
3148 LO_SUM comes first. */
3149 if (!REG_P (rs1)
3150 && GET_CODE (rs1) != SUBREG
3151 && (REG_P (rs2)
3152 || GET_CODE (rs2) == SUBREG
3153 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3154 {
3155 rs1 = XEXP (addr, 1);
3156 rs2 = XEXP (addr, 0);
3157 }
3158
3159 if ((flag_pic == 1
3160 && rs1 == pic_offset_table_rtx
3161 && !REG_P (rs2)
3162 && GET_CODE (rs2) != SUBREG
3163 && GET_CODE (rs2) != LO_SUM
3164 && GET_CODE (rs2) != MEM
208384fd 3165 && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
5751a10b
JJ		 3166 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3167 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3168 || ((REG_P (rs1)
3169 || GET_CODE (rs1) == SUBREG)
b11b0904 3170 && RTX_OK_FOR_OFFSET_P (rs2, mode)))
5751a10b
JJ		 3171 {
3172 imm1 = rs2;
3173 rs2 = NULL;
3174 }
3175 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3176 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3177 {
39ba2f92
EB		 3178 /* We prohibit REG + REG for TFmode when there are no quad move insns
3179 and we consequently need to split. We do this because REG+REG
3180 is not an offsettable address. If we get the situation in reload
5751a10b
JJ		 3181 where source and destination of a movtf pattern are both MEMs with
3182 REG+REG address, then only one of them gets converted to an
39ba2f92 3183 offsettable address. */
5751a10b 3184 if (mode == TFmode
39ba2f92 3185 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
5751a10b
JJ		 3186 return 0;
3187
3188 /* We prohibit REG + REG on ARCH32 if not optimizing for
3189 DFmode/DImode because then mem_min_alignment is likely to be zero
3190 after reload and the forced split would lack a matching splitter
3191 pattern. */
3192 if (TARGET_ARCH32 && !optimize
3193 && (mode == DFmode || mode == DImode))
3194 return 0;
3195 }
3196 else if (USE_AS_OFFSETABLE_LO10
3197 && GET_CODE (rs1) == LO_SUM
3198 && TARGET_ARCH64
3199 && ! TARGET_CM_MEDMID
b11b0904 3200 && RTX_OK_FOR_OLO10_P (rs2, mode))
5751a10b 3201 {
5751a10b
JJ		 3202 rs2 = NULL;
3203 imm1 = XEXP (rs1, 1);
3204 rs1 = XEXP (rs1, 0);
208384fd
EB		 3205 if (!CONSTANT_P (imm1)
3206 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
5751a10b
JJ		 3207 return 0;
3208 }
3209 }
3210 else if (GET_CODE (addr) == LO_SUM)
3211 {
3212 rs1 = XEXP (addr, 0);
3213 imm1 = XEXP (addr, 1);
3214
208384fd
EB		 3215 if (!CONSTANT_P (imm1)
3216 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
5751a10b
JJ		 3217 return 0;
3218
f1b259d5
EB		 3219 /* We can't allow TFmode in 32-bit mode, because an offset greater
3220 than the alignment (8) may cause the LO_SUM to overflow. */
d24088cc 3221 if (mode == TFmode && TARGET_ARCH32)
f1b259d5 3222 return 0;
5751a10b
JJ		 3223 }
3224 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3225 return 1;
3226 else
3227 return 0;
3228
3229 if (GET_CODE (rs1) == SUBREG)
3230 rs1 = SUBREG_REG (rs1);
3231 if (!REG_P (rs1))
3232 return 0;
3233
3234 if (rs2)
3235 {
3236 if (GET_CODE (rs2) == SUBREG)
3237 rs2 = SUBREG_REG (rs2);
3238 if (!REG_P (rs2))
3239 return 0;
3240 }
3241
3242 if (strict)
3243 {
3244 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3245 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3246 return 0;
3247 }
3248 else
3249 {
3250 if ((REGNO (rs1) >= 32
3251 && REGNO (rs1) != FRAME_POINTER_REGNUM
3252 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3253 || (rs2
3254 && (REGNO (rs2) >= 32
3255 && REGNO (rs2) != FRAME_POINTER_REGNUM
3256 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3257 return 0;
3258 }
3259 return 1;
3260}
3261
a6fed83f 3262/* Return the SYMBOL_REF for the tls_get_addr function. */
5751a10b 3263
a6fed83f 3264static GTY(()) rtx sparc_tls_symbol = NULL_RTX;
38fc66ba 3265
5751a10b
JJ		 3266static rtx
3267sparc_tls_get_addr (void)
3268{
3269 if (!sparc_tls_symbol)
3270 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3271
3272 return sparc_tls_symbol;
3273}
3274
a6fed83f
EB		 3275/* Return the Global Offset Table to be used in TLS mode. */
3276
5751a10b
JJ		 3277static rtx
3278sparc_tls_got (void)
3279{
a6fed83f 3280 /* In PIC mode, this is just the PIC offset table. */
5751a10b
JJ		 3281 if (flag_pic)
3282 {
e3b5732b 3283 crtl->uses_pic_offset_table = 1;
5751a10b
JJ		 3284 return pic_offset_table_rtx;
3285 }
3286
a6fed83f
EB		 3287 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
3288 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
3289 if (TARGET_SUN_TLS && TARGET_ARCH32)
3290 {
3291 load_got_register ();
3292 return global_offset_table_rtx;
3293 }
3294
3295 /* In all other cases, we load a new pseudo with the GOT symbol. */
3296 return copy_to_reg (sparc_got ());
5751a10b
JJ		 3297}
3298
208384fd 3299/* Return true if X contains a thread-local symbol. */
38fc66ba 3300
208384fd 3301static bool
38fc66ba
EB		 3302sparc_tls_referenced_p (rtx x)
3303{
3304 if (!TARGET_HAVE_TLS)
3305 return false;
3306
208384fd
EB		 3307 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
3308 x = XEXP (XEXP (x, 0), 0);
3309
3310 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x))
3311 return true;
3312
58e6223e 3313 /* That's all we handle in sparc_legitimize_tls_address for now. */
208384fd 3314 return false;
38fc66ba 3315}
5751a10b
JJ		 3316
3317/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3318 this (thread-local) address. */
3319
208384fd 3320static rtx
58e6223e 3321sparc_legitimize_tls_address (rtx addr)
5751a10b
JJ		 3322{
3323 rtx temp1, temp2, temp3, ret, o0, got, insn;
3324
b3a13419 3325 gcc_assert (can_create_pseudo_p ());
5751a10b
JJ		 3326
3327 if (GET_CODE (addr) == SYMBOL_REF)
3328 switch (SYMBOL_REF_TLS_MODEL (addr))
3329 {
3330 case TLS_MODEL_GLOBAL_DYNAMIC:
3331 start_sequence ();
3332 temp1 = gen_reg_rtx (SImode);
3333 temp2 = gen_reg_rtx (SImode);
3334 ret = gen_reg_rtx (Pmode);
3335 o0 = gen_rtx_REG (Pmode, 8);
3336 got = sparc_tls_got ();
3337 emit_insn (gen_tgd_hi22 (temp1, addr));
3338 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3339 if (TARGET_ARCH32)
3340 {
3341 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3342 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3343 addr, const1_rtx));
3344 }
3345 else
3346 {
3347 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3348 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3349 addr, const1_rtx));
3350 }
44f370bf 3351 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
5751a10b
JJ		 3352 insn = get_insns ();
3353 end_sequence ();
3354 emit_libcall_block (insn, ret, o0, addr);
3355 break;
3356
3357 case TLS_MODEL_LOCAL_DYNAMIC:
3358 start_sequence ();
3359 temp1 = gen_reg_rtx (SImode);
3360 temp2 = gen_reg_rtx (SImode);
3361 temp3 = gen_reg_rtx (Pmode);
3362 ret = gen_reg_rtx (Pmode);
3363 o0 = gen_rtx_REG (Pmode, 8);
3364 got = sparc_tls_got ();
3365 emit_insn (gen_tldm_hi22 (temp1));
3366 emit_insn (gen_tldm_lo10 (temp2, temp1));
3367 if (TARGET_ARCH32)
3368 {
3369 emit_insn (gen_tldm_add32 (o0, got, temp2));
3370 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3371 const1_rtx));
3372 }
3373 else
3374 {
3375 emit_insn (gen_tldm_add64 (o0, got, temp2));
3376 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3377 const1_rtx));
3378 }
44f370bf 3379 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
5751a10b
JJ		 3380 insn = get_insns ();
3381 end_sequence ();
3382 emit_libcall_block (insn, temp3, o0,
3383 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3384 UNSPEC_TLSLD_BASE));
3385 temp1 = gen_reg_rtx (SImode);
3386 temp2 = gen_reg_rtx (SImode);
3387 emit_insn (gen_tldo_hix22 (temp1, addr));
3388 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3389 if (TARGET_ARCH32)
3390 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3391 else
3392 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3393 break;
3394
3395 case TLS_MODEL_INITIAL_EXEC:
3396 temp1 = gen_reg_rtx (SImode);
3397 temp2 = gen_reg_rtx (SImode);
3398 temp3 = gen_reg_rtx (Pmode);
3399 got = sparc_tls_got ();
3400 emit_insn (gen_tie_hi22 (temp1, addr));
3401 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3402 if (TARGET_ARCH32)
3403 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3404 else
3405 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3406 if (TARGET_SUN_TLS)
3407 {
3408 ret = gen_reg_rtx (Pmode);
3409 if (TARGET_ARCH32)
3410 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3411 temp3, addr));
3412 else
3413 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3414 temp3, addr));
3415 }
3416 else
3417 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3418 break;
3419
3420 case TLS_MODEL_LOCAL_EXEC:
3421 temp1 = gen_reg_rtx (Pmode);
3422 temp2 = gen_reg_rtx (Pmode);
3423 if (TARGET_ARCH32)
3424 {
3425 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3426 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3427 }
3428 else
3429 {
3430 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3431 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3432 }
3433 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3434 break;
3435
3436 default:
f5f7d171 3437 gcc_unreachable ();
5751a10b
JJ		 3438 }
3439
208384fd
EB		 3440 else if (GET_CODE (addr) == CONST)
3441 {
3442 rtx base, offset;
3443
3444 gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS);
3445
58e6223e 3446 base = sparc_legitimize_tls_address (XEXP (XEXP (addr, 0), 0));
208384fd
EB		 3447 offset = XEXP (XEXP (addr, 0), 1);
3448
3449 base = force_operand (base, NULL_RTX);
3450 if (!(GET_CODE (offset) == CONST_INT && SMALL_INT (offset)))
3451 offset = force_reg (Pmode, offset);
3452 ret = gen_rtx_PLUS (Pmode, base, offset);
3453 }
3454
5751a10b 3455 else
f5f7d171 3456 gcc_unreachable (); /* for now ... */
5751a10b
JJ		 3457
3458 return ret;
3459}
3460
e0d80184
DM		 3461/* Legitimize PIC addresses. If the address is already position-independent,
3462 we return ORIG. Newly generated position-independent addresses go into a
88cad84b 3463 reg. This is REG if nonzero, otherwise we allocate register(s) as
e0d80184 3464 necessary. */
795068a4 3465
208384fd 3466static rtx
58e6223e 3467sparc_legitimize_pic_address (rtx orig, rtx reg)
e0d80184 3468{
878ee0ab
DM		 3469 bool gotdata_op = false;
3470
1910440e
RS		 3471 if (GET_CODE (orig) == SYMBOL_REF
3472 /* See the comment in sparc_expand_move. */
205e4c6a 3473 || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig)))
82d6b402 3474 {
e0d80184
DM		 3475 rtx pic_ref, address;
3476 rtx insn;
82d6b402 3477
e0d80184 3478 if (reg == 0)
82d6b402 3479 {
f5f7d171
JM		 3480 gcc_assert (! reload_in_progress && ! reload_completed);
3481 reg = gen_reg_rtx (Pmode);
82d6b402 3482 }
795068a4 3483
e0d80184 3484 if (flag_pic == 2)
4fb4e4b8 3485 {
e0d80184
DM		 3486 /* If not during reload, allocate another temp reg here for loading
3487 in the address, so that these instructions can be optimized
3488 properly. */
3489 rtx temp_reg = ((reload_in_progress || reload_completed)
3490 ? reg : gen_reg_rtx (Pmode));
3491
3492 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3493 won't get confused into thinking that these two instructions
3494 are loading in the true address of the symbol. If in the
3495 future a PIC rtx exists, that should be used instead. */
bea5071f 3496 if (TARGET_ARCH64)
be3f1ff5 3497 {
bea5071f
EB		 3498 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3499 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
be3f1ff5
DM		 3500 }
3501 else
3502 {
bea5071f
EB		 3503 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3504 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
be3f1ff5 3505 }
e0d80184 3506 address = temp_reg;
878ee0ab 3507 gotdata_op = true;
4fb4e4b8
DE		 3508 }
3509 else
e0d80184
DM		 3510 address = orig;
3511
e3b5732b 3512 crtl->uses_pic_offset_table = 1;
878ee0ab
DM		 3513 if (gotdata_op)
3514 {
3515 if (TARGET_ARCH64)
58e6223e
EB		 3516 insn = emit_insn (gen_movdi_pic_gotdata_op (reg,
3517 pic_offset_table_rtx,
878ee0ab
DM		 3518 address, orig));
3519 else
58e6223e
EB		 3520 insn = emit_insn (gen_movsi_pic_gotdata_op (reg,
3521 pic_offset_table_rtx,
878ee0ab
DM		 3522 address, orig));
3523 }
3524 else
3525 {
205e4c6a
EB		 3526 pic_ref
3527 = gen_const_mem (Pmode,
3528 gen_rtx_PLUS (Pmode,
3529 pic_offset_table_rtx, address));
878ee0ab
DM		 3530 insn = emit_move_insn (reg, pic_ref);
3531 }
205e4c6a 3532
e0d80184
DM		 3533 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3534 by loop. */
bd94cb6e 3535 set_unique_reg_note (insn, REG_EQUAL, orig);
e0d80184 3536 return reg;
795068a4 3537 }
e0d80184 3538 else if (GET_CODE (orig) == CONST)
795068a4 3539 {
e0d80184 3540 rtx base, offset;
795068a4 3541
e0d80184
DM		 3542 if (GET_CODE (XEXP (orig, 0)) == PLUS
3543 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3544 return orig;
82d6b402 3545
e0d80184 3546 if (reg == 0)
4fb4e4b8 3547 {
f5f7d171
JM		 3548 gcc_assert (! reload_in_progress && ! reload_completed);
3549 reg = gen_reg_rtx (Pmode);
4fb4e4b8 3550 }
e0d80184 3551
f5f7d171 3552 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
58e6223e
EB		 3553 base = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
3554 offset = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
3555 base == reg ? NULL_RTX : reg);
61a66555 3556
e0d80184
DM		 3557 if (GET_CODE (offset) == CONST_INT)
3558 {
3559 if (SMALL_INT (offset))
ed8908e7 3560 return plus_constant (base, INTVAL (offset));
e0d80184
DM		 3561 else if (! reload_in_progress && ! reload_completed)
3562 offset = force_reg (Pmode, offset);
3563 else
3564 /* If we reach here, then something is seriously wrong. */
f5f7d171 3565 gcc_unreachable ();
e0d80184
DM		 3566 }
3567 return gen_rtx_PLUS (Pmode, base, offset);
795068a4 3568 }
e0d80184 3569 else if (GET_CODE (orig) == LABEL_REF)
205e4c6a
EB		 3570 /* ??? We ought to be checking that the register is live instead, in case
3571 it is eliminated. */
e3b5732b 3572 crtl->uses_pic_offset_table = 1;
795068a4 3573
e0d80184
DM		 3574 return orig;
3575}
795068a4 3576
5751a10b
JJ		 3577/* Try machine-dependent ways of modifying an illegitimate address X
3578 to be legitimate. If we find one, return the new, valid address.
3579
3580 OLDX is the address as it was before break_out_memory_refs was called.
3581 In some cases it is useful to look at this to decide what needs to be done.
3582
506d7b68
PB		 3583 MODE is the mode of the operand pointed to by X.
3584
3585 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
5751a10b 3586
208384fd 3587static rtx
506d7b68
PB		 3588sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3589 enum machine_mode mode)
5751a10b
JJ		 3590{
3591 rtx orig_x = x;
3592
3593 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3594 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3595 force_operand (XEXP (x, 0), NULL_RTX));
3596 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3597 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3598 force_operand (XEXP (x, 1), NULL_RTX));
3599 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3600 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3601 XEXP (x, 1));
3602 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3603 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3604 force_operand (XEXP (x, 1), NULL_RTX));
3605
c6c3dba9 3606 if (x != orig_x && sparc_legitimate_address_p (mode, x, FALSE))
5751a10b
JJ		 3607 return x;
3608
208384fd 3609 if (sparc_tls_referenced_p (x))
58e6223e 3610 x = sparc_legitimize_tls_address (x);
5751a10b 3611 else if (flag_pic)
58e6223e 3612 x = sparc_legitimize_pic_address (x, NULL_RTX);
5751a10b
JJ		 3613 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3614 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3615 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3616 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3617 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3618 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3619 else if (GET_CODE (x) == SYMBOL_REF
3620 || GET_CODE (x) == CONST
208384fd 3621 || GET_CODE (x) == LABEL_REF)
5751a10b 3622 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
208384fd 3623
5751a10b
JJ		 3624 return x;
3625}
3626
8e7a6ed6
EB		 3627/* Delegitimize an address that was legitimized by the above function. */
3628
3629static rtx
3630sparc_delegitimize_address (rtx x)
3631{
3632 x = delegitimize_mem_from_attrs (x);
3633
145f6c5b
EB		 3634 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 1)) == UNSPEC)
3635 switch (XINT (XEXP (x, 1), 1))
3636 {
3637 case UNSPEC_MOVE_PIC:
3638 case UNSPEC_TLSLE:
3639 x = XVECEXP (XEXP (x, 1), 0, 0);
3640 gcc_assert (GET_CODE (x) == SYMBOL_REF);
3641 break;
3642 default:
3643 break;
3644 }
8e7a6ed6 3645
806c3492
EB		 3646 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
3647 if (GET_CODE (x) == MINUS
3648 && REG_P (XEXP (x, 0))
3649 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
3650 && GET_CODE (XEXP (x, 1)) == LO_SUM
3651 && GET_CODE (XEXP (XEXP (x, 1), 1)) == UNSPEC
3652 && XINT (XEXP (XEXP (x, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL)
3653 {
3654 x = XVECEXP (XEXP (XEXP (x, 1), 1), 0, 0);
3655 gcc_assert (GET_CODE (x) == LABEL_REF);
3656 }
3657
8e7a6ed6
EB		 3658 return x;
3659}
3660
58e6223e
EB		 3661/* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3662 replace the input X, or the original X if no replacement is called for.
3663 The output parameter *WIN is 1 if the calling macro should goto WIN,
3664 0 if it should not.
3665
3666 For SPARC, we wish to handle addresses by splitting them into
3667 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
3668 This cuts the number of extra insns by one.
3669
3670 Do nothing when generating PIC code and the address is a symbolic
3671 operand or requires a scratch register. */
3672
3673rtx
3674sparc_legitimize_reload_address (rtx x, enum machine_mode mode,
3675 int opnum, int type,
3676 int ind_levels ATTRIBUTE_UNUSED, int *win)
3677{
3678 /* Decompose SImode constants into HIGH+LO_SUM. */
3679 if (CONSTANT_P (x)
3680 && (mode != TFmode || TARGET_ARCH64)
3681 && GET_MODE (x) == SImode
3682 && GET_CODE (x) != LO_SUM
3683 && GET_CODE (x) != HIGH
3684 && sparc_cmodel <= CM_MEDLOW
3685 && !(flag_pic
3686 && (symbolic_operand (x, Pmode) || pic_address_needs_scratch (x))))
3687 {
3688 x = gen_rtx_LO_SUM (GET_MODE (x), gen_rtx_HIGH (GET_MODE (x), x), x);
3689 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3690 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3691 opnum, (enum reload_type)type);
3692 *win = 1;
3693 return x;
3694 }
3695
3696 /* We have to recognize what we have already generated above. */
3697 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == HIGH)
3698 {
3699 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3700 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3701 opnum, (enum reload_type)type);
3702 *win = 1;
3703 return x;
3704 }
3705
3706 *win = 0;
3707 return x;
3708}
3709
277e2873
AS		 3710/* Return true if ADDR (a legitimate address expression)
3711 has an effect that depends on the machine mode it is used for.
3712
3713 In PIC mode,
3714
3715 (mem:HI [%l7+a])
3716
3717 is not equivalent to
3718
3719 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
3720
3721 because [%l7+a+1] is interpreted as the address of (a+1). */
3722
3723
3724static bool
3725sparc_mode_dependent_address_p (const_rtx addr)
3726{
3727 if (flag_pic && GET_CODE (addr) == PLUS)
3728 {
3729 rtx op0 = XEXP (addr, 0);
3730 rtx op1 = XEXP (addr, 1);
3731 if (op0 == pic_offset_table_rtx
8b9a1428 3732 && symbolic_operand (op1, VOIDmode))
277e2873
AS		 3733 return true;
3734 }
3735
3736 return false;
3737}
3738
9fd52c6c
DM		 3739#ifdef HAVE_GAS_HIDDEN
3740# define USE_HIDDEN_LINKONCE 1
3741#else
3742# define USE_HIDDEN_LINKONCE 0
3743#endif
795068a4 3744
9ac617d4 3745static void
9fd52c6c 3746get_pc_thunk_name (char name[32], unsigned int regno)
e0d80184 3747{
a6fed83f 3748 const char *reg_name = reg_names[regno];
4fb4e4b8 3749
9fd52c6c
DM		 3750 /* Skip the leading '%' as that cannot be used in a
3751 symbol name. */
a6fed83f 3752 reg_name += 1;
82d6b402 3753
9fd52c6c 3754 if (USE_HIDDEN_LINKONCE)
a6fed83f 3755 sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
5e77eb53 3756 else
9fd52c6c 3757 ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
5e77eb53
EB		 3758}
3759
a6fed83f 3760/* Wrapper around the load_pcrel_sym{si,di} patterns. */
5e77eb53 3761
a6fed83f
EB		 3762static rtx
3763gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2, rtx op3)
5e77eb53
EB		 3764{
3765 int orig_flag_pic = flag_pic;
a6fed83f 3766 rtx insn;
5e77eb53 3767
a6fed83f
EB		 3768 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
3769 flag_pic = 0;
3770 if (TARGET_ARCH64)
3771 insn = gen_load_pcrel_symdi (op0, op1, op2, op3);
3772 else
3773 insn = gen_load_pcrel_symsi (op0, op1, op2, op3);
3774 flag_pic = orig_flag_pic;
9fd52c6c 3775
a6fed83f
EB		 3776 return insn;
3777}
9fd52c6c 3778
a6fed83f 3779/* Emit code to load the GOT register. */
9fd52c6c 3780
bc6d3f91 3781void
a6fed83f
EB		 3782load_got_register (void)
3783{
3784 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
3785 if (!global_offset_table_rtx)
3786 global_offset_table_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
82d6b402 3787
a6fed83f
EB		 3788 if (TARGET_VXWORKS_RTP)
3789 emit_insn (gen_vxworks_load_got ());
eb7a7903 3790 else
a6fed83f
EB		 3791 {
3792 /* The GOT symbol is subject to a PC-relative relocation so we need a
3793 helper function to add the PC value and thus get the final value. */
3794 if (!got_helper_rtx)
3795 {
3796 char name[32];
3797 get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
3798 got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
3799 }
3800
3801 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx, sparc_got (),
3802 got_helper_rtx,
3803 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM)));
3804 }
82d6b402 3805
e0d80184
DM		 3806 /* Need to emit this whether or not we obey regdecls,
3807 since setjmp/longjmp can cause life info to screw up.
3808 ??? In the case where we don't obey regdecls, this is not sufficient
3809 since we may not fall out the bottom. */
a6fed83f 3810 emit_use (global_offset_table_rtx);
795068a4 3811}
1910440e
RS		 3812
3813/* Emit a call instruction with the pattern given by PAT. ADDR is the
3814 address of the call target. */
3815
3816void
3817sparc_emit_call_insn (rtx pat, rtx addr)
3818{
3819 rtx insn;
3820
3821 insn = emit_call_insn (pat);
3822
3823 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
3824 if (TARGET_VXWORKS_RTP
3825 && flag_pic
3826 && GET_CODE (addr) == SYMBOL_REF
3827 && (SYMBOL_REF_DECL (addr)
3828 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
3829 : !SYMBOL_REF_LOCAL_P (addr)))
3830 {
3831 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
e3b5732b 3832 crtl->uses_pic_offset_table = 1;
1910440e
RS		 3833 }
3834}
ab835497 3835\f
e0d80184 3836/* Return 1 if RTX is a MEM which is known to be aligned to at
7a31a340 3837 least a DESIRED byte boundary. */
a3ee5899 3838
e0d80184 3839int
fc27d102 3840mem_min_alignment (rtx mem, int desired)
ab835497 3841{
e0d80184
DM		 3842 rtx addr, base, offset;
3843
3844 /* If it's not a MEM we can't accept it. */
3845 if (GET_CODE (mem) != MEM)
3846 return 0;
3847
167a1354 3848 /* Obviously... */
0f95e914
EB		 3849 if (!TARGET_UNALIGNED_DOUBLES
3850 && MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired)
167a1354
EB		 3851 return 1;
3852
3853 /* ??? The rest of the function predates MEM_ALIGN so
3854 there is probably a bit of redundancy. */
e0d80184
DM		 3855 addr = XEXP (mem, 0);
3856 base = offset = NULL_RTX;
3857 if (GET_CODE (addr) == PLUS)
ab835497 3858 {
e0d80184 3859 if (GET_CODE (XEXP (addr, 0)) == REG)
61a55e8b 3860 {
e0d80184
DM		 3861 base = XEXP (addr, 0);
3862
3863 /* What we are saying here is that if the base
3864 REG is aligned properly, the compiler will make
3865 sure any REG based index upon it will be so
3866 as well. */
3867 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3868 offset = XEXP (addr, 1);
61a55e8b 3869 else
e0d80184 3870 offset = const0_rtx;
61a55e8b 3871 }
ab835497 3872 }
e0d80184 3873 else if (GET_CODE (addr) == REG)
ab835497 3874 {
e0d80184
DM		 3875 base = addr;
3876 offset = const0_rtx;
ab835497 3877 }
82d6b402 3878
e0d80184 3879 if (base != NULL_RTX)
795068a4 3880 {
e0d80184
DM		 3881 int regno = REGNO (base);
3882
563c12b0 3883 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
61a55e8b 3884 {
e0d80184
DM		 3885 /* Check if the compiler has recorded some information
3886 about the alignment of the base REG. If reload has
021e2ecc
JJ		 3887 completed, we already matched with proper alignments.
3888 If not running global_alloc, reload might give us
3889 unaligned pointer to local stack though. */
bdb429a5
RK		 3890 if (((cfun != 0
3891 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
021e2ecc 3892 || (optimize && reload_completed))
bdb429a5 3893 && (INTVAL (offset) & (desired - 1)) == 0)
e0d80184 3894 return 1;
61a55e8b 3895 }
795068a4 3896 else
e0d80184
DM		 3897 {
3898 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3899 return 1;
3900 }
795068a4 3901 }
e0d80184
DM		 3902 else if (! TARGET_UNALIGNED_DOUBLES
3903 || CONSTANT_P (addr)
3904 || GET_CODE (addr) == LO_SUM)
795068a4 3905 {
e0d80184
DM		 3906 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3907 is true, in which case we can only assume that an access is aligned if
3908 it is to a constant address, or the address involves a LO_SUM. */
3909 return 1;
795068a4 3910 }
4900aa61 3911
e0d80184
DM		 3912 /* An obviously unaligned address. */
3913 return 0;
795068a4 3914}
e0d80184 3915
ab835497 3916\f
61a55e8b 3917/* Vectors to keep interesting information about registers where it can easily
01d3224a 3918 be got. We used to use the actual mode value as the bit number, but there
61a55e8b
DE		 3919 are more than 32 modes now. Instead we use two tables: one indexed by
3920 hard register number, and one indexed by mode. */
3921
3922/* The purpose of sparc_mode_class is to shrink the range of modes so that
a7b376ee 3923 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
61a55e8b
DE		 3924 mapped into one sparc_mode_class mode. */
3925
3926enum sparc_mode_class {
61a55e8b 3927 S_MODE, D_MODE, T_MODE, O_MODE,
c4ce6853
DE		 3928 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3929 CC_MODE, CCFP_MODE
61a55e8b 3930};
ab835497 3931
61a55e8b
DE		 3932/* Modes for single-word and smaller quantities. */
3933#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3934
3935/* Modes for double-word and smaller quantities. */
3936#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3937
3938/* Modes for quad-word and smaller quantities. */
3939#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
ab835497 3940
d0cee9ba
JJ		 3941/* Modes for 8-word and smaller quantities. */
3942#define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3943
1e4eb8d1
JW		 3944/* Modes for single-float quantities. We must allow any single word or
3945 smaller quantity. This is because the fix/float conversion instructions
3946 take integer inputs/outputs from the float registers. */
3947#define SF_MODES (S_MODES)
ab835497 3948
61a55e8b 3949/* Modes for double-float and smaller quantities. */
948bf106 3950#define DF_MODES (D_MODES)
61a55e8b
DE		 3951
3952/* Modes for quad-float and smaller quantities. */
948bf106 3953#define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
61a55e8b 3954
948bf106
EB		 3955/* Modes for quad-float pairs and smaller quantities. */
3956#define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
d0cee9ba 3957
948bf106
EB		 3958/* Modes for double-float only quantities. */
3959#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
d0cee9ba 3960
948bf106
EB		 3961/* Modes for quad-float and double-float only quantities. */
3962#define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
d0cee9ba 3963
948bf106
EB		 3964/* Modes for quad-float pairs and double-float only quantities. */
3965#define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
ab835497 3966
c4ce6853
DE		 3967/* Modes for condition codes. */
3968#define CC_MODES (1 << (int) CC_MODE)
3969#define CCFP_MODES (1 << (int) CCFP_MODE)
3970
ab835497
RK		 3971/* Value is 1 if register/mode pair is acceptable on sparc.
3972 The funny mixture of D and T modes is because integer operations
3973 do not specially operate on tetra quantities, so non-quad-aligned
3974 registers can hold quadword quantities (except %o4 and %i4 because
c4ce6853 3975 they cross fixed registers). */
ab835497 3976
61a55e8b 3977/* This points to either the 32 bit or the 64 bit version. */
0b5826ac 3978const int *hard_regno_mode_classes;
61a55e8b 3979
0b5826ac 3980static const int hard_32bit_mode_classes[] = {
c4ce6853 3981 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
ab835497
RK		 3982 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3983 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3984 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3985
d0cee9ba
JJ		 3986 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3987 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3988 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3989 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
a9e27770
DE		 3990
3991 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3992 and none can hold SFmode/SImode values. */
d0cee9ba
JJ		 3993 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3994 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3995 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3996 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
a9e27770
DE		 3997
3998 /* %fcc[0123] */
c4ce6853
DE		 3999 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4000
4001 /* %icc */
4002 CC_MODES
61a55e8b
DE		 4003};
4004
0b5826ac 4005static const int hard_64bit_mode_classes[] = {
c4ce6853 4006 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
d0cee9ba 4007 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
61a55e8b 4008 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
d0cee9ba 4009 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
61a55e8b 4010
d0cee9ba
JJ		 4011 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4012 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4013 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4014 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
61a55e8b 4015
a9e27770 4016 /* FP regs f32 to f63. Only the even numbered registers actually exist,
61a55e8b 4017 and none can hold SFmode/SImode values. */
d0cee9ba
JJ		 4018 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4019 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4020 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4021 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
61a55e8b
DE		 4022
4023 /* %fcc[0123] */
c4ce6853
DE		 4024 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4025
4026 /* %icc */
4027 CC_MODES
61a55e8b
DE		 4028};
4029
4030int sparc_mode_class [NUM_MACHINE_MODES];
4031
c4ce6853
DE		 4032enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4033
61a55e8b 4034static void
fc27d102 4035sparc_init_modes (void)
61a55e8b
DE		 4036{
4037 int i;
4038
61a55e8b
DE		 4039 for (i = 0; i < NUM_MACHINE_MODES; i++)
4040 {
4041 switch (GET_MODE_CLASS (i))
4042 {
4043 case MODE_INT:
4044 case MODE_PARTIAL_INT:
4045 case MODE_COMPLEX_INT:
4046 if (GET_MODE_SIZE (i) <= 4)
4047 sparc_mode_class[i] = 1 << (int) S_MODE;
4048 else if (GET_MODE_SIZE (i) == 8)
4049 sparc_mode_class[i] = 1 << (int) D_MODE;
4050 else if (GET_MODE_SIZE (i) == 16)
4051 sparc_mode_class[i] = 1 << (int) T_MODE;
4052 else if (GET_MODE_SIZE (i) == 32)
4053 sparc_mode_class[i] = 1 << (int) O_MODE;
4900aa61 4054 else
61a55e8b
DE		 4055 sparc_mode_class[i] = 0;
4056 break;
c75d6010
JM		 4057 case MODE_VECTOR_INT:
4058 if (GET_MODE_SIZE (i) <= 4)
4059 sparc_mode_class[i] = 1 << (int)SF_MODE;
4060 else if (GET_MODE_SIZE (i) == 8)
4061 sparc_mode_class[i] = 1 << (int)DF_MODE;
4062 break;
61a55e8b
DE		 4063 case MODE_FLOAT:
4064 case MODE_COMPLEX_FLOAT:
4065 if (GET_MODE_SIZE (i) <= 4)
4066 sparc_mode_class[i] = 1 << (int) SF_MODE;
4067 else if (GET_MODE_SIZE (i) == 8)
4068 sparc_mode_class[i] = 1 << (int) DF_MODE;
4069 else if (GET_MODE_SIZE (i) == 16)
4070 sparc_mode_class[i] = 1 << (int) TF_MODE;
4071 else if (GET_MODE_SIZE (i) == 32)
4072 sparc_mode_class[i] = 1 << (int) OF_MODE;
4900aa61 4073 else
61a55e8b
DE		 4074 sparc_mode_class[i] = 0;
4075 break;
4076 case MODE_CC:
61a55e8b
DE		 4077 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4078 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
61a55e8b 4079 else
94134f42
ZW		 4080 sparc_mode_class[i] = 1 << (int) CC_MODE;
4081 break;
4082 default:
4083 sparc_mode_class[i] = 0;
61a55e8b
DE		 4084 break;
4085 }
4086 }
4087
a9e27770 4088 if (TARGET_ARCH64)
61a55e8b
DE		 4089 hard_regno_mode_classes = hard_64bit_mode_classes;
4090 else
4091 hard_regno_mode_classes = hard_32bit_mode_classes;
c4ce6853
DE		 4092
4093 /* Initialize the array used by REGNO_REG_CLASS. */
4094 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4095 {
284d86e9
JC		 4096 if (i < 16 && TARGET_V8PLUS)
4097 sparc_regno_reg_class[i] = I64_REGS;
563c12b0 4098 else if (i < 32 || i == FRAME_POINTER_REGNUM)
c4ce6853
DE		 4099 sparc_regno_reg_class[i] = GENERAL_REGS;
4100 else if (i < 64)
4101 sparc_regno_reg_class[i] = FP_REGS;
4102 else if (i < 96)
4103 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4104 else if (i < 100)
4105 sparc_regno_reg_class[i] = FPCC_REGS;
4106 else
4107 sparc_regno_reg_class[i] = NO_REGS;
4108 }
61a55e8b 4109}
ab835497 4110\f
b11b0904
EB		 4111/* Return whether REGNO, a global or FP register, must be saved/restored. */
4112
4113static inline bool
4114save_global_or_fp_reg_p (unsigned int regno,
4115 int leaf_function ATTRIBUTE_UNUSED)
4116{
4117 return !call_used_regs[regno] && df_regs_ever_live_p (regno);
4118}
4119
4120/* Return whether the return address register (%i7) is needed. */
4121
4122static inline bool
4123return_addr_reg_needed_p (int leaf_function)
4124{
4125 /* If it is live, for example because of __builtin_return_address (0). */
4126 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM))
4127 return true;
4128
4129 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4130 if (!leaf_function
4131 /* Loading the GOT register clobbers %o7. */
4132 || crtl->uses_pic_offset_table
4133 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM))
4134 return true;
4135
4136 return false;
4137}
4138
4139/* Return whether REGNO, a local or in register, must be saved/restored. */
4140
4141static bool
4142save_local_or_in_reg_p (unsigned int regno, int leaf_function)
4143{
4144 /* General case: call-saved registers live at some point. */
4145 if (!call_used_regs[regno] && df_regs_ever_live_p (regno))
4146 return true;
4147
4148 /* Frame pointer register (%fp) if needed. */
4149 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
4150 return true;
4151
4152 /* Return address register (%i7) if needed. */
4153 if (regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p (leaf_function))
4154 return true;
4155
4156 /* PIC register (%l7) if needed. */
4157 if (regno == PIC_OFFSET_TABLE_REGNUM && crtl->uses_pic_offset_table)
4158 return true;
4159
4160 /* If the function accesses prior frames, the frame pointer and the return
4161 address of the previous frame must be saved on the stack. */
4162 if (crtl->accesses_prior_frames
4163 && (regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM))
4164 return true;
4165
4166 return false;
4167}
4168
61a55e8b 4169/* Compute the frame size required by the function. This function is called
9ac617d4 4170 during the reload pass and also by sparc_expand_prologue. */
ab835497 4171
6a151f87 4172HOST_WIDE_INT
b11b0904 4173sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function)
ab835497 4174{
b11b0904
EB		 4175 HOST_WIDE_INT frame_size, apparent_frame_size;
4176 int args_size, n_global_fp_regs = 0;
4177 bool save_local_in_regs_p = false;
4178 unsigned int i;
61a55e8b 4179
b11b0904
EB		 4180 /* If the function allocates dynamic stack space, the dynamic offset is
4181 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4182 if (leaf_function && !cfun->calls_alloca)
4183 args_size = 0;
33074e5f 4184 else
b11b0904 4185 args_size = crtl->outgoing_args_size + REG_PARM_STACK_SPACE (cfun->decl);
ab835497 4186
b11b0904
EB		 4187 /* Calculate space needed for global registers. */
4188 if (TARGET_ARCH64)
4189 for (i = 0; i < 8; i++)
4190 if (save_global_or_fp_reg_p (i, 0))
4191 n_global_fp_regs += 2;
4192 else
4193 for (i = 0; i < 8; i += 2)
4194 if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0))
4195 n_global_fp_regs += 2;
33074e5f 4196
b11b0904
EB		 4197 /* In the flat window model, find out which local and in registers need to
4198 be saved. We don't reserve space in the current frame for them as they
4199 will be spilled into the register window save area of the caller's frame.
4200 However, as soon as we use this register window save area, we must create
4201 that of the current frame to make it the live one. */
4202 if (TARGET_FLAT)
4203 for (i = 16; i < 32; i++)
4204 if (save_local_or_in_reg_p (i, leaf_function))
4205 {
4206 save_local_in_regs_p = true;
4207 break;
4208 }
ab835497 4209
b11b0904
EB		 4210 /* Calculate space needed for FP registers. */
4211 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4212 if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0))
4213 n_global_fp_regs += 2;
4214
4215 if (size == 0
4216 && n_global_fp_regs == 0
4217 && args_size == 0
4218 && !save_local_in_regs_p)
4219 frame_size = apparent_frame_size = 0;
61a55e8b
DE		 4220 else
4221 {
225909c3 4222 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
b11b0904
EB		 4223 apparent_frame_size = (size - STARTING_FRAME_OFFSET + 7) & -8;
4224 apparent_frame_size += n_global_fp_regs * 4;
4225
4226 /* We need to add the size of the outgoing argument area. */
4227 frame_size = apparent_frame_size + ((args_size + 7) & -8);
4228
4229 /* And that of the register window save area. */
4230 frame_size += FIRST_PARM_OFFSET (cfun->decl);
4231
4232 /* Finally, bump to the appropriate alignment. */
4233 frame_size = SPARC_STACK_ALIGN (frame_size);
61a55e8b 4234 }
ab835497 4235
b11b0904
EB		 4236 /* Set up values for use in prologue and epilogue. */
4237 sparc_frame_size = frame_size;
4238 sparc_apparent_frame_size = apparent_frame_size;
4239 sparc_n_global_fp_regs = n_global_fp_regs;
4240 sparc_save_local_in_regs_p = save_local_in_regs_p;
ab835497 4241
b11b0904 4242 return frame_size;
61a55e8b
DE		 4243}
4244
9ac617d4 4245/* Output any necessary .register pseudo-ops. */
61a55e8b 4246
9ac617d4
EB		 4247void
4248sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
61a55e8b 4249{
9ac617d4
EB		 4250#ifdef HAVE_AS_REGISTER_PSEUDO_OP
4251 int i;
6a151f87 4252
9ac617d4
EB		 4253 if (TARGET_ARCH32)
4254 return;
4255
4256 /* Check if %g[2367] were used without
4257 .register being printed for them already. */
4258 for (i = 2; i < 8; i++)
61a55e8b 4259 {
6fb5fa3c 4260 if (df_regs_ever_live_p (i)
9ac617d4
EB		 4261 && ! sparc_hard_reg_printed [i])
4262 {
4263 sparc_hard_reg_printed [i] = 1;
392e5756
JJ		 4264 /* %g7 is used as TLS base register, use #ignore
4265 for it instead of #scratch. */
4266 fprintf (file, "\t.register\t%%g%d, #%s\n", i,
4267 i == 7 ? "ignore" : "scratch");
9ac617d4
EB		 4268 }
4269 if (i == 3) i = 5;
61a55e8b 4270 }
6a151f87 4271#endif
9ac617d4 4272}
6a151f87 4273
260c8ba3
EB		 4274#define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
4275
4276#if PROBE_INTERVAL > 4096
4277#error Cannot use indexed addressing mode for stack probing
4278#endif
4279
4280/* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
4281 inclusive. These are offsets from the current stack pointer.
4282
4283 Note that we don't use the REG+REG addressing mode for the probes because
4284 of the stack bias in 64-bit mode. And it doesn't really buy us anything
4285 so the advantages of having a single code win here. */
4286
4287static void
4288sparc_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
4289{
4290 rtx g1 = gen_rtx_REG (Pmode, 1);
4291
4292 /* See if we have a constant small number of probes to generate. If so,
4293 that's the easy case. */
4294 if (size <= PROBE_INTERVAL)
4295 {
4296 emit_move_insn (g1, GEN_INT (first));
4297 emit_insn (gen_rtx_SET (VOIDmode, g1,
4298 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4299 emit_stack_probe (plus_constant (g1, -size));
4300 }
4301
4302 /* The run-time loop is made up of 10 insns in the generic case while the
4303 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
4304 else if (size <= 5 * PROBE_INTERVAL)
4305 {
4306 HOST_WIDE_INT i;
4307
4308 emit_move_insn (g1, GEN_INT (first + PROBE_INTERVAL));
4309 emit_insn (gen_rtx_SET (VOIDmode, g1,
4310 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4311 emit_stack_probe (g1);
4312
4313 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
4314 it exceeds SIZE. If only two probes are needed, this will not
4315 generate any code. Then probe at FIRST + SIZE. */
4316 for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
4317 {
4318 emit_insn (gen_rtx_SET (VOIDmode, g1,
4319 plus_constant (g1, -PROBE_INTERVAL)));
4320 emit_stack_probe (g1);
4321 }
4322
4323 emit_stack_probe (plus_constant (g1, (i - PROBE_INTERVAL) - size));
4324 }
4325
4326 /* Otherwise, do the same as above, but in a loop. Note that we must be
4327 extra careful with variables wrapping around because we might be at
4328 the very top (or the very bottom) of the address space and we have
4329 to be able to handle this case properly; in particular, we use an
4330 equality test for the loop condition. */
4331 else
4332 {
4333 HOST_WIDE_INT rounded_size;
4334 rtx g4 = gen_rtx_REG (Pmode, 4);
4335
4336 emit_move_insn (g1, GEN_INT (first));
4337
4338
4339 /* Step 1: round SIZE to the previous multiple of the interval. */
4340
4341 rounded_size = size & -PROBE_INTERVAL;
4342 emit_move_insn (g4, GEN_INT (rounded_size));
4343
4344
4345 /* Step 2: compute initial and final value of the loop counter. */
4346
4347 /* TEST_ADDR = SP + FIRST. */
4348 emit_insn (gen_rtx_SET (VOIDmode, g1,
4349 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4350
4351 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
4352 emit_insn (gen_rtx_SET (VOIDmode, g4, gen_rtx_MINUS (Pmode, g1, g4)));
4353
4354
4355 /* Step 3: the loop
4356
4357 while (TEST_ADDR != LAST_ADDR)
4358 {
4359 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
4360 probe at TEST_ADDR
4361 }
4362
4363 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
4364 until it is equal to ROUNDED_SIZE. */
4365
4366 if (TARGET_64BIT)
4367 emit_insn (gen_probe_stack_rangedi (g1, g1, g4));
4368 else
4369 emit_insn (gen_probe_stack_rangesi (g1, g1, g4));
4370
4371
4372 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
4373 that SIZE is equal to ROUNDED_SIZE. */
4374
4375 if (size != rounded_size)
4376 emit_stack_probe (plus_constant (g4, rounded_size - size));
4377 }
4378
4379 /* Make sure nothing is scheduled before we are done. */
4380 emit_insn (gen_blockage ());
4381}
4382
4383/* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
4384 absolute addresses. */
4385
4386const char *
4387output_probe_stack_range (rtx reg1, rtx reg2)
4388{
4389 static int labelno = 0;
4390 char loop_lab[32], end_lab[32];
4391 rtx xops[2];
4392
4393 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
4394 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
4395
4396 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
4397
4398 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
4399 xops[0] = reg1;
4400 xops[1] = reg2;
4401 output_asm_insn ("cmp\t%0, %1", xops);
4402 if (TARGET_ARCH64)
4403 fputs ("\tbe,pn\t%xcc,", asm_out_file);
4404 else
4405 fputs ("\tbe\t", asm_out_file);
4406 assemble_name_raw (asm_out_file, end_lab);
4407 fputc ('\n', asm_out_file);
4408
4409 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
4410 xops[1] = GEN_INT (-PROBE_INTERVAL);
4411 output_asm_insn (" add\t%0, %1, %0", xops);
4412
4413 /* Probe at TEST_ADDR and branch. */
4414 if (TARGET_ARCH64)
4415 fputs ("\tba,pt\t%xcc,", asm_out_file);
4416 else
4417 fputs ("\tba\t", asm_out_file);
4418 assemble_name_raw (asm_out_file, loop_lab);
4419 fputc ('\n', asm_out_file);
4420 xops[1] = GEN_INT (SPARC_STACK_BIAS);
4421 output_asm_insn (" st\t%%g0, [%0+%1]", xops);
4422
4423 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
4424
4425 return "";
4426}
4427
b11b0904
EB		 4428/* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
4429 needed. LOW is supposed to be double-word aligned for 32-bit registers.
4430 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
4431 is the action to be performed if SAVE_P returns true and ACTION_FALSE
4432 the action to be performed if it returns false. Return the new offset. */
6a151f87 4433
b11b0904
EB		 4434typedef bool (*sorr_pred_t) (unsigned int, int);
4435typedef enum { SORR_NONE, SORR_ADVANCE, SORR_SAVE, SORR_RESTORE } sorr_act_t;
9ac617d4
EB		 4436
4437static int
b11b0904
EB		 4438emit_save_or_restore_regs (unsigned int low, unsigned int high, rtx base,
4439 int offset, int leaf_function, sorr_pred_t save_p,
4440 sorr_act_t action_true, sorr_act_t action_false)
9ac617d4 4441{
b11b0904 4442 unsigned int i;
9ac617d4 4443 rtx mem, insn;
9ac617d4
EB		 4444
4445 if (TARGET_ARCH64 && high <= 32)
4446 {
b11b0904
EB		 4447 int fp_offset = -1;
4448
9ac617d4 4449 for (i = low; i < high; i++)
6a151f87 4450 {
b11b0904 4451 if (save_p (i, leaf_function))
9ac617d4 4452 {
114ce554 4453 mem = gen_frame_mem (DImode, plus_constant (base, offset));
b11b0904 4454 if (action_true == SORR_SAVE)
9ac617d4
EB		 4455 {
4456 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
4457 RTX_FRAME_RELATED_P (insn) = 1;
4458 }
b11b0904
EB		 4459 else /* action_true == SORR_RESTORE */
4460 {
4461 /* The frame pointer must be restored last since its old
4462 value may be used as base address for the frame. This
4463 is problematic in 64-bit mode only because of the lack
4464 of double-word load instruction. */
4465 if (i == HARD_FRAME_POINTER_REGNUM)
4466 fp_offset = offset;
4467 else
4468 emit_move_insn (gen_rtx_REG (DImode, i), mem);
4469 }
9ac617d4
EB		 4470 offset += 8;
4471 }
b11b0904
EB		 4472 else if (action_false == SORR_ADVANCE)
4473 offset += 8;
4474 }
4475
4476 if (fp_offset >= 0)
4477 {
4478 mem = gen_frame_mem (DImode, plus_constant (base, fp_offset));
4479 emit_move_insn (hard_frame_pointer_rtx, mem);
6a151f87 4480 }
9ac617d4
EB		 4481 }
4482 else
4483 {
4484 for (i = low; i < high; i += 2)
6a151f87 4485 {
b11b0904
EB		 4486 bool reg0 = save_p (i, leaf_function);
4487 bool reg1 = save_p (i + 1, leaf_function);
9ac617d4
EB		 4488 enum machine_mode mode;
4489 int regno;
4490
4491 if (reg0 && reg1)
4492 {
4493 mode = i < 32 ? DImode : DFmode;
4494 regno = i;
4495 }
4496 else if (reg0)
4497 {
4498 mode = i < 32 ? SImode : SFmode;
4499 regno = i;
4500 }
4501 else if (reg1)
4502 {
4503 mode = i < 32 ? SImode : SFmode;
4504 regno = i + 1;
4505 offset += 4;
4506 }
4507 else
b11b0904
EB		 4508 {
4509 if (action_false == SORR_ADVANCE)
4510 offset += 8;
4511 continue;
4512 }
9ac617d4 4513
114ce554 4514 mem = gen_frame_mem (mode, plus_constant (base, offset));
b11b0904 4515 if (action_true == SORR_SAVE)
9ac617d4
EB		 4516 {
4517 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4518 RTX_FRAME_RELATED_P (insn) = 1;
b11b0904
EB		 4519 if (mode == DImode)
4520 {
4521 rtx set1, set2;
4522 mem = gen_frame_mem (SImode, plus_constant (base, offset));
4523 set1 = gen_rtx_SET (VOIDmode, mem,
4524 gen_rtx_REG (SImode, regno));
4525 RTX_FRAME_RELATED_P (set1) = 1;
4526 mem
4527 = gen_frame_mem (SImode, plus_constant (base, offset + 4));
4528 set2 = gen_rtx_SET (VOIDmode, mem,
4529 gen_rtx_REG (SImode, regno + 1));
4530 RTX_FRAME_RELATED_P (set2) = 1;
4531 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4532 gen_rtx_PARALLEL (VOIDmode,
4533 gen_rtvec (2, set1, set2)));
4534 }
9ac617d4 4535 }
b11b0904 4536 else /* action_true == SORR_RESTORE */
9ac617d4
EB		 4537 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4538
4539 /* Always preserve double-word alignment. */
6d1e6c0f 4540 offset = (offset + 8) & -8;
6a151f87 4541 }
6a151f87 4542 }
9ac617d4
EB		 4543
4544 return offset;
ab835497
RK		 4545}
4546
b11b0904
EB		 4547/* Emit code to adjust BASE to OFFSET. Return the new base. */
4548
4549static rtx
4550emit_adjust_base_to_offset (rtx base, int offset)
4551{
4552 /* ??? This might be optimized a little as %g1 might already have a
4553 value close enough that a single add insn will do. */
4554 /* ??? Although, all of this is probably only a temporary fix because
4555 if %g1 can hold a function result, then sparc_expand_epilogue will
4556 lose (the result will be clobbered). */
4557 rtx new_base = gen_rtx_REG (Pmode, 1);
4558 emit_move_insn (new_base, GEN_INT (offset));
4559 emit_insn (gen_rtx_SET (VOIDmode,
4560 new_base, gen_rtx_PLUS (Pmode, base, new_base)));
4561 return new_base;
4562}
4563
4564/* Emit code to save/restore call-saved global and FP registers. */
9ac617d4
EB		 4565
4566static void
b11b0904 4567emit_save_or_restore_global_fp_regs (rtx base, int offset, sorr_act_t action)
1cb36a98 4568{
b11b0904
EB		 4569 if (offset < -4096 || offset + sparc_n_global_fp_regs * 4 > 4095)
4570 {
4571 base = emit_adjust_base_to_offset (base, offset);
4572 offset = 0;
4573 }
1cb36a98 4574
b11b0904
EB		 4575 offset
4576 = emit_save_or_restore_regs (0, 8, base, offset, 0,
4577 save_global_or_fp_reg_p, action, SORR_NONE);
4578 emit_save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, 0,
4579 save_global_or_fp_reg_p, action, SORR_NONE);
4580}
1cb36a98 4581
b11b0904
EB		 4582/* Emit code to save/restore call-saved local and in registers. */
4583
4584static void
4585emit_save_or_restore_local_in_regs (rtx base, int offset, sorr_act_t action)
4586{
4587 if (offset < -4096 || offset + 16 * UNITS_PER_WORD > 4095)
1cb36a98 4588 {
b11b0904 4589 base = emit_adjust_base_to_offset (base, offset);
9ac617d4 4590 offset = 0;
1cb36a98 4591 }
9ac617d4 4592
b11b0904
EB		 4593 emit_save_or_restore_regs (16, 32, base, offset, sparc_leaf_function_p,
4594 save_local_or_in_reg_p, action, SORR_ADVANCE);
9ac617d4 4595}
08c148a8 4596
e54c7471 4597/* Generate a save_register_window insn. */
08c148a8 4598
e54c7471
EB		 4599static rtx
4600gen_save_register_window (rtx increment)
08c148a8 4601{
9ac617d4 4602 if (TARGET_ARCH64)
e54c7471 4603 return gen_save_register_windowdi (increment);
9ac617d4 4604 else
e54c7471 4605 return gen_save_register_windowsi (increment);
08c148a8
NB		 4606}
4607
b11b0904
EB		 4608/* Generate a create_flat_frame_1 insn. */
4609
4610static rtx
4611gen_create_flat_frame_1 (rtx increment)
4612{
4613 if (TARGET_ARCH64)
4614 return gen_create_flat_frame_1di (increment);
4615 else
4616 return gen_create_flat_frame_1si (increment);
4617}
4618
4619/* Generate a create_flat_frame_2 insn. */
4620
4621static rtx
4622gen_create_flat_frame_2 (rtx increment)
4623{
4624 if (TARGET_ARCH64)
4625 return gen_create_flat_frame_2di (increment);
4626 else
4627 return gen_create_flat_frame_2si (increment);
4628}
4629
4630/* Generate a create_flat_frame_3 insn. */
4631
4632static rtx
4633gen_create_flat_frame_3 (rtx increment)
4634{
4635 if (TARGET_ARCH64)
4636 return gen_create_flat_frame_3di (increment);
4637 else
4638 return gen_create_flat_frame_3si (increment);
4639}
4640
e54c7471 4641/* Generate an increment for the stack pointer. */
915f619f 4642
e54c7471
EB		 4643static rtx
4644gen_stack_pointer_inc (rtx increment)
ab835497 4645{
6deb0339
EB		 4646 return gen_rtx_SET (VOIDmode,
4647 stack_pointer_rtx,
4648 gen_rtx_PLUS (Pmode,
4649 stack_pointer_rtx,
4650 increment));
e54c7471
EB		 4651}
4652
4653/* Generate a decrement for the stack pointer. */
4654
4655static rtx
4656gen_stack_pointer_dec (rtx decrement)
4657{
6deb0339
EB		 4658 return gen_rtx_SET (VOIDmode,
4659 stack_pointer_rtx,
4660 gen_rtx_MINUS (Pmode,
4661 stack_pointer_rtx,
4662 decrement));
9ac617d4
EB		 4663}
4664
4665/* Expand the function prologue. The prologue is responsible for reserving
4666 storage for the frame, saving the call-saved registers and loading the
a6fed83f 4667 GOT register if needed. */
9ac617d4
EB		 4668
4669void
4670sparc_expand_prologue (void)
4671{
b11b0904 4672 HOST_WIDE_INT size;
e54c7471
EB		 4673 rtx insn;
4674 int i;
4675
5be9b7a1
EB		 4676 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4677 on the final value of the flag means deferring the prologue/epilogue
4678 expansion until just before the second scheduling pass, which is too
4679 late to emit multiple epilogues or return insns.
4680
4681 Of course we are making the assumption that the value of the flag
4682 will not change between now and its final value. Of the three parts
4683 of the formula, only the last one can reasonably vary. Let's take a
4684 closer look, after assuming that the first two ones are set to true
4685 (otherwise the last value is effectively silenced).
4686
4687 If only_leaf_regs_used returns false, the global predicate will also
4688 be false so the actual frame size calculated below will be positive.
4689 As a consequence, the save_register_window insn will be emitted in
4690 the instruction stream; now this insn explicitly references %fp
4691 which is not a leaf register so only_leaf_regs_used will always
4692 return false subsequently.
4693
4694 If only_leaf_regs_used returns true, we hope that the subsequent
4695 optimization passes won't cause non-leaf registers to pop up. For
4696 example, the regrename pass has special provisions to not rename to
4697 non-leaf registers in a leaf function. */
4698 sparc_leaf_function_p
6d1e6c0f 4699 = optimize > 0 && current_function_is_leaf && only_leaf_regs_used ();
1cb36a98 4700
b11b0904 4701 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
ab835497 4702
a11e0df4 4703 if (flag_stack_usage_info)
b11b0904 4704 current_function_static_stack_size = size;
d3c12306 4705
b11b0904
EB		 4706 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && size)
4707 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
260c8ba3 4708
b11b0904
EB		 4709 if (size == 0)
4710 ; /* do nothing. */
5be9b7a1 4711 else if (sparc_leaf_function_p)
ab835497 4712 {
b11b0904
EB		 4713 if (size <= 4096)
4714 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-size)));
4715 else if (size <= 8192)
915f619f 4716 {
e54c7471
EB		 4717 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4718 /* %sp is still the CFA register. */
4719 RTX_FRAME_RELATED_P (insn) = 1;
b11b0904 4720 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
915f619f
JW		 4721 }
4722 else
4723 {
9ac617d4 4724 rtx reg = gen_rtx_REG (Pmode, 1);
b11b0904 4725 emit_move_insn (reg, GEN_INT (-size));
e54c7471 4726 insn = emit_insn (gen_stack_pointer_inc (reg));
bbbbb16a 4727 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
b11b0904 4728 gen_stack_pointer_inc (GEN_INT (-size)));
915f619f 4729 }
e54c7471
EB		 4730
4731 RTX_FRAME_RELATED_P (insn) = 1;
ab835497 4732 }
9ac617d4 4733 else
5f4241d5 4734 {
b11b0904
EB		 4735 if (size <= 4096)
4736 insn = emit_insn (gen_save_register_window (GEN_INT (-size)));
4737 else if (size <= 8192)
3592ea0d 4738 {
e54c7471
EB		 4739 insn = emit_insn (gen_save_register_window (GEN_INT (-4096)));
4740 /* %sp is not the CFA register anymore. */
b11b0904 4741 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
3592ea0d 4742 }
915f619f 4743 else
3592ea0d 4744 {
9ac617d4 4745 rtx reg = gen_rtx_REG (Pmode, 1);
b11b0904 4746 emit_move_insn (reg, GEN_INT (-size));
e54c7471 4747 insn = emit_insn (gen_save_register_window (reg));
3592ea0d 4748 }
e54c7471
EB		 4749
4750 RTX_FRAME_RELATED_P (insn) = 1;
4751 for (i=0; i < XVECLEN (PATTERN (insn), 0); i++)
4752 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, i)) = 1;
ab835497
RK		 4753 }
4754
b11b0904
EB		 4755 if (sparc_leaf_function_p)
4756 {
4757 sparc_frame_base_reg = stack_pointer_rtx;
4758 sparc_frame_base_offset = size + SPARC_STACK_BIAS;
4759 }
4760 else
4761 {
4762 sparc_frame_base_reg = hard_frame_pointer_rtx;
4763 sparc_frame_base_offset = SPARC_STACK_BIAS;
4764 }
4765
4766 if (sparc_n_global_fp_regs > 0)
4767 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
4768 sparc_frame_base_offset
4769 - sparc_apparent_frame_size,
4770 SORR_SAVE);
9ac617d4 4771
a6fed83f
EB		 4772 /* Load the GOT register if needed. */
4773 if (crtl->uses_pic_offset_table)
4774 load_got_register ();
b11b0904
EB		 4775
4776 /* Advertise that the data calculated just above are now valid. */
4777 sparc_prologue_data_valid_p = true;
4778}
4779
4780/* Expand the function prologue. The prologue is responsible for reserving
4781 storage for the frame, saving the call-saved registers and loading the
4782 GOT register if needed. */
4783
4784void
4785sparc_flat_expand_prologue (void)
4786{
4787 HOST_WIDE_INT size;
4788 rtx insn;
4789 int i;
4790
4791 sparc_leaf_function_p = optimize > 0 && current_function_is_leaf;
4792
4793 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
4794
4795 if (flag_stack_usage_info)
4796 current_function_static_stack_size = size;
4797
4798 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && size)
4799 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
4800
4801 if (sparc_save_local_in_regs_p)
4802 emit_save_or_restore_local_in_regs (stack_pointer_rtx, SPARC_STACK_BIAS,
4803 SORR_SAVE);
4804
4805 if (size == 0)
4806 ; /* do nothing. */
4807 else if (frame_pointer_needed)
4808 {
4809 if (size <= 4096)
4810 {
4811 if (return_addr_reg_needed_p (sparc_leaf_function_p))
4812 insn = emit_insn (gen_create_flat_frame_1 (GEN_INT (-size)));
4813 else
4814 insn = emit_insn (gen_create_flat_frame_2 (GEN_INT (-size)));
4815 RTX_FRAME_RELATED_P (insn) = 1;
4816 for (i=0; i < XVECLEN (PATTERN (insn), 0); i++)
4817 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, i)) = 1;
4818 }
4819 else
4820 {
4821 rtx reg = gen_rtx_REG (Pmode, 1), note;
4822 emit_move_insn (reg, GEN_INT (-size));
4823 if (return_addr_reg_needed_p (sparc_leaf_function_p))
4824 {
4825 insn = emit_insn (gen_create_flat_frame_1 (reg));
4826 note
4827 = gen_rtx_PARALLEL (VOIDmode,
4828 gen_rtvec
4829 (3, copy_rtx
4830 (XVECEXP (PATTERN (insn), 0, 0)),
4831 gen_stack_pointer_inc
4832 (GEN_INT (-size)),
4833 copy_rtx
4834 (XVECEXP (PATTERN (insn), 0, 2))));
4835 }
4836 else
4837 {
4838 insn = emit_insn (gen_create_flat_frame_2 (reg));
4839 note
4840 = gen_rtx_PARALLEL (VOIDmode,
4841 gen_rtvec
4842 (2, copy_rtx
4843 (XVECEXP (PATTERN (insn), 0, 0)),
4844 gen_stack_pointer_inc
4845 (GEN_INT (-size))));
4846 }
4847
4848 RTX_FRAME_RELATED_P (insn) = 1;
4849 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
4850 for (i=0; i < XVECLEN (note, 0); i++)
4851 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
4852 }
4853 }
4854 else if (return_addr_reg_needed_p (sparc_leaf_function_p))
4855 {
4856 if (size <= 4096)
4857 {
4858 insn = emit_insn (gen_create_flat_frame_3 (GEN_INT (-size)));
4859 RTX_FRAME_RELATED_P (insn) = 1;
4860 for (i=0; i < XVECLEN (PATTERN (insn), 0); i++)
4861 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, i)) = 1;
4862 }
4863 else
4864 {
4865 rtx reg = gen_rtx_REG (Pmode, 1), note;
4866 emit_move_insn (reg, GEN_INT (-size));
4867 insn = emit_insn (gen_create_flat_frame_3 (reg));
4868 note
4869 = gen_rtx_PARALLEL (VOIDmode,
4870 gen_rtvec
4871 (2, gen_stack_pointer_inc (GEN_INT (-size)),
4872 copy_rtx
4873 (XVECEXP (PATTERN (insn), 0, 1))));
4874 RTX_FRAME_RELATED_P (insn) = 1;
4875 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
4876 for (i=0; i < XVECLEN (note, 0); i++)
4877 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
4878 }
4879 }
4880 else
4881 {
4882 if (size <= 4096)
4883 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-size)));
4884 else if (size <= 8192)
4885 {
4886 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4887 RTX_FRAME_RELATED_P (insn) = 1;
4888 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
4889 }
4890 else
4891 {
4892 rtx reg = gen_rtx_REG (Pmode, 1);
4893 emit_move_insn (reg, GEN_INT (-size));
4894 insn = emit_insn (gen_stack_pointer_inc (reg));
4895 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4896 gen_stack_pointer_inc (GEN_INT (-size)));
4897 }
4898
4899 RTX_FRAME_RELATED_P (insn) = 1;
4900 }
4901
4902 /* Make sure nothing is scheduled until after the frame is established. */
4903 emit_insn (gen_blockage ());
4904
4905 if (frame_pointer_needed)
4906 {
4907 sparc_frame_base_reg = hard_frame_pointer_rtx;
4908 sparc_frame_base_offset = SPARC_STACK_BIAS;
4909 }
4910 else
4911 {
4912 sparc_frame_base_reg = stack_pointer_rtx;
4913 sparc_frame_base_offset = size + SPARC_STACK_BIAS;
4914 }
4915
4916 if (sparc_n_global_fp_regs > 0)
4917 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
4918 sparc_frame_base_offset
4919 - sparc_apparent_frame_size,
4920 SORR_SAVE);
4921
4922 /* Load the GOT register if needed. */
4923 if (crtl->uses_pic_offset_table)
4924 load_got_register ();
4925
4926 /* Advertise that the data calculated just above are now valid. */
4927 sparc_prologue_data_valid_p = true;
9ac617d4 4928}
4900aa61 4929
9ac617d4 4930/* This function generates the assembly code for function entry, which boils
f8ece000 4931 down to emitting the necessary .register directives. */
9ac617d4
EB		 4932
4933static void
4934sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4935{
5be9b7a1 4936 /* Check that the assumption we made in sparc_expand_prologue is valid. */
b11b0904
EB		 4937 if (!TARGET_FLAT)
4938 gcc_assert (sparc_leaf_function_p == current_function_uses_only_leaf_regs);
9ac617d4
EB		 4939
4940 sparc_output_scratch_registers (file);
9ac617d4
EB		 4941}
4942
4943/* Expand the function epilogue, either normal or part of a sibcall.
4944 We emit all the instructions except the return or the call. */
c53aa195 4945
9ac617d4 4946void
b11b0904 4947sparc_expand_epilogue (bool for_eh)
9ac617d4 4948{
b11b0904
EB		 4949 HOST_WIDE_INT size = sparc_frame_size;
4950
4951 if (sparc_n_global_fp_regs > 0)
4952 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
4953 sparc_frame_base_offset
4954 - sparc_apparent_frame_size,
4955 SORR_RESTORE);
ab835497 4956
b11b0904
EB		 4957 if (size == 0 || for_eh)
4958 ; /* do nothing. */
5be9b7a1 4959 else if (sparc_leaf_function_p)
9ac617d4 4960 {
b11b0904
EB		 4961 if (size <= 4096)
4962 emit_insn (gen_stack_pointer_dec (GEN_INT (-size)));
4963 else if (size <= 8192)
61a55e8b 4964 {
e54c7471 4965 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
b11b0904 4966 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size)));
61a55e8b 4967 }
ab835497 4968 else
61a55e8b 4969 {
9ac617d4 4970 rtx reg = gen_rtx_REG (Pmode, 1);
b11b0904
EB		 4971 emit_move_insn (reg, GEN_INT (-size));
4972 emit_insn (gen_stack_pointer_dec (reg));
4973 }
4974 }
4975}
4976
4977/* Expand the function epilogue, either normal or part of a sibcall.
4978 We emit all the instructions except the return or the call. */
4979
4980void
4981sparc_flat_expand_epilogue (bool for_eh)
4982{
4983 HOST_WIDE_INT size = sparc_frame_size;
4984
4985 if (sparc_n_global_fp_regs > 0)
4986 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
4987 sparc_frame_base_offset
4988 - sparc_apparent_frame_size,
4989 SORR_RESTORE);
4990
4991 /* If we have a frame pointer, we'll need both to restore it before the
4992 frame is destroyed and use its current value in destroying the frame.
4993 Since we don't have an atomic way to do that in the flat window model,
4994 we save the current value into a temporary register (%g1). */
4995 if (frame_pointer_needed && !for_eh)
4996 emit_move_insn (gen_rtx_REG (Pmode, 1), hard_frame_pointer_rtx);
4997
4998 if (return_addr_reg_needed_p (sparc_leaf_function_p))
4999 emit_move_insn (gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM),
5000 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM));
5001
5002 if (sparc_save_local_in_regs_p)
5003 emit_save_or_restore_local_in_regs (sparc_frame_base_reg,
5004 sparc_frame_base_offset,
5005 SORR_RESTORE);
5006
5007 if (size == 0 || for_eh)
5008 ; /* do nothing. */
5009 else if (frame_pointer_needed)
5010 {
5011 /* Make sure the frame is destroyed after everything else is done. */
5012 emit_insn (gen_blockage ());
5013
5014 emit_move_insn (stack_pointer_rtx, gen_rtx_REG (Pmode, 1));
5015 }
5016 else
5017 {
5018 /* Likewise. */
5019 emit_insn (gen_blockage ());
5020
5021 if (size <= 4096)
5022 emit_insn (gen_stack_pointer_dec (GEN_INT (-size)));
5023 else if (size <= 8192)
5024 {
5025 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5026 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size)));
5027 }
5028 else
5029 {
5030 rtx reg = gen_rtx_REG (Pmode, 1);
5031 emit_move_insn (reg, GEN_INT (-size));
e54c7471 5032 emit_insn (gen_stack_pointer_dec (reg));
61a55e8b 5033 }
ab835497
RK		 5034 }
5035}
5be9b7a1
EB		 5036
5037/* Return true if it is appropriate to emit `return' instructions in the
5038 body of a function. */
5039
5040bool
5041sparc_can_use_return_insn_p (void)
5042{
5043 return sparc_prologue_data_valid_p
b11b0904
EB		 5044 && sparc_n_global_fp_regs == 0
5045 && TARGET_FLAT
5046 ? (sparc_frame_size == 0 && !sparc_save_local_in_regs_p)
5047 : (sparc_frame_size == 0 || !sparc_leaf_function_p);
5be9b7a1 5048}
4900aa61 5049
9ac617d4 5050/* This function generates the assembly code for function exit. */
4900aa61 5051
9ac617d4
EB		 5052static void
5053sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5054{
891aa2ec
OH		 5055 /* If the last two instructions of a function are "call foo; dslot;"
5056 the return address might point to the first instruction in the next
5057 function and we have to output a dummy nop for the sake of sane
5058 backtraces in such cases. This is pointless for sibling calls since
5059 the return address is explicitly adjusted. */
ab835497 5060
9ac617d4 5061 rtx insn, last_real_insn;
7d167afd 5062
9ac617d4
EB		 5063 insn = get_last_insn ();
5064
5065 last_real_insn = prev_real_insn (insn);
5066 if (last_real_insn
5067 && GET_CODE (last_real_insn) == INSN
5068 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
5069 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
5070
891aa2ec
OH		 5071 if (last_real_insn
5072 && CALL_P (last_real_insn)
5073 && !SIBLING_CALL_P (last_real_insn))
9ac617d4
EB		 5074 fputs("\tnop\n", file);
5075
5076 sparc_output_deferred_case_vectors ();
5077}
4900aa61 5078
9ac617d4 5079/* Output a 'restore' instruction. */
4900aa61 5080
7d167afd 5081static void
6244b14e 5082output_restore (rtx pat)
7d167afd 5083{
6244b14e 5084 rtx operands[3];
7d167afd 5085
6244b14e 5086 if (! pat)
7d167afd 5087 {
9ac617d4
EB		 5088 fputs ("\t restore\n", asm_out_file);
5089 return;
7d167afd
JJ		 5090 }
5091
f5f7d171 5092 gcc_assert (GET_CODE (pat) == SET);
08c148a8 5093
9ac617d4
EB		 5094 operands[0] = SET_DEST (pat);
5095 pat = SET_SRC (pat);
08c148a8 5096
9ac617d4
EB		 5097 switch (GET_CODE (pat))
5098 {
5099 case PLUS:
5100 operands[1] = XEXP (pat, 0);
5101 operands[2] = XEXP (pat, 1);
5102 output_asm_insn (" restore %r1, %2, %Y0", operands);
5103 break;
5104 case LO_SUM:
5105 operands[1] = XEXP (pat, 0);
5106 operands[2] = XEXP (pat, 1);
5107 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
5108 break;
5109 case ASHIFT:
5110 operands[1] = XEXP (pat, 0);
f5f7d171 5111 gcc_assert (XEXP (pat, 1) == const1_rtx);
9ac617d4
EB		 5112 output_asm_insn (" restore %r1, %r1, %Y0", operands);
5113 break;
5114 default:
5115 operands[1] = pat;
5116 output_asm_insn (" restore %%g0, %1, %Y0", operands);
5117 break;
5118 }
08c148a8 5119}
4900aa61 5120
9ac617d4 5121/* Output a return. */
08c148a8 5122
9ac617d4
EB		 5123const char *
5124output_return (rtx insn)
ab835497 5125{
b11b0904
EB		 5126 if (crtl->calls_eh_return)
5127 {
5128 /* If the function uses __builtin_eh_return, the eh_return
5129 machinery occupies the delay slot. */
5130 gcc_assert (!final_sequence);
5131
5132 if (flag_delayed_branch)
5133 {
5134 if (!TARGET_FLAT && TARGET_V9)
5135 fputs ("\treturn\t%i7+8\n", asm_out_file);
5136 else
5137 {
5138 if (!TARGET_FLAT)
5139 fputs ("\trestore\n", asm_out_file);
5140
5141 fputs ("\tjmp\t%o7+8\n", asm_out_file);
5142 }
5143
5144 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
5145 }
5146 else
5147 {
5148 if (!TARGET_FLAT)
5149 fputs ("\trestore\n", asm_out_file);
5150
5151 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file);
5152 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file);
5153 }
5154 }
5155 else if (sparc_leaf_function_p || TARGET_FLAT)
e48addee 5156 {
b11b0904
EB		 5157 /* This is a leaf or flat function so we don't have to bother restoring
5158 the register window, which frees us from dealing with the convoluted
9ac617d4 5159 semantics of restore/return. We simply output the jump to the
4e5b002b 5160 return address and the insn in the delay slot (if any). */
7a31a340 5161
4e5b002b 5162 return "jmp\t%%o7+%)%#";
bfd6bc60 5163 }
ab835497 5164 else
ab835497 5165 {
9ac617d4
EB		 5166 /* This is a regular function so we have to restore the register window.
5167 We may have a pending insn for the delay slot, which will be either
5168 combined with the 'restore' instruction or put in the delay slot of
5169 the 'return' instruction. */
5170
b11b0904 5171 if (final_sequence)
ef8200df 5172 {
9ac617d4
EB		 5173 rtx delay, pat;
5174
5175 delay = NEXT_INSN (insn);
f5f7d171 5176 gcc_assert (delay);
1150a841 5177
9ac617d4
EB		 5178 pat = PATTERN (delay);
5179
5180 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
33074e5f 5181 {
9ac617d4 5182 epilogue_renumber (&pat, 0);
4e5b002b 5183 return "return\t%%i7+%)%#";
1150a841 5184 }
33074e5f 5185 else
ab835497 5186 {
4e5b002b 5187 output_asm_insn ("jmp\t%%i7+%)", NULL);
6244b14e 5188 output_restore (pat);
4e5b002b
EB		 5189 PATTERN (delay) = gen_blockage ();
5190 INSN_CODE (delay) = -1;
ab835497 5191 }
ef8200df 5192 }
33074e5f 5193 else
9ac617d4
EB		 5194 {
5195 /* The delay slot is empty. */
5196 if (TARGET_V9)
4e5b002b 5197 return "return\t%%i7+%)\n\t nop";
951661a1 5198 else if (flag_delayed_branch)
4e5b002b 5199 return "jmp\t%%i7+%)\n\t restore";
951661a1 5200 else
4e5b002b 5201 return "restore\n\tjmp\t%%o7+%)\n\t nop";
9ac617d4 5202 }
6a151f87 5203 }
e0d80184 5204
9ac617d4 5205 return "";
ab835497 5206}
7d167afd
JJ		 5207
5208/* Output a sibling call. */
5209
5210const char *
fc27d102 5211output_sibcall (rtx insn, rtx call_operand)
7d167afd 5212{
9ac617d4 5213 rtx operands[1];
7d167afd 5214
f5f7d171 5215 gcc_assert (flag_delayed_branch);
951661a1 5216
7d167afd
JJ		 5217 operands[0] = call_operand;
5218
b11b0904 5219 if (sparc_leaf_function_p || TARGET_FLAT)
7d167afd 5220 {
b11b0904
EB		 5221 /* This is a leaf or flat function so we don't have to bother restoring
5222 the register window. We simply output the jump to the function and
9ac617d4 5223 the insn in the delay slot (if any). */
7d167afd 5224
f5f7d171 5225 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence));
9ac617d4 5226
4e5b002b
EB		 5227 if (final_sequence)
5228 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
5229 operands);
7d167afd 5230 else
4e5b002b
EB		 5231 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
5232 it into branch if possible. */
5233 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
5234 operands);
7d167afd 5235 }
9ac617d4 5236 else
7d167afd 5237 {
9ac617d4
EB		 5238 /* This is a regular function so we have to restore the register window.
5239 We may have a pending insn for the delay slot, which will be combined
5240 with the 'restore' instruction. */
7d167afd 5241
9ac617d4 5242 output_asm_insn ("call\t%a0, 0", operands);
7d167afd 5243
4e5b002b 5244 if (final_sequence)
7d167afd 5245 {
9ac617d4 5246 rtx delay = NEXT_INSN (insn);
f5f7d171 5247 gcc_assert (delay);
9ac617d4 5248
6244b14e 5249 output_restore (PATTERN (delay));
9ac617d4
EB		 5250
5251 PATTERN (delay) = gen_blockage ();
5252 INSN_CODE (delay) = -1;
7d167afd 5253 }
9ac617d4 5254 else
6244b14e 5255 output_restore (NULL_RTX);
7d167afd 5256 }
9ac617d4 5257
7d167afd
JJ		 5258 return "";
5259}
4fb4e4b8
DE		 5260\f
5261/* Functions for handling argument passing.
5262
1b5963f7 5263 For 32-bit, the first 6 args are normally in registers and the rest are
4fb4e4b8
DE		 5264 pushed. Any arg that starts within the first 6 words is at least
5265 partially passed in a register unless its data type forbids.
5266
1b5963f7 5267 For 64-bit, the argument registers are laid out as an array of 16 elements
4fb4e4b8
DE		 5268 and arguments are added sequentially. The first 6 int args and up to the
5269 first 16 fp args (depending on size) are passed in regs.
5270
5271 Slot Stack Integral Float Float in structure Double Long Double
5272 ---- ----- -------- ----- ------------------ ------ -----------
5273 15 [SP+248] %f31 %f30,%f31 %d30
5274 14 [SP+240] %f29 %f28,%f29 %d28 %q28
5275 13 [SP+232] %f27 %f26,%f27 %d26
5276 12 [SP+224] %f25 %f24,%f25 %d24 %q24
5277 11 [SP+216] %f23 %f22,%f23 %d22
5278 10 [SP+208] %f21 %f20,%f21 %d20 %q20
5279 9 [SP+200] %f19 %f18,%f19 %d18
5280 8 [SP+192] %f17 %f16,%f17 %d16 %q16
5281 7 [SP+184] %f15 %f14,%f15 %d14
5282 6 [SP+176] %f13 %f12,%f13 %d12 %q12
5283 5 [SP+168] %o5 %f11 %f10,%f11 %d10
5284 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
5285 3 [SP+152] %o3 %f7 %f6,%f7 %d6
5286 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
5287 1 [SP+136] %o1 %f3 %f2,%f3 %d2
5288 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
5289
5290 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
5291
1b5963f7 5292 Integral arguments are always passed as 64-bit quantities appropriately
4fb4e4b8
DE		 5293 extended.
5294
5295 Passing of floating point values is handled as follows.
5296 If a prototype is in scope:
5297 If the value is in a named argument (i.e. not a stdarg function or a
5298 value not part of the `...') then the value is passed in the appropriate
5299 fp reg.
5300 If the value is part of the `...' and is passed in one of the first 6
5301 slots then the value is passed in the appropriate int reg.
5302 If the value is part of the `...' and is not passed in one of the first 6
5303 slots then the value is passed in memory.
5304 If a prototype is not in scope:
5305 If the value is one of the first 6 arguments the value is passed in the
5306 appropriate integer reg and the appropriate fp reg.
5307 If the value is not one of the first 6 arguments the value is passed in
5308 the appropriate fp reg and in memory.
1b5963f7
EB		 5309
5310
4900aa61 5311 Summary of the calling conventions implemented by GCC on the SPARC:
1b5963f7
EB		 5312
5313 32-bit ABI:
5314 size argument return value
5315
5316 small integer <4 int. reg. int. reg.
5317 word 4 int. reg. int. reg.
5318 double word 8 int. reg. int. reg.
5319
5320 _Complex small integer <8 int. reg. int. reg.
5321 _Complex word 8 int. reg. int. reg.
5322 _Complex double word 16 memory int. reg.
5323
5324 vector integer <=8 int. reg. FP reg.
5325 vector integer >8 memory memory
5326
5327 float 4 int. reg. FP reg.
5328 double 8 int. reg. FP reg.
5329 long double 16 memory memory
5330
5331 _Complex float 8 memory FP reg.
5332 _Complex double 16 memory FP reg.
5333 _Complex long double 32 memory FP reg.
5334
45261626 5335 vector float any memory memory
1b5963f7
EB		 5336
5337 aggregate any memory memory
5338
5339
5340
5341 64-bit ABI:
5342 size argument return value
5343
5344 small integer <8 int. reg. int. reg.
5345 word 8 int. reg. int. reg.
5346 double word 16 int. reg. int. reg.
5347
5348 _Complex small integer <16 int. reg. int. reg.
5349 _Complex word 16 int. reg. int. reg.
5350 _Complex double word 32 memory int. reg.
5351
5352 vector integer <=16 FP reg. FP reg.
5353 vector integer 16<s<=32 memory FP reg.
5354 vector integer >32 memory memory
5355
5356 float 4 FP reg. FP reg.
5357 double 8 FP reg. FP reg.
5358 long double 16 FP reg. FP reg.
5359
5360 _Complex float 8 FP reg. FP reg.
5361 _Complex double 16 FP reg. FP reg.
5362 _Complex long double 32 memory FP reg.
5363
5364 vector float <=16 FP reg. FP reg.
5365 vector float 16<s<=32 memory FP reg.
5366 vector float >32 memory memory
5367
5368 aggregate <=16 reg. reg.
5369 aggregate 16<s<=32 memory reg.
5370 aggregate >32 memory memory
5371
5372
5373
5374Note #1: complex floating-point types follow the extended SPARC ABIs as
5375implemented by the Sun compiler.
5376
5377Note #2: integral vector types follow the scalar floating-point types
5378conventions to match what is implemented by the Sun VIS SDK.
5379
4900aa61 5380Note #3: floating-point vector types follow the aggregate types
45261626 5381conventions. */
1b5963f7 5382
4fb4e4b8
DE		 5383
5384/* Maximum number of int regs for args. */
5385#define SPARC_INT_ARG_MAX 6
5386/* Maximum number of fp regs for args. */
5387#define SPARC_FP_ARG_MAX 16
5388
5389#define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5390
5391/* Handle the INIT_CUMULATIVE_ARGS macro.
5392 Initialize a variable CUM of type CUMULATIVE_ARGS
5393 for a call to a function whose data type is FNTYPE.
5394 For a library call, FNTYPE is 0. */
3ea1fdd3 5395
4fb4e4b8 5396void
fc27d102
KG		 5397init_cumulative_args (struct sparc_args *cum, tree fntype,
5398 rtx libname ATTRIBUTE_UNUSED,
5399 tree fndecl ATTRIBUTE_UNUSED)
4fb4e4b8
DE		 5400{
5401 cum->words = 0;
f4da8dce 5402 cum->prototype_p = fntype && prototype_p (fntype);
4fb4e4b8
DE		 5403 cum->libcall_p = fntype == 0;
5404}
61a55e8b 5405
cde0f3fd
PB		 5406/* Handle promotion of pointer and integer arguments. */
5407
5408static enum machine_mode
5e617be8 5409sparc_promote_function_mode (const_tree type,
cde0f3fd 5410 enum machine_mode mode,
5e617be8 5411 int *punsignedp,
cde0f3fd
PB		 5412 const_tree fntype ATTRIBUTE_UNUSED,
5413 int for_return ATTRIBUTE_UNUSED)
5414{
5e617be8 5415 if (type != NULL_TREE && POINTER_TYPE_P (type))
cde0f3fd
PB		 5416 {
5417 *punsignedp = POINTERS_EXTEND_UNSIGNED;
5418 return Pmode;
5419 }
5420
f79e1b0f
EB		 5421 /* Integral arguments are passed as full words, as per the ABI. */
5422 if (GET_MODE_CLASS (mode) == MODE_INT
cde0f3fd
PB		 5423 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5424 return word_mode;
5425
5426 return mode;
5427}
5428
bd5bd7ac 5429/* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
3e2cc1d1
KH		 5430
5431static bool
d5cc9181 5432sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
3e2cc1d1 5433{
1b5963f7 5434 return TARGET_ARCH64 ? true : false;
3e2cc1d1
KH		 5435}
5436
5c4f4b18
EB		 5437/* Scan the record type TYPE and return the following predicates:
5438 - INTREGS_P: the record contains at least one field or sub-field
5439 that is eligible for promotion in integer registers.
5440 - FP_REGS_P: the record contains at least one field or sub-field
5441 that is eligible for promotion in floating-point registers.
5442 - PACKED_P: the record contains at least one field that is packed.
5443
5444 Sub-fields are not taken into account for the PACKED_P predicate. */
5445
5446static void
9adafb9f
NF		 5447scan_record_type (const_tree type, int *intregs_p, int *fpregs_p,
5448 int *packed_p)
5c4f4b18
EB		 5449{
5450 tree field;
5451
910ad8de 5452 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5c4f4b18
EB		 5453 {
5454 if (TREE_CODE (field) == FIELD_DECL)
5455 {
5456 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5457 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
45261626
EB		 5458 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5459 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5460 && TARGET_FPU)
5c4f4b18
EB		 5461 *fpregs_p = 1;
5462 else
5463 *intregs_p = 1;
5464
5465 if (packed_p && DECL_PACKED (field))
5466 *packed_p = 1;
5467 }
5468 }
5469}
5470
4fb4e4b8 5471/* Compute the slot number to pass an argument in.
5c4f4b18 5472 Return the slot number or -1 if passing on the stack.
4fb4e4b8
DE		 5473
5474 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5475 the preceding args and about the function being called.
5476 MODE is the argument's machine mode.
5477 TYPE is the data type of the argument (as a tree).
5478 This is null for libcalls where that information may
5479 not be available.
5480 NAMED is nonzero if this argument is a named parameter
5481 (otherwise it is an extra parameter matching an ellipsis).
5482 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5483 *PREGNO records the register number to use if scalar type.
5484 *PPADDING records the amount of padding needed in words. */
5485
5486static int
fc27d102 5487function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
9adafb9f 5488 const_tree type, bool named, bool incoming_p,
fc27d102 5489 int *pregno, int *ppadding)
4fb4e4b8
DE		 5490{
5491 int regbase = (incoming_p
5492 ? SPARC_INCOMING_INT_ARG_FIRST
5493 : SPARC_OUTGOING_INT_ARG_FIRST);
5494 int slotno = cum->words;
45261626 5495 enum mode_class mclass;
4fb4e4b8
DE		 5496 int regno;
5497
5498 *ppadding = 0;
5499
1b5963f7 5500 if (type && TREE_ADDRESSABLE (type))
4fb4e4b8 5501 return -1;
1b5963f7 5502
4fb4e4b8 5503 if (TARGET_ARCH32
1b5963f7
EB		 5504 && mode == BLKmode
5505 && type
4fb4e4b8
DE		 5506 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5507 return -1;
5508
1b5963f7
EB		 5509 /* For SPARC64, objects requiring 16-byte alignment get it. */
5510 if (TARGET_ARCH64
7617ec02 5511 && (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128
1b5963f7
EB		 5512 && (slotno & 1) != 0)
5513 slotno++, *ppadding = 1;
4fb4e4b8 5514
45261626
EB		 5515 mclass = GET_MODE_CLASS (mode);
5516 if (type && TREE_CODE (type) == VECTOR_TYPE)
5517 {
5518 /* Vector types deserve special treatment because they are
5519 polymorphic wrt their mode, depending upon whether VIS
5520 instructions are enabled. */
5521 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
5522 {
5523 /* The SPARC port defines no floating-point vector modes. */
f5f7d171 5524 gcc_assert (mode == BLKmode);
45261626
EB		 5525 }
5526 else
5527 {
5528 /* Integral vector types should either have a vector
5529 mode or an integral mode, because we are guaranteed
5530 by pass_by_reference that their size is not greater
5531 than 16 bytes and TImode is 16-byte wide. */
f5f7d171 5532 gcc_assert (mode != BLKmode);
45261626
EB		 5533
5534 /* Vector integers are handled like floats according to
5535 the Sun VIS SDK. */
5536 mclass = MODE_FLOAT;
5537 }
5538 }
5539
5540 switch (mclass)
1b5963f7
EB		 5541 {
5542 case MODE_FLOAT:
5543 case MODE_COMPLEX_FLOAT:
0dd8c9bc 5544 case MODE_VECTOR_INT:
1b5963f7
EB		 5545 if (TARGET_ARCH64 && TARGET_FPU && named)
5546 {
5547 if (slotno >= SPARC_FP_ARG_MAX)
5548 return -1;
5549 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5550 /* Arguments filling only one single FP register are
5551 right-justified in the outer double FP register. */
5552 if (GET_MODE_SIZE (mode) <= 4)
5553 regno++;
5554 break;
5555 }
d560b0aa
EB		 5556 /* fallthrough */
5557
1b5963f7
EB		 5558 case MODE_INT:
5559 case MODE_COMPLEX_INT:
4fb4e4b8
DE		 5560 if (slotno >= SPARC_INT_ARG_MAX)
5561 return -1;
5562 regno = regbase + slotno;
5563 break;
5564
1b5963f7
EB		 5565 case MODE_RANDOM:
5566 if (mode == VOIDmode)
5567 /* MODE is VOIDmode when generating the actual call. */
5568 return -1;
d560b0aa 5569
f5f7d171 5570 gcc_assert (mode == BLKmode);
4fb4e4b8 5571
ef6843ed
EB		 5572 if (TARGET_ARCH32
5573 || !type
5574 || (TREE_CODE (type) != VECTOR_TYPE
5575 && TREE_CODE (type) != RECORD_TYPE))
4fb4e4b8
DE		 5576 {
5577 if (slotno >= SPARC_INT_ARG_MAX)
5578 return -1;
5579 regno = regbase + slotno;
5580 }
45261626 5581 else /* TARGET_ARCH64 && type */
4fb4e4b8 5582 {
5c4f4b18
EB		 5583 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5584
5585 /* First see what kinds of registers we would need. */
45261626
EB		 5586 if (TREE_CODE (type) == VECTOR_TYPE)
5587 fpregs_p = 1;
5588 else
5589 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5c4f4b18
EB		 5590
5591 /* The ABI obviously doesn't specify how packed structures
5592 are passed. These are defined to be passed in int regs
5593 if possible, otherwise memory. */
4fb4e4b8
DE		 5594 if (packed_p || !named)
5595 fpregs_p = 0, intregs_p = 1;
5596
5597 /* If all arg slots are filled, then must pass on stack. */
5598 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5599 return -1;
1b5963f7 5600
4fb4e4b8
DE		 5601 /* If there are only int args and all int arg slots are filled,
5602 then must pass on stack. */
5603 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5604 return -1;
1b5963f7 5605
4fb4e4b8
DE		 5606 /* Note that even if all int arg slots are filled, fp members may
5607 still be passed in regs if such regs are available.
5608 *PREGNO isn't set because there may be more than one, it's up
5609 to the caller to compute them. */
5610 return slotno;
5611 }
5612 break;
5613
5614 default :
f5f7d171 5615 gcc_unreachable ();
4fb4e4b8
DE		 5616 }
5617
5618 *pregno = regno;
5619 return slotno;
5620}
5621
82d6b402
RH		 5622/* Handle recursive register counting for structure field layout. */
5623
5624struct function_arg_record_value_parms
5625{
48028e21
EB		 5626 rtx ret; /* return expression being built. */
5627 int slotno; /* slot number of the argument. */
5628 int named; /* whether the argument is named. */
5629 int regbase; /* regno of the base register. */
5630 int stack; /* 1 if part of the argument is on the stack. */
1fd05073 5631 int intoffset; /* offset of the first pending integer field. */
48028e21 5632 unsigned int nregs; /* number of words passed in registers. */
82d6b402
RH		 5633};
5634
2a01c939 5635static void function_arg_record_value_3
e80d5f80 5636 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
2a01c939 5637static void function_arg_record_value_2
586de218 5638 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
b1474bb7 5639static void function_arg_record_value_1
586de218
KG		 5640 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5641static rtx function_arg_record_value (const_tree, enum machine_mode, int, int, int);
22d8d627 5642static rtx function_arg_union_value (int, enum machine_mode, int, int);
2a01c939 5643
0020b823 5644/* A subroutine of function_arg_record_value. Traverse the structure
fae778eb 5645 recursively and determine how many registers will be required. */
0020b823 5646
82d6b402 5647static void
586de218 5648function_arg_record_value_1 (const_tree type, HOST_WIDE_INT startbitpos,
cde85594
EB		 5649 struct function_arg_record_value_parms *parms,
5650 bool packed_p)
82d6b402
RH		 5651{
5652 tree field;
5653
82d6b402
RH		 5654 /* We need to compute how many registers are needed so we can
5655 allocate the PARALLEL but before we can do that we need to know
cde85594
EB		 5656 whether there are any packed fields. The ABI obviously doesn't
5657 specify how structures are passed in this case, so they are
5658 defined to be passed in int regs if possible, otherwise memory,
5659 regardless of whether there are fp values present. */
5660
5661 if (! packed_p)
5662 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5663 {
5664 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5665 {
5666 packed_p = true;
5667 break;
5668 }
5669 }
82d6b402
RH		 5670
5671 /* Compute how many registers we need. */
910ad8de 5672 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
82d6b402
RH		 5673 {
5674 if (TREE_CODE (field) == FIELD_DECL)
5675 {
75131237
RK		 5676 HOST_WIDE_INT bitpos = startbitpos;
5677
bb05e341
EB		 5678 if (DECL_SIZE (field) != 0)
5679 {
5680 if (integer_zerop (DECL_SIZE (field)))
5681 continue;
5682
5683 if (host_integerp (bit_position (field), 1))
5684 bitpos += int_bit_position (field);
5685 }
75131237 5686
82d6b402
RH		 5687 /* ??? FIXME: else assume zero offset. */
5688
5689 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
cde85594
EB		 5690 function_arg_record_value_1 (TREE_TYPE (field),
5691 bitpos,
5692 parms,
5693 packed_p);
1b5963f7
EB		 5694 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5695 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
8a98812c
EB		 5696 && TARGET_FPU
5697 && parms->named
5698 && ! packed_p)
82d6b402
RH		 5699 {
5700 if (parms->intoffset != -1)
5701 {
b2f24c85 5702 unsigned int startbit, endbit;
82d6b402
RH		 5703 int intslots, this_slotno;
5704
b2f24c85
EB		 5705 startbit = parms->intoffset & -BITS_PER_WORD;
5706 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5707
5708 intslots = (endbit - startbit) / BITS_PER_WORD;
82d6b402
RH		 5709 this_slotno = parms->slotno + parms->intoffset
5710 / BITS_PER_WORD;
5711
48028e21
EB		 5712 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5713 {
5714 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5715 /* We need to pass this field on the stack. */
5716 parms->stack = 1;
5717 }
5718
82d6b402
RH		 5719 parms->nregs += intslots;
5720 parms->intoffset = -1;
5721 }
5722
5723 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5724 If it wasn't true we wouldn't be here. */
45261626
EB		 5725 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
5726 && DECL_MODE (field) == BLKmode)
5727 parms->nregs += TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
5728 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5729 parms->nregs += 2;
5730 else
105b2084 5731 parms->nregs += 1;
82d6b402
RH		 5732 }
5733 else
5734 {
5735 if (parms->intoffset == -1)
5736 parms->intoffset = bitpos;
5737 }
5738 }
5739 }
5740}
5741
0020b823
RH		 5742/* A subroutine of function_arg_record_value. Assign the bits of the
5743 structure between parms->intoffset and bitpos to integer registers. */
82d6b402 5744
4900aa61 5745static void
fc27d102
KG		 5746function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5747 struct function_arg_record_value_parms *parms)
82d6b402
RH		 5748{
5749 enum machine_mode mode;
75131237 5750 unsigned int regno;
0020b823 5751 unsigned int startbit, endbit;
75131237 5752 int this_slotno, intslots, intoffset;
82d6b402
RH		 5753 rtx reg;
5754
5755 if (parms->intoffset == -1)
5756 return;
75131237 5757
82d6b402
RH		 5758 intoffset = parms->intoffset;
5759 parms->intoffset = -1;
5760
0020b823
RH		 5761 startbit = intoffset & -BITS_PER_WORD;
5762 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5763 intslots = (endbit - startbit) / BITS_PER_WORD;
82d6b402
RH		 5764 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5765
5766 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5767 if (intslots <= 0)
5768 return;
5769
5770 /* If this is the trailing part of a word, only load that much into
5771 the register. Otherwise load the whole register. Note that in
5772 the latter case we may pick up unwanted bits. It's not a problem
5773 at the moment but may wish to revisit. */
5774
5775 if (intoffset % BITS_PER_WORD != 0)
bb05e341
EB		 5776 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5777 MODE_INT);
82d6b402
RH		 5778 else
5779 mode = word_mode;
5780
5781 intoffset /= BITS_PER_UNIT;
5782 do
5783 {
5784 regno = parms->regbase + this_slotno;
254110c2 5785 reg = gen_rtx_REG (mode, regno);
48028e21 5786 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
254110c2 5787 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
82d6b402
RH		 5788
5789 this_slotno += 1;
5790 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
1fd05073 5791 mode = word_mode;
82d6b402
RH		 5792 parms->nregs += 1;
5793 intslots -= 1;
5794 }
5795 while (intslots > 0);
5796}
5797
0020b823
RH		 5798/* A subroutine of function_arg_record_value. Traverse the structure
5799 recursively and assign bits to floating point registers. Track which
5800 bits in between need integer registers; invoke function_arg_record_value_3
5801 to make that happen. */
5802
82d6b402 5803static void
586de218 5804function_arg_record_value_2 (const_tree type, HOST_WIDE_INT startbitpos,
cde85594
EB		 5805 struct function_arg_record_value_parms *parms,
5806 bool packed_p)
82d6b402
RH		 5807{
5808 tree field;
82d6b402 5809
cde85594 5810 if (! packed_p)
910ad8de 5811 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
cde85594
EB		 5812 {
5813 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5814 {
5815 packed_p = true;
5816 break;
5817 }
5818 }
82d6b402 5819
910ad8de 5820 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
82d6b402
RH		 5821 {
5822 if (TREE_CODE (field) == FIELD_DECL)
5823 {
75131237
RK		 5824 HOST_WIDE_INT bitpos = startbitpos;
5825
bb05e341
EB		 5826 if (DECL_SIZE (field) != 0)
5827 {
5828 if (integer_zerop (DECL_SIZE (field)))
5829 continue;
5830
5831 if (host_integerp (bit_position (field), 1))
5832 bitpos += int_bit_position (field);
5833 }
75131237 5834
82d6b402
RH		 5835 /* ??? FIXME: else assume zero offset. */
5836
5837 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
cde85594
EB		 5838 function_arg_record_value_2 (TREE_TYPE (field),
5839 bitpos,
5840 parms,
5841 packed_p);
1b5963f7
EB		 5842 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5843 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
8a98812c
EB		 5844 && TARGET_FPU
5845 && parms->named
5846 && ! packed_p)
82d6b402
RH		 5847 {
5848 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
45261626 5849 int regno, nregs, pos;
105b2084 5850 enum machine_mode mode = DECL_MODE (field);
82d6b402
RH		 5851 rtx reg;
5852
5853 function_arg_record_value_3 (bitpos, parms);
45261626
EB		 5854
5855 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
5856 && mode == BLKmode)
5857 {
5858 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
5859 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
105b2084 5860 }
45261626
EB		 5861 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5862 {
5863 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
5864 nregs = 2;
5865 }
5866 else
5867 nregs = 1;
5868
1b5963f7
EB		 5869 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
5870 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
5871 regno++;
105b2084 5872 reg = gen_rtx_REG (mode, regno);
45261626 5873 pos = bitpos / BITS_PER_UNIT;
48028e21 5874 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
45261626 5875 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
82d6b402 5876 parms->nregs += 1;
45261626 5877 while (--nregs > 0)
105b2084
JJ		 5878 {
5879 regno += GET_MODE_SIZE (mode) / 4;
5880 reg = gen_rtx_REG (mode, regno);
45261626 5881 pos += GET_MODE_SIZE (mode);
48028e21 5882 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
45261626 5883 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
105b2084
JJ		 5884 parms->nregs += 1;
5885 }
82d6b402
RH		 5886 }
5887 else
5888 {
5889 if (parms->intoffset == -1)
5890 parms->intoffset = bitpos;
5891 }
5892 }
5893 }
5894}
5895
bf44d792 5896/* Used by function_arg and sparc_function_value_1 to implement the complex
48028e21 5897 conventions of the 64-bit ABI for passing and returning structures.
bf44d792
AS		 5898 Return an expression valid as a return value for the FUNCTION_ARG
5899 and TARGET_FUNCTION_VALUE.
0020b823 5900
48028e21
EB		 5901 TYPE is the data type of the argument (as a tree).
5902 This is null for libcalls where that information may
5903 not be available.
5904 MODE is the argument's machine mode.
5905 SLOTNO is the index number of the argument's slot in the parameter array.
5906 NAMED is nonzero if this argument is a named parameter
5907 (otherwise it is an extra parameter matching an ellipsis).
5908 REGBASE is the regno of the base register for the parameter array. */
4900aa61 5909
82d6b402 5910static rtx
586de218 5911function_arg_record_value (const_tree type, enum machine_mode mode,
fc27d102 5912 int slotno, int named, int regbase)
82d6b402
RH		 5913{
5914 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5915 struct function_arg_record_value_parms parms;
75131237 5916 unsigned int nregs;
82d6b402
RH		 5917
5918 parms.ret = NULL_RTX;
5919 parms.slotno = slotno;
5920 parms.named = named;
5921 parms.regbase = regbase;
48028e21 5922 parms.stack = 0;
82d6b402
RH		 5923
5924 /* Compute how many registers we need. */
5925 parms.nregs = 0;
5926 parms.intoffset = 0;
cde85594 5927 function_arg_record_value_1 (type, 0, &parms, false);
82d6b402 5928
1fd05073 5929 /* Take into account pending integer fields. */
82d6b402
RH		 5930 if (parms.intoffset != -1)
5931 {
0020b823 5932 unsigned int startbit, endbit;
82d6b402
RH		 5933 int intslots, this_slotno;
5934
0020b823
RH		 5935 startbit = parms.intoffset & -BITS_PER_WORD;
5936 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5937 intslots = (endbit - startbit) / BITS_PER_WORD;
82d6b402
RH		 5938 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5939
48028e21
EB		 5940 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5941 {
5942 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5943 /* We need to pass this field on the stack. */
5944 parms.stack = 1;
5945 }
82d6b402
RH		 5946
5947 parms.nregs += intslots;
5948 }
5949 nregs = parms.nregs;
5950
5951 /* Allocate the vector and handle some annoying special cases. */
5952 if (nregs == 0)
5953 {
5954 /* ??? Empty structure has no value? Duh? */
5955 if (typesize <= 0)
5956 {
5957 /* Though there's nothing really to store, return a word register
5958 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5959 leads to breakage due to the fact that there are zero bytes to
5960 load. */
1eac9f59 5961 return gen_rtx_REG (mode, regbase);
82d6b402
RH		 5962 }
5963 else
5964 {
5965 /* ??? C++ has structures with no fields, and yet a size. Give up
5966 for now and pass everything back in integer registers. */
5967 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5968 }
5969 if (nregs + slotno > SPARC_INT_ARG_MAX)
5970 nregs = SPARC_INT_ARG_MAX - slotno;
5971 }
f5f7d171 5972 gcc_assert (nregs != 0);
82d6b402 5973
48028e21
EB		 5974 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5975
5976 /* If at least one field must be passed on the stack, generate
5977 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5978 also be passed on the stack. We can't do much better because the
78a52f11 5979 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
48028e21
EB		 5980 of structures for which the fields passed exclusively in registers
5981 are not at the beginning of the structure. */
5982 if (parms.stack)
5983 XVECEXP (parms.ret, 0, 0)
5984 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
82d6b402
RH		 5985
5986 /* Fill in the entries. */
5987 parms.nregs = 0;
5988 parms.intoffset = 0;
cde85594 5989 function_arg_record_value_2 (type, 0, &parms, false);
82d6b402
RH		 5990 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5991
f5f7d171 5992 gcc_assert (parms.nregs == nregs);
82d6b402
RH		 5993
5994 return parms.ret;
5995}
5996
bf44d792 5997/* Used by function_arg and sparc_function_value_1 to implement the conventions
a7bba6ca 5998 of the 64-bit ABI for passing and returning unions.
bf44d792
AS		 5999 Return an expression valid as a return value for the FUNCTION_ARG
6000 and TARGET_FUNCTION_VALUE.
a7bba6ca
EB		 6001
6002 SIZE is the size in bytes of the union.
85bbb21f 6003 MODE is the argument's machine mode.
a7bba6ca
EB		 6004 REGNO is the hard register the union will be passed in. */
6005
6006static rtx
22d8d627
EB		 6007function_arg_union_value (int size, enum machine_mode mode, int slotno,
6008 int regno)
a7bba6ca 6009{
85bbb21f
EB		 6010 int nwords = ROUND_ADVANCE (size), i;
6011 rtx regs;
a7bba6ca 6012
bb05e341
EB		 6013 /* See comment in previous function for empty structures. */
6014 if (nwords == 0)
6015 return gen_rtx_REG (mode, regno);
6016
22d8d627
EB		 6017 if (slotno == SPARC_INT_ARG_MAX - 1)
6018 nwords = 1;
6019
85bbb21f 6020 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
a7bba6ca 6021
85bbb21f 6022 for (i = 0; i < nwords; i++)
45261626
EB		 6023 {
6024 /* Unions are passed left-justified. */
6025 XVECEXP (regs, 0, i)
6026 = gen_rtx_EXPR_LIST (VOIDmode,
6027 gen_rtx_REG (word_mode, regno),
6028 GEN_INT (UNITS_PER_WORD * i));
6029 regno++;
6030 }
6031
6032 return regs;
6033}
6034
bf44d792 6035/* Used by function_arg and sparc_function_value_1 to implement the conventions
45261626 6036 for passing and returning large (BLKmode) vectors.
bf44d792
AS		 6037 Return an expression valid as a return value for the FUNCTION_ARG
6038 and TARGET_FUNCTION_VALUE.
45261626 6039
26237a50 6040 SIZE is the size in bytes of the vector (at least 8 bytes).
45261626
EB		 6041 REGNO is the FP hard register the vector will be passed in. */
6042
6043static rtx
26237a50 6044function_arg_vector_value (int size, int regno)
45261626 6045{
26237a50 6046 int i, nregs = size / 8;
45261626
EB		 6047 rtx regs;
6048
6049 regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
6050
6051 for (i = 0; i < nregs; i++)
6052 {
6053 XVECEXP (regs, 0, i)
6054 = gen_rtx_EXPR_LIST (VOIDmode,
26237a50
EB		 6055 gen_rtx_REG (DImode, regno + 2*i),
6056 GEN_INT (i*8));
45261626 6057 }
a7bba6ca 6058
85bbb21f 6059 return regs;
a7bba6ca
EB		 6060}
6061
9adafb9f 6062/* Determine where to put an argument to a function.
4fb4e4b8
DE		 6063 Value is zero to push the argument on the stack,
6064 or a hard register in which to store the argument.
6065
6066 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6067 the preceding args and about the function being called.
6068 MODE is the argument's machine mode.
6069 TYPE is the data type of the argument (as a tree).
6070 This is null for libcalls where that information may
6071 not be available.
9adafb9f 6072 NAMED is true if this argument is a named parameter
4fb4e4b8 6073 (otherwise it is an extra parameter matching an ellipsis).
9adafb9f
NF		 6074 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6075 TARGET_FUNCTION_INCOMING_ARG. */
61a55e8b 6076
9adafb9f 6077static rtx
d5cc9181 6078sparc_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode,
9adafb9f 6079 const_tree type, bool named, bool incoming_p)
61a55e8b 6080{
d5cc9181
JR		 6081 const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6082
4fb4e4b8
DE		 6083 int regbase = (incoming_p
6084 ? SPARC_INCOMING_INT_ARG_FIRST
6085 : SPARC_OUTGOING_INT_ARG_FIRST);
6086 int slotno, regno, padding;
45261626 6087 enum mode_class mclass = GET_MODE_CLASS (mode);
4fb4e4b8
DE		 6088
6089 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
6090 &regno, &padding);
4fb4e4b8
DE		 6091 if (slotno == -1)
6092 return 0;
6093
ef6843ed
EB		 6094 /* Vector types deserve special treatment because they are polymorphic wrt
6095 their mode, depending upon whether VIS instructions are enabled. */
6096 if (type && TREE_CODE (type) == VECTOR_TYPE)
4fb4e4b8 6097 {
ef6843ed
EB		 6098 HOST_WIDE_INT size = int_size_in_bytes (type);
6099 gcc_assert ((TARGET_ARCH32 && size <= 8)
6100 || (TARGET_ARCH64 && size <= 16));
6101
6102 if (mode == BLKmode)
6103 return function_arg_vector_value (size,
ef6843ed
EB		 6104 SPARC_FP_ARG_FIRST + 2*slotno);
6105 else
6106 mclass = MODE_FLOAT;
4fb4e4b8 6107 }
4043d6fb 6108
ef6843ed
EB		 6109 if (TARGET_ARCH32)
6110 return gen_rtx_REG (mode, regno);
4043d6fb 6111
ef6843ed
EB		 6112 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6113 and are promoted to registers if possible. */
6114 if (type && TREE_CODE (type) == RECORD_TYPE)
4043d6fb 6115 {
a7bba6ca 6116 HOST_WIDE_INT size = int_size_in_bytes (type);
f5f7d171 6117 gcc_assert (size <= 16);
4fb4e4b8 6118
ef6843ed 6119 return function_arg_record_value (type, mode, slotno, named, regbase);
4043d6fb 6120 }
ef6843ed
EB		 6121
6122 /* Unions up to 16 bytes in size are passed in integer registers. */
6123 else if (type && TREE_CODE (type) == UNION_TYPE)
45261626 6124 {
45261626 6125 HOST_WIDE_INT size = int_size_in_bytes (type);
f5f7d171 6126 gcc_assert (size <= 16);
45261626 6127
ef6843ed 6128 return function_arg_union_value (size, mode, slotno, regno);
45261626
EB		 6129 }
6130
4fb4e4b8
DE		 6131 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6132 but also have the slot allocated for them.
6133 If no prototype is in scope fp values in register slots get passed
6134 in two places, either fp regs and int regs or fp regs and memory. */
ef6843ed
EB		 6135 else if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6136 && SPARC_FP_REG_P (regno))
4fb4e4b8 6137 {
ef6843ed 6138 rtx reg = gen_rtx_REG (mode, regno);
4fb4e4b8
DE		 6139 if (cum->prototype_p || cum->libcall_p)
6140 {
6141 /* "* 2" because fp reg numbers are recorded in 4 byte
6142 quantities. */
82d6b402 6143#if 0
4fb4e4b8
DE		 6144 /* ??? This will cause the value to be passed in the fp reg and
6145 in the stack. When a prototype exists we want to pass the
6146 value in the reg but reserve space on the stack. That's an
956d6950 6147 optimization, and is deferred [for a bit]. */
4fb4e4b8 6148 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
254110c2 6149 return gen_rtx_PARALLEL (mode,
4fb4e4b8 6150 gen_rtvec (2,
254110c2 6151 gen_rtx_EXPR_LIST (VOIDmode,
4fb4e4b8 6152 NULL_RTX, const0_rtx),
254110c2 6153 gen_rtx_EXPR_LIST (VOIDmode,
4fb4e4b8
DE		 6154 reg, const0_rtx)));
6155 else
82d6b402
RH		 6156#else
6157 /* ??? It seems that passing back a register even when past
6158 the area declared by REG_PARM_STACK_SPACE will allocate
6159 space appropriately, and will not copy the data onto the
6160 stack, exactly as we desire.
6161
6162 This is due to locate_and_pad_parm being called in
6163 expand_call whenever reg_parm_stack_space > 0, which
fae778eb 6164 while beneficial to our example here, would seem to be
82d6b402
RH		 6165 in error from what had been intended. Ho hum... -- r~ */
6166#endif
4fb4e4b8
DE		 6167 return reg;
6168 }
6169 else
6170 {
82d6b402
RH		 6171 rtx v0, v1;
6172
4fb4e4b8
DE		 6173 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
6174 {
82d6b402
RH		 6175 int intreg;
6176
6177 /* On incoming, we don't need to know that the value
6178 is passed in %f0 and %i0, and it confuses other parts
6179 causing needless spillage even on the simplest cases. */
6180 if (incoming_p)
6181 return reg;
6182
6183 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
6184 + (regno - SPARC_FP_ARG_FIRST) / 2);
6185
6186 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
6187 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
6188 const0_rtx);
6189 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4fb4e4b8
DE		 6190 }
6191 else
82d6b402
RH		 6192 {
6193 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6194 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
6195 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
6196 }
4fb4e4b8
DE		 6197 }
6198 }
ef6843ed
EB		 6199
6200 /* All other aggregate types are passed in an integer register in a mode
6201 corresponding to the size of the type. */
6202 else if (type && AGGREGATE_TYPE_P (type))
4fb4e4b8 6203 {
ef6843ed
EB		 6204 HOST_WIDE_INT size = int_size_in_bytes (type);
6205 gcc_assert (size <= 16);
6206
6207 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
4fb4e4b8
DE		 6208 }
6209
ef6843ed 6210 return gen_rtx_REG (mode, regno);
4fb4e4b8 6211}
a7acd911 6212
9adafb9f
NF		 6213/* Handle the TARGET_FUNCTION_ARG target hook. */
6214
6215static rtx
d5cc9181 6216sparc_function_arg (cumulative_args_t cum, enum machine_mode mode,
9adafb9f
NF		 6217 const_tree type, bool named)
6218{
6219 return sparc_function_arg_1 (cum, mode, type, named, false);
6220}
6221
6222/* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6223
6224static rtx
d5cc9181 6225sparc_function_incoming_arg (cumulative_args_t cum, enum machine_mode mode,
9adafb9f
NF		 6226 const_tree type, bool named)
6227{
6228 return sparc_function_arg_1 (cum, mode, type, named, true);
6229}
6230
c2ed6cf8
NF		 6231/* For sparc64, objects requiring 16 byte alignment are passed that way. */
6232
6233static unsigned int
6234sparc_function_arg_boundary (enum machine_mode mode, const_tree type)
6235{
6236 return ((TARGET_ARCH64
6237 && (GET_MODE_ALIGNMENT (mode) == 128
6238 || (type && TYPE_ALIGN (type) == 128)))
6239 ? 128
6240 : PARM_BOUNDARY);
6241}
6242
78a52f11
RH		 6243/* For an arg passed partly in registers and partly in memory,
6244 this is the number of bytes of registers used.
4fb4e4b8 6245 For args passed entirely in registers or entirely in memory, zero.
61a55e8b 6246
4fb4e4b8
DE		 6247 Any arg that starts in the first 6 regs but won't entirely fit in them
6248 needs partial registers on v8. On v9, structures with integer
6249 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6250 values that begin in the last fp reg [where "last fp reg" varies with the
6251 mode] will be split between that reg and memory. */
61a55e8b 6252
78a52f11 6253static int
d5cc9181 6254sparc_arg_partial_bytes (cumulative_args_t cum, enum machine_mode mode,
78a52f11 6255 tree type, bool named)
4fb4e4b8
DE		 6256{
6257 int slotno, regno, padding;
61a55e8b 6258
9adafb9f 6259 /* We pass false for incoming_p here, it doesn't matter. */
d5cc9181
JR		 6260 slotno = function_arg_slotno (get_cumulative_args (cum), mode, type, named,
6261 false, &regno, &padding);
4fb4e4b8
DE		 6262
6263 if (slotno == -1)
6264 return 0;
6265
6266 if (TARGET_ARCH32)
bf62bbf1 6267 {
4fb4e4b8
DE		 6268 if ((slotno + (mode == BLKmode
6269 ? ROUND_ADVANCE (int_size_in_bytes (type))
6270 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
1b5963f7 6271 > SPARC_INT_ARG_MAX)
78a52f11 6272 return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD;
4fb4e4b8
DE		 6273 }
6274 else
6275 {
8cd5a4e0 6276 /* We are guaranteed by pass_by_reference that the size of the
78a52f11
RH		 6277 argument is not greater than 16 bytes, so we only need to return
6278 one word if the argument is partially passed in registers. */
1b5963f7 6279
4fb4e4b8
DE		 6280 if (type && AGGREGATE_TYPE_P (type))
6281 {
6282 int size = int_size_in_bytes (type);
bf62bbf1 6283
1b5963f7 6284 if (size > UNITS_PER_WORD
4fb4e4b8 6285 && slotno == SPARC_INT_ARG_MAX - 1)
78a52f11 6286 return UNITS_PER_WORD;
4fb4e4b8 6287 }
0a9e65f9 6288 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
4fb4e4b8 6289 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
c3427c7d 6290 && ! (TARGET_FPU && named)))
4fb4e4b8 6291 {
0a9e65f9 6292 /* The complex types are passed as packed types. */
1b5963f7
EB		 6293 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
6294 && slotno == SPARC_INT_ARG_MAX - 1)
78a52f11 6295 return UNITS_PER_WORD;
4fb4e4b8
DE		 6296 }
6297 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6298 {
4fb4e4b8
DE		 6299 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
6300 > SPARC_FP_ARG_MAX)
78a52f11 6301 return UNITS_PER_WORD;
4fb4e4b8 6302 }
bf62bbf1 6303 }
1b5963f7
EB		 6304
6305 return 0;
4fb4e4b8 6306}
61a55e8b 6307
45261626
EB		 6308/* Handle the TARGET_PASS_BY_REFERENCE target hook.
6309 Specify whether to pass the argument by reference. */
4fb4e4b8 6310
8cd5a4e0 6311static bool
d5cc9181 6312sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
586de218 6313 enum machine_mode mode, const_tree type,
8cd5a4e0 6314 bool named ATTRIBUTE_UNUSED)
4fb4e4b8
DE		 6315{
6316 if (TARGET_ARCH32)
45261626
EB		 6317 /* Original SPARC 32-bit ABI says that structures and unions,
6318 and quad-precision floats are passed by reference. For Pascal,
6319 also pass arrays by reference. All other base types are passed
6320 in registers.
6321
6322 Extended ABI (as implemented by the Sun compiler) says that all
6323 complex floats are passed by reference. Pass complex integers
6324 in registers up to 8 bytes. More generally, enforce the 2-word
6325 cap for passing arguments in registers.
6326
6327 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6328 integers are passed like floats of the same size, that is in
6329 registers up to 8 bytes. Pass all vector floats by reference
6330 like structure and unions. */
ef6843ed
EB		 6331 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
6332 || mode == SCmode
6333 /* Catch CDImode, TFmode, DCmode and TCmode. */
6334 || GET_MODE_SIZE (mode) > 8
6335 || (type
6336 && TREE_CODE (type) == VECTOR_TYPE
6337 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
4fb4e4b8 6338 else
45261626
EB		 6339 /* Original SPARC 64-bit ABI says that structures and unions
6340 smaller than 16 bytes are passed in registers, as well as
ef6843ed 6341 all other base types.
4900aa61 6342
45261626
EB		 6343 Extended ABI (as implemented by the Sun compiler) says that
6344 complex floats are passed in registers up to 16 bytes. Pass
6345 all complex integers in registers up to 16 bytes. More generally,
6346 enforce the 2-word cap for passing arguments in registers.
6347
6348 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6349 integers are passed like floats of the same size, that is in
6350 registers (up to 16 bytes). Pass all vector floats like structure
6351 and unions. */
ef6843ed
EB		 6352 return ((type
6353 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE)
6354 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
6355 /* Catch CTImode and TCmode. */
6356 || GET_MODE_SIZE (mode) > 16);
4fb4e4b8
DE		 6357}
6358
9adafb9f 6359/* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
4fb4e4b8
DE		 6360 Update the data in CUM to advance over an argument
6361 of mode MODE and data type TYPE.
6362 TYPE is null for libcalls where that information may not be available. */
6363
9adafb9f 6364static void
d5cc9181 6365sparc_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
9adafb9f 6366 const_tree type, bool named)
4fb4e4b8 6367{
d5cc9181 6368 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
e0c7ff23 6369 int regno, padding;
4fb4e4b8 6370
9adafb9f
NF		 6371 /* We pass false for incoming_p here, it doesn't matter. */
6372 function_arg_slotno (cum, mode, type, named, false, &regno, &padding);
4fb4e4b8 6373
e0c7ff23
EB		 6374 /* If argument requires leading padding, add it. */
6375 cum->words += padding;
eadceb59 6376
4fb4e4b8
DE		 6377 if (TARGET_ARCH32)
6378 {
6379 cum->words += (mode != BLKmode
6380 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
6381 : ROUND_ADVANCE (int_size_in_bytes (type)));
6382 }
6383 else
6384 {
6385 if (type && AGGREGATE_TYPE_P (type))
6386 {
6387 int size = int_size_in_bytes (type);
6388
6389 if (size <= 8)
6390 ++cum->words;
6391 else if (size <= 16)
6392 cum->words += 2;
6393 else /* passed by reference */
6394 ++cum->words;
6395 }
4fb4e4b8
DE		 6396 else
6397 {
6398 cum->words += (mode != BLKmode
6399 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
6400 : ROUND_ADVANCE (int_size_in_bytes (type)));
6401 }
eadceb59 6402 }
4fb4e4b8 6403}
eadceb59 6404
4fb4e4b8
DE		 6405/* Handle the FUNCTION_ARG_PADDING macro.
6406 For the 64 bit ABI structs are always stored left shifted in their
6407 argument slot. */
6408
6409enum direction
586de218 6410function_arg_padding (enum machine_mode mode, const_tree type)
4fb4e4b8 6411{
c85f7c16
JL		 6412 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
6413 return upward;
61a55e8b 6414
d3704c46
KH		 6415 /* Fall back to the default. */
6416 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
61a55e8b 6417}
82d6b402 6418
1b5963f7
EB		 6419/* Handle the TARGET_RETURN_IN_MEMORY target hook.
6420 Specify whether to return the return value in memory. */
6421
6422static bool
586de218 6423sparc_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1b5963f7
EB		 6424{
6425 if (TARGET_ARCH32)
45261626
EB		 6426 /* Original SPARC 32-bit ABI says that structures and unions,
6427 and quad-precision floats are returned in memory. All other
6428 base types are returned in registers.
6429
6430 Extended ABI (as implemented by the Sun compiler) says that
6431 all complex floats are returned in registers (8 FP registers
6432 at most for '_Complex long double'). Return all complex integers
6433 in registers (4 at most for '_Complex long long').
6434
6435 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6436 integers are returned like floats of the same size, that is in
6437 registers up to 8 bytes and in memory otherwise. Return all
6438 vector floats in memory like structure and unions; note that
6439 they always have BLKmode like the latter. */
1b5963f7
EB		 6440 return (TYPE_MODE (type) == BLKmode
6441 || TYPE_MODE (type) == TFmode
45261626
EB		 6442 || (TREE_CODE (type) == VECTOR_TYPE
6443 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
1b5963f7
EB		 6444 else
6445 /* Original SPARC 64-bit ABI says that structures and unions
45261626
EB		 6446 smaller than 32 bytes are returned in registers, as well as
6447 all other base types.
4900aa61 6448
45261626
EB		 6449 Extended ABI (as implemented by the Sun compiler) says that all
6450 complex floats are returned in registers (8 FP registers at most
6451 for '_Complex long double'). Return all complex integers in
6452 registers (4 at most for '_Complex TItype').
6453
6454 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6455 integers are returned like floats of the same size, that is in
6456 registers. Return all vector floats like structure and unions;
6457 note that they always have BLKmode like the latter. */
f79e1b0f
EB		 6458 return (TYPE_MODE (type) == BLKmode
6459 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32);
1b5963f7
EB		 6460}
6461
6462/* Handle the TARGET_STRUCT_VALUE target hook.
6463 Return where to find the structure return value address. */
6464
6465static rtx
2225b57c 6466sparc_struct_value_rtx (tree fndecl, int incoming)
1b5963f7
EB		 6467{
6468 if (TARGET_ARCH64)
6469 return 0;
6470 else
6471 {
1da4c3a7
EB		 6472 rtx mem;
6473
1b5963f7 6474 if (incoming)
114ce554
ILT		 6475 mem = gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx,
6476 STRUCT_VALUE_OFFSET));
1b5963f7 6477 else
114ce554
ILT		 6478 mem = gen_frame_mem (Pmode, plus_constant (stack_pointer_rtx,
6479 STRUCT_VALUE_OFFSET));
1da4c3a7 6480
4900aa61
EB		 6481 /* Only follow the SPARC ABI for fixed-size structure returns.
6482 Variable size structure returns are handled per the normal
2225b57c 6483 procedures in GCC. This is enabled by -mstd-struct-return */
4900aa61 6484 if (incoming == 2
2225b57c
CD		 6485 && sparc_std_struct_return
6486 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl))
6487 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl))) == INTEGER_CST)
6488 {
6489 /* We must check and adjust the return address, as it is
6490 optional as to whether the return object is really
6491 provided. */
3810076b 6492 rtx ret_reg = gen_rtx_REG (Pmode, 31);
2225b57c 6493 rtx scratch = gen_reg_rtx (SImode);
4900aa61 6494 rtx endlab = gen_label_rtx ();
2225b57c
CD		 6495
6496 /* Calculate the return object size */
6497 tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl));
6498 rtx size_rtx = GEN_INT (TREE_INT_CST_LOW (size) & 0xfff);
6499 /* Construct a temporary return value */
f79e1b0f
EB		 6500 rtx temp_val
6501 = assign_stack_local (Pmode, TREE_INT_CST_LOW (size), 0);
2225b57c 6502
f79e1b0f 6503 /* Implement SPARC 32-bit psABI callee return struct checking:
4900aa61 6504
f79e1b0f 6505 Fetch the instruction where we will return to and see if
2225b57c
CD		 6506 it's an unimp instruction (the most significant 10 bits
6507 will be zero). */
6508 emit_move_insn (scratch, gen_rtx_MEM (SImode,
3810076b 6509 plus_constant (ret_reg, 8)));
2225b57c 6510 /* Assume the size is valid and pre-adjust */
3810076b 6511 emit_insn (gen_add3_insn (ret_reg, ret_reg, GEN_INT (4)));
f79e1b0f
EB		 6512 emit_cmp_and_jump_insns (scratch, size_rtx, EQ, const0_rtx, SImode,
6513 0, endlab);
3810076b 6514 emit_insn (gen_sub3_insn (ret_reg, ret_reg, GEN_INT (4)));
f79e1b0f 6515 /* Write the address of the memory pointed to by temp_val into
2225b57c
CD		 6516 the memory pointed to by mem */
6517 emit_move_insn (mem, XEXP (temp_val, 0));
6518 emit_label (endlab);
6519 }
6520
1da4c3a7 6521 return mem;
1b5963f7
EB		 6522 }
6523}
6524
bf44d792 6525/* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
82d6b402 6526 For v9, function return values are subject to the same rules as arguments,
1b5963f7 6527 except that up to 32 bytes may be returned in registers. */
82d6b402 6528
bf44d792
AS		 6529static rtx
6530sparc_function_value_1 (const_tree type, enum machine_mode mode,
6531 bool outgoing)
82d6b402 6532{
1b5963f7 6533 /* Beware that the two values are swapped here wrt function_arg. */
bf44d792
AS		 6534 int regbase = (outgoing
6535 ? SPARC_INCOMING_INT_ARG_FIRST
6536 : SPARC_OUTGOING_INT_ARG_FIRST);
45261626 6537 enum mode_class mclass = GET_MODE_CLASS (mode);
82d6b402 6538 int regno;
82d6b402 6539
ef6843ed
EB		 6540 /* Vector types deserve special treatment because they are polymorphic wrt
6541 their mode, depending upon whether VIS instructions are enabled. */
45261626
EB		 6542 if (type && TREE_CODE (type) == VECTOR_TYPE)
6543 {
45261626 6544 HOST_WIDE_INT size = int_size_in_bytes (type);
f5f7d171
JM		 6545 gcc_assert ((TARGET_ARCH32 && size <= 8)
6546 || (TARGET_ARCH64 && size <= 32));
45261626
EB		 6547
6548 if (mode == BLKmode)
6549 return function_arg_vector_value (size,
45261626
EB		 6550 SPARC_FP_ARG_FIRST);
6551 else
6552 mclass = MODE_FLOAT;
6553 }
ef6843ed
EB		 6554
6555 if (TARGET_ARCH64 && type)
82d6b402 6556 {
ef6843ed 6557 /* Structures up to 32 bytes in size are returned in registers. */
82d6b402
RH		 6558 if (TREE_CODE (type) == RECORD_TYPE)
6559 {
ef6843ed
EB		 6560 HOST_WIDE_INT size = int_size_in_bytes (type);
6561 gcc_assert (size <= 32);
82d6b402 6562
1eac9f59 6563 return function_arg_record_value (type, mode, 0, 1, regbase);
82d6b402 6564 }
ef6843ed
EB		 6565
6566 /* Unions up to 32 bytes in size are returned in integer registers. */
a7bba6ca
EB		 6567 else if (TREE_CODE (type) == UNION_TYPE)
6568 {
6569 HOST_WIDE_INT size = int_size_in_bytes (type);
f5f7d171 6570 gcc_assert (size <= 32);
a7bba6ca 6571
22d8d627 6572 return function_arg_union_value (size, mode, 0, regbase);
a7bba6ca 6573 }
ef6843ed
EB		 6574
6575 /* Objects that require it are returned in FP registers. */
6576 else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6577 ;
6578
6579 /* All other aggregate types are returned in an integer register in a
6580 mode corresponding to the size of the type. */
8a7199ad 6581 else if (AGGREGATE_TYPE_P (type))
82d6b402 6582 {
8a7199ad
RK		 6583 /* All other aggregate types are passed in an integer register
6584 in a mode corresponding to the size of the type. */
ef6843ed
EB		 6585 HOST_WIDE_INT size = int_size_in_bytes (type);
6586 gcc_assert (size <= 32);
82d6b402 6587
ef6843ed 6588 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
c74fd3f1
EB		 6589
6590 /* ??? We probably should have made the same ABI change in
6591 3.4.0 as the one we made for unions. The latter was
6592 required by the SCD though, while the former is not
6593 specified, so we favored compatibility and efficiency.
6594
6595 Now we're stuck for aggregates larger than 16 bytes,
6596 because OImode vanished in the meantime. Let's not
6597 try to be unduly clever, and simply follow the ABI
6598 for unions in that case. */
6599 if (mode == BLKmode)
ef6843ed 6600 return function_arg_union_value (size, mode, 0, regbase);
45261626
EB		 6601 else
6602 mclass = MODE_INT;
82d6b402 6603 }
ef6843ed 6604
f79e1b0f
EB		 6605 /* We should only have pointer and integer types at this point. This
6606 must match sparc_promote_function_mode. */
ef6843ed 6607 else if (mclass == MODE_INT && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
a7bba6ca 6608 mode = word_mode;
82d6b402
RH		 6609 }
6610
f79e1b0f
EB		 6611 /* We should only have pointer and integer types at this point. This must
6612 match sparc_promote_function_mode. */
6613 else if (TARGET_ARCH32
6614 && mclass == MODE_INT
6615 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6616 mode = word_mode;
6617
ef6843ed 6618 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) && TARGET_FPU)
1b5963f7 6619 regno = SPARC_FP_ARG_FIRST;
82d6b402 6620 else
1b5963f7 6621 regno = regbase;
82d6b402 6622
254110c2 6623 return gen_rtx_REG (mode, regno);
82d6b402
RH		 6624}
6625
bf44d792 6626/* Handle TARGET_FUNCTION_VALUE.
f79e1b0f
EB		 6627 On the SPARC, the value is found in the first "output" register, but the
6628 called function leaves it in the first "input" register. */
bf44d792
AS		 6629
6630static rtx
6631sparc_function_value (const_tree valtype,
6632 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
6633 bool outgoing)
6634{
6635 return sparc_function_value_1 (valtype, TYPE_MODE (valtype), outgoing);
6636}
6637
6638/* Handle TARGET_LIBCALL_VALUE. */
6639
6640static rtx
6641sparc_libcall_value (enum machine_mode mode,
6642 const_rtx fun ATTRIBUTE_UNUSED)
6643{
6644 return sparc_function_value_1 (NULL_TREE, mode, false);
6645}
6646
f79e1b0f
EB		 6647/* Handle FUNCTION_VALUE_REGNO_P.
6648 On the SPARC, the first "output" reg is used for integer values, and the
6649 first floating point register is used for floating point values. */
bf44d792
AS		 6650
6651static bool
6652sparc_function_value_regno_p (const unsigned int regno)
6653{
6654 return (regno == 8 || regno == 32);
6655}
6656
648d2ffc
RH		 6657/* Do what is necessary for `va_start'. We look at the current function
6658 to determine if stdarg or varargs is used and return the address of
6659 the first unnamed parameter. */
3ea1fdd3 6660
3e2cc1d1 6661static rtx
fc27d102 6662sparc_builtin_saveregs (void)
3ea1fdd3 6663{
38173d38 6664 int first_reg = crtl->args.info.words;
3ea1fdd3
JW		 6665 rtx address;
6666 int regno;
6667
1b5963f7 6668 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
254110c2 6669 emit_move_insn (gen_rtx_MEM (word_mode,
8ac61af7
RK		 6670 gen_rtx_PLUS (Pmode,
6671 frame_pointer_rtx,
563c12b0 6672 GEN_INT (FIRST_PARM_OFFSET (0)
8ac61af7
RK		 6673 + (UNITS_PER_WORD
6674 * regno)))),
254110c2 6675 gen_rtx_REG (word_mode,
1b5963f7 6676 SPARC_INCOMING_INT_ARG_FIRST + regno));
3ea1fdd3 6677
254110c2 6678 address = gen_rtx_PLUS (Pmode,
8ac61af7 6679 frame_pointer_rtx,
563c12b0 6680 GEN_INT (FIRST_PARM_OFFSET (0)
8ac61af7 6681 + UNITS_PER_WORD * first_reg));
3ea1fdd3
JW		 6682
6683 return address;
6684}
a8b2c8a1 6685
1b5963f7 6686/* Implement `va_start' for stdarg. */
a8b2c8a1 6687
d7bd8aeb 6688static void
fc27d102 6689sparc_va_start (tree valist, rtx nextarg)
a8b2c8a1
RH		 6690{
6691 nextarg = expand_builtin_saveregs ();
e5faf155 6692 std_expand_builtin_va_start (valist, nextarg);
a8b2c8a1
RH		 6693}
6694
1b5963f7 6695/* Implement `va_arg' for stdarg. */
a8b2c8a1 6696
35652573 6697static tree
726a989a
RB		 6698sparc_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6699 gimple_seq *post_p)
5f393b25
JM		 6700{
6701 HOST_WIDE_INT size, rsize, align;
6702 tree addr, incr;
6703 bool indirect;
6704 tree ptrtype = build_pointer_type (type);
6705
22d66adf 6706 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5f393b25
JM		 6707 {
6708 indirect = true;
6709 size = rsize = UNITS_PER_WORD;
6710 align = 0;
6711 }
6712 else
6713 {
6714 indirect = false;
6715 size = int_size_in_bytes (type);
6716 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6717 align = 0;
3764d512 6718
5f393b25
JM		 6719 if (TARGET_ARCH64)
6720 {
6721 /* For SPARC64, objects requiring 16-byte alignment get it. */
6722 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
6723 align = 2 * UNITS_PER_WORD;
6724
6725 /* SPARC-V9 ABI states that structures up to 16 bytes in size
22d66adf 6726 are left-justified in their slots. */
5f393b25
JM		 6727 if (AGGREGATE_TYPE_P (type))
6728 {
6729 if (size == 0)
6730 size = rsize = UNITS_PER_WORD;
6731 else
6732 size = rsize;
6733 }
6734 }
6735 }
6736
6737 incr = valist;
6738 if (align)
6739 {
5be014d5
AP		 6740 incr = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr,
6741 size_int (align - 1));
6742 incr = fold_convert (sizetype, incr);
6743 incr = fold_build2 (BIT_AND_EXPR, sizetype, incr,
6744 size_int (-align));
6745 incr = fold_convert (ptr_type_node, incr);
5f393b25
JM		 6746 }
6747
6748 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
6749 addr = incr;
6750
6751 if (BYTES_BIG_ENDIAN && size < rsize)
5be014d5
AP		 6752 addr = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr,
6753 size_int (rsize - size));
5f393b25
JM		 6754
6755 if (indirect)
6756 {
6757 addr = fold_convert (build_pointer_type (ptrtype), addr);
22d66adf 6758 addr = build_va_arg_indirect_ref (addr);
5f393b25 6759 }
3764d512
EB		 6760
6761 /* If the address isn't aligned properly for the type, we need a temporary.
6762 FIXME: This is inefficient, usually we can do this in registers. */
6763 else if (align == 0 && TYPE_ALIGN (type) > BITS_PER_WORD)
5f393b25
JM		 6764 {
6765 tree tmp = create_tmp_var (type, "va_arg_tmp");
6766 tree dest_addr = build_fold_addr_expr (tmp);
3764d512
EB		 6767 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6768 3, dest_addr, addr, size_int (rsize));
6769 TREE_ADDRESSABLE (tmp) = 1;
5f393b25
JM		 6770 gimplify_and_add (copy, pre_p);
6771 addr = dest_addr;
6772 }
3764d512 6773
5f393b25
JM		 6774 else
6775 addr = fold_convert (ptrtype, addr);
6776
3764d512
EB		 6777 incr
6778 = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, incr, size_int (rsize));
726a989a 6779 gimplify_assign (valist, incr, post_p);
5f393b25 6780
22d66adf 6781 return build_va_arg_indirect_ref (addr);
5f393b25 6782}
ab835497 6783\f
c75d6010
JM		 6784/* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6785 Specify whether the vector mode is supported by the hardware. */
6786
6787static bool
6788sparc_vector_mode_supported_p (enum machine_mode mode)
6789{
6790 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
6791}
6792\f
cc4b5170 6793/* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
26983c22 6794
cc4b5170
RG		 6795static enum machine_mode
6796sparc_preferred_simd_mode (enum machine_mode mode)
26983c22 6797{
cc4b5170
RG		 6798 if (TARGET_VIS)
6799 switch (mode)
6800 {
6801 case SImode:
6802 return V2SImode;
6803 case HImode:
6804 return V4HImode;
6805 case QImode:
6806 return V8QImode;
6807
6808 default:;
6809 }
6810
6811 return word_mode;
26983c22
L		 6812}
6813\f
1b3c2c2d
EB		 6814/* Return the string to output an unconditional branch to LABEL, which is
6815 the operand number of the label.
6816
6817 DEST is the destination insn (i.e. the label), INSN is the source. */
6818
6819const char *
6820output_ubranch (rtx dest, int label, rtx insn)
6821{
6822 static char string[64];
4e5b002b 6823 bool v9_form = false;
1b3c2c2d
EB		 6824 char *p;
6825
4e5b002b 6826 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
1b3c2c2d 6827 {
4e5b002b
EB		 6828 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6829 - INSN_ADDRESSES (INSN_UID (insn)));
6830 /* Leave some instructions for "slop". */
6831 if (delta >= -260000 && delta < 260000)
6832 v9_form = true;
1b3c2c2d 6833 }
1b3c2c2d 6834
4e5b002b
EB		 6835 if (v9_form)
6836 strcpy (string, "ba%*,pt\t%%xcc, ");
6837 else
6838 strcpy (string, "b%*\t");
1b3c2c2d
EB		 6839
6840 p = strchr (string, '\0');
6841 *p++ = '%';
6842 *p++ = 'l';
6843 *p++ = '0' + label;
6844 *p++ = '%';
4e5b002b 6845 *p++ = '(';
1b3c2c2d
EB		 6846 *p = '\0';
6847
6848 return string;
6849}
6850
ab835497 6851/* Return the string to output a conditional branch to LABEL, which is
c4ce6853
DE		 6852 the operand number of the label. OP is the conditional expression.
6853 XEXP (OP, 0) is assumed to be a condition code register (integer or
6854 floating point) and its mode specifies what kind of comparison we made.
61a55e8b 6855
1b3c2c2d
EB		 6856 DEST is the destination insn (i.e. the label), INSN is the source.
6857
5e7a8ee0 6858 REVERSED is nonzero if we should reverse the sense of the comparison.
ab835497 6859
4e5b002b 6860 ANNUL is nonzero if we should generate an annulling branch. */
ab835497 6861
a6163c22 6862const char *
fc27d102 6863output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
4e5b002b 6864 rtx insn)
ab835497 6865{
a6163c22 6866 static char string[64];
ab835497 6867 enum rtx_code code = GET_CODE (op);
c4ce6853
DE		 6868 rtx cc_reg = XEXP (op, 0);
6869 enum machine_mode mode = GET_MODE (cc_reg);
0b82d204
JJ		 6870 const char *labelno, *branch;
6871 int spaces = 8, far;
6872 char *p;
6873
6874 /* v9 branches are limited to +-1MB. If it is too far away,
6875 change
6876
6877 bne,pt %xcc, .LC30
6878
6879 to
6880
6881 be,pn %xcc, .+12
a6163c22 6882 nop
0b82d204
JJ		 6883 ba .LC30
6884
6885 and
6886
6887 fbne,a,pn %fcc2, .LC29
61a55e8b 6888
0b82d204
JJ		 6889 to
6890
6891 fbe,pt %fcc2, .+16
a6163c22 6892 nop
0b82d204
JJ		 6893 ba .LC29 */
6894
883d9e0c 6895 far = TARGET_V9 && (get_attr_length (insn) >= 3);
0b82d204 6896 if (reversed ^ far)
ab835497 6897 {
e267e177
RH		 6898 /* Reversal of FP compares takes care -- an ordered compare
6899 becomes an unordered compare and vice versa. */
4d449554 6900 if (mode == CCFPmode || mode == CCFPEmode)
7913f3d0 6901 code = reverse_condition_maybe_unordered (code);
ab835497 6902 else
e267e177 6903 code = reverse_condition (code);
ab835497
RK		 6904 }
6905
e267e177
RH		 6906 /* Start by writing the branch condition. */
6907 if (mode == CCFPmode || mode == CCFPEmode)
5850dc00
RH		 6908 {
6909 switch (code)
6910 {
6911 case NE:
6912 branch = "fbne";
6913 break;
6914 case EQ:
6915 branch = "fbe";
6916 break;
6917 case GE:
6918 branch = "fbge";
6919 break;
6920 case GT:
6921 branch = "fbg";
6922 break;
6923 case LE:
6924 branch = "fble";
6925 break;
6926 case LT:
6927 branch = "fbl";
6928 break;
6929 case UNORDERED:
6930 branch = "fbu";
6931 break;
6932 case ORDERED:
6933 branch = "fbo";
6934 break;
6935 case UNGT:
6936 branch = "fbug";
6937 break;
6938 case UNLT:
6939 branch = "fbul";
6940 break;
6941 case UNEQ:
6942 branch = "fbue";
6943 break;
6944 case UNGE:
6945 branch = "fbuge";
6946 break;
6947 case UNLE:
6948 branch = "fbule";
6949 break;
6950 case LTGT:
6951 branch = "fblg";
6952 break;
6953
6954 default:
f5f7d171 6955 gcc_unreachable ();
5850dc00
RH		 6956 }
6957
6958 /* ??? !v9: FP branches cannot be preceded by another floating point
6959 insn. Because there is currently no concept of pre-delay slots,
6960 we can fix this only by always emitting a nop before a floating
6961 point branch. */
6962
6963 string[0] = '\0';
6964 if (! TARGET_V9)
6965 strcpy (string, "nop\n\t");
6966 strcat (string, branch);
6967 }
e267e177 6968 else
5850dc00
RH		 6969 {
6970 switch (code)
6971 {
6972 case NE:
6973 branch = "bne";
6974 break;
6975 case EQ:
6976 branch = "be";
6977 break;
6978 case GE:
0b82d204 6979 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5850dc00
RH		 6980 branch = "bpos";
6981 else
6982 branch = "bge";
6983 break;
6984 case GT:
6985 branch = "bg";
6986 break;
6987 case LE:
6988 branch = "ble";
6989 break;
6990 case LT:
0b82d204 6991 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5850dc00
RH		 6992 branch = "bneg";
6993 else
6994 branch = "bl";
6995 break;
6996 case GEU:
6997 branch = "bgeu";
6998 break;
6999 case GTU:
7000 branch = "bgu";
7001 break;
7002 case LEU:
7003 branch = "bleu";
7004 break;
7005 case LTU:
7006 branch = "blu";
7007 break;
7008
7009 default:
f5f7d171 7010 gcc_unreachable ();
5850dc00
RH		 7011 }
7012 strcpy (string, branch);
7013 }
e267e177 7014 spaces -= strlen (branch);
0b82d204 7015 p = strchr (string, '\0');
e267e177 7016
ab835497 7017 /* Now add the annulling, the label, and a possible noop. */
0b82d204 7018 if (annul && ! far)
e0d80184 7019 {
0b82d204
JJ		 7020 strcpy (p, ",a");
7021 p += 2;
e0d80184
DM		 7022 spaces -= 2;
7023 }
ab835497 7024
883d9e0c 7025 if (TARGET_V9)
61a55e8b 7026 {
c6b0465b 7027 rtx note;
0b82d204 7028 int v8 = 0;
c6b0465b 7029
0b82d204 7030 if (! far && insn && INSN_ADDRESSES_SET_P ())
e0d80184 7031 {
0b82d204
JJ		 7032 int delta = (INSN_ADDRESSES (INSN_UID (dest))
7033 - INSN_ADDRESSES (INSN_UID (insn)));
7034 /* Leave some instructions for "slop". */
7035 if (delta < -260000 || delta >= 260000)
7036 v8 = 1;
e0d80184 7037 }
c6b0465b 7038
61a55e8b
DE		 7039 if (mode == CCFPmode || mode == CCFPEmode)
7040 {
0b82d204 7041 static char v9_fcc_labelno[] = "%%fccX, ";
61a55e8b 7042 /* Set the char indicating the number of the fcc reg to use. */
0b82d204
JJ		 7043 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
7044 labelno = v9_fcc_labelno;
7045 if (v8)
7046 {
f5f7d171
JM		 7047 gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG);
7048 labelno = "";
0b82d204 7049 }
61a55e8b
DE		 7050 }
7051 else if (mode == CCXmode || mode == CCX_NOOVmode)
0b82d204
JJ		 7052 {
7053 labelno = "%%xcc, ";
f5f7d171 7054 gcc_assert (! v8);
0b82d204 7055 }
61a55e8b 7056 else
0b82d204
JJ		 7057 {
7058 labelno = "%%icc, ";
7059 if (v8)
7060 labelno = "";
7061 }
7062
4f31cce8 7063 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
0b82d204
JJ		 7064 {
7065 strcpy (p,
4f31cce8 7066 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
0b82d204
JJ		 7067 ? ",pt" : ",pn");
7068 p += 3;
7069 spaces -= 3;
7070 }
61a55e8b 7071 }
883d9e0c
EB		 7072 else
7073 labelno = "";
7074
e0d80184 7075 if (spaces > 0)
0b82d204 7076 *p++ = '\t';
e0d80184 7077 else
0b82d204
JJ		 7078 *p++ = ' ';
7079 strcpy (p, labelno);
7080 p = strchr (p, '\0');
7081 if (far)
7082 {
a6163c22 7083 strcpy (p, ".+12\n\t nop\n\tb\t");
4e5b002b
EB		 7084 /* Skip the next insn if requested or
7085 if we know that it will be a nop. */
7086 if (annul || ! final_sequence)
0b82d204 7087 p[3] = '6';
a6163c22 7088 p += 14;
0b82d204
JJ		 7089 }
7090 *p++ = '%';
7091 *p++ = 'l';
0b82d204 7092 *p++ = label + '0';
4e5b002b
EB		 7093 *p++ = '%';
7094 *p++ = '#';
0b82d204 7095 *p = '\0';
61a55e8b
DE		 7096
7097 return string;
7098}
7099
47ac041c 7100/* Emit a library call comparison between floating point X and Y.
19047e4a
EB		 7101 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7102 Return the new operator to be used in the comparison sequence.
7103
47ac041c
JJ		 7104 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7105 values as arguments instead of the TFmode registers themselves,
7106 that's why we cannot call emit_float_lib_cmp. */
19047e4a 7107
f90b7a5a 7108rtx
fc27d102 7109sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
47ac041c 7110{
e77d72cb 7111 const char *qpfunc;
390b17c2 7112 rtx slot0, slot1, result, tem, tem2, libfunc;
5c5c34a4 7113 enum machine_mode mode;
19047e4a 7114 enum rtx_code new_comparison;
47ac041c
JJ		 7115
7116 switch (comparison)
7117 {
7118 case EQ:
19047e4a 7119 qpfunc = (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq");
47ac041c
JJ		 7120 break;
7121
7122 case NE:
19047e4a 7123 qpfunc = (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne");
47ac041c
JJ		 7124 break;
7125
7126 case GT:
19047e4a 7127 qpfunc = (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt");
47ac041c
JJ		 7128 break;
7129
7130 case GE:
19047e4a 7131 qpfunc = (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge");
47ac041c
JJ		 7132 break;
7133
7134 case LT:
19047e4a 7135 qpfunc = (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt");
47ac041c
JJ		 7136 break;
7137
7138 case LE:
19047e4a 7139 qpfunc = (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle");
5c5c34a4
JJ		 7140 break;
7141
7142 case ORDERED:
7143 case UNORDERED:
7144 case UNGT:
7145 case UNLT:
7146 case UNEQ:
7147 case UNGE:
7148 case UNLE:
7149 case LTGT:
19047e4a 7150 qpfunc = (TARGET_ARCH64 ? "_Qp_cmp" : "_Q_cmp");
47ac041c
JJ		 7151 break;
7152
7153 default:
f5f7d171 7154 gcc_unreachable ();
47ac041c
JJ		 7155 }
7156
5c5c34a4 7157 if (TARGET_ARCH64)
47ac041c 7158 {
19047e4a
EB		 7159 if (MEM_P (x))
7160 slot0 = x;
7161 else
5c5c34a4
JJ		 7162 {
7163 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
c5d74498 7164 emit_move_insn (slot0, x);
5c5c34a4 7165 }
5c5c34a4 7166
19047e4a
EB		 7167 if (MEM_P (y))
7168 slot1 = y;
7169 else
5c5c34a4
JJ		 7170 {
7171 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
c5d74498 7172 emit_move_insn (slot1, y);
5c5c34a4 7173 }
47ac041c 7174
390b17c2
RE		 7175 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
7176 emit_library_call (libfunc, LCT_NORMAL,
5c5c34a4
JJ		 7177 DImode, 2,
7178 XEXP (slot0, 0), Pmode,
7179 XEXP (slot1, 0), Pmode);
5c5c34a4
JJ		 7180 mode = DImode;
7181 }
7182 else
47ac041c 7183 {
390b17c2
RE		 7184 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
7185 emit_library_call (libfunc, LCT_NORMAL,
5c5c34a4
JJ		 7186 SImode, 2,
7187 x, TFmode, y, TFmode);
5c5c34a4 7188 mode = SImode;
47ac041c
JJ		 7189 }
7190
47ac041c
JJ		 7191
7192 /* Immediately move the result of the libcall into a pseudo
7193 register so reload doesn't clobber the value if it needs
7194 the return register for a spill reg. */
5c5c34a4 7195 result = gen_reg_rtx (mode);
390b17c2 7196 emit_move_insn (result, hard_libcall_value (mode, libfunc));
47ac041c 7197
5c5c34a4
JJ		 7198 switch (comparison)
7199 {
7200 default:
f90b7a5a 7201 return gen_rtx_NE (VOIDmode, result, const0_rtx);
5c5c34a4
JJ		 7202 case ORDERED:
7203 case UNORDERED:
19047e4a 7204 new_comparison = (comparison == UNORDERED ? EQ : NE);
f90b7a5a 7205 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, GEN_INT(3));
5c5c34a4
JJ		 7206 case UNGT:
7207 case UNGE:
19047e4a 7208 new_comparison = (comparison == UNGT ? GT : NE);
f90b7a5a 7209 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, const1_rtx);
5c5c34a4 7210 case UNLE:
f90b7a5a 7211 return gen_rtx_NE (VOIDmode, result, const2_rtx);
5c5c34a4
JJ		 7212 case UNLT:
7213 tem = gen_reg_rtx (mode);
7214 if (TARGET_ARCH32)
7215 emit_insn (gen_andsi3 (tem, result, const1_rtx));
7216 else
7217 emit_insn (gen_anddi3 (tem, result, const1_rtx));
f90b7a5a 7218 return gen_rtx_NE (VOIDmode, tem, const0_rtx);
5c5c34a4
JJ		 7219 case UNEQ:
7220 case LTGT:
7221 tem = gen_reg_rtx (mode);
7222 if (TARGET_ARCH32)
7223 emit_insn (gen_addsi3 (tem, result, const1_rtx));
7224 else
7225 emit_insn (gen_adddi3 (tem, result, const1_rtx));
7226 tem2 = gen_reg_rtx (mode);
7227 if (TARGET_ARCH32)
7228 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
7229 else
7230 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
19047e4a 7231 new_comparison = (comparison == UNEQ ? EQ : NE);
f90b7a5a 7232 return gen_rtx_fmt_ee (new_comparison, VOIDmode, tem2, const0_rtx);
5c5c34a4 7233 }
19047e4a 7234
f90b7a5a 7235 gcc_unreachable ();
47ac041c 7236}
5c5c34a4 7237
d88e57d1
RH		 7238/* Generate an unsigned DImode to FP conversion. This is the same code
7239 optabs would emit if we didn't have TFmode patterns. */
7240
7241void
b178305d 7242sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
d88e57d1
RH		 7243{
7244 rtx neglab, donelab, i0, i1, f0, in, out;
d88e57d1
RH		 7245
7246 out = operands[0];
7247 in = force_reg (DImode, operands[1]);
d88e57d1
RH		 7248 neglab = gen_label_rtx ();
7249 donelab = gen_label_rtx ();
7250 i0 = gen_reg_rtx (DImode);
7251 i1 = gen_reg_rtx (DImode);
7252 f0 = gen_reg_rtx (mode);
7253
7254 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
7255
7256 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
7257 emit_jump_insn (gen_jump (donelab));
7258 emit_barrier ();
7259
7260 emit_label (neglab);
7261
7262 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
7263 emit_insn (gen_anddi3 (i1, in, const1_rtx));
7264 emit_insn (gen_iordi3 (i0, i0, i1));
7265 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
7266 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
7267
7268 emit_label (donelab);
7269}
7270
b178305d
EB		 7271/* Generate an FP to unsigned DImode conversion. This is the same code
7272 optabs would emit if we didn't have TFmode patterns. */
7273
7274void
7275sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
7276{
7277 rtx neglab, donelab, i0, i1, f0, in, out, limit;
7278
7279 out = operands[0];
7280 in = force_reg (mode, operands[1]);
7281 neglab = gen_label_rtx ();
7282 donelab = gen_label_rtx ();
7283 i0 = gen_reg_rtx (DImode);
7284 i1 = gen_reg_rtx (DImode);
7285 limit = gen_reg_rtx (mode);
7286 f0 = gen_reg_rtx (mode);
7287
7288 emit_move_insn (limit,
7289 CONST_DOUBLE_FROM_REAL_VALUE (
7290 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
7291 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
7292
7293 emit_insn (gen_rtx_SET (VOIDmode,
7294 out,
7295 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
7296 emit_jump_insn (gen_jump (donelab));
7297 emit_barrier ();
7298
7299 emit_label (neglab);
7300
7301 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
7302 emit_insn (gen_rtx_SET (VOIDmode,
7303 i0,
7304 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
7305 emit_insn (gen_movdi (i1, const1_rtx));
7306 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
7307 emit_insn (gen_xordi3 (out, i0, i1));
7308
7309 emit_label (donelab);
7310}
7311
61a55e8b
DE		 7312/* Return the string to output a conditional branch to LABEL, testing
7313 register REG. LABEL is the operand number of the label; REG is the
7314 operand number of the reg. OP is the conditional expression. The mode
7315 of REG says what kind of comparison we made.
7316
1b3c2c2d
EB		 7317 DEST is the destination insn (i.e. the label), INSN is the source.
7318
5e7a8ee0 7319 REVERSED is nonzero if we should reverse the sense of the comparison.
61a55e8b 7320
4e5b002b 7321 ANNUL is nonzero if we should generate an annulling branch. */
61a55e8b 7322
a6163c22 7323const char *
fc27d102 7324output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
4e5b002b 7325 int annul, rtx insn)
61a55e8b 7326{
a6163c22 7327 static char string[64];
61a55e8b
DE		 7328 enum rtx_code code = GET_CODE (op);
7329 enum machine_mode mode = GET_MODE (XEXP (op, 0));
e0d80184 7330 rtx note;
0b82d204
JJ		 7331 int far;
7332 char *p;
7333
7334 /* branch on register are limited to +-128KB. If it is too far away,
7335 change
4900aa61 7336
0b82d204 7337 brnz,pt %g1, .LC30
4900aa61 7338
0b82d204 7339 to
4900aa61 7340
0b82d204 7341 brz,pn %g1, .+12
a6163c22 7342 nop
0b82d204 7343 ba,pt %xcc, .LC30
4900aa61 7344
0b82d204 7345 and
4900aa61 7346
0b82d204 7347 brgez,a,pn %o1, .LC29
4900aa61 7348
0b82d204 7349 to
4900aa61 7350
0b82d204 7351 brlz,pt %o1, .+16
a6163c22 7352 nop
0b82d204
JJ		 7353 ba,pt %xcc, .LC29 */
7354
7355 far = get_attr_length (insn) >= 3;
61a55e8b
DE		 7356
7357 /* If not floating-point or if EQ or NE, we can just reverse the code. */
0b82d204
JJ		 7358 if (reversed ^ far)
7359 code = reverse_condition (code);
61a55e8b
DE		 7360
7361 /* Only 64 bit versions of these instructions exist. */
f5f7d171 7362 gcc_assert (mode == DImode);
61a55e8b
DE		 7363
7364 /* Start by writing the branch condition. */
7365
7366 switch (code)
7367 {
7368 case NE:
7369 strcpy (string, "brnz");
7370 break;
7371
7372 case EQ:
7373 strcpy (string, "brz");
7374 break;
7375
7376 case GE:
7377 strcpy (string, "brgez");
7378 break;
7379
7380 case LT:
7381 strcpy (string, "brlz");
7382 break;
7383
7384 case LE:
7385 strcpy (string, "brlez");
7386 break;
7387
7388 case GT:
7389 strcpy (string, "brgz");
7390 break;
7391
7392 default:
f5f7d171 7393 gcc_unreachable ();
61a55e8b
DE		 7394 }
7395
0b82d204
JJ		 7396 p = strchr (string, '\0');
7397
61a55e8b 7398 /* Now add the annulling, reg, label, and nop. */
0b82d204 7399 if (annul && ! far)
e0d80184 7400 {
0b82d204
JJ		 7401 strcpy (p, ",a");
7402 p += 2;
e0d80184 7403 }
61a55e8b 7404
4f31cce8 7405 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
e0d80184 7406 {
0b82d204 7407 strcpy (p,
4f31cce8 7408 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
0b82d204
JJ		 7409 ? ",pt" : ",pn");
7410 p += 3;
e0d80184 7411 }
61a55e8b 7412
0b82d204
JJ		 7413 *p = p < string + 8 ? '\t' : ' ';
7414 p++;
7415 *p++ = '%';
7416 *p++ = '0' + reg;
7417 *p++ = ',';
7418 *p++ = ' ';
7419 if (far)
7420 {
7421 int veryfar = 1, delta;
7422
7423 if (INSN_ADDRESSES_SET_P ())
7424 {
7425 delta = (INSN_ADDRESSES (INSN_UID (dest))
7426 - INSN_ADDRESSES (INSN_UID (insn)));
7427 /* Leave some instructions for "slop". */
7428 if (delta >= -260000 && delta < 260000)
7429 veryfar = 0;
7430 }
7431
a6163c22 7432 strcpy (p, ".+12\n\t nop\n\t");
4e5b002b
EB		 7433 /* Skip the next insn if requested or
7434 if we know that it will be a nop. */
7435 if (annul || ! final_sequence)
0b82d204 7436 p[3] = '6';
a6163c22 7437 p += 12;
0b82d204
JJ		 7438 if (veryfar)
7439 {
7440 strcpy (p, "b\t");
7441 p += 2;
7442 }
7443 else
7444 {
7445 strcpy (p, "ba,pt\t%%xcc, ");
7446 p += 13;
7447 }
7448 }
7449 *p++ = '%';
7450 *p++ = 'l';
7451 *p++ = '0' + label;
4e5b002b
EB		 7452 *p++ = '%';
7453 *p++ = '#';
0b82d204 7454 *p = '\0';
ab835497 7455
ab835497
RK		 7456 return string;
7457}
7458
e48addee
JJ		 7459/* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
7460 Such instructions cannot be used in the delay slot of return insn on v9.
7461 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
7462 */
284d86e9 7463
e48addee 7464static int
fc27d102 7465epilogue_renumber (register rtx *where, int test)
284d86e9 7466{
e48addee
JJ		 7467 register const char *fmt;
7468 register int i;
7469 register enum rtx_code code;
7470
7471 if (*where == 0)
7472 return 0;
7473
7474 code = GET_CODE (*where);
284d86e9
JC		 7475
7476 switch (code)
7477 {
284d86e9 7478 case REG:
e48addee
JJ		 7479 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
7480 return 1;
7481 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
f1c25d3b 7482 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
e48addee
JJ		 7483 case SCRATCH:
7484 case CC0:
7485 case PC:
284d86e9
JC		 7486 case CONST_INT:
7487 case CONST_DOUBLE:
e48addee 7488 return 0;
76a7c776 7489
09ebda1b
SC		 7490 /* Do not replace the frame pointer with the stack pointer because
7491 it can cause the delayed instruction to load below the stack.
7492 This occurs when instructions like:
7493
7494 (set (reg/i:SI 24 %i0)
7495 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7496 (const_int -20 [0xffffffec])) 0))
7497
7498 are in the return delayed slot. */
7499 case PLUS:
7500 if (GET_CODE (XEXP (*where, 0)) == REG
563c12b0 7501 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
09ebda1b
SC		 7502 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
7503 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
7504 return 1;
7505 break;
7506
7507 case MEM:
7508 if (SPARC_STACK_BIAS
7509 && GET_CODE (XEXP (*where, 0)) == REG
563c12b0 7510 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
09ebda1b
SC		 7511 return 1;
7512 break;
7513
76a7c776
DM		 7514 default:
7515 break;
e48addee 7516 }
284d86e9 7517
e48addee 7518 fmt = GET_RTX_FORMAT (code);
284d86e9 7519
e48addee
JJ		 7520 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7521 {
7522 if (fmt[i] == 'E')
7523 {
7524 register int j;
7525 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
7526 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
7527 return 1;
7528 }
7529 else if (fmt[i] == 'e'
7530 && epilogue_renumber (&(XEXP (*where, i)), test))
7531 return 1;
284d86e9 7532 }
e48addee 7533 return 0;
284d86e9 7534}
ab835497
RK		 7535\f
7536/* Leaf functions and non-leaf functions have different needs. */
7537
8b60264b 7538static const int
ab835497
RK		 7539reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
7540
8b60264b 7541static const int
ab835497
RK		 7542reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
7543
8b60264b 7544static const int *const reg_alloc_orders[] = {
ab835497
RK		 7545 reg_leaf_alloc_order,
7546 reg_nonleaf_alloc_order};
7547
7548void
fc27d102 7549order_regs_for_local_alloc (void)
ab835497
RK		 7550{
7551 static int last_order_nonleaf = 1;
7552
6fb5fa3c 7553 if (df_regs_ever_live_p (15) != last_order_nonleaf)
ab835497
RK		 7554 {
7555 last_order_nonleaf = !last_order_nonleaf;
2e09e75a 7556 memcpy ((char *) reg_alloc_order,
8b60264b 7557 (const char *) reg_alloc_orders[last_order_nonleaf],
2e09e75a 7558 FIRST_PSEUDO_REGISTER * sizeof (int));
ab835497
RK		 7559 }
7560}
7561\f
e0d80184
DM		 7562/* Return 1 if REG and MEM are legitimate enough to allow the various
7563 mem<-->reg splits to be run. */
7564
7565int
fc27d102 7566sparc_splitdi_legitimate (rtx reg, rtx mem)
e0d80184 7567{
e0d80184 7568 /* Punt if we are here by mistake. */
f5f7d171 7569 gcc_assert (reload_completed);
e0d80184
DM		 7570
7571 /* We must have an offsettable memory reference. */
7572 if (! offsettable_memref_p (mem))
7573 return 0;
7574
7575 /* If we have legitimate args for ldd/std, we do not want
7576 the split to happen. */
7577 if ((REGNO (reg) % 2) == 0
7578 && mem_min_alignment (mem, 8))
7579 return 0;
7580
7581 /* Success. */
7582 return 1;
7583}
7584
e61c29e9 7585/* Return 1 if x and y are some kind of REG and they refer to
fae778eb 7586 different hard registers. This test is guaranteed to be
e61c29e9
DM		 7587 run after reload. */
7588
7589int
fc27d102 7590sparc_absnegfloat_split_legitimate (rtx x, rtx y)
e61c29e9 7591{
e61c29e9
DM		 7592 if (GET_CODE (x) != REG)
7593 return 0;
e61c29e9
DM		 7594 if (GET_CODE (y) != REG)
7595 return 0;
7596 if (REGNO (x) == REGNO (y))
7597 return 0;
7598 return 1;
7599}
7600
35016322 7601/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
4900aa61 7602 This makes them candidates for using ldd and std insns.
35016322 7603
bfd6bc60 7604 Note reg1 and reg2 *must* be hard registers. */
35016322
JW		 7605
7606int
fc27d102 7607registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
35016322 7608{
35016322 7609 /* We might have been passed a SUBREG. */
4900aa61 7610 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
35016322
JW		 7611 return 0;
7612
35016322
JW		 7613 if (REGNO (reg1) % 2 != 0)
7614 return 0;
7615
4900aa61
EB		 7616 /* Integer ldd is deprecated in SPARC V9 */
7617 if (TARGET_V9 && REGNO (reg1) < 32)
7618 return 0;
bfd6bc60 7619
35016322 7620 return (REGNO (reg1) == REGNO (reg2) - 1);
35016322
JW		 7621}
7622
2aad5d68 7623/* Return 1 if the addresses in mem1 and mem2 are suitable for use in
303f8933 7624 an ldd or std insn.
4900aa61 7625
2aad5d68
DN		 7626 This can only happen when addr1 and addr2, the addresses in mem1
7627 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
303f8933
DN		 7628 addr1 must also be aligned on a 64-bit boundary.
7629
7630 Also iff dependent_reg_rtx is not null it should not be used to
7631 compute the address for mem1, i.e. we cannot optimize a sequence
7632 like:
7633 ld [%o0], %o0
7634 ld [%o0 + 4], %o1
7635 to
bcdd764b 7636 ldd [%o0], %o0
0acf409f
DM		 7637 nor:
7638 ld [%g3 + 4], %g3
7639 ld [%g3], %g2
7640 to
7641 ldd [%g3], %g2
7642
7643 But, note that the transformation from:
7644 ld [%g2 + 4], %g3
7645 ld [%g2], %g2
7646 to
7647 ldd [%g2], %g2
7648 is perfectly fine. Thus, the peephole2 patterns always pass us
7649 the destination register of the first load, never the second one.
7650
303f8933
DN		 7651 For stores we don't have a similar problem, so dependent_reg_rtx is
7652 NULL_RTX. */
35016322
JW		 7653
7654int
fc27d102 7655mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
35016322 7656{
2aad5d68 7657 rtx addr1, addr2;
0d587737 7658 unsigned int reg1;
6a151f87 7659 HOST_WIDE_INT offset1;
35016322 7660
303f8933
DN		 7661 /* The mems cannot be volatile. */
7662 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
7663 return 0;
2aad5d68 7664
303f8933 7665 /* MEM1 should be aligned on a 64-bit boundary. */
2aad5d68
DN		 7666 if (MEM_ALIGN (mem1) < 64)
7667 return 0;
4900aa61 7668
303f8933
DN		 7669 addr1 = XEXP (mem1, 0);
7670 addr2 = XEXP (mem2, 0);
4900aa61 7671
35016322
JW		 7672 /* Extract a register number and offset (if used) from the first addr. */
7673 if (GET_CODE (addr1) == PLUS)
7674 {
7675 /* If not a REG, return zero. */
7676 if (GET_CODE (XEXP (addr1, 0)) != REG)
7677 return 0;
7678 else
7679 {
7680 reg1 = REGNO (XEXP (addr1, 0));
7681 /* The offset must be constant! */
7682 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
7683 return 0;
7684 offset1 = INTVAL (XEXP (addr1, 1));
7685 }
7686 }
7687 else if (GET_CODE (addr1) != REG)
7688 return 0;
7689 else
7690 {
7691 reg1 = REGNO (addr1);
7692 /* This was a simple (mem (reg)) expression. Offset is 0. */
7693 offset1 = 0;
7694 }
7695
7696 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7697 if (GET_CODE (addr2) != PLUS)
7698 return 0;
7699
7700 if (GET_CODE (XEXP (addr2, 0)) != REG
7701 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
7702 return 0;
7703
35016322
JW		 7704 if (reg1 != REGNO (XEXP (addr2, 0)))
7705 return 0;
7706
303f8933
DN		 7707 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
7708 return 0;
4900aa61
EB		 7709
7710 /* The first offset must be evenly divisible by 8 to ensure the
35016322
JW		 7711 address is 64 bit aligned. */
7712 if (offset1 % 8 != 0)
7713 return 0;
7714
7715 /* The offset for the second addr must be 4 more than the first addr. */
7716 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
7717 return 0;
7718
7719 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7720 instructions. */
7721 return 1;
7722}
7c56249d 7723
157891a3
EB		 7724/* Return 1 if reg is a pseudo, or is the first register in
7725 a hard register pair. This makes it suitable for use in
7c56249d
JL		 7726 ldd and std insns. */
7727
7728int
fc27d102 7729register_ok_for_ldd (rtx reg)
7c56249d 7730{
7c56249d 7731 /* We might have been passed a SUBREG. */
157891a3 7732 if (!REG_P (reg))
7c56249d
JL		 7733 return 0;
7734
7735 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
7736 return (REGNO (reg) % 2 == 0);
157891a3
EB		 7737
7738 return 1;
7739}
7740
7741/* Return 1 if OP is a memory whose address is known to be
7742 aligned to 8-byte boundary, or a pseudo during reload.
7743 This makes it suitable for use in ldd and std insns. */
7744
7745int
7746memory_ok_for_ldd (rtx op)
7747{
7748 if (MEM_P (op))
7749 {
7750 /* In 64-bit mode, we assume that the address is word-aligned. */
7751 if (TARGET_ARCH32 && !mem_min_alignment (op, 8))
7752 return 0;
7753
7754 if ((reload_in_progress || reload_completed)
7755 && !strict_memory_address_p (Pmode, XEXP (op, 0)))
7756 return 0;
7757 }
7758 else if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
7759 {
7760 if (!(reload_in_progress && reg_renumber [REGNO (op)] < 0))
7761 return 0;
7762 }
7763 else
7764 return 0;
7765
7766 return 1;
7c56249d 7767}
ab835497 7768\f
46e43d2b
AS		 7769/* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7770
7771static bool
7772sparc_print_operand_punct_valid_p (unsigned char code)
7773{
7774 if (code == '#'
7775 || code == '*'
7776 || code == '('
7777 || code == ')'
7778 || code == '_'
7779 || code == '&')
7780 return true;
7781
7782 return false;
7783}
7784
7785/* Implement TARGET_PRINT_OPERAND.
7786 Print operand X (an rtx) in assembler syntax to file FILE.
ab835497
RK		 7787 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7788 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7789
46e43d2b
AS		 7790static void
7791sparc_print_operand (FILE *file, rtx x, int code)
ab835497
RK		 7792{
7793 switch (code)
7794 {
7795 case '#':
4e5b002b
EB		 7796 /* Output an insn in a delay slot. */
7797 if (final_sequence)
7798 sparc_indent_opcode = 1;
7799 else
e0d80184 7800 fputs ("\n\t nop", file);
ab835497
RK		 7801 return;
7802 case '*':
c6ce0969 7803 /* Output an annul flag if there's nothing for the delay slot and we
4e5b002b
EB		 7804 are optimizing. This is always used with '(' below.
7805 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7806 this is a dbx bug. So, we only do this when optimizing.
7807 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
bfd6bc60 7808 Always emit a nop in case the next instruction is a branch. */
4e5b002b 7809 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9))
c6ce0969
JW		 7810 fputs (",a", file);
7811 return;
7812 case '(':
7813 /* Output a 'nop' if there's nothing for the delay slot and we are
7814 not optimizing. This is always used with '*' above. */
4e5b002b 7815 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
e0d80184 7816 fputs ("\n\t nop", file);
4e5b002b
EB		 7817 else if (final_sequence)
7818 sparc_indent_opcode = 1;
7819 return;
7820 case ')':
7821 /* Output the right displacement from the saved PC on function return.
7822 The caller may have placed an "unimp" insn immediately after the call
7823 so we have to account for it. This insn is used in the 32-bit ABI
66695571 7824 when calling a function that returns a non zero-sized structure. The
4e5b002b 7825 64-bit ABI doesn't have it. Be careful to have this test be the same
66695571
EB		 7826 as that for the call. The exception is when sparc_std_struct_return
7827 is enabled, the psABI is followed exactly and the adjustment is made
7828 by the code in sparc_struct_value_rtx. The call emitted is the same
7829 when sparc_std_struct_return is enabled. */
7830 if (!TARGET_ARCH64
e3b5732b 7831 && cfun->returns_struct
66695571
EB		 7832 && !sparc_std_struct_return
7833 && DECL_SIZE (DECL_RESULT (current_function_decl))
7834 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
7835 == INTEGER_CST
7836 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))))
4e5b002b
EB		 7837 fputs ("12", file);
7838 else
7839 fputc ('8', file);
ab835497 7840 return;
61a55e8b 7841 case '_':
a0a301fc
DE		 7842 /* Output the Embedded Medium/Anywhere code model base register. */
7843 fputs (EMBMEDANY_BASE_REG, file);
61a55e8b 7844 return;
5751a10b
JJ		 7845 case '&':
7846 /* Print some local dynamic TLS name. */
7847 assemble_name (file, get_some_local_dynamic_name ());
7848 return;
4e5b002b 7849
ab835497
RK		 7850 case 'Y':
7851 /* Adjust the operand to take into account a RESTORE operation. */
bfd6bc60
JC		 7852 if (GET_CODE (x) == CONST_INT)
7853 break;
7854 else if (GET_CODE (x) != REG)
c725bd79 7855 output_operand_lossage ("invalid %%Y operand");
b3b1e8bd 7856 else if (REGNO (x) < 8)
ab835497
RK		 7857 fputs (reg_names[REGNO (x)], file);
7858 else if (REGNO (x) >= 24 && REGNO (x) < 32)
7859 fputs (reg_names[REGNO (x)-16], file);
7860 else
c725bd79 7861 output_operand_lossage ("invalid %%Y operand");
ab835497 7862 return;
0f39a9aa
DE		 7863 case 'L':
7864 /* Print out the low order register name of a register pair. */
7865 if (WORDS_BIG_ENDIAN)
7866 fputs (reg_names[REGNO (x)+1], file);
7867 else
7868 fputs (reg_names[REGNO (x)], file);
7869 return;
7870 case 'H':
7871 /* Print out the high order register name of a register pair. */
7872 if (WORDS_BIG_ENDIAN)
7873 fputs (reg_names[REGNO (x)], file);
7874 else
7875 fputs (reg_names[REGNO (x)+1], file);
7876 return;
ab835497 7877 case 'R':
795068a4 7878 /* Print out the second register name of a register pair or quad.
ab835497
RK		 7879 I.e., R (%o0) => %o1. */
7880 fputs (reg_names[REGNO (x)+1], file);
7881 return;
795068a4
JW		 7882 case 'S':
7883 /* Print out the third register name of a register quad.
7884 I.e., S (%o0) => %o2. */
7885 fputs (reg_names[REGNO (x)+2], file);
7886 return;
7887 case 'T':
7888 /* Print out the fourth register name of a register quad.
7889 I.e., T (%o0) => %o3. */
7890 fputs (reg_names[REGNO (x)+3], file);
7891 return;
304b7a23
DE		 7892 case 'x':
7893 /* Print a condition code register. */
7894 if (REGNO (x) == SPARC_ICC_REG)
7895 {
7896 /* We don't handle CC[X]_NOOVmode because they're not supposed
7897 to occur here. */
7898 if (GET_MODE (x) == CCmode)
7899 fputs ("%icc", file);
7900 else if (GET_MODE (x) == CCXmode)
7901 fputs ("%xcc", file);
7902 else
f5f7d171 7903 gcc_unreachable ();
304b7a23
DE		 7904 }
7905 else
7906 /* %fccN register */
7907 fputs (reg_names[REGNO (x)], file);
7908 return;
ab835497
RK		 7909 case 'm':
7910 /* Print the operand's address only. */
7911 output_address (XEXP (x, 0));
7912 return;
7913 case 'r':
7914 /* In this case we need a register. Use %g0 if the
77a02b01 7915 operand is const0_rtx. */
76052e74
RS		 7916 if (x == const0_rtx
7917 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
ab835497
RK		 7918 {
7919 fputs ("%g0", file);
7920 return;
7921 }
7922 else
7923 break;
7924
61a55e8b 7925 case 'A':
ab835497
RK		 7926 switch (GET_CODE (x))
7927 {
7928 case IOR: fputs ("or", file); break;
7929 case AND: fputs ("and", file); break;
7930 case XOR: fputs ("xor", file); break;
c725bd79 7931 default: output_operand_lossage ("invalid %%A operand");
ab835497
RK		 7932 }
7933 return;
7934
7935 case 'B':
7936 switch (GET_CODE (x))
7937 {
7938 case IOR: fputs ("orn", file); break;
7939 case AND: fputs ("andn", file); break;
7940 case XOR: fputs ("xnor", file); break;
c725bd79 7941 default: output_operand_lossage ("invalid %%B operand");
ab835497
RK		 7942 }
7943 return;
7944
304b7a23
DE		 7945 /* These are used by the conditional move instructions. */
7946 case 'c' :
61a55e8b 7947 case 'C':
304b7a23 7948 {
5c5c34a4
JJ		 7949 enum rtx_code rc = GET_CODE (x);
7950
7951 if (code == 'c')
7952 {
7953 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7954 if (mode == CCFPmode || mode == CCFPEmode)
7955 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7956 else
7957 rc = reverse_condition (GET_CODE (x));
7958 }
304b7a23
DE		 7959 switch (rc)
7960 {
7961 case NE: fputs ("ne", file); break;
7962 case EQ: fputs ("e", file); break;
7963 case GE: fputs ("ge", file); break;
7964 case GT: fputs ("g", file); break;
7965 case LE: fputs ("le", file); break;
7966 case LT: fputs ("l", file); break;
7967 case GEU: fputs ("geu", file); break;
7968 case GTU: fputs ("gu", file); break;
7969 case LEU: fputs ("leu", file); break;
7970 case LTU: fputs ("lu", file); break;
5c5c34a4
JJ		 7971 case LTGT: fputs ("lg", file); break;
7972 case UNORDERED: fputs ("u", file); break;
7973 case ORDERED: fputs ("o", file); break;
7974 case UNLT: fputs ("ul", file); break;
7975 case UNLE: fputs ("ule", file); break;
7976 case UNGT: fputs ("ug", file); break;
7977 case UNGE: fputs ("uge", file); break;
7978 case UNEQ: fputs ("ue", file); break;
304b7a23 7979 default: output_operand_lossage (code == 'c'
c725bd79
NB		 7980 ? "invalid %%c operand"
7981 : "invalid %%C operand");
304b7a23
DE		 7982 }
7983 return;
7984 }
7985
7986 /* These are used by the movr instruction pattern. */
7987 case 'd':
61a55e8b 7988 case 'D':
304b7a23
DE		 7989 {
7990 enum rtx_code rc = (code == 'd'
7991 ? reverse_condition (GET_CODE (x))
7992 : GET_CODE (x));
7993 switch (rc)
7994 {
7995 case NE: fputs ("ne", file); break;
7996 case EQ: fputs ("e", file); break;
7997 case GE: fputs ("gez", file); break;
7998 case LT: fputs ("lz", file); break;
7999 case LE: fputs ("lez", file); break;
8000 case GT: fputs ("gz", file); break;
8001 default: output_operand_lossage (code == 'd'
c725bd79
NB		 8002 ? "invalid %%d operand"
8003 : "invalid %%D operand");
304b7a23
DE		 8004 }
8005 return;
8006 }
61a55e8b 8007
ab835497
RK		 8008 case 'b':
8009 {
8010 /* Print a sign-extended character. */
9e0625a3 8011 int i = trunc_int_for_mode (INTVAL (x), QImode);
ab835497
RK		 8012 fprintf (file, "%d", i);
8013 return;
8014 }
8015
d2889939
RK		 8016 case 'f':
8017 /* Operand must be a MEM; write its address. */
8018 if (GET_CODE (x) != MEM)
c725bd79 8019 output_operand_lossage ("invalid %%f operand");
d2889939
RK		 8020 output_address (XEXP (x, 0));
8021 return;
8022
8707fe93
RH		 8023 case 's':
8024 {
8025 /* Print a sign-extended 32-bit value. */
8026 HOST_WIDE_INT i;
8027 if (GET_CODE(x) == CONST_INT)
8028 i = INTVAL (x);
8029 else if (GET_CODE(x) == CONST_DOUBLE)
8030 i = CONST_DOUBLE_LOW (x);
8031 else
ffa916ba
KG		 8032 {
8033 output_operand_lossage ("invalid %%s operand");
8034 return;
8035 }
8707fe93
RH		 8036 i = trunc_int_for_mode (i, SImode);
8037 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
8038 return;
8039 }
8040
ab835497
RK		 8041 case 0:
8042 /* Do nothing special. */
8043 break;
8044
8045 default:
8046 /* Undocumented flag. */
415f583e 8047 output_operand_lossage ("invalid operand output code");
ab835497
RK		 8048 }
8049
8050 if (GET_CODE (x) == REG)
8051 fputs (reg_names[REGNO (x)], file);
8052 else if (GET_CODE (x) == MEM)
8053 {
8054 fputc ('[', file);
ab835497 8055 /* Poor Sun assembler doesn't understand absolute addressing. */
e6c1be7e 8056 if (CONSTANT_P (XEXP (x, 0)))
ab835497
RK		 8057 fputs ("%g0+", file);
8058 output_address (XEXP (x, 0));
8059 fputc (']', file);
8060 }
8061 else if (GET_CODE (x) == HIGH)
8062 {
8063 fputs ("%hi(", file);
8064 output_addr_const (file, XEXP (x, 0));
8065 fputc (')', file);
8066 }
8067 else if (GET_CODE (x) == LO_SUM)
8068 {
46e43d2b 8069 sparc_print_operand (file, XEXP (x, 0), 0);
e0d80184
DM		 8070 if (TARGET_CM_MEDMID)
8071 fputs ("+%l44(", file);
8072 else
8073 fputs ("+%lo(", file);
ab835497
RK		 8074 output_addr_const (file, XEXP (x, 1));
8075 fputc (')', file);
8076 }
e601abce
JW		 8077 else if (GET_CODE (x) == CONST_DOUBLE
8078 && (GET_MODE (x) == VOIDmode
8079 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
ab835497
RK		 8080 {
8081 if (CONST_DOUBLE_HIGH (x) == 0)
0d9484c5 8082 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
ab835497
RK		 8083 else if (CONST_DOUBLE_HIGH (x) == -1
8084 && CONST_DOUBLE_LOW (x) < 0)
0d9484c5 8085 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
ab835497 8086 else
e601abce 8087 output_operand_lossage ("long long constant not a valid immediate operand");
ab835497 8088 }
e601abce
JW		 8089 else if (GET_CODE (x) == CONST_DOUBLE)
8090 output_operand_lossage ("floating point constant not a valid immediate operand");
ab835497
RK		 8091 else { output_addr_const (file, x); }
8092}
46e43d2b
AS		 8093
8094/* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8095
8096static void
8097sparc_print_operand_address (FILE *file, rtx x)
8098{
8099 register rtx base, index = 0;
8100 int offset = 0;
8101 register rtx addr = x;
8102
8103 if (REG_P (addr))
8104 fputs (reg_names[REGNO (addr)], file);
8105 else if (GET_CODE (addr) == PLUS)
8106 {
8107 if (CONST_INT_P (XEXP (addr, 0)))
8108 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
8109 else if (CONST_INT_P (XEXP (addr, 1)))
8110 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
8111 else
8112 base = XEXP (addr, 0), index = XEXP (addr, 1);
8113 if (GET_CODE (base) == LO_SUM)
8114 {
8115 gcc_assert (USE_AS_OFFSETABLE_LO10
8116 && TARGET_ARCH64
8117 && ! TARGET_CM_MEDMID);
8118 output_operand (XEXP (base, 0), 0);
8119 fputs ("+%lo(", file);
8120 output_address (XEXP (base, 1));
8121 fprintf (file, ")+%d", offset);
8122 }
8123 else
8124 {
8125 fputs (reg_names[REGNO (base)], file);
8126 if (index == 0)
8127 fprintf (file, "%+d", offset);
8128 else if (REG_P (index))
8129 fprintf (file, "+%s", reg_names[REGNO (index)]);
8130 else if (GET_CODE (index) == SYMBOL_REF
8131 || GET_CODE (index) == LABEL_REF
8132 || GET_CODE (index) == CONST)
8133 fputc ('+', file), output_addr_const (file, index);
8134 else gcc_unreachable ();
8135 }
8136 }
8137 else if (GET_CODE (addr) == MINUS
8138 && GET_CODE (XEXP (addr, 1)) == LABEL_REF)
8139 {
8140 output_addr_const (file, XEXP (addr, 0));
8141 fputs ("-(", file);
8142 output_addr_const (file, XEXP (addr, 1));
8143 fputs ("-.)", file);
8144 }
8145 else if (GET_CODE (addr) == LO_SUM)
8146 {
8147 output_operand (XEXP (addr, 0), 0);
8148 if (TARGET_CM_MEDMID)
8149 fputs ("+%l44(", file);
8150 else
8151 fputs ("+%lo(", file);
8152 output_address (XEXP (addr, 1));
8153 fputc (')', file);
8154 }
8155 else if (flag_pic
8156 && GET_CODE (addr) == CONST
8157 && GET_CODE (XEXP (addr, 0)) == MINUS
8158 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST
8159 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS
8160 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx)
8161 {
8162 addr = XEXP (addr, 0);
8163 output_addr_const (file, XEXP (addr, 0));
8164 /* Group the args of the second CONST in parenthesis. */
8165 fputs ("-(", file);
8166 /* Skip past the second CONST--it does nothing for us. */
8167 output_addr_const (file, XEXP (XEXP (addr, 1), 0));
8168 /* Close the parenthesis. */
8169 fputc (')', file);
8170 }
8171 else
8172 {
8173 output_addr_const (file, addr);
8174 }
8175}
ab835497 8176\f
301d03af
RS		 8177/* Target hook for assembling integer objects. The sparc version has
8178 special handling for aligned DI-mode objects. */
ab835497 8179
301d03af 8180static bool
fc27d102 8181sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
ab835497 8182{
301d03af
RS		 8183 /* ??? We only output .xword's for symbols and only then in environments
8184 where the assembler can handle them. */
8185 if (aligned_p && size == 8
8186 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
ab835497 8187 {
301d03af 8188 if (TARGET_V9)
61a55e8b 8189 {
301d03af
RS		 8190 assemble_integer_with_op ("\t.xword\t", x);
8191 return true;
61a55e8b
DE		 8192 }
8193 else
8194 {
301d03af
RS		 8195 assemble_aligned_integer (4, const0_rtx);
8196 assemble_aligned_integer (4, x);
8197 return true;
61a55e8b 8198 }
ab835497 8199 }
301d03af 8200 return default_assemble_integer (x, size, aligned_p);
ab835497 8201}
210aa14a 8202\f
b0468b84
RK		 8203/* Return the value of a code used in the .proc pseudo-op that says
8204 what kind of result this function returns. For non-C types, we pick
8205 the closest C type. */
8206
77a02b01
JW		 8207#ifndef SHORT_TYPE_SIZE
8208#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
8209#endif
8210
8211#ifndef INT_TYPE_SIZE
8212#define INT_TYPE_SIZE BITS_PER_WORD
8213#endif
8214
8215#ifndef LONG_TYPE_SIZE
8216#define LONG_TYPE_SIZE BITS_PER_WORD
8217#endif
8218
8219#ifndef LONG_LONG_TYPE_SIZE
8220#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
8221#endif
8222
8223#ifndef FLOAT_TYPE_SIZE
8224#define FLOAT_TYPE_SIZE BITS_PER_WORD
8225#endif
8226
8227#ifndef DOUBLE_TYPE_SIZE
8228#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8229#endif
8230
8231#ifndef LONG_DOUBLE_TYPE_SIZE
8232#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8233#endif
210aa14a
RS		 8234
8235unsigned long
fc27d102 8236sparc_type_code (register tree type)
210aa14a
RS		 8237{
8238 register unsigned long qualifiers = 0;
e5e809f4 8239 register unsigned shift;
210aa14a 8240
abc95ed3 8241 /* Only the first 30 bits of the qualifier are valid. We must refrain from
aee2c3c5
JW		 8242 setting more, since some assemblers will give an error for this. Also,
8243 we must be careful to avoid shifts of 32 bits or more to avoid getting
8244 unpredictable results. */
8245
e5e809f4 8246 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
210aa14a
RS		 8247 {
8248 switch (TREE_CODE (type))
8249 {
8250 case ERROR_MARK:
8251 return qualifiers;
4900aa61 8252
210aa14a 8253 case ARRAY_TYPE:
e5e809f4 8254 qualifiers |= (3 << shift);
210aa14a
RS		 8255 break;
8256
8257 case FUNCTION_TYPE:
8258 case METHOD_TYPE:
e5e809f4 8259 qualifiers |= (2 << shift);
210aa14a
RS		 8260 break;
8261
8262 case POINTER_TYPE:
8263 case REFERENCE_TYPE:
8264 case OFFSET_TYPE:
e5e809f4 8265 qualifiers |= (1 << shift);
210aa14a 8266 break;
ab835497 8267
210aa14a
RS		 8268 case RECORD_TYPE:
8269 return (qualifiers | 8);
8270
8271 case UNION_TYPE:
b0468b84 8272 case QUAL_UNION_TYPE:
210aa14a
RS		 8273 return (qualifiers | 9);
8274
8275 case ENUMERAL_TYPE:
8276 return (qualifiers | 10);
8277
8278 case VOID_TYPE:
8279 return (qualifiers | 16);
8280
8281 case INTEGER_TYPE:
654209e6
JW		 8282 /* If this is a range type, consider it to be the underlying
8283 type. */
8284 if (TREE_TYPE (type) != 0)
e5e809f4 8285 break;
654209e6 8286
77a02b01 8287 /* Carefully distinguish all the standard types of C,
b0468b84 8288 without messing up if the language is not C. We do this by
8df83eae 8289 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
b0468b84
RK		 8290 look at both the names and the above fields, but that's redundant.
8291 Any type whose size is between two C types will be considered
8292 to be the wider of the two types. Also, we do not have a
8293 special code to use for "long long", so anything wider than
8294 long is treated the same. Note that we can't distinguish
8295 between "int" and "long" in this code if they are the same
8296 size, but that's fine, since neither can the assembler. */
8297
8298 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
8df83eae 8299 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
4900aa61 8300
b0468b84 8301 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
8df83eae 8302 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
4900aa61 8303
b0468b84 8304 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
8df83eae 8305 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
4900aa61 8306
b0468b84 8307 else
8df83eae 8308 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
4900aa61 8309
210aa14a 8310 case REAL_TYPE:
e5e809f4
JL		 8311 /* If this is a range type, consider it to be the underlying
8312 type. */
8313 if (TREE_TYPE (type) != 0)
8314 break;
8315
77a02b01
JW		 8316 /* Carefully distinguish all the standard types of C,
8317 without messing up if the language is not C. */
b0468b84 8318
77a02b01 8319 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
210aa14a 8320 return (qualifiers | 6);
b0468b84 8321
4900aa61 8322 else
b0468b84 8323 return (qualifiers | 7);
4900aa61 8324
210aa14a 8325 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
13d39dbc 8326 /* ??? We need to distinguish between double and float complex types,
c82aa69a
JW		 8327 but I don't know how yet because I can't reach this code from
8328 existing front-ends. */
8329 return (qualifiers | 7); /* Who knows? */
8330
1b5963f7 8331 case VECTOR_TYPE:
62de55f7 8332 case BOOLEAN_TYPE: /* Boolean truth value type. */
0e7e1527
EB		 8333 case LANG_TYPE:
8334 case NULLPTR_TYPE:
26902ae0 8335 return qualifiers;
4900aa61 8336
210aa14a 8337 default:
f5f7d171 8338 gcc_unreachable (); /* Not a type! */
210aa14a
RS		 8339 }
8340 }
e5e809f4
JL		 8341
8342 return qualifiers;
210aa14a 8343}
ead69aea 8344\f
61a55e8b
DE		 8345/* Nested function support. */
8346
8347/* Emit RTL insns to initialize the variable parts of a trampoline.
8348 FNADDR is an RTX for the address of the function's pure code.
8349 CXT is an RTX for the static chain value for the function.
8350
8351 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
8352 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
8353 (to store insns). This is a bit excessive. Perhaps a different
8354 mechanism would be better here.
8355
849a528d 8356 Emit enough FLUSH insns to synchronize the data and instruction caches. */
61a55e8b 8357
809e78cc
RH		 8358static void
8359sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
61a55e8b 8360{
1ec0c607 8361 /* SPARC 32-bit trampoline:
c6b0465b 8362
e0d80184
DM		 8363 sethi %hi(fn), %g1
8364 sethi %hi(static), %g2
8365 jmp %g1+%lo(fn)
8366 or %g2, %lo(static), %g2
c6b0465b
JC		 8367
8368 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
8369 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
8370 */
8371
35aa3c1c 8372 emit_move_insn
809e78cc 8373 (adjust_address (m_tramp, SImode, 0),
35aa3c1c 8374 expand_binop (SImode, ior_optab,
eb6c3df1 8375 expand_shift (RSHIFT_EXPR, SImode, fnaddr, 10, 0, 1),
35aa3c1c
RK		 8376 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
8377 NULL_RTX, 1, OPTAB_DIRECT));
8378
8379 emit_move_insn
809e78cc 8380 (adjust_address (m_tramp, SImode, 4),
35aa3c1c 8381 expand_binop (SImode, ior_optab,
eb6c3df1 8382 expand_shift (RSHIFT_EXPR, SImode, cxt, 10, 0, 1),
35aa3c1c
RK		 8383 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
8384 NULL_RTX, 1, OPTAB_DIRECT));
8385
8386 emit_move_insn
809e78cc 8387 (adjust_address (m_tramp, SImode, 8),
35aa3c1c
RK		 8388 expand_binop (SImode, ior_optab,
8389 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
8390 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
8391 NULL_RTX, 1, OPTAB_DIRECT));
8392
8393 emit_move_insn
809e78cc 8394 (adjust_address (m_tramp, SImode, 12),
35aa3c1c
RK		 8395 expand_binop (SImode, ior_optab,
8396 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
8397 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
8398 NULL_RTX, 1, OPTAB_DIRECT));
c6b0465b 8399
c6b0465b
JC		 8400 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
8401 aligned on a 16 byte boundary so one flush clears it all. */
809e78cc 8402 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 0))));
84643cbf 8403 if (sparc_cpu != PROCESSOR_ULTRASPARC
4c837a1e 8404 && sparc_cpu != PROCESSOR_ULTRASPARC3
9eeaed6e
DM		 8405 && sparc_cpu != PROCESSOR_NIAGARA
8406 && sparc_cpu != PROCESSOR_NIAGARA2)
809e78cc 8407 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 8))));
1ec0c607
WH		 8408
8409 /* Call __enable_execute_stack after writing onto the stack to make sure
8410 the stack address is accessible. */
10e48e39 8411#ifdef HAVE_ENABLE_EXECUTE_STACK
f1c25d3b 8412 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
809e78cc 8413 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
1ec0c607
WH		 8414#endif
8415
61a55e8b
DE		 8416}
8417
1ec0c607 8418/* The 64-bit version is simpler because it makes more sense to load the
849a528d
RK		 8419 values as "immediate" data out of the trampoline. It's also easier since
8420 we can read the PC without clobbering a register. */
8421
809e78cc
RH		 8422static void
8423sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
61a55e8b 8424{
1ec0c607 8425 /* SPARC 64-bit trampoline:
345a6161 8426
e0d80184
DM		 8427 rd %pc, %g1
8428 ldx [%g1+24], %g5
8429 jmp %g5
8430 ldx [%g1+16], %g5
c6b0465b
JC		 8431 +16 bytes data
8432 */
8433
809e78cc 8434 emit_move_insn (adjust_address (m_tramp, SImode, 0),
e3aaacf4 8435 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
809e78cc 8436 emit_move_insn (adjust_address (m_tramp, SImode, 4),
e3aaacf4 8437 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
809e78cc 8438 emit_move_insn (adjust_address (m_tramp, SImode, 8),
e3aaacf4 8439 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
809e78cc 8440 emit_move_insn (adjust_address (m_tramp, SImode, 12),
e3aaacf4 8441 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
809e78cc
RH		 8442 emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt);
8443 emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr);
8444 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0))));
345a6161 8445
fae15c93 8446 if (sparc_cpu != PROCESSOR_ULTRASPARC
4c837a1e 8447 && sparc_cpu != PROCESSOR_ULTRASPARC3
9eeaed6e
DM		 8448 && sparc_cpu != PROCESSOR_NIAGARA
8449 && sparc_cpu != PROCESSOR_NIAGARA2)
809e78cc 8450 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8))));
1ec0c607
WH		 8451
8452 /* Call __enable_execute_stack after writing onto the stack to make sure
8453 the stack address is accessible. */
10e48e39 8454#ifdef HAVE_ENABLE_EXECUTE_STACK
f1c25d3b 8455 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
809e78cc 8456 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
1ec0c607 8457#endif
61a55e8b 8458}
809e78cc
RH		 8459
8460/* Worker for TARGET_TRAMPOLINE_INIT. */
8461
8462static void
8463sparc_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
8464{
8465 rtx fnaddr = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0));
8466 cxt = force_reg (Pmode, cxt);
8467 if (TARGET_ARCH64)
8468 sparc64_initialize_trampoline (m_tramp, fnaddr, cxt);
8469 else
8470 sparc32_initialize_trampoline (m_tramp, fnaddr, cxt);
8471}
61a55e8b 8472\f
dbb54862
JW		 8473/* Adjust the cost of a scheduling dependency. Return the new cost of
8474 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8475
8947065c 8476static int
fc27d102 8477supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
dbb54862
JW		 8478{
8479 enum attr_type insn_type;
8480
8481 if (! recog_memoized (insn))
8482 return 0;
8483
8484 insn_type = get_attr_type (insn);
8485
8486 if (REG_NOTE_KIND (link) == 0)
8487 {
8488 /* Data dependency; DEP_INSN writes a register that INSN reads some
8489 cycles later. */
8490
8491 /* if a load, then the dependence must be on the memory address;
3bc8b61e
DM		 8492 add an extra "cycle". Note that the cost could be two cycles
8493 if the reg was written late in an instruction group; we ca not tell
dbb54862
JW		 8494 here. */
8495 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
8496 return cost + 3;
8497
8498 /* Get the delay only if the address of the store is the dependence. */
8499 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
8500 {
8501 rtx pat = PATTERN(insn);
8502 rtx dep_pat = PATTERN (dep_insn);
8503
8504 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3bc8b61e 8505 return cost; /* This should not happen! */
dbb54862
JW		 8506
8507 /* The dependency between the two instructions was on the data that
8508 is being stored. Assume that this implies that the address of the
8509 store is not dependent. */
8510 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8511 return cost;
8512
8513 return cost + 3; /* An approximation. */
8514 }
8515
8516 /* A shift instruction cannot receive its data from an instruction
8517 in the same cycle; add a one cycle penalty. */
8518 if (insn_type == TYPE_SHIFT)
8519 return cost + 3; /* Split before cascade into shift. */
8520 }
8521 else
8522 {
8523 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8524 INSN writes some cycles later. */
8525
8526 /* These are only significant for the fpu unit; writing a fp reg before
8527 the fpu has finished with it stalls the processor. */
8528
8529 /* Reusing an integer register causes no problems. */
8530 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8531 return 0;
8532 }
8533
8534 return cost;
8535}
bfd6bc60 8536
8947065c 8537static int
fc27d102 8538hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8947065c
RH		 8539{
8540 enum attr_type insn_type, dep_type;
8541 rtx pat = PATTERN(insn);
8542 rtx dep_pat = PATTERN (dep_insn);
8543
8544 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
8545 return cost;
8546
8547 insn_type = get_attr_type (insn);
8548 dep_type = get_attr_type (dep_insn);
8549
8550 switch (REG_NOTE_KIND (link))
8551 {
8552 case 0:
8553 /* Data dependency; DEP_INSN writes a register that INSN reads some
8554 cycles later. */
8555
8556 switch (insn_type)
8557 {
8558 case TYPE_STORE:
8559 case TYPE_FPSTORE:
80ffc95e 8560 /* Get the delay iff the address of the store is the dependence. */
8947065c
RH		 8561 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8562 return cost;
8563
8564 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8565 return cost;
8566 return cost + 3;
8567
8568 case TYPE_LOAD:
8569 case TYPE_SLOAD:
8570 case TYPE_FPLOAD:
8571 /* If a load, then the dependence must be on the memory address. If
8572 the addresses aren't equal, then it might be a false dependency */
8573 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
8574 {
8575 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
4900aa61 8576 || GET_CODE (SET_DEST (dep_pat)) != MEM
8947065c
RH		 8577 || GET_CODE (SET_SRC (pat)) != MEM
8578 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
8579 XEXP (SET_SRC (pat), 0)))
8580 return cost + 2;
8581
4900aa61 8582 return cost + 8;
8947065c
RH		 8583 }
8584 break;
8585
8586 case TYPE_BRANCH:
8587 /* Compare to branch latency is 0. There is no benefit from
8588 separating compare and branch. */
8589 if (dep_type == TYPE_COMPARE)
8590 return 0;
8591 /* Floating point compare to branch latency is less than
8592 compare to conditional move. */
8593 if (dep_type == TYPE_FPCMP)
8594 return cost - 1;
8595 break;
3bb5de61
KG		 8596 default:
8597 break;
8947065c
RH		 8598 }
8599 break;
8600
8601 case REG_DEP_ANTI:
80ffc95e 8602 /* Anti-dependencies only penalize the fpu unit. */
8947065c
RH		 8603 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8604 return 0;
8605 break;
8606
8607 default:
8608 break;
4900aa61 8609 }
8947065c
RH		 8610
8611 return cost;
8612}
8613
c237e94a 8614static int
fc27d102 8615sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8947065c
RH		 8616{
8617 switch (sparc_cpu)
8618 {
8619 case PROCESSOR_SUPERSPARC:
8620 cost = supersparc_adjust_cost (insn, link, dep, cost);
8621 break;
8622 case PROCESSOR_HYPERSPARC:
8623 case PROCESSOR_SPARCLITE86X:
8624 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8625 break;
8947065c
RH		 8626 default:
8627 break;
8628 }
8629 return cost;
8630}
8631
fae15c93 8632static void
fc27d102
KG		 8633sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8634 int sched_verbose ATTRIBUTE_UNUSED,
8635 int max_ready ATTRIBUTE_UNUSED)
4900aa61
EB		 8636{}
8637
fae15c93 8638static int
fc27d102 8639sparc_use_sched_lookahead (void)
fae15c93 8640{
9eeaed6e
DM		 8641 if (sparc_cpu == PROCESSOR_NIAGARA
8642 || sparc_cpu == PROCESSOR_NIAGARA2)
4c837a1e 8643 return 0;
fae15c93
VM		 8644 if (sparc_cpu == PROCESSOR_ULTRASPARC
8645 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8646 return 4;
8647 if ((1 << sparc_cpu) &
8648 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8649 (1 << PROCESSOR_SPARCLITE86X)))
8650 return 3;
3bc8b61e
DM		 8651 return 0;
8652}
8653
fae15c93 8654static int
fc27d102 8655sparc_issue_rate (void)
bfd6bc60
JC		 8656{
8657 switch (sparc_cpu)
8658 {
4c837a1e 8659 case PROCESSOR_NIAGARA:
9eeaed6e 8660 case PROCESSOR_NIAGARA2:
fae15c93
VM		 8661 default:
8662 return 1;
8663 case PROCESSOR_V9:
284d86e9 8664 /* Assume V9 processors are capable of at least dual-issue. */
bfd6bc60 8665 return 2;
fae15c93
VM		 8666 case PROCESSOR_SUPERSPARC:
8667 return 3;
393049a9
RH		 8668 case PROCESSOR_HYPERSPARC:
8669 case PROCESSOR_SPARCLITE86X:
8670 return 2;
fae15c93
VM		 8671 case PROCESSOR_ULTRASPARC:
8672 case PROCESSOR_ULTRASPARC3:
8673 return 4;
bfd6bc60
JC		 8674 }
8675}
284d86e9
JC		 8676
8677static int
fc27d102 8678set_extends (rtx insn)
284d86e9
JC		 8679{
8680 register rtx pat = PATTERN (insn);
8681
8682 switch (GET_CODE (SET_SRC (pat)))
8683 {
80ffc95e 8684 /* Load and some shift instructions zero extend. */
284d86e9
JC		 8685 case MEM:
8686 case ZERO_EXTEND:
8687 /* sethi clears the high bits */
8688 case HIGH:
8689 /* LO_SUM is used with sethi. sethi cleared the high
8690 bits and the values used with lo_sum are positive */
8691 case LO_SUM:
284d86e9
JC		 8692 /* Store flag stores 0 or 1 */
8693 case LT: case LTU:
8694 case GT: case GTU:
8695 case LE: case LEU:
8696 case GE: case GEU:
8697 case EQ:
8698 case NE:
8699 return 1;
8700 case AND:
8701 {
4df1190a 8702 rtx op0 = XEXP (SET_SRC (pat), 0);
284d86e9
JC		 8703 rtx op1 = XEXP (SET_SRC (pat), 1);
8704 if (GET_CODE (op1) == CONST_INT)
8705 return INTVAL (op1) >= 0;
4df1190a
JJ		 8706 if (GET_CODE (op0) != REG)
8707 return 0;
8708 if (sparc_check_64 (op0, insn) == 1)
284d86e9 8709 return 1;
4df1190a
JJ		 8710 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8711 }
8712 case IOR:
8713 case XOR:
8714 {
8715 rtx op0 = XEXP (SET_SRC (pat), 0);
8716 rtx op1 = XEXP (SET_SRC (pat), 1);
8717 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8718 return 0;
8719 if (GET_CODE (op1) == CONST_INT)
8720 return INTVAL (op1) >= 0;
8721 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
284d86e9 8722 }
284d86e9
JC		 8723 case LSHIFTRT:
8724 return GET_MODE (SET_SRC (pat)) == SImode;
80ffc95e 8725 /* Positive integers leave the high bits zero. */
284d86e9 8726 case CONST_DOUBLE:
4df1190a 8727 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
284d86e9 8728 case CONST_INT:
4df1190a 8729 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
284d86e9
JC		 8730 case ASHIFTRT:
8731 case SIGN_EXTEND:
8732 return - (GET_MODE (SET_SRC (pat)) == SImode);
4df1190a
JJ		 8733 case REG:
8734 return sparc_check_64 (SET_SRC (pat), insn);
284d86e9
JC		 8735 default:
8736 return 0;
8737 }
8738}
8739
80ffc95e 8740/* We _ought_ to have only one kind per function, but... */
e2500fed
GK		 8741static GTY(()) rtx sparc_addr_diff_list;
8742static GTY(()) rtx sparc_addr_list;
e0d80184
DM		 8743
8744void
fc27d102 8745sparc_defer_case_vector (rtx lab, rtx vec, int diff)
e0d80184
DM		 8746{
8747 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8748 if (diff)
8749 sparc_addr_diff_list
8750 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8751 else
8752 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8753}
8754
4900aa61 8755static void
fc27d102 8756sparc_output_addr_vec (rtx vec)
e0d80184
DM		 8757{
8758 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8759 int idx, vlen = XVECLEN (body, 0);
8760
4900aa61 8761#ifdef ASM_OUTPUT_ADDR_VEC_START
d1accaa3
JJ		 8762 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8763#endif
8764
e0d80184
DM		 8765#ifdef ASM_OUTPUT_CASE_LABEL
8766 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8767 NEXT_INSN (lab));
8768#else
4977bab6 8769 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
e0d80184
DM		 8770#endif
8771
8772 for (idx = 0; idx < vlen; idx++)
8773 {
8774 ASM_OUTPUT_ADDR_VEC_ELT
8775 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8776 }
4900aa61 8777
d1accaa3
JJ		 8778#ifdef ASM_OUTPUT_ADDR_VEC_END
8779 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8780#endif
e0d80184
DM		 8781}
8782
4900aa61 8783static void
fc27d102 8784sparc_output_addr_diff_vec (rtx vec)
e0d80184
DM		 8785{
8786 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8787 rtx base = XEXP (XEXP (body, 0), 0);
8788 int idx, vlen = XVECLEN (body, 1);
8789
4900aa61 8790#ifdef ASM_OUTPUT_ADDR_VEC_START
d1accaa3
JJ		 8791 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8792#endif
8793
e0d80184
DM		 8794#ifdef ASM_OUTPUT_CASE_LABEL
8795 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8796 NEXT_INSN (lab));
8797#else
4977bab6 8798 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
e0d80184
DM		 8799#endif
8800
8801 for (idx = 0; idx < vlen; idx++)
8802 {
8803 ASM_OUTPUT_ADDR_DIFF_ELT
8804 (asm_out_file,
8805 body,
8806 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8807 CODE_LABEL_NUMBER (base));
8808 }
4900aa61 8809
d1accaa3
JJ		 8810#ifdef ASM_OUTPUT_ADDR_VEC_END
8811 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8812#endif
e0d80184
DM		 8813}
8814
8815static void
fc27d102 8816sparc_output_deferred_case_vectors (void)
e0d80184
DM		 8817{
8818 rtx t;
d676da68 8819 int align;
e0d80184 8820
f3b8847b
DM		 8821 if (sparc_addr_list == NULL_RTX
8822 && sparc_addr_diff_list == NULL_RTX)
8823 return;
8824
e0d80184 8825 /* Align to cache line in the function's code section. */
d6b5193b 8826 switch_to_section (current_function_section ());
d676da68
DM		 8827
8828 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8829 if (align > 0)
f3b8847b 8830 ASM_OUTPUT_ALIGN (asm_out_file, align);
4900aa61 8831
e0d80184
DM		 8832 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8833 sparc_output_addr_vec (XEXP (t, 0));
8834 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8835 sparc_output_addr_diff_vec (XEXP (t, 0));
8836
8837 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8838}
8839
284d86e9
JC		 8840/* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8841 unknown. Return 1 if the high bits are zero, -1 if the register is
8842 sign extended. */
8843int
fc27d102 8844sparc_check_64 (rtx x, rtx insn)
284d86e9
JC		 8845{
8846 /* If a register is set only once it is safe to ignore insns this
8847 code does not know how to handle. The loop will either recognize
8848 the single set and return the correct value or fail to recognize
8849 it and return 0. */
8850 int set_once = 0;
4df1190a
JJ		 8851 rtx y = x;
8852
f5f7d171 8853 gcc_assert (GET_CODE (x) == REG);
4df1190a
JJ		 8854
8855 if (GET_MODE (x) == DImode)
8856 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
284d86e9 8857
4df1190a 8858 if (flag_expensive_optimizations
b718216c 8859 && df && DF_REG_DEF_COUNT (REGNO (y)) == 1)
284d86e9
JC		 8860 set_once = 1;
8861
8862 if (insn == 0)
d6f4ec51
KG		 8863 {
8864 if (set_once)
8865 insn = get_last_insn_anywhere ();
8866 else
8867 return 0;
8868 }
284d86e9 8869
d6f4ec51 8870 while ((insn = PREV_INSN (insn)))
284d86e9
JC		 8871 {
8872 switch (GET_CODE (insn))
8873 {
8874 case JUMP_INSN:
8875 case NOTE:
8876 break;
8877 case CODE_LABEL:
8878 case CALL_INSN:
8879 default:
8880 if (! set_once)
8881 return 0;
8882 break;
8883 case INSN:
8884 {
8885 rtx pat = PATTERN (insn);
8886 if (GET_CODE (pat) != SET)
8887 return 0;
8888 if (rtx_equal_p (x, SET_DEST (pat)))
4df1190a
JJ		 8889 return set_extends (insn);
8890 if (y && rtx_equal_p (y, SET_DEST (pat)))
8891 return set_extends (insn);
8892 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
284d86e9
JC		 8893 return 0;
8894 }
8895 }
8896 }
8897 return 0;
8898}
8899
01d3224a
EB		 8900/* Returns assembly code to perform a DImode shift using
8901 a 64-bit global or out register on SPARC-V8+. */
a6163c22
EB		 8902const char *
8903output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
284d86e9
JC		 8904{
8905 static char asm_code[60];
8906
01d3224a
EB		 8907 /* The scratch register is only required when the destination
8908 register is not a 64-bit global or out register. */
8909 if (which_alternative != 2)
284d86e9 8910 operands[3] = operands[0];
01d3224a 8911
1c8b4e29
EB		 8912 /* We can only shift by constants <= 63. */
8913 if (GET_CODE (operands[2]) == CONST_INT)
8914 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8915
c6b0465b
JC		 8916 if (GET_CODE (operands[1]) == CONST_INT)
8917 {
4df1190a 8918 output_asm_insn ("mov\t%1, %3", operands);
c6b0465b
JC		 8919 }
8920 else
8921 {
4df1190a 8922 output_asm_insn ("sllx\t%H1, 32, %3", operands);
c6b0465b 8923 if (sparc_check_64 (operands[1], insn) <= 0)
4df1190a
JJ		 8924 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8925 output_asm_insn ("or\t%L1, %3, %3", operands);
c6b0465b 8926 }
284d86e9
JC		 8927
8928 strcpy(asm_code, opcode);
01d3224a 8929
284d86e9 8930 if (which_alternative != 2)
4df1190a 8931 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
284d86e9 8932 else
4df1190a 8933 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
284d86e9 8934}
2be15d0f 8935\f
89a8b315
RH		 8936/* Output rtl to increment the profiler label LABELNO
8937 for profiling a function entry. */
2be15d0f
RH		 8938
8939void
fc27d102 8940sparc_profile_hook (int labelno)
2be15d0f
RH		 8941{
8942 char buf[32];
89a8b315 8943 rtx lab, fun;
2be15d0f 8944
89a8b315 8945 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
cc44abe6
DM		 8946 if (NO_PROFILE_COUNTERS)
8947 {
8948 emit_library_call (fun, LCT_NORMAL, VOIDmode, 0);
8949 }
8950 else
8951 {
8952 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8953 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8954 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8955 }
2be15d0f 8956}
89a8b315 8957\f
2ca48caa 8958#ifdef TARGET_SOLARIS
d1ced155
EB		 8959/* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
8960
7c262518 8961static void
d1ced155
EB		 8962sparc_solaris_elf_asm_named_section (const char *name, unsigned int flags,
8963 tree decl ATTRIBUTE_UNUSED)
7c262518 8964{
2ca48caa
RO		 8965 if (HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE)
8966 {
8967 solaris_elf_asm_comdat_section (name, flags, decl);
8968 return;
8969 }
8970
7c262518
RH		 8971 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8972
8973 if (!(flags & SECTION_DEBUG))
8974 fputs (",#alloc", asm_out_file);
8975 if (flags & SECTION_WRITE)
8976 fputs (",#write", asm_out_file);
2f3321ca
EB		 8977 if (flags & SECTION_TLS)
8978 fputs (",#tls", asm_out_file);
7c262518
RH		 8979 if (flags & SECTION_CODE)
8980 fputs (",#execinstr", asm_out_file);
8981
8982 /* ??? Handle SECTION_BSS. */
8983
8984 fputc ('\n', asm_out_file);
8985}
2ca48caa 8986#endif /* TARGET_SOLARIS */
f451b552 8987
60b85c4c 8988/* We do not allow indirect calls to be optimized into sibling calls.
951661a1
EB		 8989
8990 We cannot use sibling calls when delayed branches are disabled
8991 because they will likely require the call delay slot to be filled.
8992
60b85c4c 8993 Also, on SPARC 32-bit we cannot emit a sibling call when the
4977bab6
ZW		 8994 current function returns a structure. This is because the "unimp
8995 after call" convention would cause the callee to return to the
8996 wrong place. The generic code already disallows cases where the
8997 function being called returns a structure.
8998
8999 It may seem strange how this last case could occur. Usually there
9000 is code after the call which jumps to epilogue code which dumps the
9001 return value into the struct return area. That ought to invalidate
951661a1 9002 the sibling call right? Well, in the C++ case we can end up passing
4977bab6
ZW		 9003 the pointer to the struct return area to a constructor (which returns
9004 void) and then nothing else happens. Such a sibling call would look
1910440e
RS		 9005 valid without the added check here.
9006
9007 VxWorks PIC PLT entries require the global pointer to be initialized
9008 on entry. We therefore can't emit sibling calls to them. */
4977bab6 9009static bool
fc27d102 9010sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
4977bab6 9011{
951661a1
EB		 9012 return (decl
9013 && flag_delayed_branch
e3b5732b 9014 && (TARGET_ARCH64 || ! cfun->returns_struct)
1910440e
RS		 9015 && !(TARGET_VXWORKS_RTP
9016 && flag_pic
9017 && !targetm.binds_local_p (decl)));
4977bab6 9018}
c15c90bb
ZW		 9019\f
9020/* libfunc renaming. */
c15c90bb
ZW		 9021
9022static void
9023sparc_init_libfuncs (void)
9024{
9025 if (TARGET_ARCH32)
9026 {
9027 /* Use the subroutines that Sun's library provides for integer
9028 multiply and divide. The `*' prevents an underscore from
9029 being prepended by the compiler. .umul is a little faster
ff482c8d 9030 than .mul. */
c15c90bb
ZW		 9031 set_optab_libfunc (smul_optab, SImode, "*.umul");
9032 set_optab_libfunc (sdiv_optab, SImode, "*.div");
9033 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
9034 set_optab_libfunc (smod_optab, SImode, "*.rem");
9035 set_optab_libfunc (umod_optab, SImode, "*.urem");
9036
9037 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9038 set_optab_libfunc (add_optab, TFmode, "_Q_add");
9039 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
9040 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
9041 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
9042 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
9043
9044 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9045 is because with soft-float, the SFmode and DFmode sqrt
9046 instructions will be absent, and the compiler will notice and
9047 try to use the TFmode sqrt instruction for calls to the
9048 builtin function sqrt, but this fails. */
9049 if (TARGET_FPU)
9050 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
9051
c9034561
ZW		 9052 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
9053 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
9054 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
9055 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
9056 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
9057 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
c15c90bb 9058
85363ca0
ZW		 9059 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
9060 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
9061 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
9062 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
9063
9064 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
9065 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
9066 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
9b336fa4 9067 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_Q_utoq");
c15c90bb 9068
45dcc026
JJ		 9069 if (DITF_CONVERSION_LIBFUNCS)
9070 {
9071 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
9072 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
9073 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
9b336fa4 9074 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq");
45dcc026
JJ		 9075 }
9076
c15c90bb
ZW		 9077 if (SUN_CONVERSION_LIBFUNCS)
9078 {
85363ca0
ZW		 9079 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
9080 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
9081 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
9082 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
c15c90bb
ZW		 9083 }
9084 }
9085 if (TARGET_ARCH64)
9086 {
9087 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9088 do not exist in the library. Make sure the compiler does not
9089 emit calls to them by accident. (It should always use the
9090 hardware instructions.) */
9091 set_optab_libfunc (smul_optab, SImode, 0);
9092 set_optab_libfunc (sdiv_optab, SImode, 0);
9093 set_optab_libfunc (udiv_optab, SImode, 0);
9094 set_optab_libfunc (smod_optab, SImode, 0);
9095 set_optab_libfunc (umod_optab, SImode, 0);
9096
9097 if (SUN_INTEGER_MULTIPLY_64)
9098 {
9099 set_optab_libfunc (smul_optab, DImode, "__mul64");
9100 set_optab_libfunc (sdiv_optab, DImode, "__div64");
9101 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
9102 set_optab_libfunc (smod_optab, DImode, "__rem64");
9103 set_optab_libfunc (umod_optab, DImode, "__urem64");
9104 }
9105
9106 if (SUN_CONVERSION_LIBFUNCS)
9107 {
85363ca0
ZW		 9108 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
9109 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
9110 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
9111 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
c15c90bb
ZW		 9112 }
9113 }
c15c90bb
ZW		 9114}
9115\f
16f59241 9116#define def_builtin(NAME, CODE, TYPE) \
c79efc4d
RÁE		 9117 add_builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \
9118 NULL_TREE)
16f59241
JM		 9119
9120/* Implement the TARGET_INIT_BUILTINS target hook.
9121 Create builtin functions for special SPARC instructions. */
9122
9123static void
9124sparc_init_builtins (void)
9125{
9126 if (TARGET_VIS)
9127 sparc_vis_init_builtins ();
9128}
9129
9130/* Create builtin functions for VIS 1.0 instructions. */
9131
9132static void
9133sparc_vis_init_builtins (void)
9134{
9135 tree v4qi = build_vector_type (unsigned_intQI_type_node, 4);
9136 tree v8qi = build_vector_type (unsigned_intQI_type_node, 8);
9137 tree v4hi = build_vector_type (intHI_type_node, 4);
9138 tree v2hi = build_vector_type (intHI_type_node, 2);
9139 tree v2si = build_vector_type (intSI_type_node, 2);
9140
9141 tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0);
9142 tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0);
9143 tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0);
9144 tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0);
9145 tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0);
9146 tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0);
9147 tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0);
9148 tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0);
9149 tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0);
9150 tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0);
9151 tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0);
9152 tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0);
9153 tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node,
9154 v8qi, v8qi,
9155 intDI_type_node, 0);
9156 tree di_ftype_di_di = build_function_type_list (intDI_type_node,
9157 intDI_type_node,
9158 intDI_type_node, 0);
9159 tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node,
9160 ptr_type_node,
9161 intSI_type_node, 0);
9162 tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node,
9163 ptr_type_node,
9164 intDI_type_node, 0);
9165
9166 /* Packing and expanding vectors. */
9167 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis, v4qi_ftype_v4hi);
9168 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
9169 v8qi_ftype_v2si_v8qi);
9170 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
9171 v2hi_ftype_v2si);
9172 def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis, v4hi_ftype_v4qi);
9173 def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis,
9174 v8qi_ftype_v4qi_v4qi);
9175
9176 /* Multiplications. */
9177 def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis,
9178 v4hi_ftype_v4qi_v4hi);
9179 def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis,
9180 v4hi_ftype_v4qi_v2hi);
9181 def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis,
9182 v4hi_ftype_v4qi_v2hi);
9183 def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis,
9184 v4hi_ftype_v8qi_v4hi);
9185 def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis,
9186 v4hi_ftype_v8qi_v4hi);
9187 def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis,
9188 v2si_ftype_v4qi_v2hi);
9189 def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis,
9190 v2si_ftype_v4qi_v2hi);
9191
9192 /* Data aligning. */
9193 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
9194 v4hi_ftype_v4hi_v4hi);
9195 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
9196 v8qi_ftype_v8qi_v8qi);
9197 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
9198 v2si_ftype_v2si_v2si);
9199 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis,
9200 di_ftype_di_di);
9201 if (TARGET_ARCH64)
9202 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
9203 ptr_ftype_ptr_di);
9204 else
9205 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
9206 ptr_ftype_ptr_si);
9207
9208 /* Pixel distance. */
9209 def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
9210 di_ftype_v8qi_v8qi_di);
9211}
9212
9213/* Handle TARGET_EXPAND_BUILTIN target hook.
0fa2e4df 9214 Expand builtin functions for sparc intrinsics. */
16f59241
JM		 9215
9216static rtx
724d7c55
EB		 9217sparc_expand_builtin (tree exp, rtx target,
9218 rtx subtarget ATTRIBUTE_UNUSED,
9219 enum machine_mode tmode ATTRIBUTE_UNUSED,
9220 int ignore ATTRIBUTE_UNUSED)
16f59241 9221{
5039610b
SL		 9222 tree arg;
9223 call_expr_arg_iterator iter;
9224 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
16f59241
JM		 9225 unsigned int icode = DECL_FUNCTION_CODE (fndecl);
9226 rtx pat, op[4];
9227 enum machine_mode mode[4];
9228 int arg_count = 0;
9229
724d7c55
EB		 9230 mode[0] = insn_data[icode].operand[0].mode;
9231 if (!target
9232 || GET_MODE (target) != mode[0]
9233 || ! (*insn_data[icode].operand[0].predicate) (target, mode[0]))
9234 op[0] = gen_reg_rtx (mode[0]);
16f59241 9235 else
724d7c55 9236 op[0] = target;
16f59241 9237
5039610b 9238 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
16f59241 9239 {
16f59241
JM		 9240 arg_count++;
9241 mode[arg_count] = insn_data[icode].operand[arg_count].mode;
84217346 9242 op[arg_count] = expand_normal (arg);
16f59241
JM		 9243
9244 if (! (*insn_data[icode].operand[arg_count].predicate) (op[arg_count],
9245 mode[arg_count]))
9246 op[arg_count] = copy_to_mode_reg (mode[arg_count], op[arg_count]);
9247 }
9248
9249 switch (arg_count)
9250 {
9251 case 1:
9252 pat = GEN_FCN (icode) (op[0], op[1]);
9253 break;
9254 case 2:
9255 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
9256 break;
9257 case 3:
9258 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
9259 break;
9260 default:
9261 gcc_unreachable ();
9262 }
9263
9264 if (!pat)
9265 return NULL_RTX;
9266
9267 emit_insn (pat);
9268
9269 return op[0];
9270}
8b0096b4
JM		 9271
9272static int
9273sparc_vis_mul8x16 (int e8, int e16)
9274{
9275 return (e8 * e16 + 128) / 256;
9276}
9277
9278/* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
9279 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
9280 constants. A tree list with the results of the multiplications is returned,
9281 and each element in the list is of INNER_TYPE. */
9282
9283static tree
9284sparc_handle_vis_mul8x16 (int fncode, tree inner_type, tree elts0, tree elts1)
9285{
9286 tree n_elts = NULL_TREE;
9287 int scale;
9288
9289 switch (fncode)
9290 {
9291 case CODE_FOR_fmul8x16_vis:
9292 for (; elts0 && elts1;
9293 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
9294 {
9295 int val
9296 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9297 TREE_INT_CST_LOW (TREE_VALUE (elts1)));
9298 n_elts = tree_cons (NULL_TREE,
9299 build_int_cst (inner_type, val),
9300 n_elts);
9301 }
9302 break;
9303
9304 case CODE_FOR_fmul8x16au_vis:
9305 scale = TREE_INT_CST_LOW (TREE_VALUE (elts1));
9306
9307 for (; elts0; elts0 = TREE_CHAIN (elts0))
9308 {
9309 int val
9310 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9311 scale);
9312 n_elts = tree_cons (NULL_TREE,
9313 build_int_cst (inner_type, val),
9314 n_elts);
9315 }
9316 break;
9317
9318 case CODE_FOR_fmul8x16al_vis:
9319 scale = TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1)));
9320
9321 for (; elts0; elts0 = TREE_CHAIN (elts0))
9322 {
9323 int val
9324 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9325 scale);
9326 n_elts = tree_cons (NULL_TREE,
9327 build_int_cst (inner_type, val),
9328 n_elts);
9329 }
9330 break;
9331
9332 default:
9333 gcc_unreachable ();
9334 }
9335
9336 return nreverse (n_elts);
9337
9338}
9339/* Handle TARGET_FOLD_BUILTIN target hook.
607fb860 9340 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
8b0096b4
JM		 9341 result of the function call is ignored. NULL_TREE is returned if the
9342 function could not be folded. */
9343
9344static tree
f311c3b4
NF		 9345sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED,
9346 tree *args, bool ignore)
8b0096b4
JM		 9347{
9348 tree arg0, arg1, arg2;
9349 tree rtype = TREE_TYPE (TREE_TYPE (fndecl));
bbbbb16a 9350 enum insn_code icode = (enum insn_code) DECL_FUNCTION_CODE (fndecl);
8b0096b4 9351
724d7c55 9352 if (ignore
bbbbb16a
ILT		 9353 && icode != CODE_FOR_alignaddrsi_vis
9354 && icode != CODE_FOR_alignaddrdi_vis)
e8160c9a 9355 return build_zero_cst (rtype);
8b0096b4 9356
bbbbb16a 9357 switch (icode)
8b0096b4
JM		 9358 {
9359 case CODE_FOR_fexpand_vis:
f311c3b4 9360 arg0 = args[0];
8b0096b4
JM		 9361 STRIP_NOPS (arg0);
9362
9363 if (TREE_CODE (arg0) == VECTOR_CST)
9364 {
9365 tree inner_type = TREE_TYPE (rtype);
9366 tree elts = TREE_VECTOR_CST_ELTS (arg0);
9367 tree n_elts = NULL_TREE;
9368
9369 for (; elts; elts = TREE_CHAIN (elts))
9370 {
9371 unsigned int val = TREE_INT_CST_LOW (TREE_VALUE (elts)) << 4;
9372 n_elts = tree_cons (NULL_TREE,
9373 build_int_cst (inner_type, val),
9374 n_elts);
9375 }
9376 return build_vector (rtype, nreverse (n_elts));
9377 }
9378 break;
9379
9380 case CODE_FOR_fmul8x16_vis:
9381 case CODE_FOR_fmul8x16au_vis:
9382 case CODE_FOR_fmul8x16al_vis:
f311c3b4
NF		 9383 arg0 = args[0];
9384 arg1 = args[1];
8b0096b4
JM		 9385 STRIP_NOPS (arg0);
9386 STRIP_NOPS (arg1);
9387
9388 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
9389 {
9390 tree inner_type = TREE_TYPE (rtype);
9391 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
9392 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
bbbbb16a
ILT		 9393 tree n_elts = sparc_handle_vis_mul8x16 (icode, inner_type, elts0,
9394 elts1);
8b0096b4
JM		 9395
9396 return build_vector (rtype, n_elts);
9397 }
9398 break;
9399
9400 case CODE_FOR_fpmerge_vis:
f311c3b4
NF		 9401 arg0 = args[0];
9402 arg1 = args[1];
8b0096b4
JM		 9403 STRIP_NOPS (arg0);
9404 STRIP_NOPS (arg1);
9405
9406 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
9407 {
9408 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
9409 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
9410 tree n_elts = NULL_TREE;
9411
9412 for (; elts0 && elts1;
9413 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
9414 {
9415 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts0), n_elts);
9416 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts1), n_elts);
9417 }
9418
9419 return build_vector (rtype, nreverse (n_elts));
9420 }
9421 break;
9422
9423 case CODE_FOR_pdist_vis:
f311c3b4
NF		 9424 arg0 = args[0];
9425 arg1 = args[1];
9426 arg2 = args[2];
8b0096b4
JM		 9427 STRIP_NOPS (arg0);
9428 STRIP_NOPS (arg1);
9429 STRIP_NOPS (arg2);
9430
9431 if (TREE_CODE (arg0) == VECTOR_CST
9432 && TREE_CODE (arg1) == VECTOR_CST
9433 && TREE_CODE (arg2) == INTEGER_CST)
9434 {
9435 int overflow = 0;
9436 unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (arg2);
9437 HOST_WIDE_INT high = TREE_INT_CST_HIGH (arg2);
9438 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
9439 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
9440
9441 for (; elts0 && elts1;
9442 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
9443 {
9444 unsigned HOST_WIDE_INT
9445 low0 = TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9446 low1 = TREE_INT_CST_LOW (TREE_VALUE (elts1));
9447 HOST_WIDE_INT high0 = TREE_INT_CST_HIGH (TREE_VALUE (elts0));
9448 HOST_WIDE_INT high1 = TREE_INT_CST_HIGH (TREE_VALUE (elts1));
9449
9450 unsigned HOST_WIDE_INT l;
9451 HOST_WIDE_INT h;
9452
9453 overflow |= neg_double (low1, high1, &l, &h);
9454 overflow |= add_double (low0, high0, l, h, &l, &h);
9455 if (h < 0)
9456 overflow |= neg_double (l, h, &l, &h);
9457
9458 overflow |= add_double (low, high, l, h, &low, &high);
9459 }
9460
9461 gcc_assert (overflow == 0);
9462
9463 return build_int_cst_wide (rtype, low, high);
9464 }
9465
9466 default:
9467 break;
9468 }
724d7c55 9469
8b0096b4
JM		 9470 return NULL_TREE;
9471}
16f59241 9472\f
214c6394
DM		 9473/* ??? This duplicates information provided to the compiler by the
9474 ??? scheduler description. Some day, teach genautomata to output
9475 ??? the latencies and then CSE will just use that. */
9476
3c50106f 9477static bool
f40751dd
JH		 9478sparc_rtx_costs (rtx x, int code, int outer_code, int *total,
9479 bool speed ATTRIBUTE_UNUSED)
2ce04b6b 9480{
18df6de9
DM		 9481 enum machine_mode mode = GET_MODE (x);
9482 bool float_mode_p = FLOAT_MODE_P (mode);
9483
2ce04b6b
DM		 9484 switch (code)
9485 {
18df6de9
DM		 9486 case CONST_INT:
9487 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
214c6394 9488 {
18df6de9 9489 *total = 0;
3c50106f 9490 return true;
214c6394 9491 }
18df6de9 9492 /* FALLTHRU */
214c6394 9493
18df6de9
DM		 9494 case HIGH:
9495 *total = 2;
9496 return true;
214c6394 9497
18df6de9
DM		 9498 case CONST:
9499 case LABEL_REF:
9500 case SYMBOL_REF:
9501 *total = 4;
9502 return true;
214c6394 9503
18df6de9 9504 case CONST_DOUBLE:
ca075703
DM		 9505 if (GET_MODE (x) == VOIDmode
9506 && ((CONST_DOUBLE_HIGH (x) == 0
9507 && CONST_DOUBLE_LOW (x) < 0x1000)
9508 || (CONST_DOUBLE_HIGH (x) == -1
9509 && CONST_DOUBLE_LOW (x) < 0
9510 && CONST_DOUBLE_LOW (x) >= -0x1000)))
18df6de9
DM		 9511 *total = 0;
9512 else
9513 *total = 8;
3c50106f 9514 return true;
214c6394 9515
18df6de9
DM		 9516 case MEM:
9517 /* If outer-code was a sign or zero extension, a cost
9518 of COSTS_N_INSNS (1) was already added in. This is
9519 why we are subtracting it back out. */
9520 if (outer_code == ZERO_EXTEND)
214c6394 9521 {
18df6de9 9522 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
214c6394 9523 }
18df6de9 9524 else if (outer_code == SIGN_EXTEND)
3c50106f 9525 {
18df6de9 9526 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
3c50106f 9527 }
18df6de9 9528 else if (float_mode_p)
3c50106f 9529 {
18df6de9 9530 *total = sparc_costs->float_load;
3c50106f 9531 }
18df6de9 9532 else
3c50106f 9533 {
18df6de9 9534 *total = sparc_costs->int_load;
3c50106f 9535 }
214c6394 9536
3c50106f 9537 return true;
2ce04b6b 9538
18df6de9
DM		 9539 case PLUS:
9540 case MINUS:
9541 if (float_mode_p)
9542 *total = sparc_costs->float_plusminus;
9543 else
9544 *total = COSTS_N_INSNS (1);
9545 return false;
214c6394 9546
18df6de9
DM		 9547 case MULT:
9548 if (float_mode_p)
9549 *total = sparc_costs->float_mul;
e08eb33c 9550 else if (! TARGET_HARD_MUL)
bf6c40e9 9551 *total = COSTS_N_INSNS (25);
18df6de9
DM		 9552 else
9553 {
9554 int bit_cost;
214c6394 9555
18df6de9
DM		 9556 bit_cost = 0;
9557 if (sparc_costs->int_mul_bit_factor)
9558 {
9559 int nbits;
214c6394 9560
18df6de9
DM		 9561 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
9562 {
9563 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
9564 for (nbits = 0; value != 0; value &= value - 1)
9565 nbits++;
9566 }
9567 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
ca075703 9568 && GET_MODE (XEXP (x, 1)) == VOIDmode)
18df6de9
DM		 9569 {
9570 rtx x1 = XEXP (x, 1);
ca075703
DM		 9571 unsigned HOST_WIDE_INT value1 = CONST_DOUBLE_LOW (x1);
9572 unsigned HOST_WIDE_INT value2 = CONST_DOUBLE_HIGH (x1);
18df6de9
DM		 9573
9574 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
9575 nbits++;
9576 for (; value2 != 0; value2 &= value2 - 1)
9577 nbits++;
9578 }
214c6394 9579 else
18df6de9 9580 nbits = 7;
214c6394 9581
18df6de9
DM		 9582 if (nbits < 3)
9583 nbits = 3;
9584 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
ffe384ff 9585 bit_cost = COSTS_N_INSNS (bit_cost);
214c6394 9586 }
18df6de9
DM		 9587
9588 if (mode == DImode)
ffe384ff 9589 *total = sparc_costs->int_mulX + bit_cost;
18df6de9 9590 else
ffe384ff 9591 *total = sparc_costs->int_mul + bit_cost;
214c6394 9592 }
18df6de9 9593 return false;
214c6394 9594
18df6de9
DM		 9595 case ASHIFT:
9596 case ASHIFTRT:
9597 case LSHIFTRT:
9598 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
9599 return false;
2ce04b6b 9600
18df6de9
DM		 9601 case DIV:
9602 case UDIV:
9603 case MOD:
9604 case UMOD:
9605 if (float_mode_p)
214c6394 9606 {
18df6de9
DM		 9607 if (mode == DFmode)
9608 *total = sparc_costs->float_div_df;
214c6394 9609 else
18df6de9 9610 *total = sparc_costs->float_div_sf;
214c6394 9611 }
18df6de9 9612 else
214c6394 9613 {
18df6de9
DM		 9614 if (mode == DImode)
9615 *total = sparc_costs->int_divX;
214c6394 9616 else
18df6de9 9617 *total = sparc_costs->int_div;
214c6394 9618 }
18df6de9 9619 return false;
2ce04b6b 9620
18df6de9
DM		 9621 case NEG:
9622 if (! float_mode_p)
3c50106f 9623 {
18df6de9
DM		 9624 *total = COSTS_N_INSNS (1);
9625 return false;
3c50106f 9626 }
5efb1046 9627 /* FALLTHRU */
2ce04b6b 9628
18df6de9
DM		 9629 case ABS:
9630 case FLOAT:
9631 case UNSIGNED_FLOAT:
9632 case FIX:
9633 case UNSIGNED_FIX:
9634 case FLOAT_EXTEND:
9635 case FLOAT_TRUNCATE:
9636 *total = sparc_costs->float_move;
9637 return false;
2ce04b6b 9638
18df6de9
DM		 9639 case SQRT:
9640 if (mode == DFmode)
9641 *total = sparc_costs->float_sqrt_df;
9642 else
9643 *total = sparc_costs->float_sqrt_sf;
9644 return false;
2ce04b6b 9645
18df6de9
DM		 9646 case COMPARE:
9647 if (float_mode_p)
9648 *total = sparc_costs->float_cmp;
3c50106f 9649 else
18df6de9
DM		 9650 *total = COSTS_N_INSNS (1);
9651 return false;
9652
9653 case IF_THEN_ELSE:
9654 if (float_mode_p)
9655 *total = sparc_costs->float_cmove;
9656 else
9657 *total = sparc_costs->int_cmove;
9658 return false;
2ce04b6b 9659
893e18a5
JM		 9660 case IOR:
9661 /* Handle the NAND vector patterns. */
9662 if (sparc_vector_mode_supported_p (GET_MODE (x))
9663 && GET_CODE (XEXP (x, 0)) == NOT
9664 && GET_CODE (XEXP (x, 1)) == NOT)
9665 {
9666 *total = COSTS_N_INSNS (1);
9667 return true;
9668 }
9669 else
9670 return false;
9671
2ce04b6b 9672 default:
3c50106f
RH		 9673 return false;
9674 }
2ce04b6b 9675}
fb49053f 9676
32257ddc
AS		 9677/* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
9678
9679static inline bool
9680general_or_i64_p (reg_class_t rclass)
9681{
9682 return (rclass == GENERAL_REGS || rclass == I64_REGS);
9683}
9684
9685/* Implement TARGET_REGISTER_MOVE_COST. */
9686
9687static int
9688sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
9689 reg_class_t from, reg_class_t to)
9690{
9691 if ((FP_REG_CLASS_P (from) && general_or_i64_p (to))
9692 || (general_or_i64_p (from) && FP_REG_CLASS_P (to))
9693 || from == FPCC_REGS
9694 || to == FPCC_REGS)
9695 {
9696 if (sparc_cpu == PROCESSOR_ULTRASPARC
9697 || sparc_cpu == PROCESSOR_ULTRASPARC3
9698 || sparc_cpu == PROCESSOR_NIAGARA
9699 || sparc_cpu == PROCESSOR_NIAGARA2)
9700 return 12;
9701
9702 return 6;
9703 }
9704
9705 return 2;
9706}
9707
68ba34f3
AS		 9708/* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
9709 This is achieved by means of a manual dynamic stack space allocation in
9710 the current frame. We make the assumption that SEQ doesn't contain any
a6fed83f 9711 function calls, with the possible exception of calls to the GOT helper. */
951661a1
EB		 9712
9713static void
1b970c28 9714emit_and_preserve (rtx seq, rtx reg, rtx reg2)
951661a1 9715{
68ba34f3
AS		 9716 /* We must preserve the lowest 16 words for the register save area. */
9717 HOST_WIDE_INT offset = 16*UNITS_PER_WORD;
9718 /* We really need only 2 words of fresh stack space. */
9719 HOST_WIDE_INT size = SPARC_STACK_ALIGN (offset + 2*UNITS_PER_WORD);
951661a1 9720
68ba34f3
AS		 9721 rtx slot
9722 = gen_rtx_MEM (word_mode, plus_constant (stack_pointer_rtx,
9723 SPARC_STACK_BIAS + offset));
9724
9725 emit_insn (gen_stack_pointer_dec (GEN_INT (size)));
951661a1 9726 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
1b970c28
EB		 9727 if (reg2)
9728 emit_insn (gen_rtx_SET (VOIDmode,
9729 adjust_address (slot, word_mode, UNITS_PER_WORD),
9730 reg2));
951661a1 9731 emit_insn (seq);
1b970c28
EB		 9732 if (reg2)
9733 emit_insn (gen_rtx_SET (VOIDmode,
9734 reg2,
9735 adjust_address (slot, word_mode, UNITS_PER_WORD)));
951661a1 9736 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
68ba34f3 9737 emit_insn (gen_stack_pointer_inc (GEN_INT (size)));
951661a1
EB		 9738}
9739
b9bf58e5
EB		 9740/* Output the assembler code for a thunk function. THUNK_DECL is the
9741 declaration for the thunk function itself, FUNCTION is the decl for
9742 the target function. DELTA is an immediate constant offset to be
9743 added to THIS. If VCALL_OFFSET is nonzero, the word at address
9744 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
e133041b 9745
c590b625 9746static void
fc27d102 9747sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
b9bf58e5 9748 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
fc27d102 9749 tree function)
e133041b 9750{
0a2aaacc 9751 rtx this_rtx, insn, funexp;
951661a1 9752 unsigned int int_arg_first;
e133041b
RH		 9753
9754 reload_completed = 1;
fe3ad572 9755 epilogue_completed = 1;
e133041b 9756
2e040219 9757 emit_note (NOTE_INSN_PROLOGUE_END);
e133041b 9758
b11b0904
EB		 9759 if (TARGET_FLAT)
9760 {
9761 sparc_leaf_function_p = 1;
9762
9763 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
9764 }
9765 else if (flag_delayed_branch)
951661a1
EB		 9766 {
9767 /* We will emit a regular sibcall below, so we need to instruct
9768 output_sibcall that we are in a leaf function. */
22d66adf 9769 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 1;
951661a1
EB		 9770
9771 /* This will cause final.c to invoke leaf_renumber_regs so we
9772 must behave as if we were in a not-yet-leafified function. */
9773 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
9774 }
9775 else
9776 {
9777 /* We will emit the sibcall manually below, so we will need to
9778 manually spill non-leaf registers. */
22d66adf 9779 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 0;
951661a1
EB		 9780
9781 /* We really are in a leaf function. */
9782 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
9783 }
9784
e133041b
RH		 9785 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
9786 returns a structure, the structure return pointer is there instead. */
4900aa61
EB		 9787 if (TARGET_ARCH64
9788 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
0a2aaacc 9789 this_rtx = gen_rtx_REG (Pmode, int_arg_first + 1);
e133041b 9790 else
0a2aaacc 9791 this_rtx = gen_rtx_REG (Pmode, int_arg_first);
e133041b
RH		 9792
9793 /* Add DELTA. When possible use a plain add, otherwise load it into
9794 a register first. */
b9bf58e5 9795 if (delta)
e133041b 9796 {
b9bf58e5
EB		 9797 rtx delta_rtx = GEN_INT (delta);
9798
9799 if (! SPARC_SIMM13_P (delta))
9800 {
9801 rtx scratch = gen_rtx_REG (Pmode, 1);
9802 emit_move_insn (scratch, delta_rtx);
9803 delta_rtx = scratch;
9804 }
9805
0a2aaacc
KG		 9806 /* THIS_RTX += DELTA. */
9807 emit_insn (gen_add2_insn (this_rtx, delta_rtx));
b9bf58e5
EB		 9808 }
9809
0a2aaacc 9810 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
b9bf58e5
EB		 9811 if (vcall_offset)
9812 {
9813 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
e133041b 9814 rtx scratch = gen_rtx_REG (Pmode, 1);
ed1fe829 9815
f5f7d171 9816 gcc_assert (vcall_offset < 0);
b9bf58e5 9817
0a2aaacc
KG		 9818 /* SCRATCH = *THIS_RTX. */
9819 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this_rtx));
b9bf58e5
EB		 9820
9821 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
9822 may not have any available scratch register at this point. */
9823 if (SPARC_SIMM13_P (vcall_offset))
9824 ;
9825 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
9826 else if (! fixed_regs[5]
9827 /* The below sequence is made up of at least 2 insns,
9828 while the default method may need only one. */
9829 && vcall_offset < -8192)
9830 {
9831 rtx scratch2 = gen_rtx_REG (Pmode, 5);
9832 emit_move_insn (scratch2, vcall_offset_rtx);
9833 vcall_offset_rtx = scratch2;
9834 }
e133041b 9835 else
ed1fe829 9836 {
b9bf58e5
EB		 9837 rtx increment = GEN_INT (-4096);
9838
9839 /* VCALL_OFFSET is a negative number whose typical range can be
9840 estimated as -32768..0 in 32-bit mode. In almost all cases
9841 it is therefore cheaper to emit multiple add insns than
9842 spilling and loading the constant into a register (at least
9843 6 insns). */
9844 while (! SPARC_SIMM13_P (vcall_offset))
9845 {
9846 emit_insn (gen_add2_insn (scratch, increment));
9847 vcall_offset += 4096;
9848 }
9849 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
ed1fe829
EB		 9850 }
9851
0a2aaacc 9852 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
b9bf58e5
EB		 9853 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
9854 gen_rtx_PLUS (Pmode,
9855 scratch,
9856 vcall_offset_rtx)));
e133041b 9857
0a2aaacc
KG		 9858 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
9859 emit_insn (gen_add2_insn (this_rtx, scratch));
b9bf58e5 9860 }
e133041b
RH		 9861
9862 /* Generate a tail call to the target function. */
9863 if (! TREE_USED (function))
9864 {
9865 assemble_external (function);
9866 TREE_USED (function) = 1;
9867 }
9868 funexp = XEXP (DECL_RTL (function), 0);
951661a1
EB		 9869
9870 if (flag_delayed_branch)
9871 {
9872 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
9873 insn = emit_call_insn (gen_sibcall (funexp));
9874 SIBLING_CALL_P (insn) = 1;
9875 }
9876 else
9877 {
9878 /* The hoops we have to jump through in order to generate a sibcall
9879 without using delay slots... */
a6fed83f 9880 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
951661a1
EB		 9881
9882 if (flag_pic)
9883 {
9884 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
9885 start_sequence ();
a6fed83f 9886 load_got_register (); /* clobbers %o7 */
58e6223e 9887 scratch = sparc_legitimize_pic_address (funexp, scratch);
951661a1
EB		 9888 seq = get_insns ();
9889 end_sequence ();
a6fed83f 9890 emit_and_preserve (seq, spill_reg, pic_offset_table_rtx);
951661a1
EB		 9891 }
9892 else if (TARGET_ARCH32)
9893 {
9894 emit_insn (gen_rtx_SET (VOIDmode,
9895 scratch,
9896 gen_rtx_HIGH (SImode, funexp)));
9897 emit_insn (gen_rtx_SET (VOIDmode,
9898 scratch,
9899 gen_rtx_LO_SUM (SImode, scratch, funexp)));
9900 }
9901 else /* TARGET_ARCH64 */
9902 {
9903 switch (sparc_cmodel)
9904 {
9905 case CM_MEDLOW:
9906 case CM_MEDMID:
9907 /* The destination can serve as a temporary. */
9908 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
9909 break;
9910
9911 case CM_MEDANY:
9912 case CM_EMBMEDANY:
9913 /* The destination cannot serve as a temporary. */
9914 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
9915 start_sequence ();
9916 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
9917 seq = get_insns ();
9918 end_sequence ();
1b970c28 9919 emit_and_preserve (seq, spill_reg, 0);
951661a1
EB		 9920 break;
9921
9922 default:
f5f7d171 9923 gcc_unreachable ();
951661a1
EB		 9924 }
9925 }
9926
9927 emit_jump_insn (gen_indirect_jump (scratch));
9928 }
9929
e133041b
RH		 9930 emit_barrier ();
9931
9932 /* Run just enough of rest_of_compilation to get the insns emitted.
9933 There's not really enough bulk here to make other passes such as
9934 instruction scheduling worth while. Note that use_thunk calls
9935 assemble_start_function and assemble_end_function. */
9936 insn = get_insns ();
55e092c4 9937 insn_locators_alloc ();
e133041b
RH		 9938 shorten_branches (insn);
9939 final_start_function (insn, file, 1);
c9d691e9 9940 final (insn, file, 1);
e133041b
RH		 9941 final_end_function ();
9942
9943 reload_completed = 0;
fe3ad572 9944 epilogue_completed = 0;
e133041b 9945}
e2500fed 9946
b9bf58e5
EB		 9947/* Return true if sparc_output_mi_thunk would be able to output the
9948 assembler code for the thunk function specified by the arguments
9949 it is passed, and false otherwise. */
9950static bool
3101faab 9951sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
b9bf58e5
EB		 9952 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
9953 HOST_WIDE_INT vcall_offset,
3101faab 9954 const_tree function ATTRIBUTE_UNUSED)
b9bf58e5
EB		 9955{
9956 /* Bound the loop used in the default method above. */
9957 return (vcall_offset >= -32768 || ! fixed_regs[5]);
9958}
9959
5751a10b
JJ		 9960/* How to allocate a 'struct machine_function'. */
9961
9962static struct machine_function *
9963sparc_init_machine_status (void)
9964{
a9429e29 9965 return ggc_alloc_cleared_machine_function ();
5751a10b
JJ		 9966}
9967
9968/* Locate some local-dynamic symbol still in use by this function
9969 so that we can print its name in local-dynamic base patterns. */
9970
9971static const char *
9972get_some_local_dynamic_name (void)
9973{
9974 rtx insn;
9975
9976 if (cfun->machine->some_ld_name)
9977 return cfun->machine->some_ld_name;
9978
9979 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9980 if (INSN_P (insn)
9981 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
9982 return cfun->machine->some_ld_name;
9983
f5f7d171 9984 gcc_unreachable ();
5751a10b
JJ		 9985}
9986
9987static int
9988get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9989{
9990 rtx x = *px;
9991
9992 if (x
9993 && GET_CODE (x) == SYMBOL_REF
9994 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9995 {
9996 cfun->machine->some_ld_name = XSTR (x, 0);
9997 return 1;
9998 }
9999
10000 return 0;
10001}
10002
e54c7471 10003/* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
b11b0904 10004
e54c7471 10005 This is called from dwarf2out.c to emit call frame instructions
b11b0904
EB		 10006 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
10007
e54c7471
EB		 10008static void
10009sparc_dwarf_handle_frame_unspec (const char *label,
10010 rtx pattern ATTRIBUTE_UNUSED,
10011 int index ATTRIBUTE_UNUSED)
10012{
10013 gcc_assert (index == UNSPECV_SAVEW);
10014 dwarf2out_window_save (label);
10015}
10016
fdbe66f2 10017/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5751a10b
JJ		 10018 We need to emit DTP-relative relocations. */
10019
fdbe66f2 10020static void
5751a10b
JJ		 10021sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
10022{
10023 switch (size)
10024 {
10025 case 4:
10026 fputs ("\t.word\t%r_tls_dtpoff32(", file);
10027 break;
10028 case 8:
10029 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
10030 break;
10031 default:
f5f7d171 10032 gcc_unreachable ();
5751a10b
JJ		 10033 }
10034 output_addr_const (file, x);
10035 fputs (")", file);
10036}
10037
fdbe66f2
EB		 10038/* Do whatever processing is required at the end of a file. */
10039
10040static void
10041sparc_file_end (void)
5e77eb53 10042{
a6fed83f
EB		 10043 /* If we need to emit the special GOT helper function, do so now. */
10044 if (got_helper_rtx)
9fd52c6c 10045 {
a6fed83f
EB		 10046 const char *name = XSTR (got_helper_rtx, 0);
10047 const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
9fd52c6c
DM		 10048#ifdef DWARF2_UNWIND_INFO
10049 bool do_cfi;
10050#endif
10051
9fd52c6c
DM		 10052 if (USE_HIDDEN_LINKONCE)
10053 {
10054 tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
10055 get_identifier (name),
4c203a6a
NF		 10056 build_function_type_list (void_type_node,
10057 NULL_TREE));
9fd52c6c
DM		 10058 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
10059 NULL_TREE, void_type_node);
10060 TREE_STATIC (decl) = 1;
10061 make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl));
10062 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
10063 DECL_VISIBILITY_SPECIFIED (decl) = 1;
b331ec2b 10064 resolve_unique_section (decl, 0, flag_function_sections);
9fd52c6c 10065 allocate_struct_function (decl, true);
205e4c6a 10066 cfun->is_thunk = 1;
9fd52c6c
DM		 10067 current_function_decl = decl;
10068 init_varasm_status ();
10069 assemble_start_function (decl, name);
10070 }
10071 else
10072 {
10073 const int align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
10074 switch_to_section (text_section);
10075 if (align > 0)
10076 ASM_OUTPUT_ALIGN (asm_out_file, align);
10077 ASM_OUTPUT_LABEL (asm_out_file, name);
10078 }
10079
10080#ifdef DWARF2_UNWIND_INFO
10081 do_cfi = dwarf2out_do_cfi_asm ();
10082 if (do_cfi)
10083 fprintf (asm_out_file, "\t.cfi_startproc\n");
10084#endif
10085 if (flag_delayed_branch)
10086 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
a6fed83f 10087 reg_name, reg_name);
9fd52c6c
DM		 10088 else
10089 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
a6fed83f 10090 reg_name, reg_name);
9fd52c6c
DM		 10091#ifdef DWARF2_UNWIND_INFO
10092 if (do_cfi)
10093 fprintf (asm_out_file, "\t.cfi_endproc\n");
10094#endif
10095 }
5e77eb53
EB		 10096
10097 if (NEED_INDICATE_EXEC_STACK)
10098 file_end_indicate_exec_stack ();
10099}
10100
7269aee7 10101#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
608063c3 10102/* Implement TARGET_MANGLE_TYPE. */
7269aee7
AH		 10103
10104static const char *
3101faab 10105sparc_mangle_type (const_tree type)
7269aee7
AH		 10106{
10107 if (!TARGET_64BIT
10108 && TYPE_MAIN_VARIANT (type) == long_double_type_node
10109 && TARGET_LONG_DOUBLE_128)
10110 return "g";
10111
10112 /* For all other types, use normal C++ mangling. */
10113 return NULL;
10114}
10115#endif
10116
396b535a
JJ		 10117/* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
10118 compare and swap on the word containing the byte or half-word. */
10119
10120void
10121sparc_expand_compare_and_swap_12 (rtx result, rtx mem, rtx oldval, rtx newval)
10122{
10123 rtx addr1 = force_reg (Pmode, XEXP (mem, 0));
10124 rtx addr = gen_reg_rtx (Pmode);
10125 rtx off = gen_reg_rtx (SImode);
10126 rtx oldv = gen_reg_rtx (SImode);
10127 rtx newv = gen_reg_rtx (SImode);
10128 rtx oldvalue = gen_reg_rtx (SImode);
10129 rtx newvalue = gen_reg_rtx (SImode);
10130 rtx res = gen_reg_rtx (SImode);
10131 rtx resv = gen_reg_rtx (SImode);
10132 rtx memsi, val, mask, end_label, loop_label, cc;
10133
10134 emit_insn (gen_rtx_SET (VOIDmode, addr,
10135 gen_rtx_AND (Pmode, addr1, GEN_INT (-4))));
10136
10137 if (Pmode != SImode)
10138 addr1 = gen_lowpart (SImode, addr1);
10139 emit_insn (gen_rtx_SET (VOIDmode, off,
10140 gen_rtx_AND (SImode, addr1, GEN_INT (3))));
10141
10142 memsi = gen_rtx_MEM (SImode, addr);
44d64274 10143 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
396b535a
JJ		 10144 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
10145
10146 val = force_reg (SImode, memsi);
10147
10148 emit_insn (gen_rtx_SET (VOIDmode, off,
10149 gen_rtx_XOR (SImode, off,
10150 GEN_INT (GET_MODE (mem) == QImode
10151 ? 3 : 2))));
10152
10153 emit_insn (gen_rtx_SET (VOIDmode, off,
10154 gen_rtx_ASHIFT (SImode, off, GEN_INT (3))));
10155
10156 if (GET_MODE (mem) == QImode)
10157 mask = force_reg (SImode, GEN_INT (0xff));
10158 else
10159 mask = force_reg (SImode, GEN_INT (0xffff));
10160
10161 emit_insn (gen_rtx_SET (VOIDmode, mask,
10162 gen_rtx_ASHIFT (SImode, mask, off)));
10163
10164 emit_insn (gen_rtx_SET (VOIDmode, val,
10165 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
10166 val)));
10167
10168 oldval = gen_lowpart (SImode, oldval);
10169 emit_insn (gen_rtx_SET (VOIDmode, oldv,
10170 gen_rtx_ASHIFT (SImode, oldval, off)));
10171
10172 newval = gen_lowpart_common (SImode, newval);
10173 emit_insn (gen_rtx_SET (VOIDmode, newv,
10174 gen_rtx_ASHIFT (SImode, newval, off)));
10175
10176 emit_insn (gen_rtx_SET (VOIDmode, oldv,
10177 gen_rtx_AND (SImode, oldv, mask)));
10178
10179 emit_insn (gen_rtx_SET (VOIDmode, newv,
10180 gen_rtx_AND (SImode, newv, mask)));
10181
10182 end_label = gen_label_rtx ();
10183 loop_label = gen_label_rtx ();
10184 emit_label (loop_label);
10185
10186 emit_insn (gen_rtx_SET (VOIDmode, oldvalue,
10187 gen_rtx_IOR (SImode, oldv, val)));
10188
10189 emit_insn (gen_rtx_SET (VOIDmode, newvalue,
10190 gen_rtx_IOR (SImode, newv, val)));
10191
10192 emit_insn (gen_sync_compare_and_swapsi (res, memsi, oldvalue, newvalue));
10193
10194 emit_cmp_and_jump_insns (res, oldvalue, EQ, NULL, SImode, 0, end_label);
10195
10196 emit_insn (gen_rtx_SET (VOIDmode, resv,
10197 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
10198 res)));
10199
f90b7a5a 10200 cc = gen_compare_reg_1 (NE, resv, val);
396b535a
JJ		 10201 emit_insn (gen_rtx_SET (VOIDmode, val, resv));
10202
f90b7a5a
PB		 10203 /* Use cbranchcc4 to separate the compare and branch! */
10204 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode, cc, const0_rtx),
10205 cc, const0_rtx, loop_label));
396b535a
JJ		 10206
10207 emit_label (end_label);
10208
10209 emit_insn (gen_rtx_SET (VOIDmode, res,
10210 gen_rtx_AND (SImode, res, mask)));
10211
10212 emit_insn (gen_rtx_SET (VOIDmode, res,
10213 gen_rtx_LSHIFTRT (SImode, res, off)));
10214
10215 emit_move_insn (result, gen_lowpart (GET_MODE (result), res));
10216}
10217
b52b1749
AS		 10218/* Implement TARGET_FRAME_POINTER_REQUIRED. */
10219
bc6d3f91 10220static bool
b52b1749
AS		 10221sparc_frame_pointer_required (void)
10222{
b11b0904
EB		 10223 /* If the stack pointer is dynamically modified in the function, it cannot
10224 serve as the frame pointer. */
10225 if (cfun->calls_alloca)
10226 return true;
10227
10228 /* In flat mode, that's it. */
10229 if (TARGET_FLAT)
10230 return false;
10231
10232 /* Otherwise, the frame pointer is required if the function isn't leaf. */
6d1e6c0f 10233 return !(current_function_is_leaf && only_leaf_regs_used ());
b52b1749
AS		 10234}
10235
10236/* The way this is structured, we can't eliminate SFP in favor of SP
10237 if the frame pointer is required: we want to use the SFP->HFP elimination
10238 in that case. But the test in update_eliminables doesn't know we are
10239 assuming below that we only do the former elimination. */
10240
bc6d3f91 10241static bool
b52b1749
AS		 10242sparc_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
10243{
bc6d3f91
EB		 10244 return to == HARD_FRAME_POINTER_REGNUM || !sparc_frame_pointer_required ();
10245}
10246
10247/* Return the hard frame pointer directly to bypass the stack bias. */
10248
10249static rtx
10250sparc_builtin_setjmp_frame_value (void)
10251{
10252 return hard_frame_pointer_rtx;
b52b1749
AS		 10253}
10254
5efd84c5
NF		 10255/* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
10256 they won't be allocated. */
10257
10258static void
10259sparc_conditional_register_usage (void)
10260{
10261 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
10262 {
10263 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10264 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10265 }
10266 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
10267 /* then honor it. */
10268 if (TARGET_ARCH32 && fixed_regs[5])
10269 fixed_regs[5] = 1;
10270 else if (TARGET_ARCH64 && fixed_regs[5] == 2)
10271 fixed_regs[5] = 0;
10272 if (! TARGET_V9)
10273 {
10274 int regno;
10275 for (regno = SPARC_FIRST_V9_FP_REG;
10276 regno <= SPARC_LAST_V9_FP_REG;
10277 regno++)
10278 fixed_regs[regno] = 1;
10279 /* %fcc0 is used by v8 and v9. */
10280 for (regno = SPARC_FIRST_V9_FCC_REG + 1;
10281 regno <= SPARC_LAST_V9_FCC_REG;
10282 regno++)
10283 fixed_regs[regno] = 1;
10284 }
10285 if (! TARGET_FPU)
10286 {
10287 int regno;
10288 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++)
10289 fixed_regs[regno] = 1;
10290 }
10291 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
10292 /* then honor it. Likewise with g3 and g4. */
10293 if (fixed_regs[2] == 2)
10294 fixed_regs[2] = ! TARGET_APP_REGS;
10295 if (fixed_regs[3] == 2)
10296 fixed_regs[3] = ! TARGET_APP_REGS;
10297 if (TARGET_ARCH32 && fixed_regs[4] == 2)
10298 fixed_regs[4] = ! TARGET_APP_REGS;
10299 else if (TARGET_CM_EMBMEDANY)
10300 fixed_regs[4] = 1;
10301 else if (fixed_regs[4] == 2)
10302 fixed_regs[4] = 0;
b11b0904
EB		 10303 if (TARGET_FLAT)
10304 {
10305 int regno;
10306 /* Disable leaf functions. */
10307 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER);
10308 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
10309 leaf_reg_remap [regno] = regno;
10310 }
5efd84c5
NF		 10311}
10312
112a861d
AS		 10313/* Implement TARGET_PREFERRED_RELOAD_CLASS
10314
10315 - We can't load constants into FP registers.
10316 - We can't load FP constants into integer registers when soft-float,
10317 because there is no soft-float pattern with a r/F constraint.
10318 - We can't load FP constants into integer registers for TFmode unless
10319 it is 0.0L, because there is no movtf pattern with a r/F constraint.
10320 - Try and reload integer constants (symbolic or otherwise) back into
10321 registers directly, rather than having them dumped to memory. */
10322
10323static reg_class_t
10324sparc_preferred_reload_class (rtx x, reg_class_t rclass)
10325{
10326 if (CONSTANT_P (x))
10327 {
10328 if (FP_REG_CLASS_P (rclass)
10329 || rclass == GENERAL_OR_FP_REGS
10330 || rclass == GENERAL_OR_EXTRA_FP_REGS
10331 || (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT && ! TARGET_FPU)
10332 || (GET_MODE (x) == TFmode && ! const_zero_operand (x, TFmode)))
10333 return NO_REGS;
10334
10335 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
10336 return GENERAL_REGS;
10337 }
10338
10339 return rclass;
10340}
10341
e2500fed 10342#include "gt-sparc.h"
Mirror of https://gcc.gnu.org/git/gcc.git