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1bb87f28 | 1 | /* Definitions of target machine for GNU compiler, for Sun SPARC. |
6f64bf5f | 2 | Copyright (C) 1987, 88, 89, 92, 94, 95, 1996 Free Software Foundation, Inc. |
1bb87f28 | 3 | Contributed by Michael Tiemann (tiemann@cygnus.com). |
7a6cf439 DE |
4 | 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
5 | at Cygnus Support. | |
1bb87f28 JW |
6 | |
7 | This file is part of GNU CC. | |
8 | ||
9 | GNU CC is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GNU CC is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
21 | the Free Software Foundation, 59 Temple Place - Suite 330, |
22 | Boston, MA 02111-1307, USA. */ | |
1bb87f28 JW |
23 | |
24 | /* Note that some other tm.h files include this one and then override | |
25 | many of the definitions that relate to assembler syntax. */ | |
26 | ||
7a6cf439 DE |
27 | /* Sparc64 support has been added by trying to allow for a day when one |
28 | compiler can handle both v8 and v9. There are a few cases where this | |
6f64bf5f DE |
29 | isn't doable, but keep them to a minimum! |
30 | ||
31 | TARGET_V9 is used to select at runtime the sparc64 chip. | |
32 | TARGET_ARCH64 is used to select at runtime a 64 bit environment. | |
33 | SPARC_V9 is defined as 0 or 1 (so it may be used inside and outside | |
34 | #define's), and says whether the cpu is a sparc64 chip (which may be | |
35 | running in a 32 or 64 bit environment). | |
36 | SPARC_ARCH64 is defined as 0 for a 32 bit environment and 1 for a 64 bit | |
37 | environment. | |
38 | ||
39 | In places where it is possible to choose at runtime, use TARGET_V9 and | |
40 | TARGET_ARCH64. In places where it is currently not possible to select | |
41 | between the two at runtime use SPARC_{V9,ARCH64}. Again, keep uses of | |
42 | SPARC_{V9,ARCH64} to a minimum. No attempt is made to support both v8 | |
43 | and v9 in the v9 compiler. | |
7a6cf439 DE |
44 | |
45 | If a combination v8/v9 compiler is too slow, it should always be possible | |
6f64bf5f DE |
46 | to #define TARGET_{V9,ARCH64} as 0 (and potentially other v9-only |
47 | options), and #define SPARC_{V9,ARCH64} as 0. | |
48 | I measured the difference once and it was around 10%. /dje 960120 | |
49 | */ | |
7a6cf439 | 50 | |
6f64bf5f DE |
51 | #ifndef SPARC_V9 |
52 | #define SPARC_V9 0 | |
53 | #endif | |
54 | #ifndef SPARC_ARCH64 | |
55 | #define SPARC_ARCH64 0 | |
56 | #endif | |
57 | ||
bafb031b DE |
58 | /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile. */ |
59 | #define TARGET_CPU_sparc 0 | |
60 | #define TARGET_CPU_sparclet 1 | |
61 | #define TARGET_CPU_sparclite 2 | |
62 | #define TARGET_CPU_sparc64 3 | |
63 | ||
64 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc | |
65 | #define CPP_DEFAULT_SPEC "" | |
66 | #define ASM_DEFAULT_SPEC "" | |
67 | #else | |
68 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet | |
69 | #define CPP_DEFAULT_SPEC "-D__sparclet__" | |
70 | #define ASM_DEFAULT_SPEC "-Asparclet" | |
71 | #else | |
72 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite | |
73 | #define CPP_DEFAULT_SPEC "-D__sparclite__" | |
74 | #define ASM_DEFAULT_SPEC "-Asparclite" | |
75 | #else | |
76 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc64 | |
77 | /* ??? What does Sun's CC pass? */ | |
78 | #define CPP_DEFAULT_SPEC "-D__sparc_v9__" | |
79 | /* ??? It's not clear how other assemblers will handle this, so by default | |
80 | use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case | |
81 | is handled in sol2.h. */ | |
82 | #define ASM_DEFAULT_SPEC "-Av9" | |
83 | #else | |
84 | Unrecognized value in TARGET_CPU_DEFAULT. | |
85 | #endif | |
86 | #endif | |
87 | #endif | |
88 | #endif | |
89 | ||
7a6cf439 DE |
90 | /* Names to predefine in the preprocessor for this target machine. */ |
91 | ||
92 | /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses | |
93 | the right varags.h file when bootstrapping. */ | |
bafb031b DE |
94 | /* ??? It's not clear what value we want to use for -Acpu/machine for |
95 | sparc64 in 32 bit environments, so for now we only use `sparc64' in | |
96 | 64 bit environments. */ | |
97 | /* ??? __arch64__ is subject to change. */ | |
7a6cf439 | 98 | |
6f64bf5f | 99 | #if SPARC_ARCH64 |
7a6cf439 | 100 | #define CPP_PREDEFINES \ |
bafb031b | 101 | "-Dsparc -Dsun -Dunix -D__arch64__ \ |
7a6cf439 DE |
102 | -Asystem(unix) -Asystem(bsd) -Acpu(sparc64) -Amachine(sparc64)" |
103 | #else | |
104 | #define CPP_PREDEFINES \ | |
105 | "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \ | |
857458c4 | 106 | -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)" |
7a6cf439 DE |
107 | #endif |
108 | ||
885d8175 | 109 | /* Define macros to distinguish architectures. */ |
857458c4 | 110 | |
6f64bf5f | 111 | #if SPARC_ARCH64 |
857458c4 DE |
112 | #define CPP_SPEC "\ |
113 | %{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \ | |
114 | %{mlong64:-D__LONG_MAX__=9223372036854775807LL} \ | |
115 | " | |
116 | #else | |
bafb031b DE |
117 | #define CPP_SPEC "%(cpp_cpu)" |
118 | #endif | |
119 | ||
120 | /* Common CPP definitions used by CPP_SPEC amongst the various targets | |
121 | for handling -mcpu=xxx switches. */ | |
122 | #define CPP_CPU_SPEC "\ | |
123 | %{mcypress:} \ | |
7a6cf439 DE |
124 | %{msparclite:-D__sparclite__} \ |
125 | %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ | |
126 | %{mv8:-D__sparc_v8__} \ | |
bafb031b DE |
127 | %{msupersparc:-D__supersparc__ -D__sparc_v8__} \ |
128 | %{mcpu=sparclite:-D__sparclite__} \ | |
129 | %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ | |
130 | %{mcpu=v8:-D__sparc_v8__} \ | |
131 | %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ | |
132 | %{mcpu=v9:-D__sparc_v9__} \ | |
133 | %{mcpu=ultrasparc:-D__sparc_v9__} \ | |
134 | %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_default)}}}}}}} \ | |
7a6cf439 | 135 | " |
885d8175 | 136 | |
b1fc14e5 RS |
137 | /* Prevent error on `-sun4' and `-target sun4' options. */ |
138 | /* This used to translate -dalign to -malign, but that is no good | |
139 | because it can't turn off the usual meaning of making debugging dumps. */ | |
bafb031b DE |
140 | /* Translate old style -m<cpu> into new style -mcpu=<cpu>. |
141 | At some point support for -m<cpu> will be deleted. */ | |
142 | ||
143 | #define CC1_SPEC "\ | |
144 | %{sun4:} %{target:} \ | |
145 | %{mcypress:-mcpu=cypress} \ | |
146 | %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ | |
147 | %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ | |
148 | " | |
149 | ||
150 | #define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}" | |
151 | ||
152 | /* Provide required defaults for linker -e and -d switches. */ | |
153 | ||
154 | #define LINK_SPEC \ | |
155 | "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \ | |
156 | %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}" | |
157 | ||
158 | /* Special flags to the Sun-4 assembler when using pipe for input. */ | |
159 | ||
160 | #define ASM_SPEC "\ | |
161 | %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \ | |
162 | %(asm_cpu) \ | |
163 | " | |
164 | ||
165 | /* Override in target specific files. */ | |
166 | #define ASM_CPU_SPEC "\ | |
167 | %{msparclite:-Asparclite} \ | |
168 | %{mf930:-Asparclite} %{mf934:-Asparclite} \ | |
169 | %{mcpu=sparclite:-Asparclite} \ | |
170 | %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ | |
171 | %{mcpu=v9:-Av9} \ | |
172 | %{mcpu=ultrasparc:-Av9} \ | |
173 | %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_default)}}}}}}} \ | |
174 | " | |
175 | ||
176 | /* This macro defines names of additional specifications to put in the specs | |
177 | that can be used in various specifications like CC1_SPEC. Its definition | |
178 | is an initializer with a subgrouping for each command option. | |
179 | ||
180 | Each subgrouping contains a string constant, that defines the | |
181 | specification name, and a string constant that used by the GNU CC driver | |
182 | program. | |
183 | ||
184 | Do not define this macro if it does not need to do anything. */ | |
1bb87f28 | 185 | |
bafb031b DE |
186 | #define EXTRA_SPECS \ |
187 | { "cpp_cpu", CPP_CPU_SPEC }, \ | |
188 | { "cpp_default", CPP_DEFAULT_SPEC }, \ | |
189 | { "asm_cpu", ASM_CPU_SPEC }, \ | |
190 | { "asm_default", ASM_DEFAULT_SPEC }, \ | |
191 | SUBTARGET_EXTRA_SPECS | |
1bb87f28 | 192 | |
bafb031b DE |
193 | #define SUBTARGET_EXTRA_SPECS |
194 | \f | |
6f64bf5f | 195 | #if SPARC_ARCH64 |
857458c4 DE |
196 | #define PTRDIFF_TYPE "long long int" |
197 | #define SIZE_TYPE "long long unsigned int" | |
198 | #else | |
199 | #define PTRDIFF_TYPE "int" | |
bafb031b | 200 | /* The default value for SIZE_TYPE is "unsigned int" which is what we want. */ |
857458c4 | 201 | #endif |
7a6cf439 DE |
202 | |
203 | /* ??? This should be 32 bits for v9 but what can we do? */ | |
1bb87f28 JW |
204 | #define WCHAR_TYPE "short unsigned int" |
205 | #define WCHAR_TYPE_SIZE 16 | |
7a6cf439 | 206 | #define MAX_WCHAR_TYPE_SIZE 16 |
1bb87f28 | 207 | |
4f074454 RK |
208 | /* Show we can debug even without a frame pointer. */ |
209 | #define CAN_DEBUG_WITHOUT_FP | |
1bb87f28 | 210 | |
5b485d2c JW |
211 | /* To make profiling work with -f{pic,PIC}, we need to emit the profiling |
212 | code into the rtl. Also, if we are profiling, we cannot eliminate | |
213 | the frame pointer (because the return address will get smashed). */ | |
214 | ||
7a6cf439 DE |
215 | void sparc_override_options (); |
216 | ||
5b485d2c | 217 | #define OVERRIDE_OPTIONS \ |
7a6cf439 DE |
218 | do { \ |
219 | if (profile_flag || profile_block_flag) \ | |
220 | { \ | |
221 | if (flag_pic) \ | |
222 | { \ | |
223 | char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC"; \ | |
224 | warning ("%s and profiling conflict: disabling %s", \ | |
225 | pic_string, pic_string); \ | |
226 | flag_pic = 0; \ | |
227 | } \ | |
228 | flag_omit_frame_pointer = 0; \ | |
229 | } \ | |
7a6cf439 | 230 | sparc_override_options (); \ |
bafb031b | 231 | SUBTARGET_OVERRIDE_OPTIONS; \ |
7a6cf439 | 232 | } while (0) |
84ab3bfb | 233 | |
cf9be6f0 | 234 | /* This is meant to be redefined in the host dependent files. */ |
84ab3bfb | 235 | #define SUBTARGET_OVERRIDE_OPTIONS |
5b485d2c | 236 | |
1bb87f28 JW |
237 | /* These compiler options take an argument. We ignore -target for now. */ |
238 | ||
239 | #define WORD_SWITCH_TAKES_ARG(STR) \ | |
3b39b94f ILT |
240 | (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ |
241 | || !strcmp (STR, "target") || !strcmp (STR, "assert")) | |
1bb87f28 | 242 | |
1bb87f28 JW |
243 | /* Print subsidiary information on the compiler version in use. */ |
244 | ||
245 | #define TARGET_VERSION fprintf (stderr, " (sparc)"); | |
246 | ||
247 | /* Generate DBX debugging information. */ | |
248 | ||
249 | #define DBX_DEBUGGING_INFO | |
7a6cf439 | 250 | \f |
1bb87f28 JW |
251 | /* Run-time compilation parameters selecting different hardware subsets. */ |
252 | ||
253 | extern int target_flags; | |
254 | ||
255 | /* Nonzero if we should generate code to use the fpu. */ | |
7a6cf439 DE |
256 | #define MASK_FPU 1 |
257 | #define TARGET_FPU (target_flags & MASK_FPU) | |
1bb87f28 JW |
258 | |
259 | /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we | |
260 | use fast return insns, but lose some generality. */ | |
7a6cf439 DE |
261 | #define MASK_EPILOGUE 2 |
262 | #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE) | |
1bb87f28 | 263 | |
95dea81f JW |
264 | /* Nonzero if we should assume that double pointers might be unaligned. |
265 | This can happen when linking gcc compiled code with other compilers, | |
266 | because the ABI only guarantees 4 byte alignment. */ | |
7a6cf439 DE |
267 | #define MASK_UNALIGNED_DOUBLES 4 |
268 | #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES) | |
269 | ||
885d8175 | 270 | /* Nonzero means that we should generate code for a v8 sparc. */ |
6f64bf5f | 271 | #define MASK_V8 0x8 |
7a6cf439 | 272 | #define TARGET_V8 (target_flags & MASK_V8) |
885d8175 | 273 | |
bc9e02ae JW |
274 | /* Nonzero means that we should generate code for a sparclite. |
275 | This enables the sparclite specific instructions, but does not affect | |
276 | whether FPU instructions are emitted. */ | |
6f64bf5f | 277 | #define MASK_SPARCLITE 0x10 |
7a6cf439 | 278 | #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE) |
885d8175 | 279 | |
bafb031b DE |
280 | /* Nonzero if we're compiling for the sparclet. */ |
281 | #define MASK_SPARCLET 0x20 | |
282 | #define TARGET_SPARCLET (target_flags & MASK_SPARCLET) | |
6f64bf5f DE |
283 | |
284 | /* Nonzero if we're compiling for v9 sparc. | |
285 | Note that v9's can run in 32 bit mode so this doesn't necessarily mean | |
bafb031b | 286 | the word size is 64. */ |
6f64bf5f DE |
287 | #define MASK_V9 0x40 |
288 | #define TARGET_V9 (target_flags & MASK_V9) | |
289 | ||
bafb031b DE |
290 | /* Non-zero to generate code that uses the instructions deprecated in |
291 | the v9 architecture. This option only applies to v9 systems. */ | |
292 | /* ??? This isn't user selectable yet. It's used to enable such insns | |
293 | on 32 bit v9 systems and for the moment they're permanently disabled | |
294 | on 64 bit v9 systems. */ | |
295 | #define MASK_DEPRECATED_V8_INSNS 0x80 | |
296 | #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS) | |
6f64bf5f | 297 | |
bafb031b DE |
298 | /* Mask of all CPU selection flags. */ |
299 | #define MASK_ISA \ | |
300 | (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS) | |
6f64bf5f | 301 | |
bafb031b DE |
302 | /* Non-zero means don't pass `-assert pure-text' to the linker. */ |
303 | #define MASK_IMPURE_TEXT 0x100 | |
304 | #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT) | |
5b485d2c | 305 | |
9a1c7cd7 | 306 | /* Nonzero means that we should generate code using a flat register window |
bafb031b DE |
307 | model, i.e. no save/restore instructions are generated, which is |
308 | compatible with normal sparc code. | |
309 | The frame pointer is %i7 instead of %fp. */ | |
7a6cf439 DE |
310 | #define MASK_FLAT 0x200 |
311 | #define TARGET_FLAT (target_flags & MASK_FLAT) | |
9a1c7cd7 | 312 | |
34ad7aaf | 313 | /* Nonzero means use the registers that the Sparc ABI reserves for |
bafb031b DE |
314 | application software. This must be the default to coincide with the |
315 | setting in FIXED_REGISTERS. */ | |
7a6cf439 DE |
316 | #define MASK_APP_REGS 0x400 |
317 | #define TARGET_APP_REGS (target_flags & MASK_APP_REGS) | |
34ad7aaf | 318 | |
eb582c5d DE |
319 | /* Option to select how quad word floating point is implemented. |
320 | When TARGET_HARD_QUAD is true, we use the hardware quad instructions. | |
321 | Otherwise, we use the SPARC ABI quad library functions. */ | |
7a6cf439 DE |
322 | #define MASK_HARD_QUAD 0x800 |
323 | #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD) | |
324 | ||
bafb031b | 325 | /* Bit 0x1000 currently unused. */ |
7a6cf439 DE |
326 | |
327 | /* Nonzero if ints are 64 bits. | |
328 | This automatically implies longs are 64 bits too. | |
329 | This option is for v9 only. */ | |
330 | #define MASK_INT64 0x2000 | |
331 | #define TARGET_INT64 (target_flags & MASK_INT64) | |
332 | ||
333 | /* Nonzero if longs are 64 bits. | |
334 | This option is for v9 only. */ | |
335 | #define MASK_LONG64 0x4000 | |
336 | #define TARGET_LONG64 (target_flags & MASK_LONG64) | |
337 | ||
338 | /* Nonzero if pointers are 64 bits. | |
857458c4 DE |
339 | This is not a user selectable option, though it may be one day - |
340 | so it is used to determine pointer size instead of an architecture flag. */ | |
7a6cf439 DE |
341 | #define MASK_PTR64 0x8000 |
342 | #define TARGET_PTR64 (target_flags & MASK_PTR64) | |
343 | ||
6f64bf5f DE |
344 | /* Nonzero if generating code to run in a 64 bit environment. */ |
345 | #define MASK_ARCH64 0x10000 | |
346 | #define TARGET_ARCH64 (target_flags & MASK_ARCH64) | |
6f64bf5f | 347 | #define TARGET_ARCH32 (! TARGET_ARCH64) |
7a6cf439 | 348 | |
6f64bf5f | 349 | /* SPARC64 memory models. |
eb582c5d DE |
350 | TARGET_MEDLOW: 32 bit address space, top 32 bits = 0, |
351 | avoid generating %uhi and %ulo terms. | |
352 | (pointers can be 32 or 64 bits) | |
6f64bf5f DE |
353 | TARGET_MEDANY: 64 bit address space, data segment restricted to 4G, but |
354 | can be loaded anywhere (use %g4 as offset). | |
355 | TARGET_FULLANY: 64 bit address space, no restrictions. | |
356 | This option is not fully supported yet. | |
7a6cf439 DE |
357 | These options are for v9 only. All mask values are nonzero so the v8 |
358 | compiler can assume this stuff won't interfere. */ | |
359 | #define MASK_MEDLOW 0x20000 | |
360 | #define MASK_MEDANY 0x40000 | |
361 | #define MASK_FULLANY 0x60000 | |
362 | #define MASK_CODE_MODEL (MASK_MEDLOW + MASK_MEDANY) | |
363 | #define TARGET_MEDLOW ((target_flags & MASK_CODE_MODEL) == MASK_MEDLOW) | |
364 | #define TARGET_MEDANY ((target_flags & MASK_CODE_MODEL) == MASK_MEDANY) | |
365 | #define TARGET_FULLANY ((target_flags & MASK_CODE_MODEL) == MASK_FULLANY) | |
366 | ||
367 | /* ??? There are hardcoded references to this reg in the .md file. */ | |
368 | #define MEDANY_BASE_REG "%g4" | |
369 | ||
370 | /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by | |
371 | adding 2047 to %sp. This option is for v9 only and is the default. */ | |
372 | #define MASK_STACK_BIAS 0x80000 | |
373 | #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS) | |
8248e2bc | 374 | |
1bb87f28 JW |
375 | /* Macro to define tables used to set the flags. |
376 | This is a list in braces of pairs in braces, | |
377 | each pair being { "NAME", VALUE } | |
378 | where VALUE is the bits to set or minus the bits to clear. | |
379 | An empty string NAME is used to identify the default VALUE. */ | |
380 | ||
381 | #define TARGET_SWITCHES \ | |
7a6cf439 DE |
382 | { {"fpu", MASK_FPU}, \ |
383 | {"no-fpu", -MASK_FPU}, \ | |
384 | {"hard-float", MASK_FPU}, \ | |
385 | {"soft-float", -MASK_FPU}, \ | |
386 | {"epilogue", MASK_EPILOGUE}, \ | |
387 | {"no-epilogue", -MASK_EPILOGUE}, \ | |
388 | {"unaligned-doubles", MASK_UNALIGNED_DOUBLES}, \ | |
389 | {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES}, \ | |
bafb031b DE |
390 | {"impure-text", MASK_IMPURE_TEXT}, \ |
391 | {"no-impure-text", -MASK_IMPURE_TEXT}, \ | |
392 | {"flat", MASK_FLAT}, \ | |
393 | {"no-flat", -MASK_FLAT}, \ | |
7a6cf439 DE |
394 | {"app-regs", MASK_APP_REGS}, \ |
395 | {"no-app-regs", -MASK_APP_REGS}, \ | |
396 | {"hard-quad-float", MASK_HARD_QUAD}, \ | |
397 | {"soft-quad-float", -MASK_HARD_QUAD}, \ | |
bafb031b DE |
398 | /* ??? These are coerced to -mcpu=. Delete in 2.9. */ \ |
399 | {"cypress", 0}, \ | |
400 | {"sparclite", 0}, \ | |
401 | {"f930", 0}, \ | |
402 | {"f934", 0}, \ | |
403 | {"v8", 0}, \ | |
404 | {"supersparc", 0}, \ | |
7a6cf439 | 405 | SUBTARGET_SWITCHES \ |
eb582c5d | 406 | ARCH64_SWITCHES \ |
b1fc14e5 | 407 | { "", TARGET_DEFAULT}} |
1bb87f28 | 408 | |
bafb031b DE |
409 | /* MASK_APP_REGS must always be the default because that's what |
410 | FIXED_REGISTERS is set to and -ffixed- is processed before | |
411 | CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */ | |
7a6cf439 | 412 | #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) |
84ab3bfb | 413 | |
bafb031b | 414 | /* This is meant to be redefined in target specific files. */ |
84ab3bfb | 415 | #define SUBTARGET_SWITCHES |
1bb87f28 | 416 | |
eb582c5d DE |
417 | /* ??? Until we support a combination 32/64 bit compiler, these options |
418 | are only defined for the v9 compiler in a true 64 bit environment. */ | |
6f64bf5f | 419 | #if SPARC_ARCH64 |
eb582c5d | 420 | #define ARCH64_SWITCHES \ |
6f64bf5f DE |
421 | /* {"arch32", -MASK_ARCH64}, */ \ |
422 | /* {"arch64", MASK_ARCH64}, */ \ | |
7a6cf439 DE |
423 | {"int64", MASK_INT64+MASK_LONG64}, \ |
424 | {"int32", -MASK_INT64}, \ | |
fa653e40 DE |
425 | {"int32", MASK_LONG64}, \ |
426 | {"long64", -MASK_INT64}, \ | |
7a6cf439 | 427 | {"long64", MASK_LONG64}, \ |
fa653e40 DE |
428 | {"long32", -(MASK_INT64+MASK_LONG64)}, \ |
429 | /* {"ptr64", MASK_PTR64}, */ \ | |
430 | /* {"ptr32", -MASK_PTR64}, */ \ | |
7a6cf439 | 431 | {"stack-bias", MASK_STACK_BIAS}, \ |
2454c8d4 JW |
432 | {"no-stack-bias", -MASK_STACK_BIAS}, \ |
433 | {"medlow", -MASK_CODE_MODEL}, \ | |
434 | {"medlow", MASK_MEDLOW}, \ | |
435 | {"medany", -MASK_CODE_MODEL}, \ | |
6f64bf5f DE |
436 | {"medany", MASK_MEDANY}, \ |
437 | {"fullany", -MASK_CODE_MODEL}, \ | |
438 | {"fullany", MASK_FULLANY}, | |
7a6cf439 | 439 | #else |
eb582c5d | 440 | #define ARCH64_SWITCHES |
360b1451 | 441 | #endif |
bafb031b DE |
442 | |
443 | extern enum attr_cpu sparc_cpu; | |
444 | ||
445 | /* This macro is similar to `TARGET_SWITCHES' but defines names of | |
446 | command options that have values. Its definition is an | |
447 | initializer with a subgrouping for each command option. | |
448 | ||
449 | Each subgrouping contains a string constant, that defines the | |
450 | fixed part of the option name, and the address of a variable. | |
451 | The variable, type `char *', is set to the variable part of the | |
452 | given option if the fixed part matches. The actual option name | |
453 | is made by appending `-m' to the specified name. | |
454 | ||
455 | Here is an example which defines `-mshort-data-NUMBER'. If the | |
456 | given option is `-mshort-data-512', the variable `m88k_short_data' | |
457 | will be set to the string `"512"'. | |
458 | ||
459 | extern char *m88k_short_data; | |
460 | #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */ | |
461 | ||
462 | /* ??? This isn't as fancy as rs6000.h. Maybe in time. */ | |
463 | extern char *sparc_cpu_string; | |
464 | ||
465 | #define TARGET_OPTIONS \ | |
466 | { \ | |
467 | { "cpu=", &sparc_cpu_string }, \ | |
468 | SUBTARGET_OPTIONS \ | |
469 | } | |
470 | ||
471 | /* This is meant to be redefined in target specific files. */ | |
472 | #define SUBTARGET_OPTIONS | |
7a6cf439 DE |
473 | \f |
474 | /* target machine storage layout */ | |
475 | ||
d667538b JW |
476 | /* Define for cross-compilation to a sparc target with no TFmode from a host |
477 | with a different float format (e.g. VAX). */ | |
478 | #define REAL_ARITHMETIC | |
479 | ||
1bb87f28 JW |
480 | /* Define this if most significant bit is lowest numbered |
481 | in instructions that operate on numbered bit-fields. */ | |
482 | #define BITS_BIG_ENDIAN 1 | |
483 | ||
484 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
485 | /* This is true on the SPARC. */ | |
486 | #define BYTES_BIG_ENDIAN 1 | |
487 | ||
488 | /* Define this if most significant word of a multiword number is the lowest | |
489 | numbered. */ | |
490 | /* Doubles are stored in memory with the high order word first. This | |
491 | matters when cross-compiling. */ | |
492 | #define WORDS_BIG_ENDIAN 1 | |
493 | ||
b4ac57ab | 494 | /* number of bits in an addressable storage unit */ |
1bb87f28 JW |
495 | #define BITS_PER_UNIT 8 |
496 | ||
497 | /* Width in bits of a "word", which is the contents of a machine register. | |
498 | Note that this is not necessarily the width of data type `int'; | |
499 | if using 16-bit ints on a 68000, this would still be 32. | |
500 | But on a machine with 16-bit registers, this would be 16. */ | |
6f64bf5f | 501 | #define BITS_PER_WORD (TARGET_ARCH64 ? 64 : 32) |
7a6cf439 | 502 | #define MAX_BITS_PER_WORD 64 |
1bb87f28 JW |
503 | |
504 | /* Width of a word, in units (bytes). */ | |
6f64bf5f | 505 | #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) |
ef0e53ce | 506 | #define MIN_UNITS_PER_WORD 4 |
7a6cf439 DE |
507 | |
508 | /* Now define the sizes of the C data types. */ | |
509 | ||
510 | #define SHORT_TYPE_SIZE 16 | |
511 | #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32) | |
512 | #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) | |
513 | #define LONG_LONG_TYPE_SIZE 64 | |
514 | #define FLOAT_TYPE_SIZE 32 | |
515 | #define DOUBLE_TYPE_SIZE 64 | |
516 | ||
517 | #define MAX_INT_TYPE_SIZE 64 | |
518 | #define MAX_LONG_TYPE_SIZE 64 | |
519 | ||
6f64bf5f | 520 | #if SPARC_ARCH64 |
7a6cf439 DE |
521 | /* ??? This does not work in SunOS 4.x, so it is not enabled here. |
522 | Instead, it is enabled in sol2.h, because it does work under Solaris. */ | |
523 | /* Define for support of TFmode long double and REAL_ARITHMETIC. | |
524 | Sparc ABI says that long double is 4 words. */ | |
525 | #define LONG_DOUBLE_TYPE_SIZE 128 | |
526 | #endif | |
1bb87f28 JW |
527 | |
528 | /* Width in bits of a pointer. | |
529 | See also the macro `Pmode' defined below. */ | |
7a6cf439 | 530 | #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) |
1bb87f28 JW |
531 | |
532 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
6f64bf5f | 533 | #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) |
1bb87f28 JW |
534 | |
535 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
6f64bf5f | 536 | #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) |
1bb87f28 | 537 | |
10d1b70f JW |
538 | /* ALIGN FRAMES on double word boundaries */ |
539 | ||
7a6cf439 | 540 | #define SPARC_STACK_ALIGN(LOC) \ |
6f64bf5f | 541 | (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) |
10d1b70f | 542 | |
1bb87f28 JW |
543 | /* Allocation boundary (in *bits*) for the code of a function. */ |
544 | #define FUNCTION_BOUNDARY 32 | |
545 | ||
546 | /* Alignment of field after `int : 0' in a structure. */ | |
7a6cf439 | 547 | /* ??? Should this be based on TARGET_INT64? */ |
6f64bf5f | 548 | #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) |
1bb87f28 JW |
549 | |
550 | /* Every structure's size must be a multiple of this. */ | |
551 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
552 | ||
553 | /* A bitfield declared as `int' forces `int' alignment for the struct. */ | |
554 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
555 | ||
556 | /* No data type wants to be aligned rounder than this. */ | |
6f64bf5f | 557 | #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) |
1bb87f28 | 558 | |
77a02b01 JW |
559 | /* The best alignment to use in cases where we have a choice. */ |
560 | #define FASTEST_ALIGNMENT 64 | |
561 | ||
1bb87f28 JW |
562 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
563 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
d2a8e680 RS |
564 | ((TREE_CODE (EXP) == STRING_CST \ |
565 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
566 | ? FASTEST_ALIGNMENT : (ALIGN)) | |
1bb87f28 JW |
567 | |
568 | /* Make arrays of chars word-aligned for the same reasons. */ | |
569 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
570 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
571 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
77a02b01 | 572 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) |
1bb87f28 | 573 | |
b4ac57ab | 574 | /* Set this nonzero if move instructions will actually fail to work |
1bb87f28 | 575 | when given unaligned data. */ |
b4ac57ab | 576 | #define STRICT_ALIGNMENT 1 |
1bb87f28 JW |
577 | |
578 | /* Things that must be doubleword aligned cannot go in the text section, | |
579 | because the linker fails to align the text section enough! | |
7a6cf439 | 580 | Put them in the data section. This macro is only used in this file. */ |
1bb87f28 JW |
581 | #define MAX_TEXT_ALIGN 32 |
582 | ||
68d69835 JM |
583 | /* This forces all variables and constants to the data section when PIC. |
584 | This is because the SunOS 4 shared library scheme thinks everything in | |
585 | text is a function, and patches the address to point to a loader stub. */ | |
586 | /* This is defined to zero for every system which doesn't use the a.out object | |
587 | file format. */ | |
588 | #ifndef SUNOS4_SHARED_LIBRARIES | |
589 | #define SUNOS4_SHARED_LIBRARIES 0 | |
590 | #endif | |
591 | ||
7a6cf439 | 592 | /* This is defined differently for v9 in a cover file. */ |
1bb87f28 JW |
593 | #define SELECT_SECTION(T,RELOC) \ |
594 | { \ | |
595 | if (TREE_CODE (T) == VAR_DECL) \ | |
596 | { \ | |
597 | if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \ | |
ed8969fa JW |
598 | && DECL_INITIAL (T) \ |
599 | && (DECL_INITIAL (T) == error_mark_node \ | |
600 | || TREE_CONSTANT (DECL_INITIAL (T))) \ | |
1bb87f28 | 601 | && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \ |
68d69835 | 602 | && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \ |
1bb87f28 JW |
603 | text_section (); \ |
604 | else \ | |
605 | data_section (); \ | |
606 | } \ | |
607 | else if (TREE_CODE (T) == CONSTRUCTOR) \ | |
608 | { \ | |
68d69835 | 609 | if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \ |
1bb87f28 JW |
610 | data_section (); \ |
611 | } \ | |
07516036 | 612 | else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c') \ |
1bb87f28 JW |
613 | { \ |
614 | if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \ | |
68d69835 JM |
615 | || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \ |
616 | || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \ | |
1bb87f28 JW |
617 | data_section (); \ |
618 | else \ | |
619 | text_section (); \ | |
620 | } \ | |
621 | } | |
622 | ||
623 | /* Use text section for a constant | |
624 | unless we need more alignment than that offers. */ | |
7a6cf439 | 625 | /* This is defined differently for v9 in a cover file. */ |
1bb87f28 JW |
626 | #define SELECT_RTX_SECTION(MODE, X) \ |
627 | { \ | |
628 | if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \ | |
68d69835 | 629 | && ! (flag_pic && (symbolic_operand (X) || SUNOS4_SHARED_LIBRARIES))) \ |
1bb87f28 JW |
630 | text_section (); \ |
631 | else \ | |
632 | data_section (); \ | |
633 | } | |
634 | \f | |
635 | /* Standard register usage. */ | |
636 | ||
637 | /* Number of actual hardware registers. | |
638 | The hardware registers are assigned numbers for the compiler | |
639 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
640 | All registers that the compiler knows about must be given numbers, | |
641 | even those that are not normally considered general registers. | |
642 | ||
7a6cf439 DE |
643 | SPARC has 32 integer registers and 32 floating point registers. |
644 | 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not | |
645 | accessible. We still account for them to simplify register computations | |
646 | (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so | |
647 | 32+32+32+4 == 100. | |
648 | Register 0 is used as the integer condition code register. */ | |
1bb87f28 | 649 | |
6f64bf5f | 650 | #if SPARC_V9 |
7a6cf439 DE |
651 | #define FIRST_PSEUDO_REGISTER 100 |
652 | #else | |
1bb87f28 | 653 | #define FIRST_PSEUDO_REGISTER 64 |
7a6cf439 | 654 | #endif |
1bb87f28 JW |
655 | |
656 | /* 1 for registers that have pervasive standard uses | |
657 | and are not available for the register allocator. | |
5b485d2c | 658 | g0 is used for the condition code and not to represent %g0, which is |
1bb87f28 | 659 | hardwired to 0, so reg 0 is *not* fixed. |
7a6cf439 | 660 | On non-v9 systems: |
34ad7aaf JW |
661 | g1 is free to use as temporary. |
662 | g2-g4 are reserved for applications. Gcc normally uses them as | |
663 | temporaries, but this can be disabled via the -mno-app-regs option. | |
7a6cf439 DE |
664 | g5 through g7 are reserved for the operating system. |
665 | On v9 systems: | |
666 | g1 and g5 are free to use as temporaries. | |
bafb031b DE |
667 | g2-g4 are reserved for applications. Gcc normally uses them as |
668 | temporaries, but this can be disabled via the -mno-app-regs option. | |
7a6cf439 DE |
669 | g6-g7 are reserved for the operating system. |
670 | ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must | |
671 | currently be a fixed register until this pattern is rewritten. | |
672 | Register 1 is also used when restoring call-preserved registers in large | |
673 | stack frames. */ | |
674 | ||
6f64bf5f | 675 | #if SPARC_V9 |
7a6cf439 | 676 | #define FIXED_REGISTERS \ |
bafb031b | 677 | {0, 1, 0, 0, 0, 0, 1, 1, \ |
7a6cf439 DE |
678 | 0, 0, 0, 0, 0, 0, 1, 0, \ |
679 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
680 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
681 | \ | |
682 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
683 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
684 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
685 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
686 | \ | |
687 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
688 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
689 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
690 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
691 | \ | |
692 | 0, 0, 0, 0} | |
693 | #else | |
1bb87f28 | 694 | #define FIXED_REGISTERS \ |
d9ca49d5 | 695 | {0, 0, 0, 0, 0, 1, 1, 1, \ |
1bb87f28 JW |
696 | 0, 0, 0, 0, 0, 0, 1, 0, \ |
697 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
698 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
699 | \ | |
700 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
701 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
702 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
703 | 0, 0, 0, 0, 0, 0, 0, 0} | |
7a6cf439 | 704 | #endif |
1bb87f28 JW |
705 | |
706 | /* 1 for registers not available across function calls. | |
707 | These must include the FIXED_REGISTERS and also any | |
708 | registers that can be used without being saved. | |
709 | The latter must include the registers where values are returned | |
710 | and the register where structure-value addresses are passed. | |
711 | Aside from that, you can include as many other registers as you like. */ | |
7a6cf439 | 712 | |
bafb031b | 713 | #if SPARC_V9 && SPARC_ARCH64 |
7a6cf439 DE |
714 | #define CALL_USED_REGISTERS \ |
715 | {1, 1, 1, 1, 1, 1, 1, 1, \ | |
716 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
717 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
718 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
719 | \ | |
720 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
721 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
722 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
723 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
724 | \ | |
725 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
726 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
727 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
728 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
729 | \ | |
730 | 1, 1, 1, 1} | |
731 | #else | |
bafb031b DE |
732 | #if SPARC_V9 && ! SPARC_ARCH64 |
733 | #define CALL_USED_REGISTERS \ | |
734 | {1, 1, 1, 1, 1, 1, 1, 1, \ | |
735 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
736 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
737 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
738 | \ | |
739 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
740 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
741 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
742 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
743 | \ | |
744 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
745 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
746 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
747 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
748 | \ | |
749 | 1, 1, 1, 1} | |
750 | #else | |
1bb87f28 JW |
751 | #define CALL_USED_REGISTERS \ |
752 | {1, 1, 1, 1, 1, 1, 1, 1, \ | |
753 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
754 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
755 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
756 | \ | |
757 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
758 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
759 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
760 | 1, 1, 1, 1, 1, 1, 1, 1} | |
7a6cf439 | 761 | #endif |
bafb031b | 762 | #endif |
1bb87f28 | 763 | |
26c5587d | 764 | /* If !TARGET_FPU, then make the fp registers fixed so that they won't |
7a6cf439 | 765 | be allocated. On v9, also make the fp cc regs fixed. */ |
26c5587d JW |
766 | |
767 | #define CONDITIONAL_REGISTER_USAGE \ | |
768 | do \ | |
769 | { \ | |
6f64bf5f DE |
770 | if (SPARC_V9 && ! SPARC_ARCH64) \ |
771 | { \ | |
6f64bf5f | 772 | fixed_regs[5] = 1; \ |
6f64bf5f | 773 | } \ |
26c5587d JW |
774 | if (! TARGET_FPU) \ |
775 | { \ | |
776 | int regno; \ | |
7a6cf439 | 777 | for (regno = 32; regno < FIRST_PSEUDO_REGISTER; regno++) \ |
26c5587d JW |
778 | fixed_regs[regno] = 1; \ |
779 | } \ | |
bafb031b DE |
780 | /* Don't unfix g2-g4 if they were fixed with -ffixed-. */ \ |
781 | fixed_regs[2] |= ! TARGET_APP_REGS; \ | |
782 | fixed_regs[3] |= ! TARGET_APP_REGS; \ | |
783 | fixed_regs[4] |= ! TARGET_APP_REGS || TARGET_MEDANY; \ | |
5c56efde DE |
784 | if (TARGET_FLAT) \ |
785 | { \ | |
786 | /* Let the compiler believe the frame pointer is still \ | |
787 | %fp, but output it as %i7. */ \ | |
788 | fixed_regs[31] = 1; \ | |
789 | reg_names[FRAME_POINTER_REGNUM] = "%i7"; \ | |
790 | /* ??? This is a hack to disable leaf functions. */ \ | |
791 | global_regs[7] = 1; \ | |
792 | } \ | |
9ee6230c JW |
793 | if (profile_block_flag) \ |
794 | { \ | |
795 | /* %g1 and %g2 must be fixed, because BLOCK_PROFILER \ | |
796 | uses them. */ \ | |
797 | fixed_regs[1] = 1; \ | |
798 | fixed_regs[2] = 1; \ | |
799 | } \ | |
26c5587d JW |
800 | } \ |
801 | while (0) | |
802 | ||
1bb87f28 JW |
803 | /* Return number of consecutive hard regs needed starting at reg REGNO |
804 | to hold something of mode MODE. | |
805 | This is ordinarily the length in words of a value of mode MODE | |
806 | but can be less for certain modes in special long registers. | |
807 | ||
808 | On SPARC, ordinary registers hold 32 bits worth; | |
809 | this means both integer and floating point registers. | |
7a6cf439 DE |
810 | On v9, integer regs hold 64 bits worth; floating point regs hold |
811 | 32 bits worth (this includes the new fp regs as even the odd ones are | |
812 | included in the hard register count). */ | |
1bb87f28 | 813 | |
7a6cf439 | 814 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
6f64bf5f | 815 | (TARGET_ARCH64 \ |
7a6cf439 DE |
816 | ? ((REGNO) < 32 \ |
817 | ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ | |
818 | : (GET_MODE_SIZE (MODE) + 3) / 4) \ | |
819 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
1bb87f28 JW |
820 | |
821 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
923a8d06 | 822 | See sparc.c for how we initialize this. */ |
7a6cf439 DE |
823 | extern int *hard_regno_mode_classes; |
824 | extern int sparc_mode_class[]; | |
1bb87f28 | 825 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
7a6cf439 | 826 | ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) |
1bb87f28 JW |
827 | |
828 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
829 | when one has mode MODE1 and one has mode MODE2. | |
830 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
7a6cf439 DE |
831 | for any hard reg, then this must be 0 for correct output. |
832 | ||
833 | For V9: SFmode can't be combined with other float modes, because they can't | |
834 | be allocated to the %d registers. Also, DFmode won't fit in odd %f | |
835 | registers, but SFmode will. */ | |
1bb87f28 | 836 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
7a6cf439 DE |
837 | ((MODE1) == (MODE2) \ |
838 | || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ | |
839 | && (! TARGET_V9 \ | |
840 | || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ | |
841 | || (MODE1 != SFmode && MODE2 != SFmode))))) | |
1bb87f28 JW |
842 | |
843 | /* Specify the registers used for certain standard purposes. | |
844 | The values of these macros are register numbers. */ | |
845 | ||
846 | /* SPARC pc isn't overloaded on a register that the compiler knows about. */ | |
847 | /* #define PC_REGNUM */ | |
848 | ||
849 | /* Register to use for pushing function arguments. */ | |
850 | #define STACK_POINTER_REGNUM 14 | |
851 | ||
7a6cf439 DE |
852 | /* Actual top-of-stack address is 92/136 greater than the contents of the |
853 | stack pointer register for !v9/v9. That is: | |
854 | - !v9: 64 bytes for the in and local registers, 4 bytes for structure return | |
855 | address, and 24 bytes for the 6 register parameters. | |
856 | - v9: 128 bytes for the in and local registers + 8 bytes reserved. */ | |
1bb87f28 JW |
857 | #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0) |
858 | ||
7a6cf439 DE |
859 | /* The stack bias (amount by which the hardware register is offset by). */ |
860 | #define SPARC_STACK_BIAS (TARGET_STACK_BIAS ? 2047 : 0) | |
861 | ||
1bb87f28 JW |
862 | /* Base register for access to local variables of the function. */ |
863 | #define FRAME_POINTER_REGNUM 30 | |
864 | ||
865 | #if 0 | |
866 | /* Register that is used for the return address. */ | |
867 | #define RETURN_ADDR_REGNUM 15 | |
868 | #endif | |
869 | ||
870 | /* Value should be nonzero if functions must have frame pointers. | |
871 | Zero means the frame pointer need not be set up (and parms | |
872 | may be accessed via the stack pointer) in functions that seem suitable. | |
873 | This is computed in `reload', in reload1.c. | |
a061b9fa | 874 | Used in flow.c, global.c, and reload1.c. |
1bb87f28 | 875 | |
a061b9fa DE |
876 | Being a non-leaf function does not mean a frame pointer is needed in the |
877 | flat window model. However, the debugger won't be able to backtrace through | |
878 | us with out it. */ | |
1bb87f28 | 879 | #define FRAME_POINTER_REQUIRED \ |
bafb031b DE |
880 | (TARGET_FLAT ? (current_function_calls_alloca || current_function_varargs \ |
881 | || !leaf_function_p ()) \ | |
5c56efde | 882 | : ! (leaf_function_p () && only_leaf_regs_used ())) |
1bb87f28 JW |
883 | |
884 | /* C statement to store the difference between the frame pointer | |
885 | and the stack pointer values immediately after the function prologue. | |
886 | ||
887 | Note, we always pretend that this is a leaf function because if | |
888 | it's not, there's no point in trying to eliminate the | |
889 | frame pointer. If it is a leaf function, we guessed right! */ | |
890 | #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ | |
bafb031b | 891 | ((VAR) = (TARGET_FLAT ? sparc_flat_compute_frame_size (get_frame_size ()) \ |
5b485d2c | 892 | : compute_frame_size (get_frame_size (), 1))) |
1bb87f28 JW |
893 | |
894 | /* Base register for access to arguments of the function. */ | |
5c56efde | 895 | #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM |
1bb87f28 | 896 | |
6098b63e | 897 | /* Register in which static-chain is passed to a function. This must |
c8392688 | 898 | not be a register used by the prologue. */ |
6f64bf5f | 899 | #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) |
1bb87f28 JW |
900 | |
901 | /* Register which holds offset table for position-independent | |
902 | data references. */ | |
903 | ||
904 | #define PIC_OFFSET_TABLE_REGNUM 23 | |
905 | ||
906 | #define INITIALIZE_PIC initialize_pic () | |
907 | #define FINALIZE_PIC finalize_pic () | |
908 | ||
d9ca49d5 | 909 | /* Sparc ABI says that quad-precision floats and all structures are returned |
7a6cf439 DE |
910 | in memory. |
911 | For v9, all aggregates are returned in memory. */ | |
686667bf JW |
912 | #define RETURN_IN_MEMORY(TYPE) \ |
913 | (TYPE_MODE (TYPE) == BLKmode \ | |
6f64bf5f DE |
914 | || (! TARGET_ARCH64 && (TYPE_MODE (TYPE) == TFmode \ |
915 | || TYPE_MODE (TYPE) == TCmode))) | |
d9ca49d5 | 916 | |
1bb87f28 JW |
917 | /* Functions which return large structures get the address |
918 | to place the wanted value at offset 64 from the frame. | |
7a6cf439 DE |
919 | Must reserve 64 bytes for the in and local registers. |
920 | v9: Functions which return large structures get the address to place the | |
921 | wanted value from an invisible first argument. */ | |
1bb87f28 JW |
922 | /* Used only in other #defines in this file. */ |
923 | #define STRUCT_VALUE_OFFSET 64 | |
924 | ||
925 | #define STRUCT_VALUE \ | |
6f64bf5f | 926 | (TARGET_ARCH64 \ |
7a6cf439 DE |
927 | ? 0 \ |
928 | : gen_rtx (MEM, Pmode, \ | |
929 | gen_rtx (PLUS, Pmode, stack_pointer_rtx, \ | |
930 | gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))) | |
1bb87f28 | 931 | #define STRUCT_VALUE_INCOMING \ |
6f64bf5f | 932 | (TARGET_ARCH64 \ |
7a6cf439 DE |
933 | ? 0 \ |
934 | : gen_rtx (MEM, Pmode, \ | |
935 | gen_rtx (PLUS, Pmode, frame_pointer_rtx, \ | |
936 | gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))) | |
1bb87f28 JW |
937 | \f |
938 | /* Define the classes of registers for register constraints in the | |
939 | machine description. Also define ranges of constants. | |
940 | ||
941 | One of the classes must always be named ALL_REGS and include all hard regs. | |
942 | If there is more than one class, another class must be named NO_REGS | |
943 | and contain no registers. | |
944 | ||
945 | The name GENERAL_REGS must be the name of a class (or an alias for | |
946 | another name such as ALL_REGS). This is the class of registers | |
947 | that is allowed by "g" or "r" in a register constraint. | |
948 | Also, registers outside this class are allocated only when | |
949 | instructions express preferences for them. | |
950 | ||
951 | The classes must be numbered in nondecreasing order; that is, | |
952 | a larger-numbered class must never be contained completely | |
953 | in a smaller-numbered class. | |
954 | ||
955 | For any two classes, it is very desirable that there be another | |
956 | class that represents their union. */ | |
957 | ||
7a6cf439 | 958 | /* The SPARC has two kinds of registers, general and floating point. |
24b63396 JW |
959 | |
960 | For v9 we must distinguish between the upper and lower floating point | |
961 | registers because the upper ones can't hold SFmode values. | |
962 | HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) | |
963 | satisfying a group need for a class will also satisfy a single need for | |
964 | that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp | |
965 | regs. | |
966 | ||
967 | It is important that one class contains all the general and all the standard | |
968 | fp regs. Otherwise find_reg() won't properly allocate int regs for moves, | |
969 | because reg_class_record() will bias the selection in favor of fp regs, | |
970 | because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, | |
971 | because FP_REGS > GENERAL_REGS. | |
972 | ||
973 | It is also important that one class contain all the general and all the | |
974 | fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS | |
975 | but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause | |
976 | allocate_reload_reg() to bypass it causing an abort because the compiler | |
977 | thinks it doesn't have a spill reg when in fact it does. | |
978 | ||
7a6cf439 DE |
979 | v9 also has 4 floating point condition code registers. Since we don't |
980 | have a class that is the union of FPCC_REGS with either of the others, | |
981 | it is important that it appear first. Otherwise the compiler will die | |
982 | trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its | |
983 | constraints. */ | |
7a6cf439 | 984 | |
6f64bf5f | 985 | #if SPARC_V9 |
24b63396 JW |
986 | enum reg_class { NO_REGS, FPCC_REGS, GENERAL_REGS, FP_REGS, EXTRA_FP_REGS, |
987 | GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, | |
7a6cf439 DE |
988 | ALL_REGS, LIM_REG_CLASSES }; |
989 | #else | |
1bb87f28 | 990 | enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES }; |
7a6cf439 | 991 | #endif |
1bb87f28 JW |
992 | |
993 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
994 | ||
995 | /* Give names of register classes as strings for dump file. */ | |
996 | ||
6f64bf5f | 997 | #if SPARC_V9 |
1bb87f28 | 998 | #define REG_CLASS_NAMES \ |
24b63396 JW |
999 | { "NO_REGS", "FPCC_REGS", "GENERAL_REGS", "FP_REGS", "EXTRA_FP_REGS", \ |
1000 | "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", "ALL_REGS" } | |
7a6cf439 DE |
1001 | #else |
1002 | #define REG_CLASS_NAMES \ | |
24b63396 | 1003 | { "NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" } |
7a6cf439 | 1004 | #endif |
1bb87f28 JW |
1005 | |
1006 | /* Define which registers fit in which classes. | |
1007 | This is an initializer for a vector of HARD_REG_SET | |
1008 | of length N_REG_CLASSES. */ | |
1009 | ||
6f64bf5f | 1010 | #if SPARC_V9 |
7a6cf439 | 1011 | #define REG_CLASS_CONTENTS \ |
24b63396 JW |
1012 | {{0, 0, 0, 0}, {0, 0, 0, 0xf}, {-2, 0, 0, 0}, \ |
1013 | {0, -1, 0, 0}, {0, -1, -1, 0}, {-2, -1, 0, 0}, {-2, -1, -1, 0}, \ | |
1014 | {-2, -1, -1, 0xf}} | |
7a6cf439 | 1015 | #else |
1bb87f28 JW |
1016 | #if 0 && defined (__GNUC__) |
1017 | #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL} | |
1018 | #else | |
1019 | #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}} | |
1020 | #endif | |
7a6cf439 | 1021 | #endif |
1bb87f28 JW |
1022 | |
1023 | /* The same information, inverted: | |
1024 | Return the class number of the smallest class containing | |
1025 | reg number REGNO. This could be a conditional expression | |
1026 | or could index an array. */ | |
1027 | ||
6f64bf5f | 1028 | #if SPARC_V9 |
24b63396 JW |
1029 | #define REGNO_REG_CLASS(REGNO) \ |
1030 | ((REGNO) == 0 ? NO_REGS \ | |
1031 | : (REGNO) < 32 ? GENERAL_REGS \ | |
1032 | : (REGNO) < 64 ? FP_REGS \ | |
1033 | : (REGNO) < 96 ? EXTRA_FP_REGS \ | |
1034 | : FPCC_REGS) | |
7a6cf439 | 1035 | #else |
1bb87f28 JW |
1036 | #define REGNO_REG_CLASS(REGNO) \ |
1037 | ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS) | |
7a6cf439 | 1038 | #endif |
1bb87f28 | 1039 | |
7a6cf439 | 1040 | /* This is the order in which to allocate registers normally. |
51f0e748 JW |
1041 | |
1042 | We put %f0/%f1 last among the float registers, so as to make it more | |
6a4bb1fa | 1043 | likely that a pseudo-register which dies in the float return register |
51f0e748 | 1044 | will get allocated to the float return register, thus saving a move |
7a6cf439 DE |
1045 | instruction at the end of the function. |
1046 | ||
1047 | On v9, the float registers are ordered a little "funny" because some | |
1048 | of them (%f16-%f47) are call-preserved. */ | |
6f64bf5f | 1049 | #if SPARC_V9 |
7a6cf439 DE |
1050 | #define REG_ALLOC_ORDER \ |
1051 | { 8, 9, 10, 11, 12, 13, \ | |
1052 | 15, 16, 17, 18, 19, 20, 21, 22, \ | |
1053 | 23, 24, 25, 26, 27, 28, 29, 31, \ | |
1054 | 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \ | |
1055 | 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ | |
1056 | 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ | |
1057 | 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ | |
1058 | 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ | |
1059 | 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ | |
1060 | 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ | |
1061 | 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ | |
1062 | 32, 33, /* %f0,%f1 */ \ | |
1063 | 96, 97, 98, 99, /* %fcc0-3 */ \ | |
1064 | 1, 5, 2, 3, 4, 6, 7, 0, 14, 30} | |
1065 | #else | |
1bb87f28 | 1066 | #define REG_ALLOC_ORDER \ |
b4ac57ab RS |
1067 | { 8, 9, 10, 11, 12, 13, 2, 3, \ |
1068 | 15, 16, 17, 18, 19, 20, 21, 22, \ | |
1069 | 23, 24, 25, 26, 27, 28, 29, 31, \ | |
51f0e748 | 1070 | 34, 35, 36, 37, 38, 39, \ |
1bb87f28 JW |
1071 | 40, 41, 42, 43, 44, 45, 46, 47, \ |
1072 | 48, 49, 50, 51, 52, 53, 54, 55, \ | |
1073 | 56, 57, 58, 59, 60, 61, 62, 63, \ | |
51f0e748 | 1074 | 32, 33, \ |
4b69d2a3 | 1075 | 1, 4, 5, 6, 7, 0, 14, 30} |
7a6cf439 | 1076 | #endif |
1bb87f28 JW |
1077 | |
1078 | /* This is the order in which to allocate registers for | |
1079 | leaf functions. If all registers can fit in the "i" registers, | |
7a6cf439 DE |
1080 | then we have the possibility of having a leaf function. |
1081 | v9: The floating point registers are ordered a little "funny" because some | |
1082 | of them (%f16-%f47) are call-preserved. */ | |
6f64bf5f | 1083 | #if SPARC_V9 |
7a6cf439 DE |
1084 | #define REG_LEAF_ALLOC_ORDER \ |
1085 | { 24, 25, 26, 27, 28, 29, \ | |
1086 | 15, 8, 9, 10, 11, 12, 13, \ | |
1087 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
1088 | 34, 35, 36, 37, 38, 39, \ | |
1089 | 40, 41, 42, 43, 44, 45, 46, 47, \ | |
1090 | 80, 81, 82, 83, 84, 85, 86, 87, \ | |
1091 | 88, 89, 90, 91, 92, 93, 94, 95, \ | |
1092 | 48, 49, 50, 51, 52, 53, 54, 55, \ | |
1093 | 56, 57, 58, 59, 60, 61, 62, 63, \ | |
1094 | 64, 65, 66, 67, 68, 69, 70, 71, \ | |
1095 | 72, 73, 74, 75, 76, 77, 78, 79, \ | |
1096 | 32, 33, \ | |
1097 | 96, 97, 98, 99, \ | |
1098 | 1, 5, 2, 3, 4, 6, 7, 0, 14, 30, 31} | |
1099 | #else | |
1bb87f28 JW |
1100 | #define REG_LEAF_ALLOC_ORDER \ |
1101 | { 2, 3, 24, 25, 26, 27, 28, 29, \ | |
1102 | 15, 8, 9, 10, 11, 12, 13, \ | |
1103 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
51f0e748 | 1104 | 34, 35, 36, 37, 38, 39, \ |
1bb87f28 JW |
1105 | 40, 41, 42, 43, 44, 45, 46, 47, \ |
1106 | 48, 49, 50, 51, 52, 53, 54, 55, \ | |
1107 | 56, 57, 58, 59, 60, 61, 62, 63, \ | |
51f0e748 | 1108 | 32, 33, \ |
4b69d2a3 | 1109 | 1, 4, 5, 6, 7, 0, 14, 30, 31} |
7a6cf439 | 1110 | #endif |
1bb87f28 JW |
1111 | |
1112 | #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () | |
1113 | ||
5c56efde DE |
1114 | /* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when |
1115 | -mflat is used. Function only_leaf_regs_used will return 0 if a global | |
1116 | register is used and is not permitted in a leaf function. We make %g7 | |
1117 | a global reg if -mflat and voila. Since %g7 is a system register and is | |
1118 | fixed it won't be used by gcc anyway. */ | |
6f64bf5f | 1119 | #if SPARC_V9 |
7a6cf439 DE |
1120 | #define LEAF_REGISTERS \ |
1121 | { 1, 1, 1, 1, 1, 1, 1, 0, \ | |
1122 | 0, 0, 0, 0, 0, 0, 1, 0, \ | |
1123 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1124 | 1, 1, 1, 1, 1, 1, 0, 1, \ | |
1125 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1126 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1127 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1128 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1129 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1130 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1131 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1132 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1133 | 1, 1, 1, 1} | |
1134 | #else | |
1bb87f28 | 1135 | #define LEAF_REGISTERS \ |
5c56efde | 1136 | { 1, 1, 1, 1, 1, 1, 1, 0, \ |
1bb87f28 JW |
1137 | 0, 0, 0, 0, 0, 0, 1, 0, \ |
1138 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1139 | 1, 1, 1, 1, 1, 1, 0, 1, \ | |
1140 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1141 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1142 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
4b69d2a3 | 1143 | 1, 1, 1, 1, 1, 1, 1, 1} |
7a6cf439 | 1144 | #endif |
1bb87f28 JW |
1145 | |
1146 | extern char leaf_reg_remap[]; | |
1147 | #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) | |
1bb87f28 | 1148 | |
1bb87f28 JW |
1149 | /* The class value for index registers, and the one for base regs. */ |
1150 | #define INDEX_REG_CLASS GENERAL_REGS | |
1151 | #define BASE_REG_CLASS GENERAL_REGS | |
1152 | ||
24b63396 | 1153 | /* Local macro to handle the two v9 classes of FP regs. */ |
6f64bf5f | 1154 | #if SPARC_V9 |
24b63396 JW |
1155 | #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) |
1156 | #else | |
1157 | #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS) | |
1158 | #endif | |
1159 | ||
1bb87f28 JW |
1160 | /* Get reg_class from a letter such as appears in the machine description. */ |
1161 | ||
6f64bf5f | 1162 | #if SPARC_V9 |
7a6cf439 | 1163 | #define REG_CLASS_FROM_LETTER(C) \ |
24b63396 JW |
1164 | ((C) == 'f' ? FP_REGS \ |
1165 | : (C) == 'e' ? EXTRA_FP_REGS \ | |
1166 | : (C) == 'c' ? FPCC_REGS \ | |
1167 | : NO_REGS) | |
7a6cf439 | 1168 | #else |
24b63396 JW |
1169 | /* Coerce v9's 'e' class to 'f', so we can use 'e' in the .md file for |
1170 | v8 and v9. */ | |
1bb87f28 | 1171 | #define REG_CLASS_FROM_LETTER(C) \ |
24b63396 | 1172 | ((C) == 'f' ? FP_REGS : (C) == 'e' ? FP_REGS : NO_REGS) |
7a6cf439 | 1173 | #endif |
1bb87f28 JW |
1174 | |
1175 | /* The letters I, J, K, L and M in a register constraint string | |
1176 | can be used to stand for particular ranges of immediate operands. | |
1177 | This macro defines what the ranges are. | |
1178 | C is the letter, and VALUE is a constant value. | |
1179 | Return 1 if VALUE is in the range specified by C. | |
1180 | ||
1181 | For SPARC, `I' is used for the range of constants an insn | |
1182 | can actually contain. | |
1183 | `J' is used for the range which is just zero (since that is R0). | |
9ad2c692 | 1184 | `K' is used for constants which can be loaded with a single sethi insn. */ |
1bb87f28 JW |
1185 | |
1186 | #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000) | |
1187 | ||
1188 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
1189 | ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \ | |
1190 | : (C) == 'J' ? (VALUE) == 0 \ | |
1191 | : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \ | |
1192 | : 0) | |
1193 | ||
1194 | /* Similar, but for floating constants, and defining letters G and H. | |
1195 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
1196 | ||
1197 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
96f69de5 | 1198 | ((C) == 'G' ? fp_zero_operand (VALUE) \ |
1bb87f28 JW |
1199 | : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ |
1200 | : 0) | |
1201 | ||
1202 | /* Given an rtx X being reloaded into a reg required to be | |
1203 | in class CLASS, return the class of reg to actually use. | |
1204 | In general this is just CLASS; but on some machines | |
1205 | in some cases it is preferable to use a more restrictive class. */ | |
2b9a9aea JW |
1206 | /* We can't load constants into FP registers. We can't load any FP constant |
1207 | if an 'E' constraint fails to match it. */ | |
1208 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
1209 | (CONSTANT_P (X) \ | |
24b63396 | 1210 | && (FP_REG_CLASS_P (CLASS) \ |
2b9a9aea JW |
1211 | || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ |
1212 | && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \ | |
1213 | || HOST_BITS_PER_INT != BITS_PER_WORD))) \ | |
1214 | ? NO_REGS : (CLASS)) | |
1bb87f28 JW |
1215 | |
1216 | /* Return the register class of a scratch register needed to load IN into | |
1217 | a register of class CLASS in MODE. | |
1218 | ||
1219 | On the SPARC, when PIC, we need a temporary when loading some addresses | |
ae51bd97 | 1220 | into a register. |
1bb87f28 | 1221 | |
ae51bd97 JW |
1222 | Also, we need a temporary when loading/storing a HImode/QImode value |
1223 | between memory and the FPU registers. This can happen when combine puts | |
1224 | a paradoxical subreg in a float/fix conversion insn. */ | |
1225 | ||
1226 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
24b63396 JW |
1227 | ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \ |
1228 | && (GET_CODE (IN) == MEM \ | |
1229 | || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ | |
1230 | && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS) | |
ae51bd97 JW |
1231 | |
1232 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
24b63396 JW |
1233 | ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \ |
1234 | && (GET_CODE (IN) == MEM \ | |
1235 | || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ | |
1236 | && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS) | |
1bb87f28 | 1237 | |
b924cef0 JW |
1238 | /* On SPARC it is not possible to directly move data between |
1239 | GENERAL_REGS and FP_REGS. */ | |
24b63396 JW |
1240 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1241 | (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) | |
b924cef0 | 1242 | |
55be783d JW |
1243 | /* Return the stack location to use for secondary memory needed reloads. |
1244 | We want to use the reserved location just below the frame pointer. | |
1245 | However, we must ensure that there is a frame, so use assign_stack_local | |
1246 | if the frame size is zero. */ | |
fe1f7f24 | 1247 | #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ |
55be783d | 1248 | (get_frame_size () == 0 \ |
fb3eb6f6 | 1249 | ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \ |
55be783d JW |
1250 | : gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \ |
1251 | GEN_INT (STARTING_FRAME_OFFSET)))) | |
fe1f7f24 | 1252 | |
7a6cf439 DE |
1253 | /* Get_secondary_mem widens it's argument to BITS_PER_WORD which loses on v9 |
1254 | because the movsi and movsf patterns don't handle r/f moves. | |
1255 | For v8 we copy the default definition. */ | |
1256 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
6f64bf5f | 1257 | (TARGET_ARCH64 \ |
fb3eb6f6 JW |
1258 | ? (GET_MODE_BITSIZE (MODE) < 32 \ |
1259 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
7a6cf439 | 1260 | : MODE) \ |
fb3eb6f6 JW |
1261 | : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ |
1262 | ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ | |
7a6cf439 DE |
1263 | : MODE)) |
1264 | ||
1bb87f28 JW |
1265 | /* Return the maximum number of consecutive registers |
1266 | needed to represent mode MODE in a register of class CLASS. */ | |
1267 | /* On SPARC, this is the size of MODE in words. */ | |
1268 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
24b63396 | 1269 | (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ |
7a6cf439 | 1270 | : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
1bb87f28 JW |
1271 | \f |
1272 | /* Stack layout; function entry, exit and calling. */ | |
1273 | ||
1274 | /* Define the number of register that can hold parameters. | |
7a6cf439 DE |
1275 | These two macros are used only in other macro definitions below. |
1276 | MODE is the mode of the argument. | |
1277 | !v9: All args are passed in %o0-%o5. | |
1278 | v9: Non-float args are passed in %o0-5 and float args are passed in | |
1279 | %f0-%f15. */ | |
1280 | #define NPARM_REGS(MODE) \ | |
6f64bf5f | 1281 | (TARGET_ARCH64 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 16 : 6) : 6) |
1bb87f28 JW |
1282 | |
1283 | /* Define this if pushing a word on the stack | |
1284 | makes the stack pointer a smaller address. */ | |
1285 | #define STACK_GROWS_DOWNWARD | |
1286 | ||
1287 | /* Define this if the nominal address of the stack frame | |
1288 | is at the high-address end of the local variables; | |
1289 | that is, each additional local variable allocated | |
1290 | goes at a more negative offset in the frame. */ | |
1291 | #define FRAME_GROWS_DOWNWARD | |
1292 | ||
1293 | /* Offset within stack frame to start allocating local variables at. | |
1294 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1295 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1296 | of the first local allocated. */ | |
7238ce3a JW |
1297 | /* This allows space for one TFmode floating point value. */ |
1298 | #define STARTING_FRAME_OFFSET \ | |
6f64bf5f | 1299 | (TARGET_ARCH64 ? (SPARC_STACK_BIAS - 16) \ |
7a6cf439 | 1300 | : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))) |
1bb87f28 JW |
1301 | |
1302 | /* If we generate an insn to push BYTES bytes, | |
1303 | this says how many the stack pointer really advances by. | |
1304 | On SPARC, don't define this because there are no push insns. */ | |
1305 | /* #define PUSH_ROUNDING(BYTES) */ | |
1306 | ||
1307 | /* Offset of first parameter from the argument pointer register value. | |
7a6cf439 DE |
1308 | !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg |
1309 | even if this function isn't going to use it. | |
1310 | v9: This is 128 for the ins and locals, plus a reserved space of 8. */ | |
1311 | #define FIRST_PARM_OFFSET(FNDECL) \ | |
6f64bf5f | 1312 | (TARGET_ARCH64 ? (SPARC_STACK_BIAS + 136) \ |
7a6cf439 | 1313 | : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)) |
1bb87f28 JW |
1314 | |
1315 | /* When a parameter is passed in a register, stack space is still | |
1316 | allocated for it. */ | |
6f64bf5f | 1317 | #if ! SPARC_ARCH64 |
7a6cf439 DE |
1318 | #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS (SImode) * UNITS_PER_WORD) |
1319 | #endif | |
1bb87f28 JW |
1320 | |
1321 | /* Keep the stack pointer constant throughout the function. | |
b4ac57ab | 1322 | This is both an optimization and a necessity: longjmp |
1bb87f28 JW |
1323 | doesn't behave itself when the stack pointer moves within |
1324 | the function! */ | |
1325 | #define ACCUMULATE_OUTGOING_ARGS | |
1326 | ||
1327 | /* Value is the number of bytes of arguments automatically | |
1328 | popped when returning from a subroutine call. | |
8b109b37 | 1329 | FUNDECL is the declaration node of the function (as a tree), |
1bb87f28 JW |
1330 | FUNTYPE is the data type of the function (as a tree), |
1331 | or for a library call it is an identifier node for the subroutine name. | |
1332 | SIZE is the number of bytes of arguments passed on the stack. */ | |
1333 | ||
8b109b37 | 1334 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
1bb87f28 | 1335 | |
5b485d2c JW |
1336 | /* Some subroutine macros specific to this machine. |
1337 | When !TARGET_FPU, put float return values in the general registers, | |
1338 | since we don't have any fp registers. */ | |
1bb87f28 | 1339 | #define BASE_RETURN_VALUE_REG(MODE) \ |
6f64bf5f DE |
1340 | (TARGET_ARCH64 \ |
1341 | ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \ | |
7a6cf439 | 1342 | : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)) |
1bb87f28 | 1343 | #define BASE_OUTGOING_VALUE_REG(MODE) \ |
6f64bf5f DE |
1344 | (TARGET_ARCH64 \ |
1345 | ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \ | |
bafb031b | 1346 | : TARGET_FLAT ? 8 : 24) \ |
7a6cf439 | 1347 | : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \ |
bafb031b | 1348 | : (TARGET_FLAT ? 8 : 24))) |
7a6cf439 | 1349 | #define BASE_PASSING_ARG_REG(MODE) \ |
6f64bf5f DE |
1350 | (TARGET_ARCH64 \ |
1351 | ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \ | |
1352 | : 8) | |
7a6cf439 | 1353 | #define BASE_INCOMING_ARG_REG(MODE) \ |
6f64bf5f DE |
1354 | (TARGET_ARCH64 \ |
1355 | ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \ | |
bafb031b DE |
1356 | : TARGET_FLAT ? 8 : 24) \ |
1357 | : (TARGET_FLAT ? 8 : 24)) | |
1bb87f28 | 1358 | |
92ea370b TW |
1359 | /* Define this macro if the target machine has "register windows". This |
1360 | C expression returns the register number as seen by the called function | |
1361 | corresponding to register number OUT as seen by the calling function. | |
1362 | Return OUT if register number OUT is not an outbound register. */ | |
1363 | ||
1364 | #define INCOMING_REGNO(OUT) \ | |
bafb031b | 1365 | ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) |
92ea370b TW |
1366 | |
1367 | /* Define this macro if the target machine has "register windows". This | |
1368 | C expression returns the register number as seen by the calling function | |
1369 | corresponding to register number IN as seen by the called function. | |
1370 | Return IN if register number IN is not an inbound register. */ | |
1371 | ||
1372 | #define OUTGOING_REGNO(IN) \ | |
bafb031b | 1373 | ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) |
92ea370b | 1374 | |
1bb87f28 JW |
1375 | /* Define how to find the value returned by a function. |
1376 | VALTYPE is the data type of the value (as a tree). | |
1377 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1378 | otherwise, FUNC is 0. */ | |
1379 | ||
1380 | /* On SPARC the value is found in the first "output" register. */ | |
1381 | ||
1382 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
1383 | gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE))) | |
1384 | ||
1385 | /* But the called function leaves it in the first "input" register. */ | |
1386 | ||
1387 | #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ | |
1388 | gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE))) | |
1389 | ||
1390 | /* Define how to find the value returned by a library function | |
1391 | assuming the value has mode MODE. */ | |
1392 | ||
1393 | #define LIBCALL_VALUE(MODE) \ | |
1394 | gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE)) | |
1395 | ||
1396 | /* 1 if N is a possible register number for a function value | |
1397 | as seen by the caller. | |
1398 | On SPARC, the first "output" reg is used for integer values, | |
1399 | and the first floating point register is used for floating point values. */ | |
1400 | ||
1401 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) | |
1402 | ||
34aaacec JW |
1403 | /* Define the size of space to allocate for the return value of an |
1404 | untyped_call. */ | |
1405 | ||
1406 | #define APPLY_RESULT_SIZE 16 | |
1407 | ||
1bb87f28 | 1408 | /* 1 if N is a possible register number for function argument passing. |
7a6cf439 | 1409 | On SPARC, these are the "output" registers. v9 also uses %f0-%f15. */ |
1bb87f28 | 1410 | |
7a6cf439 | 1411 | #define FUNCTION_ARG_REGNO_P(N) \ |
6f64bf5f | 1412 | (TARGET_ARCH64 ? (((N) < 14 && (N) > 7) || (N) > 31 && (N) < 48) \ |
7a6cf439 | 1413 | : ((N) < 14 && (N) > 7)) |
1bb87f28 JW |
1414 | \f |
1415 | /* Define a data type for recording info about an argument list | |
1416 | during the scan of that argument list. This data type should | |
1417 | hold all necessary information about the function itself | |
1418 | and about the args processed so far, enough to enable macros | |
1419 | such as FUNCTION_ARG to determine where the next arg should go. | |
1420 | ||
7a6cf439 | 1421 | On SPARC (!v9), this is a single integer, which is a number of words |
1bb87f28 JW |
1422 | of arguments scanned so far (including the invisible argument, |
1423 | if any, which holds the structure-value-address). | |
7a6cf439 DE |
1424 | Thus 7 or more means all following args should go on the stack. |
1425 | ||
1426 | For v9, we record how many of each type has been passed. Different | |
1427 | types get passed differently. | |
1428 | ||
1429 | - Float args are passed in %f0-15, after which they go to the stack | |
1430 | where floats and doubles are passed 8 byte aligned and long doubles | |
1431 | are passed 16 byte aligned. | |
1432 | - All aggregates are passed by reference. The callee copies | |
1433 | the structure if necessary, except if stdarg/varargs and the struct | |
1434 | matches the ellipse in which case the caller makes a copy. | |
1435 | - Any non-float argument might be split between memory and reg %o5. | |
1436 | ??? I don't think this can ever happen now that structs are no | |
1437 | longer passed in regs. | |
1438 | ||
1439 | For v9 return values: | |
1440 | ||
1441 | - For all aggregates, the caller allocates space for the return value, | |
1442 | and passes the pointer as an implicit first argument, which is | |
1443 | allocated like all other arguments. | |
1444 | - The unimp instruction stuff for structure returns is gone. */ | |
1445 | ||
6f64bf5f | 1446 | #if SPARC_ARCH64 |
7a6cf439 DE |
1447 | enum sparc_arg_class { SPARC_ARG_INT = 0, SPARC_ARG_FLOAT = 1 }; |
1448 | struct sparc_args { | |
1449 | int arg_count[2]; /* must be int! (for __builtin_args_info) */ | |
1450 | }; | |
1451 | #define CUMULATIVE_ARGS struct sparc_args | |
1452 | ||
1453 | /* Return index into CUMULATIVE_ARGS. */ | |
1454 | ||
1455 | #define GET_SPARC_ARG_CLASS(MODE) \ | |
1456 | (GET_MODE_CLASS (MODE) == MODE_FLOAT ? SPARC_ARG_FLOAT : SPARC_ARG_INT) | |
1bb87f28 | 1457 | |
7a6cf439 DE |
1458 | /* Round a register number up to a proper boundary for an arg of mode MODE. |
1459 | This macro is only used in this file. | |
1460 | ||
1461 | The "& (0x10000 - ...)" is used to round up to the next appropriate reg. */ | |
1462 | ||
1463 | #define ROUND_REG(CUM, MODE) \ | |
1464 | (GET_MODE_CLASS (MODE) != MODE_FLOAT \ | |
1465 | ? (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \ | |
1466 | : ((CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \ | |
1467 | + GET_MODE_UNIT_SIZE (MODE) / 4 - 1) \ | |
1468 | & (0x10000 - GET_MODE_UNIT_SIZE (MODE) / 4)) | |
1469 | ||
1470 | #define ROUND_ADVANCE(SIZE) \ | |
1471 | (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
1472 | ||
6f64bf5f DE |
1473 | #else /* ! SPARC_ARCH64 */ |
1474 | ||
1bb87f28 JW |
1475 | #define CUMULATIVE_ARGS int |
1476 | ||
7a6cf439 DE |
1477 | #define ROUND_REG(CUM, MODE) (CUM) |
1478 | ||
1bb87f28 | 1479 | #define ROUND_ADVANCE(SIZE) \ |
b1fc14e5 | 1480 | ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
6f64bf5f | 1481 | #endif /* ! SPARC_ARCH64 */ |
b1fc14e5 | 1482 | |
1bb87f28 JW |
1483 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1484 | for a call to a function whose data type is FNTYPE. | |
1485 | For a library call, FNTYPE is 0. | |
1486 | ||
1487 | On SPARC, the offset always starts at 0: the first parm reg is always | |
1488 | the same reg. */ | |
1489 | ||
6f64bf5f | 1490 | #if SPARC_ARCH64 |
7a6cf439 DE |
1491 | extern int sparc_arg_count,sparc_n_named_args; |
1492 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ | |
1493 | do { \ | |
1494 | (CUM).arg_count[(int) SPARC_ARG_INT] = 0; \ | |
1495 | (CUM).arg_count[(int) SPARC_ARG_FLOAT] = 0; \ | |
1496 | sparc_arg_count = 0; \ | |
1497 | sparc_n_named_args = \ | |
1498 | ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE) \ | |
1499 | ? (list_length (TYPE_ARG_TYPES (FNTYPE)) \ | |
1500 | + (TREE_CODE (TREE_TYPE (FNTYPE)) == RECORD_TYPE \ | |
4a5891af DE |
1501 | || TREE_CODE (TREE_TYPE (FNTYPE)) == QUAL_UNION_TYPE\ |
1502 | || TREE_CODE (TREE_TYPE (FNTYPE)) == SET_TYPE \ | |
7a6cf439 DE |
1503 | || TREE_CODE (TREE_TYPE (FNTYPE)) == UNION_TYPE)) \ |
1504 | /* Can't tell, treat 'em all as named. */ \ | |
1505 | : 10000); \ | |
1506 | } while (0) | |
1507 | #else | |
1bb87f28 | 1508 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0) |
7a6cf439 | 1509 | #endif |
1bb87f28 JW |
1510 | |
1511 | /* Update the data in CUM to advance over an argument | |
1512 | of mode MODE and data type TYPE. | |
1513 | (TYPE is null for libcalls where that information may not be available.) */ | |
1514 | ||
6f64bf5f | 1515 | #if SPARC_ARCH64 |
7a6cf439 DE |
1516 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
1517 | do { \ | |
1518 | (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] = \ | |
1519 | ROUND_REG ((CUM), (MODE)) \ | |
1520 | + (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1521 | ? GET_MODE_SIZE (MODE) / 4 \ | |
1522 | : ROUND_ADVANCE ((MODE) == BLKmode \ | |
1523 | ? GET_MODE_SIZE (Pmode) \ | |
1524 | : GET_MODE_SIZE (MODE))); \ | |
1525 | sparc_arg_count++; \ | |
1526 | } while (0) | |
1527 | #else | |
1bb87f28 | 1528 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
95dea81f JW |
1529 | ((CUM) += ((MODE) != BLKmode \ |
1530 | ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \ | |
1531 | : ROUND_ADVANCE (int_size_in_bytes (TYPE)))) | |
7a6cf439 DE |
1532 | #endif |
1533 | ||
1534 | /* Return boolean indicating arg of mode MODE will be passed in a reg. | |
1535 | This macro is only used in this file. */ | |
1536 | ||
6f64bf5f | 1537 | #if SPARC_ARCH64 |
7a6cf439 DE |
1538 | #define PASS_IN_REG_P(CUM, MODE, TYPE) \ |
1539 | (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \ | |
1540 | && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ | |
1541 | && ((TYPE)==0 || (MODE) != BLKmode)) | |
1542 | #else | |
1543 | #define PASS_IN_REG_P(CUM, MODE, TYPE) \ | |
1544 | ((CUM) < NPARM_REGS (SImode) \ | |
1545 | && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ | |
1546 | && ((TYPE)==0 || (MODE) != BLKmode \ | |
1547 | || (TYPE_ALIGN (TYPE) % PARM_BOUNDARY == 0))) | |
1548 | #endif | |
1bb87f28 JW |
1549 | |
1550 | /* Determine where to put an argument to a function. | |
1551 | Value is zero to push the argument on the stack, | |
1552 | or a hard register in which to store the argument. | |
1553 | ||
1554 | MODE is the argument's machine mode. | |
1555 | TYPE is the data type of the argument (as a tree). | |
1556 | This is null for libcalls where that information may | |
1557 | not be available. | |
1558 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1559 | the preceding args and about the function being called. | |
1560 | NAMED is nonzero if this argument is a named parameter | |
1561 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1562 | ||
1563 | /* On SPARC the first six args are normally in registers | |
1564 | and the rest are pushed. Any arg that starts within the first 6 words | |
7a6cf439 DE |
1565 | is at least partially passed in a register unless its data type forbids. |
1566 | For v9, the first 6 int args are passed in regs and the first N | |
1567 | float args are passed in regs (where N is such that %f0-15 are filled). | |
1568 | The rest are pushed. Any arg that starts within the first 6 words | |
1bb87f28 JW |
1569 | is at least partially passed in a register unless its data type forbids. */ |
1570 | ||
1571 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
7a6cf439 DE |
1572 | (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ |
1573 | ? gen_rtx (REG, (MODE), \ | |
1574 | (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\ | |
1575 | : 0) | |
1bb87f28 JW |
1576 | |
1577 | /* Define where a function finds its arguments. | |
1578 | This is different from FUNCTION_ARG because of register windows. */ | |
1579 | ||
1580 | #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ | |
7a6cf439 DE |
1581 | (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ |
1582 | ? gen_rtx (REG, (MODE), \ | |
1583 | (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\ | |
1584 | : 0) | |
1bb87f28 JW |
1585 | |
1586 | /* For an arg passed partly in registers and partly in memory, | |
1587 | this is the number of registers used. | |
1588 | For args passed entirely in registers or entirely in memory, zero. | |
1589 | Any arg that starts in the first 6 regs but won't entirely fit in them | |
7a6cf439 DE |
1590 | needs partial registers on the Sparc (!v9). On v9, there are no arguments |
1591 | that are passed partially in registers (??? complex values?). */ | |
1bb87f28 | 1592 | |
6f64bf5f | 1593 | #if ! SPARC_ARCH64 |
1bb87f28 | 1594 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
7a6cf439 DE |
1595 | (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ |
1596 | && ((CUM) + ((MODE) == BLKmode \ | |
1597 | ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ | |
1598 | : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS (SImode) > 0)\ | |
1599 | ? (NPARM_REGS (SImode) - (CUM)) \ | |
1bb87f28 | 1600 | : 0) |
7a6cf439 | 1601 | #endif |
1bb87f28 | 1602 | |
d9ca49d5 | 1603 | /* The SPARC ABI stipulates passing struct arguments (of any size) and |
7a6cf439 | 1604 | (!v9) quad-precision floats by invisible reference. |
87ac3809 | 1605 | For Pascal, also pass arrays by reference. */ |
3c0f5ae6 PB |
1606 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ |
1607 | ((TYPE && AGGREGATE_TYPE_P (TYPE)) \ | |
6f64bf5f | 1608 | || (!TARGET_ARCH64 && MODE == TFmode)) |
7a6cf439 DE |
1609 | |
1610 | /* A C expression that indicates when it is the called function's | |
1611 | responsibility to make copies of arguments passed by reference. | |
1612 | If the callee can determine that the argument won't be modified, it can | |
1613 | avoid the copy. */ | |
1614 | /* ??? We'd love to be able to use NAMED here. Unfortunately, it doesn't | |
1615 | include the last named argument so we keep track of the args ourselves. */ | |
1616 | ||
6f64bf5f | 1617 | #if SPARC_ARCH64 |
7a6cf439 DE |
1618 | #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \ |
1619 | (sparc_arg_count < sparc_n_named_args) | |
1620 | #endif | |
1621 | \f | |
1622 | /* Initialize data used by insn expanders. This is called from | |
1623 | init_emit, once for each function, before code is generated. | |
1624 | For v9, clear the temp slot used by float/int DImode conversions. | |
1625 | ??? There is the 16 bytes at [%fp-16], however we'd like to delete this | |
1626 | space at some point. | |
1627 | ??? Use assign_stack_temp? */ | |
1628 | ||
1629 | extern void sparc64_init_expanders (); | |
1630 | extern struct rtx_def *sparc64_fpconv_stack_temp (); | |
6f64bf5f | 1631 | #if SPARC_ARCH64 |
7a6cf439 DE |
1632 | #define INIT_EXPANDERS sparc64_init_expanders () |
1633 | #endif | |
1bb87f28 JW |
1634 | |
1635 | /* Define the information needed to generate branch and scc insns. This is | |
1636 | stored from the compare operation. Note that we can't use "rtx" here | |
1637 | since it hasn't been defined! */ | |
1638 | ||
1639 | extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1; | |
1640 | ||
1641 | /* Define the function that build the compare insn for scc and bcc. */ | |
1642 | ||
1643 | extern struct rtx_def *gen_compare_reg (); | |
7a6cf439 DE |
1644 | |
1645 | /* This function handles all v9 scc insns */ | |
1646 | ||
1647 | extern int gen_v9_scc (); | |
1bb87f28 | 1648 | \f |
4b69d2a3 RS |
1649 | /* Generate the special assembly code needed to tell the assembler whatever |
1650 | it might need to know about the return value of a function. | |
1651 | ||
1652 | For Sparc assemblers, we need to output a .proc pseudo-op which conveys | |
1653 | information to the assembler relating to peephole optimization (done in | |
1654 | the assembler). */ | |
1655 | ||
1656 | #define ASM_DECLARE_RESULT(FILE, RESULT) \ | |
1657 | fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT))) | |
1658 | ||
1bb87f28 JW |
1659 | /* Output the label for a function definition. */ |
1660 | ||
4b69d2a3 RS |
1661 | #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ |
1662 | do { \ | |
1663 | ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ | |
1664 | ASM_OUTPUT_LABEL (FILE, NAME); \ | |
1665 | } while (0) | |
1bb87f28 | 1666 | |
1bb87f28 JW |
1667 | /* This macro generates the assembly code for function entry. |
1668 | FILE is a stdio stream to output the code to. | |
1669 | SIZE is an int: how many units of temporary storage to allocate. | |
1670 | Refer to the array `regs_ever_live' to determine which registers | |
1671 | to save; `regs_ever_live[I]' is nonzero if register number I | |
1672 | is ever used in the function. This macro is responsible for | |
1673 | knowing which registers should not be saved even if used. */ | |
1674 | ||
1675 | /* On SPARC, move-double insns between fpu and cpu need an 8-byte block | |
1676 | of memory. If any fpu reg is used in the function, we allocate | |
1677 | such a block here, at the bottom of the frame, just in case it's needed. | |
1678 | ||
1679 | If this function is a leaf procedure, then we may choose not | |
1680 | to do a "save" insn. The decision about whether or not | |
1681 | to do this is made in regclass.c. */ | |
1682 | ||
a061b9fa | 1683 | extern int leaf_function; |
bafb031b DE |
1684 | #define FUNCTION_PROLOGUE(FILE, SIZE) \ |
1685 | (TARGET_FLAT ? sparc_flat_output_function_prologue (FILE, SIZE) \ | |
5b485d2c | 1686 | : output_function_prologue (FILE, SIZE, leaf_function)) |
1bb87f28 JW |
1687 | |
1688 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
1689 | for profiling a function entry. */ | |
1690 | ||
d2a8e680 RS |
1691 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
1692 | do { \ | |
1693 | fputs ("\tsethi %hi(", (FILE)); \ | |
1694 | ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \ | |
7a6cf439 DE |
1695 | fputs ("),%o0\n", (FILE)); \ |
1696 | if (TARGET_MEDANY) \ | |
1697 | fprintf (FILE, "\tadd %%o0,%s,%%o0\n", \ | |
1698 | MEDANY_BASE_REG); \ | |
1699 | fputs ("\tcall mcount\n\tadd %lo(", (FILE)); \ | |
d2a8e680 RS |
1700 | ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \ |
1701 | fputs ("),%o0,%o0\n", (FILE)); \ | |
1702 | } while (0) | |
1bb87f28 | 1703 | |
1bb87f28 | 1704 | |
88c956eb RK |
1705 | /* There are three profiling modes for basic blocks available. |
1706 | The modes are selected at compile time by using the options | |
1707 | -a or -ax of the gnu compiler. | |
1708 | The variable `profile_block_flag' will be set according to the | |
1709 | selected option. | |
1710 | ||
1711 | profile_block_flag == 0, no option used: | |
1712 | ||
1713 | No profiling done. | |
1714 | ||
1715 | profile_block_flag == 1, -a option used. | |
1716 | ||
1717 | Count frequency of execution of every basic block. | |
1718 | ||
1719 | profile_block_flag == 2, -ax option used. | |
1720 | ||
1721 | Generate code to allow several different profiling modes at run time. | |
1722 | Available modes are: | |
1723 | Produce a trace of all basic blocks. | |
1724 | Count frequency of jump instructions executed. | |
1725 | In every mode it is possible to start profiling upon entering | |
1726 | certain functions and to disable profiling of some other functions. | |
1727 | ||
1728 | The result of basic-block profiling will be written to a file `bb.out'. | |
1729 | If the -ax option is used parameters for the profiling will be read | |
1730 | from file `bb.in'. | |
1731 | ||
1732 | */ | |
1733 | ||
1734 | /* The following macro shall output assembler code to FILE | |
1735 | to initialize basic-block profiling. | |
1736 | ||
1737 | If profile_block_flag == 2 | |
1738 | ||
1739 | Output code to call the subroutine `__bb_init_trace_func' | |
1740 | and pass two parameters to it. The first parameter is | |
1741 | the address of a block allocated in the object module. | |
1742 | The second parameter is the number of the first basic block | |
1743 | of the function. | |
1744 | ||
1745 | The name of the block is a local symbol made with this statement: | |
1746 | ||
1747 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); | |
1748 | ||
1749 | Of course, since you are writing the definition of | |
1750 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
1751 | can take a short cut in the definition of this macro and use the | |
1752 | name that you know will result. | |
1753 | ||
1754 | The number of the first basic block of the function is | |
1755 | passed to the macro in BLOCK_OR_LABEL. | |
1756 | ||
1757 | If described in a virtual assembler language the code to be | |
1758 | output looks like: | |
1759 | ||
1760 | parameter1 <- LPBX0 | |
1761 | parameter2 <- BLOCK_OR_LABEL | |
1762 | call __bb_init_trace_func | |
1763 | ||
1764 | else if profile_block_flag != 0 | |
1765 | ||
1766 | Output code to call the subroutine `__bb_init_func' | |
1767 | and pass one single parameter to it, which is the same | |
1768 | as the first parameter to `__bb_init_trace_func'. | |
1769 | ||
1770 | The first word of this parameter is a flag which will be nonzero if | |
1771 | the object module has already been initialized. So test this word | |
1772 | first, and do not call `__bb_init_func' if the flag is nonzero. | |
1773 | Note: When profile_block_flag == 2 the test need not be done | |
1774 | but `__bb_init_trace_func' *must* be called. | |
1775 | ||
1776 | BLOCK_OR_LABEL may be used to generate a label number as a | |
1777 | branch destination in case `__bb_init_func' will not be called. | |
1778 | ||
1779 | If described in a virtual assembler language the code to be | |
1780 | output looks like: | |
1781 | ||
1782 | cmp (LPBX0),0 | |
1783 | jne local_label | |
1784 | parameter1 <- LPBX0 | |
1785 | call __bb_init_func | |
1786 | local_label: | |
1787 | ||
1788 | */ | |
1789 | ||
1790 | #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \ | |
1791 | do \ | |
1792 | { \ | |
1793 | int bol = (BLOCK_OR_LABEL); \ | |
1794 | switch (profile_block_flag) \ | |
1795 | { \ | |
1796 | case 2: \ | |
1797 | if (TARGET_MEDANY) \ | |
1798 | fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tadd %%o0,%s,%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tadd %g0,%%lo(%d),%%o1\n",\ | |
1799 | MEDANY_BASE_REG, bol, bol); \ | |
1800 | else \ | |
1801 | fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%o0,%%lo(LPBX0),%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tor %%o1,%%lo(%d),%%o1\n",\ | |
1802 | bol, bol); \ | |
1803 | break; \ | |
1804 | default: \ | |
1805 | if (TARGET_MEDANY) \ | |
1806 | fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%s,%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\ | |
1807 | MEDANY_BASE_REG, bol, MEDANY_BASE_REG, bol);\ | |
1808 | else \ | |
1809 | fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\ | |
1810 | bol, bol); \ | |
1811 | break; \ | |
1812 | } \ | |
1813 | } \ | |
1814 | while (0) | |
1815 | ||
1816 | /* The following macro shall output assembler code to FILE | |
1817 | to increment a counter associated with basic block number BLOCKNO. | |
1818 | ||
1819 | If profile_block_flag == 2 | |
1820 | ||
1821 | Output code to initialize the global structure `__bb' and | |
1822 | call the function `__bb_trace_func' which will increment the | |
1823 | counter. | |
1824 | ||
1825 | `__bb' consists of two words. In the first word the number | |
1826 | of the basic block has to be stored. In the second word | |
1827 | the address of a block allocated in the object module | |
1828 | has to be stored. | |
1829 | ||
1830 | The basic block number is given by BLOCKNO. | |
1831 | ||
1832 | The address of the block is given by the label created with | |
1833 | ||
1834 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); | |
1835 | ||
1836 | by FUNCTION_BLOCK_PROFILER. | |
1837 | ||
1838 | Of course, since you are writing the definition of | |
1839 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
1840 | can take a short cut in the definition of this macro and use the | |
1841 | name that you know will result. | |
1842 | ||
1843 | If described in a virtual assembler language the code to be | |
1844 | output looks like: | |
1845 | ||
1846 | move BLOCKNO -> (__bb) | |
1847 | move LPBX0 -> (__bb+4) | |
1848 | call __bb_trace_func | |
1849 | ||
1850 | Note that function `__bb_trace_func' must not change the | |
1851 | machine state, especially the flag register. To grant | |
1852 | this, you must output code to save and restore registers | |
1853 | either in this macro or in the macros MACHINE_STATE_SAVE | |
1854 | and MACHINE_STATE_RESTORE. The last two macros will be | |
1855 | used in the function `__bb_trace_func', so you must make | |
1856 | sure that the function prologue does not change any | |
1857 | register prior to saving it with MACHINE_STATE_SAVE. | |
1858 | ||
1859 | else if profile_block_flag != 0 | |
1860 | ||
1861 | Output code to increment the counter directly. | |
1862 | Basic blocks are numbered separately from zero within each | |
1863 | compiled object module. The count associated with block number | |
1864 | BLOCKNO is at index BLOCKNO in an array of words; the name of | |
1865 | this array is a local symbol made with this statement: | |
1866 | ||
1867 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2); | |
1868 | ||
1869 | Of course, since you are writing the definition of | |
1870 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
1871 | can take a short cut in the definition of this macro and use the | |
1872 | name that you know will result. | |
1873 | ||
1874 | If described in a virtual assembler language, the code to be | |
1875 | output looks like: | |
1876 | ||
1877 | inc (LPBX2+4*BLOCKNO) | |
1878 | ||
1879 | */ | |
1880 | ||
1881 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ | |
1882 | do \ | |
1883 | { \ | |
1884 | int blockn = (BLOCKNO); \ | |
1885 | switch (profile_block_flag) \ | |
1886 | { \ | |
1887 | case 2: \ | |
1888 | if (TARGET_MEDANY) \ | |
1889 | fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tor %%0,%%lo(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%s+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%0,%%lo(LPBX0),%%g2\n\tadd %%g2,%s,%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%g1+%%lo(___bb)]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\ | |
1890 | blockn, blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \ | |
1891 | else \ | |
1892 | fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%g2,%%lo(LPBX0),%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\ | |
1893 | blockn, blockn); \ | |
1894 | break; \ | |
1895 | default: \ | |
1896 | if (TARGET_MEDANY) \ | |
1897 | fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tor %%g1,%%lo(LPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \ | |
1898 | 4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \ | |
1899 | else \ | |
1900 | fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\ | |
7a6cf439 | 1901 | \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \ |
88c956eb RK |
1902 | 4 * blockn, 4 * blockn, 4 * blockn); \ |
1903 | break; \ | |
1904 | } \ | |
1905 | } \ | |
1906 | while(0) | |
1907 | ||
1908 | /* The following macro shall output assembler code to FILE | |
1909 | to indicate a return from function during basic-block profiling. | |
1910 | ||
1911 | If profiling_block_flag == 2: | |
1912 | ||
1913 | Output assembler code to call function `__bb_trace_ret'. | |
1914 | ||
1915 | Note that function `__bb_trace_ret' must not change the | |
1916 | machine state, especially the flag register. To grant | |
1917 | this, you must output code to save and restore registers | |
1918 | either in this macro or in the macros MACHINE_STATE_SAVE_RET | |
1919 | and MACHINE_STATE_RESTORE_RET. The last two macros will be | |
1920 | used in the function `__bb_trace_ret', so you must make | |
1921 | sure that the function prologue does not change any | |
1922 | register prior to saving it with MACHINE_STATE_SAVE_RET. | |
1923 | ||
1924 | else if profiling_block_flag != 0: | |
1925 | ||
1926 | The macro will not be used, so it need not distinguish | |
1927 | these cases. | |
1928 | */ | |
1929 | ||
1930 | #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \ | |
1931 | fprintf (FILE, "\tcall ___bb_trace_ret\n\tnop\n" ); | |
1932 | ||
1933 | /* The function `__bb_trace_func' is called in every basic block | |
1934 | and is not allowed to change the machine state. Saving (restoring) | |
1935 | the state can either be done in the BLOCK_PROFILER macro, | |
1936 | before calling function (rsp. after returning from function) | |
1937 | `__bb_trace_func', or it can be done inside the function by | |
1938 | defining the macros: | |
1939 | ||
1940 | MACHINE_STATE_SAVE(ID) | |
1941 | MACHINE_STATE_RESTORE(ID) | |
1942 | ||
1943 | In the latter case care must be taken, that the prologue code | |
1944 | of function `__bb_trace_func' does not already change the | |
1945 | state prior to saving it with MACHINE_STATE_SAVE. | |
1946 | ||
1947 | The parameter `ID' is a string identifying a unique macro use. | |
1948 | ||
1949 | On sparc it is sufficient to save the psw register to memory. | |
1950 | Unfortunately the psw register can be read in supervisor mode only, | |
1951 | so we read only the condition codes by using branch instructions | |
1952 | and hope that this is enough. */ | |
1953 | ||
1954 | #define MACHINE_STATE_SAVE(ID) \ | |
1955 | asm (" mov %g0,%l0");\ | |
1956 | asm (" be,a LFLGNZ" ID);\ | |
1957 | asm (" or %l0,4,%l0");\ | |
1958 | asm ("LFLGNZ" ID ": bcs,a LFLGNC" ID);\ | |
1959 | asm (" or %l0,1,%l0");\ | |
1960 | asm ("LFLGNC" ID ": bvs,a LFLGNV" ID);\ | |
1961 | asm (" or %l0,2,%l0");\ | |
1962 | asm ("LFLGNV" ID ": bneg,a LFLGNN" ID);\ | |
1963 | asm (" or %l0,8,%l0");\ | |
1964 | asm ("LFLGNN" ID ": sethi %hi(LFLAGS" ID "),%l1");\ | |
1965 | asm (" st %l0,[%l1+%lo(LFLAGS" ID ")]"); \ | |
1966 | asm (" st %g2,[%l1+%lo(LSAVRET" ID ")]"); | |
1967 | ||
1968 | /* On sparc MACHINE_STATE_RESTORE restores the psw register from memory. | |
1969 | The psw register can be written in supervisor mode only, | |
1970 | which is true even for simple condition codes. | |
1971 | We use some combination of instructions to produce the | |
1972 | proper condition codes, but some flag combinations can not | |
1973 | be generated in this way. If this happens an unimplemented | |
1974 | instruction will be executed to abort the program. */ | |
1975 | ||
1976 | #define MACHINE_STATE_RESTORE(ID) \ | |
1977 | asm (" sethi %hi(LFLGTAB" ID "),%l1");\ | |
1978 | asm (" ld [%l1+%lo(LFLGTAB" ID "-(LFLGTAB" ID "-LFLAGS" ID "))],%l0");\ | |
1979 | asm (" ld [%l1+%lo(LFLGTAB" ID "-(LFLGTAB" ID "-LSAVRET" ID "))],%g2");\ | |
1980 | asm (" sll %l0,2,%l0");\ | |
1981 | asm (" add %l0,%l1,%l0");\ | |
1982 | asm (" ld [%l0+%lo(LFLGTAB" ID ")],%l1");\ | |
1983 | asm (" jmp %l1");\ | |
1984 | asm (" nop");\ | |
1985 | asm (".data");\ | |
1d7f2164 | 1986 | asm (" .align 4");\ |
88c956eb RK |
1987 | asm ("LFLAGS" ID ":");\ |
1988 | asm (" .word 0");\ | |
1989 | asm ("LSAVRET" ID ":");\ | |
1990 | asm (" .word 0");\ | |
1991 | asm ("LFLGTAB" ID ": ");\ | |
1992 | asm (" .word LSFLG0" ID);\ | |
1993 | asm (" .word LSFLGC" ID);\ | |
1994 | asm (" .word LSFLGV" ID);\ | |
1995 | asm (" .word LSFLGVC" ID);\ | |
1996 | asm (" .word LSFLGZ" ID);\ | |
1997 | asm (" .word LSFLGZC" ID);\ | |
1998 | asm (" .word LSFLGZV" ID);\ | |
1999 | asm (" .word LSFLGZVC" ID);\ | |
2000 | asm (" .word LSFLGN" ID);\ | |
2001 | asm (" .word LSFLGNC" ID);\ | |
2002 | asm (" .word LSFLGNV" ID);\ | |
2003 | asm (" .word LSFLGNVC" ID);\ | |
2004 | asm (" .word LSFLGNZ" ID);\ | |
2005 | asm (" .word LSFLGNZC" ID);\ | |
2006 | asm (" .word LSFLGNZV" ID);\ | |
2007 | asm (" .word LSFLGNZVC" ID);\ | |
2008 | asm (".text");\ | |
2009 | asm ("LSFLGVC" ID ": mov -1,%l0");\ | |
2010 | asm (" addcc 2,%l0,%g0");\ | |
2011 | asm (" sethi %hi(0x80000000),%l0");\ | |
2012 | asm (" mov %l0,%l1");\ | |
2013 | asm (" ba LFLGRET" ID);\ | |
2014 | asm (" addxcc %l0,%l1,%l0");\ | |
2015 | asm ("LSFLGC" ID ": mov -1,%l0");\ | |
2016 | asm (" ba LFLGRET" ID);\ | |
2017 | asm (" addcc 2,%l0,%g0");\ | |
2018 | asm ("LSFLGZC" ID ": mov -1,%l0");\ | |
2019 | asm (" ba LFLGRET" ID);\ | |
2020 | asm (" addcc 1,%l0,%l0");\ | |
2021 | asm ("LSFLGZVC" ID ": sethi %hi(0x80000000),%l0");\ | |
2022 | asm (" mov %l0,%l1");\ | |
2023 | asm (" ba LFLGRET" ID);\ | |
2024 | asm (" addcc %l0,%l1,%l0");\ | |
2025 | asm ("LSFLGZ" ID ": ba LFLGRET" ID);\ | |
2026 | asm (" subcc %g0,%g0,%g0");\ | |
2027 | asm ("LSFLGNC" ID ": add %g0,1,%l0");\ | |
2028 | asm (" ba LFLGRET" ID);\ | |
2029 | asm (" subcc %g0,%l0,%g0");\ | |
2030 | asm ("LSFLG0" ID ": ba LFLGRET" ID);\ | |
2031 | asm (" orcc 1,%g0,%g0");\ | |
2032 | asm ("LSFLGN" ID ": ba LFLGRET" ID);\ | |
2033 | asm (" orcc -1,%g0,%g0");\ | |
2034 | asm ("LSFLGV" ID ":");\ | |
2035 | asm ("LSFLGZV" ID ":");\ | |
2036 | asm ("LSFLGNV" ID ":");\ | |
2037 | asm ("LSFLGNVC" ID ":");\ | |
2038 | asm ("LSFLGNZ" ID ":");\ | |
2039 | asm ("LSFLGNZC" ID ":");\ | |
2040 | asm ("LSFLGNZV" ID ":");\ | |
2041 | asm ("LSFLGNZVC" ID ":");\ | |
2042 | asm (" unimp");\ | |
2043 | asm ("LFLGRET" ID ":"); | |
1bb87f28 | 2044 | |
1bb87f28 JW |
2045 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
2046 | the stack pointer does not matter. The value is tested only in | |
2047 | functions that have frame pointers. | |
2048 | No definition is equivalent to always zero. */ | |
2049 | ||
2050 | extern int current_function_calls_alloca; | |
2051 | extern int current_function_outgoing_args_size; | |
2052 | ||
2053 | #define EXIT_IGNORE_STACK \ | |
2054 | (get_frame_size () != 0 \ | |
2055 | || current_function_calls_alloca || current_function_outgoing_args_size) | |
2056 | ||
2057 | /* This macro generates the assembly code for function exit, | |
2058 | on machines that need it. If FUNCTION_EPILOGUE is not defined | |
2059 | then individual return instructions are generated for each | |
2060 | return statement. Args are same as for FUNCTION_PROLOGUE. | |
2061 | ||
2062 | The function epilogue should not depend on the current stack pointer! | |
2063 | It should use the frame pointer only. This is mandatory because | |
2064 | of alloca; we also take advantage of it to omit stack adjustments | |
2065 | before returning. */ | |
2066 | ||
2067 | /* This declaration is needed due to traditional/ANSI | |
2068 | incompatibilities which cannot be #ifdefed away | |
2069 | because they occur inside of macros. Sigh. */ | |
2070 | extern union tree_node *current_function_decl; | |
2071 | ||
bafb031b DE |
2072 | #define FUNCTION_EPILOGUE(FILE, SIZE) \ |
2073 | (TARGET_FLAT ? sparc_flat_output_function_epilogue (FILE, SIZE) \ | |
5b485d2c | 2074 | : output_function_epilogue (FILE, SIZE, leaf_function)) |
1bb87f28 | 2075 | |
bafb031b DE |
2076 | #define DELAY_SLOTS_FOR_EPILOGUE \ |
2077 | (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1) | |
2078 | #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \ | |
2079 | (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \ | |
5b485d2c | 2080 | : eligible_for_epilogue_delay (trial, slots_filled)) |
6a4bb1fa | 2081 | \f |
1bb87f28 JW |
2082 | /* Output assembler code for a block containing the constant parts |
2083 | of a trampoline, leaving space for the variable parts. */ | |
2084 | ||
c8392688 | 2085 | /* On 32 bit sparcs, the trampoline contains five instructions: |
6098b63e RK |
2086 | sethi #TOP_OF_FUNCTION,%g1 |
2087 | or #BOTTOM_OF_FUNCTION,%g1,%g1 | |
2088 | sethi #TOP_OF_STATIC,%g2 | |
2089 | jmp g1 | |
c8392688 RK |
2090 | or #BOTTOM_OF_STATIC,%g2,%g2 |
2091 | ||
2092 | On 64 bit sparcs, the trampoline contains 4 insns and two pseudo-immediate | |
2093 | constants (plus some padding): | |
2094 | rd %pc,%g1 | |
2095 | ldx[%g1+20],%g5 | |
2096 | ldx[%g1+28],%g1 | |
2097 | jmp %g1 | |
2098 | nop | |
2099 | nop | |
2100 | .xword context | |
2101 | .xword function */ | |
2102 | ||
2103 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
2104 | do { \ | |
6f64bf5f | 2105 | if (TARGET_ARCH64) \ |
c8392688 RK |
2106 | { \ |
2107 | fprintf (FILE, "\trd %%pc,%%g1\n"); \ | |
2108 | fprintf (FILE, "\tldx [%%g1+24],%%g5\n"); \ | |
2109 | fprintf (FILE, "\tldx [%%g1+32],%%g1\n"); \ | |
2110 | fprintf (FILE, "\tjmp %%g1\n"); \ | |
2111 | fprintf (FILE, "\tnop\n"); \ | |
2112 | fprintf (FILE, "\tnop\n"); \ | |
2113 | /* -mmedlow shouldn't generate .xwords, so don't use them at all */ \ | |
2114 | fprintf (FILE, "\t.word 0,0,0,0\n"); \ | |
2115 | } \ | |
2116 | else \ | |
2117 | { \ | |
2118 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
2119 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
2120 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
2121 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C04000)); \ | |
2122 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
2123 | } \ | |
2124 | } while (0) | |
1bb87f28 JW |
2125 | |
2126 | /* Length in units of the trampoline for entering a nested function. */ | |
2127 | ||
6f64bf5f | 2128 | #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 40 : 20) |
1bb87f28 JW |
2129 | |
2130 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
2131 | FNADDR is an RTX for the address of the function's pure code. | |
7a6cf439 | 2132 | CXT is an RTX for the static chain value for the function. */ |
1bb87f28 | 2133 | |
7a6cf439 DE |
2134 | void sparc_initialize_trampoline (); |
2135 | void sparc64_initialize_trampoline (); | |
2136 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
2137 | do { \ | |
6f64bf5f | 2138 | if (TARGET_ARCH64) \ |
7a6cf439 DE |
2139 | sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \ |
2140 | else \ | |
2141 | sparc_initialize_trampoline (TRAMP, FNADDR, CXT); \ | |
2142 | } while (0) | |
6a4bb1fa | 2143 | \f |
9a1c7cd7 JW |
2144 | /* Generate necessary RTL for __builtin_saveregs(). |
2145 | ARGLIST is the argument list; see expr.c. */ | |
2146 | extern struct rtx_def *sparc_builtin_saveregs (); | |
2147 | #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST) | |
953fe179 JW |
2148 | |
2149 | /* Generate RTL to flush the register windows so as to make arbitrary frames | |
2150 | available. */ | |
2151 | #define SETUP_FRAME_ADDRESSES() \ | |
2152 | emit_insn (gen_flush_register_windows ()) | |
2153 | ||
2154 | /* Given an rtx for the address of a frame, | |
2155 | return an rtx for the address of the word in the frame | |
7a6cf439 DE |
2156 | that holds the dynamic chain--the previous frame's address. |
2157 | ??? -mflat support? */ | |
953fe179 | 2158 | #define DYNAMIC_CHAIN_ADDRESS(frame) \ |
7a6cf439 | 2159 | gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 14 * UNITS_PER_WORD)) |
953fe179 JW |
2160 | |
2161 | /* The return address isn't on the stack, it is in a register, so we can't | |
2162 | access it from the current frame pointer. We can access it from the | |
2163 | previous frame pointer though by reading a value from the register window | |
2164 | save area. */ | |
2165 | #define RETURN_ADDR_IN_PREVIOUS_FRAME | |
2166 | ||
5b6faa70 | 2167 | /* This is the offset of the return address to the true next instruction to be |
9ad61776 | 2168 | executed for the current function. */ |
6f64bf5f DE |
2169 | #define RETURN_ADDR_OFFSET \ |
2170 | (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct)) | |
5b6faa70 | 2171 | |
953fe179 JW |
2172 | /* The current return address is in %i7. The return address of anything |
2173 | farther back is in the register window save area at [%fp+60]. */ | |
2174 | /* ??? This ignores the fact that the actual return address is +8 for normal | |
2175 | returns, and +12 for structure returns. */ | |
2176 | #define RETURN_ADDR_RTX(count, frame) \ | |
2177 | ((count == -1) \ | |
2178 | ? gen_rtx (REG, Pmode, 31) \ | |
5b6faa70 RK |
2179 | : gen_rtx (MEM, Pmode, \ |
2180 | memory_address (Pmode, plus_constant (frame, 15 * UNITS_PER_WORD)))) | |
1bb87f28 JW |
2181 | \f |
2182 | /* Addressing modes, and classification of registers for them. */ | |
2183 | ||
2184 | /* #define HAVE_POST_INCREMENT */ | |
2185 | /* #define HAVE_POST_DECREMENT */ | |
2186 | ||
2187 | /* #define HAVE_PRE_DECREMENT */ | |
2188 | /* #define HAVE_PRE_INCREMENT */ | |
2189 | ||
2190 | /* Macros to check register numbers against specific register classes. */ | |
2191 | ||
2192 | /* These assume that REGNO is a hard or pseudo reg number. | |
2193 | They give nonzero only if REGNO is a hard reg of the suitable class | |
2194 | or a pseudo reg currently allocated to a suitable hard reg. | |
2195 | Since they use reg_renumber, they are safe only once reg_renumber | |
2196 | has been allocated, which happens in local-alloc.c. */ | |
2197 | ||
2198 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
2199 | (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0) | |
2200 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
2201 | (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0) | |
2202 | #define REGNO_OK_FOR_FP_P(REGNO) \ | |
7a6cf439 DE |
2203 | (((unsigned) (REGNO) - 32 < (TARGET_V9 ? 64 : 32)) \ |
2204 | || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? 64 : 32))) | |
2205 | #define REGNO_OK_FOR_CCFP_P(REGNO) \ | |
2206 | (TARGET_V9 \ | |
2207 | && ((unsigned) (REGNO) - 96 < 4) || ((unsigned) reg_renumber[REGNO] - 96 < 4)) | |
1bb87f28 JW |
2208 | |
2209 | /* Now macros that check whether X is a register and also, | |
2210 | strictly, whether it is in a specified class. | |
2211 | ||
2212 | These macros are specific to the SPARC, and may be used only | |
2213 | in code for printing assembler insns and in conditions for | |
2214 | define_optimization. */ | |
2215 | ||
2216 | /* 1 if X is an fp register. */ | |
2217 | ||
2218 | #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) | |
2219 | \f | |
2220 | /* Maximum number of registers that can appear in a valid memory address. */ | |
2221 | ||
2222 | #define MAX_REGS_PER_ADDRESS 2 | |
2223 | ||
7aca9b9c JW |
2224 | /* Recognize any constant value that is a valid address. |
2225 | When PIC, we do not accept an address that would require a scratch reg | |
2226 | to load into a register. */ | |
1bb87f28 | 2227 | |
6eff269e BK |
2228 | #define CONSTANT_ADDRESS_P(X) \ |
2229 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
7aca9b9c JW |
2230 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ |
2231 | || (GET_CODE (X) == CONST \ | |
2232 | && ! (flag_pic && pic_address_needs_scratch (X)))) | |
2233 | ||
2234 | /* Define this, so that when PIC, reload won't try to reload invalid | |
2235 | addresses which require two reload registers. */ | |
2236 | ||
2237 | #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X)) | |
1bb87f28 JW |
2238 | |
2239 | /* Nonzero if the constant value X is a legitimate general operand. | |
2240 | Anything can be made to work except floating point constants. */ | |
2241 | ||
2242 | #define LEGITIMATE_CONSTANT_P(X) \ | |
2243 | (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode) | |
2244 | ||
2245 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
2246 | and check its validity for a certain class. | |
2247 | We have two alternate definitions for each of them. | |
2248 | The usual definition accepts all pseudo regs; the other rejects | |
2249 | them unless they have been allocated suitable hard regs. | |
2250 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
2251 | ||
2252 | Most source files want to accept pseudo regs in the hope that | |
2253 | they will get allocated to the class that the insn wants them to be in. | |
2254 | Source files for reload pass need to be strict. | |
2255 | After reload, it makes no difference, since pseudo regs have | |
2256 | been eliminated by then. */ | |
2257 | ||
2258 | /* Optional extra constraints for this machine. Borrowed from romp.h. | |
2259 | ||
2260 | For the SPARC, `Q' means that this is a memory operand but not a | |
2261 | symbolic memory operand. Note that an unassigned pseudo register | |
2262 | is such a memory operand. Needed because reload will generate | |
2263 | these things in insns and then not re-recognize the insns, causing | |
2264 | constrain_operands to fail. | |
2265 | ||
7a6cf439 | 2266 | `S' handles constraints for calls. ??? So where is it? */ |
1bb87f28 JW |
2267 | |
2268 | #ifndef REG_OK_STRICT | |
2269 | ||
2270 | /* Nonzero if X is a hard reg that can be used as an index | |
2271 | or if it is a pseudo reg. */ | |
7a6cf439 DE |
2272 | #define REG_OK_FOR_INDEX_P(X) \ |
2273 | (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32) && REGNO (X) != 0) | |
1bb87f28 JW |
2274 | /* Nonzero if X is a hard reg that can be used as a base reg |
2275 | or if it is a pseudo reg. */ | |
7a6cf439 DE |
2276 | #define REG_OK_FOR_BASE_P(X) \ |
2277 | (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32) && REGNO (X) != 0) | |
2278 | ||
2279 | /* 'T', 'U' are for aligned memory loads which aren't needed for v9. */ | |
1bb87f28 JW |
2280 | |
2281 | #define EXTRA_CONSTRAINT(OP, C) \ | |
db5e449c RS |
2282 | ((C) == 'Q' \ |
2283 | ? ((GET_CODE (OP) == MEM \ | |
7a6cf439 | 2284 | && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \ |
db5e449c RS |
2285 | && ! symbolic_memory_operand (OP, VOIDmode)) \ |
2286 | || (reload_in_progress && GET_CODE (OP) == REG \ | |
2287 | && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \ | |
6f64bf5f | 2288 | : (! TARGET_ARCH64 && (C) == 'T') \ |
19858600 | 2289 | ? (mem_aligned_8 (OP)) \ |
6f64bf5f | 2290 | : (! TARGET_ARCH64 && (C) == 'U') \ |
19858600 | 2291 | ? (register_ok_for_ldd (OP)) \ |
db5e449c | 2292 | : 0) |
19858600 | 2293 | |
1bb87f28 JW |
2294 | #else |
2295 | ||
2296 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
2297 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
2298 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
2299 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
2300 | ||
2301 | #define EXTRA_CONSTRAINT(OP, C) \ | |
9ad2c692 JW |
2302 | ((C) == 'Q' \ |
2303 | ? (GET_CODE (OP) == REG \ | |
2304 | ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \ | |
2305 | && reg_renumber[REGNO (OP)] < 0) \ | |
2306 | : GET_CODE (OP) == MEM) \ | |
6f64bf5f | 2307 | : (! TARGET_ARCH64 && (C) == 'T') \ |
b165d471 | 2308 | ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \ |
6f64bf5f | 2309 | : (! TARGET_ARCH64 && (C) == 'U') \ |
b165d471 JW |
2310 | ? (GET_CODE (OP) == REG \ |
2311 | && (REGNO (OP) < FIRST_PSEUDO_REGISTER \ | |
2312 | || reg_renumber[REGNO (OP)] > 0) \ | |
2313 | && register_ok_for_ldd (OP)) : 0) | |
1bb87f28 JW |
2314 | #endif |
2315 | \f | |
2316 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
2317 | that is a valid memory address for an instruction. | |
2318 | The MODE argument is the machine mode for the MEM expression | |
2319 | that wants to use this address. | |
2320 | ||
2321 | On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT | |
2322 | ordinarily. This changes a bit when generating PIC. | |
2323 | ||
2324 | If you change this, execute "rm explow.o recog.o reload.o". */ | |
2325 | ||
bec2e359 JW |
2326 | #define RTX_OK_FOR_BASE_P(X) \ |
2327 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
2328 | || (GET_CODE (X) == SUBREG \ | |
2329 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
2330 | && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) | |
2331 | ||
2332 | #define RTX_OK_FOR_INDEX_P(X) \ | |
2333 | ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ | |
2334 | || (GET_CODE (X) == SUBREG \ | |
2335 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
2336 | && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) | |
2337 | ||
2338 | #define RTX_OK_FOR_OFFSET_P(X) \ | |
2339 | (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000) | |
2340 | ||
1bb87f28 | 2341 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
bec2e359 JW |
2342 | { if (RTX_OK_FOR_BASE_P (X)) \ |
2343 | goto ADDR; \ | |
1bb87f28 JW |
2344 | else if (GET_CODE (X) == PLUS) \ |
2345 | { \ | |
bec2e359 JW |
2346 | register rtx op0 = XEXP (X, 0); \ |
2347 | register rtx op1 = XEXP (X, 1); \ | |
2348 | if (flag_pic && op0 == pic_offset_table_rtx) \ | |
1bb87f28 | 2349 | { \ |
bec2e359 | 2350 | if (RTX_OK_FOR_BASE_P (op1)) \ |
1bb87f28 JW |
2351 | goto ADDR; \ |
2352 | else if (flag_pic == 1 \ | |
bec2e359 JW |
2353 | && GET_CODE (op1) != REG \ |
2354 | && GET_CODE (op1) != LO_SUM \ | |
7aca9b9c JW |
2355 | && GET_CODE (op1) != MEM \ |
2356 | && (GET_CODE (op1) != CONST_INT \ | |
2357 | || SMALL_INT (op1))) \ | |
1bb87f28 JW |
2358 | goto ADDR; \ |
2359 | } \ | |
bec2e359 | 2360 | else if (RTX_OK_FOR_BASE_P (op0)) \ |
1bb87f28 | 2361 | { \ |
bec2e359 JW |
2362 | if (RTX_OK_FOR_INDEX_P (op1) \ |
2363 | || RTX_OK_FOR_OFFSET_P (op1)) \ | |
1bb87f28 JW |
2364 | goto ADDR; \ |
2365 | } \ | |
bec2e359 | 2366 | else if (RTX_OK_FOR_BASE_P (op1)) \ |
1bb87f28 | 2367 | { \ |
bec2e359 JW |
2368 | if (RTX_OK_FOR_INDEX_P (op0) \ |
2369 | || RTX_OK_FOR_OFFSET_P (op0)) \ | |
1bb87f28 JW |
2370 | goto ADDR; \ |
2371 | } \ | |
2372 | } \ | |
bec2e359 JW |
2373 | else if (GET_CODE (X) == LO_SUM) \ |
2374 | { \ | |
2375 | register rtx op0 = XEXP (X, 0); \ | |
2376 | register rtx op1 = XEXP (X, 1); \ | |
2377 | if (RTX_OK_FOR_BASE_P (op0) \ | |
2f0da906 JW |
2378 | && CONSTANT_P (op1) \ |
2379 | /* We can't allow TFmode, because an offset \ | |
2380 | greater than or equal to the alignment (8) \ | |
2381 | may cause the LO_SUM to overflow. */ \ | |
2382 | && MODE != TFmode) \ | |
bec2e359 JW |
2383 | goto ADDR; \ |
2384 | } \ | |
1bb87f28 JW |
2385 | else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \ |
2386 | goto ADDR; \ | |
2387 | } | |
2388 | \f | |
2389 | /* Try machine-dependent ways of modifying an illegitimate address | |
2390 | to be legitimate. If we find one, return the new, valid address. | |
2391 | This macro is used in only one place: `memory_address' in explow.c. | |
2392 | ||
2393 | OLDX is the address as it was before break_out_memory_refs was called. | |
2394 | In some cases it is useful to look at this to decide what needs to be done. | |
2395 | ||
2396 | MODE and WIN are passed so that this macro can use | |
2397 | GO_IF_LEGITIMATE_ADDRESS. | |
2398 | ||
2399 | It is always safe for this macro to do nothing. It exists to recognize | |
2400 | opportunities to optimize the output. */ | |
2401 | ||
2402 | /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ | |
2403 | extern struct rtx_def *legitimize_pic_address (); | |
2404 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
2405 | { rtx sparc_x = (X); \ | |
2406 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ | |
2407 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \ | |
a015279e | 2408 | force_operand (XEXP (X, 0), NULL_RTX)); \ |
1bb87f28 JW |
2409 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ |
2410 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ | |
a015279e | 2411 | force_operand (XEXP (X, 1), NULL_RTX)); \ |
1bb87f28 | 2412 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \ |
a015279e | 2413 | (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\ |
1bb87f28 JW |
2414 | XEXP (X, 1)); \ |
2415 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \ | |
2416 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ | |
a015279e | 2417 | force_operand (XEXP (X, 1), NULL_RTX)); \ |
1bb87f28 JW |
2418 | if (sparc_x != (X) && memory_address_p (MODE, X)) \ |
2419 | goto WIN; \ | |
7aca9b9c | 2420 | if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \ |
1bb87f28 JW |
2421 | else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ |
2422 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ | |
2423 | copy_to_mode_reg (Pmode, XEXP (X, 1))); \ | |
2424 | else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ | |
2425 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \ | |
2426 | copy_to_mode_reg (Pmode, XEXP (X, 0))); \ | |
2427 | else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ | |
2428 | || GET_CODE (X) == LABEL_REF) \ | |
2429 | (X) = gen_rtx (LO_SUM, Pmode, \ | |
2430 | copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \ | |
2431 | if (memory_address_p (MODE, X)) \ | |
2432 | goto WIN; } | |
2433 | ||
2434 | /* Go to LABEL if ADDR (a legitimate address expression) | |
2435 | has an effect that depends on the machine mode it is used for. | |
2436 | On the SPARC this is never true. */ | |
2437 | ||
2438 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) | |
7a6cf439 DE |
2439 | |
2440 | /* If we are referencing a function make the SYMBOL_REF special. | |
2441 | In the Medium/Anywhere code model, %g4 points to the data segment so we | |
2442 | must not add it to function addresses. */ | |
2443 | ||
2444 | #define ENCODE_SECTION_INFO(DECL) \ | |
2445 | do { \ | |
2446 | if (TARGET_MEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \ | |
2447 | SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \ | |
2448 | } while (0) | |
1bb87f28 JW |
2449 | \f |
2450 | /* Specify the machine mode that this machine uses | |
2451 | for the index in the tablejump instruction. */ | |
7a6cf439 | 2452 | #define CASE_VECTOR_MODE Pmode |
1bb87f28 JW |
2453 | |
2454 | /* Define this if the tablejump instruction expects the table | |
2455 | to contain offsets from the address of the table. | |
2456 | Do not define this if the table should contain absolute addresses. */ | |
2457 | /* #define CASE_VECTOR_PC_RELATIVE */ | |
2458 | ||
2459 | /* Specify the tree operation to be used to convert reals to integers. */ | |
2460 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
2461 | ||
2462 | /* This is the kind of divide that is easiest to do in the general case. */ | |
2463 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
2464 | ||
2465 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
2466 | #define DEFAULT_SIGNED_CHAR 1 | |
2467 | ||
2468 | /* Max number of bytes we can move from memory to memory | |
2469 | in one reasonably fast instruction. */ | |
2eef2ef1 | 2470 | #define MOVE_MAX 8 |
1bb87f28 | 2471 | |
0fb5a69e | 2472 | #if 0 /* Sun 4 has matherr, so this is no good. */ |
24e2a2bf RS |
2473 | /* This is the value of the error code EDOM for this machine, |
2474 | used by the sqrt instruction. */ | |
2475 | #define TARGET_EDOM 33 | |
2476 | ||
2477 | /* This is how to refer to the variable errno. */ | |
2478 | #define GEN_ERRNO_RTX \ | |
2479 | gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno")) | |
0fb5a69e | 2480 | #endif /* 0 */ |
24e2a2bf | 2481 | |
9a63901f RK |
2482 | /* Define if operations between registers always perform the operation |
2483 | on the full register even if a narrower mode is specified. */ | |
2484 | #define WORD_REGISTER_OPERATIONS | |
2485 | ||
2486 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
2487 | will either zero-extend or sign-extend. The value of this macro should | |
2488 | be the code that says which one of the two operations is implicitly | |
2489 | done, NIL if none. */ | |
2490 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
1bb87f28 JW |
2491 | |
2492 | /* Nonzero if access to memory by bytes is slow and undesirable. | |
2493 | For RISC chips, it means that access to memory by bytes is no | |
2494 | better than access by words when possible, so grab a whole word | |
2495 | and maybe make use of that. */ | |
2496 | #define SLOW_BYTE_ACCESS 1 | |
2497 | ||
2498 | /* We assume that the store-condition-codes instructions store 0 for false | |
2499 | and some other value for true. This is the value stored for true. */ | |
2500 | ||
2501 | #define STORE_FLAG_VALUE 1 | |
2502 | ||
2503 | /* When a prototype says `char' or `short', really pass an `int'. */ | |
2504 | #define PROMOTE_PROTOTYPES | |
2505 | ||
d969caf8 RK |
2506 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
2507 | few bits. */ | |
2508 | #define SHIFT_COUNT_TRUNCATED 1 | |
1bb87f28 JW |
2509 | |
2510 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
2511 | is done just by pretending it is already truncated. */ | |
2512 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2513 | ||
2514 | /* Specify the machine mode that pointers have. | |
2515 | After generation of rtl, the compiler makes no further distinction | |
2516 | between pointers and any other objects of this machine mode. */ | |
7a6cf439 | 2517 | #define Pmode (TARGET_PTR64 ? DImode : SImode) |
1bb87f28 | 2518 | |
b4ac57ab RS |
2519 | /* Generate calls to memcpy, memcmp and memset. */ |
2520 | #define TARGET_MEM_FUNCTIONS | |
2521 | ||
1bb87f28 JW |
2522 | /* Add any extra modes needed to represent the condition code. |
2523 | ||
2524 | On the Sparc, we have a "no-overflow" mode which is used when an add or | |
2525 | subtract insn is used to set the condition code. Different branches are | |
2526 | used in this case for some operations. | |
2527 | ||
4d449554 JW |
2528 | We also have two modes to indicate that the relevant condition code is |
2529 | in the floating-point condition code register. One for comparisons which | |
2530 | will generate an exception if the result is unordered (CCFPEmode) and | |
2531 | one for comparisons which will never trap (CCFPmode). This really should | |
7a6cf439 DE |
2532 | be a separate register, but we don't want to go to 65 registers. |
2533 | ||
2534 | CCXmode and CCX_NOOVmode are only used by v9. */ | |
2535 | ||
2536 | #define EXTRA_CC_MODES CCXmode, CC_NOOVmode, CCX_NOOVmode, CCFPmode, CCFPEmode | |
1bb87f28 JW |
2537 | |
2538 | /* Define the names for the modes specified above. */ | |
7a6cf439 DE |
2539 | |
2540 | #define EXTRA_CC_NAMES "CCX", "CC_NOOV", "CCX_NOOV", "CCFP", "CCFPE" | |
1bb87f28 JW |
2541 | |
2542 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
4d449554 JW |
2543 | return the mode to be used for the comparison. For floating-point, |
2544 | CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a | |
922bd191 JW |
2545 | PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special |
2546 | processing is needed. */ | |
679655e6 | 2547 | #define SELECT_CC_MODE(OP,X,Y) \ |
4d449554 | 2548 | (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ |
922bd191 JW |
2549 | ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ |
2550 | : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ | |
2551 | || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \ | |
6f64bf5f DE |
2552 | ? (TARGET_ARCH64 && GET_MODE (X) == DImode ? CCX_NOOVmode : CC_NOOVmode) \ |
2553 | : (TARGET_ARCH64 && GET_MODE (X) == DImode ? CCXmode : CCmode))) | |
1bb87f28 | 2554 | |
b331b745 RK |
2555 | /* Return non-zero if SELECT_CC_MODE will never return MODE for a |
2556 | floating point inequality comparison. */ | |
2557 | ||
2558 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) | |
2559 | ||
1bb87f28 JW |
2560 | /* A function address in a call instruction |
2561 | is a byte address (for indexing purposes) | |
2562 | so give the MEM rtx a byte's mode. */ | |
2563 | #define FUNCTION_MODE SImode | |
2564 | ||
2565 | /* Define this if addresses of constant functions | |
2566 | shouldn't be put through pseudo regs where they can be cse'd. | |
2567 | Desirable on machines where ordinary constants are expensive | |
2568 | but a CALL with constant address is cheap. */ | |
2569 | #define NO_FUNCTION_CSE | |
2570 | ||
2571 | /* alloca should avoid clobbering the old register save area. */ | |
2572 | #define SETJMP_VIA_SAVE_AREA | |
2573 | ||
2574 | /* Define subroutines to call to handle multiply and divide. | |
2575 | Use the subroutines that Sun's library provides. | |
2576 | The `*' prevents an underscore from being prepended by the compiler. */ | |
2577 | ||
2578 | #define DIVSI3_LIBCALL "*.div" | |
2579 | #define UDIVSI3_LIBCALL "*.udiv" | |
2580 | #define MODSI3_LIBCALL "*.rem" | |
2581 | #define UMODSI3_LIBCALL "*.urem" | |
2582 | /* .umul is a little faster than .mul. */ | |
2583 | #define MULSI3_LIBCALL "*.umul" | |
2584 | ||
8248e2bc JW |
2585 | /* Define library calls for quad FP operations. These are all part of the |
2586 | SPARC ABI. */ | |
b3f741ed JW |
2587 | #define ADDTF3_LIBCALL "_Q_add" |
2588 | #define SUBTF3_LIBCALL "_Q_sub" | |
27da6752 | 2589 | #define NEGTF2_LIBCALL "_Q_neg" |
b3f741ed JW |
2590 | #define MULTF3_LIBCALL "_Q_mul" |
2591 | #define DIVTF3_LIBCALL "_Q_div" | |
b3f741ed JW |
2592 | #define FLOATSITF2_LIBCALL "_Q_itoq" |
2593 | #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi" | |
2594 | #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou" | |
2595 | #define EXTENDSFTF2_LIBCALL "_Q_stoq" | |
2596 | #define TRUNCTFSF2_LIBCALL "_Q_qtos" | |
2597 | #define EXTENDDFTF2_LIBCALL "_Q_dtoq" | |
2598 | #define TRUNCTFDF2_LIBCALL "_Q_qtod" | |
2599 | #define EQTF2_LIBCALL "_Q_feq" | |
2600 | #define NETF2_LIBCALL "_Q_fne" | |
2601 | #define GTTF2_LIBCALL "_Q_fgt" | |
2602 | #define GETF2_LIBCALL "_Q_fge" | |
2603 | #define LTTF2_LIBCALL "_Q_flt" | |
2604 | #define LETF2_LIBCALL "_Q_fle" | |
8248e2bc | 2605 | |
78e9b5df JW |
2606 | /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because |
2607 | with soft-float, the SFmode and DFmode sqrt instructions will be absent, | |
2608 | and the compiler will notice and try to use the TFmode sqrt instruction | |
2609 | for calls to the builtin function sqrt, but this fails. */ | |
27da6752 JW |
2610 | #define INIT_TARGET_OPTABS \ |
2611 | do { \ | |
27da6752 JW |
2612 | add_optab->handlers[(int) TFmode].libfunc \ |
2613 | = gen_rtx (SYMBOL_REF, Pmode, ADDTF3_LIBCALL); \ | |
2614 | sub_optab->handlers[(int) TFmode].libfunc \ | |
2615 | = gen_rtx (SYMBOL_REF, Pmode, SUBTF3_LIBCALL); \ | |
2616 | neg_optab->handlers[(int) TFmode].libfunc \ | |
2617 | = gen_rtx (SYMBOL_REF, Pmode, NEGTF2_LIBCALL); \ | |
2618 | smul_optab->handlers[(int) TFmode].libfunc \ | |
2619 | = gen_rtx (SYMBOL_REF, Pmode, MULTF3_LIBCALL); \ | |
2620 | flodiv_optab->handlers[(int) TFmode].libfunc \ | |
2621 | = gen_rtx (SYMBOL_REF, Pmode, DIVTF3_LIBCALL); \ | |
2622 | eqtf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EQTF2_LIBCALL); \ | |
2623 | netf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, NETF2_LIBCALL); \ | |
2624 | gttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GTTF2_LIBCALL); \ | |
2625 | getf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GETF2_LIBCALL); \ | |
2626 | lttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LTTF2_LIBCALL); \ | |
2627 | letf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LETF2_LIBCALL); \ | |
2628 | trunctfsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFSF2_LIBCALL); \ | |
2629 | trunctfdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFDF2_LIBCALL); \ | |
2630 | extendsftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDSFTF2_LIBCALL); \ | |
2631 | extenddftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDDFTF2_LIBCALL); \ | |
2632 | floatsitf_libfunc = gen_rtx (SYMBOL_REF, Pmode, FLOATSITF2_LIBCALL); \ | |
2633 | fixtfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, FIX_TRUNCTFSI2_LIBCALL); \ | |
2634 | fixunstfsi_libfunc \ | |
2635 | = gen_rtx (SYMBOL_REF, Pmode, FIXUNS_TRUNCTFSI2_LIBCALL); \ | |
2636 | if (TARGET_FPU) \ | |
2637 | sqrt_optab->handlers[(int) TFmode].libfunc \ | |
2638 | = gen_rtx (SYMBOL_REF, Pmode, "_Q_sqrt"); \ | |
47428190 | 2639 | INIT_SUBTARGET_OPTABS; \ |
78e9b5df JW |
2640 | } while (0) |
2641 | ||
2642 | /* This is meant to be redefined in the host dependent files */ | |
2643 | #define INIT_SUBTARGET_OPTABS | |
2644 | ||
1bb87f28 JW |
2645 | /* Compute the cost of computing a constant rtl expression RTX |
2646 | whose rtx-code is CODE. The body of this macro is a portion | |
2647 | of a switch statement. If the code is computed here, | |
2648 | return it with a return statement. Otherwise, break from the switch. */ | |
2649 | ||
3bb22aee | 2650 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ |
1bb87f28 | 2651 | case CONST_INT: \ |
1bb87f28 | 2652 | if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \ |
5b485d2c | 2653 | return 0; \ |
1bb87f28 JW |
2654 | case HIGH: \ |
2655 | return 2; \ | |
2656 | case CONST: \ | |
2657 | case LABEL_REF: \ | |
2658 | case SYMBOL_REF: \ | |
2659 | return 4; \ | |
2660 | case CONST_DOUBLE: \ | |
2661 | if (GET_MODE (RTX) == DImode) \ | |
2662 | if ((XINT (RTX, 3) == 0 \ | |
2663 | && (unsigned) XINT (RTX, 2) < 0x1000) \ | |
2664 | || (XINT (RTX, 3) == -1 \ | |
2665 | && XINT (RTX, 2) < 0 \ | |
2666 | && XINT (RTX, 2) >= -0x1000)) \ | |
5b485d2c | 2667 | return 0; \ |
1bb87f28 JW |
2668 | return 8; |
2669 | ||
a0a74fda | 2670 | /* Compute the cost of an address. For the sparc, all valid addresses are |
7a6cf439 DE |
2671 | the same cost. |
2672 | ??? Is this true for v9? */ | |
1bb87f28 | 2673 | |
a0a74fda | 2674 | #define ADDRESS_COST(RTX) 1 |
1bb87f28 JW |
2675 | |
2676 | /* Compute extra cost of moving data between one register class | |
7a6cf439 DE |
2677 | and another. |
2678 | ??? v9: We ignore FPCC_REGS on the assumption they'll never be seen. */ | |
1bb87f28 | 2679 | #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ |
24b63396 JW |
2680 | (((FP_REG_CLASS_P (CLASS1) && (CLASS2) == GENERAL_REGS) \ |
2681 | || ((CLASS1) == GENERAL_REGS && FP_REG_CLASS_P (CLASS2))) ? 6 : 2) | |
1bb87f28 JW |
2682 | |
2683 | /* Provide the costs of a rtl expression. This is in the body of a | |
2684 | switch on CODE. The purpose for the cost of MULT is to encourage | |
2685 | `synth_mult' to find a synthetic multiply when reasonable. | |
2686 | ||
2687 | If we need more than 12 insns to do a multiply, then go out-of-line, | |
2688 | since the call overhead will be < 10% of the cost of the multiply. */ | |
2689 | ||
3bb22aee | 2690 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
1bb87f28 | 2691 | case MULT: \ |
6f64bf5f DE |
2692 | return (TARGET_V8 || TARGET_SPARCLITE || TARGET_V9) \ |
2693 | ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \ | |
1bb87f28 JW |
2694 | case DIV: \ |
2695 | case UDIV: \ | |
2696 | case MOD: \ | |
2697 | case UMOD: \ | |
5b485d2c JW |
2698 | return COSTS_N_INSNS (25); \ |
2699 | /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\ | |
1bb87f28 JW |
2700 | so that cse will favor the latter. */ \ |
2701 | case FLOAT: \ | |
5b485d2c | 2702 | case FIX: \ |
1bb87f28 JW |
2703 | return 19; |
2704 | ||
bef8d8c7 JW |
2705 | /* Adjust the cost of dependencies. */ |
2706 | #define ADJUST_COST(INSN,LINK,DEP,COST) \ | |
bafb031b DE |
2707 | if (sparc_cpu == CPU_SUPERSPARC) \ |
2708 | (COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST) | |
bef8d8c7 | 2709 | |
1bb87f28 JW |
2710 | /* Conditional branches with empty delay slots have a length of two. */ |
2711 | #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ | |
2712 | if (GET_CODE (INSN) == CALL_INSN \ | |
2713 | || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \ | |
2714 | LENGTH += 1; | |
2715 | \f | |
2716 | /* Control the assembler format that we output. */ | |
2717 | ||
2718 | /* Output at beginning of assembler file. */ | |
2719 | ||
2720 | #define ASM_FILE_START(file) | |
2721 | ||
2722 | /* Output to assembler file text saying following lines | |
2723 | may contain character constants, extra white space, comments, etc. */ | |
2724 | ||
2725 | #define ASM_APP_ON "" | |
2726 | ||
2727 | /* Output to assembler file text saying following lines | |
2728 | no longer contain unusual constructs. */ | |
2729 | ||
2730 | #define ASM_APP_OFF "" | |
2731 | ||
7a6cf439 DE |
2732 | /* ??? Try to make the style consistent here (_OP?). */ |
2733 | ||
2734 | #define ASM_LONGLONG ".xword" | |
303d524a JW |
2735 | #define ASM_LONG ".word" |
2736 | #define ASM_SHORT ".half" | |
2737 | #define ASM_BYTE_OP ".byte" | |
7a6cf439 DE |
2738 | #define ASM_FLOAT ".single" |
2739 | #define ASM_DOUBLE ".double" | |
2740 | #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */ | |
303d524a | 2741 | |
1bb87f28 JW |
2742 | /* Output before read-only data. */ |
2743 | ||
2744 | #define TEXT_SECTION_ASM_OP ".text" | |
2745 | ||
2746 | /* Output before writable data. */ | |
2747 | ||
2748 | #define DATA_SECTION_ASM_OP ".data" | |
2749 | ||
2750 | /* How to refer to registers in assembler output. | |
2751 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2752 | ||
7a6cf439 DE |
2753 | #define REGISTER_NAMES \ |
2754 | {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ | |
2755 | "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ | |
2756 | "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ | |
2757 | "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ | |
2758 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ | |
2759 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ | |
2760 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ | |
2761 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ | |
6f64bf5f DE |
2762 | SPARC64_REGISTER_NAMES \ |
2763 | } | |
2764 | ||
2765 | #if SPARC_V9 | |
2766 | #define SPARC64_REGISTER_NAMES \ | |
7a6cf439 DE |
2767 | "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ |
2768 | "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ | |
2769 | "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ | |
2770 | "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ | |
6f64bf5f | 2771 | "%fcc0", "%fcc1", "%fcc2", "%fcc3" |
7a6cf439 | 2772 | #else |
6f64bf5f | 2773 | #define SPARC64_REGISTER_NAMES |
7a6cf439 | 2774 | #endif |
1bb87f28 | 2775 | |
ea3fa5f7 JW |
2776 | /* Define additional names for use in asm clobbers and asm declarations. |
2777 | ||
2778 | We define the fake Condition Code register as an alias for reg 0 (which | |
2779 | is our `condition code' register), so that condition codes can easily | |
2780 | be clobbered by an asm. No such register actually exists. Condition | |
2781 | codes are partly stored in the PSR and partly in the FSR. */ | |
2782 | ||
0eb9f40e | 2783 | #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0} |
ea3fa5f7 | 2784 | |
1bb87f28 JW |
2785 | /* How to renumber registers for dbx and gdb. */ |
2786 | ||
2787 | #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
2788 | ||
2789 | /* On Sun 4, this limit is 2048. We use 1500 to be safe, | |
2790 | since the length can run past this up to a continuation point. */ | |
2791 | #define DBX_CONTIN_LENGTH 1500 | |
2792 | ||
2793 | /* This is how to output a note to DBX telling it the line number | |
2794 | to which the following sequence of instructions corresponds. | |
2795 | ||
2796 | This is needed for SunOS 4.0, and should not hurt for 3.2 | |
2797 | versions either. */ | |
2798 | #define ASM_OUTPUT_SOURCE_LINE(file, line) \ | |
2799 | { static int sym_lineno = 1; \ | |
2800 | fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \ | |
2801 | line, sym_lineno, sym_lineno); \ | |
2802 | sym_lineno += 1; } | |
2803 | ||
2804 | /* This is how to output the definition of a user-level label named NAME, | |
2805 | such as the label on a static function or variable NAME. */ | |
2806 | ||
2807 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
2808 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
2809 | ||
2810 | /* This is how to output a command to make the user-level label named NAME | |
2811 | defined for reference from other files. */ | |
2812 | ||
2813 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ | |
2814 | do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) | |
2815 | ||
2816 | /* This is how to output a reference to a user-level label named NAME. | |
2817 | `assemble_name' uses this. */ | |
2818 | ||
2819 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
2820 | fprintf (FILE, "_%s", NAME) | |
2821 | ||
d2a8e680 | 2822 | /* This is how to output a definition of an internal numbered label where |
1bb87f28 JW |
2823 | PREFIX is the class of label and NUM is the number within the class. */ |
2824 | ||
2825 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
2826 | fprintf (FILE, "%s%d:\n", PREFIX, NUM) | |
2827 | ||
d2a8e680 RS |
2828 | /* This is how to output a reference to an internal numbered label where |
2829 | PREFIX is the class of label and NUM is the number within the class. */ | |
2830 | /* FIXME: This should be used throughout gcc, and documented in the texinfo | |
2831 | files. There is no reason you should have to allocate a buffer and | |
2832 | `sprintf' to reference an internal label (as opposed to defining it). */ | |
2833 | ||
2834 | #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \ | |
2835 | fprintf (FILE, "%s%d", PREFIX, NUM) | |
2836 | ||
1bb87f28 JW |
2837 | /* This is how to store into the string LABEL |
2838 | the symbol_ref name of an internal numbered label where | |
2839 | PREFIX is the class of label and NUM is the number within the class. | |
2840 | This is suitable for output with `assemble_name'. */ | |
2841 | ||
2842 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
2843 | sprintf (LABEL, "*%s%d", PREFIX, NUM) | |
2844 | ||
2845 | /* This is how to output an assembler line defining a `double' constant. */ | |
2846 | ||
2847 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ | |
2848 | { \ | |
2e7ac77c JW |
2849 | long t[2]; \ |
2850 | REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ | |
2851 | fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \ | |
2852 | ASM_LONG, t[0], ASM_LONG, t[1]); \ | |
1bb87f28 JW |
2853 | } |
2854 | ||
2855 | /* This is how to output an assembler line defining a `float' constant. */ | |
2856 | ||
2857 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ | |
2858 | { \ | |
2e7ac77c JW |
2859 | long t; \ |
2860 | REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ | |
2861 | fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \ | |
2862 | } \ | |
1bb87f28 | 2863 | |
0cd02cbb DE |
2864 | /* This is how to output an assembler line defining a `long double' |
2865 | constant. */ | |
2866 | ||
2867 | #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ | |
2868 | { \ | |
2869 | long t[4]; \ | |
2870 | REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \ | |
2871 | fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \ | |
2872 | ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \ | |
2873 | } | |
2874 | ||
1bb87f28 JW |
2875 | /* This is how to output an assembler line defining an `int' constant. */ |
2876 | ||
2877 | #define ASM_OUTPUT_INT(FILE,VALUE) \ | |
303d524a | 2878 | ( fprintf (FILE, "\t%s\t", ASM_LONG), \ |
1bb87f28 JW |
2879 | output_addr_const (FILE, (VALUE)), \ |
2880 | fprintf (FILE, "\n")) | |
2881 | ||
2882 | /* This is how to output an assembler line defining a DImode constant. */ | |
2883 | #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ | |
2884 | output_double_int (FILE, VALUE) | |
2885 | ||
2886 | /* Likewise for `char' and `short' constants. */ | |
2887 | ||
2888 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
303d524a | 2889 | ( fprintf (FILE, "\t%s\t", ASM_SHORT), \ |
1bb87f28 JW |
2890 | output_addr_const (FILE, (VALUE)), \ |
2891 | fprintf (FILE, "\n")) | |
2892 | ||
2893 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ | |
303d524a | 2894 | ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \ |
1bb87f28 JW |
2895 | output_addr_const (FILE, (VALUE)), \ |
2896 | fprintf (FILE, "\n")) | |
2897 | ||
2898 | /* This is how to output an assembler line for a numeric constant byte. */ | |
2899 | ||
2900 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ | |
303d524a | 2901 | fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE)) |
1bb87f28 JW |
2902 | |
2903 | /* This is how to output an element of a case-vector that is absolute. */ | |
2904 | ||
2905 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
4b69d2a3 RS |
2906 | do { \ |
2907 | char label[30]; \ | |
2908 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
7a6cf439 DE |
2909 | if (Pmode == SImode) \ |
2910 | fprintf (FILE, "\t.word\t"); \ | |
6f64bf5f | 2911 | else if (TARGET_MEDLOW) \ |
7a6cf439 DE |
2912 | fprintf (FILE, "\t.word\t0\n\t.word\t"); \ |
2913 | else \ | |
2914 | fprintf (FILE, "\t.xword\t"); \ | |
4b69d2a3 RS |
2915 | assemble_name (FILE, label); \ |
2916 | fprintf (FILE, "\n"); \ | |
2917 | } while (0) | |
1bb87f28 JW |
2918 | |
2919 | /* This is how to output an element of a case-vector that is relative. | |
2920 | (SPARC uses such vectors only when generating PIC.) */ | |
2921 | ||
4b69d2a3 RS |
2922 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ |
2923 | do { \ | |
2924 | char label[30]; \ | |
2925 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
7a6cf439 DE |
2926 | if (Pmode == SImode) \ |
2927 | fprintf (FILE, "\t.word\t"); \ | |
6f64bf5f | 2928 | else if (TARGET_MEDLOW) \ |
7a6cf439 DE |
2929 | fprintf (FILE, "\t.word\t0\n\t.word\t"); \ |
2930 | else \ | |
2931 | fprintf (FILE, "\t.xword\t"); \ | |
4b69d2a3 RS |
2932 | assemble_name (FILE, label); \ |
2933 | fprintf (FILE, "-1b\n"); \ | |
2934 | } while (0) | |
1bb87f28 JW |
2935 | |
2936 | /* This is how to output an assembler line | |
2937 | that says to advance the location counter | |
2938 | to a multiple of 2**LOG bytes. */ | |
2939 | ||
2940 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2941 | if ((LOG) != 0) \ | |
2942 | fprintf (FILE, "\t.align %d\n", (1<<(LOG))) | |
2943 | ||
2944 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
2945 | fprintf (FILE, "\t.skip %u\n", (SIZE)) | |
2946 | ||
2947 | /* This says how to output an assembler line | |
2948 | to define a global common symbol. */ | |
2949 | ||
2950 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
b277ceaf | 2951 | ( fputs ("\t.common ", (FILE)), \ |
1bb87f28 | 2952 | assemble_name ((FILE), (NAME)), \ |
b277ceaf | 2953 | fprintf ((FILE), ",%u,\"bss\"\n", (SIZE))) |
1bb87f28 | 2954 | |
b277ceaf JW |
2955 | /* This says how to output an assembler line to define a local common |
2956 | symbol. */ | |
1bb87f28 | 2957 | |
b277ceaf JW |
2958 | #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ |
2959 | ( fputs ("\t.reserve ", (FILE)), \ | |
2960 | assemble_name ((FILE), (NAME)), \ | |
2961 | fprintf ((FILE), ",%u,\"bss\",%u\n", \ | |
2962 | (SIZE), ((ALIGNED) / BITS_PER_UNIT))) | |
1bb87f28 JW |
2963 | |
2964 | /* Store in OUTPUT a string (made with alloca) containing | |
2965 | an assembler-name for a local static variable named NAME. | |
2966 | LABELNO is an integer which is different for each call. */ | |
2967 | ||
2968 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
2969 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
2970 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
2971 | ||
c14f2655 RS |
2972 | #define IDENT_ASM_OP ".ident" |
2973 | ||
2974 | /* Output #ident as a .ident. */ | |
2975 | ||
2976 | #define ASM_OUTPUT_IDENT(FILE, NAME) \ | |
2977 | fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME); | |
2978 | ||
1bb87f28 JW |
2979 | /* Define the parentheses used to group arithmetic operations |
2980 | in assembler code. */ | |
2981 | ||
2982 | #define ASM_OPEN_PAREN "(" | |
2983 | #define ASM_CLOSE_PAREN ")" | |
2984 | ||
2985 | /* Define results of standard character escape sequences. */ | |
2986 | #define TARGET_BELL 007 | |
2987 | #define TARGET_BS 010 | |
2988 | #define TARGET_TAB 011 | |
2989 | #define TARGET_NEWLINE 012 | |
2990 | #define TARGET_VT 013 | |
2991 | #define TARGET_FF 014 | |
2992 | #define TARGET_CR 015 | |
2993 | ||
2994 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
2ccdef65 | 2995 | ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(') |
1bb87f28 JW |
2996 | |
2997 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
2998 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2999 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
3000 | ||
3001 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
3002 | ||
3003 | /* Print a memory address as an operand to reference that memory location. */ | |
3004 | ||
3005 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
3006 | { register rtx base, index = 0; \ | |
3007 | int offset = 0; \ | |
3008 | register rtx addr = ADDR; \ | |
3009 | if (GET_CODE (addr) == REG) \ | |
3010 | fputs (reg_names[REGNO (addr)], FILE); \ | |
3011 | else if (GET_CODE (addr) == PLUS) \ | |
3012 | { \ | |
3013 | if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ | |
3014 | offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ | |
3015 | else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ | |
3016 | offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ | |
3017 | else \ | |
3018 | base = XEXP (addr, 0), index = XEXP (addr, 1); \ | |
3019 | fputs (reg_names[REGNO (base)], FILE); \ | |
3020 | if (index == 0) \ | |
3021 | fprintf (FILE, "%+d", offset); \ | |
3022 | else if (GET_CODE (index) == REG) \ | |
3023 | fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ | |
72d3b324 RK |
3024 | else if (GET_CODE (index) == SYMBOL_REF \ |
3025 | || GET_CODE (index) == CONST) \ | |
1bb87f28 JW |
3026 | fputc ('+', FILE), output_addr_const (FILE, index); \ |
3027 | else abort (); \ | |
3028 | } \ | |
3029 | else if (GET_CODE (addr) == MINUS \ | |
3030 | && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ | |
3031 | { \ | |
3032 | output_addr_const (FILE, XEXP (addr, 0)); \ | |
3033 | fputs ("-(", FILE); \ | |
3034 | output_addr_const (FILE, XEXP (addr, 1)); \ | |
3035 | fputs ("-.)", FILE); \ | |
3036 | } \ | |
3037 | else if (GET_CODE (addr) == LO_SUM) \ | |
3038 | { \ | |
3039 | output_operand (XEXP (addr, 0), 0); \ | |
3040 | fputs ("+%lo(", FILE); \ | |
3041 | output_address (XEXP (addr, 1)); \ | |
3042 | fputc (')', FILE); \ | |
3043 | } \ | |
3044 | else if (flag_pic && GET_CODE (addr) == CONST \ | |
3045 | && GET_CODE (XEXP (addr, 0)) == MINUS \ | |
3046 | && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ | |
3047 | && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ | |
3048 | && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ | |
3049 | { \ | |
3050 | addr = XEXP (addr, 0); \ | |
3051 | output_addr_const (FILE, XEXP (addr, 0)); \ | |
3052 | /* Group the args of the second CONST in parenthesis. */ \ | |
3053 | fputs ("-(", FILE); \ | |
3054 | /* Skip past the second CONST--it does nothing for us. */\ | |
3055 | output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ | |
3056 | /* Close the parenthesis. */ \ | |
3057 | fputc (')', FILE); \ | |
3058 | } \ | |
3059 | else \ | |
3060 | { \ | |
3061 | output_addr_const (FILE, addr); \ | |
3062 | } \ | |
3063 | } | |
3064 | ||
3065 | /* Declare functions defined in sparc.c and used in templates. */ | |
3066 | ||
3067 | extern char *singlemove_string (); | |
3068 | extern char *output_move_double (); | |
795068a4 | 3069 | extern char *output_move_quad (); |
1bb87f28 | 3070 | extern char *output_fp_move_double (); |
795068a4 | 3071 | extern char *output_fp_move_quad (); |
1bb87f28 JW |
3072 | extern char *output_block_move (); |
3073 | extern char *output_scc_insn (); | |
3074 | extern char *output_cbranch (); | |
7a6cf439 | 3075 | extern char *output_v9branch (); |
1bb87f28 | 3076 | extern char *output_return (); |
1bb87f28 JW |
3077 | |
3078 | /* Defined in flags.h, but insn-emit.c does not include flags.h. */ | |
3079 | ||
3080 | extern int flag_pic; |