]>
Commit | Line | Data |
---|---|---|
1bb87f28 | 1 | /* Definitions of target machine for GNU compiler, for Sun SPARC. |
b73bf65f | 2 | Copyright (C) 1987, 88, 89, 92, 94-98, 1999 Free Software Foundation, Inc. |
1bb87f28 | 3 | Contributed by Michael Tiemann (tiemann@cygnus.com). |
7a6cf439 DE |
4 | 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
5 | at Cygnus Support. | |
1bb87f28 JW |
6 | |
7 | This file is part of GNU CC. | |
8 | ||
9 | GNU CC is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GNU CC is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
21 | the Free Software Foundation, 59 Temple Place - Suite 330, |
22 | Boston, MA 02111-1307, USA. */ | |
1bb87f28 JW |
23 | |
24 | /* Note that some other tm.h files include this one and then override | |
a0a301fc DE |
25 | whatever definitions are necessary. */ |
26 | ||
27 | /* Specify this in a cover file to provide bi-architecture (32/64) support. */ | |
28 | /* #define SPARC_BI_ARCH */ | |
29 | ||
30 | /* Macro used later in this file to determine default architecture. */ | |
31 | #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) | |
7a6cf439 | 32 | |
a0a301fc DE |
33 | /* TARGET_ARCH{32,64} are the main macros to decide which of the two |
34 | architectures to compile for. We allow targets to choose compile time or | |
35 | runtime selection. */ | |
36 | #ifdef SPARC_BI_ARCH | |
959eb758 DM |
37 | #ifdef IN_LIBGCC2 |
38 | #if defined(__sparcv9) || defined(__sparcv_v9) || defined(__arch64__) | |
39 | #define TARGET_ARCH32 0 | |
40 | #else | |
41 | #define TARGET_ARCH32 1 | |
42 | #endif /* V9 sparc */ | |
43 | #else | |
a0a301fc | 44 | #define TARGET_ARCH32 (! TARGET_64BIT) |
959eb758 | 45 | #endif /* IN_LIBGCC2 */ |
a0a301fc DE |
46 | #else |
47 | #define TARGET_ARCH32 (DEFAULT_ARCH32_P) | |
959eb758 | 48 | #endif /* SPARC_BI_ARCH */ |
a0a301fc DE |
49 | #define TARGET_ARCH64 (! TARGET_ARCH32) |
50 | ||
51 | /* Code model selection. | |
52 | -mcmodel is used to select the v9 code model. | |
5cb01b65 | 53 | Different code models aren't supported for v7/8 code. |
a0a301fc DE |
54 | |
55 | TARGET_CM_32: 32 bit address space, top 32 bits = 0, | |
56 | pointers are 32 bits. Note that this isn't intended | |
5cb01b65 | 57 | to imply a v7/8 abi. |
a0a301fc DE |
58 | |
59 | TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0, | |
60 | avoid generating %uhi and %ulo terms, | |
61 | pointers are 64 bits. | |
62 | ||
63 | TARGET_CM_MEDMID: 64 bit address space. | |
64 | The executable must be in the low 16 TB of memory. | |
65 | This corresponds to the low 44 bits, and the %[hml]44 | |
67cb8900 JJ |
66 | relocs are used. The text segment has a maximum size |
67 | of 31 bits. | |
a0a301fc DE |
68 | |
69 | TARGET_CM_MEDANY: 64 bit address space. | |
70 | The text and data segments have a maximum size of 31 | |
71 | bits and may be located anywhere. The maximum offset | |
72 | from any instruction to the label _GLOBAL_OFFSET_TABLE_ | |
73 | is 31 bits. | |
74 | ||
75 | TARGET_CM_EMBMEDANY: 64 bit address space. | |
76 | The text and data segments have a maximum size of 31 bits | |
77 | and may be located anywhere. Register %g4 contains | |
78 | the start address of the data segment. | |
79 | */ | |
80 | ||
81 | enum cmodel { | |
82 | CM_32, | |
83 | CM_MEDLOW, | |
84 | CM_MEDMID, | |
85 | CM_MEDANY, | |
86 | CM_EMBMEDANY | |
87 | }; | |
88 | ||
89 | /* Value of -mcmodel specified by user. */ | |
3bb5de61 | 90 | extern const char *sparc_cmodel_string; |
a0a301fc DE |
91 | /* One of CM_FOO. */ |
92 | extern enum cmodel sparc_cmodel; | |
93 | ||
94 | /* V9 code model selection. */ | |
95 | #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) | |
96 | #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) | |
97 | #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) | |
98 | #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) | |
99 | ||
a0a301fc | 100 | #define SPARC_DEFAULT_CMODEL CM_MEDLOW |
6f64bf5f | 101 | |
a0a301fc DE |
102 | /* This is call-clobbered in the normal ABI, but is reserved in the |
103 | home grown (aka upward compatible) embedded ABI. */ | |
104 | #define EMBMEDANY_BASE_REG "%g4" | |
105 | \f | |
106 | /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, | |
107 | and specified by the user via --with-cpu=foo. | |
108 | This specifies the cpu implementation, not the architecture size. */ | |
8947065c RH |
109 | /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit |
110 | capable cpu's. */ | |
2163f11b RK |
111 | #define TARGET_CPU_sparc 0 |
112 | #define TARGET_CPU_v7 0 /* alias for previous */ | |
113 | #define TARGET_CPU_sparclet 1 | |
114 | #define TARGET_CPU_sparclite 2 | |
a0a301fc | 115 | #define TARGET_CPU_v8 3 /* generic v8 implementation */ |
2163f11b | 116 | #define TARGET_CPU_supersparc 4 |
8947065c | 117 | #define TARGET_CPU_hypersparc 5 |
809934df | 118 | #define TARGET_CPU_sparc86x 6 |
8947065c RH |
119 | #define TARGET_CPU_sparclite86x 6 |
120 | #define TARGET_CPU_v9 7 /* generic v9 implementation */ | |
121 | #define TARGET_CPU_sparcv9 7 /* alias */ | |
122 | #define TARGET_CPU_sparc64 7 /* alias */ | |
123 | #define TARGET_CPU_ultrasparc 8 | |
bafb031b | 124 | |
8947065c RH |
125 | #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ |
126 | || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc | |
345a6161 DM |
127 | |
128 | #define CPP_CPU32_DEFAULT_SPEC "" | |
129 | #define ASM_CPU32_DEFAULT_SPEC "" | |
130 | ||
a0a301fc | 131 | #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 |
bafb031b | 132 | /* ??? What does Sun's CC pass? */ |
345a6161 | 133 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" |
bafb031b DE |
134 | /* ??? It's not clear how other assemblers will handle this, so by default |
135 | use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case | |
136 | is handled in sol2.h. */ | |
345a6161 | 137 | #define ASM_CPU64_DEFAULT_SPEC "-Av9" |
bafb031b | 138 | #endif |
a0a301fc | 139 | #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc |
345a6161 DM |
140 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" |
141 | #define ASM_CPU64_DEFAULT_SPEC "-Av9a" | |
142 | #endif | |
143 | ||
144 | #else | |
145 | ||
146 | #define CPP_CPU64_DEFAULT_SPEC "" | |
147 | #define ASM_CPU64_DEFAULT_SPEC "" | |
148 | ||
8947065c RH |
149 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ |
150 | || TARGET_CPU_DEFAULT == TARGET_CPU_v8 | |
345a6161 DM |
151 | #define CPP_CPU32_DEFAULT_SPEC "" |
152 | #define ASM_CPU32_DEFAULT_SPEC "" | |
153 | #endif | |
8947065c | 154 | |
345a6161 DM |
155 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet |
156 | #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" | |
157 | #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" | |
bafb031b | 158 | #endif |
8947065c | 159 | |
345a6161 DM |
160 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite |
161 | #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" | |
162 | #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" | |
163 | #endif | |
164 | ||
8947065c RH |
165 | #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc |
166 | #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" | |
167 | #define ASM_CPU32_DEFAULT_SPEC "" | |
168 | #endif | |
169 | ||
170 | #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc | |
171 | #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" | |
172 | #define ASM_CPU32_DEFAULT_SPEC "" | |
173 | #endif | |
174 | ||
175 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x | |
8d72ec32 VM |
176 | #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" |
177 | #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" | |
8947065c RH |
178 | #endif |
179 | ||
345a6161 DM |
180 | #endif |
181 | ||
182 | #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) | |
a0a301fc | 183 | Unrecognized value in TARGET_CPU_DEFAULT. |
bafb031b DE |
184 | #endif |
185 | ||
345a6161 DM |
186 | #ifdef SPARC_BI_ARCH |
187 | ||
188 | #define CPP_CPU_DEFAULT_SPEC \ | |
189 | (DEFAULT_ARCH32_P ? "\ | |
190 | %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ | |
191 | %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ | |
192 | " : "\ | |
193 | %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ | |
194 | %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ | |
195 | ") | |
196 | #define ASM_CPU_DEFAULT_SPEC \ | |
197 | (DEFAULT_ARCH32_P ? "\ | |
198 | %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ | |
199 | %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ | |
200 | " : "\ | |
201 | %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ | |
202 | %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ | |
203 | ") | |
204 | ||
205 | #else /* !SPARC_BI_ARCH */ | |
206 | ||
207 | #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) | |
208 | #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) | |
209 | ||
210 | #endif /* !SPARC_BI_ARCH */ | |
211 | ||
a0a301fc DE |
212 | /* Names to predefine in the preprocessor for this target machine. |
213 | ??? It would be nice to not include any subtarget specific values here, | |
214 | however there's no way to portably provide subtarget values to | |
215 | CPP_PREFINES. Also, -D values in CPP_SUBTARGET_SPEC don't get turned into | |
38e01259 | 216 | foo, __foo and __foo__. */ |
7a6cf439 | 217 | |
a0a301fc | 218 | #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix -Asystem(unix) -Asystem(bsd)" |
7a6cf439 | 219 | |
885d8175 | 220 | /* Define macros to distinguish architectures. */ |
857458c4 | 221 | |
bafb031b DE |
222 | /* Common CPP definitions used by CPP_SPEC amongst the various targets |
223 | for handling -mcpu=xxx switches. */ | |
224 | #define CPP_CPU_SPEC "\ | |
225 | %{mcypress:} \ | |
7a6cf439 DE |
226 | %{msparclite:-D__sparclite__} \ |
227 | %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ | |
228 | %{mv8:-D__sparc_v8__} \ | |
bafb031b | 229 | %{msupersparc:-D__supersparc__ -D__sparc_v8__} \ |
9b7c06d2 | 230 | %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ |
bafb031b DE |
231 | %{mcpu=sparclite:-D__sparclite__} \ |
232 | %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ | |
233 | %{mcpu=v8:-D__sparc_v8__} \ | |
234 | %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ | |
8947065c | 235 | %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ |
8d72ec32 | 236 | %{mcpu=sparclite86x:-D__sparclite86x__} \ |
bafb031b DE |
237 | %{mcpu=v9:-D__sparc_v9__} \ |
238 | %{mcpu=ultrasparc:-D__sparc_v9__} \ | |
a0a301fc | 239 | %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ |
7a6cf439 | 240 | " |
885d8175 | 241 | |
a0a301fc DE |
242 | /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses |
243 | the right varags.h file when bootstrapping. */ | |
244 | /* ??? It's not clear what value we want to use for -Acpu/machine for | |
245 | sparc64 in 32 bit environments, so for now we only use `sparc64' in | |
246 | 64 bit environments. */ | |
247 | ||
345a6161 DM |
248 | #ifdef SPARC_BI_ARCH |
249 | ||
250 | #define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \ | |
251 | -D__GCC_NEW_VARARGS__ -Acpu(sparc) -Amachine(sparc)" | |
252 | #define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \ | |
253 | -D__arch64__ -Acpu(sparc64) -Amachine(sparc64)" | |
254 | ||
255 | #else | |
256 | ||
a0a301fc DE |
257 | #define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu(sparc) -Amachine(sparc)" |
258 | #define CPP_ARCH64_SPEC "-D__arch64__ -Acpu(sparc64) -Amachine(sparc64)" | |
345a6161 DM |
259 | |
260 | #endif | |
261 | ||
a0a301fc DE |
262 | #define CPP_ARCH_DEFAULT_SPEC \ |
263 | (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) | |
264 | ||
265 | #define CPP_ARCH_SPEC "\ | |
266 | %{m32:%(cpp_arch32)} \ | |
267 | %{m64:%(cpp_arch64)} \ | |
268 | %{!m32:%{!m64:%(cpp_arch_default)}} \ | |
269 | " | |
270 | ||
271 | /* Macros to distinguish endianness. */ | |
8947065c RH |
272 | #define CPP_ENDIAN_SPEC "\ |
273 | %{mlittle-endian:-D__LITTLE_ENDIAN__} \ | |
274 | %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}" | |
a0a301fc DE |
275 | |
276 | /* Macros to distinguish the particular subtarget. */ | |
277 | #define CPP_SUBTARGET_SPEC "" | |
278 | ||
279 | #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)" | |
280 | ||
b1fc14e5 RS |
281 | /* Prevent error on `-sun4' and `-target sun4' options. */ |
282 | /* This used to translate -dalign to -malign, but that is no good | |
283 | because it can't turn off the usual meaning of making debugging dumps. */ | |
bafb031b | 284 | /* Translate old style -m<cpu> into new style -mcpu=<cpu>. |
1cdbf242 | 285 | ??? Delete support for -m<cpu> for 2.9. */ |
bafb031b DE |
286 | |
287 | #define CC1_SPEC "\ | |
288 | %{sun4:} %{target:} \ | |
289 | %{mcypress:-mcpu=cypress} \ | |
290 | %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ | |
291 | %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ | |
292 | " | |
293 | ||
bafb031b DE |
294 | /* Override in target specific files. */ |
295 | #define ASM_CPU_SPEC "\ | |
9b7c06d2 | 296 | %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ |
bafb031b DE |
297 | %{msparclite:-Asparclite} \ |
298 | %{mf930:-Asparclite} %{mf934:-Asparclite} \ | |
299 | %{mcpu=sparclite:-Asparclite} \ | |
8d72ec32 | 300 | %{mcpu=sparclite86x:-Asparclite} \ |
bafb031b | 301 | %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ |
284d86e9 | 302 | %{mv8plus:-Av8plus} \ |
bafb031b | 303 | %{mcpu=v9:-Av9} \ |
284d86e9 | 304 | %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ |
a0a301fc | 305 | %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \ |
bafb031b DE |
306 | " |
307 | ||
e632a26c DE |
308 | /* Word size selection, among other things. |
309 | This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ | |
310 | ||
a0a301fc DE |
311 | #define ASM_ARCH32_SPEC "-32" |
312 | #define ASM_ARCH64_SPEC "-64" | |
313 | #define ASM_ARCH_DEFAULT_SPEC \ | |
e632a26c | 314 | (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) |
a0a301fc DE |
315 | |
316 | #define ASM_ARCH_SPEC "\ | |
317 | %{m32:%(asm_arch32)} \ | |
318 | %{m64:%(asm_arch64)} \ | |
319 | %{!m32:%{!m64:%(asm_arch_default)}} \ | |
320 | " | |
321 | ||
322 | /* Special flags to the Sun-4 assembler when using pipe for input. */ | |
323 | ||
324 | #define ASM_SPEC "\ | |
325 | %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \ | |
e632a26c | 326 | %(asm_cpu) \ |
a0a301fc DE |
327 | " |
328 | ||
329 | #define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}" | |
330 | ||
331 | /* Provide required defaults for linker -e and -d switches. */ | |
332 | ||
333 | #define LINK_SPEC \ | |
334 | "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \ | |
335 | %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}" | |
336 | ||
bafb031b DE |
337 | /* This macro defines names of additional specifications to put in the specs |
338 | that can be used in various specifications like CC1_SPEC. Its definition | |
339 | is an initializer with a subgrouping for each command option. | |
340 | ||
341 | Each subgrouping contains a string constant, that defines the | |
342 | specification name, and a string constant that used by the GNU CC driver | |
343 | program. | |
344 | ||
345 | Do not define this macro if it does not need to do anything. */ | |
1bb87f28 | 346 | |
a0a301fc | 347 | #define EXTRA_SPECS \ |
829245be KG |
348 | { "cpp_cpu", CPP_CPU_SPEC }, \ |
349 | { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ | |
350 | { "cpp_arch32", CPP_ARCH32_SPEC }, \ | |
351 | { "cpp_arch64", CPP_ARCH64_SPEC }, \ | |
352 | { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ | |
353 | { "cpp_arch", CPP_ARCH_SPEC }, \ | |
354 | { "cpp_endian", CPP_ENDIAN_SPEC }, \ | |
355 | { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ | |
356 | { "asm_cpu", ASM_CPU_SPEC }, \ | |
357 | { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ | |
358 | { "asm_arch32", ASM_ARCH32_SPEC }, \ | |
359 | { "asm_arch64", ASM_ARCH64_SPEC }, \ | |
360 | { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ | |
361 | { "asm_arch", ASM_ARCH_SPEC }, \ | |
bafb031b | 362 | SUBTARGET_EXTRA_SPECS |
1bb87f28 | 363 | |
bafb031b DE |
364 | #define SUBTARGET_EXTRA_SPECS |
365 | \f | |
a0a301fc DE |
366 | #ifdef SPARC_BI_ARCH |
367 | #define NO_BUILTIN_PTRDIFF_TYPE | |
368 | #define NO_BUILTIN_SIZE_TYPE | |
857458c4 | 369 | #endif |
82d6b402 RH |
370 | #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") |
371 | #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") | |
7a6cf439 DE |
372 | |
373 | /* ??? This should be 32 bits for v9 but what can we do? */ | |
1bb87f28 JW |
374 | #define WCHAR_TYPE "short unsigned int" |
375 | #define WCHAR_TYPE_SIZE 16 | |
7a6cf439 | 376 | #define MAX_WCHAR_TYPE_SIZE 16 |
1bb87f28 | 377 | |
4f074454 RK |
378 | /* Show we can debug even without a frame pointer. */ |
379 | #define CAN_DEBUG_WITHOUT_FP | |
1bb87f28 | 380 | |
5b485d2c JW |
381 | /* To make profiling work with -f{pic,PIC}, we need to emit the profiling |
382 | code into the rtl. Also, if we are profiling, we cannot eliminate | |
383 | the frame pointer (because the return address will get smashed). */ | |
384 | ||
7a6cf439 DE |
385 | void sparc_override_options (); |
386 | ||
5b485d2c | 387 | #define OVERRIDE_OPTIONS \ |
7a6cf439 | 388 | do { \ |
3a95cde8 | 389 | if (profile_flag || profile_block_flag || profile_arc_flag) \ |
7a6cf439 DE |
390 | { \ |
391 | if (flag_pic) \ | |
392 | { \ | |
3bb5de61 | 393 | const char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC";\ |
7a6cf439 DE |
394 | warning ("%s and profiling conflict: disabling %s", \ |
395 | pic_string, pic_string); \ | |
396 | flag_pic = 0; \ | |
397 | } \ | |
398 | flag_omit_frame_pointer = 0; \ | |
399 | } \ | |
7a6cf439 | 400 | sparc_override_options (); \ |
bafb031b | 401 | SUBTARGET_OVERRIDE_OPTIONS; \ |
7a6cf439 | 402 | } while (0) |
84ab3bfb | 403 | |
cf9be6f0 | 404 | /* This is meant to be redefined in the host dependent files. */ |
84ab3bfb | 405 | #define SUBTARGET_OVERRIDE_OPTIONS |
5b485d2c | 406 | |
1bb87f28 JW |
407 | /* These compiler options take an argument. We ignore -target for now. */ |
408 | ||
409 | #define WORD_SWITCH_TAKES_ARG(STR) \ | |
3b39b94f ILT |
410 | (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ |
411 | || !strcmp (STR, "target") || !strcmp (STR, "assert")) | |
1bb87f28 | 412 | |
1bb87f28 JW |
413 | /* Print subsidiary information on the compiler version in use. */ |
414 | ||
415 | #define TARGET_VERSION fprintf (stderr, " (sparc)"); | |
416 | ||
417 | /* Generate DBX debugging information. */ | |
418 | ||
419 | #define DBX_DEBUGGING_INFO | |
7a6cf439 | 420 | \f |
1bb87f28 JW |
421 | /* Run-time compilation parameters selecting different hardware subsets. */ |
422 | ||
423 | extern int target_flags; | |
424 | ||
425 | /* Nonzero if we should generate code to use the fpu. */ | |
7a6cf439 DE |
426 | #define MASK_FPU 1 |
427 | #define TARGET_FPU (target_flags & MASK_FPU) | |
1bb87f28 JW |
428 | |
429 | /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we | |
430 | use fast return insns, but lose some generality. */ | |
7a6cf439 DE |
431 | #define MASK_EPILOGUE 2 |
432 | #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE) | |
1bb87f28 | 433 | |
95dea81f JW |
434 | /* Nonzero if we should assume that double pointers might be unaligned. |
435 | This can happen when linking gcc compiled code with other compilers, | |
436 | because the ABI only guarantees 4 byte alignment. */ | |
7a6cf439 DE |
437 | #define MASK_UNALIGNED_DOUBLES 4 |
438 | #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES) | |
439 | ||
885d8175 | 440 | /* Nonzero means that we should generate code for a v8 sparc. */ |
6f64bf5f | 441 | #define MASK_V8 0x8 |
7a6cf439 | 442 | #define TARGET_V8 (target_flags & MASK_V8) |
885d8175 | 443 | |
bc9e02ae JW |
444 | /* Nonzero means that we should generate code for a sparclite. |
445 | This enables the sparclite specific instructions, but does not affect | |
446 | whether FPU instructions are emitted. */ | |
6f64bf5f | 447 | #define MASK_SPARCLITE 0x10 |
7a6cf439 | 448 | #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE) |
885d8175 | 449 | |
bafb031b DE |
450 | /* Nonzero if we're compiling for the sparclet. */ |
451 | #define MASK_SPARCLET 0x20 | |
452 | #define TARGET_SPARCLET (target_flags & MASK_SPARCLET) | |
6f64bf5f DE |
453 | |
454 | /* Nonzero if we're compiling for v9 sparc. | |
455 | Note that v9's can run in 32 bit mode so this doesn't necessarily mean | |
bafb031b | 456 | the word size is 64. */ |
6f64bf5f DE |
457 | #define MASK_V9 0x40 |
458 | #define TARGET_V9 (target_flags & MASK_V9) | |
459 | ||
bafb031b DE |
460 | /* Non-zero to generate code that uses the instructions deprecated in |
461 | the v9 architecture. This option only applies to v9 systems. */ | |
462 | /* ??? This isn't user selectable yet. It's used to enable such insns | |
463 | on 32 bit v9 systems and for the moment they're permanently disabled | |
464 | on 64 bit v9 systems. */ | |
465 | #define MASK_DEPRECATED_V8_INSNS 0x80 | |
466 | #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS) | |
6f64bf5f | 467 | |
bafb031b DE |
468 | /* Mask of all CPU selection flags. */ |
469 | #define MASK_ISA \ | |
470 | (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS) | |
6f64bf5f | 471 | |
bafb031b DE |
472 | /* Non-zero means don't pass `-assert pure-text' to the linker. */ |
473 | #define MASK_IMPURE_TEXT 0x100 | |
474 | #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT) | |
5b485d2c | 475 | |
9a1c7cd7 | 476 | /* Nonzero means that we should generate code using a flat register window |
bafb031b DE |
477 | model, i.e. no save/restore instructions are generated, which is |
478 | compatible with normal sparc code. | |
479 | The frame pointer is %i7 instead of %fp. */ | |
7a6cf439 DE |
480 | #define MASK_FLAT 0x200 |
481 | #define TARGET_FLAT (target_flags & MASK_FLAT) | |
9a1c7cd7 | 482 | |
34ad7aaf | 483 | /* Nonzero means use the registers that the Sparc ABI reserves for |
bafb031b DE |
484 | application software. This must be the default to coincide with the |
485 | setting in FIXED_REGISTERS. */ | |
7a6cf439 DE |
486 | #define MASK_APP_REGS 0x400 |
487 | #define TARGET_APP_REGS (target_flags & MASK_APP_REGS) | |
34ad7aaf | 488 | |
eb582c5d DE |
489 | /* Option to select how quad word floating point is implemented. |
490 | When TARGET_HARD_QUAD is true, we use the hardware quad instructions. | |
491 | Otherwise, we use the SPARC ABI quad library functions. */ | |
7a6cf439 DE |
492 | #define MASK_HARD_QUAD 0x800 |
493 | #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD) | |
494 | ||
62f1c649 DE |
495 | /* Non-zero on little-endian machines. */ |
496 | /* ??? Little endian support currently only exists for sparclet-aout and | |
497 | sparc64-elf configurations. May eventually want to expand the support | |
498 | to all targets, but for now it's kept local to only those two. */ | |
499 | #define MASK_LITTLE_ENDIAN 0x1000 | |
500 | #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN) | |
7a6cf439 | 501 | |
a0a301fc | 502 | /* 0x2000, 0x4000 are unused */ |
7a6cf439 DE |
503 | |
504 | /* Nonzero if pointers are 64 bits. | |
345a6161 | 505 | At the moment it must follow architecture size flag. */ |
7a6cf439 DE |
506 | #define MASK_PTR64 0x8000 |
507 | #define TARGET_PTR64 (target_flags & MASK_PTR64) | |
508 | ||
a0a301fc DE |
509 | /* Nonzero if generating code to run in a 64 bit environment. |
510 | This is intended to only be used by TARGET_ARCH{32,64} as they are the | |
511 | mechanism used to control compile time or run time selection. */ | |
512 | #define MASK_64BIT 0x10000 | |
513 | #define TARGET_64BIT (target_flags & MASK_64BIT) | |
514 | ||
515 | /* 0x20000,0x40000 unused */ | |
7a6cf439 DE |
516 | |
517 | /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by | |
518 | adding 2047 to %sp. This option is for v9 only and is the default. */ | |
519 | #define MASK_STACK_BIAS 0x80000 | |
520 | #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS) | |
8248e2bc | 521 | |
c4ce6853 DE |
522 | /* Non-zero means %g0 is a normal register. |
523 | We still clobber it as necessary, but we can't rely on it always having | |
524 | a zero value. | |
525 | We don't bother to support this in true 64 bit mode. */ | |
526 | #define MASK_LIVE_G0 0x100000 | |
527 | #define TARGET_LIVE_G0 (target_flags & MASK_LIVE_G0) | |
528 | ||
9b7c06d2 DE |
529 | /* Non-zero means the cpu has broken `save' and `restore' insns, only |
530 | the trivial versions work (save %g0,%g0,%g0; restore %g0,%g0,%g0). | |
531 | We assume the environment will properly handle or otherwise avoid | |
956d6950 JL |
532 | trouble associated with an interrupt occurring after the `save' or trap |
533 | occurring during it. */ | |
9b7c06d2 DE |
534 | #define MASK_BROKEN_SAVERESTORE 0x200000 |
535 | #define TARGET_BROKEN_SAVERESTORE (target_flags & MASK_BROKEN_SAVERESTORE) | |
536 | ||
1f1406b4 DE |
537 | /* Non-zero means -m{,no-}fpu was passed on the command line. */ |
538 | #define MASK_FPU_SET 0x400000 | |
539 | #define TARGET_FPU_SET (target_flags & MASK_FPU_SET) | |
540 | ||
bfd6bc60 JC |
541 | /* Use the UltraSPARC Visual Instruction Set extensions. */ |
542 | #define MASK_VIS 0x1000000 | |
543 | #define TARGET_VIS (target_flags & MASK_VIS) | |
544 | ||
284d86e9 | 545 | /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of |
5cb01b65 JJ |
546 | the current out and global registers and Linux 2.2+ as well. */ |
547 | #define MASK_V8PLUS 0x2000000 | |
bfd6bc60 JC |
548 | #define TARGET_V8PLUS (target_flags & MASK_V8PLUS) |
549 | ||
284d86e9 JC |
550 | /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y. |
551 | TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y | |
552 | to get high 32 bits. False in V8+ or V9 because multiply stores | |
553 | a 64 bit result in a register. */ | |
554 | ||
bfd6bc60 JC |
555 | #define TARGET_HARD_MUL32 \ |
556 | ((TARGET_V8 || TARGET_SPARCLITE \ | |
557 | || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \ | |
5cb01b65 | 558 | && ! TARGET_V8PLUS && TARGET_ARCH32) |
bfd6bc60 JC |
559 | |
560 | #define TARGET_HARD_MUL \ | |
561 | (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \ | |
562 | || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS) | |
563 | ||
564 | ||
1bb87f28 JW |
565 | /* Macro to define tables used to set the flags. |
566 | This is a list in braces of pairs in braces, | |
567 | each pair being { "NAME", VALUE } | |
568 | where VALUE is the bits to set or minus the bits to clear. | |
569 | An empty string NAME is used to identify the default VALUE. */ | |
570 | ||
571 | #define TARGET_SWITCHES \ | |
14f45d6b DM |
572 | { {"fpu", MASK_FPU | MASK_FPU_SET, "Use hardware fp" }, \ |
573 | {"no-fpu", -MASK_FPU, "Do not use hardware fp" }, \ | |
574 | {"no-fpu", MASK_FPU_SET, "Do not use hardware fp" }, \ | |
575 | {"hard-float", MASK_FPU | MASK_FPU_SET, "Use hardware fp" }, \ | |
576 | {"soft-float", -MASK_FPU, "Do not use hardware fp" }, \ | |
577 | {"soft-float", MASK_FPU_SET, "Do not use hardware fp" }, \ | |
578 | {"epilogue", MASK_EPILOGUE, "Use FUNCTION_EPILOGUE" }, \ | |
579 | {"no-epilogue", -MASK_EPILOGUE, "Do not use FUNCTION_EPILOGUE" }, \ | |
580 | {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, "Assume possible double misalignment" },\ | |
581 | {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, "Assume all doubles are aligned" }, \ | |
582 | {"impure-text", MASK_IMPURE_TEXT, "Pass -assert pure-text to linker" }, \ | |
583 | {"no-impure-text", -MASK_IMPURE_TEXT, "Do not pass -assert pure-text to linker" }, \ | |
584 | {"flat", MASK_FLAT, "Use flat register window model" }, \ | |
585 | {"no-flat", -MASK_FLAT, "Do not use flat register window model" }, \ | |
586 | {"app-regs", MASK_APP_REGS, "Use ABI reserved registers" }, \ | |
587 | {"no-app-regs", -MASK_APP_REGS, "Do not use ABI reserved registers" }, \ | |
588 | {"hard-quad-float", MASK_HARD_QUAD, "Use hardware quad fp instructions" }, \ | |
589 | {"soft-quad-float", -MASK_HARD_QUAD, "Do not use hardware quad fp instructions" }, \ | |
590 | {"v8plus", MASK_V8PLUS, "Compile for v8plus ABI" }, \ | |
591 | {"no-v8plus", -MASK_V8PLUS, "Do not compile for v8plus ABI" }, \ | |
592 | {"vis", MASK_VIS, "Utilize Visual Instruction Set" }, \ | |
593 | {"no-vis", -MASK_VIS, "Do not utilize Visual Instruction Set" }, \ | |
a0a301fc | 594 | /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \ |
14f45d6b DM |
595 | {"cypress", 0, "Optimize for Cypress processors" }, \ |
596 | {"sparclite", 0, "Optimize for SparcLite processors" }, \ | |
597 | {"f930", 0, "Optimize for F930 processors" }, \ | |
598 | {"f934", 0, "Optimize for F934 processors" }, \ | |
599 | {"v8", 0, "Use V8 Sparc ISA" }, \ | |
600 | {"supersparc", 0, "Optimize for SuperSparc processors" }, \ | |
a0a301fc | 601 | /* End of deprecated options. */ \ |
14f45d6b DM |
602 | {"ptr64", MASK_PTR64, "Pointers are 64-bit" }, \ |
603 | {"ptr32", -MASK_PTR64, "Pointers are 32-bit" }, \ | |
604 | {"32", -MASK_64BIT, "Use 32-bit ABI" }, \ | |
605 | {"64", MASK_64BIT, "Use 64-bit ABI" }, \ | |
606 | {"stack-bias", MASK_STACK_BIAS, "Use stack bias" }, \ | |
607 | {"no-stack-bias", -MASK_STACK_BIAS, "Do not use stack bias" }, \ | |
7a6cf439 | 608 | SUBTARGET_SWITCHES \ |
ee76cf2a | 609 | { "", TARGET_DEFAULT, ""}} |
1bb87f28 | 610 | |
bafb031b DE |
611 | /* MASK_APP_REGS must always be the default because that's what |
612 | FIXED_REGISTERS is set to and -ffixed- is processed before | |
613 | CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */ | |
7a6cf439 | 614 | #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) |
84ab3bfb | 615 | |
bafb031b | 616 | /* This is meant to be redefined in target specific files. */ |
84ab3bfb | 617 | #define SUBTARGET_SWITCHES |
1bb87f28 | 618 | |
6afca97d DE |
619 | /* Processor type. |
620 | These must match the values for the cpu attribute in sparc.md. */ | |
621 | enum processor_type { | |
622 | PROCESSOR_V7, | |
623 | PROCESSOR_CYPRESS, | |
624 | PROCESSOR_V8, | |
625 | PROCESSOR_SUPERSPARC, | |
626 | PROCESSOR_SPARCLITE, | |
627 | PROCESSOR_F930, | |
628 | PROCESSOR_F934, | |
8947065c RH |
629 | PROCESSOR_HYPERSPARC, |
630 | PROCESSOR_SPARCLITE86X, | |
6afca97d | 631 | PROCESSOR_SPARCLET, |
9b7c06d2 | 632 | PROCESSOR_TSC701, |
6afca97d DE |
633 | PROCESSOR_V9, |
634 | PROCESSOR_ULTRASPARC | |
635 | }; | |
636 | ||
637 | /* This is set from -m{cpu,tune}=xxx. */ | |
638 | extern enum processor_type sparc_cpu; | |
639 | ||
640 | /* Recast the cpu class to be the cpu attribute. | |
641 | Every file includes us, but not every file includes insn-attr.h. */ | |
642 | #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) | |
bafb031b DE |
643 | |
644 | /* This macro is similar to `TARGET_SWITCHES' but defines names of | |
645 | command options that have values. Its definition is an | |
646 | initializer with a subgrouping for each command option. | |
647 | ||
648 | Each subgrouping contains a string constant, that defines the | |
649 | fixed part of the option name, and the address of a variable. | |
650 | The variable, type `char *', is set to the variable part of the | |
651 | given option if the fixed part matches. The actual option name | |
652 | is made by appending `-m' to the specified name. | |
653 | ||
654 | Here is an example which defines `-mshort-data-NUMBER'. If the | |
655 | given option is `-mshort-data-512', the variable `m88k_short_data' | |
656 | will be set to the string `"512"'. | |
657 | ||
658 | extern char *m88k_short_data; | |
659 | #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */ | |
660 | ||
bafb031b | 661 | #define TARGET_OPTIONS \ |
1ccfa253 | 662 | { \ |
14f45d6b DM |
663 | { "cpu=", &sparc_select[1].string, "Use features of and schedule code for given CPU" }, \ |
664 | { "tune=", &sparc_select[2].string, "Schedule code for given CPU" }, \ | |
665 | { "cmodel=", &sparc_cmodel_string, "Use given Sparc code model" }, \ | |
666 | { "align-loops=", &sparc_align_loops_string, "Loop code aligned to this power of 2" }, \ | |
667 | { "align-jumps=", &sparc_align_jumps_string, "Jump targets are aligned to this power of 2" }, \ | |
668 | { "align-functions=", &sparc_align_funcs_string, "Function starts are aligned to this power of 2" }, \ | |
1ccfa253 | 669 | SUBTARGET_OPTIONS \ |
bafb031b DE |
670 | } |
671 | ||
672 | /* This is meant to be redefined in target specific files. */ | |
673 | #define SUBTARGET_OPTIONS | |
6afca97d DE |
674 | |
675 | /* sparc_select[0] is reserved for the default cpu. */ | |
676 | struct sparc_cpu_select | |
677 | { | |
3bb5de61 KG |
678 | const char *string; |
679 | const char *name; | |
6afca97d DE |
680 | int set_tune_p; |
681 | int set_arch_p; | |
682 | }; | |
683 | ||
684 | extern struct sparc_cpu_select sparc_select[]; | |
1ccfa253 DE |
685 | |
686 | /* Variables to record values the user passes. */ | |
3bb5de61 KG |
687 | extern const char *sparc_align_loops_string; |
688 | extern const char *sparc_align_jumps_string; | |
689 | extern const char *sparc_align_funcs_string; | |
1ccfa253 DE |
690 | /* Parsed values as a power of two. */ |
691 | extern int sparc_align_loops; | |
692 | extern int sparc_align_jumps; | |
693 | extern int sparc_align_funcs; | |
694 | ||
695 | #define DEFAULT_SPARC_ALIGN_FUNCS \ | |
696 | (sparc_cpu == PROCESSOR_ULTRASPARC ? 5 : 2) | |
7a6cf439 DE |
697 | \f |
698 | /* target machine storage layout */ | |
699 | ||
d667538b JW |
700 | /* Define for cross-compilation to a sparc target with no TFmode from a host |
701 | with a different float format (e.g. VAX). */ | |
702 | #define REAL_ARITHMETIC | |
703 | ||
1bb87f28 JW |
704 | /* Define this if most significant bit is lowest numbered |
705 | in instructions that operate on numbered bit-fields. */ | |
706 | #define BITS_BIG_ENDIAN 1 | |
707 | ||
708 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
1bb87f28 JW |
709 | #define BYTES_BIG_ENDIAN 1 |
710 | ||
711 | /* Define this if most significant word of a multiword number is the lowest | |
712 | numbered. */ | |
1bb87f28 JW |
713 | #define WORDS_BIG_ENDIAN 1 |
714 | ||
62f1c649 DE |
715 | /* Define this to set the endianness to use in libgcc2.c, which can |
716 | not depend on target_flags. */ | |
8947065c | 717 | #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__) |
62f1c649 DE |
718 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 |
719 | #else | |
720 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
721 | #endif | |
722 | ||
b4ac57ab | 723 | /* number of bits in an addressable storage unit */ |
1bb87f28 JW |
724 | #define BITS_PER_UNIT 8 |
725 | ||
726 | /* Width in bits of a "word", which is the contents of a machine register. | |
727 | Note that this is not necessarily the width of data type `int'; | |
728 | if using 16-bit ints on a 68000, this would still be 32. | |
729 | But on a machine with 16-bit registers, this would be 16. */ | |
6f64bf5f | 730 | #define BITS_PER_WORD (TARGET_ARCH64 ? 64 : 32) |
7a6cf439 | 731 | #define MAX_BITS_PER_WORD 64 |
1bb87f28 JW |
732 | |
733 | /* Width of a word, in units (bytes). */ | |
6f64bf5f | 734 | #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) |
ef0e53ce | 735 | #define MIN_UNITS_PER_WORD 4 |
7a6cf439 DE |
736 | |
737 | /* Now define the sizes of the C data types. */ | |
738 | ||
739 | #define SHORT_TYPE_SIZE 16 | |
a0a301fc DE |
740 | #define INT_TYPE_SIZE 32 |
741 | #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) | |
7a6cf439 DE |
742 | #define LONG_LONG_TYPE_SIZE 64 |
743 | #define FLOAT_TYPE_SIZE 32 | |
744 | #define DOUBLE_TYPE_SIZE 64 | |
745 | ||
a0a301fc | 746 | #if defined (SPARC_BI_ARCH) |
7a6cf439 | 747 | #define MAX_LONG_TYPE_SIZE 64 |
a0a301fc | 748 | #endif |
7a6cf439 | 749 | |
a0a301fc | 750 | #if 0 |
7a6cf439 DE |
751 | /* ??? This does not work in SunOS 4.x, so it is not enabled here. |
752 | Instead, it is enabled in sol2.h, because it does work under Solaris. */ | |
753 | /* Define for support of TFmode long double and REAL_ARITHMETIC. | |
754 | Sparc ABI says that long double is 4 words. */ | |
755 | #define LONG_DOUBLE_TYPE_SIZE 128 | |
756 | #endif | |
1bb87f28 JW |
757 | |
758 | /* Width in bits of a pointer. | |
759 | See also the macro `Pmode' defined below. */ | |
7a6cf439 | 760 | #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) |
1bb87f28 | 761 | |
4fb4e4b8 DE |
762 | /* A macro to update MODE and UNSIGNEDP when an object whose type |
763 | is TYPE and which has the specified mode and signedness is to be | |
764 | stored in a register. This macro is only called when TYPE is a | |
765 | scalar type. */ | |
766 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
767 | if (TARGET_ARCH64 \ | |
768 | && GET_MODE_CLASS (MODE) == MODE_INT \ | |
769 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
770 | { \ | |
771 | (MODE) = DImode; \ | |
772 | } | |
773 | ||
774 | /* Define this macro if the promotion described by PROMOTE_MODE | |
775 | should also be done for outgoing function arguments. */ | |
776 | /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op | |
777 | for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test | |
778 | for this value. */ | |
779 | #define PROMOTE_FUNCTION_ARGS | |
780 | ||
781 | /* Define this macro if the promotion described by PROMOTE_MODE | |
782 | should also be done for the return value of functions. | |
783 | If this macro is defined, FUNCTION_VALUE must perform the same | |
784 | promotions done by PROMOTE_MODE. */ | |
785 | /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op | |
786 | for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test | |
787 | for this value. */ | |
788 | #define PROMOTE_FUNCTION_RETURN | |
789 | ||
1bb87f28 | 790 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
6f64bf5f | 791 | #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) |
1bb87f28 JW |
792 | |
793 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
6f64bf5f | 794 | #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) |
1bb87f28 | 795 | |
10d1b70f JW |
796 | /* ALIGN FRAMES on double word boundaries */ |
797 | ||
7a6cf439 | 798 | #define SPARC_STACK_ALIGN(LOC) \ |
6f64bf5f | 799 | (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) |
10d1b70f | 800 | |
1bb87f28 | 801 | /* Allocation boundary (in *bits*) for the code of a function. */ |
1ccfa253 | 802 | #define FUNCTION_BOUNDARY (1 << (sparc_align_funcs + 3)) |
1bb87f28 JW |
803 | |
804 | /* Alignment of field after `int : 0' in a structure. */ | |
6f64bf5f | 805 | #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) |
1bb87f28 JW |
806 | |
807 | /* Every structure's size must be a multiple of this. */ | |
808 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
809 | ||
810 | /* A bitfield declared as `int' forces `int' alignment for the struct. */ | |
811 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
812 | ||
813 | /* No data type wants to be aligned rounder than this. */ | |
6f64bf5f | 814 | #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) |
1bb87f28 | 815 | |
77a02b01 JW |
816 | /* The best alignment to use in cases where we have a choice. */ |
817 | #define FASTEST_ALIGNMENT 64 | |
818 | ||
1bb87f28 JW |
819 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
820 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
d2a8e680 RS |
821 | ((TREE_CODE (EXP) == STRING_CST \ |
822 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
823 | ? FASTEST_ALIGNMENT : (ALIGN)) | |
1bb87f28 JW |
824 | |
825 | /* Make arrays of chars word-aligned for the same reasons. */ | |
826 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
827 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
828 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
77a02b01 | 829 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) |
1bb87f28 | 830 | |
b4ac57ab | 831 | /* Set this nonzero if move instructions will actually fail to work |
1bb87f28 | 832 | when given unaligned data. */ |
b4ac57ab | 833 | #define STRICT_ALIGNMENT 1 |
1bb87f28 JW |
834 | |
835 | /* Things that must be doubleword aligned cannot go in the text section, | |
836 | because the linker fails to align the text section enough! | |
7a6cf439 | 837 | Put them in the data section. This macro is only used in this file. */ |
1bb87f28 JW |
838 | #define MAX_TEXT_ALIGN 32 |
839 | ||
68d69835 JM |
840 | /* This forces all variables and constants to the data section when PIC. |
841 | This is because the SunOS 4 shared library scheme thinks everything in | |
842 | text is a function, and patches the address to point to a loader stub. */ | |
843 | /* This is defined to zero for every system which doesn't use the a.out object | |
844 | file format. */ | |
845 | #ifndef SUNOS4_SHARED_LIBRARIES | |
846 | #define SUNOS4_SHARED_LIBRARIES 0 | |
847 | #endif | |
848 | ||
7a6cf439 | 849 | /* This is defined differently for v9 in a cover file. */ |
1bb87f28 JW |
850 | #define SELECT_SECTION(T,RELOC) \ |
851 | { \ | |
852 | if (TREE_CODE (T) == VAR_DECL) \ | |
853 | { \ | |
854 | if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \ | |
ed8969fa JW |
855 | && DECL_INITIAL (T) \ |
856 | && (DECL_INITIAL (T) == error_mark_node \ | |
857 | || TREE_CONSTANT (DECL_INITIAL (T))) \ | |
1bb87f28 | 858 | && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \ |
68d69835 | 859 | && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \ |
1bb87f28 JW |
860 | text_section (); \ |
861 | else \ | |
862 | data_section (); \ | |
863 | } \ | |
864 | else if (TREE_CODE (T) == CONSTRUCTOR) \ | |
865 | { \ | |
68d69835 | 866 | if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \ |
1bb87f28 JW |
867 | data_section (); \ |
868 | } \ | |
07516036 | 869 | else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c') \ |
1bb87f28 JW |
870 | { \ |
871 | if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \ | |
68d69835 JM |
872 | || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \ |
873 | || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \ | |
1bb87f28 JW |
874 | data_section (); \ |
875 | else \ | |
876 | text_section (); \ | |
877 | } \ | |
878 | } | |
879 | ||
880 | /* Use text section for a constant | |
881 | unless we need more alignment than that offers. */ | |
7a6cf439 | 882 | /* This is defined differently for v9 in a cover file. */ |
1bb87f28 JW |
883 | #define SELECT_RTX_SECTION(MODE, X) \ |
884 | { \ | |
885 | if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \ | |
68d69835 | 886 | && ! (flag_pic && (symbolic_operand (X) || SUNOS4_SHARED_LIBRARIES))) \ |
1bb87f28 JW |
887 | text_section (); \ |
888 | else \ | |
889 | data_section (); \ | |
890 | } | |
891 | \f | |
892 | /* Standard register usage. */ | |
893 | ||
894 | /* Number of actual hardware registers. | |
895 | The hardware registers are assigned numbers for the compiler | |
896 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
897 | All registers that the compiler knows about must be given numbers, | |
898 | even those that are not normally considered general registers. | |
899 | ||
7a6cf439 DE |
900 | SPARC has 32 integer registers and 32 floating point registers. |
901 | 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not | |
902 | accessible. We still account for them to simplify register computations | |
903 | (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so | |
904 | 32+32+32+4 == 100. | |
c4ce6853 | 905 | Register 100 is used as the integer condition code register. */ |
1bb87f28 | 906 | |
c4ce6853 | 907 | #define FIRST_PSEUDO_REGISTER 101 |
6afca97d | 908 | |
4fb4e4b8 | 909 | #define SPARC_FIRST_FP_REG 32 |
6afca97d | 910 | /* Additional V9 fp regs. */ |
4fb4e4b8 DE |
911 | #define SPARC_FIRST_V9_FP_REG 64 |
912 | #define SPARC_LAST_V9_FP_REG 95 | |
c4ce6853 DE |
913 | /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ |
914 | #define SPARC_FIRST_V9_FCC_REG 96 | |
915 | #define SPARC_LAST_V9_FCC_REG 99 | |
916 | /* V8 fcc reg. */ | |
917 | #define SPARC_FCC_REG 96 | |
918 | /* Integer CC reg. We don't distinguish %icc from %xcc. */ | |
919 | #define SPARC_ICC_REG 100 | |
1bb87f28 | 920 | |
4fb4e4b8 DE |
921 | /* Nonzero if REGNO is an fp reg. */ |
922 | #define SPARC_FP_REG_P(REGNO) \ | |
923 | ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) | |
924 | ||
925 | /* Argument passing regs. */ | |
926 | #define SPARC_OUTGOING_INT_ARG_FIRST 8 | |
a9e95099 | 927 | #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) |
4fb4e4b8 DE |
928 | #define SPARC_FP_ARG_FIRST 32 |
929 | ||
1bb87f28 JW |
930 | /* 1 for registers that have pervasive standard uses |
931 | and are not available for the register allocator. | |
4fb4e4b8 | 932 | |
7a6cf439 | 933 | On non-v9 systems: |
34ad7aaf JW |
934 | g1 is free to use as temporary. |
935 | g2-g4 are reserved for applications. Gcc normally uses them as | |
936 | temporaries, but this can be disabled via the -mno-app-regs option. | |
7a6cf439 | 937 | g5 through g7 are reserved for the operating system. |
4fb4e4b8 | 938 | |
7a6cf439 | 939 | On v9 systems: |
a0a301fc DE |
940 | g1,g5 are free to use as temporaries, and are free to use between calls |
941 | if the call is to an external function via the PLT. | |
942 | g4 is free to use as a temporary in the non-embedded case. | |
943 | g4 is reserved in the embedded case. | |
4fb4e4b8 | 944 | g2-g3 are reserved for applications. Gcc normally uses them as |
bafb031b | 945 | temporaries, but this can be disabled via the -mno-app-regs option. |
a0a301fc DE |
946 | g6-g7 are reserved for the operating system (or application in |
947 | embedded case). | |
7a6cf439 DE |
948 | ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must |
949 | currently be a fixed register until this pattern is rewritten. | |
950 | Register 1 is also used when restoring call-preserved registers in large | |
6afca97d DE |
951 | stack frames. |
952 | ||
953 | Registers fixed in arch32 and not arch64 (or vice-versa) are marked in | |
954 | CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. | |
955 | */ | |
7a6cf439 | 956 | |
7a6cf439 | 957 | #define FIXED_REGISTERS \ |
c4ce6853 | 958 | {1, 0, 0, 0, 0, 0, 1, 1, \ |
7a6cf439 DE |
959 | 0, 0, 0, 0, 0, 0, 1, 0, \ |
960 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
961 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
962 | \ | |
963 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
964 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
965 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
966 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
967 | \ | |
968 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
969 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
970 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
971 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
972 | \ | |
c4ce6853 | 973 | 0, 0, 0, 0, 0} |
1bb87f28 JW |
974 | |
975 | /* 1 for registers not available across function calls. | |
976 | These must include the FIXED_REGISTERS and also any | |
977 | registers that can be used without being saved. | |
978 | The latter must include the registers where values are returned | |
979 | and the register where structure-value addresses are passed. | |
980 | Aside from that, you can include as many other registers as you like. */ | |
7a6cf439 | 981 | |
bafb031b DE |
982 | #define CALL_USED_REGISTERS \ |
983 | {1, 1, 1, 1, 1, 1, 1, 1, \ | |
984 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
985 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
986 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
987 | \ | |
988 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
989 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
990 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
991 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
992 | \ | |
993 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
994 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
995 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
996 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
997 | \ | |
c4ce6853 | 998 | 1, 1, 1, 1, 1} |
1bb87f28 | 999 | |
c4ce6853 DE |
1000 | /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that |
1001 | they won't be allocated. */ | |
26c5587d JW |
1002 | |
1003 | #define CONDITIONAL_REGISTER_USAGE \ | |
1004 | do \ | |
1005 | { \ | |
c7b2eb81 VM |
1006 | if (flag_pic) \ |
1007 | { \ | |
1008 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
1009 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
1010 | } \ | |
a0a301fc | 1011 | if (TARGET_ARCH32) \ |
6f64bf5f | 1012 | { \ |
6f64bf5f | 1013 | fixed_regs[5] = 1; \ |
6f64bf5f | 1014 | } \ |
e0d80184 DM |
1015 | if (TARGET_LIVE_G0) \ |
1016 | fixed_regs[0] = 0; \ | |
6afca97d DE |
1017 | if (! TARGET_V9) \ |
1018 | { \ | |
1019 | int regno; \ | |
1020 | for (regno = SPARC_FIRST_V9_FP_REG; \ | |
1021 | regno <= SPARC_LAST_V9_FP_REG; \ | |
1022 | regno++) \ | |
1023 | fixed_regs[regno] = 1; \ | |
c4ce6853 DE |
1024 | /* %fcc0 is used by v8 and v9. */ \ |
1025 | for (regno = SPARC_FIRST_V9_FCC_REG + 1; \ | |
1026 | regno <= SPARC_LAST_V9_FCC_REG; \ | |
1027 | regno++) \ | |
1028 | fixed_regs[regno] = 1; \ | |
6afca97d | 1029 | } \ |
26c5587d JW |
1030 | if (! TARGET_FPU) \ |
1031 | { \ | |
1032 | int regno; \ | |
c4ce6853 | 1033 | for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \ |
26c5587d JW |
1034 | fixed_regs[regno] = 1; \ |
1035 | } \ | |
bafb031b DE |
1036 | /* Don't unfix g2-g4 if they were fixed with -ffixed-. */ \ |
1037 | fixed_regs[2] |= ! TARGET_APP_REGS; \ | |
1038 | fixed_regs[3] |= ! TARGET_APP_REGS; \ | |
a0a301fc | 1039 | fixed_regs[4] |= ! TARGET_APP_REGS || TARGET_CM_EMBMEDANY; \ |
5c56efde DE |
1040 | if (TARGET_FLAT) \ |
1041 | { \ | |
1042 | /* Let the compiler believe the frame pointer is still \ | |
1043 | %fp, but output it as %i7. */ \ | |
1044 | fixed_regs[31] = 1; \ | |
1045 | reg_names[FRAME_POINTER_REGNUM] = "%i7"; \ | |
1046 | /* ??? This is a hack to disable leaf functions. */ \ | |
1047 | global_regs[7] = 1; \ | |
1048 | } \ | |
9ee6230c JW |
1049 | if (profile_block_flag) \ |
1050 | { \ | |
1051 | /* %g1 and %g2 must be fixed, because BLOCK_PROFILER \ | |
1052 | uses them. */ \ | |
1053 | fixed_regs[1] = 1; \ | |
1054 | fixed_regs[2] = 1; \ | |
1055 | } \ | |
26c5587d JW |
1056 | } \ |
1057 | while (0) | |
1058 | ||
1bb87f28 JW |
1059 | /* Return number of consecutive hard regs needed starting at reg REGNO |
1060 | to hold something of mode MODE. | |
1061 | This is ordinarily the length in words of a value of mode MODE | |
1062 | but can be less for certain modes in special long registers. | |
1063 | ||
1064 | On SPARC, ordinary registers hold 32 bits worth; | |
1065 | this means both integer and floating point registers. | |
7a6cf439 DE |
1066 | On v9, integer regs hold 64 bits worth; floating point regs hold |
1067 | 32 bits worth (this includes the new fp regs as even the odd ones are | |
1068 | included in the hard register count). */ | |
1bb87f28 | 1069 | |
7a6cf439 | 1070 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
6f64bf5f | 1071 | (TARGET_ARCH64 \ |
7a6cf439 DE |
1072 | ? ((REGNO) < 32 \ |
1073 | ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ | |
1074 | : (GET_MODE_SIZE (MODE) + 3) / 4) \ | |
1075 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
1bb87f28 | 1076 | |
284d86e9 JC |
1077 | /* A subreg in 64 bit mode will have the wrong offset for a floating point |
1078 | register. The least significant part is at offset 1, compared to 0 for | |
03ad6f4d DM |
1079 | integer registers. This only applies when FMODE is a larger mode. |
1080 | We also need to handle a special case of TF-->DF conversions. */ | |
284d86e9 | 1081 | #define ALTER_HARD_SUBREG(TMODE, WORD, FMODE, REGNO) \ |
e0d80184 DM |
1082 | (TARGET_ARCH64 \ |
1083 | && (REGNO) >= SPARC_FIRST_FP_REG \ | |
1084 | && (REGNO) <= SPARC_LAST_V9_FP_REG \ | |
1085 | && (TMODE) == SImode \ | |
1086 | && !((FMODE) == QImode || (FMODE) == HImode) \ | |
1087 | ? ((REGNO) + 1) \ | |
03ad6f4d DM |
1088 | : ((TMODE) == DFmode && (FMODE) == TFmode) \ |
1089 | ? ((REGNO) + ((WORD) * 2)) \ | |
1090 | : ((REGNO) + (WORD))) | |
284d86e9 | 1091 | |
1bb87f28 | 1092 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. |
923a8d06 | 1093 | See sparc.c for how we initialize this. */ |
7a6cf439 DE |
1094 | extern int *hard_regno_mode_classes; |
1095 | extern int sparc_mode_class[]; | |
1bb87f28 | 1096 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
7a6cf439 | 1097 | ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) |
1bb87f28 JW |
1098 | |
1099 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1100 | when one has mode MODE1 and one has mode MODE2. | |
1101 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
7a6cf439 DE |
1102 | for any hard reg, then this must be 0 for correct output. |
1103 | ||
1104 | For V9: SFmode can't be combined with other float modes, because they can't | |
1105 | be allocated to the %d registers. Also, DFmode won't fit in odd %f | |
1106 | registers, but SFmode will. */ | |
1bb87f28 | 1107 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
7a6cf439 DE |
1108 | ((MODE1) == (MODE2) \ |
1109 | || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ | |
1110 | && (! TARGET_V9 \ | |
1111 | || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ | |
1112 | || (MODE1 != SFmode && MODE2 != SFmode))))) | |
1bb87f28 JW |
1113 | |
1114 | /* Specify the registers used for certain standard purposes. | |
1115 | The values of these macros are register numbers. */ | |
1116 | ||
1117 | /* SPARC pc isn't overloaded on a register that the compiler knows about. */ | |
1118 | /* #define PC_REGNUM */ | |
1119 | ||
1120 | /* Register to use for pushing function arguments. */ | |
1121 | #define STACK_POINTER_REGNUM 14 | |
1122 | ||
4fb4e4b8 | 1123 | /* Actual top-of-stack address is 92/176 greater than the contents of the |
7a6cf439 DE |
1124 | stack pointer register for !v9/v9. That is: |
1125 | - !v9: 64 bytes for the in and local registers, 4 bytes for structure return | |
4fb4e4b8 DE |
1126 | address, and 6*4 bytes for the 6 register parameters. |
1127 | - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer | |
1128 | parameter regs. */ | |
1bb87f28 JW |
1129 | #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0) |
1130 | ||
7a6cf439 | 1131 | /* The stack bias (amount by which the hardware register is offset by). */ |
a0a301fc | 1132 | #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) |
7a6cf439 | 1133 | |
1ccfa253 DE |
1134 | /* Is stack biased? */ |
1135 | #define STACK_BIAS SPARC_STACK_BIAS | |
1136 | ||
1bb87f28 JW |
1137 | /* Base register for access to local variables of the function. */ |
1138 | #define FRAME_POINTER_REGNUM 30 | |
1139 | ||
1140 | #if 0 | |
9704efe6 | 1141 | /* Register that is used for the return address for the flat model. */ |
1bb87f28 JW |
1142 | #define RETURN_ADDR_REGNUM 15 |
1143 | #endif | |
1144 | ||
1145 | /* Value should be nonzero if functions must have frame pointers. | |
1146 | Zero means the frame pointer need not be set up (and parms | |
1147 | may be accessed via the stack pointer) in functions that seem suitable. | |
1148 | This is computed in `reload', in reload1.c. | |
a061b9fa | 1149 | Used in flow.c, global.c, and reload1.c. |
1bb87f28 | 1150 | |
a061b9fa DE |
1151 | Being a non-leaf function does not mean a frame pointer is needed in the |
1152 | flat window model. However, the debugger won't be able to backtrace through | |
1153 | us with out it. */ | |
1bb87f28 | 1154 | #define FRAME_POINTER_REQUIRED \ |
bafb031b DE |
1155 | (TARGET_FLAT ? (current_function_calls_alloca || current_function_varargs \ |
1156 | || !leaf_function_p ()) \ | |
5c56efde | 1157 | : ! (leaf_function_p () && only_leaf_regs_used ())) |
1bb87f28 JW |
1158 | |
1159 | /* C statement to store the difference between the frame pointer | |
1160 | and the stack pointer values immediately after the function prologue. | |
1161 | ||
1162 | Note, we always pretend that this is a leaf function because if | |
1163 | it's not, there's no point in trying to eliminate the | |
1164 | frame pointer. If it is a leaf function, we guessed right! */ | |
1165 | #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ | |
bafb031b | 1166 | ((VAR) = (TARGET_FLAT ? sparc_flat_compute_frame_size (get_frame_size ()) \ |
5b485d2c | 1167 | : compute_frame_size (get_frame_size (), 1))) |
1bb87f28 JW |
1168 | |
1169 | /* Base register for access to arguments of the function. */ | |
5c56efde | 1170 | #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM |
1bb87f28 | 1171 | |
6098b63e | 1172 | /* Register in which static-chain is passed to a function. This must |
c8392688 | 1173 | not be a register used by the prologue. */ |
6f64bf5f | 1174 | #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) |
1bb87f28 JW |
1175 | |
1176 | /* Register which holds offset table for position-independent | |
1177 | data references. */ | |
1178 | ||
1179 | #define PIC_OFFSET_TABLE_REGNUM 23 | |
1180 | ||
1bb87f28 JW |
1181 | #define FINALIZE_PIC finalize_pic () |
1182 | ||
82d6b402 RH |
1183 | /* Pick a default value we can notice from override_options: |
1184 | !v9: Default is on. | |
1185 | v9: Default is off. */ | |
1186 | ||
1187 | #define DEFAULT_PCC_STRUCT_RETURN -1 | |
1188 | ||
d9ca49d5 | 1189 | /* Sparc ABI says that quad-precision floats and all structures are returned |
7a6cf439 | 1190 | in memory. |
4fb4e4b8 | 1191 | For v9: unions <= 32 bytes in size are returned in int regs, |
82d6b402 | 1192 | structures up to 32 bytes are returned in int and fp regs. */ |
4fb4e4b8 | 1193 | |
686667bf | 1194 | #define RETURN_IN_MEMORY(TYPE) \ |
4fb4e4b8 DE |
1195 | (TARGET_ARCH32 \ |
1196 | ? (TYPE_MODE (TYPE) == BLKmode \ | |
1197 | || TYPE_MODE (TYPE) == TFmode \ | |
1198 | || TYPE_MODE (TYPE) == TCmode) \ | |
82d6b402 RH |
1199 | : (TYPE_MODE (TYPE) == BLKmode \ |
1200 | && int_size_in_bytes (TYPE) > 32)) | |
d9ca49d5 | 1201 | |
1bb87f28 JW |
1202 | /* Functions which return large structures get the address |
1203 | to place the wanted value at offset 64 from the frame. | |
7a6cf439 DE |
1204 | Must reserve 64 bytes for the in and local registers. |
1205 | v9: Functions which return large structures get the address to place the | |
1206 | wanted value from an invisible first argument. */ | |
1bb87f28 JW |
1207 | /* Used only in other #defines in this file. */ |
1208 | #define STRUCT_VALUE_OFFSET 64 | |
1209 | ||
1210 | #define STRUCT_VALUE \ | |
6f64bf5f | 1211 | (TARGET_ARCH64 \ |
7a6cf439 | 1212 | ? 0 \ |
284d86e9 JC |
1213 | : gen_rtx_MEM (Pmode, \ |
1214 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, \ | |
3a598fbe | 1215 | GEN_INT (STRUCT_VALUE_OFFSET)))) |
1bb87f28 | 1216 | #define STRUCT_VALUE_INCOMING \ |
6f64bf5f | 1217 | (TARGET_ARCH64 \ |
7a6cf439 | 1218 | ? 0 \ |
284d86e9 JC |
1219 | : gen_rtx_MEM (Pmode, \ |
1220 | gen_rtx_PLUS (Pmode, frame_pointer_rtx, \ | |
3a598fbe | 1221 | GEN_INT (STRUCT_VALUE_OFFSET)))) |
1bb87f28 JW |
1222 | \f |
1223 | /* Define the classes of registers for register constraints in the | |
1224 | machine description. Also define ranges of constants. | |
1225 | ||
1226 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1227 | If there is more than one class, another class must be named NO_REGS | |
1228 | and contain no registers. | |
1229 | ||
1230 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1231 | another name such as ALL_REGS). This is the class of registers | |
1232 | that is allowed by "g" or "r" in a register constraint. | |
1233 | Also, registers outside this class are allocated only when | |
1234 | instructions express preferences for them. | |
1235 | ||
1236 | The classes must be numbered in nondecreasing order; that is, | |
1237 | a larger-numbered class must never be contained completely | |
1238 | in a smaller-numbered class. | |
1239 | ||
1240 | For any two classes, it is very desirable that there be another | |
1241 | class that represents their union. */ | |
1242 | ||
4fb4e4b8 DE |
1243 | /* The SPARC has various kinds of registers: general, floating point, |
1244 | and condition codes [well, it has others as well, but none that we | |
1245 | care directly about]. | |
24b63396 JW |
1246 | |
1247 | For v9 we must distinguish between the upper and lower floating point | |
1248 | registers because the upper ones can't hold SFmode values. | |
1249 | HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) | |
1250 | satisfying a group need for a class will also satisfy a single need for | |
1251 | that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp | |
1252 | regs. | |
1253 | ||
1254 | It is important that one class contains all the general and all the standard | |
1255 | fp regs. Otherwise find_reg() won't properly allocate int regs for moves, | |
1256 | because reg_class_record() will bias the selection in favor of fp regs, | |
1257 | because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, | |
1258 | because FP_REGS > GENERAL_REGS. | |
1259 | ||
1260 | It is also important that one class contain all the general and all the | |
1261 | fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS | |
1262 | but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause | |
1263 | allocate_reload_reg() to bypass it causing an abort because the compiler | |
1264 | thinks it doesn't have a spill reg when in fact it does. | |
1265 | ||
7a6cf439 DE |
1266 | v9 also has 4 floating point condition code registers. Since we don't |
1267 | have a class that is the union of FPCC_REGS with either of the others, | |
1268 | it is important that it appear first. Otherwise the compiler will die | |
1269 | trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its | |
c4ce6853 DE |
1270 | constraints. |
1271 | ||
1272 | It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine | |
1273 | may try to use it to hold an SImode value. See register_operand. | |
956d6950 | 1274 | ??? Should %fcc[0123] be handled similarly? |
c4ce6853 | 1275 | */ |
7a6cf439 | 1276 | |
284d86e9 JC |
1277 | enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, |
1278 | EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, | |
7a6cf439 | 1279 | ALL_REGS, LIM_REG_CLASSES }; |
1bb87f28 JW |
1280 | |
1281 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1282 | ||
1283 | /* Give names of register classes as strings for dump file. */ | |
1284 | ||
1285 | #define REG_CLASS_NAMES \ | |
284d86e9 JC |
1286 | { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ |
1287 | "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ | |
1288 | "ALL_REGS" } | |
1bb87f28 JW |
1289 | |
1290 | /* Define which registers fit in which classes. | |
1291 | This is an initializer for a vector of HARD_REG_SET | |
1292 | of length N_REG_CLASSES. */ | |
1293 | ||
7a6cf439 | 1294 | #define REG_CLASS_CONTENTS \ |
284d86e9 | 1295 | {{0, 0, 0, 0}, {0, 0, 0, 0xf}, {0xffff, 0, 0, 0}, \ |
c4ce6853 DE |
1296 | {-1, 0, 0, 0}, {0, -1, 0, 0}, {0, -1, -1, 0}, \ |
1297 | {-1, -1, 0, 0}, {-1, -1, -1, 0}, {-1, -1, -1, 0x1f}} | |
1bb87f28 JW |
1298 | |
1299 | /* The same information, inverted: | |
1300 | Return the class number of the smallest class containing | |
1301 | reg number REGNO. This could be a conditional expression | |
1302 | or could index an array. */ | |
1303 | ||
c4ce6853 DE |
1304 | extern enum reg_class sparc_regno_reg_class[]; |
1305 | ||
1306 | #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] | |
1bb87f28 | 1307 | |
7a6cf439 | 1308 | /* This is the order in which to allocate registers normally. |
51f0e748 JW |
1309 | |
1310 | We put %f0/%f1 last among the float registers, so as to make it more | |
6a4bb1fa | 1311 | likely that a pseudo-register which dies in the float return register |
51f0e748 | 1312 | will get allocated to the float return register, thus saving a move |
4fb4e4b8 | 1313 | instruction at the end of the function. */ |
6afca97d | 1314 | |
7a6cf439 | 1315 | #define REG_ALLOC_ORDER \ |
6afca97d | 1316 | { 8, 9, 10, 11, 12, 13, 2, 3, \ |
7a6cf439 DE |
1317 | 15, 16, 17, 18, 19, 20, 21, 22, \ |
1318 | 23, 24, 25, 26, 27, 28, 29, 31, \ | |
1319 | 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \ | |
1320 | 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ | |
7a6cf439 DE |
1321 | 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ |
1322 | 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ | |
1323 | 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ | |
1324 | 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ | |
4fb4e4b8 DE |
1325 | 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ |
1326 | 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ | |
7a6cf439 | 1327 | 32, 33, /* %f0,%f1 */ \ |
c4ce6853 | 1328 | 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \ |
4b69d2a3 | 1329 | 1, 4, 5, 6, 7, 0, 14, 30} |
1bb87f28 JW |
1330 | |
1331 | /* This is the order in which to allocate registers for | |
1332 | leaf functions. If all registers can fit in the "i" registers, | |
4fb4e4b8 | 1333 | then we have the possibility of having a leaf function. */ |
6afca97d | 1334 | |
7a6cf439 | 1335 | #define REG_LEAF_ALLOC_ORDER \ |
6afca97d | 1336 | { 2, 3, 24, 25, 26, 27, 28, 29, \ |
7a6cf439 DE |
1337 | 15, 8, 9, 10, 11, 12, 13, \ |
1338 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
1339 | 34, 35, 36, 37, 38, 39, \ | |
1340 | 40, 41, 42, 43, 44, 45, 46, 47, \ | |
7a6cf439 DE |
1341 | 48, 49, 50, 51, 52, 53, 54, 55, \ |
1342 | 56, 57, 58, 59, 60, 61, 62, 63, \ | |
1343 | 64, 65, 66, 67, 68, 69, 70, 71, \ | |
1344 | 72, 73, 74, 75, 76, 77, 78, 79, \ | |
4fb4e4b8 DE |
1345 | 80, 81, 82, 83, 84, 85, 86, 87, \ |
1346 | 88, 89, 90, 91, 92, 93, 94, 95, \ | |
7a6cf439 | 1347 | 32, 33, \ |
c4ce6853 | 1348 | 96, 97, 98, 99, 100, \ |
4b69d2a3 | 1349 | 1, 4, 5, 6, 7, 0, 14, 30, 31} |
1bb87f28 JW |
1350 | |
1351 | #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () | |
1352 | ||
5c56efde DE |
1353 | /* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when |
1354 | -mflat is used. Function only_leaf_regs_used will return 0 if a global | |
1355 | register is used and is not permitted in a leaf function. We make %g7 | |
1356 | a global reg if -mflat and voila. Since %g7 is a system register and is | |
1357 | fixed it won't be used by gcc anyway. */ | |
6afca97d | 1358 | |
7a6cf439 DE |
1359 | #define LEAF_REGISTERS \ |
1360 | { 1, 1, 1, 1, 1, 1, 1, 0, \ | |
1361 | 0, 0, 0, 0, 0, 0, 1, 0, \ | |
1362 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1363 | 1, 1, 1, 1, 1, 1, 0, 1, \ | |
1364 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1365 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1366 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1367 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1368 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1369 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1370 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1371 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
c4ce6853 | 1372 | 1, 1, 1, 1, 1} |
1bb87f28 JW |
1373 | |
1374 | extern char leaf_reg_remap[]; | |
1375 | #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) | |
1bb87f28 | 1376 | |
1bb87f28 JW |
1377 | /* The class value for index registers, and the one for base regs. */ |
1378 | #define INDEX_REG_CLASS GENERAL_REGS | |
1379 | #define BASE_REG_CLASS GENERAL_REGS | |
1380 | ||
24b63396 | 1381 | /* Local macro to handle the two v9 classes of FP regs. */ |
24b63396 | 1382 | #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) |
24b63396 | 1383 | |
6afca97d DE |
1384 | /* Get reg_class from a letter such as appears in the machine description. |
1385 | In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the | |
bfd6bc60 | 1386 | .md file for v8 and v9. |
284d86e9 JC |
1387 | 'd' and 'b' are used for single and double precision VIS operations, |
1388 | if TARGET_VIS. | |
1389 | 'h' is used for V8+ 64 bit global and out registers. */ | |
bfd6bc60 JC |
1390 | |
1391 | #define REG_CLASS_FROM_LETTER(C) \ | |
1392 | (TARGET_V9 \ | |
1393 | ? ((C) == 'f' ? FP_REGS \ | |
1394 | : (C) == 'e' ? EXTRA_FP_REGS \ | |
1395 | : (C) == 'c' ? FPCC_REGS \ | |
284d86e9 JC |
1396 | : ((C) == 'd' && TARGET_VIS) ? FP_REGS\ |
1397 | : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\ | |
1398 | : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\ | |
bfd6bc60 JC |
1399 | : NO_REGS) \ |
1400 | : ((C) == 'f' ? FP_REGS \ | |
1401 | : (C) == 'e' ? FP_REGS \ | |
1402 | : (C) == 'c' ? FPCC_REGS \ | |
6afca97d | 1403 | : NO_REGS)) |
1bb87f28 JW |
1404 | |
1405 | /* The letters I, J, K, L and M in a register constraint string | |
1406 | can be used to stand for particular ranges of immediate operands. | |
1407 | This macro defines what the ranges are. | |
1408 | C is the letter, and VALUE is a constant value. | |
1409 | Return 1 if VALUE is in the range specified by C. | |
1410 | ||
18c5947f | 1411 | `I' is used for the range of constants an insn can actually contain. |
1bb87f28 | 1412 | `J' is used for the range which is just zero (since that is R0). |
18c5947f DE |
1413 | `K' is used for constants which can be loaded with a single sethi insn. |
1414 | `L' is used for the range of constants supported by the movcc insns. | |
1415 | `M' is used for the range of constants supported by the movrcc insns. */ | |
1bb87f28 | 1416 | |
1ccfa253 DE |
1417 | #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) |
1418 | #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) | |
1419 | #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) | |
18c5947f DE |
1420 | /* 10 and 11 bit immediates are only used for a few specific insns. |
1421 | SMALL_INT is used throughout the port so we continue to use it. */ | |
1422 | #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) | |
284d86e9 JC |
1423 | /* 13 bit immediate, considering only the low 32 bits */ |
1424 | #define SMALL_INT32(X) (SPARC_SIMM13_P ((int)INTVAL (X) & 0xffffffff)) | |
1ccfa253 DE |
1425 | #define SPARC_SETHI_P(X) \ |
1426 | (((unsigned HOST_WIDE_INT) (X) & ~(unsigned HOST_WIDE_INT) 0xfffffc00) == 0) | |
1bb87f28 JW |
1427 | |
1428 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
18c5947f | 1429 | ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \ |
1bb87f28 | 1430 | : (C) == 'J' ? (VALUE) == 0 \ |
1ccfa253 | 1431 | : (C) == 'K' ? SPARC_SETHI_P (VALUE) \ |
18c5947f DE |
1432 | : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \ |
1433 | : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \ | |
1bb87f28 JW |
1434 | : 0) |
1435 | ||
1436 | /* Similar, but for floating constants, and defining letters G and H. | |
1437 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
1438 | ||
1439 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
96f69de5 | 1440 | ((C) == 'G' ? fp_zero_operand (VALUE) \ |
1bb87f28 JW |
1441 | : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ |
1442 | : 0) | |
1443 | ||
1444 | /* Given an rtx X being reloaded into a reg required to be | |
1445 | in class CLASS, return the class of reg to actually use. | |
1446 | In general this is just CLASS; but on some machines | |
1447 | in some cases it is preferable to use a more restrictive class. */ | |
8947065c RH |
1448 | /* - We can't load constants into FP registers. We can't load any FP |
1449 | constant if an 'E' constraint fails to match it. | |
1450 | - Try and reload integer constants (symbolic or otherwise) back into | |
1451 | registers directly, rather than having them dumped to memory. */ | |
1452 | ||
2b9a9aea JW |
1453 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
1454 | (CONSTANT_P (X) \ | |
8947065c | 1455 | ? ((FP_REG_CLASS_P (CLASS) \ |
2b9a9aea JW |
1456 | || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ |
1457 | && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \ | |
1458 | || HOST_BITS_PER_INT != BITS_PER_WORD))) \ | |
8947065c RH |
1459 | ? NO_REGS \ |
1460 | : (!FP_REG_CLASS_P (CLASS) \ | |
1461 | && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \ | |
1462 | ? GENERAL_REGS \ | |
1463 | : (CLASS)) \ | |
1464 | : (CLASS)) | |
1bb87f28 JW |
1465 | |
1466 | /* Return the register class of a scratch register needed to load IN into | |
1467 | a register of class CLASS in MODE. | |
1468 | ||
e0d80184 | 1469 | We need a temporary when loading/storing a HImode/QImode value |
ae51bd97 JW |
1470 | between memory and the FPU registers. This can happen when combine puts |
1471 | a paradoxical subreg in a float/fix conversion insn. */ | |
1472 | ||
1473 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
e0d80184 DM |
1474 | ((FP_REG_CLASS_P (CLASS) \ |
1475 | && ((MODE) == HImode || (MODE) == QImode) \ | |
24b63396 | 1476 | && (GET_CODE (IN) == MEM \ |
e0d80184 DM |
1477 | || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ |
1478 | && true_regnum (IN) == -1))) \ | |
1479 | ? GENERAL_REGS \ | |
1480 | : (((TARGET_CM_MEDANY \ | |
1481 | && symbolic_operand ((IN), (MODE))) \ | |
1482 | || (TARGET_CM_EMBMEDANY \ | |
1483 | && text_segment_operand ((IN), (MODE)))) \ | |
1484 | && !flag_pic) \ | |
1485 | ? GENERAL_REGS \ | |
1486 | : NO_REGS) | |
ae51bd97 JW |
1487 | |
1488 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
e0d80184 DM |
1489 | ((FP_REG_CLASS_P (CLASS) \ |
1490 | && ((MODE) == HImode || (MODE) == QImode) \ | |
1491 | && (GET_CODE (IN) == MEM \ | |
1492 | || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ | |
1493 | && true_regnum (IN) == -1))) \ | |
1494 | ? GENERAL_REGS \ | |
1495 | : (((TARGET_CM_MEDANY \ | |
1496 | && symbolic_operand ((IN), (MODE))) \ | |
1497 | || (TARGET_CM_EMBMEDANY \ | |
1498 | && text_segment_operand ((IN), (MODE)))) \ | |
1499 | && !flag_pic) \ | |
1500 | ? GENERAL_REGS \ | |
1501 | : NO_REGS) | |
1bb87f28 | 1502 | |
b924cef0 JW |
1503 | /* On SPARC it is not possible to directly move data between |
1504 | GENERAL_REGS and FP_REGS. */ | |
24b63396 JW |
1505 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1506 | (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) | |
b924cef0 | 1507 | |
55be783d JW |
1508 | /* Return the stack location to use for secondary memory needed reloads. |
1509 | We want to use the reserved location just below the frame pointer. | |
1510 | However, we must ensure that there is a frame, so use assign_stack_local | |
1511 | if the frame size is zero. */ | |
fe1f7f24 | 1512 | #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ |
55be783d | 1513 | (get_frame_size () == 0 \ |
fb3eb6f6 | 1514 | ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \ |
284d86e9 | 1515 | : gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, frame_pointer_rtx, \ |
55be783d | 1516 | GEN_INT (STARTING_FRAME_OFFSET)))) |
fe1f7f24 | 1517 | |
9ec36da5 | 1518 | /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9 |
7a6cf439 DE |
1519 | because the movsi and movsf patterns don't handle r/f moves. |
1520 | For v8 we copy the default definition. */ | |
1521 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
6f64bf5f | 1522 | (TARGET_ARCH64 \ |
fb3eb6f6 JW |
1523 | ? (GET_MODE_BITSIZE (MODE) < 32 \ |
1524 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
7a6cf439 | 1525 | : MODE) \ |
fb3eb6f6 JW |
1526 | : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ |
1527 | ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ | |
7a6cf439 DE |
1528 | : MODE)) |
1529 | ||
1bb87f28 JW |
1530 | /* Return the maximum number of consecutive registers |
1531 | needed to represent mode MODE in a register of class CLASS. */ | |
1532 | /* On SPARC, this is the size of MODE in words. */ | |
1533 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
24b63396 | 1534 | (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ |
7a6cf439 | 1535 | : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
1bb87f28 JW |
1536 | \f |
1537 | /* Stack layout; function entry, exit and calling. */ | |
1538 | ||
1539 | /* Define the number of register that can hold parameters. | |
4fb4e4b8 | 1540 | This macro is only used in other macro definitions below and in sparc.c. |
7a6cf439 DE |
1541 | MODE is the mode of the argument. |
1542 | !v9: All args are passed in %o0-%o5. | |
4fb4e4b8 DE |
1543 | v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values. |
1544 | See the description in sparc.c. */ | |
7a6cf439 | 1545 | #define NPARM_REGS(MODE) \ |
4fb4e4b8 DE |
1546 | (TARGET_ARCH64 \ |
1547 | ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \ | |
1548 | : 6) | |
1bb87f28 JW |
1549 | |
1550 | /* Define this if pushing a word on the stack | |
1551 | makes the stack pointer a smaller address. */ | |
1552 | #define STACK_GROWS_DOWNWARD | |
1553 | ||
1554 | /* Define this if the nominal address of the stack frame | |
1555 | is at the high-address end of the local variables; | |
1556 | that is, each additional local variable allocated | |
1557 | goes at a more negative offset in the frame. */ | |
1558 | #define FRAME_GROWS_DOWNWARD | |
1559 | ||
1560 | /* Offset within stack frame to start allocating local variables at. | |
1561 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1562 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1563 | of the first local allocated. */ | |
7238ce3a JW |
1564 | /* This allows space for one TFmode floating point value. */ |
1565 | #define STARTING_FRAME_OFFSET \ | |
6f64bf5f | 1566 | (TARGET_ARCH64 ? (SPARC_STACK_BIAS - 16) \ |
7a6cf439 | 1567 | : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))) |
1bb87f28 JW |
1568 | |
1569 | /* If we generate an insn to push BYTES bytes, | |
1570 | this says how many the stack pointer really advances by. | |
1571 | On SPARC, don't define this because there are no push insns. */ | |
1572 | /* #define PUSH_ROUNDING(BYTES) */ | |
1573 | ||
1574 | /* Offset of first parameter from the argument pointer register value. | |
7a6cf439 DE |
1575 | !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg |
1576 | even if this function isn't going to use it. | |
4fb4e4b8 | 1577 | v9: This is 128 for the ins and locals. */ |
7a6cf439 | 1578 | #define FIRST_PARM_OFFSET(FNDECL) \ |
4fb4e4b8 | 1579 | (TARGET_ARCH64 ? (SPARC_STACK_BIAS + 16 * UNITS_PER_WORD) \ |
7a6cf439 | 1580 | : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)) |
1bb87f28 | 1581 | |
71038426 RH |
1582 | /* Offset from the argument pointer register value to the CFA. */ |
1583 | ||
1584 | #define ARG_POINTER_CFA_OFFSET SPARC_STACK_BIAS | |
1585 | ||
1bb87f28 | 1586 | /* When a parameter is passed in a register, stack space is still |
82d6b402 RH |
1587 | allocated for it. |
1588 | !v9: All 6 possible integer registers have backing store allocated. | |
1589 | v9: Only space for the arguments passed is allocated. */ | |
1590 | /* ??? Ideally, we'd use zero here (as the minimum), but zero has special | |
1591 | meaning to the backend. Further, we need to be able to detect if a | |
1592 | varargs/unprototyped function is called, as they may want to spill more | |
1593 | registers than we've provided space. Ugly, ugly. So for now we retain | |
1594 | all 6 slots even for v9. */ | |
4fb4e4b8 | 1595 | #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) |
1bb87f28 JW |
1596 | |
1597 | /* Keep the stack pointer constant throughout the function. | |
b4ac57ab | 1598 | This is both an optimization and a necessity: longjmp |
1bb87f28 JW |
1599 | doesn't behave itself when the stack pointer moves within |
1600 | the function! */ | |
1601 | #define ACCUMULATE_OUTGOING_ARGS | |
1602 | ||
1603 | /* Value is the number of bytes of arguments automatically | |
1604 | popped when returning from a subroutine call. | |
8b109b37 | 1605 | FUNDECL is the declaration node of the function (as a tree), |
1bb87f28 JW |
1606 | FUNTYPE is the data type of the function (as a tree), |
1607 | or for a library call it is an identifier node for the subroutine name. | |
1608 | SIZE is the number of bytes of arguments passed on the stack. */ | |
1609 | ||
8b109b37 | 1610 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
1bb87f28 | 1611 | |
5b485d2c JW |
1612 | /* Some subroutine macros specific to this machine. |
1613 | When !TARGET_FPU, put float return values in the general registers, | |
1614 | since we don't have any fp registers. */ | |
82d6b402 RH |
1615 | #define BASE_RETURN_VALUE_REG(MODE) \ |
1616 | (TARGET_ARCH64 \ | |
1617 | ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \ | |
7a6cf439 | 1618 | : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)) |
82d6b402 RH |
1619 | |
1620 | #define BASE_OUTGOING_VALUE_REG(MODE) \ | |
1621 | (TARGET_ARCH64 \ | |
1622 | ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \ | |
1623 | : TARGET_FLAT ? 8 : 24) \ | |
7a6cf439 | 1624 | : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \ |
bafb031b | 1625 | : (TARGET_FLAT ? 8 : 24))) |
82d6b402 RH |
1626 | |
1627 | #define BASE_PASSING_ARG_REG(MODE) \ | |
1628 | (TARGET_ARCH64 \ | |
1629 | ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \ | |
6f64bf5f | 1630 | : 8) |
82d6b402 RH |
1631 | |
1632 | /* ??? FIXME -- seems wrong for v9 structure passing... */ | |
1633 | #define BASE_INCOMING_ARG_REG(MODE) \ | |
1634 | (TARGET_ARCH64 \ | |
1635 | ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \ | |
1636 | : TARGET_FLAT ? 8 : 24) \ | |
bafb031b | 1637 | : (TARGET_FLAT ? 8 : 24)) |
1bb87f28 | 1638 | |
92ea370b TW |
1639 | /* Define this macro if the target machine has "register windows". This |
1640 | C expression returns the register number as seen by the called function | |
1641 | corresponding to register number OUT as seen by the calling function. | |
1642 | Return OUT if register number OUT is not an outbound register. */ | |
1643 | ||
1644 | #define INCOMING_REGNO(OUT) \ | |
bafb031b | 1645 | ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) |
92ea370b TW |
1646 | |
1647 | /* Define this macro if the target machine has "register windows". This | |
1648 | C expression returns the register number as seen by the calling function | |
1649 | corresponding to register number IN as seen by the called function. | |
1650 | Return IN if register number IN is not an inbound register. */ | |
1651 | ||
1652 | #define OUTGOING_REGNO(IN) \ | |
bafb031b | 1653 | ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) |
92ea370b | 1654 | |
1bb87f28 JW |
1655 | /* Define how to find the value returned by a function. |
1656 | VALTYPE is the data type of the value (as a tree). | |
1657 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1658 | otherwise, FUNC is 0. */ | |
1659 | ||
1660 | /* On SPARC the value is found in the first "output" register. */ | |
1661 | ||
82d6b402 RH |
1662 | extern struct rtx_def *function_value (); |
1663 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
1664 | function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1) | |
1bb87f28 JW |
1665 | |
1666 | /* But the called function leaves it in the first "input" register. */ | |
1667 | ||
82d6b402 RH |
1668 | #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ |
1669 | function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0) | |
1bb87f28 JW |
1670 | |
1671 | /* Define how to find the value returned by a library function | |
1672 | assuming the value has mode MODE. */ | |
1673 | ||
82d6b402 RH |
1674 | #define LIBCALL_VALUE(MODE) \ |
1675 | function_value (NULL_TREE, (MODE), 1) | |
1bb87f28 JW |
1676 | |
1677 | /* 1 if N is a possible register number for a function value | |
1678 | as seen by the caller. | |
1679 | On SPARC, the first "output" reg is used for integer values, | |
1680 | and the first floating point register is used for floating point values. */ | |
1681 | ||
1682 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) | |
1683 | ||
34aaacec JW |
1684 | /* Define the size of space to allocate for the return value of an |
1685 | untyped_call. */ | |
1686 | ||
1687 | #define APPLY_RESULT_SIZE 16 | |
1688 | ||
1bb87f28 | 1689 | /* 1 if N is a possible register number for function argument passing. |
4fb4e4b8 | 1690 | On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ |
1bb87f28 | 1691 | |
7a6cf439 | 1692 | #define FUNCTION_ARG_REGNO_P(N) \ |
4fb4e4b8 DE |
1693 | (TARGET_ARCH64 \ |
1694 | ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \ | |
1695 | : ((N) >= 8 && (N) <= 13)) | |
1bb87f28 JW |
1696 | \f |
1697 | /* Define a data type for recording info about an argument list | |
1698 | during the scan of that argument list. This data type should | |
1699 | hold all necessary information about the function itself | |
1700 | and about the args processed so far, enough to enable macros | |
1701 | such as FUNCTION_ARG to determine where the next arg should go. | |
1702 | ||
7a6cf439 | 1703 | On SPARC (!v9), this is a single integer, which is a number of words |
1bb87f28 JW |
1704 | of arguments scanned so far (including the invisible argument, |
1705 | if any, which holds the structure-value-address). | |
7a6cf439 DE |
1706 | Thus 7 or more means all following args should go on the stack. |
1707 | ||
4fb4e4b8 | 1708 | For v9, we also need to know whether a prototype is present. */ |
7a6cf439 | 1709 | |
7a6cf439 | 1710 | struct sparc_args { |
4fb4e4b8 DE |
1711 | int words; /* number of words passed so far */ |
1712 | int prototype_p; /* non-zero if a prototype is present */ | |
1713 | int libcall_p; /* non-zero if a library call */ | |
7a6cf439 DE |
1714 | }; |
1715 | #define CUMULATIVE_ARGS struct sparc_args | |
1716 | ||
1bb87f28 JW |
1717 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1718 | for a call to a function whose data type is FNTYPE. | |
4fb4e4b8 | 1719 | For a library call, FNTYPE is 0. */ |
1bb87f28 | 1720 | |
4fb4e4b8 DE |
1721 | extern void init_cumulative_args (); |
1722 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ | |
1723 | init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (INDIRECT)); | |
1bb87f28 JW |
1724 | |
1725 | /* Update the data in CUM to advance over an argument | |
1726 | of mode MODE and data type TYPE. | |
4fb4e4b8 | 1727 | TYPE is null for libcalls where that information may not be available. */ |
7a6cf439 | 1728 | |
4fb4e4b8 DE |
1729 | extern void function_arg_advance (); |
1730 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
1731 | function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED)) | |
1bb87f28 JW |
1732 | |
1733 | /* Determine where to put an argument to a function. | |
1734 | Value is zero to push the argument on the stack, | |
1735 | or a hard register in which to store the argument. | |
1736 | ||
1737 | MODE is the argument's machine mode. | |
1738 | TYPE is the data type of the argument (as a tree). | |
1739 | This is null for libcalls where that information may | |
1740 | not be available. | |
1741 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1742 | the preceding args and about the function being called. | |
1743 | NAMED is nonzero if this argument is a named parameter | |
1744 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1745 | ||
4fb4e4b8 DE |
1746 | extern struct rtx_def *function_arg (); |
1747 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
1748 | function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0) | |
1bb87f28 JW |
1749 | |
1750 | /* Define where a function finds its arguments. | |
1751 | This is different from FUNCTION_ARG because of register windows. */ | |
1752 | ||
4fb4e4b8 DE |
1753 | #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ |
1754 | function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1) | |
1bb87f28 JW |
1755 | |
1756 | /* For an arg passed partly in registers and partly in memory, | |
1757 | this is the number of registers used. | |
4fb4e4b8 DE |
1758 | For args passed entirely in registers or entirely in memory, zero. */ |
1759 | ||
1760 | extern int function_arg_partial_nregs (); | |
1761 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
1762 | function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED)) | |
1763 | ||
1764 | /* A C expression that indicates when an argument must be passed by reference. | |
1765 | If nonzero for an argument, a copy of that argument is made in memory and a | |
1766 | pointer to the argument is passed instead of the argument itself. | |
1767 | The pointer is passed in whatever way is appropriate for passing a pointer | |
1768 | to that type. */ | |
1769 | ||
1770 | extern int function_arg_pass_by_reference (); | |
1771 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ | |
1772 | function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED)) | |
1773 | ||
1774 | /* If defined, a C expression which determines whether, and in which direction, | |
1775 | to pad out an argument with extra space. The value should be of type | |
1776 | `enum direction': either `upward' to pad above the argument, | |
1777 | `downward' to pad below, or `none' to inhibit padding. */ | |
284d86e9 | 1778 | |
4fb4e4b8 DE |
1779 | #define FUNCTION_ARG_PADDING(MODE, TYPE) \ |
1780 | function_arg_padding ((MODE), (TYPE)) | |
1781 | ||
1782 | /* If defined, a C expression that gives the alignment boundary, in bits, | |
1783 | of an argument with the specified mode and type. If it is not defined, | |
1784 | PARM_BOUNDARY is used for all arguments. | |
1785 | For sparc64, objects requiring 16 byte alignment are passed that way. */ | |
1786 | ||
1787 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
1788 | ((TARGET_ARCH64 \ | |
1789 | && (GET_MODE_ALIGNMENT (MODE) == 128 \ | |
1790 | || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \ | |
1791 | ? 128 : PARM_BOUNDARY) | |
7a6cf439 | 1792 | \f |
1bb87f28 JW |
1793 | /* Define the information needed to generate branch and scc insns. This is |
1794 | stored from the compare operation. Note that we can't use "rtx" here | |
1795 | since it hasn't been defined! */ | |
1796 | ||
1797 | extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1; | |
1798 | ||
1799 | /* Define the function that build the compare insn for scc and bcc. */ | |
1800 | ||
1801 | extern struct rtx_def *gen_compare_reg (); | |
7a6cf439 DE |
1802 | |
1803 | /* This function handles all v9 scc insns */ | |
1804 | ||
1805 | extern int gen_v9_scc (); | |
1bb87f28 | 1806 | \f |
4b69d2a3 RS |
1807 | /* Generate the special assembly code needed to tell the assembler whatever |
1808 | it might need to know about the return value of a function. | |
1809 | ||
1810 | For Sparc assemblers, we need to output a .proc pseudo-op which conveys | |
1811 | information to the assembler relating to peephole optimization (done in | |
1812 | the assembler). */ | |
1813 | ||
1814 | #define ASM_DECLARE_RESULT(FILE, RESULT) \ | |
4f70758f | 1815 | fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) |
4b69d2a3 | 1816 | |
1bb87f28 JW |
1817 | /* Output the label for a function definition. */ |
1818 | ||
4b69d2a3 RS |
1819 | #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ |
1820 | do { \ | |
1821 | ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ | |
1822 | ASM_OUTPUT_LABEL (FILE, NAME); \ | |
1823 | } while (0) | |
1bb87f28 | 1824 | |
1cb36a98 RH |
1825 | /* Output the special assembly code needed to tell the assembler some |
1826 | register is used as global register variable. */ | |
1827 | ||
1828 | #ifdef HAVE_AS_REGISTER_PSEUDO_OP | |
1829 | #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ | |
1830 | do { \ | |
1831 | if (TARGET_ARCH64) \ | |
1832 | { \ | |
1833 | int __end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \ | |
1834 | int __reg; \ | |
1835 | extern char sparc_hard_reg_printed[8]; \ | |
1836 | for (__reg = (REGNO); __reg < 8 && __reg < __end; __reg++) \ | |
1837 | if ((__reg & ~1) == 2 || (__reg & ~1) == 6) \ | |
1838 | { \ | |
1839 | if (__reg == (REGNO)) \ | |
1840 | fprintf ((FILE), "\t.register\t%%g%d, %s\n", __reg, (NAME)); \ | |
1841 | else \ | |
1842 | fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ | |
1843 | __reg, __reg - (REGNO), (NAME)); \ | |
1844 | sparc_hard_reg_printed[__reg] = 1; \ | |
1845 | } \ | |
1846 | } \ | |
1847 | } while (0) | |
1848 | #endif | |
1849 | ||
1bb87f28 JW |
1850 | /* This macro generates the assembly code for function entry. |
1851 | FILE is a stdio stream to output the code to. | |
1852 | SIZE is an int: how many units of temporary storage to allocate. | |
1853 | Refer to the array `regs_ever_live' to determine which registers | |
1854 | to save; `regs_ever_live[I]' is nonzero if register number I | |
1855 | is ever used in the function. This macro is responsible for | |
1856 | knowing which registers should not be saved even if used. */ | |
1857 | ||
1858 | /* On SPARC, move-double insns between fpu and cpu need an 8-byte block | |
1859 | of memory. If any fpu reg is used in the function, we allocate | |
1860 | such a block here, at the bottom of the frame, just in case it's needed. | |
1861 | ||
1862 | If this function is a leaf procedure, then we may choose not | |
1863 | to do a "save" insn. The decision about whether or not | |
1864 | to do this is made in regclass.c. */ | |
1865 | ||
bafb031b | 1866 | #define FUNCTION_PROLOGUE(FILE, SIZE) \ |
284d86e9 | 1867 | (TARGET_FLAT ? sparc_flat_output_function_prologue (FILE, (int)SIZE) \ |
54ff41b7 JW |
1868 | : output_function_prologue (FILE, (int)SIZE, \ |
1869 | current_function_uses_only_leaf_regs)) | |
c4ce6853 | 1870 | \f |
1bb87f28 | 1871 | /* Output assembler code to FILE to increment profiler label # LABELNO |
2be15d0f | 1872 | for profiling a function entry. */ |
6f334f44 | 1873 | |
2be15d0f RH |
1874 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
1875 | sparc_function_profiler(FILE, LABELNO) | |
1bb87f28 | 1876 | |
2be15d0f | 1877 | /* Set the name of the mcount function for the system. */ |
88c956eb | 1878 | |
2be15d0f | 1879 | #define MCOUNT_FUNCTION "*mcount" |
88c956eb RK |
1880 | |
1881 | /* The following macro shall output assembler code to FILE | |
2be15d0f | 1882 | to initialize basic-block profiling. */ |
88c956eb | 1883 | |
2be15d0f RH |
1884 | #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \ |
1885 | sparc_function_block_profiler(FILE, BLOCK_OR_LABEL) | |
88c956eb RK |
1886 | |
1887 | /* The following macro shall output assembler code to FILE | |
2be15d0f | 1888 | to increment a counter associated with basic block number BLOCKNO. */ |
88c956eb | 1889 | |
2be15d0f RH |
1890 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ |
1891 | sparc_block_profiler (FILE, BLOCKNO) | |
88c956eb RK |
1892 | |
1893 | /* The following macro shall output assembler code to FILE | |
2be15d0f | 1894 | to indicate a return from function during basic-block profiling. */ |
88c956eb RK |
1895 | |
1896 | #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \ | |
2be15d0f | 1897 | sparc_function_block_profiler_exit(FILE) |
88c956eb RK |
1898 | |
1899 | /* The function `__bb_trace_func' is called in every basic block | |
1900 | and is not allowed to change the machine state. Saving (restoring) | |
1901 | the state can either be done in the BLOCK_PROFILER macro, | |
1902 | before calling function (rsp. after returning from function) | |
1903 | `__bb_trace_func', or it can be done inside the function by | |
1904 | defining the macros: | |
1905 | ||
1906 | MACHINE_STATE_SAVE(ID) | |
1907 | MACHINE_STATE_RESTORE(ID) | |
1908 | ||
1909 | In the latter case care must be taken, that the prologue code | |
1910 | of function `__bb_trace_func' does not already change the | |
1911 | state prior to saving it with MACHINE_STATE_SAVE. | |
1912 | ||
1913 | The parameter `ID' is a string identifying a unique macro use. | |
1914 | ||
1915 | On sparc it is sufficient to save the psw register to memory. | |
1916 | Unfortunately the psw register can be read in supervisor mode only, | |
1917 | so we read only the condition codes by using branch instructions | |
1918 | and hope that this is enough. */ | |
1919 | ||
cb85a2f3 RH |
1920 | #define MACHINE_STATE_SAVE(ID) \ |
1921 | int ms_flags, ms_saveret; \ | |
1922 | asm volatile( \ | |
1923 | "mov %%g0,%0\n\ | |
1924 | be,a LFLGNZ"ID"\n\ | |
1925 | or %0,4,%0\n\ | |
1926 | LFLGNZ"ID":\n\ | |
1927 | bcs,a LFLGNC"ID"\n\ | |
1928 | or %0,1,%0\n\ | |
1929 | LFLGNC"ID":\n\ | |
1930 | bvs,a LFLGNV"ID"\n\ | |
1931 | or %0,2,%0\n\ | |
1932 | LFLGNV"ID":\n\ | |
1933 | bneg,a LFLGNN"ID"\n\ | |
1934 | or %0,8,%0\n\ | |
1935 | LFLGNN"ID":\n\ | |
1936 | mov %%g2,%1" \ | |
1937 | : "=r"(ms_flags), "=r"(ms_saveret)); | |
88c956eb RK |
1938 | |
1939 | /* On sparc MACHINE_STATE_RESTORE restores the psw register from memory. | |
1940 | The psw register can be written in supervisor mode only, | |
1941 | which is true even for simple condition codes. | |
1942 | We use some combination of instructions to produce the | |
1943 | proper condition codes, but some flag combinations can not | |
1944 | be generated in this way. If this happens an unimplemented | |
1945 | instruction will be executed to abort the program. */ | |
1946 | ||
cb85a2f3 RH |
1947 | #define MACHINE_STATE_RESTORE(ID) \ |
1948 | { extern char flgtab[] __asm__("LFLGTAB"ID); \ | |
1949 | int scratch; \ | |
1950 | asm volatile ( \ | |
1951 | "jmpl %2+%1,%%g0\n\ | |
1952 | ! Do part of VC in the delay slot here, as it needs 3 insns.\n\ | |
1953 | addcc 2,%3,%%g0\n\ | |
1954 | LFLGTAB" ID ":\n\ | |
1955 | ! 0\n\ | |
1956 | ba LFLGRET"ID"\n\ | |
1957 | orcc 1,%%g0,%%g0\n\ | |
1958 | ! C\n\ | |
1959 | ba LFLGRET"ID"\n\ | |
1960 | addcc 2,%3,%%g0\n\ | |
1961 | ! V\n\ | |
1962 | unimp\n\ | |
1963 | nop\n\ | |
1964 | ! VC\n\ | |
1965 | ba LFLGRET"ID"\n\ | |
1966 | addxcc %4,%4,%0\n\ | |
1967 | ! Z\n\ | |
1968 | ba LFLGRET"ID"\n\ | |
1969 | subcc %%g0,%%g0,%%g0\n\ | |
1970 | ! ZC\n\ | |
1971 | ba LFLGRET"ID"\n\ | |
1972 | addcc 1,%3,%0\n\ | |
1973 | ! ZVC\n\ | |
1974 | ba LFLGRET"ID"\n\ | |
1975 | addcc %4,%4,%0\n\ | |
1976 | ! N\n\ | |
1977 | ba LFLGRET"ID"\n\ | |
1978 | orcc %%g0,-1,%%g0\n\ | |
1979 | ! NC\n\ | |
1980 | ba LFLGRET"ID"\n\ | |
1981 | addcc %%g0,%3,%%g0\n\ | |
1982 | ! NV\n\ | |
1983 | unimp\n\ | |
1984 | nop\n\ | |
1985 | ! NVC\n\ | |
1986 | unimp\n\ | |
1987 | nop\n\ | |
1988 | ! NZ\n\ | |
1989 | unimp\n\ | |
1990 | nop\n\ | |
1991 | ! NZC\n\ | |
1992 | unimp\n\ | |
1993 | nop\n\ | |
1994 | ! NZV\n\ | |
1995 | unimp\n\ | |
1996 | nop\n\ | |
1997 | ! NZVC\n\ | |
1998 | unimp\n\ | |
1999 | nop\n\ | |
2000 | LFLGRET"ID":\n\ | |
2001 | mov %5,%%g2" \ | |
2002 | : "=r"(scratch) \ | |
2003 | : "r"(ms_flags*8), "r"(flgtab), "r"(-1), \ | |
2004 | "r"(0x80000000), "r"(ms_saveret) \ | |
2005 | : "cc", "%g2"); } | |
c4ce6853 | 2006 | \f |
1bb87f28 JW |
2007 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
2008 | the stack pointer does not matter. The value is tested only in | |
2009 | functions that have frame pointers. | |
2010 | No definition is equivalent to always zero. */ | |
2011 | ||
1bb87f28 JW |
2012 | #define EXIT_IGNORE_STACK \ |
2013 | (get_frame_size () != 0 \ | |
2014 | || current_function_calls_alloca || current_function_outgoing_args_size) | |
2015 | ||
2016 | /* This macro generates the assembly code for function exit, | |
2017 | on machines that need it. If FUNCTION_EPILOGUE is not defined | |
2018 | then individual return instructions are generated for each | |
2019 | return statement. Args are same as for FUNCTION_PROLOGUE. | |
2020 | ||
2021 | The function epilogue should not depend on the current stack pointer! | |
2022 | It should use the frame pointer only. This is mandatory because | |
2023 | of alloca; we also take advantage of it to omit stack adjustments | |
2024 | before returning. */ | |
2025 | ||
bafb031b | 2026 | #define FUNCTION_EPILOGUE(FILE, SIZE) \ |
284d86e9 | 2027 | (TARGET_FLAT ? sparc_flat_output_function_epilogue (FILE, (int)SIZE) \ |
54ff41b7 JW |
2028 | : output_function_epilogue (FILE, (int)SIZE, \ |
2029 | current_function_uses_only_leaf_regs)) | |
1bb87f28 | 2030 | |
bafb031b DE |
2031 | #define DELAY_SLOTS_FOR_EPILOGUE \ |
2032 | (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1) | |
2033 | #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \ | |
2034 | (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \ | |
5b485d2c | 2035 | : eligible_for_epilogue_delay (trial, slots_filled)) |
deeeee8c MS |
2036 | |
2037 | /* Define registers used by the epilogue and return instruction. */ | |
2038 | #define EPILOGUE_USES(REGNO) \ | |
2039 | (!TARGET_FLAT && REGNO == 31) | |
6a4bb1fa | 2040 | \f |
1bb87f28 JW |
2041 | /* Length in units of the trampoline for entering a nested function. */ |
2042 | ||
c6b0465b JC |
2043 | #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) |
2044 | ||
2045 | #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */ | |
1bb87f28 JW |
2046 | |
2047 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
2048 | FNADDR is an RTX for the address of the function's pure code. | |
7a6cf439 | 2049 | CXT is an RTX for the static chain value for the function. */ |
1bb87f28 | 2050 | |
7a6cf439 DE |
2051 | void sparc_initialize_trampoline (); |
2052 | void sparc64_initialize_trampoline (); | |
2053 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
6f64bf5f | 2054 | if (TARGET_ARCH64) \ |
7a6cf439 DE |
2055 | sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \ |
2056 | else \ | |
c6b0465b | 2057 | sparc_initialize_trampoline (TRAMP, FNADDR, CXT) |
6a4bb1fa | 2058 | \f |
648d2ffc | 2059 | /* Generate necessary RTL for __builtin_saveregs(). */ |
4fb4e4b8 | 2060 | |
9a1c7cd7 | 2061 | extern struct rtx_def *sparc_builtin_saveregs (); |
648d2ffc | 2062 | #define EXPAND_BUILTIN_SAVEREGS() sparc_builtin_saveregs () |
953fe179 | 2063 | |
4fb4e4b8 DE |
2064 | /* Define this macro if the location where a function argument is passed |
2065 | depends on whether or not it is a named argument. | |
2066 | ||
2067 | This macro controls how the NAMED argument to FUNCTION_ARG | |
2068 | is set for varargs and stdarg functions. With this macro defined, | |
2069 | the NAMED argument is always true for named arguments, and false for | |
2070 | unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS | |
2071 | is defined, then all arguments are treated as named. Otherwise, all named | |
2072 | arguments except the last are treated as named. | |
2073 | For the v9 we want NAMED to mean what it says it means. */ | |
e5e809f4 JL |
2074 | |
2075 | #define STRICT_ARGUMENT_NAMING TARGET_V9 | |
4fb4e4b8 | 2076 | |
953fe179 JW |
2077 | /* Generate RTL to flush the register windows so as to make arbitrary frames |
2078 | available. */ | |
2079 | #define SETUP_FRAME_ADDRESSES() \ | |
2080 | emit_insn (gen_flush_register_windows ()) | |
2081 | ||
2082 | /* Given an rtx for the address of a frame, | |
2083 | return an rtx for the address of the word in the frame | |
7a6cf439 DE |
2084 | that holds the dynamic chain--the previous frame's address. |
2085 | ??? -mflat support? */ | |
953fe179 | 2086 | #define DYNAMIC_CHAIN_ADDRESS(frame) \ |
284d86e9 | 2087 | gen_rtx_PLUS (Pmode, frame, GEN_INT (14 * UNITS_PER_WORD)) |
953fe179 JW |
2088 | |
2089 | /* The return address isn't on the stack, it is in a register, so we can't | |
2090 | access it from the current frame pointer. We can access it from the | |
2091 | previous frame pointer though by reading a value from the register window | |
2092 | save area. */ | |
2093 | #define RETURN_ADDR_IN_PREVIOUS_FRAME | |
2094 | ||
5b6faa70 | 2095 | /* This is the offset of the return address to the true next instruction to be |
9ad61776 | 2096 | executed for the current function. */ |
6f64bf5f DE |
2097 | #define RETURN_ADDR_OFFSET \ |
2098 | (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct)) | |
5b6faa70 | 2099 | |
953fe179 JW |
2100 | /* The current return address is in %i7. The return address of anything |
2101 | farther back is in the register window save area at [%fp+60]. */ | |
2102 | /* ??? This ignores the fact that the actual return address is +8 for normal | |
2103 | returns, and +12 for structure returns. */ | |
2104 | #define RETURN_ADDR_RTX(count, frame) \ | |
2105 | ((count == -1) \ | |
284d86e9 JC |
2106 | ? gen_rtx_REG (Pmode, 31) \ |
2107 | : gen_rtx_MEM (Pmode, \ | |
5b6faa70 | 2108 | memory_address (Pmode, plus_constant (frame, 15 * UNITS_PER_WORD)))) |
9704efe6 | 2109 | |
d60bee3a DE |
2110 | /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's |
2111 | +12, but always using +8 is close enough for frame unwind purposes. | |
2112 | Actually, just using %o7 is close enough for unwinding, but %o7+8 | |
2113 | is something you can return to. */ | |
2114 | #define INCOMING_RETURN_ADDR_RTX \ | |
284d86e9 | 2115 | gen_rtx_PLUS (word_mode, gen_rtx_REG (word_mode, 15), GEN_INT (8)) |
d60bee3a DE |
2116 | |
2117 | /* The offset from the incoming value of %sp to the top of the stack frame | |
2118 | for the current function. On sparc64, we have to account for the stack | |
2119 | bias if present. */ | |
2120 | #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS | |
2121 | ||
9704efe6 | 2122 | #define DOESNT_NEED_UNWINDER (! TARGET_FLAT) |
1bb87f28 JW |
2123 | \f |
2124 | /* Addressing modes, and classification of registers for them. */ | |
2125 | ||
940da324 JL |
2126 | /* #define HAVE_POST_INCREMENT 0 */ |
2127 | /* #define HAVE_POST_DECREMENT 0 */ | |
1bb87f28 | 2128 | |
940da324 JL |
2129 | /* #define HAVE_PRE_DECREMENT 0 */ |
2130 | /* #define HAVE_PRE_INCREMENT 0 */ | |
1bb87f28 JW |
2131 | |
2132 | /* Macros to check register numbers against specific register classes. */ | |
2133 | ||
2134 | /* These assume that REGNO is a hard or pseudo reg number. | |
2135 | They give nonzero only if REGNO is a hard reg of the suitable class | |
2136 | or a pseudo reg currently allocated to a suitable hard reg. | |
2137 | Since they use reg_renumber, they are safe only once reg_renumber | |
2138 | has been allocated, which happens in local-alloc.c. */ | |
2139 | ||
2140 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
4f70758f | 2141 | ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32) |
1bb87f28 | 2142 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
4f70758f | 2143 | ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32) |
1bb87f28 | 2144 | #define REGNO_OK_FOR_FP_P(REGNO) \ |
4f70758f KG |
2145 | (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ |
2146 | || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) | |
7a6cf439 DE |
2147 | #define REGNO_OK_FOR_CCFP_P(REGNO) \ |
2148 | (TARGET_V9 \ | |
4f70758f KG |
2149 | && (((unsigned) (REGNO) - 96 < (unsigned)4) \ |
2150 | || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) | |
1bb87f28 JW |
2151 | |
2152 | /* Now macros that check whether X is a register and also, | |
2153 | strictly, whether it is in a specified class. | |
2154 | ||
2155 | These macros are specific to the SPARC, and may be used only | |
2156 | in code for printing assembler insns and in conditions for | |
2157 | define_optimization. */ | |
2158 | ||
2159 | /* 1 if X is an fp register. */ | |
2160 | ||
2161 | #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) | |
284d86e9 JC |
2162 | |
2163 | /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */ | |
2164 | #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31)) | |
1bb87f28 JW |
2165 | \f |
2166 | /* Maximum number of registers that can appear in a valid memory address. */ | |
2167 | ||
2168 | #define MAX_REGS_PER_ADDRESS 2 | |
2169 | ||
7aca9b9c JW |
2170 | /* Recognize any constant value that is a valid address. |
2171 | When PIC, we do not accept an address that would require a scratch reg | |
2172 | to load into a register. */ | |
1bb87f28 | 2173 | |
6eff269e BK |
2174 | #define CONSTANT_ADDRESS_P(X) \ |
2175 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
7aca9b9c JW |
2176 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ |
2177 | || (GET_CODE (X) == CONST \ | |
2178 | && ! (flag_pic && pic_address_needs_scratch (X)))) | |
2179 | ||
2180 | /* Define this, so that when PIC, reload won't try to reload invalid | |
2181 | addresses which require two reload registers. */ | |
2182 | ||
2183 | #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X)) | |
1bb87f28 JW |
2184 | |
2185 | /* Nonzero if the constant value X is a legitimate general operand. | |
f952a238 JJ |
2186 | Anything can be made to work except floating point constants. |
2187 | If TARGET_VIS, 0.0 can be made to work as well. */ | |
1bb87f28 | 2188 | |
f952a238 JJ |
2189 | #define LEGITIMATE_CONSTANT_P(X) \ |
2190 | (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || \ | |
2191 | (TARGET_VIS && (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode) && \ | |
2192 | fp_zero_operand (X))) | |
1bb87f28 JW |
2193 | |
2194 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
2195 | and check its validity for a certain class. | |
2196 | We have two alternate definitions for each of them. | |
2197 | The usual definition accepts all pseudo regs; the other rejects | |
2198 | them unless they have been allocated suitable hard regs. | |
2199 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
2200 | ||
2201 | Most source files want to accept pseudo regs in the hope that | |
2202 | they will get allocated to the class that the insn wants them to be in. | |
2203 | Source files for reload pass need to be strict. | |
2204 | After reload, it makes no difference, since pseudo regs have | |
2205 | been eliminated by then. */ | |
2206 | ||
e0d80184 | 2207 | /* Optional extra constraints for this machine. |
1bb87f28 | 2208 | |
e0d80184 DM |
2209 | 'T' handles memory addresses where the alignment is known to |
2210 | be at least 8 bytes. | |
1bb87f28 | 2211 | |
e0d80184 DM |
2212 | `U' handles all pseudo registers or a hard even numbered |
2213 | integer register, needed for ldd/std instructions. */ | |
1bb87f28 JW |
2214 | |
2215 | #ifndef REG_OK_STRICT | |
2216 | ||
2217 | /* Nonzero if X is a hard reg that can be used as an index | |
2218 | or if it is a pseudo reg. */ | |
7a6cf439 | 2219 | #define REG_OK_FOR_INDEX_P(X) \ |
c4ce6853 | 2220 | (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32)) |
1bb87f28 JW |
2221 | /* Nonzero if X is a hard reg that can be used as a base reg |
2222 | or if it is a pseudo reg. */ | |
7a6cf439 | 2223 | #define REG_OK_FOR_BASE_P(X) \ |
c4ce6853 | 2224 | (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32)) |
7a6cf439 DE |
2225 | |
2226 | /* 'T', 'U' are for aligned memory loads which aren't needed for v9. */ | |
1bb87f28 JW |
2227 | |
2228 | #define EXTRA_CONSTRAINT(OP, C) \ | |
e0d80184 DM |
2229 | ((! TARGET_ARCH64 && (C) == 'T') \ |
2230 | ? (mem_min_alignment (OP, 8)) \ | |
2231 | : ((! TARGET_ARCH64 && (C) == 'U') \ | |
2232 | ? (register_ok_for_ldd (OP)) \ | |
2233 | : 0)) | |
19858600 | 2234 | |
1bb87f28 JW |
2235 | #else |
2236 | ||
2237 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
2238 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
2239 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
2240 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
2241 | ||
2242 | #define EXTRA_CONSTRAINT(OP, C) \ | |
e0d80184 DM |
2243 | ((! TARGET_ARCH64 && (C) == 'T') \ |
2244 | ? mem_min_alignment (OP, 8) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \ | |
2245 | : ((! TARGET_ARCH64 && (C) == 'U') \ | |
2246 | ? (GET_CODE (OP) == REG \ | |
2247 | && (REGNO (OP) < FIRST_PSEUDO_REGISTER \ | |
2248 | || reg_renumber[REGNO (OP)] >= 0) \ | |
2249 | && register_ok_for_ldd (OP)) \ | |
2250 | : 0)) | |
1bb87f28 JW |
2251 | #endif |
2252 | \f | |
1cb36a98 RH |
2253 | /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ |
2254 | ||
2255 | #ifdef HAVE_AS_OFFSETABLE_LO10 | |
2256 | #define USE_AS_OFFSETABLE_LO10 1 | |
2257 | #else | |
2258 | #define USE_AS_OFFSETABLE_LO10 0 | |
2259 | #endif | |
2260 | \f | |
1bb87f28 JW |
2261 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
2262 | that is a valid memory address for an instruction. | |
2263 | The MODE argument is the machine mode for the MEM expression | |
2264 | that wants to use this address. | |
2265 | ||
2266 | On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT | |
2267 | ordinarily. This changes a bit when generating PIC. | |
2268 | ||
2269 | If you change this, execute "rm explow.o recog.o reload.o". */ | |
2270 | ||
bec2e359 JW |
2271 | #define RTX_OK_FOR_BASE_P(X) \ |
2272 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
2273 | || (GET_CODE (X) == SUBREG \ | |
2274 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
2275 | && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) | |
2276 | ||
2277 | #define RTX_OK_FOR_INDEX_P(X) \ | |
2278 | ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ | |
2279 | || (GET_CODE (X) == SUBREG \ | |
2280 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
2281 | && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) | |
2282 | ||
2283 | #define RTX_OK_FOR_OFFSET_P(X) \ | |
2284 | (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000) | |
1cb36a98 RH |
2285 | |
2286 | #define RTX_OK_FOR_OLO10_P(X) \ | |
2287 | (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8) | |
bec2e359 | 2288 | |
1bb87f28 | 2289 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
bec2e359 JW |
2290 | { if (RTX_OK_FOR_BASE_P (X)) \ |
2291 | goto ADDR; \ | |
1bb87f28 JW |
2292 | else if (GET_CODE (X) == PLUS) \ |
2293 | { \ | |
bec2e359 JW |
2294 | register rtx op0 = XEXP (X, 0); \ |
2295 | register rtx op1 = XEXP (X, 1); \ | |
2296 | if (flag_pic && op0 == pic_offset_table_rtx) \ | |
1bb87f28 | 2297 | { \ |
bec2e359 | 2298 | if (RTX_OK_FOR_BASE_P (op1)) \ |
1bb87f28 JW |
2299 | goto ADDR; \ |
2300 | else if (flag_pic == 1 \ | |
bec2e359 JW |
2301 | && GET_CODE (op1) != REG \ |
2302 | && GET_CODE (op1) != LO_SUM \ | |
7aca9b9c JW |
2303 | && GET_CODE (op1) != MEM \ |
2304 | && (GET_CODE (op1) != CONST_INT \ | |
2305 | || SMALL_INT (op1))) \ | |
1bb87f28 JW |
2306 | goto ADDR; \ |
2307 | } \ | |
bec2e359 | 2308 | else if (RTX_OK_FOR_BASE_P (op0)) \ |
1bb87f28 | 2309 | { \ |
54e7fb26 | 2310 | if ((RTX_OK_FOR_INDEX_P (op1) \ |
d0ae1ce3 VM |
2311 | /* We prohibit REG + REG for TFmode when \ |
2312 | there are no instructions which accept \ | |
2313 | REG+REG instructions. We do this \ | |
2314 | because REG+REG is not an offsetable \ | |
2315 | address. If we get the situation \ | |
2316 | in reload where source and destination \ | |
2317 | of a movtf pattern are both MEMs with \ | |
2318 | REG+REG address, then only one of them \ | |
2319 | gets converted to an offsetable \ | |
2320 | address. */ \ | |
2321 | && (MODE != TFmode \ | |
2322 | || (TARGET_FPU && TARGET_ARCH64 \ | |
54e7fb26 VM |
2323 | && TARGET_V9 \ |
2324 | && TARGET_HARD_QUAD))) \ | |
bec2e359 | 2325 | || RTX_OK_FOR_OFFSET_P (op1)) \ |
1bb87f28 JW |
2326 | goto ADDR; \ |
2327 | } \ | |
bec2e359 | 2328 | else if (RTX_OK_FOR_BASE_P (op1)) \ |
1bb87f28 | 2329 | { \ |
54e7fb26 | 2330 | if ((RTX_OK_FOR_INDEX_P (op0) \ |
d0ae1ce3 VM |
2331 | /* See the previous comment. */ \ |
2332 | && (MODE != TFmode \ | |
2333 | || (TARGET_FPU && TARGET_ARCH64 \ | |
54e7fb26 VM |
2334 | && TARGET_V9 \ |
2335 | && TARGET_HARD_QUAD))) \ | |
bec2e359 | 2336 | || RTX_OK_FOR_OFFSET_P (op0)) \ |
1bb87f28 JW |
2337 | goto ADDR; \ |
2338 | } \ | |
1cb36a98 RH |
2339 | else if (USE_AS_OFFSETABLE_LO10 \ |
2340 | && GET_CODE (op0) == LO_SUM \ | |
2341 | && TARGET_ARCH64 \ | |
2342 | && ! TARGET_CM_MEDMID \ | |
2343 | && RTX_OK_FOR_OLO10_P (op1)) \ | |
2344 | { \ | |
2345 | register rtx op00 = XEXP (op0, 0); \ | |
2346 | register rtx op01 = XEXP (op0, 1); \ | |
2347 | if (RTX_OK_FOR_BASE_P (op00) \ | |
2348 | && CONSTANT_P (op01)) \ | |
2349 | goto ADDR; \ | |
2350 | } \ | |
2351 | else if (USE_AS_OFFSETABLE_LO10 \ | |
2352 | && GET_CODE (op1) == LO_SUM \ | |
2353 | && TARGET_ARCH64 \ | |
2354 | && ! TARGET_CM_MEDMID \ | |
2355 | && RTX_OK_FOR_OLO10_P (op0)) \ | |
2356 | { \ | |
2357 | register rtx op10 = XEXP (op1, 0); \ | |
2358 | register rtx op11 = XEXP (op1, 1); \ | |
2359 | if (RTX_OK_FOR_BASE_P (op10) \ | |
2360 | && CONSTANT_P (op11)) \ | |
2361 | goto ADDR; \ | |
2362 | } \ | |
1bb87f28 | 2363 | } \ |
bec2e359 JW |
2364 | else if (GET_CODE (X) == LO_SUM) \ |
2365 | { \ | |
2366 | register rtx op0 = XEXP (X, 0); \ | |
2367 | register rtx op1 = XEXP (X, 1); \ | |
2368 | if (RTX_OK_FOR_BASE_P (op0) \ | |
2f0da906 JW |
2369 | && CONSTANT_P (op1) \ |
2370 | /* We can't allow TFmode, because an offset \ | |
2371 | greater than or equal to the alignment (8) \ | |
e0d80184 DM |
2372 | may cause the LO_SUM to overflow if !v9. */\ |
2373 | && (MODE != TFmode || TARGET_V9)) \ | |
bec2e359 JW |
2374 | goto ADDR; \ |
2375 | } \ | |
1bb87f28 JW |
2376 | else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \ |
2377 | goto ADDR; \ | |
2378 | } | |
2379 | \f | |
2380 | /* Try machine-dependent ways of modifying an illegitimate address | |
2381 | to be legitimate. If we find one, return the new, valid address. | |
2382 | This macro is used in only one place: `memory_address' in explow.c. | |
2383 | ||
2384 | OLDX is the address as it was before break_out_memory_refs was called. | |
2385 | In some cases it is useful to look at this to decide what needs to be done. | |
2386 | ||
2387 | MODE and WIN are passed so that this macro can use | |
2388 | GO_IF_LEGITIMATE_ADDRESS. | |
2389 | ||
2390 | It is always safe for this macro to do nothing. It exists to recognize | |
2391 | opportunities to optimize the output. */ | |
2392 | ||
2393 | /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ | |
2394 | extern struct rtx_def *legitimize_pic_address (); | |
2395 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
2396 | { rtx sparc_x = (X); \ | |
2397 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ | |
284d86e9 | 2398 | (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \ |
a015279e | 2399 | force_operand (XEXP (X, 0), NULL_RTX)); \ |
1bb87f28 | 2400 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ |
284d86e9 | 2401 | (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \ |
a015279e | 2402 | force_operand (XEXP (X, 1), NULL_RTX)); \ |
1bb87f28 | 2403 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \ |
284d86e9 | 2404 | (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\ |
1bb87f28 JW |
2405 | XEXP (X, 1)); \ |
2406 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \ | |
284d86e9 | 2407 | (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \ |
a015279e | 2408 | force_operand (XEXP (X, 1), NULL_RTX)); \ |
1bb87f28 JW |
2409 | if (sparc_x != (X) && memory_address_p (MODE, X)) \ |
2410 | goto WIN; \ | |
7aca9b9c | 2411 | if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \ |
1bb87f28 | 2412 | else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ |
284d86e9 | 2413 | (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \ |
1bb87f28 JW |
2414 | copy_to_mode_reg (Pmode, XEXP (X, 1))); \ |
2415 | else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ | |
284d86e9 | 2416 | (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \ |
1bb87f28 JW |
2417 | copy_to_mode_reg (Pmode, XEXP (X, 0))); \ |
2418 | else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ | |
2419 | || GET_CODE (X) == LABEL_REF) \ | |
e0d80184 | 2420 | (X) = copy_to_suggested_reg (X, NULL_RTX, Pmode); \ |
1bb87f28 JW |
2421 | if (memory_address_p (MODE, X)) \ |
2422 | goto WIN; } | |
2423 | ||
8947065c RH |
2424 | /* Try a machine-dependent way of reloading an illegitimate address |
2425 | operand. If we find one, push the reload and jump to WIN. This | |
2426 | macro is used in only one place: `find_reloads_address' in reload.c. | |
2427 | ||
2428 | For Sparc 32, we wish to handle addresses by splitting them into | |
2429 | HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference. | |
1256ed02 JL |
2430 | This cuts the number of extra insns by one. |
2431 | ||
2432 | Do nothing when generating PIC code and the address is a | |
2433 | symbolic operand or requires a scratch register. */ | |
2434 | ||
8947065c RH |
2435 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
2436 | do { \ | |
2437 | /* Decompose SImode constants into hi+lo_sum. We do have to \ | |
2438 | rerecognize what we produce, so be careful. */ \ | |
2439 | if (CONSTANT_P (X) \ | |
1e75bc34 | 2440 | && (MODE != TFmode || TARGET_V9) \ |
8947065c | 2441 | && GET_MODE (X) == SImode \ |
1256ed02 JL |
2442 | && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \ |
2443 | && ! (flag_pic \ | |
78eca9f2 JL |
2444 | && (symbolic_operand (X, Pmode) \ |
2445 | || pic_address_needs_scratch (X)))) \ | |
8947065c RH |
2446 | { \ |
2447 | X = gen_rtx_LO_SUM (GET_MODE (X), \ | |
2448 | gen_rtx_HIGH (GET_MODE (X), X), X); \ | |
2449 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \ | |
2450 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ | |
2451 | OPNUM, TYPE); \ | |
2452 | goto WIN; \ | |
2453 | } \ | |
2454 | /* ??? 64-bit reloads. */ \ | |
2455 | } while (0) | |
2456 | ||
1bb87f28 JW |
2457 | /* Go to LABEL if ADDR (a legitimate address expression) |
2458 | has an effect that depends on the machine mode it is used for. | |
2459 | On the SPARC this is never true. */ | |
2460 | ||
2461 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) | |
7a6cf439 DE |
2462 | |
2463 | /* If we are referencing a function make the SYMBOL_REF special. | |
a0a301fc DE |
2464 | In the Embedded Medium/Anywhere code model, %g4 points to the data segment |
2465 | so we must not add it to function addresses. */ | |
7a6cf439 DE |
2466 | |
2467 | #define ENCODE_SECTION_INFO(DECL) \ | |
2468 | do { \ | |
a0a301fc | 2469 | if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \ |
7a6cf439 DE |
2470 | SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \ |
2471 | } while (0) | |
1bb87f28 JW |
2472 | \f |
2473 | /* Specify the machine mode that this machine uses | |
2474 | for the index in the tablejump instruction. */ | |
67cb8900 JJ |
2475 | /* If we ever implement any of the full models (such as CM_FULLANY), |
2476 | this has to be DImode in that case */ | |
d1accaa3 | 2477 | #ifdef HAVE_GAS_SUBSECTION_ORDERING |
67cb8900 JJ |
2478 | #define CASE_VECTOR_MODE \ |
2479 | (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) | |
d1accaa3 JJ |
2480 | #else |
2481 | /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise | |
2482 | we have to sign extend which slows things down. */ | |
2483 | #define CASE_VECTOR_MODE \ | |
2484 | (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) | |
2485 | #endif | |
1bb87f28 | 2486 | |
18543a22 ILT |
2487 | /* Define as C expression which evaluates to nonzero if the tablejump |
2488 | instruction expects the table to contain offsets from the address of the | |
2489 | table. | |
2490 | Do not define this if the table should contain absolute addresses. */ | |
2491 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ | |
1bb87f28 JW |
2492 | |
2493 | /* Specify the tree operation to be used to convert reals to integers. */ | |
2494 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
2495 | ||
2496 | /* This is the kind of divide that is easiest to do in the general case. */ | |
2497 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
2498 | ||
2499 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
2500 | #define DEFAULT_SIGNED_CHAR 1 | |
2501 | ||
2502 | /* Max number of bytes we can move from memory to memory | |
2503 | in one reasonably fast instruction. */ | |
2eef2ef1 | 2504 | #define MOVE_MAX 8 |
1bb87f28 | 2505 | |
0fb5a69e | 2506 | #if 0 /* Sun 4 has matherr, so this is no good. */ |
24e2a2bf RS |
2507 | /* This is the value of the error code EDOM for this machine, |
2508 | used by the sqrt instruction. */ | |
2509 | #define TARGET_EDOM 33 | |
2510 | ||
2511 | /* This is how to refer to the variable errno. */ | |
2512 | #define GEN_ERRNO_RTX \ | |
284d86e9 | 2513 | gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno")) |
0fb5a69e | 2514 | #endif /* 0 */ |
24e2a2bf | 2515 | |
9a63901f RK |
2516 | /* Define if operations between registers always perform the operation |
2517 | on the full register even if a narrower mode is specified. */ | |
2518 | #define WORD_REGISTER_OPERATIONS | |
2519 | ||
2520 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
2521 | will either zero-extend or sign-extend. The value of this macro should | |
2522 | be the code that says which one of the two operations is implicitly | |
2523 | done, NIL if none. */ | |
2524 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
1bb87f28 JW |
2525 | |
2526 | /* Nonzero if access to memory by bytes is slow and undesirable. | |
2527 | For RISC chips, it means that access to memory by bytes is no | |
2528 | better than access by words when possible, so grab a whole word | |
2529 | and maybe make use of that. */ | |
2530 | #define SLOW_BYTE_ACCESS 1 | |
2531 | ||
2532 | /* We assume that the store-condition-codes instructions store 0 for false | |
2533 | and some other value for true. This is the value stored for true. */ | |
2534 | ||
2535 | #define STORE_FLAG_VALUE 1 | |
2536 | ||
2537 | /* When a prototype says `char' or `short', really pass an `int'. */ | |
cb560352 | 2538 | #define PROMOTE_PROTOTYPES (TARGET_ARCH32) |
1bb87f28 | 2539 | |
d969caf8 RK |
2540 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
2541 | few bits. */ | |
2542 | #define SHIFT_COUNT_TRUNCATED 1 | |
1bb87f28 JW |
2543 | |
2544 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
2545 | is done just by pretending it is already truncated. */ | |
2546 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2547 | ||
2548 | /* Specify the machine mode that pointers have. | |
2549 | After generation of rtl, the compiler makes no further distinction | |
2550 | between pointers and any other objects of this machine mode. */ | |
7a6cf439 | 2551 | #define Pmode (TARGET_PTR64 ? DImode : SImode) |
1bb87f28 | 2552 | |
b4ac57ab RS |
2553 | /* Generate calls to memcpy, memcmp and memset. */ |
2554 | #define TARGET_MEM_FUNCTIONS | |
2555 | ||
1bb87f28 JW |
2556 | /* Add any extra modes needed to represent the condition code. |
2557 | ||
2558 | On the Sparc, we have a "no-overflow" mode which is used when an add or | |
2559 | subtract insn is used to set the condition code. Different branches are | |
2560 | used in this case for some operations. | |
2561 | ||
4d449554 JW |
2562 | We also have two modes to indicate that the relevant condition code is |
2563 | in the floating-point condition code register. One for comparisons which | |
2564 | will generate an exception if the result is unordered (CCFPEmode) and | |
c4ce6853 | 2565 | one for comparisons which will never trap (CCFPmode). |
7a6cf439 DE |
2566 | |
2567 | CCXmode and CCX_NOOVmode are only used by v9. */ | |
2568 | ||
2569 | #define EXTRA_CC_MODES CCXmode, CC_NOOVmode, CCX_NOOVmode, CCFPmode, CCFPEmode | |
1bb87f28 JW |
2570 | |
2571 | /* Define the names for the modes specified above. */ | |
7a6cf439 DE |
2572 | |
2573 | #define EXTRA_CC_NAMES "CCX", "CC_NOOV", "CCX_NOOV", "CCFP", "CCFPE" | |
1bb87f28 JW |
2574 | |
2575 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
4d449554 JW |
2576 | return the mode to be used for the comparison. For floating-point, |
2577 | CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a | |
922bd191 JW |
2578 | PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special |
2579 | processing is needed. */ | |
679655e6 | 2580 | #define SELECT_CC_MODE(OP,X,Y) \ |
4d449554 | 2581 | (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ |
922bd191 JW |
2582 | ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ |
2583 | : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ | |
2584 | || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \ | |
6f64bf5f | 2585 | ? (TARGET_ARCH64 && GET_MODE (X) == DImode ? CCX_NOOVmode : CC_NOOVmode) \ |
284d86e9 | 2586 | : ((TARGET_ARCH64 || TARGET_V8PLUS) && GET_MODE (X) == DImode ? CCXmode : CCmode))) |
1bb87f28 | 2587 | |
b331b745 RK |
2588 | /* Return non-zero if SELECT_CC_MODE will never return MODE for a |
2589 | floating point inequality comparison. */ | |
2590 | ||
2591 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) | |
2592 | ||
1bb87f28 JW |
2593 | /* A function address in a call instruction |
2594 | is a byte address (for indexing purposes) | |
2595 | so give the MEM rtx a byte's mode. */ | |
2596 | #define FUNCTION_MODE SImode | |
2597 | ||
2598 | /* Define this if addresses of constant functions | |
2599 | shouldn't be put through pseudo regs where they can be cse'd. | |
2600 | Desirable on machines where ordinary constants are expensive | |
2601 | but a CALL with constant address is cheap. */ | |
2602 | #define NO_FUNCTION_CSE | |
2603 | ||
2604 | /* alloca should avoid clobbering the old register save area. */ | |
2605 | #define SETJMP_VIA_SAVE_AREA | |
2606 | ||
2607 | /* Define subroutines to call to handle multiply and divide. | |
2608 | Use the subroutines that Sun's library provides. | |
2609 | The `*' prevents an underscore from being prepended by the compiler. */ | |
2610 | ||
2611 | #define DIVSI3_LIBCALL "*.div" | |
2612 | #define UDIVSI3_LIBCALL "*.udiv" | |
2613 | #define MODSI3_LIBCALL "*.rem" | |
2614 | #define UMODSI3_LIBCALL "*.urem" | |
2615 | /* .umul is a little faster than .mul. */ | |
2616 | #define MULSI3_LIBCALL "*.umul" | |
2617 | ||
8248e2bc | 2618 | /* Define library calls for quad FP operations. These are all part of the |
d559a4db DM |
2619 | SPARC ABI. |
2620 | ??? ARCH64 still does not work as the _Qp_* routines take pointers. */ | |
2621 | #define ADDTF3_LIBCALL (TARGET_ARCH64 ? "_Qp_add" : "_Q_add") | |
2622 | #define SUBTF3_LIBCALL (TARGET_ARCH64 ? "_Qp_sub" : "_Q_sub") | |
2623 | #define NEGTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_neg" : "_Q_neg") | |
2624 | #define MULTF3_LIBCALL (TARGET_ARCH64 ? "_Qp_mul" : "_Q_mul") | |
2625 | #define DIVTF3_LIBCALL (TARGET_ARCH64 ? "_Qp_div" : "_Q_div") | |
2626 | #define FLOATSITF2_LIBCALL (TARGET_ARCH64 ? "_Qp_itoq" : "_Q_itoq") | |
2627 | #define FIX_TRUNCTFSI2_LIBCALL (TARGET_ARCH64 ? "_Qp_qtoi" : "_Q_qtoi") | |
2628 | #define FIXUNS_TRUNCTFSI2_LIBCALL (TARGET_ARCH64 ? "_Qp_qtoui" : "_Q_qtou") | |
2629 | #define EXTENDSFTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_stoq" : "_Q_stoq") | |
2630 | #define TRUNCTFSF2_LIBCALL (TARGET_ARCH64 ? "_Qp_qtos" : "_Q_qtos") | |
2631 | #define EXTENDDFTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_dtoq" : "_Q_dtoq") | |
2632 | #define TRUNCTFDF2_LIBCALL (TARGET_ARCH64 ? "_Qp_qtod" : "_Q_qtod") | |
2633 | #define EQTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq") | |
2634 | #define NETF2_LIBCALL (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne") | |
2635 | #define GTTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt") | |
2636 | #define GETF2_LIBCALL (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge") | |
2637 | #define LTTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt") | |
2638 | #define LETF2_LIBCALL (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle") | |
8248e2bc | 2639 | |
78e9b5df JW |
2640 | /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because |
2641 | with soft-float, the SFmode and DFmode sqrt instructions will be absent, | |
2642 | and the compiler will notice and try to use the TFmode sqrt instruction | |
2643 | for calls to the builtin function sqrt, but this fails. */ | |
27da6752 JW |
2644 | #define INIT_TARGET_OPTABS \ |
2645 | do { \ | |
27da6752 | 2646 | add_optab->handlers[(int) TFmode].libfunc \ |
284d86e9 | 2647 | = gen_rtx_SYMBOL_REF (Pmode, ADDTF3_LIBCALL); \ |
27da6752 | 2648 | sub_optab->handlers[(int) TFmode].libfunc \ |
284d86e9 | 2649 | = gen_rtx_SYMBOL_REF (Pmode, SUBTF3_LIBCALL); \ |
27da6752 | 2650 | neg_optab->handlers[(int) TFmode].libfunc \ |
284d86e9 | 2651 | = gen_rtx_SYMBOL_REF (Pmode, NEGTF2_LIBCALL); \ |
27da6752 | 2652 | smul_optab->handlers[(int) TFmode].libfunc \ |
284d86e9 | 2653 | = gen_rtx_SYMBOL_REF (Pmode, MULTF3_LIBCALL); \ |
27da6752 | 2654 | flodiv_optab->handlers[(int) TFmode].libfunc \ |
284d86e9 JC |
2655 | = gen_rtx_SYMBOL_REF (Pmode, DIVTF3_LIBCALL); \ |
2656 | eqtf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EQTF2_LIBCALL); \ | |
2657 | netf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, NETF2_LIBCALL); \ | |
2658 | gttf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, GTTF2_LIBCALL); \ | |
2659 | getf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, GETF2_LIBCALL); \ | |
2660 | lttf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, LTTF2_LIBCALL); \ | |
2661 | letf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, LETF2_LIBCALL); \ | |
2662 | trunctfsf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, TRUNCTFSF2_LIBCALL); \ | |
2663 | trunctfdf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, TRUNCTFDF2_LIBCALL); \ | |
2664 | extendsftf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EXTENDSFTF2_LIBCALL); \ | |
2665 | extenddftf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EXTENDDFTF2_LIBCALL); \ | |
2666 | floatsitf_libfunc = gen_rtx_SYMBOL_REF (Pmode, FLOATSITF2_LIBCALL); \ | |
2667 | fixtfsi_libfunc = gen_rtx_SYMBOL_REF (Pmode, FIX_TRUNCTFSI2_LIBCALL); \ | |
27da6752 | 2668 | fixunstfsi_libfunc \ |
284d86e9 | 2669 | = gen_rtx_SYMBOL_REF (Pmode, FIXUNS_TRUNCTFSI2_LIBCALL); \ |
27da6752 JW |
2670 | if (TARGET_FPU) \ |
2671 | sqrt_optab->handlers[(int) TFmode].libfunc \ | |
284d86e9 | 2672 | = gen_rtx_SYMBOL_REF (Pmode, "_Q_sqrt"); \ |
47428190 | 2673 | INIT_SUBTARGET_OPTABS; \ |
78e9b5df JW |
2674 | } while (0) |
2675 | ||
2676 | /* This is meant to be redefined in the host dependent files */ | |
2677 | #define INIT_SUBTARGET_OPTABS | |
2678 | ||
1bb87f28 JW |
2679 | /* Compute the cost of computing a constant rtl expression RTX |
2680 | whose rtx-code is CODE. The body of this macro is a portion | |
2681 | of a switch statement. If the code is computed here, | |
2682 | return it with a return statement. Otherwise, break from the switch. */ | |
2683 | ||
3bb22aee | 2684 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ |
1bb87f28 | 2685 | case CONST_INT: \ |
1bb87f28 | 2686 | if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \ |
5b485d2c | 2687 | return 0; \ |
1bb87f28 JW |
2688 | case HIGH: \ |
2689 | return 2; \ | |
2690 | case CONST: \ | |
2691 | case LABEL_REF: \ | |
2692 | case SYMBOL_REF: \ | |
2693 | return 4; \ | |
2694 | case CONST_DOUBLE: \ | |
2695 | if (GET_MODE (RTX) == DImode) \ | |
2696 | if ((XINT (RTX, 3) == 0 \ | |
2697 | && (unsigned) XINT (RTX, 2) < 0x1000) \ | |
2698 | || (XINT (RTX, 3) == -1 \ | |
2699 | && XINT (RTX, 2) < 0 \ | |
2700 | && XINT (RTX, 2) >= -0x1000)) \ | |
5b485d2c | 2701 | return 0; \ |
1bb87f28 JW |
2702 | return 8; |
2703 | ||
a0a74fda | 2704 | #define ADDRESS_COST(RTX) 1 |
1bb87f28 JW |
2705 | |
2706 | /* Compute extra cost of moving data between one register class | |
bfd6bc60 | 2707 | and another. */ |
284d86e9 | 2708 | #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS) |
bfd6bc60 | 2709 | #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ |
284d86e9 JC |
2710 | (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \ |
2711 | || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \ | |
bfd6bc60 | 2712 | || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \ |
284d86e9 | 2713 | ? (sparc_cpu == PROCESSOR_ULTRASPARC ? 12 : 6) : 2) |
1bb87f28 JW |
2714 | |
2715 | /* Provide the costs of a rtl expression. This is in the body of a | |
2716 | switch on CODE. The purpose for the cost of MULT is to encourage | |
2717 | `synth_mult' to find a synthetic multiply when reasonable. | |
2718 | ||
2719 | If we need more than 12 insns to do a multiply, then go out-of-line, | |
2720 | since the call overhead will be < 10% of the cost of the multiply. */ | |
2721 | ||
3bb22aee | 2722 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
1bb87f28 | 2723 | case MULT: \ |
3bc8b61e DM |
2724 | if (sparc_cpu == PROCESSOR_ULTRASPARC) \ |
2725 | return (GET_MODE (X) == DImode ? \ | |
2726 | COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); \ | |
bfd6bc60 | 2727 | return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \ |
1bb87f28 JW |
2728 | case DIV: \ |
2729 | case UDIV: \ | |
2730 | case MOD: \ | |
2731 | case UMOD: \ | |
3bc8b61e DM |
2732 | if (sparc_cpu == PROCESSOR_ULTRASPARC) \ |
2733 | return (GET_MODE (X) == DImode ? \ | |
2734 | COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); \ | |
5b485d2c JW |
2735 | return COSTS_N_INSNS (25); \ |
2736 | /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\ | |
1bb87f28 JW |
2737 | so that cse will favor the latter. */ \ |
2738 | case FLOAT: \ | |
5b485d2c | 2739 | case FIX: \ |
1bb87f28 JW |
2740 | return 19; |
2741 | ||
bfd6bc60 JC |
2742 | #define ISSUE_RATE sparc_issue_rate() |
2743 | ||
bef8d8c7 | 2744 | /* Adjust the cost of dependencies. */ |
8947065c RH |
2745 | #define ADJUST_COST(INSN,LINK,DEP,COST) \ |
2746 | sparc_adjust_cost(INSN, LINK, DEP, COST) | |
bef8d8c7 | 2747 | |
3bc8b61e DM |
2748 | extern void ultrasparc_sched_reorder (); |
2749 | extern void ultrasparc_sched_init (); | |
2750 | extern int ultrasparc_variable_issue (); | |
2751 | ||
2752 | #define MD_SCHED_INIT(DUMP, SCHED_VERBOSE) \ | |
2753 | if (sparc_cpu == PROCESSOR_ULTRASPARC) \ | |
2754 | ultrasparc_sched_init (DUMP, SCHED_VERBOSE) | |
2755 | ||
197043f5 RH |
2756 | #define MD_SCHED_REORDER(DUMP, SCHED_VERBOSE, READY, N_READY, CLOCK, CIM) \ |
2757 | do { \ | |
3bc8b61e | 2758 | if (sparc_cpu == PROCESSOR_ULTRASPARC) \ |
197043f5 RH |
2759 | ultrasparc_sched_reorder (DUMP, SCHED_VERBOSE, READY, N_READY); \ |
2760 | CIM = issue_rate; \ | |
2761 | } while (0) | |
3bc8b61e DM |
2762 | |
2763 | #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \ | |
197043f5 RH |
2764 | do { \ |
2765 | if (sparc_cpu == PROCESSOR_ULTRASPARC) \ | |
2766 | (CAN_ISSUE_MORE) = ultrasparc_variable_issue (INSN); \ | |
2767 | else \ | |
2768 | (CAN_ISSUE_MORE)--; \ | |
2769 | } while (0) | |
3bc8b61e | 2770 | |
1bb87f28 | 2771 | /* Conditional branches with empty delay slots have a length of two. */ |
bfd6bc60 | 2772 | #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ |
197043f5 | 2773 | do { \ |
1bb87f28 JW |
2774 | if (GET_CODE (INSN) == CALL_INSN \ |
2775 | || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \ | |
197043f5 RH |
2776 | LENGTH += 1; \ |
2777 | } while (0) | |
1bb87f28 JW |
2778 | \f |
2779 | /* Control the assembler format that we output. */ | |
2780 | ||
2781 | /* Output at beginning of assembler file. */ | |
2782 | ||
2783 | #define ASM_FILE_START(file) | |
2784 | ||
1ccfa253 DE |
2785 | /* A C string constant describing how to begin a comment in the target |
2786 | assembler language. The compiler assumes that the comment will end at | |
2787 | the end of the line. */ | |
2788 | ||
2789 | #define ASM_COMMENT_START "!" | |
2790 | ||
1bb87f28 JW |
2791 | /* Output to assembler file text saying following lines |
2792 | may contain character constants, extra white space, comments, etc. */ | |
2793 | ||
2794 | #define ASM_APP_ON "" | |
2795 | ||
2796 | /* Output to assembler file text saying following lines | |
2797 | no longer contain unusual constructs. */ | |
2798 | ||
2799 | #define ASM_APP_OFF "" | |
2800 | ||
7a6cf439 DE |
2801 | /* ??? Try to make the style consistent here (_OP?). */ |
2802 | ||
2803 | #define ASM_LONGLONG ".xword" | |
303d524a JW |
2804 | #define ASM_LONG ".word" |
2805 | #define ASM_SHORT ".half" | |
2806 | #define ASM_BYTE_OP ".byte" | |
7a6cf439 DE |
2807 | #define ASM_FLOAT ".single" |
2808 | #define ASM_DOUBLE ".double" | |
2809 | #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */ | |
303d524a | 2810 | |
1bb87f28 JW |
2811 | /* Output before read-only data. */ |
2812 | ||
2813 | #define TEXT_SECTION_ASM_OP ".text" | |
2814 | ||
2815 | /* Output before writable data. */ | |
2816 | ||
2817 | #define DATA_SECTION_ASM_OP ".data" | |
2818 | ||
2819 | /* How to refer to registers in assembler output. | |
2820 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2821 | ||
7a6cf439 DE |
2822 | #define REGISTER_NAMES \ |
2823 | {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ | |
2824 | "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ | |
2825 | "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ | |
2826 | "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ | |
2827 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ | |
2828 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ | |
2829 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ | |
2830 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ | |
2831 | "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ | |
2832 | "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ | |
2833 | "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ | |
2834 | "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ | |
c4ce6853 | 2835 | "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc"} |
ea3fa5f7 | 2836 | |
c4ce6853 | 2837 | /* Define additional names for use in asm clobbers and asm declarations. */ |
ea3fa5f7 | 2838 | |
c4ce6853 DE |
2839 | #define ADDITIONAL_REGISTER_NAMES \ |
2840 | {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} | |
ea3fa5f7 | 2841 | |
c53aa195 JM |
2842 | /* How to renumber registers for dbx and gdb. In the flat model, the frame |
2843 | pointer is really %i7. */ | |
1bb87f28 | 2844 | |
c53aa195 JM |
2845 | #define DBX_REGISTER_NUMBER(REGNO) \ |
2846 | (TARGET_FLAT && REGNO == FRAME_POINTER_REGNUM ? 31 : REGNO) | |
1bb87f28 | 2847 | |
5bcb3f13 JM |
2848 | /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length |
2849 | can run past this up to a continuation point. Once we used 1500, but | |
2850 | a single entry in C++ can run more than 500 bytes, due to the length of | |
2851 | mangled symbol names. dbxout.c should really be fixed to do | |
2852 | continuations when they are actually needed instead of trying to | |
2853 | guess... */ | |
2854 | #define DBX_CONTIN_LENGTH 1000 | |
1bb87f28 JW |
2855 | |
2856 | /* This is how to output a note to DBX telling it the line number | |
2857 | to which the following sequence of instructions corresponds. | |
2858 | ||
2859 | This is needed for SunOS 4.0, and should not hurt for 3.2 | |
2860 | versions either. */ | |
2861 | #define ASM_OUTPUT_SOURCE_LINE(file, line) \ | |
2862 | { static int sym_lineno = 1; \ | |
2863 | fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \ | |
2864 | line, sym_lineno, sym_lineno); \ | |
2865 | sym_lineno += 1; } | |
2866 | ||
2867 | /* This is how to output the definition of a user-level label named NAME, | |
2868 | such as the label on a static function or variable NAME. */ | |
2869 | ||
2870 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
2871 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
2872 | ||
2873 | /* This is how to output a command to make the user-level label named NAME | |
2874 | defined for reference from other files. */ | |
2875 | ||
2876 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ | |
2877 | do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) | |
2878 | ||
4e0c8ad2 | 2879 | /* The prefix to add to user-visible assembler symbols. */ |
1bb87f28 | 2880 | |
4e0c8ad2 | 2881 | #define USER_LABEL_PREFIX "_" |
1bb87f28 | 2882 | |
d2a8e680 | 2883 | /* This is how to output a definition of an internal numbered label where |
1bb87f28 JW |
2884 | PREFIX is the class of label and NUM is the number within the class. */ |
2885 | ||
2886 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
2887 | fprintf (FILE, "%s%d:\n", PREFIX, NUM) | |
2888 | ||
2889 | /* This is how to store into the string LABEL | |
2890 | the symbol_ref name of an internal numbered label where | |
2891 | PREFIX is the class of label and NUM is the number within the class. | |
2892 | This is suitable for output with `assemble_name'. */ | |
2893 | ||
2894 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
4f70758f | 2895 | sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) |
1bb87f28 | 2896 | |
1ccfa253 DE |
2897 | /* This is how to output an assembler line defining a `float' constant. |
2898 | We always have to use a .long pseudo-op to do this because the native | |
2899 | SVR4 ELF assembler is buggy and it generates incorrect values when we | |
2900 | try to use the .float pseudo-op instead. */ | |
1bb87f28 | 2901 | |
1ccfa253 DE |
2902 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ |
2903 | { \ | |
2904 | long t; \ | |
2905 | char str[30]; \ | |
2906 | REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ | |
2907 | REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ | |
2908 | fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t, \ | |
2909 | ASM_COMMENT_START, str); \ | |
2910 | } \ | |
1bb87f28 | 2911 | |
1ccfa253 DE |
2912 | /* This is how to output an assembler line defining a `double' constant. |
2913 | We always have to use a .long pseudo-op to do this because the native | |
2914 | SVR4 ELF assembler is buggy and it generates incorrect values when we | |
2915 | try to use the .float pseudo-op instead. */ | |
1bb87f28 | 2916 | |
1ccfa253 DE |
2917 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ |
2918 | { \ | |
2919 | long t[2]; \ | |
2920 | char str[30]; \ | |
2921 | REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ | |
2922 | REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ | |
2923 | fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0], \ | |
2924 | ASM_COMMENT_START, str); \ | |
2925 | fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]); \ | |
2926 | } | |
1bb87f28 | 2927 | |
0cd02cbb DE |
2928 | /* This is how to output an assembler line defining a `long double' |
2929 | constant. */ | |
2930 | ||
1ccfa253 DE |
2931 | #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ |
2932 | { \ | |
2933 | long t[4]; \ | |
2934 | char str[30]; \ | |
2935 | REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \ | |
2936 | REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ | |
2937 | fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0], \ | |
2938 | ASM_COMMENT_START, str); \ | |
2939 | fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]); \ | |
2940 | fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[2]); \ | |
2941 | fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[3]); \ | |
0cd02cbb DE |
2942 | } |
2943 | ||
1bb87f28 JW |
2944 | /* This is how to output an assembler line defining an `int' constant. */ |
2945 | ||
2946 | #define ASM_OUTPUT_INT(FILE,VALUE) \ | |
303d524a | 2947 | ( fprintf (FILE, "\t%s\t", ASM_LONG), \ |
1bb87f28 JW |
2948 | output_addr_const (FILE, (VALUE)), \ |
2949 | fprintf (FILE, "\n")) | |
2950 | ||
2951 | /* This is how to output an assembler line defining a DImode constant. */ | |
2952 | #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ | |
2953 | output_double_int (FILE, VALUE) | |
2954 | ||
2955 | /* Likewise for `char' and `short' constants. */ | |
2956 | ||
2957 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
303d524a | 2958 | ( fprintf (FILE, "\t%s\t", ASM_SHORT), \ |
1bb87f28 JW |
2959 | output_addr_const (FILE, (VALUE)), \ |
2960 | fprintf (FILE, "\n")) | |
2961 | ||
2962 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ | |
303d524a | 2963 | ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \ |
1bb87f28 JW |
2964 | output_addr_const (FILE, (VALUE)), \ |
2965 | fprintf (FILE, "\n")) | |
2966 | ||
2967 | /* This is how to output an assembler line for a numeric constant byte. */ | |
2968 | ||
2969 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ | |
303d524a | 2970 | fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE)) |
1bb87f28 | 2971 | |
e0d80184 DM |
2972 | /* This is how we hook in and defer the case-vector until the end of |
2973 | the function. */ | |
df4f7565 | 2974 | extern void sparc_defer_case_vector (); |
e0d80184 DM |
2975 | |
2976 | #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ | |
2977 | sparc_defer_case_vector ((LAB),(VEC), 0) | |
2978 | ||
2979 | #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ | |
2980 | sparc_defer_case_vector ((LAB),(VEC), 1) | |
2981 | ||
1bb87f28 JW |
2982 | /* This is how to output an element of a case-vector that is absolute. */ |
2983 | ||
2984 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
4b69d2a3 RS |
2985 | do { \ |
2986 | char label[30]; \ | |
2987 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
67cb8900 | 2988 | if (CASE_VECTOR_MODE == SImode) \ |
7a6cf439 | 2989 | fprintf (FILE, "\t.word\t"); \ |
7a6cf439 DE |
2990 | else \ |
2991 | fprintf (FILE, "\t.xword\t"); \ | |
4b69d2a3 | 2992 | assemble_name (FILE, label); \ |
e0d80184 | 2993 | fputc ('\n', FILE); \ |
4b69d2a3 | 2994 | } while (0) |
1bb87f28 JW |
2995 | |
2996 | /* This is how to output an element of a case-vector that is relative. | |
2997 | (SPARC uses such vectors only when generating PIC.) */ | |
2998 | ||
33f7f353 | 2999 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
4b69d2a3 RS |
3000 | do { \ |
3001 | char label[30]; \ | |
e0d80184 | 3002 | ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ |
67cb8900 | 3003 | if (CASE_VECTOR_MODE == SImode) \ |
7a6cf439 | 3004 | fprintf (FILE, "\t.word\t"); \ |
7a6cf439 DE |
3005 | else \ |
3006 | fprintf (FILE, "\t.xword\t"); \ | |
4b69d2a3 | 3007 | assemble_name (FILE, label); \ |
e0d80184 DM |
3008 | ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ |
3009 | fputc ('-', FILE); \ | |
3010 | assemble_name (FILE, label); \ | |
3011 | fputc ('\n', FILE); \ | |
4b69d2a3 | 3012 | } while (0) |
1bb87f28 | 3013 | |
d1accaa3 JJ |
3014 | /* This is what to output before and after case-vector (both |
3015 | relative and absolute). If .subsection -1 works, we put case-vectors | |
3016 | at the beginning of the current section. */ | |
3017 | ||
3018 | #ifdef HAVE_GAS_SUBSECTION_ORDERING | |
3019 | ||
3020 | #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ | |
3021 | fprintf(FILE, "\t.subsection\t-1\n") | |
3022 | ||
3023 | #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ | |
3024 | fprintf(FILE, "\t.previous\n") | |
3025 | ||
3026 | #endif | |
3027 | ||
1bb87f28 JW |
3028 | /* This is how to output an assembler line |
3029 | that says to advance the location counter | |
3030 | to a multiple of 2**LOG bytes. */ | |
3031 | ||
3032 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
3033 | if ((LOG) != 0) \ | |
3034 | fprintf (FILE, "\t.align %d\n", (1<<(LOG))) | |
3035 | ||
fc470718 | 3036 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (sparc_align_jumps) |
1ccfa253 | 3037 | |
fc470718 | 3038 | #define LOOP_ALIGN(LABEL) (sparc_align_loops) |
1ccfa253 | 3039 | |
1bb87f28 JW |
3040 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ |
3041 | fprintf (FILE, "\t.skip %u\n", (SIZE)) | |
3042 | ||
3043 | /* This says how to output an assembler line | |
3044 | to define a global common symbol. */ | |
3045 | ||
3046 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
b277ceaf | 3047 | ( fputs ("\t.common ", (FILE)), \ |
1bb87f28 | 3048 | assemble_name ((FILE), (NAME)), \ |
b277ceaf | 3049 | fprintf ((FILE), ",%u,\"bss\"\n", (SIZE))) |
1bb87f28 | 3050 | |
b277ceaf JW |
3051 | /* This says how to output an assembler line to define a local common |
3052 | symbol. */ | |
1bb87f28 | 3053 | |
b277ceaf JW |
3054 | #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ |
3055 | ( fputs ("\t.reserve ", (FILE)), \ | |
3056 | assemble_name ((FILE), (NAME)), \ | |
3057 | fprintf ((FILE), ",%u,\"bss\",%u\n", \ | |
3058 | (SIZE), ((ALIGNED) / BITS_PER_UNIT))) | |
1bb87f28 | 3059 | |
101d9529 JM |
3060 | /* A C statement (sans semicolon) to output to the stdio stream |
3061 | FILE the assembler definition of uninitialized global DECL named | |
3062 | NAME whose size is SIZE bytes and alignment is ALIGN bytes. | |
3063 | Try to use asm_output_aligned_bss to implement this macro. */ | |
3064 | ||
3065 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
3066 | do { \ | |
3067 | fputs (".globl ", (FILE)); \ | |
3068 | assemble_name ((FILE), (NAME)); \ | |
3069 | fputs ("\n", (FILE)); \ | |
3070 | ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ | |
3071 | } while (0) | |
3072 | ||
1bb87f28 JW |
3073 | /* Store in OUTPUT a string (made with alloca) containing |
3074 | an assembler-name for a local static variable named NAME. | |
3075 | LABELNO is an integer which is different for each call. */ | |
3076 | ||
3077 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
3078 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
3079 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
3080 | ||
c14f2655 RS |
3081 | #define IDENT_ASM_OP ".ident" |
3082 | ||
3083 | /* Output #ident as a .ident. */ | |
3084 | ||
3085 | #define ASM_OUTPUT_IDENT(FILE, NAME) \ | |
3086 | fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME); | |
3087 | ||
c94b3179 JM |
3088 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. |
3089 | Used for C++ multiple inheritance. */ | |
1df8f58f JM |
3090 | #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ |
3091 | do { \ | |
3092 | int big_delta = (DELTA) >= 4096 || (DELTA) < -4096; \ | |
3093 | if (big_delta) \ | |
3094 | fprintf (FILE, "\tset %d,%%g1\n\tadd %%o0,%%g1,%%o0\n", (DELTA)); \ | |
194faace RH |
3095 | /* Don't use the jmp solution unless we know the target is local to \ |
3096 | the application or shared object. \ | |
3097 | XXX: Wimp out and don't actually check anything except if this is \ | |
3098 | an embedded target where we assume there are no shared libs. */ \ | |
3099 | if (!TARGET_CM_EMBMEDANY || flag_pic) \ | |
fd407cd2 JM |
3100 | { \ |
3101 | if (! big_delta) \ | |
3102 | fprintf (FILE, "\tadd %%o0,%d,%%o0\n", DELTA); \ | |
194faace | 3103 | fprintf (FILE, "\tmov %%o7,%%g1\n"); \ |
fd407cd2 | 3104 | fprintf (FILE, "\tcall "); \ |
92d4501f | 3105 | assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ |
fd407cd2 JM |
3106 | fprintf (FILE, ",0\n"); \ |
3107 | } \ | |
a0a301fc | 3108 | else if (TARGET_CM_EMBMEDANY) \ |
1df8f58f JM |
3109 | { \ |
3110 | fprintf (FILE, "\tsetx "); \ | |
92d4501f | 3111 | assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ |
1df8f58f JM |
3112 | fprintf (FILE, ",%%g5,%%g1\n\tjmp %%g1\n"); \ |
3113 | } \ | |
3114 | else \ | |
3115 | { \ | |
3116 | fprintf (FILE, "\tsethi %%hi("); \ | |
92d4501f | 3117 | assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ |
1df8f58f | 3118 | fprintf (FILE, "),%%g1\n\tjmp %%g1+%%lo("); \ |
92d4501f | 3119 | assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ |
1df8f58f JM |
3120 | fprintf (FILE, ")\n"); \ |
3121 | } \ | |
194faace RH |
3122 | if (!TARGET_CM_EMBMEDANY || flag_pic) \ |
3123 | fprintf (FILE, "\tmov %%g1,%%o7\n"); \ | |
3124 | else if (big_delta) \ | |
fd407cd2 | 3125 | fprintf (FILE, "\tnop\n"); \ |
fd407cd2 JM |
3126 | else \ |
3127 | fprintf (FILE, "\tadd %%o0,%d,%%o0\n", DELTA); \ | |
c94b3179 JM |
3128 | } while (0) |
3129 | ||
1bb87f28 JW |
3130 | /* Define the parentheses used to group arithmetic operations |
3131 | in assembler code. */ | |
3132 | ||
3133 | #define ASM_OPEN_PAREN "(" | |
3134 | #define ASM_CLOSE_PAREN ")" | |
3135 | ||
3136 | /* Define results of standard character escape sequences. */ | |
3137 | #define TARGET_BELL 007 | |
3138 | #define TARGET_BS 010 | |
3139 | #define TARGET_TAB 011 | |
3140 | #define TARGET_NEWLINE 012 | |
3141 | #define TARGET_VT 013 | |
3142 | #define TARGET_FF 014 | |
3143 | #define TARGET_CR 015 | |
3144 | ||
3145 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
a0a301fc | 3146 | ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_') |
1bb87f28 JW |
3147 | |
3148 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
3149 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
3150 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
3151 | ||
3152 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
3153 | ||
3154 | /* Print a memory address as an operand to reference that memory location. */ | |
3155 | ||
3156 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
3157 | { register rtx base, index = 0; \ | |
3158 | int offset = 0; \ | |
3159 | register rtx addr = ADDR; \ | |
3160 | if (GET_CODE (addr) == REG) \ | |
3161 | fputs (reg_names[REGNO (addr)], FILE); \ | |
3162 | else if (GET_CODE (addr) == PLUS) \ | |
3163 | { \ | |
3164 | if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ | |
3165 | offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ | |
3166 | else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ | |
3167 | offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ | |
3168 | else \ | |
3169 | base = XEXP (addr, 0), index = XEXP (addr, 1); \ | |
1cb36a98 RH |
3170 | if (GET_CODE (base) == LO_SUM) \ |
3171 | { \ | |
3172 | if (! USE_AS_OFFSETABLE_LO10 \ | |
3173 | || TARGET_ARCH32 \ | |
3174 | || TARGET_CM_MEDMID) \ | |
3175 | abort (); \ | |
3176 | output_operand (XEXP (base, 0), 0); \ | |
3177 | fputs ("+%lo(", FILE); \ | |
3178 | output_address (XEXP (base, 1)); \ | |
3179 | fprintf (FILE, ")+%d", offset); \ | |
3180 | } \ | |
3181 | else \ | |
3182 | { \ | |
3183 | fputs (reg_names[REGNO (base)], FILE); \ | |
3184 | if (index == 0) \ | |
3185 | fprintf (FILE, "%+d", offset); \ | |
3186 | else if (GET_CODE (index) == REG) \ | |
3187 | fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ | |
3188 | else if (GET_CODE (index) == SYMBOL_REF \ | |
3189 | || GET_CODE (index) == CONST) \ | |
3190 | fputc ('+', FILE), output_addr_const (FILE, index); \ | |
3191 | else abort (); \ | |
3192 | } \ | |
1bb87f28 JW |
3193 | } \ |
3194 | else if (GET_CODE (addr) == MINUS \ | |
3195 | && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ | |
3196 | { \ | |
3197 | output_addr_const (FILE, XEXP (addr, 0)); \ | |
3198 | fputs ("-(", FILE); \ | |
3199 | output_addr_const (FILE, XEXP (addr, 1)); \ | |
3200 | fputs ("-.)", FILE); \ | |
3201 | } \ | |
3202 | else if (GET_CODE (addr) == LO_SUM) \ | |
3203 | { \ | |
3204 | output_operand (XEXP (addr, 0), 0); \ | |
e0d80184 DM |
3205 | if (TARGET_CM_MEDMID) \ |
3206 | fputs ("+%l44(", FILE); \ | |
3207 | else \ | |
3208 | fputs ("+%lo(", FILE); \ | |
1bb87f28 JW |
3209 | output_address (XEXP (addr, 1)); \ |
3210 | fputc (')', FILE); \ | |
3211 | } \ | |
3212 | else if (flag_pic && GET_CODE (addr) == CONST \ | |
3213 | && GET_CODE (XEXP (addr, 0)) == MINUS \ | |
3214 | && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ | |
3215 | && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ | |
3216 | && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ | |
3217 | { \ | |
3218 | addr = XEXP (addr, 0); \ | |
3219 | output_addr_const (FILE, XEXP (addr, 0)); \ | |
3220 | /* Group the args of the second CONST in parenthesis. */ \ | |
3221 | fputs ("-(", FILE); \ | |
3222 | /* Skip past the second CONST--it does nothing for us. */\ | |
3223 | output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ | |
3224 | /* Close the parenthesis. */ \ | |
3225 | fputc (')', FILE); \ | |
3226 | } \ | |
3227 | else \ | |
3228 | { \ | |
3229 | output_addr_const (FILE, addr); \ | |
3230 | } \ | |
3231 | } | |
3232 | ||
f7e0e539 DM |
3233 | /* Define the codes that are matched by predicates in sparc.c. */ |
3234 | ||
11301057 RH |
3235 | #define PREDICATE_CODES \ |
3236 | {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
3237 | {"fp_zero_operand", {CONST_DOUBLE}}, \ | |
3238 | {"intreg_operand", {SUBREG, REG}}, \ | |
3239 | {"fcc_reg_operand", {REG}}, \ | |
3240 | {"icc_or_fcc_reg_operand", {REG}}, \ | |
3241 | {"restore_operand", {REG}}, \ | |
3242 | {"call_operand", {MEM}}, \ | |
3243 | {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \ | |
3244 | ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \ | |
3245 | {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE}}, \ | |
3246 | {"symbolic_memory_operand", {SUBREG, MEM}}, \ | |
3247 | {"label_ref_operand", {LABEL_REF}}, \ | |
3248 | {"sp64_medium_pic_operand", {CONST}}, \ | |
3249 | {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \ | |
3250 | {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \ | |
3251 | {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \ | |
3252 | {"splittable_symbolic_memory_operand", {MEM}}, \ | |
3253 | {"splittable_immediate_memory_operand", {MEM}}, \ | |
3254 | {"eq_or_neq", {EQ, NE}}, \ | |
3255 | {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \ | |
3256 | {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \ | |
3257 | {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \ | |
3258 | {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \ | |
3259 | {"cc_arithop", {AND, IOR, XOR}}, \ | |
3260 | {"cc_arithopn", {AND, IOR}}, \ | |
3261 | {"arith_operand", {SUBREG, REG, CONST_INT}}, \ | |
3262 | {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \ | |
3263 | {"arith11_operand", {SUBREG, REG, CONST_INT}}, \ | |
3264 | {"arith10_operand", {SUBREG, REG, CONST_INT}}, \ | |
3265 | {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
3266 | {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
3267 | {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
3268 | {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
3269 | {"small_int", {CONST_INT}}, \ | |
3270 | {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \ | |
3271 | {"uns_small_int", {CONST_INT}}, \ | |
3272 | {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \ | |
3273 | {"clobbered_register", {REG}}, \ | |
3274 | {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \ | |
3275 | {"zero_operand", {CONST_INT}}, \ | |
3276 | {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \ | |
3277 | {"const64_high_operand", {CONST_INT, CONST_DOUBLE}}, | |
f7e0e539 | 3278 | |
27a36778 MS |
3279 | /* The number of Pmode words for the setjmp buffer. */ |
3280 | #define JMP_BUF_SIZE 12 | |
3281 | ||
59ba1a3a MS |
3282 | #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic) |
3283 | ||
1bb87f28 JW |
3284 | /* Declare functions defined in sparc.c and used in templates. */ |
3285 | ||
e0d80184 DM |
3286 | extern void sparc_emit_set_const32 (); |
3287 | extern void sparc_emit_set_const64 (); | |
3288 | extern void sparc_emit_set_symbolic_const64 (); | |
3289 | extern int sparc_splitdi_legitimate (); | |
e61c29e9 | 3290 | extern int sparc_absnegfloat_split_legitimate (); |
e0d80184 | 3291 | |
27d8f9ea | 3292 | extern char *output_cbranch (); |
3bb5de61 | 3293 | extern const char *output_return (); |
7a6cf439 | 3294 | extern char *output_v9branch (); |
27d8f9ea KG |
3295 | |
3296 | extern void emit_v9_brxx_insn (); | |
3297 | extern void finalize_pic (); | |
487a6e06 | 3298 | extern void order_regs_for_local_alloc (); |
27d8f9ea KG |
3299 | extern void output_double_int (); |
3300 | extern void output_function_epilogue (); | |
3301 | extern void output_function_prologue (); | |
3302 | extern void print_operand (); | |
3303 | extern void sparc_flat_output_function_epilogue (); | |
3304 | extern void sparc_flat_output_function_prologue (); | |
3305 | ||
3306 | extern int addrs_ok_for_ldd_peep (); | |
3307 | extern int arith10_double_operand (); | |
3308 | extern int arith10_operand (); | |
3309 | extern int arith11_double_operand (); | |
3310 | extern int arith11_operand (); | |
3311 | extern int arith_double_operand (); | |
5d6d3339 JJ |
3312 | extern int arith_double_4096_operand (); |
3313 | extern int arith_double_add_operand (); | |
27d8f9ea | 3314 | extern int arith_operand (); |
5d6d3339 JJ |
3315 | extern int arith_4096_operand (); |
3316 | extern int arith_add_operand (); | |
27d8f9ea | 3317 | extern int call_operand_address (); |
e0d80184 DM |
3318 | extern int input_operand (); |
3319 | extern int zero_operand (); | |
89e65674 DM |
3320 | extern int const64_operand (); |
3321 | extern int const64_high_operand (); | |
27d8f9ea KG |
3322 | extern int cc_arithop (); |
3323 | extern int cc_arithopn (); | |
3324 | extern int check_pic (); | |
3325 | extern int compute_frame_size (); | |
3326 | extern int data_segment_operand (); | |
3327 | extern int eligible_for_epilogue_delay (); | |
487a6e06 | 3328 | extern int eligible_for_return_delay (); |
27d8f9ea KG |
3329 | extern int emit_move_sequence (); |
3330 | extern int extend_op (); | |
3331 | extern int fcc_reg_operand (); | |
3332 | extern int fp_zero_operand (); | |
3333 | extern int icc_or_fcc_reg_operand (); | |
3334 | extern int label_ref_operand (); | |
e0d80184 | 3335 | extern int mem_min_alignment (); |
27d8f9ea KG |
3336 | extern int noov_compare_op (); |
3337 | extern int pic_address_needs_scratch (); | |
3338 | extern int reg_or_0_operand (); | |
3339 | extern int reg_or_nonsymb_mem_operand (); | |
3340 | extern int reg_unused_after (); | |
3341 | extern int register_ok_for_ldd (); | |
3342 | extern int registers_ok_for_ldd_peep (); | |
3343 | extern int restore_operand (); | |
3344 | extern int short_branch (); | |
3345 | extern int small_int (); | |
e0d80184 | 3346 | extern int small_int_or_double (); |
27d8f9ea KG |
3347 | extern int sp64_medium_pic_operand (); |
3348 | extern int sparc_flat_eligible_for_epilogue_delay (); | |
3349 | extern int sparc_flat_epilogue_delay_slots (); | |
487a6e06 | 3350 | extern int sparc_issue_rate (); |
27d8f9ea KG |
3351 | extern int splittable_immediate_memory_operand (); |
3352 | extern int splittable_symbolic_memory_operand (); | |
8947065c | 3353 | extern int sparc_adjust_cost (); |
27d8f9ea KG |
3354 | extern int symbolic_memory_operand (); |
3355 | extern int symbolic_operand (); | |
3356 | extern int text_segment_operand (); | |
27d8f9ea KG |
3357 | extern int uns_small_int (); |
3358 | extern int v9_regcmp_op (); | |
3359 | extern int v9_regcmp_p (); | |
3360 | ||
3361 | extern unsigned long sparc_flat_compute_frame_size (); | |
3362 | extern unsigned long sparc_type_code (); | |
1bb87f28 | 3363 | |
2be15d0f RH |
3364 | extern void sparc_function_profiler (); |
3365 | extern void sparc_function_block_profiler (); | |
3366 | extern void sparc_block_profiler (); | |
3367 | extern void sparc_function_block_profiler_exit (); | |
3368 | ||
284d86e9 JC |
3369 | extern char *sparc_v8plus_shift (); |
3370 | ||
3371 | #ifdef __STDC__ | |
3372 | /* Function used for V8+ code generation. Returns 1 if the high | |
3373 | 32 bits of REG are 0 before INSN. */ | |
3374 | extern int sparc_check_64 (struct rtx_def *, struct rtx_def *); | |
3375 | extern int sparc_return_peephole_ok (struct rtx_def *, struct rtx_def *); | |
3376 | extern int compute_frame_size (int, int); | |
3377 | #endif | |
3378 | ||
1bb87f28 JW |
3379 | /* Defined in flags.h, but insn-emit.c does not include flags.h. */ |
3380 | ||
3381 | extern int flag_pic; |