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1bb87f28 | 1 | /* Definitions of target machine for GNU compiler, for Sun SPARC. |
4592bdcb | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999 |
c9280dfe | 3 | 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
1bb87f28 | 4 | Contributed by Michael Tiemann (tiemann@cygnus.com). |
7a6cf439 DE |
5 | 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
6 | at Cygnus Support. | |
1bb87f28 | 7 | |
7ec022b2 | 8 | This file is part of GCC. |
1bb87f28 | 9 | |
7ec022b2 | 10 | GCC is free software; you can redistribute it and/or modify |
1bb87f28 JW |
11 | it under the terms of the GNU General Public License as published by |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
7ec022b2 | 15 | GCC is distributed in the hope that it will be useful, |
1bb87f28 JW |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
7ec022b2 | 21 | along with GCC; see the file COPYING. If not, write to |
c15c9075 RK |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, |
23 | Boston, MA 02111-1307, USA. */ | |
1bb87f28 JW |
24 | |
25 | /* Note that some other tm.h files include this one and then override | |
a0a301fc DE |
26 | whatever definitions are necessary. */ |
27 | ||
094a51ff | 28 | /* Target CPU builtins. FIXME: Defining sparc is for the benefit of |
fae778eb | 29 | Solaris only; otherwise just define __sparc__. Sadly the headers |
094a51ff | 30 | are such a mess there is no Solaris-specific header. */ |
9b8466f4 NB |
31 | #define TARGET_CPU_CPP_BUILTINS() \ |
32 | do \ | |
33 | { \ | |
094a51ff | 34 | builtin_define_std ("sparc"); \ |
9b8466f4 NB |
35 | if (TARGET_64BIT) \ |
36 | { \ | |
37 | builtin_assert ("cpu=sparc"); \ | |
38 | builtin_assert ("machine=sparc"); \ | |
39 | } \ | |
40 | else \ | |
41 | { \ | |
42 | builtin_assert ("cpu=sparc64"); \ | |
43 | builtin_assert ("machine=sparc64"); \ | |
44 | } \ | |
45 | } \ | |
46 | while (0) | |
47 | ||
a0a301fc DE |
48 | /* Specify this in a cover file to provide bi-architecture (32/64) support. */ |
49 | /* #define SPARC_BI_ARCH */ | |
50 | ||
51 | /* Macro used later in this file to determine default architecture. */ | |
52 | #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) | |
7a6cf439 | 53 | |
a0a301fc DE |
54 | /* TARGET_ARCH{32,64} are the main macros to decide which of the two |
55 | architectures to compile for. We allow targets to choose compile time or | |
56 | runtime selection. */ | |
959eb758 | 57 | #ifdef IN_LIBGCC2 |
afdac905 | 58 | #if defined(__sparcv9) || defined(__arch64__) |
959eb758 DM |
59 | #define TARGET_ARCH32 0 |
60 | #else | |
61 | #define TARGET_ARCH32 1 | |
afdac905 | 62 | #endif /* sparc64 */ |
959eb758 | 63 | #else |
53f4a9f6 | 64 | #ifdef SPARC_BI_ARCH |
a0a301fc DE |
65 | #define TARGET_ARCH32 (! TARGET_64BIT) |
66 | #else | |
67 | #define TARGET_ARCH32 (DEFAULT_ARCH32_P) | |
959eb758 | 68 | #endif /* SPARC_BI_ARCH */ |
53f4a9f6 | 69 | #endif /* IN_LIBGCC2 */ |
a0a301fc DE |
70 | #define TARGET_ARCH64 (! TARGET_ARCH32) |
71 | ||
72 | /* Code model selection. | |
73 | -mcmodel is used to select the v9 code model. | |
5cb01b65 | 74 | Different code models aren't supported for v7/8 code. |
a0a301fc DE |
75 | |
76 | TARGET_CM_32: 32 bit address space, top 32 bits = 0, | |
77 | pointers are 32 bits. Note that this isn't intended | |
5cb01b65 | 78 | to imply a v7/8 abi. |
a0a301fc DE |
79 | |
80 | TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0, | |
81 | avoid generating %uhi and %ulo terms, | |
82 | pointers are 64 bits. | |
83 | ||
84 | TARGET_CM_MEDMID: 64 bit address space. | |
85 | The executable must be in the low 16 TB of memory. | |
86 | This corresponds to the low 44 bits, and the %[hml]44 | |
67cb8900 JJ |
87 | relocs are used. The text segment has a maximum size |
88 | of 31 bits. | |
a0a301fc DE |
89 | |
90 | TARGET_CM_MEDANY: 64 bit address space. | |
91 | The text and data segments have a maximum size of 31 | |
92 | bits and may be located anywhere. The maximum offset | |
93 | from any instruction to the label _GLOBAL_OFFSET_TABLE_ | |
94 | is 31 bits. | |
95 | ||
96 | TARGET_CM_EMBMEDANY: 64 bit address space. | |
97 | The text and data segments have a maximum size of 31 bits | |
98 | and may be located anywhere. Register %g4 contains | |
99 | the start address of the data segment. | |
100 | */ | |
101 | ||
102 | enum cmodel { | |
103 | CM_32, | |
104 | CM_MEDLOW, | |
105 | CM_MEDMID, | |
106 | CM_MEDANY, | |
107 | CM_EMBMEDANY | |
108 | }; | |
109 | ||
110 | /* Value of -mcmodel specified by user. */ | |
3bb5de61 | 111 | extern const char *sparc_cmodel_string; |
a0a301fc DE |
112 | /* One of CM_FOO. */ |
113 | extern enum cmodel sparc_cmodel; | |
114 | ||
115 | /* V9 code model selection. */ | |
116 | #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) | |
117 | #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) | |
118 | #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) | |
119 | #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) | |
120 | ||
a330e73b | 121 | #define SPARC_DEFAULT_CMODEL CM_32 |
6f64bf5f | 122 | |
a0a301fc DE |
123 | /* This is call-clobbered in the normal ABI, but is reserved in the |
124 | home grown (aka upward compatible) embedded ABI. */ | |
125 | #define EMBMEDANY_BASE_REG "%g4" | |
126 | \f | |
127 | /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, | |
128 | and specified by the user via --with-cpu=foo. | |
129 | This specifies the cpu implementation, not the architecture size. */ | |
3aabf9a5 | 130 | /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit |
8947065c | 131 | capable cpu's. */ |
2163f11b RK |
132 | #define TARGET_CPU_sparc 0 |
133 | #define TARGET_CPU_v7 0 /* alias for previous */ | |
134 | #define TARGET_CPU_sparclet 1 | |
135 | #define TARGET_CPU_sparclite 2 | |
a0a301fc | 136 | #define TARGET_CPU_v8 3 /* generic v8 implementation */ |
2163f11b | 137 | #define TARGET_CPU_supersparc 4 |
8947065c | 138 | #define TARGET_CPU_hypersparc 5 |
809934df | 139 | #define TARGET_CPU_sparc86x 6 |
8947065c RH |
140 | #define TARGET_CPU_sparclite86x 6 |
141 | #define TARGET_CPU_v9 7 /* generic v9 implementation */ | |
142 | #define TARGET_CPU_sparcv9 7 /* alias */ | |
143 | #define TARGET_CPU_sparc64 7 /* alias */ | |
144 | #define TARGET_CPU_ultrasparc 8 | |
fae15c93 | 145 | #define TARGET_CPU_ultrasparc3 9 |
bafb031b | 146 | |
8947065c | 147 | #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ |
fae15c93 VM |
148 | || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ |
149 | || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 | |
345a6161 DM |
150 | |
151 | #define CPP_CPU32_DEFAULT_SPEC "" | |
152 | #define ASM_CPU32_DEFAULT_SPEC "" | |
153 | ||
a0a301fc | 154 | #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 |
bafb031b | 155 | /* ??? What does Sun's CC pass? */ |
345a6161 | 156 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" |
bafb031b DE |
157 | /* ??? It's not clear how other assemblers will handle this, so by default |
158 | use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case | |
159 | is handled in sol2.h. */ | |
345a6161 | 160 | #define ASM_CPU64_DEFAULT_SPEC "-Av9" |
bafb031b | 161 | #endif |
a0a301fc | 162 | #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc |
345a6161 DM |
163 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" |
164 | #define ASM_CPU64_DEFAULT_SPEC "-Av9a" | |
165 | #endif | |
fae15c93 VM |
166 | #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 |
167 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
168 | #define ASM_CPU64_DEFAULT_SPEC "-Av9b" | |
169 | #endif | |
345a6161 DM |
170 | |
171 | #else | |
172 | ||
173 | #define CPP_CPU64_DEFAULT_SPEC "" | |
174 | #define ASM_CPU64_DEFAULT_SPEC "" | |
175 | ||
8947065c RH |
176 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ |
177 | || TARGET_CPU_DEFAULT == TARGET_CPU_v8 | |
345a6161 DM |
178 | #define CPP_CPU32_DEFAULT_SPEC "" |
179 | #define ASM_CPU32_DEFAULT_SPEC "" | |
180 | #endif | |
8947065c | 181 | |
345a6161 DM |
182 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet |
183 | #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" | |
184 | #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" | |
bafb031b | 185 | #endif |
8947065c | 186 | |
345a6161 DM |
187 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite |
188 | #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" | |
189 | #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" | |
190 | #endif | |
191 | ||
8947065c RH |
192 | #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc |
193 | #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" | |
194 | #define ASM_CPU32_DEFAULT_SPEC "" | |
195 | #endif | |
196 | ||
197 | #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc | |
198 | #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" | |
199 | #define ASM_CPU32_DEFAULT_SPEC "" | |
200 | #endif | |
201 | ||
202 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x | |
8d72ec32 VM |
203 | #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" |
204 | #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" | |
8947065c RH |
205 | #endif |
206 | ||
345a6161 DM |
207 | #endif |
208 | ||
209 | #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) | |
3aabf9a5 | 210 | #error Unrecognized value in TARGET_CPU_DEFAULT. |
bafb031b DE |
211 | #endif |
212 | ||
345a6161 DM |
213 | #ifdef SPARC_BI_ARCH |
214 | ||
215 | #define CPP_CPU_DEFAULT_SPEC \ | |
216 | (DEFAULT_ARCH32_P ? "\ | |
217 | %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ | |
218 | %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ | |
219 | " : "\ | |
220 | %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ | |
221 | %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ | |
222 | ") | |
223 | #define ASM_CPU_DEFAULT_SPEC \ | |
224 | (DEFAULT_ARCH32_P ? "\ | |
225 | %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ | |
226 | %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ | |
227 | " : "\ | |
228 | %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ | |
229 | %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ | |
230 | ") | |
231 | ||
232 | #else /* !SPARC_BI_ARCH */ | |
233 | ||
234 | #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) | |
235 | #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) | |
236 | ||
237 | #endif /* !SPARC_BI_ARCH */ | |
238 | ||
885d8175 | 239 | /* Define macros to distinguish architectures. */ |
857458c4 | 240 | |
bafb031b DE |
241 | /* Common CPP definitions used by CPP_SPEC amongst the various targets |
242 | for handling -mcpu=xxx switches. */ | |
243 | #define CPP_CPU_SPEC "\ | |
7adb4be8 | 244 | %{msoft-float:-D_SOFT_FLOAT} \ |
bafb031b | 245 | %{mcypress:} \ |
7a6cf439 DE |
246 | %{msparclite:-D__sparclite__} \ |
247 | %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ | |
248 | %{mv8:-D__sparc_v8__} \ | |
bafb031b | 249 | %{msupersparc:-D__supersparc__ -D__sparc_v8__} \ |
9b7c06d2 | 250 | %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ |
bafb031b DE |
251 | %{mcpu=sparclite:-D__sparclite__} \ |
252 | %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ | |
253 | %{mcpu=v8:-D__sparc_v8__} \ | |
254 | %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ | |
8947065c | 255 | %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ |
8d72ec32 | 256 | %{mcpu=sparclite86x:-D__sparclite86x__} \ |
bafb031b DE |
257 | %{mcpu=v9:-D__sparc_v9__} \ |
258 | %{mcpu=ultrasparc:-D__sparc_v9__} \ | |
fae15c93 | 259 | %{mcpu=ultrasparc3:-D__sparc_v9__} \ |
a0a301fc | 260 | %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ |
7a6cf439 | 261 | " |
9b8466f4 NB |
262 | #define CPP_ARCH32_SPEC "" |
263 | #define CPP_ARCH64_SPEC "-D__arch64__" | |
345a6161 | 264 | |
a0a301fc DE |
265 | #define CPP_ARCH_DEFAULT_SPEC \ |
266 | (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) | |
267 | ||
268 | #define CPP_ARCH_SPEC "\ | |
269 | %{m32:%(cpp_arch32)} \ | |
270 | %{m64:%(cpp_arch64)} \ | |
271 | %{!m32:%{!m64:%(cpp_arch_default)}} \ | |
272 | " | |
273 | ||
274 | /* Macros to distinguish endianness. */ | |
8947065c RH |
275 | #define CPP_ENDIAN_SPEC "\ |
276 | %{mlittle-endian:-D__LITTLE_ENDIAN__} \ | |
277 | %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}" | |
a0a301fc DE |
278 | |
279 | /* Macros to distinguish the particular subtarget. */ | |
280 | #define CPP_SUBTARGET_SPEC "" | |
281 | ||
282 | #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)" | |
283 | ||
b1fc14e5 RS |
284 | /* Prevent error on `-sun4' and `-target sun4' options. */ |
285 | /* This used to translate -dalign to -malign, but that is no good | |
286 | because it can't turn off the usual meaning of making debugging dumps. */ | |
bafb031b | 287 | /* Translate old style -m<cpu> into new style -mcpu=<cpu>. |
1cdbf242 | 288 | ??? Delete support for -m<cpu> for 2.9. */ |
bafb031b DE |
289 | |
290 | #define CC1_SPEC "\ | |
291 | %{sun4:} %{target:} \ | |
292 | %{mcypress:-mcpu=cypress} \ | |
293 | %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ | |
294 | %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ | |
295 | " | |
296 | ||
bafb031b DE |
297 | /* Override in target specific files. */ |
298 | #define ASM_CPU_SPEC "\ | |
9b7c06d2 | 299 | %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ |
bafb031b DE |
300 | %{msparclite:-Asparclite} \ |
301 | %{mf930:-Asparclite} %{mf934:-Asparclite} \ | |
302 | %{mcpu=sparclite:-Asparclite} \ | |
8d72ec32 | 303 | %{mcpu=sparclite86x:-Asparclite} \ |
bafb031b | 304 | %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ |
284d86e9 | 305 | %{mv8plus:-Av8plus} \ |
bafb031b | 306 | %{mcpu=v9:-Av9} \ |
284d86e9 | 307 | %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ |
fae15c93 | 308 | %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ |
a0a301fc | 309 | %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \ |
bafb031b DE |
310 | " |
311 | ||
e632a26c DE |
312 | /* Word size selection, among other things. |
313 | This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ | |
314 | ||
a0a301fc | 315 | #define ASM_ARCH32_SPEC "-32" |
6149cebb JJ |
316 | #ifdef HAVE_AS_REGISTER_PSEUDO_OP |
317 | #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" | |
318 | #else | |
a0a301fc | 319 | #define ASM_ARCH64_SPEC "-64" |
6149cebb | 320 | #endif |
a0a301fc | 321 | #define ASM_ARCH_DEFAULT_SPEC \ |
e632a26c | 322 | (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) |
a0a301fc DE |
323 | |
324 | #define ASM_ARCH_SPEC "\ | |
325 | %{m32:%(asm_arch32)} \ | |
326 | %{m64:%(asm_arch64)} \ | |
327 | %{!m32:%{!m64:%(asm_arch_default)}} \ | |
328 | " | |
329 | ||
e95b1e6a JJ |
330 | #ifdef HAVE_AS_RELAX_OPTION |
331 | #define ASM_RELAX_SPEC "%{!mno-relax:-relax}" | |
332 | #else | |
333 | #define ASM_RELAX_SPEC "" | |
334 | #endif | |
335 | ||
a0a301fc DE |
336 | /* Special flags to the Sun-4 assembler when using pipe for input. */ |
337 | ||
338 | #define ASM_SPEC "\ | |
24a4dd31 | 339 | %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \ |
e95b1e6a | 340 | %(asm_cpu) %(asm_relax)" |
a0a301fc | 341 | |
4977bab6 ZW |
342 | #define AS_NEEDS_DASH_FOR_PIPED_INPUT |
343 | ||
bafb031b DE |
344 | /* This macro defines names of additional specifications to put in the specs |
345 | that can be used in various specifications like CC1_SPEC. Its definition | |
346 | is an initializer with a subgrouping for each command option. | |
347 | ||
348 | Each subgrouping contains a string constant, that defines the | |
7ec022b2 | 349 | specification name, and a string constant that used by the GCC driver |
bafb031b DE |
350 | program. |
351 | ||
352 | Do not define this macro if it does not need to do anything. */ | |
1bb87f28 | 353 | |
a0a301fc | 354 | #define EXTRA_SPECS \ |
829245be KG |
355 | { "cpp_cpu", CPP_CPU_SPEC }, \ |
356 | { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ | |
357 | { "cpp_arch32", CPP_ARCH32_SPEC }, \ | |
358 | { "cpp_arch64", CPP_ARCH64_SPEC }, \ | |
359 | { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ | |
360 | { "cpp_arch", CPP_ARCH_SPEC }, \ | |
361 | { "cpp_endian", CPP_ENDIAN_SPEC }, \ | |
362 | { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ | |
363 | { "asm_cpu", ASM_CPU_SPEC }, \ | |
364 | { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ | |
365 | { "asm_arch32", ASM_ARCH32_SPEC }, \ | |
366 | { "asm_arch64", ASM_ARCH64_SPEC }, \ | |
e95b1e6a | 367 | { "asm_relax", ASM_RELAX_SPEC }, \ |
829245be KG |
368 | { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ |
369 | { "asm_arch", ASM_ARCH_SPEC }, \ | |
bafb031b | 370 | SUBTARGET_EXTRA_SPECS |
1bb87f28 | 371 | |
bafb031b | 372 | #define SUBTARGET_EXTRA_SPECS |
bbd7687d DM |
373 | |
374 | /* Because libgcc can generate references back to libc (via .umul etc.) we have | |
375 | to list libc again after the second libgcc. */ | |
376 | #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L" | |
377 | ||
bafb031b | 378 | \f |
82d6b402 RH |
379 | #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") |
380 | #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") | |
7a6cf439 DE |
381 | |
382 | /* ??? This should be 32 bits for v9 but what can we do? */ | |
1bb87f28 JW |
383 | #define WCHAR_TYPE "short unsigned int" |
384 | #define WCHAR_TYPE_SIZE 16 | |
385 | ||
4f074454 RK |
386 | /* Show we can debug even without a frame pointer. */ |
387 | #define CAN_DEBUG_WITHOUT_FP | |
1bb87f28 | 388 | |
89a8b315 | 389 | #define OVERRIDE_OPTIONS sparc_override_options () |
5b485d2c | 390 | |
1bb87f28 JW |
391 | /* Generate DBX debugging information. */ |
392 | ||
23532de9 | 393 | #define DBX_DEBUGGING_INFO 1 |
7a6cf439 | 394 | \f |
1bb87f28 JW |
395 | /* Run-time compilation parameters selecting different hardware subsets. */ |
396 | ||
397 | extern int target_flags; | |
398 | ||
399 | /* Nonzero if we should generate code to use the fpu. */ | |
7a6cf439 DE |
400 | #define MASK_FPU 1 |
401 | #define TARGET_FPU (target_flags & MASK_FPU) | |
1bb87f28 | 402 | |
95dea81f JW |
403 | /* Nonzero if we should assume that double pointers might be unaligned. |
404 | This can happen when linking gcc compiled code with other compilers, | |
405 | because the ABI only guarantees 4 byte alignment. */ | |
7a6cf439 DE |
406 | #define MASK_UNALIGNED_DOUBLES 4 |
407 | #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES) | |
408 | ||
885d8175 | 409 | /* Nonzero means that we should generate code for a v8 sparc. */ |
6f64bf5f | 410 | #define MASK_V8 0x8 |
7a6cf439 | 411 | #define TARGET_V8 (target_flags & MASK_V8) |
885d8175 | 412 | |
bc9e02ae JW |
413 | /* Nonzero means that we should generate code for a sparclite. |
414 | This enables the sparclite specific instructions, but does not affect | |
415 | whether FPU instructions are emitted. */ | |
6f64bf5f | 416 | #define MASK_SPARCLITE 0x10 |
7a6cf439 | 417 | #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE) |
885d8175 | 418 | |
bafb031b DE |
419 | /* Nonzero if we're compiling for the sparclet. */ |
420 | #define MASK_SPARCLET 0x20 | |
421 | #define TARGET_SPARCLET (target_flags & MASK_SPARCLET) | |
6f64bf5f DE |
422 | |
423 | /* Nonzero if we're compiling for v9 sparc. | |
424 | Note that v9's can run in 32 bit mode so this doesn't necessarily mean | |
bafb031b | 425 | the word size is 64. */ |
6f64bf5f DE |
426 | #define MASK_V9 0x40 |
427 | #define TARGET_V9 (target_flags & MASK_V9) | |
428 | ||
5e7a8ee0 | 429 | /* Nonzero to generate code that uses the instructions deprecated in |
bafb031b DE |
430 | the v9 architecture. This option only applies to v9 systems. */ |
431 | /* ??? This isn't user selectable yet. It's used to enable such insns | |
432 | on 32 bit v9 systems and for the moment they're permanently disabled | |
433 | on 64 bit v9 systems. */ | |
434 | #define MASK_DEPRECATED_V8_INSNS 0x80 | |
435 | #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS) | |
6f64bf5f | 436 | |
bafb031b DE |
437 | /* Mask of all CPU selection flags. */ |
438 | #define MASK_ISA \ | |
439 | (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS) | |
6f64bf5f | 440 | |
5e7a8ee0 | 441 | /* Nonzero means don't pass `-assert pure-text' to the linker. */ |
bafb031b DE |
442 | #define MASK_IMPURE_TEXT 0x100 |
443 | #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT) | |
5b485d2c | 444 | |
9a1c7cd7 | 445 | /* Nonzero means that we should generate code using a flat register window |
bafb031b DE |
446 | model, i.e. no save/restore instructions are generated, which is |
447 | compatible with normal sparc code. | |
448 | The frame pointer is %i7 instead of %fp. */ | |
7a6cf439 DE |
449 | #define MASK_FLAT 0x200 |
450 | #define TARGET_FLAT (target_flags & MASK_FLAT) | |
9a1c7cd7 | 451 | |
56149abc | 452 | /* Nonzero means use the registers that the SPARC ABI reserves for |
bafb031b DE |
453 | application software. This must be the default to coincide with the |
454 | setting in FIXED_REGISTERS. */ | |
7a6cf439 DE |
455 | #define MASK_APP_REGS 0x400 |
456 | #define TARGET_APP_REGS (target_flags & MASK_APP_REGS) | |
34ad7aaf | 457 | |
eb582c5d DE |
458 | /* Option to select how quad word floating point is implemented. |
459 | When TARGET_HARD_QUAD is true, we use the hardware quad instructions. | |
460 | Otherwise, we use the SPARC ABI quad library functions. */ | |
7a6cf439 DE |
461 | #define MASK_HARD_QUAD 0x800 |
462 | #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD) | |
463 | ||
5e7a8ee0 | 464 | /* Nonzero on little-endian machines. */ |
62f1c649 DE |
465 | /* ??? Little endian support currently only exists for sparclet-aout and |
466 | sparc64-elf configurations. May eventually want to expand the support | |
467 | to all targets, but for now it's kept local to only those two. */ | |
468 | #define MASK_LITTLE_ENDIAN 0x1000 | |
469 | #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN) | |
7a6cf439 | 470 | |
a0a301fc | 471 | /* 0x2000, 0x4000 are unused */ |
7a6cf439 | 472 | |
7def3512 | 473 | /* Nonzero if pointers are 64 bits. */ |
7a6cf439 DE |
474 | #define MASK_PTR64 0x8000 |
475 | #define TARGET_PTR64 (target_flags & MASK_PTR64) | |
476 | ||
a0a301fc DE |
477 | /* Nonzero if generating code to run in a 64 bit environment. |
478 | This is intended to only be used by TARGET_ARCH{32,64} as they are the | |
479 | mechanism used to control compile time or run time selection. */ | |
480 | #define MASK_64BIT 0x10000 | |
481 | #define TARGET_64BIT (target_flags & MASK_64BIT) | |
482 | ||
483 | /* 0x20000,0x40000 unused */ | |
7a6cf439 | 484 | |
5e7a8ee0 | 485 | /* Nonzero means use a stack bias of 2047. Stack offsets are obtained by |
7a6cf439 DE |
486 | adding 2047 to %sp. This option is for v9 only and is the default. */ |
487 | #define MASK_STACK_BIAS 0x80000 | |
488 | #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS) | |
8248e2bc | 489 | |
e6c1be7e | 490 | /* 0x100000,0x200000 unused */ |
9b7c06d2 | 491 | |
5e7a8ee0 | 492 | /* Nonzero means -m{,no-}fpu was passed on the command line. */ |
1f1406b4 DE |
493 | #define MASK_FPU_SET 0x400000 |
494 | #define TARGET_FPU_SET (target_flags & MASK_FPU_SET) | |
495 | ||
bfd6bc60 | 496 | /* Use the UltraSPARC Visual Instruction Set extensions. */ |
3aabf9a5 | 497 | #define MASK_VIS 0x1000000 |
bfd6bc60 JC |
498 | #define TARGET_VIS (target_flags & MASK_VIS) |
499 | ||
284d86e9 | 500 | /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of |
5cb01b65 JJ |
501 | the current out and global registers and Linux 2.2+ as well. */ |
502 | #define MASK_V8PLUS 0x2000000 | |
3aabf9a5 | 503 | #define TARGET_V8PLUS (target_flags & MASK_V8PLUS) |
bfd6bc60 | 504 | |
c219ddf7 BK |
505 | /* Force a the fastest alignment on structures to take advantage of |
506 | faster copies. */ | |
507 | #define MASK_FASTER_STRUCTS 0x4000000 | |
508 | #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS) | |
509 | ||
4710d3eb JJ |
510 | /* Use IEEE quad long double. */ |
511 | #define MASK_LONG_DOUBLE_128 0x8000000 | |
512 | #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128) | |
513 | ||
284d86e9 JC |
514 | /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y. |
515 | TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y | |
516 | to get high 32 bits. False in V8+ or V9 because multiply stores | |
517 | a 64 bit result in a register. */ | |
518 | ||
bfd6bc60 JC |
519 | #define TARGET_HARD_MUL32 \ |
520 | ((TARGET_V8 || TARGET_SPARCLITE \ | |
521 | || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \ | |
5cb01b65 | 522 | && ! TARGET_V8PLUS && TARGET_ARCH32) |
bfd6bc60 JC |
523 | |
524 | #define TARGET_HARD_MUL \ | |
525 | (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \ | |
3aabf9a5 | 526 | || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS) |
bfd6bc60 JC |
527 | |
528 | ||
1bb87f28 JW |
529 | /* Macro to define tables used to set the flags. |
530 | This is a list in braces of pairs in braces, | |
531 | each pair being { "NAME", VALUE } | |
532 | where VALUE is the bits to set or minus the bits to clear. | |
533 | An empty string NAME is used to identify the default VALUE. */ | |
534 | ||
535 | #define TARGET_SWITCHES \ | |
047142d3 PT |
536 | { {"fpu", MASK_FPU | MASK_FPU_SET, \ |
537 | N_("Use hardware fp") }, \ | |
538 | {"no-fpu", -MASK_FPU, \ | |
539 | N_("Do not use hardware fp") }, \ | |
46cc13b3 | 540 | {"no-fpu", MASK_FPU_SET, NULL, }, \ |
047142d3 PT |
541 | {"hard-float", MASK_FPU | MASK_FPU_SET, \ |
542 | N_("Use hardware fp") }, \ | |
543 | {"soft-float", -MASK_FPU, \ | |
544 | N_("Do not use hardware fp") }, \ | |
545 | {"soft-float", MASK_FPU_SET, NULL }, \ | |
047142d3 PT |
546 | {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \ |
547 | N_("Assume possible double misalignment") }, \ | |
548 | {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \ | |
549 | N_("Assume all doubles are aligned") }, \ | |
550 | {"impure-text", MASK_IMPURE_TEXT, \ | |
551 | N_("Pass -assert pure-text to linker") }, \ | |
552 | {"no-impure-text", -MASK_IMPURE_TEXT, \ | |
553 | N_("Do not pass -assert pure-text to linker") }, \ | |
554 | {"flat", MASK_FLAT, \ | |
555 | N_("Use flat register window model") }, \ | |
556 | {"no-flat", -MASK_FLAT, \ | |
557 | N_("Do not use flat register window model") }, \ | |
558 | {"app-regs", MASK_APP_REGS, \ | |
559 | N_("Use ABI reserved registers") }, \ | |
560 | {"no-app-regs", -MASK_APP_REGS, \ | |
561 | N_("Do not use ABI reserved registers") }, \ | |
562 | {"hard-quad-float", MASK_HARD_QUAD, \ | |
563 | N_("Use hardware quad fp instructions") }, \ | |
564 | {"soft-quad-float", -MASK_HARD_QUAD, \ | |
565 | N_("Do not use hardware quad fp instructions") }, \ | |
566 | {"v8plus", MASK_V8PLUS, \ | |
567 | N_("Compile for v8plus ABI") }, \ | |
568 | {"no-v8plus", -MASK_V8PLUS, \ | |
569 | N_("Do not compile for v8plus ABI") }, \ | |
570 | {"vis", MASK_VIS, \ | |
571 | N_("Utilize Visual Instruction Set") }, \ | |
572 | {"no-vis", -MASK_VIS, \ | |
573 | N_("Do not utilize Visual Instruction Set") }, \ | |
a0a301fc | 574 | /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \ |
047142d3 PT |
575 | {"cypress", 0, \ |
576 | N_("Optimize for Cypress processors") }, \ | |
577 | {"sparclite", 0, \ | |
56149abc | 578 | N_("Optimize for SPARCLite processors") }, \ |
047142d3 PT |
579 | {"f930", 0, \ |
580 | N_("Optimize for F930 processors") }, \ | |
581 | {"f934", 0, \ | |
582 | N_("Optimize for F934 processors") }, \ | |
583 | {"v8", 0, \ | |
56149abc | 584 | N_("Use V8 SPARC ISA") }, \ |
047142d3 | 585 | {"supersparc", 0, \ |
56149abc | 586 | N_("Optimize for SuperSPARC processors") }, \ |
047142d3 PT |
587 | /* End of deprecated options. */ \ |
588 | {"ptr64", MASK_PTR64, \ | |
589 | N_("Pointers are 64-bit") }, \ | |
590 | {"ptr32", -MASK_PTR64, \ | |
591 | N_("Pointers are 32-bit") }, \ | |
592 | {"32", -MASK_64BIT, \ | |
593 | N_("Use 32-bit ABI") }, \ | |
594 | {"64", MASK_64BIT, \ | |
595 | N_("Use 64-bit ABI") }, \ | |
596 | {"stack-bias", MASK_STACK_BIAS, \ | |
597 | N_("Use stack bias") }, \ | |
598 | {"no-stack-bias", -MASK_STACK_BIAS, \ | |
599 | N_("Do not use stack bias") }, \ | |
600 | {"faster-structs", MASK_FASTER_STRUCTS, \ | |
601 | N_("Use structs on stronger alignment for double-word copies") }, \ | |
602 | {"no-faster-structs", -MASK_FASTER_STRUCTS, \ | |
603 | N_("Do not use structs on stronger alignment for double-word copies") }, \ | |
604 | {"relax", 0, \ | |
605 | N_("Optimize tail call instructions in assembler and linker") }, \ | |
606 | {"no-relax", 0, \ | |
607 | N_("Do not optimize tail call instructions in assembler or linker") }, \ | |
7a6cf439 | 608 | SUBTARGET_SWITCHES \ |
ee76cf2a | 609 | { "", TARGET_DEFAULT, ""}} |
1bb87f28 | 610 | |
bafb031b DE |
611 | /* MASK_APP_REGS must always be the default because that's what |
612 | FIXED_REGISTERS is set to and -ffixed- is processed before | |
613 | CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */ | |
33074e5f | 614 | #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) |
84ab3bfb | 615 | |
bafb031b | 616 | /* This is meant to be redefined in target specific files. */ |
84ab3bfb | 617 | #define SUBTARGET_SWITCHES |
1bb87f28 | 618 | |
6afca97d DE |
619 | /* Processor type. |
620 | These must match the values for the cpu attribute in sparc.md. */ | |
621 | enum processor_type { | |
622 | PROCESSOR_V7, | |
623 | PROCESSOR_CYPRESS, | |
624 | PROCESSOR_V8, | |
625 | PROCESSOR_SUPERSPARC, | |
626 | PROCESSOR_SPARCLITE, | |
627 | PROCESSOR_F930, | |
628 | PROCESSOR_F934, | |
8947065c RH |
629 | PROCESSOR_HYPERSPARC, |
630 | PROCESSOR_SPARCLITE86X, | |
6afca97d | 631 | PROCESSOR_SPARCLET, |
9b7c06d2 | 632 | PROCESSOR_TSC701, |
6afca97d | 633 | PROCESSOR_V9, |
fae15c93 VM |
634 | PROCESSOR_ULTRASPARC, |
635 | PROCESSOR_ULTRASPARC3 | |
6afca97d DE |
636 | }; |
637 | ||
638 | /* This is set from -m{cpu,tune}=xxx. */ | |
639 | extern enum processor_type sparc_cpu; | |
640 | ||
641 | /* Recast the cpu class to be the cpu attribute. | |
642 | Every file includes us, but not every file includes insn-attr.h. */ | |
643 | #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) | |
bafb031b | 644 | |
bafb031b | 645 | #define TARGET_OPTIONS \ |
047142d3 PT |
646 | { \ |
647 | { "cpu=", &sparc_select[1].string, \ | |
c409ea0d | 648 | N_("Use features of and schedule code for given CPU"), 0}, \ |
047142d3 | 649 | { "tune=", &sparc_select[2].string, \ |
c409ea0d | 650 | N_("Schedule code for given CPU"), 0}, \ |
047142d3 | 651 | { "cmodel=", &sparc_cmodel_string, \ |
c409ea0d | 652 | N_("Use given SPARC code model"), 0}, \ |
047142d3 | 653 | SUBTARGET_OPTIONS \ |
bafb031b DE |
654 | } |
655 | ||
656 | /* This is meant to be redefined in target specific files. */ | |
657 | #define SUBTARGET_OPTIONS | |
6afca97d | 658 | |
7816bea0 DJ |
659 | /* Support for a compile-time default CPU, et cetera. The rules are: |
660 | --with-cpu is ignored if -mcpu is specified. | |
661 | --with-tune is ignored if -mtune is specified. | |
662 | --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu | |
663 | are specified. */ | |
664 | #define OPTION_DEFAULT_SPECS \ | |
665 | {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ | |
666 | {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ | |
667 | {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" } | |
668 | ||
6afca97d DE |
669 | /* sparc_select[0] is reserved for the default cpu. */ |
670 | struct sparc_cpu_select | |
671 | { | |
3bb5de61 | 672 | const char *string; |
8b60264b KG |
673 | const char *const name; |
674 | const int set_tune_p; | |
675 | const int set_arch_p; | |
6afca97d DE |
676 | }; |
677 | ||
678 | extern struct sparc_cpu_select sparc_select[]; | |
7a6cf439 DE |
679 | \f |
680 | /* target machine storage layout */ | |
681 | ||
1bb87f28 JW |
682 | /* Define this if most significant bit is lowest numbered |
683 | in instructions that operate on numbered bit-fields. */ | |
684 | #define BITS_BIG_ENDIAN 1 | |
685 | ||
686 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
1bb87f28 JW |
687 | #define BYTES_BIG_ENDIAN 1 |
688 | ||
689 | /* Define this if most significant word of a multiword number is the lowest | |
690 | numbered. */ | |
1bb87f28 JW |
691 | #define WORDS_BIG_ENDIAN 1 |
692 | ||
62f1c649 DE |
693 | /* Define this to set the endianness to use in libgcc2.c, which can |
694 | not depend on target_flags. */ | |
8947065c | 695 | #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__) |
62f1c649 DE |
696 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 |
697 | #else | |
698 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
699 | #endif | |
700 | ||
7a6cf439 | 701 | #define MAX_BITS_PER_WORD 64 |
1bb87f28 JW |
702 | |
703 | /* Width of a word, in units (bytes). */ | |
6f64bf5f | 704 | #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) |
8b156b3e JJ |
705 | #ifdef IN_LIBGCC2 |
706 | #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
707 | #else | |
ef0e53ce | 708 | #define MIN_UNITS_PER_WORD 4 |
8b156b3e | 709 | #endif |
7a6cf439 DE |
710 | |
711 | /* Now define the sizes of the C data types. */ | |
712 | ||
713 | #define SHORT_TYPE_SIZE 16 | |
a0a301fc DE |
714 | #define INT_TYPE_SIZE 32 |
715 | #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) | |
7a6cf439 DE |
716 | #define LONG_LONG_TYPE_SIZE 64 |
717 | #define FLOAT_TYPE_SIZE 32 | |
718 | #define DOUBLE_TYPE_SIZE 64 | |
719 | ||
3276910d | 720 | #ifdef SPARC_BI_ARCH |
7a6cf439 | 721 | #define MAX_LONG_TYPE_SIZE 64 |
a0a301fc | 722 | #endif |
7a6cf439 | 723 | |
a0a301fc | 724 | #if 0 |
7a6cf439 DE |
725 | /* ??? This does not work in SunOS 4.x, so it is not enabled here. |
726 | Instead, it is enabled in sol2.h, because it does work under Solaris. */ | |
ba31d94e | 727 | /* Define for support of TFmode long double. |
56149abc | 728 | SPARC ABI says that long double is 4 words. */ |
7a6cf439 DE |
729 | #define LONG_DOUBLE_TYPE_SIZE 128 |
730 | #endif | |
1bb87f28 JW |
731 | |
732 | /* Width in bits of a pointer. | |
733 | See also the macro `Pmode' defined below. */ | |
7a6cf439 | 734 | #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) |
1bb87f28 | 735 | |
3276910d RK |
736 | /* If we have to extend pointers (only when TARGET_ARCH64 and not |
737 | TARGET_PTR64), we want to do it unsigned. This macro does nothing | |
738 | if ptr_mode and Pmode are the same. */ | |
739 | #define POINTERS_EXTEND_UNSIGNED 1 | |
740 | ||
4fb4e4b8 DE |
741 | /* A macro to update MODE and UNSIGNEDP when an object whose type |
742 | is TYPE and which has the specified mode and signedness is to be | |
743 | stored in a register. This macro is only called when TYPE is a | |
744 | scalar type. */ | |
745 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
746 | if (TARGET_ARCH64 \ | |
747 | && GET_MODE_CLASS (MODE) == MODE_INT \ | |
748 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
3276910d | 749 | (MODE) = DImode; |
4fb4e4b8 DE |
750 | |
751 | /* Define this macro if the promotion described by PROMOTE_MODE | |
752 | should also be done for outgoing function arguments. */ | |
753 | /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op | |
754 | for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test | |
755 | for this value. */ | |
756 | #define PROMOTE_FUNCTION_ARGS | |
757 | ||
758 | /* Define this macro if the promotion described by PROMOTE_MODE | |
759 | should also be done for the return value of functions. | |
760 | If this macro is defined, FUNCTION_VALUE must perform the same | |
761 | promotions done by PROMOTE_MODE. */ | |
762 | /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op | |
763 | for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test | |
764 | for this value. */ | |
765 | #define PROMOTE_FUNCTION_RETURN | |
766 | ||
47841d1b JJ |
767 | /* Define this macro if the promotion described by PROMOTE_MODE |
768 | should _only_ be performed for outgoing function arguments or | |
769 | function return values, as specified by PROMOTE_FUNCTION_ARGS | |
770 | and PROMOTE_FUNCTION_RETURN, respectively. */ | |
771 | /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op | |
772 | for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test | |
773 | for this value. For TARGET_ARCH64 we need it, as we don't have instructions | |
774 | for arithmetic operations which do zero/sign extension at the same time, | |
775 | so without this we end up with a srl/sra after every assignment to an | |
776 | user variable, which means very very bad code. */ | |
777 | #define PROMOTE_FOR_CALL_ONLY | |
778 | ||
1bb87f28 | 779 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
6f64bf5f | 780 | #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) |
1bb87f28 JW |
781 | |
782 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
6f64bf5f | 783 | #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) |
1bb87f28 | 784 | |
10d1b70f JW |
785 | /* ALIGN FRAMES on double word boundaries */ |
786 | ||
7a6cf439 | 787 | #define SPARC_STACK_ALIGN(LOC) \ |
6f64bf5f | 788 | (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) |
10d1b70f | 789 | |
1bb87f28 | 790 | /* Allocation boundary (in *bits*) for the code of a function. */ |
efa3896a | 791 | #define FUNCTION_BOUNDARY 32 |
1bb87f28 JW |
792 | |
793 | /* Alignment of field after `int : 0' in a structure. */ | |
6f64bf5f | 794 | #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) |
1bb87f28 JW |
795 | |
796 | /* Every structure's size must be a multiple of this. */ | |
797 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
798 | ||
43a88a8c | 799 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
1bb87f28 JW |
800 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
801 | ||
802 | /* No data type wants to be aligned rounder than this. */ | |
6f64bf5f | 803 | #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) |
1bb87f28 | 804 | |
77a02b01 JW |
805 | /* The best alignment to use in cases where we have a choice. */ |
806 | #define FASTEST_ALIGNMENT 64 | |
807 | ||
c219ddf7 BK |
808 | /* Define this macro as an expression for the alignment of a structure |
809 | (given by STRUCT as a tree node) if the alignment computed in the | |
810 | usual way is COMPUTED and the alignment explicitly specified was | |
811 | SPECIFIED. | |
812 | ||
813 | The default is to use SPECIFIED if it is larger; otherwise, use | |
814 | the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ | |
815 | #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ | |
816 | (TARGET_FASTER_STRUCTS ? \ | |
817 | ((TREE_CODE (STRUCT) == RECORD_TYPE \ | |
818 | || TREE_CODE (STRUCT) == UNION_TYPE \ | |
819 | || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ | |
820 | && TYPE_FIELDS (STRUCT) != 0 \ | |
821 | ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ | |
822 | : MAX ((COMPUTED), (SPECIFIED))) \ | |
823 | : MAX ((COMPUTED), (SPECIFIED))) | |
824 | ||
1bb87f28 JW |
825 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
826 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
d2a8e680 RS |
827 | ((TREE_CODE (EXP) == STRING_CST \ |
828 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
829 | ? FASTEST_ALIGNMENT : (ALIGN)) | |
1bb87f28 JW |
830 | |
831 | /* Make arrays of chars word-aligned for the same reasons. */ | |
832 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
833 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
834 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
77a02b01 | 835 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) |
1bb87f28 | 836 | |
b4ac57ab | 837 | /* Set this nonzero if move instructions will actually fail to work |
1bb87f28 | 838 | when given unaligned data. */ |
b4ac57ab | 839 | #define STRICT_ALIGNMENT 1 |
1bb87f28 JW |
840 | |
841 | /* Things that must be doubleword aligned cannot go in the text section, | |
842 | because the linker fails to align the text section enough! | |
7a6cf439 | 843 | Put them in the data section. This macro is only used in this file. */ |
1bb87f28 JW |
844 | #define MAX_TEXT_ALIGN 32 |
845 | ||
68d69835 JM |
846 | /* This forces all variables and constants to the data section when PIC. |
847 | This is because the SunOS 4 shared library scheme thinks everything in | |
848 | text is a function, and patches the address to point to a loader stub. */ | |
849 | /* This is defined to zero for every system which doesn't use the a.out object | |
850 | file format. */ | |
851 | #ifndef SUNOS4_SHARED_LIBRARIES | |
852 | #define SUNOS4_SHARED_LIBRARIES 0 | |
853 | #endif | |
1bb87f28 JW |
854 | \f |
855 | /* Standard register usage. */ | |
856 | ||
857 | /* Number of actual hardware registers. | |
858 | The hardware registers are assigned numbers for the compiler | |
859 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
860 | All registers that the compiler knows about must be given numbers, | |
861 | even those that are not normally considered general registers. | |
862 | ||
7a6cf439 DE |
863 | SPARC has 32 integer registers and 32 floating point registers. |
864 | 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not | |
865 | accessible. We still account for them to simplify register computations | |
866 | (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so | |
867 | 32+32+32+4 == 100. | |
563c12b0 RH |
868 | Register 100 is used as the integer condition code register. |
869 | Register 101 is used as the soft frame pointer register. */ | |
1bb87f28 | 870 | |
563c12b0 | 871 | #define FIRST_PSEUDO_REGISTER 102 |
6afca97d | 872 | |
4fb4e4b8 | 873 | #define SPARC_FIRST_FP_REG 32 |
6afca97d | 874 | /* Additional V9 fp regs. */ |
4fb4e4b8 DE |
875 | #define SPARC_FIRST_V9_FP_REG 64 |
876 | #define SPARC_LAST_V9_FP_REG 95 | |
c4ce6853 DE |
877 | /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ |
878 | #define SPARC_FIRST_V9_FCC_REG 96 | |
879 | #define SPARC_LAST_V9_FCC_REG 99 | |
880 | /* V8 fcc reg. */ | |
881 | #define SPARC_FCC_REG 96 | |
882 | /* Integer CC reg. We don't distinguish %icc from %xcc. */ | |
883 | #define SPARC_ICC_REG 100 | |
1bb87f28 | 884 | |
4fb4e4b8 DE |
885 | /* Nonzero if REGNO is an fp reg. */ |
886 | #define SPARC_FP_REG_P(REGNO) \ | |
887 | ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) | |
888 | ||
889 | /* Argument passing regs. */ | |
890 | #define SPARC_OUTGOING_INT_ARG_FIRST 8 | |
a9e95099 | 891 | #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) |
4fb4e4b8 DE |
892 | #define SPARC_FP_ARG_FIRST 32 |
893 | ||
1bb87f28 JW |
894 | /* 1 for registers that have pervasive standard uses |
895 | and are not available for the register allocator. | |
4fb4e4b8 | 896 | |
7a6cf439 | 897 | On non-v9 systems: |
34ad7aaf JW |
898 | g1 is free to use as temporary. |
899 | g2-g4 are reserved for applications. Gcc normally uses them as | |
900 | temporaries, but this can be disabled via the -mno-app-regs option. | |
7a6cf439 | 901 | g5 through g7 are reserved for the operating system. |
4fb4e4b8 | 902 | |
7a6cf439 | 903 | On v9 systems: |
a0a301fc DE |
904 | g1,g5 are free to use as temporaries, and are free to use between calls |
905 | if the call is to an external function via the PLT. | |
906 | g4 is free to use as a temporary in the non-embedded case. | |
907 | g4 is reserved in the embedded case. | |
4fb4e4b8 | 908 | g2-g3 are reserved for applications. Gcc normally uses them as |
bafb031b | 909 | temporaries, but this can be disabled via the -mno-app-regs option. |
a0a301fc DE |
910 | g6-g7 are reserved for the operating system (or application in |
911 | embedded case). | |
7a6cf439 DE |
912 | ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must |
913 | currently be a fixed register until this pattern is rewritten. | |
914 | Register 1 is also used when restoring call-preserved registers in large | |
6afca97d DE |
915 | stack frames. |
916 | ||
917 | Registers fixed in arch32 and not arch64 (or vice-versa) are marked in | |
918 | CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. | |
919 | */ | |
7a6cf439 | 920 | |
7a6cf439 | 921 | #define FIXED_REGISTERS \ |
e48addee | 922 | {1, 0, 2, 2, 2, 2, 1, 1, \ |
7a6cf439 DE |
923 | 0, 0, 0, 0, 0, 0, 1, 0, \ |
924 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
925 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
926 | \ | |
927 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
928 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
929 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
930 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
931 | \ | |
932 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
933 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
934 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
935 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
936 | \ | |
563c12b0 | 937 | 0, 0, 0, 0, 0, 1} |
1bb87f28 JW |
938 | |
939 | /* 1 for registers not available across function calls. | |
940 | These must include the FIXED_REGISTERS and also any | |
941 | registers that can be used without being saved. | |
942 | The latter must include the registers where values are returned | |
943 | and the register where structure-value addresses are passed. | |
944 | Aside from that, you can include as many other registers as you like. */ | |
7a6cf439 | 945 | |
bafb031b DE |
946 | #define CALL_USED_REGISTERS \ |
947 | {1, 1, 1, 1, 1, 1, 1, 1, \ | |
948 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
949 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
950 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
951 | \ | |
952 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
953 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
954 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
955 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
956 | \ | |
957 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
958 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
959 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
960 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
961 | \ | |
563c12b0 | 962 | 1, 1, 1, 1, 1, 1} |
1bb87f28 | 963 | |
c4ce6853 DE |
964 | /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that |
965 | they won't be allocated. */ | |
26c5587d JW |
966 | |
967 | #define CONDITIONAL_REGISTER_USAGE \ | |
968 | do \ | |
969 | { \ | |
5b43fed1 | 970 | if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ |
c7b2eb81 VM |
971 | { \ |
972 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
973 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
974 | } \ | |
e48addee | 975 | /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \ |
5e7a8ee0 | 976 | /* then honor it. */ \ |
e48addee JJ |
977 | if (TARGET_ARCH32 && fixed_regs[5]) \ |
978 | fixed_regs[5] = 1; \ | |
979 | else if (TARGET_ARCH64 && fixed_regs[5] == 2) \ | |
980 | fixed_regs[5] = 0; \ | |
6afca97d DE |
981 | if (! TARGET_V9) \ |
982 | { \ | |
983 | int regno; \ | |
984 | for (regno = SPARC_FIRST_V9_FP_REG; \ | |
985 | regno <= SPARC_LAST_V9_FP_REG; \ | |
986 | regno++) \ | |
987 | fixed_regs[regno] = 1; \ | |
c4ce6853 DE |
988 | /* %fcc0 is used by v8 and v9. */ \ |
989 | for (regno = SPARC_FIRST_V9_FCC_REG + 1; \ | |
990 | regno <= SPARC_LAST_V9_FCC_REG; \ | |
991 | regno++) \ | |
992 | fixed_regs[regno] = 1; \ | |
6afca97d | 993 | } \ |
26c5587d JW |
994 | if (! TARGET_FPU) \ |
995 | { \ | |
996 | int regno; \ | |
c4ce6853 | 997 | for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \ |
26c5587d JW |
998 | fixed_regs[regno] = 1; \ |
999 | } \ | |
e48addee | 1000 | /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \ |
5e7a8ee0 | 1001 | /* then honor it. Likewise with g3 and g4. */ \ |
e48addee JJ |
1002 | if (fixed_regs[2] == 2) \ |
1003 | fixed_regs[2] = ! TARGET_APP_REGS; \ | |
1004 | if (fixed_regs[3] == 2) \ | |
1005 | fixed_regs[3] = ! TARGET_APP_REGS; \ | |
1006 | if (TARGET_ARCH32 && fixed_regs[4] == 2) \ | |
1007 | fixed_regs[4] = ! TARGET_APP_REGS; \ | |
1008 | else if (TARGET_CM_EMBMEDANY) \ | |
1009 | fixed_regs[4] = 1; \ | |
1010 | else if (fixed_regs[4] == 2) \ | |
1011 | fixed_regs[4] = 0; \ | |
5c56efde DE |
1012 | if (TARGET_FLAT) \ |
1013 | { \ | |
d70e94ec | 1014 | int regno; \ |
5c56efde DE |
1015 | /* Let the compiler believe the frame pointer is still \ |
1016 | %fp, but output it as %i7. */ \ | |
1017 | fixed_regs[31] = 1; \ | |
563c12b0 | 1018 | reg_names[HARD_FRAME_POINTER_REGNUM] = "%i7"; \ |
7d167afd | 1019 | /* Disable leaf functions */ \ |
2e09e75a | 1020 | memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); \ |
d70e94ec JJ |
1021 | /* Make LEAF_REG_REMAP a noop. */ \ |
1022 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \ | |
1023 | leaf_reg_remap [regno] = regno; \ | |
5c56efde | 1024 | } \ |
26c5587d JW |
1025 | } \ |
1026 | while (0) | |
1027 | ||
1bb87f28 JW |
1028 | /* Return number of consecutive hard regs needed starting at reg REGNO |
1029 | to hold something of mode MODE. | |
1030 | This is ordinarily the length in words of a value of mode MODE | |
1031 | but can be less for certain modes in special long registers. | |
1032 | ||
1033 | On SPARC, ordinary registers hold 32 bits worth; | |
1034 | this means both integer and floating point registers. | |
7a6cf439 DE |
1035 | On v9, integer regs hold 64 bits worth; floating point regs hold |
1036 | 32 bits worth (this includes the new fp regs as even the odd ones are | |
1037 | included in the hard register count). */ | |
1bb87f28 | 1038 | |
7a6cf439 | 1039 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
6f64bf5f | 1040 | (TARGET_ARCH64 \ |
563c12b0 RH |
1041 | ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \ |
1042 | ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ | |
1043 | : (GET_MODE_SIZE (MODE) + 3) / 4) \ | |
7a6cf439 | 1044 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) |
1bb87f28 | 1045 | |
fae778eb | 1046 | /* Due to the ARCH64 discrepancy above we must override this next |
ec8e621d | 1047 | macro too. */ |
ddef6bc7 JJ |
1048 | #define REGMODE_NATURAL_SIZE(MODE) \ |
1049 | ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD) | |
284d86e9 | 1050 | |
1bb87f28 | 1051 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. |
923a8d06 | 1052 | See sparc.c for how we initialize this. */ |
0b5826ac | 1053 | extern const int *hard_regno_mode_classes; |
7a6cf439 | 1054 | extern int sparc_mode_class[]; |
ddef6bc7 JJ |
1055 | |
1056 | /* ??? Because of the funny way we pass parameters we should allow certain | |
1057 | ??? types of float/complex values to be in integer registers during | |
1058 | ??? RTL generation. This only matters on arch32. */ | |
1bb87f28 | 1059 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
7a6cf439 | 1060 | ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) |
1bb87f28 JW |
1061 | |
1062 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1063 | when one has mode MODE1 and one has mode MODE2. | |
1064 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
7a6cf439 DE |
1065 | for any hard reg, then this must be 0 for correct output. |
1066 | ||
1067 | For V9: SFmode can't be combined with other float modes, because they can't | |
1068 | be allocated to the %d registers. Also, DFmode won't fit in odd %f | |
1069 | registers, but SFmode will. */ | |
1bb87f28 | 1070 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
7a6cf439 DE |
1071 | ((MODE1) == (MODE2) \ |
1072 | || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ | |
1073 | && (! TARGET_V9 \ | |
1074 | || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ | |
1075 | || (MODE1 != SFmode && MODE2 != SFmode))))) | |
1bb87f28 JW |
1076 | |
1077 | /* Specify the registers used for certain standard purposes. | |
1078 | The values of these macros are register numbers. */ | |
1079 | ||
1080 | /* SPARC pc isn't overloaded on a register that the compiler knows about. */ | |
1081 | /* #define PC_REGNUM */ | |
1082 | ||
1083 | /* Register to use for pushing function arguments. */ | |
1084 | #define STACK_POINTER_REGNUM 14 | |
1085 | ||
563c12b0 RH |
1086 | /* The stack bias (amount by which the hardware register is offset by). */ |
1087 | #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) | |
1088 | ||
4fb4e4b8 | 1089 | /* Actual top-of-stack address is 92/176 greater than the contents of the |
7a6cf439 DE |
1090 | stack pointer register for !v9/v9. That is: |
1091 | - !v9: 64 bytes for the in and local registers, 4 bytes for structure return | |
4fb4e4b8 DE |
1092 | address, and 6*4 bytes for the 6 register parameters. |
1093 | - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer | |
1094 | parameter regs. */ | |
563c12b0 | 1095 | #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) |
1ccfa253 | 1096 | |
1bb87f28 | 1097 | /* Base register for access to local variables of the function. */ |
563c12b0 RH |
1098 | #define HARD_FRAME_POINTER_REGNUM 30 |
1099 | ||
1100 | /* The soft frame pointer does not have the stack bias applied. */ | |
1101 | #define FRAME_POINTER_REGNUM 101 | |
1102 | ||
1103 | /* Given the stack bias, the stack pointer isn't actually aligned. */ | |
1104 | #define INIT_EXPANDERS \ | |
1105 | do { \ | |
1106 | if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \ | |
1107 | { \ | |
1108 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \ | |
1109 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \ | |
1110 | } \ | |
1111 | } while (0) | |
1bb87f28 JW |
1112 | |
1113 | /* Value should be nonzero if functions must have frame pointers. | |
1114 | Zero means the frame pointer need not be set up (and parms | |
1115 | may be accessed via the stack pointer) in functions that seem suitable. | |
1116 | This is computed in `reload', in reload1.c. | |
a061b9fa | 1117 | Used in flow.c, global.c, and reload1.c. |
1bb87f28 | 1118 | |
a061b9fa DE |
1119 | Being a non-leaf function does not mean a frame pointer is needed in the |
1120 | flat window model. However, the debugger won't be able to backtrace through | |
1121 | us with out it. */ | |
563c12b0 RH |
1122 | #define FRAME_POINTER_REQUIRED \ |
1123 | (TARGET_FLAT \ | |
1124 | ? (current_function_calls_alloca \ | |
563c12b0 | 1125 | || !leaf_function_p ()) \ |
5c56efde | 1126 | : ! (leaf_function_p () && only_leaf_regs_used ())) |
1bb87f28 | 1127 | |
1bb87f28 | 1128 | /* Base register for access to arguments of the function. */ |
5c56efde | 1129 | #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM |
1bb87f28 | 1130 | |
6098b63e | 1131 | /* Register in which static-chain is passed to a function. This must |
c8392688 | 1132 | not be a register used by the prologue. */ |
6f64bf5f | 1133 | #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) |
1bb87f28 JW |
1134 | |
1135 | /* Register which holds offset table for position-independent | |
1136 | data references. */ | |
1137 | ||
5b43fed1 | 1138 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM) |
1bb87f28 | 1139 | |
82d6b402 RH |
1140 | /* Pick a default value we can notice from override_options: |
1141 | !v9: Default is on. | |
1142 | v9: Default is off. */ | |
1143 | ||
1144 | #define DEFAULT_PCC_STRUCT_RETURN -1 | |
1145 | ||
56149abc | 1146 | /* SPARC ABI says that quad-precision floats and all structures are returned |
7a6cf439 | 1147 | in memory. |
4fb4e4b8 | 1148 | For v9: unions <= 32 bytes in size are returned in int regs, |
82d6b402 | 1149 | structures up to 32 bytes are returned in int and fp regs. */ |
4fb4e4b8 | 1150 | |
686667bf | 1151 | #define RETURN_IN_MEMORY(TYPE) \ |
4fb4e4b8 DE |
1152 | (TARGET_ARCH32 \ |
1153 | ? (TYPE_MODE (TYPE) == BLKmode \ | |
1154 | || TYPE_MODE (TYPE) == TFmode \ | |
1155 | || TYPE_MODE (TYPE) == TCmode) \ | |
82d6b402 | 1156 | : (TYPE_MODE (TYPE) == BLKmode \ |
f07d22aa | 1157 | && (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 32)) |
d9ca49d5 | 1158 | |
1bb87f28 JW |
1159 | /* Functions which return large structures get the address |
1160 | to place the wanted value at offset 64 from the frame. | |
7a6cf439 DE |
1161 | Must reserve 64 bytes for the in and local registers. |
1162 | v9: Functions which return large structures get the address to place the | |
1163 | wanted value from an invisible first argument. */ | |
1bb87f28 JW |
1164 | /* Used only in other #defines in this file. */ |
1165 | #define STRUCT_VALUE_OFFSET 64 | |
1166 | ||
1167 | #define STRUCT_VALUE \ | |
6f64bf5f | 1168 | (TARGET_ARCH64 \ |
7a6cf439 | 1169 | ? 0 \ |
c5c76735 JL |
1170 | : gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \ |
1171 | STRUCT_VALUE_OFFSET))) | |
1172 | ||
1bb87f28 | 1173 | #define STRUCT_VALUE_INCOMING \ |
c5c76735 JL |
1174 | (TARGET_ARCH64 \ |
1175 | ? 0 \ | |
1176 | : gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, \ | |
1177 | STRUCT_VALUE_OFFSET))) | |
1bb87f28 JW |
1178 | \f |
1179 | /* Define the classes of registers for register constraints in the | |
1180 | machine description. Also define ranges of constants. | |
1181 | ||
1182 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1183 | If there is more than one class, another class must be named NO_REGS | |
1184 | and contain no registers. | |
1185 | ||
1186 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1187 | another name such as ALL_REGS). This is the class of registers | |
1188 | that is allowed by "g" or "r" in a register constraint. | |
1189 | Also, registers outside this class are allocated only when | |
1190 | instructions express preferences for them. | |
1191 | ||
1192 | The classes must be numbered in nondecreasing order; that is, | |
1193 | a larger-numbered class must never be contained completely | |
1194 | in a smaller-numbered class. | |
1195 | ||
1196 | For any two classes, it is very desirable that there be another | |
1197 | class that represents their union. */ | |
1198 | ||
4fb4e4b8 DE |
1199 | /* The SPARC has various kinds of registers: general, floating point, |
1200 | and condition codes [well, it has others as well, but none that we | |
1201 | care directly about]. | |
24b63396 JW |
1202 | |
1203 | For v9 we must distinguish between the upper and lower floating point | |
1204 | registers because the upper ones can't hold SFmode values. | |
1205 | HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) | |
1206 | satisfying a group need for a class will also satisfy a single need for | |
1207 | that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp | |
1208 | regs. | |
1209 | ||
1210 | It is important that one class contains all the general and all the standard | |
1211 | fp regs. Otherwise find_reg() won't properly allocate int regs for moves, | |
1212 | because reg_class_record() will bias the selection in favor of fp regs, | |
1213 | because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, | |
1214 | because FP_REGS > GENERAL_REGS. | |
1215 | ||
1216 | It is also important that one class contain all the general and all the | |
1217 | fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS | |
1218 | but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause | |
1219 | allocate_reload_reg() to bypass it causing an abort because the compiler | |
1220 | thinks it doesn't have a spill reg when in fact it does. | |
1221 | ||
7a6cf439 DE |
1222 | v9 also has 4 floating point condition code registers. Since we don't |
1223 | have a class that is the union of FPCC_REGS with either of the others, | |
1224 | it is important that it appear first. Otherwise the compiler will die | |
1225 | trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its | |
c4ce6853 DE |
1226 | constraints. |
1227 | ||
1228 | It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine | |
1229 | may try to use it to hold an SImode value. See register_operand. | |
956d6950 | 1230 | ??? Should %fcc[0123] be handled similarly? |
c4ce6853 | 1231 | */ |
7a6cf439 | 1232 | |
284d86e9 JC |
1233 | enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, |
1234 | EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, | |
7a6cf439 | 1235 | ALL_REGS, LIM_REG_CLASSES }; |
1bb87f28 JW |
1236 | |
1237 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1238 | ||
80ffc95e | 1239 | /* Give names of register classes as strings for dump file. */ |
1bb87f28 JW |
1240 | |
1241 | #define REG_CLASS_NAMES \ | |
284d86e9 JC |
1242 | { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ |
1243 | "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ | |
1244 | "ALL_REGS" } | |
1bb87f28 JW |
1245 | |
1246 | /* Define which registers fit in which classes. | |
1247 | This is an initializer for a vector of HARD_REG_SET | |
1248 | of length N_REG_CLASSES. */ | |
1249 | ||
563c12b0 RH |
1250 | #define REG_CLASS_CONTENTS \ |
1251 | {{0, 0, 0, 0}, /* NO_REGS */ \ | |
1252 | {0, 0, 0, 0xf}, /* FPCC_REGS */ \ | |
1253 | {0xffff, 0, 0, 0}, /* I64_REGS */ \ | |
1254 | {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ | |
1255 | {0, -1, 0, 0}, /* FP_REGS */ \ | |
1256 | {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ | |
1257 | {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ | |
1258 | {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ | |
1259 | {-1, -1, -1, 0x3f}} /* ALL_REGS */ | |
1bb87f28 JW |
1260 | |
1261 | /* The same information, inverted: | |
1262 | Return the class number of the smallest class containing | |
1263 | reg number REGNO. This could be a conditional expression | |
1264 | or could index an array. */ | |
1265 | ||
f540a7d3 | 1266 | extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
c4ce6853 DE |
1267 | |
1268 | #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] | |
1bb87f28 | 1269 | |
3aabf9a5 EC |
1270 | /* This is the order in which to allocate registers normally. |
1271 | ||
af54350e | 1272 | We put %f0-%f7 last among the float registers, so as to make it more |
6a4bb1fa | 1273 | likely that a pseudo-register which dies in the float return register |
af54350e DM |
1274 | area will get allocated to the float return register, thus saving a move |
1275 | instruction at the end of the function. | |
1276 | ||
1277 | Similarly for integer return value registers. | |
1278 | ||
1279 | We know in this case that we will not end up with a leaf function. | |
1280 | ||
fae778eb | 1281 | The register allocator is given the global and out registers first |
af54350e DM |
1282 | because these registers are call clobbered and thus less useful to |
1283 | global register allocation. | |
1284 | ||
1285 | Next we list the local and in registers. They are not call clobbered | |
1286 | and thus very useful for global register allocation. We list the input | |
1287 | registers before the locals so that it is more likely the incoming | |
1288 | arguments received in those registers can just stay there and not be | |
1289 | reloaded. */ | |
6afca97d | 1290 | |
7a6cf439 | 1291 | #define REG_ALLOC_ORDER \ |
af54350e DM |
1292 | { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ |
1293 | 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ | |
1294 | 15, /* %o7 */ \ | |
1295 | 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ | |
1296 | 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ | |
7a6cf439 | 1297 | 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ |
7a6cf439 DE |
1298 | 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ |
1299 | 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ | |
1300 | 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ | |
1301 | 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ | |
4fb4e4b8 DE |
1302 | 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ |
1303 | 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ | |
af54350e DM |
1304 | 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ |
1305 | 96, 97, 98, 99, /* %fcc0-3 */ \ | |
1306 | 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */ | |
1bb87f28 JW |
1307 | |
1308 | /* This is the order in which to allocate registers for | |
af54350e DM |
1309 | leaf functions. If all registers can fit in the global and |
1310 | output registers, then we have the possibility of having a leaf | |
1311 | function. | |
1312 | ||
1313 | The macro actually mentioned the input registers first, | |
1314 | because they get renumbered into the output registers once | |
1315 | we know really do have a leaf function. | |
1316 | ||
1317 | To be more precise, this register allocation order is used | |
1318 | when %o7 is found to not be clobbered right before register | |
1319 | allocation. Normally, the reason %o7 would be clobbered is | |
1320 | due to a call which could not be transformed into a sibling | |
1321 | call. | |
1322 | ||
1323 | As a consequence, it is possible to use the leaf register | |
1324 | allocation order and not end up with a leaf function. We will | |
1325 | not get suboptimal register allocation in that case because by | |
1326 | definition of being potentially leaf, there were no function | |
1327 | calls. Therefore, allocation order within the local register | |
1328 | window is not critical like it is when we do have function calls. */ | |
6afca97d | 1329 | |
7a6cf439 | 1330 | #define REG_LEAF_ALLOC_ORDER \ |
af54350e DM |
1331 | { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ |
1332 | 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ | |
1333 | 15, /* %o7 */ \ | |
1334 | 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ | |
1335 | 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ | |
1336 | 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ | |
1337 | 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ | |
1338 | 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ | |
1339 | 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ | |
1340 | 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ | |
1341 | 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ | |
1342 | 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ | |
1343 | 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ | |
1344 | 96, 97, 98, 99, /* %fcc0-3 */ \ | |
1345 | 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */ | |
3aabf9a5 | 1346 | |
1bb87f28 JW |
1347 | #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () |
1348 | ||
7d167afd JJ |
1349 | extern char sparc_leaf_regs[]; |
1350 | #define LEAF_REGISTERS sparc_leaf_regs | |
1bb87f28 | 1351 | |
d70e94ec | 1352 | extern char leaf_reg_remap[]; |
1bb87f28 | 1353 | #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) |
1bb87f28 | 1354 | |
1bb87f28 JW |
1355 | /* The class value for index registers, and the one for base regs. */ |
1356 | #define INDEX_REG_CLASS GENERAL_REGS | |
1357 | #define BASE_REG_CLASS GENERAL_REGS | |
1358 | ||
24b63396 | 1359 | /* Local macro to handle the two v9 classes of FP regs. */ |
24b63396 | 1360 | #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) |
24b63396 | 1361 | |
6afca97d DE |
1362 | /* Get reg_class from a letter such as appears in the machine description. |
1363 | In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the | |
bfd6bc60 | 1364 | .md file for v8 and v9. |
284d86e9 JC |
1365 | 'd' and 'b' are used for single and double precision VIS operations, |
1366 | if TARGET_VIS. | |
80ffc95e | 1367 | 'h' is used for V8+ 64 bit global and out registers. */ |
bfd6bc60 JC |
1368 | |
1369 | #define REG_CLASS_FROM_LETTER(C) \ | |
1370 | (TARGET_V9 \ | |
1371 | ? ((C) == 'f' ? FP_REGS \ | |
1372 | : (C) == 'e' ? EXTRA_FP_REGS \ | |
1373 | : (C) == 'c' ? FPCC_REGS \ | |
284d86e9 JC |
1374 | : ((C) == 'd' && TARGET_VIS) ? FP_REGS\ |
1375 | : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\ | |
1376 | : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\ | |
bfd6bc60 JC |
1377 | : NO_REGS) \ |
1378 | : ((C) == 'f' ? FP_REGS \ | |
1379 | : (C) == 'e' ? FP_REGS \ | |
1380 | : (C) == 'c' ? FPCC_REGS \ | |
6afca97d | 1381 | : NO_REGS)) |
1bb87f28 JW |
1382 | |
1383 | /* The letters I, J, K, L and M in a register constraint string | |
1384 | can be used to stand for particular ranges of immediate operands. | |
1385 | This macro defines what the ranges are. | |
1386 | C is the letter, and VALUE is a constant value. | |
1387 | Return 1 if VALUE is in the range specified by C. | |
1388 | ||
18c5947f | 1389 | `I' is used for the range of constants an insn can actually contain. |
1bb87f28 | 1390 | `J' is used for the range which is just zero (since that is R0). |
18c5947f DE |
1391 | `K' is used for constants which can be loaded with a single sethi insn. |
1392 | `L' is used for the range of constants supported by the movcc insns. | |
7d6040e8 | 1393 | `M' is used for the range of constants supported by the movrcc insns. |
ef0139b1 EB |
1394 | `N' is like K, but for constants wider than 32 bits. |
1395 | `O' is used for the range which is just 4096. */ | |
1bb87f28 | 1396 | |
1ccfa253 DE |
1397 | #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) |
1398 | #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) | |
1399 | #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) | |
18c5947f DE |
1400 | /* 10 and 11 bit immediates are only used for a few specific insns. |
1401 | SMALL_INT is used throughout the port so we continue to use it. */ | |
1402 | #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) | |
284d86e9 | 1403 | /* 13 bit immediate, considering only the low 32 bits */ |
9e0625a3 AO |
1404 | #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \ |
1405 | (INTVAL (X), SImode))) | |
1ccfa253 | 1406 | #define SPARC_SETHI_P(X) \ |
7d6040e8 AO |
1407 | (((unsigned HOST_WIDE_INT) (X) \ |
1408 | & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) | |
1409 | #define SPARC_SETHI32_P(X) \ | |
1410 | (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) | |
1bb87f28 JW |
1411 | |
1412 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
18c5947f | 1413 | ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \ |
1bb87f28 | 1414 | : (C) == 'J' ? (VALUE) == 0 \ |
7d6040e8 | 1415 | : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \ |
18c5947f DE |
1416 | : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \ |
1417 | : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \ | |
7d6040e8 | 1418 | : (C) == 'N' ? SPARC_SETHI_P (VALUE) \ |
ef0139b1 | 1419 | : (C) == 'O' ? (VALUE) == 4096 \ |
1bb87f28 JW |
1420 | : 0) |
1421 | ||
1422 | /* Similar, but for floating constants, and defining letters G and H. | |
1423 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
1424 | ||
1425 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
7ce86678 RH |
1426 | ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \ |
1427 | : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ | |
ef0139b1 | 1428 | : (C) == 'O' ? arith_double_4096_operand (VALUE, DImode) \ |
1bb87f28 JW |
1429 | : 0) |
1430 | ||
1431 | /* Given an rtx X being reloaded into a reg required to be | |
1432 | in class CLASS, return the class of reg to actually use. | |
1433 | In general this is just CLASS; but on some machines | |
1434 | in some cases it is preferable to use a more restrictive class. */ | |
3e7cd49f JW |
1435 | /* - We can't load constants into FP registers. |
1436 | - We can't load FP constants into integer registers when soft-float, | |
1437 | because there is no soft-float pattern with a r/F constraint. | |
1573b933 JJ |
1438 | - We can't load FP constants into integer registers for TFmode unless |
1439 | it is 0.0L, because there is no movtf pattern with a r/F constraint. | |
8947065c RH |
1440 | - Try and reload integer constants (symbolic or otherwise) back into |
1441 | registers directly, rather than having them dumped to memory. */ | |
1442 | ||
2b9a9aea JW |
1443 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
1444 | (CONSTANT_P (X) \ | |
8947065c | 1445 | ? ((FP_REG_CLASS_P (CLASS) \ |
7ae3e57c DM |
1446 | || (CLASS) == GENERAL_OR_FP_REGS \ |
1447 | || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \ | |
2b9a9aea | 1448 | || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ |
1573b933 JJ |
1449 | && ! TARGET_FPU) \ |
1450 | || (GET_MODE (X) == TFmode \ | |
1451 | && ! fp_zero_operand (X, TFmode))) \ | |
8947065c RH |
1452 | ? NO_REGS \ |
1453 | : (!FP_REG_CLASS_P (CLASS) \ | |
1454 | && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \ | |
1455 | ? GENERAL_REGS \ | |
1456 | : (CLASS)) \ | |
1457 | : (CLASS)) | |
1bb87f28 JW |
1458 | |
1459 | /* Return the register class of a scratch register needed to load IN into | |
1460 | a register of class CLASS in MODE. | |
1461 | ||
e0d80184 | 1462 | We need a temporary when loading/storing a HImode/QImode value |
ae51bd97 | 1463 | between memory and the FPU registers. This can happen when combine puts |
26aeede4 JJ |
1464 | a paradoxical subreg in a float/fix conversion insn. |
1465 | ||
1466 | We need a temporary when loading/storing a DFmode value between | |
1467 | unaligned memory and the upper FPU registers. */ | |
ae51bd97 JW |
1468 | |
1469 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
e0d80184 DM |
1470 | ((FP_REG_CLASS_P (CLASS) \ |
1471 | && ((MODE) == HImode || (MODE) == QImode) \ | |
24b63396 | 1472 | && (GET_CODE (IN) == MEM \ |
e0d80184 DM |
1473 | || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ |
1474 | && true_regnum (IN) == -1))) \ | |
1475 | ? GENERAL_REGS \ | |
26aeede4 JJ |
1476 | : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ |
1477 | && GET_CODE (IN) == MEM && TARGET_ARCH32 \ | |
1478 | && ! mem_min_alignment ((IN), 8)) \ | |
1479 | ? FP_REGS \ | |
1480 | : (((TARGET_CM_MEDANY \ | |
1481 | && symbolic_operand ((IN), (MODE))) \ | |
1482 | || (TARGET_CM_EMBMEDANY \ | |
1483 | && text_segment_operand ((IN), (MODE)))) \ | |
1484 | && !flag_pic) \ | |
1485 | ? GENERAL_REGS \ | |
1486 | : NO_REGS) | |
ae51bd97 JW |
1487 | |
1488 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
26aeede4 | 1489 | ((FP_REG_CLASS_P (CLASS) \ |
e0d80184 DM |
1490 | && ((MODE) == HImode || (MODE) == QImode) \ |
1491 | && (GET_CODE (IN) == MEM \ | |
1492 | || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ | |
1493 | && true_regnum (IN) == -1))) \ | |
26aeede4 JJ |
1494 | ? GENERAL_REGS \ |
1495 | : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ | |
1496 | && GET_CODE (IN) == MEM && TARGET_ARCH32 \ | |
1497 | && ! mem_min_alignment ((IN), 8)) \ | |
1498 | ? FP_REGS \ | |
1499 | : (((TARGET_CM_MEDANY \ | |
1500 | && symbolic_operand ((IN), (MODE))) \ | |
1501 | || (TARGET_CM_EMBMEDANY \ | |
1502 | && text_segment_operand ((IN), (MODE)))) \ | |
1503 | && !flag_pic) \ | |
1504 | ? GENERAL_REGS \ | |
1505 | : NO_REGS) | |
1bb87f28 | 1506 | |
3aabf9a5 | 1507 | /* On SPARC it is not possible to directly move data between |
b924cef0 | 1508 | GENERAL_REGS and FP_REGS. */ |
24b63396 JW |
1509 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1510 | (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) | |
b924cef0 | 1511 | |
55be783d JW |
1512 | /* Return the stack location to use for secondary memory needed reloads. |
1513 | We want to use the reserved location just below the frame pointer. | |
1514 | However, we must ensure that there is a frame, so use assign_stack_local | |
1515 | if the frame size is zero. */ | |
fe1f7f24 | 1516 | #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ |
55be783d | 1517 | (get_frame_size () == 0 \ |
fb3eb6f6 | 1518 | ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \ |
c5c76735 JL |
1519 | : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \ |
1520 | STARTING_FRAME_OFFSET))) | |
fe1f7f24 | 1521 | |
9ec36da5 | 1522 | /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9 |
7a6cf439 DE |
1523 | because the movsi and movsf patterns don't handle r/f moves. |
1524 | For v8 we copy the default definition. */ | |
1525 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
6f64bf5f | 1526 | (TARGET_ARCH64 \ |
fb3eb6f6 JW |
1527 | ? (GET_MODE_BITSIZE (MODE) < 32 \ |
1528 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
7a6cf439 | 1529 | : MODE) \ |
fb3eb6f6 JW |
1530 | : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ |
1531 | ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ | |
7a6cf439 DE |
1532 | : MODE)) |
1533 | ||
1bb87f28 JW |
1534 | /* Return the maximum number of consecutive registers |
1535 | needed to represent mode MODE in a register of class CLASS. */ | |
1536 | /* On SPARC, this is the size of MODE in words. */ | |
1537 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
24b63396 | 1538 | (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ |
7a6cf439 | 1539 | : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
1bb87f28 JW |
1540 | \f |
1541 | /* Stack layout; function entry, exit and calling. */ | |
1542 | ||
1543 | /* Define the number of register that can hold parameters. | |
4fb4e4b8 | 1544 | This macro is only used in other macro definitions below and in sparc.c. |
7a6cf439 DE |
1545 | MODE is the mode of the argument. |
1546 | !v9: All args are passed in %o0-%o5. | |
4fb4e4b8 DE |
1547 | v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values. |
1548 | See the description in sparc.c. */ | |
7a6cf439 | 1549 | #define NPARM_REGS(MODE) \ |
4fb4e4b8 DE |
1550 | (TARGET_ARCH64 \ |
1551 | ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \ | |
1552 | : 6) | |
1bb87f28 JW |
1553 | |
1554 | /* Define this if pushing a word on the stack | |
1555 | makes the stack pointer a smaller address. */ | |
1556 | #define STACK_GROWS_DOWNWARD | |
1557 | ||
1558 | /* Define this if the nominal address of the stack frame | |
1559 | is at the high-address end of the local variables; | |
1560 | that is, each additional local variable allocated | |
1561 | goes at a more negative offset in the frame. */ | |
1562 | #define FRAME_GROWS_DOWNWARD | |
1563 | ||
1564 | /* Offset within stack frame to start allocating local variables at. | |
1565 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1566 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1567 | of the first local allocated. */ | |
7238ce3a JW |
1568 | /* This allows space for one TFmode floating point value. */ |
1569 | #define STARTING_FRAME_OFFSET \ | |
563c12b0 | 1570 | (TARGET_ARCH64 ? -16 \ |
7a6cf439 | 1571 | : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))) |
1bb87f28 JW |
1572 | |
1573 | /* If we generate an insn to push BYTES bytes, | |
1574 | this says how many the stack pointer really advances by. | |
1575 | On SPARC, don't define this because there are no push insns. */ | |
1576 | /* #define PUSH_ROUNDING(BYTES) */ | |
1577 | ||
1578 | /* Offset of first parameter from the argument pointer register value. | |
7a6cf439 DE |
1579 | !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg |
1580 | even if this function isn't going to use it. | |
4fb4e4b8 | 1581 | v9: This is 128 for the ins and locals. */ |
7a6cf439 | 1582 | #define FIRST_PARM_OFFSET(FNDECL) \ |
563c12b0 | 1583 | (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) |
1bb87f28 | 1584 | |
2c849145 JM |
1585 | /* Offset from the argument pointer register value to the CFA. |
1586 | This is different from FIRST_PARM_OFFSET because the register window | |
1587 | comes between the CFA and the arguments. */ | |
c2c9f6c9 | 1588 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 |
71038426 | 1589 | |
1bb87f28 | 1590 | /* When a parameter is passed in a register, stack space is still |
82d6b402 RH |
1591 | allocated for it. |
1592 | !v9: All 6 possible integer registers have backing store allocated. | |
80ffc95e | 1593 | v9: Only space for the arguments passed is allocated. */ |
82d6b402 RH |
1594 | /* ??? Ideally, we'd use zero here (as the minimum), but zero has special |
1595 | meaning to the backend. Further, we need to be able to detect if a | |
1596 | varargs/unprototyped function is called, as they may want to spill more | |
1597 | registers than we've provided space. Ugly, ugly. So for now we retain | |
1598 | all 6 slots even for v9. */ | |
4fb4e4b8 | 1599 | #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) |
1bb87f28 | 1600 | |
563c12b0 RH |
1601 | /* Definitions for register elimination. */ |
1602 | /* ??? In TARGET_FLAT mode we needn't have a hard frame pointer. */ | |
3aabf9a5 | 1603 | |
563c12b0 | 1604 | #define ELIMINABLE_REGS \ |
e387e99b JJ |
1605 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
1606 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } | |
563c12b0 | 1607 | |
91d4b3fd RK |
1608 | /* The way this is structured, we can't eliminate SFP in favor of SP |
1609 | if the frame pointer is required: we want to use the SFP->HFP elimination | |
1610 | in that case. But the test in update_eliminables doesn't know we are | |
1611 | assuming below that we only do the former elimination. */ | |
1612 | #define CAN_ELIMINATE(FROM, TO) \ | |
1613 | ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED) | |
563c12b0 RH |
1614 | |
1615 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
e387e99b JJ |
1616 | do { \ |
1617 | (OFFSET) = 0; \ | |
1618 | if ((TO) == STACK_POINTER_REGNUM) \ | |
1619 | { \ | |
1620 | /* Note, we always pretend that this is a leaf function \ | |
1621 | because if it's not, there's no point in trying to \ | |
1622 | eliminate the frame pointer. If it is a leaf \ | |
1623 | function, we guessed right! */ \ | |
1624 | if (TARGET_FLAT) \ | |
1625 | (OFFSET) = \ | |
1626 | sparc_flat_compute_frame_size (get_frame_size ()); \ | |
1627 | else \ | |
1628 | (OFFSET) = compute_frame_size (get_frame_size (), 1); \ | |
1629 | } \ | |
1630 | (OFFSET) += SPARC_STACK_BIAS; \ | |
1631 | } while (0) | |
563c12b0 | 1632 | |
1bb87f28 | 1633 | /* Keep the stack pointer constant throughout the function. |
b4ac57ab | 1634 | This is both an optimization and a necessity: longjmp |
1bb87f28 JW |
1635 | doesn't behave itself when the stack pointer moves within |
1636 | the function! */ | |
f73ad30e | 1637 | #define ACCUMULATE_OUTGOING_ARGS 1 |
1bb87f28 JW |
1638 | |
1639 | /* Value is the number of bytes of arguments automatically | |
1640 | popped when returning from a subroutine call. | |
8b109b37 | 1641 | FUNDECL is the declaration node of the function (as a tree), |
1bb87f28 JW |
1642 | FUNTYPE is the data type of the function (as a tree), |
1643 | or for a library call it is an identifier node for the subroutine name. | |
1644 | SIZE is the number of bytes of arguments passed on the stack. */ | |
1645 | ||
8b109b37 | 1646 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
1bb87f28 | 1647 | |
5b485d2c JW |
1648 | /* Some subroutine macros specific to this machine. |
1649 | When !TARGET_FPU, put float return values in the general registers, | |
1650 | since we don't have any fp registers. */ | |
82d6b402 RH |
1651 | #define BASE_RETURN_VALUE_REG(MODE) \ |
1652 | (TARGET_ARCH64 \ | |
1653 | ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \ | |
7a6cf439 | 1654 | : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)) |
82d6b402 RH |
1655 | |
1656 | #define BASE_OUTGOING_VALUE_REG(MODE) \ | |
1657 | (TARGET_ARCH64 \ | |
1658 | ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \ | |
1659 | : TARGET_FLAT ? 8 : 24) \ | |
7a6cf439 | 1660 | : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \ |
bafb031b | 1661 | : (TARGET_FLAT ? 8 : 24))) |
82d6b402 RH |
1662 | |
1663 | #define BASE_PASSING_ARG_REG(MODE) \ | |
1664 | (TARGET_ARCH64 \ | |
1665 | ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \ | |
6f64bf5f | 1666 | : 8) |
82d6b402 | 1667 | |
80ffc95e | 1668 | /* ??? FIXME -- seems wrong for v9 structure passing... */ |
82d6b402 RH |
1669 | #define BASE_INCOMING_ARG_REG(MODE) \ |
1670 | (TARGET_ARCH64 \ | |
1671 | ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \ | |
1672 | : TARGET_FLAT ? 8 : 24) \ | |
bafb031b | 1673 | : (TARGET_FLAT ? 8 : 24)) |
1bb87f28 | 1674 | |
92ea370b TW |
1675 | /* Define this macro if the target machine has "register windows". This |
1676 | C expression returns the register number as seen by the called function | |
1677 | corresponding to register number OUT as seen by the calling function. | |
1678 | Return OUT if register number OUT is not an outbound register. */ | |
1679 | ||
1680 | #define INCOMING_REGNO(OUT) \ | |
bafb031b | 1681 | ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) |
92ea370b TW |
1682 | |
1683 | /* Define this macro if the target machine has "register windows". This | |
1684 | C expression returns the register number as seen by the calling function | |
1685 | corresponding to register number IN as seen by the called function. | |
1686 | Return IN if register number IN is not an inbound register. */ | |
1687 | ||
1688 | #define OUTGOING_REGNO(IN) \ | |
bafb031b | 1689 | ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) |
92ea370b | 1690 | |
2a3e384f RH |
1691 | /* Define this macro if the target machine has register windows. This |
1692 | C expression returns true if the register is call-saved but is in the | |
1693 | register window. */ | |
1694 | ||
1695 | #define LOCAL_REGNO(REGNO) \ | |
1696 | (TARGET_FLAT ? 0 : (REGNO) >= 16 && (REGNO) <= 31) | |
1697 | ||
1bb87f28 JW |
1698 | /* Define how to find the value returned by a function. |
1699 | VALTYPE is the data type of the value (as a tree). | |
1700 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1701 | otherwise, FUNC is 0. */ | |
1702 | ||
1703 | /* On SPARC the value is found in the first "output" register. */ | |
1704 | ||
82d6b402 RH |
1705 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
1706 | function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1) | |
1bb87f28 JW |
1707 | |
1708 | /* But the called function leaves it in the first "input" register. */ | |
1709 | ||
82d6b402 RH |
1710 | #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ |
1711 | function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0) | |
1bb87f28 JW |
1712 | |
1713 | /* Define how to find the value returned by a library function | |
1714 | assuming the value has mode MODE. */ | |
1715 | ||
82d6b402 RH |
1716 | #define LIBCALL_VALUE(MODE) \ |
1717 | function_value (NULL_TREE, (MODE), 1) | |
1bb87f28 JW |
1718 | |
1719 | /* 1 if N is a possible register number for a function value | |
1720 | as seen by the caller. | |
1721 | On SPARC, the first "output" reg is used for integer values, | |
1722 | and the first floating point register is used for floating point values. */ | |
1723 | ||
1724 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) | |
1725 | ||
34aaacec JW |
1726 | /* Define the size of space to allocate for the return value of an |
1727 | untyped_call. */ | |
1728 | ||
1729 | #define APPLY_RESULT_SIZE 16 | |
1730 | ||
1bb87f28 | 1731 | /* 1 if N is a possible register number for function argument passing. |
4fb4e4b8 | 1732 | On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ |
1bb87f28 | 1733 | |
7a6cf439 | 1734 | #define FUNCTION_ARG_REGNO_P(N) \ |
4fb4e4b8 DE |
1735 | (TARGET_ARCH64 \ |
1736 | ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \ | |
1737 | : ((N) >= 8 && (N) <= 13)) | |
1bb87f28 JW |
1738 | \f |
1739 | /* Define a data type for recording info about an argument list | |
1740 | during the scan of that argument list. This data type should | |
1741 | hold all necessary information about the function itself | |
1742 | and about the args processed so far, enough to enable macros | |
1743 | such as FUNCTION_ARG to determine where the next arg should go. | |
1744 | ||
7a6cf439 | 1745 | On SPARC (!v9), this is a single integer, which is a number of words |
1bb87f28 JW |
1746 | of arguments scanned so far (including the invisible argument, |
1747 | if any, which holds the structure-value-address). | |
7a6cf439 DE |
1748 | Thus 7 or more means all following args should go on the stack. |
1749 | ||
4fb4e4b8 | 1750 | For v9, we also need to know whether a prototype is present. */ |
7a6cf439 | 1751 | |
7a6cf439 | 1752 | struct sparc_args { |
4fb4e4b8 | 1753 | int words; /* number of words passed so far */ |
5e7a8ee0 KH |
1754 | int prototype_p; /* nonzero if a prototype is present */ |
1755 | int libcall_p; /* nonzero if a library call */ | |
7a6cf439 DE |
1756 | }; |
1757 | #define CUMULATIVE_ARGS struct sparc_args | |
1758 | ||
1bb87f28 JW |
1759 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1760 | for a call to a function whose data type is FNTYPE. | |
4fb4e4b8 | 1761 | For a library call, FNTYPE is 0. */ |
1bb87f28 | 1762 | |
563a317a JH |
1763 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \ |
1764 | init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); | |
1bb87f28 JW |
1765 | |
1766 | /* Update the data in CUM to advance over an argument | |
1767 | of mode MODE and data type TYPE. | |
4fb4e4b8 | 1768 | TYPE is null for libcalls where that information may not be available. */ |
7a6cf439 | 1769 | |
4fb4e4b8 DE |
1770 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
1771 | function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED)) | |
1bb87f28 | 1772 | |
7b0c7e62 JJ |
1773 | /* Nonzero if we do not know how to pass TYPE solely in registers. */ |
1774 | ||
1775 | #define MUST_PASS_IN_STACK(MODE,TYPE) \ | |
1776 | ((TYPE) != 0 \ | |
1777 | && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ | |
1778 | || TREE_ADDRESSABLE (TYPE))) | |
1779 | ||
1bb87f28 JW |
1780 | /* Determine where to put an argument to a function. |
1781 | Value is zero to push the argument on the stack, | |
1782 | or a hard register in which to store the argument. | |
1783 | ||
1784 | MODE is the argument's machine mode. | |
1785 | TYPE is the data type of the argument (as a tree). | |
1786 | This is null for libcalls where that information may | |
1787 | not be available. | |
1788 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1789 | the preceding args and about the function being called. | |
1790 | NAMED is nonzero if this argument is a named parameter | |
1791 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1792 | ||
4fb4e4b8 DE |
1793 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
1794 | function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0) | |
1bb87f28 JW |
1795 | |
1796 | /* Define where a function finds its arguments. | |
1797 | This is different from FUNCTION_ARG because of register windows. */ | |
1798 | ||
4fb4e4b8 DE |
1799 | #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ |
1800 | function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1) | |
1bb87f28 JW |
1801 | |
1802 | /* For an arg passed partly in registers and partly in memory, | |
1803 | this is the number of registers used. | |
4fb4e4b8 DE |
1804 | For args passed entirely in registers or entirely in memory, zero. */ |
1805 | ||
4fb4e4b8 DE |
1806 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
1807 | function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED)) | |
1808 | ||
1809 | /* A C expression that indicates when an argument must be passed by reference. | |
1810 | If nonzero for an argument, a copy of that argument is made in memory and a | |
1811 | pointer to the argument is passed instead of the argument itself. | |
1812 | The pointer is passed in whatever way is appropriate for passing a pointer | |
1813 | to that type. */ | |
1814 | ||
4fb4e4b8 DE |
1815 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ |
1816 | function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED)) | |
1817 | ||
1818 | /* If defined, a C expression which determines whether, and in which direction, | |
1819 | to pad out an argument with extra space. The value should be of type | |
1820 | `enum direction': either `upward' to pad above the argument, | |
1821 | `downward' to pad below, or `none' to inhibit padding. */ | |
284d86e9 | 1822 | |
4fb4e4b8 DE |
1823 | #define FUNCTION_ARG_PADDING(MODE, TYPE) \ |
1824 | function_arg_padding ((MODE), (TYPE)) | |
1825 | ||
1826 | /* If defined, a C expression that gives the alignment boundary, in bits, | |
1827 | of an argument with the specified mode and type. If it is not defined, | |
1828 | PARM_BOUNDARY is used for all arguments. | |
1829 | For sparc64, objects requiring 16 byte alignment are passed that way. */ | |
1830 | ||
1831 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
1832 | ((TARGET_ARCH64 \ | |
1833 | && (GET_MODE_ALIGNMENT (MODE) == 128 \ | |
1834 | || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \ | |
1835 | ? 128 : PARM_BOUNDARY) | |
7a6cf439 | 1836 | \f |
1bb87f28 JW |
1837 | /* Define the information needed to generate branch and scc insns. This is |
1838 | stored from the compare operation. Note that we can't use "rtx" here | |
1839 | since it hasn't been defined! */ | |
1840 | ||
e2500fed GK |
1841 | extern GTY(()) rtx sparc_compare_op0; |
1842 | extern GTY(()) rtx sparc_compare_op1; | |
1bb87f28 | 1843 | |
1bb87f28 | 1844 | \f |
4b69d2a3 RS |
1845 | /* Generate the special assembly code needed to tell the assembler whatever |
1846 | it might need to know about the return value of a function. | |
1847 | ||
56149abc | 1848 | For SPARC assemblers, we need to output a .proc pseudo-op which conveys |
4b69d2a3 RS |
1849 | information to the assembler relating to peephole optimization (done in |
1850 | the assembler). */ | |
1851 | ||
1852 | #define ASM_DECLARE_RESULT(FILE, RESULT) \ | |
4f70758f | 1853 | fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) |
4b69d2a3 | 1854 | |
1cb36a98 | 1855 | /* Output the special assembly code needed to tell the assembler some |
3aabf9a5 | 1856 | register is used as global register variable. |
730f0207 JJ |
1857 | |
1858 | SPARC 64bit psABI declares registers %g2 and %g3 as application | |
1859 | registers and %g6 and %g7 as OS registers. Any object using them | |
1860 | should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them | |
1861 | and how they are used (scratch or some global variable). | |
1862 | Linker will then refuse to link together objects which use those | |
1863 | registers incompatibly. | |
1864 | ||
1865 | Unless the registers are used for scratch, two different global | |
1866 | registers cannot be declared to the same name, so in the unlikely | |
1867 | case of a global register variable occupying more than one register | |
1868 | we prefix the second and following registers with .gnu.part1. etc. */ | |
1869 | ||
1870 | extern char sparc_hard_reg_printed[8]; | |
1cb36a98 RH |
1871 | |
1872 | #ifdef HAVE_AS_REGISTER_PSEUDO_OP | |
1873 | #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ | |
1874 | do { \ | |
1875 | if (TARGET_ARCH64) \ | |
1876 | { \ | |
730f0207 JJ |
1877 | int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \ |
1878 | int reg; \ | |
1879 | for (reg = (REGNO); reg < 8 && reg < end; reg++) \ | |
1880 | if ((reg & ~1) == 2 || (reg & ~1) == 6) \ | |
1cb36a98 | 1881 | { \ |
730f0207 JJ |
1882 | if (reg == (REGNO)) \ |
1883 | fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ | |
1cb36a98 RH |
1884 | else \ |
1885 | fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ | |
730f0207 JJ |
1886 | reg, reg - (REGNO), (NAME)); \ |
1887 | sparc_hard_reg_printed[reg] = 1; \ | |
1cb36a98 RH |
1888 | } \ |
1889 | } \ | |
1890 | } while (0) | |
1891 | #endif | |
1892 | ||
c4ce6853 | 1893 | \f |
89a8b315 RH |
1894 | /* Emit rtl for profiling. */ |
1895 | #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) | |
6f334f44 | 1896 | |
89a8b315 RH |
1897 | /* All the work done in PROFILE_HOOK, but still required. */ |
1898 | #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) | |
1bb87f28 | 1899 | |
2be15d0f | 1900 | /* Set the name of the mcount function for the system. */ |
2be15d0f | 1901 | #define MCOUNT_FUNCTION "*mcount" |
c4ce6853 | 1902 | \f |
1bb87f28 JW |
1903 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1904 | the stack pointer does not matter. The value is tested only in | |
1905 | functions that have frame pointers. | |
1906 | No definition is equivalent to always zero. */ | |
1907 | ||
1bb87f28 JW |
1908 | #define EXIT_IGNORE_STACK \ |
1909 | (get_frame_size () != 0 \ | |
1910 | || current_function_calls_alloca || current_function_outgoing_args_size) | |
1911 | ||
bafb031b DE |
1912 | #define DELAY_SLOTS_FOR_EPILOGUE \ |
1913 | (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1) | |
1914 | #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \ | |
1915 | (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \ | |
5b485d2c | 1916 | : eligible_for_epilogue_delay (trial, slots_filled)) |
deeeee8c MS |
1917 | |
1918 | /* Define registers used by the epilogue and return instruction. */ | |
1919 | #define EPILOGUE_USES(REGNO) \ | |
1920 | (!TARGET_FLAT && REGNO == 31) | |
6a4bb1fa | 1921 | \f |
1bb87f28 JW |
1922 | /* Length in units of the trampoline for entering a nested function. */ |
1923 | ||
c6b0465b JC |
1924 | #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) |
1925 | ||
1926 | #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */ | |
1bb87f28 JW |
1927 | |
1928 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1929 | FNADDR is an RTX for the address of the function's pure code. | |
7a6cf439 | 1930 | CXT is an RTX for the static chain value for the function. */ |
1bb87f28 | 1931 | |
7a6cf439 | 1932 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
6f64bf5f | 1933 | if (TARGET_ARCH64) \ |
7a6cf439 DE |
1934 | sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \ |
1935 | else \ | |
c6b0465b | 1936 | sparc_initialize_trampoline (TRAMP, FNADDR, CXT) |
6a4bb1fa | 1937 | \f |
648d2ffc | 1938 | /* Generate necessary RTL for __builtin_saveregs(). */ |
4fb4e4b8 | 1939 | |
648d2ffc | 1940 | #define EXPAND_BUILTIN_SAVEREGS() sparc_builtin_saveregs () |
953fe179 | 1941 | |
a8b2c8a1 | 1942 | /* Implement `va_start' for varargs and stdarg. */ |
e5faf155 ZW |
1943 | #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ |
1944 | sparc_va_start (valist, nextarg) | |
a8b2c8a1 RH |
1945 | |
1946 | /* Implement `va_arg'. */ | |
1947 | #define EXPAND_BUILTIN_VA_ARG(valist, type) \ | |
1948 | sparc_va_arg (valist, type) | |
1949 | ||
4fb4e4b8 DE |
1950 | /* Define this macro if the location where a function argument is passed |
1951 | depends on whether or not it is a named argument. | |
1952 | ||
1953 | This macro controls how the NAMED argument to FUNCTION_ARG | |
1954 | is set for varargs and stdarg functions. With this macro defined, | |
1955 | the NAMED argument is always true for named arguments, and false for | |
1956 | unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS | |
1957 | is defined, then all arguments are treated as named. Otherwise, all named | |
1958 | arguments except the last are treated as named. | |
1959 | For the v9 we want NAMED to mean what it says it means. */ | |
e5e809f4 JL |
1960 | |
1961 | #define STRICT_ARGUMENT_NAMING TARGET_V9 | |
4fb4e4b8 | 1962 | |
953fe179 JW |
1963 | /* Generate RTL to flush the register windows so as to make arbitrary frames |
1964 | available. */ | |
1965 | #define SETUP_FRAME_ADDRESSES() \ | |
1966 | emit_insn (gen_flush_register_windows ()) | |
1967 | ||
1968 | /* Given an rtx for the address of a frame, | |
1969 | return an rtx for the address of the word in the frame | |
7a6cf439 DE |
1970 | that holds the dynamic chain--the previous frame's address. |
1971 | ??? -mflat support? */ | |
8773135d JS |
1972 | #define DYNAMIC_CHAIN_ADDRESS(frame) \ |
1973 | plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) | |
953fe179 JW |
1974 | |
1975 | /* The return address isn't on the stack, it is in a register, so we can't | |
1976 | access it from the current frame pointer. We can access it from the | |
1977 | previous frame pointer though by reading a value from the register window | |
1978 | save area. */ | |
1979 | #define RETURN_ADDR_IN_PREVIOUS_FRAME | |
1980 | ||
5b6faa70 | 1981 | /* This is the offset of the return address to the true next instruction to be |
80ffc95e | 1982 | executed for the current function. */ |
6f64bf5f DE |
1983 | #define RETURN_ADDR_OFFSET \ |
1984 | (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct)) | |
5b6faa70 | 1985 | |
953fe179 JW |
1986 | /* The current return address is in %i7. The return address of anything |
1987 | farther back is in the register window save area at [%fp+60]. */ | |
1988 | /* ??? This ignores the fact that the actual return address is +8 for normal | |
1989 | returns, and +12 for structure returns. */ | |
1990 | #define RETURN_ADDR_RTX(count, frame) \ | |
1991 | ((count == -1) \ | |
284d86e9 JC |
1992 | ? gen_rtx_REG (Pmode, 31) \ |
1993 | : gen_rtx_MEM (Pmode, \ | |
c5c76735 | 1994 | memory_address (Pmode, plus_constant (frame, \ |
cd49f073 AM |
1995 | 15 * UNITS_PER_WORD \ |
1996 | + SPARC_STACK_BIAS)))) | |
9704efe6 | 1997 | |
d60bee3a DE |
1998 | /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's |
1999 | +12, but always using +8 is close enough for frame unwind purposes. | |
2000 | Actually, just using %o7 is close enough for unwinding, but %o7+8 | |
2001 | is something you can return to. */ | |
2002 | #define INCOMING_RETURN_ADDR_RTX \ | |
c5c76735 | 2003 | plus_constant (gen_rtx_REG (word_mode, 15), 8) |
8034da37 | 2004 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15) |
d60bee3a DE |
2005 | |
2006 | /* The offset from the incoming value of %sp to the top of the stack frame | |
2007 | for the current function. On sparc64, we have to account for the stack | |
2008 | bias if present. */ | |
2009 | #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS | |
2010 | ||
1150a841 RH |
2011 | /* Describe how we implement __builtin_eh_return. */ |
2012 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) | |
2013 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */ | |
2014 | #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */ | |
17e9e88c JJ |
2015 | |
2016 | /* Select a format to encode pointers in exception handling data. CODE | |
2017 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2018 | true if the symbol may be affected by dynamic relocations. | |
2019 | ||
2020 | If assembler and linker properly support .uaword %r_disp32(foo), | |
2021 | then use PC relative 32-bit relocations instead of absolute relocs | |
2022 | for shared libraries. On sparc64, use pc relative 32-bit relocs even | |
cf7b8b0d JJ |
2023 | for binaries, to save memory. |
2024 | ||
2025 | binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the | |
2026 | symbol %r_disp32() is against was not local, but .hidden. In that | |
2027 | case, we have to use DW_EH_PE_absptr for pic personality. */ | |
17e9e88c | 2028 | #ifdef HAVE_AS_SPARC_UA_PCREL |
cf7b8b0d | 2029 | #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN |
17e9e88c JJ |
2030 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ |
2031 | (flag_pic \ | |
2032 | ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ | |
2033 | : ((TARGET_ARCH64 && ! GLOBAL) \ | |
2034 | ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ | |
2035 | : DW_EH_PE_absptr)) | |
cf7b8b0d JJ |
2036 | #else |
2037 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ | |
2038 | (flag_pic \ | |
2039 | ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ | |
2040 | : ((TARGET_ARCH64 && ! GLOBAL) \ | |
2041 | ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ | |
2042 | : DW_EH_PE_absptr)) | |
2043 | #endif | |
17e9e88c JJ |
2044 | |
2045 | /* Emit a PC-relative relocation. */ | |
2046 | #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ | |
2047 | do { \ | |
2048 | fputs (integer_asm_op (SIZE, FALSE), FILE); \ | |
2049 | fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ | |
2050 | assemble_name (FILE, LABEL); \ | |
2051 | fputc (')', FILE); \ | |
2052 | } while (0) | |
2053 | #endif | |
1bb87f28 JW |
2054 | \f |
2055 | /* Addressing modes, and classification of registers for them. */ | |
2056 | ||
1bb87f28 JW |
2057 | /* Macros to check register numbers against specific register classes. */ |
2058 | ||
2059 | /* These assume that REGNO is a hard or pseudo reg number. | |
2060 | They give nonzero only if REGNO is a hard reg of the suitable class | |
2061 | or a pseudo reg currently allocated to a suitable hard reg. | |
2062 | Since they use reg_renumber, they are safe only once reg_renumber | |
2063 | has been allocated, which happens in local-alloc.c. */ | |
2064 | ||
2065 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
563c12b0 RH |
2066 | ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \ |
2067 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
2068 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) | |
2069 | ||
2070 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) | |
2071 | ||
1bb87f28 | 2072 | #define REGNO_OK_FOR_FP_P(REGNO) \ |
4f70758f KG |
2073 | (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ |
2074 | || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) | |
7a6cf439 DE |
2075 | #define REGNO_OK_FOR_CCFP_P(REGNO) \ |
2076 | (TARGET_V9 \ | |
4f70758f KG |
2077 | && (((unsigned) (REGNO) - 96 < (unsigned)4) \ |
2078 | || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) | |
1bb87f28 JW |
2079 | |
2080 | /* Now macros that check whether X is a register and also, | |
2081 | strictly, whether it is in a specified class. | |
2082 | ||
2083 | These macros are specific to the SPARC, and may be used only | |
2084 | in code for printing assembler insns and in conditions for | |
2085 | define_optimization. */ | |
2086 | ||
2087 | /* 1 if X is an fp register. */ | |
2088 | ||
2089 | #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) | |
284d86e9 JC |
2090 | |
2091 | /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */ | |
2092 | #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31)) | |
1bb87f28 JW |
2093 | \f |
2094 | /* Maximum number of registers that can appear in a valid memory address. */ | |
2095 | ||
2096 | #define MAX_REGS_PER_ADDRESS 2 | |
2097 | ||
7aca9b9c JW |
2098 | /* Recognize any constant value that is a valid address. |
2099 | When PIC, we do not accept an address that would require a scratch reg | |
2100 | to load into a register. */ | |
1bb87f28 | 2101 | |
5751a10b | 2102 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
7aca9b9c JW |
2103 | |
2104 | /* Define this, so that when PIC, reload won't try to reload invalid | |
2105 | addresses which require two reload registers. */ | |
2106 | ||
5751a10b | 2107 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
1bb87f28 JW |
2108 | |
2109 | /* Nonzero if the constant value X is a legitimate general operand. | |
f952a238 JJ |
2110 | Anything can be made to work except floating point constants. |
2111 | If TARGET_VIS, 0.0 can be made to work as well. */ | |
1bb87f28 | 2112 | |
5751a10b | 2113 | #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) |
1bb87f28 JW |
2114 | |
2115 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
2116 | and check its validity for a certain class. | |
2117 | We have two alternate definitions for each of them. | |
2118 | The usual definition accepts all pseudo regs; the other rejects | |
2119 | them unless they have been allocated suitable hard regs. | |
2120 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
2121 | ||
2122 | Most source files want to accept pseudo regs in the hope that | |
2123 | they will get allocated to the class that the insn wants them to be in. | |
2124 | Source files for reload pass need to be strict. | |
2125 | After reload, it makes no difference, since pseudo regs have | |
2126 | been eliminated by then. */ | |
2127 | ||
e0d80184 | 2128 | /* Optional extra constraints for this machine. |
1bb87f28 | 2129 | |
62190128 DM |
2130 | 'Q' handles floating point constants which can be moved into |
2131 | an integer register with a single sethi instruction. | |
2132 | ||
2133 | 'R' handles floating point constants which can be moved into | |
2134 | an integer register with a single mov instruction. | |
2135 | ||
2136 | 'S' handles floating point constants which can be moved into | |
2137 | an integer register using a high/lo_sum sequence. | |
2138 | ||
e0d80184 DM |
2139 | 'T' handles memory addresses where the alignment is known to |
2140 | be at least 8 bytes. | |
1bb87f28 | 2141 | |
e0d80184 | 2142 | `U' handles all pseudo registers or a hard even numbered |
7a31a340 DM |
2143 | integer register, needed for ldd/std instructions. |
2144 | ||
2145 | 'W' handles the memory operand when moving operands in/out | |
2146 | of 'e' constraint floating point registers. */ | |
1bb87f28 JW |
2147 | |
2148 | #ifndef REG_OK_STRICT | |
2149 | ||
2150 | /* Nonzero if X is a hard reg that can be used as an index | |
2151 | or if it is a pseudo reg. */ | |
7a6cf439 | 2152 | #define REG_OK_FOR_INDEX_P(X) \ |
563c12b0 RH |
2153 | (REGNO (X) < 32 \ |
2154 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
2155 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
2156 | ||
1bb87f28 JW |
2157 | /* Nonzero if X is a hard reg that can be used as a base reg |
2158 | or if it is a pseudo reg. */ | |
563c12b0 | 2159 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X) |
7a6cf439 | 2160 | |
7a31a340 | 2161 | /* 'T', 'U' are for aligned memory loads which aren't needed for arch64. |
f451b552 DM |
2162 | 'W' is like 'T' but is assumed true on arch64. |
2163 | ||
2164 | Remember to accept pseudo-registers for memory constraints if reload is | |
2165 | in progress. */ | |
2166 | ||
2167 | #define EXTRA_CONSTRAINT(OP, C) \ | |
2168 | sparc_extra_constraint_check(OP, C, 0) | |
62190128 | 2169 | |
1bb87f28 JW |
2170 | #else |
2171 | ||
2172 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
2173 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
2174 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
2175 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
2176 | ||
f451b552 DM |
2177 | #define EXTRA_CONSTRAINT(OP, C) \ |
2178 | sparc_extra_constraint_check(OP, C, 1) | |
62190128 | 2179 | |
1bb87f28 JW |
2180 | #endif |
2181 | \f | |
1cb36a98 RH |
2182 | /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ |
2183 | ||
2184 | #ifdef HAVE_AS_OFFSETABLE_LO10 | |
2185 | #define USE_AS_OFFSETABLE_LO10 1 | |
2186 | #else | |
2187 | #define USE_AS_OFFSETABLE_LO10 0 | |
2188 | #endif | |
2189 | \f | |
1bb87f28 JW |
2190 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
2191 | that is a valid memory address for an instruction. | |
2192 | The MODE argument is the machine mode for the MEM expression | |
2193 | that wants to use this address. | |
2194 | ||
2195 | On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT | |
2196 | ordinarily. This changes a bit when generating PIC. | |
2197 | ||
2198 | If you change this, execute "rm explow.o recog.o reload.o". */ | |
2199 | ||
731458a4 EB |
2200 | #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode) |
2201 | ||
bec2e359 JW |
2202 | #define RTX_OK_FOR_BASE_P(X) \ |
2203 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
2204 | || (GET_CODE (X) == SUBREG \ | |
2205 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
2206 | && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) | |
2207 | ||
2208 | #define RTX_OK_FOR_INDEX_P(X) \ | |
2209 | ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ | |
2210 | || (GET_CODE (X) == SUBREG \ | |
2211 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
2212 | && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) | |
2213 | ||
2214 | #define RTX_OK_FOR_OFFSET_P(X) \ | |
ce3e1311 | 2215 | (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8) |
3aabf9a5 | 2216 | |
1cb36a98 RH |
2217 | #define RTX_OK_FOR_OLO10_P(X) \ |
2218 | (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8) | |
bec2e359 | 2219 | |
5751a10b | 2220 | #ifdef REG_OK_STRICT |
1bb87f28 | 2221 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
5751a10b JJ |
2222 | { \ |
2223 | if (legitimate_address_p (MODE, X, 1)) \ | |
bec2e359 | 2224 | goto ADDR; \ |
5751a10b JJ |
2225 | } |
2226 | #else | |
2227 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
2228 | { \ | |
2229 | if (legitimate_address_p (MODE, X, 0)) \ | |
1bb87f28 JW |
2230 | goto ADDR; \ |
2231 | } | |
5751a10b | 2232 | #endif |
731458a4 EB |
2233 | |
2234 | /* Go to LABEL if ADDR (a legitimate address expression) | |
2235 | has an effect that depends on the machine mode it is used for. | |
2236 | ||
2237 | In PIC mode, | |
2238 | ||
2239 | (mem:HI [%l7+a]) | |
2240 | ||
2241 | is not equivalent to | |
2242 | ||
2243 | (mem:QI [%l7+a]) (mem:QI [%l7+a+1]) | |
2244 | ||
2245 | because [%l7+a+1] is interpreted as the address of (a+1). */ | |
2246 | ||
2247 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ | |
2248 | { \ | |
2249 | if (flag_pic == 1) \ | |
2250 | { \ | |
2251 | if (GET_CODE (ADDR) == PLUS) \ | |
2252 | { \ | |
2253 | rtx op0 = XEXP (ADDR, 0); \ | |
2254 | rtx op1 = XEXP (ADDR, 1); \ | |
2255 | if (op0 == pic_offset_table_rtx \ | |
2256 | && SYMBOLIC_CONST (op1)) \ | |
2257 | goto LABEL; \ | |
2258 | } \ | |
2259 | } \ | |
2260 | } | |
1bb87f28 JW |
2261 | \f |
2262 | /* Try machine-dependent ways of modifying an illegitimate address | |
2263 | to be legitimate. If we find one, return the new, valid address. | |
2264 | This macro is used in only one place: `memory_address' in explow.c. | |
2265 | ||
2266 | OLDX is the address as it was before break_out_memory_refs was called. | |
2267 | In some cases it is useful to look at this to decide what needs to be done. | |
2268 | ||
2269 | MODE and WIN are passed so that this macro can use | |
2270 | GO_IF_LEGITIMATE_ADDRESS. | |
2271 | ||
2272 | It is always safe for this macro to do nothing. It exists to recognize | |
2273 | opportunities to optimize the output. */ | |
2274 | ||
2275 | /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ | |
1bb87f28 | 2276 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ |
5751a10b JJ |
2277 | { \ |
2278 | (X) = legitimize_address (X, OLDX, MODE); \ | |
2279 | if (memory_address_p (MODE, X)) \ | |
2280 | goto WIN; \ | |
2281 | } | |
1bb87f28 | 2282 | |
8947065c RH |
2283 | /* Try a machine-dependent way of reloading an illegitimate address |
2284 | operand. If we find one, push the reload and jump to WIN. This | |
2285 | macro is used in only one place: `find_reloads_address' in reload.c. | |
2286 | ||
56149abc | 2287 | For SPARC 32, we wish to handle addresses by splitting them into |
3aabf9a5 | 2288 | HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference. |
1256ed02 JL |
2289 | This cuts the number of extra insns by one. |
2290 | ||
2291 | Do nothing when generating PIC code and the address is a | |
2292 | symbolic operand or requires a scratch register. */ | |
2293 | ||
8947065c RH |
2294 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
2295 | do { \ | |
2296 | /* Decompose SImode constants into hi+lo_sum. We do have to \ | |
2297 | rerecognize what we produce, so be careful. */ \ | |
2298 | if (CONSTANT_P (X) \ | |
2f15e255 | 2299 | && (MODE != TFmode || TARGET_ARCH64) \ |
8947065c | 2300 | && GET_MODE (X) == SImode \ |
1256ed02 JL |
2301 | && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \ |
2302 | && ! (flag_pic \ | |
78eca9f2 | 2303 | && (symbolic_operand (X, Pmode) \ |
2f15e255 RH |
2304 | || pic_address_needs_scratch (X))) \ |
2305 | && sparc_cmodel <= CM_MEDLOW) \ | |
8947065c RH |
2306 | { \ |
2307 | X = gen_rtx_LO_SUM (GET_MODE (X), \ | |
2308 | gen_rtx_HIGH (GET_MODE (X), X), X); \ | |
df4ae160 | 2309 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ |
8947065c RH |
2310 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ |
2311 | OPNUM, TYPE); \ | |
2312 | goto WIN; \ | |
2313 | } \ | |
2314 | /* ??? 64-bit reloads. */ \ | |
2315 | } while (0) | |
1bb87f28 JW |
2316 | \f |
2317 | /* Specify the machine mode that this machine uses | |
2318 | for the index in the tablejump instruction. */ | |
67cb8900 JJ |
2319 | /* If we ever implement any of the full models (such as CM_FULLANY), |
2320 | this has to be DImode in that case */ | |
d1accaa3 | 2321 | #ifdef HAVE_GAS_SUBSECTION_ORDERING |
67cb8900 JJ |
2322 | #define CASE_VECTOR_MODE \ |
2323 | (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) | |
d1accaa3 JJ |
2324 | #else |
2325 | /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise | |
80ffc95e | 2326 | we have to sign extend which slows things down. */ |
d1accaa3 JJ |
2327 | #define CASE_VECTOR_MODE \ |
2328 | (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) | |
2329 | #endif | |
1bb87f28 | 2330 | |
18543a22 ILT |
2331 | /* Define as C expression which evaluates to nonzero if the tablejump |
2332 | instruction expects the table to contain offsets from the address of the | |
2333 | table. | |
80ffc95e | 2334 | Do not define this if the table should contain absolute addresses. */ |
18543a22 | 2335 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ |
1bb87f28 | 2336 | |
1bb87f28 JW |
2337 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
2338 | #define DEFAULT_SIGNED_CHAR 1 | |
2339 | ||
2340 | /* Max number of bytes we can move from memory to memory | |
2341 | in one reasonably fast instruction. */ | |
2eef2ef1 | 2342 | #define MOVE_MAX 8 |
1bb87f28 | 2343 | |
0fb5a69e | 2344 | #if 0 /* Sun 4 has matherr, so this is no good. */ |
24e2a2bf RS |
2345 | /* This is the value of the error code EDOM for this machine, |
2346 | used by the sqrt instruction. */ | |
2347 | #define TARGET_EDOM 33 | |
2348 | ||
2349 | /* This is how to refer to the variable errno. */ | |
2350 | #define GEN_ERRNO_RTX \ | |
284d86e9 | 2351 | gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno")) |
0fb5a69e | 2352 | #endif /* 0 */ |
24e2a2bf | 2353 | |
9a63901f RK |
2354 | /* Define if operations between registers always perform the operation |
2355 | on the full register even if a narrower mode is specified. */ | |
2356 | #define WORD_REGISTER_OPERATIONS | |
2357 | ||
2358 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
2359 | will either zero-extend or sign-extend. The value of this macro should | |
2360 | be the code that says which one of the two operations is implicitly | |
2361 | done, NIL if none. */ | |
2362 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
1bb87f28 JW |
2363 | |
2364 | /* Nonzero if access to memory by bytes is slow and undesirable. | |
2365 | For RISC chips, it means that access to memory by bytes is no | |
2366 | better than access by words when possible, so grab a whole word | |
2367 | and maybe make use of that. */ | |
2368 | #define SLOW_BYTE_ACCESS 1 | |
2369 | ||
1bb87f28 | 2370 | /* When a prototype says `char' or `short', really pass an `int'. */ |
cb560352 | 2371 | #define PROMOTE_PROTOTYPES (TARGET_ARCH32) |
1bb87f28 | 2372 | |
d969caf8 | 2373 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
80ffc95e | 2374 | few bits. */ |
d969caf8 | 2375 | #define SHIFT_COUNT_TRUNCATED 1 |
1bb87f28 JW |
2376 | |
2377 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
2378 | is done just by pretending it is already truncated. */ | |
2379 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2380 | ||
2381 | /* Specify the machine mode that pointers have. | |
2382 | After generation of rtl, the compiler makes no further distinction | |
2383 | between pointers and any other objects of this machine mode. */ | |
3276910d | 2384 | #define Pmode (TARGET_ARCH64 ? DImode : SImode) |
1bb87f28 | 2385 | |
b4ac57ab RS |
2386 | /* Generate calls to memcpy, memcmp and memset. */ |
2387 | #define TARGET_MEM_FUNCTIONS | |
2388 | ||
1bb87f28 | 2389 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
4d449554 | 2390 | return the mode to be used for the comparison. For floating-point, |
7913f3d0 RH |
2391 | CCFP[E]mode is used. CC_NOOVmode should be used when the first operand |
2392 | is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special | |
922bd191 | 2393 | processing is needed. */ |
e267e177 | 2394 | #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) |
1bb87f28 | 2395 | |
5e7a8ee0 | 2396 | /* Return nonzero if MODE implies a floating point inequality can be |
56149abc | 2397 | reversed. For SPARC this is always true because we have a full |
46238b7d JJ |
2398 | compliment of ordered and unordered comparisons, but until generic |
2399 | code knows how to reverse it correctly we keep the old definition. */ | |
2400 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) | |
b331b745 | 2401 | |
3276910d RK |
2402 | /* A function address in a call instruction for indexing purposes. */ |
2403 | #define FUNCTION_MODE Pmode | |
1bb87f28 JW |
2404 | |
2405 | /* Define this if addresses of constant functions | |
2406 | shouldn't be put through pseudo regs where they can be cse'd. | |
2407 | Desirable on machines where ordinary constants are expensive | |
2408 | but a CALL with constant address is cheap. */ | |
2409 | #define NO_FUNCTION_CSE | |
2410 | ||
2411 | /* alloca should avoid clobbering the old register save area. */ | |
2412 | #define SETJMP_VIA_SAVE_AREA | |
2413 | ||
2414 | /* Define subroutines to call to handle multiply and divide. | |
2415 | Use the subroutines that Sun's library provides. | |
2416 | The `*' prevents an underscore from being prepended by the compiler. */ | |
2417 | ||
2418 | #define DIVSI3_LIBCALL "*.div" | |
2419 | #define UDIVSI3_LIBCALL "*.udiv" | |
2420 | #define MODSI3_LIBCALL "*.rem" | |
2421 | #define UMODSI3_LIBCALL "*.urem" | |
2422 | /* .umul is a little faster than .mul. */ | |
2423 | #define MULSI3_LIBCALL "*.umul" | |
2424 | ||
8248e2bc | 2425 | /* Define library calls for quad FP operations. These are all part of the |
47ac041c JJ |
2426 | SPARC 32bit ABI. */ |
2427 | #define ADDTF3_LIBCALL "_Q_add" | |
2428 | #define SUBTF3_LIBCALL "_Q_sub" | |
2429 | #define NEGTF2_LIBCALL "_Q_neg" | |
2430 | #define MULTF3_LIBCALL "_Q_mul" | |
2431 | #define DIVTF3_LIBCALL "_Q_div" | |
2432 | #define FLOATSITF2_LIBCALL "_Q_itoq" | |
2433 | #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi" | |
2434 | #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou" | |
2435 | #define EXTENDSFTF2_LIBCALL "_Q_stoq" | |
2436 | #define TRUNCTFSF2_LIBCALL "_Q_qtos" | |
2437 | #define EXTENDDFTF2_LIBCALL "_Q_dtoq" | |
2438 | #define TRUNCTFDF2_LIBCALL "_Q_qtod" | |
2439 | #define EQTF2_LIBCALL "_Q_feq" | |
2440 | #define NETF2_LIBCALL "_Q_fne" | |
2441 | #define GTTF2_LIBCALL "_Q_fgt" | |
2442 | #define GETF2_LIBCALL "_Q_fge" | |
2443 | #define LTTF2_LIBCALL "_Q_flt" | |
2444 | #define LETF2_LIBCALL "_Q_fle" | |
8248e2bc | 2445 | |
4e7d5d27 DM |
2446 | /* Assume by default that the _Qp_* 64-bit libcalls are implemented such |
2447 | that the inputs are fully consumed before the output memory is clobbered. */ | |
2448 | ||
2449 | #define TARGET_BUGGY_QP_LIB 0 | |
2450 | ||
78e9b5df JW |
2451 | /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because |
2452 | with soft-float, the SFmode and DFmode sqrt instructions will be absent, | |
2453 | and the compiler will notice and try to use the TFmode sqrt instruction | |
2454 | for calls to the builtin function sqrt, but this fails. */ | |
27da6752 JW |
2455 | #define INIT_TARGET_OPTABS \ |
2456 | do { \ | |
47ac041c JJ |
2457 | if (TARGET_ARCH32) \ |
2458 | { \ | |
2459 | add_optab->handlers[(int) TFmode].libfunc \ | |
2460 | = init_one_libfunc (ADDTF3_LIBCALL); \ | |
2461 | sub_optab->handlers[(int) TFmode].libfunc \ | |
2462 | = init_one_libfunc (SUBTF3_LIBCALL); \ | |
2463 | neg_optab->handlers[(int) TFmode].libfunc \ | |
2464 | = init_one_libfunc (NEGTF2_LIBCALL); \ | |
2465 | smul_optab->handlers[(int) TFmode].libfunc \ | |
2466 | = init_one_libfunc (MULTF3_LIBCALL); \ | |
ef89d648 | 2467 | sdiv_optab->handlers[(int) TFmode].libfunc \ |
47ac041c JJ |
2468 | = init_one_libfunc (DIVTF3_LIBCALL); \ |
2469 | eqtf2_libfunc = init_one_libfunc (EQTF2_LIBCALL); \ | |
2470 | netf2_libfunc = init_one_libfunc (NETF2_LIBCALL); \ | |
2471 | gttf2_libfunc = init_one_libfunc (GTTF2_LIBCALL); \ | |
2472 | getf2_libfunc = init_one_libfunc (GETF2_LIBCALL); \ | |
2473 | lttf2_libfunc = init_one_libfunc (LTTF2_LIBCALL); \ | |
2474 | letf2_libfunc = init_one_libfunc (LETF2_LIBCALL); \ | |
2475 | trunctfsf2_libfunc = init_one_libfunc (TRUNCTFSF2_LIBCALL); \ | |
2476 | trunctfdf2_libfunc = init_one_libfunc (TRUNCTFDF2_LIBCALL); \ | |
2477 | extendsftf2_libfunc = init_one_libfunc (EXTENDSFTF2_LIBCALL); \ | |
2478 | extenddftf2_libfunc = init_one_libfunc (EXTENDDFTF2_LIBCALL); \ | |
2479 | floatsitf_libfunc = init_one_libfunc (FLOATSITF2_LIBCALL); \ | |
2480 | fixtfsi_libfunc = init_one_libfunc (FIX_TRUNCTFSI2_LIBCALL); \ | |
2481 | fixunstfsi_libfunc \ | |
2482 | = init_one_libfunc (FIXUNS_TRUNCTFSI2_LIBCALL); \ | |
2483 | if (TARGET_FPU) \ | |
2484 | sqrt_optab->handlers[(int) TFmode].libfunc \ | |
2485 | = init_one_libfunc ("_Q_sqrt"); \ | |
2486 | } \ | |
556a56ac DM |
2487 | if (TARGET_ARCH64) \ |
2488 | { \ | |
2489 | /* In the SPARC 64bit ABI, these libfuncs do not exist in the \ | |
2490 | library. Make sure the compiler does not emit calls to them \ | |
2491 | by accident. */ \ | |
2492 | sdiv_optab->handlers[(int) SImode].libfunc = NULL; \ | |
2493 | udiv_optab->handlers[(int) SImode].libfunc = NULL; \ | |
2494 | smod_optab->handlers[(int) SImode].libfunc = NULL; \ | |
2495 | umod_optab->handlers[(int) SImode].libfunc = NULL; \ | |
2496 | smul_optab->handlers[(int) SImode].libfunc = NULL; \ | |
2497 | } \ | |
47428190 | 2498 | INIT_SUBTARGET_OPTABS; \ |
78e9b5df JW |
2499 | } while (0) |
2500 | ||
2501 | /* This is meant to be redefined in the host dependent files */ | |
2502 | #define INIT_SUBTARGET_OPTABS | |
2503 | ||
c5c60e15 BS |
2504 | /* Nonzero if a floating point comparison library call for |
2505 | mode MODE that will return a boolean value. Zero if one | |
2506 | of the libgcc2 functions is used. */ | |
2507 | #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) | |
2508 | ||
1bb87f28 | 2509 | /* Compute extra cost of moving data between one register class |
bfd6bc60 | 2510 | and another. */ |
284d86e9 | 2511 | #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS) |
cf011243 | 2512 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
284d86e9 JC |
2513 | (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \ |
2514 | || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \ | |
bfd6bc60 | 2515 | || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \ |
fae15c93 VM |
2516 | ? ((sparc_cpu == PROCESSOR_ULTRASPARC \ |
2517 | || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2) | |
1bb87f28 | 2518 | |
2f82dbf8 DM |
2519 | /* Provide the cost of a branch. For pre-v9 processors we use |
2520 | a value of 3 to take into account the potential annulling of | |
2521 | the delay slot (which ends up being a bubble in the pipeline slot) | |
2522 | plus a cycle to take into consideration the instruction cache | |
2523 | effects. | |
2524 | ||
2525 | On v9 and later, which have branch prediction facilities, we set | |
2526 | it to the depth of the pipeline as that is the cost of a | |
84643cbf | 2527 | mispredicted branch. */ |
2f82dbf8 DM |
2528 | |
2529 | #define BRANCH_COST \ | |
2530 | ((sparc_cpu == PROCESSOR_V9 \ | |
2531 | || sparc_cpu == PROCESSOR_ULTRASPARC) \ | |
84643cbf DM |
2532 | ? 7 \ |
2533 | : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ | |
2534 | ? 9 : 3)) | |
2f82dbf8 | 2535 | |
1bbad4c6 | 2536 | #define PREFETCH_BLOCK \ |
84643cbf DM |
2537 | ((sparc_cpu == PROCESSOR_ULTRASPARC \ |
2538 | || sparc_cpu == PROCESSOR_ULTRASPARC3) \ | |
2539 | ? 64 : 32) | |
1bbad4c6 | 2540 | |
1bbad4c6 | 2541 | #define SIMULTANEOUS_PREFETCHES \ |
84643cbf DM |
2542 | ((sparc_cpu == PROCESSOR_ULTRASPARC) \ |
2543 | ? 2 \ | |
2544 | : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ | |
2545 | ? 8 : 3)) | |
1bb87f28 JW |
2546 | \f |
2547 | /* Control the assembler format that we output. */ | |
2548 | ||
1ccfa253 DE |
2549 | /* A C string constant describing how to begin a comment in the target |
2550 | assembler language. The compiler assumes that the comment will end at | |
2551 | the end of the line. */ | |
2552 | ||
2553 | #define ASM_COMMENT_START "!" | |
2554 | ||
1bb87f28 JW |
2555 | /* Output to assembler file text saying following lines |
2556 | may contain character constants, extra white space, comments, etc. */ | |
2557 | ||
2558 | #define ASM_APP_ON "" | |
2559 | ||
2560 | /* Output to assembler file text saying following lines | |
2561 | no longer contain unusual constructs. */ | |
2562 | ||
2563 | #define ASM_APP_OFF "" | |
2564 | ||
7a6cf439 DE |
2565 | /* ??? Try to make the style consistent here (_OP?). */ |
2566 | ||
7a6cf439 DE |
2567 | #define ASM_FLOAT ".single" |
2568 | #define ASM_DOUBLE ".double" | |
80ffc95e | 2569 | #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */ |
303d524a | 2570 | |
1bb87f28 JW |
2571 | /* How to refer to registers in assembler output. |
2572 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2573 | ||
7a6cf439 DE |
2574 | #define REGISTER_NAMES \ |
2575 | {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ | |
2576 | "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ | |
2577 | "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ | |
2578 | "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ | |
2579 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ | |
2580 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ | |
2581 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ | |
2582 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ | |
2583 | "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ | |
2584 | "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ | |
2585 | "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ | |
2586 | "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ | |
563c12b0 | 2587 | "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" } |
ea3fa5f7 | 2588 | |
c4ce6853 | 2589 | /* Define additional names for use in asm clobbers and asm declarations. */ |
ea3fa5f7 | 2590 | |
c4ce6853 DE |
2591 | #define ADDITIONAL_REGISTER_NAMES \ |
2592 | {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} | |
ea3fa5f7 | 2593 | |
5bcb3f13 JM |
2594 | /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length |
2595 | can run past this up to a continuation point. Once we used 1500, but | |
2596 | a single entry in C++ can run more than 500 bytes, due to the length of | |
2597 | mangled symbol names. dbxout.c should really be fixed to do | |
2598 | continuations when they are actually needed instead of trying to | |
2599 | guess... */ | |
2600 | #define DBX_CONTIN_LENGTH 1000 | |
1bb87f28 | 2601 | |
1bb87f28 JW |
2602 | /* This is how to output a command to make the user-level label named NAME |
2603 | defined for reference from other files. */ | |
2604 | ||
506a61b1 KG |
2605 | /* Globalizing directive for a label. */ |
2606 | #define GLOBAL_ASM_OP "\t.global " | |
1bb87f28 | 2607 | |
80ffc95e | 2608 | /* The prefix to add to user-visible assembler symbols. */ |
1bb87f28 | 2609 | |
4e0c8ad2 | 2610 | #define USER_LABEL_PREFIX "_" |
1bb87f28 | 2611 | |
1bb87f28 JW |
2612 | /* This is how to store into the string LABEL |
2613 | the symbol_ref name of an internal numbered label where | |
2614 | PREFIX is the class of label and NUM is the number within the class. | |
2615 | This is suitable for output with `assemble_name'. */ | |
2616 | ||
2617 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
4f70758f | 2618 | sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) |
1bb87f28 | 2619 | |
e0d80184 DM |
2620 | /* This is how we hook in and defer the case-vector until the end of |
2621 | the function. */ | |
e0d80184 DM |
2622 | #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ |
2623 | sparc_defer_case_vector ((LAB),(VEC), 0) | |
2624 | ||
2625 | #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ | |
2626 | sparc_defer_case_vector ((LAB),(VEC), 1) | |
2627 | ||
1bb87f28 JW |
2628 | /* This is how to output an element of a case-vector that is absolute. */ |
2629 | ||
2630 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
4b69d2a3 RS |
2631 | do { \ |
2632 | char label[30]; \ | |
2633 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
67cb8900 | 2634 | if (CASE_VECTOR_MODE == SImode) \ |
7a6cf439 | 2635 | fprintf (FILE, "\t.word\t"); \ |
7a6cf439 DE |
2636 | else \ |
2637 | fprintf (FILE, "\t.xword\t"); \ | |
4b69d2a3 | 2638 | assemble_name (FILE, label); \ |
e0d80184 | 2639 | fputc ('\n', FILE); \ |
4b69d2a3 | 2640 | } while (0) |
1bb87f28 JW |
2641 | |
2642 | /* This is how to output an element of a case-vector that is relative. | |
2643 | (SPARC uses such vectors only when generating PIC.) */ | |
2644 | ||
33f7f353 | 2645 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
4b69d2a3 RS |
2646 | do { \ |
2647 | char label[30]; \ | |
e0d80184 | 2648 | ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ |
67cb8900 | 2649 | if (CASE_VECTOR_MODE == SImode) \ |
7a6cf439 | 2650 | fprintf (FILE, "\t.word\t"); \ |
7a6cf439 DE |
2651 | else \ |
2652 | fprintf (FILE, "\t.xword\t"); \ | |
4b69d2a3 | 2653 | assemble_name (FILE, label); \ |
e0d80184 DM |
2654 | ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ |
2655 | fputc ('-', FILE); \ | |
2656 | assemble_name (FILE, label); \ | |
2657 | fputc ('\n', FILE); \ | |
4b69d2a3 | 2658 | } while (0) |
1bb87f28 | 2659 | |
d1accaa3 JJ |
2660 | /* This is what to output before and after case-vector (both |
2661 | relative and absolute). If .subsection -1 works, we put case-vectors | |
2662 | at the beginning of the current section. */ | |
2663 | ||
2664 | #ifdef HAVE_GAS_SUBSECTION_ORDERING | |
2665 | ||
2666 | #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ | |
2667 | fprintf(FILE, "\t.subsection\t-1\n") | |
2668 | ||
2669 | #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ | |
2670 | fprintf(FILE, "\t.previous\n") | |
2671 | ||
2672 | #endif | |
2673 | ||
1bb87f28 JW |
2674 | /* This is how to output an assembler line |
2675 | that says to advance the location counter | |
2676 | to a multiple of 2**LOG bytes. */ | |
2677 | ||
2678 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2679 | if ((LOG) != 0) \ | |
2680 | fprintf (FILE, "\t.align %d\n", (1<<(LOG))) | |
2681 | ||
8e16ab99 SF |
2682 | /* This is how to output an assembler line that says to advance |
2683 | the location counter to a multiple of 2**LOG bytes using the | |
2684 | "nop" instruction as padding. */ | |
2685 | #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \ | |
2686 | if ((LOG) != 0) \ | |
2687 | fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG))) | |
2688 | ||
1bb87f28 | 2689 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ |
58e15542 | 2690 | fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
1bb87f28 JW |
2691 | |
2692 | /* This says how to output an assembler line | |
2693 | to define a global common symbol. */ | |
2694 | ||
2695 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
b277ceaf | 2696 | ( fputs ("\t.common ", (FILE)), \ |
1bb87f28 | 2697 | assemble_name ((FILE), (NAME)), \ |
58e15542 | 2698 | fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) |
1bb87f28 | 2699 | |
b277ceaf JW |
2700 | /* This says how to output an assembler line to define a local common |
2701 | symbol. */ | |
1bb87f28 | 2702 | |
b277ceaf JW |
2703 | #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ |
2704 | ( fputs ("\t.reserve ", (FILE)), \ | |
2705 | assemble_name ((FILE), (NAME)), \ | |
58e15542 | 2706 | fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ |
b277ceaf | 2707 | (SIZE), ((ALIGNED) / BITS_PER_UNIT))) |
1bb87f28 | 2708 | |
101d9529 JM |
2709 | /* A C statement (sans semicolon) to output to the stdio stream |
2710 | FILE the assembler definition of uninitialized global DECL named | |
2711 | NAME whose size is SIZE bytes and alignment is ALIGN bytes. | |
2712 | Try to use asm_output_aligned_bss to implement this macro. */ | |
2713 | ||
2714 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
2715 | do { \ | |
101d9529 JM |
2716 | ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ |
2717 | } while (0) | |
2718 | ||
471b6f1b | 2719 | #define IDENT_ASM_OP "\t.ident\t" |
c14f2655 RS |
2720 | |
2721 | /* Output #ident as a .ident. */ | |
2722 | ||
2723 | #define ASM_OUTPUT_IDENT(FILE, NAME) \ | |
b9f7d63e | 2724 | fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME); |
c14f2655 | 2725 | |
5751a10b JJ |
2726 | /* Emit a dtp-relative reference to a TLS variable. */ |
2727 | ||
2728 | #ifdef HAVE_AS_TLS | |
2729 | #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \ | |
2730 | sparc_output_dwarf_dtprel (FILE, SIZE, X) | |
2731 | #endif | |
2732 | ||
1bb87f28 | 2733 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ |
5751a10b JJ |
2734 | ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' \ |
2735 | || (CHAR) == '(' || (CHAR) == '_' || (CHAR) == '&') | |
1bb87f28 JW |
2736 | |
2737 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
2738 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2739 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2740 | ||
2741 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2742 | ||
2743 | /* Print a memory address as an operand to reference that memory location. */ | |
2744 | ||
2745 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
2746 | { register rtx base, index = 0; \ | |
2747 | int offset = 0; \ | |
2748 | register rtx addr = ADDR; \ | |
2749 | if (GET_CODE (addr) == REG) \ | |
2750 | fputs (reg_names[REGNO (addr)], FILE); \ | |
2751 | else if (GET_CODE (addr) == PLUS) \ | |
2752 | { \ | |
2753 | if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ | |
2754 | offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ | |
2755 | else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ | |
2756 | offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ | |
2757 | else \ | |
2758 | base = XEXP (addr, 0), index = XEXP (addr, 1); \ | |
1cb36a98 RH |
2759 | if (GET_CODE (base) == LO_SUM) \ |
2760 | { \ | |
2761 | if (! USE_AS_OFFSETABLE_LO10 \ | |
2762 | || TARGET_ARCH32 \ | |
2763 | || TARGET_CM_MEDMID) \ | |
2764 | abort (); \ | |
2765 | output_operand (XEXP (base, 0), 0); \ | |
2766 | fputs ("+%lo(", FILE); \ | |
2767 | output_address (XEXP (base, 1)); \ | |
2768 | fprintf (FILE, ")+%d", offset); \ | |
2769 | } \ | |
2770 | else \ | |
2771 | { \ | |
2772 | fputs (reg_names[REGNO (base)], FILE); \ | |
2773 | if (index == 0) \ | |
2774 | fprintf (FILE, "%+d", offset); \ | |
2775 | else if (GET_CODE (index) == REG) \ | |
2776 | fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ | |
2777 | else if (GET_CODE (index) == SYMBOL_REF \ | |
2778 | || GET_CODE (index) == CONST) \ | |
2779 | fputc ('+', FILE), output_addr_const (FILE, index); \ | |
2780 | else abort (); \ | |
2781 | } \ | |
1bb87f28 JW |
2782 | } \ |
2783 | else if (GET_CODE (addr) == MINUS \ | |
2784 | && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ | |
2785 | { \ | |
2786 | output_addr_const (FILE, XEXP (addr, 0)); \ | |
2787 | fputs ("-(", FILE); \ | |
2788 | output_addr_const (FILE, XEXP (addr, 1)); \ | |
2789 | fputs ("-.)", FILE); \ | |
2790 | } \ | |
2791 | else if (GET_CODE (addr) == LO_SUM) \ | |
2792 | { \ | |
2793 | output_operand (XEXP (addr, 0), 0); \ | |
e0d80184 DM |
2794 | if (TARGET_CM_MEDMID) \ |
2795 | fputs ("+%l44(", FILE); \ | |
2796 | else \ | |
2797 | fputs ("+%lo(", FILE); \ | |
1bb87f28 JW |
2798 | output_address (XEXP (addr, 1)); \ |
2799 | fputc (')', FILE); \ | |
2800 | } \ | |
2801 | else if (flag_pic && GET_CODE (addr) == CONST \ | |
2802 | && GET_CODE (XEXP (addr, 0)) == MINUS \ | |
2803 | && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ | |
2804 | && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ | |
2805 | && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ | |
2806 | { \ | |
2807 | addr = XEXP (addr, 0); \ | |
2808 | output_addr_const (FILE, XEXP (addr, 0)); \ | |
2809 | /* Group the args of the second CONST in parenthesis. */ \ | |
2810 | fputs ("-(", FILE); \ | |
2811 | /* Skip past the second CONST--it does nothing for us. */\ | |
2812 | output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ | |
2813 | /* Close the parenthesis. */ \ | |
2814 | fputc (')', FILE); \ | |
2815 | } \ | |
2816 | else \ | |
2817 | { \ | |
2818 | output_addr_const (FILE, addr); \ | |
2819 | } \ | |
2820 | } | |
2821 | ||
5751a10b JJ |
2822 | #ifdef HAVE_AS_TLS |
2823 | #define TARGET_TLS 1 | |
2824 | #else | |
2825 | #define TARGET_TLS 0 | |
2826 | #endif | |
2827 | #define TARGET_SUN_TLS TARGET_TLS | |
2828 | #define TARGET_GNU_TLS 0 | |
2829 | ||
f7e0e539 DM |
2830 | /* Define the codes that are matched by predicates in sparc.c. */ |
2831 | ||
11301057 RH |
2832 | #define PREDICATE_CODES \ |
2833 | {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
84ea5bc1 | 2834 | {"const1_operand", {CONST_INT}}, \ |
11301057 | 2835 | {"fp_zero_operand", {CONST_DOUBLE}}, \ |
2a732575 | 2836 | {"fp_register_operand", {SUBREG, REG}}, \ |
11301057 RH |
2837 | {"intreg_operand", {SUBREG, REG}}, \ |
2838 | {"fcc_reg_operand", {REG}}, \ | |
0b82d204 | 2839 | {"fcc0_reg_operand", {REG}}, \ |
11301057 RH |
2840 | {"icc_or_fcc_reg_operand", {REG}}, \ |
2841 | {"restore_operand", {REG}}, \ | |
2842 | {"call_operand", {MEM}}, \ | |
2843 | {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \ | |
2844 | ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \ | |
6871dd65 | 2845 | {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ |
11301057 RH |
2846 | {"symbolic_memory_operand", {SUBREG, MEM}}, \ |
2847 | {"label_ref_operand", {LABEL_REF}}, \ | |
2848 | {"sp64_medium_pic_operand", {CONST}}, \ | |
2849 | {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \ | |
2850 | {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \ | |
2851 | {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \ | |
2852 | {"splittable_symbolic_memory_operand", {MEM}}, \ | |
2853 | {"splittable_immediate_memory_operand", {MEM}}, \ | |
2854 | {"eq_or_neq", {EQ, NE}}, \ | |
2855 | {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \ | |
2856 | {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \ | |
0b82d204 | 2857 | {"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \ |
11301057 RH |
2858 | {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \ |
2859 | {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \ | |
2860 | {"cc_arithop", {AND, IOR, XOR}}, \ | |
2861 | {"cc_arithopn", {AND, IOR}}, \ | |
2862 | {"arith_operand", {SUBREG, REG, CONST_INT}}, \ | |
2863 | {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \ | |
2864 | {"arith11_operand", {SUBREG, REG, CONST_INT}}, \ | |
2865 | {"arith10_operand", {SUBREG, REG, CONST_INT}}, \ | |
2866 | {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
2867 | {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
2868 | {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
2869 | {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
2870 | {"small_int", {CONST_INT}}, \ | |
2871 | {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \ | |
2872 | {"uns_small_int", {CONST_INT}}, \ | |
2873 | {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \ | |
2874 | {"clobbered_register", {REG}}, \ | |
2875 | {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \ | |
11301057 | 2876 | {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \ |
5751a10b JJ |
2877 | {"const64_high_operand", {CONST_INT, CONST_DOUBLE}}, \ |
2878 | {"tgd_symbolic_operand", {SYMBOL_REF}}, \ | |
2879 | {"tld_symbolic_operand", {SYMBOL_REF}}, \ | |
2880 | {"tie_symbolic_operand", {SYMBOL_REF}}, \ | |
2881 | {"tle_symbolic_operand", {SYMBOL_REF}}, | |
f7e0e539 | 2882 | |
27a36778 MS |
2883 | /* The number of Pmode words for the setjmp buffer. */ |
2884 | #define JMP_BUF_SIZE 12 | |
2885 | ||
59ba1a3a | 2886 | #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic) |