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1 | ;; Scheduling description for UltraSPARC-III. |
2 | ;; Copyright (C) 2002 Free Software Foundation, Inc. | |
3 | ;; | |
4 | ;; This file is part of GNU CC. | |
5 | ;; | |
6 | ;; GNU CC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 2, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GNU CC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GNU CC; see the file COPYING. If not, write to | |
18 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, | |
19 | ;; Boston, MA 02111-1307, USA. | |
20 | ||
21 | ;; UltraSPARC-III is a quad-issue processor. | |
22 | ;; | |
23 | ;; It is also a much simpler beast than Ultra-I/II, no silly | |
24 | ;; slotting rules and both integer units are fully symmetric. | |
25 | ;; It does still have single-issue instructions though. | |
26 | ||
27 | (define_automaton "ultrasparc3_0,ultrasparc3_1") | |
28 | ||
29 | (define_cpu_unit "us3_a0,us3_a1,us3_ms,us3_br,us3_fpm" "ultrasparc3_0") | |
30 | (define_cpu_unit "us3_slot0,us3_slot1,us3_slot2,us3_slot3,us3_fpa" "ultrasparc3_1") | |
31 | (define_cpu_unit "us3_load_writeback" "ultrasparc3_1") | |
32 | ||
33 | (define_reservation "us3_slotany" "(us3_slot0 | us3_slot1 | us3_slot2 | us3_slot3)") | |
34 | (define_reservation "us3_single_issue" "us3_slot0 + us3_slot1 + us3_slot2 + us3_slot3") | |
35 | (define_reservation "us3_ax" "(us3_a0 | us3_a1)") | |
36 | ||
37 | (define_insn_reservation "us3_integer" 1 | |
38 | (and (eq_attr "cpu" "ultrasparc3") | |
39 | (eq_attr "type" "ialu,shift,compare")) | |
40 | "us3_ax + us3_slotany") | |
41 | ||
42 | (define_insn_reservation "us3_cmove" 2 | |
43 | (and (eq_attr "cpu" "ultrasparc3") | |
44 | (eq_attr "type" "cmove")) | |
45 | "us3_ms + us3_br + us3_slotany, nothing") | |
46 | ||
47 | ;; ??? Not entirely accurate. | |
48 | ;; ??? It can run from 6 to 9 cycles. The first cycle the MS pipe | |
49 | ;; ??? is needed, and the instruction group is broken right after | |
50 | ;; ??? the imul. Then 'helper' instructions are generated to perform | |
51 | ;; ??? each further stage of the multiplication, each such 'helper' is | |
52 | ;; ??? single group. So, the reservation aspect is represented accurately | |
53 | ;; ??? here, but the variable cycles are not. | |
54 | ;; ??? Currently I have no idea how to determine the variability, but once | |
55 | ;; ??? known we can simply add a define_bypass or similar to model it. | |
56 | (define_insn_reservation "us3_imul" 6 | |
57 | (and (eq_attr "cpu" "ultrasparc3") | |
58 | (eq_attr "type" "imul")) | |
59 | "us3_ms + us3_slotany, us3_single_issue*5") | |
60 | ||
61 | (define_insn_reservation "us3_idiv" 71 | |
62 | (and (eq_attr "cpu" "ultrasparc3") | |
63 | (eq_attr "type" "idiv")) | |
64 | "us3_ms + us3_slotany, us3_single_issue*70") | |
65 | ||
66 | ;; UltraSPARC-III has a similar load delay as UltraSPARC-I/II except | |
67 | ;; that all loads except 32-bit/64-bit unsigned loads take the extra | |
68 | ;; delay for sign/zero extension. | |
69 | (define_insn_reservation "us3_2cycle_load" 2 | |
70 | (and (eq_attr "cpu" "ultrasparc3") | |
71 | (and (eq_attr "type" "load,fpload") | |
72 | (eq_attr "us3load_type" "2cycle"))) | |
73 | "us3_ms + us3_slotany, us3_load_writeback") | |
74 | ||
75 | (define_insn_reservation "us3_load_delayed" 3 | |
76 | (and (eq_attr "cpu" "ultrasparc3") | |
77 | (and (eq_attr "type" "load,sload") | |
78 | (eq_attr "us3load_type" "3cycle"))) | |
79 | "us3_ms + us3_slotany, nothing, us3_load_writeback") | |
80 | ||
81 | (define_insn_reservation "us3_store" 1 | |
82 | (and (eq_attr "cpu" "ultrasparc3") | |
83 | (eq_attr "type" "store,fpstore")) | |
84 | "us3_ms + us3_slotany") | |
85 | ||
86 | (define_insn_reservation "us3_branch" 1 | |
87 | (and (eq_attr "cpu" "ultrasparc3") | |
88 | (eq_attr "type" "branch")) | |
89 | "us3_br + us3_slotany") | |
90 | ||
91 | (define_insn_reservation "us3_call_jmpl" 1 | |
92 | (and (eq_attr "cpu" "ultrasparc3") | |
93 | (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch")) | |
94 | "us3_br + us3_ms + us3_slotany") | |
95 | ||
96 | (define_insn_reservation "us3_fmov" 3 | |
97 | (and (eq_attr "cpu" "ultrasparc3") | |
98 | (eq_attr "type" "fpmove")) | |
99 | "us3_fpa + us3_slotany, nothing*2") | |
100 | ||
101 | (define_insn_reservation "us3_fcmov" 3 | |
102 | (and (eq_attr "cpu" "ultrasparc3") | |
103 | (eq_attr "type" "fpcmove")) | |
104 | "us3_fpa + us3_br + us3_slotany, nothing*2") | |
105 | ||
106 | (define_insn_reservation "us3_fcrmov" 3 | |
107 | (and (eq_attr "cpu" "ultrasparc3") | |
108 | (eq_attr "type" "fpcrmove")) | |
109 | "us3_fpa + us3_ms + us3_slotany, nothing*2") | |
110 | ||
111 | (define_insn_reservation "us3_faddsub" 4 | |
112 | (and (eq_attr "cpu" "ultrasparc3") | |
113 | (eq_attr "type" "fp")) | |
114 | "us3_fpa + us3_slotany, nothing*3") | |
115 | ||
116 | (define_insn_reservation "us3_fpcmp" 5 | |
117 | (and (eq_attr "cpu" "ultrasparc3") | |
118 | (eq_attr "type" "fpcmp")) | |
119 | "us3_fpa + us3_slotany, nothing*4") | |
120 | ||
121 | (define_insn_reservation "us3_fmult" 4 | |
122 | (and (eq_attr "cpu" "ultrasparc3") | |
123 | (eq_attr "type" "fpmul")) | |
124 | "us3_fpm + us3_slotany, nothing*3") | |
125 | ||
126 | (define_insn_reservation "us3_fdivs" 17 | |
127 | (and (eq_attr "cpu" "ultrasparc3") | |
128 | (eq_attr "type" "fpdivs")) | |
129 | "(us3_fpm + us3_slotany), us3_fpm*14, nothing*2") | |
130 | ||
131 | (define_insn_reservation "us3_fsqrts" 20 | |
132 | (and (eq_attr "cpu" "ultrasparc3") | |
133 | (eq_attr "type" "fpsqrts")) | |
134 | "(us3_fpm + us3_slotany), us3_fpm*17, nothing*2") | |
135 | ||
136 | (define_insn_reservation "us3_fdivd" 20 | |
137 | (and (eq_attr "cpu" "ultrasparc3") | |
138 | (eq_attr "type" "fpdivd")) | |
139 | "(us3_fpm + us3_slotany), us3_fpm*17, nothing*2") | |
140 | ||
141 | (define_insn_reservation "us3_fsqrtd" 29 | |
142 | (and (eq_attr "cpu" "ultrasparc3") | |
143 | (eq_attr "type" "fpsqrtd")) | |
144 | "(us3_fpm + us3_slotany), us3_fpm*26, nothing*2") | |
145 | ||
146 | ;; Any store may multi issue with the insn creating the source | |
147 | ;; data as long as that creating insn is not an FPU div/sqrt. | |
148 | ;; We need a special guard function because this bypass does | |
149 | ;; not apply to the address inputs of the store. | |
150 | (define_bypass 0 "us3_integer,us3_faddsub,us3_fmov,us3_fcmov,us3_fmult" "us3_store" | |
151 | "store_data_bypass_p") | |
152 | ||
153 | ;; An integer branch may execute in the same cycle as the compare | |
154 | ;; creating the condition codes. | |
155 | (define_bypass 0 "us3_integer" "us3_branch") | |
156 | ||
157 | ;; If FMOVfcc is user of FPCMP, latency is only 1 cycle. | |
158 | (define_bypass 1 "us3_fpcmp" "us3_fcmov") |