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85d9c13c | 1 | ;; Predicate definitions for CELL SPU |
a5544970 | 2 | ;; Copyright (C) 2006-2019 Free Software Foundation, Inc. |
85d9c13c TS |
3 | ;; |
4 | ;; This file is free software; you can redistribute it and/or modify it under | |
5 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 6 | ;; Software Foundation; either version 3 of the License, or (at your option) |
85d9c13c TS |
7 | ;; any later version. |
8 | ||
9 | ;; This file is distributed in the hope that it will be useful, but WITHOUT | |
10 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | ;; for more details. | |
13 | ||
14 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
15 | ;; along with GCC; see the file COPYING3. If not see |
16 | ;; <http://www.gnu.org/licenses/>. | |
85d9c13c | 17 | |
39aeae85 SL |
18 | ;; Return 1 if operand is constant zero of its mode |
19 | (define_predicate "const_zero_operand" | |
20 | (and (match_code "const_int,const,const_double,const_vector") | |
21 | (match_test "op == CONST0_RTX (mode)"))) | |
22 | ||
23 | (define_predicate "const_one_operand" | |
24 | (and (match_code "const_int,const,const_double,const_vector") | |
25 | (match_test "op == CONST1_RTX (mode)"))) | |
26 | ||
85d9c13c TS |
27 | (define_predicate "spu_reg_operand" |
28 | (and (match_operand 0 "register_operand") | |
29 | (ior (not (match_code "subreg")) | |
30 | (match_test "valid_subreg (op)")))) | |
31 | ||
32 | (define_predicate "spu_nonimm_operand" | |
33 | (and (match_operand 0 "nonimmediate_operand") | |
34 | (ior (not (match_code "subreg")) | |
35 | (match_test "valid_subreg (op)")))) | |
36 | ||
37 | (define_predicate "spu_nonmem_operand" | |
38 | (and (match_operand 0 "nonmemory_operand") | |
39 | (ior (not (match_code "subreg")) | |
40 | (match_test "valid_subreg (op)")))) | |
41 | ||
09aad82b | 42 | (define_predicate "spu_mov_operand" |
eec9405e | 43 | (ior (match_operand 0 "memory_operand") |
09aad82b TS |
44 | (match_operand 0 "spu_nonmem_operand"))) |
45 | ||
eec9405e TS |
46 | (define_predicate "spu_dest_operand" |
47 | (ior (match_operand 0 "memory_operand") | |
48 | (match_operand 0 "spu_reg_operand"))) | |
49 | ||
85d9c13c TS |
50 | (define_predicate "call_operand" |
51 | (and (match_code "mem") | |
52 | (match_test "(!TARGET_LARGE_MEM && satisfies_constraint_S (op)) | |
53 | || (satisfies_constraint_R (op) | |
54 | && REGNO (XEXP (op, 0)) != FRAME_POINTER_REGNUM | |
55 | && REGNO (XEXP (op, 0)) != ARG_POINTER_REGNUM | |
56 | && (REGNO (XEXP (op, 0)) < FIRST_PSEUDO_REGISTER | |
57 | || REGNO (XEXP (op, 0)) > LAST_VIRTUAL_REGISTER))"))) | |
58 | ||
59 | (define_predicate "vec_imm_operand" | |
60 | (and (match_code "const_int,const_double,const_vector") | |
1a627b35 | 61 | (match_test "spu_legitimate_constant_p (mode, op)"))) |
85d9c13c TS |
62 | |
63 | (define_predicate "spu_arith_operand" | |
64 | (match_code "reg,subreg,const_int,const_vector") | |
65 | { | |
66 | if (spu_reg_operand (op, mode)) | |
67 | return 1; | |
68 | if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_VECTOR) | |
69 | return arith_immediate_p (op, mode, -0x200, 0x1ff); | |
70 | return 0; | |
71 | }) | |
72 | ||
73 | (define_predicate "spu_logical_operand" | |
74 | (match_code "reg,subreg,const_int,const_double,const_vector") | |
75 | { | |
76 | if (spu_reg_operand (op, mode)) | |
77 | return 1; | |
78 | if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE | |
79 | || GET_CODE (op) == CONST_VECTOR) | |
80 | return logical_immediate_p (op, mode); | |
81 | return 0; | |
82 | }) | |
83 | ||
84 | (define_predicate "spu_ior_operand" | |
85 | (match_code "reg,subreg,const_int,const_double,const_vector") | |
86 | { | |
87 | if (spu_reg_operand (op, mode)) | |
88 | return 1; | |
89 | if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE | |
90 | || GET_CODE (op) == CONST_VECTOR) | |
91 | return logical_immediate_p (op, mode) | |
92 | || iohl_immediate_p (op, mode); | |
93 | return 0; | |
94 | }) | |
95 | ||
73701e27 TS |
96 | (define_predicate "imm_K_operand" |
97 | (and (match_code "const_int") | |
98 | (match_test "arith_immediate_p (op, mode, -0x200, 0x1ff)"))) | |
85d9c13c TS |
99 | |
100 | ;; Return 1 if OP is a comparison operation that is valid for a branch insn. | |
101 | ;; We only check the opcode against the mode of the register value here. | |
102 | (define_predicate "branch_comparison_operator" | |
103 | (and (match_code "eq,ne") | |
104 | (ior (match_test "GET_MODE (XEXP (op, 0)) == HImode") | |
105 | (match_test "GET_MODE (XEXP (op, 0)) == SImode")))) | |
106 | ||
5345cf68 TS |
107 | (define_predicate "spu_inv_exp2_operand" |
108 | (and (match_code "const_double,const_vector") | |
109 | (and (match_operand 0 "immediate_operand") | |
110 | (match_test "exp2_immediate_p (op, mode, -126, 0)")))) | |
111 | ||
112 | (define_predicate "spu_exp2_operand" | |
113 | (and (match_code "const_double,const_vector") | |
114 | (and (match_operand 0 "immediate_operand") | |
115 | (match_test "exp2_immediate_p (op, mode, 0, 127)")))) | |
116 | ||
eec9405e TS |
117 | (define_predicate "shiftrt_operator" |
118 | (match_code "lshiftrt,ashiftrt")) | |
119 | ||
120 | (define_predicate "extend_operator" | |
121 | (match_code "sign_extend,zero_extend")) | |
122 |