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a5544970 | 1 | /* Copyright (C) 2006-2019 Free Software Foundation, Inc. |
85d9c13c TS |
2 | |
3 | This file is free software; you can redistribute it and/or modify it under | |
4 | the terms of the GNU General Public License as published by the Free | |
748086b7 | 5 | Software Foundation; either version 3 of the License, or (at your option) |
85d9c13c TS |
6 | any later version. |
7 | ||
8 | This file is distributed in the hope that it will be useful, but WITHOUT | |
9 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
11 | for more details. | |
12 | ||
748086b7 JJ |
13 | Under Section 7 of GPL version 3, you are granted additional |
14 | permissions described in the GCC Runtime Library Exception, version | |
15 | 3.1, as published by the Free Software Foundation. | |
85d9c13c | 16 | |
748086b7 JJ |
17 | You should have received a copy of the GNU General Public License and |
18 | a copy of the GCC Runtime Library Exception along with this program; | |
19 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
20 | <http://www.gnu.org/licenses/>. */ | |
85d9c13c TS |
21 | |
22 | #ifndef __SPU_MFCIO_H__ | |
23 | #define __SPU_MFCIO_H__ 1 | |
24 | ||
25 | #include <spu_intrinsics.h> | |
1763dfa7 | 26 | #ifdef __IN_LIBGCC2 |
cae85ca9 | 27 | typedef unsigned long long uint64_t; |
1763dfa7 | 28 | #else |
85d9c13c | 29 | #include <stdint.h> |
1763dfa7 | 30 | #endif |
85d9c13c | 31 | |
e3834d38 UW |
32 | #ifdef __cplusplus |
33 | extern "C" { | |
34 | #endif | |
35 | ||
85d9c13c TS |
36 | |
37 | /****************************************************************/ | |
38 | /* DMA list element structure*/ | |
39 | /****************************************************************/ | |
40 | ||
41 | #ifdef __GNUC__ | |
42 | __extension__ | |
43 | #endif | |
44 | typedef struct mfc_list_element { | |
45 | uint64_t notify : 1; /** Stall-and-notify bit */ | |
a991f101 BE |
46 | uint64_t reserved : 16; |
47 | uint64_t size : 15; /** Transfer size */ | |
85d9c13c TS |
48 | uint64_t eal : 32; /** Lower word of effective address */ |
49 | } mfc_list_element_t; | |
50 | ||
51 | /****************************************************************/ | |
52 | /* DMA max/min size definitions. */ | |
53 | /****************************************************************/ | |
54 | ||
55 | #define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */ | |
56 | #define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */ | |
57 | ||
58 | #define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT) | |
59 | #define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT) | |
60 | ||
61 | #define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1) | |
62 | #define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1) | |
63 | ||
e3834d38 UW |
64 | #define MFC_MIN_DMA_LIST_ELEMENTS 1 |
65 | #define MFC_MAX_DMA_LIST_ELEMENTS 2048 | |
66 | ||
67 | #define MFC_MIN_DMA_LIST_SIZE (MFC_MIN_DMA_LIST_ELEMENTS << 3) /* 8 bytes */ | |
68 | #define MFC_MAX_DMA_LIST_SIZE (MFC_MAX_DMA_LIST_ELEMENTS << 3) /* 16K bytes */ | |
85d9c13c TS |
69 | |
70 | /****************************************************************/ | |
e3834d38 | 71 | /* MFC DMA command modifiers to identify classes of operations. */ |
85d9c13c | 72 | /****************************************************************/ |
e3834d38 UW |
73 | |
74 | /* Note: These commands modifier may be used in conjunction with the base | |
75 | command types (i.e. MFC_PUT_CMD, MFC_GET_CMD, and MFC_SNDSIG_CMD) | |
76 | to construct the various command permutations. */ | |
85d9c13c TS |
77 | |
78 | #define MFC_BARRIER_ENABLE 0x0001 | |
79 | #define MFC_FENCE_ENABLE 0x0002 | |
e3834d38 | 80 | #define MFC_LIST_ENABLE 0x0004 |
85d9c13c TS |
81 | #define MFC_RESULT_ENABLE 0x0010 |
82 | ||
83 | /****************************************************************/ | |
84 | /* MFC DMA Put Commands */ | |
85 | /****************************************************************/ | |
86 | ||
87 | #define MFC_PUT_CMD 0x0020 | |
e3834d38 UW |
88 | #define MFC_PUTB_CMD (MFC_PUT_CMD | MFC_BARRIER_ENABLE) |
89 | #define MFC_PUTF_CMD (MFC_PUT_CMD | MFC_FENCE_ENABLE) | |
90 | #define MFC_PUTL_CMD (MFC_PUT_CMD | MFC_LIST_ENABLE) | |
91 | #define MFC_PUTLB_CMD (MFC_PUTL_CMD | MFC_BARRIER_ENABLE) | |
92 | #define MFC_PUTLF_CMD (MFC_PUTL_CMD | MFC_FENCE_ENABLE) | |
93 | ||
94 | #define MFC_PUTR_CMD (MFC_PUT_CMD | MFC_RESULT_ENABLE) | |
95 | #define MFC_PUTRB_CMD (MFC_PUTR_CMD | MFC_BARRIER_ENABLE) | |
96 | #define MFC_PUTRF_CMD (MFC_PUTR_CMD | MFC_FENCE_ENABLE) | |
97 | #define MFC_PUTRL_CMD (MFC_PUTR_CMD | MFC_LIST_ENABLE) | |
98 | #define MFC_PUTRLB_CMD (MFC_PUTRL_CMD | MFC_BARRIER_ENABLE) | |
99 | #define MFC_PUTRLF_CMD (MFC_PUTRL_CMD | MFC_FENCE_ENABLE) | |
85d9c13c TS |
100 | |
101 | /****************************************************************/ | |
102 | /* MFC DMA Get Commands */ | |
103 | /****************************************************************/ | |
104 | ||
105 | #define MFC_GET_CMD 0x0040 | |
e3834d38 UW |
106 | #define MFC_GETB_CMD (MFC_GET_CMD | MFC_BARRIER_ENABLE) |
107 | #define MFC_GETF_CMD (MFC_GET_CMD | MFC_FENCE_ENABLE) | |
108 | #define MFC_GETL_CMD (MFC_GET_CMD | MFC_LIST_ENABLE) | |
109 | #define MFC_GETLB_CMD (MFC_GETL_CMD | MFC_BARRIER_ENABLE) | |
110 | #define MFC_GETLF_CMD (MFC_GETL_CMD | MFC_FENCE_ENABLE) | |
85d9c13c TS |
111 | |
112 | /****************************************************************/ | |
113 | /* MFC Synchronization Commands */ | |
114 | /****************************************************************/ | |
115 | ||
116 | #define MFC_SNDSIG_CMD 0x00A0 | |
e3834d38 UW |
117 | #define MFC_SNDSIGB_CMD (MFC_SNDSIG_CMD | MFC_BARRIER_ENABLE) |
118 | #define MFC_SNDSIGF_CMD (MFC_SNDSIG_CMD | MFC_FENCE_ENABLE) | |
85d9c13c TS |
119 | #define MFC_BARRIER_CMD 0x00C0 |
120 | #define MFC_EIEIO_CMD 0x00C8 | |
121 | #define MFC_SYNC_CMD 0x00CC | |
122 | ||
123 | /****************************************************************/ | |
124 | /* MFC Atomic Commands */ | |
125 | /****************************************************************/ | |
126 | ||
e3834d38 UW |
127 | #define MFC_GETLLAR_CMD 0x00D0 |
128 | #define MFC_PUTLLC_CMD 0x00B4 | |
129 | #define MFC_PUTLLUC_CMD 0x00B0 | |
130 | #define MFC_PUTQLLUC_CMD 0x00B8 | |
131 | ||
132 | /****************************************************************/ | |
133 | /* MFC SL1 Storage Control Commands */ | |
134 | /****************************************************************/ | |
135 | ||
136 | #define MFC_SDCRT_CMD 0x0080 | |
137 | #define MFC_SDCRTST_CMD 0x0081 | |
138 | #define MFC_SDCRZ_CMD 0x0089 | |
139 | #define MFC_SDCRST_CMD 0x008D | |
140 | #define MFC_SDCRF_CMD 0x008F | |
85d9c13c TS |
141 | |
142 | /****************************************************************/ | |
143 | /* Channel Defines */ | |
144 | /****************************************************************/ | |
145 | ||
146 | /* Events Defines for channels | |
147 | * 0 (SPU_RdEventStat), | |
148 | * 1 (SPU_WrEventMask), and | |
149 | * 2 (SPU_WrEventAck). | |
150 | */ | |
151 | #define MFC_TAG_STATUS_UPDATE_EVENT 0x00000001 | |
152 | #define MFC_LIST_STALL_NOTIFY_EVENT 0x00000002 | |
153 | #define MFC_COMMAND_QUEUE_AVAILABLE_EVENT 0x00000008 | |
154 | #define MFC_IN_MBOX_AVAILABLE_EVENT 0x00000010 | |
155 | #define MFC_DECREMENTER_EVENT 0x00000020 | |
156 | #define MFC_OUT_INTR_MBOX_AVAILABLE_EVENT 0x00000040 | |
157 | #define MFC_OUT_MBOX_AVAILABLE_EVENT 0x00000080 | |
158 | #define MFC_SIGNAL_NOTIFY_2_EVENT 0x00000100 | |
159 | #define MFC_SIGNAL_NOTIFY_1_EVENT 0x00000200 | |
160 | #define MFC_LLR_LOST_EVENT 0x00000400 | |
161 | #define MFC_PRIV_ATTN_EVENT 0x00000800 | |
162 | #define MFC_MULTI_SRC_SYNC_EVENT 0x00001000 | |
163 | ||
164 | /* Tag Status Update defines for channel 23 (MFC_WrTagUpdate) */ | |
165 | #define MFC_TAG_UPDATE_IMMEDIATE 0x0 | |
166 | #define MFC_TAG_UPDATE_ANY 0x1 | |
167 | #define MFC_TAG_UPDATE_ALL 0x2 | |
168 | ||
169 | /* Atomic Command Status defines for channel 27 (MFC_RdAtomicStat) */ | |
170 | #define MFC_PUTLLC_STATUS 0x00000001 | |
171 | #define MFC_PUTLLUC_STATUS 0x00000002 | |
172 | #define MFC_GETLLAR_STATUS 0x00000004 | |
173 | ||
174 | ||
175 | /****************************************************************/ | |
176 | /* Definitions for constructing a 32-bit command word */ | |
177 | /* including the transfer and replacement class id and the */ | |
178 | /* command opcode. */ | |
179 | /****************************************************************/ | |
180 | #define MFC_CMD_WORD(_tid, _rid, _cmd) (((_tid)<<24)|((_rid)<<16)|(_cmd)) | |
181 | ||
182 | ||
183 | /* Addressing Utilities */ | |
184 | #define mfc_ea2h(ea) (unsigned int)((unsigned long long)(ea)>>32) | |
185 | #define mfc_ea2l(ea) (unsigned int)(ea) | |
186 | #define mfc_hl2ea(h,l) si_to_ullong(si_selb(si_from_uint(h),\ | |
187 | si_rotqbyi(si_from_uint(l), -4),\ | |
188 | si_fsmbi(0x0f0f))) | |
189 | #define mfc_ceil128(v) (((v) + 127) & ~127) | |
190 | ||
191 | /* MFC DMA */ | |
192 | #define mfc_put( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUT_CMD)) | |
193 | #define mfc_putf( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTF_CMD)) | |
194 | #define mfc_putb( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTB_CMD)) | |
195 | #define mfc_get( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GET_CMD)) | |
196 | #define mfc_getf( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETF_CMD)) | |
197 | #define mfc_getb( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETB_CMD)) | |
198 | ||
199 | /* MFC list DMA */ | |
200 | #define mfc_putl( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTL_CMD)) | |
201 | #define mfc_putlf( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTLF_CMD)) | |
202 | #define mfc_putlb( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTLB_CMD)) | |
203 | #define mfc_getl( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETL_CMD)) | |
204 | #define mfc_getlf( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETLF_CMD)) | |
205 | #define mfc_getlb( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETLB_CMD)) | |
206 | ||
207 | /* MFC Atomic Update DMA */ | |
208 | #define mfc_getllar( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_GETLLAR_CMD)) | |
209 | #define mfc_putllc( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_PUTLLC_CMD)) | |
210 | #define mfc_putlluc( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_PUTLLUC_CMD)) | |
211 | #define mfc_putqlluc(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128,tag,MFC_CMD_WORD(tid,rid,MFC_PUTQLLUC_CMD)) | |
212 | ||
213 | /* MFC Synchronization Commands */ | |
214 | #define mfc_sndsig( ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIG_CMD)) | |
215 | #define mfc_sndsigb(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIGB_CMD)) | |
216 | #define mfc_sndsigf(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIGF_CMD)) | |
217 | #define mfc_barrier(tag) spu_mfcdma32(0,0,0,tag,MFC_BARRIER_CMD) | |
218 | #define mfc_eieio(tag,tid,rid) spu_mfcdma32(0,0,0,tag,MFC_CMD_WORD(tid,rid,MFC_EIEIO_CMD)) | |
219 | #define mfc_sync(tag) spu_mfcdma32(0,0,0,tag,MFC_SYNC_CMD) | |
220 | ||
e3834d38 UW |
221 | /* MFC SL1 Storage Control Commands */ |
222 | #define mfc_sdcrt( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRT_CMD)) | |
223 | #define mfc_sdcrtst(ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRTST_CMD)) | |
224 | #define mfc_sdcrz( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRZ_CMD)) | |
225 | #define mfc_sdcrst( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRST_CMD)) | |
226 | #define mfc_sdcrf( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRF_CMD)) | |
227 | ||
85d9c13c TS |
228 | /* DMA Queue */ |
229 | #define mfc_stat_cmd_queue() spu_readchcnt(MFC_Cmd) | |
230 | ||
231 | /* MFC Tag-Status */ | |
232 | #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask) | |
233 | #define mfc_read_tag_mask() spu_readch(MFC_RdTagMask) | |
234 | ||
235 | #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts) | |
236 | #define mfc_write_tag_update_immediate() mfc_write_tag_update(MFC_TAG_UPDATE_IMMEDIATE) | |
237 | #define mfc_write_tag_update_any() mfc_write_tag_update(MFC_TAG_UPDATE_ANY) | |
238 | #define mfc_write_tag_update_all() mfc_write_tag_update(MFC_TAG_UPDATE_ALL) | |
239 | #define mfc_stat_tag_update() spu_readchcnt(MFC_WrTagUpdate) | |
240 | ||
241 | #define mfc_read_tag_status() spu_readch(MFC_RdTagStat) | |
242 | #define mfc_read_tag_status_immediate() (mfc_write_tag_update_immediate(), mfc_read_tag_status()) | |
243 | #define mfc_read_tag_status_any() (mfc_write_tag_update_any(), mfc_read_tag_status()) | |
244 | #define mfc_read_tag_status_all() (mfc_write_tag_update_all(), mfc_read_tag_status()) | |
245 | #define mfc_stat_tag_status() spu_readchcnt(MFC_RdTagStat) | |
246 | ||
247 | /* MFC List Stall-and-Notify Tag */ | |
248 | #define mfc_read_list_stall_status() spu_readch(MFC_RdListStallStat) | |
249 | #define mfc_stat_list_stall_status() spu_readchcnt(MFC_RdListStallStat) | |
250 | #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag) | |
251 | ||
252 | /* Atomic DMA */ | |
253 | #define mfc_read_atomic_status() spu_readch(MFC_RdAtomicStat) | |
254 | #define mfc_stat_atomic_status() spu_readchcnt(MFC_RdAtomicStat) | |
255 | ||
256 | /* MFC Multi-source Synchronization */ | |
257 | #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0) | |
258 | #define mfc_stat_multi_src_sync_request() spu_readchcnt(MFC_WrMSSyncReq) | |
259 | ||
260 | /* SPU Signal */ | |
261 | #define spu_read_signal1() spu_readch(SPU_RdSigNotify1) | |
262 | #define spu_stat_signal1() spu_readchcnt(SPU_RdSigNotify1) | |
263 | #define spu_read_signal2() spu_readch(SPU_RdSigNotify2) | |
264 | #define spu_stat_signal2() spu_readchcnt(SPU_RdSigNotify2) | |
265 | ||
266 | /* SPU/PPE Mailbox */ | |
267 | #define spu_read_in_mbox() spu_readch(SPU_RdInMbox) | |
268 | #define spu_stat_in_mbox() spu_readchcnt(SPU_RdInMbox) | |
269 | #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a) | |
270 | #define spu_stat_out_mbox() spu_readchcnt(SPU_WrOutMbox) | |
271 | #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a) | |
272 | #define spu_stat_out_intr_mbox() spu_readchcnt(SPU_WrOutIntrMbox) | |
273 | ||
274 | /* SPU Decrementer */ | |
275 | #define spu_read_decrementer() spu_readch(SPU_RdDec) | |
276 | #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt)) | |
277 | ||
278 | /* SPU Event */ | |
279 | #define spu_read_event_status() spu_readch(SPU_RdEventStat) | |
280 | #define spu_stat_event_status() spu_readchcnt(SPU_RdEventStat) | |
281 | #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask)) | |
282 | #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack)) | |
dc6ba965 | 283 | #define spu_read_event_mask() spu_readch(SPU_RdEventMask) |
85d9c13c TS |
284 | |
285 | /* SPU State Management */ | |
e3834d38 | 286 | #define spu_read_machine_status() spu_readch(SPU_RdMachStat) |
85d9c13c TS |
287 | #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0) |
288 | #define spu_read_srr0() spu_readch(SPU_RdSRR0) | |
289 | ||
b704f034 UW |
290 | /* Interrupt-Safe Critical Sections */ |
291 | ||
292 | static __inline__ unsigned int mfc_begin_critical_section (void) | |
293 | __attribute__ ((__always_inline__)); | |
294 | ||
295 | static __inline__ unsigned int | |
296 | mfc_begin_critical_section (void) | |
297 | { | |
298 | #ifdef SPU_MFCIO_INTERRUPT_SAFE | |
299 | unsigned int __status = spu_read_machine_status (); | |
300 | spu_idisable (); | |
301 | return __status; | |
302 | #else | |
303 | return 0; | |
304 | #endif | |
305 | } | |
306 | ||
307 | static __inline__ void mfc_end_critical_section (unsigned int) | |
308 | __attribute__ ((__always_inline__)); | |
309 | ||
310 | static __inline__ void | |
311 | mfc_end_critical_section (unsigned int __status __attribute__ ((__unused__))) | |
312 | { | |
313 | #ifdef SPU_MFCIO_INTERRUPT_SAFE | |
314 | if (__status & 1) | |
315 | spu_ienable (); | |
316 | #endif | |
317 | } | |
1763dfa7 UW |
318 | |
319 | /* MFC Tag Manager */ | |
320 | ||
321 | #define MFC_TAG_INVALID 0xFFFFFFFF | |
322 | #define MFC_TAG_VALID 0x00000000 | |
323 | ||
324 | #define mfc_tag_reserve() \ | |
325 | __mfc_tag_reserve() | |
326 | #define mfc_tag_release(tag) \ | |
327 | __mfc_tag_release((tag)) | |
328 | #define mfc_multi_tag_reserve(nr_tags) \ | |
329 | __mfc_multi_tag_reserve((nr_tags)) | |
330 | #define mfc_multi_tag_release(tag, nr_tags) \ | |
331 | __mfc_multi_tag_release((tag),(nr_tags)) | |
332 | ||
333 | extern unsigned int __mfc_tag_reserve (void); | |
334 | extern unsigned int __mfc_tag_release (unsigned int); | |
335 | extern unsigned int __mfc_multi_tag_reserve (unsigned int); | |
336 | extern unsigned int __mfc_multi_tag_release (unsigned int, unsigned int); | |
337 | ||
e3834d38 UW |
338 | #ifdef __cplusplus |
339 | } | |
340 | #endif | |
341 | ||
85d9c13c | 342 | #endif /* __SPU_MFCIO_H__ */ |