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c6243b4c | 1 | /* Xstormy16 target functions. |
a5544970 | 2 | Copyright (C) 1997-2019 Free Software Foundation, Inc. |
4b58290f GK |
3 | Contributed by Red Hat, Inc. |
4 | ||
5ab9749e | 5 | This file is part of GCC. |
4b58290f | 6 | |
5ab9749e NC |
7 | GCC is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
4b58290f | 11 | |
5ab9749e NC |
12 | GCC is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
4b58290f | 16 | |
5ab9749e NC |
17 | You should have received a copy of the GNU General Public License |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
4b58290f | 20 | |
8fcc61f8 RS |
21 | #define IN_TARGET_CODE 1 |
22 | ||
4b58290f GK |
23 | #include "config.h" |
24 | #include "system.h" | |
4977bab6 | 25 | #include "coretypes.h" |
c7131fb2 | 26 | #include "backend.h" |
e11c4407 AM |
27 | #include "target.h" |
28 | #include "rtl.h" | |
c7131fb2 | 29 | #include "tree.h" |
314e6352 ML |
30 | #include "stringpool.h" |
31 | #include "attribs.h" | |
c7131fb2 | 32 | #include "gimple.h" |
c7131fb2 | 33 | #include "df.h" |
4d0cdd0c | 34 | #include "memmodel.h" |
e11c4407 AM |
35 | #include "tm_p.h" |
36 | #include "stringpool.h" | |
37 | #include "optabs.h" | |
38 | #include "emit-rtl.h" | |
4b58290f | 39 | #include "recog.h" |
718f9c0f | 40 | #include "diagnostic-core.h" |
e11c4407 | 41 | #include "output.h" |
40e23961 | 42 | #include "fold-const.h" |
d8a2d370 DN |
43 | #include "stor-layout.h" |
44 | #include "varasm.h" | |
45 | #include "calls.h" | |
36566b39 | 46 | #include "explow.h" |
4b58290f | 47 | #include "expr.h" |
f1e639b1 | 48 | #include "langhooks.h" |
60393bbc | 49 | #include "cfgrtl.h" |
45b0be94 | 50 | #include "gimplify.h" |
6b1ce545 | 51 | #include "reload.h" |
9b2b7279 | 52 | #include "builtins.h" |
4b58290f | 53 | |
994c5d85 | 54 | /* This file should be included last. */ |
d58627a0 RS |
55 | #include "target-def.h" |
56 | ||
51c16b7e SB |
57 | static rtx emit_addhi3_postreload (rtx, rtx, rtx); |
58 | static void xstormy16_asm_out_constructor (rtx, int); | |
59 | static void xstormy16_asm_out_destructor (rtx, int); | |
60 | static void xstormy16_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, | |
61 | HOST_WIDE_INT, tree); | |
4b58290f | 62 | |
51c16b7e | 63 | static void xstormy16_init_builtins (void); |
ef4bddc2 | 64 | static rtx xstormy16_expand_builtin (tree, rtx, rtx, machine_mode, int); |
ef4bddc2 | 65 | static int xstormy16_address_cost (rtx, machine_mode, addr_space_t, bool); |
586de218 | 66 | static bool xstormy16_return_in_memory (const_tree, const_tree); |
3d4b192a | 67 | |
d6b5193b RS |
68 | static GTY(()) section *bss100_section; |
69 | ||
3c50106f RH |
70 | /* Compute a (partial) cost for rtx X. Return true if the complete |
71 | cost has been computed, and false if subexpressions should be | |
72 | scanned. In either case, *TOTAL contains the cost result. */ | |
73 | ||
74 | static bool | |
e548c9df AM |
75 | xstormy16_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, |
76 | int outer_code ATTRIBUTE_UNUSED, | |
68f932c4 RS |
77 | int opno ATTRIBUTE_UNUSED, int *total, |
78 | bool speed ATTRIBUTE_UNUSED) | |
3c50106f | 79 | { |
e548c9df AM |
80 | int code = GET_CODE (x); |
81 | ||
3c50106f RH |
82 | switch (code) |
83 | { | |
84 | case CONST_INT: | |
85 | if (INTVAL (x) < 16 && INTVAL (x) >= 0) | |
86 | *total = COSTS_N_INSNS (1) / 2; | |
87 | else if (INTVAL (x) < 256 && INTVAL (x) >= 0) | |
88 | *total = COSTS_N_INSNS (1); | |
89 | else | |
90 | *total = COSTS_N_INSNS (2); | |
91 | return true; | |
92 | ||
93 | case CONST_DOUBLE: | |
94 | case CONST: | |
95 | case SYMBOL_REF: | |
96 | case LABEL_REF: | |
5ab9749e | 97 | *total = COSTS_N_INSNS (2); |
3c50106f RH |
98 | return true; |
99 | ||
100 | case MULT: | |
101 | *total = COSTS_N_INSNS (35 + 6); | |
102 | return true; | |
103 | case DIV: | |
104 | *total = COSTS_N_INSNS (51 - 6); | |
105 | return true; | |
106 | ||
107 | default: | |
108 | return false; | |
109 | } | |
110 | } | |
111 | ||
dcefdf67 | 112 | static int |
ef4bddc2 | 113 | xstormy16_address_cost (rtx x, machine_mode mode ATTRIBUTE_UNUSED, |
b413068c OE |
114 | addr_space_t as ATTRIBUTE_UNUSED, |
115 | bool speed ATTRIBUTE_UNUSED) | |
dcefdf67 | 116 | { |
a21eaf5e | 117 | return (CONST_INT_P (x) ? 2 |
dcefdf67 RH |
118 | : GET_CODE (x) == PLUS ? 7 |
119 | : 5); | |
120 | } | |
3c50106f | 121 | |
6b1ce545 AS |
122 | /* Worker function for TARGET_MEMORY_MOVE_COST. */ |
123 | ||
124 | static int | |
ef4bddc2 | 125 | xstormy16_memory_move_cost (machine_mode mode, reg_class_t rclass, |
6b1ce545 AS |
126 | bool in) |
127 | { | |
128 | return (5 + memory_move_secondary_cost (mode, rclass, in)); | |
129 | } | |
130 | ||
4b58290f GK |
131 | /* Branches are handled as follows: |
132 | ||
133 | 1. HImode compare-and-branches. The machine supports these | |
134 | natively, so the appropriate pattern is emitted directly. | |
135 | ||
136 | 2. SImode EQ and NE. These are emitted as pairs of HImode | |
5ab9749e | 137 | compare-and-branches. |
4b58290f GK |
138 | |
139 | 3. SImode LT, GE, LTU and GEU. These are emitted as a sequence | |
140 | of a SImode subtract followed by a branch (not a compare-and-branch), | |
141 | like this: | |
142 | sub | |
143 | sbc | |
144 | blt | |
145 | ||
146 | 4. SImode GT, LE, GTU, LEU. These are emitted as a sequence like: | |
147 | sub | |
148 | sbc | |
149 | blt | |
150 | or | |
5ab9749e | 151 | bne. */ |
4b58290f GK |
152 | |
153 | /* Emit a branch of kind CODE to location LOC. */ | |
154 | ||
155 | void | |
f90b7a5a | 156 | xstormy16_emit_cbranch (enum rtx_code code, rtx op0, rtx op1, rtx loc) |
4b58290f | 157 | { |
4b58290f GK |
158 | rtx condition_rtx, loc_ref, branch, cy_clobber; |
159 | rtvec vec; | |
ef4bddc2 | 160 | machine_mode mode; |
5ab9749e | 161 | |
4b58290f | 162 | mode = GET_MODE (op0); |
4718bfd8 | 163 | gcc_assert (mode == HImode || mode == SImode); |
4b58290f GK |
164 | |
165 | if (mode == SImode | |
166 | && (code == GT || code == LE || code == GTU || code == LEU)) | |
167 | { | |
168 | int unsigned_p = (code == GTU || code == LEU); | |
169 | int gt_p = (code == GT || code == GTU); | |
cd4c46f3 | 170 | rtx lab = NULL_RTX; |
5ab9749e | 171 | |
4b58290f GK |
172 | if (gt_p) |
173 | lab = gen_label_rtx (); | |
f90b7a5a | 174 | xstormy16_emit_cbranch (unsigned_p ? LTU : LT, op0, op1, gt_p ? lab : loc); |
4b58290f GK |
175 | /* This should be generated as a comparison against the temporary |
176 | created by the previous insn, but reload can't handle that. */ | |
f90b7a5a | 177 | xstormy16_emit_cbranch (gt_p ? NE : EQ, op0, op1, loc); |
4b58290f GK |
178 | if (gt_p) |
179 | emit_label (lab); | |
180 | return; | |
181 | } | |
5ab9749e | 182 | else if (mode == SImode |
4b58290f GK |
183 | && (code == NE || code == EQ) |
184 | && op1 != const0_rtx) | |
185 | { | |
f90b7a5a | 186 | rtx op0_word, op1_word; |
cd4c46f3 | 187 | rtx lab = NULL_RTX; |
4b58290f GK |
188 | int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; |
189 | int i; | |
5ab9749e | 190 | |
4b58290f GK |
191 | if (code == EQ) |
192 | lab = gen_label_rtx (); | |
5ab9749e | 193 | |
4b58290f GK |
194 | for (i = 0; i < num_words - 1; i++) |
195 | { | |
f90b7a5a PB |
196 | op0_word = simplify_gen_subreg (word_mode, op0, mode, |
197 | i * UNITS_PER_WORD); | |
198 | op1_word = simplify_gen_subreg (word_mode, op1, mode, | |
199 | i * UNITS_PER_WORD); | |
200 | xstormy16_emit_cbranch (NE, op0_word, op1_word, code == EQ ? lab : loc); | |
4b58290f | 201 | } |
f90b7a5a PB |
202 | op0_word = simplify_gen_subreg (word_mode, op0, mode, |
203 | i * UNITS_PER_WORD); | |
204 | op1_word = simplify_gen_subreg (word_mode, op1, mode, | |
205 | i * UNITS_PER_WORD); | |
206 | xstormy16_emit_cbranch (code, op0_word, op1_word, loc); | |
4b58290f GK |
207 | |
208 | if (code == EQ) | |
209 | emit_label (lab); | |
210 | return; | |
211 | } | |
212 | ||
213 | /* We can't allow reload to try to generate any reload after a branch, | |
214 | so when some register must match we must make the temporary ourselves. */ | |
215 | if (mode != HImode) | |
216 | { | |
217 | rtx tmp; | |
218 | tmp = gen_reg_rtx (mode); | |
219 | emit_move_insn (tmp, op0); | |
220 | op0 = tmp; | |
221 | } | |
222 | ||
1c563bed | 223 | condition_rtx = gen_rtx_fmt_ee (code, mode, op0, op1); |
4b58290f | 224 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); |
f7df4a84 | 225 | branch = gen_rtx_SET (pc_rtx, |
4b58290f GK |
226 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, |
227 | loc_ref, pc_rtx)); | |
228 | ||
b72bbbcb | 229 | cy_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); |
4b58290f GK |
230 | |
231 | if (mode == HImode) | |
232 | vec = gen_rtvec (2, branch, cy_clobber); | |
233 | else if (code == NE || code == EQ) | |
234 | vec = gen_rtvec (2, branch, gen_rtx_CLOBBER (VOIDmode, op0)); | |
235 | else | |
236 | { | |
237 | rtx sub; | |
238 | #if 0 | |
f7df4a84 | 239 | sub = gen_rtx_SET (op0, gen_rtx_MINUS (SImode, op0, op1)); |
4b58290f GK |
240 | #else |
241 | sub = gen_rtx_CLOBBER (SImode, op0); | |
242 | #endif | |
243 | vec = gen_rtvec (3, branch, sub, cy_clobber); | |
244 | } | |
245 | ||
246 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec)); | |
247 | } | |
248 | ||
249 | /* Take a SImode conditional branch, one of GT/LE/GTU/LEU, and split | |
250 | the arithmetic operation. Most of the work is done by | |
c6243b4c | 251 | xstormy16_expand_arith. */ |
4b58290f GK |
252 | |
253 | void | |
ef4bddc2 | 254 | xstormy16_split_cbranch (machine_mode mode, rtx label, rtx comparison, |
d40ba0b6 | 255 | rtx dest) |
4b58290f GK |
256 | { |
257 | rtx op0 = XEXP (comparison, 0); | |
258 | rtx op1 = XEXP (comparison, 1); | |
b32d5189 | 259 | rtx_insn *seq, *last_insn; |
4b58290f | 260 | rtx compare; |
5ab9749e | 261 | |
4b58290f | 262 | start_sequence (); |
d40ba0b6 | 263 | xstormy16_expand_arith (mode, COMPARE, dest, op0, op1); |
2f937369 | 264 | seq = get_insns (); |
4b58290f | 265 | end_sequence (); |
2f937369 | 266 | |
4718bfd8 | 267 | gcc_assert (INSN_P (seq)); |
2f937369 DM |
268 | |
269 | last_insn = seq; | |
270 | while (NEXT_INSN (last_insn) != NULL_RTX) | |
271 | last_insn = NEXT_INSN (last_insn); | |
272 | ||
273 | compare = SET_SRC (XVECEXP (PATTERN (last_insn), 0, 0)); | |
4b58290f GK |
274 | PUT_CODE (XEXP (compare, 0), GET_CODE (comparison)); |
275 | XEXP (compare, 1) = gen_rtx_LABEL_REF (VOIDmode, label); | |
276 | emit_insn (seq); | |
277 | } | |
278 | ||
279 | ||
280 | /* Return the string to output a conditional branch to LABEL, which is | |
281 | the operand number of the label. | |
282 | ||
283 | OP is the conditional expression, or NULL for branch-always. | |
284 | ||
5e7a8ee0 | 285 | REVERSED is nonzero if we should reverse the sense of the comparison. |
4b58290f GK |
286 | |
287 | INSN is the insn. */ | |
288 | ||
289 | char * | |
84034c69 DM |
290 | xstormy16_output_cbranch_hi (rtx op, const char *label, int reversed, |
291 | rtx_insn *insn) | |
4b58290f GK |
292 | { |
293 | static char string[64]; | |
294 | int need_longbranch = (op != NULL_RTX | |
295 | ? get_attr_length (insn) == 8 | |
296 | : get_attr_length (insn) == 4); | |
297 | int really_reversed = reversed ^ need_longbranch; | |
298 | const char *ccode; | |
0a2aaacc | 299 | const char *templ; |
4b58290f GK |
300 | const char *operands; |
301 | enum rtx_code code; | |
5ab9749e | 302 | |
4b58290f GK |
303 | if (! op) |
304 | { | |
305 | if (need_longbranch) | |
306 | ccode = "jmpf"; | |
307 | else | |
308 | ccode = "br"; | |
309 | sprintf (string, "%s %s", ccode, label); | |
310 | return string; | |
311 | } | |
312 | ||
313 | code = GET_CODE (op); | |
314 | ||
a21eaf5e | 315 | if (! REG_P (XEXP (op, 0))) |
4b58290f GK |
316 | { |
317 | code = swap_condition (code); | |
318 | operands = "%3,%2"; | |
319 | } | |
320 | else | |
321 | operands = "%2,%3"; | |
322 | ||
323 | /* Work out which way this really branches. */ | |
324 | if (really_reversed) | |
325 | code = reverse_condition (code); | |
326 | ||
327 | switch (code) | |
328 | { | |
329 | case EQ: ccode = "z"; break; | |
330 | case NE: ccode = "nz"; break; | |
331 | case GE: ccode = "ge"; break; | |
332 | case LT: ccode = "lt"; break; | |
333 | case GT: ccode = "gt"; break; | |
334 | case LE: ccode = "le"; break; | |
335 | case GEU: ccode = "nc"; break; | |
336 | case LTU: ccode = "c"; break; | |
337 | case GTU: ccode = "hi"; break; | |
338 | case LEU: ccode = "ls"; break; | |
5ab9749e | 339 | |
4b58290f | 340 | default: |
4718bfd8 | 341 | gcc_unreachable (); |
4b58290f GK |
342 | } |
343 | ||
344 | if (need_longbranch) | |
0a2aaacc | 345 | templ = "b%s %s,.+8 | jmpf %s"; |
4b58290f | 346 | else |
0a2aaacc KG |
347 | templ = "b%s %s,%s"; |
348 | sprintf (string, templ, ccode, operands, label); | |
5ab9749e | 349 | |
4b58290f GK |
350 | return string; |
351 | } | |
352 | ||
353 | /* Return the string to output a conditional branch to LABEL, which is | |
354 | the operand number of the label, but suitable for the tail of a | |
355 | SImode branch. | |
356 | ||
357 | OP is the conditional expression (OP is never NULL_RTX). | |
358 | ||
5e7a8ee0 | 359 | REVERSED is nonzero if we should reverse the sense of the comparison. |
4b58290f GK |
360 | |
361 | INSN is the insn. */ | |
362 | ||
363 | char * | |
84034c69 DM |
364 | xstormy16_output_cbranch_si (rtx op, const char *label, int reversed, |
365 | rtx_insn *insn) | |
4b58290f GK |
366 | { |
367 | static char string[64]; | |
368 | int need_longbranch = get_attr_length (insn) >= 8; | |
369 | int really_reversed = reversed ^ need_longbranch; | |
370 | const char *ccode; | |
0a2aaacc | 371 | const char *templ; |
4b58290f GK |
372 | char prevop[16]; |
373 | enum rtx_code code; | |
5ab9749e | 374 | |
4b58290f GK |
375 | code = GET_CODE (op); |
376 | ||
377 | /* Work out which way this really branches. */ | |
378 | if (really_reversed) | |
379 | code = reverse_condition (code); | |
380 | ||
381 | switch (code) | |
382 | { | |
383 | case EQ: ccode = "z"; break; | |
384 | case NE: ccode = "nz"; break; | |
385 | case GE: ccode = "ge"; break; | |
386 | case LT: ccode = "lt"; break; | |
387 | case GEU: ccode = "nc"; break; | |
388 | case LTU: ccode = "c"; break; | |
389 | ||
390 | /* The missing codes above should never be generated. */ | |
391 | default: | |
4718bfd8 | 392 | gcc_unreachable (); |
4b58290f GK |
393 | } |
394 | ||
395 | switch (code) | |
396 | { | |
397 | case EQ: case NE: | |
398 | { | |
399 | int regnum; | |
5ab9749e | 400 | |
a21eaf5e | 401 | gcc_assert (REG_P (XEXP (op, 0))); |
5ab9749e | 402 | |
4b58290f GK |
403 | regnum = REGNO (XEXP (op, 0)); |
404 | sprintf (prevop, "or %s,%s", reg_names[regnum], reg_names[regnum+1]); | |
405 | } | |
406 | break; | |
407 | ||
408 | case GE: case LT: case GEU: case LTU: | |
409 | strcpy (prevop, "sbc %2,%3"); | |
410 | break; | |
411 | ||
412 | default: | |
4718bfd8 | 413 | gcc_unreachable (); |
4b58290f GK |
414 | } |
415 | ||
416 | if (need_longbranch) | |
0a2aaacc | 417 | templ = "%s | b%s .+6 | jmpf %s"; |
4b58290f | 418 | else |
0a2aaacc KG |
419 | templ = "%s | b%s %s"; |
420 | sprintf (string, templ, prevop, ccode, label); | |
5ab9749e | 421 | |
4b58290f GK |
422 | return string; |
423 | } | |
424 | \f | |
425 | /* Many machines have some registers that cannot be copied directly to or from | |
426 | memory or even from other types of registers. An example is the `MQ' | |
427 | register, which on most machines, can only be copied to or from general | |
428 | registers, but not memory. Some machines allow copying all registers to and | |
429 | from memory, but require a scratch register for stores to some memory | |
430 | locations (e.g., those with symbolic address on the RT, and those with | |
981f6289 | 431 | certain symbolic address on the SPARC when compiling PIC). In some cases, |
4b58290f GK |
432 | both an intermediate and a scratch register are required. |
433 | ||
434 | You should define these macros to indicate to the reload phase that it may | |
435 | need to allocate at least one register for a reload in addition to the | |
436 | register to contain the data. Specifically, if copying X to a register | |
0a2aaacc | 437 | RCLASS in MODE requires an intermediate register, you should define |
4b58290f GK |
438 | `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of |
439 | whose registers can be used as intermediate registers or scratch registers. | |
440 | ||
0a2aaacc | 441 | If copying a register RCLASS in MODE to X requires an intermediate or scratch |
4b58290f GK |
442 | register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the |
443 | largest register class required. If the requirements for input and output | |
444 | reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used | |
445 | instead of defining both macros identically. | |
446 | ||
447 | The values returned by these macros are often `GENERAL_REGS'. Return | |
448 | `NO_REGS' if no spare register is needed; i.e., if X can be directly copied | |
0a2aaacc | 449 | to or from a register of RCLASS in MODE without requiring a scratch register. |
4b58290f GK |
450 | Do not define this macro if it would always return `NO_REGS'. |
451 | ||
452 | If a scratch register is required (either with or without an intermediate | |
453 | register), you should define patterns for `reload_inM' or `reload_outM', as | |
454 | required.. These patterns, which will normally be implemented with a | |
455 | `define_expand', should be similar to the `movM' patterns, except that | |
456 | operand 2 is the scratch register. | |
457 | ||
458 | Define constraints for the reload register and scratch register that contain | |
459 | a single register class. If the original reload register (whose class is | |
0a2aaacc | 460 | RCLASS) can meet the constraint given in the pattern, the value returned by |
4b58290f GK |
461 | these macros is used for the class of the scratch register. Otherwise, two |
462 | additional reload registers are required. Their classes are obtained from | |
463 | the constraints in the insn pattern. | |
464 | ||
465 | X might be a pseudo-register or a `subreg' of a pseudo-register, which could | |
466 | either be in a hard register or in memory. Use `true_regnum' to find out; | |
467 | it will return -1 if the pseudo is in memory and the hard register number if | |
468 | it is in a register. | |
469 | ||
470 | These macros should not be used in the case where a particular class of | |
471 | registers can only be copied to memory and not to another class of | |
472 | registers. In that case, secondary reload registers are not needed and | |
473 | would not be helpful. Instead, a stack location must be used to perform the | |
e03f5d43 | 474 | copy and the `movM' pattern should use memory as an intermediate storage. |
4b58290f GK |
475 | This case often occurs between floating-point and general registers. */ |
476 | ||
477 | enum reg_class | |
0a2aaacc | 478 | xstormy16_secondary_reload_class (enum reg_class rclass, |
ef4bddc2 | 479 | machine_mode mode ATTRIBUTE_UNUSED, |
51c16b7e | 480 | rtx x) |
4b58290f GK |
481 | { |
482 | /* This chip has the interesting property that only the first eight | |
483 | registers can be moved to/from memory. */ | |
a21eaf5e NC |
484 | if ((MEM_P (x) |
485 | || ((GET_CODE (x) == SUBREG || REG_P (x)) | |
4b58290f GK |
486 | && (true_regnum (x) == -1 |
487 | || true_regnum (x) >= FIRST_PSEUDO_REGISTER))) | |
0a2aaacc | 488 | && ! reg_class_subset_p (rclass, EIGHT_REGS)) |
4b58290f GK |
489 | return EIGHT_REGS; |
490 | ||
4b58290f GK |
491 | return NO_REGS; |
492 | } | |
493 | ||
ef795fc2 AS |
494 | /* Worker function for TARGET_PREFERRED_RELOAD_CLASS |
495 | and TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */ | |
496 | ||
497 | static reg_class_t | |
498 | xstormy16_preferred_reload_class (rtx x, reg_class_t rclass) | |
4b58290f | 499 | { |
a21eaf5e | 500 | if (rclass == GENERAL_REGS && MEM_P (x)) |
4b58290f GK |
501 | return EIGHT_REGS; |
502 | ||
0a2aaacc | 503 | return rclass; |
4b58290f GK |
504 | } |
505 | ||
54e9a19d DD |
506 | /* Predicate for symbols and addresses that reflect special 8-bit |
507 | addressing. */ | |
5ab9749e | 508 | |
54e9a19d DD |
509 | int |
510 | xstormy16_below100_symbol (rtx x, | |
ef4bddc2 | 511 | machine_mode mode ATTRIBUTE_UNUSED) |
54e9a19d DD |
512 | { |
513 | if (GET_CODE (x) == CONST) | |
514 | x = XEXP (x, 0); | |
a21eaf5e | 515 | if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) |
54e9a19d | 516 | x = XEXP (x, 0); |
2f806f3b | 517 | |
54e9a19d | 518 | if (GET_CODE (x) == SYMBOL_REF) |
2f806f3b NC |
519 | return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_XSTORMY16_BELOW100) != 0; |
520 | ||
a21eaf5e | 521 | if (CONST_INT_P (x)) |
54e9a19d DD |
522 | { |
523 | HOST_WIDE_INT i = INTVAL (x); | |
a21eaf5e | 524 | |
54e9a19d DD |
525 | if ((i >= 0x0000 && i <= 0x00ff) |
526 | || (i >= 0x7f00 && i <= 0x7fff)) | |
527 | return 1; | |
528 | } | |
529 | return 0; | |
530 | } | |
531 | ||
54e9a19d DD |
532 | /* Likewise, but only for non-volatile MEMs, for patterns where the |
533 | MEM will get split into smaller sized accesses. */ | |
5ab9749e | 534 | |
54e9a19d | 535 | int |
ef4bddc2 | 536 | xstormy16_splittable_below100_operand (rtx x, machine_mode mode) |
54e9a19d | 537 | { |
a21eaf5e | 538 | if (MEM_P (x) && MEM_VOLATILE_P (x)) |
54e9a19d DD |
539 | return 0; |
540 | return xstormy16_below100_operand (x, mode); | |
541 | } | |
542 | ||
54e9a19d DD |
543 | /* Expand an 8-bit IOR. This either detects the one case we can |
544 | actually do, or uses a 16-bit IOR. */ | |
5ab9749e | 545 | |
54e9a19d DD |
546 | void |
547 | xstormy16_expand_iorqi3 (rtx *operands) | |
548 | { | |
549 | rtx in, out, outsub, val; | |
550 | ||
551 | out = operands[0]; | |
552 | in = operands[1]; | |
553 | val = operands[2]; | |
554 | ||
555 | if (xstormy16_onebit_set_operand (val, QImode)) | |
556 | { | |
557 | if (!xstormy16_below100_or_register (in, QImode)) | |
558 | in = copy_to_mode_reg (QImode, in); | |
559 | if (!xstormy16_below100_or_register (out, QImode)) | |
560 | out = gen_reg_rtx (QImode); | |
561 | emit_insn (gen_iorqi3_internal (out, in, val)); | |
562 | if (out != operands[0]) | |
563 | emit_move_insn (operands[0], out); | |
564 | return; | |
565 | } | |
566 | ||
a21eaf5e | 567 | if (! REG_P (in)) |
54e9a19d | 568 | in = copy_to_mode_reg (QImode, in); |
a21eaf5e NC |
569 | |
570 | if (! REG_P (val) && ! CONST_INT_P (val)) | |
54e9a19d | 571 | val = copy_to_mode_reg (QImode, val); |
a21eaf5e NC |
572 | |
573 | if (! REG_P (out)) | |
54e9a19d DD |
574 | out = gen_reg_rtx (QImode); |
575 | ||
576 | in = simplify_gen_subreg (HImode, in, QImode, 0); | |
577 | outsub = simplify_gen_subreg (HImode, out, QImode, 0); | |
a21eaf5e NC |
578 | |
579 | if (! CONST_INT_P (val)) | |
54e9a19d DD |
580 | val = simplify_gen_subreg (HImode, val, QImode, 0); |
581 | ||
582 | emit_insn (gen_iorhi3 (outsub, in, val)); | |
583 | ||
584 | if (out != operands[0]) | |
585 | emit_move_insn (operands[0], out); | |
586 | } | |
587 | ||
5ab9749e NC |
588 | /* Expand an 8-bit AND. This either detects the one case we can |
589 | actually do, or uses a 16-bit AND. */ | |
590 | ||
54e9a19d DD |
591 | void |
592 | xstormy16_expand_andqi3 (rtx *operands) | |
593 | { | |
594 | rtx in, out, outsub, val; | |
595 | ||
596 | out = operands[0]; | |
597 | in = operands[1]; | |
598 | val = operands[2]; | |
599 | ||
600 | if (xstormy16_onebit_clr_operand (val, QImode)) | |
601 | { | |
602 | if (!xstormy16_below100_or_register (in, QImode)) | |
603 | in = copy_to_mode_reg (QImode, in); | |
604 | if (!xstormy16_below100_or_register (out, QImode)) | |
605 | out = gen_reg_rtx (QImode); | |
606 | emit_insn (gen_andqi3_internal (out, in, val)); | |
607 | if (out != operands[0]) | |
608 | emit_move_insn (operands[0], out); | |
609 | return; | |
610 | } | |
611 | ||
a21eaf5e | 612 | if (! REG_P (in)) |
54e9a19d | 613 | in = copy_to_mode_reg (QImode, in); |
a21eaf5e NC |
614 | |
615 | if (! REG_P (val) && ! CONST_INT_P (val)) | |
54e9a19d | 616 | val = copy_to_mode_reg (QImode, val); |
a21eaf5e NC |
617 | |
618 | if (! REG_P (out)) | |
54e9a19d DD |
619 | out = gen_reg_rtx (QImode); |
620 | ||
621 | in = simplify_gen_subreg (HImode, in, QImode, 0); | |
622 | outsub = simplify_gen_subreg (HImode, out, QImode, 0); | |
a21eaf5e NC |
623 | |
624 | if (! CONST_INT_P (val)) | |
54e9a19d DD |
625 | val = simplify_gen_subreg (HImode, val, QImode, 0); |
626 | ||
627 | emit_insn (gen_andhi3 (outsub, in, val)); | |
628 | ||
629 | if (out != operands[0]) | |
630 | emit_move_insn (operands[0], out); | |
631 | } | |
632 | ||
4b58290f | 633 | #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \ |
a21eaf5e | 634 | (CONST_INT_P (X) \ |
4b58290f GK |
635 | && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 2048) < 4096) |
636 | ||
637 | #define LEGITIMATE_ADDRESS_CONST_INT_P(X, OFFSET) \ | |
a21eaf5e | 638 | (CONST_INT_P (X) \ |
4b58290f GK |
639 | && INTVAL (X) + (OFFSET) >= 0 \ |
640 | && INTVAL (X) + (OFFSET) < 0x8000 \ | |
641 | && (INTVAL (X) + (OFFSET) < 0x100 || INTVAL (X) + (OFFSET) >= 0x7F00)) | |
642 | ||
d634083b | 643 | bool |
ef4bddc2 | 644 | xstormy16_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, |
c6c3dba9 | 645 | rtx x, bool strict) |
4b58290f GK |
646 | { |
647 | if (LEGITIMATE_ADDRESS_CONST_INT_P (x, 0)) | |
a21eaf5e | 648 | return true; |
4b58290f GK |
649 | |
650 | if (GET_CODE (x) == PLUS | |
651 | && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 0)) | |
813ab1d7 NC |
652 | { |
653 | x = XEXP (x, 0); | |
654 | /* PR 31232: Do not allow INT+INT as an address. */ | |
a21eaf5e NC |
655 | if (CONST_INT_P (x)) |
656 | return false; | |
813ab1d7 | 657 | } |
5ab9749e | 658 | |
a21eaf5e | 659 | if ((GET_CODE (x) == PRE_MODIFY && CONST_INT_P (XEXP (XEXP (x, 1), 1))) |
f3922fd2 | 660 | || GET_CODE (x) == POST_INC |
4b58290f GK |
661 | || GET_CODE (x) == PRE_DEC) |
662 | x = XEXP (x, 0); | |
5ab9749e | 663 | |
a21eaf5e NC |
664 | if (REG_P (x) |
665 | && REGNO_OK_FOR_BASE_P (REGNO (x)) | |
4b58290f | 666 | && (! strict || REGNO (x) < FIRST_PSEUDO_REGISTER)) |
a21eaf5e | 667 | return true; |
54e9a19d | 668 | |
f84fe9b6 | 669 | if (xstormy16_below100_symbol (x, mode)) |
a21eaf5e | 670 | return true; |
5ab9749e | 671 | |
a21eaf5e | 672 | return false; |
4b58290f GK |
673 | } |
674 | ||
192997cf | 675 | /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. |
5ab9749e | 676 | |
4b58290f GK |
677 | On this chip, this is true if the address is valid with an offset |
678 | of 0 but not of 6, because in that case it cannot be used as an | |
679 | address for DImode or DFmode, or if the address is a post-increment | |
680 | or pre-decrement address. */ | |
5ab9749e | 681 | |
192997cf | 682 | static bool |
5bfed9a9 GJL |
683 | xstormy16_mode_dependent_address_p (const_rtx x, |
684 | addr_space_t as ATTRIBUTE_UNUSED) | |
4b58290f GK |
685 | { |
686 | if (LEGITIMATE_ADDRESS_CONST_INT_P (x, 0) | |
687 | && ! LEGITIMATE_ADDRESS_CONST_INT_P (x, 6)) | |
192997cf | 688 | return true; |
5ab9749e | 689 | |
4b58290f GK |
690 | if (GET_CODE (x) == PLUS |
691 | && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 0) | |
692 | && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 6)) | |
192997cf | 693 | return true; |
4b58290f | 694 | |
b9a76028 | 695 | /* Auto-increment addresses are now treated generically in recog.c. */ |
192997cf | 696 | return false; |
4b58290f GK |
697 | } |
698 | ||
4b58290f | 699 | int |
ef4bddc2 | 700 | short_memory_operand (rtx x, machine_mode mode) |
4b58290f GK |
701 | { |
702 | if (! memory_operand (x, mode)) | |
703 | return 0; | |
704 | return (GET_CODE (XEXP (x, 0)) != PLUS); | |
705 | } | |
706 | ||
fae778eb | 707 | /* Splitter for the 'move' patterns, for modes not directly implemented |
4b58290f GK |
708 | by hardware. Emit insns to copy a value of mode MODE from SRC to |
709 | DEST. | |
710 | ||
5ab9749e | 711 | This function is only called when reload_completed. */ |
4b58290f | 712 | |
5ab9749e | 713 | void |
ef4bddc2 | 714 | xstormy16_split_move (machine_mode mode, rtx dest, rtx src) |
4b58290f GK |
715 | { |
716 | int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; | |
717 | int direction, end, i; | |
718 | int src_modifies = 0; | |
719 | int dest_modifies = 0; | |
720 | int src_volatile = 0; | |
721 | int dest_volatile = 0; | |
722 | rtx mem_operand; | |
7c87e9f9 | 723 | rtx auto_inc_reg_rtx = NULL_RTX; |
5ab9749e | 724 | |
4b58290f | 725 | /* Check initial conditions. */ |
4718bfd8 NS |
726 | gcc_assert (reload_completed |
727 | && mode != QImode && mode != HImode | |
728 | && nonimmediate_operand (dest, mode) | |
729 | && general_operand (src, mode)); | |
4b58290f GK |
730 | |
731 | /* This case is not supported below, and shouldn't be generated. */ | |
a21eaf5e | 732 | gcc_assert (! MEM_P (dest) || ! MEM_P (src)); |
4b58290f GK |
733 | |
734 | /* This case is very very bad after reload, so trap it now. */ | |
4718bfd8 | 735 | gcc_assert (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG); |
4b58290f GK |
736 | |
737 | /* The general idea is to copy by words, offsetting the source and | |
738 | destination. Normally the least-significant word will be copied | |
5ab9749e | 739 | first, but for pre-dec operations it's better to copy the |
4b58290f | 740 | most-significant word first. Only one operand can be a pre-dec |
5ab9749e | 741 | or post-inc operand. |
4b58290f GK |
742 | |
743 | It's also possible that the copy overlaps so that the direction | |
744 | must be reversed. */ | |
745 | direction = 1; | |
5ab9749e | 746 | |
a21eaf5e | 747 | if (MEM_P (dest)) |
4b58290f GK |
748 | { |
749 | mem_operand = XEXP (dest, 0); | |
750 | dest_modifies = side_effects_p (mem_operand); | |
7c87e9f9 CM |
751 | if (auto_inc_p (mem_operand)) |
752 | auto_inc_reg_rtx = XEXP (mem_operand, 0); | |
4b58290f GK |
753 | dest_volatile = MEM_VOLATILE_P (dest); |
754 | if (dest_volatile) | |
755 | { | |
756 | dest = copy_rtx (dest); | |
757 | MEM_VOLATILE_P (dest) = 0; | |
758 | } | |
759 | } | |
a21eaf5e | 760 | else if (MEM_P (src)) |
4b58290f GK |
761 | { |
762 | mem_operand = XEXP (src, 0); | |
763 | src_modifies = side_effects_p (mem_operand); | |
7c87e9f9 CM |
764 | if (auto_inc_p (mem_operand)) |
765 | auto_inc_reg_rtx = XEXP (mem_operand, 0); | |
4b58290f GK |
766 | src_volatile = MEM_VOLATILE_P (src); |
767 | if (src_volatile) | |
768 | { | |
769 | src = copy_rtx (src); | |
770 | MEM_VOLATILE_P (src) = 0; | |
771 | } | |
772 | } | |
773 | else | |
774 | mem_operand = NULL_RTX; | |
775 | ||
776 | if (mem_operand == NULL_RTX) | |
777 | { | |
a21eaf5e NC |
778 | if (REG_P (src) |
779 | && REG_P (dest) | |
4b58290f GK |
780 | && reg_overlap_mentioned_p (dest, src) |
781 | && REGNO (dest) > REGNO (src)) | |
782 | direction = -1; | |
783 | } | |
784 | else if (GET_CODE (mem_operand) == PRE_DEC | |
5ab9749e | 785 | || (GET_CODE (mem_operand) == PLUS |
4b58290f GK |
786 | && GET_CODE (XEXP (mem_operand, 0)) == PRE_DEC)) |
787 | direction = -1; | |
a21eaf5e | 788 | else if (MEM_P (src) && reg_overlap_mentioned_p (dest, src)) |
4b58290f GK |
789 | { |
790 | int regno; | |
5ab9749e | 791 | |
a21eaf5e | 792 | gcc_assert (REG_P (dest)); |
4b58290f | 793 | regno = REGNO (dest); |
5ab9749e | 794 | |
4718bfd8 NS |
795 | gcc_assert (refers_to_regno_p (regno, regno + num_words, |
796 | mem_operand, 0)); | |
5ab9749e | 797 | |
c9bd6bcd | 798 | if (refers_to_regno_p (regno, mem_operand)) |
4b58290f GK |
799 | direction = -1; |
800 | else if (refers_to_regno_p (regno + num_words - 1, regno + num_words, | |
801 | mem_operand, 0)) | |
802 | direction = 1; | |
803 | else | |
804 | /* This means something like | |
805 | (set (reg:DI r0) (mem:DI (reg:HI r1))) | |
806 | which we'd need to support by doing the set of the second word | |
807 | last. */ | |
4718bfd8 | 808 | gcc_unreachable (); |
4b58290f GK |
809 | } |
810 | ||
811 | end = direction < 0 ? -1 : num_words; | |
812 | for (i = direction < 0 ? num_words - 1 : 0; i != end; i += direction) | |
813 | { | |
7c87e9f9 CM |
814 | rtx w_src, w_dest, insn; |
815 | ||
4b58290f GK |
816 | if (src_modifies) |
817 | w_src = gen_rtx_MEM (word_mode, mem_operand); | |
818 | else | |
819 | w_src = simplify_gen_subreg (word_mode, src, mode, i * UNITS_PER_WORD); | |
820 | if (src_volatile) | |
821 | MEM_VOLATILE_P (w_src) = 1; | |
822 | if (dest_modifies) | |
823 | w_dest = gen_rtx_MEM (word_mode, mem_operand); | |
824 | else | |
5ab9749e | 825 | w_dest = simplify_gen_subreg (word_mode, dest, mode, |
4b58290f GK |
826 | i * UNITS_PER_WORD); |
827 | if (dest_volatile) | |
828 | MEM_VOLATILE_P (w_dest) = 1; | |
5ab9749e | 829 | |
4b58290f | 830 | /* The simplify_subreg calls must always be able to simplify. */ |
4718bfd8 NS |
831 | gcc_assert (GET_CODE (w_src) != SUBREG |
832 | && GET_CODE (w_dest) != SUBREG); | |
5ab9749e | 833 | |
f7df4a84 | 834 | insn = emit_insn (gen_rtx_SET (w_dest, w_src)); |
7c87e9f9 CM |
835 | if (auto_inc_reg_rtx) |
836 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC, | |
837 | auto_inc_reg_rtx, | |
838 | REG_NOTES (insn)); | |
4b58290f GK |
839 | } |
840 | } | |
841 | ||
842 | /* Expander for the 'move' patterns. Emit insns to copy a value of | |
843 | mode MODE from SRC to DEST. */ | |
844 | ||
5ab9749e | 845 | void |
ef4bddc2 | 846 | xstormy16_expand_move (machine_mode mode, rtx dest, rtx src) |
4b58290f | 847 | { |
a21eaf5e | 848 | if (MEM_P (dest) && (GET_CODE (XEXP (dest, 0)) == PRE_MODIFY)) |
f3922fd2 DD |
849 | { |
850 | rtx pmv = XEXP (dest, 0); | |
851 | rtx dest_reg = XEXP (pmv, 0); | |
852 | rtx dest_mod = XEXP (pmv, 1); | |
f7df4a84 | 853 | rtx set = gen_rtx_SET (dest_reg, dest_mod); |
b72bbbcb | 854 | rtx clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); |
5ab9749e | 855 | |
f3922fd2 DD |
856 | dest = gen_rtx_MEM (mode, dest_reg); |
857 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); | |
858 | } | |
a21eaf5e | 859 | else if (MEM_P (src) && (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)) |
f3922fd2 DD |
860 | { |
861 | rtx pmv = XEXP (src, 0); | |
862 | rtx src_reg = XEXP (pmv, 0); | |
863 | rtx src_mod = XEXP (pmv, 1); | |
f7df4a84 | 864 | rtx set = gen_rtx_SET (src_reg, src_mod); |
b72bbbcb | 865 | rtx clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); |
5ab9749e | 866 | |
f3922fd2 DD |
867 | src = gen_rtx_MEM (mode, src_reg); |
868 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); | |
869 | } | |
5ab9749e | 870 | |
4b58290f GK |
871 | /* There are only limited immediate-to-memory move instructions. */ |
872 | if (! reload_in_progress | |
873 | && ! reload_completed | |
a21eaf5e NC |
874 | && MEM_P (dest) |
875 | && (! CONST_INT_P (XEXP (dest, 0)) | |
c6243b4c | 876 | || ! xstormy16_legitimate_address_p (mode, XEXP (dest, 0), 0)) |
54e9a19d | 877 | && ! xstormy16_below100_operand (dest, mode) |
a21eaf5e | 878 | && ! REG_P (src) |
4b58290f GK |
879 | && GET_CODE (src) != SUBREG) |
880 | src = copy_to_mode_reg (mode, src); | |
881 | ||
882 | /* Don't emit something we would immediately split. */ | |
883 | if (reload_completed | |
884 | && mode != HImode && mode != QImode) | |
885 | { | |
c6243b4c | 886 | xstormy16_split_move (mode, dest, src); |
4b58290f GK |
887 | return; |
888 | } | |
5ab9749e | 889 | |
f7df4a84 | 890 | emit_insn (gen_rtx_SET (dest, src)); |
4b58290f | 891 | } |
4b58290f GK |
892 | \f |
893 | /* Stack Layout: | |
894 | ||
895 | The stack is laid out as follows: | |
896 | ||
897 | SP-> | |
898 | FP-> Local variables | |
899 | Register save area (up to 4 words) | |
900 | Argument register save area for stdarg (NUM_ARGUMENT_REGISTERS words) | |
901 | ||
902 | AP-> Return address (two words) | |
903 | 9th procedure parameter word | |
904 | 10th procedure parameter word | |
905 | ... | |
906 | last procedure parameter word | |
907 | ||
908 | The frame pointer location is tuned to make it most likely that all | |
909 | parameters and local variables can be accessed using a load-indexed | |
910 | instruction. */ | |
911 | ||
912 | /* A structure to describe the layout. */ | |
c6243b4c | 913 | struct xstormy16_stack_layout |
4b58290f GK |
914 | { |
915 | /* Size of the topmost three items on the stack. */ | |
916 | int locals_size; | |
917 | int register_save_size; | |
918 | int stdarg_save_size; | |
919 | /* Sum of the above items. */ | |
920 | int frame_size; | |
921 | /* Various offsets. */ | |
922 | int first_local_minus_ap; | |
923 | int sp_minus_fp; | |
924 | int fp_minus_ap; | |
925 | }; | |
926 | ||
927 | /* Does REGNO need to be saved? */ | |
928 | #define REG_NEEDS_SAVE(REGNUM, IFUN) \ | |
6fb5fa3c | 929 | ((df_regs_ever_live_p (REGNUM) && ! call_used_regs[REGNUM]) \ |
4b58290f | 930 | || (IFUN && ! fixed_regs[REGNUM] && call_used_regs[REGNUM] \ |
d40ba0b6 | 931 | && (REGNUM != CARRY_REGNUM) \ |
416ff32e | 932 | && (df_regs_ever_live_p (REGNUM) || ! crtl->is_leaf))) |
4b58290f GK |
933 | |
934 | /* Compute the stack layout. */ | |
5ab9749e NC |
935 | |
936 | struct xstormy16_stack_layout | |
51c16b7e | 937 | xstormy16_compute_stack_layout (void) |
4b58290f | 938 | { |
c6243b4c | 939 | struct xstormy16_stack_layout layout; |
4b58290f | 940 | int regno; |
c6243b4c | 941 | const int ifun = xstormy16_interrupt_function_p (); |
4b58290f GK |
942 | |
943 | layout.locals_size = get_frame_size (); | |
5ab9749e | 944 | |
4b58290f GK |
945 | layout.register_save_size = 0; |
946 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
947 | if (REG_NEEDS_SAVE (regno, ifun)) | |
948 | layout.register_save_size += UNITS_PER_WORD; | |
5ab9749e | 949 | |
e3b5732b | 950 | if (cfun->stdarg) |
4b58290f GK |
951 | layout.stdarg_save_size = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD; |
952 | else | |
953 | layout.stdarg_save_size = 0; | |
5ab9749e NC |
954 | |
955 | layout.frame_size = (layout.locals_size | |
956 | + layout.register_save_size | |
4b58290f | 957 | + layout.stdarg_save_size); |
5ab9749e | 958 | |
38173d38 | 959 | if (crtl->args.size <= 2048 && crtl->args.size != -1) |
4b58290f | 960 | { |
5ab9749e | 961 | if (layout.frame_size - INCOMING_FRAME_SP_OFFSET |
38173d38 | 962 | + crtl->args.size <= 2048) |
b72bbbcb | 963 | layout.fp_minus_ap = layout.frame_size - INCOMING_FRAME_SP_OFFSET; |
4b58290f | 964 | else |
38173d38 | 965 | layout.fp_minus_ap = 2048 - crtl->args.size; |
4b58290f GK |
966 | } |
967 | else | |
5ab9749e | 968 | layout.fp_minus_ap = (layout.stdarg_save_size |
4b58290f | 969 | + layout.register_save_size |
b72bbbcb | 970 | - INCOMING_FRAME_SP_OFFSET); |
5ab9749e | 971 | layout.sp_minus_fp = (layout.frame_size - INCOMING_FRAME_SP_OFFSET |
4b58290f GK |
972 | - layout.fp_minus_ap); |
973 | layout.first_local_minus_ap = layout.sp_minus_fp - layout.locals_size; | |
974 | return layout; | |
975 | } | |
976 | ||
7b5cbb57 AS |
977 | /* Worker function for TARGET_CAN_ELIMINATE. */ |
978 | ||
979 | static bool | |
980 | xstormy16_can_eliminate (const int from, const int to) | |
981 | { | |
982 | return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM | |
983 | ? ! frame_pointer_needed | |
984 | : true); | |
985 | } | |
986 | ||
4b58290f | 987 | /* Determine how all the special registers get eliminated. */ |
5ab9749e | 988 | |
4b58290f | 989 | int |
51c16b7e | 990 | xstormy16_initial_elimination_offset (int from, int to) |
4b58290f | 991 | { |
c6243b4c | 992 | struct xstormy16_stack_layout layout; |
4b58290f | 993 | int result; |
5ab9749e | 994 | |
c6243b4c | 995 | layout = xstormy16_compute_stack_layout (); |
4b58290f GK |
996 | |
997 | if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) | |
998 | result = layout.sp_minus_fp - layout.locals_size; | |
999 | else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
b72bbbcb | 1000 | result = - layout.locals_size; |
4b58290f | 1001 | else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) |
b72bbbcb | 1002 | result = - layout.fp_minus_ap; |
4b58290f | 1003 | else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
b72bbbcb | 1004 | result = - (layout.sp_minus_fp + layout.fp_minus_ap); |
4b58290f | 1005 | else |
4718bfd8 | 1006 | gcc_unreachable (); |
4b58290f GK |
1007 | |
1008 | return result; | |
1009 | } | |
1010 | ||
1011 | static rtx | |
51c16b7e | 1012 | emit_addhi3_postreload (rtx dest, rtx src0, rtx src1) |
4b58290f GK |
1013 | { |
1014 | rtx set, clobber, insn; | |
5ab9749e | 1015 | |
f7df4a84 | 1016 | set = gen_rtx_SET (dest, gen_rtx_PLUS (HImode, src0, src1)); |
b72bbbcb | 1017 | clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); |
4b58290f GK |
1018 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); |
1019 | return insn; | |
1020 | } | |
1021 | ||
41441dc7 NB |
1022 | /* Called after register allocation to add any instructions needed for |
1023 | the prologue. Using a prologue insn is favored compared to putting | |
1024 | all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro, | |
1025 | since it allows the scheduler to intermix instructions with the | |
1026 | saves of the caller saved registers. In some cases, it might be | |
1027 | necessary to emit a barrier instruction as the last insn to prevent | |
1028 | such scheduling. | |
4b58290f GK |
1029 | |
1030 | Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 | |
1031 | so that the debug info generation code can handle them properly. */ | |
5ab9749e | 1032 | |
4b58290f | 1033 | void |
51c16b7e | 1034 | xstormy16_expand_prologue (void) |
4b58290f | 1035 | { |
c6243b4c | 1036 | struct xstormy16_stack_layout layout; |
4b58290f GK |
1037 | int regno; |
1038 | rtx insn; | |
1039 | rtx mem_push_rtx; | |
c6243b4c | 1040 | const int ifun = xstormy16_interrupt_function_p (); |
5ab9749e | 1041 | |
4b58290f GK |
1042 | mem_push_rtx = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); |
1043 | mem_push_rtx = gen_rtx_MEM (HImode, mem_push_rtx); | |
5ab9749e | 1044 | |
c6243b4c | 1045 | layout = xstormy16_compute_stack_layout (); |
4b58290f | 1046 | |
f3922fd2 | 1047 | if (layout.locals_size >= 32768) |
ab532386 | 1048 | error ("local variable memory requirements exceed capacity"); |
f3922fd2 | 1049 | |
315bdf71 NC |
1050 | if (flag_stack_usage_info) |
1051 | current_function_static_stack_size = layout.frame_size; | |
1052 | ||
4b58290f GK |
1053 | /* Save the argument registers if necessary. */ |
1054 | if (layout.stdarg_save_size) | |
5ab9749e | 1055 | for (regno = FIRST_ARGUMENT_REGISTER; |
4b58290f GK |
1056 | regno < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS; |
1057 | regno++) | |
1058 | { | |
f3922fd2 | 1059 | rtx dwarf; |
4b58290f | 1060 | rtx reg = gen_rtx_REG (HImode, regno); |
f3922fd2 | 1061 | |
4b58290f GK |
1062 | insn = emit_move_insn (mem_push_rtx, reg); |
1063 | RTX_FRAME_RELATED_P (insn) = 1; | |
f3922fd2 DD |
1064 | |
1065 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (2)); | |
5ab9749e | 1066 | |
f7df4a84 | 1067 | XVECEXP (dwarf, 0, 0) = gen_rtx_SET (gen_rtx_MEM (Pmode, stack_pointer_rtx), |
f3922fd2 | 1068 | reg); |
f7df4a84 | 1069 | XVECEXP (dwarf, 0, 1) = gen_rtx_SET (stack_pointer_rtx, |
0a81f074 RS |
1070 | plus_constant (Pmode, |
1071 | stack_pointer_rtx, | |
f3922fd2 | 1072 | GET_MODE_SIZE (Pmode))); |
f1cb6795 | 1073 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
f3922fd2 DD |
1074 | RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 0)) = 1; |
1075 | RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 1)) = 1; | |
4b58290f | 1076 | } |
5ab9749e | 1077 | |
4b58290f GK |
1078 | /* Push each of the registers to save. */ |
1079 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
1080 | if (REG_NEEDS_SAVE (regno, ifun)) | |
1081 | { | |
f3922fd2 | 1082 | rtx dwarf; |
4b58290f | 1083 | rtx reg = gen_rtx_REG (HImode, regno); |
f3922fd2 | 1084 | |
4b58290f GK |
1085 | insn = emit_move_insn (mem_push_rtx, reg); |
1086 | RTX_FRAME_RELATED_P (insn) = 1; | |
f3922fd2 DD |
1087 | |
1088 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (2)); | |
5ab9749e | 1089 | |
f7df4a84 | 1090 | XVECEXP (dwarf, 0, 0) = gen_rtx_SET (gen_rtx_MEM (Pmode, stack_pointer_rtx), |
f3922fd2 | 1091 | reg); |
f7df4a84 | 1092 | XVECEXP (dwarf, 0, 1) = gen_rtx_SET (stack_pointer_rtx, |
a6178a25 | 1093 | plus_constant (Pmode, |
0a81f074 | 1094 | stack_pointer_rtx, |
f3922fd2 | 1095 | GET_MODE_SIZE (Pmode))); |
f1cb6795 | 1096 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
f3922fd2 DD |
1097 | RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 0)) = 1; |
1098 | RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 1)) = 1; | |
4b58290f GK |
1099 | } |
1100 | ||
1101 | /* It's just possible that the SP here might be what we need for | |
b1c9bc51 | 1102 | the new FP... */ |
4b58290f | 1103 | if (frame_pointer_needed && layout.sp_minus_fp == layout.locals_size) |
b72bbbcb DD |
1104 | { |
1105 | insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); | |
1106 | RTX_FRAME_RELATED_P (insn) = 1; | |
1107 | } | |
4b58290f GK |
1108 | |
1109 | /* Allocate space for local variables. */ | |
1110 | if (layout.locals_size) | |
1111 | { | |
1112 | insn = emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx, | |
1113 | GEN_INT (layout.locals_size)); | |
1114 | RTX_FRAME_RELATED_P (insn) = 1; | |
1115 | } | |
1116 | ||
1117 | /* Set up the frame pointer, if required. */ | |
1118 | if (frame_pointer_needed && layout.sp_minus_fp != layout.locals_size) | |
1119 | { | |
1120 | insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); | |
b72bbbcb | 1121 | RTX_FRAME_RELATED_P (insn) = 1; |
6208b55d | 1122 | |
4b58290f | 1123 | if (layout.sp_minus_fp) |
b72bbbcb DD |
1124 | { |
1125 | insn = emit_addhi3_postreload (hard_frame_pointer_rtx, | |
1126 | hard_frame_pointer_rtx, | |
1127 | GEN_INT (- layout.sp_minus_fp)); | |
1128 | RTX_FRAME_RELATED_P (insn) = 1; | |
1129 | } | |
4b58290f GK |
1130 | } |
1131 | } | |
1132 | ||
1133 | /* Do we need an epilogue at all? */ | |
5ab9749e | 1134 | |
4b58290f | 1135 | int |
51c16b7e | 1136 | direct_return (void) |
4b58290f | 1137 | { |
5ab9749e | 1138 | return (reload_completed |
2fd7ba4a NC |
1139 | && xstormy16_compute_stack_layout ().frame_size == 0 |
1140 | && ! xstormy16_interrupt_function_p ()); | |
4b58290f GK |
1141 | } |
1142 | ||
41441dc7 | 1143 | /* Called after register allocation to add any instructions needed for |
e03f5d43 | 1144 | the epilogue. Using an epilogue insn is favored compared to putting |
41441dc7 NB |
1145 | all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro, |
1146 | since it allows the scheduler to intermix instructions with the | |
1147 | saves of the caller saved registers. In some cases, it might be | |
1148 | necessary to emit a barrier instruction as the last insn to prevent | |
1149 | such scheduling. */ | |
4b58290f GK |
1150 | |
1151 | void | |
51c16b7e | 1152 | xstormy16_expand_epilogue (void) |
4b58290f | 1153 | { |
c6243b4c | 1154 | struct xstormy16_stack_layout layout; |
a21eaf5e | 1155 | rtx mem_pop_rtx; |
4b58290f | 1156 | int regno; |
c6243b4c | 1157 | const int ifun = xstormy16_interrupt_function_p (); |
5ab9749e | 1158 | |
4b58290f GK |
1159 | mem_pop_rtx = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); |
1160 | mem_pop_rtx = gen_rtx_MEM (HImode, mem_pop_rtx); | |
5ab9749e | 1161 | |
c6243b4c | 1162 | layout = xstormy16_compute_stack_layout (); |
4b58290f GK |
1163 | |
1164 | /* Pop the stack for the locals. */ | |
1165 | if (layout.locals_size) | |
e2470e1b GK |
1166 | { |
1167 | if (frame_pointer_needed && layout.sp_minus_fp == layout.locals_size) | |
1168 | emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); | |
1169 | else | |
b72bbbcb DD |
1170 | emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx, |
1171 | GEN_INT (- layout.locals_size)); | |
e2470e1b | 1172 | } |
4b58290f GK |
1173 | |
1174 | /* Restore any call-saved registers. */ | |
1175 | for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--) | |
1176 | if (REG_NEEDS_SAVE (regno, ifun)) | |
b72bbbcb | 1177 | emit_move_insn (gen_rtx_REG (HImode, regno), mem_pop_rtx); |
5ab9749e | 1178 | |
4b58290f GK |
1179 | /* Pop the stack for the stdarg save area. */ |
1180 | if (layout.stdarg_save_size) | |
b72bbbcb DD |
1181 | emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx, |
1182 | GEN_INT (- layout.stdarg_save_size)); | |
4b58290f GK |
1183 | |
1184 | /* Return. */ | |
1185 | if (ifun) | |
1186 | emit_jump_insn (gen_return_internal_interrupt ()); | |
1187 | else | |
1188 | emit_jump_insn (gen_return_internal ()); | |
1189 | } | |
1190 | ||
1191 | int | |
51c16b7e | 1192 | xstormy16_epilogue_uses (int regno) |
4b58290f GK |
1193 | { |
1194 | if (reload_completed && call_used_regs[regno]) | |
1195 | { | |
c6243b4c | 1196 | const int ifun = xstormy16_interrupt_function_p (); |
4b58290f GK |
1197 | return REG_NEEDS_SAVE (regno, ifun); |
1198 | } | |
1199 | return 0; | |
1200 | } | |
14b56832 DD |
1201 | |
1202 | void | |
51c16b7e | 1203 | xstormy16_function_profiler (void) |
14b56832 DD |
1204 | { |
1205 | sorry ("function_profiler support"); | |
1206 | } | |
4b58290f | 1207 | \f |
6930c98c RS |
1208 | /* Update CUM to advance past argument ARG. Once this is done, |
1209 | the variable CUM is suitable for analyzing the *following* | |
bf425ddd | 1210 | argument with `TARGET_FUNCTION_ARG', etc. |
4b58290f GK |
1211 | |
1212 | This function need not do anything if the argument in question was | |
1213 | passed on the stack. The compiler knows how to track the amount of | |
1214 | stack space used for arguments without any special help. However, | |
c6243b4c | 1215 | it makes life easier for xstormy16_build_va_list if it does update |
4b58290f | 1216 | the word count. */ |
5ab9749e | 1217 | |
bf425ddd | 1218 | static void |
6930c98c RS |
1219 | xstormy16_function_arg_advance (cumulative_args_t cum_v, |
1220 | const function_arg_info &arg) | |
4b58290f | 1221 | { |
d5cc9181 JR |
1222 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
1223 | ||
4b58290f GK |
1224 | /* If an argument would otherwise be passed partially in registers, |
1225 | and partially on the stack, the whole of it is passed on the | |
1226 | stack. */ | |
bf425ddd | 1227 | if (*cum < NUM_ARGUMENT_REGISTERS |
6930c98c RS |
1228 | && (*cum + XSTORMY16_WORD_SIZE (arg.type, arg.mode) |
1229 | > NUM_ARGUMENT_REGISTERS)) | |
bf425ddd | 1230 | *cum = NUM_ARGUMENT_REGISTERS; |
5ab9749e | 1231 | |
6930c98c | 1232 | *cum += XSTORMY16_WORD_SIZE (arg.type, arg.mode); |
4b58290f GK |
1233 | } |
1234 | ||
bf425ddd | 1235 | static rtx |
6783fdb7 | 1236 | xstormy16_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) |
06d22853 | 1237 | { |
d5cc9181 JR |
1238 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
1239 | ||
6783fdb7 | 1240 | if (arg.end_marker_p ()) |
06d22853 | 1241 | return const0_rtx; |
0ffef200 | 1242 | if (targetm.calls.must_pass_in_stack (arg) |
6783fdb7 RS |
1243 | || (*cum + XSTORMY16_WORD_SIZE (arg.type, arg.mode) |
1244 | > NUM_ARGUMENT_REGISTERS)) | |
5ab9749e | 1245 | return NULL_RTX; |
6783fdb7 | 1246 | return gen_rtx_REG (arg.mode, *cum + FIRST_ARGUMENT_REGISTER); |
06d22853 DD |
1247 | } |
1248 | ||
4b58290f GK |
1249 | /* Build the va_list type. |
1250 | ||
1251 | For this chip, va_list is a record containing a counter and a pointer. | |
1252 | The counter is of type 'int' and indicates how many bytes | |
1253 | have been used to date. The pointer indicates the stack position | |
5ab9749e | 1254 | for arguments that have not been passed in registers. |
4b58290f GK |
1255 | To keep the layout nice, the pointer is first in the structure. */ |
1256 | ||
37cd4bca NC |
1257 | static tree |
1258 | xstormy16_build_builtin_va_list (void) | |
4b58290f GK |
1259 | { |
1260 | tree f_1, f_2, record, type_decl; | |
1261 | ||
f1e639b1 | 1262 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
4c4bde29 AH |
1263 | type_decl = build_decl (BUILTINS_LOCATION, |
1264 | TYPE_DECL, get_identifier ("__va_list_tag"), record); | |
4b58290f | 1265 | |
4c4bde29 AH |
1266 | f_1 = build_decl (BUILTINS_LOCATION, |
1267 | FIELD_DECL, get_identifier ("base"), | |
4b58290f | 1268 | ptr_type_node); |
4c4bde29 AH |
1269 | f_2 = build_decl (BUILTINS_LOCATION, |
1270 | FIELD_DECL, get_identifier ("count"), | |
4b58290f GK |
1271 | unsigned_type_node); |
1272 | ||
1273 | DECL_FIELD_CONTEXT (f_1) = record; | |
1274 | DECL_FIELD_CONTEXT (f_2) = record; | |
1275 | ||
0fd2eac2 | 1276 | TYPE_STUB_DECL (record) = type_decl; |
4b58290f GK |
1277 | TYPE_NAME (record) = type_decl; |
1278 | TYPE_FIELDS (record) = f_1; | |
910ad8de | 1279 | DECL_CHAIN (f_1) = f_2; |
4b58290f GK |
1280 | |
1281 | layout_type (record); | |
1282 | ||
1283 | return record; | |
1284 | } | |
1285 | ||
5e7a8ee0 | 1286 | /* Implement the stdarg/varargs va_start macro. STDARG_P is nonzero if this |
4b58290f GK |
1287 | is stdarg.h instead of varargs.h. VALIST is the tree of the va_list |
1288 | variable to initialize. NEXTARG is the machine independent notion of the | |
1289 | 'next' argument after the variable arguments. */ | |
5ab9749e | 1290 | |
d7bd8aeb | 1291 | static void |
51c16b7e | 1292 | xstormy16_expand_builtin_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) |
4b58290f GK |
1293 | { |
1294 | tree f_base, f_count; | |
1295 | tree base, count; | |
f84fe9b6 | 1296 | tree t,u; |
4b58290f | 1297 | |
c6243b4c | 1298 | if (xstormy16_interrupt_function_p ()) |
4b58290f | 1299 | error ("cannot use va_start in interrupt function"); |
5ab9749e | 1300 | |
4b58290f | 1301 | f_base = TYPE_FIELDS (va_list_type_node); |
910ad8de | 1302 | f_count = DECL_CHAIN (f_base); |
5ab9749e | 1303 | |
47a25a46 RG |
1304 | base = build3 (COMPONENT_REF, TREE_TYPE (f_base), valist, f_base, NULL_TREE); |
1305 | count = build3 (COMPONENT_REF, TREE_TYPE (f_count), valist, f_count, | |
1306 | NULL_TREE); | |
4b58290f GK |
1307 | |
1308 | t = make_tree (TREE_TYPE (base), virtual_incoming_args_rtx); | |
b72bbbcb | 1309 | u = build_int_cst (NULL_TREE, - INCOMING_FRAME_SP_OFFSET); |
f84fe9b6 | 1310 | u = fold_convert (TREE_TYPE (count), u); |
5d49b6a7 | 1311 | t = fold_build_pointer_plus (t, u); |
726a989a | 1312 | t = build2 (MODIFY_EXPR, TREE_TYPE (base), base, t); |
4b58290f GK |
1313 | TREE_SIDE_EFFECTS (t) = 1; |
1314 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
1315 | ||
5ab9749e | 1316 | t = build2 (MODIFY_EXPR, TREE_TYPE (count), count, |
47a25a46 | 1317 | build_int_cst (NULL_TREE, |
38173d38 | 1318 | crtl->args.info * UNITS_PER_WORD)); |
4b58290f GK |
1319 | TREE_SIDE_EFFECTS (t) = 1; |
1320 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
1321 | } | |
1322 | ||
1323 | /* Implement the stdarg/varargs va_arg macro. VALIST is the variable | |
cf4c092e CM |
1324 | of type va_list as a tree, TYPE is the type passed to va_arg. |
1325 | Note: This algorithm is documented in stormy-abi. */ | |
5ab9749e | 1326 | |
5d47df87 | 1327 | static tree |
726a989a RB |
1328 | xstormy16_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
1329 | gimple_seq *post_p ATTRIBUTE_UNUSED) | |
4b58290f GK |
1330 | { |
1331 | tree f_base, f_count; | |
1332 | tree base, count; | |
5d47df87 RH |
1333 | tree count_tmp, addr, t; |
1334 | tree lab_gotaddr, lab_fromstack; | |
06d22853 | 1335 | int size, size_of_reg_args, must_stack; |
5d47df87 RH |
1336 | tree size_tree; |
1337 | ||
4b58290f | 1338 | f_base = TYPE_FIELDS (va_list_type_node); |
910ad8de | 1339 | f_count = DECL_CHAIN (f_base); |
5ab9749e | 1340 | |
47a25a46 RG |
1341 | base = build3 (COMPONENT_REF, TREE_TYPE (f_base), valist, f_base, NULL_TREE); |
1342 | count = build3 (COMPONENT_REF, TREE_TYPE (f_count), valist, f_count, | |
1343 | NULL_TREE); | |
4b58290f | 1344 | |
4f53599c | 1345 | must_stack = must_pass_va_arg_in_stack (type); |
4b58290f | 1346 | size_tree = round_up (size_in_bytes (type), UNITS_PER_WORD); |
5d47df87 | 1347 | gimplify_expr (&size_tree, pre_p, NULL, is_gimple_val, fb_rvalue); |
5ab9749e | 1348 | |
cf4c092e | 1349 | size_of_reg_args = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD; |
4b58290f | 1350 | |
5d47df87 | 1351 | count_tmp = get_initialized_tmp_var (count, pre_p, NULL); |
4c4bde29 AH |
1352 | lab_gotaddr = create_artificial_label (UNKNOWN_LOCATION); |
1353 | lab_fromstack = create_artificial_label (UNKNOWN_LOCATION); | |
9b489f31 | 1354 | addr = create_tmp_var (ptr_type_node); |
cf4c092e | 1355 | |
06d22853 DD |
1356 | if (!must_stack) |
1357 | { | |
5d47df87 RH |
1358 | tree r; |
1359 | ||
1360 | t = fold_convert (TREE_TYPE (count), size_tree); | |
47a25a46 | 1361 | t = build2 (PLUS_EXPR, TREE_TYPE (count), count_tmp, t); |
5d47df87 | 1362 | r = fold_convert (TREE_TYPE (count), size_int (size_of_reg_args)); |
47a25a46 RG |
1363 | t = build2 (GT_EXPR, boolean_type_node, t, r); |
1364 | t = build3 (COND_EXPR, void_type_node, t, | |
1365 | build1 (GOTO_EXPR, void_type_node, lab_fromstack), | |
1366 | NULL_TREE); | |
5d47df87 | 1367 | gimplify_and_add (t, pre_p); |
f84fe9b6 | 1368 | |
5d49b6a7 | 1369 | t = fold_build_pointer_plus (base, count_tmp); |
726a989a | 1370 | gimplify_assign (addr, t, pre_p); |
5d47df87 | 1371 | |
47a25a46 | 1372 | t = build1 (GOTO_EXPR, void_type_node, lab_gotaddr); |
5d47df87 RH |
1373 | gimplify_and_add (t, pre_p); |
1374 | ||
47a25a46 | 1375 | t = build1 (LABEL_EXPR, void_type_node, lab_fromstack); |
5d47df87 | 1376 | gimplify_and_add (t, pre_p); |
06d22853 | 1377 | } |
5ab9749e | 1378 | |
4b58290f GK |
1379 | /* Arguments larger than a word might need to skip over some |
1380 | registers, since arguments are either passed entirely in | |
1381 | registers or entirely on the stack. */ | |
06d22853 DD |
1382 | size = PUSH_ROUNDING (int_size_in_bytes (type)); |
1383 | if (size > 2 || size < 0 || must_stack) | |
4b58290f | 1384 | { |
5d47df87 RH |
1385 | tree r, u; |
1386 | ||
1387 | r = size_int (NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD); | |
726a989a | 1388 | u = build2 (MODIFY_EXPR, TREE_TYPE (count_tmp), count_tmp, r); |
5d47df87 RH |
1389 | |
1390 | t = fold_convert (TREE_TYPE (count), r); | |
47a25a46 RG |
1391 | t = build2 (GE_EXPR, boolean_type_node, count_tmp, t); |
1392 | t = build3 (COND_EXPR, void_type_node, t, NULL_TREE, u); | |
5d47df87 | 1393 | gimplify_and_add (t, pre_p); |
4b58290f GK |
1394 | } |
1395 | ||
5d47df87 | 1396 | t = size_int (NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD |
b72bbbcb | 1397 | + INCOMING_FRAME_SP_OFFSET); |
5d47df87 | 1398 | t = fold_convert (TREE_TYPE (count), t); |
47a25a46 RG |
1399 | t = build2 (MINUS_EXPR, TREE_TYPE (count), count_tmp, t); |
1400 | t = build2 (PLUS_EXPR, TREE_TYPE (count), t, | |
1401 | fold_convert (TREE_TYPE (count), size_tree)); | |
f84fe9b6 NC |
1402 | t = fold_convert (TREE_TYPE (t), fold (t)); |
1403 | t = fold_build1 (NEGATE_EXPR, TREE_TYPE (t), t); | |
5d49b6a7 | 1404 | t = fold_build_pointer_plus (base, t); |
726a989a | 1405 | gimplify_assign (addr, t, pre_p); |
5d47df87 | 1406 | |
47a25a46 | 1407 | t = build1 (LABEL_EXPR, void_type_node, lab_gotaddr); |
5d47df87 | 1408 | gimplify_and_add (t, pre_p); |
4b58290f | 1409 | |
5d47df87 | 1410 | t = fold_convert (TREE_TYPE (count), size_tree); |
47a25a46 | 1411 | t = build2 (PLUS_EXPR, TREE_TYPE (count), count_tmp, t); |
726a989a | 1412 | gimplify_assign (count, t, pre_p); |
5ab9749e | 1413 | |
5d47df87 | 1414 | addr = fold_convert (build_pointer_type (type), addr); |
d6e9821f | 1415 | return build_va_arg_indirect_ref (addr); |
4b58290f GK |
1416 | } |
1417 | ||
fb8d0fac | 1418 | /* Worker function for TARGET_TRAMPOLINE_INIT. */ |
5ab9749e | 1419 | |
fb8d0fac RH |
1420 | static void |
1421 | xstormy16_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain) | |
4b58290f | 1422 | { |
4b58290f GK |
1423 | rtx temp = gen_reg_rtx (HImode); |
1424 | rtx reg_fnaddr = gen_reg_rtx (HImode); | |
fb8d0fac | 1425 | rtx reg_addr, reg_addr_mem; |
4b58290f | 1426 | |
fb8d0fac RH |
1427 | reg_addr = copy_to_reg (XEXP (m_tramp, 0)); |
1428 | reg_addr_mem = adjust_automodify_address (m_tramp, HImode, reg_addr, 0); | |
5ab9749e | 1429 | |
4b58290f GK |
1430 | emit_move_insn (temp, GEN_INT (0x3130 | STATIC_CHAIN_REGNUM)); |
1431 | emit_move_insn (reg_addr_mem, temp); | |
e2470e1b | 1432 | emit_insn (gen_addhi3 (reg_addr, reg_addr, const2_rtx)); |
fb8d0fac RH |
1433 | reg_addr_mem = adjust_automodify_address (reg_addr_mem, VOIDmode, NULL, 2); |
1434 | ||
4b58290f GK |
1435 | emit_move_insn (temp, static_chain); |
1436 | emit_move_insn (reg_addr_mem, temp); | |
e2470e1b | 1437 | emit_insn (gen_addhi3 (reg_addr, reg_addr, const2_rtx)); |
fb8d0fac RH |
1438 | reg_addr_mem = adjust_automodify_address (reg_addr_mem, VOIDmode, NULL, 2); |
1439 | ||
1440 | emit_move_insn (reg_fnaddr, XEXP (DECL_RTL (fndecl), 0)); | |
4b58290f GK |
1441 | emit_move_insn (temp, reg_fnaddr); |
1442 | emit_insn (gen_andhi3 (temp, temp, GEN_INT (0xFF))); | |
1443 | emit_insn (gen_iorhi3 (temp, temp, GEN_INT (0x0200))); | |
1444 | emit_move_insn (reg_addr_mem, temp); | |
e2470e1b | 1445 | emit_insn (gen_addhi3 (reg_addr, reg_addr, const2_rtx)); |
fb8d0fac RH |
1446 | reg_addr_mem = adjust_automodify_address (reg_addr_mem, VOIDmode, NULL, 2); |
1447 | ||
4b58290f GK |
1448 | emit_insn (gen_lshrhi3 (reg_fnaddr, reg_fnaddr, GEN_INT (8))); |
1449 | emit_move_insn (reg_addr_mem, reg_fnaddr); | |
1450 | } | |
1451 | ||
998871e9 | 1452 | /* Worker function for TARGET_FUNCTION_VALUE. */ |
bd5bd7ac | 1453 | |
998871e9 AS |
1454 | static rtx |
1455 | xstormy16_function_value (const_tree valtype, | |
1456 | const_tree func ATTRIBUTE_UNUSED, | |
1457 | bool outgoing ATTRIBUTE_UNUSED) | |
4b58290f | 1458 | { |
ef4bddc2 | 1459 | machine_mode mode; |
4b58290f GK |
1460 | mode = TYPE_MODE (valtype); |
1461 | PROMOTE_MODE (mode, 0, valtype); | |
1462 | return gen_rtx_REG (mode, RETURN_VALUE_REGNUM); | |
1463 | } | |
1464 | ||
998871e9 AS |
1465 | /* Worker function for TARGET_LIBCALL_VALUE. */ |
1466 | ||
1467 | static rtx | |
ef4bddc2 | 1468 | xstormy16_libcall_value (machine_mode mode, |
998871e9 AS |
1469 | const_rtx fun ATTRIBUTE_UNUSED) |
1470 | { | |
1471 | return gen_rtx_REG (mode, RETURN_VALUE_REGNUM); | |
1472 | } | |
1473 | ||
1474 | /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. */ | |
1475 | ||
1476 | static bool | |
1477 | xstormy16_function_value_regno_p (const unsigned int regno) | |
1478 | { | |
1479 | return (regno == RETURN_VALUE_REGNUM); | |
1480 | } | |
1481 | ||
52560c7b GK |
1482 | /* A C compound statement that outputs the assembler code for a thunk function, |
1483 | used to implement C++ virtual function calls with multiple inheritance. The | |
1484 | thunk acts as a wrapper around a virtual function, adjusting the implicit | |
1485 | object parameter before handing control off to the real function. | |
1486 | ||
1487 | First, emit code to add the integer DELTA to the location that contains the | |
1488 | incoming first argument. Assume that this argument contains a pointer, and | |
1489 | is the one used to pass the `this' pointer in C++. This is the incoming | |
1490 | argument *before* the function prologue, e.g. `%o0' on a sparc. The | |
1491 | addition must preserve the values of all other incoming arguments. | |
1492 | ||
1493 | After the addition, emit code to jump to FUNCTION, which is a | |
1494 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch | |
1495 | the return address. Hence returning from FUNCTION will return to whoever | |
1496 | called the current `thunk'. | |
1497 | ||
1498 | The effect must be as if @var{function} had been called directly | |
1499 | with the adjusted first argument. This macro is responsible for | |
1500 | emitting all of the code for a thunk function; | |
1501 | TARGET_ASM_FUNCTION_PROLOGUE and TARGET_ASM_FUNCTION_EPILOGUE are | |
1502 | not invoked. | |
1503 | ||
1504 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been | |
1505 | extracted from it.) It might possibly be useful on some targets, but | |
1506 | probably not. */ | |
1507 | ||
c590b625 | 1508 | static void |
51c16b7e SB |
1509 | xstormy16_asm_output_mi_thunk (FILE *file, |
1510 | tree thunk_fndecl ATTRIBUTE_UNUSED, | |
1511 | HOST_WIDE_INT delta, | |
1512 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
1513 | tree function) | |
52560c7b | 1514 | { |
f7430263 | 1515 | const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl)); |
52560c7b | 1516 | int regnum = FIRST_ARGUMENT_REGISTER; |
5ab9749e | 1517 | |
f7430263 | 1518 | assemble_start_function (thunk_fndecl, fnname); |
52560c7b | 1519 | /* There might be a hidden first argument for a returned structure. */ |
61f71b34 | 1520 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
52560c7b | 1521 | regnum += 1; |
5ab9749e | 1522 | |
eb0424da | 1523 | fprintf (file, "\tadd %s,#0x%x\n", reg_names[regnum], (int) delta & 0xFFFF); |
52560c7b GK |
1524 | fputs ("\tjmpf ", file); |
1525 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
1526 | putc ('\n', file); | |
f7430263 | 1527 | assemble_end_function (thunk_fndecl, fnname); |
52560c7b GK |
1528 | } |
1529 | ||
54e9a19d DD |
1530 | /* The purpose of this function is to override the default behavior of |
1531 | BSS objects. Normally, they go into .bss or .sbss via ".common" | |
1532 | directives, but we need to override that and put them in | |
1533 | .bss_below100. We can't just use a section override (like we do | |
1534 | for .data_below100), because that makes them initialized rather | |
1535 | than uninitialized. */ | |
5ab9749e | 1536 | |
54e9a19d DD |
1537 | void |
1538 | xstormy16_asm_output_aligned_common (FILE *stream, | |
2f806f3b | 1539 | tree decl, |
54e9a19d DD |
1540 | const char *name, |
1541 | int size, | |
1542 | int align, | |
1543 | int global) | |
1544 | { | |
038eab67 | 1545 | rtx mem = decl == NULL_TREE ? NULL_RTX : DECL_RTL (decl); |
2f806f3b | 1546 | rtx symbol; |
5ab9749e | 1547 | |
2f806f3b | 1548 | if (mem != NULL_RTX |
a21eaf5e | 1549 | && MEM_P (mem) |
2f806f3b NC |
1550 | && GET_CODE (symbol = XEXP (mem, 0)) == SYMBOL_REF |
1551 | && SYMBOL_REF_FLAGS (symbol) & SYMBOL_FLAG_XSTORMY16_BELOW100) | |
54e9a19d | 1552 | { |
2f806f3b NC |
1553 | const char *name2; |
1554 | int p2align = 0; | |
1555 | ||
d6b5193b | 1556 | switch_to_section (bss100_section); |
2f806f3b NC |
1557 | |
1558 | while (align > 8) | |
54e9a19d | 1559 | { |
2f806f3b NC |
1560 | align /= 2; |
1561 | p2align ++; | |
54e9a19d | 1562 | } |
54e9a19d | 1563 | |
2f806f3b NC |
1564 | name2 = default_strip_name_encoding (name); |
1565 | if (global) | |
1566 | fprintf (stream, "\t.globl\t%s\n", name2); | |
1567 | if (p2align) | |
1568 | fprintf (stream, "\t.p2align %d\n", p2align); | |
1569 | fprintf (stream, "\t.type\t%s, @object\n", name2); | |
1570 | fprintf (stream, "\t.size\t%s, %d\n", name2, size); | |
1571 | fprintf (stream, "%s:\n\t.space\t%d\n", name2, size); | |
1572 | return; | |
54e9a19d DD |
1573 | } |
1574 | ||
1575 | if (!global) | |
1576 | { | |
1577 | fprintf (stream, "\t.local\t"); | |
1578 | assemble_name (stream, name); | |
1579 | fprintf (stream, "\n"); | |
1580 | } | |
1581 | fprintf (stream, "\t.comm\t"); | |
1582 | assemble_name (stream, name); | |
43f51151 | 1583 | fprintf (stream, ",%u,%u\n", size, align / BITS_PER_UNIT); |
54e9a19d DD |
1584 | } |
1585 | ||
d6b5193b RS |
1586 | /* Implement TARGET_ASM_INIT_SECTIONS. */ |
1587 | ||
1588 | static void | |
1589 | xstormy16_asm_init_sections (void) | |
1590 | { | |
1591 | bss100_section | |
1592 | = get_unnamed_section (SECTION_WRITE | SECTION_BSS, | |
1593 | output_section_asm_op, | |
1594 | "\t.section \".bss_below100\",\"aw\",@nobits"); | |
1595 | } | |
1596 | ||
54e9a19d DD |
1597 | /* Mark symbols with the "below100" attribute so that we can use the |
1598 | special addressing modes for them. */ | |
1599 | ||
1600 | static void | |
2f806f3b | 1601 | xstormy16_encode_section_info (tree decl, rtx r, int first) |
54e9a19d | 1602 | { |
e5eb9a52 NC |
1603 | default_encode_section_info (decl, r, first); |
1604 | ||
2f806f3b | 1605 | if (TREE_CODE (decl) == VAR_DECL |
54e9a19d DD |
1606 | && (lookup_attribute ("below100", DECL_ATTRIBUTES (decl)) |
1607 | || lookup_attribute ("BELOW100", DECL_ATTRIBUTES (decl)))) | |
1608 | { | |
2f806f3b | 1609 | rtx symbol = XEXP (r, 0); |
5ab9749e | 1610 | |
2f806f3b NC |
1611 | gcc_assert (GET_CODE (symbol) == SYMBOL_REF); |
1612 | SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_XSTORMY16_BELOW100; | |
54e9a19d DD |
1613 | } |
1614 | } | |
1615 | ||
6208b55d | 1616 | #undef TARGET_ASM_CONSTRUCTOR |
5ab9749e | 1617 | #define TARGET_ASM_CONSTRUCTOR xstormy16_asm_out_constructor |
6208b55d | 1618 | #undef TARGET_ASM_DESTRUCTOR |
5ab9749e NC |
1619 | #define TARGET_ASM_DESTRUCTOR xstormy16_asm_out_destructor |
1620 | ||
1621 | /* Output constructors and destructors. Just like | |
1622 | default_named_section_asm_out_* but don't set the sections writable. */ | |
43898541 GK |
1623 | |
1624 | static void | |
51c16b7e | 1625 | xstormy16_asm_out_destructor (rtx symbol, int priority) |
43898541 GK |
1626 | { |
1627 | const char *section = ".dtors"; | |
42ee9611 | 1628 | char buf[18]; |
43898541 | 1629 | |
71cc389b | 1630 | /* ??? This only works reliably with the GNU linker. */ |
43898541 GK |
1631 | if (priority != DEFAULT_INIT_PRIORITY) |
1632 | { | |
1633 | sprintf (buf, ".dtors.%.5u", | |
1634 | /* Invert the numbering so the linker puts us in the proper | |
1635 | order; constructors are run from right to left, and the | |
1636 | linker sorts in increasing order. */ | |
1637 | MAX_INIT_PRIORITY - priority); | |
1638 | section = buf; | |
1639 | } | |
1640 | ||
d6b5193b | 1641 | switch_to_section (get_section (section, 0, NULL)); |
43898541 GK |
1642 | assemble_align (POINTER_SIZE); |
1643 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); | |
1644 | } | |
1645 | ||
1646 | static void | |
51c16b7e | 1647 | xstormy16_asm_out_constructor (rtx symbol, int priority) |
43898541 GK |
1648 | { |
1649 | const char *section = ".ctors"; | |
42ee9611 | 1650 | char buf[18]; |
43898541 | 1651 | |
71cc389b | 1652 | /* ??? This only works reliably with the GNU linker. */ |
43898541 GK |
1653 | if (priority != DEFAULT_INIT_PRIORITY) |
1654 | { | |
1655 | sprintf (buf, ".ctors.%.5u", | |
1656 | /* Invert the numbering so the linker puts us in the proper | |
1657 | order; constructors are run from right to left, and the | |
1658 | linker sorts in increasing order. */ | |
1659 | MAX_INIT_PRIORITY - priority); | |
1660 | section = buf; | |
1661 | } | |
1662 | ||
d6b5193b | 1663 | switch_to_section (get_section (section, 0, NULL)); |
43898541 GK |
1664 | assemble_align (POINTER_SIZE); |
1665 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); | |
1666 | } | |
4b58290f | 1667 | \f |
43070a6e | 1668 | /* Worker function for TARGET_PRINT_OPERAND_ADDRESS. |
5ab9749e | 1669 | |
43070a6e AS |
1670 | Print a memory address as an operand to reference that memory location. */ |
1671 | ||
1672 | static void | |
cc8ca59e JB |
1673 | xstormy16_print_operand_address (FILE *file, machine_mode /*mode*/, |
1674 | rtx address) | |
4b58290f GK |
1675 | { |
1676 | HOST_WIDE_INT offset; | |
1677 | int pre_dec, post_inc; | |
1678 | ||
1679 | /* There are a few easy cases. */ | |
a21eaf5e | 1680 | if (CONST_INT_P (address)) |
4b58290f GK |
1681 | { |
1682 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (address) & 0xFFFF); | |
1683 | return; | |
1684 | } | |
5ab9749e | 1685 | |
a21eaf5e | 1686 | if (CONSTANT_P (address) || LABEL_P (address)) |
4b58290f GK |
1687 | { |
1688 | output_addr_const (file, address); | |
1689 | return; | |
1690 | } | |
4b58290f | 1691 | |
5ab9749e NC |
1692 | /* Otherwise, it's hopefully something of the form |
1693 | (plus:HI (pre_dec:HI (reg:HI ...)) (const_int ...)). */ | |
4b58290f GK |
1694 | if (GET_CODE (address) == PLUS) |
1695 | { | |
a21eaf5e | 1696 | gcc_assert (CONST_INT_P (XEXP (address, 1))); |
4b58290f GK |
1697 | offset = INTVAL (XEXP (address, 1)); |
1698 | address = XEXP (address, 0); | |
1699 | } | |
1700 | else | |
1701 | offset = 0; | |
1702 | ||
1703 | pre_dec = (GET_CODE (address) == PRE_DEC); | |
1704 | post_inc = (GET_CODE (address) == POST_INC); | |
1705 | if (pre_dec || post_inc) | |
1706 | address = XEXP (address, 0); | |
5ab9749e | 1707 | |
a21eaf5e | 1708 | gcc_assert (REG_P (address)); |
4b58290f GK |
1709 | |
1710 | fputc ('(', file); | |
1711 | if (pre_dec) | |
1712 | fputs ("--", file); | |
1713 | fputs (reg_names [REGNO (address)], file); | |
1714 | if (post_inc) | |
1715 | fputs ("++", file); | |
1716 | if (offset != 0) | |
4a0a75dd | 1717 | fprintf (file, "," HOST_WIDE_INT_PRINT_DEC, offset); |
4b58290f GK |
1718 | fputc (')', file); |
1719 | } | |
1720 | ||
43070a6e | 1721 | /* Worker function for TARGET_PRINT_OPERAND. |
5ab9749e | 1722 | |
43070a6e AS |
1723 | Print an operand to an assembler instruction. */ |
1724 | ||
1725 | static void | |
51c16b7e | 1726 | xstormy16_print_operand (FILE *file, rtx x, int code) |
4b58290f GK |
1727 | { |
1728 | switch (code) | |
1729 | { | |
1730 | case 'B': | |
1731 | /* There is either one bit set, or one bit clear, in X. | |
1732 | Print it preceded by '#'. */ | |
1733 | { | |
54e9a19d | 1734 | static int bits_set[8] = { 0, 1, 1, 2, 1, 2, 2, 3 }; |
e9818db2 GK |
1735 | HOST_WIDE_INT xx = 1; |
1736 | HOST_WIDE_INT l; | |
4b58290f | 1737 | |
a21eaf5e | 1738 | if (CONST_INT_P (x)) |
4b58290f GK |
1739 | xx = INTVAL (x); |
1740 | else | |
9e637a26 | 1741 | output_operand_lossage ("'B' operand is not constant"); |
5ab9749e | 1742 | |
54e9a19d DD |
1743 | /* GCC sign-extends masks with the MSB set, so we have to |
1744 | detect all the cases that differ only in sign extension | |
1745 | beyond the bits we care about. Normally, the predicates | |
1746 | and constraints ensure that we have the right values. This | |
1747 | works correctly for valid masks. */ | |
1748 | if (bits_set[xx & 7] <= 1) | |
1749 | { | |
1750 | /* Remove sign extension bits. */ | |
1751 | if ((~xx & ~(HOST_WIDE_INT)0xff) == 0) | |
1752 | xx &= 0xff; | |
1753 | else if ((~xx & ~(HOST_WIDE_INT)0xffff) == 0) | |
1754 | xx &= 0xffff; | |
1755 | l = exact_log2 (xx); | |
1756 | } | |
1757 | else | |
1758 | { | |
1759 | /* Add sign extension bits. */ | |
1760 | if ((xx & ~(HOST_WIDE_INT)0xff) == 0) | |
1761 | xx |= ~(HOST_WIDE_INT)0xff; | |
1762 | else if ((xx & ~(HOST_WIDE_INT)0xffff) == 0) | |
1763 | xx |= ~(HOST_WIDE_INT)0xffff; | |
1764 | l = exact_log2 (~xx); | |
1765 | } | |
1766 | ||
4b58290f | 1767 | if (l == -1) |
9e637a26 | 1768 | output_operand_lossage ("'B' operand has multiple bits set"); |
5ab9749e | 1769 | |
4a0a75dd | 1770 | fprintf (file, IMMEDIATE_PREFIX HOST_WIDE_INT_PRINT_DEC, l); |
4b58290f GK |
1771 | return; |
1772 | } | |
1773 | ||
1774 | case 'C': | |
1775 | /* Print the symbol without a surrounding @fptr(). */ | |
1776 | if (GET_CODE (x) == SYMBOL_REF) | |
1777 | assemble_name (file, XSTR (x, 0)); | |
a21eaf5e | 1778 | else if (LABEL_P (x)) |
2f0b7af6 | 1779 | output_asm_label (x); |
4b58290f | 1780 | else |
cc8ca59e | 1781 | xstormy16_print_operand_address (file, VOIDmode, x); |
4b58290f GK |
1782 | return; |
1783 | ||
1784 | case 'o': | |
1785 | case 'O': | |
5ab9749e | 1786 | /* Print the immediate operand less one, preceded by '#'. |
4b58290f GK |
1787 | For 'O', negate it first. */ |
1788 | { | |
e9818db2 | 1789 | HOST_WIDE_INT xx = 0; |
5ab9749e | 1790 | |
a21eaf5e | 1791 | if (CONST_INT_P (x)) |
4b58290f GK |
1792 | xx = INTVAL (x); |
1793 | else | |
9e637a26 | 1794 | output_operand_lossage ("'o' operand is not constant"); |
5ab9749e | 1795 | |
4b58290f GK |
1796 | if (code == 'O') |
1797 | xx = -xx; | |
5ab9749e | 1798 | |
4a0a75dd | 1799 | fprintf (file, IMMEDIATE_PREFIX HOST_WIDE_INT_PRINT_DEC, xx - 1); |
4b58290f GK |
1800 | return; |
1801 | } | |
1802 | ||
54e9a19d DD |
1803 | case 'b': |
1804 | /* Print the shift mask for bp/bn. */ | |
1805 | { | |
1806 | HOST_WIDE_INT xx = 1; | |
1807 | HOST_WIDE_INT l; | |
1808 | ||
a21eaf5e | 1809 | if (CONST_INT_P (x)) |
54e9a19d DD |
1810 | xx = INTVAL (x); |
1811 | else | |
9e637a26 | 1812 | output_operand_lossage ("'B' operand is not constant"); |
5ab9749e | 1813 | |
54e9a19d | 1814 | l = 7 - xx; |
5ab9749e | 1815 | |
54e9a19d DD |
1816 | fputs (IMMEDIATE_PREFIX, file); |
1817 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, l); | |
1818 | return; | |
1819 | } | |
1820 | ||
4b58290f GK |
1821 | case 0: |
1822 | /* Handled below. */ | |
1823 | break; | |
5ab9749e | 1824 | |
4b58290f | 1825 | default: |
c6243b4c | 1826 | output_operand_lossage ("xstormy16_print_operand: unknown code"); |
4b58290f GK |
1827 | return; |
1828 | } | |
1829 | ||
1830 | switch (GET_CODE (x)) | |
1831 | { | |
1832 | case REG: | |
1833 | fputs (reg_names [REGNO (x)], file); | |
1834 | break; | |
1835 | ||
1836 | case MEM: | |
cc8ca59e | 1837 | xstormy16_print_operand_address (file, GET_MODE (x), XEXP (x, 0)); |
4b58290f GK |
1838 | break; |
1839 | ||
1840 | default: | |
1841 | /* Some kind of constant or label; an immediate operand, | |
1842 | so prefix it with '#' for the assembler. */ | |
1843 | fputs (IMMEDIATE_PREFIX, file); | |
1844 | output_addr_const (file, x); | |
1845 | break; | |
1846 | } | |
1847 | ||
1848 | return; | |
1849 | } | |
4b58290f GK |
1850 | \f |
1851 | /* Expander for the `casesi' pattern. | |
1852 | INDEX is the index of the switch statement. | |
1853 | LOWER_BOUND is a CONST_INT that is the value of INDEX corresponding | |
1854 | to the first table entry. | |
1855 | RANGE is the number of table entries. | |
1856 | TABLE is an ADDR_VEC that is the jump table. | |
1857 | DEFAULT_LABEL is the address to branch to if INDEX is outside the | |
5ab9749e | 1858 | range LOWER_BOUND to LOWER_BOUND + RANGE - 1. */ |
4b58290f | 1859 | |
5ab9749e | 1860 | void |
51c16b7e SB |
1861 | xstormy16_expand_casesi (rtx index, rtx lower_bound, rtx range, |
1862 | rtx table, rtx default_label) | |
4b58290f GK |
1863 | { |
1864 | HOST_WIDE_INT range_i = INTVAL (range); | |
1865 | rtx int_index; | |
1866 | ||
1867 | /* This code uses 'br', so it can deal only with tables of size up to | |
1868 | 8192 entries. */ | |
1869 | if (range_i >= 8192) | |
5ab9749e | 1870 | sorry ("switch statement of size %lu entries too large", |
4b58290f GK |
1871 | (unsigned long) range_i); |
1872 | ||
4192f0d2 | 1873 | index = expand_binop (SImode, sub_optab, index, lower_bound, NULL_RTX, 0, |
4b58290f GK |
1874 | OPTAB_LIB_WIDEN); |
1875 | emit_cmp_and_jump_insns (index, range, GTU, NULL_RTX, SImode, 1, | |
40c13662 | 1876 | default_label); |
4b58290f | 1877 | int_index = gen_lowpart_common (HImode, index); |
a556fd39 | 1878 | emit_insn (gen_ashlhi3 (int_index, int_index, const2_rtx)); |
4b58290f GK |
1879 | emit_jump_insn (gen_tablejump_pcrel (int_index, table)); |
1880 | } | |
1881 | ||
1882 | /* Output an ADDR_VEC. It is output as a sequence of 'jmpf' | |
1883 | instructions, without label or alignment or any other special | |
1884 | constructs. We know that the previous instruction will be the | |
1885 | `tablejump_pcrel' output above. | |
1886 | ||
1887 | TODO: it might be nice to output 'br' instructions if they could | |
1888 | all reach. */ | |
1889 | ||
1890 | void | |
51c16b7e | 1891 | xstormy16_output_addr_vec (FILE *file, rtx label ATTRIBUTE_UNUSED, rtx table) |
5ab9749e | 1892 | { |
4b58290f | 1893 | int vlen, idx; |
5ab9749e | 1894 | |
d6b5193b | 1895 | switch_to_section (current_function_section ()); |
4b58290f GK |
1896 | |
1897 | vlen = XVECLEN (table, 0); | |
1898 | for (idx = 0; idx < vlen; idx++) | |
1899 | { | |
1900 | fputs ("\tjmpf ", file); | |
2f0b7af6 | 1901 | output_asm_label (XEXP (XVECEXP (table, 0, idx), 0)); |
4b58290f GK |
1902 | fputc ('\n', file); |
1903 | } | |
1904 | } | |
4b58290f GK |
1905 | \f |
1906 | /* Expander for the `call' patterns. | |
a21eaf5e NC |
1907 | RETVAL is the RTL for the return register or NULL for void functions. |
1908 | DEST is the function to call, expressed as a MEM. | |
1909 | COUNTER is ignored. */ | |
4b58290f | 1910 | |
5ab9749e | 1911 | void |
51c16b7e | 1912 | xstormy16_expand_call (rtx retval, rtx dest, rtx counter) |
4b58290f GK |
1913 | { |
1914 | rtx call, temp; | |
ef4bddc2 | 1915 | machine_mode mode; |
4b58290f | 1916 | |
a21eaf5e | 1917 | gcc_assert (MEM_P (dest)); |
4b58290f GK |
1918 | dest = XEXP (dest, 0); |
1919 | ||
a21eaf5e | 1920 | if (! CONSTANT_P (dest) && ! REG_P (dest)) |
4b58290f | 1921 | dest = force_reg (Pmode, dest); |
5ab9749e | 1922 | |
4b58290f GK |
1923 | if (retval == NULL) |
1924 | mode = VOIDmode; | |
1925 | else | |
1926 | mode = GET_MODE (retval); | |
1927 | ||
1928 | call = gen_rtx_CALL (mode, gen_rtx_MEM (FUNCTION_MODE, dest), | |
1929 | counter); | |
1930 | if (retval) | |
f7df4a84 | 1931 | call = gen_rtx_SET (retval, call); |
5ab9749e | 1932 | |
4b58290f GK |
1933 | if (! CONSTANT_P (dest)) |
1934 | { | |
1935 | temp = gen_reg_rtx (HImode); | |
1936 | emit_move_insn (temp, const0_rtx); | |
1937 | } | |
1938 | else | |
1939 | temp = const0_rtx; | |
5ab9749e NC |
1940 | |
1941 | call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, | |
4b58290f GK |
1942 | gen_rtx_USE (VOIDmode, temp))); |
1943 | emit_call_insn (call); | |
1944 | } | |
1945 | \f | |
1946 | /* Expanders for multiword computational operations. */ | |
1947 | ||
1948 | /* Expander for arithmetic operations; emit insns to compute | |
1949 | ||
1950 | (set DEST (CODE:MODE SRC0 SRC1)) | |
5ab9749e | 1951 | |
d40ba0b6 NC |
1952 | When CODE is COMPARE, a branch template is generated |
1953 | (this saves duplicating code in xstormy16_split_cbranch). */ | |
4b58290f | 1954 | |
5ab9749e | 1955 | void |
ef4bddc2 | 1956 | xstormy16_expand_arith (machine_mode mode, enum rtx_code code, |
d40ba0b6 | 1957 | rtx dest, rtx src0, rtx src1) |
4b58290f GK |
1958 | { |
1959 | int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; | |
1960 | int i; | |
1961 | int firstloop = 1; | |
1962 | ||
1963 | if (code == NEG) | |
9be13211 | 1964 | emit_move_insn (src0, const0_rtx); |
5ab9749e | 1965 | |
4b58290f GK |
1966 | for (i = 0; i < num_words; i++) |
1967 | { | |
1968 | rtx w_src0, w_src1, w_dest; | |
1969 | rtx insn; | |
5ab9749e NC |
1970 | |
1971 | w_src0 = simplify_gen_subreg (word_mode, src0, mode, | |
9be13211 | 1972 | i * UNITS_PER_WORD); |
4b58290f GK |
1973 | w_src1 = simplify_gen_subreg (word_mode, src1, mode, i * UNITS_PER_WORD); |
1974 | w_dest = simplify_gen_subreg (word_mode, dest, mode, i * UNITS_PER_WORD); | |
1975 | ||
1976 | switch (code) | |
1977 | { | |
1978 | case PLUS: | |
1979 | if (firstloop | |
a21eaf5e NC |
1980 | && CONST_INT_P (w_src1) |
1981 | && INTVAL (w_src1) == 0) | |
4b58290f | 1982 | continue; |
5ab9749e | 1983 | |
4b58290f | 1984 | if (firstloop) |
d40ba0b6 | 1985 | insn = gen_addchi4 (w_dest, w_src0, w_src1); |
4b58290f | 1986 | else |
d40ba0b6 | 1987 | insn = gen_addchi5 (w_dest, w_src0, w_src1); |
4b58290f GK |
1988 | break; |
1989 | ||
1990 | case NEG: | |
1991 | case MINUS: | |
1992 | case COMPARE: | |
1993 | if (code == COMPARE && i == num_words - 1) | |
1994 | { | |
1995 | rtx branch, sub, clobber, sub_1; | |
5ab9749e NC |
1996 | |
1997 | sub_1 = gen_rtx_MINUS (HImode, w_src0, | |
b72bbbcb | 1998 | gen_rtx_ZERO_EXTEND (HImode, gen_rtx_REG (BImode, CARRY_REGNUM))); |
f7df4a84 | 1999 | sub = gen_rtx_SET (w_dest, |
4b58290f | 2000 | gen_rtx_MINUS (HImode, sub_1, w_src1)); |
b72bbbcb | 2001 | clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); |
f7df4a84 | 2002 | branch = gen_rtx_SET (pc_rtx, |
4b58290f GK |
2003 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
2004 | gen_rtx_EQ (HImode, | |
2005 | sub_1, | |
2006 | w_src1), | |
2007 | pc_rtx, | |
2008 | pc_rtx)); | |
2009 | insn = gen_rtx_PARALLEL (VOIDmode, | |
2010 | gen_rtvec (3, branch, sub, clobber)); | |
2011 | } | |
2012 | else if (firstloop | |
2013 | && code != COMPARE | |
a21eaf5e NC |
2014 | && CONST_INT_P (w_src1) |
2015 | && INTVAL (w_src1) == 0) | |
4b58290f GK |
2016 | continue; |
2017 | else if (firstloop) | |
d40ba0b6 | 2018 | insn = gen_subchi4 (w_dest, w_src0, w_src1); |
4b58290f | 2019 | else |
d40ba0b6 | 2020 | insn = gen_subchi5 (w_dest, w_src0, w_src1); |
4b58290f GK |
2021 | break; |
2022 | ||
2023 | case IOR: | |
2024 | case XOR: | |
2025 | case AND: | |
a21eaf5e | 2026 | if (CONST_INT_P (w_src1) |
4b58290f GK |
2027 | && INTVAL (w_src1) == -(code == AND)) |
2028 | continue; | |
5ab9749e | 2029 | |
f7df4a84 RS |
2030 | insn = gen_rtx_SET (w_dest, gen_rtx_fmt_ee (code, mode, |
2031 | w_src0, w_src1)); | |
4b58290f GK |
2032 | break; |
2033 | ||
2034 | case NOT: | |
f7df4a84 | 2035 | insn = gen_rtx_SET (w_dest, gen_rtx_NOT (mode, w_src0)); |
4b58290f GK |
2036 | break; |
2037 | ||
2038 | default: | |
4718bfd8 | 2039 | gcc_unreachable (); |
4b58290f | 2040 | } |
5ab9749e | 2041 | |
4b58290f GK |
2042 | firstloop = 0; |
2043 | emit (insn); | |
2044 | } | |
f3cd0185 DD |
2045 | |
2046 | /* If we emit nothing, try_split() will think we failed. So emit | |
2047 | something that does nothing and can be optimized away. */ | |
2048 | if (firstloop) | |
2049 | emit (gen_nop ()); | |
4b58290f GK |
2050 | } |
2051 | ||
4b58290f | 2052 | /* The shift operations are split at output time for constant values; |
5ab9749e | 2053 | variable-width shifts get handed off to a library routine. |
4b58290f GK |
2054 | |
2055 | Generate an output string to do (set X (CODE:MODE X SIZE_R)) | |
2056 | SIZE_R will be a CONST_INT, X will be a hard register. */ | |
2057 | ||
5ab9749e | 2058 | const char * |
ef4bddc2 | 2059 | xstormy16_output_shift (machine_mode mode, enum rtx_code code, |
51c16b7e | 2060 | rtx x, rtx size_r, rtx temp) |
4b58290f GK |
2061 | { |
2062 | HOST_WIDE_INT size; | |
2063 | const char *r0, *r1, *rt; | |
2064 | static char r[64]; | |
2065 | ||
a21eaf5e NC |
2066 | gcc_assert (CONST_INT_P (size_r) |
2067 | && REG_P (x) | |
2068 | && mode == SImode); | |
2069 | ||
4b58290f GK |
2070 | size = INTVAL (size_r) & (GET_MODE_BITSIZE (mode) - 1); |
2071 | ||
2072 | if (size == 0) | |
2073 | return ""; | |
2074 | ||
2075 | r0 = reg_names [REGNO (x)]; | |
2076 | r1 = reg_names [REGNO (x) + 1]; | |
4b58290f GK |
2077 | |
2078 | /* For shifts of size 1, we can use the rotate instructions. */ | |
2079 | if (size == 1) | |
2080 | { | |
2081 | switch (code) | |
2082 | { | |
2083 | case ASHIFT: | |
2084 | sprintf (r, "shl %s,#1 | rlc %s,#1", r0, r1); | |
2085 | break; | |
2086 | case ASHIFTRT: | |
2087 | sprintf (r, "asr %s,#1 | rrc %s,#1", r1, r0); | |
2088 | break; | |
2089 | case LSHIFTRT: | |
2090 | sprintf (r, "shr %s,#1 | rrc %s,#1", r1, r0); | |
2091 | break; | |
2092 | default: | |
4718bfd8 | 2093 | gcc_unreachable (); |
4b58290f GK |
2094 | } |
2095 | return r; | |
2096 | } | |
5ab9749e | 2097 | |
4b58290f GK |
2098 | /* For large shifts, there are easy special cases. */ |
2099 | if (size == 16) | |
2100 | { | |
2101 | switch (code) | |
2102 | { | |
2103 | case ASHIFT: | |
2104 | sprintf (r, "mov %s,%s | mov %s,#0", r1, r0, r0); | |
2105 | break; | |
2106 | case ASHIFTRT: | |
2107 | sprintf (r, "mov %s,%s | asr %s,#15", r0, r1, r1); | |
2108 | break; | |
2109 | case LSHIFTRT: | |
2110 | sprintf (r, "mov %s,%s | mov %s,#0", r0, r1, r1); | |
2111 | break; | |
2112 | default: | |
4718bfd8 | 2113 | gcc_unreachable (); |
4b58290f GK |
2114 | } |
2115 | return r; | |
2116 | } | |
2117 | if (size > 16) | |
2118 | { | |
2119 | switch (code) | |
2120 | { | |
2121 | case ASHIFT: | |
5ab9749e | 2122 | sprintf (r, "mov %s,%s | mov %s,#0 | shl %s,#%d", |
4b58290f GK |
2123 | r1, r0, r0, r1, (int) size - 16); |
2124 | break; | |
2125 | case ASHIFTRT: | |
5ab9749e | 2126 | sprintf (r, "mov %s,%s | asr %s,#15 | asr %s,#%d", |
4b58290f GK |
2127 | r0, r1, r1, r0, (int) size - 16); |
2128 | break; | |
2129 | case LSHIFTRT: | |
5ab9749e | 2130 | sprintf (r, "mov %s,%s | mov %s,#0 | shr %s,#%d", |
4b58290f GK |
2131 | r0, r1, r1, r0, (int) size - 16); |
2132 | break; | |
2133 | default: | |
4718bfd8 | 2134 | gcc_unreachable (); |
4b58290f GK |
2135 | } |
2136 | return r; | |
2137 | } | |
2138 | ||
2139 | /* For the rest, we have to do more work. In particular, we | |
2140 | need a temporary. */ | |
5766e0ef | 2141 | rt = reg_names [REGNO (temp)]; |
4b58290f GK |
2142 | switch (code) |
2143 | { | |
2144 | case ASHIFT: | |
5ab9749e NC |
2145 | sprintf (r, |
2146 | "mov %s,%s | shl %s,#%d | shl %s,#%d | shr %s,#%d | or %s,%s", | |
2147 | rt, r0, r0, (int) size, r1, (int) size, rt, (int) (16 - size), | |
4b58290f GK |
2148 | r1, rt); |
2149 | break; | |
2150 | case ASHIFTRT: | |
5ab9749e NC |
2151 | sprintf (r, |
2152 | "mov %s,%s | asr %s,#%d | shr %s,#%d | shl %s,#%d | or %s,%s", | |
2153 | rt, r1, r1, (int) size, r0, (int) size, rt, (int) (16 - size), | |
4b58290f GK |
2154 | r0, rt); |
2155 | break; | |
2156 | case LSHIFTRT: | |
5ab9749e NC |
2157 | sprintf (r, |
2158 | "mov %s,%s | shr %s,#%d | shr %s,#%d | shl %s,#%d | or %s,%s", | |
2159 | rt, r1, r1, (int) size, r0, (int) size, rt, (int) (16 - size), | |
4b58290f GK |
2160 | r0, rt); |
2161 | break; | |
2162 | default: | |
4718bfd8 | 2163 | gcc_unreachable (); |
4b58290f GK |
2164 | } |
2165 | return r; | |
2166 | } | |
2167 | \f | |
2168 | /* Attribute handling. */ | |
2169 | ||
2170 | /* Return nonzero if the function is an interrupt function. */ | |
5ab9749e | 2171 | |
4b58290f | 2172 | int |
51c16b7e | 2173 | xstormy16_interrupt_function_p (void) |
4b58290f GK |
2174 | { |
2175 | tree attributes; | |
5ab9749e | 2176 | |
4b58290f GK |
2177 | /* The dwarf2 mechanism asks for INCOMING_FRAME_SP_OFFSET before |
2178 | any functions are declared, which is demonstrably wrong, but | |
2179 | it is worked around here. FIXME. */ | |
2180 | if (!cfun) | |
2181 | return 0; | |
2182 | ||
2183 | attributes = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)); | |
2184 | return lookup_attribute ("interrupt", attributes) != NULL_TREE; | |
2185 | } | |
2186 | ||
5ab9749e NC |
2187 | #undef TARGET_ATTRIBUTE_TABLE |
2188 | #define TARGET_ATTRIBUTE_TABLE xstormy16_attribute_table | |
2189 | ||
51c16b7e SB |
2190 | static tree xstormy16_handle_interrupt_attribute |
2191 | (tree *, tree, tree, int, bool *); | |
54e9a19d DD |
2192 | static tree xstormy16_handle_below100_attribute |
2193 | (tree *, tree, tree, int, bool *); | |
51c16b7e | 2194 | |
c6243b4c | 2195 | static const struct attribute_spec xstormy16_attribute_table[] = |
91d231cb | 2196 | { |
4849deb1 JJ |
2197 | /* name, min_len, max_len, decl_req, type_req, fn_type_req, |
2198 | affects_type_identity, handler, exclude. */ | |
2199 | { "interrupt", 0, 0, false, true, true, false, | |
2200 | xstormy16_handle_interrupt_attribute, NULL }, | |
2201 | { "BELOW100", 0, 0, false, false, false, false, | |
2202 | xstormy16_handle_below100_attribute, NULL }, | |
2203 | { "below100", 0, 0, false, false, false, false, | |
2204 | xstormy16_handle_below100_attribute, NULL }, | |
2205 | { NULL, 0, 0, false, false, false, false, NULL, NULL } | |
91d231cb JM |
2206 | }; |
2207 | ||
2208 | /* Handle an "interrupt" attribute; | |
2209 | arguments as in struct attribute_spec.handler. */ | |
5ab9749e | 2210 | |
91d231cb | 2211 | static tree |
51c16b7e SB |
2212 | xstormy16_handle_interrupt_attribute (tree *node, tree name, |
2213 | tree args ATTRIBUTE_UNUSED, | |
2214 | int flags ATTRIBUTE_UNUSED, | |
2215 | bool *no_add_attrs) | |
4b58290f | 2216 | { |
91d231cb JM |
2217 | if (TREE_CODE (*node) != FUNCTION_TYPE) |
2218 | { | |
29d08eba JM |
2219 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
2220 | name); | |
91d231cb JM |
2221 | *no_add_attrs = true; |
2222 | } | |
4b58290f | 2223 | |
91d231cb | 2224 | return NULL_TREE; |
4b58290f | 2225 | } |
54e9a19d DD |
2226 | |
2227 | /* Handle an "below" attribute; | |
2228 | arguments as in struct attribute_spec.handler. */ | |
5ab9749e | 2229 | |
54e9a19d DD |
2230 | static tree |
2231 | xstormy16_handle_below100_attribute (tree *node, | |
2232 | tree name ATTRIBUTE_UNUSED, | |
2233 | tree args ATTRIBUTE_UNUSED, | |
2234 | int flags ATTRIBUTE_UNUSED, | |
2235 | bool *no_add_attrs) | |
2236 | { | |
2237 | if (TREE_CODE (*node) != VAR_DECL | |
2238 | && TREE_CODE (*node) != POINTER_TYPE | |
2239 | && TREE_CODE (*node) != TYPE_DECL) | |
2240 | { | |
5c498b10 DD |
2241 | warning (OPT_Wattributes, |
2242 | "%<__BELOW100__%> attribute only applies to variables"); | |
54e9a19d DD |
2243 | *no_add_attrs = true; |
2244 | } | |
2245 | else if (args == NULL_TREE && TREE_CODE (*node) == VAR_DECL) | |
2246 | { | |
2247 | if (! (TREE_PUBLIC (*node) || TREE_STATIC (*node))) | |
2248 | { | |
5c498b10 | 2249 | warning (OPT_Wattributes, "__BELOW100__ attribute not allowed " |
ab532386 | 2250 | "with auto storage class"); |
54e9a19d DD |
2251 | *no_add_attrs = true; |
2252 | } | |
2253 | } | |
5ab9749e | 2254 | |
54e9a19d DD |
2255 | return NULL_TREE; |
2256 | } | |
3d4b192a | 2257 | \f |
5ab9749e NC |
2258 | #undef TARGET_INIT_BUILTINS |
2259 | #define TARGET_INIT_BUILTINS xstormy16_init_builtins | |
2260 | #undef TARGET_EXPAND_BUILTIN | |
2261 | #define TARGET_EXPAND_BUILTIN xstormy16_expand_builtin | |
2262 | ||
2263 | static struct | |
2264 | { | |
2265 | const char * name; | |
2266 | int md_code; | |
2267 | const char * arg_ops; /* 0..9, t for temp register, r for return value. */ | |
2268 | const char * arg_types; /* s=short,l=long, upper case for unsigned. */ | |
2269 | } | |
2270 | s16builtins[] = | |
2271 | { | |
3d4b192a DD |
2272 | { "__sdivlh", CODE_FOR_sdivlh, "rt01", "sls" }, |
2273 | { "__smodlh", CODE_FOR_sdivlh, "tr01", "sls" }, | |
2274 | { "__udivlh", CODE_FOR_udivlh, "rt01", "SLS" }, | |
2275 | { "__umodlh", CODE_FOR_udivlh, "tr01", "SLS" }, | |
5ab9749e | 2276 | { NULL, 0, NULL, NULL } |
3d4b192a DD |
2277 | }; |
2278 | ||
2279 | static void | |
51c16b7e | 2280 | xstormy16_init_builtins (void) |
3d4b192a | 2281 | { |
2c67cf6e NF |
2282 | tree args[2], ret_type, arg = NULL_TREE, ftype; |
2283 | int i, a, n_args; | |
3d4b192a DD |
2284 | |
2285 | ret_type = void_type_node; | |
2286 | ||
5ab9749e | 2287 | for (i = 0; s16builtins[i].name; i++) |
3d4b192a | 2288 | { |
2c67cf6e NF |
2289 | n_args = strlen (s16builtins[i].arg_types) - 1; |
2290 | ||
2291 | gcc_assert (n_args <= (int) ARRAY_SIZE (args)); | |
2292 | ||
15f072f9 | 2293 | for (a = n_args - 1; a >= 0; a--) |
2c67cf6e NF |
2294 | args[a] = NULL_TREE; |
2295 | ||
2296 | for (a = n_args; a >= 0; a--) | |
3d4b192a DD |
2297 | { |
2298 | switch (s16builtins[i].arg_types[a]) | |
2299 | { | |
2300 | case 's': arg = short_integer_type_node; break; | |
2301 | case 'S': arg = short_unsigned_type_node; break; | |
2302 | case 'l': arg = long_integer_type_node; break; | |
2303 | case 'L': arg = long_unsigned_type_node; break; | |
4718bfd8 | 2304 | default: gcc_unreachable (); |
3d4b192a DD |
2305 | } |
2306 | if (a == 0) | |
2307 | ret_type = arg; | |
2308 | else | |
2c67cf6e | 2309 | args[a-1] = arg; |
3d4b192a | 2310 | } |
15f072f9 | 2311 | ftype = build_function_type_list (ret_type, args[0], args[1], NULL_TREE); |
2c67cf6e | 2312 | add_builtin_function (s16builtins[i].name, ftype, |
15f072f9 | 2313 | i, BUILT_IN_MD, NULL, NULL_TREE); |
3d4b192a DD |
2314 | } |
2315 | } | |
2316 | ||
2317 | static rtx | |
f84fe9b6 NC |
2318 | xstormy16_expand_builtin (tree exp, rtx target, |
2319 | rtx subtarget ATTRIBUTE_UNUSED, | |
ef4bddc2 | 2320 | machine_mode mode ATTRIBUTE_UNUSED, |
f84fe9b6 | 2321 | int ignore ATTRIBUTE_UNUSED) |
3d4b192a DD |
2322 | { |
2323 | rtx op[10], args[10], pat, copyto[10], retval = 0; | |
2324 | tree fndecl, argtree; | |
2325 | int i, a, o, code; | |
2326 | ||
2327 | fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
2328 | argtree = TREE_OPERAND (exp, 1); | |
4d732405 | 2329 | i = DECL_MD_FUNCTION_CODE (fndecl); |
3d4b192a DD |
2330 | code = s16builtins[i].md_code; |
2331 | ||
2332 | for (a = 0; a < 10 && argtree; a++) | |
2333 | { | |
f1cb6795 | 2334 | args[a] = expand_normal (TREE_VALUE (argtree)); |
3d4b192a DD |
2335 | argtree = TREE_CHAIN (argtree); |
2336 | } | |
2337 | ||
2338 | for (o = 0; s16builtins[i].arg_ops[o]; o++) | |
2339 | { | |
2340 | char ao = s16builtins[i].arg_ops[o]; | |
2341 | char c = insn_data[code].operand[o].constraint[0]; | |
ef4bddc2 | 2342 | machine_mode omode; |
3d4b192a DD |
2343 | |
2344 | copyto[o] = 0; | |
2345 | ||
ef4bddc2 | 2346 | omode = (machine_mode) insn_data[code].operand[o].mode; |
3d4b192a DD |
2347 | if (ao == 'r') |
2348 | op[o] = target ? target : gen_reg_rtx (omode); | |
2349 | else if (ao == 't') | |
2350 | op[o] = gen_reg_rtx (omode); | |
2351 | else | |
2352 | op[o] = args[(int) hex_value (ao)]; | |
2353 | ||
2354 | if (! (*insn_data[code].operand[o].predicate) (op[o], GET_MODE (op[o]))) | |
2355 | { | |
2356 | if (c == '+' || c == '=') | |
2357 | { | |
2358 | copyto[o] = op[o]; | |
2359 | op[o] = gen_reg_rtx (omode); | |
2360 | } | |
2361 | else | |
2362 | op[o] = copy_to_mode_reg (omode, op[o]); | |
2363 | } | |
2364 | ||
2365 | if (ao == 'r') | |
2366 | retval = op[o]; | |
2367 | } | |
2368 | ||
2369 | pat = GEN_FCN (code) (op[0], op[1], op[2], op[3], op[4], | |
2370 | op[5], op[6], op[7], op[8], op[9]); | |
2371 | emit_insn (pat); | |
2372 | ||
2373 | for (o = 0; s16builtins[i].arg_ops[o]; o++) | |
2374 | if (copyto[o]) | |
2375 | { | |
2376 | emit_move_insn (copyto[o], op[o]); | |
2377 | if (op[o] == retval) | |
2378 | retval = copyto[o]; | |
2379 | } | |
2380 | ||
2381 | return retval; | |
2382 | } | |
54e9a19d | 2383 | \f |
54e9a19d DD |
2384 | /* Look for combinations of insns that can be converted to BN or BP |
2385 | opcodes. This is, unfortunately, too complex to do with MD | |
2386 | patterns. */ | |
5ab9749e | 2387 | |
54e9a19d | 2388 | static void |
b32d5189 | 2389 | combine_bnp (rtx_insn *insn) |
54e9a19d | 2390 | { |
f99652b5 NC |
2391 | int insn_code, regno, need_extend; |
2392 | unsigned int mask; | |
647d790d DM |
2393 | rtx cond, reg, qireg, mem; |
2394 | rtx_insn *and_insn, *load; | |
ef4bddc2 RS |
2395 | machine_mode load_mode = QImode; |
2396 | machine_mode and_mode = QImode; | |
647d790d | 2397 | rtx_insn *shift = NULL; |
54e9a19d DD |
2398 | |
2399 | insn_code = recog_memoized (insn); | |
2400 | if (insn_code != CODE_FOR_cbranchhi | |
2401 | && insn_code != CODE_FOR_cbranchhi_neg) | |
2402 | return; | |
2403 | ||
2404 | cond = XVECEXP (PATTERN (insn), 0, 0); /* set */ | |
2405 | cond = XEXP (cond, 1); /* if */ | |
2406 | cond = XEXP (cond, 0); /* cond */ | |
2407 | switch (GET_CODE (cond)) | |
2408 | { | |
2409 | case NE: | |
2410 | case EQ: | |
2411 | need_extend = 0; | |
2412 | break; | |
2413 | case LT: | |
2414 | case GE: | |
2415 | need_extend = 1; | |
2416 | break; | |
2417 | default: | |
2418 | return; | |
2419 | } | |
2420 | ||
2421 | reg = XEXP (cond, 0); | |
a21eaf5e | 2422 | if (! REG_P (reg)) |
54e9a19d DD |
2423 | return; |
2424 | regno = REGNO (reg); | |
2425 | if (XEXP (cond, 1) != const0_rtx) | |
2426 | return; | |
2427 | if (! find_regno_note (insn, REG_DEAD, regno)) | |
2428 | return; | |
2429 | qireg = gen_rtx_REG (QImode, regno); | |
2430 | ||
2431 | if (need_extend) | |
2432 | { | |
569b7f6a | 2433 | /* LT and GE conditionals should have a sign extend before |
54e9a19d | 2434 | them. */ |
15f072f9 NC |
2435 | for (and_insn = prev_real_insn (insn); |
2436 | and_insn != NULL_RTX; | |
f1cb6795 | 2437 | and_insn = prev_real_insn (and_insn)) |
54e9a19d | 2438 | { |
f1cb6795 | 2439 | int and_code = recog_memoized (and_insn); |
f99652b5 | 2440 | |
54e9a19d | 2441 | if (and_code == CODE_FOR_extendqihi2 |
f1cb6795 JR |
2442 | && rtx_equal_p (SET_DEST (PATTERN (and_insn)), reg) |
2443 | && rtx_equal_p (XEXP (SET_SRC (PATTERN (and_insn)), 0), qireg)) | |
f99652b5 | 2444 | break; |
5ab9749e | 2445 | |
54e9a19d | 2446 | if (and_code == CODE_FOR_movhi_internal |
f1cb6795 | 2447 | && rtx_equal_p (SET_DEST (PATTERN (and_insn)), reg)) |
54e9a19d DD |
2448 | { |
2449 | /* This is for testing bit 15. */ | |
f1cb6795 | 2450 | and_insn = insn; |
54e9a19d DD |
2451 | break; |
2452 | } | |
2453 | ||
f1cb6795 | 2454 | if (reg_mentioned_p (reg, and_insn)) |
54e9a19d | 2455 | return; |
f99652b5 | 2456 | |
b64925dc | 2457 | if (! NOTE_P (and_insn) && ! NONJUMP_INSN_P (and_insn)) |
54e9a19d DD |
2458 | return; |
2459 | } | |
2460 | } | |
2461 | else | |
2462 | { | |
2463 | /* EQ and NE conditionals have an AND before them. */ | |
15f072f9 NC |
2464 | for (and_insn = prev_real_insn (insn); |
2465 | and_insn != NULL_RTX; | |
f1cb6795 | 2466 | and_insn = prev_real_insn (and_insn)) |
54e9a19d | 2467 | { |
f1cb6795 JR |
2468 | if (recog_memoized (and_insn) == CODE_FOR_andhi3 |
2469 | && rtx_equal_p (SET_DEST (PATTERN (and_insn)), reg) | |
2470 | && rtx_equal_p (XEXP (SET_SRC (PATTERN (and_insn)), 0), reg)) | |
f99652b5 | 2471 | break; |
5ab9749e | 2472 | |
f1cb6795 | 2473 | if (reg_mentioned_p (reg, and_insn)) |
54e9a19d | 2474 | return; |
f99652b5 | 2475 | |
b64925dc | 2476 | if (! NOTE_P (and_insn) && ! NONJUMP_INSN_P (and_insn)) |
54e9a19d DD |
2477 | return; |
2478 | } | |
f99652b5 | 2479 | |
f1cb6795 | 2480 | if (and_insn) |
f99652b5 | 2481 | { |
aabcd309 | 2482 | /* Some mis-optimizations by GCC can generate a RIGHT-SHIFT |
f99652b5 NC |
2483 | followed by an AND like this: |
2484 | ||
2485 | (parallel [(set (reg:HI r7) (lshiftrt:HI (reg:HI r7) (const_int 3))) | |
2486 | (clobber (reg:BI carry))] | |
2487 | ||
2488 | (set (reg:HI r7) (and:HI (reg:HI r7) (const_int 1))) | |
5ab9749e | 2489 | |
f99652b5 | 2490 | Attempt to detect this here. */ |
f1cb6795 JR |
2491 | for (shift = prev_real_insn (and_insn); shift; |
2492 | shift = prev_real_insn (shift)) | |
f99652b5 NC |
2493 | { |
2494 | if (recog_memoized (shift) == CODE_FOR_lshrhi3 | |
2495 | && rtx_equal_p (SET_DEST (XVECEXP (PATTERN (shift), 0, 0)), reg) | |
2496 | && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (shift), 0, 0)), 0), reg)) | |
2497 | break; | |
5ab9749e | 2498 | |
f99652b5 | 2499 | if (reg_mentioned_p (reg, shift) |
b64925dc | 2500 | || (! NOTE_P (shift) && ! NONJUMP_INSN_P (shift))) |
f99652b5 | 2501 | { |
647d790d | 2502 | shift = NULL; |
f99652b5 NC |
2503 | break; |
2504 | } | |
2505 | } | |
2506 | } | |
54e9a19d | 2507 | } |
15f072f9 NC |
2508 | |
2509 | if (and_insn == NULL_RTX) | |
54e9a19d DD |
2510 | return; |
2511 | ||
f1cb6795 | 2512 | for (load = shift ? prev_real_insn (shift) : prev_real_insn (and_insn); |
f99652b5 NC |
2513 | load; |
2514 | load = prev_real_insn (load)) | |
54e9a19d DD |
2515 | { |
2516 | int load_code = recog_memoized (load); | |
f99652b5 | 2517 | |
54e9a19d | 2518 | if (load_code == CODE_FOR_movhi_internal |
f99652b5 NC |
2519 | && rtx_equal_p (SET_DEST (PATTERN (load)), reg) |
2520 | && xstormy16_below100_operand (SET_SRC (PATTERN (load)), HImode) | |
2521 | && ! MEM_VOLATILE_P (SET_SRC (PATTERN (load)))) | |
54e9a19d DD |
2522 | { |
2523 | load_mode = HImode; | |
2524 | break; | |
2525 | } | |
2526 | ||
2527 | if (load_code == CODE_FOR_movqi_internal | |
f99652b5 NC |
2528 | && rtx_equal_p (SET_DEST (PATTERN (load)), qireg) |
2529 | && xstormy16_below100_operand (SET_SRC (PATTERN (load)), QImode)) | |
54e9a19d DD |
2530 | { |
2531 | load_mode = QImode; | |
2532 | break; | |
2533 | } | |
f99652b5 NC |
2534 | |
2535 | if (load_code == CODE_FOR_zero_extendqihi2 | |
2536 | && rtx_equal_p (SET_DEST (PATTERN (load)), reg) | |
2537 | && xstormy16_below100_operand (XEXP (SET_SRC (PATTERN (load)), 0), QImode)) | |
2538 | { | |
2539 | load_mode = QImode; | |
2540 | and_mode = HImode; | |
2541 | break; | |
2542 | } | |
2543 | ||
54e9a19d DD |
2544 | if (reg_mentioned_p (reg, load)) |
2545 | return; | |
f99652b5 | 2546 | |
b64925dc | 2547 | if (! NOTE_P (load) && ! NONJUMP_INSN_P (load)) |
54e9a19d DD |
2548 | return; |
2549 | } | |
2550 | if (!load) | |
2551 | return; | |
2552 | ||
f99652b5 NC |
2553 | mem = SET_SRC (PATTERN (load)); |
2554 | ||
2555 | if (need_extend) | |
54e9a19d | 2556 | { |
f99652b5 NC |
2557 | mask = (load_mode == HImode) ? 0x8000 : 0x80; |
2558 | ||
2559 | /* If the mem includes a zero-extend operation and we are | |
2560 | going to generate a sign-extend operation then move the | |
2561 | mem inside the zero-extend. */ | |
2562 | if (GET_CODE (mem) == ZERO_EXTEND) | |
2563 | mem = XEXP (mem, 0); | |
54e9a19d DD |
2564 | } |
2565 | else | |
f99652b5 | 2566 | { |
f1cb6795 JR |
2567 | if (!xstormy16_onebit_set_operand (XEXP (SET_SRC (PATTERN (and_insn)), 1), |
2568 | load_mode)) | |
f99652b5 NC |
2569 | return; |
2570 | ||
f1cb6795 | 2571 | mask = (int) INTVAL (XEXP (SET_SRC (PATTERN (and_insn)), 1)); |
f99652b5 NC |
2572 | |
2573 | if (shift) | |
2574 | mask <<= INTVAL (XEXP (SET_SRC (XVECEXP (PATTERN (shift), 0, 0)), 1)); | |
2575 | } | |
54e9a19d | 2576 | |
54e9a19d DD |
2577 | if (load_mode == HImode) |
2578 | { | |
2579 | rtx addr = XEXP (mem, 0); | |
f99652b5 | 2580 | |
54e9a19d DD |
2581 | if (! (mask & 0xff)) |
2582 | { | |
0a81f074 | 2583 | addr = plus_constant (Pmode, addr, 1); |
54e9a19d DD |
2584 | mask >>= 8; |
2585 | } | |
2586 | mem = gen_rtx_MEM (QImode, addr); | |
2587 | } | |
2588 | ||
2589 | if (need_extend) | |
2590 | XEXP (cond, 0) = gen_rtx_SIGN_EXTEND (HImode, mem); | |
2591 | else | |
f99652b5 NC |
2592 | XEXP (cond, 0) = gen_rtx_AND (and_mode, mem, GEN_INT (mask)); |
2593 | ||
54e9a19d DD |
2594 | INSN_CODE (insn) = -1; |
2595 | delete_insn (load); | |
f99652b5 | 2596 | |
f1cb6795 JR |
2597 | if (and_insn != insn) |
2598 | delete_insn (and_insn); | |
f99652b5 NC |
2599 | |
2600 | if (shift != NULL_RTX) | |
2601 | delete_insn (shift); | |
54e9a19d DD |
2602 | } |
2603 | ||
2604 | static void | |
2605 | xstormy16_reorg (void) | |
2606 | { | |
b32d5189 | 2607 | rtx_insn *insn; |
54e9a19d DD |
2608 | |
2609 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
2610 | { | |
2611 | if (! JUMP_P (insn)) | |
2612 | continue; | |
2613 | combine_bnp (insn); | |
2614 | } | |
2615 | } | |
7e43c821 | 2616 | \f |
78bc94a2 KH |
2617 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
2618 | ||
7e43c821 | 2619 | static bool |
586de218 | 2620 | xstormy16_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
7e43c821 | 2621 | { |
586de218 | 2622 | const HOST_WIDE_INT size = int_size_in_bytes (type); |
78bc94a2 | 2623 | return (size == -1 || size > UNITS_PER_WORD * NUM_ARGUMENT_REGISTERS); |
7e43c821 | 2624 | } |
f939c3e6 RS |
2625 | |
2626 | /* Implement TARGET_HARD_REGNO_MODE_OK. */ | |
2627 | ||
2628 | static bool | |
2629 | xstormy16_hard_regno_mode_ok (unsigned int regno, machine_mode mode) | |
2630 | { | |
2631 | return regno != 16 || mode == BImode; | |
2632 | } | |
99e1629f RS |
2633 | |
2634 | /* Implement TARGET_MODES_TIEABLE_P. */ | |
2635 | ||
2636 | static bool | |
2637 | xstormy16_modes_tieable_p (machine_mode mode1, machine_mode mode2) | |
2638 | { | |
2639 | return mode1 != BImode && mode2 != BImode; | |
2640 | } | |
7b4df2bf RS |
2641 | |
2642 | /* Implement PUSH_ROUNDING. */ | |
2643 | ||
2644 | poly_int64 | |
2645 | xstormy16_push_rounding (poly_int64 bytes) | |
2646 | { | |
2647 | return (bytes + 1) & ~1; | |
2648 | } | |
4b58290f | 2649 | \f |
5ab9749e | 2650 | #undef TARGET_ASM_ALIGNED_HI_OP |
301d03af | 2651 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" |
5ab9749e | 2652 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af | 2653 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" |
5ab9749e | 2654 | #undef TARGET_ENCODE_SECTION_INFO |
54e9a19d | 2655 | #define TARGET_ENCODE_SECTION_INFO xstormy16_encode_section_info |
301d03af | 2656 | |
5ab9749e | 2657 | /* Select_section doesn't handle .bss_below100. */ |
434aeebb RS |
2658 | #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS |
2659 | #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS false | |
2660 | ||
5ab9749e | 2661 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
c590b625 | 2662 | #define TARGET_ASM_OUTPUT_MI_THUNK xstormy16_asm_output_mi_thunk |
5ab9749e | 2663 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3961e8fe | 2664 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall |
c590b625 | 2665 | |
43070a6e AS |
2666 | #undef TARGET_PRINT_OPERAND |
2667 | #define TARGET_PRINT_OPERAND xstormy16_print_operand | |
2668 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
2669 | #define TARGET_PRINT_OPERAND_ADDRESS xstormy16_print_operand_address | |
2670 | ||
6b1ce545 AS |
2671 | #undef TARGET_MEMORY_MOVE_COST |
2672 | #define TARGET_MEMORY_MOVE_COST xstormy16_memory_move_cost | |
5ab9749e | 2673 | #undef TARGET_RTX_COSTS |
3c50106f | 2674 | #define TARGET_RTX_COSTS xstormy16_rtx_costs |
5ab9749e | 2675 | #undef TARGET_ADDRESS_COST |
dcefdf67 | 2676 | #define TARGET_ADDRESS_COST xstormy16_address_cost |
3c50106f | 2677 | |
5ab9749e | 2678 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
f2f61ee7 | 2679 | #define TARGET_BUILD_BUILTIN_VA_LIST xstormy16_build_builtin_va_list |
5ab9749e | 2680 | #undef TARGET_EXPAND_BUILTIN_VA_START |
d7bd8aeb | 2681 | #define TARGET_EXPAND_BUILTIN_VA_START xstormy16_expand_builtin_va_start |
5ab9749e | 2682 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
f84fe9b6 | 2683 | #define TARGET_GIMPLIFY_VA_ARG_EXPR xstormy16_gimplify_va_arg_expr |
37cd4bca | 2684 | |
cde0f3fd PB |
2685 | #undef TARGET_PROMOTE_FUNCTION_MODE |
2686 | #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote | |
5ab9749e | 2687 | #undef TARGET_PROMOTE_PROTOTYPES |
586de218 | 2688 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
7e43c821 | 2689 | |
bf425ddd NF |
2690 | #undef TARGET_FUNCTION_ARG |
2691 | #define TARGET_FUNCTION_ARG xstormy16_function_arg | |
2692 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
2693 | #define TARGET_FUNCTION_ARG_ADVANCE xstormy16_function_arg_advance | |
2694 | ||
5ab9749e | 2695 | #undef TARGET_RETURN_IN_MEMORY |
7e43c821 | 2696 | #define TARGET_RETURN_IN_MEMORY xstormy16_return_in_memory |
998871e9 AS |
2697 | #undef TARGET_FUNCTION_VALUE |
2698 | #define TARGET_FUNCTION_VALUE xstormy16_function_value | |
2699 | #undef TARGET_LIBCALL_VALUE | |
2700 | #define TARGET_LIBCALL_VALUE xstormy16_libcall_value | |
2701 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
2702 | #define TARGET_FUNCTION_VALUE_REGNO_P xstormy16_function_value_regno_p | |
7e43c821 | 2703 | |
5ab9749e | 2704 | #undef TARGET_MACHINE_DEPENDENT_REORG |
54e9a19d DD |
2705 | #define TARGET_MACHINE_DEPENDENT_REORG xstormy16_reorg |
2706 | ||
ef795fc2 AS |
2707 | #undef TARGET_PREFERRED_RELOAD_CLASS |
2708 | #define TARGET_PREFERRED_RELOAD_CLASS xstormy16_preferred_reload_class | |
2709 | #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS | |
2710 | #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS xstormy16_preferred_reload_class | |
2711 | ||
d81db636 SB |
2712 | #undef TARGET_LRA_P |
2713 | #define TARGET_LRA_P hook_bool_void_false | |
2714 | ||
c6c3dba9 PB |
2715 | #undef TARGET_LEGITIMATE_ADDRESS_P |
2716 | #define TARGET_LEGITIMATE_ADDRESS_P xstormy16_legitimate_address_p | |
192997cf AS |
2717 | #undef TARGET_MODE_DEPENDENT_ADDRESS_P |
2718 | #define TARGET_MODE_DEPENDENT_ADDRESS_P xstormy16_mode_dependent_address_p | |
c6c3dba9 | 2719 | |
7b5cbb57 AS |
2720 | #undef TARGET_CAN_ELIMINATE |
2721 | #define TARGET_CAN_ELIMINATE xstormy16_can_eliminate | |
2722 | ||
fb8d0fac RH |
2723 | #undef TARGET_TRAMPOLINE_INIT |
2724 | #define TARGET_TRAMPOLINE_INIT xstormy16_trampoline_init | |
2725 | ||
f939c3e6 RS |
2726 | #undef TARGET_HARD_REGNO_MODE_OK |
2727 | #define TARGET_HARD_REGNO_MODE_OK xstormy16_hard_regno_mode_ok | |
99e1629f RS |
2728 | #undef TARGET_MODES_TIEABLE_P |
2729 | #define TARGET_MODES_TIEABLE_P xstormy16_modes_tieable_p | |
f939c3e6 | 2730 | |
58e17cf8 RS |
2731 | #undef TARGET_CONSTANT_ALIGNMENT |
2732 | #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings | |
2733 | ||
01557bd4 NC |
2734 | #undef TARGET_HAVE_SPECULATION_SAFE_VALUE |
2735 | #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed | |
2736 | ||
4b58290f | 2737 | struct gcc_target targetm = TARGET_INITIALIZER; |
d6b5193b RS |
2738 | |
2739 | #include "gt-stormy16.h" |