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dddb37d8 | 1 | /* Xstormy16 target functions. |
3aea1f79 | 2 | Copyright (C) 1997-2014 Free Software Foundation, Inc. |
96fb1e39 | 3 | Contributed by Red Hat, Inc. |
4 | ||
3bdb7a0a | 5 | This file is part of GCC. |
96fb1e39 | 6 | |
3bdb7a0a | 7 | GCC is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
96fb1e39 | 11 | |
3bdb7a0a | 12 | GCC is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
96fb1e39 | 16 | |
3bdb7a0a | 17 | You should have received a copy of the GNU General Public License |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
96fb1e39 | 20 | |
21 | #include "config.h" | |
22 | #include "system.h" | |
805e22b2 | 23 | #include "coretypes.h" |
24 | #include "tm.h" | |
96fb1e39 | 25 | #include "rtl.h" |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
96fb1e39 | 28 | #include "insn-config.h" |
29 | #include "conditions.h" | |
30 | #include "insn-flags.h" | |
31 | #include "output.h" | |
32 | #include "insn-attr.h" | |
33 | #include "flags.h" | |
34 | #include "recog.h" | |
0b205f4c | 35 | #include "diagnostic-core.h" |
96fb1e39 | 36 | #include "obstack.h" |
37 | #include "tree.h" | |
9ed99284 | 38 | #include "stringpool.h" |
39 | #include "stor-layout.h" | |
40 | #include "varasm.h" | |
41 | #include "calls.h" | |
96fb1e39 | 42 | #include "expr.h" |
43 | #include "optabs.h" | |
96fb1e39 | 44 | #include "except.h" |
a3020f2f | 45 | #include "hashtab.h" |
46 | #include "hash-set.h" | |
47 | #include "vec.h" | |
48 | #include "machmode.h" | |
49 | #include "input.h" | |
96fb1e39 | 50 | #include "function.h" |
51 | #include "target.h" | |
52 | #include "target-def.h" | |
53 | #include "tm_p.h" | |
a1f71e15 | 54 | #include "langhooks.h" |
bc61cadb | 55 | #include "hash-table.h" |
bc61cadb | 56 | #include "ggc.h" |
57 | #include "basic-block.h" | |
58 | #include "tree-ssa-alias.h" | |
59 | #include "internal-fn.h" | |
60 | #include "gimple-fold.h" | |
61 | #include "tree-eh.h" | |
62 | #include "gimple-expr.h" | |
63 | #include "is-a.h" | |
e795d6e1 | 64 | #include "gimple.h" |
a8783bee | 65 | #include "gimplify.h" |
bcf954af | 66 | #include "df.h" |
f9fd3680 | 67 | #include "reload.h" |
f7715905 | 68 | #include "builtins.h" |
96fb1e39 | 69 | |
3aed9a8d | 70 | static rtx emit_addhi3_postreload (rtx, rtx, rtx); |
71 | static void xstormy16_asm_out_constructor (rtx, int); | |
72 | static void xstormy16_asm_out_destructor (rtx, int); | |
73 | static void xstormy16_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, | |
74 | HOST_WIDE_INT, tree); | |
96fb1e39 | 75 | |
3aed9a8d | 76 | static void xstormy16_init_builtins (void); |
77 | static rtx xstormy16_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
20d892d1 | 78 | static bool xstormy16_rtx_costs (rtx, int, int, int, int *, bool); |
d9c5e5f4 | 79 | static int xstormy16_address_cost (rtx, enum machine_mode, addr_space_t, bool); |
fb80456a | 80 | static bool xstormy16_return_in_memory (const_tree, const_tree); |
537da7d2 | 81 | |
2f14b1f9 | 82 | static GTY(()) section *bss100_section; |
83 | ||
fab7adbf | 84 | /* Compute a (partial) cost for rtx X. Return true if the complete |
85 | cost has been computed, and false if subexpressions should be | |
86 | scanned. In either case, *TOTAL contains the cost result. */ | |
87 | ||
88 | static bool | |
3aed9a8d | 89 | xstormy16_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, |
20d892d1 | 90 | int opno ATTRIBUTE_UNUSED, int *total, |
91 | bool speed ATTRIBUTE_UNUSED) | |
fab7adbf | 92 | { |
93 | switch (code) | |
94 | { | |
95 | case CONST_INT: | |
96 | if (INTVAL (x) < 16 && INTVAL (x) >= 0) | |
97 | *total = COSTS_N_INSNS (1) / 2; | |
98 | else if (INTVAL (x) < 256 && INTVAL (x) >= 0) | |
99 | *total = COSTS_N_INSNS (1); | |
100 | else | |
101 | *total = COSTS_N_INSNS (2); | |
102 | return true; | |
103 | ||
104 | case CONST_DOUBLE: | |
105 | case CONST: | |
106 | case SYMBOL_REF: | |
107 | case LABEL_REF: | |
3bdb7a0a | 108 | *total = COSTS_N_INSNS (2); |
fab7adbf | 109 | return true; |
110 | ||
111 | case MULT: | |
112 | *total = COSTS_N_INSNS (35 + 6); | |
113 | return true; | |
114 | case DIV: | |
115 | *total = COSTS_N_INSNS (51 - 6); | |
116 | return true; | |
117 | ||
118 | default: | |
119 | return false; | |
120 | } | |
121 | } | |
122 | ||
ec0457a8 | 123 | static int |
d9c5e5f4 | 124 | xstormy16_address_cost (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED, |
125 | addr_space_t as ATTRIBUTE_UNUSED, | |
126 | bool speed ATTRIBUTE_UNUSED) | |
ec0457a8 | 127 | { |
899fa8d2 | 128 | return (CONST_INT_P (x) ? 2 |
ec0457a8 | 129 | : GET_CODE (x) == PLUS ? 7 |
130 | : 5); | |
131 | } | |
fab7adbf | 132 | |
f9fd3680 | 133 | /* Worker function for TARGET_MEMORY_MOVE_COST. */ |
134 | ||
135 | static int | |
136 | xstormy16_memory_move_cost (enum machine_mode mode, reg_class_t rclass, | |
137 | bool in) | |
138 | { | |
139 | return (5 + memory_move_secondary_cost (mode, rclass, in)); | |
140 | } | |
141 | ||
96fb1e39 | 142 | /* Branches are handled as follows: |
143 | ||
144 | 1. HImode compare-and-branches. The machine supports these | |
145 | natively, so the appropriate pattern is emitted directly. | |
146 | ||
147 | 2. SImode EQ and NE. These are emitted as pairs of HImode | |
3bdb7a0a | 148 | compare-and-branches. |
96fb1e39 | 149 | |
150 | 3. SImode LT, GE, LTU and GEU. These are emitted as a sequence | |
151 | of a SImode subtract followed by a branch (not a compare-and-branch), | |
152 | like this: | |
153 | sub | |
154 | sbc | |
155 | blt | |
156 | ||
157 | 4. SImode GT, LE, GTU, LEU. These are emitted as a sequence like: | |
158 | sub | |
159 | sbc | |
160 | blt | |
161 | or | |
3bdb7a0a | 162 | bne. */ |
96fb1e39 | 163 | |
164 | /* Emit a branch of kind CODE to location LOC. */ | |
165 | ||
166 | void | |
74f4459c | 167 | xstormy16_emit_cbranch (enum rtx_code code, rtx op0, rtx op1, rtx loc) |
96fb1e39 | 168 | { |
96fb1e39 | 169 | rtx condition_rtx, loc_ref, branch, cy_clobber; |
170 | rtvec vec; | |
171 | enum machine_mode mode; | |
3bdb7a0a | 172 | |
96fb1e39 | 173 | mode = GET_MODE (op0); |
73dcc01f | 174 | gcc_assert (mode == HImode || mode == SImode); |
96fb1e39 | 175 | |
176 | if (mode == SImode | |
177 | && (code == GT || code == LE || code == GTU || code == LEU)) | |
178 | { | |
179 | int unsigned_p = (code == GTU || code == LEU); | |
180 | int gt_p = (code == GT || code == GTU); | |
7b7a8c50 | 181 | rtx lab = NULL_RTX; |
3bdb7a0a | 182 | |
96fb1e39 | 183 | if (gt_p) |
184 | lab = gen_label_rtx (); | |
74f4459c | 185 | xstormy16_emit_cbranch (unsigned_p ? LTU : LT, op0, op1, gt_p ? lab : loc); |
96fb1e39 | 186 | /* This should be generated as a comparison against the temporary |
187 | created by the previous insn, but reload can't handle that. */ | |
74f4459c | 188 | xstormy16_emit_cbranch (gt_p ? NE : EQ, op0, op1, loc); |
96fb1e39 | 189 | if (gt_p) |
190 | emit_label (lab); | |
191 | return; | |
192 | } | |
3bdb7a0a | 193 | else if (mode == SImode |
96fb1e39 | 194 | && (code == NE || code == EQ) |
195 | && op1 != const0_rtx) | |
196 | { | |
74f4459c | 197 | rtx op0_word, op1_word; |
7b7a8c50 | 198 | rtx lab = NULL_RTX; |
96fb1e39 | 199 | int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; |
200 | int i; | |
3bdb7a0a | 201 | |
96fb1e39 | 202 | if (code == EQ) |
203 | lab = gen_label_rtx (); | |
3bdb7a0a | 204 | |
96fb1e39 | 205 | for (i = 0; i < num_words - 1; i++) |
206 | { | |
74f4459c | 207 | op0_word = simplify_gen_subreg (word_mode, op0, mode, |
208 | i * UNITS_PER_WORD); | |
209 | op1_word = simplify_gen_subreg (word_mode, op1, mode, | |
210 | i * UNITS_PER_WORD); | |
211 | xstormy16_emit_cbranch (NE, op0_word, op1_word, code == EQ ? lab : loc); | |
96fb1e39 | 212 | } |
74f4459c | 213 | op0_word = simplify_gen_subreg (word_mode, op0, mode, |
214 | i * UNITS_PER_WORD); | |
215 | op1_word = simplify_gen_subreg (word_mode, op1, mode, | |
216 | i * UNITS_PER_WORD); | |
217 | xstormy16_emit_cbranch (code, op0_word, op1_word, loc); | |
96fb1e39 | 218 | |
219 | if (code == EQ) | |
220 | emit_label (lab); | |
221 | return; | |
222 | } | |
223 | ||
224 | /* We can't allow reload to try to generate any reload after a branch, | |
225 | so when some register must match we must make the temporary ourselves. */ | |
226 | if (mode != HImode) | |
227 | { | |
228 | rtx tmp; | |
229 | tmp = gen_reg_rtx (mode); | |
230 | emit_move_insn (tmp, op0); | |
231 | op0 = tmp; | |
232 | } | |
233 | ||
29bb088d | 234 | condition_rtx = gen_rtx_fmt_ee (code, mode, op0, op1); |
96fb1e39 | 235 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); |
236 | branch = gen_rtx_SET (VOIDmode, pc_rtx, | |
237 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
238 | loc_ref, pc_rtx)); | |
239 | ||
f6af892b | 240 | cy_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); |
96fb1e39 | 241 | |
242 | if (mode == HImode) | |
243 | vec = gen_rtvec (2, branch, cy_clobber); | |
244 | else if (code == NE || code == EQ) | |
245 | vec = gen_rtvec (2, branch, gen_rtx_CLOBBER (VOIDmode, op0)); | |
246 | else | |
247 | { | |
248 | rtx sub; | |
249 | #if 0 | |
250 | sub = gen_rtx_SET (VOIDmode, op0, gen_rtx_MINUS (SImode, op0, op1)); | |
251 | #else | |
252 | sub = gen_rtx_CLOBBER (SImode, op0); | |
253 | #endif | |
254 | vec = gen_rtvec (3, branch, sub, cy_clobber); | |
255 | } | |
256 | ||
257 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec)); | |
258 | } | |
259 | ||
260 | /* Take a SImode conditional branch, one of GT/LE/GTU/LEU, and split | |
261 | the arithmetic operation. Most of the work is done by | |
dddb37d8 | 262 | xstormy16_expand_arith. */ |
96fb1e39 | 263 | |
264 | void | |
3aed9a8d | 265 | xstormy16_split_cbranch (enum machine_mode mode, rtx label, rtx comparison, |
247d6784 | 266 | rtx dest) |
96fb1e39 | 267 | { |
268 | rtx op0 = XEXP (comparison, 0); | |
269 | rtx op1 = XEXP (comparison, 1); | |
91a55c11 | 270 | rtx_insn *seq, *last_insn; |
96fb1e39 | 271 | rtx compare; |
3bdb7a0a | 272 | |
96fb1e39 | 273 | start_sequence (); |
247d6784 | 274 | xstormy16_expand_arith (mode, COMPARE, dest, op0, op1); |
31d3e01c | 275 | seq = get_insns (); |
96fb1e39 | 276 | end_sequence (); |
31d3e01c | 277 | |
73dcc01f | 278 | gcc_assert (INSN_P (seq)); |
31d3e01c | 279 | |
280 | last_insn = seq; | |
281 | while (NEXT_INSN (last_insn) != NULL_RTX) | |
282 | last_insn = NEXT_INSN (last_insn); | |
283 | ||
284 | compare = SET_SRC (XVECEXP (PATTERN (last_insn), 0, 0)); | |
96fb1e39 | 285 | PUT_CODE (XEXP (compare, 0), GET_CODE (comparison)); |
286 | XEXP (compare, 1) = gen_rtx_LABEL_REF (VOIDmode, label); | |
287 | emit_insn (seq); | |
288 | } | |
289 | ||
290 | ||
291 | /* Return the string to output a conditional branch to LABEL, which is | |
292 | the operand number of the label. | |
293 | ||
294 | OP is the conditional expression, or NULL for branch-always. | |
295 | ||
808a491c | 296 | REVERSED is nonzero if we should reverse the sense of the comparison. |
96fb1e39 | 297 | |
298 | INSN is the insn. */ | |
299 | ||
300 | char * | |
d3ffa7b4 | 301 | xstormy16_output_cbranch_hi (rtx op, const char *label, int reversed, |
302 | rtx_insn *insn) | |
96fb1e39 | 303 | { |
304 | static char string[64]; | |
305 | int need_longbranch = (op != NULL_RTX | |
306 | ? get_attr_length (insn) == 8 | |
307 | : get_attr_length (insn) == 4); | |
308 | int really_reversed = reversed ^ need_longbranch; | |
309 | const char *ccode; | |
8deb3959 | 310 | const char *templ; |
96fb1e39 | 311 | const char *operands; |
312 | enum rtx_code code; | |
3bdb7a0a | 313 | |
96fb1e39 | 314 | if (! op) |
315 | { | |
316 | if (need_longbranch) | |
317 | ccode = "jmpf"; | |
318 | else | |
319 | ccode = "br"; | |
320 | sprintf (string, "%s %s", ccode, label); | |
321 | return string; | |
322 | } | |
323 | ||
324 | code = GET_CODE (op); | |
325 | ||
899fa8d2 | 326 | if (! REG_P (XEXP (op, 0))) |
96fb1e39 | 327 | { |
328 | code = swap_condition (code); | |
329 | operands = "%3,%2"; | |
330 | } | |
331 | else | |
332 | operands = "%2,%3"; | |
333 | ||
334 | /* Work out which way this really branches. */ | |
335 | if (really_reversed) | |
336 | code = reverse_condition (code); | |
337 | ||
338 | switch (code) | |
339 | { | |
340 | case EQ: ccode = "z"; break; | |
341 | case NE: ccode = "nz"; break; | |
342 | case GE: ccode = "ge"; break; | |
343 | case LT: ccode = "lt"; break; | |
344 | case GT: ccode = "gt"; break; | |
345 | case LE: ccode = "le"; break; | |
346 | case GEU: ccode = "nc"; break; | |
347 | case LTU: ccode = "c"; break; | |
348 | case GTU: ccode = "hi"; break; | |
349 | case LEU: ccode = "ls"; break; | |
3bdb7a0a | 350 | |
96fb1e39 | 351 | default: |
73dcc01f | 352 | gcc_unreachable (); |
96fb1e39 | 353 | } |
354 | ||
355 | if (need_longbranch) | |
8deb3959 | 356 | templ = "b%s %s,.+8 | jmpf %s"; |
96fb1e39 | 357 | else |
8deb3959 | 358 | templ = "b%s %s,%s"; |
359 | sprintf (string, templ, ccode, operands, label); | |
3bdb7a0a | 360 | |
96fb1e39 | 361 | return string; |
362 | } | |
363 | ||
364 | /* Return the string to output a conditional branch to LABEL, which is | |
365 | the operand number of the label, but suitable for the tail of a | |
366 | SImode branch. | |
367 | ||
368 | OP is the conditional expression (OP is never NULL_RTX). | |
369 | ||
808a491c | 370 | REVERSED is nonzero if we should reverse the sense of the comparison. |
96fb1e39 | 371 | |
372 | INSN is the insn. */ | |
373 | ||
374 | char * | |
d3ffa7b4 | 375 | xstormy16_output_cbranch_si (rtx op, const char *label, int reversed, |
376 | rtx_insn *insn) | |
96fb1e39 | 377 | { |
378 | static char string[64]; | |
379 | int need_longbranch = get_attr_length (insn) >= 8; | |
380 | int really_reversed = reversed ^ need_longbranch; | |
381 | const char *ccode; | |
8deb3959 | 382 | const char *templ; |
96fb1e39 | 383 | char prevop[16]; |
384 | enum rtx_code code; | |
3bdb7a0a | 385 | |
96fb1e39 | 386 | code = GET_CODE (op); |
387 | ||
388 | /* Work out which way this really branches. */ | |
389 | if (really_reversed) | |
390 | code = reverse_condition (code); | |
391 | ||
392 | switch (code) | |
393 | { | |
394 | case EQ: ccode = "z"; break; | |
395 | case NE: ccode = "nz"; break; | |
396 | case GE: ccode = "ge"; break; | |
397 | case LT: ccode = "lt"; break; | |
398 | case GEU: ccode = "nc"; break; | |
399 | case LTU: ccode = "c"; break; | |
400 | ||
401 | /* The missing codes above should never be generated. */ | |
402 | default: | |
73dcc01f | 403 | gcc_unreachable (); |
96fb1e39 | 404 | } |
405 | ||
406 | switch (code) | |
407 | { | |
408 | case EQ: case NE: | |
409 | { | |
410 | int regnum; | |
3bdb7a0a | 411 | |
899fa8d2 | 412 | gcc_assert (REG_P (XEXP (op, 0))); |
3bdb7a0a | 413 | |
96fb1e39 | 414 | regnum = REGNO (XEXP (op, 0)); |
415 | sprintf (prevop, "or %s,%s", reg_names[regnum], reg_names[regnum+1]); | |
416 | } | |
417 | break; | |
418 | ||
419 | case GE: case LT: case GEU: case LTU: | |
420 | strcpy (prevop, "sbc %2,%3"); | |
421 | break; | |
422 | ||
423 | default: | |
73dcc01f | 424 | gcc_unreachable (); |
96fb1e39 | 425 | } |
426 | ||
427 | if (need_longbranch) | |
8deb3959 | 428 | templ = "%s | b%s .+6 | jmpf %s"; |
96fb1e39 | 429 | else |
8deb3959 | 430 | templ = "%s | b%s %s"; |
431 | sprintf (string, templ, prevop, ccode, label); | |
3bdb7a0a | 432 | |
96fb1e39 | 433 | return string; |
434 | } | |
435 | \f | |
436 | /* Many machines have some registers that cannot be copied directly to or from | |
437 | memory or even from other types of registers. An example is the `MQ' | |
438 | register, which on most machines, can only be copied to or from general | |
439 | registers, but not memory. Some machines allow copying all registers to and | |
440 | from memory, but require a scratch register for stores to some memory | |
441 | locations (e.g., those with symbolic address on the RT, and those with | |
7800959d | 442 | certain symbolic address on the SPARC when compiling PIC). In some cases, |
96fb1e39 | 443 | both an intermediate and a scratch register are required. |
444 | ||
445 | You should define these macros to indicate to the reload phase that it may | |
446 | need to allocate at least one register for a reload in addition to the | |
447 | register to contain the data. Specifically, if copying X to a register | |
8deb3959 | 448 | RCLASS in MODE requires an intermediate register, you should define |
96fb1e39 | 449 | `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of |
450 | whose registers can be used as intermediate registers or scratch registers. | |
451 | ||
8deb3959 | 452 | If copying a register RCLASS in MODE to X requires an intermediate or scratch |
96fb1e39 | 453 | register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the |
454 | largest register class required. If the requirements for input and output | |
455 | reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used | |
456 | instead of defining both macros identically. | |
457 | ||
458 | The values returned by these macros are often `GENERAL_REGS'. Return | |
459 | `NO_REGS' if no spare register is needed; i.e., if X can be directly copied | |
8deb3959 | 460 | to or from a register of RCLASS in MODE without requiring a scratch register. |
96fb1e39 | 461 | Do not define this macro if it would always return `NO_REGS'. |
462 | ||
463 | If a scratch register is required (either with or without an intermediate | |
464 | register), you should define patterns for `reload_inM' or `reload_outM', as | |
465 | required.. These patterns, which will normally be implemented with a | |
466 | `define_expand', should be similar to the `movM' patterns, except that | |
467 | operand 2 is the scratch register. | |
468 | ||
469 | Define constraints for the reload register and scratch register that contain | |
470 | a single register class. If the original reload register (whose class is | |
8deb3959 | 471 | RCLASS) can meet the constraint given in the pattern, the value returned by |
96fb1e39 | 472 | these macros is used for the class of the scratch register. Otherwise, two |
473 | additional reload registers are required. Their classes are obtained from | |
474 | the constraints in the insn pattern. | |
475 | ||
476 | X might be a pseudo-register or a `subreg' of a pseudo-register, which could | |
477 | either be in a hard register or in memory. Use `true_regnum' to find out; | |
478 | it will return -1 if the pseudo is in memory and the hard register number if | |
479 | it is in a register. | |
480 | ||
481 | These macros should not be used in the case where a particular class of | |
482 | registers can only be copied to memory and not to another class of | |
483 | registers. In that case, secondary reload registers are not needed and | |
484 | would not be helpful. Instead, a stack location must be used to perform the | |
ebb11c7b | 485 | copy and the `movM' pattern should use memory as an intermediate storage. |
96fb1e39 | 486 | This case often occurs between floating-point and general registers. */ |
487 | ||
488 | enum reg_class | |
8deb3959 | 489 | xstormy16_secondary_reload_class (enum reg_class rclass, |
899fa8d2 | 490 | enum machine_mode mode ATTRIBUTE_UNUSED, |
3aed9a8d | 491 | rtx x) |
96fb1e39 | 492 | { |
493 | /* This chip has the interesting property that only the first eight | |
494 | registers can be moved to/from memory. */ | |
899fa8d2 | 495 | if ((MEM_P (x) |
496 | || ((GET_CODE (x) == SUBREG || REG_P (x)) | |
96fb1e39 | 497 | && (true_regnum (x) == -1 |
498 | || true_regnum (x) >= FIRST_PSEUDO_REGISTER))) | |
8deb3959 | 499 | && ! reg_class_subset_p (rclass, EIGHT_REGS)) |
96fb1e39 | 500 | return EIGHT_REGS; |
501 | ||
96fb1e39 | 502 | return NO_REGS; |
503 | } | |
504 | ||
8fe62af3 | 505 | /* Worker function for TARGET_PREFERRED_RELOAD_CLASS |
506 | and TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */ | |
507 | ||
508 | static reg_class_t | |
509 | xstormy16_preferred_reload_class (rtx x, reg_class_t rclass) | |
96fb1e39 | 510 | { |
899fa8d2 | 511 | if (rclass == GENERAL_REGS && MEM_P (x)) |
96fb1e39 | 512 | return EIGHT_REGS; |
513 | ||
8deb3959 | 514 | return rclass; |
96fb1e39 | 515 | } |
516 | ||
3c1df5aa | 517 | /* Predicate for symbols and addresses that reflect special 8-bit |
518 | addressing. */ | |
3bdb7a0a | 519 | |
3c1df5aa | 520 | int |
521 | xstormy16_below100_symbol (rtx x, | |
522 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
523 | { | |
524 | if (GET_CODE (x) == CONST) | |
525 | x = XEXP (x, 0); | |
899fa8d2 | 526 | if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) |
3c1df5aa | 527 | x = XEXP (x, 0); |
ab764c12 | 528 | |
3c1df5aa | 529 | if (GET_CODE (x) == SYMBOL_REF) |
ab764c12 | 530 | return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_XSTORMY16_BELOW100) != 0; |
531 | ||
899fa8d2 | 532 | if (CONST_INT_P (x)) |
3c1df5aa | 533 | { |
534 | HOST_WIDE_INT i = INTVAL (x); | |
899fa8d2 | 535 | |
3c1df5aa | 536 | if ((i >= 0x0000 && i <= 0x00ff) |
537 | || (i >= 0x7f00 && i <= 0x7fff)) | |
538 | return 1; | |
539 | } | |
540 | return 0; | |
541 | } | |
542 | ||
3c1df5aa | 543 | /* Likewise, but only for non-volatile MEMs, for patterns where the |
544 | MEM will get split into smaller sized accesses. */ | |
3bdb7a0a | 545 | |
3c1df5aa | 546 | int |
547 | xstormy16_splittable_below100_operand (rtx x, enum machine_mode mode) | |
548 | { | |
899fa8d2 | 549 | if (MEM_P (x) && MEM_VOLATILE_P (x)) |
3c1df5aa | 550 | return 0; |
551 | return xstormy16_below100_operand (x, mode); | |
552 | } | |
553 | ||
3c1df5aa | 554 | /* Expand an 8-bit IOR. This either detects the one case we can |
555 | actually do, or uses a 16-bit IOR. */ | |
3bdb7a0a | 556 | |
3c1df5aa | 557 | void |
558 | xstormy16_expand_iorqi3 (rtx *operands) | |
559 | { | |
560 | rtx in, out, outsub, val; | |
561 | ||
562 | out = operands[0]; | |
563 | in = operands[1]; | |
564 | val = operands[2]; | |
565 | ||
566 | if (xstormy16_onebit_set_operand (val, QImode)) | |
567 | { | |
568 | if (!xstormy16_below100_or_register (in, QImode)) | |
569 | in = copy_to_mode_reg (QImode, in); | |
570 | if (!xstormy16_below100_or_register (out, QImode)) | |
571 | out = gen_reg_rtx (QImode); | |
572 | emit_insn (gen_iorqi3_internal (out, in, val)); | |
573 | if (out != operands[0]) | |
574 | emit_move_insn (operands[0], out); | |
575 | return; | |
576 | } | |
577 | ||
899fa8d2 | 578 | if (! REG_P (in)) |
3c1df5aa | 579 | in = copy_to_mode_reg (QImode, in); |
899fa8d2 | 580 | |
581 | if (! REG_P (val) && ! CONST_INT_P (val)) | |
3c1df5aa | 582 | val = copy_to_mode_reg (QImode, val); |
899fa8d2 | 583 | |
584 | if (! REG_P (out)) | |
3c1df5aa | 585 | out = gen_reg_rtx (QImode); |
586 | ||
587 | in = simplify_gen_subreg (HImode, in, QImode, 0); | |
588 | outsub = simplify_gen_subreg (HImode, out, QImode, 0); | |
899fa8d2 | 589 | |
590 | if (! CONST_INT_P (val)) | |
3c1df5aa | 591 | val = simplify_gen_subreg (HImode, val, QImode, 0); |
592 | ||
593 | emit_insn (gen_iorhi3 (outsub, in, val)); | |
594 | ||
595 | if (out != operands[0]) | |
596 | emit_move_insn (operands[0], out); | |
597 | } | |
598 | ||
3bdb7a0a | 599 | /* Expand an 8-bit AND. This either detects the one case we can |
600 | actually do, or uses a 16-bit AND. */ | |
601 | ||
3c1df5aa | 602 | void |
603 | xstormy16_expand_andqi3 (rtx *operands) | |
604 | { | |
605 | rtx in, out, outsub, val; | |
606 | ||
607 | out = operands[0]; | |
608 | in = operands[1]; | |
609 | val = operands[2]; | |
610 | ||
611 | if (xstormy16_onebit_clr_operand (val, QImode)) | |
612 | { | |
613 | if (!xstormy16_below100_or_register (in, QImode)) | |
614 | in = copy_to_mode_reg (QImode, in); | |
615 | if (!xstormy16_below100_or_register (out, QImode)) | |
616 | out = gen_reg_rtx (QImode); | |
617 | emit_insn (gen_andqi3_internal (out, in, val)); | |
618 | if (out != operands[0]) | |
619 | emit_move_insn (operands[0], out); | |
620 | return; | |
621 | } | |
622 | ||
899fa8d2 | 623 | if (! REG_P (in)) |
3c1df5aa | 624 | in = copy_to_mode_reg (QImode, in); |
899fa8d2 | 625 | |
626 | if (! REG_P (val) && ! CONST_INT_P (val)) | |
3c1df5aa | 627 | val = copy_to_mode_reg (QImode, val); |
899fa8d2 | 628 | |
629 | if (! REG_P (out)) | |
3c1df5aa | 630 | out = gen_reg_rtx (QImode); |
631 | ||
632 | in = simplify_gen_subreg (HImode, in, QImode, 0); | |
633 | outsub = simplify_gen_subreg (HImode, out, QImode, 0); | |
899fa8d2 | 634 | |
635 | if (! CONST_INT_P (val)) | |
3c1df5aa | 636 | val = simplify_gen_subreg (HImode, val, QImode, 0); |
637 | ||
638 | emit_insn (gen_andhi3 (outsub, in, val)); | |
639 | ||
640 | if (out != operands[0]) | |
641 | emit_move_insn (operands[0], out); | |
642 | } | |
643 | ||
96fb1e39 | 644 | #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \ |
899fa8d2 | 645 | (CONST_INT_P (X) \ |
96fb1e39 | 646 | && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 2048) < 4096) |
647 | ||
648 | #define LEGITIMATE_ADDRESS_CONST_INT_P(X, OFFSET) \ | |
899fa8d2 | 649 | (CONST_INT_P (X) \ |
96fb1e39 | 650 | && INTVAL (X) + (OFFSET) >= 0 \ |
651 | && INTVAL (X) + (OFFSET) < 0x8000 \ | |
652 | && (INTVAL (X) + (OFFSET) < 0x100 || INTVAL (X) + (OFFSET) >= 0x7F00)) | |
653 | ||
ee34ed40 | 654 | bool |
3aed9a8d | 655 | xstormy16_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, |
fd50b071 | 656 | rtx x, bool strict) |
96fb1e39 | 657 | { |
658 | if (LEGITIMATE_ADDRESS_CONST_INT_P (x, 0)) | |
899fa8d2 | 659 | return true; |
96fb1e39 | 660 | |
661 | if (GET_CODE (x) == PLUS | |
662 | && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 0)) | |
a0ebe2ee | 663 | { |
664 | x = XEXP (x, 0); | |
665 | /* PR 31232: Do not allow INT+INT as an address. */ | |
899fa8d2 | 666 | if (CONST_INT_P (x)) |
667 | return false; | |
a0ebe2ee | 668 | } |
3bdb7a0a | 669 | |
899fa8d2 | 670 | if ((GET_CODE (x) == PRE_MODIFY && CONST_INT_P (XEXP (XEXP (x, 1), 1))) |
6a3c0fd8 | 671 | || GET_CODE (x) == POST_INC |
96fb1e39 | 672 | || GET_CODE (x) == PRE_DEC) |
673 | x = XEXP (x, 0); | |
3bdb7a0a | 674 | |
899fa8d2 | 675 | if (REG_P (x) |
676 | && REGNO_OK_FOR_BASE_P (REGNO (x)) | |
96fb1e39 | 677 | && (! strict || REGNO (x) < FIRST_PSEUDO_REGISTER)) |
899fa8d2 | 678 | return true; |
3c1df5aa | 679 | |
bcf954af | 680 | if (xstormy16_below100_symbol (x, mode)) |
899fa8d2 | 681 | return true; |
3bdb7a0a | 682 | |
899fa8d2 | 683 | return false; |
96fb1e39 | 684 | } |
685 | ||
e53c7df3 | 686 | /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. |
3bdb7a0a | 687 | |
96fb1e39 | 688 | On this chip, this is true if the address is valid with an offset |
689 | of 0 but not of 6, because in that case it cannot be used as an | |
690 | address for DImode or DFmode, or if the address is a post-increment | |
691 | or pre-decrement address. */ | |
3bdb7a0a | 692 | |
e53c7df3 | 693 | static bool |
4e27ffd0 | 694 | xstormy16_mode_dependent_address_p (const_rtx x, |
695 | addr_space_t as ATTRIBUTE_UNUSED) | |
96fb1e39 | 696 | { |
697 | if (LEGITIMATE_ADDRESS_CONST_INT_P (x, 0) | |
698 | && ! LEGITIMATE_ADDRESS_CONST_INT_P (x, 6)) | |
e53c7df3 | 699 | return true; |
3bdb7a0a | 700 | |
96fb1e39 | 701 | if (GET_CODE (x) == PLUS |
702 | && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 0) | |
703 | && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 6)) | |
e53c7df3 | 704 | return true; |
96fb1e39 | 705 | |
cad2a6b5 | 706 | /* Auto-increment addresses are now treated generically in recog.c. */ |
e53c7df3 | 707 | return false; |
96fb1e39 | 708 | } |
709 | ||
96fb1e39 | 710 | int |
3aed9a8d | 711 | short_memory_operand (rtx x, enum machine_mode mode) |
96fb1e39 | 712 | { |
713 | if (! memory_operand (x, mode)) | |
714 | return 0; | |
715 | return (GET_CODE (XEXP (x, 0)) != PLUS); | |
716 | } | |
717 | ||
1fc184ee | 718 | /* Splitter for the 'move' patterns, for modes not directly implemented |
96fb1e39 | 719 | by hardware. Emit insns to copy a value of mode MODE from SRC to |
720 | DEST. | |
721 | ||
3bdb7a0a | 722 | This function is only called when reload_completed. */ |
96fb1e39 | 723 | |
3bdb7a0a | 724 | void |
3aed9a8d | 725 | xstormy16_split_move (enum machine_mode mode, rtx dest, rtx src) |
96fb1e39 | 726 | { |
727 | int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; | |
728 | int direction, end, i; | |
729 | int src_modifies = 0; | |
730 | int dest_modifies = 0; | |
731 | int src_volatile = 0; | |
732 | int dest_volatile = 0; | |
733 | rtx mem_operand; | |
af12f29d | 734 | rtx auto_inc_reg_rtx = NULL_RTX; |
3bdb7a0a | 735 | |
96fb1e39 | 736 | /* Check initial conditions. */ |
73dcc01f | 737 | gcc_assert (reload_completed |
738 | && mode != QImode && mode != HImode | |
739 | && nonimmediate_operand (dest, mode) | |
740 | && general_operand (src, mode)); | |
96fb1e39 | 741 | |
742 | /* This case is not supported below, and shouldn't be generated. */ | |
899fa8d2 | 743 | gcc_assert (! MEM_P (dest) || ! MEM_P (src)); |
96fb1e39 | 744 | |
745 | /* This case is very very bad after reload, so trap it now. */ | |
73dcc01f | 746 | gcc_assert (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG); |
96fb1e39 | 747 | |
748 | /* The general idea is to copy by words, offsetting the source and | |
749 | destination. Normally the least-significant word will be copied | |
3bdb7a0a | 750 | first, but for pre-dec operations it's better to copy the |
96fb1e39 | 751 | most-significant word first. Only one operand can be a pre-dec |
3bdb7a0a | 752 | or post-inc operand. |
96fb1e39 | 753 | |
754 | It's also possible that the copy overlaps so that the direction | |
755 | must be reversed. */ | |
756 | direction = 1; | |
3bdb7a0a | 757 | |
899fa8d2 | 758 | if (MEM_P (dest)) |
96fb1e39 | 759 | { |
760 | mem_operand = XEXP (dest, 0); | |
761 | dest_modifies = side_effects_p (mem_operand); | |
af12f29d | 762 | if (auto_inc_p (mem_operand)) |
763 | auto_inc_reg_rtx = XEXP (mem_operand, 0); | |
96fb1e39 | 764 | dest_volatile = MEM_VOLATILE_P (dest); |
765 | if (dest_volatile) | |
766 | { | |
767 | dest = copy_rtx (dest); | |
768 | MEM_VOLATILE_P (dest) = 0; | |
769 | } | |
770 | } | |
899fa8d2 | 771 | else if (MEM_P (src)) |
96fb1e39 | 772 | { |
773 | mem_operand = XEXP (src, 0); | |
774 | src_modifies = side_effects_p (mem_operand); | |
af12f29d | 775 | if (auto_inc_p (mem_operand)) |
776 | auto_inc_reg_rtx = XEXP (mem_operand, 0); | |
96fb1e39 | 777 | src_volatile = MEM_VOLATILE_P (src); |
778 | if (src_volatile) | |
779 | { | |
780 | src = copy_rtx (src); | |
781 | MEM_VOLATILE_P (src) = 0; | |
782 | } | |
783 | } | |
784 | else | |
785 | mem_operand = NULL_RTX; | |
786 | ||
787 | if (mem_operand == NULL_RTX) | |
788 | { | |
899fa8d2 | 789 | if (REG_P (src) |
790 | && REG_P (dest) | |
96fb1e39 | 791 | && reg_overlap_mentioned_p (dest, src) |
792 | && REGNO (dest) > REGNO (src)) | |
793 | direction = -1; | |
794 | } | |
795 | else if (GET_CODE (mem_operand) == PRE_DEC | |
3bdb7a0a | 796 | || (GET_CODE (mem_operand) == PLUS |
96fb1e39 | 797 | && GET_CODE (XEXP (mem_operand, 0)) == PRE_DEC)) |
798 | direction = -1; | |
899fa8d2 | 799 | else if (MEM_P (src) && reg_overlap_mentioned_p (dest, src)) |
96fb1e39 | 800 | { |
801 | int regno; | |
3bdb7a0a | 802 | |
899fa8d2 | 803 | gcc_assert (REG_P (dest)); |
96fb1e39 | 804 | regno = REGNO (dest); |
3bdb7a0a | 805 | |
73dcc01f | 806 | gcc_assert (refers_to_regno_p (regno, regno + num_words, |
807 | mem_operand, 0)); | |
3bdb7a0a | 808 | |
96fb1e39 | 809 | if (refers_to_regno_p (regno, regno + 1, mem_operand, 0)) |
810 | direction = -1; | |
811 | else if (refers_to_regno_p (regno + num_words - 1, regno + num_words, | |
812 | mem_operand, 0)) | |
813 | direction = 1; | |
814 | else | |
815 | /* This means something like | |
816 | (set (reg:DI r0) (mem:DI (reg:HI r1))) | |
817 | which we'd need to support by doing the set of the second word | |
818 | last. */ | |
73dcc01f | 819 | gcc_unreachable (); |
96fb1e39 | 820 | } |
821 | ||
822 | end = direction < 0 ? -1 : num_words; | |
823 | for (i = direction < 0 ? num_words - 1 : 0; i != end; i += direction) | |
824 | { | |
af12f29d | 825 | rtx w_src, w_dest, insn; |
826 | ||
96fb1e39 | 827 | if (src_modifies) |
828 | w_src = gen_rtx_MEM (word_mode, mem_operand); | |
829 | else | |
830 | w_src = simplify_gen_subreg (word_mode, src, mode, i * UNITS_PER_WORD); | |
831 | if (src_volatile) | |
832 | MEM_VOLATILE_P (w_src) = 1; | |
833 | if (dest_modifies) | |
834 | w_dest = gen_rtx_MEM (word_mode, mem_operand); | |
835 | else | |
3bdb7a0a | 836 | w_dest = simplify_gen_subreg (word_mode, dest, mode, |
96fb1e39 | 837 | i * UNITS_PER_WORD); |
838 | if (dest_volatile) | |
839 | MEM_VOLATILE_P (w_dest) = 1; | |
3bdb7a0a | 840 | |
96fb1e39 | 841 | /* The simplify_subreg calls must always be able to simplify. */ |
73dcc01f | 842 | gcc_assert (GET_CODE (w_src) != SUBREG |
843 | && GET_CODE (w_dest) != SUBREG); | |
3bdb7a0a | 844 | |
af12f29d | 845 | insn = emit_insn (gen_rtx_SET (VOIDmode, w_dest, w_src)); |
846 | if (auto_inc_reg_rtx) | |
847 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC, | |
848 | auto_inc_reg_rtx, | |
849 | REG_NOTES (insn)); | |
96fb1e39 | 850 | } |
851 | } | |
852 | ||
853 | /* Expander for the 'move' patterns. Emit insns to copy a value of | |
854 | mode MODE from SRC to DEST. */ | |
855 | ||
3bdb7a0a | 856 | void |
3aed9a8d | 857 | xstormy16_expand_move (enum machine_mode mode, rtx dest, rtx src) |
96fb1e39 | 858 | { |
899fa8d2 | 859 | if (MEM_P (dest) && (GET_CODE (XEXP (dest, 0)) == PRE_MODIFY)) |
6a3c0fd8 | 860 | { |
861 | rtx pmv = XEXP (dest, 0); | |
862 | rtx dest_reg = XEXP (pmv, 0); | |
863 | rtx dest_mod = XEXP (pmv, 1); | |
864 | rtx set = gen_rtx_SET (Pmode, dest_reg, dest_mod); | |
f6af892b | 865 | rtx clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); |
3bdb7a0a | 866 | |
6a3c0fd8 | 867 | dest = gen_rtx_MEM (mode, dest_reg); |
868 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); | |
869 | } | |
899fa8d2 | 870 | else if (MEM_P (src) && (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)) |
6a3c0fd8 | 871 | { |
872 | rtx pmv = XEXP (src, 0); | |
873 | rtx src_reg = XEXP (pmv, 0); | |
874 | rtx src_mod = XEXP (pmv, 1); | |
875 | rtx set = gen_rtx_SET (Pmode, src_reg, src_mod); | |
f6af892b | 876 | rtx clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); |
3bdb7a0a | 877 | |
6a3c0fd8 | 878 | src = gen_rtx_MEM (mode, src_reg); |
879 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); | |
880 | } | |
3bdb7a0a | 881 | |
96fb1e39 | 882 | /* There are only limited immediate-to-memory move instructions. */ |
883 | if (! reload_in_progress | |
884 | && ! reload_completed | |
899fa8d2 | 885 | && MEM_P (dest) |
886 | && (! CONST_INT_P (XEXP (dest, 0)) | |
dddb37d8 | 887 | || ! xstormy16_legitimate_address_p (mode, XEXP (dest, 0), 0)) |
3c1df5aa | 888 | && ! xstormy16_below100_operand (dest, mode) |
899fa8d2 | 889 | && ! REG_P (src) |
96fb1e39 | 890 | && GET_CODE (src) != SUBREG) |
891 | src = copy_to_mode_reg (mode, src); | |
892 | ||
893 | /* Don't emit something we would immediately split. */ | |
894 | if (reload_completed | |
895 | && mode != HImode && mode != QImode) | |
896 | { | |
dddb37d8 | 897 | xstormy16_split_move (mode, dest, src); |
96fb1e39 | 898 | return; |
899 | } | |
3bdb7a0a | 900 | |
96fb1e39 | 901 | emit_insn (gen_rtx_SET (VOIDmode, dest, src)); |
902 | } | |
96fb1e39 | 903 | \f |
904 | /* Stack Layout: | |
905 | ||
906 | The stack is laid out as follows: | |
907 | ||
908 | SP-> | |
909 | FP-> Local variables | |
910 | Register save area (up to 4 words) | |
911 | Argument register save area for stdarg (NUM_ARGUMENT_REGISTERS words) | |
912 | ||
913 | AP-> Return address (two words) | |
914 | 9th procedure parameter word | |
915 | 10th procedure parameter word | |
916 | ... | |
917 | last procedure parameter word | |
918 | ||
919 | The frame pointer location is tuned to make it most likely that all | |
920 | parameters and local variables can be accessed using a load-indexed | |
921 | instruction. */ | |
922 | ||
923 | /* A structure to describe the layout. */ | |
dddb37d8 | 924 | struct xstormy16_stack_layout |
96fb1e39 | 925 | { |
926 | /* Size of the topmost three items on the stack. */ | |
927 | int locals_size; | |
928 | int register_save_size; | |
929 | int stdarg_save_size; | |
930 | /* Sum of the above items. */ | |
931 | int frame_size; | |
932 | /* Various offsets. */ | |
933 | int first_local_minus_ap; | |
934 | int sp_minus_fp; | |
935 | int fp_minus_ap; | |
936 | }; | |
937 | ||
938 | /* Does REGNO need to be saved? */ | |
939 | #define REG_NEEDS_SAVE(REGNUM, IFUN) \ | |
3072d30e | 940 | ((df_regs_ever_live_p (REGNUM) && ! call_used_regs[REGNUM]) \ |
96fb1e39 | 941 | || (IFUN && ! fixed_regs[REGNUM] && call_used_regs[REGNUM] \ |
247d6784 | 942 | && (REGNUM != CARRY_REGNUM) \ |
d5bf7b64 | 943 | && (df_regs_ever_live_p (REGNUM) || ! crtl->is_leaf))) |
96fb1e39 | 944 | |
945 | /* Compute the stack layout. */ | |
3bdb7a0a | 946 | |
947 | struct xstormy16_stack_layout | |
3aed9a8d | 948 | xstormy16_compute_stack_layout (void) |
96fb1e39 | 949 | { |
dddb37d8 | 950 | struct xstormy16_stack_layout layout; |
96fb1e39 | 951 | int regno; |
dddb37d8 | 952 | const int ifun = xstormy16_interrupt_function_p (); |
96fb1e39 | 953 | |
954 | layout.locals_size = get_frame_size (); | |
3bdb7a0a | 955 | |
96fb1e39 | 956 | layout.register_save_size = 0; |
957 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
958 | if (REG_NEEDS_SAVE (regno, ifun)) | |
959 | layout.register_save_size += UNITS_PER_WORD; | |
3bdb7a0a | 960 | |
18d50ae6 | 961 | if (cfun->stdarg) |
96fb1e39 | 962 | layout.stdarg_save_size = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD; |
963 | else | |
964 | layout.stdarg_save_size = 0; | |
3bdb7a0a | 965 | |
966 | layout.frame_size = (layout.locals_size | |
967 | + layout.register_save_size | |
96fb1e39 | 968 | + layout.stdarg_save_size); |
3bdb7a0a | 969 | |
abe32cce | 970 | if (crtl->args.size <= 2048 && crtl->args.size != -1) |
96fb1e39 | 971 | { |
3bdb7a0a | 972 | if (layout.frame_size - INCOMING_FRAME_SP_OFFSET |
abe32cce | 973 | + crtl->args.size <= 2048) |
f6af892b | 974 | layout.fp_minus_ap = layout.frame_size - INCOMING_FRAME_SP_OFFSET; |
96fb1e39 | 975 | else |
abe32cce | 976 | layout.fp_minus_ap = 2048 - crtl->args.size; |
96fb1e39 | 977 | } |
978 | else | |
3bdb7a0a | 979 | layout.fp_minus_ap = (layout.stdarg_save_size |
96fb1e39 | 980 | + layout.register_save_size |
f6af892b | 981 | - INCOMING_FRAME_SP_OFFSET); |
3bdb7a0a | 982 | layout.sp_minus_fp = (layout.frame_size - INCOMING_FRAME_SP_OFFSET |
96fb1e39 | 983 | - layout.fp_minus_ap); |
984 | layout.first_local_minus_ap = layout.sp_minus_fp - layout.locals_size; | |
985 | return layout; | |
986 | } | |
987 | ||
cd90919d | 988 | /* Worker function for TARGET_CAN_ELIMINATE. */ |
989 | ||
990 | static bool | |
991 | xstormy16_can_eliminate (const int from, const int to) | |
992 | { | |
993 | return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM | |
994 | ? ! frame_pointer_needed | |
995 | : true); | |
996 | } | |
997 | ||
96fb1e39 | 998 | /* Determine how all the special registers get eliminated. */ |
3bdb7a0a | 999 | |
96fb1e39 | 1000 | int |
3aed9a8d | 1001 | xstormy16_initial_elimination_offset (int from, int to) |
96fb1e39 | 1002 | { |
dddb37d8 | 1003 | struct xstormy16_stack_layout layout; |
96fb1e39 | 1004 | int result; |
3bdb7a0a | 1005 | |
dddb37d8 | 1006 | layout = xstormy16_compute_stack_layout (); |
96fb1e39 | 1007 | |
1008 | if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) | |
1009 | result = layout.sp_minus_fp - layout.locals_size; | |
1010 | else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
f6af892b | 1011 | result = - layout.locals_size; |
96fb1e39 | 1012 | else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) |
f6af892b | 1013 | result = - layout.fp_minus_ap; |
96fb1e39 | 1014 | else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
f6af892b | 1015 | result = - (layout.sp_minus_fp + layout.fp_minus_ap); |
96fb1e39 | 1016 | else |
73dcc01f | 1017 | gcc_unreachable (); |
96fb1e39 | 1018 | |
1019 | return result; | |
1020 | } | |
1021 | ||
1022 | static rtx | |
3aed9a8d | 1023 | emit_addhi3_postreload (rtx dest, rtx src0, rtx src1) |
96fb1e39 | 1024 | { |
1025 | rtx set, clobber, insn; | |
3bdb7a0a | 1026 | |
96fb1e39 | 1027 | set = gen_rtx_SET (VOIDmode, dest, gen_rtx_PLUS (HImode, src0, src1)); |
f6af892b | 1028 | clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); |
96fb1e39 | 1029 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); |
1030 | return insn; | |
1031 | } | |
1032 | ||
cfc9bfb9 | 1033 | /* Called after register allocation to add any instructions needed for |
1034 | the prologue. Using a prologue insn is favored compared to putting | |
1035 | all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro, | |
1036 | since it allows the scheduler to intermix instructions with the | |
1037 | saves of the caller saved registers. In some cases, it might be | |
1038 | necessary to emit a barrier instruction as the last insn to prevent | |
1039 | such scheduling. | |
96fb1e39 | 1040 | |
1041 | Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 | |
1042 | so that the debug info generation code can handle them properly. */ | |
3bdb7a0a | 1043 | |
96fb1e39 | 1044 | void |
3aed9a8d | 1045 | xstormy16_expand_prologue (void) |
96fb1e39 | 1046 | { |
dddb37d8 | 1047 | struct xstormy16_stack_layout layout; |
96fb1e39 | 1048 | int regno; |
1049 | rtx insn; | |
1050 | rtx mem_push_rtx; | |
dddb37d8 | 1051 | const int ifun = xstormy16_interrupt_function_p (); |
3bdb7a0a | 1052 | |
96fb1e39 | 1053 | mem_push_rtx = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); |
1054 | mem_push_rtx = gen_rtx_MEM (HImode, mem_push_rtx); | |
3bdb7a0a | 1055 | |
dddb37d8 | 1056 | layout = xstormy16_compute_stack_layout (); |
96fb1e39 | 1057 | |
6a3c0fd8 | 1058 | if (layout.locals_size >= 32768) |
0a81f5a0 | 1059 | error ("local variable memory requirements exceed capacity"); |
6a3c0fd8 | 1060 | |
54474b85 | 1061 | if (flag_stack_usage_info) |
1062 | current_function_static_stack_size = layout.frame_size; | |
1063 | ||
96fb1e39 | 1064 | /* Save the argument registers if necessary. */ |
1065 | if (layout.stdarg_save_size) | |
3bdb7a0a | 1066 | for (regno = FIRST_ARGUMENT_REGISTER; |
96fb1e39 | 1067 | regno < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS; |
1068 | regno++) | |
1069 | { | |
6a3c0fd8 | 1070 | rtx dwarf; |
96fb1e39 | 1071 | rtx reg = gen_rtx_REG (HImode, regno); |
6a3c0fd8 | 1072 | |
96fb1e39 | 1073 | insn = emit_move_insn (mem_push_rtx, reg); |
1074 | RTX_FRAME_RELATED_P (insn) = 1; | |
6a3c0fd8 | 1075 | |
1076 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (2)); | |
3bdb7a0a | 1077 | |
6a3c0fd8 | 1078 | XVECEXP (dwarf, 0, 0) = gen_rtx_SET (VOIDmode, |
1079 | gen_rtx_MEM (Pmode, stack_pointer_rtx), | |
1080 | reg); | |
1081 | XVECEXP (dwarf, 0, 1) = gen_rtx_SET (Pmode, stack_pointer_rtx, | |
29c05e22 | 1082 | plus_constant (Pmode, |
1083 | stack_pointer_rtx, | |
6a3c0fd8 | 1084 | GET_MODE_SIZE (Pmode))); |
e53bb401 | 1085 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
6a3c0fd8 | 1086 | RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 0)) = 1; |
1087 | RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 1)) = 1; | |
96fb1e39 | 1088 | } |
3bdb7a0a | 1089 | |
96fb1e39 | 1090 | /* Push each of the registers to save. */ |
1091 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
1092 | if (REG_NEEDS_SAVE (regno, ifun)) | |
1093 | { | |
6a3c0fd8 | 1094 | rtx dwarf; |
96fb1e39 | 1095 | rtx reg = gen_rtx_REG (HImode, regno); |
6a3c0fd8 | 1096 | |
96fb1e39 | 1097 | insn = emit_move_insn (mem_push_rtx, reg); |
1098 | RTX_FRAME_RELATED_P (insn) = 1; | |
6a3c0fd8 | 1099 | |
1100 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (2)); | |
3bdb7a0a | 1101 | |
6a3c0fd8 | 1102 | XVECEXP (dwarf, 0, 0) = gen_rtx_SET (VOIDmode, |
1103 | gen_rtx_MEM (Pmode, stack_pointer_rtx), | |
1104 | reg); | |
1105 | XVECEXP (dwarf, 0, 1) = gen_rtx_SET (Pmode, stack_pointer_rtx, | |
c694a5cd | 1106 | plus_constant (Pmode, |
29c05e22 | 1107 | stack_pointer_rtx, |
6a3c0fd8 | 1108 | GET_MODE_SIZE (Pmode))); |
e53bb401 | 1109 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
6a3c0fd8 | 1110 | RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 0)) = 1; |
1111 | RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 1)) = 1; | |
96fb1e39 | 1112 | } |
1113 | ||
1114 | /* It's just possible that the SP here might be what we need for | |
d2833c15 | 1115 | the new FP... */ |
96fb1e39 | 1116 | if (frame_pointer_needed && layout.sp_minus_fp == layout.locals_size) |
f6af892b | 1117 | { |
1118 | insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); | |
1119 | RTX_FRAME_RELATED_P (insn) = 1; | |
1120 | } | |
96fb1e39 | 1121 | |
1122 | /* Allocate space for local variables. */ | |
1123 | if (layout.locals_size) | |
1124 | { | |
1125 | insn = emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx, | |
1126 | GEN_INT (layout.locals_size)); | |
1127 | RTX_FRAME_RELATED_P (insn) = 1; | |
1128 | } | |
1129 | ||
1130 | /* Set up the frame pointer, if required. */ | |
1131 | if (frame_pointer_needed && layout.sp_minus_fp != layout.locals_size) | |
1132 | { | |
1133 | insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); | |
f6af892b | 1134 | RTX_FRAME_RELATED_P (insn) = 1; |
a9d1218f | 1135 | |
96fb1e39 | 1136 | if (layout.sp_minus_fp) |
f6af892b | 1137 | { |
1138 | insn = emit_addhi3_postreload (hard_frame_pointer_rtx, | |
1139 | hard_frame_pointer_rtx, | |
1140 | GEN_INT (- layout.sp_minus_fp)); | |
1141 | RTX_FRAME_RELATED_P (insn) = 1; | |
1142 | } | |
96fb1e39 | 1143 | } |
1144 | } | |
1145 | ||
1146 | /* Do we need an epilogue at all? */ | |
3bdb7a0a | 1147 | |
96fb1e39 | 1148 | int |
3aed9a8d | 1149 | direct_return (void) |
96fb1e39 | 1150 | { |
3bdb7a0a | 1151 | return (reload_completed |
dd79b8f5 | 1152 | && xstormy16_compute_stack_layout ().frame_size == 0 |
1153 | && ! xstormy16_interrupt_function_p ()); | |
96fb1e39 | 1154 | } |
1155 | ||
cfc9bfb9 | 1156 | /* Called after register allocation to add any instructions needed for |
ebb11c7b | 1157 | the epilogue. Using an epilogue insn is favored compared to putting |
cfc9bfb9 | 1158 | all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro, |
1159 | since it allows the scheduler to intermix instructions with the | |
1160 | saves of the caller saved registers. In some cases, it might be | |
1161 | necessary to emit a barrier instruction as the last insn to prevent | |
1162 | such scheduling. */ | |
96fb1e39 | 1163 | |
1164 | void | |
3aed9a8d | 1165 | xstormy16_expand_epilogue (void) |
96fb1e39 | 1166 | { |
dddb37d8 | 1167 | struct xstormy16_stack_layout layout; |
899fa8d2 | 1168 | rtx mem_pop_rtx; |
96fb1e39 | 1169 | int regno; |
dddb37d8 | 1170 | const int ifun = xstormy16_interrupt_function_p (); |
3bdb7a0a | 1171 | |
96fb1e39 | 1172 | mem_pop_rtx = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); |
1173 | mem_pop_rtx = gen_rtx_MEM (HImode, mem_pop_rtx); | |
3bdb7a0a | 1174 | |
dddb37d8 | 1175 | layout = xstormy16_compute_stack_layout (); |
96fb1e39 | 1176 | |
1177 | /* Pop the stack for the locals. */ | |
1178 | if (layout.locals_size) | |
ac8b36b9 | 1179 | { |
1180 | if (frame_pointer_needed && layout.sp_minus_fp == layout.locals_size) | |
1181 | emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); | |
1182 | else | |
f6af892b | 1183 | emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx, |
1184 | GEN_INT (- layout.locals_size)); | |
ac8b36b9 | 1185 | } |
96fb1e39 | 1186 | |
1187 | /* Restore any call-saved registers. */ | |
1188 | for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--) | |
1189 | if (REG_NEEDS_SAVE (regno, ifun)) | |
f6af892b | 1190 | emit_move_insn (gen_rtx_REG (HImode, regno), mem_pop_rtx); |
3bdb7a0a | 1191 | |
96fb1e39 | 1192 | /* Pop the stack for the stdarg save area. */ |
1193 | if (layout.stdarg_save_size) | |
f6af892b | 1194 | emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx, |
1195 | GEN_INT (- layout.stdarg_save_size)); | |
96fb1e39 | 1196 | |
1197 | /* Return. */ | |
1198 | if (ifun) | |
1199 | emit_jump_insn (gen_return_internal_interrupt ()); | |
1200 | else | |
1201 | emit_jump_insn (gen_return_internal ()); | |
1202 | } | |
1203 | ||
1204 | int | |
3aed9a8d | 1205 | xstormy16_epilogue_uses (int regno) |
96fb1e39 | 1206 | { |
1207 | if (reload_completed && call_used_regs[regno]) | |
1208 | { | |
dddb37d8 | 1209 | const int ifun = xstormy16_interrupt_function_p (); |
96fb1e39 | 1210 | return REG_NEEDS_SAVE (regno, ifun); |
1211 | } | |
1212 | return 0; | |
1213 | } | |
dbea1f2f | 1214 | |
1215 | void | |
3aed9a8d | 1216 | xstormy16_function_profiler (void) |
dbea1f2f | 1217 | { |
1218 | sorry ("function_profiler support"); | |
1219 | } | |
96fb1e39 | 1220 | \f |
ee2f4146 | 1221 | /* Update CUM to advance past an argument in the argument list. The |
1222 | values MODE, TYPE and NAMED describe that argument. Once this is | |
1223 | done, the variable CUM is suitable for analyzing the *following* | |
1224 | argument with `TARGET_FUNCTION_ARG', etc. | |
96fb1e39 | 1225 | |
1226 | This function need not do anything if the argument in question was | |
1227 | passed on the stack. The compiler knows how to track the amount of | |
1228 | stack space used for arguments without any special help. However, | |
dddb37d8 | 1229 | it makes life easier for xstormy16_build_va_list if it does update |
96fb1e39 | 1230 | the word count. */ |
3bdb7a0a | 1231 | |
ee2f4146 | 1232 | static void |
39cba157 | 1233 | xstormy16_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, |
ee2f4146 | 1234 | const_tree type, bool named ATTRIBUTE_UNUSED) |
96fb1e39 | 1235 | { |
39cba157 | 1236 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
1237 | ||
96fb1e39 | 1238 | /* If an argument would otherwise be passed partially in registers, |
1239 | and partially on the stack, the whole of it is passed on the | |
1240 | stack. */ | |
ee2f4146 | 1241 | if (*cum < NUM_ARGUMENT_REGISTERS |
1242 | && *cum + XSTORMY16_WORD_SIZE (type, mode) > NUM_ARGUMENT_REGISTERS) | |
1243 | *cum = NUM_ARGUMENT_REGISTERS; | |
3bdb7a0a | 1244 | |
ee2f4146 | 1245 | *cum += XSTORMY16_WORD_SIZE (type, mode); |
96fb1e39 | 1246 | } |
1247 | ||
ee2f4146 | 1248 | static rtx |
39cba157 | 1249 | xstormy16_function_arg (cumulative_args_t cum_v, enum machine_mode mode, |
ee2f4146 | 1250 | const_tree type, bool named ATTRIBUTE_UNUSED) |
db8291e0 | 1251 | { |
39cba157 | 1252 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
1253 | ||
db8291e0 | 1254 | if (mode == VOIDmode) |
1255 | return const0_rtx; | |
0336f0f0 | 1256 | if (targetm.calls.must_pass_in_stack (mode, type) |
e53bb401 | 1257 | || *cum + XSTORMY16_WORD_SIZE (type, mode) > NUM_ARGUMENT_REGISTERS) |
3bdb7a0a | 1258 | return NULL_RTX; |
e53bb401 | 1259 | return gen_rtx_REG (mode, *cum + FIRST_ARGUMENT_REGISTER); |
db8291e0 | 1260 | } |
1261 | ||
96fb1e39 | 1262 | /* Build the va_list type. |
1263 | ||
1264 | For this chip, va_list is a record containing a counter and a pointer. | |
1265 | The counter is of type 'int' and indicates how many bytes | |
1266 | have been used to date. The pointer indicates the stack position | |
3bdb7a0a | 1267 | for arguments that have not been passed in registers. |
96fb1e39 | 1268 | To keep the layout nice, the pointer is first in the structure. */ |
1269 | ||
89176bdb | 1270 | static tree |
1271 | xstormy16_build_builtin_va_list (void) | |
96fb1e39 | 1272 | { |
1273 | tree f_1, f_2, record, type_decl; | |
1274 | ||
a1f71e15 | 1275 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
54e46243 | 1276 | type_decl = build_decl (BUILTINS_LOCATION, |
1277 | TYPE_DECL, get_identifier ("__va_list_tag"), record); | |
96fb1e39 | 1278 | |
54e46243 | 1279 | f_1 = build_decl (BUILTINS_LOCATION, |
1280 | FIELD_DECL, get_identifier ("base"), | |
96fb1e39 | 1281 | ptr_type_node); |
54e46243 | 1282 | f_2 = build_decl (BUILTINS_LOCATION, |
1283 | FIELD_DECL, get_identifier ("count"), | |
96fb1e39 | 1284 | unsigned_type_node); |
1285 | ||
1286 | DECL_FIELD_CONTEXT (f_1) = record; | |
1287 | DECL_FIELD_CONTEXT (f_2) = record; | |
1288 | ||
bc907808 | 1289 | TYPE_STUB_DECL (record) = type_decl; |
96fb1e39 | 1290 | TYPE_NAME (record) = type_decl; |
1291 | TYPE_FIELDS (record) = f_1; | |
1767a056 | 1292 | DECL_CHAIN (f_1) = f_2; |
96fb1e39 | 1293 | |
1294 | layout_type (record); | |
1295 | ||
1296 | return record; | |
1297 | } | |
1298 | ||
808a491c | 1299 | /* Implement the stdarg/varargs va_start macro. STDARG_P is nonzero if this |
96fb1e39 | 1300 | is stdarg.h instead of varargs.h. VALIST is the tree of the va_list |
1301 | variable to initialize. NEXTARG is the machine independent notion of the | |
1302 | 'next' argument after the variable arguments. */ | |
3bdb7a0a | 1303 | |
8a58ed0a | 1304 | static void |
3aed9a8d | 1305 | xstormy16_expand_builtin_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) |
96fb1e39 | 1306 | { |
1307 | tree f_base, f_count; | |
1308 | tree base, count; | |
bcf954af | 1309 | tree t,u; |
96fb1e39 | 1310 | |
dddb37d8 | 1311 | if (xstormy16_interrupt_function_p ()) |
96fb1e39 | 1312 | error ("cannot use va_start in interrupt function"); |
3bdb7a0a | 1313 | |
96fb1e39 | 1314 | f_base = TYPE_FIELDS (va_list_type_node); |
1767a056 | 1315 | f_count = DECL_CHAIN (f_base); |
3bdb7a0a | 1316 | |
ed03eadb | 1317 | base = build3 (COMPONENT_REF, TREE_TYPE (f_base), valist, f_base, NULL_TREE); |
1318 | count = build3 (COMPONENT_REF, TREE_TYPE (f_count), valist, f_count, | |
1319 | NULL_TREE); | |
96fb1e39 | 1320 | |
1321 | t = make_tree (TREE_TYPE (base), virtual_incoming_args_rtx); | |
f6af892b | 1322 | u = build_int_cst (NULL_TREE, - INCOMING_FRAME_SP_OFFSET); |
bcf954af | 1323 | u = fold_convert (TREE_TYPE (count), u); |
2cc66f2a | 1324 | t = fold_build_pointer_plus (t, u); |
75a70cf9 | 1325 | t = build2 (MODIFY_EXPR, TREE_TYPE (base), base, t); |
96fb1e39 | 1326 | TREE_SIDE_EFFECTS (t) = 1; |
1327 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
1328 | ||
3bdb7a0a | 1329 | t = build2 (MODIFY_EXPR, TREE_TYPE (count), count, |
ed03eadb | 1330 | build_int_cst (NULL_TREE, |
abe32cce | 1331 | crtl->args.info * UNITS_PER_WORD)); |
96fb1e39 | 1332 | TREE_SIDE_EFFECTS (t) = 1; |
1333 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
1334 | } | |
1335 | ||
1336 | /* Implement the stdarg/varargs va_arg macro. VALIST is the variable | |
3c7203bf | 1337 | of type va_list as a tree, TYPE is the type passed to va_arg. |
1338 | Note: This algorithm is documented in stormy-abi. */ | |
3bdb7a0a | 1339 | |
a98995ea | 1340 | static tree |
75a70cf9 | 1341 | xstormy16_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
1342 | gimple_seq *post_p ATTRIBUTE_UNUSED) | |
96fb1e39 | 1343 | { |
1344 | tree f_base, f_count; | |
1345 | tree base, count; | |
a98995ea | 1346 | tree count_tmp, addr, t; |
1347 | tree lab_gotaddr, lab_fromstack; | |
db8291e0 | 1348 | int size, size_of_reg_args, must_stack; |
a98995ea | 1349 | tree size_tree; |
1350 | ||
96fb1e39 | 1351 | f_base = TYPE_FIELDS (va_list_type_node); |
1767a056 | 1352 | f_count = DECL_CHAIN (f_base); |
3bdb7a0a | 1353 | |
ed03eadb | 1354 | base = build3 (COMPONENT_REF, TREE_TYPE (f_base), valist, f_base, NULL_TREE); |
1355 | count = build3 (COMPONENT_REF, TREE_TYPE (f_count), valist, f_count, | |
1356 | NULL_TREE); | |
96fb1e39 | 1357 | |
0336f0f0 | 1358 | must_stack = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type); |
96fb1e39 | 1359 | size_tree = round_up (size_in_bytes (type), UNITS_PER_WORD); |
a98995ea | 1360 | gimplify_expr (&size_tree, pre_p, NULL, is_gimple_val, fb_rvalue); |
3bdb7a0a | 1361 | |
3c7203bf | 1362 | size_of_reg_args = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD; |
96fb1e39 | 1363 | |
a98995ea | 1364 | count_tmp = get_initialized_tmp_var (count, pre_p, NULL); |
54e46243 | 1365 | lab_gotaddr = create_artificial_label (UNKNOWN_LOCATION); |
1366 | lab_fromstack = create_artificial_label (UNKNOWN_LOCATION); | |
a98995ea | 1367 | addr = create_tmp_var (ptr_type_node, NULL); |
3c7203bf | 1368 | |
db8291e0 | 1369 | if (!must_stack) |
1370 | { | |
a98995ea | 1371 | tree r; |
1372 | ||
1373 | t = fold_convert (TREE_TYPE (count), size_tree); | |
ed03eadb | 1374 | t = build2 (PLUS_EXPR, TREE_TYPE (count), count_tmp, t); |
a98995ea | 1375 | r = fold_convert (TREE_TYPE (count), size_int (size_of_reg_args)); |
ed03eadb | 1376 | t = build2 (GT_EXPR, boolean_type_node, t, r); |
1377 | t = build3 (COND_EXPR, void_type_node, t, | |
1378 | build1 (GOTO_EXPR, void_type_node, lab_fromstack), | |
1379 | NULL_TREE); | |
a98995ea | 1380 | gimplify_and_add (t, pre_p); |
bcf954af | 1381 | |
2cc66f2a | 1382 | t = fold_build_pointer_plus (base, count_tmp); |
75a70cf9 | 1383 | gimplify_assign (addr, t, pre_p); |
a98995ea | 1384 | |
ed03eadb | 1385 | t = build1 (GOTO_EXPR, void_type_node, lab_gotaddr); |
a98995ea | 1386 | gimplify_and_add (t, pre_p); |
1387 | ||
ed03eadb | 1388 | t = build1 (LABEL_EXPR, void_type_node, lab_fromstack); |
a98995ea | 1389 | gimplify_and_add (t, pre_p); |
db8291e0 | 1390 | } |
3bdb7a0a | 1391 | |
96fb1e39 | 1392 | /* Arguments larger than a word might need to skip over some |
1393 | registers, since arguments are either passed entirely in | |
1394 | registers or entirely on the stack. */ | |
db8291e0 | 1395 | size = PUSH_ROUNDING (int_size_in_bytes (type)); |
1396 | if (size > 2 || size < 0 || must_stack) | |
96fb1e39 | 1397 | { |
a98995ea | 1398 | tree r, u; |
1399 | ||
1400 | r = size_int (NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD); | |
75a70cf9 | 1401 | u = build2 (MODIFY_EXPR, TREE_TYPE (count_tmp), count_tmp, r); |
a98995ea | 1402 | |
1403 | t = fold_convert (TREE_TYPE (count), r); | |
ed03eadb | 1404 | t = build2 (GE_EXPR, boolean_type_node, count_tmp, t); |
1405 | t = build3 (COND_EXPR, void_type_node, t, NULL_TREE, u); | |
a98995ea | 1406 | gimplify_and_add (t, pre_p); |
96fb1e39 | 1407 | } |
1408 | ||
a98995ea | 1409 | t = size_int (NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD |
f6af892b | 1410 | + INCOMING_FRAME_SP_OFFSET); |
a98995ea | 1411 | t = fold_convert (TREE_TYPE (count), t); |
ed03eadb | 1412 | t = build2 (MINUS_EXPR, TREE_TYPE (count), count_tmp, t); |
1413 | t = build2 (PLUS_EXPR, TREE_TYPE (count), t, | |
1414 | fold_convert (TREE_TYPE (count), size_tree)); | |
bcf954af | 1415 | t = fold_convert (TREE_TYPE (t), fold (t)); |
1416 | t = fold_build1 (NEGATE_EXPR, TREE_TYPE (t), t); | |
2cc66f2a | 1417 | t = fold_build_pointer_plus (base, t); |
75a70cf9 | 1418 | gimplify_assign (addr, t, pre_p); |
a98995ea | 1419 | |
ed03eadb | 1420 | t = build1 (LABEL_EXPR, void_type_node, lab_gotaddr); |
a98995ea | 1421 | gimplify_and_add (t, pre_p); |
96fb1e39 | 1422 | |
a98995ea | 1423 | t = fold_convert (TREE_TYPE (count), size_tree); |
ed03eadb | 1424 | t = build2 (PLUS_EXPR, TREE_TYPE (count), count_tmp, t); |
75a70cf9 | 1425 | gimplify_assign (count, t, pre_p); |
3bdb7a0a | 1426 | |
a98995ea | 1427 | addr = fold_convert (build_pointer_type (type), addr); |
063f5fdd | 1428 | return build_va_arg_indirect_ref (addr); |
96fb1e39 | 1429 | } |
1430 | ||
cb9cec17 | 1431 | /* Worker function for TARGET_TRAMPOLINE_INIT. */ |
3bdb7a0a | 1432 | |
cb9cec17 | 1433 | static void |
1434 | xstormy16_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain) | |
96fb1e39 | 1435 | { |
96fb1e39 | 1436 | rtx temp = gen_reg_rtx (HImode); |
1437 | rtx reg_fnaddr = gen_reg_rtx (HImode); | |
cb9cec17 | 1438 | rtx reg_addr, reg_addr_mem; |
96fb1e39 | 1439 | |
cb9cec17 | 1440 | reg_addr = copy_to_reg (XEXP (m_tramp, 0)); |
1441 | reg_addr_mem = adjust_automodify_address (m_tramp, HImode, reg_addr, 0); | |
3bdb7a0a | 1442 | |
96fb1e39 | 1443 | emit_move_insn (temp, GEN_INT (0x3130 | STATIC_CHAIN_REGNUM)); |
1444 | emit_move_insn (reg_addr_mem, temp); | |
ac8b36b9 | 1445 | emit_insn (gen_addhi3 (reg_addr, reg_addr, const2_rtx)); |
cb9cec17 | 1446 | reg_addr_mem = adjust_automodify_address (reg_addr_mem, VOIDmode, NULL, 2); |
1447 | ||
96fb1e39 | 1448 | emit_move_insn (temp, static_chain); |
1449 | emit_move_insn (reg_addr_mem, temp); | |
ac8b36b9 | 1450 | emit_insn (gen_addhi3 (reg_addr, reg_addr, const2_rtx)); |
cb9cec17 | 1451 | reg_addr_mem = adjust_automodify_address (reg_addr_mem, VOIDmode, NULL, 2); |
1452 | ||
1453 | emit_move_insn (reg_fnaddr, XEXP (DECL_RTL (fndecl), 0)); | |
96fb1e39 | 1454 | emit_move_insn (temp, reg_fnaddr); |
1455 | emit_insn (gen_andhi3 (temp, temp, GEN_INT (0xFF))); | |
1456 | emit_insn (gen_iorhi3 (temp, temp, GEN_INT (0x0200))); | |
1457 | emit_move_insn (reg_addr_mem, temp); | |
ac8b36b9 | 1458 | emit_insn (gen_addhi3 (reg_addr, reg_addr, const2_rtx)); |
cb9cec17 | 1459 | reg_addr_mem = adjust_automodify_address (reg_addr_mem, VOIDmode, NULL, 2); |
1460 | ||
96fb1e39 | 1461 | emit_insn (gen_lshrhi3 (reg_fnaddr, reg_fnaddr, GEN_INT (8))); |
1462 | emit_move_insn (reg_addr_mem, reg_fnaddr); | |
1463 | } | |
1464 | ||
65bf7507 | 1465 | /* Worker function for TARGET_FUNCTION_VALUE. */ |
6644435d | 1466 | |
65bf7507 | 1467 | static rtx |
1468 | xstormy16_function_value (const_tree valtype, | |
1469 | const_tree func ATTRIBUTE_UNUSED, | |
1470 | bool outgoing ATTRIBUTE_UNUSED) | |
96fb1e39 | 1471 | { |
1472 | enum machine_mode mode; | |
1473 | mode = TYPE_MODE (valtype); | |
1474 | PROMOTE_MODE (mode, 0, valtype); | |
1475 | return gen_rtx_REG (mode, RETURN_VALUE_REGNUM); | |
1476 | } | |
1477 | ||
65bf7507 | 1478 | /* Worker function for TARGET_LIBCALL_VALUE. */ |
1479 | ||
1480 | static rtx | |
1481 | xstormy16_libcall_value (enum machine_mode mode, | |
1482 | const_rtx fun ATTRIBUTE_UNUSED) | |
1483 | { | |
1484 | return gen_rtx_REG (mode, RETURN_VALUE_REGNUM); | |
1485 | } | |
1486 | ||
1487 | /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. */ | |
1488 | ||
1489 | static bool | |
1490 | xstormy16_function_value_regno_p (const unsigned int regno) | |
1491 | { | |
1492 | return (regno == RETURN_VALUE_REGNUM); | |
1493 | } | |
1494 | ||
41798525 | 1495 | /* A C compound statement that outputs the assembler code for a thunk function, |
1496 | used to implement C++ virtual function calls with multiple inheritance. The | |
1497 | thunk acts as a wrapper around a virtual function, adjusting the implicit | |
1498 | object parameter before handing control off to the real function. | |
1499 | ||
1500 | First, emit code to add the integer DELTA to the location that contains the | |
1501 | incoming first argument. Assume that this argument contains a pointer, and | |
1502 | is the one used to pass the `this' pointer in C++. This is the incoming | |
1503 | argument *before* the function prologue, e.g. `%o0' on a sparc. The | |
1504 | addition must preserve the values of all other incoming arguments. | |
1505 | ||
1506 | After the addition, emit code to jump to FUNCTION, which is a | |
1507 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch | |
1508 | the return address. Hence returning from FUNCTION will return to whoever | |
1509 | called the current `thunk'. | |
1510 | ||
1511 | The effect must be as if @var{function} had been called directly | |
1512 | with the adjusted first argument. This macro is responsible for | |
1513 | emitting all of the code for a thunk function; | |
1514 | TARGET_ASM_FUNCTION_PROLOGUE and TARGET_ASM_FUNCTION_EPILOGUE are | |
1515 | not invoked. | |
1516 | ||
1517 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been | |
1518 | extracted from it.) It might possibly be useful on some targets, but | |
1519 | probably not. */ | |
1520 | ||
6988553d | 1521 | static void |
3aed9a8d | 1522 | xstormy16_asm_output_mi_thunk (FILE *file, |
1523 | tree thunk_fndecl ATTRIBUTE_UNUSED, | |
1524 | HOST_WIDE_INT delta, | |
1525 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
1526 | tree function) | |
41798525 | 1527 | { |
1528 | int regnum = FIRST_ARGUMENT_REGISTER; | |
3bdb7a0a | 1529 | |
41798525 | 1530 | /* There might be a hidden first argument for a returned structure. */ |
45550790 | 1531 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
41798525 | 1532 | regnum += 1; |
3bdb7a0a | 1533 | |
e7f5e241 | 1534 | fprintf (file, "\tadd %s,#0x%x\n", reg_names[regnum], (int) delta & 0xFFFF); |
41798525 | 1535 | fputs ("\tjmpf ", file); |
1536 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
1537 | putc ('\n', file); | |
1538 | } | |
1539 | ||
3c1df5aa | 1540 | /* The purpose of this function is to override the default behavior of |
1541 | BSS objects. Normally, they go into .bss or .sbss via ".common" | |
1542 | directives, but we need to override that and put them in | |
1543 | .bss_below100. We can't just use a section override (like we do | |
1544 | for .data_below100), because that makes them initialized rather | |
1545 | than uninitialized. */ | |
3bdb7a0a | 1546 | |
3c1df5aa | 1547 | void |
1548 | xstormy16_asm_output_aligned_common (FILE *stream, | |
ab764c12 | 1549 | tree decl, |
3c1df5aa | 1550 | const char *name, |
1551 | int size, | |
1552 | int align, | |
1553 | int global) | |
1554 | { | |
579a6158 | 1555 | rtx mem = decl == NULL_TREE ? NULL_RTX : DECL_RTL (decl); |
ab764c12 | 1556 | rtx symbol; |
3bdb7a0a | 1557 | |
ab764c12 | 1558 | if (mem != NULL_RTX |
899fa8d2 | 1559 | && MEM_P (mem) |
ab764c12 | 1560 | && GET_CODE (symbol = XEXP (mem, 0)) == SYMBOL_REF |
1561 | && SYMBOL_REF_FLAGS (symbol) & SYMBOL_FLAG_XSTORMY16_BELOW100) | |
3c1df5aa | 1562 | { |
ab764c12 | 1563 | const char *name2; |
1564 | int p2align = 0; | |
1565 | ||
2f14b1f9 | 1566 | switch_to_section (bss100_section); |
ab764c12 | 1567 | |
1568 | while (align > 8) | |
3c1df5aa | 1569 | { |
ab764c12 | 1570 | align /= 2; |
1571 | p2align ++; | |
3c1df5aa | 1572 | } |
3c1df5aa | 1573 | |
ab764c12 | 1574 | name2 = default_strip_name_encoding (name); |
1575 | if (global) | |
1576 | fprintf (stream, "\t.globl\t%s\n", name2); | |
1577 | if (p2align) | |
1578 | fprintf (stream, "\t.p2align %d\n", p2align); | |
1579 | fprintf (stream, "\t.type\t%s, @object\n", name2); | |
1580 | fprintf (stream, "\t.size\t%s, %d\n", name2, size); | |
1581 | fprintf (stream, "%s:\n\t.space\t%d\n", name2, size); | |
1582 | return; | |
3c1df5aa | 1583 | } |
1584 | ||
1585 | if (!global) | |
1586 | { | |
1587 | fprintf (stream, "\t.local\t"); | |
1588 | assemble_name (stream, name); | |
1589 | fprintf (stream, "\n"); | |
1590 | } | |
1591 | fprintf (stream, "\t.comm\t"); | |
1592 | assemble_name (stream, name); | |
a95d9e97 | 1593 | fprintf (stream, ",%u,%u\n", size, align / BITS_PER_UNIT); |
3c1df5aa | 1594 | } |
1595 | ||
2f14b1f9 | 1596 | /* Implement TARGET_ASM_INIT_SECTIONS. */ |
1597 | ||
1598 | static void | |
1599 | xstormy16_asm_init_sections (void) | |
1600 | { | |
1601 | bss100_section | |
1602 | = get_unnamed_section (SECTION_WRITE | SECTION_BSS, | |
1603 | output_section_asm_op, | |
1604 | "\t.section \".bss_below100\",\"aw\",@nobits"); | |
1605 | } | |
1606 | ||
3c1df5aa | 1607 | /* Mark symbols with the "below100" attribute so that we can use the |
1608 | special addressing modes for them. */ | |
1609 | ||
1610 | static void | |
ab764c12 | 1611 | xstormy16_encode_section_info (tree decl, rtx r, int first) |
3c1df5aa | 1612 | { |
7852debe | 1613 | default_encode_section_info (decl, r, first); |
1614 | ||
ab764c12 | 1615 | if (TREE_CODE (decl) == VAR_DECL |
3c1df5aa | 1616 | && (lookup_attribute ("below100", DECL_ATTRIBUTES (decl)) |
1617 | || lookup_attribute ("BELOW100", DECL_ATTRIBUTES (decl)))) | |
1618 | { | |
ab764c12 | 1619 | rtx symbol = XEXP (r, 0); |
3bdb7a0a | 1620 | |
ab764c12 | 1621 | gcc_assert (GET_CODE (symbol) == SYMBOL_REF); |
1622 | SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_XSTORMY16_BELOW100; | |
3c1df5aa | 1623 | } |
1624 | } | |
1625 | ||
a9d1218f | 1626 | #undef TARGET_ASM_CONSTRUCTOR |
3bdb7a0a | 1627 | #define TARGET_ASM_CONSTRUCTOR xstormy16_asm_out_constructor |
a9d1218f | 1628 | #undef TARGET_ASM_DESTRUCTOR |
3bdb7a0a | 1629 | #define TARGET_ASM_DESTRUCTOR xstormy16_asm_out_destructor |
1630 | ||
1631 | /* Output constructors and destructors. Just like | |
1632 | default_named_section_asm_out_* but don't set the sections writable. */ | |
f32f9992 | 1633 | |
1634 | static void | |
3aed9a8d | 1635 | xstormy16_asm_out_destructor (rtx symbol, int priority) |
f32f9992 | 1636 | { |
1637 | const char *section = ".dtors"; | |
1638 | char buf[16]; | |
1639 | ||
5aedf60c | 1640 | /* ??? This only works reliably with the GNU linker. */ |
f32f9992 | 1641 | if (priority != DEFAULT_INIT_PRIORITY) |
1642 | { | |
1643 | sprintf (buf, ".dtors.%.5u", | |
1644 | /* Invert the numbering so the linker puts us in the proper | |
1645 | order; constructors are run from right to left, and the | |
1646 | linker sorts in increasing order. */ | |
1647 | MAX_INIT_PRIORITY - priority); | |
1648 | section = buf; | |
1649 | } | |
1650 | ||
2f14b1f9 | 1651 | switch_to_section (get_section (section, 0, NULL)); |
f32f9992 | 1652 | assemble_align (POINTER_SIZE); |
1653 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); | |
1654 | } | |
1655 | ||
1656 | static void | |
3aed9a8d | 1657 | xstormy16_asm_out_constructor (rtx symbol, int priority) |
f32f9992 | 1658 | { |
1659 | const char *section = ".ctors"; | |
1660 | char buf[16]; | |
1661 | ||
5aedf60c | 1662 | /* ??? This only works reliably with the GNU linker. */ |
f32f9992 | 1663 | if (priority != DEFAULT_INIT_PRIORITY) |
1664 | { | |
1665 | sprintf (buf, ".ctors.%.5u", | |
1666 | /* Invert the numbering so the linker puts us in the proper | |
1667 | order; constructors are run from right to left, and the | |
1668 | linker sorts in increasing order. */ | |
1669 | MAX_INIT_PRIORITY - priority); | |
1670 | section = buf; | |
1671 | } | |
1672 | ||
2f14b1f9 | 1673 | switch_to_section (get_section (section, 0, NULL)); |
f32f9992 | 1674 | assemble_align (POINTER_SIZE); |
1675 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); | |
1676 | } | |
96fb1e39 | 1677 | \f |
3d451f7c | 1678 | /* Worker function for TARGET_PRINT_OPERAND_ADDRESS. |
3bdb7a0a | 1679 | |
3d451f7c | 1680 | Print a memory address as an operand to reference that memory location. */ |
1681 | ||
1682 | static void | |
3aed9a8d | 1683 | xstormy16_print_operand_address (FILE *file, rtx address) |
96fb1e39 | 1684 | { |
1685 | HOST_WIDE_INT offset; | |
1686 | int pre_dec, post_inc; | |
1687 | ||
1688 | /* There are a few easy cases. */ | |
899fa8d2 | 1689 | if (CONST_INT_P (address)) |
96fb1e39 | 1690 | { |
1691 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (address) & 0xFFFF); | |
1692 | return; | |
1693 | } | |
3bdb7a0a | 1694 | |
899fa8d2 | 1695 | if (CONSTANT_P (address) || LABEL_P (address)) |
96fb1e39 | 1696 | { |
1697 | output_addr_const (file, address); | |
1698 | return; | |
1699 | } | |
96fb1e39 | 1700 | |
3bdb7a0a | 1701 | /* Otherwise, it's hopefully something of the form |
1702 | (plus:HI (pre_dec:HI (reg:HI ...)) (const_int ...)). */ | |
96fb1e39 | 1703 | if (GET_CODE (address) == PLUS) |
1704 | { | |
899fa8d2 | 1705 | gcc_assert (CONST_INT_P (XEXP (address, 1))); |
96fb1e39 | 1706 | offset = INTVAL (XEXP (address, 1)); |
1707 | address = XEXP (address, 0); | |
1708 | } | |
1709 | else | |
1710 | offset = 0; | |
1711 | ||
1712 | pre_dec = (GET_CODE (address) == PRE_DEC); | |
1713 | post_inc = (GET_CODE (address) == POST_INC); | |
1714 | if (pre_dec || post_inc) | |
1715 | address = XEXP (address, 0); | |
3bdb7a0a | 1716 | |
899fa8d2 | 1717 | gcc_assert (REG_P (address)); |
96fb1e39 | 1718 | |
1719 | fputc ('(', file); | |
1720 | if (pre_dec) | |
1721 | fputs ("--", file); | |
1722 | fputs (reg_names [REGNO (address)], file); | |
1723 | if (post_inc) | |
1724 | fputs ("++", file); | |
1725 | if (offset != 0) | |
4840a03a | 1726 | fprintf (file, "," HOST_WIDE_INT_PRINT_DEC, offset); |
96fb1e39 | 1727 | fputc (')', file); |
1728 | } | |
1729 | ||
3d451f7c | 1730 | /* Worker function for TARGET_PRINT_OPERAND. |
3bdb7a0a | 1731 | |
3d451f7c | 1732 | Print an operand to an assembler instruction. */ |
1733 | ||
1734 | static void | |
3aed9a8d | 1735 | xstormy16_print_operand (FILE *file, rtx x, int code) |
96fb1e39 | 1736 | { |
1737 | switch (code) | |
1738 | { | |
1739 | case 'B': | |
1740 | /* There is either one bit set, or one bit clear, in X. | |
1741 | Print it preceded by '#'. */ | |
1742 | { | |
3c1df5aa | 1743 | static int bits_set[8] = { 0, 1, 1, 2, 1, 2, 2, 3 }; |
ea53ad7c | 1744 | HOST_WIDE_INT xx = 1; |
1745 | HOST_WIDE_INT l; | |
96fb1e39 | 1746 | |
899fa8d2 | 1747 | if (CONST_INT_P (x)) |
96fb1e39 | 1748 | xx = INTVAL (x); |
1749 | else | |
1e5fcbe2 | 1750 | output_operand_lossage ("'B' operand is not constant"); |
3bdb7a0a | 1751 | |
3c1df5aa | 1752 | /* GCC sign-extends masks with the MSB set, so we have to |
1753 | detect all the cases that differ only in sign extension | |
1754 | beyond the bits we care about. Normally, the predicates | |
1755 | and constraints ensure that we have the right values. This | |
1756 | works correctly for valid masks. */ | |
1757 | if (bits_set[xx & 7] <= 1) | |
1758 | { | |
1759 | /* Remove sign extension bits. */ | |
1760 | if ((~xx & ~(HOST_WIDE_INT)0xff) == 0) | |
1761 | xx &= 0xff; | |
1762 | else if ((~xx & ~(HOST_WIDE_INT)0xffff) == 0) | |
1763 | xx &= 0xffff; | |
1764 | l = exact_log2 (xx); | |
1765 | } | |
1766 | else | |
1767 | { | |
1768 | /* Add sign extension bits. */ | |
1769 | if ((xx & ~(HOST_WIDE_INT)0xff) == 0) | |
1770 | xx |= ~(HOST_WIDE_INT)0xff; | |
1771 | else if ((xx & ~(HOST_WIDE_INT)0xffff) == 0) | |
1772 | xx |= ~(HOST_WIDE_INT)0xffff; | |
1773 | l = exact_log2 (~xx); | |
1774 | } | |
1775 | ||
96fb1e39 | 1776 | if (l == -1) |
1e5fcbe2 | 1777 | output_operand_lossage ("'B' operand has multiple bits set"); |
3bdb7a0a | 1778 | |
4840a03a | 1779 | fprintf (file, IMMEDIATE_PREFIX HOST_WIDE_INT_PRINT_DEC, l); |
96fb1e39 | 1780 | return; |
1781 | } | |
1782 | ||
1783 | case 'C': | |
1784 | /* Print the symbol without a surrounding @fptr(). */ | |
1785 | if (GET_CODE (x) == SYMBOL_REF) | |
1786 | assemble_name (file, XSTR (x, 0)); | |
899fa8d2 | 1787 | else if (LABEL_P (x)) |
633beede | 1788 | output_asm_label (x); |
96fb1e39 | 1789 | else |
dddb37d8 | 1790 | xstormy16_print_operand_address (file, x); |
96fb1e39 | 1791 | return; |
1792 | ||
1793 | case 'o': | |
1794 | case 'O': | |
3bdb7a0a | 1795 | /* Print the immediate operand less one, preceded by '#'. |
96fb1e39 | 1796 | For 'O', negate it first. */ |
1797 | { | |
ea53ad7c | 1798 | HOST_WIDE_INT xx = 0; |
3bdb7a0a | 1799 | |
899fa8d2 | 1800 | if (CONST_INT_P (x)) |
96fb1e39 | 1801 | xx = INTVAL (x); |
1802 | else | |
1e5fcbe2 | 1803 | output_operand_lossage ("'o' operand is not constant"); |
3bdb7a0a | 1804 | |
96fb1e39 | 1805 | if (code == 'O') |
1806 | xx = -xx; | |
3bdb7a0a | 1807 | |
4840a03a | 1808 | fprintf (file, IMMEDIATE_PREFIX HOST_WIDE_INT_PRINT_DEC, xx - 1); |
96fb1e39 | 1809 | return; |
1810 | } | |
1811 | ||
3c1df5aa | 1812 | case 'b': |
1813 | /* Print the shift mask for bp/bn. */ | |
1814 | { | |
1815 | HOST_WIDE_INT xx = 1; | |
1816 | HOST_WIDE_INT l; | |
1817 | ||
899fa8d2 | 1818 | if (CONST_INT_P (x)) |
3c1df5aa | 1819 | xx = INTVAL (x); |
1820 | else | |
1e5fcbe2 | 1821 | output_operand_lossage ("'B' operand is not constant"); |
3bdb7a0a | 1822 | |
3c1df5aa | 1823 | l = 7 - xx; |
3bdb7a0a | 1824 | |
3c1df5aa | 1825 | fputs (IMMEDIATE_PREFIX, file); |
1826 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, l); | |
1827 | return; | |
1828 | } | |
1829 | ||
96fb1e39 | 1830 | case 0: |
1831 | /* Handled below. */ | |
1832 | break; | |
3bdb7a0a | 1833 | |
96fb1e39 | 1834 | default: |
dddb37d8 | 1835 | output_operand_lossage ("xstormy16_print_operand: unknown code"); |
96fb1e39 | 1836 | return; |
1837 | } | |
1838 | ||
1839 | switch (GET_CODE (x)) | |
1840 | { | |
1841 | case REG: | |
1842 | fputs (reg_names [REGNO (x)], file); | |
1843 | break; | |
1844 | ||
1845 | case MEM: | |
dddb37d8 | 1846 | xstormy16_print_operand_address (file, XEXP (x, 0)); |
96fb1e39 | 1847 | break; |
1848 | ||
1849 | default: | |
1850 | /* Some kind of constant or label; an immediate operand, | |
1851 | so prefix it with '#' for the assembler. */ | |
1852 | fputs (IMMEDIATE_PREFIX, file); | |
1853 | output_addr_const (file, x); | |
1854 | break; | |
1855 | } | |
1856 | ||
1857 | return; | |
1858 | } | |
96fb1e39 | 1859 | \f |
1860 | /* Expander for the `casesi' pattern. | |
1861 | INDEX is the index of the switch statement. | |
1862 | LOWER_BOUND is a CONST_INT that is the value of INDEX corresponding | |
1863 | to the first table entry. | |
1864 | RANGE is the number of table entries. | |
1865 | TABLE is an ADDR_VEC that is the jump table. | |
1866 | DEFAULT_LABEL is the address to branch to if INDEX is outside the | |
3bdb7a0a | 1867 | range LOWER_BOUND to LOWER_BOUND + RANGE - 1. */ |
96fb1e39 | 1868 | |
3bdb7a0a | 1869 | void |
3aed9a8d | 1870 | xstormy16_expand_casesi (rtx index, rtx lower_bound, rtx range, |
1871 | rtx table, rtx default_label) | |
96fb1e39 | 1872 | { |
1873 | HOST_WIDE_INT range_i = INTVAL (range); | |
1874 | rtx int_index; | |
1875 | ||
1876 | /* This code uses 'br', so it can deal only with tables of size up to | |
1877 | 8192 entries. */ | |
1878 | if (range_i >= 8192) | |
3bdb7a0a | 1879 | sorry ("switch statement of size %lu entries too large", |
96fb1e39 | 1880 | (unsigned long) range_i); |
1881 | ||
382e2d29 | 1882 | index = expand_binop (SImode, sub_optab, index, lower_bound, NULL_RTX, 0, |
96fb1e39 | 1883 | OPTAB_LIB_WIDEN); |
1884 | emit_cmp_and_jump_insns (index, range, GTU, NULL_RTX, SImode, 1, | |
ac6d7fed | 1885 | default_label); |
96fb1e39 | 1886 | int_index = gen_lowpart_common (HImode, index); |
bcd9bd66 | 1887 | emit_insn (gen_ashlhi3 (int_index, int_index, const2_rtx)); |
96fb1e39 | 1888 | emit_jump_insn (gen_tablejump_pcrel (int_index, table)); |
1889 | } | |
1890 | ||
1891 | /* Output an ADDR_VEC. It is output as a sequence of 'jmpf' | |
1892 | instructions, without label or alignment or any other special | |
1893 | constructs. We know that the previous instruction will be the | |
1894 | `tablejump_pcrel' output above. | |
1895 | ||
1896 | TODO: it might be nice to output 'br' instructions if they could | |
1897 | all reach. */ | |
1898 | ||
1899 | void | |
3aed9a8d | 1900 | xstormy16_output_addr_vec (FILE *file, rtx label ATTRIBUTE_UNUSED, rtx table) |
3bdb7a0a | 1901 | { |
96fb1e39 | 1902 | int vlen, idx; |
3bdb7a0a | 1903 | |
2f14b1f9 | 1904 | switch_to_section (current_function_section ()); |
96fb1e39 | 1905 | |
1906 | vlen = XVECLEN (table, 0); | |
1907 | for (idx = 0; idx < vlen; idx++) | |
1908 | { | |
1909 | fputs ("\tjmpf ", file); | |
633beede | 1910 | output_asm_label (XEXP (XVECEXP (table, 0, idx), 0)); |
96fb1e39 | 1911 | fputc ('\n', file); |
1912 | } | |
1913 | } | |
96fb1e39 | 1914 | \f |
1915 | /* Expander for the `call' patterns. | |
899fa8d2 | 1916 | RETVAL is the RTL for the return register or NULL for void functions. |
1917 | DEST is the function to call, expressed as a MEM. | |
1918 | COUNTER is ignored. */ | |
96fb1e39 | 1919 | |
3bdb7a0a | 1920 | void |
3aed9a8d | 1921 | xstormy16_expand_call (rtx retval, rtx dest, rtx counter) |
96fb1e39 | 1922 | { |
1923 | rtx call, temp; | |
1924 | enum machine_mode mode; | |
1925 | ||
899fa8d2 | 1926 | gcc_assert (MEM_P (dest)); |
96fb1e39 | 1927 | dest = XEXP (dest, 0); |
1928 | ||
899fa8d2 | 1929 | if (! CONSTANT_P (dest) && ! REG_P (dest)) |
96fb1e39 | 1930 | dest = force_reg (Pmode, dest); |
3bdb7a0a | 1931 | |
96fb1e39 | 1932 | if (retval == NULL) |
1933 | mode = VOIDmode; | |
1934 | else | |
1935 | mode = GET_MODE (retval); | |
1936 | ||
1937 | call = gen_rtx_CALL (mode, gen_rtx_MEM (FUNCTION_MODE, dest), | |
1938 | counter); | |
1939 | if (retval) | |
1940 | call = gen_rtx_SET (VOIDmode, retval, call); | |
3bdb7a0a | 1941 | |
96fb1e39 | 1942 | if (! CONSTANT_P (dest)) |
1943 | { | |
1944 | temp = gen_reg_rtx (HImode); | |
1945 | emit_move_insn (temp, const0_rtx); | |
1946 | } | |
1947 | else | |
1948 | temp = const0_rtx; | |
3bdb7a0a | 1949 | |
1950 | call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, | |
96fb1e39 | 1951 | gen_rtx_USE (VOIDmode, temp))); |
1952 | emit_call_insn (call); | |
1953 | } | |
1954 | \f | |
1955 | /* Expanders for multiword computational operations. */ | |
1956 | ||
1957 | /* Expander for arithmetic operations; emit insns to compute | |
1958 | ||
1959 | (set DEST (CODE:MODE SRC0 SRC1)) | |
3bdb7a0a | 1960 | |
247d6784 | 1961 | When CODE is COMPARE, a branch template is generated |
1962 | (this saves duplicating code in xstormy16_split_cbranch). */ | |
96fb1e39 | 1963 | |
3bdb7a0a | 1964 | void |
3aed9a8d | 1965 | xstormy16_expand_arith (enum machine_mode mode, enum rtx_code code, |
247d6784 | 1966 | rtx dest, rtx src0, rtx src1) |
96fb1e39 | 1967 | { |
1968 | int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; | |
1969 | int i; | |
1970 | int firstloop = 1; | |
1971 | ||
1972 | if (code == NEG) | |
aeb91dea | 1973 | emit_move_insn (src0, const0_rtx); |
3bdb7a0a | 1974 | |
96fb1e39 | 1975 | for (i = 0; i < num_words; i++) |
1976 | { | |
1977 | rtx w_src0, w_src1, w_dest; | |
1978 | rtx insn; | |
3bdb7a0a | 1979 | |
1980 | w_src0 = simplify_gen_subreg (word_mode, src0, mode, | |
aeb91dea | 1981 | i * UNITS_PER_WORD); |
96fb1e39 | 1982 | w_src1 = simplify_gen_subreg (word_mode, src1, mode, i * UNITS_PER_WORD); |
1983 | w_dest = simplify_gen_subreg (word_mode, dest, mode, i * UNITS_PER_WORD); | |
1984 | ||
1985 | switch (code) | |
1986 | { | |
1987 | case PLUS: | |
1988 | if (firstloop | |
899fa8d2 | 1989 | && CONST_INT_P (w_src1) |
1990 | && INTVAL (w_src1) == 0) | |
96fb1e39 | 1991 | continue; |
3bdb7a0a | 1992 | |
96fb1e39 | 1993 | if (firstloop) |
247d6784 | 1994 | insn = gen_addchi4 (w_dest, w_src0, w_src1); |
96fb1e39 | 1995 | else |
247d6784 | 1996 | insn = gen_addchi5 (w_dest, w_src0, w_src1); |
96fb1e39 | 1997 | break; |
1998 | ||
1999 | case NEG: | |
2000 | case MINUS: | |
2001 | case COMPARE: | |
2002 | if (code == COMPARE && i == num_words - 1) | |
2003 | { | |
2004 | rtx branch, sub, clobber, sub_1; | |
3bdb7a0a | 2005 | |
2006 | sub_1 = gen_rtx_MINUS (HImode, w_src0, | |
f6af892b | 2007 | gen_rtx_ZERO_EXTEND (HImode, gen_rtx_REG (BImode, CARRY_REGNUM))); |
96fb1e39 | 2008 | sub = gen_rtx_SET (VOIDmode, w_dest, |
2009 | gen_rtx_MINUS (HImode, sub_1, w_src1)); | |
f6af892b | 2010 | clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); |
96fb1e39 | 2011 | branch = gen_rtx_SET (VOIDmode, pc_rtx, |
2012 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
2013 | gen_rtx_EQ (HImode, | |
2014 | sub_1, | |
2015 | w_src1), | |
2016 | pc_rtx, | |
2017 | pc_rtx)); | |
2018 | insn = gen_rtx_PARALLEL (VOIDmode, | |
2019 | gen_rtvec (3, branch, sub, clobber)); | |
2020 | } | |
2021 | else if (firstloop | |
2022 | && code != COMPARE | |
899fa8d2 | 2023 | && CONST_INT_P (w_src1) |
2024 | && INTVAL (w_src1) == 0) | |
96fb1e39 | 2025 | continue; |
2026 | else if (firstloop) | |
247d6784 | 2027 | insn = gen_subchi4 (w_dest, w_src0, w_src1); |
96fb1e39 | 2028 | else |
247d6784 | 2029 | insn = gen_subchi5 (w_dest, w_src0, w_src1); |
96fb1e39 | 2030 | break; |
2031 | ||
2032 | case IOR: | |
2033 | case XOR: | |
2034 | case AND: | |
899fa8d2 | 2035 | if (CONST_INT_P (w_src1) |
96fb1e39 | 2036 | && INTVAL (w_src1) == -(code == AND)) |
2037 | continue; | |
3bdb7a0a | 2038 | |
29bb088d | 2039 | insn = gen_rtx_SET (VOIDmode, w_dest, gen_rtx_fmt_ee (code, mode, |
dc55b8a9 | 2040 | w_src0, w_src1)); |
96fb1e39 | 2041 | break; |
2042 | ||
2043 | case NOT: | |
2044 | insn = gen_rtx_SET (VOIDmode, w_dest, gen_rtx_NOT (mode, w_src0)); | |
2045 | break; | |
2046 | ||
2047 | default: | |
73dcc01f | 2048 | gcc_unreachable (); |
96fb1e39 | 2049 | } |
3bdb7a0a | 2050 | |
96fb1e39 | 2051 | firstloop = 0; |
2052 | emit (insn); | |
2053 | } | |
9e1f4e74 | 2054 | |
2055 | /* If we emit nothing, try_split() will think we failed. So emit | |
2056 | something that does nothing and can be optimized away. */ | |
2057 | if (firstloop) | |
2058 | emit (gen_nop ()); | |
96fb1e39 | 2059 | } |
2060 | ||
96fb1e39 | 2061 | /* The shift operations are split at output time for constant values; |
3bdb7a0a | 2062 | variable-width shifts get handed off to a library routine. |
96fb1e39 | 2063 | |
2064 | Generate an output string to do (set X (CODE:MODE X SIZE_R)) | |
2065 | SIZE_R will be a CONST_INT, X will be a hard register. */ | |
2066 | ||
3bdb7a0a | 2067 | const char * |
3aed9a8d | 2068 | xstormy16_output_shift (enum machine_mode mode, enum rtx_code code, |
2069 | rtx x, rtx size_r, rtx temp) | |
96fb1e39 | 2070 | { |
2071 | HOST_WIDE_INT size; | |
2072 | const char *r0, *r1, *rt; | |
2073 | static char r[64]; | |
2074 | ||
899fa8d2 | 2075 | gcc_assert (CONST_INT_P (size_r) |
2076 | && REG_P (x) | |
2077 | && mode == SImode); | |
2078 | ||
96fb1e39 | 2079 | size = INTVAL (size_r) & (GET_MODE_BITSIZE (mode) - 1); |
2080 | ||
2081 | if (size == 0) | |
2082 | return ""; | |
2083 | ||
2084 | r0 = reg_names [REGNO (x)]; | |
2085 | r1 = reg_names [REGNO (x) + 1]; | |
96fb1e39 | 2086 | |
2087 | /* For shifts of size 1, we can use the rotate instructions. */ | |
2088 | if (size == 1) | |
2089 | { | |
2090 | switch (code) | |
2091 | { | |
2092 | case ASHIFT: | |
2093 | sprintf (r, "shl %s,#1 | rlc %s,#1", r0, r1); | |
2094 | break; | |
2095 | case ASHIFTRT: | |
2096 | sprintf (r, "asr %s,#1 | rrc %s,#1", r1, r0); | |
2097 | break; | |
2098 | case LSHIFTRT: | |
2099 | sprintf (r, "shr %s,#1 | rrc %s,#1", r1, r0); | |
2100 | break; | |
2101 | default: | |
73dcc01f | 2102 | gcc_unreachable (); |
96fb1e39 | 2103 | } |
2104 | return r; | |
2105 | } | |
3bdb7a0a | 2106 | |
96fb1e39 | 2107 | /* For large shifts, there are easy special cases. */ |
2108 | if (size == 16) | |
2109 | { | |
2110 | switch (code) | |
2111 | { | |
2112 | case ASHIFT: | |
2113 | sprintf (r, "mov %s,%s | mov %s,#0", r1, r0, r0); | |
2114 | break; | |
2115 | case ASHIFTRT: | |
2116 | sprintf (r, "mov %s,%s | asr %s,#15", r0, r1, r1); | |
2117 | break; | |
2118 | case LSHIFTRT: | |
2119 | sprintf (r, "mov %s,%s | mov %s,#0", r0, r1, r1); | |
2120 | break; | |
2121 | default: | |
73dcc01f | 2122 | gcc_unreachable (); |
96fb1e39 | 2123 | } |
2124 | return r; | |
2125 | } | |
2126 | if (size > 16) | |
2127 | { | |
2128 | switch (code) | |
2129 | { | |
2130 | case ASHIFT: | |
3bdb7a0a | 2131 | sprintf (r, "mov %s,%s | mov %s,#0 | shl %s,#%d", |
96fb1e39 | 2132 | r1, r0, r0, r1, (int) size - 16); |
2133 | break; | |
2134 | case ASHIFTRT: | |
3bdb7a0a | 2135 | sprintf (r, "mov %s,%s | asr %s,#15 | asr %s,#%d", |
96fb1e39 | 2136 | r0, r1, r1, r0, (int) size - 16); |
2137 | break; | |
2138 | case LSHIFTRT: | |
3bdb7a0a | 2139 | sprintf (r, "mov %s,%s | mov %s,#0 | shr %s,#%d", |
96fb1e39 | 2140 | r0, r1, r1, r0, (int) size - 16); |
2141 | break; | |
2142 | default: | |
73dcc01f | 2143 | gcc_unreachable (); |
96fb1e39 | 2144 | } |
2145 | return r; | |
2146 | } | |
2147 | ||
2148 | /* For the rest, we have to do more work. In particular, we | |
2149 | need a temporary. */ | |
c71bbf38 | 2150 | rt = reg_names [REGNO (temp)]; |
96fb1e39 | 2151 | switch (code) |
2152 | { | |
2153 | case ASHIFT: | |
3bdb7a0a | 2154 | sprintf (r, |
2155 | "mov %s,%s | shl %s,#%d | shl %s,#%d | shr %s,#%d | or %s,%s", | |
2156 | rt, r0, r0, (int) size, r1, (int) size, rt, (int) (16 - size), | |
96fb1e39 | 2157 | r1, rt); |
2158 | break; | |
2159 | case ASHIFTRT: | |
3bdb7a0a | 2160 | sprintf (r, |
2161 | "mov %s,%s | asr %s,#%d | shr %s,#%d | shl %s,#%d | or %s,%s", | |
2162 | rt, r1, r1, (int) size, r0, (int) size, rt, (int) (16 - size), | |
96fb1e39 | 2163 | r0, rt); |
2164 | break; | |
2165 | case LSHIFTRT: | |
3bdb7a0a | 2166 | sprintf (r, |
2167 | "mov %s,%s | shr %s,#%d | shr %s,#%d | shl %s,#%d | or %s,%s", | |
2168 | rt, r1, r1, (int) size, r0, (int) size, rt, (int) (16 - size), | |
96fb1e39 | 2169 | r0, rt); |
2170 | break; | |
2171 | default: | |
73dcc01f | 2172 | gcc_unreachable (); |
96fb1e39 | 2173 | } |
2174 | return r; | |
2175 | } | |
2176 | \f | |
2177 | /* Attribute handling. */ | |
2178 | ||
2179 | /* Return nonzero if the function is an interrupt function. */ | |
3bdb7a0a | 2180 | |
96fb1e39 | 2181 | int |
3aed9a8d | 2182 | xstormy16_interrupt_function_p (void) |
96fb1e39 | 2183 | { |
2184 | tree attributes; | |
3bdb7a0a | 2185 | |
96fb1e39 | 2186 | /* The dwarf2 mechanism asks for INCOMING_FRAME_SP_OFFSET before |
2187 | any functions are declared, which is demonstrably wrong, but | |
2188 | it is worked around here. FIXME. */ | |
2189 | if (!cfun) | |
2190 | return 0; | |
2191 | ||
2192 | attributes = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)); | |
2193 | return lookup_attribute ("interrupt", attributes) != NULL_TREE; | |
2194 | } | |
2195 | ||
3bdb7a0a | 2196 | #undef TARGET_ATTRIBUTE_TABLE |
2197 | #define TARGET_ATTRIBUTE_TABLE xstormy16_attribute_table | |
2198 | ||
3aed9a8d | 2199 | static tree xstormy16_handle_interrupt_attribute |
2200 | (tree *, tree, tree, int, bool *); | |
3c1df5aa | 2201 | static tree xstormy16_handle_below100_attribute |
2202 | (tree *, tree, tree, int, bool *); | |
3aed9a8d | 2203 | |
dddb37d8 | 2204 | static const struct attribute_spec xstormy16_attribute_table[] = |
e3c541f0 | 2205 | { |
ac86af5d | 2206 | /* name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
2207 | affects_type_identity. */ | |
2208 | { "interrupt", 0, 0, false, true, true, | |
2209 | xstormy16_handle_interrupt_attribute , false }, | |
2210 | { "BELOW100", 0, 0, false, false, false, | |
2211 | xstormy16_handle_below100_attribute, false }, | |
2212 | { "below100", 0, 0, false, false, false, | |
2213 | xstormy16_handle_below100_attribute, false }, | |
2214 | { NULL, 0, 0, false, false, false, NULL, false } | |
e3c541f0 | 2215 | }; |
2216 | ||
2217 | /* Handle an "interrupt" attribute; | |
2218 | arguments as in struct attribute_spec.handler. */ | |
3bdb7a0a | 2219 | |
e3c541f0 | 2220 | static tree |
3aed9a8d | 2221 | xstormy16_handle_interrupt_attribute (tree *node, tree name, |
2222 | tree args ATTRIBUTE_UNUSED, | |
2223 | int flags ATTRIBUTE_UNUSED, | |
2224 | bool *no_add_attrs) | |
96fb1e39 | 2225 | { |
e3c541f0 | 2226 | if (TREE_CODE (*node) != FUNCTION_TYPE) |
2227 | { | |
67a779df | 2228 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
2229 | name); | |
e3c541f0 | 2230 | *no_add_attrs = true; |
2231 | } | |
96fb1e39 | 2232 | |
e3c541f0 | 2233 | return NULL_TREE; |
96fb1e39 | 2234 | } |
3c1df5aa | 2235 | |
2236 | /* Handle an "below" attribute; | |
2237 | arguments as in struct attribute_spec.handler. */ | |
3bdb7a0a | 2238 | |
3c1df5aa | 2239 | static tree |
2240 | xstormy16_handle_below100_attribute (tree *node, | |
2241 | tree name ATTRIBUTE_UNUSED, | |
2242 | tree args ATTRIBUTE_UNUSED, | |
2243 | int flags ATTRIBUTE_UNUSED, | |
2244 | bool *no_add_attrs) | |
2245 | { | |
2246 | if (TREE_CODE (*node) != VAR_DECL | |
2247 | && TREE_CODE (*node) != POINTER_TYPE | |
2248 | && TREE_CODE (*node) != TYPE_DECL) | |
2249 | { | |
9b2d6d13 | 2250 | warning (OPT_Wattributes, |
2251 | "%<__BELOW100__%> attribute only applies to variables"); | |
3c1df5aa | 2252 | *no_add_attrs = true; |
2253 | } | |
2254 | else if (args == NULL_TREE && TREE_CODE (*node) == VAR_DECL) | |
2255 | { | |
2256 | if (! (TREE_PUBLIC (*node) || TREE_STATIC (*node))) | |
2257 | { | |
9b2d6d13 | 2258 | warning (OPT_Wattributes, "__BELOW100__ attribute not allowed " |
0a81f5a0 | 2259 | "with auto storage class"); |
3c1df5aa | 2260 | *no_add_attrs = true; |
2261 | } | |
2262 | } | |
3bdb7a0a | 2263 | |
3c1df5aa | 2264 | return NULL_TREE; |
2265 | } | |
537da7d2 | 2266 | \f |
3bdb7a0a | 2267 | #undef TARGET_INIT_BUILTINS |
2268 | #define TARGET_INIT_BUILTINS xstormy16_init_builtins | |
2269 | #undef TARGET_EXPAND_BUILTIN | |
2270 | #define TARGET_EXPAND_BUILTIN xstormy16_expand_builtin | |
2271 | ||
2272 | static struct | |
2273 | { | |
2274 | const char * name; | |
2275 | int md_code; | |
2276 | const char * arg_ops; /* 0..9, t for temp register, r for return value. */ | |
2277 | const char * arg_types; /* s=short,l=long, upper case for unsigned. */ | |
2278 | } | |
2279 | s16builtins[] = | |
2280 | { | |
537da7d2 | 2281 | { "__sdivlh", CODE_FOR_sdivlh, "rt01", "sls" }, |
2282 | { "__smodlh", CODE_FOR_sdivlh, "tr01", "sls" }, | |
2283 | { "__udivlh", CODE_FOR_udivlh, "rt01", "SLS" }, | |
2284 | { "__umodlh", CODE_FOR_udivlh, "tr01", "SLS" }, | |
3bdb7a0a | 2285 | { NULL, 0, NULL, NULL } |
537da7d2 | 2286 | }; |
2287 | ||
2288 | static void | |
3aed9a8d | 2289 | xstormy16_init_builtins (void) |
537da7d2 | 2290 | { |
2a3cbbd4 | 2291 | tree args[2], ret_type, arg = NULL_TREE, ftype; |
2292 | int i, a, n_args; | |
537da7d2 | 2293 | |
2294 | ret_type = void_type_node; | |
2295 | ||
3bdb7a0a | 2296 | for (i = 0; s16builtins[i].name; i++) |
537da7d2 | 2297 | { |
2a3cbbd4 | 2298 | n_args = strlen (s16builtins[i].arg_types) - 1; |
2299 | ||
2300 | gcc_assert (n_args <= (int) ARRAY_SIZE (args)); | |
2301 | ||
89a2af15 | 2302 | for (a = n_args - 1; a >= 0; a--) |
2a3cbbd4 | 2303 | args[a] = NULL_TREE; |
2304 | ||
2305 | for (a = n_args; a >= 0; a--) | |
537da7d2 | 2306 | { |
2307 | switch (s16builtins[i].arg_types[a]) | |
2308 | { | |
2309 | case 's': arg = short_integer_type_node; break; | |
2310 | case 'S': arg = short_unsigned_type_node; break; | |
2311 | case 'l': arg = long_integer_type_node; break; | |
2312 | case 'L': arg = long_unsigned_type_node; break; | |
73dcc01f | 2313 | default: gcc_unreachable (); |
537da7d2 | 2314 | } |
2315 | if (a == 0) | |
2316 | ret_type = arg; | |
2317 | else | |
2a3cbbd4 | 2318 | args[a-1] = arg; |
537da7d2 | 2319 | } |
89a2af15 | 2320 | ftype = build_function_type_list (ret_type, args[0], args[1], NULL_TREE); |
2a3cbbd4 | 2321 | add_builtin_function (s16builtins[i].name, ftype, |
89a2af15 | 2322 | i, BUILT_IN_MD, NULL, NULL_TREE); |
537da7d2 | 2323 | } |
2324 | } | |
2325 | ||
2326 | static rtx | |
bcf954af | 2327 | xstormy16_expand_builtin (tree exp, rtx target, |
2328 | rtx subtarget ATTRIBUTE_UNUSED, | |
2329 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
2330 | int ignore ATTRIBUTE_UNUSED) | |
537da7d2 | 2331 | { |
2332 | rtx op[10], args[10], pat, copyto[10], retval = 0; | |
2333 | tree fndecl, argtree; | |
2334 | int i, a, o, code; | |
2335 | ||
2336 | fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
2337 | argtree = TREE_OPERAND (exp, 1); | |
2338 | i = DECL_FUNCTION_CODE (fndecl); | |
2339 | code = s16builtins[i].md_code; | |
2340 | ||
2341 | for (a = 0; a < 10 && argtree; a++) | |
2342 | { | |
e53bb401 | 2343 | args[a] = expand_normal (TREE_VALUE (argtree)); |
537da7d2 | 2344 | argtree = TREE_CHAIN (argtree); |
2345 | } | |
2346 | ||
2347 | for (o = 0; s16builtins[i].arg_ops[o]; o++) | |
2348 | { | |
2349 | char ao = s16builtins[i].arg_ops[o]; | |
2350 | char c = insn_data[code].operand[o].constraint[0]; | |
e53bb401 | 2351 | enum machine_mode omode; |
537da7d2 | 2352 | |
2353 | copyto[o] = 0; | |
2354 | ||
e53bb401 | 2355 | omode = (enum machine_mode) insn_data[code].operand[o].mode; |
537da7d2 | 2356 | if (ao == 'r') |
2357 | op[o] = target ? target : gen_reg_rtx (omode); | |
2358 | else if (ao == 't') | |
2359 | op[o] = gen_reg_rtx (omode); | |
2360 | else | |
2361 | op[o] = args[(int) hex_value (ao)]; | |
2362 | ||
2363 | if (! (*insn_data[code].operand[o].predicate) (op[o], GET_MODE (op[o]))) | |
2364 | { | |
2365 | if (c == '+' || c == '=') | |
2366 | { | |
2367 | copyto[o] = op[o]; | |
2368 | op[o] = gen_reg_rtx (omode); | |
2369 | } | |
2370 | else | |
2371 | op[o] = copy_to_mode_reg (omode, op[o]); | |
2372 | } | |
2373 | ||
2374 | if (ao == 'r') | |
2375 | retval = op[o]; | |
2376 | } | |
2377 | ||
2378 | pat = GEN_FCN (code) (op[0], op[1], op[2], op[3], op[4], | |
2379 | op[5], op[6], op[7], op[8], op[9]); | |
2380 | emit_insn (pat); | |
2381 | ||
2382 | for (o = 0; s16builtins[i].arg_ops[o]; o++) | |
2383 | if (copyto[o]) | |
2384 | { | |
2385 | emit_move_insn (copyto[o], op[o]); | |
2386 | if (op[o] == retval) | |
2387 | retval = copyto[o]; | |
2388 | } | |
2389 | ||
2390 | return retval; | |
2391 | } | |
3c1df5aa | 2392 | \f |
3c1df5aa | 2393 | /* Look for combinations of insns that can be converted to BN or BP |
2394 | opcodes. This is, unfortunately, too complex to do with MD | |
2395 | patterns. */ | |
3bdb7a0a | 2396 | |
3c1df5aa | 2397 | static void |
91a55c11 | 2398 | combine_bnp (rtx_insn *insn) |
3c1df5aa | 2399 | { |
0784ecd8 | 2400 | int insn_code, regno, need_extend; |
2401 | unsigned int mask; | |
ed3e6e5d | 2402 | rtx cond, reg, qireg, mem; |
2403 | rtx_insn *and_insn, *load; | |
3c1df5aa | 2404 | enum machine_mode load_mode = QImode; |
0784ecd8 | 2405 | enum machine_mode and_mode = QImode; |
ed3e6e5d | 2406 | rtx_insn *shift = NULL; |
3c1df5aa | 2407 | |
2408 | insn_code = recog_memoized (insn); | |
2409 | if (insn_code != CODE_FOR_cbranchhi | |
2410 | && insn_code != CODE_FOR_cbranchhi_neg) | |
2411 | return; | |
2412 | ||
2413 | cond = XVECEXP (PATTERN (insn), 0, 0); /* set */ | |
2414 | cond = XEXP (cond, 1); /* if */ | |
2415 | cond = XEXP (cond, 0); /* cond */ | |
2416 | switch (GET_CODE (cond)) | |
2417 | { | |
2418 | case NE: | |
2419 | case EQ: | |
2420 | need_extend = 0; | |
2421 | break; | |
2422 | case LT: | |
2423 | case GE: | |
2424 | need_extend = 1; | |
2425 | break; | |
2426 | default: | |
2427 | return; | |
2428 | } | |
2429 | ||
2430 | reg = XEXP (cond, 0); | |
899fa8d2 | 2431 | if (! REG_P (reg)) |
3c1df5aa | 2432 | return; |
2433 | regno = REGNO (reg); | |
2434 | if (XEXP (cond, 1) != const0_rtx) | |
2435 | return; | |
2436 | if (! find_regno_note (insn, REG_DEAD, regno)) | |
2437 | return; | |
2438 | qireg = gen_rtx_REG (QImode, regno); | |
2439 | ||
2440 | if (need_extend) | |
2441 | { | |
77aa6362 | 2442 | /* LT and GE conditionals should have a sign extend before |
3c1df5aa | 2443 | them. */ |
89a2af15 | 2444 | for (and_insn = prev_real_insn (insn); |
2445 | and_insn != NULL_RTX; | |
e53bb401 | 2446 | and_insn = prev_real_insn (and_insn)) |
3c1df5aa | 2447 | { |
e53bb401 | 2448 | int and_code = recog_memoized (and_insn); |
0784ecd8 | 2449 | |
3c1df5aa | 2450 | if (and_code == CODE_FOR_extendqihi2 |
e53bb401 | 2451 | && rtx_equal_p (SET_DEST (PATTERN (and_insn)), reg) |
2452 | && rtx_equal_p (XEXP (SET_SRC (PATTERN (and_insn)), 0), qireg)) | |
0784ecd8 | 2453 | break; |
3bdb7a0a | 2454 | |
3c1df5aa | 2455 | if (and_code == CODE_FOR_movhi_internal |
e53bb401 | 2456 | && rtx_equal_p (SET_DEST (PATTERN (and_insn)), reg)) |
3c1df5aa | 2457 | { |
2458 | /* This is for testing bit 15. */ | |
e53bb401 | 2459 | and_insn = insn; |
3c1df5aa | 2460 | break; |
2461 | } | |
2462 | ||
e53bb401 | 2463 | if (reg_mentioned_p (reg, and_insn)) |
3c1df5aa | 2464 | return; |
0784ecd8 | 2465 | |
aa90bb35 | 2466 | if (! NOTE_P (and_insn) && ! NONJUMP_INSN_P (and_insn)) |
3c1df5aa | 2467 | return; |
2468 | } | |
2469 | } | |
2470 | else | |
2471 | { | |
2472 | /* EQ and NE conditionals have an AND before them. */ | |
89a2af15 | 2473 | for (and_insn = prev_real_insn (insn); |
2474 | and_insn != NULL_RTX; | |
e53bb401 | 2475 | and_insn = prev_real_insn (and_insn)) |
3c1df5aa | 2476 | { |
e53bb401 | 2477 | if (recog_memoized (and_insn) == CODE_FOR_andhi3 |
2478 | && rtx_equal_p (SET_DEST (PATTERN (and_insn)), reg) | |
2479 | && rtx_equal_p (XEXP (SET_SRC (PATTERN (and_insn)), 0), reg)) | |
0784ecd8 | 2480 | break; |
3bdb7a0a | 2481 | |
e53bb401 | 2482 | if (reg_mentioned_p (reg, and_insn)) |
3c1df5aa | 2483 | return; |
0784ecd8 | 2484 | |
aa90bb35 | 2485 | if (! NOTE_P (and_insn) && ! NONJUMP_INSN_P (and_insn)) |
3c1df5aa | 2486 | return; |
2487 | } | |
0784ecd8 | 2488 | |
e53bb401 | 2489 | if (and_insn) |
0784ecd8 | 2490 | { |
06b27565 | 2491 | /* Some mis-optimizations by GCC can generate a RIGHT-SHIFT |
0784ecd8 | 2492 | followed by an AND like this: |
2493 | ||
2494 | (parallel [(set (reg:HI r7) (lshiftrt:HI (reg:HI r7) (const_int 3))) | |
2495 | (clobber (reg:BI carry))] | |
2496 | ||
2497 | (set (reg:HI r7) (and:HI (reg:HI r7) (const_int 1))) | |
3bdb7a0a | 2498 | |
0784ecd8 | 2499 | Attempt to detect this here. */ |
e53bb401 | 2500 | for (shift = prev_real_insn (and_insn); shift; |
2501 | shift = prev_real_insn (shift)) | |
0784ecd8 | 2502 | { |
2503 | if (recog_memoized (shift) == CODE_FOR_lshrhi3 | |
2504 | && rtx_equal_p (SET_DEST (XVECEXP (PATTERN (shift), 0, 0)), reg) | |
2505 | && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (shift), 0, 0)), 0), reg)) | |
2506 | break; | |
3bdb7a0a | 2507 | |
0784ecd8 | 2508 | if (reg_mentioned_p (reg, shift) |
aa90bb35 | 2509 | || (! NOTE_P (shift) && ! NONJUMP_INSN_P (shift))) |
0784ecd8 | 2510 | { |
ed3e6e5d | 2511 | shift = NULL; |
0784ecd8 | 2512 | break; |
2513 | } | |
2514 | } | |
2515 | } | |
3c1df5aa | 2516 | } |
89a2af15 | 2517 | |
2518 | if (and_insn == NULL_RTX) | |
3c1df5aa | 2519 | return; |
2520 | ||
e53bb401 | 2521 | for (load = shift ? prev_real_insn (shift) : prev_real_insn (and_insn); |
0784ecd8 | 2522 | load; |
2523 | load = prev_real_insn (load)) | |
3c1df5aa | 2524 | { |
2525 | int load_code = recog_memoized (load); | |
0784ecd8 | 2526 | |
3c1df5aa | 2527 | if (load_code == CODE_FOR_movhi_internal |
0784ecd8 | 2528 | && rtx_equal_p (SET_DEST (PATTERN (load)), reg) |
2529 | && xstormy16_below100_operand (SET_SRC (PATTERN (load)), HImode) | |
2530 | && ! MEM_VOLATILE_P (SET_SRC (PATTERN (load)))) | |
3c1df5aa | 2531 | { |
2532 | load_mode = HImode; | |
2533 | break; | |
2534 | } | |
2535 | ||
2536 | if (load_code == CODE_FOR_movqi_internal | |
0784ecd8 | 2537 | && rtx_equal_p (SET_DEST (PATTERN (load)), qireg) |
2538 | && xstormy16_below100_operand (SET_SRC (PATTERN (load)), QImode)) | |
3c1df5aa | 2539 | { |
2540 | load_mode = QImode; | |
2541 | break; | |
2542 | } | |
0784ecd8 | 2543 | |
2544 | if (load_code == CODE_FOR_zero_extendqihi2 | |
2545 | && rtx_equal_p (SET_DEST (PATTERN (load)), reg) | |
2546 | && xstormy16_below100_operand (XEXP (SET_SRC (PATTERN (load)), 0), QImode)) | |
2547 | { | |
2548 | load_mode = QImode; | |
2549 | and_mode = HImode; | |
2550 | break; | |
2551 | } | |
2552 | ||
3c1df5aa | 2553 | if (reg_mentioned_p (reg, load)) |
2554 | return; | |
0784ecd8 | 2555 | |
aa90bb35 | 2556 | if (! NOTE_P (load) && ! NONJUMP_INSN_P (load)) |
3c1df5aa | 2557 | return; |
2558 | } | |
2559 | if (!load) | |
2560 | return; | |
2561 | ||
0784ecd8 | 2562 | mem = SET_SRC (PATTERN (load)); |
2563 | ||
2564 | if (need_extend) | |
3c1df5aa | 2565 | { |
0784ecd8 | 2566 | mask = (load_mode == HImode) ? 0x8000 : 0x80; |
2567 | ||
2568 | /* If the mem includes a zero-extend operation and we are | |
2569 | going to generate a sign-extend operation then move the | |
2570 | mem inside the zero-extend. */ | |
2571 | if (GET_CODE (mem) == ZERO_EXTEND) | |
2572 | mem = XEXP (mem, 0); | |
3c1df5aa | 2573 | } |
2574 | else | |
0784ecd8 | 2575 | { |
e53bb401 | 2576 | if (!xstormy16_onebit_set_operand (XEXP (SET_SRC (PATTERN (and_insn)), 1), |
2577 | load_mode)) | |
0784ecd8 | 2578 | return; |
2579 | ||
e53bb401 | 2580 | mask = (int) INTVAL (XEXP (SET_SRC (PATTERN (and_insn)), 1)); |
0784ecd8 | 2581 | |
2582 | if (shift) | |
2583 | mask <<= INTVAL (XEXP (SET_SRC (XVECEXP (PATTERN (shift), 0, 0)), 1)); | |
2584 | } | |
3c1df5aa | 2585 | |
3c1df5aa | 2586 | if (load_mode == HImode) |
2587 | { | |
2588 | rtx addr = XEXP (mem, 0); | |
0784ecd8 | 2589 | |
3c1df5aa | 2590 | if (! (mask & 0xff)) |
2591 | { | |
29c05e22 | 2592 | addr = plus_constant (Pmode, addr, 1); |
3c1df5aa | 2593 | mask >>= 8; |
2594 | } | |
2595 | mem = gen_rtx_MEM (QImode, addr); | |
2596 | } | |
2597 | ||
2598 | if (need_extend) | |
2599 | XEXP (cond, 0) = gen_rtx_SIGN_EXTEND (HImode, mem); | |
2600 | else | |
0784ecd8 | 2601 | XEXP (cond, 0) = gen_rtx_AND (and_mode, mem, GEN_INT (mask)); |
2602 | ||
3c1df5aa | 2603 | INSN_CODE (insn) = -1; |
2604 | delete_insn (load); | |
0784ecd8 | 2605 | |
e53bb401 | 2606 | if (and_insn != insn) |
2607 | delete_insn (and_insn); | |
0784ecd8 | 2608 | |
2609 | if (shift != NULL_RTX) | |
2610 | delete_insn (shift); | |
3c1df5aa | 2611 | } |
2612 | ||
2613 | static void | |
2614 | xstormy16_reorg (void) | |
2615 | { | |
91a55c11 | 2616 | rtx_insn *insn; |
3c1df5aa | 2617 | |
2618 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
2619 | { | |
2620 | if (! JUMP_P (insn)) | |
2621 | continue; | |
2622 | combine_bnp (insn); | |
2623 | } | |
2624 | } | |
b4073628 | 2625 | \f |
39cc9599 | 2626 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
2627 | ||
b4073628 | 2628 | static bool |
fb80456a | 2629 | xstormy16_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
b4073628 | 2630 | { |
fb80456a | 2631 | const HOST_WIDE_INT size = int_size_in_bytes (type); |
39cc9599 | 2632 | return (size == -1 || size > UNITS_PER_WORD * NUM_ARGUMENT_REGISTERS); |
b4073628 | 2633 | } |
96fb1e39 | 2634 | \f |
3bdb7a0a | 2635 | #undef TARGET_ASM_ALIGNED_HI_OP |
58356836 | 2636 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" |
3bdb7a0a | 2637 | #undef TARGET_ASM_ALIGNED_SI_OP |
58356836 | 2638 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" |
3bdb7a0a | 2639 | #undef TARGET_ENCODE_SECTION_INFO |
3c1df5aa | 2640 | #define TARGET_ENCODE_SECTION_INFO xstormy16_encode_section_info |
58356836 | 2641 | |
3bdb7a0a | 2642 | /* Select_section doesn't handle .bss_below100. */ |
102e3995 | 2643 | #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS |
2644 | #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS false | |
2645 | ||
3bdb7a0a | 2646 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
6988553d | 2647 | #define TARGET_ASM_OUTPUT_MI_THUNK xstormy16_asm_output_mi_thunk |
3bdb7a0a | 2648 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
eb344f43 | 2649 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall |
6988553d | 2650 | |
3d451f7c | 2651 | #undef TARGET_PRINT_OPERAND |
2652 | #define TARGET_PRINT_OPERAND xstormy16_print_operand | |
2653 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
2654 | #define TARGET_PRINT_OPERAND_ADDRESS xstormy16_print_operand_address | |
2655 | ||
f9fd3680 | 2656 | #undef TARGET_MEMORY_MOVE_COST |
2657 | #define TARGET_MEMORY_MOVE_COST xstormy16_memory_move_cost | |
3bdb7a0a | 2658 | #undef TARGET_RTX_COSTS |
fab7adbf | 2659 | #define TARGET_RTX_COSTS xstormy16_rtx_costs |
3bdb7a0a | 2660 | #undef TARGET_ADDRESS_COST |
ec0457a8 | 2661 | #define TARGET_ADDRESS_COST xstormy16_address_cost |
fab7adbf | 2662 | |
3bdb7a0a | 2663 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
5fb9750f | 2664 | #define TARGET_BUILD_BUILTIN_VA_LIST xstormy16_build_builtin_va_list |
3bdb7a0a | 2665 | #undef TARGET_EXPAND_BUILTIN_VA_START |
8a58ed0a | 2666 | #define TARGET_EXPAND_BUILTIN_VA_START xstormy16_expand_builtin_va_start |
3bdb7a0a | 2667 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
bcf954af | 2668 | #define TARGET_GIMPLIFY_VA_ARG_EXPR xstormy16_gimplify_va_arg_expr |
89176bdb | 2669 | |
3b2411a8 | 2670 | #undef TARGET_PROMOTE_FUNCTION_MODE |
2671 | #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote | |
3bdb7a0a | 2672 | #undef TARGET_PROMOTE_PROTOTYPES |
fb80456a | 2673 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
b4073628 | 2674 | |
ee2f4146 | 2675 | #undef TARGET_FUNCTION_ARG |
2676 | #define TARGET_FUNCTION_ARG xstormy16_function_arg | |
2677 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
2678 | #define TARGET_FUNCTION_ARG_ADVANCE xstormy16_function_arg_advance | |
2679 | ||
3bdb7a0a | 2680 | #undef TARGET_RETURN_IN_MEMORY |
b4073628 | 2681 | #define TARGET_RETURN_IN_MEMORY xstormy16_return_in_memory |
65bf7507 | 2682 | #undef TARGET_FUNCTION_VALUE |
2683 | #define TARGET_FUNCTION_VALUE xstormy16_function_value | |
2684 | #undef TARGET_LIBCALL_VALUE | |
2685 | #define TARGET_LIBCALL_VALUE xstormy16_libcall_value | |
2686 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
2687 | #define TARGET_FUNCTION_VALUE_REGNO_P xstormy16_function_value_regno_p | |
b4073628 | 2688 | |
3bdb7a0a | 2689 | #undef TARGET_MACHINE_DEPENDENT_REORG |
3c1df5aa | 2690 | #define TARGET_MACHINE_DEPENDENT_REORG xstormy16_reorg |
2691 | ||
8fe62af3 | 2692 | #undef TARGET_PREFERRED_RELOAD_CLASS |
2693 | #define TARGET_PREFERRED_RELOAD_CLASS xstormy16_preferred_reload_class | |
2694 | #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS | |
2695 | #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS xstormy16_preferred_reload_class | |
2696 | ||
fd50b071 | 2697 | #undef TARGET_LEGITIMATE_ADDRESS_P |
2698 | #define TARGET_LEGITIMATE_ADDRESS_P xstormy16_legitimate_address_p | |
e53c7df3 | 2699 | #undef TARGET_MODE_DEPENDENT_ADDRESS_P |
2700 | #define TARGET_MODE_DEPENDENT_ADDRESS_P xstormy16_mode_dependent_address_p | |
fd50b071 | 2701 | |
cd90919d | 2702 | #undef TARGET_CAN_ELIMINATE |
2703 | #define TARGET_CAN_ELIMINATE xstormy16_can_eliminate | |
2704 | ||
cb9cec17 | 2705 | #undef TARGET_TRAMPOLINE_INIT |
2706 | #define TARGET_TRAMPOLINE_INIT xstormy16_trampoline_init | |
2707 | ||
96fb1e39 | 2708 | struct gcc_target targetm = TARGET_INITIALIZER; |
2f14b1f9 | 2709 | |
2710 | #include "gt-stormy16.h" |