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c6243b4c | 1 | /* Xstormy16 cpu description. |
cf7442bb | 2 | Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2007, |
192997cf | 3 | 2008, 2009, 2010, 2011 Free Software Foundation, Inc. |
4b58290f GK |
4 | Contributed by Red Hat, Inc. |
5 | ||
038eab67 | 6 | This file is part of GCC. |
4b58290f | 7 | |
038eab67 NC |
8 | GCC is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
4b58290f | 12 | |
038eab67 NC |
13 | GCC is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
4b58290f | 17 | |
038eab67 NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
4b58290f | 21 | |
4b58290f | 22 | \f |
038eab67 | 23 | /* Driver configuration. */ |
4b58290f | 24 | |
038eab67 | 25 | #undef ASM_SPEC |
322fe6e1 | 26 | #define ASM_SPEC "" |
4b58290f | 27 | |
5519175f JM |
28 | #undef LINK_SPEC |
29 | #define LINK_SPEC "%{h*} %{v:-V} \ | |
30 | %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}" | |
31 | ||
d1552d7b | 32 | /* For xstormy16: |
3eaaf577 GK |
33 | - If -msim is specified, everything is built and linked as for the sim. |
34 | - If -T is specified, that linker script is used, and it should provide | |
35 | appropriate libraries. | |
36 | - If neither is specified, everything is built as for the sim, but no | |
038eab67 NC |
37 | I/O support is assumed. */ |
38 | #undef LIB_SPEC | |
3eaaf577 | 39 | #define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:%{!T*:-lnosys}} -)" |
4b58290f | 40 | |
038eab67 | 41 | #undef STARTFILE_SPEC |
4b58290f GK |
42 | #define STARTFILE_SPEC "crt0.o%s crti.o%s crtbegin.o%s" |
43 | ||
038eab67 | 44 | #undef ENDFILE_SPEC |
4b58290f GK |
45 | #define ENDFILE_SPEC "crtend.o%s crtn.o%s" |
46 | ||
4b58290f | 47 | \f |
038eab67 | 48 | /* Run-time target specifications. */ |
4b58290f | 49 | |
038eab67 NC |
50 | #define TARGET_CPU_CPP_BUILTINS() \ |
51 | do \ | |
52 | { \ | |
53 | builtin_define_std ("xstormy16"); \ | |
54 | builtin_assert ("machine=xstormy16"); \ | |
55 | builtin_assert ("cpu=xstormy16"); \ | |
56 | } \ | |
57 | while (0) | |
4b58290f | 58 | \f |
038eab67 | 59 | /* Storage Layout. */ |
4b58290f | 60 | |
4b58290f GK |
61 | #define BITS_BIG_ENDIAN 1 |
62 | ||
4b58290f GK |
63 | #define BYTES_BIG_ENDIAN 0 |
64 | ||
4b58290f GK |
65 | #define WORDS_BIG_ENDIAN 0 |
66 | ||
4b58290f GK |
67 | #define UNITS_PER_WORD 2 |
68 | ||
038eab67 NC |
69 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
70 | do \ | |
71 | { \ | |
72 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
73 | && GET_MODE_SIZE (MODE) < 2) \ | |
74 | (MODE) = HImode; \ | |
75 | } \ | |
76 | while (0) | |
4b58290f | 77 | |
4b58290f GK |
78 | #define PARM_BOUNDARY 16 |
79 | ||
4b58290f GK |
80 | #define STACK_BOUNDARY 16 |
81 | ||
4b58290f GK |
82 | #define FUNCTION_BOUNDARY 16 |
83 | ||
4b58290f GK |
84 | #define BIGGEST_ALIGNMENT 16 |
85 | ||
4b58290f GK |
86 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
87 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
88 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
89 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
90 | ||
4b58290f GK |
91 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
92 | (TREE_CODE (EXP) == STRING_CST \ | |
93 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
94 | ||
4b58290f GK |
95 | #define STRICT_ALIGNMENT 1 |
96 | ||
4b58290f | 97 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
4b58290f | 98 | \f |
038eab67 | 99 | /* Layout of Source Language Data Types. */ |
4b58290f | 100 | |
4b58290f GK |
101 | #define INT_TYPE_SIZE 16 |
102 | ||
4b58290f GK |
103 | #define SHORT_TYPE_SIZE 16 |
104 | ||
4b58290f GK |
105 | #define LONG_TYPE_SIZE 32 |
106 | ||
4b58290f GK |
107 | #define LONG_LONG_TYPE_SIZE 64 |
108 | ||
4b58290f GK |
109 | #define FLOAT_TYPE_SIZE 32 |
110 | ||
4b58290f GK |
111 | #define DOUBLE_TYPE_SIZE 64 |
112 | ||
4b58290f GK |
113 | #define LONG_DOUBLE_TYPE_SIZE 64 |
114 | ||
4b58290f GK |
115 | #define DEFAULT_SIGNED_CHAR 0 |
116 | ||
4b58290f GK |
117 | #define SIZE_TYPE "unsigned int" |
118 | ||
4b58290f GK |
119 | #define PTRDIFF_TYPE "int" |
120 | ||
5519175f JM |
121 | #undef WCHAR_TYPE |
122 | #define WCHAR_TYPE "long int" | |
123 | ||
038eab67 | 124 | #undef WCHAR_TYPE_SIZE |
4b58290f GK |
125 | #define WCHAR_TYPE_SIZE 32 |
126 | ||
4b58290f | 127 | \f |
038eab67 | 128 | /* Register Basics. */ |
4b58290f | 129 | |
4b58290f GK |
130 | #define FIRST_PSEUDO_REGISTER 19 |
131 | ||
4b58290f GK |
132 | #define FIXED_REGISTERS \ |
133 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1 } | |
134 | ||
4b58290f GK |
135 | #define CALL_USED_REGISTERS \ |
136 | { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1 } | |
137 | ||
4b58290f | 138 | \f |
038eab67 | 139 | /* Order of allocation of registers. */ |
4b58290f | 140 | |
da6e254e | 141 | #define REG_ALLOC_ORDER { 7, 6, 5, 4, 3, 2, 1, 0, 9, 8, 10, 11, 12, 13, 14, 15, 16 } |
4b58290f | 142 | |
4b58290f | 143 | \f |
038eab67 | 144 | /* How Values Fit in Registers. */ |
4b58290f | 145 | |
4b58290f GK |
146 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
147 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
148 | ||
4b58290f GK |
149 | #define HARD_REGNO_MODE_OK(REGNO, MODE) ((REGNO) != 16 || (MODE) == BImode) |
150 | ||
151 | /* A C expression that is nonzero if it is desirable to choose register | |
152 | allocation so as to avoid move instructions between a value of mode MODE1 | |
153 | and a value of mode MODE2. | |
154 | ||
155 | If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are | |
156 | ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be | |
157 | zero. */ | |
158 | #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) != BImode && (MODE2) != BImode) | |
159 | ||
4b58290f | 160 | \f |
038eab67 | 161 | /* Register Classes. */ |
4b58290f | 162 | |
4b58290f GK |
163 | enum reg_class |
164 | { | |
165 | NO_REGS, | |
166 | R0_REGS, | |
167 | R1_REGS, | |
168 | TWO_REGS, | |
169 | R2_REGS, | |
170 | EIGHT_REGS, | |
171 | R8_REGS, | |
da6e254e | 172 | ICALL_REGS, |
4b58290f | 173 | GENERAL_REGS, |
4b58290f GK |
174 | ALL_REGS, |
175 | LIM_REG_CLASSES | |
176 | }; | |
177 | ||
4b58290f GK |
178 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
179 | ||
4b58290f GK |
180 | #define REG_CLASS_NAMES \ |
181 | { \ | |
182 | "NO_REGS", \ | |
183 | "R0_REGS", \ | |
184 | "R1_REGS", \ | |
185 | "TWO_REGS", \ | |
186 | "R2_REGS", \ | |
187 | "EIGHT_REGS", \ | |
188 | "R8_REGS", \ | |
da6e254e | 189 | "ICALL_REGS", \ |
4b58290f | 190 | "GENERAL_REGS", \ |
4b58290f GK |
191 | "ALL_REGS" \ |
192 | } | |
193 | ||
4b58290f GK |
194 | #define REG_CLASS_CONTENTS \ |
195 | { \ | |
b3656137 KG |
196 | { 0x00000 }, \ |
197 | { 0x00001 }, \ | |
198 | { 0x00002 }, \ | |
199 | { 0x00003 }, \ | |
200 | { 0x00004 }, \ | |
201 | { 0x000FF }, \ | |
202 | { 0x00100 }, \ | |
203 | { 0x00300 }, \ | |
204 | { 0x6FFFF }, \ | |
b3656137 | 205 | { (1 << FIRST_PSEUDO_REGISTER) - 1 } \ |
4b58290f GK |
206 | } |
207 | ||
4b58290f | 208 | #define REGNO_REG_CLASS(REGNO) \ |
d40ba0b6 NC |
209 | ( (REGNO) == 0 ? R0_REGS \ |
210 | : (REGNO) == 1 ? R1_REGS \ | |
211 | : (REGNO) == 2 ? R2_REGS \ | |
212 | : (REGNO) < 8 ? EIGHT_REGS \ | |
213 | : (REGNO) == 8 ? R8_REGS \ | |
4b58290f GK |
214 | : (REGNO) <= 18 ? GENERAL_REGS \ |
215 | : ALL_REGS) | |
216 | ||
4b58290f GK |
217 | #define BASE_REG_CLASS GENERAL_REGS |
218 | ||
4b58290f GK |
219 | #define INDEX_REG_CLASS GENERAL_REGS |
220 | ||
4b58290f GK |
221 | #define REGNO_OK_FOR_BASE_P(NUM) 1 |
222 | ||
4b58290f GK |
223 | #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM) |
224 | ||
4b58290f GK |
225 | /* This chip has the interesting property that only the first eight |
226 | registers can be moved to/from memory. */ | |
227 | #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ | |
c6243b4c | 228 | xstormy16_secondary_reload_class (CLASS, MODE, X) |
4b58290f | 229 | |
4b58290f GK |
230 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
231 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
232 | ||
4b58290f | 233 | \f |
038eab67 | 234 | /* Basic Stack Layout. */ |
4b58290f | 235 | |
4b58290f GK |
236 | /* We want to use post-increment instructions to push things on the stack, |
237 | because we don't have any pre-increment ones. */ | |
238 | #define STACK_PUSH_CODE POST_INC | |
239 | ||
f62c8a5c | 240 | #define FRAME_GROWS_DOWNWARD 0 |
4b58290f | 241 | |
4b58290f GK |
242 | #define ARGS_GROW_DOWNWARD 1 |
243 | ||
4b58290f GK |
244 | #define STARTING_FRAME_OFFSET 0 |
245 | ||
4b58290f GK |
246 | #define FIRST_PARM_OFFSET(FUNDECL) 0 |
247 | ||
4b58290f GK |
248 | #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \ |
249 | ((COUNT) == 0 \ | |
250 | ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \ | |
251 | : NULL_RTX) | |
252 | ||
4b58290f GK |
253 | #define INCOMING_RETURN_ADDR_RTX \ |
254 | gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-4))) | |
255 | ||
b72bbbcb | 256 | #define INCOMING_FRAME_SP_OFFSET (xstormy16_interrupt_function_p () ? -6 : -4) |
4b58290f | 257 | |
4b58290f GK |
258 | \f |
259 | /* Register That Address the Stack Frame. */ | |
260 | ||
d40ba0b6 | 261 | #define STATIC_CHAIN_REGNUM 1 |
4b58290f | 262 | #define HARD_FRAME_POINTER_REGNUM 13 |
d40ba0b6 NC |
263 | #define STACK_POINTER_REGNUM 15 |
264 | #define CARRY_REGNUM 16 | |
265 | #define FRAME_POINTER_REGNUM 17 | |
266 | #define ARG_POINTER_REGNUM 18 | |
4b58290f GK |
267 | |
268 | \f | |
038eab67 | 269 | /* Eliminating the Frame Pointer and the Arg Pointer. */ |
4b58290f | 270 | |
4b58290f GK |
271 | #define ELIMINABLE_REGS \ |
272 | { \ | |
273 | {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
274 | {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
275 | {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
276 | {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
277 | } | |
278 | ||
4b58290f | 279 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
c6243b4c | 280 | (OFFSET) = xstormy16_initial_elimination_offset (FROM, TO) |
4b58290f | 281 | |
4b58290f | 282 | \f |
038eab67 | 283 | /* Passing Function Arguments on the Stack. */ |
4b58290f | 284 | |
4b58290f GK |
285 | #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1) |
286 | ||
4b58290f | 287 | \f |
038eab67 | 288 | /* Function Arguments in Registers. */ |
4b58290f | 289 | |
038eab67 | 290 | #define NUM_ARGUMENT_REGISTERS 6 |
4b58290f GK |
291 | #define FIRST_ARGUMENT_REGISTER 2 |
292 | ||
c6243b4c | 293 | #define XSTORMY16_WORD_SIZE(TYPE, MODE) \ |
4b58290f GK |
294 | ((((TYPE) ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \ |
295 | + 1) \ | |
296 | / 2) | |
297 | ||
595cac16 | 298 | /* For this platform, the value of CUMULATIVE_ARGS is the number of words |
4b58290f | 299 | of arguments that have been passed in registers so far. */ |
c8f863fc | 300 | #define CUMULATIVE_ARGS int |
4b58290f | 301 | |
0f6937fe AM |
302 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
303 | (CUM) = 0 | |
4b58290f | 304 | |
4b58290f GK |
305 | #define FUNCTION_ARG_REGNO_P(REGNO) \ |
306 | ((REGNO) >= FIRST_ARGUMENT_REGISTER \ | |
307 | && (REGNO) < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS) | |
308 | ||
309 | \f | |
038eab67 | 310 | /* How Scalar Function Values are Returned. */ |
4b58290f GK |
311 | |
312 | /* The number of the hard register that is used to return a scalar value from a | |
313 | function call. */ | |
314 | #define RETURN_VALUE_REGNUM FIRST_ARGUMENT_REGISTER | |
4b58290f | 315 | |
4b58290f | 316 | \f |
038eab67 | 317 | /* Function Entry and Exit. */ |
4b58290f | 318 | |
4b58290f | 319 | #define EPILOGUE_USES(REGNO) \ |
c6243b4c | 320 | xstormy16_epilogue_uses (REGNO) |
4b58290f | 321 | |
4b58290f GK |
322 | \f |
323 | /* Generating Code for Profiling. */ | |
324 | ||
595cac16 | 325 | /* This declaration must be present, but it can be an abort if profiling is |
4b58290f GK |
326 | not implemented. */ |
327 | ||
14b56832 | 328 | #define FUNCTION_PROFILER(FILE, LABELNO) xstormy16_function_profiler () |
4b58290f | 329 | |
4b58290f | 330 | \f |
4b58290f GK |
331 | /* Trampolines for Nested Functions. */ |
332 | ||
4b58290f | 333 | #define TRAMPOLINE_SIZE 8 |
4b58290f | 334 | #define TRAMPOLINE_ALIGNMENT 16 |
4b58290f | 335 | \f |
4b58290f | 336 | |
038eab67 | 337 | /* Addressing Modes. */ |
4b58290f | 338 | |
4b58290f GK |
339 | #define HAVE_POST_INCREMENT 1 |
340 | ||
4b58290f GK |
341 | #define HAVE_PRE_DECREMENT 1 |
342 | ||
4b58290f GK |
343 | #define MAX_REGS_PER_ADDRESS 1 |
344 | ||
4b58290f | 345 | \f |
038eab67 | 346 | /* Describing Relative Costs of Operations. */ |
4b58290f | 347 | |
3a4fd356 | 348 | #define BRANCH_COST(speed_p, predictable_p) 5 |
4b58290f | 349 | |
4b58290f GK |
350 | #define SLOW_BYTE_ACCESS 0 |
351 | ||
4b58290f GK |
352 | #define NO_FUNCTION_CSE |
353 | ||
4b58290f GK |
354 | \f |
355 | /* Dividing the output into sections. */ | |
356 | ||
4b58290f GK |
357 | #define TEXT_SECTION_ASM_OP ".text" |
358 | ||
4b58290f GK |
359 | #define DATA_SECTION_ASM_OP ".data" |
360 | ||
752151e8 | 361 | #define BSS_SECTION_ASM_OP "\t.section\t.bss" |
4b58290f | 362 | |
4b58290f GK |
363 | /* Define the pseudo-ops used to switch to the .ctors and .dtors sections. |
364 | There are no shared libraries on this target so these sections need | |
365 | not be writable. | |
366 | ||
367 | Defined in elfos.h. */ | |
368 | ||
369 | #undef CTORS_SECTION_ASM_OP | |
370 | #undef DTORS_SECTION_ASM_OP | |
371 | #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\"" | |
372 | #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\"" | |
373 | ||
d6b5193b | 374 | #define TARGET_ASM_INIT_SECTIONS xstormy16_asm_init_sections |
4b58290f | 375 | |
d6b5193b | 376 | #define JUMP_TABLES_IN_TEXT_SECTION 1 |
4b58290f GK |
377 | \f |
378 | /* The Overall Framework of an Assembler File. */ | |
379 | ||
7c87e9f9 | 380 | #define ASM_COMMENT_START ";" |
4b58290f | 381 | |
4b58290f GK |
382 | #define ASM_APP_ON "#APP\n" |
383 | ||
4b58290f | 384 | #define ASM_APP_OFF "#NO_APP\n" |
4b58290f GK |
385 | \f |
386 | /* Output of Data. */ | |
387 | ||
980d8882 | 388 | #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '|') |
4b58290f | 389 | |
54e9a19d | 390 | #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ |
2f806f3b | 391 | xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1) |
54e9a19d | 392 | #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ |
2f806f3b | 393 | xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0) |
54e9a19d | 394 | |
4b58290f GK |
395 | \f |
396 | /* Output and Generation of Labels. */ | |
2f806f3b | 397 | #define SYMBOL_FLAG_XSTORMY16_BELOW100 (SYMBOL_FLAG_MACH_DEP << 0) |
4b58290f | 398 | |
038eab67 NC |
399 | #define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL) \ |
400 | do \ | |
401 | { \ | |
402 | const char *rn = XSTR (SYMBOL, 0); \ | |
403 | \ | |
404 | if (SYMBOL_REF_FUNCTION_P (SYMBOL)) \ | |
405 | ASM_OUTPUT_LABEL_REF ((STREAM), rn); \ | |
406 | else \ | |
407 | assemble_name (STREAM, rn); \ | |
408 | } \ | |
409 | while (0) | |
4b58290f | 410 | |
2f0b7af6 | 411 | #define ASM_OUTPUT_LABEL_REF(STREAM, NAME) \ |
038eab67 NC |
412 | do \ |
413 | { \ | |
414 | fputs ("@fptr(", STREAM); \ | |
415 | assemble_name (STREAM, NAME); \ | |
416 | fputc (')', STREAM); \ | |
417 | } \ | |
418 | while (0) | |
2f0b7af6 | 419 | |
506a61b1 KG |
420 | /* Globalizing directive for a label. */ |
421 | #define GLOBAL_ASM_OP "\t.globl " | |
4b58290f | 422 | |
4b58290f GK |
423 | \f |
424 | /* Output of Assembler Instructions. */ | |
425 | ||
4b58290f GK |
426 | #define REGISTER_NAMES \ |
427 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \ | |
428 | "r11", "r12", "r13", "psw", "sp", "carry", "fp", "ap" } | |
429 | ||
4b58290f GK |
430 | #define ADDITIONAL_REGISTER_NAMES \ |
431 | { { "r14", 14 }, \ | |
432 | { "r15", 15 } } | |
433 | ||
4b58290f GK |
434 | #define REGISTER_PREFIX "" |
435 | #define LOCAL_LABEL_PREFIX "." | |
436 | #define USER_LABEL_PREFIX "" | |
437 | #define IMMEDIATE_PREFIX "#" | |
438 | ||
4b58290f GK |
439 | #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
440 | fprintf (STREAM, "\tpush %d\n", REGNO) | |
441 | ||
4b58290f GK |
442 | #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ |
443 | fprintf (STREAM, "\tpop %d\n", REGNO) | |
444 | ||
445 | \f | |
446 | /* Output of dispatch tables. */ | |
447 | ||
448 | /* This port does not use the ASM_OUTPUT_ADDR_VEC_ELT macro, because | |
449 | this could cause label alignment to appear between the 'br' and the table, | |
450 | which would be bad. Instead, it controls the output of the table | |
451 | itself. */ | |
452 | #define ASM_OUTPUT_ADDR_VEC(LABEL, BODY) \ | |
c6243b4c | 453 | xstormy16_output_addr_vec (file, LABEL, BODY) |
4b58290f GK |
454 | |
455 | /* Alignment for ADDR_VECs is the same as for code. */ | |
456 | #define ADDR_VEC_ALIGN(ADDR_VEC) 1 | |
457 | ||
458 | \f | |
459 | /* Assembler Commands for Exception Regions. */ | |
460 | ||
b72bbbcb DD |
461 | #define DWARF2_UNWIND_INFO 0 |
462 | #define DWARF_CIE_DATA_ALIGNMENT 1 | |
4b58290f | 463 | |
038eab67 | 464 | #undef DONT_USE_BUILTIN_SETJMP |
9defc9b7 | 465 | #define JMP_BUF_SIZE 8 |
4b58290f GK |
466 | \f |
467 | /* Assembler Commands for Alignment. */ | |
468 | ||
4b58290f GK |
469 | #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ |
470 | fprintf ((STREAM), "\t.p2align %d\n", (POWER)) | |
471 | ||
472 | \f | |
473 | /* Macros Affecting all Debug Formats. */ | |
474 | ||
038eab67 | 475 | #undef PREFERRED_DEBUGGING_TYPE |
4b58290f GK |
476 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG |
477 | ||
4b58290f GK |
478 | \f |
479 | /* Macros for SDB and Dwarf Output. */ | |
480 | ||
4b58290f GK |
481 | /* Define this macro if addresses in Dwarf 2 debugging info should not |
482 | be the same size as pointers on the target architecture. The | |
483 | macro's value should be the size, in bytes, to use for addresses in | |
484 | the debugging info. | |
485 | ||
486 | Some architectures use word addresses to refer to code locations, | |
487 | but Dwarf 2 info always uses byte addresses. On such machines, | |
488 | Dwarf 2 addresses need to be larger than the architecture's | |
489 | pointers. */ | |
490 | #define DWARF2_ADDR_SIZE 4 | |
491 | ||
4b58290f GK |
492 | \f |
493 | /* Miscellaneous Parameters. */ | |
494 | ||
4b58290f GK |
495 | #define CASE_VECTOR_MODE SImode |
496 | ||
4b58290f GK |
497 | #define WORD_REGISTER_OPERATIONS |
498 | ||
4b58290f GK |
499 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
500 | ||
4b58290f GK |
501 | #define MOVE_MAX 2 |
502 | ||
4b58290f GK |
503 | #define SHIFT_COUNT_TRUNCATED 1 |
504 | ||
4b58290f GK |
505 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
506 | ||
4b58290f GK |
507 | #define Pmode HImode |
508 | ||
4b58290f GK |
509 | #define FUNCTION_MODE HImode |
510 | ||
4b58290f | 511 | #define NO_IMPLICIT_EXTERN_C |