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c6243b4c | 1 | /* Xstormy16 cpu description. |
99dee823 | 2 | Copyright (C) 1997-2021 Free Software Foundation, Inc. |
4b58290f GK |
3 | Contributed by Red Hat, Inc. |
4 | ||
038eab67 | 5 | This file is part of GCC. |
4b58290f | 6 | |
038eab67 NC |
7 | GCC is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
4b58290f | 11 | |
038eab67 NC |
12 | GCC is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
4b58290f | 16 | |
038eab67 NC |
17 | You should have received a copy of the GNU General Public License |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
4b58290f | 20 | |
4b58290f | 21 | \f |
038eab67 | 22 | /* Driver configuration. */ |
4b58290f | 23 | |
038eab67 | 24 | #undef ASM_SPEC |
322fe6e1 | 25 | #define ASM_SPEC "" |
4b58290f | 26 | |
5519175f JM |
27 | #undef LINK_SPEC |
28 | #define LINK_SPEC "%{h*} %{v:-V} \ | |
29 | %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}" | |
30 | ||
d1552d7b | 31 | /* For xstormy16: |
3eaaf577 GK |
32 | - If -msim is specified, everything is built and linked as for the sim. |
33 | - If -T is specified, that linker script is used, and it should provide | |
34 | appropriate libraries. | |
35 | - If neither is specified, everything is built as for the sim, but no | |
038eab67 NC |
36 | I/O support is assumed. */ |
37 | #undef LIB_SPEC | |
3eaaf577 | 38 | #define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:%{!T*:-lnosys}} -)" |
4b58290f | 39 | |
038eab67 | 40 | #undef STARTFILE_SPEC |
4b58290f GK |
41 | #define STARTFILE_SPEC "crt0.o%s crti.o%s crtbegin.o%s" |
42 | ||
038eab67 | 43 | #undef ENDFILE_SPEC |
4b58290f GK |
44 | #define ENDFILE_SPEC "crtend.o%s crtn.o%s" |
45 | ||
4b58290f | 46 | \f |
038eab67 | 47 | /* Run-time target specifications. */ |
4b58290f | 48 | |
038eab67 NC |
49 | #define TARGET_CPU_CPP_BUILTINS() \ |
50 | do \ | |
51 | { \ | |
52 | builtin_define_std ("xstormy16"); \ | |
53 | builtin_assert ("machine=xstormy16"); \ | |
54 | builtin_assert ("cpu=xstormy16"); \ | |
55 | } \ | |
56 | while (0) | |
4b58290f | 57 | \f |
038eab67 | 58 | /* Storage Layout. */ |
4b58290f | 59 | |
4b58290f GK |
60 | #define BITS_BIG_ENDIAN 1 |
61 | ||
4b58290f GK |
62 | #define BYTES_BIG_ENDIAN 0 |
63 | ||
4b58290f GK |
64 | #define WORDS_BIG_ENDIAN 0 |
65 | ||
4b58290f GK |
66 | #define UNITS_PER_WORD 2 |
67 | ||
038eab67 NC |
68 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
69 | do \ | |
70 | { \ | |
71 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
72 | && GET_MODE_SIZE (MODE) < 2) \ | |
73 | (MODE) = HImode; \ | |
74 | } \ | |
75 | while (0) | |
4b58290f | 76 | |
4b58290f GK |
77 | #define PARM_BOUNDARY 16 |
78 | ||
4b58290f GK |
79 | #define STACK_BOUNDARY 16 |
80 | ||
4b58290f GK |
81 | #define FUNCTION_BOUNDARY 16 |
82 | ||
4b58290f GK |
83 | #define BIGGEST_ALIGNMENT 16 |
84 | ||
4b58290f GK |
85 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
86 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
87 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
88 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
89 | ||
4b58290f GK |
90 | #define STRICT_ALIGNMENT 1 |
91 | ||
4b58290f | 92 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
4b58290f | 93 | \f |
038eab67 | 94 | /* Layout of Source Language Data Types. */ |
4b58290f | 95 | |
4b58290f GK |
96 | #define INT_TYPE_SIZE 16 |
97 | ||
4b58290f GK |
98 | #define SHORT_TYPE_SIZE 16 |
99 | ||
4b58290f GK |
100 | #define LONG_TYPE_SIZE 32 |
101 | ||
4b58290f GK |
102 | #define LONG_LONG_TYPE_SIZE 64 |
103 | ||
4b58290f GK |
104 | #define FLOAT_TYPE_SIZE 32 |
105 | ||
4b58290f GK |
106 | #define DOUBLE_TYPE_SIZE 64 |
107 | ||
4b58290f GK |
108 | #define LONG_DOUBLE_TYPE_SIZE 64 |
109 | ||
4b58290f GK |
110 | #define DEFAULT_SIGNED_CHAR 0 |
111 | ||
4b58290f GK |
112 | #define SIZE_TYPE "unsigned int" |
113 | ||
4b58290f GK |
114 | #define PTRDIFF_TYPE "int" |
115 | ||
5519175f JM |
116 | #undef WCHAR_TYPE |
117 | #define WCHAR_TYPE "long int" | |
118 | ||
038eab67 | 119 | #undef WCHAR_TYPE_SIZE |
4b58290f GK |
120 | #define WCHAR_TYPE_SIZE 32 |
121 | ||
4b58290f | 122 | \f |
038eab67 | 123 | /* Register Basics. */ |
4b58290f | 124 | |
4b58290f GK |
125 | #define FIRST_PSEUDO_REGISTER 19 |
126 | ||
4b58290f GK |
127 | #define FIXED_REGISTERS \ |
128 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1 } | |
129 | ||
4b58290f GK |
130 | #define CALL_USED_REGISTERS \ |
131 | { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1 } | |
132 | ||
4b58290f | 133 | \f |
038eab67 | 134 | /* Order of allocation of registers. */ |
4b58290f | 135 | |
da6e254e | 136 | #define REG_ALLOC_ORDER { 7, 6, 5, 4, 3, 2, 1, 0, 9, 8, 10, 11, 12, 13, 14, 15, 16 } |
4b58290f | 137 | |
4b58290f | 138 | \f |
038eab67 | 139 | /* Register Classes. */ |
4b58290f | 140 | |
4b58290f GK |
141 | enum reg_class |
142 | { | |
143 | NO_REGS, | |
144 | R0_REGS, | |
145 | R1_REGS, | |
146 | TWO_REGS, | |
147 | R2_REGS, | |
148 | EIGHT_REGS, | |
149 | R8_REGS, | |
da6e254e | 150 | ICALL_REGS, |
4b58290f | 151 | GENERAL_REGS, |
4b58290f GK |
152 | ALL_REGS, |
153 | LIM_REG_CLASSES | |
154 | }; | |
155 | ||
4b58290f GK |
156 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
157 | ||
4b58290f GK |
158 | #define REG_CLASS_NAMES \ |
159 | { \ | |
160 | "NO_REGS", \ | |
161 | "R0_REGS", \ | |
162 | "R1_REGS", \ | |
163 | "TWO_REGS", \ | |
164 | "R2_REGS", \ | |
165 | "EIGHT_REGS", \ | |
166 | "R8_REGS", \ | |
da6e254e | 167 | "ICALL_REGS", \ |
4b58290f | 168 | "GENERAL_REGS", \ |
4b58290f GK |
169 | "ALL_REGS" \ |
170 | } | |
171 | ||
4b58290f GK |
172 | #define REG_CLASS_CONTENTS \ |
173 | { \ | |
b3656137 KG |
174 | { 0x00000 }, \ |
175 | { 0x00001 }, \ | |
176 | { 0x00002 }, \ | |
177 | { 0x00003 }, \ | |
178 | { 0x00004 }, \ | |
179 | { 0x000FF }, \ | |
180 | { 0x00100 }, \ | |
181 | { 0x00300 }, \ | |
182 | { 0x6FFFF }, \ | |
b3656137 | 183 | { (1 << FIRST_PSEUDO_REGISTER) - 1 } \ |
4b58290f GK |
184 | } |
185 | ||
4b58290f | 186 | #define REGNO_REG_CLASS(REGNO) \ |
d40ba0b6 NC |
187 | ( (REGNO) == 0 ? R0_REGS \ |
188 | : (REGNO) == 1 ? R1_REGS \ | |
189 | : (REGNO) == 2 ? R2_REGS \ | |
190 | : (REGNO) < 8 ? EIGHT_REGS \ | |
191 | : (REGNO) == 8 ? R8_REGS \ | |
4b58290f GK |
192 | : (REGNO) <= 18 ? GENERAL_REGS \ |
193 | : ALL_REGS) | |
194 | ||
4b58290f GK |
195 | #define BASE_REG_CLASS GENERAL_REGS |
196 | ||
4b58290f GK |
197 | #define INDEX_REG_CLASS GENERAL_REGS |
198 | ||
4b58290f GK |
199 | #define REGNO_OK_FOR_BASE_P(NUM) 1 |
200 | ||
4b58290f GK |
201 | #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM) |
202 | ||
4b58290f GK |
203 | /* This chip has the interesting property that only the first eight |
204 | registers can be moved to/from memory. */ | |
205 | #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ | |
c6243b4c | 206 | xstormy16_secondary_reload_class (CLASS, MODE, X) |
4b58290f | 207 | |
4b58290f | 208 | \f |
038eab67 | 209 | /* Basic Stack Layout. */ |
4b58290f | 210 | |
4b58290f GK |
211 | /* We want to use post-increment instructions to push things on the stack, |
212 | because we don't have any pre-increment ones. */ | |
213 | #define STACK_PUSH_CODE POST_INC | |
214 | ||
f62c8a5c | 215 | #define FRAME_GROWS_DOWNWARD 0 |
4b58290f | 216 | |
4b58290f GK |
217 | #define ARGS_GROW_DOWNWARD 1 |
218 | ||
4b58290f GK |
219 | #define FIRST_PARM_OFFSET(FUNDECL) 0 |
220 | ||
4b58290f GK |
221 | #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \ |
222 | ((COUNT) == 0 \ | |
223 | ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \ | |
224 | : NULL_RTX) | |
225 | ||
4b58290f GK |
226 | #define INCOMING_RETURN_ADDR_RTX \ |
227 | gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-4))) | |
228 | ||
b72bbbcb | 229 | #define INCOMING_FRAME_SP_OFFSET (xstormy16_interrupt_function_p () ? -6 : -4) |
4b58290f | 230 | |
26fc730d | 231 | #define DEFAULT_INCOMING_FRAME_SP_OFFSET -4 |
4b58290f GK |
232 | \f |
233 | /* Register That Address the Stack Frame. */ | |
234 | ||
d40ba0b6 | 235 | #define STATIC_CHAIN_REGNUM 1 |
4b58290f | 236 | #define HARD_FRAME_POINTER_REGNUM 13 |
d40ba0b6 NC |
237 | #define STACK_POINTER_REGNUM 15 |
238 | #define CARRY_REGNUM 16 | |
239 | #define FRAME_POINTER_REGNUM 17 | |
240 | #define ARG_POINTER_REGNUM 18 | |
4b58290f GK |
241 | |
242 | \f | |
038eab67 | 243 | /* Eliminating the Frame Pointer and the Arg Pointer. */ |
4b58290f | 244 | |
4b58290f GK |
245 | #define ELIMINABLE_REGS \ |
246 | { \ | |
247 | {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
248 | {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
249 | {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
250 | {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
251 | } | |
252 | ||
4b58290f | 253 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
c6243b4c | 254 | (OFFSET) = xstormy16_initial_elimination_offset (FROM, TO) |
4b58290f | 255 | |
4b58290f | 256 | \f |
038eab67 | 257 | /* Passing Function Arguments on the Stack. */ |
4b58290f | 258 | |
7b4df2bf | 259 | #define PUSH_ROUNDING(BYTES) xstormy16_push_rounding (BYTES) |
4b58290f | 260 | |
4b58290f | 261 | \f |
038eab67 | 262 | /* Function Arguments in Registers. */ |
4b58290f | 263 | |
038eab67 | 264 | #define NUM_ARGUMENT_REGISTERS 6 |
4b58290f GK |
265 | #define FIRST_ARGUMENT_REGISTER 2 |
266 | ||
c6243b4c | 267 | #define XSTORMY16_WORD_SIZE(TYPE, MODE) \ |
4b58290f GK |
268 | ((((TYPE) ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \ |
269 | + 1) \ | |
270 | / 2) | |
271 | ||
595cac16 | 272 | /* For this platform, the value of CUMULATIVE_ARGS is the number of words |
4b58290f | 273 | of arguments that have been passed in registers so far. */ |
c8f863fc | 274 | #define CUMULATIVE_ARGS int |
4b58290f | 275 | |
0f6937fe AM |
276 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
277 | (CUM) = 0 | |
4b58290f | 278 | |
4b58290f GK |
279 | #define FUNCTION_ARG_REGNO_P(REGNO) \ |
280 | ((REGNO) >= FIRST_ARGUMENT_REGISTER \ | |
281 | && (REGNO) < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS) | |
282 | ||
283 | \f | |
038eab67 | 284 | /* How Scalar Function Values are Returned. */ |
4b58290f GK |
285 | |
286 | /* The number of the hard register that is used to return a scalar value from a | |
287 | function call. */ | |
288 | #define RETURN_VALUE_REGNUM FIRST_ARGUMENT_REGISTER | |
4b58290f | 289 | |
4b58290f | 290 | \f |
038eab67 | 291 | /* Function Entry and Exit. */ |
4b58290f | 292 | |
4b58290f | 293 | #define EPILOGUE_USES(REGNO) \ |
c6243b4c | 294 | xstormy16_epilogue_uses (REGNO) |
4b58290f | 295 | |
4b58290f GK |
296 | \f |
297 | /* Generating Code for Profiling. */ | |
298 | ||
595cac16 | 299 | /* This declaration must be present, but it can be an abort if profiling is |
4b58290f GK |
300 | not implemented. */ |
301 | ||
14b56832 | 302 | #define FUNCTION_PROFILER(FILE, LABELNO) xstormy16_function_profiler () |
4b58290f | 303 | |
4b58290f | 304 | \f |
4b58290f GK |
305 | /* Trampolines for Nested Functions. */ |
306 | ||
4b58290f | 307 | #define TRAMPOLINE_SIZE 8 |
4b58290f | 308 | #define TRAMPOLINE_ALIGNMENT 16 |
4b58290f | 309 | \f |
4b58290f | 310 | |
038eab67 | 311 | /* Addressing Modes. */ |
4b58290f | 312 | |
4b58290f GK |
313 | #define HAVE_POST_INCREMENT 1 |
314 | ||
4b58290f GK |
315 | #define HAVE_PRE_DECREMENT 1 |
316 | ||
4b58290f GK |
317 | #define MAX_REGS_PER_ADDRESS 1 |
318 | ||
4b58290f | 319 | \f |
038eab67 | 320 | /* Describing Relative Costs of Operations. */ |
4b58290f | 321 | |
3a4fd356 | 322 | #define BRANCH_COST(speed_p, predictable_p) 5 |
4b58290f | 323 | |
4b58290f GK |
324 | #define SLOW_BYTE_ACCESS 0 |
325 | ||
1e8552c2 | 326 | #define NO_FUNCTION_CSE 1 |
4b58290f | 327 | |
4b58290f GK |
328 | \f |
329 | /* Dividing the output into sections. */ | |
330 | ||
4b58290f GK |
331 | #define TEXT_SECTION_ASM_OP ".text" |
332 | ||
4b58290f GK |
333 | #define DATA_SECTION_ASM_OP ".data" |
334 | ||
752151e8 | 335 | #define BSS_SECTION_ASM_OP "\t.section\t.bss" |
4b58290f | 336 | |
4b58290f GK |
337 | /* Define the pseudo-ops used to switch to the .ctors and .dtors sections. |
338 | There are no shared libraries on this target so these sections need | |
339 | not be writable. | |
340 | ||
341 | Defined in elfos.h. */ | |
342 | ||
343 | #undef CTORS_SECTION_ASM_OP | |
344 | #undef DTORS_SECTION_ASM_OP | |
345 | #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\"" | |
346 | #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\"" | |
347 | ||
d6b5193b | 348 | #define TARGET_ASM_INIT_SECTIONS xstormy16_asm_init_sections |
4b58290f | 349 | |
d6b5193b | 350 | #define JUMP_TABLES_IN_TEXT_SECTION 1 |
4b58290f GK |
351 | \f |
352 | /* The Overall Framework of an Assembler File. */ | |
353 | ||
7c87e9f9 | 354 | #define ASM_COMMENT_START ";" |
4b58290f | 355 | |
4b58290f GK |
356 | #define ASM_APP_ON "#APP\n" |
357 | ||
4b58290f | 358 | #define ASM_APP_OFF "#NO_APP\n" |
4b58290f GK |
359 | \f |
360 | /* Output of Data. */ | |
361 | ||
980d8882 | 362 | #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '|') |
4b58290f | 363 | |
54e9a19d | 364 | #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ |
2f806f3b | 365 | xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1) |
54e9a19d | 366 | #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ |
2f806f3b | 367 | xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0) |
54e9a19d | 368 | |
4b58290f GK |
369 | \f |
370 | /* Output and Generation of Labels. */ | |
2f806f3b | 371 | #define SYMBOL_FLAG_XSTORMY16_BELOW100 (SYMBOL_FLAG_MACH_DEP << 0) |
4b58290f | 372 | |
038eab67 NC |
373 | #define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL) \ |
374 | do \ | |
375 | { \ | |
376 | const char *rn = XSTR (SYMBOL, 0); \ | |
377 | \ | |
378 | if (SYMBOL_REF_FUNCTION_P (SYMBOL)) \ | |
379 | ASM_OUTPUT_LABEL_REF ((STREAM), rn); \ | |
380 | else \ | |
381 | assemble_name (STREAM, rn); \ | |
382 | } \ | |
383 | while (0) | |
4b58290f | 384 | |
2f0b7af6 | 385 | #define ASM_OUTPUT_LABEL_REF(STREAM, NAME) \ |
038eab67 NC |
386 | do \ |
387 | { \ | |
388 | fputs ("@fptr(", STREAM); \ | |
389 | assemble_name (STREAM, NAME); \ | |
390 | fputc (')', STREAM); \ | |
391 | } \ | |
392 | while (0) | |
2f0b7af6 | 393 | |
506a61b1 KG |
394 | /* Globalizing directive for a label. */ |
395 | #define GLOBAL_ASM_OP "\t.globl " | |
4b58290f | 396 | |
4b58290f GK |
397 | \f |
398 | /* Output of Assembler Instructions. */ | |
399 | ||
4b58290f GK |
400 | #define REGISTER_NAMES \ |
401 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \ | |
402 | "r11", "r12", "r13", "psw", "sp", "carry", "fp", "ap" } | |
403 | ||
4b58290f GK |
404 | #define ADDITIONAL_REGISTER_NAMES \ |
405 | { { "r14", 14 }, \ | |
406 | { "r15", 15 } } | |
407 | ||
4b58290f GK |
408 | #define REGISTER_PREFIX "" |
409 | #define LOCAL_LABEL_PREFIX "." | |
410 | #define USER_LABEL_PREFIX "" | |
411 | #define IMMEDIATE_PREFIX "#" | |
412 | ||
4b58290f GK |
413 | #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
414 | fprintf (STREAM, "\tpush %d\n", REGNO) | |
415 | ||
4b58290f GK |
416 | #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ |
417 | fprintf (STREAM, "\tpop %d\n", REGNO) | |
418 | ||
419 | \f | |
420 | /* Output of dispatch tables. */ | |
421 | ||
422 | /* This port does not use the ASM_OUTPUT_ADDR_VEC_ELT macro, because | |
423 | this could cause label alignment to appear between the 'br' and the table, | |
424 | which would be bad. Instead, it controls the output of the table | |
425 | itself. */ | |
426 | #define ASM_OUTPUT_ADDR_VEC(LABEL, BODY) \ | |
c6243b4c | 427 | xstormy16_output_addr_vec (file, LABEL, BODY) |
4b58290f GK |
428 | |
429 | /* Alignment for ADDR_VECs is the same as for code. */ | |
430 | #define ADDR_VEC_ALIGN(ADDR_VEC) 1 | |
431 | ||
432 | \f | |
433 | /* Assembler Commands for Exception Regions. */ | |
434 | ||
b72bbbcb DD |
435 | #define DWARF2_UNWIND_INFO 0 |
436 | #define DWARF_CIE_DATA_ALIGNMENT 1 | |
4b58290f | 437 | |
4b58290f GK |
438 | /* Assembler Commands for Alignment. */ |
439 | ||
4b58290f GK |
440 | #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ |
441 | fprintf ((STREAM), "\t.p2align %d\n", (POWER)) | |
442 | ||
443 | \f | |
444 | /* Macros Affecting all Debug Formats. */ | |
445 | ||
038eab67 | 446 | #undef PREFERRED_DEBUGGING_TYPE |
4b58290f GK |
447 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG |
448 | ||
4b58290f | 449 | \f |
180295ed | 450 | /* Macros for Dwarf Output. */ |
4b58290f | 451 | |
4b58290f GK |
452 | /* Define this macro if addresses in Dwarf 2 debugging info should not |
453 | be the same size as pointers on the target architecture. The | |
454 | macro's value should be the size, in bytes, to use for addresses in | |
455 | the debugging info. | |
456 | ||
457 | Some architectures use word addresses to refer to code locations, | |
458 | but Dwarf 2 info always uses byte addresses. On such machines, | |
459 | Dwarf 2 addresses need to be larger than the architecture's | |
460 | pointers. */ | |
461 | #define DWARF2_ADDR_SIZE 4 | |
462 | ||
4b58290f GK |
463 | \f |
464 | /* Miscellaneous Parameters. */ | |
465 | ||
4b58290f GK |
466 | #define CASE_VECTOR_MODE SImode |
467 | ||
9e11bfef | 468 | #define WORD_REGISTER_OPERATIONS 1 |
4b58290f | 469 | |
4b58290f GK |
470 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
471 | ||
4b58290f GK |
472 | #define MOVE_MAX 2 |
473 | ||
4b58290f GK |
474 | #define SHIFT_COUNT_TRUNCATED 1 |
475 | ||
4b58290f GK |
476 | #define Pmode HImode |
477 | ||
4b58290f | 478 | #define FUNCTION_MODE HImode |