]>
Commit | Line | Data |
---|---|---|
8aeea6e6 | 1 | /* Subroutines for insn-output.c for VAX. |
5624e564 | 2 | Copyright (C) 1987-2015 Free Software Foundation, Inc. |
9c21a7e7 | 3 | |
e7d9d16b | 4 | This file is part of GCC. |
9c21a7e7 | 5 | |
e7d9d16b | 6 | GCC is free software; you can redistribute it and/or modify |
9c21a7e7 | 7 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
9c21a7e7 RS |
9 | any later version. |
10 | ||
e7d9d16b | 11 | GCC is distributed in the hope that it will be useful, |
9c21a7e7 RS |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
9c21a7e7 | 19 | |
9c21a7e7 | 20 | #include "config.h" |
c5c76735 | 21 | #include "system.h" |
4977bab6 ZW |
22 | #include "coretypes.h" |
23 | #include "tm.h" | |
9c21a7e7 | 24 | #include "rtl.h" |
60393bbc AM |
25 | #include "dominance.h" |
26 | #include "cfg.h" | |
27 | #include "cfgrtl.h" | |
28 | #include "cfganal.h" | |
29 | #include "lcm.h" | |
30 | #include "cfgbuild.h" | |
31 | #include "cfgcleanup.h" | |
32 | #include "predict.h" | |
33 | #include "basic-block.h" | |
c4e75102 | 34 | #include "df.h" |
40e23961 MC |
35 | #include "hash-set.h" |
36 | #include "machmode.h" | |
37 | #include "vec.h" | |
38 | #include "double-int.h" | |
39 | #include "input.h" | |
40 | #include "alias.h" | |
41 | #include "symtab.h" | |
42 | #include "wide-int.h" | |
43 | #include "inchash.h" | |
92bc3c1a | 44 | #include "tree.h" |
d8a2d370 DN |
45 | #include "calls.h" |
46 | #include "varasm.h" | |
9c21a7e7 RS |
47 | #include "regs.h" |
48 | #include "hard-reg-set.h" | |
9c21a7e7 RS |
49 | #include "insn-config.h" |
50 | #include "conditions.h" | |
83685514 | 51 | #include "input.h" |
49ad7cfa | 52 | #include "function.h" |
9c21a7e7 RS |
53 | #include "output.h" |
54 | #include "insn-attr.h" | |
08c148a8 | 55 | #include "recog.h" |
215b48a7 | 56 | #include "expr.h" |
b0710fe1 | 57 | #include "insn-codes.h" |
c15c90bb | 58 | #include "optabs.h" |
fb49053f | 59 | #include "flags.h" |
ec20cffb | 60 | #include "debug.h" |
718f9c0f | 61 | #include "diagnostic-core.h" |
c30e7434 | 62 | #include "reload.h" |
c4e75102 MT |
63 | #include "tm-preds.h" |
64 | #include "tm-constrs.h" | |
2fd58acb | 65 | #include "tm_p.h" |
672a6f42 NB |
66 | #include "target.h" |
67 | #include "target-def.h" | |
807e902e | 68 | #include "wide-int.h" |
9b2b7279 | 69 | #include "builtins.h" |
08c148a8 | 70 | |
c5387660 | 71 | static void vax_option_override (void); |
ef4bddc2 | 72 | static bool vax_legitimate_address_p (machine_mode, rtx, bool); |
0d92b0e4 | 73 | static void vax_file_start (void); |
c15c90bb | 74 | static void vax_init_libfuncs (void); |
0d92b0e4 NN |
75 | static void vax_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
76 | HOST_WIDE_INT, tree); | |
77 | static int vax_address_cost_1 (rtx); | |
ef4bddc2 | 78 | static int vax_address_cost (rtx, machine_mode, addr_space_t, bool); |
68f932c4 | 79 | static bool vax_rtx_costs (rtx, int, int, int, int *, bool); |
ef4bddc2 | 80 | static rtx vax_function_arg (cumulative_args_t, machine_mode, |
8f8a46ba | 81 | const_tree, bool); |
ef4bddc2 | 82 | static void vax_function_arg_advance (cumulative_args_t, machine_mode, |
8f8a46ba | 83 | const_tree, bool); |
f289e226 | 84 | static rtx vax_struct_value_rtx (tree, int); |
c4e75102 | 85 | static rtx vax_builtin_setjmp_frame_value (void); |
3814318d RH |
86 | static void vax_asm_trampoline_template (FILE *); |
87 | static void vax_trampoline_init (rtx, tree, rtx); | |
079e7538 | 88 | static int vax_return_pops_args (tree, tree, int); |
5bfed9a9 | 89 | static bool vax_mode_dependent_address_p (const_rtx, addr_space_t); |
672a6f42 NB |
90 | \f |
91 | /* Initialize the GCC target structure. */ | |
301d03af RS |
92 | #undef TARGET_ASM_ALIGNED_HI_OP |
93 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
94 | ||
1bc7c5b6 ZW |
95 | #undef TARGET_ASM_FILE_START |
96 | #define TARGET_ASM_FILE_START vax_file_start | |
97 | #undef TARGET_ASM_FILE_START_APP_OFF | |
98 | #define TARGET_ASM_FILE_START_APP_OFF true | |
99 | ||
c15c90bb ZW |
100 | #undef TARGET_INIT_LIBFUNCS |
101 | #define TARGET_INIT_LIBFUNCS vax_init_libfuncs | |
102 | ||
3961e8fe RH |
103 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
104 | #define TARGET_ASM_OUTPUT_MI_THUNK vax_output_mi_thunk | |
105 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
106 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
107 | ||
3c50106f RH |
108 | #undef TARGET_RTX_COSTS |
109 | #define TARGET_RTX_COSTS vax_rtx_costs | |
dcefdf67 RH |
110 | #undef TARGET_ADDRESS_COST |
111 | #define TARGET_ADDRESS_COST vax_address_cost | |
3c50106f | 112 | |
f289e226 | 113 | #undef TARGET_PROMOTE_PROTOTYPES |
586de218 | 114 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
f289e226 | 115 | |
8f8a46ba NF |
116 | #undef TARGET_FUNCTION_ARG |
117 | #define TARGET_FUNCTION_ARG vax_function_arg | |
118 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
119 | #define TARGET_FUNCTION_ARG_ADVANCE vax_function_arg_advance | |
120 | ||
f289e226 KH |
121 | #undef TARGET_STRUCT_VALUE_RTX |
122 | #define TARGET_STRUCT_VALUE_RTX vax_struct_value_rtx | |
123 | ||
c4e75102 MT |
124 | #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE |
125 | #define TARGET_BUILTIN_SETJMP_FRAME_VALUE vax_builtin_setjmp_frame_value | |
126 | ||
c6c3dba9 PB |
127 | #undef TARGET_LEGITIMATE_ADDRESS_P |
128 | #define TARGET_LEGITIMATE_ADDRESS_P vax_legitimate_address_p | |
b0f6b612 NF |
129 | #undef TARGET_MODE_DEPENDENT_ADDRESS_P |
130 | #define TARGET_MODE_DEPENDENT_ADDRESS_P vax_mode_dependent_address_p | |
c6c3dba9 | 131 | |
b52b1749 AS |
132 | #undef TARGET_FRAME_POINTER_REQUIRED |
133 | #define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true | |
134 | ||
3814318d RH |
135 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
136 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE vax_asm_trampoline_template | |
137 | #undef TARGET_TRAMPOLINE_INIT | |
138 | #define TARGET_TRAMPOLINE_INIT vax_trampoline_init | |
079e7538 NF |
139 | #undef TARGET_RETURN_POPS_ARGS |
140 | #define TARGET_RETURN_POPS_ARGS vax_return_pops_args | |
3814318d | 141 | |
c5387660 JM |
142 | #undef TARGET_OPTION_OVERRIDE |
143 | #define TARGET_OPTION_OVERRIDE vax_option_override | |
144 | ||
f6897b10 | 145 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 146 | \f |
3dc85dfb RH |
147 | /* Set global variables as needed for the options enabled. */ |
148 | ||
c5387660 JM |
149 | static void |
150 | vax_option_override (void) | |
3dc85dfb RH |
151 | { |
152 | /* We're VAX floating point, not IEEE floating point. */ | |
94134f42 ZW |
153 | if (TARGET_G_FLOAT) |
154 | REAL_MODE_FORMAT (DFmode) = &vax_g_format; | |
c5387660 JM |
155 | |
156 | #ifdef SUBTARGET_OVERRIDE_OPTIONS | |
157 | SUBTARGET_OVERRIDE_OPTIONS; | |
158 | #endif | |
3dc85dfb RH |
159 | } |
160 | ||
a3515605 RH |
161 | static void |
162 | vax_add_reg_cfa_offset (rtx insn, int offset, rtx src) | |
163 | { | |
164 | rtx x; | |
165 | ||
0a81f074 | 166 | x = plus_constant (Pmode, frame_pointer_rtx, offset); |
a3515605 RH |
167 | x = gen_rtx_MEM (SImode, x); |
168 | x = gen_rtx_SET (VOIDmode, x, src); | |
169 | add_reg_note (insn, REG_CFA_OFFSET, x); | |
170 | } | |
171 | ||
08c148a8 NB |
172 | /* Generate the assembly code for function entry. FILE is a stdio |
173 | stream to output the code to. SIZE is an int: how many units of | |
174 | temporary storage to allocate. | |
175 | ||
176 | Refer to the array `regs_ever_live' to determine which registers to | |
177 | save; `regs_ever_live[I]' is nonzero if register number I is ever | |
178 | used in the function. This function is responsible for knowing | |
179 | which registers should not be saved even if used. */ | |
180 | ||
a3515605 RH |
181 | void |
182 | vax_expand_prologue (void) | |
08c148a8 | 183 | { |
a3515605 | 184 | int regno, offset; |
d001241c | 185 | int mask = 0; |
a3515605 RH |
186 | HOST_WIDE_INT size; |
187 | rtx insn; | |
08c148a8 NB |
188 | |
189 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
6fb5fa3c | 190 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
08c148a8 NB |
191 | mask |= 1 << regno; |
192 | ||
a3515605 RH |
193 | insn = emit_insn (gen_procedure_entry_mask (GEN_INT (mask))); |
194 | RTX_FRAME_RELATED_P (insn) = 1; | |
08c148a8 | 195 | |
a3515605 | 196 | /* The layout of the CALLG/S stack frame is follows: |
ec20cffb | 197 | |
a3515605 RH |
198 | <- CFA, AP |
199 | r11 | |
200 | r10 | |
201 | ... Registers saved as specified by MASK | |
202 | r3 | |
203 | r2 | |
204 | return-addr | |
205 | old fp | |
206 | old ap | |
207 | old psw | |
208 | zero | |
209 | <- FP, SP | |
ec20cffb | 210 | |
a3515605 RH |
211 | The rest of the prologue will adjust the SP for the local frame. */ |
212 | ||
213 | vax_add_reg_cfa_offset (insn, 4, arg_pointer_rtx); | |
214 | vax_add_reg_cfa_offset (insn, 8, frame_pointer_rtx); | |
215 | vax_add_reg_cfa_offset (insn, 12, pc_rtx); | |
ec20cffb | 216 | |
a3515605 RH |
217 | offset = 16; |
218 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
219 | if (mask & (1 << regno)) | |
220 | { | |
221 | vax_add_reg_cfa_offset (insn, offset, gen_rtx_REG (SImode, regno)); | |
222 | offset += 4; | |
223 | } | |
224 | ||
225 | /* Because add_reg_note pushes the notes, adding this last means that | |
226 | it will be processed first. This is required to allow the other | |
227 | notes be interpreted properly. */ | |
228 | add_reg_note (insn, REG_CFA_DEF_CFA, | |
0a81f074 | 229 | plus_constant (Pmode, frame_pointer_rtx, offset)); |
a3515605 RH |
230 | |
231 | /* Allocate the local stack frame. */ | |
232 | size = get_frame_size (); | |
23361093 | 233 | size -= STARTING_FRAME_OFFSET; |
a3515605 RH |
234 | emit_insn (gen_addsi3 (stack_pointer_rtx, |
235 | stack_pointer_rtx, GEN_INT (-size))); | |
236 | ||
237 | /* Do not allow instructions referencing local stack memory to be | |
238 | scheduled before the frame is allocated. This is more pedantic | |
239 | than anything else, given that VAX does not currently have a | |
240 | scheduling description. */ | |
241 | emit_insn (gen_blockage ()); | |
08c148a8 NB |
242 | } |
243 | ||
1bc7c5b6 ZW |
244 | /* When debugging with stabs, we want to output an extra dummy label |
245 | so that gas can distinguish between D_float and G_float prior to | |
246 | processing the .stabs directive identifying type double. */ | |
247 | static void | |
0d92b0e4 | 248 | vax_file_start (void) |
1bc7c5b6 ZW |
249 | { |
250 | default_file_start (); | |
251 | ||
252 | if (write_symbols == DBX_DEBUG) | |
253 | fprintf (asm_out_file, "___vax_%c_doubles:\n", ASM_DOUBLE_CHAR); | |
254 | } | |
255 | ||
c15c90bb ZW |
256 | /* We can use the BSD C library routines for the libgcc calls that are |
257 | still generated, since that's what they boil down to anyways. When | |
258 | ELF, avoid the user's namespace. */ | |
259 | ||
260 | static void | |
261 | vax_init_libfuncs (void) | |
262 | { | |
1df34d4d MR |
263 | if (TARGET_BSD_DIVMOD) |
264 | { | |
265 | set_optab_libfunc (udiv_optab, SImode, TARGET_ELF ? "*__udiv" : "*udiv"); | |
266 | set_optab_libfunc (umod_optab, SImode, TARGET_ELF ? "*__urem" : "*urem"); | |
267 | } | |
c15c90bb ZW |
268 | } |
269 | ||
2a4bfeed RS |
270 | /* This is like nonimmediate_operand with a restriction on the type of MEM. */ |
271 | ||
c4e75102 MT |
272 | static void |
273 | split_quadword_operands (rtx insn, enum rtx_code code, rtx * operands, | |
274 | rtx * low, int n) | |
9c21a7e7 RS |
275 | { |
276 | int i; | |
9c21a7e7 | 277 | |
c4e75102 MT |
278 | for (i = 0; i < n; i++) |
279 | low[i] = 0; | |
280 | ||
281 | for (i = 0; i < n; i++) | |
9c21a7e7 | 282 | { |
c4e75102 MT |
283 | if (MEM_P (operands[i]) |
284 | && (GET_CODE (XEXP (operands[i], 0)) == PRE_DEC | |
285 | || GET_CODE (XEXP (operands[i], 0)) == POST_INC)) | |
9c21a7e7 RS |
286 | { |
287 | rtx addr = XEXP (operands[i], 0); | |
c5c76735 | 288 | operands[i] = low[i] = gen_rtx_MEM (SImode, addr); |
c4e75102 MT |
289 | } |
290 | else if (optimize_size && MEM_P (operands[i]) | |
291 | && REG_P (XEXP (operands[i], 0)) | |
292 | && (code != MINUS || operands[1] != const0_rtx) | |
293 | && find_regno_note (insn, REG_DEAD, | |
294 | REGNO (XEXP (operands[i], 0)))) | |
295 | { | |
296 | low[i] = gen_rtx_MEM (SImode, | |
297 | gen_rtx_POST_INC (Pmode, | |
298 | XEXP (operands[i], 0))); | |
299 | operands[i] = gen_rtx_MEM (SImode, XEXP (operands[i], 0)); | |
9c21a7e7 RS |
300 | } |
301 | else | |
302 | { | |
303 | low[i] = operand_subword (operands[i], 0, 0, DImode); | |
304 | operands[i] = operand_subword (operands[i], 1, 0, DImode); | |
305 | } | |
306 | } | |
307 | } | |
308 | \f | |
2fd58acb | 309 | void |
d001241c | 310 | print_operand_address (FILE * file, rtx addr) |
9c21a7e7 | 311 | { |
c4e75102 | 312 | rtx orig = addr; |
d001241c | 313 | rtx reg1, breg, ireg; |
9c21a7e7 RS |
314 | rtx offset; |
315 | ||
316 | retry: | |
317 | switch (GET_CODE (addr)) | |
318 | { | |
319 | case MEM: | |
320 | fprintf (file, "*"); | |
321 | addr = XEXP (addr, 0); | |
322 | goto retry; | |
323 | ||
324 | case REG: | |
325 | fprintf (file, "(%s)", reg_names[REGNO (addr)]); | |
326 | break; | |
327 | ||
328 | case PRE_DEC: | |
329 | fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); | |
330 | break; | |
331 | ||
332 | case POST_INC: | |
333 | fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); | |
334 | break; | |
335 | ||
336 | case PLUS: | |
337 | /* There can be either two or three things added here. One must be a | |
338 | REG. One can be either a REG or a MULT of a REG and an appropriate | |
339 | constant, and the third can only be a constant or a MEM. | |
340 | ||
341 | We get these two or three things and put the constant or MEM in | |
342 | OFFSET, the MULT or REG in IREG, and the REG in BREG. If we have | |
343 | a register and can't tell yet if it is a base or index register, | |
344 | put it into REG1. */ | |
345 | ||
346 | reg1 = 0; ireg = 0; breg = 0; offset = 0; | |
347 | ||
348 | if (CONSTANT_ADDRESS_P (XEXP (addr, 0)) | |
ff9d4590 | 349 | || MEM_P (XEXP (addr, 0))) |
9c21a7e7 RS |
350 | { |
351 | offset = XEXP (addr, 0); | |
352 | addr = XEXP (addr, 1); | |
353 | } | |
354 | else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)) | |
ff9d4590 | 355 | || MEM_P (XEXP (addr, 1))) |
9c21a7e7 RS |
356 | { |
357 | offset = XEXP (addr, 1); | |
358 | addr = XEXP (addr, 0); | |
359 | } | |
360 | else if (GET_CODE (XEXP (addr, 1)) == MULT) | |
361 | { | |
362 | ireg = XEXP (addr, 1); | |
363 | addr = XEXP (addr, 0); | |
364 | } | |
365 | else if (GET_CODE (XEXP (addr, 0)) == MULT) | |
366 | { | |
367 | ireg = XEXP (addr, 0); | |
368 | addr = XEXP (addr, 1); | |
369 | } | |
ff9d4590 | 370 | else if (REG_P (XEXP (addr, 1))) |
9c21a7e7 RS |
371 | { |
372 | reg1 = XEXP (addr, 1); | |
373 | addr = XEXP (addr, 0); | |
374 | } | |
ff9d4590 | 375 | else if (REG_P (XEXP (addr, 0))) |
2d6cb879 TW |
376 | { |
377 | reg1 = XEXP (addr, 0); | |
378 | addr = XEXP (addr, 1); | |
379 | } | |
9c21a7e7 | 380 | else |
90285d8d | 381 | gcc_unreachable (); |
9c21a7e7 | 382 | |
ff9d4590 | 383 | if (REG_P (addr)) |
9c21a7e7 RS |
384 | { |
385 | if (reg1) | |
386 | ireg = addr; | |
387 | else | |
388 | reg1 = addr; | |
389 | } | |
390 | else if (GET_CODE (addr) == MULT) | |
391 | ireg = addr; | |
90285d8d | 392 | else |
9c21a7e7 | 393 | { |
90285d8d | 394 | gcc_assert (GET_CODE (addr) == PLUS); |
9c21a7e7 | 395 | if (CONSTANT_ADDRESS_P (XEXP (addr, 0)) |
ff9d4590 | 396 | || MEM_P (XEXP (addr, 0))) |
9c21a7e7 RS |
397 | { |
398 | if (offset) | |
399 | { | |
d97c1295 | 400 | if (CONST_INT_P (offset)) |
0a81f074 RS |
401 | offset = plus_constant (Pmode, XEXP (addr, 0), |
402 | INTVAL (offset)); | |
9c21a7e7 | 403 | else |
90285d8d | 404 | { |
d97c1295 | 405 | gcc_assert (CONST_INT_P (XEXP (addr, 0))); |
0a81f074 RS |
406 | offset = plus_constant (Pmode, offset, |
407 | INTVAL (XEXP (addr, 0))); | |
90285d8d | 408 | } |
9c21a7e7 RS |
409 | } |
410 | offset = XEXP (addr, 0); | |
411 | } | |
ff9d4590 | 412 | else if (REG_P (XEXP (addr, 0))) |
9c21a7e7 RS |
413 | { |
414 | if (reg1) | |
415 | ireg = reg1, breg = XEXP (addr, 0), reg1 = 0; | |
416 | else | |
417 | reg1 = XEXP (addr, 0); | |
418 | } | |
90285d8d | 419 | else |
9c21a7e7 | 420 | { |
90285d8d NS |
421 | gcc_assert (GET_CODE (XEXP (addr, 0)) == MULT); |
422 | gcc_assert (!ireg); | |
9c21a7e7 RS |
423 | ireg = XEXP (addr, 0); |
424 | } | |
9c21a7e7 RS |
425 | |
426 | if (CONSTANT_ADDRESS_P (XEXP (addr, 1)) | |
ff9d4590 | 427 | || MEM_P (XEXP (addr, 1))) |
9c21a7e7 RS |
428 | { |
429 | if (offset) | |
430 | { | |
d97c1295 | 431 | if (CONST_INT_P (offset)) |
0a81f074 RS |
432 | offset = plus_constant (Pmode, XEXP (addr, 1), |
433 | INTVAL (offset)); | |
9c21a7e7 | 434 | else |
90285d8d | 435 | { |
d97c1295 | 436 | gcc_assert (CONST_INT_P (XEXP (addr, 1))); |
0a81f074 RS |
437 | offset = plus_constant (Pmode, offset, |
438 | INTVAL (XEXP (addr, 1))); | |
90285d8d | 439 | } |
9c21a7e7 RS |
440 | } |
441 | offset = XEXP (addr, 1); | |
442 | } | |
ff9d4590 | 443 | else if (REG_P (XEXP (addr, 1))) |
9c21a7e7 RS |
444 | { |
445 | if (reg1) | |
446 | ireg = reg1, breg = XEXP (addr, 1), reg1 = 0; | |
447 | else | |
448 | reg1 = XEXP (addr, 1); | |
449 | } | |
90285d8d | 450 | else |
9c21a7e7 | 451 | { |
90285d8d NS |
452 | gcc_assert (GET_CODE (XEXP (addr, 1)) == MULT); |
453 | gcc_assert (!ireg); | |
9c21a7e7 RS |
454 | ireg = XEXP (addr, 1); |
455 | } | |
9c21a7e7 | 456 | } |
9c21a7e7 | 457 | |
5e7a8ee0 | 458 | /* If REG1 is nonzero, figure out if it is a base or index register. */ |
9c21a7e7 RS |
459 | if (reg1) |
460 | { | |
c4e75102 MT |
461 | if (breg |
462 | || (flag_pic && GET_CODE (addr) == SYMBOL_REF) | |
463 | || (offset | |
464 | && (MEM_P (offset) | |
465 | || (flag_pic && symbolic_operand (offset, SImode))))) | |
9c21a7e7 | 466 | { |
90285d8d | 467 | gcc_assert (!ireg); |
9c21a7e7 RS |
468 | ireg = reg1; |
469 | } | |
470 | else | |
471 | breg = reg1; | |
472 | } | |
473 | ||
474 | if (offset != 0) | |
c4e75102 MT |
475 | { |
476 | if (flag_pic && symbolic_operand (offset, SImode)) | |
477 | { | |
478 | if (breg && ireg) | |
479 | { | |
480 | debug_rtx (orig); | |
481 | output_operand_lossage ("symbol used with both base and indexed registers"); | |
482 | } | |
483 | ||
484 | #ifdef NO_EXTERNAL_INDIRECT_ADDRESS | |
485 | if (flag_pic > 1 && GET_CODE (offset) == CONST | |
486 | && GET_CODE (XEXP (XEXP (offset, 0), 0)) == SYMBOL_REF | |
487 | && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (offset, 0), 0))) | |
488 | { | |
489 | debug_rtx (orig); | |
490 | output_operand_lossage ("symbol with offset used in PIC mode"); | |
491 | } | |
492 | #endif | |
493 | ||
494 | /* symbol(reg) isn't PIC, but symbol[reg] is. */ | |
495 | if (breg) | |
496 | { | |
497 | ireg = breg; | |
498 | breg = 0; | |
499 | } | |
500 | ||
501 | } | |
502 | ||
503 | output_address (offset); | |
504 | } | |
9c21a7e7 RS |
505 | |
506 | if (breg != 0) | |
507 | fprintf (file, "(%s)", reg_names[REGNO (breg)]); | |
508 | ||
509 | if (ireg != 0) | |
510 | { | |
511 | if (GET_CODE (ireg) == MULT) | |
512 | ireg = XEXP (ireg, 0); | |
ff9d4590 | 513 | gcc_assert (REG_P (ireg)); |
9c21a7e7 RS |
514 | fprintf (file, "[%s]", reg_names[REGNO (ireg)]); |
515 | } | |
516 | break; | |
517 | ||
518 | default: | |
519 | output_addr_const (file, addr); | |
520 | } | |
521 | } | |
c4e75102 MT |
522 | |
523 | void | |
524 | print_operand (FILE *file, rtx x, int code) | |
525 | { | |
526 | if (code == '#') | |
527 | fputc (ASM_DOUBLE_CHAR, file); | |
528 | else if (code == '|') | |
529 | fputs (REGISTER_PREFIX, file); | |
f90b7a5a PB |
530 | else if (code == 'c') |
531 | fputs (cond_name (x), file); | |
c4e75102 MT |
532 | else if (code == 'C') |
533 | fputs (rev_cond_name (x), file); | |
534 | else if (code == 'D' && CONST_INT_P (x) && INTVAL (x) < 0) | |
535 | fprintf (file, "$" NEG_HWI_PRINT_HEX16, INTVAL (x)); | |
536 | else if (code == 'P' && CONST_INT_P (x)) | |
537 | fprintf (file, "$" HOST_WIDE_INT_PRINT_DEC, INTVAL (x) + 1); | |
538 | else if (code == 'N' && CONST_INT_P (x)) | |
539 | fprintf (file, "$" HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x)); | |
540 | /* rotl instruction cannot deal with negative arguments. */ | |
541 | else if (code == 'R' && CONST_INT_P (x)) | |
542 | fprintf (file, "$" HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x)); | |
543 | else if (code == 'H' && CONST_INT_P (x)) | |
544 | fprintf (file, "$%d", (int) (0xffff & ~ INTVAL (x))); | |
545 | else if (code == 'h' && CONST_INT_P (x)) | |
546 | fprintf (file, "$%d", (short) - INTVAL (x)); | |
547 | else if (code == 'B' && CONST_INT_P (x)) | |
548 | fprintf (file, "$%d", (int) (0xff & ~ INTVAL (x))); | |
549 | else if (code == 'b' && CONST_INT_P (x)) | |
550 | fprintf (file, "$%d", (int) (0xff & - INTVAL (x))); | |
551 | else if (code == 'M' && CONST_INT_P (x)) | |
552 | fprintf (file, "$%d", ~((1 << INTVAL (x)) - 1)); | |
a3515605 RH |
553 | else if (code == 'x' && CONST_INT_P (x)) |
554 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); | |
c4e75102 MT |
555 | else if (REG_P (x)) |
556 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
557 | else if (MEM_P (x)) | |
558 | output_address (XEXP (x, 0)); | |
559 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) | |
560 | { | |
561 | char dstr[30]; | |
562 | real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), | |
563 | sizeof (dstr), 0, 1); | |
564 | fprintf (file, "$0f%s", dstr); | |
565 | } | |
566 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) | |
567 | { | |
568 | char dstr[30]; | |
569 | real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), | |
570 | sizeof (dstr), 0, 1); | |
571 | fprintf (file, "$0%c%s", ASM_DOUBLE_CHAR, dstr); | |
572 | } | |
573 | else | |
574 | { | |
575 | if (flag_pic > 1 && symbolic_operand (x, SImode)) | |
576 | { | |
577 | debug_rtx (x); | |
578 | output_operand_lossage ("symbol used as immediate operand"); | |
579 | } | |
580 | putc ('$', file); | |
581 | output_addr_const (file, x); | |
582 | } | |
583 | } | |
9c21a7e7 | 584 | \f |
f90b7a5a PB |
585 | const char * |
586 | cond_name (rtx op) | |
587 | { | |
588 | switch (GET_CODE (op)) | |
589 | { | |
590 | case NE: | |
591 | return "neq"; | |
592 | case EQ: | |
593 | return "eql"; | |
594 | case GE: | |
595 | return "geq"; | |
596 | case GT: | |
597 | return "gtr"; | |
598 | case LE: | |
599 | return "leq"; | |
600 | case LT: | |
601 | return "lss"; | |
602 | case GEU: | |
603 | return "gequ"; | |
604 | case GTU: | |
605 | return "gtru"; | |
606 | case LEU: | |
607 | return "lequ"; | |
608 | case LTU: | |
609 | return "lssu"; | |
610 | ||
611 | default: | |
612 | gcc_unreachable (); | |
613 | } | |
614 | } | |
615 | ||
2fd58acb | 616 | const char * |
0d92b0e4 | 617 | rev_cond_name (rtx op) |
9c21a7e7 RS |
618 | { |
619 | switch (GET_CODE (op)) | |
620 | { | |
621 | case EQ: | |
622 | return "neq"; | |
623 | case NE: | |
624 | return "eql"; | |
625 | case LT: | |
626 | return "geq"; | |
627 | case LE: | |
628 | return "gtr"; | |
629 | case GT: | |
630 | return "leq"; | |
631 | case GE: | |
632 | return "lss"; | |
633 | case LTU: | |
634 | return "gequ"; | |
635 | case LEU: | |
636 | return "gtru"; | |
637 | case GTU: | |
638 | return "lequ"; | |
639 | case GEU: | |
640 | return "lssu"; | |
641 | ||
642 | default: | |
90285d8d | 643 | gcc_unreachable (); |
9c21a7e7 RS |
644 | } |
645 | } | |
d3797078 | 646 | |
c4e75102 MT |
647 | static bool |
648 | vax_float_literal (rtx c) | |
d3797078 | 649 | { |
ef4bddc2 | 650 | machine_mode mode; |
b216cd4a | 651 | REAL_VALUE_TYPE r, s; |
d3797078 | 652 | int i; |
d3797078 RS |
653 | |
654 | if (GET_CODE (c) != CONST_DOUBLE) | |
c4e75102 | 655 | return false; |
d3797078 RS |
656 | |
657 | mode = GET_MODE (c); | |
658 | ||
659 | if (c == const_tiny_rtx[(int) mode][0] | |
660 | || c == const_tiny_rtx[(int) mode][1] | |
661 | || c == const_tiny_rtx[(int) mode][2]) | |
c4e75102 | 662 | return true; |
d3797078 | 663 | |
b216cd4a | 664 | REAL_VALUE_FROM_CONST_DOUBLE (r, c); |
d3797078 | 665 | |
b216cd4a ZW |
666 | for (i = 0; i < 7; i++) |
667 | { | |
668 | int x = 1 << i; | |
90285d8d | 669 | bool ok; |
807e902e | 670 | real_from_integer (&s, mode, x, SIGNED); |
d3797078 | 671 | |
b216cd4a | 672 | if (REAL_VALUES_EQUAL (r, s)) |
c4e75102 | 673 | return true; |
90285d8d NS |
674 | ok = exact_real_inverse (mode, &s); |
675 | gcc_assert (ok); | |
b216cd4a | 676 | if (REAL_VALUES_EQUAL (r, s)) |
c4e75102 | 677 | return true; |
b216cd4a | 678 | } |
c4e75102 | 679 | return false; |
d3797078 RS |
680 | } |
681 | ||
682 | ||
683 | /* Return the cost in cycles of a memory address, relative to register | |
684 | indirect. | |
685 | ||
686 | Each of the following adds the indicated number of cycles: | |
687 | ||
688 | 1 - symbolic address | |
689 | 1 - pre-decrement | |
690 | 1 - indexing and/or offset(register) | |
691 | 2 - indirect */ | |
692 | ||
693 | ||
dcefdf67 | 694 | static int |
d001241c | 695 | vax_address_cost_1 (rtx addr) |
d3797078 RS |
696 | { |
697 | int reg = 0, indexed = 0, indir = 0, offset = 0, predec = 0; | |
698 | rtx plus_op0 = 0, plus_op1 = 0; | |
699 | restart: | |
700 | switch (GET_CODE (addr)) | |
701 | { | |
702 | case PRE_DEC: | |
703 | predec = 1; | |
704 | case REG: | |
705 | case SUBREG: | |
706 | case POST_INC: | |
707 | reg = 1; | |
708 | break; | |
709 | case MULT: | |
710 | indexed = 1; /* 2 on VAX 2 */ | |
711 | break; | |
712 | case CONST_INT: | |
713 | /* byte offsets cost nothing (on a VAX 2, they cost 1 cycle) */ | |
714 | if (offset == 0) | |
76335fef | 715 | offset = (unsigned HOST_WIDE_INT)(INTVAL(addr)+128) > 256; |
d3797078 RS |
716 | break; |
717 | case CONST: | |
718 | case SYMBOL_REF: | |
719 | offset = 1; /* 2 on VAX 2 */ | |
720 | break; | |
721 | case LABEL_REF: /* this is probably a byte offset from the pc */ | |
722 | if (offset == 0) | |
723 | offset = 1; | |
724 | break; | |
725 | case PLUS: | |
726 | if (plus_op0) | |
727 | plus_op1 = XEXP (addr, 0); | |
728 | else | |
729 | plus_op0 = XEXP (addr, 0); | |
730 | addr = XEXP (addr, 1); | |
731 | goto restart; | |
732 | case MEM: | |
733 | indir = 2; /* 3 on VAX 2 */ | |
734 | addr = XEXP (addr, 0); | |
735 | goto restart; | |
2fd58acb KG |
736 | default: |
737 | break; | |
d3797078 RS |
738 | } |
739 | ||
740 | /* Up to 3 things can be added in an address. They are stored in | |
741 | plus_op0, plus_op1, and addr. */ | |
742 | ||
743 | if (plus_op0) | |
744 | { | |
745 | addr = plus_op0; | |
746 | plus_op0 = 0; | |
747 | goto restart; | |
748 | } | |
749 | if (plus_op1) | |
750 | { | |
751 | addr = plus_op1; | |
752 | plus_op1 = 0; | |
753 | goto restart; | |
754 | } | |
755 | /* Indexing and register+offset can both be used (except on a VAX 2) | |
6b857ce3 | 756 | without increasing execution time over either one alone. */ |
d3797078 RS |
757 | if (reg && indexed && offset) |
758 | return reg + indir + offset + predec; | |
759 | return reg + indexed + indir + offset + predec; | |
760 | } | |
761 | ||
dcefdf67 | 762 | static int |
ef4bddc2 | 763 | vax_address_cost (rtx x, machine_mode mode ATTRIBUTE_UNUSED, |
b413068c OE |
764 | addr_space_t as ATTRIBUTE_UNUSED, |
765 | bool speed ATTRIBUTE_UNUSED) | |
dcefdf67 | 766 | { |
ff9d4590 | 767 | return (1 + (REG_P (x) ? 0 : vax_address_cost_1 (x))); |
dcefdf67 RH |
768 | } |
769 | ||
d3797078 RS |
770 | /* Cost of an expression on a VAX. This version has costs tuned for the |
771 | CVAX chip (found in the VAX 3 series) with comments for variations on | |
ccb527e4 | 772 | other models. |
d3797078 | 773 | |
ccb527e4 JDA |
774 | FIXME: The costs need review, particularly for TRUNCATE, FLOAT_EXTEND |
775 | and FLOAT_TRUNCATE. We need a -mcpu option to allow provision of | |
776 | costs on a per cpu basis. */ | |
777 | ||
778 | static bool | |
68f932c4 RS |
779 | vax_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
780 | int *total, bool speed ATTRIBUTE_UNUSED) | |
d3797078 | 781 | { |
ef4bddc2 | 782 | machine_mode mode = GET_MODE (x); |
ccb527e4 | 783 | int i = 0; /* may be modified in switch */ |
6f7d635c | 784 | const char *fmt = GET_RTX_FORMAT (code); /* may be modified in switch */ |
d3797078 RS |
785 | |
786 | switch (code) | |
787 | { | |
3c50106f | 788 | /* On a VAX, constants from 0..63 are cheap because they can use the |
ccb527e4 JDA |
789 | 1 byte literal constant format. Compare to -1 should be made cheap |
790 | so that decrement-and-branch insns can be formed more easily (if | |
791 | the value -1 is copied to a register some decrement-and-branch | |
3c50106f RH |
792 | patterns will not match). */ |
793 | case CONST_INT: | |
794 | if (INTVAL (x) == 0) | |
c4e75102 MT |
795 | { |
796 | *total = 0; | |
797 | return true; | |
798 | } | |
3c50106f | 799 | if (outer_code == AND) |
ccb527e4 | 800 | { |
c4e75102 | 801 | *total = ((unsigned HOST_WIDE_INT) ~INTVAL (x) <= 077) ? 1 : 2; |
ccb527e4 JDA |
802 | return true; |
803 | } | |
804 | if ((unsigned HOST_WIDE_INT) INTVAL (x) <= 077 | |
805 | || (outer_code == COMPARE | |
806 | && INTVAL (x) == -1) | |
807 | || ((outer_code == PLUS || outer_code == MINUS) | |
808 | && (unsigned HOST_WIDE_INT) -INTVAL (x) <= 077)) | |
809 | { | |
810 | *total = 1; | |
811 | return true; | |
812 | } | |
5efb1046 | 813 | /* FALLTHRU */ |
3c50106f RH |
814 | |
815 | case CONST: | |
816 | case LABEL_REF: | |
817 | case SYMBOL_REF: | |
ccb527e4 JDA |
818 | *total = 3; |
819 | return true; | |
3c50106f RH |
820 | |
821 | case CONST_DOUBLE: | |
822 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
ccb527e4 | 823 | *total = vax_float_literal (x) ? 5 : 8; |
3c50106f | 824 | else |
c4e75102 | 825 | *total = ((CONST_DOUBLE_HIGH (x) == 0 |
ccb527e4 JDA |
826 | && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (x) < 64) |
827 | || (outer_code == PLUS | |
828 | && CONST_DOUBLE_HIGH (x) == -1 | |
829 | && (unsigned HOST_WIDE_INT)-CONST_DOUBLE_LOW (x) < 64)) | |
830 | ? 2 : 5; | |
831 | return true; | |
b20f13e9 | 832 | |
d3797078 | 833 | case POST_INC: |
ccb527e4 JDA |
834 | *total = 2; |
835 | return true; /* Implies register operand. */ | |
836 | ||
d3797078 | 837 | case PRE_DEC: |
ccb527e4 JDA |
838 | *total = 3; |
839 | return true; /* Implies register operand. */ | |
840 | ||
d3797078 RS |
841 | case MULT: |
842 | switch (mode) | |
843 | { | |
844 | case DFmode: | |
ccb527e4 | 845 | *total = 16; /* 4 on VAX 9000 */ |
d3797078 RS |
846 | break; |
847 | case SFmode: | |
ccb527e4 | 848 | *total = 9; /* 4 on VAX 9000, 12 on VAX 2 */ |
d3797078 RS |
849 | break; |
850 | case DImode: | |
ccb527e4 | 851 | *total = 16; /* 6 on VAX 9000, 28 on VAX 2 */ |
d3797078 RS |
852 | break; |
853 | case SImode: | |
854 | case HImode: | |
855 | case QImode: | |
ccb527e4 | 856 | *total = 10; /* 3-4 on VAX 9000, 20-28 on VAX 2 */ |
d3797078 | 857 | break; |
2fd58acb | 858 | default: |
ccb527e4 JDA |
859 | *total = MAX_COST; /* Mode is not supported. */ |
860 | return true; | |
d3797078 RS |
861 | } |
862 | break; | |
ccb527e4 | 863 | |
d3797078 | 864 | case UDIV: |
5c41fdfb | 865 | if (mode != SImode) |
ccb527e4 JDA |
866 | { |
867 | *total = MAX_COST; /* Mode is not supported. */ | |
868 | return true; | |
869 | } | |
870 | *total = 17; | |
d3797078 | 871 | break; |
ccb527e4 | 872 | |
d3797078 RS |
873 | case DIV: |
874 | if (mode == DImode) | |
ccb527e4 | 875 | *total = 30; /* Highly variable. */ |
d3797078 RS |
876 | else if (mode == DFmode) |
877 | /* divide takes 28 cycles if the result is not zero, 13 otherwise */ | |
ccb527e4 | 878 | *total = 24; |
d3797078 | 879 | else |
ccb527e4 | 880 | *total = 11; /* 25 on VAX 2 */ |
d3797078 | 881 | break; |
ccb527e4 | 882 | |
d3797078 | 883 | case MOD: |
ccb527e4 | 884 | *total = 23; |
d3797078 | 885 | break; |
ccb527e4 | 886 | |
d3797078 | 887 | case UMOD: |
5c41fdfb | 888 | if (mode != SImode) |
ccb527e4 JDA |
889 | { |
890 | *total = MAX_COST; /* Mode is not supported. */ | |
891 | return true; | |
892 | } | |
893 | *total = 29; | |
d3797078 | 894 | break; |
ccb527e4 | 895 | |
d3797078 | 896 | case FLOAT: |
ccb527e4 JDA |
897 | *total = (6 /* 4 on VAX 9000 */ |
898 | + (mode == DFmode) + (GET_MODE (XEXP (x, 0)) != SImode)); | |
d3797078 | 899 | break; |
ccb527e4 | 900 | |
d3797078 | 901 | case FIX: |
ccb527e4 | 902 | *total = 7; /* 17 on VAX 2 */ |
d3797078 | 903 | break; |
ccb527e4 | 904 | |
d3797078 RS |
905 | case ASHIFT: |
906 | case LSHIFTRT: | |
907 | case ASHIFTRT: | |
908 | if (mode == DImode) | |
ccb527e4 | 909 | *total = 12; |
d3797078 | 910 | else |
ccb527e4 | 911 | *total = 10; /* 6 on VAX 9000 */ |
d3797078 | 912 | break; |
ccb527e4 | 913 | |
d3797078 RS |
914 | case ROTATE: |
915 | case ROTATERT: | |
ccb527e4 | 916 | *total = 6; /* 5 on VAX 2, 4 on VAX 9000 */ |
d97c1295 | 917 | if (CONST_INT_P (XEXP (x, 1))) |
ccb527e4 | 918 | fmt = "e"; /* all constant rotate counts are short */ |
d3797078 | 919 | break; |
ccb527e4 | 920 | |
d3797078 | 921 | case PLUS: |
d3797078 | 922 | case MINUS: |
ccb527e4 | 923 | *total = (mode == DFmode) ? 13 : 8; /* 6/8 on VAX 9000, 16/15 on VAX 2 */ |
76335fef | 924 | /* Small integer operands can use subl2 and addl2. */ |
d97c1295 | 925 | if ((CONST_INT_P (XEXP (x, 1))) |
76335fef JDA |
926 | && (unsigned HOST_WIDE_INT)(INTVAL (XEXP (x, 1)) + 63) < 127) |
927 | fmt = "e"; | |
928 | break; | |
ccb527e4 | 929 | |
d3797078 RS |
930 | case IOR: |
931 | case XOR: | |
ccb527e4 | 932 | *total = 3; |
d3797078 | 933 | break; |
ccb527e4 | 934 | |
d3797078 | 935 | case AND: |
6b857ce3 | 936 | /* AND is special because the first operand is complemented. */ |
ccb527e4 | 937 | *total = 3; |
d97c1295 | 938 | if (CONST_INT_P (XEXP (x, 0))) |
d3797078 | 939 | { |
76335fef | 940 | if ((unsigned HOST_WIDE_INT)~INTVAL (XEXP (x, 0)) > 63) |
ccb527e4 | 941 | *total = 4; |
d3797078 RS |
942 | fmt = "e"; |
943 | i = 1; | |
944 | } | |
945 | break; | |
ccb527e4 | 946 | |
d3797078 RS |
947 | case NEG: |
948 | if (mode == DFmode) | |
ccb527e4 | 949 | *total = 9; |
d3797078 | 950 | else if (mode == SFmode) |
ccb527e4 | 951 | *total = 6; |
d3797078 | 952 | else if (mode == DImode) |
ccb527e4 JDA |
953 | *total = 4; |
954 | else | |
955 | *total = 2; | |
956 | break; | |
957 | ||
d3797078 | 958 | case NOT: |
ccb527e4 JDA |
959 | *total = 2; |
960 | break; | |
961 | ||
d3797078 RS |
962 | case ZERO_EXTRACT: |
963 | case SIGN_EXTRACT: | |
ccb527e4 | 964 | *total = 15; |
d3797078 | 965 | break; |
ccb527e4 | 966 | |
d3797078 RS |
967 | case MEM: |
968 | if (mode == DImode || mode == DFmode) | |
ccb527e4 | 969 | *total = 5; /* 7 on VAX 2 */ |
d3797078 | 970 | else |
ccb527e4 | 971 | *total = 3; /* 4 on VAX 2 */ |
d3797078 | 972 | x = XEXP (x, 0); |
ff9d4590 | 973 | if (!REG_P (x) && GET_CODE (x) != POST_INC) |
ccb527e4 JDA |
974 | *total += vax_address_cost_1 (x); |
975 | return true; | |
976 | ||
977 | case FLOAT_EXTEND: | |
978 | case FLOAT_TRUNCATE: | |
979 | case TRUNCATE: | |
980 | *total = 3; /* FIXME: Costs need to be checked */ | |
d3797078 | 981 | break; |
ccb527e4 JDA |
982 | |
983 | default: | |
984 | return false; | |
d3797078 RS |
985 | } |
986 | ||
d3797078 RS |
987 | /* Now look inside the expression. Operands which are not registers or |
988 | short constants add to the cost. | |
989 | ||
990 | FMT and I may have been adjusted in the switch above for instructions | |
ccb527e4 | 991 | which require special handling. */ |
d3797078 RS |
992 | |
993 | while (*fmt++ == 'e') | |
994 | { | |
ccb527e4 JDA |
995 | rtx op = XEXP (x, i); |
996 | ||
997 | i += 1; | |
d3797078 RS |
998 | code = GET_CODE (op); |
999 | ||
1000 | /* A NOT is likely to be found as the first operand of an AND | |
1001 | (in which case the relevant cost is of the operand inside | |
1002 | the not) and not likely to be found anywhere else. */ | |
1003 | if (code == NOT) | |
1004 | op = XEXP (op, 0), code = GET_CODE (op); | |
1005 | ||
1006 | switch (code) | |
1007 | { | |
1008 | case CONST_INT: | |
76335fef JDA |
1009 | if ((unsigned HOST_WIDE_INT)INTVAL (op) > 63 |
1010 | && GET_MODE (x) != QImode) | |
ccb527e4 | 1011 | *total += 1; /* 2 on VAX 2 */ |
d3797078 RS |
1012 | break; |
1013 | case CONST: | |
1014 | case LABEL_REF: | |
1015 | case SYMBOL_REF: | |
ccb527e4 | 1016 | *total += 1; /* 2 on VAX 2 */ |
d3797078 RS |
1017 | break; |
1018 | case CONST_DOUBLE: | |
1019 | if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT) | |
1020 | { | |
1021 | /* Registers are faster than floating point constants -- even | |
1022 | those constants which can be encoded in a single byte. */ | |
1023 | if (vax_float_literal (op)) | |
ccb527e4 | 1024 | *total += 1; |
d3797078 | 1025 | else |
ccb527e4 | 1026 | *total += (GET_MODE (x) == DFmode) ? 3 : 2; |
d3797078 RS |
1027 | } |
1028 | else | |
1029 | { | |
1030 | if (CONST_DOUBLE_HIGH (op) != 0 | |
c4e75102 | 1031 | || (unsigned HOST_WIDE_INT)CONST_DOUBLE_LOW (op) > 63) |
ccb527e4 | 1032 | *total += 2; |
d3797078 RS |
1033 | } |
1034 | break; | |
1035 | case MEM: | |
ccb527e4 | 1036 | *total += 1; /* 2 on VAX 2 */ |
ff9d4590 | 1037 | if (!REG_P (XEXP (op, 0))) |
ccb527e4 | 1038 | *total += vax_address_cost_1 (XEXP (op, 0)); |
d3797078 RS |
1039 | break; |
1040 | case REG: | |
1041 | case SUBREG: | |
1042 | break; | |
1043 | default: | |
ccb527e4 | 1044 | *total += 1; |
d3797078 RS |
1045 | break; |
1046 | } | |
1047 | } | |
3c50106f RH |
1048 | return true; |
1049 | } | |
ebea352b | 1050 | \f |
b9962e0a RH |
1051 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. |
1052 | Used for C++ multiple inheritance. | |
1053 | .mask ^m<r2,r3,r4,r5,r6,r7,r8,r9,r10,r11> #conservative entry mask | |
1054 | addl2 $DELTA, 4(ap) #adjust first argument | |
1055 | jmp FUNCTION+2 #jump beyond FUNCTION's entry mask | |
1056 | */ | |
1057 | ||
3961e8fe | 1058 | static void |
0d92b0e4 | 1059 | vax_output_mi_thunk (FILE * file, |
c4e75102 MT |
1060 | tree thunk ATTRIBUTE_UNUSED, |
1061 | HOST_WIDE_INT delta, | |
1062 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
1063 | tree function) | |
483ab821 | 1064 | { |
4a0a75dd | 1065 | fprintf (file, "\t.word 0x0ffc\n\taddl2 $" HOST_WIDE_INT_PRINT_DEC, delta); |
eb0424da | 1066 | asm_fprintf (file, ",4(%Rap)\n"); |
b20f13e9 MT |
1067 | fprintf (file, "\tjmp "); |
1068 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
1069 | fprintf (file, "+2\n"); | |
483ab821 | 1070 | } |
f289e226 KH |
1071 | \f |
1072 | static rtx | |
1073 | vax_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
1074 | int incoming ATTRIBUTE_UNUSED) | |
1075 | { | |
1076 | return gen_rtx_REG (Pmode, VAX_STRUCT_VALUE_REGNUM); | |
1077 | } | |
af0ec113 | 1078 | |
c4e75102 MT |
1079 | static rtx |
1080 | vax_builtin_setjmp_frame_value (void) | |
1081 | { | |
1082 | return hard_frame_pointer_rtx; | |
1083 | } | |
1084 | ||
af0ec113 KH |
1085 | /* Worker function for NOTICE_UPDATE_CC. */ |
1086 | ||
1087 | void | |
1088 | vax_notice_update_cc (rtx exp, rtx insn ATTRIBUTE_UNUSED) | |
1089 | { | |
1090 | if (GET_CODE (exp) == SET) | |
1091 | { | |
1092 | if (GET_CODE (SET_SRC (exp)) == CALL) | |
1093 | CC_STATUS_INIT; | |
1094 | else if (GET_CODE (SET_DEST (exp)) != ZERO_EXTRACT | |
1095 | && GET_CODE (SET_DEST (exp)) != PC) | |
1096 | { | |
1097 | cc_status.flags = 0; | |
1098 | /* The integer operations below don't set carry or | |
1099 | set it in an incompatible way. That's ok though | |
1100 | as the Z bit is all we need when doing unsigned | |
1101 | comparisons on the result of these insns (since | |
1102 | they're always with 0). Set CC_NO_OVERFLOW to | |
1103 | generate the correct unsigned branches. */ | |
1104 | switch (GET_CODE (SET_SRC (exp))) | |
1105 | { | |
1106 | case NEG: | |
1107 | if (GET_MODE_CLASS (GET_MODE (exp)) == MODE_FLOAT) | |
b20f13e9 | 1108 | break; |
af0ec113 KH |
1109 | case AND: |
1110 | case IOR: | |
1111 | case XOR: | |
1112 | case NOT: | |
1113 | case MEM: | |
1114 | case REG: | |
1115 | cc_status.flags = CC_NO_OVERFLOW; | |
1116 | break; | |
1117 | default: | |
1118 | break; | |
1119 | } | |
1120 | cc_status.value1 = SET_DEST (exp); | |
1121 | cc_status.value2 = SET_SRC (exp); | |
1122 | } | |
1123 | } | |
1124 | else if (GET_CODE (exp) == PARALLEL | |
1125 | && GET_CODE (XVECEXP (exp, 0, 0)) == SET) | |
1126 | { | |
1127 | if (GET_CODE (SET_SRC (XVECEXP (exp, 0, 0))) == CALL) | |
1128 | CC_STATUS_INIT; | |
1129 | else if (GET_CODE (SET_DEST (XVECEXP (exp, 0, 0))) != PC) | |
1130 | { | |
1131 | cc_status.flags = 0; | |
1132 | cc_status.value1 = SET_DEST (XVECEXP (exp, 0, 0)); | |
1133 | cc_status.value2 = SET_SRC (XVECEXP (exp, 0, 0)); | |
1134 | } | |
1135 | else | |
1136 | /* PARALLELs whose first element sets the PC are aob, | |
1137 | sob insns. They do change the cc's. */ | |
1138 | CC_STATUS_INIT; | |
1139 | } | |
1140 | else | |
1141 | CC_STATUS_INIT; | |
ff9d4590 | 1142 | if (cc_status.value1 && REG_P (cc_status.value1) |
af0ec113 KH |
1143 | && cc_status.value2 |
1144 | && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) | |
1145 | cc_status.value2 = 0; | |
ff9d4590 | 1146 | if (cc_status.value1 && MEM_P (cc_status.value1) |
af0ec113 | 1147 | && cc_status.value2 |
ff9d4590 | 1148 | && MEM_P (cc_status.value2)) |
af0ec113 KH |
1149 | cc_status.value2 = 0; |
1150 | /* Actual condition, one line up, should be that value2's address | |
1151 | depends on value1, but that is too much of a pain. */ | |
1152 | } | |
20acd226 SB |
1153 | |
1154 | /* Output integer move instructions. */ | |
1155 | ||
1156 | const char * | |
1157 | vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands, | |
ef4bddc2 | 1158 | machine_mode mode) |
20acd226 | 1159 | { |
c4e75102 MT |
1160 | rtx hi[3], lo[3]; |
1161 | const char *pattern_hi, *pattern_lo; | |
1162 | ||
20acd226 SB |
1163 | switch (mode) |
1164 | { | |
c4e75102 MT |
1165 | case DImode: |
1166 | if (operands[1] == const0_rtx) | |
1167 | return "clrq %0"; | |
1168 | if (TARGET_QMATH && optimize_size | |
1169 | && (CONST_INT_P (operands[1]) | |
1170 | || GET_CODE (operands[1]) == CONST_DOUBLE)) | |
1171 | { | |
1172 | unsigned HOST_WIDE_INT hval, lval; | |
1173 | int n; | |
1174 | ||
1175 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
1176 | { | |
1177 | gcc_assert (HOST_BITS_PER_WIDE_INT != 64); | |
1178 | ||
1179 | /* Make sure only the low 32 bits are valid. */ | |
1180 | lval = CONST_DOUBLE_LOW (operands[1]) & 0xffffffff; | |
1181 | hval = CONST_DOUBLE_HIGH (operands[1]) & 0xffffffff; | |
1182 | } | |
1183 | else | |
1184 | { | |
1185 | lval = INTVAL (operands[1]); | |
1186 | hval = 0; | |
1187 | } | |
1188 | ||
1189 | /* Here we see if we are trying to see if the 64bit value is really | |
1190 | a 6bit shifted some arbitrary amount. If so, we can use ashq to | |
1191 | shift it to the correct value saving 7 bytes (1 addr-mode-byte + | |
1192 | 8 bytes - 1 shift byte - 1 short literal byte. */ | |
1193 | if (lval != 0 | |
1194 | && (n = exact_log2 (lval & (- lval))) != -1 | |
1195 | && (lval >> n) < 64) | |
1196 | { | |
1197 | lval >>= n; | |
1198 | ||
c4e75102 MT |
1199 | /* On 32bit platforms, if the 6bits didn't overflow into the |
1200 | upper 32bit value that value better be 0. If we have | |
1201 | overflowed, make sure it wasn't too much. */ | |
ce7190e5 | 1202 | if (HOST_BITS_PER_WIDE_INT == 32 && hval != 0) |
c4e75102 MT |
1203 | { |
1204 | if (n <= 26 || hval >= ((unsigned)1 << (n - 26))) | |
1205 | n = 0; /* failure */ | |
1206 | else | |
1207 | lval |= hval << (32 - n); | |
1208 | } | |
c4e75102 MT |
1209 | /* If n is 0, then ashq is not the best way to emit this. */ |
1210 | if (n > 0) | |
1211 | { | |
1212 | operands[1] = GEN_INT (lval); | |
1213 | operands[2] = GEN_INT (n); | |
7691132c | 1214 | return "ashq %2,%D1,%0"; |
c4e75102 MT |
1215 | } |
1216 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1217 | } | |
1218 | /* On 32bit platforms, if the low 32bit value is 0, checkout the | |
1219 | upper 32bit value. */ | |
1220 | else if (hval != 0 | |
1221 | && (n = exact_log2 (hval & (- hval)) - 1) != -1 | |
1222 | && (hval >> n) < 64) | |
1223 | { | |
1224 | operands[1] = GEN_INT (hval >> n); | |
1225 | operands[2] = GEN_INT (n + 32); | |
7691132c | 1226 | return "ashq %2,%D1,%0"; |
c4e75102 MT |
1227 | #endif |
1228 | } | |
1229 | } | |
1230 | ||
1231 | if (TARGET_QMATH | |
1232 | && (!MEM_P (operands[0]) | |
1233 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC | |
1234 | || GET_CODE (XEXP (operands[0], 0)) == POST_INC | |
1235 | || !illegal_addsub_di_memory_operand (operands[0], DImode)) | |
1236 | && ((CONST_INT_P (operands[1]) | |
1237 | && (unsigned HOST_WIDE_INT) INTVAL (operands[1]) >= 64) | |
1238 | || GET_CODE (operands[1]) == CONST_DOUBLE)) | |
1239 | { | |
1240 | hi[0] = operands[0]; | |
1241 | hi[1] = operands[1]; | |
1242 | ||
1243 | split_quadword_operands (insn, SET, hi, lo, 2); | |
1244 | ||
1245 | pattern_lo = vax_output_int_move (NULL, lo, SImode); | |
1246 | pattern_hi = vax_output_int_move (NULL, hi, SImode); | |
1247 | ||
1248 | /* The patterns are just movl/movl or pushl/pushl then a movq will | |
1249 | be shorter (1 opcode byte + 1 addrmode byte + 8 immediate value | |
1250 | bytes .vs. 2 opcode bytes + 2 addrmode bytes + 8 immediate value | |
1251 | value bytes. */ | |
1252 | if ((!strncmp (pattern_lo, "movl", 4) | |
1253 | && !strncmp (pattern_hi, "movl", 4)) | |
1254 | || (!strncmp (pattern_lo, "pushl", 5) | |
1255 | && !strncmp (pattern_hi, "pushl", 5))) | |
1256 | return "movq %1,%0"; | |
1257 | ||
1258 | if (MEM_P (operands[0]) | |
1259 | && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) | |
1260 | { | |
1261 | output_asm_insn (pattern_hi, hi); | |
1262 | operands[0] = lo[0]; | |
1263 | operands[1] = lo[1]; | |
1264 | operands[2] = lo[2]; | |
1265 | return pattern_lo; | |
1266 | } | |
1267 | else | |
1268 | { | |
1269 | output_asm_insn (pattern_lo, lo); | |
1270 | operands[0] = hi[0]; | |
1271 | operands[1] = hi[1]; | |
1272 | operands[2] = hi[2]; | |
1273 | return pattern_hi; | |
1274 | } | |
1275 | } | |
1276 | return "movq %1,%0"; | |
1277 | ||
20acd226 | 1278 | case SImode: |
c4e75102 | 1279 | if (symbolic_operand (operands[1], SImode)) |
20acd226 SB |
1280 | { |
1281 | if (push_operand (operands[0], SImode)) | |
1282 | return "pushab %a1"; | |
1283 | return "movab %a1,%0"; | |
1284 | } | |
c4e75102 | 1285 | |
20acd226 | 1286 | if (operands[1] == const0_rtx) |
c4e75102 MT |
1287 | { |
1288 | if (push_operand (operands[1], SImode)) | |
1289 | return "pushl %1"; | |
1290 | return "clrl %0"; | |
1291 | } | |
1292 | ||
d97c1295 | 1293 | if (CONST_INT_P (operands[1]) |
c4e75102 | 1294 | && (unsigned HOST_WIDE_INT) INTVAL (operands[1]) >= 64) |
20acd226 | 1295 | { |
c4e75102 MT |
1296 | HOST_WIDE_INT i = INTVAL (operands[1]); |
1297 | int n; | |
1298 | if ((unsigned HOST_WIDE_INT)(~i) < 64) | |
20acd226 | 1299 | return "mcoml %N1,%0"; |
c4e75102 | 1300 | if ((unsigned HOST_WIDE_INT)i < 0x100) |
20acd226 SB |
1301 | return "movzbl %1,%0"; |
1302 | if (i >= -0x80 && i < 0) | |
1303 | return "cvtbl %1,%0"; | |
c4e75102 MT |
1304 | if (optimize_size |
1305 | && (n = exact_log2 (i & (-i))) != -1 | |
1306 | && ((unsigned HOST_WIDE_INT)i >> n) < 64) | |
1307 | { | |
1308 | operands[1] = GEN_INT ((unsigned HOST_WIDE_INT)i >> n); | |
1309 | operands[2] = GEN_INT (n); | |
1310 | return "ashl %2,%1,%0"; | |
1311 | } | |
1312 | if ((unsigned HOST_WIDE_INT)i < 0x10000) | |
20acd226 SB |
1313 | return "movzwl %1,%0"; |
1314 | if (i >= -0x8000 && i < 0) | |
1315 | return "cvtwl %1,%0"; | |
1316 | } | |
1317 | if (push_operand (operands[0], SImode)) | |
1318 | return "pushl %1"; | |
1319 | return "movl %1,%0"; | |
1320 | ||
1321 | case HImode: | |
d97c1295 | 1322 | if (CONST_INT_P (operands[1])) |
20acd226 | 1323 | { |
c4e75102 | 1324 | HOST_WIDE_INT i = INTVAL (operands[1]); |
20acd226 SB |
1325 | if (i == 0) |
1326 | return "clrw %0"; | |
c4e75102 | 1327 | else if ((unsigned HOST_WIDE_INT)i < 64) |
20acd226 | 1328 | return "movw %1,%0"; |
c4e75102 | 1329 | else if ((unsigned HOST_WIDE_INT)~i < 64) |
20acd226 | 1330 | return "mcomw %H1,%0"; |
c4e75102 | 1331 | else if ((unsigned HOST_WIDE_INT)i < 256) |
20acd226 | 1332 | return "movzbw %1,%0"; |
c4e75102 MT |
1333 | else if (i >= -0x80 && i < 0) |
1334 | return "cvtbw %1,%0"; | |
20acd226 SB |
1335 | } |
1336 | return "movw %1,%0"; | |
1337 | ||
1338 | case QImode: | |
d97c1295 | 1339 | if (CONST_INT_P (operands[1])) |
20acd226 | 1340 | { |
c4e75102 | 1341 | HOST_WIDE_INT i = INTVAL (operands[1]); |
20acd226 SB |
1342 | if (i == 0) |
1343 | return "clrb %0"; | |
c4e75102 | 1344 | else if ((unsigned HOST_WIDE_INT)~i < 64) |
20acd226 SB |
1345 | return "mcomb %B1,%0"; |
1346 | } | |
1347 | return "movb %1,%0"; | |
1348 | ||
1349 | default: | |
1350 | gcc_unreachable (); | |
1351 | } | |
1352 | } | |
1353 | ||
1354 | /* Output integer add instructions. | |
1355 | ||
1356 | The space-time-opcode tradeoffs for addition vary by model of VAX. | |
1357 | ||
1358 | On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3", | |
1359 | but it not faster on other models. | |
1360 | ||
1361 | "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is | |
1362 | faster on a VAX 3, but some VAXen (e.g. VAX 9000) will stall if | |
1363 | a register is used in an address too soon after it is set. | |
1364 | Compromise by using movab only when it is shorter than the add | |
1365 | or the base register in the address is one of sp, ap, and fp, | |
1366 | which are not modified very often. */ | |
1367 | ||
1368 | const char * | |
ef4bddc2 | 1369 | vax_output_int_add (rtx insn, rtx *operands, machine_mode mode) |
20acd226 SB |
1370 | { |
1371 | switch (mode) | |
1372 | { | |
c4e75102 MT |
1373 | case DImode: |
1374 | { | |
1375 | rtx low[3]; | |
1376 | const char *pattern; | |
1377 | int carry = 1; | |
1378 | bool sub; | |
1379 | ||
1380 | if (TARGET_QMATH && 0) | |
1381 | debug_rtx (insn); | |
1382 | ||
1383 | split_quadword_operands (insn, PLUS, operands, low, 3); | |
1384 | ||
1385 | if (TARGET_QMATH) | |
1386 | { | |
1387 | gcc_assert (rtx_equal_p (operands[0], operands[1])); | |
1388 | #ifdef NO_EXTERNAL_INDIRECT_ADDRESSS | |
1389 | gcc_assert (!flag_pic || !external_memory_operand (low[2], SImode)); | |
1390 | gcc_assert (!flag_pic || !external_memory_operand (low[0], SImode)); | |
1391 | #endif | |
1392 | ||
1393 | /* No reason to add a 0 to the low part and thus no carry, so just | |
1394 | emit the appropriate add/sub instruction. */ | |
1395 | if (low[2] == const0_rtx) | |
1396 | return vax_output_int_add (NULL, operands, SImode); | |
1397 | ||
1398 | /* Are we doing addition or subtraction? */ | |
1399 | sub = CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0; | |
1400 | ||
1401 | /* We can't use vax_output_int_add since some the patterns don't | |
1402 | modify the carry bit. */ | |
1403 | if (sub) | |
1404 | { | |
1405 | if (low[2] == constm1_rtx) | |
1406 | pattern = "decl %0"; | |
1407 | else | |
1408 | pattern = "subl2 $%n2,%0"; | |
1409 | } | |
1410 | else | |
1411 | { | |
1412 | if (low[2] == const1_rtx) | |
1413 | pattern = "incl %0"; | |
1414 | else | |
1415 | pattern = "addl2 %2,%0"; | |
1416 | } | |
1417 | output_asm_insn (pattern, low); | |
1418 | ||
1419 | /* In 2's complement, -n = ~n + 1. Since we are dealing with | |
1420 | two 32bit parts, we complement each and then add one to | |
1421 | low part. We know that the low part can't overflow since | |
1422 | it's value can never be 0. */ | |
1423 | if (sub) | |
1424 | return "sbwc %N2,%0"; | |
1425 | return "adwc %2,%0"; | |
1426 | } | |
1427 | ||
1428 | /* Add low parts. */ | |
1429 | if (rtx_equal_p (operands[0], operands[1])) | |
1430 | { | |
1431 | if (low[2] == const0_rtx) | |
1432 | /* Should examine operand, punt if not POST_INC. */ | |
1433 | pattern = "tstl %0", carry = 0; | |
1434 | else if (low[2] == const1_rtx) | |
1435 | pattern = "incl %0"; | |
1436 | else | |
1437 | pattern = "addl2 %2,%0"; | |
1438 | } | |
1439 | else | |
1440 | { | |
1441 | if (low[2] == const0_rtx) | |
1442 | pattern = "movl %1,%0", carry = 0; | |
1443 | else | |
1444 | pattern = "addl3 %2,%1,%0"; | |
1445 | } | |
1446 | if (pattern) | |
1447 | output_asm_insn (pattern, low); | |
1448 | if (!carry) | |
1449 | /* If CARRY is 0, we don't have any carry value to worry about. */ | |
1450 | return get_insn_template (CODE_FOR_addsi3, insn); | |
1451 | /* %0 = C + %1 + %2 */ | |
1452 | if (!rtx_equal_p (operands[0], operands[1])) | |
1453 | output_asm_insn ((operands[1] == const0_rtx | |
1454 | ? "clrl %0" | |
1455 | : "movl %1,%0"), operands); | |
1456 | return "adwc %2,%0"; | |
1457 | } | |
1458 | ||
20acd226 SB |
1459 | case SImode: |
1460 | if (rtx_equal_p (operands[0], operands[1])) | |
1461 | { | |
1462 | if (operands[2] == const1_rtx) | |
1463 | return "incl %0"; | |
1464 | if (operands[2] == constm1_rtx) | |
1465 | return "decl %0"; | |
d97c1295 | 1466 | if (CONST_INT_P (operands[2]) |
c4e75102 | 1467 | && (unsigned HOST_WIDE_INT) (- INTVAL (operands[2])) < 64) |
20acd226 | 1468 | return "subl2 $%n2,%0"; |
d97c1295 | 1469 | if (CONST_INT_P (operands[2]) |
c4e75102 | 1470 | && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 64 |
ff9d4590 | 1471 | && REG_P (operands[1]) |
20acd226 SB |
1472 | && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768) |
1473 | || REGNO (operands[1]) > 11)) | |
1474 | return "movab %c2(%1),%0"; | |
c4e75102 MT |
1475 | if (REG_P (operands[0]) && symbolic_operand (operands[2], SImode)) |
1476 | return "movab %a2[%0],%0"; | |
20acd226 SB |
1477 | return "addl2 %2,%0"; |
1478 | } | |
1479 | ||
1480 | if (rtx_equal_p (operands[0], operands[2])) | |
c4e75102 MT |
1481 | { |
1482 | if (REG_P (operands[0]) && symbolic_operand (operands[1], SImode)) | |
1483 | return "movab %a1[%0],%0"; | |
1484 | return "addl2 %1,%0"; | |
1485 | } | |
20acd226 | 1486 | |
d97c1295 | 1487 | if (CONST_INT_P (operands[2]) |
20acd226 SB |
1488 | && INTVAL (operands[2]) < 32767 |
1489 | && INTVAL (operands[2]) > -32768 | |
ff9d4590 | 1490 | && REG_P (operands[1]) |
20acd226 SB |
1491 | && push_operand (operands[0], SImode)) |
1492 | return "pushab %c2(%1)"; | |
1493 | ||
d97c1295 | 1494 | if (CONST_INT_P (operands[2]) |
c4e75102 | 1495 | && (unsigned HOST_WIDE_INT) (- INTVAL (operands[2])) < 64) |
20acd226 SB |
1496 | return "subl3 $%n2,%1,%0"; |
1497 | ||
d97c1295 | 1498 | if (CONST_INT_P (operands[2]) |
c4e75102 | 1499 | && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 64 |
ff9d4590 | 1500 | && REG_P (operands[1]) |
20acd226 SB |
1501 | && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768) |
1502 | || REGNO (operands[1]) > 11)) | |
1503 | return "movab %c2(%1),%0"; | |
1504 | ||
1505 | /* Add this if using gcc on a VAX 3xxx: | |
1506 | if (REG_P (operands[1]) && REG_P (operands[2])) | |
1507 | return "movab (%1)[%2],%0"; | |
1508 | */ | |
c4e75102 MT |
1509 | |
1510 | if (REG_P (operands[1]) && symbolic_operand (operands[2], SImode)) | |
1511 | { | |
1512 | if (push_operand (operands[0], SImode)) | |
1513 | return "pushab %a2[%1]"; | |
1514 | return "movab %a2[%1],%0"; | |
1515 | } | |
1516 | ||
1517 | if (REG_P (operands[2]) && symbolic_operand (operands[1], SImode)) | |
1518 | { | |
1519 | if (push_operand (operands[0], SImode)) | |
1520 | return "pushab %a1[%2]"; | |
1521 | return "movab %a1[%2],%0"; | |
1522 | } | |
1523 | ||
1524 | if (flag_pic && REG_P (operands[0]) | |
1525 | && symbolic_operand (operands[2], SImode)) | |
1526 | return "movab %a2,%0;addl2 %1,%0"; | |
1527 | ||
1528 | if (flag_pic | |
1529 | && (symbolic_operand (operands[1], SImode) | |
1530 | || symbolic_operand (operands[1], SImode))) | |
1531 | debug_rtx (insn); | |
1532 | ||
20acd226 SB |
1533 | return "addl3 %1,%2,%0"; |
1534 | ||
1535 | case HImode: | |
1536 | if (rtx_equal_p (operands[0], operands[1])) | |
1537 | { | |
1538 | if (operands[2] == const1_rtx) | |
1539 | return "incw %0"; | |
1540 | if (operands[2] == constm1_rtx) | |
1541 | return "decw %0"; | |
d97c1295 | 1542 | if (CONST_INT_P (operands[2]) |
c4e75102 | 1543 | && (unsigned HOST_WIDE_INT) (- INTVAL (operands[2])) < 64) |
20acd226 SB |
1544 | return "subw2 $%n2,%0"; |
1545 | return "addw2 %2,%0"; | |
1546 | } | |
1547 | if (rtx_equal_p (operands[0], operands[2])) | |
1548 | return "addw2 %1,%0"; | |
d97c1295 | 1549 | if (CONST_INT_P (operands[2]) |
c4e75102 | 1550 | && (unsigned HOST_WIDE_INT) (- INTVAL (operands[2])) < 64) |
20acd226 SB |
1551 | return "subw3 $%n2,%1,%0"; |
1552 | return "addw3 %1,%2,%0"; | |
1553 | ||
1554 | case QImode: | |
1555 | if (rtx_equal_p (operands[0], operands[1])) | |
1556 | { | |
1557 | if (operands[2] == const1_rtx) | |
1558 | return "incb %0"; | |
1559 | if (operands[2] == constm1_rtx) | |
1560 | return "decb %0"; | |
d97c1295 | 1561 | if (CONST_INT_P (operands[2]) |
c4e75102 | 1562 | && (unsigned HOST_WIDE_INT) (- INTVAL (operands[2])) < 64) |
20acd226 SB |
1563 | return "subb2 $%n2,%0"; |
1564 | return "addb2 %2,%0"; | |
1565 | } | |
1566 | if (rtx_equal_p (operands[0], operands[2])) | |
1567 | return "addb2 %1,%0"; | |
d97c1295 | 1568 | if (CONST_INT_P (operands[2]) |
c4e75102 | 1569 | && (unsigned HOST_WIDE_INT) (- INTVAL (operands[2])) < 64) |
20acd226 SB |
1570 | return "subb3 $%n2,%1,%0"; |
1571 | return "addb3 %1,%2,%0"; | |
1572 | ||
1573 | default: | |
1574 | gcc_unreachable (); | |
1575 | } | |
1576 | } | |
1577 | ||
c4e75102 | 1578 | const char * |
ef4bddc2 | 1579 | vax_output_int_subtract (rtx insn, rtx *operands, machine_mode mode) |
c4e75102 MT |
1580 | { |
1581 | switch (mode) | |
1582 | { | |
1583 | case DImode: | |
1584 | { | |
1585 | rtx low[3]; | |
1586 | const char *pattern; | |
1587 | int carry = 1; | |
1588 | ||
1589 | if (TARGET_QMATH && 0) | |
1590 | debug_rtx (insn); | |
1591 | ||
1592 | split_quadword_operands (insn, MINUS, operands, low, 3); | |
1593 | ||
1594 | if (TARGET_QMATH) | |
1595 | { | |
1596 | if (operands[1] == const0_rtx && low[1] == const0_rtx) | |
1597 | { | |
1598 | /* Negation is tricky. It's basically complement and increment. | |
1599 | Negate hi, then lo, and subtract the carry back. */ | |
1600 | if ((MEM_P (low[0]) && GET_CODE (XEXP (low[0], 0)) == POST_INC) | |
1601 | || (MEM_P (operands[0]) | |
1602 | && GET_CODE (XEXP (operands[0], 0)) == POST_INC)) | |
1603 | fatal_insn ("illegal operand detected", insn); | |
1604 | output_asm_insn ("mnegl %2,%0", operands); | |
1605 | output_asm_insn ("mnegl %2,%0", low); | |
1606 | return "sbwc $0,%0"; | |
1607 | } | |
1608 | gcc_assert (rtx_equal_p (operands[0], operands[1])); | |
1609 | gcc_assert (rtx_equal_p (low[0], low[1])); | |
1610 | if (low[2] == const1_rtx) | |
1611 | output_asm_insn ("decl %0", low); | |
1612 | else | |
1613 | output_asm_insn ("subl2 %2,%0", low); | |
1614 | return "sbwc %2,%0"; | |
1615 | } | |
1616 | ||
1617 | /* Subtract low parts. */ | |
1618 | if (rtx_equal_p (operands[0], operands[1])) | |
1619 | { | |
1620 | if (low[2] == const0_rtx) | |
1621 | pattern = 0, carry = 0; | |
1622 | else if (low[2] == constm1_rtx) | |
1623 | pattern = "decl %0"; | |
1624 | else | |
1625 | pattern = "subl2 %2,%0"; | |
1626 | } | |
1627 | else | |
1628 | { | |
1629 | if (low[2] == constm1_rtx) | |
1630 | pattern = "decl %0"; | |
1631 | else if (low[2] == const0_rtx) | |
1632 | pattern = get_insn_template (CODE_FOR_movsi, insn), carry = 0; | |
1633 | else | |
1634 | pattern = "subl3 %2,%1,%0"; | |
1635 | } | |
1636 | if (pattern) | |
1637 | output_asm_insn (pattern, low); | |
1638 | if (carry) | |
1639 | { | |
1640 | if (!rtx_equal_p (operands[0], operands[1])) | |
1641 | return "movl %1,%0;sbwc %2,%0"; | |
1642 | return "sbwc %2,%0"; | |
1643 | /* %0 = %2 - %1 - C */ | |
1644 | } | |
1645 | return get_insn_template (CODE_FOR_subsi3, insn); | |
1646 | } | |
1647 | ||
1648 | default: | |
1649 | gcc_unreachable (); | |
1650 | } | |
1651 | } | |
1652 | ||
c4e75102 | 1653 | /* True if X is an rtx for a constant that is a valid address. */ |
fbf55580 | 1654 | |
c4e75102 | 1655 | bool |
fbf55580 MT |
1656 | legitimate_constant_address_p (rtx x) |
1657 | { | |
c4e75102 MT |
1658 | if (GET_CODE (x) == LABEL_REF || GET_CODE (x) == SYMBOL_REF |
1659 | || CONST_INT_P (x) || GET_CODE (x) == HIGH) | |
1660 | return true; | |
1661 | if (GET_CODE (x) != CONST) | |
1662 | return false; | |
1663 | #ifdef NO_EXTERNAL_INDIRECT_ADDRESS | |
1664 | if (flag_pic | |
1665 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
1666 | && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (x, 0), 0))) | |
1667 | return false; | |
1668 | #endif | |
1669 | return true; | |
fbf55580 MT |
1670 | } |
1671 | ||
fbf55580 MT |
1672 | /* The other macros defined here are used only in legitimate_address_p (). */ |
1673 | ||
1674 | /* Nonzero if X is a hard reg that can be used as an index | |
1675 | or, if not strict, if it is a pseudo reg. */ | |
b20f13e9 | 1676 | #define INDEX_REGISTER_P(X, STRICT) \ |
ff9d4590 | 1677 | (REG_P (X) && (!(STRICT) || REGNO_OK_FOR_INDEX_P (REGNO (X)))) |
fbf55580 MT |
1678 | |
1679 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1680 | or, if not strict, if it is a pseudo reg. */ | |
b20f13e9 | 1681 | #define BASE_REGISTER_P(X, STRICT) \ |
ff9d4590 | 1682 | (REG_P (X) && (!(STRICT) || REGNO_OK_FOR_BASE_P (REGNO (X)))) |
fbf55580 MT |
1683 | |
1684 | #ifdef NO_EXTERNAL_INDIRECT_ADDRESS | |
1685 | ||
1686 | /* Re-definition of CONSTANT_ADDRESS_P, which is true only when there | |
1687 | are no SYMBOL_REFs for external symbols present. */ | |
1688 | ||
c4e75102 MT |
1689 | static bool |
1690 | indirectable_constant_address_p (rtx x, bool indirect) | |
fbf55580 | 1691 | { |
c4e75102 MT |
1692 | if (GET_CODE (x) == SYMBOL_REF) |
1693 | return !flag_pic || SYMBOL_REF_LOCAL_P (x) || !indirect; | |
1694 | ||
1695 | if (GET_CODE (x) == CONST) | |
1696 | return !flag_pic | |
1697 | || GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
1698 | || SYMBOL_REF_LOCAL_P (XEXP (XEXP (x, 0), 0)); | |
1699 | ||
1700 | return CONSTANT_ADDRESS_P (x); | |
fbf55580 MT |
1701 | } |
1702 | ||
1703 | #else /* not NO_EXTERNAL_INDIRECT_ADDRESS */ | |
1704 | ||
c4e75102 MT |
1705 | static bool |
1706 | indirectable_constant_address_p (rtx x, bool indirect ATTRIBUTE_UNUSED) | |
fbf55580 MT |
1707 | { |
1708 | return CONSTANT_ADDRESS_P (x); | |
1709 | } | |
1710 | ||
1711 | #endif /* not NO_EXTERNAL_INDIRECT_ADDRESS */ | |
1712 | ||
c4e75102 | 1713 | /* True if X is an address which can be indirected. External symbols |
fbf55580 MT |
1714 | could be in a sharable image library, so we disallow those. */ |
1715 | ||
c4e75102 MT |
1716 | static bool |
1717 | indirectable_address_p (rtx x, bool strict, bool indirect) | |
fbf55580 | 1718 | { |
c4e75102 MT |
1719 | if (indirectable_constant_address_p (x, indirect) |
1720 | || BASE_REGISTER_P (x, strict)) | |
1721 | return true; | |
1722 | if (GET_CODE (x) != PLUS | |
1723 | || !BASE_REGISTER_P (XEXP (x, 0), strict) | |
1724 | || (flag_pic && !CONST_INT_P (XEXP (x, 1)))) | |
1725 | return false; | |
1726 | return indirectable_constant_address_p (XEXP (x, 1), indirect); | |
fbf55580 MT |
1727 | } |
1728 | ||
c4e75102 | 1729 | /* Return true if x is a valid address not using indexing. |
fbf55580 | 1730 | (This much is the easy part.) */ |
c4e75102 MT |
1731 | static bool |
1732 | nonindexed_address_p (rtx x, bool strict) | |
fbf55580 MT |
1733 | { |
1734 | rtx xfoo0; | |
ff9d4590 | 1735 | if (REG_P (x)) |
fbf55580 | 1736 | { |
c4e75102 | 1737 | if (! reload_in_progress |
f2034d06 JL |
1738 | || reg_equiv_mem (REGNO (x)) == 0 |
1739 | || indirectable_address_p (reg_equiv_mem (REGNO (x)), strict, false)) | |
c4e75102 | 1740 | return true; |
fbf55580 | 1741 | } |
c4e75102 MT |
1742 | if (indirectable_constant_address_p (x, false)) |
1743 | return true; | |
1744 | if (indirectable_address_p (x, strict, false)) | |
1745 | return true; | |
fbf55580 | 1746 | xfoo0 = XEXP (x, 0); |
c4e75102 MT |
1747 | if (MEM_P (x) && indirectable_address_p (xfoo0, strict, true)) |
1748 | return true; | |
fbf55580 MT |
1749 | if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC) |
1750 | && BASE_REGISTER_P (xfoo0, strict)) | |
c4e75102 MT |
1751 | return true; |
1752 | return false; | |
fbf55580 MT |
1753 | } |
1754 | ||
c4e75102 | 1755 | /* True if PROD is either a reg times size of mode MODE and MODE is less |
fbf55580 MT |
1756 | than or equal 8 bytes, or just a reg if MODE is one byte. */ |
1757 | ||
c4e75102 | 1758 | static bool |
ef4bddc2 | 1759 | index_term_p (rtx prod, machine_mode mode, bool strict) |
fbf55580 MT |
1760 | { |
1761 | rtx xfoo0, xfoo1; | |
1762 | ||
1763 | if (GET_MODE_SIZE (mode) == 1) | |
1764 | return BASE_REGISTER_P (prod, strict); | |
1765 | ||
1766 | if (GET_CODE (prod) != MULT || GET_MODE_SIZE (mode) > 8) | |
c4e75102 | 1767 | return false; |
fbf55580 MT |
1768 | |
1769 | xfoo0 = XEXP (prod, 0); | |
1770 | xfoo1 = XEXP (prod, 1); | |
1771 | ||
d97c1295 | 1772 | if (CONST_INT_P (xfoo0) |
fbf55580 MT |
1773 | && INTVAL (xfoo0) == (int)GET_MODE_SIZE (mode) |
1774 | && INDEX_REGISTER_P (xfoo1, strict)) | |
c4e75102 | 1775 | return true; |
fbf55580 | 1776 | |
d97c1295 | 1777 | if (CONST_INT_P (xfoo1) |
fbf55580 MT |
1778 | && INTVAL (xfoo1) == (int)GET_MODE_SIZE (mode) |
1779 | && INDEX_REGISTER_P (xfoo0, strict)) | |
c4e75102 | 1780 | return true; |
fbf55580 | 1781 | |
c4e75102 | 1782 | return false; |
fbf55580 MT |
1783 | } |
1784 | ||
c4e75102 | 1785 | /* Return true if X is the sum of a register |
fbf55580 | 1786 | and a valid index term for mode MODE. */ |
c4e75102 | 1787 | static bool |
ef4bddc2 | 1788 | reg_plus_index_p (rtx x, machine_mode mode, bool strict) |
fbf55580 MT |
1789 | { |
1790 | rtx xfoo0, xfoo1; | |
1791 | ||
1792 | if (GET_CODE (x) != PLUS) | |
c4e75102 | 1793 | return false; |
fbf55580 MT |
1794 | |
1795 | xfoo0 = XEXP (x, 0); | |
1796 | xfoo1 = XEXP (x, 1); | |
1797 | ||
1798 | if (BASE_REGISTER_P (xfoo0, strict) && index_term_p (xfoo1, mode, strict)) | |
c4e75102 | 1799 | return true; |
fbf55580 MT |
1800 | |
1801 | if (BASE_REGISTER_P (xfoo1, strict) && index_term_p (xfoo0, mode, strict)) | |
c4e75102 | 1802 | return true; |
fbf55580 | 1803 | |
c4e75102 | 1804 | return false; |
fbf55580 MT |
1805 | } |
1806 | ||
c4e75102 MT |
1807 | /* Return true if xfoo0 and xfoo1 constitute a valid indexed address. */ |
1808 | static bool | |
ef4bddc2 | 1809 | indexable_address_p (rtx xfoo0, rtx xfoo1, machine_mode mode, bool strict) |
c4e75102 MT |
1810 | { |
1811 | if (!CONSTANT_ADDRESS_P (xfoo0)) | |
1812 | return false; | |
1813 | if (BASE_REGISTER_P (xfoo1, strict)) | |
1814 | return !flag_pic || mode == QImode; | |
1815 | if (flag_pic && symbolic_operand (xfoo0, SImode)) | |
1816 | return false; | |
1817 | return reg_plus_index_p (xfoo1, mode, strict); | |
1818 | } | |
1819 | ||
1820 | /* legitimate_address_p returns true if it recognizes an RTL expression "x" | |
fbf55580 MT |
1821 | that is a valid memory address for an instruction. |
1822 | The MODE argument is the machine mode for the MEM expression | |
1823 | that wants to use this address. */ | |
c4e75102 | 1824 | bool |
ef4bddc2 | 1825 | vax_legitimate_address_p (machine_mode mode, rtx x, bool strict) |
fbf55580 MT |
1826 | { |
1827 | rtx xfoo0, xfoo1; | |
1828 | ||
1829 | if (nonindexed_address_p (x, strict)) | |
c4e75102 | 1830 | return true; |
fbf55580 MT |
1831 | |
1832 | if (GET_CODE (x) != PLUS) | |
c4e75102 | 1833 | return false; |
fbf55580 MT |
1834 | |
1835 | /* Handle <address>[index] represented with index-sum outermost */ | |
1836 | ||
1837 | xfoo0 = XEXP (x, 0); | |
1838 | xfoo1 = XEXP (x, 1); | |
1839 | ||
1840 | if (index_term_p (xfoo0, mode, strict) | |
1841 | && nonindexed_address_p (xfoo1, strict)) | |
c4e75102 | 1842 | return true; |
fbf55580 MT |
1843 | |
1844 | if (index_term_p (xfoo1, mode, strict) | |
1845 | && nonindexed_address_p (xfoo0, strict)) | |
c4e75102 | 1846 | return true; |
fbf55580 | 1847 | |
b20f13e9 | 1848 | /* Handle offset(reg)[index] with offset added outermost */ |
fbf55580 | 1849 | |
c4e75102 MT |
1850 | if (indexable_address_p (xfoo0, xfoo1, mode, strict) |
1851 | || indexable_address_p (xfoo1, xfoo0, mode, strict)) | |
1852 | return true; | |
fbf55580 | 1853 | |
c4e75102 | 1854 | return false; |
b20f13e9 | 1855 | } |
fbf55580 | 1856 | |
c4e75102 | 1857 | /* Return true if x (a legitimate address expression) has an effect that |
fbf55580 MT |
1858 | depends on the machine mode it is used for. On the VAX, the predecrement |
1859 | and postincrement address depend thus (the amount of decrement or | |
1860 | increment being the length of the operand) and all indexed address depend | |
1861 | thus (because the index scale factor is the length of the operand). */ | |
1862 | ||
b0f6b612 | 1863 | static bool |
5bfed9a9 | 1864 | vax_mode_dependent_address_p (const_rtx x, addr_space_t as ATTRIBUTE_UNUSED) |
fbf55580 MT |
1865 | { |
1866 | rtx xfoo0, xfoo1; | |
1867 | ||
b9a76028 | 1868 | /* Auto-increment cases are now dealt with generically in recog.c. */ |
fbf55580 | 1869 | if (GET_CODE (x) != PLUS) |
c4e75102 | 1870 | return false; |
fbf55580 MT |
1871 | |
1872 | xfoo0 = XEXP (x, 0); | |
1873 | xfoo1 = XEXP (x, 1); | |
1874 | ||
c4e75102 MT |
1875 | if (CONST_INT_P (xfoo0) && REG_P (xfoo1)) |
1876 | return false; | |
1877 | if (CONST_INT_P (xfoo1) && REG_P (xfoo0)) | |
1878 | return false; | |
1879 | if (!flag_pic && CONSTANT_ADDRESS_P (xfoo0) && REG_P (xfoo1)) | |
1880 | return false; | |
1881 | if (!flag_pic && CONSTANT_ADDRESS_P (xfoo1) && REG_P (xfoo0)) | |
1882 | return false; | |
1883 | ||
1884 | return true; | |
1885 | } | |
1886 | ||
1887 | static rtx | |
ef4bddc2 | 1888 | fixup_mathdi_operand (rtx x, machine_mode mode) |
c4e75102 MT |
1889 | { |
1890 | if (illegal_addsub_di_memory_operand (x, mode)) | |
1891 | { | |
1892 | rtx addr = XEXP (x, 0); | |
1893 | rtx temp = gen_reg_rtx (Pmode); | |
1894 | rtx offset = 0; | |
1895 | #ifdef NO_EXTERNAL_INDIRECT_ADDRESS | |
1896 | if (GET_CODE (addr) == CONST && flag_pic) | |
1897 | { | |
1898 | offset = XEXP (XEXP (addr, 0), 1); | |
1899 | addr = XEXP (XEXP (addr, 0), 0); | |
1900 | } | |
1901 | #endif | |
1902 | emit_move_insn (temp, addr); | |
1903 | if (offset) | |
1904 | temp = gen_rtx_PLUS (Pmode, temp, offset); | |
1905 | x = gen_rtx_MEM (DImode, temp); | |
1906 | } | |
1907 | return x; | |
1908 | } | |
1909 | ||
1910 | void | |
1911 | vax_expand_addsub_di_operands (rtx * operands, enum rtx_code code) | |
1912 | { | |
1913 | int hi_only = operand_subword (operands[2], 0, 0, DImode) == const0_rtx; | |
1914 | rtx temp; | |
1915 | ||
1916 | rtx (*gen_old_insn)(rtx, rtx, rtx); | |
1917 | rtx (*gen_si_insn)(rtx, rtx, rtx); | |
1918 | rtx (*gen_insn)(rtx, rtx, rtx); | |
1919 | ||
1920 | if (code == PLUS) | |
1921 | { | |
1922 | gen_old_insn = gen_adddi3_old; | |
1923 | gen_si_insn = gen_addsi3; | |
1924 | gen_insn = gen_adcdi3; | |
1925 | } | |
1926 | else if (code == MINUS) | |
1927 | { | |
1928 | gen_old_insn = gen_subdi3_old; | |
1929 | gen_si_insn = gen_subsi3; | |
1930 | gen_insn = gen_sbcdi3; | |
1931 | } | |
1932 | else | |
1933 | gcc_unreachable (); | |
1934 | ||
1935 | /* If this is addition (thus operands are commutative) and if there is one | |
1936 | addend that duplicates the desination, we want that addend to be the | |
1937 | first addend. */ | |
1938 | if (code == PLUS | |
1939 | && rtx_equal_p (operands[0], operands[2]) | |
1940 | && !rtx_equal_p (operands[1], operands[2])) | |
1941 | { | |
1942 | temp = operands[2]; | |
1943 | operands[2] = operands[1]; | |
1944 | operands[1] = temp; | |
1945 | } | |
1946 | ||
1947 | if (!TARGET_QMATH) | |
1948 | { | |
1949 | emit_insn ((*gen_old_insn) (operands[0], operands[1], operands[2])); | |
1950 | } | |
1951 | else if (hi_only) | |
1952 | { | |
1953 | if (!rtx_equal_p (operands[0], operands[1]) | |
1954 | && (REG_P (operands[0]) && MEM_P (operands[1]))) | |
1955 | { | |
1956 | emit_move_insn (operands[0], operands[1]); | |
1957 | operands[1] = operands[0]; | |
1958 | } | |
1959 | ||
1960 | operands[0] = fixup_mathdi_operand (operands[0], DImode); | |
1961 | operands[1] = fixup_mathdi_operand (operands[1], DImode); | |
1962 | operands[2] = fixup_mathdi_operand (operands[2], DImode); | |
1963 | ||
1964 | if (!rtx_equal_p (operands[0], operands[1])) | |
1965 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
1966 | operand_subword (operands[1], 0, 0, DImode)); | |
1967 | ||
1968 | emit_insn ((*gen_si_insn) (operand_subword (operands[0], 1, 0, DImode), | |
1969 | operand_subword (operands[1], 1, 0, DImode), | |
1970 | operand_subword (operands[2], 1, 0, DImode))); | |
1971 | } | |
1972 | else | |
1973 | { | |
1974 | /* If are adding the same value together, that's really a multiply by 2, | |
1975 | and that's just a left shift of 1. */ | |
1976 | if (rtx_equal_p (operands[1], operands[2])) | |
1977 | { | |
1978 | gcc_assert (code != MINUS); | |
1979 | emit_insn (gen_ashldi3 (operands[0], operands[1], const1_rtx)); | |
1980 | return; | |
1981 | } | |
1982 | ||
1983 | operands[0] = fixup_mathdi_operand (operands[0], DImode); | |
1984 | ||
1985 | /* If an operand is the same as operand[0], use the operand[0] rtx | |
1986 | because fixup will an equivalent rtx but not an equal one. */ | |
1987 | ||
1988 | if (rtx_equal_p (operands[0], operands[1])) | |
1989 | operands[1] = operands[0]; | |
1990 | else | |
1991 | operands[1] = fixup_mathdi_operand (operands[1], DImode); | |
1992 | ||
1993 | if (rtx_equal_p (operands[0], operands[2])) | |
1994 | operands[2] = operands[0]; | |
1995 | else | |
1996 | operands[2] = fixup_mathdi_operand (operands[2], DImode); | |
1997 | ||
1998 | /* If we are subtracting not from ourselves [d = a - b], and because the | |
1999 | carry ops are two operand only, we would need to do a move prior to | |
2000 | the subtract. And if d == b, we would need a temp otherwise | |
2001 | [d = a, d -= d] and we end up with 0. Instead we rewrite d = a - b | |
2002 | into d = -b, d += a. Since -b can never overflow, even if b == d, | |
2003 | no temp is needed. | |
2004 | ||
2005 | If we are doing addition, since the carry ops are two operand, if | |
2006 | we aren't adding to ourselves, move the first addend to the | |
2007 | destination first. */ | |
2008 | ||
2009 | gcc_assert (operands[1] != const0_rtx || code == MINUS); | |
2010 | if (!rtx_equal_p (operands[0], operands[1]) && operands[1] != const0_rtx) | |
2011 | { | |
2012 | if (code == MINUS && CONSTANT_P (operands[1])) | |
2013 | { | |
2014 | temp = gen_reg_rtx (DImode); | |
2015 | emit_insn (gen_sbcdi3 (operands[0], const0_rtx, operands[2])); | |
2016 | code = PLUS; | |
2017 | gen_insn = gen_adcdi3; | |
2018 | operands[2] = operands[1]; | |
2019 | operands[1] = operands[0]; | |
2020 | } | |
2021 | else | |
2022 | emit_move_insn (operands[0], operands[1]); | |
2023 | } | |
2024 | ||
2025 | /* Subtracting a constant will have been rewritten to an addition of the | |
2026 | negative of that constant before we get here. */ | |
2027 | gcc_assert (!CONSTANT_P (operands[2]) || code == PLUS); | |
2028 | emit_insn ((*gen_insn) (operands[0], operands[1], operands[2])); | |
2029 | } | |
2030 | } | |
2031 | ||
2032 | bool | |
ef4bddc2 | 2033 | adjacent_operands_p (rtx lo, rtx hi, machine_mode mode) |
c4e75102 MT |
2034 | { |
2035 | HOST_WIDE_INT lo_offset; | |
2036 | HOST_WIDE_INT hi_offset; | |
2037 | ||
2038 | if (GET_CODE (lo) != GET_CODE (hi)) | |
2039 | return false; | |
2040 | ||
2041 | if (REG_P (lo)) | |
2042 | return mode == SImode && REGNO (lo) + 1 == REGNO (hi); | |
2043 | if (CONST_INT_P (lo)) | |
2044 | return INTVAL (hi) == 0 && 0 <= INTVAL (lo) && INTVAL (lo) < 64; | |
2045 | if (CONST_INT_P (lo)) | |
2046 | return mode != SImode; | |
2047 | ||
2048 | if (!MEM_P (lo)) | |
2049 | return false; | |
2050 | ||
2051 | if (MEM_VOLATILE_P (lo) || MEM_VOLATILE_P (hi)) | |
2052 | return false; | |
2053 | ||
2054 | lo = XEXP (lo, 0); | |
2055 | hi = XEXP (hi, 0); | |
2056 | ||
2057 | if (GET_CODE (lo) == POST_INC /* || GET_CODE (lo) == PRE_DEC */) | |
2058 | return rtx_equal_p (lo, hi); | |
2059 | ||
2060 | switch (GET_CODE (lo)) | |
2061 | { | |
2062 | case REG: | |
2063 | case SYMBOL_REF: | |
2064 | lo_offset = 0; | |
2065 | break; | |
2066 | case CONST: | |
2067 | lo = XEXP (lo, 0); | |
2068 | /* FALLTHROUGH */ | |
2069 | case PLUS: | |
2070 | if (!CONST_INT_P (XEXP (lo, 1))) | |
2071 | return false; | |
2072 | lo_offset = INTVAL (XEXP (lo, 1)); | |
2073 | lo = XEXP (lo, 0); | |
2074 | break; | |
2075 | default: | |
2076 | return false; | |
2077 | } | |
2078 | ||
2079 | switch (GET_CODE (hi)) | |
2080 | { | |
2081 | case REG: | |
2082 | case SYMBOL_REF: | |
2083 | hi_offset = 0; | |
2084 | break; | |
2085 | case CONST: | |
2086 | hi = XEXP (hi, 0); | |
2087 | /* FALLTHROUGH */ | |
2088 | case PLUS: | |
2089 | if (!CONST_INT_P (XEXP (hi, 1))) | |
2090 | return false; | |
2091 | hi_offset = INTVAL (XEXP (hi, 1)); | |
2092 | hi = XEXP (hi, 0); | |
2093 | break; | |
2094 | default: | |
2095 | return false; | |
2096 | } | |
2097 | ||
2098 | if (GET_CODE (lo) == MULT || GET_CODE (lo) == PLUS) | |
2099 | return false; | |
fbf55580 | 2100 | |
c4e75102 MT |
2101 | return rtx_equal_p (lo, hi) |
2102 | && hi_offset - lo_offset == GET_MODE_SIZE (mode); | |
fbf55580 | 2103 | } |
3814318d RH |
2104 | |
2105 | /* Output assembler code for a block containing the constant parts | |
2106 | of a trampoline, leaving space for the variable parts. */ | |
2107 | ||
2108 | /* On the VAX, the trampoline contains an entry mask and two instructions: | |
2109 | .word NN | |
2110 | movl $STATIC,r0 (store the functions static chain) | |
2111 | jmp *$FUNCTION (jump to function code at address FUNCTION) */ | |
2112 | ||
2113 | static void | |
2114 | vax_asm_trampoline_template (FILE *f ATTRIBUTE_UNUSED) | |
2115 | { | |
2116 | assemble_aligned_integer (2, const0_rtx); | |
2117 | assemble_aligned_integer (2, GEN_INT (0x8fd0)); | |
2118 | assemble_aligned_integer (4, const0_rtx); | |
2119 | assemble_aligned_integer (1, GEN_INT (0x50 + STATIC_CHAIN_REGNUM)); | |
2120 | assemble_aligned_integer (2, GEN_INT (0x9f17)); | |
2121 | assemble_aligned_integer (4, const0_rtx); | |
2122 | } | |
2123 | ||
2124 | /* We copy the register-mask from the function's pure code | |
2125 | to the start of the trampoline. */ | |
2126 | ||
2127 | static void | |
2128 | vax_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) | |
2129 | { | |
2130 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
2131 | rtx mem; | |
2132 | ||
2133 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
2134 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
2135 | ||
2136 | mem = adjust_address (m_tramp, HImode, 0); | |
2137 | emit_move_insn (mem, gen_const_mem (HImode, fnaddr)); | |
2138 | ||
2139 | mem = adjust_address (m_tramp, SImode, 4); | |
2140 | emit_move_insn (mem, cxt); | |
2141 | mem = adjust_address (m_tramp, SImode, 11); | |
0a81f074 | 2142 | emit_move_insn (mem, plus_constant (Pmode, fnaddr, 2)); |
3814318d RH |
2143 | emit_insn (gen_sync_istream ()); |
2144 | } | |
2145 | ||
079e7538 NF |
2146 | /* Value is the number of bytes of arguments automatically |
2147 | popped when returning from a subroutine call. | |
2148 | FUNDECL is the declaration node of the function (as a tree), | |
2149 | FUNTYPE is the data type of the function (as a tree), | |
2150 | or for a library call it is an identifier node for the subroutine name. | |
2151 | SIZE is the number of bytes of arguments passed on the stack. | |
2152 | ||
2153 | On the VAX, the RET insn pops a maximum of 255 args for any function. */ | |
2154 | ||
2155 | static int | |
2156 | vax_return_pops_args (tree fundecl ATTRIBUTE_UNUSED, | |
2157 | tree funtype ATTRIBUTE_UNUSED, int size) | |
2158 | { | |
2159 | return size > 255 * 4 ? 0 : size; | |
2160 | } | |
8f8a46ba NF |
2161 | |
2162 | /* Define where to put the arguments to a function. | |
2163 | Value is zero to push the argument on the stack, | |
2164 | or a hard register in which to store the argument. | |
2165 | ||
2166 | MODE is the argument's machine mode. | |
2167 | TYPE is the data type of the argument (as a tree). | |
2168 | This is null for libcalls where that information may | |
2169 | not be available. | |
2170 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2171 | the preceding args and about the function being called. | |
2172 | NAMED is nonzero if this argument is a named parameter | |
2173 | (otherwise it is an extra parameter matching an ellipsis). */ | |
2174 | ||
2175 | /* On the VAX all args are pushed. */ | |
2176 | ||
2177 | static rtx | |
d5cc9181 | 2178 | vax_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED, |
ef4bddc2 | 2179 | machine_mode mode ATTRIBUTE_UNUSED, |
8f8a46ba NF |
2180 | const_tree type ATTRIBUTE_UNUSED, |
2181 | bool named ATTRIBUTE_UNUSED) | |
2182 | { | |
2183 | return NULL_RTX; | |
2184 | } | |
2185 | ||
2186 | /* Update the data in CUM to advance over an argument of mode MODE and | |
2187 | data type TYPE. (TYPE is null for libcalls where that information | |
2188 | may not be available.) */ | |
2189 | ||
2190 | static void | |
ef4bddc2 | 2191 | vax_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, |
8f8a46ba NF |
2192 | const_tree type, bool named ATTRIBUTE_UNUSED) |
2193 | { | |
d5cc9181 JR |
2194 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
2195 | ||
8f8a46ba NF |
2196 | *cum += (mode != BLKmode |
2197 | ? (GET_MODE_SIZE (mode) + 3) & ~3 | |
2198 | : (int_size_in_bytes (type) + 3) & ~3); | |
2199 | } |