]>
Commit | Line | Data |
---|---|---|
8992df51 | 1 | ;; Scheduling description for GR6. |
fbd26352 | 2 | ;; Copyright (C) 2013-2019 Free Software Foundation, Inc. |
8992df51 | 3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ||
20 | ;; GR6 is a dual-issue, superscalar, out-of-order processor. | |
21 | ;; | |
22 | ;; The GR6 pipeline has 3 major components: | |
23 | ;; 1. The FETCH/DECODE/DISPATCH stages, an in-order front-end, | |
24 | ;; 2. The PROCESS stage, which is the out-of-order core, | |
25 | ;; 3. The STORE stage, an in-order register storage stage. | |
26 | ;; | |
27 | ;; The front-end and the back-end (PROCESS + STORE) are connected through a set | |
28 | ;; of reservation stations which, among other things, serve as buffers for the | |
29 | ;; decoded instructions. The reservation stations are attached to a specific | |
30 | ;; execution unit of the PROCESS stage and the DISPATCH stage is responsible | |
31 | ;; for dispatching the decoded instructions to the appropriate stations. Most | |
32 | ;; execution units have multiple reservation stations, thus making it possible | |
33 | ;; to dispatch two instructions per unit on a given cycle, but only one of them | |
34 | ;; can be executed on the next cycle. | |
35 | ;; | |
36 | ;; Since the core executes the instructions out of order, the most important | |
37 | ;; consideration for performance tuning is to make sure that enough decoded | |
38 | ;; instructions are ready for execution in the PROCESS stage while not stalling | |
39 | ;; the front-end, i.e while not trying to dispatch a decoded instruction to an | |
40 | ;; execution unit whose reservation stations are full. Therefore, we do not | |
41 | ;; model the reservation stations (which is equivalent to pretending that there | |
42 | ;; is only one of them for each execution unit) but only the execution unit, | |
43 | ;; thus preserving some margin in case the unit itself stalls unexpectedly. | |
44 | ||
45 | ;; CPU execution units: | |
46 | ;; | |
47 | ;; inst[1|2] The front-end: 2 instructions can be issued on a given | |
48 | ;; cycle by the FETCH/DECODE/DISPATCH stages, except for | |
49 | ;; the Block Move instructions. | |
50 | ;; | |
51 | ;; mov Move Execution Unit: immediate moves into registers. | |
52 | ;; | |
53 | ;; alu[1|2] The 2 Arithmetic and Logic Units: other instructions | |
54 | ;; operating on the registers. | |
55 | ;; | |
56 | ;; bru Branch Resolution Unit: all branches. | |
57 | ;; | |
58 | ;; mem_wr Memory Write Unit: all writes to memory. | |
59 | ;; | |
60 | ;; mem_rd Memory Read Unit: all reads from memory. | |
61 | ;; | |
62 | ;; mem_eam EAM interface: reads and writes from and to the EAM | |
63 | ;; and reads from the FP registers. | |
64 | ;; | |
65 | ;; eam Extended Arithmetic Module: multiply, divide and | |
66 | ;; 64-bit shifts. | |
67 | ;; | |
68 | ;; fpcu Floating-Point Compare Unit: FP comparisons. | |
69 | ;; | |
70 | ;; fpu[1|2|3|4] The 4 Floating-Point Units: all other instructions | |
71 | ;; operating on the FP registers. | |
72 | ||
73 | (define_automaton "gr6,gr6_fpu") | |
74 | ||
75 | (define_cpu_unit "gr6_inst1, gr6_inst2" "gr6") | |
76 | (define_cpu_unit "gr6_mov" "gr6") | |
77 | (define_cpu_unit "gr6_alu1,gr6_alu2" "gr6") | |
78 | (define_cpu_unit "gr6_bru" "gr6") | |
79 | (define_cpu_unit "gr6_mem_wr,gr6_mem_rd,gr6_mem_eam" "gr6") | |
80 | (define_cpu_unit "gr6_eam" "gr6") | |
81 | (define_cpu_unit "gr6_fpcu" "gr6") | |
82 | (define_cpu_unit "gr6_fpu1,gr6_fpu2,gr6_fpu3,gr6_fpu4" "gr6_fpu") | |
83 | ||
84 | (define_reservation "gr6_issue" "(gr6_inst1 | gr6_inst2)") | |
85 | (define_reservation "gr6_single_issue" "gr6_inst1 + gr6_inst2") | |
86 | ||
87 | (define_insn_reservation "gr6_immediate" 1 | |
88 | (and (eq_attr "cpu" "gr6") | |
89 | (eq_attr "type" "imm_reg")) | |
90 | "gr6_issue + gr6_mov") | |
91 | ||
92 | (define_insn_reservation "gr6_alu" 1 | |
93 | (and (eq_attr "cpu" "gr6") | |
94 | (eq_attr "type" "arith,arith2,logic,cmp")) | |
95 | "gr6_issue + (gr6_alu1 | gr6_alu2)") | |
96 | ||
97 | (define_insn_reservation "gr6_branch" 1 | |
98 | (and (eq_attr "cpu" "gr6") | |
99 | (eq_attr "type" "abs_branch,branch,call,ret,rfi")) | |
100 | "gr6_issue + gr6_bru") | |
101 | ||
102 | (define_insn_reservation "gr6_block_move" 16 | |
103 | (and (eq_attr "cpu" "gr6") | |
104 | (eq_attr "type" "bmi")) | |
105 | "gr6_single_issue*16") | |
106 | ||
107 | (define_insn_reservation "gr6_cpu_other" 1 | |
108 | (and (eq_attr "cpu" "gr6") | |
109 | (eq_attr "type" "dsi,nop")) | |
110 | "gr6_issue") | |
111 | ||
112 | (define_insn_reservation "gr6_write_mem" 1 | |
113 | (and (eq_attr "cpu" "gr6") | |
114 | (eq_attr "type" "reg_mem")) | |
115 | "gr6_issue + gr6_mem_wr") | |
116 | ||
117 | (define_insn_reservation "gr6_read_mem" 6 | |
118 | (and (eq_attr "cpu" "gr6") | |
119 | (eq_attr "type" "mem_reg")) | |
120 | "gr6_issue + gr6_mem_rd, nothing*5") | |
121 | ||
122 | ;; EAM instructions. | |
123 | ||
124 | (define_insn_reservation "gr6_write_eam" 2 | |
125 | (and (eq_attr "cpu" "gr6") | |
126 | (eq_attr "type" "reg_eam")) | |
127 | "gr6_issue + gr6_mem_eam, nothing") | |
128 | ||
129 | (define_reservation "gr6_issue_eam" "gr6_issue + gr6_mem_eam + gr6_eam") | |
130 | ||
131 | (define_insn_reservation "gr6_read_eam" 2 | |
132 | (and (eq_attr "cpu" "gr6") | |
133 | (eq_attr "type" "eam_reg")) | |
134 | "gr6_issue_eam, nothing") | |
135 | ||
136 | (define_insn_reservation "gr6_shiftdi" 2 | |
137 | (and (eq_attr "cpu" "gr6") | |
138 | (eq_attr "type" "shiftdi")) | |
139 | "gr6_issue_eam, gr6_eam") | |
140 | ||
141 | (define_insn_reservation "gr6_mul" 3 | |
142 | (and (eq_attr "cpu" "gr6") | |
143 | (eq_attr "type" "mul")) | |
144 | "gr6_issue_eam, gr6_eam*2") | |
145 | ||
146 | (define_insn_reservation "gr6_div" 34 | |
147 | (and (eq_attr "cpu" "gr6") | |
148 | (eq_attr "type" "div")) | |
149 | "gr6_issue_eam, gr6_eam*33") | |
150 | ||
151 | (define_insn_reservation "gr6_divd" 66 | |
152 | (and (eq_attr "cpu" "gr6") | |
153 | (eq_attr "type" "divd")) | |
154 | "gr6_issue_eam, gr6_eam*65") | |
155 | ||
156 | ;; FPU instructions. | |
157 | ||
158 | (define_insn_reservation "gr6_read_fp" 2 | |
159 | (and (eq_attr "cpu" "gr6") | |
160 | (eq_attr "type" "fp_reg")) | |
161 | "gr6_issue + gr6_mem_eam, nothing") | |
162 | ||
163 | (define_insn_reservation "gr6_cmp_fp" 1 | |
164 | (and (eq_attr "cpu" "gr6") | |
165 | (eq_attr "type" "fcmp")) | |
166 | "gr6_issue + gr6_fpcu") | |
167 | ||
168 | (define_insn_reservation "gr6_fp_1cycle" 1 | |
169 | (and (eq_attr "cpu" "gr6") | |
170 | (eq_attr "type" "fmove,ftoi,itof")) | |
171 | "gr6_issue + gr6_fpu1") | |
172 | ||
173 | (define_insn_reservation "gr6_fp_3cycle" 3 | |
174 | (and (eq_attr "cpu" "gr6") | |
175 | (eq_attr "type" "fp")) | |
176 | "gr6_issue + gr6_fpu2, nothing*2") | |
177 | ||
178 | (define_insn_reservation "gr6_fp_17cycle" 17 | |
179 | (and (eq_attr "cpu" "gr6") | |
180 | (eq_attr "type" "fdiv,fsqrt")) | |
181 | "gr6_issue + gr6_fpu3, gr6_fpu3*14, nothing*2") | |
182 | ||
183 | (define_insn_reservation "gr6_write_fp" 1 | |
184 | (and (eq_attr "cpu" "gr6") | |
185 | (eq_attr "type" "reg_fp")) | |
186 | "gr6_issue + gr6_fpu4") |