[thirdparty/gcc.git] / gcc / config / visium / visium.opt

; Options for Visium.
; Copyright (C) 2005-2016 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it
; under the terms of the GNU General Public License as published
; by the Free Software Foundation; either version 3, or (at your
; option) any later version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3.  If not see
; <http://www.gnu.org/licenses/>.  */

HeaderInclude
config/visium/visium-opts.h

mdebug
Target RejectNegative
Link with libc.a and libdebug.a.

msim
Target RejectNegative
Link with libc.a and libsim.a.

mfpu
Target Report Mask(FPU)
Use hardware FP (default).

mhard-float
Target RejectNegative Mask(FPU) MaskExists
Use hardware FP.

msoft-float
Target RejectNegative InverseMask(FPU)
Do not use hardware FP.

mcpu=
Target RejectNegative Joined Var(visium_cpu_and_features) Enum(visium_processor_type) Init(PROCESSOR_GR5)
Use features of and schedule code for given CPU.

mtune=
Target RejectNegative Joined Var(visium_cpu) Enum(visium_processor_type) Init(PROCESSOR_GR5)
Schedule code for given CPU.

Enum
Name(visium_processor_type) Type(enum processor_type)

EnumValue
Enum(visium_processor_type) String(mcm) Value(PROCESSOR_GR5)

EnumValue
Enum(visium_processor_type) String(gr5) Value(PROCESSOR_GR5)

EnumValue
Enum(visium_processor_type) String(gr6) Value(PROCESSOR_GR6)

msv-mode
Target RejectNegative Report Mask(SV_MODE)
Generate code for the supervisor mode (default).

muser-mode
Target RejectNegative Report InverseMask(SV_MODE)
Generate code for the user mode.

menable-trampolines
Target RejectNegative
Only retained for backward compatibility.

Mask(MCM)
; Generate code for the MCM

Mask(BMI)
; Generate the Block Move Instructions

Mask(FPU_IEEE)
; Generate code for an IEEE-compliant FPU
Commit	Line	Data
8992df51	1	; Options for Visium.
f1717362	2	; Copyright (C) 2005-2016 Free Software Foundation, Inc.
8992df51	3	;
	4	; This file is part of GCC.
	5	;
	6	; GCC is free software; you can redistribute it and/or modify it
	7	; under the terms of the GNU General Public License as published
	8	; by the Free Software Foundation; either version 3, or (at your
	9	; option) any later version.
	10	;
	11	; GCC is distributed in the hope that it will be useful, but WITHOUT
	12	; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	14	; License for more details.
	15	;
	16	; You should have received a copy of the GNU General Public License
	17	; along with GCC; see the file COPYING3. If not see
	18	; <http://www.gnu.org/licenses/>. */
	19
	20	HeaderInclude
	21	config/visium/visium-opts.h
	22
	23	mdebug
	24	Target RejectNegative
8fb42bbc	25	Link with libc.a and libdebug.a.
8992df51	26
	27	msim
	28	Target RejectNegative
8fb42bbc	29	Link with libc.a and libsim.a.
8992df51	30
	31	mfpu
	32	Target Report Mask(FPU)
8fb42bbc	33	Use hardware FP (default).
8992df51	34
	35	mhard-float
	36	Target RejectNegative Mask(FPU) MaskExists
8fb42bbc	37	Use hardware FP.
8992df51	38
	39	msoft-float
	40	Target RejectNegative InverseMask(FPU)
8fb42bbc	41	Do not use hardware FP.
8992df51	42
	43	mcpu=
	44	Target RejectNegative Joined Var(visium_cpu_and_features) Enum(visium_processor_type) Init(PROCESSOR_GR5)
8fb42bbc	45	Use features of and schedule code for given CPU.
8992df51	46
	47	mtune=
	48	Target RejectNegative Joined Var(visium_cpu) Enum(visium_processor_type) Init(PROCESSOR_GR5)
8fb42bbc	49	Schedule code for given CPU.
8992df51	50
	51	Enum
	52	Name(visium_processor_type) Type(enum processor_type)
	53
	54	EnumValue
	55	Enum(visium_processor_type) String(mcm) Value(PROCESSOR_GR5)
	56
	57	EnumValue
	58	Enum(visium_processor_type) String(gr5) Value(PROCESSOR_GR5)
	59
	60	EnumValue
	61	Enum(visium_processor_type) String(gr6) Value(PROCESSOR_GR6)
	62
	63	msv-mode
c7105f0f	64	Target RejectNegative Report Mask(SV_MODE)
8fb42bbc	65	Generate code for the supervisor mode (default).
8992df51	66
8992df51	67	muser-mode
c7105f0f	68	Target RejectNegative Report InverseMask(SV_MODE)
8fb42bbc	69	Generate code for the user mode.
8992df51	70
	71	menable-trampolines
	72	Target RejectNegative
	73	Only retained for backward compatibility.
	74
	75	Mask(MCM)
	76	; Generate code for the MCM
	77
	78	Mask(BMI)
	79	; Generate the Block Move Instructions
	80
	81	Mask(FPU_IEEE)
	82	; Generate code for an IEEE-compliant FPU