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03984308 | 1 | /* Subroutines for insn-output.c for Tensilica's Xtensa architecture. |
23a5b65a | 2 | Copyright (C) 2001-2014 Free Software Foundation, Inc. |
03984308 BW |
3 | Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 9 | Software Foundation; either version 3, or (at your option) any later |
03984308 BW |
10 | version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
03984308 BW |
20 | |
21 | #include "config.h" | |
22 | #include "system.h" | |
4977bab6 ZW |
23 | #include "coretypes.h" |
24 | #include "tm.h" | |
03984308 BW |
25 | #include "rtl.h" |
26 | #include "regs.h" | |
03984308 | 27 | #include "hard-reg-set.h" |
60393bbc AM |
28 | #include "predict.h" |
29 | #include "vec.h" | |
30 | #include "hashtab.h" | |
31 | #include "hash-set.h" | |
32 | #include "machmode.h" | |
33 | #include "input.h" | |
34 | #include "function.h" | |
35 | #include "dominance.h" | |
36 | #include "cfg.h" | |
37 | #include "cfgrtl.h" | |
38 | #include "cfganal.h" | |
39 | #include "lcm.h" | |
40 | #include "cfgbuild.h" | |
41 | #include "cfgcleanup.h" | |
03984308 | 42 | #include "basic-block.h" |
03984308 BW |
43 | #include "insn-config.h" |
44 | #include "conditions.h" | |
45 | #include "insn-flags.h" | |
46 | #include "insn-attr.h" | |
47 | #include "insn-codes.h" | |
48 | #include "recog.h" | |
49 | #include "output.h" | |
50 | #include "tree.h" | |
d8a2d370 DN |
51 | #include "stringpool.h" |
52 | #include "stor-layout.h" | |
53 | #include "calls.h" | |
54 | #include "varasm.h" | |
03984308 BW |
55 | #include "expr.h" |
56 | #include "flags.h" | |
57 | #include "reload.h" | |
58 | #include "tm_p.h" | |
718f9c0f | 59 | #include "diagnostic-core.h" |
03984308 BW |
60 | #include "optabs.h" |
61 | #include "libfuncs.h" | |
07232638 | 62 | #include "ggc.h" |
03984308 BW |
63 | #include "target.h" |
64 | #include "target-def.h" | |
540eaea8 | 65 | #include "langhooks.h" |
2fb9a547 AM |
66 | #include "hash-table.h" |
67 | #include "tree-ssa-alias.h" | |
68 | #include "internal-fn.h" | |
69 | #include "gimple-fold.h" | |
70 | #include "tree-eh.h" | |
71 | #include "gimple-expr.h" | |
72 | #include "is-a.h" | |
18f429e2 | 73 | #include "gimple.h" |
45b0be94 | 74 | #include "gimplify.h" |
e70312d4 | 75 | #include "df.h" |
9b2b7279 | 76 | #include "builtins.h" |
2f36a994 | 77 | #include "rtl-iter.h" |
85d53c1d | 78 | |
03984308 BW |
79 | |
80 | /* Enumeration for all of the relational tests, so that we can build | |
81 | arrays indexed by the test type, and not worry about the order | |
638db43e | 82 | of EQ, NE, etc. */ |
03984308 | 83 | |
ffbc8796 BW |
84 | enum internal_test |
85 | { | |
86 | ITEST_EQ, | |
87 | ITEST_NE, | |
88 | ITEST_GT, | |
89 | ITEST_GE, | |
90 | ITEST_LT, | |
91 | ITEST_LE, | |
92 | ITEST_GTU, | |
93 | ITEST_GEU, | |
94 | ITEST_LTU, | |
95 | ITEST_LEU, | |
96 | ITEST_MAX | |
97 | }; | |
03984308 | 98 | |
03984308 BW |
99 | /* Array giving truth value on whether or not a given hard register |
100 | can support a given mode. */ | |
101 | char xtensa_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; | |
102 | ||
103 | /* Current frame size calculated by compute_frame_size. */ | |
104 | unsigned xtensa_current_frame_size; | |
105 | ||
a46bbb5a | 106 | /* Largest block move to handle in-line. */ |
03984308 BW |
107 | #define LARGEST_MOVE_RATIO 15 |
108 | ||
109 | /* Define the structure for the machine field in struct function. */ | |
d1b38208 | 110 | struct GTY(()) machine_function |
03984308 BW |
111 | { |
112 | int accesses_prev_frame; | |
997b8b4d BW |
113 | bool need_a7_copy; |
114 | bool vararg_a7; | |
0d8442b8 | 115 | rtx vararg_a7_copy; |
240a513f | 116 | rtx_insn *set_frame_ptr_insn; |
03984308 BW |
117 | }; |
118 | ||
119 | /* Vector, indexed by hard register number, which contains 1 for a | |
120 | register that is allowable in a candidate for leaf function | |
638db43e | 121 | treatment. */ |
03984308 BW |
122 | |
123 | const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] = | |
124 | { | |
125 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, | |
126 | 1, 1, 1, | |
127 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, | |
128 | 1 | |
129 | }; | |
130 | ||
131 | /* Map hard register number to register class */ | |
132 | const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER] = | |
133 | { | |
89f6025d BW |
134 | RL_REGS, SP_REG, RL_REGS, RL_REGS, |
135 | RL_REGS, RL_REGS, RL_REGS, GR_REGS, | |
136 | RL_REGS, RL_REGS, RL_REGS, RL_REGS, | |
137 | RL_REGS, RL_REGS, RL_REGS, RL_REGS, | |
03984308 BW |
138 | AR_REGS, AR_REGS, BR_REGS, |
139 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
140 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
141 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
142 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
143 | ACC_REG, | |
144 | }; | |
145 | ||
c5387660 | 146 | static void xtensa_option_override (void); |
ffbc8796 BW |
147 | static enum internal_test map_test_to_internal_test (enum rtx_code); |
148 | static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *); | |
149 | static rtx gen_float_relational (enum rtx_code, rtx, rtx); | |
f90b7a5a | 150 | static rtx gen_conditional_move (enum rtx_code, enum machine_mode, rtx, rtx); |
ffbc8796 | 151 | static rtx fixup_subreg_mem (rtx); |
ffbc8796 | 152 | static struct machine_function * xtensa_init_machine_status (void); |
6a7a462c | 153 | static rtx xtensa_legitimize_tls_address (rtx); |
506d7b68 | 154 | static rtx xtensa_legitimize_address (rtx, rtx, enum machine_mode); |
5bfed9a9 | 155 | static bool xtensa_mode_dependent_address_p (const_rtx, addr_space_t); |
586de218 | 156 | static bool xtensa_return_in_msb (const_tree); |
ffbc8796 BW |
157 | static void printx (FILE *, signed int); |
158 | static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT); | |
4c45af42 | 159 | static rtx xtensa_builtin_saveregs (void); |
c6c3dba9 | 160 | static bool xtensa_legitimate_address_p (enum machine_mode, rtx, bool); |
ffbc8796 BW |
161 | static unsigned int xtensa_multibss_section_type_flags (tree, const char *, |
162 | int) ATTRIBUTE_UNUSED; | |
d6b5193b RS |
163 | static section *xtensa_select_rtx_section (enum machine_mode, rtx, |
164 | unsigned HOST_WIDE_INT); | |
68f932c4 | 165 | static bool xtensa_rtx_costs (rtx, int, int, int, int *, bool); |
5378dda2 AS |
166 | static int xtensa_register_move_cost (enum machine_mode, reg_class_t, |
167 | reg_class_t); | |
168 | static int xtensa_memory_move_cost (enum machine_mode, reg_class_t, bool); | |
c35d187f | 169 | static tree xtensa_build_builtin_va_list (void); |
586de218 | 170 | static bool xtensa_return_in_memory (const_tree, const_tree); |
726a989a RB |
171 | static tree xtensa_gimplify_va_arg_expr (tree, tree, gimple_seq *, |
172 | gimple_seq *); | |
d5cc9181 | 173 | static void xtensa_function_arg_advance (cumulative_args_t, enum machine_mode, |
626a4b31 | 174 | const_tree, bool); |
d5cc9181 | 175 | static rtx xtensa_function_arg (cumulative_args_t, enum machine_mode, |
626a4b31 | 176 | const_tree, bool); |
d5cc9181 | 177 | static rtx xtensa_function_incoming_arg (cumulative_args_t, |
626a4b31 | 178 | enum machine_mode, const_tree, bool); |
e2b2d01e | 179 | static rtx xtensa_function_value (const_tree, const_tree, bool); |
dde8a3a4 AS |
180 | static rtx xtensa_libcall_value (enum machine_mode, const_rtx); |
181 | static bool xtensa_function_value_regno_p (const unsigned int); | |
c2ed6cf8 NF |
182 | static unsigned int xtensa_function_arg_boundary (enum machine_mode, |
183 | const_tree); | |
09fa8841 | 184 | static void xtensa_init_builtins (void); |
f311c3b4 | 185 | static tree xtensa_fold_builtin (tree, int, tree *, bool); |
09fa8841 | 186 | static rtx xtensa_expand_builtin (tree, rtx, rtx, enum machine_mode, int); |
9d0b1619 | 187 | static void xtensa_va_start (tree, rtx); |
b52b1749 | 188 | static bool xtensa_frame_pointer_required (void); |
2b4fa409 | 189 | static rtx xtensa_static_chain (const_tree, bool); |
3c1229cb RH |
190 | static void xtensa_asm_trampoline_template (FILE *); |
191 | static void xtensa_trampoline_init (rtx, tree, rtx); | |
2ac6bb04 | 192 | static bool xtensa_output_addr_const_extra (FILE *, rtx); |
fbbf66e7 | 193 | static bool xtensa_cannot_force_const_mem (enum machine_mode, rtx); |
b64a1b53 | 194 | |
a6e508f9 AS |
195 | static reg_class_t xtensa_preferred_reload_class (rtx, reg_class_t); |
196 | static reg_class_t xtensa_preferred_output_reload_class (rtx, reg_class_t); | |
197 | static reg_class_t xtensa_secondary_reload (bool, rtx, reg_class_t, | |
198 | enum machine_mode, | |
199 | struct secondary_reload_info *); | |
200 | ||
a1a79768 | 201 | static bool constantpool_address_p (const_rtx addr); |
1a627b35 | 202 | static bool xtensa_legitimate_constant_p (enum machine_mode, rtx); |
a1a79768 | 203 | |
d9886a9e L |
204 | static bool xtensa_member_type_forces_blk (const_tree, |
205 | enum machine_mode mode); | |
206 | ||
b64a1b53 RH |
207 | static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] = |
208 | REG_ALLOC_ORDER; | |
209 | \f | |
03984308 BW |
210 | |
211 | /* This macro generates the assembly code for function exit, | |
212 | on machines that need it. If FUNCTION_EPILOGUE is not defined | |
213 | then individual return instructions are generated for each | |
214 | return statement. Args are same as for FUNCTION_PROLOGUE. */ | |
215 | ||
216 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
217 | #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue | |
218 | ||
219 | /* These hooks specify assembly directives for creating certain kinds | |
220 | of integer object. */ | |
221 | ||
222 | #undef TARGET_ASM_ALIGNED_SI_OP | |
223 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
224 | ||
b64a1b53 RH |
225 | #undef TARGET_ASM_SELECT_RTX_SECTION |
226 | #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section | |
03984308 | 227 | |
506d7b68 PB |
228 | #undef TARGET_LEGITIMIZE_ADDRESS |
229 | #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address | |
a1a79768 AS |
230 | #undef TARGET_MODE_DEPENDENT_ADDRESS_P |
231 | #define TARGET_MODE_DEPENDENT_ADDRESS_P xtensa_mode_dependent_address_p | |
506d7b68 | 232 | |
5378dda2 AS |
233 | #undef TARGET_REGISTER_MOVE_COST |
234 | #define TARGET_REGISTER_MOVE_COST xtensa_register_move_cost | |
235 | #undef TARGET_MEMORY_MOVE_COST | |
236 | #define TARGET_MEMORY_MOVE_COST xtensa_memory_move_cost | |
3c50106f RH |
237 | #undef TARGET_RTX_COSTS |
238 | #define TARGET_RTX_COSTS xtensa_rtx_costs | |
dcefdf67 | 239 | #undef TARGET_ADDRESS_COST |
b413068c | 240 | #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0 |
3c50106f | 241 | |
d9886a9e L |
242 | #undef TARGET_MEMBER_TYPE_FORCES_BLK |
243 | #define TARGET_MEMBER_TYPE_FORCES_BLK xtensa_member_type_forces_blk | |
244 | ||
c35d187f RH |
245 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
246 | #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list | |
247 | ||
d7bd8aeb JJ |
248 | #undef TARGET_EXPAND_BUILTIN_VA_START |
249 | #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start | |
250 | ||
cde0f3fd PB |
251 | #undef TARGET_PROMOTE_FUNCTION_MODE |
252 | #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote | |
4c45af42 | 253 | #undef TARGET_PROMOTE_PROTOTYPES |
586de218 | 254 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
4c45af42 | 255 | |
4c45af42 KH |
256 | #undef TARGET_RETURN_IN_MEMORY |
257 | #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory | |
e2b2d01e AS |
258 | #undef TARGET_FUNCTION_VALUE |
259 | #define TARGET_FUNCTION_VALUE xtensa_function_value | |
dde8a3a4 AS |
260 | #undef TARGET_LIBCALL_VALUE |
261 | #define TARGET_LIBCALL_VALUE xtensa_libcall_value | |
262 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
263 | #define TARGET_FUNCTION_VALUE_REGNO_P xtensa_function_value_regno_p | |
264 | ||
42ba5130 | 265 | #undef TARGET_SPLIT_COMPLEX_ARG |
3101faab | 266 | #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true |
fe984136 RH |
267 | #undef TARGET_MUST_PASS_IN_STACK |
268 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
626a4b31 NF |
269 | #undef TARGET_FUNCTION_ARG_ADVANCE |
270 | #define TARGET_FUNCTION_ARG_ADVANCE xtensa_function_arg_advance | |
271 | #undef TARGET_FUNCTION_ARG | |
272 | #define TARGET_FUNCTION_ARG xtensa_function_arg | |
273 | #undef TARGET_FUNCTION_INCOMING_ARG | |
274 | #define TARGET_FUNCTION_INCOMING_ARG xtensa_function_incoming_arg | |
c2ed6cf8 NF |
275 | #undef TARGET_FUNCTION_ARG_BOUNDARY |
276 | #define TARGET_FUNCTION_ARG_BOUNDARY xtensa_function_arg_boundary | |
4c45af42 KH |
277 | |
278 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
279 | #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs | |
85d53c1d RH |
280 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
281 | #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr | |
4c45af42 | 282 | |
6e5ff6e7 BW |
283 | #undef TARGET_RETURN_IN_MSB |
284 | #define TARGET_RETURN_IN_MSB xtensa_return_in_msb | |
285 | ||
09fa8841 BW |
286 | #undef TARGET_INIT_BUILTINS |
287 | #define TARGET_INIT_BUILTINS xtensa_init_builtins | |
288 | #undef TARGET_FOLD_BUILTIN | |
289 | #define TARGET_FOLD_BUILTIN xtensa_fold_builtin | |
290 | #undef TARGET_EXPAND_BUILTIN | |
291 | #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin | |
292 | ||
a6e508f9 AS |
293 | #undef TARGET_PREFERRED_RELOAD_CLASS |
294 | #define TARGET_PREFERRED_RELOAD_CLASS xtensa_preferred_reload_class | |
295 | #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS | |
296 | #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS xtensa_preferred_output_reload_class | |
297 | ||
37fbe8a3 BW |
298 | #undef TARGET_SECONDARY_RELOAD |
299 | #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload | |
300 | ||
6a7a462c BW |
301 | #undef TARGET_HAVE_TLS |
302 | #define TARGET_HAVE_TLS (TARGET_THREADPTR && HAVE_AS_TLS) | |
303 | ||
304 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
fbbf66e7 | 305 | #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_cannot_force_const_mem |
6a7a462c | 306 | |
c6c3dba9 PB |
307 | #undef TARGET_LEGITIMATE_ADDRESS_P |
308 | #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p | |
309 | ||
b52b1749 AS |
310 | #undef TARGET_FRAME_POINTER_REQUIRED |
311 | #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required | |
312 | ||
2b4fa409 RH |
313 | #undef TARGET_STATIC_CHAIN |
314 | #define TARGET_STATIC_CHAIN xtensa_static_chain | |
3c1229cb RH |
315 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
316 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE xtensa_asm_trampoline_template | |
317 | #undef TARGET_TRAMPOLINE_INIT | |
318 | #define TARGET_TRAMPOLINE_INIT xtensa_trampoline_init | |
319 | ||
c5387660 JM |
320 | #undef TARGET_OPTION_OVERRIDE |
321 | #define TARGET_OPTION_OVERRIDE xtensa_option_override | |
322 | ||
2ac6bb04 AS |
323 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
324 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA xtensa_output_addr_const_extra | |
325 | ||
1a627b35 RS |
326 | #undef TARGET_LEGITIMATE_CONSTANT_P |
327 | #define TARGET_LEGITIMATE_CONSTANT_P xtensa_legitimate_constant_p | |
328 | ||
b64a1b53 | 329 | struct gcc_target targetm = TARGET_INITIALIZER; |
03984308 | 330 | |
887af464 BW |
331 | \f |
332 | /* Functions to test Xtensa immediate operand validity. */ | |
03984308 | 333 | |
8eb1bc5c BW |
334 | bool |
335 | xtensa_simm8 (HOST_WIDE_INT v) | |
336 | { | |
337 | return v >= -128 && v <= 127; | |
338 | } | |
339 | ||
340 | ||
341 | bool | |
342 | xtensa_simm8x256 (HOST_WIDE_INT v) | |
343 | { | |
344 | return (v & 255) == 0 && (v >= -32768 && v <= 32512); | |
345 | } | |
346 | ||
347 | ||
348 | bool | |
349 | xtensa_simm12b (HOST_WIDE_INT v) | |
350 | { | |
351 | return v >= -2048 && v <= 2047; | |
352 | } | |
353 | ||
354 | ||
355 | static bool | |
356 | xtensa_uimm8 (HOST_WIDE_INT v) | |
357 | { | |
358 | return v >= 0 && v <= 255; | |
359 | } | |
360 | ||
361 | ||
362 | static bool | |
363 | xtensa_uimm8x2 (HOST_WIDE_INT v) | |
364 | { | |
365 | return (v & 1) == 0 && (v >= 0 && v <= 510); | |
366 | } | |
367 | ||
368 | ||
369 | static bool | |
370 | xtensa_uimm8x4 (HOST_WIDE_INT v) | |
371 | { | |
372 | return (v & 3) == 0 && (v >= 0 && v <= 1020); | |
373 | } | |
374 | ||
375 | ||
376 | static bool | |
377 | xtensa_b4const (HOST_WIDE_INT v) | |
03984308 BW |
378 | { |
379 | switch (v) | |
380 | { | |
8eb1bc5c BW |
381 | case -1: |
382 | case 1: | |
03984308 BW |
383 | case 2: |
384 | case 3: | |
385 | case 4: | |
386 | case 5: | |
387 | case 6: | |
388 | case 7: | |
389 | case 8: | |
390 | case 10: | |
391 | case 12: | |
392 | case 16: | |
393 | case 32: | |
394 | case 64: | |
395 | case 128: | |
396 | case 256: | |
8eb1bc5c | 397 | return true; |
03984308 | 398 | } |
8eb1bc5c | 399 | return false; |
03984308 BW |
400 | } |
401 | ||
03984308 | 402 | |
8eb1bc5c BW |
403 | bool |
404 | xtensa_b4const_or_zero (HOST_WIDE_INT v) | |
03984308 | 405 | { |
8eb1bc5c BW |
406 | if (v == 0) |
407 | return true; | |
408 | return xtensa_b4const (v); | |
03984308 BW |
409 | } |
410 | ||
03984308 | 411 | |
8eb1bc5c BW |
412 | bool |
413 | xtensa_b4constu (HOST_WIDE_INT v) | |
03984308 BW |
414 | { |
415 | switch (v) | |
416 | { | |
8eb1bc5c BW |
417 | case 32768: |
418 | case 65536: | |
03984308 BW |
419 | case 2: |
420 | case 3: | |
421 | case 4: | |
422 | case 5: | |
423 | case 6: | |
424 | case 7: | |
425 | case 8: | |
426 | case 10: | |
427 | case 12: | |
428 | case 16: | |
429 | case 32: | |
430 | case 64: | |
431 | case 128: | |
432 | case 256: | |
8eb1bc5c | 433 | return true; |
03984308 | 434 | } |
8eb1bc5c | 435 | return false; |
03984308 BW |
436 | } |
437 | ||
03984308 | 438 | |
8eb1bc5c BW |
439 | bool |
440 | xtensa_mask_immediate (HOST_WIDE_INT v) | |
03984308 | 441 | { |
8eb1bc5c BW |
442 | #define MAX_MASK_SIZE 16 |
443 | int mask_size; | |
03984308 | 444 | |
8eb1bc5c BW |
445 | for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++) |
446 | { | |
447 | if ((v & 1) == 0) | |
448 | return false; | |
449 | v = v >> 1; | |
450 | if (v == 0) | |
451 | return true; | |
452 | } | |
03984308 | 453 | |
8eb1bc5c | 454 | return false; |
03984308 BW |
455 | } |
456 | ||
03984308 | 457 | |
03984308 | 458 | /* This is just like the standard true_regnum() function except that it |
638db43e | 459 | works even when reg_renumber is not initialized. */ |
03984308 BW |
460 | |
461 | int | |
ffbc8796 | 462 | xt_true_regnum (rtx x) |
03984308 BW |
463 | { |
464 | if (GET_CODE (x) == REG) | |
465 | { | |
466 | if (reg_renumber | |
467 | && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
468 | && reg_renumber[REGNO (x)] >= 0) | |
469 | return reg_renumber[REGNO (x)]; | |
470 | return REGNO (x); | |
471 | } | |
472 | if (GET_CODE (x) == SUBREG) | |
473 | { | |
474 | int base = xt_true_regnum (SUBREG_REG (x)); | |
475 | if (base >= 0 && base < FIRST_PSEUDO_REGISTER) | |
476 | return base + subreg_regno_offset (REGNO (SUBREG_REG (x)), | |
477 | GET_MODE (SUBREG_REG (x)), | |
478 | SUBREG_BYTE (x), GET_MODE (x)); | |
479 | } | |
480 | return -1; | |
481 | } | |
482 | ||
483 | ||
03984308 | 484 | int |
ffbc8796 | 485 | xtensa_valid_move (enum machine_mode mode, rtx *operands) |
03984308 | 486 | { |
a8cacfd2 BW |
487 | /* Either the destination or source must be a register, and the |
488 | MAC16 accumulator doesn't count. */ | |
489 | ||
490 | if (register_operand (operands[0], mode)) | |
491 | { | |
492 | int dst_regnum = xt_true_regnum (operands[0]); | |
493 | ||
638db43e | 494 | /* The stack pointer can only be assigned with a MOVSP opcode. */ |
a8cacfd2 BW |
495 | if (dst_regnum == STACK_POINTER_REGNUM) |
496 | return (mode == SImode | |
497 | && register_operand (operands[1], mode) | |
498 | && !ACC_REG_P (xt_true_regnum (operands[1]))); | |
499 | ||
500 | if (!ACC_REG_P (dst_regnum)) | |
501 | return true; | |
502 | } | |
3437320b | 503 | if (register_operand (operands[1], mode)) |
a8cacfd2 BW |
504 | { |
505 | int src_regnum = xt_true_regnum (operands[1]); | |
506 | if (!ACC_REG_P (src_regnum)) | |
507 | return true; | |
508 | } | |
03984308 BW |
509 | return FALSE; |
510 | } | |
511 | ||
512 | ||
03984308 | 513 | int |
ffbc8796 | 514 | smalloffset_mem_p (rtx op) |
03984308 BW |
515 | { |
516 | if (GET_CODE (op) == MEM) | |
517 | { | |
518 | rtx addr = XEXP (op, 0); | |
519 | if (GET_CODE (addr) == REG) | |
da1f39e4 | 520 | return BASE_REG_P (addr, 0); |
03984308 BW |
521 | if (GET_CODE (addr) == PLUS) |
522 | { | |
523 | rtx offset = XEXP (addr, 0); | |
8eb1bc5c | 524 | HOST_WIDE_INT val; |
03984308 BW |
525 | if (GET_CODE (offset) != CONST_INT) |
526 | offset = XEXP (addr, 1); | |
527 | if (GET_CODE (offset) != CONST_INT) | |
528 | return FALSE; | |
8eb1bc5c BW |
529 | |
530 | val = INTVAL (offset); | |
531 | return (val & 3) == 0 && (val >= 0 && val <= 60); | |
03984308 BW |
532 | } |
533 | } | |
534 | return FALSE; | |
535 | } | |
536 | ||
537 | ||
a1a79768 AS |
538 | static bool |
539 | constantpool_address_p (const_rtx addr) | |
03984308 | 540 | { |
a1a79768 | 541 | const_rtx sym = addr; |
03984308 BW |
542 | |
543 | if (GET_CODE (addr) == CONST) | |
544 | { | |
545 | rtx offset; | |
546 | ||
3bbc2af6 | 547 | /* Only handle (PLUS (SYM, OFFSET)) form. */ |
03984308 BW |
548 | addr = XEXP (addr, 0); |
549 | if (GET_CODE (addr) != PLUS) | |
a1a79768 | 550 | return false; |
03984308 | 551 | |
3bbc2af6 | 552 | /* Make sure the address is word aligned. */ |
03984308 | 553 | offset = XEXP (addr, 1); |
a1a79768 | 554 | if ((!CONST_INT_P (offset)) |
03984308 | 555 | || ((INTVAL (offset) & 3) != 0)) |
a1a79768 | 556 | return false; |
03984308 BW |
557 | |
558 | sym = XEXP (addr, 0); | |
559 | } | |
560 | ||
561 | if ((GET_CODE (sym) == SYMBOL_REF) | |
562 | && CONSTANT_POOL_ADDRESS_P (sym)) | |
a1a79768 AS |
563 | return true; |
564 | return false; | |
03984308 BW |
565 | } |
566 | ||
567 | ||
568 | int | |
ffbc8796 | 569 | constantpool_mem_p (rtx op) |
03984308 | 570 | { |
63694bdd BW |
571 | if (GET_CODE (op) == SUBREG) |
572 | op = SUBREG_REG (op); | |
03984308 BW |
573 | if (GET_CODE (op) == MEM) |
574 | return constantpool_address_p (XEXP (op, 0)); | |
575 | return FALSE; | |
576 | } | |
577 | ||
578 | ||
6a7a462c BW |
579 | /* Return TRUE if X is a thread-local symbol. */ |
580 | ||
581 | static bool | |
582 | xtensa_tls_symbol_p (rtx x) | |
583 | { | |
584 | if (! TARGET_HAVE_TLS) | |
585 | return false; | |
586 | ||
587 | return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0; | |
588 | } | |
589 | ||
590 | ||
03984308 | 591 | void |
ffbc8796 | 592 | xtensa_extend_reg (rtx dst, rtx src) |
03984308 BW |
593 | { |
594 | rtx temp = gen_reg_rtx (SImode); | |
595 | rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src))); | |
596 | ||
3bbc2af6 | 597 | /* Generate paradoxical subregs as needed so that the modes match. */ |
03984308 BW |
598 | src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0); |
599 | dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0); | |
600 | ||
601 | emit_insn (gen_ashlsi3 (temp, src, shift)); | |
602 | emit_insn (gen_ashrsi3 (dst, temp, shift)); | |
603 | } | |
604 | ||
605 | ||
8eb1bc5c | 606 | bool |
ffbc8796 | 607 | xtensa_mem_offset (unsigned v, enum machine_mode mode) |
03984308 BW |
608 | { |
609 | switch (mode) | |
610 | { | |
611 | case BLKmode: | |
612 | /* Handle the worst case for block moves. See xtensa_expand_block_move | |
613 | where we emit an optimized block move operation if the block can be | |
614 | moved in < "move_ratio" pieces. The worst case is when the block is | |
615 | aligned but has a size of (3 mod 4) (does this happen?) so that the | |
638db43e | 616 | last piece requires a byte load/store. */ |
f42f5a1b BW |
617 | return (xtensa_uimm8 (v) |
618 | && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO)); | |
03984308 BW |
619 | |
620 | case QImode: | |
621 | return xtensa_uimm8 (v); | |
622 | ||
623 | case HImode: | |
624 | return xtensa_uimm8x2 (v); | |
625 | ||
626 | case DFmode: | |
627 | return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4)); | |
628 | ||
629 | default: | |
630 | break; | |
631 | } | |
632 | ||
633 | return xtensa_uimm8x4 (v); | |
634 | } | |
635 | ||
636 | ||
ffbc8796 | 637 | /* Make normal rtx_code into something we can index from an array. */ |
03984308 BW |
638 | |
639 | static enum internal_test | |
ffbc8796 | 640 | map_test_to_internal_test (enum rtx_code test_code) |
03984308 BW |
641 | { |
642 | enum internal_test test = ITEST_MAX; | |
643 | ||
644 | switch (test_code) | |
645 | { | |
646 | default: break; | |
647 | case EQ: test = ITEST_EQ; break; | |
648 | case NE: test = ITEST_NE; break; | |
649 | case GT: test = ITEST_GT; break; | |
650 | case GE: test = ITEST_GE; break; | |
651 | case LT: test = ITEST_LT; break; | |
652 | case LE: test = ITEST_LE; break; | |
653 | case GTU: test = ITEST_GTU; break; | |
654 | case GEU: test = ITEST_GEU; break; | |
655 | case LTU: test = ITEST_LTU; break; | |
656 | case LEU: test = ITEST_LEU; break; | |
657 | } | |
658 | ||
659 | return test; | |
660 | } | |
661 | ||
662 | ||
663 | /* Generate the code to compare two integer values. The return value is | |
638db43e | 664 | the comparison expression. */ |
03984308 BW |
665 | |
666 | static rtx | |
ffbc8796 BW |
667 | gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */ |
668 | rtx cmp0, /* first operand to compare */ | |
669 | rtx cmp1, /* second operand to compare */ | |
670 | int *p_invert /* whether branch needs to reverse test */) | |
03984308 | 671 | { |
ffbc8796 BW |
672 | struct cmp_info |
673 | { | |
03984308 | 674 | enum rtx_code test_code; /* test code to use in insn */ |
8eb1bc5c | 675 | bool (*const_range_p) (HOST_WIDE_INT); /* range check function */ |
03984308 BW |
676 | int const_add; /* constant to add (convert LE -> LT) */ |
677 | int reverse_regs; /* reverse registers in test */ | |
678 | int invert_const; /* != 0 if invert value if cmp1 is constant */ | |
679 | int invert_reg; /* != 0 if invert value if cmp1 is register */ | |
680 | int unsignedp; /* != 0 for unsigned comparisons. */ | |
681 | }; | |
682 | ||
683 | static struct cmp_info info[ (int)ITEST_MAX ] = { | |
684 | ||
8eb1bc5c BW |
685 | { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */ |
686 | { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */ | |
03984308 | 687 | |
8eb1bc5c BW |
688 | { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */ |
689 | { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */ | |
690 | { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */ | |
691 | { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */ | |
03984308 BW |
692 | |
693 | { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */ | |
694 | { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */ | |
695 | { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */ | |
696 | { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */ | |
697 | }; | |
698 | ||
699 | enum internal_test test; | |
700 | enum machine_mode mode; | |
701 | struct cmp_info *p_info; | |
702 | ||
703 | test = map_test_to_internal_test (test_code); | |
177b6be0 | 704 | gcc_assert (test != ITEST_MAX); |
03984308 BW |
705 | |
706 | p_info = &info[ (int)test ]; | |
707 | ||
708 | mode = GET_MODE (cmp0); | |
709 | if (mode == VOIDmode) | |
710 | mode = GET_MODE (cmp1); | |
711 | ||
712 | /* Make sure we can handle any constants given to us. */ | |
713 | if (GET_CODE (cmp1) == CONST_INT) | |
714 | { | |
715 | HOST_WIDE_INT value = INTVAL (cmp1); | |
716 | unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value; | |
717 | ||
718 | /* if the immediate overflows or does not fit in the immediate field, | |
719 | spill it to a register */ | |
720 | ||
721 | if ((p_info->unsignedp ? | |
722 | (uvalue + p_info->const_add > uvalue) : | |
723 | (value + p_info->const_add > value)) != (p_info->const_add > 0)) | |
724 | { | |
725 | cmp1 = force_reg (mode, cmp1); | |
726 | } | |
727 | else if (!(p_info->const_range_p) (value + p_info->const_add)) | |
728 | { | |
729 | cmp1 = force_reg (mode, cmp1); | |
730 | } | |
731 | } | |
732 | else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG)) | |
733 | { | |
734 | cmp1 = force_reg (mode, cmp1); | |
735 | } | |
736 | ||
737 | /* See if we need to invert the result. */ | |
738 | *p_invert = ((GET_CODE (cmp1) == CONST_INT) | |
739 | ? p_info->invert_const | |
740 | : p_info->invert_reg); | |
741 | ||
742 | /* Comparison to constants, may involve adding 1 to change a LT into LE. | |
743 | Comparison between two registers, may involve switching operands. */ | |
744 | if (GET_CODE (cmp1) == CONST_INT) | |
745 | { | |
746 | if (p_info->const_add != 0) | |
747 | cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add); | |
748 | ||
749 | } | |
750 | else if (p_info->reverse_regs) | |
751 | { | |
752 | rtx temp = cmp0; | |
753 | cmp0 = cmp1; | |
754 | cmp1 = temp; | |
755 | } | |
756 | ||
1c563bed | 757 | return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1); |
03984308 BW |
758 | } |
759 | ||
760 | ||
761 | /* Generate the code to compare two float values. The return value is | |
638db43e | 762 | the comparison expression. */ |
03984308 BW |
763 | |
764 | static rtx | |
ffbc8796 BW |
765 | gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */ |
766 | rtx cmp0, /* first operand to compare */ | |
767 | rtx cmp1 /* second operand to compare */) | |
03984308 | 768 | { |
ffbc8796 | 769 | rtx (*gen_fn) (rtx, rtx, rtx); |
03984308 BW |
770 | rtx brtmp; |
771 | int reverse_regs, invert; | |
772 | ||
773 | switch (test_code) | |
774 | { | |
775 | case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break; | |
776 | case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break; | |
777 | case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break; | |
778 | case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break; | |
779 | case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break; | |
780 | case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break; | |
ff779f98 BW |
781 | case UNEQ: reverse_regs = 0; invert = 0; gen_fn = gen_suneq_sf; break; |
782 | case LTGT: reverse_regs = 0; invert = 1; gen_fn = gen_suneq_sf; break; | |
783 | case UNLE: reverse_regs = 0; invert = 0; gen_fn = gen_sunle_sf; break; | |
784 | case UNGT: reverse_regs = 1; invert = 0; gen_fn = gen_sunlt_sf; break; | |
785 | case UNLT: reverse_regs = 0; invert = 0; gen_fn = gen_sunlt_sf; break; | |
786 | case UNGE: reverse_regs = 1; invert = 0; gen_fn = gen_sunle_sf; break; | |
787 | case UNORDERED: | |
788 | reverse_regs = 0; invert = 0; gen_fn = gen_sunordered_sf; break; | |
789 | case ORDERED: | |
790 | reverse_regs = 0; invert = 1; gen_fn = gen_sunordered_sf; break; | |
633e4eb4 | 791 | default: |
1c563bed | 792 | fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1)); |
03984308 BW |
793 | reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */ |
794 | } | |
795 | ||
796 | if (reverse_regs) | |
797 | { | |
798 | rtx temp = cmp0; | |
799 | cmp0 = cmp1; | |
800 | cmp1 = temp; | |
801 | } | |
802 | ||
803 | brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM); | |
804 | emit_insn (gen_fn (brtmp, cmp0, cmp1)); | |
805 | ||
1c563bed | 806 | return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx); |
03984308 BW |
807 | } |
808 | ||
809 | ||
810 | void | |
f90b7a5a | 811 | xtensa_expand_conditional_branch (rtx *operands, enum machine_mode mode) |
03984308 | 812 | { |
f90b7a5a PB |
813 | enum rtx_code test_code = GET_CODE (operands[0]); |
814 | rtx cmp0 = operands[1]; | |
815 | rtx cmp1 = operands[2]; | |
03984308 BW |
816 | rtx cmp; |
817 | int invert; | |
818 | rtx label1, label2; | |
819 | ||
f90b7a5a | 820 | switch (mode) |
03984308 | 821 | { |
f90b7a5a | 822 | case DFmode: |
03984308 | 823 | default: |
1c563bed | 824 | fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1)); |
03984308 | 825 | |
f90b7a5a | 826 | case SImode: |
03984308 BW |
827 | invert = FALSE; |
828 | cmp = gen_int_relational (test_code, cmp0, cmp1, &invert); | |
829 | break; | |
830 | ||
f90b7a5a | 831 | case SFmode: |
03984308 | 832 | if (!TARGET_HARD_FLOAT) |
da1f39e4 BW |
833 | fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, |
834 | cmp0, cmp1)); | |
03984308 BW |
835 | invert = FALSE; |
836 | cmp = gen_float_relational (test_code, cmp0, cmp1); | |
837 | break; | |
838 | } | |
839 | ||
840 | /* Generate the branch. */ | |
841 | ||
f90b7a5a | 842 | label1 = gen_rtx_LABEL_REF (VOIDmode, operands[3]); |
03984308 BW |
843 | label2 = pc_rtx; |
844 | ||
845 | if (invert) | |
846 | { | |
847 | label2 = label1; | |
848 | label1 = pc_rtx; | |
849 | } | |
850 | ||
851 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
852 | gen_rtx_IF_THEN_ELSE (VOIDmode, cmp, | |
853 | label1, | |
854 | label2))); | |
855 | } | |
856 | ||
857 | ||
858 | static rtx | |
f90b7a5a PB |
859 | gen_conditional_move (enum rtx_code code, enum machine_mode mode, |
860 | rtx op0, rtx op1) | |
03984308 | 861 | { |
f90b7a5a | 862 | if (mode == SImode) |
03984308 | 863 | { |
f90b7a5a PB |
864 | rtx cmp; |
865 | ||
03984308 BW |
866 | /* Jump optimization calls get_condition() which canonicalizes |
867 | comparisons like (GE x <const>) to (GT x <const-1>). | |
868 | Transform those comparisons back to GE, since that is the | |
869 | comparison supported in Xtensa. We shouldn't have to | |
870 | transform <LE x const> comparisons, because neither | |
871 | xtensa_expand_conditional_branch() nor get_condition() will | |
638db43e | 872 | produce them. */ |
03984308 BW |
873 | |
874 | if ((code == GT) && (op1 == constm1_rtx)) | |
875 | { | |
876 | code = GE; | |
877 | op1 = const0_rtx; | |
878 | } | |
1c563bed | 879 | cmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx); |
03984308 BW |
880 | |
881 | if (boolean_operator (cmp, VOIDmode)) | |
882 | { | |
3bbc2af6 | 883 | /* Swap the operands to make const0 second. */ |
03984308 BW |
884 | if (op0 == const0_rtx) |
885 | { | |
886 | op0 = op1; | |
887 | op1 = const0_rtx; | |
888 | } | |
889 | ||
3bbc2af6 | 890 | /* If not comparing against zero, emit a comparison (subtract). */ |
03984308 BW |
891 | if (op1 != const0_rtx) |
892 | { | |
893 | op0 = expand_binop (SImode, sub_optab, op0, op1, | |
894 | 0, 0, OPTAB_LIB_WIDEN); | |
895 | op1 = const0_rtx; | |
896 | } | |
897 | } | |
898 | else if (branch_operator (cmp, VOIDmode)) | |
899 | { | |
3bbc2af6 | 900 | /* Swap the operands to make const0 second. */ |
03984308 BW |
901 | if (op0 == const0_rtx) |
902 | { | |
903 | op0 = op1; | |
904 | op1 = const0_rtx; | |
905 | ||
906 | switch (code) | |
907 | { | |
908 | case LT: code = GE; break; | |
909 | case GE: code = LT; break; | |
177b6be0 | 910 | default: gcc_unreachable (); |
03984308 BW |
911 | } |
912 | } | |
913 | ||
914 | if (op1 != const0_rtx) | |
915 | return 0; | |
916 | } | |
917 | else | |
918 | return 0; | |
919 | ||
1c563bed | 920 | return gen_rtx_fmt_ee (code, VOIDmode, op0, op1); |
03984308 BW |
921 | } |
922 | ||
f90b7a5a | 923 | if (TARGET_HARD_FLOAT && mode == SFmode) |
03984308 BW |
924 | return gen_float_relational (code, op0, op1); |
925 | ||
926 | return 0; | |
927 | } | |
928 | ||
929 | ||
930 | int | |
ffbc8796 | 931 | xtensa_expand_conditional_move (rtx *operands, int isflt) |
03984308 | 932 | { |
f90b7a5a PB |
933 | rtx dest = operands[0]; |
934 | rtx cmp = operands[1]; | |
935 | enum machine_mode cmp_mode = GET_MODE (XEXP (cmp, 0)); | |
ffbc8796 | 936 | rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx); |
03984308 | 937 | |
f90b7a5a PB |
938 | if (!(cmp = gen_conditional_move (GET_CODE (cmp), cmp_mode, |
939 | XEXP (cmp, 0), XEXP (cmp, 1)))) | |
03984308 BW |
940 | return 0; |
941 | ||
942 | if (isflt) | |
f90b7a5a | 943 | gen_fn = (cmp_mode == SImode |
03984308 BW |
944 | ? gen_movsfcc_internal0 |
945 | : gen_movsfcc_internal1); | |
946 | else | |
f90b7a5a | 947 | gen_fn = (cmp_mode == SImode |
03984308 BW |
948 | ? gen_movsicc_internal0 |
949 | : gen_movsicc_internal1); | |
950 | ||
f90b7a5a | 951 | emit_insn (gen_fn (dest, XEXP (cmp, 0), operands[2], operands[3], cmp)); |
03984308 BW |
952 | return 1; |
953 | } | |
954 | ||
955 | ||
956 | int | |
f90b7a5a | 957 | xtensa_expand_scc (rtx operands[4], enum machine_mode cmp_mode) |
03984308 BW |
958 | { |
959 | rtx dest = operands[0]; | |
f90b7a5a | 960 | rtx cmp; |
03984308 | 961 | rtx one_tmp, zero_tmp; |
ffbc8796 | 962 | rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx); |
03984308 | 963 | |
f90b7a5a PB |
964 | if (!(cmp = gen_conditional_move (GET_CODE (operands[1]), cmp_mode, |
965 | operands[2], operands[3]))) | |
03984308 BW |
966 | return 0; |
967 | ||
968 | one_tmp = gen_reg_rtx (SImode); | |
969 | zero_tmp = gen_reg_rtx (SImode); | |
970 | emit_insn (gen_movsi (one_tmp, const_true_rtx)); | |
971 | emit_insn (gen_movsi (zero_tmp, const0_rtx)); | |
972 | ||
f90b7a5a | 973 | gen_fn = (cmp_mode == SImode |
03984308 BW |
974 | ? gen_movsicc_internal0 |
975 | : gen_movsicc_internal1); | |
976 | emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp)); | |
977 | return 1; | |
978 | } | |
979 | ||
980 | ||
633e4eb4 BW |
981 | /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is |
982 | for the output, i.e., the input operands are twice as big as MODE. */ | |
983 | ||
984 | void | |
ffbc8796 | 985 | xtensa_split_operand_pair (rtx operands[4], enum machine_mode mode) |
633e4eb4 BW |
986 | { |
987 | switch (GET_CODE (operands[1])) | |
988 | { | |
989 | case REG: | |
990 | operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1); | |
991 | operands[2] = gen_rtx_REG (mode, REGNO (operands[1])); | |
992 | break; | |
993 | ||
994 | case MEM: | |
995 | operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode)); | |
996 | operands[2] = adjust_address (operands[1], mode, 0); | |
997 | break; | |
998 | ||
999 | case CONST_INT: | |
1000 | case CONST_DOUBLE: | |
1001 | split_double (operands[1], &operands[2], &operands[3]); | |
1002 | break; | |
1003 | ||
1004 | default: | |
177b6be0 | 1005 | gcc_unreachable (); |
633e4eb4 BW |
1006 | } |
1007 | ||
1008 | switch (GET_CODE (operands[0])) | |
1009 | { | |
1010 | case REG: | |
1011 | operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1); | |
1012 | operands[0] = gen_rtx_REG (mode, REGNO (operands[0])); | |
1013 | break; | |
1014 | ||
1015 | case MEM: | |
1016 | operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode)); | |
1017 | operands[0] = adjust_address (operands[0], mode, 0); | |
1018 | break; | |
1019 | ||
1020 | default: | |
177b6be0 | 1021 | gcc_unreachable (); |
633e4eb4 BW |
1022 | } |
1023 | } | |
1024 | ||
1025 | ||
03984308 | 1026 | /* Emit insns to move operands[1] into operands[0]. |
03984308 BW |
1027 | Return 1 if we have written out everything that needs to be done to |
1028 | do the move. Otherwise, return 0 and the caller will emit the move | |
1029 | normally. */ | |
1030 | ||
1031 | int | |
ffbc8796 | 1032 | xtensa_emit_move_sequence (rtx *operands, enum machine_mode mode) |
03984308 | 1033 | { |
6a7a462c BW |
1034 | rtx src = operands[1]; |
1035 | ||
1036 | if (CONSTANT_P (src) | |
1037 | && (GET_CODE (src) != CONST_INT || ! xtensa_simm12b (INTVAL (src)))) | |
03984308 | 1038 | { |
6a7a462c BW |
1039 | rtx dst = operands[0]; |
1040 | ||
1041 | if (xtensa_tls_referenced_p (src)) | |
1042 | { | |
1043 | rtx addend = NULL; | |
1044 | ||
1045 | if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS) | |
1046 | { | |
1047 | addend = XEXP (XEXP (src, 0), 1); | |
1048 | src = XEXP (XEXP (src, 0), 0); | |
1049 | } | |
1050 | ||
1051 | src = xtensa_legitimize_tls_address (src); | |
1052 | if (addend) | |
1053 | { | |
1054 | src = gen_rtx_PLUS (mode, src, addend); | |
1055 | src = force_operand (src, dst); | |
1056 | } | |
1057 | emit_move_insn (dst, src); | |
1058 | return 1; | |
1059 | } | |
1060 | ||
1061 | if (! TARGET_CONST16) | |
1062 | { | |
1063 | src = force_const_mem (SImode, src); | |
1064 | operands[1] = src; | |
1065 | } | |
f42f5a1b BW |
1066 | |
1067 | /* PC-relative loads are always SImode, and CONST16 is only | |
1068 | supported in the movsi pattern, so add a SUBREG for any other | |
1069 | (smaller) mode. */ | |
1070 | ||
1071 | if (mode != SImode) | |
1072 | { | |
6a7a462c | 1073 | if (register_operand (dst, mode)) |
f42f5a1b | 1074 | { |
6a7a462c | 1075 | emit_move_insn (simplify_gen_subreg (SImode, dst, mode, 0), src); |
f42f5a1b BW |
1076 | return 1; |
1077 | } | |
1078 | else | |
1079 | { | |
6a7a462c BW |
1080 | src = force_reg (SImode, src); |
1081 | src = gen_lowpart_SUBREG (mode, src); | |
1082 | operands[1] = src; | |
f42f5a1b BW |
1083 | } |
1084 | } | |
03984308 BW |
1085 | } |
1086 | ||
997b8b4d BW |
1087 | if (!(reload_in_progress | reload_completed) |
1088 | && !xtensa_valid_move (mode, operands)) | |
1089 | operands[1] = force_reg (mode, operands[1]); | |
03984308 | 1090 | |
997b8b4d | 1091 | operands[1] = xtensa_copy_incoming_a7 (operands[1]); |
03984308 BW |
1092 | |
1093 | /* During reload we don't want to emit (subreg:X (mem:Y)) since that | |
638db43e BW |
1094 | instruction won't be recognized after reload, so we remove the |
1095 | subreg and adjust mem accordingly. */ | |
03984308 BW |
1096 | if (reload_in_progress) |
1097 | { | |
1098 | operands[0] = fixup_subreg_mem (operands[0]); | |
1099 | operands[1] = fixup_subreg_mem (operands[1]); | |
1100 | } | |
1101 | return 0; | |
1102 | } | |
1103 | ||
f42f5a1b | 1104 | |
03984308 | 1105 | static rtx |
ffbc8796 | 1106 | fixup_subreg_mem (rtx x) |
03984308 BW |
1107 | { |
1108 | if (GET_CODE (x) == SUBREG | |
1109 | && GET_CODE (SUBREG_REG (x)) == REG | |
1110 | && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER) | |
1111 | { | |
1112 | rtx temp = | |
1113 | gen_rtx_SUBREG (GET_MODE (x), | |
f2034d06 | 1114 | reg_equiv_mem (REGNO (SUBREG_REG (x))), |
03984308 | 1115 | SUBREG_BYTE (x)); |
55a2c322 | 1116 | x = alter_subreg (&temp, true); |
03984308 BW |
1117 | } |
1118 | return x; | |
1119 | } | |
1120 | ||
1121 | ||
997b8b4d BW |
1122 | /* Check if an incoming argument in a7 is expected to be used soon and |
1123 | if OPND is a register or register pair that includes a7. If so, | |
1124 | create a new pseudo and copy a7 into that pseudo at the very | |
1125 | beginning of the function, followed by the special "set_frame_ptr" | |
1126 | unspec_volatile insn. The return value is either the original | |
1127 | operand, if it is not a7, or the new pseudo containing a copy of | |
1128 | the incoming argument. This is necessary because the register | |
1129 | allocator will ignore conflicts with a7 and may either assign some | |
1130 | other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering | |
1131 | the incoming argument in a7. By copying the argument out of a7 as | |
1132 | the very first thing, and then immediately following that with an | |
1133 | unspec_volatile to keep the scheduler away, we should avoid any | |
1134 | problems. Putting the set_frame_ptr insn at the beginning, with | |
1135 | only the a7 copy before it, also makes it easier for the prologue | |
1136 | expander to initialize the frame pointer after the a7 copy and to | |
1137 | fix up the a7 copy to use the stack pointer instead of the frame | |
1138 | pointer. */ | |
58db834b | 1139 | |
997b8b4d BW |
1140 | rtx |
1141 | xtensa_copy_incoming_a7 (rtx opnd) | |
58db834b | 1142 | { |
997b8b4d BW |
1143 | rtx entry_insns = 0; |
1144 | rtx reg, tmp; | |
1145 | enum machine_mode mode; | |
1146 | ||
1147 | if (!cfun->machine->need_a7_copy) | |
1148 | return opnd; | |
1149 | ||
1150 | /* This function should never be called again once a7 has been copied. */ | |
177b6be0 | 1151 | gcc_assert (!cfun->machine->set_frame_ptr_insn); |
997b8b4d BW |
1152 | |
1153 | mode = GET_MODE (opnd); | |
1154 | ||
1155 | /* The operand using a7 may come in a later instruction, so just return | |
1156 | the original operand if it doesn't use a7. */ | |
1157 | reg = opnd; | |
1158 | if (GET_CODE (reg) == SUBREG) | |
58db834b | 1159 | { |
177b6be0 | 1160 | gcc_assert (SUBREG_BYTE (reg) == 0); |
997b8b4d BW |
1161 | reg = SUBREG_REG (reg); |
1162 | } | |
1163 | if (GET_CODE (reg) != REG | |
1164 | || REGNO (reg) > A7_REG | |
1165 | || REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) <= A7_REG) | |
1166 | return opnd; | |
e6aecf8e | 1167 | |
997b8b4d | 1168 | /* 1-word args will always be in a7; 2-word args in a6/a7. */ |
177b6be0 | 1169 | gcc_assert (REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) - 1 == A7_REG); |
58db834b | 1170 | |
997b8b4d | 1171 | cfun->machine->need_a7_copy = false; |
58db834b | 1172 | |
997b8b4d BW |
1173 | /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to |
1174 | create the REG for a7 so that hard_frame_pointer_rtx is not used. */ | |
58db834b | 1175 | |
0d8442b8 | 1176 | start_sequence (); |
997b8b4d | 1177 | tmp = gen_reg_rtx (mode); |
58db834b | 1178 | |
997b8b4d BW |
1179 | switch (mode) |
1180 | { | |
1181 | case DFmode: | |
1182 | case DImode: | |
b412869c BW |
1183 | /* Copy the value out of A7 here but keep the first word in A6 until |
1184 | after the set_frame_ptr insn. Otherwise, the register allocator | |
1185 | may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming | |
1186 | value. */ | |
997b8b4d BW |
1187 | emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4), |
1188 | gen_raw_REG (SImode, A7_REG))); | |
1189 | break; | |
1190 | case SFmode: | |
1191 | emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG))); | |
1192 | break; | |
1193 | case SImode: | |
1194 | emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG))); | |
1195 | break; | |
1196 | case HImode: | |
1197 | emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG))); | |
1198 | break; | |
1199 | case QImode: | |
1200 | emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG))); | |
1201 | break; | |
1202 | default: | |
177b6be0 | 1203 | gcc_unreachable (); |
58db834b BW |
1204 | } |
1205 | ||
997b8b4d | 1206 | cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ()); |
b412869c BW |
1207 | |
1208 | /* For DF and DI mode arguments, copy the incoming value in A6 now. */ | |
1209 | if (mode == DFmode || mode == DImode) | |
1210 | emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0), | |
1211 | gen_rtx_REG (SImode, A7_REG - 1))); | |
997b8b4d BW |
1212 | entry_insns = get_insns (); |
1213 | end_sequence (); | |
1214 | ||
1215 | if (cfun->machine->vararg_a7) | |
1216 | { | |
0d8442b8 BW |
1217 | /* This is called from within builtin_saveregs, which will insert the |
1218 | saveregs code at the function entry, ahead of anything placed at | |
1219 | the function entry now. Instead, save the sequence to be inserted | |
1220 | at the beginning of the saveregs code. */ | |
1221 | cfun->machine->vararg_a7_copy = entry_insns; | |
997b8b4d BW |
1222 | } |
1223 | else | |
1224 | { | |
1225 | /* Put entry_insns after the NOTE that starts the function. If | |
1226 | this is inside a start_sequence, make the outer-level insn | |
1227 | chain current, so the code is placed at the start of the | |
1228 | function. */ | |
1229 | push_topmost_sequence (); | |
0d8442b8 BW |
1230 | /* Do not use entry_of_function() here. This is called from within |
1231 | expand_function_start, when the CFG still holds GIMPLE. */ | |
997b8b4d BW |
1232 | emit_insn_after (entry_insns, get_insns ()); |
1233 | pop_topmost_sequence (); | |
1234 | } | |
1235 | ||
1236 | return tmp; | |
58db834b BW |
1237 | } |
1238 | ||
1239 | ||
a46bbb5a BW |
1240 | /* Try to expand a block move operation to a sequence of RTL move |
1241 | instructions. If not optimizing, or if the block size is not a | |
1242 | constant, or if the block is too large, the expansion fails and GCC | |
1243 | falls back to calling memcpy(). | |
03984308 BW |
1244 | |
1245 | operands[0] is the destination | |
1246 | operands[1] is the source | |
1247 | operands[2] is the length | |
1248 | operands[3] is the alignment */ | |
1249 | ||
1250 | int | |
ffbc8796 | 1251 | xtensa_expand_block_move (rtx *operands) |
03984308 | 1252 | { |
7eda7cda RH |
1253 | static const enum machine_mode mode_from_align[] = |
1254 | { | |
1255 | VOIDmode, QImode, HImode, VOIDmode, SImode, | |
1256 | }; | |
1257 | ||
1258 | rtx dst_mem = operands[0]; | |
1259 | rtx src_mem = operands[1]; | |
1260 | HOST_WIDE_INT bytes, align; | |
03984308 | 1261 | int num_pieces, move_ratio; |
7eda7cda RH |
1262 | rtx temp[2]; |
1263 | enum machine_mode mode[2]; | |
1264 | int amount[2]; | |
1265 | bool active[2]; | |
1266 | int phase = 0; | |
1267 | int next; | |
1268 | int offset_ld = 0; | |
1269 | int offset_st = 0; | |
1270 | rtx x; | |
03984308 | 1271 | |
3bbc2af6 | 1272 | /* If this is not a fixed size move, just call memcpy. */ |
03984308 BW |
1273 | if (!optimize || (GET_CODE (operands[2]) != CONST_INT)) |
1274 | return 0; | |
1275 | ||
7eda7cda RH |
1276 | bytes = INTVAL (operands[2]); |
1277 | align = INTVAL (operands[3]); | |
1278 | ||
3bbc2af6 | 1279 | /* Anything to move? */ |
03984308 | 1280 | if (bytes <= 0) |
7eda7cda | 1281 | return 0; |
03984308 BW |
1282 | |
1283 | if (align > MOVE_MAX) | |
1284 | align = MOVE_MAX; | |
1285 | ||
3bbc2af6 | 1286 | /* Decide whether to expand inline based on the optimization level. */ |
03984308 BW |
1287 | move_ratio = 4; |
1288 | if (optimize > 2) | |
1289 | move_ratio = LARGEST_MOVE_RATIO; | |
3bbc2af6 | 1290 | num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */ |
7eda7cda | 1291 | if (num_pieces > move_ratio) |
03984308 BW |
1292 | return 0; |
1293 | ||
7eda7cda RH |
1294 | x = XEXP (dst_mem, 0); |
1295 | if (!REG_P (x)) | |
1296 | { | |
1297 | x = force_reg (Pmode, x); | |
1298 | dst_mem = replace_equiv_address (dst_mem, x); | |
1299 | } | |
03984308 | 1300 | |
7eda7cda RH |
1301 | x = XEXP (src_mem, 0); |
1302 | if (!REG_P (x)) | |
1303 | { | |
1304 | x = force_reg (Pmode, x); | |
1305 | src_mem = replace_equiv_address (src_mem, x); | |
1306 | } | |
03984308 | 1307 | |
7eda7cda | 1308 | active[0] = active[1] = false; |
03984308 | 1309 | |
7eda7cda | 1310 | do |
03984308 | 1311 | { |
7eda7cda RH |
1312 | next = phase; |
1313 | phase ^= 1; | |
03984308 | 1314 | |
7eda7cda | 1315 | if (bytes > 0) |
03984308 | 1316 | { |
7eda7cda | 1317 | int next_amount; |
03984308 | 1318 | |
7eda7cda RH |
1319 | next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1)); |
1320 | next_amount = MIN (next_amount, align); | |
03984308 | 1321 | |
7eda7cda RH |
1322 | amount[next] = next_amount; |
1323 | mode[next] = mode_from_align[next_amount]; | |
1324 | temp[next] = gen_reg_rtx (mode[next]); | |
03984308 | 1325 | |
7eda7cda RH |
1326 | x = adjust_address (src_mem, mode[next], offset_ld); |
1327 | emit_insn (gen_rtx_SET (VOIDmode, temp[next], x)); | |
03984308 | 1328 | |
7eda7cda RH |
1329 | offset_ld += next_amount; |
1330 | bytes -= next_amount; | |
1331 | active[next] = true; | |
1332 | } | |
03984308 | 1333 | |
7eda7cda RH |
1334 | if (active[phase]) |
1335 | { | |
1336 | active[phase] = false; | |
1337 | ||
1338 | x = adjust_address (dst_mem, mode[phase], offset_st); | |
1339 | emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase])); | |
03984308 | 1340 | |
7eda7cda RH |
1341 | offset_st += amount[phase]; |
1342 | } | |
03984308 | 1343 | } |
7eda7cda | 1344 | while (active[next]); |
03984308 | 1345 | |
7eda7cda | 1346 | return 1; |
03984308 BW |
1347 | } |
1348 | ||
1349 | ||
1350 | void | |
ffbc8796 | 1351 | xtensa_expand_nonlocal_goto (rtx *operands) |
03984308 BW |
1352 | { |
1353 | rtx goto_handler = operands[1]; | |
1354 | rtx containing_fp = operands[3]; | |
1355 | ||
3bbc2af6 KH |
1356 | /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code |
1357 | is too big to generate in-line. */ | |
03984308 BW |
1358 | |
1359 | if (GET_CODE (containing_fp) != REG) | |
1360 | containing_fp = force_reg (Pmode, containing_fp); | |
1361 | ||
03984308 | 1362 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"), |
046845de | 1363 | LCT_NORMAL, VOIDmode, 2, |
03984308 BW |
1364 | containing_fp, Pmode, |
1365 | goto_handler, Pmode); | |
1366 | } | |
1367 | ||
1368 | ||
e2500fed | 1369 | static struct machine_function * |
ffbc8796 | 1370 | xtensa_init_machine_status (void) |
03984308 | 1371 | { |
766090c2 | 1372 | return ggc_cleared_alloc<machine_function> (); |
03984308 BW |
1373 | } |
1374 | ||
1375 | ||
2a48b790 BW |
1376 | /* Shift VAL of mode MODE left by COUNT bits. */ |
1377 | ||
1378 | static inline rtx | |
1379 | xtensa_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count) | |
1380 | { | |
1381 | val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)), | |
1382 | NULL_RTX, 1, OPTAB_DIRECT); | |
1383 | return expand_simple_binop (SImode, ASHIFT, val, count, | |
1384 | NULL_RTX, 1, OPTAB_DIRECT); | |
1385 | } | |
1386 | ||
1387 | ||
1388 | /* Structure to hold the initial parameters for a compare_and_swap operation | |
1389 | in HImode and QImode. */ | |
1390 | ||
1391 | struct alignment_context | |
1392 | { | |
1393 | rtx memsi; /* SI aligned memory location. */ | |
1394 | rtx shift; /* Bit offset with regard to lsb. */ | |
1395 | rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */ | |
1396 | rtx modemaski; /* ~modemask */ | |
1397 | }; | |
1398 | ||
1399 | ||
1400 | /* Initialize structure AC for word access to HI and QI mode memory. */ | |
1401 | ||
1402 | static void | |
1403 | init_alignment_context (struct alignment_context *ac, rtx mem) | |
1404 | { | |
1405 | enum machine_mode mode = GET_MODE (mem); | |
1406 | rtx byteoffset = NULL_RTX; | |
1407 | bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode)); | |
1408 | ||
1409 | if (aligned) | |
1410 | ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */ | |
1411 | else | |
1412 | { | |
1413 | /* Alignment is unknown. */ | |
1414 | rtx addr, align; | |
1415 | ||
1416 | /* Force the address into a register. */ | |
1417 | addr = force_reg (Pmode, XEXP (mem, 0)); | |
1418 | ||
1419 | /* Align it to SImode. */ | |
1420 | align = expand_simple_binop (Pmode, AND, addr, | |
1421 | GEN_INT (-GET_MODE_SIZE (SImode)), | |
1422 | NULL_RTX, 1, OPTAB_DIRECT); | |
1423 | /* Generate MEM. */ | |
1424 | ac->memsi = gen_rtx_MEM (SImode, align); | |
1425 | MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem); | |
1426 | set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER); | |
1427 | set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode)); | |
1428 | ||
1429 | byteoffset = expand_simple_binop (Pmode, AND, addr, | |
1430 | GEN_INT (GET_MODE_SIZE (SImode) - 1), | |
1431 | NULL_RTX, 1, OPTAB_DIRECT); | |
1432 | } | |
1433 | ||
1434 | /* Calculate shiftcount. */ | |
1435 | if (TARGET_BIG_ENDIAN) | |
1436 | { | |
1437 | ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode)); | |
1438 | if (!aligned) | |
1439 | ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset, | |
1440 | NULL_RTX, 1, OPTAB_DIRECT); | |
1441 | } | |
1442 | else | |
1443 | { | |
1444 | if (aligned) | |
1445 | ac->shift = NULL_RTX; | |
1446 | else | |
1447 | ac->shift = byteoffset; | |
1448 | } | |
1449 | ||
1450 | if (ac->shift != NULL_RTX) | |
1451 | { | |
1452 | /* Shift is the byte count, but we need the bitcount. */ | |
1453 | ac->shift = expand_simple_binop (SImode, MULT, ac->shift, | |
1454 | GEN_INT (BITS_PER_UNIT), | |
1455 | NULL_RTX, 1, OPTAB_DIRECT); | |
1456 | ac->modemask = expand_simple_binop (SImode, ASHIFT, | |
1457 | GEN_INT (GET_MODE_MASK (mode)), | |
1458 | ac->shift, | |
1459 | NULL_RTX, 1, OPTAB_DIRECT); | |
1460 | } | |
1461 | else | |
1462 | ac->modemask = GEN_INT (GET_MODE_MASK (mode)); | |
1463 | ||
1464 | ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1); | |
1465 | } | |
1466 | ||
1467 | ||
1468 | /* Expand an atomic compare and swap operation for HImode and QImode. | |
1469 | MEM is the memory location, CMP the old value to compare MEM with | |
0a2aaacc | 1470 | and NEW_RTX the value to set if CMP == MEM. */ |
2a48b790 BW |
1471 | |
1472 | void | |
0a2aaacc | 1473 | xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new_rtx) |
2a48b790 BW |
1474 | { |
1475 | enum machine_mode mode = GET_MODE (mem); | |
1476 | struct alignment_context ac; | |
1477 | rtx tmp, cmpv, newv, val; | |
1478 | rtx oldval = gen_reg_rtx (SImode); | |
1479 | rtx res = gen_reg_rtx (SImode); | |
240a513f DM |
1480 | rtx_code_label *csloop = gen_label_rtx (); |
1481 | rtx_code_label *csend = gen_label_rtx (); | |
2a48b790 BW |
1482 | |
1483 | init_alignment_context (&ac, mem); | |
1484 | ||
1485 | if (ac.shift != NULL_RTX) | |
1486 | { | |
1487 | cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift); | |
0a2aaacc | 1488 | new_rtx = xtensa_expand_mask_and_shift (new_rtx, mode, ac.shift); |
2a48b790 BW |
1489 | } |
1490 | ||
1491 | /* Load the surrounding word into VAL with the MEM value masked out. */ | |
1492 | val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi, | |
1493 | ac.modemaski, NULL_RTX, 1, | |
1494 | OPTAB_DIRECT)); | |
1495 | emit_label (csloop); | |
1496 | ||
0a2aaacc | 1497 | /* Patch CMP and NEW_RTX into VAL at correct position. */ |
2a48b790 BW |
1498 | cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val, |
1499 | NULL_RTX, 1, OPTAB_DIRECT)); | |
0a2aaacc | 1500 | newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val, |
2a48b790 BW |
1501 | NULL_RTX, 1, OPTAB_DIRECT)); |
1502 | ||
1503 | /* Jump to end if we're done. */ | |
1504 | emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv)); | |
1505 | emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend); | |
1506 | ||
1507 | /* Check for changes outside mode. */ | |
1508 | emit_move_insn (oldval, val); | |
1509 | tmp = expand_simple_binop (SImode, AND, res, ac.modemaski, | |
1510 | val, 1, OPTAB_DIRECT); | |
1511 | if (tmp != val) | |
1512 | emit_move_insn (val, tmp); | |
1513 | ||
1514 | /* Loop internal if so. */ | |
1515 | emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop); | |
1516 | ||
1517 | emit_label (csend); | |
1518 | ||
1519 | /* Return the correct part of the bitfield. */ | |
1520 | convert_move (target, | |
1521 | (ac.shift == NULL_RTX ? res | |
1522 | : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift, | |
1523 | NULL_RTX, 1, OPTAB_DIRECT)), | |
1524 | 1); | |
1525 | } | |
1526 | ||
1527 | ||
1528 | /* Expand an atomic operation CODE of mode MODE (either HImode or QImode -- | |
1529 | the default expansion works fine for SImode). MEM is the memory location | |
1530 | and VAL the value to play with. If AFTER is true then store the value | |
1531 | MEM holds after the operation, if AFTER is false then store the value MEM | |
1532 | holds before the operation. If TARGET is zero then discard that value, else | |
1533 | store it to TARGET. */ | |
1534 | ||
1535 | void | |
1536 | xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val, | |
1537 | bool after) | |
1538 | { | |
1539 | enum machine_mode mode = GET_MODE (mem); | |
1540 | struct alignment_context ac; | |
240a513f | 1541 | rtx_code_label *csloop = gen_label_rtx (); |
2a48b790 BW |
1542 | rtx cmp, tmp; |
1543 | rtx old = gen_reg_rtx (SImode); | |
0a2aaacc | 1544 | rtx new_rtx = gen_reg_rtx (SImode); |
2a48b790 BW |
1545 | rtx orig = NULL_RTX; |
1546 | ||
1547 | init_alignment_context (&ac, mem); | |
1548 | ||
1549 | /* Prepare values before the compare-and-swap loop. */ | |
1550 | if (ac.shift != NULL_RTX) | |
1551 | val = xtensa_expand_mask_and_shift (val, mode, ac.shift); | |
1552 | switch (code) | |
1553 | { | |
1554 | case PLUS: | |
1555 | case MINUS: | |
1556 | orig = gen_reg_rtx (SImode); | |
1557 | convert_move (orig, val, 1); | |
1558 | break; | |
1559 | ||
1560 | case SET: | |
1561 | case IOR: | |
1562 | case XOR: | |
1563 | break; | |
1564 | ||
1565 | case MULT: /* NAND */ | |
1566 | case AND: | |
1567 | /* val = "11..1<val>11..1" */ | |
1568 | val = expand_simple_binop (SImode, XOR, val, ac.modemaski, | |
1569 | NULL_RTX, 1, OPTAB_DIRECT); | |
1570 | break; | |
1571 | ||
1572 | default: | |
1573 | gcc_unreachable (); | |
1574 | } | |
1575 | ||
1576 | /* Load full word. Subsequent loads are performed by S32C1I. */ | |
1577 | cmp = force_reg (SImode, ac.memsi); | |
1578 | ||
1579 | emit_label (csloop); | |
1580 | emit_move_insn (old, cmp); | |
1581 | ||
1582 | switch (code) | |
1583 | { | |
1584 | case PLUS: | |
1585 | case MINUS: | |
1586 | val = expand_simple_binop (SImode, code, old, orig, | |
1587 | NULL_RTX, 1, OPTAB_DIRECT); | |
1588 | val = expand_simple_binop (SImode, AND, val, ac.modemask, | |
1589 | NULL_RTX, 1, OPTAB_DIRECT); | |
1590 | /* FALLTHRU */ | |
1591 | case SET: | |
1592 | tmp = expand_simple_binop (SImode, AND, old, ac.modemaski, | |
1593 | NULL_RTX, 1, OPTAB_DIRECT); | |
1594 | tmp = expand_simple_binop (SImode, IOR, tmp, val, | |
0a2aaacc | 1595 | new_rtx, 1, OPTAB_DIRECT); |
2a48b790 BW |
1596 | break; |
1597 | ||
1598 | case AND: | |
1599 | case IOR: | |
1600 | case XOR: | |
1601 | tmp = expand_simple_binop (SImode, code, old, val, | |
0a2aaacc | 1602 | new_rtx, 1, OPTAB_DIRECT); |
2a48b790 BW |
1603 | break; |
1604 | ||
1605 | case MULT: /* NAND */ | |
1606 | tmp = expand_simple_binop (SImode, XOR, old, ac.modemask, | |
1607 | NULL_RTX, 1, OPTAB_DIRECT); | |
1608 | tmp = expand_simple_binop (SImode, AND, tmp, val, | |
0a2aaacc | 1609 | new_rtx, 1, OPTAB_DIRECT); |
2a48b790 BW |
1610 | break; |
1611 | ||
1612 | default: | |
1613 | gcc_unreachable (); | |
1614 | } | |
1615 | ||
0a2aaacc KG |
1616 | if (tmp != new_rtx) |
1617 | emit_move_insn (new_rtx, tmp); | |
1618 | emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new_rtx)); | |
2a48b790 BW |
1619 | emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop); |
1620 | ||
1621 | if (target) | |
1622 | { | |
0a2aaacc | 1623 | tmp = (after ? new_rtx : cmp); |
2a48b790 BW |
1624 | convert_move (target, |
1625 | (ac.shift == NULL_RTX ? tmp | |
1626 | : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift, | |
1627 | NULL_RTX, 1, OPTAB_DIRECT)), | |
1628 | 1); | |
1629 | } | |
1630 | } | |
1631 | ||
1632 | ||
03984308 | 1633 | void |
ffbc8796 | 1634 | xtensa_setup_frame_addresses (void) |
03984308 | 1635 | { |
b52b1749 | 1636 | /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */ |
03984308 BW |
1637 | cfun->machine->accesses_prev_frame = 1; |
1638 | ||
1639 | emit_library_call | |
1640 | (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"), | |
046845de | 1641 | LCT_NORMAL, VOIDmode, 0); |
03984308 BW |
1642 | } |
1643 | ||
1644 | ||
638db43e BW |
1645 | /* Emit the assembly for the end of a zero-cost loop. Normally we just emit |
1646 | a comment showing where the end of the loop is. However, if there is a | |
03984308 | 1647 | label or a branch at the end of the loop then we need to place a nop |
638db43e | 1648 | there. If the loop ends with a label we need the nop so that branches |
839a4992 KH |
1649 | targeting that label will target the nop (and thus remain in the loop), |
1650 | instead of targeting the instruction after the loop (and thus exiting | |
638db43e | 1651 | the loop). If the loop ends with a branch, we need the nop in case the |
839a4992 | 1652 | branch is targeting a location inside the loop. When the branch |
03984308 BW |
1653 | executes it will cause the loop count to be decremented even if it is |
1654 | taken (because it is the last instruction in the loop), so we need to | |
1655 | nop after the branch to prevent the loop count from being decremented | |
638db43e | 1656 | when the branch is taken. */ |
03984308 BW |
1657 | |
1658 | void | |
240a513f | 1659 | xtensa_emit_loop_end (rtx_insn *insn, rtx *operands) |
03984308 BW |
1660 | { |
1661 | char done = 0; | |
1662 | ||
1663 | for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn)) | |
1664 | { | |
1665 | switch (GET_CODE (insn)) | |
1666 | { | |
1667 | case NOTE: | |
1668 | case BARRIER: | |
1669 | break; | |
1670 | ||
1671 | case CODE_LABEL: | |
0bd0703d | 1672 | output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands); |
03984308 BW |
1673 | done = 1; |
1674 | break; | |
1675 | ||
1676 | default: | |
1677 | { | |
1678 | rtx body = PATTERN (insn); | |
1679 | ||
b64925dc | 1680 | if (JUMP_P (body)) |
03984308 | 1681 | { |
0bd0703d | 1682 | output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands); |
03984308 BW |
1683 | done = 1; |
1684 | } | |
1685 | else if ((GET_CODE (body) != USE) | |
1686 | && (GET_CODE (body) != CLOBBER)) | |
1687 | done = 1; | |
1688 | } | |
1689 | break; | |
1690 | } | |
1691 | } | |
1692 | ||
1693 | output_asm_insn ("# loop end for %0", operands); | |
1694 | } | |
1695 | ||
1696 | ||
036a2b7a BW |
1697 | char * |
1698 | xtensa_emit_branch (bool inverted, bool immed, rtx *operands) | |
1699 | { | |
1700 | static char result[64]; | |
1701 | enum rtx_code code; | |
1702 | const char *op; | |
1703 | ||
1704 | code = GET_CODE (operands[3]); | |
1705 | switch (code) | |
1706 | { | |
1707 | case EQ: op = inverted ? "ne" : "eq"; break; | |
1708 | case NE: op = inverted ? "eq" : "ne"; break; | |
1709 | case LT: op = inverted ? "ge" : "lt"; break; | |
1710 | case GE: op = inverted ? "lt" : "ge"; break; | |
1711 | case LTU: op = inverted ? "geu" : "ltu"; break; | |
1712 | case GEU: op = inverted ? "ltu" : "geu"; break; | |
1713 | default: gcc_unreachable (); | |
1714 | } | |
1715 | ||
1716 | if (immed) | |
1717 | { | |
1718 | if (INTVAL (operands[1]) == 0) | |
1719 | sprintf (result, "b%sz%s\t%%0, %%2", op, | |
1720 | (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : ""); | |
1721 | else | |
1722 | sprintf (result, "b%si\t%%0, %%d1, %%2", op); | |
1723 | } | |
1724 | else | |
1725 | sprintf (result, "b%s\t%%0, %%1, %%2", op); | |
1726 | ||
1727 | return result; | |
1728 | } | |
1729 | ||
1730 | ||
1731 | char * | |
1732 | xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands) | |
1733 | { | |
1734 | static char result[64]; | |
1735 | const char *op; | |
1736 | ||
1737 | switch (GET_CODE (operands[3])) | |
1738 | { | |
1739 | case EQ: op = inverted ? "bs" : "bc"; break; | |
1740 | case NE: op = inverted ? "bc" : "bs"; break; | |
1741 | default: gcc_unreachable (); | |
1742 | } | |
1743 | ||
1744 | if (immed) | |
1745 | { | |
1746 | unsigned bitnum = INTVAL (operands[1]) & 0x1f; | |
1747 | operands[1] = GEN_INT (bitnum); | |
1748 | sprintf (result, "b%si\t%%0, %%d1, %%2", op); | |
1749 | } | |
1750 | else | |
1751 | sprintf (result, "b%s\t%%0, %%1, %%2", op); | |
1752 | ||
1753 | return result; | |
1754 | } | |
1755 | ||
1756 | ||
1757 | char * | |
1758 | xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands) | |
1759 | { | |
1760 | static char result[64]; | |
1761 | enum rtx_code code; | |
1762 | const char *op; | |
1763 | ||
1764 | code = GET_CODE (operands[4]); | |
1765 | if (isbool) | |
1766 | { | |
1767 | switch (code) | |
1768 | { | |
1769 | case EQ: op = inverted ? "t" : "f"; break; | |
1770 | case NE: op = inverted ? "f" : "t"; break; | |
1771 | default: gcc_unreachable (); | |
1772 | } | |
1773 | } | |
1774 | else | |
1775 | { | |
1776 | switch (code) | |
1777 | { | |
1778 | case EQ: op = inverted ? "nez" : "eqz"; break; | |
1779 | case NE: op = inverted ? "eqz" : "nez"; break; | |
1780 | case LT: op = inverted ? "gez" : "ltz"; break; | |
1781 | case GE: op = inverted ? "ltz" : "gez"; break; | |
1782 | default: gcc_unreachable (); | |
1783 | } | |
1784 | } | |
1785 | ||
1786 | sprintf (result, "mov%s%s\t%%0, %%%d, %%1", | |
1787 | op, isfp ? ".s" : "", inverted ? 3 : 2); | |
1788 | return result; | |
1789 | } | |
1790 | ||
1791 | ||
03984308 | 1792 | char * |
ffbc8796 | 1793 | xtensa_emit_call (int callop, rtx *operands) |
03984308 | 1794 | { |
b64a1b53 | 1795 | static char result[64]; |
03984308 BW |
1796 | rtx tgt = operands[callop]; |
1797 | ||
1798 | if (GET_CODE (tgt) == CONST_INT) | |
1d0ea52e | 1799 | sprintf (result, "call8\t0x%lx", INTVAL (tgt)); |
03984308 BW |
1800 | else if (register_operand (tgt, VOIDmode)) |
1801 | sprintf (result, "callx8\t%%%d", callop); | |
1802 | else | |
1803 | sprintf (result, "call8\t%%%d", callop); | |
1804 | ||
1805 | return result; | |
1806 | } | |
1807 | ||
1808 | ||
da1f39e4 BW |
1809 | bool |
1810 | xtensa_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict) | |
1811 | { | |
1812 | /* Allow constant pool addresses. */ | |
1813 | if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD | |
6a7a462c BW |
1814 | && ! TARGET_CONST16 && constantpool_address_p (addr) |
1815 | && ! xtensa_tls_referenced_p (addr)) | |
da1f39e4 BW |
1816 | return true; |
1817 | ||
1818 | while (GET_CODE (addr) == SUBREG) | |
1819 | addr = SUBREG_REG (addr); | |
1820 | ||
1821 | /* Allow base registers. */ | |
1822 | if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict)) | |
1823 | return true; | |
1824 | ||
1825 | /* Check for "register + offset" addressing. */ | |
1826 | if (GET_CODE (addr) == PLUS) | |
1827 | { | |
1828 | rtx xplus0 = XEXP (addr, 0); | |
1829 | rtx xplus1 = XEXP (addr, 1); | |
1830 | enum rtx_code code0; | |
1831 | enum rtx_code code1; | |
1832 | ||
1833 | while (GET_CODE (xplus0) == SUBREG) | |
1834 | xplus0 = SUBREG_REG (xplus0); | |
1835 | code0 = GET_CODE (xplus0); | |
1836 | ||
1837 | while (GET_CODE (xplus1) == SUBREG) | |
1838 | xplus1 = SUBREG_REG (xplus1); | |
1839 | code1 = GET_CODE (xplus1); | |
1840 | ||
1841 | /* Swap operands if necessary so the register is first. */ | |
1842 | if (code0 != REG && code1 == REG) | |
1843 | { | |
1844 | xplus0 = XEXP (addr, 1); | |
1845 | xplus1 = XEXP (addr, 0); | |
1846 | code0 = GET_CODE (xplus0); | |
1847 | code1 = GET_CODE (xplus1); | |
1848 | } | |
1849 | ||
1850 | if (code0 == REG && BASE_REG_P (xplus0, strict) | |
1851 | && code1 == CONST_INT | |
1852 | && xtensa_mem_offset (INTVAL (xplus1), mode)) | |
1853 | return true; | |
1854 | } | |
1855 | ||
1856 | return false; | |
1857 | } | |
1858 | ||
1859 | ||
6a7a462c BW |
1860 | /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */ |
1861 | ||
1862 | static GTY(()) rtx xtensa_tls_module_base_symbol; | |
1863 | ||
1864 | static rtx | |
1865 | xtensa_tls_module_base (void) | |
1866 | { | |
1867 | if (! xtensa_tls_module_base_symbol) | |
1868 | { | |
1869 | xtensa_tls_module_base_symbol = | |
1870 | gen_rtx_SYMBOL_REF (Pmode, "_TLS_MODULE_BASE_"); | |
1871 | SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol) | |
1872 | |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT; | |
1873 | } | |
1874 | ||
1875 | return xtensa_tls_module_base_symbol; | |
1876 | } | |
1877 | ||
1878 | ||
240a513f | 1879 | static rtx_insn * |
6a7a462c BW |
1880 | xtensa_call_tls_desc (rtx sym, rtx *retp) |
1881 | { | |
240a513f DM |
1882 | rtx fn, arg, a10; |
1883 | rtx_insn *call_insn, *insns; | |
6a7a462c BW |
1884 | |
1885 | start_sequence (); | |
1886 | fn = gen_reg_rtx (Pmode); | |
1887 | arg = gen_reg_rtx (Pmode); | |
1888 | a10 = gen_rtx_REG (Pmode, 10); | |
1889 | ||
1890 | emit_insn (gen_tls_func (fn, sym)); | |
1891 | emit_insn (gen_tls_arg (arg, sym)); | |
1892 | emit_move_insn (a10, arg); | |
1893 | call_insn = emit_call_insn (gen_tls_call (a10, fn, sym, const1_rtx)); | |
44f370bf | 1894 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), a10); |
6a7a462c BW |
1895 | insns = get_insns (); |
1896 | end_sequence (); | |
1897 | ||
1898 | *retp = a10; | |
1899 | return insns; | |
1900 | } | |
1901 | ||
1902 | ||
1903 | static rtx | |
1904 | xtensa_legitimize_tls_address (rtx x) | |
1905 | { | |
1906 | unsigned int model = SYMBOL_REF_TLS_MODEL (x); | |
240a513f DM |
1907 | rtx dest, tp, ret, modbase, base, addend; |
1908 | rtx_insn *insns; | |
6a7a462c BW |
1909 | |
1910 | dest = gen_reg_rtx (Pmode); | |
1911 | switch (model) | |
1912 | { | |
1913 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
1914 | insns = xtensa_call_tls_desc (x, &ret); | |
1915 | emit_libcall_block (insns, dest, ret, x); | |
1916 | break; | |
1917 | ||
1918 | case TLS_MODEL_LOCAL_DYNAMIC: | |
1919 | base = gen_reg_rtx (Pmode); | |
1920 | modbase = xtensa_tls_module_base (); | |
1921 | insns = xtensa_call_tls_desc (modbase, &ret); | |
1922 | emit_libcall_block (insns, base, ret, modbase); | |
1923 | addend = force_reg (SImode, gen_sym_DTPOFF (x)); | |
1924 | emit_insn (gen_addsi3 (dest, base, addend)); | |
1925 | break; | |
1926 | ||
1927 | case TLS_MODEL_INITIAL_EXEC: | |
1928 | case TLS_MODEL_LOCAL_EXEC: | |
1929 | tp = gen_reg_rtx (SImode); | |
f959607b | 1930 | emit_insn (gen_get_thread_pointersi (tp)); |
6a7a462c BW |
1931 | addend = force_reg (SImode, gen_sym_TPOFF (x)); |
1932 | emit_insn (gen_addsi3 (dest, tp, addend)); | |
1933 | break; | |
1934 | ||
1935 | default: | |
1936 | gcc_unreachable (); | |
1937 | } | |
1938 | ||
1939 | return dest; | |
1940 | } | |
1941 | ||
1942 | ||
da1f39e4 BW |
1943 | rtx |
1944 | xtensa_legitimize_address (rtx x, | |
1945 | rtx oldx ATTRIBUTE_UNUSED, | |
1946 | enum machine_mode mode) | |
1947 | { | |
6a7a462c BW |
1948 | if (xtensa_tls_symbol_p (x)) |
1949 | return xtensa_legitimize_tls_address (x); | |
1950 | ||
da1f39e4 BW |
1951 | if (GET_CODE (x) == PLUS) |
1952 | { | |
1953 | rtx plus0 = XEXP (x, 0); | |
1954 | rtx plus1 = XEXP (x, 1); | |
1955 | ||
1956 | if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) | |
1957 | { | |
1958 | plus0 = XEXP (x, 1); | |
1959 | plus1 = XEXP (x, 0); | |
1960 | } | |
1961 | ||
1962 | /* Try to split up the offset to use an ADDMI instruction. */ | |
1963 | if (GET_CODE (plus0) == REG | |
1964 | && GET_CODE (plus1) == CONST_INT | |
1965 | && !xtensa_mem_offset (INTVAL (plus1), mode) | |
1966 | && !xtensa_simm8 (INTVAL (plus1)) | |
1967 | && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode) | |
1968 | && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) | |
1969 | { | |
1970 | rtx temp = gen_reg_rtx (Pmode); | |
1971 | rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff); | |
1972 | emit_insn (gen_rtx_SET (Pmode, temp, | |
1973 | gen_rtx_PLUS (Pmode, plus0, addmi_offset))); | |
1974 | return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff)); | |
1975 | } | |
1976 | } | |
1977 | ||
506d7b68 | 1978 | return x; |
da1f39e4 BW |
1979 | } |
1980 | ||
a1a79768 AS |
1981 | /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. |
1982 | ||
1983 | Treat constant-pool references as "mode dependent" since they can | |
1984 | only be accessed with SImode loads. This works around a bug in the | |
1985 | combiner where a constant pool reference is temporarily converted | |
1986 | to an HImode load, which is then assumed to zero-extend based on | |
1987 | our definition of LOAD_EXTEND_OP. This is wrong because the high | |
1988 | bits of a 16-bit value in the constant pool are now sign-extended | |
1989 | by default. */ | |
1990 | ||
1991 | static bool | |
5bfed9a9 GJL |
1992 | xtensa_mode_dependent_address_p (const_rtx addr, |
1993 | addr_space_t as ATTRIBUTE_UNUSED) | |
a1a79768 AS |
1994 | { |
1995 | return constantpool_address_p (addr); | |
1996 | } | |
da1f39e4 | 1997 | |
6a7a462c BW |
1998 | /* Return TRUE if X contains any TLS symbol references. */ |
1999 | ||
2000 | bool | |
2001 | xtensa_tls_referenced_p (rtx x) | |
2002 | { | |
2003 | if (! TARGET_HAVE_TLS) | |
2004 | return false; | |
2005 | ||
2f36a994 RS |
2006 | subrtx_iterator::array_type array; |
2007 | FOR_EACH_SUBRTX (iter, array, x, ALL) | |
2008 | { | |
2009 | const_rtx x = *iter; | |
2010 | if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0) | |
2011 | return true; | |
2012 | ||
2013 | /* Ignore TLS references that have already been legitimized. */ | |
2014 | if (GET_CODE (x) == UNSPEC) | |
2015 | switch (XINT (x, 1)) | |
2016 | { | |
2017 | case UNSPEC_TPOFF: | |
2018 | case UNSPEC_DTPOFF: | |
2019 | case UNSPEC_TLS_FUNC: | |
2020 | case UNSPEC_TLS_ARG: | |
2021 | case UNSPEC_TLS_CALL: | |
2022 | iter.skip_subrtxes (); | |
2023 | break; | |
2024 | default: | |
2025 | break; | |
2026 | } | |
2027 | } | |
2028 | return false; | |
6a7a462c BW |
2029 | } |
2030 | ||
2031 | ||
fbbf66e7 RS |
2032 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ |
2033 | ||
2034 | static bool | |
2035 | xtensa_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
2036 | { | |
2037 | return xtensa_tls_referenced_p (x); | |
2038 | } | |
2039 | ||
2040 | ||
b0c6e48f | 2041 | /* Return the debugger register number to use for 'regno'. */ |
03984308 BW |
2042 | |
2043 | int | |
ffbc8796 | 2044 | xtensa_dbx_register_number (int regno) |
03984308 BW |
2045 | { |
2046 | int first = -1; | |
633e4eb4 BW |
2047 | |
2048 | if (GP_REG_P (regno)) | |
2049 | { | |
2050 | regno -= GP_REG_FIRST; | |
2051 | first = 0; | |
2052 | } | |
2053 | else if (BR_REG_P (regno)) | |
2054 | { | |
2055 | regno -= BR_REG_FIRST; | |
2056 | first = 16; | |
2057 | } | |
2058 | else if (FP_REG_P (regno)) | |
2059 | { | |
2060 | regno -= FP_REG_FIRST; | |
b0c6e48f | 2061 | first = 48; |
633e4eb4 | 2062 | } |
03984308 BW |
2063 | else if (ACC_REG_P (regno)) |
2064 | { | |
b0c6e48f BW |
2065 | first = 0x200; /* Start of Xtensa special registers. */ |
2066 | regno = 16; /* ACCLO is special register 16. */ | |
03984308 BW |
2067 | } |
2068 | ||
2069 | /* When optimizing, we sometimes get asked about pseudo-registers | |
638db43e | 2070 | that don't represent hard registers. Return 0 for these. */ |
03984308 BW |
2071 | if (first == -1) |
2072 | return 0; | |
2073 | ||
2074 | return first + regno; | |
2075 | } | |
2076 | ||
2077 | ||
2078 | /* Argument support functions. */ | |
2079 | ||
2080 | /* Initialize CUMULATIVE_ARGS for a function. */ | |
2081 | ||
2082 | void | |
997b8b4d | 2083 | init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming) |
03984308 BW |
2084 | { |
2085 | cum->arg_words = 0; | |
997b8b4d | 2086 | cum->incoming = incoming; |
03984308 BW |
2087 | } |
2088 | ||
ffbc8796 | 2089 | |
03984308 BW |
2090 | /* Advance the argument to the next argument position. */ |
2091 | ||
626a4b31 | 2092 | static void |
d5cc9181 | 2093 | xtensa_function_arg_advance (cumulative_args_t cum, enum machine_mode mode, |
626a4b31 | 2094 | const_tree type, bool named ATTRIBUTE_UNUSED) |
03984308 BW |
2095 | { |
2096 | int words, max; | |
2097 | int *arg_words; | |
2098 | ||
d5cc9181 | 2099 | arg_words = &get_cumulative_args (cum)->arg_words; |
03984308 BW |
2100 | max = MAX_ARGS_IN_REGISTERS; |
2101 | ||
2102 | words = (((mode != BLKmode) | |
2103 | ? (int) GET_MODE_SIZE (mode) | |
2104 | : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
2105 | ||
85d91d5b BW |
2106 | if (*arg_words < max |
2107 | && (targetm.calls.must_pass_in_stack (mode, type) | |
2108 | || *arg_words + words > max)) | |
03984308 BW |
2109 | *arg_words = max; |
2110 | ||
2111 | *arg_words += words; | |
2112 | } | |
2113 | ||
2114 | ||
2115 | /* Return an RTL expression containing the register for the given mode, | |
368ebcd6 | 2116 | or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero |
ffbc8796 | 2117 | if this is an incoming argument to the current function. */ |
03984308 | 2118 | |
626a4b31 | 2119 | static rtx |
d5cc9181 | 2120 | xtensa_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode, |
626a4b31 | 2121 | const_tree type, bool incoming_p) |
03984308 | 2122 | { |
d5cc9181 | 2123 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
03984308 BW |
2124 | int regbase, words, max; |
2125 | int *arg_words; | |
2126 | int regno; | |
03984308 BW |
2127 | |
2128 | arg_words = &cum->arg_words; | |
2129 | regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST); | |
2130 | max = MAX_ARGS_IN_REGISTERS; | |
2131 | ||
2132 | words = (((mode != BLKmode) | |
2133 | ? (int) GET_MODE_SIZE (mode) | |
2134 | : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
2135 | ||
2136 | if (type && (TYPE_ALIGN (type) > BITS_PER_WORD)) | |
822e895c | 2137 | { |
d2348985 | 2138 | int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_WORD; |
822e895c BW |
2139 | *arg_words = (*arg_words + align - 1) & -align; |
2140 | } | |
03984308 BW |
2141 | |
2142 | if (*arg_words + words > max) | |
2143 | return (rtx)0; | |
2144 | ||
2145 | regno = regbase + *arg_words; | |
03984308 | 2146 | |
997b8b4d BW |
2147 | if (cum->incoming && regno <= A7_REG && regno + words > A7_REG) |
2148 | cfun->machine->need_a7_copy = true; | |
03984308 | 2149 | |
997b8b4d | 2150 | return gen_rtx_REG (mode, regno); |
03984308 BW |
2151 | } |
2152 | ||
626a4b31 NF |
2153 | /* Implement TARGET_FUNCTION_ARG. */ |
2154 | ||
2155 | static rtx | |
d5cc9181 | 2156 | xtensa_function_arg (cumulative_args_t cum, enum machine_mode mode, |
626a4b31 NF |
2157 | const_tree type, bool named ATTRIBUTE_UNUSED) |
2158 | { | |
2159 | return xtensa_function_arg_1 (cum, mode, type, false); | |
2160 | } | |
2161 | ||
2162 | /* Implement TARGET_FUNCTION_INCOMING_ARG. */ | |
2163 | ||
2164 | static rtx | |
d5cc9181 | 2165 | xtensa_function_incoming_arg (cumulative_args_t cum, enum machine_mode mode, |
626a4b31 NF |
2166 | const_tree type, bool named ATTRIBUTE_UNUSED) |
2167 | { | |
2168 | return xtensa_function_arg_1 (cum, mode, type, true); | |
2169 | } | |
03984308 | 2170 | |
c2ed6cf8 | 2171 | static unsigned int |
84ec98d2 | 2172 | xtensa_function_arg_boundary (enum machine_mode mode, const_tree type) |
d2348985 BW |
2173 | { |
2174 | unsigned int alignment; | |
2175 | ||
2176 | alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); | |
2177 | if (alignment < PARM_BOUNDARY) | |
2178 | alignment = PARM_BOUNDARY; | |
2179 | if (alignment > STACK_BOUNDARY) | |
2180 | alignment = STACK_BOUNDARY; | |
2181 | return alignment; | |
2182 | } | |
2183 | ||
2184 | ||
6e5ff6e7 | 2185 | static bool |
586de218 | 2186 | xtensa_return_in_msb (const_tree valtype) |
6e5ff6e7 BW |
2187 | { |
2188 | return (TARGET_BIG_ENDIAN | |
2189 | && AGGREGATE_TYPE_P (valtype) | |
2190 | && int_size_in_bytes (valtype) >= UNITS_PER_WORD); | |
2191 | } | |
2192 | ||
2193 | ||
c5387660 JM |
2194 | static void |
2195 | xtensa_option_override (void) | |
03984308 BW |
2196 | { |
2197 | int regno; | |
2198 | enum machine_mode mode; | |
2199 | ||
2200 | if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT) | |
2201 | error ("boolean registers required for the floating-point option"); | |
2202 | ||
638db43e | 2203 | /* Set up array giving whether a given register can hold a given mode. */ |
03984308 BW |
2204 | for (mode = VOIDmode; |
2205 | mode != MAX_MACHINE_MODE; | |
2206 | mode = (enum machine_mode) ((int) mode + 1)) | |
2207 | { | |
2208 | int size = GET_MODE_SIZE (mode); | |
0a2aaacc | 2209 | enum mode_class mclass = GET_MODE_CLASS (mode); |
03984308 BW |
2210 | |
2211 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
2212 | { | |
2213 | int temp; | |
2214 | ||
2215 | if (ACC_REG_P (regno)) | |
f42f5a1b | 2216 | temp = (TARGET_MAC16 |
0a2aaacc | 2217 | && (mclass == MODE_INT) && (size <= UNITS_PER_WORD)); |
03984308 BW |
2218 | else if (GP_REG_P (regno)) |
2219 | temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD)); | |
2220 | else if (FP_REG_P (regno)) | |
2221 | temp = (TARGET_HARD_FLOAT && (mode == SFmode)); | |
2222 | else if (BR_REG_P (regno)) | |
2223 | temp = (TARGET_BOOLEANS && (mode == CCmode)); | |
2224 | else | |
2225 | temp = FALSE; | |
2226 | ||
2227 | xtensa_hard_regno_mode_ok[(int) mode][regno] = temp; | |
2228 | } | |
2229 | } | |
2230 | ||
2231 | init_machine_status = xtensa_init_machine_status; | |
03984308 | 2232 | |
f42f5a1b BW |
2233 | /* Check PIC settings. PIC is only supported when using L32R |
2234 | instructions, and some targets need to always use PIC. */ | |
2235 | if (flag_pic && TARGET_CONST16) | |
2236 | error ("-f%s is not supported with CONST16 instructions", | |
2237 | (flag_pic > 1 ? "PIC" : "pic")); | |
1b408ba1 SA |
2238 | else if (TARGET_FORCE_NO_PIC) |
2239 | flag_pic = 0; | |
f42f5a1b BW |
2240 | else if (XTENSA_ALWAYS_PIC) |
2241 | { | |
2242 | if (TARGET_CONST16) | |
2243 | error ("PIC is required but not supported with CONST16 instructions"); | |
2244 | flag_pic = 1; | |
2245 | } | |
2246 | /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */ | |
2247 | if (flag_pic > 1) | |
03984308 | 2248 | flag_pic = 1; |
166b25dc BW |
2249 | if (flag_pic && !flag_pie) |
2250 | flag_shlib = 1; | |
87c8b4be CT |
2251 | |
2252 | /* Hot/cold partitioning does not work on this architecture, because of | |
2253 | constant pools (the load instruction cannot necessarily reach that far). | |
2254 | Therefore disable it on this architecture. */ | |
2255 | if (flag_reorder_blocks_and_partition) | |
2256 | { | |
2257 | flag_reorder_blocks_and_partition = 0; | |
2258 | flag_reorder_blocks = 1; | |
2259 | } | |
03984308 BW |
2260 | } |
2261 | ||
03984308 BW |
2262 | /* A C compound statement to output to stdio stream STREAM the |
2263 | assembler syntax for an instruction operand X. X is an RTL | |
2264 | expression. | |
2265 | ||
2266 | CODE is a value that can be used to specify one of several ways | |
2267 | of printing the operand. It is used when identical operands | |
2268 | must be printed differently depending on the context. CODE | |
2269 | comes from the '%' specification that was used to request | |
2270 | printing of the operand. If the specification was just '%DIGIT' | |
2271 | then CODE is 0; if the specification was '%LTR DIGIT' then CODE | |
2272 | is the ASCII code for LTR. | |
2273 | ||
2274 | If X is a register, this macro should print the register's name. | |
2275 | The names can be found in an array 'reg_names' whose type is | |
2276 | 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'. | |
2277 | ||
2278 | When the machine description has a specification '%PUNCT' (a '%' | |
2279 | followed by a punctuation character), this macro is called with | |
2280 | a null pointer for X and the punctuation character for CODE. | |
2281 | ||
2282 | 'a', 'c', 'l', and 'n' are reserved. | |
633e4eb4 | 2283 | |
03984308 BW |
2284 | The Xtensa specific codes are: |
2285 | ||
2286 | 'd' CONST_INT, print as signed decimal | |
2287 | 'x' CONST_INT, print as signed hexadecimal | |
2288 | 'K' CONST_INT, print number of bits in mask for EXTUI | |
2289 | 'R' CONST_INT, print (X & 0x1f) | |
2290 | 'L' CONST_INT, print ((32 - X) & 0x1f) | |
2291 | 'D' REG, print second register of double-word register operand | |
2292 | 'N' MEM, print address of next word following a memory operand | |
2293 | 'v' MEM, if memory reference is volatile, output a MEMW before it | |
f42f5a1b BW |
2294 | 't' any constant, add "@h" suffix for top 16 bits |
2295 | 'b' any constant, add "@l" suffix for bottom 16 bits | |
03984308 BW |
2296 | */ |
2297 | ||
2298 | static void | |
ffbc8796 | 2299 | printx (FILE *file, signed int val) |
03984308 | 2300 | { |
ffbc8796 | 2301 | /* Print a hexadecimal value in a nice way. */ |
03984308 BW |
2302 | if ((val > -0xa) && (val < 0xa)) |
2303 | fprintf (file, "%d", val); | |
2304 | else if (val < 0) | |
2305 | fprintf (file, "-0x%x", -val); | |
2306 | else | |
2307 | fprintf (file, "0x%x", val); | |
2308 | } | |
2309 | ||
2310 | ||
2311 | void | |
ffbc8796 | 2312 | print_operand (FILE *file, rtx x, int letter) |
03984308 | 2313 | { |
f42f5a1b | 2314 | if (!x) |
03984308 BW |
2315 | error ("PRINT_OPERAND null pointer"); |
2316 | ||
f42f5a1b | 2317 | switch (letter) |
03984308 | 2318 | { |
f42f5a1b BW |
2319 | case 'D': |
2320 | if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) | |
2321 | fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]); | |
2322 | else | |
2323 | output_operand_lossage ("invalid %%D value"); | |
2324 | break; | |
03984308 | 2325 | |
f42f5a1b BW |
2326 | case 'v': |
2327 | if (GET_CODE (x) == MEM) | |
2328 | { | |
2329 | /* For a volatile memory reference, emit a MEMW before the | |
2330 | load or store. */ | |
66e58b33 | 2331 | if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE) |
f42f5a1b BW |
2332 | fprintf (file, "memw\n\t"); |
2333 | } | |
2334 | else | |
2335 | output_operand_lossage ("invalid %%v value"); | |
2336 | break; | |
03984308 | 2337 | |
f42f5a1b BW |
2338 | case 'N': |
2339 | if (GET_CODE (x) == MEM | |
2340 | && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode)) | |
2341 | { | |
2342 | x = adjust_address (x, GET_MODE (x) == DFmode ? SFmode : SImode, 4); | |
2343 | output_address (XEXP (x, 0)); | |
2344 | } | |
2345 | else | |
2346 | output_operand_lossage ("invalid %%N value"); | |
2347 | break; | |
03984308 | 2348 | |
f42f5a1b BW |
2349 | case 'K': |
2350 | if (GET_CODE (x) == CONST_INT) | |
03984308 | 2351 | { |
f42f5a1b BW |
2352 | int num_bits = 0; |
2353 | unsigned val = INTVAL (x); | |
2354 | while (val & 1) | |
2355 | { | |
2356 | num_bits += 1; | |
2357 | val = val >> 1; | |
2358 | } | |
2359 | if ((val != 0) || (num_bits == 0) || (num_bits > 16)) | |
2360 | fatal_insn ("invalid mask", x); | |
03984308 | 2361 | |
f42f5a1b BW |
2362 | fprintf (file, "%d", num_bits); |
2363 | } | |
2364 | else | |
2365 | output_operand_lossage ("invalid %%K value"); | |
2366 | break; | |
03984308 | 2367 | |
f42f5a1b BW |
2368 | case 'L': |
2369 | if (GET_CODE (x) == CONST_INT) | |
2370 | fprintf (file, "%ld", (32 - INTVAL (x)) & 0x1f); | |
2371 | else | |
2372 | output_operand_lossage ("invalid %%L value"); | |
2373 | break; | |
03984308 | 2374 | |
f42f5a1b BW |
2375 | case 'R': |
2376 | if (GET_CODE (x) == CONST_INT) | |
2377 | fprintf (file, "%ld", INTVAL (x) & 0x1f); | |
2378 | else | |
2379 | output_operand_lossage ("invalid %%R value"); | |
2380 | break; | |
03984308 | 2381 | |
f42f5a1b BW |
2382 | case 'x': |
2383 | if (GET_CODE (x) == CONST_INT) | |
2384 | printx (file, INTVAL (x)); | |
2385 | else | |
2386 | output_operand_lossage ("invalid %%x value"); | |
2387 | break; | |
03984308 | 2388 | |
f42f5a1b BW |
2389 | case 'd': |
2390 | if (GET_CODE (x) == CONST_INT) | |
2391 | fprintf (file, "%ld", INTVAL (x)); | |
2392 | else | |
2393 | output_operand_lossage ("invalid %%d value"); | |
2394 | break; | |
03984308 | 2395 | |
f42f5a1b BW |
2396 | case 't': |
2397 | case 'b': | |
2398 | if (GET_CODE (x) == CONST_INT) | |
2399 | { | |
2400 | printx (file, INTVAL (x)); | |
2401 | fputs (letter == 't' ? "@h" : "@l", file); | |
2402 | } | |
2403 | else if (GET_CODE (x) == CONST_DOUBLE) | |
2404 | { | |
2405 | REAL_VALUE_TYPE r; | |
2406 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
2407 | if (GET_MODE (x) == SFmode) | |
2408 | { | |
2409 | long l; | |
2410 | REAL_VALUE_TO_TARGET_SINGLE (r, l); | |
2411 | fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l'); | |
2412 | } | |
2413 | else | |
2414 | output_operand_lossage ("invalid %%t/%%b value"); | |
2415 | } | |
2416 | else if (GET_CODE (x) == CONST) | |
2417 | { | |
2418 | /* X must be a symbolic constant on ELF. Write an expression | |
2419 | suitable for 'const16' that sets the high or low 16 bits. */ | |
2420 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
2421 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
2422 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
2423 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
2424 | output_operand_lossage ("invalid %%t/%%b value"); | |
2425 | print_operand (file, XEXP (XEXP (x, 0), 0), 0); | |
2426 | fputs (letter == 't' ? "@h" : "@l", file); | |
2427 | /* There must be a non-alphanumeric character between 'h' or 'l' | |
2428 | and the number. The '-' is added by print_operand() already. */ | |
2429 | if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
2430 | fputs ("+", file); | |
2431 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); | |
2432 | } | |
2433 | else | |
633e4eb4 | 2434 | { |
f42f5a1b BW |
2435 | output_addr_const (file, x); |
2436 | fputs (letter == 't' ? "@h" : "@l", file); | |
03984308 BW |
2437 | } |
2438 | break; | |
2439 | ||
2440 | default: | |
f42f5a1b BW |
2441 | if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) |
2442 | fprintf (file, "%s", reg_names[xt_true_regnum (x)]); | |
2443 | else if (GET_CODE (x) == MEM) | |
2444 | output_address (XEXP (x, 0)); | |
2445 | else if (GET_CODE (x) == CONST_INT) | |
2446 | fprintf (file, "%ld", INTVAL (x)); | |
2447 | else | |
2448 | output_addr_const (file, x); | |
03984308 BW |
2449 | } |
2450 | } | |
2451 | ||
2452 | ||
2453 | /* A C compound statement to output to stdio stream STREAM the | |
2454 | assembler syntax for an instruction operand that is a memory | |
fb49053f | 2455 | reference whose address is ADDR. ADDR is an RTL expression. */ |
03984308 BW |
2456 | |
2457 | void | |
ffbc8796 | 2458 | print_operand_address (FILE *file, rtx addr) |
03984308 BW |
2459 | { |
2460 | if (!addr) | |
2461 | error ("PRINT_OPERAND_ADDRESS, null pointer"); | |
2462 | ||
2463 | switch (GET_CODE (addr)) | |
2464 | { | |
2465 | default: | |
2466 | fatal_insn ("invalid address", addr); | |
2467 | break; | |
2468 | ||
2469 | case REG: | |
2470 | fprintf (file, "%s, 0", reg_names [REGNO (addr)]); | |
2471 | break; | |
2472 | ||
2473 | case PLUS: | |
2474 | { | |
2475 | rtx reg = (rtx)0; | |
2476 | rtx offset = (rtx)0; | |
2477 | rtx arg0 = XEXP (addr, 0); | |
2478 | rtx arg1 = XEXP (addr, 1); | |
2479 | ||
2480 | if (GET_CODE (arg0) == REG) | |
2481 | { | |
2482 | reg = arg0; | |
2483 | offset = arg1; | |
2484 | } | |
2485 | else if (GET_CODE (arg1) == REG) | |
2486 | { | |
2487 | reg = arg1; | |
2488 | offset = arg0; | |
2489 | } | |
2490 | else | |
2491 | fatal_insn ("no register in address", addr); | |
2492 | ||
2493 | if (CONSTANT_P (offset)) | |
2494 | { | |
2495 | fprintf (file, "%s, ", reg_names [REGNO (reg)]); | |
2496 | output_addr_const (file, offset); | |
2497 | } | |
2498 | else | |
2499 | fatal_insn ("address offset not a constant", addr); | |
2500 | } | |
2501 | break; | |
2502 | ||
2503 | case LABEL_REF: | |
2504 | case SYMBOL_REF: | |
2505 | case CONST_INT: | |
2506 | case CONST: | |
2507 | output_addr_const (file, addr); | |
2508 | break; | |
2509 | } | |
2510 | } | |
2511 | ||
2ac6bb04 | 2512 | /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */ |
03984308 | 2513 | |
2ac6bb04 | 2514 | static bool |
da1f39e4 BW |
2515 | xtensa_output_addr_const_extra (FILE *fp, rtx x) |
2516 | { | |
2517 | if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1) | |
2518 | { | |
2519 | switch (XINT (x, 1)) | |
2520 | { | |
6a7a462c BW |
2521 | case UNSPEC_TPOFF: |
2522 | output_addr_const (fp, XVECEXP (x, 0, 0)); | |
2523 | fputs ("@TPOFF", fp); | |
2524 | return true; | |
2525 | case UNSPEC_DTPOFF: | |
2526 | output_addr_const (fp, XVECEXP (x, 0, 0)); | |
2527 | fputs ("@DTPOFF", fp); | |
2528 | return true; | |
da1f39e4 BW |
2529 | case UNSPEC_PLT: |
2530 | if (flag_pic) | |
2531 | { | |
2532 | output_addr_const (fp, XVECEXP (x, 0, 0)); | |
2533 | fputs ("@PLT", fp); | |
2534 | return true; | |
2535 | } | |
2536 | break; | |
2537 | default: | |
2538 | break; | |
2539 | } | |
2540 | } | |
2541 | return false; | |
2542 | } | |
2543 | ||
2544 | ||
03984308 | 2545 | void |
ffbc8796 | 2546 | xtensa_output_literal (FILE *file, rtx x, enum machine_mode mode, int labelno) |
03984308 BW |
2547 | { |
2548 | long value_long[2]; | |
b216cd4a | 2549 | REAL_VALUE_TYPE r; |
03984308 | 2550 | int size; |
74ed13f5 | 2551 | rtx first, second; |
03984308 BW |
2552 | |
2553 | fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno); | |
2554 | ||
2555 | switch (GET_MODE_CLASS (mode)) | |
2556 | { | |
2557 | case MODE_FLOAT: | |
177b6be0 | 2558 | gcc_assert (GET_CODE (x) == CONST_DOUBLE); |
03984308 | 2559 | |
b216cd4a | 2560 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
03984308 BW |
2561 | switch (mode) |
2562 | { | |
2563 | case SFmode: | |
b216cd4a | 2564 | REAL_VALUE_TO_TARGET_SINGLE (r, value_long[0]); |
4575a800 BW |
2565 | if (HOST_BITS_PER_LONG > 32) |
2566 | value_long[0] &= 0xffffffff; | |
b216cd4a | 2567 | fprintf (file, "0x%08lx\n", value_long[0]); |
03984308 BW |
2568 | break; |
2569 | ||
2570 | case DFmode: | |
b216cd4a | 2571 | REAL_VALUE_TO_TARGET_DOUBLE (r, value_long); |
4575a800 BW |
2572 | if (HOST_BITS_PER_LONG > 32) |
2573 | { | |
2574 | value_long[0] &= 0xffffffff; | |
2575 | value_long[1] &= 0xffffffff; | |
2576 | } | |
b216cd4a ZW |
2577 | fprintf (file, "0x%08lx, 0x%08lx\n", |
2578 | value_long[0], value_long[1]); | |
03984308 BW |
2579 | break; |
2580 | ||
2581 | default: | |
177b6be0 | 2582 | gcc_unreachable (); |
03984308 BW |
2583 | } |
2584 | ||
2585 | break; | |
2586 | ||
2587 | case MODE_INT: | |
2588 | case MODE_PARTIAL_INT: | |
2589 | size = GET_MODE_SIZE (mode); | |
177b6be0 | 2590 | switch (size) |
03984308 | 2591 | { |
177b6be0 | 2592 | case 4: |
03984308 BW |
2593 | output_addr_const (file, x); |
2594 | fputs ("\n", file); | |
177b6be0 NS |
2595 | break; |
2596 | ||
2597 | case 8: | |
74ed13f5 BW |
2598 | split_double (x, &first, &second); |
2599 | output_addr_const (file, first); | |
03984308 | 2600 | fputs (", ", file); |
74ed13f5 | 2601 | output_addr_const (file, second); |
03984308 | 2602 | fputs ("\n", file); |
177b6be0 NS |
2603 | break; |
2604 | ||
2605 | default: | |
2606 | gcc_unreachable (); | |
03984308 | 2607 | } |
03984308 BW |
2608 | break; |
2609 | ||
2610 | default: | |
177b6be0 | 2611 | gcc_unreachable (); |
03984308 BW |
2612 | } |
2613 | } | |
2614 | ||
2615 | ||
2616 | /* Return the bytes needed to compute the frame pointer from the current | |
638db43e | 2617 | stack pointer. */ |
03984308 BW |
2618 | |
2619 | #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT) | |
2620 | #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1)) | |
2621 | ||
2622 | long | |
ffbc8796 | 2623 | compute_frame_size (int size) |
03984308 | 2624 | { |
ffbc8796 | 2625 | /* Add space for the incoming static chain value. */ |
6de9cd9a | 2626 | if (cfun->static_chain_decl != NULL) |
03984308 BW |
2627 | size += (1 * UNITS_PER_WORD); |
2628 | ||
2629 | xtensa_current_frame_size = | |
2630 | XTENSA_STACK_ALIGN (size | |
38173d38 | 2631 | + crtl->outgoing_args_size |
03984308 BW |
2632 | + (WINDOW_SIZE * UNITS_PER_WORD)); |
2633 | return xtensa_current_frame_size; | |
2634 | } | |
2635 | ||
2636 | ||
b52b1749 | 2637 | bool |
ffbc8796 | 2638 | xtensa_frame_pointer_required (void) |
03984308 BW |
2639 | { |
2640 | /* The code to expand builtin_frame_addr and builtin_return_addr | |
2641 | currently uses the hard_frame_pointer instead of frame_pointer. | |
2642 | This seems wrong but maybe it's necessary for other architectures. | |
638db43e | 2643 | This function is derived from the i386 code. */ |
03984308 BW |
2644 | |
2645 | if (cfun->machine->accesses_prev_frame) | |
b52b1749 | 2646 | return true; |
03984308 | 2647 | |
b52b1749 | 2648 | return false; |
03984308 BW |
2649 | } |
2650 | ||
2651 | ||
7f0ee694 BW |
2652 | /* minimum frame = reg save area (4 words) plus static chain (1 word) |
2653 | and the total number of words must be a multiple of 128 bits. */ | |
2654 | #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD) | |
2655 | ||
f42f5a1b | 2656 | void |
ffbc8796 | 2657 | xtensa_expand_prologue (void) |
f42f5a1b BW |
2658 | { |
2659 | HOST_WIDE_INT total_size; | |
2660 | rtx size_rtx; | |
240a513f DM |
2661 | rtx_insn *insn; |
2662 | rtx note_rtx; | |
18dbd950 | 2663 | |
f42f5a1b BW |
2664 | total_size = compute_frame_size (get_frame_size ()); |
2665 | size_rtx = GEN_INT (total_size); | |
18dbd950 | 2666 | |
f42f5a1b | 2667 | if (total_size < (1 << (12+3))) |
35a3be48 | 2668 | insn = emit_insn (gen_entry (size_rtx)); |
03984308 BW |
2669 | else |
2670 | { | |
f42f5a1b BW |
2671 | /* Use a8 as a temporary since a0-a7 may be live. */ |
2672 | rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG); | |
35a3be48 | 2673 | emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE))); |
f42f5a1b BW |
2674 | emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE)); |
2675 | emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg)); | |
4e6c2193 | 2676 | insn = emit_insn (gen_movsi (stack_pointer_rtx, tmp_reg)); |
03984308 BW |
2677 | } |
2678 | ||
f42f5a1b | 2679 | if (frame_pointer_needed) |
03984308 | 2680 | { |
997b8b4d | 2681 | if (cfun->machine->set_frame_ptr_insn) |
03984308 | 2682 | { |
240a513f | 2683 | rtx_insn *first; |
03984308 | 2684 | |
997b8b4d BW |
2685 | push_topmost_sequence (); |
2686 | first = get_insns (); | |
2687 | pop_topmost_sequence (); | |
03984308 | 2688 | |
f42f5a1b BW |
2689 | /* For all instructions prior to set_frame_ptr_insn, replace |
2690 | hard_frame_pointer references with stack_pointer. */ | |
2691 | for (insn = first; | |
997b8b4d | 2692 | insn != cfun->machine->set_frame_ptr_insn; |
f42f5a1b BW |
2693 | insn = NEXT_INSN (insn)) |
2694 | { | |
2695 | if (INSN_P (insn)) | |
20dca97b BW |
2696 | { |
2697 | PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)), | |
2698 | hard_frame_pointer_rtx, | |
2699 | stack_pointer_rtx); | |
2700 | df_insn_rescan (insn); | |
2701 | } | |
f42f5a1b BW |
2702 | } |
2703 | } | |
2704 | else | |
4e6c2193 BW |
2705 | insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, |
2706 | stack_pointer_rtx)); | |
03984308 | 2707 | } |
4e6c2193 BW |
2708 | |
2709 | /* Create a note to describe the CFA. Because this is only used to set | |
2710 | DW_AT_frame_base for debug info, don't bother tracking changes through | |
2711 | each instruction in the prologue. It just takes up space. */ | |
2712 | note_rtx = gen_rtx_SET (VOIDmode, (frame_pointer_needed | |
2713 | ? hard_frame_pointer_rtx | |
2714 | : stack_pointer_rtx), | |
0a81f074 RS |
2715 | plus_constant (Pmode, stack_pointer_rtx, |
2716 | -total_size)); | |
4e6c2193 | 2717 | RTX_FRAME_RELATED_P (insn) = 1; |
046845de | 2718 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx); |
03984308 BW |
2719 | } |
2720 | ||
2721 | ||
f42f5a1b | 2722 | /* Clear variables at function end. */ |
03984308 BW |
2723 | |
2724 | void | |
ffbc8796 BW |
2725 | xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
2726 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
03984308 | 2727 | { |
03984308 BW |
2728 | xtensa_current_frame_size = 0; |
2729 | } | |
2730 | ||
2731 | ||
0c14a54d | 2732 | rtx |
ffbc8796 | 2733 | xtensa_return_addr (int count, rtx frame) |
0c14a54d | 2734 | { |
7f0ee694 | 2735 | rtx result, retaddr, curaddr, label; |
0c14a54d BW |
2736 | |
2737 | if (count == -1) | |
f42f5a1b | 2738 | retaddr = gen_rtx_REG (Pmode, A0_REG); |
0c14a54d BW |
2739 | else |
2740 | { | |
0a81f074 | 2741 | rtx addr = plus_constant (Pmode, frame, -4 * UNITS_PER_WORD); |
0c14a54d BW |
2742 | addr = memory_address (Pmode, addr); |
2743 | retaddr = gen_reg_rtx (Pmode); | |
2744 | emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr)); | |
2745 | } | |
2746 | ||
2747 | /* The 2 most-significant bits of the return address on Xtensa hold | |
2748 | the register window size. To get the real return address, these | |
7f0ee694 BW |
2749 | bits must be replaced with the high bits from some address in the |
2750 | code. */ | |
2751 | ||
2752 | /* Get the 2 high bits of a local label in the code. */ | |
2753 | curaddr = gen_reg_rtx (Pmode); | |
2754 | label = gen_label_rtx (); | |
2755 | emit_label (label); | |
2756 | LABEL_PRESERVE_P (label) = 1; | |
2757 | emit_move_insn (curaddr, gen_rtx_LABEL_REF (Pmode, label)); | |
2758 | emit_insn (gen_lshrsi3 (curaddr, curaddr, GEN_INT (30))); | |
2759 | emit_insn (gen_ashlsi3 (curaddr, curaddr, GEN_INT (30))); | |
2760 | ||
2761 | /* Clear the 2 high bits of the return address. */ | |
0c14a54d | 2762 | result = gen_reg_rtx (Pmode); |
7f0ee694 BW |
2763 | emit_insn (gen_ashlsi3 (result, retaddr, GEN_INT (2))); |
2764 | emit_insn (gen_lshrsi3 (result, result, GEN_INT (2))); | |
2765 | ||
2766 | /* Combine them to get the result. */ | |
2767 | emit_insn (gen_iorsi3 (result, result, curaddr)); | |
0c14a54d BW |
2768 | return result; |
2769 | } | |
2770 | ||
d9886a9e L |
2771 | /* Disable the use of word-sized or smaller complex modes for structures, |
2772 | and for function arguments in particular, where they cause problems with | |
2773 | register a7. The xtensa_copy_incoming_a7 function assumes that there is | |
2774 | a single reference to an argument in a7, but with small complex modes the | |
2775 | real and imaginary components may be extracted separately, leading to two | |
2776 | uses of the register, only one of which would be replaced. */ | |
2777 | ||
2778 | static bool | |
2779 | xtensa_member_type_forces_blk (const_tree, enum machine_mode mode) | |
2780 | { | |
2781 | return mode == CQImode || mode == CHImode; | |
2782 | } | |
0c14a54d | 2783 | |
03984308 | 2784 | /* Create the va_list data type. |
822e895c BW |
2785 | |
2786 | This structure is set up by __builtin_saveregs. The __va_reg field | |
2787 | points to a stack-allocated region holding the contents of the | |
2788 | incoming argument registers. The __va_ndx field is an index | |
2789 | initialized to the position of the first unnamed (variable) | |
2790 | argument. This same index is also used to address the arguments | |
2791 | passed in memory. Thus, the __va_stk field is initialized to point | |
2792 | to the position of the first argument in memory offset to account | |
2793 | for the arguments passed in registers and to account for the size | |
2794 | of the argument registers not being 16-byte aligned. E.G., there | |
2795 | are 6 argument registers of 4 bytes each, but we want the __va_ndx | |
2796 | for the first stack argument to have the maximal alignment of 16 | |
2797 | bytes, so we offset the __va_stk address by 32 bytes so that | |
2798 | __va_stk[32] references the first argument on the stack. */ | |
03984308 | 2799 | |
c35d187f RH |
2800 | static tree |
2801 | xtensa_build_builtin_va_list (void) | |
03984308 | 2802 | { |
540eaea8 | 2803 | tree f_stk, f_reg, f_ndx, record, type_decl; |
03984308 | 2804 | |
540eaea8 | 2805 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
4c4bde29 AH |
2806 | type_decl = build_decl (BUILTINS_LOCATION, |
2807 | TYPE_DECL, get_identifier ("__va_list_tag"), record); | |
03984308 | 2808 | |
4c4bde29 AH |
2809 | f_stk = build_decl (BUILTINS_LOCATION, |
2810 | FIELD_DECL, get_identifier ("__va_stk"), | |
03984308 | 2811 | ptr_type_node); |
4c4bde29 AH |
2812 | f_reg = build_decl (BUILTINS_LOCATION, |
2813 | FIELD_DECL, get_identifier ("__va_reg"), | |
03984308 | 2814 | ptr_type_node); |
4c4bde29 AH |
2815 | f_ndx = build_decl (BUILTINS_LOCATION, |
2816 | FIELD_DECL, get_identifier ("__va_ndx"), | |
03984308 BW |
2817 | integer_type_node); |
2818 | ||
2819 | DECL_FIELD_CONTEXT (f_stk) = record; | |
2820 | DECL_FIELD_CONTEXT (f_reg) = record; | |
2821 | DECL_FIELD_CONTEXT (f_ndx) = record; | |
2822 | ||
0fd2eac2 | 2823 | TYPE_STUB_DECL (record) = type_decl; |
540eaea8 | 2824 | TYPE_NAME (record) = type_decl; |
03984308 | 2825 | TYPE_FIELDS (record) = f_stk; |
910ad8de NF |
2826 | DECL_CHAIN (f_stk) = f_reg; |
2827 | DECL_CHAIN (f_reg) = f_ndx; | |
03984308 BW |
2828 | |
2829 | layout_type (record); | |
2830 | return record; | |
2831 | } | |
2832 | ||
2833 | ||
2834 | /* Save the incoming argument registers on the stack. Returns the | |
638db43e | 2835 | address of the saved registers. */ |
03984308 | 2836 | |
4c45af42 | 2837 | static rtx |
ffbc8796 | 2838 | xtensa_builtin_saveregs (void) |
03984308 | 2839 | { |
e70312d4 | 2840 | rtx gp_regs; |
38173d38 | 2841 | int arg_words = crtl->args.info.arg_words; |
03984308 | 2842 | int gp_left = MAX_ARGS_IN_REGISTERS - arg_words; |
03984308 | 2843 | |
997b8b4d | 2844 | if (gp_left <= 0) |
03984308 BW |
2845 | return const0_rtx; |
2846 | ||
3bbc2af6 | 2847 | /* Allocate the general-purpose register space. */ |
03984308 BW |
2848 | gp_regs = assign_stack_local |
2849 | (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1); | |
540eaea8 | 2850 | set_mem_alias_set (gp_regs, get_varargs_alias_set ()); |
03984308 BW |
2851 | |
2852 | /* Now store the incoming registers. */ | |
997b8b4d BW |
2853 | cfun->machine->need_a7_copy = true; |
2854 | cfun->machine->vararg_a7 = true; | |
e70312d4 BW |
2855 | move_block_from_reg (GP_ARG_FIRST + arg_words, |
2856 | adjust_address (gp_regs, BLKmode, | |
2857 | arg_words * UNITS_PER_WORD), | |
2858 | gp_left); | |
0d8442b8 BW |
2859 | gcc_assert (cfun->machine->vararg_a7_copy != 0); |
2860 | emit_insn_before (cfun->machine->vararg_a7_copy, get_insns ()); | |
03984308 BW |
2861 | |
2862 | return XEXP (gp_regs, 0); | |
2863 | } | |
2864 | ||
2865 | ||
2866 | /* Implement `va_start' for varargs and stdarg. We look at the | |
638db43e | 2867 | current function to fill in an initial va_list. */ |
03984308 | 2868 | |
d7bd8aeb | 2869 | static void |
ffbc8796 | 2870 | xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) |
03984308 BW |
2871 | { |
2872 | tree f_stk, stk; | |
2873 | tree f_reg, reg; | |
2874 | tree f_ndx, ndx; | |
2875 | tree t, u; | |
2876 | int arg_words; | |
2877 | ||
38173d38 | 2878 | arg_words = crtl->args.info.arg_words; |
03984308 BW |
2879 | |
2880 | f_stk = TYPE_FIELDS (va_list_type_node); | |
910ad8de NF |
2881 | f_reg = DECL_CHAIN (f_stk); |
2882 | f_ndx = DECL_CHAIN (f_reg); | |
03984308 | 2883 | |
47a25a46 | 2884 | stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE); |
fa1615d7 BW |
2885 | reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist), |
2886 | f_reg, NULL_TREE); | |
2887 | ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist), | |
2888 | f_ndx, NULL_TREE); | |
03984308 BW |
2889 | |
2890 | /* Call __builtin_saveregs; save the result in __va_reg */ | |
e70312d4 BW |
2891 | u = make_tree (sizetype, expand_builtin_saveregs ()); |
2892 | u = fold_convert (ptr_type_node, u); | |
726a989a | 2893 | t = build2 (MODIFY_EXPR, ptr_type_node, reg, u); |
03984308 BW |
2894 | TREE_SIDE_EFFECTS (t) = 1; |
2895 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2896 | ||
822e895c | 2897 | /* Set the __va_stk member to ($arg_ptr - 32). */ |
03984308 | 2898 | u = make_tree (ptr_type_node, virtual_incoming_args_rtx); |
5d49b6a7 | 2899 | u = fold_build_pointer_plus_hwi (u, -32); |
726a989a | 2900 | t = build2 (MODIFY_EXPR, ptr_type_node, stk, u); |
03984308 BW |
2901 | TREE_SIDE_EFFECTS (t) = 1; |
2902 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2903 | ||
822e895c BW |
2904 | /* Set the __va_ndx member. If the first variable argument is on |
2905 | the stack, adjust __va_ndx by 2 words to account for the extra | |
2906 | alignment offset for __va_stk. */ | |
2907 | if (arg_words >= MAX_ARGS_IN_REGISTERS) | |
2908 | arg_words += 2; | |
726a989a | 2909 | t = build2 (MODIFY_EXPR, integer_type_node, ndx, |
f4d3e7fd | 2910 | build_int_cst (integer_type_node, arg_words * UNITS_PER_WORD)); |
03984308 BW |
2911 | TREE_SIDE_EFFECTS (t) = 1; |
2912 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2913 | } | |
2914 | ||
2915 | ||
2916 | /* Implement `va_arg'. */ | |
2917 | ||
85d53c1d | 2918 | static tree |
726a989a RB |
2919 | xtensa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
2920 | gimple_seq *post_p ATTRIBUTE_UNUSED) | |
03984308 BW |
2921 | { |
2922 | tree f_stk, stk; | |
2923 | tree f_reg, reg; | |
2924 | tree f_ndx, ndx; | |
85d53c1d RH |
2925 | tree type_size, array, orig_ndx, addr, size, va_size, t; |
2926 | tree lab_false, lab_over, lab_false2; | |
08b0dc1b RH |
2927 | bool indirect; |
2928 | ||
2929 | indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false); | |
2930 | if (indirect) | |
2931 | type = build_pointer_type (type); | |
03984308 | 2932 | |
3712281f BW |
2933 | /* Handle complex values as separate real and imaginary parts. */ |
2934 | if (TREE_CODE (type) == COMPLEX_TYPE) | |
2935 | { | |
85d53c1d | 2936 | tree real_part, imag_part; |
3712281f | 2937 | |
85d53c1d RH |
2938 | real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type), |
2939 | pre_p, NULL); | |
2940 | real_part = get_initialized_tmp_var (real_part, pre_p, NULL); | |
3712281f | 2941 | |
fa1615d7 BW |
2942 | imag_part = xtensa_gimplify_va_arg_expr (unshare_expr (valist), |
2943 | TREE_TYPE (type), | |
85d53c1d RH |
2944 | pre_p, NULL); |
2945 | imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL); | |
3712281f | 2946 | |
47a25a46 | 2947 | return build2 (COMPLEX_EXPR, type, real_part, imag_part); |
3712281f BW |
2948 | } |
2949 | ||
03984308 | 2950 | f_stk = TYPE_FIELDS (va_list_type_node); |
910ad8de NF |
2951 | f_reg = DECL_CHAIN (f_stk); |
2952 | f_ndx = DECL_CHAIN (f_reg); | |
03984308 | 2953 | |
fa1615d7 BW |
2954 | stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, |
2955 | f_stk, NULL_TREE); | |
2956 | reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist), | |
2957 | f_reg, NULL_TREE); | |
2958 | ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist), | |
2959 | f_ndx, NULL_TREE); | |
03984308 | 2960 | |
85d53c1d RH |
2961 | type_size = size_in_bytes (type); |
2962 | va_size = round_up (type_size, UNITS_PER_WORD); | |
2963 | gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue); | |
8be56275 | 2964 | |
03984308 | 2965 | |
822e895c | 2966 | /* First align __va_ndx if necessary for this arg: |
03984308 | 2967 | |
85d53c1d | 2968 | orig_ndx = (AP).__va_ndx; |
822e895c | 2969 | if (__alignof__ (TYPE) > 4 ) |
85d53c1d | 2970 | orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1) |
822e895c | 2971 | & -__alignof__ (TYPE)); */ |
03984308 | 2972 | |
85d53c1d RH |
2973 | orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL); |
2974 | ||
03984308 BW |
2975 | if (TYPE_ALIGN (type) > BITS_PER_WORD) |
2976 | { | |
d2348985 | 2977 | int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT; |
85d53c1d | 2978 | |
fa1615d7 | 2979 | t = build2 (PLUS_EXPR, integer_type_node, unshare_expr (orig_ndx), |
f4d3e7fd BW |
2980 | build_int_cst (integer_type_node, align - 1)); |
2981 | t = build2 (BIT_AND_EXPR, integer_type_node, t, | |
2982 | build_int_cst (integer_type_node, -align)); | |
fa1615d7 | 2983 | gimplify_assign (unshare_expr (orig_ndx), t, pre_p); |
03984308 BW |
2984 | } |
2985 | ||
2986 | ||
2987 | /* Increment __va_ndx to point past the argument: | |
2988 | ||
85d53c1d | 2989 | (AP).__va_ndx = orig_ndx + __va_size (TYPE); */ |
03984308 | 2990 | |
85d53c1d | 2991 | t = fold_convert (integer_type_node, va_size); |
47a25a46 | 2992 | t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t); |
fa1615d7 | 2993 | gimplify_assign (unshare_expr (ndx), t, pre_p); |
03984308 BW |
2994 | |
2995 | ||
2996 | /* Check if the argument is in registers: | |
2997 | ||
bcf88f9b | 2998 | if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4 |
fe984136 | 2999 | && !must_pass_in_stack (type)) |
ffbc8796 | 3000 | __array = (AP).__va_reg; */ |
03984308 | 3001 | |
85d53c1d | 3002 | array = create_tmp_var (ptr_type_node, NULL); |
03984308 | 3003 | |
85d53c1d | 3004 | lab_over = NULL; |
fe984136 | 3005 | if (!targetm.calls.must_pass_in_stack (TYPE_MODE (type), type)) |
bcf88f9b | 3006 | { |
4c4bde29 AH |
3007 | lab_false = create_artificial_label (UNKNOWN_LOCATION); |
3008 | lab_over = create_artificial_label (UNKNOWN_LOCATION); | |
85d53c1d | 3009 | |
fa1615d7 | 3010 | t = build2 (GT_EXPR, boolean_type_node, unshare_expr (ndx), |
f4d3e7fd BW |
3011 | build_int_cst (integer_type_node, |
3012 | MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)); | |
47a25a46 RG |
3013 | t = build3 (COND_EXPR, void_type_node, t, |
3014 | build1 (GOTO_EXPR, void_type_node, lab_false), | |
3015 | NULL_TREE); | |
85d53c1d RH |
3016 | gimplify_and_add (t, pre_p); |
3017 | ||
fa1615d7 | 3018 | gimplify_assign (unshare_expr (array), reg, pre_p); |
85d53c1d | 3019 | |
47a25a46 | 3020 | t = build1 (GOTO_EXPR, void_type_node, lab_over); |
85d53c1d RH |
3021 | gimplify_and_add (t, pre_p); |
3022 | ||
47a25a46 | 3023 | t = build1 (LABEL_EXPR, void_type_node, lab_false); |
85d53c1d | 3024 | gimplify_and_add (t, pre_p); |
bcf88f9b | 3025 | } |
03984308 | 3026 | |
85d53c1d | 3027 | |
03984308 BW |
3028 | /* ...otherwise, the argument is on the stack (never split between |
3029 | registers and the stack -- change __va_ndx if necessary): | |
3030 | ||
3031 | else | |
3032 | { | |
822e895c BW |
3033 | if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4) |
3034 | (AP).__va_ndx = 32 + __va_size (TYPE); | |
03984308 | 3035 | __array = (AP).__va_stk; |
ffbc8796 | 3036 | } */ |
03984308 | 3037 | |
4c4bde29 | 3038 | lab_false2 = create_artificial_label (UNKNOWN_LOCATION); |
03984308 | 3039 | |
fa1615d7 | 3040 | t = build2 (GT_EXPR, boolean_type_node, unshare_expr (orig_ndx), |
f4d3e7fd BW |
3041 | build_int_cst (integer_type_node, |
3042 | MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)); | |
47a25a46 RG |
3043 | t = build3 (COND_EXPR, void_type_node, t, |
3044 | build1 (GOTO_EXPR, void_type_node, lab_false2), | |
3045 | NULL_TREE); | |
85d53c1d | 3046 | gimplify_and_add (t, pre_p); |
03984308 | 3047 | |
fa1615d7 | 3048 | t = size_binop (PLUS_EXPR, unshare_expr (va_size), size_int (32)); |
85d53c1d | 3049 | t = fold_convert (integer_type_node, t); |
fa1615d7 | 3050 | gimplify_assign (unshare_expr (ndx), t, pre_p); |
03984308 | 3051 | |
47a25a46 | 3052 | t = build1 (LABEL_EXPR, void_type_node, lab_false2); |
85d53c1d | 3053 | gimplify_and_add (t, pre_p); |
03984308 | 3054 | |
726a989a | 3055 | gimplify_assign (array, stk, pre_p); |
85d53c1d RH |
3056 | |
3057 | if (lab_over) | |
3058 | { | |
47a25a46 | 3059 | t = build1 (LABEL_EXPR, void_type_node, lab_over); |
85d53c1d RH |
3060 | gimplify_and_add (t, pre_p); |
3061 | } | |
8be56275 | 3062 | |
03984308 BW |
3063 | |
3064 | /* Given the base array pointer (__array) and index to the subsequent | |
3065 | argument (__va_ndx), find the address: | |
3066 | ||
8be56275 BW |
3067 | __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4 |
3068 | ? sizeof (TYPE) | |
3069 | : __va_size (TYPE)) | |
03984308 BW |
3070 | |
3071 | The results are endian-dependent because values smaller than one word | |
ffbc8796 | 3072 | are aligned differently. */ |
03984308 | 3073 | |
633e4eb4 | 3074 | |
85d91d5b | 3075 | if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST) |
8be56275 | 3076 | { |
fa1615d7 | 3077 | t = fold_build2 (GE_EXPR, boolean_type_node, unshare_expr (type_size), |
e70312d4 | 3078 | size_int (PARM_BOUNDARY / BITS_PER_UNIT)); |
fa1615d7 BW |
3079 | t = fold_build3 (COND_EXPR, sizetype, t, unshare_expr (va_size), |
3080 | unshare_expr (type_size)); | |
85d53c1d | 3081 | size = t; |
8be56275 | 3082 | } |
85d53c1d | 3083 | else |
fa1615d7 | 3084 | size = unshare_expr (va_size); |
85d53c1d | 3085 | |
fa1615d7 | 3086 | t = fold_convert (sizetype, unshare_expr (ndx)); |
f4d3e7fd | 3087 | t = build2 (MINUS_EXPR, sizetype, t, size); |
5d49b6a7 | 3088 | addr = fold_build_pointer_plus (unshare_expr (array), t); |
03984308 | 3089 | |
85d53c1d | 3090 | addr = fold_convert (build_pointer_type (type), addr); |
08b0dc1b | 3091 | if (indirect) |
d6e9821f RH |
3092 | addr = build_va_arg_indirect_ref (addr); |
3093 | return build_va_arg_indirect_ref (addr); | |
03984308 BW |
3094 | } |
3095 | ||
3096 | ||
09fa8841 BW |
3097 | /* Builtins. */ |
3098 | ||
3099 | enum xtensa_builtin | |
3100 | { | |
3101 | XTENSA_BUILTIN_UMULSIDI3, | |
3102 | XTENSA_BUILTIN_max | |
3103 | }; | |
3104 | ||
3105 | ||
3106 | static void | |
3107 | xtensa_init_builtins (void) | |
3108 | { | |
6a7a462c | 3109 | tree ftype, decl; |
09fa8841 BW |
3110 | |
3111 | ftype = build_function_type_list (unsigned_intDI_type_node, | |
3112 | unsigned_intSI_type_node, | |
3113 | unsigned_intSI_type_node, NULL_TREE); | |
3114 | ||
6a7a462c BW |
3115 | decl = add_builtin_function ("__builtin_umulsidi3", ftype, |
3116 | XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD, | |
3117 | "__umulsidi3", NULL_TREE); | |
3118 | TREE_NOTHROW (decl) = 1; | |
3119 | TREE_READONLY (decl) = 1; | |
09fa8841 BW |
3120 | } |
3121 | ||
3122 | ||
3123 | static tree | |
f311c3b4 NF |
3124 | xtensa_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args, |
3125 | bool ignore ATTRIBUTE_UNUSED) | |
09fa8841 BW |
3126 | { |
3127 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
3128 | tree arg0, arg1; | |
3129 | ||
6a7a462c | 3130 | switch (fcode) |
09fa8841 | 3131 | { |
6a7a462c | 3132 | case XTENSA_BUILTIN_UMULSIDI3: |
f311c3b4 NF |
3133 | arg0 = args[0]; |
3134 | arg1 = args[1]; | |
09fa8841 BW |
3135 | if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST) |
3136 | || TARGET_MUL32_HIGH) | |
3137 | return fold_build2 (MULT_EXPR, unsigned_intDI_type_node, | |
3138 | fold_convert (unsigned_intDI_type_node, arg0), | |
3139 | fold_convert (unsigned_intDI_type_node, arg1)); | |
6a7a462c BW |
3140 | break; |
3141 | ||
6a7a462c BW |
3142 | default: |
3143 | internal_error ("bad builtin code"); | |
3144 | break; | |
09fa8841 BW |
3145 | } |
3146 | ||
09fa8841 BW |
3147 | return NULL; |
3148 | } | |
3149 | ||
3150 | ||
3151 | static rtx | |
3152 | xtensa_expand_builtin (tree exp, rtx target, | |
3153 | rtx subtarget ATTRIBUTE_UNUSED, | |
3154 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
3155 | int ignore) | |
3156 | { | |
ec3643e8 | 3157 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
09fa8841 | 3158 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
6a7a462c BW |
3159 | |
3160 | switch (fcode) | |
3161 | { | |
3162 | case XTENSA_BUILTIN_UMULSIDI3: | |
3163 | /* The umulsidi3 builtin is just a mechanism to avoid calling the real | |
3164 | __umulsidi3 function when the Xtensa configuration can directly | |
3165 | implement it. If not, just call the function. */ | |
3166 | return expand_call (exp, target, ignore); | |
09fa8841 | 3167 | |
6a7a462c BW |
3168 | default: |
3169 | internal_error ("bad builtin code"); | |
3170 | } | |
09fa8841 BW |
3171 | return NULL_RTX; |
3172 | } | |
3173 | ||
a6e508f9 | 3174 | /* Worker function for TARGET_PREFERRED_RELOAD_CLASS. */ |
09fa8841 | 3175 | |
a6e508f9 AS |
3176 | static reg_class_t |
3177 | xtensa_preferred_reload_class (rtx x, reg_class_t rclass) | |
a8cacfd2 | 3178 | { |
a6e508f9 | 3179 | if (CONSTANT_P (x) && CONST_DOUBLE_P (x)) |
a8cacfd2 BW |
3180 | return NO_REGS; |
3181 | ||
89f6025d BW |
3182 | /* Don't use the stack pointer or hard frame pointer for reloads! |
3183 | The hard frame pointer would normally be OK except that it may | |
3184 | briefly hold an incoming argument in the prologue, and reload | |
3185 | won't know that it is live because the hard frame pointer is | |
3186 | treated specially. */ | |
3187 | ||
0a2aaacc | 3188 | if (rclass == AR_REGS || rclass == GR_REGS) |
89f6025d | 3189 | return RL_REGS; |
a8cacfd2 | 3190 | |
0a2aaacc | 3191 | return rclass; |
a8cacfd2 BW |
3192 | } |
3193 | ||
a6e508f9 AS |
3194 | /* Worker function for TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */ |
3195 | ||
3196 | static reg_class_t | |
3197 | xtensa_preferred_output_reload_class (rtx x ATTRIBUTE_UNUSED, | |
3198 | reg_class_t rclass) | |
3199 | { | |
3200 | /* Don't use the stack pointer or hard frame pointer for reloads! | |
3201 | The hard frame pointer would normally be OK except that it may | |
3202 | briefly hold an incoming argument in the prologue, and reload | |
3203 | won't know that it is live because the hard frame pointer is | |
3204 | treated specially. */ | |
3205 | ||
3206 | if (rclass == AR_REGS || rclass == GR_REGS) | |
3207 | return RL_REGS; | |
3208 | ||
3209 | return rclass; | |
3210 | } | |
3211 | ||
3212 | /* Worker function for TARGET_SECONDARY_RELOAD. */ | |
a8cacfd2 | 3213 | |
a6e508f9 | 3214 | static reg_class_t |
a87cf97e | 3215 | xtensa_secondary_reload (bool in_p, rtx x, reg_class_t rclass, |
37fbe8a3 | 3216 | enum machine_mode mode, secondary_reload_info *sri) |
03984308 BW |
3217 | { |
3218 | int regno; | |
3219 | ||
37fbe8a3 | 3220 | if (in_p && constantpool_mem_p (x)) |
03984308 | 3221 | { |
37fbe8a3 | 3222 | if (rclass == FP_REGS) |
89f6025d | 3223 | return RL_REGS; |
37fbe8a3 BW |
3224 | |
3225 | if (mode == QImode) | |
3226 | sri->icode = CODE_FOR_reloadqi_literal; | |
3227 | else if (mode == HImode) | |
3228 | sri->icode = CODE_FOR_reloadhi_literal; | |
03984308 BW |
3229 | } |
3230 | ||
37fbe8a3 | 3231 | regno = xt_true_regnum (x); |
03984308 | 3232 | if (ACC_REG_P (regno)) |
0a2aaacc KG |
3233 | return ((rclass == GR_REGS || rclass == RL_REGS) ? NO_REGS : RL_REGS); |
3234 | if (rclass == ACC_REG) | |
89f6025d | 3235 | return (GP_REG_P (regno) ? NO_REGS : RL_REGS); |
03984308 BW |
3236 | |
3237 | return NO_REGS; | |
3238 | } | |
3239 | ||
3240 | ||
3241 | void | |
ffbc8796 | 3242 | order_regs_for_local_alloc (void) |
03984308 BW |
3243 | { |
3244 | if (!leaf_function_p ()) | |
3245 | { | |
3246 | memcpy (reg_alloc_order, reg_nonleaf_alloc_order, | |
3247 | FIRST_PSEUDO_REGISTER * sizeof (int)); | |
3248 | } | |
3249 | else | |
3250 | { | |
3251 | int i, num_arg_regs; | |
3252 | int nxt = 0; | |
3253 | ||
3bbc2af6 KH |
3254 | /* Use the AR registers in increasing order (skipping a0 and a1) |
3255 | but save the incoming argument registers for a last resort. */ | |
38173d38 | 3256 | num_arg_regs = crtl->args.info.arg_words; |
03984308 BW |
3257 | if (num_arg_regs > MAX_ARGS_IN_REGISTERS) |
3258 | num_arg_regs = MAX_ARGS_IN_REGISTERS; | |
3259 | for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++) | |
3260 | reg_alloc_order[nxt++] = i + num_arg_regs; | |
3261 | for (i = 0; i < num_arg_regs; i++) | |
3262 | reg_alloc_order[nxt++] = GP_ARG_FIRST + i; | |
3263 | ||
3bbc2af6 | 3264 | /* List the coprocessor registers in order. */ |
985d0d50 BW |
3265 | for (i = 0; i < BR_REG_NUM; i++) |
3266 | reg_alloc_order[nxt++] = BR_REG_FIRST + i; | |
3267 | ||
3bbc2af6 | 3268 | /* List the FP registers in order for now. */ |
03984308 BW |
3269 | for (i = 0; i < 16; i++) |
3270 | reg_alloc_order[nxt++] = FP_REG_FIRST + i; | |
3271 | ||
638db43e | 3272 | /* GCC requires that we list *all* the registers.... */ |
03984308 BW |
3273 | reg_alloc_order[nxt++] = 0; /* a0 = return address */ |
3274 | reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */ | |
3275 | reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */ | |
3276 | reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */ | |
3277 | ||
03984308 BW |
3278 | reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */ |
3279 | } | |
3280 | } | |
3281 | ||
3282 | ||
01abf342 BW |
3283 | /* Some Xtensa targets support multiple bss sections. If the section |
3284 | name ends with ".bss", add SECTION_BSS to the flags. */ | |
3285 | ||
3286 | static unsigned int | |
ffbc8796 | 3287 | xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc) |
01abf342 BW |
3288 | { |
3289 | unsigned int flags = default_section_type_flags (decl, name, reloc); | |
3290 | const char *suffix; | |
3291 | ||
3292 | suffix = strrchr (name, '.'); | |
3293 | if (suffix && strcmp (suffix, ".bss") == 0) | |
3294 | { | |
3295 | if (!decl || (TREE_CODE (decl) == VAR_DECL | |
3296 | && DECL_INITIAL (decl) == NULL_TREE)) | |
3297 | flags |= SECTION_BSS; /* @nobits */ | |
3298 | else | |
d4ee4d25 | 3299 | warning (0, "only uninitialized variables can be placed in a " |
01abf342 BW |
3300 | ".bss section"); |
3301 | } | |
3302 | ||
3303 | return flags; | |
3304 | } | |
3305 | ||
3306 | ||
b64a1b53 RH |
3307 | /* The literal pool stays with the function. */ |
3308 | ||
d6b5193b | 3309 | static section * |
ffbc8796 BW |
3310 | xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED, |
3311 | rtx x ATTRIBUTE_UNUSED, | |
3312 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
b64a1b53 | 3313 | { |
d6b5193b | 3314 | return function_section (current_function_decl); |
b64a1b53 | 3315 | } |
fb49053f | 3316 | |
5378dda2 AS |
3317 | /* Worker function for TARGET_REGISTER_MOVE_COST. */ |
3318 | ||
3319 | static int | |
3320 | xtensa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
3321 | reg_class_t from, reg_class_t to) | |
3322 | { | |
3323 | if (from == to && from != BR_REGS && to != BR_REGS) | |
3324 | return 2; | |
3325 | else if (reg_class_subset_p (from, AR_REGS) | |
3326 | && reg_class_subset_p (to, AR_REGS)) | |
3327 | return 2; | |
3328 | else if (reg_class_subset_p (from, AR_REGS) && to == ACC_REG) | |
3329 | return 3; | |
3330 | else if (from == ACC_REG && reg_class_subset_p (to, AR_REGS)) | |
3331 | return 3; | |
3332 | else | |
3333 | return 10; | |
3334 | } | |
3335 | ||
3336 | /* Worker function for TARGET_MEMORY_MOVE_COST. */ | |
3337 | ||
3338 | static int | |
3339 | xtensa_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
3340 | reg_class_t rclass ATTRIBUTE_UNUSED, | |
3341 | bool in ATTRIBUTE_UNUSED) | |
3342 | { | |
3343 | return 4; | |
3344 | } | |
ffbc8796 | 3345 | |
3c50106f RH |
3346 | /* Compute a (partial) cost for rtx X. Return true if the complete |
3347 | cost has been computed, and false if subexpressions should be | |
3348 | scanned. In either case, *TOTAL contains the cost result. */ | |
3349 | ||
3350 | static bool | |
68f932c4 RS |
3351 | xtensa_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
3352 | int *total, bool speed ATTRIBUTE_UNUSED) | |
3c50106f RH |
3353 | { |
3354 | switch (code) | |
3355 | { | |
3356 | case CONST_INT: | |
3357 | switch (outer_code) | |
3358 | { | |
3359 | case SET: | |
3360 | if (xtensa_simm12b (INTVAL (x))) | |
3361 | { | |
3362 | *total = 4; | |
3363 | return true; | |
3364 | } | |
3365 | break; | |
3366 | case PLUS: | |
3367 | if (xtensa_simm8 (INTVAL (x)) | |
3368 | || xtensa_simm8x256 (INTVAL (x))) | |
3369 | { | |
3370 | *total = 0; | |
3371 | return true; | |
3372 | } | |
3373 | break; | |
3374 | case AND: | |
3375 | if (xtensa_mask_immediate (INTVAL (x))) | |
3376 | { | |
3377 | *total = 0; | |
3378 | return true; | |
3379 | } | |
3380 | break; | |
3381 | case COMPARE: | |
3382 | if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x))) | |
3383 | { | |
3384 | *total = 0; | |
3385 | return true; | |
3386 | } | |
3387 | break; | |
3388 | case ASHIFT: | |
3389 | case ASHIFTRT: | |
3390 | case LSHIFTRT: | |
3391 | case ROTATE: | |
3392 | case ROTATERT: | |
3bbc2af6 | 3393 | /* No way to tell if X is the 2nd operand so be conservative. */ |
3c50106f RH |
3394 | default: break; |
3395 | } | |
3396 | if (xtensa_simm12b (INTVAL (x))) | |
3397 | *total = 5; | |
f42f5a1b BW |
3398 | else if (TARGET_CONST16) |
3399 | *total = COSTS_N_INSNS (2); | |
3c50106f RH |
3400 | else |
3401 | *total = 6; | |
3402 | return true; | |
3403 | ||
3404 | case CONST: | |
3405 | case LABEL_REF: | |
3406 | case SYMBOL_REF: | |
f42f5a1b BW |
3407 | if (TARGET_CONST16) |
3408 | *total = COSTS_N_INSNS (2); | |
3409 | else | |
3410 | *total = 5; | |
3c50106f RH |
3411 | return true; |
3412 | ||
3413 | case CONST_DOUBLE: | |
f42f5a1b BW |
3414 | if (TARGET_CONST16) |
3415 | *total = COSTS_N_INSNS (4); | |
3416 | else | |
3417 | *total = 7; | |
3c50106f RH |
3418 | return true; |
3419 | ||
3420 | case MEM: | |
3421 | { | |
3422 | int num_words = | |
3423 | (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) ? 2 : 1; | |
3424 | ||
3425 | if (memory_address_p (GET_MODE (x), XEXP ((x), 0))) | |
3426 | *total = COSTS_N_INSNS (num_words); | |
3427 | else | |
3428 | *total = COSTS_N_INSNS (2*num_words); | |
3429 | return true; | |
3430 | } | |
3431 | ||
3432 | case FFS: | |
09fa8841 | 3433 | case CTZ: |
3c50106f RH |
3434 | *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50); |
3435 | return true; | |
3436 | ||
09fa8841 BW |
3437 | case CLZ: |
3438 | *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50); | |
3439 | return true; | |
3440 | ||
3c50106f RH |
3441 | case NOT: |
3442 | *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 3 : 2); | |
3443 | return true; | |
3444 | ||
3445 | case AND: | |
3446 | case IOR: | |
3447 | case XOR: | |
3448 | if (GET_MODE (x) == DImode) | |
3449 | *total = COSTS_N_INSNS (2); | |
3450 | else | |
3451 | *total = COSTS_N_INSNS (1); | |
3452 | return true; | |
3453 | ||
3454 | case ASHIFT: | |
3455 | case ASHIFTRT: | |
3456 | case LSHIFTRT: | |
3457 | if (GET_MODE (x) == DImode) | |
3458 | *total = COSTS_N_INSNS (50); | |
3459 | else | |
3460 | *total = COSTS_N_INSNS (1); | |
3461 | return true; | |
3462 | ||
3463 | case ABS: | |
3464 | { | |
3465 | enum machine_mode xmode = GET_MODE (x); | |
3466 | if (xmode == SFmode) | |
3467 | *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); | |
3468 | else if (xmode == DFmode) | |
3469 | *total = COSTS_N_INSNS (50); | |
3470 | else | |
3471 | *total = COSTS_N_INSNS (4); | |
3472 | return true; | |
3473 | } | |
3474 | ||
3475 | case PLUS: | |
3476 | case MINUS: | |
3477 | { | |
3478 | enum machine_mode xmode = GET_MODE (x); | |
3479 | if (xmode == SFmode) | |
3480 | *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); | |
3481 | else if (xmode == DFmode || xmode == DImode) | |
3482 | *total = COSTS_N_INSNS (50); | |
3483 | else | |
3484 | *total = COSTS_N_INSNS (1); | |
3485 | return true; | |
3486 | } | |
3487 | ||
3488 | case NEG: | |
3489 | *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 4 : 2); | |
3490 | return true; | |
3491 | ||
3492 | case MULT: | |
3493 | { | |
3494 | enum machine_mode xmode = GET_MODE (x); | |
3495 | if (xmode == SFmode) | |
3496 | *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50); | |
09fa8841 | 3497 | else if (xmode == DFmode) |
3c50106f | 3498 | *total = COSTS_N_INSNS (50); |
09fa8841 BW |
3499 | else if (xmode == DImode) |
3500 | *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50); | |
3c50106f RH |
3501 | else if (TARGET_MUL32) |
3502 | *total = COSTS_N_INSNS (4); | |
3503 | else if (TARGET_MAC16) | |
3504 | *total = COSTS_N_INSNS (16); | |
3505 | else if (TARGET_MUL16) | |
3506 | *total = COSTS_N_INSNS (12); | |
3507 | else | |
3508 | *total = COSTS_N_INSNS (50); | |
3509 | return true; | |
3510 | } | |
3511 | ||
3512 | case DIV: | |
3513 | case MOD: | |
3514 | { | |
3515 | enum machine_mode xmode = GET_MODE (x); | |
3516 | if (xmode == SFmode) | |
3517 | { | |
3518 | *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50); | |
3519 | return true; | |
3520 | } | |
3521 | else if (xmode == DFmode) | |
3522 | { | |
3523 | *total = COSTS_N_INSNS (50); | |
3524 | return true; | |
3525 | } | |
3526 | } | |
3bbc2af6 | 3527 | /* Fall through. */ |
3c50106f RH |
3528 | |
3529 | case UDIV: | |
3530 | case UMOD: | |
3531 | { | |
3532 | enum machine_mode xmode = GET_MODE (x); | |
3533 | if (xmode == DImode) | |
3534 | *total = COSTS_N_INSNS (50); | |
3535 | else if (TARGET_DIV32) | |
3536 | *total = COSTS_N_INSNS (32); | |
3537 | else | |
3538 | *total = COSTS_N_INSNS (50); | |
3539 | return true; | |
3540 | } | |
3541 | ||
3542 | case SQRT: | |
3543 | if (GET_MODE (x) == SFmode) | |
3544 | *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50); | |
3545 | else | |
3546 | *total = COSTS_N_INSNS (50); | |
3547 | return true; | |
3548 | ||
3549 | case SMIN: | |
3550 | case UMIN: | |
3551 | case SMAX: | |
3552 | case UMAX: | |
3553 | *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50); | |
3554 | return true; | |
3555 | ||
3556 | case SIGN_EXTRACT: | |
3557 | case SIGN_EXTEND: | |
3558 | *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2); | |
3559 | return true; | |
3560 | ||
3561 | case ZERO_EXTRACT: | |
3562 | case ZERO_EXTEND: | |
3563 | *total = COSTS_N_INSNS (1); | |
3564 | return true; | |
3565 | ||
3566 | default: | |
3567 | return false; | |
3568 | } | |
3569 | } | |
3570 | ||
bd5bd7ac KH |
3571 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
3572 | ||
4c45af42 | 3573 | static bool |
586de218 | 3574 | xtensa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
4c45af42 KH |
3575 | { |
3576 | return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) | |
3577 | > 4 * UNITS_PER_WORD); | |
3578 | } | |
3579 | ||
e2b2d01e AS |
3580 | /* Worker function for TARGET_FUNCTION_VALUE. */ |
3581 | ||
3582 | rtx | |
3583 | xtensa_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED, | |
3584 | bool outgoing) | |
3585 | { | |
3586 | return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype) | |
3587 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
3588 | ? SImode : TYPE_MODE (valtype), | |
3589 | outgoing ? GP_OUTGOING_RETURN : GP_RETURN); | |
3590 | } | |
7f0ee694 | 3591 | |
dde8a3a4 AS |
3592 | /* Worker function for TARGET_LIBCALL_VALUE. */ |
3593 | ||
3594 | static rtx | |
3595 | xtensa_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) | |
3596 | { | |
3597 | return gen_rtx_REG ((GET_MODE_CLASS (mode) == MODE_INT | |
3598 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
3599 | ? SImode : mode, GP_RETURN); | |
3600 | } | |
3601 | ||
3602 | /* Worker function TARGET_FUNCTION_VALUE_REGNO_P. */ | |
3603 | ||
3604 | static bool | |
3605 | xtensa_function_value_regno_p (const unsigned int regno) | |
3606 | { | |
3607 | return (regno == GP_RETURN); | |
3608 | } | |
3609 | ||
2b4fa409 RH |
3610 | /* The static chain is passed in memory. Provide rtx giving 'mem' |
3611 | expressions that denote where they are stored. */ | |
3612 | ||
3613 | static rtx | |
3614 | xtensa_static_chain (const_tree ARG_UNUSED (fndecl), bool incoming_p) | |
3615 | { | |
3616 | rtx base = incoming_p ? arg_pointer_rtx : stack_pointer_rtx; | |
0a81f074 RS |
3617 | return gen_frame_mem (Pmode, plus_constant (Pmode, base, |
3618 | -5 * UNITS_PER_WORD)); | |
2b4fa409 RH |
3619 | } |
3620 | ||
3621 | ||
7f0ee694 BW |
3622 | /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY |
3623 | instruction with a minimal stack frame in order to get some free | |
3624 | registers. Once the actual call target is known, the proper stack frame | |
3625 | size is extracted from the ENTRY instruction at the target and the | |
3626 | current frame is adjusted to match. The trampoline then transfers | |
3627 | control to the instruction following the ENTRY at the target. Note: | |
3628 | this assumes that the target begins with an ENTRY instruction. */ | |
3629 | ||
3c1229cb RH |
3630 | static void |
3631 | xtensa_asm_trampoline_template (FILE *stream) | |
7f0ee694 BW |
3632 | { |
3633 | bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS); | |
3634 | ||
3635 | fprintf (stream, "\t.begin no-transform\n"); | |
3636 | fprintf (stream, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); | |
3637 | ||
3638 | if (use_call0) | |
3639 | { | |
3640 | /* Save the return address. */ | |
3641 | fprintf (stream, "\tmov\ta10, a0\n"); | |
3642 | ||
3643 | /* Use a CALL0 instruction to skip past the constants and in the | |
3644 | process get the PC into A0. This allows PC-relative access to | |
3645 | the constants without relying on L32R. */ | |
3646 | fprintf (stream, "\tcall0\t.Lskipconsts\n"); | |
3647 | } | |
3648 | else | |
3649 | fprintf (stream, "\tj\t.Lskipconsts\n"); | |
3650 | ||
3651 | fprintf (stream, "\t.align\t4\n"); | |
3652 | fprintf (stream, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); | |
3653 | fprintf (stream, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); | |
3654 | fprintf (stream, ".Lskipconsts:\n"); | |
3655 | ||
3656 | /* Load the static chain and function address from the trampoline. */ | |
3657 | if (use_call0) | |
3658 | { | |
3659 | fprintf (stream, "\taddi\ta0, a0, 3\n"); | |
3660 | fprintf (stream, "\tl32i\ta9, a0, 0\n"); | |
3661 | fprintf (stream, "\tl32i\ta8, a0, 4\n"); | |
3662 | } | |
3663 | else | |
3664 | { | |
3665 | fprintf (stream, "\tl32r\ta9, .Lchainval\n"); | |
3666 | fprintf (stream, "\tl32r\ta8, .Lfnaddr\n"); | |
3667 | } | |
3668 | ||
3669 | /* Store the static chain. */ | |
3670 | fprintf (stream, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE - 20); | |
3671 | ||
3672 | /* Set the proper stack pointer value. */ | |
3673 | fprintf (stream, "\tl32i\ta9, a8, 0\n"); | |
3674 | fprintf (stream, "\textui\ta9, a9, %d, 12\n", | |
3675 | TARGET_BIG_ENDIAN ? 8 : 12); | |
3676 | fprintf (stream, "\tslli\ta9, a9, 3\n"); | |
3677 | fprintf (stream, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); | |
3678 | fprintf (stream, "\tsub\ta9, sp, a9\n"); | |
3679 | fprintf (stream, "\tmovsp\tsp, a9\n"); | |
3680 | ||
3681 | if (use_call0) | |
3682 | /* Restore the return address. */ | |
3683 | fprintf (stream, "\tmov\ta0, a10\n"); | |
3684 | ||
3685 | /* Jump to the instruction following the ENTRY. */ | |
3686 | fprintf (stream, "\taddi\ta8, a8, 3\n"); | |
3687 | fprintf (stream, "\tjx\ta8\n"); | |
3688 | ||
3689 | /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */ | |
3690 | if (use_call0) | |
3691 | fprintf (stream, "\t.byte\t0\n"); | |
3692 | else | |
3693 | fprintf (stream, "\tnop\n"); | |
3694 | ||
3695 | fprintf (stream, "\t.end no-transform\n"); | |
3696 | } | |
3697 | ||
3c1229cb RH |
3698 | static void |
3699 | xtensa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain) | |
7f0ee694 | 3700 | { |
3c1229cb | 3701 | rtx func = XEXP (DECL_RTL (fndecl), 0); |
7f0ee694 BW |
3702 | bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS); |
3703 | int chain_off = use_call0 ? 12 : 8; | |
3704 | int func_off = use_call0 ? 16 : 12; | |
3c1229cb RH |
3705 | |
3706 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
3707 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
3708 | ||
3709 | emit_move_insn (adjust_address (m_tramp, SImode, chain_off), chain); | |
3710 | emit_move_insn (adjust_address (m_tramp, SImode, func_off), func); | |
7f0ee694 | 3711 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"), |
046845de | 3712 | LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode); |
7f0ee694 BW |
3713 | } |
3714 | ||
1a627b35 RS |
3715 | /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ |
3716 | ||
3717 | static bool | |
3718 | xtensa_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
3719 | { | |
3720 | return !xtensa_tls_referenced_p (x); | |
3721 | } | |
7f0ee694 | 3722 | |
e2500fed | 3723 | #include "gt-xtensa.h" |