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03984308 | 1 | /* Definitions of Tensilica's Xtensa target machine for GNU compiler. |
dde8a3a4 | 2 | Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
da1f39e4 | 3 | Free Software Foundation, Inc. |
03984308 BW |
4 | Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it under | |
9 | the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 10 | Software Foundation; either version 3, or (at your option) any later |
03984308 BW |
11 | version. |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
03984308 BW |
21 | |
22 | /* Get Xtensa configuration settings */ | |
e677f70c | 23 | #include "xtensa-config.h" |
03984308 | 24 | |
03984308 BW |
25 | /* External variables defined in xtensa.c. */ |
26 | ||
03984308 BW |
27 | extern unsigned xtensa_current_frame_size; |
28 | ||
6cedbe44 BW |
29 | /* Macros used in the machine description to select various Xtensa |
30 | configuration options. */ | |
327e3a03 BW |
31 | #ifndef XCHAL_HAVE_MUL32_HIGH |
32 | #define XCHAL_HAVE_MUL32_HIGH 0 | |
33 | #endif | |
2a48b790 BW |
34 | #ifndef XCHAL_HAVE_RELEASE_SYNC |
35 | #define XCHAL_HAVE_RELEASE_SYNC 0 | |
36 | #endif | |
37 | #ifndef XCHAL_HAVE_S32C1I | |
38 | #define XCHAL_HAVE_S32C1I 0 | |
39 | #endif | |
6a7a462c BW |
40 | #ifndef XCHAL_HAVE_THREADPTR |
41 | #define XCHAL_HAVE_THREADPTR 0 | |
42 | #endif | |
6cedbe44 BW |
43 | #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE |
44 | #define TARGET_DENSITY XCHAL_HAVE_DENSITY | |
45 | #define TARGET_MAC16 XCHAL_HAVE_MAC16 | |
46 | #define TARGET_MUL16 XCHAL_HAVE_MUL16 | |
47 | #define TARGET_MUL32 XCHAL_HAVE_MUL32 | |
09fa8841 | 48 | #define TARGET_MUL32_HIGH XCHAL_HAVE_MUL32_HIGH |
6cedbe44 BW |
49 | #define TARGET_DIV32 XCHAL_HAVE_DIV32 |
50 | #define TARGET_NSA XCHAL_HAVE_NSA | |
51 | #define TARGET_MINMAX XCHAL_HAVE_MINMAX | |
52 | #define TARGET_SEXT XCHAL_HAVE_SEXT | |
53 | #define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS | |
54 | #define TARGET_HARD_FLOAT XCHAL_HAVE_FP | |
55 | #define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV | |
56 | #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP | |
57 | #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT | |
58 | #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT | |
59 | #define TARGET_ABS XCHAL_HAVE_ABS | |
60 | #define TARGET_ADDX XCHAL_HAVE_ADDX | |
2a48b790 BW |
61 | #define TARGET_RELEASE_SYNC XCHAL_HAVE_RELEASE_SYNC |
62 | #define TARGET_S32C1I XCHAL_HAVE_S32C1I | |
7f0ee694 | 63 | #define TARGET_ABSOLUTE_LITERALS XSHAL_USE_ABSOLUTE_LITERALS |
6a7a462c | 64 | #define TARGET_THREADPTR XCHAL_HAVE_THREADPTR |
6cedbe44 | 65 | |
66e58b33 BW |
66 | #define TARGET_DEFAULT \ |
67 | ((XCHAL_HAVE_L32R ? 0 : MASK_CONST16) | \ | |
68 | MASK_SERIALIZE_VOLATILE) | |
03984308 | 69 | |
6a7a462c BW |
70 | #ifndef HAVE_AS_TLS |
71 | #define HAVE_AS_TLS 0 | |
72 | #endif | |
73 | ||
624f0d60 BW |
74 | \f |
75 | /* Target CPU builtins. */ | |
76 | #define TARGET_CPU_CPP_BUILTINS() \ | |
77 | do { \ | |
78 | builtin_assert ("cpu=xtensa"); \ | |
79 | builtin_assert ("machine=xtensa"); \ | |
48c0150c | 80 | builtin_define ("__xtensa__"); \ |
624f0d60 | 81 | builtin_define ("__XTENSA__"); \ |
c0b57a5a | 82 | builtin_define ("__XTENSA_WINDOWED_ABI__"); \ |
624f0d60 BW |
83 | builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \ |
84 | if (!TARGET_HARD_FLOAT) \ | |
85 | builtin_define ("__XTENSA_SOFT_FLOAT__"); \ | |
624f0d60 | 86 | } while (0) |
03984308 | 87 | |
6a2b287f BW |
88 | #define CPP_SPEC " %(subtarget_cpp_spec) " |
89 | ||
90 | #ifndef SUBTARGET_CPP_SPEC | |
91 | #define SUBTARGET_CPP_SPEC "" | |
92 | #endif | |
93 | ||
ab409f1b | 94 | #define EXTRA_SPECS \ |
6a2b287f BW |
95 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, |
96 | ||
03984308 BW |
97 | /* Target machine storage layout */ |
98 | ||
03984308 BW |
99 | /* Define this if most significant bit is lowest numbered |
100 | in instructions that operate on numbered bit-fields. */ | |
101 | #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) | |
102 | ||
3bbc2af6 | 103 | /* Define this if most significant byte of a word is the lowest numbered. */ |
03984308 BW |
104 | #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) |
105 | ||
3bbc2af6 | 106 | /* Define this if most significant word of a multiword number is the lowest. */ |
03984308 BW |
107 | #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) |
108 | ||
03984308 BW |
109 | #define MAX_BITS_PER_WORD 32 |
110 | ||
111 | /* Width of a word, in units (bytes). */ | |
112 | #define UNITS_PER_WORD 4 | |
113 | #define MIN_UNITS_PER_WORD 4 | |
114 | ||
115 | /* Width of a floating point register. */ | |
116 | #define UNITS_PER_FPREG 4 | |
117 | ||
118 | /* Size in bits of various types on the target machine. */ | |
119 | #define INT_TYPE_SIZE 32 | |
03984308 BW |
120 | #define SHORT_TYPE_SIZE 16 |
121 | #define LONG_TYPE_SIZE 32 | |
03984308 | 122 | #define LONG_LONG_TYPE_SIZE 64 |
03984308 BW |
123 | #define FLOAT_TYPE_SIZE 32 |
124 | #define DOUBLE_TYPE_SIZE 64 | |
125 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
03984308 | 126 | |
03984308 BW |
127 | /* Allocation boundary (in *bits*) for storing pointers in memory. */ |
128 | #define POINTER_BOUNDARY 32 | |
129 | ||
130 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
131 | #define PARM_BOUNDARY 32 | |
132 | ||
133 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
134 | #define FUNCTION_BOUNDARY 32 | |
135 | ||
136 | /* Alignment of field after 'int : 0' in a structure. */ | |
137 | #define EMPTY_FIELD_BOUNDARY 32 | |
138 | ||
139 | /* Every structure's size must be a multiple of this. */ | |
140 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
141 | ||
142 | /* There is no point aligning anything to a rounder boundary than this. */ | |
143 | #define BIGGEST_ALIGNMENT 128 | |
144 | ||
145 | /* Set this nonzero if move instructions will actually fail to work | |
146 | when given unaligned data. */ | |
147 | #define STRICT_ALIGNMENT 1 | |
148 | ||
149 | /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP | |
150 | for QImode, because there is no 8-bit load from memory with sign | |
151 | extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit | |
152 | loads both with and without sign extension. */ | |
153 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
154 | do { \ | |
155 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
156 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
157 | { \ | |
158 | if ((MODE) == QImode) \ | |
159 | (UNSIGNEDP) = 1; \ | |
160 | (MODE) = SImode; \ | |
161 | } \ | |
162 | } while (0) | |
163 | ||
03984308 BW |
164 | /* Imitate the way many other C compilers handle alignment of |
165 | bitfields and the structures that contain them. */ | |
166 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
167 | ||
9a7363b9 BW |
168 | /* Disable the use of word-sized or smaller complex modes for structures, |
169 | and for function arguments in particular, where they cause problems with | |
170 | register a7. The xtensa_copy_incoming_a7 function assumes that there is | |
171 | a single reference to an argument in a7, but with small complex modes the | |
172 | real and imaginary components may be extracted separately, leading to two | |
173 | uses of the register, only one of which would be replaced. */ | |
174 | #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \ | |
175 | ((MODE) == CQImode || (MODE) == CHImode) | |
176 | ||
03984308 BW |
177 | /* Align string constants and constructors to at least a word boundary. |
178 | The typical use of this macro is to increase alignment for string | |
179 | constants to be word aligned so that 'strcpy' calls that copy | |
180 | constants can be done inline. */ | |
181 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
182 | ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ | |
183 | && (ALIGN) < BITS_PER_WORD \ | |
184 | ? BITS_PER_WORD \ | |
185 | : (ALIGN)) | |
186 | ||
187 | /* Align arrays, unions and records to at least a word boundary. | |
188 | One use of this macro is to increase alignment of medium-size | |
189 | data to make it all fit in fewer cache lines. Another is to | |
190 | cause character arrays to be word-aligned so that 'strcpy' calls | |
191 | that copy constants to character arrays can be done inline. */ | |
192 | #undef DATA_ALIGNMENT | |
193 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
194 | ((((ALIGN) < BITS_PER_WORD) \ | |
195 | && (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
196 | || TREE_CODE (TYPE) == UNION_TYPE \ | |
197 | || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
198 | ||
03984308 BW |
199 | /* Operations between registers always perform the operation |
200 | on the full register even if a narrower mode is specified. */ | |
201 | #define WORD_REGISTER_OPERATIONS | |
202 | ||
203 | /* Xtensa loads are zero-extended by default. */ | |
204 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
205 | ||
206 | /* Standard register usage. */ | |
207 | ||
208 | /* Number of actual hardware registers. | |
209 | The hardware registers are assigned numbers for the compiler | |
210 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
211 | All registers that the compiler knows about must be given numbers, | |
212 | even those that are not normally considered general registers. | |
213 | ||
214 | The fake frame pointer and argument pointer will never appear in | |
215 | the generated code, since they will always be eliminated and replaced | |
216 | by either the stack pointer or the hard frame pointer. | |
217 | ||
218 | 0 - 15 AR[0] - AR[15] | |
219 | 16 FRAME_POINTER (fake = initial sp) | |
220 | 17 ARG_POINTER (fake = initial sp + framesize) | |
03984308 BW |
221 | 18 BR[0] for floating-point CC |
222 | 19 - 34 FR[0] - FR[15] | |
223 | 35 MAC16 accumulator */ | |
224 | ||
225 | #define FIRST_PSEUDO_REGISTER 36 | |
226 | ||
3bbc2af6 | 227 | /* Return the stabs register number to use for REGNO. */ |
03984308 BW |
228 | #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO) |
229 | ||
230 | /* 1 for registers that have pervasive standard uses | |
3bbc2af6 | 231 | and are not available for the register allocator. */ |
03984308 BW |
232 | #define FIXED_REGISTERS \ |
233 | { \ | |
234 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
235 | 1, 1, 0, \ | |
236 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
237 | 0, \ | |
238 | } | |
239 | ||
240 | /* 1 for registers not available across function calls. | |
241 | These must include the FIXED_REGISTERS and also any | |
242 | registers that can be used without being saved. | |
243 | The latter must include the registers where values are returned | |
244 | and the register where structure-value addresses are passed. | |
245 | Aside from that, you can include as many other registers as you like. */ | |
246 | #define CALL_USED_REGISTERS \ | |
247 | { \ | |
248 | 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
249 | 1, 1, 1, \ | |
250 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
251 | 1, \ | |
252 | } | |
253 | ||
254 | /* For non-leaf procedures on Xtensa processors, the allocation order | |
255 | is as specified below by REG_ALLOC_ORDER. For leaf procedures, we | |
256 | want to use the lowest numbered registers first to minimize | |
257 | register window overflows. However, local-alloc is not smart | |
258 | enough to consider conflicts with incoming arguments. If an | |
259 | incoming argument in a2 is live throughout the function and | |
260 | local-alloc decides to use a2, then the incoming argument must | |
261 | either be spilled or copied to another register. To get around | |
5a733826 | 262 | this, we define ADJUST_REG_ALLOC_ORDER to redefine |
03984308 BW |
263 | reg_alloc_order for leaf functions such that lowest numbered |
264 | registers are used first with the exception that the incoming | |
265 | argument registers are not used until after other register choices | |
266 | have been exhausted. */ | |
267 | ||
268 | #define REG_ALLOC_ORDER \ | |
985d0d50 BW |
269 | { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \ |
270 | 18, \ | |
271 | 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \ | |
03984308 | 272 | 0, 1, 16, 17, \ |
985d0d50 | 273 | 35, \ |
03984308 BW |
274 | } |
275 | ||
5a733826 | 276 | #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () |
03984308 BW |
277 | |
278 | /* For Xtensa, the only point of this is to prevent GCC from otherwise | |
279 | giving preference to call-used registers. To minimize window | |
280 | overflows for the AR registers, we want to give preference to the | |
281 | lower-numbered AR registers. For other register files, which are | |
3bbc2af6 | 282 | not windowed, we still prefer call-used registers, if there are any. */ |
03984308 BW |
283 | extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER]; |
284 | #define LEAF_REGISTERS xtensa_leaf_regs | |
285 | ||
286 | /* For Xtensa, no remapping is necessary, but this macro must be | |
3bbc2af6 | 287 | defined if LEAF_REGISTERS is defined. */ |
03984308 BW |
288 | #define LEAF_REG_REMAP(REGNO) (REGNO) |
289 | ||
3bbc2af6 | 290 | /* This must be declared if LEAF_REGISTERS is set. */ |
03984308 BW |
291 | extern int leaf_function; |
292 | ||
3bbc2af6 | 293 | /* Internal macros to classify a register number. */ |
03984308 BW |
294 | |
295 | /* 16 address registers + fake registers */ | |
296 | #define GP_REG_FIRST 0 | |
297 | #define GP_REG_LAST 17 | |
298 | #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) | |
299 | ||
03984308 BW |
300 | /* Coprocessor registers */ |
301 | #define BR_REG_FIRST 18 | |
302 | #define BR_REG_LAST 18 | |
303 | #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1) | |
304 | ||
305 | /* 16 floating-point registers */ | |
306 | #define FP_REG_FIRST 19 | |
307 | #define FP_REG_LAST 34 | |
308 | #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) | |
309 | ||
310 | /* MAC16 accumulator */ | |
311 | #define ACC_REG_FIRST 35 | |
312 | #define ACC_REG_LAST 35 | |
313 | #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1) | |
314 | ||
315 | #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM) | |
316 | #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM) | |
317 | #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM) | |
318 | #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM) | |
319 | ||
320 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
321 | to hold something of mode MODE. */ | |
322 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
323 | (FP_REG_P (REGNO) ? \ | |
324 | ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \ | |
325 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
326 | ||
327 | /* Value is 1 if hard register REGNO can hold a value of machine-mode | |
3bbc2af6 | 328 | MODE. */ |
03984308 BW |
329 | extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; |
330 | ||
331 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
332 | xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)] | |
333 | ||
334 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
335 | when one has mode MODE1 and one has mode MODE2. | |
336 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
337 | for any hard reg, then this must be 0 for correct output. */ | |
338 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
339 | ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ | |
340 | GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ | |
341 | == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ | |
342 | GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) | |
343 | ||
03984308 BW |
344 | /* Register to use for pushing function arguments. */ |
345 | #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1) | |
346 | ||
347 | /* Base register for access to local variables of the function. */ | |
348 | #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7) | |
349 | ||
350 | /* The register number of the frame pointer register, which is used to | |
351 | access automatic variables in the stack frame. For Xtensa, this | |
352 | register never appears in the output. It is always eliminated to | |
3bbc2af6 | 353 | either the stack pointer or the hard frame pointer. */ |
03984308 BW |
354 | #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16) |
355 | ||
03984308 BW |
356 | /* Base register for access to arguments of the function. */ |
357 | #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17) | |
358 | ||
03984308 BW |
359 | /* For now we don't try to use the full set of boolean registers. Without |
360 | software pipelining of FP operations, there's not much to gain and it's | |
361 | a real pain to get them reloaded. */ | |
362 | #define FPCC_REGNUM (BR_REG_FIRST + 0) | |
363 | ||
03984308 BW |
364 | /* It is as good or better to call a constant function address than to |
365 | call an address kept in a register. */ | |
366 | #define NO_FUNCTION_CSE 1 | |
367 | ||
03984308 BW |
368 | /* Xtensa processors have "register windows". GCC does not currently |
369 | take advantage of the possibility for variable-sized windows; instead, | |
370 | we use a fixed window size of 8. */ | |
371 | ||
372 | #define INCOMING_REGNO(OUT) \ | |
373 | ((GP_REG_P (OUT) && \ | |
374 | ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \ | |
375 | (OUT) - WINDOW_SIZE : (OUT)) | |
376 | ||
377 | #define OUTGOING_REGNO(IN) \ | |
378 | ((GP_REG_P (IN) && \ | |
379 | ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \ | |
380 | (IN) + WINDOW_SIZE : (IN)) | |
381 | ||
382 | ||
383 | /* Define the classes of registers for register constraints in the | |
384 | machine description. */ | |
385 | enum reg_class | |
386 | { | |
387 | NO_REGS, /* no registers in set */ | |
388 | BR_REGS, /* coprocessor boolean registers */ | |
389 | FP_REGS, /* floating point registers */ | |
390 | ACC_REG, /* MAC16 accumulator */ | |
391 | SP_REG, /* sp register (aka a1) */ | |
89f6025d | 392 | RL_REGS, /* preferred reload regs (not sp or fp) */ |
03984308 BW |
393 | GR_REGS, /* integer registers except sp */ |
394 | AR_REGS, /* all integer registers */ | |
395 | ALL_REGS, /* all registers */ | |
396 | LIM_REG_CLASSES /* max value + 1 */ | |
397 | }; | |
398 | ||
399 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
400 | ||
401 | #define GENERAL_REGS AR_REGS | |
402 | ||
403 | /* An initializer containing the names of the register classes as C | |
404 | string constants. These names are used in writing some of the | |
405 | debugging dumps. */ | |
406 | #define REG_CLASS_NAMES \ | |
407 | { \ | |
408 | "NO_REGS", \ | |
409 | "BR_REGS", \ | |
410 | "FP_REGS", \ | |
411 | "ACC_REG", \ | |
412 | "SP_REG", \ | |
89f6025d | 413 | "RL_REGS", \ |
03984308 BW |
414 | "GR_REGS", \ |
415 | "AR_REGS", \ | |
416 | "ALL_REGS" \ | |
417 | } | |
418 | ||
419 | /* Contents of the register classes. The Nth integer specifies the | |
420 | contents of class N. The way the integer MASK is interpreted is | |
421 | that register R is in the class if 'MASK & (1 << R)' is 1. */ | |
422 | #define REG_CLASS_CONTENTS \ | |
423 | { \ | |
424 | { 0x00000000, 0x00000000 }, /* no registers */ \ | |
425 | { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \ | |
426 | { 0xfff80000, 0x00000007 }, /* floating-point registers */ \ | |
427 | { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \ | |
428 | { 0x00000002, 0x00000000 }, /* stack pointer register */ \ | |
89f6025d | 429 | { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \ |
03984308 BW |
430 | { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \ |
431 | { 0x0003ffff, 0x00000000 }, /* integer registers */ \ | |
432 | { 0xffffffff, 0x0000000f } /* all registers */ \ | |
433 | } | |
434 | ||
435 | /* A C expression whose value is a register class containing hard | |
436 | register REGNO. In general there is more that one such class; | |
437 | choose a class which is "minimal", meaning that no smaller class | |
438 | also contains the register. */ | |
439 | extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER]; | |
440 | ||
441 | #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ] | |
442 | ||
443 | /* Use the Xtensa AR register file for base registers. | |
444 | No index registers. */ | |
445 | #define BASE_REG_CLASS AR_REGS | |
446 | #define INDEX_REG_CLASS NO_REGS | |
447 | ||
42db504c SB |
448 | /* The small_register_classes_for_mode_p hook must always return true for |
449 | Xtrnase, because all of the 16 AR registers may be explicitly used in | |
450 | the RTL, as either incoming or outgoing arguments. */ | |
451 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true | |
03984308 | 452 | |
03984308 BW |
453 | /* Return the maximum number of consecutive registers |
454 | needed to represent mode MODE in a register of class CLASS. */ | |
455 | #define CLASS_UNITS(mode, size) \ | |
456 | ((GET_MODE_SIZE (mode) + (size) - 1) / (size)) | |
457 | ||
458 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
459 | (CLASS_UNITS (MODE, UNITS_PER_WORD)) | |
460 | ||
461 | ||
462 | /* Stack layout; function entry, exit and calling. */ | |
463 | ||
464 | #define STACK_GROWS_DOWNWARD | |
465 | ||
466 | /* Offset within stack frame to start allocating local variables at. */ | |
467 | #define STARTING_FRAME_OFFSET \ | |
38173d38 | 468 | crtl->outgoing_args_size |
03984308 BW |
469 | |
470 | /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so | |
471 | they are eliminated to either the stack pointer or hard frame pointer. */ | |
472 | #define ELIMINABLE_REGS \ | |
473 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
474 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
475 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
476 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
477 | ||
03984308 BW |
478 | /* Specify the initial difference between the specified pair of registers. */ |
479 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
480 | do { \ | |
481 | compute_frame_size (get_frame_size ()); \ | |
177b6be0 NS |
482 | switch (FROM) \ |
483 | { \ | |
484 | case FRAME_POINTER_REGNUM: \ | |
485 | (OFFSET) = 0; \ | |
486 | break; \ | |
487 | case ARG_POINTER_REGNUM: \ | |
488 | (OFFSET) = xtensa_current_frame_size; \ | |
489 | break; \ | |
490 | default: \ | |
491 | gcc_unreachable (); \ | |
492 | } \ | |
03984308 BW |
493 | } while (0) |
494 | ||
495 | /* If defined, the maximum amount of space required for outgoing | |
496 | arguments will be computed and placed into the variable | |
38173d38 | 497 | 'crtl->outgoing_args_size'. No space will be pushed |
03984308 BW |
498 | onto the stack for each call; instead, the function prologue |
499 | should increase the stack frame size by this amount. */ | |
500 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
501 | ||
502 | /* Offset from the argument pointer register to the first argument's | |
503 | address. On some machines it may depend on the data type of the | |
504 | function. If 'ARGS_GROW_DOWNWARD', this is the offset to the | |
505 | location above the first argument's address. */ | |
506 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
507 | ||
508 | /* Align stack frames on 128 bits for Xtensa. This is necessary for | |
509 | 128-bit datatypes defined in TIE (e.g., for Vectra). */ | |
510 | #define STACK_BOUNDARY 128 | |
511 | ||
03984308 BW |
512 | /* Use a fixed register window size of 8. */ |
513 | #define WINDOW_SIZE 8 | |
514 | ||
515 | /* Symbolic macros for the registers used to return integer, floating | |
516 | point, and values of coprocessor and user-defined modes. */ | |
517 | #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE) | |
518 | #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2) | |
519 | ||
520 | /* Symbolic macros for the first/last argument registers. */ | |
521 | #define GP_ARG_FIRST (GP_REG_FIRST + 2) | |
522 | #define GP_ARG_LAST (GP_REG_FIRST + 7) | |
523 | #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE) | |
524 | #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE) | |
525 | ||
526 | #define MAX_ARGS_IN_REGISTERS 6 | |
527 | ||
528 | /* Don't worry about compatibility with PCC. */ | |
529 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
530 | ||
03984308 BW |
531 | /* A C expression that is nonzero if REGNO is the number of a hard |
532 | register in which function arguments are sometimes passed. This | |
533 | does *not* include implicit arguments such as the static chain and | |
534 | the structure-value address. On many machines, no registers can be | |
535 | used for this purpose since all function arguments are pushed on | |
3bbc2af6 | 536 | the stack. */ |
03984308 BW |
537 | #define FUNCTION_ARG_REGNO_P(N) \ |
538 | ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST) | |
539 | ||
997b8b4d BW |
540 | /* Record the number of argument words seen so far, along with a flag to |
541 | indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG | |
542 | is used for both incoming and outgoing args, so a separate flag is | |
543 | needed. */ | |
544 | typedef struct xtensa_args | |
545 | { | |
546 | int arg_words; | |
547 | int incoming; | |
03984308 BW |
548 | } CUMULATIVE_ARGS; |
549 | ||
0f6937fe | 550 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
997b8b4d | 551 | init_cumulative_args (&CUM, 0) |
03984308 BW |
552 | |
553 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ | |
997b8b4d | 554 | init_cumulative_args (&CUM, 1) |
03984308 | 555 | |
5ee924c2 BW |
556 | /* Profiling Xtensa code is typically done with the built-in profiling |
557 | feature of Tensilica's instruction set simulator, which does not | |
558 | require any compiler support. Profiling code on a real (i.e., | |
559 | non-simulated) Xtensa processor is currently only supported by | |
560 | GNU/Linux with glibc. The glibc version of _mcount doesn't require | |
561 | counter variables. The _mcount function needs the current PC and | |
562 | the current return address to identify an arc in the call graph. | |
563 | Pass the current return address as the first argument; the current | |
564 | PC is available as a0 in _mcount's register window. Both of these | |
565 | values contain window size information in the two most significant | |
566 | bits; we assume that _mcount will mask off those bits. The call to | |
567 | _mcount uses a window size of 8 to make sure that it doesn't clobber | |
3bbc2af6 | 568 | any incoming argument values. */ |
03984308 | 569 | |
9739c90c | 570 | #define NO_PROFILE_COUNTERS 1 |
5ee924c2 BW |
571 | |
572 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
03984308 | 573 | do { \ |
5ee924c2 BW |
574 | fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \ |
575 | if (flag_pic) \ | |
576 | { \ | |
577 | fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \ | |
578 | fprintf (FILE, "\tcallx8\ta8\n"); \ | |
579 | } \ | |
580 | else \ | |
581 | fprintf (FILE, "\tcall8\t_mcount\n"); \ | |
582 | } while (0) | |
03984308 BW |
583 | |
584 | /* Stack pointer value doesn't matter at exit. */ | |
585 | #define EXIT_IGNORE_STACK 1 | |
586 | ||
85333688 BW |
587 | /* Size in bytes of the trampoline, as an integer. Make sure this is |
588 | a multiple of TRAMPOLINE_ALIGNMENT to avoid -Wpadded warnings. */ | |
7f0ee694 | 589 | #define TRAMPOLINE_SIZE (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS ? 60 : 52) |
03984308 BW |
590 | |
591 | /* Alignment required for trampolines, in bits. */ | |
7f0ee694 | 592 | #define TRAMPOLINE_ALIGNMENT 32 |
03984308 | 593 | |
03984308 BW |
594 | /* If defined, a C expression that produces the machine-specific code |
595 | to setup the stack so that arbitrary frames can be accessed. | |
596 | ||
597 | On Xtensa, a stack back-trace must always begin from the stack pointer, | |
598 | so that the register overflow save area can be located. However, the | |
599 | stack-walking code in GCC always begins from the hard_frame_pointer | |
600 | register, not the stack pointer. The frame pointer is usually equal | |
601 | to the stack pointer, but the __builtin_return_address and | |
602 | __builtin_frame_address functions will not work if count > 0 and | |
603 | they are called from a routine that uses alloca. These functions | |
604 | are not guaranteed to work at all if count > 0 so maybe that is OK. | |
605 | ||
606 | A nicer solution would be to allow the architecture-specific files to | |
607 | specify whether to start from the stack pointer or frame pointer. That | |
608 | would also allow us to skip the machine->accesses_prev_frame stuff that | |
609 | we currently need to ensure that there is a frame pointer when these | |
3bbc2af6 | 610 | builtin functions are used. */ |
03984308 | 611 | |
0c14a54d | 612 | #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses |
03984308 BW |
613 | |
614 | /* A C expression whose value is RTL representing the address in a | |
615 | stack frame where the pointer to the caller's frame is stored. | |
616 | Assume that FRAMEADDR is an RTL expression for the address of the | |
617 | stack frame itself. | |
618 | ||
619 | For Xtensa, there is no easy way to get the frame pointer if it is | |
620 | not equivalent to the stack pointer. Moreover, the result of this | |
621 | macro is used for continuing to walk back up the stack, so it must | |
622 | return the stack pointer address. Thus, there is some inconsistency | |
623 | here in that __builtin_frame_address will return the frame pointer | |
3bbc2af6 | 624 | when count == 0 and the stack pointer when count > 0. */ |
03984308 BW |
625 | |
626 | #define DYNAMIC_CHAIN_ADDRESS(frame) \ | |
f1c25d3b | 627 | gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD)) |
03984308 BW |
628 | |
629 | /* Define this if the return address of a particular stack frame is | |
3bbc2af6 | 630 | accessed from the frame pointer of the previous stack frame. */ |
03984308 BW |
631 | #define RETURN_ADDR_IN_PREVIOUS_FRAME |
632 | ||
633 | /* A C expression whose value is RTL representing the value of the | |
634 | return address for the frame COUNT steps up from the current | |
0c14a54d BW |
635 | frame, after the prologue. */ |
636 | #define RETURN_ADDR_RTX xtensa_return_addr | |
03984308 BW |
637 | |
638 | /* Addressing modes, and classification of registers for them. */ | |
639 | ||
640 | /* C expressions which are nonzero if register number NUM is suitable | |
da1f39e4 | 641 | for use as a base or index register in operand addresses. */ |
03984308 | 642 | |
da1f39e4 | 643 | #define REGNO_OK_FOR_INDEX_P(NUM) 0 |
03984308 BW |
644 | #define REGNO_OK_FOR_BASE_P(NUM) \ |
645 | (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM])) | |
646 | ||
03984308 | 647 | /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is |
da1f39e4 | 648 | valid for use as a base or index register. */ |
03984308 BW |
649 | |
650 | #ifdef REG_OK_STRICT | |
da1f39e4 BW |
651 | #define REG_OK_STRICT_FLAG 1 |
652 | #else | |
653 | #define REG_OK_STRICT_FLAG 0 | |
654 | #endif | |
03984308 | 655 | |
da1f39e4 BW |
656 | #define BASE_REG_P(X, STRICT) \ |
657 | ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
658 | || REGNO_OK_FOR_BASE_P (REGNO (X))) | |
03984308 BW |
659 | |
660 | #define REG_OK_FOR_INDEX_P(X) 0 | |
da1f39e4 | 661 | #define REG_OK_FOR_BASE_P(X) BASE_REG_P (X, REG_OK_STRICT_FLAG) |
03984308 BW |
662 | |
663 | /* Maximum number of registers that can appear in a valid memory address. */ | |
664 | #define MAX_REGS_PER_ADDRESS 1 | |
665 | ||
03984308 BW |
666 | /* A C expression that is 1 if the RTX X is a constant which is a |
667 | valid address. This is defined to be the same as 'CONSTANT_P (X)', | |
668 | but rejecting CONST_DOUBLE. */ | |
669 | #define CONSTANT_ADDRESS_P(X) \ | |
670 | ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
671 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ | |
672 | || (GET_CODE (X) == CONST))) | |
673 | ||
03984308 BW |
674 | /* A C expression that is nonzero if X is a legitimate immediate |
675 | operand on the target machine when generating position independent | |
676 | code. */ | |
677 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
f1dfe704 BW |
678 | ((GET_CODE (X) != SYMBOL_REF \ |
679 | || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \ | |
03984308 BW |
680 | && GET_CODE (X) != LABEL_REF \ |
681 | && GET_CODE (X) != CONST) | |
682 | ||
03984308 BW |
683 | /* Specify the machine mode that this machine uses |
684 | for the index in the tablejump instruction. */ | |
685 | #define CASE_VECTOR_MODE (SImode) | |
686 | ||
03984308 BW |
687 | /* Define this as 1 if 'char' should by default be signed; else as 0. */ |
688 | #define DEFAULT_SIGNED_CHAR 0 | |
689 | ||
690 | /* Max number of bytes we can move from memory to memory | |
691 | in one reasonably fast instruction. */ | |
692 | #define MOVE_MAX 4 | |
693 | #define MAX_MOVE_MAX 4 | |
694 | ||
695 | /* Prefer word-sized loads. */ | |
696 | #define SLOW_BYTE_ACCESS 1 | |
697 | ||
03984308 BW |
698 | /* Shift instructions ignore all but the low-order few bits. */ |
699 | #define SHIFT_COUNT_TRUNCATED 1 | |
700 | ||
701 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
3bbc2af6 | 702 | is done just by pretending it is already truncated. */ |
03984308 BW |
703 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
704 | ||
09fa8841 BW |
705 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) |
706 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1) | |
707 | ||
03984308 BW |
708 | /* Specify the machine mode that pointers have. |
709 | After generation of rtl, the compiler makes no further distinction | |
710 | between pointers and any other objects of this machine mode. */ | |
711 | #define Pmode SImode | |
712 | ||
713 | /* A function address in a call instruction is a word address (for | |
714 | indexing purposes) so give the MEM rtx a words's mode. */ | |
715 | #define FUNCTION_MODE SImode | |
716 | ||
3a4fd356 | 717 | #define BRANCH_COST(speed_p, predictable_p) 3 |
03984308 | 718 | |
03984308 | 719 | /* How to refer to registers in assembler output. |
3bbc2af6 | 720 | This sequence is indexed by compiler's hard-register-number (see above). */ |
03984308 BW |
721 | #define REGISTER_NAMES \ |
722 | { \ | |
723 | "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \ | |
724 | "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \ | |
725 | "fp", "argp", "b0", \ | |
726 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
727 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ | |
728 | "acc" \ | |
729 | } | |
730 | ||
731 | /* If defined, a C initializer for an array of structures containing a | |
732 | name and a register number. This macro defines additional names | |
733 | for hard registers, thus allowing the 'asm' option in declarations | |
3bbc2af6 | 734 | to refer to registers using alternate names. */ |
03984308 BW |
735 | #define ADDITIONAL_REGISTER_NAMES \ |
736 | { \ | |
737 | { "a1", 1 + GP_REG_FIRST } \ | |
738 | } | |
739 | ||
740 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
741 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
742 | ||
506a61b1 KG |
743 | /* Globalizing directive for a label. */ |
744 | #define GLOBAL_ASM_OP "\t.global\t" | |
03984308 | 745 | |
6a2b287f BW |
746 | /* Declare an uninitialized external linkage data object. */ |
747 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
748 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
03984308 BW |
749 | |
750 | /* This is how to output an element of a case-vector that is absolute. */ | |
751 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ | |
752 | fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \ | |
753 | LOCAL_LABEL_PREFIX, VALUE) | |
754 | ||
755 | /* This is how to output an element of a case-vector that is relative. | |
3bbc2af6 | 756 | This is used for pc-relative code. */ |
03984308 BW |
757 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ |
758 | do { \ | |
759 | fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \ | |
760 | LOCAL_LABEL_PREFIX, (VALUE), \ | |
761 | LOCAL_LABEL_PREFIX, (REL)); \ | |
762 | } while (0) | |
763 | ||
764 | /* This is how to output an assembler line that says to advance the | |
765 | location counter to a multiple of 2**LOG bytes. */ | |
766 | #define ASM_OUTPUT_ALIGN(STREAM, LOG) \ | |
767 | do { \ | |
768 | if ((LOG) != 0) \ | |
769 | fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \ | |
770 | } while (0) | |
771 | ||
772 | /* Indicate that jump tables go in the text section. This is | |
773 | necessary when compiling PIC code. */ | |
774 | #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) | |
775 | ||
776 | ||
03984308 | 777 | /* Define the strings to put out for each section in the object file. */ |
6a2b287f BW |
778 | #define TEXT_SECTION_ASM_OP "\t.text" |
779 | #define DATA_SECTION_ASM_OP "\t.data" | |
780 | #define BSS_SECTION_ASM_OP "\t.section\t.bss" | |
03984308 BW |
781 | |
782 | ||
9eb8a531 | 783 | /* Define output to appear before the constant pool. */ |
03984308 BW |
784 | #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \ |
785 | do { \ | |
958c70ff | 786 | if ((SIZE) > 0) \ |
86d8c251 | 787 | { \ |
9eb8a531 | 788 | resolve_unique_section ((FUNDECL), 0, flag_function_sections); \ |
d6b5193b | 789 | switch_to_section (function_section (FUNDECL)); \ |
86d8c251 BW |
790 | fprintf (FILE, "\t.literal_position\n"); \ |
791 | } \ | |
03984308 BW |
792 | } while (0) |
793 | ||
794 | ||
03984308 BW |
795 | /* A C statement (with or without semicolon) to output a constant in |
796 | the constant pool, if it needs special treatment. */ | |
797 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \ | |
798 | do { \ | |
799 | xtensa_output_literal (FILE, X, MODE, LABELNO); \ | |
800 | goto JUMPTO; \ | |
801 | } while (0) | |
802 | ||
3bbc2af6 | 803 | /* How to start an assembler comment. */ |
03984308 BW |
804 | #define ASM_COMMENT_START "#" |
805 | ||
6eb065e6 SA |
806 | /* Exception handling. Xtensa uses much of the standard DWARF2 unwinding |
807 | machinery, but the variable size register window save areas are too | |
808 | complicated to efficiently describe with CFI entries. The CFA must | |
809 | still be specified in DWARF so that DW_AT_frame_base is set correctly | |
810 | for debugging. */ | |
4e6c2193 BW |
811 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 0) |
812 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (0) | |
6eb065e6 SA |
813 | #define DWARF_FRAME_REGISTERS 16 |
814 | #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + 2 : INVALID_REGNUM) | |
24eaa34f BW |
815 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
816 | (flag_pic \ | |
817 | ? (((GLOBAL) ? DW_EH_PE_indirect : 0) \ | |
818 | | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ | |
819 | : DW_EH_PE_absptr) | |
820 | ||
821 | /* Emit a PC-relative relocation. */ | |
822 | #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ | |
823 | do { \ | |
824 | fputs (integer_asm_op (SIZE, FALSE), FILE); \ | |
825 | assemble_name (FILE, LABEL); \ | |
826 | fputs ("@pcrel", FILE); \ | |
827 | } while (0) | |
03984308 | 828 | |
a7bda3d5 BW |
829 | /* Xtensa constant pool breaks the devices in crtstuff.c to control |
830 | section in where code resides. We have to write it as asm code. Use | |
831 | a MOVI and let the assembler relax it -- for the .init and .fini | |
832 | sections, the assembler knows to put the literal in the right | |
833 | place. */ | |
834 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
835 | asm (SECTION_OP "\n\ | |
836 | movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\ | |
837 | callx8\ta8\n" \ | |
838 | TEXT_SECTION_ASM_OP); |