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03984308 | 1 | /* Definitions of Tensilica's Xtensa target machine for GNU compiler. |
66e58b33 | 2 | Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 |
da1f39e4 | 3 | Free Software Foundation, Inc. |
03984308 BW |
4 | Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it under | |
9 | the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 10 | Software Foundation; either version 3, or (at your option) any later |
03984308 BW |
11 | version. |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
03984308 BW |
21 | |
22 | /* Get Xtensa configuration settings */ | |
e677f70c | 23 | #include "xtensa-config.h" |
03984308 BW |
24 | |
25 | /* Standard GCC variables that we reference. */ | |
03984308 BW |
26 | extern int optimize; |
27 | ||
28 | /* External variables defined in xtensa.c. */ | |
29 | ||
30 | /* comparison type */ | |
31 | enum cmp_type { | |
32 | CMP_SI, /* four byte integers */ | |
33 | CMP_DI, /* eight byte integers */ | |
34 | CMP_SF, /* single precision floats */ | |
35 | CMP_DF, /* double precision floats */ | |
36 | CMP_MAX /* max comparison type */ | |
37 | }; | |
38 | ||
39 | extern struct rtx_def * branch_cmp[2]; /* operands for compare */ | |
40 | extern enum cmp_type branch_type; /* what type of branch to use */ | |
41 | extern unsigned xtensa_current_frame_size; | |
42 | ||
6cedbe44 BW |
43 | /* Macros used in the machine description to select various Xtensa |
44 | configuration options. */ | |
327e3a03 BW |
45 | #ifndef XCHAL_HAVE_MUL32_HIGH |
46 | #define XCHAL_HAVE_MUL32_HIGH 0 | |
47 | #endif | |
2a48b790 BW |
48 | #ifndef XCHAL_HAVE_RELEASE_SYNC |
49 | #define XCHAL_HAVE_RELEASE_SYNC 0 | |
50 | #endif | |
51 | #ifndef XCHAL_HAVE_S32C1I | |
52 | #define XCHAL_HAVE_S32C1I 0 | |
53 | #endif | |
6a7a462c BW |
54 | #ifndef XCHAL_HAVE_THREADPTR |
55 | #define XCHAL_HAVE_THREADPTR 0 | |
56 | #endif | |
6cedbe44 BW |
57 | #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE |
58 | #define TARGET_DENSITY XCHAL_HAVE_DENSITY | |
59 | #define TARGET_MAC16 XCHAL_HAVE_MAC16 | |
60 | #define TARGET_MUL16 XCHAL_HAVE_MUL16 | |
61 | #define TARGET_MUL32 XCHAL_HAVE_MUL32 | |
09fa8841 | 62 | #define TARGET_MUL32_HIGH XCHAL_HAVE_MUL32_HIGH |
6cedbe44 BW |
63 | #define TARGET_DIV32 XCHAL_HAVE_DIV32 |
64 | #define TARGET_NSA XCHAL_HAVE_NSA | |
65 | #define TARGET_MINMAX XCHAL_HAVE_MINMAX | |
66 | #define TARGET_SEXT XCHAL_HAVE_SEXT | |
67 | #define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS | |
68 | #define TARGET_HARD_FLOAT XCHAL_HAVE_FP | |
69 | #define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV | |
70 | #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP | |
71 | #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT | |
72 | #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT | |
73 | #define TARGET_ABS XCHAL_HAVE_ABS | |
74 | #define TARGET_ADDX XCHAL_HAVE_ADDX | |
2a48b790 BW |
75 | #define TARGET_RELEASE_SYNC XCHAL_HAVE_RELEASE_SYNC |
76 | #define TARGET_S32C1I XCHAL_HAVE_S32C1I | |
7f0ee694 | 77 | #define TARGET_ABSOLUTE_LITERALS XSHAL_USE_ABSOLUTE_LITERALS |
6a7a462c | 78 | #define TARGET_THREADPTR XCHAL_HAVE_THREADPTR |
6cedbe44 | 79 | |
66e58b33 BW |
80 | #define TARGET_DEFAULT \ |
81 | ((XCHAL_HAVE_L32R ? 0 : MASK_CONST16) | \ | |
82 | MASK_SERIALIZE_VOLATILE) | |
03984308 | 83 | |
6a7a462c BW |
84 | #ifndef HAVE_AS_TLS |
85 | #define HAVE_AS_TLS 0 | |
86 | #endif | |
87 | ||
03984308 | 88 | #define OVERRIDE_OPTIONS override_options () |
528a7d22 BW |
89 | |
90 | /* Reordering blocks for Xtensa is not a good idea unless the compiler | |
91 | understands the range of conditional branches. Currently all branch | |
92 | relaxation for Xtensa is handled in the assembler, so GCC cannot do a | |
93 | good job of reordering blocks. Do not enable reordering unless it is | |
94 | explicitly requested. */ | |
95 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ | |
96 | do \ | |
97 | { \ | |
98 | flag_reorder_blocks = 0; \ | |
99 | } \ | |
100 | while (0) | |
101 | ||
624f0d60 BW |
102 | \f |
103 | /* Target CPU builtins. */ | |
104 | #define TARGET_CPU_CPP_BUILTINS() \ | |
105 | do { \ | |
106 | builtin_assert ("cpu=xtensa"); \ | |
107 | builtin_assert ("machine=xtensa"); \ | |
48c0150c | 108 | builtin_define ("__xtensa__"); \ |
624f0d60 | 109 | builtin_define ("__XTENSA__"); \ |
c0b57a5a | 110 | builtin_define ("__XTENSA_WINDOWED_ABI__"); \ |
624f0d60 BW |
111 | builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \ |
112 | if (!TARGET_HARD_FLOAT) \ | |
113 | builtin_define ("__XTENSA_SOFT_FLOAT__"); \ | |
624f0d60 | 114 | } while (0) |
03984308 | 115 | |
6a2b287f BW |
116 | #define CPP_SPEC " %(subtarget_cpp_spec) " |
117 | ||
118 | #ifndef SUBTARGET_CPP_SPEC | |
119 | #define SUBTARGET_CPP_SPEC "" | |
120 | #endif | |
121 | ||
ab409f1b | 122 | #define EXTRA_SPECS \ |
6a2b287f BW |
123 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, |
124 | ||
01e4596e BW |
125 | #ifdef __XTENSA_EB__ |
126 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
127 | #else | |
128 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
129 | #endif | |
03984308 BW |
130 | |
131 | /* Show we can debug even without a frame pointer. */ | |
132 | #define CAN_DEBUG_WITHOUT_FP | |
133 | ||
134 | ||
135 | /* Target machine storage layout */ | |
136 | ||
03984308 BW |
137 | /* Define this if most significant bit is lowest numbered |
138 | in instructions that operate on numbered bit-fields. */ | |
139 | #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) | |
140 | ||
3bbc2af6 | 141 | /* Define this if most significant byte of a word is the lowest numbered. */ |
03984308 BW |
142 | #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) |
143 | ||
3bbc2af6 | 144 | /* Define this if most significant word of a multiword number is the lowest. */ |
03984308 BW |
145 | #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) |
146 | ||
03984308 BW |
147 | #define MAX_BITS_PER_WORD 32 |
148 | ||
149 | /* Width of a word, in units (bytes). */ | |
150 | #define UNITS_PER_WORD 4 | |
151 | #define MIN_UNITS_PER_WORD 4 | |
152 | ||
153 | /* Width of a floating point register. */ | |
154 | #define UNITS_PER_FPREG 4 | |
155 | ||
156 | /* Size in bits of various types on the target machine. */ | |
157 | #define INT_TYPE_SIZE 32 | |
03984308 BW |
158 | #define SHORT_TYPE_SIZE 16 |
159 | #define LONG_TYPE_SIZE 32 | |
03984308 | 160 | #define LONG_LONG_TYPE_SIZE 64 |
03984308 BW |
161 | #define FLOAT_TYPE_SIZE 32 |
162 | #define DOUBLE_TYPE_SIZE 64 | |
163 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
03984308 | 164 | |
03984308 BW |
165 | /* Allocation boundary (in *bits*) for storing pointers in memory. */ |
166 | #define POINTER_BOUNDARY 32 | |
167 | ||
168 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
169 | #define PARM_BOUNDARY 32 | |
170 | ||
171 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
172 | #define FUNCTION_BOUNDARY 32 | |
173 | ||
174 | /* Alignment of field after 'int : 0' in a structure. */ | |
175 | #define EMPTY_FIELD_BOUNDARY 32 | |
176 | ||
177 | /* Every structure's size must be a multiple of this. */ | |
178 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
179 | ||
180 | /* There is no point aligning anything to a rounder boundary than this. */ | |
181 | #define BIGGEST_ALIGNMENT 128 | |
182 | ||
183 | /* Set this nonzero if move instructions will actually fail to work | |
184 | when given unaligned data. */ | |
185 | #define STRICT_ALIGNMENT 1 | |
186 | ||
187 | /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP | |
188 | for QImode, because there is no 8-bit load from memory with sign | |
189 | extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit | |
190 | loads both with and without sign extension. */ | |
191 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
192 | do { \ | |
193 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
194 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
195 | { \ | |
196 | if ((MODE) == QImode) \ | |
197 | (UNSIGNEDP) = 1; \ | |
198 | (MODE) = SImode; \ | |
199 | } \ | |
200 | } while (0) | |
201 | ||
03984308 BW |
202 | /* Imitate the way many other C compilers handle alignment of |
203 | bitfields and the structures that contain them. */ | |
204 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
205 | ||
9a7363b9 BW |
206 | /* Disable the use of word-sized or smaller complex modes for structures, |
207 | and for function arguments in particular, where they cause problems with | |
208 | register a7. The xtensa_copy_incoming_a7 function assumes that there is | |
209 | a single reference to an argument in a7, but with small complex modes the | |
210 | real and imaginary components may be extracted separately, leading to two | |
211 | uses of the register, only one of which would be replaced. */ | |
212 | #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \ | |
213 | ((MODE) == CQImode || (MODE) == CHImode) | |
214 | ||
03984308 BW |
215 | /* Align string constants and constructors to at least a word boundary. |
216 | The typical use of this macro is to increase alignment for string | |
217 | constants to be word aligned so that 'strcpy' calls that copy | |
218 | constants can be done inline. */ | |
219 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
220 | ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ | |
221 | && (ALIGN) < BITS_PER_WORD \ | |
222 | ? BITS_PER_WORD \ | |
223 | : (ALIGN)) | |
224 | ||
225 | /* Align arrays, unions and records to at least a word boundary. | |
226 | One use of this macro is to increase alignment of medium-size | |
227 | data to make it all fit in fewer cache lines. Another is to | |
228 | cause character arrays to be word-aligned so that 'strcpy' calls | |
229 | that copy constants to character arrays can be done inline. */ | |
230 | #undef DATA_ALIGNMENT | |
231 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
232 | ((((ALIGN) < BITS_PER_WORD) \ | |
233 | && (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
234 | || TREE_CODE (TYPE) == UNION_TYPE \ | |
235 | || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
236 | ||
03984308 BW |
237 | /* Operations between registers always perform the operation |
238 | on the full register even if a narrower mode is specified. */ | |
239 | #define WORD_REGISTER_OPERATIONS | |
240 | ||
241 | /* Xtensa loads are zero-extended by default. */ | |
242 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
243 | ||
244 | /* Standard register usage. */ | |
245 | ||
246 | /* Number of actual hardware registers. | |
247 | The hardware registers are assigned numbers for the compiler | |
248 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
249 | All registers that the compiler knows about must be given numbers, | |
250 | even those that are not normally considered general registers. | |
251 | ||
252 | The fake frame pointer and argument pointer will never appear in | |
253 | the generated code, since they will always be eliminated and replaced | |
254 | by either the stack pointer or the hard frame pointer. | |
255 | ||
256 | 0 - 15 AR[0] - AR[15] | |
257 | 16 FRAME_POINTER (fake = initial sp) | |
258 | 17 ARG_POINTER (fake = initial sp + framesize) | |
03984308 BW |
259 | 18 BR[0] for floating-point CC |
260 | 19 - 34 FR[0] - FR[15] | |
261 | 35 MAC16 accumulator */ | |
262 | ||
263 | #define FIRST_PSEUDO_REGISTER 36 | |
264 | ||
3bbc2af6 | 265 | /* Return the stabs register number to use for REGNO. */ |
03984308 BW |
266 | #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO) |
267 | ||
268 | /* 1 for registers that have pervasive standard uses | |
3bbc2af6 | 269 | and are not available for the register allocator. */ |
03984308 BW |
270 | #define FIXED_REGISTERS \ |
271 | { \ | |
272 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
273 | 1, 1, 0, \ | |
274 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
275 | 0, \ | |
276 | } | |
277 | ||
278 | /* 1 for registers not available across function calls. | |
279 | These must include the FIXED_REGISTERS and also any | |
280 | registers that can be used without being saved. | |
281 | The latter must include the registers where values are returned | |
282 | and the register where structure-value addresses are passed. | |
283 | Aside from that, you can include as many other registers as you like. */ | |
284 | #define CALL_USED_REGISTERS \ | |
285 | { \ | |
286 | 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
287 | 1, 1, 1, \ | |
288 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
289 | 1, \ | |
290 | } | |
291 | ||
292 | /* For non-leaf procedures on Xtensa processors, the allocation order | |
293 | is as specified below by REG_ALLOC_ORDER. For leaf procedures, we | |
294 | want to use the lowest numbered registers first to minimize | |
295 | register window overflows. However, local-alloc is not smart | |
296 | enough to consider conflicts with incoming arguments. If an | |
297 | incoming argument in a2 is live throughout the function and | |
298 | local-alloc decides to use a2, then the incoming argument must | |
299 | either be spilled or copied to another register. To get around | |
300 | this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine | |
301 | reg_alloc_order for leaf functions such that lowest numbered | |
302 | registers are used first with the exception that the incoming | |
303 | argument registers are not used until after other register choices | |
304 | have been exhausted. */ | |
305 | ||
306 | #define REG_ALLOC_ORDER \ | |
985d0d50 BW |
307 | { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \ |
308 | 18, \ | |
309 | 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \ | |
03984308 | 310 | 0, 1, 16, 17, \ |
985d0d50 | 311 | 35, \ |
03984308 BW |
312 | } |
313 | ||
314 | #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () | |
315 | ||
316 | /* For Xtensa, the only point of this is to prevent GCC from otherwise | |
317 | giving preference to call-used registers. To minimize window | |
318 | overflows for the AR registers, we want to give preference to the | |
319 | lower-numbered AR registers. For other register files, which are | |
3bbc2af6 | 320 | not windowed, we still prefer call-used registers, if there are any. */ |
03984308 BW |
321 | extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER]; |
322 | #define LEAF_REGISTERS xtensa_leaf_regs | |
323 | ||
324 | /* For Xtensa, no remapping is necessary, but this macro must be | |
3bbc2af6 | 325 | defined if LEAF_REGISTERS is defined. */ |
03984308 BW |
326 | #define LEAF_REG_REMAP(REGNO) (REGNO) |
327 | ||
3bbc2af6 | 328 | /* This must be declared if LEAF_REGISTERS is set. */ |
03984308 BW |
329 | extern int leaf_function; |
330 | ||
3bbc2af6 | 331 | /* Internal macros to classify a register number. */ |
03984308 BW |
332 | |
333 | /* 16 address registers + fake registers */ | |
334 | #define GP_REG_FIRST 0 | |
335 | #define GP_REG_LAST 17 | |
336 | #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) | |
337 | ||
03984308 BW |
338 | /* Coprocessor registers */ |
339 | #define BR_REG_FIRST 18 | |
340 | #define BR_REG_LAST 18 | |
341 | #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1) | |
342 | ||
343 | /* 16 floating-point registers */ | |
344 | #define FP_REG_FIRST 19 | |
345 | #define FP_REG_LAST 34 | |
346 | #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) | |
347 | ||
348 | /* MAC16 accumulator */ | |
349 | #define ACC_REG_FIRST 35 | |
350 | #define ACC_REG_LAST 35 | |
351 | #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1) | |
352 | ||
353 | #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM) | |
354 | #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM) | |
355 | #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM) | |
356 | #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM) | |
357 | ||
358 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
359 | to hold something of mode MODE. */ | |
360 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
361 | (FP_REG_P (REGNO) ? \ | |
362 | ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \ | |
363 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
364 | ||
365 | /* Value is 1 if hard register REGNO can hold a value of machine-mode | |
3bbc2af6 | 366 | MODE. */ |
03984308 BW |
367 | extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; |
368 | ||
369 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
370 | xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)] | |
371 | ||
372 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
373 | when one has mode MODE1 and one has mode MODE2. | |
374 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
375 | for any hard reg, then this must be 0 for correct output. */ | |
376 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
377 | ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ | |
378 | GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ | |
379 | == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ | |
380 | GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) | |
381 | ||
03984308 BW |
382 | /* Register to use for pushing function arguments. */ |
383 | #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1) | |
384 | ||
385 | /* Base register for access to local variables of the function. */ | |
386 | #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7) | |
387 | ||
388 | /* The register number of the frame pointer register, which is used to | |
389 | access automatic variables in the stack frame. For Xtensa, this | |
390 | register never appears in the output. It is always eliminated to | |
3bbc2af6 | 391 | either the stack pointer or the hard frame pointer. */ |
03984308 BW |
392 | #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16) |
393 | ||
394 | /* Value should be nonzero if functions must have frame pointers. | |
395 | Zero means the frame pointer need not be set up (and parms | |
396 | may be accessed via the stack pointer) in functions that seem suitable. | |
397 | This is computed in 'reload', in reload1.c. */ | |
398 | #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required () | |
399 | ||
400 | /* Base register for access to arguments of the function. */ | |
401 | #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17) | |
402 | ||
403 | /* If the static chain is passed in memory, these macros provide rtx | |
404 | giving 'mem' expressions that denote where they are stored. | |
405 | 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as | |
406 | seen by the calling and called functions, respectively. */ | |
407 | ||
408 | #define STATIC_CHAIN \ | |
409 | gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD)) | |
410 | ||
411 | #define STATIC_CHAIN_INCOMING \ | |
412 | gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD)) | |
413 | ||
414 | /* For now we don't try to use the full set of boolean registers. Without | |
415 | software pipelining of FP operations, there's not much to gain and it's | |
416 | a real pain to get them reloaded. */ | |
417 | #define FPCC_REGNUM (BR_REG_FIRST + 0) | |
418 | ||
03984308 BW |
419 | /* It is as good or better to call a constant function address than to |
420 | call an address kept in a register. */ | |
421 | #define NO_FUNCTION_CSE 1 | |
422 | ||
03984308 BW |
423 | /* Xtensa processors have "register windows". GCC does not currently |
424 | take advantage of the possibility for variable-sized windows; instead, | |
425 | we use a fixed window size of 8. */ | |
426 | ||
427 | #define INCOMING_REGNO(OUT) \ | |
428 | ((GP_REG_P (OUT) && \ | |
429 | ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \ | |
430 | (OUT) - WINDOW_SIZE : (OUT)) | |
431 | ||
432 | #define OUTGOING_REGNO(IN) \ | |
433 | ((GP_REG_P (IN) && \ | |
434 | ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \ | |
435 | (IN) + WINDOW_SIZE : (IN)) | |
436 | ||
437 | ||
438 | /* Define the classes of registers for register constraints in the | |
439 | machine description. */ | |
440 | enum reg_class | |
441 | { | |
442 | NO_REGS, /* no registers in set */ | |
443 | BR_REGS, /* coprocessor boolean registers */ | |
444 | FP_REGS, /* floating point registers */ | |
445 | ACC_REG, /* MAC16 accumulator */ | |
446 | SP_REG, /* sp register (aka a1) */ | |
89f6025d | 447 | RL_REGS, /* preferred reload regs (not sp or fp) */ |
03984308 BW |
448 | GR_REGS, /* integer registers except sp */ |
449 | AR_REGS, /* all integer registers */ | |
450 | ALL_REGS, /* all registers */ | |
451 | LIM_REG_CLASSES /* max value + 1 */ | |
452 | }; | |
453 | ||
454 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
455 | ||
456 | #define GENERAL_REGS AR_REGS | |
457 | ||
458 | /* An initializer containing the names of the register classes as C | |
459 | string constants. These names are used in writing some of the | |
460 | debugging dumps. */ | |
461 | #define REG_CLASS_NAMES \ | |
462 | { \ | |
463 | "NO_REGS", \ | |
464 | "BR_REGS", \ | |
465 | "FP_REGS", \ | |
466 | "ACC_REG", \ | |
467 | "SP_REG", \ | |
89f6025d | 468 | "RL_REGS", \ |
03984308 BW |
469 | "GR_REGS", \ |
470 | "AR_REGS", \ | |
471 | "ALL_REGS" \ | |
472 | } | |
473 | ||
474 | /* Contents of the register classes. The Nth integer specifies the | |
475 | contents of class N. The way the integer MASK is interpreted is | |
476 | that register R is in the class if 'MASK & (1 << R)' is 1. */ | |
477 | #define REG_CLASS_CONTENTS \ | |
478 | { \ | |
479 | { 0x00000000, 0x00000000 }, /* no registers */ \ | |
480 | { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \ | |
481 | { 0xfff80000, 0x00000007 }, /* floating-point registers */ \ | |
482 | { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \ | |
483 | { 0x00000002, 0x00000000 }, /* stack pointer register */ \ | |
89f6025d | 484 | { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \ |
03984308 BW |
485 | { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \ |
486 | { 0x0003ffff, 0x00000000 }, /* integer registers */ \ | |
487 | { 0xffffffff, 0x0000000f } /* all registers */ \ | |
488 | } | |
489 | ||
a1f626ad BW |
490 | #define IRA_COVER_CLASSES \ |
491 | { \ | |
492 | BR_REGS, FP_REGS, ACC_REG, AR_REGS, LIM_REG_CLASSES \ | |
493 | } | |
494 | ||
03984308 BW |
495 | /* A C expression whose value is a register class containing hard |
496 | register REGNO. In general there is more that one such class; | |
497 | choose a class which is "minimal", meaning that no smaller class | |
498 | also contains the register. */ | |
499 | extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER]; | |
500 | ||
501 | #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ] | |
502 | ||
503 | /* Use the Xtensa AR register file for base registers. | |
504 | No index registers. */ | |
505 | #define BASE_REG_CLASS AR_REGS | |
506 | #define INDEX_REG_CLASS NO_REGS | |
507 | ||
508 | /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the | |
509 | 16 AR registers may be explicitly used in the RTL, as either | |
3bbc2af6 | 510 | incoming or outgoing arguments. */ |
03984308 BW |
511 | #define SMALL_REGISTER_CLASSES 1 |
512 | ||
03984308 | 513 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ |
89f6025d | 514 | xtensa_preferred_reload_class (X, CLASS, 0) |
03984308 BW |
515 | |
516 | #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ | |
89f6025d | 517 | xtensa_preferred_reload_class (X, CLASS, 1) |
03984308 | 518 | |
03984308 BW |
519 | /* Return the maximum number of consecutive registers |
520 | needed to represent mode MODE in a register of class CLASS. */ | |
521 | #define CLASS_UNITS(mode, size) \ | |
522 | ((GET_MODE_SIZE (mode) + (size) - 1) / (size)) | |
523 | ||
524 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
525 | (CLASS_UNITS (MODE, UNITS_PER_WORD)) | |
526 | ||
527 | ||
528 | /* Stack layout; function entry, exit and calling. */ | |
529 | ||
530 | #define STACK_GROWS_DOWNWARD | |
531 | ||
532 | /* Offset within stack frame to start allocating local variables at. */ | |
533 | #define STARTING_FRAME_OFFSET \ | |
38173d38 | 534 | crtl->outgoing_args_size |
03984308 BW |
535 | |
536 | /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so | |
537 | they are eliminated to either the stack pointer or hard frame pointer. */ | |
538 | #define ELIMINABLE_REGS \ | |
539 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
540 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
541 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
542 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
543 | ||
544 | #define CAN_ELIMINATE(FROM, TO) 1 | |
545 | ||
546 | /* Specify the initial difference between the specified pair of registers. */ | |
547 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
548 | do { \ | |
549 | compute_frame_size (get_frame_size ()); \ | |
177b6be0 NS |
550 | switch (FROM) \ |
551 | { \ | |
552 | case FRAME_POINTER_REGNUM: \ | |
553 | (OFFSET) = 0; \ | |
554 | break; \ | |
555 | case ARG_POINTER_REGNUM: \ | |
556 | (OFFSET) = xtensa_current_frame_size; \ | |
557 | break; \ | |
558 | default: \ | |
559 | gcc_unreachable (); \ | |
560 | } \ | |
03984308 BW |
561 | } while (0) |
562 | ||
563 | /* If defined, the maximum amount of space required for outgoing | |
564 | arguments will be computed and placed into the variable | |
38173d38 | 565 | 'crtl->outgoing_args_size'. No space will be pushed |
03984308 BW |
566 | onto the stack for each call; instead, the function prologue |
567 | should increase the stack frame size by this amount. */ | |
568 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
569 | ||
570 | /* Offset from the argument pointer register to the first argument's | |
571 | address. On some machines it may depend on the data type of the | |
572 | function. If 'ARGS_GROW_DOWNWARD', this is the offset to the | |
573 | location above the first argument's address. */ | |
574 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
575 | ||
576 | /* Align stack frames on 128 bits for Xtensa. This is necessary for | |
577 | 128-bit datatypes defined in TIE (e.g., for Vectra). */ | |
578 | #define STACK_BOUNDARY 128 | |
579 | ||
580 | /* Functions do not pop arguments off the stack. */ | |
581 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 | |
582 | ||
583 | /* Use a fixed register window size of 8. */ | |
584 | #define WINDOW_SIZE 8 | |
585 | ||
586 | /* Symbolic macros for the registers used to return integer, floating | |
587 | point, and values of coprocessor and user-defined modes. */ | |
588 | #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE) | |
589 | #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2) | |
590 | ||
591 | /* Symbolic macros for the first/last argument registers. */ | |
592 | #define GP_ARG_FIRST (GP_REG_FIRST + 2) | |
593 | #define GP_ARG_LAST (GP_REG_FIRST + 7) | |
594 | #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE) | |
595 | #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE) | |
596 | ||
597 | #define MAX_ARGS_IN_REGISTERS 6 | |
598 | ||
599 | /* Don't worry about compatibility with PCC. */ | |
600 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
601 | ||
03984308 BW |
602 | /* Define how to find the value returned by a library function |
603 | assuming the value has mode MODE. Because we have defined | |
4c45af42 KH |
604 | TARGET_PROMOTE_FUNCTION_RETURN that returns true, we have to |
605 | perform the same promotions as PROMOTE_MODE. */ | |
03984308 BW |
606 | #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \ |
607 | gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \ | |
608 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
609 | ? SImode : (MODE), \ | |
610 | OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN) | |
611 | ||
612 | #define LIBCALL_VALUE(MODE) \ | |
613 | XTENSA_LIBCALL_VALUE ((MODE), 0) | |
614 | ||
615 | #define LIBCALL_OUTGOING_VALUE(MODE) \ | |
616 | XTENSA_LIBCALL_VALUE ((MODE), 1) | |
617 | ||
03984308 BW |
618 | /* A C expression that is nonzero if REGNO is the number of a hard |
619 | register in which the values of called function may come back. A | |
620 | register whose use for returning values is limited to serving as | |
621 | the second of a pair (for a value of type 'double', say) need not | |
622 | be recognized by this macro. If the machine has register windows, | |
623 | so that the caller and the called function use different registers | |
624 | for the return value, this macro should recognize only the caller's | |
3bbc2af6 | 625 | register numbers. */ |
03984308 BW |
626 | #define FUNCTION_VALUE_REGNO_P(N) \ |
627 | ((N) == GP_RETURN) | |
628 | ||
629 | /* A C expression that is nonzero if REGNO is the number of a hard | |
630 | register in which function arguments are sometimes passed. This | |
631 | does *not* include implicit arguments such as the static chain and | |
632 | the structure-value address. On many machines, no registers can be | |
633 | used for this purpose since all function arguments are pushed on | |
3bbc2af6 | 634 | the stack. */ |
03984308 BW |
635 | #define FUNCTION_ARG_REGNO_P(N) \ |
636 | ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST) | |
637 | ||
997b8b4d BW |
638 | /* Record the number of argument words seen so far, along with a flag to |
639 | indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG | |
640 | is used for both incoming and outgoing args, so a separate flag is | |
641 | needed. */ | |
642 | typedef struct xtensa_args | |
643 | { | |
644 | int arg_words; | |
645 | int incoming; | |
03984308 BW |
646 | } CUMULATIVE_ARGS; |
647 | ||
0f6937fe | 648 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
997b8b4d | 649 | init_cumulative_args (&CUM, 0) |
03984308 BW |
650 | |
651 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ | |
997b8b4d | 652 | init_cumulative_args (&CUM, 1) |
03984308 BW |
653 | |
654 | /* Update the data in CUM to advance over an argument | |
655 | of mode MODE and data type TYPE. | |
656 | (TYPE is null for libcalls where that information may not be available.) */ | |
657 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
658 | function_arg_advance (&CUM, MODE, TYPE) | |
659 | ||
660 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
661 | function_arg (&CUM, MODE, TYPE, FALSE) | |
662 | ||
663 | #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ | |
664 | function_arg (&CUM, MODE, TYPE, TRUE) | |
665 | ||
d2348985 | 666 | #define FUNCTION_ARG_BOUNDARY function_arg_boundary |
03984308 | 667 | |
5ee924c2 BW |
668 | /* Profiling Xtensa code is typically done with the built-in profiling |
669 | feature of Tensilica's instruction set simulator, which does not | |
670 | require any compiler support. Profiling code on a real (i.e., | |
671 | non-simulated) Xtensa processor is currently only supported by | |
672 | GNU/Linux with glibc. The glibc version of _mcount doesn't require | |
673 | counter variables. The _mcount function needs the current PC and | |
674 | the current return address to identify an arc in the call graph. | |
675 | Pass the current return address as the first argument; the current | |
676 | PC is available as a0 in _mcount's register window. Both of these | |
677 | values contain window size information in the two most significant | |
678 | bits; we assume that _mcount will mask off those bits. The call to | |
679 | _mcount uses a window size of 8 to make sure that it doesn't clobber | |
3bbc2af6 | 680 | any incoming argument values. */ |
03984308 | 681 | |
9739c90c | 682 | #define NO_PROFILE_COUNTERS 1 |
5ee924c2 BW |
683 | |
684 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
03984308 | 685 | do { \ |
5ee924c2 BW |
686 | fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \ |
687 | if (flag_pic) \ | |
688 | { \ | |
689 | fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \ | |
690 | fprintf (FILE, "\tcallx8\ta8\n"); \ | |
691 | } \ | |
692 | else \ | |
693 | fprintf (FILE, "\tcall8\t_mcount\n"); \ | |
694 | } while (0) | |
03984308 BW |
695 | |
696 | /* Stack pointer value doesn't matter at exit. */ | |
697 | #define EXIT_IGNORE_STACK 1 | |
698 | ||
7f0ee694 | 699 | #define TRAMPOLINE_TEMPLATE(STREAM) xtensa_trampoline_template (STREAM) |
03984308 | 700 | |
85333688 BW |
701 | /* Size in bytes of the trampoline, as an integer. Make sure this is |
702 | a multiple of TRAMPOLINE_ALIGNMENT to avoid -Wpadded warnings. */ | |
7f0ee694 | 703 | #define TRAMPOLINE_SIZE (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS ? 60 : 52) |
03984308 BW |
704 | |
705 | /* Alignment required for trampolines, in bits. */ | |
7f0ee694 | 706 | #define TRAMPOLINE_ALIGNMENT 32 |
03984308 BW |
707 | |
708 | /* A C statement to initialize the variable parts of a trampoline. */ | |
709 | #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \ | |
7f0ee694 BW |
710 | xtensa_initialize_trampoline (ADDR, FUNC, CHAIN) |
711 | ||
03984308 | 712 | |
03984308 BW |
713 | /* If defined, a C expression that produces the machine-specific code |
714 | to setup the stack so that arbitrary frames can be accessed. | |
715 | ||
716 | On Xtensa, a stack back-trace must always begin from the stack pointer, | |
717 | so that the register overflow save area can be located. However, the | |
718 | stack-walking code in GCC always begins from the hard_frame_pointer | |
719 | register, not the stack pointer. The frame pointer is usually equal | |
720 | to the stack pointer, but the __builtin_return_address and | |
721 | __builtin_frame_address functions will not work if count > 0 and | |
722 | they are called from a routine that uses alloca. These functions | |
723 | are not guaranteed to work at all if count > 0 so maybe that is OK. | |
724 | ||
725 | A nicer solution would be to allow the architecture-specific files to | |
726 | specify whether to start from the stack pointer or frame pointer. That | |
727 | would also allow us to skip the machine->accesses_prev_frame stuff that | |
728 | we currently need to ensure that there is a frame pointer when these | |
3bbc2af6 | 729 | builtin functions are used. */ |
03984308 | 730 | |
0c14a54d | 731 | #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses |
03984308 BW |
732 | |
733 | /* A C expression whose value is RTL representing the address in a | |
734 | stack frame where the pointer to the caller's frame is stored. | |
735 | Assume that FRAMEADDR is an RTL expression for the address of the | |
736 | stack frame itself. | |
737 | ||
738 | For Xtensa, there is no easy way to get the frame pointer if it is | |
739 | not equivalent to the stack pointer. Moreover, the result of this | |
740 | macro is used for continuing to walk back up the stack, so it must | |
741 | return the stack pointer address. Thus, there is some inconsistency | |
742 | here in that __builtin_frame_address will return the frame pointer | |
3bbc2af6 | 743 | when count == 0 and the stack pointer when count > 0. */ |
03984308 BW |
744 | |
745 | #define DYNAMIC_CHAIN_ADDRESS(frame) \ | |
f1c25d3b | 746 | gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD)) |
03984308 BW |
747 | |
748 | /* Define this if the return address of a particular stack frame is | |
3bbc2af6 | 749 | accessed from the frame pointer of the previous stack frame. */ |
03984308 BW |
750 | #define RETURN_ADDR_IN_PREVIOUS_FRAME |
751 | ||
752 | /* A C expression whose value is RTL representing the value of the | |
753 | return address for the frame COUNT steps up from the current | |
0c14a54d BW |
754 | frame, after the prologue. */ |
755 | #define RETURN_ADDR_RTX xtensa_return_addr | |
03984308 BW |
756 | |
757 | /* Addressing modes, and classification of registers for them. */ | |
758 | ||
759 | /* C expressions which are nonzero if register number NUM is suitable | |
da1f39e4 | 760 | for use as a base or index register in operand addresses. */ |
03984308 | 761 | |
da1f39e4 | 762 | #define REGNO_OK_FOR_INDEX_P(NUM) 0 |
03984308 BW |
763 | #define REGNO_OK_FOR_BASE_P(NUM) \ |
764 | (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM])) | |
765 | ||
03984308 | 766 | /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is |
da1f39e4 | 767 | valid for use as a base or index register. */ |
03984308 BW |
768 | |
769 | #ifdef REG_OK_STRICT | |
da1f39e4 BW |
770 | #define REG_OK_STRICT_FLAG 1 |
771 | #else | |
772 | #define REG_OK_STRICT_FLAG 0 | |
773 | #endif | |
03984308 | 774 | |
da1f39e4 BW |
775 | #define BASE_REG_P(X, STRICT) \ |
776 | ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
777 | || REGNO_OK_FOR_BASE_P (REGNO (X))) | |
03984308 BW |
778 | |
779 | #define REG_OK_FOR_INDEX_P(X) 0 | |
da1f39e4 | 780 | #define REG_OK_FOR_BASE_P(X) BASE_REG_P (X, REG_OK_STRICT_FLAG) |
03984308 BW |
781 | |
782 | /* Maximum number of registers that can appear in a valid memory address. */ | |
783 | #define MAX_REGS_PER_ADDRESS 1 | |
784 | ||
785 | /* Identify valid Xtensa addresses. */ | |
eb8e00ea | 786 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, ADDR, LABEL) \ |
03984308 | 787 | do { \ |
da1f39e4 | 788 | if (xtensa_legitimate_address_p (MODE, ADDR, REG_OK_STRICT_FLAG)) \ |
eb8e00ea | 789 | goto LABEL; \ |
03984308 BW |
790 | } while (0) |
791 | ||
792 | /* A C expression that is 1 if the RTX X is a constant which is a | |
793 | valid address. This is defined to be the same as 'CONSTANT_P (X)', | |
794 | but rejecting CONST_DOUBLE. */ | |
795 | #define CONSTANT_ADDRESS_P(X) \ | |
796 | ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
797 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ | |
798 | || (GET_CODE (X) == CONST))) | |
799 | ||
800 | /* Nonzero if the constant value X is a legitimate general operand. | |
3bbc2af6 | 801 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
6a7a462c | 802 | #define LEGITIMATE_CONSTANT_P(X) (! xtensa_tls_referenced_p (X)) |
03984308 BW |
803 | |
804 | /* A C expression that is nonzero if X is a legitimate immediate | |
805 | operand on the target machine when generating position independent | |
806 | code. */ | |
807 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
f1dfe704 BW |
808 | ((GET_CODE (X) != SYMBOL_REF \ |
809 | || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \ | |
03984308 BW |
810 | && GET_CODE (X) != LABEL_REF \ |
811 | && GET_CODE (X) != CONST) | |
812 | ||
03984308 BW |
813 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
814 | do { \ | |
da1f39e4 BW |
815 | rtx new_x = xtensa_legitimize_address (X, OLDX, MODE); \ |
816 | if (new_x) \ | |
817 | { \ | |
818 | X = new_x; \ | |
819 | goto WIN; \ | |
03984308 BW |
820 | } \ |
821 | } while (0) | |
822 | ||
823 | ||
eb8e00ea BW |
824 | /* Treat constant-pool references as "mode dependent" since they can |
825 | only be accessed with SImode loads. This works around a bug in the | |
826 | combiner where a constant pool reference is temporarily converted | |
827 | to an HImode load, which is then assumed to zero-extend based on | |
828 | our definition of LOAD_EXTEND_OP. This is wrong because the high | |
829 | bits of a 16-bit value in the constant pool are now sign-extended | |
830 | by default. */ | |
831 | ||
832 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ | |
833 | do { \ | |
834 | if (constantpool_address_p (ADDR)) \ | |
835 | goto LABEL; \ | |
836 | } while (0) | |
03984308 | 837 | |
03984308 BW |
838 | /* Specify the machine mode that this machine uses |
839 | for the index in the tablejump instruction. */ | |
840 | #define CASE_VECTOR_MODE (SImode) | |
841 | ||
03984308 BW |
842 | /* Define this as 1 if 'char' should by default be signed; else as 0. */ |
843 | #define DEFAULT_SIGNED_CHAR 0 | |
844 | ||
845 | /* Max number of bytes we can move from memory to memory | |
846 | in one reasonably fast instruction. */ | |
847 | #define MOVE_MAX 4 | |
848 | #define MAX_MOVE_MAX 4 | |
849 | ||
850 | /* Prefer word-sized loads. */ | |
851 | #define SLOW_BYTE_ACCESS 1 | |
852 | ||
03984308 BW |
853 | /* Shift instructions ignore all but the low-order few bits. */ |
854 | #define SHIFT_COUNT_TRUNCATED 1 | |
855 | ||
856 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
3bbc2af6 | 857 | is done just by pretending it is already truncated. */ |
03984308 BW |
858 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
859 | ||
09fa8841 BW |
860 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) |
861 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1) | |
862 | ||
03984308 BW |
863 | /* Specify the machine mode that pointers have. |
864 | After generation of rtl, the compiler makes no further distinction | |
865 | between pointers and any other objects of this machine mode. */ | |
866 | #define Pmode SImode | |
867 | ||
868 | /* A function address in a call instruction is a word address (for | |
869 | indexing purposes) so give the MEM rtx a words's mode. */ | |
870 | #define FUNCTION_MODE SImode | |
871 | ||
03984308 BW |
872 | /* A C expression for the cost of moving data from a register in |
873 | class FROM to one in class TO. The classes are expressed using | |
874 | the enumeration values such as 'GENERAL_REGS'. A value of 2 is | |
875 | the default; other values are interpreted relative to that. */ | |
876 | #define REGISTER_MOVE_COST(MODE, FROM, TO) \ | |
877 | (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \ | |
878 | ? 2 \ | |
879 | : (reg_class_subset_p ((FROM), AR_REGS) \ | |
880 | && reg_class_subset_p ((TO), AR_REGS) \ | |
881 | ? 2 \ | |
882 | : (reg_class_subset_p ((FROM), AR_REGS) \ | |
883 | && (TO) == ACC_REG \ | |
884 | ? 3 \ | |
885 | : ((FROM) == ACC_REG \ | |
886 | && reg_class_subset_p ((TO), AR_REGS) \ | |
887 | ? 3 \ | |
888 | : 10)))) | |
889 | ||
890 | #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4 | |
891 | ||
3a4fd356 | 892 | #define BRANCH_COST(speed_p, predictable_p) 3 |
03984308 | 893 | |
03984308 | 894 | /* How to refer to registers in assembler output. |
3bbc2af6 | 895 | This sequence is indexed by compiler's hard-register-number (see above). */ |
03984308 BW |
896 | #define REGISTER_NAMES \ |
897 | { \ | |
898 | "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \ | |
899 | "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \ | |
900 | "fp", "argp", "b0", \ | |
901 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
902 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ | |
903 | "acc" \ | |
904 | } | |
905 | ||
906 | /* If defined, a C initializer for an array of structures containing a | |
907 | name and a register number. This macro defines additional names | |
908 | for hard registers, thus allowing the 'asm' option in declarations | |
3bbc2af6 | 909 | to refer to registers using alternate names. */ |
03984308 BW |
910 | #define ADDITIONAL_REGISTER_NAMES \ |
911 | { \ | |
912 | { "a1", 1 + GP_REG_FIRST } \ | |
913 | } | |
914 | ||
915 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
916 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
917 | ||
918 | /* Recognize machine-specific patterns that may appear within | |
919 | constants. Used for PIC-specific UNSPECs. */ | |
920 | #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \ | |
921 | do { \ | |
da1f39e4 | 922 | if (xtensa_output_addr_const_extra (STREAM, X) == FALSE) \ |
03984308 BW |
923 | goto FAIL; \ |
924 | } while (0) | |
925 | ||
506a61b1 KG |
926 | /* Globalizing directive for a label. */ |
927 | #define GLOBAL_ASM_OP "\t.global\t" | |
03984308 | 928 | |
6a2b287f BW |
929 | /* Declare an uninitialized external linkage data object. */ |
930 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
931 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
03984308 BW |
932 | |
933 | /* This is how to output an element of a case-vector that is absolute. */ | |
934 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ | |
935 | fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \ | |
936 | LOCAL_LABEL_PREFIX, VALUE) | |
937 | ||
938 | /* This is how to output an element of a case-vector that is relative. | |
3bbc2af6 | 939 | This is used for pc-relative code. */ |
03984308 BW |
940 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ |
941 | do { \ | |
942 | fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \ | |
943 | LOCAL_LABEL_PREFIX, (VALUE), \ | |
944 | LOCAL_LABEL_PREFIX, (REL)); \ | |
945 | } while (0) | |
946 | ||
947 | /* This is how to output an assembler line that says to advance the | |
948 | location counter to a multiple of 2**LOG bytes. */ | |
949 | #define ASM_OUTPUT_ALIGN(STREAM, LOG) \ | |
950 | do { \ | |
951 | if ((LOG) != 0) \ | |
952 | fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \ | |
953 | } while (0) | |
954 | ||
955 | /* Indicate that jump tables go in the text section. This is | |
956 | necessary when compiling PIC code. */ | |
957 | #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) | |
958 | ||
959 | ||
03984308 | 960 | /* Define the strings to put out for each section in the object file. */ |
6a2b287f BW |
961 | #define TEXT_SECTION_ASM_OP "\t.text" |
962 | #define DATA_SECTION_ASM_OP "\t.data" | |
963 | #define BSS_SECTION_ASM_OP "\t.section\t.bss" | |
03984308 BW |
964 | |
965 | ||
9eb8a531 | 966 | /* Define output to appear before the constant pool. */ |
03984308 BW |
967 | #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \ |
968 | do { \ | |
958c70ff | 969 | if ((SIZE) > 0) \ |
86d8c251 | 970 | { \ |
9eb8a531 | 971 | resolve_unique_section ((FUNDECL), 0, flag_function_sections); \ |
d6b5193b | 972 | switch_to_section (function_section (FUNDECL)); \ |
86d8c251 BW |
973 | fprintf (FILE, "\t.literal_position\n"); \ |
974 | } \ | |
03984308 BW |
975 | } while (0) |
976 | ||
977 | ||
03984308 BW |
978 | /* A C statement (with or without semicolon) to output a constant in |
979 | the constant pool, if it needs special treatment. */ | |
980 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \ | |
981 | do { \ | |
982 | xtensa_output_literal (FILE, X, MODE, LABELNO); \ | |
983 | goto JUMPTO; \ | |
984 | } while (0) | |
985 | ||
3bbc2af6 | 986 | /* How to start an assembler comment. */ |
03984308 BW |
987 | #define ASM_COMMENT_START "#" |
988 | ||
6eb065e6 SA |
989 | /* Exception handling. Xtensa uses much of the standard DWARF2 unwinding |
990 | machinery, but the variable size register window save areas are too | |
991 | complicated to efficiently describe with CFI entries. The CFA must | |
992 | still be specified in DWARF so that DW_AT_frame_base is set correctly | |
993 | for debugging. */ | |
4e6c2193 BW |
994 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 0) |
995 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (0) | |
6eb065e6 SA |
996 | #define DWARF_FRAME_REGISTERS 16 |
997 | #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + 2 : INVALID_REGNUM) | |
24eaa34f BW |
998 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
999 | (flag_pic \ | |
1000 | ? (((GLOBAL) ? DW_EH_PE_indirect : 0) \ | |
1001 | | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ | |
1002 | : DW_EH_PE_absptr) | |
1003 | ||
1004 | /* Emit a PC-relative relocation. */ | |
1005 | #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ | |
1006 | do { \ | |
1007 | fputs (integer_asm_op (SIZE, FALSE), FILE); \ | |
1008 | assemble_name (FILE, LABEL); \ | |
1009 | fputs ("@pcrel", FILE); \ | |
1010 | } while (0) | |
03984308 | 1011 | |
a7bda3d5 BW |
1012 | /* Xtensa constant pool breaks the devices in crtstuff.c to control |
1013 | section in where code resides. We have to write it as asm code. Use | |
1014 | a MOVI and let the assembler relax it -- for the .init and .fini | |
1015 | sections, the assembler knows to put the literal in the right | |
1016 | place. */ | |
1017 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
1018 | asm (SECTION_OP "\n\ | |
1019 | movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\ | |
1020 | callx8\ta8\n" \ | |
1021 | TEXT_SECTION_ASM_OP); |