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f6b7ba2b | 1 | /* Definitions of Tensilica's Xtensa target machine for GNU compiler. |
a8332086 | 2 | Copyright 2001,2002 Free Software Foundation, Inc. |
f6b7ba2b | 3 | Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
21 | ||
22 | /* Get Xtensa configuration settings */ | |
23 | #include "xtensa/xtensa-config.h" | |
24 | ||
25 | /* Standard GCC variables that we reference. */ | |
26 | extern int current_function_calls_alloca; | |
27 | extern int target_flags; | |
28 | extern int optimize; | |
29 | ||
30 | /* External variables defined in xtensa.c. */ | |
31 | ||
32 | /* comparison type */ | |
33 | enum cmp_type { | |
34 | CMP_SI, /* four byte integers */ | |
35 | CMP_DI, /* eight byte integers */ | |
36 | CMP_SF, /* single precision floats */ | |
37 | CMP_DF, /* double precision floats */ | |
38 | CMP_MAX /* max comparison type */ | |
39 | }; | |
40 | ||
41 | extern struct rtx_def * branch_cmp[2]; /* operands for compare */ | |
42 | extern enum cmp_type branch_type; /* what type of branch to use */ | |
43 | extern unsigned xtensa_current_frame_size; | |
44 | ||
45 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
46 | ||
47 | #define MASK_BIG_ENDIAN 0x00000001 /* big or little endian */ | |
48 | #define MASK_DENSITY 0x00000002 /* code density option */ | |
49 | #define MASK_MAC16 0x00000004 /* MAC16 option */ | |
50 | #define MASK_MUL16 0x00000008 /* 16-bit integer multiply */ | |
51 | #define MASK_MUL32 0x00000010 /* integer multiply/divide */ | |
52 | #define MASK_DIV32 0x00000020 /* integer multiply/divide */ | |
53 | #define MASK_NSA 0x00000040 /* nsa instruction option */ | |
54 | #define MASK_MINMAX 0x00000080 /* min/max instructions */ | |
55 | #define MASK_SEXT 0x00000100 /* sign extend insn option */ | |
56 | #define MASK_BOOLEANS 0x00000200 /* boolean register option */ | |
57 | #define MASK_HARD_FLOAT 0x00000400 /* floating-point option */ | |
58 | #define MASK_HARD_FLOAT_DIV 0x00000800 /* floating-point divide */ | |
59 | #define MASK_HARD_FLOAT_RECIP 0x00001000 /* floating-point reciprocal */ | |
60 | #define MASK_HARD_FLOAT_SQRT 0x00002000 /* floating-point sqrt */ | |
61 | #define MASK_HARD_FLOAT_RSQRT 0x00004000 /* floating-point recip sqrt */ | |
62 | #define MASK_NO_FUSED_MADD 0x00008000 /* avoid f-p mul/add */ | |
63 | #define MASK_SERIALIZE_VOLATILE 0x00010000 /* serialize volatile refs */ | |
64 | ||
65 | /* Macros used in the machine description to test the flags. */ | |
66 | ||
67 | #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN) | |
68 | #define TARGET_DENSITY (target_flags & MASK_DENSITY) | |
69 | #define TARGET_MAC16 (target_flags & MASK_MAC16) | |
70 | #define TARGET_MUL16 (target_flags & MASK_MUL16) | |
71 | #define TARGET_MUL32 (target_flags & MASK_MUL32) | |
72 | #define TARGET_DIV32 (target_flags & MASK_DIV32) | |
73 | #define TARGET_NSA (target_flags & MASK_NSA) | |
74 | #define TARGET_MINMAX (target_flags & MASK_MINMAX) | |
75 | #define TARGET_SEXT (target_flags & MASK_SEXT) | |
76 | #define TARGET_BOOLEANS (target_flags & MASK_BOOLEANS) | |
77 | #define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT) | |
78 | #define TARGET_HARD_FLOAT_DIV (target_flags & MASK_HARD_FLOAT_DIV) | |
79 | #define TARGET_HARD_FLOAT_RECIP (target_flags & MASK_HARD_FLOAT_RECIP) | |
80 | #define TARGET_HARD_FLOAT_SQRT (target_flags & MASK_HARD_FLOAT_SQRT) | |
81 | #define TARGET_HARD_FLOAT_RSQRT (target_flags & MASK_HARD_FLOAT_RSQRT) | |
82 | #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD) | |
83 | #define TARGET_SERIALIZE_VOLATILE (target_flags & MASK_SERIALIZE_VOLATILE) | |
84 | ||
85 | /* Default target_flags if no switches are specified */ | |
86 | ||
87 | #define TARGET_DEFAULT ( \ | |
88 | (XCHAL_HAVE_BE ? MASK_BIG_ENDIAN : 0) | \ | |
89 | (XCHAL_HAVE_DENSITY ? MASK_DENSITY : 0) | \ | |
90 | (XCHAL_HAVE_MAC16 ? MASK_MAC16 : 0) | \ | |
91 | (XCHAL_HAVE_MUL16 ? MASK_MUL16 : 0) | \ | |
92 | (XCHAL_HAVE_MUL32 ? MASK_MUL32 : 0) | \ | |
93 | (XCHAL_HAVE_DIV32 ? MASK_DIV32 : 0) | \ | |
94 | (XCHAL_HAVE_NSA ? MASK_NSA : 0) | \ | |
95 | (XCHAL_HAVE_MINMAX ? MASK_MINMAX : 0) | \ | |
96 | (XCHAL_HAVE_SEXT ? MASK_SEXT : 0) | \ | |
97 | (XCHAL_HAVE_BOOLEANS ? MASK_BOOLEANS : 0) | \ | |
98 | (XCHAL_HAVE_FP ? MASK_HARD_FLOAT : 0) | \ | |
99 | (XCHAL_HAVE_FP_DIV ? MASK_HARD_FLOAT_DIV : 0) | \ | |
100 | (XCHAL_HAVE_FP_RECIP ? MASK_HARD_FLOAT_RECIP : 0) | \ | |
101 | (XCHAL_HAVE_FP_SQRT ? MASK_HARD_FLOAT_SQRT : 0) | \ | |
102 | (XCHAL_HAVE_FP_RSQRT ? MASK_HARD_FLOAT_RSQRT : 0) | \ | |
103 | MASK_SERIALIZE_VOLATILE) | |
104 | ||
105 | /* Macro to define tables used to set the flags. */ | |
106 | ||
107 | #define TARGET_SWITCHES \ | |
108 | { \ | |
109 | {"big-endian", MASK_BIG_ENDIAN, \ | |
110 | N_("Use big-endian byte order")}, \ | |
111 | {"little-endian", -MASK_BIG_ENDIAN, \ | |
112 | N_("Use little-endian byte order")}, \ | |
113 | {"density", MASK_DENSITY, \ | |
114 | N_("Use the Xtensa code density option")}, \ | |
115 | {"no-density", -MASK_DENSITY, \ | |
116 | N_("Do not use the Xtensa code density option")}, \ | |
117 | {"mac16", MASK_MAC16, \ | |
118 | N_("Use the Xtensa MAC16 option")}, \ | |
119 | {"no-mac16", -MASK_MAC16, \ | |
120 | N_("Do not use the Xtensa MAC16 option")}, \ | |
121 | {"mul16", MASK_MUL16, \ | |
122 | N_("Use the Xtensa MUL16 option")}, \ | |
123 | {"no-mul16", -MASK_MUL16, \ | |
124 | N_("Do not use the Xtensa MUL16 option")}, \ | |
125 | {"mul32", MASK_MUL32, \ | |
126 | N_("Use the Xtensa MUL32 option")}, \ | |
127 | {"no-mul32", -MASK_MUL32, \ | |
128 | N_("Do not use the Xtensa MUL32 option")}, \ | |
129 | {"div32", MASK_DIV32, \ | |
130 | 0 /* undocumented */}, \ | |
131 | {"no-div32", -MASK_DIV32, \ | |
132 | 0 /* undocumented */}, \ | |
133 | {"nsa", MASK_NSA, \ | |
134 | N_("Use the Xtensa NSA option")}, \ | |
135 | {"no-nsa", -MASK_NSA, \ | |
136 | N_("Do not use the Xtensa NSA option")}, \ | |
137 | {"minmax", MASK_MINMAX, \ | |
138 | N_("Use the Xtensa MIN/MAX option")}, \ | |
139 | {"no-minmax", -MASK_MINMAX, \ | |
140 | N_("Do not use the Xtensa MIN/MAX option")}, \ | |
141 | {"sext", MASK_SEXT, \ | |
142 | N_("Use the Xtensa SEXT option")}, \ | |
143 | {"no-sext", -MASK_SEXT, \ | |
144 | N_("Do not use the Xtensa SEXT option")}, \ | |
145 | {"booleans", MASK_BOOLEANS, \ | |
146 | N_("Use the Xtensa boolean register option")}, \ | |
147 | {"no-booleans", -MASK_BOOLEANS, \ | |
148 | N_("Do not use the Xtensa boolean register option")}, \ | |
149 | {"hard-float", MASK_HARD_FLOAT, \ | |
150 | N_("Use the Xtensa floating-point unit")}, \ | |
151 | {"soft-float", -MASK_HARD_FLOAT, \ | |
152 | N_("Do not use the Xtensa floating-point unit")}, \ | |
153 | {"hard-float-div", MASK_HARD_FLOAT_DIV, \ | |
154 | 0 /* undocumented */}, \ | |
155 | {"no-hard-float-div", -MASK_HARD_FLOAT_DIV, \ | |
156 | 0 /* undocumented */}, \ | |
157 | {"hard-float-recip", MASK_HARD_FLOAT_RECIP, \ | |
158 | 0 /* undocumented */}, \ | |
159 | {"no-hard-float-recip", -MASK_HARD_FLOAT_RECIP, \ | |
160 | 0 /* undocumented */}, \ | |
161 | {"hard-float-sqrt", MASK_HARD_FLOAT_SQRT, \ | |
162 | 0 /* undocumented */}, \ | |
163 | {"no-hard-float-sqrt", -MASK_HARD_FLOAT_SQRT, \ | |
164 | 0 /* undocumented */}, \ | |
165 | {"hard-float-rsqrt", MASK_HARD_FLOAT_RSQRT, \ | |
166 | 0 /* undocumented */}, \ | |
167 | {"no-hard-float-rsqrt", -MASK_HARD_FLOAT_RSQRT, \ | |
168 | 0 /* undocumented */}, \ | |
169 | {"no-fused-madd", MASK_NO_FUSED_MADD, \ | |
170 | N_("Disable fused multiply/add and multiply/subtract FP instructions")}, \ | |
171 | {"fused-madd", -MASK_NO_FUSED_MADD, \ | |
172 | N_("Enable fused multiply/add and multiply/subtract FP instructions")}, \ | |
173 | {"serialize-volatile", MASK_SERIALIZE_VOLATILE, \ | |
174 | N_("Serialize volatile memory references with MEMW instructions")}, \ | |
175 | {"no-serialize-volatile", -MASK_SERIALIZE_VOLATILE, \ | |
176 | N_("Do not serialize volatile memory references with MEMW instructions")},\ | |
177 | {"text-section-literals", 0, \ | |
178 | N_("Intersperse literal pools with code in the text section")}, \ | |
179 | {"no-text-section-literals", 0, \ | |
180 | N_("Put literal pools in a separate literal section")}, \ | |
181 | {"target-align", 0, \ | |
182 | N_("Automatically align branch targets to reduce branch penalties")}, \ | |
183 | {"no-target-align", 0, \ | |
184 | N_("Do not automatically align branch targets")}, \ | |
185 | {"longcalls", 0, \ | |
186 | N_("Use indirect CALLXn instructions for large programs")}, \ | |
187 | {"no-longcalls", 0, \ | |
188 | N_("Use direct CALLn instructions for fast calls")}, \ | |
189 | {"", TARGET_DEFAULT, 0} \ | |
190 | } | |
191 | ||
192 | ||
193 | #define OVERRIDE_OPTIONS override_options () | |
56abe40c | 194 | \f |
195 | /* Target CPU builtins. */ | |
196 | #define TARGET_CPU_CPP_BUILTINS() \ | |
197 | do { \ | |
198 | builtin_assert ("cpu=xtensa"); \ | |
199 | builtin_assert ("machine=xtensa"); \ | |
200 | builtin_define ("__XTENSA__"); \ | |
201 | builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \ | |
202 | if (!TARGET_HARD_FLOAT) \ | |
203 | builtin_define ("__XTENSA_SOFT_FLOAT__"); \ | |
204 | if (flag_pic) \ | |
205 | { \ | |
206 | builtin_define ("__PIC__"); \ | |
207 | builtin_define ("__pic__"); \ | |
208 | } \ | |
209 | } while (0) | |
f6b7ba2b | 210 | |
211 | /* Define this to set the endianness to use in libgcc2.c, which can | |
212 | not depend on target_flags. */ | |
213 | #define LIBGCC2_WORDS_BIG_ENDIAN XCHAL_HAVE_BE | |
214 | ||
215 | /* Show we can debug even without a frame pointer. */ | |
216 | #define CAN_DEBUG_WITHOUT_FP | |
217 | ||
218 | ||
219 | /* Target machine storage layout */ | |
220 | ||
f6b7ba2b | 221 | /* Define this if most significant bit is lowest numbered |
222 | in instructions that operate on numbered bit-fields. */ | |
223 | #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) | |
224 | ||
225 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
226 | #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) | |
227 | ||
228 | /* Define this if most significant word of a multiword number is the lowest. */ | |
229 | #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) | |
230 | ||
f6b7ba2b | 231 | #define MAX_BITS_PER_WORD 32 |
232 | ||
233 | /* Width of a word, in units (bytes). */ | |
234 | #define UNITS_PER_WORD 4 | |
235 | #define MIN_UNITS_PER_WORD 4 | |
236 | ||
237 | /* Width of a floating point register. */ | |
238 | #define UNITS_PER_FPREG 4 | |
239 | ||
240 | /* Size in bits of various types on the target machine. */ | |
241 | #define INT_TYPE_SIZE 32 | |
f6b7ba2b | 242 | #define SHORT_TYPE_SIZE 16 |
243 | #define LONG_TYPE_SIZE 32 | |
244 | #define MAX_LONG_TYPE_SIZE 32 | |
245 | #define LONG_LONG_TYPE_SIZE 64 | |
f6b7ba2b | 246 | #define FLOAT_TYPE_SIZE 32 |
247 | #define DOUBLE_TYPE_SIZE 64 | |
248 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
f6b7ba2b | 249 | |
f6b7ba2b | 250 | /* Allocation boundary (in *bits*) for storing pointers in memory. */ |
251 | #define POINTER_BOUNDARY 32 | |
252 | ||
253 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
254 | #define PARM_BOUNDARY 32 | |
255 | ||
256 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
257 | #define FUNCTION_BOUNDARY 32 | |
258 | ||
259 | /* Alignment of field after 'int : 0' in a structure. */ | |
260 | #define EMPTY_FIELD_BOUNDARY 32 | |
261 | ||
262 | /* Every structure's size must be a multiple of this. */ | |
263 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
264 | ||
265 | /* There is no point aligning anything to a rounder boundary than this. */ | |
266 | #define BIGGEST_ALIGNMENT 128 | |
267 | ||
268 | /* Set this nonzero if move instructions will actually fail to work | |
269 | when given unaligned data. */ | |
270 | #define STRICT_ALIGNMENT 1 | |
271 | ||
272 | /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP | |
273 | for QImode, because there is no 8-bit load from memory with sign | |
274 | extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit | |
275 | loads both with and without sign extension. */ | |
276 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
277 | do { \ | |
278 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
279 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
280 | { \ | |
281 | if ((MODE) == QImode) \ | |
282 | (UNSIGNEDP) = 1; \ | |
283 | (MODE) = SImode; \ | |
284 | } \ | |
285 | } while (0) | |
286 | ||
287 | /* The promotion described by `PROMOTE_MODE' should also be done for | |
288 | outgoing function arguments. */ | |
289 | #define PROMOTE_FUNCTION_ARGS | |
290 | ||
291 | /* The promotion described by `PROMOTE_MODE' should also be done for | |
292 | the return value of functions. Note: `FUNCTION_VALUE' must perform | |
293 | the same promotions done by `PROMOTE_MODE'. */ | |
294 | #define PROMOTE_FUNCTION_RETURN | |
295 | ||
296 | /* Imitate the way many other C compilers handle alignment of | |
297 | bitfields and the structures that contain them. */ | |
298 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
299 | ||
300 | /* Align string constants and constructors to at least a word boundary. | |
301 | The typical use of this macro is to increase alignment for string | |
302 | constants to be word aligned so that 'strcpy' calls that copy | |
303 | constants can be done inline. */ | |
304 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
305 | ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ | |
306 | && (ALIGN) < BITS_PER_WORD \ | |
307 | ? BITS_PER_WORD \ | |
308 | : (ALIGN)) | |
309 | ||
310 | /* Align arrays, unions and records to at least a word boundary. | |
311 | One use of this macro is to increase alignment of medium-size | |
312 | data to make it all fit in fewer cache lines. Another is to | |
313 | cause character arrays to be word-aligned so that 'strcpy' calls | |
314 | that copy constants to character arrays can be done inline. */ | |
315 | #undef DATA_ALIGNMENT | |
316 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
317 | ((((ALIGN) < BITS_PER_WORD) \ | |
318 | && (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
319 | || TREE_CODE (TYPE) == UNION_TYPE \ | |
320 | || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
321 | ||
322 | /* An argument declared as 'char' or 'short' in a prototype should | |
323 | actually be passed as an 'int'. */ | |
324 | #define PROMOTE_PROTOTYPES 1 | |
325 | ||
326 | /* Operations between registers always perform the operation | |
327 | on the full register even if a narrower mode is specified. */ | |
328 | #define WORD_REGISTER_OPERATIONS | |
329 | ||
330 | /* Xtensa loads are zero-extended by default. */ | |
331 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
332 | ||
333 | /* Standard register usage. */ | |
334 | ||
335 | /* Number of actual hardware registers. | |
336 | The hardware registers are assigned numbers for the compiler | |
337 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
338 | All registers that the compiler knows about must be given numbers, | |
339 | even those that are not normally considered general registers. | |
340 | ||
341 | The fake frame pointer and argument pointer will never appear in | |
342 | the generated code, since they will always be eliminated and replaced | |
343 | by either the stack pointer or the hard frame pointer. | |
344 | ||
345 | 0 - 15 AR[0] - AR[15] | |
346 | 16 FRAME_POINTER (fake = initial sp) | |
347 | 17 ARG_POINTER (fake = initial sp + framesize) | |
348 | 18 LOOP_COUNT (loop count special register) | |
349 | 18 BR[0] for floating-point CC | |
350 | 19 - 34 FR[0] - FR[15] | |
351 | 35 MAC16 accumulator */ | |
352 | ||
353 | #define FIRST_PSEUDO_REGISTER 36 | |
354 | ||
355 | /* Return the stabs register number to use for REGNO. */ | |
356 | #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO) | |
357 | ||
358 | /* 1 for registers that have pervasive standard uses | |
359 | and are not available for the register allocator. */ | |
360 | #define FIXED_REGISTERS \ | |
361 | { \ | |
362 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
363 | 1, 1, 0, \ | |
364 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
365 | 0, \ | |
366 | } | |
367 | ||
368 | /* 1 for registers not available across function calls. | |
369 | These must include the FIXED_REGISTERS and also any | |
370 | registers that can be used without being saved. | |
371 | The latter must include the registers where values are returned | |
372 | and the register where structure-value addresses are passed. | |
373 | Aside from that, you can include as many other registers as you like. */ | |
374 | #define CALL_USED_REGISTERS \ | |
375 | { \ | |
376 | 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
377 | 1, 1, 1, \ | |
378 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
379 | 1, \ | |
380 | } | |
381 | ||
382 | /* For non-leaf procedures on Xtensa processors, the allocation order | |
383 | is as specified below by REG_ALLOC_ORDER. For leaf procedures, we | |
384 | want to use the lowest numbered registers first to minimize | |
385 | register window overflows. However, local-alloc is not smart | |
386 | enough to consider conflicts with incoming arguments. If an | |
387 | incoming argument in a2 is live throughout the function and | |
388 | local-alloc decides to use a2, then the incoming argument must | |
389 | either be spilled or copied to another register. To get around | |
390 | this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine | |
391 | reg_alloc_order for leaf functions such that lowest numbered | |
392 | registers are used first with the exception that the incoming | |
393 | argument registers are not used until after other register choices | |
394 | have been exhausted. */ | |
395 | ||
396 | #define REG_ALLOC_ORDER \ | |
397 | { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, 19, \ | |
398 | 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, \ | |
399 | 0, 1, 16, 17, \ | |
400 | 36, \ | |
401 | } | |
402 | ||
403 | #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () | |
404 | ||
405 | /* For Xtensa, the only point of this is to prevent GCC from otherwise | |
406 | giving preference to call-used registers. To minimize window | |
407 | overflows for the AR registers, we want to give preference to the | |
408 | lower-numbered AR registers. For other register files, which are | |
409 | not windowed, we still prefer call-used registers, if there are any. */ | |
410 | extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER]; | |
411 | #define LEAF_REGISTERS xtensa_leaf_regs | |
412 | ||
413 | /* For Xtensa, no remapping is necessary, but this macro must be | |
414 | defined if LEAF_REGISTERS is defined. */ | |
415 | #define LEAF_REG_REMAP(REGNO) (REGNO) | |
416 | ||
417 | /* this must be declared if LEAF_REGISTERS is set */ | |
418 | extern int leaf_function; | |
419 | ||
420 | /* Internal macros to classify a register number. */ | |
421 | ||
422 | /* 16 address registers + fake registers */ | |
423 | #define GP_REG_FIRST 0 | |
424 | #define GP_REG_LAST 17 | |
425 | #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) | |
426 | ||
427 | /* Special registers */ | |
428 | #define SPEC_REG_FIRST 18 | |
429 | #define SPEC_REG_LAST 18 | |
430 | #define SPEC_REG_NUM (SPEC_REG_LAST - SPEC_REG_FIRST + 1) | |
431 | ||
432 | /* Coprocessor registers */ | |
433 | #define BR_REG_FIRST 18 | |
434 | #define BR_REG_LAST 18 | |
435 | #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1) | |
436 | ||
437 | /* 16 floating-point registers */ | |
438 | #define FP_REG_FIRST 19 | |
439 | #define FP_REG_LAST 34 | |
440 | #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) | |
441 | ||
442 | /* MAC16 accumulator */ | |
443 | #define ACC_REG_FIRST 35 | |
444 | #define ACC_REG_LAST 35 | |
445 | #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1) | |
446 | ||
447 | #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM) | |
448 | #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM) | |
449 | #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM) | |
450 | #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM) | |
451 | ||
452 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
453 | to hold something of mode MODE. */ | |
454 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
455 | (FP_REG_P (REGNO) ? \ | |
456 | ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \ | |
457 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
458 | ||
459 | /* Value is 1 if hard register REGNO can hold a value of machine-mode | |
460 | MODE. */ | |
461 | extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; | |
462 | ||
463 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
464 | xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)] | |
465 | ||
466 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
467 | when one has mode MODE1 and one has mode MODE2. | |
468 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
469 | for any hard reg, then this must be 0 for correct output. */ | |
470 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
471 | ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ | |
472 | GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ | |
473 | == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ | |
474 | GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) | |
475 | ||
476 | /* Register to use for LCOUNT special register. */ | |
477 | #define COUNT_REGISTER_REGNUM (SPEC_REG_FIRST + 0) | |
478 | ||
479 | /* Register to use for pushing function arguments. */ | |
480 | #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1) | |
481 | ||
482 | /* Base register for access to local variables of the function. */ | |
483 | #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7) | |
484 | ||
485 | /* The register number of the frame pointer register, which is used to | |
486 | access automatic variables in the stack frame. For Xtensa, this | |
487 | register never appears in the output. It is always eliminated to | |
488 | either the stack pointer or the hard frame pointer. */ | |
489 | #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16) | |
490 | ||
491 | /* Value should be nonzero if functions must have frame pointers. | |
492 | Zero means the frame pointer need not be set up (and parms | |
493 | may be accessed via the stack pointer) in functions that seem suitable. | |
494 | This is computed in 'reload', in reload1.c. */ | |
495 | #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required () | |
496 | ||
497 | /* Base register for access to arguments of the function. */ | |
498 | #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17) | |
499 | ||
500 | /* If the static chain is passed in memory, these macros provide rtx | |
501 | giving 'mem' expressions that denote where they are stored. | |
502 | 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as | |
503 | seen by the calling and called functions, respectively. */ | |
504 | ||
505 | #define STATIC_CHAIN \ | |
506 | gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD)) | |
507 | ||
508 | #define STATIC_CHAIN_INCOMING \ | |
509 | gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD)) | |
510 | ||
511 | /* For now we don't try to use the full set of boolean registers. Without | |
512 | software pipelining of FP operations, there's not much to gain and it's | |
513 | a real pain to get them reloaded. */ | |
514 | #define FPCC_REGNUM (BR_REG_FIRST + 0) | |
515 | ||
516 | /* Pass structure value address as an "invisible" first argument. */ | |
517 | #define STRUCT_VALUE 0 | |
518 | ||
519 | /* It is as good or better to call a constant function address than to | |
520 | call an address kept in a register. */ | |
521 | #define NO_FUNCTION_CSE 1 | |
522 | ||
523 | /* It is as good or better for a function to call itself with an | |
524 | explicit address than to call an address kept in a register. */ | |
525 | #define NO_RECURSIVE_FUNCTION_CSE 1 | |
526 | ||
527 | /* Xtensa processors have "register windows". GCC does not currently | |
528 | take advantage of the possibility for variable-sized windows; instead, | |
529 | we use a fixed window size of 8. */ | |
530 | ||
531 | #define INCOMING_REGNO(OUT) \ | |
532 | ((GP_REG_P (OUT) && \ | |
533 | ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \ | |
534 | (OUT) - WINDOW_SIZE : (OUT)) | |
535 | ||
536 | #define OUTGOING_REGNO(IN) \ | |
537 | ((GP_REG_P (IN) && \ | |
538 | ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \ | |
539 | (IN) + WINDOW_SIZE : (IN)) | |
540 | ||
541 | ||
542 | /* Define the classes of registers for register constraints in the | |
543 | machine description. */ | |
544 | enum reg_class | |
545 | { | |
546 | NO_REGS, /* no registers in set */ | |
547 | BR_REGS, /* coprocessor boolean registers */ | |
548 | FP_REGS, /* floating point registers */ | |
549 | ACC_REG, /* MAC16 accumulator */ | |
550 | SP_REG, /* sp register (aka a1) */ | |
a8332086 | 551 | RL_REGS, /* preferred reload regs (not sp or fp) */ |
f6b7ba2b | 552 | GR_REGS, /* integer registers except sp */ |
553 | AR_REGS, /* all integer registers */ | |
554 | ALL_REGS, /* all registers */ | |
555 | LIM_REG_CLASSES /* max value + 1 */ | |
556 | }; | |
557 | ||
558 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
559 | ||
560 | #define GENERAL_REGS AR_REGS | |
561 | ||
562 | /* An initializer containing the names of the register classes as C | |
563 | string constants. These names are used in writing some of the | |
564 | debugging dumps. */ | |
565 | #define REG_CLASS_NAMES \ | |
566 | { \ | |
567 | "NO_REGS", \ | |
568 | "BR_REGS", \ | |
569 | "FP_REGS", \ | |
570 | "ACC_REG", \ | |
571 | "SP_REG", \ | |
a8332086 | 572 | "RL_REGS", \ |
f6b7ba2b | 573 | "GR_REGS", \ |
574 | "AR_REGS", \ | |
575 | "ALL_REGS" \ | |
576 | } | |
577 | ||
578 | /* Contents of the register classes. The Nth integer specifies the | |
579 | contents of class N. The way the integer MASK is interpreted is | |
580 | that register R is in the class if 'MASK & (1 << R)' is 1. */ | |
581 | #define REG_CLASS_CONTENTS \ | |
582 | { \ | |
583 | { 0x00000000, 0x00000000 }, /* no registers */ \ | |
584 | { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \ | |
585 | { 0xfff80000, 0x00000007 }, /* floating-point registers */ \ | |
586 | { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \ | |
587 | { 0x00000002, 0x00000000 }, /* stack pointer register */ \ | |
a8332086 | 588 | { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \ |
f6b7ba2b | 589 | { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \ |
590 | { 0x0003ffff, 0x00000000 }, /* integer registers */ \ | |
591 | { 0xffffffff, 0x0000000f } /* all registers */ \ | |
592 | } | |
593 | ||
594 | /* A C expression whose value is a register class containing hard | |
595 | register REGNO. In general there is more that one such class; | |
596 | choose a class which is "minimal", meaning that no smaller class | |
597 | also contains the register. */ | |
598 | extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER]; | |
599 | ||
600 | #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ] | |
601 | ||
602 | /* Use the Xtensa AR register file for base registers. | |
603 | No index registers. */ | |
604 | #define BASE_REG_CLASS AR_REGS | |
605 | #define INDEX_REG_CLASS NO_REGS | |
606 | ||
607 | /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the | |
608 | 16 AR registers may be explicitly used in the RTL, as either | |
609 | incoming or outgoing arguments. */ | |
610 | #define SMALL_REGISTER_CLASSES 1 | |
611 | ||
612 | ||
613 | /* REGISTER AND CONSTANT CLASSES */ | |
614 | ||
615 | /* Get reg_class from a letter such as appears in the machine | |
616 | description. | |
617 | ||
618 | Available letters: a-f,h,j-l,q,t-z,A-D,W,Y-Z | |
619 | ||
620 | DEFINED REGISTER CLASSES: | |
621 | ||
622 | 'a' general-purpose registers except sp | |
623 | 'q' sp (aka a1) | |
624 | 'D' general-purpose registers (only if density option enabled) | |
625 | 'd' general-purpose registers, including sp (only if density enabled) | |
626 | 'A' MAC16 accumulator (only if MAC16 option enabled) | |
627 | 'B' general-purpose registers (only if sext instruction enabled) | |
628 | 'C' general-purpose registers (only if mul16 option enabled) | |
629 | 'b' coprocessor boolean registers | |
630 | 'f' floating-point registers | |
631 | */ | |
632 | ||
633 | extern enum reg_class xtensa_char_to_class[256]; | |
634 | ||
635 | #define REG_CLASS_FROM_LETTER(C) xtensa_char_to_class[ (int) (C) ] | |
636 | ||
637 | /* The letters I, J, K, L, M, N, O, and P in a register constraint | |
638 | string can be used to stand for particular ranges of immediate | |
639 | operands. This macro defines what the ranges are. C is the | |
640 | letter, and VALUE is a constant value. Return 1 if VALUE is | |
641 | in the range specified by C. | |
642 | ||
643 | For Xtensa: | |
644 | ||
645 | I = 12-bit signed immediate for movi | |
646 | J = 8-bit signed immediate for addi | |
647 | K = 4-bit value in (b4const U {0}) | |
648 | L = 4-bit value in b4constu | |
649 | M = 7-bit value in simm7 | |
650 | N = 8-bit unsigned immediate shifted left by 8 bits for addmi | |
651 | O = 4-bit value in ai4const | |
652 | P = valid immediate mask value for extui */ | |
653 | ||
654 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
655 | ((C) == 'I' ? (xtensa_simm12b (VALUE)) \ | |
656 | : (C) == 'J' ? (xtensa_simm8 (VALUE)) \ | |
657 | : (C) == 'K' ? (((VALUE) == 0) || xtensa_b4const (VALUE)) \ | |
658 | : (C) == 'L' ? (xtensa_b4constu (VALUE)) \ | |
659 | : (C) == 'M' ? (xtensa_simm7 (VALUE)) \ | |
660 | : (C) == 'N' ? (xtensa_simm8x256 (VALUE)) \ | |
661 | : (C) == 'O' ? (xtensa_ai4const (VALUE)) \ | |
662 | : (C) == 'P' ? (xtensa_mask_immediate (VALUE)) \ | |
663 | : FALSE) | |
664 | ||
665 | ||
666 | /* Similar, but for floating constants, and defining letters G and H. | |
667 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
668 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) (0) | |
669 | ||
670 | ||
671 | /* Other letters can be defined in a machine-dependent fashion to | |
672 | stand for particular classes of registers or other arbitrary | |
673 | operand types. | |
674 | ||
675 | R = memory that can be accessed with a 4-bit unsigned offset | |
676 | S = memory where the second word can be addressed with a 4-bit offset | |
677 | T = memory in a constant pool (addressable with a pc-relative load) | |
678 | U = memory *NOT* in a constant pool | |
679 | ||
680 | The offset range should not be checked here (except to distinguish | |
681 | denser versions of the instructions for which more general versions | |
682 | are available). Doing so leads to problems in reloading: an | |
683 | argptr-relative address may become invalid when the phony argptr is | |
684 | eliminated in favor of the stack pointer (the offset becomes too | |
685 | large to fit in the instruction's immediate field); a reload is | |
686 | generated to fix this but the RTL is not immediately updated; in | |
687 | the meantime, the constraints are checked and none match. The | |
688 | solution seems to be to simply skip the offset check here. The | |
689 | address will be checked anyway because of the code in | |
690 | GO_IF_LEGITIMATE_ADDRESS. */ | |
691 | ||
692 | #define EXTRA_CONSTRAINT(OP, CODE) \ | |
693 | ((GET_CODE (OP) != MEM) ? \ | |
694 | ((CODE) >= 'R' && (CODE) <= 'U' \ | |
695 | && reload_in_progress && GET_CODE (OP) == REG \ | |
696 | && REGNO (OP) >= FIRST_PSEUDO_REGISTER) \ | |
697 | : ((CODE) == 'R') ? smalloffset_mem_p (OP) \ | |
698 | : ((CODE) == 'S') ? smalloffset_double_mem_p (OP) \ | |
699 | : ((CODE) == 'T') ? constantpool_mem_p (OP) \ | |
700 | : ((CODE) == 'U') ? !constantpool_mem_p (OP) \ | |
701 | : FALSE) | |
702 | ||
f6b7ba2b | 703 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ |
a8332086 | 704 | xtensa_preferred_reload_class (X, CLASS, 0) |
f6b7ba2b | 705 | |
706 | #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ | |
a8332086 | 707 | xtensa_preferred_reload_class (X, CLASS, 1) |
f6b7ba2b | 708 | |
709 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
710 | xtensa_secondary_reload_class (CLASS, MODE, X, 0) | |
711 | ||
712 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
713 | xtensa_secondary_reload_class (CLASS, MODE, X, 1) | |
714 | ||
715 | /* Return the maximum number of consecutive registers | |
716 | needed to represent mode MODE in a register of class CLASS. */ | |
717 | #define CLASS_UNITS(mode, size) \ | |
718 | ((GET_MODE_SIZE (mode) + (size) - 1) / (size)) | |
719 | ||
720 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
721 | (CLASS_UNITS (MODE, UNITS_PER_WORD)) | |
722 | ||
723 | ||
724 | /* Stack layout; function entry, exit and calling. */ | |
725 | ||
726 | #define STACK_GROWS_DOWNWARD | |
727 | ||
728 | /* Offset within stack frame to start allocating local variables at. */ | |
729 | #define STARTING_FRAME_OFFSET \ | |
730 | current_function_outgoing_args_size | |
731 | ||
732 | /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so | |
733 | they are eliminated to either the stack pointer or hard frame pointer. */ | |
734 | #define ELIMINABLE_REGS \ | |
735 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
736 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
737 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
738 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
739 | ||
740 | #define CAN_ELIMINATE(FROM, TO) 1 | |
741 | ||
742 | /* Specify the initial difference between the specified pair of registers. */ | |
743 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
744 | do { \ | |
745 | compute_frame_size (get_frame_size ()); \ | |
746 | if ((FROM) == FRAME_POINTER_REGNUM) \ | |
747 | (OFFSET) = 0; \ | |
748 | else if ((FROM) == ARG_POINTER_REGNUM) \ | |
749 | (OFFSET) = xtensa_current_frame_size; \ | |
750 | else \ | |
751 | abort (); \ | |
752 | } while (0) | |
753 | ||
754 | /* If defined, the maximum amount of space required for outgoing | |
755 | arguments will be computed and placed into the variable | |
756 | 'current_function_outgoing_args_size'. No space will be pushed | |
757 | onto the stack for each call; instead, the function prologue | |
758 | should increase the stack frame size by this amount. */ | |
759 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
760 | ||
761 | /* Offset from the argument pointer register to the first argument's | |
762 | address. On some machines it may depend on the data type of the | |
763 | function. If 'ARGS_GROW_DOWNWARD', this is the offset to the | |
764 | location above the first argument's address. */ | |
765 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
766 | ||
767 | /* Align stack frames on 128 bits for Xtensa. This is necessary for | |
768 | 128-bit datatypes defined in TIE (e.g., for Vectra). */ | |
769 | #define STACK_BOUNDARY 128 | |
770 | ||
771 | /* Functions do not pop arguments off the stack. */ | |
772 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 | |
773 | ||
774 | /* Use a fixed register window size of 8. */ | |
775 | #define WINDOW_SIZE 8 | |
776 | ||
777 | /* Symbolic macros for the registers used to return integer, floating | |
778 | point, and values of coprocessor and user-defined modes. */ | |
779 | #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE) | |
780 | #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2) | |
781 | ||
782 | /* Symbolic macros for the first/last argument registers. */ | |
783 | #define GP_ARG_FIRST (GP_REG_FIRST + 2) | |
784 | #define GP_ARG_LAST (GP_REG_FIRST + 7) | |
785 | #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE) | |
786 | #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE) | |
787 | ||
788 | #define MAX_ARGS_IN_REGISTERS 6 | |
789 | ||
790 | /* Don't worry about compatibility with PCC. */ | |
791 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
792 | ||
21f3b542 | 793 | /* For Xtensa, up to 4 words can be returned in registers. (It would |
794 | have been nice to allow up to 6 words in registers but GCC cannot | |
795 | support that. The return value must be given one of the standard | |
796 | MODE_INT modes, and there is no 6 word mode. Instead, if we try to | |
797 | return a 6 word structure, GCC selects the next biggest mode | |
798 | (OImode, 8 words) and then the register allocator fails because | |
799 | there is no 8-register group beginning with a10.) */ | |
f6b7ba2b | 800 | #define RETURN_IN_MEMORY(TYPE) \ |
801 | ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 4 * UNITS_PER_WORD) | |
802 | ||
803 | /* Define how to find the value returned by a library function | |
804 | assuming the value has mode MODE. Because we have defined | |
805 | PROMOTE_FUNCTION_RETURN, we have to perform the same promotions as | |
806 | PROMOTE_MODE. */ | |
807 | #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \ | |
808 | gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \ | |
809 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
810 | ? SImode : (MODE), \ | |
811 | OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN) | |
812 | ||
813 | #define LIBCALL_VALUE(MODE) \ | |
814 | XTENSA_LIBCALL_VALUE ((MODE), 0) | |
815 | ||
816 | #define LIBCALL_OUTGOING_VALUE(MODE) \ | |
817 | XTENSA_LIBCALL_VALUE ((MODE), 1) | |
818 | ||
819 | /* Define how to find the value returned by a function. | |
820 | VALTYPE is the data type of the value (as a tree). | |
821 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
822 | otherwise, FUNC is 0. */ | |
823 | #define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP) \ | |
824 | gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \ | |
825 | && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ | |
826 | ? SImode: TYPE_MODE (VALTYPE), \ | |
827 | OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN) | |
828 | ||
829 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
830 | XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0) | |
831 | ||
832 | #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ | |
833 | XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1) | |
834 | ||
835 | /* A C expression that is nonzero if REGNO is the number of a hard | |
836 | register in which the values of called function may come back. A | |
837 | register whose use for returning values is limited to serving as | |
838 | the second of a pair (for a value of type 'double', say) need not | |
839 | be recognized by this macro. If the machine has register windows, | |
840 | so that the caller and the called function use different registers | |
841 | for the return value, this macro should recognize only the caller's | |
842 | register numbers. */ | |
843 | #define FUNCTION_VALUE_REGNO_P(N) \ | |
844 | ((N) == GP_RETURN) | |
845 | ||
846 | /* A C expression that is nonzero if REGNO is the number of a hard | |
847 | register in which function arguments are sometimes passed. This | |
848 | does *not* include implicit arguments such as the static chain and | |
849 | the structure-value address. On many machines, no registers can be | |
850 | used for this purpose since all function arguments are pushed on | |
851 | the stack. */ | |
852 | #define FUNCTION_ARG_REGNO_P(N) \ | |
853 | ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST) | |
854 | ||
f6b7ba2b | 855 | /* Define a data type for recording info about an argument list |
856 | during the scan of that argument list. This data type should | |
857 | hold all necessary information about the function itself | |
858 | and about the args processed so far, enough to enable macros | |
859 | such as FUNCTION_ARG to determine where the next arg should go. */ | |
860 | typedef struct xtensa_args { | |
861 | int arg_words; /* # total words the arguments take */ | |
862 | } CUMULATIVE_ARGS; | |
863 | ||
864 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
865 | for a call to a function whose data type is FNTYPE. | |
866 | For a library call, FNTYPE is 0. */ | |
867 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ | |
868 | init_cumulative_args (&CUM, FNTYPE, LIBNAME) | |
869 | ||
870 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ | |
871 | init_cumulative_args (&CUM, FNTYPE, LIBNAME) | |
872 | ||
873 | /* Update the data in CUM to advance over an argument | |
874 | of mode MODE and data type TYPE. | |
875 | (TYPE is null for libcalls where that information may not be available.) */ | |
876 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
877 | function_arg_advance (&CUM, MODE, TYPE) | |
878 | ||
879 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
880 | function_arg (&CUM, MODE, TYPE, FALSE) | |
881 | ||
882 | #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ | |
883 | function_arg (&CUM, MODE, TYPE, TRUE) | |
884 | ||
885 | /* Arguments are never passed partly in memory and partly in registers. */ | |
886 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0) | |
887 | ||
888 | /* Specify function argument alignment. */ | |
889 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
890 | ((TYPE) != 0 \ | |
891 | ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \ | |
892 | ? PARM_BOUNDARY \ | |
893 | : TYPE_ALIGN (TYPE)) \ | |
894 | : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \ | |
895 | ? PARM_BOUNDARY \ | |
896 | : GET_MODE_ALIGNMENT (MODE))) | |
897 | ||
898 | ||
899 | /* Nonzero if we do not know how to pass TYPE solely in registers. | |
900 | We cannot do so in the following cases: | |
901 | ||
902 | - if the type has variable size | |
903 | - if the type is marked as addressable (it is required to be constructed | |
904 | into the stack) | |
905 | ||
906 | This differs from the default in that it does not check if the padding | |
907 | and mode of the type are such that a copy into a register would put it | |
908 | into the wrong part of the register. */ | |
909 | ||
910 | #define MUST_PASS_IN_STACK(MODE, TYPE) \ | |
911 | ((TYPE) != 0 \ | |
912 | && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ | |
913 | || TREE_ADDRESSABLE (TYPE))) | |
914 | ||
f5a4bf2f | 915 | /* Profiling Xtensa code is typically done with the built-in profiling |
916 | feature of Tensilica's instruction set simulator, which does not | |
917 | require any compiler support. Profiling code on a real (i.e., | |
918 | non-simulated) Xtensa processor is currently only supported by | |
919 | GNU/Linux with glibc. The glibc version of _mcount doesn't require | |
920 | counter variables. The _mcount function needs the current PC and | |
921 | the current return address to identify an arc in the call graph. | |
922 | Pass the current return address as the first argument; the current | |
923 | PC is available as a0 in _mcount's register window. Both of these | |
924 | values contain window size information in the two most significant | |
925 | bits; we assume that _mcount will mask off those bits. The call to | |
926 | _mcount uses a window size of 8 to make sure that it doesn't clobber | |
f6b7ba2b | 927 | any incoming argument values. */ |
928 | ||
f5a4bf2f | 929 | #define NO_PROFILE_COUNTERS |
930 | ||
931 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
f6b7ba2b | 932 | do { \ |
f5a4bf2f | 933 | fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \ |
934 | if (flag_pic) \ | |
935 | { \ | |
936 | fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \ | |
937 | fprintf (FILE, "\tcallx8\ta8\n"); \ | |
938 | } \ | |
939 | else \ | |
940 | fprintf (FILE, "\tcall8\t_mcount\n"); \ | |
941 | } while (0) | |
f6b7ba2b | 942 | |
943 | /* Stack pointer value doesn't matter at exit. */ | |
944 | #define EXIT_IGNORE_STACK 1 | |
945 | ||
946 | /* A C statement to output, on the stream FILE, assembler code for a | |
947 | block of data that contains the constant parts of a trampoline. | |
948 | This code should not include a label--the label is taken care of | |
949 | automatically. | |
950 | ||
951 | For Xtensa, the trampoline must perform an entry instruction with a | |
952 | minimal stack frame in order to get some free registers. Once the | |
953 | actual call target is known, the proper stack frame size is extracted | |
954 | from the entry instruction at the target and the current frame is | |
955 | adjusted to match. The trampoline then transfers control to the | |
956 | instruction following the entry at the target. Note: this assumes | |
957 | that the target begins with an entry instruction. */ | |
958 | ||
959 | /* minimum frame = reg save area (4 words) plus static chain (1 word) | |
960 | and the total number of words must be a multiple of 128 bits */ | |
961 | #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD) | |
962 | ||
963 | #define TRAMPOLINE_TEMPLATE(STREAM) \ | |
964 | do { \ | |
965 | fprintf (STREAM, "\t.begin no-generics\n"); \ | |
966 | fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); \ | |
967 | \ | |
968 | /* GCC isn't prepared to deal with data at the beginning of the \ | |
969 | trampoline, and the Xtensa l32r instruction requires that the \ | |
970 | constant pool be located before the code. We put the constant \ | |
971 | pool in the middle of the trampoline and jump around it. */ \ | |
972 | \ | |
973 | fprintf (STREAM, "\tj\t.Lskipconsts\n"); \ | |
974 | fprintf (STREAM, "\t.align\t4\n"); \ | |
975 | fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); \ | |
976 | fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); \ | |
977 | fprintf (STREAM, ".Lskipconsts:\n"); \ | |
978 | \ | |
979 | /* store the static chain */ \ | |
980 | fprintf (STREAM, "\tl32r\ta8, .Lchainval\n"); \ | |
981 | fprintf (STREAM, "\ts32i\ta8, sp, %d\n", \ | |
982 | MIN_FRAME_SIZE - (5 * UNITS_PER_WORD)); \ | |
983 | \ | |
984 | /* set the proper stack pointer value */ \ | |
985 | fprintf (STREAM, "\tl32r\ta8, .Lfnaddr\n"); \ | |
986 | fprintf (STREAM, "\tl32i\ta9, a8, 0\n"); \ | |
987 | fprintf (STREAM, "\textui\ta9, a9, %d, 12\n", \ | |
988 | TARGET_BIG_ENDIAN ? 8 : 12); \ | |
989 | fprintf (STREAM, "\tslli\ta9, a9, 3\n"); \ | |
990 | fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); \ | |
991 | fprintf (STREAM, "\tsub\ta9, sp, a9\n"); \ | |
992 | fprintf (STREAM, "\tmovsp\tsp, a9\n"); \ | |
993 | \ | |
994 | /* jump to the instruction following the entry */ \ | |
995 | fprintf (STREAM, "\taddi\ta8, a8, 3\n"); \ | |
996 | fprintf (STREAM, "\tjx\ta8\n"); \ | |
997 | fprintf (STREAM, "\t.end no-generics\n"); \ | |
998 | } while (0) | |
999 | ||
1000 | /* Size in bytes of the trampoline, as an integer. */ | |
1001 | #define TRAMPOLINE_SIZE 49 | |
1002 | ||
1003 | /* Alignment required for trampolines, in bits. */ | |
1004 | #define TRAMPOLINE_ALIGNMENT (32) | |
1005 | ||
1006 | /* A C statement to initialize the variable parts of a trampoline. */ | |
1007 | #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \ | |
1008 | do { \ | |
1009 | rtx addr = ADDR; \ | |
1010 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 8)), FUNC); \ | |
1011 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \ | |
1012 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__xtensa_sync_caches"), \ | |
1013 | 0, VOIDmode, 1, addr, Pmode); \ | |
1014 | } while (0) | |
1015 | ||
1016 | /* Define the `__builtin_va_list' type for the ABI. */ | |
1017 | #define BUILD_VA_LIST_TYPE(VALIST) \ | |
1018 | (VALIST) = xtensa_build_va_list () | |
1019 | ||
1020 | /* If defined, is a C expression that produces the machine-specific | |
1021 | code for a call to '__builtin_saveregs'. This code will be moved | |
1022 | to the very beginning of the function, before any parameter access | |
1023 | are made. The return value of this function should be an RTX that | |
1024 | contains the value to use as the return of '__builtin_saveregs'. */ | |
1025 | #define EXPAND_BUILTIN_SAVEREGS \ | |
1026 | xtensa_builtin_saveregs | |
1027 | ||
1028 | /* Implement `va_start' for varargs and stdarg. */ | |
7df226a2 | 1029 | #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ |
1030 | xtensa_va_start (valist, nextarg) | |
f6b7ba2b | 1031 | |
1032 | /* Implement `va_arg'. */ | |
1033 | #define EXPAND_BUILTIN_VA_ARG(valist, type) \ | |
1034 | xtensa_va_arg (valist, type) | |
1035 | ||
1036 | /* If defined, a C expression that produces the machine-specific code | |
1037 | to setup the stack so that arbitrary frames can be accessed. | |
1038 | ||
1039 | On Xtensa, a stack back-trace must always begin from the stack pointer, | |
1040 | so that the register overflow save area can be located. However, the | |
1041 | stack-walking code in GCC always begins from the hard_frame_pointer | |
1042 | register, not the stack pointer. The frame pointer is usually equal | |
1043 | to the stack pointer, but the __builtin_return_address and | |
1044 | __builtin_frame_address functions will not work if count > 0 and | |
1045 | they are called from a routine that uses alloca. These functions | |
1046 | are not guaranteed to work at all if count > 0 so maybe that is OK. | |
1047 | ||
1048 | A nicer solution would be to allow the architecture-specific files to | |
1049 | specify whether to start from the stack pointer or frame pointer. That | |
1050 | would also allow us to skip the machine->accesses_prev_frame stuff that | |
1051 | we currently need to ensure that there is a frame pointer when these | |
1052 | builtin functions are used. */ | |
1053 | ||
43326cf7 | 1054 | #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses |
f6b7ba2b | 1055 | |
1056 | /* A C expression whose value is RTL representing the address in a | |
1057 | stack frame where the pointer to the caller's frame is stored. | |
1058 | Assume that FRAMEADDR is an RTL expression for the address of the | |
1059 | stack frame itself. | |
1060 | ||
1061 | For Xtensa, there is no easy way to get the frame pointer if it is | |
1062 | not equivalent to the stack pointer. Moreover, the result of this | |
1063 | macro is used for continuing to walk back up the stack, so it must | |
1064 | return the stack pointer address. Thus, there is some inconsistency | |
1065 | here in that __builtin_frame_address will return the frame pointer | |
1066 | when count == 0 and the stack pointer when count > 0. */ | |
1067 | ||
1068 | #define DYNAMIC_CHAIN_ADDRESS(frame) \ | |
1069 | gen_rtx (PLUS, Pmode, frame, \ | |
1070 | gen_rtx_CONST_INT (VOIDmode, -3 * UNITS_PER_WORD)) | |
1071 | ||
1072 | /* Define this if the return address of a particular stack frame is | |
1073 | accessed from the frame pointer of the previous stack frame. */ | |
1074 | #define RETURN_ADDR_IN_PREVIOUS_FRAME | |
1075 | ||
1076 | /* A C expression whose value is RTL representing the value of the | |
1077 | return address for the frame COUNT steps up from the current | |
43326cf7 | 1078 | frame, after the prologue. */ |
1079 | #define RETURN_ADDR_RTX xtensa_return_addr | |
f6b7ba2b | 1080 | |
1081 | /* Addressing modes, and classification of registers for them. */ | |
1082 | ||
1083 | /* C expressions which are nonzero if register number NUM is suitable | |
1084 | for use as a base or index register in operand addresses. It may | |
1085 | be either a suitable hard register or a pseudo register that has | |
1086 | been allocated such a hard register. The difference between an | |
1087 | index register and a base register is that the index register may | |
1088 | be scaled. */ | |
1089 | ||
1090 | #define REGNO_OK_FOR_BASE_P(NUM) \ | |
1091 | (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM])) | |
1092 | ||
1093 | #define REGNO_OK_FOR_INDEX_P(NUM) 0 | |
1094 | ||
1095 | /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is | |
1096 | valid for use as a base or index register. For hard registers, it | |
1097 | should always accept those which the hardware permits and reject | |
1098 | the others. Whether the macro accepts or rejects pseudo registers | |
1099 | must be controlled by `REG_OK_STRICT'. This usually requires two | |
1100 | variant definitions, of which `REG_OK_STRICT' controls the one | |
1101 | actually used. The difference between an index register and a base | |
1102 | register is that the index register may be scaled. */ | |
1103 | ||
1104 | #ifdef REG_OK_STRICT | |
1105 | ||
1106 | #define REG_OK_FOR_INDEX_P(X) 0 | |
1107 | #define REG_OK_FOR_BASE_P(X) \ | |
1108 | REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1109 | ||
1110 | #else /* !REG_OK_STRICT */ | |
1111 | ||
1112 | #define REG_OK_FOR_INDEX_P(X) 0 | |
1113 | #define REG_OK_FOR_BASE_P(X) \ | |
1114 | ((REGNO (X) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (REGNO (X)))) | |
1115 | ||
1116 | #endif /* !REG_OK_STRICT */ | |
1117 | ||
1118 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1119 | #define MAX_REGS_PER_ADDRESS 1 | |
1120 | ||
1121 | /* Identify valid Xtensa addresses. */ | |
7ad1c420 | 1122 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, ADDR, LABEL) \ |
f6b7ba2b | 1123 | do { \ |
7ad1c420 | 1124 | rtx xinsn = (ADDR); \ |
f6b7ba2b | 1125 | \ |
1126 | /* allow constant pool addresses */ \ | |
1127 | if ((MODE) != BLKmode && GET_MODE_SIZE (MODE) >= UNITS_PER_WORD \ | |
1128 | && constantpool_address_p (xinsn)) \ | |
7ad1c420 | 1129 | goto LABEL; \ |
f6b7ba2b | 1130 | \ |
1131 | while (GET_CODE (xinsn) == SUBREG) \ | |
1132 | xinsn = SUBREG_REG (xinsn); \ | |
1133 | \ | |
1134 | /* allow base registers */ \ | |
1135 | if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \ | |
7ad1c420 | 1136 | goto LABEL; \ |
f6b7ba2b | 1137 | \ |
1138 | /* check for "register + offset" addressing */ \ | |
1139 | if (GET_CODE (xinsn) == PLUS) \ | |
1140 | { \ | |
1141 | rtx xplus0 = XEXP (xinsn, 0); \ | |
1142 | rtx xplus1 = XEXP (xinsn, 1); \ | |
1143 | enum rtx_code code0; \ | |
1144 | enum rtx_code code1; \ | |
1145 | \ | |
1146 | while (GET_CODE (xplus0) == SUBREG) \ | |
1147 | xplus0 = SUBREG_REG (xplus0); \ | |
1148 | code0 = GET_CODE (xplus0); \ | |
1149 | \ | |
1150 | while (GET_CODE (xplus1) == SUBREG) \ | |
1151 | xplus1 = SUBREG_REG (xplus1); \ | |
1152 | code1 = GET_CODE (xplus1); \ | |
1153 | \ | |
1154 | /* swap operands if necessary so the register is first */ \ | |
1155 | if (code0 != REG && code1 == REG) \ | |
1156 | { \ | |
1157 | xplus0 = XEXP (xinsn, 1); \ | |
1158 | xplus1 = XEXP (xinsn, 0); \ | |
1159 | code0 = GET_CODE (xplus0); \ | |
1160 | code1 = GET_CODE (xplus1); \ | |
1161 | } \ | |
1162 | \ | |
1163 | if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \ | |
1164 | && code1 == CONST_INT \ | |
1165 | && xtensa_mem_offset (INTVAL (xplus1), (MODE))) \ | |
1166 | { \ | |
7ad1c420 | 1167 | goto LABEL; \ |
f6b7ba2b | 1168 | } \ |
1169 | } \ | |
1170 | } while (0) | |
1171 | ||
1172 | /* A C expression that is 1 if the RTX X is a constant which is a | |
1173 | valid address. This is defined to be the same as 'CONSTANT_P (X)', | |
1174 | but rejecting CONST_DOUBLE. */ | |
1175 | #define CONSTANT_ADDRESS_P(X) \ | |
1176 | ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1177 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ | |
1178 | || (GET_CODE (X) == CONST))) | |
1179 | ||
1180 | /* Nonzero if the constant value X is a legitimate general operand. | |
1181 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1182 | #define LEGITIMATE_CONSTANT_P(X) 1 | |
1183 | ||
1184 | /* A C expression that is nonzero if X is a legitimate immediate | |
1185 | operand on the target machine when generating position independent | |
1186 | code. */ | |
1187 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
1188 | ((GET_CODE (X) != SYMBOL_REF || SYMBOL_REF_FLAG (X)) \ | |
1189 | && GET_CODE (X) != LABEL_REF \ | |
1190 | && GET_CODE (X) != CONST) | |
1191 | ||
1192 | /* Tell GCC how to use ADDMI to generate addresses. */ | |
1193 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ | |
1194 | do { \ | |
1195 | rtx xinsn = (X); \ | |
1196 | if (GET_CODE (xinsn) == PLUS) \ | |
1197 | { \ | |
1198 | rtx plus0 = XEXP (xinsn, 0); \ | |
1199 | rtx plus1 = XEXP (xinsn, 1); \ | |
1200 | \ | |
1201 | if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) \ | |
1202 | { \ | |
1203 | plus0 = XEXP (xinsn, 1); \ | |
1204 | plus1 = XEXP (xinsn, 0); \ | |
1205 | } \ | |
1206 | \ | |
1207 | if (GET_CODE (plus0) == REG \ | |
1208 | && GET_CODE (plus1) == CONST_INT \ | |
1209 | && !xtensa_mem_offset (INTVAL (plus1), MODE) \ | |
1210 | && !xtensa_simm8 (INTVAL (plus1)) \ | |
1211 | && xtensa_mem_offset (INTVAL (plus1) & 0xff, MODE) \ | |
1212 | && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) \ | |
1213 | { \ | |
1214 | rtx temp = gen_reg_rtx (Pmode); \ | |
1215 | emit_insn (gen_rtx (SET, Pmode, temp, \ | |
1216 | gen_rtx (PLUS, Pmode, plus0, \ | |
1217 | GEN_INT (INTVAL (plus1) & ~0xff)))); \ | |
1218 | (X) = gen_rtx (PLUS, Pmode, temp, \ | |
1219 | GEN_INT (INTVAL (plus1) & 0xff)); \ | |
1220 | goto WIN; \ | |
1221 | } \ | |
1222 | } \ | |
1223 | } while (0) | |
1224 | ||
1225 | ||
7ad1c420 | 1226 | /* Treat constant-pool references as "mode dependent" since they can |
1227 | only be accessed with SImode loads. This works around a bug in the | |
1228 | combiner where a constant pool reference is temporarily converted | |
1229 | to an HImode load, which is then assumed to zero-extend based on | |
1230 | our definition of LOAD_EXTEND_OP. This is wrong because the high | |
1231 | bits of a 16-bit value in the constant pool are now sign-extended | |
1232 | by default. */ | |
1233 | ||
1234 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ | |
1235 | do { \ | |
1236 | if (constantpool_address_p (ADDR)) \ | |
1237 | goto LABEL; \ | |
1238 | } while (0) | |
f6b7ba2b | 1239 | |
f6b7ba2b | 1240 | /* Specify the machine mode that this machine uses |
1241 | for the index in the tablejump instruction. */ | |
1242 | #define CASE_VECTOR_MODE (SImode) | |
1243 | ||
1244 | /* Define this if the tablejump instruction expects the table | |
1245 | to contain offsets from the address of the table. | |
1246 | Do not define this if the table should contain absolute addresses. */ | |
1247 | /* #define CASE_VECTOR_PC_RELATIVE */ | |
1248 | ||
f6b7ba2b | 1249 | /* Define this as 1 if 'char' should by default be signed; else as 0. */ |
1250 | #define DEFAULT_SIGNED_CHAR 0 | |
1251 | ||
1252 | /* Max number of bytes we can move from memory to memory | |
1253 | in one reasonably fast instruction. */ | |
1254 | #define MOVE_MAX 4 | |
1255 | #define MAX_MOVE_MAX 4 | |
1256 | ||
1257 | /* Prefer word-sized loads. */ | |
1258 | #define SLOW_BYTE_ACCESS 1 | |
1259 | ||
1260 | /* Xtensa doesn't have any instructions that set integer values based on the | |
1261 | results of comparisons, but the simplification code in the combiner also | |
1262 | uses this macro. The value should be either 1 or -1 to enable some | |
1263 | optimizations in the combiner; I'm not sure which is better for us. | |
1264 | Since we've been using 1 for a while, it should probably stay that way for | |
1265 | compatibility. */ | |
1266 | #define STORE_FLAG_VALUE 1 | |
1267 | ||
1268 | /* Shift instructions ignore all but the low-order few bits. */ | |
1269 | #define SHIFT_COUNT_TRUNCATED 1 | |
1270 | ||
1271 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1272 | is done just by pretending it is already truncated. */ | |
1273 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1274 | ||
1275 | /* Specify the machine mode that pointers have. | |
1276 | After generation of rtl, the compiler makes no further distinction | |
1277 | between pointers and any other objects of this machine mode. */ | |
1278 | #define Pmode SImode | |
1279 | ||
1280 | /* A function address in a call instruction is a word address (for | |
1281 | indexing purposes) so give the MEM rtx a words's mode. */ | |
1282 | #define FUNCTION_MODE SImode | |
1283 | ||
f6b7ba2b | 1284 | /* Xtensa constant costs. */ |
1285 | #define CONST_COSTS(X, CODE, OUTER_CODE) \ | |
1286 | case CONST_INT: \ | |
1287 | switch (OUTER_CODE) \ | |
1288 | { \ | |
1289 | case SET: \ | |
1290 | if (xtensa_simm12b (INTVAL (X))) return 4; \ | |
1291 | break; \ | |
1292 | case PLUS: \ | |
1293 | if (xtensa_simm8 (INTVAL (X))) return 0; \ | |
1294 | if (xtensa_simm8x256 (INTVAL (X))) return 0; \ | |
1295 | break; \ | |
1296 | case AND: \ | |
1297 | if (xtensa_mask_immediate (INTVAL (X))) return 0; \ | |
1298 | break; \ | |
1299 | case COMPARE: \ | |
1300 | if ((INTVAL (X) == 0) || xtensa_b4const (INTVAL (X))) return 0; \ | |
1301 | break; \ | |
1302 | case ASHIFT: \ | |
1303 | case ASHIFTRT: \ | |
1304 | case LSHIFTRT: \ | |
1305 | case ROTATE: \ | |
1306 | case ROTATERT: \ | |
1307 | /* no way to tell if X is the 2nd operand so be conservative */ \ | |
1308 | default: break; \ | |
1309 | } \ | |
1310 | if (xtensa_simm12b (INTVAL (X))) return 5; \ | |
1311 | return 6; \ | |
1312 | case CONST: \ | |
1313 | case LABEL_REF: \ | |
1314 | case SYMBOL_REF: \ | |
1315 | return 5; \ | |
1316 | case CONST_DOUBLE: \ | |
1317 | return 7; | |
1318 | ||
1319 | /* Costs of various Xtensa operations. */ | |
1320 | #define RTX_COSTS(X, CODE, OUTER_CODE) \ | |
1321 | case MEM: \ | |
1322 | { \ | |
1323 | int num_words = \ | |
1324 | (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \ | |
1325 | if (memory_address_p (GET_MODE (X), XEXP ((X), 0))) \ | |
1326 | return COSTS_N_INSNS (num_words); \ | |
1327 | \ | |
1328 | return COSTS_N_INSNS (2*num_words); \ | |
1329 | } \ | |
1330 | \ | |
1331 | case FFS: \ | |
1332 | return COSTS_N_INSNS (TARGET_NSA ? 5 : 50); \ | |
1333 | \ | |
1334 | case NOT: \ | |
1335 | return COSTS_N_INSNS ((GET_MODE (X) == DImode) ? 3 : 2); \ | |
1336 | \ | |
1337 | case AND: \ | |
1338 | case IOR: \ | |
1339 | case XOR: \ | |
1340 | if (GET_MODE (X) == DImode) return COSTS_N_INSNS (2); \ | |
1341 | return COSTS_N_INSNS (1); \ | |
1342 | \ | |
1343 | case ASHIFT: \ | |
1344 | case ASHIFTRT: \ | |
1345 | case LSHIFTRT: \ | |
1346 | if (GET_MODE (X) == DImode) return COSTS_N_INSNS (50); \ | |
1347 | return COSTS_N_INSNS (1); \ | |
1348 | \ | |
1349 | case ABS: \ | |
1350 | { \ | |
1351 | enum machine_mode xmode = GET_MODE (X); \ | |
1352 | if (xmode == SFmode) \ | |
1353 | return COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); \ | |
1354 | if (xmode == DFmode) \ | |
1355 | return COSTS_N_INSNS (50); \ | |
1356 | return COSTS_N_INSNS (4); \ | |
1357 | } \ | |
1358 | \ | |
1359 | case PLUS: \ | |
1360 | case MINUS: \ | |
1361 | { \ | |
1362 | enum machine_mode xmode = GET_MODE (X); \ | |
1363 | if (xmode == SFmode) \ | |
1364 | return COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); \ | |
1365 | if (xmode == DFmode || xmode == DImode) \ | |
1366 | return COSTS_N_INSNS (50); \ | |
1367 | return COSTS_N_INSNS (1); \ | |
1368 | } \ | |
1369 | \ | |
1370 | case NEG: \ | |
1371 | return COSTS_N_INSNS ((GET_MODE (X) == DImode) ? 4 : 2); \ | |
1372 | \ | |
1373 | case MULT: \ | |
1374 | { \ | |
1375 | enum machine_mode xmode = GET_MODE (X); \ | |
1376 | if (xmode == SFmode) \ | |
1377 | return COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50); \ | |
1378 | if (xmode == DFmode || xmode == DImode) \ | |
1379 | return COSTS_N_INSNS (50); \ | |
1380 | if (TARGET_MUL32) \ | |
1381 | return COSTS_N_INSNS (4); \ | |
1382 | if (TARGET_MAC16) \ | |
1383 | return COSTS_N_INSNS (16); \ | |
1384 | if (TARGET_MUL16) \ | |
1385 | return COSTS_N_INSNS (12); \ | |
1386 | return COSTS_N_INSNS (50); \ | |
1387 | } \ | |
1388 | \ | |
1389 | case DIV: \ | |
1390 | case MOD: \ | |
1391 | { \ | |
1392 | enum machine_mode xmode = GET_MODE (X); \ | |
1393 | if (xmode == SFmode) \ | |
1394 | return COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50); \ | |
1395 | if (xmode == DFmode) \ | |
1396 | return COSTS_N_INSNS (50); \ | |
1397 | } \ | |
1398 | /* fall through */ \ | |
1399 | \ | |
1400 | case UDIV: \ | |
1401 | case UMOD: \ | |
1402 | { \ | |
1403 | enum machine_mode xmode = GET_MODE (X); \ | |
1404 | if (xmode == DImode) \ | |
1405 | return COSTS_N_INSNS (50); \ | |
1406 | if (TARGET_DIV32) \ | |
1407 | return COSTS_N_INSNS (32); \ | |
1408 | return COSTS_N_INSNS (50); \ | |
1409 | } \ | |
1410 | \ | |
1411 | case SQRT: \ | |
1412 | if (GET_MODE (X) == SFmode) \ | |
1413 | return COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50); \ | |
1414 | return COSTS_N_INSNS (50); \ | |
1415 | \ | |
1416 | case SMIN: \ | |
1417 | case UMIN: \ | |
1418 | case SMAX: \ | |
1419 | case UMAX: \ | |
1420 | return COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50); \ | |
1421 | \ | |
1422 | case SIGN_EXTRACT: \ | |
1423 | case SIGN_EXTEND: \ | |
1424 | return COSTS_N_INSNS (TARGET_SEXT ? 1 : 2); \ | |
1425 | \ | |
1426 | case ZERO_EXTRACT: \ | |
1427 | case ZERO_EXTEND: \ | |
1428 | return COSTS_N_INSNS (1); | |
1429 | ||
1430 | ||
1431 | /* An expression giving the cost of an addressing mode that | |
1432 | contains ADDRESS. */ | |
1433 | #define ADDRESS_COST(ADDR) 1 | |
1434 | ||
1435 | /* A C expression for the cost of moving data from a register in | |
1436 | class FROM to one in class TO. The classes are expressed using | |
1437 | the enumeration values such as 'GENERAL_REGS'. A value of 2 is | |
1438 | the default; other values are interpreted relative to that. */ | |
1439 | #define REGISTER_MOVE_COST(MODE, FROM, TO) \ | |
1440 | (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \ | |
1441 | ? 2 \ | |
1442 | : (reg_class_subset_p ((FROM), AR_REGS) \ | |
1443 | && reg_class_subset_p ((TO), AR_REGS) \ | |
1444 | ? 2 \ | |
1445 | : (reg_class_subset_p ((FROM), AR_REGS) \ | |
1446 | && (TO) == ACC_REG \ | |
1447 | ? 3 \ | |
1448 | : ((FROM) == ACC_REG \ | |
1449 | && reg_class_subset_p ((TO), AR_REGS) \ | |
1450 | ? 3 \ | |
1451 | : 10)))) | |
1452 | ||
1453 | #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4 | |
1454 | ||
1455 | #define BRANCH_COST 3 | |
1456 | ||
1457 | /* Optionally define this if you have added predicates to | |
1458 | 'MACHINE.c'. This macro is called within an initializer of an | |
1459 | array of structures. The first field in the structure is the | |
1460 | name of a predicate and the second field is an array of rtl | |
1461 | codes. For each predicate, list all rtl codes that can be in | |
1462 | expressions matched by the predicate. The list should have a | |
1463 | trailing comma. */ | |
1464 | ||
1465 | #define PREDICATE_CODES \ | |
1466 | {"add_operand", { REG, CONST_INT, SUBREG }}, \ | |
1467 | {"arith_operand", { REG, CONST_INT, SUBREG }}, \ | |
1468 | {"nonimmed_operand", { REG, SUBREG, MEM }}, \ | |
f6b7ba2b | 1469 | {"mem_operand", { MEM }}, \ |
1470 | {"mask_operand", { REG, CONST_INT, SUBREG }}, \ | |
1471 | {"extui_fldsz_operand", { CONST_INT }}, \ | |
1472 | {"sext_fldsz_operand", { CONST_INT }}, \ | |
1473 | {"lsbitnum_operand", { CONST_INT }}, \ | |
1474 | {"fpmem_offset_operand", { CONST_INT }}, \ | |
1475 | {"sext_operand", { REG, SUBREG, MEM }}, \ | |
1476 | {"branch_operand", { REG, CONST_INT, SUBREG }}, \ | |
1477 | {"ubranch_operand", { REG, CONST_INT, SUBREG }}, \ | |
1478 | {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG }}, \ | |
1479 | {"move_operand", { REG, SUBREG, MEM, CONST_INT, CONST_DOUBLE, \ | |
1480 | CONST, SYMBOL_REF, LABEL_REF }}, \ | |
1481 | {"non_const_move_operand", { REG, SUBREG, MEM }}, \ | |
1482 | {"const_float_1_operand", { CONST_DOUBLE }}, \ | |
1483 | {"branch_operator", { EQ, NE, LT, GE }}, \ | |
1484 | {"ubranch_operator", { LTU, GEU }}, \ | |
1485 | {"boolean_operator", { EQ, NE }}, | |
1486 | ||
1487 | /* Control the assembler format that we output. */ | |
1488 | ||
1489 | /* How to refer to registers in assembler output. | |
1490 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1491 | #define REGISTER_NAMES \ | |
1492 | { \ | |
1493 | "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \ | |
1494 | "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \ | |
1495 | "fp", "argp", "b0", \ | |
1496 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
1497 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ | |
1498 | "acc" \ | |
1499 | } | |
1500 | ||
1501 | /* If defined, a C initializer for an array of structures containing a | |
1502 | name and a register number. This macro defines additional names | |
1503 | for hard registers, thus allowing the 'asm' option in declarations | |
1504 | to refer to registers using alternate names. */ | |
1505 | #define ADDITIONAL_REGISTER_NAMES \ | |
1506 | { \ | |
1507 | { "a1", 1 + GP_REG_FIRST } \ | |
1508 | } | |
1509 | ||
1510 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
1511 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
1512 | ||
1513 | /* Recognize machine-specific patterns that may appear within | |
1514 | constants. Used for PIC-specific UNSPECs. */ | |
1515 | #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \ | |
1516 | do { \ | |
1517 | if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \ | |
1518 | { \ | |
1519 | switch (XINT ((X), 1)) \ | |
1520 | { \ | |
1521 | case UNSPEC_PLT: \ | |
1522 | output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ | |
1523 | fputs ("@PLT", (STREAM)); \ | |
1524 | break; \ | |
1525 | default: \ | |
1526 | goto FAIL; \ | |
1527 | } \ | |
1528 | break; \ | |
1529 | } \ | |
1530 | else \ | |
1531 | goto FAIL; \ | |
1532 | } while (0) | |
1533 | ||
0036ad94 | 1534 | /* Globalizing directive for a label. */ |
1535 | #define GLOBAL_ASM_OP "\t.global\t" | |
f6b7ba2b | 1536 | |
1537 | /* This says how to define a global common symbol. */ | |
1538 | #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \ | |
1539 | xtensa_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE)) | |
1540 | ||
1541 | /* This says how to define a local common symbol (ie, not visible to | |
1542 | linker). */ | |
1543 | #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \ | |
1544 | xtensa_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE)) | |
1545 | ||
1546 | /* This is how to output an element of a case-vector that is absolute. */ | |
1547 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ | |
1548 | fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \ | |
1549 | LOCAL_LABEL_PREFIX, VALUE) | |
1550 | ||
1551 | /* This is how to output an element of a case-vector that is relative. | |
1552 | This is used for pc-relative code. */ | |
1553 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ | |
1554 | do { \ | |
1555 | fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \ | |
1556 | LOCAL_LABEL_PREFIX, (VALUE), \ | |
1557 | LOCAL_LABEL_PREFIX, (REL)); \ | |
1558 | } while (0) | |
1559 | ||
1560 | /* This is how to output an assembler line that says to advance the | |
1561 | location counter to a multiple of 2**LOG bytes. */ | |
1562 | #define ASM_OUTPUT_ALIGN(STREAM, LOG) \ | |
1563 | do { \ | |
1564 | if ((LOG) != 0) \ | |
1565 | fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \ | |
1566 | } while (0) | |
1567 | ||
1568 | /* Indicate that jump tables go in the text section. This is | |
1569 | necessary when compiling PIC code. */ | |
1570 | #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) | |
1571 | ||
1572 | ||
1573 | /* Define this macro for the rare case where the RTL needs some sort of | |
1574 | machine-dependent fixup immediately before register allocation is done. | |
1575 | ||
1576 | If the stack frame size is too big to fit in the immediate field of | |
1577 | the ENTRY instruction, we need to store the frame size in the | |
1578 | constant pool. However, the code in xtensa_function_prologue runs too | |
1579 | late to be able to add anything to the constant pool. Since the | |
1580 | final frame size isn't known until reload is complete, this seems | |
1581 | like the best place to do it. | |
1582 | ||
1583 | There may also be some fixup required if there is an incoming argument | |
1584 | in a7 and the function requires a frame pointer. */ | |
1585 | ||
1586 | #define MACHINE_DEPENDENT_REORG(INSN) xtensa_reorg (INSN) | |
1587 | ||
1588 | ||
1589 | /* Define the strings to put out for each section in the object file. */ | |
1590 | #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ | |
1591 | #define DATA_SECTION_ASM_OP "\t.data" /* large data */ | |
1592 | ||
1593 | ||
1594 | /* Define output to appear before the constant pool. If the function | |
1595 | has been assigned to a specific ELF section, or if it goes into a | |
1596 | unique section, set the name of that section to be the literal | |
1597 | prefix. */ | |
1598 | #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \ | |
1599 | do { \ | |
1600 | tree fnsection; \ | |
bbfbe351 | 1601 | resolve_unique_section ((FUNDECL), 0, flag_function_sections); \ |
f6b7ba2b | 1602 | fnsection = DECL_SECTION_NAME (FUNDECL); \ |
1603 | if (fnsection != NULL_TREE) \ | |
1604 | { \ | |
1605 | const char *fnsectname = TREE_STRING_POINTER (fnsection); \ | |
1606 | fprintf (FILE, "\t.begin\tliteral_prefix %s\n", \ | |
1607 | strcmp (fnsectname, ".text") ? fnsectname : ""); \ | |
1608 | } \ | |
9703ff3b | 1609 | if ((SIZE) > 0) \ |
efa381d9 | 1610 | { \ |
1611 | function_section (FUNDECL); \ | |
1612 | fprintf (FILE, "\t.literal_position\n"); \ | |
1613 | } \ | |
f6b7ba2b | 1614 | } while (0) |
1615 | ||
1616 | ||
1617 | /* Define code to write out the ".end literal_prefix" directive for a | |
1618 | function in a special section. This is appended to the standard ELF | |
1619 | code for ASM_DECLARE_FUNCTION_SIZE. */ | |
1620 | #define XTENSA_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ | |
1621 | if (DECL_SECTION_NAME (DECL) != NULL_TREE) \ | |
1622 | fprintf (FILE, "\t.end\tliteral_prefix\n") | |
1623 | ||
1624 | /* A C statement (with or without semicolon) to output a constant in | |
1625 | the constant pool, if it needs special treatment. */ | |
1626 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \ | |
1627 | do { \ | |
1628 | xtensa_output_literal (FILE, X, MODE, LABELNO); \ | |
1629 | goto JUMPTO; \ | |
1630 | } while (0) | |
1631 | ||
f6b7ba2b | 1632 | /* How to start an assembler comment. */ |
1633 | #define ASM_COMMENT_START "#" | |
1634 | ||
1635 | /* Exception handling TODO!! */ | |
1636 | #define DWARF_UNWIND_INFO 0 | |
1637 |