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7afe21cc | 1 | /* Common subexpression elimination for GNU compiler. |
aeee4812 | 2 | Copyright (C) 1987-2023 Free Software Foundation, Inc. |
7afe21cc | 3 | |
1322177d | 4 | This file is part of GCC. |
7afe21cc | 5 | |
1322177d LB |
6 | GCC is free software; you can redistribute it and/or modify it under |
7 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 8 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 9 | version. |
7afe21cc | 10 | |
1322177d LB |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
7afe21cc RK |
15 | |
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
7afe21cc | 19 | |
7afe21cc | 20 | #include "config.h" |
670ee920 | 21 | #include "system.h" |
4977bab6 | 22 | #include "coretypes.h" |
c7131fb2 | 23 | #include "backend.h" |
957060b5 | 24 | #include "target.h" |
7afe21cc | 25 | #include "rtl.h" |
957060b5 AM |
26 | #include "tree.h" |
27 | #include "cfghooks.h" | |
c7131fb2 | 28 | #include "df.h" |
4d0cdd0c | 29 | #include "memmodel.h" |
6baf1cc8 | 30 | #include "tm_p.h" |
957060b5 | 31 | #include "insn-config.h" |
7932a3db | 32 | #include "regs.h" |
957060b5 AM |
33 | #include "emit-rtl.h" |
34 | #include "recog.h" | |
60393bbc AM |
35 | #include "cfgrtl.h" |
36 | #include "cfganal.h" | |
37 | #include "cfgcleanup.h" | |
36566b39 | 38 | #include "alias.h" |
50b2596f | 39 | #include "toplev.h" |
2f93eea8 | 40 | #include "rtlhooks-def.h" |
ef330312 | 41 | #include "tree-pass.h" |
6fb5fa3c | 42 | #include "dbgcnt.h" |
e89b312e | 43 | #include "rtl-iter.h" |
311b62ce RS |
44 | #include "regs.h" |
45 | #include "function-abi.h" | |
8695bf78 | 46 | #include "rtlanal.h" |
68b48f3f | 47 | #include "expr.h" |
7afe21cc RK |
48 | |
49 | /* The basic idea of common subexpression elimination is to go | |
50 | through the code, keeping a record of expressions that would | |
51 | have the same value at the current scan point, and replacing | |
52 | expressions encountered with the cheapest equivalent expression. | |
53 | ||
54 | It is too complicated to keep track of the different possibilities | |
e48a7fbe JL |
55 | when control paths merge in this code; so, at each label, we forget all |
56 | that is known and start fresh. This can be described as processing each | |
57 | extended basic block separately. We have a separate pass to perform | |
58 | global CSE. | |
59 | ||
60 | Note CSE can turn a conditional or computed jump into a nop or | |
61 | an unconditional jump. When this occurs we arrange to run the jump | |
62 | optimizer after CSE to delete the unreachable code. | |
7afe21cc RK |
63 | |
64 | We use two data structures to record the equivalent expressions: | |
1bb98cec DM |
65 | a hash table for most expressions, and a vector of "quantity |
66 | numbers" to record equivalent (pseudo) registers. | |
7afe21cc RK |
67 | |
68 | The use of the special data structure for registers is desirable | |
69 | because it is faster. It is possible because registers references | |
70 | contain a fairly small number, the register number, taken from | |
71 | a contiguously allocated series, and two register references are | |
72 | identical if they have the same number. General expressions | |
73 | do not have any such thing, so the only way to retrieve the | |
74 | information recorded on an expression other than a register | |
75 | is to keep it in a hash table. | |
76 | ||
77 | Registers and "quantity numbers": | |
278a83b2 | 78 | |
7afe21cc RK |
79 | At the start of each basic block, all of the (hardware and pseudo) |
80 | registers used in the function are given distinct quantity | |
81 | numbers to indicate their contents. During scan, when the code | |
82 | copies one register into another, we copy the quantity number. | |
83 | When a register is loaded in any other way, we allocate a new | |
84 | quantity number to describe the value generated by this operation. | |
459281be | 85 | `REG_QTY (N)' records what quantity register N is currently thought |
7afe21cc RK |
86 | of as containing. |
87 | ||
08a69267 | 88 | All real quantity numbers are greater than or equal to zero. |
459281be | 89 | If register N has not been assigned a quantity, `REG_QTY (N)' will |
08a69267 | 90 | equal -N - 1, which is always negative. |
7afe21cc | 91 | |
08a69267 RS |
92 | Quantity numbers below zero do not exist and none of the `qty_table' |
93 | entries should be referenced with a negative index. | |
7afe21cc RK |
94 | |
95 | We also maintain a bidirectional chain of registers for each | |
1bb98cec DM |
96 | quantity number. The `qty_table` members `first_reg' and `last_reg', |
97 | and `reg_eqv_table' members `next' and `prev' hold these chains. | |
7afe21cc RK |
98 | |
99 | The first register in a chain is the one whose lifespan is least local. | |
100 | Among equals, it is the one that was seen first. | |
101 | We replace any equivalent register with that one. | |
102 | ||
103 | If two registers have the same quantity number, it must be true that | |
1bb98cec | 104 | REG expressions with qty_table `mode' must be in the hash table for both |
7afe21cc RK |
105 | registers and must be in the same class. |
106 | ||
107 | The converse is not true. Since hard registers may be referenced in | |
108 | any mode, two REG expressions might be equivalent in the hash table | |
109 | but not have the same quantity number if the quantity number of one | |
110 | of the registers is not the same mode as those expressions. | |
278a83b2 | 111 | |
7afe21cc RK |
112 | Constants and quantity numbers |
113 | ||
114 | When a quantity has a known constant value, that value is stored | |
1bb98cec | 115 | in the appropriate qty_table `const_rtx'. This is in addition to |
7afe21cc RK |
116 | putting the constant in the hash table as is usual for non-regs. |
117 | ||
d45cf215 | 118 | Whether a reg or a constant is preferred is determined by the configuration |
7afe21cc RK |
119 | macro CONST_COSTS and will often depend on the constant value. In any |
120 | event, expressions containing constants can be simplified, by fold_rtx. | |
121 | ||
122 | When a quantity has a known nearly constant value (such as an address | |
1bb98cec DM |
123 | of a stack slot), that value is stored in the appropriate qty_table |
124 | `const_rtx'. | |
7afe21cc RK |
125 | |
126 | Integer constants don't have a machine mode. However, cse | |
127 | determines the intended machine mode from the destination | |
128 | of the instruction that moves the constant. The machine mode | |
129 | is recorded in the hash table along with the actual RTL | |
130 | constant expression so that different modes are kept separate. | |
131 | ||
132 | Other expressions: | |
133 | ||
134 | To record known equivalences among expressions in general | |
135 | we use a hash table called `table'. It has a fixed number of buckets | |
136 | that contain chains of `struct table_elt' elements for expressions. | |
137 | These chains connect the elements whose expressions have the same | |
138 | hash codes. | |
139 | ||
140 | Other chains through the same elements connect the elements which | |
141 | currently have equivalent values. | |
142 | ||
143 | Register references in an expression are canonicalized before hashing | |
1bb98cec | 144 | the expression. This is done using `reg_qty' and qty_table `first_reg'. |
7afe21cc RK |
145 | The hash code of a register reference is computed using the quantity |
146 | number, not the register number. | |
147 | ||
148 | When the value of an expression changes, it is necessary to remove from the | |
149 | hash table not just that expression but all expressions whose values | |
150 | could be different as a result. | |
151 | ||
152 | 1. If the value changing is in memory, except in special cases | |
153 | ANYTHING referring to memory could be changed. That is because | |
154 | nobody knows where a pointer does not point. | |
155 | The function `invalidate_memory' removes what is necessary. | |
156 | ||
157 | The special cases are when the address is constant or is | |
158 | a constant plus a fixed register such as the frame pointer | |
159 | or a static chain pointer. When such addresses are stored in, | |
160 | we can tell exactly which other such addresses must be invalidated | |
161 | due to overlap. `invalidate' does this. | |
162 | All expressions that refer to non-constant | |
163 | memory addresses are also invalidated. `invalidate_memory' does this. | |
164 | ||
165 | 2. If the value changing is a register, all expressions | |
166 | containing references to that register, and only those, | |
167 | must be removed. | |
168 | ||
169 | Because searching the entire hash table for expressions that contain | |
170 | a register is very slow, we try to figure out when it isn't necessary. | |
171 | Precisely, this is necessary only when expressions have been | |
172 | entered in the hash table using this register, and then the value has | |
173 | changed, and then another expression wants to be added to refer to | |
174 | the register's new value. This sequence of circumstances is rare | |
175 | within any one basic block. | |
176 | ||
459281be KH |
177 | `REG_TICK' and `REG_IN_TABLE', accessors for members of |
178 | cse_reg_info, are used to detect this case. REG_TICK (i) is | |
179 | incremented whenever a value is stored in register i. | |
180 | REG_IN_TABLE (i) holds -1 if no references to register i have been | |
181 | entered in the table; otherwise, it contains the value REG_TICK (i) | |
182 | had when the references were entered. If we want to enter a | |
183 | reference and REG_IN_TABLE (i) != REG_TICK (i), we must scan and | |
184 | remove old references. Until we want to enter a new entry, the | |
185 | mere fact that the two vectors don't match makes the entries be | |
186 | ignored if anyone tries to match them. | |
7afe21cc RK |
187 | |
188 | Registers themselves are entered in the hash table as well as in | |
459281be KH |
189 | the equivalent-register chains. However, `REG_TICK' and |
190 | `REG_IN_TABLE' do not apply to expressions which are simple | |
7afe21cc RK |
191 | register references. These expressions are removed from the table |
192 | immediately when they become invalid, and this can be done even if | |
193 | we do not immediately search for all the expressions that refer to | |
194 | the register. | |
195 | ||
196 | A CLOBBER rtx in an instruction invalidates its operand for further | |
197 | reuse. A CLOBBER or SET rtx whose operand is a MEM:BLK | |
198 | invalidates everything that resides in memory. | |
199 | ||
200 | Related expressions: | |
201 | ||
202 | Constant expressions that differ only by an additive integer | |
203 | are called related. When a constant expression is put in | |
204 | the table, the related expression with no constant term | |
205 | is also entered. These are made to point at each other | |
206 | so that it is possible to find out if there exists any | |
207 | register equivalent to an expression related to a given expression. */ | |
278a83b2 | 208 | |
1bb98cec DM |
209 | /* Length of qty_table vector. We know in advance we will not need |
210 | a quantity number this big. */ | |
7afe21cc RK |
211 | |
212 | static int max_qty; | |
213 | ||
214 | /* Next quantity number to be allocated. | |
215 | This is 1 + the largest number needed so far. */ | |
216 | ||
217 | static int next_qty; | |
218 | ||
1bb98cec | 219 | /* Per-qty information tracking. |
7afe21cc | 220 | |
1bb98cec DM |
221 | `first_reg' and `last_reg' track the head and tail of the |
222 | chain of registers which currently contain this quantity. | |
7afe21cc | 223 | |
1bb98cec | 224 | `mode' contains the machine mode of this quantity. |
7afe21cc | 225 | |
1bb98cec DM |
226 | `const_rtx' holds the rtx of the constant value of this |
227 | quantity, if known. A summations of the frame/arg pointer | |
228 | and a constant can also be entered here. When this holds | |
229 | a known value, `const_insn' is the insn which stored the | |
230 | constant value. | |
7afe21cc | 231 | |
1bb98cec DM |
232 | `comparison_{code,const,qty}' are used to track when a |
233 | comparison between a quantity and some constant or register has | |
234 | been passed. In such a case, we know the results of the comparison | |
235 | in case we see it again. These members record a comparison that | |
236 | is known to be true. `comparison_code' holds the rtx code of such | |
237 | a comparison, else it is set to UNKNOWN and the other two | |
238 | comparison members are undefined. `comparison_const' holds | |
239 | the constant being compared against, or zero if the comparison | |
240 | is not against a constant. `comparison_qty' holds the quantity | |
241 | being compared against when the result is known. If the comparison | |
242 | is not with a register, `comparison_qty' is -1. */ | |
7afe21cc | 243 | |
1bb98cec DM |
244 | struct qty_table_elem |
245 | { | |
246 | rtx const_rtx; | |
20468884 | 247 | rtx_insn *const_insn; |
1bb98cec DM |
248 | rtx comparison_const; |
249 | int comparison_qty; | |
770ae6cc | 250 | unsigned int first_reg, last_reg; |
b14af304 PL |
251 | ENUM_BITFIELD(machine_mode) mode : MACHINE_MODE_BITSIZE; |
252 | ENUM_BITFIELD(rtx_code) comparison_code : RTX_CODE_BITSIZE; | |
1bb98cec | 253 | }; |
7afe21cc | 254 | |
1bb98cec DM |
255 | /* The table of all qtys, indexed by qty number. */ |
256 | static struct qty_table_elem *qty_table; | |
7afe21cc | 257 | |
7afe21cc RK |
258 | /* Insn being scanned. */ |
259 | ||
20468884 | 260 | static rtx_insn *this_insn; |
f40751dd | 261 | static bool optimize_this_for_speed_p; |
7afe21cc | 262 | |
71d306d1 DE |
263 | /* Index by register number, gives the number of the next (or |
264 | previous) register in the chain of registers sharing the same | |
7afe21cc RK |
265 | value. |
266 | ||
267 | Or -1 if this register is at the end of the chain. | |
268 | ||
459281be | 269 | If REG_QTY (N) == -N - 1, reg_eqv_table[N].next is undefined. */ |
1bb98cec DM |
270 | |
271 | /* Per-register equivalence chain. */ | |
272 | struct reg_eqv_elem | |
273 | { | |
274 | int next, prev; | |
275 | }; | |
7afe21cc | 276 | |
1bb98cec DM |
277 | /* The table of all register equivalence chains. */ |
278 | static struct reg_eqv_elem *reg_eqv_table; | |
7afe21cc | 279 | |
14a774a9 RK |
280 | struct cse_reg_info |
281 | { | |
bc5e3b54 KH |
282 | /* The timestamp at which this register is initialized. */ |
283 | unsigned int timestamp; | |
9b1549b8 DM |
284 | |
285 | /* The quantity number of the register's current contents. */ | |
286 | int reg_qty; | |
287 | ||
288 | /* The number of times the register has been altered in the current | |
289 | basic block. */ | |
290 | int reg_tick; | |
291 | ||
30f72379 MM |
292 | /* The REG_TICK value at which rtx's containing this register are |
293 | valid in the hash table. If this does not equal the current | |
294 | reg_tick value, such expressions existing in the hash table are | |
295 | invalid. */ | |
296 | int reg_in_table; | |
46081bb3 SH |
297 | |
298 | /* The SUBREG that was set when REG_TICK was last incremented. Set | |
299 | to -1 if the last store was to the whole register, not a subreg. */ | |
5dd78e9a | 300 | unsigned int subreg_ticked; |
30f72379 | 301 | }; |
7afe21cc | 302 | |
bc5e3b54 | 303 | /* A table of cse_reg_info indexed by register numbers. */ |
f00822b2 | 304 | static struct cse_reg_info *cse_reg_info_table; |
c1edba58 | 305 | |
bc5e3b54 KH |
306 | /* The size of the above table. */ |
307 | static unsigned int cse_reg_info_table_size; | |
9b1549b8 | 308 | |
bc5e3b54 KH |
309 | /* The index of the first entry that has not been initialized. */ |
310 | static unsigned int cse_reg_info_table_first_uninitialized; | |
7afe21cc | 311 | |
bc5e3b54 | 312 | /* The timestamp at the beginning of the current run of |
932ad4d9 SB |
313 | cse_extended_basic_block. We increment this variable at the beginning of |
314 | the current run of cse_extended_basic_block. The timestamp field of a | |
bc5e3b54 KH |
315 | cse_reg_info entry matches the value of this variable if and only |
316 | if the entry has been initialized during the current run of | |
932ad4d9 | 317 | cse_extended_basic_block. */ |
bc5e3b54 | 318 | static unsigned int cse_reg_info_timestamp; |
7afe21cc | 319 | |
278a83b2 | 320 | /* A HARD_REG_SET containing all the hard registers for which there is |
7afe21cc RK |
321 | currently a REG expression in the hash table. Note the difference |
322 | from the above variables, which indicate if the REG is mentioned in some | |
323 | expression in the table. */ | |
324 | ||
325 | static HARD_REG_SET hard_regs_in_table; | |
326 | ||
2aac3a01 EB |
327 | /* True if CSE has altered the CFG. */ |
328 | static bool cse_cfg_altered; | |
7afe21cc | 329 | |
2aac3a01 EB |
330 | /* True if CSE has altered conditional jump insns in such a way |
331 | that jump optimization should be redone. */ | |
332 | static bool cse_jumps_altered; | |
7afe21cc | 333 | |
2aac3a01 EB |
334 | /* True if we put a LABEL_REF into the hash table for an INSN |
335 | without a REG_LABEL_OPERAND, we have to rerun jump after CSE | |
336 | to put in the note. */ | |
337 | static bool recorded_label_ref; | |
a5dfb4ee | 338 | |
bd1cd0d0 SB |
339 | /* canon_hash stores 1 in do_not_record if it notices a reference to PC or |
340 | some other volatile subexpression. */ | |
7afe21cc RK |
341 | |
342 | static int do_not_record; | |
343 | ||
344 | /* canon_hash stores 1 in hash_arg_in_memory | |
345 | if it notices a reference to memory within the expression being hashed. */ | |
346 | ||
347 | static int hash_arg_in_memory; | |
348 | ||
7afe21cc RK |
349 | /* The hash table contains buckets which are chains of `struct table_elt's, |
350 | each recording one expression's information. | |
351 | That expression is in the `exp' field. | |
352 | ||
db048faf MM |
353 | The canon_exp field contains a canonical (from the point of view of |
354 | alias analysis) version of the `exp' field. | |
355 | ||
7afe21cc RK |
356 | Those elements with the same hash code are chained in both directions |
357 | through the `next_same_hash' and `prev_same_hash' fields. | |
358 | ||
359 | Each set of expressions with equivalent values | |
360 | are on a two-way chain through the `next_same_value' | |
361 | and `prev_same_value' fields, and all point with | |
362 | the `first_same_value' field at the first element in | |
363 | that chain. The chain is in order of increasing cost. | |
364 | Each element's cost value is in its `cost' field. | |
365 | ||
366 | The `in_memory' field is nonzero for elements that | |
367 | involve any reference to memory. These elements are removed | |
368 | whenever a write is done to an unidentified location in memory. | |
369 | To be safe, we assume that a memory address is unidentified unless | |
370 | the address is either a symbol constant or a constant plus | |
371 | the frame pointer or argument pointer. | |
372 | ||
7afe21cc RK |
373 | The `related_value' field is used to connect related expressions |
374 | (that differ by adding an integer). | |
375 | The related expressions are chained in a circular fashion. | |
376 | `related_value' is zero for expressions for which this | |
377 | chain is not useful. | |
378 | ||
379 | The `cost' field stores the cost of this element's expression. | |
630c79be BS |
380 | The `regcost' field stores the value returned by approx_reg_cost for |
381 | this element's expression. | |
7afe21cc RK |
382 | |
383 | The `is_const' flag is set if the element is a constant (including | |
384 | a fixed address). | |
385 | ||
386 | The `flag' field is used as a temporary during some search routines. | |
387 | ||
388 | The `mode' field is usually the same as GET_MODE (`exp'), but | |
389 | if `exp' is a CONST_INT and has no machine mode then the `mode' | |
390 | field is the mode it was being used as. Each constant is | |
391 | recorded separately for each mode it is used with. */ | |
392 | ||
7afe21cc RK |
393 | struct table_elt |
394 | { | |
395 | rtx exp; | |
db048faf | 396 | rtx canon_exp; |
7afe21cc RK |
397 | struct table_elt *next_same_hash; |
398 | struct table_elt *prev_same_hash; | |
399 | struct table_elt *next_same_value; | |
400 | struct table_elt *prev_same_value; | |
401 | struct table_elt *first_same_value; | |
402 | struct table_elt *related_value; | |
403 | int cost; | |
630c79be | 404 | int regcost; |
b14af304 | 405 | ENUM_BITFIELD(machine_mode) mode : MACHINE_MODE_BITSIZE; |
7afe21cc | 406 | char in_memory; |
7afe21cc RK |
407 | char is_const; |
408 | char flag; | |
409 | }; | |
410 | ||
7afe21cc RK |
411 | /* We don't want a lot of buckets, because we rarely have very many |
412 | things stored in the hash table, and a lot of buckets slows | |
413 | down a lot of loops that happen frequently. */ | |
9b1549b8 DM |
414 | #define HASH_SHIFT 5 |
415 | #define HASH_SIZE (1 << HASH_SHIFT) | |
416 | #define HASH_MASK (HASH_SIZE - 1) | |
7afe21cc | 417 | |
630c79be BS |
418 | /* Determine whether register number N is considered a fixed register for the |
419 | purpose of approximating register costs. | |
7afe21cc RK |
420 | It is desirable to replace other regs with fixed regs, to reduce need for |
421 | non-fixed hard regs. | |
553687c9 | 422 | A reg wins if it is either the frame pointer or designated as fixed. */ |
7afe21cc | 423 | #define FIXED_REGNO_P(N) \ |
8bc169f2 | 424 | ((N) == FRAME_POINTER_REGNUM || (N) == HARD_FRAME_POINTER_REGNUM \ |
6ab832bc | 425 | || fixed_regs[N] || global_regs[N]) |
7afe21cc RK |
426 | |
427 | /* Compute cost of X, as stored in the `cost' field of a table_elt. Fixed | |
ac07e066 RK |
428 | hard registers and pointers into the frame are the cheapest with a cost |
429 | of 0. Next come pseudos with a cost of one and other hard registers with | |
430 | a cost of 2. Aside from these special cases, call `rtx_cost'. */ | |
431 | ||
d67fb775 | 432 | #define CHEAP_REGNO(N) \ |
c3284718 | 433 | (REGNO_PTR_FRAME_P (N) \ |
d67fb775 | 434 | || (HARD_REGISTER_NUM_P (N) \ |
e7bb59fa | 435 | && FIXED_REGNO_P (N) && REGNO_REG_CLASS (N) != NO_REGS)) |
7afe21cc | 436 | |
e548c9df AM |
437 | #define COST(X, MODE) \ |
438 | (REG_P (X) ? 0 : notreg_cost (X, MODE, SET, 1)) | |
439 | #define COST_IN(X, MODE, OUTER, OPNO) \ | |
440 | (REG_P (X) ? 0 : notreg_cost (X, MODE, OUTER, OPNO)) | |
7afe21cc | 441 | |
30f72379 MM |
442 | /* Get the number of times this register has been updated in this |
443 | basic block. */ | |
444 | ||
bc5e3b54 | 445 | #define REG_TICK(N) (get_cse_reg_info (N)->reg_tick) |
30f72379 MM |
446 | |
447 | /* Get the point at which REG was recorded in the table. */ | |
448 | ||
bc5e3b54 | 449 | #define REG_IN_TABLE(N) (get_cse_reg_info (N)->reg_in_table) |
30f72379 | 450 | |
46081bb3 SH |
451 | /* Get the SUBREG set at the last increment to REG_TICK (-1 if not a |
452 | SUBREG). */ | |
453 | ||
bc5e3b54 | 454 | #define SUBREG_TICKED(N) (get_cse_reg_info (N)->subreg_ticked) |
46081bb3 | 455 | |
30f72379 MM |
456 | /* Get the quantity number for REG. */ |
457 | ||
bc5e3b54 | 458 | #define REG_QTY(N) (get_cse_reg_info (N)->reg_qty) |
30f72379 | 459 | |
7afe21cc | 460 | /* Determine if the quantity number for register X represents a valid index |
1bb98cec | 461 | into the qty_table. */ |
7afe21cc | 462 | |
08a69267 | 463 | #define REGNO_QTY_VALID_P(N) (REG_QTY (N) >= 0) |
7afe21cc | 464 | |
2c5bfdf7 AN |
465 | /* Compare table_elt X and Y and return true iff X is cheaper than Y. */ |
466 | ||
467 | #define CHEAPER(X, Y) \ | |
468 | (preferable ((X)->cost, (X)->regcost, (Y)->cost, (Y)->regcost) < 0) | |
469 | ||
9b1549b8 | 470 | static struct table_elt *table[HASH_SIZE]; |
7afe21cc RK |
471 | |
472 | /* Chain of `struct table_elt's made so far for this function | |
473 | but currently removed from the table. */ | |
474 | ||
475 | static struct table_elt *free_element_chain; | |
476 | ||
24b97832 ILT |
477 | /* Trace a patch through the CFG. */ |
478 | ||
479 | struct branch_path | |
480 | { | |
481 | /* The basic block for this path entry. */ | |
482 | basic_block bb; | |
483 | }; | |
484 | ||
932ad4d9 SB |
485 | /* This data describes a block that will be processed by |
486 | cse_extended_basic_block. */ | |
6cd4575e | 487 | |
14a774a9 RK |
488 | struct cse_basic_block_data |
489 | { | |
6cd4575e RK |
490 | /* Total number of SETs in block. */ |
491 | int nsets; | |
6cd4575e RK |
492 | /* Size of current branch path, if any. */ |
493 | int path_size; | |
932ad4d9 | 494 | /* Current path, indicating which basic_blocks will be processed. */ |
24b97832 | 495 | struct branch_path *path; |
6cd4575e RK |
496 | }; |
497 | ||
6fb5fa3c DB |
498 | |
499 | /* Pointers to the live in/live out bitmaps for the boundaries of the | |
500 | current EBB. */ | |
501 | static bitmap cse_ebb_live_in, cse_ebb_live_out; | |
502 | ||
932ad4d9 SB |
503 | /* A simple bitmap to track which basic blocks have been visited |
504 | already as part of an already processed extended basic block. */ | |
505 | static sbitmap cse_visited_basic_blocks; | |
506 | ||
7080f735 | 507 | static bool fixed_base_plus_p (rtx x); |
e548c9df | 508 | static int notreg_cost (rtx, machine_mode, enum rtx_code, int); |
56ae04af | 509 | static int preferable (int, int, int, int); |
7080f735 | 510 | static void new_basic_block (void); |
ef4bddc2 | 511 | static void make_new_qty (unsigned int, machine_mode); |
7080f735 AJ |
512 | static void make_regs_eqv (unsigned int, unsigned int); |
513 | static void delete_reg_equiv (unsigned int); | |
dec7aaab UB |
514 | static bool mention_regs (rtx); |
515 | static bool insert_regs (rtx, struct table_elt *, bool); | |
7080f735 | 516 | static void remove_from_table (struct table_elt *, unsigned); |
d556d181 | 517 | static void remove_pseudo_from_table (rtx, unsigned); |
ef4bddc2 RS |
518 | static struct table_elt *lookup (rtx, unsigned, machine_mode); |
519 | static struct table_elt *lookup_for_remove (rtx, unsigned, machine_mode); | |
7080f735 | 520 | static rtx lookup_as_function (rtx, enum rtx_code); |
2c5bfdf7 | 521 | static struct table_elt *insert_with_costs (rtx, struct table_elt *, unsigned, |
ef4bddc2 | 522 | machine_mode, int, int); |
7080f735 | 523 | static struct table_elt *insert (rtx, struct table_elt *, unsigned, |
ef4bddc2 | 524 | machine_mode); |
7080f735 | 525 | static void merge_equiv_classes (struct table_elt *, struct table_elt *); |
ef4bddc2 | 526 | static void invalidate (rtx, machine_mode); |
7080f735 | 527 | static void remove_invalid_refs (unsigned int); |
91914e56 | 528 | static void remove_invalid_subreg_refs (unsigned int, poly_uint64, |
ef4bddc2 | 529 | machine_mode); |
7080f735 AJ |
530 | static void rehash_using_reg (rtx); |
531 | static void invalidate_memory (void); | |
7080f735 | 532 | static rtx use_related_value (rtx, struct table_elt *); |
0516f6fe | 533 | |
ef4bddc2 RS |
534 | static inline unsigned canon_hash (rtx, machine_mode); |
535 | static inline unsigned safe_hash (rtx, machine_mode); | |
e855c69d | 536 | static inline unsigned hash_rtx_string (const char *); |
0516f6fe | 537 | |
20468884 | 538 | static rtx canon_reg (rtx, rtx_insn *); |
7080f735 | 539 | static enum rtx_code find_comparison_args (enum rtx_code, rtx *, rtx *, |
ef4bddc2 RS |
540 | machine_mode *, |
541 | machine_mode *); | |
20468884 | 542 | static rtx fold_rtx (rtx, rtx_insn *); |
7080f735 | 543 | static rtx equiv_constant (rtx); |
20468884 | 544 | static void record_jump_equiv (rtx_insn *, bool); |
dec7aaab | 545 | static void record_jump_cond (enum rtx_code, machine_mode, rtx, rtx); |
20468884 | 546 | static void cse_insn (rtx_insn *); |
932ad4d9 | 547 | static void cse_prescan_path (struct cse_basic_block_data *); |
20468884 DM |
548 | static void invalidate_from_clobbers (rtx_insn *); |
549 | static void invalidate_from_sets_and_clobbers (rtx_insn *); | |
932ad4d9 | 550 | static void cse_extended_basic_block (struct cse_basic_block_data *); |
7080f735 | 551 | extern void dump_class (struct table_elt*); |
bc5e3b54 KH |
552 | static void get_cse_reg_info_1 (unsigned int regno); |
553 | static struct cse_reg_info * get_cse_reg_info (unsigned int regno); | |
7080f735 AJ |
554 | |
555 | static void flush_hash_table (void); | |
20468884 | 556 | static bool insn_live_p (rtx_insn *, int *); |
bd1cd0d0 | 557 | static bool set_live_p (rtx, int *); |
20468884 DM |
558 | static void cse_change_cc_mode_insn (rtx_insn *, rtx); |
559 | static void cse_change_cc_mode_insns (rtx_insn *, rtx_insn *, rtx); | |
ef4bddc2 | 560 | static machine_mode cse_cc_succs (basic_block, basic_block, rtx, rtx, |
31e9ebaf | 561 | bool); |
7afe21cc | 562 | \f |
2f93eea8 PB |
563 | |
564 | #undef RTL_HOOKS_GEN_LOWPART | |
565 | #define RTL_HOOKS_GEN_LOWPART gen_lowpart_if_possible | |
566 | ||
567 | static const struct rtl_hooks cse_rtl_hooks = RTL_HOOKS_INITIALIZER; | |
568 | \f | |
aeeec83b RB |
569 | /* Compute hash code of X in mode M. Special-case case where X is a pseudo |
570 | register (hard registers may require `do_not_record' to be set). */ | |
571 | ||
572 | static inline unsigned | |
573 | HASH (rtx x, machine_mode mode) | |
574 | { | |
575 | unsigned h = (REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
576 | ? (((unsigned) REG << 7) + (unsigned) REG_QTY (REGNO (x))) | |
577 | : canon_hash (x, mode)); | |
578 | return (h ^ (h >> HASH_SHIFT)) & HASH_MASK; | |
579 | } | |
580 | ||
581 | /* Like HASH, but without side-effects. */ | |
582 | ||
583 | static inline unsigned | |
584 | SAFE_HASH (rtx x, machine_mode mode) | |
585 | { | |
586 | unsigned h = (REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
587 | ? (((unsigned) REG << 7) + (unsigned) REG_QTY (REGNO (x))) | |
588 | : safe_hash (x, mode)); | |
589 | return (h ^ (h >> HASH_SHIFT)) & HASH_MASK; | |
590 | } | |
591 | ||
6399c0ab | 592 | /* Nonzero if X has the form (PLUS frame-pointer integer). */ |
4977bab6 ZW |
593 | |
594 | static bool | |
7080f735 | 595 | fixed_base_plus_p (rtx x) |
4977bab6 ZW |
596 | { |
597 | switch (GET_CODE (x)) | |
598 | { | |
599 | case REG: | |
600 | if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx) | |
601 | return true; | |
602 | if (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]) | |
603 | return true; | |
4977bab6 ZW |
604 | return false; |
605 | ||
606 | case PLUS: | |
481683e1 | 607 | if (!CONST_INT_P (XEXP (x, 1))) |
4977bab6 ZW |
608 | return false; |
609 | return fixed_base_plus_p (XEXP (x, 0)); | |
610 | ||
4977bab6 ZW |
611 | default: |
612 | return false; | |
613 | } | |
614 | } | |
615 | ||
a4c6502a MM |
616 | /* Dump the expressions in the equivalence class indicated by CLASSP. |
617 | This function is used only for debugging. */ | |
711417cd | 618 | DEBUG_FUNCTION void |
7080f735 | 619 | dump_class (struct table_elt *classp) |
a4c6502a MM |
620 | { |
621 | struct table_elt *elt; | |
622 | ||
623 | fprintf (stderr, "Equivalence chain for "); | |
624 | print_rtl (stderr, classp->exp); | |
625 | fprintf (stderr, ": \n"); | |
278a83b2 | 626 | |
a4c6502a MM |
627 | for (elt = classp->first_same_value; elt; elt = elt->next_same_value) |
628 | { | |
629 | print_rtl (stderr, elt->exp); | |
630 | fprintf (stderr, "\n"); | |
631 | } | |
632 | } | |
633 | ||
e89b312e RS |
634 | /* Return an estimate of the cost of the registers used in an rtx. |
635 | This is mostly the number of different REG expressions in the rtx; | |
636 | however for some exceptions like fixed registers we use a cost of | |
637 | 0. If any other hard register reference occurs, return MAX_COST. */ | |
be8ac49a | 638 | |
630c79be | 639 | static int |
e89b312e | 640 | approx_reg_cost (const_rtx x) |
630c79be | 641 | { |
e89b312e RS |
642 | int cost = 0; |
643 | subrtx_iterator::array_type array; | |
644 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
c863f8c2 | 645 | { |
e89b312e RS |
646 | const_rtx x = *iter; |
647 | if (REG_P (x)) | |
c863f8c2 | 648 | { |
e89b312e RS |
649 | unsigned int regno = REGNO (x); |
650 | if (!CHEAP_REGNO (regno)) | |
c863f8c2 | 651 | { |
e89b312e RS |
652 | if (regno < FIRST_PSEUDO_REGISTER) |
653 | { | |
654 | if (targetm.small_register_classes_for_mode_p (GET_MODE (x))) | |
655 | return MAX_COST; | |
656 | cost += 2; | |
657 | } | |
658 | else | |
659 | cost += 1; | |
c863f8c2 | 660 | } |
c863f8c2 DM |
661 | } |
662 | } | |
c863f8c2 | 663 | return cost; |
630c79be BS |
664 | } |
665 | ||
666 | /* Return a negative value if an rtx A, whose costs are given by COST_A | |
667 | and REGCOST_A, is more desirable than an rtx B. | |
668 | Return a positive value if A is less desirable, or 0 if the two are | |
669 | equally good. */ | |
670 | static int | |
56ae04af | 671 | preferable (int cost_a, int regcost_a, int cost_b, int regcost_b) |
630c79be | 672 | { |
423adbb9 | 673 | /* First, get rid of cases involving expressions that are entirely |
f1c1dfc3 BS |
674 | unwanted. */ |
675 | if (cost_a != cost_b) | |
676 | { | |
677 | if (cost_a == MAX_COST) | |
678 | return 1; | |
679 | if (cost_b == MAX_COST) | |
680 | return -1; | |
681 | } | |
682 | ||
683 | /* Avoid extending lifetimes of hardregs. */ | |
684 | if (regcost_a != regcost_b) | |
685 | { | |
686 | if (regcost_a == MAX_COST) | |
687 | return 1; | |
688 | if (regcost_b == MAX_COST) | |
689 | return -1; | |
690 | } | |
691 | ||
692 | /* Normal operation costs take precedence. */ | |
630c79be BS |
693 | if (cost_a != cost_b) |
694 | return cost_a - cost_b; | |
f1c1dfc3 | 695 | /* Only if these are identical consider effects on register pressure. */ |
630c79be BS |
696 | if (regcost_a != regcost_b) |
697 | return regcost_a - regcost_b; | |
698 | return 0; | |
699 | } | |
700 | ||
954a5693 RK |
701 | /* Internal function, to compute cost when X is not a register; called |
702 | from COST macro to keep it simple. */ | |
703 | ||
704 | static int | |
e548c9df | 705 | notreg_cost (rtx x, machine_mode mode, enum rtx_code outer, int opno) |
954a5693 | 706 | { |
b4206259 | 707 | scalar_int_mode int_mode, inner_mode; |
954a5693 | 708 | return ((GET_CODE (x) == SUBREG |
f8cfc6aa | 709 | && REG_P (SUBREG_REG (x)) |
b4206259 RS |
710 | && is_int_mode (mode, &int_mode) |
711 | && is_int_mode (GET_MODE (SUBREG_REG (x)), &inner_mode) | |
712 | && GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (inner_mode) | |
954a5693 | 713 | && subreg_lowpart_p (x) |
b4206259 | 714 | && TRULY_NOOP_TRUNCATION_MODES_P (int_mode, inner_mode)) |
630c79be | 715 | ? 0 |
e548c9df | 716 | : rtx_cost (x, mode, outer, opno, optimize_this_for_speed_p) * 2); |
954a5693 RK |
717 | } |
718 | ||
01329426 | 719 | \f |
bc5e3b54 | 720 | /* Initialize CSE_REG_INFO_TABLE. */ |
9b1549b8 | 721 | |
bc5e3b54 KH |
722 | static void |
723 | init_cse_reg_info (unsigned int nregs) | |
724 | { | |
725 | /* Do we need to grow the table? */ | |
726 | if (nregs > cse_reg_info_table_size) | |
30f72379 | 727 | { |
bc5e3b54 KH |
728 | unsigned int new_size; |
729 | ||
730 | if (cse_reg_info_table_size < 2048) | |
30f72379 | 731 | { |
bc5e3b54 KH |
732 | /* Compute a new size that is a power of 2 and no smaller |
733 | than the large of NREGS and 64. */ | |
734 | new_size = (cse_reg_info_table_size | |
735 | ? cse_reg_info_table_size : 64); | |
736 | ||
737 | while (new_size < nregs) | |
738 | new_size *= 2; | |
30f72379 MM |
739 | } |
740 | else | |
1590d0d4 | 741 | { |
bc5e3b54 KH |
742 | /* If we need a big table, allocate just enough to hold |
743 | NREGS registers. */ | |
744 | new_size = nregs; | |
1590d0d4 | 745 | } |
9b1549b8 | 746 | |
bc5e3b54 | 747 | /* Reallocate the table with NEW_SIZE entries. */ |
04695783 | 748 | free (cse_reg_info_table); |
5ed6ace5 | 749 | cse_reg_info_table = XNEWVEC (struct cse_reg_info, new_size); |
bc5e3b54 | 750 | cse_reg_info_table_size = new_size; |
a811c672 | 751 | cse_reg_info_table_first_uninitialized = 0; |
bc5e3b54 KH |
752 | } |
753 | ||
754 | /* Do we have all of the first NREGS entries initialized? */ | |
755 | if (cse_reg_info_table_first_uninitialized < nregs) | |
756 | { | |
757 | unsigned int old_timestamp = cse_reg_info_timestamp - 1; | |
758 | unsigned int i; | |
759 | ||
760 | /* Put the old timestamp on newly allocated entries so that they | |
761 | will all be considered out of date. We do not touch those | |
762 | entries beyond the first NREGS entries to be nice to the | |
763 | virtual memory. */ | |
764 | for (i = cse_reg_info_table_first_uninitialized; i < nregs; i++) | |
765 | cse_reg_info_table[i].timestamp = old_timestamp; | |
30f72379 | 766 | |
bc5e3b54 | 767 | cse_reg_info_table_first_uninitialized = nregs; |
30f72379 | 768 | } |
bc5e3b54 KH |
769 | } |
770 | ||
a52aff23 | 771 | /* Given REGNO, initialize the cse_reg_info entry for REGNO. */ |
bc5e3b54 KH |
772 | |
773 | static void | |
774 | get_cse_reg_info_1 (unsigned int regno) | |
775 | { | |
776 | /* Set TIMESTAMP field to CSE_REG_INFO_TIMESTAMP so that this | |
777 | entry will be considered to have been initialized. */ | |
778 | cse_reg_info_table[regno].timestamp = cse_reg_info_timestamp; | |
779 | ||
780 | /* Initialize the rest of the entry. */ | |
781 | cse_reg_info_table[regno].reg_tick = 1; | |
782 | cse_reg_info_table[regno].reg_in_table = -1; | |
783 | cse_reg_info_table[regno].subreg_ticked = -1; | |
784 | cse_reg_info_table[regno].reg_qty = -regno - 1; | |
785 | } | |
786 | ||
787 | /* Find a cse_reg_info entry for REGNO. */ | |
30f72379 | 788 | |
bc5e3b54 KH |
789 | static inline struct cse_reg_info * |
790 | get_cse_reg_info (unsigned int regno) | |
791 | { | |
792 | struct cse_reg_info *p = &cse_reg_info_table[regno]; | |
793 | ||
782c0a3e KH |
794 | /* If this entry has not been initialized, go ahead and initialize |
795 | it. */ | |
bc5e3b54 KH |
796 | if (p->timestamp != cse_reg_info_timestamp) |
797 | get_cse_reg_info_1 (regno); | |
30f72379 | 798 | |
9b1549b8 | 799 | return p; |
30f72379 MM |
800 | } |
801 | ||
7afe21cc RK |
802 | /* Clear the hash table and initialize each register with its own quantity, |
803 | for a new basic block. */ | |
804 | ||
805 | static void | |
7080f735 | 806 | new_basic_block (void) |
7afe21cc | 807 | { |
b3694847 | 808 | int i; |
7afe21cc | 809 | |
08a69267 | 810 | next_qty = 0; |
7afe21cc | 811 | |
a52aff23 | 812 | /* Invalidate cse_reg_info_table. */ |
bc5e3b54 | 813 | cse_reg_info_timestamp++; |
7afe21cc | 814 | |
bc5e3b54 | 815 | /* Clear out hash table state for this pass. */ |
7afe21cc RK |
816 | CLEAR_HARD_REG_SET (hard_regs_in_table); |
817 | ||
818 | /* The per-quantity values used to be initialized here, but it is | |
819 | much faster to initialize each as it is made in `make_new_qty'. */ | |
820 | ||
9b1549b8 | 821 | for (i = 0; i < HASH_SIZE; i++) |
7afe21cc | 822 | { |
9b1549b8 DM |
823 | struct table_elt *first; |
824 | ||
825 | first = table[i]; | |
826 | if (first != NULL) | |
7afe21cc | 827 | { |
9b1549b8 DM |
828 | struct table_elt *last = first; |
829 | ||
830 | table[i] = NULL; | |
831 | ||
832 | while (last->next_same_hash != NULL) | |
833 | last = last->next_same_hash; | |
834 | ||
835 | /* Now relink this hash entire chain into | |
836 | the free element list. */ | |
837 | ||
838 | last->next_same_hash = free_element_chain; | |
839 | free_element_chain = first; | |
7afe21cc RK |
840 | } |
841 | } | |
7afe21cc RK |
842 | } |
843 | ||
1bb98cec DM |
844 | /* Say that register REG contains a quantity in mode MODE not in any |
845 | register before and initialize that quantity. */ | |
7afe21cc RK |
846 | |
847 | static void | |
ef4bddc2 | 848 | make_new_qty (unsigned int reg, machine_mode mode) |
7afe21cc | 849 | { |
b3694847 SS |
850 | int q; |
851 | struct qty_table_elem *ent; | |
852 | struct reg_eqv_elem *eqv; | |
7afe21cc | 853 | |
341c100f | 854 | gcc_assert (next_qty < max_qty); |
7afe21cc | 855 | |
30f72379 | 856 | q = REG_QTY (reg) = next_qty++; |
1bb98cec DM |
857 | ent = &qty_table[q]; |
858 | ent->first_reg = reg; | |
859 | ent->last_reg = reg; | |
860 | ent->mode = mode; | |
20468884 | 861 | ent->const_rtx = ent->const_insn = NULL; |
1bb98cec DM |
862 | ent->comparison_code = UNKNOWN; |
863 | ||
864 | eqv = ®_eqv_table[reg]; | |
865 | eqv->next = eqv->prev = -1; | |
7afe21cc RK |
866 | } |
867 | ||
868 | /* Make reg NEW equivalent to reg OLD. | |
869 | OLD is not changing; NEW is. */ | |
870 | ||
871 | static void | |
32e9fa48 | 872 | make_regs_eqv (unsigned int new_reg, unsigned int old_reg) |
7afe21cc | 873 | { |
770ae6cc | 874 | unsigned int lastr, firstr; |
32e9fa48 | 875 | int q = REG_QTY (old_reg); |
770ae6cc | 876 | struct qty_table_elem *ent; |
1bb98cec DM |
877 | |
878 | ent = &qty_table[q]; | |
7afe21cc RK |
879 | |
880 | /* Nothing should become eqv until it has a "non-invalid" qty number. */ | |
32e9fa48 | 881 | gcc_assert (REGNO_QTY_VALID_P (old_reg)); |
7afe21cc | 882 | |
32e9fa48 | 883 | REG_QTY (new_reg) = q; |
1bb98cec DM |
884 | firstr = ent->first_reg; |
885 | lastr = ent->last_reg; | |
7afe21cc RK |
886 | |
887 | /* Prefer fixed hard registers to anything. Prefer pseudo regs to other | |
888 | hard regs. Among pseudos, if NEW will live longer than any other reg | |
889 | of the same qty, and that is beyond the current basic block, | |
890 | make it the new canonical replacement for this qty. */ | |
891 | if (! (firstr < FIRST_PSEUDO_REGISTER && FIXED_REGNO_P (firstr)) | |
892 | /* Certain fixed registers might be of the class NO_REGS. This means | |
893 | that not only can they not be allocated by the compiler, but | |
830a38ee | 894 | they cannot be used in substitutions or canonicalizations |
7afe21cc | 895 | either. */ |
32e9fa48 KG |
896 | && (new_reg >= FIRST_PSEUDO_REGISTER || REGNO_REG_CLASS (new_reg) != NO_REGS) |
897 | && ((new_reg < FIRST_PSEUDO_REGISTER && FIXED_REGNO_P (new_reg)) | |
898 | || (new_reg >= FIRST_PSEUDO_REGISTER | |
7afe21cc | 899 | && (firstr < FIRST_PSEUDO_REGISTER |
32e9fa48 | 900 | || (bitmap_bit_p (cse_ebb_live_out, new_reg) |
6fb5fa3c | 901 | && !bitmap_bit_p (cse_ebb_live_out, firstr)) |
32e9fa48 | 902 | || (bitmap_bit_p (cse_ebb_live_in, new_reg) |
6fb5fa3c | 903 | && !bitmap_bit_p (cse_ebb_live_in, firstr)))))) |
7afe21cc | 904 | { |
32e9fa48 KG |
905 | reg_eqv_table[firstr].prev = new_reg; |
906 | reg_eqv_table[new_reg].next = firstr; | |
907 | reg_eqv_table[new_reg].prev = -1; | |
908 | ent->first_reg = new_reg; | |
7afe21cc RK |
909 | } |
910 | else | |
911 | { | |
912 | /* If NEW is a hard reg (known to be non-fixed), insert at end. | |
913 | Otherwise, insert before any non-fixed hard regs that are at the | |
914 | end. Registers of class NO_REGS cannot be used as an | |
915 | equivalent for anything. */ | |
1bb98cec | 916 | while (lastr < FIRST_PSEUDO_REGISTER && reg_eqv_table[lastr].prev >= 0 |
7afe21cc | 917 | && (REGNO_REG_CLASS (lastr) == NO_REGS || ! FIXED_REGNO_P (lastr)) |
32e9fa48 | 918 | && new_reg >= FIRST_PSEUDO_REGISTER) |
1bb98cec | 919 | lastr = reg_eqv_table[lastr].prev; |
32e9fa48 | 920 | reg_eqv_table[new_reg].next = reg_eqv_table[lastr].next; |
1bb98cec | 921 | if (reg_eqv_table[lastr].next >= 0) |
32e9fa48 | 922 | reg_eqv_table[reg_eqv_table[lastr].next].prev = new_reg; |
7afe21cc | 923 | else |
32e9fa48 KG |
924 | qty_table[q].last_reg = new_reg; |
925 | reg_eqv_table[lastr].next = new_reg; | |
926 | reg_eqv_table[new_reg].prev = lastr; | |
7afe21cc RK |
927 | } |
928 | } | |
929 | ||
930 | /* Remove REG from its equivalence class. */ | |
931 | ||
932 | static void | |
7080f735 | 933 | delete_reg_equiv (unsigned int reg) |
7afe21cc | 934 | { |
b3694847 SS |
935 | struct qty_table_elem *ent; |
936 | int q = REG_QTY (reg); | |
937 | int p, n; | |
7afe21cc | 938 | |
a4e262bc | 939 | /* If invalid, do nothing. */ |
08a69267 | 940 | if (! REGNO_QTY_VALID_P (reg)) |
7afe21cc RK |
941 | return; |
942 | ||
1bb98cec DM |
943 | ent = &qty_table[q]; |
944 | ||
945 | p = reg_eqv_table[reg].prev; | |
946 | n = reg_eqv_table[reg].next; | |
a4e262bc | 947 | |
7afe21cc | 948 | if (n != -1) |
1bb98cec | 949 | reg_eqv_table[n].prev = p; |
7afe21cc | 950 | else |
1bb98cec | 951 | ent->last_reg = p; |
7afe21cc | 952 | if (p != -1) |
1bb98cec | 953 | reg_eqv_table[p].next = n; |
7afe21cc | 954 | else |
1bb98cec | 955 | ent->first_reg = n; |
7afe21cc | 956 | |
08a69267 | 957 | REG_QTY (reg) = -reg - 1; |
7afe21cc RK |
958 | } |
959 | ||
960 | /* Remove any invalid expressions from the hash table | |
961 | that refer to any of the registers contained in expression X. | |
962 | ||
963 | Make sure that newly inserted references to those registers | |
964 | as subexpressions will be considered valid. | |
965 | ||
966 | mention_regs is not called when a register itself | |
967 | is being stored in the table. | |
968 | ||
dec7aaab UB |
969 | Return true if we have done something that may have changed |
970 | the hash code of X. */ | |
7afe21cc | 971 | |
dec7aaab | 972 | static bool |
7080f735 | 973 | mention_regs (rtx x) |
7afe21cc | 974 | { |
b3694847 SS |
975 | enum rtx_code code; |
976 | int i, j; | |
977 | const char *fmt; | |
dec7aaab | 978 | bool changed = false; |
7afe21cc RK |
979 | |
980 | if (x == 0) | |
dec7aaab | 981 | return false; |
7afe21cc RK |
982 | |
983 | code = GET_CODE (x); | |
984 | if (code == REG) | |
985 | { | |
770ae6cc | 986 | unsigned int regno = REGNO (x); |
09e18274 | 987 | unsigned int endregno = END_REGNO (x); |
770ae6cc | 988 | unsigned int i; |
7afe21cc RK |
989 | |
990 | for (i = regno; i < endregno; i++) | |
991 | { | |
30f72379 | 992 | if (REG_IN_TABLE (i) >= 0 && REG_IN_TABLE (i) != REG_TICK (i)) |
7afe21cc RK |
993 | remove_invalid_refs (i); |
994 | ||
30f72379 | 995 | REG_IN_TABLE (i) = REG_TICK (i); |
46081bb3 | 996 | SUBREG_TICKED (i) = -1; |
7afe21cc RK |
997 | } |
998 | ||
dec7aaab | 999 | return false; |
7afe21cc RK |
1000 | } |
1001 | ||
34c73909 R |
1002 | /* If this is a SUBREG, we don't want to discard other SUBREGs of the same |
1003 | pseudo if they don't use overlapping words. We handle only pseudos | |
1004 | here for simplicity. */ | |
f8cfc6aa | 1005 | if (code == SUBREG && REG_P (SUBREG_REG (x)) |
34c73909 R |
1006 | && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER) |
1007 | { | |
770ae6cc | 1008 | unsigned int i = REGNO (SUBREG_REG (x)); |
34c73909 | 1009 | |
30f72379 | 1010 | if (REG_IN_TABLE (i) >= 0 && REG_IN_TABLE (i) != REG_TICK (i)) |
34c73909 | 1011 | { |
46081bb3 SH |
1012 | /* If REG_IN_TABLE (i) differs from REG_TICK (i) by one, and |
1013 | the last store to this register really stored into this | |
1014 | subreg, then remove the memory of this subreg. | |
1015 | Otherwise, remove any memory of the entire register and | |
1016 | all its subregs from the table. */ | |
1017 | if (REG_TICK (i) - REG_IN_TABLE (i) > 1 | |
5dd78e9a | 1018 | || SUBREG_TICKED (i) != REGNO (SUBREG_REG (x))) |
34c73909 R |
1019 | remove_invalid_refs (i); |
1020 | else | |
ddef6bc7 | 1021 | remove_invalid_subreg_refs (i, SUBREG_BYTE (x), GET_MODE (x)); |
34c73909 R |
1022 | } |
1023 | ||
30f72379 | 1024 | REG_IN_TABLE (i) = REG_TICK (i); |
5dd78e9a | 1025 | SUBREG_TICKED (i) = REGNO (SUBREG_REG (x)); |
dec7aaab | 1026 | return false; |
34c73909 R |
1027 | } |
1028 | ||
7afe21cc RK |
1029 | /* If X is a comparison or a COMPARE and either operand is a register |
1030 | that does not have a quantity, give it one. This is so that a later | |
1031 | call to record_jump_equiv won't cause X to be assigned a different | |
1032 | hash code and not found in the table after that call. | |
1033 | ||
1034 | It is not necessary to do this here, since rehash_using_reg can | |
1035 | fix up the table later, but doing this here eliminates the need to | |
1036 | call that expensive function in the most common case where the only | |
1037 | use of the register is in the comparison. */ | |
1038 | ||
ec8e098d | 1039 | if (code == COMPARE || COMPARISON_P (x)) |
7afe21cc | 1040 | { |
f8cfc6aa | 1041 | if (REG_P (XEXP (x, 0)) |
7afe21cc | 1042 | && ! REGNO_QTY_VALID_P (REGNO (XEXP (x, 0)))) |
dec7aaab | 1043 | if (insert_regs (XEXP (x, 0), NULL, false)) |
7afe21cc RK |
1044 | { |
1045 | rehash_using_reg (XEXP (x, 0)); | |
dec7aaab | 1046 | changed = true; |
7afe21cc RK |
1047 | } |
1048 | ||
f8cfc6aa | 1049 | if (REG_P (XEXP (x, 1)) |
7afe21cc | 1050 | && ! REGNO_QTY_VALID_P (REGNO (XEXP (x, 1)))) |
dec7aaab | 1051 | if (insert_regs (XEXP (x, 1), NULL, false)) |
7afe21cc RK |
1052 | { |
1053 | rehash_using_reg (XEXP (x, 1)); | |
dec7aaab | 1054 | changed = true; |
7afe21cc RK |
1055 | } |
1056 | } | |
1057 | ||
1058 | fmt = GET_RTX_FORMAT (code); | |
1059 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1060 | if (fmt[i] == 'e') | |
dec7aaab UB |
1061 | { |
1062 | if (mention_regs (XEXP (x, i))) | |
1063 | changed = true; | |
1064 | } | |
7afe21cc RK |
1065 | else if (fmt[i] == 'E') |
1066 | for (j = 0; j < XVECLEN (x, i); j++) | |
dec7aaab UB |
1067 | if (mention_regs (XVECEXP (x, i, j))) |
1068 | changed = true; | |
7afe21cc RK |
1069 | |
1070 | return changed; | |
1071 | } | |
1072 | ||
1073 | /* Update the register quantities for inserting X into the hash table | |
1074 | with a value equivalent to CLASSP. | |
1075 | (If the class does not contain a REG, it is irrelevant.) | |
dec7aaab | 1076 | If MODIFIED is true, X is a destination; it is being modified. |
7afe21cc RK |
1077 | Note that delete_reg_equiv should be called on a register |
1078 | before insert_regs is done on that register with MODIFIED != 0. | |
1079 | ||
dec7aaab | 1080 | True value means that elements of reg_qty have changed |
7afe21cc RK |
1081 | so X's hash code may be different. */ |
1082 | ||
dec7aaab UB |
1083 | static bool |
1084 | insert_regs (rtx x, struct table_elt *classp, bool modified) | |
7afe21cc | 1085 | { |
f8cfc6aa | 1086 | if (REG_P (x)) |
7afe21cc | 1087 | { |
770ae6cc RK |
1088 | unsigned int regno = REGNO (x); |
1089 | int qty_valid; | |
7afe21cc | 1090 | |
1ff0c00d RK |
1091 | /* If REGNO is in the equivalence table already but is of the |
1092 | wrong mode for that equivalence, don't do anything here. */ | |
1093 | ||
1bb98cec DM |
1094 | qty_valid = REGNO_QTY_VALID_P (regno); |
1095 | if (qty_valid) | |
1096 | { | |
1097 | struct qty_table_elem *ent = &qty_table[REG_QTY (regno)]; | |
1ff0c00d | 1098 | |
1bb98cec | 1099 | if (ent->mode != GET_MODE (x)) |
dec7aaab | 1100 | return false; |
1bb98cec DM |
1101 | } |
1102 | ||
1103 | if (modified || ! qty_valid) | |
7afe21cc RK |
1104 | { |
1105 | if (classp) | |
1106 | for (classp = classp->first_same_value; | |
1107 | classp != 0; | |
1108 | classp = classp->next_same_value) | |
f8cfc6aa | 1109 | if (REG_P (classp->exp) |
7afe21cc RK |
1110 | && GET_MODE (classp->exp) == GET_MODE (x)) |
1111 | { | |
cd928652 ZD |
1112 | unsigned c_regno = REGNO (classp->exp); |
1113 | ||
1114 | gcc_assert (REGNO_QTY_VALID_P (c_regno)); | |
1115 | ||
1116 | /* Suppose that 5 is hard reg and 100 and 101 are | |
1117 | pseudos. Consider | |
1118 | ||
1119 | (set (reg:si 100) (reg:si 5)) | |
1120 | (set (reg:si 5) (reg:si 100)) | |
1121 | (set (reg:di 101) (reg:di 5)) | |
1122 | ||
1123 | We would now set REG_QTY (101) = REG_QTY (5), but the | |
1124 | entry for 5 is in SImode. When we use this later in | |
1125 | copy propagation, we get the register in wrong mode. */ | |
1126 | if (qty_table[REG_QTY (c_regno)].mode != GET_MODE (x)) | |
1127 | continue; | |
1128 | ||
1129 | make_regs_eqv (regno, c_regno); | |
dec7aaab | 1130 | return true; |
7afe21cc RK |
1131 | } |
1132 | ||
d9f20424 R |
1133 | /* Mention_regs for a SUBREG checks if REG_TICK is exactly one larger |
1134 | than REG_IN_TABLE to find out if there was only a single preceding | |
1135 | invalidation - for the SUBREG - or another one, which would be | |
1136 | for the full register. However, if we find here that REG_TICK | |
1137 | indicates that the register is invalid, it means that it has | |
1138 | been invalidated in a separate operation. The SUBREG might be used | |
1139 | now (then this is a recursive call), or we might use the full REG | |
1140 | now and a SUBREG of it later. So bump up REG_TICK so that | |
1141 | mention_regs will do the right thing. */ | |
1142 | if (! modified | |
1143 | && REG_IN_TABLE (regno) >= 0 | |
1144 | && REG_TICK (regno) == REG_IN_TABLE (regno) + 1) | |
1145 | REG_TICK (regno)++; | |
1bb98cec | 1146 | make_new_qty (regno, GET_MODE (x)); |
dec7aaab | 1147 | return true; |
7afe21cc | 1148 | } |
cdf4112f | 1149 | |
dec7aaab | 1150 | return false; |
7afe21cc | 1151 | } |
c610adec RK |
1152 | |
1153 | /* If X is a SUBREG, we will likely be inserting the inner register in the | |
1154 | table. If that register doesn't have an assigned quantity number at | |
1155 | this point but does later, the insertion that we will be doing now will | |
1156 | not be accessible because its hash code will have changed. So assign | |
1157 | a quantity number now. */ | |
1158 | ||
f8cfc6aa | 1159 | else if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) |
c610adec RK |
1160 | && ! REGNO_QTY_VALID_P (REGNO (SUBREG_REG (x)))) |
1161 | { | |
dec7aaab | 1162 | insert_regs (SUBREG_REG (x), NULL, false); |
34c73909 | 1163 | mention_regs (x); |
dec7aaab | 1164 | return true; |
c610adec | 1165 | } |
7afe21cc RK |
1166 | else |
1167 | return mention_regs (x); | |
1168 | } | |
1169 | \f | |
2c5bfdf7 AN |
1170 | |
1171 | /* Compute upper and lower anchors for CST. Also compute the offset of CST | |
1172 | from these anchors/bases such that *_BASE + *_OFFS = CST. Return false iff | |
1173 | CST is equal to an anchor. */ | |
1174 | ||
1175 | static bool | |
1176 | compute_const_anchors (rtx cst, | |
1177 | HOST_WIDE_INT *lower_base, HOST_WIDE_INT *lower_offs, | |
1178 | HOST_WIDE_INT *upper_base, HOST_WIDE_INT *upper_offs) | |
1179 | { | |
0cb5d7cd | 1180 | unsigned HOST_WIDE_INT n = UINTVAL (cst); |
2c5bfdf7 AN |
1181 | |
1182 | *lower_base = n & ~(targetm.const_anchor - 1); | |
0cb5d7cd | 1183 | if ((unsigned HOST_WIDE_INT) *lower_base == n) |
2c5bfdf7 AN |
1184 | return false; |
1185 | ||
0cb5d7cd JJ |
1186 | *upper_base = ((n + (targetm.const_anchor - 1)) |
1187 | & ~(targetm.const_anchor - 1)); | |
2c5bfdf7 AN |
1188 | *upper_offs = n - *upper_base; |
1189 | *lower_offs = n - *lower_base; | |
1190 | return true; | |
1191 | } | |
1192 | ||
1193 | /* Insert the equivalence between ANCHOR and (REG + OFF) in mode MODE. */ | |
1194 | ||
1195 | static void | |
1196 | insert_const_anchor (HOST_WIDE_INT anchor, rtx reg, HOST_WIDE_INT offs, | |
ef4bddc2 | 1197 | machine_mode mode) |
2c5bfdf7 AN |
1198 | { |
1199 | struct table_elt *elt; | |
1200 | unsigned hash; | |
1201 | rtx anchor_exp; | |
1202 | rtx exp; | |
1203 | ||
0cb5d7cd | 1204 | anchor_exp = gen_int_mode (anchor, mode); |
2c5bfdf7 AN |
1205 | hash = HASH (anchor_exp, mode); |
1206 | elt = lookup (anchor_exp, hash, mode); | |
1207 | if (!elt) | |
1208 | elt = insert (anchor_exp, NULL, hash, mode); | |
1209 | ||
0a81f074 | 1210 | exp = plus_constant (mode, reg, offs); |
2c5bfdf7 AN |
1211 | /* REG has just been inserted and the hash codes recomputed. */ |
1212 | mention_regs (exp); | |
1213 | hash = HASH (exp, mode); | |
1214 | ||
1215 | /* Use the cost of the register rather than the whole expression. When | |
1216 | looking up constant anchors we will further offset the corresponding | |
1217 | expression therefore it does not make sense to prefer REGs over | |
1218 | reg-immediate additions. Prefer instead the oldest expression. Also | |
1219 | don't prefer pseudos over hard regs so that we derive constants in | |
1220 | argument registers from other argument registers rather than from the | |
1221 | original pseudo that was used to synthesize the constant. */ | |
e548c9df | 1222 | insert_with_costs (exp, elt, hash, mode, COST (reg, mode), 1); |
2c5bfdf7 AN |
1223 | } |
1224 | ||
1225 | /* The constant CST is equivalent to the register REG. Create | |
1226 | equivalences between the two anchors of CST and the corresponding | |
1227 | register-offset expressions using REG. */ | |
1228 | ||
1229 | static void | |
ef4bddc2 | 1230 | insert_const_anchors (rtx reg, rtx cst, machine_mode mode) |
2c5bfdf7 AN |
1231 | { |
1232 | HOST_WIDE_INT lower_base, lower_offs, upper_base, upper_offs; | |
1233 | ||
1234 | if (!compute_const_anchors (cst, &lower_base, &lower_offs, | |
1235 | &upper_base, &upper_offs)) | |
1236 | return; | |
1237 | ||
1238 | /* Ignore anchors of value 0. Constants accessible from zero are | |
1239 | simple. */ | |
1240 | if (lower_base != 0) | |
1241 | insert_const_anchor (lower_base, reg, -lower_offs, mode); | |
1242 | ||
1243 | if (upper_base != 0) | |
1244 | insert_const_anchor (upper_base, reg, -upper_offs, mode); | |
1245 | } | |
1246 | ||
1247 | /* We need to express ANCHOR_ELT->exp + OFFS. Walk the equivalence list of | |
1248 | ANCHOR_ELT and see if offsetting any of the entries by OFFS would create a | |
1249 | valid expression. Return the cheapest and oldest of such expressions. In | |
1250 | *OLD, return how old the resulting expression is compared to the other | |
1251 | equivalent expressions. */ | |
1252 | ||
1253 | static rtx | |
1254 | find_reg_offset_for_const (struct table_elt *anchor_elt, HOST_WIDE_INT offs, | |
1255 | unsigned *old) | |
1256 | { | |
1257 | struct table_elt *elt; | |
1258 | unsigned idx; | |
1259 | struct table_elt *match_elt; | |
1260 | rtx match; | |
1261 | ||
1262 | /* Find the cheapest and *oldest* expression to maximize the chance of | |
1263 | reusing the same pseudo. */ | |
1264 | ||
1265 | match_elt = NULL; | |
1266 | match = NULL_RTX; | |
1267 | for (elt = anchor_elt->first_same_value, idx = 0; | |
1268 | elt; | |
1269 | elt = elt->next_same_value, idx++) | |
1270 | { | |
1271 | if (match_elt && CHEAPER (match_elt, elt)) | |
1272 | return match; | |
1273 | ||
1274 | if (REG_P (elt->exp) | |
1275 | || (GET_CODE (elt->exp) == PLUS | |
1276 | && REG_P (XEXP (elt->exp, 0)) | |
1277 | && GET_CODE (XEXP (elt->exp, 1)) == CONST_INT)) | |
1278 | { | |
1279 | rtx x; | |
1280 | ||
1281 | /* Ignore expressions that are no longer valid. */ | |
1282 | if (!REG_P (elt->exp) && !exp_equiv_p (elt->exp, elt->exp, 1, false)) | |
1283 | continue; | |
1284 | ||
0a81f074 | 1285 | x = plus_constant (GET_MODE (elt->exp), elt->exp, offs); |
2c5bfdf7 AN |
1286 | if (REG_P (x) |
1287 | || (GET_CODE (x) == PLUS | |
1288 | && IN_RANGE (INTVAL (XEXP (x, 1)), | |
1289 | -targetm.const_anchor, | |
1290 | targetm.const_anchor - 1))) | |
1291 | { | |
1292 | match = x; | |
1293 | match_elt = elt; | |
1294 | *old = idx; | |
1295 | } | |
1296 | } | |
1297 | } | |
1298 | ||
1299 | return match; | |
1300 | } | |
1301 | ||
1302 | /* Try to express the constant SRC_CONST using a register+offset expression | |
1303 | derived from a constant anchor. Return it if successful or NULL_RTX, | |
1304 | otherwise. */ | |
1305 | ||
1306 | static rtx | |
ef4bddc2 | 1307 | try_const_anchors (rtx src_const, machine_mode mode) |
2c5bfdf7 AN |
1308 | { |
1309 | struct table_elt *lower_elt, *upper_elt; | |
1310 | HOST_WIDE_INT lower_base, lower_offs, upper_base, upper_offs; | |
1311 | rtx lower_anchor_rtx, upper_anchor_rtx; | |
1312 | rtx lower_exp = NULL_RTX, upper_exp = NULL_RTX; | |
1313 | unsigned lower_old, upper_old; | |
1314 | ||
c0bd7930 JG |
1315 | /* CONST_INT may be in various modes, avoid non-scalar-int mode. */ |
1316 | if (!SCALAR_INT_MODE_P (mode)) | |
40dbb05c RS |
1317 | return NULL_RTX; |
1318 | ||
2c5bfdf7 AN |
1319 | if (!compute_const_anchors (src_const, &lower_base, &lower_offs, |
1320 | &upper_base, &upper_offs)) | |
1321 | return NULL_RTX; | |
1322 | ||
1323 | lower_anchor_rtx = GEN_INT (lower_base); | |
1324 | upper_anchor_rtx = GEN_INT (upper_base); | |
1325 | lower_elt = lookup (lower_anchor_rtx, HASH (lower_anchor_rtx, mode), mode); | |
1326 | upper_elt = lookup (upper_anchor_rtx, HASH (upper_anchor_rtx, mode), mode); | |
1327 | ||
1328 | if (lower_elt) | |
1329 | lower_exp = find_reg_offset_for_const (lower_elt, lower_offs, &lower_old); | |
1330 | if (upper_elt) | |
1331 | upper_exp = find_reg_offset_for_const (upper_elt, upper_offs, &upper_old); | |
1332 | ||
1333 | if (!lower_exp) | |
1334 | return upper_exp; | |
1335 | if (!upper_exp) | |
1336 | return lower_exp; | |
1337 | ||
1338 | /* Return the older expression. */ | |
1339 | return (upper_old > lower_old ? upper_exp : lower_exp); | |
1340 | } | |
1341 | \f | |
7afe21cc RK |
1342 | /* Look in or update the hash table. */ |
1343 | ||
7afe21cc RK |
1344 | /* Remove table element ELT from use in the table. |
1345 | HASH is its hash code, made using the HASH macro. | |
1346 | It's an argument because often that is known in advance | |
1347 | and we save much time not recomputing it. */ | |
1348 | ||
1349 | static void | |
7080f735 | 1350 | remove_from_table (struct table_elt *elt, unsigned int hash) |
7afe21cc RK |
1351 | { |
1352 | if (elt == 0) | |
1353 | return; | |
1354 | ||
1355 | /* Mark this element as removed. See cse_insn. */ | |
1356 | elt->first_same_value = 0; | |
1357 | ||
1358 | /* Remove the table element from its equivalence class. */ | |
278a83b2 | 1359 | |
7afe21cc | 1360 | { |
b3694847 SS |
1361 | struct table_elt *prev = elt->prev_same_value; |
1362 | struct table_elt *next = elt->next_same_value; | |
7afe21cc | 1363 | |
278a83b2 KH |
1364 | if (next) |
1365 | next->prev_same_value = prev; | |
7afe21cc RK |
1366 | |
1367 | if (prev) | |
1368 | prev->next_same_value = next; | |
1369 | else | |
1370 | { | |
b3694847 | 1371 | struct table_elt *newfirst = next; |
7afe21cc RK |
1372 | while (next) |
1373 | { | |
1374 | next->first_same_value = newfirst; | |
1375 | next = next->next_same_value; | |
1376 | } | |
1377 | } | |
1378 | } | |
1379 | ||
1380 | /* Remove the table element from its hash bucket. */ | |
1381 | ||
1382 | { | |
b3694847 SS |
1383 | struct table_elt *prev = elt->prev_same_hash; |
1384 | struct table_elt *next = elt->next_same_hash; | |
7afe21cc | 1385 | |
278a83b2 KH |
1386 | if (next) |
1387 | next->prev_same_hash = prev; | |
7afe21cc RK |
1388 | |
1389 | if (prev) | |
1390 | prev->next_same_hash = next; | |
1391 | else if (table[hash] == elt) | |
1392 | table[hash] = next; | |
1393 | else | |
1394 | { | |
1395 | /* This entry is not in the proper hash bucket. This can happen | |
1396 | when two classes were merged by `merge_equiv_classes'. Search | |
1397 | for the hash bucket that it heads. This happens only very | |
1398 | rarely, so the cost is acceptable. */ | |
9b1549b8 | 1399 | for (hash = 0; hash < HASH_SIZE; hash++) |
7afe21cc RK |
1400 | if (table[hash] == elt) |
1401 | table[hash] = next; | |
1402 | } | |
1403 | } | |
1404 | ||
1405 | /* Remove the table element from its related-value circular chain. */ | |
1406 | ||
1407 | if (elt->related_value != 0 && elt->related_value != elt) | |
1408 | { | |
b3694847 | 1409 | struct table_elt *p = elt->related_value; |
770ae6cc | 1410 | |
7afe21cc RK |
1411 | while (p->related_value != elt) |
1412 | p = p->related_value; | |
1413 | p->related_value = elt->related_value; | |
1414 | if (p->related_value == p) | |
1415 | p->related_value = 0; | |
1416 | } | |
1417 | ||
9b1549b8 DM |
1418 | /* Now add it to the free element chain. */ |
1419 | elt->next_same_hash = free_element_chain; | |
1420 | free_element_chain = elt; | |
7afe21cc RK |
1421 | } |
1422 | ||
d556d181 EB |
1423 | /* Same as above, but X is a pseudo-register. */ |
1424 | ||
1425 | static void | |
1426 | remove_pseudo_from_table (rtx x, unsigned int hash) | |
1427 | { | |
1428 | struct table_elt *elt; | |
1429 | ||
1430 | /* Because a pseudo-register can be referenced in more than one | |
1431 | mode, we might have to remove more than one table entry. */ | |
1432 | while ((elt = lookup_for_remove (x, hash, VOIDmode))) | |
1433 | remove_from_table (elt, hash); | |
1434 | } | |
1435 | ||
7afe21cc RK |
1436 | /* Look up X in the hash table and return its table element, |
1437 | or 0 if X is not in the table. | |
1438 | ||
1439 | MODE is the machine-mode of X, or if X is an integer constant | |
1440 | with VOIDmode then MODE is the mode with which X will be used. | |
1441 | ||
1442 | Here we are satisfied to find an expression whose tree structure | |
1443 | looks like X. */ | |
1444 | ||
1445 | static struct table_elt * | |
ef4bddc2 | 1446 | lookup (rtx x, unsigned int hash, machine_mode mode) |
7afe21cc | 1447 | { |
b3694847 | 1448 | struct table_elt *p; |
7afe21cc RK |
1449 | |
1450 | for (p = table[hash]; p; p = p->next_same_hash) | |
f8cfc6aa | 1451 | if (mode == p->mode && ((x == p->exp && REG_P (x)) |
0516f6fe | 1452 | || exp_equiv_p (x, p->exp, !REG_P (x), false))) |
7afe21cc RK |
1453 | return p; |
1454 | ||
1455 | return 0; | |
1456 | } | |
1457 | ||
1458 | /* Like `lookup' but don't care whether the table element uses invalid regs. | |
1459 | Also ignore discrepancies in the machine mode of a register. */ | |
1460 | ||
1461 | static struct table_elt * | |
ef4bddc2 | 1462 | lookup_for_remove (rtx x, unsigned int hash, machine_mode mode) |
7afe21cc | 1463 | { |
b3694847 | 1464 | struct table_elt *p; |
7afe21cc | 1465 | |
f8cfc6aa | 1466 | if (REG_P (x)) |
7afe21cc | 1467 | { |
770ae6cc RK |
1468 | unsigned int regno = REGNO (x); |
1469 | ||
7afe21cc RK |
1470 | /* Don't check the machine mode when comparing registers; |
1471 | invalidating (REG:SI 0) also invalidates (REG:DF 0). */ | |
1472 | for (p = table[hash]; p; p = p->next_same_hash) | |
f8cfc6aa | 1473 | if (REG_P (p->exp) |
7afe21cc RK |
1474 | && REGNO (p->exp) == regno) |
1475 | return p; | |
1476 | } | |
1477 | else | |
1478 | { | |
1479 | for (p = table[hash]; p; p = p->next_same_hash) | |
0516f6fe SB |
1480 | if (mode == p->mode |
1481 | && (x == p->exp || exp_equiv_p (x, p->exp, 0, false))) | |
7afe21cc RK |
1482 | return p; |
1483 | } | |
1484 | ||
1485 | return 0; | |
1486 | } | |
1487 | ||
1488 | /* Look for an expression equivalent to X and with code CODE. | |
1489 | If one is found, return that expression. */ | |
1490 | ||
1491 | static rtx | |
7080f735 | 1492 | lookup_as_function (rtx x, enum rtx_code code) |
7afe21cc | 1493 | { |
b3694847 | 1494 | struct table_elt *p |
0516f6fe | 1495 | = lookup (x, SAFE_HASH (x, VOIDmode), GET_MODE (x)); |
770ae6cc | 1496 | |
7afe21cc RK |
1497 | if (p == 0) |
1498 | return 0; | |
1499 | ||
1500 | for (p = p->first_same_value; p; p = p->next_same_value) | |
770ae6cc RK |
1501 | if (GET_CODE (p->exp) == code |
1502 | /* Make sure this is a valid entry in the table. */ | |
0516f6fe | 1503 | && exp_equiv_p (p->exp, p->exp, 1, false)) |
770ae6cc | 1504 | return p->exp; |
278a83b2 | 1505 | |
7afe21cc RK |
1506 | return 0; |
1507 | } | |
1508 | ||
2c5bfdf7 AN |
1509 | /* Insert X in the hash table, assuming HASH is its hash code and |
1510 | CLASSP is an element of the class it should go in (or 0 if a new | |
1511 | class should be made). COST is the code of X and reg_cost is the | |
1512 | cost of registers in X. It is inserted at the proper position to | |
1513 | keep the class in the order cheapest first. | |
7afe21cc RK |
1514 | |
1515 | MODE is the machine-mode of X, or if X is an integer constant | |
1516 | with VOIDmode then MODE is the mode with which X will be used. | |
1517 | ||
1518 | For elements of equal cheapness, the most recent one | |
1519 | goes in front, except that the first element in the list | |
1520 | remains first unless a cheaper element is added. The order of | |
1521 | pseudo-registers does not matter, as canon_reg will be called to | |
830a38ee | 1522 | find the cheapest when a register is retrieved from the table. |
7afe21cc RK |
1523 | |
1524 | The in_memory field in the hash table element is set to 0. | |
1525 | The caller must set it nonzero if appropriate. | |
1526 | ||
1527 | You should call insert_regs (X, CLASSP, MODIFY) before calling here, | |
1528 | and if insert_regs returns a nonzero value | |
1529 | you must then recompute its hash code before calling here. | |
1530 | ||
1531 | If necessary, update table showing constant values of quantities. */ | |
1532 | ||
7afe21cc | 1533 | static struct table_elt * |
2c5bfdf7 | 1534 | insert_with_costs (rtx x, struct table_elt *classp, unsigned int hash, |
ef4bddc2 | 1535 | machine_mode mode, int cost, int reg_cost) |
7afe21cc | 1536 | { |
b3694847 | 1537 | struct table_elt *elt; |
7afe21cc RK |
1538 | |
1539 | /* If X is a register and we haven't made a quantity for it, | |
1540 | something is wrong. */ | |
341c100f | 1541 | gcc_assert (!REG_P (x) || REGNO_QTY_VALID_P (REGNO (x))); |
7afe21cc RK |
1542 | |
1543 | /* If X is a hard register, show it is being put in the table. */ | |
f8cfc6aa | 1544 | if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER) |
09e18274 | 1545 | add_to_hard_reg_set (&hard_regs_in_table, GET_MODE (x), REGNO (x)); |
7afe21cc | 1546 | |
7afe21cc RK |
1547 | /* Put an element for X into the right hash bucket. */ |
1548 | ||
9b1549b8 DM |
1549 | elt = free_element_chain; |
1550 | if (elt) | |
770ae6cc | 1551 | free_element_chain = elt->next_same_hash; |
9b1549b8 | 1552 | else |
5ed6ace5 | 1553 | elt = XNEW (struct table_elt); |
9b1549b8 | 1554 | |
7afe21cc | 1555 | elt->exp = x; |
db048faf | 1556 | elt->canon_exp = NULL_RTX; |
2c5bfdf7 AN |
1557 | elt->cost = cost; |
1558 | elt->regcost = reg_cost; | |
7afe21cc RK |
1559 | elt->next_same_value = 0; |
1560 | elt->prev_same_value = 0; | |
1561 | elt->next_same_hash = table[hash]; | |
1562 | elt->prev_same_hash = 0; | |
1563 | elt->related_value = 0; | |
1564 | elt->in_memory = 0; | |
1565 | elt->mode = mode; | |
389fdba0 | 1566 | elt->is_const = (CONSTANT_P (x) || fixed_base_plus_p (x)); |
7afe21cc RK |
1567 | |
1568 | if (table[hash]) | |
1569 | table[hash]->prev_same_hash = elt; | |
1570 | table[hash] = elt; | |
1571 | ||
1572 | /* Put it into the proper value-class. */ | |
1573 | if (classp) | |
1574 | { | |
1575 | classp = classp->first_same_value; | |
1576 | if (CHEAPER (elt, classp)) | |
f9da5064 | 1577 | /* Insert at the head of the class. */ |
7afe21cc | 1578 | { |
b3694847 | 1579 | struct table_elt *p; |
7afe21cc RK |
1580 | elt->next_same_value = classp; |
1581 | classp->prev_same_value = elt; | |
1582 | elt->first_same_value = elt; | |
1583 | ||
1584 | for (p = classp; p; p = p->next_same_value) | |
1585 | p->first_same_value = elt; | |
1586 | } | |
1587 | else | |
1588 | { | |
1589 | /* Insert not at head of the class. */ | |
1590 | /* Put it after the last element cheaper than X. */ | |
b3694847 | 1591 | struct table_elt *p, *next; |
770ae6cc | 1592 | |
e84a58ff EB |
1593 | for (p = classp; |
1594 | (next = p->next_same_value) && CHEAPER (next, elt); | |
1595 | p = next) | |
1596 | ; | |
770ae6cc | 1597 | |
7afe21cc RK |
1598 | /* Put it after P and before NEXT. */ |
1599 | elt->next_same_value = next; | |
1600 | if (next) | |
1601 | next->prev_same_value = elt; | |
770ae6cc | 1602 | |
7afe21cc RK |
1603 | elt->prev_same_value = p; |
1604 | p->next_same_value = elt; | |
1605 | elt->first_same_value = classp; | |
1606 | } | |
1607 | } | |
1608 | else | |
1609 | elt->first_same_value = elt; | |
1610 | ||
1611 | /* If this is a constant being set equivalent to a register or a register | |
1612 | being set equivalent to a constant, note the constant equivalence. | |
1613 | ||
1614 | If this is a constant, it cannot be equivalent to a different constant, | |
1615 | and a constant is the only thing that can be cheaper than a register. So | |
1616 | we know the register is the head of the class (before the constant was | |
1617 | inserted). | |
1618 | ||
1619 | If this is a register that is not already known equivalent to a | |
1620 | constant, we must check the entire class. | |
1621 | ||
1622 | If this is a register that is already known equivalent to an insn, | |
1bb98cec | 1623 | update the qtys `const_insn' to show that `this_insn' is the latest |
7afe21cc RK |
1624 | insn making that quantity equivalent to the constant. */ |
1625 | ||
f8cfc6aa JQ |
1626 | if (elt->is_const && classp && REG_P (classp->exp) |
1627 | && !REG_P (x)) | |
7afe21cc | 1628 | { |
1bb98cec DM |
1629 | int exp_q = REG_QTY (REGNO (classp->exp)); |
1630 | struct qty_table_elem *exp_ent = &qty_table[exp_q]; | |
1631 | ||
4de249d9 | 1632 | exp_ent->const_rtx = gen_lowpart (exp_ent->mode, x); |
1bb98cec | 1633 | exp_ent->const_insn = this_insn; |
7afe21cc RK |
1634 | } |
1635 | ||
f8cfc6aa | 1636 | else if (REG_P (x) |
1bb98cec DM |
1637 | && classp |
1638 | && ! qty_table[REG_QTY (REGNO (x))].const_rtx | |
f353588a | 1639 | && ! elt->is_const) |
7afe21cc | 1640 | { |
b3694847 | 1641 | struct table_elt *p; |
7afe21cc RK |
1642 | |
1643 | for (p = classp; p != 0; p = p->next_same_value) | |
1644 | { | |
f8cfc6aa | 1645 | if (p->is_const && !REG_P (p->exp)) |
7afe21cc | 1646 | { |
1bb98cec DM |
1647 | int x_q = REG_QTY (REGNO (x)); |
1648 | struct qty_table_elem *x_ent = &qty_table[x_q]; | |
1649 | ||
770ae6cc | 1650 | x_ent->const_rtx |
4de249d9 | 1651 | = gen_lowpart (GET_MODE (x), p->exp); |
1bb98cec | 1652 | x_ent->const_insn = this_insn; |
7afe21cc RK |
1653 | break; |
1654 | } | |
1655 | } | |
1656 | } | |
1657 | ||
f8cfc6aa | 1658 | else if (REG_P (x) |
1bb98cec DM |
1659 | && qty_table[REG_QTY (REGNO (x))].const_rtx |
1660 | && GET_MODE (x) == qty_table[REG_QTY (REGNO (x))].mode) | |
1661 | qty_table[REG_QTY (REGNO (x))].const_insn = this_insn; | |
7afe21cc RK |
1662 | |
1663 | /* If this is a constant with symbolic value, | |
1664 | and it has a term with an explicit integer value, | |
1665 | link it up with related expressions. */ | |
1666 | if (GET_CODE (x) == CONST) | |
1667 | { | |
1668 | rtx subexp = get_related_value (x); | |
2197a88a | 1669 | unsigned subhash; |
7afe21cc RK |
1670 | struct table_elt *subelt, *subelt_prev; |
1671 | ||
1672 | if (subexp != 0) | |
1673 | { | |
1674 | /* Get the integer-free subexpression in the hash table. */ | |
0516f6fe | 1675 | subhash = SAFE_HASH (subexp, mode); |
7afe21cc RK |
1676 | subelt = lookup (subexp, subhash, mode); |
1677 | if (subelt == 0) | |
9714cf43 | 1678 | subelt = insert (subexp, NULL, subhash, mode); |
7afe21cc RK |
1679 | /* Initialize SUBELT's circular chain if it has none. */ |
1680 | if (subelt->related_value == 0) | |
1681 | subelt->related_value = subelt; | |
1682 | /* Find the element in the circular chain that precedes SUBELT. */ | |
1683 | subelt_prev = subelt; | |
1684 | while (subelt_prev->related_value != subelt) | |
1685 | subelt_prev = subelt_prev->related_value; | |
1686 | /* Put new ELT into SUBELT's circular chain just before SUBELT. | |
1687 | This way the element that follows SUBELT is the oldest one. */ | |
1688 | elt->related_value = subelt_prev->related_value; | |
1689 | subelt_prev->related_value = elt; | |
1690 | } | |
1691 | } | |
1692 | ||
1693 | return elt; | |
1694 | } | |
2c5bfdf7 AN |
1695 | |
1696 | /* Wrap insert_with_costs by passing the default costs. */ | |
1697 | ||
1698 | static struct table_elt * | |
1699 | insert (rtx x, struct table_elt *classp, unsigned int hash, | |
ef4bddc2 | 1700 | machine_mode mode) |
2c5bfdf7 | 1701 | { |
e548c9df AM |
1702 | return insert_with_costs (x, classp, hash, mode, |
1703 | COST (x, mode), approx_reg_cost (x)); | |
2c5bfdf7 AN |
1704 | } |
1705 | ||
7afe21cc RK |
1706 | \f |
1707 | /* Given two equivalence classes, CLASS1 and CLASS2, put all the entries from | |
1708 | CLASS2 into CLASS1. This is done when we have reached an insn which makes | |
1709 | the two classes equivalent. | |
1710 | ||
1711 | CLASS1 will be the surviving class; CLASS2 should not be used after this | |
1712 | call. | |
1713 | ||
1714 | Any invalid entries in CLASS2 will not be copied. */ | |
1715 | ||
1716 | static void | |
7080f735 | 1717 | merge_equiv_classes (struct table_elt *class1, struct table_elt *class2) |
7afe21cc | 1718 | { |
32e9fa48 | 1719 | struct table_elt *elt, *next, *new_elt; |
7afe21cc RK |
1720 | |
1721 | /* Ensure we start with the head of the classes. */ | |
1722 | class1 = class1->first_same_value; | |
1723 | class2 = class2->first_same_value; | |
1724 | ||
1725 | /* If they were already equal, forget it. */ | |
1726 | if (class1 == class2) | |
1727 | return; | |
1728 | ||
1729 | for (elt = class2; elt; elt = next) | |
1730 | { | |
770ae6cc | 1731 | unsigned int hash; |
7afe21cc | 1732 | rtx exp = elt->exp; |
ef4bddc2 | 1733 | machine_mode mode = elt->mode; |
7afe21cc RK |
1734 | |
1735 | next = elt->next_same_value; | |
1736 | ||
1737 | /* Remove old entry, make a new one in CLASS1's class. | |
1738 | Don't do this for invalid entries as we cannot find their | |
0f41302f | 1739 | hash code (it also isn't necessary). */ |
0516f6fe | 1740 | if (REG_P (exp) || exp_equiv_p (exp, exp, 1, false)) |
7afe21cc | 1741 | { |
a90fc8e0 RH |
1742 | bool need_rehash = false; |
1743 | ||
7afe21cc | 1744 | hash_arg_in_memory = 0; |
7afe21cc | 1745 | hash = HASH (exp, mode); |
278a83b2 | 1746 | |
f8cfc6aa | 1747 | if (REG_P (exp)) |
a90fc8e0 | 1748 | { |
08a69267 | 1749 | need_rehash = REGNO_QTY_VALID_P (REGNO (exp)); |
a90fc8e0 RH |
1750 | delete_reg_equiv (REGNO (exp)); |
1751 | } | |
278a83b2 | 1752 | |
d556d181 EB |
1753 | if (REG_P (exp) && REGNO (exp) >= FIRST_PSEUDO_REGISTER) |
1754 | remove_pseudo_from_table (exp, hash); | |
1755 | else | |
1756 | remove_from_table (elt, hash); | |
7afe21cc | 1757 | |
dec7aaab | 1758 | if (insert_regs (exp, class1, false) || need_rehash) |
8ae2b8f6 JW |
1759 | { |
1760 | rehash_using_reg (exp); | |
1761 | hash = HASH (exp, mode); | |
1762 | } | |
32e9fa48 KG |
1763 | new_elt = insert (exp, class1, hash, mode); |
1764 | new_elt->in_memory = hash_arg_in_memory; | |
6c4d60f8 JJ |
1765 | if (GET_CODE (exp) == ASM_OPERANDS && elt->cost == MAX_COST) |
1766 | new_elt->cost = MAX_COST; | |
7afe21cc RK |
1767 | } |
1768 | } | |
1769 | } | |
1770 | \f | |
01e752d3 JL |
1771 | /* Flush the entire hash table. */ |
1772 | ||
1773 | static void | |
7080f735 | 1774 | flush_hash_table (void) |
01e752d3 JL |
1775 | { |
1776 | int i; | |
1777 | struct table_elt *p; | |
1778 | ||
9b1549b8 | 1779 | for (i = 0; i < HASH_SIZE; i++) |
01e752d3 JL |
1780 | for (p = table[i]; p; p = table[i]) |
1781 | { | |
1782 | /* Note that invalidate can remove elements | |
1783 | after P in the current hash chain. */ | |
f8cfc6aa | 1784 | if (REG_P (p->exp)) |
524e3576 | 1785 | invalidate (p->exp, VOIDmode); |
01e752d3 JL |
1786 | else |
1787 | remove_from_table (p, i); | |
1788 | } | |
1789 | } | |
14a774a9 | 1790 | \f |
c992c066 RS |
1791 | /* Check whether an anti dependence exists between X and EXP. MODE and |
1792 | ADDR are as for canon_anti_dependence. */ | |
be8ac49a | 1793 | |
c992c066 | 1794 | static bool |
ef4bddc2 | 1795 | check_dependence (const_rtx x, rtx exp, machine_mode mode, rtx addr) |
2ce6dc2f | 1796 | { |
c992c066 RS |
1797 | subrtx_iterator::array_type array; |
1798 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
1799 | { | |
1800 | const_rtx x = *iter; | |
1801 | if (MEM_P (x) && canon_anti_dependence (x, true, exp, mode, addr)) | |
1802 | return true; | |
1803 | } | |
1804 | return false; | |
2ce6dc2f | 1805 | } |
99788e06 AH |
1806 | |
1807 | /* Remove from the hash table, or mark as invalid, all expressions whose | |
17d184e5 | 1808 | values could be altered by storing in register X. */ |
99788e06 AH |
1809 | |
1810 | static void | |
17d184e5 | 1811 | invalidate_reg (rtx x) |
99788e06 AH |
1812 | { |
1813 | gcc_assert (GET_CODE (x) == REG); | |
1814 | ||
1815 | /* If X is a register, dependencies on its contents are recorded | |
1816 | through the qty number mechanism. Just change the qty number of | |
1817 | the register, mark it as invalid for expressions that refer to it, | |
1818 | and remove it itself. */ | |
1819 | unsigned int regno = REGNO (x); | |
1820 | unsigned int hash = HASH (x, GET_MODE (x)); | |
1821 | ||
1822 | /* Remove REGNO from any quantity list it might be on and indicate | |
1823 | that its value might have changed. If it is a pseudo, remove its | |
1824 | entry from the hash table. | |
1825 | ||
1826 | For a hard register, we do the first two actions above for any | |
1827 | additional hard registers corresponding to X. Then, if any of these | |
1828 | registers are in the table, we must remove any REG entries that | |
1829 | overlap these registers. */ | |
1830 | ||
1831 | delete_reg_equiv (regno); | |
1832 | REG_TICK (regno)++; | |
1833 | SUBREG_TICKED (regno) = -1; | |
1834 | ||
1835 | if (regno >= FIRST_PSEUDO_REGISTER) | |
17d184e5 | 1836 | remove_pseudo_from_table (x, hash); |
99788e06 AH |
1837 | else |
1838 | { | |
1839 | HOST_WIDE_INT in_table = TEST_HARD_REG_BIT (hard_regs_in_table, regno); | |
1840 | unsigned int endregno = END_REGNO (x); | |
1841 | unsigned int rn; | |
1842 | struct table_elt *p, *next; | |
1843 | ||
1844 | CLEAR_HARD_REG_BIT (hard_regs_in_table, regno); | |
1845 | ||
1846 | for (rn = regno + 1; rn < endregno; rn++) | |
1847 | { | |
1848 | in_table |= TEST_HARD_REG_BIT (hard_regs_in_table, rn); | |
1849 | CLEAR_HARD_REG_BIT (hard_regs_in_table, rn); | |
1850 | delete_reg_equiv (rn); | |
1851 | REG_TICK (rn)++; | |
1852 | SUBREG_TICKED (rn) = -1; | |
1853 | } | |
1854 | ||
1855 | if (in_table) | |
1856 | for (hash = 0; hash < HASH_SIZE; hash++) | |
1857 | for (p = table[hash]; p; p = next) | |
1858 | { | |
1859 | next = p->next_same_hash; | |
1860 | ||
1861 | if (!REG_P (p->exp) || REGNO (p->exp) >= FIRST_PSEUDO_REGISTER) | |
1862 | continue; | |
1863 | ||
17d184e5 RS |
1864 | unsigned int tregno = REGNO (p->exp); |
1865 | unsigned int tendregno = END_REGNO (p->exp); | |
1866 | if (tendregno > regno && tregno < endregno) | |
1867 | remove_from_table (p, hash); | |
99788e06 AH |
1868 | } |
1869 | } | |
1870 | } | |
1871 | ||
14a774a9 RK |
1872 | /* Remove from the hash table, or mark as invalid, all expressions whose |
1873 | values could be altered by storing in X. X is a register, a subreg, or | |
1874 | a memory reference with nonvarying address (because, when a memory | |
1875 | reference with a varying address is stored in, all memory references are | |
1876 | removed by invalidate_memory so specific invalidation is superfluous). | |
1877 | FULL_MODE, if not VOIDmode, indicates that this much should be | |
1878 | invalidated instead of just the amount indicated by the mode of X. This | |
1879 | is only used for bitfield stores into memory. | |
1880 | ||
1881 | A nonvarying address may be just a register or just a symbol reference, | |
1882 | or it may be either of those plus a numeric offset. */ | |
7afe21cc RK |
1883 | |
1884 | static void | |
ef4bddc2 | 1885 | invalidate (rtx x, machine_mode full_mode) |
7afe21cc | 1886 | { |
b3694847 SS |
1887 | int i; |
1888 | struct table_elt *p; | |
9ddb66ca | 1889 | rtx addr; |
7afe21cc | 1890 | |
14a774a9 | 1891 | switch (GET_CODE (x)) |
7afe21cc | 1892 | { |
14a774a9 | 1893 | case REG: |
17d184e5 | 1894 | invalidate_reg (x); |
7afe21cc | 1895 | return; |
7afe21cc | 1896 | |
14a774a9 | 1897 | case SUBREG: |
bb4034b3 | 1898 | invalidate (SUBREG_REG (x), VOIDmode); |
7afe21cc | 1899 | return; |
aac5cc16 | 1900 | |
14a774a9 | 1901 | case PARALLEL: |
278a83b2 | 1902 | for (i = XVECLEN (x, 0) - 1; i >= 0; --i) |
aac5cc16 RH |
1903 | invalidate (XVECEXP (x, 0, i), VOIDmode); |
1904 | return; | |
aac5cc16 | 1905 | |
14a774a9 RK |
1906 | case EXPR_LIST: |
1907 | /* This is part of a disjoint return value; extract the location in | |
1908 | question ignoring the offset. */ | |
aac5cc16 RH |
1909 | invalidate (XEXP (x, 0), VOIDmode); |
1910 | return; | |
7afe21cc | 1911 | |
14a774a9 | 1912 | case MEM: |
9ddb66ca | 1913 | addr = canon_rtx (get_addr (XEXP (x, 0))); |
db048faf MM |
1914 | /* Calculate the canonical version of X here so that |
1915 | true_dependence doesn't generate new RTL for X on each call. */ | |
1916 | x = canon_rtx (x); | |
1917 | ||
14a774a9 RK |
1918 | /* Remove all hash table elements that refer to overlapping pieces of |
1919 | memory. */ | |
1920 | if (full_mode == VOIDmode) | |
1921 | full_mode = GET_MODE (x); | |
bb4034b3 | 1922 | |
9b1549b8 | 1923 | for (i = 0; i < HASH_SIZE; i++) |
7afe21cc | 1924 | { |
b3694847 | 1925 | struct table_elt *next; |
14a774a9 RK |
1926 | |
1927 | for (p = table[i]; p; p = next) | |
1928 | { | |
1929 | next = p->next_same_hash; | |
db048faf MM |
1930 | if (p->in_memory) |
1931 | { | |
2ce6dc2f JH |
1932 | /* Just canonicalize the expression once; |
1933 | otherwise each time we call invalidate | |
1934 | true_dependence will canonicalize the | |
1935 | expression again. */ | |
1936 | if (!p->canon_exp) | |
1937 | p->canon_exp = canon_rtx (p->exp); | |
c992c066 | 1938 | if (check_dependence (p->canon_exp, x, full_mode, addr)) |
db048faf | 1939 | remove_from_table (p, i); |
db048faf | 1940 | } |
14a774a9 | 1941 | } |
7afe21cc | 1942 | } |
14a774a9 RK |
1943 | return; |
1944 | ||
1945 | default: | |
341c100f | 1946 | gcc_unreachable (); |
7afe21cc RK |
1947 | } |
1948 | } | |
2a1d78d8 JJ |
1949 | |
1950 | /* Invalidate DEST. Used when DEST is not going to be added | |
1951 | into the hash table for some reason, e.g. do_not_record | |
1952 | flagged on it. */ | |
1953 | ||
1954 | static void | |
1955 | invalidate_dest (rtx dest) | |
1956 | { | |
1957 | if (REG_P (dest) | |
1958 | || GET_CODE (dest) == SUBREG | |
1959 | || MEM_P (dest)) | |
1960 | invalidate (dest, VOIDmode); | |
1961 | else if (GET_CODE (dest) == STRICT_LOW_PART | |
1962 | || GET_CODE (dest) == ZERO_EXTRACT) | |
1963 | invalidate (XEXP (dest, 0), GET_MODE (dest)); | |
1964 | } | |
14a774a9 | 1965 | \f |
7afe21cc RK |
1966 | /* Remove all expressions that refer to register REGNO, |
1967 | since they are already invalid, and we are about to | |
1968 | mark that register valid again and don't want the old | |
1969 | expressions to reappear as valid. */ | |
1970 | ||
1971 | static void | |
7080f735 | 1972 | remove_invalid_refs (unsigned int regno) |
7afe21cc | 1973 | { |
770ae6cc RK |
1974 | unsigned int i; |
1975 | struct table_elt *p, *next; | |
7afe21cc | 1976 | |
9b1549b8 | 1977 | for (i = 0; i < HASH_SIZE; i++) |
7afe21cc RK |
1978 | for (p = table[i]; p; p = next) |
1979 | { | |
1980 | next = p->next_same_hash; | |
c9bd6bcd | 1981 | if (!REG_P (p->exp) && refers_to_regno_p (regno, p->exp)) |
7afe21cc RK |
1982 | remove_from_table (p, i); |
1983 | } | |
1984 | } | |
34c73909 | 1985 | |
ddef6bc7 JJ |
1986 | /* Likewise for a subreg with subreg_reg REGNO, subreg_byte OFFSET, |
1987 | and mode MODE. */ | |
34c73909 | 1988 | static void |
91914e56 | 1989 | remove_invalid_subreg_refs (unsigned int regno, poly_uint64 offset, |
ef4bddc2 | 1990 | machine_mode mode) |
34c73909 | 1991 | { |
770ae6cc RK |
1992 | unsigned int i; |
1993 | struct table_elt *p, *next; | |
34c73909 | 1994 | |
9b1549b8 | 1995 | for (i = 0; i < HASH_SIZE; i++) |
34c73909 R |
1996 | for (p = table[i]; p; p = next) |
1997 | { | |
ddef6bc7 | 1998 | rtx exp = p->exp; |
34c73909 | 1999 | next = p->next_same_hash; |
278a83b2 | 2000 | |
f8cfc6aa | 2001 | if (!REG_P (exp) |
34c73909 | 2002 | && (GET_CODE (exp) != SUBREG |
f8cfc6aa | 2003 | || !REG_P (SUBREG_REG (exp)) |
34c73909 | 2004 | || REGNO (SUBREG_REG (exp)) != regno |
91914e56 RS |
2005 | || ranges_maybe_overlap_p (SUBREG_BYTE (exp), |
2006 | GET_MODE_SIZE (GET_MODE (exp)), | |
2007 | offset, GET_MODE_SIZE (mode))) | |
c9bd6bcd | 2008 | && refers_to_regno_p (regno, p->exp)) |
34c73909 R |
2009 | remove_from_table (p, i); |
2010 | } | |
2011 | } | |
7afe21cc RK |
2012 | \f |
2013 | /* Recompute the hash codes of any valid entries in the hash table that | |
2014 | reference X, if X is a register, or SUBREG_REG (X) if X is a SUBREG. | |
2015 | ||
2016 | This is called when we make a jump equivalence. */ | |
2017 | ||
2018 | static void | |
7080f735 | 2019 | rehash_using_reg (rtx x) |
7afe21cc | 2020 | { |
973838fd | 2021 | unsigned int i; |
7afe21cc | 2022 | struct table_elt *p, *next; |
2197a88a | 2023 | unsigned hash; |
7afe21cc RK |
2024 | |
2025 | if (GET_CODE (x) == SUBREG) | |
2026 | x = SUBREG_REG (x); | |
2027 | ||
2028 | /* If X is not a register or if the register is known not to be in any | |
2029 | valid entries in the table, we have no work to do. */ | |
2030 | ||
f8cfc6aa | 2031 | if (!REG_P (x) |
30f72379 MM |
2032 | || REG_IN_TABLE (REGNO (x)) < 0 |
2033 | || REG_IN_TABLE (REGNO (x)) != REG_TICK (REGNO (x))) | |
7afe21cc RK |
2034 | return; |
2035 | ||
2036 | /* Scan all hash chains looking for valid entries that mention X. | |
a90fc8e0 | 2037 | If we find one and it is in the wrong hash chain, move it. */ |
7afe21cc | 2038 | |
9b1549b8 | 2039 | for (i = 0; i < HASH_SIZE; i++) |
7afe21cc RK |
2040 | for (p = table[i]; p; p = next) |
2041 | { | |
2042 | next = p->next_same_hash; | |
a90fc8e0 | 2043 | if (reg_mentioned_p (x, p->exp) |
0516f6fe SB |
2044 | && exp_equiv_p (p->exp, p->exp, 1, false) |
2045 | && i != (hash = SAFE_HASH (p->exp, p->mode))) | |
7afe21cc RK |
2046 | { |
2047 | if (p->next_same_hash) | |
2048 | p->next_same_hash->prev_same_hash = p->prev_same_hash; | |
2049 | ||
2050 | if (p->prev_same_hash) | |
2051 | p->prev_same_hash->next_same_hash = p->next_same_hash; | |
2052 | else | |
2053 | table[i] = p->next_same_hash; | |
2054 | ||
2055 | p->next_same_hash = table[hash]; | |
2056 | p->prev_same_hash = 0; | |
2057 | if (table[hash]) | |
2058 | table[hash]->prev_same_hash = p; | |
2059 | table[hash] = p; | |
2060 | } | |
2061 | } | |
2062 | } | |
2063 | \f | |
7afe21cc | 2064 | /* Remove from the hash table any expression that is a call-clobbered |
311b62ce | 2065 | register in INSN. Also update their TICK values. */ |
7afe21cc RK |
2066 | |
2067 | static void | |
311b62ce | 2068 | invalidate_for_call (rtx_insn *insn) |
7afe21cc | 2069 | { |
311b62ce | 2070 | unsigned int regno; |
2197a88a | 2071 | unsigned hash; |
7afe21cc RK |
2072 | struct table_elt *p, *next; |
2073 | int in_table = 0; | |
c7fb4c7a | 2074 | hard_reg_set_iterator hrsi; |
7afe21cc | 2075 | |
311b62ce RS |
2076 | /* Go through all the hard registers. For each that might be clobbered |
2077 | in call insn INSN, remove the register from quantity chains and update | |
7afe21cc | 2078 | reg_tick if defined. Also see if any of these registers is currently |
311b62ce RS |
2079 | in the table. |
2080 | ||
2081 | ??? We could be more precise for partially-clobbered registers, | |
2082 | and only invalidate values that actually occupy the clobbered part | |
2083 | of the registers. It doesn't seem worth the effort though, since | |
2084 | we shouldn't see this situation much before RA. Whatever choice | |
2085 | we make here has to be consistent with the table walk below, | |
2086 | so any change to this test will require a change there too. */ | |
2087 | HARD_REG_SET callee_clobbers | |
2088 | = insn_callee_abi (insn).full_and_partial_reg_clobbers (); | |
2089 | EXECUTE_IF_SET_IN_HARD_REG_SET (callee_clobbers, 0, regno, hrsi) | |
c7fb4c7a SB |
2090 | { |
2091 | delete_reg_equiv (regno); | |
2092 | if (REG_TICK (regno) >= 0) | |
2093 | { | |
2094 | REG_TICK (regno)++; | |
2095 | SUBREG_TICKED (regno) = -1; | |
2096 | } | |
2097 | in_table |= (TEST_HARD_REG_BIT (hard_regs_in_table, regno) != 0); | |
2098 | } | |
7afe21cc RK |
2099 | |
2100 | /* In the case where we have no call-clobbered hard registers in the | |
2101 | table, we are done. Otherwise, scan the table and remove any | |
2102 | entry that overlaps a call-clobbered register. */ | |
2103 | ||
2104 | if (in_table) | |
9b1549b8 | 2105 | for (hash = 0; hash < HASH_SIZE; hash++) |
7afe21cc RK |
2106 | for (p = table[hash]; p; p = next) |
2107 | { | |
2108 | next = p->next_same_hash; | |
2109 | ||
f8cfc6aa | 2110 | if (!REG_P (p->exp) |
7afe21cc RK |
2111 | || REGNO (p->exp) >= FIRST_PSEUDO_REGISTER) |
2112 | continue; | |
2113 | ||
311b62ce RS |
2114 | /* This must use the same test as above rather than the |
2115 | more accurate clobbers_reg_p. */ | |
2116 | if (overlaps_hard_reg_set_p (callee_clobbers, GET_MODE (p->exp), | |
2117 | REGNO (p->exp))) | |
2118 | remove_from_table (p, hash); | |
7afe21cc RK |
2119 | } |
2120 | } | |
2121 | \f | |
2122 | /* Given an expression X of type CONST, | |
2123 | and ELT which is its table entry (or 0 if it | |
2124 | is not in the hash table), | |
2125 | return an alternate expression for X as a register plus integer. | |
2126 | If none can be found, return 0. */ | |
2127 | ||
2128 | static rtx | |
7080f735 | 2129 | use_related_value (rtx x, struct table_elt *elt) |
7afe21cc | 2130 | { |
b3694847 SS |
2131 | struct table_elt *relt = 0; |
2132 | struct table_elt *p, *q; | |
906c4e36 | 2133 | HOST_WIDE_INT offset; |
7afe21cc RK |
2134 | |
2135 | /* First, is there anything related known? | |
2136 | If we have a table element, we can tell from that. | |
2137 | Otherwise, must look it up. */ | |
2138 | ||
2139 | if (elt != 0 && elt->related_value != 0) | |
2140 | relt = elt; | |
2141 | else if (elt == 0 && GET_CODE (x) == CONST) | |
2142 | { | |
2143 | rtx subexp = get_related_value (x); | |
2144 | if (subexp != 0) | |
2145 | relt = lookup (subexp, | |
0516f6fe | 2146 | SAFE_HASH (subexp, GET_MODE (subexp)), |
7afe21cc RK |
2147 | GET_MODE (subexp)); |
2148 | } | |
2149 | ||
2150 | if (relt == 0) | |
2151 | return 0; | |
2152 | ||
2153 | /* Search all related table entries for one that has an | |
2154 | equivalent register. */ | |
2155 | ||
2156 | p = relt; | |
2157 | while (1) | |
2158 | { | |
2159 | /* This loop is strange in that it is executed in two different cases. | |
2160 | The first is when X is already in the table. Then it is searching | |
2161 | the RELATED_VALUE list of X's class (RELT). The second case is when | |
2162 | X is not in the table. Then RELT points to a class for the related | |
2163 | value. | |
2164 | ||
2165 | Ensure that, whatever case we are in, that we ignore classes that have | |
2166 | the same value as X. */ | |
2167 | ||
2168 | if (rtx_equal_p (x, p->exp)) | |
2169 | q = 0; | |
2170 | else | |
2171 | for (q = p->first_same_value; q; q = q->next_same_value) | |
f8cfc6aa | 2172 | if (REG_P (q->exp)) |
7afe21cc RK |
2173 | break; |
2174 | ||
2175 | if (q) | |
2176 | break; | |
2177 | ||
2178 | p = p->related_value; | |
2179 | ||
2180 | /* We went all the way around, so there is nothing to be found. | |
2181 | Alternatively, perhaps RELT was in the table for some other reason | |
2182 | and it has no related values recorded. */ | |
2183 | if (p == relt || p == 0) | |
2184 | break; | |
2185 | } | |
2186 | ||
2187 | if (q == 0) | |
2188 | return 0; | |
2189 | ||
2190 | offset = (get_integer_term (x) - get_integer_term (p->exp)); | |
2191 | /* Note: OFFSET may be 0 if P->xexp and X are related by commutativity. */ | |
0a81f074 | 2192 | return plus_constant (q->mode, q->exp, offset); |
7afe21cc RK |
2193 | } |
2194 | \f | |
e855c69d | 2195 | |
6462bb43 AO |
2196 | /* Hash a string. Just add its bytes up. */ |
2197 | static inline unsigned | |
0516f6fe | 2198 | hash_rtx_string (const char *ps) |
6462bb43 AO |
2199 | { |
2200 | unsigned hash = 0; | |
68252e27 KH |
2201 | const unsigned char *p = (const unsigned char *) ps; |
2202 | ||
6462bb43 AO |
2203 | if (p) |
2204 | while (*p) | |
2205 | hash += *p++; | |
2206 | ||
2207 | return hash; | |
2208 | } | |
2209 | ||
47fa3cef UB |
2210 | /* Hash an rtx. We are careful to make sure the value is never negative. |
2211 | Equivalent registers hash identically. | |
2212 | MODE is used in hashing for CONST_INTs only; | |
2213 | otherwise the mode of X is used. | |
2214 | ||
2215 | Store 1 in DO_NOT_RECORD_P if any subexpression is volatile. | |
2216 | ||
2217 | If HASH_ARG_IN_MEMORY_P is not NULL, store 1 in it if X contains | |
2218 | a MEM rtx which does not have the MEM_READONLY_P flag set. | |
2219 | ||
2220 | Note that cse_insn knows that the hash code of a MEM expression | |
2221 | is just (int) MEM plus the hash code of the address. | |
2222 | ||
2223 | Call CB on each rtx if CB is not NULL. | |
e855c69d | 2224 | When the callback returns true, we continue with the new rtx. */ |
7afe21cc | 2225 | |
0516f6fe | 2226 | unsigned |
47fa3cef UB |
2227 | hash_rtx (const_rtx x, machine_mode mode, |
2228 | int *do_not_record_p, int *hash_arg_in_memory_p, | |
2229 | bool have_reg_qty, hash_rtx_callback_function cb) | |
7afe21cc | 2230 | { |
b3694847 SS |
2231 | int i, j; |
2232 | unsigned hash = 0; | |
2233 | enum rtx_code code; | |
2234 | const char *fmt; | |
ef4bddc2 | 2235 | machine_mode newmode; |
e855c69d | 2236 | rtx newx; |
7afe21cc | 2237 | |
0516f6fe SB |
2238 | /* Used to turn recursion into iteration. We can't rely on GCC's |
2239 | tail-recursion elimination since we need to keep accumulating values | |
2240 | in HASH. */ | |
7afe21cc RK |
2241 | repeat: |
2242 | if (x == 0) | |
2243 | return hash; | |
2244 | ||
e855c69d | 2245 | /* Invoke the callback first. */ |
b8698a0f | 2246 | if (cb != NULL |
e855c69d AB |
2247 | && ((*cb) (x, mode, &newx, &newmode))) |
2248 | { | |
47fa3cef UB |
2249 | hash += hash_rtx (newx, newmode, do_not_record_p, |
2250 | hash_arg_in_memory_p, have_reg_qty, cb); | |
e855c69d AB |
2251 | return hash; |
2252 | } | |
2253 | ||
7afe21cc RK |
2254 | code = GET_CODE (x); |
2255 | switch (code) | |
2256 | { | |
2257 | case REG: | |
2258 | { | |
770ae6cc | 2259 | unsigned int regno = REGNO (x); |
7afe21cc | 2260 | |
e855c69d | 2261 | if (do_not_record_p && !reload_completed) |
7afe21cc | 2262 | { |
0516f6fe SB |
2263 | /* On some machines, we can't record any non-fixed hard register, |
2264 | because extending its life will cause reload problems. We | |
2265 | consider ap, fp, sp, gp to be fixed for this purpose. | |
2266 | ||
2267 | We also consider CCmode registers to be fixed for this purpose; | |
2268 | failure to do so leads to failure to simplify 0<100 type of | |
2269 | conditionals. | |
2270 | ||
2271 | On all machines, we can't record any global registers. | |
2272 | Nor should we record any register that is in a small | |
07b8f0a8 | 2273 | class, as defined by TARGET_CLASS_LIKELY_SPILLED_P. */ |
0516f6fe SB |
2274 | bool record; |
2275 | ||
2276 | if (regno >= FIRST_PSEUDO_REGISTER) | |
2277 | record = true; | |
2278 | else if (x == frame_pointer_rtx | |
2279 | || x == hard_frame_pointer_rtx | |
2280 | || x == arg_pointer_rtx | |
2281 | || x == stack_pointer_rtx | |
2282 | || x == pic_offset_table_rtx) | |
2283 | record = true; | |
2284 | else if (global_regs[regno]) | |
2285 | record = false; | |
2286 | else if (fixed_regs[regno]) | |
2287 | record = true; | |
2288 | else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) | |
2289 | record = true; | |
42db504c | 2290 | else if (targetm.small_register_classes_for_mode_p (GET_MODE (x))) |
0516f6fe | 2291 | record = false; |
07b8f0a8 | 2292 | else if (targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno))) |
0516f6fe SB |
2293 | record = false; |
2294 | else | |
2295 | record = true; | |
2296 | ||
2297 | if (!record) | |
2298 | { | |
2299 | *do_not_record_p = 1; | |
2300 | return 0; | |
2301 | } | |
7afe21cc | 2302 | } |
770ae6cc | 2303 | |
0516f6fe SB |
2304 | hash += ((unsigned int) REG << 7); |
2305 | hash += (have_reg_qty ? (unsigned) REG_QTY (regno) : regno); | |
2197a88a | 2306 | return hash; |
7afe21cc RK |
2307 | } |
2308 | ||
34c73909 R |
2309 | /* We handle SUBREG of a REG specially because the underlying |
2310 | reg changes its hash value with every value change; we don't | |
2311 | want to have to forget unrelated subregs when one subreg changes. */ | |
2312 | case SUBREG: | |
2313 | { | |
f8cfc6aa | 2314 | if (REG_P (SUBREG_REG (x))) |
34c73909 | 2315 | { |
0516f6fe | 2316 | hash += (((unsigned int) SUBREG << 7) |
ddef6bc7 | 2317 | + REGNO (SUBREG_REG (x)) |
91914e56 RS |
2318 | + (constant_lower_bound (SUBREG_BYTE (x)) |
2319 | / UNITS_PER_WORD)); | |
34c73909 R |
2320 | return hash; |
2321 | } | |
2322 | break; | |
2323 | } | |
2324 | ||
7afe21cc | 2325 | case CONST_INT: |
0516f6fe SB |
2326 | hash += (((unsigned int) CONST_INT << 7) + (unsigned int) mode |
2327 | + (unsigned int) INTVAL (x)); | |
2328 | return hash; | |
7afe21cc | 2329 | |
807e902e KZ |
2330 | case CONST_WIDE_INT: |
2331 | for (i = 0; i < CONST_WIDE_INT_NUNITS (x); i++) | |
2332 | hash += CONST_WIDE_INT_ELT (x, i); | |
2333 | return hash; | |
2334 | ||
0c12fc9b RS |
2335 | case CONST_POLY_INT: |
2336 | { | |
2337 | inchash::hash h; | |
2338 | h.add_int (hash); | |
2339 | for (unsigned int i = 0; i < NUM_POLY_INT_COEFFS; ++i) | |
2340 | h.add_wide_int (CONST_POLY_INT_COEFFS (x)[i]); | |
2341 | return h.end (); | |
2342 | } | |
2343 | ||
7afe21cc RK |
2344 | case CONST_DOUBLE: |
2345 | /* This is like the general case, except that it only counts | |
2346 | the integers representing the constant. */ | |
0516f6fe | 2347 | hash += (unsigned int) code + (unsigned int) GET_MODE (x); |
807e902e | 2348 | if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (x) == VOIDmode) |
0516f6fe SB |
2349 | hash += ((unsigned int) CONST_DOUBLE_LOW (x) |
2350 | + (unsigned int) CONST_DOUBLE_HIGH (x)); | |
807e902e KZ |
2351 | else |
2352 | hash += real_hash (CONST_DOUBLE_REAL_VALUE (x)); | |
7afe21cc RK |
2353 | return hash; |
2354 | ||
091a3ac7 CF |
2355 | case CONST_FIXED: |
2356 | hash += (unsigned int) code + (unsigned int) GET_MODE (x); | |
2357 | hash += fixed_hash (CONST_FIXED_VALUE (x)); | |
2358 | return hash; | |
2359 | ||
69ef87e2 AH |
2360 | case CONST_VECTOR: |
2361 | { | |
2362 | int units; | |
2363 | rtx elt; | |
2364 | ||
16c78b66 | 2365 | units = const_vector_encoded_nelts (x); |
69ef87e2 AH |
2366 | |
2367 | for (i = 0; i < units; ++i) | |
2368 | { | |
16c78b66 | 2369 | elt = CONST_VECTOR_ENCODED_ELT (x, i); |
47fa3cef UB |
2370 | hash += hash_rtx (elt, GET_MODE (elt), |
2371 | do_not_record_p, hash_arg_in_memory_p, | |
2372 | have_reg_qty, cb); | |
69ef87e2 AH |
2373 | } |
2374 | ||
2375 | return hash; | |
2376 | } | |
2377 | ||
7afe21cc RK |
2378 | /* Assume there is only one rtx object for any given label. */ |
2379 | case LABEL_REF: | |
0516f6fe SB |
2380 | /* We don't hash on the address of the CODE_LABEL to avoid bootstrap |
2381 | differences and differences between each stage's debugging dumps. */ | |
2382 | hash += (((unsigned int) LABEL_REF << 7) | |
04a121a7 | 2383 | + CODE_LABEL_NUMBER (label_ref_label (x))); |
2197a88a | 2384 | return hash; |
7afe21cc RK |
2385 | |
2386 | case SYMBOL_REF: | |
0516f6fe SB |
2387 | { |
2388 | /* Don't hash on the symbol's address to avoid bootstrap differences. | |
2389 | Different hash values may cause expressions to be recorded in | |
2390 | different orders and thus different registers to be used in the | |
2391 | final assembler. This also avoids differences in the dump files | |
2392 | between various stages. */ | |
2393 | unsigned int h = 0; | |
2394 | const unsigned char *p = (const unsigned char *) XSTR (x, 0); | |
2395 | ||
2396 | while (*p) | |
2397 | h += (h << 7) + *p++; /* ??? revisit */ | |
2398 | ||
2399 | hash += ((unsigned int) SYMBOL_REF << 7) + h; | |
2400 | return hash; | |
2401 | } | |
7afe21cc RK |
2402 | |
2403 | case MEM: | |
14a774a9 RK |
2404 | /* We don't record if marked volatile or if BLKmode since we don't |
2405 | know the size of the move. */ | |
e855c69d | 2406 | if (do_not_record_p && (MEM_VOLATILE_P (x) || GET_MODE (x) == BLKmode)) |
7afe21cc | 2407 | { |
0516f6fe | 2408 | *do_not_record_p = 1; |
7afe21cc RK |
2409 | return 0; |
2410 | } | |
0516f6fe SB |
2411 | if (hash_arg_in_memory_p && !MEM_READONLY_P (x)) |
2412 | *hash_arg_in_memory_p = 1; | |
4977bab6 | 2413 | |
7afe21cc RK |
2414 | /* Now that we have already found this special case, |
2415 | might as well speed it up as much as possible. */ | |
2197a88a | 2416 | hash += (unsigned) MEM; |
7afe21cc RK |
2417 | x = XEXP (x, 0); |
2418 | goto repeat; | |
2419 | ||
bb07060a JW |
2420 | case USE: |
2421 | /* A USE that mentions non-volatile memory needs special | |
2422 | handling since the MEM may be BLKmode which normally | |
2423 | prevents an entry from being made. Pure calls are | |
0516f6fe | 2424 | marked by a USE which mentions BLKmode memory. |
e53b6e56 | 2425 | See calls.cc:emit_call_1. */ |
3c0cb5de | 2426 | if (MEM_P (XEXP (x, 0)) |
bb07060a JW |
2427 | && ! MEM_VOLATILE_P (XEXP (x, 0))) |
2428 | { | |
68252e27 | 2429 | hash += (unsigned) USE; |
bb07060a JW |
2430 | x = XEXP (x, 0); |
2431 | ||
0516f6fe SB |
2432 | if (hash_arg_in_memory_p && !MEM_READONLY_P (x)) |
2433 | *hash_arg_in_memory_p = 1; | |
bb07060a JW |
2434 | |
2435 | /* Now that we have already found this special case, | |
2436 | might as well speed it up as much as possible. */ | |
2437 | hash += (unsigned) MEM; | |
2438 | x = XEXP (x, 0); | |
2439 | goto repeat; | |
2440 | } | |
2441 | break; | |
2442 | ||
7afe21cc RK |
2443 | case PRE_DEC: |
2444 | case PRE_INC: | |
2445 | case POST_DEC: | |
2446 | case POST_INC: | |
4b983fdc RH |
2447 | case PRE_MODIFY: |
2448 | case POST_MODIFY: | |
7afe21cc | 2449 | case PC: |
7afe21cc RK |
2450 | case CALL: |
2451 | case UNSPEC_VOLATILE: | |
e855c69d AB |
2452 | if (do_not_record_p) { |
2453 | *do_not_record_p = 1; | |
2454 | return 0; | |
2455 | } | |
2456 | else | |
2457 | return hash; | |
2458 | break; | |
7afe21cc RK |
2459 | |
2460 | case ASM_OPERANDS: | |
e855c69d | 2461 | if (do_not_record_p && MEM_VOLATILE_P (x)) |
7afe21cc | 2462 | { |
0516f6fe | 2463 | *do_not_record_p = 1; |
7afe21cc RK |
2464 | return 0; |
2465 | } | |
6462bb43 AO |
2466 | else |
2467 | { | |
2468 | /* We don't want to take the filename and line into account. */ | |
2469 | hash += (unsigned) code + (unsigned) GET_MODE (x) | |
0516f6fe SB |
2470 | + hash_rtx_string (ASM_OPERANDS_TEMPLATE (x)) |
2471 | + hash_rtx_string (ASM_OPERANDS_OUTPUT_CONSTRAINT (x)) | |
6462bb43 AO |
2472 | + (unsigned) ASM_OPERANDS_OUTPUT_IDX (x); |
2473 | ||
2474 | if (ASM_OPERANDS_INPUT_LENGTH (x)) | |
2475 | { | |
2476 | for (i = 1; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) | |
2477 | { | |
47fa3cef UB |
2478 | hash += (hash_rtx (ASM_OPERANDS_INPUT (x, i), |
2479 | GET_MODE (ASM_OPERANDS_INPUT (x, i)), | |
2480 | do_not_record_p, hash_arg_in_memory_p, | |
2481 | have_reg_qty, cb) | |
0516f6fe | 2482 | + hash_rtx_string |
e855c69d | 2483 | (ASM_OPERANDS_INPUT_CONSTRAINT (x, i))); |
6462bb43 AO |
2484 | } |
2485 | ||
0516f6fe | 2486 | hash += hash_rtx_string (ASM_OPERANDS_INPUT_CONSTRAINT (x, 0)); |
6462bb43 AO |
2487 | x = ASM_OPERANDS_INPUT (x, 0); |
2488 | mode = GET_MODE (x); | |
2489 | goto repeat; | |
2490 | } | |
2491 | ||
2492 | return hash; | |
2493 | } | |
e9a25f70 | 2494 | break; |
278a83b2 | 2495 | |
e9a25f70 JL |
2496 | default: |
2497 | break; | |
7afe21cc RK |
2498 | } |
2499 | ||
2500 | i = GET_RTX_LENGTH (code) - 1; | |
2197a88a | 2501 | hash += (unsigned) code + (unsigned) GET_MODE (x); |
7afe21cc RK |
2502 | fmt = GET_RTX_FORMAT (code); |
2503 | for (; i >= 0; i--) | |
2504 | { | |
341c100f | 2505 | switch (fmt[i]) |
7afe21cc | 2506 | { |
341c100f | 2507 | case 'e': |
7afe21cc RK |
2508 | /* If we are about to do the last recursive call |
2509 | needed at this level, change it into iteration. | |
2510 | This function is called enough to be worth it. */ | |
2511 | if (i == 0) | |
2512 | { | |
0516f6fe | 2513 | x = XEXP (x, i); |
7afe21cc RK |
2514 | goto repeat; |
2515 | } | |
b8698a0f | 2516 | |
47fa3cef UB |
2517 | hash += hash_rtx (XEXP (x, i), VOIDmode, do_not_record_p, |
2518 | hash_arg_in_memory_p, | |
2519 | have_reg_qty, cb); | |
341c100f | 2520 | break; |
0516f6fe | 2521 | |
341c100f NS |
2522 | case 'E': |
2523 | for (j = 0; j < XVECLEN (x, i); j++) | |
47fa3cef UB |
2524 | hash += hash_rtx (XVECEXP (x, i, j), VOIDmode, do_not_record_p, |
2525 | hash_arg_in_memory_p, | |
2526 | have_reg_qty, cb); | |
341c100f | 2527 | break; |
0516f6fe | 2528 | |
341c100f NS |
2529 | case 's': |
2530 | hash += hash_rtx_string (XSTR (x, i)); | |
2531 | break; | |
2532 | ||
2533 | case 'i': | |
2534 | hash += (unsigned int) XINT (x, i); | |
2535 | break; | |
2536 | ||
91914e56 RS |
2537 | case 'p': |
2538 | hash += constant_lower_bound (SUBREG_BYTE (x)); | |
2539 | break; | |
2540 | ||
341c100f NS |
2541 | case '0': case 't': |
2542 | /* Unused. */ | |
2543 | break; | |
2544 | ||
2545 | default: | |
2546 | gcc_unreachable (); | |
2547 | } | |
7afe21cc | 2548 | } |
0516f6fe | 2549 | |
7afe21cc RK |
2550 | return hash; |
2551 | } | |
2552 | ||
0516f6fe SB |
2553 | /* Hash an rtx X for cse via hash_rtx. |
2554 | Stores 1 in do_not_record if any subexpression is volatile. | |
2555 | Stores 1 in hash_arg_in_memory if X contains a mem rtx which | |
3e55d79b | 2556 | does not have the MEM_READONLY_P flag set. */ |
0516f6fe SB |
2557 | |
2558 | static inline unsigned | |
ef4bddc2 | 2559 | canon_hash (rtx x, machine_mode mode) |
0516f6fe SB |
2560 | { |
2561 | return hash_rtx (x, mode, &do_not_record, &hash_arg_in_memory, true); | |
2562 | } | |
2563 | ||
2564 | /* Like canon_hash but with no side effects, i.e. do_not_record | |
2565 | and hash_arg_in_memory are not changed. */ | |
7afe21cc | 2566 | |
0516f6fe | 2567 | static inline unsigned |
ef4bddc2 | 2568 | safe_hash (rtx x, machine_mode mode) |
7afe21cc | 2569 | { |
0516f6fe SB |
2570 | int dummy_do_not_record; |
2571 | return hash_rtx (x, mode, &dummy_do_not_record, NULL, true); | |
7afe21cc RK |
2572 | } |
2573 | \f | |
dec7aaab | 2574 | /* Return true iff X and Y would canonicalize into the same thing, |
7afe21cc RK |
2575 | without actually constructing the canonicalization of either one. |
2576 | If VALIDATE is nonzero, | |
2577 | we assume X is an expression being processed from the rtl | |
2578 | and Y was found in the hash table. We check register refs | |
2579 | in Y for being marked as valid. | |
2580 | ||
0516f6fe | 2581 | If FOR_GCSE is true, we compare X and Y for equivalence for GCSE. */ |
7afe21cc | 2582 | |
dec7aaab | 2583 | bool |
4f588890 | 2584 | exp_equiv_p (const_rtx x, const_rtx y, int validate, bool for_gcse) |
7afe21cc | 2585 | { |
b3694847 SS |
2586 | int i, j; |
2587 | enum rtx_code code; | |
2588 | const char *fmt; | |
7afe21cc RK |
2589 | |
2590 | /* Note: it is incorrect to assume an expression is equivalent to itself | |
2591 | if VALIDATE is nonzero. */ | |
2592 | if (x == y && !validate) | |
dec7aaab | 2593 | return true; |
0516f6fe | 2594 | |
7afe21cc RK |
2595 | if (x == 0 || y == 0) |
2596 | return x == y; | |
2597 | ||
2598 | code = GET_CODE (x); | |
2599 | if (code != GET_CODE (y)) | |
dec7aaab | 2600 | return false; |
7afe21cc RK |
2601 | |
2602 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
2603 | if (GET_MODE (x) != GET_MODE (y)) | |
dec7aaab | 2604 | return false; |
7afe21cc | 2605 | |
5932a4d4 | 2606 | /* MEMs referring to different address space are not equivalent. */ |
09e881c9 | 2607 | if (code == MEM && MEM_ADDR_SPACE (x) != MEM_ADDR_SPACE (y)) |
dec7aaab | 2608 | return false; |
09e881c9 | 2609 | |
7afe21cc RK |
2610 | switch (code) |
2611 | { | |
2612 | case PC: | |
d8116890 | 2613 | CASE_CONST_UNIQUE: |
c13e8210 | 2614 | return x == y; |
7afe21cc | 2615 | |
a87d3f96 RS |
2616 | case CONST_VECTOR: |
2617 | if (!same_vector_encodings_p (x, y)) | |
2618 | return false; | |
2619 | break; | |
2620 | ||
7afe21cc | 2621 | case LABEL_REF: |
04a121a7 | 2622 | return label_ref_label (x) == label_ref_label (y); |
7afe21cc | 2623 | |
f54d4924 RK |
2624 | case SYMBOL_REF: |
2625 | return XSTR (x, 0) == XSTR (y, 0); | |
2626 | ||
7afe21cc | 2627 | case REG: |
0516f6fe SB |
2628 | if (for_gcse) |
2629 | return REGNO (x) == REGNO (y); | |
2630 | else | |
2631 | { | |
2632 | unsigned int regno = REGNO (y); | |
2633 | unsigned int i; | |
09e18274 | 2634 | unsigned int endregno = END_REGNO (y); |
7afe21cc | 2635 | |
0516f6fe SB |
2636 | /* If the quantities are not the same, the expressions are not |
2637 | equivalent. If there are and we are not to validate, they | |
2638 | are equivalent. Otherwise, ensure all regs are up-to-date. */ | |
7afe21cc | 2639 | |
0516f6fe | 2640 | if (REG_QTY (REGNO (x)) != REG_QTY (regno)) |
dec7aaab | 2641 | return false; |
0516f6fe SB |
2642 | |
2643 | if (! validate) | |
dec7aaab | 2644 | return true; |
0516f6fe SB |
2645 | |
2646 | for (i = regno; i < endregno; i++) | |
2647 | if (REG_IN_TABLE (i) != REG_TICK (i)) | |
dec7aaab | 2648 | return false; |
7afe21cc | 2649 | |
dec7aaab | 2650 | return true; |
0516f6fe | 2651 | } |
7afe21cc | 2652 | |
0516f6fe SB |
2653 | case MEM: |
2654 | if (for_gcse) | |
2655 | { | |
0516f6fe SB |
2656 | /* A volatile mem should not be considered equivalent to any |
2657 | other. */ | |
2658 | if (MEM_VOLATILE_P (x) || MEM_VOLATILE_P (y)) | |
dec7aaab | 2659 | return false; |
8a76c4a0 JJ |
2660 | |
2661 | /* Can't merge two expressions in different alias sets, since we | |
2662 | can decide that the expression is transparent in a block when | |
2663 | it isn't, due to it being set with the different alias set. | |
2664 | ||
2665 | Also, can't merge two expressions with different MEM_ATTRS. | |
2666 | They could e.g. be two different entities allocated into the | |
2667 | same space on the stack (see e.g. PR25130). In that case, the | |
2668 | MEM addresses can be the same, even though the two MEMs are | |
2669 | absolutely not equivalent. | |
2670 | ||
2671 | But because really all MEM attributes should be the same for | |
2672 | equivalent MEMs, we just use the invariant that MEMs that have | |
2673 | the same attributes share the same mem_attrs data structure. */ | |
96b3c03f | 2674 | if (!mem_attrs_eq_p (MEM_ATTRS (x), MEM_ATTRS (y))) |
dec7aaab | 2675 | return false; |
e304caa4 EB |
2676 | |
2677 | /* If we are handling exceptions, we cannot consider two expressions | |
2678 | with different trapping status as equivalent, because simple_mem | |
2679 | might accept one and reject the other. */ | |
2680 | if (cfun->can_throw_non_call_exceptions | |
2681 | && (MEM_NOTRAP_P (x) != MEM_NOTRAP_P (y))) | |
dec7aaab | 2682 | return false; |
0516f6fe SB |
2683 | } |
2684 | break; | |
7afe21cc RK |
2685 | |
2686 | /* For commutative operations, check both orders. */ | |
2687 | case PLUS: | |
2688 | case MULT: | |
2689 | case AND: | |
2690 | case IOR: | |
2691 | case XOR: | |
2692 | case NE: | |
2693 | case EQ: | |
0516f6fe SB |
2694 | return ((exp_equiv_p (XEXP (x, 0), XEXP (y, 0), |
2695 | validate, for_gcse) | |
7afe21cc | 2696 | && exp_equiv_p (XEXP (x, 1), XEXP (y, 1), |
0516f6fe | 2697 | validate, for_gcse)) |
7afe21cc | 2698 | || (exp_equiv_p (XEXP (x, 0), XEXP (y, 1), |
0516f6fe | 2699 | validate, for_gcse) |
7afe21cc | 2700 | && exp_equiv_p (XEXP (x, 1), XEXP (y, 0), |
0516f6fe | 2701 | validate, for_gcse))); |
278a83b2 | 2702 | |
6462bb43 AO |
2703 | case ASM_OPERANDS: |
2704 | /* We don't use the generic code below because we want to | |
2705 | disregard filename and line numbers. */ | |
2706 | ||
2707 | /* A volatile asm isn't equivalent to any other. */ | |
2708 | if (MEM_VOLATILE_P (x) || MEM_VOLATILE_P (y)) | |
dec7aaab | 2709 | return false; |
6462bb43 AO |
2710 | |
2711 | if (GET_MODE (x) != GET_MODE (y) | |
2712 | || strcmp (ASM_OPERANDS_TEMPLATE (x), ASM_OPERANDS_TEMPLATE (y)) | |
2713 | || strcmp (ASM_OPERANDS_OUTPUT_CONSTRAINT (x), | |
2714 | ASM_OPERANDS_OUTPUT_CONSTRAINT (y)) | |
2715 | || ASM_OPERANDS_OUTPUT_IDX (x) != ASM_OPERANDS_OUTPUT_IDX (y) | |
2716 | || ASM_OPERANDS_INPUT_LENGTH (x) != ASM_OPERANDS_INPUT_LENGTH (y)) | |
dec7aaab | 2717 | return false; |
6462bb43 AO |
2718 | |
2719 | if (ASM_OPERANDS_INPUT_LENGTH (x)) | |
2720 | { | |
2721 | for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--) | |
2722 | if (! exp_equiv_p (ASM_OPERANDS_INPUT (x, i), | |
2723 | ASM_OPERANDS_INPUT (y, i), | |
0516f6fe | 2724 | validate, for_gcse) |
6462bb43 AO |
2725 | || strcmp (ASM_OPERANDS_INPUT_CONSTRAINT (x, i), |
2726 | ASM_OPERANDS_INPUT_CONSTRAINT (y, i))) | |
dec7aaab | 2727 | return false; |
6462bb43 AO |
2728 | } |
2729 | ||
dec7aaab | 2730 | return true; |
6462bb43 | 2731 | |
e9a25f70 JL |
2732 | default: |
2733 | break; | |
7afe21cc RK |
2734 | } |
2735 | ||
2736 | /* Compare the elements. If any pair of corresponding elements | |
0516f6fe | 2737 | fail to match, return 0 for the whole thing. */ |
7afe21cc RK |
2738 | |
2739 | fmt = GET_RTX_FORMAT (code); | |
2740 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2741 | { | |
906c4e36 | 2742 | switch (fmt[i]) |
7afe21cc | 2743 | { |
906c4e36 | 2744 | case 'e': |
0516f6fe SB |
2745 | if (! exp_equiv_p (XEXP (x, i), XEXP (y, i), |
2746 | validate, for_gcse)) | |
dec7aaab | 2747 | return false; |
906c4e36 RK |
2748 | break; |
2749 | ||
2750 | case 'E': | |
7afe21cc RK |
2751 | if (XVECLEN (x, i) != XVECLEN (y, i)) |
2752 | return 0; | |
2753 | for (j = 0; j < XVECLEN (x, i); j++) | |
2754 | if (! exp_equiv_p (XVECEXP (x, i, j), XVECEXP (y, i, j), | |
0516f6fe | 2755 | validate, for_gcse)) |
dec7aaab | 2756 | return false; |
906c4e36 RK |
2757 | break; |
2758 | ||
2759 | case 's': | |
7afe21cc | 2760 | if (strcmp (XSTR (x, i), XSTR (y, i))) |
dec7aaab | 2761 | return false; |
906c4e36 RK |
2762 | break; |
2763 | ||
2764 | case 'i': | |
7afe21cc | 2765 | if (XINT (x, i) != XINT (y, i)) |
dec7aaab | 2766 | return false; |
906c4e36 RK |
2767 | break; |
2768 | ||
2769 | case 'w': | |
2770 | if (XWINT (x, i) != XWINT (y, i)) | |
dec7aaab | 2771 | return false; |
278a83b2 | 2772 | break; |
906c4e36 | 2773 | |
91914e56 RS |
2774 | case 'p': |
2775 | if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y))) | |
dec7aaab | 2776 | return false; |
91914e56 RS |
2777 | break; |
2778 | ||
906c4e36 | 2779 | case '0': |
8f985ec4 | 2780 | case 't': |
906c4e36 RK |
2781 | break; |
2782 | ||
2783 | default: | |
341c100f | 2784 | gcc_unreachable (); |
7afe21cc | 2785 | } |
278a83b2 | 2786 | } |
906c4e36 | 2787 | |
dec7aaab | 2788 | return true; |
7afe21cc RK |
2789 | } |
2790 | \f | |
eef3c949 RS |
2791 | /* Subroutine of canon_reg. Pass *XLOC through canon_reg, and validate |
2792 | the result if necessary. INSN is as for canon_reg. */ | |
2793 | ||
2794 | static void | |
20468884 | 2795 | validate_canon_reg (rtx *xloc, rtx_insn *insn) |
eef3c949 | 2796 | { |
6fb5fa3c DB |
2797 | if (*xloc) |
2798 | { | |
32e9fa48 | 2799 | rtx new_rtx = canon_reg (*xloc, insn); |
eef3c949 | 2800 | |
6fb5fa3c DB |
2801 | /* If replacing pseudo with hard reg or vice versa, ensure the |
2802 | insn remains valid. Likewise if the insn has MATCH_DUPs. */ | |
32e9fa48 KG |
2803 | gcc_assert (insn && new_rtx); |
2804 | validate_change (insn, xloc, new_rtx, 1); | |
6fb5fa3c | 2805 | } |
eef3c949 RS |
2806 | } |
2807 | ||
7afe21cc RK |
2808 | /* Canonicalize an expression: |
2809 | replace each register reference inside it | |
2810 | with the "oldest" equivalent register. | |
2811 | ||
67e0a632 | 2812 | If INSN is nonzero validate_change is used to ensure that INSN remains valid |
da7d8304 | 2813 | after we make our substitution. The calls are made with IN_GROUP nonzero |
7722328e RK |
2814 | so apply_change_group must be called upon the outermost return from this |
2815 | function (unless INSN is zero). The result of apply_change_group can | |
2816 | generally be discarded since the changes we are making are optional. */ | |
7afe21cc RK |
2817 | |
2818 | static rtx | |
20468884 | 2819 | canon_reg (rtx x, rtx_insn *insn) |
7afe21cc | 2820 | { |
b3694847 SS |
2821 | int i; |
2822 | enum rtx_code code; | |
2823 | const char *fmt; | |
7afe21cc RK |
2824 | |
2825 | if (x == 0) | |
2826 | return x; | |
2827 | ||
2828 | code = GET_CODE (x); | |
2829 | switch (code) | |
2830 | { | |
2831 | case PC: | |
7afe21cc | 2832 | case CONST: |
d8116890 | 2833 | CASE_CONST_ANY: |
7afe21cc RK |
2834 | case SYMBOL_REF: |
2835 | case LABEL_REF: | |
2836 | case ADDR_VEC: | |
2837 | case ADDR_DIFF_VEC: | |
2838 | return x; | |
2839 | ||
2840 | case REG: | |
2841 | { | |
b3694847 SS |
2842 | int first; |
2843 | int q; | |
2844 | struct qty_table_elem *ent; | |
7afe21cc RK |
2845 | |
2846 | /* Never replace a hard reg, because hard regs can appear | |
2847 | in more than one machine mode, and we must preserve the mode | |
2848 | of each occurrence. Also, some hard regs appear in | |
2849 | MEMs that are shared and mustn't be altered. Don't try to | |
2850 | replace any reg that maps to a reg of class NO_REGS. */ | |
2851 | if (REGNO (x) < FIRST_PSEUDO_REGISTER | |
2852 | || ! REGNO_QTY_VALID_P (REGNO (x))) | |
2853 | return x; | |
2854 | ||
278a83b2 | 2855 | q = REG_QTY (REGNO (x)); |
1bb98cec DM |
2856 | ent = &qty_table[q]; |
2857 | first = ent->first_reg; | |
7afe21cc RK |
2858 | return (first >= FIRST_PSEUDO_REGISTER ? regno_reg_rtx[first] |
2859 | : REGNO_REG_CLASS (first) == NO_REGS ? x | |
1bb98cec | 2860 | : gen_rtx_REG (ent->mode, first)); |
7afe21cc | 2861 | } |
278a83b2 | 2862 | |
e9a25f70 JL |
2863 | default: |
2864 | break; | |
7afe21cc RK |
2865 | } |
2866 | ||
2867 | fmt = GET_RTX_FORMAT (code); | |
2868 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2869 | { | |
b3694847 | 2870 | int j; |
7afe21cc RK |
2871 | |
2872 | if (fmt[i] == 'e') | |
eef3c949 | 2873 | validate_canon_reg (&XEXP (x, i), insn); |
7afe21cc RK |
2874 | else if (fmt[i] == 'E') |
2875 | for (j = 0; j < XVECLEN (x, i); j++) | |
eef3c949 | 2876 | validate_canon_reg (&XVECEXP (x, i, j), insn); |
7afe21cc RK |
2877 | } |
2878 | ||
2879 | return x; | |
2880 | } | |
2881 | \f | |
bca05d20 RK |
2882 | /* Given an operation (CODE, *PARG1, *PARG2), where code is a comparison |
2883 | operation (EQ, NE, GT, etc.), follow it back through the hash table and | |
2884 | what values are being compared. | |
1a87eea2 | 2885 | |
bca05d20 | 2886 | *PARG1 and *PARG2 are updated to contain the rtx representing the values |
bd1cd0d0 SB |
2887 | actually being compared. For example, if *PARG1 was (reg:CC CC_REG) and |
2888 | *PARG2 was (const_int 0), *PARG1 and *PARG2 will be set to the objects that | |
2889 | were compared to produce (reg:CC CC_REG). | |
a432f20d | 2890 | |
bca05d20 RK |
2891 | The return value is the comparison operator and is either the code of |
2892 | A or the code corresponding to the inverse of the comparison. */ | |
7afe21cc | 2893 | |
0cedb36c | 2894 | static enum rtx_code |
7080f735 | 2895 | find_comparison_args (enum rtx_code code, rtx *parg1, rtx *parg2, |
ef4bddc2 | 2896 | machine_mode *pmode1, machine_mode *pmode2) |
7afe21cc | 2897 | { |
0cedb36c | 2898 | rtx arg1, arg2; |
6e2830c3 | 2899 | hash_set<rtx> *visited = NULL; |
27ec0502 AJ |
2900 | /* Set nonzero when we find something of interest. */ |
2901 | rtx x = NULL; | |
1a87eea2 | 2902 | |
0cedb36c | 2903 | arg1 = *parg1, arg2 = *parg2; |
7afe21cc | 2904 | |
0cedb36c | 2905 | /* If ARG2 is const0_rtx, see what ARG1 is equivalent to. */ |
7afe21cc | 2906 | |
0cedb36c | 2907 | while (arg2 == CONST0_RTX (GET_MODE (arg1))) |
a432f20d | 2908 | { |
0cedb36c JL |
2909 | int reverse_code = 0; |
2910 | struct table_elt *p = 0; | |
6076248a | 2911 | |
27ec0502 AJ |
2912 | /* Remember state from previous iteration. */ |
2913 | if (x) | |
2914 | { | |
2915 | if (!visited) | |
6e2830c3 TS |
2916 | visited = new hash_set<rtx>; |
2917 | visited->add (x); | |
27ec0502 AJ |
2918 | x = 0; |
2919 | } | |
2920 | ||
bd1cd0d0 | 2921 | /* If arg1 is a COMPARE, extract the comparison arguments from it. */ |
6076248a | 2922 | |
0cedb36c JL |
2923 | if (GET_CODE (arg1) == COMPARE && arg2 == const0_rtx) |
2924 | x = arg1; | |
6076248a | 2925 | |
0cedb36c JL |
2926 | /* If ARG1 is a comparison operator and CODE is testing for |
2927 | STORE_FLAG_VALUE, get the inner arguments. */ | |
a432f20d | 2928 | |
ec8e098d | 2929 | else if (COMPARISON_P (arg1)) |
7afe21cc | 2930 | { |
efdc7e19 RH |
2931 | #ifdef FLOAT_STORE_FLAG_VALUE |
2932 | REAL_VALUE_TYPE fsfv; | |
2933 | #endif | |
2934 | ||
0cedb36c JL |
2935 | if (code == NE |
2936 | || (GET_MODE_CLASS (GET_MODE (arg1)) == MODE_INT | |
2937 | && code == LT && STORE_FLAG_VALUE == -1) | |
2938 | #ifdef FLOAT_STORE_FLAG_VALUE | |
9b92bf04 | 2939 | || (SCALAR_FLOAT_MODE_P (GET_MODE (arg1)) |
efdc7e19 RH |
2940 | && (fsfv = FLOAT_STORE_FLAG_VALUE (GET_MODE (arg1)), |
2941 | REAL_VALUE_NEGATIVE (fsfv))) | |
7afe21cc | 2942 | #endif |
a432f20d | 2943 | ) |
0cedb36c JL |
2944 | x = arg1; |
2945 | else if (code == EQ | |
2946 | || (GET_MODE_CLASS (GET_MODE (arg1)) == MODE_INT | |
2947 | && code == GE && STORE_FLAG_VALUE == -1) | |
2948 | #ifdef FLOAT_STORE_FLAG_VALUE | |
9b92bf04 | 2949 | || (SCALAR_FLOAT_MODE_P (GET_MODE (arg1)) |
efdc7e19 RH |
2950 | && (fsfv = FLOAT_STORE_FLAG_VALUE (GET_MODE (arg1)), |
2951 | REAL_VALUE_NEGATIVE (fsfv))) | |
0cedb36c JL |
2952 | #endif |
2953 | ) | |
2954 | x = arg1, reverse_code = 1; | |
7afe21cc RK |
2955 | } |
2956 | ||
0cedb36c | 2957 | /* ??? We could also check for |
7afe21cc | 2958 | |
0cedb36c | 2959 | (ne (and (eq (...) (const_int 1))) (const_int 0)) |
7afe21cc | 2960 | |
0cedb36c | 2961 | and related forms, but let's wait until we see them occurring. */ |
7afe21cc | 2962 | |
0cedb36c JL |
2963 | if (x == 0) |
2964 | /* Look up ARG1 in the hash table and see if it has an equivalence | |
2965 | that lets us see what is being compared. */ | |
0516f6fe | 2966 | p = lookup (arg1, SAFE_HASH (arg1, GET_MODE (arg1)), GET_MODE (arg1)); |
278a83b2 | 2967 | if (p) |
8b03b984 R |
2968 | { |
2969 | p = p->first_same_value; | |
2970 | ||
2971 | /* If what we compare is already known to be constant, that is as | |
2972 | good as it gets. | |
2973 | We need to break the loop in this case, because otherwise we | |
2974 | can have an infinite loop when looking at a reg that is known | |
2975 | to be a constant which is the same as a comparison of a reg | |
2976 | against zero which appears later in the insn stream, which in | |
2977 | turn is constant and the same as the comparison of the first reg | |
2978 | against zero... */ | |
2979 | if (p->is_const) | |
2980 | break; | |
2981 | } | |
7afe21cc | 2982 | |
0cedb36c | 2983 | for (; p; p = p->next_same_value) |
7afe21cc | 2984 | { |
ef4bddc2 | 2985 | machine_mode inner_mode = GET_MODE (p->exp); |
efdc7e19 RH |
2986 | #ifdef FLOAT_STORE_FLAG_VALUE |
2987 | REAL_VALUE_TYPE fsfv; | |
2988 | #endif | |
7afe21cc | 2989 | |
0cedb36c | 2990 | /* If the entry isn't valid, skip it. */ |
0516f6fe | 2991 | if (! exp_equiv_p (p->exp, p->exp, 1, false)) |
0cedb36c | 2992 | continue; |
f76b9db2 | 2993 | |
27ec0502 | 2994 | /* If it's a comparison we've used before, skip it. */ |
6e2830c3 | 2995 | if (visited && visited->contains (p->exp)) |
8f1ad6b6 SL |
2996 | continue; |
2997 | ||
bca05d20 RK |
2998 | if (GET_CODE (p->exp) == COMPARE |
2999 | /* Another possibility is that this machine has a compare insn | |
3000 | that includes the comparison code. In that case, ARG1 would | |
3001 | be equivalent to a comparison operation that would set ARG1 to | |
3002 | either STORE_FLAG_VALUE or zero. If this is an NE operation, | |
3003 | ORIG_CODE is the actual comparison being done; if it is an EQ, | |
3004 | we must reverse ORIG_CODE. On machine with a negative value | |
3005 | for STORE_FLAG_VALUE, also look at LT and GE operations. */ | |
3006 | || ((code == NE | |
3007 | || (code == LT | |
2d0c270f BS |
3008 | && val_signbit_known_set_p (inner_mode, |
3009 | STORE_FLAG_VALUE)) | |
0cedb36c | 3010 | #ifdef FLOAT_STORE_FLAG_VALUE |
bca05d20 | 3011 | || (code == LT |
3d8bf70f | 3012 | && SCALAR_FLOAT_MODE_P (inner_mode) |
efdc7e19 RH |
3013 | && (fsfv = FLOAT_STORE_FLAG_VALUE (GET_MODE (arg1)), |
3014 | REAL_VALUE_NEGATIVE (fsfv))) | |
0cedb36c | 3015 | #endif |
bca05d20 | 3016 | ) |
ec8e098d | 3017 | && COMPARISON_P (p->exp))) |
7afe21cc | 3018 | { |
0cedb36c JL |
3019 | x = p->exp; |
3020 | break; | |
3021 | } | |
3022 | else if ((code == EQ | |
3023 | || (code == GE | |
2d0c270f BS |
3024 | && val_signbit_known_set_p (inner_mode, |
3025 | STORE_FLAG_VALUE)) | |
0cedb36c JL |
3026 | #ifdef FLOAT_STORE_FLAG_VALUE |
3027 | || (code == GE | |
3d8bf70f | 3028 | && SCALAR_FLOAT_MODE_P (inner_mode) |
efdc7e19 RH |
3029 | && (fsfv = FLOAT_STORE_FLAG_VALUE (GET_MODE (arg1)), |
3030 | REAL_VALUE_NEGATIVE (fsfv))) | |
0cedb36c JL |
3031 | #endif |
3032 | ) | |
ec8e098d | 3033 | && COMPARISON_P (p->exp)) |
0cedb36c JL |
3034 | { |
3035 | reverse_code = 1; | |
3036 | x = p->exp; | |
3037 | break; | |
7afe21cc RK |
3038 | } |
3039 | ||
4977bab6 ZW |
3040 | /* If this non-trapping address, e.g. fp + constant, the |
3041 | equivalent is a better operand since it may let us predict | |
3042 | the value of the comparison. */ | |
3043 | else if (!rtx_addr_can_trap_p (p->exp)) | |
0cedb36c JL |
3044 | { |
3045 | arg1 = p->exp; | |
3046 | continue; | |
3047 | } | |
7afe21cc | 3048 | } |
7afe21cc | 3049 | |
0cedb36c JL |
3050 | /* If we didn't find a useful equivalence for ARG1, we are done. |
3051 | Otherwise, set up for the next iteration. */ | |
3052 | if (x == 0) | |
3053 | break; | |
7afe21cc | 3054 | |
026c3cfd | 3055 | /* If we need to reverse the comparison, make sure that is |
78192b09 RH |
3056 | possible -- we can't necessarily infer the value of GE from LT |
3057 | with floating-point operands. */ | |
0cedb36c | 3058 | if (reverse_code) |
261efdef | 3059 | { |
c9b0a227 | 3060 | enum rtx_code reversed = reversed_comparison_code (x, NULL); |
261efdef JH |
3061 | if (reversed == UNKNOWN) |
3062 | break; | |
68252e27 KH |
3063 | else |
3064 | code = reversed; | |
261efdef | 3065 | } |
ec8e098d | 3066 | else if (COMPARISON_P (x)) |
261efdef JH |
3067 | code = GET_CODE (x); |
3068 | arg1 = XEXP (x, 0), arg2 = XEXP (x, 1); | |
7afe21cc RK |
3069 | } |
3070 | ||
0cedb36c JL |
3071 | /* Return our results. Return the modes from before fold_rtx |
3072 | because fold_rtx might produce const_int, and then it's too late. */ | |
3073 | *pmode1 = GET_MODE (arg1), *pmode2 = GET_MODE (arg2); | |
3074 | *parg1 = fold_rtx (arg1, 0), *parg2 = fold_rtx (arg2, 0); | |
3075 | ||
27ec0502 | 3076 | if (visited) |
6e2830c3 | 3077 | delete visited; |
0cedb36c | 3078 | return code; |
7afe21cc RK |
3079 | } |
3080 | \f | |
a52b023a PB |
3081 | /* If X is a nontrivial arithmetic operation on an argument for which |
3082 | a constant value can be determined, return the result of operating | |
3083 | on that value, as a constant. Otherwise, return X, possibly with | |
3084 | one or more operands changed to a forward-propagated constant. | |
25910ca4 | 3085 | |
a52b023a PB |
3086 | If X is a register whose contents are known, we do NOT return |
3087 | those contents here; equiv_constant is called to perform that task. | |
3088 | For SUBREGs and MEMs, we do that both here and in equiv_constant. | |
7afe21cc RK |
3089 | |
3090 | INSN is the insn that we may be modifying. If it is 0, make a copy | |
3091 | of X before modifying it. */ | |
3092 | ||
3093 | static rtx | |
20468884 | 3094 | fold_rtx (rtx x, rtx_insn *insn) |
7afe21cc | 3095 | { |
b3694847 | 3096 | enum rtx_code code; |
ef4bddc2 | 3097 | machine_mode mode; |
b3694847 SS |
3098 | const char *fmt; |
3099 | int i; | |
32e9fa48 | 3100 | rtx new_rtx = 0; |
dec7aaab | 3101 | bool changed = false; |
5284e559 | 3102 | poly_int64 xval; |
7afe21cc | 3103 | |
a52b023a | 3104 | /* Operands of X. */ |
e54bd4ab JJ |
3105 | /* Workaround -Wmaybe-uninitialized false positive during |
3106 | profiledbootstrap by initializing them. */ | |
3107 | rtx folded_arg0 = NULL_RTX; | |
3108 | rtx folded_arg1 = NULL_RTX; | |
7afe21cc RK |
3109 | |
3110 | /* Constant equivalents of first three operands of X; | |
3111 | 0 when no such equivalent is known. */ | |
3112 | rtx const_arg0; | |
3113 | rtx const_arg1; | |
3114 | rtx const_arg2; | |
3115 | ||
3116 | /* The mode of the first operand of X. We need this for sign and zero | |
3117 | extends. */ | |
ef4bddc2 | 3118 | machine_mode mode_arg0; |
7afe21cc RK |
3119 | |
3120 | if (x == 0) | |
3121 | return x; | |
3122 | ||
a52b023a | 3123 | /* Try to perform some initial simplifications on X. */ |
7afe21cc RK |
3124 | code = GET_CODE (x); |
3125 | switch (code) | |
3126 | { | |
a52b023a PB |
3127 | case MEM: |
3128 | case SUBREG: | |
5141ed42 JL |
3129 | /* The first operand of a SIGN/ZERO_EXTRACT has a different meaning |
3130 | than it would in other contexts. Basically its mode does not | |
3131 | signify the size of the object read. That information is carried | |
3132 | by size operand. If we happen to have a MEM of the appropriate | |
3133 | mode in our tables with a constant value we could simplify the | |
3134 | extraction incorrectly if we allowed substitution of that value | |
3135 | for the MEM. */ | |
3136 | case ZERO_EXTRACT: | |
3137 | case SIGN_EXTRACT: | |
32e9fa48 KG |
3138 | if ((new_rtx = equiv_constant (x)) != NULL_RTX) |
3139 | return new_rtx; | |
a52b023a PB |
3140 | return x; |
3141 | ||
7afe21cc | 3142 | case CONST: |
d8116890 | 3143 | CASE_CONST_ANY: |
7afe21cc RK |
3144 | case SYMBOL_REF: |
3145 | case LABEL_REF: | |
3146 | case REG: | |
01aa1d43 | 3147 | case PC: |
7afe21cc RK |
3148 | /* No use simplifying an EXPR_LIST |
3149 | since they are used only for lists of args | |
3150 | in a function call's REG_EQUAL note. */ | |
3151 | case EXPR_LIST: | |
3152 | return x; | |
3153 | ||
9255709c | 3154 | case ASM_OPERANDS: |
6c667859 AB |
3155 | if (insn) |
3156 | { | |
3157 | for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--) | |
3158 | validate_change (insn, &ASM_OPERANDS_INPUT (x, i), | |
3159 | fold_rtx (ASM_OPERANDS_INPUT (x, i), insn), 0); | |
3160 | } | |
a52b023a PB |
3161 | return x; |
3162 | ||
a52b023a | 3163 | case CALL: |
1e8552c2 | 3164 | if (NO_FUNCTION_CSE && CONSTANT_P (XEXP (XEXP (x, 0), 0))) |
a52b023a | 3165 | return x; |
9255709c | 3166 | break; |
8695bf78 JW |
3167 | case VEC_SELECT: |
3168 | { | |
3169 | rtx trueop0 = XEXP (x, 0); | |
3170 | mode = GET_MODE (trueop0); | |
3171 | rtx trueop1 = XEXP (x, 1); | |
3172 | /* If we select a low-part subreg, return that. */ | |
3173 | if (vec_series_lowpart_p (GET_MODE (x), mode, trueop1)) | |
3174 | { | |
3175 | rtx new_rtx = lowpart_subreg (GET_MODE (x), trueop0, mode); | |
3176 | if (new_rtx != NULL_RTX) | |
3177 | return new_rtx; | |
3178 | } | |
3179 | } | |
278a83b2 | 3180 | |
a52b023a | 3181 | /* Anything else goes through the loop below. */ |
e9a25f70 JL |
3182 | default: |
3183 | break; | |
7afe21cc RK |
3184 | } |
3185 | ||
a52b023a | 3186 | mode = GET_MODE (x); |
7afe21cc RK |
3187 | const_arg0 = 0; |
3188 | const_arg1 = 0; | |
3189 | const_arg2 = 0; | |
3190 | mode_arg0 = VOIDmode; | |
3191 | ||
3192 | /* Try folding our operands. | |
3193 | Then see which ones have constant values known. */ | |
3194 | ||
3195 | fmt = GET_RTX_FORMAT (code); | |
3196 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3197 | if (fmt[i] == 'e') | |
3198 | { | |
a52b023a | 3199 | rtx folded_arg = XEXP (x, i), const_arg; |
ef4bddc2 | 3200 | machine_mode mode_arg = GET_MODE (folded_arg); |
7e7e28c7 AO |
3201 | |
3202 | switch (GET_CODE (folded_arg)) | |
3203 | { | |
3204 | case MEM: | |
3205 | case REG: | |
3206 | case SUBREG: | |
3207 | const_arg = equiv_constant (folded_arg); | |
3208 | break; | |
3209 | ||
3210 | case CONST: | |
d8116890 | 3211 | CASE_CONST_ANY: |
7e7e28c7 AO |
3212 | case SYMBOL_REF: |
3213 | case LABEL_REF: | |
7e7e28c7 AO |
3214 | const_arg = folded_arg; |
3215 | break; | |
3216 | ||
7e7e28c7 AO |
3217 | default: |
3218 | folded_arg = fold_rtx (folded_arg, insn); | |
3219 | const_arg = equiv_constant (folded_arg); | |
3220 | break; | |
3221 | } | |
7afe21cc RK |
3222 | |
3223 | /* For the first three operands, see if the operand | |
3224 | is constant or equivalent to a constant. */ | |
3225 | switch (i) | |
3226 | { | |
3227 | case 0: | |
3228 | folded_arg0 = folded_arg; | |
3229 | const_arg0 = const_arg; | |
3230 | mode_arg0 = mode_arg; | |
3231 | break; | |
3232 | case 1: | |
3233 | folded_arg1 = folded_arg; | |
3234 | const_arg1 = const_arg; | |
3235 | break; | |
3236 | case 2: | |
3237 | const_arg2 = const_arg; | |
3238 | break; | |
3239 | } | |
3240 | ||
a52b023a PB |
3241 | /* Pick the least expensive of the argument and an equivalent constant |
3242 | argument. */ | |
3243 | if (const_arg != 0 | |
3244 | && const_arg != folded_arg | |
e548c9df AM |
3245 | && (COST_IN (const_arg, mode_arg, code, i) |
3246 | <= COST_IN (folded_arg, mode_arg, code, i)) | |
f2fa288f | 3247 | |
8cce3d04 RS |
3248 | /* It's not safe to substitute the operand of a conversion |
3249 | operator with a constant, as the conversion's identity | |
f652d14b | 3250 | depends upon the mode of its operand. This optimization |
8cce3d04 | 3251 | is handled by the call to simplify_unary_operation. */ |
a52b023a PB |
3252 | && (GET_RTX_CLASS (code) != RTX_UNARY |
3253 | || GET_MODE (const_arg) == mode_arg0 | |
3254 | || (code != ZERO_EXTEND | |
3255 | && code != SIGN_EXTEND | |
3256 | && code != TRUNCATE | |
3257 | && code != FLOAT_TRUNCATE | |
3258 | && code != FLOAT_EXTEND | |
3259 | && code != FLOAT | |
3260 | && code != FIX | |
3261 | && code != UNSIGNED_FLOAT | |
3262 | && code != UNSIGNED_FIX))) | |
3263 | folded_arg = const_arg; | |
3264 | ||
3265 | if (folded_arg == XEXP (x, i)) | |
3266 | continue; | |
7afe21cc | 3267 | |
a52b023a PB |
3268 | if (insn == NULL_RTX && !changed) |
3269 | x = copy_rtx (x); | |
dec7aaab | 3270 | changed = true; |
b8b89e7c | 3271 | validate_unshare_change (insn, &XEXP (x, i), folded_arg, 1); |
2d8b0f3a | 3272 | } |
7afe21cc | 3273 | |
a52b023a | 3274 | if (changed) |
7afe21cc | 3275 | { |
a52b023a PB |
3276 | /* Canonicalize X if necessary, and keep const_argN and folded_argN |
3277 | consistent with the order in X. */ | |
3278 | if (canonicalize_change_group (insn, x)) | |
7afe21cc | 3279 | { |
4e1952ab KT |
3280 | std::swap (const_arg0, const_arg1); |
3281 | std::swap (folded_arg0, folded_arg1); | |
7afe21cc | 3282 | } |
a52b023a PB |
3283 | |
3284 | apply_change_group (); | |
7afe21cc RK |
3285 | } |
3286 | ||
3287 | /* If X is an arithmetic operation, see if we can simplify it. */ | |
3288 | ||
3289 | switch (GET_RTX_CLASS (code)) | |
3290 | { | |
ec8e098d | 3291 | case RTX_UNARY: |
67a37737 | 3292 | { |
67a37737 RK |
3293 | /* We can't simplify extension ops unless we know the |
3294 | original mode. */ | |
3295 | if ((code == ZERO_EXTEND || code == SIGN_EXTEND) | |
3296 | && mode_arg0 == VOIDmode) | |
3297 | break; | |
3298 | ||
32e9fa48 | 3299 | new_rtx = simplify_unary_operation (code, mode, |
696d76a5 MS |
3300 | const_arg0 ? const_arg0 : folded_arg0, |
3301 | mode_arg0); | |
67a37737 | 3302 | } |
7afe21cc | 3303 | break; |
278a83b2 | 3304 | |
ec8e098d PB |
3305 | case RTX_COMPARE: |
3306 | case RTX_COMM_COMPARE: | |
7afe21cc RK |
3307 | /* See what items are actually being compared and set FOLDED_ARG[01] |
3308 | to those values and CODE to the actual comparison code. If any are | |
3309 | constant, set CONST_ARG0 and CONST_ARG1 appropriately. We needn't | |
3310 | do anything if both operands are already known to be constant. */ | |
3311 | ||
21e5076a UB |
3312 | /* ??? Vector mode comparisons are not supported yet. */ |
3313 | if (VECTOR_MODE_P (mode)) | |
3314 | break; | |
3315 | ||
7afe21cc RK |
3316 | if (const_arg0 == 0 || const_arg1 == 0) |
3317 | { | |
3318 | struct table_elt *p0, *p1; | |
9e6a14a4 | 3319 | rtx true_rtx, false_rtx; |
ef4bddc2 | 3320 | machine_mode mode_arg1; |
c610adec | 3321 | |
9b92bf04 | 3322 | if (SCALAR_FLOAT_MODE_P (mode)) |
c610adec | 3323 | { |
9e6a14a4 | 3324 | #ifdef FLOAT_STORE_FLAG_VALUE |
555affd7 | 3325 | true_rtx = (const_double_from_real_value |
68252e27 | 3326 | (FLOAT_STORE_FLAG_VALUE (mode), mode)); |
9e6a14a4 L |
3327 | #else |
3328 | true_rtx = NULL_RTX; | |
3329 | #endif | |
d6edb99e | 3330 | false_rtx = CONST0_RTX (mode); |
c610adec | 3331 | } |
9e6a14a4 L |
3332 | else |
3333 | { | |
3334 | true_rtx = const_true_rtx; | |
3335 | false_rtx = const0_rtx; | |
3336 | } | |
7afe21cc | 3337 | |
13c9910f RS |
3338 | code = find_comparison_args (code, &folded_arg0, &folded_arg1, |
3339 | &mode_arg0, &mode_arg1); | |
7afe21cc | 3340 | |
13c9910f RS |
3341 | /* If the mode is VOIDmode or a MODE_CC mode, we don't know |
3342 | what kinds of things are being compared, so we can't do | |
3343 | anything with this comparison. */ | |
7afe21cc RK |
3344 | |
3345 | if (mode_arg0 == VOIDmode || GET_MODE_CLASS (mode_arg0) == MODE_CC) | |
3346 | break; | |
3347 | ||
75335440 KH |
3348 | const_arg0 = equiv_constant (folded_arg0); |
3349 | const_arg1 = equiv_constant (folded_arg1); | |
3350 | ||
0f41302f MS |
3351 | /* If we do not now have two constants being compared, see |
3352 | if we can nevertheless deduce some things about the | |
3353 | comparison. */ | |
7afe21cc RK |
3354 | if (const_arg0 == 0 || const_arg1 == 0) |
3355 | { | |
08678f51 HPN |
3356 | if (const_arg1 != NULL) |
3357 | { | |
3358 | rtx cheapest_simplification; | |
3359 | int cheapest_cost; | |
3360 | rtx simp_result; | |
3361 | struct table_elt *p; | |
3362 | ||
3363 | /* See if we can find an equivalent of folded_arg0 | |
3364 | that gets us a cheaper expression, possibly a | |
3365 | constant through simplifications. */ | |
3366 | p = lookup (folded_arg0, SAFE_HASH (folded_arg0, mode_arg0), | |
3367 | mode_arg0); | |
b8698a0f | 3368 | |
08678f51 HPN |
3369 | if (p != NULL) |
3370 | { | |
3371 | cheapest_simplification = x; | |
e548c9df | 3372 | cheapest_cost = COST (x, mode); |
08678f51 HPN |
3373 | |
3374 | for (p = p->first_same_value; p != NULL; p = p->next_same_value) | |
3375 | { | |
3376 | int cost; | |
3377 | ||
3378 | /* If the entry isn't valid, skip it. */ | |
3379 | if (! exp_equiv_p (p->exp, p->exp, 1, false)) | |
3380 | continue; | |
3381 | ||
3382 | /* Try to simplify using this equivalence. */ | |
3383 | simp_result | |
3384 | = simplify_relational_operation (code, mode, | |
3385 | mode_arg0, | |
3386 | p->exp, | |
3387 | const_arg1); | |
3388 | ||
3389 | if (simp_result == NULL) | |
3390 | continue; | |
3391 | ||
e548c9df | 3392 | cost = COST (simp_result, mode); |
08678f51 HPN |
3393 | if (cost < cheapest_cost) |
3394 | { | |
3395 | cheapest_cost = cost; | |
3396 | cheapest_simplification = simp_result; | |
3397 | } | |
3398 | } | |
3399 | ||
3400 | /* If we have a cheaper expression now, use that | |
3401 | and try folding it further, from the top. */ | |
3402 | if (cheapest_simplification != x) | |
7903b3e5 JH |
3403 | return fold_rtx (copy_rtx (cheapest_simplification), |
3404 | insn); | |
08678f51 HPN |
3405 | } |
3406 | } | |
3407 | ||
fd13313f JH |
3408 | /* See if the two operands are the same. */ |
3409 | ||
39641489 PB |
3410 | if ((REG_P (folded_arg0) |
3411 | && REG_P (folded_arg1) | |
3412 | && (REG_QTY (REGNO (folded_arg0)) | |
3413 | == REG_QTY (REGNO (folded_arg1)))) | |
fd13313f | 3414 | || ((p0 = lookup (folded_arg0, |
0516f6fe SB |
3415 | SAFE_HASH (folded_arg0, mode_arg0), |
3416 | mode_arg0)) | |
fd13313f | 3417 | && (p1 = lookup (folded_arg1, |
0516f6fe SB |
3418 | SAFE_HASH (folded_arg1, mode_arg0), |
3419 | mode_arg0)) | |
fd13313f | 3420 | && p0->first_same_value == p1->first_same_value)) |
39641489 | 3421 | folded_arg1 = folded_arg0; |
7afe21cc RK |
3422 | |
3423 | /* If FOLDED_ARG0 is a register, see if the comparison we are | |
3424 | doing now is either the same as we did before or the reverse | |
3425 | (we only check the reverse if not floating-point). */ | |
f8cfc6aa | 3426 | else if (REG_P (folded_arg0)) |
7afe21cc | 3427 | { |
30f72379 | 3428 | int qty = REG_QTY (REGNO (folded_arg0)); |
7afe21cc | 3429 | |
1bb98cec DM |
3430 | if (REGNO_QTY_VALID_P (REGNO (folded_arg0))) |
3431 | { | |
3432 | struct qty_table_elem *ent = &qty_table[qty]; | |
3433 | ||
3434 | if ((comparison_dominates_p (ent->comparison_code, code) | |
1eb8759b RH |
3435 | || (! FLOAT_MODE_P (mode_arg0) |
3436 | && comparison_dominates_p (ent->comparison_code, | |
3437 | reverse_condition (code)))) | |
1bb98cec DM |
3438 | && (rtx_equal_p (ent->comparison_const, folded_arg1) |
3439 | || (const_arg1 | |
3440 | && rtx_equal_p (ent->comparison_const, | |
3441 | const_arg1)) | |
f8cfc6aa | 3442 | || (REG_P (folded_arg1) |
1bb98cec | 3443 | && (REG_QTY (REGNO (folded_arg1)) == ent->comparison_qty)))) |
9e6a14a4 L |
3444 | { |
3445 | if (comparison_dominates_p (ent->comparison_code, code)) | |
3446 | { | |
3447 | if (true_rtx) | |
3448 | return true_rtx; | |
3449 | else | |
3450 | break; | |
3451 | } | |
3452 | else | |
3453 | return false_rtx; | |
3454 | } | |
1bb98cec | 3455 | } |
7afe21cc RK |
3456 | } |
3457 | } | |
3458 | } | |
3459 | ||
3460 | /* If we are comparing against zero, see if the first operand is | |
3461 | equivalent to an IOR with a constant. If so, we may be able to | |
3462 | determine the result of this comparison. */ | |
39641489 | 3463 | if (const_arg1 == const0_rtx && !const_arg0) |
7afe21cc RK |
3464 | { |
3465 | rtx y = lookup_as_function (folded_arg0, IOR); | |
3466 | rtx inner_const; | |
3467 | ||
3468 | if (y != 0 | |
3469 | && (inner_const = equiv_constant (XEXP (y, 1))) != 0 | |
481683e1 | 3470 | && CONST_INT_P (inner_const) |
7afe21cc | 3471 | && INTVAL (inner_const) != 0) |
39641489 | 3472 | folded_arg0 = gen_rtx_IOR (mode_arg0, XEXP (y, 0), inner_const); |
7afe21cc RK |
3473 | } |
3474 | ||
c6fb08ad | 3475 | { |
bca3cc97 JJ |
3476 | rtx op0 = const_arg0 ? const_arg0 : copy_rtx (folded_arg0); |
3477 | rtx op1 = const_arg1 ? const_arg1 : copy_rtx (folded_arg1); | |
3478 | new_rtx = simplify_relational_operation (code, mode, mode_arg0, | |
3479 | op0, op1); | |
c6fb08ad | 3480 | } |
7afe21cc RK |
3481 | break; |
3482 | ||
ec8e098d PB |
3483 | case RTX_BIN_ARITH: |
3484 | case RTX_COMM_ARITH: | |
7afe21cc RK |
3485 | switch (code) |
3486 | { | |
3487 | case PLUS: | |
3488 | /* If the second operand is a LABEL_REF, see if the first is a MINUS | |
3489 | with that LABEL_REF as its second operand. If so, the result is | |
3490 | the first operand of that MINUS. This handles switches with an | |
3491 | ADDR_DIFF_VEC table. */ | |
3492 | if (const_arg1 && GET_CODE (const_arg1) == LABEL_REF) | |
3493 | { | |
e650cbda RK |
3494 | rtx y |
3495 | = GET_CODE (folded_arg0) == MINUS ? folded_arg0 | |
ddc356e8 | 3496 | : lookup_as_function (folded_arg0, MINUS); |
7afe21cc RK |
3497 | |
3498 | if (y != 0 && GET_CODE (XEXP (y, 1)) == LABEL_REF | |
04a121a7 | 3499 | && label_ref_label (XEXP (y, 1)) == label_ref_label (const_arg1)) |
7afe21cc | 3500 | return XEXP (y, 0); |
67a37737 RK |
3501 | |
3502 | /* Now try for a CONST of a MINUS like the above. */ | |
e650cbda RK |
3503 | if ((y = (GET_CODE (folded_arg0) == CONST ? folded_arg0 |
3504 | : lookup_as_function (folded_arg0, CONST))) != 0 | |
67a37737 RK |
3505 | && GET_CODE (XEXP (y, 0)) == MINUS |
3506 | && GET_CODE (XEXP (XEXP (y, 0), 1)) == LABEL_REF | |
04a121a7 | 3507 | && label_ref_label (XEXP (XEXP (y, 0), 1)) == label_ref_label (const_arg1)) |
67a37737 | 3508 | return XEXP (XEXP (y, 0), 0); |
7afe21cc | 3509 | } |
c2cc0778 | 3510 | |
e650cbda RK |
3511 | /* Likewise if the operands are in the other order. */ |
3512 | if (const_arg0 && GET_CODE (const_arg0) == LABEL_REF) | |
3513 | { | |
3514 | rtx y | |
3515 | = GET_CODE (folded_arg1) == MINUS ? folded_arg1 | |
ddc356e8 | 3516 | : lookup_as_function (folded_arg1, MINUS); |
e650cbda RK |
3517 | |
3518 | if (y != 0 && GET_CODE (XEXP (y, 1)) == LABEL_REF | |
04a121a7 | 3519 | && label_ref_label (XEXP (y, 1)) == label_ref_label (const_arg0)) |
e650cbda RK |
3520 | return XEXP (y, 0); |
3521 | ||
3522 | /* Now try for a CONST of a MINUS like the above. */ | |
3523 | if ((y = (GET_CODE (folded_arg1) == CONST ? folded_arg1 | |
3524 | : lookup_as_function (folded_arg1, CONST))) != 0 | |
3525 | && GET_CODE (XEXP (y, 0)) == MINUS | |
3526 | && GET_CODE (XEXP (XEXP (y, 0), 1)) == LABEL_REF | |
04a121a7 | 3527 | && label_ref_label (XEXP (XEXP (y, 0), 1)) == label_ref_label (const_arg0)) |
e650cbda RK |
3528 | return XEXP (XEXP (y, 0), 0); |
3529 | } | |
3530 | ||
c2cc0778 RK |
3531 | /* If second operand is a register equivalent to a negative |
3532 | CONST_INT, see if we can find a register equivalent to the | |
3533 | positive constant. Make a MINUS if so. Don't do this for | |
5d595063 | 3534 | a non-negative constant since we might then alternate between |
a1f300c0 | 3535 | choosing positive and negative constants. Having the positive |
5d595063 RK |
3536 | constant previously-used is the more common case. Be sure |
3537 | the resulting constant is non-negative; if const_arg1 were | |
3538 | the smallest negative number this would overflow: depending | |
3539 | on the mode, this would either just be the same value (and | |
3540 | hence not save anything) or be incorrect. */ | |
481683e1 | 3541 | if (const_arg1 != 0 && CONST_INT_P (const_arg1) |
5d595063 | 3542 | && INTVAL (const_arg1) < 0 |
4741f6ad JL |
3543 | /* This used to test |
3544 | ||
ddc356e8 | 3545 | -INTVAL (const_arg1) >= 0 |
4741f6ad JL |
3546 | |
3547 | But The Sun V5.0 compilers mis-compiled that test. So | |
3548 | instead we test for the problematic value in a more direct | |
3549 | manner and hope the Sun compilers get it correct. */ | |
5c45a8ac | 3550 | && INTVAL (const_arg1) != |
fecfbfa4 | 3551 | (HOST_WIDE_INT_1 << (HOST_BITS_PER_WIDE_INT - 1)) |
f8cfc6aa | 3552 | && REG_P (folded_arg1)) |
c2cc0778 | 3553 | { |
ddc356e8 | 3554 | rtx new_const = GEN_INT (-INTVAL (const_arg1)); |
c2cc0778 | 3555 | struct table_elt *p |
0516f6fe | 3556 | = lookup (new_const, SAFE_HASH (new_const, mode), mode); |
c2cc0778 RK |
3557 | |
3558 | if (p) | |
3559 | for (p = p->first_same_value; p; p = p->next_same_value) | |
f8cfc6aa | 3560 | if (REG_P (p->exp)) |
0cedb36c | 3561 | return simplify_gen_binary (MINUS, mode, folded_arg0, |
20468884 | 3562 | canon_reg (p->exp, NULL)); |
c2cc0778 | 3563 | } |
13c9910f RS |
3564 | goto from_plus; |
3565 | ||
3566 | case MINUS: | |
3567 | /* If we have (MINUS Y C), see if Y is known to be (PLUS Z C2). | |
3568 | If so, produce (PLUS Z C2-C). */ | |
5284e559 | 3569 | if (const_arg1 != 0 && poly_int_rtx_p (const_arg1, &xval)) |
13c9910f RS |
3570 | { |
3571 | rtx y = lookup_as_function (XEXP (x, 0), PLUS); | |
5284e559 RS |
3572 | if (y && poly_int_rtx_p (XEXP (y, 1))) |
3573 | return fold_rtx (plus_constant (mode, copy_rtx (y), -xval), | |
20468884 | 3574 | NULL); |
13c9910f | 3575 | } |
7afe21cc | 3576 | |
ddc356e8 | 3577 | /* Fall through. */ |
7afe21cc | 3578 | |
13c9910f | 3579 | from_plus: |
7afe21cc RK |
3580 | case SMIN: case SMAX: case UMIN: case UMAX: |
3581 | case IOR: case AND: case XOR: | |
f930bfd0 | 3582 | case MULT: |
7afe21cc RK |
3583 | case ASHIFT: case LSHIFTRT: case ASHIFTRT: |
3584 | /* If we have (<op> <reg> <const_int>) for an associative OP and REG | |
3585 | is known to be of similar form, we may be able to replace the | |
3586 | operation with a combined operation. This may eliminate the | |
3587 | intermediate operation if every use is simplified in this way. | |
e53b6e56 | 3588 | Note that the similar optimization done by combine.cc only works |
7afe21cc RK |
3589 | if the intermediate operation's result has only one reference. */ |
3590 | ||
f8cfc6aa | 3591 | if (REG_P (folded_arg0) |
481683e1 | 3592 | && const_arg1 && CONST_INT_P (const_arg1)) |
7afe21cc RK |
3593 | { |
3594 | int is_shift | |
3595 | = (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT); | |
5bb51e1d | 3596 | rtx y, inner_const, new_const; |
39b2ac74 | 3597 | rtx canon_const_arg1 = const_arg1; |
7afe21cc | 3598 | enum rtx_code associate_code; |
7afe21cc | 3599 | |
824a4527 | 3600 | if (is_shift |
bb06a2d8 | 3601 | && (INTVAL (const_arg1) >= GET_MODE_UNIT_PRECISION (mode) |
824a4527 JDA |
3602 | || INTVAL (const_arg1) < 0)) |
3603 | { | |
3604 | if (SHIFT_COUNT_TRUNCATED) | |
abd3c800 RS |
3605 | canon_const_arg1 = gen_int_shift_amount |
3606 | (mode, (INTVAL (const_arg1) | |
3607 | & (GET_MODE_UNIT_BITSIZE (mode) - 1))); | |
824a4527 JDA |
3608 | else |
3609 | break; | |
3610 | } | |
3611 | ||
5bb51e1d | 3612 | y = lookup_as_function (folded_arg0, code); |
824a4527 JDA |
3613 | if (y == 0) |
3614 | break; | |
824a4527 JDA |
3615 | |
3616 | /* If we have compiled a statement like | |
3617 | "if (x == (x & mask1))", and now are looking at | |
3618 | "x & mask2", we will have a case where the first operand | |
3619 | of Y is the same as our first operand. Unless we detect | |
3620 | this case, an infinite loop will result. */ | |
3621 | if (XEXP (y, 0) == folded_arg0) | |
7afe21cc RK |
3622 | break; |
3623 | ||
5bb51e1d | 3624 | inner_const = equiv_constant (fold_rtx (XEXP (y, 1), 0)); |
481683e1 | 3625 | if (!inner_const || !CONST_INT_P (inner_const)) |
5bb51e1d EB |
3626 | break; |
3627 | ||
7afe21cc RK |
3628 | /* Don't associate these operations if they are a PLUS with the |
3629 | same constant and it is a power of two. These might be doable | |
3630 | with a pre- or post-increment. Similarly for two subtracts of | |
3631 | identical powers of two with post decrement. */ | |
3632 | ||
213d5fbc | 3633 | if (code == PLUS && const_arg1 == inner_const |
940da324 | 3634 | && ((HAVE_PRE_INCREMENT |
146ec50f | 3635 | && pow2p_hwi (INTVAL (const_arg1))) |
940da324 | 3636 | || (HAVE_POST_INCREMENT |
146ec50f | 3637 | && pow2p_hwi (INTVAL (const_arg1))) |
940da324 | 3638 | || (HAVE_PRE_DECREMENT |
146ec50f | 3639 | && pow2p_hwi (- INTVAL (const_arg1))) |
940da324 | 3640 | || (HAVE_POST_DECREMENT |
146ec50f | 3641 | && pow2p_hwi (- INTVAL (const_arg1))))) |
7afe21cc RK |
3642 | break; |
3643 | ||
88057dc8 UB |
3644 | /* ??? Vector mode shifts by scalar |
3645 | shift operand are not supported yet. */ | |
3646 | if (is_shift && VECTOR_MODE_P (mode)) | |
3647 | break; | |
3648 | ||
824a4527 | 3649 | if (is_shift |
bb06a2d8 | 3650 | && (INTVAL (inner_const) >= GET_MODE_UNIT_PRECISION (mode) |
824a4527 JDA |
3651 | || INTVAL (inner_const) < 0)) |
3652 | { | |
3653 | if (SHIFT_COUNT_TRUNCATED) | |
abd3c800 RS |
3654 | inner_const = gen_int_shift_amount |
3655 | (mode, (INTVAL (inner_const) | |
3656 | & (GET_MODE_UNIT_BITSIZE (mode) - 1))); | |
824a4527 JDA |
3657 | else |
3658 | break; | |
3659 | } | |
3660 | ||
7afe21cc | 3661 | /* Compute the code used to compose the constants. For example, |
f930bfd0 | 3662 | A-C1-C2 is A-(C1 + C2), so if CODE == MINUS, we want PLUS. */ |
7afe21cc | 3663 | |
f930bfd0 | 3664 | associate_code = (is_shift || code == MINUS ? PLUS : code); |
7afe21cc RK |
3665 | |
3666 | new_const = simplify_binary_operation (associate_code, mode, | |
39b2ac74 JJ |
3667 | canon_const_arg1, |
3668 | inner_const); | |
7afe21cc RK |
3669 | |
3670 | if (new_const == 0) | |
3671 | break; | |
3672 | ||
3673 | /* If we are associating shift operations, don't let this | |
4908e508 RS |
3674 | produce a shift of the size of the object or larger. |
3675 | This could occur when we follow a sign-extend by a right | |
3676 | shift on a machine that does a sign-extend as a pair | |
3677 | of shifts. */ | |
7afe21cc | 3678 | |
824a4527 | 3679 | if (is_shift |
481683e1 | 3680 | && CONST_INT_P (new_const) |
bb06a2d8 | 3681 | && INTVAL (new_const) >= GET_MODE_UNIT_PRECISION (mode)) |
4908e508 RS |
3682 | { |
3683 | /* As an exception, we can turn an ASHIFTRT of this | |
3684 | form into a shift of the number of bits - 1. */ | |
3685 | if (code == ASHIFTRT) | |
abd3c800 RS |
3686 | new_const = gen_int_shift_amount |
3687 | (mode, GET_MODE_UNIT_BITSIZE (mode) - 1); | |
824a4527 JDA |
3688 | else if (!side_effects_p (XEXP (y, 0))) |
3689 | return CONST0_RTX (mode); | |
4908e508 RS |
3690 | else |
3691 | break; | |
3692 | } | |
7afe21cc RK |
3693 | |
3694 | y = copy_rtx (XEXP (y, 0)); | |
3695 | ||
3696 | /* If Y contains our first operand (the most common way this | |
3697 | can happen is if Y is a MEM), we would do into an infinite | |
3698 | loop if we tried to fold it. So don't in that case. */ | |
3699 | ||
3700 | if (! reg_mentioned_p (folded_arg0, y)) | |
3701 | y = fold_rtx (y, insn); | |
3702 | ||
0cedb36c | 3703 | return simplify_gen_binary (code, mode, y, new_const); |
7afe21cc | 3704 | } |
e9a25f70 JL |
3705 | break; |
3706 | ||
f930bfd0 JW |
3707 | case DIV: case UDIV: |
3708 | /* ??? The associative optimization performed immediately above is | |
3709 | also possible for DIV and UDIV using associate_code of MULT. | |
3710 | However, we would need extra code to verify that the | |
3711 | multiplication does not overflow, that is, there is no overflow | |
3712 | in the calculation of new_const. */ | |
3713 | break; | |
3714 | ||
e9a25f70 JL |
3715 | default: |
3716 | break; | |
7afe21cc RK |
3717 | } |
3718 | ||
32e9fa48 | 3719 | new_rtx = simplify_binary_operation (code, mode, |
7afe21cc RK |
3720 | const_arg0 ? const_arg0 : folded_arg0, |
3721 | const_arg1 ? const_arg1 : folded_arg1); | |
3722 | break; | |
3723 | ||
ec8e098d | 3724 | case RTX_OBJ: |
7afe21cc RK |
3725 | /* (lo_sum (high X) X) is simply X. */ |
3726 | if (code == LO_SUM && const_arg0 != 0 | |
3727 | && GET_CODE (const_arg0) == HIGH | |
3728 | && rtx_equal_p (XEXP (const_arg0, 0), const_arg1)) | |
3729 | return const_arg1; | |
3730 | break; | |
3731 | ||
ec8e098d PB |
3732 | case RTX_TERNARY: |
3733 | case RTX_BITFIELD_OPS: | |
32e9fa48 | 3734 | new_rtx = simplify_ternary_operation (code, mode, mode_arg0, |
7afe21cc RK |
3735 | const_arg0 ? const_arg0 : folded_arg0, |
3736 | const_arg1 ? const_arg1 : folded_arg1, | |
3737 | const_arg2 ? const_arg2 : XEXP (x, 2)); | |
3738 | break; | |
ee5332b8 | 3739 | |
ec8e098d PB |
3740 | default: |
3741 | break; | |
7afe21cc RK |
3742 | } |
3743 | ||
32e9fa48 | 3744 | return new_rtx ? new_rtx : x; |
7afe21cc RK |
3745 | } |
3746 | \f | |
3747 | /* Return a constant value currently equivalent to X. | |
3748 | Return 0 if we don't know one. */ | |
3749 | ||
3750 | static rtx | |
7080f735 | 3751 | equiv_constant (rtx x) |
7afe21cc | 3752 | { |
f8cfc6aa | 3753 | if (REG_P (x) |
1bb98cec DM |
3754 | && REGNO_QTY_VALID_P (REGNO (x))) |
3755 | { | |
3756 | int x_q = REG_QTY (REGNO (x)); | |
3757 | struct qty_table_elem *x_ent = &qty_table[x_q]; | |
3758 | ||
3759 | if (x_ent->const_rtx) | |
4de249d9 | 3760 | x = gen_lowpart (GET_MODE (x), x_ent->const_rtx); |
1bb98cec | 3761 | } |
7afe21cc | 3762 | |
2ce5e1b4 | 3763 | if (x == 0 || CONSTANT_P (x)) |
7afe21cc RK |
3764 | return x; |
3765 | ||
a52b023a PB |
3766 | if (GET_CODE (x) == SUBREG) |
3767 | { | |
ef4bddc2 RS |
3768 | machine_mode mode = GET_MODE (x); |
3769 | machine_mode imode = GET_MODE (SUBREG_REG (x)); | |
32e9fa48 | 3770 | rtx new_rtx; |
a52b023a PB |
3771 | |
3772 | /* See if we previously assigned a constant value to this SUBREG. */ | |
32e9fa48 | 3773 | if ((new_rtx = lookup_as_function (x, CONST_INT)) != 0 |
807e902e | 3774 | || (new_rtx = lookup_as_function (x, CONST_WIDE_INT)) != 0 |
0c12fc9b RS |
3775 | || (NUM_POLY_INT_COEFFS > 1 |
3776 | && (new_rtx = lookup_as_function (x, CONST_POLY_INT)) != 0) | |
32e9fa48 KG |
3777 | || (new_rtx = lookup_as_function (x, CONST_DOUBLE)) != 0 |
3778 | || (new_rtx = lookup_as_function (x, CONST_FIXED)) != 0) | |
3779 | return new_rtx; | |
a52b023a | 3780 | |
f5f8d79d EB |
3781 | /* If we didn't and if doing so makes sense, see if we previously |
3782 | assigned a constant value to the enclosing word mode SUBREG. */ | |
cf098191 RS |
3783 | if (known_lt (GET_MODE_SIZE (mode), UNITS_PER_WORD) |
3784 | && known_lt (UNITS_PER_WORD, GET_MODE_SIZE (imode))) | |
f5f8d79d | 3785 | { |
91914e56 RS |
3786 | poly_int64 byte = (SUBREG_BYTE (x) |
3787 | - subreg_lowpart_offset (mode, word_mode)); | |
3788 | if (known_ge (byte, 0) && multiple_p (byte, UNITS_PER_WORD)) | |
f5f8d79d EB |
3789 | { |
3790 | rtx y = gen_rtx_SUBREG (word_mode, SUBREG_REG (x), byte); | |
3791 | new_rtx = lookup_as_function (y, CONST_INT); | |
3792 | if (new_rtx) | |
3793 | return gen_lowpart (mode, new_rtx); | |
3794 | } | |
3795 | } | |
3796 | ||
7cb6668a MI |
3797 | /* Otherwise see if we already have a constant for the inner REG, |
3798 | and if that is enough to calculate an equivalent constant for | |
3799 | the subreg. Note that the upper bits of paradoxical subregs | |
3800 | are undefined, so they cannot be said to equal anything. */ | |
a52b023a | 3801 | if (REG_P (SUBREG_REG (x)) |
03a95621 | 3802 | && !paradoxical_subreg_p (x) |
32e9fa48 | 3803 | && (new_rtx = equiv_constant (SUBREG_REG (x))) != 0) |
f5f8d79d | 3804 | return simplify_subreg (mode, new_rtx, imode, SUBREG_BYTE (x)); |
a52b023a PB |
3805 | |
3806 | return 0; | |
3807 | } | |
3808 | ||
3809 | /* If X is a MEM, see if it is a constant-pool reference, or look it up in | |
3810 | the hash table in case its value was seen before. */ | |
fc3ffe83 | 3811 | |
3c0cb5de | 3812 | if (MEM_P (x)) |
fc3ffe83 RK |
3813 | { |
3814 | struct table_elt *elt; | |
3815 | ||
a52b023a | 3816 | x = avoid_constant_pool_reference (x); |
fc3ffe83 RK |
3817 | if (CONSTANT_P (x)) |
3818 | return x; | |
3819 | ||
0516f6fe | 3820 | elt = lookup (x, SAFE_HASH (x, GET_MODE (x)), GET_MODE (x)); |
fc3ffe83 RK |
3821 | if (elt == 0) |
3822 | return 0; | |
3823 | ||
3824 | for (elt = elt->first_same_value; elt; elt = elt->next_same_value) | |
3825 | if (elt->is_const && CONSTANT_P (elt->exp)) | |
3826 | return elt->exp; | |
3827 | } | |
3828 | ||
7afe21cc RK |
3829 | return 0; |
3830 | } | |
3831 | \f | |
0129d079 SB |
3832 | /* Given INSN, a jump insn, TAKEN indicates if we are following the |
3833 | "taken" branch. | |
7afe21cc RK |
3834 | |
3835 | In certain cases, this can cause us to add an equivalence. For example, | |
278a83b2 | 3836 | if we are following the taken case of |
7080f735 | 3837 | if (i == 2) |
7afe21cc RK |
3838 | we can add the fact that `i' and '2' are now equivalent. |
3839 | ||
3840 | In any case, we can record that this comparison was passed. If the same | |
3841 | comparison is seen later, we will know its value. */ | |
3842 | ||
3843 | static void | |
20468884 | 3844 | record_jump_equiv (rtx_insn *insn, bool taken) |
7afe21cc RK |
3845 | { |
3846 | int cond_known_true; | |
3847 | rtx op0, op1; | |
7f1c097d | 3848 | rtx set; |
ef4bddc2 | 3849 | machine_mode mode, mode0, mode1; |
7afe21cc RK |
3850 | enum rtx_code code; |
3851 | ||
3852 | /* Ensure this is the right kind of insn. */ | |
0129d079 SB |
3853 | gcc_assert (any_condjump_p (insn)); |
3854 | ||
7f1c097d | 3855 | set = pc_set (insn); |
7afe21cc RK |
3856 | |
3857 | /* See if this jump condition is known true or false. */ | |
3858 | if (taken) | |
7f1c097d | 3859 | cond_known_true = (XEXP (SET_SRC (set), 2) == pc_rtx); |
7afe21cc | 3860 | else |
7f1c097d | 3861 | cond_known_true = (XEXP (SET_SRC (set), 1) == pc_rtx); |
7afe21cc RK |
3862 | |
3863 | /* Get the type of comparison being done and the operands being compared. | |
3864 | If we had to reverse a non-equality condition, record that fact so we | |
3865 | know that it isn't valid for floating-point. */ | |
7f1c097d JH |
3866 | code = GET_CODE (XEXP (SET_SRC (set), 0)); |
3867 | op0 = fold_rtx (XEXP (XEXP (SET_SRC (set), 0), 0), insn); | |
3868 | op1 = fold_rtx (XEXP (XEXP (SET_SRC (set), 0), 1), insn); | |
7afe21cc | 3869 | |
bd1cd0d0 | 3870 | /* If fold_rtx returns NULL_RTX, there's nothing to record. */ |
3f1d32a5 JL |
3871 | if (op0 == NULL_RTX || op1 == NULL_RTX) |
3872 | return; | |
3873 | ||
13c9910f | 3874 | code = find_comparison_args (code, &op0, &op1, &mode0, &mode1); |
7afe21cc RK |
3875 | if (! cond_known_true) |
3876 | { | |
261efdef | 3877 | code = reversed_comparison_code_parts (code, op0, op1, insn); |
1eb8759b RH |
3878 | |
3879 | /* Don't remember if we can't find the inverse. */ | |
3880 | if (code == UNKNOWN) | |
3881 | return; | |
7afe21cc RK |
3882 | } |
3883 | ||
3884 | /* The mode is the mode of the non-constant. */ | |
13c9910f RS |
3885 | mode = mode0; |
3886 | if (mode1 != VOIDmode) | |
3887 | mode = mode1; | |
7afe21cc | 3888 | |
dec7aaab | 3889 | record_jump_cond (code, mode, op0, op1); |
7afe21cc RK |
3890 | } |
3891 | ||
794693c0 RH |
3892 | /* Yet another form of subreg creation. In this case, we want something in |
3893 | MODE, and we should assume OP has MODE iff it is naturally modeless. */ | |
3894 | ||
3895 | static rtx | |
ef4bddc2 | 3896 | record_jump_cond_subreg (machine_mode mode, rtx op) |
794693c0 | 3897 | { |
ef4bddc2 | 3898 | machine_mode op_mode = GET_MODE (op); |
794693c0 RH |
3899 | if (op_mode == mode || op_mode == VOIDmode) |
3900 | return op; | |
3901 | return lowpart_subreg (mode, op, op_mode); | |
3902 | } | |
3903 | ||
7afe21cc | 3904 | /* We know that comparison CODE applied to OP0 and OP1 in MODE is true. |
7afe21cc RK |
3905 | Make any useful entries we can with that information. Called from |
3906 | above function and called recursively. */ | |
3907 | ||
3908 | static void | |
dec7aaab | 3909 | record_jump_cond (enum rtx_code code, machine_mode mode, rtx op0, rtx op1) |
7afe21cc | 3910 | { |
2197a88a | 3911 | unsigned op0_hash, op1_hash; |
e428d738 | 3912 | int op0_in_memory, op1_in_memory; |
7afe21cc RK |
3913 | struct table_elt *op0_elt, *op1_elt; |
3914 | ||
3915 | /* If OP0 and OP1 are known equal, and either is a paradoxical SUBREG, | |
3916 | we know that they are also equal in the smaller mode (this is also | |
3917 | true for all smaller modes whether or not there is a SUBREG, but | |
ac7ef8d5 | 3918 | is not worth testing for with no SUBREG). */ |
7afe21cc | 3919 | |
2e794ee8 | 3920 | /* Note that GET_MODE (op0) may not equal MODE. */ |
6a4bdc79 | 3921 | if (code == EQ && paradoxical_subreg_p (op0)) |
7afe21cc | 3922 | { |
ef4bddc2 | 3923 | machine_mode inner_mode = GET_MODE (SUBREG_REG (op0)); |
794693c0 RH |
3924 | rtx tem = record_jump_cond_subreg (inner_mode, op1); |
3925 | if (tem) | |
dec7aaab | 3926 | record_jump_cond (code, mode, SUBREG_REG (op0), tem); |
7afe21cc RK |
3927 | } |
3928 | ||
6a4bdc79 | 3929 | if (code == EQ && paradoxical_subreg_p (op1)) |
7afe21cc | 3930 | { |
ef4bddc2 | 3931 | machine_mode inner_mode = GET_MODE (SUBREG_REG (op1)); |
794693c0 RH |
3932 | rtx tem = record_jump_cond_subreg (inner_mode, op0); |
3933 | if (tem) | |
dec7aaab | 3934 | record_jump_cond (code, mode, SUBREG_REG (op1), tem); |
7afe21cc RK |
3935 | } |
3936 | ||
278a83b2 | 3937 | /* Similarly, if this is an NE comparison, and either is a SUBREG |
7afe21cc RK |
3938 | making a smaller mode, we know the whole thing is also NE. */ |
3939 | ||
2e794ee8 RS |
3940 | /* Note that GET_MODE (op0) may not equal MODE; |
3941 | if we test MODE instead, we can get an infinite recursion | |
3942 | alternating between two modes each wider than MODE. */ | |
3943 | ||
bd4288c0 RS |
3944 | if (code == NE |
3945 | && partial_subreg_p (op0) | |
3946 | && subreg_lowpart_p (op0)) | |
7afe21cc | 3947 | { |
ef4bddc2 | 3948 | machine_mode inner_mode = GET_MODE (SUBREG_REG (op0)); |
794693c0 RH |
3949 | rtx tem = record_jump_cond_subreg (inner_mode, op1); |
3950 | if (tem) | |
dec7aaab | 3951 | record_jump_cond (code, mode, SUBREG_REG (op0), tem); |
7afe21cc RK |
3952 | } |
3953 | ||
bd4288c0 RS |
3954 | if (code == NE |
3955 | && partial_subreg_p (op1) | |
3956 | && subreg_lowpart_p (op1)) | |
7afe21cc | 3957 | { |
ef4bddc2 | 3958 | machine_mode inner_mode = GET_MODE (SUBREG_REG (op1)); |
794693c0 RH |
3959 | rtx tem = record_jump_cond_subreg (inner_mode, op0); |
3960 | if (tem) | |
dec7aaab | 3961 | record_jump_cond (code, mode, SUBREG_REG (op1), tem); |
7afe21cc RK |
3962 | } |
3963 | ||
3964 | /* Hash both operands. */ | |
3965 | ||
3966 | do_not_record = 0; | |
3967 | hash_arg_in_memory = 0; | |
2197a88a | 3968 | op0_hash = HASH (op0, mode); |
7afe21cc | 3969 | op0_in_memory = hash_arg_in_memory; |
7afe21cc RK |
3970 | |
3971 | if (do_not_record) | |
3972 | return; | |
3973 | ||
3974 | do_not_record = 0; | |
3975 | hash_arg_in_memory = 0; | |
2197a88a | 3976 | op1_hash = HASH (op1, mode); |
7afe21cc | 3977 | op1_in_memory = hash_arg_in_memory; |
278a83b2 | 3978 | |
7afe21cc RK |
3979 | if (do_not_record) |
3980 | return; | |
3981 | ||
3982 | /* Look up both operands. */ | |
2197a88a RK |
3983 | op0_elt = lookup (op0, op0_hash, mode); |
3984 | op1_elt = lookup (op1, op1_hash, mode); | |
7afe21cc | 3985 | |
af3869c1 RK |
3986 | /* If both operands are already equivalent or if they are not in the |
3987 | table but are identical, do nothing. */ | |
3988 | if ((op0_elt != 0 && op1_elt != 0 | |
3989 | && op0_elt->first_same_value == op1_elt->first_same_value) | |
3990 | || op0 == op1 || rtx_equal_p (op0, op1)) | |
3991 | return; | |
3992 | ||
7afe21cc | 3993 | /* If we aren't setting two things equal all we can do is save this |
b2796a4b RK |
3994 | comparison. Similarly if this is floating-point. In the latter |
3995 | case, OP1 might be zero and both -0.0 and 0.0 are equal to it. | |
3996 | If we record the equality, we might inadvertently delete code | |
3997 | whose intent was to change -0 to +0. */ | |
3998 | ||
cbf6a543 | 3999 | if (code != EQ || FLOAT_MODE_P (GET_MODE (op0))) |
7afe21cc | 4000 | { |
1bb98cec DM |
4001 | struct qty_table_elem *ent; |
4002 | int qty; | |
4003 | ||
dec7aaab UB |
4004 | /* If OP0 is not a register, or if OP1 is neither a register |
4005 | or constant, we can't do anything. */ | |
7afe21cc | 4006 | |
f8cfc6aa | 4007 | if (!REG_P (op1)) |
7afe21cc RK |
4008 | op1 = equiv_constant (op1); |
4009 | ||
dec7aaab | 4010 | if (!REG_P (op0) || op1 == 0) |
7afe21cc RK |
4011 | return; |
4012 | ||
4013 | /* Put OP0 in the hash table if it isn't already. This gives it a | |
4014 | new quantity number. */ | |
4015 | if (op0_elt == 0) | |
4016 | { | |
dec7aaab | 4017 | if (insert_regs (op0, NULL, false)) |
7afe21cc RK |
4018 | { |
4019 | rehash_using_reg (op0); | |
2197a88a | 4020 | op0_hash = HASH (op0, mode); |
2bb81c86 RK |
4021 | |
4022 | /* If OP0 is contained in OP1, this changes its hash code | |
4023 | as well. Faster to rehash than to check, except | |
4024 | for the simple case of a constant. */ | |
4025 | if (! CONSTANT_P (op1)) | |
2197a88a | 4026 | op1_hash = HASH (op1,mode); |
7afe21cc RK |
4027 | } |
4028 | ||
9714cf43 | 4029 | op0_elt = insert (op0, NULL, op0_hash, mode); |
7afe21cc | 4030 | op0_elt->in_memory = op0_in_memory; |
7afe21cc RK |
4031 | } |
4032 | ||
1bb98cec DM |
4033 | qty = REG_QTY (REGNO (op0)); |
4034 | ent = &qty_table[qty]; | |
4035 | ||
4036 | ent->comparison_code = code; | |
f8cfc6aa | 4037 | if (REG_P (op1)) |
7afe21cc | 4038 | { |
5d5ea909 | 4039 | /* Look it up again--in case op0 and op1 are the same. */ |
2197a88a | 4040 | op1_elt = lookup (op1, op1_hash, mode); |
5d5ea909 | 4041 | |
7afe21cc RK |
4042 | /* Put OP1 in the hash table so it gets a new quantity number. */ |
4043 | if (op1_elt == 0) | |
4044 | { | |
dec7aaab | 4045 | if (insert_regs (op1, NULL, false)) |
7afe21cc RK |
4046 | { |
4047 | rehash_using_reg (op1); | |
2197a88a | 4048 | op1_hash = HASH (op1, mode); |
7afe21cc RK |
4049 | } |
4050 | ||
9714cf43 | 4051 | op1_elt = insert (op1, NULL, op1_hash, mode); |
7afe21cc | 4052 | op1_elt->in_memory = op1_in_memory; |
7afe21cc RK |
4053 | } |
4054 | ||
1bb98cec DM |
4055 | ent->comparison_const = NULL_RTX; |
4056 | ent->comparison_qty = REG_QTY (REGNO (op1)); | |
7afe21cc RK |
4057 | } |
4058 | else | |
4059 | { | |
1bb98cec DM |
4060 | ent->comparison_const = op1; |
4061 | ent->comparison_qty = -1; | |
7afe21cc RK |
4062 | } |
4063 | ||
4064 | return; | |
4065 | } | |
4066 | ||
eb5ad42a RS |
4067 | /* If either side is still missing an equivalence, make it now, |
4068 | then merge the equivalences. */ | |
7afe21cc | 4069 | |
7afe21cc RK |
4070 | if (op0_elt == 0) |
4071 | { | |
dec7aaab | 4072 | if (insert_regs (op0, NULL, false)) |
7afe21cc RK |
4073 | { |
4074 | rehash_using_reg (op0); | |
2197a88a | 4075 | op0_hash = HASH (op0, mode); |
7afe21cc RK |
4076 | } |
4077 | ||
9714cf43 | 4078 | op0_elt = insert (op0, NULL, op0_hash, mode); |
7afe21cc | 4079 | op0_elt->in_memory = op0_in_memory; |
7afe21cc RK |
4080 | } |
4081 | ||
4082 | if (op1_elt == 0) | |
4083 | { | |
dec7aaab | 4084 | if (insert_regs (op1, NULL, false)) |
7afe21cc RK |
4085 | { |
4086 | rehash_using_reg (op1); | |
2197a88a | 4087 | op1_hash = HASH (op1, mode); |
7afe21cc RK |
4088 | } |
4089 | ||
9714cf43 | 4090 | op1_elt = insert (op1, NULL, op1_hash, mode); |
7afe21cc | 4091 | op1_elt->in_memory = op1_in_memory; |
7afe21cc | 4092 | } |
eb5ad42a RS |
4093 | |
4094 | merge_equiv_classes (op0_elt, op1_elt); | |
7afe21cc RK |
4095 | } |
4096 | \f | |
4097 | /* CSE processing for one instruction. | |
7b02f4e0 SB |
4098 | |
4099 | Most "true" common subexpressions are mostly optimized away in GIMPLE, | |
4100 | but the few that "leak through" are cleaned up by cse_insn, and complex | |
4101 | addressing modes are often formed here. | |
4102 | ||
4103 | The main function is cse_insn, and between here and that function | |
4104 | a couple of helper functions is defined to keep the size of cse_insn | |
4105 | within reasonable proportions. | |
4106 | ||
4107 | Data is shared between the main and helper functions via STRUCT SET, | |
4108 | that contains all data related for every set in the instruction that | |
4109 | is being processed. | |
4110 | ||
4111 | Note that cse_main processes all sets in the instruction. Most | |
4112 | passes in GCC only process simple SET insns or single_set insns, but | |
4113 | CSE processes insns with multiple sets as well. */ | |
7afe21cc RK |
4114 | |
4115 | /* Data on one SET contained in the instruction. */ | |
4116 | ||
4117 | struct set | |
4118 | { | |
4119 | /* The SET rtx itself. */ | |
4120 | rtx rtl; | |
4121 | /* The SET_SRC of the rtx (the original value, if it is changing). */ | |
4122 | rtx src; | |
4123 | /* The hash-table element for the SET_SRC of the SET. */ | |
4124 | struct table_elt *src_elt; | |
2197a88a RK |
4125 | /* Hash value for the SET_SRC. */ |
4126 | unsigned src_hash; | |
4127 | /* Hash value for the SET_DEST. */ | |
4128 | unsigned dest_hash; | |
7afe21cc RK |
4129 | /* The SET_DEST, with SUBREG, etc., stripped. */ |
4130 | rtx inner_dest; | |
278a83b2 | 4131 | /* Nonzero if the SET_SRC is in memory. */ |
7afe21cc | 4132 | char src_in_memory; |
7afe21cc RK |
4133 | /* Nonzero if the SET_SRC contains something |
4134 | whose value cannot be predicted and understood. */ | |
4135 | char src_volatile; | |
b14af304 PL |
4136 | /* Original machine mode, in case it becomes a CONST_INT. */ |
4137 | ENUM_BITFIELD(machine_mode) mode : MACHINE_MODE_BITSIZE; | |
2197a88a RK |
4138 | /* Hash value of constant equivalent for SET_SRC. */ |
4139 | unsigned src_const_hash; | |
34e82342 RB |
4140 | /* A constant equivalent for SET_SRC, if any. */ |
4141 | rtx src_const; | |
7afe21cc RK |
4142 | /* Table entry for constant equivalent for SET_SRC, if any. */ |
4143 | struct table_elt *src_const_elt; | |
05c433f3 PB |
4144 | /* Table entry for the destination address. */ |
4145 | struct table_elt *dest_addr_elt; | |
7afe21cc | 4146 | }; |
7b02f4e0 SB |
4147 | \f |
4148 | /* Special handling for (set REG0 REG1) where REG0 is the | |
4149 | "cheapest", cheaper than REG1. After cse, REG1 will probably not | |
4150 | be used in the sequel, so (if easily done) change this insn to | |
4151 | (set REG1 REG0) and replace REG1 with REG0 in the previous insn | |
4152 | that computed their value. Then REG1 will become a dead store | |
4153 | and won't cloud the situation for later optimizations. | |
4154 | ||
4155 | Do not make this change if REG1 is a hard register, because it will | |
4156 | then be used in the sequel and we may be changing a two-operand insn | |
4157 | into a three-operand insn. | |
4158 | ||
4159 | This is the last transformation that cse_insn will try to do. */ | |
7afe21cc RK |
4160 | |
4161 | static void | |
20468884 | 4162 | try_back_substitute_reg (rtx set, rtx_insn *insn) |
7afe21cc | 4163 | { |
7b02f4e0 SB |
4164 | rtx dest = SET_DEST (set); |
4165 | rtx src = SET_SRC (set); | |
7afe21cc | 4166 | |
7b02f4e0 SB |
4167 | if (REG_P (dest) |
4168 | && REG_P (src) && ! HARD_REGISTER_P (src) | |
4169 | && REGNO_QTY_VALID_P (REGNO (src))) | |
4170 | { | |
4171 | int src_q = REG_QTY (REGNO (src)); | |
4172 | struct qty_table_elem *src_ent = &qty_table[src_q]; | |
7afe21cc | 4173 | |
7b02f4e0 SB |
4174 | if (src_ent->first_reg == REGNO (dest)) |
4175 | { | |
4176 | /* Scan for the previous nonnote insn, but stop at a basic | |
4177 | block boundary. */ | |
20468884 DM |
4178 | rtx_insn *prev = insn; |
4179 | rtx_insn *bb_head = BB_HEAD (BLOCK_FOR_INSN (insn)); | |
7b02f4e0 SB |
4180 | do |
4181 | { | |
4182 | prev = PREV_INSN (prev); | |
4183 | } | |
4184 | while (prev != bb_head && (NOTE_P (prev) || DEBUG_INSN_P (prev))); | |
7afe21cc | 4185 | |
7b02f4e0 SB |
4186 | /* Do not swap the registers around if the previous instruction |
4187 | attaches a REG_EQUIV note to REG1. | |
7afe21cc | 4188 | |
7b02f4e0 SB |
4189 | ??? It's not entirely clear whether we can transfer a REG_EQUIV |
4190 | from the pseudo that originally shadowed an incoming argument | |
4191 | to another register. Some uses of REG_EQUIV might rely on it | |
4192 | being attached to REG1 rather than REG2. | |
7afe21cc | 4193 | |
7b02f4e0 SB |
4194 | This section previously turned the REG_EQUIV into a REG_EQUAL |
4195 | note. We cannot do that because REG_EQUIV may provide an | |
4196 | uninitialized stack slot when REG_PARM_STACK_SPACE is used. */ | |
4197 | if (NONJUMP_INSN_P (prev) | |
4198 | && GET_CODE (PATTERN (prev)) == SET | |
4199 | && SET_DEST (PATTERN (prev)) == src | |
4200 | && ! find_reg_note (prev, REG_EQUIV, NULL_RTX)) | |
4201 | { | |
4202 | rtx note; | |
4203 | ||
4204 | validate_change (prev, &SET_DEST (PATTERN (prev)), dest, 1); | |
4205 | validate_change (insn, &SET_DEST (set), src, 1); | |
4206 | validate_change (insn, &SET_SRC (set), dest, 1); | |
4207 | apply_change_group (); | |
4208 | ||
4209 | /* If INSN has a REG_EQUAL note, and this note mentions | |
4210 | REG0, then we must delete it, because the value in | |
4211 | REG0 has changed. If the note's value is REG1, we must | |
4212 | also delete it because that is now this insn's dest. */ | |
4213 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
4214 | if (note != 0 | |
4215 | && (reg_mentioned_p (dest, XEXP (note, 0)) | |
4216 | || rtx_equal_p (src, XEXP (note, 0)))) | |
4217 | remove_note (insn, note); | |
966a140d JL |
4218 | |
4219 | /* If INSN has a REG_ARGS_SIZE note, move it to PREV. */ | |
4220 | note = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX); | |
4221 | if (note != 0) | |
4222 | { | |
4223 | remove_note (insn, note); | |
4224 | gcc_assert (!find_reg_note (prev, REG_ARGS_SIZE, NULL_RTX)); | |
4225 | set_unique_reg_note (prev, REG_ARGS_SIZE, XEXP (note, 0)); | |
4226 | } | |
7b02f4e0 | 4227 | } |
f474c6f8 | 4228 | } |
f1e7c95f | 4229 | } |
7b02f4e0 | 4230 | } |
68b48f3f TC |
4231 | |
4232 | /* Add an entry containing RTL X into SETS. */ | |
4233 | static inline void | |
4234 | add_to_set (vec<struct set> *sets, rtx x) | |
4235 | { | |
4236 | struct set entry = {}; | |
4237 | entry.rtl = x; | |
4238 | sets->safe_push (entry); | |
4239 | } | |
4240 | ||
7b02f4e0 SB |
4241 | /* Record all the SETs in this instruction into SETS_PTR, |
4242 | and return the number of recorded sets. */ | |
4243 | static int | |
68b48f3f | 4244 | find_sets_in_insn (rtx_insn *insn, vec<struct set> *psets) |
7b02f4e0 | 4245 | { |
7b02f4e0 | 4246 | rtx x = PATTERN (insn); |
f1e7c95f | 4247 | |
7afe21cc RK |
4248 | if (GET_CODE (x) == SET) |
4249 | { | |
7afe21cc RK |
4250 | /* Ignore SETs that are unconditional jumps. |
4251 | They never need cse processing, so this does not hurt. | |
4252 | The reason is not efficiency but rather | |
4253 | so that we can test at the end for instructions | |
4254 | that have been simplified to unconditional jumps | |
4255 | and not be misled by unchanged instructions | |
4256 | that were unconditional jumps to begin with. */ | |
4257 | if (SET_DEST (x) == pc_rtx | |
4258 | && GET_CODE (SET_SRC (x)) == LABEL_REF) | |
4259 | ; | |
7afe21cc RK |
4260 | /* Don't count call-insns, (set (reg 0) (call ...)), as a set. |
4261 | The hard function value register is used only once, to copy to | |
7b02f4e0 | 4262 | someplace else, so it isn't worth cse'ing. */ |
7afe21cc | 4263 | else if (GET_CODE (SET_SRC (x)) == CALL) |
7b02f4e0 | 4264 | ; |
68b48f3f | 4265 | else if (GET_CODE (SET_SRC (x)) == CONST_VECTOR |
c2c84384 TC |
4266 | && GET_MODE_CLASS (GET_MODE (SET_SRC (x))) != MODE_VECTOR_BOOL |
4267 | /* Prevent duplicates from being generated if the type is a V1 | |
4268 | type and a subreg. Folding this will result in the same | |
4269 | element as folding x itself. */ | |
4270 | && !(SUBREG_P (SET_DEST (x)) | |
4271 | && known_eq (GET_MODE_NUNITS (GET_MODE (SET_SRC (x))), 1))) | |
68b48f3f TC |
4272 | { |
4273 | /* First register the vector itself. */ | |
4274 | add_to_set (psets, x); | |
4275 | rtx src = SET_SRC (x); | |
4276 | /* Go over the constants of the CONST_VECTOR in forward order, to | |
4277 | put them in the same order in the SETS array. */ | |
4278 | for (unsigned i = 0; i < const_vector_encoded_nelts (src) ; i++) | |
4279 | { | |
4280 | /* These are templates and don't actually get emitted but are | |
4281 | used to tell CSE how to get to a particular constant. */ | |
4282 | rtx y = simplify_gen_vec_select (SET_DEST (x), i); | |
4283 | gcc_assert (y); | |
4284 | add_to_set (psets, gen_rtx_SET (y, CONST_VECTOR_ELT (src, i))); | |
4285 | } | |
4286 | } | |
7afe21cc | 4287 | else |
68b48f3f | 4288 | add_to_set (psets, x); |
7afe21cc RK |
4289 | } |
4290 | else if (GET_CODE (x) == PARALLEL) | |
4291 | { | |
7b02f4e0 | 4292 | int i, lim = XVECLEN (x, 0); |
278a83b2 | 4293 | |
6c4d60f8 | 4294 | /* Go over the expressions of the PARALLEL in forward order, to |
7b02f4e0 | 4295 | put them in the same order in the SETS array. */ |
7afe21cc RK |
4296 | for (i = 0; i < lim; i++) |
4297 | { | |
b3694847 | 4298 | rtx y = XVECEXP (x, 0, i); |
7afe21cc RK |
4299 | if (GET_CODE (y) == SET) |
4300 | { | |
7722328e RK |
4301 | /* As above, we ignore unconditional jumps and call-insns and |
4302 | ignore the result of apply_change_group. */ | |
7b02f4e0 SB |
4303 | if (SET_DEST (y) == pc_rtx |
4304 | && GET_CODE (SET_SRC (y)) == LABEL_REF) | |
4305 | ; | |
4306 | else if (GET_CODE (SET_SRC (y)) == CALL) | |
7afe21cc RK |
4307 | ; |
4308 | else | |
68b48f3f | 4309 | add_to_set (psets, y); |
7afe21cc | 4310 | } |
7afe21cc RK |
4311 | } |
4312 | } | |
7b02f4e0 | 4313 | |
68b48f3f | 4314 | return psets->length (); |
7b02f4e0 SB |
4315 | } |
4316 | \f | |
6380a82e EB |
4317 | /* Subroutine of canonicalize_insn. X is an ASM_OPERANDS in INSN. */ |
4318 | ||
4319 | static void | |
4320 | canon_asm_operands (rtx x, rtx_insn *insn) | |
4321 | { | |
4322 | for (int i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--) | |
4323 | { | |
4324 | rtx input = ASM_OPERANDS_INPUT (x, i); | |
4325 | if (!(REG_P (input) && HARD_REGISTER_P (input))) | |
4326 | { | |
4327 | input = canon_reg (input, insn); | |
4328 | validate_change (insn, &ASM_OPERANDS_INPUT (x, i), input, 1); | |
4329 | } | |
4330 | } | |
4331 | } | |
4332 | ||
7b02f4e0 | 4333 | /* Where possible, substitute every register reference in the N_SETS |
026c3cfd | 4334 | number of SETS in INSN with the canonical register. |
7b02f4e0 SB |
4335 | |
4336 | Register canonicalization propagatest the earliest register (i.e. | |
4337 | one that is set before INSN) with the same value. This is a very | |
4338 | useful, simple form of CSE, to clean up warts from expanding GIMPLE | |
4339 | to RTL. For instance, a CONST for an address is usually expanded | |
4340 | multiple times to loads into different registers, thus creating many | |
4341 | subexpressions of the form: | |
4342 | ||
4343 | (set (reg1) (some_const)) | |
4344 | (set (mem (... reg1 ...) (thing))) | |
4345 | (set (reg2) (some_const)) | |
4346 | (set (mem (... reg2 ...) (thing))) | |
4347 | ||
4348 | After canonicalizing, the code takes the following form: | |
4349 | ||
4350 | (set (reg1) (some_const)) | |
4351 | (set (mem (... reg1 ...) (thing))) | |
4352 | (set (reg2) (some_const)) | |
4353 | (set (mem (... reg1 ...) (thing))) | |
4354 | ||
4355 | The set to reg2 is now trivially dead, and the memory reference (or | |
4356 | address, or whatever) may be a candidate for further CSEing. | |
4357 | ||
4358 | In this function, the result of apply_change_group can be ignored; | |
4359 | see canon_reg. */ | |
4360 | ||
4361 | static void | |
68b48f3f | 4362 | canonicalize_insn (rtx_insn *insn, vec<struct set> *psets) |
7b02f4e0 | 4363 | { |
68b48f3f TC |
4364 | vec<struct set> sets = *psets; |
4365 | int n_sets = sets.length (); | |
7b02f4e0 SB |
4366 | rtx tem; |
4367 | rtx x = PATTERN (insn); | |
4368 | int i; | |
4369 | ||
4370 | if (CALL_P (insn)) | |
4371 | { | |
4372 | for (tem = CALL_INSN_FUNCTION_USAGE (insn); tem; tem = XEXP (tem, 1)) | |
e384e6b5 BS |
4373 | if (GET_CODE (XEXP (tem, 0)) != SET) |
4374 | XEXP (tem, 0) = canon_reg (XEXP (tem, 0), insn); | |
7b02f4e0 SB |
4375 | } |
4376 | ||
4377 | if (GET_CODE (x) == SET && GET_CODE (SET_SRC (x)) == CALL) | |
4378 | { | |
4379 | canon_reg (SET_SRC (x), insn); | |
4380 | apply_change_group (); | |
4381 | fold_rtx (SET_SRC (x), insn); | |
4382 | } | |
7afe21cc RK |
4383 | else if (GET_CODE (x) == CLOBBER) |
4384 | { | |
7b02f4e0 SB |
4385 | /* If we clobber memory, canon the address. |
4386 | This does nothing when a register is clobbered | |
4387 | because we have already invalidated the reg. */ | |
3c0cb5de | 4388 | if (MEM_P (XEXP (x, 0))) |
6fb5fa3c | 4389 | canon_reg (XEXP (x, 0), insn); |
7afe21cc | 4390 | } |
7afe21cc | 4391 | else if (GET_CODE (x) == USE |
f8cfc6aa | 4392 | && ! (REG_P (XEXP (x, 0)) |
7afe21cc | 4393 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)) |
7b02f4e0 | 4394 | /* Canonicalize a USE of a pseudo register or memory location. */ |
b1ba284c EB |
4395 | canon_reg (x, insn); |
4396 | else if (GET_CODE (x) == ASM_OPERANDS) | |
6380a82e | 4397 | canon_asm_operands (x, insn); |
7afe21cc RK |
4398 | else if (GET_CODE (x) == CALL) |
4399 | { | |
4400 | canon_reg (x, insn); | |
77fa0940 | 4401 | apply_change_group (); |
7afe21cc RK |
4402 | fold_rtx (x, insn); |
4403 | } | |
b5b8b0ac AO |
4404 | else if (DEBUG_INSN_P (insn)) |
4405 | canon_reg (PATTERN (insn), insn); | |
7b02f4e0 SB |
4406 | else if (GET_CODE (x) == PARALLEL) |
4407 | { | |
4408 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
4409 | { | |
4410 | rtx y = XVECEXP (x, 0, i); | |
4411 | if (GET_CODE (y) == SET && GET_CODE (SET_SRC (y)) == CALL) | |
4412 | { | |
4413 | canon_reg (SET_SRC (y), insn); | |
4414 | apply_change_group (); | |
4415 | fold_rtx (SET_SRC (y), insn); | |
4416 | } | |
4417 | else if (GET_CODE (y) == CLOBBER) | |
4418 | { | |
4419 | if (MEM_P (XEXP (y, 0))) | |
4420 | canon_reg (XEXP (y, 0), insn); | |
4421 | } | |
4422 | else if (GET_CODE (y) == USE | |
4423 | && ! (REG_P (XEXP (y, 0)) | |
4424 | && REGNO (XEXP (y, 0)) < FIRST_PSEUDO_REGISTER)) | |
4425 | canon_reg (y, insn); | |
6380a82e EB |
4426 | else if (GET_CODE (y) == ASM_OPERANDS) |
4427 | canon_asm_operands (y, insn); | |
7b02f4e0 SB |
4428 | else if (GET_CODE (y) == CALL) |
4429 | { | |
4430 | canon_reg (y, insn); | |
4431 | apply_change_group (); | |
4432 | fold_rtx (y, insn); | |
4433 | } | |
4434 | } | |
4435 | } | |
7afe21cc | 4436 | |
92f9aa51 | 4437 | if (n_sets == 1 && REG_NOTES (insn) != 0 |
7b02f4e0 | 4438 | && (tem = find_reg_note (insn, REG_EQUAL, NULL_RTX)) != 0) |
7b668f9e | 4439 | { |
7b02f4e0 SB |
4440 | /* We potentially will process this insn many times. Therefore, |
4441 | drop the REG_EQUAL note if it is equal to the SET_SRC of the | |
4442 | unique set in INSN. | |
4443 | ||
4444 | Do not do so if the REG_EQUAL note is for a STRICT_LOW_PART, | |
4445 | because cse_insn handles those specially. */ | |
4446 | if (GET_CODE (SET_DEST (sets[0].rtl)) != STRICT_LOW_PART | |
4447 | && rtx_equal_p (XEXP (tem, 0), SET_SRC (sets[0].rtl))) | |
4448 | remove_note (insn, tem); | |
4449 | else | |
4450 | { | |
4451 | canon_reg (XEXP (tem, 0), insn); | |
4452 | apply_change_group (); | |
4453 | XEXP (tem, 0) = fold_rtx (XEXP (tem, 0), insn); | |
4454 | df_notes_rescan (insn); | |
4455 | } | |
7b668f9e | 4456 | } |
7afe21cc RK |
4457 | |
4458 | /* Canonicalize sources and addresses of destinations. | |
4459 | We do this in a separate pass to avoid problems when a MATCH_DUP is | |
4460 | present in the insn pattern. In that case, we want to ensure that | |
4461 | we don't break the duplicate nature of the pattern. So we will replace | |
4462 | both operands at the same time. Otherwise, we would fail to find an | |
4463 | equivalent substitution in the loop calling validate_change below. | |
7afe21cc RK |
4464 | |
4465 | We used to suppress canonicalization of DEST if it appears in SRC, | |
77fa0940 | 4466 | but we don't do this any more. */ |
7afe21cc RK |
4467 | |
4468 | for (i = 0; i < n_sets; i++) | |
4469 | { | |
4470 | rtx dest = SET_DEST (sets[i].rtl); | |
4471 | rtx src = SET_SRC (sets[i].rtl); | |
32e9fa48 | 4472 | rtx new_rtx = canon_reg (src, insn); |
7afe21cc | 4473 | |
32e9fa48 | 4474 | validate_change (insn, &SET_SRC (sets[i].rtl), new_rtx, 1); |
7afe21cc | 4475 | |
46d096a3 | 4476 | if (GET_CODE (dest) == ZERO_EXTRACT) |
7afe21cc RK |
4477 | { |
4478 | validate_change (insn, &XEXP (dest, 1), | |
77fa0940 | 4479 | canon_reg (XEXP (dest, 1), insn), 1); |
7afe21cc | 4480 | validate_change (insn, &XEXP (dest, 2), |
77fa0940 | 4481 | canon_reg (XEXP (dest, 2), insn), 1); |
7afe21cc RK |
4482 | } |
4483 | ||
46d096a3 | 4484 | while (GET_CODE (dest) == SUBREG |
7afe21cc | 4485 | || GET_CODE (dest) == ZERO_EXTRACT |
46d096a3 | 4486 | || GET_CODE (dest) == STRICT_LOW_PART) |
7afe21cc RK |
4487 | dest = XEXP (dest, 0); |
4488 | ||
3c0cb5de | 4489 | if (MEM_P (dest)) |
7afe21cc RK |
4490 | canon_reg (dest, insn); |
4491 | } | |
4492 | ||
77fa0940 RK |
4493 | /* Now that we have done all the replacements, we can apply the change |
4494 | group and see if they all work. Note that this will cause some | |
4495 | canonicalizations that would have worked individually not to be applied | |
4496 | because some other canonicalization didn't work, but this should not | |
278a83b2 | 4497 | occur often. |
7722328e RK |
4498 | |
4499 | The result of apply_change_group can be ignored; see canon_reg. */ | |
77fa0940 RK |
4500 | |
4501 | apply_change_group (); | |
7b02f4e0 SB |
4502 | } |
4503 | \f | |
4504 | /* Main function of CSE. | |
4505 | First simplify sources and addresses of all assignments | |
4506 | in the instruction, using previously-computed equivalents values. | |
4507 | Then install the new sources and destinations in the table | |
4508 | of available values. */ | |
4509 | ||
4510 | static void | |
20468884 | 4511 | cse_insn (rtx_insn *insn) |
7b02f4e0 SB |
4512 | { |
4513 | rtx x = PATTERN (insn); | |
4514 | int i; | |
4515 | rtx tem; | |
4516 | int n_sets = 0; | |
4517 | ||
4518 | rtx src_eqv = 0; | |
4519 | struct table_elt *src_eqv_elt = 0; | |
4520 | int src_eqv_volatile = 0; | |
4521 | int src_eqv_in_memory = 0; | |
4522 | unsigned src_eqv_hash = 0; | |
4523 | ||
7b02f4e0 | 4524 | this_insn = insn; |
7b02f4e0 SB |
4525 | |
4526 | /* Find all regs explicitly clobbered in this insn, | |
4527 | to ensure they are not replaced with any other regs | |
4528 | elsewhere in this insn. */ | |
4529 | invalidate_from_sets_and_clobbers (insn); | |
4530 | ||
4531 | /* Record all the SETs in this instruction. */ | |
68b48f3f TC |
4532 | auto_vec<struct set, 8> sets; |
4533 | n_sets = find_sets_in_insn (insn, (vec<struct set>*)&sets); | |
7b02f4e0 SB |
4534 | |
4535 | /* Substitute the canonical register where possible. */ | |
68b48f3f | 4536 | canonicalize_insn (insn, (vec<struct set>*)&sets); |
7b02f4e0 SB |
4537 | |
4538 | /* If this insn has a REG_EQUAL note, store the equivalent value in SRC_EQV, | |
7f7379f6 KV |
4539 | if different, or if the DEST is a STRICT_LOW_PART/ZERO_EXTRACT. The |
4540 | latter condition is necessary because SRC_EQV is handled specially for | |
4541 | this case, and if it isn't set, then there will be no equivalence | |
4542 | for the destination. */ | |
7b02f4e0 | 4543 | if (n_sets == 1 && REG_NOTES (insn) != 0 |
1e928e07 | 4544 | && (tem = find_reg_note (insn, REG_EQUAL, NULL_RTX)) != 0) |
7f7379f6 | 4545 | { |
7f7379f6 | 4546 | |
1e928e07 KV |
4547 | if (GET_CODE (SET_DEST (sets[0].rtl)) != ZERO_EXTRACT |
4548 | && (! rtx_equal_p (XEXP (tem, 0), SET_SRC (sets[0].rtl)) | |
4549 | || GET_CODE (SET_DEST (sets[0].rtl)) == STRICT_LOW_PART)) | |
4550 | src_eqv = copy_rtx (XEXP (tem, 0)); | |
7f7379f6 KV |
4551 | /* If DEST is of the form ZERO_EXTACT, as in: |
4552 | (set (zero_extract:SI (reg:SI 119) | |
4553 | (const_int 16 [0x10]) | |
4554 | (const_int 16 [0x10])) | |
4555 | (const_int 51154 [0xc7d2])) | |
4556 | REG_EQUAL note will specify the value of register (reg:SI 119) at this | |
4557 | point. Note that this is different from SRC_EQV. We can however | |
4558 | calculate SRC_EQV with the position and width of ZERO_EXTRACT. */ | |
4559 | else if (GET_CODE (SET_DEST (sets[0].rtl)) == ZERO_EXTRACT | |
fa24123b | 4560 | && CONST_INT_P (XEXP (tem, 0)) |
7f7379f6 KV |
4561 | && CONST_INT_P (XEXP (SET_DEST (sets[0].rtl), 1)) |
4562 | && CONST_INT_P (XEXP (SET_DEST (sets[0].rtl), 2))) | |
4563 | { | |
4564 | rtx dest_reg = XEXP (SET_DEST (sets[0].rtl), 0); | |
c7ad039d RS |
4565 | /* This is the mode of XEXP (tem, 0) as well. */ |
4566 | scalar_int_mode dest_mode | |
4567 | = as_a <scalar_int_mode> (GET_MODE (dest_reg)); | |
7f7379f6 KV |
4568 | rtx width = XEXP (SET_DEST (sets[0].rtl), 1); |
4569 | rtx pos = XEXP (SET_DEST (sets[0].rtl), 2); | |
fa24123b | 4570 | HOST_WIDE_INT val = INTVAL (XEXP (tem, 0)); |
7f7379f6 KV |
4571 | HOST_WIDE_INT mask; |
4572 | unsigned int shift; | |
4573 | if (BITS_BIG_ENDIAN) | |
c7ad039d RS |
4574 | shift = (GET_MODE_PRECISION (dest_mode) |
4575 | - INTVAL (pos) - INTVAL (width)); | |
7f7379f6 KV |
4576 | else |
4577 | shift = INTVAL (pos); | |
4578 | if (INTVAL (width) == HOST_BITS_PER_WIDE_INT) | |
dd4786fe | 4579 | mask = HOST_WIDE_INT_M1; |
7f7379f6 | 4580 | else |
fecfbfa4 | 4581 | mask = (HOST_WIDE_INT_1 << INTVAL (width)) - 1; |
7f7379f6 KV |
4582 | val = (val >> shift) & mask; |
4583 | src_eqv = GEN_INT (val); | |
4584 | } | |
4585 | } | |
77fa0940 | 4586 | |
7afe21cc RK |
4587 | /* Set sets[i].src_elt to the class each source belongs to. |
4588 | Detect assignments from or to volatile things | |
4589 | and set set[i] to zero so they will be ignored | |
4590 | in the rest of this function. | |
4591 | ||
4592 | Nothing in this loop changes the hash table or the register chains. */ | |
4593 | ||
4594 | for (i = 0; i < n_sets; i++) | |
4595 | { | |
b4ab701f | 4596 | bool repeat = false; |
4aded535 | 4597 | bool noop_insn = false; |
b3694847 SS |
4598 | rtx src, dest; |
4599 | rtx src_folded; | |
4600 | struct table_elt *elt = 0, *p; | |
ef4bddc2 | 4601 | machine_mode mode; |
7afe21cc RK |
4602 | rtx src_eqv_here; |
4603 | rtx src_const = 0; | |
4604 | rtx src_related = 0; | |
2961db43 | 4605 | rtx dest_related = 0; |
2c5bfdf7 | 4606 | bool src_related_is_const_anchor = false; |
7afe21cc | 4607 | struct table_elt *src_const_elt = 0; |
99a9c946 GS |
4608 | int src_cost = MAX_COST; |
4609 | int src_eqv_cost = MAX_COST; | |
4610 | int src_folded_cost = MAX_COST; | |
4611 | int src_related_cost = MAX_COST; | |
4612 | int src_elt_cost = MAX_COST; | |
4613 | int src_regcost = MAX_COST; | |
4614 | int src_eqv_regcost = MAX_COST; | |
4615 | int src_folded_regcost = MAX_COST; | |
4616 | int src_related_regcost = MAX_COST; | |
4617 | int src_elt_regcost = MAX_COST; | |
b4206259 | 4618 | scalar_int_mode int_mode; |
7afe21cc RK |
4619 | |
4620 | dest = SET_DEST (sets[i].rtl); | |
4621 | src = SET_SRC (sets[i].rtl); | |
4622 | ||
4623 | /* If SRC is a constant that has no machine mode, | |
4624 | hash it with the destination's machine mode. | |
4625 | This way we can keep different modes separate. */ | |
4626 | ||
4627 | mode = GET_MODE (src) == VOIDmode ? GET_MODE (dest) : GET_MODE (src); | |
4628 | sets[i].mode = mode; | |
4629 | ||
4630 | if (src_eqv) | |
4631 | { | |
ef4bddc2 | 4632 | machine_mode eqvmode = mode; |
7afe21cc RK |
4633 | if (GET_CODE (dest) == STRICT_LOW_PART) |
4634 | eqvmode = GET_MODE (SUBREG_REG (XEXP (dest, 0))); | |
4635 | do_not_record = 0; | |
4636 | hash_arg_in_memory = 0; | |
2197a88a | 4637 | src_eqv_hash = HASH (src_eqv, eqvmode); |
7afe21cc RK |
4638 | |
4639 | /* Find the equivalence class for the equivalent expression. */ | |
4640 | ||
4641 | if (!do_not_record) | |
2197a88a | 4642 | src_eqv_elt = lookup (src_eqv, src_eqv_hash, eqvmode); |
7afe21cc RK |
4643 | |
4644 | src_eqv_volatile = do_not_record; | |
4645 | src_eqv_in_memory = hash_arg_in_memory; | |
7afe21cc RK |
4646 | } |
4647 | ||
4648 | /* If this is a STRICT_LOW_PART assignment, src_eqv corresponds to the | |
4649 | value of the INNER register, not the destination. So it is not | |
3826a3da | 4650 | a valid substitution for the source. But save it for later. */ |
7afe21cc RK |
4651 | if (GET_CODE (dest) == STRICT_LOW_PART) |
4652 | src_eqv_here = 0; | |
4653 | else | |
4654 | src_eqv_here = src_eqv; | |
4655 | ||
4656 | /* Simplify and foldable subexpressions in SRC. Then get the fully- | |
4657 | simplified result, which may not necessarily be valid. */ | |
625d55af | 4658 | src_folded = fold_rtx (src, NULL); |
7afe21cc | 4659 | |
e6a125a0 RK |
4660 | #if 0 |
4661 | /* ??? This caused bad code to be generated for the m68k port with -O2. | |
4662 | Suppose src is (CONST_INT -1), and that after truncation src_folded | |
4663 | is (CONST_INT 3). Suppose src_folded is then used for src_const. | |
4664 | At the end we will add src and src_const to the same equivalence | |
4665 | class. We now have 3 and -1 on the same equivalence class. This | |
4666 | causes later instructions to be mis-optimized. */ | |
7afe21cc RK |
4667 | /* If storing a constant in a bitfield, pre-truncate the constant |
4668 | so we will be able to record it later. */ | |
46d096a3 | 4669 | if (GET_CODE (SET_DEST (sets[i].rtl)) == ZERO_EXTRACT) |
7afe21cc RK |
4670 | { |
4671 | rtx width = XEXP (SET_DEST (sets[i].rtl), 1); | |
4672 | ||
481683e1 SZ |
4673 | if (CONST_INT_P (src) |
4674 | && CONST_INT_P (width) | |
906c4e36 RK |
4675 | && INTVAL (width) < HOST_BITS_PER_WIDE_INT |
4676 | && (INTVAL (src) & ((HOST_WIDE_INT) (-1) << INTVAL (width)))) | |
4677 | src_folded | |
fecfbfa4 | 4678 | = GEN_INT (INTVAL (src) & ((HOST_WIDE_INT_1 |
906c4e36 | 4679 | << INTVAL (width)) - 1)); |
7afe21cc | 4680 | } |
e6a125a0 | 4681 | #endif |
7afe21cc RK |
4682 | |
4683 | /* Compute SRC's hash code, and also notice if it | |
4684 | should not be recorded at all. In that case, | |
3737ccc4 JL |
4685 | prevent any further processing of this assignment. |
4686 | ||
4687 | We set DO_NOT_RECORD if the destination has a REG_UNUSED note. | |
4688 | This avoids getting the source register into the tables, where it | |
4689 | may be invalidated later (via REG_QTY), then trigger an ICE upon | |
4690 | re-insertion. | |
4691 | ||
4692 | This is only a problem in multi-set insns. If it were a single | |
4693 | set the dead copy would have been removed. If the RHS were anything | |
4694 | but a simple REG, then we won't call insert_regs and thus there's | |
4695 | no potential for triggering the ICE. */ | |
4696 | do_not_record = (REG_P (dest) | |
4697 | && REG_P (src) | |
4698 | && find_reg_note (insn, REG_UNUSED, dest)); | |
7afe21cc | 4699 | hash_arg_in_memory = 0; |
7afe21cc RK |
4700 | |
4701 | sets[i].src = src; | |
2197a88a | 4702 | sets[i].src_hash = HASH (src, mode); |
7afe21cc RK |
4703 | sets[i].src_volatile = do_not_record; |
4704 | sets[i].src_in_memory = hash_arg_in_memory; | |
7afe21cc | 4705 | |
50196afa | 4706 | /* If SRC is a MEM, there is a REG_EQUIV note for SRC, and DEST is |
43e72072 JJ |
4707 | a pseudo, do not record SRC. Using SRC as a replacement for |
4708 | anything else will be incorrect in that situation. Note that | |
4709 | this usually occurs only for stack slots, in which case all the | |
4710 | RTL would be referring to SRC, so we don't lose any optimization | |
4711 | opportunities by not having SRC in the hash table. */ | |
50196afa | 4712 | |
3c0cb5de | 4713 | if (MEM_P (src) |
43e72072 | 4714 | && find_reg_note (insn, REG_EQUIV, NULL_RTX) != 0 |
f8cfc6aa | 4715 | && REG_P (dest) |
43e72072 | 4716 | && REGNO (dest) >= FIRST_PSEUDO_REGISTER) |
50196afa RK |
4717 | sets[i].src_volatile = 1; |
4718 | ||
d8d6ea53 JJ |
4719 | else if (GET_CODE (src) == ASM_OPERANDS |
4720 | && GET_CODE (x) == PARALLEL) | |
6c4d60f8 JJ |
4721 | { |
4722 | /* Do not record result of a non-volatile inline asm with | |
4723 | more than one result. */ | |
4724 | if (n_sets > 1) | |
4725 | sets[i].src_volatile = 1; | |
4726 | ||
4727 | int j, lim = XVECLEN (x, 0); | |
4728 | for (j = 0; j < lim; j++) | |
4729 | { | |
4730 | rtx y = XVECEXP (x, 0, j); | |
4731 | /* And do not record result of a non-volatile inline asm | |
4732 | with "memory" clobber. */ | |
4733 | if (GET_CODE (y) == CLOBBER && MEM_P (XEXP (y, 0))) | |
4734 | { | |
4735 | sets[i].src_volatile = 1; | |
4736 | break; | |
4737 | } | |
4738 | } | |
4739 | } | |
d8d6ea53 | 4740 | |
0dadecf6 RK |
4741 | #if 0 |
4742 | /* It is no longer clear why we used to do this, but it doesn't | |
4743 | appear to still be needed. So let's try without it since this | |
4744 | code hurts cse'ing widened ops. */ | |
9a5a17f3 | 4745 | /* If source is a paradoxical subreg (such as QI treated as an SI), |
7afe21cc RK |
4746 | treat it as volatile. It may do the work of an SI in one context |
4747 | where the extra bits are not being used, but cannot replace an SI | |
4748 | in general. */ | |
6a4bdc79 | 4749 | if (paradoxical_subreg_p (src)) |
7afe21cc | 4750 | sets[i].src_volatile = 1; |
0dadecf6 | 4751 | #endif |
7afe21cc RK |
4752 | |
4753 | /* Locate all possible equivalent forms for SRC. Try to replace | |
4754 | SRC in the insn with each cheaper equivalent. | |
4755 | ||
4756 | We have the following types of equivalents: SRC itself, a folded | |
4757 | version, a value given in a REG_EQUAL note, or a value related | |
4758 | to a constant. | |
4759 | ||
4760 | Each of these equivalents may be part of an additional class | |
4761 | of equivalents (if more than one is in the table, they must be in | |
4762 | the same class; we check for this). | |
4763 | ||
4764 | If the source is volatile, we don't do any table lookups. | |
4765 | ||
4766 | We note any constant equivalent for possible later use in a | |
4767 | REG_NOTE. */ | |
4768 | ||
4769 | if (!sets[i].src_volatile) | |
2197a88a | 4770 | elt = lookup (src, sets[i].src_hash, mode); |
7afe21cc RK |
4771 | |
4772 | sets[i].src_elt = elt; | |
4773 | ||
4774 | if (elt && src_eqv_here && src_eqv_elt) | |
278a83b2 KH |
4775 | { |
4776 | if (elt->first_same_value != src_eqv_elt->first_same_value) | |
7afe21cc RK |
4777 | { |
4778 | /* The REG_EQUAL is indicating that two formerly distinct | |
4779 | classes are now equivalent. So merge them. */ | |
4780 | merge_equiv_classes (elt, src_eqv_elt); | |
2197a88a RK |
4781 | src_eqv_hash = HASH (src_eqv, elt->mode); |
4782 | src_eqv_elt = lookup (src_eqv, src_eqv_hash, elt->mode); | |
7afe21cc RK |
4783 | } |
4784 | ||
278a83b2 KH |
4785 | src_eqv_here = 0; |
4786 | } | |
7afe21cc RK |
4787 | |
4788 | else if (src_eqv_elt) | |
278a83b2 | 4789 | elt = src_eqv_elt; |
7afe21cc RK |
4790 | |
4791 | /* Try to find a constant somewhere and record it in `src_const'. | |
4792 | Record its table element, if any, in `src_const_elt'. Look in | |
4793 | any known equivalences first. (If the constant is not in the | |
2197a88a | 4794 | table, also set `sets[i].src_const_hash'). */ |
7afe21cc | 4795 | if (elt) |
278a83b2 | 4796 | for (p = elt->first_same_value; p; p = p->next_same_value) |
7afe21cc RK |
4797 | if (p->is_const) |
4798 | { | |
4799 | src_const = p->exp; | |
4800 | src_const_elt = elt; | |
4801 | break; | |
4802 | } | |
4803 | ||
4804 | if (src_const == 0 | |
4805 | && (CONSTANT_P (src_folded) | |
278a83b2 | 4806 | /* Consider (minus (label_ref L1) (label_ref L2)) as |
7afe21cc RK |
4807 | "constant" here so we will record it. This allows us |
4808 | to fold switch statements when an ADDR_DIFF_VEC is used. */ | |
4809 | || (GET_CODE (src_folded) == MINUS | |
4810 | && GET_CODE (XEXP (src_folded, 0)) == LABEL_REF | |
4811 | && GET_CODE (XEXP (src_folded, 1)) == LABEL_REF))) | |
4812 | src_const = src_folded, src_const_elt = elt; | |
4813 | else if (src_const == 0 && src_eqv_here && CONSTANT_P (src_eqv_here)) | |
4814 | src_const = src_eqv_here, src_const_elt = src_eqv_elt; | |
4815 | ||
4816 | /* If we don't know if the constant is in the table, get its | |
4817 | hash code and look it up. */ | |
4818 | if (src_const && src_const_elt == 0) | |
4819 | { | |
2197a88a RK |
4820 | sets[i].src_const_hash = HASH (src_const, mode); |
4821 | src_const_elt = lookup (src_const, sets[i].src_const_hash, mode); | |
7afe21cc RK |
4822 | } |
4823 | ||
4824 | sets[i].src_const = src_const; | |
4825 | sets[i].src_const_elt = src_const_elt; | |
4826 | ||
4827 | /* If the constant and our source are both in the table, mark them as | |
4828 | equivalent. Otherwise, if a constant is in the table but the source | |
4829 | isn't, set ELT to it. */ | |
4830 | if (src_const_elt && elt | |
4831 | && src_const_elt->first_same_value != elt->first_same_value) | |
4832 | merge_equiv_classes (elt, src_const_elt); | |
4833 | else if (src_const_elt && elt == 0) | |
4834 | elt = src_const_elt; | |
4835 | ||
4836 | /* See if there is a register linearly related to a constant | |
4837 | equivalent of SRC. */ | |
4838 | if (src_const | |
4839 | && (GET_CODE (src_const) == CONST | |
4840 | || (src_const_elt && src_const_elt->related_value != 0))) | |
278a83b2 KH |
4841 | { |
4842 | src_related = use_related_value (src_const, src_const_elt); | |
4843 | if (src_related) | |
4844 | { | |
7afe21cc | 4845 | struct table_elt *src_related_elt |
278a83b2 | 4846 | = lookup (src_related, HASH (src_related, mode), mode); |
7afe21cc | 4847 | if (src_related_elt && elt) |
278a83b2 | 4848 | { |
7afe21cc RK |
4849 | if (elt->first_same_value |
4850 | != src_related_elt->first_same_value) | |
278a83b2 | 4851 | /* This can occur when we previously saw a CONST |
7afe21cc RK |
4852 | involving a SYMBOL_REF and then see the SYMBOL_REF |
4853 | twice. Merge the involved classes. */ | |
4854 | merge_equiv_classes (elt, src_related_elt); | |
4855 | ||
278a83b2 | 4856 | src_related = 0; |
7afe21cc | 4857 | src_related_elt = 0; |
278a83b2 KH |
4858 | } |
4859 | else if (src_related_elt && elt == 0) | |
4860 | elt = src_related_elt; | |
7afe21cc | 4861 | } |
278a83b2 | 4862 | } |
7afe21cc | 4863 | |
e4600702 RK |
4864 | /* See if we have a CONST_INT that is already in a register in a |
4865 | wider mode. */ | |
4866 | ||
481683e1 | 4867 | if (src_const && src_related == 0 && CONST_INT_P (src_const) |
b4206259 RS |
4868 | && is_int_mode (mode, &int_mode) |
4869 | && GET_MODE_PRECISION (int_mode) < BITS_PER_WORD) | |
e4600702 | 4870 | { |
b4206259 RS |
4871 | opt_scalar_int_mode wider_mode_iter; |
4872 | FOR_EACH_WIDER_MODE (wider_mode_iter, int_mode) | |
e4600702 | 4873 | { |
b4206259 | 4874 | scalar_int_mode wider_mode = wider_mode_iter.require (); |
c94843d2 RS |
4875 | if (GET_MODE_PRECISION (wider_mode) > BITS_PER_WORD) |
4876 | break; | |
4877 | ||
e4600702 RK |
4878 | struct table_elt *const_elt |
4879 | = lookup (src_const, HASH (src_const, wider_mode), wider_mode); | |
4880 | ||
4881 | if (const_elt == 0) | |
4882 | continue; | |
4883 | ||
4884 | for (const_elt = const_elt->first_same_value; | |
4885 | const_elt; const_elt = const_elt->next_same_value) | |
f8cfc6aa | 4886 | if (REG_P (const_elt->exp)) |
e4600702 | 4887 | { |
b4206259 | 4888 | src_related = gen_lowpart (int_mode, const_elt->exp); |
e4600702 RK |
4889 | break; |
4890 | } | |
c94843d2 RS |
4891 | |
4892 | if (src_related != 0) | |
4893 | break; | |
e4600702 RK |
4894 | } |
4895 | } | |
4896 | ||
d45cf215 RS |
4897 | /* Another possibility is that we have an AND with a constant in |
4898 | a mode narrower than a word. If so, it might have been generated | |
4899 | as part of an "if" which would narrow the AND. If we already | |
4900 | have done the AND in a wider mode, we can use a SUBREG of that | |
4901 | value. */ | |
4902 | ||
4903 | if (flag_expensive_optimizations && ! src_related | |
54651377 | 4904 | && is_a <scalar_int_mode> (mode, &int_mode) |
481683e1 | 4905 | && GET_CODE (src) == AND && CONST_INT_P (XEXP (src, 1)) |
54651377 | 4906 | && GET_MODE_SIZE (int_mode) < UNITS_PER_WORD) |
d45cf215 | 4907 | { |
59b51186 | 4908 | opt_scalar_int_mode tmode_iter; |
38a448ca | 4909 | rtx new_and = gen_rtx_AND (VOIDmode, NULL_RTX, XEXP (src, 1)); |
d45cf215 | 4910 | |
59b51186 | 4911 | FOR_EACH_WIDER_MODE (tmode_iter, int_mode) |
d45cf215 | 4912 | { |
59b51186 | 4913 | scalar_int_mode tmode = tmode_iter.require (); |
c94843d2 RS |
4914 | if (GET_MODE_SIZE (tmode) > UNITS_PER_WORD) |
4915 | break; | |
4916 | ||
4de249d9 | 4917 | rtx inner = gen_lowpart (tmode, XEXP (src, 0)); |
d45cf215 RS |
4918 | struct table_elt *larger_elt; |
4919 | ||
4920 | if (inner) | |
4921 | { | |
4922 | PUT_MODE (new_and, tmode); | |
4923 | XEXP (new_and, 0) = inner; | |
4924 | larger_elt = lookup (new_and, HASH (new_and, tmode), tmode); | |
4925 | if (larger_elt == 0) | |
4926 | continue; | |
4927 | ||
4928 | for (larger_elt = larger_elt->first_same_value; | |
4929 | larger_elt; larger_elt = larger_elt->next_same_value) | |
f8cfc6aa | 4930 | if (REG_P (larger_elt->exp)) |
d45cf215 RS |
4931 | { |
4932 | src_related | |
54651377 | 4933 | = gen_lowpart (int_mode, larger_elt->exp); |
d45cf215 RS |
4934 | break; |
4935 | } | |
4936 | ||
4937 | if (src_related) | |
4938 | break; | |
4939 | } | |
4940 | } | |
4941 | } | |
7bac1be0 | 4942 | |
7bac1be0 RK |
4943 | /* See if a MEM has already been loaded with a widening operation; |
4944 | if it has, we can use a subreg of that. Many CISC machines | |
4945 | also have such operations, but this is only likely to be | |
71cc389b | 4946 | beneficial on these machines. */ |
278a83b2 | 4947 | |
3712c7a3 | 4948 | rtx_code extend_op; |
ddc356e8 | 4949 | if (flag_expensive_optimizations && src_related == 0 |
3c0cb5de | 4950 | && MEM_P (src) && ! do_not_record |
095a49c8 RS |
4951 | && is_a <scalar_int_mode> (mode, &int_mode) |
4952 | && (extend_op = load_extend_op (int_mode)) != UNKNOWN) | |
7bac1be0 | 4953 | { |
9d80ef7c RH |
4954 | struct rtx_def memory_extend_buf; |
4955 | rtx memory_extend_rtx = &memory_extend_buf; | |
278a83b2 | 4956 | |
7bac1be0 RK |
4957 | /* Set what we are trying to extend and the operation it might |
4958 | have been extended with. */ | |
c3284718 | 4959 | memset (memory_extend_rtx, 0, sizeof (*memory_extend_rtx)); |
3712c7a3 | 4960 | PUT_CODE (memory_extend_rtx, extend_op); |
7bac1be0 | 4961 | XEXP (memory_extend_rtx, 0) = src; |
278a83b2 | 4962 | |
59b51186 RS |
4963 | opt_scalar_int_mode tmode_iter; |
4964 | FOR_EACH_WIDER_MODE (tmode_iter, int_mode) | |
7bac1be0 RK |
4965 | { |
4966 | struct table_elt *larger_elt; | |
278a83b2 | 4967 | |
59b51186 | 4968 | scalar_int_mode tmode = tmode_iter.require (); |
c94843d2 RS |
4969 | if (GET_MODE_SIZE (tmode) > UNITS_PER_WORD) |
4970 | break; | |
4971 | ||
7bac1be0 | 4972 | PUT_MODE (memory_extend_rtx, tmode); |
278a83b2 | 4973 | larger_elt = lookup (memory_extend_rtx, |
7bac1be0 RK |
4974 | HASH (memory_extend_rtx, tmode), tmode); |
4975 | if (larger_elt == 0) | |
4976 | continue; | |
278a83b2 | 4977 | |
7bac1be0 RK |
4978 | for (larger_elt = larger_elt->first_same_value; |
4979 | larger_elt; larger_elt = larger_elt->next_same_value) | |
f8cfc6aa | 4980 | if (REG_P (larger_elt->exp)) |
7bac1be0 | 4981 | { |
095a49c8 | 4982 | src_related = gen_lowpart (int_mode, larger_elt->exp); |
7bac1be0 RK |
4983 | break; |
4984 | } | |
278a83b2 | 4985 | |
7bac1be0 RK |
4986 | if (src_related) |
4987 | break; | |
4988 | } | |
4989 | } | |
278a83b2 | 4990 | |
2c5bfdf7 AN |
4991 | /* Try to express the constant using a register+offset expression |
4992 | derived from a constant anchor. */ | |
4993 | ||
4994 | if (targetm.const_anchor | |
4995 | && !src_related | |
4996 | && src_const | |
4997 | && GET_CODE (src_const) == CONST_INT) | |
4998 | { | |
4999 | src_related = try_const_anchors (src_const, mode); | |
5000 | src_related_is_const_anchor = src_related != NULL_RTX; | |
5001 | } | |
5002 | ||
68b48f3f TC |
5003 | /* Try to re-materialize a vec_dup with an existing constant. */ |
5004 | rtx src_elt; | |
5005 | if ((!src_eqv_here || CONSTANT_P (src_eqv_here)) | |
5006 | && const_vec_duplicate_p (src, &src_elt)) | |
5007 | { | |
5008 | machine_mode const_mode = GET_MODE_INNER (GET_MODE (src)); | |
5009 | struct table_elt *related_elt | |
5010 | = lookup (src_elt, HASH (src_elt, const_mode), const_mode); | |
5011 | if (related_elt) | |
5012 | { | |
5013 | for (related_elt = related_elt->first_same_value; | |
5014 | related_elt; related_elt = related_elt->next_same_value) | |
5015 | if (REG_P (related_elt->exp)) | |
5016 | { | |
5017 | /* We don't need to compare costs with an existing (constant) | |
5018 | src_eqv_here, since any such src_eqv_here should already be | |
5019 | available in src_const. */ | |
5020 | src_eqv_here | |
5021 | = gen_rtx_VEC_DUPLICATE (GET_MODE (src), | |
5022 | related_elt->exp); | |
5023 | break; | |
5024 | } | |
5025 | } | |
5026 | } | |
2c5bfdf7 | 5027 | |
7afe21cc | 5028 | if (src == src_folded) |
278a83b2 | 5029 | src_folded = 0; |
7afe21cc | 5030 | |
da7d8304 | 5031 | /* At this point, ELT, if nonzero, points to a class of expressions |
7afe21cc | 5032 | equivalent to the source of this SET and SRC, SRC_EQV, SRC_FOLDED, |
da7d8304 | 5033 | and SRC_RELATED, if nonzero, each contain additional equivalent |
7afe21cc RK |
5034 | expressions. Prune these latter expressions by deleting expressions |
5035 | already in the equivalence class. | |
5036 | ||
5037 | Check for an equivalent identical to the destination. If found, | |
5038 | this is the preferred equivalent since it will likely lead to | |
5039 | elimination of the insn. Indicate this by placing it in | |
5040 | `src_related'. */ | |
5041 | ||
278a83b2 KH |
5042 | if (elt) |
5043 | elt = elt->first_same_value; | |
7afe21cc | 5044 | for (p = elt; p; p = p->next_same_value) |
278a83b2 | 5045 | { |
7afe21cc RK |
5046 | enum rtx_code code = GET_CODE (p->exp); |
5047 | ||
5048 | /* If the expression is not valid, ignore it. Then we do not | |
5049 | have to check for validity below. In most cases, we can use | |
5050 | `rtx_equal_p', since canonicalization has already been done. */ | |
0516f6fe | 5051 | if (code != REG && ! exp_equiv_p (p->exp, p->exp, 1, false)) |
7afe21cc RK |
5052 | continue; |
5053 | ||
5a03c8c4 RK |
5054 | /* Also skip paradoxical subregs, unless that's what we're |
5055 | looking for. */ | |
6a4bdc79 | 5056 | if (paradoxical_subreg_p (p->exp) |
5a03c8c4 RK |
5057 | && ! (src != 0 |
5058 | && GET_CODE (src) == SUBREG | |
5059 | && GET_MODE (src) == GET_MODE (p->exp) | |
bd4288c0 RS |
5060 | && partial_subreg_p (GET_MODE (SUBREG_REG (src)), |
5061 | GET_MODE (SUBREG_REG (p->exp))))) | |
5a03c8c4 RK |
5062 | continue; |
5063 | ||
278a83b2 | 5064 | if (src && GET_CODE (src) == code && rtx_equal_p (src, p->exp)) |
7afe21cc | 5065 | src = 0; |
278a83b2 | 5066 | else if (src_folded && GET_CODE (src_folded) == code |
7afe21cc RK |
5067 | && rtx_equal_p (src_folded, p->exp)) |
5068 | src_folded = 0; | |
278a83b2 | 5069 | else if (src_eqv_here && GET_CODE (src_eqv_here) == code |
7afe21cc RK |
5070 | && rtx_equal_p (src_eqv_here, p->exp)) |
5071 | src_eqv_here = 0; | |
278a83b2 | 5072 | else if (src_related && GET_CODE (src_related) == code |
7afe21cc RK |
5073 | && rtx_equal_p (src_related, p->exp)) |
5074 | src_related = 0; | |
5075 | ||
5076 | /* This is the same as the destination of the insns, we want | |
2961db43 RB |
5077 | to prefer it. The code below will then give it a negative |
5078 | cost. */ | |
5079 | if (!dest_related | |
5080 | && GET_CODE (dest) == code && rtx_equal_p (p->exp, dest)) | |
5081 | dest_related = p->exp; | |
278a83b2 | 5082 | } |
7afe21cc RK |
5083 | |
5084 | /* Find the cheapest valid equivalent, trying all the available | |
5085 | possibilities. Prefer items not in the hash table to ones | |
5086 | that are when they are equal cost. Note that we can never | |
5087 | worsen an insn as the current contents will also succeed. | |
05c33dd8 | 5088 | If we find an equivalent identical to the destination, use it as best, |
0f41302f | 5089 | since this insn will probably be eliminated in that case. */ |
7afe21cc RK |
5090 | if (src) |
5091 | { | |
5092 | if (rtx_equal_p (src, dest)) | |
f1c1dfc3 | 5093 | src_cost = src_regcost = -1; |
7afe21cc | 5094 | else |
630c79be | 5095 | { |
e548c9df | 5096 | src_cost = COST (src, mode); |
630c79be BS |
5097 | src_regcost = approx_reg_cost (src); |
5098 | } | |
7afe21cc RK |
5099 | } |
5100 | ||
5101 | if (src_eqv_here) | |
5102 | { | |
5103 | if (rtx_equal_p (src_eqv_here, dest)) | |
f1c1dfc3 | 5104 | src_eqv_cost = src_eqv_regcost = -1; |
7afe21cc | 5105 | else |
630c79be | 5106 | { |
e548c9df | 5107 | src_eqv_cost = COST (src_eqv_here, mode); |
630c79be BS |
5108 | src_eqv_regcost = approx_reg_cost (src_eqv_here); |
5109 | } | |
7afe21cc RK |
5110 | } |
5111 | ||
5112 | if (src_folded) | |
5113 | { | |
5114 | if (rtx_equal_p (src_folded, dest)) | |
f1c1dfc3 | 5115 | src_folded_cost = src_folded_regcost = -1; |
7afe21cc | 5116 | else |
630c79be | 5117 | { |
e548c9df | 5118 | src_folded_cost = COST (src_folded, mode); |
630c79be BS |
5119 | src_folded_regcost = approx_reg_cost (src_folded); |
5120 | } | |
7afe21cc RK |
5121 | } |
5122 | ||
2961db43 | 5123 | if (dest_related) |
7afe21cc | 5124 | { |
2961db43 RB |
5125 | src_related_cost = src_related_regcost = -1; |
5126 | /* Handle it as src_related. */ | |
5127 | src_related = dest_related; | |
5128 | } | |
5129 | else if (src_related) | |
5130 | { | |
5131 | src_related_cost = COST (src_related, mode); | |
5132 | src_related_regcost = approx_reg_cost (src_related); | |
5133 | ||
5134 | /* If a const-anchor is used to synthesize a constant that | |
5135 | normally requires multiple instructions then slightly prefer | |
5136 | it over the original sequence. These instructions are likely | |
5137 | to become redundant now. We can't compare against the cost | |
5138 | of src_eqv_here because, on MIPS for example, multi-insn | |
5139 | constants have zero cost; they are assumed to be hoisted from | |
5140 | loops. */ | |
5141 | if (src_related_is_const_anchor | |
5142 | && src_related_cost == src_cost | |
5143 | && src_eqv_here) | |
5144 | src_related_cost--; | |
7afe21cc RK |
5145 | } |
5146 | ||
5147 | /* If this was an indirect jump insn, a known label will really be | |
5148 | cheaper even though it looks more expensive. */ | |
5149 | if (dest == pc_rtx && src_const && GET_CODE (src_const) == LABEL_REF) | |
99a9c946 | 5150 | src_folded = src_const, src_folded_cost = src_folded_regcost = -1; |
278a83b2 | 5151 | |
7afe21cc RK |
5152 | /* Terminate loop when replacement made. This must terminate since |
5153 | the current contents will be tested and will always be valid. */ | |
5154 | while (1) | |
278a83b2 KH |
5155 | { |
5156 | rtx trial; | |
7afe21cc | 5157 | |
278a83b2 | 5158 | /* Skip invalid entries. */ |
f8cfc6aa | 5159 | while (elt && !REG_P (elt->exp) |
0516f6fe | 5160 | && ! exp_equiv_p (elt->exp, elt->exp, 1, false)) |
278a83b2 | 5161 | elt = elt->next_same_value; |
5a03c8c4 RK |
5162 | |
5163 | /* A paradoxical subreg would be bad here: it'll be the right | |
5164 | size, but later may be adjusted so that the upper bits aren't | |
5165 | what we want. So reject it. */ | |
5166 | if (elt != 0 | |
6a4bdc79 | 5167 | && paradoxical_subreg_p (elt->exp) |
5a03c8c4 RK |
5168 | /* It is okay, though, if the rtx we're trying to match |
5169 | will ignore any of the bits we can't predict. */ | |
5170 | && ! (src != 0 | |
5171 | && GET_CODE (src) == SUBREG | |
5172 | && GET_MODE (src) == GET_MODE (elt->exp) | |
bd4288c0 RS |
5173 | && partial_subreg_p (GET_MODE (SUBREG_REG (src)), |
5174 | GET_MODE (SUBREG_REG (elt->exp))))) | |
5a03c8c4 RK |
5175 | { |
5176 | elt = elt->next_same_value; | |
5177 | continue; | |
5178 | } | |
278a83b2 | 5179 | |
68252e27 | 5180 | if (elt) |
630c79be BS |
5181 | { |
5182 | src_elt_cost = elt->cost; | |
5183 | src_elt_regcost = elt->regcost; | |
5184 | } | |
7afe21cc | 5185 | |
68252e27 | 5186 | /* Find cheapest and skip it for the next time. For items |
7afe21cc RK |
5187 | of equal cost, use this order: |
5188 | src_folded, src, src_eqv, src_related and hash table entry. */ | |
99a9c946 | 5189 | if (src_folded |
56ae04af KH |
5190 | && preferable (src_folded_cost, src_folded_regcost, |
5191 | src_cost, src_regcost) <= 0 | |
5192 | && preferable (src_folded_cost, src_folded_regcost, | |
5193 | src_eqv_cost, src_eqv_regcost) <= 0 | |
5194 | && preferable (src_folded_cost, src_folded_regcost, | |
5195 | src_related_cost, src_related_regcost) <= 0 | |
5196 | && preferable (src_folded_cost, src_folded_regcost, | |
5197 | src_elt_cost, src_elt_regcost) <= 0) | |
247c407c | 5198 | trial = src_folded, src_folded_cost = MAX_COST; |
99a9c946 | 5199 | else if (src |
56ae04af KH |
5200 | && preferable (src_cost, src_regcost, |
5201 | src_eqv_cost, src_eqv_regcost) <= 0 | |
5202 | && preferable (src_cost, src_regcost, | |
5203 | src_related_cost, src_related_regcost) <= 0 | |
5204 | && preferable (src_cost, src_regcost, | |
5205 | src_elt_cost, src_elt_regcost) <= 0) | |
f1c1dfc3 | 5206 | trial = src, src_cost = MAX_COST; |
99a9c946 | 5207 | else if (src_eqv_here |
56ae04af KH |
5208 | && preferable (src_eqv_cost, src_eqv_regcost, |
5209 | src_related_cost, src_related_regcost) <= 0 | |
5210 | && preferable (src_eqv_cost, src_eqv_regcost, | |
5211 | src_elt_cost, src_elt_regcost) <= 0) | |
a36b8a1e | 5212 | trial = src_eqv_here, src_eqv_cost = MAX_COST; |
99a9c946 | 5213 | else if (src_related |
56ae04af KH |
5214 | && preferable (src_related_cost, src_related_regcost, |
5215 | src_elt_cost, src_elt_regcost) <= 0) | |
a36b8a1e | 5216 | trial = src_related, src_related_cost = MAX_COST; |
278a83b2 | 5217 | else |
7afe21cc | 5218 | { |
a36b8a1e | 5219 | trial = elt->exp; |
7afe21cc | 5220 | elt = elt->next_same_value; |
f1c1dfc3 | 5221 | src_elt_cost = MAX_COST; |
7afe21cc RK |
5222 | } |
5223 | ||
b4ab701f JJ |
5224 | /* Try to optimize |
5225 | (set (reg:M N) (const_int A)) | |
5226 | (set (reg:M2 O) (const_int B)) | |
5227 | (set (zero_extract:M2 (reg:M N) (const_int C) (const_int D)) | |
5228 | (reg:M2 O)). */ | |
5229 | if (GET_CODE (SET_DEST (sets[i].rtl)) == ZERO_EXTRACT | |
5230 | && CONST_INT_P (trial) | |
5231 | && CONST_INT_P (XEXP (SET_DEST (sets[i].rtl), 1)) | |
5232 | && CONST_INT_P (XEXP (SET_DEST (sets[i].rtl), 2)) | |
5233 | && REG_P (XEXP (SET_DEST (sets[i].rtl), 0)) | |
bb94ec76 RS |
5234 | && (known_ge |
5235 | (GET_MODE_PRECISION (GET_MODE (SET_DEST (sets[i].rtl))), | |
5236 | INTVAL (XEXP (SET_DEST (sets[i].rtl), 1)))) | |
b4ab701f JJ |
5237 | && ((unsigned) INTVAL (XEXP (SET_DEST (sets[i].rtl), 1)) |
5238 | + (unsigned) INTVAL (XEXP (SET_DEST (sets[i].rtl), 2)) | |
5239 | <= HOST_BITS_PER_WIDE_INT)) | |
5240 | { | |
5241 | rtx dest_reg = XEXP (SET_DEST (sets[i].rtl), 0); | |
5242 | rtx width = XEXP (SET_DEST (sets[i].rtl), 1); | |
5243 | rtx pos = XEXP (SET_DEST (sets[i].rtl), 2); | |
5244 | unsigned int dest_hash = HASH (dest_reg, GET_MODE (dest_reg)); | |
5245 | struct table_elt *dest_elt | |
5246 | = lookup (dest_reg, dest_hash, GET_MODE (dest_reg)); | |
5247 | rtx dest_cst = NULL; | |
5248 | ||
5249 | if (dest_elt) | |
5250 | for (p = dest_elt->first_same_value; p; p = p->next_same_value) | |
5251 | if (p->is_const && CONST_INT_P (p->exp)) | |
5252 | { | |
5253 | dest_cst = p->exp; | |
5254 | break; | |
5255 | } | |
5256 | if (dest_cst) | |
5257 | { | |
5258 | HOST_WIDE_INT val = INTVAL (dest_cst); | |
5259 | HOST_WIDE_INT mask; | |
5260 | unsigned int shift; | |
c7ad039d RS |
5261 | /* This is the mode of DEST_CST as well. */ |
5262 | scalar_int_mode dest_mode | |
5263 | = as_a <scalar_int_mode> (GET_MODE (dest_reg)); | |
b4ab701f | 5264 | if (BITS_BIG_ENDIAN) |
c7ad039d | 5265 | shift = GET_MODE_PRECISION (dest_mode) |
b4ab701f JJ |
5266 | - INTVAL (pos) - INTVAL (width); |
5267 | else | |
5268 | shift = INTVAL (pos); | |
5269 | if (INTVAL (width) == HOST_BITS_PER_WIDE_INT) | |
dd4786fe | 5270 | mask = HOST_WIDE_INT_M1; |
b4ab701f | 5271 | else |
fecfbfa4 | 5272 | mask = (HOST_WIDE_INT_1 << INTVAL (width)) - 1; |
b4ab701f JJ |
5273 | val &= ~(mask << shift); |
5274 | val |= (INTVAL (trial) & mask) << shift; | |
c7ad039d | 5275 | val = trunc_int_for_mode (val, dest_mode); |
b4ab701f JJ |
5276 | validate_unshare_change (insn, &SET_DEST (sets[i].rtl), |
5277 | dest_reg, 1); | |
5278 | validate_unshare_change (insn, &SET_SRC (sets[i].rtl), | |
5279 | GEN_INT (val), 1); | |
5280 | if (apply_change_group ()) | |
5281 | { | |
5282 | rtx note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
5283 | if (note) | |
5284 | { | |
5285 | remove_note (insn, note); | |
5286 | df_notes_rescan (insn); | |
5287 | } | |
5288 | src_eqv = NULL_RTX; | |
5289 | src_eqv_elt = NULL; | |
5290 | src_eqv_volatile = 0; | |
5291 | src_eqv_in_memory = 0; | |
5292 | src_eqv_hash = 0; | |
5293 | repeat = true; | |
5294 | break; | |
5295 | } | |
5296 | } | |
5297 | } | |
5298 | ||
7afe21cc RK |
5299 | /* We don't normally have an insn matching (set (pc) (pc)), so |
5300 | check for this separately here. We will delete such an | |
5301 | insn below. | |
5302 | ||
d466c016 JL |
5303 | For other cases such as a table jump or conditional jump |
5304 | where we know the ultimate target, go ahead and replace the | |
5305 | operand. While that may not make a valid insn, we will | |
5306 | reemit the jump below (and also insert any necessary | |
5307 | barriers). */ | |
7afe21cc RK |
5308 | if (n_sets == 1 && dest == pc_rtx |
5309 | && (trial == pc_rtx | |
5310 | || (GET_CODE (trial) == LABEL_REF | |
5311 | && ! condjump_p (insn)))) | |
5312 | { | |
2f39b6ca UW |
5313 | /* Don't substitute non-local labels, this confuses CFG. */ |
5314 | if (GET_CODE (trial) == LABEL_REF | |
5315 | && LABEL_REF_NONLOCAL_P (trial)) | |
5316 | continue; | |
5317 | ||
d466c016 | 5318 | SET_SRC (sets[i].rtl) = trial; |
2aac3a01 | 5319 | cse_jumps_altered = true; |
7afe21cc RK |
5320 | break; |
5321 | } | |
278a83b2 | 5322 | |
dd77684f | 5323 | /* Similarly, lots of targets don't allow no-op |
4aded535 RS |
5324 | (set (mem x) (mem x)) moves. Even (set (reg x) (reg x)) |
5325 | might be impossible for certain registers (like CC registers). */ | |
dd77684f | 5326 | else if (n_sets == 1 |
4aded535 RS |
5327 | && !CALL_P (insn) |
5328 | && (MEM_P (trial) || REG_P (trial)) | |
dd77684f JJ |
5329 | && rtx_equal_p (trial, dest) |
5330 | && !side_effects_p (dest) | |
5331 | && (cfun->can_delete_dead_exceptions | |
dd9ca9d7 RB |
5332 | || insn_nothrow_p (insn)) |
5333 | /* We can only remove the later store if the earlier aliases | |
5334 | at least all accesses the later one. */ | |
5335 | && (!MEM_P (trial) | |
5336 | || ((MEM_ALIAS_SET (dest) == MEM_ALIAS_SET (trial) | |
5337 | || alias_set_subset_of (MEM_ALIAS_SET (dest), | |
5338 | MEM_ALIAS_SET (trial))) | |
5339 | && (!MEM_EXPR (trial) | |
5340 | || refs_same_for_tbaa_p (MEM_EXPR (trial), | |
5341 | MEM_EXPR (dest)))))) | |
dd77684f JJ |
5342 | { |
5343 | SET_SRC (sets[i].rtl) = trial; | |
4aded535 | 5344 | noop_insn = true; |
dd77684f JJ |
5345 | break; |
5346 | } | |
5347 | ||
1ef6855c KH |
5348 | /* Reject certain invalid forms of CONST that we create. */ |
5349 | else if (CONSTANT_P (trial) | |
5350 | && GET_CODE (trial) == CONST | |
5351 | /* Reject cases that will cause decode_rtx_const to | |
5352 | die. On the alpha when simplifying a switch, we | |
5353 | get (const (truncate (minus (label_ref) | |
5354 | (label_ref)))). */ | |
5355 | && (GET_CODE (XEXP (trial, 0)) == TRUNCATE | |
5356 | /* Likewise on IA-64, except without the | |
5357 | truncate. */ | |
5358 | || (GET_CODE (XEXP (trial, 0)) == MINUS | |
5359 | && GET_CODE (XEXP (XEXP (trial, 0), 0)) == LABEL_REF | |
5360 | && GET_CODE (XEXP (XEXP (trial, 0), 1)) == LABEL_REF))) | |
5361 | /* Do nothing for this case. */ | |
5362 | ; | |
5363 | ||
23741374 BE |
5364 | /* Do not replace anything with a MEM, except the replacement |
5365 | is a no-op. This allows this loop to terminate. */ | |
5366 | else if (MEM_P (trial) && !rtx_equal_p (trial, SET_SRC(sets[i].rtl))) | |
5367 | /* Do nothing for this case. */ | |
5368 | ; | |
5369 | ||
7afe21cc | 5370 | /* Look for a substitution that makes a valid insn. */ |
6c4d60f8 JJ |
5371 | else if (validate_unshare_change (insn, &SET_SRC (sets[i].rtl), |
5372 | trial, 0)) | |
05c33dd8 | 5373 | { |
32e9fa48 | 5374 | rtx new_rtx = canon_reg (SET_SRC (sets[i].rtl), insn); |
dbaff908 | 5375 | |
7722328e RK |
5376 | /* The result of apply_change_group can be ignored; see |
5377 | canon_reg. */ | |
5378 | ||
32e9fa48 | 5379 | validate_change (insn, &SET_SRC (sets[i].rtl), new_rtx, 1); |
6702af89 | 5380 | apply_change_group (); |
932ad4d9 | 5381 | |
05c33dd8 RK |
5382 | break; |
5383 | } | |
7afe21cc | 5384 | |
247c407c RS |
5385 | /* If the current function uses a constant pool and this is a |
5386 | constant, try making a pool entry. Put it in src_folded | |
5387 | unless we already have done this since that is where it | |
5388 | likely came from. */ | |
7afe21cc | 5389 | |
247c407c | 5390 | else if (crtl->uses_const_pool |
7afe21cc | 5391 | && CONSTANT_P (trial) |
247c407c RS |
5392 | && !CONST_INT_P (trial) |
5393 | && (src_folded == 0 || !MEM_P (src_folded)) | |
9ae8ffe7 JL |
5394 | && GET_MODE_CLASS (mode) != MODE_CC |
5395 | && mode != VOIDmode) | |
7afe21cc | 5396 | { |
247c407c RS |
5397 | src_folded = force_const_mem (mode, trial); |
5398 | if (src_folded) | |
5399 | { | |
5400 | src_folded_cost = COST (src_folded, mode); | |
5401 | src_folded_regcost = approx_reg_cost (src_folded); | |
5402 | } | |
7afe21cc | 5403 | } |
278a83b2 | 5404 | } |
7afe21cc | 5405 | |
b4ab701f JJ |
5406 | /* If we changed the insn too much, handle this set from scratch. */ |
5407 | if (repeat) | |
5408 | { | |
5409 | i--; | |
5410 | continue; | |
5411 | } | |
5412 | ||
7afe21cc RK |
5413 | src = SET_SRC (sets[i].rtl); |
5414 | ||
5415 | /* In general, it is good to have a SET with SET_SRC == SET_DEST. | |
5416 | However, there is an important exception: If both are registers | |
5417 | that are not the head of their equivalence class, replace SET_SRC | |
5418 | with the head of the class. If we do not do this, we will have | |
5419 | both registers live over a portion of the basic block. This way, | |
5420 | their lifetimes will likely abut instead of overlapping. */ | |
f8cfc6aa | 5421 | if (REG_P (dest) |
1bb98cec | 5422 | && REGNO_QTY_VALID_P (REGNO (dest))) |
7afe21cc | 5423 | { |
1bb98cec DM |
5424 | int dest_q = REG_QTY (REGNO (dest)); |
5425 | struct qty_table_elem *dest_ent = &qty_table[dest_q]; | |
5426 | ||
5427 | if (dest_ent->mode == GET_MODE (dest) | |
5428 | && dest_ent->first_reg != REGNO (dest) | |
f8cfc6aa | 5429 | && REG_P (src) && REGNO (src) == REGNO (dest) |
1bb98cec DM |
5430 | /* Don't do this if the original insn had a hard reg as |
5431 | SET_SRC or SET_DEST. */ | |
f8cfc6aa | 5432 | && (!REG_P (sets[i].src) |
1bb98cec | 5433 | || REGNO (sets[i].src) >= FIRST_PSEUDO_REGISTER) |
f8cfc6aa | 5434 | && (!REG_P (dest) || REGNO (dest) >= FIRST_PSEUDO_REGISTER)) |
1bb98cec DM |
5435 | /* We can't call canon_reg here because it won't do anything if |
5436 | SRC is a hard register. */ | |
759bd8b7 | 5437 | { |
1bb98cec DM |
5438 | int src_q = REG_QTY (REGNO (src)); |
5439 | struct qty_table_elem *src_ent = &qty_table[src_q]; | |
5440 | int first = src_ent->first_reg; | |
5441 | rtx new_src | |
5442 | = (first >= FIRST_PSEUDO_REGISTER | |
5443 | ? regno_reg_rtx[first] : gen_rtx_REG (GET_MODE (src), first)); | |
5444 | ||
5445 | /* We must use validate-change even for this, because this | |
5446 | might be a special no-op instruction, suitable only to | |
5447 | tag notes onto. */ | |
5448 | if (validate_change (insn, &SET_SRC (sets[i].rtl), new_src, 0)) | |
5449 | { | |
5450 | src = new_src; | |
5451 | /* If we had a constant that is cheaper than what we are now | |
5452 | setting SRC to, use that constant. We ignored it when we | |
5453 | thought we could make this into a no-op. */ | |
e548c9df | 5454 | if (src_const && COST (src_const, mode) < COST (src, mode) |
278a83b2 KH |
5455 | && validate_change (insn, &SET_SRC (sets[i].rtl), |
5456 | src_const, 0)) | |
1bb98cec DM |
5457 | src = src_const; |
5458 | } | |
759bd8b7 | 5459 | } |
7afe21cc RK |
5460 | } |
5461 | ||
5462 | /* If we made a change, recompute SRC values. */ | |
5463 | if (src != sets[i].src) | |
278a83b2 | 5464 | { |
278a83b2 KH |
5465 | do_not_record = 0; |
5466 | hash_arg_in_memory = 0; | |
7afe21cc | 5467 | sets[i].src = src; |
278a83b2 KH |
5468 | sets[i].src_hash = HASH (src, mode); |
5469 | sets[i].src_volatile = do_not_record; | |
5470 | sets[i].src_in_memory = hash_arg_in_memory; | |
5471 | sets[i].src_elt = lookup (src, sets[i].src_hash, mode); | |
5472 | } | |
7afe21cc RK |
5473 | |
5474 | /* If this is a single SET, we are setting a register, and we have an | |
73dd3123 EB |
5475 | equivalent constant, we want to add a REG_EQUAL note if the constant |
5476 | is different from the source. We don't want to do it for a constant | |
5477 | pseudo since verifying that this pseudo hasn't been eliminated is a | |
5478 | pain; moreover such a note won't help anything. | |
ac7ef8d5 FS |
5479 | |
5480 | Avoid a REG_EQUAL note for (CONST (MINUS (LABEL_REF) (LABEL_REF))) | |
5481 | which can be created for a reference to a compile time computable | |
5482 | entry in a jump table. */ | |
73dd3123 EB |
5483 | if (n_sets == 1 |
5484 | && REG_P (dest) | |
5485 | && src_const | |
f8cfc6aa | 5486 | && !REG_P (src_const) |
73dd3123 EB |
5487 | && !(GET_CODE (src_const) == SUBREG |
5488 | && REG_P (SUBREG_REG (src_const))) | |
5489 | && !(GET_CODE (src_const) == CONST | |
5490 | && GET_CODE (XEXP (src_const, 0)) == MINUS | |
5491 | && GET_CODE (XEXP (XEXP (src_const, 0), 0)) == LABEL_REF | |
5492 | && GET_CODE (XEXP (XEXP (src_const, 0), 1)) == LABEL_REF) | |
5493 | && !rtx_equal_p (src, src_const)) | |
7afe21cc | 5494 | { |
73dd3123 EB |
5495 | /* Make sure that the rtx is not shared. */ |
5496 | src_const = copy_rtx (src_const); | |
51e2a951 | 5497 | |
73dd3123 EB |
5498 | /* Record the actual constant value in a REG_EQUAL note, |
5499 | making a new one if one does not already exist. */ | |
5500 | set_unique_reg_note (insn, REG_EQUAL, src_const); | |
5501 | df_notes_rescan (insn); | |
7afe21cc RK |
5502 | } |
5503 | ||
5504 | /* Now deal with the destination. */ | |
5505 | do_not_record = 0; | |
7afe21cc | 5506 | |
46d096a3 SB |
5507 | /* Look within any ZERO_EXTRACT to the MEM or REG within it. */ |
5508 | while (GET_CODE (dest) == SUBREG | |
7afe21cc | 5509 | || GET_CODE (dest) == ZERO_EXTRACT |
7afe21cc | 5510 | || GET_CODE (dest) == STRICT_LOW_PART) |
0339ce7e | 5511 | dest = XEXP (dest, 0); |
7afe21cc RK |
5512 | |
5513 | sets[i].inner_dest = dest; | |
5514 | ||
3c0cb5de | 5515 | if (MEM_P (dest)) |
7afe21cc | 5516 | { |
9ae8ffe7 JL |
5517 | #ifdef PUSH_ROUNDING |
5518 | /* Stack pushes invalidate the stack pointer. */ | |
5519 | rtx addr = XEXP (dest, 0); | |
ec8e098d | 5520 | if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC |
9ae8ffe7 | 5521 | && XEXP (addr, 0) == stack_pointer_rtx) |
524e3576 | 5522 | invalidate (stack_pointer_rtx, VOIDmode); |
9ae8ffe7 | 5523 | #endif |
7afe21cc | 5524 | dest = fold_rtx (dest, insn); |
7afe21cc RK |
5525 | } |
5526 | ||
5527 | /* Compute the hash code of the destination now, | |
5528 | before the effects of this instruction are recorded, | |
5529 | since the register values used in the address computation | |
5530 | are those before this instruction. */ | |
2197a88a | 5531 | sets[i].dest_hash = HASH (dest, mode); |
7afe21cc RK |
5532 | |
5533 | /* Don't enter a bit-field in the hash table | |
5534 | because the value in it after the store | |
5535 | may not equal what was stored, due to truncation. */ | |
5536 | ||
46d096a3 | 5537 | if (GET_CODE (SET_DEST (sets[i].rtl)) == ZERO_EXTRACT) |
7afe21cc RK |
5538 | { |
5539 | rtx width = XEXP (SET_DEST (sets[i].rtl), 1); | |
5540 | ||
481683e1 SZ |
5541 | if (src_const != 0 && CONST_INT_P (src_const) |
5542 | && CONST_INT_P (width) | |
906c4e36 RK |
5543 | && INTVAL (width) < HOST_BITS_PER_WIDE_INT |
5544 | && ! (INTVAL (src_const) | |
0cadbfaa | 5545 | & (HOST_WIDE_INT_M1U << INTVAL (width)))) |
7afe21cc RK |
5546 | /* Exception: if the value is constant, |
5547 | and it won't be truncated, record it. */ | |
5548 | ; | |
5549 | else | |
5550 | { | |
5551 | /* This is chosen so that the destination will be invalidated | |
5552 | but no new value will be recorded. | |
5553 | We must invalidate because sometimes constant | |
5554 | values can be recorded for bitfields. */ | |
5555 | sets[i].src_elt = 0; | |
5556 | sets[i].src_volatile = 1; | |
5557 | src_eqv = 0; | |
5558 | src_eqv_elt = 0; | |
5559 | } | |
5560 | } | |
5561 | ||
5562 | /* If only one set in a JUMP_INSN and it is now a no-op, we can delete | |
5563 | the insn. */ | |
5564 | else if (n_sets == 1 && dest == pc_rtx && src == pc_rtx) | |
5565 | { | |
ef178af3 | 5566 | /* One less use of the label this insn used to jump to. */ |
98ccd1d7 | 5567 | cse_cfg_altered |= delete_insn_and_edges (insn); |
2aac3a01 | 5568 | cse_jumps_altered = true; |
7afe21cc RK |
5569 | /* No more processing for this set. */ |
5570 | sets[i].rtl = 0; | |
5571 | } | |
5572 | ||
4aded535 RS |
5573 | /* Similarly for no-op moves. */ |
5574 | else if (noop_insn) | |
dd77684f JJ |
5575 | { |
5576 | if (cfun->can_throw_non_call_exceptions && can_throw_internal (insn)) | |
5577 | cse_cfg_altered = true; | |
98ccd1d7 | 5578 | cse_cfg_altered |= delete_insn_and_edges (insn); |
dd77684f JJ |
5579 | /* No more processing for this set. */ |
5580 | sets[i].rtl = 0; | |
5581 | } | |
5582 | ||
7afe21cc | 5583 | /* If this SET is now setting PC to a label, we know it used to |
d466c016 | 5584 | be a conditional or computed branch. */ |
8f235343 JH |
5585 | else if (dest == pc_rtx && GET_CODE (src) == LABEL_REF |
5586 | && !LABEL_REF_NONLOCAL_P (src)) | |
7afe21cc | 5587 | { |
d466c016 JL |
5588 | /* We reemit the jump in as many cases as possible just in |
5589 | case the form of an unconditional jump is significantly | |
5590 | different than a computed jump or conditional jump. | |
5591 | ||
5592 | If this insn has multiple sets, then reemitting the | |
5593 | jump is nontrivial. So instead we just force rerecognition | |
5594 | and hope for the best. */ | |
5595 | if (n_sets == 1) | |
7afe21cc | 5596 | { |
e67d1102 | 5597 | rtx_jump_insn *new_rtx; |
49506606 | 5598 | rtx note; |
8fb1e50e | 5599 | |
ec4a505f RS |
5600 | rtx_insn *seq = targetm.gen_jump (XEXP (src, 0)); |
5601 | new_rtx = emit_jump_insn_before (seq, insn); | |
32e9fa48 | 5602 | JUMP_LABEL (new_rtx) = XEXP (src, 0); |
7afe21cc | 5603 | LABEL_NUSES (XEXP (src, 0))++; |
9dcb4381 RH |
5604 | |
5605 | /* Make sure to copy over REG_NON_LOCAL_GOTO. */ | |
5606 | note = find_reg_note (insn, REG_NON_LOCAL_GOTO, 0); | |
5607 | if (note) | |
5608 | { | |
5609 | XEXP (note, 1) = NULL_RTX; | |
32e9fa48 | 5610 | REG_NOTES (new_rtx) = note; |
9dcb4381 RH |
5611 | } |
5612 | ||
98ccd1d7 | 5613 | cse_cfg_altered |= delete_insn_and_edges (insn); |
49506606 | 5614 | insn = new_rtx; |
7afe21cc | 5615 | } |
31dcf83f | 5616 | else |
31dcf83f | 5617 | INSN_CODE (insn) = -1; |
7afe21cc | 5618 | |
2aac3a01 EB |
5619 | /* Do not bother deleting any unreachable code, let jump do it. */ |
5620 | cse_jumps_altered = true; | |
7afe21cc RK |
5621 | sets[i].rtl = 0; |
5622 | } | |
5623 | ||
c2a47e48 RK |
5624 | /* If destination is volatile, invalidate it and then do no further |
5625 | processing for this assignment. */ | |
7afe21cc RK |
5626 | |
5627 | else if (do_not_record) | |
c2a47e48 | 5628 | { |
2a1d78d8 | 5629 | invalidate_dest (dest); |
c2a47e48 RK |
5630 | sets[i].rtl = 0; |
5631 | } | |
7afe21cc RK |
5632 | |
5633 | if (sets[i].rtl != 0 && dest != SET_DEST (sets[i].rtl)) | |
2a1d78d8 JJ |
5634 | { |
5635 | do_not_record = 0; | |
5636 | sets[i].dest_hash = HASH (SET_DEST (sets[i].rtl), mode); | |
5637 | if (do_not_record) | |
5638 | { | |
5639 | invalidate_dest (SET_DEST (sets[i].rtl)); | |
5640 | sets[i].rtl = 0; | |
5641 | } | |
5642 | } | |
7afe21cc RK |
5643 | } |
5644 | ||
5645 | /* Now enter all non-volatile source expressions in the hash table | |
5646 | if they are not already present. | |
5647 | Record their equivalence classes in src_elt. | |
5648 | This way we can insert the corresponding destinations into | |
5649 | the same classes even if the actual sources are no longer in them | |
5650 | (having been invalidated). */ | |
5651 | ||
5652 | if (src_eqv && src_eqv_elt == 0 && sets[0].rtl != 0 && ! src_eqv_volatile | |
5653 | && ! rtx_equal_p (src_eqv, SET_DEST (sets[0].rtl))) | |
5654 | { | |
b3694847 SS |
5655 | struct table_elt *elt; |
5656 | struct table_elt *classp = sets[0].src_elt; | |
7afe21cc | 5657 | rtx dest = SET_DEST (sets[0].rtl); |
ef4bddc2 | 5658 | machine_mode eqvmode = GET_MODE (dest); |
7afe21cc RK |
5659 | |
5660 | if (GET_CODE (dest) == STRICT_LOW_PART) | |
5661 | { | |
5662 | eqvmode = GET_MODE (SUBREG_REG (XEXP (dest, 0))); | |
5663 | classp = 0; | |
5664 | } | |
dec7aaab | 5665 | if (insert_regs (src_eqv, classp, false)) |
8ae2b8f6 JW |
5666 | { |
5667 | rehash_using_reg (src_eqv); | |
5668 | src_eqv_hash = HASH (src_eqv, eqvmode); | |
5669 | } | |
2197a88a | 5670 | elt = insert (src_eqv, classp, src_eqv_hash, eqvmode); |
7afe21cc | 5671 | elt->in_memory = src_eqv_in_memory; |
7afe21cc | 5672 | src_eqv_elt = elt; |
f7911249 JW |
5673 | |
5674 | /* Check to see if src_eqv_elt is the same as a set source which | |
5675 | does not yet have an elt, and if so set the elt of the set source | |
5676 | to src_eqv_elt. */ | |
5677 | for (i = 0; i < n_sets; i++) | |
26132f71 JW |
5678 | if (sets[i].rtl && sets[i].src_elt == 0 |
5679 | && rtx_equal_p (SET_SRC (sets[i].rtl), src_eqv)) | |
f7911249 | 5680 | sets[i].src_elt = src_eqv_elt; |
7afe21cc RK |
5681 | } |
5682 | ||
5683 | for (i = 0; i < n_sets; i++) | |
5684 | if (sets[i].rtl && ! sets[i].src_volatile | |
5685 | && ! rtx_equal_p (SET_SRC (sets[i].rtl), SET_DEST (sets[i].rtl))) | |
5686 | { | |
5687 | if (GET_CODE (SET_DEST (sets[i].rtl)) == STRICT_LOW_PART) | |
5688 | { | |
5689 | /* REG_EQUAL in setting a STRICT_LOW_PART | |
5690 | gives an equivalent for the entire destination register, | |
5691 | not just for the subreg being stored in now. | |
5692 | This is a more interesting equivalence, so we arrange later | |
5693 | to treat the entire reg as the destination. */ | |
5694 | sets[i].src_elt = src_eqv_elt; | |
2197a88a | 5695 | sets[i].src_hash = src_eqv_hash; |
7afe21cc RK |
5696 | } |
5697 | else | |
5698 | { | |
5699 | /* Insert source and constant equivalent into hash table, if not | |
5700 | already present. */ | |
b3694847 SS |
5701 | struct table_elt *classp = src_eqv_elt; |
5702 | rtx src = sets[i].src; | |
5703 | rtx dest = SET_DEST (sets[i].rtl); | |
ef4bddc2 | 5704 | machine_mode mode |
7afe21cc RK |
5705 | = GET_MODE (src) == VOIDmode ? GET_MODE (dest) : GET_MODE (src); |
5706 | ||
1fcc57f1 AM |
5707 | /* It's possible that we have a source value known to be |
5708 | constant but don't have a REG_EQUAL note on the insn. | |
5709 | Lack of a note will mean src_eqv_elt will be NULL. This | |
5710 | can happen where we've generated a SUBREG to access a | |
5711 | CONST_INT that is already in a register in a wider mode. | |
5712 | Ensure that the source expression is put in the proper | |
5713 | constant class. */ | |
5714 | if (!classp) | |
5715 | classp = sets[i].src_const_elt; | |
5716 | ||
26132f71 | 5717 | if (sets[i].src_elt == 0) |
7afe21cc | 5718 | { |
4a8cae83 | 5719 | struct table_elt *elt; |
26132f71 | 5720 | |
4a8cae83 SB |
5721 | /* Note that these insert_regs calls cannot remove |
5722 | any of the src_elt's, because they would have failed to | |
5723 | match if not still valid. */ | |
dec7aaab | 5724 | if (insert_regs (src, classp, false)) |
4a8cae83 SB |
5725 | { |
5726 | rehash_using_reg (src); | |
5727 | sets[i].src_hash = HASH (src, mode); | |
8ae2b8f6 | 5728 | } |
4a8cae83 SB |
5729 | elt = insert (src, classp, sets[i].src_hash, mode); |
5730 | elt->in_memory = sets[i].src_in_memory; | |
6c4d60f8 JJ |
5731 | /* If inline asm has any clobbers, ensure we only reuse |
5732 | existing inline asms and never try to put the ASM_OPERANDS | |
5733 | into an insn that isn't inline asm. */ | |
5734 | if (GET_CODE (src) == ASM_OPERANDS | |
5735 | && GET_CODE (x) == PARALLEL) | |
5736 | elt->cost = MAX_COST; | |
4a8cae83 | 5737 | sets[i].src_elt = classp = elt; |
7afe21cc | 5738 | } |
7afe21cc RK |
5739 | if (sets[i].src_const && sets[i].src_const_elt == 0 |
5740 | && src != sets[i].src_const | |
5741 | && ! rtx_equal_p (sets[i].src_const, src)) | |
5742 | sets[i].src_elt = insert (sets[i].src_const, classp, | |
2197a88a | 5743 | sets[i].src_const_hash, mode); |
7afe21cc RK |
5744 | } |
5745 | } | |
5746 | else if (sets[i].src_elt == 0) | |
5747 | /* If we did not insert the source into the hash table (e.g., it was | |
5748 | volatile), note the equivalence class for the REG_EQUAL value, if any, | |
5749 | so that the destination goes into that class. */ | |
5750 | sets[i].src_elt = src_eqv_elt; | |
5751 | ||
05c433f3 PB |
5752 | /* Record destination addresses in the hash table. This allows us to |
5753 | check if they are invalidated by other sets. */ | |
5754 | for (i = 0; i < n_sets; i++) | |
5755 | { | |
5756 | if (sets[i].rtl) | |
5757 | { | |
5758 | rtx x = sets[i].inner_dest; | |
5759 | struct table_elt *elt; | |
ef4bddc2 | 5760 | machine_mode mode; |
05c433f3 PB |
5761 | unsigned hash; |
5762 | ||
5763 | if (MEM_P (x)) | |
5764 | { | |
5765 | x = XEXP (x, 0); | |
5766 | mode = GET_MODE (x); | |
5767 | hash = HASH (x, mode); | |
5768 | elt = lookup (x, hash, mode); | |
5769 | if (!elt) | |
5770 | { | |
dec7aaab | 5771 | if (insert_regs (x, NULL, false)) |
05c433f3 | 5772 | { |
7e7e28c7 AO |
5773 | rtx dest = SET_DEST (sets[i].rtl); |
5774 | ||
05c433f3 PB |
5775 | rehash_using_reg (x); |
5776 | hash = HASH (x, mode); | |
7e7e28c7 | 5777 | sets[i].dest_hash = HASH (dest, GET_MODE (dest)); |
05c433f3 PB |
5778 | } |
5779 | elt = insert (x, NULL, hash, mode); | |
5780 | } | |
5781 | ||
5782 | sets[i].dest_addr_elt = elt; | |
5783 | } | |
5784 | else | |
5785 | sets[i].dest_addr_elt = NULL; | |
5786 | } | |
5787 | } | |
5788 | ||
7b02f4e0 | 5789 | invalidate_from_clobbers (insn); |
77fa0940 | 5790 | |
278a83b2 | 5791 | /* Some registers are invalidated by subroutine calls. Memory is |
77fa0940 RK |
5792 | invalidated by non-constant calls. */ |
5793 | ||
4b4bf941 | 5794 | if (CALL_P (insn)) |
7afe21cc | 5795 | { |
becfd6e5 | 5796 | if (!(RTL_CONST_OR_PURE_CALL_P (insn))) |
9ae8ffe7 | 5797 | invalidate_memory (); |
67c25816 JJ |
5798 | else |
5799 | /* For const/pure calls, invalidate any argument slots, because | |
5800 | those are owned by the callee. */ | |
5801 | for (tem = CALL_INSN_FUNCTION_USAGE (insn); tem; tem = XEXP (tem, 1)) | |
5802 | if (GET_CODE (XEXP (tem, 0)) == USE | |
5803 | && MEM_P (XEXP (XEXP (tem, 0), 0))) | |
5804 | invalidate (XEXP (XEXP (tem, 0), 0), VOIDmode); | |
311b62ce | 5805 | invalidate_for_call (insn); |
7afe21cc RK |
5806 | } |
5807 | ||
5808 | /* Now invalidate everything set by this instruction. | |
5809 | If a SUBREG or other funny destination is being set, | |
5810 | sets[i].rtl is still nonzero, so here we invalidate the reg | |
5811 | a part of which is being set. */ | |
5812 | ||
5813 | for (i = 0; i < n_sets; i++) | |
5814 | if (sets[i].rtl) | |
5815 | { | |
bb4034b3 JW |
5816 | /* We can't use the inner dest, because the mode associated with |
5817 | a ZERO_EXTRACT is significant. */ | |
b3694847 | 5818 | rtx dest = SET_DEST (sets[i].rtl); |
7afe21cc RK |
5819 | |
5820 | /* Needed for registers to remove the register from its | |
5821 | previous quantity's chain. | |
5822 | Needed for memory if this is a nonvarying address, unless | |
5823 | we have just done an invalidate_memory that covers even those. */ | |
f8cfc6aa | 5824 | if (REG_P (dest) || GET_CODE (dest) == SUBREG) |
bb4034b3 | 5825 | invalidate (dest, VOIDmode); |
3c0cb5de | 5826 | else if (MEM_P (dest)) |
32fab725 | 5827 | invalidate (dest, VOIDmode); |
2708da92 RS |
5828 | else if (GET_CODE (dest) == STRICT_LOW_PART |
5829 | || GET_CODE (dest) == ZERO_EXTRACT) | |
bb4034b3 | 5830 | invalidate (XEXP (dest, 0), GET_MODE (dest)); |
7afe21cc RK |
5831 | } |
5832 | ||
932ad4d9 SB |
5833 | /* Don't cse over a call to setjmp; on some machines (eg VAX) |
5834 | the regs restored by the longjmp come from a later time | |
5835 | than the setjmp. */ | |
5836 | if (CALL_P (insn) && find_reg_note (insn, REG_SETJMP, NULL)) | |
5837 | { | |
5838 | flush_hash_table (); | |
5839 | goto done; | |
5840 | } | |
5841 | ||
7afe21cc RK |
5842 | /* Make sure registers mentioned in destinations |
5843 | are safe for use in an expression to be inserted. | |
5844 | This removes from the hash table | |
5845 | any invalid entry that refers to one of these registers. | |
5846 | ||
5847 | We don't care about the return value from mention_regs because | |
5848 | we are going to hash the SET_DEST values unconditionally. */ | |
5849 | ||
5850 | for (i = 0; i < n_sets; i++) | |
34c73909 R |
5851 | { |
5852 | if (sets[i].rtl) | |
5853 | { | |
5854 | rtx x = SET_DEST (sets[i].rtl); | |
5855 | ||
f8cfc6aa | 5856 | if (!REG_P (x)) |
34c73909 R |
5857 | mention_regs (x); |
5858 | else | |
5859 | { | |
5860 | /* We used to rely on all references to a register becoming | |
5861 | inaccessible when a register changes to a new quantity, | |
5862 | since that changes the hash code. However, that is not | |
9b1549b8 | 5863 | safe, since after HASH_SIZE new quantities we get a |
34c73909 R |
5864 | hash 'collision' of a register with its own invalid |
5865 | entries. And since SUBREGs have been changed not to | |
5866 | change their hash code with the hash code of the register, | |
5867 | it wouldn't work any longer at all. So we have to check | |
5868 | for any invalid references lying around now. | |
5869 | This code is similar to the REG case in mention_regs, | |
5870 | but it knows that reg_tick has been incremented, and | |
5871 | it leaves reg_in_table as -1 . */ | |
770ae6cc | 5872 | unsigned int regno = REGNO (x); |
09e18274 | 5873 | unsigned int endregno = END_REGNO (x); |
770ae6cc | 5874 | unsigned int i; |
34c73909 R |
5875 | |
5876 | for (i = regno; i < endregno; i++) | |
5877 | { | |
30f72379 | 5878 | if (REG_IN_TABLE (i) >= 0) |
34c73909 R |
5879 | { |
5880 | remove_invalid_refs (i); | |
30f72379 | 5881 | REG_IN_TABLE (i) = -1; |
34c73909 R |
5882 | } |
5883 | } | |
5884 | } | |
5885 | } | |
5886 | } | |
7afe21cc RK |
5887 | |
5888 | /* We may have just removed some of the src_elt's from the hash table. | |
05c433f3 PB |
5889 | So replace each one with the current head of the same class. |
5890 | Also check if destination addresses have been removed. */ | |
7afe21cc RK |
5891 | |
5892 | for (i = 0; i < n_sets; i++) | |
5893 | if (sets[i].rtl) | |
5894 | { | |
05c433f3 PB |
5895 | if (sets[i].dest_addr_elt |
5896 | && sets[i].dest_addr_elt->first_same_value == 0) | |
5897 | { | |
e67b81d1 | 5898 | /* The elt was removed, which means this destination is not |
05c433f3 PB |
5899 | valid after this instruction. */ |
5900 | sets[i].rtl = NULL_RTX; | |
5901 | } | |
5902 | else if (sets[i].src_elt && sets[i].src_elt->first_same_value == 0) | |
7afe21cc RK |
5903 | /* If elt was removed, find current head of same class, |
5904 | or 0 if nothing remains of that class. */ | |
5905 | { | |
b3694847 | 5906 | struct table_elt *elt = sets[i].src_elt; |
7afe21cc RK |
5907 | |
5908 | while (elt && elt->prev_same_value) | |
5909 | elt = elt->prev_same_value; | |
5910 | ||
5911 | while (elt && elt->first_same_value == 0) | |
5912 | elt = elt->next_same_value; | |
5913 | sets[i].src_elt = elt ? elt->first_same_value : 0; | |
5914 | } | |
5915 | } | |
5916 | ||
5917 | /* Now insert the destinations into their equivalence classes. */ | |
5918 | ||
5919 | for (i = 0; i < n_sets; i++) | |
5920 | if (sets[i].rtl) | |
5921 | { | |
b3694847 | 5922 | rtx dest = SET_DEST (sets[i].rtl); |
b3694847 | 5923 | struct table_elt *elt; |
7afe21cc RK |
5924 | |
5925 | /* Don't record value if we are not supposed to risk allocating | |
5926 | floating-point values in registers that might be wider than | |
5927 | memory. */ | |
5928 | if ((flag_float_store | |
3c0cb5de | 5929 | && MEM_P (dest) |
cbf6a543 | 5930 | && FLOAT_MODE_P (GET_MODE (dest))) |
bc4ddc77 JW |
5931 | /* Don't record BLKmode values, because we don't know the |
5932 | size of it, and can't be sure that other BLKmode values | |
5933 | have the same or smaller size. */ | |
5934 | || GET_MODE (dest) == BLKmode | |
7afe21cc RK |
5935 | /* If we didn't put a REG_EQUAL value or a source into the hash |
5936 | table, there is no point is recording DEST. */ | |
086ad22e | 5937 | || sets[i].src_elt == 0) |
7afe21cc RK |
5938 | continue; |
5939 | ||
5940 | /* STRICT_LOW_PART isn't part of the value BEING set, | |
5941 | and neither is the SUBREG inside it. | |
5942 | Note that in this case SETS[I].SRC_ELT is really SRC_EQV_ELT. */ | |
5943 | if (GET_CODE (dest) == STRICT_LOW_PART) | |
5944 | dest = SUBREG_REG (XEXP (dest, 0)); | |
5945 | ||
f8cfc6aa | 5946 | if (REG_P (dest) || GET_CODE (dest) == SUBREG) |
7afe21cc | 5947 | /* Registers must also be inserted into chains for quantities. */ |
dec7aaab | 5948 | if (insert_regs (dest, sets[i].src_elt, true)) |
8ae2b8f6 JW |
5949 | { |
5950 | /* If `insert_regs' changes something, the hash code must be | |
5951 | recalculated. */ | |
5952 | rehash_using_reg (dest); | |
5953 | sets[i].dest_hash = HASH (dest, GET_MODE (dest)); | |
5954 | } | |
7afe21cc | 5955 | |
086ad22e BE |
5956 | /* If DEST is a paradoxical SUBREG, don't record DEST since the bits |
5957 | outside the mode of GET_MODE (SUBREG_REG (dest)) are undefined. */ | |
5958 | if (paradoxical_subreg_p (dest)) | |
5959 | continue; | |
5960 | ||
8fff4fc1 RH |
5961 | elt = insert (dest, sets[i].src_elt, |
5962 | sets[i].dest_hash, GET_MODE (dest)); | |
9de2c71a | 5963 | |
2c5bfdf7 AN |
5964 | /* If this is a constant, insert the constant anchors with the |
5965 | equivalent register-offset expressions using register DEST. */ | |
5966 | if (targetm.const_anchor | |
5967 | && REG_P (dest) | |
5968 | && SCALAR_INT_MODE_P (GET_MODE (dest)) | |
5969 | && GET_CODE (sets[i].src_elt->exp) == CONST_INT) | |
5970 | insert_const_anchors (dest, sets[i].src_elt->exp, GET_MODE (dest)); | |
5971 | ||
3c0cb5de | 5972 | elt->in_memory = (MEM_P (sets[i].inner_dest) |
389fdba0 | 5973 | && !MEM_READONLY_P (sets[i].inner_dest)); |
c256df0b | 5974 | |
fc3ffe83 RK |
5975 | /* If we have (set (subreg:m1 (reg:m2 foo) 0) (bar:m1)), M1 is no |
5976 | narrower than M2, and both M1 and M2 are the same number of words, | |
5977 | we are also doing (set (reg:m2 foo) (subreg:m2 (bar:m1) 0)) so | |
5978 | make that equivalence as well. | |
7afe21cc | 5979 | |
4de249d9 PB |
5980 | However, BAR may have equivalences for which gen_lowpart |
5981 | will produce a simpler value than gen_lowpart applied to | |
7afe21cc | 5982 | BAR (e.g., if BAR was ZERO_EXTENDed from M2), so we will scan all |
278a83b2 | 5983 | BAR's equivalences. If we don't get a simplified form, make |
7afe21cc RK |
5984 | the SUBREG. It will not be used in an equivalence, but will |
5985 | cause two similar assignments to be detected. | |
5986 | ||
5987 | Note the loop below will find SUBREG_REG (DEST) since we have | |
5988 | already entered SRC and DEST of the SET in the table. */ | |
5989 | ||
5990 | if (GET_CODE (dest) == SUBREG | |
cf098191 RS |
5991 | && (known_equal_after_align_down |
5992 | (GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) - 1, | |
5993 | GET_MODE_SIZE (GET_MODE (dest)) - 1, | |
5994 | UNITS_PER_WORD)) | |
bd4288c0 | 5995 | && !partial_subreg_p (dest) |
7afe21cc RK |
5996 | && sets[i].src_elt != 0) |
5997 | { | |
ef4bddc2 | 5998 | machine_mode new_mode = GET_MODE (SUBREG_REG (dest)); |
7afe21cc RK |
5999 | struct table_elt *elt, *classp = 0; |
6000 | ||
6001 | for (elt = sets[i].src_elt->first_same_value; elt; | |
6002 | elt = elt->next_same_value) | |
6003 | { | |
6004 | rtx new_src = 0; | |
2197a88a | 6005 | unsigned src_hash; |
7afe21cc RK |
6006 | struct table_elt *src_elt; |
6007 | ||
6008 | /* Ignore invalid entries. */ | |
f8cfc6aa | 6009 | if (!REG_P (elt->exp) |
0516f6fe | 6010 | && ! exp_equiv_p (elt->exp, elt->exp, 1, false)) |
7afe21cc RK |
6011 | continue; |
6012 | ||
9beb7d20 RH |
6013 | /* We may have already been playing subreg games. If the |
6014 | mode is already correct for the destination, use it. */ | |
6015 | if (GET_MODE (elt->exp) == new_mode) | |
6016 | new_src = elt->exp; | |
6017 | else | |
6018 | { | |
91914e56 | 6019 | poly_uint64 byte |
610c45fc | 6020 | = subreg_lowpart_offset (new_mode, GET_MODE (dest)); |
9beb7d20 RH |
6021 | new_src = simplify_gen_subreg (new_mode, elt->exp, |
6022 | GET_MODE (dest), byte); | |
6023 | } | |
6024 | ||
ff27a429 R |
6025 | /* The call to simplify_gen_subreg fails if the value |
6026 | is VOIDmode, yet we can't do any simplification, e.g. | |
6027 | for EXPR_LISTs denoting function call results. | |
6028 | It is invalid to construct a SUBREG with a VOIDmode | |
6029 | SUBREG_REG, hence a zero new_src means we can't do | |
6030 | this substitution. */ | |
6031 | if (! new_src) | |
6032 | continue; | |
7afe21cc RK |
6033 | |
6034 | src_hash = HASH (new_src, new_mode); | |
6035 | src_elt = lookup (new_src, src_hash, new_mode); | |
6036 | ||
6037 | /* Put the new source in the hash table is if isn't | |
6038 | already. */ | |
6039 | if (src_elt == 0) | |
6040 | { | |
dec7aaab | 6041 | if (insert_regs (new_src, classp, false)) |
8ae2b8f6 JW |
6042 | { |
6043 | rehash_using_reg (new_src); | |
6044 | src_hash = HASH (new_src, new_mode); | |
6045 | } | |
7afe21cc RK |
6046 | src_elt = insert (new_src, classp, src_hash, new_mode); |
6047 | src_elt->in_memory = elt->in_memory; | |
6c4d60f8 JJ |
6048 | if (GET_CODE (new_src) == ASM_OPERANDS |
6049 | && elt->cost == MAX_COST) | |
6050 | src_elt->cost = MAX_COST; | |
7afe21cc RK |
6051 | } |
6052 | else if (classp && classp != src_elt->first_same_value) | |
278a83b2 | 6053 | /* Show that two things that we've seen before are |
7afe21cc RK |
6054 | actually the same. */ |
6055 | merge_equiv_classes (src_elt, classp); | |
6056 | ||
6057 | classp = src_elt->first_same_value; | |
da932f04 JL |
6058 | /* Ignore invalid entries. */ |
6059 | while (classp | |
f8cfc6aa | 6060 | && !REG_P (classp->exp) |
0516f6fe | 6061 | && ! exp_equiv_p (classp->exp, classp->exp, 1, false)) |
da932f04 | 6062 | classp = classp->next_same_value; |
7afe21cc RK |
6063 | } |
6064 | } | |
6065 | } | |
6066 | ||
403e25d0 RK |
6067 | /* Special handling for (set REG0 REG1) where REG0 is the |
6068 | "cheapest", cheaper than REG1. After cse, REG1 will probably not | |
6069 | be used in the sequel, so (if easily done) change this insn to | |
6070 | (set REG1 REG0) and replace REG1 with REG0 in the previous insn | |
6071 | that computed their value. Then REG1 will become a dead store | |
6072 | and won't cloud the situation for later optimizations. | |
7afe21cc RK |
6073 | |
6074 | Do not make this change if REG1 is a hard register, because it will | |
6075 | then be used in the sequel and we may be changing a two-operand insn | |
6076 | into a three-operand insn. | |
6077 | ||
4a8cae83 | 6078 | Also do not do this if we are operating on a copy of INSN. */ |
7afe21cc | 6079 | |
7b02f4e0 SB |
6080 | if (n_sets == 1 && sets[0].rtl) |
6081 | try_back_substitute_reg (sets[0].rtl, insn); | |
7afe21cc | 6082 | |
932ad4d9 | 6083 | done:; |
7afe21cc RK |
6084 | } |
6085 | \f | |
a4c6502a | 6086 | /* Remove from the hash table all expressions that reference memory. */ |
14a774a9 | 6087 | |
7afe21cc | 6088 | static void |
7080f735 | 6089 | invalidate_memory (void) |
7afe21cc | 6090 | { |
b3694847 SS |
6091 | int i; |
6092 | struct table_elt *p, *next; | |
7afe21cc | 6093 | |
9b1549b8 | 6094 | for (i = 0; i < HASH_SIZE; i++) |
9ae8ffe7 JL |
6095 | for (p = table[i]; p; p = next) |
6096 | { | |
6097 | next = p->next_same_hash; | |
6098 | if (p->in_memory) | |
6099 | remove_from_table (p, i); | |
6100 | } | |
6101 | } | |
6102 | ||
7b02f4e0 | 6103 | /* Perform invalidation on the basis of everything about INSN, |
7afe21cc RK |
6104 | except for invalidating the actual places that are SET in it. |
6105 | This includes the places CLOBBERed, and anything that might | |
7b02f4e0 | 6106 | alias with something that is SET or CLOBBERed. */ |
7afe21cc RK |
6107 | |
6108 | static void | |
20468884 | 6109 | invalidate_from_clobbers (rtx_insn *insn) |
7afe21cc | 6110 | { |
7b02f4e0 SB |
6111 | rtx x = PATTERN (insn); |
6112 | ||
7afe21cc RK |
6113 | if (GET_CODE (x) == CLOBBER) |
6114 | { | |
6115 | rtx ref = XEXP (x, 0); | |
9ae8ffe7 JL |
6116 | if (ref) |
6117 | { | |
f8cfc6aa | 6118 | if (REG_P (ref) || GET_CODE (ref) == SUBREG |
3c0cb5de | 6119 | || MEM_P (ref)) |
9ae8ffe7 JL |
6120 | invalidate (ref, VOIDmode); |
6121 | else if (GET_CODE (ref) == STRICT_LOW_PART | |
6122 | || GET_CODE (ref) == ZERO_EXTRACT) | |
6123 | invalidate (XEXP (ref, 0), GET_MODE (ref)); | |
6124 | } | |
7afe21cc RK |
6125 | } |
6126 | else if (GET_CODE (x) == PARALLEL) | |
6127 | { | |
b3694847 | 6128 | int i; |
7afe21cc RK |
6129 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) |
6130 | { | |
b3694847 | 6131 | rtx y = XVECEXP (x, 0, i); |
7afe21cc RK |
6132 | if (GET_CODE (y) == CLOBBER) |
6133 | { | |
6134 | rtx ref = XEXP (y, 0); | |
f8cfc6aa | 6135 | if (REG_P (ref) || GET_CODE (ref) == SUBREG |
3c0cb5de | 6136 | || MEM_P (ref)) |
9ae8ffe7 JL |
6137 | invalidate (ref, VOIDmode); |
6138 | else if (GET_CODE (ref) == STRICT_LOW_PART | |
6139 | || GET_CODE (ref) == ZERO_EXTRACT) | |
6140 | invalidate (XEXP (ref, 0), GET_MODE (ref)); | |
7afe21cc RK |
6141 | } |
6142 | } | |
6143 | } | |
6144 | } | |
6145 | \f | |
7b02f4e0 SB |
6146 | /* Perform invalidation on the basis of everything about INSN. |
6147 | This includes the places CLOBBERed, and anything that might | |
6148 | alias with something that is SET or CLOBBERed. */ | |
6149 | ||
6150 | static void | |
20468884 | 6151 | invalidate_from_sets_and_clobbers (rtx_insn *insn) |
7b02f4e0 SB |
6152 | { |
6153 | rtx tem; | |
6154 | rtx x = PATTERN (insn); | |
6155 | ||
6156 | if (CALL_P (insn)) | |
6157 | { | |
6158 | for (tem = CALL_INSN_FUNCTION_USAGE (insn); tem; tem = XEXP (tem, 1)) | |
99788e06 AH |
6159 | { |
6160 | rtx temx = XEXP (tem, 0); | |
6161 | if (GET_CODE (temx) == CLOBBER) | |
6162 | invalidate (SET_DEST (temx), VOIDmode); | |
99788e06 | 6163 | } |
7b02f4e0 SB |
6164 | } |
6165 | ||
6166 | /* Ensure we invalidate the destination register of a CALL insn. | |
6167 | This is necessary for machines where this register is a fixed_reg, | |
6168 | because no other code would invalidate it. */ | |
6169 | if (GET_CODE (x) == SET && GET_CODE (SET_SRC (x)) == CALL) | |
6170 | invalidate (SET_DEST (x), VOIDmode); | |
6171 | ||
6172 | else if (GET_CODE (x) == PARALLEL) | |
6173 | { | |
6174 | int i; | |
6175 | ||
6176 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
6177 | { | |
6178 | rtx y = XVECEXP (x, 0, i); | |
6179 | if (GET_CODE (y) == CLOBBER) | |
6180 | { | |
6181 | rtx clobbered = XEXP (y, 0); | |
6182 | ||
6183 | if (REG_P (clobbered) | |
6184 | || GET_CODE (clobbered) == SUBREG) | |
6185 | invalidate (clobbered, VOIDmode); | |
6186 | else if (GET_CODE (clobbered) == STRICT_LOW_PART | |
6187 | || GET_CODE (clobbered) == ZERO_EXTRACT) | |
6188 | invalidate (XEXP (clobbered, 0), GET_MODE (clobbered)); | |
6189 | } | |
6190 | else if (GET_CODE (y) == SET && GET_CODE (SET_SRC (y)) == CALL) | |
6191 | invalidate (SET_DEST (y), VOIDmode); | |
6192 | } | |
6193 | } | |
6194 | } | |
6195 | \f | |
66ec22b0 | 6196 | static rtx cse_process_note (rtx); |
7afe21cc | 6197 | |
66ec22b0 RS |
6198 | /* A simplify_replace_fn_rtx callback for cse_process_note. Process X, |
6199 | part of the REG_NOTES of an insn. Replace any registers with either | |
6200 | an equivalent constant or the canonical form of the register. | |
6201 | Only replace addresses if the containing MEM remains valid. | |
7afe21cc | 6202 | |
66ec22b0 RS |
6203 | Return the replacement for X, or null if it should be simplified |
6204 | recursively. */ | |
7afe21cc RK |
6205 | |
6206 | static rtx | |
66ec22b0 | 6207 | cse_process_note_1 (rtx x, const_rtx, void *) |
7afe21cc | 6208 | { |
66ec22b0 | 6209 | if (MEM_P (x)) |
7afe21cc | 6210 | { |
66ec22b0 | 6211 | validate_change (x, &XEXP (x, 0), cse_process_note (XEXP (x, 0)), false); |
7afe21cc | 6212 | return x; |
66ec22b0 | 6213 | } |
7afe21cc | 6214 | |
66ec22b0 RS |
6215 | if (REG_P (x)) |
6216 | { | |
6217 | int i = REG_QTY (REGNO (x)); | |
7afe21cc RK |
6218 | |
6219 | /* Return a constant or a constant register. */ | |
1bb98cec | 6220 | if (REGNO_QTY_VALID_P (REGNO (x))) |
7afe21cc | 6221 | { |
1bb98cec DM |
6222 | struct qty_table_elem *ent = &qty_table[i]; |
6223 | ||
6224 | if (ent->const_rtx != NULL_RTX | |
6225 | && (CONSTANT_P (ent->const_rtx) | |
f8cfc6aa | 6226 | || REG_P (ent->const_rtx))) |
1bb98cec | 6227 | { |
32e9fa48 KG |
6228 | rtx new_rtx = gen_lowpart (GET_MODE (x), ent->const_rtx); |
6229 | if (new_rtx) | |
6230 | return copy_rtx (new_rtx); | |
1bb98cec | 6231 | } |
7afe21cc RK |
6232 | } |
6233 | ||
6234 | /* Otherwise, canonicalize this register. */ | |
20468884 | 6235 | return canon_reg (x, NULL); |
7afe21cc RK |
6236 | } |
6237 | ||
66ec22b0 | 6238 | return NULL_RTX; |
7afe21cc | 6239 | } |
6fb5fa3c | 6240 | |
66ec22b0 RS |
6241 | /* Process X, part of the REG_NOTES of an insn. Replace any registers in it |
6242 | with either an equivalent constant or the canonical form of the register. | |
6243 | Only replace addresses if the containing MEM remains valid. */ | |
6244 | ||
6fb5fa3c | 6245 | static rtx |
66ec22b0 | 6246 | cse_process_note (rtx x) |
6fb5fa3c | 6247 | { |
66ec22b0 | 6248 | return simplify_replace_fn_rtx (x, NULL_RTX, cse_process_note_1, NULL); |
6fb5fa3c DB |
6249 | } |
6250 | ||
7afe21cc | 6251 | \f |
932ad4d9 | 6252 | /* Find a path in the CFG, starting with FIRST_BB to perform CSE on. |
7afe21cc | 6253 | |
932ad4d9 SB |
6254 | DATA is a pointer to a struct cse_basic_block_data, that is used to |
6255 | describe the path. | |
6256 | It is filled with a queue of basic blocks, starting with FIRST_BB | |
6257 | and following a trace through the CFG. | |
b8698a0f | 6258 | |
932ad4d9 SB |
6259 | If all paths starting at FIRST_BB have been followed, or no new path |
6260 | starting at FIRST_BB can be constructed, this function returns FALSE. | |
6261 | Otherwise, DATA->path is filled and the function returns TRUE indicating | |
6262 | that a path to follow was found. | |
7afe21cc | 6263 | |
2e226e66 | 6264 | If FOLLOW_JUMPS is false, the maximum path length is 1 and the only |
932ad4d9 | 6265 | block in the path will be FIRST_BB. */ |
7afe21cc | 6266 | |
932ad4d9 SB |
6267 | static bool |
6268 | cse_find_path (basic_block first_bb, struct cse_basic_block_data *data, | |
6269 | int follow_jumps) | |
7afe21cc | 6270 | { |
932ad4d9 SB |
6271 | basic_block bb; |
6272 | edge e; | |
6273 | int path_size; | |
b8698a0f | 6274 | |
d7c028c0 | 6275 | bitmap_set_bit (cse_visited_basic_blocks, first_bb->index); |
7afe21cc | 6276 | |
932ad4d9 SB |
6277 | /* See if there is a previous path. */ |
6278 | path_size = data->path_size; | |
6279 | ||
6280 | /* There is a previous path. Make sure it started with FIRST_BB. */ | |
6281 | if (path_size) | |
6282 | gcc_assert (data->path[0].bb == first_bb); | |
6283 | ||
6284 | /* There was only one basic block in the last path. Clear the path and | |
6285 | return, so that paths starting at another basic block can be tried. */ | |
6286 | if (path_size == 1) | |
6287 | { | |
6288 | path_size = 0; | |
6289 | goto done; | |
6290 | } | |
6291 | ||
6292 | /* If the path was empty from the beginning, construct a new path. */ | |
6293 | if (path_size == 0) | |
6294 | data->path[path_size++].bb = first_bb; | |
6295 | else | |
7afe21cc | 6296 | { |
932ad4d9 SB |
6297 | /* Otherwise, path_size must be equal to or greater than 2, because |
6298 | a previous path exists that is at least two basic blocks long. | |
6299 | ||
6300 | Update the previous branch path, if any. If the last branch was | |
6301 | previously along the branch edge, take the fallthrough edge now. */ | |
6302 | while (path_size >= 2) | |
7afe21cc | 6303 | { |
932ad4d9 SB |
6304 | basic_block last_bb_in_path, previous_bb_in_path; |
6305 | edge e; | |
6306 | ||
6307 | --path_size; | |
6308 | last_bb_in_path = data->path[path_size].bb; | |
6309 | previous_bb_in_path = data->path[path_size - 1].bb; | |
6310 | ||
6311 | /* If we previously followed a path along the branch edge, try | |
6312 | the fallthru edge now. */ | |
6313 | if (EDGE_COUNT (previous_bb_in_path->succs) == 2 | |
6314 | && any_condjump_p (BB_END (previous_bb_in_path)) | |
6315 | && (e = find_edge (previous_bb_in_path, last_bb_in_path)) | |
6316 | && e == BRANCH_EDGE (previous_bb_in_path)) | |
6317 | { | |
6318 | bb = FALLTHRU_EDGE (previous_bb_in_path)->dest; | |
fefa31b5 | 6319 | if (bb != EXIT_BLOCK_PTR_FOR_FN (cfun) |
481e0a49 AO |
6320 | && single_pred_p (bb) |
6321 | /* We used to assert here that we would only see blocks | |
6322 | that we have not visited yet. But we may end up | |
6323 | visiting basic blocks twice if the CFG has changed | |
6324 | in this run of cse_main, because when the CFG changes | |
6325 | the topological sort of the CFG also changes. A basic | |
6326 | blocks that previously had more than two predecessors | |
6327 | may now have a single predecessor, and become part of | |
6328 | a path that starts at another basic block. | |
6329 | ||
6330 | We still want to visit each basic block only once, so | |
6331 | halt the path here if we have already visited BB. */ | |
d7c028c0 | 6332 | && !bitmap_bit_p (cse_visited_basic_blocks, bb->index)) |
932ad4d9 | 6333 | { |
d7c028c0 | 6334 | bitmap_set_bit (cse_visited_basic_blocks, bb->index); |
932ad4d9 SB |
6335 | data->path[path_size++].bb = bb; |
6336 | break; | |
6337 | } | |
6338 | } | |
6339 | ||
6340 | data->path[path_size].bb = NULL; | |
6341 | } | |
6342 | ||
6343 | /* If only one block remains in the path, bail. */ | |
6344 | if (path_size == 1) | |
6345 | { | |
6346 | path_size = 0; | |
6347 | goto done; | |
7afe21cc | 6348 | } |
7afe21cc RK |
6349 | } |
6350 | ||
932ad4d9 SB |
6351 | /* Extend the path if possible. */ |
6352 | if (follow_jumps) | |
7afe21cc | 6353 | { |
932ad4d9 | 6354 | bb = data->path[path_size - 1].bb; |
028d4092 | 6355 | while (bb && path_size < param_max_cse_path_length) |
932ad4d9 SB |
6356 | { |
6357 | if (single_succ_p (bb)) | |
6358 | e = single_succ_edge (bb); | |
6359 | else if (EDGE_COUNT (bb->succs) == 2 | |
6360 | && any_condjump_p (BB_END (bb))) | |
6361 | { | |
6362 | /* First try to follow the branch. If that doesn't lead | |
6363 | to a useful path, follow the fallthru edge. */ | |
6364 | e = BRANCH_EDGE (bb); | |
6365 | if (!single_pred_p (e->dest)) | |
6366 | e = FALLTHRU_EDGE (bb); | |
6367 | } | |
6368 | else | |
6369 | e = NULL; | |
7afe21cc | 6370 | |
bc6d3f91 | 6371 | if (e |
76015c34 | 6372 | && !((e->flags & EDGE_ABNORMAL_CALL) && cfun->has_nonlocal_label) |
fefa31b5 | 6373 | && e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun) |
481e0a49 AO |
6374 | && single_pred_p (e->dest) |
6375 | /* Avoid visiting basic blocks twice. The large comment | |
6376 | above explains why this can happen. */ | |
d7c028c0 | 6377 | && !bitmap_bit_p (cse_visited_basic_blocks, e->dest->index)) |
932ad4d9 SB |
6378 | { |
6379 | basic_block bb2 = e->dest; | |
d7c028c0 | 6380 | bitmap_set_bit (cse_visited_basic_blocks, bb2->index); |
932ad4d9 SB |
6381 | data->path[path_size++].bb = bb2; |
6382 | bb = bb2; | |
6383 | } | |
6384 | else | |
6385 | bb = NULL; | |
6386 | } | |
6387 | } | |
6388 | ||
6389 | done: | |
6390 | data->path_size = path_size; | |
6391 | return path_size != 0; | |
6392 | } | |
6393 | \f | |
6394 | /* Dump the path in DATA to file F. NSETS is the number of sets | |
6395 | in the path. */ | |
6396 | ||
6397 | static void | |
6398 | cse_dump_path (struct cse_basic_block_data *data, int nsets, FILE *f) | |
6399 | { | |
6400 | int path_entry; | |
6401 | ||
6402 | fprintf (f, ";; Following path with %d sets: ", nsets); | |
6403 | for (path_entry = 0; path_entry < data->path_size; path_entry++) | |
6404 | fprintf (f, "%d ", (data->path[path_entry].bb)->index); | |
a29dd8dd | 6405 | fputc ('\n', f); |
932ad4d9 SB |
6406 | fflush (f); |
6407 | } | |
6408 | ||
a7582f7c SB |
6409 | \f |
6410 | /* Return true if BB has exception handling successor edges. */ | |
6411 | ||
6412 | static bool | |
6413 | have_eh_succ_edges (basic_block bb) | |
6414 | { | |
6415 | edge e; | |
6416 | edge_iterator ei; | |
6417 | ||
6418 | FOR_EACH_EDGE (e, ei, bb->succs) | |
6419 | if (e->flags & EDGE_EH) | |
6420 | return true; | |
6421 | ||
6422 | return false; | |
6423 | } | |
6424 | ||
932ad4d9 SB |
6425 | \f |
6426 | /* Scan to the end of the path described by DATA. Return an estimate of | |
6fb5fa3c | 6427 | the total number of SETs of all insns in the path. */ |
932ad4d9 SB |
6428 | |
6429 | static void | |
6430 | cse_prescan_path (struct cse_basic_block_data *data) | |
6431 | { | |
6432 | int nsets = 0; | |
932ad4d9 SB |
6433 | int path_size = data->path_size; |
6434 | int path_entry; | |
6435 | ||
6436 | /* Scan to end of each basic block in the path. */ | |
b8698a0f | 6437 | for (path_entry = 0; path_entry < path_size; path_entry++) |
932ad4d9 SB |
6438 | { |
6439 | basic_block bb; | |
20468884 | 6440 | rtx_insn *insn; |
164c8956 | 6441 | |
932ad4d9 | 6442 | bb = data->path[path_entry].bb; |
7afe21cc | 6443 | |
932ad4d9 | 6444 | FOR_BB_INSNS (bb, insn) |
7afe21cc | 6445 | { |
932ad4d9 SB |
6446 | if (!INSN_P (insn)) |
6447 | continue; | |
278a83b2 | 6448 | |
932ad4d9 SB |
6449 | /* A PARALLEL can have lots of SETs in it, |
6450 | especially if it is really an ASM_OPERANDS. */ | |
6451 | if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
6452 | nsets += XVECLEN (PATTERN (insn), 0); | |
6453 | else | |
6454 | nsets += 1; | |
7afe21cc | 6455 | } |
932ad4d9 SB |
6456 | } |
6457 | ||
932ad4d9 SB |
6458 | data->nsets = nsets; |
6459 | } | |
6460 | \f | |
f0002948 RS |
6461 | /* Return true if the pattern of INSN uses a LABEL_REF for which |
6462 | there isn't a REG_LABEL_OPERAND note. */ | |
6463 | ||
6464 | static bool | |
6465 | check_for_label_ref (rtx_insn *insn) | |
6466 | { | |
6467 | /* If this insn uses a LABEL_REF and there isn't a REG_LABEL_OPERAND | |
6468 | note for it, we must rerun jump since it needs to place the note. If | |
6469 | this is a LABEL_REF for a CODE_LABEL that isn't in the insn chain, | |
6470 | don't do this since no REG_LABEL_OPERAND will be added. */ | |
6471 | subrtx_iterator::array_type array; | |
6472 | FOR_EACH_SUBRTX (iter, array, PATTERN (insn), ALL) | |
6473 | { | |
6474 | const_rtx x = *iter; | |
6475 | if (GET_CODE (x) == LABEL_REF | |
6476 | && !LABEL_REF_NONLOCAL_P (x) | |
6477 | && (!JUMP_P (insn) | |
04a121a7 TS |
6478 | || !label_is_jump_target_p (label_ref_label (x), insn)) |
6479 | && LABEL_P (label_ref_label (x)) | |
6480 | && INSN_UID (label_ref_label (x)) != 0 | |
6481 | && !find_reg_note (insn, REG_LABEL_OPERAND, label_ref_label (x))) | |
f0002948 RS |
6482 | return true; |
6483 | } | |
6484 | return false; | |
6485 | } | |
6486 | ||
932ad4d9 | 6487 | /* Process a single extended basic block described by EBB_DATA. */ |
7afe21cc | 6488 | |
932ad4d9 SB |
6489 | static void |
6490 | cse_extended_basic_block (struct cse_basic_block_data *ebb_data) | |
6491 | { | |
6492 | int path_size = ebb_data->path_size; | |
6493 | int path_entry; | |
6494 | int num_insns = 0; | |
6495 | ||
6496 | /* Allocate the space needed by qty_table. */ | |
6497 | qty_table = XNEWVEC (struct qty_table_elem, max_qty); | |
6498 | ||
6499 | new_basic_block (); | |
89a95777 KZ |
6500 | cse_ebb_live_in = df_get_live_in (ebb_data->path[0].bb); |
6501 | cse_ebb_live_out = df_get_live_out (ebb_data->path[path_size - 1].bb); | |
932ad4d9 SB |
6502 | for (path_entry = 0; path_entry < path_size; path_entry++) |
6503 | { | |
6504 | basic_block bb; | |
20468884 | 6505 | rtx_insn *insn; |
932ad4d9 SB |
6506 | |
6507 | bb = ebb_data->path[path_entry].bb; | |
e186ff69 AK |
6508 | |
6509 | /* Invalidate recorded information for eh regs if there is an EH | |
6510 | edge pointing to that bb. */ | |
6511 | if (bb_has_eh_pred (bb)) | |
6512 | { | |
292321a5 | 6513 | df_ref def; |
e186ff69 | 6514 | |
292321a5 RS |
6515 | FOR_EACH_ARTIFICIAL_DEF (def, bb->index) |
6516 | if (DF_REF_FLAGS (def) & DF_REF_AT_TOP) | |
6517 | invalidate (DF_REF_REG (def), GET_MODE (DF_REF_REG (def))); | |
e186ff69 AK |
6518 | } |
6519 | ||
9fcb01de | 6520 | optimize_this_for_speed_p = optimize_bb_for_speed_p (bb); |
ba4807a0 | 6521 | FOR_BB_INSNS (bb, insn) |
7afe21cc | 6522 | { |
932ad4d9 SB |
6523 | /* If we have processed 1,000 insns, flush the hash table to |
6524 | avoid extreme quadratic behavior. We must not include NOTEs | |
6525 | in the count since there may be more of them when generating | |
6526 | debugging information. If we clear the table at different | |
6527 | times, code generated with -g -O might be different than code | |
6528 | generated with -O but not -g. | |
6529 | ||
6530 | FIXME: This is a real kludge and needs to be done some other | |
6531 | way. */ | |
b5b8b0ac | 6532 | if (NONDEBUG_INSN_P (insn) |
028d4092 | 6533 | && num_insns++ > param_max_cse_insns) |
932ad4d9 SB |
6534 | { |
6535 | flush_hash_table (); | |
6536 | num_insns = 0; | |
6537 | } | |
7afe21cc | 6538 | |
932ad4d9 | 6539 | if (INSN_P (insn)) |
7afe21cc | 6540 | { |
932ad4d9 SB |
6541 | /* Process notes first so we have all notes in canonical forms |
6542 | when looking for duplicate operations. */ | |
66ec22b0 RS |
6543 | bool changed = false; |
6544 | for (rtx note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
6545 | if (REG_NOTE_KIND (note) == REG_EQUAL) | |
6546 | { | |
6547 | rtx newval = cse_process_note (XEXP (note, 0)); | |
6548 | if (newval != XEXP (note, 0)) | |
6549 | { | |
6550 | XEXP (note, 0) = newval; | |
6551 | changed = true; | |
6552 | } | |
6553 | } | |
6554 | if (changed) | |
6555 | df_notes_rescan (insn); | |
932ad4d9 | 6556 | |
4a8cae83 | 6557 | cse_insn (insn); |
932ad4d9 | 6558 | |
932ad4d9 SB |
6559 | /* If we haven't already found an insn where we added a LABEL_REF, |
6560 | check this one. */ | |
2aac3a01 | 6561 | if (INSN_P (insn) && !recorded_label_ref |
f0002948 | 6562 | && check_for_label_ref (insn)) |
2aac3a01 | 6563 | recorded_label_ref = true; |
932ad4d9 SB |
6564 | } |
6565 | } | |
7afe21cc | 6566 | |
a7582f7c SB |
6567 | /* With non-call exceptions, we are not always able to update |
6568 | the CFG properly inside cse_insn. So clean up possibly | |
6569 | redundant EH edges here. */ | |
8f4f502f | 6570 | if (cfun->can_throw_non_call_exceptions && have_eh_succ_edges (bb)) |
2aac3a01 | 6571 | cse_cfg_altered |= purge_dead_edges (bb); |
a7582f7c | 6572 | |
932ad4d9 SB |
6573 | /* If we changed a conditional jump, we may have terminated |
6574 | the path we are following. Check that by verifying that | |
6575 | the edge we would take still exists. If the edge does | |
6576 | not exist anymore, purge the remainder of the path. | |
6577 | Note that this will cause us to return to the caller. */ | |
6578 | if (path_entry < path_size - 1) | |
6579 | { | |
6580 | basic_block next_bb = ebb_data->path[path_entry + 1].bb; | |
6581 | if (!find_edge (bb, next_bb)) | |
27511c65 SB |
6582 | { |
6583 | do | |
6584 | { | |
6585 | path_size--; | |
6586 | ||
6587 | /* If we truncate the path, we must also reset the | |
6588 | visited bit on the remaining blocks in the path, | |
6589 | or we will never visit them at all. */ | |
d7c028c0 | 6590 | bitmap_clear_bit (cse_visited_basic_blocks, |
27511c65 SB |
6591 | ebb_data->path[path_size].bb->index); |
6592 | ebb_data->path[path_size].bb = NULL; | |
6593 | } | |
6594 | while (path_size - 1 != path_entry); | |
6595 | ebb_data->path_size = path_size; | |
6596 | } | |
7afe21cc | 6597 | } |
7afe21cc | 6598 | |
932ad4d9 SB |
6599 | /* If this is a conditional jump insn, record any known |
6600 | equivalences due to the condition being tested. */ | |
6601 | insn = BB_END (bb); | |
6602 | if (path_entry < path_size - 1 | |
e2da9ffe | 6603 | && EDGE_COUNT (bb->succs) == 2 |
932ad4d9 SB |
6604 | && JUMP_P (insn) |
6605 | && single_set (insn) | |
6606 | && any_condjump_p (insn)) | |
6607 | { | |
6608 | basic_block next_bb = ebb_data->path[path_entry + 1].bb; | |
6609 | bool taken = (next_bb == BRANCH_EDGE (bb)->dest); | |
6610 | record_jump_equiv (insn, taken); | |
6611 | } | |
6612 | } | |
7afe21cc | 6613 | |
932ad4d9 | 6614 | gcc_assert (next_qty <= max_qty); |
7afe21cc | 6615 | |
932ad4d9 | 6616 | free (qty_table); |
7afe21cc | 6617 | } |
6fb5fa3c | 6618 | |
7afe21cc | 6619 | \f |
7afe21cc RK |
6620 | /* Perform cse on the instructions of a function. |
6621 | F is the first instruction. | |
6622 | NREGS is one plus the highest pseudo-reg number used in the instruction. | |
6623 | ||
2aac3a01 EB |
6624 | Return 2 if jump optimizations should be redone due to simplifications |
6625 | in conditional jump instructions. | |
6626 | Return 1 if the CFG should be cleaned up because it has been modified. | |
6627 | Return 0 otherwise. */ | |
7afe21cc | 6628 | |
711417cd | 6629 | static int |
20468884 | 6630 | cse_main (rtx_insn *f ATTRIBUTE_UNUSED, int nregs) |
7afe21cc | 6631 | { |
932ad4d9 SB |
6632 | struct cse_basic_block_data ebb_data; |
6633 | basic_block bb; | |
8b1c6fd7 | 6634 | int *rc_order = XNEWVEC (int, last_basic_block_for_fn (cfun)); |
932ad4d9 | 6635 | int i, n_blocks; |
7afe21cc | 6636 | |
afb72432 IE |
6637 | /* CSE doesn't use dominane info but can invalidate it in different ways. |
6638 | For simplicity free dominance info here. */ | |
6639 | free_dominance_info (CDI_DOMINATORS); | |
6640 | ||
6fb5fa3c | 6641 | df_set_flags (DF_LR_RUN_DCE); |
dca3da7a | 6642 | df_note_add_problem (); |
6fb5fa3c DB |
6643 | df_analyze (); |
6644 | df_set_flags (DF_DEFER_INSN_RESCAN); | |
6645 | ||
6646 | reg_scan (get_insns (), max_reg_num ()); | |
bc5e3b54 KH |
6647 | init_cse_reg_info (nregs); |
6648 | ||
932ad4d9 | 6649 | ebb_data.path = XNEWVEC (struct branch_path, |
028d4092 | 6650 | param_max_cse_path_length); |
9bf8cfbf | 6651 | |
2aac3a01 EB |
6652 | cse_cfg_altered = false; |
6653 | cse_jumps_altered = false; | |
6654 | recorded_label_ref = false; | |
932ad4d9 SB |
6655 | ebb_data.path_size = 0; |
6656 | ebb_data.nsets = 0; | |
2f93eea8 | 6657 | rtl_hooks = cse_rtl_hooks; |
7afe21cc RK |
6658 | |
6659 | init_recog (); | |
9ae8ffe7 | 6660 | init_alias_analysis (); |
7afe21cc | 6661 | |
5ed6ace5 | 6662 | reg_eqv_table = XNEWVEC (struct reg_eqv_elem, nregs); |
7afe21cc | 6663 | |
932ad4d9 | 6664 | /* Set up the table of already visited basic blocks. */ |
8b1c6fd7 | 6665 | cse_visited_basic_blocks = sbitmap_alloc (last_basic_block_for_fn (cfun)); |
f61e445a | 6666 | bitmap_clear (cse_visited_basic_blocks); |
7afe21cc | 6667 | |
a7582f7c | 6668 | /* Loop over basic blocks in reverse completion order (RPO), |
932ad4d9 | 6669 | excluding the ENTRY and EXIT blocks. */ |
27511c65 | 6670 | n_blocks = pre_and_rev_post_order_compute (NULL, rc_order, false); |
932ad4d9 SB |
6671 | i = 0; |
6672 | while (i < n_blocks) | |
7afe21cc | 6673 | { |
a7582f7c | 6674 | /* Find the first block in the RPO queue that we have not yet |
932ad4d9 SB |
6675 | processed before. */ |
6676 | do | |
e9a25f70 | 6677 | { |
06e28de2 | 6678 | bb = BASIC_BLOCK_FOR_FN (cfun, rc_order[i++]); |
e9a25f70 | 6679 | } |
d7c028c0 | 6680 | while (bitmap_bit_p (cse_visited_basic_blocks, bb->index) |
932ad4d9 | 6681 | && i < n_blocks); |
7afe21cc | 6682 | |
932ad4d9 SB |
6683 | /* Find all paths starting with BB, and process them. */ |
6684 | while (cse_find_path (bb, &ebb_data, flag_cse_follow_jumps)) | |
7afe21cc | 6685 | { |
932ad4d9 SB |
6686 | /* Pre-scan the path. */ |
6687 | cse_prescan_path (&ebb_data); | |
7afe21cc | 6688 | |
932ad4d9 SB |
6689 | /* If this basic block has no sets, skip it. */ |
6690 | if (ebb_data.nsets == 0) | |
6691 | continue; | |
7afe21cc | 6692 | |
2e226e66 | 6693 | /* Get a reasonable estimate for the maximum number of qty's |
932ad4d9 SB |
6694 | needed for this path. For this, we take the number of sets |
6695 | and multiply that by MAX_RECOG_OPERANDS. */ | |
6696 | max_qty = ebb_data.nsets * MAX_RECOG_OPERANDS; | |
7afe21cc | 6697 | |
932ad4d9 SB |
6698 | /* Dump the path we're about to process. */ |
6699 | if (dump_file) | |
6700 | cse_dump_path (&ebb_data, ebb_data.nsets, dump_file); | |
6a5293dc | 6701 | |
932ad4d9 | 6702 | cse_extended_basic_block (&ebb_data); |
7afe21cc | 6703 | } |
7afe21cc RK |
6704 | } |
6705 | ||
932ad4d9 SB |
6706 | /* Clean up. */ |
6707 | end_alias_analysis (); | |
932ad4d9 SB |
6708 | free (reg_eqv_table); |
6709 | free (ebb_data.path); | |
6710 | sbitmap_free (cse_visited_basic_blocks); | |
27511c65 | 6711 | free (rc_order); |
932ad4d9 | 6712 | rtl_hooks = general_rtl_hooks; |
75c6bd46 | 6713 | |
2aac3a01 EB |
6714 | if (cse_jumps_altered || recorded_label_ref) |
6715 | return 2; | |
6716 | else if (cse_cfg_altered) | |
6717 | return 1; | |
6718 | else | |
6719 | return 0; | |
7afe21cc RK |
6720 | } |
6721 | \f | |
6722 | /* Count the number of times registers are used (not set) in X. | |
6723 | COUNTS is an array in which we accumulate the count, INCR is how much | |
b92ba6ff R |
6724 | we count each register usage. |
6725 | ||
6726 | Don't count a usage of DEST, which is the SET_DEST of a SET which | |
6727 | contains X in its SET_SRC. This is because such a SET does not | |
6728 | modify the liveness of DEST. | |
34161e98 RS |
6729 | DEST is set to pc_rtx for a trapping insn, or for an insn with side effects. |
6730 | We must then count uses of a SET_DEST regardless, because the insn can't be | |
6731 | deleted here. */ | |
7afe21cc RK |
6732 | |
6733 | static void | |
b92ba6ff | 6734 | count_reg_usage (rtx x, int *counts, rtx dest, int incr) |
7afe21cc | 6735 | { |
f1e7c95f | 6736 | enum rtx_code code; |
b17d5d7c | 6737 | rtx note; |
6f7d635c | 6738 | const char *fmt; |
7afe21cc RK |
6739 | int i, j; |
6740 | ||
f1e7c95f RK |
6741 | if (x == 0) |
6742 | return; | |
6743 | ||
6744 | switch (code = GET_CODE (x)) | |
7afe21cc RK |
6745 | { |
6746 | case REG: | |
b92ba6ff R |
6747 | if (x != dest) |
6748 | counts[REGNO (x)] += incr; | |
7afe21cc RK |
6749 | return; |
6750 | ||
6751 | case PC: | |
7afe21cc | 6752 | case CONST: |
d8116890 | 6753 | CASE_CONST_ANY: |
7afe21cc RK |
6754 | case SYMBOL_REF: |
6755 | case LABEL_REF: | |
02e39abc JL |
6756 | return; |
6757 | ||
278a83b2 | 6758 | case CLOBBER: |
02e39abc JL |
6759 | /* If we are clobbering a MEM, mark any registers inside the address |
6760 | as being used. */ | |
3c0cb5de | 6761 | if (MEM_P (XEXP (x, 0))) |
b92ba6ff | 6762 | count_reg_usage (XEXP (XEXP (x, 0), 0), counts, NULL_RTX, incr); |
7afe21cc RK |
6763 | return; |
6764 | ||
6765 | case SET: | |
6766 | /* Unless we are setting a REG, count everything in SET_DEST. */ | |
f8cfc6aa | 6767 | if (!REG_P (SET_DEST (x))) |
b92ba6ff R |
6768 | count_reg_usage (SET_DEST (x), counts, NULL_RTX, incr); |
6769 | count_reg_usage (SET_SRC (x), counts, | |
6770 | dest ? dest : SET_DEST (x), | |
6771 | incr); | |
7afe21cc RK |
6772 | return; |
6773 | ||
b5b8b0ac AO |
6774 | case DEBUG_INSN: |
6775 | return; | |
6776 | ||
f1e7c95f | 6777 | case CALL_INSN: |
7afe21cc RK |
6778 | case INSN: |
6779 | case JUMP_INSN: | |
2da02156 | 6780 | /* We expect dest to be NULL_RTX here. If the insn may throw, |
34161e98 RS |
6781 | or if it cannot be deleted due to side-effects, mark this fact |
6782 | by setting DEST to pc_rtx. */ | |
2da02156 EB |
6783 | if ((!cfun->can_delete_dead_exceptions && !insn_nothrow_p (x)) |
6784 | || side_effects_p (PATTERN (x))) | |
b92ba6ff R |
6785 | dest = pc_rtx; |
6786 | if (code == CALL_INSN) | |
6787 | count_reg_usage (CALL_INSN_FUNCTION_USAGE (x), counts, dest, incr); | |
6788 | count_reg_usage (PATTERN (x), counts, dest, incr); | |
7afe21cc RK |
6789 | |
6790 | /* Things used in a REG_EQUAL note aren't dead since loop may try to | |
6791 | use them. */ | |
6792 | ||
b17d5d7c ZD |
6793 | note = find_reg_equal_equiv_note (x); |
6794 | if (note) | |
839844be R |
6795 | { |
6796 | rtx eqv = XEXP (note, 0); | |
6797 | ||
6798 | if (GET_CODE (eqv) == EXPR_LIST) | |
6799 | /* This REG_EQUAL note describes the result of a function call. | |
6800 | Process all the arguments. */ | |
6801 | do | |
6802 | { | |
b92ba6ff | 6803 | count_reg_usage (XEXP (eqv, 0), counts, dest, incr); |
839844be R |
6804 | eqv = XEXP (eqv, 1); |
6805 | } | |
6806 | while (eqv && GET_CODE (eqv) == EXPR_LIST); | |
6807 | else | |
b92ba6ff | 6808 | count_reg_usage (eqv, counts, dest, incr); |
839844be | 6809 | } |
7afe21cc RK |
6810 | return; |
6811 | ||
ee960939 OH |
6812 | case EXPR_LIST: |
6813 | if (REG_NOTE_KIND (x) == REG_EQUAL | |
6814 | || (REG_NOTE_KIND (x) != REG_NONNEG && GET_CODE (XEXP (x,0)) == USE) | |
6815 | /* FUNCTION_USAGE expression lists may include (CLOBBER (mem /u)), | |
6816 | involving registers in the address. */ | |
17d184e5 | 6817 | || GET_CODE (XEXP (x, 0)) == CLOBBER) |
b92ba6ff | 6818 | count_reg_usage (XEXP (x, 0), counts, NULL_RTX, incr); |
ee960939 | 6819 | |
b92ba6ff | 6820 | count_reg_usage (XEXP (x, 1), counts, NULL_RTX, incr); |
ee960939 OH |
6821 | return; |
6822 | ||
a6c14a64 | 6823 | case ASM_OPERANDS: |
a6c14a64 RH |
6824 | /* Iterate over just the inputs, not the constraints as well. */ |
6825 | for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--) | |
b92ba6ff | 6826 | count_reg_usage (ASM_OPERANDS_INPUT (x, i), counts, dest, incr); |
a6c14a64 RH |
6827 | return; |
6828 | ||
7afe21cc | 6829 | case INSN_LIST: |
f91aec98 | 6830 | case INT_LIST: |
341c100f | 6831 | gcc_unreachable (); |
278a83b2 | 6832 | |
e9a25f70 JL |
6833 | default: |
6834 | break; | |
7afe21cc RK |
6835 | } |
6836 | ||
6837 | fmt = GET_RTX_FORMAT (code); | |
6838 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6839 | { | |
6840 | if (fmt[i] == 'e') | |
b92ba6ff | 6841 | count_reg_usage (XEXP (x, i), counts, dest, incr); |
7afe21cc RK |
6842 | else if (fmt[i] == 'E') |
6843 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
b92ba6ff | 6844 | count_reg_usage (XVECEXP (x, i, j), counts, dest, incr); |
7afe21cc RK |
6845 | } |
6846 | } | |
6847 | \f | |
6699b754 | 6848 | /* Return true if X is a dead register. */ |
b5b8b0ac | 6849 | |
dec7aaab | 6850 | static inline bool |
a5b9bc17 | 6851 | is_dead_reg (const_rtx x, int *counts) |
b5b8b0ac | 6852 | { |
b5b8b0ac AO |
6853 | return (REG_P (x) |
6854 | && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
6855 | && counts[REGNO (x)] == 0); | |
6856 | } | |
6857 | ||
4793dca1 JH |
6858 | /* Return true if set is live. */ |
6859 | static bool | |
bd1cd0d0 | 6860 | set_live_p (rtx set, int *counts) |
4793dca1 | 6861 | { |
4793dca1 | 6862 | if (set_noop_p (set)) |
4793dca1 | 6863 | return false; |
bd1cd0d0 SB |
6864 | |
6865 | if (!is_dead_reg (SET_DEST (set), counts) | |
6866 | || side_effects_p (SET_SRC (set))) | |
4793dca1 | 6867 | return true; |
bd1cd0d0 | 6868 | |
4793dca1 JH |
6869 | return false; |
6870 | } | |
6871 | ||
6872 | /* Return true if insn is live. */ | |
6873 | ||
6874 | static bool | |
20468884 | 6875 | insn_live_p (rtx_insn *insn, int *counts) |
4793dca1 JH |
6876 | { |
6877 | int i; | |
2da02156 | 6878 | if (!cfun->can_delete_dead_exceptions && !insn_nothrow_p (insn)) |
a646f6cc AH |
6879 | return true; |
6880 | else if (GET_CODE (PATTERN (insn)) == SET) | |
bd1cd0d0 | 6881 | return set_live_p (PATTERN (insn), counts); |
4793dca1 | 6882 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) |
0021de69 DB |
6883 | { |
6884 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
6885 | { | |
6886 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
4793dca1 | 6887 | |
0021de69 DB |
6888 | if (GET_CODE (elt) == SET) |
6889 | { | |
bd1cd0d0 | 6890 | if (set_live_p (elt, counts)) |
0021de69 DB |
6891 | return true; |
6892 | } | |
17d184e5 | 6893 | else if (GET_CODE (elt) != CLOBBER && GET_CODE (elt) != USE) |
0021de69 DB |
6894 | return true; |
6895 | } | |
6896 | return false; | |
6897 | } | |
b5b8b0ac AO |
6898 | else if (DEBUG_INSN_P (insn)) |
6899 | { | |
96a95ac1 AO |
6900 | if (DEBUG_MARKER_INSN_P (insn)) |
6901 | return true; | |
6902 | ||
675ac882 RB |
6903 | if (DEBUG_BIND_INSN_P (insn) |
6904 | && TREE_VISITED (INSN_VAR_LOCATION_DECL (insn))) | |
6905 | return false; | |
b5b8b0ac | 6906 | |
b5b8b0ac AO |
6907 | return true; |
6908 | } | |
4793dca1 JH |
6909 | else |
6910 | return true; | |
6911 | } | |
6912 | ||
6699b754 JJ |
6913 | /* Count the number of stores into pseudo. Callback for note_stores. */ |
6914 | ||
6915 | static void | |
6916 | count_stores (rtx x, const_rtx set ATTRIBUTE_UNUSED, void *data) | |
6917 | { | |
6918 | int *counts = (int *) data; | |
6919 | if (REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER) | |
6920 | counts[REGNO (x)]++; | |
6921 | } | |
6922 | ||
a5b9bc17 RS |
6923 | /* Return if DEBUG_INSN pattern PAT needs to be reset because some dead |
6924 | pseudo doesn't have a replacement. COUNTS[X] is zero if register X | |
6925 | is dead and REPLACEMENTS[X] is null if it has no replacemenet. | |
6926 | Set *SEEN_REPL to true if we see a dead register that does have | |
6927 | a replacement. */ | |
6699b754 | 6928 | |
a5b9bc17 RS |
6929 | static bool |
6930 | is_dead_debug_insn (const_rtx pat, int *counts, rtx *replacements, | |
6931 | bool *seen_repl) | |
6699b754 | 6932 | { |
a5b9bc17 RS |
6933 | subrtx_iterator::array_type array; |
6934 | FOR_EACH_SUBRTX (iter, array, pat, NONCONST) | |
6699b754 | 6935 | { |
a5b9bc17 RS |
6936 | const_rtx x = *iter; |
6937 | if (is_dead_reg (x, counts)) | |
6938 | { | |
6939 | if (replacements && replacements[REGNO (x)] != NULL_RTX) | |
6940 | *seen_repl = true; | |
6941 | else | |
6942 | return true; | |
6943 | } | |
6699b754 | 6944 | } |
a5b9bc17 | 6945 | return false; |
6699b754 JJ |
6946 | } |
6947 | ||
6948 | /* Replace a dead pseudo in a DEBUG_INSN with replacement DEBUG_EXPR. | |
6949 | Callback for simplify_replace_fn_rtx. */ | |
6950 | ||
6951 | static rtx | |
6952 | replace_dead_reg (rtx x, const_rtx old_rtx ATTRIBUTE_UNUSED, void *data) | |
6953 | { | |
6954 | rtx *replacements = (rtx *) data; | |
6955 | ||
6956 | if (REG_P (x) | |
6957 | && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
6958 | && replacements[REGNO (x)] != NULL_RTX) | |
6959 | { | |
6960 | if (GET_MODE (x) == GET_MODE (replacements[REGNO (x)])) | |
6961 | return replacements[REGNO (x)]; | |
6962 | return lowpart_subreg (GET_MODE (x), replacements[REGNO (x)], | |
6963 | GET_MODE (replacements[REGNO (x)])); | |
6964 | } | |
6965 | return NULL_RTX; | |
6966 | } | |
6967 | ||
7afe21cc RK |
6968 | /* Scan all the insns and delete any that are dead; i.e., they store a register |
6969 | that is never used or they copy a register to itself. | |
6970 | ||
c6a26dc4 JL |
6971 | This is used to remove insns made obviously dead by cse, loop or other |
6972 | optimizations. It improves the heuristics in loop since it won't try to | |
6973 | move dead invariants out of loops or make givs for dead quantities. The | |
6974 | remaining passes of the compilation are also sped up. */ | |
7afe21cc | 6975 | |
3dec4024 | 6976 | int |
169d13f5 | 6977 | delete_trivially_dead_insns (rtx_insn *insns, int nreg) |
7afe21cc | 6978 | { |
4da896b2 | 6979 | int *counts; |
169d13f5 | 6980 | rtx_insn *insn, *prev; |
6699b754 | 6981 | rtx *replacements = NULL; |
65e9fa10 | 6982 | int ndead = 0; |
7afe21cc | 6983 | |
3dec4024 | 6984 | timevar_push (TV_DELETE_TRIVIALLY_DEAD); |
7afe21cc | 6985 | /* First count the number of times each register is used. */ |
36f52e8f | 6986 | if (MAY_HAVE_DEBUG_BIND_INSNS) |
6699b754 JJ |
6987 | { |
6988 | counts = XCNEWVEC (int, nreg * 3); | |
6989 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
36f52e8f | 6990 | if (DEBUG_BIND_INSN_P (insn)) |
675ac882 RB |
6991 | { |
6992 | count_reg_usage (INSN_VAR_LOCATION_LOC (insn), counts + nreg, | |
6993 | NULL_RTX, 1); | |
6994 | TREE_VISITED (INSN_VAR_LOCATION_DECL (insn)) = 0; | |
6995 | } | |
6699b754 JJ |
6996 | else if (INSN_P (insn)) |
6997 | { | |
6998 | count_reg_usage (insn, counts, NULL_RTX, 1); | |
e8448ba5 | 6999 | note_stores (insn, count_stores, counts + nreg * 2); |
6699b754 JJ |
7000 | } |
7001 | /* If there can be debug insns, COUNTS are 3 consecutive arrays. | |
7002 | First one counts how many times each pseudo is used outside | |
7003 | of debug insns, second counts how many times each pseudo is | |
7004 | used in debug insns and third counts how many times a pseudo | |
7005 | is stored. */ | |
7006 | } | |
7007 | else | |
7008 | { | |
7009 | counts = XCNEWVEC (int, nreg); | |
7010 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
7011 | if (INSN_P (insn)) | |
7012 | count_reg_usage (insn, counts, NULL_RTX, 1); | |
7013 | /* If no debug insns can be present, COUNTS is just an array | |
7014 | which counts how many times each pseudo is used. */ | |
7015 | } | |
56873e13 ES |
7016 | /* Pseudo PIC register should be considered as used due to possible |
7017 | new usages generated. */ | |
7018 | if (!reload_completed | |
7019 | && pic_offset_table_rtx | |
7020 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
7021 | counts[REGNO (pic_offset_table_rtx)]++; | |
65e9fa10 KH |
7022 | /* Go from the last insn to the first and delete insns that only set unused |
7023 | registers or copy a register to itself. As we delete an insn, remove | |
7024 | usage counts for registers it uses. | |
0cedb36c | 7025 | |
65e9fa10 KH |
7026 | The first jump optimization pass may leave a real insn as the last |
7027 | insn in the function. We must not skip that insn or we may end | |
6699b754 JJ |
7028 | up deleting code that is not really dead. |
7029 | ||
7030 | If some otherwise unused register is only used in DEBUG_INSNs, | |
7031 | try to create a DEBUG_EXPR temporary and emit a DEBUG_INSN before | |
7032 | the setter. Then go through DEBUG_INSNs and if a DEBUG_EXPR | |
7033 | has been created for the unused register, replace it with | |
7034 | the DEBUG_EXPR, otherwise reset the DEBUG_INSN. */ | |
675ac882 | 7035 | auto_vec<tree, 32> later_debug_set_vars; |
03ce14db | 7036 | for (insn = get_last_insn (); insn; insn = prev) |
65e9fa10 KH |
7037 | { |
7038 | int live_insn = 0; | |
7afe21cc | 7039 | |
03ce14db KH |
7040 | prev = PREV_INSN (insn); |
7041 | if (!INSN_P (insn)) | |
7042 | continue; | |
7afe21cc | 7043 | |
4a8cae83 | 7044 | live_insn = insn_live_p (insn, counts); |
7afe21cc | 7045 | |
65e9fa10 KH |
7046 | /* If this is a dead insn, delete it and show registers in it aren't |
7047 | being used. */ | |
7afe21cc | 7048 | |
6fb5fa3c | 7049 | if (! live_insn && dbg_cnt (delete_trivial_dead)) |
65e9fa10 | 7050 | { |
6699b754 | 7051 | if (DEBUG_INSN_P (insn)) |
36f52e8f AO |
7052 | { |
7053 | if (DEBUG_BIND_INSN_P (insn)) | |
7054 | count_reg_usage (INSN_VAR_LOCATION_LOC (insn), counts + nreg, | |
7055 | NULL_RTX, -1); | |
7056 | } | |
6699b754 JJ |
7057 | else |
7058 | { | |
7059 | rtx set; | |
36f52e8f | 7060 | if (MAY_HAVE_DEBUG_BIND_INSNS |
6699b754 JJ |
7061 | && (set = single_set (insn)) != NULL_RTX |
7062 | && is_dead_reg (SET_DEST (set), counts) | |
7063 | /* Used at least once in some DEBUG_INSN. */ | |
7064 | && counts[REGNO (SET_DEST (set)) + nreg] > 0 | |
7065 | /* And set exactly once. */ | |
7066 | && counts[REGNO (SET_DEST (set)) + nreg * 2] == 1 | |
7067 | && !side_effects_p (SET_SRC (set)) | |
7068 | && asm_noperands (PATTERN (insn)) < 0) | |
7069 | { | |
b2908ba6 DM |
7070 | rtx dval, bind_var_loc; |
7071 | rtx_insn *bind; | |
6699b754 JJ |
7072 | |
7073 | /* Create DEBUG_EXPR (and DEBUG_EXPR_DECL). */ | |
7074 | dval = make_debug_expr_from_rtl (SET_DEST (set)); | |
7075 | ||
7076 | /* Emit a debug bind insn before the insn in which | |
7077 | reg dies. */ | |
b2908ba6 DM |
7078 | bind_var_loc = |
7079 | gen_rtx_VAR_LOCATION (GET_MODE (SET_DEST (set)), | |
7080 | DEBUG_EXPR_TREE_DECL (dval), | |
7081 | SET_SRC (set), | |
7082 | VAR_INIT_STATUS_INITIALIZED); | |
7083 | count_reg_usage (bind_var_loc, counts + nreg, NULL_RTX, 1); | |
7084 | ||
7085 | bind = emit_debug_insn_before (bind_var_loc, insn); | |
6699b754 JJ |
7086 | df_insn_rescan (bind); |
7087 | ||
7088 | if (replacements == NULL) | |
7089 | replacements = XCNEWVEC (rtx, nreg); | |
7090 | replacements[REGNO (SET_DEST (set))] = dval; | |
7091 | } | |
7092 | ||
7093 | count_reg_usage (insn, counts, NULL_RTX, -1); | |
7094 | ndead++; | |
7095 | } | |
98ccd1d7 | 7096 | cse_cfg_altered |= delete_insn_and_edges (insn); |
65e9fa10 | 7097 | } |
675ac882 RB |
7098 | else |
7099 | { | |
7100 | if (!DEBUG_INSN_P (insn) || DEBUG_MARKER_INSN_P (insn)) | |
7101 | { | |
7102 | for (tree var : later_debug_set_vars) | |
7103 | TREE_VISITED (var) = 0; | |
7104 | later_debug_set_vars.truncate (0); | |
7105 | } | |
7106 | else if (DEBUG_BIND_INSN_P (insn) | |
7107 | && !TREE_VISITED (INSN_VAR_LOCATION_DECL (insn))) | |
7108 | { | |
7109 | later_debug_set_vars.safe_push (INSN_VAR_LOCATION_DECL (insn)); | |
7110 | TREE_VISITED (INSN_VAR_LOCATION_DECL (insn)) = 1; | |
7111 | } | |
7112 | } | |
68252e27 | 7113 | } |
4da896b2 | 7114 | |
36f52e8f | 7115 | if (MAY_HAVE_DEBUG_BIND_INSNS) |
6699b754 | 7116 | { |
6699b754 | 7117 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) |
36f52e8f | 7118 | if (DEBUG_BIND_INSN_P (insn)) |
6699b754 JJ |
7119 | { |
7120 | /* If this debug insn references a dead register that wasn't replaced | |
7121 | with an DEBUG_EXPR, reset the DEBUG_INSN. */ | |
a5b9bc17 RS |
7122 | bool seen_repl = false; |
7123 | if (is_dead_debug_insn (INSN_VAR_LOCATION_LOC (insn), | |
7124 | counts, replacements, &seen_repl)) | |
6699b754 JJ |
7125 | { |
7126 | INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC (); | |
7127 | df_insn_rescan (insn); | |
7128 | } | |
a5b9bc17 | 7129 | else if (seen_repl) |
6699b754 JJ |
7130 | { |
7131 | INSN_VAR_LOCATION_LOC (insn) | |
7132 | = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn), | |
7133 | NULL_RTX, replace_dead_reg, | |
7134 | replacements); | |
7135 | df_insn_rescan (insn); | |
7136 | } | |
7137 | } | |
04695783 | 7138 | free (replacements); |
6699b754 JJ |
7139 | } |
7140 | ||
c263766c | 7141 | if (dump_file && ndead) |
65e9fa10 KH |
7142 | fprintf (dump_file, "Deleted %i trivially dead insns\n", |
7143 | ndead); | |
4da896b2 MM |
7144 | /* Clean up. */ |
7145 | free (counts); | |
3dec4024 JH |
7146 | timevar_pop (TV_DELETE_TRIVIALLY_DEAD); |
7147 | return ndead; | |
7afe21cc | 7148 | } |
e129d93a | 7149 | |
a9052a40 RS |
7150 | /* If LOC contains references to NEWREG in a different mode, change them |
7151 | to use NEWREG instead. */ | |
e129d93a | 7152 | |
a9052a40 RS |
7153 | static void |
7154 | cse_change_cc_mode (subrtx_ptr_iterator::array_type &array, | |
88bdcd3d | 7155 | rtx *loc, rtx_insn *insn, rtx newreg) |
e129d93a | 7156 | { |
a9052a40 | 7157 | FOR_EACH_SUBRTX_PTR (iter, array, loc, NONCONST) |
e129d93a | 7158 | { |
a9052a40 RS |
7159 | rtx *loc = *iter; |
7160 | rtx x = *loc; | |
7161 | if (x | |
7162 | && REG_P (x) | |
7163 | && REGNO (x) == REGNO (newreg) | |
7164 | && GET_MODE (x) != GET_MODE (newreg)) | |
7165 | { | |
7166 | validate_change (insn, loc, newreg, 1); | |
7167 | iter.skip_subrtxes (); | |
7168 | } | |
e129d93a | 7169 | } |
e129d93a ILT |
7170 | } |
7171 | ||
fc188d37 AK |
7172 | /* Change the mode of any reference to the register REGNO (NEWREG) to |
7173 | GET_MODE (NEWREG) in INSN. */ | |
7174 | ||
7175 | static void | |
20468884 | 7176 | cse_change_cc_mode_insn (rtx_insn *insn, rtx newreg) |
fc188d37 | 7177 | { |
fc188d37 AK |
7178 | int success; |
7179 | ||
7180 | if (!INSN_P (insn)) | |
7181 | return; | |
7182 | ||
a9052a40 RS |
7183 | subrtx_ptr_iterator::array_type array; |
7184 | cse_change_cc_mode (array, &PATTERN (insn), insn, newreg); | |
7185 | cse_change_cc_mode (array, ®_NOTES (insn), insn, newreg); | |
b8698a0f | 7186 | |
fc188d37 AK |
7187 | /* If the following assertion was triggered, there is most probably |
7188 | something wrong with the cc_modes_compatible back end function. | |
7189 | CC modes only can be considered compatible if the insn - with the mode | |
7190 | replaced by any of the compatible modes - can still be recognized. */ | |
7191 | success = apply_change_group (); | |
7192 | gcc_assert (success); | |
7193 | } | |
7194 | ||
e129d93a ILT |
7195 | /* Change the mode of any reference to the register REGNO (NEWREG) to |
7196 | GET_MODE (NEWREG), starting at START. Stop before END. Stop at | |
2e802a6f | 7197 | any instruction which modifies NEWREG. */ |
e129d93a ILT |
7198 | |
7199 | static void | |
20468884 | 7200 | cse_change_cc_mode_insns (rtx_insn *start, rtx_insn *end, rtx newreg) |
e129d93a | 7201 | { |
20468884 | 7202 | rtx_insn *insn; |
e129d93a ILT |
7203 | |
7204 | for (insn = start; insn != end; insn = NEXT_INSN (insn)) | |
7205 | { | |
7206 | if (! INSN_P (insn)) | |
7207 | continue; | |
7208 | ||
2e802a6f | 7209 | if (reg_set_p (newreg, insn)) |
e129d93a ILT |
7210 | return; |
7211 | ||
fc188d37 | 7212 | cse_change_cc_mode_insn (insn, newreg); |
e129d93a ILT |
7213 | } |
7214 | } | |
7215 | ||
7216 | /* BB is a basic block which finishes with CC_REG as a condition code | |
7217 | register which is set to CC_SRC. Look through the successors of BB | |
7218 | to find blocks which have a single predecessor (i.e., this one), | |
7219 | and look through those blocks for an assignment to CC_REG which is | |
7220 | equivalent to CC_SRC. CAN_CHANGE_MODE indicates whether we are | |
7221 | permitted to change the mode of CC_SRC to a compatible mode. This | |
7222 | returns VOIDmode if no equivalent assignments were found. | |
7223 | Otherwise it returns the mode which CC_SRC should wind up with. | |
31e9ebaf JJ |
7224 | ORIG_BB should be the same as BB in the outermost cse_cc_succs call, |
7225 | but is passed unmodified down to recursive calls in order to prevent | |
7226 | endless recursion. | |
e129d93a ILT |
7227 | |
7228 | The main complexity in this function is handling the mode issues. | |
7229 | We may have more than one duplicate which we can eliminate, and we | |
7230 | try to find a mode which will work for multiple duplicates. */ | |
7231 | ||
ef4bddc2 | 7232 | static machine_mode |
31e9ebaf JJ |
7233 | cse_cc_succs (basic_block bb, basic_block orig_bb, rtx cc_reg, rtx cc_src, |
7234 | bool can_change_mode) | |
e129d93a ILT |
7235 | { |
7236 | bool found_equiv; | |
ef4bddc2 | 7237 | machine_mode mode; |
e129d93a ILT |
7238 | unsigned int insn_count; |
7239 | edge e; | |
20468884 | 7240 | rtx_insn *insns[2]; |
ef4bddc2 | 7241 | machine_mode modes[2]; |
20468884 | 7242 | rtx_insn *last_insns[2]; |
e129d93a ILT |
7243 | unsigned int i; |
7244 | rtx newreg; | |
628f6a4e | 7245 | edge_iterator ei; |
e129d93a ILT |
7246 | |
7247 | /* We expect to have two successors. Look at both before picking | |
7248 | the final mode for the comparison. If we have more successors | |
7249 | (i.e., some sort of table jump, although that seems unlikely), | |
7250 | then we require all beyond the first two to use the same | |
7251 | mode. */ | |
7252 | ||
7253 | found_equiv = false; | |
7254 | mode = GET_MODE (cc_src); | |
7255 | insn_count = 0; | |
628f6a4e | 7256 | FOR_EACH_EDGE (e, ei, bb->succs) |
e129d93a | 7257 | { |
20468884 DM |
7258 | rtx_insn *insn; |
7259 | rtx_insn *end; | |
e129d93a ILT |
7260 | |
7261 | if (e->flags & EDGE_COMPLEX) | |
7262 | continue; | |
7263 | ||
628f6a4e | 7264 | if (EDGE_COUNT (e->dest->preds) != 1 |
fefa31b5 | 7265 | || e->dest == EXIT_BLOCK_PTR_FOR_FN (cfun) |
31e9ebaf JJ |
7266 | /* Avoid endless recursion on unreachable blocks. */ |
7267 | || e->dest == orig_bb) | |
e129d93a ILT |
7268 | continue; |
7269 | ||
7270 | end = NEXT_INSN (BB_END (e->dest)); | |
7271 | for (insn = BB_HEAD (e->dest); insn != end; insn = NEXT_INSN (insn)) | |
7272 | { | |
7273 | rtx set; | |
7274 | ||
7275 | if (! INSN_P (insn)) | |
7276 | continue; | |
7277 | ||
7278 | /* If CC_SRC is modified, we have to stop looking for | |
7279 | something which uses it. */ | |
7280 | if (modified_in_p (cc_src, insn)) | |
7281 | break; | |
7282 | ||
7283 | /* Check whether INSN sets CC_REG to CC_SRC. */ | |
7284 | set = single_set (insn); | |
7285 | if (set | |
f8cfc6aa | 7286 | && REG_P (SET_DEST (set)) |
e129d93a ILT |
7287 | && REGNO (SET_DEST (set)) == REGNO (cc_reg)) |
7288 | { | |
7289 | bool found; | |
ef4bddc2 RS |
7290 | machine_mode set_mode; |
7291 | machine_mode comp_mode; | |
e129d93a ILT |
7292 | |
7293 | found = false; | |
7294 | set_mode = GET_MODE (SET_SRC (set)); | |
7295 | comp_mode = set_mode; | |
7296 | if (rtx_equal_p (cc_src, SET_SRC (set))) | |
7297 | found = true; | |
7298 | else if (GET_CODE (cc_src) == COMPARE | |
7299 | && GET_CODE (SET_SRC (set)) == COMPARE | |
1f44254c | 7300 | && mode != set_mode |
e129d93a ILT |
7301 | && rtx_equal_p (XEXP (cc_src, 0), |
7302 | XEXP (SET_SRC (set), 0)) | |
7303 | && rtx_equal_p (XEXP (cc_src, 1), | |
7304 | XEXP (SET_SRC (set), 1))) | |
b8698a0f | 7305 | |
e129d93a | 7306 | { |
5fd9b178 | 7307 | comp_mode = targetm.cc_modes_compatible (mode, set_mode); |
e129d93a ILT |
7308 | if (comp_mode != VOIDmode |
7309 | && (can_change_mode || comp_mode == mode)) | |
7310 | found = true; | |
7311 | } | |
7312 | ||
7313 | if (found) | |
7314 | { | |
7315 | found_equiv = true; | |
1f44254c | 7316 | if (insn_count < ARRAY_SIZE (insns)) |
e129d93a ILT |
7317 | { |
7318 | insns[insn_count] = insn; | |
7319 | modes[insn_count] = set_mode; | |
7320 | last_insns[insn_count] = end; | |
7321 | ++insn_count; | |
7322 | ||
1f44254c ILT |
7323 | if (mode != comp_mode) |
7324 | { | |
341c100f | 7325 | gcc_assert (can_change_mode); |
1f44254c | 7326 | mode = comp_mode; |
fc188d37 AK |
7327 | |
7328 | /* The modified insn will be re-recognized later. */ | |
1f44254c ILT |
7329 | PUT_MODE (cc_src, mode); |
7330 | } | |
e129d93a ILT |
7331 | } |
7332 | else | |
7333 | { | |
7334 | if (set_mode != mode) | |
1f44254c ILT |
7335 | { |
7336 | /* We found a matching expression in the | |
7337 | wrong mode, but we don't have room to | |
7338 | store it in the array. Punt. This case | |
7339 | should be rare. */ | |
7340 | break; | |
7341 | } | |
e129d93a ILT |
7342 | /* INSN sets CC_REG to a value equal to CC_SRC |
7343 | with the right mode. We can simply delete | |
7344 | it. */ | |
7345 | delete_insn (insn); | |
7346 | } | |
7347 | ||
7348 | /* We found an instruction to delete. Keep looking, | |
7349 | in the hopes of finding a three-way jump. */ | |
7350 | continue; | |
7351 | } | |
7352 | ||
7353 | /* We found an instruction which sets the condition | |
7354 | code, so don't look any farther. */ | |
7355 | break; | |
7356 | } | |
7357 | ||
7358 | /* If INSN sets CC_REG in some other way, don't look any | |
7359 | farther. */ | |
7360 | if (reg_set_p (cc_reg, insn)) | |
7361 | break; | |
7362 | } | |
7363 | ||
7364 | /* If we fell off the bottom of the block, we can keep looking | |
7365 | through successors. We pass CAN_CHANGE_MODE as false because | |
7366 | we aren't prepared to handle compatibility between the | |
7367 | further blocks and this block. */ | |
7368 | if (insn == end) | |
7369 | { | |
ef4bddc2 | 7370 | machine_mode submode; |
1f44254c | 7371 | |
31e9ebaf | 7372 | submode = cse_cc_succs (e->dest, orig_bb, cc_reg, cc_src, false); |
1f44254c ILT |
7373 | if (submode != VOIDmode) |
7374 | { | |
341c100f | 7375 | gcc_assert (submode == mode); |
1f44254c ILT |
7376 | found_equiv = true; |
7377 | can_change_mode = false; | |
7378 | } | |
e129d93a ILT |
7379 | } |
7380 | } | |
7381 | ||
7382 | if (! found_equiv) | |
7383 | return VOIDmode; | |
7384 | ||
7385 | /* Now INSN_COUNT is the number of instructions we found which set | |
7386 | CC_REG to a value equivalent to CC_SRC. The instructions are in | |
7387 | INSNS. The modes used by those instructions are in MODES. */ | |
7388 | ||
7389 | newreg = NULL_RTX; | |
7390 | for (i = 0; i < insn_count; ++i) | |
7391 | { | |
7392 | if (modes[i] != mode) | |
7393 | { | |
7394 | /* We need to change the mode of CC_REG in INSNS[i] and | |
7395 | subsequent instructions. */ | |
7396 | if (! newreg) | |
7397 | { | |
7398 | if (GET_MODE (cc_reg) == mode) | |
7399 | newreg = cc_reg; | |
7400 | else | |
7401 | newreg = gen_rtx_REG (mode, REGNO (cc_reg)); | |
7402 | } | |
7403 | cse_change_cc_mode_insns (NEXT_INSN (insns[i]), last_insns[i], | |
7404 | newreg); | |
7405 | } | |
7406 | ||
98ccd1d7 | 7407 | cse_cfg_altered |= delete_insn_and_edges (insns[i]); |
e129d93a ILT |
7408 | } |
7409 | ||
7410 | return mode; | |
7411 | } | |
7412 | ||
7413 | /* If we have a fixed condition code register (or two), walk through | |
7414 | the instructions and try to eliminate duplicate assignments. */ | |
7415 | ||
cab2264d | 7416 | static void |
e129d93a ILT |
7417 | cse_condition_code_reg (void) |
7418 | { | |
7419 | unsigned int cc_regno_1; | |
7420 | unsigned int cc_regno_2; | |
7421 | rtx cc_reg_1; | |
7422 | rtx cc_reg_2; | |
7423 | basic_block bb; | |
7424 | ||
5fd9b178 | 7425 | if (! targetm.fixed_condition_code_regs (&cc_regno_1, &cc_regno_2)) |
e129d93a ILT |
7426 | return; |
7427 | ||
7428 | cc_reg_1 = gen_rtx_REG (CCmode, cc_regno_1); | |
7429 | if (cc_regno_2 != INVALID_REGNUM) | |
7430 | cc_reg_2 = gen_rtx_REG (CCmode, cc_regno_2); | |
7431 | else | |
7432 | cc_reg_2 = NULL_RTX; | |
7433 | ||
11cd3bed | 7434 | FOR_EACH_BB_FN (bb, cfun) |
e129d93a | 7435 | { |
20468884 | 7436 | rtx_insn *last_insn; |
e129d93a | 7437 | rtx cc_reg; |
20468884 DM |
7438 | rtx_insn *insn; |
7439 | rtx_insn *cc_src_insn; | |
e129d93a | 7440 | rtx cc_src; |
ef4bddc2 RS |
7441 | machine_mode mode; |
7442 | machine_mode orig_mode; | |
e129d93a ILT |
7443 | |
7444 | /* Look for blocks which end with a conditional jump based on a | |
7445 | condition code register. Then look for the instruction which | |
7446 | sets the condition code register. Then look through the | |
7447 | successor blocks for instructions which set the condition | |
7448 | code register to the same value. There are other possible | |
7449 | uses of the condition code register, but these are by far the | |
7450 | most common and the ones which we are most likely to be able | |
7451 | to optimize. */ | |
7452 | ||
7453 | last_insn = BB_END (bb); | |
4b4bf941 | 7454 | if (!JUMP_P (last_insn)) |
e129d93a ILT |
7455 | continue; |
7456 | ||
7457 | if (reg_referenced_p (cc_reg_1, PATTERN (last_insn))) | |
7458 | cc_reg = cc_reg_1; | |
7459 | else if (cc_reg_2 && reg_referenced_p (cc_reg_2, PATTERN (last_insn))) | |
7460 | cc_reg = cc_reg_2; | |
7461 | else | |
7462 | continue; | |
7463 | ||
20468884 | 7464 | cc_src_insn = NULL; |
e129d93a ILT |
7465 | cc_src = NULL_RTX; |
7466 | for (insn = PREV_INSN (last_insn); | |
7467 | insn && insn != PREV_INSN (BB_HEAD (bb)); | |
7468 | insn = PREV_INSN (insn)) | |
7469 | { | |
7470 | rtx set; | |
7471 | ||
7472 | if (! INSN_P (insn)) | |
7473 | continue; | |
7474 | set = single_set (insn); | |
7475 | if (set | |
f8cfc6aa | 7476 | && REG_P (SET_DEST (set)) |
e129d93a ILT |
7477 | && REGNO (SET_DEST (set)) == REGNO (cc_reg)) |
7478 | { | |
7479 | cc_src_insn = insn; | |
7480 | cc_src = SET_SRC (set); | |
7481 | break; | |
7482 | } | |
7483 | else if (reg_set_p (cc_reg, insn)) | |
7484 | break; | |
7485 | } | |
7486 | ||
7487 | if (! cc_src_insn) | |
7488 | continue; | |
7489 | ||
7490 | if (modified_between_p (cc_src, cc_src_insn, NEXT_INSN (last_insn))) | |
7491 | continue; | |
7492 | ||
7493 | /* Now CC_REG is a condition code register used for a | |
7494 | conditional jump at the end of the block, and CC_SRC, in | |
7495 | CC_SRC_INSN, is the value to which that condition code | |
7496 | register is set, and CC_SRC is still meaningful at the end of | |
7497 | the basic block. */ | |
7498 | ||
1f44254c | 7499 | orig_mode = GET_MODE (cc_src); |
31e9ebaf | 7500 | mode = cse_cc_succs (bb, bb, cc_reg, cc_src, true); |
1f44254c | 7501 | if (mode != VOIDmode) |
e129d93a | 7502 | { |
341c100f | 7503 | gcc_assert (mode == GET_MODE (cc_src)); |
1f44254c | 7504 | if (mode != orig_mode) |
2e802a6f KH |
7505 | { |
7506 | rtx newreg = gen_rtx_REG (mode, REGNO (cc_reg)); | |
7507 | ||
fc188d37 | 7508 | cse_change_cc_mode_insn (cc_src_insn, newreg); |
2e802a6f KH |
7509 | |
7510 | /* Do the same in the following insns that use the | |
7511 | current value of CC_REG within BB. */ | |
7512 | cse_change_cc_mode_insns (NEXT_INSN (cc_src_insn), | |
7513 | NEXT_INSN (last_insn), | |
7514 | newreg); | |
7515 | } | |
e129d93a ILT |
7516 | } |
7517 | } | |
7518 | } | |
ef330312 PB |
7519 | \f |
7520 | ||
7521 | /* Perform common subexpression elimination. Nonzero value from | |
7522 | `cse_main' means that jumps were simplified and some code may now | |
7523 | be unreachable, so do jump optimization again. */ | |
c2924966 | 7524 | static unsigned int |
ef330312 PB |
7525 | rest_of_handle_cse (void) |
7526 | { | |
7527 | int tem; | |
6fb5fa3c | 7528 | |
ef330312 | 7529 | if (dump_file) |
5b4fdb20 | 7530 | dump_flow_info (dump_file, dump_flags); |
ef330312 | 7531 | |
10d22567 | 7532 | tem = cse_main (get_insns (), max_reg_num ()); |
ef330312 PB |
7533 | |
7534 | /* If we are not running more CSE passes, then we are no longer | |
7535 | expecting CSE to be run. But always rerun it in a cheap mode. */ | |
7536 | cse_not_expected = !flag_rerun_cse_after_loop && !flag_gcse; | |
7537 | ||
2aac3a01 EB |
7538 | if (tem == 2) |
7539 | { | |
7540 | timevar_push (TV_JUMP); | |
7541 | rebuild_jump_labels (get_insns ()); | |
da7674f6 | 7542 | cse_cfg_altered |= cleanup_cfg (CLEANUP_CFG_CHANGED); |
2aac3a01 EB |
7543 | timevar_pop (TV_JUMP); |
7544 | } | |
7545 | else if (tem == 1 || optimize > 1) | |
da7674f6 | 7546 | cse_cfg_altered |= cleanup_cfg (0); |
932ad4d9 | 7547 | |
c2924966 | 7548 | return 0; |
ef330312 PB |
7549 | } |
7550 | ||
27a4cd48 DM |
7551 | namespace { |
7552 | ||
7553 | const pass_data pass_data_cse = | |
ef330312 | 7554 | { |
27a4cd48 DM |
7555 | RTL_PASS, /* type */ |
7556 | "cse1", /* name */ | |
7557 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
7558 | TV_CSE, /* tv_id */ |
7559 | 0, /* properties_required */ | |
7560 | 0, /* properties_provided */ | |
7561 | 0, /* properties_destroyed */ | |
7562 | 0, /* todo_flags_start */ | |
3bea341f | 7563 | TODO_df_finish, /* todo_flags_finish */ |
ef330312 PB |
7564 | }; |
7565 | ||
27a4cd48 DM |
7566 | class pass_cse : public rtl_opt_pass |
7567 | { | |
7568 | public: | |
c3284718 RS |
7569 | pass_cse (gcc::context *ctxt) |
7570 | : rtl_opt_pass (pass_data_cse, ctxt) | |
27a4cd48 DM |
7571 | {} |
7572 | ||
7573 | /* opt_pass methods: */ | |
725793af DM |
7574 | bool gate (function *) final override { return optimize > 0; } |
7575 | unsigned int execute (function *) final override | |
7576 | { | |
7577 | return rest_of_handle_cse (); | |
7578 | } | |
27a4cd48 DM |
7579 | |
7580 | }; // class pass_cse | |
7581 | ||
7582 | } // anon namespace | |
7583 | ||
7584 | rtl_opt_pass * | |
7585 | make_pass_cse (gcc::context *ctxt) | |
7586 | { | |
7587 | return new pass_cse (ctxt); | |
7588 | } | |
7589 | ||
ef330312 | 7590 | |
ef330312 | 7591 | /* Run second CSE pass after loop optimizations. */ |
c2924966 | 7592 | static unsigned int |
ef330312 PB |
7593 | rest_of_handle_cse2 (void) |
7594 | { | |
7595 | int tem; | |
7596 | ||
7597 | if (dump_file) | |
5b4fdb20 | 7598 | dump_flow_info (dump_file, dump_flags); |
ef330312 | 7599 | |
10d22567 | 7600 | tem = cse_main (get_insns (), max_reg_num ()); |
ef330312 PB |
7601 | |
7602 | /* Run a pass to eliminate duplicated assignments to condition code | |
7603 | registers. We have to run this after bypass_jumps, because it | |
7604 | makes it harder for that pass to determine whether a jump can be | |
7605 | bypassed safely. */ | |
7606 | cse_condition_code_reg (); | |
7607 | ||
ef330312 PB |
7608 | delete_trivially_dead_insns (get_insns (), max_reg_num ()); |
7609 | ||
2aac3a01 | 7610 | if (tem == 2) |
ef330312 PB |
7611 | { |
7612 | timevar_push (TV_JUMP); | |
7613 | rebuild_jump_labels (get_insns ()); | |
da7674f6 | 7614 | cse_cfg_altered |= cleanup_cfg (CLEANUP_CFG_CHANGED); |
ef330312 PB |
7615 | timevar_pop (TV_JUMP); |
7616 | } | |
ba585b91 | 7617 | else if (tem == 1 || cse_cfg_altered) |
da7674f6 | 7618 | cse_cfg_altered |= cleanup_cfg (0); |
2aac3a01 | 7619 | |
ef330312 | 7620 | cse_not_expected = 1; |
c2924966 | 7621 | return 0; |
ef330312 PB |
7622 | } |
7623 | ||
7624 | ||
27a4cd48 DM |
7625 | namespace { |
7626 | ||
7627 | const pass_data pass_data_cse2 = | |
ef330312 | 7628 | { |
27a4cd48 DM |
7629 | RTL_PASS, /* type */ |
7630 | "cse2", /* name */ | |
7631 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
7632 | TV_CSE2, /* tv_id */ |
7633 | 0, /* properties_required */ | |
7634 | 0, /* properties_provided */ | |
7635 | 0, /* properties_destroyed */ | |
7636 | 0, /* todo_flags_start */ | |
3bea341f | 7637 | TODO_df_finish, /* todo_flags_finish */ |
ef330312 | 7638 | }; |
5f39ad47 | 7639 | |
27a4cd48 DM |
7640 | class pass_cse2 : public rtl_opt_pass |
7641 | { | |
7642 | public: | |
c3284718 RS |
7643 | pass_cse2 (gcc::context *ctxt) |
7644 | : rtl_opt_pass (pass_data_cse2, ctxt) | |
27a4cd48 DM |
7645 | {} |
7646 | ||
7647 | /* opt_pass methods: */ | |
725793af | 7648 | bool gate (function *) final override |
1a3d085c TS |
7649 | { |
7650 | return optimize > 0 && flag_rerun_cse_after_loop; | |
7651 | } | |
7652 | ||
725793af DM |
7653 | unsigned int execute (function *) final override |
7654 | { | |
7655 | return rest_of_handle_cse2 (); | |
7656 | } | |
27a4cd48 DM |
7657 | |
7658 | }; // class pass_cse2 | |
7659 | ||
7660 | } // anon namespace | |
7661 | ||
7662 | rtl_opt_pass * | |
7663 | make_pass_cse2 (gcc::context *ctxt) | |
7664 | { | |
7665 | return new pass_cse2 (ctxt); | |
7666 | } | |
7667 | ||
5f39ad47 SB |
7668 | /* Run second CSE pass after loop optimizations. */ |
7669 | static unsigned int | |
7670 | rest_of_handle_cse_after_global_opts (void) | |
7671 | { | |
7672 | int save_cfj; | |
7673 | int tem; | |
7674 | ||
7675 | /* We only want to do local CSE, so don't follow jumps. */ | |
7676 | save_cfj = flag_cse_follow_jumps; | |
7677 | flag_cse_follow_jumps = 0; | |
7678 | ||
7679 | rebuild_jump_labels (get_insns ()); | |
7680 | tem = cse_main (get_insns (), max_reg_num ()); | |
98ccd1d7 | 7681 | cse_cfg_altered |= purge_all_dead_edges (); |
5f39ad47 SB |
7682 | delete_trivially_dead_insns (get_insns (), max_reg_num ()); |
7683 | ||
7684 | cse_not_expected = !flag_rerun_cse_after_loop; | |
7685 | ||
7686 | /* If cse altered any jumps, rerun jump opts to clean things up. */ | |
7687 | if (tem == 2) | |
7688 | { | |
7689 | timevar_push (TV_JUMP); | |
7690 | rebuild_jump_labels (get_insns ()); | |
da7674f6 | 7691 | cse_cfg_altered |= cleanup_cfg (CLEANUP_CFG_CHANGED); |
5f39ad47 SB |
7692 | timevar_pop (TV_JUMP); |
7693 | } | |
ba585b91 | 7694 | else if (tem == 1 || cse_cfg_altered) |
da7674f6 | 7695 | cse_cfg_altered |= cleanup_cfg (0); |
5f39ad47 SB |
7696 | |
7697 | flag_cse_follow_jumps = save_cfj; | |
7698 | return 0; | |
7699 | } | |
7700 | ||
27a4cd48 DM |
7701 | namespace { |
7702 | ||
7703 | const pass_data pass_data_cse_after_global_opts = | |
5f39ad47 | 7704 | { |
27a4cd48 DM |
7705 | RTL_PASS, /* type */ |
7706 | "cse_local", /* name */ | |
7707 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
7708 | TV_CSE, /* tv_id */ |
7709 | 0, /* properties_required */ | |
7710 | 0, /* properties_provided */ | |
7711 | 0, /* properties_destroyed */ | |
7712 | 0, /* todo_flags_start */ | |
3bea341f | 7713 | TODO_df_finish, /* todo_flags_finish */ |
5f39ad47 | 7714 | }; |
27a4cd48 DM |
7715 | |
7716 | class pass_cse_after_global_opts : public rtl_opt_pass | |
7717 | { | |
7718 | public: | |
c3284718 RS |
7719 | pass_cse_after_global_opts (gcc::context *ctxt) |
7720 | : rtl_opt_pass (pass_data_cse_after_global_opts, ctxt) | |
27a4cd48 DM |
7721 | {} |
7722 | ||
7723 | /* opt_pass methods: */ | |
725793af | 7724 | bool gate (function *) final override |
1a3d085c TS |
7725 | { |
7726 | return optimize > 0 && flag_rerun_cse_after_global_opts; | |
7727 | } | |
7728 | ||
725793af | 7729 | unsigned int execute (function *) final override |
be55bfe6 TS |
7730 | { |
7731 | return rest_of_handle_cse_after_global_opts (); | |
7732 | } | |
27a4cd48 DM |
7733 | |
7734 | }; // class pass_cse_after_global_opts | |
7735 | ||
7736 | } // anon namespace | |
7737 | ||
7738 | rtl_opt_pass * | |
7739 | make_pass_cse_after_global_opts (gcc::context *ctxt) | |
7740 | { | |
7741 | return new pass_cse_after_global_opts (ctxt); | |
7742 | } |