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b5e01d4b | 1 | @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001, |
55a2c322 | 2 | @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 |
66647d44 | 3 | @c Free Software Foundation, Inc. |
03dda8e3 RK |
4 | @c This is part of the GCC manual. |
5 | @c For copying conditions, see the file gcc.texi. | |
6 | ||
7 | @ifset INTERNALS | |
8 | @node Machine Desc | |
9 | @chapter Machine Descriptions | |
10 | @cindex machine descriptions | |
11 | ||
12 | A machine description has two parts: a file of instruction patterns | |
13 | (@file{.md} file) and a C header file of macro definitions. | |
14 | ||
15 | The @file{.md} file for a target machine contains a pattern for each | |
16 | instruction that the target machine supports (or at least each instruction | |
17 | that is worth telling the compiler about). It may also contain comments. | |
18 | A semicolon causes the rest of the line to be a comment, unless the semicolon | |
19 | is inside a quoted string. | |
20 | ||
21 | See the next chapter for information on the C header file. | |
22 | ||
23 | @menu | |
55e4756f | 24 | * Overview:: How the machine description is used. |
03dda8e3 RK |
25 | * Patterns:: How to write instruction patterns. |
26 | * Example:: An explained example of a @code{define_insn} pattern. | |
27 | * RTL Template:: The RTL template defines what insns match a pattern. | |
28 | * Output Template:: The output template says how to make assembler code | |
6ccde948 | 29 | from such an insn. |
03dda8e3 | 30 | * Output Statement:: For more generality, write C code to output |
6ccde948 | 31 | the assembler code. |
e543e219 | 32 | * Predicates:: Controlling what kinds of operands can be used |
6ccde948 | 33 | for an insn. |
e543e219 | 34 | * Constraints:: Fine-tuning operand selection. |
03dda8e3 RK |
35 | * Standard Names:: Names mark patterns to use for code generation. |
36 | * Pattern Ordering:: When the order of patterns makes a difference. | |
37 | * Dependent Patterns:: Having one pattern may make you need another. | |
38 | * Jump Patterns:: Special considerations for patterns for jump insns. | |
6e4fcc95 | 39 | * Looping Patterns:: How to define patterns for special looping insns. |
03dda8e3 | 40 | * Insn Canonicalizations::Canonicalization of Instructions |
03dda8e3 | 41 | * Expander Definitions::Generating a sequence of several RTL insns |
6ccde948 | 42 | for a standard operation. |
f3a3d0d3 | 43 | * Insn Splitting:: Splitting Instructions into Multiple Instructions. |
6ccde948 | 44 | * Including Patterns:: Including Patterns in Machine Descriptions. |
f3a3d0d3 | 45 | * Peephole Definitions::Defining machine-specific peephole optimizations. |
03dda8e3 | 46 | * Insn Attributes:: Specifying the value of attributes for generated insns. |
3262c1f5 | 47 | * Conditional Execution::Generating @code{define_insn} patterns for |
6ccde948 | 48 | predication. |
c25c12b8 R |
49 | * Constant Definitions::Defining symbolic constants that can be used in the |
50 | md file. | |
3abcb3a7 | 51 | * Iterators:: Using iterators to generate patterns from a template. |
03dda8e3 RK |
52 | @end menu |
53 | ||
55e4756f DD |
54 | @node Overview |
55 | @section Overview of How the Machine Description is Used | |
56 | ||
57 | There are three main conversions that happen in the compiler: | |
58 | ||
59 | @enumerate | |
60 | ||
61 | @item | |
62 | The front end reads the source code and builds a parse tree. | |
63 | ||
64 | @item | |
65 | The parse tree is used to generate an RTL insn list based on named | |
66 | instruction patterns. | |
67 | ||
68 | @item | |
69 | The insn list is matched against the RTL templates to produce assembler | |
70 | code. | |
71 | ||
72 | @end enumerate | |
73 | ||
74 | For the generate pass, only the names of the insns matter, from either a | |
75 | named @code{define_insn} or a @code{define_expand}. The compiler will | |
76 | choose the pattern with the right name and apply the operands according | |
77 | to the documentation later in this chapter, without regard for the RTL | |
78 | template or operand constraints. Note that the names the compiler looks | |
d7d9c429 | 79 | for are hard-coded in the compiler---it will ignore unnamed patterns and |
55e4756f DD |
80 | patterns with names it doesn't know about, but if you don't provide a |
81 | named pattern it needs, it will abort. | |
82 | ||
83 | If a @code{define_insn} is used, the template given is inserted into the | |
84 | insn list. If a @code{define_expand} is used, one of three things | |
85 | happens, based on the condition logic. The condition logic may manually | |
86 | create new insns for the insn list, say via @code{emit_insn()}, and | |
aee96fe9 | 87 | invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the |
55e4756f DD |
88 | compiler to use an alternate way of performing that task. If it invokes |
89 | neither @code{DONE} nor @code{FAIL}, the template given in the pattern | |
90 | is inserted, as if the @code{define_expand} were a @code{define_insn}. | |
91 | ||
92 | Once the insn list is generated, various optimization passes convert, | |
93 | replace, and rearrange the insns in the insn list. This is where the | |
94 | @code{define_split} and @code{define_peephole} patterns get used, for | |
95 | example. | |
96 | ||
97 | Finally, the insn list's RTL is matched up with the RTL templates in the | |
98 | @code{define_insn} patterns, and those patterns are used to emit the | |
99 | final assembly code. For this purpose, each named @code{define_insn} | |
100 | acts like it's unnamed, since the names are ignored. | |
101 | ||
03dda8e3 RK |
102 | @node Patterns |
103 | @section Everything about Instruction Patterns | |
104 | @cindex patterns | |
105 | @cindex instruction patterns | |
106 | ||
107 | @findex define_insn | |
108 | Each instruction pattern contains an incomplete RTL expression, with pieces | |
109 | to be filled in later, operand constraints that restrict how the pieces can | |
110 | be filled in, and an output pattern or C code to generate the assembler | |
111 | output, all wrapped up in a @code{define_insn} expression. | |
112 | ||
113 | A @code{define_insn} is an RTL expression containing four or five operands: | |
114 | ||
115 | @enumerate | |
116 | @item | |
117 | An optional name. The presence of a name indicate that this instruction | |
118 | pattern can perform a certain standard job for the RTL-generation | |
119 | pass of the compiler. This pass knows certain names and will use | |
120 | the instruction patterns with those names, if the names are defined | |
121 | in the machine description. | |
122 | ||
123 | The absence of a name is indicated by writing an empty string | |
124 | where the name should go. Nameless instruction patterns are never | |
125 | used for generating RTL code, but they may permit several simpler insns | |
126 | to be combined later on. | |
127 | ||
128 | Names that are not thus known and used in RTL-generation have no | |
129 | effect; they are equivalent to no name at all. | |
130 | ||
661cb0b7 RK |
131 | For the purpose of debugging the compiler, you may also specify a |
132 | name beginning with the @samp{*} character. Such a name is used only | |
133 | for identifying the instruction in RTL dumps; it is entirely equivalent | |
134 | to having a nameless pattern for all other purposes. | |
135 | ||
03dda8e3 RK |
136 | @item |
137 | The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete | |
138 | RTL expressions which show what the instruction should look like. It is | |
139 | incomplete because it may contain @code{match_operand}, | |
140 | @code{match_operator}, and @code{match_dup} expressions that stand for | |
141 | operands of the instruction. | |
142 | ||
143 | If the vector has only one element, that element is the template for the | |
144 | instruction pattern. If the vector has multiple elements, then the | |
145 | instruction pattern is a @code{parallel} expression containing the | |
146 | elements described. | |
147 | ||
148 | @item | |
149 | @cindex pattern conditions | |
150 | @cindex conditions, in patterns | |
151 | A condition. This is a string which contains a C expression that is | |
152 | the final test to decide whether an insn body matches this pattern. | |
153 | ||
154 | @cindex named patterns and conditions | |
155 | For a named pattern, the condition (if present) may not depend on | |
156 | the data in the insn being matched, but only the target-machine-type | |
157 | flags. The compiler needs to test these conditions during | |
158 | initialization in order to learn exactly which named instructions are | |
159 | available in a particular run. | |
160 | ||
161 | @findex operands | |
162 | For nameless patterns, the condition is applied only when matching an | |
163 | individual insn, and only after the insn has matched the pattern's | |
164 | recognition template. The insn's operands may be found in the vector | |
fde6d81f HPN |
165 | @code{operands}. For an insn where the condition has once matched, it |
166 | can't be used to control register allocation, for example by excluding | |
167 | certain hard registers or hard register combinations. | |
03dda8e3 RK |
168 | |
169 | @item | |
170 | The @dfn{output template}: a string that says how to output matching | |
171 | insns as assembler code. @samp{%} in this string specifies where | |
172 | to substitute the value of an operand. @xref{Output Template}. | |
173 | ||
174 | When simple substitution isn't general enough, you can specify a piece | |
175 | of C code to compute the output. @xref{Output Statement}. | |
176 | ||
177 | @item | |
178 | Optionally, a vector containing the values of attributes for insns matching | |
179 | this pattern. @xref{Insn Attributes}. | |
180 | @end enumerate | |
181 | ||
182 | @node Example | |
183 | @section Example of @code{define_insn} | |
184 | @cindex @code{define_insn} example | |
185 | ||
186 | Here is an actual example of an instruction pattern, for the 68000/68020. | |
187 | ||
3ab51846 | 188 | @smallexample |
03dda8e3 RK |
189 | (define_insn "tstsi" |
190 | [(set (cc0) | |
191 | (match_operand:SI 0 "general_operand" "rm"))] | |
192 | "" | |
193 | "* | |
f282ffb3 | 194 | @{ |
0f40f9f7 | 195 | if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) |
03dda8e3 | 196 | return \"tstl %0\"; |
f282ffb3 | 197 | return \"cmpl #0,%0\"; |
0f40f9f7 | 198 | @}") |
3ab51846 | 199 | @end smallexample |
0f40f9f7 ZW |
200 | |
201 | @noindent | |
202 | This can also be written using braced strings: | |
203 | ||
3ab51846 | 204 | @smallexample |
0f40f9f7 ZW |
205 | (define_insn "tstsi" |
206 | [(set (cc0) | |
207 | (match_operand:SI 0 "general_operand" "rm"))] | |
208 | "" | |
f282ffb3 | 209 | @{ |
0f40f9f7 ZW |
210 | if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) |
211 | return "tstl %0"; | |
f282ffb3 | 212 | return "cmpl #0,%0"; |
0f40f9f7 | 213 | @}) |
3ab51846 | 214 | @end smallexample |
03dda8e3 RK |
215 | |
216 | This is an instruction that sets the condition codes based on the value of | |
217 | a general operand. It has no condition, so any insn whose RTL description | |
218 | has the form shown may be handled according to this pattern. The name | |
219 | @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation | |
220 | pass that, when it is necessary to test such a value, an insn to do so | |
221 | can be constructed using this pattern. | |
222 | ||
223 | The output control string is a piece of C code which chooses which | |
224 | output template to return based on the kind of operand and the specific | |
225 | type of CPU for which code is being generated. | |
226 | ||
227 | @samp{"rm"} is an operand constraint. Its meaning is explained below. | |
228 | ||
229 | @node RTL Template | |
230 | @section RTL Template | |
231 | @cindex RTL insn template | |
232 | @cindex generating insns | |
233 | @cindex insns, generating | |
234 | @cindex recognizing insns | |
235 | @cindex insns, recognizing | |
236 | ||
237 | The RTL template is used to define which insns match the particular pattern | |
238 | and how to find their operands. For named patterns, the RTL template also | |
239 | says how to construct an insn from specified operands. | |
240 | ||
241 | Construction involves substituting specified operands into a copy of the | |
242 | template. Matching involves determining the values that serve as the | |
243 | operands in the insn being matched. Both of these activities are | |
244 | controlled by special expression types that direct matching and | |
245 | substitution of the operands. | |
246 | ||
247 | @table @code | |
248 | @findex match_operand | |
249 | @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint}) | |
250 | This expression is a placeholder for operand number @var{n} of | |
251 | the insn. When constructing an insn, operand number @var{n} | |
252 | will be substituted at this point. When matching an insn, whatever | |
253 | appears at this position in the insn will be taken as operand | |
254 | number @var{n}; but it must satisfy @var{predicate} or this instruction | |
255 | pattern will not match at all. | |
256 | ||
257 | Operand numbers must be chosen consecutively counting from zero in | |
258 | each instruction pattern. There may be only one @code{match_operand} | |
259 | expression in the pattern for each operand number. Usually operands | |
260 | are numbered in the order of appearance in @code{match_operand} | |
72938a4c MM |
261 | expressions. In the case of a @code{define_expand}, any operand numbers |
262 | used only in @code{match_dup} expressions have higher values than all | |
263 | other operand numbers. | |
03dda8e3 | 264 | |
e543e219 ZW |
265 | @var{predicate} is a string that is the name of a function that |
266 | accepts two arguments, an expression and a machine mode. | |
267 | @xref{Predicates}. During matching, the function will be called with | |
268 | the putative operand as the expression and @var{m} as the mode | |
269 | argument (if @var{m} is not specified, @code{VOIDmode} will be used, | |
270 | which normally causes @var{predicate} to accept any mode). If it | |
271 | returns zero, this instruction pattern fails to match. | |
272 | @var{predicate} may be an empty string; then it means no test is to be | |
273 | done on the operand, so anything which occurs in this position is | |
274 | valid. | |
03dda8e3 RK |
275 | |
276 | Most of the time, @var{predicate} will reject modes other than @var{m}---but | |
277 | not always. For example, the predicate @code{address_operand} uses | |
278 | @var{m} as the mode of memory ref that the address should be valid for. | |
279 | Many predicates accept @code{const_int} nodes even though their mode is | |
280 | @code{VOIDmode}. | |
281 | ||
282 | @var{constraint} controls reloading and the choice of the best register | |
283 | class to use for a value, as explained later (@pxref{Constraints}). | |
e543e219 | 284 | If the constraint would be an empty string, it can be omitted. |
03dda8e3 RK |
285 | |
286 | People are often unclear on the difference between the constraint and the | |
287 | predicate. The predicate helps decide whether a given insn matches the | |
288 | pattern. The constraint plays no role in this decision; instead, it | |
289 | controls various decisions in the case of an insn which does match. | |
290 | ||
03dda8e3 RK |
291 | @findex match_scratch |
292 | @item (match_scratch:@var{m} @var{n} @var{constraint}) | |
293 | This expression is also a placeholder for operand number @var{n} | |
294 | and indicates that operand must be a @code{scratch} or @code{reg} | |
295 | expression. | |
296 | ||
297 | When matching patterns, this is equivalent to | |
298 | ||
299 | @smallexample | |
300 | (match_operand:@var{m} @var{n} "scratch_operand" @var{pred}) | |
301 | @end smallexample | |
302 | ||
303 | but, when generating RTL, it produces a (@code{scratch}:@var{m}) | |
304 | expression. | |
305 | ||
306 | If the last few expressions in a @code{parallel} are @code{clobber} | |
307 | expressions whose operands are either a hard register or | |
308 | @code{match_scratch}, the combiner can add or delete them when | |
309 | necessary. @xref{Side Effects}. | |
310 | ||
311 | @findex match_dup | |
312 | @item (match_dup @var{n}) | |
313 | This expression is also a placeholder for operand number @var{n}. | |
314 | It is used when the operand needs to appear more than once in the | |
315 | insn. | |
316 | ||
317 | In construction, @code{match_dup} acts just like @code{match_operand}: | |
318 | the operand is substituted into the insn being constructed. But in | |
319 | matching, @code{match_dup} behaves differently. It assumes that operand | |
320 | number @var{n} has already been determined by a @code{match_operand} | |
321 | appearing earlier in the recognition template, and it matches only an | |
322 | identical-looking expression. | |
323 | ||
55e4756f DD |
324 | Note that @code{match_dup} should not be used to tell the compiler that |
325 | a particular register is being used for two operands (example: | |
326 | @code{add} that adds one register to another; the second register is | |
327 | both an input operand and the output operand). Use a matching | |
328 | constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one | |
329 | operand is used in two places in the template, such as an instruction | |
330 | that computes both a quotient and a remainder, where the opcode takes | |
331 | two input operands but the RTL template has to refer to each of those | |
332 | twice; once for the quotient pattern and once for the remainder pattern. | |
333 | ||
03dda8e3 RK |
334 | @findex match_operator |
335 | @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}]) | |
336 | This pattern is a kind of placeholder for a variable RTL expression | |
337 | code. | |
338 | ||
339 | When constructing an insn, it stands for an RTL expression whose | |
340 | expression code is taken from that of operand @var{n}, and whose | |
341 | operands are constructed from the patterns @var{operands}. | |
342 | ||
343 | When matching an expression, it matches an expression if the function | |
344 | @var{predicate} returns nonzero on that expression @emph{and} the | |
345 | patterns @var{operands} match the operands of the expression. | |
346 | ||
347 | Suppose that the function @code{commutative_operator} is defined as | |
348 | follows, to match any expression whose operator is one of the | |
349 | commutative arithmetic operators of RTL and whose mode is @var{mode}: | |
350 | ||
351 | @smallexample | |
352 | int | |
ec8e098d | 353 | commutative_integer_operator (x, mode) |
03dda8e3 RK |
354 | rtx x; |
355 | enum machine_mode mode; | |
356 | @{ | |
357 | enum rtx_code code = GET_CODE (x); | |
358 | if (GET_MODE (x) != mode) | |
359 | return 0; | |
ec8e098d | 360 | return (GET_RTX_CLASS (code) == RTX_COMM_ARITH |
03dda8e3 RK |
361 | || code == EQ || code == NE); |
362 | @} | |
363 | @end smallexample | |
364 | ||
365 | Then the following pattern will match any RTL expression consisting | |
366 | of a commutative operator applied to two general operands: | |
367 | ||
368 | @smallexample | |
369 | (match_operator:SI 3 "commutative_operator" | |
370 | [(match_operand:SI 1 "general_operand" "g") | |
371 | (match_operand:SI 2 "general_operand" "g")]) | |
372 | @end smallexample | |
373 | ||
374 | Here the vector @code{[@var{operands}@dots{}]} contains two patterns | |
375 | because the expressions to be matched all contain two operands. | |
376 | ||
377 | When this pattern does match, the two operands of the commutative | |
378 | operator are recorded as operands 1 and 2 of the insn. (This is done | |
379 | by the two instances of @code{match_operand}.) Operand 3 of the insn | |
380 | will be the entire commutative expression: use @code{GET_CODE | |
381 | (operands[3])} to see which commutative operator was used. | |
382 | ||
383 | The machine mode @var{m} of @code{match_operator} works like that of | |
384 | @code{match_operand}: it is passed as the second argument to the | |
385 | predicate function, and that function is solely responsible for | |
386 | deciding whether the expression to be matched ``has'' that mode. | |
387 | ||
388 | When constructing an insn, argument 3 of the gen-function will specify | |
e979f9e8 | 389 | the operation (i.e.@: the expression code) for the expression to be |
03dda8e3 RK |
390 | made. It should be an RTL expression, whose expression code is copied |
391 | into a new expression whose operands are arguments 1 and 2 of the | |
392 | gen-function. The subexpressions of argument 3 are not used; | |
393 | only its expression code matters. | |
394 | ||
395 | When @code{match_operator} is used in a pattern for matching an insn, | |
396 | it usually best if the operand number of the @code{match_operator} | |
397 | is higher than that of the actual operands of the insn. This improves | |
398 | register allocation because the register allocator often looks at | |
399 | operands 1 and 2 of insns to see if it can do register tying. | |
400 | ||
401 | There is no way to specify constraints in @code{match_operator}. The | |
402 | operand of the insn which corresponds to the @code{match_operator} | |
403 | never has any constraints because it is never reloaded as a whole. | |
404 | However, if parts of its @var{operands} are matched by | |
405 | @code{match_operand} patterns, those parts may have constraints of | |
406 | their own. | |
407 | ||
408 | @findex match_op_dup | |
409 | @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}]) | |
410 | Like @code{match_dup}, except that it applies to operators instead of | |
411 | operands. When constructing an insn, operand number @var{n} will be | |
412 | substituted at this point. But in matching, @code{match_op_dup} behaves | |
413 | differently. It assumes that operand number @var{n} has already been | |
414 | determined by a @code{match_operator} appearing earlier in the | |
415 | recognition template, and it matches only an identical-looking | |
416 | expression. | |
417 | ||
418 | @findex match_parallel | |
419 | @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}]) | |
420 | This pattern is a placeholder for an insn that consists of a | |
421 | @code{parallel} expression with a variable number of elements. This | |
422 | expression should only appear at the top level of an insn pattern. | |
423 | ||
424 | When constructing an insn, operand number @var{n} will be substituted at | |
425 | this point. When matching an insn, it matches if the body of the insn | |
426 | is a @code{parallel} expression with at least as many elements as the | |
427 | vector of @var{subpat} expressions in the @code{match_parallel}, if each | |
428 | @var{subpat} matches the corresponding element of the @code{parallel}, | |
429 | @emph{and} the function @var{predicate} returns nonzero on the | |
430 | @code{parallel} that is the body of the insn. It is the responsibility | |
431 | of the predicate to validate elements of the @code{parallel} beyond | |
bd819a4a | 432 | those listed in the @code{match_parallel}. |
03dda8e3 RK |
433 | |
434 | A typical use of @code{match_parallel} is to match load and store | |
435 | multiple expressions, which can contain a variable number of elements | |
436 | in a @code{parallel}. For example, | |
03dda8e3 RK |
437 | |
438 | @smallexample | |
439 | (define_insn "" | |
440 | [(match_parallel 0 "load_multiple_operation" | |
441 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
442 | (match_operand:SI 2 "memory_operand" "m")) | |
443 | (use (reg:SI 179)) | |
444 | (clobber (reg:SI 179))])] | |
445 | "" | |
446 | "loadm 0,0,%1,%2") | |
447 | @end smallexample | |
448 | ||
449 | This example comes from @file{a29k.md}. The function | |
9c34dbbf | 450 | @code{load_multiple_operation} is defined in @file{a29k.c} and checks |
03dda8e3 RK |
451 | that subsequent elements in the @code{parallel} are the same as the |
452 | @code{set} in the pattern, except that they are referencing subsequent | |
453 | registers and memory locations. | |
454 | ||
455 | An insn that matches this pattern might look like: | |
456 | ||
457 | @smallexample | |
458 | (parallel | |
459 | [(set (reg:SI 20) (mem:SI (reg:SI 100))) | |
460 | (use (reg:SI 179)) | |
461 | (clobber (reg:SI 179)) | |
462 | (set (reg:SI 21) | |
463 | (mem:SI (plus:SI (reg:SI 100) | |
464 | (const_int 4)))) | |
465 | (set (reg:SI 22) | |
466 | (mem:SI (plus:SI (reg:SI 100) | |
467 | (const_int 8))))]) | |
468 | @end smallexample | |
469 | ||
470 | @findex match_par_dup | |
471 | @item (match_par_dup @var{n} [@var{subpat}@dots{}]) | |
472 | Like @code{match_op_dup}, but for @code{match_parallel} instead of | |
473 | @code{match_operator}. | |
474 | ||
03dda8e3 RK |
475 | @end table |
476 | ||
477 | @node Output Template | |
478 | @section Output Templates and Operand Substitution | |
479 | @cindex output templates | |
480 | @cindex operand substitution | |
481 | ||
482 | @cindex @samp{%} in template | |
483 | @cindex percent sign | |
484 | The @dfn{output template} is a string which specifies how to output the | |
485 | assembler code for an instruction pattern. Most of the template is a | |
486 | fixed string which is output literally. The character @samp{%} is used | |
487 | to specify where to substitute an operand; it can also be used to | |
488 | identify places where different variants of the assembler require | |
489 | different syntax. | |
490 | ||
491 | In the simplest case, a @samp{%} followed by a digit @var{n} says to output | |
492 | operand @var{n} at that point in the string. | |
493 | ||
494 | @samp{%} followed by a letter and a digit says to output an operand in an | |
495 | alternate fashion. Four letters have standard, built-in meanings described | |
496 | below. The machine description macro @code{PRINT_OPERAND} can define | |
497 | additional letters with nonstandard meanings. | |
498 | ||
499 | @samp{%c@var{digit}} can be used to substitute an operand that is a | |
500 | constant value without the syntax that normally indicates an immediate | |
501 | operand. | |
502 | ||
503 | @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of | |
504 | the constant is negated before printing. | |
505 | ||
506 | @samp{%a@var{digit}} can be used to substitute an operand as if it were a | |
507 | memory reference, with the actual operand treated as the address. This may | |
508 | be useful when outputting a ``load address'' instruction, because often the | |
509 | assembler syntax for such an instruction requires you to write the operand | |
510 | as if it were a memory reference. | |
511 | ||
512 | @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump | |
513 | instruction. | |
514 | ||
515 | @samp{%=} outputs a number which is unique to each instruction in the | |
516 | entire compilation. This is useful for making local labels to be | |
517 | referred to more than once in a single template that generates multiple | |
518 | assembler instructions. | |
519 | ||
520 | @samp{%} followed by a punctuation character specifies a substitution that | |
521 | does not use an operand. Only one case is standard: @samp{%%} outputs a | |
522 | @samp{%} into the assembler code. Other nonstandard cases can be | |
523 | defined in the @code{PRINT_OPERAND} macro. You must also define | |
524 | which punctuation characters are valid with the | |
525 | @code{PRINT_OPERAND_PUNCT_VALID_P} macro. | |
526 | ||
527 | @cindex \ | |
528 | @cindex backslash | |
529 | The template may generate multiple assembler instructions. Write the text | |
530 | for the instructions, with @samp{\;} between them. | |
531 | ||
532 | @cindex matching operands | |
533 | When the RTL contains two operands which are required by constraint to match | |
534 | each other, the output template must refer only to the lower-numbered operand. | |
535 | Matching operands are not always identical, and the rest of the compiler | |
536 | arranges to put the proper RTL expression for printing into the lower-numbered | |
537 | operand. | |
538 | ||
539 | One use of nonstandard letters or punctuation following @samp{%} is to | |
540 | distinguish between different assembler languages for the same machine; for | |
541 | example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax | |
542 | requires periods in most opcode names, while MIT syntax does not. For | |
543 | example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola | |
544 | syntax. The same file of patterns is used for both kinds of output syntax, | |
545 | but the character sequence @samp{%.} is used in each place where Motorola | |
546 | syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax | |
547 | defines the sequence to output a period; the macro for MIT syntax defines | |
548 | it to do nothing. | |
549 | ||
550 | @cindex @code{#} in template | |
551 | As a special case, a template consisting of the single character @code{#} | |
552 | instructs the compiler to first split the insn, and then output the | |
553 | resulting instructions separately. This helps eliminate redundancy in the | |
554 | output templates. If you have a @code{define_insn} that needs to emit | |
e4ae5e77 | 555 | multiple assembler instructions, and there is a matching @code{define_split} |
03dda8e3 RK |
556 | already defined, then you can simply use @code{#} as the output template |
557 | instead of writing an output template that emits the multiple assembler | |
558 | instructions. | |
559 | ||
560 | If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct | |
561 | of the form @samp{@{option0|option1|option2@}} in the templates. These | |
562 | describe multiple variants of assembler language syntax. | |
563 | @xref{Instruction Output}. | |
564 | ||
565 | @node Output Statement | |
566 | @section C Statements for Assembler Output | |
567 | @cindex output statements | |
568 | @cindex C statements for assembler output | |
569 | @cindex generating assembler output | |
570 | ||
571 | Often a single fixed template string cannot produce correct and efficient | |
572 | assembler code for all the cases that are recognized by a single | |
573 | instruction pattern. For example, the opcodes may depend on the kinds of | |
574 | operands; or some unfortunate combinations of operands may require extra | |
575 | machine instructions. | |
576 | ||
577 | If the output control string starts with a @samp{@@}, then it is actually | |
578 | a series of templates, each on a separate line. (Blank lines and | |
579 | leading spaces and tabs are ignored.) The templates correspond to the | |
580 | pattern's constraint alternatives (@pxref{Multi-Alternative}). For example, | |
581 | if a target machine has a two-address add instruction @samp{addr} to add | |
582 | into a register and another @samp{addm} to add a register to memory, you | |
583 | might write this pattern: | |
584 | ||
585 | @smallexample | |
586 | (define_insn "addsi3" | |
587 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
588 | (plus:SI (match_operand:SI 1 "general_operand" "0,0") | |
589 | (match_operand:SI 2 "general_operand" "g,r")))] | |
590 | "" | |
591 | "@@ | |
592 | addr %2,%0 | |
593 | addm %2,%0") | |
594 | @end smallexample | |
595 | ||
596 | @cindex @code{*} in template | |
597 | @cindex asterisk in template | |
598 | If the output control string starts with a @samp{*}, then it is not an | |
599 | output template but rather a piece of C program that should compute a | |
600 | template. It should execute a @code{return} statement to return the | |
601 | template-string you want. Most such templates use C string literals, which | |
602 | require doublequote characters to delimit them. To include these | |
603 | doublequote characters in the string, prefix each one with @samp{\}. | |
604 | ||
0f40f9f7 ZW |
605 | If the output control string is written as a brace block instead of a |
606 | double-quoted string, it is automatically assumed to be C code. In that | |
607 | case, it is not necessary to put in a leading asterisk, or to escape the | |
608 | doublequotes surrounding C string literals. | |
609 | ||
03dda8e3 RK |
610 | The operands may be found in the array @code{operands}, whose C data type |
611 | is @code{rtx []}. | |
612 | ||
613 | It is very common to select different ways of generating assembler code | |
614 | based on whether an immediate operand is within a certain range. Be | |
615 | careful when doing this, because the result of @code{INTVAL} is an | |
616 | integer on the host machine. If the host machine has more bits in an | |
617 | @code{int} than the target machine has in the mode in which the constant | |
618 | will be used, then some of the bits you get from @code{INTVAL} will be | |
619 | superfluous. For proper results, you must carefully disregard the | |
620 | values of those bits. | |
621 | ||
622 | @findex output_asm_insn | |
623 | It is possible to output an assembler instruction and then go on to output | |
624 | or compute more of them, using the subroutine @code{output_asm_insn}. This | |
625 | receives two arguments: a template-string and a vector of operands. The | |
626 | vector may be @code{operands}, or it may be another array of @code{rtx} | |
627 | that you declare locally and initialize yourself. | |
628 | ||
629 | @findex which_alternative | |
630 | When an insn pattern has multiple alternatives in its constraints, often | |
631 | the appearance of the assembler code is determined mostly by which alternative | |
632 | was matched. When this is so, the C code can test the variable | |
633 | @code{which_alternative}, which is the ordinal number of the alternative | |
634 | that was actually satisfied (0 for the first, 1 for the second alternative, | |
635 | etc.). | |
636 | ||
637 | For example, suppose there are two opcodes for storing zero, @samp{clrreg} | |
638 | for registers and @samp{clrmem} for memory locations. Here is how | |
639 | a pattern could use @code{which_alternative} to choose between them: | |
640 | ||
641 | @smallexample | |
642 | (define_insn "" | |
643 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
644 | (const_int 0))] | |
645 | "" | |
0f40f9f7 | 646 | @{ |
03dda8e3 | 647 | return (which_alternative == 0 |
0f40f9f7 ZW |
648 | ? "clrreg %0" : "clrmem %0"); |
649 | @}) | |
03dda8e3 RK |
650 | @end smallexample |
651 | ||
652 | The example above, where the assembler code to generate was | |
653 | @emph{solely} determined by the alternative, could also have been specified | |
654 | as follows, having the output control string start with a @samp{@@}: | |
655 | ||
656 | @smallexample | |
657 | @group | |
658 | (define_insn "" | |
659 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
660 | (const_int 0))] | |
661 | "" | |
662 | "@@ | |
663 | clrreg %0 | |
664 | clrmem %0") | |
665 | @end group | |
666 | @end smallexample | |
e543e219 | 667 | |
94c765ab R |
668 | If you just need a little bit of C code in one (or a few) alternatives, |
669 | you can use @samp{*} inside of a @samp{@@} multi-alternative template: | |
670 | ||
671 | @smallexample | |
672 | @group | |
673 | (define_insn "" | |
674 | [(set (match_operand:SI 0 "general_operand" "=r,<,m") | |
675 | (const_int 0))] | |
676 | "" | |
677 | "@@ | |
678 | clrreg %0 | |
679 | * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\"; | |
680 | clrmem %0") | |
681 | @end group | |
682 | @end smallexample | |
683 | ||
e543e219 ZW |
684 | @node Predicates |
685 | @section Predicates | |
686 | @cindex predicates | |
687 | @cindex operand predicates | |
688 | @cindex operator predicates | |
689 | ||
690 | A predicate determines whether a @code{match_operand} or | |
691 | @code{match_operator} expression matches, and therefore whether the | |
692 | surrounding instruction pattern will be used for that combination of | |
693 | operands. GCC has a number of machine-independent predicates, and you | |
694 | can define machine-specific predicates as needed. By convention, | |
695 | predicates used with @code{match_operand} have names that end in | |
696 | @samp{_operand}, and those used with @code{match_operator} have names | |
697 | that end in @samp{_operator}. | |
698 | ||
699 | All predicates are Boolean functions (in the mathematical sense) of | |
700 | two arguments: the RTL expression that is being considered at that | |
701 | position in the instruction pattern, and the machine mode that the | |
702 | @code{match_operand} or @code{match_operator} specifies. In this | |
703 | section, the first argument is called @var{op} and the second argument | |
704 | @var{mode}. Predicates can be called from C as ordinary two-argument | |
705 | functions; this can be useful in output templates or other | |
706 | machine-specific code. | |
707 | ||
708 | Operand predicates can allow operands that are not actually acceptable | |
709 | to the hardware, as long as the constraints give reload the ability to | |
710 | fix them up (@pxref{Constraints}). However, GCC will usually generate | |
711 | better code if the predicates specify the requirements of the machine | |
712 | instructions as closely as possible. Reload cannot fix up operands | |
713 | that must be constants (``immediate operands''); you must use a | |
714 | predicate that allows only constants, or else enforce the requirement | |
715 | in the extra condition. | |
716 | ||
717 | @cindex predicates and machine modes | |
718 | @cindex normal predicates | |
719 | @cindex special predicates | |
720 | Most predicates handle their @var{mode} argument in a uniform manner. | |
721 | If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have | |
722 | any mode. If @var{mode} is anything else, then @var{op} must have the | |
723 | same mode, unless @var{op} is a @code{CONST_INT} or integer | |
724 | @code{CONST_DOUBLE}. These RTL expressions always have | |
725 | @code{VOIDmode}, so it would be counterproductive to check that their | |
726 | mode matches. Instead, predicates that accept @code{CONST_INT} and/or | |
727 | integer @code{CONST_DOUBLE} check that the value stored in the | |
728 | constant will fit in the requested mode. | |
729 | ||
730 | Predicates with this behavior are called @dfn{normal}. | |
731 | @command{genrecog} can optimize the instruction recognizer based on | |
732 | knowledge of how normal predicates treat modes. It can also diagnose | |
733 | certain kinds of common errors in the use of normal predicates; for | |
734 | instance, it is almost always an error to use a normal predicate | |
735 | without specifying a mode. | |
736 | ||
737 | Predicates that do something different with their @var{mode} argument | |
738 | are called @dfn{special}. The generic predicates | |
739 | @code{address_operand} and @code{pmode_register_operand} are special | |
740 | predicates. @command{genrecog} does not do any optimizations or | |
741 | diagnosis when special predicates are used. | |
742 | ||
743 | @menu | |
744 | * Machine-Independent Predicates:: Predicates available to all back ends. | |
745 | * Defining Predicates:: How to write machine-specific predicate | |
746 | functions. | |
747 | @end menu | |
748 | ||
749 | @node Machine-Independent Predicates | |
750 | @subsection Machine-Independent Predicates | |
751 | @cindex machine-independent predicates | |
752 | @cindex generic predicates | |
753 | ||
754 | These are the generic predicates available to all back ends. They are | |
755 | defined in @file{recog.c}. The first category of predicates allow | |
756 | only constant, or @dfn{immediate}, operands. | |
757 | ||
758 | @defun immediate_operand | |
759 | This predicate allows any sort of constant that fits in @var{mode}. | |
760 | It is an appropriate choice for instructions that take operands that | |
761 | must be constant. | |
762 | @end defun | |
763 | ||
764 | @defun const_int_operand | |
765 | This predicate allows any @code{CONST_INT} expression that fits in | |
766 | @var{mode}. It is an appropriate choice for an immediate operand that | |
767 | does not allow a symbol or label. | |
768 | @end defun | |
769 | ||
770 | @defun const_double_operand | |
771 | This predicate accepts any @code{CONST_DOUBLE} expression that has | |
772 | exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also | |
773 | accept @code{CONST_INT}. It is intended for immediate floating point | |
774 | constants. | |
775 | @end defun | |
776 | ||
777 | @noindent | |
778 | The second category of predicates allow only some kind of machine | |
779 | register. | |
780 | ||
781 | @defun register_operand | |
782 | This predicate allows any @code{REG} or @code{SUBREG} expression that | |
783 | is valid for @var{mode}. It is often suitable for arithmetic | |
784 | instruction operands on a RISC machine. | |
785 | @end defun | |
786 | ||
787 | @defun pmode_register_operand | |
788 | This is a slight variant on @code{register_operand} which works around | |
789 | a limitation in the machine-description reader. | |
790 | ||
cd1a8088 | 791 | @smallexample |
e543e219 | 792 | (match_operand @var{n} "pmode_register_operand" @var{constraint}) |
cd1a8088 | 793 | @end smallexample |
e543e219 ZW |
794 | |
795 | @noindent | |
796 | means exactly what | |
797 | ||
cd1a8088 | 798 | @smallexample |
e543e219 | 799 | (match_operand:P @var{n} "register_operand" @var{constraint}) |
cd1a8088 | 800 | @end smallexample |
e543e219 ZW |
801 | |
802 | @noindent | |
803 | would mean, if the machine-description reader accepted @samp{:P} | |
804 | mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an | |
805 | alias for some other mode, and might vary with machine-specific | |
8a36672b | 806 | options. @xref{Misc}. |
e543e219 ZW |
807 | @end defun |
808 | ||
809 | @defun scratch_operand | |
810 | This predicate allows hard registers and @code{SCRATCH} expressions, | |
811 | but not pseudo-registers. It is used internally by @code{match_scratch}; | |
812 | it should not be used directly. | |
813 | @end defun | |
814 | ||
815 | @noindent | |
816 | The third category of predicates allow only some kind of memory reference. | |
817 | ||
818 | @defun memory_operand | |
819 | This predicate allows any valid reference to a quantity of mode | |
820 | @var{mode} in memory, as determined by the weak form of | |
821 | @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}). | |
822 | @end defun | |
823 | ||
824 | @defun address_operand | |
825 | This predicate is a little unusual; it allows any operand that is a | |
826 | valid expression for the @emph{address} of a quantity of mode | |
827 | @var{mode}, again determined by the weak form of | |
828 | @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if | |
829 | @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to | |
830 | @code{memory_operand}, then @var{exp} is acceptable to | |
831 | @code{address_operand}. Note that @var{exp} does not necessarily have | |
832 | the mode @var{mode}. | |
833 | @end defun | |
834 | ||
835 | @defun indirect_operand | |
836 | This is a stricter form of @code{memory_operand} which allows only | |
837 | memory references with a @code{general_operand} as the address | |
838 | expression. New uses of this predicate are discouraged, because | |
839 | @code{general_operand} is very permissive, so it's hard to tell what | |
840 | an @code{indirect_operand} does or does not allow. If a target has | |
841 | different requirements for memory operands for different instructions, | |
842 | it is better to define target-specific predicates which enforce the | |
843 | hardware's requirements explicitly. | |
844 | @end defun | |
845 | ||
846 | @defun push_operand | |
847 | This predicate allows a memory reference suitable for pushing a value | |
848 | onto the stack. This will be a @code{MEM} which refers to | |
849 | @code{stack_pointer_rtx}, with a side-effect in its address expression | |
850 | (@pxref{Incdec}); which one is determined by the | |
851 | @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}). | |
852 | @end defun | |
853 | ||
854 | @defun pop_operand | |
855 | This predicate allows a memory reference suitable for popping a value | |
856 | off the stack. Again, this will be a @code{MEM} referring to | |
857 | @code{stack_pointer_rtx}, with a side-effect in its address | |
858 | expression. However, this time @code{STACK_POP_CODE} is expected. | |
859 | @end defun | |
860 | ||
861 | @noindent | |
862 | The fourth category of predicates allow some combination of the above | |
863 | operands. | |
864 | ||
865 | @defun nonmemory_operand | |
866 | This predicate allows any immediate or register operand valid for @var{mode}. | |
867 | @end defun | |
868 | ||
869 | @defun nonimmediate_operand | |
870 | This predicate allows any register or memory operand valid for @var{mode}. | |
871 | @end defun | |
872 | ||
873 | @defun general_operand | |
874 | This predicate allows any immediate, register, or memory operand | |
875 | valid for @var{mode}. | |
876 | @end defun | |
877 | ||
878 | @noindent | |
c6963675 | 879 | Finally, there are two generic operator predicates. |
e543e219 ZW |
880 | |
881 | @defun comparison_operator | |
882 | This predicate matches any expression which performs an arithmetic | |
883 | comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the | |
884 | expression code. | |
885 | @end defun | |
886 | ||
c6963675 PB |
887 | @defun ordered_comparison_operator |
888 | This predicate matches any expression which performs an arithmetic | |
889 | comparison in @var{mode} and whose expression code is valid for integer | |
890 | modes; that is, the expression code will be one of @code{eq}, @code{ne}, | |
891 | @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu}, | |
892 | @code{ge}, @code{geu}. | |
893 | @end defun | |
894 | ||
e543e219 ZW |
895 | @node Defining Predicates |
896 | @subsection Defining Machine-Specific Predicates | |
897 | @cindex defining predicates | |
898 | @findex define_predicate | |
899 | @findex define_special_predicate | |
900 | ||
901 | Many machines have requirements for their operands that cannot be | |
902 | expressed precisely using the generic predicates. You can define | |
903 | additional predicates using @code{define_predicate} and | |
904 | @code{define_special_predicate} expressions. These expressions have | |
905 | three operands: | |
906 | ||
907 | @itemize @bullet | |
908 | @item | |
909 | The name of the predicate, as it will be referred to in | |
910 | @code{match_operand} or @code{match_operator} expressions. | |
911 | ||
912 | @item | |
913 | An RTL expression which evaluates to true if the predicate allows the | |
914 | operand @var{op}, false if it does not. This expression can only use | |
915 | the following RTL codes: | |
916 | ||
917 | @table @code | |
918 | @item MATCH_OPERAND | |
919 | When written inside a predicate expression, a @code{MATCH_OPERAND} | |
920 | expression evaluates to true if the predicate it names would allow | |
921 | @var{op}. The operand number and constraint are ignored. Due to | |
922 | limitations in @command{genrecog}, you can only refer to generic | |
923 | predicates and predicates that have already been defined. | |
924 | ||
925 | @item MATCH_CODE | |
6e7a4706 ZW |
926 | This expression evaluates to true if @var{op} or a specified |
927 | subexpression of @var{op} has one of a given list of RTX codes. | |
928 | ||
929 | The first operand of this expression is a string constant containing a | |
930 | comma-separated list of RTX code names (in lower case). These are the | |
931 | codes for which the @code{MATCH_CODE} will be true. | |
932 | ||
933 | The second operand is a string constant which indicates what | |
934 | subexpression of @var{op} to examine. If it is absent or the empty | |
935 | string, @var{op} itself is examined. Otherwise, the string constant | |
936 | must be a sequence of digits and/or lowercase letters. Each character | |
937 | indicates a subexpression to extract from the current expression; for | |
938 | the first character this is @var{op}, for the second and subsequent | |
939 | characters it is the result of the previous character. A digit | |
940 | @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l} | |
941 | extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the | |
942 | alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The | |
943 | @code{MATCH_CODE} then examines the RTX code of the subexpression | |
944 | extracted by the complete string. It is not possible to extract | |
945 | components of an @code{rtvec} that is not at position 0 within its RTX | |
946 | object. | |
e543e219 ZW |
947 | |
948 | @item MATCH_TEST | |
949 | This expression has one operand, a string constant containing a C | |
950 | expression. The predicate's arguments, @var{op} and @var{mode}, are | |
951 | available with those names in the C expression. The @code{MATCH_TEST} | |
952 | evaluates to true if the C expression evaluates to a nonzero value. | |
953 | @code{MATCH_TEST} expressions must not have side effects. | |
954 | ||
955 | @item AND | |
956 | @itemx IOR | |
957 | @itemx NOT | |
958 | @itemx IF_THEN_ELSE | |
959 | The basic @samp{MATCH_} expressions can be combined using these | |
960 | logical operators, which have the semantics of the C operators | |
6e7a4706 ZW |
961 | @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As |
962 | in Common Lisp, you may give an @code{AND} or @code{IOR} expression an | |
963 | arbitrary number of arguments; this has exactly the same effect as | |
964 | writing a chain of two-argument @code{AND} or @code{IOR} expressions. | |
e543e219 ZW |
965 | @end table |
966 | ||
967 | @item | |
f0eb93a8 | 968 | An optional block of C code, which should execute |
e543e219 ZW |
969 | @samp{@w{return true}} if the predicate is found to match and |
970 | @samp{@w{return false}} if it does not. It must not have any side | |
971 | effects. The predicate arguments, @var{op} and @var{mode}, are | |
972 | available with those names. | |
973 | ||
974 | If a code block is present in a predicate definition, then the RTL | |
975 | expression must evaluate to true @emph{and} the code block must | |
976 | execute @samp{@w{return true}} for the predicate to allow the operand. | |
977 | The RTL expression is evaluated first; do not re-check anything in the | |
978 | code block that was checked in the RTL expression. | |
979 | @end itemize | |
980 | ||
981 | The program @command{genrecog} scans @code{define_predicate} and | |
982 | @code{define_special_predicate} expressions to determine which RTX | |
983 | codes are possibly allowed. You should always make this explicit in | |
984 | the RTL predicate expression, using @code{MATCH_OPERAND} and | |
985 | @code{MATCH_CODE}. | |
986 | ||
987 | Here is an example of a simple predicate definition, from the IA64 | |
988 | machine description: | |
989 | ||
990 | @smallexample | |
991 | @group | |
992 | ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.} | |
993 | (define_predicate "small_addr_symbolic_operand" | |
994 | (and (match_code "symbol_ref") | |
995 | (match_test "SYMBOL_REF_SMALL_ADDR_P (op)"))) | |
996 | @end group | |
997 | @end smallexample | |
998 | ||
999 | @noindent | |
1000 | And here is another, showing the use of the C block. | |
1001 | ||
1002 | @smallexample | |
1003 | @group | |
1004 | ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.} | |
1005 | (define_predicate "gr_register_operand" | |
1006 | (match_operand 0 "register_operand") | |
1007 | @{ | |
1008 | unsigned int regno; | |
1009 | if (GET_CODE (op) == SUBREG) | |
1010 | op = SUBREG_REG (op); | |
1011 | ||
1012 | regno = REGNO (op); | |
1013 | return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno)); | |
1014 | @}) | |
1015 | @end group | |
1016 | @end smallexample | |
1017 | ||
1018 | Predicates written with @code{define_predicate} automatically include | |
1019 | a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same | |
1020 | mode as @var{mode}, or @var{op} is a @code{CONST_INT} or | |
1021 | @code{CONST_DOUBLE}. They do @emph{not} check specifically for | |
1022 | integer @code{CONST_DOUBLE}, nor do they test that the value of either | |
1023 | kind of constant fits in the requested mode. This is because | |
1024 | target-specific predicates that take constants usually have to do more | |
1025 | stringent value checks anyway. If you need the exact same treatment | |
1026 | of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates | |
1027 | provide, use a @code{MATCH_OPERAND} subexpression to call | |
1028 | @code{const_int_operand}, @code{const_double_operand}, or | |
1029 | @code{immediate_operand}. | |
1030 | ||
1031 | Predicates written with @code{define_special_predicate} do not get any | |
1032 | automatic mode checks, and are treated as having special mode handling | |
1033 | by @command{genrecog}. | |
1034 | ||
1035 | The program @command{genpreds} is responsible for generating code to | |
1036 | test predicates. It also writes a header file containing function | |
1037 | declarations for all machine-specific predicates. It is not necessary | |
1038 | to declare these predicates in @file{@var{cpu}-protos.h}. | |
03dda8e3 RK |
1039 | @end ifset |
1040 | ||
1041 | @c Most of this node appears by itself (in a different place) even | |
b11cc610 JM |
1042 | @c when the INTERNALS flag is clear. Passages that require the internals |
1043 | @c manual's context are conditionalized to appear only in the internals manual. | |
03dda8e3 RK |
1044 | @ifset INTERNALS |
1045 | @node Constraints | |
1046 | @section Operand Constraints | |
1047 | @cindex operand constraints | |
1048 | @cindex constraints | |
1049 | ||
e543e219 ZW |
1050 | Each @code{match_operand} in an instruction pattern can specify |
1051 | constraints for the operands allowed. The constraints allow you to | |
1052 | fine-tune matching within the set of operands allowed by the | |
1053 | predicate. | |
1054 | ||
03dda8e3 RK |
1055 | @end ifset |
1056 | @ifclear INTERNALS | |
1057 | @node Constraints | |
1058 | @section Constraints for @code{asm} Operands | |
1059 | @cindex operand constraints, @code{asm} | |
1060 | @cindex constraints, @code{asm} | |
1061 | @cindex @code{asm} constraints | |
1062 | ||
1063 | Here are specific details on what constraint letters you can use with | |
1064 | @code{asm} operands. | |
1065 | @end ifclear | |
1066 | Constraints can say whether | |
1067 | an operand may be in a register, and which kinds of register; whether the | |
1068 | operand can be a memory reference, and which kinds of address; whether the | |
1069 | operand may be an immediate constant, and which possible values it may | |
1070 | have. Constraints can also require two operands to match. | |
54f044eb JJ |
1071 | Side-effects aren't allowed in operands of inline @code{asm}, unless |
1072 | @samp{<} or @samp{>} constraints are used, because there is no guarantee | |
1073 | that the side-effects will happen exactly once in an instruction that can update | |
1074 | the addressing register. | |
03dda8e3 RK |
1075 | |
1076 | @ifset INTERNALS | |
1077 | @menu | |
1078 | * Simple Constraints:: Basic use of constraints. | |
1079 | * Multi-Alternative:: When an insn has two alternative constraint-patterns. | |
1080 | * Class Preferences:: Constraints guide which hard register to put things in. | |
1081 | * Modifiers:: More precise control over effects of constraints. | |
7ac28727 | 1082 | * Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute. |
03dda8e3 | 1083 | * Machine Constraints:: Existing constraints for some particular machines. |
f38840db ZW |
1084 | * Define Constraints:: How to define machine-specific constraints. |
1085 | * C Constraint Interface:: How to test constraints from C code. | |
03dda8e3 RK |
1086 | @end menu |
1087 | @end ifset | |
1088 | ||
1089 | @ifclear INTERNALS | |
1090 | @menu | |
1091 | * Simple Constraints:: Basic use of constraints. | |
1092 | * Multi-Alternative:: When an insn has two alternative constraint-patterns. | |
1093 | * Modifiers:: More precise control over effects of constraints. | |
1094 | * Machine Constraints:: Special constraints for some particular machines. | |
1095 | @end menu | |
1096 | @end ifclear | |
1097 | ||
1098 | @node Simple Constraints | |
1099 | @subsection Simple Constraints | |
1100 | @cindex simple constraints | |
1101 | ||
1102 | The simplest kind of constraint is a string full of letters, each of | |
1103 | which describes one kind of operand that is permitted. Here are | |
1104 | the letters that are allowed: | |
1105 | ||
1106 | @table @asis | |
88a56c2e HPN |
1107 | @item whitespace |
1108 | Whitespace characters are ignored and can be inserted at any position | |
1109 | except the first. This enables each alternative for different operands to | |
1110 | be visually aligned in the machine description even if they have different | |
1111 | number of constraints and modifiers. | |
1112 | ||
03dda8e3 RK |
1113 | @cindex @samp{m} in constraint |
1114 | @cindex memory references in constraints | |
1115 | @item @samp{m} | |
1116 | A memory operand is allowed, with any kind of address that the machine | |
1117 | supports in general. | |
a4edaf83 AK |
1118 | Note that the letter used for the general memory constraint can be |
1119 | re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro. | |
03dda8e3 RK |
1120 | |
1121 | @cindex offsettable address | |
1122 | @cindex @samp{o} in constraint | |
1123 | @item @samp{o} | |
1124 | A memory operand is allowed, but only if the address is | |
1125 | @dfn{offsettable}. This means that adding a small integer (actually, | |
1126 | the width in bytes of the operand, as determined by its machine mode) | |
1127 | may be added to the address and the result is also a valid memory | |
1128 | address. | |
1129 | ||
1130 | @cindex autoincrement/decrement addressing | |
1131 | For example, an address which is constant is offsettable; so is an | |
1132 | address that is the sum of a register and a constant (as long as a | |
1133 | slightly larger constant is also within the range of address-offsets | |
1134 | supported by the machine); but an autoincrement or autodecrement | |
1135 | address is not offsettable. More complicated indirect/indexed | |
1136 | addresses may or may not be offsettable depending on the other | |
1137 | addressing modes that the machine supports. | |
1138 | ||
1139 | Note that in an output operand which can be matched by another | |
1140 | operand, the constraint letter @samp{o} is valid only when accompanied | |
1141 | by both @samp{<} (if the target machine has predecrement addressing) | |
1142 | and @samp{>} (if the target machine has preincrement addressing). | |
1143 | ||
1144 | @cindex @samp{V} in constraint | |
1145 | @item @samp{V} | |
1146 | A memory operand that is not offsettable. In other words, anything that | |
1147 | would fit the @samp{m} constraint but not the @samp{o} constraint. | |
1148 | ||
1149 | @cindex @samp{<} in constraint | |
1150 | @item @samp{<} | |
1151 | A memory operand with autodecrement addressing (either predecrement or | |
54f044eb JJ |
1152 | postdecrement) is allowed. In inline @code{asm} this constraint is only |
1153 | allowed if the operand is used exactly once in an instruction that can | |
1154 | handle the side-effects. Not using an operand with @samp{<} in constraint | |
1155 | string in the inline @code{asm} pattern at all or using it in multiple | |
1156 | instructions isn't valid, because the side-effects wouldn't be performed | |
1157 | or would be performed more than once. Furthermore, on some targets | |
1158 | the operand with @samp{<} in constraint string must be accompanied by | |
1159 | special instruction suffixes like @code{%U0} instruction suffix on PowerPC | |
1160 | or @code{%P0} on IA-64. | |
03dda8e3 RK |
1161 | |
1162 | @cindex @samp{>} in constraint | |
1163 | @item @samp{>} | |
1164 | A memory operand with autoincrement addressing (either preincrement or | |
54f044eb JJ |
1165 | postincrement) is allowed. In inline @code{asm} the same restrictions |
1166 | as for @samp{<} apply. | |
03dda8e3 RK |
1167 | |
1168 | @cindex @samp{r} in constraint | |
1169 | @cindex registers in constraints | |
1170 | @item @samp{r} | |
1171 | A register operand is allowed provided that it is in a general | |
1172 | register. | |
1173 | ||
03dda8e3 RK |
1174 | @cindex constants in constraints |
1175 | @cindex @samp{i} in constraint | |
1176 | @item @samp{i} | |
1177 | An immediate integer operand (one with constant value) is allowed. | |
1178 | This includes symbolic constants whose values will be known only at | |
8ac658b6 | 1179 | assembly time or later. |
03dda8e3 RK |
1180 | |
1181 | @cindex @samp{n} in constraint | |
1182 | @item @samp{n} | |
1183 | An immediate integer operand with a known numeric value is allowed. | |
1184 | Many systems cannot support assembly-time constants for operands less | |
1185 | than a word wide. Constraints for these operands should use @samp{n} | |
1186 | rather than @samp{i}. | |
1187 | ||
1188 | @cindex @samp{I} in constraint | |
1189 | @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P} | |
1190 | Other letters in the range @samp{I} through @samp{P} may be defined in | |
1191 | a machine-dependent fashion to permit immediate integer operands with | |
1192 | explicit integer values in specified ranges. For example, on the | |
1193 | 68000, @samp{I} is defined to stand for the range of values 1 to 8. | |
1194 | This is the range permitted as a shift count in the shift | |
1195 | instructions. | |
1196 | ||
1197 | @cindex @samp{E} in constraint | |
1198 | @item @samp{E} | |
1199 | An immediate floating operand (expression code @code{const_double}) is | |
1200 | allowed, but only if the target floating point format is the same as | |
1201 | that of the host machine (on which the compiler is running). | |
1202 | ||
1203 | @cindex @samp{F} in constraint | |
1204 | @item @samp{F} | |
bf7cd754 R |
1205 | An immediate floating operand (expression code @code{const_double} or |
1206 | @code{const_vector}) is allowed. | |
03dda8e3 RK |
1207 | |
1208 | @cindex @samp{G} in constraint | |
1209 | @cindex @samp{H} in constraint | |
1210 | @item @samp{G}, @samp{H} | |
1211 | @samp{G} and @samp{H} may be defined in a machine-dependent fashion to | |
1212 | permit immediate floating operands in particular ranges of values. | |
1213 | ||
1214 | @cindex @samp{s} in constraint | |
1215 | @item @samp{s} | |
1216 | An immediate integer operand whose value is not an explicit integer is | |
1217 | allowed. | |
1218 | ||
1219 | This might appear strange; if an insn allows a constant operand with a | |
1220 | value not known at compile time, it certainly must allow any known | |
1221 | value. So why use @samp{s} instead of @samp{i}? Sometimes it allows | |
1222 | better code to be generated. | |
1223 | ||
1224 | For example, on the 68000 in a fullword instruction it is possible to | |
630d3d5a | 1225 | use an immediate operand; but if the immediate value is between @minus{}128 |
03dda8e3 RK |
1226 | and 127, better code results from loading the value into a register and |
1227 | using the register. This is because the load into the register can be | |
1228 | done with a @samp{moveq} instruction. We arrange for this to happen | |
1229 | by defining the letter @samp{K} to mean ``any integer outside the | |
630d3d5a | 1230 | range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand |
03dda8e3 RK |
1231 | constraints. |
1232 | ||
1233 | @cindex @samp{g} in constraint | |
1234 | @item @samp{g} | |
1235 | Any register, memory or immediate integer operand is allowed, except for | |
1236 | registers that are not general registers. | |
1237 | ||
1238 | @cindex @samp{X} in constraint | |
1239 | @item @samp{X} | |
1240 | @ifset INTERNALS | |
1241 | Any operand whatsoever is allowed, even if it does not satisfy | |
1242 | @code{general_operand}. This is normally used in the constraint of | |
1243 | a @code{match_scratch} when certain alternatives will not actually | |
1244 | require a scratch register. | |
1245 | @end ifset | |
1246 | @ifclear INTERNALS | |
1247 | Any operand whatsoever is allowed. | |
1248 | @end ifclear | |
1249 | ||
1250 | @cindex @samp{0} in constraint | |
1251 | @cindex digits in constraint | |
1252 | @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9} | |
1253 | An operand that matches the specified operand number is allowed. If a | |
1254 | digit is used together with letters within the same alternative, the | |
1255 | digit should come last. | |
1256 | ||
84b72302 | 1257 | This number is allowed to be more than a single digit. If multiple |
c0478a66 | 1258 | digits are encountered consecutively, they are interpreted as a single |
84b72302 RH |
1259 | decimal integer. There is scant chance for ambiguity, since to-date |
1260 | it has never been desirable that @samp{10} be interpreted as matching | |
1261 | either operand 1 @emph{or} operand 0. Should this be desired, one | |
1262 | can use multiple alternatives instead. | |
1263 | ||
03dda8e3 RK |
1264 | @cindex matching constraint |
1265 | @cindex constraint, matching | |
1266 | This is called a @dfn{matching constraint} and what it really means is | |
1267 | that the assembler has only a single operand that fills two roles | |
1268 | @ifset INTERNALS | |
1269 | considered separate in the RTL insn. For example, an add insn has two | |
1270 | input operands and one output operand in the RTL, but on most CISC | |
1271 | @end ifset | |
1272 | @ifclear INTERNALS | |
1273 | which @code{asm} distinguishes. For example, an add instruction uses | |
1274 | two input operands and an output operand, but on most CISC | |
1275 | @end ifclear | |
1276 | machines an add instruction really has only two operands, one of them an | |
1277 | input-output operand: | |
1278 | ||
1279 | @smallexample | |
1280 | addl #35,r12 | |
1281 | @end smallexample | |
1282 | ||
1283 | Matching constraints are used in these circumstances. | |
1284 | More precisely, the two operands that match must include one input-only | |
1285 | operand and one output-only operand. Moreover, the digit must be a | |
1286 | smaller number than the number of the operand that uses it in the | |
1287 | constraint. | |
1288 | ||
1289 | @ifset INTERNALS | |
1290 | For operands to match in a particular case usually means that they | |
1291 | are identical-looking RTL expressions. But in a few special cases | |
1292 | specific kinds of dissimilarity are allowed. For example, @code{*x} | |
1293 | as an input operand will match @code{*x++} as an output operand. | |
1294 | For proper results in such cases, the output template should always | |
1295 | use the output-operand's number when printing the operand. | |
1296 | @end ifset | |
1297 | ||
1298 | @cindex load address instruction | |
1299 | @cindex push address instruction | |
1300 | @cindex address constraints | |
1301 | @cindex @samp{p} in constraint | |
1302 | @item @samp{p} | |
1303 | An operand that is a valid memory address is allowed. This is | |
1304 | for ``load address'' and ``push address'' instructions. | |
1305 | ||
1306 | @findex address_operand | |
1307 | @samp{p} in the constraint must be accompanied by @code{address_operand} | |
1308 | as the predicate in the @code{match_operand}. This predicate interprets | |
1309 | the mode specified in the @code{match_operand} as the mode of the memory | |
1310 | reference for which the address would be valid. | |
1311 | ||
c2cba7a9 | 1312 | @cindex other register constraints |
03dda8e3 | 1313 | @cindex extensible constraints |
630d3d5a | 1314 | @item @var{other-letters} |
c2cba7a9 RH |
1315 | Other letters can be defined in machine-dependent fashion to stand for |
1316 | particular classes of registers or other arbitrary operand types. | |
1317 | @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand | |
1318 | for data, address and floating point registers. | |
03dda8e3 RK |
1319 | @end table |
1320 | ||
1321 | @ifset INTERNALS | |
1322 | In order to have valid assembler code, each operand must satisfy | |
1323 | its constraint. But a failure to do so does not prevent the pattern | |
1324 | from applying to an insn. Instead, it directs the compiler to modify | |
1325 | the code so that the constraint will be satisfied. Usually this is | |
1326 | done by copying an operand into a register. | |
1327 | ||
1328 | Contrast, therefore, the two instruction patterns that follow: | |
1329 | ||
1330 | @smallexample | |
1331 | (define_insn "" | |
1332 | [(set (match_operand:SI 0 "general_operand" "=r") | |
1333 | (plus:SI (match_dup 0) | |
1334 | (match_operand:SI 1 "general_operand" "r")))] | |
1335 | "" | |
1336 | "@dots{}") | |
1337 | @end smallexample | |
1338 | ||
1339 | @noindent | |
1340 | which has two operands, one of which must appear in two places, and | |
1341 | ||
1342 | @smallexample | |
1343 | (define_insn "" | |
1344 | [(set (match_operand:SI 0 "general_operand" "=r") | |
1345 | (plus:SI (match_operand:SI 1 "general_operand" "0") | |
1346 | (match_operand:SI 2 "general_operand" "r")))] | |
1347 | "" | |
1348 | "@dots{}") | |
1349 | @end smallexample | |
1350 | ||
1351 | @noindent | |
1352 | which has three operands, two of which are required by a constraint to be | |
1353 | identical. If we are considering an insn of the form | |
1354 | ||
1355 | @smallexample | |
1356 | (insn @var{n} @var{prev} @var{next} | |
1357 | (set (reg:SI 3) | |
1358 | (plus:SI (reg:SI 6) (reg:SI 109))) | |
1359 | @dots{}) | |
1360 | @end smallexample | |
1361 | ||
1362 | @noindent | |
1363 | the first pattern would not apply at all, because this insn does not | |
1364 | contain two identical subexpressions in the right place. The pattern would | |
d78aa55c | 1365 | say, ``That does not look like an add instruction; try other patterns''. |
03dda8e3 | 1366 | The second pattern would say, ``Yes, that's an add instruction, but there |
d78aa55c | 1367 | is something wrong with it''. It would direct the reload pass of the |
03dda8e3 RK |
1368 | compiler to generate additional insns to make the constraint true. The |
1369 | results might look like this: | |
1370 | ||
1371 | @smallexample | |
1372 | (insn @var{n2} @var{prev} @var{n} | |
1373 | (set (reg:SI 3) (reg:SI 6)) | |
1374 | @dots{}) | |
1375 | ||
1376 | (insn @var{n} @var{n2} @var{next} | |
1377 | (set (reg:SI 3) | |
1378 | (plus:SI (reg:SI 3) (reg:SI 109))) | |
1379 | @dots{}) | |
1380 | @end smallexample | |
1381 | ||
1382 | It is up to you to make sure that each operand, in each pattern, has | |
1383 | constraints that can handle any RTL expression that could be present for | |
1384 | that operand. (When multiple alternatives are in use, each pattern must, | |
1385 | for each possible combination of operand expressions, have at least one | |
1386 | alternative which can handle that combination of operands.) The | |
1387 | constraints don't need to @emph{allow} any possible operand---when this is | |
1388 | the case, they do not constrain---but they must at least point the way to | |
1389 | reloading any possible operand so that it will fit. | |
1390 | ||
1391 | @itemize @bullet | |
1392 | @item | |
1393 | If the constraint accepts whatever operands the predicate permits, | |
1394 | there is no problem: reloading is never necessary for this operand. | |
1395 | ||
1396 | For example, an operand whose constraints permit everything except | |
1397 | registers is safe provided its predicate rejects registers. | |
1398 | ||
1399 | An operand whose predicate accepts only constant values is safe | |
1400 | provided its constraints include the letter @samp{i}. If any possible | |
1401 | constant value is accepted, then nothing less than @samp{i} will do; | |
1402 | if the predicate is more selective, then the constraints may also be | |
1403 | more selective. | |
1404 | ||
1405 | @item | |
1406 | Any operand expression can be reloaded by copying it into a register. | |
1407 | So if an operand's constraints allow some kind of register, it is | |
1408 | certain to be safe. It need not permit all classes of registers; the | |
1409 | compiler knows how to copy a register into another register of the | |
1410 | proper class in order to make an instruction valid. | |
1411 | ||
1412 | @cindex nonoffsettable memory reference | |
1413 | @cindex memory reference, nonoffsettable | |
1414 | @item | |
1415 | A nonoffsettable memory reference can be reloaded by copying the | |
1416 | address into a register. So if the constraint uses the letter | |
1417 | @samp{o}, all memory references are taken care of. | |
1418 | ||
1419 | @item | |
1420 | A constant operand can be reloaded by allocating space in memory to | |
1421 | hold it as preinitialized data. Then the memory reference can be used | |
1422 | in place of the constant. So if the constraint uses the letters | |
1423 | @samp{o} or @samp{m}, constant operands are not a problem. | |
1424 | ||
1425 | @item | |
1426 | If the constraint permits a constant and a pseudo register used in an insn | |
1427 | was not allocated to a hard register and is equivalent to a constant, | |
1428 | the register will be replaced with the constant. If the predicate does | |
1429 | not permit a constant and the insn is re-recognized for some reason, the | |
1430 | compiler will crash. Thus the predicate must always recognize any | |
1431 | objects allowed by the constraint. | |
1432 | @end itemize | |
1433 | ||
1434 | If the operand's predicate can recognize registers, but the constraint does | |
1435 | not permit them, it can make the compiler crash. When this operand happens | |
1436 | to be a register, the reload pass will be stymied, because it does not know | |
1437 | how to copy a register temporarily into memory. | |
1438 | ||
1439 | If the predicate accepts a unary operator, the constraint applies to the | |
1440 | operand. For example, the MIPS processor at ISA level 3 supports an | |
1441 | instruction which adds two registers in @code{SImode} to produce a | |
1442 | @code{DImode} result, but only if the registers are correctly sign | |
1443 | extended. This predicate for the input operands accepts a | |
1444 | @code{sign_extend} of an @code{SImode} register. Write the constraint | |
1445 | to indicate the type of register that is required for the operand of the | |
1446 | @code{sign_extend}. | |
1447 | @end ifset | |
1448 | ||
1449 | @node Multi-Alternative | |
1450 | @subsection Multiple Alternative Constraints | |
1451 | @cindex multiple alternative constraints | |
1452 | ||
1453 | Sometimes a single instruction has multiple alternative sets of possible | |
1454 | operands. For example, on the 68000, a logical-or instruction can combine | |
1455 | register or an immediate value into memory, or it can combine any kind of | |
1456 | operand into a register; but it cannot combine one memory location into | |
1457 | another. | |
1458 | ||
1459 | These constraints are represented as multiple alternatives. An alternative | |
1460 | can be described by a series of letters for each operand. The overall | |
1461 | constraint for an operand is made from the letters for this operand | |
1462 | from the first alternative, a comma, the letters for this operand from | |
1463 | the second alternative, a comma, and so on until the last alternative. | |
1464 | @ifset INTERNALS | |
1465 | Here is how it is done for fullword logical-or on the 68000: | |
1466 | ||
1467 | @smallexample | |
1468 | (define_insn "iorsi3" | |
1469 | [(set (match_operand:SI 0 "general_operand" "=m,d") | |
1470 | (ior:SI (match_operand:SI 1 "general_operand" "%0,0") | |
1471 | (match_operand:SI 2 "general_operand" "dKs,dmKs")))] | |
1472 | @dots{}) | |
1473 | @end smallexample | |
1474 | ||
1475 | The first alternative has @samp{m} (memory) for operand 0, @samp{0} for | |
1476 | operand 1 (meaning it must match operand 0), and @samp{dKs} for operand | |
1477 | 2. The second alternative has @samp{d} (data register) for operand 0, | |
1478 | @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and | |
1479 | @samp{%} in the constraints apply to all the alternatives; their | |
1480 | meaning is explained in the next section (@pxref{Class Preferences}). | |
1481 | @end ifset | |
1482 | ||
1483 | @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL | |
1484 | If all the operands fit any one alternative, the instruction is valid. | |
1485 | Otherwise, for each alternative, the compiler counts how many instructions | |
1486 | must be added to copy the operands so that that alternative applies. | |
1487 | The alternative requiring the least copying is chosen. If two alternatives | |
1488 | need the same amount of copying, the one that comes first is chosen. | |
1489 | These choices can be altered with the @samp{?} and @samp{!} characters: | |
1490 | ||
1491 | @table @code | |
1492 | @cindex @samp{?} in constraint | |
1493 | @cindex question mark | |
1494 | @item ? | |
1495 | Disparage slightly the alternative that the @samp{?} appears in, | |
1496 | as a choice when no alternative applies exactly. The compiler regards | |
1497 | this alternative as one unit more costly for each @samp{?} that appears | |
1498 | in it. | |
1499 | ||
1500 | @cindex @samp{!} in constraint | |
1501 | @cindex exclamation point | |
1502 | @item ! | |
1503 | Disparage severely the alternative that the @samp{!} appears in. | |
1504 | This alternative can still be used if it fits without reloading, | |
1505 | but if reloading is needed, some other alternative will be used. | |
1506 | @end table | |
1507 | ||
1508 | @ifset INTERNALS | |
1509 | When an insn pattern has multiple alternatives in its constraints, often | |
1510 | the appearance of the assembler code is determined mostly by which | |
1511 | alternative was matched. When this is so, the C code for writing the | |
1512 | assembler code can use the variable @code{which_alternative}, which is | |
1513 | the ordinal number of the alternative that was actually satisfied (0 for | |
1514 | the first, 1 for the second alternative, etc.). @xref{Output Statement}. | |
1515 | @end ifset | |
1516 | ||
1517 | @ifset INTERNALS | |
1518 | @node Class Preferences | |
1519 | @subsection Register Class Preferences | |
1520 | @cindex class preference constraints | |
1521 | @cindex register class preference constraints | |
1522 | ||
1523 | @cindex voting between constraint alternatives | |
1524 | The operand constraints have another function: they enable the compiler | |
1525 | to decide which kind of hardware register a pseudo register is best | |
1526 | allocated to. The compiler examines the constraints that apply to the | |
1527 | insns that use the pseudo register, looking for the machine-dependent | |
1528 | letters such as @samp{d} and @samp{a} that specify classes of registers. | |
1529 | The pseudo register is put in whichever class gets the most ``votes''. | |
1530 | The constraint letters @samp{g} and @samp{r} also vote: they vote in | |
1531 | favor of a general register. The machine description says which registers | |
1532 | are considered general. | |
1533 | ||
1534 | Of course, on some machines all registers are equivalent, and no register | |
1535 | classes are defined. Then none of this complexity is relevant. | |
1536 | @end ifset | |
1537 | ||
1538 | @node Modifiers | |
1539 | @subsection Constraint Modifier Characters | |
1540 | @cindex modifiers in constraints | |
1541 | @cindex constraint modifier characters | |
1542 | ||
1543 | @c prevent bad page break with this line | |
1544 | Here are constraint modifier characters. | |
1545 | ||
1546 | @table @samp | |
1547 | @cindex @samp{=} in constraint | |
1548 | @item = | |
1549 | Means that this operand is write-only for this instruction: the previous | |
1550 | value is discarded and replaced by output data. | |
1551 | ||
1552 | @cindex @samp{+} in constraint | |
1553 | @item + | |
1554 | Means that this operand is both read and written by the instruction. | |
1555 | ||
1556 | When the compiler fixes up the operands to satisfy the constraints, | |
1557 | it needs to know which operands are inputs to the instruction and | |
1558 | which are outputs from it. @samp{=} identifies an output; @samp{+} | |
1559 | identifies an operand that is both input and output; all other operands | |
1560 | are assumed to be input only. | |
1561 | ||
c5c76735 JL |
1562 | If you specify @samp{=} or @samp{+} in a constraint, you put it in the |
1563 | first character of the constraint string. | |
1564 | ||
03dda8e3 RK |
1565 | @cindex @samp{&} in constraint |
1566 | @cindex earlyclobber operand | |
1567 | @item & | |
1568 | Means (in a particular alternative) that this operand is an | |
1569 | @dfn{earlyclobber} operand, which is modified before the instruction is | |
1570 | finished using the input operands. Therefore, this operand may not lie | |
1571 | in a register that is used as an input operand or as part of any memory | |
1572 | address. | |
1573 | ||
1574 | @samp{&} applies only to the alternative in which it is written. In | |
1575 | constraints with multiple alternatives, sometimes one alternative | |
1576 | requires @samp{&} while others do not. See, for example, the | |
1577 | @samp{movdf} insn of the 68000. | |
1578 | ||
ebb48a4d | 1579 | An input operand can be tied to an earlyclobber operand if its only |
03dda8e3 RK |
1580 | use as an input occurs before the early result is written. Adding |
1581 | alternatives of this form often allows GCC to produce better code | |
ebb48a4d | 1582 | when only some of the inputs can be affected by the earlyclobber. |
161d7b59 | 1583 | See, for example, the @samp{mulsi3} insn of the ARM@. |
03dda8e3 RK |
1584 | |
1585 | @samp{&} does not obviate the need to write @samp{=}. | |
1586 | ||
1587 | @cindex @samp{%} in constraint | |
1588 | @item % | |
1589 | Declares the instruction to be commutative for this operand and the | |
1590 | following operand. This means that the compiler may interchange the | |
1591 | two operands if that is the cheapest way to make all operands fit the | |
1592 | constraints. | |
1593 | @ifset INTERNALS | |
1594 | This is often used in patterns for addition instructions | |
1595 | that really have only two operands: the result must go in one of the | |
1596 | arguments. Here for example, is how the 68000 halfword-add | |
1597 | instruction is defined: | |
1598 | ||
1599 | @smallexample | |
1600 | (define_insn "addhi3" | |
1601 | [(set (match_operand:HI 0 "general_operand" "=m,r") | |
1602 | (plus:HI (match_operand:HI 1 "general_operand" "%0,0") | |
1603 | (match_operand:HI 2 "general_operand" "di,g")))] | |
1604 | @dots{}) | |
1605 | @end smallexample | |
1606 | @end ifset | |
daf2f129 | 1607 | GCC can only handle one commutative pair in an asm; if you use more, |
595163db EB |
1608 | the compiler may fail. Note that you need not use the modifier if |
1609 | the two alternatives are strictly identical; this would only waste | |
be3914df HPN |
1610 | time in the reload pass. The modifier is not operational after |
1611 | register allocation, so the result of @code{define_peephole2} | |
1612 | and @code{define_split}s performed after reload cannot rely on | |
1613 | @samp{%} to make the intended insn match. | |
03dda8e3 RK |
1614 | |
1615 | @cindex @samp{#} in constraint | |
1616 | @item # | |
1617 | Says that all following characters, up to the next comma, are to be | |
1618 | ignored as a constraint. They are significant only for choosing | |
1619 | register preferences. | |
1620 | ||
03dda8e3 RK |
1621 | @cindex @samp{*} in constraint |
1622 | @item * | |
1623 | Says that the following character should be ignored when choosing | |
1624 | register preferences. @samp{*} has no effect on the meaning of the | |
55a2c322 VM |
1625 | constraint as a constraint, and no effect on reloading. For LRA |
1626 | @samp{*} additionally disparages slightly the alternative if the | |
1627 | following character matches the operand. | |
03dda8e3 | 1628 | |
9f339dde | 1629 | @ifset INTERNALS |
03dda8e3 RK |
1630 | Here is an example: the 68000 has an instruction to sign-extend a |
1631 | halfword in a data register, and can also sign-extend a value by | |
1632 | copying it into an address register. While either kind of register is | |
1633 | acceptable, the constraints on an address-register destination are | |
1634 | less strict, so it is best if register allocation makes an address | |
1635 | register its goal. Therefore, @samp{*} is used so that the @samp{d} | |
1636 | constraint letter (for data register) is ignored when computing | |
1637 | register preferences. | |
1638 | ||
1639 | @smallexample | |
1640 | (define_insn "extendhisi2" | |
1641 | [(set (match_operand:SI 0 "general_operand" "=*d,a") | |
1642 | (sign_extend:SI | |
1643 | (match_operand:HI 1 "general_operand" "0,g")))] | |
1644 | @dots{}) | |
1645 | @end smallexample | |
1646 | @end ifset | |
1647 | @end table | |
1648 | ||
1649 | @node Machine Constraints | |
1650 | @subsection Constraints for Particular Machines | |
1651 | @cindex machine specific constraints | |
1652 | @cindex constraints, machine specific | |
1653 | ||
1654 | Whenever possible, you should use the general-purpose constraint letters | |
1655 | in @code{asm} arguments, since they will convey meaning more readily to | |
1656 | people reading your code. Failing that, use the constraint letters | |
1657 | that usually have very similar meanings across architectures. The most | |
1658 | commonly used constraints are @samp{m} and @samp{r} (for memory and | |
1659 | general-purpose registers respectively; @pxref{Simple Constraints}), and | |
1660 | @samp{I}, usually the letter indicating the most common | |
1661 | immediate-constant format. | |
1662 | ||
f38840db ZW |
1663 | Each architecture defines additional constraints. These constraints |
1664 | are used by the compiler itself for instruction generation, as well as | |
1665 | for @code{asm} statements; therefore, some of the constraints are not | |
1666 | particularly useful for @code{asm}. Here is a summary of some of the | |
1667 | machine-dependent constraints available on some particular machines; | |
1668 | it includes both constraints that are useful for @code{asm} and | |
1669 | constraints that aren't. The compiler source file mentioned in the | |
1670 | table heading for each architecture is the definitive reference for | |
1671 | the meanings of that architecture's constraints. | |
6ccde948 | 1672 | |
03dda8e3 | 1673 | @table @emph |
dae840fc | 1674 | @item ARM family---@file{config/arm/constraints.md} |
03dda8e3 | 1675 | @table @code |
9b66ebb1 PB |
1676 | @item w |
1677 | VFP floating-point register | |
1678 | ||
03dda8e3 | 1679 | @item G |
dae840fc | 1680 | The floating-point constant 0.0 |
03dda8e3 RK |
1681 | |
1682 | @item I | |
1683 | Integer that is valid as an immediate operand in a data processing | |
1684 | instruction. That is, an integer in the range 0 to 255 rotated by a | |
1685 | multiple of 2 | |
1686 | ||
1687 | @item J | |
630d3d5a | 1688 | Integer in the range @minus{}4095 to 4095 |
03dda8e3 RK |
1689 | |
1690 | @item K | |
1691 | Integer that satisfies constraint @samp{I} when inverted (ones complement) | |
1692 | ||
1693 | @item L | |
1694 | Integer that satisfies constraint @samp{I} when negated (twos complement) | |
1695 | ||
1696 | @item M | |
1697 | Integer in the range 0 to 32 | |
1698 | ||
1699 | @item Q | |
1700 | A memory reference where the exact address is in a single register | |
1701 | (`@samp{m}' is preferable for @code{asm} statements) | |
1702 | ||
1703 | @item R | |
1704 | An item in the constant pool | |
1705 | ||
1706 | @item S | |
1707 | A symbol in the text segment of the current file | |
03dda8e3 | 1708 | |
1e1ab407 | 1709 | @item Uv |
9b66ebb1 PB |
1710 | A memory reference suitable for VFP load/store insns (reg+constant offset) |
1711 | ||
fdd695fd PB |
1712 | @item Uy |
1713 | A memory reference suitable for iWMMXt load/store instructions. | |
1714 | ||
1e1ab407 | 1715 | @item Uq |
0bdcd332 | 1716 | A memory reference suitable for the ARMv4 ldrsb instruction. |
db875b15 | 1717 | @end table |
1e1ab407 | 1718 | |
fc262682 | 1719 | @item AVR family---@file{config/avr/constraints.md} |
052a4b28 DC |
1720 | @table @code |
1721 | @item l | |
1722 | Registers from r0 to r15 | |
1723 | ||
1724 | @item a | |
1725 | Registers from r16 to r23 | |
1726 | ||
1727 | @item d | |
1728 | Registers from r16 to r31 | |
1729 | ||
1730 | @item w | |
3a69a7d5 | 1731 | Registers from r24 to r31. These registers can be used in @samp{adiw} command |
052a4b28 DC |
1732 | |
1733 | @item e | |
d7d9c429 | 1734 | Pointer register (r26--r31) |
052a4b28 DC |
1735 | |
1736 | @item b | |
d7d9c429 | 1737 | Base pointer register (r28--r31) |
052a4b28 | 1738 | |
3a69a7d5 MM |
1739 | @item q |
1740 | Stack pointer register (SPH:SPL) | |
1741 | ||
052a4b28 DC |
1742 | @item t |
1743 | Temporary register r0 | |
1744 | ||
1745 | @item x | |
1746 | Register pair X (r27:r26) | |
1747 | ||
1748 | @item y | |
1749 | Register pair Y (r29:r28) | |
1750 | ||
1751 | @item z | |
1752 | Register pair Z (r31:r30) | |
1753 | ||
1754 | @item I | |
630d3d5a | 1755 | Constant greater than @minus{}1, less than 64 |
052a4b28 DC |
1756 | |
1757 | @item J | |
630d3d5a | 1758 | Constant greater than @minus{}64, less than 1 |
052a4b28 DC |
1759 | |
1760 | @item K | |
1761 | Constant integer 2 | |
1762 | ||
1763 | @item L | |
1764 | Constant integer 0 | |
1765 | ||
1766 | @item M | |
1767 | Constant that fits in 8 bits | |
1768 | ||
1769 | @item N | |
630d3d5a | 1770 | Constant integer @minus{}1 |
052a4b28 DC |
1771 | |
1772 | @item O | |
3a69a7d5 | 1773 | Constant integer 8, 16, or 24 |
052a4b28 DC |
1774 | |
1775 | @item P | |
1776 | Constant integer 1 | |
1777 | ||
1778 | @item G | |
1779 | A floating point constant 0.0 | |
0e8eb4d8 | 1780 | |
0e8eb4d8 EW |
1781 | @item Q |
1782 | A memory address based on Y or Z pointer with displacement. | |
052a4b28 | 1783 | @end table |
53054e77 | 1784 | |
feeeff5c JR |
1785 | @item Epiphany---@file{config/epiphany/constraints.md} |
1786 | @table @code | |
1787 | @item U16 | |
1788 | An unsigned 16-bit constant. | |
1789 | ||
1790 | @item K | |
1791 | An unsigned 5-bit constant. | |
1792 | ||
1793 | @item L | |
1794 | A signed 11-bit constant. | |
1795 | ||
1796 | @item Cm1 | |
1797 | A signed 11-bit constant added to @minus{}1. | |
1798 | Can only match when the @option{-m1reg-@var{reg}} option is active. | |
1799 | ||
1800 | @item Cl1 | |
1801 | Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest | |
1802 | being a block of trailing zeroes. | |
1803 | Can only match when the @option{-m1reg-@var{reg}} option is active. | |
1804 | ||
1805 | @item Cr1 | |
1806 | Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the | |
1807 | rest being zeroes. Or to put it another way, one less than a power of two. | |
1808 | Can only match when the @option{-m1reg-@var{reg}} option is active. | |
1809 | ||
1810 | @item Cal | |
1811 | Constant for arithmetic/logical operations. | |
1812 | This is like @code{i}, except that for position independent code, | |
1813 | no symbols / expressions needing relocations are allowed. | |
1814 | ||
1815 | @item Csy | |
1816 | Symbolic constant for call/jump instruction. | |
1817 | ||
1818 | @item Rcs | |
1819 | The register class usable in short insns. This is a register class | |
1820 | constraint, and can thus drive register allocation. | |
1821 | This constraint won't match unless @option{-mprefer-short-insn-regs} is | |
1822 | in effect. | |
1823 | ||
1824 | @item Rsc | |
1825 | The the register class of registers that can be used to hold a | |
1826 | sibcall call address. I.e., a caller-saved register. | |
1827 | ||
1828 | @item Rct | |
1829 | Core control register class. | |
1830 | ||
1831 | @item Rgs | |
1832 | The register group usable in short insns. | |
1833 | This constraint does not use a register class, so that it only | |
1834 | passively matches suitable registers, and doesn't drive register allocation. | |
1835 | ||
1836 | @ifset INTERNALS | |
1837 | @item Car | |
1838 | Constant suitable for the addsi3_r pattern. This is a valid offset | |
1839 | For byte, halfword, or word addressing. | |
1840 | @end ifset | |
1841 | ||
1842 | @item Rra | |
1843 | Matches the return address if it can be replaced with the link register. | |
1844 | ||
1845 | @item Rcc | |
1846 | Matches the integer condition code register. | |
1847 | ||
1848 | @item Sra | |
1849 | Matches the return address if it is in a stack slot. | |
1850 | ||
1851 | @item Cfm | |
1852 | Matches control register values to switch fp mode, which are encapsulated in | |
1853 | @code{UNSPEC_FP_MODE}. | |
1854 | @end table | |
1855 | ||
b25364a0 S |
1856 | @item CR16 Architecture---@file{config/cr16/cr16.h} |
1857 | @table @code | |
1858 | ||
1859 | @item b | |
1860 | Registers from r0 to r14 (registers without stack pointer) | |
1861 | ||
1862 | @item t | |
1863 | Register from r0 to r11 (all 16-bit registers) | |
1864 | ||
1865 | @item p | |
1866 | Register from r12 to r15 (all 32-bit registers) | |
1867 | ||
1868 | @item I | |
1869 | Signed constant that fits in 4 bits | |
1870 | ||
1871 | @item J | |
1872 | Signed constant that fits in 5 bits | |
1873 | ||
1874 | @item K | |
1875 | Signed constant that fits in 6 bits | |
1876 | ||
1877 | @item L | |
1878 | Unsigned constant that fits in 4 bits | |
1879 | ||
1880 | @item M | |
1881 | Signed constant that fits in 32 bits | |
1882 | ||
1883 | @item N | |
1884 | Check for 64 bits wide constants for add/sub instructions | |
1885 | ||
1886 | @item G | |
1887 | Floating point constant that is legal for store immediate | |
1888 | @end table | |
1889 | ||
8119b4e4 JDA |
1890 | @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h} |
1891 | @table @code | |
1892 | @item a | |
1893 | General register 1 | |
1894 | ||
1895 | @item f | |
1896 | Floating point register | |
1897 | ||
1898 | @item q | |
1899 | Shift amount register | |
1900 | ||
1901 | @item x | |
1902 | Floating point register (deprecated) | |
1903 | ||
1904 | @item y | |
1905 | Upper floating point register (32-bit), floating point register (64-bit) | |
1906 | ||
1907 | @item Z | |
1908 | Any register | |
1909 | ||
1910 | @item I | |
1911 | Signed 11-bit integer constant | |
1912 | ||
1913 | @item J | |
1914 | Signed 14-bit integer constant | |
1915 | ||
1916 | @item K | |
1917 | Integer constant that can be deposited with a @code{zdepi} instruction | |
1918 | ||
1919 | @item L | |
1920 | Signed 5-bit integer constant | |
1921 | ||
1922 | @item M | |
1923 | Integer constant 0 | |
1924 | ||
1925 | @item N | |
1926 | Integer constant that can be loaded with a @code{ldil} instruction | |
1927 | ||
1928 | @item O | |
1929 | Integer constant whose value plus one is a power of 2 | |
1930 | ||
1931 | @item P | |
1932 | Integer constant that can be used for @code{and} operations in @code{depi} | |
1933 | and @code{extru} instructions | |
1934 | ||
1935 | @item S | |
1936 | Integer constant 31 | |
1937 | ||
1938 | @item U | |
1939 | Integer constant 63 | |
1940 | ||
1941 | @item G | |
1942 | Floating-point constant 0.0 | |
1943 | ||
1944 | @item A | |
1945 | A @code{lo_sum} data-linkage-table memory operand | |
1946 | ||
1947 | @item Q | |
1948 | A memory operand that can be used as the destination operand of an | |
1949 | integer store instruction | |
1950 | ||
1951 | @item R | |
1952 | A scaled or unscaled indexed memory operand | |
1953 | ||
1954 | @item T | |
1955 | A memory operand for floating-point loads and stores | |
1956 | ||
1957 | @item W | |
1958 | A register indirect memory operand | |
1959 | @end table | |
1960 | ||
358da97e HS |
1961 | @item picoChip family---@file{picochip.h} |
1962 | @table @code | |
1963 | @item k | |
1964 | Stack register. | |
1965 | ||
1966 | @item f | |
1967 | Pointer register. A register which can be used to access memory without | |
1968 | supplying an offset. Any other register can be used to access memory, | |
1969 | but will need a constant offset. In the case of the offset being zero, | |
1970 | it is more efficient to use a pointer register, since this reduces code | |
1971 | size. | |
1972 | ||
1973 | @item t | |
1974 | A twin register. A register which may be paired with an adjacent | |
1975 | register to create a 32-bit register. | |
1976 | ||
1977 | @item a | |
1978 | Any absolute memory address (e.g., symbolic constant, symbolic | |
1979 | constant + offset). | |
1980 | ||
1981 | @item I | |
1982 | 4-bit signed integer. | |
1983 | ||
1984 | @item J | |
1985 | 4-bit unsigned integer. | |
1986 | ||
1987 | @item K | |
1988 | 8-bit signed integer. | |
1989 | ||
1990 | @item M | |
1991 | Any constant whose absolute value is no greater than 4-bits. | |
1992 | ||
1993 | @item N | |
1994 | 10-bit signed integer | |
1995 | ||
1996 | @item O | |
1997 | 16-bit signed integer. | |
1998 | ||
1999 | @end table | |
2000 | ||
74fe790b | 2001 | @item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h} |
03dda8e3 RK |
2002 | @table @code |
2003 | @item b | |
2004 | Address base register | |
2005 | ||
799dbb0f ME |
2006 | @item d |
2007 | Floating point register (containing 64-bit value) | |
2008 | ||
03dda8e3 | 2009 | @item f |
799dbb0f | 2010 | Floating point register (containing 32-bit value) |
03dda8e3 | 2011 | |
2dcfc29d | 2012 | @item v |
29e6733c MM |
2013 | Altivec vector register |
2014 | ||
2015 | @item wd | |
2016 | VSX vector register to hold vector double data | |
2017 | ||
2018 | @item wf | |
2019 | VSX vector register to hold vector float data | |
2020 | ||
2021 | @item ws | |
2022 | VSX vector register to hold scalar float data | |
2023 | ||
2024 | @item wa | |
2025 | Any VSX register | |
2dcfc29d | 2026 | |
03dda8e3 RK |
2027 | @item h |
2028 | @samp{MQ}, @samp{CTR}, or @samp{LINK} register | |
2029 | ||
2030 | @item q | |
2031 | @samp{MQ} register | |
2032 | ||
2033 | @item c | |
2034 | @samp{CTR} register | |
2035 | ||
2036 | @item l | |
2037 | @samp{LINK} register | |
2038 | ||
2039 | @item x | |
2040 | @samp{CR} register (condition register) number 0 | |
2041 | ||
2042 | @item y | |
2043 | @samp{CR} register (condition register) | |
2044 | ||
8f685459 | 2045 | @item z |
f6b5d695 | 2046 | @samp{XER[CA]} carry bit (part of the XER register) |
8f685459 | 2047 | |
03dda8e3 | 2048 | @item I |
1e5f973d | 2049 | Signed 16-bit constant |
03dda8e3 RK |
2050 | |
2051 | @item J | |
ebb48a4d | 2052 | Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for |
5f59ecb7 | 2053 | @code{SImode} constants) |
03dda8e3 RK |
2054 | |
2055 | @item K | |
1e5f973d | 2056 | Unsigned 16-bit constant |
03dda8e3 RK |
2057 | |
2058 | @item L | |
1e5f973d | 2059 | Signed 16-bit constant shifted left 16 bits |
03dda8e3 RK |
2060 | |
2061 | @item M | |
2062 | Constant larger than 31 | |
2063 | ||
2064 | @item N | |
2065 | Exact power of 2 | |
2066 | ||
2067 | @item O | |
2068 | Zero | |
2069 | ||
2070 | @item P | |
1e5f973d | 2071 | Constant whose negation is a signed 16-bit constant |
03dda8e3 RK |
2072 | |
2073 | @item G | |
2074 | Floating point constant that can be loaded into a register with one | |
2075 | instruction per word | |
2076 | ||
a8a51a97 AP |
2077 | @item H |
2078 | Integer/Floating point constant that can be loaded into a register using | |
2079 | three instructions | |
2080 | ||
1d447995 | 2081 | @item m |
ff2ce160 | 2082 | Memory operand. |
fea31288 JJ |
2083 | Normally, @code{m} does not allow addresses that update the base register. |
2084 | If @samp{<} or @samp{>} constraint is also used, they are allowed and | |
2085 | therefore on PowerPC targets in that case it is only safe | |
2086 | to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement | |
1d447995 RS |
2087 | accesses the operand exactly once. The @code{asm} statement must also |
2088 | use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the | |
2089 | corresponding load or store instruction. For example: | |
2090 | ||
2091 | @smallexample | |
fea31288 | 2092 | asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val)); |
1d447995 RS |
2093 | @end smallexample |
2094 | ||
2095 | is correct but: | |
2096 | ||
2097 | @smallexample | |
fea31288 | 2098 | asm ("st %1,%0" : "=m<>" (mem) : "r" (val)); |
1d447995 RS |
2099 | @end smallexample |
2100 | ||
fea31288 | 2101 | is not. |
1d447995 RS |
2102 | |
2103 | @item es | |
2104 | A ``stable'' memory operand; that is, one which does not include any | |
fea31288 JJ |
2105 | automodification of the base register. This used to be useful when |
2106 | @samp{m} allowed automodification of the base register, but as those are now only | |
2107 | allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same | |
2108 | as @samp{m} without @samp{<} and @samp{>}. | |
1d447995 | 2109 | |
03dda8e3 | 2110 | @item Q |
1d447995 RS |
2111 | Memory operand that is an offset from a register (it is usually better |
2112 | to use @samp{m} or @samp{es} in @code{asm} statements) | |
03dda8e3 | 2113 | |
a8a51a97 | 2114 | @item Z |
1d447995 RS |
2115 | Memory operand that is an indexed or indirect from a register (it is |
2116 | usually better to use @samp{m} or @samp{es} in @code{asm} statements) | |
a8a51a97 | 2117 | |
03dda8e3 RK |
2118 | @item R |
2119 | AIX TOC entry | |
2120 | ||
a8a51a97 AP |
2121 | @item a |
2122 | Address operand that is an indexed or indirect from a register (@samp{p} is | |
2123 | preferable for @code{asm} statements) | |
2124 | ||
03dda8e3 | 2125 | @item S |
8f685459 | 2126 | Constant suitable as a 64-bit mask operand |
03dda8e3 | 2127 | |
5f59ecb7 DE |
2128 | @item T |
2129 | Constant suitable as a 32-bit mask operand | |
2130 | ||
03dda8e3 RK |
2131 | @item U |
2132 | System V Release 4 small data area reference | |
a8a51a97 AP |
2133 | |
2134 | @item t | |
2135 | AND masks that can be performed by two rldic@{l, r@} instructions | |
2136 | ||
2137 | @item W | |
2138 | Vector constant that does not require memory | |
2139 | ||
29e6733c MM |
2140 | @item j |
2141 | Vector constant that is all zeros. | |
2142 | ||
03dda8e3 RK |
2143 | @end table |
2144 | ||
08b1e29a | 2145 | @item Intel 386---@file{config/i386/constraints.md} |
03dda8e3 | 2146 | @table @code |
0c56474e | 2147 | @item R |
f38840db ZW |
2148 | Legacy register---the eight integer registers available on all |
2149 | i386 processors (@code{a}, @code{b}, @code{c}, @code{d}, | |
2150 | @code{si}, @code{di}, @code{bp}, @code{sp}). | |
03dda8e3 | 2151 | |
f38840db ZW |
2152 | @item q |
2153 | Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a}, | |
2154 | @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register. | |
03dda8e3 | 2155 | |
f38840db ZW |
2156 | @item Q |
2157 | Any register accessible as @code{@var{r}h}: @code{a}, @code{b}, | |
2158 | @code{c}, and @code{d}. | |
03dda8e3 | 2159 | |
f38840db ZW |
2160 | @ifset INTERNALS |
2161 | @item l | |
2162 | Any register that can be used as the index in a base+index memory | |
2163 | access: that is, any general register except the stack pointer. | |
2164 | @end ifset | |
03dda8e3 RK |
2165 | |
2166 | @item a | |
f38840db | 2167 | The @code{a} register. |
03dda8e3 RK |
2168 | |
2169 | @item b | |
f38840db | 2170 | The @code{b} register. |
03dda8e3 RK |
2171 | |
2172 | @item c | |
f38840db | 2173 | The @code{c} register. |
f8ca7923 | 2174 | |
03dda8e3 | 2175 | @item d |
f38840db ZW |
2176 | The @code{d} register. |
2177 | ||
2178 | @item S | |
2179 | The @code{si} register. | |
03dda8e3 RK |
2180 | |
2181 | @item D | |
f38840db | 2182 | The @code{di} register. |
03dda8e3 | 2183 | |
f38840db | 2184 | @item A |
ae8358d6 RG |
2185 | The @code{a} and @code{d} registers. This class is used for instructions |
2186 | that return double word results in the @code{ax:dx} register pair. Single | |
2187 | word values will be allocated either in @code{ax} or @code{dx}. | |
2188 | For example on i386 the following implements @code{rdtsc}: | |
2189 | ||
2190 | @smallexample | |
2191 | unsigned long long rdtsc (void) | |
2192 | @{ | |
2193 | unsigned long long tick; | |
2194 | __asm__ __volatile__("rdtsc":"=A"(tick)); | |
2195 | return tick; | |
2196 | @} | |
2197 | @end smallexample | |
2198 | ||
2199 | This is not correct on x86_64 as it would allocate tick in either @code{ax} | |
2200 | or @code{dx}. You have to use the following variant instead: | |
2201 | ||
2202 | @smallexample | |
2203 | unsigned long long rdtsc (void) | |
2204 | @{ | |
2205 | unsigned int tickl, tickh; | |
2206 | __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh)); | |
2207 | return ((unsigned long long)tickh << 32)|tickl; | |
2208 | @} | |
2209 | @end smallexample | |
2210 | ||
03dda8e3 | 2211 | |
f38840db ZW |
2212 | @item f |
2213 | Any 80387 floating-point (stack) register. | |
2214 | ||
2215 | @item t | |
2216 | Top of 80387 floating-point stack (@code{%st(0)}). | |
2217 | ||
2218 | @item u | |
2219 | Second from top of 80387 floating-point stack (@code{%st(1)}). | |
994682b9 AJ |
2220 | |
2221 | @item y | |
f38840db ZW |
2222 | Any MMX register. |
2223 | ||
2224 | @item x | |
2225 | Any SSE register. | |
2226 | ||
c5245af5 L |
2227 | @item Yz |
2228 | First SSE register (@code{%xmm0}). | |
2229 | ||
f38840db | 2230 | @ifset INTERNALS |
c5245af5 L |
2231 | @item Y2 |
2232 | Any SSE register, when SSE2 is enabled. | |
2233 | ||
2234 | @item Yi | |
2235 | Any SSE register, when SSE2 and inter-unit moves are enabled. | |
2236 | ||
2237 | @item Ym | |
2238 | Any MMX register, when inter-unit moves are enabled. | |
f38840db | 2239 | @end ifset |
994682b9 | 2240 | |
03dda8e3 | 2241 | @item I |
f38840db | 2242 | Integer constant in the range 0 @dots{} 31, for 32-bit shifts. |
03dda8e3 RK |
2243 | |
2244 | @item J | |
f38840db | 2245 | Integer constant in the range 0 @dots{} 63, for 64-bit shifts. |
03dda8e3 RK |
2246 | |
2247 | @item K | |
f38840db | 2248 | Signed 8-bit integer constant. |
03dda8e3 RK |
2249 | |
2250 | @item L | |
f38840db | 2251 | @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move. |
03dda8e3 RK |
2252 | |
2253 | @item M | |
f38840db | 2254 | 0, 1, 2, or 3 (shifts for the @code{lea} instruction). |
03dda8e3 RK |
2255 | |
2256 | @item N | |
ff2ce160 | 2257 | Unsigned 8-bit integer constant (for @code{in} and @code{out} |
f38840db | 2258 | instructions). |
03dda8e3 | 2259 | |
f38840db ZW |
2260 | @ifset INTERNALS |
2261 | @item O | |
2262 | Integer constant in the range 0 @dots{} 127, for 128-bit shifts. | |
2263 | @end ifset | |
2264 | ||
2265 | @item G | |
2266 | Standard 80387 floating point constant. | |
2267 | ||
2268 | @item C | |
2269 | Standard SSE floating point constant. | |
0c56474e JH |
2270 | |
2271 | @item e | |
f38840db ZW |
2272 | 32-bit signed integer constant, or a symbolic reference known |
2273 | to fit that range (for immediate operands in sign-extending x86-64 | |
2274 | instructions). | |
2275 | ||
2276 | @item Z | |
2277 | 32-bit unsigned integer constant, or a symbolic reference known | |
2278 | to fit that range (for immediate operands in zero-extending x86-64 | |
2279 | instructions). | |
0c56474e | 2280 | |
03dda8e3 RK |
2281 | @end table |
2282 | ||
74fe790b | 2283 | @item Intel IA-64---@file{config/ia64/ia64.h} |
7a430e3b SC |
2284 | @table @code |
2285 | @item a | |
2286 | General register @code{r0} to @code{r3} for @code{addl} instruction | |
2287 | ||
2288 | @item b | |
2289 | Branch register | |
2290 | ||
2291 | @item c | |
2292 | Predicate register (@samp{c} as in ``conditional'') | |
2293 | ||
2294 | @item d | |
2295 | Application register residing in M-unit | |
2296 | ||
2297 | @item e | |
2298 | Application register residing in I-unit | |
2299 | ||
2300 | @item f | |
2301 | Floating-point register | |
2302 | ||
2303 | @item m | |
fea31288 JJ |
2304 | Memory operand. If used together with @samp{<} or @samp{>}, |
2305 | the operand can have postincrement and postdecrement which | |
7a430e3b | 2306 | require printing with @samp{%Pn} on IA-64. |
7a430e3b SC |
2307 | |
2308 | @item G | |
2309 | Floating-point constant 0.0 or 1.0 | |
2310 | ||
2311 | @item I | |
2312 | 14-bit signed integer constant | |
2313 | ||
2314 | @item J | |
2315 | 22-bit signed integer constant | |
2316 | ||
2317 | @item K | |
2318 | 8-bit signed integer constant for logical instructions | |
2319 | ||
2320 | @item L | |
2321 | 8-bit adjusted signed integer constant for compare pseudo-ops | |
2322 | ||
2323 | @item M | |
2324 | 6-bit unsigned integer constant for shift counts | |
2325 | ||
2326 | @item N | |
2327 | 9-bit signed integer constant for load and store postincrements | |
2328 | ||
2329 | @item O | |
2330 | The constant zero | |
2331 | ||
2332 | @item P | |
78466c0e | 2333 | 0 or @minus{}1 for @code{dep} instruction |
7a430e3b SC |
2334 | |
2335 | @item Q | |
2336 | Non-volatile memory for floating-point loads and stores | |
2337 | ||
2338 | @item R | |
2339 | Integer constant in the range 1 to 4 for @code{shladd} instruction | |
2340 | ||
2341 | @item S | |
fea31288 JJ |
2342 | Memory operand except postincrement and postdecrement. This is |
2343 | now roughly the same as @samp{m} when not used together with @samp{<} | |
2344 | or @samp{>}. | |
7a430e3b | 2345 | @end table |
03dda8e3 | 2346 | |
74fe790b | 2347 | @item FRV---@file{config/frv/frv.h} |
70899148 BS |
2348 | @table @code |
2349 | @item a | |
840758d3 | 2350 | Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}). |
70899148 BS |
2351 | |
2352 | @item b | |
840758d3 | 2353 | Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}). |
70899148 BS |
2354 | |
2355 | @item c | |
840758d3 BS |
2356 | Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and |
2357 | @code{icc0} to @code{icc3}). | |
70899148 BS |
2358 | |
2359 | @item d | |
840758d3 | 2360 | Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}). |
70899148 BS |
2361 | |
2362 | @item e | |
840758d3 | 2363 | Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}). |
70899148 BS |
2364 | Odd registers are excluded not in the class but through the use of a machine |
2365 | mode larger than 4 bytes. | |
2366 | ||
2367 | @item f | |
840758d3 | 2368 | Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}). |
70899148 BS |
2369 | |
2370 | @item h | |
840758d3 | 2371 | Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}). |
70899148 BS |
2372 | Odd registers are excluded not in the class but through the use of a machine |
2373 | mode larger than 4 bytes. | |
2374 | ||
2375 | @item l | |
840758d3 | 2376 | Register in the class @code{LR_REG} (the @code{lr} register). |
70899148 BS |
2377 | |
2378 | @item q | |
840758d3 | 2379 | Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}). |
70899148 BS |
2380 | Register numbers not divisible by 4 are excluded not in the class but through |
2381 | the use of a machine mode larger than 8 bytes. | |
2382 | ||
2383 | @item t | |
840758d3 | 2384 | Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}). |
70899148 BS |
2385 | |
2386 | @item u | |
840758d3 | 2387 | Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}). |
70899148 BS |
2388 | |
2389 | @item v | |
840758d3 | 2390 | Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}). |
70899148 BS |
2391 | |
2392 | @item w | |
840758d3 | 2393 | Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}). |
70899148 BS |
2394 | |
2395 | @item x | |
840758d3 | 2396 | Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}). |
70899148 BS |
2397 | Register numbers not divisible by 4 are excluded not in the class but through |
2398 | the use of a machine mode larger than 8 bytes. | |
2399 | ||
2400 | @item z | |
840758d3 | 2401 | Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}). |
70899148 BS |
2402 | |
2403 | @item A | |
840758d3 | 2404 | Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}). |
70899148 BS |
2405 | |
2406 | @item B | |
840758d3 | 2407 | Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}). |
70899148 BS |
2408 | |
2409 | @item C | |
840758d3 | 2410 | Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}). |
70899148 BS |
2411 | |
2412 | @item G | |
2413 | Floating point constant zero | |
2414 | ||
2415 | @item I | |
2416 | 6-bit signed integer constant | |
2417 | ||
2418 | @item J | |
2419 | 10-bit signed integer constant | |
2420 | ||
2421 | @item L | |
2422 | 16-bit signed integer constant | |
2423 | ||
2424 | @item M | |
2425 | 16-bit unsigned integer constant | |
2426 | ||
2427 | @item N | |
840758d3 BS |
2428 | 12-bit signed integer constant that is negative---i.e.@: in the |
2429 | range of @minus{}2048 to @minus{}1 | |
70899148 BS |
2430 | |
2431 | @item O | |
2432 | Constant zero | |
2433 | ||
2434 | @item P | |
840758d3 | 2435 | 12-bit signed integer constant that is greater than zero---i.e.@: in the |
70899148 BS |
2436 | range of 1 to 2047. |
2437 | ||
2438 | @end table | |
2439 | ||
9fdd7520 | 2440 | @item Blackfin family---@file{config/bfin/constraints.md} |
0d4a78eb BS |
2441 | @table @code |
2442 | @item a | |
2443 | P register | |
2444 | ||
2445 | @item d | |
2446 | D register | |
2447 | ||
2448 | @item z | |
2449 | A call clobbered P register. | |
2450 | ||
03848bd0 BS |
2451 | @item q@var{n} |
2452 | A single register. If @var{n} is in the range 0 to 7, the corresponding D | |
2453 | register. If it is @code{A}, then the register P0. | |
2454 | ||
0d4a78eb BS |
2455 | @item D |
2456 | Even-numbered D register | |
2457 | ||
2458 | @item W | |
2459 | Odd-numbered D register | |
2460 | ||
2461 | @item e | |
2462 | Accumulator register. | |
2463 | ||
2464 | @item A | |
2465 | Even-numbered accumulator register. | |
2466 | ||
2467 | @item B | |
2468 | Odd-numbered accumulator register. | |
2469 | ||
2470 | @item b | |
2471 | I register | |
2472 | ||
a9c46998 | 2473 | @item v |
0d4a78eb BS |
2474 | B register |
2475 | ||
2476 | @item f | |
2477 | M register | |
2478 | ||
2479 | @item c | |
2480 | Registers used for circular buffering, i.e. I, B, or L registers. | |
2481 | ||
2482 | @item C | |
2483 | The CC register. | |
2484 | ||
a9c46998 JZ |
2485 | @item t |
2486 | LT0 or LT1. | |
2487 | ||
2488 | @item k | |
2489 | LC0 or LC1. | |
2490 | ||
2491 | @item u | |
2492 | LB0 or LB1. | |
2493 | ||
0d4a78eb BS |
2494 | @item x |
2495 | Any D, P, B, M, I or L register. | |
2496 | ||
2497 | @item y | |
2498 | Additional registers typically used only in prologues and epilogues: RETS, | |
2499 | RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP. | |
2500 | ||
2501 | @item w | |
2502 | Any register except accumulators or CC. | |
2503 | ||
2504 | @item Ksh | |
8ad1dde7 | 2505 | Signed 16 bit integer (in the range @minus{}32768 to 32767) |
0d4a78eb BS |
2506 | |
2507 | @item Kuh | |
2508 | Unsigned 16 bit integer (in the range 0 to 65535) | |
2509 | ||
2510 | @item Ks7 | |
8ad1dde7 | 2511 | Signed 7 bit integer (in the range @minus{}64 to 63) |
0d4a78eb BS |
2512 | |
2513 | @item Ku7 | |
2514 | Unsigned 7 bit integer (in the range 0 to 127) | |
2515 | ||
2516 | @item Ku5 | |
2517 | Unsigned 5 bit integer (in the range 0 to 31) | |
2518 | ||
2519 | @item Ks4 | |
8ad1dde7 | 2520 | Signed 4 bit integer (in the range @minus{}8 to 7) |
0d4a78eb BS |
2521 | |
2522 | @item Ks3 | |
8ad1dde7 | 2523 | Signed 3 bit integer (in the range @minus{}3 to 4) |
0d4a78eb BS |
2524 | |
2525 | @item Ku3 | |
2526 | Unsigned 3 bit integer (in the range 0 to 7) | |
2527 | ||
2528 | @item P@var{n} | |
2529 | Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4. | |
2530 | ||
3efd5670 BS |
2531 | @item PA |
2532 | An integer equal to one of the MACFLAG_XXX constants that is suitable for | |
2533 | use with either accumulator. | |
2534 | ||
2535 | @item PB | |
2536 | An integer equal to one of the MACFLAG_XXX constants that is suitable for | |
2537 | use only with accumulator A1. | |
2538 | ||
0d4a78eb BS |
2539 | @item M1 |
2540 | Constant 255. | |
2541 | ||
2542 | @item M2 | |
2543 | Constant 65535. | |
2544 | ||
2545 | @item J | |
2546 | An integer constant with exactly a single bit set. | |
2547 | ||
2548 | @item L | |
2549 | An integer constant with all bits set except exactly one. | |
2550 | ||
2551 | @item H | |
2552 | ||
2553 | @item Q | |
2554 | Any SYMBOL_REF. | |
2555 | @end table | |
2556 | ||
74fe790b ZW |
2557 | @item M32C---@file{config/m32c/m32c.c} |
2558 | @table @code | |
38b2d076 DD |
2559 | @item Rsp |
2560 | @itemx Rfb | |
2561 | @itemx Rsb | |
2562 | @samp{$sp}, @samp{$fb}, @samp{$sb}. | |
2563 | ||
2564 | @item Rcr | |
2565 | Any control register, when they're 16 bits wide (nothing if control | |
2566 | registers are 24 bits wide) | |
2567 | ||
2568 | @item Rcl | |
2569 | Any control register, when they're 24 bits wide. | |
2570 | ||
2571 | @item R0w | |
2572 | @itemx R1w | |
2573 | @itemx R2w | |
2574 | @itemx R3w | |
2575 | $r0, $r1, $r2, $r3. | |
2576 | ||
2577 | @item R02 | |
2578 | $r0 or $r2, or $r2r0 for 32 bit values. | |
2579 | ||
2580 | @item R13 | |
2581 | $r1 or $r3, or $r3r1 for 32 bit values. | |
2582 | ||
2583 | @item Rdi | |
2584 | A register that can hold a 64 bit value. | |
2585 | ||
2586 | @item Rhl | |
2587 | $r0 or $r1 (registers with addressable high/low bytes) | |
2588 | ||
2589 | @item R23 | |
2590 | $r2 or $r3 | |
2591 | ||
2592 | @item Raa | |
2593 | Address registers | |
2594 | ||
2595 | @item Raw | |
2596 | Address registers when they're 16 bits wide. | |
2597 | ||
2598 | @item Ral | |
2599 | Address registers when they're 24 bits wide. | |
2600 | ||
2601 | @item Rqi | |
2602 | Registers that can hold QI values. | |
2603 | ||
2604 | @item Rad | |
2605 | Registers that can be used with displacements ($a0, $a1, $sb). | |
2606 | ||
2607 | @item Rsi | |
2608 | Registers that can hold 32 bit values. | |
2609 | ||
2610 | @item Rhi | |
2611 | Registers that can hold 16 bit values. | |
2612 | ||
2613 | @item Rhc | |
2614 | Registers chat can hold 16 bit values, including all control | |
2615 | registers. | |
2616 | ||
2617 | @item Rra | |
2618 | $r0 through R1, plus $a0 and $a1. | |
2619 | ||
2620 | @item Rfl | |
2621 | The flags register. | |
2622 | ||
2623 | @item Rmm | |
2624 | The memory-based pseudo-registers $mem0 through $mem15. | |
2625 | ||
2626 | @item Rpi | |
2627 | Registers that can hold pointers (16 bit registers for r8c, m16c; 24 | |
2628 | bit registers for m32cm, m32c). | |
2629 | ||
2630 | @item Rpa | |
2631 | Matches multiple registers in a PARALLEL to form a larger register. | |
2632 | Used to match function return values. | |
2633 | ||
2634 | @item Is3 | |
8ad1dde7 | 2635 | @minus{}8 @dots{} 7 |
38b2d076 DD |
2636 | |
2637 | @item IS1 | |
8ad1dde7 | 2638 | @minus{}128 @dots{} 127 |
38b2d076 DD |
2639 | |
2640 | @item IS2 | |
8ad1dde7 | 2641 | @minus{}32768 @dots{} 32767 |
38b2d076 DD |
2642 | |
2643 | @item IU2 | |
2644 | 0 @dots{} 65535 | |
2645 | ||
2646 | @item In4 | |
8ad1dde7 | 2647 | @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8 |
38b2d076 DD |
2648 | |
2649 | @item In5 | |
8ad1dde7 | 2650 | @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16 |
38b2d076 | 2651 | |
23fed240 | 2652 | @item In6 |
8ad1dde7 | 2653 | @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32 |
38b2d076 DD |
2654 | |
2655 | @item IM2 | |
8ad1dde7 | 2656 | @minus{}65536 @dots{} @minus{}1 |
38b2d076 DD |
2657 | |
2658 | @item Ilb | |
2659 | An 8 bit value with exactly one bit set. | |
2660 | ||
2661 | @item Ilw | |
2662 | A 16 bit value with exactly one bit set. | |
2663 | ||
2664 | @item Sd | |
2665 | The common src/dest memory addressing modes. | |
2666 | ||
2667 | @item Sa | |
2668 | Memory addressed using $a0 or $a1. | |
2669 | ||
2670 | @item Si | |
2671 | Memory addressed with immediate addresses. | |
2672 | ||
2673 | @item Ss | |
2674 | Memory addressed using the stack pointer ($sp). | |
2675 | ||
2676 | @item Sf | |
2677 | Memory addressed using the frame base register ($fb). | |
2678 | ||
2679 | @item Ss | |
2680 | Memory addressed using the small base register ($sb). | |
2681 | ||
2682 | @item S1 | |
2683 | $r1h | |
e2491744 DD |
2684 | @end table |
2685 | ||
2686 | @item MeP---@file{config/mep/constraints.md} | |
2687 | @table @code | |
2688 | ||
2689 | @item a | |
2690 | The $sp register. | |
2691 | ||
2692 | @item b | |
2693 | The $tp register. | |
2694 | ||
2695 | @item c | |
2696 | Any control register. | |
2697 | ||
2698 | @item d | |
2699 | Either the $hi or the $lo register. | |
2700 | ||
2701 | @item em | |
2702 | Coprocessor registers that can be directly loaded ($c0-$c15). | |
2703 | ||
2704 | @item ex | |
2705 | Coprocessor registers that can be moved to each other. | |
2706 | ||
2707 | @item er | |
2708 | Coprocessor registers that can be moved to core registers. | |
2709 | ||
2710 | @item h | |
2711 | The $hi register. | |
2712 | ||
2713 | @item j | |
2714 | The $rpc register. | |
2715 | ||
2716 | @item l | |
2717 | The $lo register. | |
2718 | ||
2719 | @item t | |
2720 | Registers which can be used in $tp-relative addressing. | |
2721 | ||
2722 | @item v | |
2723 | The $gp register. | |
2724 | ||
2725 | @item x | |
2726 | The coprocessor registers. | |
2727 | ||
2728 | @item y | |
2729 | The coprocessor control registers. | |
2730 | ||
2731 | @item z | |
2732 | The $0 register. | |
2733 | ||
2734 | @item A | |
2735 | User-defined register set A. | |
2736 | ||
2737 | @item B | |
2738 | User-defined register set B. | |
2739 | ||
2740 | @item C | |
2741 | User-defined register set C. | |
2742 | ||
2743 | @item D | |
2744 | User-defined register set D. | |
2745 | ||
2746 | @item I | |
2747 | Offsets for $gp-rel addressing. | |
2748 | ||
2749 | @item J | |
2750 | Constants that can be used directly with boolean insns. | |
2751 | ||
2752 | @item K | |
2753 | Constants that can be moved directly to registers. | |
2754 | ||
2755 | @item L | |
2756 | Small constants that can be added to registers. | |
2757 | ||
2758 | @item M | |
2759 | Long shift counts. | |
2760 | ||
2761 | @item N | |
2762 | Small constants that can be compared to registers. | |
2763 | ||
2764 | @item O | |
2765 | Constants that can be loaded into the top half of registers. | |
2766 | ||
2767 | @item S | |
2768 | Signed 8-bit immediates. | |
2769 | ||
2770 | @item T | |
2771 | Symbols encoded for $tp-rel or $gp-rel addressing. | |
2772 | ||
2773 | @item U | |
2774 | Non-constant addresses for loading/saving coprocessor registers. | |
2775 | ||
2776 | @item W | |
2777 | The top half of a symbol's value. | |
2778 | ||
2779 | @item Y | |
2780 | A register indirect address without offset. | |
2781 | ||
2782 | @item Z | |
2783 | Symbolic references to the control bus. | |
2784 | ||
80920132 | 2785 | @end table |
e2491744 | 2786 | |
80920132 ME |
2787 | @item MicroBlaze---@file{config/microblaze/constraints.md} |
2788 | @table @code | |
2789 | @item d | |
2790 | A general register (@code{r0} to @code{r31}). | |
2791 | ||
2792 | @item z | |
2793 | A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}). | |
e2491744 | 2794 | |
74fe790b | 2795 | @end table |
38b2d076 | 2796 | |
cbbb5b6d | 2797 | @item MIPS---@file{config/mips/constraints.md} |
4226378a PK |
2798 | @table @code |
2799 | @item d | |
cbbb5b6d RS |
2800 | An address register. This is equivalent to @code{r} unless |
2801 | generating MIPS16 code. | |
4226378a PK |
2802 | |
2803 | @item f | |
cbbb5b6d | 2804 | A floating-point register (if available). |
4226378a PK |
2805 | |
2806 | @item h | |
21dfc6dc | 2807 | Formerly the @code{hi} register. This constraint is no longer supported. |
4226378a PK |
2808 | |
2809 | @item l | |
21dfc6dc RS |
2810 | The @code{lo} register. Use this register to store values that are |
2811 | no bigger than a word. | |
4226378a PK |
2812 | |
2813 | @item x | |
21dfc6dc RS |
2814 | The concatenated @code{hi} and @code{lo} registers. Use this register |
2815 | to store doubleword values. | |
cbbb5b6d RS |
2816 | |
2817 | @item c | |
2818 | A register suitable for use in an indirect jump. This will always be | |
2819 | @code{$25} for @option{-mabicalls}. | |
4226378a | 2820 | |
2feaae20 RS |
2821 | @item v |
2822 | Register @code{$3}. Do not use this constraint in new code; | |
2823 | it is retained only for compatibility with glibc. | |
2824 | ||
4226378a | 2825 | @item y |
cbbb5b6d | 2826 | Equivalent to @code{r}; retained for backwards compatibility. |
4226378a PK |
2827 | |
2828 | @item z | |
cbbb5b6d | 2829 | A floating-point condition code register. |
4226378a PK |
2830 | |
2831 | @item I | |
cbbb5b6d | 2832 | A signed 16-bit constant (for arithmetic instructions). |
4226378a PK |
2833 | |
2834 | @item J | |
cbbb5b6d | 2835 | Integer zero. |
4226378a PK |
2836 | |
2837 | @item K | |
cbbb5b6d | 2838 | An unsigned 16-bit constant (for logic instructions). |
4226378a PK |
2839 | |
2840 | @item L | |
cbbb5b6d RS |
2841 | A signed 32-bit constant in which the lower 16 bits are zero. |
2842 | Such constants can be loaded using @code{lui}. | |
4226378a PK |
2843 | |
2844 | @item M | |
cbbb5b6d RS |
2845 | A constant that cannot be loaded using @code{lui}, @code{addiu} |
2846 | or @code{ori}. | |
4226378a PK |
2847 | |
2848 | @item N | |
8ad1dde7 | 2849 | A constant in the range @minus{}65535 to @minus{}1 (inclusive). |
4226378a PK |
2850 | |
2851 | @item O | |
cbbb5b6d | 2852 | A signed 15-bit constant. |
4226378a PK |
2853 | |
2854 | @item P | |
cbbb5b6d | 2855 | A constant in the range 1 to 65535 (inclusive). |
4226378a PK |
2856 | |
2857 | @item G | |
cbbb5b6d | 2858 | Floating-point zero. |
4226378a PK |
2859 | |
2860 | @item R | |
cbbb5b6d | 2861 | An address that can be used in a non-macro load or store. |
4226378a PK |
2862 | @end table |
2863 | ||
c47b0cb4 | 2864 | @item Motorola 680x0---@file{config/m68k/constraints.md} |
03dda8e3 RK |
2865 | @table @code |
2866 | @item a | |
2867 | Address register | |
2868 | ||
2869 | @item d | |
2870 | Data register | |
2871 | ||
2872 | @item f | |
2873 | 68881 floating-point register, if available | |
2874 | ||
03dda8e3 RK |
2875 | @item I |
2876 | Integer in the range 1 to 8 | |
2877 | ||
2878 | @item J | |
1e5f973d | 2879 | 16-bit signed number |
03dda8e3 RK |
2880 | |
2881 | @item K | |
2882 | Signed number whose magnitude is greater than 0x80 | |
2883 | ||
2884 | @item L | |
630d3d5a | 2885 | Integer in the range @minus{}8 to @minus{}1 |
03dda8e3 RK |
2886 | |
2887 | @item M | |
2888 | Signed number whose magnitude is greater than 0x100 | |
2889 | ||
c47b0cb4 MK |
2890 | @item N |
2891 | Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate | |
2892 | ||
2893 | @item O | |
2894 | 16 (for rotate using swap) | |
2895 | ||
2896 | @item P | |
2897 | Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate | |
2898 | ||
2899 | @item R | |
2900 | Numbers that mov3q can handle | |
2901 | ||
03dda8e3 RK |
2902 | @item G |
2903 | Floating point constant that is not a 68881 constant | |
c47b0cb4 MK |
2904 | |
2905 | @item S | |
2906 | Operands that satisfy 'm' when -mpcrel is in effect | |
2907 | ||
2908 | @item T | |
2909 | Operands that satisfy 's' when -mpcrel is not in effect | |
2910 | ||
2911 | @item Q | |
2912 | Address register indirect addressing mode | |
2913 | ||
2914 | @item U | |
2915 | Register offset addressing | |
2916 | ||
2917 | @item W | |
2918 | const_call_operand | |
2919 | ||
2920 | @item Cs | |
2921 | symbol_ref or const | |
2922 | ||
2923 | @item Ci | |
2924 | const_int | |
2925 | ||
2926 | @item C0 | |
2927 | const_int 0 | |
2928 | ||
2929 | @item Cj | |
2930 | Range of signed numbers that don't fit in 16 bits | |
2931 | ||
2932 | @item Cmvq | |
2933 | Integers valid for mvq | |
2934 | ||
2935 | @item Capsw | |
2936 | Integers valid for a moveq followed by a swap | |
2937 | ||
2938 | @item Cmvz | |
2939 | Integers valid for mvz | |
2940 | ||
2941 | @item Cmvs | |
2942 | Integers valid for mvs | |
2943 | ||
2944 | @item Ap | |
2945 | push_operand | |
2946 | ||
2947 | @item Ac | |
2948 | Non-register operands allowed in clr | |
2949 | ||
03dda8e3 RK |
2950 | @end table |
2951 | ||
cceb575c AG |
2952 | @item Moxie---@file{config/moxie/constraints.md} |
2953 | @table @code | |
2954 | @item A | |
2955 | An absolute address | |
2956 | ||
2957 | @item B | |
2958 | An offset address | |
2959 | ||
2960 | @item W | |
2961 | A register indirect memory operand | |
2962 | ||
2963 | @item I | |
2964 | A constant in the range of 0 to 255. | |
2965 | ||
2966 | @item N | |
8ad1dde7 | 2967 | A constant in the range of 0 to @minus{}255. |
cceb575c AG |
2968 | |
2969 | @end table | |
2970 | ||
5e426dd4 PK |
2971 | @item PDP-11---@file{config/pdp11/constraints.md} |
2972 | @table @code | |
2973 | @item a | |
2974 | Floating point registers AC0 through AC3. These can be loaded from/to | |
2975 | memory with a single instruction. | |
2976 | ||
2977 | @item d | |
868e54d1 PK |
2978 | Odd numbered general registers (R1, R3, R5). These are used for |
2979 | 16-bit multiply operations. | |
5e426dd4 PK |
2980 | |
2981 | @item f | |
2982 | Any of the floating point registers (AC0 through AC5). | |
2983 | ||
2984 | @item G | |
2985 | Floating point constant 0. | |
2986 | ||
2987 | @item I | |
2988 | An integer constant that fits in 16 bits. | |
2989 | ||
2990 | @item J | |
2991 | An integer constant whose low order 16 bits are zero. | |
2992 | ||
2993 | @item K | |
2994 | An integer constant that does not meet the constraints for codes | |
2995 | @samp{I} or @samp{J}. | |
2996 | ||
2997 | @item L | |
2998 | The integer constant 1. | |
2999 | ||
3000 | @item M | |
868e54d1 | 3001 | The integer constant @minus{}1. |
5e426dd4 PK |
3002 | |
3003 | @item N | |
3004 | The integer constant 0. | |
3005 | ||
3006 | @item O | |
868e54d1 | 3007 | Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these |
5e426dd4 PK |
3008 | amounts are handled as multiple single-bit shifts rather than a single |
3009 | variable-length shift. | |
3010 | ||
3011 | @item Q | |
3012 | A memory reference which requires an additional word (address or | |
3013 | offset) after the opcode. | |
3014 | ||
3015 | @item R | |
3016 | A memory reference that is encoded within the opcode. | |
3017 | ||
3018 | @end table | |
3019 | ||
85b8555e DD |
3020 | @item RL78---@file{config/rl78/constraints.md} |
3021 | @table @code | |
3022 | ||
3023 | @item Int3 | |
3024 | An integer constant in the range 1 @dots{} 7. | |
3025 | @item Int8 | |
3026 | An integer constant in the range 0 @dots{} 255. | |
3027 | @item J | |
3028 | An integer constant in the range @minus{}255 @dots{} 0 | |
3029 | @item K | |
3030 | The integer constant 1. | |
3031 | @item L | |
3032 | The integer constant -1. | |
3033 | @item M | |
3034 | The integer constant 0. | |
3035 | @item N | |
3036 | The integer constant 2. | |
3037 | @item O | |
3038 | The integer constant -2. | |
3039 | @item P | |
3040 | An integer constant in the range 1 @dots{} 15. | |
3041 | @item Qbi | |
3042 | The built-in compare types--eq, ne, gtu, ltu, geu, and leu. | |
3043 | @item Qsc | |
3044 | The synthetic compare types--gt, lt, ge, and le. | |
3045 | @item Wab | |
3046 | A memory reference with an absolute address. | |
3047 | @item Wbc | |
3048 | A memory reference using @code{BC} as a base register, with an optional offset. | |
3049 | @item Wca | |
3050 | A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls. | |
3051 | @item Wcv | |
3052 | A memory reference using any 16-bit register pair for the address, for calls. | |
3053 | @item Wd2 | |
3054 | A memory reference using @code{DE} as a base register, with an optional offset. | |
3055 | @item Wde | |
3056 | A memory reference using @code{DE} as a base register, without any offset. | |
3057 | @item Wfr | |
3058 | Any memory reference to an address in the far address space. | |
3059 | @item Wh1 | |
3060 | A memory reference using @code{HL} as a base register, with an optional one-byte offset. | |
3061 | @item Whb | |
3062 | A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register. | |
3063 | @item Whl | |
3064 | A memory reference using @code{HL} as a base register, without any offset. | |
3065 | @item Ws1 | |
3066 | A memory reference using @code{SP} as a base register, with an optional one-byte offset. | |
3067 | @item Y | |
3068 | Any memory reference to an address in the near address space. | |
3069 | @item A | |
3070 | The @code{AX} register. | |
3071 | @item B | |
3072 | The @code{BC} register. | |
3073 | @item D | |
3074 | The @code{DE} register. | |
3075 | @item R | |
3076 | @code{A} through @code{L} registers. | |
3077 | @item S | |
3078 | The @code{SP} register. | |
3079 | @item T | |
3080 | The @code{HL} register. | |
3081 | @item Z08W | |
3082 | The 16-bit @code{R8} register. | |
3083 | @item Z10W | |
3084 | The 16-bit @code{R10} register. | |
3085 | @item Zint | |
3086 | The registers reserved for interrupts (@code{R24} to @code{R31}). | |
3087 | @item a | |
3088 | The @code{A} register. | |
3089 | @item b | |
3090 | The @code{B} register. | |
3091 | @item c | |
3092 | The @code{C} register. | |
3093 | @item d | |
3094 | The @code{D} register. | |
3095 | @item e | |
3096 | The @code{E} register. | |
3097 | @item h | |
3098 | The @code{H} register. | |
3099 | @item l | |
3100 | The @code{L} register. | |
3101 | @item v | |
3102 | The virtual registers. | |
3103 | @item w | |
3104 | The @code{PSW} register. | |
3105 | @item x | |
3106 | The @code{X} register. | |
3107 | ||
3108 | @end table | |
3109 | ||
65a324b4 NC |
3110 | @item RX---@file{config/rx/constraints.md} |
3111 | @table @code | |
3112 | @item Q | |
3113 | An address which does not involve register indirect addressing or | |
3114 | pre/post increment/decrement addressing. | |
3115 | ||
3116 | @item Symbol | |
3117 | A symbol reference. | |
3118 | ||
3119 | @item Int08 | |
3120 | A constant in the range @minus{}256 to 255, inclusive. | |
3121 | ||
3122 | @item Sint08 | |
3123 | A constant in the range @minus{}128 to 127, inclusive. | |
3124 | ||
3125 | @item Sint16 | |
3126 | A constant in the range @minus{}32768 to 32767, inclusive. | |
3127 | ||
3128 | @item Sint24 | |
3129 | A constant in the range @minus{}8388608 to 8388607, inclusive. | |
3130 | ||
3131 | @item Uint04 | |
3132 | A constant in the range 0 to 15, inclusive. | |
3133 | ||
3134 | @end table | |
3135 | ||
03dda8e3 | 3136 | @need 1000 |
74fe790b | 3137 | @item SPARC---@file{config/sparc/sparc.h} |
03dda8e3 RK |
3138 | @table @code |
3139 | @item f | |
53e5f173 EB |
3140 | Floating-point register on the SPARC-V8 architecture and |
3141 | lower floating-point register on the SPARC-V9 architecture. | |
03dda8e3 RK |
3142 | |
3143 | @item e | |
8a36672b | 3144 | Floating-point register. It is equivalent to @samp{f} on the |
53e5f173 EB |
3145 | SPARC-V8 architecture and contains both lower and upper |
3146 | floating-point registers on the SPARC-V9 architecture. | |
03dda8e3 | 3147 | |
8a69f99f EB |
3148 | @item c |
3149 | Floating-point condition code register. | |
3150 | ||
3151 | @item d | |
8a36672b | 3152 | Lower floating-point register. It is only valid on the SPARC-V9 |
53e5f173 | 3153 | architecture when the Visual Instruction Set is available. |
8a69f99f EB |
3154 | |
3155 | @item b | |
8a36672b | 3156 | Floating-point register. It is only valid on the SPARC-V9 architecture |
53e5f173 | 3157 | when the Visual Instruction Set is available. |
8a69f99f EB |
3158 | |
3159 | @item h | |
3160 | 64-bit global or out register for the SPARC-V8+ architecture. | |
3161 | ||
66e62b49 KH |
3162 | @item D |
3163 | A vector constant | |
3164 | ||
03dda8e3 | 3165 | @item I |
1e5f973d | 3166 | Signed 13-bit constant |
03dda8e3 RK |
3167 | |
3168 | @item J | |
3169 | Zero | |
3170 | ||
3171 | @item K | |
1e5f973d | 3172 | 32-bit constant with the low 12 bits clear (a constant that can be |
03dda8e3 RK |
3173 | loaded with the @code{sethi} instruction) |
3174 | ||
7d6040e8 AO |
3175 | @item L |
3176 | A constant in the range supported by @code{movcc} instructions | |
3177 | ||
3178 | @item M | |
3179 | A constant in the range supported by @code{movrcc} instructions | |
3180 | ||
3181 | @item N | |
3182 | Same as @samp{K}, except that it verifies that bits that are not in the | |
57694e40 | 3183 | lower 32-bit range are all zero. Must be used instead of @samp{K} for |
7d6040e8 AO |
3184 | modes wider than @code{SImode} |
3185 | ||
ef0139b1 EB |
3186 | @item O |
3187 | The constant 4096 | |
3188 | ||
03dda8e3 RK |
3189 | @item G |
3190 | Floating-point zero | |
3191 | ||
3192 | @item H | |
1e5f973d | 3193 | Signed 13-bit constant, sign-extended to 32 or 64 bits |
03dda8e3 RK |
3194 | |
3195 | @item Q | |
62190128 DM |
3196 | Floating-point constant whose integral representation can |
3197 | be moved into an integer register using a single sethi | |
3198 | instruction | |
3199 | ||
3200 | @item R | |
3201 | Floating-point constant whose integral representation can | |
3202 | be moved into an integer register using a single mov | |
3203 | instruction | |
03dda8e3 RK |
3204 | |
3205 | @item S | |
62190128 DM |
3206 | Floating-point constant whose integral representation can |
3207 | be moved into an integer register using a high/lo_sum | |
3208 | instruction sequence | |
03dda8e3 RK |
3209 | |
3210 | @item T | |
3211 | Memory address aligned to an 8-byte boundary | |
3212 | ||
3213 | @item U | |
3214 | Even register | |
6ca30df6 | 3215 | |
7a31a340 | 3216 | @item W |
c75d6010 JM |
3217 | Memory address for @samp{e} constraint registers |
3218 | ||
3219 | @item Y | |
3220 | Vector zero | |
7a31a340 | 3221 | |
6ca30df6 MH |
3222 | @end table |
3223 | ||
85d9c13c TS |
3224 | @item SPU---@file{config/spu/spu.h} |
3225 | @table @code | |
3226 | @item a | |
ff2ce160 | 3227 | An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value. |
85d9c13c TS |
3228 | |
3229 | @item c | |
ff2ce160 | 3230 | An immediate for and/xor/or instructions. const_int is treated as a 64 bit value. |
85d9c13c TS |
3231 | |
3232 | @item d | |
ff2ce160 | 3233 | An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value. |
85d9c13c TS |
3234 | |
3235 | @item f | |
ff2ce160 | 3236 | An immediate which can be loaded with @code{fsmbi}. |
85d9c13c TS |
3237 | |
3238 | @item A | |
ff2ce160 | 3239 | An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value. |
85d9c13c TS |
3240 | |
3241 | @item B | |
ff2ce160 | 3242 | An immediate for most arithmetic instructions. const_int is treated as a 32 bit value. |
85d9c13c TS |
3243 | |
3244 | @item C | |
ff2ce160 | 3245 | An immediate for and/xor/or instructions. const_int is treated as a 32 bit value. |
85d9c13c TS |
3246 | |
3247 | @item D | |
ff2ce160 | 3248 | An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value. |
85d9c13c TS |
3249 | |
3250 | @item I | |
ff2ce160 | 3251 | A constant in the range [@minus{}64, 63] for shift/rotate instructions. |
85d9c13c TS |
3252 | |
3253 | @item J | |
ff2ce160 | 3254 | An unsigned 7-bit constant for conversion/nop/channel instructions. |
85d9c13c TS |
3255 | |
3256 | @item K | |
ff2ce160 | 3257 | A signed 10-bit constant for most arithmetic instructions. |
85d9c13c TS |
3258 | |
3259 | @item M | |
ff2ce160 | 3260 | A signed 16 bit immediate for @code{stop}. |
85d9c13c TS |
3261 | |
3262 | @item N | |
ff2ce160 | 3263 | An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}. |
85d9c13c TS |
3264 | |
3265 | @item O | |
ff2ce160 | 3266 | An unsigned 7-bit constant whose 3 least significant bits are 0. |
85d9c13c TS |
3267 | |
3268 | @item P | |
ff2ce160 | 3269 | An unsigned 3-bit constant for 16-byte rotates and shifts |
85d9c13c TS |
3270 | |
3271 | @item R | |
ff2ce160 | 3272 | Call operand, reg, for indirect calls |
85d9c13c TS |
3273 | |
3274 | @item S | |
ff2ce160 | 3275 | Call operand, symbol, for relative calls. |
85d9c13c TS |
3276 | |
3277 | @item T | |
ff2ce160 | 3278 | Call operand, const_int, for absolute calls. |
85d9c13c TS |
3279 | |
3280 | @item U | |
ff2ce160 | 3281 | An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit. |
85d9c13c TS |
3282 | |
3283 | @item W | |
ff2ce160 | 3284 | An immediate for shift and rotate instructions. const_int is treated as a 32 bit value. |
85d9c13c TS |
3285 | |
3286 | @item Y | |
ff2ce160 | 3287 | An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit. |
85d9c13c TS |
3288 | |
3289 | @item Z | |
ff2ce160 | 3290 | An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit. |
85d9c13c TS |
3291 | |
3292 | @end table | |
3293 | ||
74fe790b | 3294 | @item S/390 and zSeries---@file{config/s390/s390.h} |
91abf72d HP |
3295 | @table @code |
3296 | @item a | |
3297 | Address register (general purpose register except r0) | |
3298 | ||
9dc62c00 AK |
3299 | @item c |
3300 | Condition code register | |
3301 | ||
91abf72d HP |
3302 | @item d |
3303 | Data register (arbitrary general purpose register) | |
3304 | ||
3305 | @item f | |
3306 | Floating-point register | |
3307 | ||
3308 | @item I | |
3309 | Unsigned 8-bit constant (0--255) | |
3310 | ||
3311 | @item J | |
3312 | Unsigned 12-bit constant (0--4095) | |
3313 | ||
3314 | @item K | |
3315 | Signed 16-bit constant (@minus{}32768--32767) | |
3316 | ||
3317 | @item L | |
f19a9af7 AK |
3318 | Value appropriate as displacement. |
3319 | @table @code | |
6ccde948 RW |
3320 | @item (0..4095) |
3321 | for short displacement | |
8ad1dde7 | 3322 | @item (@minus{}524288..524287) |
6ccde948 | 3323 | for long displacement |
f19a9af7 AK |
3324 | @end table |
3325 | ||
3326 | @item M | |
3327 | Constant integer with a value of 0x7fffffff. | |
3328 | ||
3329 | @item N | |
3330 | Multiple letter constraint followed by 4 parameter letters. | |
3331 | @table @code | |
6ccde948 RW |
3332 | @item 0..9: |
3333 | number of the part counting from most to least significant | |
3334 | @item H,Q: | |
3335 | mode of the part | |
3336 | @item D,S,H: | |
3337 | mode of the containing operand | |
3338 | @item 0,F: | |
3339 | value of the other parts (F---all bits set) | |
f19a9af7 AK |
3340 | @end table |
3341 | The constraint matches if the specified part of a constant | |
dc9a511d | 3342 | has a value different from its other parts. |
91abf72d HP |
3343 | |
3344 | @item Q | |
f19a9af7 AK |
3345 | Memory reference without index register and with short displacement. |
3346 | ||
3347 | @item R | |
3348 | Memory reference with index register and short displacement. | |
91abf72d HP |
3349 | |
3350 | @item S | |
f19a9af7 AK |
3351 | Memory reference without index register but with long displacement. |
3352 | ||
3353 | @item T | |
3354 | Memory reference with index register and long displacement. | |
3355 | ||
3356 | @item U | |
3357 | Pointer with short displacement. | |
3358 | ||
3359 | @item W | |
3360 | Pointer with long displacement. | |
3361 | ||
3362 | @item Y | |
3363 | Shift count operand. | |
91abf72d HP |
3364 | |
3365 | @end table | |
3366 | ||
93ef7c1f CL |
3367 | @item Score family---@file{config/score/score.h} |
3368 | @table @code | |
3369 | @item d | |
3370 | Registers from r0 to r32. | |
3371 | ||
3372 | @item e | |
3373 | Registers from r0 to r16. | |
3374 | ||
3375 | @item t | |
3376 | r8---r11 or r22---r27 registers. | |
3377 | ||
3378 | @item h | |
3379 | hi register. | |
3380 | ||
3381 | @item l | |
3382 | lo register. | |
3383 | ||
3384 | @item x | |
3385 | hi + lo register. | |
3386 | ||
3387 | @item q | |
3388 | cnt register. | |
3389 | ||
3390 | @item y | |
3391 | lcb register. | |
3392 | ||
3393 | @item z | |
3394 | scb register. | |
3395 | ||
3396 | @item a | |
3397 | cnt + lcb + scb register. | |
3398 | ||
3399 | @item c | |
3400 | cr0---cr15 register. | |
3401 | ||
3402 | @item b | |
3403 | cp1 registers. | |
3404 | ||
3405 | @item f | |
3406 | cp2 registers. | |
3407 | ||
3408 | @item i | |
3409 | cp3 registers. | |
3410 | ||
3411 | @item j | |
3412 | cp1 + cp2 + cp3 registers. | |
3413 | ||
3414 | @item I | |
c6681463 | 3415 | High 16-bit constant (32-bit constant with 16 LSBs zero). |
93ef7c1f CL |
3416 | |
3417 | @item J | |
3418 | Unsigned 5 bit integer (in the range 0 to 31). | |
3419 | ||
3420 | @item K | |
3421 | Unsigned 16 bit integer (in the range 0 to 65535). | |
3422 | ||
3423 | @item L | |
3424 | Signed 16 bit integer (in the range @minus{}32768 to 32767). | |
3425 | ||
3426 | @item M | |
3427 | Unsigned 14 bit integer (in the range 0 to 16383). | |
3428 | ||
3429 | @item N | |
3430 | Signed 14 bit integer (in the range @minus{}8192 to 8191). | |
3431 | ||
93ef7c1f CL |
3432 | @item Z |
3433 | Any SYMBOL_REF. | |
3434 | @end table | |
3435 | ||
74fe790b | 3436 | @item Xstormy16---@file{config/stormy16/stormy16.h} |
9f339dde GK |
3437 | @table @code |
3438 | @item a | |
3439 | Register r0. | |
3440 | ||
3441 | @item b | |
3442 | Register r1. | |
3443 | ||
3444 | @item c | |
3445 | Register r2. | |
3446 | ||
3447 | @item d | |
3448 | Register r8. | |
3449 | ||
3450 | @item e | |
3451 | Registers r0 through r7. | |
3452 | ||
3453 | @item t | |
3454 | Registers r0 and r1. | |
3455 | ||
3456 | @item y | |
3457 | The carry register. | |
3458 | ||
3459 | @item z | |
3460 | Registers r8 and r9. | |
3461 | ||
3462 | @item I | |
3463 | A constant between 0 and 3 inclusive. | |
3464 | ||
3465 | @item J | |
3466 | A constant that has exactly one bit set. | |
3467 | ||
3468 | @item K | |
3469 | A constant that has exactly one bit clear. | |
3470 | ||
3471 | @item L | |
3472 | A constant between 0 and 255 inclusive. | |
3473 | ||
3474 | @item M | |
69a0611f | 3475 | A constant between @minus{}255 and 0 inclusive. |
9f339dde GK |
3476 | |
3477 | @item N | |
69a0611f | 3478 | A constant between @minus{}3 and 0 inclusive. |
9f339dde GK |
3479 | |
3480 | @item O | |
3481 | A constant between 1 and 4 inclusive. | |
3482 | ||
3483 | @item P | |
69a0611f | 3484 | A constant between @minus{}4 and @minus{}1 inclusive. |
9f339dde GK |
3485 | |
3486 | @item Q | |
3487 | A memory reference that is a stack push. | |
3488 | ||
3489 | @item R | |
3490 | A memory reference that is a stack pop. | |
3491 | ||
3492 | @item S | |
63519d23 | 3493 | A memory reference that refers to a constant address of known value. |
9f339dde GK |
3494 | |
3495 | @item T | |
3496 | The register indicated by Rx (not implemented yet). | |
3497 | ||
3498 | @item U | |
3499 | A constant that is not between 2 and 15 inclusive. | |
3500 | ||
e2ce66a9 DD |
3501 | @item Z |
3502 | The constant 0. | |
3503 | ||
9f339dde GK |
3504 | @end table |
3505 | ||
bcead286 BS |
3506 | @item TI C6X family---@file{config/c6x/constraints.md} |
3507 | @table @code | |
3508 | @item a | |
3509 | Register file A (A0--A31). | |
3510 | ||
3511 | @item b | |
3512 | Register file B (B0--B31). | |
3513 | ||
3514 | @item A | |
3515 | Predicate registers in register file A (A0--A2 on C64X and | |
3516 | higher, A1 and A2 otherwise). | |
3517 | ||
3518 | @item B | |
3519 | Predicate registers in register file B (B0--B2). | |
3520 | ||
3521 | @item C | |
3522 | A call-used register in register file B (B0--B9, B16--B31). | |
3523 | ||
3524 | @item Da | |
3525 | Register file A, excluding predicate registers (A3--A31, | |
3526 | plus A0 if not C64X or higher). | |
3527 | ||
3528 | @item Db | |
3529 | Register file B, excluding predicate registers (B3--B31). | |
3530 | ||
3531 | @item Iu4 | |
3532 | Integer constant in the range 0 @dots{} 15. | |
3533 | ||
3534 | @item Iu5 | |
3535 | Integer constant in the range 0 @dots{} 31. | |
3536 | ||
3537 | @item In5 | |
3538 | Integer constant in the range @minus{}31 @dots{} 0. | |
3539 | ||
3540 | @item Is5 | |
3541 | Integer constant in the range @minus{}16 @dots{} 15. | |
3542 | ||
3543 | @item I5x | |
3544 | Integer constant that can be the operand of an ADDA or a SUBA insn. | |
3545 | ||
3546 | @item IuB | |
3547 | Integer constant in the range 0 @dots{} 65535. | |
3548 | ||
3549 | @item IsB | |
3550 | Integer constant in the range @minus{}32768 @dots{} 32767. | |
3551 | ||
3552 | @item IsC | |
3553 | Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}. | |
3554 | ||
3555 | @item Jc | |
3556 | Integer constant that is a valid mask for the clr instruction. | |
3557 | ||
3558 | @item Js | |
3559 | Integer constant that is a valid mask for the set instruction. | |
3560 | ||
3561 | @item Q | |
3562 | Memory location with A base register. | |
3563 | ||
3564 | @item R | |
3565 | Memory location with B base register. | |
3566 | ||
3567 | @ifset INTERNALS | |
3568 | @item S0 | |
3569 | On C64x+ targets, a GP-relative small data reference. | |
3570 | ||
3571 | @item S1 | |
3572 | Any kind of @code{SYMBOL_REF}, for use in a call address. | |
3573 | ||
3574 | @item Si | |
3575 | Any kind of immediate operand, unless it matches the S0 constraint. | |
3576 | ||
3577 | @item T | |
3578 | Memory location with B base register, but not using a long offset. | |
3579 | ||
3580 | @item W | |
3581 | A memory operand with an address that can't be used in an unaligned access. | |
3582 | ||
3583 | @end ifset | |
3584 | @item Z | |
3585 | Register B14 (aka DP). | |
3586 | ||
3587 | @end table | |
3588 | ||
dd552284 WL |
3589 | @item TILE-Gx---@file{config/tilegx/constraints.md} |
3590 | @table @code | |
3591 | @item R00 | |
3592 | @itemx R01 | |
3593 | @itemx R02 | |
3594 | @itemx R03 | |
3595 | @itemx R04 | |
3596 | @itemx R05 | |
3597 | @itemx R06 | |
3598 | @itemx R07 | |
3599 | @itemx R08 | |
3600 | @itemx R09 | |
655c5444 | 3601 | @itemx R10 |
dd552284 WL |
3602 | Each of these represents a register constraint for an individual |
3603 | register, from r0 to r10. | |
3604 | ||
3605 | @item I | |
3606 | Signed 8-bit integer constant. | |
3607 | ||
3608 | @item J | |
3609 | Signed 16-bit integer constant. | |
3610 | ||
3611 | @item K | |
3612 | Unsigned 16-bit integer constant. | |
3613 | ||
3614 | @item L | |
3615 | Integer constant that fits in one signed byte when incremented by one | |
3616 | (@minus{}129 @dots{} 126). | |
3617 | ||
3618 | @item m | |
3619 | Memory operand. If used together with @samp{<} or @samp{>}, the | |
3620 | operand can have postincrement which requires printing with @samp{%In} | |
3621 | and @samp{%in} on TILE-Gx. For example: | |
3622 | ||
3623 | @smallexample | |
3624 | asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val)); | |
3625 | @end smallexample | |
3626 | ||
3627 | @item M | |
3628 | A bit mask suitable for the BFINS instruction. | |
3629 | ||
3630 | @item N | |
3631 | Integer constant that is a byte tiled out eight times. | |
3632 | ||
3633 | @item O | |
3634 | The integer zero constant. | |
3635 | ||
3636 | @item P | |
3637 | Integer constant that is a sign-extended byte tiled out as four shorts. | |
3638 | ||
3639 | @item Q | |
3640 | Integer constant that fits in one signed byte when incremented | |
3641 | (@minus{}129 @dots{} 126), but excluding -1. | |
3642 | ||
3643 | @item S | |
3644 | Integer constant that has all 1 bits consecutive and starting at bit 0. | |
3645 | ||
3646 | @item T | |
3647 | A 16-bit fragment of a got, tls, or pc-relative reference. | |
3648 | ||
3649 | @item U | |
3650 | Memory operand except postincrement. This is roughly the same as | |
3651 | @samp{m} when not used together with @samp{<} or @samp{>}. | |
3652 | ||
3653 | @item W | |
3654 | An 8-element vector constant with identical elements. | |
3655 | ||
3656 | @item Y | |
3657 | A 4-element vector constant with identical elements. | |
3658 | ||
3659 | @item Z0 | |
3660 | The integer constant 0xffffffff. | |
3661 | ||
3662 | @item Z1 | |
3663 | The integer constant 0xffffffff00000000. | |
3664 | ||
3665 | @end table | |
3666 | ||
3667 | @item TILEPro---@file{config/tilepro/constraints.md} | |
3668 | @table @code | |
3669 | @item R00 | |
3670 | @itemx R01 | |
3671 | @itemx R02 | |
3672 | @itemx R03 | |
3673 | @itemx R04 | |
3674 | @itemx R05 | |
3675 | @itemx R06 | |
3676 | @itemx R07 | |
3677 | @itemx R08 | |
3678 | @itemx R09 | |
655c5444 | 3679 | @itemx R10 |
dd552284 WL |
3680 | Each of these represents a register constraint for an individual |
3681 | register, from r0 to r10. | |
3682 | ||
3683 | @item I | |
3684 | Signed 8-bit integer constant. | |
3685 | ||
3686 | @item J | |
3687 | Signed 16-bit integer constant. | |
3688 | ||
3689 | @item K | |
3690 | Nonzero integer constant with low 16 bits zero. | |
3691 | ||
3692 | @item L | |
3693 | Integer constant that fits in one signed byte when incremented by one | |
3694 | (@minus{}129 @dots{} 126). | |
3695 | ||
3696 | @item m | |
3697 | Memory operand. If used together with @samp{<} or @samp{>}, the | |
3698 | operand can have postincrement which requires printing with @samp{%In} | |
3699 | and @samp{%in} on TILEPro. For example: | |
3700 | ||
3701 | @smallexample | |
3702 | asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val)); | |
3703 | @end smallexample | |
3704 | ||
3705 | @item M | |
3706 | A bit mask suitable for the MM instruction. | |
3707 | ||
3708 | @item N | |
3709 | Integer constant that is a byte tiled out four times. | |
3710 | ||
3711 | @item O | |
3712 | The integer zero constant. | |
3713 | ||
3714 | @item P | |
3715 | Integer constant that is a sign-extended byte tiled out as two shorts. | |
3716 | ||
3717 | @item Q | |
3718 | Integer constant that fits in one signed byte when incremented | |
3719 | (@minus{}129 @dots{} 126), but excluding -1. | |
3720 | ||
3721 | @item T | |
3722 | A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative | |
3723 | reference. | |
3724 | ||
3725 | @item U | |
3726 | Memory operand except postincrement. This is roughly the same as | |
3727 | @samp{m} when not used together with @samp{<} or @samp{>}. | |
3728 | ||
3729 | @item W | |
3730 | A 4-element vector constant with identical elements. | |
3731 | ||
3732 | @item Y | |
3733 | A 2-element vector constant with identical elements. | |
3734 | ||
3735 | @end table | |
3736 | ||
887af464 | 3737 | @item Xtensa---@file{config/xtensa/constraints.md} |
03984308 BW |
3738 | @table @code |
3739 | @item a | |
3740 | General-purpose 32-bit register | |
3741 | ||
3742 | @item b | |
3743 | One-bit boolean register | |
3744 | ||
3745 | @item A | |
3746 | MAC16 40-bit accumulator register | |
3747 | ||
3748 | @item I | |
3749 | Signed 12-bit integer constant, for use in MOVI instructions | |
3750 | ||
3751 | @item J | |
3752 | Signed 8-bit integer constant, for use in ADDI instructions | |
3753 | ||
3754 | @item K | |
3755 | Integer constant valid for BccI instructions | |
3756 | ||
3757 | @item L | |
3758 | Unsigned constant valid for BccUI instructions | |
3759 | ||
3760 | @end table | |
3761 | ||
03dda8e3 RK |
3762 | @end table |
3763 | ||
7ac28727 AK |
3764 | @ifset INTERNALS |
3765 | @node Disable Insn Alternatives | |
3766 | @subsection Disable insn alternatives using the @code{enabled} attribute | |
3767 | @cindex enabled | |
3768 | ||
3769 | The @code{enabled} insn attribute may be used to disable certain insn | |
3770 | alternatives for machine-specific reasons. This is useful when adding | |
3771 | new instructions to an existing pattern which are only available for | |
3772 | certain cpu architecture levels as specified with the @code{-march=} | |
3773 | option. | |
3774 | ||
3775 | If an insn alternative is disabled, then it will never be used. The | |
3776 | compiler treats the constraints for the disabled alternative as | |
3777 | unsatisfiable. | |
3778 | ||
3779 | In order to make use of the @code{enabled} attribute a back end has to add | |
3780 | in the machine description files: | |
3781 | ||
3782 | @enumerate | |
3783 | @item | |
3784 | A definition of the @code{enabled} insn attribute. The attribute is | |
3785 | defined as usual using the @code{define_attr} command. This | |
3786 | definition should be based on other insn attributes and/or target flags. | |
3787 | The @code{enabled} attribute is a numeric attribute and should evaluate to | |
3788 | @code{(const_int 1)} for an enabled alternative and to | |
3789 | @code{(const_int 0)} otherwise. | |
3790 | @item | |
3791 | A definition of another insn attribute used to describe for what | |
3792 | reason an insn alternative might be available or | |
3793 | not. E.g. @code{cpu_facility} as in the example below. | |
3794 | @item | |
a640c13b | 3795 | An assignment for the second attribute to each insn definition |
7ac28727 AK |
3796 | combining instructions which are not all available under the same |
3797 | circumstances. (Note: It obviously only makes sense for definitions | |
3798 | with more than one alternative. Otherwise the insn pattern should be | |
3799 | disabled or enabled using the insn condition.) | |
3800 | @end enumerate | |
3801 | ||
3802 | E.g. the following two patterns could easily be merged using the @code{enabled} | |
3803 | attribute: | |
3804 | ||
3805 | @smallexample | |
3806 | ||
3807 | (define_insn "*movdi_old" | |
3808 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3809 | (match_operand:DI 1 "register_operand" " d"))] | |
3810 | "!TARGET_NEW" | |
3811 | "lgr %0,%1") | |
3812 | ||
3813 | (define_insn "*movdi_new" | |
3814 | [(set (match_operand:DI 0 "register_operand" "=d,f,d") | |
3815 | (match_operand:DI 1 "register_operand" " d,d,f"))] | |
3816 | "TARGET_NEW" | |
3817 | "@@ | |
3818 | lgr %0,%1 | |
3819 | ldgr %0,%1 | |
3820 | lgdr %0,%1") | |
3821 | ||
3822 | @end smallexample | |
3823 | ||
3824 | to: | |
3825 | ||
3826 | @smallexample | |
3827 | ||
3828 | (define_insn "*movdi_combined" | |
3829 | [(set (match_operand:DI 0 "register_operand" "=d,f,d") | |
3830 | (match_operand:DI 1 "register_operand" " d,d,f"))] | |
3831 | "" | |
3832 | "@@ | |
3833 | lgr %0,%1 | |
3834 | ldgr %0,%1 | |
3835 | lgdr %0,%1" | |
3836 | [(set_attr "cpu_facility" "*,new,new")]) | |
3837 | ||
3838 | @end smallexample | |
3839 | ||
3840 | with the @code{enabled} attribute defined like this: | |
3841 | ||
3842 | @smallexample | |
3843 | ||
3844 | (define_attr "cpu_facility" "standard,new" (const_string "standard")) | |
3845 | ||
3846 | (define_attr "enabled" "" | |
3847 | (cond [(eq_attr "cpu_facility" "standard") (const_int 1) | |
3848 | (and (eq_attr "cpu_facility" "new") | |
3849 | (ne (symbol_ref "TARGET_NEW") (const_int 0))) | |
3850 | (const_int 1)] | |
3851 | (const_int 0))) | |
3852 | ||
3853 | @end smallexample | |
3854 | ||
3855 | @end ifset | |
3856 | ||
03dda8e3 | 3857 | @ifset INTERNALS |
f38840db ZW |
3858 | @node Define Constraints |
3859 | @subsection Defining Machine-Specific Constraints | |
3860 | @cindex defining constraints | |
3861 | @cindex constraints, defining | |
3862 | ||
3863 | Machine-specific constraints fall into two categories: register and | |
3864 | non-register constraints. Within the latter category, constraints | |
3865 | which allow subsets of all possible memory or address operands should | |
3866 | be specially marked, to give @code{reload} more information. | |
3867 | ||
3868 | Machine-specific constraints can be given names of arbitrary length, | |
3869 | but they must be entirely composed of letters, digits, underscores | |
3870 | (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they | |
ff2ce160 | 3871 | must begin with a letter or underscore. |
f38840db ZW |
3872 | |
3873 | In order to avoid ambiguity in operand constraint strings, no | |
3874 | constraint can have a name that begins with any other constraint's | |
3875 | name. For example, if @code{x} is defined as a constraint name, | |
3876 | @code{xy} may not be, and vice versa. As a consequence of this rule, | |
3877 | no constraint may begin with one of the generic constraint letters: | |
3878 | @samp{E F V X g i m n o p r s}. | |
3879 | ||
3880 | Register constraints correspond directly to register classes. | |
3881 | @xref{Register Classes}. There is thus not much flexibility in their | |
3882 | definitions. | |
3883 | ||
3884 | @deffn {MD Expression} define_register_constraint name regclass docstring | |
3885 | All three arguments are string constants. | |
3886 | @var{name} is the name of the constraint, as it will appear in | |
5be527d0 RG |
3887 | @code{match_operand} expressions. If @var{name} is a multi-letter |
3888 | constraint its length shall be the same for all constraints starting | |
3889 | with the same letter. @var{regclass} can be either the | |
f38840db ZW |
3890 | name of the corresponding register class (@pxref{Register Classes}), |
3891 | or a C expression which evaluates to the appropriate register class. | |
3892 | If it is an expression, it must have no side effects, and it cannot | |
3893 | look at the operand. The usual use of expressions is to map some | |
3894 | register constraints to @code{NO_REGS} when the register class | |
3895 | is not available on a given subarchitecture. | |
3896 | ||
3897 | @var{docstring} is a sentence documenting the meaning of the | |
3898 | constraint. Docstrings are explained further below. | |
3899 | @end deffn | |
3900 | ||
3901 | Non-register constraints are more like predicates: the constraint | |
3902 | definition gives a Boolean expression which indicates whether the | |
3903 | constraint matches. | |
3904 | ||
3905 | @deffn {MD Expression} define_constraint name docstring exp | |
3906 | The @var{name} and @var{docstring} arguments are the same as for | |
3907 | @code{define_register_constraint}, but note that the docstring comes | |
3908 | immediately after the name for these expressions. @var{exp} is an RTL | |
3909 | expression, obeying the same rules as the RTL expressions in predicate | |
3910 | definitions. @xref{Defining Predicates}, for details. If it | |
3911 | evaluates true, the constraint matches; if it evaluates false, it | |
3912 | doesn't. Constraint expressions should indicate which RTL codes they | |
3913 | might match, just like predicate expressions. | |
3914 | ||
3915 | @code{match_test} C expressions have access to the | |
3916 | following variables: | |
3917 | ||
3918 | @table @var | |
3919 | @item op | |
3920 | The RTL object defining the operand. | |
3921 | @item mode | |
3922 | The machine mode of @var{op}. | |
3923 | @item ival | |
3924 | @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}. | |
3925 | @item hval | |
3926 | @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer | |
3927 | @code{const_double}. | |
3928 | @item lval | |
3929 | @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer | |
3930 | @code{const_double}. | |
3931 | @item rval | |
3932 | @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point | |
3fa1b0e5 | 3933 | @code{const_double}. |
f38840db ZW |
3934 | @end table |
3935 | ||
3936 | The @var{*val} variables should only be used once another piece of the | |
3937 | expression has verified that @var{op} is the appropriate kind of RTL | |
3938 | object. | |
3939 | @end deffn | |
3940 | ||
3941 | Most non-register constraints should be defined with | |
3942 | @code{define_constraint}. The remaining two definition expressions | |
3943 | are only appropriate for constraints that should be handled specially | |
3944 | by @code{reload} if they fail to match. | |
3945 | ||
3946 | @deffn {MD Expression} define_memory_constraint name docstring exp | |
3947 | Use this expression for constraints that match a subset of all memory | |
3948 | operands: that is, @code{reload} can make them match by converting the | |
3949 | operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a | |
3950 | base register (from the register class specified by | |
3951 | @code{BASE_REG_CLASS}, @pxref{Register Classes}). | |
3952 | ||
3953 | For example, on the S/390, some instructions do not accept arbitrary | |
3954 | memory references, but only those that do not make use of an index | |
3955 | register. The constraint letter @samp{Q} is defined to represent a | |
3956 | memory address of this type. If @samp{Q} is defined with | |
3957 | @code{define_memory_constraint}, a @samp{Q} constraint can handle any | |
3958 | memory operand, because @code{reload} knows it can simply copy the | |
3959 | memory address into a base register if required. This is analogous to | |
e4ae5e77 | 3960 | the way an @samp{o} constraint can handle any memory operand. |
f38840db ZW |
3961 | |
3962 | The syntax and semantics are otherwise identical to | |
3963 | @code{define_constraint}. | |
3964 | @end deffn | |
3965 | ||
3966 | @deffn {MD Expression} define_address_constraint name docstring exp | |
3967 | Use this expression for constraints that match a subset of all address | |
3968 | operands: that is, @code{reload} can make the constraint match by | |
3969 | converting the operand to the form @samp{@w{(reg @var{X})}}, again | |
3970 | with @var{X} a base register. | |
3971 | ||
3972 | Constraints defined with @code{define_address_constraint} can only be | |
3973 | used with the @code{address_operand} predicate, or machine-specific | |
3974 | predicates that work the same way. They are treated analogously to | |
3975 | the generic @samp{p} constraint. | |
3976 | ||
3977 | The syntax and semantics are otherwise identical to | |
3978 | @code{define_constraint}. | |
3979 | @end deffn | |
3980 | ||
3981 | For historical reasons, names beginning with the letters @samp{G H} | |
3982 | are reserved for constraints that match only @code{const_double}s, and | |
3983 | names beginning with the letters @samp{I J K L M N O P} are reserved | |
3984 | for constraints that match only @code{const_int}s. This may change in | |
3985 | the future. For the time being, constraints with these names must be | |
3986 | written in a stylized form, so that @code{genpreds} can tell you did | |
3987 | it correctly: | |
3988 | ||
3989 | @smallexample | |
3990 | @group | |
3991 | (define_constraint "[@var{GHIJKLMNOP}]@dots{}" | |
3992 | "@var{doc}@dots{}" | |
3993 | (and (match_code "const_int") ; @r{@code{const_double} for G/H} | |
3994 | @var{condition}@dots{})) ; @r{usually a @code{match_test}} | |
3995 | @end group | |
3996 | @end smallexample | |
3997 | @c the semicolons line up in the formatted manual | |
3998 | ||
3999 | It is fine to use names beginning with other letters for constraints | |
4000 | that match @code{const_double}s or @code{const_int}s. | |
4001 | ||
4002 | Each docstring in a constraint definition should be one or more complete | |
4003 | sentences, marked up in Texinfo format. @emph{They are currently unused.} | |
4004 | In the future they will be copied into the GCC manual, in @ref{Machine | |
4005 | Constraints}, replacing the hand-maintained tables currently found in | |
4006 | that section. Also, in the future the compiler may use this to give | |
4007 | more helpful diagnostics when poor choice of @code{asm} constraints | |
4008 | causes a reload failure. | |
4009 | ||
4010 | If you put the pseudo-Texinfo directive @samp{@@internal} at the | |
4011 | beginning of a docstring, then (in the future) it will appear only in | |
4012 | the internals manual's version of the machine-specific constraint tables. | |
4013 | Use this for constraints that should not appear in @code{asm} statements. | |
4014 | ||
4015 | @node C Constraint Interface | |
4016 | @subsection Testing constraints from C | |
4017 | @cindex testing constraints | |
4018 | @cindex constraints, testing | |
4019 | ||
4020 | It is occasionally useful to test a constraint from C code rather than | |
4021 | implicitly via the constraint string in a @code{match_operand}. The | |
4022 | generated file @file{tm_p.h} declares a few interfaces for working | |
4023 | with machine-specific constraints. None of these interfaces work with | |
4024 | the generic constraints described in @ref{Simple Constraints}. This | |
4025 | may change in the future. | |
4026 | ||
4027 | @strong{Warning:} @file{tm_p.h} may declare other functions that | |
4028 | operate on constraints, besides the ones documented here. Do not use | |
4029 | those functions from machine-dependent code. They exist to implement | |
4030 | the old constraint interface that machine-independent components of | |
4031 | the compiler still expect. They will change or disappear in the | |
4032 | future. | |
4033 | ||
4034 | Some valid constraint names are not valid C identifiers, so there is a | |
4035 | mangling scheme for referring to them from C@. Constraint names that | |
4036 | do not contain angle brackets or underscores are left unchanged. | |
4037 | Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and | |
4038 | each @samp{>} with @samp{_g}. Here are some examples: | |
4039 | ||
4040 | @c the @c's prevent double blank lines in the printed manual. | |
4041 | @example | |
4042 | @multitable {Original} {Mangled} | |
cccb0908 | 4043 | @item @strong{Original} @tab @strong{Mangled} @c |
f38840db ZW |
4044 | @item @code{x} @tab @code{x} @c |
4045 | @item @code{P42x} @tab @code{P42x} @c | |
4046 | @item @code{P4_x} @tab @code{P4__x} @c | |
4047 | @item @code{P4>x} @tab @code{P4_gx} @c | |
4048 | @item @code{P4>>} @tab @code{P4_g_g} @c | |
4049 | @item @code{P4_g>} @tab @code{P4__g_g} @c | |
4050 | @end multitable | |
4051 | @end example | |
4052 | ||
4053 | Throughout this section, the variable @var{c} is either a constraint | |
4054 | in the abstract sense, or a constant from @code{enum constraint_num}; | |
4055 | the variable @var{m} is a mangled constraint name (usually as part of | |
4056 | a larger identifier). | |
4057 | ||
4058 | @deftp Enum constraint_num | |
4059 | For each machine-specific constraint, there is a corresponding | |
4060 | enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the | |
4061 | constraint. Functions that take an @code{enum constraint_num} as an | |
4062 | argument expect one of these constants. | |
4063 | ||
4064 | Machine-independent constraints do not have associated constants. | |
4065 | This may change in the future. | |
4066 | @end deftp | |
4067 | ||
4068 | @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp}) | |
4069 | For each machine-specific, non-register constraint @var{m}, there is | |
4070 | one of these functions; it returns @code{true} if @var{exp} satisfies the | |
4071 | constraint. These functions are only visible if @file{rtl.h} was included | |
4072 | before @file{tm_p.h}. | |
4073 | @end deftypefun | |
4074 | ||
4075 | @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c}) | |
4076 | Like the @code{satisfies_constraint_@var{m}} functions, but the | |
4077 | constraint to test is given as an argument, @var{c}. If @var{c} | |
4078 | specifies a register constraint, this function will always return | |
4079 | @code{false}. | |
4080 | @end deftypefun | |
4081 | ||
4082 | @deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c}) | |
4083 | Returns the register class associated with @var{c}. If @var{c} is not | |
4084 | a register constraint, or those registers are not available for the | |
4085 | currently selected subtarget, returns @code{NO_REGS}. | |
4086 | @end deftypefun | |
4087 | ||
4088 | Here is an example use of @code{satisfies_constraint_@var{m}}. In | |
4089 | peephole optimizations (@pxref{Peephole Definitions}), operand | |
4090 | constraint strings are ignored, so if there are relevant constraints, | |
4091 | they must be tested in the C condition. In the example, the | |
4092 | optimization is applied if operand 2 does @emph{not} satisfy the | |
4093 | @samp{K} constraint. (This is a simplified version of a peephole | |
4094 | definition from the i386 machine description.) | |
4095 | ||
4096 | @smallexample | |
4097 | (define_peephole2 | |
4098 | [(match_scratch:SI 3 "r") | |
4099 | (set (match_operand:SI 0 "register_operand" "") | |
6ccde948 RW |
4100 | (mult:SI (match_operand:SI 1 "memory_operand" "") |
4101 | (match_operand:SI 2 "immediate_operand" "")))] | |
f38840db ZW |
4102 | |
4103 | "!satisfies_constraint_K (operands[2])" | |
4104 | ||
4105 | [(set (match_dup 3) (match_dup 1)) | |
4106 | (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))] | |
4107 | ||
4108 | "") | |
4109 | @end smallexample | |
4110 | ||
03dda8e3 RK |
4111 | @node Standard Names |
4112 | @section Standard Pattern Names For Generation | |
4113 | @cindex standard pattern names | |
4114 | @cindex pattern names | |
4115 | @cindex names, pattern | |
4116 | ||
4117 | Here is a table of the instruction names that are meaningful in the RTL | |
4118 | generation pass of the compiler. Giving one of these names to an | |
4119 | instruction pattern tells the RTL generation pass that it can use the | |
556e0f21 | 4120 | pattern to accomplish a certain task. |
03dda8e3 RK |
4121 | |
4122 | @table @asis | |
4123 | @cindex @code{mov@var{m}} instruction pattern | |
4124 | @item @samp{mov@var{m}} | |
4bd0bee9 | 4125 | Here @var{m} stands for a two-letter machine mode name, in lowercase. |
03dda8e3 RK |
4126 | This instruction pattern moves data with that machine mode from operand |
4127 | 1 to operand 0. For example, @samp{movsi} moves full-word data. | |
4128 | ||
4129 | If operand 0 is a @code{subreg} with mode @var{m} of a register whose | |
4130 | own mode is wider than @var{m}, the effect of this instruction is | |
4131 | to store the specified value in the part of the register that corresponds | |
8feb4e28 JL |
4132 | to mode @var{m}. Bits outside of @var{m}, but which are within the |
4133 | same target word as the @code{subreg} are undefined. Bits which are | |
4134 | outside the target word are left unchanged. | |
03dda8e3 RK |
4135 | |
4136 | This class of patterns is special in several ways. First of all, each | |
65945ec1 HPN |
4137 | of these names up to and including full word size @emph{must} be defined, |
4138 | because there is no other way to copy a datum from one place to another. | |
4139 | If there are patterns accepting operands in larger modes, | |
4140 | @samp{mov@var{m}} must be defined for integer modes of those sizes. | |
03dda8e3 RK |
4141 | |
4142 | Second, these patterns are not used solely in the RTL generation pass. | |
4143 | Even the reload pass can generate move insns to copy values from stack | |
4144 | slots into temporary registers. When it does so, one of the operands is | |
4145 | a hard register and the other is an operand that can need to be reloaded | |
4146 | into a register. | |
4147 | ||
4148 | @findex force_reg | |
4149 | Therefore, when given such a pair of operands, the pattern must generate | |
4150 | RTL which needs no reloading and needs no temporary registers---no | |
4151 | registers other than the operands. For example, if you support the | |
4152 | pattern with a @code{define_expand}, then in such a case the | |
4153 | @code{define_expand} mustn't call @code{force_reg} or any other such | |
4154 | function which might generate new pseudo registers. | |
4155 | ||
4156 | This requirement exists even for subword modes on a RISC machine where | |
4157 | fetching those modes from memory normally requires several insns and | |
39ed8974 | 4158 | some temporary registers. |
03dda8e3 RK |
4159 | |
4160 | @findex change_address | |
4161 | During reload a memory reference with an invalid address may be passed | |
4162 | as an operand. Such an address will be replaced with a valid address | |
4163 | later in the reload pass. In this case, nothing may be done with the | |
4164 | address except to use it as it stands. If it is copied, it will not be | |
4165 | replaced with a valid address. No attempt should be made to make such | |
4166 | an address into a valid address and no routine (such as | |
4167 | @code{change_address}) that will do so may be called. Note that | |
4168 | @code{general_operand} will fail when applied to such an address. | |
4169 | ||
4170 | @findex reload_in_progress | |
4171 | The global variable @code{reload_in_progress} (which must be explicitly | |
4172 | declared if required) can be used to determine whether such special | |
4173 | handling is required. | |
4174 | ||
4175 | The variety of operands that have reloads depends on the rest of the | |
4176 | machine description, but typically on a RISC machine these can only be | |
4177 | pseudo registers that did not get hard registers, while on other | |
4178 | machines explicit memory references will get optional reloads. | |
4179 | ||
4180 | If a scratch register is required to move an object to or from memory, | |
f1db3576 JL |
4181 | it can be allocated using @code{gen_reg_rtx} prior to life analysis. |
4182 | ||
9c34dbbf | 4183 | If there are cases which need scratch registers during or after reload, |
8a99f6f9 | 4184 | you must provide an appropriate secondary_reload target hook. |
03dda8e3 | 4185 | |
ef4375b2 KZ |
4186 | @findex can_create_pseudo_p |
4187 | The macro @code{can_create_pseudo_p} can be used to determine if it | |
f1db3576 JL |
4188 | is unsafe to create new pseudo registers. If this variable is nonzero, then |
4189 | it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo. | |
4190 | ||
956d6950 | 4191 | The constraints on a @samp{mov@var{m}} must permit moving any hard |
03dda8e3 RK |
4192 | register to any other hard register provided that |
4193 | @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and | |
de8f4b07 AS |
4194 | @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value |
4195 | of 2. | |
03dda8e3 | 4196 | |
956d6950 | 4197 | It is obligatory to support floating point @samp{mov@var{m}} |
03dda8e3 RK |
4198 | instructions into and out of any registers that can hold fixed point |
4199 | values, because unions and structures (which have modes @code{SImode} or | |
4200 | @code{DImode}) can be in those registers and they may have floating | |
4201 | point members. | |
4202 | ||
956d6950 | 4203 | There may also be a need to support fixed point @samp{mov@var{m}} |
03dda8e3 RK |
4204 | instructions in and out of floating point registers. Unfortunately, I |
4205 | have forgotten why this was so, and I don't know whether it is still | |
4206 | true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in | |
4207 | floating point registers, then the constraints of the fixed point | |
956d6950 | 4208 | @samp{mov@var{m}} instructions must be designed to avoid ever trying to |
03dda8e3 RK |
4209 | reload into a floating point register. |
4210 | ||
4211 | @cindex @code{reload_in} instruction pattern | |
4212 | @cindex @code{reload_out} instruction pattern | |
4213 | @item @samp{reload_in@var{m}} | |
4214 | @itemx @samp{reload_out@var{m}} | |
8a99f6f9 R |
4215 | These named patterns have been obsoleted by the target hook |
4216 | @code{secondary_reload}. | |
4217 | ||
03dda8e3 RK |
4218 | Like @samp{mov@var{m}}, but used when a scratch register is required to |
4219 | move between operand 0 and operand 1. Operand 2 describes the scratch | |
4220 | register. See the discussion of the @code{SECONDARY_RELOAD_CLASS} | |
4221 | macro in @pxref{Register Classes}. | |
4222 | ||
d989f648 | 4223 | There are special restrictions on the form of the @code{match_operand}s |
f282ffb3 | 4224 | used in these patterns. First, only the predicate for the reload |
560dbedd RH |
4225 | operand is examined, i.e., @code{reload_in} examines operand 1, but not |
4226 | the predicates for operand 0 or 2. Second, there may be only one | |
d989f648 RH |
4227 | alternative in the constraints. Third, only a single register class |
4228 | letter may be used for the constraint; subsequent constraint letters | |
4229 | are ignored. As a special exception, an empty constraint string | |
4230 | matches the @code{ALL_REGS} register class. This may relieve ports | |
4231 | of the burden of defining an @code{ALL_REGS} constraint letter just | |
4232 | for these patterns. | |
4233 | ||
03dda8e3 RK |
4234 | @cindex @code{movstrict@var{m}} instruction pattern |
4235 | @item @samp{movstrict@var{m}} | |
4236 | Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg} | |
4237 | with mode @var{m} of a register whose natural mode is wider, | |
4238 | the @samp{movstrict@var{m}} instruction is guaranteed not to alter | |
4239 | any of the register except the part which belongs to mode @var{m}. | |
4240 | ||
1e0598e2 RH |
4241 | @cindex @code{movmisalign@var{m}} instruction pattern |
4242 | @item @samp{movmisalign@var{m}} | |
4243 | This variant of a move pattern is designed to load or store a value | |
4244 | from a memory address that is not naturally aligned for its mode. | |
4245 | For a store, the memory will be in operand 0; for a load, the memory | |
4246 | will be in operand 1. The other operand is guaranteed not to be a | |
4247 | memory, so that it's easy to tell whether this is a load or store. | |
4248 | ||
4249 | This pattern is used by the autovectorizer, and when expanding a | |
4250 | @code{MISALIGNED_INDIRECT_REF} expression. | |
4251 | ||
03dda8e3 RK |
4252 | @cindex @code{load_multiple} instruction pattern |
4253 | @item @samp{load_multiple} | |
4254 | Load several consecutive memory locations into consecutive registers. | |
4255 | Operand 0 is the first of the consecutive registers, operand 1 | |
4256 | is the first memory location, and operand 2 is a constant: the | |
4257 | number of consecutive registers. | |
4258 | ||
4259 | Define this only if the target machine really has such an instruction; | |
4260 | do not define this if the most efficient way of loading consecutive | |
4261 | registers from memory is to do them one at a time. | |
4262 | ||
4263 | On some machines, there are restrictions as to which consecutive | |
4264 | registers can be stored into memory, such as particular starting or | |
4265 | ending register numbers or only a range of valid counts. For those | |
4266 | machines, use a @code{define_expand} (@pxref{Expander Definitions}) | |
4267 | and make the pattern fail if the restrictions are not met. | |
4268 | ||
4269 | Write the generated insn as a @code{parallel} with elements being a | |
4270 | @code{set} of one register from the appropriate memory location (you may | |
4271 | also need @code{use} or @code{clobber} elements). Use a | |
4272 | @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See | |
c9693e96 | 4273 | @file{rs6000.md} for examples of the use of this insn pattern. |
03dda8e3 RK |
4274 | |
4275 | @cindex @samp{store_multiple} instruction pattern | |
4276 | @item @samp{store_multiple} | |
4277 | Similar to @samp{load_multiple}, but store several consecutive registers | |
4278 | into consecutive memory locations. Operand 0 is the first of the | |
4279 | consecutive memory locations, operand 1 is the first register, and | |
4280 | operand 2 is a constant: the number of consecutive registers. | |
4281 | ||
272c6793 RS |
4282 | @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern |
4283 | @item @samp{vec_load_lanes@var{m}@var{n}} | |
4284 | Perform an interleaved load of several vectors from memory operand 1 | |
4285 | into register operand 0. Both operands have mode @var{m}. The register | |
4286 | operand is viewed as holding consecutive vectors of mode @var{n}, | |
4287 | while the memory operand is a flat array that contains the same number | |
4288 | of elements. The operation is equivalent to: | |
4289 | ||
4290 | @smallexample | |
4291 | int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); | |
4292 | for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) | |
4293 | for (i = 0; i < c; i++) | |
4294 | operand0[i][j] = operand1[j * c + i]; | |
4295 | @end smallexample | |
4296 | ||
4297 | For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values | |
4298 | from memory into a register of mode @samp{TI}@. The register | |
4299 | contains two consecutive vectors of mode @samp{V4HI}@. | |
4300 | ||
4301 | This pattern can only be used if: | |
4302 | @smallexample | |
4303 | TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c}) | |
4304 | @end smallexample | |
4305 | is true. GCC assumes that, if a target supports this kind of | |
4306 | instruction for some mode @var{n}, it also supports unaligned | |
4307 | loads for vectors of mode @var{n}. | |
4308 | ||
4309 | @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern | |
4310 | @item @samp{vec_store_lanes@var{m}@var{n}} | |
4311 | Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory | |
4312 | and register operands reversed. That is, the instruction is | |
4313 | equivalent to: | |
4314 | ||
4315 | @smallexample | |
4316 | int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); | |
4317 | for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) | |
4318 | for (i = 0; i < c; i++) | |
4319 | operand0[j * c + i] = operand1[i][j]; | |
4320 | @end smallexample | |
4321 | ||
4322 | for a memory operand 0 and register operand 1. | |
4323 | ||
ef1140a9 JH |
4324 | @cindex @code{vec_set@var{m}} instruction pattern |
4325 | @item @samp{vec_set@var{m}} | |
4326 | Set given field in the vector value. Operand 0 is the vector to modify, | |
4327 | operand 1 is new value of field and operand 2 specify the field index. | |
4328 | ||
4329 | @cindex @code{vec_extract@var{m}} instruction pattern | |
4330 | @item @samp{vec_extract@var{m}} | |
4331 | Extract given field from the vector value. Operand 1 is the vector, operand 2 | |
4332 | specify field index and operand 0 place to store value into. | |
4333 | ||
4334 | @cindex @code{vec_init@var{m}} instruction pattern | |
4335 | @item @samp{vec_init@var{m}} | |
425a2bde | 4336 | Initialize the vector to given values. Operand 0 is the vector to initialize |
ef1140a9 JH |
4337 | and operand 1 is parallel containing values for individual fields. |
4338 | ||
e9e1d143 RG |
4339 | @cindex @code{vcond@var{m}@var{n}} instruction pattern |
4340 | @item @samp{vcond@var{m}@var{n}} | |
4341 | Output a conditional vector move. Operand 0 is the destination to | |
4342 | receive a combination of operand 1 and operand 2, which are of mode @var{m}, | |
4343 | dependent on the outcome of the predicate in operand 3 which is a | |
4344 | vector comparison with operands of mode @var{n} in operands 4 and 5. The | |
4345 | modes @var{m} and @var{n} should have the same size. Operand 0 | |
4346 | will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk} | |
4347 | where @var{msk} is computed by element-wise evaluation of the vector | |
4348 | comparison with a truth value of all-ones and a false value of all-zeros. | |
4349 | ||
2205ed25 RH |
4350 | @cindex @code{vec_perm@var{m}} instruction pattern |
4351 | @item @samp{vec_perm@var{m}} | |
4352 | Output a (variable) vector permutation. Operand 0 is the destination | |
4353 | to receive elements from operand 1 and operand 2, which are of mode | |
4354 | @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode | |
4355 | vector of the same width and number of elements as mode @var{m}. | |
4356 | ||
4357 | The input elements are numbered from 0 in operand 1 through | |
4358 | @math{2*@var{N}-1} in operand 2. The elements of the selector must | |
4359 | be computed modulo @math{2*@var{N}}. Note that if | |
4360 | @code{rtx_equal_p(operand1, operand2)}, this can be implemented | |
4361 | with just operand 1 and selector elements modulo @var{N}. | |
4362 | ||
d7943c8b RH |
4363 | In order to make things easy for a number of targets, if there is no |
4364 | @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q} | |
4365 | where @var{q} is a vector of @code{QImode} of the same width as @var{m}, | |
4366 | the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to | |
4367 | mode @var{q}. | |
4368 | ||
82675d94 | 4369 | @cindex @code{vec_perm_const@var{m}} instruction pattern |
2205ed25 RH |
4370 | @item @samp{vec_perm_const@var{m}} |
4371 | Like @samp{vec_perm} except that the permutation is a compile-time | |
4372 | constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}. | |
4373 | ||
4374 | Some targets cannot perform a permutation with a variable selector, | |
4375 | but can efficiently perform a constant permutation. Further, the | |
4376 | target hook @code{vec_perm_ok} is queried to determine if the | |
4377 | specific constant permutation is available efficiently; the named | |
4378 | pattern is never expanded without @code{vec_perm_ok} returning true. | |
4379 | ||
4380 | There is no need for a target to supply both @samp{vec_perm@var{m}} | |
4381 | and @samp{vec_perm_const@var{m}} if the former can trivially implement | |
4382 | the operation with, say, the vector constant loaded into a register. | |
4383 | ||
759915ca EC |
4384 | @cindex @code{push@var{m}1} instruction pattern |
4385 | @item @samp{push@var{m}1} | |
299c5111 | 4386 | Output a push instruction. Operand 0 is value to push. Used only when |
38f4324c JH |
4387 | @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be |
4388 | missing and in such case an @code{mov} expander is used instead, with a | |
6e9aac46 | 4389 | @code{MEM} expression forming the push operation. The @code{mov} expander |
38f4324c JH |
4390 | method is deprecated. |
4391 | ||
03dda8e3 RK |
4392 | @cindex @code{add@var{m}3} instruction pattern |
4393 | @item @samp{add@var{m}3} | |
4394 | Add operand 2 and operand 1, storing the result in operand 0. All operands | |
4395 | must have mode @var{m}. This can be used even on two-address machines, by | |
4396 | means of constraints requiring operands 1 and 0 to be the same location. | |
4397 | ||
0f996086 CF |
4398 | @cindex @code{ssadd@var{m}3} instruction pattern |
4399 | @cindex @code{usadd@var{m}3} instruction pattern | |
03dda8e3 | 4400 | @cindex @code{sub@var{m}3} instruction pattern |
0f996086 CF |
4401 | @cindex @code{sssub@var{m}3} instruction pattern |
4402 | @cindex @code{ussub@var{m}3} instruction pattern | |
03dda8e3 | 4403 | @cindex @code{mul@var{m}3} instruction pattern |
0f996086 CF |
4404 | @cindex @code{ssmul@var{m}3} instruction pattern |
4405 | @cindex @code{usmul@var{m}3} instruction pattern | |
03dda8e3 | 4406 | @cindex @code{div@var{m}3} instruction pattern |
0f996086 | 4407 | @cindex @code{ssdiv@var{m}3} instruction pattern |
03dda8e3 | 4408 | @cindex @code{udiv@var{m}3} instruction pattern |
0f996086 | 4409 | @cindex @code{usdiv@var{m}3} instruction pattern |
03dda8e3 RK |
4410 | @cindex @code{mod@var{m}3} instruction pattern |
4411 | @cindex @code{umod@var{m}3} instruction pattern | |
03dda8e3 RK |
4412 | @cindex @code{umin@var{m}3} instruction pattern |
4413 | @cindex @code{umax@var{m}3} instruction pattern | |
4414 | @cindex @code{and@var{m}3} instruction pattern | |
4415 | @cindex @code{ior@var{m}3} instruction pattern | |
4416 | @cindex @code{xor@var{m}3} instruction pattern | |
0f996086 CF |
4417 | @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3} |
4418 | @item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3} | |
4419 | @item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3} | |
4420 | @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3} | |
4421 | @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3} | |
7ae4d8d4 RH |
4422 | @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3} |
4423 | @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3} | |
03dda8e3 RK |
4424 | @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} |
4425 | Similar, for other arithmetic operations. | |
7ae4d8d4 | 4426 | |
1b1562a5 MM |
4427 | @cindex @code{fma@var{m}4} instruction pattern |
4428 | @item @samp{fma@var{m}4} | |
4429 | Multiply operand 2 and operand 1, then add operand 3, storing the | |
d6373302 KZ |
4430 | result in operand 0 without doing an intermediate rounding step. All |
4431 | operands must have mode @var{m}. This pattern is used to implement | |
4432 | the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from | |
4433 | the ISO C99 standard. | |
1b1562a5 | 4434 | |
16949072 RG |
4435 | @cindex @code{fms@var{m}4} instruction pattern |
4436 | @item @samp{fms@var{m}4} | |
4437 | Like @code{fma@var{m}4}, except operand 3 subtracted from the | |
4438 | product instead of added to the product. This is represented | |
4439 | in the rtl as | |
4440 | ||
4441 | @smallexample | |
4442 | (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3})) | |
4443 | @end smallexample | |
4444 | ||
4445 | @cindex @code{fnma@var{m}4} instruction pattern | |
4446 | @item @samp{fnma@var{m}4} | |
4447 | Like @code{fma@var{m}4} except that the intermediate product | |
4448 | is negated before being added to operand 3. This is represented | |
4449 | in the rtl as | |
4450 | ||
4451 | @smallexample | |
4452 | (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3}) | |
4453 | @end smallexample | |
4454 | ||
4455 | @cindex @code{fnms@var{m}4} instruction pattern | |
4456 | @item @samp{fnms@var{m}4} | |
4457 | Like @code{fms@var{m}4} except that the intermediate product | |
4458 | is negated before subtracting operand 3. This is represented | |
4459 | in the rtl as | |
4460 | ||
4461 | @smallexample | |
4462 | (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3})) | |
4463 | @end smallexample | |
4464 | ||
b71b019a JH |
4465 | @cindex @code{min@var{m}3} instruction pattern |
4466 | @cindex @code{max@var{m}3} instruction pattern | |
7ae4d8d4 RH |
4467 | @item @samp{smin@var{m}3}, @samp{smax@var{m}3} |
4468 | Signed minimum and maximum operations. When used with floating point, | |
4469 | if both operands are zeros, or if either operand is @code{NaN}, then | |
4470 | it is unspecified which of the two operands is returned as the result. | |
03dda8e3 | 4471 | |
61abee65 DN |
4472 | @cindex @code{reduc_smin_@var{m}} instruction pattern |
4473 | @cindex @code{reduc_smax_@var{m}} instruction pattern | |
4474 | @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}} | |
4475 | Find the signed minimum/maximum of the elements of a vector. The vector is | |
759915ca EC |
4476 | operand 1, and the scalar result is stored in the least significant bits of |
4477 | operand 0 (also a vector). The output and input vector should have the same | |
61abee65 DN |
4478 | modes. |
4479 | ||
4480 | @cindex @code{reduc_umin_@var{m}} instruction pattern | |
4481 | @cindex @code{reduc_umax_@var{m}} instruction pattern | |
4482 | @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}} | |
4483 | Find the unsigned minimum/maximum of the elements of a vector. The vector is | |
759915ca EC |
4484 | operand 1, and the scalar result is stored in the least significant bits of |
4485 | operand 0 (also a vector). The output and input vector should have the same | |
61abee65 DN |
4486 | modes. |
4487 | ||
4488 | @cindex @code{reduc_splus_@var{m}} instruction pattern | |
4489 | @item @samp{reduc_splus_@var{m}} | |
759915ca EC |
4490 | Compute the sum of the signed elements of a vector. The vector is operand 1, |
4491 | and the scalar result is stored in the least significant bits of operand 0 | |
61abee65 DN |
4492 | (also a vector). The output and input vector should have the same modes. |
4493 | ||
4494 | @cindex @code{reduc_uplus_@var{m}} instruction pattern | |
4495 | @item @samp{reduc_uplus_@var{m}} | |
759915ca EC |
4496 | Compute the sum of the unsigned elements of a vector. The vector is operand 1, |
4497 | and the scalar result is stored in the least significant bits of operand 0 | |
61abee65 DN |
4498 | (also a vector). The output and input vector should have the same modes. |
4499 | ||
20f06221 DN |
4500 | @cindex @code{sdot_prod@var{m}} instruction pattern |
4501 | @item @samp{sdot_prod@var{m}} | |
4502 | @cindex @code{udot_prod@var{m}} instruction pattern | |
4503 | @item @samp{udot_prod@var{m}} | |
ff2ce160 MS |
4504 | Compute the sum of the products of two signed/unsigned elements. |
4505 | Operand 1 and operand 2 are of the same mode. Their product, which is of a | |
4506 | wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or | |
20f06221 | 4507 | wider than the mode of the product. The result is placed in operand 0, which |
ff2ce160 | 4508 | is of the same mode as operand 3. |
20f06221 DN |
4509 | |
4510 | @cindex @code{ssum_widen@var{m3}} instruction pattern | |
4511 | @item @samp{ssum_widen@var{m3}} | |
4512 | @cindex @code{usum_widen@var{m3}} instruction pattern | |
4513 | @item @samp{usum_widen@var{m3}} | |
ff2ce160 | 4514 | Operands 0 and 2 are of the same mode, which is wider than the mode of |
20f06221 DN |
4515 | operand 1. Add operand 1 to operand 2 and place the widened result in |
4516 | operand 0. (This is used express accumulation of elements into an accumulator | |
4517 | of a wider mode.) | |
4518 | ||
61abee65 DN |
4519 | @cindex @code{vec_shl_@var{m}} instruction pattern |
4520 | @cindex @code{vec_shr_@var{m}} instruction pattern | |
4521 | @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}} | |
4522 | Whole vector left/right shift in bits. | |
4523 | Operand 1 is a vector to be shifted. | |
759915ca | 4524 | Operand 2 is an integer shift amount in bits. |
61abee65 DN |
4525 | Operand 0 is where the resulting shifted vector is stored. |
4526 | The output and input vectors should have the same modes. | |
4527 | ||
8115817b UB |
4528 | @cindex @code{vec_pack_trunc_@var{m}} instruction pattern |
4529 | @item @samp{vec_pack_trunc_@var{m}} | |
4530 | Narrow (demote) and merge the elements of two vectors. Operands 1 and 2 | |
4531 | are vectors of the same mode having N integral or floating point elements | |
0ee2ea09 | 4532 | of size S@. Operand 0 is the resulting vector in which 2*N elements of |
8115817b UB |
4533 | size N/2 are concatenated after narrowing them down using truncation. |
4534 | ||
89d67cca DN |
4535 | @cindex @code{vec_pack_ssat_@var{m}} instruction pattern |
4536 | @cindex @code{vec_pack_usat_@var{m}} instruction pattern | |
8115817b UB |
4537 | @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}} |
4538 | Narrow (demote) and merge the elements of two vectors. Operands 1 and 2 | |
4539 | are vectors of the same mode having N integral elements of size S. | |
89d67cca | 4540 | Operand 0 is the resulting vector in which the elements of the two input |
8115817b UB |
4541 | vectors are concatenated after narrowing them down using signed/unsigned |
4542 | saturating arithmetic. | |
89d67cca | 4543 | |
d9987fb4 UB |
4544 | @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern |
4545 | @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern | |
4546 | @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}} | |
4547 | Narrow, convert to signed/unsigned integral type and merge the elements | |
4548 | of two vectors. Operands 1 and 2 are vectors of the same mode having N | |
0ee2ea09 | 4549 | floating point elements of size S@. Operand 0 is the resulting vector |
d9987fb4 UB |
4550 | in which 2*N elements of size N/2 are concatenated. |
4551 | ||
89d67cca DN |
4552 | @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern |
4553 | @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern | |
8115817b UB |
4554 | @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}} |
4555 | Extract and widen (promote) the high/low part of a vector of signed | |
4556 | integral or floating point elements. The input vector (operand 1) has N | |
0ee2ea09 | 4557 | elements of size S@. Widen (promote) the high/low elements of the vector |
8115817b UB |
4558 | using signed or floating point extension and place the resulting N/2 |
4559 | values of size 2*S in the output vector (operand 0). | |
4560 | ||
89d67cca DN |
4561 | @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern |
4562 | @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern | |
8115817b UB |
4563 | @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}} |
4564 | Extract and widen (promote) the high/low part of a vector of unsigned | |
4565 | integral elements. The input vector (operand 1) has N elements of size S. | |
4566 | Widen (promote) the high/low elements of the vector using zero extension and | |
4567 | place the resulting N/2 values of size 2*S in the output vector (operand 0). | |
89d67cca | 4568 | |
d9987fb4 UB |
4569 | @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern |
4570 | @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern | |
4571 | @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern | |
4572 | @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern | |
4573 | @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}} | |
4574 | @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}} | |
4575 | Extract, convert to floating point type and widen the high/low part of a | |
4576 | vector of signed/unsigned integral elements. The input vector (operand 1) | |
0ee2ea09 | 4577 | has N elements of size S@. Convert the high/low elements of the vector using |
d9987fb4 UB |
4578 | floating point conversion and place the resulting N/2 values of size 2*S in |
4579 | the output vector (operand 0). | |
4580 | ||
89d67cca | 4581 | @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern |
3f30a9a6 | 4582 | @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern |
89d67cca DN |
4583 | @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern |
4584 | @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern | |
3f30a9a6 RH |
4585 | @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern |
4586 | @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern | |
4587 | @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern | |
4588 | @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern | |
d9987fb4 UB |
4589 | @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}} |
4590 | @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}} | |
3f30a9a6 RH |
4591 | @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}} |
4592 | @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}} | |
8115817b | 4593 | Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2) |
0ee2ea09 | 4594 | are vectors with N signed/unsigned elements of size S@. Multiply the high/low |
3f30a9a6 RH |
4595 | or even/odd elements of the two vectors, and put the N/2 products of size 2*S |
4596 | in the output vector (operand 0). | |
89d67cca | 4597 | |
36ba4aae IR |
4598 | @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern |
4599 | @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern | |
4600 | @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern | |
4601 | @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern | |
4602 | @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}} | |
4603 | @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}} | |
4604 | Signed/Unsigned widening shift left. The first input (operand 1) is a vector | |
4605 | with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift | |
4606 | the high/low elements of operand 1, and put the N/2 results of size 2*S in the | |
4607 | output vector (operand 0). | |
4608 | ||
03dda8e3 RK |
4609 | @cindex @code{mulhisi3} instruction pattern |
4610 | @item @samp{mulhisi3} | |
4611 | Multiply operands 1 and 2, which have mode @code{HImode}, and store | |
4612 | a @code{SImode} product in operand 0. | |
4613 | ||
4614 | @cindex @code{mulqihi3} instruction pattern | |
4615 | @cindex @code{mulsidi3} instruction pattern | |
4616 | @item @samp{mulqihi3}, @samp{mulsidi3} | |
4617 | Similar widening-multiplication instructions of other widths. | |
4618 | ||
4619 | @cindex @code{umulqihi3} instruction pattern | |
4620 | @cindex @code{umulhisi3} instruction pattern | |
4621 | @cindex @code{umulsidi3} instruction pattern | |
4622 | @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3} | |
4623 | Similar widening-multiplication instructions that do unsigned | |
4624 | multiplication. | |
4625 | ||
8b44057d BS |
4626 | @cindex @code{usmulqihi3} instruction pattern |
4627 | @cindex @code{usmulhisi3} instruction pattern | |
4628 | @cindex @code{usmulsidi3} instruction pattern | |
4629 | @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3} | |
4630 | Similar widening-multiplication instructions that interpret the first | |
4631 | operand as unsigned and the second operand as signed, then do a signed | |
4632 | multiplication. | |
4633 | ||
03dda8e3 | 4634 | @cindex @code{smul@var{m}3_highpart} instruction pattern |
759c58af | 4635 | @item @samp{smul@var{m}3_highpart} |
03dda8e3 RK |
4636 | Perform a signed multiplication of operands 1 and 2, which have mode |
4637 | @var{m}, and store the most significant half of the product in operand 0. | |
4638 | The least significant half of the product is discarded. | |
4639 | ||
4640 | @cindex @code{umul@var{m}3_highpart} instruction pattern | |
4641 | @item @samp{umul@var{m}3_highpart} | |
4642 | Similar, but the multiplication is unsigned. | |
4643 | ||
7f9844ca RS |
4644 | @cindex @code{madd@var{m}@var{n}4} instruction pattern |
4645 | @item @samp{madd@var{m}@var{n}4} | |
4646 | Multiply operands 1 and 2, sign-extend them to mode @var{n}, add | |
4647 | operand 3, and store the result in operand 0. Operands 1 and 2 | |
4648 | have mode @var{m} and operands 0 and 3 have mode @var{n}. | |
0f996086 | 4649 | Both modes must be integer or fixed-point modes and @var{n} must be twice |
7f9844ca RS |
4650 | the size of @var{m}. |
4651 | ||
4652 | In other words, @code{madd@var{m}@var{n}4} is like | |
4653 | @code{mul@var{m}@var{n}3} except that it also adds operand 3. | |
4654 | ||
4655 | These instructions are not allowed to @code{FAIL}. | |
4656 | ||
4657 | @cindex @code{umadd@var{m}@var{n}4} instruction pattern | |
4658 | @item @samp{umadd@var{m}@var{n}4} | |
4659 | Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication | |
4660 | operands instead of sign-extending them. | |
4661 | ||
0f996086 CF |
4662 | @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern |
4663 | @item @samp{ssmadd@var{m}@var{n}4} | |
4664 | Like @code{madd@var{m}@var{n}4}, but all involved operations must be | |
4665 | signed-saturating. | |
4666 | ||
4667 | @cindex @code{usmadd@var{m}@var{n}4} instruction pattern | |
4668 | @item @samp{usmadd@var{m}@var{n}4} | |
4669 | Like @code{umadd@var{m}@var{n}4}, but all involved operations must be | |
4670 | unsigned-saturating. | |
4671 | ||
14661f36 CF |
4672 | @cindex @code{msub@var{m}@var{n}4} instruction pattern |
4673 | @item @samp{msub@var{m}@var{n}4} | |
4674 | Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the | |
4675 | result from operand 3, and store the result in operand 0. Operands 1 and 2 | |
4676 | have mode @var{m} and operands 0 and 3 have mode @var{n}. | |
0f996086 | 4677 | Both modes must be integer or fixed-point modes and @var{n} must be twice |
14661f36 CF |
4678 | the size of @var{m}. |
4679 | ||
4680 | In other words, @code{msub@var{m}@var{n}4} is like | |
4681 | @code{mul@var{m}@var{n}3} except that it also subtracts the result | |
4682 | from operand 3. | |
4683 | ||
4684 | These instructions are not allowed to @code{FAIL}. | |
4685 | ||
4686 | @cindex @code{umsub@var{m}@var{n}4} instruction pattern | |
4687 | @item @samp{umsub@var{m}@var{n}4} | |
4688 | Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication | |
4689 | operands instead of sign-extending them. | |
4690 | ||
0f996086 CF |
4691 | @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern |
4692 | @item @samp{ssmsub@var{m}@var{n}4} | |
4693 | Like @code{msub@var{m}@var{n}4}, but all involved operations must be | |
4694 | signed-saturating. | |
4695 | ||
4696 | @cindex @code{usmsub@var{m}@var{n}4} instruction pattern | |
4697 | @item @samp{usmsub@var{m}@var{n}4} | |
4698 | Like @code{umsub@var{m}@var{n}4}, but all involved operations must be | |
4699 | unsigned-saturating. | |
4700 | ||
03dda8e3 RK |
4701 | @cindex @code{divmod@var{m}4} instruction pattern |
4702 | @item @samp{divmod@var{m}4} | |
4703 | Signed division that produces both a quotient and a remainder. | |
4704 | Operand 1 is divided by operand 2 to produce a quotient stored | |
4705 | in operand 0 and a remainder stored in operand 3. | |
4706 | ||
4707 | For machines with an instruction that produces both a quotient and a | |
4708 | remainder, provide a pattern for @samp{divmod@var{m}4} but do not | |
4709 | provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This | |
4710 | allows optimization in the relatively common case when both the quotient | |
4711 | and remainder are computed. | |
4712 | ||
4713 | If an instruction that just produces a quotient or just a remainder | |
4714 | exists and is more efficient than the instruction that produces both, | |
4715 | write the output routine of @samp{divmod@var{m}4} to call | |
4716 | @code{find_reg_note} and look for a @code{REG_UNUSED} note on the | |
4717 | quotient or remainder and generate the appropriate instruction. | |
4718 | ||
4719 | @cindex @code{udivmod@var{m}4} instruction pattern | |
4720 | @item @samp{udivmod@var{m}4} | |
4721 | Similar, but does unsigned division. | |
4722 | ||
273a2526 | 4723 | @anchor{shift patterns} |
03dda8e3 | 4724 | @cindex @code{ashl@var{m}3} instruction pattern |
0f996086 CF |
4725 | @cindex @code{ssashl@var{m}3} instruction pattern |
4726 | @cindex @code{usashl@var{m}3} instruction pattern | |
4727 | @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3} | |
03dda8e3 RK |
4728 | Arithmetic-shift operand 1 left by a number of bits specified by operand |
4729 | 2, and store the result in operand 0. Here @var{m} is the mode of | |
4730 | operand 0 and operand 1; operand 2's mode is specified by the | |
4731 | instruction pattern, and the compiler will convert the operand to that | |
273a2526 RS |
4732 | mode before generating the instruction. The meaning of out-of-range shift |
4733 | counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}. | |
71d46ca5 | 4734 | @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type. |
03dda8e3 RK |
4735 | |
4736 | @cindex @code{ashr@var{m}3} instruction pattern | |
4737 | @cindex @code{lshr@var{m}3} instruction pattern | |
4738 | @cindex @code{rotl@var{m}3} instruction pattern | |
4739 | @cindex @code{rotr@var{m}3} instruction pattern | |
4740 | @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3} | |
4741 | Other shift and rotate instructions, analogous to the | |
71d46ca5 MM |
4742 | @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type. |
4743 | ||
4744 | @cindex @code{vashl@var{m}3} instruction pattern | |
4745 | @cindex @code{vashr@var{m}3} instruction pattern | |
4746 | @cindex @code{vlshr@var{m}3} instruction pattern | |
4747 | @cindex @code{vrotl@var{m}3} instruction pattern | |
4748 | @cindex @code{vrotr@var{m}3} instruction pattern | |
4749 | @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3} | |
4750 | Vector shift and rotate instructions that take vectors as operand 2 | |
4751 | instead of a scalar type. | |
03dda8e3 | 4752 | |
ac868f29 EB |
4753 | @cindex @code{bswap@var{m}2} instruction pattern |
4754 | @item @samp{bswap@var{m}2} | |
4755 | Reverse the order of bytes of operand 1 and store the result in operand 0. | |
4756 | ||
03dda8e3 | 4757 | @cindex @code{neg@var{m}2} instruction pattern |
0f996086 CF |
4758 | @cindex @code{ssneg@var{m}2} instruction pattern |
4759 | @cindex @code{usneg@var{m}2} instruction pattern | |
4760 | @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2} | |
03dda8e3 RK |
4761 | Negate operand 1 and store the result in operand 0. |
4762 | ||
4763 | @cindex @code{abs@var{m}2} instruction pattern | |
4764 | @item @samp{abs@var{m}2} | |
4765 | Store the absolute value of operand 1 into operand 0. | |
4766 | ||
4767 | @cindex @code{sqrt@var{m}2} instruction pattern | |
4768 | @item @samp{sqrt@var{m}2} | |
4769 | Store the square root of operand 1 into operand 0. | |
4770 | ||
4771 | The @code{sqrt} built-in function of C always uses the mode which | |
e7b489c8 RS |
4772 | corresponds to the C data type @code{double} and the @code{sqrtf} |
4773 | built-in function uses the mode which corresponds to the C data | |
4774 | type @code{float}. | |
4775 | ||
17b98269 UB |
4776 | @cindex @code{fmod@var{m}3} instruction pattern |
4777 | @item @samp{fmod@var{m}3} | |
4778 | Store the remainder of dividing operand 1 by operand 2 into | |
4779 | operand 0, rounded towards zero to an integer. | |
4780 | ||
4781 | The @code{fmod} built-in function of C always uses the mode which | |
4782 | corresponds to the C data type @code{double} and the @code{fmodf} | |
4783 | built-in function uses the mode which corresponds to the C data | |
4784 | type @code{float}. | |
4785 | ||
4786 | @cindex @code{remainder@var{m}3} instruction pattern | |
4787 | @item @samp{remainder@var{m}3} | |
4788 | Store the remainder of dividing operand 1 by operand 2 into | |
4789 | operand 0, rounded to the nearest integer. | |
4790 | ||
4791 | The @code{remainder} built-in function of C always uses the mode | |
4792 | which corresponds to the C data type @code{double} and the | |
4793 | @code{remainderf} built-in function uses the mode which corresponds | |
4794 | to the C data type @code{float}. | |
4795 | ||
e7b489c8 RS |
4796 | @cindex @code{cos@var{m}2} instruction pattern |
4797 | @item @samp{cos@var{m}2} | |
4798 | Store the cosine of operand 1 into operand 0. | |
4799 | ||
4800 | The @code{cos} built-in function of C always uses the mode which | |
4801 | corresponds to the C data type @code{double} and the @code{cosf} | |
4802 | built-in function uses the mode which corresponds to the C data | |
4803 | type @code{float}. | |
4804 | ||
4805 | @cindex @code{sin@var{m}2} instruction pattern | |
4806 | @item @samp{sin@var{m}2} | |
4807 | Store the sine of operand 1 into operand 0. | |
4808 | ||
4809 | The @code{sin} built-in function of C always uses the mode which | |
4810 | corresponds to the C data type @code{double} and the @code{sinf} | |
4811 | built-in function uses the mode which corresponds to the C data | |
4812 | type @code{float}. | |
4813 | ||
6d1f6aff OE |
4814 | @cindex @code{sincos@var{m}3} instruction pattern |
4815 | @item @samp{sincos@var{m}3} | |
4816 | Store the sine of operand 2 into operand 0 and the cosine of | |
4817 | operand 2 into operand 1. | |
4818 | ||
4819 | The @code{sin} and @code{cos} built-in functions of C always use the | |
4820 | mode which corresponds to the C data type @code{double} and the | |
4821 | @code{sinf} and @code{cosf} built-in function use the mode which | |
4822 | corresponds to the C data type @code{float}. | |
4823 | Targets that can calculate the sine and cosine simultaneously can | |
4824 | implement this pattern as opposed to implementing individual | |
4825 | @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin} | |
4826 | and @code{cos} built-in functions will then be expanded to the | |
4827 | @code{sincos@var{m}3} pattern, with one of the output values | |
4828 | left unused. | |
4829 | ||
e7b489c8 RS |
4830 | @cindex @code{exp@var{m}2} instruction pattern |
4831 | @item @samp{exp@var{m}2} | |
4832 | Store the exponential of operand 1 into operand 0. | |
4833 | ||
4834 | The @code{exp} built-in function of C always uses the mode which | |
4835 | corresponds to the C data type @code{double} and the @code{expf} | |
4836 | built-in function uses the mode which corresponds to the C data | |
4837 | type @code{float}. | |
4838 | ||
4839 | @cindex @code{log@var{m}2} instruction pattern | |
4840 | @item @samp{log@var{m}2} | |
4841 | Store the natural logarithm of operand 1 into operand 0. | |
4842 | ||
4843 | The @code{log} built-in function of C always uses the mode which | |
4844 | corresponds to the C data type @code{double} and the @code{logf} | |
4845 | built-in function uses the mode which corresponds to the C data | |
4846 | type @code{float}. | |
03dda8e3 | 4847 | |
b5e01d4b RS |
4848 | @cindex @code{pow@var{m}3} instruction pattern |
4849 | @item @samp{pow@var{m}3} | |
4850 | Store the value of operand 1 raised to the exponent operand 2 | |
4851 | into operand 0. | |
4852 | ||
4853 | The @code{pow} built-in function of C always uses the mode which | |
4854 | corresponds to the C data type @code{double} and the @code{powf} | |
4855 | built-in function uses the mode which corresponds to the C data | |
4856 | type @code{float}. | |
4857 | ||
4858 | @cindex @code{atan2@var{m}3} instruction pattern | |
4859 | @item @samp{atan2@var{m}3} | |
4860 | Store the arc tangent (inverse tangent) of operand 1 divided by | |
4861 | operand 2 into operand 0, using the signs of both arguments to | |
4862 | determine the quadrant of the result. | |
4863 | ||
4864 | The @code{atan2} built-in function of C always uses the mode which | |
4865 | corresponds to the C data type @code{double} and the @code{atan2f} | |
4866 | built-in function uses the mode which corresponds to the C data | |
4867 | type @code{float}. | |
4868 | ||
4977bab6 ZW |
4869 | @cindex @code{floor@var{m}2} instruction pattern |
4870 | @item @samp{floor@var{m}2} | |
4871 | Store the largest integral value not greater than argument. | |
4872 | ||
4873 | The @code{floor} built-in function of C always uses the mode which | |
4874 | corresponds to the C data type @code{double} and the @code{floorf} | |
4875 | built-in function uses the mode which corresponds to the C data | |
4876 | type @code{float}. | |
4877 | ||
10553f10 UB |
4878 | @cindex @code{btrunc@var{m}2} instruction pattern |
4879 | @item @samp{btrunc@var{m}2} | |
4977bab6 ZW |
4880 | Store the argument rounded to integer towards zero. |
4881 | ||
4882 | The @code{trunc} built-in function of C always uses the mode which | |
4883 | corresponds to the C data type @code{double} and the @code{truncf} | |
4884 | built-in function uses the mode which corresponds to the C data | |
4885 | type @code{float}. | |
4886 | ||
4887 | @cindex @code{round@var{m}2} instruction pattern | |
4888 | @item @samp{round@var{m}2} | |
4889 | Store the argument rounded to integer away from zero. | |
4890 | ||
4891 | The @code{round} built-in function of C always uses the mode which | |
4892 | corresponds to the C data type @code{double} and the @code{roundf} | |
4893 | built-in function uses the mode which corresponds to the C data | |
4894 | type @code{float}. | |
4895 | ||
4896 | @cindex @code{ceil@var{m}2} instruction pattern | |
4897 | @item @samp{ceil@var{m}2} | |
4898 | Store the argument rounded to integer away from zero. | |
4899 | ||
4900 | The @code{ceil} built-in function of C always uses the mode which | |
4901 | corresponds to the C data type @code{double} and the @code{ceilf} | |
4902 | built-in function uses the mode which corresponds to the C data | |
4903 | type @code{float}. | |
4904 | ||
4905 | @cindex @code{nearbyint@var{m}2} instruction pattern | |
4906 | @item @samp{nearbyint@var{m}2} | |
4907 | Store the argument rounded according to the default rounding mode | |
4908 | ||
4909 | The @code{nearbyint} built-in function of C always uses the mode which | |
4910 | corresponds to the C data type @code{double} and the @code{nearbyintf} | |
4911 | built-in function uses the mode which corresponds to the C data | |
4912 | type @code{float}. | |
4913 | ||
10553f10 UB |
4914 | @cindex @code{rint@var{m}2} instruction pattern |
4915 | @item @samp{rint@var{m}2} | |
4916 | Store the argument rounded according to the default rounding mode and | |
4917 | raise the inexact exception when the result differs in value from | |
4918 | the argument | |
4919 | ||
4920 | The @code{rint} built-in function of C always uses the mode which | |
4921 | corresponds to the C data type @code{double} and the @code{rintf} | |
4922 | built-in function uses the mode which corresponds to the C data | |
4923 | type @code{float}. | |
4924 | ||
bb7f0423 RG |
4925 | @cindex @code{lrint@var{m}@var{n}2} |
4926 | @item @samp{lrint@var{m}@var{n}2} | |
4927 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
4928 | point mode @var{n} as a signed number according to the current | |
4929 | rounding mode and store in operand 0 (which has mode @var{n}). | |
4930 | ||
4d81bf84 | 4931 | @cindex @code{lround@var{m}@var{n}2} |
e0d4c0b3 | 4932 | @item @samp{lround@var{m}@var{n}2} |
4d81bf84 RG |
4933 | Convert operand 1 (valid for floating point mode @var{m}) to fixed |
4934 | point mode @var{n} as a signed number rounding to nearest and away | |
4935 | from zero and store in operand 0 (which has mode @var{n}). | |
4936 | ||
c3a4177f | 4937 | @cindex @code{lfloor@var{m}@var{n}2} |
e0d4c0b3 | 4938 | @item @samp{lfloor@var{m}@var{n}2} |
c3a4177f RG |
4939 | Convert operand 1 (valid for floating point mode @var{m}) to fixed |
4940 | point mode @var{n} as a signed number rounding down and store in | |
4941 | operand 0 (which has mode @var{n}). | |
4942 | ||
4943 | @cindex @code{lceil@var{m}@var{n}2} | |
e0d4c0b3 | 4944 | @item @samp{lceil@var{m}@var{n}2} |
c3a4177f RG |
4945 | Convert operand 1 (valid for floating point mode @var{m}) to fixed |
4946 | point mode @var{n} as a signed number rounding up and store in | |
4947 | operand 0 (which has mode @var{n}). | |
4948 | ||
d35a40fc DE |
4949 | @cindex @code{copysign@var{m}3} instruction pattern |
4950 | @item @samp{copysign@var{m}3} | |
4951 | Store a value with the magnitude of operand 1 and the sign of operand | |
4952 | 2 into operand 0. | |
4953 | ||
4954 | The @code{copysign} built-in function of C always uses the mode which | |
4955 | corresponds to the C data type @code{double} and the @code{copysignf} | |
4956 | built-in function uses the mode which corresponds to the C data | |
4957 | type @code{float}. | |
4958 | ||
03dda8e3 RK |
4959 | @cindex @code{ffs@var{m}2} instruction pattern |
4960 | @item @samp{ffs@var{m}2} | |
4961 | Store into operand 0 one plus the index of the least significant 1-bit | |
4962 | of operand 1. If operand 1 is zero, store zero. @var{m} is the mode | |
4963 | of operand 0; operand 1's mode is specified by the instruction | |
4964 | pattern, and the compiler will convert the operand to that mode before | |
4965 | generating the instruction. | |
4966 | ||
4967 | The @code{ffs} built-in function of C always uses the mode which | |
4968 | corresponds to the C data type @code{int}. | |
4969 | ||
2928cd7a RH |
4970 | @cindex @code{clz@var{m}2} instruction pattern |
4971 | @item @samp{clz@var{m}2} | |
4972 | Store into operand 0 the number of leading 0-bits in @var{x}, starting | |
2a6627c2 JN |
4973 | at the most significant bit position. If @var{x} is 0, the |
4974 | @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if | |
4975 | the result is undefined or has a useful value. | |
4976 | @var{m} is the mode of operand 0; operand 1's mode is | |
2928cd7a RH |
4977 | specified by the instruction pattern, and the compiler will convert the |
4978 | operand to that mode before generating the instruction. | |
4979 | ||
4980 | @cindex @code{ctz@var{m}2} instruction pattern | |
4981 | @item @samp{ctz@var{m}2} | |
4982 | Store into operand 0 the number of trailing 0-bits in @var{x}, starting | |
2a6627c2 JN |
4983 | at the least significant bit position. If @var{x} is 0, the |
4984 | @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if | |
4985 | the result is undefined or has a useful value. | |
4986 | @var{m} is the mode of operand 0; operand 1's mode is | |
2928cd7a RH |
4987 | specified by the instruction pattern, and the compiler will convert the |
4988 | operand to that mode before generating the instruction. | |
4989 | ||
4990 | @cindex @code{popcount@var{m}2} instruction pattern | |
4991 | @item @samp{popcount@var{m}2} | |
4992 | Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the | |
4993 | mode of operand 0; operand 1's mode is specified by the instruction | |
4994 | pattern, and the compiler will convert the operand to that mode before | |
4995 | generating the instruction. | |
4996 | ||
4997 | @cindex @code{parity@var{m}2} instruction pattern | |
4998 | @item @samp{parity@var{m}2} | |
8a36672b | 4999 | Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits |
2928cd7a RH |
5000 | in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode |
5001 | is specified by the instruction pattern, and the compiler will convert | |
5002 | the operand to that mode before generating the instruction. | |
5003 | ||
03dda8e3 RK |
5004 | @cindex @code{one_cmpl@var{m}2} instruction pattern |
5005 | @item @samp{one_cmpl@var{m}2} | |
5006 | Store the bitwise-complement of operand 1 into operand 0. | |
5007 | ||
70128ad9 AO |
5008 | @cindex @code{movmem@var{m}} instruction pattern |
5009 | @item @samp{movmem@var{m}} | |
beed8fc0 AO |
5010 | Block move instruction. The destination and source blocks of memory |
5011 | are the first two operands, and both are @code{mem:BLK}s with an | |
5012 | address in mode @code{Pmode}. | |
e5e809f4 | 5013 | |
03dda8e3 | 5014 | The number of bytes to move is the third operand, in mode @var{m}. |
e5e809f4 JL |
5015 | Usually, you specify @code{word_mode} for @var{m}. However, if you can |
5016 | generate better code knowing the range of valid lengths is smaller than | |
5017 | those representable in a full word, you should provide a pattern with a | |
5018 | mode corresponding to the range of values you can handle efficiently | |
5019 | (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers | |
5020 | that appear negative) and also a pattern with @code{word_mode}. | |
03dda8e3 RK |
5021 | |
5022 | The fourth operand is the known shared alignment of the source and | |
5023 | destination, in the form of a @code{const_int} rtx. Thus, if the | |
5024 | compiler knows that both source and destination are word-aligned, | |
5025 | it may provide the value 4 for this operand. | |
5026 | ||
079a182e JH |
5027 | Optional operands 5 and 6 specify expected alignment and size of block |
5028 | respectively. The expected alignment differs from alignment in operand 4 | |
5029 | in a way that the blocks are not required to be aligned according to it in | |
9946ca2d RA |
5030 | all cases. This expected alignment is also in bytes, just like operand 4. |
5031 | Expected size, when unknown, is set to @code{(const_int -1)}. | |
079a182e | 5032 | |
70128ad9 | 5033 | Descriptions of multiple @code{movmem@var{m}} patterns can only be |
4693911f | 5034 | beneficial if the patterns for smaller modes have fewer restrictions |
8c01d9b6 | 5035 | on their first, second and fourth operands. Note that the mode @var{m} |
70128ad9 | 5036 | in @code{movmem@var{m}} does not impose any restriction on the mode of |
8c01d9b6 JL |
5037 | individually moved data units in the block. |
5038 | ||
03dda8e3 RK |
5039 | These patterns need not give special consideration to the possibility |
5040 | that the source and destination strings might overlap. | |
5041 | ||
beed8fc0 AO |
5042 | @cindex @code{movstr} instruction pattern |
5043 | @item @samp{movstr} | |
5044 | String copy instruction, with @code{stpcpy} semantics. Operand 0 is | |
5045 | an output operand in mode @code{Pmode}. The addresses of the | |
5046 | destination and source strings are operands 1 and 2, and both are | |
5047 | @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of | |
5048 | the expansion of this pattern should store in operand 0 the address in | |
5049 | which the @code{NUL} terminator was stored in the destination string. | |
5050 | ||
57e84f18 AS |
5051 | @cindex @code{setmem@var{m}} instruction pattern |
5052 | @item @samp{setmem@var{m}} | |
5053 | Block set instruction. The destination string is the first operand, | |
beed8fc0 | 5054 | given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The |
57e84f18 AS |
5055 | number of bytes to set is the second operand, in mode @var{m}. The value to |
5056 | initialize the memory with is the third operand. Targets that only support the | |
5057 | clearing of memory should reject any value that is not the constant 0. See | |
beed8fc0 | 5058 | @samp{movmem@var{m}} for a discussion of the choice of mode. |
03dda8e3 | 5059 | |
57e84f18 | 5060 | The fourth operand is the known alignment of the destination, in the form |
03dda8e3 RK |
5061 | of a @code{const_int} rtx. Thus, if the compiler knows that the |
5062 | destination is word-aligned, it may provide the value 4 for this | |
5063 | operand. | |
5064 | ||
079a182e JH |
5065 | Optional operands 5 and 6 specify expected alignment and size of block |
5066 | respectively. The expected alignment differs from alignment in operand 4 | |
5067 | in a way that the blocks are not required to be aligned according to it in | |
9946ca2d RA |
5068 | all cases. This expected alignment is also in bytes, just like operand 4. |
5069 | Expected size, when unknown, is set to @code{(const_int -1)}. | |
079a182e | 5070 | |
57e84f18 | 5071 | The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}. |
8c01d9b6 | 5072 | |
40c1d5f8 AS |
5073 | @cindex @code{cmpstrn@var{m}} instruction pattern |
5074 | @item @samp{cmpstrn@var{m}} | |
358b8f01 | 5075 | String compare instruction, with five operands. Operand 0 is the output; |
03dda8e3 | 5076 | it has mode @var{m}. The remaining four operands are like the operands |
70128ad9 | 5077 | of @samp{movmem@var{m}}. The two memory blocks specified are compared |
5cc2f4f3 KG |
5078 | byte by byte in lexicographic order starting at the beginning of each |
5079 | string. The instruction is not allowed to prefetch more than one byte | |
5080 | at a time since either string may end in the first byte and reading past | |
5081 | that may access an invalid page or segment and cause a fault. The | |
9b0f6f5e NC |
5082 | comparison terminates early if the fetched bytes are different or if |
5083 | they are equal to zero. The effect of the instruction is to store a | |
5084 | value in operand 0 whose sign indicates the result of the comparison. | |
03dda8e3 | 5085 | |
40c1d5f8 AS |
5086 | @cindex @code{cmpstr@var{m}} instruction pattern |
5087 | @item @samp{cmpstr@var{m}} | |
5088 | String compare instruction, without known maximum length. Operand 0 is the | |
5089 | output; it has mode @var{m}. The second and third operand are the blocks of | |
5090 | memory to be compared; both are @code{mem:BLK} with an address in mode | |
5091 | @code{Pmode}. | |
5092 | ||
5093 | The fourth operand is the known shared alignment of the source and | |
5094 | destination, in the form of a @code{const_int} rtx. Thus, if the | |
5095 | compiler knows that both source and destination are word-aligned, | |
5096 | it may provide the value 4 for this operand. | |
5097 | ||
5098 | The two memory blocks specified are compared byte by byte in lexicographic | |
5099 | order starting at the beginning of each string. The instruction is not allowed | |
5100 | to prefetch more than one byte at a time since either string may end in the | |
5101 | first byte and reading past that may access an invalid page or segment and | |
9b0f6f5e NC |
5102 | cause a fault. The comparison will terminate when the fetched bytes |
5103 | are different or if they are equal to zero. The effect of the | |
5104 | instruction is to store a value in operand 0 whose sign indicates the | |
5105 | result of the comparison. | |
40c1d5f8 | 5106 | |
358b8f01 JJ |
5107 | @cindex @code{cmpmem@var{m}} instruction pattern |
5108 | @item @samp{cmpmem@var{m}} | |
5109 | Block compare instruction, with five operands like the operands | |
5110 | of @samp{cmpstr@var{m}}. The two memory blocks specified are compared | |
5111 | byte by byte in lexicographic order starting at the beginning of each | |
5112 | block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch | |
9b0f6f5e NC |
5113 | any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}} |
5114 | the comparison will not stop if both bytes are zero. The effect of | |
5115 | the instruction is to store a value in operand 0 whose sign indicates | |
5116 | the result of the comparison. | |
358b8f01 | 5117 | |
03dda8e3 RK |
5118 | @cindex @code{strlen@var{m}} instruction pattern |
5119 | @item @samp{strlen@var{m}} | |
5120 | Compute the length of a string, with three operands. | |
5121 | Operand 0 is the result (of mode @var{m}), operand 1 is | |
5122 | a @code{mem} referring to the first character of the string, | |
5123 | operand 2 is the character to search for (normally zero), | |
5124 | and operand 3 is a constant describing the known alignment | |
5125 | of the beginning of the string. | |
5126 | ||
e0d4c0b3 | 5127 | @cindex @code{float@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
5128 | @item @samp{float@var{m}@var{n}2} |
5129 | Convert signed integer operand 1 (valid for fixed point mode @var{m}) to | |
5130 | floating point mode @var{n} and store in operand 0 (which has mode | |
5131 | @var{n}). | |
5132 | ||
e0d4c0b3 | 5133 | @cindex @code{floatuns@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
5134 | @item @samp{floatuns@var{m}@var{n}2} |
5135 | Convert unsigned integer operand 1 (valid for fixed point mode @var{m}) | |
5136 | to floating point mode @var{n} and store in operand 0 (which has mode | |
5137 | @var{n}). | |
5138 | ||
e0d4c0b3 | 5139 | @cindex @code{fix@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
5140 | @item @samp{fix@var{m}@var{n}2} |
5141 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
5142 | point mode @var{n} as a signed number and store in operand 0 (which | |
5143 | has mode @var{n}). This instruction's result is defined only when | |
5144 | the value of operand 1 is an integer. | |
5145 | ||
0e1d7f32 AH |
5146 | If the machine description defines this pattern, it also needs to |
5147 | define the @code{ftrunc} pattern. | |
5148 | ||
e0d4c0b3 | 5149 | @cindex @code{fixuns@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
5150 | @item @samp{fixuns@var{m}@var{n}2} |
5151 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
5152 | point mode @var{n} as an unsigned number and store in operand 0 (which | |
5153 | has mode @var{n}). This instruction's result is defined only when the | |
5154 | value of operand 1 is an integer. | |
5155 | ||
5156 | @cindex @code{ftrunc@var{m}2} instruction pattern | |
5157 | @item @samp{ftrunc@var{m}2} | |
5158 | Convert operand 1 (valid for floating point mode @var{m}) to an | |
5159 | integer value, still represented in floating point mode @var{m}, and | |
5160 | store it in operand 0 (valid for floating point mode @var{m}). | |
5161 | ||
e0d4c0b3 | 5162 | @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
5163 | @item @samp{fix_trunc@var{m}@var{n}2} |
5164 | Like @samp{fix@var{m}@var{n}2} but works for any floating point value | |
5165 | of mode @var{m} by converting the value to an integer. | |
5166 | ||
e0d4c0b3 | 5167 | @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
5168 | @item @samp{fixuns_trunc@var{m}@var{n}2} |
5169 | Like @samp{fixuns@var{m}@var{n}2} but works for any floating point | |
5170 | value of mode @var{m} by converting the value to an integer. | |
5171 | ||
e0d4c0b3 | 5172 | @cindex @code{trunc@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
5173 | @item @samp{trunc@var{m}@var{n}2} |
5174 | Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and | |
5175 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
5176 | point or both floating point. | |
5177 | ||
e0d4c0b3 | 5178 | @cindex @code{extend@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
5179 | @item @samp{extend@var{m}@var{n}2} |
5180 | Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and | |
5181 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
5182 | point or both floating point. | |
5183 | ||
e0d4c0b3 | 5184 | @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
5185 | @item @samp{zero_extend@var{m}@var{n}2} |
5186 | Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and | |
5187 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
5188 | point. | |
5189 | ||
e0d4c0b3 | 5190 | @cindex @code{fract@var{m}@var{n}2} instruction pattern |
0f996086 CF |
5191 | @item @samp{fract@var{m}@var{n}2} |
5192 | Convert operand 1 of mode @var{m} to mode @var{n} and store in | |
5193 | operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n} | |
5194 | could be fixed-point to fixed-point, signed integer to fixed-point, | |
5195 | fixed-point to signed integer, floating-point to fixed-point, | |
5196 | or fixed-point to floating-point. | |
5197 | When overflows or underflows happen, the results are undefined. | |
5198 | ||
e0d4c0b3 | 5199 | @cindex @code{satfract@var{m}@var{n}2} instruction pattern |
0f996086 CF |
5200 | @item @samp{satfract@var{m}@var{n}2} |
5201 | Convert operand 1 of mode @var{m} to mode @var{n} and store in | |
5202 | operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n} | |
5203 | could be fixed-point to fixed-point, signed integer to fixed-point, | |
5204 | or floating-point to fixed-point. | |
5205 | When overflows or underflows happen, the instruction saturates the | |
5206 | results to the maximum or the minimum. | |
5207 | ||
e0d4c0b3 | 5208 | @cindex @code{fractuns@var{m}@var{n}2} instruction pattern |
0f996086 CF |
5209 | @item @samp{fractuns@var{m}@var{n}2} |
5210 | Convert operand 1 of mode @var{m} to mode @var{n} and store in | |
5211 | operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n} | |
5212 | could be unsigned integer to fixed-point, or | |
5213 | fixed-point to unsigned integer. | |
5214 | When overflows or underflows happen, the results are undefined. | |
5215 | ||
e0d4c0b3 | 5216 | @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern |
0f996086 CF |
5217 | @item @samp{satfractuns@var{m}@var{n}2} |
5218 | Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode | |
5219 | @var{n} and store in operand 0 (which has mode @var{n}). | |
5220 | When overflows or underflows happen, the instruction saturates the | |
5221 | results to the maximum or the minimum. | |
5222 | ||
03dda8e3 RK |
5223 | @cindex @code{extv} instruction pattern |
5224 | @item @samp{extv} | |
c771326b | 5225 | Extract a bit-field from operand 1 (a register or memory operand), where |
03dda8e3 RK |
5226 | operand 2 specifies the width in bits and operand 3 the starting bit, |
5227 | and store it in operand 0. Operand 0 must have mode @code{word_mode}. | |
5228 | Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often | |
5229 | @code{word_mode} is allowed only for registers. Operands 2 and 3 must | |
5230 | be valid for @code{word_mode}. | |
5231 | ||
5232 | The RTL generation pass generates this instruction only with constants | |
3ab997e8 | 5233 | for operands 2 and 3 and the constant is never zero for operand 2. |
03dda8e3 RK |
5234 | |
5235 | The bit-field value is sign-extended to a full word integer | |
5236 | before it is stored in operand 0. | |
5237 | ||
5238 | @cindex @code{extzv} instruction pattern | |
5239 | @item @samp{extzv} | |
5240 | Like @samp{extv} except that the bit-field value is zero-extended. | |
5241 | ||
5242 | @cindex @code{insv} instruction pattern | |
5243 | @item @samp{insv} | |
c771326b JM |
5244 | Store operand 3 (which must be valid for @code{word_mode}) into a |
5245 | bit-field in operand 0, where operand 1 specifies the width in bits and | |
03dda8e3 RK |
5246 | operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or |
5247 | @code{word_mode}; often @code{word_mode} is allowed only for registers. | |
5248 | Operands 1 and 2 must be valid for @code{word_mode}. | |
5249 | ||
5250 | The RTL generation pass generates this instruction only with constants | |
3ab997e8 | 5251 | for operands 1 and 2 and the constant is never zero for operand 1. |
03dda8e3 RK |
5252 | |
5253 | @cindex @code{mov@var{mode}cc} instruction pattern | |
5254 | @item @samp{mov@var{mode}cc} | |
5255 | Conditionally move operand 2 or operand 3 into operand 0 according to the | |
5256 | comparison in operand 1. If the comparison is true, operand 2 is moved | |
5257 | into operand 0, otherwise operand 3 is moved. | |
5258 | ||
5259 | The mode of the operands being compared need not be the same as the operands | |
5260 | being moved. Some machines, sparc64 for example, have instructions that | |
5261 | conditionally move an integer value based on the floating point condition | |
5262 | codes and vice versa. | |
5263 | ||
5264 | If the machine does not have conditional move instructions, do not | |
5265 | define these patterns. | |
5266 | ||
068f5dea | 5267 | @cindex @code{add@var{mode}cc} instruction pattern |
4b5cc2b3 | 5268 | @item @samp{add@var{mode}cc} |
068f5dea JH |
5269 | Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally |
5270 | move operand 2 or (operands 2 + operand 3) into operand 0 according to the | |
5285c21c | 5271 | comparison in operand 1. If the comparison is false, operand 2 is moved into |
4b5cc2b3 | 5272 | operand 0, otherwise (operand 2 + operand 3) is moved. |
068f5dea | 5273 | |
f90b7a5a PB |
5274 | @cindex @code{cstore@var{mode}4} instruction pattern |
5275 | @item @samp{cstore@var{mode}4} | |
5276 | Store zero or nonzero in operand 0 according to whether a comparison | |
5277 | is true. Operand 1 is a comparison operator. Operand 2 and operand 3 | |
5278 | are the first and second operand of the comparison, respectively. | |
5279 | You specify the mode that operand 0 must have when you write the | |
5280 | @code{match_operand} expression. The compiler automatically sees which | |
5281 | mode you have used and supplies an operand of that mode. | |
03dda8e3 RK |
5282 | |
5283 | The value stored for a true condition must have 1 as its low bit, or | |
5284 | else must be negative. Otherwise the instruction is not suitable and | |
5285 | you should omit it from the machine description. You describe to the | |
5286 | compiler exactly which value is stored by defining the macro | |
5287 | @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be | |
ac5eda13 PB |
5288 | found that can be used for all the possible comparison operators, you |
5289 | should pick one and use a @code{define_expand} to map all results | |
5290 | onto the one you chose. | |
5291 | ||
5292 | These operations may @code{FAIL}, but should do so only in relatively | |
5293 | uncommon cases; if they would @code{FAIL} for common cases involving | |
5294 | integer comparisons, it is best to restrict the predicates to not | |
5295 | allow these operands. Likewise if a given comparison operator will | |
5296 | always fail, independent of the operands (for floating-point modes, the | |
5297 | @code{ordered_comparison_operator} predicate is often useful in this case). | |
5298 | ||
5299 | If this pattern is omitted, the compiler will generate a conditional | |
5300 | branch---for example, it may copy a constant one to the target and branching | |
5301 | around an assignment of zero to the target---or a libcall. If the predicate | |
5302 | for operand 1 only rejects some operators, it will also try reordering the | |
5303 | operands and/or inverting the result value (e.g.@: by an exclusive OR). | |
5304 | These possibilities could be cheaper or equivalent to the instructions | |
5305 | used for the @samp{cstore@var{mode}4} pattern followed by those required | |
5306 | to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this | |
5307 | case, you can and should make operand 1's predicate reject some operators | |
5308 | in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether | |
5309 | from the machine description. | |
03dda8e3 | 5310 | |
66c87bae KH |
5311 | @cindex @code{cbranch@var{mode}4} instruction pattern |
5312 | @item @samp{cbranch@var{mode}4} | |
5313 | Conditional branch instruction combined with a compare instruction. | |
5314 | Operand 0 is a comparison operator. Operand 1 and operand 2 are the | |
5315 | first and second operands of the comparison, respectively. Operand 3 | |
5316 | is a @code{label_ref} that refers to the label to jump to. | |
5317 | ||
d26eedb6 HPN |
5318 | @cindex @code{jump} instruction pattern |
5319 | @item @samp{jump} | |
5320 | A jump inside a function; an unconditional branch. Operand 0 is the | |
5321 | @code{label_ref} of the label to jump to. This pattern name is mandatory | |
5322 | on all machines. | |
5323 | ||
03dda8e3 RK |
5324 | @cindex @code{call} instruction pattern |
5325 | @item @samp{call} | |
5326 | Subroutine call instruction returning no value. Operand 0 is the | |
5327 | function to call; operand 1 is the number of bytes of arguments pushed | |
f5963e61 JL |
5328 | as a @code{const_int}; operand 2 is the number of registers used as |
5329 | operands. | |
03dda8e3 RK |
5330 | |
5331 | On most machines, operand 2 is not actually stored into the RTL | |
5332 | pattern. It is supplied for the sake of some RISC machines which need | |
5333 | to put this information into the assembler code; they can put it in | |
5334 | the RTL instead of operand 1. | |
5335 | ||
5336 | Operand 0 should be a @code{mem} RTX whose address is the address of the | |
5337 | function. Note, however, that this address can be a @code{symbol_ref} | |
5338 | expression even if it would not be a legitimate memory address on the | |
5339 | target machine. If it is also not a valid argument for a call | |
5340 | instruction, the pattern for this operation should be a | |
5341 | @code{define_expand} (@pxref{Expander Definitions}) that places the | |
5342 | address into a register and uses that register in the call instruction. | |
5343 | ||
5344 | @cindex @code{call_value} instruction pattern | |
5345 | @item @samp{call_value} | |
5346 | Subroutine call instruction returning a value. Operand 0 is the hard | |
5347 | register in which the value is returned. There are three more | |
5348 | operands, the same as the three operands of the @samp{call} | |
5349 | instruction (but with numbers increased by one). | |
5350 | ||
5351 | Subroutines that return @code{BLKmode} objects use the @samp{call} | |
5352 | insn. | |
5353 | ||
5354 | @cindex @code{call_pop} instruction pattern | |
5355 | @cindex @code{call_value_pop} instruction pattern | |
5356 | @item @samp{call_pop}, @samp{call_value_pop} | |
5357 | Similar to @samp{call} and @samp{call_value}, except used if defined and | |
df2a54e9 | 5358 | if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel} |
03dda8e3 RK |
5359 | that contains both the function call and a @code{set} to indicate the |
5360 | adjustment made to the frame pointer. | |
5361 | ||
df2a54e9 | 5362 | For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these |
03dda8e3 RK |
5363 | patterns increases the number of functions for which the frame pointer |
5364 | can be eliminated, if desired. | |
5365 | ||
5366 | @cindex @code{untyped_call} instruction pattern | |
5367 | @item @samp{untyped_call} | |
5368 | Subroutine call instruction returning a value of any type. Operand 0 is | |
5369 | the function to call; operand 1 is a memory location where the result of | |
5370 | calling the function is to be stored; operand 2 is a @code{parallel} | |
5371 | expression where each element is a @code{set} expression that indicates | |
5372 | the saving of a function return value into the result block. | |
5373 | ||
5374 | This instruction pattern should be defined to support | |
5375 | @code{__builtin_apply} on machines where special instructions are needed | |
5376 | to call a subroutine with arbitrary arguments or to save the value | |
5377 | returned. This instruction pattern is required on machines that have | |
e979f9e8 JM |
5378 | multiple registers that can hold a return value |
5379 | (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register). | |
03dda8e3 RK |
5380 | |
5381 | @cindex @code{return} instruction pattern | |
5382 | @item @samp{return} | |
5383 | Subroutine return instruction. This instruction pattern name should be | |
5384 | defined only if a single instruction can do all the work of returning | |
5385 | from a function. | |
5386 | ||
5387 | Like the @samp{mov@var{m}} patterns, this pattern is also used after the | |
5388 | RTL generation phase. In this case it is to support machines where | |
5389 | multiple instructions are usually needed to return from a function, but | |
5390 | some class of functions only requires one instruction to implement a | |
5391 | return. Normally, the applicable functions are those which do not need | |
5392 | to save any registers or allocate stack space. | |
5393 | ||
26898771 BS |
5394 | It is valid for this pattern to expand to an instruction using |
5395 | @code{simple_return} if no epilogue is required. | |
5396 | ||
5397 | @cindex @code{simple_return} instruction pattern | |
5398 | @item @samp{simple_return} | |
5399 | Subroutine return instruction. This instruction pattern name should be | |
5400 | defined only if a single instruction can do all the work of returning | |
5401 | from a function on a path where no epilogue is required. This pattern | |
5402 | is very similar to the @code{return} instruction pattern, but it is emitted | |
5403 | only by the shrink-wrapping optimization on paths where the function | |
5404 | prologue has not been executed, and a function return should occur without | |
5405 | any of the effects of the epilogue. Additional uses may be introduced on | |
5406 | paths where both the prologue and the epilogue have executed. | |
5407 | ||
03dda8e3 RK |
5408 | @findex reload_completed |
5409 | @findex leaf_function_p | |
5410 | For such machines, the condition specified in this pattern should only | |
df2a54e9 | 5411 | be true when @code{reload_completed} is nonzero and the function's |
03dda8e3 RK |
5412 | epilogue would only be a single instruction. For machines with register |
5413 | windows, the routine @code{leaf_function_p} may be used to determine if | |
5414 | a register window push is required. | |
5415 | ||
5416 | Machines that have conditional return instructions should define patterns | |
5417 | such as | |
5418 | ||
5419 | @smallexample | |
5420 | (define_insn "" | |
5421 | [(set (pc) | |
5422 | (if_then_else (match_operator | |
5423 | 0 "comparison_operator" | |
5424 | [(cc0) (const_int 0)]) | |
5425 | (return) | |
5426 | (pc)))] | |
5427 | "@var{condition}" | |
5428 | "@dots{}") | |
5429 | @end smallexample | |
5430 | ||
5431 | where @var{condition} would normally be the same condition specified on the | |
5432 | named @samp{return} pattern. | |
5433 | ||
5434 | @cindex @code{untyped_return} instruction pattern | |
5435 | @item @samp{untyped_return} | |
5436 | Untyped subroutine return instruction. This instruction pattern should | |
5437 | be defined to support @code{__builtin_return} on machines where special | |
5438 | instructions are needed to return a value of any type. | |
5439 | ||
5440 | Operand 0 is a memory location where the result of calling a function | |
5441 | with @code{__builtin_apply} is stored; operand 1 is a @code{parallel} | |
5442 | expression where each element is a @code{set} expression that indicates | |
5443 | the restoring of a function return value from the result block. | |
5444 | ||
5445 | @cindex @code{nop} instruction pattern | |
5446 | @item @samp{nop} | |
5447 | No-op instruction. This instruction pattern name should always be defined | |
5448 | to output a no-op in assembler code. @code{(const_int 0)} will do as an | |
5449 | RTL pattern. | |
5450 | ||
5451 | @cindex @code{indirect_jump} instruction pattern | |
5452 | @item @samp{indirect_jump} | |
5453 | An instruction to jump to an address which is operand zero. | |
5454 | This pattern name is mandatory on all machines. | |
5455 | ||
5456 | @cindex @code{casesi} instruction pattern | |
5457 | @item @samp{casesi} | |
5458 | Instruction to jump through a dispatch table, including bounds checking. | |
5459 | This instruction takes five operands: | |
5460 | ||
5461 | @enumerate | |
5462 | @item | |
5463 | The index to dispatch on, which has mode @code{SImode}. | |
5464 | ||
5465 | @item | |
5466 | The lower bound for indices in the table, an integer constant. | |
5467 | ||
5468 | @item | |
5469 | The total range of indices in the table---the largest index | |
5470 | minus the smallest one (both inclusive). | |
5471 | ||
5472 | @item | |
5473 | A label that precedes the table itself. | |
5474 | ||
5475 | @item | |
5476 | A label to jump to if the index has a value outside the bounds. | |
03dda8e3 RK |
5477 | @end enumerate |
5478 | ||
e4ae5e77 | 5479 | The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a |
03dda8e3 RK |
5480 | @code{jump_insn}. The number of elements in the table is one plus the |
5481 | difference between the upper bound and the lower bound. | |
5482 | ||
5483 | @cindex @code{tablejump} instruction pattern | |
5484 | @item @samp{tablejump} | |
5485 | Instruction to jump to a variable address. This is a low-level | |
5486 | capability which can be used to implement a dispatch table when there | |
5487 | is no @samp{casesi} pattern. | |
5488 | ||
5489 | This pattern requires two operands: the address or offset, and a label | |
5490 | which should immediately precede the jump table. If the macro | |
f1f5f142 JL |
5491 | @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first |
5492 | operand is an offset which counts from the address of the table; otherwise, | |
5493 | it is an absolute address to jump to. In either case, the first operand has | |
03dda8e3 RK |
5494 | mode @code{Pmode}. |
5495 | ||
5496 | The @samp{tablejump} insn is always the last insn before the jump | |
5497 | table it uses. Its assembler code normally has no need to use the | |
5498 | second operand, but you should incorporate it in the RTL pattern so | |
5499 | that the jump optimizer will not delete the table as unreachable code. | |
5500 | ||
6e4fcc95 MH |
5501 | |
5502 | @cindex @code{decrement_and_branch_until_zero} instruction pattern | |
5503 | @item @samp{decrement_and_branch_until_zero} | |
5504 | Conditional branch instruction that decrements a register and | |
df2a54e9 | 5505 | jumps if the register is nonzero. Operand 0 is the register to |
6e4fcc95 | 5506 | decrement and test; operand 1 is the label to jump to if the |
df2a54e9 | 5507 | register is nonzero. @xref{Looping Patterns}. |
6e4fcc95 MH |
5508 | |
5509 | This optional instruction pattern is only used by the combiner, | |
5510 | typically for loops reversed by the loop optimizer when strength | |
5511 | reduction is enabled. | |
5512 | ||
5513 | @cindex @code{doloop_end} instruction pattern | |
5514 | @item @samp{doloop_end} | |
5515 | Conditional branch instruction that decrements a register and jumps if | |
df2a54e9 | 5516 | the register is nonzero. This instruction takes five operands: Operand |
6e4fcc95 MH |
5517 | 0 is the register to decrement and test; operand 1 is the number of loop |
5518 | iterations as a @code{const_int} or @code{const0_rtx} if this cannot be | |
5519 | determined until run-time; operand 2 is the actual or estimated maximum | |
5520 | number of iterations as a @code{const_int}; operand 3 is the number of | |
5521 | enclosed loops as a @code{const_int} (an innermost loop has a value of | |
2407343c JR |
5522 | 1); operand 4 is the label to jump to if the register is nonzero; |
5523 | operand 5 is const1_rtx if the loop in entered at its top, const0_rtx | |
5524 | otherwise. | |
5c25e11d | 5525 | @xref{Looping Patterns}. |
6e4fcc95 MH |
5526 | |
5527 | This optional instruction pattern should be defined for machines with | |
5528 | low-overhead looping instructions as the loop optimizer will try to | |
5529 | modify suitable loops to utilize it. If nested low-overhead looping is | |
5530 | not supported, use a @code{define_expand} (@pxref{Expander Definitions}) | |
5531 | and make the pattern fail if operand 3 is not @code{const1_rtx}. | |
5532 | Similarly, if the actual or estimated maximum number of iterations is | |
5533 | too large for this instruction, make it fail. | |
5534 | ||
5535 | @cindex @code{doloop_begin} instruction pattern | |
5536 | @item @samp{doloop_begin} | |
5537 | Companion instruction to @code{doloop_end} required for machines that | |
c21cd8b1 JM |
5538 | need to perform some initialization, such as loading special registers |
5539 | used by a low-overhead looping instruction. If initialization insns do | |
6e4fcc95 MH |
5540 | not always need to be emitted, use a @code{define_expand} |
5541 | (@pxref{Expander Definitions}) and make it fail. | |
5542 | ||
5543 | ||
03dda8e3 RK |
5544 | @cindex @code{canonicalize_funcptr_for_compare} instruction pattern |
5545 | @item @samp{canonicalize_funcptr_for_compare} | |
5546 | Canonicalize the function pointer in operand 1 and store the result | |
5547 | into operand 0. | |
5548 | ||
5549 | Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1 | |
5550 | may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc | |
5551 | and also has mode @code{Pmode}. | |
5552 | ||
5553 | Canonicalization of a function pointer usually involves computing | |
5554 | the address of the function which would be called if the function | |
5555 | pointer were used in an indirect call. | |
5556 | ||
5557 | Only define this pattern if function pointers on the target machine | |
5558 | can have different values but still call the same function when | |
5559 | used in an indirect call. | |
5560 | ||
5561 | @cindex @code{save_stack_block} instruction pattern | |
5562 | @cindex @code{save_stack_function} instruction pattern | |
5563 | @cindex @code{save_stack_nonlocal} instruction pattern | |
5564 | @cindex @code{restore_stack_block} instruction pattern | |
5565 | @cindex @code{restore_stack_function} instruction pattern | |
5566 | @cindex @code{restore_stack_nonlocal} instruction pattern | |
5567 | @item @samp{save_stack_block} | |
5568 | @itemx @samp{save_stack_function} | |
5569 | @itemx @samp{save_stack_nonlocal} | |
5570 | @itemx @samp{restore_stack_block} | |
5571 | @itemx @samp{restore_stack_function} | |
5572 | @itemx @samp{restore_stack_nonlocal} | |
5573 | Most machines save and restore the stack pointer by copying it to or | |
5574 | from an object of mode @code{Pmode}. Do not define these patterns on | |
5575 | such machines. | |
5576 | ||
5577 | Some machines require special handling for stack pointer saves and | |
5578 | restores. On those machines, define the patterns corresponding to the | |
5579 | non-standard cases by using a @code{define_expand} (@pxref{Expander | |
5580 | Definitions}) that produces the required insns. The three types of | |
5581 | saves and restores are: | |
5582 | ||
5583 | @enumerate | |
5584 | @item | |
5585 | @samp{save_stack_block} saves the stack pointer at the start of a block | |
5586 | that allocates a variable-sized object, and @samp{restore_stack_block} | |
5587 | restores the stack pointer when the block is exited. | |
5588 | ||
5589 | @item | |
5590 | @samp{save_stack_function} and @samp{restore_stack_function} do a | |
5591 | similar job for the outermost block of a function and are used when the | |
5592 | function allocates variable-sized objects or calls @code{alloca}. Only | |
5593 | the epilogue uses the restored stack pointer, allowing a simpler save or | |
5594 | restore sequence on some machines. | |
5595 | ||
5596 | @item | |
5597 | @samp{save_stack_nonlocal} is used in functions that contain labels | |
5598 | branched to by nested functions. It saves the stack pointer in such a | |
5599 | way that the inner function can use @samp{restore_stack_nonlocal} to | |
5600 | restore the stack pointer. The compiler generates code to restore the | |
5601 | frame and argument pointer registers, but some machines require saving | |
5602 | and restoring additional data such as register window information or | |
5603 | stack backchains. Place insns in these patterns to save and restore any | |
5604 | such required data. | |
5605 | @end enumerate | |
5606 | ||
5607 | When saving the stack pointer, operand 0 is the save area and operand 1 | |
73c8090f DE |
5608 | is the stack pointer. The mode used to allocate the save area defaults |
5609 | to @code{Pmode} but you can override that choice by defining the | |
7e390c9d | 5610 | @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must |
73c8090f DE |
5611 | specify an integral mode, or @code{VOIDmode} if no save area is needed |
5612 | for a particular type of save (either because no save is needed or | |
5613 | because a machine-specific save area can be used). Operand 0 is the | |
5614 | stack pointer and operand 1 is the save area for restore operations. If | |
5615 | @samp{save_stack_block} is defined, operand 0 must not be | |
5616 | @code{VOIDmode} since these saves can be arbitrarily nested. | |
03dda8e3 RK |
5617 | |
5618 | A save area is a @code{mem} that is at a constant offset from | |
5619 | @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by | |
5620 | nonlocal gotos and a @code{reg} in the other two cases. | |
5621 | ||
5622 | @cindex @code{allocate_stack} instruction pattern | |
5623 | @item @samp{allocate_stack} | |
72938a4c | 5624 | Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from |
03dda8e3 RK |
5625 | the stack pointer to create space for dynamically allocated data. |
5626 | ||
72938a4c MM |
5627 | Store the resultant pointer to this space into operand 0. If you |
5628 | are allocating space from the main stack, do this by emitting a | |
5629 | move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0. | |
5630 | If you are allocating the space elsewhere, generate code to copy the | |
5631 | location of the space to operand 0. In the latter case, you must | |
956d6950 | 5632 | ensure this space gets freed when the corresponding space on the main |
72938a4c MM |
5633 | stack is free. |
5634 | ||
03dda8e3 RK |
5635 | Do not define this pattern if all that must be done is the subtraction. |
5636 | Some machines require other operations such as stack probes or | |
5637 | maintaining the back chain. Define this pattern to emit those | |
5638 | operations in addition to updating the stack pointer. | |
5639 | ||
861bb6c1 JL |
5640 | @cindex @code{check_stack} instruction pattern |
5641 | @item @samp{check_stack} | |
507d0069 EB |
5642 | If stack checking (@pxref{Stack Checking}) cannot be done on your system by |
5643 | probing the stack, define this pattern to perform the needed check and signal | |
5644 | an error if the stack has overflowed. The single operand is the address in | |
5645 | the stack farthest from the current stack pointer that you need to validate. | |
5646 | Normally, on platforms where this pattern is needed, you would obtain the | |
5647 | stack limit from a global or thread-specific variable or register. | |
d809253a | 5648 | |
7b84aac0 EB |
5649 | @cindex @code{probe_stack_address} instruction pattern |
5650 | @item @samp{probe_stack_address} | |
5651 | If stack checking (@pxref{Stack Checking}) can be done on your system by | |
5652 | probing the stack but without the need to actually access it, define this | |
5653 | pattern and signal an error if the stack has overflowed. The single operand | |
5654 | is the memory address in the stack that needs to be probed. | |
5655 | ||
d809253a EB |
5656 | @cindex @code{probe_stack} instruction pattern |
5657 | @item @samp{probe_stack} | |
507d0069 EB |
5658 | If stack checking (@pxref{Stack Checking}) can be done on your system by |
5659 | probing the stack but doing it with a ``store zero'' instruction is not valid | |
5660 | or optimal, define this pattern to do the probing differently and signal an | |
5661 | error if the stack has overflowed. The single operand is the memory reference | |
5662 | in the stack that needs to be probed. | |
861bb6c1 | 5663 | |
03dda8e3 RK |
5664 | @cindex @code{nonlocal_goto} instruction pattern |
5665 | @item @samp{nonlocal_goto} | |
5666 | Emit code to generate a non-local goto, e.g., a jump from one function | |
5667 | to a label in an outer function. This pattern has four arguments, | |
5668 | each representing a value to be used in the jump. The first | |
45bb86fd | 5669 | argument is to be loaded into the frame pointer, the second is |
03dda8e3 RK |
5670 | the address to branch to (code to dispatch to the actual label), |
5671 | the third is the address of a location where the stack is saved, | |
5672 | and the last is the address of the label, to be placed in the | |
5673 | location for the incoming static chain. | |
5674 | ||
f0523f02 | 5675 | On most machines you need not define this pattern, since GCC will |
03dda8e3 RK |
5676 | already generate the correct code, which is to load the frame pointer |
5677 | and static chain, restore the stack (using the | |
5678 | @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly | |
5679 | to the dispatcher. You need only define this pattern if this code will | |
5680 | not work on your machine. | |
5681 | ||
5682 | @cindex @code{nonlocal_goto_receiver} instruction pattern | |
5683 | @item @samp{nonlocal_goto_receiver} | |
5684 | This pattern, if defined, contains code needed at the target of a | |
161d7b59 | 5685 | nonlocal goto after the code already generated by GCC@. You will not |
03dda8e3 RK |
5686 | normally need to define this pattern. A typical reason why you might |
5687 | need this pattern is if some value, such as a pointer to a global table, | |
c30ddbc9 | 5688 | must be restored when the frame pointer is restored. Note that a nonlocal |
89bcce1b | 5689 | goto only occurs within a unit-of-translation, so a global table pointer |
c30ddbc9 RH |
5690 | that is shared by all functions of a given module need not be restored. |
5691 | There are no arguments. | |
861bb6c1 JL |
5692 | |
5693 | @cindex @code{exception_receiver} instruction pattern | |
5694 | @item @samp{exception_receiver} | |
5695 | This pattern, if defined, contains code needed at the site of an | |
5696 | exception handler that isn't needed at the site of a nonlocal goto. You | |
5697 | will not normally need to define this pattern. A typical reason why you | |
5698 | might need this pattern is if some value, such as a pointer to a global | |
5699 | table, must be restored after control flow is branched to the handler of | |
5700 | an exception. There are no arguments. | |
c85f7c16 | 5701 | |
c30ddbc9 RH |
5702 | @cindex @code{builtin_setjmp_setup} instruction pattern |
5703 | @item @samp{builtin_setjmp_setup} | |
5704 | This pattern, if defined, contains additional code needed to initialize | |
5705 | the @code{jmp_buf}. You will not normally need to define this pattern. | |
5706 | A typical reason why you might need this pattern is if some value, such | |
5707 | as a pointer to a global table, must be restored. Though it is | |
5708 | preferred that the pointer value be recalculated if possible (given the | |
5709 | address of a label for instance). The single argument is a pointer to | |
5710 | the @code{jmp_buf}. Note that the buffer is five words long and that | |
5711 | the first three are normally used by the generic mechanism. | |
5712 | ||
c85f7c16 JL |
5713 | @cindex @code{builtin_setjmp_receiver} instruction pattern |
5714 | @item @samp{builtin_setjmp_receiver} | |
e4ae5e77 | 5715 | This pattern, if defined, contains code needed at the site of a |
c771326b | 5716 | built-in setjmp that isn't needed at the site of a nonlocal goto. You |
c85f7c16 JL |
5717 | will not normally need to define this pattern. A typical reason why you |
5718 | might need this pattern is if some value, such as a pointer to a global | |
c30ddbc9 | 5719 | table, must be restored. It takes one argument, which is the label |
073a8998 | 5720 | to which builtin_longjmp transferred control; this pattern may be emitted |
c30ddbc9 RH |
5721 | at a small offset from that label. |
5722 | ||
5723 | @cindex @code{builtin_longjmp} instruction pattern | |
5724 | @item @samp{builtin_longjmp} | |
5725 | This pattern, if defined, performs the entire action of the longjmp. | |
5726 | You will not normally need to define this pattern unless you also define | |
5727 | @code{builtin_setjmp_setup}. The single argument is a pointer to the | |
5728 | @code{jmp_buf}. | |
f69864aa | 5729 | |
52a11cbf RH |
5730 | @cindex @code{eh_return} instruction pattern |
5731 | @item @samp{eh_return} | |
f69864aa | 5732 | This pattern, if defined, affects the way @code{__builtin_eh_return}, |
52a11cbf RH |
5733 | and thence the call frame exception handling library routines, are |
5734 | built. It is intended to handle non-trivial actions needed along | |
5735 | the abnormal return path. | |
5736 | ||
34dc173c | 5737 | The address of the exception handler to which the function should return |
daf2f129 | 5738 | is passed as operand to this pattern. It will normally need to copied by |
34dc173c UW |
5739 | the pattern to some special register or memory location. |
5740 | If the pattern needs to determine the location of the target call | |
5741 | frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX}, | |
5742 | if defined; it will have already been assigned. | |
5743 | ||
5744 | If this pattern is not defined, the default action will be to simply | |
5745 | copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either | |
5746 | that macro or this pattern needs to be defined if call frame exception | |
5747 | handling is to be used. | |
0b433de6 JL |
5748 | |
5749 | @cindex @code{prologue} instruction pattern | |
17b53c33 | 5750 | @anchor{prologue instruction pattern} |
0b433de6 JL |
5751 | @item @samp{prologue} |
5752 | This pattern, if defined, emits RTL for entry to a function. The function | |
b192711e | 5753 | entry is responsible for setting up the stack frame, initializing the frame |
0b433de6 JL |
5754 | pointer register, saving callee saved registers, etc. |
5755 | ||
5756 | Using a prologue pattern is generally preferred over defining | |
17b53c33 | 5757 | @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue. |
0b433de6 JL |
5758 | |
5759 | The @code{prologue} pattern is particularly useful for targets which perform | |
5760 | instruction scheduling. | |
5761 | ||
12c5ffe5 EB |
5762 | @cindex @code{window_save} instruction pattern |
5763 | @anchor{window_save instruction pattern} | |
5764 | @item @samp{window_save} | |
5765 | This pattern, if defined, emits RTL for a register window save. It should | |
5766 | be defined if the target machine has register windows but the window events | |
5767 | are decoupled from calls to subroutines. The canonical example is the SPARC | |
5768 | architecture. | |
5769 | ||
0b433de6 | 5770 | @cindex @code{epilogue} instruction pattern |
17b53c33 | 5771 | @anchor{epilogue instruction pattern} |
0b433de6 | 5772 | @item @samp{epilogue} |
396ad517 | 5773 | This pattern emits RTL for exit from a function. The function |
b192711e | 5774 | exit is responsible for deallocating the stack frame, restoring callee saved |
0b433de6 JL |
5775 | registers and emitting the return instruction. |
5776 | ||
5777 | Using an epilogue pattern is generally preferred over defining | |
17b53c33 | 5778 | @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue. |
0b433de6 JL |
5779 | |
5780 | The @code{epilogue} pattern is particularly useful for targets which perform | |
5781 | instruction scheduling or which have delay slots for their return instruction. | |
5782 | ||
5783 | @cindex @code{sibcall_epilogue} instruction pattern | |
5784 | @item @samp{sibcall_epilogue} | |
5785 | This pattern, if defined, emits RTL for exit from a function without the final | |
5786 | branch back to the calling function. This pattern will be emitted before any | |
5787 | sibling call (aka tail call) sites. | |
5788 | ||
5789 | The @code{sibcall_epilogue} pattern must not clobber any arguments used for | |
5790 | parameter passing or any stack slots for arguments passed to the current | |
ebb48a4d | 5791 | function. |
a157febd GK |
5792 | |
5793 | @cindex @code{trap} instruction pattern | |
5794 | @item @samp{trap} | |
5795 | This pattern, if defined, signals an error, typically by causing some | |
5796 | kind of signal to be raised. Among other places, it is used by the Java | |
c771326b | 5797 | front end to signal `invalid array index' exceptions. |
a157febd | 5798 | |
f90b7a5a PB |
5799 | @cindex @code{ctrap@var{MM}4} instruction pattern |
5800 | @item @samp{ctrap@var{MM}4} | |
a157febd | 5801 | Conditional trap instruction. Operand 0 is a piece of RTL which |
f90b7a5a PB |
5802 | performs a comparison, and operands 1 and 2 are the arms of the |
5803 | comparison. Operand 3 is the trap code, an integer. | |
a157febd | 5804 | |
f90b7a5a | 5805 | A typical @code{ctrap} pattern looks like |
a157febd GK |
5806 | |
5807 | @smallexample | |
f90b7a5a | 5808 | (define_insn "ctrapsi4" |
ebb48a4d | 5809 | [(trap_if (match_operator 0 "trap_operator" |
f90b7a5a | 5810 | [(match_operand 1 "register_operand") |
73b8bfe1 | 5811 | (match_operand 2 "immediate_operand")]) |
f90b7a5a | 5812 | (match_operand 3 "const_int_operand" "i"))] |
a157febd GK |
5813 | "" |
5814 | "@dots{}") | |
5815 | @end smallexample | |
5816 | ||
e83d297b JJ |
5817 | @cindex @code{prefetch} instruction pattern |
5818 | @item @samp{prefetch} | |
5819 | ||
5820 | This pattern, if defined, emits code for a non-faulting data prefetch | |
5821 | instruction. Operand 0 is the address of the memory to prefetch. Operand 1 | |
5822 | is a constant 1 if the prefetch is preparing for a write to the memory | |
5823 | address, or a constant 0 otherwise. Operand 2 is the expected degree of | |
5824 | temporal locality of the data and is a value between 0 and 3, inclusive; 0 | |
5825 | means that the data has no temporal locality, so it need not be left in the | |
5826 | cache after the access; 3 means that the data has a high degree of temporal | |
5827 | locality and should be left in all levels of cache possible; 1 and 2 mean, | |
5828 | respectively, a low or moderate degree of temporal locality. | |
5829 | ||
5830 | Targets that do not support write prefetches or locality hints can ignore | |
5831 | the values of operands 1 and 2. | |
5832 | ||
b6bd3371 DE |
5833 | @cindex @code{blockage} instruction pattern |
5834 | @item @samp{blockage} | |
5835 | ||
5836 | This pattern defines a pseudo insn that prevents the instruction | |
5837 | scheduler from moving instructions across the boundary defined by the | |
5838 | blockage insn. Normally an UNSPEC_VOLATILE pattern. | |
5839 | ||
48ae6c13 RH |
5840 | @cindex @code{memory_barrier} instruction pattern |
5841 | @item @samp{memory_barrier} | |
5842 | ||
5843 | If the target memory model is not fully synchronous, then this pattern | |
5844 | should be defined to an instruction that orders both loads and stores | |
5845 | before the instruction with respect to loads and stores after the instruction. | |
5846 | This pattern has no operands. | |
5847 | ||
5848 | @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern | |
5849 | @item @samp{sync_compare_and_swap@var{mode}} | |
5850 | ||
5851 | This pattern, if defined, emits code for an atomic compare-and-swap | |
5852 | operation. Operand 1 is the memory on which the atomic operation is | |
5853 | performed. Operand 2 is the ``old'' value to be compared against the | |
5854 | current contents of the memory location. Operand 3 is the ``new'' value | |
5855 | to store in the memory if the compare succeeds. Operand 0 is the result | |
915167f5 GK |
5856 | of the operation; it should contain the contents of the memory |
5857 | before the operation. If the compare succeeds, this should obviously be | |
5858 | a copy of operand 2. | |
48ae6c13 RH |
5859 | |
5860 | This pattern must show that both operand 0 and operand 1 are modified. | |
5861 | ||
915167f5 GK |
5862 | This pattern must issue any memory barrier instructions such that all |
5863 | memory operations before the atomic operation occur before the atomic | |
5864 | operation and all memory operations after the atomic operation occur | |
5865 | after the atomic operation. | |
48ae6c13 | 5866 | |
4a77c72b | 5867 | For targets where the success or failure of the compare-and-swap |
f90b7a5a PB |
5868 | operation is available via the status flags, it is possible to |
5869 | avoid a separate compare operation and issue the subsequent | |
5870 | branch or store-flag operation immediately after the compare-and-swap. | |
5871 | To this end, GCC will look for a @code{MODE_CC} set in the | |
5872 | output of @code{sync_compare_and_swap@var{mode}}; if the machine | |
5873 | description includes such a set, the target should also define special | |
5874 | @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then | |
5875 | be able to take the destination of the @code{MODE_CC} set and pass it | |
5876 | to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first | |
5877 | operand of the comparison (the second will be @code{(const_int 0)}). | |
48ae6c13 | 5878 | |
cedb4a1a RH |
5879 | For targets where the operating system may provide support for this |
5880 | operation via library calls, the @code{sync_compare_and_swap_optab} | |
5881 | may be initialized to a function with the same interface as the | |
5882 | @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire | |
5883 | set of @var{__sync} builtins are supported via library calls, the | |
5884 | target can initialize all of the optabs at once with | |
5885 | @code{init_sync_libfuncs}. | |
5886 | For the purposes of C++11 @code{std::atomic::is_lock_free}, it is | |
5887 | assumed that these library calls do @emph{not} use any kind of | |
5888 | interruptable locking. | |
5889 | ||
48ae6c13 RH |
5890 | @cindex @code{sync_add@var{mode}} instruction pattern |
5891 | @cindex @code{sync_sub@var{mode}} instruction pattern | |
5892 | @cindex @code{sync_ior@var{mode}} instruction pattern | |
5893 | @cindex @code{sync_and@var{mode}} instruction pattern | |
5894 | @cindex @code{sync_xor@var{mode}} instruction pattern | |
5895 | @cindex @code{sync_nand@var{mode}} instruction pattern | |
5896 | @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}} | |
5897 | @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}} | |
5898 | @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}} | |
5899 | ||
5900 | These patterns emit code for an atomic operation on memory. | |
5901 | Operand 0 is the memory on which the atomic operation is performed. | |
5902 | Operand 1 is the second operand to the binary operator. | |
5903 | ||
915167f5 GK |
5904 | This pattern must issue any memory barrier instructions such that all |
5905 | memory operations before the atomic operation occur before the atomic | |
5906 | operation and all memory operations after the atomic operation occur | |
5907 | after the atomic operation. | |
48ae6c13 RH |
5908 | |
5909 | If these patterns are not defined, the operation will be constructed | |
5910 | from a compare-and-swap operation, if defined. | |
5911 | ||
5912 | @cindex @code{sync_old_add@var{mode}} instruction pattern | |
5913 | @cindex @code{sync_old_sub@var{mode}} instruction pattern | |
5914 | @cindex @code{sync_old_ior@var{mode}} instruction pattern | |
5915 | @cindex @code{sync_old_and@var{mode}} instruction pattern | |
5916 | @cindex @code{sync_old_xor@var{mode}} instruction pattern | |
5917 | @cindex @code{sync_old_nand@var{mode}} instruction pattern | |
5918 | @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}} | |
5919 | @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}} | |
5920 | @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}} | |
5921 | ||
c29c1030 | 5922 | These patterns emit code for an atomic operation on memory, |
48ae6c13 RH |
5923 | and return the value that the memory contained before the operation. |
5924 | Operand 0 is the result value, operand 1 is the memory on which the | |
5925 | atomic operation is performed, and operand 2 is the second operand | |
5926 | to the binary operator. | |
5927 | ||
915167f5 GK |
5928 | This pattern must issue any memory barrier instructions such that all |
5929 | memory operations before the atomic operation occur before the atomic | |
5930 | operation and all memory operations after the atomic operation occur | |
5931 | after the atomic operation. | |
48ae6c13 RH |
5932 | |
5933 | If these patterns are not defined, the operation will be constructed | |
5934 | from a compare-and-swap operation, if defined. | |
5935 | ||
5936 | @cindex @code{sync_new_add@var{mode}} instruction pattern | |
5937 | @cindex @code{sync_new_sub@var{mode}} instruction pattern | |
5938 | @cindex @code{sync_new_ior@var{mode}} instruction pattern | |
5939 | @cindex @code{sync_new_and@var{mode}} instruction pattern | |
5940 | @cindex @code{sync_new_xor@var{mode}} instruction pattern | |
5941 | @cindex @code{sync_new_nand@var{mode}} instruction pattern | |
5942 | @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}} | |
5943 | @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}} | |
5944 | @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}} | |
5945 | ||
5946 | These patterns are like their @code{sync_old_@var{op}} counterparts, | |
5947 | except that they return the value that exists in the memory location | |
5948 | after the operation, rather than before the operation. | |
5949 | ||
5950 | @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern | |
5951 | @item @samp{sync_lock_test_and_set@var{mode}} | |
5952 | ||
5953 | This pattern takes two forms, based on the capabilities of the target. | |
5954 | In either case, operand 0 is the result of the operand, operand 1 is | |
5955 | the memory on which the atomic operation is performed, and operand 2 | |
5956 | is the value to set in the lock. | |
5957 | ||
5958 | In the ideal case, this operation is an atomic exchange operation, in | |
5959 | which the previous value in memory operand is copied into the result | |
5960 | operand, and the value operand is stored in the memory operand. | |
5961 | ||
5962 | For less capable targets, any value operand that is not the constant 1 | |
5963 | should be rejected with @code{FAIL}. In this case the target may use | |
5964 | an atomic test-and-set bit operation. The result operand should contain | |
5965 | 1 if the bit was previously set and 0 if the bit was previously clear. | |
5966 | The true contents of the memory operand are implementation defined. | |
5967 | ||
5968 | This pattern must issue any memory barrier instructions such that the | |
915167f5 GK |
5969 | pattern as a whole acts as an acquire barrier, that is all memory |
5970 | operations after the pattern do not occur until the lock is acquired. | |
48ae6c13 RH |
5971 | |
5972 | If this pattern is not defined, the operation will be constructed from | |
5973 | a compare-and-swap operation, if defined. | |
5974 | ||
5975 | @cindex @code{sync_lock_release@var{mode}} instruction pattern | |
5976 | @item @samp{sync_lock_release@var{mode}} | |
5977 | ||
5978 | This pattern, if defined, releases a lock set by | |
5979 | @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory | |
8635a919 GK |
5980 | that contains the lock; operand 1 is the value to store in the lock. |
5981 | ||
5982 | If the target doesn't implement full semantics for | |
5983 | @code{sync_lock_test_and_set@var{mode}}, any value operand which is not | |
5984 | the constant 0 should be rejected with @code{FAIL}, and the true contents | |
5985 | of the memory operand are implementation defined. | |
48ae6c13 RH |
5986 | |
5987 | This pattern must issue any memory barrier instructions such that the | |
915167f5 GK |
5988 | pattern as a whole acts as a release barrier, that is the lock is |
5989 | released only after all previous memory operations have completed. | |
48ae6c13 RH |
5990 | |
5991 | If this pattern is not defined, then a @code{memory_barrier} pattern | |
8635a919 | 5992 | will be emitted, followed by a store of the value to the memory operand. |
48ae6c13 | 5993 | |
86951993 AM |
5994 | @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern |
5995 | @item @samp{atomic_compare_and_swap@var{mode}} | |
5996 | This pattern, if defined, emits code for an atomic compare-and-swap | |
5997 | operation with memory model semantics. Operand 2 is the memory on which | |
5998 | the atomic operation is performed. Operand 0 is an output operand which | |
5999 | is set to true or false based on whether the operation succeeded. Operand | |
6000 | 1 is an output operand which is set to the contents of the memory before | |
6001 | the operation was attempted. Operand 3 is the value that is expected to | |
6002 | be in memory. Operand 4 is the value to put in memory if the expected | |
6003 | value is found there. Operand 5 is set to 1 if this compare and swap is to | |
6004 | be treated as a weak operation. Operand 6 is the memory model to be used | |
6005 | if the operation is a success. Operand 7 is the memory model to be used | |
6006 | if the operation fails. | |
6007 | ||
6008 | If memory referred to in operand 2 contains the value in operand 3, then | |
6009 | operand 4 is stored in memory pointed to by operand 2 and fencing based on | |
6010 | the memory model in operand 6 is issued. | |
6011 | ||
6012 | If memory referred to in operand 2 does not contain the value in operand 3, | |
6013 | then fencing based on the memory model in operand 7 is issued. | |
6014 | ||
6015 | If a target does not support weak compare-and-swap operations, or the port | |
6016 | elects not to implement weak operations, the argument in operand 5 can be | |
6017 | ignored. Note a strong implementation must be provided. | |
6018 | ||
6019 | If this pattern is not provided, the @code{__atomic_compare_exchange} | |
6020 | built-in functions will utilize the legacy @code{sync_compare_and_swap} | |
6021 | pattern with an @code{__ATOMIC_SEQ_CST} memory model. | |
6022 | ||
6023 | @cindex @code{atomic_load@var{mode}} instruction pattern | |
6024 | @item @samp{atomic_load@var{mode}} | |
6025 | This pattern implements an atomic load operation with memory model | |
6026 | semantics. Operand 1 is the memory address being loaded from. Operand 0 | |
6027 | is the result of the load. Operand 2 is the memory model to be used for | |
6028 | the load operation. | |
6029 | ||
6030 | If not present, the @code{__atomic_load} built-in function will either | |
6031 | resort to a normal load with memory barriers, or a compare-and-swap | |
6032 | operation if a normal load would not be atomic. | |
6033 | ||
6034 | @cindex @code{atomic_store@var{mode}} instruction pattern | |
6035 | @item @samp{atomic_store@var{mode}} | |
6036 | This pattern implements an atomic store operation with memory model | |
6037 | semantics. Operand 0 is the memory address being stored to. Operand 1 | |
6038 | is the value to be written. Operand 2 is the memory model to be used for | |
6039 | the operation. | |
6040 | ||
6041 | If not present, the @code{__atomic_store} built-in function will attempt to | |
6042 | perform a normal store and surround it with any required memory fences. If | |
6043 | the store would not be atomic, then an @code{__atomic_exchange} is | |
6044 | attempted with the result being ignored. | |
6045 | ||
6046 | @cindex @code{atomic_exchange@var{mode}} instruction pattern | |
6047 | @item @samp{atomic_exchange@var{mode}} | |
6048 | This pattern implements an atomic exchange operation with memory model | |
6049 | semantics. Operand 1 is the memory location the operation is performed on. | |
6050 | Operand 0 is an output operand which is set to the original value contained | |
6051 | in the memory pointed to by operand 1. Operand 2 is the value to be | |
6052 | stored. Operand 3 is the memory model to be used. | |
6053 | ||
6054 | If this pattern is not present, the built-in function | |
6055 | @code{__atomic_exchange} will attempt to preform the operation with a | |
6056 | compare and swap loop. | |
6057 | ||
6058 | @cindex @code{atomic_add@var{mode}} instruction pattern | |
6059 | @cindex @code{atomic_sub@var{mode}} instruction pattern | |
6060 | @cindex @code{atomic_or@var{mode}} instruction pattern | |
6061 | @cindex @code{atomic_and@var{mode}} instruction pattern | |
6062 | @cindex @code{atomic_xor@var{mode}} instruction pattern | |
6063 | @cindex @code{atomic_nand@var{mode}} instruction pattern | |
6064 | @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}} | |
6065 | @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}} | |
6066 | @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}} | |
6067 | ||
6068 | These patterns emit code for an atomic operation on memory with memory | |
6069 | model semantics. Operand 0 is the memory on which the atomic operation is | |
6070 | performed. Operand 1 is the second operand to the binary operator. | |
6071 | Operand 2 is the memory model to be used by the operation. | |
6072 | ||
6073 | If these patterns are not defined, attempts will be made to use legacy | |
c29c1030 | 6074 | @code{sync} patterns, or equivalent patterns which return a result. If |
86951993 AM |
6075 | none of these are available a compare-and-swap loop will be used. |
6076 | ||
6077 | @cindex @code{atomic_fetch_add@var{mode}} instruction pattern | |
6078 | @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern | |
6079 | @cindex @code{atomic_fetch_or@var{mode}} instruction pattern | |
6080 | @cindex @code{atomic_fetch_and@var{mode}} instruction pattern | |
6081 | @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern | |
6082 | @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern | |
6083 | @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}} | |
6084 | @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}} | |
6085 | @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}} | |
6086 | ||
6087 | These patterns emit code for an atomic operation on memory with memory | |
6088 | model semantics, and return the original value. Operand 0 is an output | |
6089 | operand which contains the value of the memory location before the | |
6090 | operation was performed. Operand 1 is the memory on which the atomic | |
6091 | operation is performed. Operand 2 is the second operand to the binary | |
6092 | operator. Operand 3 is the memory model to be used by the operation. | |
6093 | ||
6094 | If these patterns are not defined, attempts will be made to use legacy | |
6095 | @code{sync} patterns. If none of these are available a compare-and-swap | |
6096 | loop will be used. | |
6097 | ||
6098 | @cindex @code{atomic_add_fetch@var{mode}} instruction pattern | |
6099 | @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern | |
6100 | @cindex @code{atomic_or_fetch@var{mode}} instruction pattern | |
6101 | @cindex @code{atomic_and_fetch@var{mode}} instruction pattern | |
6102 | @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern | |
6103 | @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern | |
6104 | @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}} | |
6105 | @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}} | |
6106 | @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}} | |
6107 | ||
6108 | These patterns emit code for an atomic operation on memory with memory | |
6109 | model semantics and return the result after the operation is performed. | |
6110 | Operand 0 is an output operand which contains the value after the | |
6111 | operation. Operand 1 is the memory on which the atomic operation is | |
6112 | performed. Operand 2 is the second operand to the binary operator. | |
6113 | Operand 3 is the memory model to be used by the operation. | |
6114 | ||
6115 | If these patterns are not defined, attempts will be made to use legacy | |
c29c1030 | 6116 | @code{sync} patterns, or equivalent patterns which return the result before |
86951993 AM |
6117 | the operation followed by the arithmetic operation required to produce the |
6118 | result. If none of these are available a compare-and-swap loop will be | |
6119 | used. | |
6120 | ||
f8a27aa6 RH |
6121 | @cindex @code{atomic_test_and_set} instruction pattern |
6122 | @item @samp{atomic_test_and_set} | |
6123 | ||
6124 | This pattern emits code for @code{__builtin_atomic_test_and_set}. | |
6125 | Operand 0 is an output operand which is set to true if the previous | |
6126 | previous contents of the byte was "set", and false otherwise. Operand 1 | |
6127 | is the @code{QImode} memory to be modified. Operand 2 is the memory | |
6128 | model to be used. | |
6129 | ||
6130 | The specific value that defines "set" is implementation defined, and | |
6131 | is normally based on what is performed by the native atomic test and set | |
6132 | instruction. | |
6133 | ||
86951993 AM |
6134 | @cindex @code{mem_thread_fence@var{mode}} instruction pattern |
6135 | @item @samp{mem_thread_fence@var{mode}} | |
6136 | This pattern emits code required to implement a thread fence with | |
6137 | memory model semantics. Operand 0 is the memory model to be used. | |
6138 | ||
6139 | If this pattern is not specified, all memory models except | |
6140 | @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize} | |
6141 | barrier pattern. | |
6142 | ||
6143 | @cindex @code{mem_signal_fence@var{mode}} instruction pattern | |
6144 | @item @samp{mem_signal_fence@var{mode}} | |
6145 | This pattern emits code required to implement a signal fence with | |
6146 | memory model semantics. Operand 0 is the memory model to be used. | |
6147 | ||
6148 | This pattern should impact the compiler optimizers the same way that | |
6149 | mem_signal_fence does, but it does not need to issue any barrier | |
6150 | instructions. | |
6151 | ||
6152 | If this pattern is not specified, all memory models except | |
6153 | @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize} | |
6154 | barrier pattern. | |
6155 | ||
f959607b CLT |
6156 | @cindex @code{get_thread_pointer@var{mode}} instruction pattern |
6157 | @cindex @code{set_thread_pointer@var{mode}} instruction pattern | |
6158 | @item @samp{get_thread_pointer@var{mode}} | |
6159 | @itemx @samp{set_thread_pointer@var{mode}} | |
6160 | These patterns emit code that reads/sets the TLS thread pointer. Currently, | |
6161 | these are only needed if the target needs to support the | |
6162 | @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer} | |
6163 | builtins. | |
6164 | ||
6165 | The get/set patterns have a single output/input operand respectively, | |
6166 | with @var{mode} intended to be @code{Pmode}. | |
6167 | ||
7d69de61 RH |
6168 | @cindex @code{stack_protect_set} instruction pattern |
6169 | @item @samp{stack_protect_set} | |
6170 | ||
643e867f | 6171 | This pattern, if defined, moves a @code{ptr_mode} value from the memory |
7d69de61 RH |
6172 | in operand 1 to the memory in operand 0 without leaving the value in |
6173 | a register afterward. This is to avoid leaking the value some place | |
759915ca | 6174 | that an attacker might use to rewrite the stack guard slot after |
7d69de61 RH |
6175 | having clobbered it. |
6176 | ||
6177 | If this pattern is not defined, then a plain move pattern is generated. | |
6178 | ||
6179 | @cindex @code{stack_protect_test} instruction pattern | |
6180 | @item @samp{stack_protect_test} | |
6181 | ||
643e867f | 6182 | This pattern, if defined, compares a @code{ptr_mode} value from the |
7d69de61 | 6183 | memory in operand 1 with the memory in operand 0 without leaving the |
3aebbe5f | 6184 | value in a register afterward and branches to operand 2 if the values |
e9d3ef3b | 6185 | were equal. |
7d69de61 | 6186 | |
3aebbe5f JJ |
6187 | If this pattern is not defined, then a plain compare pattern and |
6188 | conditional branch pattern is used. | |
7d69de61 | 6189 | |
677feb77 DD |
6190 | @cindex @code{clear_cache} instruction pattern |
6191 | @item @samp{clear_cache} | |
6192 | ||
6193 | This pattern, if defined, flushes the instruction cache for a region of | |
6194 | memory. The region is bounded to by the Pmode pointers in operand 0 | |
6195 | inclusive and operand 1 exclusive. | |
6196 | ||
6197 | If this pattern is not defined, a call to the library function | |
6198 | @code{__clear_cache} is used. | |
6199 | ||
03dda8e3 RK |
6200 | @end table |
6201 | ||
a5249a21 HPN |
6202 | @end ifset |
6203 | @c Each of the following nodes are wrapped in separate | |
6204 | @c "@ifset INTERNALS" to work around memory limits for the default | |
6205 | @c configuration in older tetex distributions. Known to not work: | |
6206 | @c tetex-1.0.7, known to work: tetex-2.0.2. | |
6207 | @ifset INTERNALS | |
03dda8e3 RK |
6208 | @node Pattern Ordering |
6209 | @section When the Order of Patterns Matters | |
6210 | @cindex Pattern Ordering | |
6211 | @cindex Ordering of Patterns | |
6212 | ||
6213 | Sometimes an insn can match more than one instruction pattern. Then the | |
6214 | pattern that appears first in the machine description is the one used. | |
6215 | Therefore, more specific patterns (patterns that will match fewer things) | |
6216 | and faster instructions (those that will produce better code when they | |
6217 | do match) should usually go first in the description. | |
6218 | ||
6219 | In some cases the effect of ordering the patterns can be used to hide | |
6220 | a pattern when it is not valid. For example, the 68000 has an | |
6221 | instruction for converting a fullword to floating point and another | |
6222 | for converting a byte to floating point. An instruction converting | |
6223 | an integer to floating point could match either one. We put the | |
6224 | pattern to convert the fullword first to make sure that one will | |
6225 | be used rather than the other. (Otherwise a large integer might | |
6226 | be generated as a single-byte immediate quantity, which would not work.) | |
6227 | Instead of using this pattern ordering it would be possible to make the | |
6228 | pattern for convert-a-byte smart enough to deal properly with any | |
6229 | constant value. | |
6230 | ||
a5249a21 HPN |
6231 | @end ifset |
6232 | @ifset INTERNALS | |
03dda8e3 RK |
6233 | @node Dependent Patterns |
6234 | @section Interdependence of Patterns | |
6235 | @cindex Dependent Patterns | |
6236 | @cindex Interdependence of Patterns | |
6237 | ||
03dda8e3 RK |
6238 | In some cases machines support instructions identical except for the |
6239 | machine mode of one or more operands. For example, there may be | |
6240 | ``sign-extend halfword'' and ``sign-extend byte'' instructions whose | |
6241 | patterns are | |
6242 | ||
3ab51846 | 6243 | @smallexample |
03dda8e3 RK |
6244 | (set (match_operand:SI 0 @dots{}) |
6245 | (extend:SI (match_operand:HI 1 @dots{}))) | |
6246 | ||
6247 | (set (match_operand:SI 0 @dots{}) | |
6248 | (extend:SI (match_operand:QI 1 @dots{}))) | |
3ab51846 | 6249 | @end smallexample |
03dda8e3 RK |
6250 | |
6251 | @noindent | |
6252 | Constant integers do not specify a machine mode, so an instruction to | |
6253 | extend a constant value could match either pattern. The pattern it | |
6254 | actually will match is the one that appears first in the file. For correct | |
6255 | results, this must be the one for the widest possible mode (@code{HImode}, | |
6256 | here). If the pattern matches the @code{QImode} instruction, the results | |
6257 | will be incorrect if the constant value does not actually fit that mode. | |
6258 | ||
6259 | Such instructions to extend constants are rarely generated because they are | |
6260 | optimized away, but they do occasionally happen in nonoptimized | |
6261 | compilations. | |
6262 | ||
6263 | If a constraint in a pattern allows a constant, the reload pass may | |
6264 | replace a register with a constant permitted by the constraint in some | |
6265 | cases. Similarly for memory references. Because of this substitution, | |
6266 | you should not provide separate patterns for increment and decrement | |
6267 | instructions. Instead, they should be generated from the same pattern | |
6268 | that supports register-register add insns by examining the operands and | |
6269 | generating the appropriate machine instruction. | |
6270 | ||
a5249a21 HPN |
6271 | @end ifset |
6272 | @ifset INTERNALS | |
03dda8e3 RK |
6273 | @node Jump Patterns |
6274 | @section Defining Jump Instruction Patterns | |
6275 | @cindex jump instruction patterns | |
6276 | @cindex defining jump instruction patterns | |
6277 | ||
f90b7a5a PB |
6278 | GCC does not assume anything about how the machine realizes jumps. |
6279 | The machine description should define a single pattern, usually | |
6280 | a @code{define_expand}, which expands to all the required insns. | |
6281 | ||
6282 | Usually, this would be a comparison insn to set the condition code | |
6283 | and a separate branch insn testing the condition code and branching | |
6284 | or not according to its value. For many machines, however, | |
6285 | separating compares and branches is limiting, which is why the | |
6286 | more flexible approach with one @code{define_expand} is used in GCC. | |
6287 | The machine description becomes clearer for architectures that | |
6288 | have compare-and-branch instructions but no condition code. It also | |
6289 | works better when different sets of comparison operators are supported | |
6290 | by different kinds of conditional branches (e.g. integer vs. floating-point), | |
6291 | or by conditional branches with respect to conditional stores. | |
6292 | ||
6293 | Two separate insns are always used if the machine description represents | |
6294 | a condition code register using the legacy RTL expression @code{(cc0)}, | |
6295 | and on most machines that use a separate condition code register | |
6296 | (@pxref{Condition Code}). For machines that use @code{(cc0)}, in | |
6297 | fact, the set and use of the condition code must be separate and | |
6298 | adjacent@footnote{@code{note} insns can separate them, though.}, thus | |
6299 | allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and | |
6300 | so that the comparison and branch insns could be located from each other | |
6301 | by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}. | |
6302 | ||
6303 | Even in this case having a single entry point for conditional branches | |
6304 | is advantageous, because it handles equally well the case where a single | |
6305 | comparison instruction records the results of both signed and unsigned | |
6306 | comparison of the given operands (with the branch insns coming in distinct | |
6307 | signed and unsigned flavors) as in the x86 or SPARC, and the case where | |
6308 | there are distinct signed and unsigned compare instructions and only | |
6309 | one set of conditional branch instructions as in the PowerPC. | |
03dda8e3 | 6310 | |
a5249a21 HPN |
6311 | @end ifset |
6312 | @ifset INTERNALS | |
6e4fcc95 MH |
6313 | @node Looping Patterns |
6314 | @section Defining Looping Instruction Patterns | |
6315 | @cindex looping instruction patterns | |
6316 | @cindex defining looping instruction patterns | |
6317 | ||
05713b80 | 6318 | Some machines have special jump instructions that can be utilized to |
6e4fcc95 MH |
6319 | make loops more efficient. A common example is the 68000 @samp{dbra} |
6320 | instruction which performs a decrement of a register and a branch if the | |
6321 | result was greater than zero. Other machines, in particular digital | |
6322 | signal processors (DSPs), have special block repeat instructions to | |
6323 | provide low-overhead loop support. For example, the TI TMS320C3x/C4x | |
6324 | DSPs have a block repeat instruction that loads special registers to | |
6325 | mark the top and end of a loop and to count the number of loop | |
6326 | iterations. This avoids the need for fetching and executing a | |
c771326b | 6327 | @samp{dbra}-like instruction and avoids pipeline stalls associated with |
6e4fcc95 MH |
6328 | the jump. |
6329 | ||
9c34dbbf ZW |
6330 | GCC has three special named patterns to support low overhead looping. |
6331 | They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin}, | |
6332 | and @samp{doloop_end}. The first pattern, | |
6e4fcc95 MH |
6333 | @samp{decrement_and_branch_until_zero}, is not emitted during RTL |
6334 | generation but may be emitted during the instruction combination phase. | |
6335 | This requires the assistance of the loop optimizer, using information | |
6336 | collected during strength reduction, to reverse a loop to count down to | |
6337 | zero. Some targets also require the loop optimizer to add a | |
6338 | @code{REG_NONNEG} note to indicate that the iteration count is always | |
6339 | positive. This is needed if the target performs a signed loop | |
6340 | termination test. For example, the 68000 uses a pattern similar to the | |
6341 | following for its @code{dbra} instruction: | |
6342 | ||
6343 | @smallexample | |
6344 | @group | |
6345 | (define_insn "decrement_and_branch_until_zero" | |
6346 | [(set (pc) | |
6ccde948 RW |
6347 | (if_then_else |
6348 | (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am") | |
6349 | (const_int -1)) | |
6350 | (const_int 0)) | |
6351 | (label_ref (match_operand 1 "" "")) | |
6352 | (pc))) | |
6e4fcc95 | 6353 | (set (match_dup 0) |
6ccde948 RW |
6354 | (plus:SI (match_dup 0) |
6355 | (const_int -1)))] | |
6e4fcc95 | 6356 | "find_reg_note (insn, REG_NONNEG, 0)" |
630d3d5a | 6357 | "@dots{}") |
6e4fcc95 MH |
6358 | @end group |
6359 | @end smallexample | |
6360 | ||
6361 | Note that since the insn is both a jump insn and has an output, it must | |
6362 | deal with its own reloads, hence the `m' constraints. Also note that | |
6363 | since this insn is generated by the instruction combination phase | |
6364 | combining two sequential insns together into an implicit parallel insn, | |
6365 | the iteration counter needs to be biased by the same amount as the | |
630d3d5a | 6366 | decrement operation, in this case @minus{}1. Note that the following similar |
6e4fcc95 MH |
6367 | pattern will not be matched by the combiner. |
6368 | ||
6369 | @smallexample | |
6370 | @group | |
6371 | (define_insn "decrement_and_branch_until_zero" | |
6372 | [(set (pc) | |
6ccde948 RW |
6373 | (if_then_else |
6374 | (ge (match_operand:SI 0 "general_operand" "+d*am") | |
6375 | (const_int 1)) | |
6376 | (label_ref (match_operand 1 "" "")) | |
6377 | (pc))) | |
6e4fcc95 | 6378 | (set (match_dup 0) |
6ccde948 RW |
6379 | (plus:SI (match_dup 0) |
6380 | (const_int -1)))] | |
6e4fcc95 | 6381 | "find_reg_note (insn, REG_NONNEG, 0)" |
630d3d5a | 6382 | "@dots{}") |
6e4fcc95 MH |
6383 | @end group |
6384 | @end smallexample | |
6385 | ||
6386 | The other two special looping patterns, @samp{doloop_begin} and | |
c21cd8b1 | 6387 | @samp{doloop_end}, are emitted by the loop optimizer for certain |
6e4fcc95 | 6388 | well-behaved loops with a finite number of loop iterations using |
ebb48a4d | 6389 | information collected during strength reduction. |
6e4fcc95 MH |
6390 | |
6391 | The @samp{doloop_end} pattern describes the actual looping instruction | |
6392 | (or the implicit looping operation) and the @samp{doloop_begin} pattern | |
c21cd8b1 | 6393 | is an optional companion pattern that can be used for initialization |
6e4fcc95 MH |
6394 | needed for some low-overhead looping instructions. |
6395 | ||
6396 | Note that some machines require the actual looping instruction to be | |
6397 | emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting | |
6398 | the true RTL for a looping instruction at the top of the loop can cause | |
6399 | problems with flow analysis. So instead, a dummy @code{doloop} insn is | |
6400 | emitted at the end of the loop. The machine dependent reorg pass checks | |
6401 | for the presence of this @code{doloop} insn and then searches back to | |
6402 | the top of the loop, where it inserts the true looping insn (provided | |
6403 | there are no instructions in the loop which would cause problems). Any | |
6404 | additional labels can be emitted at this point. In addition, if the | |
6405 | desired special iteration counter register was not allocated, this | |
6406 | machine dependent reorg pass could emit a traditional compare and jump | |
6407 | instruction pair. | |
6408 | ||
6409 | The essential difference between the | |
6410 | @samp{decrement_and_branch_until_zero} and the @samp{doloop_end} | |
6411 | patterns is that the loop optimizer allocates an additional pseudo | |
6412 | register for the latter as an iteration counter. This pseudo register | |
6413 | cannot be used within the loop (i.e., general induction variables cannot | |
6414 | be derived from it), however, in many cases the loop induction variable | |
6415 | may become redundant and removed by the flow pass. | |
6416 | ||
6417 | ||
a5249a21 HPN |
6418 | @end ifset |
6419 | @ifset INTERNALS | |
03dda8e3 RK |
6420 | @node Insn Canonicalizations |
6421 | @section Canonicalization of Instructions | |
6422 | @cindex canonicalization of instructions | |
6423 | @cindex insn canonicalization | |
6424 | ||
6425 | There are often cases where multiple RTL expressions could represent an | |
6426 | operation performed by a single machine instruction. This situation is | |
6427 | most commonly encountered with logical, branch, and multiply-accumulate | |
6428 | instructions. In such cases, the compiler attempts to convert these | |
6429 | multiple RTL expressions into a single canonical form to reduce the | |
6430 | number of insn patterns required. | |
6431 | ||
6432 | In addition to algebraic simplifications, following canonicalizations | |
6433 | are performed: | |
6434 | ||
6435 | @itemize @bullet | |
6436 | @item | |
6437 | For commutative and comparison operators, a constant is always made the | |
6438 | second operand. If a machine only supports a constant as the second | |
6439 | operand, only patterns that match a constant in the second operand need | |
6440 | be supplied. | |
6441 | ||
e3d6e740 GK |
6442 | @item |
6443 | For associative operators, a sequence of operators will always chain | |
6444 | to the left; for instance, only the left operand of an integer @code{plus} | |
6445 | can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor}, | |
6446 | @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and | |
6447 | @code{umax} are associative when applied to integers, and sometimes to | |
6448 | floating-point. | |
6449 | ||
6450 | @item | |
03dda8e3 RK |
6451 | @cindex @code{neg}, canonicalization of |
6452 | @cindex @code{not}, canonicalization of | |
6453 | @cindex @code{mult}, canonicalization of | |
6454 | @cindex @code{plus}, canonicalization of | |
6455 | @cindex @code{minus}, canonicalization of | |
6456 | For these operators, if only one operand is a @code{neg}, @code{not}, | |
6457 | @code{mult}, @code{plus}, or @code{minus} expression, it will be the | |
6458 | first operand. | |
6459 | ||
16823694 GK |
6460 | @item |
6461 | In combinations of @code{neg}, @code{mult}, @code{plus}, and | |
6462 | @code{minus}, the @code{neg} operations (if any) will be moved inside | |
daf2f129 | 6463 | the operations as far as possible. For instance, |
16823694 | 6464 | @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but |
9302a061 | 6465 | @code{(plus (mult (neg B) C) A)} is canonicalized as |
16823694 GK |
6466 | @code{(minus A (mult B C))}. |
6467 | ||
03dda8e3 RK |
6468 | @cindex @code{compare}, canonicalization of |
6469 | @item | |
6470 | For the @code{compare} operator, a constant is always the second operand | |
f90b7a5a | 6471 | if the first argument is a condition code register or @code{(cc0)}. |
03dda8e3 | 6472 | |
f90b7a5a | 6473 | @item |
03dda8e3 RK |
6474 | An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or |
6475 | @code{minus} is made the first operand under the same conditions as | |
6476 | above. | |
6477 | ||
921c4418 RIL |
6478 | @item |
6479 | @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to | |
6480 | @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead | |
6481 | of @code{ltu}. | |
6482 | ||
03dda8e3 RK |
6483 | @item |
6484 | @code{(minus @var{x} (const_int @var{n}))} is converted to | |
6485 | @code{(plus @var{x} (const_int @var{-n}))}. | |
6486 | ||
6487 | @item | |
6488 | Within address computations (i.e., inside @code{mem}), a left shift is | |
6489 | converted into the appropriate multiplication by a power of two. | |
6490 | ||
6491 | @cindex @code{ior}, canonicalization of | |
6492 | @cindex @code{and}, canonicalization of | |
6493 | @cindex De Morgan's law | |
72938a4c | 6494 | @item |
090359d6 | 6495 | De Morgan's Law is used to move bitwise negation inside a bitwise |
03dda8e3 RK |
6496 | logical-and or logical-or operation. If this results in only one |
6497 | operand being a @code{not} expression, it will be the first one. | |
6498 | ||
6499 | A machine that has an instruction that performs a bitwise logical-and of one | |
6500 | operand with the bitwise negation of the other should specify the pattern | |
6501 | for that instruction as | |
6502 | ||
3ab51846 | 6503 | @smallexample |
03dda8e3 RK |
6504 | (define_insn "" |
6505 | [(set (match_operand:@var{m} 0 @dots{}) | |
6506 | (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) | |
6507 | (match_operand:@var{m} 2 @dots{})))] | |
6508 | "@dots{}" | |
6509 | "@dots{}") | |
3ab51846 | 6510 | @end smallexample |
03dda8e3 RK |
6511 | |
6512 | @noindent | |
6513 | Similarly, a pattern for a ``NAND'' instruction should be written | |
6514 | ||
3ab51846 | 6515 | @smallexample |
03dda8e3 RK |
6516 | (define_insn "" |
6517 | [(set (match_operand:@var{m} 0 @dots{}) | |
6518 | (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) | |
6519 | (not:@var{m} (match_operand:@var{m} 2 @dots{}))))] | |
6520 | "@dots{}" | |
6521 | "@dots{}") | |
3ab51846 | 6522 | @end smallexample |
03dda8e3 RK |
6523 | |
6524 | In both cases, it is not necessary to include patterns for the many | |
6525 | logically equivalent RTL expressions. | |
6526 | ||
6527 | @cindex @code{xor}, canonicalization of | |
6528 | @item | |
6529 | The only possible RTL expressions involving both bitwise exclusive-or | |
6530 | and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})} | |
bd819a4a | 6531 | and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}. |
03dda8e3 RK |
6532 | |
6533 | @item | |
6534 | The sum of three items, one of which is a constant, will only appear in | |
6535 | the form | |
6536 | ||
3ab51846 | 6537 | @smallexample |
03dda8e3 | 6538 | (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant}) |
3ab51846 | 6539 | @end smallexample |
03dda8e3 | 6540 | |
03dda8e3 RK |
6541 | @cindex @code{zero_extract}, canonicalization of |
6542 | @cindex @code{sign_extract}, canonicalization of | |
6543 | @item | |
6544 | Equality comparisons of a group of bits (usually a single bit) with zero | |
6545 | will be written using @code{zero_extract} rather than the equivalent | |
6546 | @code{and} or @code{sign_extract} operations. | |
6547 | ||
c536876e AS |
6548 | @cindex @code{mult}, canonicalization of |
6549 | @item | |
6550 | @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x}) | |
6551 | (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1} | |
6552 | (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise | |
6553 | for @code{zero_extend}. | |
6554 | ||
6555 | @item | |
6556 | @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2} | |
6557 | @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted | |
6558 | to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2} | |
6559 | @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for | |
6560 | patterns using @code{zero_extend} and @code{lshiftrt}. If the second | |
6561 | operand of @code{mult} is also a shift, then that is extended also. | |
6562 | This transformation is only applied when it can be proven that the | |
6563 | original operation had sufficient precision to prevent overflow. | |
6564 | ||
03dda8e3 RK |
6565 | @end itemize |
6566 | ||
cd16503a HPN |
6567 | Further canonicalization rules are defined in the function |
6568 | @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}. | |
6569 | ||
a5249a21 HPN |
6570 | @end ifset |
6571 | @ifset INTERNALS | |
03dda8e3 RK |
6572 | @node Expander Definitions |
6573 | @section Defining RTL Sequences for Code Generation | |
6574 | @cindex expander definitions | |
6575 | @cindex code generation RTL sequences | |
6576 | @cindex defining RTL sequences for code generation | |
6577 | ||
6578 | On some target machines, some standard pattern names for RTL generation | |
6579 | cannot be handled with single insn, but a sequence of RTL insns can | |
6580 | represent them. For these target machines, you can write a | |
161d7b59 | 6581 | @code{define_expand} to specify how to generate the sequence of RTL@. |
03dda8e3 RK |
6582 | |
6583 | @findex define_expand | |
6584 | A @code{define_expand} is an RTL expression that looks almost like a | |
6585 | @code{define_insn}; but, unlike the latter, a @code{define_expand} is used | |
6586 | only for RTL generation and it can produce more than one RTL insn. | |
6587 | ||
6588 | A @code{define_expand} RTX has four operands: | |
6589 | ||
6590 | @itemize @bullet | |
6591 | @item | |
6592 | The name. Each @code{define_expand} must have a name, since the only | |
6593 | use for it is to refer to it by name. | |
6594 | ||
03dda8e3 | 6595 | @item |
f3a3d0d3 RH |
6596 | The RTL template. This is a vector of RTL expressions representing |
6597 | a sequence of separate instructions. Unlike @code{define_insn}, there | |
6598 | is no implicit surrounding @code{PARALLEL}. | |
03dda8e3 RK |
6599 | |
6600 | @item | |
6601 | The condition, a string containing a C expression. This expression is | |
6602 | used to express how the availability of this pattern depends on | |
f0523f02 JM |
6603 | subclasses of target machine, selected by command-line options when GCC |
6604 | is run. This is just like the condition of a @code{define_insn} that | |
03dda8e3 RK |
6605 | has a standard name. Therefore, the condition (if present) may not |
6606 | depend on the data in the insn being matched, but only the | |
6607 | target-machine-type flags. The compiler needs to test these conditions | |
6608 | during initialization in order to learn exactly which named instructions | |
6609 | are available in a particular run. | |
6610 | ||
6611 | @item | |
6612 | The preparation statements, a string containing zero or more C | |
6613 | statements which are to be executed before RTL code is generated from | |
6614 | the RTL template. | |
6615 | ||
6616 | Usually these statements prepare temporary registers for use as | |
6617 | internal operands in the RTL template, but they can also generate RTL | |
6618 | insns directly by calling routines such as @code{emit_insn}, etc. | |
6619 | Any such insns precede the ones that come from the RTL template. | |
6620 | @end itemize | |
6621 | ||
6622 | Every RTL insn emitted by a @code{define_expand} must match some | |
6623 | @code{define_insn} in the machine description. Otherwise, the compiler | |
6624 | will crash when trying to generate code for the insn or trying to optimize | |
6625 | it. | |
6626 | ||
6627 | The RTL template, in addition to controlling generation of RTL insns, | |
6628 | also describes the operands that need to be specified when this pattern | |
6629 | is used. In particular, it gives a predicate for each operand. | |
6630 | ||
6631 | A true operand, which needs to be specified in order to generate RTL from | |
6632 | the pattern, should be described with a @code{match_operand} in its first | |
6633 | occurrence in the RTL template. This enters information on the operand's | |
f0523f02 | 6634 | predicate into the tables that record such things. GCC uses the |
03dda8e3 RK |
6635 | information to preload the operand into a register if that is required for |
6636 | valid RTL code. If the operand is referred to more than once, subsequent | |
6637 | references should use @code{match_dup}. | |
6638 | ||
6639 | The RTL template may also refer to internal ``operands'' which are | |
6640 | temporary registers or labels used only within the sequence made by the | |
6641 | @code{define_expand}. Internal operands are substituted into the RTL | |
6642 | template with @code{match_dup}, never with @code{match_operand}. The | |
6643 | values of the internal operands are not passed in as arguments by the | |
6644 | compiler when it requests use of this pattern. Instead, they are computed | |
6645 | within the pattern, in the preparation statements. These statements | |
6646 | compute the values and store them into the appropriate elements of | |
6647 | @code{operands} so that @code{match_dup} can find them. | |
6648 | ||
6649 | There are two special macros defined for use in the preparation statements: | |
6650 | @code{DONE} and @code{FAIL}. Use them with a following semicolon, | |
6651 | as a statement. | |
6652 | ||
6653 | @table @code | |
6654 | ||
6655 | @findex DONE | |
6656 | @item DONE | |
6657 | Use the @code{DONE} macro to end RTL generation for the pattern. The | |
6658 | only RTL insns resulting from the pattern on this occasion will be | |
6659 | those already emitted by explicit calls to @code{emit_insn} within the | |
6660 | preparation statements; the RTL template will not be generated. | |
6661 | ||
6662 | @findex FAIL | |
6663 | @item FAIL | |
6664 | Make the pattern fail on this occasion. When a pattern fails, it means | |
6665 | that the pattern was not truly available. The calling routines in the | |
6666 | compiler will try other strategies for code generation using other patterns. | |
6667 | ||
6668 | Failure is currently supported only for binary (addition, multiplication, | |
c771326b | 6669 | shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv}) |
03dda8e3 RK |
6670 | operations. |
6671 | @end table | |
6672 | ||
55e4756f DD |
6673 | If the preparation falls through (invokes neither @code{DONE} nor |
6674 | @code{FAIL}), then the @code{define_expand} acts like a | |
6675 | @code{define_insn} in that the RTL template is used to generate the | |
6676 | insn. | |
6677 | ||
6678 | The RTL template is not used for matching, only for generating the | |
6679 | initial insn list. If the preparation statement always invokes | |
6680 | @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple | |
6681 | list of operands, such as this example: | |
6682 | ||
6683 | @smallexample | |
6684 | @group | |
6685 | (define_expand "addsi3" | |
6686 | [(match_operand:SI 0 "register_operand" "") | |
6687 | (match_operand:SI 1 "register_operand" "") | |
6688 | (match_operand:SI 2 "register_operand" "")] | |
6689 | @end group | |
6690 | @group | |
6691 | "" | |
6692 | " | |
58097133 | 6693 | @{ |
55e4756f DD |
6694 | handle_add (operands[0], operands[1], operands[2]); |
6695 | DONE; | |
58097133 | 6696 | @}") |
55e4756f DD |
6697 | @end group |
6698 | @end smallexample | |
6699 | ||
03dda8e3 RK |
6700 | Here is an example, the definition of left-shift for the SPUR chip: |
6701 | ||
6702 | @smallexample | |
6703 | @group | |
6704 | (define_expand "ashlsi3" | |
6705 | [(set (match_operand:SI 0 "register_operand" "") | |
6706 | (ashift:SI | |
6707 | @end group | |
6708 | @group | |
6709 | (match_operand:SI 1 "register_operand" "") | |
6710 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
6711 | "" | |
6712 | " | |
6713 | @end group | |
6714 | @end smallexample | |
6715 | ||
6716 | @smallexample | |
6717 | @group | |
6718 | @{ | |
6719 | if (GET_CODE (operands[2]) != CONST_INT | |
6720 | || (unsigned) INTVAL (operands[2]) > 3) | |
6721 | FAIL; | |
6722 | @}") | |
6723 | @end group | |
6724 | @end smallexample | |
6725 | ||
6726 | @noindent | |
6727 | This example uses @code{define_expand} so that it can generate an RTL insn | |
6728 | for shifting when the shift-count is in the supported range of 0 to 3 but | |
6729 | fail in other cases where machine insns aren't available. When it fails, | |
6730 | the compiler tries another strategy using different patterns (such as, a | |
6731 | library call). | |
6732 | ||
6733 | If the compiler were able to handle nontrivial condition-strings in | |
6734 | patterns with names, then it would be possible to use a | |
6735 | @code{define_insn} in that case. Here is another case (zero-extension | |
6736 | on the 68000) which makes more use of the power of @code{define_expand}: | |
6737 | ||
6738 | @smallexample | |
6739 | (define_expand "zero_extendhisi2" | |
6740 | [(set (match_operand:SI 0 "general_operand" "") | |
6741 | (const_int 0)) | |
6742 | (set (strict_low_part | |
6743 | (subreg:HI | |
6744 | (match_dup 0) | |
6745 | 0)) | |
6746 | (match_operand:HI 1 "general_operand" ""))] | |
6747 | "" | |
6748 | "operands[1] = make_safe_from (operands[1], operands[0]);") | |
6749 | @end smallexample | |
6750 | ||
6751 | @noindent | |
6752 | @findex make_safe_from | |
6753 | Here two RTL insns are generated, one to clear the entire output operand | |
6754 | and the other to copy the input operand into its low half. This sequence | |
6755 | is incorrect if the input operand refers to [the old value of] the output | |
6756 | operand, so the preparation statement makes sure this isn't so. The | |
6757 | function @code{make_safe_from} copies the @code{operands[1]} into a | |
6758 | temporary register if it refers to @code{operands[0]}. It does this | |
6759 | by emitting another RTL insn. | |
6760 | ||
6761 | Finally, a third example shows the use of an internal operand. | |
6762 | Zero-extension on the SPUR chip is done by @code{and}-ing the result | |
6763 | against a halfword mask. But this mask cannot be represented by a | |
6764 | @code{const_int} because the constant value is too large to be legitimate | |
6765 | on this machine. So it must be copied into a register with | |
6766 | @code{force_reg} and then the register used in the @code{and}. | |
6767 | ||
6768 | @smallexample | |
6769 | (define_expand "zero_extendhisi2" | |
6770 | [(set (match_operand:SI 0 "register_operand" "") | |
6771 | (and:SI (subreg:SI | |
6772 | (match_operand:HI 1 "register_operand" "") | |
6773 | 0) | |
6774 | (match_dup 2)))] | |
6775 | "" | |
6776 | "operands[2] | |
3a598fbe | 6777 | = force_reg (SImode, GEN_INT (65535)); ") |
03dda8e3 RK |
6778 | @end smallexample |
6779 | ||
f4559287 | 6780 | @emph{Note:} If the @code{define_expand} is used to serve a |
c771326b | 6781 | standard binary or unary arithmetic operation or a bit-field operation, |
03dda8e3 RK |
6782 | then the last insn it generates must not be a @code{code_label}, |
6783 | @code{barrier} or @code{note}. It must be an @code{insn}, | |
6784 | @code{jump_insn} or @code{call_insn}. If you don't need a real insn | |
6785 | at the end, emit an insn to copy the result of the operation into | |
6786 | itself. Such an insn will generate no code, but it can avoid problems | |
bd819a4a | 6787 | in the compiler. |
03dda8e3 | 6788 | |
a5249a21 HPN |
6789 | @end ifset |
6790 | @ifset INTERNALS | |
03dda8e3 RK |
6791 | @node Insn Splitting |
6792 | @section Defining How to Split Instructions | |
6793 | @cindex insn splitting | |
6794 | @cindex instruction splitting | |
6795 | @cindex splitting instructions | |
6796 | ||
fae15c93 VM |
6797 | There are two cases where you should specify how to split a pattern |
6798 | into multiple insns. On machines that have instructions requiring | |
6799 | delay slots (@pxref{Delay Slots}) or that have instructions whose | |
6800 | output is not available for multiple cycles (@pxref{Processor pipeline | |
6801 | description}), the compiler phases that optimize these cases need to | |
6802 | be able to move insns into one-instruction delay slots. However, some | |
6803 | insns may generate more than one machine instruction. These insns | |
6804 | cannot be placed into a delay slot. | |
03dda8e3 RK |
6805 | |
6806 | Often you can rewrite the single insn as a list of individual insns, | |
6807 | each corresponding to one machine instruction. The disadvantage of | |
6808 | doing so is that it will cause the compilation to be slower and require | |
6809 | more space. If the resulting insns are too complex, it may also | |
6810 | suppress some optimizations. The compiler splits the insn if there is a | |
6811 | reason to believe that it might improve instruction or delay slot | |
6812 | scheduling. | |
6813 | ||
6814 | The insn combiner phase also splits putative insns. If three insns are | |
6815 | merged into one insn with a complex expression that cannot be matched by | |
6816 | some @code{define_insn} pattern, the combiner phase attempts to split | |
6817 | the complex pattern into two insns that are recognized. Usually it can | |
6818 | break the complex pattern into two patterns by splitting out some | |
6819 | subexpression. However, in some other cases, such as performing an | |
6820 | addition of a large constant in two insns on a RISC machine, the way to | |
6821 | split the addition into two insns is machine-dependent. | |
6822 | ||
f3a3d0d3 | 6823 | @findex define_split |
03dda8e3 RK |
6824 | The @code{define_split} definition tells the compiler how to split a |
6825 | complex insn into several simpler insns. It looks like this: | |
6826 | ||
6827 | @smallexample | |
6828 | (define_split | |
6829 | [@var{insn-pattern}] | |
6830 | "@var{condition}" | |
6831 | [@var{new-insn-pattern-1} | |
6832 | @var{new-insn-pattern-2} | |
6833 | @dots{}] | |
630d3d5a | 6834 | "@var{preparation-statements}") |
03dda8e3 RK |
6835 | @end smallexample |
6836 | ||
6837 | @var{insn-pattern} is a pattern that needs to be split and | |
6838 | @var{condition} is the final condition to be tested, as in a | |
6839 | @code{define_insn}. When an insn matching @var{insn-pattern} and | |
6840 | satisfying @var{condition} is found, it is replaced in the insn list | |
6841 | with the insns given by @var{new-insn-pattern-1}, | |
6842 | @var{new-insn-pattern-2}, etc. | |
6843 | ||
630d3d5a | 6844 | The @var{preparation-statements} are similar to those statements that |
03dda8e3 RK |
6845 | are specified for @code{define_expand} (@pxref{Expander Definitions}) |
6846 | and are executed before the new RTL is generated to prepare for the | |
6847 | generated code or emit some insns whose pattern is not fixed. Unlike | |
6848 | those in @code{define_expand}, however, these statements must not | |
6849 | generate any new pseudo-registers. Once reload has completed, they also | |
6850 | must not allocate any space in the stack frame. | |
6851 | ||
6852 | Patterns are matched against @var{insn-pattern} in two different | |
6853 | circumstances. If an insn needs to be split for delay slot scheduling | |
6854 | or insn scheduling, the insn is already known to be valid, which means | |
6855 | that it must have been matched by some @code{define_insn} and, if | |
df2a54e9 | 6856 | @code{reload_completed} is nonzero, is known to satisfy the constraints |
03dda8e3 RK |
6857 | of that @code{define_insn}. In that case, the new insn patterns must |
6858 | also be insns that are matched by some @code{define_insn} and, if | |
df2a54e9 | 6859 | @code{reload_completed} is nonzero, must also satisfy the constraints |
03dda8e3 RK |
6860 | of those definitions. |
6861 | ||
6862 | As an example of this usage of @code{define_split}, consider the following | |
6863 | example from @file{a29k.md}, which splits a @code{sign_extend} from | |
6864 | @code{HImode} to @code{SImode} into a pair of shift insns: | |
6865 | ||
6866 | @smallexample | |
6867 | (define_split | |
6868 | [(set (match_operand:SI 0 "gen_reg_operand" "") | |
6869 | (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] | |
6870 | "" | |
6871 | [(set (match_dup 0) | |
6872 | (ashift:SI (match_dup 1) | |
6873 | (const_int 16))) | |
6874 | (set (match_dup 0) | |
6875 | (ashiftrt:SI (match_dup 0) | |
6876 | (const_int 16)))] | |
6877 | " | |
6878 | @{ operands[1] = gen_lowpart (SImode, operands[1]); @}") | |
6879 | @end smallexample | |
6880 | ||
6881 | When the combiner phase tries to split an insn pattern, it is always the | |
6882 | case that the pattern is @emph{not} matched by any @code{define_insn}. | |
6883 | The combiner pass first tries to split a single @code{set} expression | |
6884 | and then the same @code{set} expression inside a @code{parallel}, but | |
6885 | followed by a @code{clobber} of a pseudo-reg to use as a scratch | |
6886 | register. In these cases, the combiner expects exactly two new insn | |
6887 | patterns to be generated. It will verify that these patterns match some | |
6888 | @code{define_insn} definitions, so you need not do this test in the | |
6889 | @code{define_split} (of course, there is no point in writing a | |
6890 | @code{define_split} that will never produce insns that match). | |
6891 | ||
6892 | Here is an example of this use of @code{define_split}, taken from | |
6893 | @file{rs6000.md}: | |
6894 | ||
6895 | @smallexample | |
6896 | (define_split | |
6897 | [(set (match_operand:SI 0 "gen_reg_operand" "") | |
6898 | (plus:SI (match_operand:SI 1 "gen_reg_operand" "") | |
6899 | (match_operand:SI 2 "non_add_cint_operand" "")))] | |
6900 | "" | |
6901 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) | |
6902 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
6903 | " | |
6904 | @{ | |
6905 | int low = INTVAL (operands[2]) & 0xffff; | |
6906 | int high = (unsigned) INTVAL (operands[2]) >> 16; | |
6907 | ||
6908 | if (low & 0x8000) | |
6909 | high++, low |= 0xffff0000; | |
6910 | ||
3a598fbe JL |
6911 | operands[3] = GEN_INT (high << 16); |
6912 | operands[4] = GEN_INT (low); | |
03dda8e3 RK |
6913 | @}") |
6914 | @end smallexample | |
6915 | ||
6916 | Here the predicate @code{non_add_cint_operand} matches any | |
6917 | @code{const_int} that is @emph{not} a valid operand of a single add | |
6918 | insn. The add with the smaller displacement is written so that it | |
6919 | can be substituted into the address of a subsequent operation. | |
6920 | ||
6921 | An example that uses a scratch register, from the same file, generates | |
6922 | an equality comparison of a register and a large constant: | |
6923 | ||
6924 | @smallexample | |
6925 | (define_split | |
6926 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
6927 | (compare:CC (match_operand:SI 1 "gen_reg_operand" "") | |
6928 | (match_operand:SI 2 "non_short_cint_operand" ""))) | |
6929 | (clobber (match_operand:SI 3 "gen_reg_operand" ""))] | |
6930 | "find_single_use (operands[0], insn, 0) | |
6931 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
6932 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
6933 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
6934 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
6935 | " | |
6936 | @{ | |
12bcfaa1 | 6937 | /* @r{Get the constant we are comparing against, C, and see what it |
03dda8e3 | 6938 | looks like sign-extended to 16 bits. Then see what constant |
12bcfaa1 | 6939 | could be XOR'ed with C to get the sign-extended value.} */ |
03dda8e3 RK |
6940 | |
6941 | int c = INTVAL (operands[2]); | |
6942 | int sextc = (c << 16) >> 16; | |
6943 | int xorv = c ^ sextc; | |
6944 | ||
3a598fbe JL |
6945 | operands[4] = GEN_INT (xorv); |
6946 | operands[5] = GEN_INT (sextc); | |
03dda8e3 RK |
6947 | @}") |
6948 | @end smallexample | |
6949 | ||
6950 | To avoid confusion, don't write a single @code{define_split} that | |
6951 | accepts some insns that match some @code{define_insn} as well as some | |
6952 | insns that don't. Instead, write two separate @code{define_split} | |
6953 | definitions, one for the insns that are valid and one for the insns that | |
6954 | are not valid. | |
6955 | ||
6b24c259 JH |
6956 | The splitter is allowed to split jump instructions into sequence of |
6957 | jumps or create new jumps in while splitting non-jump instructions. As | |
6958 | the central flowgraph and branch prediction information needs to be updated, | |
f282ffb3 | 6959 | several restriction apply. |
6b24c259 JH |
6960 | |
6961 | Splitting of jump instruction into sequence that over by another jump | |
c21cd8b1 | 6962 | instruction is always valid, as compiler expect identical behavior of new |
6b24c259 JH |
6963 | jump. When new sequence contains multiple jump instructions or new labels, |
6964 | more assistance is needed. Splitter is required to create only unconditional | |
6965 | jumps, or simple conditional jump instructions. Additionally it must attach a | |
63519d23 | 6966 | @code{REG_BR_PROB} note to each conditional jump. A global variable |
addd6f64 | 6967 | @code{split_branch_probability} holds the probability of the original branch in case |
e4ae5e77 | 6968 | it was a simple conditional jump, @minus{}1 otherwise. To simplify |
addd6f64 | 6969 | recomputing of edge frequencies, the new sequence is required to have only |
6b24c259 JH |
6970 | forward jumps to the newly created labels. |
6971 | ||
fae81b38 | 6972 | @findex define_insn_and_split |
c88c0d42 CP |
6973 | For the common case where the pattern of a define_split exactly matches the |
6974 | pattern of a define_insn, use @code{define_insn_and_split}. It looks like | |
6975 | this: | |
6976 | ||
6977 | @smallexample | |
6978 | (define_insn_and_split | |
6979 | [@var{insn-pattern}] | |
6980 | "@var{condition}" | |
6981 | "@var{output-template}" | |
6982 | "@var{split-condition}" | |
6983 | [@var{new-insn-pattern-1} | |
6984 | @var{new-insn-pattern-2} | |
6985 | @dots{}] | |
630d3d5a | 6986 | "@var{preparation-statements}" |
c88c0d42 CP |
6987 | [@var{insn-attributes}]) |
6988 | ||
6989 | @end smallexample | |
6990 | ||
6991 | @var{insn-pattern}, @var{condition}, @var{output-template}, and | |
6992 | @var{insn-attributes} are used as in @code{define_insn}. The | |
6993 | @var{new-insn-pattern} vector and the @var{preparation-statements} are used as | |
6994 | in a @code{define_split}. The @var{split-condition} is also used as in | |
6995 | @code{define_split}, with the additional behavior that if the condition starts | |
6996 | with @samp{&&}, the condition used for the split will be the constructed as a | |
d7d9c429 | 6997 | logical ``and'' of the split condition with the insn condition. For example, |
c88c0d42 CP |
6998 | from i386.md: |
6999 | ||
7000 | @smallexample | |
7001 | (define_insn_and_split "zero_extendhisi2_and" | |
7002 | [(set (match_operand:SI 0 "register_operand" "=r") | |
7003 | (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))) | |
7004 | (clobber (reg:CC 17))] | |
7005 | "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" | |
7006 | "#" | |
7007 | "&& reload_completed" | |
f282ffb3 | 7008 | [(parallel [(set (match_dup 0) |
9c34dbbf | 7009 | (and:SI (match_dup 0) (const_int 65535))) |
6ccde948 | 7010 | (clobber (reg:CC 17))])] |
c88c0d42 CP |
7011 | "" |
7012 | [(set_attr "type" "alu1")]) | |
7013 | ||
7014 | @end smallexample | |
7015 | ||
ebb48a4d | 7016 | In this case, the actual split condition will be |
aee96fe9 | 7017 | @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}. |
c88c0d42 CP |
7018 | |
7019 | The @code{define_insn_and_split} construction provides exactly the same | |
7020 | functionality as two separate @code{define_insn} and @code{define_split} | |
7021 | patterns. It exists for compactness, and as a maintenance tool to prevent | |
7022 | having to ensure the two patterns' templates match. | |
7023 | ||
a5249a21 HPN |
7024 | @end ifset |
7025 | @ifset INTERNALS | |
04d8aa70 AM |
7026 | @node Including Patterns |
7027 | @section Including Patterns in Machine Descriptions. | |
7028 | @cindex insn includes | |
7029 | ||
7030 | @findex include | |
7031 | The @code{include} pattern tells the compiler tools where to | |
7032 | look for patterns that are in files other than in the file | |
8a36672b | 7033 | @file{.md}. This is used only at build time and there is no preprocessing allowed. |
04d8aa70 AM |
7034 | |
7035 | It looks like: | |
7036 | ||
7037 | @smallexample | |
7038 | ||
7039 | (include | |
7040 | @var{pathname}) | |
7041 | @end smallexample | |
7042 | ||
7043 | For example: | |
7044 | ||
7045 | @smallexample | |
7046 | ||
f282ffb3 | 7047 | (include "filestuff") |
04d8aa70 AM |
7048 | |
7049 | @end smallexample | |
7050 | ||
27d30956 | 7051 | Where @var{pathname} is a string that specifies the location of the file, |
8a36672b | 7052 | specifies the include file to be in @file{gcc/config/target/filestuff}. The |
04d8aa70 AM |
7053 | directory @file{gcc/config/target} is regarded as the default directory. |
7054 | ||
7055 | ||
f282ffb3 JM |
7056 | Machine descriptions may be split up into smaller more manageable subsections |
7057 | and placed into subdirectories. | |
04d8aa70 AM |
7058 | |
7059 | By specifying: | |
7060 | ||
7061 | @smallexample | |
7062 | ||
f282ffb3 | 7063 | (include "BOGUS/filestuff") |
04d8aa70 AM |
7064 | |
7065 | @end smallexample | |
7066 | ||
7067 | the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}. | |
7068 | ||
7069 | Specifying an absolute path for the include file such as; | |
7070 | @smallexample | |
7071 | ||
f282ffb3 | 7072 | (include "/u2/BOGUS/filestuff") |
04d8aa70 AM |
7073 | |
7074 | @end smallexample | |
f282ffb3 | 7075 | is permitted but is not encouraged. |
04d8aa70 AM |
7076 | |
7077 | @subsection RTL Generation Tool Options for Directory Search | |
7078 | @cindex directory options .md | |
7079 | @cindex options, directory search | |
7080 | @cindex search options | |
7081 | ||
7082 | The @option{-I@var{dir}} option specifies directories to search for machine descriptions. | |
7083 | For example: | |
7084 | ||
7085 | @smallexample | |
7086 | ||
7087 | genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md | |
7088 | ||
7089 | @end smallexample | |
7090 | ||
7091 | ||
7092 | Add the directory @var{dir} to the head of the list of directories to be | |
7093 | searched for header files. This can be used to override a system machine definition | |
7094 | file, substituting your own version, since these directories are | |
7095 | searched before the default machine description file directories. If you use more than | |
7096 | one @option{-I} option, the directories are scanned in left-to-right | |
7097 | order; the standard default directory come after. | |
7098 | ||
7099 | ||
a5249a21 HPN |
7100 | @end ifset |
7101 | @ifset INTERNALS | |
f3a3d0d3 RH |
7102 | @node Peephole Definitions |
7103 | @section Machine-Specific Peephole Optimizers | |
7104 | @cindex peephole optimizer definitions | |
7105 | @cindex defining peephole optimizers | |
7106 | ||
7107 | In addition to instruction patterns the @file{md} file may contain | |
7108 | definitions of machine-specific peephole optimizations. | |
7109 | ||
7110 | The combiner does not notice certain peephole optimizations when the data | |
7111 | flow in the program does not suggest that it should try them. For example, | |
7112 | sometimes two consecutive insns related in purpose can be combined even | |
7113 | though the second one does not appear to use a register computed in the | |
7114 | first one. A machine-specific peephole optimizer can detect such | |
7115 | opportunities. | |
7116 | ||
7117 | There are two forms of peephole definitions that may be used. The | |
7118 | original @code{define_peephole} is run at assembly output time to | |
7119 | match insns and substitute assembly text. Use of @code{define_peephole} | |
7120 | is deprecated. | |
7121 | ||
7122 | A newer @code{define_peephole2} matches insns and substitutes new | |
7123 | insns. The @code{peephole2} pass is run after register allocation | |
ebb48a4d | 7124 | but before scheduling, which may result in much better code for |
f3a3d0d3 RH |
7125 | targets that do scheduling. |
7126 | ||
7127 | @menu | |
7128 | * define_peephole:: RTL to Text Peephole Optimizers | |
7129 | * define_peephole2:: RTL to RTL Peephole Optimizers | |
7130 | @end menu | |
7131 | ||
a5249a21 HPN |
7132 | @end ifset |
7133 | @ifset INTERNALS | |
f3a3d0d3 RH |
7134 | @node define_peephole |
7135 | @subsection RTL to Text Peephole Optimizers | |
7136 | @findex define_peephole | |
7137 | ||
7138 | @need 1000 | |
7139 | A definition looks like this: | |
7140 | ||
7141 | @smallexample | |
7142 | (define_peephole | |
7143 | [@var{insn-pattern-1} | |
7144 | @var{insn-pattern-2} | |
7145 | @dots{}] | |
7146 | "@var{condition}" | |
7147 | "@var{template}" | |
630d3d5a | 7148 | "@var{optional-insn-attributes}") |
f3a3d0d3 RH |
7149 | @end smallexample |
7150 | ||
7151 | @noindent | |
7152 | The last string operand may be omitted if you are not using any | |
7153 | machine-specific information in this machine description. If present, | |
7154 | it must obey the same rules as in a @code{define_insn}. | |
7155 | ||
7156 | In this skeleton, @var{insn-pattern-1} and so on are patterns to match | |
7157 | consecutive insns. The optimization applies to a sequence of insns when | |
7158 | @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches | |
bd819a4a | 7159 | the next, and so on. |
f3a3d0d3 RH |
7160 | |
7161 | Each of the insns matched by a peephole must also match a | |
7162 | @code{define_insn}. Peepholes are checked only at the last stage just | |
7163 | before code generation, and only optionally. Therefore, any insn which | |
7164 | would match a peephole but no @code{define_insn} will cause a crash in code | |
7165 | generation in an unoptimized compilation, or at various optimization | |
7166 | stages. | |
7167 | ||
7168 | The operands of the insns are matched with @code{match_operands}, | |
7169 | @code{match_operator}, and @code{match_dup}, as usual. What is not | |
7170 | usual is that the operand numbers apply to all the insn patterns in the | |
7171 | definition. So, you can check for identical operands in two insns by | |
7172 | using @code{match_operand} in one insn and @code{match_dup} in the | |
7173 | other. | |
7174 | ||
7175 | The operand constraints used in @code{match_operand} patterns do not have | |
7176 | any direct effect on the applicability of the peephole, but they will | |
7177 | be validated afterward, so make sure your constraints are general enough | |
7178 | to apply whenever the peephole matches. If the peephole matches | |
7179 | but the constraints are not satisfied, the compiler will crash. | |
7180 | ||
7181 | It is safe to omit constraints in all the operands of the peephole; or | |
7182 | you can write constraints which serve as a double-check on the criteria | |
7183 | previously tested. | |
7184 | ||
7185 | Once a sequence of insns matches the patterns, the @var{condition} is | |
7186 | checked. This is a C expression which makes the final decision whether to | |
7187 | perform the optimization (we do so if the expression is nonzero). If | |
7188 | @var{condition} is omitted (in other words, the string is empty) then the | |
7189 | optimization is applied to every sequence of insns that matches the | |
7190 | patterns. | |
7191 | ||
7192 | The defined peephole optimizations are applied after register allocation | |
7193 | is complete. Therefore, the peephole definition can check which | |
7194 | operands have ended up in which kinds of registers, just by looking at | |
7195 | the operands. | |
7196 | ||
7197 | @findex prev_active_insn | |
7198 | The way to refer to the operands in @var{condition} is to write | |
7199 | @code{operands[@var{i}]} for operand number @var{i} (as matched by | |
7200 | @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn} | |
7201 | to refer to the last of the insns being matched; use | |
7202 | @code{prev_active_insn} to find the preceding insns. | |
7203 | ||
7204 | @findex dead_or_set_p | |
7205 | When optimizing computations with intermediate results, you can use | |
7206 | @var{condition} to match only when the intermediate results are not used | |
7207 | elsewhere. Use the C expression @code{dead_or_set_p (@var{insn}, | |
7208 | @var{op})}, where @var{insn} is the insn in which you expect the value | |
7209 | to be used for the last time (from the value of @code{insn}, together | |
7210 | with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate | |
bd819a4a | 7211 | value (from @code{operands[@var{i}]}). |
f3a3d0d3 RH |
7212 | |
7213 | Applying the optimization means replacing the sequence of insns with one | |
7214 | new insn. The @var{template} controls ultimate output of assembler code | |
7215 | for this combined insn. It works exactly like the template of a | |
7216 | @code{define_insn}. Operand numbers in this template are the same ones | |
7217 | used in matching the original sequence of insns. | |
7218 | ||
7219 | The result of a defined peephole optimizer does not need to match any of | |
7220 | the insn patterns in the machine description; it does not even have an | |
7221 | opportunity to match them. The peephole optimizer definition itself serves | |
7222 | as the insn pattern to control how the insn is output. | |
7223 | ||
7224 | Defined peephole optimizers are run as assembler code is being output, | |
7225 | so the insns they produce are never combined or rearranged in any way. | |
7226 | ||
7227 | Here is an example, taken from the 68000 machine description: | |
7228 | ||
7229 | @smallexample | |
7230 | (define_peephole | |
7231 | [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) | |
7232 | (set (match_operand:DF 0 "register_operand" "=f") | |
7233 | (match_operand:DF 1 "register_operand" "ad"))] | |
7234 | "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" | |
f3a3d0d3 RH |
7235 | @{ |
7236 | rtx xoperands[2]; | |
a2a8cc44 | 7237 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
f3a3d0d3 | 7238 | #ifdef MOTOROLA |
0f40f9f7 ZW |
7239 | output_asm_insn ("move.l %1,(sp)", xoperands); |
7240 | output_asm_insn ("move.l %1,-(sp)", operands); | |
7241 | return "fmove.d (sp)+,%0"; | |
f3a3d0d3 | 7242 | #else |
0f40f9f7 ZW |
7243 | output_asm_insn ("movel %1,sp@@", xoperands); |
7244 | output_asm_insn ("movel %1,sp@@-", operands); | |
7245 | return "fmoved sp@@+,%0"; | |
f3a3d0d3 | 7246 | #endif |
0f40f9f7 | 7247 | @}) |
f3a3d0d3 RH |
7248 | @end smallexample |
7249 | ||
7250 | @need 1000 | |
7251 | The effect of this optimization is to change | |
7252 | ||
7253 | @smallexample | |
7254 | @group | |
7255 | jbsr _foobar | |
7256 | addql #4,sp | |
7257 | movel d1,sp@@- | |
7258 | movel d0,sp@@- | |
7259 | fmoved sp@@+,fp0 | |
7260 | @end group | |
7261 | @end smallexample | |
7262 | ||
7263 | @noindent | |
7264 | into | |
7265 | ||
7266 | @smallexample | |
7267 | @group | |
7268 | jbsr _foobar | |
7269 | movel d1,sp@@ | |
7270 | movel d0,sp@@- | |
7271 | fmoved sp@@+,fp0 | |
7272 | @end group | |
7273 | @end smallexample | |
7274 | ||
7275 | @ignore | |
7276 | @findex CC_REVERSED | |
7277 | If a peephole matches a sequence including one or more jump insns, you must | |
7278 | take account of the flags such as @code{CC_REVERSED} which specify that the | |
7279 | condition codes are represented in an unusual manner. The compiler | |
7280 | automatically alters any ordinary conditional jumps which occur in such | |
7281 | situations, but the compiler cannot alter jumps which have been replaced by | |
7282 | peephole optimizations. So it is up to you to alter the assembler code | |
7283 | that the peephole produces. Supply C code to write the assembler output, | |
7284 | and in this C code check the condition code status flags and change the | |
7285 | assembler code as appropriate. | |
7286 | @end ignore | |
7287 | ||
7288 | @var{insn-pattern-1} and so on look @emph{almost} like the second | |
7289 | operand of @code{define_insn}. There is one important difference: the | |
7290 | second operand of @code{define_insn} consists of one or more RTX's | |
7291 | enclosed in square brackets. Usually, there is only one: then the same | |
7292 | action can be written as an element of a @code{define_peephole}. But | |
7293 | when there are multiple actions in a @code{define_insn}, they are | |
7294 | implicitly enclosed in a @code{parallel}. Then you must explicitly | |
7295 | write the @code{parallel}, and the square brackets within it, in the | |
7296 | @code{define_peephole}. Thus, if an insn pattern looks like this, | |
7297 | ||
7298 | @smallexample | |
7299 | (define_insn "divmodsi4" | |
7300 | [(set (match_operand:SI 0 "general_operand" "=d") | |
7301 | (div:SI (match_operand:SI 1 "general_operand" "0") | |
7302 | (match_operand:SI 2 "general_operand" "dmsK"))) | |
7303 | (set (match_operand:SI 3 "general_operand" "=d") | |
7304 | (mod:SI (match_dup 1) (match_dup 2)))] | |
7305 | "TARGET_68020" | |
7306 | "divsl%.l %2,%3:%0") | |
7307 | @end smallexample | |
7308 | ||
7309 | @noindent | |
7310 | then the way to mention this insn in a peephole is as follows: | |
7311 | ||
7312 | @smallexample | |
7313 | (define_peephole | |
7314 | [@dots{} | |
7315 | (parallel | |
7316 | [(set (match_operand:SI 0 "general_operand" "=d") | |
7317 | (div:SI (match_operand:SI 1 "general_operand" "0") | |
7318 | (match_operand:SI 2 "general_operand" "dmsK"))) | |
7319 | (set (match_operand:SI 3 "general_operand" "=d") | |
7320 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
7321 | @dots{}] | |
7322 | @dots{}) | |
7323 | @end smallexample | |
7324 | ||
a5249a21 HPN |
7325 | @end ifset |
7326 | @ifset INTERNALS | |
f3a3d0d3 RH |
7327 | @node define_peephole2 |
7328 | @subsection RTL to RTL Peephole Optimizers | |
7329 | @findex define_peephole2 | |
7330 | ||
7331 | The @code{define_peephole2} definition tells the compiler how to | |
ebb48a4d | 7332 | substitute one sequence of instructions for another sequence, |
f3a3d0d3 RH |
7333 | what additional scratch registers may be needed and what their |
7334 | lifetimes must be. | |
7335 | ||
7336 | @smallexample | |
7337 | (define_peephole2 | |
7338 | [@var{insn-pattern-1} | |
7339 | @var{insn-pattern-2} | |
7340 | @dots{}] | |
7341 | "@var{condition}" | |
7342 | [@var{new-insn-pattern-1} | |
7343 | @var{new-insn-pattern-2} | |
7344 | @dots{}] | |
630d3d5a | 7345 | "@var{preparation-statements}") |
f3a3d0d3 RH |
7346 | @end smallexample |
7347 | ||
7348 | The definition is almost identical to @code{define_split} | |
7349 | (@pxref{Insn Splitting}) except that the pattern to match is not a | |
7350 | single instruction, but a sequence of instructions. | |
7351 | ||
7352 | It is possible to request additional scratch registers for use in the | |
7353 | output template. If appropriate registers are not free, the pattern | |
7354 | will simply not match. | |
7355 | ||
7356 | @findex match_scratch | |
7357 | @findex match_dup | |
7358 | Scratch registers are requested with a @code{match_scratch} pattern at | |
7359 | the top level of the input pattern. The allocated register (initially) will | |
7360 | be dead at the point requested within the original sequence. If the scratch | |
7361 | is used at more than a single point, a @code{match_dup} pattern at the | |
7362 | top level of the input pattern marks the last position in the input sequence | |
7363 | at which the register must be available. | |
7364 | ||
7365 | Here is an example from the IA-32 machine description: | |
7366 | ||
7367 | @smallexample | |
7368 | (define_peephole2 | |
7369 | [(match_scratch:SI 2 "r") | |
7370 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
7371 | (match_operator:SI 3 "arith_or_logical_operator" | |
7372 | [(match_dup 0) | |
7373 | (match_operand:SI 1 "memory_operand" "")])) | |
7374 | (clobber (reg:CC 17))])] | |
7375 | "! optimize_size && ! TARGET_READ_MODIFY" | |
7376 | [(set (match_dup 2) (match_dup 1)) | |
7377 | (parallel [(set (match_dup 0) | |
7378 | (match_op_dup 3 [(match_dup 0) (match_dup 2)])) | |
7379 | (clobber (reg:CC 17))])] | |
7380 | "") | |
7381 | @end smallexample | |
7382 | ||
7383 | @noindent | |
7384 | This pattern tries to split a load from its use in the hopes that we'll be | |
7385 | able to schedule around the memory load latency. It allocates a single | |
7386 | @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs | |
7387 | to be live only at the point just before the arithmetic. | |
7388 | ||
b192711e | 7389 | A real example requiring extended scratch lifetimes is harder to come by, |
f3a3d0d3 RH |
7390 | so here's a silly made-up example: |
7391 | ||
7392 | @smallexample | |
7393 | (define_peephole2 | |
7394 | [(match_scratch:SI 4 "r") | |
7395 | (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" "")) | |
7396 | (set (match_operand:SI 2 "" "") (match_dup 1)) | |
7397 | (match_dup 4) | |
7398 | (set (match_operand:SI 3 "" "") (match_dup 1))] | |
630d3d5a | 7399 | "/* @r{determine 1 does not overlap 0 and 2} */" |
f3a3d0d3 RH |
7400 | [(set (match_dup 4) (match_dup 1)) |
7401 | (set (match_dup 0) (match_dup 4)) | |
7402 | (set (match_dup 2) (match_dup 4))] | |
7403 | (set (match_dup 3) (match_dup 4))] | |
7404 | "") | |
7405 | @end smallexample | |
7406 | ||
7407 | @noindent | |
a628d195 RH |
7408 | If we had not added the @code{(match_dup 4)} in the middle of the input |
7409 | sequence, it might have been the case that the register we chose at the | |
7410 | beginning of the sequence is killed by the first or second @code{set}. | |
f3a3d0d3 | 7411 | |
a5249a21 HPN |
7412 | @end ifset |
7413 | @ifset INTERNALS | |
03dda8e3 RK |
7414 | @node Insn Attributes |
7415 | @section Instruction Attributes | |
7416 | @cindex insn attributes | |
7417 | @cindex instruction attributes | |
7418 | ||
7419 | In addition to describing the instruction supported by the target machine, | |
7420 | the @file{md} file also defines a group of @dfn{attributes} and a set of | |
7421 | values for each. Every generated insn is assigned a value for each attribute. | |
7422 | One possible attribute would be the effect that the insn has on the machine's | |
7423 | condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC} | |
7424 | to track the condition codes. | |
7425 | ||
7426 | @menu | |
7427 | * Defining Attributes:: Specifying attributes and their values. | |
7428 | * Expressions:: Valid expressions for attribute values. | |
7429 | * Tagging Insns:: Assigning attribute values to insns. | |
7430 | * Attr Example:: An example of assigning attributes. | |
7431 | * Insn Lengths:: Computing the length of insns. | |
7432 | * Constant Attributes:: Defining attributes that are constant. | |
7433 | * Delay Slots:: Defining delay slots required for a machine. | |
fae15c93 | 7434 | * Processor pipeline description:: Specifying information for insn scheduling. |
03dda8e3 RK |
7435 | @end menu |
7436 | ||
a5249a21 HPN |
7437 | @end ifset |
7438 | @ifset INTERNALS | |
03dda8e3 RK |
7439 | @node Defining Attributes |
7440 | @subsection Defining Attributes and their Values | |
7441 | @cindex defining attributes and their values | |
7442 | @cindex attributes, defining | |
7443 | ||
7444 | @findex define_attr | |
7445 | The @code{define_attr} expression is used to define each attribute required | |
7446 | by the target machine. It looks like: | |
7447 | ||
7448 | @smallexample | |
7449 | (define_attr @var{name} @var{list-of-values} @var{default}) | |
7450 | @end smallexample | |
7451 | ||
7452 | @var{name} is a string specifying the name of the attribute being defined. | |
0bddee8e BS |
7453 | Some attributes are used in a special way by the rest of the compiler. The |
7454 | @code{enabled} attribute can be used to conditionally enable or disable | |
7455 | insn alternatives (@pxref{Disable Insn Alternatives}). The @code{predicable} | |
7456 | attribute, together with a suitable @code{define_cond_exec} | |
7457 | (@pxref{Conditional Execution}), can be used to automatically generate | |
7458 | conditional variants of instruction patterns. The compiler internally uses | |
7459 | the names @code{ce_enabled} and @code{nonce_enabled}, so they should not be | |
7460 | used elsewhere as alternative names. | |
03dda8e3 RK |
7461 | |
7462 | @var{list-of-values} is either a string that specifies a comma-separated | |
7463 | list of values that can be assigned to the attribute, or a null string to | |
7464 | indicate that the attribute takes numeric values. | |
7465 | ||
7466 | @var{default} is an attribute expression that gives the value of this | |
7467 | attribute for insns that match patterns whose definition does not include | |
7468 | an explicit value for this attribute. @xref{Attr Example}, for more | |
7469 | information on the handling of defaults. @xref{Constant Attributes}, | |
7470 | for information on attributes that do not depend on any particular insn. | |
7471 | ||
7472 | @findex insn-attr.h | |
7473 | For each defined attribute, a number of definitions are written to the | |
7474 | @file{insn-attr.h} file. For cases where an explicit set of values is | |
7475 | specified for an attribute, the following are defined: | |
7476 | ||
7477 | @itemize @bullet | |
7478 | @item | |
7479 | A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}. | |
7480 | ||
7481 | @item | |
2eac577f | 7482 | An enumerated class is defined for @samp{attr_@var{name}} with |
03dda8e3 | 7483 | elements of the form @samp{@var{upper-name}_@var{upper-value}} where |
4bd0bee9 | 7484 | the attribute name and value are first converted to uppercase. |
03dda8e3 RK |
7485 | |
7486 | @item | |
7487 | A function @samp{get_attr_@var{name}} is defined that is passed an insn and | |
7488 | returns the attribute value for that insn. | |
7489 | @end itemize | |
7490 | ||
7491 | For example, if the following is present in the @file{md} file: | |
7492 | ||
7493 | @smallexample | |
7494 | (define_attr "type" "branch,fp,load,store,arith" @dots{}) | |
7495 | @end smallexample | |
7496 | ||
7497 | @noindent | |
7498 | the following lines will be written to the file @file{insn-attr.h}. | |
7499 | ||
7500 | @smallexample | |
7501 | #define HAVE_ATTR_type | |
7502 | enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD, | |
7503 | TYPE_STORE, TYPE_ARITH@}; | |
7504 | extern enum attr_type get_attr_type (); | |
7505 | @end smallexample | |
7506 | ||
7507 | If the attribute takes numeric values, no @code{enum} type will be | |
7508 | defined and the function to obtain the attribute's value will return | |
7509 | @code{int}. | |
7510 | ||
7ac28727 AK |
7511 | There are attributes which are tied to a specific meaning. These |
7512 | attributes are not free to use for other purposes: | |
7513 | ||
7514 | @table @code | |
7515 | @item length | |
7516 | The @code{length} attribute is used to calculate the length of emitted | |
7517 | code chunks. This is especially important when verifying branch | |
7518 | distances. @xref{Insn Lengths}. | |
7519 | ||
7520 | @item enabled | |
7521 | The @code{enabled} attribute can be defined to prevent certain | |
7522 | alternatives of an insn definition from being used during code | |
7523 | generation. @xref{Disable Insn Alternatives}. | |
7ac28727 AK |
7524 | @end table |
7525 | ||
8f4fe86c RS |
7526 | @findex define_enum_attr |
7527 | @anchor{define_enum_attr} | |
7528 | Another way of defining an attribute is to use: | |
7529 | ||
7530 | @smallexample | |
7531 | (define_enum_attr "@var{attr}" "@var{enum}" @var{default}) | |
7532 | @end smallexample | |
7533 | ||
7534 | This works in just the same way as @code{define_attr}, except that | |
7535 | the list of values is taken from a separate enumeration called | |
7536 | @var{enum} (@pxref{define_enum}). This form allows you to use | |
7537 | the same list of values for several attributes without having to | |
7538 | repeat the list each time. For example: | |
7539 | ||
7540 | @smallexample | |
7541 | (define_enum "processor" [ | |
7542 | model_a | |
7543 | model_b | |
7544 | @dots{} | |
7545 | ]) | |
7546 | (define_enum_attr "arch" "processor" | |
7547 | (const (symbol_ref "target_arch"))) | |
7548 | (define_enum_attr "tune" "processor" | |
7549 | (const (symbol_ref "target_tune"))) | |
7550 | @end smallexample | |
7551 | ||
7552 | defines the same attributes as: | |
7553 | ||
7554 | @smallexample | |
7555 | (define_attr "arch" "model_a,model_b,@dots{}" | |
7556 | (const (symbol_ref "target_arch"))) | |
7557 | (define_attr "tune" "model_a,model_b,@dots{}" | |
7558 | (const (symbol_ref "target_tune"))) | |
7559 | @end smallexample | |
7560 | ||
7561 | but without duplicating the processor list. The second example defines two | |
7562 | separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first | |
7563 | defines a single C enum (@code{processor}). | |
a5249a21 HPN |
7564 | @end ifset |
7565 | @ifset INTERNALS | |
03dda8e3 RK |
7566 | @node Expressions |
7567 | @subsection Attribute Expressions | |
7568 | @cindex attribute expressions | |
7569 | ||
7570 | RTL expressions used to define attributes use the codes described above | |
7571 | plus a few specific to attribute definitions, to be discussed below. | |
7572 | Attribute value expressions must have one of the following forms: | |
7573 | ||
7574 | @table @code | |
7575 | @cindex @code{const_int} and attributes | |
7576 | @item (const_int @var{i}) | |
7577 | The integer @var{i} specifies the value of a numeric attribute. @var{i} | |
7578 | must be non-negative. | |
7579 | ||
7580 | The value of a numeric attribute can be specified either with a | |
00bc45c1 RH |
7581 | @code{const_int}, or as an integer represented as a string in |
7582 | @code{const_string}, @code{eq_attr} (see below), @code{attr}, | |
7583 | @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr} | |
7584 | overrides on specific instructions (@pxref{Tagging Insns}). | |
03dda8e3 RK |
7585 | |
7586 | @cindex @code{const_string} and attributes | |
7587 | @item (const_string @var{value}) | |
7588 | The string @var{value} specifies a constant attribute value. | |
7589 | If @var{value} is specified as @samp{"*"}, it means that the default value of | |
7590 | the attribute is to be used for the insn containing this expression. | |
7591 | @samp{"*"} obviously cannot be used in the @var{default} expression | |
bd819a4a | 7592 | of a @code{define_attr}. |
03dda8e3 RK |
7593 | |
7594 | If the attribute whose value is being specified is numeric, @var{value} | |
7595 | must be a string containing a non-negative integer (normally | |
7596 | @code{const_int} would be used in this case). Otherwise, it must | |
7597 | contain one of the valid values for the attribute. | |
7598 | ||
7599 | @cindex @code{if_then_else} and attributes | |
7600 | @item (if_then_else @var{test} @var{true-value} @var{false-value}) | |
7601 | @var{test} specifies an attribute test, whose format is defined below. | |
7602 | The value of this expression is @var{true-value} if @var{test} is true, | |
7603 | otherwise it is @var{false-value}. | |
7604 | ||
7605 | @cindex @code{cond} and attributes | |
7606 | @item (cond [@var{test1} @var{value1} @dots{}] @var{default}) | |
7607 | The first operand of this expression is a vector containing an even | |
7608 | number of expressions and consisting of pairs of @var{test} and @var{value} | |
7609 | expressions. The value of the @code{cond} expression is that of the | |
7610 | @var{value} corresponding to the first true @var{test} expression. If | |
7611 | none of the @var{test} expressions are true, the value of the @code{cond} | |
7612 | expression is that of the @var{default} expression. | |
7613 | @end table | |
7614 | ||
7615 | @var{test} expressions can have one of the following forms: | |
7616 | ||
7617 | @table @code | |
7618 | @cindex @code{const_int} and attribute tests | |
7619 | @item (const_int @var{i}) | |
df2a54e9 | 7620 | This test is true if @var{i} is nonzero and false otherwise. |
03dda8e3 RK |
7621 | |
7622 | @cindex @code{not} and attributes | |
7623 | @cindex @code{ior} and attributes | |
7624 | @cindex @code{and} and attributes | |
7625 | @item (not @var{test}) | |
7626 | @itemx (ior @var{test1} @var{test2}) | |
7627 | @itemx (and @var{test1} @var{test2}) | |
7628 | These tests are true if the indicated logical function is true. | |
7629 | ||
7630 | @cindex @code{match_operand} and attributes | |
7631 | @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints}) | |
7632 | This test is true if operand @var{n} of the insn whose attribute value | |
7633 | is being determined has mode @var{m} (this part of the test is ignored | |
7634 | if @var{m} is @code{VOIDmode}) and the function specified by the string | |
df2a54e9 | 7635 | @var{pred} returns a nonzero value when passed operand @var{n} and mode |
03dda8e3 RK |
7636 | @var{m} (this part of the test is ignored if @var{pred} is the null |
7637 | string). | |
7638 | ||
7639 | The @var{constraints} operand is ignored and should be the null string. | |
7640 | ||
0c0d3957 RS |
7641 | @cindex @code{match_test} and attributes |
7642 | @item (match_test @var{c-expr}) | |
7643 | The test is true if C expression @var{c-expr} is true. In non-constant | |
7644 | attributes, @var{c-expr} has access to the following variables: | |
7645 | ||
7646 | @table @var | |
7647 | @item insn | |
7648 | The rtl instruction under test. | |
7649 | @item which_alternative | |
7650 | The @code{define_insn} alternative that @var{insn} matches. | |
7651 | @xref{Output Statement}. | |
7652 | @item operands | |
7653 | An array of @var{insn}'s rtl operands. | |
7654 | @end table | |
7655 | ||
7656 | @var{c-expr} behaves like the condition in a C @code{if} statement, | |
7657 | so there is no need to explicitly convert the expression into a boolean | |
7658 | 0 or 1 value. For example, the following two tests are equivalent: | |
7659 | ||
7660 | @smallexample | |
7661 | (match_test "x & 2") | |
7662 | (match_test "(x & 2) != 0") | |
7663 | @end smallexample | |
7664 | ||
03dda8e3 RK |
7665 | @cindex @code{le} and attributes |
7666 | @cindex @code{leu} and attributes | |
7667 | @cindex @code{lt} and attributes | |
7668 | @cindex @code{gt} and attributes | |
7669 | @cindex @code{gtu} and attributes | |
7670 | @cindex @code{ge} and attributes | |
7671 | @cindex @code{geu} and attributes | |
7672 | @cindex @code{ne} and attributes | |
7673 | @cindex @code{eq} and attributes | |
7674 | @cindex @code{plus} and attributes | |
7675 | @cindex @code{minus} and attributes | |
7676 | @cindex @code{mult} and attributes | |
7677 | @cindex @code{div} and attributes | |
7678 | @cindex @code{mod} and attributes | |
7679 | @cindex @code{abs} and attributes | |
7680 | @cindex @code{neg} and attributes | |
7681 | @cindex @code{ashift} and attributes | |
7682 | @cindex @code{lshiftrt} and attributes | |
7683 | @cindex @code{ashiftrt} and attributes | |
7684 | @item (le @var{arith1} @var{arith2}) | |
7685 | @itemx (leu @var{arith1} @var{arith2}) | |
7686 | @itemx (lt @var{arith1} @var{arith2}) | |
7687 | @itemx (ltu @var{arith1} @var{arith2}) | |
7688 | @itemx (gt @var{arith1} @var{arith2}) | |
7689 | @itemx (gtu @var{arith1} @var{arith2}) | |
7690 | @itemx (ge @var{arith1} @var{arith2}) | |
7691 | @itemx (geu @var{arith1} @var{arith2}) | |
7692 | @itemx (ne @var{arith1} @var{arith2}) | |
7693 | @itemx (eq @var{arith1} @var{arith2}) | |
7694 | These tests are true if the indicated comparison of the two arithmetic | |
7695 | expressions is true. Arithmetic expressions are formed with | |
7696 | @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod}, | |
7697 | @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not}, | |
bd819a4a | 7698 | @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions. |
03dda8e3 RK |
7699 | |
7700 | @findex get_attr | |
7701 | @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn | |
7702 | Lengths},for additional forms). @code{symbol_ref} is a string | |
7703 | denoting a C expression that yields an @code{int} when evaluated by the | |
7704 | @samp{get_attr_@dots{}} routine. It should normally be a global | |
bd819a4a | 7705 | variable. |
03dda8e3 RK |
7706 | |
7707 | @findex eq_attr | |
7708 | @item (eq_attr @var{name} @var{value}) | |
7709 | @var{name} is a string specifying the name of an attribute. | |
7710 | ||
7711 | @var{value} is a string that is either a valid value for attribute | |
7712 | @var{name}, a comma-separated list of values, or @samp{!} followed by a | |
7713 | value or list. If @var{value} does not begin with a @samp{!}, this | |
7714 | test is true if the value of the @var{name} attribute of the current | |
7715 | insn is in the list specified by @var{value}. If @var{value} begins | |
7716 | with a @samp{!}, this test is true if the attribute's value is | |
7717 | @emph{not} in the specified list. | |
7718 | ||
7719 | For example, | |
7720 | ||
7721 | @smallexample | |
7722 | (eq_attr "type" "load,store") | |
7723 | @end smallexample | |
7724 | ||
7725 | @noindent | |
7726 | is equivalent to | |
7727 | ||
7728 | @smallexample | |
7729 | (ior (eq_attr "type" "load") (eq_attr "type" "store")) | |
7730 | @end smallexample | |
7731 | ||
7732 | If @var{name} specifies an attribute of @samp{alternative}, it refers to the | |
7733 | value of the compiler variable @code{which_alternative} | |
7734 | (@pxref{Output Statement}) and the values must be small integers. For | |
bd819a4a | 7735 | example, |
03dda8e3 RK |
7736 | |
7737 | @smallexample | |
7738 | (eq_attr "alternative" "2,3") | |
7739 | @end smallexample | |
7740 | ||
7741 | @noindent | |
7742 | is equivalent to | |
7743 | ||
7744 | @smallexample | |
7745 | (ior (eq (symbol_ref "which_alternative") (const_int 2)) | |
7746 | (eq (symbol_ref "which_alternative") (const_int 3))) | |
7747 | @end smallexample | |
7748 | ||
7749 | Note that, for most attributes, an @code{eq_attr} test is simplified in cases | |
7750 | where the value of the attribute being tested is known for all insns matching | |
bd819a4a | 7751 | a particular pattern. This is by far the most common case. |
03dda8e3 RK |
7752 | |
7753 | @findex attr_flag | |
7754 | @item (attr_flag @var{name}) | |
7755 | The value of an @code{attr_flag} expression is true if the flag | |
7756 | specified by @var{name} is true for the @code{insn} currently being | |
7757 | scheduled. | |
7758 | ||
7759 | @var{name} is a string specifying one of a fixed set of flags to test. | |
7760 | Test the flags @code{forward} and @code{backward} to determine the | |
81e7aa8e | 7761 | direction of a conditional branch. |
03dda8e3 RK |
7762 | |
7763 | This example describes a conditional branch delay slot which | |
7764 | can be nullified for forward branches that are taken (annul-true) or | |
7765 | for backward branches which are not taken (annul-false). | |
7766 | ||
7767 | @smallexample | |
7768 | (define_delay (eq_attr "type" "cbranch") | |
7769 | [(eq_attr "in_branch_delay" "true") | |
7770 | (and (eq_attr "in_branch_delay" "true") | |
7771 | (attr_flag "forward")) | |
7772 | (and (eq_attr "in_branch_delay" "true") | |
7773 | (attr_flag "backward"))]) | |
7774 | @end smallexample | |
7775 | ||
7776 | The @code{forward} and @code{backward} flags are false if the current | |
7777 | @code{insn} being scheduled is not a conditional branch. | |
7778 | ||
03dda8e3 RK |
7779 | @code{attr_flag} is only used during delay slot scheduling and has no |
7780 | meaning to other passes of the compiler. | |
00bc45c1 RH |
7781 | |
7782 | @findex attr | |
7783 | @item (attr @var{name}) | |
7784 | The value of another attribute is returned. This is most useful | |
7785 | for numeric attributes, as @code{eq_attr} and @code{attr_flag} | |
7786 | produce more efficient code for non-numeric attributes. | |
03dda8e3 RK |
7787 | @end table |
7788 | ||
a5249a21 HPN |
7789 | @end ifset |
7790 | @ifset INTERNALS | |
03dda8e3 RK |
7791 | @node Tagging Insns |
7792 | @subsection Assigning Attribute Values to Insns | |
7793 | @cindex tagging insns | |
7794 | @cindex assigning attribute values to insns | |
7795 | ||
7796 | The value assigned to an attribute of an insn is primarily determined by | |
7797 | which pattern is matched by that insn (or which @code{define_peephole} | |
7798 | generated it). Every @code{define_insn} and @code{define_peephole} can | |
7799 | have an optional last argument to specify the values of attributes for | |
7800 | matching insns. The value of any attribute not specified in a particular | |
7801 | insn is set to the default value for that attribute, as specified in its | |
7802 | @code{define_attr}. Extensive use of default values for attributes | |
7803 | permits the specification of the values for only one or two attributes | |
7804 | in the definition of most insn patterns, as seen in the example in the | |
bd819a4a | 7805 | next section. |
03dda8e3 RK |
7806 | |
7807 | The optional last argument of @code{define_insn} and | |
7808 | @code{define_peephole} is a vector of expressions, each of which defines | |
7809 | the value for a single attribute. The most general way of assigning an | |
7810 | attribute's value is to use a @code{set} expression whose first operand is an | |
7811 | @code{attr} expression giving the name of the attribute being set. The | |
7812 | second operand of the @code{set} is an attribute expression | |
bd819a4a | 7813 | (@pxref{Expressions}) giving the value of the attribute. |
03dda8e3 RK |
7814 | |
7815 | When the attribute value depends on the @samp{alternative} attribute | |
7816 | (i.e., which is the applicable alternative in the constraint of the | |
7817 | insn), the @code{set_attr_alternative} expression can be used. It | |
7818 | allows the specification of a vector of attribute expressions, one for | |
7819 | each alternative. | |
7820 | ||
7821 | @findex set_attr | |
7822 | When the generality of arbitrary attribute expressions is not required, | |
7823 | the simpler @code{set_attr} expression can be used, which allows | |
7824 | specifying a string giving either a single attribute value or a list | |
7825 | of attribute values, one for each alternative. | |
7826 | ||
7827 | The form of each of the above specifications is shown below. In each case, | |
7828 | @var{name} is a string specifying the attribute to be set. | |
7829 | ||
7830 | @table @code | |
7831 | @item (set_attr @var{name} @var{value-string}) | |
7832 | @var{value-string} is either a string giving the desired attribute value, | |
7833 | or a string containing a comma-separated list giving the values for | |
7834 | succeeding alternatives. The number of elements must match the number | |
7835 | of alternatives in the constraint of the insn pattern. | |
7836 | ||
7837 | Note that it may be useful to specify @samp{*} for some alternative, in | |
7838 | which case the attribute will assume its default value for insns matching | |
7839 | that alternative. | |
7840 | ||
7841 | @findex set_attr_alternative | |
7842 | @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}]) | |
7843 | Depending on the alternative of the insn, the value will be one of the | |
7844 | specified values. This is a shorthand for using a @code{cond} with | |
7845 | tests on the @samp{alternative} attribute. | |
7846 | ||
7847 | @findex attr | |
7848 | @item (set (attr @var{name}) @var{value}) | |
7849 | The first operand of this @code{set} must be the special RTL expression | |
7850 | @code{attr}, whose sole operand is a string giving the name of the | |
7851 | attribute being set. @var{value} is the value of the attribute. | |
7852 | @end table | |
7853 | ||
7854 | The following shows three different ways of representing the same | |
7855 | attribute value specification: | |
7856 | ||
7857 | @smallexample | |
7858 | (set_attr "type" "load,store,arith") | |
7859 | ||
7860 | (set_attr_alternative "type" | |
7861 | [(const_string "load") (const_string "store") | |
7862 | (const_string "arith")]) | |
7863 | ||
7864 | (set (attr "type") | |
7865 | (cond [(eq_attr "alternative" "1") (const_string "load") | |
7866 | (eq_attr "alternative" "2") (const_string "store")] | |
7867 | (const_string "arith"))) | |
7868 | @end smallexample | |
7869 | ||
7870 | @need 1000 | |
7871 | @findex define_asm_attributes | |
7872 | The @code{define_asm_attributes} expression provides a mechanism to | |
7873 | specify the attributes assigned to insns produced from an @code{asm} | |
7874 | statement. It has the form: | |
7875 | ||
7876 | @smallexample | |
7877 | (define_asm_attributes [@var{attr-sets}]) | |
7878 | @end smallexample | |
7879 | ||
7880 | @noindent | |
7881 | where @var{attr-sets} is specified the same as for both the | |
7882 | @code{define_insn} and the @code{define_peephole} expressions. | |
7883 | ||
7884 | These values will typically be the ``worst case'' attribute values. For | |
7885 | example, they might indicate that the condition code will be clobbered. | |
7886 | ||
7887 | A specification for a @code{length} attribute is handled specially. The | |
7888 | way to compute the length of an @code{asm} insn is to multiply the | |
7889 | length specified in the expression @code{define_asm_attributes} by the | |
7890 | number of machine instructions specified in the @code{asm} statement, | |
7891 | determined by counting the number of semicolons and newlines in the | |
7892 | string. Therefore, the value of the @code{length} attribute specified | |
7893 | in a @code{define_asm_attributes} should be the maximum possible length | |
7894 | of a single machine instruction. | |
7895 | ||
a5249a21 HPN |
7896 | @end ifset |
7897 | @ifset INTERNALS | |
03dda8e3 RK |
7898 | @node Attr Example |
7899 | @subsection Example of Attribute Specifications | |
7900 | @cindex attribute specifications example | |
7901 | @cindex attribute specifications | |
7902 | ||
7903 | The judicious use of defaulting is important in the efficient use of | |
7904 | insn attributes. Typically, insns are divided into @dfn{types} and an | |
7905 | attribute, customarily called @code{type}, is used to represent this | |
7906 | value. This attribute is normally used only to define the default value | |
7907 | for other attributes. An example will clarify this usage. | |
7908 | ||
7909 | Assume we have a RISC machine with a condition code and in which only | |
7910 | full-word operations are performed in registers. Let us assume that we | |
7911 | can divide all insns into loads, stores, (integer) arithmetic | |
7912 | operations, floating point operations, and branches. | |
7913 | ||
7914 | Here we will concern ourselves with determining the effect of an insn on | |
7915 | the condition code and will limit ourselves to the following possible | |
7916 | effects: The condition code can be set unpredictably (clobbered), not | |
7917 | be changed, be set to agree with the results of the operation, or only | |
7918 | changed if the item previously set into the condition code has been | |
7919 | modified. | |
7920 | ||
7921 | Here is part of a sample @file{md} file for such a machine: | |
7922 | ||
7923 | @smallexample | |
7924 | (define_attr "type" "load,store,arith,fp,branch" (const_string "arith")) | |
7925 | ||
7926 | (define_attr "cc" "clobber,unchanged,set,change0" | |
7927 | (cond [(eq_attr "type" "load") | |
7928 | (const_string "change0") | |
7929 | (eq_attr "type" "store,branch") | |
7930 | (const_string "unchanged") | |
7931 | (eq_attr "type" "arith") | |
7932 | (if_then_else (match_operand:SI 0 "" "") | |
7933 | (const_string "set") | |
7934 | (const_string "clobber"))] | |
7935 | (const_string "clobber"))) | |
7936 | ||
7937 | (define_insn "" | |
7938 | [(set (match_operand:SI 0 "general_operand" "=r,r,m") | |
7939 | (match_operand:SI 1 "general_operand" "r,m,r"))] | |
7940 | "" | |
7941 | "@@ | |
7942 | move %0,%1 | |
7943 | load %0,%1 | |
7944 | store %0,%1" | |
7945 | [(set_attr "type" "arith,load,store")]) | |
7946 | @end smallexample | |
7947 | ||
7948 | Note that we assume in the above example that arithmetic operations | |
7949 | performed on quantities smaller than a machine word clobber the condition | |
7950 | code since they will set the condition code to a value corresponding to the | |
7951 | full-word result. | |
7952 | ||
a5249a21 HPN |
7953 | @end ifset |
7954 | @ifset INTERNALS | |
03dda8e3 RK |
7955 | @node Insn Lengths |
7956 | @subsection Computing the Length of an Insn | |
7957 | @cindex insn lengths, computing | |
7958 | @cindex computing the length of an insn | |
7959 | ||
7960 | For many machines, multiple types of branch instructions are provided, each | |
7961 | for different length branch displacements. In most cases, the assembler | |
7962 | will choose the correct instruction to use. However, when the assembler | |
b49900cc | 7963 | cannot do so, GCC can when a special attribute, the @code{length} |
03dda8e3 RK |
7964 | attribute, is defined. This attribute must be defined to have numeric |
7965 | values by specifying a null string in its @code{define_attr}. | |
7966 | ||
b49900cc | 7967 | In the case of the @code{length} attribute, two additional forms of |
03dda8e3 RK |
7968 | arithmetic terms are allowed in test expressions: |
7969 | ||
7970 | @table @code | |
7971 | @cindex @code{match_dup} and attributes | |
7972 | @item (match_dup @var{n}) | |
7973 | This refers to the address of operand @var{n} of the current insn, which | |
7974 | must be a @code{label_ref}. | |
7975 | ||
7976 | @cindex @code{pc} and attributes | |
7977 | @item (pc) | |
7978 | This refers to the address of the @emph{current} insn. It might have | |
7979 | been more consistent with other usage to make this the address of the | |
7980 | @emph{next} insn but this would be confusing because the length of the | |
7981 | current insn is to be computed. | |
7982 | @end table | |
7983 | ||
7984 | @cindex @code{addr_vec}, length of | |
7985 | @cindex @code{addr_diff_vec}, length of | |
7986 | For normal insns, the length will be determined by value of the | |
b49900cc | 7987 | @code{length} attribute. In the case of @code{addr_vec} and |
03dda8e3 RK |
7988 | @code{addr_diff_vec} insn patterns, the length is computed as |
7989 | the number of vectors multiplied by the size of each vector. | |
7990 | ||
7991 | Lengths are measured in addressable storage units (bytes). | |
7992 | ||
7993 | The following macros can be used to refine the length computation: | |
7994 | ||
7995 | @table @code | |
03dda8e3 RK |
7996 | @findex ADJUST_INSN_LENGTH |
7997 | @item ADJUST_INSN_LENGTH (@var{insn}, @var{length}) | |
7998 | If defined, modifies the length assigned to instruction @var{insn} as a | |
7999 | function of the context in which it is used. @var{length} is an lvalue | |
8000 | that contains the initially computed length of the insn and should be | |
a8aa4e0b | 8001 | updated with the correct length of the insn. |
03dda8e3 RK |
8002 | |
8003 | This macro will normally not be required. A case in which it is | |
161d7b59 | 8004 | required is the ROMP@. On this machine, the size of an @code{addr_vec} |
03dda8e3 RK |
8005 | insn must be increased by two to compensate for the fact that alignment |
8006 | may be required. | |
8007 | @end table | |
8008 | ||
8009 | @findex get_attr_length | |
8010 | The routine that returns @code{get_attr_length} (the value of the | |
8011 | @code{length} attribute) can be used by the output routine to | |
8012 | determine the form of the branch instruction to be written, as the | |
8013 | example below illustrates. | |
8014 | ||
8015 | As an example of the specification of variable-length branches, consider | |
8016 | the IBM 360. If we adopt the convention that a register will be set to | |
8017 | the starting address of a function, we can jump to labels within 4k of | |
8018 | the start using a four-byte instruction. Otherwise, we need a six-byte | |
8019 | sequence to load the address from memory and then branch to it. | |
8020 | ||
8021 | On such a machine, a pattern for a branch instruction might be specified | |
8022 | as follows: | |
8023 | ||
8024 | @smallexample | |
8025 | (define_insn "jump" | |
8026 | [(set (pc) | |
8027 | (label_ref (match_operand 0 "" "")))] | |
8028 | "" | |
03dda8e3 RK |
8029 | @{ |
8030 | return (get_attr_length (insn) == 4 | |
0f40f9f7 ZW |
8031 | ? "b %l0" : "l r15,=a(%l0); br r15"); |
8032 | @} | |
9c34dbbf ZW |
8033 | [(set (attr "length") |
8034 | (if_then_else (lt (match_dup 0) (const_int 4096)) | |
8035 | (const_int 4) | |
8036 | (const_int 6)))]) | |
03dda8e3 RK |
8037 | @end smallexample |
8038 | ||
a5249a21 HPN |
8039 | @end ifset |
8040 | @ifset INTERNALS | |
03dda8e3 RK |
8041 | @node Constant Attributes |
8042 | @subsection Constant Attributes | |
8043 | @cindex constant attributes | |
8044 | ||
8045 | A special form of @code{define_attr}, where the expression for the | |
8046 | default value is a @code{const} expression, indicates an attribute that | |
8047 | is constant for a given run of the compiler. Constant attributes may be | |
8048 | used to specify which variety of processor is used. For example, | |
8049 | ||
8050 | @smallexample | |
8051 | (define_attr "cpu" "m88100,m88110,m88000" | |
8052 | (const | |
8053 | (cond [(symbol_ref "TARGET_88100") (const_string "m88100") | |
8054 | (symbol_ref "TARGET_88110") (const_string "m88110")] | |
8055 | (const_string "m88000")))) | |
8056 | ||
8057 | (define_attr "memory" "fast,slow" | |
8058 | (const | |
8059 | (if_then_else (symbol_ref "TARGET_FAST_MEM") | |
8060 | (const_string "fast") | |
8061 | (const_string "slow")))) | |
8062 | @end smallexample | |
8063 | ||
8064 | The routine generated for constant attributes has no parameters as it | |
8065 | does not depend on any particular insn. RTL expressions used to define | |
8066 | the value of a constant attribute may use the @code{symbol_ref} form, | |
8067 | but may not use either the @code{match_operand} form or @code{eq_attr} | |
8068 | forms involving insn attributes. | |
8069 | ||
a5249a21 HPN |
8070 | @end ifset |
8071 | @ifset INTERNALS | |
03dda8e3 RK |
8072 | @node Delay Slots |
8073 | @subsection Delay Slot Scheduling | |
8074 | @cindex delay slots, defining | |
8075 | ||
8076 | The insn attribute mechanism can be used to specify the requirements for | |
8077 | delay slots, if any, on a target machine. An instruction is said to | |
8078 | require a @dfn{delay slot} if some instructions that are physically | |
8079 | after the instruction are executed as if they were located before it. | |
8080 | Classic examples are branch and call instructions, which often execute | |
8081 | the following instruction before the branch or call is performed. | |
8082 | ||
8083 | On some machines, conditional branch instructions can optionally | |
8084 | @dfn{annul} instructions in the delay slot. This means that the | |
8085 | instruction will not be executed for certain branch outcomes. Both | |
8086 | instructions that annul if the branch is true and instructions that | |
8087 | annul if the branch is false are supported. | |
8088 | ||
8089 | Delay slot scheduling differs from instruction scheduling in that | |
8090 | determining whether an instruction needs a delay slot is dependent only | |
8091 | on the type of instruction being generated, not on data flow between the | |
8092 | instructions. See the next section for a discussion of data-dependent | |
8093 | instruction scheduling. | |
8094 | ||
8095 | @findex define_delay | |
8096 | The requirement of an insn needing one or more delay slots is indicated | |
8097 | via the @code{define_delay} expression. It has the following form: | |
8098 | ||
8099 | @smallexample | |
8100 | (define_delay @var{test} | |
8101 | [@var{delay-1} @var{annul-true-1} @var{annul-false-1} | |
8102 | @var{delay-2} @var{annul-true-2} @var{annul-false-2} | |
8103 | @dots{}]) | |
8104 | @end smallexample | |
8105 | ||
8106 | @var{test} is an attribute test that indicates whether this | |
8107 | @code{define_delay} applies to a particular insn. If so, the number of | |
8108 | required delay slots is determined by the length of the vector specified | |
8109 | as the second argument. An insn placed in delay slot @var{n} must | |
8110 | satisfy attribute test @var{delay-n}. @var{annul-true-n} is an | |
8111 | attribute test that specifies which insns may be annulled if the branch | |
8112 | is true. Similarly, @var{annul-false-n} specifies which insns in the | |
8113 | delay slot may be annulled if the branch is false. If annulling is not | |
bd819a4a | 8114 | supported for that delay slot, @code{(nil)} should be coded. |
03dda8e3 RK |
8115 | |
8116 | For example, in the common case where branch and call insns require | |
8117 | a single delay slot, which may contain any insn other than a branch or | |
8118 | call, the following would be placed in the @file{md} file: | |
8119 | ||
8120 | @smallexample | |
8121 | (define_delay (eq_attr "type" "branch,call") | |
8122 | [(eq_attr "type" "!branch,call") (nil) (nil)]) | |
8123 | @end smallexample | |
8124 | ||
8125 | Multiple @code{define_delay} expressions may be specified. In this | |
8126 | case, each such expression specifies different delay slot requirements | |
8127 | and there must be no insn for which tests in two @code{define_delay} | |
8128 | expressions are both true. | |
8129 | ||
8130 | For example, if we have a machine that requires one delay slot for branches | |
8131 | but two for calls, no delay slot can contain a branch or call insn, | |
8132 | and any valid insn in the delay slot for the branch can be annulled if the | |
8133 | branch is true, we might represent this as follows: | |
8134 | ||
8135 | @smallexample | |
8136 | (define_delay (eq_attr "type" "branch") | |
8137 | [(eq_attr "type" "!branch,call") | |
8138 | (eq_attr "type" "!branch,call") | |
8139 | (nil)]) | |
8140 | ||
8141 | (define_delay (eq_attr "type" "call") | |
8142 | [(eq_attr "type" "!branch,call") (nil) (nil) | |
8143 | (eq_attr "type" "!branch,call") (nil) (nil)]) | |
8144 | @end smallexample | |
8145 | @c the above is *still* too long. --mew 4feb93 | |
8146 | ||
a5249a21 HPN |
8147 | @end ifset |
8148 | @ifset INTERNALS | |
fae15c93 VM |
8149 | @node Processor pipeline description |
8150 | @subsection Specifying processor pipeline description | |
8151 | @cindex processor pipeline description | |
8152 | @cindex processor functional units | |
8153 | @cindex instruction latency time | |
8154 | @cindex interlock delays | |
8155 | @cindex data dependence delays | |
8156 | @cindex reservation delays | |
8157 | @cindex pipeline hazard recognizer | |
8158 | @cindex automaton based pipeline description | |
8159 | @cindex regular expressions | |
8160 | @cindex deterministic finite state automaton | |
8161 | @cindex automaton based scheduler | |
8162 | @cindex RISC | |
8163 | @cindex VLIW | |
8164 | ||
ef261fee | 8165 | To achieve better performance, most modern processors |
fae15c93 VM |
8166 | (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW} |
8167 | processors) have many @dfn{functional units} on which several | |
8168 | instructions can be executed simultaneously. An instruction starts | |
8169 | execution if its issue conditions are satisfied. If not, the | |
ef261fee | 8170 | instruction is stalled until its conditions are satisfied. Such |
fae15c93 | 8171 | @dfn{interlock (pipeline) delay} causes interruption of the fetching |
431ae0bf | 8172 | of successor instructions (or demands nop instructions, e.g.@: for some |
fae15c93 VM |
8173 | MIPS processors). |
8174 | ||
8175 | There are two major kinds of interlock delays in modern processors. | |
8176 | The first one is a data dependence delay determining @dfn{instruction | |
8177 | latency time}. The instruction execution is not started until all | |
8178 | source data have been evaluated by prior instructions (there are more | |
8179 | complex cases when the instruction execution starts even when the data | |
c0478a66 | 8180 | are not available but will be ready in given time after the |
fae15c93 VM |
8181 | instruction execution start). Taking the data dependence delays into |
8182 | account is simple. The data dependence (true, output, and | |
8183 | anti-dependence) delay between two instructions is given by a | |
8184 | constant. In most cases this approach is adequate. The second kind | |
8185 | of interlock delays is a reservation delay. The reservation delay | |
8186 | means that two instructions under execution will be in need of shared | |
431ae0bf | 8187 | processors resources, i.e.@: buses, internal registers, and/or |
fae15c93 VM |
8188 | functional units, which are reserved for some time. Taking this kind |
8189 | of delay into account is complex especially for modern @acronym{RISC} | |
8190 | processors. | |
8191 | ||
8192 | The task of exploiting more processor parallelism is solved by an | |
ef261fee | 8193 | instruction scheduler. For a better solution to this problem, the |
fae15c93 | 8194 | instruction scheduler has to have an adequate description of the |
fa0aee89 PB |
8195 | processor parallelism (or @dfn{pipeline description}). GCC |
8196 | machine descriptions describe processor parallelism and functional | |
8197 | unit reservations for groups of instructions with the aid of | |
8198 | @dfn{regular expressions}. | |
ef261fee R |
8199 | |
8200 | The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to | |
fae15c93 | 8201 | figure out the possibility of the instruction issue by the processor |
ef261fee R |
8202 | on a given simulated processor cycle. The pipeline hazard recognizer is |
8203 | automatically generated from the processor pipeline description. The | |
fa0aee89 PB |
8204 | pipeline hazard recognizer generated from the machine description |
8205 | is based on a deterministic finite state automaton (@acronym{DFA}): | |
8206 | the instruction issue is possible if there is a transition from one | |
8207 | automaton state to another one. This algorithm is very fast, and | |
8208 | furthermore, its speed is not dependent on processor | |
8209 | complexity@footnote{However, the size of the automaton depends on | |
6ccde948 RW |
8210 | processor complexity. To limit this effect, machine descriptions |
8211 | can split orthogonal parts of the machine description among several | |
8212 | automata: but then, since each of these must be stepped independently, | |
8213 | this does cause a small decrease in the algorithm's performance.}. | |
fae15c93 | 8214 | |
fae15c93 | 8215 | @cindex automaton based pipeline description |
fa0aee89 PB |
8216 | The rest of this section describes the directives that constitute |
8217 | an automaton-based processor pipeline description. The order of | |
8218 | these constructions within the machine description file is not | |
8219 | important. | |
fae15c93 VM |
8220 | |
8221 | @findex define_automaton | |
8222 | @cindex pipeline hazard recognizer | |
8223 | The following optional construction describes names of automata | |
8224 | generated and used for the pipeline hazards recognition. Sometimes | |
8225 | the generated finite state automaton used by the pipeline hazard | |
ef261fee | 8226 | recognizer is large. If we use more than one automaton and bind functional |
daf2f129 | 8227 | units to the automata, the total size of the automata is usually |
fae15c93 VM |
8228 | less than the size of the single automaton. If there is no one such |
8229 | construction, only one finite state automaton is generated. | |
8230 | ||
8231 | @smallexample | |
8232 | (define_automaton @var{automata-names}) | |
8233 | @end smallexample | |
8234 | ||
8235 | @var{automata-names} is a string giving names of the automata. The | |
8236 | names are separated by commas. All the automata should have unique names. | |
c62347f0 | 8237 | The automaton name is used in the constructions @code{define_cpu_unit} and |
fae15c93 VM |
8238 | @code{define_query_cpu_unit}. |
8239 | ||
8240 | @findex define_cpu_unit | |
8241 | @cindex processor functional units | |
c62347f0 | 8242 | Each processor functional unit used in the description of instruction |
fae15c93 VM |
8243 | reservations should be described by the following construction. |
8244 | ||
8245 | @smallexample | |
8246 | (define_cpu_unit @var{unit-names} [@var{automaton-name}]) | |
8247 | @end smallexample | |
8248 | ||
8249 | @var{unit-names} is a string giving the names of the functional units | |
8250 | separated by commas. Don't use name @samp{nothing}, it is reserved | |
8251 | for other goals. | |
8252 | ||
ef261fee | 8253 | @var{automaton-name} is a string giving the name of the automaton with |
fae15c93 VM |
8254 | which the unit is bound. The automaton should be described in |
8255 | construction @code{define_automaton}. You should give | |
8256 | @dfn{automaton-name}, if there is a defined automaton. | |
8257 | ||
30028c85 VM |
8258 | The assignment of units to automata are constrained by the uses of the |
8259 | units in insn reservations. The most important constraint is: if a | |
8260 | unit reservation is present on a particular cycle of an alternative | |
8261 | for an insn reservation, then some unit from the same automaton must | |
8262 | be present on the same cycle for the other alternatives of the insn | |
8263 | reservation. The rest of the constraints are mentioned in the | |
8264 | description of the subsequent constructions. | |
8265 | ||
fae15c93 VM |
8266 | @findex define_query_cpu_unit |
8267 | @cindex querying function unit reservations | |
8268 | The following construction describes CPU functional units analogously | |
30028c85 VM |
8269 | to @code{define_cpu_unit}. The reservation of such units can be |
8270 | queried for an automaton state. The instruction scheduler never | |
8271 | queries reservation of functional units for given automaton state. So | |
8272 | as a rule, you don't need this construction. This construction could | |
431ae0bf | 8273 | be used for future code generation goals (e.g.@: to generate |
30028c85 | 8274 | @acronym{VLIW} insn templates). |
fae15c93 VM |
8275 | |
8276 | @smallexample | |
8277 | (define_query_cpu_unit @var{unit-names} [@var{automaton-name}]) | |
8278 | @end smallexample | |
8279 | ||
8280 | @var{unit-names} is a string giving names of the functional units | |
8281 | separated by commas. | |
8282 | ||
ef261fee | 8283 | @var{automaton-name} is a string giving the name of the automaton with |
fae15c93 VM |
8284 | which the unit is bound. |
8285 | ||
8286 | @findex define_insn_reservation | |
8287 | @cindex instruction latency time | |
8288 | @cindex regular expressions | |
8289 | @cindex data bypass | |
ef261fee | 8290 | The following construction is the major one to describe pipeline |
fae15c93 VM |
8291 | characteristics of an instruction. |
8292 | ||
8293 | @smallexample | |
8294 | (define_insn_reservation @var{insn-name} @var{default_latency} | |
8295 | @var{condition} @var{regexp}) | |
8296 | @end smallexample | |
8297 | ||
8298 | @var{default_latency} is a number giving latency time of the | |
8299 | instruction. There is an important difference between the old | |
8300 | description and the automaton based pipeline description. The latency | |
8301 | time is used for all dependencies when we use the old description. In | |
ef261fee R |
8302 | the automaton based pipeline description, the given latency time is only |
8303 | used for true dependencies. The cost of anti-dependencies is always | |
fae15c93 VM |
8304 | zero and the cost of output dependencies is the difference between |
8305 | latency times of the producing and consuming insns (if the difference | |
ef261fee R |
8306 | is negative, the cost is considered to be zero). You can always |
8307 | change the default costs for any description by using the target hook | |
fae15c93 VM |
8308 | @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}). |
8309 | ||
cc6a602b | 8310 | @var{insn-name} is a string giving the internal name of the insn. The |
fae15c93 VM |
8311 | internal names are used in constructions @code{define_bypass} and in |
8312 | the automaton description file generated for debugging. The internal | |
ef261fee | 8313 | name has nothing in common with the names in @code{define_insn}. It is a |
fae15c93 VM |
8314 | good practice to use insn classes described in the processor manual. |
8315 | ||
8316 | @var{condition} defines what RTL insns are described by this | |
8317 | construction. You should remember that you will be in trouble if | |
8318 | @var{condition} for two or more different | |
8319 | @code{define_insn_reservation} constructions is TRUE for an insn. In | |
8320 | this case what reservation will be used for the insn is not defined. | |
8321 | Such cases are not checked during generation of the pipeline hazards | |
8322 | recognizer because in general recognizing that two conditions may have | |
8323 | the same value is quite difficult (especially if the conditions | |
8324 | contain @code{symbol_ref}). It is also not checked during the | |
8325 | pipeline hazard recognizer work because it would slow down the | |
8326 | recognizer considerably. | |
8327 | ||
ef261fee | 8328 | @var{regexp} is a string describing the reservation of the cpu's functional |
fae15c93 VM |
8329 | units by the instruction. The reservations are described by a regular |
8330 | expression according to the following syntax: | |
8331 | ||
8332 | @smallexample | |
8333 | regexp = regexp "," oneof | |
8334 | | oneof | |
8335 | ||
8336 | oneof = oneof "|" allof | |
8337 | | allof | |
8338 | ||
8339 | allof = allof "+" repeat | |
8340 | | repeat | |
daf2f129 | 8341 | |
fae15c93 VM |
8342 | repeat = element "*" number |
8343 | | element | |
8344 | ||
8345 | element = cpu_function_unit_name | |
8346 | | reservation_name | |
8347 | | result_name | |
8348 | | "nothing" | |
8349 | | "(" regexp ")" | |
8350 | @end smallexample | |
8351 | ||
8352 | @itemize @bullet | |
8353 | @item | |
8354 | @samp{,} is used for describing the start of the next cycle in | |
8355 | the reservation. | |
8356 | ||
8357 | @item | |
8358 | @samp{|} is used for describing a reservation described by the first | |
8359 | regular expression @strong{or} a reservation described by the second | |
8360 | regular expression @strong{or} etc. | |
8361 | ||
8362 | @item | |
8363 | @samp{+} is used for describing a reservation described by the first | |
8364 | regular expression @strong{and} a reservation described by the | |
8365 | second regular expression @strong{and} etc. | |
8366 | ||
8367 | @item | |
8368 | @samp{*} is used for convenience and simply means a sequence in which | |
8369 | the regular expression are repeated @var{number} times with cycle | |
8370 | advancing (see @samp{,}). | |
8371 | ||
8372 | @item | |
8373 | @samp{cpu_function_unit_name} denotes reservation of the named | |
8374 | functional unit. | |
8375 | ||
8376 | @item | |
8377 | @samp{reservation_name} --- see description of construction | |
8378 | @samp{define_reservation}. | |
8379 | ||
8380 | @item | |
8381 | @samp{nothing} denotes no unit reservations. | |
8382 | @end itemize | |
8383 | ||
8384 | @findex define_reservation | |
8385 | Sometimes unit reservations for different insns contain common parts. | |
8386 | In such case, you can simplify the pipeline description by describing | |
8387 | the common part by the following construction | |
8388 | ||
8389 | @smallexample | |
8390 | (define_reservation @var{reservation-name} @var{regexp}) | |
8391 | @end smallexample | |
8392 | ||
8393 | @var{reservation-name} is a string giving name of @var{regexp}. | |
8394 | Functional unit names and reservation names are in the same name | |
8395 | space. So the reservation names should be different from the | |
cc6a602b | 8396 | functional unit names and can not be the reserved name @samp{nothing}. |
fae15c93 VM |
8397 | |
8398 | @findex define_bypass | |
8399 | @cindex instruction latency time | |
8400 | @cindex data bypass | |
8401 | The following construction is used to describe exceptions in the | |
8402 | latency time for given instruction pair. This is so called bypasses. | |
8403 | ||
8404 | @smallexample | |
8405 | (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names} | |
8406 | [@var{guard}]) | |
8407 | @end smallexample | |
8408 | ||
8409 | @var{number} defines when the result generated by the instructions | |
8410 | given in string @var{out_insn_names} will be ready for the | |
f9bf5a8e RS |
8411 | instructions given in string @var{in_insn_names}. Each of these |
8412 | strings is a comma-separated list of filename-style globs and | |
8413 | they refer to the names of @code{define_insn_reservation}s. | |
8414 | For example: | |
8415 | @smallexample | |
8416 | (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*") | |
8417 | @end smallexample | |
8418 | defines a bypass between instructions that start with | |
8419 | @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with | |
8420 | @samp{cpu1_load_}. | |
fae15c93 | 8421 | |
ef261fee | 8422 | @var{guard} is an optional string giving the name of a C function which |
fae15c93 VM |
8423 | defines an additional guard for the bypass. The function will get the |
8424 | two insns as parameters. If the function returns zero the bypass will | |
8425 | be ignored for this case. The additional guard is necessary to | |
431ae0bf | 8426 | recognize complicated bypasses, e.g.@: when the consumer is only an address |
fae15c93 VM |
8427 | of insn @samp{store} (not a stored value). |
8428 | ||
20a07f44 VM |
8429 | If there are more one bypass with the same output and input insns, the |
8430 | chosen bypass is the first bypass with a guard in description whose | |
8431 | guard function returns nonzero. If there is no such bypass, then | |
8432 | bypass without the guard function is chosen. | |
8433 | ||
fae15c93 VM |
8434 | @findex exclusion_set |
8435 | @findex presence_set | |
30028c85 | 8436 | @findex final_presence_set |
fae15c93 | 8437 | @findex absence_set |
30028c85 | 8438 | @findex final_absence_set |
fae15c93 VM |
8439 | @cindex VLIW |
8440 | @cindex RISC | |
cc6a602b BE |
8441 | The following five constructions are usually used to describe |
8442 | @acronym{VLIW} processors, or more precisely, to describe a placement | |
8443 | of small instructions into @acronym{VLIW} instruction slots. They | |
8444 | can be used for @acronym{RISC} processors, too. | |
fae15c93 VM |
8445 | |
8446 | @smallexample | |
8447 | (exclusion_set @var{unit-names} @var{unit-names}) | |
30028c85 VM |
8448 | (presence_set @var{unit-names} @var{patterns}) |
8449 | (final_presence_set @var{unit-names} @var{patterns}) | |
8450 | (absence_set @var{unit-names} @var{patterns}) | |
8451 | (final_absence_set @var{unit-names} @var{patterns}) | |
fae15c93 VM |
8452 | @end smallexample |
8453 | ||
8454 | @var{unit-names} is a string giving names of functional units | |
8455 | separated by commas. | |
8456 | ||
30028c85 | 8457 | @var{patterns} is a string giving patterns of functional units |
0bdcd332 | 8458 | separated by comma. Currently pattern is one unit or units |
30028c85 VM |
8459 | separated by white-spaces. |
8460 | ||
fae15c93 VM |
8461 | The first construction (@samp{exclusion_set}) means that each |
8462 | functional unit in the first string can not be reserved simultaneously | |
8463 | with a unit whose name is in the second string and vice versa. For | |
8464 | example, the construction is useful for describing processors | |
431ae0bf | 8465 | (e.g.@: some SPARC processors) with a fully pipelined floating point |
fae15c93 VM |
8466 | functional unit which can execute simultaneously only single floating |
8467 | point insns or only double floating point insns. | |
8468 | ||
8469 | The second construction (@samp{presence_set}) means that each | |
8470 | functional unit in the first string can not be reserved unless at | |
30028c85 VM |
8471 | least one of pattern of units whose names are in the second string is |
8472 | reserved. This is an asymmetric relation. For example, it is useful | |
8473 | for description that @acronym{VLIW} @samp{slot1} is reserved after | |
8474 | @samp{slot0} reservation. We could describe it by the following | |
8475 | construction | |
8476 | ||
8477 | @smallexample | |
8478 | (presence_set "slot1" "slot0") | |
8479 | @end smallexample | |
8480 | ||
8481 | Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0} | |
8482 | reservation. In this case we could write | |
8483 | ||
8484 | @smallexample | |
8485 | (presence_set "slot1" "slot0 b0") | |
8486 | @end smallexample | |
8487 | ||
8488 | The third construction (@samp{final_presence_set}) is analogous to | |
8489 | @samp{presence_set}. The difference between them is when checking is | |
8490 | done. When an instruction is issued in given automaton state | |
8491 | reflecting all current and planned unit reservations, the automaton | |
8492 | state is changed. The first state is a source state, the second one | |
8493 | is a result state. Checking for @samp{presence_set} is done on the | |
8494 | source state reservation, checking for @samp{final_presence_set} is | |
8495 | done on the result reservation. This construction is useful to | |
8496 | describe a reservation which is actually two subsequent reservations. | |
8497 | For example, if we use | |
8498 | ||
8499 | @smallexample | |
8500 | (presence_set "slot1" "slot0") | |
8501 | @end smallexample | |
8502 | ||
8503 | the following insn will be never issued (because @samp{slot1} requires | |
8504 | @samp{slot0} which is absent in the source state). | |
8505 | ||
8506 | @smallexample | |
8507 | (define_reservation "insn_and_nop" "slot0 + slot1") | |
8508 | @end smallexample | |
8509 | ||
8510 | but it can be issued if we use analogous @samp{final_presence_set}. | |
8511 | ||
8512 | The forth construction (@samp{absence_set}) means that each functional | |
8513 | unit in the first string can be reserved only if each pattern of units | |
8514 | whose names are in the second string is not reserved. This is an | |
8515 | asymmetric relation (actually @samp{exclusion_set} is analogous to | |
ff2ce160 | 8516 | this one but it is symmetric). For example it might be useful in a |
a71b1c58 NC |
8517 | @acronym{VLIW} description to say that @samp{slot0} cannot be reserved |
8518 | after either @samp{slot1} or @samp{slot2} have been reserved. This | |
8519 | can be described as: | |
30028c85 VM |
8520 | |
8521 | @smallexample | |
a71b1c58 | 8522 | (absence_set "slot0" "slot1, slot2") |
30028c85 VM |
8523 | @end smallexample |
8524 | ||
8525 | Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0} | |
8526 | are reserved or @samp{slot1} and unit @samp{b1} are reserved. In | |
8527 | this case we could write | |
8528 | ||
8529 | @smallexample | |
8530 | (absence_set "slot2" "slot0 b0, slot1 b1") | |
8531 | @end smallexample | |
fae15c93 | 8532 | |
ef261fee | 8533 | All functional units mentioned in a set should belong to the same |
fae15c93 VM |
8534 | automaton. |
8535 | ||
30028c85 VM |
8536 | The last construction (@samp{final_absence_set}) is analogous to |
8537 | @samp{absence_set} but checking is done on the result (state) | |
8538 | reservation. See comments for @samp{final_presence_set}. | |
8539 | ||
fae15c93 VM |
8540 | @findex automata_option |
8541 | @cindex deterministic finite state automaton | |
8542 | @cindex nondeterministic finite state automaton | |
8543 | @cindex finite state automaton minimization | |
8544 | You can control the generator of the pipeline hazard recognizer with | |
8545 | the following construction. | |
8546 | ||
8547 | @smallexample | |
8548 | (automata_option @var{options}) | |
8549 | @end smallexample | |
8550 | ||
8551 | @var{options} is a string giving options which affect the generated | |
8552 | code. Currently there are the following options: | |
8553 | ||
8554 | @itemize @bullet | |
8555 | @item | |
8556 | @dfn{no-minimization} makes no minimization of the automaton. This is | |
30028c85 VM |
8557 | only worth to do when we are debugging the description and need to |
8558 | look more accurately at reservations of states. | |
fae15c93 VM |
8559 | |
8560 | @item | |
df1133a6 BE |
8561 | @dfn{time} means printing time statistics about the generation of |
8562 | automata. | |
8563 | ||
8564 | @item | |
8565 | @dfn{stats} means printing statistics about the generated automata | |
8566 | such as the number of DFA states, NDFA states and arcs. | |
e3c8eb86 VM |
8567 | |
8568 | @item | |
8569 | @dfn{v} means a generation of the file describing the result automata. | |
8570 | The file has suffix @samp{.dfa} and can be used for the description | |
8571 | verification and debugging. | |
8572 | ||
8573 | @item | |
8574 | @dfn{w} means a generation of warning instead of error for | |
8575 | non-critical errors. | |
fae15c93 | 8576 | |
e12da141 BS |
8577 | @item |
8578 | @dfn{no-comb-vect} prevents the automaton generator from generating | |
8579 | two data structures and comparing them for space efficiency. Using | |
8580 | a comb vector to represent transitions may be better, but it can be | |
8581 | very expensive to construct. This option is useful if the build | |
8582 | process spends an unacceptably long time in genautomata. | |
8583 | ||
fae15c93 VM |
8584 | @item |
8585 | @dfn{ndfa} makes nondeterministic finite state automata. This affects | |
8586 | the treatment of operator @samp{|} in the regular expressions. The | |
8587 | usual treatment of the operator is to try the first alternative and, | |
8588 | if the reservation is not possible, the second alternative. The | |
8589 | nondeterministic treatment means trying all alternatives, some of them | |
96ddf8ef | 8590 | may be rejected by reservations in the subsequent insns. |
dfa849f3 | 8591 | |
1e6a9047 BS |
8592 | @item |
8593 | @dfn{collapse-ndfa} modifies the behaviour of the generator when | |
8594 | producing an automaton. An additional state transition to collapse a | |
8595 | nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA} | |
8596 | state is generated. It can be triggered by passing @code{const0_rtx} to | |
8597 | state_transition. In such an automaton, cycle advance transitions are | |
8598 | available only for these collapsed states. This option is useful for | |
8599 | ports that want to use the @code{ndfa} option, but also want to use | |
8600 | @code{define_query_cpu_unit} to assign units to insns issued in a cycle. | |
8601 | ||
dfa849f3 VM |
8602 | @item |
8603 | @dfn{progress} means output of a progress bar showing how many states | |
8604 | were generated so far for automaton being processed. This is useful | |
8605 | during debugging a @acronym{DFA} description. If you see too many | |
8606 | generated states, you could interrupt the generator of the pipeline | |
8607 | hazard recognizer and try to figure out a reason for generation of the | |
8608 | huge automaton. | |
fae15c93 VM |
8609 | @end itemize |
8610 | ||
8611 | As an example, consider a superscalar @acronym{RISC} machine which can | |
8612 | issue three insns (two integer insns and one floating point insn) on | |
8613 | the cycle but can finish only two insns. To describe this, we define | |
8614 | the following functional units. | |
8615 | ||
8616 | @smallexample | |
8617 | (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline") | |
ef261fee | 8618 | (define_cpu_unit "port0, port1") |
fae15c93 VM |
8619 | @end smallexample |
8620 | ||
8621 | All simple integer insns can be executed in any integer pipeline and | |
8622 | their result is ready in two cycles. The simple integer insns are | |
8623 | issued into the first pipeline unless it is reserved, otherwise they | |
8624 | are issued into the second pipeline. Integer division and | |
8625 | multiplication insns can be executed only in the second integer | |
8626 | pipeline and their results are ready correspondingly in 8 and 4 | |
431ae0bf | 8627 | cycles. The integer division is not pipelined, i.e.@: the subsequent |
fae15c93 VM |
8628 | integer division insn can not be issued until the current division |
8629 | insn finished. Floating point insns are fully pipelined and their | |
ef261fee R |
8630 | results are ready in 3 cycles. Where the result of a floating point |
8631 | insn is used by an integer insn, an additional delay of one cycle is | |
8632 | incurred. To describe all of this we could specify | |
fae15c93 VM |
8633 | |
8634 | @smallexample | |
8635 | (define_cpu_unit "div") | |
8636 | ||
68e4d4c5 | 8637 | (define_insn_reservation "simple" 2 (eq_attr "type" "int") |
ef261fee | 8638 | "(i0_pipeline | i1_pipeline), (port0 | port1)") |
fae15c93 | 8639 | |
68e4d4c5 | 8640 | (define_insn_reservation "mult" 4 (eq_attr "type" "mult") |
ef261fee | 8641 | "i1_pipeline, nothing*2, (port0 | port1)") |
fae15c93 | 8642 | |
68e4d4c5 | 8643 | (define_insn_reservation "div" 8 (eq_attr "type" "div") |
ef261fee | 8644 | "i1_pipeline, div*7, div + (port0 | port1)") |
fae15c93 | 8645 | |
68e4d4c5 | 8646 | (define_insn_reservation "float" 3 (eq_attr "type" "float") |
ef261fee | 8647 | "f_pipeline, nothing, (port0 | port1)) |
fae15c93 | 8648 | |
ef261fee | 8649 | (define_bypass 4 "float" "simple,mult,div") |
fae15c93 VM |
8650 | @end smallexample |
8651 | ||
8652 | To simplify the description we could describe the following reservation | |
8653 | ||
8654 | @smallexample | |
8655 | (define_reservation "finish" "port0|port1") | |
8656 | @end smallexample | |
8657 | ||
8658 | and use it in all @code{define_insn_reservation} as in the following | |
8659 | construction | |
8660 | ||
8661 | @smallexample | |
68e4d4c5 | 8662 | (define_insn_reservation "simple" 2 (eq_attr "type" "int") |
fae15c93 VM |
8663 | "(i0_pipeline | i1_pipeline), finish") |
8664 | @end smallexample | |
8665 | ||
8666 | ||
a5249a21 HPN |
8667 | @end ifset |
8668 | @ifset INTERNALS | |
3262c1f5 RH |
8669 | @node Conditional Execution |
8670 | @section Conditional Execution | |
8671 | @cindex conditional execution | |
8672 | @cindex predication | |
8673 | ||
8674 | A number of architectures provide for some form of conditional | |
8675 | execution, or predication. The hallmark of this feature is the | |
8676 | ability to nullify most of the instructions in the instruction set. | |
8677 | When the instruction set is large and not entirely symmetric, it | |
8678 | can be quite tedious to describe these forms directly in the | |
8679 | @file{.md} file. An alternative is the @code{define_cond_exec} template. | |
8680 | ||
8681 | @findex define_cond_exec | |
8682 | @smallexample | |
8683 | (define_cond_exec | |
8684 | [@var{predicate-pattern}] | |
8685 | "@var{condition}" | |
630d3d5a | 8686 | "@var{output-template}") |
3262c1f5 RH |
8687 | @end smallexample |
8688 | ||
8689 | @var{predicate-pattern} is the condition that must be true for the | |
8690 | insn to be executed at runtime and should match a relational operator. | |
8691 | One can use @code{match_operator} to match several relational operators | |
8692 | at once. Any @code{match_operand} operands must have no more than one | |
8693 | alternative. | |
8694 | ||
8695 | @var{condition} is a C expression that must be true for the generated | |
8696 | pattern to match. | |
8697 | ||
8698 | @findex current_insn_predicate | |
630d3d5a | 8699 | @var{output-template} is a string similar to the @code{define_insn} |
3262c1f5 RH |
8700 | output template (@pxref{Output Template}), except that the @samp{*} |
8701 | and @samp{@@} special cases do not apply. This is only useful if the | |
8702 | assembly text for the predicate is a simple prefix to the main insn. | |
8703 | In order to handle the general case, there is a global variable | |
8704 | @code{current_insn_predicate} that will contain the entire predicate | |
8705 | if the current insn is predicated, and will otherwise be @code{NULL}. | |
8706 | ||
ebb48a4d JM |
8707 | When @code{define_cond_exec} is used, an implicit reference to |
8708 | the @code{predicable} instruction attribute is made. | |
0bddee8e BS |
8709 | @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have |
8710 | exactly two elements in its @var{list-of-values}), with the possible | |
8711 | values being @code{no} and @code{yes}. The default and all uses in | |
8712 | the insns must be a simple constant, not a complex expressions. It | |
8713 | may, however, depend on the alternative, by using a comma-separated | |
8714 | list of values. If that is the case, the port should also define an | |
8715 | @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which | |
8716 | should also allow only @code{no} and @code{yes} as its values. | |
3262c1f5 | 8717 | |
ebb48a4d | 8718 | For each @code{define_insn} for which the @code{predicable} |
3262c1f5 RH |
8719 | attribute is true, a new @code{define_insn} pattern will be |
8720 | generated that matches a predicated version of the instruction. | |
8721 | For example, | |
8722 | ||
8723 | @smallexample | |
8724 | (define_insn "addsi" | |
8725 | [(set (match_operand:SI 0 "register_operand" "r") | |
8726 | (plus:SI (match_operand:SI 1 "register_operand" "r") | |
8727 | (match_operand:SI 2 "register_operand" "r")))] | |
8728 | "@var{test1}" | |
8729 | "add %2,%1,%0") | |
8730 | ||
8731 | (define_cond_exec | |
8732 | [(ne (match_operand:CC 0 "register_operand" "c") | |
8733 | (const_int 0))] | |
8734 | "@var{test2}" | |
8735 | "(%0)") | |
8736 | @end smallexample | |
8737 | ||
8738 | @noindent | |
8739 | generates a new pattern | |
8740 | ||
8741 | @smallexample | |
8742 | (define_insn "" | |
8743 | [(cond_exec | |
8744 | (ne (match_operand:CC 3 "register_operand" "c") (const_int 0)) | |
8745 | (set (match_operand:SI 0 "register_operand" "r") | |
8746 | (plus:SI (match_operand:SI 1 "register_operand" "r") | |
8747 | (match_operand:SI 2 "register_operand" "r"))))] | |
8748 | "(@var{test2}) && (@var{test1})" | |
8749 | "(%3) add %2,%1,%0") | |
8750 | @end smallexample | |
c25c12b8 | 8751 | |
a5249a21 HPN |
8752 | @end ifset |
8753 | @ifset INTERNALS | |
c25c12b8 R |
8754 | @node Constant Definitions |
8755 | @section Constant Definitions | |
8756 | @cindex constant definitions | |
8757 | @findex define_constants | |
8758 | ||
8759 | Using literal constants inside instruction patterns reduces legibility and | |
8760 | can be a maintenance problem. | |
8761 | ||
8762 | To overcome this problem, you may use the @code{define_constants} | |
8763 | expression. It contains a vector of name-value pairs. From that | |
8764 | point on, wherever any of the names appears in the MD file, it is as | |
8765 | if the corresponding value had been written instead. You may use | |
8766 | @code{define_constants} multiple times; each appearance adds more | |
8767 | constants to the table. It is an error to redefine a constant with | |
8768 | a different value. | |
8769 | ||
8770 | To come back to the a29k load multiple example, instead of | |
8771 | ||
8772 | @smallexample | |
8773 | (define_insn "" | |
8774 | [(match_parallel 0 "load_multiple_operation" | |
8775 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
8776 | (match_operand:SI 2 "memory_operand" "m")) | |
8777 | (use (reg:SI 179)) | |
8778 | (clobber (reg:SI 179))])] | |
8779 | "" | |
8780 | "loadm 0,0,%1,%2") | |
8781 | @end smallexample | |
8782 | ||
8783 | You could write: | |
8784 | ||
8785 | @smallexample | |
8786 | (define_constants [ | |
8787 | (R_BP 177) | |
8788 | (R_FC 178) | |
8789 | (R_CR 179) | |
8790 | (R_Q 180) | |
8791 | ]) | |
8792 | ||
8793 | (define_insn "" | |
8794 | [(match_parallel 0 "load_multiple_operation" | |
8795 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
8796 | (match_operand:SI 2 "memory_operand" "m")) | |
8797 | (use (reg:SI R_CR)) | |
8798 | (clobber (reg:SI R_CR))])] | |
8799 | "" | |
8800 | "loadm 0,0,%1,%2") | |
8801 | @end smallexample | |
8802 | ||
8803 | The constants that are defined with a define_constant are also output | |
8804 | in the insn-codes.h header file as #defines. | |
24609606 RS |
8805 | |
8806 | @cindex enumerations | |
8807 | @findex define_c_enum | |
8808 | You can also use the machine description file to define enumerations. | |
8809 | Like the constants defined by @code{define_constant}, these enumerations | |
8810 | are visible to both the machine description file and the main C code. | |
8811 | ||
8812 | The syntax is as follows: | |
8813 | ||
8814 | @smallexample | |
8815 | (define_c_enum "@var{name}" [ | |
8816 | @var{value0} | |
8817 | @var{value1} | |
8818 | @dots{} | |
8819 | @var{valuen} | |
8820 | ]) | |
8821 | @end smallexample | |
8822 | ||
8823 | This definition causes the equivalent of the following C code to appear | |
8824 | in @file{insn-constants.h}: | |
8825 | ||
8826 | @smallexample | |
8827 | enum @var{name} @{ | |
8828 | @var{value0} = 0, | |
8829 | @var{value1} = 1, | |
8830 | @dots{} | |
8831 | @var{valuen} = @var{n} | |
8832 | @}; | |
8833 | #define NUM_@var{cname}_VALUES (@var{n} + 1) | |
8834 | @end smallexample | |
8835 | ||
8836 | where @var{cname} is the capitalized form of @var{name}. | |
8837 | It also makes each @var{valuei} available in the machine description | |
8838 | file, just as if it had been declared with: | |
8839 | ||
8840 | @smallexample | |
8841 | (define_constants [(@var{valuei} @var{i})]) | |
8842 | @end smallexample | |
8843 | ||
8844 | Each @var{valuei} is usually an upper-case identifier and usually | |
8845 | begins with @var{cname}. | |
8846 | ||
8847 | You can split the enumeration definition into as many statements as | |
8848 | you like. The above example is directly equivalent to: | |
8849 | ||
8850 | @smallexample | |
8851 | (define_c_enum "@var{name}" [@var{value0}]) | |
8852 | (define_c_enum "@var{name}" [@var{value1}]) | |
8853 | @dots{} | |
8854 | (define_c_enum "@var{name}" [@var{valuen}]) | |
8855 | @end smallexample | |
8856 | ||
8857 | Splitting the enumeration helps to improve the modularity of each | |
8858 | individual @code{.md} file. For example, if a port defines its | |
8859 | synchronization instructions in a separate @file{sync.md} file, | |
8860 | it is convenient to define all synchronization-specific enumeration | |
8861 | values in @file{sync.md} rather than in the main @file{.md} file. | |
8862 | ||
0fe60a1b RS |
8863 | Some enumeration names have special significance to GCC: |
8864 | ||
8865 | @table @code | |
8866 | @item unspecv | |
8867 | @findex unspec_volatile | |
8868 | If an enumeration called @code{unspecv} is defined, GCC will use it | |
8869 | when printing out @code{unspec_volatile} expressions. For example: | |
8870 | ||
8871 | @smallexample | |
8872 | (define_c_enum "unspecv" [ | |
8873 | UNSPECV_BLOCKAGE | |
8874 | ]) | |
8875 | @end smallexample | |
8876 | ||
8877 | causes GCC to print @samp{(unspec_volatile @dots{} 0)} as: | |
8878 | ||
8879 | @smallexample | |
8880 | (unspec_volatile ... UNSPECV_BLOCKAGE) | |
8881 | @end smallexample | |
8882 | ||
8883 | @item unspec | |
8884 | @findex unspec | |
8885 | If an enumeration called @code{unspec} is defined, GCC will use | |
8886 | it when printing out @code{unspec} expressions. GCC will also use | |
8887 | it when printing out @code{unspec_volatile} expressions unless an | |
8888 | @code{unspecv} enumeration is also defined. You can therefore | |
8889 | decide whether to keep separate enumerations for volatile and | |
8890 | non-volatile expressions or whether to use the same enumeration | |
8891 | for both. | |
8892 | @end table | |
8893 | ||
24609606 | 8894 | @findex define_enum |
8f4fe86c | 8895 | @anchor{define_enum} |
24609606 RS |
8896 | Another way of defining an enumeration is to use @code{define_enum}: |
8897 | ||
8898 | @smallexample | |
8899 | (define_enum "@var{name}" [ | |
8900 | @var{value0} | |
8901 | @var{value1} | |
8902 | @dots{} | |
8903 | @var{valuen} | |
8904 | ]) | |
8905 | @end smallexample | |
8906 | ||
8907 | This directive implies: | |
8908 | ||
8909 | @smallexample | |
8910 | (define_c_enum "@var{name}" [ | |
8911 | @var{cname}_@var{cvalue0} | |
8912 | @var{cname}_@var{cvalue1} | |
8913 | @dots{} | |
8914 | @var{cname}_@var{cvaluen} | |
8915 | ]) | |
8916 | @end smallexample | |
8917 | ||
8f4fe86c | 8918 | @findex define_enum_attr |
24609606 | 8919 | where @var{cvaluei} is the capitalized form of @var{valuei}. |
8f4fe86c RS |
8920 | However, unlike @code{define_c_enum}, the enumerations defined |
8921 | by @code{define_enum} can be used in attribute specifications | |
8922 | (@pxref{define_enum_attr}). | |
b11cc610 | 8923 | @end ifset |
032e8348 | 8924 | @ifset INTERNALS |
3abcb3a7 HPN |
8925 | @node Iterators |
8926 | @section Iterators | |
8927 | @cindex iterators in @file{.md} files | |
032e8348 RS |
8928 | |
8929 | Ports often need to define similar patterns for more than one machine | |
3abcb3a7 | 8930 | mode or for more than one rtx code. GCC provides some simple iterator |
032e8348 RS |
8931 | facilities to make this process easier. |
8932 | ||
8933 | @menu | |
3abcb3a7 HPN |
8934 | * Mode Iterators:: Generating variations of patterns for different modes. |
8935 | * Code Iterators:: Doing the same for codes. | |
57a4717b | 8936 | * Int Iterators:: Doing the same for integers. |
032e8348 RS |
8937 | @end menu |
8938 | ||
3abcb3a7 HPN |
8939 | @node Mode Iterators |
8940 | @subsection Mode Iterators | |
8941 | @cindex mode iterators in @file{.md} files | |
032e8348 RS |
8942 | |
8943 | Ports often need to define similar patterns for two or more different modes. | |
8944 | For example: | |
8945 | ||
8946 | @itemize @bullet | |
8947 | @item | |
8948 | If a processor has hardware support for both single and double | |
8949 | floating-point arithmetic, the @code{SFmode} patterns tend to be | |
8950 | very similar to the @code{DFmode} ones. | |
8951 | ||
8952 | @item | |
8953 | If a port uses @code{SImode} pointers in one configuration and | |
8954 | @code{DImode} pointers in another, it will usually have very similar | |
8955 | @code{SImode} and @code{DImode} patterns for manipulating pointers. | |
8956 | @end itemize | |
8957 | ||
3abcb3a7 | 8958 | Mode iterators allow several patterns to be instantiated from one |
032e8348 RS |
8959 | @file{.md} file template. They can be used with any type of |
8960 | rtx-based construct, such as a @code{define_insn}, | |
8961 | @code{define_split}, or @code{define_peephole2}. | |
8962 | ||
8963 | @menu | |
3abcb3a7 | 8964 | * Defining Mode Iterators:: Defining a new mode iterator. |
6ccde948 RW |
8965 | * Substitutions:: Combining mode iterators with substitutions |
8966 | * Examples:: Examples | |
032e8348 RS |
8967 | @end menu |
8968 | ||
3abcb3a7 HPN |
8969 | @node Defining Mode Iterators |
8970 | @subsubsection Defining Mode Iterators | |
8971 | @findex define_mode_iterator | |
032e8348 | 8972 | |
3abcb3a7 | 8973 | The syntax for defining a mode iterator is: |
032e8348 RS |
8974 | |
8975 | @smallexample | |
923158be | 8976 | (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")]) |
032e8348 RS |
8977 | @end smallexample |
8978 | ||
8979 | This allows subsequent @file{.md} file constructs to use the mode suffix | |
8980 | @code{:@var{name}}. Every construct that does so will be expanded | |
8981 | @var{n} times, once with every use of @code{:@var{name}} replaced by | |
8982 | @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}}, | |
8983 | and so on. In the expansion for a particular @var{modei}, every | |
8984 | C condition will also require that @var{condi} be true. | |
8985 | ||
8986 | For example: | |
8987 | ||
8988 | @smallexample | |
3abcb3a7 | 8989 | (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) |
032e8348 RS |
8990 | @end smallexample |
8991 | ||
8992 | defines a new mode suffix @code{:P}. Every construct that uses | |
8993 | @code{:P} will be expanded twice, once with every @code{:P} replaced | |
8994 | by @code{:SI} and once with every @code{:P} replaced by @code{:DI}. | |
8995 | The @code{:SI} version will only apply if @code{Pmode == SImode} and | |
8996 | the @code{:DI} version will only apply if @code{Pmode == DImode}. | |
8997 | ||
8998 | As with other @file{.md} conditions, an empty string is treated | |
8999 | as ``always true''. @code{(@var{mode} "")} can also be abbreviated | |
9000 | to @code{@var{mode}}. For example: | |
9001 | ||
9002 | @smallexample | |
3abcb3a7 | 9003 | (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) |
032e8348 RS |
9004 | @end smallexample |
9005 | ||
9006 | means that the @code{:DI} expansion only applies if @code{TARGET_64BIT} | |
9007 | but that the @code{:SI} expansion has no such constraint. | |
9008 | ||
3abcb3a7 HPN |
9009 | Iterators are applied in the order they are defined. This can be |
9010 | significant if two iterators are used in a construct that requires | |
f30990b2 | 9011 | substitutions. @xref{Substitutions}. |
032e8348 | 9012 | |
f30990b2 | 9013 | @node Substitutions |
3abcb3a7 | 9014 | @subsubsection Substitution in Mode Iterators |
032e8348 RS |
9015 | @findex define_mode_attr |
9016 | ||
3abcb3a7 | 9017 | If an @file{.md} file construct uses mode iterators, each version of the |
f30990b2 ILT |
9018 | construct will often need slightly different strings or modes. For |
9019 | example: | |
032e8348 RS |
9020 | |
9021 | @itemize @bullet | |
9022 | @item | |
9023 | When a @code{define_expand} defines several @code{add@var{m}3} patterns | |
9024 | (@pxref{Standard Names}), each expander will need to use the | |
9025 | appropriate mode name for @var{m}. | |
9026 | ||
9027 | @item | |
9028 | When a @code{define_insn} defines several instruction patterns, | |
9029 | each instruction will often use a different assembler mnemonic. | |
f30990b2 ILT |
9030 | |
9031 | @item | |
9032 | When a @code{define_insn} requires operands with different modes, | |
3abcb3a7 | 9033 | using an iterator for one of the operand modes usually requires a specific |
f30990b2 | 9034 | mode for the other operand(s). |
032e8348 RS |
9035 | @end itemize |
9036 | ||
9037 | GCC supports such variations through a system of ``mode attributes''. | |
9038 | There are two standard attributes: @code{mode}, which is the name of | |
9039 | the mode in lower case, and @code{MODE}, which is the same thing in | |
9040 | upper case. You can define other attributes using: | |
9041 | ||
9042 | @smallexample | |
923158be | 9043 | (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")]) |
032e8348 RS |
9044 | @end smallexample |
9045 | ||
9046 | where @var{name} is the name of the attribute and @var{valuei} | |
9047 | is the value associated with @var{modei}. | |
9048 | ||
3abcb3a7 | 9049 | When GCC replaces some @var{:iterator} with @var{:mode}, it will scan |
f30990b2 | 9050 | each string and mode in the pattern for sequences of the form |
3abcb3a7 | 9051 | @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a |
f30990b2 | 9052 | mode attribute. If the attribute is defined for @var{mode}, the whole |
923158be | 9053 | @code{<@dots{}>} sequence will be replaced by the appropriate attribute |
f30990b2 | 9054 | value. |
032e8348 RS |
9055 | |
9056 | For example, suppose an @file{.md} file has: | |
9057 | ||
9058 | @smallexample | |
3abcb3a7 | 9059 | (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) |
032e8348 RS |
9060 | (define_mode_attr load [(SI "lw") (DI "ld")]) |
9061 | @end smallexample | |
9062 | ||
9063 | If one of the patterns that uses @code{:P} contains the string | |
9064 | @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern | |
9065 | will use @code{"lw\t%0,%1"} and the @code{DI} version will use | |
9066 | @code{"ld\t%0,%1"}. | |
9067 | ||
f30990b2 ILT |
9068 | Here is an example of using an attribute for a mode: |
9069 | ||
9070 | @smallexample | |
3abcb3a7 | 9071 | (define_mode_iterator LONG [SI DI]) |
f30990b2 | 9072 | (define_mode_attr SHORT [(SI "HI") (DI "SI")]) |
923158be RW |
9073 | (define_insn @dots{} |
9074 | (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{}) | |
f30990b2 ILT |
9075 | @end smallexample |
9076 | ||
3abcb3a7 HPN |
9077 | The @code{@var{iterator}:} prefix may be omitted, in which case the |
9078 | substitution will be attempted for every iterator expansion. | |
032e8348 RS |
9079 | |
9080 | @node Examples | |
3abcb3a7 | 9081 | @subsubsection Mode Iterator Examples |
032e8348 RS |
9082 | |
9083 | Here is an example from the MIPS port. It defines the following | |
9084 | modes and attributes (among others): | |
9085 | ||
9086 | @smallexample | |
3abcb3a7 | 9087 | (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) |
032e8348 RS |
9088 | (define_mode_attr d [(SI "") (DI "d")]) |
9089 | @end smallexample | |
9090 | ||
9091 | and uses the following template to define both @code{subsi3} | |
9092 | and @code{subdi3}: | |
9093 | ||
9094 | @smallexample | |
9095 | (define_insn "sub<mode>3" | |
9096 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
9097 | (minus:GPR (match_operand:GPR 1 "register_operand" "d") | |
9098 | (match_operand:GPR 2 "register_operand" "d")))] | |
9099 | "" | |
9100 | "<d>subu\t%0,%1,%2" | |
9101 | [(set_attr "type" "arith") | |
9102 | (set_attr "mode" "<MODE>")]) | |
9103 | @end smallexample | |
9104 | ||
9105 | This is exactly equivalent to: | |
9106 | ||
9107 | @smallexample | |
9108 | (define_insn "subsi3" | |
9109 | [(set (match_operand:SI 0 "register_operand" "=d") | |
9110 | (minus:SI (match_operand:SI 1 "register_operand" "d") | |
9111 | (match_operand:SI 2 "register_operand" "d")))] | |
9112 | "" | |
9113 | "subu\t%0,%1,%2" | |
9114 | [(set_attr "type" "arith") | |
9115 | (set_attr "mode" "SI")]) | |
9116 | ||
9117 | (define_insn "subdi3" | |
9118 | [(set (match_operand:DI 0 "register_operand" "=d") | |
9119 | (minus:DI (match_operand:DI 1 "register_operand" "d") | |
9120 | (match_operand:DI 2 "register_operand" "d")))] | |
9121 | "" | |
9122 | "dsubu\t%0,%1,%2" | |
9123 | [(set_attr "type" "arith") | |
9124 | (set_attr "mode" "DI")]) | |
9125 | @end smallexample | |
9126 | ||
3abcb3a7 HPN |
9127 | @node Code Iterators |
9128 | @subsection Code Iterators | |
9129 | @cindex code iterators in @file{.md} files | |
9130 | @findex define_code_iterator | |
032e8348 RS |
9131 | @findex define_code_attr |
9132 | ||
3abcb3a7 | 9133 | Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}. |
032e8348 RS |
9134 | |
9135 | The construct: | |
9136 | ||
9137 | @smallexample | |
923158be | 9138 | (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")]) |
032e8348 RS |
9139 | @end smallexample |
9140 | ||
9141 | defines a pseudo rtx code @var{name} that can be instantiated as | |
9142 | @var{codei} if condition @var{condi} is true. Each @var{codei} | |
9143 | must have the same rtx format. @xref{RTL Classes}. | |
9144 | ||
3abcb3a7 | 9145 | As with mode iterators, each pattern that uses @var{name} will be |
032e8348 RS |
9146 | expanded @var{n} times, once with all uses of @var{name} replaced by |
9147 | @var{code1}, once with all uses replaced by @var{code2}, and so on. | |
3abcb3a7 | 9148 | @xref{Defining Mode Iterators}. |
032e8348 RS |
9149 | |
9150 | It is possible to define attributes for codes as well as for modes. | |
9151 | There are two standard code attributes: @code{code}, the name of the | |
9152 | code in lower case, and @code{CODE}, the name of the code in upper case. | |
9153 | Other attributes are defined using: | |
9154 | ||
9155 | @smallexample | |
923158be | 9156 | (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")]) |
032e8348 RS |
9157 | @end smallexample |
9158 | ||
3abcb3a7 | 9159 | Here's an example of code iterators in action, taken from the MIPS port: |
032e8348 RS |
9160 | |
9161 | @smallexample | |
3abcb3a7 HPN |
9162 | (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt |
9163 | eq ne gt ge lt le gtu geu ltu leu]) | |
032e8348 RS |
9164 | |
9165 | (define_expand "b<code>" | |
9166 | [(set (pc) | |
9167 | (if_then_else (any_cond:CC (cc0) | |
9168 | (const_int 0)) | |
9169 | (label_ref (match_operand 0 "")) | |
9170 | (pc)))] | |
9171 | "" | |
9172 | @{ | |
9173 | gen_conditional_branch (operands, <CODE>); | |
9174 | DONE; | |
9175 | @}) | |
9176 | @end smallexample | |
9177 | ||
9178 | This is equivalent to: | |
9179 | ||
9180 | @smallexample | |
9181 | (define_expand "bunordered" | |
9182 | [(set (pc) | |
9183 | (if_then_else (unordered:CC (cc0) | |
9184 | (const_int 0)) | |
9185 | (label_ref (match_operand 0 "")) | |
9186 | (pc)))] | |
9187 | "" | |
9188 | @{ | |
9189 | gen_conditional_branch (operands, UNORDERED); | |
9190 | DONE; | |
9191 | @}) | |
9192 | ||
9193 | (define_expand "bordered" | |
9194 | [(set (pc) | |
9195 | (if_then_else (ordered:CC (cc0) | |
9196 | (const_int 0)) | |
9197 | (label_ref (match_operand 0 "")) | |
9198 | (pc)))] | |
9199 | "" | |
9200 | @{ | |
9201 | gen_conditional_branch (operands, ORDERED); | |
9202 | DONE; | |
9203 | @}) | |
9204 | ||
923158be | 9205 | @dots{} |
032e8348 RS |
9206 | @end smallexample |
9207 | ||
57a4717b TB |
9208 | @node Int Iterators |
9209 | @subsection Int Iterators | |
9210 | @cindex int iterators in @file{.md} files | |
9211 | @findex define_int_iterator | |
9212 | @findex define_int_attr | |
9213 | ||
9214 | Int iterators operate in a similar way to code iterators. @xref{Code Iterators}. | |
9215 | ||
9216 | The construct: | |
9217 | ||
9218 | @smallexample | |
9219 | (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")]) | |
9220 | @end smallexample | |
9221 | ||
9222 | defines a pseudo integer constant @var{name} that can be instantiated as | |
9223 | @var{inti} if condition @var{condi} is true. Each @var{int} | |
9224 | must have the same rtx format. @xref{RTL Classes}. Int iterators can appear | |
9225 | in only those rtx fields that have 'i' as the specifier. This means that | |
9226 | each @var{int} has to be a constant defined using define_constant or | |
9227 | define_c_enum. | |
9228 | ||
9229 | As with mode and code iterators, each pattern that uses @var{name} will be | |
9230 | expanded @var{n} times, once with all uses of @var{name} replaced by | |
9231 | @var{int1}, once with all uses replaced by @var{int2}, and so on. | |
9232 | @xref{Defining Mode Iterators}. | |
9233 | ||
9234 | It is possible to define attributes for ints as well as for codes and modes. | |
9235 | Attributes are defined using: | |
9236 | ||
9237 | @smallexample | |
9238 | (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")]) | |
9239 | @end smallexample | |
9240 | ||
9241 | Here's an example of int iterators in action, taken from the ARM port: | |
9242 | ||
9243 | @smallexample | |
9244 | (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG]) | |
9245 | ||
9246 | (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")]) | |
9247 | ||
9248 | (define_insn "neon_vq<absneg><mode>" | |
9249 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | |
9250 | (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") | |
9251 | (match_operand:SI 2 "immediate_operand" "i")] | |
9252 | QABSNEG))] | |
9253 | "TARGET_NEON" | |
9254 | "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1" | |
9255 | [(set_attr "neon_type" "neon_vqneg_vqabs")] | |
9256 | ) | |
9257 | ||
9258 | @end smallexample | |
9259 | ||
9260 | This is equivalent to: | |
9261 | ||
9262 | @smallexample | |
9263 | (define_insn "neon_vqabs<mode>" | |
9264 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | |
9265 | (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") | |
9266 | (match_operand:SI 2 "immediate_operand" "i")] | |
9267 | UNSPEC_VQABS))] | |
9268 | "TARGET_NEON" | |
9269 | "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1" | |
9270 | [(set_attr "neon_type" "neon_vqneg_vqabs")] | |
9271 | ) | |
9272 | ||
9273 | (define_insn "neon_vqneg<mode>" | |
9274 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | |
9275 | (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") | |
9276 | (match_operand:SI 2 "immediate_operand" "i")] | |
9277 | UNSPEC_VQNEG))] | |
9278 | "TARGET_NEON" | |
9279 | "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1" | |
9280 | [(set_attr "neon_type" "neon_vqneg_vqabs")] | |
9281 | ) | |
9282 | ||
9283 | @end smallexample | |
9284 | ||
032e8348 | 9285 | @end ifset |