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f1717362 | 1 | @c Copyright (C) 1988-2016 Free Software Foundation, Inc. |
5fc0eb84 | 2 | @c This is part of the GCC manual. |
3 | @c For copying conditions, see the file gcc.texi. | |
4 | ||
5 | @node RTL | |
6 | @chapter RTL Representation | |
7 | @cindex RTL representation | |
8 | @cindex representation of RTL | |
9 | @cindex Register Transfer Language (RTL) | |
10 | ||
507ec136 | 11 | The last part of the compiler work is done on a low-level intermediate |
12 | representation called Register Transfer Language. In this language, the | |
13 | instructions to be output are described, pretty much one by one, in an | |
14 | algebraic form that describes what the instruction does. | |
5fc0eb84 | 15 | |
16 | RTL is inspired by Lisp lists. It has both an internal form, made up of | |
17 | structures that point at other structures, and a textual form that is used | |
18 | in the machine description and in printed debugging dumps. The textual | |
19 | form uses nested parentheses to indicate the pointers in the internal form. | |
20 | ||
21 | @menu | |
22 | * RTL Objects:: Expressions vs vectors vs strings vs integers. | |
8e5fcce7 | 23 | * RTL Classes:: Categories of RTL expression objects, and their structure. |
5fc0eb84 | 24 | * Accessors:: Macros to access expression operands or vector elts. |
650e773f | 25 | * Special Accessors:: Macros to access specific annotations on RTL. |
5fc0eb84 | 26 | * Flags:: Other flags in an RTL expression. |
27 | * Machine Modes:: Describing the size and format of a datum. | |
28 | * Constants:: Expressions with constant values. | |
29 | * Regs and Memory:: Expressions representing register contents or memory. | |
30 | * Arithmetic:: Expressions representing arithmetic on other expressions. | |
31 | * Comparisons:: Expressions representing comparison of expressions. | |
8e5fcce7 | 32 | * Bit-Fields:: Expressions representing bit-fields in memory or reg. |
35a03fc8 | 33 | * Vector Operations:: Expressions involving vector datatypes. |
5fc0eb84 | 34 | * Conversions:: Extending, truncating, floating or fixing. |
35 | * RTL Declarations:: Declaring volatility, constancy, etc. | |
36 | * Side Effects:: Expressions for storing in registers, etc. | |
37 | * Incdec:: Embedded side-effects for autoincrement addressing. | |
38 | * Assembler:: Representing @code{asm} with operands. | |
539f863b | 39 | * Debug Information:: Expressions representing debugging information. |
5fc0eb84 | 40 | * Insns:: Expression types for entire insns. |
41 | * Calls:: RTL representation of function call insns. | |
42 | * Sharing:: Some expressions are unique; others *must* be copied. | |
43 | * Reading RTL:: Reading textual RTL from a file. | |
44 | @end menu | |
45 | ||
b3fb49ae | 46 | @node RTL Objects |
5fc0eb84 | 47 | @section RTL Object Types |
48 | @cindex RTL object types | |
49 | ||
50 | @cindex RTL integers | |
51 | @cindex RTL strings | |
52 | @cindex RTL vectors | |
53 | @cindex RTL expression | |
54 | @cindex RTX (See RTL) | |
55 | RTL uses five kinds of objects: expressions, integers, wide integers, | |
56 | strings and vectors. Expressions are the most important ones. An RTL | |
57 | expression (``RTX'', for short) is a C structure, but it is usually | |
58 | referred to with a pointer; a type that is given the typedef name | |
59 | @code{rtx}. | |
60 | ||
531d4872 | 61 | An integer is simply an @code{int}; their written form uses decimal |
62 | digits. A wide integer is an integral object whose type is | |
63 | @code{HOST_WIDE_INT}; their written form uses decimal digits. | |
5fc0eb84 | 64 | |
65 | A string is a sequence of characters. In core it is represented as a | |
66 | @code{char *} in usual C fashion, and it is written in C syntax as well. | |
67 | However, strings in RTL may never be null. If you write an empty string in | |
68 | a machine description, it is represented in core as a null pointer rather | |
69 | than as a pointer to a null character. In certain contexts, these null | |
70 | pointers instead of strings are valid. Within RTL code, strings are most | |
71 | commonly found inside @code{symbol_ref} expressions, but they appear in | |
77f71523 | 72 | other contexts in the RTL expressions that make up machine descriptions. |
5fc0eb84 | 73 | |
875d8740 | 74 | In a machine description, strings are normally written with double |
b3d47662 | 75 | quotes, as you would in C@. However, strings in machine descriptions may |
875d8740 | 76 | extend over many lines, which is invalid C, and adjacent string |
b3d47662 | 77 | constants are not concatenated as they are in C@. Any string constant |
875d8740 | 78 | may be surrounded with a single set of parentheses. Sometimes this |
79 | makes the machine description easier to read. | |
80 | ||
81 | There is also a special syntax for strings, which can be useful when C | |
82 | code is embedded in a machine description. Wherever a string can | |
83 | appear, it is also valid to write a C-style brace block. The entire | |
84 | brace block, including the outermost pair of braces, is considered to be | |
85 | the string constant. Double quote characters inside the braces are not | |
86 | special. Therefore, if you write string constants in the C code, you | |
87 | need not escape each quote character with a backslash. | |
88 | ||
5fc0eb84 | 89 | A vector contains an arbitrary number of pointers to expressions. The |
90 | number of elements in the vector is explicitly present in the vector. | |
91 | The written form of a vector consists of square brackets | |
92 | (@samp{[@dots{}]}) surrounding the elements, in sequence and with | |
93 | whitespace separating them. Vectors of length zero are not created; | |
94 | null pointers are used instead. | |
95 | ||
96 | @cindex expression codes | |
97 | @cindex codes, RTL expression | |
98 | @findex GET_CODE | |
99 | @findex PUT_CODE | |
100 | Expressions are classified by @dfn{expression codes} (also called RTX | |
101 | codes). The expression code is a name defined in @file{rtl.def}, which is | |
f613a8c9 | 102 | also (in uppercase) a C enumeration constant. The possible expression |
5fc0eb84 | 103 | codes and their meanings are machine-independent. The code of an RTX can |
104 | be extracted with the macro @code{GET_CODE (@var{x})} and altered with | |
105 | @code{PUT_CODE (@var{x}, @var{newcode})}. | |
106 | ||
107 | The expression code determines how many operands the expression contains, | |
108 | and what kinds of objects they are. In RTL, unlike Lisp, you cannot tell | |
109 | by looking at an operand what kind of object it is. Instead, you must know | |
110 | from its context---from the expression code of the containing expression. | |
111 | For example, in an expression of code @code{subreg}, the first operand is | |
112 | to be regarded as an expression and the second operand as an integer. In | |
113 | an expression of code @code{plus}, there are two operands, both of which | |
114 | are to be regarded as expressions. In a @code{symbol_ref} expression, | |
115 | there is one operand, which is to be regarded as a string. | |
116 | ||
117 | Expressions are written as parentheses containing the name of the | |
118 | expression type, its flags and machine mode if any, and then the operands | |
119 | of the expression (separated by spaces). | |
120 | ||
f613a8c9 | 121 | Expression code names in the @samp{md} file are written in lowercase, |
122 | but when they appear in C code they are written in uppercase. In this | |
5fc0eb84 | 123 | manual, they are shown as follows: @code{const_int}. |
124 | ||
125 | @cindex (nil) | |
126 | @cindex nil | |
127 | In a few contexts a null pointer is valid where an expression is normally | |
128 | wanted. The written form of this is @code{(nil)}. | |
129 | ||
b3fb49ae | 130 | @node RTL Classes |
c0f28e1d | 131 | @section RTL Classes and Formats |
132 | @cindex RTL classes | |
133 | @cindex classes of RTX codes | |
134 | @cindex RTX codes, classes of | |
135 | @findex GET_RTX_CLASS | |
136 | ||
137 | The various expression codes are divided into several @dfn{classes}, | |
138 | which are represented by single characters. You can determine the class | |
139 | of an RTX code with the macro @code{GET_RTX_CLASS (@var{code})}. | |
51dd3024 | 140 | Currently, @file{rtl.def} defines these classes: |
c0f28e1d | 141 | |
142 | @table @code | |
6720e96c | 143 | @item RTX_OBJ |
c0f28e1d | 144 | An RTX code that represents an actual object, such as a register |
145 | (@code{REG}) or a memory location (@code{MEM}, @code{SYMBOL_REF}). | |
6720e96c | 146 | @code{LO_SUM}) is also included; instead, @code{SUBREG} and |
147 | @code{STRICT_LOW_PART} are not in this class, but in class @code{x}. | |
c0f28e1d | 148 | |
6720e96c | 149 | @item RTX_CONST_OBJ |
150 | An RTX code that represents a constant object. @code{HIGH} is also | |
151 | included in this class. | |
c0f28e1d | 152 | |
6720e96c | 153 | @item RTX_COMPARE |
154 | An RTX code for a non-symmetric comparison, such as @code{GEU} or | |
155 | @code{LT}. | |
156 | ||
157 | @item RTX_COMM_COMPARE | |
158 | An RTX code for a symmetric (commutative) comparison, such as @code{EQ} | |
159 | or @code{ORDERED}. | |
160 | ||
161 | @item RTX_UNARY | |
c0f28e1d | 162 | An RTX code for a unary arithmetic operation, such as @code{NEG}, |
163 | @code{NOT}, or @code{ABS}. This category also includes value extension | |
164 | (sign or zero) and conversions between integer and floating point. | |
165 | ||
6720e96c | 166 | @item RTX_COMM_ARITH |
c0f28e1d | 167 | An RTX code for a commutative binary operation, such as @code{PLUS} or |
168 | @code{AND}. @code{NE} and @code{EQ} are comparisons, so they have class | |
169 | @code{<}. | |
170 | ||
6720e96c | 171 | @item RTX_BIN_ARITH |
c0f28e1d | 172 | An RTX code for a non-commutative binary operation, such as @code{MINUS}, |
173 | @code{DIV}, or @code{ASHIFTRT}. | |
174 | ||
6720e96c | 175 | @item RTX_BITFIELD_OPS |
8e5fcce7 | 176 | An RTX code for a bit-field operation. Currently only |
c0f28e1d | 177 | @code{ZERO_EXTRACT} and @code{SIGN_EXTRACT}. These have three inputs |
8e5fcce7 | 178 | and are lvalues (so they can be used for insertion as well). |
179 | @xref{Bit-Fields}. | |
c0f28e1d | 180 | |
6720e96c | 181 | @item RTX_TERNARY |
c0f28e1d | 182 | An RTX code for other three input operations. Currently only |
7e0713b1 | 183 | @code{IF_THEN_ELSE}, @code{VEC_MERGE}, @code{SIGN_EXTRACT}, |
184 | @code{ZERO_EXTRACT}, and @code{FMA}. | |
c0f28e1d | 185 | |
6720e96c | 186 | @item RTX_INSN |
c0f28e1d | 187 | An RTX code for an entire instruction: @code{INSN}, @code{JUMP_INSN}, and |
71d6ad5e | 188 | @code{CALL_INSN}. @xref{Insns}. |
c0f28e1d | 189 | |
6720e96c | 190 | @item RTX_MATCH |
c0f28e1d | 191 | An RTX code for something that matches in insns, such as |
192 | @code{MATCH_DUP}. These only occur in machine descriptions. | |
193 | ||
6720e96c | 194 | @item RTX_AUTOINC |
40988080 | 195 | An RTX code for an auto-increment addressing mode, such as |
c0cb30e0 | 196 | @code{POST_INC}. @samp{XEXP (@var{x}, 0)} gives the auto-modified |
197 | register. | |
40988080 | 198 | |
6720e96c | 199 | @item RTX_EXTRA |
c0f28e1d | 200 | All other RTX codes. This category includes the remaining codes used |
201 | only in machine descriptions (@code{DEFINE_*}, etc.). It also includes | |
202 | all the codes describing side effects (@code{SET}, @code{USE}, | |
203 | @code{CLOBBER}, etc.) and the non-insns that may appear on an insn | |
204 | chain, such as @code{NOTE}, @code{BARRIER}, and @code{CODE_LABEL}. | |
6720e96c | 205 | @code{SUBREG} is also part of this class. |
c0f28e1d | 206 | @end table |
5fc0eb84 | 207 | |
208 | @cindex RTL format | |
7b479d17 | 209 | For each expression code, @file{rtl.def} specifies the number of |
210 | contained objects and their kinds using a sequence of characters | |
211 | called the @dfn{format} of the expression code. For example, | |
212 | the format of @code{subreg} is @samp{ei}. | |
5fc0eb84 | 213 | |
214 | @cindex RTL format characters | |
7b479d17 | 215 | These are the most commonly used format characters: |
216 | ||
217 | @table @code | |
218 | @item e | |
219 | An expression (actually a pointer to an expression). | |
220 | ||
221 | @item i | |
222 | An integer. | |
223 | ||
224 | @item w | |
225 | A wide integer. | |
226 | ||
227 | @item s | |
228 | A string. | |
229 | ||
230 | @item E | |
231 | A vector of expressions. | |
232 | @end table | |
233 | ||
5fc0eb84 | 234 | A few other format characters are used occasionally: |
235 | ||
236 | @table @code | |
237 | @item u | |
238 | @samp{u} is equivalent to @samp{e} except that it is printed differently | |
239 | in debugging dumps. It is used for pointers to insns. | |
240 | ||
241 | @item n | |
242 | @samp{n} is equivalent to @samp{i} except that it is printed differently | |
243 | in debugging dumps. It is used for the line number or code number of a | |
244 | @code{note} insn. | |
245 | ||
246 | @item S | |
247 | @samp{S} indicates a string which is optional. In the RTL objects in | |
248 | core, @samp{S} is equivalent to @samp{s}, but when the object is read, | |
249 | from an @samp{md} file, the string value of this operand may be omitted. | |
250 | An omitted string is taken to be the null string. | |
251 | ||
252 | @item V | |
253 | @samp{V} indicates a vector which is optional. In the RTL objects in | |
254 | core, @samp{V} is equivalent to @samp{E}, but when the object is read | |
255 | from an @samp{md} file, the vector value of this operand may be omitted. | |
256 | An omitted vector is effectively the same as a vector of no elements. | |
257 | ||
c100ae55 | 258 | @item B |
42cc08b5 | 259 | @samp{B} indicates a pointer to basic block structure. |
c100ae55 | 260 | |
5fc0eb84 | 261 | @item 0 |
262 | @samp{0} means a slot whose contents do not fit any normal category. | |
263 | @samp{0} slots are not printed at all in dumps, and are often used in | |
264 | special ways by small parts of the compiler. | |
265 | @end table | |
266 | ||
c0f28e1d | 267 | There are macros to get the number of operands and the format |
268 | of an expression code: | |
5fc0eb84 | 269 | |
270 | @table @code | |
271 | @findex GET_RTX_LENGTH | |
272 | @item GET_RTX_LENGTH (@var{code}) | |
273 | Number of operands of an RTX of code @var{code}. | |
274 | ||
275 | @findex GET_RTX_FORMAT | |
276 | @item GET_RTX_FORMAT (@var{code}) | |
277 | The format of an RTX of code @var{code}, as a C string. | |
c0f28e1d | 278 | @end table |
5fc0eb84 | 279 | |
c0f28e1d | 280 | Some classes of RTX codes always have the same format. For example, it |
281 | is safe to assume that all comparison operations have format @code{ee}. | |
5fc0eb84 | 282 | |
283 | @table @code | |
5fc0eb84 | 284 | @item 1 |
c0f28e1d | 285 | All codes of this class have format @code{e}. |
5fc0eb84 | 286 | |
c0f28e1d | 287 | @item < |
288 | @itemx c | |
289 | @itemx 2 | |
290 | All codes of these classes have format @code{ee}. | |
5fc0eb84 | 291 | |
292 | @item b | |
c0f28e1d | 293 | @itemx 3 |
294 | All codes of these classes have format @code{eee}. | |
5fc0eb84 | 295 | |
296 | @item i | |
c0f28e1d | 297 | All codes of this class have formats that begin with @code{iuueiee}. |
298 | @xref{Insns}. Note that not all RTL objects linked onto an insn chain | |
299 | are of class @code{i}. | |
5fc0eb84 | 300 | |
c0f28e1d | 301 | @item o |
302 | @itemx m | |
303 | @itemx x | |
304 | You can make no assumptions about the format of these codes. | |
5fc0eb84 | 305 | @end table |
306 | ||
b3fb49ae | 307 | @node Accessors |
c0f28e1d | 308 | @section Access to Operands |
309 | @cindex accessors | |
310 | @cindex access to operands | |
311 | @cindex operand access | |
312 | ||
5fc0eb84 | 313 | @findex XEXP |
314 | @findex XINT | |
315 | @findex XWINT | |
316 | @findex XSTR | |
317 | Operands of expressions are accessed using the macros @code{XEXP}, | |
318 | @code{XINT}, @code{XWINT} and @code{XSTR}. Each of these macros takes | |
319 | two arguments: an expression-pointer (RTX) and an operand number | |
f36eeacd | 320 | (counting from zero). Thus, |
5fc0eb84 | 321 | |
a0ecd6b1 | 322 | @smallexample |
5fc0eb84 | 323 | XEXP (@var{x}, 2) |
a0ecd6b1 | 324 | @end smallexample |
5fc0eb84 | 325 | |
326 | @noindent | |
327 | accesses operand 2 of expression @var{x}, as an expression. | |
328 | ||
a0ecd6b1 | 329 | @smallexample |
5fc0eb84 | 330 | XINT (@var{x}, 2) |
a0ecd6b1 | 331 | @end smallexample |
5fc0eb84 | 332 | |
333 | @noindent | |
334 | accesses the same operand as an integer. @code{XSTR}, used in the same | |
335 | fashion, would access it as a string. | |
336 | ||
337 | Any operand can be accessed as an integer, as an expression or as a string. | |
338 | You must choose the correct method of access for the kind of value actually | |
339 | stored in the operand. You would do this based on the expression code of | |
340 | the containing expression. That is also how you would know how many | |
341 | operands there are. | |
342 | ||
343 | For example, if @var{x} is a @code{subreg} expression, you know that it has | |
344 | two operands which can be correctly accessed as @code{XEXP (@var{x}, 0)} | |
345 | and @code{XINT (@var{x}, 1)}. If you did @code{XINT (@var{x}, 0)}, you | |
346 | would get the address of the expression operand but cast as an integer; | |
347 | that might occasionally be useful, but it would be cleaner to write | |
348 | @code{(int) XEXP (@var{x}, 0)}. @code{XEXP (@var{x}, 1)} would also | |
349 | compile without error, and would return the second, integer operand cast as | |
350 | an expression pointer, which would probably result in a crash when | |
351 | accessed. Nothing stops you from writing @code{XEXP (@var{x}, 28)} either, | |
352 | but this will access memory past the end of the expression with | |
f36eeacd | 353 | unpredictable results. |
5fc0eb84 | 354 | |
355 | Access to operands which are vectors is more complicated. You can use the | |
356 | macro @code{XVEC} to get the vector-pointer itself, or the macros | |
357 | @code{XVECEXP} and @code{XVECLEN} to access the elements and length of a | |
358 | vector. | |
359 | ||
360 | @table @code | |
361 | @findex XVEC | |
362 | @item XVEC (@var{exp}, @var{idx}) | |
363 | Access the vector-pointer which is operand number @var{idx} in @var{exp}. | |
364 | ||
365 | @findex XVECLEN | |
366 | @item XVECLEN (@var{exp}, @var{idx}) | |
367 | Access the length (number of elements) in the vector which is | |
368 | in operand number @var{idx} in @var{exp}. This value is an @code{int}. | |
369 | ||
370 | @findex XVECEXP | |
371 | @item XVECEXP (@var{exp}, @var{idx}, @var{eltnum}) | |
372 | Access element number @var{eltnum} in the vector which is | |
0858e3a2 | 373 | in operand number @var{idx} in @var{exp}. This value is an RTX@. |
5fc0eb84 | 374 | |
375 | It is up to you to make sure that @var{eltnum} is not negative | |
376 | and is less than @code{XVECLEN (@var{exp}, @var{idx})}. | |
377 | @end table | |
378 | ||
379 | All the macros defined in this section expand into lvalues and therefore | |
380 | can be used to assign the operands, lengths and vector elements as well as | |
381 | to access them. | |
382 | ||
650e773f | 383 | @node Special Accessors |
384 | @section Access to Special Operands | |
385 | @cindex access to special operands | |
386 | ||
387 | Some RTL nodes have special annotations associated with them. | |
388 | ||
389 | @table @code | |
390 | @item MEM | |
391 | @table @code | |
392 | @findex MEM_ALIAS_SET | |
393 | @item MEM_ALIAS_SET (@var{x}) | |
394 | If 0, @var{x} is not in any alias set, and may alias anything. Otherwise, | |
395 | @var{x} can only alias @code{MEM}s in a conflicting alias set. This value | |
396 | is set in a language-dependent manner in the front-end, and should not be | |
397 | altered in the back-end. In some front-ends, these numbers may correspond | |
398 | in some way to types, or other language-level entities, but they need not, | |
399 | and the back-end makes no such assumptions. | |
400 | These set numbers are tested with @code{alias_sets_conflict_p}. | |
401 | ||
402 | @findex MEM_EXPR | |
403 | @item MEM_EXPR (@var{x}) | |
404 | If this register is known to hold the value of some user-level | |
405 | declaration, this is that tree node. It may also be a | |
406 | @code{COMPONENT_REF}, in which case this is some field reference, | |
407 | and @code{TREE_OPERAND (@var{x}, 0)} contains the declaration, | |
408 | or another @code{COMPONENT_REF}, or null if there is no compile-time | |
409 | object associated with the reference. | |
410 | ||
da443c27 | 411 | @findex MEM_OFFSET_KNOWN_P |
412 | @item MEM_OFFSET_KNOWN_P (@var{x}) | |
413 | True if the offset of the memory reference from @code{MEM_EXPR} is known. | |
414 | @samp{MEM_OFFSET (@var{x})} provides the offset if so. | |
415 | ||
650e773f | 416 | @findex MEM_OFFSET |
417 | @item MEM_OFFSET (@var{x}) | |
da443c27 | 418 | The offset from the start of @code{MEM_EXPR}. The value is only valid if |
419 | @samp{MEM_OFFSET_KNOWN_P (@var{x})} is true. | |
650e773f | 420 | |
5b2a69fa | 421 | @findex MEM_SIZE_KNOWN_P |
422 | @item MEM_SIZE_KNOWN_P (@var{x}) | |
423 | True if the size of the memory reference is known. | |
424 | @samp{MEM_SIZE (@var{x})} provides its size if so. | |
425 | ||
650e773f | 426 | @findex MEM_SIZE |
427 | @item MEM_SIZE (@var{x}) | |
5b2a69fa | 428 | The size in bytes of the memory reference. |
650e773f | 429 | This is mostly relevant for @code{BLKmode} references as otherwise |
5b2a69fa | 430 | the size is implied by the mode. The value is only valid if |
431 | @samp{MEM_SIZE_KNOWN_P (@var{x})} is true. | |
650e773f | 432 | |
433 | @findex MEM_ALIGN | |
434 | @item MEM_ALIGN (@var{x}) | |
435 | The known alignment in bits of the memory reference. | |
bd1a81f7 | 436 | |
437 | @findex MEM_ADDR_SPACE | |
438 | @item MEM_ADDR_SPACE (@var{x}) | |
439 | The address space of the memory reference. This will commonly be zero | |
440 | for the generic address space. | |
650e773f | 441 | @end table |
442 | ||
443 | @item REG | |
444 | @table @code | |
445 | @findex ORIGINAL_REGNO | |
446 | @item ORIGINAL_REGNO (@var{x}) | |
447 | This field holds the number the register ``originally'' had; for a | |
448 | pseudo register turned into a hard reg this will hold the old pseudo | |
449 | register number. | |
450 | ||
451 | @findex REG_EXPR | |
452 | @item REG_EXPR (@var{x}) | |
453 | If this register is known to hold the value of some user-level | |
454 | declaration, this is that tree node. | |
455 | ||
456 | @findex REG_OFFSET | |
457 | @item REG_OFFSET (@var{x}) | |
458 | If this register is known to hold the value of some user-level | |
459 | declaration, this is the offset into that logical storage. | |
460 | @end table | |
461 | ||
462 | @item SYMBOL_REF | |
463 | @table @code | |
464 | @findex SYMBOL_REF_DECL | |
465 | @item SYMBOL_REF_DECL (@var{x}) | |
466 | If the @code{symbol_ref} @var{x} was created for a @code{VAR_DECL} or | |
467 | a @code{FUNCTION_DECL}, that tree is recorded here. If this value is | |
468 | null, then @var{x} was created by back end code generation routines, | |
b2fd8d52 | 469 | and there is no associated front end symbol table entry. |
470 | ||
471 | @code{SYMBOL_REF_DECL} may also point to a tree of class @code{'c'}, | |
472 | that is, some sort of constant. In this case, the @code{symbol_ref} | |
473 | is an entry in the per-file constant pool; again, there is no associated | |
474 | front end symbol table entry. | |
650e773f | 475 | |
7c266bb1 | 476 | @findex SYMBOL_REF_CONSTANT |
477 | @item SYMBOL_REF_CONSTANT (@var{x}) | |
478 | If @samp{CONSTANT_POOL_ADDRESS_P (@var{x})} is true, this is the constant | |
479 | pool entry for @var{x}. It is null otherwise. | |
480 | ||
481 | @findex SYMBOL_REF_DATA | |
482 | @item SYMBOL_REF_DATA (@var{x}) | |
b864739b | 483 | A field of opaque type used to store @code{SYMBOL_REF_DECL} or |
7c266bb1 | 484 | @code{SYMBOL_REF_CONSTANT}. |
485 | ||
650e773f | 486 | @findex SYMBOL_REF_FLAGS |
487 | @item SYMBOL_REF_FLAGS (@var{x}) | |
488 | In a @code{symbol_ref}, this is used to communicate various predicates | |
489 | about the symbol. Some of these are common enough to be computed by | |
490 | common code, some are specific to the target. The common bits are: | |
491 | ||
492 | @table @code | |
493 | @findex SYMBOL_REF_FUNCTION_P | |
494 | @findex SYMBOL_FLAG_FUNCTION | |
495 | @item SYMBOL_FLAG_FUNCTION | |
496 | Set if the symbol refers to a function. | |
497 | ||
498 | @findex SYMBOL_REF_LOCAL_P | |
499 | @findex SYMBOL_FLAG_LOCAL | |
500 | @item SYMBOL_FLAG_LOCAL | |
501 | Set if the symbol is local to this ``module''. | |
502 | See @code{TARGET_BINDS_LOCAL_P}. | |
503 | ||
504 | @findex SYMBOL_REF_EXTERNAL_P | |
505 | @findex SYMBOL_FLAG_EXTERNAL | |
506 | @item SYMBOL_FLAG_EXTERNAL | |
507 | Set if this symbol is not defined in this translation unit. | |
508 | Note that this is not the inverse of @code{SYMBOL_FLAG_LOCAL}. | |
509 | ||
510 | @findex SYMBOL_REF_SMALL_P | |
511 | @findex SYMBOL_FLAG_SMALL | |
512 | @item SYMBOL_FLAG_SMALL | |
513 | Set if the symbol is located in the small data section. | |
514 | See @code{TARGET_IN_SMALL_DATA_P}. | |
515 | ||
516 | @findex SYMBOL_FLAG_TLS_SHIFT | |
517 | @findex SYMBOL_REF_TLS_MODEL | |
518 | @item SYMBOL_REF_TLS_MODEL (@var{x}) | |
519 | This is a multi-bit field accessor that returns the @code{tls_model} | |
520 | to be used for a thread-local storage symbol. It returns zero for | |
521 | non-thread-local symbols. | |
f2d0e9f1 | 522 | |
6617cbc1 | 523 | @findex SYMBOL_REF_HAS_BLOCK_INFO_P |
524 | @findex SYMBOL_FLAG_HAS_BLOCK_INFO | |
525 | @item SYMBOL_FLAG_HAS_BLOCK_INFO | |
526 | Set if the symbol has @code{SYMBOL_REF_BLOCK} and | |
527 | @code{SYMBOL_REF_BLOCK_OFFSET} fields. | |
f2d0e9f1 | 528 | |
529 | @findex SYMBOL_REF_ANCHOR_P | |
530 | @findex SYMBOL_FLAG_ANCHOR | |
531 | @cindex @option{-fsection-anchors} | |
532 | @item SYMBOL_FLAG_ANCHOR | |
533 | Set if the symbol is used as a section anchor. ``Section anchors'' | |
534 | are symbols that have a known position within an @code{object_block} | |
535 | and that can be used to access nearby members of that block. | |
536 | They are used to implement @option{-fsection-anchors}. | |
537 | ||
6617cbc1 | 538 | If this flag is set, then @code{SYMBOL_FLAG_HAS_BLOCK_INFO} will be too. |
650e773f | 539 | @end table |
540 | ||
541 | Bits beginning with @code{SYMBOL_FLAG_MACH_DEP} are available for | |
542 | the target's use. | |
543 | @end table | |
f2d0e9f1 | 544 | |
545 | @findex SYMBOL_REF_BLOCK | |
546 | @item SYMBOL_REF_BLOCK (@var{x}) | |
6617cbc1 | 547 | If @samp{SYMBOL_REF_HAS_BLOCK_INFO_P (@var{x})}, this is the |
548 | @samp{object_block} structure to which the symbol belongs, | |
549 | or @code{NULL} if it has not been assigned a block. | |
f2d0e9f1 | 550 | |
551 | @findex SYMBOL_REF_BLOCK_OFFSET | |
552 | @item SYMBOL_REF_BLOCK_OFFSET (@var{x}) | |
6617cbc1 | 553 | If @samp{SYMBOL_REF_HAS_BLOCK_INFO_P (@var{x})}, this is the offset of @var{x} |
f2d0e9f1 | 554 | from the first object in @samp{SYMBOL_REF_BLOCK (@var{x})}. The value is |
6617cbc1 | 555 | negative if @var{x} has not yet been assigned to a block, or it has not |
556 | been given an offset within that block. | |
650e773f | 557 | @end table |
558 | ||
b3fb49ae | 559 | @node Flags |
5fc0eb84 | 560 | @section Flags in an RTL Expression |
561 | @cindex flags in RTL expression | |
562 | ||
4ae38af9 | 563 | RTL expressions contain several flags (one-bit bit-fields) |
564 | that are used in certain types of expression. Most often they | |
92778b4a | 565 | are accessed with the following macros, which expand into lvalues. |
5fc0eb84 | 566 | |
567 | @table @code | |
4ae38af9 | 568 | @findex CONSTANT_POOL_ADDRESS_P |
569 | @cindex @code{symbol_ref} and @samp{/u} | |
570 | @cindex @code{unchanging}, in @code{symbol_ref} | |
571 | @item CONSTANT_POOL_ADDRESS_P (@var{x}) | |
572 | Nonzero in a @code{symbol_ref} if it refers to part of the current | |
573 | function's constant pool. For most targets these addresses are in a | |
574 | @code{.rodata} section entirely separate from the function, but for | |
575 | some targets the addresses are close to the beginning of the function. | |
576 | In either case GCC assumes these addresses can be addressed directly, | |
577 | perhaps with the help of base registers. | |
578 | Stored in the @code{unchanging} field and printed as @samp{/u}. | |
579 | ||
0b7b55ea | 580 | @findex RTL_CONST_CALL_P |
4ae38af9 | 581 | @cindex @code{call_insn} and @samp{/u} |
582 | @cindex @code{unchanging}, in @code{call_insn} | |
f5c6c4b2 | 583 | @item RTL_CONST_CALL_P (@var{x}) |
0b7b55ea | 584 | In a @code{call_insn} indicates that the insn represents a call to a |
585 | const function. Stored in the @code{unchanging} field and printed as | |
586 | @samp{/u}. | |
587 | ||
588 | @findex RTL_PURE_CALL_P | |
589 | @cindex @code{call_insn} and @samp{/i} | |
590 | @cindex @code{return_val}, in @code{call_insn} | |
f5c6c4b2 | 591 | @item RTL_PURE_CALL_P (@var{x}) |
0b7b55ea | 592 | In a @code{call_insn} indicates that the insn represents a call to a |
593 | pure function. Stored in the @code{return_val} field and printed as | |
594 | @samp{/i}. | |
595 | ||
596 | @findex RTL_CONST_OR_PURE_CALL_P | |
597 | @cindex @code{call_insn} and @samp{/u} or @samp{/i} | |
598 | @item RTL_CONST_OR_PURE_CALL_P (@var{x}) | |
599 | In a @code{call_insn}, true if @code{RTL_CONST_CALL_P} or | |
600 | @code{RTL_PURE_CALL_P} is true. | |
601 | ||
602 | @findex RTL_LOOPING_CONST_OR_PURE_CALL_P | |
603 | @cindex @code{call_insn} and @samp{/c} | |
604 | @cindex @code{call}, in @code{call_insn} | |
605 | @item RTL_LOOPING_CONST_OR_PURE_CALL_P (@var{x}) | |
606 | In a @code{call_insn} indicates that the insn represents a possibly | |
607 | infinite looping call to a const or pure function. Stored in the | |
608 | @code{call} field and printed as @samp{/c}. Only true if one of | |
609 | @code{RTL_CONST_CALL_P} or @code{RTL_PURE_CALL_P} is true. | |
4ae38af9 | 610 | |
611 | @findex INSN_ANNULLED_BRANCH_P | |
3c6858c6 | 612 | @cindex @code{jump_insn} and @samp{/u} |
00f2bb6a | 613 | @cindex @code{call_insn} and @samp{/u} |
5fdf542c | 614 | @cindex @code{insn} and @samp{/u} |
615 | @cindex @code{unchanging}, in @code{jump_insn}, @code{call_insn} and @code{insn} | |
4ae38af9 | 616 | @item INSN_ANNULLED_BRANCH_P (@var{x}) |
5fdf542c | 617 | In a @code{jump_insn}, @code{call_insn}, or @code{insn} indicates |
618 | that the branch is an annulling one. See the discussion under | |
b3d47662 | 619 | @code{sequence} below. Stored in the @code{unchanging} field and |
5fdf542c | 620 | printed as @samp{/u}. |
4ae38af9 | 621 | |
4ae38af9 | 622 | @findex INSN_DELETED_P |
623 | @cindex @code{insn} and @samp{/v} | |
92778b4a | 624 | @cindex @code{call_insn} and @samp{/v} |
625 | @cindex @code{jump_insn} and @samp{/v} | |
626 | @cindex @code{code_label} and @samp{/v} | |
9ddbb404 | 627 | @cindex @code{jump_table_data} and @samp{/v} |
92778b4a | 628 | @cindex @code{barrier} and @samp{/v} |
629 | @cindex @code{note} and @samp{/v} | |
9ddbb404 | 630 | @cindex @code{volatil}, in @code{insn}, @code{call_insn}, @code{jump_insn}, @code{code_label}, @code{jump_table_data}, @code{barrier}, and @code{note} |
4ae38af9 | 631 | @item INSN_DELETED_P (@var{x}) |
92778b4a | 632 | In an @code{insn}, @code{call_insn}, @code{jump_insn}, @code{code_label}, |
9ddbb404 | 633 | @code{jump_table_data}, @code{barrier}, or @code{note}, |
92778b4a | 634 | nonzero if the insn has been deleted. Stored in the |
4ae38af9 | 635 | @code{volatil} field and printed as @samp{/v}. |
636 | ||
637 | @findex INSN_FROM_TARGET_P | |
638 | @cindex @code{insn} and @samp{/s} | |
3c6858c6 | 639 | @cindex @code{jump_insn} and @samp{/s} |
00f2bb6a | 640 | @cindex @code{call_insn} and @samp{/s} |
641 | @cindex @code{in_struct}, in @code{insn} and @code{jump_insn} and @code{call_insn} | |
4ae38af9 | 642 | @item INSN_FROM_TARGET_P (@var{x}) |
00f2bb6a | 643 | In an @code{insn} or @code{jump_insn} or @code{call_insn} in a delay |
644 | slot of a branch, indicates that the insn | |
4ae38af9 | 645 | is from the target of the branch. If the branch insn has |
646 | @code{INSN_ANNULLED_BRANCH_P} set, this insn will only be executed if | |
647 | the branch is taken. For annulled branches with | |
648 | @code{INSN_FROM_TARGET_P} clear, the insn will be executed only if the | |
649 | branch is not taken. When @code{INSN_ANNULLED_BRANCH_P} is not set, | |
650 | this insn will always be executed. Stored in the @code{in_struct} | |
651 | field and printed as @samp{/s}. | |
652 | ||
4ae38af9 | 653 | @findex LABEL_PRESERVE_P |
654 | @cindex @code{code_label} and @samp{/i} | |
92778b4a | 655 | @cindex @code{note} and @samp{/i} |
656 | @cindex @code{in_struct}, in @code{code_label} and @code{note} | |
4ae38af9 | 657 | @item LABEL_PRESERVE_P (@var{x}) |
92778b4a | 658 | In a @code{code_label} or @code{note}, indicates that the label is referenced by |
4ae38af9 | 659 | code or data not visible to the RTL of a given function. |
660 | Labels referenced by a non-local goto will have this bit set. Stored | |
661 | in the @code{in_struct} field and printed as @samp{/s}. | |
662 | ||
663 | @findex LABEL_REF_NONLOCAL_P | |
664 | @cindex @code{label_ref} and @samp{/v} | |
92778b4a | 665 | @cindex @code{reg_label} and @samp{/v} |
666 | @cindex @code{volatil}, in @code{label_ref} and @code{reg_label} | |
4ae38af9 | 667 | @item LABEL_REF_NONLOCAL_P (@var{x}) |
668 | In @code{label_ref} and @code{reg_label} expressions, nonzero if this is | |
669 | a reference to a non-local label. | |
5fc0eb84 | 670 | Stored in the @code{volatil} field and printed as @samp{/v}. |
671 | ||
4ae38af9 | 672 | @findex MEM_KEEP_ALIAS_SET_P |
673 | @cindex @code{mem} and @samp{/j} | |
674 | @cindex @code{jump}, in @code{mem} | |
675 | @item MEM_KEEP_ALIAS_SET_P (@var{x}) | |
676 | In @code{mem} expressions, 1 if we should keep the alias set for this | |
677 | mem unchanged when we access a component. Set to 1, for example, when we | |
678 | are already in a non-addressable component of an aggregate. | |
679 | Stored in the @code{jump} field and printed as @samp{/j}. | |
6a0934dd | 680 | |
4ae38af9 | 681 | @findex MEM_VOLATILE_P |
682 | @cindex @code{mem} and @samp{/v} | |
3c6858c6 | 683 | @cindex @code{asm_input} and @samp{/v} |
92778b4a | 684 | @cindex @code{asm_operands} and @samp{/v} |
3c6858c6 | 685 | @cindex @code{volatil}, in @code{mem}, @code{asm_operands}, and @code{asm_input} |
4ae38af9 | 686 | @item MEM_VOLATILE_P (@var{x}) |
3c6858c6 | 687 | In @code{mem}, @code{asm_operands}, and @code{asm_input} expressions, |
688 | nonzero for volatile memory references. | |
4ae38af9 | 689 | Stored in the @code{volatil} field and printed as @samp{/v}. |
690 | ||
1ed8ccdb | 691 | @findex MEM_NOTRAP_P |
692 | @cindex @code{mem} and @samp{/c} | |
693 | @cindex @code{call}, in @code{mem} | |
694 | @item MEM_NOTRAP_P (@var{x}) | |
695 | In @code{mem}, nonzero for memory references that will not trap. | |
696 | Stored in the @code{call} field and printed as @samp{/c}. | |
697 | ||
2877f49f | 698 | @findex MEM_POINTER |
699 | @cindex @code{mem} and @samp{/f} | |
700 | @cindex @code{frame_related}, in @code{mem} | |
701 | @item MEM_POINTER (@var{x}) | |
702 | Nonzero in a @code{mem} if the memory reference holds a pointer. | |
703 | Stored in the @code{frame_related} field and printed as @samp{/f}. | |
704 | ||
4ae38af9 | 705 | @findex REG_FUNCTION_VALUE_P |
706 | @cindex @code{reg} and @samp{/i} | |
2877f49f | 707 | @cindex @code{return_val}, in @code{reg} |
4ae38af9 | 708 | @item REG_FUNCTION_VALUE_P (@var{x}) |
709 | Nonzero in a @code{reg} if it is the place in which this function's | |
710 | value is going to be returned. (This happens only in a hard | |
2877f49f | 711 | register.) Stored in the @code{return_val} field and printed as |
4ae38af9 | 712 | @samp{/i}. |
b5ba9f3a | 713 | |
4ae38af9 | 714 | @findex REG_POINTER |
715 | @cindex @code{reg} and @samp{/f} | |
716 | @cindex @code{frame_related}, in @code{reg} | |
717 | @item REG_POINTER (@var{x}) | |
718 | Nonzero in a @code{reg} if the register holds a pointer. Stored in the | |
719 | @code{frame_related} field and printed as @samp{/f}. | |
720 | ||
77f71523 | 721 | @findex REG_USERVAR_P |
5fc0eb84 | 722 | @cindex @code{reg} and @samp{/v} |
723 | @cindex @code{volatil}, in @code{reg} | |
724 | @item REG_USERVAR_P (@var{x}) | |
725 | In a @code{reg}, nonzero if it corresponds to a variable present in | |
726 | the user's source code. Zero for temporaries generated internally by | |
727 | the compiler. Stored in the @code{volatil} field and printed as | |
728 | @samp{/v}. | |
729 | ||
5fc0eb84 | 730 | The same hard register may be used also for collecting the values of |
731 | functions called by this one, but @code{REG_FUNCTION_VALUE_P} is zero | |
732 | in this kind of use. | |
733 | ||
ad81c4f2 | 734 | @findex RTX_FRAME_RELATED_P |
4ae38af9 | 735 | @cindex @code{insn} and @samp{/f} |
92778b4a | 736 | @cindex @code{call_insn} and @samp{/f} |
737 | @cindex @code{jump_insn} and @samp{/f} | |
738 | @cindex @code{barrier} and @samp{/f} | |
739 | @cindex @code{set} and @samp{/f} | |
740 | @cindex @code{frame_related}, in @code{insn}, @code{call_insn}, @code{jump_insn}, @code{barrier}, and @code{set} | |
ad81c4f2 | 741 | @item RTX_FRAME_RELATED_P (@var{x}) |
92778b4a | 742 | Nonzero in an @code{insn}, @code{call_insn}, @code{jump_insn}, |
743 | @code{barrier}, or @code{set} which is part of a function prologue | |
950ae8fe | 744 | and sets the stack pointer, sets the frame pointer, or saves a register. |
745 | This flag should also be set on an instruction that sets up a temporary | |
746 | register to use in place of the frame pointer. | |
4ae38af9 | 747 | Stored in the @code{frame_related} field and printed as @samp{/f}. |
950ae8fe | 748 | |
749 | In particular, on RISC targets where there are limits on the sizes of | |
750 | immediate constants, it is sometimes impossible to reach the register | |
751 | save area directly from the stack pointer. In that case, a temporary | |
752 | register is used that is near enough to the register save area, and the | |
753 | Canonical Frame Address, i.e., DWARF2's logical frame pointer, register | |
754 | must (temporarily) be changed to be this temporary register. So, the | |
755 | instruction that sets this temporary register must be marked as | |
756 | @code{RTX_FRAME_RELATED_P}. | |
757 | ||
758 | If the marked instruction is overly complex (defined in terms of what | |
759 | @code{dwarf2out_frame_debug_expr} can handle), you will also have to | |
760 | create a @code{REG_FRAME_RELATED_EXPR} note and attach it to the | |
761 | instruction. This note should contain a simple expression of the | |
762 | computation performed by this instruction, i.e., one that | |
763 | @code{dwarf2out_frame_debug_expr} can handle. | |
764 | ||
765 | This flag is required for exception handling support on targets with RTL | |
766 | prologues. | |
ad81c4f2 | 767 | |
b04fab2a | 768 | @findex MEM_READONLY_P |
4ae38af9 | 769 | @cindex @code{mem} and @samp{/u} |
b04fab2a | 770 | @cindex @code{unchanging}, in @code{mem} |
771 | @item MEM_READONLY_P (@var{x}) | |
772 | Nonzero in a @code{mem}, if the memory is statically allocated and read-only. | |
773 | ||
8a9d312b | 774 | Read-only in this context means never modified during the lifetime of the |
b04fab2a | 775 | program, not necessarily in ROM or in write-disabled pages. A common |
776 | example of the later is a shared library's global offset table. This | |
777 | table is initialized by the runtime loader, so the memory is technically | |
9d75589a | 778 | writable, but after control is transferred from the runtime loader to the |
b04fab2a | 779 | application, this memory will never be subsequently modified. |
5738b814 | 780 | |
781 | Stored in the @code{unchanging} field and printed as @samp{/u}. | |
4ae38af9 | 782 | |
783 | @findex SCHED_GROUP_P | |
f372955c | 784 | @cindex @code{insn} and @samp{/s} |
785 | @cindex @code{call_insn} and @samp{/s} | |
786 | @cindex @code{jump_insn} and @samp{/s} | |
9ddbb404 | 787 | @cindex @code{jump_table_data} and @samp{/s} |
788 | @cindex @code{in_struct}, in @code{insn}, @code{call_insn}, @code{jump_insn} and @code{jump_table_data} | |
4ae38af9 | 789 | @item SCHED_GROUP_P (@var{x}) |
9ddbb404 | 790 | During instruction scheduling, in an @code{insn}, @code{call_insn}, |
791 | @code{jump_insn} or @code{jump_table_data}, indicates that the | |
4ae38af9 | 792 | previous insn must be scheduled together with this insn. This is used to |
793 | ensure that certain groups of instructions will not be split up by the | |
794 | instruction scheduling pass, for example, @code{use} insns before | |
795 | a @code{call_insn} may not be separated from the @code{call_insn}. | |
796 | Stored in the @code{in_struct} field and printed as @samp{/s}. | |
797 | ||
798 | @findex SET_IS_RETURN_P | |
799 | @cindex @code{insn} and @samp{/j} | |
800 | @cindex @code{jump}, in @code{insn} | |
801 | @item SET_IS_RETURN_P (@var{x}) | |
802 | For a @code{set}, nonzero if it is for a return. | |
803 | Stored in the @code{jump} field and printed as @samp{/j}. | |
804 | ||
805 | @findex SIBLING_CALL_P | |
806 | @cindex @code{call_insn} and @samp{/j} | |
807 | @cindex @code{jump}, in @code{call_insn} | |
808 | @item SIBLING_CALL_P (@var{x}) | |
809 | For a @code{call_insn}, nonzero if the insn is a sibling call. | |
810 | Stored in the @code{jump} field and printed as @samp{/j}. | |
811 | ||
812 | @findex STRING_POOL_ADDRESS_P | |
813 | @cindex @code{symbol_ref} and @samp{/f} | |
814 | @cindex @code{frame_related}, in @code{symbol_ref} | |
815 | @item STRING_POOL_ADDRESS_P (@var{x}) | |
816 | For a @code{symbol_ref} expression, nonzero if it addresses this function's | |
817 | string constant pool. | |
818 | Stored in the @code{frame_related} field and printed as @samp{/f}. | |
819 | ||
820 | @findex SUBREG_PROMOTED_UNSIGNED_P | |
bfd242e8 | 821 | @cindex @code{subreg} and @samp{/u} and @samp{/v} |
4ae38af9 | 822 | @cindex @code{unchanging}, in @code{subreg} |
bfd242e8 | 823 | @cindex @code{volatil}, in @code{subreg} |
4ae38af9 | 824 | @item SUBREG_PROMOTED_UNSIGNED_P (@var{x}) |
bfd242e8 | 825 | Returns a value greater then zero for a @code{subreg} that has |
826 | @code{SUBREG_PROMOTED_VAR_P} nonzero if the object being referenced is kept | |
827 | zero-extended, zero if it is kept sign-extended, and less then zero if it is | |
828 | extended some other way via the @code{ptr_extend} instruction. | |
829 | Stored in the @code{unchanging} | |
830 | field and @code{volatil} field, printed as @samp{/u} and @samp{/v}. | |
831 | This macro may only be used to get the value it may not be used to change | |
832 | the value. Use @code{SUBREG_PROMOTED_UNSIGNED_SET} to change the value. | |
833 | ||
834 | @findex SUBREG_PROMOTED_UNSIGNED_SET | |
835 | @cindex @code{subreg} and @samp{/u} | |
836 | @cindex @code{unchanging}, in @code{subreg} | |
837 | @cindex @code{volatil}, in @code{subreg} | |
838 | @item SUBREG_PROMOTED_UNSIGNED_SET (@var{x}) | |
839 | Set the @code{unchanging} and @code{volatil} fields in a @code{subreg} | |
840 | to reflect zero, sign, or other extension. If @code{volatil} is | |
841 | zero, then @code{unchanging} as nonzero means zero extension and as | |
b3d47662 | 842 | zero means sign extension. If @code{volatil} is nonzero then some |
bfd242e8 | 843 | other type of extension was done via the @code{ptr_extend} instruction. |
4ae38af9 | 844 | |
845 | @findex SUBREG_PROMOTED_VAR_P | |
846 | @cindex @code{subreg} and @samp{/s} | |
847 | @cindex @code{in_struct}, in @code{subreg} | |
848 | @item SUBREG_PROMOTED_VAR_P (@var{x}) | |
849 | Nonzero in a @code{subreg} if it was made when accessing an object that | |
850 | was promoted to a wider mode in accord with the @code{PROMOTED_MODE} machine | |
851 | description macro (@pxref{Storage Layout}). In this case, the mode of | |
852 | the @code{subreg} is the declared mode of the object and the mode of | |
853 | @code{SUBREG_REG} is the mode of the register that holds the object. | |
854 | Promoted variables are always either sign- or zero-extended to the wider | |
855 | mode on every assignment. Stored in the @code{in_struct} field and | |
856 | printed as @samp{/s}. | |
5fc0eb84 | 857 | |
4ae38af9 | 858 | @findex SYMBOL_REF_USED |
859 | @cindex @code{used}, in @code{symbol_ref} | |
860 | @item SYMBOL_REF_USED (@var{x}) | |
861 | In a @code{symbol_ref}, indicates that @var{x} has been used. This is | |
862 | normally only used to ensure that @var{x} is only declared external | |
863 | once. Stored in the @code{used} field. | |
864 | ||
67f79732 | 865 | @findex SYMBOL_REF_WEAK |
866 | @cindex @code{symbol_ref} and @samp{/i} | |
2877f49f | 867 | @cindex @code{return_val}, in @code{symbol_ref} |
67f79732 | 868 | @item SYMBOL_REF_WEAK (@var{x}) |
869 | In a @code{symbol_ref}, indicates that @var{x} has been declared weak. | |
2877f49f | 870 | Stored in the @code{return_val} field and printed as @samp{/i}. |
650e773f | 871 | |
872 | @findex SYMBOL_REF_FLAG | |
873 | @cindex @code{symbol_ref} and @samp{/v} | |
874 | @cindex @code{volatil}, in @code{symbol_ref} | |
875 | @item SYMBOL_REF_FLAG (@var{x}) | |
876 | In a @code{symbol_ref}, this is used as a flag for machine-specific purposes. | |
877 | Stored in the @code{volatil} field and printed as @samp{/v}. | |
878 | ||
879 | Most uses of @code{SYMBOL_REF_FLAG} are historic and may be subsumed | |
880 | by @code{SYMBOL_REF_FLAGS}. Certainly use of @code{SYMBOL_REF_FLAGS} | |
881 | is mandatory if the target requires more than one bit of storage. | |
6540132c | 882 | |
883 | @findex PREFETCH_SCHEDULE_BARRIER_P | |
884 | @cindex @code{prefetch} and @samp{/v} | |
885 | @cindex @code{volatile}, in @code{prefetch} | |
886 | @item PREFETCH_SCHEDULE_BARRIER_P (@var{x}) | |
887 | In a @code{prefetch}, indicates that the prefetch is a scheduling barrier. | |
888 | No other INSNs will be moved over it. | |
889 | Stored in the @code{volatil} field and printed as @samp{/v}. | |
5fc0eb84 | 890 | @end table |
891 | ||
4ae38af9 | 892 | These are the fields to which the above macros refer: |
5fc0eb84 | 893 | |
894 | @table @code | |
4ae38af9 | 895 | @findex call |
896 | @cindex @samp{/c} in RTL dump | |
897 | @item call | |
1ed8ccdb | 898 | In a @code{mem}, 1 means that the memory reference will not trap. |
5fc0eb84 | 899 | |
0b7b55ea | 900 | In a @code{call}, 1 means that this pure or const call may possibly |
901 | infinite loop. | |
902 | ||
4ae38af9 | 903 | In an RTL dump, this flag is represented as @samp{/c}. |
5fc0eb84 | 904 | |
4ae38af9 | 905 | @findex frame_related |
906 | @cindex @samp{/f} in RTL dump | |
907 | @item frame_related | |
908 | In an @code{insn} or @code{set} expression, 1 means that it is part of | |
909 | a function prologue and sets the stack pointer, sets the frame pointer, | |
910 | saves a register, or sets up a temporary register to use in place of the | |
911 | frame pointer. | |
5fc0eb84 | 912 | |
4ae38af9 | 913 | In @code{reg} expressions, 1 means that the register holds a pointer. |
5fc0eb84 | 914 | |
2877f49f | 915 | In @code{mem} expressions, 1 means that the memory reference holds a pointer. |
916 | ||
4ae38af9 | 917 | In @code{symbol_ref} expressions, 1 means that the reference addresses |
918 | this function's string constant pool. | |
5fc0eb84 | 919 | |
4ae38af9 | 920 | In an RTL dump, this flag is represented as @samp{/f}. |
5fc0eb84 | 921 | |
922 | @findex in_struct | |
4ae38af9 | 923 | @cindex @samp{/s} in RTL dump |
5fc0eb84 | 924 | @item in_struct |
5fc0eb84 | 925 | In @code{reg} expressions, it is 1 if the register has its entire life |
926 | contained within the test expression of some loop. | |
927 | ||
928 | In @code{subreg} expressions, 1 means that the @code{subreg} is accessing | |
929 | an object that has had its mode promoted from a wider mode. | |
930 | ||
931 | In @code{label_ref} expressions, 1 means that the referenced label is | |
932 | outside the innermost loop containing the insn in which the @code{label_ref} | |
933 | was found. | |
934 | ||
935 | In @code{code_label} expressions, it is 1 if the label may never be deleted. | |
ac2fdb7a | 936 | This is used for labels which are the target of non-local gotos. Such a |
937 | label that would have been deleted is replaced with a @code{note} of type | |
938 | @code{NOTE_INSN_DELETED_LABEL}. | |
5fc0eb84 | 939 | |
4ae38af9 | 940 | In an @code{insn} during dead-code elimination, 1 means that the insn is |
941 | dead code. | |
942 | ||
3c6858c6 | 943 | In an @code{insn} or @code{jump_insn} during reorg for an insn in the |
944 | delay slot of a branch, | |
4ae38af9 | 945 | 1 means that this insn is from the target of the branch. |
946 | ||
947 | In an @code{insn} during instruction scheduling, 1 means that this insn | |
948 | must be scheduled as part of a group together with the previous insn. | |
949 | ||
5fc0eb84 | 950 | In an RTL dump, this flag is represented as @samp{/s}. |
951 | ||
2877f49f | 952 | @findex return_val |
4ae38af9 | 953 | @cindex @samp{/i} in RTL dump |
2877f49f | 954 | @item return_val |
4ae38af9 | 955 | In @code{reg} expressions, 1 means the register contains |
956 | the value to be returned by the current function. On | |
957 | machines that pass parameters in registers, the same register number | |
958 | may be used for parameters as well, but this flag is not set on such | |
959 | uses. | |
960 | ||
961 | In @code{symbol_ref} expressions, 1 means the referenced symbol is weak. | |
962 | ||
0b7b55ea | 963 | In @code{call} expressions, 1 means the call is pure. |
964 | ||
4ae38af9 | 965 | In an RTL dump, this flag is represented as @samp{/i}. |
966 | ||
967 | @findex jump | |
968 | @cindex @samp{/j} in RTL dump | |
969 | @item jump | |
970 | In a @code{mem} expression, 1 means we should keep the alias set for this | |
971 | mem unchanged when we access a component. | |
972 | ||
973 | In a @code{set}, 1 means it is for a return. | |
974 | ||
975 | In a @code{call_insn}, 1 means it is a sibling call. | |
976 | ||
4ae38af9 | 977 | In an RTL dump, this flag is represented as @samp{/j}. |
978 | ||
5fc0eb84 | 979 | @findex unchanging |
4ae38af9 | 980 | @cindex @samp{/u} in RTL dump |
5fc0eb84 | 981 | @item unchanging |
982 | In @code{reg} and @code{mem} expressions, 1 means | |
983 | that the value of the expression never changes. | |
984 | ||
985 | In @code{subreg} expressions, it is 1 if the @code{subreg} references an | |
986 | unsigned object whose mode has been promoted to a wider mode. | |
987 | ||
3c6858c6 | 988 | In an @code{insn} or @code{jump_insn} in the delay slot of a branch |
989 | instruction, 1 means an annulling branch should be used. | |
5fc0eb84 | 990 | |
991 | In a @code{symbol_ref} expression, 1 means that this symbol addresses | |
4ae38af9 | 992 | something in the per-function constant pool. |
5fc0eb84 | 993 | |
0b7b55ea | 994 | In a @code{call_insn} 1 means that this instruction is a call to a const |
995 | function. | |
5fc0eb84 | 996 | |
997 | In an RTL dump, this flag is represented as @samp{/u}. | |
998 | ||
4ae38af9 | 999 | @findex used |
1000 | @item used | |
1001 | This flag is used directly (without an access macro) at the end of RTL | |
1002 | generation for a function, to count the number of times an expression | |
1003 | appears in insns. Expressions that appear more than once are copied, | |
1004 | according to the rules for shared structure (@pxref{Sharing}). | |
5fc0eb84 | 1005 | |
4ae38af9 | 1006 | For a @code{reg}, it is used directly (without an access macro) by the |
1007 | leaf register renumbering code to ensure that each register is only | |
1008 | renumbered once. | |
1009 | ||
1010 | In a @code{symbol_ref}, it indicates that an external declaration for | |
1011 | the symbol has already been written. | |
1012 | ||
1013 | @findex volatil | |
1014 | @cindex @samp{/v} in RTL dump | |
1015 | @item volatil | |
1016 | @cindex volatile memory references | |
3c6858c6 | 1017 | In a @code{mem}, @code{asm_operands}, or @code{asm_input} |
1018 | expression, it is 1 if the memory | |
4ae38af9 | 1019 | reference is volatile. Volatile memory references may not be deleted, |
1020 | reordered or combined. | |
1021 | ||
1022 | In a @code{symbol_ref} expression, it is used for machine-specific | |
1023 | purposes. | |
1024 | ||
1025 | In a @code{reg} expression, it is 1 if the value is a user-level variable. | |
1026 | 0 indicates an internal compiler temporary. | |
1027 | ||
1028 | In an @code{insn}, 1 means the insn has been deleted. | |
1029 | ||
1030 | In @code{label_ref} and @code{reg_label} expressions, 1 means a reference | |
1031 | to a non-local label. | |
1032 | ||
6540132c | 1033 | In @code{prefetch} expressions, 1 means that the containing insn is a |
1034 | scheduling barrier. | |
1035 | ||
4ae38af9 | 1036 | In an RTL dump, this flag is represented as @samp{/v}. |
5fc0eb84 | 1037 | @end table |
1038 | ||
b3fb49ae | 1039 | @node Machine Modes |
5fc0eb84 | 1040 | @section Machine Modes |
1041 | @cindex machine modes | |
1042 | ||
3754d046 | 1043 | @findex machine_mode |
5fc0eb84 | 1044 | A machine mode describes a size of data object and the representation used |
1045 | for it. In the C code, machine modes are represented by an enumeration | |
3754d046 | 1046 | type, @code{machine_mode}, defined in @file{machmode.def}. Each RTL |
5fc0eb84 | 1047 | expression has room for a machine mode and so do certain kinds of tree |
1048 | expressions (declarations and types, to be precise). | |
1049 | ||
1050 | In debugging dumps and machine descriptions, the machine mode of an RTL | |
1051 | expression is written after the expression code with a colon to separate | |
1052 | them. The letters @samp{mode} which appear at the end of each machine mode | |
1053 | name are omitted. For example, @code{(reg:SI 38)} is a @code{reg} | |
1054 | expression with machine mode @code{SImode}. If the mode is | |
1055 | @code{VOIDmode}, it is not written at all. | |
1056 | ||
1057 | Here is a table of machine modes. The term ``byte'' below refers to an | |
1058 | object of @code{BITS_PER_UNIT} bits (@pxref{Storage Layout}). | |
1059 | ||
1060 | @table @code | |
bcf1adbd | 1061 | @findex BImode |
1062 | @item BImode | |
1063 | ``Bit'' mode represents a single bit, for predicate registers. | |
1064 | ||
5fc0eb84 | 1065 | @findex QImode |
1066 | @item QImode | |
1067 | ``Quarter-Integer'' mode represents a single byte treated as an integer. | |
1068 | ||
1069 | @findex HImode | |
1070 | @item HImode | |
1071 | ``Half-Integer'' mode represents a two-byte integer. | |
1072 | ||
1073 | @findex PSImode | |
1074 | @item PSImode | |
1075 | ``Partial Single Integer'' mode represents an integer which occupies | |
1076 | four bytes but which doesn't really use all four. On some machines, | |
1077 | this is the right mode to use for pointers. | |
1078 | ||
1079 | @findex SImode | |
1080 | @item SImode | |
1081 | ``Single Integer'' mode represents a four-byte integer. | |
1082 | ||
1083 | @findex PDImode | |
1084 | @item PDImode | |
1085 | ``Partial Double Integer'' mode represents an integer which occupies | |
1086 | eight bytes but which doesn't really use all eight. On some machines, | |
1087 | this is the right mode to use for certain pointers. | |
1088 | ||
1089 | @findex DImode | |
1090 | @item DImode | |
1091 | ``Double Integer'' mode represents an eight-byte integer. | |
1092 | ||
1093 | @findex TImode | |
1094 | @item TImode | |
1095 | ``Tetra Integer'' (?) mode represents a sixteen-byte integer. | |
1096 | ||
bcf1adbd | 1097 | @findex OImode |
1098 | @item OImode | |
1099 | ``Octa Integer'' (?) mode represents a thirty-two-byte integer. | |
1100 | ||
e13e1b39 | 1101 | @findex XImode |
1102 | @item XImode | |
1103 | ``Hexadeca Integer'' (?) mode represents a sixty-four-byte integer. | |
1104 | ||
3f03ec2f | 1105 | @findex QFmode |
1106 | @item QFmode | |
1107 | ``Quarter-Floating'' mode represents a quarter-precision (single byte) | |
1108 | floating point number. | |
1109 | ||
1110 | @findex HFmode | |
1111 | @item HFmode | |
1112 | ``Half-Floating'' mode represents a half-precision (two byte) floating | |
1113 | point number. | |
1114 | ||
1115 | @findex TQFmode | |
1116 | @item TQFmode | |
1117 | ``Three-Quarter-Floating'' (?) mode represents a three-quarter-precision | |
1118 | (three byte) floating point number. | |
1119 | ||
5fc0eb84 | 1120 | @findex SFmode |
1121 | @item SFmode | |
f7e36447 | 1122 | ``Single Floating'' mode represents a four byte floating point number. |
1123 | In the common case, of a processor with IEEE arithmetic and 8-bit bytes, | |
1124 | this is a single-precision IEEE floating point number; it can also be | |
1125 | used for double-precision (on processors with 16-bit bytes) and | |
3f03ec2f | 1126 | single-precision VAX and IBM types. |
5fc0eb84 | 1127 | |
1128 | @findex DFmode | |
1129 | @item DFmode | |
f7e36447 | 1130 | ``Double Floating'' mode represents an eight byte floating point number. |
1131 | In the common case, of a processor with IEEE arithmetic and 8-bit bytes, | |
1132 | this is a double-precision IEEE floating point number. | |
5fc0eb84 | 1133 | |
1134 | @findex XFmode | |
1135 | @item XFmode | |
77d98cfe | 1136 | ``Extended Floating'' mode represents an IEEE extended floating point |
1137 | number. This mode only has 80 meaningful bits (ten bytes). Some | |
1138 | processors require such numbers to be padded to twelve bytes, others | |
1139 | to sixteen; this mode is used for either. | |
5fc0eb84 | 1140 | |
e03b3837 | 1141 | @findex SDmode |
1142 | @item SDmode | |
1143 | ``Single Decimal Floating'' mode represents a four byte decimal | |
1144 | floating point number (as distinct from conventional binary floating | |
1145 | point). | |
1146 | ||
1147 | @findex DDmode | |
1148 | @item DDmode | |
1149 | ``Double Decimal Floating'' mode represents an eight byte decimal | |
1150 | floating point number. | |
1151 | ||
1152 | @findex TDmode | |
1153 | @item TDmode | |
1154 | ``Tetra Decimal Floating'' mode represents a sixteen byte decimal | |
1155 | floating point number all 128 of whose bits are meaningful. | |
1156 | ||
5fc0eb84 | 1157 | @findex TFmode |
1158 | @item TFmode | |
77d98cfe | 1159 | ``Tetra Floating'' mode represents a sixteen byte floating point number |
1160 | all 128 of whose bits are meaningful. One common use is the | |
1161 | IEEE quad-precision format. | |
5fc0eb84 | 1162 | |
c559c639 | 1163 | @findex QQmode |
1164 | @item QQmode | |
1165 | ``Quarter-Fractional'' mode represents a single byte treated as a signed | |
1166 | fractional number. The default format is ``s.7''. | |
1167 | ||
1168 | @findex HQmode | |
1169 | @item HQmode | |
1170 | ``Half-Fractional'' mode represents a two-byte signed fractional number. | |
1171 | The default format is ``s.15''. | |
1172 | ||
1173 | @findex SQmode | |
1174 | @item SQmode | |
1175 | ``Single Fractional'' mode represents a four-byte signed fractional number. | |
1176 | The default format is ``s.31''. | |
1177 | ||
1178 | @findex DQmode | |
1179 | @item DQmode | |
1180 | ``Double Fractional'' mode represents an eight-byte signed fractional number. | |
1181 | The default format is ``s.63''. | |
1182 | ||
1183 | @findex TQmode | |
1184 | @item TQmode | |
1185 | ``Tetra Fractional'' mode represents a sixteen-byte signed fractional number. | |
1186 | The default format is ``s.127''. | |
1187 | ||
1188 | @findex UQQmode | |
1189 | @item UQQmode | |
1190 | ``Unsigned Quarter-Fractional'' mode represents a single byte treated as an | |
1191 | unsigned fractional number. The default format is ``.8''. | |
1192 | ||
1193 | @findex UHQmode | |
1194 | @item UHQmode | |
1195 | ``Unsigned Half-Fractional'' mode represents a two-byte unsigned fractional | |
1196 | number. The default format is ``.16''. | |
1197 | ||
1198 | @findex USQmode | |
1199 | @item USQmode | |
1200 | ``Unsigned Single Fractional'' mode represents a four-byte unsigned fractional | |
1201 | number. The default format is ``.32''. | |
1202 | ||
1203 | @findex UDQmode | |
1204 | @item UDQmode | |
1205 | ``Unsigned Double Fractional'' mode represents an eight-byte unsigned | |
1206 | fractional number. The default format is ``.64''. | |
1207 | ||
1208 | @findex UTQmode | |
1209 | @item UTQmode | |
1210 | ``Unsigned Tetra Fractional'' mode represents a sixteen-byte unsigned | |
1211 | fractional number. The default format is ``.128''. | |
1212 | ||
1213 | @findex HAmode | |
1214 | @item HAmode | |
1215 | ``Half-Accumulator'' mode represents a two-byte signed accumulator. | |
1216 | The default format is ``s8.7''. | |
1217 | ||
1218 | @findex SAmode | |
1219 | @item SAmode | |
1220 | ``Single Accumulator'' mode represents a four-byte signed accumulator. | |
1221 | The default format is ``s16.15''. | |
1222 | ||
1223 | @findex DAmode | |
1224 | @item DAmode | |
1225 | ``Double Accumulator'' mode represents an eight-byte signed accumulator. | |
1226 | The default format is ``s32.31''. | |
1227 | ||
1228 | @findex TAmode | |
1229 | @item TAmode | |
1230 | ``Tetra Accumulator'' mode represents a sixteen-byte signed accumulator. | |
1231 | The default format is ``s64.63''. | |
1232 | ||
1233 | @findex UHAmode | |
1234 | @item UHAmode | |
1235 | ``Unsigned Half-Accumulator'' mode represents a two-byte unsigned accumulator. | |
1236 | The default format is ``8.8''. | |
1237 | ||
1238 | @findex USAmode | |
1239 | @item USAmode | |
1240 | ``Unsigned Single Accumulator'' mode represents a four-byte unsigned | |
1241 | accumulator. The default format is ``16.16''. | |
1242 | ||
1243 | @findex UDAmode | |
1244 | @item UDAmode | |
1245 | ``Unsigned Double Accumulator'' mode represents an eight-byte unsigned | |
1246 | accumulator. The default format is ``32.32''. | |
1247 | ||
1248 | @findex UTAmode | |
1249 | @item UTAmode | |
1250 | ``Unsigned Tetra Accumulator'' mode represents a sixteen-byte unsigned | |
1251 | accumulator. The default format is ``64.64''. | |
1252 | ||
5fc0eb84 | 1253 | @findex CCmode |
1254 | @item CCmode | |
1255 | ``Condition Code'' mode represents the value of a condition code, which | |
1256 | is a machine-specific set of bits used to represent the result of a | |
1257 | comparison operation. Other machine-specific modes may also be used for | |
1258 | the condition code. These modes are not used on machines that use | |
1f071633 | 1259 | @code{cc0} (@pxref{Condition Code}). |
5fc0eb84 | 1260 | |
1261 | @findex BLKmode | |
1262 | @item BLKmode | |
1263 | ``Block'' mode represents values that are aggregates to which none of | |
1264 | the other modes apply. In RTL, only memory references can have this mode, | |
1265 | and only if they appear in string-move or vector instructions. On machines | |
0858e3a2 | 1266 | which have no such instructions, @code{BLKmode} will not appear in RTL@. |
5fc0eb84 | 1267 | |
1268 | @findex VOIDmode | |
1269 | @item VOIDmode | |
1270 | Void mode means the absence of a mode or an unspecified mode. | |
1271 | For example, RTL expressions of code @code{const_int} have mode | |
1272 | @code{VOIDmode} because they can be taken to have whatever mode the context | |
1273 | requires. In debugging dumps of RTL, @code{VOIDmode} is expressed by | |
1274 | the absence of any mode. | |
1275 | ||
3f03ec2f | 1276 | @findex QCmode |
1277 | @findex HCmode | |
5fc0eb84 | 1278 | @findex SCmode |
1279 | @findex DCmode | |
1280 | @findex XCmode | |
1281 | @findex TCmode | |
3f03ec2f | 1282 | @item QCmode, HCmode, SCmode, DCmode, XCmode, TCmode |
5fc0eb84 | 1283 | These modes stand for a complex number represented as a pair of floating |
3f03ec2f | 1284 | point values. The floating point values are in @code{QFmode}, |
1285 | @code{HFmode}, @code{SFmode}, @code{DFmode}, @code{XFmode}, and | |
1286 | @code{TFmode}, respectively. | |
5fc0eb84 | 1287 | |
1288 | @findex CQImode | |
1289 | @findex CHImode | |
1290 | @findex CSImode | |
1291 | @findex CDImode | |
1292 | @findex CTImode | |
1293 | @findex COImode | |
1294 | @item CQImode, CHImode, CSImode, CDImode, CTImode, COImode | |
1295 | These modes stand for a complex number represented as a pair of integer | |
1296 | values. The integer values are in @code{QImode}, @code{HImode}, | |
1297 | @code{SImode}, @code{DImode}, @code{TImode}, and @code{OImode}, | |
1298 | respectively. | |
058a1b7a | 1299 | |
1300 | @findex BND32mode | |
1301 | @findex BND64mode | |
1302 | @item BND32mode BND64mode | |
1303 | These modes stand for bounds for pointer of 32 and 64 bit size respectively. | |
1304 | Mode size is double pointer mode size. | |
5fc0eb84 | 1305 | @end table |
1306 | ||
1307 | The machine description defines @code{Pmode} as a C macro which expands | |
1308 | into the machine mode used for addresses. Normally this is the mode | |
1309 | whose size is @code{BITS_PER_WORD}, @code{SImode} on 32-bit machines. | |
1310 | ||
1311 | The only modes which a machine description @i{must} support are | |
1312 | @code{QImode}, and the modes corresponding to @code{BITS_PER_WORD}, | |
1313 | @code{FLOAT_TYPE_SIZE} and @code{DOUBLE_TYPE_SIZE}. | |
1314 | The compiler will attempt to use @code{DImode} for 8-byte structures and | |
1315 | unions, but this can be prevented by overriding the definition of | |
1316 | @code{MAX_FIXED_MODE_SIZE}. Alternatively, you can have the compiler | |
1317 | use @code{TImode} for 16-byte structures and unions. Likewise, you can | |
1318 | arrange for the C type @code{short int} to avoid using @code{HImode}. | |
1319 | ||
1320 | @cindex mode classes | |
1321 | Very few explicit references to machine modes remain in the compiler and | |
1322 | these few references will soon be removed. Instead, the machine modes | |
1323 | are divided into mode classes. These are represented by the enumeration | |
1324 | type @code{enum mode_class} defined in @file{machmode.h}. The possible | |
1325 | mode classes are: | |
1326 | ||
1327 | @table @code | |
1328 | @findex MODE_INT | |
1329 | @item MODE_INT | |
3f03ec2f | 1330 | Integer modes. By default these are @code{BImode}, @code{QImode}, |
1331 | @code{HImode}, @code{SImode}, @code{DImode}, @code{TImode}, and | |
1332 | @code{OImode}. | |
5fc0eb84 | 1333 | |
1334 | @findex MODE_PARTIAL_INT | |
1335 | @item MODE_PARTIAL_INT | |
3f03ec2f | 1336 | The ``partial integer'' modes, @code{PQImode}, @code{PHImode}, |
1337 | @code{PSImode} and @code{PDImode}. | |
5fc0eb84 | 1338 | |
1339 | @findex MODE_FLOAT | |
1340 | @item MODE_FLOAT | |
3f03ec2f | 1341 | Floating point modes. By default these are @code{QFmode}, |
1342 | @code{HFmode}, @code{TQFmode}, @code{SFmode}, @code{DFmode}, | |
5fc0eb84 | 1343 | @code{XFmode} and @code{TFmode}. |
1344 | ||
e03b3837 | 1345 | @findex MODE_DECIMAL_FLOAT |
1346 | @item MODE_DECIMAL_FLOAT | |
1347 | Decimal floating point modes. By default these are @code{SDmode}, | |
1348 | @code{DDmode} and @code{TDmode}. | |
1349 | ||
c559c639 | 1350 | @findex MODE_FRACT |
1351 | @item MODE_FRACT | |
1352 | Signed fractional modes. By default these are @code{QQmode}, @code{HQmode}, | |
1353 | @code{SQmode}, @code{DQmode} and @code{TQmode}. | |
1354 | ||
1355 | @findex MODE_UFRACT | |
1356 | @item MODE_UFRACT | |
1357 | Unsigned fractional modes. By default these are @code{UQQmode}, @code{UHQmode}, | |
1358 | @code{USQmode}, @code{UDQmode} and @code{UTQmode}. | |
1359 | ||
1360 | @findex MODE_ACCUM | |
1361 | @item MODE_ACCUM | |
1362 | Signed accumulator modes. By default these are @code{HAmode}, | |
1363 | @code{SAmode}, @code{DAmode} and @code{TAmode}. | |
1364 | ||
1365 | @findex MODE_UACCUM | |
1366 | @item MODE_UACCUM | |
1367 | Unsigned accumulator modes. By default these are @code{UHAmode}, | |
1368 | @code{USAmode}, @code{UDAmode} and @code{UTAmode}. | |
1369 | ||
5fc0eb84 | 1370 | @findex MODE_COMPLEX_INT |
1371 | @item MODE_COMPLEX_INT | |
1372 | Complex integer modes. (These are not currently implemented). | |
1373 | ||
1374 | @findex MODE_COMPLEX_FLOAT | |
1375 | @item MODE_COMPLEX_FLOAT | |
3f03ec2f | 1376 | Complex floating point modes. By default these are @code{QCmode}, |
1377 | @code{HCmode}, @code{SCmode}, @code{DCmode}, @code{XCmode}, and | |
1378 | @code{TCmode}. | |
5fc0eb84 | 1379 | |
1380 | @findex MODE_FUNCTION | |
1381 | @item MODE_FUNCTION | |
1382 | Algol or Pascal function variables including a static chain. | |
1383 | (These are not currently implemented). | |
1384 | ||
1385 | @findex MODE_CC | |
1386 | @item MODE_CC | |
1387 | Modes representing condition code values. These are @code{CCmode} plus | |
15b474a2 | 1388 | any @code{CC_MODE} modes listed in the @file{@var{machine}-modes.def}. |
fefe3807 | 1389 | @xref{Jump Patterns}, |
5fc0eb84 | 1390 | also see @ref{Condition Code}. |
1391 | ||
058a1b7a | 1392 | @findex MODE_POINTER_BOUNDS |
1393 | @item MODE_POINTER_BOUNDS | |
1394 | Pointer bounds modes. Used to represent values of pointer bounds type. | |
1395 | Operations in these modes may be executed as NOPs depending on hardware | |
1396 | features and environment setup. | |
1397 | ||
5fc0eb84 | 1398 | @findex MODE_RANDOM |
1399 | @item MODE_RANDOM | |
1400 | This is a catchall mode class for modes which don't fit into the above | |
1401 | classes. Currently @code{VOIDmode} and @code{BLKmode} are in | |
1402 | @code{MODE_RANDOM}. | |
1403 | @end table | |
1404 | ||
1405 | Here are some C macros that relate to machine modes: | |
1406 | ||
1407 | @table @code | |
1408 | @findex GET_MODE | |
1409 | @item GET_MODE (@var{x}) | |
1410 | Returns the machine mode of the RTX @var{x}. | |
1411 | ||
1412 | @findex PUT_MODE | |
1413 | @item PUT_MODE (@var{x}, @var{newmode}) | |
1414 | Alters the machine mode of the RTX @var{x} to be @var{newmode}. | |
1415 | ||
1416 | @findex NUM_MACHINE_MODES | |
1417 | @item NUM_MACHINE_MODES | |
1418 | Stands for the number of machine modes available on the target | |
1419 | machine. This is one greater than the largest numeric value of any | |
1420 | machine mode. | |
1421 | ||
1422 | @findex GET_MODE_NAME | |
1423 | @item GET_MODE_NAME (@var{m}) | |
1424 | Returns the name of mode @var{m} as a string. | |
1425 | ||
1426 | @findex GET_MODE_CLASS | |
1427 | @item GET_MODE_CLASS (@var{m}) | |
1428 | Returns the mode class of mode @var{m}. | |
1429 | ||
1430 | @findex GET_MODE_WIDER_MODE | |
1431 | @item GET_MODE_WIDER_MODE (@var{m}) | |
1432 | Returns the next wider natural mode. For example, the expression | |
1433 | @code{GET_MODE_WIDER_MODE (QImode)} returns @code{HImode}. | |
1434 | ||
1435 | @findex GET_MODE_SIZE | |
1436 | @item GET_MODE_SIZE (@var{m}) | |
1437 | Returns the size in bytes of a datum of mode @var{m}. | |
1438 | ||
1439 | @findex GET_MODE_BITSIZE | |
1440 | @item GET_MODE_BITSIZE (@var{m}) | |
1441 | Returns the size in bits of a datum of mode @var{m}. | |
1442 | ||
c559c639 | 1443 | @findex GET_MODE_IBIT |
1444 | @item GET_MODE_IBIT (@var{m}) | |
1445 | Returns the number of integral bits of a datum of fixed-point mode @var{m}. | |
1446 | ||
1447 | @findex GET_MODE_FBIT | |
1448 | @item GET_MODE_FBIT (@var{m}) | |
1449 | Returns the number of fractional bits of a datum of fixed-point mode @var{m}. | |
1450 | ||
5fc0eb84 | 1451 | @findex GET_MODE_MASK |
1452 | @item GET_MODE_MASK (@var{m}) | |
1453 | Returns a bitmask containing 1 for all bits in a word that fit within | |
1454 | mode @var{m}. This macro can only be used for modes whose bitsize is | |
1455 | less than or equal to @code{HOST_BITS_PER_INT}. | |
1456 | ||
1457 | @findex GET_MODE_ALIGNMENT | |
b80cbab1 | 1458 | @item GET_MODE_ALIGNMENT (@var{m}) |
5fc0eb84 | 1459 | Return the required alignment, in bits, for an object of mode @var{m}. |
1460 | ||
1461 | @findex GET_MODE_UNIT_SIZE | |
1462 | @item GET_MODE_UNIT_SIZE (@var{m}) | |
1463 | Returns the size in bytes of the subunits of a datum of mode @var{m}. | |
1464 | This is the same as @code{GET_MODE_SIZE} except in the case of complex | |
1465 | modes. For them, the unit size is the size of the real or imaginary | |
1466 | part. | |
1467 | ||
1468 | @findex GET_MODE_NUNITS | |
1469 | @item GET_MODE_NUNITS (@var{m}) | |
1470 | Returns the number of units contained in a mode, i.e., | |
1471 | @code{GET_MODE_SIZE} divided by @code{GET_MODE_UNIT_SIZE}. | |
1472 | ||
1473 | @findex GET_CLASS_NARROWEST_MODE | |
1474 | @item GET_CLASS_NARROWEST_MODE (@var{c}) | |
1475 | Returns the narrowest mode in mode class @var{c}. | |
1476 | @end table | |
1477 | ||
2cb32abf | 1478 | The following 3 variables are defined on every target. They can be |
f9cb58ae | 1479 | used to allocate buffers that are guaranteed to be large enough to |
2cb32abf | 1480 | hold any value that can be represented on the target. The first two |
1481 | can be overridden by defining them in the target's mode.def file, | |
1482 | however, the value must be a constant that can determined very early | |
1483 | in the compilation process. The third symbol cannot be overridden. | |
f9cb58ae | 1484 | |
1485 | @table @code | |
2cb32abf | 1486 | @findex BITS_PER_UNIT |
1487 | @item BITS_PER_UNIT | |
1488 | The number of bits in an addressable storage unit (byte). If you do | |
1489 | not define this, the default is 8. | |
1490 | ||
f9cb58ae | 1491 | @findex MAX_BITSIZE_MODE_ANY_INT |
1492 | @item MAX_BITSIZE_MODE_ANY_INT | |
2cb32abf | 1493 | The maximum bitsize of any mode that is used in integer math. This |
1494 | should be overridden by the target if it uses large integers as | |
1495 | containers for larger vectors but otherwise never uses the contents to | |
1496 | compute integer values. | |
f9cb58ae | 1497 | |
1498 | @findex MAX_BITSIZE_MODE_ANY_MODE | |
1499 | @item MAX_BITSIZE_MODE_ANY_MODE | |
1500 | The bitsize of the largest mode on the target. | |
1501 | @end table | |
1502 | ||
5fc0eb84 | 1503 | @findex byte_mode |
1504 | @findex word_mode | |
1505 | The global variables @code{byte_mode} and @code{word_mode} contain modes | |
1506 | whose classes are @code{MODE_INT} and whose bitsizes are either | |
1507 | @code{BITS_PER_UNIT} or @code{BITS_PER_WORD}, respectively. On 32-bit | |
1508 | machines, these are @code{QImode} and @code{SImode}, respectively. | |
1509 | ||
b3fb49ae | 1510 | @node Constants |
5fc0eb84 | 1511 | @section Constant Expression Types |
1512 | @cindex RTL constants | |
1513 | @cindex RTL constant expression types | |
1514 | ||
1515 | The simplest RTL expressions are those that represent constant values. | |
1516 | ||
1517 | @table @code | |
1518 | @findex const_int | |
1519 | @item (const_int @var{i}) | |
1520 | This type of expression represents the integer value @var{i}. @var{i} | |
1521 | is customarily accessed with the macro @code{INTVAL} as in | |
1522 | @code{INTVAL (@var{exp})}, which is equivalent to @code{XWINT (@var{exp}, 0)}. | |
1523 | ||
db20fb47 | 1524 | Constants generated for modes with fewer bits than in |
1525 | @code{HOST_WIDE_INT} must be sign extended to full width (e.g., with | |
1526 | @code{gen_int_mode}). For constants for modes with more bits than in | |
1527 | @code{HOST_WIDE_INT} the implied high order bits of that constant are | |
1528 | copies of the top bit. Note however that values are neither | |
1529 | inherently signed nor inherently unsigned; where necessary, signedness | |
1530 | is determined by the rtl operation instead. | |
51d3cd38 | 1531 | |
5fc0eb84 | 1532 | @findex const0_rtx |
1533 | @findex const1_rtx | |
1534 | @findex const2_rtx | |
1535 | @findex constm1_rtx | |
1536 | There is only one expression object for the integer value zero; it is | |
1537 | the value of the variable @code{const0_rtx}. Likewise, the only | |
1538 | expression for integer value one is found in @code{const1_rtx}, the only | |
1539 | expression for integer value two is found in @code{const2_rtx}, and the | |
1540 | only expression for integer value negative one is found in | |
1541 | @code{constm1_rtx}. Any attempt to create an expression of code | |
1542 | @code{const_int} and value zero, one, two or negative one will return | |
1543 | @code{const0_rtx}, @code{const1_rtx}, @code{const2_rtx} or | |
f36eeacd | 1544 | @code{constm1_rtx} as appropriate. |
5fc0eb84 | 1545 | |
1546 | @findex const_true_rtx | |
1547 | Similarly, there is only one object for the integer whose value is | |
1548 | @code{STORE_FLAG_VALUE}. It is found in @code{const_true_rtx}. If | |
1549 | @code{STORE_FLAG_VALUE} is one, @code{const_true_rtx} and | |
1550 | @code{const1_rtx} will point to the same object. If | |
8ae77b3c | 1551 | @code{STORE_FLAG_VALUE} is @minus{}1, @code{const_true_rtx} and |
f36eeacd | 1552 | @code{constm1_rtx} will point to the same object. |
5fc0eb84 | 1553 | |
1554 | @findex const_double | |
8990536a | 1555 | @item (const_double:@var{m} @var{i0} @var{i1} @dots{}) |
e913b5cd | 1556 | This represents either a floating-point constant of mode @var{m} or |
a342dbb2 | 1557 | (on older ports that do not define |
e913b5cd | 1558 | @code{TARGET_SUPPORTS_WIDE_INT}) an integer constant too large to fit |
1559 | into @code{HOST_BITS_PER_WIDE_INT} bits but small enough to fit within | |
a342dbb2 | 1560 | twice that number of bits. In the latter case, @var{m} will be |
e913b5cd | 1561 | @code{VOIDmode}. For integral values constants for modes with more |
1562 | bits than twice the number in @code{HOST_WIDE_INT} the implied high | |
1563 | order bits of that constant are copies of the top bit of | |
1564 | @code{CONST_DOUBLE_HIGH}. Note however that integral values are | |
1565 | neither inherently signed nor inherently unsigned; where necessary, | |
1566 | signedness is determined by the rtl operation instead. | |
1567 | ||
1568 | On more modern ports, @code{CONST_DOUBLE} only represents floating | |
b3fba3cd | 1569 | point values. New ports define @code{TARGET_SUPPORTS_WIDE_INT} to |
e913b5cd | 1570 | make this designation. |
5fc0eb84 | 1571 | |
8990536a | 1572 | @findex CONST_DOUBLE_LOW |
1573 | If @var{m} is @code{VOIDmode}, the bits of the value are stored in | |
1574 | @var{i0} and @var{i1}. @var{i0} is customarily accessed with the macro | |
1575 | @code{CONST_DOUBLE_LOW} and @var{i1} with @code{CONST_DOUBLE_HIGH}. | |
1576 | ||
1577 | If the constant is floating point (regardless of its precision), then | |
1578 | the number of integers used to store the value depends on the size of | |
1579 | @code{REAL_VALUE_TYPE} (@pxref{Floating Point}). The integers | |
1580 | represent a floating point number, but not precisely in the target | |
1581 | machine's or host machine's floating point format. To convert them to | |
1582 | the precise bit pattern used by the target machine, use the macro | |
1583 | @code{REAL_VALUE_TO_TARGET_DOUBLE} and friends (@pxref{Data Output}). | |
1584 | ||
e913b5cd | 1585 | @findex CONST_WIDE_INT |
1586 | @item (const_wide_int:@var{m} @var{nunits} @var{elt0} @dots{}) | |
b3fba3cd | 1587 | This contains an array of @code{HOST_WIDE_INT}s that is large enough |
e913b5cd | 1588 | to hold any constant that can be represented on the target. This form |
1589 | of rtl is only used on targets that define | |
a342dbb2 | 1590 | @code{TARGET_SUPPORTS_WIDE_INT} to be nonzero and then |
1591 | @code{CONST_DOUBLE}s are only used to hold floating-point values. If | |
e913b5cd | 1592 | the target leaves @code{TARGET_SUPPORTS_WIDE_INT} defined as 0, |
1593 | @code{CONST_WIDE_INT}s are not used and @code{CONST_DOUBLE}s are as | |
1594 | they were before. | |
1595 | ||
a342dbb2 | 1596 | The values are stored in a compressed format. The higher-order |
e913b5cd | 1597 | 0s or -1s are not represented if they are just the logical sign |
ddb1be65 | 1598 | extension of the number that is represented. |
e913b5cd | 1599 | |
1600 | @findex CONST_WIDE_INT_VEC | |
1601 | @item CONST_WIDE_INT_VEC (@var{code}) | |
1602 | Returns the entire array of @code{HOST_WIDE_INT}s that are used to | |
a342dbb2 | 1603 | store the value. This macro should be rarely used. |
e913b5cd | 1604 | |
1605 | @findex CONST_WIDE_INT_NUNITS | |
1606 | @item CONST_WIDE_INT_NUNITS (@var{code}) | |
1607 | The number of @code{HOST_WIDE_INT}s used to represent the number. | |
a342dbb2 | 1608 | Note that this generally is smaller than the number of |
e913b5cd | 1609 | @code{HOST_WIDE_INT}s implied by the mode size. |
1610 | ||
1611 | @findex CONST_WIDE_INT_ELT | |
1612 | @item CONST_WIDE_INT_NUNITS (@var{code},@var{i}) | |
1613 | Returns the @code{i}th element of the array. Element 0 is contains | |
1614 | the low order bits of the constant. | |
1615 | ||
e397ad8e | 1616 | @findex const_fixed |
8990536a | 1617 | @item (const_fixed:@var{m} @dots{}) |
e397ad8e | 1618 | Represents a fixed-point constant of mode @var{m}. |
8990536a | 1619 | The operand is a data structure of type @code{struct fixed_value} and |
1620 | is accessed with the macro @code{CONST_FIXED_VALUE}. The high part of | |
1621 | data is accessed with @code{CONST_FIXED_VALUE_HIGH}; the low part is | |
1622 | accessed with @code{CONST_FIXED_VALUE_LOW}. | |
e397ad8e | 1623 | |
886cfd4f | 1624 | @findex const_vector |
1625 | @item (const_vector:@var{m} [@var{x0} @var{x1} @dots{}]) | |
1626 | Represents a vector constant. The square brackets stand for the vector | |
1627 | containing the constant elements. @var{x0}, @var{x1} and so on are | |
0d57cc93 | 1628 | the @code{const_int}, @code{const_double} or @code{const_fixed} elements. |
886cfd4f | 1629 | |
1630 | The number of units in a @code{const_vector} is obtained with the macro | |
1631 | @code{CONST_VECTOR_NUNITS} as in @code{CONST_VECTOR_NUNITS (@var{v})}. | |
1632 | ||
1633 | Individual elements in a vector constant are accessed with the macro | |
e981b81b | 1634 | @code{CONST_VECTOR_ELT} as in @code{CONST_VECTOR_ELT (@var{v}, @var{n})} |
886cfd4f | 1635 | where @var{v} is the vector constant and @var{n} is the element |
1636 | desired. | |
1637 | ||
5fc0eb84 | 1638 | @findex const_string |
1639 | @item (const_string @var{str}) | |
1640 | Represents a constant string with value @var{str}. Currently this is | |
1641 | used only for insn attributes (@pxref{Insn Attributes}) since constant | |
1642 | strings in C are placed in memory. | |
1643 | ||
1644 | @findex symbol_ref | |
1645 | @item (symbol_ref:@var{mode} @var{symbol}) | |
1646 | Represents the value of an assembler label for data. @var{symbol} is | |
1647 | a string that describes the name of the assembler label. If it starts | |
1648 | with a @samp{*}, the label is the rest of @var{symbol} not including | |
1649 | the @samp{*}. Otherwise, the label is @var{symbol}, usually prefixed | |
1650 | with @samp{_}. | |
1651 | ||
1652 | The @code{symbol_ref} contains a mode, which is usually @code{Pmode}. | |
1653 | Usually that is the only mode for which a symbol is directly valid. | |
1654 | ||
1655 | @findex label_ref | |
514b43f8 | 1656 | @item (label_ref:@var{mode} @var{label}) |
5fc0eb84 | 1657 | Represents the value of an assembler label for code. It contains one |
ac2fdb7a | 1658 | operand, an expression, which must be a @code{code_label} or a @code{note} |
1659 | of type @code{NOTE_INSN_DELETED_LABEL} that appears in the instruction | |
1660 | sequence to identify the place where the label should go. | |
5fc0eb84 | 1661 | |
1662 | The reason for using a distinct expression type for code label | |
1663 | references is so that jump optimization can distinguish them. | |
1664 | ||
514b43f8 | 1665 | The @code{label_ref} contains a mode, which is usually @code{Pmode}. |
1666 | Usually that is the only mode for which a label is directly valid. | |
1667 | ||
8990536a | 1668 | @findex const |
5fc0eb84 | 1669 | @item (const:@var{m} @var{exp}) |
1670 | Represents a constant that is the result of an assembly-time | |
1671 | arithmetic computation. The operand, @var{exp}, is an expression that | |
1672 | contains only constants (@code{const_int}, @code{symbol_ref} and | |
1673 | @code{label_ref} expressions) combined with @code{plus} and | |
1674 | @code{minus}. However, not all combinations are valid, since the | |
1675 | assembler cannot do arbitrary arithmetic on relocatable symbols. | |
1676 | ||
1677 | @var{m} should be @code{Pmode}. | |
1678 | ||
1679 | @findex high | |
1680 | @item (high:@var{m} @var{exp}) | |
1681 | Represents the high-order bits of @var{exp}, usually a | |
1682 | @code{symbol_ref}. The number of bits is machine-dependent and is | |
1683 | normally the number of bits specified in an instruction that initializes | |
1684 | the high order bits of a register. It is used with @code{lo_sum} to | |
1685 | represent the typical two-instruction sequence used in RISC machines to | |
1686 | reference a global memory location. | |
1687 | ||
1688 | @var{m} should be @code{Pmode}. | |
1689 | @end table | |
1690 | ||
8990536a | 1691 | @findex CONST0_RTX |
1692 | @findex CONST1_RTX | |
1693 | @findex CONST2_RTX | |
1694 | The macro @code{CONST0_RTX (@var{mode})} refers to an expression with | |
1695 | value 0 in mode @var{mode}. If mode @var{mode} is of mode class | |
1696 | @code{MODE_INT}, it returns @code{const0_rtx}. If mode @var{mode} is of | |
1697 | mode class @code{MODE_FLOAT}, it returns a @code{CONST_DOUBLE} | |
1698 | expression in mode @var{mode}. Otherwise, it returns a | |
1699 | @code{CONST_VECTOR} expression in mode @var{mode}. Similarly, the macro | |
1700 | @code{CONST1_RTX (@var{mode})} refers to an expression with value 1 in | |
1701 | mode @var{mode} and similarly for @code{CONST2_RTX}. The | |
1702 | @code{CONST1_RTX} and @code{CONST2_RTX} macros are undefined | |
1703 | for vector modes. | |
1704 | ||
b3fb49ae | 1705 | @node Regs and Memory |
5fc0eb84 | 1706 | @section Registers and Memory |
1707 | @cindex RTL register expressions | |
1708 | @cindex RTL memory expressions | |
1709 | ||
1710 | Here are the RTL expression types for describing access to machine | |
1711 | registers and to main memory. | |
1712 | ||
1713 | @table @code | |
1714 | @findex reg | |
1715 | @cindex hard registers | |
1716 | @cindex pseudo registers | |
1717 | @item (reg:@var{m} @var{n}) | |
1718 | For small values of the integer @var{n} (those that are less than | |
1719 | @code{FIRST_PSEUDO_REGISTER}), this stands for a reference to machine | |
1720 | register number @var{n}: a @dfn{hard register}. For larger values of | |
1721 | @var{n}, it stands for a temporary value or @dfn{pseudo register}. | |
1722 | The compiler's strategy is to generate code assuming an unlimited | |
1723 | number of such pseudo registers, and later convert them into hard | |
1724 | registers or into memory references. | |
1725 | ||
1726 | @var{m} is the machine mode of the reference. It is necessary because | |
1727 | machines can generally refer to each register in more than one mode. | |
1728 | For example, a register may contain a full word but there may be | |
1729 | instructions to refer to it as a half word or as a single byte, as | |
1730 | well as instructions to refer to it as a floating point number of | |
1731 | various precisions. | |
1732 | ||
1733 | Even for a register that the machine can access in only one mode, | |
1734 | the mode must always be specified. | |
1735 | ||
1736 | The symbol @code{FIRST_PSEUDO_REGISTER} is defined by the machine | |
1737 | description, since the number of hard registers on the machine is an | |
1738 | invariant characteristic of the machine. Note, however, that not | |
1739 | all of the machine registers must be general registers. All the | |
1740 | machine registers that can be used for storage of data are given | |
1741 | hard register numbers, even those that can be used only in certain | |
1742 | instructions or can hold only certain types of data. | |
1743 | ||
1744 | A hard register may be accessed in various modes throughout one | |
1745 | function, but each pseudo register is given a natural mode | |
1746 | and is accessed only in that mode. When it is necessary to describe | |
1747 | an access to a pseudo register using a nonnatural mode, a @code{subreg} | |
1748 | expression is used. | |
1749 | ||
1750 | A @code{reg} expression with a machine mode that specifies more than | |
1751 | one word of data may actually stand for several consecutive registers. | |
1752 | If in addition the register number specifies a hardware register, then | |
1753 | it actually represents several consecutive hardware registers starting | |
1754 | with the specified one. | |
1755 | ||
1756 | Each pseudo register number used in a function's RTL code is | |
1757 | represented by a unique @code{reg} expression. | |
1758 | ||
1759 | @findex FIRST_VIRTUAL_REGISTER | |
1760 | @findex LAST_VIRTUAL_REGISTER | |
1761 | Some pseudo register numbers, those within the range of | |
1762 | @code{FIRST_VIRTUAL_REGISTER} to @code{LAST_VIRTUAL_REGISTER} only | |
1763 | appear during the RTL generation phase and are eliminated before the | |
1764 | optimization phases. These represent locations in the stack frame that | |
1765 | cannot be determined until RTL generation for the function has been | |
1766 | completed. The following virtual register numbers are defined: | |
1767 | ||
1768 | @table @code | |
1769 | @findex VIRTUAL_INCOMING_ARGS_REGNUM | |
1770 | @item VIRTUAL_INCOMING_ARGS_REGNUM | |
1771 | This points to the first word of the incoming arguments passed on the | |
1772 | stack. Normally these arguments are placed there by the caller, but the | |
1773 | callee may have pushed some arguments that were previously passed in | |
1774 | registers. | |
1775 | ||
1776 | @cindex @code{FIRST_PARM_OFFSET} and virtual registers | |
1777 | @cindex @code{ARG_POINTER_REGNUM} and virtual registers | |
1778 | When RTL generation is complete, this virtual register is replaced | |
1779 | by the sum of the register given by @code{ARG_POINTER_REGNUM} and the | |
1780 | value of @code{FIRST_PARM_OFFSET}. | |
1781 | ||
1782 | @findex VIRTUAL_STACK_VARS_REGNUM | |
1783 | @cindex @code{FRAME_GROWS_DOWNWARD} and virtual registers | |
1784 | @item VIRTUAL_STACK_VARS_REGNUM | |
3ce7ff97 | 1785 | If @code{FRAME_GROWS_DOWNWARD} is defined to a nonzero value, this points |
d28d5017 | 1786 | to immediately above the first variable on the stack. Otherwise, it points |
1787 | to the first variable on the stack. | |
5fc0eb84 | 1788 | |
1789 | @cindex @code{STARTING_FRAME_OFFSET} and virtual registers | |
1790 | @cindex @code{FRAME_POINTER_REGNUM} and virtual registers | |
1791 | @code{VIRTUAL_STACK_VARS_REGNUM} is replaced with the sum of the | |
1792 | register given by @code{FRAME_POINTER_REGNUM} and the value | |
1793 | @code{STARTING_FRAME_OFFSET}. | |
1794 | ||
1795 | @findex VIRTUAL_STACK_DYNAMIC_REGNUM | |
1796 | @item VIRTUAL_STACK_DYNAMIC_REGNUM | |
1797 | This points to the location of dynamically allocated memory on the stack | |
1798 | immediately after the stack pointer has been adjusted by the amount of | |
1799 | memory desired. | |
1800 | ||
1801 | @cindex @code{STACK_DYNAMIC_OFFSET} and virtual registers | |
1802 | @cindex @code{STACK_POINTER_REGNUM} and virtual registers | |
1803 | This virtual register is replaced by the sum of the register given by | |
1804 | @code{STACK_POINTER_REGNUM} and the value @code{STACK_DYNAMIC_OFFSET}. | |
1805 | ||
1806 | @findex VIRTUAL_OUTGOING_ARGS_REGNUM | |
1807 | @item VIRTUAL_OUTGOING_ARGS_REGNUM | |
1808 | This points to the location in the stack at which outgoing arguments | |
1809 | should be written when the stack is pre-pushed (arguments pushed using | |
1810 | push insns should always use @code{STACK_POINTER_REGNUM}). | |
1811 | ||
1812 | @cindex @code{STACK_POINTER_OFFSET} and virtual registers | |
1813 | This virtual register is replaced by the sum of the register given by | |
1814 | @code{STACK_POINTER_REGNUM} and the value @code{STACK_POINTER_OFFSET}. | |
1815 | @end table | |
1816 | ||
1817 | @findex subreg | |
6cbc0aeb | 1818 | @item (subreg:@var{m1} @var{reg:m2} @var{bytenum}) |
1819 | ||
5fc0eb84 | 1820 | @code{subreg} expressions are used to refer to a register in a machine |
1821 | mode other than its natural one, or to refer to one register of | |
701e46d0 | 1822 | a multi-part @code{reg} that actually refers to several registers. |
5fc0eb84 | 1823 | |
6cbc0aeb | 1824 | Each pseudo register has a natural mode. If it is necessary to |
14c9ac55 | 1825 | operate on it in a different mode, the register must be |
15b474a2 | 1826 | enclosed in a @code{subreg}. |
6cbc0aeb | 1827 | |
14c9ac55 | 1828 | There are currently three supported types for the first operand of a |
1829 | @code{subreg}: | |
1830 | @itemize | |
1831 | @item pseudo registers | |
1832 | This is the most common case. Most @code{subreg}s have pseudo | |
1833 | @code{reg}s as their first operand. | |
1834 | ||
1835 | @item mem | |
1836 | @code{subreg}s of @code{mem} were common in earlier versions of GCC and | |
1837 | are still supported. During the reload pass these are replaced by plain | |
1838 | @code{mem}s. On machines that do not do instruction scheduling, use of | |
1839 | @code{subreg}s of @code{mem} are still used, but this is no longer | |
1840 | recommended. Such @code{subreg}s are considered to be | |
1841 | @code{register_operand}s rather than @code{memory_operand}s before and | |
1842 | during reload. Because of this, the scheduling passes cannot properly | |
1843 | schedule instructions with @code{subreg}s of @code{mem}, so for machines | |
1844 | that do scheduling, @code{subreg}s of @code{mem} should never be used. | |
1845 | To support this, the combine and recog passes have explicit code to | |
1846 | inhibit the creation of @code{subreg}s of @code{mem} when | |
1847 | @code{INSN_SCHEDULING} is defined. | |
1848 | ||
1849 | The use of @code{subreg}s of @code{mem} after the reload pass is an area | |
1850 | that is not well understood and should be avoided. There is still some | |
1851 | code in the compiler to support this, but this code has possibly rotted. | |
1852 | This use of @code{subreg}s is discouraged and will most likely not be | |
1853 | supported in the future. | |
1854 | ||
1855 | @item hard registers | |
6cbc0aeb | 1856 | It is seldom necessary to wrap hard registers in @code{subreg}s; such |
1857 | registers would normally reduce to a single @code{reg} rtx. This use of | |
14c9ac55 | 1858 | @code{subreg}s is discouraged and may not be supported in the future. |
1859 | ||
1860 | @end itemize | |
1861 | ||
1862 | @code{subreg}s of @code{subreg}s are not supported. Using | |
1863 | @code{simplify_gen_subreg} is the recommended way to avoid this problem. | |
6cbc0aeb | 1864 | |
1865 | @code{subreg}s come in two distinct flavors, each having its own | |
1866 | usage and rules: | |
1867 | ||
1868 | @table @asis | |
1869 | @item Paradoxical subregs | |
1870 | When @var{m1} is strictly wider than @var{m2}, the @code{subreg} | |
1871 | expression is called @dfn{paradoxical}. The canonical test for this | |
1872 | class of @code{subreg} is: | |
1873 | ||
1874 | @smallexample | |
1875 | GET_MODE_SIZE (@var{m1}) > GET_MODE_SIZE (@var{m2}) | |
1876 | @end smallexample | |
1877 | ||
1878 | Paradoxical @code{subreg}s can be used as both lvalues and rvalues. | |
14c9ac55 | 1879 | When used as an lvalue, the low-order bits of the source value |
1880 | are stored in @var{reg} and the high-order bits are discarded. | |
6cbc0aeb | 1881 | When used as an rvalue, the low-order bits of the @code{subreg} are |
14c9ac55 | 1882 | taken from @var{reg} while the high-order bits may or may not be |
15b474a2 | 1883 | defined. |
14c9ac55 | 1884 | |
1885 | The high-order bits of rvalues are in the following circumstances: | |
1886 | ||
1887 | @itemize | |
1888 | @item @code{subreg}s of @code{mem} | |
1889 | When @var{m2} is smaller than a word, the macro @code{LOAD_EXTEND_OP}, | |
1890 | can control how the high-order bits are defined. | |
1891 | ||
1892 | @item @code{subreg} of @code{reg}s | |
1893 | The upper bits are defined when @code{SUBREG_PROMOTED_VAR_P} is true. | |
1894 | @code{SUBREG_PROMOTED_UNSIGNED_P} describes what the upper bits hold. | |
1895 | Such subregs usually represent local variables, register variables | |
1896 | and parameter pseudo variables that have been promoted to a wider mode. | |
1897 | ||
1898 | @end itemize | |
6cbc0aeb | 1899 | |
1900 | @var{bytenum} is always zero for a paradoxical @code{subreg}, even on | |
1901 | big-endian targets. | |
1902 | ||
1903 | For example, the paradoxical @code{subreg}: | |
1904 | ||
1905 | @smallexample | |
1906 | (set (subreg:SI (reg:HI @var{x}) 0) @var{y}) | |
1907 | @end smallexample | |
1908 | ||
1909 | stores the lower 2 bytes of @var{y} in @var{x} and discards the upper | |
1910 | 2 bytes. A subsequent: | |
5fc0eb84 | 1911 | |
6cbc0aeb | 1912 | @smallexample |
1913 | (set @var{z} (subreg:SI (reg:HI @var{x}) 0)) | |
1914 | @end smallexample | |
1915 | ||
14c9ac55 | 1916 | would set the lower two bytes of @var{z} to @var{y} and set the upper |
1917 | two bytes to an unknown value assuming @code{SUBREG_PROMOTED_VAR_P} is | |
1918 | false. | |
6cbc0aeb | 1919 | |
15b474a2 | 1920 | @item Normal subregs |
6cbc0aeb | 1921 | When @var{m1} is at least as narrow as @var{m2} the @code{subreg} |
1922 | expression is called @dfn{normal}. | |
1923 | ||
14c9ac55 | 1924 | Normal @code{subreg}s restrict consideration to certain bits of |
1925 | @var{reg}. There are two cases. If @var{m1} is smaller than a word, | |
1926 | the @code{subreg} refers to the least-significant part (or | |
1927 | @dfn{lowpart}) of one word of @var{reg}. If @var{m1} is word-sized or | |
1928 | greater, the @code{subreg} refers to one or more complete words. | |
6cbc0aeb | 1929 | |
1930 | When used as an lvalue, @code{subreg} is a word-based accessor. | |
1931 | Storing to a @code{subreg} modifies all the words of @var{reg} that | |
1932 | overlap the @code{subreg}, but it leaves the other words of @var{reg} | |
1933 | alone. | |
1934 | ||
1935 | When storing to a normal @code{subreg} that is smaller than a word, | |
1936 | the other bits of the referenced word are usually left in an undefined | |
1937 | state. This laxity makes it easier to generate efficient code for | |
1938 | such instructions. To represent an instruction that preserves all the | |
1939 | bits outside of those in the @code{subreg}, use @code{strict_low_part} | |
1940 | or @code{zero_extract} around the @code{subreg}. | |
1941 | ||
1942 | @var{bytenum} must identify the offset of the first byte of the | |
1943 | @code{subreg} from the start of @var{reg}, assuming that @var{reg} is | |
1944 | laid out in memory order. The memory order of bytes is defined by | |
1945 | two target macros, @code{WORDS_BIG_ENDIAN} and @code{BYTES_BIG_ENDIAN}: | |
1946 | ||
1947 | @itemize | |
1948 | @item | |
5fc0eb84 | 1949 | @cindex @code{WORDS_BIG_ENDIAN}, effect on @code{subreg} |
6cbc0aeb | 1950 | @code{WORDS_BIG_ENDIAN}, if set to 1, says that byte number zero is |
1951 | part of the most significant word; otherwise, it is part of the least | |
1952 | significant word. | |
701e46d0 | 1953 | |
6cbc0aeb | 1954 | @item |
701e46d0 | 1955 | @cindex @code{BYTES_BIG_ENDIAN}, effect on @code{subreg} |
6cbc0aeb | 1956 | @code{BYTES_BIG_ENDIAN}, if set to 1, says that byte number zero is |
1957 | the most significant byte within a word; otherwise, it is the least | |
1958 | significant byte within a word. | |
1959 | @end itemize | |
5fc0eb84 | 1960 | |
03ccabb4 | 1961 | @cindex @code{FLOAT_WORDS_BIG_ENDIAN}, (lack of) effect on @code{subreg} |
1962 | On a few targets, @code{FLOAT_WORDS_BIG_ENDIAN} disagrees with | |
6cbc0aeb | 1963 | @code{WORDS_BIG_ENDIAN}. However, most parts of the compiler treat |
1964 | floating point values as if they had the same endianness as integer | |
1965 | values. This works because they handle them solely as a collection of | |
1966 | integer values, with no particular numerical value. Only real.c and | |
1967 | the runtime libraries care about @code{FLOAT_WORDS_BIG_ENDIAN}. | |
1968 | ||
15b474a2 | 1969 | Thus, |
6cbc0aeb | 1970 | |
1971 | @smallexample | |
1972 | (subreg:HI (reg:SI @var{x}) 2) | |
1973 | @end smallexample | |
1974 | ||
1975 | on a @code{BYTES_BIG_ENDIAN}, @samp{UNITS_PER_WORD == 4} target is the same as | |
1976 | ||
1977 | @smallexample | |
1978 | (subreg:HI (reg:SI @var{x}) 0) | |
1979 | @end smallexample | |
1980 | ||
1981 | on a little-endian, @samp{UNITS_PER_WORD == 4} target. Both | |
1982 | @code{subreg}s access the lower two bytes of register @var{x}. | |
1983 | ||
1984 | @end table | |
1985 | ||
1986 | A @code{MODE_PARTIAL_INT} mode behaves as if it were as wide as the | |
1987 | corresponding @code{MODE_INT} mode, except that it has an unknown | |
1988 | number of undefined bits. For example: | |
1989 | ||
1990 | @smallexample | |
1991 | (subreg:PSI (reg:SI 0) 0) | |
1992 | @end smallexample | |
1993 | ||
1994 | accesses the whole of @samp{(reg:SI 0)}, but the exact relationship | |
1995 | between the @code{PSImode} value and the @code{SImode} value is not | |
1996 | defined. If we assume @samp{UNITS_PER_WORD <= 4}, then the following | |
1997 | two @code{subreg}s: | |
1998 | ||
1999 | @smallexample | |
2000 | (subreg:PSI (reg:DI 0) 0) | |
2001 | (subreg:PSI (reg:DI 0) 4) | |
2002 | @end smallexample | |
2003 | ||
2004 | represent independent 4-byte accesses to the two halves of | |
2005 | @samp{(reg:DI 0)}. Both @code{subreg}s have an unknown number | |
2006 | of undefined bits. | |
2007 | ||
2008 | If @samp{UNITS_PER_WORD <= 2} then these two @code{subreg}s: | |
2009 | ||
2010 | @smallexample | |
2011 | (subreg:HI (reg:PSI 0) 0) | |
2012 | (subreg:HI (reg:PSI 0) 2) | |
2013 | @end smallexample | |
2014 | ||
2015 | represent independent 2-byte accesses that together span the whole | |
2016 | of @samp{(reg:PSI 0)}. Storing to the first @code{subreg} does not | |
2017 | affect the value of the second, and vice versa. @samp{(reg:PSI 0)} | |
2018 | has an unknown number of undefined bits, so the assignment: | |
2019 | ||
2020 | @smallexample | |
2021 | (set (subreg:HI (reg:PSI 0) 0) (reg:HI 4)) | |
2022 | @end smallexample | |
2023 | ||
2024 | does not guarantee that @samp{(subreg:HI (reg:PSI 0) 0)} has the | |
2025 | value @samp{(reg:HI 4)}. | |
2026 | ||
2027 | @cindex @code{CANNOT_CHANGE_MODE_CLASS} and subreg semantics | |
2028 | The rules above apply to both pseudo @var{reg}s and hard @var{reg}s. | |
2029 | If the semantics are not correct for particular combinations of | |
2030 | @var{m1}, @var{m2} and hard @var{reg}, the target-specific code | |
2031 | must ensure that those combinations are never used. For example: | |
2032 | ||
2033 | @smallexample | |
2034 | CANNOT_CHANGE_MODE_CLASS (@var{m2}, @var{m1}, @var{class}) | |
2035 | @end smallexample | |
2036 | ||
2037 | must be true for every class @var{class} that includes @var{reg}. | |
5fc0eb84 | 2038 | |
2039 | @findex SUBREG_REG | |
701e46d0 | 2040 | @findex SUBREG_BYTE |
77f71523 | 2041 | The first operand of a @code{subreg} expression is customarily accessed |
5fc0eb84 | 2042 | with the @code{SUBREG_REG} macro and the second operand is customarily |
701e46d0 | 2043 | accessed with the @code{SUBREG_BYTE} macro. |
5fc0eb84 | 2044 | |
6cbc0aeb | 2045 | It has been several years since a platform in which |
14c9ac55 | 2046 | @code{BYTES_BIG_ENDIAN} not equal to @code{WORDS_BIG_ENDIAN} has |
6cbc0aeb | 2047 | been tested. Anyone wishing to support such a platform in the future |
2048 | may be confronted with code rot. | |
2049 | ||
5fc0eb84 | 2050 | @findex scratch |
2051 | @cindex scratch operands | |
2052 | @item (scratch:@var{m}) | |
2053 | This represents a scratch register that will be required for the | |
2054 | execution of a single instruction and not used subsequently. It is | |
2055 | converted into a @code{reg} by either the local register allocator or | |
2056 | the reload pass. | |
2057 | ||
2058 | @code{scratch} is usually present inside a @code{clobber} operation | |
2059 | (@pxref{Side Effects}). | |
2060 | ||
2061 | @findex cc0 | |
2062 | @cindex condition code register | |
2063 | @item (cc0) | |
2064 | This refers to the machine's condition code register. It has no | |
2065 | operands and may not have a machine mode. There are two ways to use it: | |
2066 | ||
2067 | @itemize @bullet | |
2068 | @item | |
2069 | To stand for a complete set of condition code flags. This is best on | |
2070 | most machines, where each comparison sets the entire series of flags. | |
2071 | ||
2072 | With this technique, @code{(cc0)} may be validly used in only two | |
2073 | contexts: as the destination of an assignment (in test and compare | |
2074 | instructions) and in comparison operators comparing against zero | |
2075 | (@code{const_int} with value zero; that is to say, @code{const0_rtx}). | |
2076 | ||
2077 | @item | |
2078 | To stand for a single flag that is the result of a single condition. | |
2079 | This is useful on machines that have only a single flag bit, and in | |
2080 | which comparison instructions must specify the condition to test. | |
2081 | ||
2082 | With this technique, @code{(cc0)} may be validly used in only two | |
2083 | contexts: as the destination of an assignment (in test and compare | |
2084 | instructions) where the source is a comparison operator, and as the | |
2085 | first operand of @code{if_then_else} (in a conditional branch). | |
2086 | @end itemize | |
2087 | ||
2088 | @findex cc0_rtx | |
2089 | There is only one expression object of code @code{cc0}; it is the | |
2090 | value of the variable @code{cc0_rtx}. Any attempt to create an | |
2091 | expression of code @code{cc0} will return @code{cc0_rtx}. | |
2092 | ||
2093 | Instructions can set the condition code implicitly. On many machines, | |
2094 | nearly all instructions set the condition code based on the value that | |
2095 | they compute or store. It is not necessary to record these actions | |
2096 | explicitly in the RTL because the machine description includes a | |
2097 | prescription for recognizing the instructions that do so (by means of | |
2098 | the macro @code{NOTICE_UPDATE_CC}). @xref{Condition Code}. Only | |
2099 | instructions whose sole purpose is to set the condition code, and | |
2100 | instructions that use the condition code, need mention @code{(cc0)}. | |
2101 | ||
2102 | On some machines, the condition code register is given a register number | |
2103 | and a @code{reg} is used instead of @code{(cc0)}. This is usually the | |
2104 | preferable approach if only a small subset of instructions modify the | |
2105 | condition code. Other machines store condition codes in general | |
2106 | registers; in such cases a pseudo register should be used. | |
2107 | ||
7800959d | 2108 | Some machines, such as the SPARC and RS/6000, have two sets of |
5fc0eb84 | 2109 | arithmetic instructions, one that sets and one that does not set the |
2110 | condition code. This is best handled by normally generating the | |
2111 | instruction that does not set the condition code, and making a pattern | |
2112 | that both performs the arithmetic and sets the condition code register | |
2113 | (which would not be @code{(cc0)} in this case). For examples, search | |
2114 | for @samp{addcc} and @samp{andcc} in @file{sparc.md}. | |
2115 | ||
2116 | @findex pc | |
2117 | @item (pc) | |
2118 | @cindex program counter | |
2119 | This represents the machine's program counter. It has no operands and | |
2120 | may not have a machine mode. @code{(pc)} may be validly used only in | |
2121 | certain specific contexts in jump instructions. | |
2122 | ||
2123 | @findex pc_rtx | |
2124 | There is only one expression object of code @code{pc}; it is the value | |
2125 | of the variable @code{pc_rtx}. Any attempt to create an expression of | |
2126 | code @code{pc} will return @code{pc_rtx}. | |
2127 | ||
2128 | All instructions that do not jump alter the program counter implicitly | |
0858e3a2 | 2129 | by incrementing it, but there is no need to mention this in the RTL@. |
5fc0eb84 | 2130 | |
2131 | @findex mem | |
42d17561 | 2132 | @item (mem:@var{m} @var{addr} @var{alias}) |
5fc0eb84 | 2133 | This RTX represents a reference to main memory at an address |
2134 | represented by the expression @var{addr}. @var{m} specifies how large | |
71d6ad5e | 2135 | a unit of memory is accessed. @var{alias} specifies an alias set for the |
2136 | reference. In general two items are in different alias sets if they cannot | |
42d17561 | 2137 | reference the same memory address. |
0dbd1c74 | 2138 | |
3986e66f | 2139 | The construct @code{(mem:BLK (scratch))} is considered to alias all |
2140 | other memories. Thus it may be used as a memory barrier in epilogue | |
2141 | stack deallocation patterns. | |
2142 | ||
1a6a0f2a | 2143 | @findex concat |
2144 | @item (concat@var{m} @var{rtx} @var{rtx}) | |
2145 | This RTX represents the concatenation of two other RTXs. This is used | |
2146 | for complex values. It should only appear in the RTL attached to | |
2147 | declarations and during RTL generation. It should not appear in the | |
2148 | ordinary insn chain. | |
2149 | ||
2150 | @findex concatn | |
7a5a9c54 | 2151 | @item (concatn@var{m} [@var{rtx} @dots{}]) |
1a6a0f2a | 2152 | This RTX represents the concatenation of all the @var{rtx} to make a |
2153 | single value. Like @code{concat}, this should only appear in | |
2154 | declarations, and not in the insn chain. | |
5fc0eb84 | 2155 | @end table |
2156 | ||
b3fb49ae | 2157 | @node Arithmetic |
5fc0eb84 | 2158 | @section RTL Expressions for Arithmetic |
2159 | @cindex arithmetic, in RTL | |
2160 | @cindex math, in RTL | |
2161 | @cindex RTL expressions for arithmetic | |
2162 | ||
2163 | Unless otherwise specified, all the operands of arithmetic expressions | |
2164 | must be valid for mode @var{m}. An operand is valid for mode @var{m} | |
2165 | if it has mode @var{m}, or if it is a @code{const_int} or | |
2166 | @code{const_double} and @var{m} is a mode of class @code{MODE_INT}. | |
2167 | ||
2168 | For commutative binary operations, constants should be placed in the | |
2169 | second operand. | |
2170 | ||
2171 | @table @code | |
2172 | @findex plus | |
c480d0a9 | 2173 | @findex ss_plus |
2174 | @findex us_plus | |
5fc0eb84 | 2175 | @cindex RTL sum |
c480d0a9 | 2176 | @cindex RTL addition |
2177 | @cindex RTL addition with signed saturation | |
2178 | @cindex RTL addition with unsigned saturation | |
5fc0eb84 | 2179 | @item (plus:@var{m} @var{x} @var{y}) |
c480d0a9 | 2180 | @itemx (ss_plus:@var{m} @var{x} @var{y}) |
2181 | @itemx (us_plus:@var{m} @var{x} @var{y}) | |
5fc0eb84 | 2182 | |
c480d0a9 | 2183 | These three expressions all represent the sum of the values |
2184 | represented by @var{x} and @var{y} carried out in machine mode | |
2185 | @var{m}. They differ in their behavior on overflow of integer modes. | |
2186 | @code{plus} wraps round modulo the width of @var{m}; @code{ss_plus} | |
2187 | saturates at the maximum signed value representable in @var{m}; | |
2188 | @code{us_plus} saturates at the maximum unsigned value. | |
5fc0eb84 | 2189 | |
c480d0a9 | 2190 | @c ??? What happens on overflow of floating point modes? |
5fc0eb84 | 2191 | |
c480d0a9 | 2192 | @findex lo_sum |
2193 | @item (lo_sum:@var{m} @var{x} @var{y}) | |
35a03fc8 | 2194 | |
c480d0a9 | 2195 | This expression represents the sum of @var{x} and the low-order bits |
2196 | of @var{y}. It is used with @code{high} (@pxref{Constants}) to | |
2197 | represent the typical two-instruction sequence used in RISC machines | |
09c8496f | 2198 | to reference a global memory location. |
35a03fc8 | 2199 | |
c480d0a9 | 2200 | The number of low order bits is machine-dependent but is |
2201 | normally the number of bits in a @code{Pmode} item minus the number of | |
2202 | bits set by @code{high}. | |
35a03fc8 | 2203 | |
c480d0a9 | 2204 | @var{m} should be @code{Pmode}. |
35a03fc8 | 2205 | |
c480d0a9 | 2206 | @findex minus |
35a03fc8 | 2207 | @findex ss_minus |
35a03fc8 | 2208 | @findex us_minus |
c480d0a9 | 2209 | @cindex RTL difference |
2210 | @cindex RTL subtraction | |
2211 | @cindex RTL subtraction with signed saturation | |
2212 | @cindex RTL subtraction with unsigned saturation | |
2213 | @item (minus:@var{m} @var{x} @var{y}) | |
2214 | @itemx (ss_minus:@var{m} @var{x} @var{y}) | |
2215 | @itemx (us_minus:@var{m} @var{x} @var{y}) | |
35a03fc8 | 2216 | |
c480d0a9 | 2217 | These three expressions represent the result of subtracting @var{y} |
2218 | from @var{x}, carried out in mode @var{M}. Behavior on overflow is | |
2219 | the same as for the three variants of @code{plus} (see above). | |
35a03fc8 | 2220 | |
5fc0eb84 | 2221 | @findex compare |
2222 | @cindex RTL comparison | |
2223 | @item (compare:@var{m} @var{x} @var{y}) | |
2224 | Represents the result of subtracting @var{y} from @var{x} for purposes | |
2225 | of comparison. The result is computed without overflow, as if with | |
2226 | infinite precision. | |
2227 | ||
2228 | Of course, machines can't really subtract with infinite precision. | |
7513a387 | 2229 | However, they can pretend to do so when only the sign of the result will |
2230 | be used, which is the case when the result is stored in the condition | |
2231 | code. And that is the @emph{only} way this kind of expression may | |
2232 | validly be used: as a value to be stored in the condition codes, either | |
71d6ad5e | 2233 | @code{(cc0)} or a register. @xref{Comparisons}. |
7513a387 | 2234 | |
2235 | The mode @var{m} is not related to the modes of @var{x} and @var{y}, but | |
2236 | instead is the mode of the condition code value. If @code{(cc0)} is | |
2237 | used, it is @code{VOIDmode}. Otherwise it is some mode in class | |
2238 | @code{MODE_CC}, often @code{CCmode}. @xref{Condition Code}. If @var{m} | |
2239 | is @code{VOIDmode} or @code{CCmode}, the operation returns sufficient | |
2240 | information (in an unspecified format) so that any comparison operator | |
2241 | can be applied to the result of the @code{COMPARE} operation. For other | |
2242 | modes in class @code{MODE_CC}, the operation only returns a subset of | |
2243 | this information. | |
5fc0eb84 | 2244 | |
2245 | Normally, @var{x} and @var{y} must have the same mode. Otherwise, | |
2246 | @code{compare} is valid only if the mode of @var{x} is in class | |
2247 | @code{MODE_INT} and @var{y} is a @code{const_int} or | |
2248 | @code{const_double} with mode @code{VOIDmode}. The mode of @var{x} | |
2249 | determines what mode the comparison is to be done in; thus it must not | |
2250 | be @code{VOIDmode}. | |
2251 | ||
2252 | If one of the operands is a constant, it should be placed in the | |
77f71523 | 2253 | second operand and the comparison code adjusted as appropriate. |
5fc0eb84 | 2254 | |
2255 | A @code{compare} specifying two @code{VOIDmode} constants is not valid | |
2256 | since there is no way to know in what mode the comparison is to be | |
2257 | performed; the comparison must either be folded during the compilation | |
2258 | or the first operand must be loaded into a register while its mode is | |
2259 | still known. | |
2260 | ||
2261 | @findex neg | |
719ee5e5 | 2262 | @findex ss_neg |
e397ad8e | 2263 | @findex us_neg |
719ee5e5 | 2264 | @cindex negation |
2265 | @cindex negation with signed saturation | |
e397ad8e | 2266 | @cindex negation with unsigned saturation |
5fc0eb84 | 2267 | @item (neg:@var{m} @var{x}) |
719ee5e5 | 2268 | @itemx (ss_neg:@var{m} @var{x}) |
e397ad8e | 2269 | @itemx (us_neg:@var{m} @var{x}) |
719ee5e5 | 2270 | These two expressions represent the negation (subtraction from zero) of |
2271 | the value represented by @var{x}, carried out in mode @var{m}. They | |
554f2707 | 2272 | differ in the behavior on overflow of integer modes. In the case of |
719ee5e5 | 2273 | @code{neg}, the negation of the operand may be a number not representable |
2274 | in mode @var{m}, in which case it is truncated to @var{m}. @code{ss_neg} | |
e397ad8e | 2275 | and @code{us_neg} ensure that an out-of-bounds result saturates to the |
2276 | maximum or minimum signed or unsigned value. | |
5fc0eb84 | 2277 | |
2278 | @findex mult | |
e397ad8e | 2279 | @findex ss_mult |
2280 | @findex us_mult | |
5fc0eb84 | 2281 | @cindex multiplication |
2282 | @cindex product | |
e397ad8e | 2283 | @cindex multiplication with signed saturation |
2284 | @cindex multiplication with unsigned saturation | |
5fc0eb84 | 2285 | @item (mult:@var{m} @var{x} @var{y}) |
e397ad8e | 2286 | @itemx (ss_mult:@var{m} @var{x} @var{y}) |
2287 | @itemx (us_mult:@var{m} @var{x} @var{y}) | |
5fc0eb84 | 2288 | Represents the signed product of the values represented by @var{x} and |
2289 | @var{y} carried out in machine mode @var{m}. | |
e397ad8e | 2290 | @code{ss_mult} and @code{us_mult} ensure that an out-of-bounds result |
2291 | saturates to the maximum or minimum signed or unsigned value. | |
5fc0eb84 | 2292 | |
2293 | Some machines support a multiplication that generates a product wider | |
2294 | than the operands. Write the pattern for this as | |
2295 | ||
a0ecd6b1 | 2296 | @smallexample |
5fc0eb84 | 2297 | (mult:@var{m} (sign_extend:@var{m} @var{x}) (sign_extend:@var{m} @var{y})) |
a0ecd6b1 | 2298 | @end smallexample |
5fc0eb84 | 2299 | |
2300 | where @var{m} is wider than the modes of @var{x} and @var{y}, which need | |
2301 | not be the same. | |
2302 | ||
0fff59be | 2303 | For unsigned widening multiplication, use the same idiom, but with |
2304 | @code{zero_extend} instead of @code{sign_extend}. | |
5fc0eb84 | 2305 | |
7e0713b1 | 2306 | @findex fma |
2307 | @item (fma:@var{m} @var{x} @var{y} @var{z}) | |
2308 | Represents the @code{fma}, @code{fmaf}, and @code{fmal} builtin | |
704f0707 | 2309 | functions, which compute @samp{@var{x} * @var{y} + @var{z}} |
2310 | without doing an intermediate rounding step. | |
7e0713b1 | 2311 | |
5fc0eb84 | 2312 | @findex div |
e397ad8e | 2313 | @findex ss_div |
5fc0eb84 | 2314 | @cindex division |
2315 | @cindex signed division | |
e397ad8e | 2316 | @cindex signed division with signed saturation |
5fc0eb84 | 2317 | @cindex quotient |
2318 | @item (div:@var{m} @var{x} @var{y}) | |
e397ad8e | 2319 | @itemx (ss_div:@var{m} @var{x} @var{y}) |
5fc0eb84 | 2320 | Represents the quotient in signed division of @var{x} by @var{y}, |
2321 | carried out in machine mode @var{m}. If @var{m} is a floating point | |
2322 | mode, it represents the exact quotient; otherwise, the integerized | |
2323 | quotient. | |
e397ad8e | 2324 | @code{ss_div} ensures that an out-of-bounds result saturates to the maximum |
2325 | or minimum signed value. | |
5fc0eb84 | 2326 | |
2327 | Some machines have division instructions in which the operands and | |
77f71523 | 2328 | quotient widths are not all the same; you should represent |
5fc0eb84 | 2329 | such instructions using @code{truncate} and @code{sign_extend} as in, |
2330 | ||
a0ecd6b1 | 2331 | @smallexample |
5fc0eb84 | 2332 | (truncate:@var{m1} (div:@var{m2} @var{x} (sign_extend:@var{m2} @var{y}))) |
a0ecd6b1 | 2333 | @end smallexample |
5fc0eb84 | 2334 | |
2335 | @findex udiv | |
2336 | @cindex unsigned division | |
e397ad8e | 2337 | @cindex unsigned division with unsigned saturation |
5fc0eb84 | 2338 | @cindex division |
2339 | @item (udiv:@var{m} @var{x} @var{y}) | |
e397ad8e | 2340 | @itemx (us_div:@var{m} @var{x} @var{y}) |
5fc0eb84 | 2341 | Like @code{div} but represents unsigned division. |
e397ad8e | 2342 | @code{us_div} ensures that an out-of-bounds result saturates to the maximum |
2343 | or minimum unsigned value. | |
5fc0eb84 | 2344 | |
2345 | @findex mod | |
2346 | @findex umod | |
2347 | @cindex remainder | |
2348 | @cindex division | |
2349 | @item (mod:@var{m} @var{x} @var{y}) | |
2350 | @itemx (umod:@var{m} @var{x} @var{y}) | |
2351 | Like @code{div} and @code{udiv} but represent the remainder instead of | |
2352 | the quotient. | |
2353 | ||
2354 | @findex smin | |
2355 | @findex smax | |
2356 | @cindex signed minimum | |
2357 | @cindex signed maximum | |
2358 | @item (smin:@var{m} @var{x} @var{y}) | |
2359 | @itemx (smax:@var{m} @var{x} @var{y}) | |
2360 | Represents the smaller (for @code{smin}) or larger (for @code{smax}) of | |
10c2e6f6 | 2361 | @var{x} and @var{y}, interpreted as signed values in mode @var{m}. |
2362 | When used with floating point, if both operands are zeros, or if either | |
2363 | operand is @code{NaN}, then it is unspecified which of the two operands | |
2364 | is returned as the result. | |
5fc0eb84 | 2365 | |
2366 | @findex umin | |
2367 | @findex umax | |
2368 | @cindex unsigned minimum and maximum | |
2369 | @item (umin:@var{m} @var{x} @var{y}) | |
2370 | @itemx (umax:@var{m} @var{x} @var{y}) | |
2371 | Like @code{smin} and @code{smax}, but the values are interpreted as unsigned | |
2372 | integers. | |
2373 | ||
2374 | @findex not | |
2375 | @cindex complement, bitwise | |
2376 | @cindex bitwise complement | |
2377 | @item (not:@var{m} @var{x}) | |
2378 | Represents the bitwise complement of the value represented by @var{x}, | |
2379 | carried out in mode @var{m}, which must be a fixed-point machine mode. | |
2380 | ||
2381 | @findex and | |
2382 | @cindex logical-and, bitwise | |
2383 | @cindex bitwise logical-and | |
2384 | @item (and:@var{m} @var{x} @var{y}) | |
2385 | Represents the bitwise logical-and of the values represented by | |
2386 | @var{x} and @var{y}, carried out in machine mode @var{m}, which must be | |
2387 | a fixed-point machine mode. | |
2388 | ||
2389 | @findex ior | |
2390 | @cindex inclusive-or, bitwise | |
2391 | @cindex bitwise inclusive-or | |
2392 | @item (ior:@var{m} @var{x} @var{y}) | |
2393 | Represents the bitwise inclusive-or of the values represented by @var{x} | |
2394 | and @var{y}, carried out in machine mode @var{m}, which must be a | |
2395 | fixed-point mode. | |
2396 | ||
2397 | @findex xor | |
2398 | @cindex exclusive-or, bitwise | |
2399 | @cindex bitwise exclusive-or | |
2400 | @item (xor:@var{m} @var{x} @var{y}) | |
2401 | Represents the bitwise exclusive-or of the values represented by @var{x} | |
2402 | and @var{y}, carried out in machine mode @var{m}, which must be a | |
2403 | fixed-point mode. | |
2404 | ||
2405 | @findex ashift | |
719ee5e5 | 2406 | @findex ss_ashift |
e397ad8e | 2407 | @findex us_ashift |
5fc0eb84 | 2408 | @cindex left shift |
2409 | @cindex shift | |
2410 | @cindex arithmetic shift | |
719ee5e5 | 2411 | @cindex arithmetic shift with signed saturation |
e397ad8e | 2412 | @cindex arithmetic shift with unsigned saturation |
5fc0eb84 | 2413 | @item (ashift:@var{m} @var{x} @var{c}) |
719ee5e5 | 2414 | @itemx (ss_ashift:@var{m} @var{x} @var{c}) |
e397ad8e | 2415 | @itemx (us_ashift:@var{m} @var{x} @var{c}) |
2416 | These three expressions represent the result of arithmetically shifting @var{x} | |
719ee5e5 | 2417 | left by @var{c} places. They differ in their behavior on overflow of integer |
554f2707 | 2418 | modes. An @code{ashift} operation is a plain shift with no special behavior |
e397ad8e | 2419 | in case of a change in the sign bit; @code{ss_ashift} and @code{us_ashift} |
2420 | saturates to the minimum or maximum representable value if any of the bits | |
2421 | shifted out differs from the final sign bit. | |
719ee5e5 | 2422 | |
2423 | @var{x} have mode @var{m}, a fixed-point machine mode. @var{c} | |
5fc0eb84 | 2424 | be a fixed-point mode or be a constant with mode @code{VOIDmode}; which |
2425 | mode is determined by the mode called for in the machine description | |
6c842310 | 2426 | entry for the left-shift instruction. For example, on the VAX, the mode |
5fc0eb84 | 2427 | of @var{c} is @code{QImode} regardless of @var{m}. |
2428 | ||
2429 | @findex lshiftrt | |
2430 | @cindex right shift | |
2431 | @findex ashiftrt | |
2432 | @item (lshiftrt:@var{m} @var{x} @var{c}) | |
2433 | @itemx (ashiftrt:@var{m} @var{x} @var{c}) | |
2434 | Like @code{ashift} but for right shift. Unlike the case for left shift, | |
2435 | these two operations are distinct. | |
2436 | ||
2437 | @findex rotate | |
77f71523 | 2438 | @cindex rotate |
5fc0eb84 | 2439 | @cindex left rotate |
2440 | @findex rotatert | |
2441 | @cindex right rotate | |
2442 | @item (rotate:@var{m} @var{x} @var{c}) | |
2443 | @itemx (rotatert:@var{m} @var{x} @var{c}) | |
2444 | Similar but represent left and right rotate. If @var{c} is a constant, | |
2445 | use @code{rotate}. | |
2446 | ||
2447 | @findex abs | |
bcd06eff | 2448 | @findex ss_abs |
5fc0eb84 | 2449 | @cindex absolute value |
2450 | @item (abs:@var{m} @var{x}) | |
bcd06eff | 2451 | @item (ss_abs:@var{m} @var{x}) |
5fc0eb84 | 2452 | Represents the absolute value of @var{x}, computed in mode @var{m}. |
bcd06eff | 2453 | @code{ss_abs} ensures that an out-of-bounds result saturates to the |
2454 | maximum signed value. | |
2455 | ||
5fc0eb84 | 2456 | |
2457 | @findex sqrt | |
2458 | @cindex square root | |
2459 | @item (sqrt:@var{m} @var{x}) | |
2460 | Represents the square root of @var{x}, computed in mode @var{m}. | |
2461 | Most often @var{m} will be a floating point mode. | |
2462 | ||
2463 | @findex ffs | |
2464 | @item (ffs:@var{m} @var{x}) | |
2465 | Represents one plus the index of the least significant 1-bit in | |
2466 | @var{x}, represented as an integer of mode @var{m}. (The value is | |
011b255e | 2467 | zero if @var{x} is zero.) The mode of @var{x} must be @var{m} |
2468 | or @code{VOIDmode}. | |
6a08d0ab | 2469 | |
d8492bd3 | 2470 | @findex clrsb |
2471 | @item (clrsb:@var{m} @var{x}) | |
2472 | Represents the number of redundant leading sign bits in @var{x}, | |
2473 | represented as an integer of mode @var{m}, starting at the most | |
2474 | significant bit position. This is one less than the number of leading | |
2475 | sign bits (either 0 or 1), with no special cases. The mode of @var{x} | |
011b255e | 2476 | must be @var{m} or @code{VOIDmode}. |
d8492bd3 | 2477 | |
6a08d0ab | 2478 | @findex clz |
2479 | @item (clz:@var{m} @var{x}) | |
2480 | Represents the number of leading 0-bits in @var{x}, represented as an | |
2481 | integer of mode @var{m}, starting at the most significant bit position. | |
8f4be2be | 2482 | If @var{x} is zero, the value is determined by |
4ebee9e4 | 2483 | @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}). Note that this is one of |
6a08d0ab | 2484 | the few expressions that is not invariant under widening. The mode of |
011b255e | 2485 | @var{x} must be @var{m} or @code{VOIDmode}. |
6a08d0ab | 2486 | |
2487 | @findex ctz | |
2488 | @item (ctz:@var{m} @var{x}) | |
2489 | Represents the number of trailing 0-bits in @var{x}, represented as an | |
2490 | integer of mode @var{m}, starting at the least significant bit position. | |
8f4be2be | 2491 | If @var{x} is zero, the value is determined by |
4ebee9e4 | 2492 | @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}). Except for this case, |
6a08d0ab | 2493 | @code{ctz(x)} is equivalent to @code{ffs(@var{x}) - 1}. The mode of |
011b255e | 2494 | @var{x} must be @var{m} or @code{VOIDmode}. |
6a08d0ab | 2495 | |
2496 | @findex popcount | |
2497 | @item (popcount:@var{m} @var{x}) | |
2498 | Represents the number of 1-bits in @var{x}, represented as an integer of | |
011b255e | 2499 | mode @var{m}. The mode of @var{x} must be @var{m} or @code{VOIDmode}. |
6a08d0ab | 2500 | |
2501 | @findex parity | |
2502 | @item (parity:@var{m} @var{x}) | |
2503 | Represents the number of 1-bits modulo 2 in @var{x}, represented as an | |
011b255e | 2504 | integer of mode @var{m}. The mode of @var{x} must be @var{m} or |
2505 | @code{VOIDmode}. | |
42791117 | 2506 | |
2507 | @findex bswap | |
2508 | @item (bswap:@var{m} @var{x}) | |
2509 | Represents the value @var{x} with the order of bytes reversed, carried out | |
2510 | in mode @var{m}, which must be a fixed-point machine mode. | |
011b255e | 2511 | The mode of @var{x} must be @var{m} or @code{VOIDmode}. |
5fc0eb84 | 2512 | @end table |
2513 | ||
b3fb49ae | 2514 | @node Comparisons |
5fc0eb84 | 2515 | @section Comparison Operations |
2516 | @cindex RTL comparison operations | |
2517 | ||
2518 | Comparison operators test a relation on two operands and are considered | |
2519 | to represent a machine-dependent nonzero value described by, but not | |
2520 | necessarily equal to, @code{STORE_FLAG_VALUE} (@pxref{Misc}) | |
da475a45 | 2521 | if the relation holds, or zero if it does not, for comparison operators |
7be10878 | 2522 | whose results have a `MODE_INT' mode, |
da475a45 | 2523 | @code{FLOAT_STORE_FLAG_VALUE} (@pxref{Misc}) if the relation holds, or |
2524 | zero if it does not, for comparison operators that return floating-point | |
7be10878 | 2525 | values, and a vector of either @code{VECTOR_STORE_FLAG_VALUE} (@pxref{Misc}) |
2526 | if the relation holds, or of zeros if it does not, for comparison operators | |
2527 | that return vector results. | |
2528 | The mode of the comparison operation is independent of the mode | |
da475a45 | 2529 | of the data being compared. If the comparison operation is being tested |
2530 | (e.g., the first operand of an @code{if_then_else}), the mode must be | |
2531 | @code{VOIDmode}. | |
5fc0eb84 | 2532 | |
2533 | @cindex condition codes | |
2534 | There are two ways that comparison operations may be used. The | |
2535 | comparison operators may be used to compare the condition codes | |
2536 | @code{(cc0)} against zero, as in @code{(eq (cc0) (const_int 0))}. Such | |
2537 | a construct actually refers to the result of the preceding instruction | |
0261a271 | 2538 | in which the condition codes were set. The instruction setting the |
5fc0eb84 | 2539 | condition code must be adjacent to the instruction using the condition |
2540 | code; only @code{note} insns may separate them. | |
2541 | ||
2542 | Alternatively, a comparison operation may directly compare two data | |
2543 | objects. The mode of the comparison is determined by the operands; they | |
2544 | must both be valid for a common machine mode. A comparison with both | |
2545 | operands constant would be invalid as the machine mode could not be | |
2546 | deduced from it, but such a comparison should never exist in RTL due to | |
2547 | constant folding. | |
2548 | ||
2549 | In the example above, if @code{(cc0)} were last set to | |
2550 | @code{(compare @var{x} @var{y})}, the comparison operation is | |
2551 | identical to @code{(eq @var{x} @var{y})}. Usually only one style | |
2552 | of comparisons is supported on a particular machine, but the combine | |
2553 | pass will try to merge the operations to produce the @code{eq} shown | |
2554 | in case it exists in the context of the particular insn involved. | |
2555 | ||
2556 | Inequality comparisons come in two flavors, signed and unsigned. Thus, | |
2557 | there are distinct expression codes @code{gt} and @code{gtu} for signed and | |
2558 | unsigned greater-than. These can produce different results for the same | |
8ae77b3c | 2559 | pair of integer values: for example, 1 is signed greater-than @minus{}1 but not |
2560 | unsigned greater-than, because @minus{}1 when regarded as unsigned is actually | |
5fc0eb84 | 2561 | @code{0xffffffff} which is greater than 1. |
2562 | ||
2563 | The signed comparisons are also used for floating point values. Floating | |
2564 | point comparisons are distinguished by the machine modes of the operands. | |
2565 | ||
2566 | @table @code | |
2567 | @findex eq | |
2568 | @cindex equal | |
2569 | @item (eq:@var{m} @var{x} @var{y}) | |
3d4a9264 | 2570 | @code{STORE_FLAG_VALUE} if the values represented by @var{x} and @var{y} |
2571 | are equal, otherwise 0. | |
5fc0eb84 | 2572 | |
2573 | @findex ne | |
2574 | @cindex not equal | |
2575 | @item (ne:@var{m} @var{x} @var{y}) | |
3d4a9264 | 2576 | @code{STORE_FLAG_VALUE} if the values represented by @var{x} and @var{y} |
2577 | are not equal, otherwise 0. | |
5fc0eb84 | 2578 | |
2579 | @findex gt | |
2580 | @cindex greater than | |
2581 | @item (gt:@var{m} @var{x} @var{y}) | |
3d4a9264 | 2582 | @code{STORE_FLAG_VALUE} if the @var{x} is greater than @var{y}. If they |
2583 | are fixed-point, the comparison is done in a signed sense. | |
5fc0eb84 | 2584 | |
2585 | @findex gtu | |
2586 | @cindex greater than | |
2587 | @cindex unsigned greater than | |
2588 | @item (gtu:@var{m} @var{x} @var{y}) | |
2589 | Like @code{gt} but does unsigned comparison, on fixed-point numbers only. | |
2590 | ||
2591 | @findex lt | |
2592 | @cindex less than | |
2593 | @findex ltu | |
2594 | @cindex unsigned less than | |
2595 | @item (lt:@var{m} @var{x} @var{y}) | |
2596 | @itemx (ltu:@var{m} @var{x} @var{y}) | |
2597 | Like @code{gt} and @code{gtu} but test for ``less than''. | |
2598 | ||
2599 | @findex ge | |
2600 | @cindex greater than | |
2601 | @findex geu | |
2602 | @cindex unsigned greater than | |
2603 | @item (ge:@var{m} @var{x} @var{y}) | |
2604 | @itemx (geu:@var{m} @var{x} @var{y}) | |
2605 | Like @code{gt} and @code{gtu} but test for ``greater than or equal''. | |
2606 | ||
2607 | @findex le | |
2608 | @cindex less than or equal | |
2609 | @findex leu | |
2610 | @cindex unsigned less than | |
2611 | @item (le:@var{m} @var{x} @var{y}) | |
2612 | @itemx (leu:@var{m} @var{x} @var{y}) | |
2613 | Like @code{gt} and @code{gtu} but test for ``less than or equal''. | |
2614 | ||
2615 | @findex if_then_else | |
2616 | @item (if_then_else @var{cond} @var{then} @var{else}) | |
2617 | This is not a comparison operation but is listed here because it is | |
2618 | always used in conjunction with a comparison operation. To be | |
2619 | precise, @var{cond} is a comparison expression. This expression | |
2620 | represents a choice, according to @var{cond}, between the value | |
2621 | represented by @var{then} and the one represented by @var{else}. | |
2622 | ||
2623 | On most machines, @code{if_then_else} expressions are valid only | |
2624 | to express conditional jumps. | |
2625 | ||
2626 | @findex cond | |
2627 | @item (cond [@var{test1} @var{value1} @var{test2} @var{value2} @dots{}] @var{default}) | |
2628 | Similar to @code{if_then_else}, but more general. Each of @var{test1}, | |
2629 | @var{test2}, @dots{} is performed in turn. The result of this expression is | |
f45856ef | 2630 | the @var{value} corresponding to the first nonzero test, or @var{default} if |
2631 | none of the tests are nonzero expressions. | |
5fc0eb84 | 2632 | |
2633 | This is currently not valid for instruction patterns and is supported only | |
2634 | for insn attributes. @xref{Insn Attributes}. | |
2635 | @end table | |
2636 | ||
8e5fcce7 | 2637 | @node Bit-Fields |
2638 | @section Bit-Fields | |
2639 | @cindex bit-fields | |
5fc0eb84 | 2640 | |
8e5fcce7 | 2641 | Special expression codes exist to represent bit-field instructions. |
5fc0eb84 | 2642 | |
2643 | @table @code | |
2644 | @findex sign_extract | |
2645 | @cindex @code{BITS_BIG_ENDIAN}, effect on @code{sign_extract} | |
2646 | @item (sign_extract:@var{m} @var{loc} @var{size} @var{pos}) | |
8e5fcce7 | 2647 | This represents a reference to a sign-extended bit-field contained or |
2648 | starting in @var{loc} (a memory or register reference). The bit-field | |
5fc0eb84 | 2649 | is @var{size} bits wide and starts at bit @var{pos}. The compilation |
2650 | option @code{BITS_BIG_ENDIAN} says which end of the memory unit | |
2651 | @var{pos} counts from. | |
2652 | ||
2653 | If @var{loc} is in memory, its mode must be a single-byte integer mode. | |
2654 | If @var{loc} is in a register, the mode to use is specified by the | |
2655 | operand of the @code{insv} or @code{extv} pattern | |
2656 | (@pxref{Standard Names}) and is usually a full-word integer mode, | |
2657 | which is the default if none is specified. | |
2658 | ||
2659 | The mode of @var{pos} is machine-specific and is also specified | |
2660 | in the @code{insv} or @code{extv} pattern. | |
2661 | ||
2662 | The mode @var{m} is the same as the mode that would be used for | |
2663 | @var{loc} if it were a register. | |
2664 | ||
476d094d | 2665 | A @code{sign_extract} can not appear as an lvalue, or part thereof, |
2666 | in RTL. | |
2667 | ||
5fc0eb84 | 2668 | @findex zero_extract |
2669 | @item (zero_extract:@var{m} @var{loc} @var{size} @var{pos}) | |
2670 | Like @code{sign_extract} but refers to an unsigned or zero-extended | |
8e5fcce7 | 2671 | bit-field. The same sequence of bits are extracted, but they |
5fc0eb84 | 2672 | are filled to an entire word with zeros instead of by sign-extension. |
476d094d | 2673 | |
2674 | Unlike @code{sign_extract}, this type of expressions can be lvalues | |
2675 | in RTL; they may appear on the left side of an assignment, indicating | |
2676 | insertion of a value into the specified bit-field. | |
5fc0eb84 | 2677 | @end table |
2678 | ||
35a03fc8 | 2679 | @node Vector Operations |
2680 | @section Vector Operations | |
2681 | @cindex vector operations | |
2682 | ||
70c2c81c | 2683 | All normal RTL expressions can be used with vector modes; they are |
35a03fc8 | 2684 | interpreted as operating on each part of the vector independently. |
2685 | Additionally, there are a few new expressions to describe specific vector | |
2686 | operations. | |
2687 | ||
2688 | @table @code | |
2689 | @findex vec_merge | |
2690 | @item (vec_merge:@var{m} @var{vec1} @var{vec2} @var{items}) | |
2691 | This describes a merge operation between two vectors. The result is a vector | |
2692 | of mode @var{m}; its elements are selected from either @var{vec1} or | |
2693 | @var{vec2}. Which elements are selected is described by @var{items}, which | |
2694 | is a bit mask represented by a @code{const_int}; a zero bit indicates the | |
2695 | corresponding element in the result vector is taken from @var{vec2} while | |
2696 | a set bit indicates it is taken from @var{vec1}. | |
2697 | ||
2698 | @findex vec_select | |
2699 | @item (vec_select:@var{m} @var{vec1} @var{selection}) | |
2700 | This describes an operation that selects parts of a vector. @var{vec1} is | |
8fad942e | 2701 | the source vector, and @var{selection} is a @code{parallel} that contains a |
35a03fc8 | 2702 | @code{const_int} for each of the subparts of the result vector, giving the |
15b474a2 | 2703 | number of the source subpart that should be stored into it. |
8fad942e | 2704 | The result mode @var{m} is either the submode for a single element of |
15b474a2 | 2705 | @var{vec1} (if only one subpart is selected), or another vector mode |
8fad942e | 2706 | with that element submode (if multiple subparts are selected). |
35a03fc8 | 2707 | |
2708 | @findex vec_concat | |
16a3d053 | 2709 | @item (vec_concat:@var{m} @var{x1} @var{x2}) |
35a03fc8 | 2710 | Describes a vector concat operation. The result is a concatenation of the |
16a3d053 | 2711 | vectors or scalars @var{x1} and @var{x2}; its length is the sum of the |
2712 | lengths of the two inputs. | |
35a03fc8 | 2713 | |
35a03fc8 | 2714 | @findex vec_duplicate |
16a3d053 | 2715 | @item (vec_duplicate:@var{m} @var{x}) |
2716 | This operation converts a scalar into a vector or a small vector into a | |
2717 | larger one by duplicating the input values. The output vector mode must have | |
2718 | the same submodes as the input vector mode or the scalar modes, and the | |
2719 | number of output parts must be an integer multiple of the number of input | |
2720 | parts. | |
35a03fc8 | 2721 | |
2722 | @end table | |
2723 | ||
b3fb49ae | 2724 | @node Conversions |
5fc0eb84 | 2725 | @section Conversions |
2726 | @cindex conversions | |
2727 | @cindex machine mode conversions | |
2728 | ||
2729 | All conversions between machine modes must be represented by | |
2730 | explicit conversion operations. For example, an expression | |
2731 | which is the sum of a byte and a full word cannot be written as | |
2732 | @code{(plus:SI (reg:QI 34) (reg:SI 80))} because the @code{plus} | |
2733 | operation requires two operands of the same machine mode. | |
2734 | Therefore, the byte-sized operand is enclosed in a conversion | |
2735 | operation, as in | |
2736 | ||
a0ecd6b1 | 2737 | @smallexample |
5fc0eb84 | 2738 | (plus:SI (sign_extend:SI (reg:QI 34)) (reg:SI 80)) |
a0ecd6b1 | 2739 | @end smallexample |
5fc0eb84 | 2740 | |
2741 | The conversion operation is not a mere placeholder, because there | |
2742 | may be more than one way of converting from a given starting mode | |
2743 | to the desired final mode. The conversion operation code says how | |
2744 | to do it. | |
2745 | ||
2746 | For all conversion operations, @var{x} must not be @code{VOIDmode} | |
2747 | because the mode in which to do the conversion would not be known. | |
2748 | The conversion must either be done at compile-time or @var{x} | |
2749 | must be placed into a register. | |
2750 | ||
2751 | @table @code | |
2752 | @findex sign_extend | |
2753 | @item (sign_extend:@var{m} @var{x}) | |
2754 | Represents the result of sign-extending the value @var{x} | |
2755 | to machine mode @var{m}. @var{m} must be a fixed-point mode | |
2756 | and @var{x} a fixed-point value of a mode narrower than @var{m}. | |
2757 | ||
2758 | @findex zero_extend | |
2759 | @item (zero_extend:@var{m} @var{x}) | |
2760 | Represents the result of zero-extending the value @var{x} | |
2761 | to machine mode @var{m}. @var{m} must be a fixed-point mode | |
2762 | and @var{x} a fixed-point value of a mode narrower than @var{m}. | |
2763 | ||
2764 | @findex float_extend | |
2765 | @item (float_extend:@var{m} @var{x}) | |
2766 | Represents the result of extending the value @var{x} | |
2767 | to machine mode @var{m}. @var{m} must be a floating point mode | |
2768 | and @var{x} a floating point value of a mode narrower than @var{m}. | |
2769 | ||
2770 | @findex truncate | |
2771 | @item (truncate:@var{m} @var{x}) | |
2772 | Represents the result of truncating the value @var{x} | |
2773 | to machine mode @var{m}. @var{m} must be a fixed-point mode | |
2774 | and @var{x} a fixed-point value of a mode wider than @var{m}. | |
2775 | ||
35a03fc8 | 2776 | @findex ss_truncate |
2777 | @item (ss_truncate:@var{m} @var{x}) | |
2778 | Represents the result of truncating the value @var{x} | |
2779 | to machine mode @var{m}, using signed saturation in the case of | |
2780 | overflow. Both @var{m} and the mode of @var{x} must be fixed-point | |
2781 | modes. | |
2782 | ||
2783 | @findex us_truncate | |
2784 | @item (us_truncate:@var{m} @var{x}) | |
2785 | Represents the result of truncating the value @var{x} | |
2786 | to machine mode @var{m}, using unsigned saturation in the case of | |
2787 | overflow. Both @var{m} and the mode of @var{x} must be fixed-point | |
2788 | modes. | |
2789 | ||
5fc0eb84 | 2790 | @findex float_truncate |
2791 | @item (float_truncate:@var{m} @var{x}) | |
2792 | Represents the result of truncating the value @var{x} | |
2793 | to machine mode @var{m}. @var{m} must be a floating point mode | |
2794 | and @var{x} a floating point value of a mode wider than @var{m}. | |
2795 | ||
2796 | @findex float | |
2797 | @item (float:@var{m} @var{x}) | |
2798 | Represents the result of converting fixed point value @var{x}, | |
2799 | regarded as signed, to floating point mode @var{m}. | |
2800 | ||
2801 | @findex unsigned_float | |
2802 | @item (unsigned_float:@var{m} @var{x}) | |
2803 | Represents the result of converting fixed point value @var{x}, | |
2804 | regarded as unsigned, to floating point mode @var{m}. | |
2805 | ||
2806 | @findex fix | |
2807 | @item (fix:@var{m} @var{x}) | |
8990536a | 2808 | When @var{m} is a floating-point mode, represents the result of |
2809 | converting floating point value @var{x} (valid for mode @var{m}) to an | |
2810 | integer, still represented in floating point mode @var{m}, by rounding | |
2811 | towards zero. | |
2812 | ||
2813 | When @var{m} is a fixed-point mode, represents the result of | |
5fc0eb84 | 2814 | converting floating point value @var{x} to mode @var{m}, regarded as |
2815 | signed. How rounding is done is not specified, so this operation may | |
2816 | be used validly in compiling C code only for integer-valued operands. | |
2817 | ||
2818 | @findex unsigned_fix | |
2819 | @item (unsigned_fix:@var{m} @var{x}) | |
2820 | Represents the result of converting floating point value @var{x} to | |
2821 | fixed point mode @var{m}, regarded as unsigned. How rounding is done | |
2822 | is not specified. | |
2823 | ||
e397ad8e | 2824 | @findex fract_convert |
2825 | @item (fract_convert:@var{m} @var{x}) | |
2826 | Represents the result of converting fixed-point value @var{x} to | |
2827 | fixed-point mode @var{m}, signed integer value @var{x} to | |
2828 | fixed-point mode @var{m}, floating-point value @var{x} to | |
2829 | fixed-point mode @var{m}, fixed-point value @var{x} to integer mode @var{m} | |
2830 | regarded as signed, or fixed-point value @var{x} to floating-point mode @var{m}. | |
2831 | When overflows or underflows happen, the results are undefined. | |
2832 | ||
2833 | @findex sat_fract | |
2834 | @item (sat_fract:@var{m} @var{x}) | |
2835 | Represents the result of converting fixed-point value @var{x} to | |
2836 | fixed-point mode @var{m}, signed integer value @var{x} to | |
2837 | fixed-point mode @var{m}, or floating-point value @var{x} to | |
2838 | fixed-point mode @var{m}. | |
2839 | When overflows or underflows happen, the results are saturated to the | |
2840 | maximum or the minimum. | |
2841 | ||
2842 | @findex unsigned_fract_convert | |
2843 | @item (unsigned_fract_convert:@var{m} @var{x}) | |
2844 | Represents the result of converting fixed-point value @var{x} to | |
2845 | integer mode @var{m} regarded as unsigned, or unsigned integer value @var{x} to | |
2846 | fixed-point mode @var{m}. | |
2847 | When overflows or underflows happen, the results are undefined. | |
2848 | ||
2849 | @findex unsigned_sat_fract | |
2850 | @item (unsigned_sat_fract:@var{m} @var{x}) | |
2851 | Represents the result of converting unsigned integer value @var{x} to | |
2852 | fixed-point mode @var{m}. | |
2853 | When overflows or underflows happen, the results are saturated to the | |
2854 | maximum or the minimum. | |
5fc0eb84 | 2855 | @end table |
2856 | ||
b3fb49ae | 2857 | @node RTL Declarations |
5fc0eb84 | 2858 | @section Declarations |
2859 | @cindex RTL declarations | |
2860 | @cindex declarations, RTL | |
2861 | ||
2862 | Declaration expression codes do not represent arithmetic operations | |
2863 | but rather state assertions about their operands. | |
2864 | ||
2865 | @table @code | |
2866 | @findex strict_low_part | |
2867 | @cindex @code{subreg}, in @code{strict_low_part} | |
2868 | @item (strict_low_part (subreg:@var{m} (reg:@var{n} @var{r}) 0)) | |
2869 | This expression code is used in only one context: as the destination operand of a | |
2870 | @code{set} expression. In addition, the operand of this expression | |
2871 | must be a non-paradoxical @code{subreg} expression. | |
2872 | ||
2873 | The presence of @code{strict_low_part} says that the part of the | |
2874 | register which is meaningful in mode @var{n}, but is not part of | |
2875 | mode @var{m}, is not to be altered. Normally, an assignment to such | |
2876 | a subreg is allowed to have undefined effects on the rest of the | |
2877 | register when @var{m} is less than a word. | |
2878 | @end table | |
2879 | ||
b3fb49ae | 2880 | @node Side Effects |
5fc0eb84 | 2881 | @section Side Effect Expressions |
2882 | @cindex RTL side effect expressions | |
2883 | ||
2884 | The expression codes described so far represent values, not actions. | |
2885 | But machine instructions never produce values; they are meaningful | |
2886 | only for their side effects on the state of the machine. Special | |
2887 | expression codes are used to represent side effects. | |
2888 | ||
2889 | The body of an instruction is always one of these side effect codes; | |
2890 | the codes described above, which represent values, appear only as | |
2891 | the operands of these. | |
2892 | ||
2893 | @table @code | |
2894 | @findex set | |
2895 | @item (set @var{lval} @var{x}) | |
2896 | Represents the action of storing the value of @var{x} into the place | |
2897 | represented by @var{lval}. @var{lval} must be an expression | |
7c4a3dc7 | 2898 | representing a place that can be stored in: @code{reg} (or @code{subreg}, |
2899 | @code{strict_low_part} or @code{zero_extract}), @code{mem}, @code{pc}, | |
2900 | @code{parallel}, or @code{cc0}. | |
5fc0eb84 | 2901 | |
2902 | If @var{lval} is a @code{reg}, @code{subreg} or @code{mem}, it has a | |
f36eeacd | 2903 | machine mode; then @var{x} must be valid for that mode. |
5fc0eb84 | 2904 | |
2905 | If @var{lval} is a @code{reg} whose machine mode is less than the full | |
2906 | width of the register, then it means that the part of the register | |
2907 | specified by the machine mode is given the specified value and the | |
2908 | rest of the register receives an undefined value. Likewise, if | |
2909 | @var{lval} is a @code{subreg} whose machine mode is narrower than | |
2910 | the mode of the register, the rest of the register can be changed in | |
2911 | an undefined way. | |
2912 | ||
476d094d | 2913 | If @var{lval} is a @code{strict_low_part} of a subreg, then the part |
2914 | of the register specified by the machine mode of the @code{subreg} is | |
2915 | given the value @var{x} and the rest of the register is not changed. | |
2916 | ||
2917 | If @var{lval} is a @code{zero_extract}, then the referenced part of | |
2918 | the bit-field (a memory or register reference) specified by the | |
2919 | @code{zero_extract} is given the value @var{x} and the rest of the | |
2920 | bit-field is not changed. Note that @code{sign_extract} can not | |
2921 | appear in @var{lval}. | |
5fc0eb84 | 2922 | |
2923 | If @var{lval} is @code{(cc0)}, it has no machine mode, and @var{x} may | |
2924 | be either a @code{compare} expression or a value that may have any mode. | |
2925 | The latter case represents a ``test'' instruction. The expression | |
2926 | @code{(set (cc0) (reg:@var{m} @var{n}))} is equivalent to | |
2927 | @code{(set (cc0) (compare (reg:@var{m} @var{n}) (const_int 0)))}. | |
2928 | Use the former expression to save space during the compilation. | |
2929 | ||
4b303227 | 2930 | If @var{lval} is a @code{parallel}, it is used to represent the case of |
2931 | a function returning a structure in multiple registers. Each element | |
8e5fcce7 | 2932 | of the @code{parallel} is an @code{expr_list} whose first operand is a |
4b303227 | 2933 | @code{reg} and whose second operand is a @code{const_int} representing the |
2934 | offset (in bytes) into the structure at which the data in that register | |
2935 | corresponds. The first element may be null to indicate that the structure | |
2936 | is also passed partly in memory. | |
2937 | ||
5fc0eb84 | 2938 | @cindex jump instructions and @code{set} |
2939 | @cindex @code{if_then_else} usage | |
2940 | If @var{lval} is @code{(pc)}, we have a jump instruction, and the | |
2941 | possibilities for @var{x} are very limited. It may be a | |
2942 | @code{label_ref} expression (unconditional jump). It may be an | |
2943 | @code{if_then_else} (conditional jump), in which case either the | |
2944 | second or the third operand must be @code{(pc)} (for the case which | |
2945 | does not jump) and the other of the two must be a @code{label_ref} | |
2946 | (for the case which does jump). @var{x} may also be a @code{mem} or | |
2947 | @code{(plus:SI (pc) @var{y})}, where @var{y} may be a @code{reg} or a | |
2948 | @code{mem}; these unusual patterns are used to represent jumps through | |
f36eeacd | 2949 | branch tables. |
5fc0eb84 | 2950 | |
2951 | If @var{lval} is neither @code{(cc0)} nor @code{(pc)}, the mode of | |
2952 | @var{lval} must not be @code{VOIDmode} and the mode of @var{x} must be | |
2953 | valid for the mode of @var{lval}. | |
2954 | ||
2955 | @findex SET_DEST | |
2956 | @findex SET_SRC | |
77f71523 | 2957 | @var{lval} is customarily accessed with the @code{SET_DEST} macro and |
5fc0eb84 | 2958 | @var{x} with the @code{SET_SRC} macro. |
2959 | ||
2960 | @findex return | |
2961 | @item (return) | |
2962 | As the sole expression in a pattern, represents a return from the | |
2963 | current function, on machines where this can be done with one | |
6c842310 | 2964 | instruction, such as VAXen. On machines where a multi-instruction |
5fc0eb84 | 2965 | ``epilogue'' must be executed in order to return from the function, |
2966 | returning is done by jumping to a label which precedes the epilogue, and | |
2967 | the @code{return} expression code is never used. | |
2968 | ||
2969 | Inside an @code{if_then_else} expression, represents the value to be | |
2970 | placed in @code{pc} to return to the caller. | |
2971 | ||
2972 | Note that an insn pattern of @code{(return)} is logically equivalent to | |
2973 | @code{(set (pc) (return))}, but the latter form is never used. | |
2974 | ||
9cb2517e | 2975 | @findex simple_return |
2976 | @item (simple_return) | |
2977 | Like @code{(return)}, but truly represents only a function return, while | |
2978 | @code{(return)} may represent an insn that also performs other functions | |
2979 | of the function epilogue. Like @code{(return)}, this may also occur in | |
2980 | conditional jumps. | |
2981 | ||
5fc0eb84 | 2982 | @findex call |
2983 | @item (call @var{function} @var{nargs}) | |
2984 | Represents a function call. @var{function} is a @code{mem} expression | |
2985 | whose address is the address of the function to be called. | |
2986 | @var{nargs} is an expression which can be used for two purposes: on | |
2987 | some machines it represents the number of bytes of stack argument; on | |
2988 | others, it represents the number of argument registers. | |
2989 | ||
2990 | Each machine has a standard machine mode which @var{function} must | |
2991 | have. The machine description defines macro @code{FUNCTION_MODE} to | |
2992 | expand into the requisite mode name. The purpose of this mode is to | |
2993 | specify what kind of addressing is allowed, on machines where the | |
2994 | allowed kinds of addressing depend on the machine mode being | |
2995 | addressed. | |
2996 | ||
2997 | @findex clobber | |
2998 | @item (clobber @var{x}) | |
2999 | Represents the storing or possible storing of an unpredictable, | |
3000 | undescribed value into @var{x}, which must be a @code{reg}, | |
4b303227 | 3001 | @code{scratch}, @code{parallel} or @code{mem} expression. |
5fc0eb84 | 3002 | |
3003 | One place this is used is in string instructions that store standard | |
3004 | values into particular hard registers. It may not be worth the | |
3005 | trouble to describe the values that are stored, but it is essential to | |
3006 | inform the compiler that the registers will be altered, lest it | |
3007 | attempt to keep data in them across the string instruction. | |
3008 | ||
7a0ad664 | 3009 | If @var{x} is @code{(mem:BLK (const_int 0))} or |
62ede483 | 3010 | @code{(mem:BLK (scratch))}, it means that all memory |
4b303227 | 3011 | locations must be presumed clobbered. If @var{x} is a @code{parallel}, |
3012 | it has the same meaning as a @code{parallel} in a @code{set} expression. | |
5fc0eb84 | 3013 | |
3014 | Note that the machine description classifies certain hard registers as | |
3015 | ``call-clobbered''. All function call instructions are assumed by | |
3016 | default to clobber these registers, so there is no need to use | |
3017 | @code{clobber} expressions to indicate this fact. Also, each function | |
3018 | call is assumed to have the potential to alter any memory location, | |
3019 | unless the function is declared @code{const}. | |
3020 | ||
3021 | If the last group of expressions in a @code{parallel} are each a | |
3022 | @code{clobber} expression whose arguments are @code{reg} or | |
3023 | @code{match_scratch} (@pxref{RTL Template}) expressions, the combiner | |
3024 | phase can add the appropriate @code{clobber} expressions to an insn it | |
3025 | has constructed when doing so will cause a pattern to be matched. | |
3026 | ||
3027 | This feature can be used, for example, on a machine that whose multiply | |
3028 | and add instructions don't use an MQ register but which has an | |
3029 | add-accumulate instruction that does clobber the MQ register. Similarly, | |
3030 | a combined instruction might require a temporary register while the | |
3031 | constituent instructions might not. | |
3032 | ||
3033 | When a @code{clobber} expression for a register appears inside a | |
3034 | @code{parallel} with other side effects, the register allocator | |
3035 | guarantees that the register is unoccupied both before and after that | |
7173d4d0 | 3036 | insn if it is a hard register clobber. For pseudo-register clobber, |
3037 | the register allocator and the reload pass do not assign the same hard | |
3038 | register to the clobber and the input operands if there is an insn | |
3039 | alternative containing the @samp{&} constraint (@pxref{Modifiers}) for | |
3040 | the clobber and the hard register is in register classes of the | |
3041 | clobber in the alternative. You can clobber either a specific hard | |
6761cdfb | 3042 | register, a pseudo register, or a @code{scratch} expression; in the |
3043 | latter two cases, GCC will allocate a hard register that is available | |
3044 | there for use as a temporary. | |
5fc0eb84 | 3045 | |
3046 | For instructions that require a temporary register, you should use | |
3047 | @code{scratch} instead of a pseudo-register because this will allow the | |
3048 | combiner phase to add the @code{clobber} when required. You do this by | |
3049 | coding (@code{clobber} (@code{match_scratch} @dots{})). If you do | |
3050 | clobber a pseudo register, use one which appears nowhere else---generate | |
0858e3a2 | 3051 | a new one each time. Otherwise, you may confuse CSE@. |
5fc0eb84 | 3052 | |
3053 | There is one other known use for clobbering a pseudo register in a | |
3054 | @code{parallel}: when one of the input operands of the insn is also | |
3055 | clobbered by the insn. In this case, using the same pseudo register in | |
3056 | the clobber and elsewhere in the insn produces the expected results. | |
3057 | ||
3058 | @findex use | |
3059 | @item (use @var{x}) | |
3060 | Represents the use of the value of @var{x}. It indicates that the | |
3061 | value in @var{x} at this point in the program is needed, even though | |
3062 | it may not be apparent why this is so. Therefore, the compiler will | |
3063 | not attempt to delete previous instructions whose only effect is to | |
3064 | store a value in @var{x}. @var{x} must be a @code{reg} expression. | |
3065 | ||
2d192af5 | 3066 | In some situations, it may be tempting to add a @code{use} of a |
3067 | register in a @code{parallel} to describe a situation where the value | |
18566b13 | 3068 | of a special register will modify the behavior of the instruction. |
68576faf | 3069 | A hypothetical example might be a pattern for an addition that can |
2d192af5 | 3070 | either wrap around or use saturating addition depending on the value |
3071 | of a special control register: | |
3072 | ||
b724fad7 | 3073 | @smallexample |
228c5b30 | 3074 | (parallel [(set (reg:SI 2) (unspec:SI [(reg:SI 3) |
0fff59be | 3075 | (reg:SI 4)] 0)) |
2d192af5 | 3076 | (use (reg:SI 1))]) |
b724fad7 | 3077 | @end smallexample |
2d192af5 | 3078 | |
3079 | @noindent | |
3080 | ||
3081 | This will not work, several of the optimizers only look at expressions | |
3082 | locally; it is very likely that if you have multiple insns with | |
3083 | identical inputs to the @code{unspec}, they will be optimized away even | |
3084 | if register 1 changes in between. | |
3085 | ||
3086 | This means that @code{use} can @emph{only} be used to describe | |
3087 | that the register is live. You should think twice before adding | |
3088 | @code{use} statements, more often you will want to use @code{unspec} | |
3089 | instead. The @code{use} RTX is most commonly useful to describe that | |
3090 | a fixed register is implicitly used in an insn. It is also safe to use | |
3091 | in patterns where the compiler knows for other reasons that the result | |
008c057d | 3092 | of the whole pattern is variable, such as @samp{movmem@var{m}} or |
2d192af5 | 3093 | @samp{call} patterns. |
3094 | ||
6aed5e78 | 3095 | During the reload phase, an insn that has a @code{use} as pattern |
3096 | can carry a reg_equal note. These @code{use} insns will be deleted | |
3097 | before the reload phase exits. | |
3098 | ||
5fc0eb84 | 3099 | During the delayed branch scheduling phase, @var{x} may be an insn. |
3100 | This indicates that @var{x} previously was located at this place in the | |
3101 | code and its data dependencies need to be taken into account. These | |
3102 | @code{use} insns will be deleted before the delayed branch scheduling | |
3103 | phase exits. | |
3104 | ||
3105 | @findex parallel | |
3106 | @item (parallel [@var{x0} @var{x1} @dots{}]) | |
3107 | Represents several side effects performed in parallel. The square | |
3108 | brackets stand for a vector; the operand of @code{parallel} is a | |
3109 | vector of expressions. @var{x0}, @var{x1} and so on are individual | |
3110 | side effect expressions---expressions of code @code{set}, @code{call}, | |
9cb2517e | 3111 | @code{return}, @code{simple_return}, @code{clobber} or @code{use}. |
5fc0eb84 | 3112 | |
3113 | ``In parallel'' means that first all the values used in the individual | |
3114 | side-effects are computed, and second all the actual side-effects are | |
3115 | performed. For example, | |
3116 | ||
a0ecd6b1 | 3117 | @smallexample |
5fc0eb84 | 3118 | (parallel [(set (reg:SI 1) (mem:SI (reg:SI 1))) |
3119 | (set (mem:SI (reg:SI 1)) (reg:SI 1))]) | |
a0ecd6b1 | 3120 | @end smallexample |
5fc0eb84 | 3121 | |
3122 | @noindent | |
3123 | says unambiguously that the values of hard register 1 and the memory | |
3124 | location addressed by it are interchanged. In both places where | |
3125 | @code{(reg:SI 1)} appears as a memory address it refers to the value | |
3126 | in register 1 @emph{before} the execution of the insn. | |
3127 | ||
3128 | It follows that it is @emph{incorrect} to use @code{parallel} and | |
3129 | expect the result of one @code{set} to be available for the next one. | |
3130 | For example, people sometimes attempt to represent a jump-if-zero | |
3131 | instruction this way: | |
3132 | ||
a0ecd6b1 | 3133 | @smallexample |
5fc0eb84 | 3134 | (parallel [(set (cc0) (reg:SI 34)) |
3135 | (set (pc) (if_then_else | |
3136 | (eq (cc0) (const_int 0)) | |
3137 | (label_ref @dots{}) | |
3138 | (pc)))]) | |
a0ecd6b1 | 3139 | @end smallexample |
5fc0eb84 | 3140 | |
3141 | @noindent | |
3142 | But this is incorrect, because it says that the jump condition depends | |
3143 | on the condition code value @emph{before} this instruction, not on the | |
3144 | new value that is set by this instruction. | |
3145 | ||
3146 | @cindex peephole optimization, RTL representation | |
3147 | Peephole optimization, which takes place together with final assembly | |
3148 | code output, can produce insns whose patterns consist of a @code{parallel} | |
3149 | whose elements are the operands needed to output the resulting | |
3150 | assembler code---often @code{reg}, @code{mem} or constant expressions. | |
3151 | This would not be well-formed RTL at any other stage in compilation, | |
88eebb49 | 3152 | but it is OK then because no further optimization remains to be done. |
5fc0eb84 | 3153 | However, the definition of the macro @code{NOTICE_UPDATE_CC}, if |
3154 | any, must deal with such insns if you define any peephole optimizations. | |
3155 | ||
997af237 | 3156 | @findex cond_exec |
3157 | @item (cond_exec [@var{cond} @var{expr}]) | |
3158 | Represents a conditionally executed expression. The @var{expr} is | |
f45856ef | 3159 | executed only if the @var{cond} is nonzero. The @var{cond} expression |
997af237 | 3160 | must not have side-effects, but the @var{expr} may very well have |
3161 | side-effects. | |
3162 | ||
5fc0eb84 | 3163 | @findex sequence |
3164 | @item (sequence [@var{insns} @dots{}]) | |
3ff7f7e7 | 3165 | Represents a sequence of insns. If a @code{sequence} appears in the |
3166 | chain of insns, then each of the @var{insns} that appears in the sequence | |
3167 | must be suitable for appearing in the chain of insns, i.e. must satisfy | |
3168 | the @code{INSN_P} predicate. | |
5fc0eb84 | 3169 | |
3170 | After delay-slot scheduling is completed, an insn and all the insns that | |
3171 | reside in its delay slots are grouped together into a @code{sequence}. | |
3172 | The insn requiring the delay slot is the first insn in the vector; | |
3173 | subsequent insns are to be placed in the delay slot. | |
3174 | ||
3175 | @code{INSN_ANNULLED_BRANCH_P} is set on an insn in a delay slot to | |
3176 | indicate that a branch insn should be used that will conditionally annul | |
3177 | the effect of the insns in the delay slots. In such a case, | |
3178 | @code{INSN_FROM_TARGET_P} indicates that the insn is from the target of | |
3179 | the branch and should be executed only if the branch is taken; otherwise | |
3180 | the insn should be executed only if the branch is not taken. | |
3181 | @xref{Delay Slots}. | |
3ff7f7e7 | 3182 | |
3183 | Some back ends also use @code{sequence} objects for purposes other than | |
3184 | delay-slot groups. This is not supported in the common parts of the | |
3185 | compiler, which treat such sequences as delay-slot groups. | |
3186 | ||
3187 | DWARF2 Call Frame Address (CFA) adjustments are sometimes also expressed | |
3188 | using @code{sequence} objects as the value of a @code{RTX_FRAME_RELATED_P} | |
3189 | note. This only happens if the CFA adjustments cannot be easily derived | |
3190 | from the pattern of the instruction to which the note is attached. In | |
3191 | such cases, the value of the note is used instead of best-guesing the | |
3192 | semantics of the instruction. The back end can attach notes containing | |
3193 | a @code{sequence} of @code{set} patterns that express the effect of the | |
3194 | parent instruction. | |
5fc0eb84 | 3195 | @end table |
3196 | ||
3197 | These expression codes appear in place of a side effect, as the body of | |
3198 | an insn, though strictly speaking they do not always describe side | |
3199 | effects as such: | |
3200 | ||
3201 | @table @code | |
3202 | @findex asm_input | |
3203 | @item (asm_input @var{s}) | |
3204 | Represents literal assembler code as described by the string @var{s}. | |
3205 | ||
3206 | @findex unspec | |
3207 | @findex unspec_volatile | |
3208 | @item (unspec [@var{operands} @dots{}] @var{index}) | |
3209 | @itemx (unspec_volatile [@var{operands} @dots{}] @var{index}) | |
3210 | Represents a machine-specific operation on @var{operands}. @var{index} | |
3211 | selects between multiple machine-specific operations. | |
3212 | @code{unspec_volatile} is used for volatile operations and operations | |
3213 | that may trap; @code{unspec} is used for other operations. | |
3214 | ||
3215 | These codes may appear inside a @code{pattern} of an | |
3216 | insn, inside a @code{parallel}, or inside an expression. | |
3217 | ||
3218 | @findex addr_vec | |
3219 | @item (addr_vec:@var{m} [@var{lr0} @var{lr1} @dots{}]) | |
3220 | Represents a table of jump addresses. The vector elements @var{lr0}, | |
3221 | etc., are @code{label_ref} expressions. The mode @var{m} specifies | |
3222 | how much space is given to each address; normally @var{m} would be | |
3223 | @code{Pmode}. | |
3224 | ||
3225 | @findex addr_diff_vec | |
9eaab178 | 3226 | @item (addr_diff_vec:@var{m} @var{base} [@var{lr0} @var{lr1} @dots{}] @var{min} @var{max} @var{flags}) |
5fc0eb84 | 3227 | Represents a table of jump addresses expressed as offsets from |
3228 | @var{base}. The vector elements @var{lr0}, etc., are @code{label_ref} | |
3229 | expressions and so is @var{base}. The mode @var{m} specifies how much | |
9eaab178 | 3230 | space is given to each address-difference. @var{min} and @var{max} |
3231 | are set up by branch shortening and hold a label with a minimum and a | |
3232 | maximum address, respectively. @var{flags} indicates the relative | |
ae7d2789 | 3233 | position of @var{base}, @var{min} and @var{max} to the containing insn |
f36eeacd | 3234 | and of @var{min} and @var{max} to @var{base}. See rtl.def for details. |
9f449ed6 | 3235 | |
3236 | @findex prefetch | |
3237 | @item (prefetch:@var{m} @var{addr} @var{rw} @var{locality}) | |
3238 | Represents prefetch of memory at address @var{addr}. | |
3239 | Operand @var{rw} is 1 if the prefetch is for data to be written, 0 otherwise; | |
3240 | targets that do not support write prefetches should treat this as a normal | |
3241 | prefetch. | |
3242 | Operand @var{locality} specifies the amount of temporal locality; 0 if there | |
3243 | is none or 1, 2, or 3 for increasing levels of temporal locality; | |
3244 | targets that do not support locality hints should ignore this. | |
3245 | ||
3246 | This insn is used to minimize cache-miss latency by moving data into a | |
3247 | cache before it is accessed. It should use only non-faulting data prefetch | |
3248 | instructions. | |
5fc0eb84 | 3249 | @end table |
3250 | ||
b3fb49ae | 3251 | @node Incdec |
5fc0eb84 | 3252 | @section Embedded Side-Effects on Addresses |
3253 | @cindex RTL preincrement | |
3254 | @cindex RTL postincrement | |
3255 | @cindex RTL predecrement | |
3256 | @cindex RTL postdecrement | |
3257 | ||
cbd845cd | 3258 | Six special side-effect expression codes appear as memory addresses. |
5fc0eb84 | 3259 | |
3260 | @table @code | |
3261 | @findex pre_dec | |
3262 | @item (pre_dec:@var{m} @var{x}) | |
3263 | Represents the side effect of decrementing @var{x} by a standard | |
3264 | amount and represents also the value that @var{x} has after being | |
3265 | decremented. @var{x} must be a @code{reg} or @code{mem}, but most | |
3266 | machines allow only a @code{reg}. @var{m} must be the machine mode | |
3267 | for pointers on the machine in use. The amount @var{x} is decremented | |
3268 | by is the length in bytes of the machine mode of the containing memory | |
3269 | reference of which this expression serves as the address. Here is an | |
f36eeacd | 3270 | example of its use: |
5fc0eb84 | 3271 | |
a0ecd6b1 | 3272 | @smallexample |
5fc0eb84 | 3273 | (mem:DF (pre_dec:SI (reg:SI 39))) |
a0ecd6b1 | 3274 | @end smallexample |
5fc0eb84 | 3275 | |
3276 | @noindent | |
3277 | This says to decrement pseudo register 39 by the length of a @code{DFmode} | |
3278 | value and use the result to address a @code{DFmode} value. | |
3279 | ||
3280 | @findex pre_inc | |
3281 | @item (pre_inc:@var{m} @var{x}) | |
3282 | Similar, but specifies incrementing @var{x} instead of decrementing it. | |
3283 | ||
3284 | @findex post_dec | |
3285 | @item (post_dec:@var{m} @var{x}) | |
3286 | Represents the same side effect as @code{pre_dec} but a different | |
3287 | value. The value represented here is the value @var{x} has @i{before} | |
3288 | being decremented. | |
3289 | ||
3290 | @findex post_inc | |
3291 | @item (post_inc:@var{m} @var{x}) | |
3292 | Similar, but specifies incrementing @var{x} instead of decrementing it. | |
cbd845cd | 3293 | |
3294 | @findex post_modify | |
3295 | @item (post_modify:@var{m} @var{x} @var{y}) | |
3296 | ||
3297 | Represents the side effect of setting @var{x} to @var{y} and | |
3298 | represents @var{x} before @var{x} is modified. @var{x} must be a | |
3299 | @code{reg} or @code{mem}, but most machines allow only a @code{reg}. | |
3300 | @var{m} must be the machine mode for pointers on the machine in use. | |
cbd845cd | 3301 | |
3302 | The expression @var{y} must be one of three forms: | |
cbd845cd | 3303 | @code{(plus:@var{m} @var{x} @var{z})}, |
3304 | @code{(minus:@var{m} @var{x} @var{z})}, or | |
3305 | @code{(plus:@var{m} @var{x} @var{i})}, | |
cbd845cd | 3306 | where @var{z} is an index register and @var{i} is a constant. |
3307 | ||
f36eeacd | 3308 | Here is an example of its use: |
cbd845cd | 3309 | |
b724fad7 | 3310 | @smallexample |
70c2c81c | 3311 | (mem:SF (post_modify:SI (reg:SI 42) (plus (reg:SI 42) |
3312 | (reg:SI 48)))) | |
b724fad7 | 3313 | @end smallexample |
cbd845cd | 3314 | |
3315 | This says to modify pseudo register 42 by adding the contents of pseudo | |
3316 | register 48 to it, after the use of what ever 42 points to. | |
3317 | ||
158c5d5e | 3318 | @findex pre_modify |
cbd845cd | 3319 | @item (pre_modify:@var{m} @var{x} @var{expr}) |
3320 | Similar except side effects happen before the use. | |
5fc0eb84 | 3321 | @end table |
3322 | ||
3323 | These embedded side effect expressions must be used with care. Instruction | |
3324 | patterns may not use them. Until the @samp{flow} pass of the compiler, | |
3325 | they may occur only to represent pushes onto the stack. The @samp{flow} | |
3326 | pass finds cases where registers are incremented or decremented in one | |
3327 | instruction and used as an address shortly before or after; these cases are | |
3328 | then transformed to use pre- or post-increment or -decrement. | |
3329 | ||
3330 | If a register used as the operand of these expressions is used in | |
3331 | another address in an insn, the original value of the register is used. | |
3332 | Uses of the register outside of an address are not permitted within the | |
3333 | same insn as a use in an embedded side effect expression because such | |
3334 | insns behave differently on different machines and hence must be treated | |
3335 | as ambiguous and disallowed. | |
3336 | ||
3337 | An instruction that can be represented with an embedded side effect | |
3338 | could also be represented using @code{parallel} containing an additional | |
3339 | @code{set} to describe how the address register is altered. This is not | |
3340 | done because machines that allow these operations at all typically | |
3341 | allow them wherever a memory address is called for. Describing them as | |
3342 | additional parallel stores would require doubling the number of entries | |
3343 | in the machine description. | |
3344 | ||
b3fb49ae | 3345 | @node Assembler |
5fc0eb84 | 3346 | @section Assembler Instructions as Expressions |
3347 | @cindex assembler instructions in RTL | |
3348 | ||
3349 | @cindex @code{asm_operands}, usage | |
3350 | The RTX code @code{asm_operands} represents a value produced by a | |
3351 | user-specified assembler instruction. It is used to represent | |
3352 | an @code{asm} statement with arguments. An @code{asm} statement with | |
3353 | a single output operand, like this: | |
3354 | ||
3355 | @smallexample | |
3356 | asm ("foo %1,%2,%0" : "=a" (outputvar) : "g" (x + y), "di" (*z)); | |
3357 | @end smallexample | |
3358 | ||
3359 | @noindent | |
3360 | is represented using a single @code{asm_operands} RTX which represents | |
3361 | the value that is stored in @code{outputvar}: | |
3362 | ||
3363 | @smallexample | |
3364 | (set @var{rtx-for-outputvar} | |
3365 | (asm_operands "foo %1,%2,%0" "a" 0 | |
3366 | [@var{rtx-for-addition-result} @var{rtx-for-*z}] | |
3367 | [(asm_input:@var{m1} "g") | |
3368 | (asm_input:@var{m2} "di")])) | |
3369 | @end smallexample | |
3370 | ||
3371 | @noindent | |
3372 | Here the operands of the @code{asm_operands} RTX are the assembler | |
3373 | template string, the output-operand's constraint, the index-number of the | |
3374 | output operand among the output operands specified, a vector of input | |
3375 | operand RTX's, and a vector of input-operand modes and constraints. The | |
3376 | mode @var{m1} is the mode of the sum @code{x+y}; @var{m2} is that of | |
3377 | @code{*z}. | |
3378 | ||
3379 | When an @code{asm} statement has multiple output values, its insn has | |
3380 | several such @code{set} RTX's inside of a @code{parallel}. Each @code{set} | |
68576faf | 3381 | contains an @code{asm_operands}; all of these share the same assembler |
5fc0eb84 | 3382 | template and vectors, but each contains the constraint for the respective |
3383 | output operand. They are also distinguished by the output-operand index | |
3384 | number, which is 0, 1, @dots{} for successive output operands. | |
3385 | ||
539f863b | 3386 | @node Debug Information |
3387 | @section Variable Location Debug Information in RTL | |
3388 | @cindex Variable Location Debug Information in RTL | |
3389 | ||
3390 | Variable tracking relies on @code{MEM_EXPR} and @code{REG_EXPR} | |
3391 | annotations to determine what user variables memory and register | |
3392 | references refer to. | |
3393 | ||
3394 | Variable tracking at assignments uses these notes only when they refer | |
3395 | to variables that live at fixed locations (e.g., addressable | |
3396 | variables, global non-automatic variables). For variables whose | |
3397 | location may vary, it relies on the following types of notes. | |
3398 | ||
3399 | @table @code | |
3400 | @findex var_location | |
3401 | @item (var_location:@var{mode} @var{var} @var{exp} @var{stat}) | |
3402 | Binds variable @code{var}, a tree, to value @var{exp}, an RTL | |
3403 | expression. It appears only in @code{NOTE_INSN_VAR_LOCATION} and | |
3404 | @code{DEBUG_INSN}s, with slightly different meanings. @var{mode}, if | |
3405 | present, represents the mode of @var{exp}, which is useful if it is a | |
3406 | modeless expression. @var{stat} is only meaningful in notes, | |
3407 | indicating whether the variable is known to be initialized or | |
3408 | uninitialized. | |
3409 | ||
3410 | @findex debug_expr | |
3411 | @item (debug_expr:@var{mode} @var{decl}) | |
3412 | Stands for the value bound to the @code{DEBUG_EXPR_DECL} @var{decl}, | |
3413 | that points back to it, within value expressions in | |
3414 | @code{VAR_LOCATION} nodes. | |
3415 | ||
3416 | @end table | |
3417 | ||
b3fb49ae | 3418 | @node Insns |
5fc0eb84 | 3419 | @section Insns |
3420 | @cindex insns | |
3421 | ||
3422 | The RTL representation of the code for a function is a doubly-linked | |
3423 | chain of objects called @dfn{insns}. Insns are expressions with | |
3424 | special codes that are used for no other purpose. Some insns are | |
3425 | actual instructions; others represent dispatch tables for @code{switch} | |
3426 | statements; others represent labels to jump to or various sorts of | |
3427 | declarative information. | |
3428 | ||
3429 | In addition to its own specific data, each insn must have a unique | |
3430 | id-number that distinguishes it from all other insns in the current | |
3431 | function (after delayed branch scheduling, copies of an insn with the | |
3432 | same id-number may be present in multiple places in a function, but | |
3433 | these copies will always be identical and will only appear inside a | |
3434 | @code{sequence}), and chain pointers to the preceding and following | |
3435 | insns. These three fields occupy the same position in every insn, | |
3436 | independent of the expression code of the insn. They could be accessed | |
3437 | with @code{XEXP} and @code{XINT}, but instead three special macros are | |
3438 | always used: | |
3439 | ||
3440 | @table @code | |
3441 | @findex INSN_UID | |
3442 | @item INSN_UID (@var{i}) | |
3443 | Accesses the unique id of insn @var{i}. | |
3444 | ||
3445 | @findex PREV_INSN | |
3446 | @item PREV_INSN (@var{i}) | |
3447 | Accesses the chain pointer to the insn preceding @var{i}. | |
3448 | If @var{i} is the first insn, this is a null pointer. | |
3449 | ||
3450 | @findex NEXT_INSN | |
3451 | @item NEXT_INSN (@var{i}) | |
3452 | Accesses the chain pointer to the insn following @var{i}. | |
3453 | If @var{i} is the last insn, this is a null pointer. | |
3454 | @end table | |
3455 | ||
3456 | @findex get_insns | |
3457 | @findex get_last_insn | |
3458 | The first insn in the chain is obtained by calling @code{get_insns}; the | |
3459 | last insn is the result of calling @code{get_last_insn}. Within the | |
3460 | chain delimited by these insns, the @code{NEXT_INSN} and | |
3461 | @code{PREV_INSN} pointers must always correspond: if @var{insn} is not | |
3462 | the first insn, | |
3463 | ||
a0ecd6b1 | 3464 | @smallexample |
5fc0eb84 | 3465 | NEXT_INSN (PREV_INSN (@var{insn})) == @var{insn} |
a0ecd6b1 | 3466 | @end smallexample |
5fc0eb84 | 3467 | |
3468 | @noindent | |
3469 | is always true and if @var{insn} is not the last insn, | |
3470 | ||
a0ecd6b1 | 3471 | @smallexample |
5fc0eb84 | 3472 | PREV_INSN (NEXT_INSN (@var{insn})) == @var{insn} |
a0ecd6b1 | 3473 | @end smallexample |
5fc0eb84 | 3474 | |
3475 | @noindent | |
3476 | is always true. | |
3477 | ||
3478 | After delay slot scheduling, some of the insns in the chain might be | |
3479 | @code{sequence} expressions, which contain a vector of insns. The value | |
3480 | of @code{NEXT_INSN} in all but the last of these insns is the next insn | |
3481 | in the vector; the value of @code{NEXT_INSN} of the last insn in the vector | |
3482 | is the same as the value of @code{NEXT_INSN} for the @code{sequence} in | |
3483 | which it is contained. Similar rules apply for @code{PREV_INSN}. | |
3484 | ||
3485 | This means that the above invariants are not necessarily true for insns | |
3486 | inside @code{sequence} expressions. Specifically, if @var{insn} is the | |
3487 | first insn in a @code{sequence}, @code{NEXT_INSN (PREV_INSN (@var{insn}))} | |
3488 | is the insn containing the @code{sequence} expression, as is the value | |
f8c5d98c | 3489 | of @code{PREV_INSN (NEXT_INSN (@var{insn}))} if @var{insn} is the last |
5fc0eb84 | 3490 | insn in the @code{sequence} expression. You can use these expressions |
f36eeacd | 3491 | to find the containing @code{sequence} expression. |
5fc0eb84 | 3492 | |
539f863b | 3493 | Every insn has one of the following expression codes: |
5fc0eb84 | 3494 | |
3495 | @table @code | |
3496 | @findex insn | |
3497 | @item insn | |
3498 | The expression code @code{insn} is used for instructions that do not jump | |
3499 | and do not do function calls. @code{sequence} expressions are always | |
3500 | contained in insns with code @code{insn} even if one of those insns | |
3501 | should jump or do function calls. | |
3502 | ||
3503 | Insns with code @code{insn} have four additional fields beyond the three | |
3504 | mandatory ones listed above. These four are described in a table below. | |
3505 | ||
3506 | @findex jump_insn | |
3507 | @item jump_insn | |
3508 | The expression code @code{jump_insn} is used for instructions that may | |
19d2fe05 | 3509 | jump (or, more generally, may contain @code{label_ref} expressions to |
3510 | which @code{pc} can be set in that instruction). If there is an | |
3511 | instruction to return from the current function, it is recorded as a | |
3512 | @code{jump_insn}. | |
5fc0eb84 | 3513 | |
3514 | @findex JUMP_LABEL | |
3515 | @code{jump_insn} insns have the same extra fields as @code{insn} insns, | |
3516 | accessed in the same way and in addition contain a field | |
3517 | @code{JUMP_LABEL} which is defined once jump optimization has completed. | |
3518 | ||
41441b59 | 3519 | For simple conditional and unconditional jumps, this field contains |
3520 | the @code{code_label} to which this insn will (possibly conditionally) | |
5fc0eb84 | 3521 | branch. In a more complex jump, @code{JUMP_LABEL} records one of the |
19d2fe05 | 3522 | labels that the insn refers to; other jump target labels are recorded |
3523 | as @code{REG_LABEL_TARGET} notes. The exception is @code{addr_vec} | |
3524 | and @code{addr_diff_vec}, where @code{JUMP_LABEL} is @code{NULL_RTX} | |
3525 | and the only way to find the labels is to scan the entire body of the | |
3526 | insn. | |
5fc0eb84 | 3527 | |
41441b59 | 3528 | Return insns count as jumps, but since they do not refer to any |
3529 | labels, their @code{JUMP_LABEL} is @code{NULL_RTX}. | |
5fc0eb84 | 3530 | |
3531 | @findex call_insn | |
3532 | @item call_insn | |
3533 | The expression code @code{call_insn} is used for instructions that may do | |
3534 | function calls. It is important to distinguish these instructions because | |
3535 | they imply that certain registers and memory locations may be altered | |
3536 | unpredictably. | |
3537 | ||
3538 | @findex CALL_INSN_FUNCTION_USAGE | |
3539 | @code{call_insn} insns have the same extra fields as @code{insn} insns, | |
3540 | accessed in the same way and in addition contain a field | |
3541 | @code{CALL_INSN_FUNCTION_USAGE}, which contains a list (chain of | |
c8010b80 | 3542 | @code{expr_list} expressions) containing @code{use}, @code{clobber} and |
3543 | sometimes @code{set} expressions that denote hard registers and | |
3544 | @code{mem}s used or clobbered by the called function. | |
d2552d01 | 3545 | |
c8010b80 | 3546 | A @code{mem} generally points to a stack slot in which arguments passed |
d2552d01 | 3547 | to the libcall by reference (@pxref{Register Arguments, |
13f08ee7 | 3548 | TARGET_PASS_BY_REFERENCE}) are stored. If the argument is |
3549 | caller-copied (@pxref{Register Arguments, TARGET_CALLEE_COPIES}), | |
c8010b80 | 3550 | the stack slot will be mentioned in @code{clobber} and @code{use} |
3551 | entries; if it's callee-copied, only a @code{use} will appear, and the | |
3552 | @code{mem} may point to addresses that are not stack slots. | |
3553 | ||
3554 | Registers occurring inside a @code{clobber} in this list augment | |
3555 | registers specified in @code{CALL_USED_REGISTERS} (@pxref{Register | |
3556 | Basics}). | |
3557 | ||
3558 | If the list contains a @code{set} involving two registers, it indicates | |
3559 | that the function returns one of its arguments. Such a @code{set} may | |
3560 | look like a no-op if the same register holds the argument and the return | |
3561 | value. | |
5fc0eb84 | 3562 | |
3563 | @findex code_label | |
3564 | @findex CODE_LABEL_NUMBER | |
3565 | @item code_label | |
3566 | A @code{code_label} insn represents a label that a jump insn can jump | |
3567 | to. It contains two special fields of data in addition to the three | |
3568 | standard ones. @code{CODE_LABEL_NUMBER} is used to hold the @dfn{label | |
3569 | number}, a number that identifies this label uniquely among all the | |
3570 | labels in the compilation (not just in the current function). | |
3571 | Ultimately, the label is represented in the assembler output as an | |
3572 | assembler label, usually of the form @samp{L@var{n}} where @var{n} is | |
3573 | the label number. | |
3574 | ||
3575 | When a @code{code_label} appears in an RTL expression, it normally | |
3576 | appears within a @code{label_ref} which represents the address of | |
3577 | the label, as a number. | |
3578 | ||
ac2fdb7a | 3579 | Besides as a @code{code_label}, a label can also be represented as a |
3580 | @code{note} of type @code{NOTE_INSN_DELETED_LABEL}. | |
3581 | ||
5fc0eb84 | 3582 | @findex LABEL_NUSES |
3583 | The field @code{LABEL_NUSES} is only defined once the jump optimization | |
a7ae1e59 | 3584 | phase is completed. It contains the number of times this label is |
5fc0eb84 | 3585 | referenced in the current function. |
3586 | ||
a7ae1e59 | 3587 | @findex LABEL_KIND |
3588 | @findex SET_LABEL_KIND | |
3589 | @findex LABEL_ALT_ENTRY_P | |
3590 | @cindex alternate entry points | |
3591 | The field @code{LABEL_KIND} differentiates four different types of | |
3592 | labels: @code{LABEL_NORMAL}, @code{LABEL_STATIC_ENTRY}, | |
3593 | @code{LABEL_GLOBAL_ENTRY}, and @code{LABEL_WEAK_ENTRY}. The only labels | |
3594 | that do not have type @code{LABEL_NORMAL} are @dfn{alternate entry | |
3595 | points} to the current function. These may be static (visible only in | |
3596 | the containing translation unit), global (exposed to all translation | |
a99e98db | 3597 | units), or weak (global, but can be overridden by another symbol with the |
a7ae1e59 | 3598 | same name). |
3599 | ||
3600 | Much of the compiler treats all four kinds of label identically. Some | |
3601 | of it needs to know whether or not a label is an alternate entry point; | |
3602 | for this purpose, the macro @code{LABEL_ALT_ENTRY_P} is provided. It is | |
3603 | equivalent to testing whether @samp{LABEL_KIND (label) == LABEL_NORMAL}. | |
3604 | The only place that cares about the distinction between static, global, | |
3605 | and weak alternate entry points, besides the front-end code that creates | |
3606 | them, is the function @code{output_alternate_entry_point}, in | |
3607 | @file{final.c}. | |
3608 | ||
3609 | To set the kind of a label, use the @code{SET_LABEL_KIND} macro. | |
bfee5366 | 3610 | |
9ddbb404 | 3611 | @findex jump_table_data |
3612 | @item jump_table_data | |
3613 | A @code{jump_table_data} insn is a placeholder for the jump-table data | |
3614 | of a @code{casesi} or @code{tablejump} insn. They are placed after | |
3615 | a @code{tablejump_p} insn. A @code{jump_table_data} insn is not part o | |
3616 | a basic blockm but it is associated with the basic block that ends with | |
3617 | the @code{tablejump_p} insn. The @code{PATTERN} of a @code{jump_table_data} | |
3618 | is always either an @code{addr_vec} or an @code{addr_diff_vec}, and a | |
3619 | @code{jump_table_data} insn is always preceded by a @code{code_label}. | |
3620 | The @code{tablejump_p} insn refers to that @code{code_label} via its | |
3621 | @code{JUMP_LABEL}. | |
3622 | ||
5fc0eb84 | 3623 | @findex barrier |
3624 | @item barrier | |
3625 | Barriers are placed in the instruction stream when control cannot flow | |
3626 | past them. They are placed after unconditional jump instructions to | |
3627 | indicate that the jumps are unconditional and after calls to | |
3628 | @code{volatile} functions, which do not return (e.g., @code{exit}). | |
3629 | They contain no information beyond the three standard fields. | |
3630 | ||
3631 | @findex note | |
3632 | @findex NOTE_LINE_NUMBER | |
3633 | @findex NOTE_SOURCE_FILE | |
3634 | @item note | |
3635 | @code{note} insns are used to represent additional debugging and | |
3636 | declarative information. They contain two nonstandard fields, an | |
3637 | integer which is accessed with the macro @code{NOTE_LINE_NUMBER} and a | |
3638 | string accessed with @code{NOTE_SOURCE_FILE}. | |
3639 | ||
3640 | If @code{NOTE_LINE_NUMBER} is positive, the note represents the | |
3641 | position of a source line and @code{NOTE_SOURCE_FILE} is the source file name | |
3642 | that the line came from. These notes control generation of line | |
3643 | number data in the assembler output. | |
3644 | ||
3645 | Otherwise, @code{NOTE_LINE_NUMBER} is not really a line number but a | |
3646 | code with one of the following values (and @code{NOTE_SOURCE_FILE} | |
3647 | must contain a null pointer): | |
3648 | ||
3649 | @table @code | |
3650 | @findex NOTE_INSN_DELETED | |
3651 | @item NOTE_INSN_DELETED | |
3652 | Such a note is completely ignorable. Some passes of the compiler | |
3653 | delete insns by altering them into notes of this kind. | |
3654 | ||
ac2fdb7a | 3655 | @findex NOTE_INSN_DELETED_LABEL |
3656 | @item NOTE_INSN_DELETED_LABEL | |
3657 | This marks what used to be a @code{code_label}, but was not used for other | |
3658 | purposes than taking its address and was transformed to mark that no | |
3659 | code jumps to it. | |
3660 | ||
5fc0eb84 | 3661 | @findex NOTE_INSN_BLOCK_BEG |
3662 | @findex NOTE_INSN_BLOCK_END | |
3663 | @item NOTE_INSN_BLOCK_BEG | |
3664 | @itemx NOTE_INSN_BLOCK_END | |
3665 | These types of notes indicate the position of the beginning and end | |
3666 | of a level of scoping of variable names. They control the output | |
3667 | of debugging information. | |
3668 | ||
3669 | @findex NOTE_INSN_EH_REGION_BEG | |
3670 | @findex NOTE_INSN_EH_REGION_END | |
3671 | @item NOTE_INSN_EH_REGION_BEG | |
3672 | @itemx NOTE_INSN_EH_REGION_END | |
3673 | These types of notes indicate the position of the beginning and end of a | |
3ff7f7e7 | 3674 | level of scoping for exception handling. @code{NOTE_EH_HANDLER} |
3675 | identifies which region is associated with these notes. | |
5fc0eb84 | 3676 | |
bc3cc6e8 | 3677 | @findex NOTE_INSN_FUNCTION_BEG |
51dd3024 | 3678 | @item NOTE_INSN_FUNCTION_BEG |
bc3cc6e8 | 3679 | Appears at the start of the function body, after the function |
3680 | prologue. | |
3681 | ||
539f863b | 3682 | @findex NOTE_INSN_VAR_LOCATION |
3683 | @findex NOTE_VAR_LOCATION | |
3684 | @item NOTE_INSN_VAR_LOCATION | |
3685 | This note is used to generate variable location debugging information. | |
3686 | It indicates that the user variable in its @code{VAR_LOCATION} operand | |
3687 | is at the location given in the RTL expression, or holds a value that | |
3688 | can be computed by evaluating the RTL expression from that static | |
3689 | point in the program up to the next such note for the same user | |
3690 | variable. | |
3691 | ||
5fc0eb84 | 3692 | @end table |
3693 | ||
3694 | These codes are printed symbolically when they appear in debugging dumps. | |
539f863b | 3695 | |
3696 | @findex debug_insn | |
3697 | @findex INSN_VAR_LOCATION | |
3698 | @item debug_insn | |
3699 | The expression code @code{debug_insn} is used for pseudo-instructions | |
3700 | that hold debugging information for variable tracking at assignments | |
3701 | (see @option{-fvar-tracking-assignments} option). They are the RTL | |
3702 | representation of @code{GIMPLE_DEBUG} statements | |
3703 | (@ref{@code{GIMPLE_DEBUG}}), with a @code{VAR_LOCATION} operand that | |
3704 | binds a user variable tree to an RTL representation of the | |
3705 | @code{value} in the corresponding statement. A @code{DEBUG_EXPR} in | |
3706 | it stands for the value bound to the corresponding | |
3707 | @code{DEBUG_EXPR_DECL}. | |
3708 | ||
3709 | Throughout optimization passes, binding information is kept in | |
3710 | pseudo-instruction form, so that, unlike notes, it gets the same | |
3711 | treatment and adjustments that regular instructions would. It is the | |
3712 | variable tracking pass that turns these pseudo-instructions into var | |
3713 | location notes, analyzing control flow, value equivalences and changes | |
3714 | to registers and memory referenced in value expressions, propagating | |
3715 | the values of debug temporaries and determining expressions that can | |
3716 | be used to compute the value of each user variable at as many points | |
3717 | (ranges, actually) in the program as possible. | |
3718 | ||
3719 | Unlike @code{NOTE_INSN_VAR_LOCATION}, the value expression in an | |
3720 | @code{INSN_VAR_LOCATION} denotes a value at that specific point in the | |
3721 | program, rather than an expression that can be evaluated at any later | |
3722 | point before an overriding @code{VAR_LOCATION} is encountered. E.g., | |
3723 | if a user variable is bound to a @code{REG} and then a subsequent insn | |
3724 | modifies the @code{REG}, the note location would keep mapping the user | |
3725 | variable to the register across the insn, whereas the insn location | |
3726 | would keep the variable bound to the value, so that the variable | |
3727 | tracking pass would emit another location note for the variable at the | |
3728 | point in which the register is modified. | |
3729 | ||
5fc0eb84 | 3730 | @end table |
3731 | ||
58579bb7 | 3732 | @cindex @code{TImode}, in @code{insn} |
5fc0eb84 | 3733 | @cindex @code{HImode}, in @code{insn} |
3734 | @cindex @code{QImode}, in @code{insn} | |
3735 | The machine mode of an insn is normally @code{VOIDmode}, but some | |
77f71523 | 3736 | phases use the mode for various purposes. |
58579bb7 | 3737 | |
3738 | The common subexpression elimination pass sets the mode of an insn to | |
3739 | @code{QImode} when it is the first insn in a block that has already | |
3740 | been processed. | |
3741 | ||
3742 | The second Haifa scheduling pass, for targets that can multiple issue, | |
3743 | sets the mode of an insn to @code{TImode} when it is believed that the | |
77f71523 | 3744 | instruction begins an issue group. That is, when the instruction |
58579bb7 | 3745 | cannot issue simultaneously with the previous. This may be relied on |
8e5fcce7 | 3746 | by later passes, in particular machine-dependent reorg. |
5fc0eb84 | 3747 | |
3748 | Here is a table of the extra fields of @code{insn}, @code{jump_insn} | |
3749 | and @code{call_insn} insns: | |
3750 | ||
3751 | @table @code | |
3752 | @findex PATTERN | |
3753 | @item PATTERN (@var{i}) | |
9cb2517e | 3754 | An expression for the side effect performed by this insn. This must |
3755 | be one of the following codes: @code{set}, @code{call}, @code{use}, | |
3756 | @code{clobber}, @code{return}, @code{simple_return}, @code{asm_input}, | |
3757 | @code{asm_output}, @code{addr_vec}, @code{addr_diff_vec}, | |
3758 | @code{trap_if}, @code{unspec}, @code{unspec_volatile}, | |
3759 | @code{parallel}, @code{cond_exec}, or @code{sequence}. If it is a | |
3760 | @code{parallel}, each element of the @code{parallel} must be one these | |
3761 | codes, except that @code{parallel} expressions cannot be nested and | |
3762 | @code{addr_vec} and @code{addr_diff_vec} are not permitted inside a | |
3763 | @code{parallel} expression. | |
5fc0eb84 | 3764 | |
3765 | @findex INSN_CODE | |
3766 | @item INSN_CODE (@var{i}) | |
3767 | An integer that says which pattern in the machine description matches | |
8ae77b3c | 3768 | this insn, or @minus{}1 if the matching has not yet been attempted. |
5fc0eb84 | 3769 | |
8ae77b3c | 3770 | Such matching is never attempted and this field remains @minus{}1 on an insn |
5fc0eb84 | 3771 | whose pattern consists of a single @code{use}, @code{clobber}, |
3772 | @code{asm_input}, @code{addr_vec} or @code{addr_diff_vec} expression. | |
3773 | ||
3774 | @findex asm_noperands | |
3775 | Matching is also never attempted on insns that result from an @code{asm} | |
3776 | statement. These contain at least one @code{asm_operands} expression. | |
3777 | The function @code{asm_noperands} returns a non-negative value for | |
3778 | such insns. | |
3779 | ||
3780 | In the debugging output, this field is printed as a number followed by | |
3781 | a symbolic representation that locates the pattern in the @file{md} | |
3782 | file as some small positive or negative offset from a named pattern. | |
3783 | ||
3784 | @findex LOG_LINKS | |
3785 | @item LOG_LINKS (@var{i}) | |
3786 | A list (chain of @code{insn_list} expressions) giving information about | |
3787 | dependencies between instructions within a basic block. Neither a jump | |
3072d30e | 3788 | nor a label may come between the related insns. These are only used by |
3789 | the schedulers and by combine. This is a deprecated data structure. | |
15b474a2 | 3790 | Def-use and use-def chains are now preferred. |
5fc0eb84 | 3791 | |
3792 | @findex REG_NOTES | |
3793 | @item REG_NOTES (@var{i}) | |
9eb946de | 3794 | A list (chain of @code{expr_list}, @code{insn_list} and @code{int_list} |
3795 | expressions) giving miscellaneous information about the insn. It is often | |
5fc0eb84 | 3796 | information pertaining to the registers used in this insn. |
3797 | @end table | |
3798 | ||
3799 | The @code{LOG_LINKS} field of an insn is a chain of @code{insn_list} | |
3800 | expressions. Each of these has two operands: the first is an insn, | |
3801 | and the second is another @code{insn_list} expression (the next one in | |
3802 | the chain). The last @code{insn_list} in the chain has a null pointer | |
3803 | as second operand. The significant thing about the chain is which | |
3804 | insns appear in it (as first operands of @code{insn_list} | |
3805 | expressions). Their order is not significant. | |
3806 | ||
3807 | This list is originally set up by the flow analysis pass; it is a null | |
3808 | pointer until then. Flow only adds links for those data dependencies | |
3809 | which can be used for instruction combination. For each insn, the flow | |
3810 | analysis pass adds a link to insns which store into registers values | |
9997bd27 | 3811 | that are used for the first time in this insn. |
5fc0eb84 | 3812 | |
3813 | The @code{REG_NOTES} field of an insn is a chain similar to the | |
9eb946de | 3814 | @code{LOG_LINKS} field but it includes @code{expr_list} and @code{int_list} |
3815 | expressions in addition to @code{insn_list} expressions. There are several | |
3816 | kinds of register notes, which are distinguished by the machine mode, which | |
3817 | in a register note is really understood as being an @code{enum reg_note}. | |
5fc0eb84 | 3818 | The first operand @var{op} of the note is data whose meaning depends on |
3819 | the kind of note. | |
3820 | ||
3821 | @findex REG_NOTE_KIND | |
3822 | @findex PUT_REG_NOTE_KIND | |
3823 | The macro @code{REG_NOTE_KIND (@var{x})} returns the kind of | |
3824 | register note. Its counterpart, the macro @code{PUT_REG_NOTE_KIND | |
3825 | (@var{x}, @var{newkind})} sets the register note type of @var{x} to be | |
3826 | @var{newkind}. | |
3827 | ||
3828 | Register notes are of three classes: They may say something about an | |
3829 | input to an insn, they may say something about an output of an insn, or | |
3830 | they may create a linkage between two insns. There are also a set | |
3831 | of values that are only used in @code{LOG_LINKS}. | |
3832 | ||
3833 | These register notes annotate inputs to an insn: | |
3834 | ||
3835 | @table @code | |
77f71523 | 3836 | @findex REG_DEAD |
5fc0eb84 | 3837 | @item REG_DEAD |
3838 | The value in @var{op} dies in this insn; that is to say, altering the | |
3839 | value immediately after this insn would not affect the future behavior | |
77f71523 | 3840 | of the program. |
5fc0eb84 | 3841 | |
c4c4e18f | 3842 | It does not follow that the register @var{op} has no useful value after |
3843 | this insn since @var{op} is not necessarily modified by this insn. | |
3844 | Rather, no subsequent instruction uses the contents of @var{op}. | |
3845 | ||
3846 | @findex REG_UNUSED | |
3847 | @item REG_UNUSED | |
3848 | The register @var{op} being set by this insn will not be used in a | |
3849 | subsequent insn. This differs from a @code{REG_DEAD} note, which | |
3850 | indicates that the value in an input will not be used subsequently. | |
3851 | These two notes are independent; both may be present for the same | |
3852 | register. | |
5fc0eb84 | 3853 | |
3854 | @findex REG_INC | |
3855 | @item REG_INC | |
3856 | The register @var{op} is incremented (or decremented; at this level | |
3857 | there is no distinction) by an embedded side effect inside this insn. | |
3858 | This means it appears in a @code{post_inc}, @code{pre_inc}, | |
3859 | @code{post_dec} or @code{pre_dec} expression. | |
3860 | ||
3861 | @findex REG_NONNEG | |
3862 | @item REG_NONNEG | |
3863 | The register @var{op} is known to have a nonnegative value when this | |
3864 | insn is reached. This is used so that decrement and branch until zero | |
3865 | instructions, such as the m68k dbra, can be matched. | |
3866 | ||
3867 | The @code{REG_NONNEG} note is added to insns only if the machine | |
3868 | description has a @samp{decrement_and_branch_until_zero} pattern. | |
3869 | ||
19d2fe05 | 3870 | @findex REG_LABEL_OPERAND |
3871 | @item REG_LABEL_OPERAND | |
ac2fdb7a | 3872 | This insn uses @var{op}, a @code{code_label} or a @code{note} of type |
19d2fe05 | 3873 | @code{NOTE_INSN_DELETED_LABEL}, but is not a @code{jump_insn}, or it |
3874 | is a @code{jump_insn} that refers to the operand as an ordinary | |
3875 | operand. The label may still eventually be a jump target, but if so | |
3876 | in an indirect jump in a subsequent insn. The presence of this note | |
3877 | allows jump optimization to be aware that @var{op} is, in fact, being | |
3878 | used, and flow optimization to build an accurate flow graph. | |
3879 | ||
3880 | @findex REG_LABEL_TARGET | |
3881 | @item REG_LABEL_TARGET | |
68576faf | 3882 | This insn is a @code{jump_insn} but not an @code{addr_vec} or |
19d2fe05 | 3883 | @code{addr_diff_vec}. It uses @var{op}, a @code{code_label} as a |
3884 | direct or indirect jump target. Its purpose is similar to that of | |
3885 | @code{REG_LABEL_OPERAND}. This note is only present if the insn has | |
3886 | multiple targets; the last label in the insn (in the highest numbered | |
3887 | insn-field) goes into the @code{JUMP_LABEL} field and does not have a | |
3888 | @code{REG_LABEL_TARGET} note. @xref{Insns, JUMP_LABEL}. | |
4f18499c | 3889 | |
3890 | @findex REG_CROSSING_JUMP | |
3891 | @item REG_CROSSING_JUMP | |
68576faf | 3892 | This insn is a branching instruction (either an unconditional jump or |
4f18499c | 3893 | an indirect jump) which crosses between hot and cold sections, which |
3894 | could potentially be very far apart in the executable. The presence | |
d2258b2f | 3895 | of this note indicates to other optimizations that this branching |
4f18499c | 3896 | instruction should not be ``collapsed'' into a simpler branching |
3897 | construct. It is used when the optimization to partition basic blocks | |
3898 | into hot and cold sections is turned on. | |
b012e613 | 3899 | |
3900 | @findex REG_SETJMP | |
15b474a2 | 3901 | @item REG_SETJMP |
3902 | Appears attached to each @code{CALL_INSN} to @code{setjmp} or a | |
b012e613 | 3903 | related function. |
5fc0eb84 | 3904 | @end table |
3905 | ||
3906 | The following notes describe attributes of outputs of an insn: | |
3907 | ||
3908 | @table @code | |
3909 | @findex REG_EQUIV | |
3910 | @findex REG_EQUAL | |
3911 | @item REG_EQUIV | |
3912 | @itemx REG_EQUAL | |
3913 | This note is only valid on an insn that sets only one register and | |
3914 | indicates that that register will be equal to @var{op} at run time; the | |
3915 | scope of this equivalence differs between the two types of notes. The | |
3916 | value which the insn explicitly copies into the register may look | |
3917 | different from @var{op}, but they will be equal at run time. If the | |
3918 | output of the single @code{set} is a @code{strict_low_part} expression, | |
3919 | the note refers to the register that is contained in @code{SUBREG_REG} | |
3920 | of the @code{subreg} expression. | |
77f71523 | 3921 | |
5fc0eb84 | 3922 | For @code{REG_EQUIV}, the register is equivalent to @var{op} throughout |
3923 | the entire function, and could validly be replaced in all its | |
3924 | occurrences by @var{op}. (``Validly'' here refers to the data flow of | |
3925 | the program; simple replacement may make some insns invalid.) For | |
3926 | example, when a constant is loaded into a register that is never | |
3927 | assigned any other value, this kind of note is used. | |
3928 | ||
3929 | When a parameter is copied into a pseudo-register at entry to a function, | |
3930 | a note of this kind records that the register is equivalent to the stack | |
3931 | slot where the parameter was passed. Although in this case the register | |
3932 | may be set by other insns, it is still valid to replace the register | |
3933 | by the stack slot throughout the function. | |
3934 | ||
3935 | A @code{REG_EQUIV} note is also used on an instruction which copies a | |
3936 | register parameter into a pseudo-register at entry to a function, if | |
3937 | there is a stack slot where that parameter could be stored. Although | |
3938 | other insns may set the pseudo-register, it is valid for the compiler to | |
3939 | replace the pseudo-register by stack slot throughout the function, | |
3940 | provided the compiler ensures that the stack slot is properly | |
3941 | initialized by making the replacement in the initial copy instruction as | |
3942 | well. This is used on machines for which the calling convention | |
3943 | allocates stack space for register parameters. See | |
3944 | @code{REG_PARM_STACK_SPACE} in @ref{Stack Arguments}. | |
3945 | ||
3946 | In the case of @code{REG_EQUAL}, the register that is set by this insn | |
3947 | will be equal to @var{op} at run time at the end of this insn but not | |
3948 | necessarily elsewhere in the function. In this case, @var{op} | |
3949 | is typically an arithmetic expression. For example, when a sequence of | |
3950 | insns such as a library call is used to perform an arithmetic operation, | |
3951 | this kind of note is attached to the insn that produces or copies the | |
3952 | final value. | |
3953 | ||
3954 | These two notes are used in different ways by the compiler passes. | |
3955 | @code{REG_EQUAL} is used by passes prior to register allocation (such as | |
3956 | common subexpression elimination and loop optimization) to tell them how | |
3957 | to think of that value. @code{REG_EQUIV} notes are used by register | |
3958 | allocation to indicate that there is an available substitute expression | |
3959 | (either a constant or a @code{mem} expression for the location of a | |
3960 | parameter on the stack) that may be used in place of a register if | |
3961 | insufficient registers are available. | |
3962 | ||
3963 | Except for stack homes for parameters, which are indicated by a | |
3964 | @code{REG_EQUIV} note and are not useful to the early optimization | |
3965 | passes and pseudo registers that are equivalent to a memory location | |
f8c5d98c | 3966 | throughout their entire life, which is not detected until later in |
5fc0eb84 | 3967 | the compilation, all equivalences are initially indicated by an attached |
3968 | @code{REG_EQUAL} note. In the early stages of register allocation, a | |
3969 | @code{REG_EQUAL} note is changed into a @code{REG_EQUIV} note if | |
3970 | @var{op} is a constant and the insn represents the only set of its | |
3971 | destination register. | |
3972 | ||
3973 | Thus, compiler passes prior to register allocation need only check for | |
3974 | @code{REG_EQUAL} notes and passes subsequent to register allocation | |
3975 | need only check for @code{REG_EQUIV} notes. | |
5fc0eb84 | 3976 | @end table |
3977 | ||
3978 | These notes describe linkages between insns. They occur in pairs: one | |
3979 | insn has one of a pair of notes that points to a second insn, which has | |
3980 | the inverse note pointing back to the first insn. | |
3981 | ||
3982 | @table @code | |
5fc0eb84 | 3983 | @findex REG_CC_SETTER |
3984 | @findex REG_CC_USER | |
3985 | @item REG_CC_SETTER | |
3986 | @itemx REG_CC_USER | |
3987 | On machines that use @code{cc0}, the insns which set and use @code{cc0} | |
3988 | set and use @code{cc0} are adjacent. However, when branch delay slot | |
3989 | filling is done, this may no longer be true. In this case a | |
3990 | @code{REG_CC_USER} note will be placed on the insn setting @code{cc0} to | |
3991 | point to the insn using @code{cc0} and a @code{REG_CC_SETTER} note will | |
3992 | be placed on the insn using @code{cc0} to point to the insn setting | |
f36eeacd | 3993 | @code{cc0}. |
5fc0eb84 | 3994 | @end table |
3995 | ||
3996 | These values are only used in the @code{LOG_LINKS} field, and indicate | |
3997 | the type of dependency that each link represents. Links which indicate | |
3998 | a data dependence (a read after write dependence) do not use any code, | |
3999 | they simply have mode @code{VOIDmode}, and are printed without any | |
4000 | descriptive text. | |
4001 | ||
4002 | @table @code | |
9997bd27 | 4003 | @findex REG_DEP_TRUE |
4004 | @item REG_DEP_TRUE | |
4005 | This indicates a true dependence (a read after write dependence). | |
5fc0eb84 | 4006 | |
4007 | @findex REG_DEP_OUTPUT | |
4008 | @item REG_DEP_OUTPUT | |
4009 | This indicates an output dependence (a write after write dependence). | |
9997bd27 | 4010 | |
4011 | @findex REG_DEP_ANTI | |
4012 | @item REG_DEP_ANTI | |
4013 | This indicates an anti dependence (a write after read dependence). | |
4014 | ||
5fc0eb84 | 4015 | @end table |
4016 | ||
4017 | These notes describe information gathered from gcov profile data. They | |
9eb946de | 4018 | are stored in the @code{REG_NOTES} field of an insn. |
5fc0eb84 | 4019 | |
4020 | @table @code | |
5fc0eb84 | 4021 | @findex REG_BR_PROB |
4022 | @item REG_BR_PROB | |
4023 | This is used to specify the ratio of branches to non-branches of a | |
9eb946de | 4024 | branch insn according to the profile data. The note is represented |
4025 | as an @code{int_list} expression whose integer value is between 0 and | |
4026 | REG_BR_PROB_BASE. Larger values indicate a higher probability that | |
4027 | the branch will be taken. | |
0e8ea3ed | 4028 | |
4029 | @findex REG_BR_PRED | |
4030 | @item REG_BR_PRED | |
4031 | These notes are found in JUMP insns after delayed branch scheduling | |
ae7d2789 | 4032 | has taken place. They indicate both the direction and the likelihood |
0858e3a2 | 4033 | of the JUMP@. The format is a bitmask of ATTR_FLAG_* values. |
86b18255 | 4034 | |
4035 | @findex REG_FRAME_RELATED_EXPR | |
4036 | @item REG_FRAME_RELATED_EXPR | |
4037 | This is used on an RTX_FRAME_RELATED_P insn wherein the attached expression | |
4038 | is used in place of the actual insn pattern. This is done in cases where | |
4039 | the pattern is either complex or misleading. | |
5fc0eb84 | 4040 | @end table |
4041 | ||
4042 | For convenience, the machine mode in an @code{insn_list} or | |
4043 | @code{expr_list} is printed using these symbolic codes in debugging dumps. | |
4044 | ||
4045 | @findex insn_list | |
4046 | @findex expr_list | |
4047 | The only difference between the expression codes @code{insn_list} and | |
4048 | @code{expr_list} is that the first operand of an @code{insn_list} is | |
4049 | assumed to be an insn and is printed in debugging dumps as the insn's | |
4050 | unique id; the first operand of an @code{expr_list} is printed in the | |
4051 | ordinary way as an expression. | |
4052 | ||
b3fb49ae | 4053 | @node Calls |
5fc0eb84 | 4054 | @section RTL Representation of Function-Call Insns |
4055 | @cindex calling functions in RTL | |
4056 | @cindex RTL function-call insns | |
4057 | @cindex function-call insns | |
4058 | ||
4059 | Insns that call subroutines have the RTL expression code @code{call_insn}. | |
4060 | These insns must satisfy special rules, and their bodies must use a special | |
4061 | RTL expression code, @code{call}. | |
4062 | ||
4063 | @cindex @code{call} usage | |
4064 | A @code{call} expression has two operands, as follows: | |
4065 | ||
a0ecd6b1 | 4066 | @smallexample |
5fc0eb84 | 4067 | (call (mem:@var{fm} @var{addr}) @var{nbytes}) |
a0ecd6b1 | 4068 | @end smallexample |
5fc0eb84 | 4069 | |
4070 | @noindent | |
4071 | Here @var{nbytes} is an operand that represents the number of bytes of | |
4072 | argument data being passed to the subroutine, @var{fm} is a machine mode | |
4073 | (which must equal as the definition of the @code{FUNCTION_MODE} macro in | |
4074 | the machine description) and @var{addr} represents the address of the | |
4075 | subroutine. | |
4076 | ||
4077 | For a subroutine that returns no value, the @code{call} expression as | |
4078 | shown above is the entire body of the insn, except that the insn might | |
4079 | also contain @code{use} or @code{clobber} expressions. | |
4080 | ||
4081 | @cindex @code{BLKmode}, and function return values | |
4082 | For a subroutine that returns a value whose mode is not @code{BLKmode}, | |
4083 | the value is returned in a hard register. If this register's number is | |
4084 | @var{r}, then the body of the call insn looks like this: | |
4085 | ||
a0ecd6b1 | 4086 | @smallexample |
5fc0eb84 | 4087 | (set (reg:@var{m} @var{r}) |
4088 | (call (mem:@var{fm} @var{addr}) @var{nbytes})) | |
a0ecd6b1 | 4089 | @end smallexample |
5fc0eb84 | 4090 | |
4091 | @noindent | |
4092 | This RTL expression makes it clear (to the optimizer passes) that the | |
4093 | appropriate register receives a useful value in this insn. | |
4094 | ||
4095 | When a subroutine returns a @code{BLKmode} value, it is handled by | |
4096 | passing to the subroutine the address of a place to store the value. | |
4097 | So the call insn itself does not ``return'' any value, and it has the | |
4098 | same RTL form as a call that returns nothing. | |
4099 | ||
4100 | On some machines, the call instruction itself clobbers some register, | |
4101 | for example to contain the return address. @code{call_insn} insns | |
4102 | on these machines should have a body which is a @code{parallel} | |
4103 | that contains both the @code{call} expression and @code{clobber} | |
4104 | expressions that indicate which registers are destroyed. Similarly, | |
4105 | if the call instruction requires some register other than the stack | |
837bbb8b | 4106 | pointer that is not explicitly mentioned in its RTL, a @code{use} |
5fc0eb84 | 4107 | subexpression should mention that register. |
4108 | ||
4109 | Functions that are called are assumed to modify all registers listed in | |
4110 | the configuration macro @code{CALL_USED_REGISTERS} (@pxref{Register | |
4111 | Basics}) and, with the exception of @code{const} functions and library | |
4112 | calls, to modify all of memory. | |
4113 | ||
4114 | Insns containing just @code{use} expressions directly precede the | |
4115 | @code{call_insn} insn to indicate which registers contain inputs to the | |
4116 | function. Similarly, if registers other than those in | |
4117 | @code{CALL_USED_REGISTERS} are clobbered by the called function, insns | |
4118 | containing a single @code{clobber} follow immediately after the call to | |
4119 | indicate which registers. | |
4120 | ||
4121 | @node Sharing | |
4122 | @section Structure Sharing Assumptions | |
4123 | @cindex sharing of RTL components | |
4124 | @cindex RTL structure sharing assumptions | |
4125 | ||
4126 | The compiler assumes that certain kinds of RTL expressions are unique; | |
4127 | there do not exist two distinct objects representing the same value. | |
4128 | In other cases, it makes an opposite assumption: that no RTL expression | |
4129 | object of a certain kind appears in more than one place in the | |
4130 | containing structure. | |
4131 | ||
4132 | These assumptions refer to a single function; except for the RTL | |
4133 | objects that describe global variables and external functions, | |
4134 | and a few standard objects such as small integer constants, | |
4135 | no RTL objects are common to two functions. | |
4136 | ||
4137 | @itemize @bullet | |
4138 | @cindex @code{reg}, RTL sharing | |
4139 | @item | |
4140 | Each pseudo-register has only a single @code{reg} object to represent it, | |
4141 | and therefore only a single machine mode. | |
4142 | ||
4143 | @cindex symbolic label | |
4144 | @cindex @code{symbol_ref}, RTL sharing | |
4145 | @item | |
4146 | For any symbolic label, there is only one @code{symbol_ref} object | |
4147 | referring to it. | |
4148 | ||
4149 | @cindex @code{const_int}, RTL sharing | |
4150 | @item | |
73f5c1e3 | 4151 | All @code{const_int} expressions with equal values are shared. |
5fc0eb84 | 4152 | |
4153 | @cindex @code{pc}, RTL sharing | |
4154 | @item | |
4155 | There is only one @code{pc} expression. | |
4156 | ||
4157 | @cindex @code{cc0}, RTL sharing | |
4158 | @item | |
4159 | There is only one @code{cc0} expression. | |
4160 | ||
4161 | @cindex @code{const_double}, RTL sharing | |
4162 | @item | |
4163 | There is only one @code{const_double} expression with value 0 for | |
4164 | each floating point mode. Likewise for values 1 and 2. | |
4165 | ||
886cfd4f | 4166 | @cindex @code{const_vector}, RTL sharing |
4167 | @item | |
4168 | There is only one @code{const_vector} expression with value 0 for | |
4169 | each vector mode, be it an integer or a double constant vector. | |
4170 | ||
5fc0eb84 | 4171 | @cindex @code{label_ref}, RTL sharing |
4172 | @cindex @code{scratch}, RTL sharing | |
4173 | @item | |
4174 | No @code{label_ref} or @code{scratch} appears in more than one place in | |
4175 | the RTL structure; in other words, it is safe to do a tree-walk of all | |
4176 | the insns in the function and assume that each time a @code{label_ref} | |
4177 | or @code{scratch} is seen it is distinct from all others that are seen. | |
4178 | ||
4179 | @cindex @code{mem}, RTL sharing | |
4180 | @item | |
4181 | Only one @code{mem} object is normally created for each static | |
4182 | variable or stack slot, so these objects are frequently shared in all | |
4183 | the places they appear. However, separate but equal objects for these | |
4184 | variables are occasionally made. | |
4185 | ||
4186 | @cindex @code{asm_operands}, RTL sharing | |
4187 | @item | |
4188 | When a single @code{asm} statement has multiple output operands, a | |
4189 | distinct @code{asm_operands} expression is made for each output operand. | |
4190 | However, these all share the vector which contains the sequence of input | |
4191 | operands. This sharing is used later on to test whether two | |
4192 | @code{asm_operands} expressions come from the same statement, so all | |
4193 | optimizations must carefully preserve the sharing if they copy the | |
4194 | vector at all. | |
4195 | ||
4196 | @item | |
4197 | No RTL object appears in more than one place in the RTL structure | |
4198 | except as described above. Many passes of the compiler rely on this | |
4199 | by assuming that they can modify RTL objects in place without unwanted | |
4200 | side-effects on other insns. | |
4201 | ||
4202 | @findex unshare_all_rtl | |
4203 | @item | |
4204 | During initial RTL generation, shared structure is freely introduced. | |
4205 | After all the RTL for a function has been generated, all shared | |
4206 | structure is copied by @code{unshare_all_rtl} in @file{emit-rtl.c}, | |
4207 | after which the above rules are guaranteed to be followed. | |
4208 | ||
4209 | @findex copy_rtx_if_shared | |
4210 | @item | |
4211 | During the combiner pass, shared structure within an insn can exist | |
4212 | temporarily. However, the shared structure is copied before the | |
4213 | combiner is finished with the insn. This is done by calling | |
4214 | @code{copy_rtx_if_shared}, which is a subroutine of | |
4215 | @code{unshare_all_rtl}. | |
4216 | @end itemize | |
4217 | ||
4218 | @node Reading RTL | |
4219 | @section Reading RTL | |
4220 | ||
4221 | To read an RTL object from a file, call @code{read_rtx}. It takes one | |
875d8740 | 4222 | argument, a stdio stream, and returns a single RTL object. This routine |
4223 | is defined in @file{read-rtl.c}. It is not available in the compiler | |
4224 | itself, only the various programs that generate the compiler back end | |
4225 | from the machine description. | |
5fc0eb84 | 4226 | |
4227 | People frequently have the idea of using RTL stored as text in a file as | |
0858e3a2 | 4228 | an interface between a language front end and the bulk of GCC@. This |
5fc0eb84 | 4229 | idea is not feasible. |
4230 | ||
37744367 | 4231 | GCC was designed to use RTL internally only. Correct RTL for a given |
5fc0eb84 | 4232 | program is very dependent on the particular target machine. And the RTL |
4233 | does not contain all the information about the program. | |
4234 | ||
37744367 | 4235 | The proper way to interface GCC to a new language front end is with |
e3f59894 | 4236 | the ``tree'' data structure, described in the files @file{tree.h} and |
84ccaae3 | 4237 | @file{tree.def}. The documentation for this structure (@pxref{GENERIC}) |
e3f59894 | 4238 | is incomplete. |